Compal LA 3071P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Compal LA-3071P - Schematics. Free.

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Page Count: 60

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Cover Sheet

159Friday, May 12, 2006

Compal Electronics, Inc.

COMPAL P/N :

PCB NO :

COMPAL CONFIDENTIAL

MODEL NAME :

HAU30

Crockett Schematics Document

uFCBGA Mobile Yonah-ULV

REV : 1.0 (DELL: A00)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

LA-3071P

PCB P/N: DA800004H1L

BOM NO. 43140131L01

DA800004H1L

Intel Calistoga-GMS + ICH7M

2006-5-12

Part Number Description

DA800004H1L PCB 00B LA-3071P REV1 M/B

MB PCB

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PS_ID_IN

PWR_ID

PQ_G

-DCIN_JACK

PS_ID

+DCIN_JACK

+DC_IN_SS

+5V_ALW

+DOCK_DC_IN

+3.3V_ALW

+5V_ALW +5V_ALW

+PWR_SRC +3.3V_RTC_LDO_1

PS_ID_IN <38>

PS_ID <40>

PS_ID_DISABLE# <40>

PS_ID_IN<38>

Title

Size Document Number Re v

Date: Sheet of

0.4

+DCIN

110Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DELL CONFIDENTIAL/PROPRIETARY

NOTE: "THE POINT LOCATED

AT PS MODULE

THE POINT

+DC_IN Source

PS_ID Detector

+3.3VX Source

PR4

100K_0402_1%~D

1 2

PD3

SM24_SOT23

@

2

3

1

PC2

0.01U_0402_25V7K~D

12

MIC5235-3.3BM5_SOT23-5~D

PU10

IN

1

GND

2

OUT 5

NC 4

EN

3

PR10

47K_0402_5%~D

12

PC142

2.2U_0603_6.3V6K~D

1

2

PD1

DA204U_SOT323~D

2

3

1

PC4

0.1U_0603_25V7K~D

12

PC1

0.47U_0805_25V7k

1 2

PC3

0.1U_0603_25V7K~D

12

PR6

100_0402_5%~D@

1 2

G

D

S

PQ1

FDV301N_SOT23

2

1 3

PR7

15K_0402_1%~D

1 2

PC143

1U_0805_25V4Z~D

12

PR1

2.2K_0402_5%~D

1 2

PR8

240K_0402_5%~D

12

PL1

BLM11B102S 0603~D

12

PD2

DA204U_SOT323~D

@

2

3

1

PR2

0_0402_5%~D@

1 2

PL2

FBM-L11-453215-900LMAT_1812~D

1 2

PC5

10U_1206_25V6M~D

12

PC6

0.01U_0402_25V7K~D

@

12

PL3

FBM-L11-453215-900LMAT_1812~D

1 2

PR9

4.7K_0603_5%~D

12

PQ3

SI4825DY_SO8~D

3 6

5

7

8

2

4

1

PJDCIN

FOX_JPD113E-LB103-7F

SINGAL 5

DC+_1 1

DC+_2 2

DC-_2 4

GND2

7

GND4

9

GND3

8

GND1

6

DC-_1 3

C

BE

PQ2

PMBT3904_SOT23~D

2

3 1

PR3

33_0402_5%~D

1 2

PR5

10K_0402_1%~D

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Block Diagram

259Friday, May 12, 2006

Compal Electronics, Inc.

Clock Generator

uFCBGA CPU

INTEL

DMI

H_D#(0..63)H_A#(3..31)

Compal confidential

Model : HAU30

AMP & INT.

Speaker

Pentium-M

Block Diagram

Azalia Codec

Power On/Off

SW & LED

System Bus

INTEL

Memory BUS

(DDR2)

FSB 400/533 MHz

+1.5V_RUN

100MHz

+1.8V_SUS 400/533MHz

48MHz

ATA100

MDC

998pin BGA

SLG84450VTR

STAC9200

Azalia I/F

Calistoga-GMS

ICH7-M

RJ11

HeadPhone &

MIC Jack

PATA HDD

+3.3V_HDD

+VDDA

+5V_SUS +3.3V_RUN

+1.8V_SUS

+1.5V_RUN

+1.05V_VCCP

+VCC_CORE

+1.05V_VCCP

+3.3V_RUN

BANK 2, 3

DDRII-DIMM X1

+0.9V_DDR_VTT

+1.8V_SUS

Cable

+3.3V_SUS

479pin

DC/DC Interface

CPU ITP Port

+FAN1_VOUT

Yonah-2M ULV

+3.3V_RUN

+2.5V_RUN

+3.3V_RUN

VCORE (IMVP-6)

1.5V/1.05V

CHARGER

1.8V/0.9V

BATT IN

DC IN

3V/5V/15V

GUARDIAN

EMC4000

Thermal

+3.3V_SUS

FAN

Power Sequence

DELL CONFIDENTIAL/PROPRIETARY

652pin BGA

pg 7,8

pg 18

pg 18

pg 6pg 7

pg 10,11,12,13,14

pg 22,23,24,25

pg 48

pg 26 pg 27

pg 34

pg 49

pg 50

pg 45

pg 46

pg 47pg 42,43

pg 44

pg 45

pg 28 pg 28

pg 15

+3.3V_ALW

pg 41

Int.KBD &

Stick

SMSC KBC

+3.3V_ALW

+RTC_CELL

MEC5004

pg 40

pg 41

SPI

LPC BUS

+3.3V_RUN

33MHz

SMSC SIO

+5V_RUN

+3.3V_ALW

Touch Pad

ECE5018

pg 39

USB[1]

USB Ports X1

+5V_SUS

pg 33

USB[6] REAR

HUB USB[1]

HUB USB[2]

pg 40

pg 37

FIR

DOCKING

BUFFER

pg 37

DOCKING PORT

pg 38 pg 31,32

PCI BUS

CardBus & 1394 & SD

R5C843 CSP208

+3.3V_RUN 33MHz

IDSEL:AD17

(PIRQB,C,D#,GNT2#,REQ2#)

+3.3V_RUN

+3.3V_SUS

HUB USB[2]USB[0]

Mini Card2

+3.3V_RUN

WLAN Mini Card 1

+3.3V_RUN

PCI Express BUS

+1.5V_RUN+1.5V_RUN

pg 29

GIGA Enthernet

+3.3V_LAN

+3.3V_RUN/ +1.5V_RUN 100MHz

pg 36

BCM5752

WWAN

pg 36

HUB USB[1]

USB[7]

Bluetooth

+3.3V_RUN

HUB USB[4]

Stick

INT MIC

+5V_SUS

+1.05V_VCCP

+3.3V_RUN

+3.3V_SUS

+1.5V_RUN

pg 34

SPI

+5V_RUN

+3.3V_RUN

pg 16,17

DDRII 512MB on Board

+0.9V_DDR_VTT

+1.8V_SUS

pg 19

LVDS

LVDS CONN

RGB

pg 20

DVO

DVI Bridge SI1362

CRT CONN

pg 21

TV

DVI

PWR USB X1

+5V_SUS

USB[5] REAR

SD card SLOT

1394 CONNCard Bus SLOT

IDSEL:AD24

(PIRQA#,GNT0#,REQ0#)

pg 30

RJ45

LAN SWITCH

PI3L500E

pg 30

Transformer

pg 30

+3.3V_LAN

+2.5V_LOM

pg 30

+3.3V_LAN+3.3V_LAN

SIM Card

pg 36

+SIM_PWR

+DOCK_PWR_SRC

+3.3V_RUN

+2.5V_LOM

pg 32

+SD_VCC

pg 31pg 32

+3.3V_RUN

+1.8V_RUN

+LCDVDD

+GFX_PWR_SRC

pg 33

DH_PORT_PWRSRC

USB Ports X1

+5V_SUS

pg 33

USB[4] REAR

ST M25P80

+2.5V_RUN

pg 18

Smart Card

+5V_RUN

pg 35

OZ77C6

HUB_USB[3]

SLOT

pg 51

pg 35

pg 41

Fingerprint

+3.3V_RUN

USB_BIO

+5V_RUN

+1.05V_VCCP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Z4304

+PBATT

Z4305

Z4306

Z4307

+VCHGR

+PBATT

+3.3V_ALW

+3.3V_ALW

PBAT_SMBDAT <40,51> PBAT_PRES# <39>

PBAT_ALARM# <39>

PBAT_SMBCLK <40,51>

Title

Size Document Number Rev

Date: Sheet of

0.4

Battery Conn

210Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DELL CONFIDENTIAL/PROPRIETARY

SUYIN_200028MR009G502ZL

TOP view

9

8

7

6

5

4

3

2

1

Battery Connector

ESD Diodes

PC8

2200P_0402_50V7K~D

12

PR11

10K_0402_1%~D

12

PJBAT1

SUYIN200277MR009G508ZR~D

BATT1+ 9

SMB_CLK 7

SMB_DAT 6

BATT_PRES# 5

SYSPRES# 4

BATT2- 1

GND

10

GND

11

BATT2+ 8

BATT_VOLT 3

BATT1- 2

PD5

DA204U_SOT323~D@

2

3

1

PD4

DA204U_SOT323~D@

2

3

1

PD6

DA204U_SOT323~D@

2

3

1

PR15

100_0402_5%~D

1 2

PD7

DA204U_SOT323~D@

2

3

1

PR12

100_0402_5%~D

1 2 PR14

100_0402_5%~D

1 2

PL4

FBM-L11-453215-900LMAT_1812~D

1 2

PC7

0.1U_0603_25V7K~D

12

PR13

100_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Index and Config.

359Friday, May 12, 2006

Compal Electronics, Inc.

PIRQ

B,C,D

+1.05V_VCCP

PM TABLE

ON

ON

AD17

OFF

PCI DEVICE

TABLE

CARD BUS

IDSEL

S0

TABLE

2

PCI

ON

ON

S3

USB

ON

OFF

ON

+3.3V_SUS

OFF

+5V_SUS+5V_ALW

S1

S5 S4/AC don't exist

+1.8V_RUN

+VCC_CORE

REQ#/GNT#

+5V_RUN

ON

power

plane

+3.3V_RUN

S5 S4/AC

ON

ON

+3.3V_ALW

State

OFFOFF

OFF

+1.5V_RUN

0

4,6

7

USB PORT# DESTINATION

PWR USB

1

USB Hub (5018)

Docking

Blue tooth

2

Tolerance

0.1U_0402_6.3VXX

Ceramic Capacitors :

Temperature Characteristics

Rated Voltage

Package Size

Value

CH

A

Capacitor Spec Guide:

1

SL

CODE

COG SJ

9

B

+-3%

CODE

Symbol F

+40,-20%

+-20%

4

G

+20,-10%

X

UK

5

B

Z

C

+-0.05PF

Y5V

Temperature Characteristics:

Y5P

CK

V

+-0.1PF

X5R

A

Z5U

BJ

+100,-0%

Y5U X7R

P

+-30%

C

SH

8

H

CJ

+30,-10%

K

+-5%

7

Q

+80,-20%

6

+-0.5PF +-1PF

Z5V

+-10%

J

+-0.25PF

Tolerance:

+-2%

N

D

Z5P

2

UJ

DEFG

HI J

30

Symbol

X6SNPO

K

X5S

M

Value

Package Size

Rated Voltage

Tolerance

Low ESR Mark : 45 m ohm

10U_D2_10VX_R45

Tantalum or Polymer Capacitors :

+0.9V_DDR_VTT

@XX : Depop component

NOTE1:

+1.8V_SUS

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

2

USB HUB DESTINATION

4

3

PC Card Bay

Mini 1(WWAN)

Mini 2(WLAN)

N/A

+2.5V_RUN

REAR

SMART CARD

5

DOCKING

AD24 0

A

USB HUB on

OZ77C6LN DESTINATION

DP_HUB

Fingerprint

+15V_SUS

3

N/A

+3.3V_SRC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TPS51120_VFB2

+5V_SUSP_L

TPS51120_VO1

TPS51120_VFB1

+3.3V_SRCP_L

+5V_SUSP

TPS51120_DRVL2

TPS51120_CS2

+15VS

TPS51120_DRVL1

+15VS_L

TPS51120_LL2

TPS51120_LL1

TPS51120_VO2 TPS51120_CS1

+3.3V_SRCP

TPS51120_DRVH1

TPS51120_DRVH2

TPS51120_SKIP#

+15VP

+3.3V_SRCP

+5V_SUSP

+15VP

+5V_SUS

+3.3V_SRC

+15V_SUS

+PWR_SRC

GNDA_DCDC1

+3.3V_RTC_LDO

+3.3V_SRCP

+3.3V_RTC_LDO

+3.3V_SRCP

+3.3V_SRCP

+VCC_TPS51120

+5V_ALW

+DC1_PWR_SRC

+VCC_TPS51120

GNDA_DCDC1

GNDA_DCDC1

GNDA_DCDC1

GNDA_DCDC1

+3.3V_ALW

+VCC_TPS51120

+5V_SUSP

GNDA_DCDC1

+VCC_TPS51120

GNDA_DCDC1

+VCC_TPS51120

+3.3V_RTC_LDO

+3.3V_ALW

+3.3V_RTC_LDO_1

THERM_STP#<18>

SUS_ON<40,42,43>

SUS_ON<40,42,43> SUSPWROK_5V <49>

AUX_EN<40,42>

ALWON<40>

RUN_ON<19,40,42,43,48,49>

RUN_ENABLE <42>

Title

Size Document Number R ev

Date: Sheet of

0.4

+3.3V/+5V/+15V

310Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DELL CONFIDENTIAL/PROPRIETARY

5 Volt +/- 5%

Design Current:3.63A

Maximum current: 5.191 A

OCP: 6.35A

DC/DC +3V/ +5V/ +15V

Place these CAPs

close to FETs

3.3 Volt +/- 5%

Design Current: 6.5 A

Maximum current: 9.1A

OCP: 10.95A

15 Volt

Maximum Current: 10mA

3.3V OCP

Fsw=440 KHZ

Rds_on_MAX=15m; Itrip_MIN=8.5uA;L=2.7uH

Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)

=3.3/2.7u * 1/440K *(1-3.3/19)=2.3A

Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*14.7K/15m=8.33A

Ivalley= Itrip*Rtrip/Rds_on=10u*14.7K/15m=9.8A

Iocp_MIN=8.33+2.3/2=9.48A

Iocp=9.8+2.3/2=10.95A

Place these CAPs

close to FETs

32 QFN 5X5

5V OCP

Fsw=290 KHZ

Rds_on_MAX=20m; Itrip_MIN=8.5uA;L=4.7uH

Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)

=5/4.7u * 1/290K *(1-5/19)=2.7A

Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*10K/20m=4.25A

Ivalley= Itrip*Rtrip/Rds_on=10u*10K/20m=5A

Iocp_MIN=4.25+2.7/2=5.6A

Iocp=5+2.7/2=6.35A

PC30

10U_0805_6.3V5K~D

12

PR41

200K_0402_1%~D

@

12

PC9

2.2U_1206_25V7M~D

12

PR157

100K_0402_1%~D

1 2

PJP5

PAD-OPEN 4x4m

@

1 2

PQ5

SI4800DY-T1_SO8~D

3 6

5

7

8

2

4

1

PQ6

SI4810BDY_SO8~D

3 6

5

7

8

2

4

1

PR136

0_0402_5%~D@

12

PJP2

PAD-OPEN 4x4m

@

1 2

PC33

4.7U_1206_10V7K~D

12

PR24

0_0402_5%~D

@

1 2

PJP12

PAD-OPEN 4x4m

@

1 2

PR159

2.2M_0402_5%~D

12

PC11

0.1U_0603_25V7K~D

12

PC17

10U_1206_25V6M~D

12

PR27

10K_0402_5%~D

12

PC14

0.1U_0603_25V7K~D

12

PD18

BAT54CW_SOT323~D

3

2

1

PR22

0_0402_5%~D

@

1 2

PR16

0_0805_5%~D

1 2

PC134

10U_1206_25V6M~D

@

12

PC26

0.1U_0603_25V7K~D

12

PJP4

PAD-OPEN 4x4m

@

1 2

PR34

0_0402_5%~D@

1 2

G

D

S

PQ9

SI2301BDS-T1-E3 _SOT23~D

2

13

PQ4

SI4800DY-T1_SO8~D

3 6

5

7

8

2

4

1

PC15

2200P_0402_50V7K~D

12

PC16

2.2U_1206_25V7M~D

12

PR38

0_0402_5%~D

12

G

D

S

PQ8

SI2301BDS-T1-E3 _SOT23~D@

2

13

PR138

0_0805_5%~D

@

1 2

G

D

S

PQ11

RHU002N06_SOT323

2

13

PC12

10U_1206_25V6M~D

12

PR29

0_0402_5%~D

1 2

PR40

4.7K_0402_5%~D

12

PL7

2.7U_SIL1055R-2R7PF_9A

1 2

PC10

2200P_0402_50V7K~D

12

PC20

0.1U_0603_25V7K~D

12

PC18

1U_0603_10V6K~D

12

PR32

0_0402_5%~D

@

1 2

PR137

10K_0805_5%~D

12

PC19

1U_0603_10V6K~D

12

PL5

FBM-L11-453215-900LMAT_1812~D

1 2

PR133

0_0603_5%~D

12

PC24

0.1U_0603_25V7K~D

12

PR30

10K_0402_5%~D

12

+

PC25

330U_D3L_6.3VM_R25~D

1

2

PR31

100K_0402_1%~D

1 2

PR162

0_0402_5%~D@

12

PC13

10U_1206_25V6M~D

12

PC29

1000P_0402_50V7K~D

12

PC22

0.1U_0603_25V7K~D

12

PQ7

FDS6690AS_NL_SO8~D

3 6

5

7

8

2

4

1

PR25

10K_0402_1%~D

1 2

G

D

S

PQ10

RHU002N06_SOT323 @

2

13

PR161

0_0805_5%~D

@

12

PR23

0_0402_5%~D

1 2

PR19

0_0402_5%~D

@

1 2

PC118

0.1U_0603_25V7K~D

12

PC120

10U_1206_25V6M~D

@

12

PD10

RB717F_SOT323~D

@

3

21

PD21

BAT54CW_SOT323~D

@

3

2

1

S

GD

PQ24

FDC655BN_NL_SSOT-6~D

3

6

245

1

PR135

0_0402_5%~D

1 2

PU7

SN74AHC1G32DCKR_SSOP5~D

I0

2

I1

1

O4

P

5G3

PR28

0_0402_5%~D

@

1 2

PC32

0.01U_0603_25V7K~D

12

PR20

0_0603_5%~D

1 2

PR21

0_0402_5%~D

@

1 2

PD9

EC11FS2_SOD106~D

2 1

PC31

1000P_0402_50V7K~D

@

12

PR39

0_0402_5%~D@

1 2

PR26

14.7K_0402_1%~D

1 2

PD8

MMBZ5245B_SOT23~D

1

2

3

PJP3

PAD-OPEN 4x4m

@

1 2

PR160

0_0402_5%~D

@

1 2

PR36

1K_0402_5%~D

12

PL6

4.7U_SDT-1204P-4R7D-122GP_20%

1 4

3 2

PR18

0_0603_5%~D

1 2

PR17

5.1_0603_5%~D

12

PC27

1000P_0402_50V7K~D

12

+

PC23

330U_D3L_6.3VM_R25~D

1

2

PC28

1000P_0402_50V7K~D

12

PR37

0_0402_5%~D @

1 2

PC21

0.1U_0603_25V7K~D

1 2

PR35

0_0402_5%~D @

1 2

PU1

TPS51120

VIN

22

V5FILT

20

EN5

9

VBST2

13

DRVH2

14

LL2

15

DRVL2

16

VO2

8

VFB2

6

EN2

12

EN1

29

VREG3

19

SKIPSEL

32

PGOOD2 11

PGOOD1 30

GND 5

PGND2

17

TONSEL 31

VREF2 4

CS2 18

CS1 23

VFB1 3

VO1 1

PGND1 24

DRVL1 25

LL1 26

DRVH1 27

VBST1 28

VREG5 21

EN3

10

PAD

33

COMP1 2

COMP2 7

C

BE

PQ25

2N2222_SOT23~D

2

31

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Power Rail

459Friday, May 12, 2006

Compal Electronics, Inc.

+5V_ALW

+5V_SUS

BATTERY

+PWR_SRC

+3.3V_SRC

+3.3V_ALW

+3.3V_RUN

ADAPTER

SUS_ON

RUN_ON

+5V_RUN VDDA

AUDIO_AVDD_ON

(Option)

+15V_SUS

+2.5V_RUN

TPS51120

EMC4000

RUN_ON

PL8

L47

793475

FDS4435 +GFX_PWR_SRC

RUN_ON

SI4800

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SI3456

ENAB_3VLAN

+3.3V_LAN

ALWON

ALWON

SI4800

SUS_ON

+VCC_CORE

RUNPWROK

+VCCP

SI3456

+1.5V_RUN

RUN_ON

SC483

+1.8V_SUS

RUN_ON

RUNPWROK

AD3207 SC480

+1.8V_RUN

RUNPWROK

SUSPWROK_5V

+0.9V_DDR_VTT

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

+DC2_PWR_SRC

+1.5V_RUN_P

+1.05V_VCCP_P

GNDA_DC2A

+1.05V_VCCP_P

+5V_SUS

GNDA_DC2A

+1.5V_RUN_P

GNDA_DC2B

GNDA_DC2A

GNDA_DC2B

+PWR_SRC

GNDA_DC2B

+3.3V_RUN

+1.05V_VCCP

+1.5V_RUN

+3.3V_RUN

1.05V_RUN_PWRGD <43>

1.5V_RUN_PWRGD<43>

RUN_ON<19,40,42,43,47,49>

Title

Size Document Number Rev

Date: Sheet of

0.4

+1.5VRUNP /+VCCP_1P05VP

410Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DELL CONFIDENTIAL/PROPRIETARY

Ref Des SC483 TPS52483

---------------------------------

PR56 30.0K 15.0K

PR58 15.0K 15.0K

PR55 16.5K 11.8K

PR57 15.0K 29.4K

1.05V +/- 5%

Thermal Design Current: 3.36A

Maximum Current:4.8A

MIN_OCP:5.2A

1.5V +/- 5%

Thermal Design Current: 2.5A

Maximum Current: 3.6A

MIN_OCP: 3.7A

Use PR56 and PR58 for

Voltage Margining.

BOM

Structure Description

-----------------------------------------------

@ Do Not Populate

4@ Populate for Semtech - SC483 Only

5@ Populate for Ti - TPS51483 Only

Use PR55 and P57 for

Voltage Margining.

Place these CAPs

close to FETs Place these CAPs

close to FETs

Create new P/N

PR52

12.7K_0402_1%

1 2

PR50

0_0603_5%~D

12

FDS6994S_SO8~D

PQ12

G2

2

D2 8

S1

3D1 5

S2

1D2 7

G1

4

D1 6

PD20

MMBD4148W-7-F_SOD323~D

1 2

PC53

1U_0603_10V6K~D@

12

PL9

3.3uH_PCMC063T-3R3MN_6A_20%

12

+

PC49

330U_D2E_2.5VM_R9

1

2

PC45

1U_0603_6.3V6M

1 2

PR46

10_0402_5%

1 2

PC48

0.1U_0603_25V7K~D

12

PR58

15K_0402_1%

12

PR43

1M_0402_5%~D

1 2

PC35

10U_1206_25V6M~D

12

PC40

10U_1206_25V6M~D

12

PC141

0.1U_0603_25V7K~D

@

1 2

SC483/TPS51483

PU2

SC1485ITSTR-TPS51483_TSSOP28

PGND1

1

DL1

2

VDDP1

3

ILIM1

4

LX1

5

DH1

6

BST1

7

EN/PSV2 8

TON2 9

VOUT2 10

VCCA2 11

FBK2 12

PGOOD2 13

AGND2 14

PGND2 15

DL2 16

VDDP2 17

ILIM2 18

LX2 19

DH2 20

BST2 21

EN/PSV1

22

TON1

23

VOUT1

24

VCCA1

25

FBK1

26

PGOOD1

27

AGND1

28

PR51

8.45K_0402_1%

1 2

PR44

750K_0402_1%~D

1 2

PL8

FBM-L11-453215-900LMAT_1812~D

1 2

PC47

0.1U_0603_25V7K~D

12

PC37

2200P_0402_50V7K~D

12

PR60

1K_0402_1%~D

12

PR53

10K_0402_1%~D 5@

1 2

PR62

1K_0402_1%~D

1 2

PJP7

PAD-OPEN 4x4m

@

1 2

FDS6994S_SO8~D

PQ13

G2 2

D2

8

S1 3

D1

5

S2 1

D2

7

G1 4

D1

6

PC44

1U_0603_6.3V6M

1 2

PR57

15K_0402_1%~D

12

PC43

1000P_0402_50V7K~D

12

PC50

1U_0603_10V6K~D@

12

PR48

499K_0402_1%

5@

1 2

PJP6

PAD-OPEN 4x4m

@

1 2

PC36

0.1U_0603_25V7K~D

12

PC54

82P_0402_50V8J

12

PR56

30K_0402_1%

12

PR49

0_0603_5%~D

12

PR140

100K_0402_1%~D

12

+

PC51

330U_D2E_2.5VM_R9

1

2

PC55

18P_0402_50V8J

12

PR139

0_0402_5%~D@

1 2

PR54

9.09K_0603_1%~D5@

1 2

PC38

2200P_0402_50V7K~D

12

PR61

100K_0402_1%~D

12

PC41

1U_0603_10V6K~D

12

PR55

16.5K_0402_1%

12

PD17

BAT54A-7-F_SOT23~L

32

1

PC46

1000P_0402_50V7K~D

12

PJP8

PAD-OPEN 4x4m

@

1 2

PR45

10_0402_5%

1 2

PR63

0_0603_5%~D

12

PC39

0.1U_0603_25V7K~D

12

PR64

0_0603_5%~D

12

PR47

453K_0402_1%~D5@

12

PC42

1U_0603_10V6K~D

12 PC34

1U_0603_10V6K~D

12

PL10

3.3uH_PCMC063T-3R3MN_6A_20%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

SMBUS TOPOLOGY

559Friday, May 12, 2006

Compal Electronics, Inc.

CLK GEN.

Macallan IV

ICH7-M

DAT_SMB +3.3V_ALW

CLK_SMB

GUARDIAN

ICH_SMBDATA

+3.3V_SUS

ICH_SMBCLK

SIO

PBAT_SMBCLK

PBAT_SMBDAT +3.3V_ALW BATTERY

CONN

CHARGER

DELL CONFIDENTIAL/PROPRIETARY

DIMM1

DDR II 512M

ON Board

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+3.3V_SUS

2N7002

2N7002

+3.3V_RUN

2.2K 2.2K 2.2K 2.2K

CLK_SCLK

CLK_SDATA

10K

SMBUS Address [A0]

SMBUS Address [A2]

195

197

B22

C22

17

16

5

6

7

8

SMBUS Address [D2]

SMBUS Address [2F]

+3.3V_ALW

8.2K8.2K

100

100

SMBUS Address [16]

SMBUS Address [12]

3

4

9

10

8

7

WWAN

SMBUS Address [TBD]

3032

WLAN

3032

SMBUS Address [TBD]

SBAT_SMBDAT

111

112

+3.3V_ALW

+3.3V_ALW

SMBUS Address [58]

5

6

SBAT_SMBCLK

Inverter

INV

8.2K 8.2K

10K 10K

SMBUS Address [C4, 72, 70, 48]

DOCK_SMB_CLK

+5V_ALW

10

+5V_ALW

DOCKING

9DOCK_SMB_DAT

39

40

5752M

LOM

C8C7

SMBUS Address [C8]

SMBUS Address [5A]

Power USB

DOG house

10K

+3.3V_ALW

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+PWR_SRC

+1.8V_SUSP

+0.9V_DDR_VTT

+0.9V_DDR_VTTP

+DDR_PWR_SRC

+DDR_PWR_SRC

+5V_SUS

+1.8V_SUSP

+5V_SUS

+0.9V_DDR_VTTP

+1.8V_SUSP

+1.8V_SUSP

+1.8V_SUSP

+5V_SUS

GNDA_DDR

+1.8V_SUSP

GNDA_DDR

GNDA_DDR

GNDA_DDR

GNDA_DDR

GNDA_DDR GNDA_DDR

GNDA_DDR

+1.8V_SUS

GNDA_DDR

RUN_ON <19,40,42,43,47,48>

SUSPWROK_5V <47>

SUSPWROK_1P8V <43>

V_DDR_MCH_REF<10,15,16,17>

Title

Size Document Number Re v

Date: Sheet of

LA-3071P

0.4

+1.8VSUSP/ +0.9V_DDR_VT

510Friday, May 12, 2006

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

TPS51116

20 QFN 4 X 4

<GMCH>

<5V_3V regulator>

<EC>

PAD

NOTE: Component Values Shown for SEMTECH SC480 ONLY.

For Texas Instruments TPS51116, Please USE Reference BOM.

NOTE: For Test purposes only

.9 Volt +/- 5%

Design Current:1.05A

Maximum current:1.5A

1.8 Volt +/- 5%

Design Current:3.5A

Maximum current:4.9A

MIN_OCP:5A

Place these CAPs

close to FETs

Create new P/N

<GMCH, DDR>

PC70

1U_0603_10V6K~D

12

PC71

1U_0603_10V6K~D

12

PL11

FBM-L11-453215-900LMAT_1812~D

1 2

PC73

0.1U_0402_10V7K~D

12

PC65

10U_0805_6.3V5K~D

@

1

2

PJP10

PAD-OPEN 4x4m

@

1 2

PR74

100_0402_5%~D

1 2

PR77

17.4K_0603_1%~D

@

12

PR70

100K_0402_1%~D

12

PD13

RB751V-40_SOD323~D

2 1

PR69

0_0402_5%~D

1 2

PC132

10U_1206_25V6M~D @

12

PC59

0.1U_0603_25V7K~D

12

PC57

0.1U_0603_25V7K~D

12

PR75

0_0402_5%~D

1 2

PC58

10U_1206_25V6M~D

12

PC62

0.1U_0402_10V7K~D

12

PC67

1U_0603_10V6K~D

@

12

FDS6994S_SO8~D

PQ14

G2 2

D2

8

S1 3

D1

5

S2 1

D2

7

G1 4

D1

6

PR73

0_0402_5%~D

@

12

PU3

SC480ITSTR_MLPQ24~D

PGND2

1

VTTS

2

VSSA

3

TON

4

REF

5

VCCA

6

NC

7

VTTEN

10

FB

9

LX 20

DL 19

PGND1 18

PGND1 17

ILIM 16

VDDP 15

VDDP 14

NC

12

EN/PSV

11

VDDQS

8

PGD 13

VTTIN 23

VTT 24

BST 22

DH 21

PAD 25

+

PC60

220U_D2_4VM~D

1

2

PC63

10U_0805_6.3V5K~D

1

2

PJP9

PAD-OPEN 4x4m

@

1 2

PR66

12.4K_0402_1%~D

12

PJP11

PAD-OPEN 43X79

@

1 2

PR67

1M_0402_5%~D

1 2

PC72

1U_0603_10V6K~D

12

PC69

1U_0603_10V6K~D

@

12

+

PC133

220U_D2_4VM~D

1

2

PR76

27.4K_0603_1%~D

@

12

PC66

1U_0603_10V6K~D

12

PC64

10U_0805_6.3V5K~D

1

2

PL12

3.3uH_PCMC063T-3R3MN_6A_20%

12

PC68

1000P_0402_50V7K~D

1 2

PR72

10_0402_1%~D

1 2

PR71

10_0402_1%~D

1 2

PR65

0_0603_5%~D

12

PC119

18P_0402_50V8J

@

12

PR68

10K_0402_1%~D

@

12

PC56

2200P_0402_50V7K~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_ITP#

CLK_CPU_ITP

CLK_CPU_ITP#

CPU_ITP

H_STP_CPU#

H_STP_PCI#

CLK_MCH_BCLK#MCH_BCLK#

CPU_BCLK

CLK_CPU_BCLK#CPU_BCLK#

CLK_CPU_BCLK

+CK_VDD_A

+CK_VDD_MAIN

CLK_XTAL_IN

FSA

CLK_CPU_BCLK#

CLK_CPU_BCLK

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CPU_ITP#

CLK_CPU_ITP

CLK_PCIE_LOM#

CLK_PCIE_LOM

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICH#

CLK_PCIE_ICH

ICH_SMBDATA

ICH_SMBCLK

CLK_SDATA

CLK_SCLK

FSC

CLK_ICH_48M FSA

CLK14M_REFCLK_ICH_14M

CLK_SIO_14M

CLK_ENABLE#

CLKIREF

CLK_SDATA

CLK_SCLK

FCTSEL1

FCTSEL1

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

CLK_MCH_BCLKMCH_BCLK

PCIE_MINI2

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

PCIE_MINI2#

CLK_PCI_SIO

CLK_PCI_ICH PCI_ICH

CLK_SMCARD_48M

CLK_PCI_5004

PCIE_ICH

PCIE_ICH#

CLK_PCIE_ICH

CLK_PCIE_ICH#

PCIE_MINI1

PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

+CK_VDD_REF

+CK_VDD_48

+CK_VDD_48+CK_VDD_A +CK_VDD_REF

CLK_XTAL_OUT

MCH_DREFCLK# DOT96#

DOT96MCH_DREFCLK

DOT96_SSC

DOT96_SSC#

DREF_SSCLK#

DREF_SSCLK

MCH_DREFCLK#

MCH_DREFCLK

CLK_PCIE_LOMPCIE_LOM

CLK_PCIE_LOM#PCIE_LOM#

MCH_3GPLL CLK_MCH_3GPLL

CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCI_LOM PCI_LOM

CLK_PCI_PCCARD PCI_PCCARD

PCI_DOCKCLK_PCI_DOCK

CLK_SD_48M

+CK_VDD_MAIN

+CK_VDD_MAIN2

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN +3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

H_STP_CPU# <24>

H_STP_PCI# <24>

CLK_MCH_BCLK# <10>

CLK_MCH_BCLK <10>

CLK_CPU_BCLK# <7>

CLK_CPU_BCLK <7>

CLK_CPU_ITP <7>

CLK_CPU_ITP# <7>

CLK_ICH_14M<24> CLK_SIO_14M<39>

CLK_PCIE_MINI2 <36>

CLK_PCIE_MINI2# <36>

CLK_PCI_SIO<39>

CLK_PCI_ICH<22>

CLK_SMCARD_48M<35>

CLK_PCI_5004<40>

CLK_ICH_48M<24>

CLK_PCIE_ICH# <24>

CLK_PCIE_ICH <24>

CLK_PCIE_MINI1 <36>

CLK_PCIE_MINI1# <36>

MINI2CLK_REQ# <36>

MINI1CLK_REQ# <36>

MCH_DREFCLK<10>

MCH_DREFCLK#<10>

CPU_MCH_BSEL1<8,10> CPU_MCH_BSEL2<8,10>

CLK_PCIE_LOM <29>

CLK_PCIE_LOM# <29>

CLK_MCH_3GPLL <12>

CLK_MCH_3GPLL# <12>

CLK_3GPLLREQ# <10>

CLK_PCI_LOM<29>

CLK_PCI_PCCARD<31>

CLK_PCI_DOCK<38>

LOM_CLKREQ# <29>

CLK_SD_48M<31>

ICH_SMBDATA<24,29,36> CLK_SDATA <15,17>

CPU_MCH_BSEL0<8,10>

CLK_ENABLE#<50>

DREF_SSCLK <10>

DREF_SSCLK# <10>

ICH_SMBCLK<24,29,36> CLK_SCLK <15,17>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Clock Generator

659Friday, May 12, 2006

Compal Electronics, Inc.

Place crystal within

500 mils of CK410

3

1

G S

2N7002

2

D

1

*

CLKSEL2 CLKSEL0CLKSEL1

FSC FSB FSA CPU

MHz

SRC

MHz

PCI

MHz

266

133

200

166

333

100

400

100

100

100

100

100

100

100

33.3

33.3

33.3

33.3

33.3

33.3

33.3

000

00

0

0

0

00

0

0

1

1

11

1

1

1

11

1

1

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

0

0

0

1

Place near each pin

W>40 mil

Place near CK410+

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Reserve

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0

1

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

60ohm,500mA,0.1ohm

60ohm,500mA,0.1ohm

R19 49.9_0402_1%~D

1 2

R15 2.2_0603_5%~D

1 2 R16 49.9_0402_1%~D

1 2

R34 39_0402_5%~D

1 2

R66 10K_0402_5%~D

1 2

R62 33_0402_5%~D

1 2

R41 15_0402_5%~D

1 2

X1

14.31818MHz_20P_1BX14318CC1A~D

12

C15

27P_0402_50V8J~D

12

R30 0_0402_5%~D

1 2

R39 56_0402_5%~D

1 2

R29 33_0402_5%~D

1 2

R18 49.9_0402_1%~D

1 2

R67

10K_0402_5%~D

@

1 2

C11

0.047U_0402_16V7K~D

1

2

R48 56_0402_5%~D

1 2

C8

0.1U_0402_16V4Z~D

1

2

R61 33_0402_5%~D

1 2

R561 8.2K_0402_5%~D@12

R51 475_0402_1%~D

1 2

R24 33_0402_5%~D

1 2

R1 49.9_0402_1%~D

12

R14 49.9_0402_1%~D 1 2

R43 33_0402_5%~D

1 2

R50 33_0402_5%~D

1 2

R21 49.9_0402_1%~D

1 2

C5

0.1U_0402_16V4Z~D

1

2

R605 39_0402_5%~D

12

R55 10K_0402_5%~D

1 2

R26 33_0402_5%~D

1 2

R44 33_0402_5%~D

1 2

C643

0.1U_0402_16V4Z~D

1

2

R12 49.9_0402_1%~D

1 2

R49 33_0402_5%~D

1 2

R71

10K_0402_5%~D

12

R54 33_0402_5%~D

1 2

R20 49.9_0402_1%~D

1 2

R63 10K_0402_5%~D

1 2

R38 56_0402_5%~D

1 2

C16

27P_0402_50V8J~D

12

U1

SLG84450VTR_QFN72~D

VDDSRC

1

VDDSRC

49

VDDSRC

65

VDDPCI

30

VDDPCI

36

VDD48

40

VDDCPU

12

VDDREF

18

USB_48MHz/FSLA

41

FSLB/TEST_MODE

45

X2

19

X1

20

GNDPCI

31

PCICLK2

32

REF0/FSLC/TEST_SEL

23

SMBDAT

17

SMBCLK

16

ITP_EN/PCICLK_F0

37

IREF

9

CPU_STOP# 24

CPUT1 11

CPUC1 10

CPUT_ITP/SRCT10 6

PCICLK3

33

PCICLK4/FCTSEL1

34

CPUC0 13

CPUT0 14

PCI_SRC_STOP# 25

GNDA 8

VDDA 7

GNDPCI

35

CPUC_ITP/SRCC10 5

GNDREF

21

GNDCPU

15

GNDSRC

4

GND48

42

GNDSRC

68

DOTT_96MHz/27MHz

43

DOTC_96MHz/27MHz(SS)

44

Vtt_PwrGd#/PD

39

REF1

22 SRCT7 66

SRCC7 67

SRCT8 70

SRCC8 69

SRCT9 3

SRCC9 2

SRCC1 51

LCD100/96/SRC0_T 47

SRCT2 52

SRCT4 58

SRCT1 50

CLKREQ4# 57

SRCC2 53

SRCC5 61

SRCC4 59

SRCT5 60

LCD100/96/SRC0_C 48

SRCC3 56

SRCT3 55

SRCT6 63

SRCC6 64

CLKREQ6# 62

CLKREQ8# 71

CLKREQ9# 72

CLKREQ1# 46

CLKREQ5# 29

CLKREQ3# 28

CLKREQ2# 26

CLKREQ7# 38

VDDSRC

54

PCICLK1

27

THRM_PAD

73

THRM_PAD

76

THRM_PAD

74

THRM_PAD

75

R56 8.2K_0402_5%~D

12

R11 49.9_0402_1%~D

1 2

R46 10K_0402_5%~D

1 2

R28 33_0402_5%~D

1 2

C3

0.1U_0402_16V4Z~D

1

2

R70 33_0402_5%~D 1 2

C1

10U_0805_10V4Z~D

1

2

R69

10K_0402_5%~D

1 2

L2

BLM18PG600SN1_0603~D

1 2

R68 33_0402_5%~D 1 2

R31 33_0402_5%~D

1 2

R22 49.9_0402_1%~D 1 2

R3 49.9_0402_1%~D

12

R32 39_0402_5%~D

12

R4

2.2K_0402_5%~D

12

C4

0.1U_0402_16V4Z~D

1

2

R45 33_0402_5%~D

1 2

C6

0.1U_0402_16V4Z~D

1

2

R25 1_0603_5%~D

1 2

R36 39_0402_5%~D

12

R37 56_0402_5%~D

1 2

R5

2.2K_0402_5%~D

12

R33 33_0402_5%~D

1 2

C14

0.047U_0402_16V7K~D

1

2

R7 49.9_0402_1%~D

12

R17 49.9_0402_1%~D

1 2

C10

4.7U_0603_6.3V6M~D

1

2

G

D

S

Q2

2N7002W-7-F_SOT323~D

2

1 3

C9

0.1U_0402_16V4Z~D

1

2

R72

10K_0402_5%~D

@

12

G

D

S

Q1

2N7002W-7-F_SOT323~D

2

1 3

R65 33_0402_5%~D

1 2

R40 15_0402_5%~D

1 2

R35 39_0402_5%~D

12

R27 2.2_0603_5%~D

1 2

R23 49.9_0402_1%~D 1 2

C2

0.1U_0402_16V4Z~D

1

2R6 49.9_0402_1%~D

12

R13 49.9_0402_1%~D 1 2

R53 33_0402_5%~D

1 2

L1

BLM18PG600SN1_0603~D

1 2

R42 33_0402_5%~D

1 2

R9 49.9_0402_1%~D

1 2

R10 49.9_0402_1%~D

1 2

C12

4.7U_0603_6.3V6M~D

1

2

R8 49.9_0402_1%~D

12

R52 10K_0402_5%~D

1 2

C7

10U_0805_10V4Z~D

1

2

R64 33_0402_5%~D

1 2

R47 10K_0402_5%~D

1 2

C13

0.047U_0402_16V7K~D

1

2

R2 49.9_0402_1%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_FERR#

H_ADSTB#0

H_D#52

H_D#20

H_REQ#2

H_D#10

H_D#5

H_D#49

H_D#3

H_REQ#0

H_D#39

H_D#57

H_D#29

H_IGNNE#

H_D#34

H_D#14

H_BNR#

H_DSTBP#0

H_D#51

H_D#22

H_DEFER#

H_INIT#

H_REQ#1

H_D#50

H_D#48

H_D#0

H_RS#0

H_DSTBN#1

H_D#58

H_D#28

ITP_BPM#2

H_BPRI#

H_ADS#

ITP_BPM#3

H_RS#1

H_DSTBP#1

H_D#46

H_D#41

H_D#12

H_IERR#

H_HITM#

H_DSTBN#0

H_D#47

H_D#37

H_INTR

H_DSTBN#2

H_D#9

H_D#7

H_REQ#4

H_D#31

H_D#13

ITP_DBRESET#

H_DRDY#

H_A20M#

H_D#27

H_D#25

H_D#4

H_DSTBP#2

H_D#56

H_D#35

H_D#59

H_D#63

H_D#45

H_D#24

H_D#30

H_D#55

H_D#40

H_D#19

H_D#62

H_D#44

H_D#23

H_D#2

H_D#8

H_D#6

H_D#54

H_D#33

H_D#18

H_D#16

H_D#61

H_D#43

H_D#1

H_D#26

H_DSTBN#3

H_D#53

H_D#32

H_D#11

H_DSTBP#3

H_D#38

H_D#36

H_D#17

H_D#15

H_NMI

H_D#60

H_D#42

H_D#21

H_BR0#

H_LOCK#

H_DPSLP#

H_HIT#

H_ADSTB#1

H_THERMTRIP#

H_DBSY#

H_RS#2

H_RESET#

ITP_BPM#1

H_REQ#3

H_SMI#

H_STPCLK#

ITP_TCK

ITP_TRST#

TEST1

TEST2

ITP_TMS

H_CPUSLP#

ITP_TDO

ITP_TDI

ITP_BPM#5

H_DPWR#

ITP_BPM#4

CPU_PROCHOT#

H_THERMTRIP#

H_TRDY#

CLK_CPU_BCLK

CLK_CPU_BCLK#

ITP_BPM#0

ITP_TDO

ITP_TDO

ITP_TDI

ITP_TRST#

ITP_TCK

ITP_DBRESET#

H_RESET#

H_RESET#

H_THERMDA

H_THERMDC

TEST2

H_DPRSTP#

ITP_BPM#5

ITP_TMS

ITP_TCK

ITP_TCK

ITP_DBRESET#

ITP_BPM#0

CLK_CPU_ITP#

CLK_CPU_ITP

ITP_TRST#

ITP_TMS

ITP_TDI

ITP_BPM#5

ITP_BPM#4

ITP_BPM#2

ITP_BPM#3

ITP_BPM#1

CPU_PROCHOT#TEST1

H_A#26

H_A#14

H_A#24

H_A#16

H_A#11

H_A#18

H_A#3

H_A#8

H_A#27

H_A#30

H_A#20

H_A#12

H_A#28

H_A#22

H_A#7

H_A#13

H_A#17

H_A#6

H_A#5

H_A#10

H_A#15

H_A#31

H_A#9

H_A#19

H_A#25

H_A#21

H_A#23

H_A#4

H_A#29

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_THERMTRIP#<18>

H_THERMDA<18>

H_THERMDC<18>

H_ADS#<10>

H_REQ#[0..4]<10>

H_BPRI#<10> H_BNR#<10>

H_HITM#<10>

H_BR0#<10>

H_HIT#<10>

H_D#[0..63] <10>

H_DPSLP#<23>

H_RESET#<10>

H_DRDY#<10>

H_ADSTB#0<10>

H_DSTBP#[0..3] <10>

H_ADSTB#1<10>

H_DSTBN#[0..3] <10>

H_DINV#0 <10>

H_DINV#2 <10>

H_DBSY#<10>

H_DINV#1 <10>

H_IGNNE# <23>

H_INTR <23>

H_NMI <23>

H_DINV#3 <10>

H_INIT# <23>

ITP_DBRESET#<24,40>

H_A20M# <23>

H_STPCLK# <23>

H_SMI# <23>

H_CPUSLP#<10,23>

H_DPWR#<10>

H_DPRSTP#<23,50>

H_TRDY#<10>

CLK_CPU_BCLK<6> CLK_CPU_BCLK#<6>

CLK_CPU_ITP#<6> CLK_CPU_ITP<6>

H_DEFER#<10>

H_LOCK#<10>

H_RS#[0..2]<10>

CPU_PROCHOT#<39>

H_PWRGOOD<23>

H_FERR# <23>

H_A#[3..31]<10>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Yonah-ULV in mFCPGA479

759Friday, May 12, 2006

Compal Electronics, Inc.

H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

This shall place near CPU

For Yonah B0

C17

0.1U_0402_16V4Z~D

1

2

R579 1K_0402_5%~D@1 2

R84 51_0402_5%~D

1 2

R78 150_0402_1%~D

1 2

J2

MOLEX_52435-2891_28P~D@

TDI

1TMS

2TRST#

3NC1

4TCK

5NC2

6TDO

7BCLKN

8BCLKP

9GND0

10 FBO

11 RESET#

12 BPM5#

13

BPM4#

15

BPM3#

17

BPM2#

19

BPM1#

21

BPM0#

23 DBA#

24 DBR#

25 VTAP

26 VTT0

27 VTT1

28

GND1

14

GND2

16

GND3

18

GND4

20

GND5

22

GND7

30

C18

2200P_0402_50V7K~D

@

1

2

R80 22.6_0402_1%~D

1 2 R81 27.4_0402_1%~D

1 2

R82

56_0402_5%~D

1 2

R76 39_0402_5%~D

1 2

R73 150_0402_1%~D

1 2

C633

0.1U_0402_16V4Z~D

1

2

R575 54.9_0402_1%~D@1 2

R468 75_0402_5%~D

1 2

ADDR GROUP

CONTROL

HOST CLK

MISC

DATA GROUP

THERMAL

DIODE

LEGACY CPU

YONAH-ULV

U2A

Yonah-ULV_1.06G SC_UFCBGA479~D1@

A3#

J4

A4#

L4

A5#

M3

A6#

K5

A7#

M1

A8#

N2

A9#

J1

A10#

N3

A11#

P5

A12#

P2

A13#

L1

A14#

P4

A15#

P1

A16#

R1

A17#

Y2

A18#

U5

A19#

R3

A20#

W6

A21#

U4

A22#

Y5

A23#

U2

A24#

R4

A25#

T5

A26#

T3

A27#

W3

A28#

W5

A29#

Y4

A30#

W2

A31#

Y1

REQ0#

K3

REQ1#

H2

REQ2#

K2

REQ3#

J3

REQ4#

L5

ADSTB0#

L2

ADSTB1#

V4

BCLK0

A22

BCLK1

A21

ADS#

H1

BNR#

E2

BPRI#

G5

BR0#

F1

DEFER#

H5

DRDY#

F21

HIT#

G6

HITM#

E4

IERR#

D20

LOCK#

H4

RESET#

B1

RS0#

F3

RS1#

F4

RS2#

G3

TRDY#

G2

BPM0#

AD4

BPM1#

AD3

BPM2#

AD1

BPM3#

AC4

DBR#

C20

DBSY#

E1

DPSLP#

B5

DPWR#

D24

PRDY#

AC2

PREQ#

AC1

PROCHOT#

D21

PWRGOOD

D6

SLP#

D7

TCK

AC5

TDI

AA6

TDO

AB3

TEST1

C26

TEST2

D25

TMS

AB5

TRST#

AB6

THERMDA

A24

THERMDC

A25

THERMTRIP#

C7

D0# E22

D1# F24

D2# E26

D3# H22

D4# F23

D5# G25

D6# E25

D7# E23

D8# K24

D9# G24

D10# J24

D11# J23

D12# H26

D13# F26

D14# K22

D15# H25

D16# N22

D17# K25

D18# P26

D19# R23

D20# L25

D21# L22

D22# L23

D23# M23

D24# P25

D25# P22

D26# P23

D27# T24

D28# R24

D29# L26

D30# T25

D31# N24

D32# AA23

D33# AB24

D34# V24

D35# V26

D36# W25

D37# U23

D38# U25

D39# U22

D40# AB25

D41# W22

D42# Y23

D43# AA26

D44# Y26

D45# Y22

D46# AC26

D47# AA24

D48# AC22

D49# AC23

D50# AB22

D51# AA21

D52# AB21

D53# AC25

D54# AD20

D55# AE22

D56# AF23

D57# AD24

D58# AE21

D59# AD21

D60# AE25

D61# AF25

D62# AF22

D63# AF26

DINV0# J26

DINV1# M26

DINV2# V23

DINV3# AC20

DSTBN0# H23

DSTBN1# M24

DSTBN2# W24

DSTBN3# AD23

DSTBP0# G22

DSTBP1# N25

DSTBP2# Y25

DSTBP3# AE24

A20M# A6

FERR# A5

IGNNE# C4

INIT# B3

LINT0 C6

LINT1 B4

STPCLK# D5

SMI# A3

DPRSTP#

E5

R74 51_0402_5%~D

1 2

R77

22.6_0402_1%~D

1 2

R79 680_0402_5%~D

1 2

R83 56_0402_5%~D

1 2

R75 54.9_0402_1%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX8731_CSSP

MAX8731_DHI

ACAV_IN

ACAV_IN

MAX8731_DAC

MAX8731_CSIN

GNDA_CHGR

MAX8731_CCI

MAX8731_CCS

MAX8731_CSIP

MAX8731_LDO

MAX8731_LDO

MAX8731_REF

MAX8731_ACOK

MAX8731_VCC

N657586

MAX8731_ACIN

MAX8731_LX

MAX8731_BSTB

MAX8731_CSSN

MAX8731_CCV

MAX8731_REF

+VCHGR_L

MAX8731_IINP

MAX8731_IINP

GND

MAX8731_DLO

+CHRG_IN

+VCHGR

+DC_IN_SS

+VCHGR

GNDA_CHGR

+VCHGR

GNDA_CHGR

+PWR_SRC

GNDA_CHGR

+DC_IN_SS

GNDA_CHGR

GNDA_CHGR

+5V_ALW

+5V_ALW +3.3V_ALW

+5V_ALW

+5V_ALW

GNDA_CHGR

+5V_ALW

GNDA_CHGR

GNDA_CHGR

GNDA_CHGR

PBAT_SMBCLK<40,46>

ACAV_IN<18,40>

PBAT_SMBDAT<40,46>

ADAPT_OC <39>

ADAPT_TRIP_SEL<39>

Title

Size Document Number Rev

Date: Sheet of

0.4

Charger

710Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DELL CONFIDENTIAL/PROPRIETARY

Smart Charger

Place these CAPs

close to FETs

+DC_IN discharge path

Maximum Battery Charge current = 3.15A

when system off, S3, S4.

Need double confirm

Need modify

DELL CONFIDENTIAL/PROPRIETARY

Battery Type:

4cell: Charging Voltage=17.325V;Charging Current =1.6A

6cell: Charging Voltage=12.975V;Charging Current =3.15A

9cell:Charging Voltage=12.975V;Charging Current =3.15A

ADAPTER(W)TRIP CURRENT

(A) PR142 PR145 PR148 PR154

65

90

130

150

3.17

4.43

6.44

7.44

4.32M 301K 56.2K 27.4K NA

976K 49.9K 13.3K 9.31K 38.3K

33.2K

66.1K

15K

10K

33.2K

20K649K

976K 13.3K

13K

Table1

PR147

G

D

S

PQ26

RHU002N06_SOT323

2

13

PR158

1K_0603_1%~D

1 2

PR119

10K_0402_1%~D

12

PC98

1U_0805_25V4Z~D

12

PC116

0.01U_0402_25V7K~D

12

PR125

0_0603_5%~D

1 2

PC129

0.01U_0402_25V8K

12

PQ23

SI4810BDY_SO8~D

3 6

5

7

8

2

4

1

PR144

100K_0402_1%~D

12

PC140

0.01U_0402_50V7K~D

@

12

PR117

10K_0402_1%~D

12

PC111

220P_0603_50V8J~D

1 2

PR155

100_0402_5%~D

1 2

PC105

0.1U_0603_25V7K~D

12

PR128

1_0603_5%~D

1 2

PC113

0.01U_0402_25V7K~D

12

PC103

10U_1206_25V6M~D

12

PC122

0.1U_0603_25V7M~D

12

PC104

0.01U_0402_25V7K~D

12

PC97

10U_1206_25V6M~D

12

PR142

4.32M_0402_1%

1 2

PC99

1U_0603_10V6K~D

1 2

PR131

0_0603_5%~D

12

PC100

2200P_0402_50V7K~D

12

PU9A

LM393DR_SO8~D

IN+

3

IN-

2

O1

P

8G4

PR123

10K_0402_1%~D

1 2

PL15

FBM-L11-453215-900LMAT_1812~D

1 2

PC114

1U_0603_10V6K~D

12

PU6

MAX8731_TQFN28~D

DHI 24

CSIP 18

LX 23

FBSA 15

SDA

9

IINP

8

GND 1

DCIN

22

ACIN

2

VDD

11

SCL

10

ACOK

13

BATSEL

14

BST 25

FBSB 16

CCS

4

LDO 21

VCC 26

CSSP 28

CSIN 17

PGND 19

DLO 20

CCV

6

CCI

5

CSSN 27

REF

3

DAC

7

GND

12

PR120

100K_0402_1%~D

12

PL16

5.6U_HMU1356-5R6_8.8A_20%~D

2 1

PR127

33_0603_1%~D

1 2

PC108

0.1U_0805_50V7M~D

12

PC115

0.1U_0402_10V7K~D

12

PR149

100K_0402_1%~D

＠

1 2

PC110

10U_1206_25V6M~D

12

PR146

0_0402_5%

1 2

PC130

100P_0402_50V8J

12

PR130

4.7K_0402_5%~D

12

PR121

365K_0402_1%~D

1 2

G

D

S

PQ21

RHU002N06_SOT323

2

13

1SS355_SOD323~D

PD19

21

PR145

301K_0402_1%~D

12 PC112

0.01U_0402_25V7K~D

12

PQ22

IRF7821_SO8~D

3 6

5

7

8

2

4

1

PC101

0.1U_0603_25V7M~D

12

PC126

0.01U_0402_25V8K

12

PC139

0.01U_0402_50V7K~D

@

12

PC117

0.1U_0402_10V7K~D

12

PC102

10U_1206_25V6M~D

12

PC107

1U_0603_10V6K~D

1 2

PR116

0.01_2512_1%~D

4

2

1

3

PC106

0.1U_0402_10V7K~D

12

PR118

470K_0402_5%~D

12

G

D

S

PQ20

RHU002N06_SOT323

2

13

PD15

RB751V-40_SOD323~D

2 1

PR124

49.9K_0402_1%~D

12

PU9B

LM393DR_SO8~D

IN+

5

IN-

6O7

P8

G

4

PR147

56.2K_0402_1%

12

PQ18

SI4835BDY_SO8~D

3 6

5

7

8

2

4

1

PR126

0_0402_5%~D

1 2

PC109

10U_1206_25V6M~D

12

PC121

2200P_0402_50V7K~D

12

PR143

100K_0402_1%~D

12

PR132

10K_0402_1%~D

12

PC135

0.01U_0603_25V7M~D

@

12

PC128

100P_0402_50V8J

12

PR122

15.8K_0402_1%~D

12

PC138

3300P_0402_50V7K~D

1 2

PC125

10P_0402_50V8J~D

<BOM Structure>

12

PR129

0.01_2512_1%~D

4

2

1

3

PR148

27.4K_0402_1%

12

PC127

100P_0402_50V8J

12

PC131

0.01U_0402_25V8K

12

PR154

154K_0402_1%@

12

PQ19

SI4835BDY_SO8~D

36

5

7

82

4

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSSENSE

VCCSENSE

VSSSENSE

COMP0

VID3

VID6

VID5

VID2

VID4

VID1

VCCSENSE

COMP1

H_PSI#

COMP2

VID0

COMP3

+1.05V_VCCP

+VCC_CORE

+1.05V_VCCP

V_CPU_GTLREF

V_CPU_GTLREF

+1.5V_RUN

+VCC_CORE

+VCC_CORE

H_PSI#<50>

VID0<50> VID1<50> VID2<50> VID3<50> VID4<50> VID5<50> VID6<50>

VCCSENSE<50> VSSSENSE<50>

CPU_MCH_BSEL0<6,10> CPU_MCH_BSEL1<6,10> CPU_MCH_BSEL2<6,10>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Yonah-ULV in mFCBGA479

859Friday, May 12, 2006

Compal Electronics, Inc.

Resistor placed within

0.5" of CPU pin.Trace

should be at least 25

mils away from any

other toggling signal.

R_B

R_A

Layout close CPU PIN AD26

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.5 inch (max)

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

01

CPU_BSEL0

1

1

Length match within 25 mils

Layout close CPU

VCCSENSE/VSSSENSE

trace width 18mil,

space 7mil, for

other signal 15mil

Close to U2.B26

POWER, GROUND

YONAH-ULV

U2C

Yonah-ULV_1.06G SC_UFCBGA479~D1@

VCC

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VSS K1

VSS J2

VSS M2

VSS N1

VSS T1

VSS R2

VSS V2

VSS W1

VSS A26

VSS D26

VSS C25

VSS F25

VSS B24

VSS A23

VSS D23

VSS E24

VSS B21

VSS C22

VSS F22

VSS E21

VSS B19

VSS A19

VSS D19

VSS C19

VSS F19

VSS E19

VSS B16

VSS A16

VSS D16

VSS C16

VSS F16

VSS E16

VSS B13

VSS A14

VSS D13

VSS C14

VSS F13

VSS E14

VSS B11

VSS A11

VSS D11

VSS C11

VSS F11

VSS E11

VSS B8

VSS A8

VSS D8

VSS C8

VSS F8

VSS E8

VSS G26

VSS K26

VSS J25

VSS M25

VSS N26

VSS T26

VSS R25

VSS V25

VSS W26

VSS H24

VSS G23

VSS K23

VSS L24

VSS P24

VSS N23

VSS T23

VSS U24

VSS Y24

VSS W23

VSS H21

VSS J22

VSS M22

VSS L21

VSS P21

VSS R22

VSS V22

VSS U21

VSS Y21

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

F7 VCC

A7

R94

54.9_0402_1%~D

12

R88 100_0402_1%~D

1 2

POWER, GROUNG, RESERVED SIGNALS AND NC

YONAH-ULV

U2B

Yonah-ULV_1.06G SC_UFCBGA479~D1@

PSI#

AE6

GTLREF

AD26

VCCSENSE

AF7

VCCA

B26

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

RSVD

T22

RSVD

V3

RSVD

B2

RSVD

C3

VSS AB26

VSS AA25

VSS AD25

VSS AE26

VSS AB23

VSS AC24

VSS AF24

VSS AE23

VSS AA22

VSS AD22

VSS AC21

VSS AF21

VSS AB19

VSS AA19

VSS AD19

VSS AC19

VSS AF19

VSS AE19

VSS AB16

VSS AA16

VSS AD16

VSS AC16

VSS AF16

VSS AE16

VSS AB13

VSS AA14

VSS AD13

VSS AC14

VSS AF13

VSS AE14

VSS AB11

VSS AA11

VSS AD11

VSS AC11

VSS AF11

VSS AE11

VSS AB8

VSS AA8

VSS AD8

VSS AC8

VSS AF8

VSS AE8

VSS AA5

VSS AD5

VSS AC6

VSS AF6

VSS AB4

VSS AC3

VSS AF3

VSS AE4

VSS AB1

VSS AA2

VSS AD2

VSS AE1

VSS B6

VSS C5

VSS F5

VSS E6

VSS H6

VSS J5

VSS M5

VSS L6

VSS P6

VSS R5

VSS V5

VSS U6

VSS Y6

VSS A4

VSS D4

VSS E3

VSS H3

VSS G4

VSS K4

VSS L3

VSS P3

VSS N4

VSS T4

VSS U3

VSS Y3

VSS W4

VSS D1

VSS C2

VSS F2

VSS G1

RSVD

B25

VSSSENSE

AE7

VCCP

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VID0

AD6

VID1

AF5

VID2

AE5

VID3

AF4

VID4

AE3

VID5

AF2

VID6

AE2

BSEL0

B22

BSEL1

B23

BSEL2

C21

COMP0

R26

COMP1

U26

COMP2

U1

COMP3

V1

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

VCC

E7

C20

10U_0805_6.3V6M~D

1

2

R91

27.4_0402_1%~D

12

R93

27.4_0402_1%~D

12

C19

0.01U_0402_16V7K~D

1

2

R87

1K_0402_1%~D

12

R89 100_0402_1%~D

1 2

R92

54.9_0402_1%~D

12

R90

2K_0402_1%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCC_CORE

+VCC_CORE

+VCC_CORE

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

CPU Bypass

959Friday, May 12, 2006

Compal Electronics, Inc.

High Frequence Decoupling

7mOhm

PS CAP

ESR <= 1.5m ohm

Capacitor = 1320uF

Near VCORE regulator.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Place these inside

socket cavity on L8

(North side

Secondary)

Place these inside

socket cavity on L8

(Sorth side

Secondary)

South Side Secondary

Place these inside

socket cavity on L8

(North side

Secondary)

CRB was 270uF

North Side Secondary

7mOhm

PS CAP 6mOhm

PS CAP 6/7mOhm

PS CAP

Temp. characteristics: X5R

Operating range: -55~+85degree

6/7mOhm

PS CAP 6mOhm

PS CAP

CPU speed

1.06G 5.5W

1.2G 5.5W

1.2G 9.5W

CPU type

Signal core

Dual core

1@

2@

3@

P/N

BOM introduction

Use of decoupling

1. 220uF poly cap 2pcs

2. 22uF MLCC cap 8pcs

SA000017Z2L

1.06G 7.5W

4@

SA00000Z30L

1. 220uF poly cap 4pcs

2. 10uF MLCC cap 26pcs

BOM TAA

6@

W/O

W/O

5@ W

1.2G Signal core SA000017Z2L W

8@ 1.06G 5.5W

1. 220uF poly cap 2pcs

2. 22uF MLCC cap 8pcs

SA00000Z33L

SA00000Z33L

Note:

C42,C43,C41,C44

will change to

220U 2.5V 6M on

Dual Core CPU for

CPU transition

noise

Note:

C21,C23,C26,C28,C29,C31,C34,C36

use 22U on Single Core CPU and

use 10U on Dual Core CPU.

SA00001CF1L

Part Number Description

SA00000Z33L S IC LE80538UE0042M SL8W7 1.06G C0 FCBGA

Yonah-ULV_1.06G SC_UFCBGA479~D8@

C36

22U_0805_6.3V6M~D

1

2

C21

22U_0805_6.3V6M~D

1

2

C697

10U_0805_4VAM~D

4@

1

2

C51

0.1U_0402_10V7K~D

1

2

C48

0.1U_0402_16V4Z~D

1

2

+

C42

220U_D_2VM_R7M~D

4@

1

2

Part Number Description

SA000017Z2L S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA

Yonah-ULV_1.2G SC_UFCBGA479~D6@

C31

22U_0805_6.3V6M~D

1

2

+

C44

330U_D_2.5VM_R6M~D

1

2

C699

10U_0805_4VAM~D

4@

1

2

C23

22U_0805_6.3V6M~D

1

2

C696

10U_0805_4VAM~D

@

1

2

C40

10U_0805_4VAM~D

4@

1

2

Part Number Description

SA00001CF1L S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P

Yonah-ULV_1.2G DC_UFCBGA479~D4@

+

C705

330U_D_2.5VM_R6M~D

@

1

2

C693

10U_0805_4VAM~D

4@

1

2

C32

10U_0805_4VAM~D

@

1

2

+

C45

330U_D2E_2.5VM_R9~D

@

1

2

C701

10U_0805_4VAM~D

@

1

2

C698

10U_0805_4VAM~D

4@

1

2

Part Number Description

SA000017Z2L S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA

Yonah-ULV_1.2G SC_UFCBGA479~D2@

C702

10U_0805_4VAM~D

@

1

2

C46

0.1U_0402_10V7K~D

1

2

C695

10U_0805_4VAM~D

@

1

2

C47

0.1U_0402_10V7K~D

1

2

C22

10U_0805_4VAM~D

4@

1

2

C30

10U_0805_4VAM~D

4@

1

2

C700

10U_0805_4VAM~D

4@

1

2

C703

10U_0805_4VAM~D

4@

1

2

C50

0.1U_0402_10V7K~D

1

2

C33

10U_0805_4VAM~D

4@

1

2

C34

22U_0805_6.3V6M~D

1

2

+

C706

330U_D_2.5VM_R6M~D

@

1

2

C35

10U_0805_4VAM~D

4@

1

2

C37

10U_0805_4VAM~D

4@

1

2

Part Number Description

SA00001CF1L S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P

Yonah-ULV_1.2G DC_UFCBGA479~D5@

C704

10U_0805_4VAM~D

4@

1

2

C26

22U_0805_6.3V6M~D

1

2

C27

10U_0805_4VAM~D

4@

1

2

C39

10U_0805_4VAM~D

4@

1

2

C28

22U_0805_6.3V6M~D

1

2

+

C43

220U_D_2VM_R7M~D

4@

1

2

C24

10U_0805_4VAM~D

@

1

2

+

C41

330U_D_2.5VM_R6M~D

1

2

C49

0.1U_0402_16V4Z~D

1

2

C694

10U_0805_4VAM~D

4@

1

2

C38

10U_0805_4VAM~D

4@

1

2

C29

22U_0805_6.3V6M~D

1

2

C25

10U_0805_4VAM~D

4@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_SWNG1

H_SWNG0

H_VREF

V_DDR_MCH_REF

H_A#28

H_A#15

H_SWNG1

H_XRCOMP

H_D#16

H_D#10

H_A#16

H_D#62

H_D#60

H_D#19

H_D#7

H_D#0

H_A#20

H_A#17

H_A#13

H_SWNG0

H_D#53

H_D#39

H_D#38

H_D#32

H_D#13

M_OCDOCMP0

H_A#8

H_D#59

H_D#27

H_D#20

H_A#26

H_A#19

H_D#58

H_D#48

H_D#46

H_D#40

H_D#8

H_D#44

H_D#12

H_D#3

H_D#1

H_A#7

H_YSCOMP

H_D#43

H_D#35

H_D#31

H_D#25

H_D#24

H_A#22

H_D#61

H_D#56

H_D#21

H_D#11

H_D#6

H_A#27

H_A#6

H_A#3

H_D#37

H_D#33

H_D#30

H_D#63

H_D#51

H_D#9

H_D#2

SMRCOMPN

H_A#25

H_D#50

H_D#41

H_D#36

H_D#23

H_D#4

H_A#12

H_A#11

H_D#54

H_D#42

M_OCDOCMP1

H_A#18

H_A#10

H_D#52

H_D#45

H_D#28

H_D#22

H_A#14

H_XSCOMP

H_D#29

H_A#21

H_D#47

H_D#34

H_D#18

H_A#31

H_A#30

H_A#29

H_A#24

H_A#23

H_D#55

H_D#49

H_D#17

H_D#15

M_ODT0

H_A#9

H_A#5

H_A#4

H_D#57

H_D#26

H_D#14

H_D#5

H_YRCOMP

M_CLK_DDR1

M_CLK_DDR0

M_CLK_DDR#0

M_CLK_DDR#1

PM_EXTTS#0

ICH_PWRGD

M_CLK_DDR#2

M_CLK_DDR#3

M_CLK_DDR3

M_CLK_DDR2

M_ODT3

M_ODT2 PM_EXTTS#1

PM_EXTTS#0

H_DSTBP#0

H_DSTBP#2

H_DSTBP#3

H_DSTBN#3

H_DSTBP#1

H_DSTBN#1

H_DSTBN#0

H_DSTBN#2

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_RS#0

H_RS#2

H_RS#1

H_REQ#0

H_REQ#4

H_REQ#2

H_REQ#3

H_REQ#1

H_CPUSLP#

H_TRDY#

H_RESET#

H_VREF

H_BNR#

H_BPRI#

H_BR0#

H_VREF

H_ADSTB#1

H_ADSTB#0

H_ADS#

V_DDR_MCH_REF

SMRCOMPP

CPU_MCH_BSEL0

CPU_MCH_BSEL1

CPU_MCH_BSEL2

CFG3

CFG5

CFG5

CPU_MCH_BSEL0

THERMTRIP_MCH#

DMI_MTX_IRX_N0

DMI_MTX_IRX_N1

DMI_MRX_ITX_N0

DMI_MRX_ITX_N1

DMI_MTX_IRX_P0

DMI_MTX_IRX_P1

DMI_MRX_ITX_P0

DMI_MRX_ITX_P1

PLTRST_R#

DDR_CKE0

DDR_CKE1

DDR_CKE2_DIMMA

DDR_CKE3_DIMMA

DDR_CS3_DIMMA#

DDR_CS2_DIMMA#

DDR_CS1#

M_OCDOCMP1

M_OCDOCMP0

CFG6

PM_EXTTS#1

M_ODT1

DDR_CS0#

+1.8V_SUS

+3.3V_RUN

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_D#[0..63]<7>

CLK_MCH_BCLK# <6>

CLK_MCH_BCLK <6>

H_CPUSLP# <7,23>

V_DDR_MCH_REF<15,16,17,49>

MCH_DREFCLK <6>

MCH_DREFCLK# <6>

ICH_PWRGD <24,43>

MCH_ICH_SYNC# <22>

CLK_3GPLLREQ# <6>

PM_BMBUSY# <24>

THERMTRIP_MCH# <18>

PLTRST# <20,22,24,29,36>

H_REQ#[0..4] <7>

H_DPWR# <7>

H_DRDY# <7>

H_DSTBP#[0..3] <7>

H_DSTBN#[0..3] <7>

H_HIT# <7>

H_HITM# <7>

H_LOCK# <7>

H_RS#[0..2] <7>

H_BPRI# <7>

CFG19<13>

CPU_MCH_BSEL0 <6,8>DMI_MRX_ITX_N0<24> DMI_MRX_ITX_N1<24> DMI_MRX_ITX_P0<24> DMI_MRX_ITX_P1<24>

CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>

DDR_CKE0<16,17>

DDR_CKE3_DIMMA<15> DDR_CKE2_DIMMA<15>

DDR_CS3_DIMMA#<15> DDR_CS2_DIMMA#<15>

DDR_CS0#<16,17>

H_A#[3..31] <7>

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>

H_BNR# <7>

H_BR0# <7>

H_RESET# <7>

H_DBSY# <7>

H_DEFER# <7>

H_DINV#0 <7>

H_DINV#2 <7>

H_DINV#1 <7>

H_DINV#3 <7>

H_TRDY# <7>

DMI_MTX_IRX_N0<24> DMI_MTX_IRX_N1<24> DMI_MTX_IRX_P0<24> DMI_MTX_IRX_P1<24>

M_CLK_DDR0<16,17> M_CLK_DDR1<16,17>

M_CLK_DDR2<15> M_CLK_DDR3<15>

M_CLK_DDR#0<16,17> M_CLK_DDR#1<16,17>

M_CLK_DDR#2<15> M_CLK_DDR#3<15>

M_ODT0<16,17>

M_ODT2<15> M_ODT3<15>

DREF_SSCLK# <6>

DREF_SSCLK <6>

PM_EXTTS#0 <15>

PM_EXTTS#1 <24>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Calistoga(1 of 5)

10 59Friday, May 12, 2006

Compal Electronics, Inc.

Layout Note:

H_XRCOMP & H_YRCOMP trace width

and spacing is 10/20

Layout Note:

Route as short

as possible

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Stuff R111 & R112 for A1 Calistoga

(DMI Lane Reversal)

CFG19

Calistoga-GMS not have CFG4,CFG[7..18],CFG[20]

Need to double check

*

Low = DMI x 2

High = DMI x 4

CFG5

Strap Pin Table

Low = Normal

Operation (Default):

Lane number in Order

High = Reverse Lane

R105

200_0402_1%~D

12

C53

0.1U_0402_10V6K~D

1

2

T2PAD~D

C52

0.1U_0402_10V6K~D

1

2

R104

54.9_0402_1%~D

12

R101 80.6_0402_1%~D

1 2

CFG/RSVD

DMI

PM

DDR2 MUXING

CLK

Calistoga-GMS_FCBGA998~D

U3B

DMI_RXN_0

Y29

DMI_RXN_1

Y32

DMI_RXP_0

Y28

DMI_RXP_1

Y31

DMI_TXN_0

V28

DMI_TXN_1

V31

DMI_TXP_0

V29

DMI_TXP_1

V32

SM_CK_0

AF33

SM_CK_1

AG1

SM_CK_2

AJ1

SM_CK_3

AM30

SM_CK#_0

AG33

SM_CK#_1

AF1

SM_CK#_2

AK1

SM_CK#_3

AN30

SM_CKE_0

AN21

SM_CKE_1

AN22

SM_CKE_2

AF26

SM_CKE_3

AF25

SM_CS#_0

AG14

SM_CS#_1

AF12

SM_CS#_2

AK14

SM_CS#_3

AH12

SM_OCDCOMP_0

AJ21

SM_OCDCOMP_1

AF11

SM_ODT_0

AE12

SM_ODT_1

AF14

SM_ODT_2

AJ14

SM_ODT_3

AJ12

SM_RCOMPN

AN12

SM_RCOMPP

AN14

SM_VREF_0

AA33

SM_VREF_1

AE1 D_REFCLKN A27

D_REFCLKP A26

D_REFSSCLKN J33

D_REFSSCLKP H33

THRMTRIP# J15

PWROK AB29

RSTIN# W27

PM_BMBUSY# G21

PM_EXTTS#_0 F26

CFG_0 C18

CFG_1 E18

CFG_2 G20

CFG_5 J20

CFG_6 J18

PM_EXTTS#_1 H26

RESERVED8 F18

CLKREQ# J22

CFG_3 G18

PM_ICHSYNC# E31

RESERVED9 A3

RESERVED7 C17

RESERVED1 K32

RESERVED2 K31

R107

24.9_0402_1%~D

12

R97

221_0402_1%~D

12

T14 PAD~D

R113 1K_0402_5%~D @ 1 2

T13 PAD~D

R106

24.9_0402_1%~D

12

C55

0.1U_0402_10V6K~D

@

1

2

R109 10K_0402_5%~D@12

R96

100_0402_1%~D

12

R100100_0402_1%~D

1 2

T15 PAD~D

T3PAD~D

R98

100_0402_1%~D

12

R102

100_0402_1%~D

12

R110 1K_0402_5%~D @ 1 2

R103

54.9_0402_1%~D

12

R111

40.2_0402_1%~D

@

12

R95

221_0402_1%~D

12

R108 10K_0402_5%~D

12

R112

40.2_0402_1%~D

@

12

HOST

Calistoga-GMS_FCBGA998~D

U3A

H_XRCOMP

A10

H_XSCOMP

A6

H_XSWING

C15

H_YRCOMP

J1

H_YSCOMP

K1

H_YSWING

H1

H_D#_0

C4

H_D#_1

F6

H_D#_2

H9

H_D#_3

H6

H_D#_4

F7

H_D#_5

E3

H_D#_6

C2

H_D#_7

C3

H_D#_8

K9

H_D#_9

F5

H_D#_10

J7

H_D#_11

K7

H_D#_12

H8

H_D#_13

E5

H_D#_14

K8

H_D#_15

J8

H_D#_16

J2

H_D#_17

J3

H_D#_18

N1

H_D#_19

M5

H_D#_20

K5

H_D#_21

J5

H_D#_22

H3

H_D#_23

J4

H_D#_24

N3

H_D#_25

M4

H_D#_26

M3

H_D#_27

N8

H_D#_28

N6

H_D#_29

K3

H_D#_30

N9

H_D#_31

M1

H_D#_32

V8

H_D#_33

V9

H_D#_34

R6

H_D#_35

T8

H_D#_36

R2

H_D#_37

N5

H_D#_38

N2

H_D#_39

R5

H_D#_40

U7

H_D#_41

R8

H_D#_42

T4

H_D#_43

T7

H_D#_44

R3

H_D#_45

T5

H_D#_46

V6

H_D#_47

V3

H_D#_48

W2

H_D#_49

W1

H_D#_50

V2

H_D#_51

W4

H_D#_52

W7

H_D#_53

W5

H_D#_54

V5

H_D#_55

AB4

H_D#_56

AB8

H_D#_57

W8

H_D#_58

AA9

H_D#_59

AA8

H_D#_60

AB1

H_D#_61

AB7

H_D#_62

AA2

H_D#_63

AB5

H_A#_3 F8

H_A#_4 D12

H_A#_5 C13

H_A#_6 A8

H_A#_7 E13

H_A#_8 E12

H_A#_9 J12

H_A#_10 B13

H_A#_11 A13

H_A#_12 G13

H_A#_13 A12

H_A#_14 D14

H_A#_15 F14

H_A#_16 J13

H_A#_17 E17

H_A#_18 H15

H_A#_19 G15

H_A#_20 G14

H_A#_21 A15

H_A#_22 B18

H_A#_23 B15

H_A#_24 E14

H_A#_25 H13

H_A#_26 C14

H_A#_27 A17

H_A#_28 E15

H_A#_29 H17

H_A#_30 D17

H_A#_31 G17

H_ADS# F10

H_ADSTB#_0 C12

H_ADSTB#_1 H16

H_VREF0 E2

H_BNR# B9

H_BPRI# C7

H_BREQ0# G8

H_CPURST# B10

HCLKN AA6

HCLKP AA5

H_DBSY# C10

H_DEFER# C6

H_DINV#_0 H5

H_DINV#_1 J6

H_DINV#_2 T9

H_DINV#_3 U6

H_DPWR# G7

H_DRDY# E6

H_DSTBN#_0 F3

H_DSTBN#_1 M8

H_DSTBN#_2 T1

H_DSTBN#_3 AA3

H_DSTBP#_0 F4

H_DSTBP#_1 M7

H_DSTBP#_2 T2

H_DSTBP#_3 AB3

H_HIT# C8

H_HITM# B4

H_LOCK# C5

H_REQ#_0 G9

H_REQ#_1 E9

H_REQ#_2 G12

H_REQ#_3 B8

H_REQ#_4 F12

H_RS#_0 A5

H_RS#_1 B6

H_RS#_2 G10

H_SLPCPU# E8

H_TRDY# E10

H_VREF1 E1

R115 2.2K_0402_5%~D

1 2

R114 75_0402_5%~D

1 2

R99 80.6_0402_1%~D

1 2

C54

0.1U_0402_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D58

DDR_A_D43

DDR_A_D39

DDR_B_MA9

DDR_B_MA8

DDR_A_D61

DDR_A_D52

DDR_A_D27

DDR_A_D13

DDR_A_D3

DDR_B_MA2

DDR_A_D56

DDR_A_D45

DDR_A_D42

DDR_A_D37

DDR_A_D31

DDR_A_D26

DDR_A_D49

DDR_A_D38

DDR_A_D15

DDR_A_D11

DDR_A_D8

DDR_B_MA6

DDR_B_MA5

DDR_B_MA4

DDR_B_RAS#

DDR_A_D47

DDR_A_D23

DDR_A_D20

DDR_B_MA12

DDR_A_BS0

DDR_A_D62

DDR_A_D54

DDR_A_D50

DDR_A_D18

DDR_A_D9

DDR_A_D5

DDR_A_D48

DDR_A_D4

DDR_A_D17

DDR_A_D14

DDR_A_D10

DDR_B_MA1

DDR_A_D46

DDR_A_D41

DDR_B_MA11 DDR_B_CAS#

DDR_A_D36

DDR_A_D25

DDR_B_MA0 DDR_A_D55

DDR_A_D32

DDR_A_D30

DDR_B_WE#

DDR_A_D59

DDR_A_D51

DDR_A_D34

DDR_A_D12

DDR_A_D6

DDR_A_BS1

DDR_A_D44

DDR_A_D35

DDR_A_D21

DDR_A_D19

DDR_A_D40

DDR_A_D28

DDR_A_D24

DDR_B_MA10

DDR_A_D60

DDR_A_D33

DDR_A_D2

DDR_A_D1

DDR_A_D0

DDR_B_MA7 DDR_A_D63

DDR_A_D53

DDR_A_D16

DDR_B_MA3

DDR_A_D57

DDR_A_D29

DDR_A_D22

DDR_A_D7

DDR_A_DM0

DDR_A_DM3

DDR_A_DM1

DDR_A_DM4

DDR_A_DM6

DDR_A_DM2

DDR_A_DM5

DDR_A_DM7

DDR_A_DQS0

DDR_A_DQS2

DDR_A_DQS1

DDR_A_DQS6

DDR_A_DQS3

DDR_A_DQS7

DDR_A_DQS4

DDR_A_DQS5

DDR_A_DQS#1

DDR_A_DQS#4

DDR_A_DQS#3

DDR_A_DQS#6

DDR_A_DQS#2

DDR_A_DQS#5

DDR_A_DQS#7

DDR_A_DQS#0

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA5

DDR_A_MA9

DDR_A_MA8

DDR_A_MA11

DDR_A_MA10

DDR_A_MA12

DDR_A_CAS#

DDR_A_RAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR_A_WE#

DDR_B_BS0

DDR_B_BS1

DDR_B_MA13

DDR_B_BS2

DDR_A_MA13

DDR_A_D[0..63] <15,16>

DDR_A_BS1<16,17> DDR_A_BS0<16,17>

DDR_B_MA[0..13]<15>

DDR_B_WE# <15>

DDR_B_CAS# <15>

DDR_B_RAS# <15>

DDR_A_DM[0..7]<15,16>

DDR_A_MA[0..13]<16,17>

DDR_A_CAS#<16,17> DDR_A_RAS#<16,17>

DDR_A_WE#<16,17>

DDR_B_BS1<15> DDR_B_BS0<15>

DDR_B_BS2<15>

DDR_A_DQS#[0..7]<15,16>

DDR_A_DQS[0..7]<15,16>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Calistogo(2 of 5)

11 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DDR2 SYSTEM MEMORY

Calistoga-GMS_FCBGA998~D

U3C

SA_DQ_0 AC31

SA_DQ_1 AB28

SA_DQ_2 AE33

SA_DQ_3 AF32

SA_DQ_4 AC33

SA_DQ_5 AB32

SA_DQ_6 AB31

SA_DQ_7 AE31

SA_DQ_8 AH31

SA_DQ_9 AK31

SA_DQ_10 AL28

SA_DQ_11 AK27

SA_DQ_12 AH30

SA_DQ_13 AL32

SA_DQ_14 AJ28

SA_DQ_15 AJ27

SA_DQ_16 AH32

SA_DQ_17 AF31

SA_DQ_18 AH27

SA_DQ_19 AF28

SA_DQ_20 AJ32

SA_DQ_21 AG31

SA_DQ_22 AG28

SA_DQ_23 AG27

SA_DQ_24 AN27

SA_DQ_25 AM26

SA_DQ_26 AJ26

SA_DQ_27 AJ25

SA_DQ_28 AL27

SA_DQ_29 AN26

SA_DQ_30 AH25

SA_DQ_31 AG26

SA_DQ_32 AM12

SA_DQ_33 AL11

SA_DQ_34 AH9

SA_DQ_35 AK9

SA_DQ_36 AM11

SA_DQ_37 AK11

SA_DQ_38 AM8

SA_DQ_39 AK8

SA_DQ_40 AG9

SA_DQ_41 AF9

SA_DQ_42 AF8

SA_DQ_43 AK6

SA_DQ_44 AF7

SA_DQ_45 AG11

SA_DQ_46 AJ6

SA_DQ_47 AH6

SA_DQ_48 AN6

SA_DQ_49 AM6

SA_DQ_50 AK3

SA_DQ_51 AL2

SA_DQ_52 AM5

SA_DQ_53 AL5

SA_DQ_54 AJ3

SA_DQ_55 AJ2

SA_DQ_56 AG2

SA_DQ_57 AF3

SA_DQ_58 AE7

SA_DQ_59 AF6

SA_DQ_60 AH5

SA_DQ_61 AG3

SA_DQ_62 AG5

SA_DQ_63 AF5

SB_CAS# AG19

SB_RAS# AG21

SB_WE# AG20

SB_MA_0

AN20

SB_MA_1

AL21

SB_MA_2

AK21

SB_MA_3

AK22

SB_MA_4

AL22

SB_MA_5

AH22

SB_MA_6

AG22

SB_MA_7

AF21

SB_MA_8

AM21

SB_MA_9

AE21

SB_MA_10

AL20

SB_MA_11

AE22

SB_MA_12

AE26

SB_MA_13

AE20

SA_CAS#

AJ17

SA_RAS#

AK18

SA_RCVENIN#

AN28

SA_RCVENOUT#

AM28

SA_WE#

AH17

SA_MA_0

AJ15

SA_MA_1

AM17

SA_MA_2

AM15

SA_MA_3

AH15

SA_MA_4

AK15

SA_MA_5

AN15

SA_MA_6

AJ18

SA_MA_7

AF19

SA_MA_8

AN17

SA_MA_9

AL17

SA_MA_10

AG16

SA_MA_11

AL18

SA_MA_12

AG18

SA_MA_13

AL14

SA_DQS#_0

AC29

SA_DQS#_1

AK30

SA_DQS#_2

AJ33

SA_DQS#_3

AM25

SA_DQS#_4

AN8

SA_DQS#_5

AJ8

SA_DQS#_6

AM3

SA_DQS#_7

AE2

SA_DQS_0

AC28

SA_DQS_1

AJ30

SA_DQS_2

AK33

SA_DQS_3

AL25

SA_DQS_4

AN9

SA_DQS_5

AH8

SA_DQS_6

AM2

SA_DQS_7

AE3

SA_DM_0

AB30

SA_DM_1

AL31

SA_DM_2

AF30

SA_DM_3

AK26

SA_DM_4

AL9

SA_DM_5

AG7

SA_DM_6

AK5

SA_DM_7

AH3

SA_BS_0

AK12

SA_BS_1

AH11

SA_BS_2

AG17

SB_BS_0

AH21

SB_BS_1

AJ20

SB_BS_2

AE27

T4 PAD~D

T5 PAD~D

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAT_DDC2

CLK_DDC2

LCTLA_CLK

LCTLB_DATA

G_DAT_DDC2

VGA_RED

VGA_GRN

VGA_BLU

LCD_A2+

LCD_A2-

SDVO_CTRLDATA

L_IBG

LCD_A1-

LCD_A0-

LCD_A0+

LCD_A1+

G_CLK_DDC2

DVO_BLUE_C

SDVO_CTRLCLK +PEGCOMP

TVIREF

G_CLK_DDC2

G_DAT_DDC2

CRT_IREF

BIA_PWM

PANEL_BKEN

LCTLB_DATA

LCTLA_CLK

LCD_DDCDATA

LCD_DDCCLK

DVO_RED#_C

DVO_RED_C

DVO_GREEN#_C

DVO_GREEN_C

DVO_BLUE#_C

DVO_CLK#_C

DVO_CLK_C

LCD_DDCDATA

LCD_DDCCLK

LCD_ACLK-

LCD_ACLK+

LCD_ACLK-

LCD_A1-

LCD_A2+

LCD_ACLK+

LCD_A0+

LCD_A1+

LCD_A2-

LCD_A0-

+1.5VRUN_PCIE

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

DAT_DDC2 <21,38>

SDVOB_BLUE+ <20>

LCD_A0+<19> LCD_A1+<19> LCD_A2+<19>

LCD_A0-<19> LCD_A1-<19> LCD_A2-<19>

CLK_MCH_3GPLL#<6> CLK_MCH_3GPLL<6>

BIA_PWM<19,40>

LCD_DDCDATA<19>

LCD_ACLK-<19>

SDVOB_RED- <20>

SDVOB_RED+ <20>

SDVOB_GREEN- <20>

SDVOB_GREEN+ <20>

SDVOB_BLUE- <20>

SDVOB_CLK- <20>

SDVOB_CLK+ <20>

LCD_ACLK+<19>

SDVOB_INT- <20>

SDVOB_INT+ <20>

TV_CVBS <38>

TV_Y <38>

TV_C <38>

SDVO_CTRLDATA<20>

VGA_BLU<21,38>

VGA_GRN<21,38>

VGA_RED<21,38>

VGA_VSYNC<21> VGA_HSYNC<21>

PANEL_BKEN<19>

ENVDD<19>

SDVO_CTRLCLK<20>

LCD_DDCCLK<19>

CLK_DDC2 <21,38>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Calistoga(3 of 5)

12 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Close to U3.H25

Close to U3.G23

R126 150_0402_1%~D

12

C57 0.1U_0402_10V6K~D

1 2

R128 150_0402_1%~D

12

R120

150_0402_1%~D

12

R121

150_0402_1%~D

12

C713

3.3P_0402_50VJ~D

1

2

R580 2.2K_0402_5%~D

1 2

R130

2.2K_0402_5%~D

12

C712

3.3P_0402_50VJ~D

1

2

R581 2.2K_0402_5%~D

1 2

C56 0.1U_0402_10V6K~D

1 2

C58 0.1U_0402_10V6K~D

1 2

R129

2.2K_0402_5%~D

12

R123 10K_0402_5%~D

1 2

R119

150_0402_1%~D

12

R116

24.9_0402_1%~D

1 2

SDVO

LVDS VGA

TV

MISC

Calistoga-GMS_FCBGA998~D

U3F

SDVO_CTRLCLK

J27

G_CLKN

Y26

G_CLKP

AA26

SDVO_CTRLDATA

H27

TV_DACA A21

TV_DACB C20

TV_DACC E20

TV_IREF G23

TV_IRTNA B21

TV_IRTNB C21

TV_IRTNC D21

CRT_DDC_CLK

H20

CRT_DDC_DATA

H22

CRT_BLUE

A24

CRT_BLUE#

A23

CRT_GREEN

E25

CRT_GREEN#

F25

CRT_RED

C25

CRT_RED#

D25

CRT_VSYNC

F27

CRT_HSYNC

D27

CRT_IREF

H25

L_BKLTCTL

H30

L_BKLTEN

G29

L_CLKCTLA

F28

L_CTLBDATA

E28

L_DDC_CLK

G28

L_DDC_DATA

H28

L_VDDEN

K30

L_IBG

K27

L_VBG

J29

L_VREFH

J30

L_VREFL

K29

LA_CLKN

D30

LA_CLKP

C30

LA_DATAN_0

G31

LA_DATAN_1

F32

LA_DATAN_2

D31

LA_DATAP_0

H31

LA_DATAP_1

G32

LA_DATAP_2

C31

SDVO_RED N28

SDVO_GREEN M32

SDVO_BLUE P33

SDVO_CLKP R32

SDVO_RED# P28

SDVO_GREEN# N32

SDVO_BLUE# P32

SDVO_CLKN T32

SDVO_TVCLKIN M30

SDVO_INT P30

SDVO_FLDSTALL T30

SDVO_TVCLKIN# N30

SDVO_INT# R30

SDVO_FLDSTALL# T29

EXP_A_COMPI R28

EXP_A_ICOMPO M28

LB_DATAN_0

F33

LB_DATAN_1

D33

LB_DATAN_2

F30

LB_DATAP_0

E33

LB_DATAP_1

D32

LB_DATAP_2

F29

LB_CLKN

A30

LB_CLKP

A29

TV_DCONSEL0 G26

TV_DCONSEL1 J26

C60 0.1U_0402_10V6K~D

1 2

R127 150_0402_1%~D

12

R117 255_0402_1%~D

12

R122

4.99K_0402_1%~D

12

G

D

S

Q3

2N7002W-7-F_SOT323~D

2

13

C62 0.1U_0402_10V6K~D

1 2

R118 1.5K_0402_1%~D

12

G

D

S

Q4

2N7002W-7-F_SOT323~D

2

13

C61 0.1U_0402_10V6K~D

1 2

C63 0.1U_0402_10V6K~D

1 2

C714

3.3P_0402_50VJ~D

1

2

C59 0.1U_0402_10V6K~D

1 2

C711

8.2P_0402_50V8J~D 1

2

R124 10K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG19

+1.5V_RUN

+1.05V_VCCP

+1.05V_VCCP

CFG19 <10>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Calistoga(4 of 5)

13 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CRB 270uF

+

C71

220U_D2_4M_R45~D

1

2

C66

0.1U_0402_10V6K~D

1

2

C67

10U_0805_6.3V6M~D

1

2

NC

Calistoga-GMS_FCBGA998~D

U3G

NC1

W33

NC2

AM33

NC3

AL33

NC4

C33

NC5

B33

NC6

AN32

NC7

A32

NC8

AN31

NC9

W28

NC10

V27

NC11

W29

NC12

J24

NC13

H24

NC14

W32

NC15

G24

NC16

F24

NC17

E24

NC18

D24

NC19

K33

NC20

A31

NC21

E21

NC22

C23

NC23

AN19

NC24

AM19

NC25

AL19

NC29

AN3

NC30

Y9

NC31

J19

NC32

H19

NC33

G19

NC34

F19

NC35

E19

NC36

D19

NC37

C19

NC38

B19

NC41

G16

NC42

F16

NC43

E16

NC44

D16

NC45

C16

NC46

B16

NC47

AN2

NC49

Y7

NC50

AM4

NC51

AF4

NC52

AD4

NC53

AL4

NC54

AK4

NC57

AH4

NC58

AG4

NC59

AE4

NC60

AM1

NC64 Y5

NC63 AL1

NC62 Y6

NC61 W30

RESERVED26 Y25

RESERVED27 Y24

RESERVED28 AB22

RESERVED29 AB21

RESERVED30 AB19

RESERVED31 AB16

RESERVED32 AB14

RESERVED33 AA12

RESERVED34 W24

RESERVED35 AA24

RESERVED36 AB24

RESERVED37 AB20

RESERVED38 AB18

RESERVED39 AB15

RESERVED40 AB13

RESERVED41 AB12

NC28

AH19

NC26

AK19

NC27

AJ19

NC39

A19

NC40

Y8

NC48

A16

NC55

W31

NC56

AJ4 RESERVED42 AB17

NC65 Y10

NC66 W10

NC67 W25

NC68 V24

NC69 U24

NC70 V10

NC71 U10

NC72 K18

C64

0.1U_0402_10V6K~D

1

2

NCTF

Calistoga-GMS_FCBGA998~D

U3H

VCC_NCTF1

T25

VCC_NCTF2

R25

VCC_NCTF3

P25

VCC_NCTF4

N25

VCC_NCTF5

M25

VCC_NCTF6

P24

VCC_NCTF7

N24

VCC_NCTF8

M24

VCC_NCTF9

Y22

VCC_NCTF10

W22

VCC_NCTF11

V22

VCC_NCTF12

U22

VCC_NCTF13

T22

VCC_NCTF14

R22

VCC_NCTF15

P22

VCC_NCTF16

N22

VCC_NCTF17

M22

VCC_NCTF18

Y21

VCC_NCTF19

W21

VCC_NCTF20

V21

VCC_NCTF21

U21

VCC_NCTF22

T21

VCC_NCTF23

R21

VCC_NCTF24

P21

VCC_NCTF25

N21

VCC_NCTF26

M21

VCC_NCTF27

Y20

VCC_NCTF28

W20

VCC_NCTF29

V20

VCC_NCTF30

U20

VCC_NCTF31

T20

VCC_NCTF32

R20

VCC_NCTF33

P20

VCC_NCTF34

N20

VCC_NCTF35

M20

VCC_NCTF36

Y19

VCC_NCTF37

P19

VCC_NCTF38

N19

VCC_NCTF39

M19

VCC_NCTF40

Y18

VCC_NCTF41

P18

VCC_NCTF42

N18

VCC_NCTF43

M18

VCC_NCTF44

Y17

VCC_NCTF45

P17

VCC_NCTF46

N17

VCC_NCTF47

M17

VCC_NCTF48

Y16

VCC_NCTF49

P16

VCC_NCTF50

N16

VCC_NCTF51

M16

VCC_NCTF52

Y15

VCC_NCTF53

P15

VCC_NCTF54

N15

VCC_NCTF55

M15

VCC_NCTF56

Y14

VCCAUX_NCTF1 AD25

VCCAUX_NCTF2 AC25

VCCAUX_NCTF3 AB25

VCCAUX_NCTF4 AD24

VCCAUX_NCTF5 AC24

VCCAUX_NCTF6 AD22

VCCAUX_NCTF7 AD21

VCCAUX_NCTF8 AD20

VCCAUX_NCTF9 AD19

VCCAUX_NCTF10 AD18

VCCAUX_NCTF11 AD17

VCCAUX_NCTF12 AD16

VCCAUX_NCTF13 AD15

VCCAUX_NCTF14 AD14

VCCAUX_NCTF15 K14

VCCAUX_NCTF16 AD13

VCCAUX_NCTF17 Y13

VCCAUX_NCTF18 W13

VCCAUX_NCTF19 V13

VCCAUX_NCTF20 U13

VCCAUX_NCTF21 T13

VCCAUX_NCTF22 R13

VCCAUX_NCTF23 P13

VCCAUX_NCTF24 N13

VCCAUX_NCTF25 M13

VCCAUX_NCTF26 AD12

VCCAUX_NCTF27 Y12

VCCAUX_NCTF28 W12

VSS_NCTF1 AN33

VSS_NCTF2 AA25

VSS_NCTF3 V25

VSS_NCTF4 U25

VSS_NCTF5 AA22

VSS_NCTF6 AA21

VSS_NCTF7 AA20

VSS_NCTF8 AA19

VSS_NCTF9 AA18

VSS_NCTF10 AA17

VSS_NCTF11 AA16

VSS_NCTF12 AA15

VSS_NCTF13 AA14

VTT_NCTF1

T10

VTT_NCTF2

R10

VTT_NCTF3

P10

VTT_NCTF4

N10

VTT_NCTF5

L10

VCC_NCTF57

W14

VCC_NCTF58

V14

VCC_NCTF59

U14

VCC_NCTF60

T14

VCC_NCTF61

R14

VCCAUX_NCTF29 V12

VCCAUX_NCTF30 U12

VCCAUX_NCTF31 T12

VCCAUX_NCTF32 R12

VCCAUX_NCTF33 P12

VCCAUX_NCTF34 N12

VCCAUX_NCTF35 M12

VCCAUX_NCTF36 AD11

VCCAUX_NCTF37 AD10

VCCAUX_NCTF38 K10

VCC_NCTF62

P14

VCC_NCTF63

N14

VCC_NCTF64

M14

VTT_NCTF6

D1

VSS_NCTF14 AA13

VSS_NCTF15 A4

VSS_NCTF16 A33

VSS_NCTF17 B2

VSS_NCTF18 AN1

VSS_NCTF19 C1

RSVD_3

M10

RSVD_4

A18

RSVD_5

AB10

RSVD_6

AA10

CFG_19 K28

RESERVED10 K25

RESERVED11 K26

RESERVED12 R24

RESERVED13 T24

RESERVED14 K21

RESERVED15 K19

RESERVED16 K20

RESERVED17 K24

RESERVED18 K22

RESERVED19 J17

RESERVED20 K23

RESERVED21 K17

RESERVED22 K12

RESERVED23 K13

RESERVED24 K16

RESERVED25 K15

C68

10U_0805_6.3V6M~D

1

2

+

C70

220U_D2_4M_R45~D

1

2

VSS

Calistoga-GMS_FCBGA998~D

U3E

VSS_1

AH33

VSS_2

Y33

VSS_3

V33

VSS_4

R33

VSS_6

AK32

VSS_7

AG32

VSS_8

AE32

VSS_9

AC32

VSS_10

AA32

VSS_11

U32

VSS_12

H32

VSS_13

E32

VSS_14

C32

VSS_15

AM31

VSS_16

AJ31

VSS_17

AA31

VSS_18

U31

VSS_19

T31

VSS_20

R31

VSS_21

P31

VSS_22

N31

VSS_23

M31

VSS_24

J31

VSS_25

F31

VSS_26

AL30

VSS_27

AG30

VSS_28

AE30

VSS_29

AC30

VSS_30

AA30

VSS_31

Y30

VSS_32

V30

VSS_33

U30

VSS_34

G30

VSS_35

E30

VSS_36

B30

VSS_37

AA29

VSS_38

U29

VSS_39

R29

VSS_40

P29

VSS_41

N29

VSS_42

M29

VSS_43

H29

VSS_44

E29

VSS_45

B29

VSS_46

AK28

VSS_47

AH28

VSS_48

AE28

VSS_49

AA28

VSS_50

U28

VSS_51

T28

VSS_52

J28

VSS_53

D28

VSS_54

AM27

VSS_55

AF27

VSS_56

AB27

VSS_57

AA27

VSS_58

Y27

VSS_59

U27

VSS_60

T27

VSS_61

R27

VSS_62

P27

VSS_63

N27

VSS_64

M27

VSS_65

G27

VSS_67

C27

VSS_68

B27

VSS_69

AL26

VSS_71

W26

VSS_72

U26

VSS_73

AN25

VSS_74

AK25

VSS_77

J25

VSS_78

G25

VSS_79

A25

VSS_80

H23

VSS_81

F23

VSS_111 J16

VSS_112 AL15

VSS_113 AG15

VSS_114 W15

VSS_115 R15

VSS_116 F15

VSS_117 D15

VSS_118 AM14

VSS_119 AH14

VSS_120 AE14

VSS_121 H14

VSS_122 B14

VSS_123 F13

VSS_124 D13

VSS_125 AL12

VSS_126 AG12

VSS_127 H12

VSS_128 B12

VSS_129 AN11

VSS_130 AJ11

VSS_131 AE11

VSS_132 AM9

VSS_134 AB9

VSS_135 W9

VSS_136 R9

VSS_137 M9

VSS_138 J9

VSS_139 F9

VSS_140 C9

VSS_141 A9

VSS_142 AL8

VSS_143 AG8

VSS_144 AE8

VSS_145 U8

VSS_146 AA7

VSS_147 V7

VSS_148 R7

VSS_149 N7

VSS_150 H7

VSS_151 E7

VSS_152 B7

VSS_153 AL6

VSS_154 AG6

VSS_155 AE6

VSS_156 AB6

VSS_157 W6

VSS_158 T6

VSS_159 M6

VSS_160 K6

VSS_161 AN5

VSS_162 AJ5

VSS_163 B5

VSS_164 AA4

VSS_165 V4

VSS_166 R4

VSS_167 N4

VSS_168 K4

VSS_169 H4

VSS_170 E4

VSS_171 AL3

VSS_172 AD3

VSS_173 W3

VSS_174 T3

VSS_5

G33

VSS_133 AJ9

VSS_175 B3

VSS_176 AK2

VSS_177 AH2

VSS_178 AF2

VSS_179 AB2

VSS_180 M2

VSS_181 K2

VSS_182 H2

VSS_183 F2

VSS_184 V1

VSS_185 R1

VSS_66

E27

VSS_70

AH26

VSS_75

AG25

VSS_76

AE25

VSS_82

B23

VSS_84

AJ22

VSS_85

AF22

VSS_86

G22

VSS_83

AM22

VSS_87

E22

VSS_88

J21

VSS_89

H21

VSS_90

F21

VSS_91

AM20

VSS_100

AF18 VSS_99

AH18 VSS_98

AM18

VSS_96

W19 VSS_95

D20 VSS_94

AF20

VSS_92

AK20

VSS_93

AH20

VSS_97

R19

VSS_101

U18

VSS_102

H18

VSS_103

D18

VSS_104

AK17

VSS_105

V17

VSS_106

T17

VSS_107

F17

VSS_108

B17

VSS_109

AH16

VSS_110

U16

C65

0.1U_0402_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSA_TVBG

U3_F1

U3_AB33

U3_AH1

VSSA_TVBG

+3VRUN_ATV

+3.3V_TV

+2.5V_CRT

+3GPLL_R

U3_AM32

U3_AN4

U3_AN18

U3_AA1

U3_A14

U3_A7

+2.5V_CRTDAC

+3GPLL_L

+VCC3G_R

+2.5V_RUN

+2.5V_RUN +1.5VRUN_PCIE

+2.5V_RUN

+1.5VRUN_QTVDAC

+2.5V_RUN

+3VRUN_ATVBG

+3VRUN_TVDACC

+3VRUN_TVDACB

+3VRUN_TVDACA

+2.5V_RUN

+1.5VRUN_MPLL

+1.5VRUN_HPLL

+1.5VRUN_DPLLA

+1.5VRUN_DPLLB

+1.5VRUN_3GPLL

+2.5V_RUN

+3VRUN_TVDACA

+3VRUN_TVDACB

+3V_TVDAC

+3VRUN_ATVBG

+3VRUN_TVDACC

+1.5VRUN_3GPLL

+1.5VRUN_HPLL +1.5VRUN_DPLLA

+1.5VRUN_MPLL

+1.5VRUN_DPLLB

+1.5VRUN_QTVDAC

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+2.5V_RUN

+2.5V_RUN

+2.5V_RUN

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.05V_VCCP

+1.5V_RUN

+1.5V_RUN

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Calistoga(5 of 5)

14 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

close pin B31

Route VSSA_TVBG GND from GMCH to

decoupling cap ground lead and then

connect to the GND plane.

CRB 270uF

Route VSSA_TVBG GND from GMCH to

decoupling cap ground lead and then

connect to the GND plane.

CRTDAC: Route FB

within 3" of Calistoga

Route VSSACRTDAC gnd from GMCH to

decoupling cap ground lead and then

connect to the gnd plane.

Route +2.5VRUN from GMCH pinN33 to

decoupling cap (C66)<200mil to the edge.

C65, C73, C83 replace by 0

ohm 0805 resistor

close pin C29/D29

45mA Max. 40mA Max.

45mA Max.

40mA Max.

CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV

Follow 945GMS desgin

guild to modify

180ohm,1500mA,0.09ohm

120ohm,600mA,0.25ohm

180ohm,1500mA,0.09ohm

120ohm,600mA,0.25ohm

60ohm,3000mA,0.025ohm

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

Close to U3.F20

L3

BLM18PG181SN1_0603~D

12

C100

22U_0805_6.3V6M~D

1

2

C84

0.022U_0402_16V7K~D

1

2

C88

0_0805_5%~D

1 2

3

C126

4.7U_0603_6.3V6M~D

1

2

C102

0.1U_0402_10V6K~D

1

2

C119

0.1U_0402_10V6K~D

1

2

+

C105

330U_D2E_2.5VM_R9~D

@

1

2

R131

0_0603_5%~D

1 2

+

C110

220U_D2_4M_R45~D

1

2

C86

0.022U_0402_16V7K~D

1

2

L7

BLM11A121S_0603~D

12

C79

10U_0805_6.3V6M~D

1

2

C81

4.7U_0603_6.3V6M~D

1

2

C114

10U_0805_6.3V6M~D

1

2

R583

0_0805_5%~D

1 2

C90

4.7U_0603_6.3V6M~D

@

1

2

C82

4.7U_0603_6.3V6M~D

1

2

C92

0.1U_0402_10V6K~D

1

2

R133

10_0402_5%~D

1 2

C125

0.01U_0402_16V7K~D

1

2

+

C101

470U_D2_2.5VM~D

1

2

C87

0.1U_0402_10V6K~D

1

2

R134

10_0402_5%~D

1 2

C74

10U_0805_6.3V6M~D

1

2

R132

0.5_0805_1%~D

1 2

C83

0_0805_5%~D

1 2

3

C130

10U_0805_6.3V6M~D

1

2

+

C121

470U_D2_2.5VM~D

1

2

C632

0.47U_0402_16V4Z~D

1 2

C77

0_0805_5%~D

1 2

3

C80

0.1U_0402_10V6K~D

1

2

C115

0.1U_0402_10V6K~D

1

2

C631

0.47U_0402_16V4Z~D

1 2

+

C123

220U_D2_4M_R45~D

1

2

C85

0.1U_0402_10V6K~D

1

2

C75

10U_0805_6.3V6M~D

1

2

C113

10U_0805_6.3V6M~D

1

2

D2

MMBD4148W-7-F_SOT323~D

1

3

2

C129

0.1U_0402_10V6K~D

1

2

L11

BLM18PG181SN1_0603~D

12

L9

BLM18PG181SN1_0603~D

1 2

C96

1U_0402_6.3V4Z~D

1

2

C78

0.1U_0402_10V6K~D

1

2

C118

0.47U_0402_16V4Z~D

1

2

C97

1U_0402_6.3V4Z~D

1

2

C91

0.1U_0402_10V6K~D

1

2

C124

0.1U_0402_10V6K~D

1

2

R582

0_0805_5%~D

1 2 C109

22U_0805_6.3V6M~D

1

2

C127

0.1U_0402_10V6K~D

1

2

C76

0.1U_0402_10V6K~D

1

2

C108

0.1U_0402_10V6K~D

1

2

POWER

Calistoga-GMS_FCBGA998~D

U3D

VCC0

T26

VCC1

R26

VCC2

P26

VCC3

N26

VCC4

M26

VCC5

V19

VCC6

U19

VCC7

T19

VCC8

W18

VCC9

V18

VCC10

T18

VCC11

R18

VCCDHMPLL1 AE5

VCCDHMPLL2 AD5

VCCADPLLA B26

VCCADPLLB J32

VCCAHPLL AD2

VCCAMPLL AD1

VCCACRTDAC0 C24

VCCACRTDAC1 B24

VSSACRTDAC B25

VCCSYNC J23

VTT0

A14

VTT1

D10

VTT2

P9

VTT3

L9

VTT4

D9

VTT5

P8

VTT6

L8

VTT7

D8

VTT8

P7

VTT9

L7

VTT10

D7

VTT11

A7

VTT12

P6

VTT13

L6

VTT14

G6

VTT15

D6

VTT16

U5

VTT17

P5

VTT18

L5

VTT19

G5

VTT20

D5

VCCA3GBG N33

VSSA3GBG M33

VCCA3GPLL V26

VCC3G0 U33

VCC3G1 T33

VCCTXLVDS1 C29

VCCSM0 AB33

VCCSM1 AM32

VCCSM2 AN29

VCCSM3 AM29

VCCSM4 AL29

VCCSM5 AK29

VCCSM6 AJ29

VCCSM7 AH29

VCCSM8 AG29

VCCSM9 AF29

VCCSM10 AE29

VCCSM11 AN24

VCCSM12 AM24

VCCSM13 AL24

VCCSM14 AK24

VCCSM15 AJ24

VCCSM16 AH24

VCCSM17 AG24

VCCSM18 AF24

VCCSM19 AE24

VCCSM20 AN18

VCCSM21 AN16

VCCHV0 E26

VCCHV1 D26

VCCHV2 C26

VCCALVDS B31

VCCDLVDS0 C28

VCCDLVDS1 B28

VCCDLVDS2 A28

VCCDTVDAC F20

VCCDQTVDAC F22

VCCATVBG D23

VSSATVBG E23

VCCATVDACA0 B20

VCCATVDACA1 A20

VCCATVDACB0 B22

VCCATVDACB1 A22

VCCATVDACC0 D22

VCCATVDACC1 C22

VCC12

W17

VCC13

U17

VCC14

R17

VCC15

W16

VCC16

V16

VCC17

T16

VCC18

R16

VCC19

V15

VCC20

U15

VCC21

T15

VCCAUX1

AD33

VCCAUX2

AD32

VCCAUX3

AD31

VCCAUX4

AD30

VCCAUX5

AD29

VCCAUX6

AD28

VCCAUX7

AD27

VCCAUX8

AC27

VCCAUX9

AD26

VCCAUX10

AC26

VCCAUX11

AB26

VCCAUX12

AE19

VCCAUX13

AE18

VCCAUX14

AF17

VCCAUX15

AE17

VCCAUX16

AF16

VCCAUX17

AE16

VCCAUX18

AF15

VCCAUX19

AE15

VCCAUX20

J14

VCCAUX21

J10

VCCAUX26

AD8

VCCAUX27

AD7

VCCAUX28

AD6

VCCTXLVDS0 D29

VCCSM22 AM16

VCCSM23 AL16

VCCSM24 AK16

VCCSM25 AJ16

VCCSM26 AN13

VCCSM27 AM13

VCCSM28 AL13

VCCSM29 AK13

VCCSM30 AJ13

VCCSM31 AH13

VCCSM32 AG13

VCCSM33 AF13

VCCSM34 AE13

VCCSM35 AN4

VCCSM36 AM10

VCCSM37 AL10

VCCSM38 AK10

VCCSM39 AH1

VCCSM40 AH10

VCCSM41 AG10

VCCSM42 AF10

VCCSM43 AE10

VCCSM44 AN7

VTT22

U4

VTT23

P4

VCCSM45 AM7

VTT24

L4

VTT25

G4

VTT26

D4

VTT27

Y3

VTT28

U3

VTT29

P3

VTT30

L3

VTT31

G3

VTT32

D3

VTT33

Y2

VTT34

U2

VTT35

L2 VTT36

P2

VTT37

G2

VTT38

D2

VTT39

AA1

VTT45 Y1

VCCAUX22

H10

VCCAUX23

AE9

VCCAUX24

AD9

VCCAUX25

U9

VSSALVDS B32

VTT44 U1

VTT41 P1

VTT42 L1

VTT43 G1

VTT40

F1

VCCSM46 AL7

VCCSM47 AK7

VCCSM48 AJ7

VCCSM49 AH7

VCCSM50 AN10

VCCSM51 AJ10

VTT21

Y4

L5

BLM11A121S_0603~D

12

D1

MMBD4148W-7-F_SOT323~D

1

3

2

C99

0.1U_0402_10V6K~D

1

2

L10

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

12

C104

0.1U_0402_10V6K~D

1

2

C117

0.1U_0402_10V6K~D

1

2

L6

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

12

L4

BLM18PG181SN1_0603~D

12

C95

1U_0402_6.3V4Z~D

1

2

C112

4.7U_0603_6.3V6M~D

1

2

C111

4.7U_0603_6.3V6M~D

1

2

C128

0.1U_0402_10V6K~D

1

2

C89

0.1U_0402_10V6K~D

1

2

C93

1U_0402_6.3V4Z~D

1

2

C73

0.1U_0402_10V6K~D

1

2

C122

0.1U_0402_10V6K~D

1

2

L8

BLM21PG600SN1D_0805~D

12

C94

1U_0402_6.3V4Z~D

1

2

C116

0.022U_0402_16V7K~D

1

2

C72

0_0805_5%~D

1 2

3

C120

0.47U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_B_MA11

V_DDR_MCH_REF

DDR_CKE3_DIMMA

M_CLK_DDR3

M_CLK_DDR2

M_CLK_DDR#3

M_CLK_DDR#2

DDR_CKE3_DIMMA

DDR_CS2_DIMMA#

CLK_SCLK

DDR_B_MA1

DDR_B_MA10

DDR_B_MA3

DDR_B_MA9 DDR_B_MA7

DDR_B_MA12

DDR_B_MA5

DDR_B_WE#

DDR_A_D9

DDR_A_D3

DDR_A_D13

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D15

DDR_A_D24

DDR_A_D21

DDR_A_D23

DDR_A_D17

DDR_A_D19

DDR_A_D14

DDR_A_D28

DDR_A_D27

DDR_A_D36

DDR_A_D60

DDR_A_D43

DDR_A_D49

DDR_A_D48

DDR_A_D63

DDR_A_D62

DDR_A_D61

DDR_A_DQS1

DDR_A_DQS0

DDR_A_DQS2

DDR_A_DM3

DDR_A_DM1

DDR_A_DM2

DDR_A_DQS4

DDR_A_DQS6

DDR_A_DQS7

CLK_SDATA

DDR_CKE2_DIMMA

DDR_B_MA8

DDR_CS3_DIMMA#

DDR_B_MA11

DDR_B_MA2

DDR_B_MA0

DDR_B_MA4

DDR_B_MA6

DDR_B_CAS#

DDR_B_BS1

DDR_B_RAS#

DDR_A_D1

DDR_A_D0

DDR_A_D2

DDR_A_D4

DDR_A_D11

DDR_A_D16

DDR_A_D10

DDR_A_D20

DDR_A_D22

DDR_A_D12

DDR_A_D8

DDR_A_D29

DDR_A_D31

DDR_A_D18

DDR_A_D25

DDR_A_D34

DDR_A_D45

DDR_A_D53

DDR_A_D52

DDR_A_D56

DDR_A_D58

DDR_A_D57

DDR_A_D59

DDR_A_DM6

DDR_A_DM4

DDR_A_DM5

DDR_A_DM7

DDR_B_MA13

DDR_A_DQS5

DDR_B_BS0

DDR_B_BS2

DDR_A_DQS#0

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

DDR_B_MA0

DDR_B_MA4

DDR_B_BS1

DDR_B_MA6

DDR_B_MA2

M_ODT2

M_ODT3

M_ODT2

DDR_B_MA13

DDR_B_MA7

DDR_A_DM0

DDR_A_D47

DDR_CS2_DIMMA#

DDR_B_RAS#

DDR_A_D46DDR_A_D44

DDR_A_D42

DDR_A_D35

DDR_A_D39

DDR_A_D38

DDR_A_D32 DDR_A_D37

DDR_A_D33

DDR_A_D26 DDR_A_D30

M_ODT3

DDR_B_BS2

DDR_B_BS0

DDR_B_MA10

DDR_B_CAS#

DDR_B_WE#

DDR_CKE2_DIMMA

DDR_B_MA9

DDR_B_MA5

DDR_B_MA12

DDR_B_MA8

DDR_A_D41

DDR_A_D40

DDR_B_MA3

DDR_B_MA1

DDR_CS3_DIMMA#

PM_EXTTS#0

DDR_A_D54

DDR_A_D55 DDR_A_D50

DDR_A_D51

+0.9V_DDR_VTT

+0.9V_DDR_VTT

+3.3V_RUN

+1.8V_SUS

+1.8V_SUS +1.8V_SUS

+3.3V_RUN

DDR_A_DQS[0..7]<11,16>

DDR_B_MA[0..13]<11>

M_CLK_DDR3 <10>

M_CLK_DDR2 <10>

M_CLK_DDR#3 <10>

M_CLK_DDR#2 <10>

DDR_CKE3_DIMMA <10>

DDR_CS2_DIMMA# <10>

DDR_CKE2_DIMMA<10>

DDR_CS3_DIMMA#<10>

DDR_A_DQS#[0..7]<11,16>

M_ODT2 <10>

M_ODT3<10>

DDR_B_BS1 <11>

DDR_B_WE#<11> DDR_B_RAS# <11>

DDR_B_CAS#<11>

DDR_B_BS0<11>

DDR_B_BS2<11>

V_DDR_MCH_REF <10,16,17,49>

PM_EXTTS#0 <10>

DDR_A_DM[0..7]<11,16>

CLK_SDATA<6,17> CLK_SCLK<6,17>

DDR_A_D[0..63]<11,16>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

DDRII-SODIMM SLOT1

15 59Friday, May 12, 2006

Compal Electronics, Inc.

Layout Note:

Place these resistor

closely DIMM0,all

trace length

Max=1.3"

Layout Note:

Place near JDIM1

Layout Note:

Place one cap close to every 2 pullup

resistors terminated to +0.9V_DDR_VTT

Layout Note:

Place these resistor

closely DIMM0,all

trace length<750 mil

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ON Bottom SIDE

STANDARD

DIMMA

C145

0.1U_0402_16V4Z~D

1

2

C139

0.1U_0402_16V4Z~D

1

2

R135 10K_0402_5%~D

1 2

RN2

56_0404_4P2R_5%~D

14 23

C150

0.1U_0402_16V4Z~D

1

2

C152

0.1U_0402_16V4Z~D

1

2

RN1

56_0404_4P2R_5%~D

1 4

2 3

C131

2.2U_0603_6.3V6K~D

1

2

RN9

56_0404_4P2R_5%~D

1 4

2 3

RN6

56_0404_4P2R_5%~D

14 23

C136

2.2U_0603_6.3V6K~D

1

2

C148

0.1U_0402_16V4Z~D

1

2

C154

0.1U_0402_16V4Z~D

1

2

C142

0.1U_0402_16V4Z~D

1

2

RN4

56_0404_4P2R_5%~D

14 23

C133

2.2U_0603_6.3V6K~D

1

2

C141

0.1U_0402_16V4Z~D

1

2

R565 0_0402_5%~D

12

RN3

56_0404_4P2R_5%~D

1 4

2 3

C156

2.2U_0603_6.3V6K~D

1

2

C144

0.1U_0402_16V4Z~D

1

2

RN12

56_0404_4P2R_5%~D

1 4

2 3

C153

0.1U_0402_16V4Z~D

1

2

C140

0.1U_0402_16V4Z~D

1

2

C135

2.2U_0603_6.3V6K~D

1

2

RN8

56_0404_4P2R_5%~D

14 23

RN13

56_0404_4P2R_5%~D

14 23

C146

0.1U_0402_16V4Z~D

1

2

R136 10K_0402_5%~D

1 2

C132

0.1U_0402_16V4Z~D

1

2

R597

100K_0402_5%~D

@

1 2

RN10

56_0404_4P2R_5%~D

14 23

C143

0.1U_0402_16V4Z~D

1

2

JDIMB

TYCO_1775803-2~D

VREF

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DQS0#

11

DQS0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

VSS 2

DQ4 4

DQ5 6

VSS 8

DM0 10

VSS 12

DQ6 14

DQ7 16

VSS 18

DQ12 20

DQ13 22

VSS 24

DM1 26

VSS 28

CK0 30

CK0# 32

VSS 34

DQ14 36

DQ15 38

VSS 40

VSS

41

DQ16

43

DQ17

45

VSS

47

DQS2#

49

DQS2

51

VSS

53

DQ18

55

DQ19

57

VSS

59

DQ24

61

DQ25

63

VSS

65

DM3

67

NC

69

VSS

71

DQ26

73

DQ27

75

VSS

77

CKE0

79

VDD

81

NC

83

BA2

85

VDD

87

A12

89

A9

91

A8

93

VDD

95

A5

97

A3

99

A1

101

VDD

103

A10/AP

105

BA0

107

WE#

109

VDD

111

CAS#

113

NC/S1#

115

VDD

117

NC/ODT1

119

VSS

121

DQ32

123

DQ33

125

VSS

127

DQS4#

129

DQS4

131

VSS

133

DQ34

135

DQ35

137

VSS

139

DQ40

141

DQ41

143

VSS

145

DM5

147

VSS

149

DQ42

151

DQ43

153

VSS

155

DQ48

157

DQ49

159

VSS

161

NC,TEST

163

VSS

165

DQS6#

167

DQS6

169

VSS

171

DQ50

173

DQ51

175

VSS

177

DQ56

179

DQ57

181

VSS

183

DM7

185

VSS

187

DQ58

189

DQ59

191

VSS

193

SDA

195

SCL

197

VDDSPD

199

VSS 42

DQ20 44

DQ21 46

VSS 48

NC 50

DM2 52

VSS 54

DQ22 56

DQ23 58

VSS 60

DQ28 62

DQ29 64

VSS 66

DQS3# 68

DQS3 70

VSS 72

DQ30 74

DQ31 76

VSS 78

NC/CKE1 80

VDD 82

NC/A15 84

NC/A14 86

VDD 88

A11 90

A7 92

A6 94

VDD 96

A4 98

A2 100

A0 102

VDD 104

BA1 106

RAS# 108

S0# 110

VDD 112

ODT0 114

NC/A13 116

VDD 118

NC 120

VSS 122

DQ36 124

DQ37 126

VSS 128

DM4 130

VSS 132

DQ38 134

DQ39 136

VSS 138

DQ44 140

DQ45 142

VSS 144

DQS5# 146

DQS5 148

VSS 150

DQ46 152

DQ47 154

VSS 156

DQ52 158

DQ53 160

VSS 162

CK1 164

CK1# 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

SAO 198

SA1 200

C155

0.1U_0402_16V4Z~D

1

2

RN5

56_0404_4P2R_5%~D

1 4

2 3

C137

2.2U_0603_6.3V6K~D

1

2

RN11

56_0404_4P2R_5%~D

14 23

RN7

56_0404_4P2R_5%~D

1 4

2 3

C149

0.1U_0402_16V4Z~D

1

2

C138

0.1U_0402_16V4Z~D

1

2

C147

0.1U_0402_16V4Z~D

1

2

C134

2.2U_0603_6.3V6K~D

1

2

C151

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D5

DDR_A_D6 DDR_SDQ5

DDR_SDQ6

DDR_A_D2

DDR_A_D1

DDR_A_D4

DDR_A_D0

DDR_A_D3

DDR_A_D7

DDR_A_D8

DDR_A_D12

DDR_A_D14

DDR_A_D15

DDR_A_D13

DDR_A_D9

DDR_A_D11

DDR_A_D10

DDR_A_D20

DDR_A_D16

DDR_A_D18

DDR_A_D22

DDR_A_D21

DDR_A_D17

DDR_A_D23

DDR_A_D19

DDR_A_D29

DDR_A_D25

DDR_A_D27

DDR_A_D26

DDR_A_D24

DDR_A_D28

DDR_A_D31

DDR_A_D30

DDR_SDQ2

DDR_SDQ1

DDR_SDQ4

DDR_SDQ0

DDR_SDQ3

DDR_SDQ7

DDR_SDQ8

DDR_SDQ12

DDR_SDQ14

DDR_SDQ15

DDR_SDQ13

DDR_SDQ9

DDR_SDQ11

DDR_SDQ10

DDR_SDQ20

DDR_SDQ16

DDR_SDQ18

DDR_SDQ22

DDR_SDQ21

DDR_SDQ17

DDR_SDQ23

DDR_SDQ19

DDR_SDQ29

DDR_SDQ25

DDR_SDQ27

DDR_SDQ26

DDR_SDQ24

DDR_SDQ28

DDR_SDQ31

DDR_SDQ30

DDR_A_D35

DDR_A_D38

DDR_A_D36

DDR_A_D32

DDR_A_D37

DDR_A_D33

DDR_A_D34

DDR_A_D39

DDR_A_D40

DDR_A_D42

DDR_A_D47

DDR_A_D46

DDR_A_D41

DDR_A_D45

DDR_A_D43

DDR_A_D44

DDR_A_D49

DDR_A_D48

DDR_A_D55

DDR_A_D54

DDR_A_D53

DDR_A_D52

DDR_A_D51

DDR_A_D50

DDR_A_D57

DDR_A_D56

DDR_A_D63

DDR_A_D62

DDR_A_D61

DDR_A_D60

DDR_A_D58

DDR_A_D59

DDR_SDQ35

DDR_SDQ38

DDR_SDQ36

DDR_SDQ32

DDR_SDQ37

DDR_SDQ33

DDR_SDQ34

DDR_SDQ39

DDR_SDQ40

DDR_SDQ42

DDR_SDQ47

DDR_SDQ46

DDR_SDQ41

DDR_SDQ45

DDR_SDQ43

DDR_SDQ44

DDR_SDQ49

DDR_SDQ48

DDR_SDQ55

DDR_SDQ54

DDR_SDQ53

DDR_SDQ52

DDR_SDQ51

DDR_SDQ50

DDR_SDQ57

DDR_SDQ56

DDR_SDQ63

DDR_SDQ62

DDR_SDQ61

DDR_SDQ60

DDR_SDQ58

DDR_SDQ59

DDR_A_DQS0

DDR_A_DQS#0 DDR_SDQS0

DDR_SDQS#0

DDR_A_DQS1

DDR_A_DQS#1 DDR_SDQS#1

DDR_A_DQS2

DDR_A_DQS#2

DDR_SDQS1

DDR_SDQS2

DDR_SDQS#3

DDR_A_DQS3

DDR_A_DQS#3 DDR_SDQS3

DDR_A_DQS5

DDR_A_DQS4

DDR_SDQS5

DDR_SDQS4

DDR_SDQS#2

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_DQS#7

DDR_A_DQS7

DDR_SDQS6

DDR_SDQS7

DDR_SDQS#5

DDR_SDQS#4

DDR_SDQS#6

DDR_SDQS#7

DDR_A_DM0 DDR_SDM0

DDR_A_DM1 DDR_SDM1

DDR_A_DM2 DDR_SDM2

DDR_A_DM3 DDR_SDM3

DDR_A_DM4 DDR_SDM4

DDR_A_DM5 DDR_SDM5

DDR_A_DM6 DDR_SDM6

DDR_A_DM7 DDR_SDM7

V_DDR_MCH_REF

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

M_CLK_DDR#0

M_CLK_DDR0

M_ODT0

DDR_CKE0

DDR_A_BS0

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

V_DDR_MCH_REF

V_DDR_MCH_REF

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

M_CLK_DDR#1

DDR_CKE0

DDR_A_BS0

M_CLK_DDR1

M_ODT0

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

V_DDR_MCH_REF

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

M_CLK_DDR#1

DDR_CKE0

DDR_A_BS0

M_CLK_DDR1

M_ODT0

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

DDR_CKE0

M_CLK_DDR#0

M_CLK_DDR0

DDR_A_BS0

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

DDR_SDQS#2

DDR_SDQS2

DDR_SDM2

DDR_SDQS#4

DDR_SDQS4

DDR_SDM4 DDR_SDQS#6

DDR_SDQS6

DDR_SDM6

DDR_A_BS1 DDR_A_BS1

DDR_A_BS1 DDR_A_BS1

M_ODT0

DDR_SDM0

DDR_SDQS#0

DDR_SDQS0

DDR_SDQ0

DDR_SDQ2

DDR_SDQ1

DDR_SDQ5

DDR_SDQ4

DDR_SDQ7

DDR_SDQ3

DDR_SDQ6

DDR_SDQ16

DDR_SDQ17

DDR_SDQ18

DDR_SDQ19

DDR_SDQ20

DDR_SDQ22

DDR_SDQ23

DDR_SDQ21

DDR_SDQ32

DDR_SDQ33

DDR_SDQ34

DDR_SDQ35

DDR_SDQ36

DDR_SDQ37

DDR_SDQ38

DDR_SDQ39 DDR_SDQ48

DDR_SDQ49

DDR_SDQ50

DDR_SDQ51

DDR_SDQ52

DDR_SDQ53

DDR_SDQ54

DDR_SDQ55

+1.8V_SUS +1.8V_SUS

+1.8V_SUS +1.8V_SUS+1.8V_SUS

DDR_A_D[0..63]<11,15>

DDR_A_DQS[0..7]<11,15>

DDR_A_MA[0..13]<11,17>

DDR_A_DQS#[0..7]<11,15>

DDR_SDQS#[0..7]<17>

DDR_SDQ[0..63]<17>

DDR_SDQS[0..7]<17>

V_DDR_MCH_REF<10,15,17,49> M_CLK_DDR0 <10,17>

M_CLK_DDR#0 <10,17>

M_ODT0 <10,17>

DDR_CKE0 <10,17>

DDR_A_BS0 <11,17>

DDR_A_WE# <11,17>

DDR_A_RAS# <11,17>

DDR_A_CAS# <11,17>

DDR_CS0# <10,17>

M_CLK_DDR1 <10,17>

M_CLK_DDR#1 <10,17>

DDR_A_BS1 <11,17>

DDR_A_DM[0..7]<11,15>

DDR_SDM[0..7]<17>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

DDRII-ON BOARD I

16 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Place clost to each VREF pin

Layout Note:

Place near U4,U5,U6,U7

RN42

10_0404_4P2R_5%~D

1 4

2 3

RN69

10_0404_4P2R_5%~D

1 4

2 3

C661

0.1U_0402_16V4Z~D

1

2

C660

0.1U_0402_16V4Z~D

1

2

C665

2700P_0402_50V7K~D

1

2

R572 10_0402_5%~D

1 2

RN59

10_0404_4P2R_5%~D

1 4

2 3

C160

0.1U_0402_16V4Z~D

1

2

U5

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C664

0.1U_0402_16V4Z~D

1

2

RN15

10_0404_4P2R_5%~D

1 4

2 3

R566 10_0402_5%~D

1 2

RN56

10_0404_4P2R_5%~D

1 4

2 3

RN33

10_0404_4P2R_5%~D

1 4

2 3

RN65

10_0404_4P2R_5%~D

1 4

2 3

RN51

10_0404_4P2R_5%~D

1 4

2 3

RN29

10_0404_4P2R_5%~D

1 4

2 3

R569 10_0402_5%~D

1 2

RN68

10_0404_4P2R_5%~D

1 4

2 3

C656

2.2U_0603_6.3V6K~D

1

2

RN38

10_0404_4P2R_5%~D

1 4

2 3

C672

2700P_0402_50V7K~D

1

2

C667

2700P_0402_50V7K~D

1

2

R570 10_0402_5%~D

1 2

RN36

10_0404_4P2R_5%~D

1 4

2 3

C662

0.1U_0402_16V4Z~D

1

2

RN48

10_0404_4P2R_5%~D

1 4

2 3

RN32

10_0404_4P2R_5%~D

1 4

2 3

RN57

10_0404_4P2R_5%~D

1 4

2 3

C669

2700P_0402_50V7K~D

1

2

RN45

10_0404_4P2R_5%~D

1 4

2 3

R567 10_0402_5%~D

1 2

RN27

10_0404_4P2R_5%~D

1 4

2 3

RN47

10_0404_4P2R_5%~D

1 4

2 3

C159

0.1U_0402_16V4Z~D

1

2

RN62

10_0404_4P2R_5%~D

1 4

2 3

RN24

10_0404_4P2R_5%~D

1 4

2 3

RN54

10_0404_4P2R_5%~D

1 4

2 3

RN18

10_0404_4P2R_5%~D

1 4

2 3

C158

2.2U_0603_6.3V6K~D

1

2

RN20

10_0404_4P2R_5%~D

1 4

2 3

RN35

10_0404_4P2R_5%~D

1 4

2 3

C658

2.2U_0603_6.3V6K~D

1

2

RN41

10_0404_4P2R_5%~D

1 4

2 3

RN17

10_0404_4P2R_5%~D

1 4

2 3

U4

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C654

2.2U_0603_6.3V6K~D

1

2

C671

2700P_0402_50V7K~D

1

2

RN26

10_0404_4P2R_5%~D

1 4

2 3

U6

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

RN21

10_0404_4P2R_5%~D

1 4

2 3

RN39

10_0404_4P2R_5%~D

1 4

2 3

R568 10_0402_5%~D

1 2

C670

2700P_0402_50V7K~D

1

2

RN66

10_0404_4P2R_5%~D

1 4

2 3

RN44

10_0404_4P2R_5%~D

1 4

2 3

C157

0.1U_0402_16V4Z~D

1

2

R573 10_0402_5%~D

1 2

RN23

10_0404_4P2R_5%~D

1 4

2 3

C668

2700P_0402_50V7K~D

1

2

RN30

10_0404_4P2R_5%~D

1 4

2 3

RN19

10_0404_4P2R_5%~D

1 4

2 3

RN63

10_0404_4P2R_5%~D

1 4

2 3

RN60

10_0404_4P2R_5%~D

1 4

2 3

RN53

10_0404_4P2R_5%~D

1 4

2 3

C663

0.1U_0402_16V4Z~D

1

2

R571 10_0402_5%~D

1 2

RN14

10_0404_4P2R_5%~D

1 4

2 3

C655

2.2U_0603_6.3V6K~D

1

2

RN50

10_0404_4P2R_5%~D

1 4

2 3

C629

0.1U_0402_16V4Z~D

1

2

C659

0.1U_0402_16V4Z~D

1

2

C657

2.2U_0603_6.3V6K~D

1

2

U7

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C666

2700P_0402_50V7K~D

1

2

RN16

10_0404_4P2R_5%~D

1 4

2 3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_SCLK

CLK_SDATA

M_CLK_DDR0

DDR_A_MA10

DDR_A_WE#

DDR_A_MA0

DDR_A_MA1

DDR_A_MA3

DDR_A_MA8

DDR_A_BS0

DDR_CS0#

DDR_A_CAS#

DDR_A_BS1

DDR_A_MA12

DDR_A_MA7

DDR_A_MA6

DDR_A_MA5

DDR_A_MA4

DDR_A_MA2

DDR_A_MA9

M_CLK_DDR#0

DDR_A_MA11

DDR_A_RAS#

DDR_CS0#

DDR_CKE0

M_CLK_DDR#0

M_CLK_DDR0

M_ODT0

DDR_A_BS0

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

V_DDR_MCH_REF

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

V_DDR_MCH_REF

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_CKE0

M_CLK_DDR#0

M_CLK_DDR0

M_ODT0

DDR_A_BS0

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

V_DDR_MCH_REF

DDR_A_MA13

M_CLK_DDR#1

M_CLK_DDR#1

M_ODT0

DDR_A_BS0

M_CLK_DDR1

M_CLK_DDR1

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

DDR_SDQS1

DDR_SDQS#1

DDR_SDM1

DDR_SDQS#3

DDR_SDQS3

DDR_SDM3

DDR_SDQ40

DDR_SDQ41

DDR_SDQ42

DDR_SDQ43

DDR_SDQ44

DDR_SDQ45

DDR_SDQ46

DDR_SDQ47

DDR_SDQS#5

DDR_SDQS5

DDR_SDM5

DDR_SDQ56

DDR_SDQ57

DDR_SDQ58

DDR_SDQ59

DDR_SDQ60

DDR_SDQ61

DDR_SDQ62

DDR_SDQ63

DDR_SDQS#7

DDR_SDQS7

DDR_SDM7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

V_DDR_MCH_REF

DDR_A_MA13

M_CLK_DDR#1

M_CLK_DDR1

M_ODT0

DDR_A_BS0

DDR_CS0#

DDR_A_WE#

DDR_A_CAS#

DDR_A_RAS#

DDR_A_BS1 DDR_A_BS1

DDR_A_BS1DDR_A_BS1

M_ODT0

DDR_CKE0 DDR_CKE0

DDR_CKE0

DDR_SDQ8

DDR_SDQ9

DDR_SDQ10

DDR_SDQ11

DDR_SDQ12

DDR_SDQ13

DDR_SDQ14

DDR_SDQ15

DDR_SDQ25

DDR_SDQ24

DDR_SDQ26

DDR_SDQ27

DDR_SDQ28

DDR_SDQ29

DDR_SDQ30

DDR_SDQ31

+0.9V_DDR_VTT

+0.9V_DDR_VTT

+3.3V_RUN

+3.3V_RUN

+1.8V_SUS +1.8V_SUS

+1.8V_SUS +1.8V_SUS

+1.8V_SUS DDR_SDQS#[0..7]<16>

DDR_SDQ[0..63]<16>

DDR_SDQS[0..7]<16>

DDR_A_MA[0..13]<11,16>

DDR_A_WE#<11,16>

DDR_A_BS0<11,16>

DDR_CS0#<10,16>

DDR_A_CAS# <11,16>

DDR_A_BS1<11,16>

DDR_A_RAS# <11,16>

DDR_CS0# <10,16>

M_CLK_DDR0 <10,16>

M_CLK_DDR#0 <10,16>

DDR_CKE0 <10,16>

M_ODT0 <10,16>

DDR_A_BS0 <11,16>

DDR_A_WE# <11,16>

DDR_A_RAS# <11,16>

DDR_A_CAS# <11,16>

V_DDR_MCH_REF<10,15,16,49>

M_CLK_DDR#1 <10,16>

M_CLK_DDR1 <10,16>

DDR_A_BS1 <11,16>

M_ODT0<10,16>

DDR_CKE0 <10,16>

DDR_SDM[0..7]<16>

CLK_SDATA<6,15> CLK_SCLK<6,15>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

DDRII-ON BOARD II

17 59Friday, May 12, 2006

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Layout Note:

Place near U8,U9,U10,U11

Layout Note:

Place one cap close to every 2 pullup

resistors terminated to +0.9V_DDR_VTT

Layout Note:

Place these resistor

closely DIMM0,all

trace length

Max=1.3"

Layout Note:

Place these resistor

closely DIMM0,all

trace length<750 mil

Place clost to each VREF pin

C180

0.1U_0402_16V4Z~D

1

2

C165

2.2U_0603_6.3V6K~D

1

2

C179

0.1U_0402_16V4Z~D

1

2

C188

3.3P_0402_50VJ~D

1

2

RN74

56_0404_4P2R_5%~D

1 4

2 3

C175

0.1U_0402_16V4Z~D

1

2

C174

3.3P_0402_50VJ~D

1

2

C168

0.1U_0402_16V4Z~D

1

2

C172

0.1U_0402_16V4Z~D

1

2

C167

0.1U_0402_16V4Z~D

1

2

C677

2700P_0402_50V7K~D

1

2

RN73

56_0404_4P2R_5%~D

14 23

C682

2700P_0402_50V7K~D

1

2

C169

0.1U_0402_16V4Z~D

1

2

C166

0.1U_0402_16V4Z~D

1

2

R625

56_0402_5%~D

12

RN72

56_0404_4P2R_5%~D

1 4

2 3

C674

0.1U_0402_16V4Z~D

1

2

C176

0.1U_0402_16V4Z~D

1

2

RN71

56_0404_4P2R_5%~D

14 23

U10

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C630

0.1U_0402_16V4Z~D

1

2

U9

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

R140 10K_0402_5%~D@12

C161

2.2U_0603_6.3V6K~D

1

2

C163

2.2U_0603_6.3V6K~D

1

2

R138

200_0402_5%~D

12

C675

2700P_0402_50V7K~D

1

2

R137

200_0402_5%~D

12

RN79

56_0404_4P2R_5%~D

14 23

EEPROM

U12

24LC256T-I/ST_TSSOP8~D@

SA0

1

SA1

2

SA2

3GND 4

WP

7

SCL

6

SDA

5VDD 8

C673

0.1U_0402_16V4Z~D

1

2

R576

200_0402_5%~D

12

U8

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C676

2700P_0402_50V7K~D

1

2

C183

0.1U_0402_16V4Z~D

1

2

R139

10K_0402_5%~D

@

12

C681

2700P_0402_50V7K~D

1

2

C178

0.1U_0402_16V4Z~D

1

2

C184

0.1U_0402_16V4Z~D

1

2

C171

2.2U_0603_6.3V6K~D

1

2

C170

0.1U_0402_16V4Z~D

1

2

RN70

56_0404_4P2R_5%~D

1 4

2 3

RN78

56_0404_4P2R_5%~D

1 4

2 3

C173

0.1U_0402_16V4Z~D

1

2

RN77

56_0404_4P2R_5%~D

14 23

C189

0.1U_0402_16V4Z~D

@

1

2

C162

2.2U_0603_6.3V6K~D

1

2

RN75

56_0404_4P2R_5%~D

14 23

U11

K4T51083QC-ZCLD5_FBGA60~D

DQS#

A8

DM/RDQS

B3

DQ0

C8

DQ1

C2

DQ2

D7

DQ3

D3

DQ4

D1

DQ5

D9

DQ6

B1

DQ7

B9

DQS

B7 VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VREF

E2

A0

H8

A1

H3

A2

H7

A3

J2

A4

J8

A5

J3

A6

J7

A7

K2

A8

K8

A9

K3

A10

H2

A11

K7

A12

L2

A13

L8

NC

G1

NC

L3

NC

L7

VDD A1

VDD E9

VDD H9

VDD L1

VDDL E1

ODT F9

CK E8

CK# F8

CKE F2

BA0 G2

BA1 G3

CS# G8

RAS# F7

CAS# G7

WE# F3

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSS E3

VSS J1

VSS K9

VSSDL E7

VSS A3

NU/RDQS

A2

C182

0.1U_0402_16V4Z~D

1

2

R577

200_0402_5%~D

12

C186

0.1U_0402_16V4Z~D

1

2

R141 10K_0402_5%~D@12

C679

2700P_0402_50V7K~D

1

2

C678

2700P_0402_50V7K~D

1

2

C181

0.1U_0402_16V4Z~D

1

2

C164

2.2U_0603_6.3V6K~D

1

2

RN81

56_0404_4P2R_5%~D

14 23

C680

2700P_0402_50V7K~D

1

2

C177

0.1U_0402_16V4Z~D

1

2

C185

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+FAN1_VOUT

THERMATRIP1#

THERMATRIP2#

REM_DIODE1_P

REM_DIODE1_N

FAN1_TACH

THERMATRIP3#

THERMATRIP2#

+3VSUS_THRM

THERMATRIP1#

LDO_SET

+3V_LDOIN

REM_DIODE3_N

REM_DIODE3_P

+FAN1_VOUT

SNIFFER_GREEN#

SNIFFER_YELLOW#

LDO_SET

+3.3V_ALW

+RTC_CELL

+5V_RUN

+RTC_CELL

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+2.5V_RUN

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS +3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+2.5V_RUN

FAN1_TACH <40>

ATF_INT# <40>

THERMTRIP_SIO <39>

THERMTRIP_MCH#<10>

H_THERMTRIP#<7>

DAT_SMB<33,40>

H_THERMDA<7>

H_THERMDC<7>

SUSPWROK<24,43>

POWER_SW#<38,40,44>

ICH_PWRGD#<43>

ACAV_IN <40,51>

THERM_STP# <47>

SNIFFER_GREEN#<44> SNIFFER_YELLOW#<44>

2.5V_RUN_PWRGD <43>

CLK_SMB<33,40>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

FAN & Thermal Sensor

18 59Friday, May 12, 2006

Compal Electronics, Inc.

FAN1 Control and Tachometer

Place under CPU

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SMBUS ADDRESS : 2F

Place cap close to the

Guardian pins as possible.

REM_DIODE3_N, REM_DIODE3_P routing together.

Trace width / Spacing = 10 / 10 mil

Place near the bottom SODIMM

Place C341 close to the Guardian

pins as possible

Place C197 close to the Guardian

pins as possible

Use Rev:C

Need create P/N

For Vmargin pop R578 and

R158=30K,R158=1K for production.

SET local temperature on M/B

VSET=(Tp-70)/21

=3.3V*R157/(R152+R157)

=1.044

Tp=92 degree

C207

0.1U_0402_16V4Z~D

@

1

2

C191

22U_0805_6.3V6M~D

1

2

R159

2.2K_0402_5%~D

1 2

C200

2200P_0402_50V7K~D

1

2

R158

1K_0603_5%~D

12

R148 1K_0402_5%~D

1 2

C203

0.1U_0402_16V4Z~D

@

1

2

R151 8.2K_0402_5%~D

1 2

R145 7.5K_0402_5%~D

1 2

C193

2200P_0402_50V7K~D

1

2

C209

0.1U_0402_16V4Z~D

1

2

E

B

C

Q8 MMST3904-7-F_SOT323~D

2

31

R152

147K_0402_1%~D

12

R149

2.2K_0402_5%~D

1 2

R144

49.9_0603_1%~D

1 2

R154

8.2K_0402_5%~D

12

C198

2200P_0402_50V7K~D

@

1

2

R143

10K_0402_5%~D

12

R146

8.2K_0402_5%~D

12

C205

2200P_0402_50V7K~D

@

1

2

R142

10K_0402_5%~D

12

C201

0.1U_0402_16V4Z~D

1

2

EB

C

Q6

MMST3904-7-F_SOT323~D

2

31

JFAN1

MOLEX_53780-0370~D

1

1

2

2

3

3

GND 4

GND 5

R157

68K_0402_1%~D

12

C196

0.1U_0402_16V4Z~D

1

2

E

B

C

Q7

MMST3904-7-F_SOT323~D

2

3 1

C195

0.1U_0402_16V4Z~D

1

2

R160 0.27_1210_5%~D

12

R153

10K_0402_5%~D

12

E

B

C

Q5

MMST3904-7-F_SOT323~D

2

3 1

C202

10U_0805_6.3V6M~D

1

2

R147

10K_0402_5%~D

12

C194

0.1U_0402_16V4Z~D

1

2

C190

100P_0402_50V8J~D

@

1

2

R155

1K_0402_5%~D

1 2

C208

10U_0805_10V4Z~D

1

2

U13

EMC4000_QFN40~D

SMDATA

7

SMBCLK

8

LDO_SHDN#_ADDR

23

DP2

35

DN2

34

+3V_SUS

12

VSUS_PWRGD

21

+RTC_PWR3V

18

+3V_PWROK#

13

POWER_SW#

38

THERMTRIP1#

14

THERMTRIP2#

15

THERMTRIP3#

16

VSET

39

HW_LOCK#

29

VSS

9

ATF_INT# 17

VCP 3

LDO_POK 31

DN1 36

DP1 37

THERMTRIP_SIO 30

ACAV_CLR 4

SYS_SHDN# 22

DP3

1

DN3

2

VDD_5V 5

FAN_OUT

6

GPIO1

10

GPIO2

11

GPIO3

19

GPIO4

20

LDO_SET 24

LDO_OUT 25

LDO_IN 26

LDO_OUT 27

LDO_IN 28

GPIO5

32

FAN_DAC

33

VCP 40

THERMAL PAD 41

D3

RB751S40T1_SOD523-2~D

@

2 1

C206

1U_0603_10V4Z~D

1

2

C192

22U_0805_6.3V6M~D

@

1

2

R578

31.6K_0402_1%~D

@

12

R150 1K_0402_5%~D

1 2

R156

10K_0402_5%~D

@

12

C197

2200P_0402_50V7K~D

1

2

C204

2200P_0402_50V7K~D

1

2

C199

0.1U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCD_TST

LCD_DDCCLK

LCD_DDCDATA

LCD_A1-

LCD_A0+

LCD_A2-

LCD_A0-

LCD_A2+

LCD_A1+

LCD_ACLK+

LCD_ACLK-

FPBACK_EN BIA_PWM

PANEL_BKEN

LAMP_STAT#

LAMP_D_STAT#

BIA_PWM

+LCDVDD

+PWR_SRC

+5V_ALW

+LCDVDD

+LCDVDD

+15V_SUS

+GFX_PWR_SRC +GFX_PWR_SRC

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN+15V_SUS

SBAT_SMBDAT <40>

RUN_ON<40,42,43,47,48,49>

LCD_TST <24>

LCD_A0- <12>

LCD_A0+ <12>

LCD_A1- <12>

LCD_A1+ <12>

LCD_A2- <12>

LCD_A2+ <12>

LCD_ACLK- <12>

LCD_ACLK+ <12>

ENVDD<12>

FPBACK_EN<39>

PANEL_BKEN<12>

BIA_PWM <12,40>

LCD_DDCDATA <12>

LCD_DDCCLK <12>

SBAT_SMBCLK <40>

LAMP_STAT# <24>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Internal LVDS

19 59Friday, May 12, 2006

Compal Electronics, Inc.

FDS4435: P CHANNAL

40mil

40mil

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

M'07 inverter support - Populate Ra,U54 Depop Ua.

D'05 inverter support - Populate Ua, Depop Ra,U54

M00 support D05 inverter

Ra Ua

M'07 inverter support - Depop D19.

D'05 inverter support - Populate D19

C216

0.1U_0603_50V4Z~D

1

2

S

G

D

Q9

SI3456DV-T1-E3_TSOP6~D

3

6

2

4 5

1

R166 0_0402_5%~D

1 2

C212

0.1U_0402_16V4Z~D

1

2

R165

200K_0402_5%~D

12

Q13

FDS4435_NL_SO8~D

4

7

8

6

5

1

2

3

D19

RB751S40T1_SOD523-2~D

@

21

JP1

I-PEX_20143-030E-20F~D

29 29

27 27

25 25

23 23

21 21

19 19

16 16

15 15

13 13

11 11

99

77

22

44

55

30 30

28 28

26 26

24 24

22 22

20 20

18 18

17 17

14 14

12 12

10 10

88

66

11

33

MGND1

31

MGND2

32

MGND3

33

MGND4

34

R163

470_0402_5%~D

12

C215

0.1U_0603_50V4Z~D

1

2

G

D

S

Q11

2N7002W-7-F_SOT323~D

2

13

C217

1000P_0402_50V7K~D

1

2

C210

0.1U_0402_16V4Z~D

1

2

R162

100K_0402_5%~D

12

R161

100K_0402_5%~D

12

C211

0.1U_0603_50V4Z~D

1

2

G

D

S

Q14

2N7002W-7-F_SOT323~D

2

1 3

C213

0.1U_0402_16V4Z~D

1

2

Q12

DDTC124EUA-7-F_SOT323~D

I

2

O1

G

3

U14

SN74AHC1G08DCKR_SC70-5~D

@

IN1

1

IN2

2

G

3

O4

P5

C214

0.1U_0402_16V4Z~D

1

2

G

D

S

Q10

2N7002W-7-F_SOT323~D

2

13

R168

100K_0402_5%~D

12

R167

100K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDVOB_GREEN+

DVI_TX2+

SDVOB_BLUE+

INT-

SDVOB_RED-

DVI_TX2-

+VSWING

DVI_SCLK

DVI_TX1-

DVI_TX0-

DVI_CLK+

SDVOB_BLUE-

DVI_TX1+

DVI_CLK-

SDVOB_GREEN-

DVI_TX0+

INT+

DVI_SDATA

SDVOB_RED+

SDVO_CTRLCLK

SDVO_CTRLDATA

DVI_TX2+

DVI_TX2-

DVI_TX1+

DVI_TX1-

DVI_TX0+

DVI_TX0-

DVI_CLK+

DVI_CLK-

+SPVCC_TMDS

+PVCC1_TMDS

+VCC_TMDS

+SVCC_TMDS

+PVCC2_TMDS

+1.8V_RUN

+AVCC_TMDS

+1.8V_RUN

+AVCC_TMDS+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+5V_RUN

+2.5V_RUN

SDVOB_BLUE+<12>

SDVOB_INT+<12> SDVOB_INT-<12>

SDVOB_RED+<12> SDVOB_RED-<12>

PLTRST#<10,22,24,29,36>

SDVOB_CLK+<12>

SDVOB_GREEN+<12>

SDVOB_CLK-<12>

SDVOB_GREEN-<12>

DVI_DETECT<38>

SDVOB_BLUE-<12>

SDVO_CTRLDATA <12>

DVI_SDATA <38>

DVI_TX2+ <38>

DVI_TX2- <38>

DVI_TX1+ <38>

DVI_TX1- <38>

DVI_TX0- <38>

DVI_TX0+ <38>

DVI_CLK- <38>

DVI_CLK+ <38>

DVI_SCLK <38>

SDVO_CTRLCLK <12>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Internal LVDS

20 59Friday, May 12, 2006

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

A1 LOW: Address = 0x70

HIGH: Address = 0x72

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

180ohm,1500mA,0.09ohm

C224

10U_0805_10V4Z~D

1

2

L16

BLM18PG181SN1_0603~D

12

R175 220_0402_5%~D

12

C237

100P_0402_50V8J~D

@

1

2

C240

10U_0805_10V4Z~D

1

2

C225

10U_0805_10V4Z~D

1

2

R178

1K_0402_5%~D

12

C246

100P_0402_50V8J~D

@

1

2

L13

BLM18PG181SN1_0603~D

12

C231

10U_0805_10V4Z~D

1

2

C241

0.1U_0402_16V4Z~D

1

2

C245

10U_0805_10V4Z~D

1

2

C235

0.1U_0402_16V4Z~D

1

2

C243

0.1U_0402_16V4Z~D

1

2

C249 0.1U_0402_16V4Z~D

1 2

C244 0.1U_0402_16V4Z~D

1 2

C220

0.1U_0402_16V4Z~D

12

R180

4.7K_0402_5%~D

12

R171

110_0402_1%~D

1 2

C239

0.1U_0402_16V4Z~D

1

2

R170

110_0402_1%~D

1 2

C226

100P_0402_50V8J~D

@

1

2

L17

BLM18PG181SN1_0603~D

12

C228

0.1U_0402_16V4Z~D

1

2

L15

BLM18PG181SN1_0603~D

12

R174

2.2K_0402_5%~D

12

C242

0.1U_0402_16V4Z~D

1

2

R176 1K_0402_5%~D@ 1 2

R173

2.2K_0402_5%~D

12

R179

4.7K_0402_5%~D

12

C230

0.1U_0402_16V4Z~D

1

2

C248

0.1U_0402_16V4Z~D

1

2

C218

0.1U_0402_16V4Z~D

12

L14

BLM18PG181SN1_0603~D

12

L12

BLM18PG181SN1_0603~D

12

C223

0.1U_0402_16V4Z~D

1

2

C221

0.1U_0402_16V4Z~D

12 R172

110_0402_1%~D

1 2

C238

1000P_0402_50V7K~D

1

2

U15

SII1362CLU_LQFP48~D

HTPLG

29

PGND2

27

SDI+

32

SDI-

33

EXT_RES

35

SDADDC 9

SCLDDC 8

SDSCL 5

SDSDA 4

SDR+

37

SDR-

38

SDG+

40

SDG-

41

SDB+

43

SDB-

44

SDC+

46

SDC-

47

SPGND

3

RESET#

2

PVCC2 26

EXT_SWING

25

PVCC1 11

VCC 10

VCC 34

AGND

12

VCC 28

OVCC 1

AVCC 15

AVCC 21

SVCC 36

SVCC 42

SPVCC 48

GND

7

TEST

30

GND

31

SGND

39

SGND

45

AGND

18

AGND

24

A1 6

TXC- 13

TXC+ 14

TX0- 16

TX0+ 17

TX1- 19

TX1+ 20

TX2- 22

TX2+ 23

C227

1000P_0402_50V7K~D

@

1

2

C222

0.1U_0402_16V4Z~D

1

2

R169

110_0402_1%~D

1 2

C219

0.1U_0402_16V4Z~D

12

C247

1000P_0402_50V7K~D

1

2

R177

1K_0402_5%~D

1 2

C229

0.1U_0402_16V4Z~D

1

2

C232

10U_0805_10V4Z~D

1

2

C233

1000P_0402_50V7K~D

@

1

2

C236

10U_0805_10V4Z~D

1

2

C234

100P_0402_50V8J~D

@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VGA_GRN

VGA_BLU

CLK_DDC2

+CRT_VCC

VGA_HSYNC_B

VGA_VSYNC_B

JVGA_HS

BLUE

RED

GREEN

JVGA_VS

VGA_RED

M_ID2#

DAT_DDC2

+CRT_VCC

+CRT_VCC

+3.3V_RUN

+CRT_VCC

+5V_RUN

VGA_RED<12,38>

VGA_VSYNC<12>

VGA_GRN<12,38>

VGA_BLU<12,38>

VGA_HSYNC<12>

DAT_DDC2<12,38>

VSYNC_R <38>

HSYNC_R <38>

CLK_DDC2<12,38>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

CRT Connector

21 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

K1 A2

A1 K2

DA204U

22ohm,500mA,0.1ohm

120ohm,600mA,0.25ohm

120ohm,600mA,0.25ohm

22ohm,500mA,0.1ohm

22ohm,500mA,0.1ohm

C254

10P_0402_50V8J~D

@

1

2

L19

BLM18BB220SN1D_0603~D

1 2

D6

DA204U_SOT323~D

@

2

31

L18

BLM18BB220SN1D_0603~D

1 2

C258

22P_0402_50V8J~D

1

2

R650

0_0402_5%~D

1 2

R649

0_1206_5%~D

12

C250

22P_0402_50V8J~D

@

1

2

D4

DA204U_SOT323~D

@

2

31

C257

22P_0402_50V8J~D

1

2

U16

SN74AHCT1G125GW_SOT-353~D

A

2Y4

P5

G

3

OE# 1

R181

150_0402_1%~D

12

R185

1K_0402_5%~D

@

12

R183

150_0402_1%~D

12

R190

39_0402_5%~D

1 2

C637

0.1U_0402_16V4Z~D

1

2

L21

BLM11A121S_0603~D

1 2

JCRT1

SUYIN_070546FR015S2307R~D

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

16

17

C252

22P_0402_50V8J~D

@

1

2

C255

10P_0402_50V8J~D

@

1

2

U17

SN74AHCT1G125GW_SOT-353~D

A

2Y4

P5

G

3

OE# 1

R186

2.2K_0402_5%~D

1 2

R184

1K_0402_5%~D

@

12

R188

1K_0402_5%~D

1 2

C253

10P_0402_50V8J~D

@

1

2

D7

RB751S40T1_SOD523-2~D

21

R651

0_0402_5%~D

1 2

R189

39_0402_5%~D

1 2

C251

22P_0402_50V8J~D

@

1

2

L22

BLM11A121S_0603~D

1 2

L20

BLM18BB220SN1D_0603~D

1 2

T12 PAD~D

C256

0.01U_0402_16V7K~D

1

2

R182

150_0402_1%~D

12

R187

2.2K_0402_5%~D

1 2

D5

DA204U_SOT323~D

@

2

31

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PCI_ICH

PCI_SERR#

PCI_DEVSEL#

PCI_PCIRST#

PCI_C_BE0#

PCI_REQ4#

PCI_PERR#

PCI_GNT4#

ICH_GPIO4_PIRQG#

PCI_PIRQB#

PCI_REQ5#

PCI_STOP#

PCI_C_BE1#

PCI_C_BE3#

ICH_GPIO3_PIRQF#

PCI_PIRQC#

PCI_REQ2#

ICH_GPIO2_PIRQE#

PCI_FRAME#

PCI_REQ3#

PCI_PLOCK#

PCI_IRDY#

PCI_C_BE2#

PCI_REQ1#

PCI_REQ0#

PCI_PIRQD#

PCI_PIRQA#

PCI_PAR

PCI_TRDY#

ICH_GPIO5_PIRQH#

PCI_PLTRST#

CLK_PCI_ICH

ICH_PME#

PCI_AD0

PCI_AD1

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD5

PCI_AD7

PCI_AD6

PCI_AD8

PCI_AD9

PCI_AD11

PCI_AD10

PCI_AD14

PCI_AD15

PCI_AD13

PCI_AD12

PCI_AD16

PCI_AD17

PCI_AD19

PCI_AD18

PCI_AD22

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD25

PCI_AD24

PCI_AD28

PCI_AD29

PCI_AD31

PCI_AD30

PCI_AD26

PCI_AD27

PCI_TRDY#

PCI_DEVSEL#

PCI_STOP#

PCI_FRAME#

PCI_IRDY#

PCI_PLOCK#

PCI_SERR#

PCI_PERR#

PCI_PIRQC#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQD#

ICH_GPIO5_PIRQH#

ICH_GPIO4_PIRQG#

ICH_GPIO3_PIRQF#

ICH_GPIO2_PIRQE#

PCI_REQ0#

PCI_REQ2#

PCI_REQ3#

PCI_REQ4#

PCI_REQ5#

PCI_REQ1#

PCI_GNT5#

PCI_GNT0#

PCI_GNT5# PCI_GNT4#

PLTRST2#

PCI_GNT2#

PLTRST#

PCI_PLTRST#

PCI_RST#

PCI_PCIRST#

+3.3V_RUN

+3.3V_RUN

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

PCI_C_BE1# <31,37>

PCI_SERR# <31,37>

PCI_PAR <31,37>

PCI_IRDY# <31,37,38>

PCI_PERR# <31,37>

PCI_PIRQC#<31>

PCI_C_BE3# <31,37>

PCI_FRAME# <31,37,38>

PCI_C_BE2# <31,37>

PCI_DEVSEL# <31,37>

PCI_TRDY# <31,37>

PCI_C_BE0# <31,37>

PCI_STOP# <31,37>

PCI_AD[0..31]<31,37>

ICH_PME# <39>

PCI_RST# <31,35,37>

PLTRST# <10,20,24,29,36>

MCH_ICH_SYNC# <10>

PCI_PIRQA#<37>

PCI_REQ0# <38>

PCI_PLOCK# <37>

PCI_GNT0# <37,38>

PLTRST2# <39,40>

PCI_PIRQB#<31>

PCI_PIRQD#<31>

PCI_GNT2# <31>

PCI_REQ2# <31>

CLK_PCI_ICH <6>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

ICH7(1/4)

22 59Friday, May 12, 2006

Compal Electronics, Inc.

Place closely pin U45.A9

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

LPC

PCI

SPI

GNT5#

R214 GNT4#

R213

(11)

(10)

(01)

unstuff unstuff

unstuff

unstuff stuff

stuff *

U18C

74VHC08MTCX_NL_TSSOP14~D

IN1

10

IN2

9OUT 8

P14

G

7

R196 8.2K_0402_5%~D

1 2

R212

1K_0402_5%~D

12

R204 8.2K_0402_5%~D

1 2

R192 8.2K_0402_5%~D

1 2

Interrupt I/F

PCI

MISC

U19B

82801GHM SL8YB B0_BGA652~D

FRAME# F16

GPIO17 / GNT5# D8

TRDY# F14

STOP# F15

GPIO2 / PIRQE# G8

GPIO3 / PIRQF# F7

GPIO4 / PIRQG# F8

GPIO5 / PIRQH# G7

C/BE0# B15

C/BE1# C12

C/BE2# D12

C/BE3# C15

IRDY# A7

PAR E10

PCIRST# B18

DEVSEL# A12

PERR# C9

PLOCK# E11

SERR# B10

PIRQC#

C5

RSVD[4]

AH4

PIRQA#

A3

RSVD[5]

AD9

RSVD[2]

AD5

RSVD[3]

AG4

PIRQB#

B4

PIRQD#

B5

RSVD[1]

AE5

REQ0# D7

GNT0# E7

REQ1# C16

GNT1# D16

REQ2# C17

GNT2# D17

REQ3# E13

GNT3# F13

REQ4# / GPIO22 A13

GNT4# / GPIO48 A14

GPIO1 / REQ5# C8

AD0

E18

AD1

C18

AD2

A16

AD3

F18

AD4

E16

AD5

A18

AD6

E17

AD7

A17

AD8

A15

AD9

C14

AD10

E14

AD11

D14

AD12

B12

AD13

C13

AD14

G15

AD15

G13

AD16

E12

AD17

C11

AD18

D11

AD19

A11

AD20

A10

AD21

F11

AD22

F10

AD23

E9

AD24

D9

AD25

B9

AD26

A8

AD27

A6

AD28

C7

AD29

B6

AD30

E6

AD31

D6

RSVD[6] AE9

RSVD[7] AG8

RSVD[8] AH8

RSVD[9] F21

MCH_SYNC# AH20

PLTRST# C26

PCICLK A9

PME# B19

R193 8.2K_0402_5%~D

1 2

U18B

74VHC08MTCX_NL_TSSOP14~D

IN1

4

IN2

5OUT 6

P14

G

7

R194 8.2K_0402_5%~D

1 2

R214 8.2K_0402_5%~D

1 2

R195 8.2K_0402_5%~D

1 2

R198 8.2K_0402_5%~D

1 2

U18D

74VHC08MTCX_NL_TSSOP14~D

IN1

13

IN2

12 OUT 11

P14

G

7

R206 8.2K_0402_5%~D

1 2

R211 8.2K_0402_5%~D

1 2

R191 8.2K_0402_5%~D

1 2

R202 8.2K_0402_5%~D

1 2

R209 8.2K_0402_5%~D

1 2

R197 8.2K_0402_5%~D

1 2

R201 8.2K_0402_5%~D

1 2

R210

10_0402_5%~D

@

1 2

R213

1K_0402_5%~D

@

12

R200 8.2K_0402_5%~D

1 2

C259

8.2P_0402_50V8J~D

@

1

2

R208 8.2K_0402_5%~D

1 2

R203 8.2K_0402_5%~D

1 2

U18A

74VHC08MTCX_NL_TSSOP14~D

IN1

1

IN2

2OUT 3

P14

G

7

R207 8.2K_0402_5%~D

1 2

R205 8.2K_0402_5%~D

1 2

R199 8.2K_0402_5%~D

1 2

R215 8.2K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDE_DDREQ

H_A20M#

H_INIT#

H_IGNNE#

H_INTR

H_NMI

H_STPCLK#

H_FERR#

IDE_IRQ

H_DPRSTP#

IDE_DD9

IDE_DD2

IDE_DD15

IDE_DD0

IDE_DIOR#

DPRSLP#

LPC_LFRAME#

IDE_DA1

IDE_DD14

IDE_DA2

LPC_LDRQ1#

ICH_AZ_MDC_SDIN1

IDE_DD6

IDE_DA0

ICH_AC_SDOUT_R

IDE_DD13

IDE_DD10

IDE_DD8

IDE_DD1

IDE_DD7

IDE_DD4

LPC_LAD3

ICH_AC_RST_R#

IDE_IRQ

IDE_DD[0..15]

IDE_DD12

IDE_DD3

THRMTRIP_ICH#

IDE_DD5

SIO_RCIN#

LPC_LAD0

ICH_RTCRST#

IDE_DD11

IDE_DDACK#

ICH_AZ_CODEC_SDIN0

LPC_LDRQ0#

H_DPSLP#

SM_INTRUDER#

IDE_DIORDY

IDE_DSC1#

SM_INTRUDER#

ICH_AC_SYNC_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_SDOUT_R

H_CPUSLP#

H_CPUSLP_R#

SIO_A20GATE

H_PWRGOOD

H_SMI#

LPC_LAD2

IDE_DSC3#

H_FERR#

LPC_LAD1

ICH_INTVRMEN

ICH_AC_BITCLK_R

ICH_AC_BITCLK_R

SIO_A20GATE

SIO_RCIN#

IDE_DIOW#

ICH_RTCX1

ICH_RTCX2

+RTC_CELL

+RTC_CELL

+3.3V_RUN

+3.3V_RUN

+1.05V_VCCP

+1.05V_VCCP

IDE_DD[0..15] <26>

IDE_DIOR#<26> IDE_DIOW#<26>

ICH_AZ_MDC_SDIN1<34>

LPC_LAD[0..3] <29,39,40>

IDE_DA[0..2] <26>

H_INTR <7>

H_INIT# <7>

H_DPSLP# <7>

H_SMI# <7>

H_IGNNE# <7>

H_A20M# <7>

H_NMI <7>

H_STPCLK# <7>

H_CPUSLP# <7,10>

IDE_IRQ<26>

H_DPRSTP# <7,50>

H_PWRGOOD <7>

SIO_RCIN# <40>

IDE_DIORDY<26>

IDE_DSC1# <26>

SIO_A20GATE <40>

ICH_AZ_CODEC_SDIN0<27>

IDE_DSC3# <26>

ICH_AZ_CODEC_RST#<27>

ICH_AZ_CODEC_SYNC<27>

ICH_AZ_CODEC_SDOUT<27>

ICH_AZ_MDC_SYNC<34>

ICH_AZ_MDC_SDOUT<34>

ICH_AZ_MDC_BITCLK<34>

ICH_AZ_CODEC_BITCLK<27>

ICH_AZ_MDC_RST#<34>

IDE_DDACK#<26> IDE_DDREQ <26>

H_FERR# <7>

LPC_LFRAME# <29,39,40>

LPC_LDRQ0# <39>

LPC_LDRQ1# <39>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

ICH7(2/4)

23 59Friday, May 12, 2006

Compal Electronics, Inc.

Package

9.6X4.06 mm

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DPRSTP# daisy

Close to U19

ICH7-M --> IMVP6 -->Yonah

R226 56_0402_5%~D

1 2

CMOS1

@SHORT PADS~D

1

122

R233

33_0402_5%~D

1 2

C262

1U_0603_10V4Z~D

1 2

R584 10K_0402_5%~D

12

C263 27P_0402_50V8J~D@

12

R220 10K_0402_5%~D

12

R216

1M_0402_5%~D

12

R643 0_0402_5%~D

12

R222 0_0402_5%~D

12

R219

332K_0402_1%~D

1 2

Y2

32.768K_12.5PF_Q13MC30610003~D

14

23

R217

10M_0402_5%~D

12

R229

8.2K_0402_5%~D

12

R22533_0402_5%~D

1 2

R227

33_0402_5%~D

1 2

R22433_0402_5%~D

1 2

R232

33_0402_5%~D

1 2

RTC

LAN

SATA

AC-97/AZALIA

LPCCPU

IDE

U19A

82801GHM SL8YB B0_BGA652~D

RTCX1

AB1

RTCX2

AB2

RTCRST#

AA3

INTVRMEN

W4

INTRUDER#

Y5

EE_CS

W1

EE_SHCLK

Y1

EE_DOUT

Y2

EE_DIN

W3

LAN_CLK

V3

LAN_RSTSYNC

U3

LAN_RXD0

U5

LAN_RXD1

V4

LAN_RXD2

T5

LAN_TXD0

U7

LAN_TXD1

V6

LAN_TXD2

V7

ACZ_BCLK

U1

ACZ_SYNC

R6

ACZ_RST#

R5

ACZ_SDIN0

T2

ACZ_SDIN1

T3

ACZ_SDIN2

T1

ACZ_SDOUT

T4

SATALED#

AF18

SATA0RXN

AF3

SATA0RXP

AE3

SATA0TXN

AG2

SATA0TXP

AH2

SATA2RXN

AF7

SATA2RXP

AE7

SATA2TXN

AG6

SATA2TXP

AH6

SATA_CLKN

AF1

SATA_CLKP

AE1

SATARBIASN

AH10

SATARBIASP

AG10

IORDY

AG16

IDEIRQ

AH16

DDACK#

AF16

DIOW#

AH15

DIOR#

AF15

LAD0 AA6

LAD1 AB5

LAD2 AC4

LAD3 Y6

LDRQ0# AC3

LDRQ1# / GPIO23 AA5

LFRAME# AB3

A20GATE AE22

A20M# AH28

CPUSLP# AG27

TP1 / DPRSTP# AF24

TP2 / DPSLP# AH25

FERR# AG26

GPIO49 / CPUPWRGD AG24

IGNNE# AG22

INIT3_3V# AG21

INIT# AF22

INTR AF25

RCIN# AG23

SMI# AF23

NMI AH24

STPCLK# AH22

THERMTRIP# AF26

DA0 AH17

DA1 AE17

DA2 AF17

DCS1# AE16

DCS3# AD16

DD0 AB15

DD1 AE14

DD2 AG13

DD3 AF13

DD4 AD14

DD5 AC13

DD6 AD12

DD7 AC12

DD8 AE12

DD9 AF12

DD10 AB13

DD11 AC14

DD12 AF14

DD13 AH13

DD14 AH14

DD15 AC15

DDREQ AE15

R228

56_0402_5%~D

12

R218

20K_0402_5%~D

1 2

R221 0_0402_5%~D@12

R22333_0402_5%~D

1 2

C260

12P_0402_50V8J~D

12

R230

33_0402_5%~D

1 2

C261

12P_0402_50V8J~D

12

C264

27P_0402_50V8J~D

@

1

2

R231

33_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LINKALERT#

ICH_BATLOW#

ICH_PCIE_WAKE#

SIO_THRM#

IRQ_SERIRQ

CLKRUN# ICH_SMBDATA

USB_OC1#

SIO_THRM#

USBP5-

ICH_PCIE_WAKE#

USBP7-

CLK_PCIE_ICH#

USB_OC2#

USBP5+

CLK_ICH_48M

PM_BMBUSY#

CLK_ICH_14M

CLK_PCIE_ICH

PLTRST#

USBP4-

USBP6-

H_STP_CPU#

IMVP_PWRGD

SIO_SLP_S3#

ITP_DBRESET#

CLK_ICH_48M

CLK_ICH_14M

ICH_RI#

USBP6+

IRQ_SERIRQ

SIO_EXT_SMI#

SIO_SLP_S5#

USBP4+

USBP7+

SMBALERT#

USBRBIAS

DMI_IRCOMP

GPIO24

USB_OC0#

USB_OC3#

USB_OC1#

USB_OC2#

USB_OC5#

USB_OC7#

USB_OC6#

USB_OC7#

ICH_SMBCLK

SPKR

LINKALERT#

USB_OC4#

H_STP_PCI#

ICH_SMLINK0ICH_SMLINK0

ICH_SMLINK1 ICH_SMLINK1

SUSPWROK

ICH_BATLOW#

SIO_PWRBTN#

ICH_PWRGD

ICH_SUSCLK

PCIE_IRX_WLANTX_N2

PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_P2

SIO_EXT_WAKE#

SIO_EXT_SCI#

USBP1+

USBP1-

DMI_MTX_IRX_N0

DMI_MTX_IRX_N1

DMI_MTX_IRX_P0

DMI_MTX_IRX_P1

DMI_MRX_ITX_P0

DMI_MRX_ITX_P1

DMI_MRX_ITX_N0

DMI_MRX_ITX_N1

USBP0+

USBP0-

USB_OC0#

PCIE_IRX_WANTX_N1

PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_P1

PCIE_ITX_LOMRX_N3

PCIE_IRX_LOMTX_N3

PCIE_IRX_LOMTX_P3

PCIE_ITX_LOMRX_P3

USB_OC4#

USB_OC6#

LCD_TST

ICH_SPI_CLK

BT_RADIO_DIS#

WWAN_RADIO_DIS#

WWAN_RADIO_DIS#

ICH_EC_SPI_CLK

USB_OC5#

IDE_HRESET#

LAMP_STAT#

BT_RADIO_DIS#

DPRSLPVR

SMBALERT# DPRSLPVR

SIO_EXT_SCI#

SIO_EXT_SMI#

USB_OC3#

LAMP_STAT#

ICHI_ECI_SPIO_DATA ICHO_SPIIICHO_ECO_SPII_DATA

CLKRUN#

RSVD_HDDC_EN#

SPI_CS#

PCIE_ITX_WANRX_N1

PCIE_ITX_WLANRX_N2

+3.3V_SUS

+3.3V_RUN

+3.3V_SUS

+3.3V_SUS

+1.5V_RUN

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS+3.3V_SUS

+3.3V_RUN

+3.3V_SUS

SIO_EXT_SMI#<40>

H_STP_CPU#<6>

IMVP_PWRGD<43,50>

USBP4+ <33>

USBP5- <33>

USBP5+ <33>

USBP4- <33>

IRQ_SERIRQ<29,31,39,40>

SIO_SLP_S3# <40>

SIO_SLP_S5# <40>

CLK_PCIE_ICH# <6>

CLK_PCIE_ICH <6>

PM_BMBUSY#<10>

SIO_THRM#<40>

ICH_PCIE_WAKE#<39>

USBP6+ <33>

USBP7- <38>

USBP7+ <38>

USBP6- <33>

PLTRST# <10,20,22,29,36>

CLK_ICH_14M <6>

CLK_ICH_48M <6>

CLKRUN#<31,39,40>

SPKR<27>

H_STP_PCI#<6>

SUSPWROK <18,43>

SIO_PWRBTN# <40>

DPRSLPVR <50>

PCIE_IRX_WLANTX_N2<36> PCIE_IRX_WLANTX_P2<36>

PCIE_ITX_WLANRX_N2_C<36>

PCIE_ITX_WLANRX_P2_C<36>

SIO_EXT_WAKE#<40>

SIO_EXT_SCI# <40>

USBP1+ <39>

USBP1- <39>

DMI_MRX_ITX_N0 <10>

DMI_MRX_ITX_P0 <10>

DMI_MRX_ITX_N1 <10>

DMI_MRX_ITX_P1 <10>

USBP0+ <36>

USBP0- <36>

USB_OC5# <33>

USB_OC3#

PCIE_IRX_WANTX_N1<36> PCIE_IRX_WANTX_P1<36>

PCIE_ITX_WANRX_N1_C<36>

PCIE_ITX_WANRX_P1_C<36>

PCIE_IRX_LOMTX_N3<29>

PCIE_ITX_LOMRX_N3_C<29>

PCIE_ITX_LOMRX_P3_C<29>

PCIE_IRX_LOMTX_P3<29>

USB_OC4# <33>

USB_OC6# <33>

ICH_EC_SPI_CLK<40>

ICHO_ECO_SPII_DATA<40> ICHI_ECI_SPIO_DATA<40>

ITP_DBRESET#<7,40>

LCD_TST<19>

BT_RADIO_DIS#<34>

WWAN_RADIO_DIS# <36>

IDE_HRESET#<26>

LAMP_STAT#<19>

PM_EXTTS#1 <10>

ICH_SMBDATA<6,29,36> ICH_SMBCLK<6,29,36>

DMI_MTX_IRX_N0 <10>

DMI_MTX_IRX_P0 <10>

DMI_MTX_IRX_N1 <10>

DMI_MTX_IRX_P1 <10>

SPI_CS#<40>

ICH_PWRGD <6>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

ICH7(3/4)

24 59Friday, May 12, 2006

Compal Electronics, Inc.

(PCI Express Wake Event)

Place closely pin U45.B2

Place closely pin U45.AC1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

close to ICH7-M

Within 500 mils

Within 500 mils

<---Docking

<---REAR

<---REAR

<---SIO USB Hub

<---PWR USB

GIGA LAN--->

Mini Card 1--->

Mini Card 2--->

<---Mini2 WLAN

R239

10K_0402_5%~D

1 2

R266

10K_0402_5%~D

1 2

R241

8.2K_0402_5%~D

1 2

R246 8.2K_0402_5%~D

1 2

R237 8.2K_0402_5%~D@1 2

R270

10_0402_5%~D

@

12

R250 10K_0402_5%~D

1 2

R264 24.9_0402_1%~D

1 2

R248 10K_0402_5%~D 1 2

R267

10K_0402_5%~D

1 2

R253 680_0402_5%~D

1 2

R257 10K_0402_5%~D 1 2

T7PAD~D

R259 10K_0402_5%~D 1 2

R258 10K_0402_5%~D 1 2

C269 0.1U_0402_10V6K~D

1 2

R245 10K_0402_5%~D

1 2

R238

10K_0402_5%~D

1 2

R574 0_0402_5%~D

12

R263 10K_0402_5%~D 1 2

C265

4.7P_0402_50V8C~D

@

1

2

C270 0.1U_0402_10V6K~D

1 2

R247 10K_0402_5%~D

1 2

R244 8.2K_0402_5%~D

1 2 R243

10_0402_5%~D

@

12

R271 22.6_0402_1%~D

1 2

R255 100K_0402_5%~D

1 2

R261 10K_0402_5%~D 1 2

R252 10K_0402_5%~D

1 2

R256 10K_0402_5%~D 1 2

R236

2.2K_0402_5%~D

12

C272

4.7P_0402_50V8C~D

@

1

2

R235

2.2K_0402_5%~D

12

R262 10K_0402_5%~D 1 2

R251 8.2K_0402_5%~D

1 2

R641 47_0402_5%~D

12

T6PAD~D

R249 10K_0402_5%~D

1 2

R268

47_0402_5%~D

1 2

R242 10K_0402_5%~D

1 2

R260 10K_0402_5%~D 1 2

R234 10K_0402_5%~D

1 2

R269 47_0402_5%~D

1 2

R254 10K_0402_5%~D

1 2

C267 0.1U_0402_10V6K~D

1 2

C268 0.1U_0402_10V6K~D

1 2

PCI-EXPRESS

DIRECT MEDIA INTERFACE

USB

SPI

U19D

82801GHM SL8YB B0_BGA652~D

SPI_CLK

R2

SPI_CS#

P6

SPI_ARB

P1

SPI_MOSI

P5

SPI_MISO

P2

DMI0RXN V26

DMI0RXP V25

DMI0TXN U28

DMI0TXP U27

DMI1RXN Y26

DMI1RXP Y25

DMI1TXN W28

DMI1TXP W27

DMI2RXN AB26

DMI2RXP AB25

DMI2TXN AA28

DMI2TXP AA27

DMI3RXN AD25

DMI3RXP AD24

DMI3TXN AC28

DMI3TXP AC27

DMI_CLKN AE28

DMI_CLKP AE27

DMI_ZCOMP C25

DMI_IRCOMP D25

PERn1

F26

PERp1

F25

PETn1

E28

PETp1

E27

PERn2

H26

PERp2

H25

PETn2

G28

PETp2

G27

PERn3

K26

PERp3

K25

PETn3

J28

PETp3

J27

PERn4

M26

PERp4

M25

PETn4

L28

PETp4

L27

PERn5

P26

PERp5

P25

PETn5

N28

PETp5

N27

PERn6

T25

PERp6

T24

PETn6

R28

PETp6

R27

OC0#

D3

OC1#

C4

OC2#

D5

OC3#

D4

OC4#

E5

OC5# / GPIO29

C3

OC6# / GPIO30

A2

OC7# / GPIO31

B3

USBP0N F1

USBP0P F2

USBP1N G4

USBP1P G3

USBP2N H1

USBP2P H2

USBP3N J4

USBP3P J3

USBP4N K1

USBP4P K2

USBP5N L4

USBP5P L5

USBP6N M1

USBP6P M2

USBP7N N4

USBP7P N3

USBRBIAS# D2

USBRBIAS D1

C271 0.1U_0402_10V6K~D

1 2

T17PAD~D

R240 10K_0402_5%~D

1 2 R370

10K_0402_5%~D

@

1 2

SATA

POWER MGT

SYS

SMB

GPIO

Clocks

GPIO

GPIO

U19C

82801GHM SL8YB B0_BGA652~D

RI#

A28

SPKR

A19

SYS_RST#

A22 SUS_STAT#

A27

GPIO0 / BM_BUSY#

AB18

GPIO26

A21

GPIO27

B21

GPIO28

E23

GPIO32 / CLKRUN#

AG18

GPIO33 / AZ_DOCK_EN#

AC19

GPIO34 / AZ_DOCK_RST#

U2

VRMPWRGD

AD22

GPIO11 / SMBALERT#

B23

SUSCLK C20

SLP_S3# B24

SLP_S4# D23

SLP_S5# F22

PWROK AA4

GPIO16 / DPRSLPVR AC22

TP0 / BATLOW# C21

PWRBTN# C23

LAN_RST# C19

RSMRST# Y4

GPIO21 / SATA0GP AF19

GPIO19 / SATA1GP AH18

GPIO36 / SATA2GP AH19

GPIO37 / SATA3GP AE19

CLK14 AC1

CLK48 B2

GPIO9 E20

GPIO10 A20

GPIO12 F19

GPIO13 E19

GPIO14 R4

GPIO15 E22

GPIO24 R3

GPIO25 D20

SATACLKREQ#/GPIO35 AD21

GPIO38 AD20

GPIO39 AE20

SMBCLK

C22

SMBDATA

B22

LINKALERT#

A26

SMLINK0

B25

SMLINK1

A25

GPIO18 / STPPCI#

AC20

GPIO20 / STPCPU#

AF21

WAKE#

F20

SERIRQ

AH21

THRM#

AF20

GPIO6

AC21

GPIO7

AC18

GPIO8

E21

R265

10K_0402_5%~D

1 2

C266 0.1U_0402_10V6K~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+DMIPLL_R

ICH_V5REF_SUS

+1.5V_DMIPLL

ICH_V5REF_RUN

+1.5V_RUN_L

ICH_V5REF_RUN

ICH_V5REF_SUS

+RTC_CELL

+5V_SUS

+1.5V_RUN_L

+1.5V_DMIPLL

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+5V_RUN

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

ICH7(4/4)

25 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CRB is 270uF

60ohm,3000mA,0.025ohm

600ohm,100mA

C283

0.1U_0402_10V6K~D

1

2

C299

10U_0805_6.3V6M~D

1

2

C295

0.1U_0402_10V6K~D

1

2

C307

0.1U_0402_10V6K~D

1

2

C297

0.1U_0402_10V6K~D

1

2

C305

0.1U_0402_10V6K~D

1 2

L24

BLM11A601S_0603~D

1 2

C291

0.1U_0402_10V6K~D

1

2

R585

0.5_0805_1%~D

1 2

C285

0.1U_0402_10V6K~D

1 2

C287

4.7U_0603_6.3V6M~D

1 2

R273

10_0402_5%~D

12

C296

0.1U_0402_10V6K~D

1

2

C289

0.1U_0402_10V6K~D

1

2

+

C276

220U_D2_4M_R45~D

1

2

C308

0.1U_0402_10V6K~D

1

2

D8

RB751S40T1_SOD523-2~D

21

C300

0.1U_0402_10V6K~D

1

2

U19F

82801GHM SL8YB B0_BGA652~D

V5REF[1]

G10

V5REF[2]

AD17

V5REF_Sus

F6

Vcc1_5_B[1]

AA22

Vcc1_5_B[2]

AA23

Vcc1_5_B[3]

AB22

Vcc1_5_B[4]

AB23

Vcc1_5_B[5]

AC23

Vcc1_5_B[6]

AC24

Vcc1_5_B[7]

AC25

Vcc1_5_B[8]

AC26

Vcc1_5_B[9]

AD26

Vcc1_5_B[10]

AD27

Vcc1_5_B[11]

AD28

Vcc1_5_B[12]

D26

Vcc1_5_B[13]

D27

Vcc1_5_B[14]

D28

Vcc1_5_B[15]

E24

Vcc1_5_B[16]

E25

Vcc1_5_B[17]

E26

Vcc1_5_B[18]

F23

Vcc1_5_B[19]

F24

Vcc1_5_B[20]

G22

Vcc1_5_B[21]

G23

Vcc1_5_B[22]

H22

Vcc1_5_B[23]

H23

Vcc1_5_B[24]

J22

Vcc1_5_B[25]

J23

Vcc1_5_B[26]

K22

Vcc1_5_B[27]

K23

Vcc1_5_B[28]

L22

Vcc1_5_B[29]

L23

Vcc1_5_B[30]

M22

Vcc1_5_B[31]

M23

Vcc1_5_B[32]

N22

Vcc1_5_B[33]

N23

Vcc1_5_B[34]

P22

Vcc1_5_B[35]

P23

Vcc1_5_B[36]

R22

Vcc1_5_B[37]

R23

Vcc1_5_B[38]

R24

Vcc1_5_B[39]

R25

Vcc1_5_B[41]

T22

Vcc1_5_B[42]

T23

Vcc1_5_B[43]

T26

Vcc1_5_B[44]

T27

Vcc1_5_B[45]

T28

Vcc1_5_B[46]

U22

Vcc1_5_B[47]

U23

Vcc1_5_B[48]

V22

Vcc1_5_B[49]

V23

Vcc1_5_B[50]

W22

Vcc1_5_B[52]

Y22

Vcc1_5_B[53]

Y23

Vcc1_5_B[51]

W23

Vcc1_5_B[40]

R26

Vcc3_3[1]

B27

VccDMIPLL

AG28

VccSATAPLL

AD2

Vcc3_3[2]

AH11

Vcc1_05[1] L11

Vcc1_05[2] L12

Vcc1_05[3] L14

Vcc1_05[4] L16

Vcc1_05[6] L18

Vcc1_05[5] L17

Vcc1_05[7] M11

Vcc1_05[8] M18

Vcc1_05[9] P11

Vcc1_05[10] P18

Vcc1_05[11] T11

Vcc1_05[12] T18

Vcc1_05[13] U11

Vcc1_05[14] U18

Vcc1_05[15] V11

Vcc1_05[16] V12

Vcc1_05[17] V14

Vcc1_05[18] V16

Vcc1_05[19] V17

Vcc1_05[20] V18

Vcc3_3 / VccHDA U6

VccSus3_3/VccSusHDA R7

V_CPU_IO[1] AE23

V_CPU_IO[2] AE26

V_CPU_IO[3] AH26

Vcc3_3[3] AA7

Vcc3_3[4] AB12

Vcc3_3[5] AB20

Vcc3_3[6] AC16

Vcc3_3[7] AD13

Vcc3_3[8] AD18

Vcc3_3[9] AG12

Vcc3_3[10] AG15

Vcc3_3[11] AG19

Vcc3_3[12] A5

Vcc3_3[14] B16

Vcc3_3[15] B7

Vcc3_3[16] C10

Vcc3_3[13] B13

Vcc3_3[17] D15

Vcc3_3[18] F9

Vcc3_3[19] G11

Vcc3_3[20] G12

VccRTC W5

VccSus3_3[1] P7

VccSus3_3[2] A24

VccSus3_3[4] D19

VccSus3_3[5] D22

VccSus3_3[6] G19

VccSus3_3[3] C24

VccSus3_3[7] K3

VccSus3_3[8] K4

VccSus3_3[9] K5

VccSus3_3[10] K6

VccSus3_3[11] L1

Vcc1_5_A[19] AB17

Vcc1_5_A[20] AC17

Vcc1_5_A[21] T7

Vcc1_5_A[22] F17

Vcc1_5_A[23] G17

Vcc1_5_A[24] AB8

Vcc1_5_A[25] AC8

VccSus1_05[1] K7

Vcc1_5_A[1]

AB7

Vcc1_5_A[2]

AC6

Vcc1_5_A[3]

AC7

Vcc1_5_A[4]

AD6

Vcc1_5_A[5]

AE6

Vcc1_5_A[6]

AF5

Vcc1_5_A[7]

AF6

Vcc1_5_A[8]

AG5

Vcc1_5_A[9]

AH5

Vcc1_5_A[10]

AB10

Vcc1_5_A[11]

AB9

Vcc1_5_A[12]

AC10

Vcc1_5_A[13]

AD10

Vcc1_5_A[14]

AE10

Vcc1_5_A[15]

AF10

Vcc1_5_A[16]

AF9

Vcc1_5_A[17]

AG9

Vcc1_5_A[18]

AH9

VccSus3_3[19]

E3

VccUSBPLL

C1

VccSus1_05/VccLAN1_05[1]

AA2

VccSus1_05/VccLAN1_05[2]

Y7

VccSus3_3/VccLAN3_3[1]

V5

VccSus3_3/VccLAN3_3[2]

V1

VccSus3_3/VccLAN3_3[3]

W2

VccSus3_3/VccLAN3_3[4]

W7

Vcc3_3[21] G16

VccSus3_3[12] L2

VccSus3_3[13] L3

VccSus3_3[14] L6

VccSus3_3[15] L7

VccSus3_3[16] M6

VccSus3_3[17] M7

VccSus3_3[18] N7

VccSus1_05[2] C28

VccSus1_05[3] G20

Vcc1_5_A[26] A1

Vcc1_5_A[27] H6

Vcc1_5_A[28] H7

Vcc1_5_A[29] J6

Vcc1_5_A[30] J7

C290

0.1U_0402_10V6K~D

1

2

C309

0.1U_0402_10V6K~D

1

2

C273

1U_0603_10V4Z~D

1

2

C298

0.01U_0402_16V7K~D

1

2

C293

0.1U_0402_10V6K~D

1

2

C274

0.1U_0402_10V6K~D

1

2

C277

0.1U_0402_10V6K~D

1

2

C284

0.1U_0402_10V6K~D

1 2

D9

RB751S40T1_SOD523-2~D

21

C306

0.1U_0402_10V6K~D

1

2

C282

0.1U_0402_10V6K~D

1

2

C303

0.1U_0402_10V6K~D

1

2

+

C275

330U_V_6.3VM_R25M~D

1

2

C286

0.1U_0402_10V6K~D

1

2

C304

1U_0603_10V4Z~D

1

2

R272

100_0402_5%~D

12

C278

0.1U_0402_10V6K~D

1

2

C302

0.1U_0402_10V6K~D

1

2

U19E

82801GHM SL8YB B0_BGA652~D

VSS[0]

A4

VSS[1]

A23

VSS[2]

B1

VSS[3]

B8

VSS[4]

B11

VSS[5]

B14

VSS[6]

B17

VSS[7]

B20

VSS[8]

B26

VSS[9]

B28

VSS[10]

C2

VSS[11]

C6

VSS[12]

C27

VSS[13]

D10

VSS[14]

D13

VSS[15]

D18

VSS[16]

D21

VSS[17]

D24

VSS[18]

E1

VSS[19]

E2

VSS[21]

E4

VSS[22]

E8

VSS[23]

E15

VSS[24]

F3

VSS[25]

F4

VSS[26]

F5

VSS[27]

F12

VSS[28]

F27

VSS[29]

F28

VSS[30]

G1

VSS[31]

G2

VSS[32]

G5

VSS[33]

G6

VSS[34]

G9

VSS[35]

G14

VSS[36]

G18

VSS[37]

G21

VSS[38]

G24

VSS[39]

G25

VSS[40]

G26

VSS[41]

H3

VSS[42]

H4

VSS[43]

H5

VSS[44]

H24

VSS[45]

H27

VSS[46]

H28

VSS[47]

J1

VSS[48]

J2

VSS[49]

J5

VSS[50]

J24

VSS[51]

J25

VSS[52]

J26

VSS[53]

K24

VSS[54]

K27

VSS[55]

K28

VSS[56]

L13

VSS[57]

L15

VSS[58]

L24

VSS[59]

L25

VSS[60]

L26

VSS[61]

M3

VSS[62]

M4

VSS[63]

M5

VSS[64]

M12

VSS[65]

M13

VSS[66]

M14

VSS[67]

M15

VSS[68]

M16

VSS[69]

M17

VSS[70]

M24

VSS[71]

M27

VSS[72]

M28

VSS[73]

N1

VSS[74]

N2

VSS[75]

N5

VSS[76]

N6

VSS[77]

N11

VSS[78]

N12

VSS[79]

N13

VSS[80]

N14

VSS[81]

N15

VSS[82]

N16

VSS[83]

N17

VSS[84]

N18

VSS[85]

N24

VSS[86]

N25

VSS[87]

N26

VSS[88]

P3

VSS[89]

P4

VSS[90]

P12

VSS[91]

P13

VSS[92]

P14

VSS[93]

P15

VSS[94]

P16

VSS[95]

P17

VSS[96]

P24

VSS[97]

P27

VSS[98] P28

VSS[99] R1

VSS[100] R11

VSS[101] R12

VSS[102] R13

VSS[103] R14

VSS[104] R15

VSS[105] R16

VSS[106] R17

VSS[107] R18

VSS[108] T6

VSS[109] T12

VSS[110] T13

VSS[111] T14

VSS[112] T15

VSS[113] T16

VSS[114] T17

VSS[115] U4

VSS[116] U12

VSS[117] U13

VSS[118] U14

VSS[119] U15

VSS[120] U16

VSS[121] U17

VSS[122] U24

VSS[123] U25

VSS[124] U26

VSS[125] V2

VSS[126] V13

VSS[127] V15

VSS[128] V24

VSS[129] V27

VSS[130] V28

VSS[131] W6

VSS[132] W24

VSS[133] W25

VSS[134] W26

VSS[135] Y3

VSS[136] Y24

VSS[137] Y27

VSS[138] Y28

VSS[139] AA1

VSS[140] AA24

VSS[141] AA25

VSS[142] AA26

VSS[143] AB4

VSS[144] AB6

VSS[145] AB11

VSS[146] AB14

VSS[147] AB16

VSS[148] AB19

VSS[149] AB21

VSS[150] AB24

VSS[151] AB27

VSS[152] AB28

VSS[153] AC2

VSS[154] AC5

VSS[155] AC9

VSS[156] AC11

VSS[157] AD1

VSS[158] AD3

VSS[159] AD4

VSS[160] AD7

VSS[161] AD8

VSS[162] AD11

VSS[163] AD15

VSS[164] AD19

VSS[165] AD23

VSS[166] AE2

VSS[167] AE4

VSS[168] AE8

VSS[169] AE11

VSS[170] AE13

VSS[171] AE18

VSS[172] AE21

VSS[173] AE24

VSS[174] AE25

VSS[175] AF2

VSS[176] AF4

VSS[177] AF8

VSS[178] AF11

VSS[179] AF27

VSS[180] AF28

VSS[181] AG1

VSS[182] AG3

VSS[183] AG7

VSS[184] AG11

VSS[185] AG14

VSS[186] AG17

VSS[187] AG20

VSS[188] AG25

VSS[189] AH1

VSS[190] AH3

VSS[191] AH7

VSS[192] AH12

VSS[193] AH23

VSS[194] AH27

L23

BLM21PG600SN1D_0805~D

1 2

C294

0.1U_0402_10V6K~D

1

2

C301

0.1U_0402_10V6K~D

1

2

C292

0.1U_0402_10V6K~D

1

2

C279

0.1U_0402_10V6K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDE_DIORDY

IDE_ACT#

IDE_DIOR#

IDE_DIORDY

IDE_DDACK#

IDE_ACT#

IDE_DA1

IDE_DA0

IDE_DD1

IDE_DD0

IDE_DD6

IDE_DD5

IDE_DD4

IDE_DD3

IDE_DD7

IDE_DD2

IDE_HRESET#

IDE_DIOW#

IDE_IRQ

IDE_DA2

PDIAG#

IDE_DDREQ

IDE_DD8

IDE_DD11

IDE_DD13

IDE_DD12

IDE_DD15

IDE_DD14

IDE_DD10

IDE_DD9

HDD_EN_3.3V

+3.3V_HDD

+3.3V_HDD

+3.3V_HDD

+3.3V_RUN

+3.3V_RUN

+3.3V_SUS+15V_SUS

+3.3V_HDD

+3.3V_HDD

IDE_DA[0..2]<23>

IDE_DD[0..15]<23>

HDDC_EN#<39>

IDE_DIORDY<23>

IDE_DSC1#<23> IDE_ACT#<44>

IDE_HRESET#<24>

IDE_DIOW# <23>

IDE_IRQ <23>

IDE_DDREQ <23>

IDE_DSC3# <23>

IDE_DIOR#<23>

IDE_DDACK#<23>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

IDE HDD Connector

26 59Friday, May 12, 2006

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Pleace near HD CONN

+3.3V_HDD Source

HDD PWR

Need to modify of FPC ZIP connector

HDD Connector

C311

0.1U_0402_16V4Z~D

1

2

R278 510_0402_5%~D@12

JHDD1

FOX_QT510406-2101-7F~D

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

GND

41

GND

43

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

GND 42

GND 44

C310

1000P_0402_50V7K~D

1

2

C315

10U_0805_10V4Z~D

1

2

R280

100K_0402_5%~D

@

12

R281

100K_0402_5%~D

12

C312

1U_0603_10V4Z~D

1

2

R275

10K_0402_5%~D

1 2

C313

0.1U_0402_16V4Z~D

1

2

C314

0.1U_0402_16V4Z~D

@

1

2

R276 4.7K_0402_5%~D

1 2

PJP1

PAD-OPEN 4x4m

1 2

S

GD

Q15

SI3456DV-T1-E3_TSOP6~D

@

3

6

2

4 5

1

G

D

S

Q16

2N7002W-7-F_SOT323~D

@

2

13

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AC97VREFI

CAP2

AUDIO_AVDD_ON TPS793475_BYPASS

AC97VREFI

ICH_AZ_CODEC_RST#

ICH_AZ_CODEC_SDOUT

ICH_AZ_CODEC_SYNC

ICH_AC_SDIN0_R

ICH_AZ_CODEC_BITCLK

CAP2

HP_NB_SENSE

SPDIF_SHDN

SENSE_A

SENSE_A

Z2403 PC_BEEPZ2402

HP_NB_SENSE

ICH_AZ_CODEC_SDOUT

DOCK_HP_MUTE#

DOCK_HP_MUTE#

+VDDA

+VDDA

+5V_SUS

+VDDA

+VREFOUT

+VDDA

+3.3V_RUN

+5V_RUN

+3.3V_RUN

ICH_AZ_CODEC_RST#<23>

ICH_AZ_CODEC_SYNC<23>

ICH_AZ_CODEC_SDOUT<23>

ICH_AZ_CODEC_BITCLK<23>

HP_OUT_L <28>

HP_OUT_R <28>

AUDIO_AVDD_ON<39>

NB_MICIN_L <28>

SPDIF_DOCK<38>

SPDIF_SHDN<39>

MIC_SWITCH <28>

AUD_LINE_OUT <28>

NB_MICIN_R <28>

INT_MIC <28>

BEEP<39>

SPKR<24> PC_BEEP <28>

HP_NB_SENSE<28,39>

DOCK_HP_MUTE#<39>

EAPD<28>

ICH_AZ_CODEC_SDIN0<23>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Azalia (HD) Codec

27 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

This signal must be under 1V.

+VDDA=4.75V

Close to U24.18

Close to U24.20

Close to U24.5

W=30 mil

Close to U24

Close to U24.3

When L47 is popped, no pop U22.

TRACE>15 mil

45

2

single gate TTL

31

W=20 mil

600ohm,100mA

Note: C336,C340,C341,C326,C327,C328,C619,C620 use

Temp. characteristics: X5R

Operating range: -55~+85degree

STAC9200 Rev.

CA1

B1

R22 R109

5.11K 10K

39.2K 20K

C620

10U_0805_10V6M~D

1

2

C339

10P_0402_50V8J~D

@

1 2

C334 1000P_0402_50V7K~D

1 2

U22

TPS793475DBVRG4_SOT23-5~D

OUT 5

BYPASS 4

GND

2

EN

3

IN

1L26

BLM11A601S_0603~D

@1 2

C322

0.047U_0402_16V7K~D

1

2

C321

0.1U_0402_10V6K~D

1

2

R286 5.1K_0402_1%~D

12

R288 2.2K_0402_5%~D

1 2

R287 2.2K_0402_5%~D

1 2

C328

10U_0805_10V6M~D

1

2

C332 0.1U_0402_10V6K~D

1 2

R604 100K_0402_5%~D

12

STAC9200

U24

STAC9200X5NAEB1XR_QFN32~D

SDATA_OUT

2

BIT_CLK

3

SYNC

7

RESET#

8

SPDIF _OUT

32

CAP2

20

VREF_OUT

19

VREF_IN

18

AVDD 26

AVSS1

17

AVSS2

29

SPDIF _ IN/EAPD /GPIO3

31

SENSE_A 9

SDATA_IN

5

LINE_IN_L 15

LINE_IN_R 16

CD_L 10

CD_R 12

HP_L 27

HP_R 28

LOUT_L 23

LOUT_R 24

MONO_OUT 25

DVDD 6

DVSS

4

GPIO0

21

GPIO1

22

GPIO2

30

MIC1 13

MIC2 14

NC1

1

NC2

11

R554 0_0402_5%~D@12

C340

1U_0603_10V6K~D

1

2

R291

20K_0402_1%~D

12

C324

0.1U_0402_10V6K~D

1

2

C338

10P_0402_50V8J~D

@

1 2

G

D

S

Q18

2N7002W-7-F_SOT323~D

2

13

R282

10K_0402_5%~D

1 2

R289

47_0402_5%~D

@

12

G

D

S

Q17

2N7002W-7-F_SOT323~D

2

13

C316

0.1U_0402_10V6K~D

1

2

C323

0.1U_0402_10V6K~D

1

2

R283

2.2K_0402_5%~D

12

C341

0.1U_0402_10V6K~D

1

2

C721 1000P_0402_50V7K~D

1 2

C320

2.2U_0603_6.3V6K~D

1

2

C619

0.1U_0402_10V6K~D

1

2

U23

SN74AHCT1G86DCKR_SC70-5~D

A

1

B

2Y4

P5

G

3

R284 33_0402_5%~D

1 2

C326

1U_0603_10V6K~D

1

2

C331

22P_0402_50V8J~D

@

1

2

C325

0.1U_0402_10V6K~D

1 2

C317

0.047U_0402_16V7K~D

1

2

R290

39.2K_0402_1%~D

12

C333

0.1U_0402_10V6K~D

1 2

C336

1U_0603_10V6K~D

1

2

R591 0_0402_5%~D

12

C327

0.1U_0402_10V6K~D

1

2

C318

1U_0603_10V6K~D

1

2

C337

22P_0402_50V8J~D

@

1

2

C342

10P_0402_50V8J~D

@

1 2

C335 1000P_0402_50V7K~D

1 2

R285

22_0402_5%~D

@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUD_GAIN0

AUD_GAIN1

AUD_LINE_IN_R

C1P

C1N

HP_SPK_L1

PVSS

HP_SPK_R1

INT_SPK_R1

+5V_AMPVCC

BYPASS

RIN-

AUD_GAIN0

AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

AUD_LINE_IN_L

MIC_L1

MIC_R1 MIC_R2

MIC_BIAS

MIC_BIAS

HP_SPK_R1

HP_SPK_L1 HP_SPK_L2

HP_SPK_R2

INT_SPK_R2

INT_MIC+

INT_MIC-

INT_MIC+

INT_MIC-

SPK_SHUTDOWN#

HP_NB_SENSE

NB_MUTE

MIC_L2

+5V_AMPVCC

+3.3V_RUN

+5V_SUS +5V_AMPVCC

+3VRUN_4411

+VREFOUT

+VDDA

+VDDA

+VDDA

+VDDA

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+5V_SUS

NB_MUTE<39>

HP_OUT_L<27>

HP_OUT_R<27>

AUD_LINE_OUT<27>

MIC_SWITCH<27>

NB_MICIN_R<27>

NB_MICIN_L<27>

INT_MIC <27>

PC_BEEP<27>

HP_NB_SENSE<27,39>

EAPD<27>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

AMP and PHONE JACK

28 59Friday, May 12, 2006

Compal Electronics, Inc.

Gain Setting

GAIN0 INPUTAV(inv)GAIN1

21.6dB

15.6dB

6dB

1

0

10dB

25K ohm

45K ohm

70K ohm

90K ohm

IMPEDANCE

11

0

0

0

*

1

Speaker Connector

15 mils trace W=40mils

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

600ohm,100mA

120ohm,600mA,0.25ohm

120ohm,600mA,0.25ohm

60ohm,3000mA,0.025ohm

120ohm,600mA,0.25ohm

120ohm,600mA,0.25ohm

Note:

C343,C344,C345,C346,C350,C351,C353,C354,C355,C356,C357 use

Temp. characteristics: X5R

Operating range: -55~+85degree

C348

100P_0402_50V8J~D

1

2

D20

DA204U_SOT323~D

@

2

3

1

C364

10U_0805_10V6M~D

1

2

C365

0.1U_0402_10V6K~D

1

2

R305

10K_0402_5%~D

1 2

R298

100K_0402_5%~D

12

U25A

LM358DR2G_SOIC8~D

P8

IN+ 3

IN- 2

G

4

O

1

C372

0.47U_0402_16V4Z~D

1

2

C347

2.2U_0603_6.3V6K~D

1

2

C354

0.1U_0402_10V6K~D

1 2

C346

2.2U_0603_6.3V6K~D

1 2

R303

100K_0402_5%~D

1 2

C344

1U_0603_10V6K~D

1

2

R310

1K_0402_5%~D

12

R312

1K_0402_5%~D

@

12

R304

1K_0402_5%~D

12

C370

47P_0402_50V8J~D

1

2

C639

47P_0402_50V8J~D

1

2

G

D

S

Q80

2N7002W-7-F_SOT323~D

2

13

R293

4.7K_0402_5%~D

12

C351

1U_0603_10V6K~D

1 2

R295

4.99_0402_1%~D

12

R306

10K_0402_5%~D

1 2

C369

4700P_0402_25V7K~D

12

C343

1000P_0402_50V7K~D

1 2

U26

MAX4411ETP+_TQFN20~D

C1P

1

PGND

2

C1N

3

NC-4 4

PVss

5

NC-6 6

SVss

7

NC-8 8

OUTL 9

SVDD 10

INR

15

SHDNR#

14

INL

13

NC-12 12

OUTR 11

NC-20 20

PVDD 19

SHDNL#

18

SGND

17

NC-16 16

D21

DA204U_SOT323~D

@

2

3

1

JSPK1

MOLEX_53780-0270~D

1

1

2

2

GND

3

GND

4

R307

100K_0402_5%~D

1 2

MIC1

WM-63PCY_2P~D

1

2

JP8

SUYIN_010030FR006G103ZL~D

1

2

3

4

5

6

7

8

C360

100P_0402_50V8J~D

1

2

L32

BLM21PG600SN1D_0805~D

1 2

L28

BLM11A121S_0603~D

12

R301

100K_0402_5%~D

12

C352

2.2U_0603_6.3V6K~D

1 2

C361

1000P_0402_50V7K~D

@

1

2

C371

4700P_0402_25V7K~D

12

C358

2.2U_0603_6.3V6K~D

1 2

U25B

LM358DR2G_SOIC8~D

P8

IN+

5

IN-

6

G

4

O7

C621

47P_0402_50V8J~D

12

R300

20K_0402_1%~D

@

12

C345

2.2U_0603_6.3V6K~D

1 2

C362

1000P_0402_50V7K~D

@

1

2

L27

BLM11A601S_0603~D

1 2

JP7

SUYIN_010030FR006G103ZL~D

1

2

3

4

5

6

7

8

C363

1U_0603_10V6K~D

1

2

C356

0.1U_0402_10V6K~D

1 2

C353

2.2U_0603_10V6K~D

1

2

C359

100P_0402_50V8J~D

1

2

R309

1K_0402_5%~D

12

C357

2.2U_0603_10V6K~D

1

2

R297

4.99_0402_1%~D

12

C367

4700P_0402_25V7K~D

12

D25

SM24_SOT23~D

@

2

3

1

R308

1K_0402_5%~D

12

C640

47P_0402_50V8J~D

1

2

C350

1U_0603_10V6K~D

1 2

R313

1K_0402_5%~D

12

G

D

S

Q79

2N7002W-7-F_SOT323~D

@

2

13

R311

1K_0402_5%~D

@

12

C625

0.1U_0402_10V6K~D

12

L30

BLM11A121S_0603~D

12

U27

TPA6017A2PWP_TSSOP20~D

GND4

1GND3

11 GND2

13 GND1

20

VDD 16

PVDD1 15

RIN-

17

BYPASS 10

NC 12

LOUT- 8

LOUT+ 4

ROUT- 14

ROUT+ 18

RIN+

7

LIN-

5

LIN+

9

GAIN0 2

GAIN1 3

PVDD2 6

SHUTDOWN

19

GND_T

21

C366

0.1U_0402_10V6K~D

1

2

L31

BLM11A121S_0603~D

12

C368

4700P_0402_25V7K~D

12

C355

0.1U_0402_10V6K~D

12

G

D

S

Q21

2N7002W-7-F_SOT323~D

2

13

R296

100K_0402_5%~D

12

R294

100K_0402_5%~D

12

R302

1K_0402_5%~D

12

R314

100K_0402_5%~D

1 2

R299

20K_0402_1%~D

@

12

R292

4.7K_0402_5%~D

12

C652

100P_0402_50V8J~D

@

1

2

C349

100P_0402_50V8J~D

1

2

L29

BLM11A121S_0603~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TPM_EN#

TPM_GPIO2

CLK_PCIE_LOM#

LAN_TX3+

PLTRST#

LAN_TX3-

LOM_CS#

LOM_SI

LPC_LAD1

TPM_GPIO1

LAN_ACT#

PCIE_IRX_LOMTX_P3_C

LPC_LAD0

LOM_SO

IRQ_SERIRQ

LAN_TX1-

LAN_TX2+

LPC_LFRAME#

PCIE_IRX_LOMTX_N3_C

REGCTL_PNP25

REGCTL_PNP12

TPM_GPIO0

LOM_SCLK

LAN_TX0-

LAN_TX1+

XTALI

XTALO

LPC_LAD3

REGCTL_PNP12

CLK_PCIE_LOM

LINK_100#

LAN_TX2-

PCIE_WAKE#

LINK_10#

LAN_TX0+

PLTRST#

LPC_LAD2

CLK_PCI_LOM

CLK_PCI_LOM

TPM_GPIO0

TPM_GPIO1

TPM_GPIO2

TPM_EN#

LOM_LOW_PWR

BCM5752_K5

BCM5752_K5

LOM_SCLK

LOM_CS#

LOM_SOLOM_SI

LOM_LOW_PWR

REGCTL_PNP25

+3.3V_LAN

+3.3V_SRC

+1.2V_PCIE_PLLVDD

+2.5V_XTALVDD

+2.5V_AVDD

+3.3V_LAN

+1.2V_GPHY_PLLVDD

+1.2V_AVDDL

+1.2V_PCIE_PLLVDD

+1.2V_PCIE_SDS_VDD

+2.5V_BIASVDD

+2.5V_XTALVDD

+2.5V_AVDD

+1.2V_LOM

+1.2V_AVDDL

+1.2V_PCIE_SDS_VDD

+2.5V_BIASVDD

+3.3V_RUN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+3.3V_LAN

+2.5V_LOM

+2.5V_LOM

+2.5V_LOM

+2.5V_LOM

+2.5V_LOM

+1.2V_LOM

+1.2V_LOM

+1.2V_LOM

+1.2V_LOM

+1.2V_GPHY_PLLVDD

PCIE_WAKE# <36,39>

CLK_PCIE_LOM# <6>

CLK_PCIE_LOM <6>

LAN_TX3- <30>

LAN_TX1- <30>

LAN_TX3+ <30>

LAN_TX2- <30>

LAN_TX1+ <30>

ENAB_3VLAN<42>

PCIE_IRX_LOMTX_P3 <24>

PCIE_ITX_LOMRX_N3_C <24>

PCIE_IRX_LOMTX_N3 <24>

PCIE_ITX_LOMRX_P3_C <24>

LAN_TX2+ <30>

LAN_ACT#<30>

LINK_10#<30>

LINK_100#<30>

CLK_PCI_LOM<6>

ICH_SMBDATA<6,24,36>

LOM_TPM_EN#<39>

LPC_LFRAME#<23,39,40>

IRQ_SERIRQ<24,31,39,40> PLTRST#<10,20,22,24,36>

LPC_LAD[0..3]<23,39,40>

LOM_CLKREQ#<6>

LOM_CABLE_DETECT<39>

LOM_LOW_PWR <39>

ICH_SMBCLK<6,24,36>

PLTRST# <10,20,22,24,36>

LAN_TX0+ <30>

LAN_TX0- <30>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

BCM5751M

29 59Friday, May 12, 2006

1

C

4

MMJT9435

B

C

2

3

E

Layout Notice : 1.2V filter. Place as close

chip as possible.

Layout Notice : Place as close

chip as possible.

Layout Notice : No high

speed signal should be

routed near RDAC or on

adjacent layer to RDAC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Atmel AT45BCM021B

ST M45PE20

NV_STRAP1 NV_STRAP0 SO SI CS# SCLK

0

1

00

000

1

1

11

1

Place closely pin J8

Rc, Rd are 1/2 W rating

Rc Rd

600ohm,100mA

600ohm,100mA

600ohm,100mA

600ohm,100mA

600ohm,100mA

600ohm,100mA

Follow Travis to add that

Broadcom will be update for

next version.

Follow M07 schematic

Pop R341 to use BLM11A601S

If noise margin on SDSVDD so that

pop C412,C413

C403

0.1U_0402_16V4Z~D

1

2

C4010.1U_0402_16V4Z~D

1 2

C407

0.1U_0402_16V4Z~D

1

2

C410

4.7U_0603_6.3V6M~D

1

2

L38

BLM11A601S_0603~D

12

C383

0.1U_0402_16V4Z~D

1

2

R599

20K_0402_5%~D

@

12

R329 4.7K_0402_5%~D

@

1 2

R326 10K_0402_5%~D

1 2

C374

0.1U_0402_16V4Z~D

1

2

C710

0.1U_0402_16V4Z~D

1

2

C414

0.1U_0402_16V4Z~D

1

2

X3

25MHZ_18PF_1BX25000CK1D~D

1 2

C400

0.1U_0402_16V4Z~D

1

2

R340

4.7K_0402_5%~D

12

C375

4.7U_0603_6.3V6M~D

1

2

C384

0.1U_0402_16V4Z~D

1

2

R327 10K_0402_5%~D

1 2

C412

4.7U_0603_6.3V6M~D

@

1

2

C413

0.1U_0402_16V4Z~D

@

1

2

C388

0.1U_0402_16V4Z~D

1

2

R328 10K_0402_5%~D

1 2

R333

4.7K_0402_5%~D

@

1 2

C382

0.1U_0402_16V4Z~D

1

2

R335 4.7K_0402_5%~D@1 2

R620

4.7K_0402_5%~D @

12

L36

BLM11A601S_0603~D

12

BCM5752

Analog

power

PLL

GND

Digial power

BIAS

U28B

BCM5752KFBG A2_FPBGA144~D

VDDC_0

D5

VDDC_4

H5

VDDC_5

H6

VDDC_6

H8

VDDC_7

J4

VDDIO_3

F1

VDDIO_4

G10

VDDIO_5

J2

VDDIO_6

L1

VDDIO_7

L12

VSS_4 E6

VSS_5 E7

VSS_6 E8

VSS_7 E9

VSS_8 F4

VSS_9 F5

VSS_10 F6

VSS_11 F7

VSS_12 F8

VSS_13 F9

VSS_14 G5

VSS_15 G6

VSS_16 G7

VSS_17 G8

VSS_18 L2

VSS_19 L6

VSS_20 M6

NC_7 D2

NC_8 D3

NC_9 E1

NC_10 E2

NC_11 F2

VDDC_3

D8 VDDC_2

D7 VDDC_1

D6

VSS_3 E5

VSS_2 E4

VSS_1 B10

VSS_0 B2

NC_18 J10

VDDP_0

A5

VDDP_1

G3

VDDP_2

L11

XTALVDD

H12

PCIE_SDSVDD

K4

AVDDL_0

F10

AVDDL_1

F11

AVDD_0

A11

AVDD_1

F12

PCIE_PLLVDD

K6

GPHY_PLLVDD

G12

BIASVDD

A12

NC_12 G1

NC_0 A1

NC_1 A6

NC_2 A7

NC_3 B7

NC_4 C1

NC_5 C3

NC_6 D1

NC_13 G2

NC_14 G9

NC_15 H1

NC_16 H2

NC_17 H10

NC_19 K1

NC_20 K2

NC_21 K3

NC_22 K5

NC_23 K7

NC_24 K8

NC_25 K10

NC_26 K11

NC_27 L4

NC_28 L8

NC_29 M8

VDDIO_0

A3

VDDIO_1

C2

VDDIO_2

D10

C387

0.1U_0402_16V4Z~D

1

2

R341

BLM11A601S_0603~D

12

L33

BLM11A601S_0603~D

12

C396

0.1U_0402_16V4Z~D

1

2

R331 4.7K_0402_5%~D@1 2

R315

2_1210_5%~D

12

R321

33_0402_5%~D

@

12

R330

4.7K_0402_5%~D

@

1 2

Q24

MMJT9435T1G_SOT223~D

1

2 3

4

C391

0.1U_0402_16V4Z~D

1

2

S

GD

Q22

SI3456DV-T1-E3_TSOP6~D

3

6

245

1

C408

27P_0402_50V8J~D

1

2

Q23

MMJT9435T1G_SOT223~D

1

2 3

4

C385

4.7U_0603_6.3V6M~D

1

2

L34

BLM11A601S_0603~D

12

R332 4.7K_0402_5%~D@1 2

C726

4700P_0402_25V7K~D

1

2

C378

0.1U_0402_16V4Z~D

1

2

R603 0_0402_5%~D

12

C379

0.1U_0402_16V4Z~D

1

2

C381

0.1U_0402_16V4Z~D

1

2

R337 0_0402_5%~D@1 2

C386

4.7U_0603_6.3V6M~D

1

2

C411

0.1U_0402_16V4Z~D

1

2

L35

BLM11A601S_0603~D

12

R322 4.7K_0402_5%~D

12

C395

10U_0805_10V4Z~D

1

2

LPC/TPM

Media

GPIO

BCM5752

Power

PCI-ETEST

LED

Bias

Clock

Control

Regulator

Control

SPI

SMBUS

U28A

BCM5752KFBG A2_FPBGA144~D

TRD3+ B11

TRD3- B12

TRD2+ C11

TRD2- C12

TRD1+ D11

TRD1- D12

TRD0+ E11

TRD0- E12

LCLK

J8

LAD0

J7

LAD1

L10

LAD2

J5

LAD3

K9

LFRAME

J9

LRESET

M10

SERIRQ

H7

GPIO0

H9

GPIO1

H11

GPIO2

C5

SMB_CLK

C8

SMB_DATA

C7

SERIAL_DI J1

SERIAL_DO M4

SI

E10 SCLK

C9

SO

D9

CS

C10

PERST B1

REGCTL12 J11

REGCTL25 M11

REGSEN25 M12

LINKLED

A9

SPD100LED

B9

SPD1000LED

A10

TRAFFICLED

B8

PCIE_TXDN M3

PCIE_TXDP L3

PCIE_RXDN L7

PCIE_RXDP M7

WAKE A4

REFCLK- L5

REFCLK+ M5

VAUXPRSNT B6

TCK B5

TDI F3

TDO B4

TMS E3

TRST D4

RDAC A8

XTALI

L9

XTALO

M9

REFCLK_SEL B3

LOW_PWR H4

REGSUP12 K12

REGSEN12 J12

GPIO3

C4

GPHY_TVCOI C6

ATTN_BTTN A2

TPM_GPIO0

G4

TPM_GPIO2

H3 TPM_GPIO1

J3

TPM_EN

J6 VMAINPRSNT G11

NV_STRAP1

M1 NV_STRAP0

M2

R601 0_0402_5%~D@12

R324 0_0402_5%~D

12

R640

2K_0402_5%~D

1 2

C389

0.1U_0402_16V4Z~D

1

2

C409

27P_0402_50V8J~D

1

2

R339

4.7K_0402_5%~D

12

U30

AT45BCM021B-SU_SO8~D

SI 1

SCK 2

RESET# 3

CS# 4

SO

8

GND

7

VCC

6

WP#

5

C390

0.1U_0402_16V4Z~D

1

2

C376

0.1U_0402_16V4Z~D

1

2

R323 1K_0402_5%~D

12

C405

0.1U_0402_16V4Z~D

1

2

C399

0.1U_0402_16V4Z~D

1

2

C4020.1U_0402_16V4Z~D

1 2

R316

2_1210_5%~D

12

U29

M45PE20-VMN6TP_SO8~D@

D1

C2

RESET# 3

S# 4

Q

8

VSS

7

VCC

6

W#

5

C397

0.1U_0402_16V4Z~D

1

2

C377

0.1U_0402_16V4Z~D

1

2

R325 1K_0402_5%~D

12

R334 330_0402_5%~D

12

C380

0.1U_0402_16V4Z~D

1

2

R336 4.7K_0402_5%~D

1 2

C404

4.7U_0603_6.3V6M~D

1

2

C394

0.1U_0402_16V4Z~D

1

2

R338

1.18K_0402_1%~D

1 2

C393

470P_0402_50V7K~D

1

2

C406

4.7U_0603_6.3V6M~D

1

2

C398

22P_0402_50V8J~D

@

1

2

L37

BLM11A601S_0603~D

12

C392

10U_0805_10V4Z~D

1

2

R600

39K_0402_5%~D

@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DOCKED

DOCK_LED_100#

DOCK_LED_10#

LINK_LED100#

DOCK_LAN_ACTLED_YEL#

LAN_ACT#

LINK_100#

LINK_LED10#

LINK_LED100#

LAN_LEDACT# LAN_ACTLED_YEL_R#

LED_10_GRN_R#

LED_100_ORG_R#

LAN_TX3-

LAN_TX3+

LAN_TX2-

LAN_TX2+

LAN_TX1+

LAN_TX0+

LAN_TX1-

LINK_10#

LINK_LED10#

LAN_LEDACT#

RJ_TIP

RJ_RINGRJ_RING_L

RJ_TIP_L

NB_LAN_TX0+

NB_LAN_TX1+

NB_LAN_TX1-

NB_LAN_TX0-

NB_LAN_TX2+

NB_LAN_TX3+

NB_LAN_TX3-

NB_LAN_TX2-

LAN_TX0-

LAN_TX0+

LAN_TX1-

LAN_TX1+

LAN_TX2-

LAN_TX2+

LAN_TX3-

LAN_TX3+ LAN_TX3+R

LAN_TX3-R

LAN_TX0+R

LAN_TX0-R

LAN_TX2+R

LAN_TX2-R

LAN_TX1-R

LAN_TX1+R SW_LAN_TX3+

SW_LAN_TX3-

SW_LAN_TX0-

SW_LAN_TX0+

SW_LAN_TX2+

SW_LAN_TX2-

SW_LAN_TX1-

SW_LAN_TX1+

DOCK_LAN_TX0-

DOCK_LAN_TX0+

DOCK_LAN_TX1-

DOCK_LAN_TX1+

DOCK_LAN_TX2-

DOCK_LAN_TX2+

DOCK_LAN_TX3-

DOCK_LAN_TX3+

LAN_ACTLED_YEL_R#

LED_10_GRN_R#

LED_100_ORG_R#

SW_LAN_TX3- NB_LAN_TX3-

NB_LAN_TX1-

SW_LAN_TX1+

TRM_CT

NB_LAN_TX2-

Z2805

NB_LAN_TX2+

Z2807

SW_LAN_TX2+

NB_LAN_TX0-

NB_LAN_TX0+

Z2806

SW_LAN_TX1-

NB_LAN_TX1+

SW_LAN_TX0+

SW_LAN_TX3+

SW_LAN_TX0-

Z2808

NB_LAN_TX3+

SW_LAN_TX2-

LAN_TX0- +3.3V_LAN

+3.3V_LAN

+2.5V_LOM

+3.3V_LAN

DOCKED<38,39>

LAN_ACT#<29> LINK_10#<29> LINK_100#<29> DOCK_LAN_ACTLED_YEL# <38>

DOCK_LED_10# <38>

DOCK_LED_100# <38>

RJ_TIP_L<38>

RJ_RING_L<38>

LAN_TX0-<29>

LAN_TX0+<29>

LAN_TX2-<29>

LAN_TX2+<29>

LAN_TX3-<29>

LAN_TX3+<29>

DOCK_LAN_TX0- <38>

DOCK_LAN_TX0+ <38>

DOCK_LAN_TX1- <38>

DOCK_LAN_TX1+ <38>

DOCK_LAN_TX2- <38>

DOCK_LAN_TX2+ <38>

DOCK_LAN_TX3- <38>

DOCK_LAN_TX3+ <38>

LAN_TX1-<29>

LAN_TX1+<29>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

LAN TRANSFOMER

30 59Friday, May 12, 2006

TO

DOCK

FROM NIC DOCKED 1: TO DOCK

0: TO RJ45

LAN ANALOG

SWITCH

Layout Notice : Place bead as

close PI3L500 as possible

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Layout Notice : Place

termination as close as

ASIC as possible

The resistors need at

least 1/16W

GND

CHASIS

C642

300P_1808_3000V8K~D

@1

2

L47

FBMA-L11-160808-301LMA20T_2P~D

12

R342 48.7_0402_1%~D

1 2

C416 0.1U_0402_16V4Z~D

1 2

R349 48.7_0402_1%~D

1 2

R351

10K_0402_5%~D

@

12

L40 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

C417 0.1U_0402_16V4Z~D

1 2

L41 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

C421

0.1U_0402_10V6K~D

1

2

C418 0.1U_0402_16V4Z~D

1 2

R354 150_0402_5%~D

1 2

R346 48.7_0402_1%~D

1 2

L66

BLM11A601S_0603~D

12

R356 150_0402_5%~D

1 2

C420

0.1U_0402_10V6K~D

1

2

JPHON1

FOX_JM74613-P2002-7F~D

1

1

2

2

GND1

3

GND2

4

1:1

1:1

1:1

1:1

TR8

H5015NLT_24P~D

TCT1

1

TD1+

2

TD1-

3

TCT2

4

TD21+

5

TD2-

6

TCT3

7

TD3+

8

TD3-

9

TCT4

10

TD4+

11

TD4-

12 MX4- 13

MX3- 16

MCT3 18

MX2- 19

MX2+ 20

MCT2 21

MX1- 22

MX1+ 23

MCT1 24

MX4+ 14

MCT4 15

MX3+ 17

R355 150_0402_5%~D

1 2

R348 48.7_0402_1%~D

1 2

L39 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

R353

10K_0402_5%~D

@

12

C415 0.1U_0402_16V4Z~D

1 2

R359 75_0402_1%~D

12

R343 48.7_0402_1%~D

1 2

R344 48.7_0402_1%~D

1 2

L48

FBMA-L11-160808-301LMA20T_2P~D

12

L44 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

L42 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

JP2

FOX_JM36113-P2651-7F~D

PR1-

2

PR1+

1

PR2+

3

PR3+

4

PR3-

5

PR2-

6

PR4+

7

PR4-

8

LED_YELLOW- 13

SHLD1

15

LED_YELLOW+ 12

A2 11

LDE_GREEN- 10

LDE_ORANGE- 9

SHLD2

16

NC 14

R347 48.7_0402_1%~D

1 2

JP9

MOLEX_53780-0270~D

11

22

GND 3

GND 4

C419

0.1U_0402_10V6K~D

1

2

R358 75_0402_1%~D

12

R357 75_0402_1%~D

12

C422

0.1U_0402_10V6K~D

1

2

C423 1000P_1808_3KV7K~D

1 2

L43 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

L45 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

R360 75_0402_1%~D

12

C641

300P_1808_3000V8K~D

@1

2

L46 39NH_ 0603CS-390EJTS_5%_2P~D

1 2

R345 48.7_0402_1%~D

1 2

R352

10K_0402_5%~D

@

12

U31

PI3L500E_TQFN56~D

SEL

17

A0

2

A1

3

A2

7

A3

8

A4

11

A5

12

A6

14

0B1 48

0B2 46

1B1 47

1B2 45

2B1 43

2B2 41

3B1 42

3B2 40

4B1 37

4B2 35

5B1 36

5B2 34

6B1 32

6B2 30

7B1 31

7B2 29

A7

15

LED0

19

LED1

20

LED2

54

0LED1 22

0LED2 25

1LED1 23

1LED2 26

2LED1 52

2LED2 51

NC

5

VDD0 4

VDD1 10

VDD2 18

VDD3 27

VDD4 38

VDD5 50

VDD6 56

GND0

1

GND1

6

GND2

9

GND3

13

GND4

16

GND5

21

GND6

24

GND7

28

GND8

33

GND9

39

GND10

44

GND11

49

GND12

53

GND13

55

GND P

57

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CBS_CSTSCHNG

CBS_CCLKRUN#

CBS_CCLK_INTERNAL

CBS_CINT#

CBS_CAUDIO

CBS_RSVD/A18

CBS_RSVD/D14

CBS_RSVD/D2

CBS_CCD2#_R5C843

CBS_CVS2

CBS_CVS1

PCI_AD29

PCI_AD30

PCI_AD28

PCI_AD31

PCI_AD26

PCI_AD25

PCI_AD27

PCI_AD22

PCI_AD23

PCI_AD20

PCI_AD24

PCI_AD21

PCI_AD18

PCI_AD17

PCI_AD19

PCI_AD14

PCI_AD16

PCI_AD13

PCI_AD15

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD7

PCI_AD6

PCI_AD8

PCI_AD4

PCI_AD5

PCI_AD1

PCI_AD2

PCI_AD3

PCI_AD0

PCI_C_BE3#

PCI_C_BE0#

PCI_C_BE2#

PCI_C_BE1#

PCI_PAR

PCI_FRAME#

PCI_STOP#

PCI_DEVSEL#

PCI_TRDY#

PCI_IRDY#

PCI_AD17 CBS_IDSEL

PCI_REQ2#

PCI_GNT2#

PCI_PERR#

PCI_SERR#

CBUS_GRST#

PCI_RST#

CLK_PCI_PCCARD

IEEE1394_TPBN0

CK33M_CBS_TERM

CLK_PCI_PCCARD

CBS_CAD15

CBS_CAD13

CBS_CC/BE3#

CBS_CC/BE2#

CBS_CC/BE0#

CBS_CC/BE1#

CBS_CPAR

CBS_CDEVSEL#

CBS_CTRDY#

CBS_CFRAME#

CBS_CIRDY#

CBS_CSTOP#

CBS_CPERR#

CBS_CREQ#

CBS_CGNT#

CBS_CBLOCK#

CBUS_GRST#

CBS_SPK

IEEE1394_TPAP0

IEEE1394_TPBP0

R5C843XI

IEEE1394_TPBN0

IEEE1394_TPAN0

IEEE1394_TPAP0

R5C843XI

SD_CLK

SD_EN

R5C843XO

IEEE1394_TPBIAS0

TPB0+

TPA0+

TPA0-

TPB0-

CBS_CCD1#_R5C843

CLK_SD_48M

CK48M_SD

CLK_SD_48M

R5C843XO

SD_EN

IEEE1394_TPBP0

IEEE1394_TPBIAS0

IEEE1394_TPAN0

Z3008

MDIO06

USB_HUBP1+

USB_HUBP1-

CBS_CRST#

CBS_CSERR#

+3.3V_RUN_PHY

+3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

+3.3V_RUN_CARD+3.3V_R5C843

+3.3V_R5C843

VPPEN0<32>

SD_CMD <32>

CLKRUN#<24,39,40>

CBS_CCLKRUN# <32>

CBS_CSTSCHNG <32>

CBS_CCLK <32>

CBS_CRST# <32>

CBS_CINT# <32>

CBS_CAUDIO <32>

CBS_RSVD/D2 <32>

CBS_RSVD/D14 <32>

CBS_RSVD/A18 <32>

PCI_AD[0..31]<22,37>

PCI_C_BE3#<22,37>

PCI_C_BE1#<22,37> PCI_C_BE0#<22,37>

PCI_C_BE2#<22,37>

PCI_PAR<22,37>

PCI_TRDY#<22,37> PCI_FRAME#<22,37,38>

PCI_IRDY#<22,37,38> PCI_STOP#<22,37> PCI_DEVSEL#<22,37>

PCI_GNT2#<22> PCI_REQ2#<22>

PCI_RST#<22,35,37>

CLK_PCI_PCCARD<6>

CBS_CAD0 <32>

CBS_CAD19 <32>

CBS_CAD17 <32>

CBS_CAD18 <32>

CBS_CAD15 <32>

CBS_CAD12 <32>

CBS_CAD14 <32>

CBS_CAD11 <32>

CBS_CAD10 <32>

CBS_CAD9 <32>

CBS_CAD8 <32>

CBS_CAD7 <32>

CBS_CAD6 <32>

CBS_CAD5 <32>

CBS_CAD4 <32>

CBS_CAD3 <32>

CBS_CAD2 <32>

CBS_CAD1 <32>

CBS_CAD31 <32>

CBS_CAD29 <32>

CBS_CAD27 <32>

CBS_CAD23 <32>

CBS_CAD24 <32>

CBS_CAD28 <32>

CBS_CAD26 <32>

CBS_CAD21 <32>

CBS_CAD20 <32>

CBS_CAD30 <32>

CBS_CAD25 <32>

CBS_CAD13 <32>

CBS_CAD16 <32>

CBS_CAD22 <32>

CBS_CC/BE3# <32>

CBS_CC/BE1# <32>

CBS_CC/BE2# <32>

CBS_CC/BE0# <32>

CBS_CPAR <32>

CBS_CREQ# <32>

CBS_CGNT# <32>

CBS_CPERR# <32>

CBS_CFRAME# <32>

CBS_CTRDY# <32>

CBS_CSTOP# <32>

CBS_CIRDY# <32>

CBS_CBLOCK# <32>

CBS_CDEVSEL# <32>

IRQ_SERIRQ<24,29,39,40>

CB_HWSPND#<39>

SD_DET# <32>

PCI_PIRQD#<22>

SD_CLK <32>

VPPEN1<32>

VCC5EN#<32> VCC3EN#<32>

PCI_PIRQC#<22> PCI_PIRQB#<22>

USB_HUBP1+<32,39> USB_HUBP1-<32,39>

PCI_PERR#<22,37>

PCI_SERR#<22,37>

CBUS_GRST#<39>

SYS_PME#<37,39>

CBS_CSERR# <32>

CLK_SD_48M <6>

SD_WP# <32>

SD_DATA0 <32>

SD_DATA1 <32>

SD_DATA2 <32>

SD_DATA3 <32>

CBS_CVS1 <32>

CBS_CVS2 <32>

CBS_CCD1#_R5C843 <32>

CBS_CCD2#_R5C843 <32>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

CardBus Controller(R5C843)

31 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Close to U32.A16,B16

Close to U32.A14

Close to U32.D13,B14

Close to J1

Close to U32

Close to JP5 pin5 Close to JP5 pin5

C428 Close Cardbus connector

C424, C425 need to

test the starting

vaule, then modify

the value

R373 10K_0402_5%~D

1 2

R377

56.2_0402_1%~D

12

R363

100K_0402_5%~D

12

R5C843

U32A

R5C843-CSP208P_CSP208~D

AD31

M2

AD30

M1

AD29

N5

AD28

N4

AD27

N2

AD26

N1

AD25

P5

AD24

P4

AD23

R4

AD22

R2

AD21

R1

AD20

T2

AD19

T1

AD18

U2

AD17

U1

AD16

V1

AD15

T7

AD14

V7

AD13

W7

AD12

R8

AD11

T8

AD10

V8

AD9

W8

AD8

R9

AD7

V9

AD6

W9

AD5

T11

AD4

V11

AD3

W11

AD2

T12

AD1

V12

AD0

W12

PAR

V6

DEVSEL#

T5

FRAME#

V3

GNT#

M5

IDSEL

P1

IRDY#

V4

PERR#

W5

REQ#

M4

SERR#

T6

STOP#

V5

TRDY#

W4

CCLK/CADR16 L19

CCLKRUN#/WP(IOIS16#) A18

CRST#/RESET H19

RESERVED/CDATA2 C19

RESERVED/CDATA14 W18

RESERVED/CADR18 N16

CAD31/CDATA10 B19

CAD30/CDATA9 C18

CAD29/CDATA1 D19

CAD28/CDATA8 D18

CAD27/CDATA0 E19

CAD26/CADR0 E16

CAD25/CADR1 F18

CAD24/CADR2 F15

CAD23/CADR3 G18

CAD22/CADR4 G15

CAD21/CADR5 H18

CAD20/CADR6 H15

CAD19/CADR25 J18

CAD18/CADR7 J16

CAD17/CADR24 J15

CAD16/CADR17 P16

CAD15/IOWR# P19

CAD14/CADR9 R19

CAD13/IORD# P18

CAD12/CADR11 R18

CAD11/OE# T19

CAD10/CE2# T18

CAD9/CADR10 U19

CAD8/CDATA15 U18

CAD7/CDATA7 W17

CAD6/CDATA13 V17

CAD5/CDATA6 W16

CAD4/CDATA12 V16

CAD3/CDATA5 W15

CAD2/CDATA11 V15

CAD1/CDATA4 T15

CAD0/CDATA3 R14

CC/BE3#/REG# F16

CC/BE2#/CADR12 K18

CC/BE1#/CADR8 P15

CC/BE0#/CE1# V19

CPAR/CADR13 N15

CAUDIO/BVD2(SPKR#/LED) F19

RESERVED/CADR19 N19

CCD1#/CD1# T14

CCD2#/CD2# D15

CDEVSEL#/CADR21 L18

CFRAME#/CADR23 K16

CGNT#/WE# M15

CINT#/RDY(IREQ#) M18

CIRDY#/CADR15 K15

CREQ#/INPACK# G19

CSTOP#/CADR20 M16

CSTSCHG/BVD1(STSCHG#/RI#) E18

CTRDY#/CADR22 L16

CVS1/VS1# R16

CVS2/VS2# H16

PCICLK

K1

PCIRST#

L4

GBRST#

G2

CPERR#/CADR14 N18

CSERR#/WAIT# G16

HWSPND#

F2

CLKRUN#

L5

INTA#

J2

C/BE3#

P2

C/BE2#

W2

C/BE1#

W6

C/BE0#

T9

INTB#

K4

INTC#

K2

UDIO0/SERIRQ#

J4

UDIO1

H1

UDIO2

H2

UDIO3

H4

UDIO4

H5

UDIO5

G1

RI_OUT#/PME#

G4

SPKROUT

F1

TEST

F4

C426

0.01U_0402_16V7K~D

1 2

R365 22_0402_5%~D 12

C653

4.7P_0402_50V8C~D

@

1

2

C683

0.1U_0402_16V4Z~D

1

2

R362100_0402_5%~D

1 2

C435

1U_0603_10V4Z~D

1

2

L49

857CM-0009~D

@

1

1

2

23

3

4

455

66

77

88

R5C843

U32B

R5C843-CSP208P_CSP208~D

CPS

D11

TPAP1

B10

TPAP0

B12

TPAN0

A12

TPBP0

B13

TPBN0

A13

TPBIAS0

D12

XO

B16 XI

A16

TPAN1

A10

TPBP1

B11

TPBN1

A11

VREF

D13

REXT

B14

MDIO00 B1

MDIO01 A2

MDIO02 A3

MDIO03 B3

MDIO04 B4

MDIO05 A5

MDIO06 B5

MDIO07 D5

MDIO08 A6

MDIO09 B6

MDIO10 D6

MDIO11 E6

MDIO12 A7

MDIO13 B7

MDIO14 D7

MDIO15 E7

MDIO16 A8

MDIO17 B8

MDIO18 D8

MDIO19 E8

FIL0

A14

TPBIAS1

D10

USBDP

V14

USBDM

W14

VPPEN0

V13

VPPEN1

W13

VCC5EN#

R13

VCC3EN#

T13

REGEN#

R7

C431

0.1U_0402_16V4Z~D

1

2

C428 0.01U_0402_16V7K~D

1 2

R618

150K_0402_5%~D

1 2

R381

56.2_0402_1%~D

12

C436

4.7P_0402_50V8C~D

@

1

2

R384 0_0402_5%~D

12

C433

0.01U_0402_16V7K~D

1

2

X4

24.576MHz_16P_1BG24576CKIA~D

1 2

C432

1U_0603_10V4Z~D

1

2

R383 0_0402_5%~D

12

R374 100K_0402_5%~D

1 2

R647 33_0402_5%~D

12

R376

56.2_0402_1%~D

12

R372 10K_0402_5%~D

1 2

R366

100K_0402_5%~D

@

12

C717 100P_0402_50V8J~D

12

R379

100K_0402_5%~D

12

C425

18P_0402_50V8J~D

12

R595 0_0402_5%~D@12

C720 100P_0402_50V8J~D

12

R367 0_0402_5%~D

1 2

C434

0.33U_0603_10V7K~D

1

2

R609 0_0402_5%~D@12

R378

10_0402_5%~D

@

12

C427

0.01U_0402_16V7K~D

1

2

R606 0_0402_5%~D

12

R646 33_0402_5%~D

12

C424

18P_0402_50V8J~D

12

U33

AAT4250IGV-T1_SOT23-5~D

IN

5

ON/OFF#

4

OUT 1

GND 2

N.C 3

R371 10K_0402_5%~D

1 2

R386 0_0402_5%~D

12

R648 33_0402_5%~D

12

R645 33_0402_5%~D

12

R607

10_0402_5%~D

@

12

C437

270P_0402_50V7K~D

1

2

J1

FOX_UV31413-4TA-7F~D

A+

4

A-

3

B+

2

B-

1

GND

5GND

6

C719 100P_0402_50V8J~D

12

R385

5.1K_0402_1%~D

1 2

R364

100K_0402_5%~D

12

T16PAD~D

R617 0_0402_5%~D

12

R593 0_0402_5%~D@12

C718 100P_0402_50V8J~D

12

R361

10K_0402_5%~D

12

R382 0_0402_5%~D

12

R380

56.2_0402_1%~D

12

R594 33_0402_5%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CBS_CAD17

CBS_CAD13

CBS_CIRDY#

CBS_CPAR

CBS_CC/BE1#

CBS_CAD30

CBS_CC/BE3#

CBS_RSVD/D14

CBS_CAD10

CBS_CAD27

CBS_CREQ#

CBS_CBLOCK#

CBS_CAD15

CBS_CAD29

CBS_CC/BE0#

CBS_CAD16

CBS_CAD21

CBS_CGNT#

CBS_CAD9

CBS_CAD7

CBS_CAD0

CBS_RSVD/A18

CBS_CAD14

CBS_CAD4

CBS_CFRAME#

CBS_CVS1

CBS_CRST#

CBS_CCLK

CBS_CAD11

CBS_CAD31

CBS_CVS2

CBS_CAD25

CBS_CSERR#

CBS_CAD19

CBS_RSVD/D2

CBS_CPERR#

CBS_CAD5

CBS_CTRDY#

CBS_CAD6

CBS_CAD2

CBS_CCLKRUN#

CBS_CAD23

CBS_CAD1

CBS_CAD24

CBS_CC/BE2#

CBS_CAD12

CBS_CSTOP#

CBS_CAD18

CBS_CINT#

CBS_CAD3

CBS_CDEVSEL#

CBS_CAD26

CBS_CAD20

CBS_CSTSCHNG

CBS_CAD28

CBS_CAUDIO

CBS_CAD8

CBS_CAD22

SD_WP#

UIM_RESET

UIM_CLK

UIM_DATA

+UIM_VPP

USB_HUBP1- CBS_CAD15

EXUSB_EN#

EXUSB_EN#

EXUSB_EN#

VCC3EN#_R5531

CBS_CAD13 USB_HUBP1+

CBS_CCD1#_R5C843

CBS_CCD2#_R5C843

EXUSB_EN#_CCD EXUSB_EN#

CBS_CCD2#

EXUSB_EN#_CCD

CBS_CCD1#

CBS_CCD2#

CBS_CCD1#

VCC3EN#_R5531

CBS_VPP

CBS_VCC

+3.3V_RUN_PHY

+3.3V_RUN_PHY

+3.3V_RUN_CARD

+3.3V_R5C843

+3.3V_R5C843

+5V_RUN

+3.3V_RUN +3.3V_R5C843 +3.3V_R5C843

+3.3V_R5C843

+SIM_PWR

+UIM_VPP

CBS_VCC

CBS_VPP

+SC_PWR

+3.3V_R5C843

CBS_VCC

+SC_PWR

CBS_VCC

CBS_VPP

+SIM_PWR

+3.3V_R5C843 +3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

+3.3V_R5C843

VPPEN0<31> VPPEN1<31>

VCC5EN#<31>

SD_CLK<31>

CBS_CAD[0..31]<31>

SD_WP#<31>

SD_CMD<31>

UIM_CLK<36> UIM_RESET<36> UIM_DATA<36> CBS_CRST#<31>

CBS_CAUDIO<31> CBS_CC/BE3#<31> CBS_CREQ#<31>CBS_CSERR#<31>

CBS_CFRAME#<31> CBS_CTRDY#<31>

CBS_CDEVSEL#<31> CBS_CSTOP#<31>CBS_CBLOCK#<31> CBS_RSVD/A18<31>

CBS_CIRDY# <31>

CBS_RSVD/D2 <31>

CBS_CCLKRUN# <31>

SCCD-<35>

CBS_RSVD/D14<31>

CBS_CPAR <31>

CBS_CCLK <31>

SC_IO_R<35>

CBS_CC/BE1# <31>

CBS_CINT# <31>

CBS_CC/BE2# <31>

SCCD+ <35>

CBS_CSTSCHNG<31>

CBS_CC/BE0# <31>

CBS_CGNT# <31>

SC_DET# <35,39>

CBS_CPERR# <31>

SD_DET#<31>

EXUSB_EN# <39>

USB_HUBP1-<31,39>

VCC3EN#<31>

USB_HUBP1+ <31,39>

SD_DATA1<31> SD_DATA0<31>

SD_DATA3<31> SD_DATA2<31>

CBS_CCD2#<39>

CBS_CCD1#_R5C843 <31>

CBS_CCD2#_R5C843 <31>

SC_RST#_R <35>

SC_CLK_R <35>

CBS_CVS1<31>

CBS_CVS2<31>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

CardBus/SD card Socket

32 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SIM & SD CARD will combine together,

the connector will update to 18pin

Close to U32

USB signal,impedance

90ohm,trace

width/space=5/6

Close to JCBUS1 pin22,62

Close to JCBUS1 pin23,63

C429, C430 Close Cardbus connector

C430

270P_0402_50V7K~D

@

1 2

C707

0.01U_0402_16V7K~D

1

2

C447

10U_0805_10V4Z~D

1

2

C684

0.01U_0402_16V7K~D

1

2

C455

0.1U_0402_16V4Z~D

1

2

C445

0.01U_0402_16V7K~D

1

2

C722

0.1U_0402_16V4Z~D

1 2

R592 0_0805_5%~D

1 2

C715

0.1U_0402_16V4Z~D

1 2

C429

270P_0402_50V7K~D

@ 1 2

C466

0.1U_0402_16V4Z~D

1

2

C444

0.01U_0402_16V7K~D

1

2

C463

0.01U_0402_16V7K~D

1

2

C506

33P_0402_50V8J~D

1

2

C708

10U_0805_10V4Z~D

1

2

R656 0_0402_5%~D@12

U62

74AHC1G08GW_SOT353-5~D

IN1

1

IN2

2

G

3

O4

P5

JP5

HRS_FH12-40(19)SA-1SH(55) ~D

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

16

16

17

17

18

18

15

15

GND

20

GND

21

19

19

C504

1U_0603_10V4Z~D

1

2

C457

0.01U_0402_16V7K~D

1

2

C505

33P_0402_50V8J~D

1

2

C716

0.1U_0402_16V4Z~D

1 2

C456

0.01U_0402_16V7K~D

1

2

U63B

SN74CB3Q3306APWR_TSSOP8~D

2A

52B 6

2OE 7

G

4P8

R654 0_0402_5%~D@12

C443

10U_0805_10V4Z~D

1

2

C508

33P_0402_50V8J~D

1

2

U65B

SN74CB3Q3306APWR_TSSOP8~D

2A

52B 6

2OE 7

G

4P8

C467

0.01U_0402_16V7K~D

1

2

U65A

SN74CB3Q3306APWR_TSSOP8~D

1A

21B 3

P8

1OE 1

G

4

C446

0.01U_0402_16V7K~D

1

2

C441

0.01U_0402_16V7K~D

1

2

C448

0.01U_0402_16V7K~D

1

2

D12

NNCD5.6LG~D

@

2

3

1

4

5

C462

0.1U_0402_16V4Z~D

1

2

C454

10U_0805_10V4Z~D

1

2

L50

BLM21A601SPT_0805~D

1 2

R659

10K_0402_5%~D

1 2

C461

0.47U_0603_16V4Z~D

1

2

C709

0.01U_0402_16V7K~D

1

2

R5C843

U32C

R5C843-CSP208P_CSP208~D

VCC_3V1

F5

VCC_3V2

G5

VCC_3V3

J19

VCC_3V4

K19

VCC_PCI3V1

W3

VCC_PCI3V2

R11

VCC_PCI3V3

R12

VCC_MD3V

A4

VCC_RIN1

R6

VCC_RIN2

E13

VCC_ROUT1

L1

AGND1

A9

AGND2

B9

AGND3

D9

VCC_ROUT2

E14

AVCC_PHY1

E10

AVCC_PHY2

E11

AVCC_PHY3

A17

GND1

J1

GND2

J5

GND3

K5

GND4

E9

GND5

R10

GND6

T10

GND7

V10

GND8

W10

GND9

L15

GND10

M19

NC1 L2

NC2 C1

NC3 D1

NC4 E1

NC5 C2

NC6 D2

NC7 E2

NC8 E4

NC9 E12

AVCC_PHY4

B17

AGND4

D14

AGND5

A15

AGND6

B15

JCBUS1

FOX_QTS0080A-1021-9F~D

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

42 42

44 44

46 46

48 48

54 54

50 50

52 52

56 56

58 58

64 64

60 60

62 62

66 66

68 68

72 72

70 70

74 74

76 76

78 78

80 80

3

35

57

79

9

15

15

11

11 13

13

17

17 19

19

23

23

21

21

25

25 27

27 29

29 31

31 33

33 35

35 37

37 39

39 41

41 43

43 45

45 47

47

53

53

49

49 51

51

55

55 57

57

63

63

59

59 61

61

65

65 67

67

71

71

69

69

73

73 75

75 77

77

1

1

79

79

U34

R5531V002-E2-FA_SSOP16~D

VCC3IN

11

NC 10

VCC5_EN

1

EN0

3

EN1

4

FLG

5

VCCOUT 12

VCCOUT 14

VCC5IN

15

VCC3_EN

2

VPPOUT 8

NC 7

NC 6

GND

16

VCC5IN

13

VCCOUT 9

C458

0.01U_0402_16V7K~D

1

2

C451

1000P_0402_50V7K~D

1

2

R652

10K_0402_5%~D

1 2

C450

1000P_0402_50V7K~D

1

2

C460

0.47U_0603_16V4Z~D

1

2

R655

0_0402_5%~D

@12

C459

0.01U_0402_16V7K~D

1

2

C442

0.01U_0402_16V7K~D

1

2

C453

0.01U_0402_16V7K~D

1

2

C439

0.01U_0402_16V7K~D

1

2

C438

10U_0805_10V4Z~D

1

2

U63A

SN74CB3Q3306APWR_TSSOP8~D

1A

21B 3

P8

1OE 1

G

4

C440

0.01U_0402_16V7K~D

1

2

C465

0.1U_0402_16V4Z~D

1

2

U64

NC7SZ04P5X_NL_SC70-5~D

A2

Y

4

P5

NC 1

G

3

C464

10U_0805_10V4Z~D

1

2

C449

0.01U_0402_16V7K~D

1

2

C507

33P_0402_50V8J~D

1

2

C723

0.1U_0402_16V4Z~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_OC4#

USB_OC5#

USB_OC6#USB_BACK_EN#

USBP6_D-

USBP6_D+

USBP4-

USBP4_D+

USBP6_D+

USBP6_D-

USBP4_D+

USBP4_D-

USBP5_D-

USBP5_D+

DH_SMBCLK

DH_SMBDAT

PORT_PWRUSB_SRC

DH_SMBDAT

PWRUSB_SMBEN

DH_SMBCLKCLK_SMB

DAT_SMB

Z2501

Z2502

PWRUSB_SRC

USBP5+

USBP5-

USBP5_D+

USBP5_D-

PORT_PWRUSB_SRC

USB_BACK_EN#

USBP5+

USBP5-

USBP4_D-

USBP4+

USBP6+ USBP4-

USBP4+

USBP6-

USBP6-

USBP6+

+USB_BACK_PWR

+USB_BACK_PWR

+USBP5_PWR

+USBP5_PWR

+PWR_SRC

+5V_SUS

+5V_SUS

+USB_BACK_PWR

+USBP5_PWR

USB_OC4# <24>

USB_OC5# <24>

USB_OC6# <24>USB_BACK_EN#<39>

USBP4-<24>

USBP4+<24>

USBP6-<24>

USBP6+<24>

CLK_SMB<18,40>

PWRUSB_EN <39>

PWRUSB_OC#<39>

DBAY_MODPRES#<39>

USB_BACK_EN#<39>

USBP5+<24>

USBP5-<24>

DAT_SMB<18,40>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

USB 2.0 Port

33 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

USB Port

Rear USB Ports

C476

10U_0805_10V4Z~D

1

2

+

C468

150U_D_6.3VM_R55~D

1

2

L53 DLW21SN900SQ2_0805~D@

1

1

4

433

22

C482

0.1U_0603_50V4Z~D

1

2

C480

10U_0805_10V4Z~D

1

2

+

C473

150U_D_6.3VM_R55~D

1

2

R394

0_0402_5%~D

1 2

U21

IP4220CZ6_SO6~D

@

D2+ 4

D1- 6

VCC 5

D1+

1

GND

2

D2-

3

C475

0.1U_0402_16V4Z~D

1

2

F1

1.5A_24V_MINISMDC150F/24~D

1 2

C623

0.1U_0603_50V4Z~D

1

2

C622

1000P_0402_50V7K~D

@1

2

C472

0.1U_0402_16V4Z~D

1

2

R399

100K_0402_5%~D

12

L58

MURATA BLM31PG500SNI_1206~D

1 2

R401

100K_0402_5%~D

1 2

G

D

S

Q27

2N7002W-7-F_SOT323~D

2

1 3

R398

0_0402_5%~D

1 2

JDOG1

FOX_UB1112C-PB202-7F_9P~D

T1

1

T2

2

T3

3

T4

4

PWR_SRC

5

SMB_DATA

6

SMB_ALERT

7

SMB_CLK

8

GND2

9

SHLD1 10

SHLD2 11

SHLD3 12

SHLD4 13

L57 DLW21SN900SQ2_0805~D

@

1

1

4

433

22

U20

PRTR5V0U2X_SOT143-4~D

@

GND

1

IO1

2

IO2 3

VIN 4

R397

0_0402_5%~D

1 2

G

D

S

Q29

2N7002W-7-F_SOT323~D

2

13

R403

150_0402_5%~D

1 2

C474

0.1U_0402_16V4Z~D

1

2

JP12

SUYIN_020173MR004S558ZL~D

VCC

4

D-

3

D+

2

GND

1

GND 5

GND 6

GND 7

GND 8

R406

200K_0402_5%~D

12

C481

0.1U_0603_50V4Z~D

1

2

JP11

SUYIN_020173MR004S558ZL~D

VCC

4

D-

3

D+

2

GND

1

GND 5

GND 6

GND 7

GND 8

R404

100K_0402_5%~D

12

U35

TPS2062DR_SO8~D

GND

1

IN

2

EN1#

3

EN2#

4

OC1# 8

OUT1 7

OUT2 6

OC2# 5

R395

0_0402_5%~D

1 2

G

D

S

Q30

2N7002W-7-F_SOT323~D

@2

13

R393

0_0402_5%~D

1 2

C469

0.1U_0402_16V4Z~D

1

2

U37

TPS2062DR_SO8~D

GND

1

IN

2

EN1#

3

EN2#

4

OC1# 8

OUT1 7

OUT2 6

OC2# 5

C479

0.1U_0402_16V4Z~D

1

2

R396

0_0402_5%~D

1 2

L56 DLW21SN900SQ2_0805~D@

1

1

4

433

22

Q25

FDS4435_NL_SO8~D

4

7

8

6

5

1

2

3

G

D

S

Q26

2N7002W-7-F_SOT323~D

2

1 3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ICH_AZ_MDC_BITCLK

ICH_AZ_MDC_SYNC

ICH_AZ_MDC_SDOUT

ICH_AC_SDOUT_MDCTERM

ICH_AZ_MDC_SDOUT

MDC_AC_BITCLK_TERM

MDC_SDIN

ICH_AZ_MDC_BITCLK

ICH_RST_MDC_R#

ICH_AZ_MDC_SYNC

ICH_AZ_MDC_SDOUT

ICH_AZ_MDC_RST#

COEX2_WLAN_ACTIVE

COEX1_BT_ACTIVE COEX3

BT_RADIO_DIS#

ICH_RST_MDC_R#

BT_ACTIVE

+3.3V_RUN

+3.3V_SUS

+5V_SUS

ICH_AZ_MDC_SYNC<23>

ICH_AZ_MDC_BITCLK<23>

ICH_AZ_MDC_SDOUT<23>

COEX2_WLAN_ACTIVE<36>

COEX1_BT_ACTIVE<36>

BT_RADIO_DIS#<24>

USB_HUBP4-<39>

USB_HUBP4+<39>

MDC_RST_DIS#<39>

ICH_AZ_MDC_RST#<23>

BT_ACTIVE<36,44>

ICH_AZ_MDC_SDIN1<23>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

BT PORT & MDC

34 59Friday, May 12, 2006

Compal Electronics, Inc.

1

3

5

7

9

11 12

10

8

6

4

2

GND

IAC_SDATA0

IAC_SYNC

IAC_SDATAIN

IAC_RESET#

RES

RES

3.3V

GND

GND

IAC_BITCLK

GND

New MDC connector.

W=20 mil

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Bluetooth

R410

100K_0402_5%~D

12

JBT1

JST_SM10B-SRSS-TB1(LF)(SN)~D

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

GND 11

GND 12

R409

0_0402_5%~D

@

1 2

C492

10P_0402_50V8J~D@

1 2

C488

10P_0402_50V8J~D@

1 2

T9 PAD~D

G

D

S

Q32

BSS138W-7-F_SOT323~D

2

1 3

C486

4.7U_0603_6.3V6M~D

1

2

C483

0.1U_0402_16V4Z~D

1

2

R407

10K_0402_5%~D

12

C490

10P_0402_50V8J~D

@

1

2

R411

10K_0402_5%~D

12

C484

33P_0402_50V8J~D

1

2

Connector for MDC Rev1.5

JMDC1

TYCO_1-179397-2~D

GND1

1

IAC_SDATA_OUT

3

GND2

5

IAC_SYNC

7

IAC_SDATA_IN

9

IAC_RESET#

11

RES0 2

RES1 4

3.3V 6

GND3 8

GND4 10

IAC_BITCLK 12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

R413

10_0402_5%~D@

1 2

C487

0.1U_0402_16V4Z~D

1

2

R414

33_0402_5%~D

1 2

R408

10K_0402_5%~D

12

C489

10P_0402_50V8J~D

@

1

2

C485

100P_0402_50V8J~D

@

1

2

C491

10P_0402_50V8J~D@

1 2

R412

10_0402_5%~D@

1 2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SC_RST#_R

SC_CLK_R

SC_IO_R

CLK_SMCARD_48M

MD0

SC_RST#

SCCD+

SC_IO

SCCD-

SC_DET#

CLK_SMCARD_48M

PCI_RST#

SCCD-

SCCD+

VRCPR

+SC_PWR

USB_HUBP3-

SC_CLK

USB_HUBP3+

SC_C4

HUB_USB_BIO+

HUB_USB_BIO-

+SC_PWR

+3.3V_OUT

+3.3V_RUN

+5V_RUN

CLK_SMCARD_48M<6>

PCI_RST#<22,31,37>

USB_HUBP3+<39> USB_HUBP3-<39>

SC_DET# <32,39>

SC_CLK_R <32>

SC_RST#_R <32>

SC_IO_R <32>

USB_BIO- <41>

USB_BIO+ <41>

SCCD+ <32>

SCCD- <32>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Smart Card OZ77C6

35 59Friday, May 12, 2006

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

USB SMARTCARD READER.

& USB SMARTCARDS ARE SUPPORTED.

TYPE A (5V), B (3V), AB (5V/3V)

Place closely pin 3

Close to Smart Card Conn.

<---Fingerprint

C724

47P_0402_50V8J~D

@

1

2

R415

15K_0402_5%~D

12

C502

1U_0603_10V4Z~D

12

C494

0.1U_0402_16V4Z~D

1

2

C503

4.7P_0402_50V8C~D

@

1

2

C496

0.1U_0402_16V4Z~D

1

2

R563

15K_0402_5%~D

1 2

R416

15K_0402_5%~D

12

C497

0.1U_0402_16V4Z~D

1

2

C501

0.1U_0402_16V4Z~D

1

2

R658 33_0402_5%~D 1 2

R418

10K_0402_5%~D

12

R424 220_0402_5%~D

12

C495

4.7U_0603_6.3V6M~D

1

2

R417

1.5K_0402_1%~D

12

R657 33_0402_5%~D 1 2

R422 220_0402_5%~D

12

R562

15K_0402_5%~D

1 2

R420

47K_0402_5%~D

12

L67

DLW21SN900SQ2_0805~D

@

1

1

4

433

22

R426

4.7K_0402_5%~D

12

C725

47P_0402_50V8J~D

@

1

2

R425 220_0402_5%~D

12

C498

4.7U_0603_6.3V6M~D

1

2

R423 33_0402_5%~D

12

U38

OZ77C6LN-B1_QFN32~D

VCC5V_IN

5

VCC5V_IN

28

UPD-

17

UPD+

16

RST#

14

NC

30

NC

31

XI/48M_IN

3

XO

4

MODE0/SC_LED#

32

MODE1

1

MODE2

2

GND

11

GND

13

GND

26

+3.3V_OUT 29

DPD- 19

DPD+ 18

EGATED- 21

EGATED+ 20

SC_VCC 27

SC_RST# 24

SC_CLK 23

SC_C4 22

SC_IO 25

SC_DET# 15

RF_OUT 8

RF_IN/RX 7

RF_CLK 9

RF_AUX 10

VR_CPR

6

VR_CPR

12

R427

10_0402_5%~D

@

12

C500

1U_0603_10V4Z~D

1

2

C499

0.1U_0402_16V4Z~D

1

2

C493

4.7U_0603_6.3V6M~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_HUBP2_D+

ICH_SMBCLK

USB_HUBP2_D-

ICH_SMBDATA

WWAN_RADIO_DIS#

LED_WLAN_OUT#

PCIE_IRX_WLANTX_N2

PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_N2_C

PCIE_ITX_WLANRX_P2_C

WLAN_RADIO_OFF#

PLTRST#

UIM_DATA

UIM_CLK

+UIM_VPP

PCIE_IRX_WANTX_N1

PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_N1_C

PCIE_ITX_WANRX_P1_C

USB_HUBP2_D-

USB_HUBP2_D+

CLK_PCIE_MINI1#

CLK_PCIE_MINI1

MINI1CLK_REQ#

PLTRST#

PCIE_WAKE#

UIM_RESET

WLAN_RADIO_OFF#

COEX2

COEX1

+3.3V_LAN

+SIM_PWR

+3.3V_LAN

+3.3V_RUN +3.3V_RUN

+3.3V_RUN+3.3V_RUN

+3.3V_RUN

+3.3V_RUN +3.3V_LAN

+3.3V_LAN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+UIM_VPP

COEX1_BT_ACTIVE<34> COEX2_WLAN_ACTIVE<34>

PCIE_IRX_WLANTX_N2<24> PCIE_IRX_WLANTX_P2<24>

MINI2CLK_REQ#<6>

PCIE_ITX_WLANRX_N2_C<24> PCIE_ITX_WLANRX_P2_C<24>

PCIE_IRX_WANTX_N1<24>

PCIE_IRX_WANTX_P1<24>

PCIE_ITX_WANRX_N1_C<24> PCIE_ITX_WANRX_P1_C<24>

USB_HUBP2+<39>

USB_HUBP2-<39>

MINI1CLK_REQ#<6>

PLTRST# <10,20,22,24,29>

PLTRST# <10,20,22,24,29>

PCIE_WAKE#<29,39>

PCIE_WAKE#<29,39>

WWAN_RADIO_DIS# <24>

LED_WLAN_OUT# <44>

BT_ACTIVE <34,44>

UIM_CLK <32>

UIM_RESET <32>

USBP0+ <24>

USBP0- <24>

HOST_DEBUG_TX <40>

HOST_DEBUG_RX<40>

8051RX <40>

8051TX<40>

WLAN_RADIO_DIS#<39>

CLK_PCIE_MINI2#<6> CLK_PCIE_MINI2<6>

ICH_SMBDATA <6,24,29>

ICH_SMBCLK <6,24,29>

CLK_PCIE_MINI1#<6> CLK_PCIE_MINI1<6>

UIM_DATA <32>

ICH_SMBDATA <6,24,29>

ICH_SMBCLK <6,24,29>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Mini Card

36 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+-9%

+3.3Vaux

+3.3V

Voltage

Tolerance

+1.5V

+-9%

+-5%

PWR

Rail

Primary Power Aux Power

Peak Normal Normal

1000 750

330

500

250

375

250 (Wake enable)

5 (Not wake enable)

NA

Mini Card

Wire less WAN

Wire less LAN

Mini Card

Mini-Card Latch

Mini-Card Latch

C521

0.047U_0402_16V4Z~D

1

2

C524

4.7U_0603_6.3V6M~D

1

2

JCLIP2

MOLEX_48099-5200~D

1

1

2

2

3

3

4

4

D23

RB751S40T1_SOD523-2~D

21

R555

0_0402_5%~D

@1 2

JMINI1

MOLEX_67910-5200~D

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

GND1

53

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

42 42

44 44

46 46

48 48

50 50

52 52

GND2 54

+

C685

330U_V_6.3VM_R25M~D

1

2

C517

0.1U_0402_16V4Z~D

1

2

R6390_0402_5%~D

1 2

C515

33P_0402_50V8J~D

1

2

C511

0.047U_0402_16V4Z~D

1

2

+

C509

330U_V_6.3VM_R25M~D

1

2

R634

0_0402_5%~D

@1 2

R430

0_0402_5%~D

1 2

C510

0.1U_0402_16V4Z~D

1

2

JCLIP1

MOLEX_48099-5200~D

1

1

2

2

3

3

4

4

C523

0.1U_0402_16V4Z~D

1

2

C514

0.047U_0402_16V4Z~D

1

2

C519

0.047U_0402_16V4Z~D

1

2

C522

0.1U_0402_16V4Z~D

1

2

C513

0.047U_0402_16V4Z~D

1

2

JMINI2

MOLEX_67910-5200~D

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

GND1

53

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

42 42

44 44

46 46

48 48

50 50

52 52

GND2 54

R638

0_0402_5%~D

1 2

C512

33P_0402_50V8J~D

1

2

C516

33P_0402_50V8J~D

1

2

L60 DLW21SN900SQ2_0805~D@

1

1

4

433

22

C520

0.047U_0402_16V4Z~D

1

2

R431

0_0402_5%~D

1 2

C518

0.047U_0402_16V4Z~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

QUIETE#

DOCK_PCI_EN#

QBUFEN#

DOCK_SERR#

DOCK_LOCK#

PCI_C_BE3#

PCI_SERR#

DOCK_C_BE2#

PCI_PLOCK#

PCI_PIRQA#

PCI_AD24

DOCK_TRDY#

DOCK_PCIRST#

PCI_C_BE1# DOCK_C_BE0#

PCI_PERR#

PCI_PAR

PCI_C_BE0#

DOCK_SPME#

PCI_STOP#

DOCK_GNT0#

DOCK_PAR

DOCK_STOP#

DOCK_PIRQA#

PCI_TRDY#

SYS_PME# DOCK_C_BE3#

DOCK_DEVSEL#

PCI_IRDY#

PCI_C_BE2#

DOCK_IRDY#

PCI_FRAME#

DOCK_PCI_IDSEL

DOCK_PERR#

DOCK_FRAME#

PCI_DEVSEL#

DOCK_C_BE1#

PCI_GNT0#

PCI_RST#

PCI_AD22

PCI_AD26

PCI_AD15

PCI_AD16

PCI_AD30

PCI_AD28

PCI_AD25

PCI_AD18

PCI_AD2

PCI_AD5

PCI_AD20

PCI_AD10

PCI_AD7

PCI_AD31

PCI_AD17

PCI_AD24

PCI_AD1

PCI_AD29

PCI_AD14

PCI_AD4

PCI_AD21

PCI_AD23

PCI_AD27

PCI_AD3

PCI_AD8

PCI_AD0

PCI_AD9

PCI_AD19

PCI_AD6

PCI_AD11

PCI_AD12

PCI_AD13

DOCK_AD30

DOCK_AD27

DOCK_AD18

DOCK_AD24

DOCK_AD23

DOCK_AD14

DOCK_AD6

DOCK_AD3

DOCK_AD2

DOCK_AD13

DOCK_AD26

DOCK_AD0

DOCK_AD15

DOCK_AD11

DOCK_AD1

DOCK_AD28

DOCK_AD8

DOCK_AD21

DOCK_AD25

DOCK_AD10

DOCK_AD19

DOCK_AD16

DOCK_AD22

DOCK_AD31

DOCK_AD7

DOCK_AD5

DOCK_AD20

DOCK_AD17

DOCK_AD9

DOCK_AD12

DOCK_AD29

DOCK_AD4

QUIETE#

QUIETE#

+IRVCC

+VCC_QBUFD

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+5V_RUN +VCC_QBUF

DOCK_PCI_EN#<38>

QBUFEN#<39>

DOCK_PAR <38>

PCI_TRDY#<22,31>

PCI_FRAME#<22,31,38>

DOCK_C_BE1# <38>

SYS_PME#<31,39>

DOCK_TRDY# <38>

PCI_DEVSEL#<22,31>

DOCK_GNT0# <38>

DOCK_C_BE0# <38>

PCI_PIRQA#<22>

DOCK_IRDY# <38>

PCI_GNT0#<22,38>

DOCK_DEVSEL# <38>

PCI_C_BE3#<22,31>

DOCK_LOCK# <38>

PCI_C_BE1#<22,31> DOCK_C_BE2# <38>

DOCK_FRAME# <38>

PCI_PERR#<22,31>

PCI_PAR<22,31>

DOCK_PERR# <38>

PCI_RST#<22,31,35>

PCI_STOP#<22,31>

DOCK_SPME# <38>

PCI_C_BE2#<22,31>

DOCK_PIRQA# <38>

DOCK_SERR# <38>

PCI_IRDY#<22,31,38>

PCI_SERR#<22,31>

PCI_PLOCK#<22>

DOCK_PCI_IDSEL <38>

PCI_C_BE0#<22,31>

DOCK_PCIRST# <38>

DOCK_STOP# <38>

DOCK_C_BE3# <38>

PCI_AD[0..31]<22,31> DOCK_AD[0..31] <38>

IRRX <39>

IRTX<39>

D_IRMODE<39>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

DOCKING BUFFER & FIR

37 59Friday, May 12, 2006

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

FIR

Need to modify PAD width from 9mil to 8mil

R432

1K_0402_5%~D

12

U40

TFDU6102-TR3_8P~D

VCC

6

SD_MODE

5

IRED_CATHODE

2

TXD

3

IRED_ANODE 1

RXD 4

MODE 7

GND 8

C525

0.1U_0402_16V4Z~D

1 2

C530

0.1U_0402_16V4Z~D

1 2

D13

RB751S40T1_SOD523-2~D

2 1

U41

PI5C162861BE_BQSOP48~D

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

A9

11

A10

14

A11

15

A12

16

A13

17

A14

18

A15

19

B0 46

B1 45

B2 44

B3 43

B4 42

B5 41

B6 40

B7 39

B8 38

B9 37

B10 34

B11 33

B12 32

B13 31

B14 30

B15 29

GND1 12

GND2 24

NC1

1

NC2

13

OE1

47

OE2

35 VCC2 48

VCC1 36

A16

20

A17

21

A18

22

A19

23

B16 28

B17 27

B18 26

B19 25

R437

100K_0402_5%~D

1 2 C528

4.7U_0603_6.3V6M~D

1

2

R433

47_0805_5%~D

12

C526

4.7U_0603_6.3V6M~D

1

2

C687

0.47U_0402_16V4Z~D

1

2

C686

0.1U_0402_16V4Z~D

1

2

U39

PI5C34X2245BE_BQSOP80~D

NC1

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

GND1

10

NC2

11

A9

12

A10

13

A11

14

A12

15

A13

16

A14

17

A15

18

A16

19

GND2

20

NC3

21

A17

22

A18

23

A19

24

A20

25

A21

26

A22

27

A23

28

A24

29

GND3

30

NC4

31

A25

32

A26

33

A27

34

A28

35

A29

36

A30

37

A31

38

A32

39

GND4

40

VCC4 80

OE1# 79

B1 78

B2 77

B3 76

B4 75

B5 74

B6 73

B7 72

B8 71

VCC3 70

OE2# 69

B9 68

B10 67

B11 66

B12 65

B13 64

B14 63

B15 62

B16 61

VCC2 60

OE3# 59

B17 58

B18 57

B19 56

B20 55

B21 54

B22 53

B23 52

B24 51

VCC1 50

OE4# 49

B25 48

B26 47

B27 46

B28 45

B29 44

B30 43

B31 42

B32 41

R435

10K_0402_5%~D

12

C529

0.1U_0402_16V4Z~D

1

2

D14

RB751S40T1_SOD523-2~D

2 1

R436

10K_0402_5%~D

12

C527

0.1U_0402_16V4Z~D

1

2

U42

SN74AHC1G32DCKR_SC70-5~D

INB

2

INA

1

O4

P5

G

3

C688

0.47U_0402_16V4Z~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DOCK_AD28

DOCK_AD13

DOCK_AD22

DOCK_OWNS_PCI

DOCK_SIO_ALERT#

DOCK_AD31

TV_Y

TV_C

DOCK_C_BE2#

DOCK_AD30

DOCK_AD8

VGA_RED

DOCK_AD4

DOCK_AD23

DOCK_AD11

PCI_IRDY#

DOCK_AD16

DOCK_AD0

DOCK_AD10

Z3306

DOCK_AD11

DOCK_AD0

DOCK_AD19

DOCK_AD5

DOCK_AD3

DOCK_AD7

DOCK_AD31

DOCK_AD9

DOCK_AD4

DOCK_TRDY#

DOCK_AD26

PCI_GNT0#

DOCK_AD6

D_LAD2

DOCK_C_BE0#

TV_CVBS

DOCK_AD14

DOCK_AD18

DOCK_C_BE1#

DOCK_AD20

DOCK_AD12

DOCK_AD6

DOCK_AD30

PCI_FRAME#

DOCK_LAN_ACTLED_YEL#

G_DOC_PWRSRC

DOCK_AD2

DOCK_AD7

TV_Y

DOCK_OWNS_PCI

DOCK_AD29

R_PIDEACT

DOCK_AD8

DOCK_AD14

DOCK_AD10

DOCK_AD2

DOCK_AD27

DOCK_AD25

DOCK_AD17

VGA_RED

DOCK_C_BE3#

DOCK_AD17

DOCK_AD25

TV_CVBS

DOCK_AD24

Z3305

DOCK_LED_100#

DOCK_AD20

DOCK_AD16

DOCK_AD15

TV_C

DOCK_AD21

DOCK_AD18

DOCK_AD28 DOCK_AD1

VGA_BLU

DOCK_AD21

D_LAD0

DOCK_AD19

DOCK_PWR_EN

DOCK_AD13

DOCK_AD5

DOCK_AD27

VGA_GRN

DOCK_AD12

DOCK_STOP#

Z3307

DOCK_AD22

DOCK_PCIRST#

DOCK_AD15

DOCK_PERR#

VGA_GRN

DOCK_AD29

D_LAD1

DOCK_AD1

DOCK_AD23

DOCK_LED_10#

SPDIF_DOCK

DOCK_AD24

VGA_BLU

D_LAD3

DOCK_AD9

DOCK_AD3

DOCK_DET# DOCK_DET#

Z3308

DOCK_DET#

USBP7-

USBP7+

CLK_PCI_DOCK

PCI_REQ0#

DOCK_AD26

VSYNC_R

HSYNC_R

TV_C

TV_CVBS

TV_Y

+2.5V_LOM_DOCK

+PWR_SRC +DOCK_PWR_SRC

+DOCK_PWR_SRC

+5V_ALW

+DOCK_DC_IN

+3.3V_ALW

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_SUS

+2.5V_LOM

DOCK_FRAME#<37>

DAT_KBD <40>

DOCK_TRDY# <37>

DOCK_LAN_TX3+ <30>

CLK_PCI_DOCK<6>

VGA_BLU<12,21>

CLK_KBD <40>

DOCK_AD[0..31] <37>

DOCK_LAN_TX3- <30>

VGA_GRN<12,21>

VGA_RED<12,21>

DOCK_SMB_INT# <40>

DOCK_GNT0# <37>

DVI_TX0-<20>

D_LFRAME# <39>

DOCK_IRDY# <37>

DVI_DETECT <20>

PCI_GNT0#<22,37>

PS_ID_IN<45>

DOCK_DEVSEL# <37>

DVI_TX0+<20>

DVI_SDATA <20>

PCI_FRAME#<22,31,37>

DVI_CLK+<20>

DVI_SCLK <20>

PCI_IRDY#<22,31,37>

DVI_TX1-<20>

D_DLDRQ1# <39> D_LAD0 <39>

DVI_TX1+<20>

DOCK_C_BE3# <37>

DOCK_LOCK#<37>

DAT_DOCK<40>

DOCK_SMB_DAT<40>

DOCK_PCI_IDSEL <37>

TV_CVBS<12>

DOCK_PAR<37>

DOCK_LED_100#<30>

DOCK_C_BE2#<37>

SPDIF_DOCK<27>

DOCK_LAN_TX0-<30>

CLK_DOCK<40>

D_LAD1<39>

DVI_CLK-<20>

D_LAD2<39>

D_SERIRQ <39>

TV_Y<12>

DOCK_LAN_TX1-<30>

DVI_TX2-<20>

R_PIDEACT <44>

DOCK_SIO_ALERT# <39>

DOCK_PCIRST# <37>

DOCK_SMB_CLK<40>

D_LAD3<39>

DOCK_LAN_ACTLED_YEL# <30>

DOCK_C_BE0# <37>

TV_C<12>

DOCK_PERR# <37>

D_CLKRUN# <39>

DOCK_STOP# <37>

DOCK_PCI_EN#<37>

DOCK_SERR#<37>

DVI_TX2+<20>

DOCK_C_BE1# <37>

DOCK_LAN_TX2+ <30>

DOCK_PIRQA#<37>

DOCK_LAN_TX0+<30>

DOCK_SPME#<37>

DOCK_LAN_TX1+<30>

DOCK_LAN_TX2- <30>

DOCK_PWR_EN<39>

DOCK_LED_10#<30>

DAT_DDC2 <12,21>

CLK_DDC2 <12,21>

DOCKED <30,39>

USBP7- <24>

USBP7+ <24>

PCI_REQ0# <22>

HSYNC_R <21>

VSYNC_R <21>

RJ_TIP_L<30>RJ_RING_L <30>

POWER_SW#<18,40,44>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

DOCKING CONN.

38 59Friday, May 12, 2006

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

self power dock

NB

PWR_SRC

no power dock

DVI_TX4-

DVI_TX4+

DVI_TX3+

DVI_TX3-

DVI_TX5+

DVI_TX5-

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

C535

0.01U_0402_16V7K~D

1 2

C690

1000P_0402_50V7K~D

1

2

JDOCK1C

TYCO_2-1612415-3~D

P1

P1

P2

P2

P3

P3

P4

P4

P5 P5

P6 P6

P7 P7

P8 P8

MH1

MH1 MH2 MH2

SHLD5

MH9

SHLD1

MH5

SHLD2

MH6

SHLD3 MH7

SHLD6

MH10

SHLD4 MH8

SHLD7 MH11

SHLD8 MH12

MH16 MH16

MH15

MH15 MH14 MH14

MH13

MH13

R438 100K_0402_5%~D@12

R442 150_0402_1%~D 1 2

C531

0.1U_0603_50V4Z~D

1

2

SIGNAL 218P

RJ11 2P

VOID 52P

POWER 8P

VOID PIN: V14 V16 V44 V46 V56~V68 V123 V124

V129~V135 V191 V192 V197~V203 V219

V221 V249 V251 V260~V272

JDOCK1D

TYCO_2-1612415-3~D

R446

100K_0402_5%~D

12

R443

33_0402_5%~D

@

12

C650

0.1U_0402_16V4Z~D

1 2

U46

74AHC1G08GW_SOT353-5~D

IN1

1

IN2

2

G3

O4

P

5

R449

0_0402_5%~D

@

1 2

C533

0.01U_0402_16V7K~D

1 2

R444

100K_0402_5%~D

1 2

C536

0.01U_0402_16V7K~D

12

C649

0.1U_0402_16V4Z~D

1

2

C534

0.01U_0402_16V7K~D

12

U45

74AHC1G08GW_SOT353-5~D

IN1

1

IN2

2

G

3

O4

P5

C689

1000P_0402_50V7K~D

1

2

Q33

FDS4435_NL_SO8~D

4

7

8

6

5

1

2

3

Q34

DDTC144EUA-7-F_SOT323~D

2

13

U43

NC7SZ04P5X_NL_SC70-5~D

A

2Y4

P5

NC 1

G

3

R447

100K_0402_5%~D

1 2

C538

0.1U_0603_50V4Z~D

1

2

R448

100K_0402_5%~D

1 2

D15

SM05_SOT23~D

@

2

3

1

R445

100K_0402_5%~D

1 2

JDOCK1B

TYCO_2-1612415-3~D

S137

137

S138

138

S139

139

S140

140

S141

141

S142

142

S143

143

S144

144

S145

145

S146

146

S147

147

S148

148

S149

149

S150

150

S151

151

S152

152

S153

153

S154

154

S155

155

S156

156

S157

157

S158

158

S159

159

S160

160

S161

161

S162

162

S163

163

S164

164

S165

165

S166

166

S167

167

S168

168

S169

169

S170

170

S171

171

S172

172

S173

173

S174

174

S175

175

S176

176

S177

177

S178

178

S179

179

S180

180

S181

181

S182

182

S183

183

S184

184

S185

185

S186

186

S187

187

S188

188

S189

189

S190

190

S205 205

S206 206

S207 207

S208 208

S209 209

S210 210

S211 211

S212 212

S213 213

S214 214

S215 215

S216 216

S217 217

S218 218

S220 220

S222 222

S223 223

S224 224

S225 225

S226 226

S227 227

S228 228

S229 229

S230 230

S231 231

S232 232

S233 233

S234 234

S235 235

S236 236

S237 237

S238 238

S239 239

S240 240

S241 241

S242 242

S243 243

S244 244

S245 245

S246 246

S247 247

S248 248

S250 250

S252 252

S253 253

S254 254

S255 255

S256 256

S257 257

S258 258

S259 259

S193

193

S194

194

S195

195

S196

196

M204

204

U44

74AHC1G08GW_SOT353-5~D

IN1

1

IN2

2

G

3

O4

P5

JDOCK1A

TYCO_2-1612415-3~D

S1

1

S2

2

S3

3

S4

4

S5

5

S6

6

S7

7

S8

8

S9

9

S10

10

S11

11

S12

12

S13

13

S15

15

S17

17

S18

18

S19

19

S20

20

S21

21

S22

22

S23

23

S24

24

S25

25

S26

26

S27

27

S28

28

S29

29

S30

30

S31

31

S32

32

S33

33

S34

34

S35

35

S36

36

S37

37

S38

38

S39

39

S40

40

S41

41

S42

42

S43

43

S45

45

S47

47

S48

48

S49

49

S50

50

S51

51

S52

52

S53

53

S54

54

S55

55

S69 69

S70 70

S71 71

S72 72

S73 73

S74 74

S75 75

S76 76

S77 77

S78 78

S79 79

S80 80

S81 81

S82 82

S83 83

S84 84

S85 85

S86 86

S87 87

S88 88

S89 89

S90 90

S91 91

S92 92

S93 93

S94 94

S95 95

S96 96

S97 97

S98 98

S99 99

S100 100

S101 101

S102 102

S103 103

S104 104

S105 105

S106 106

S107 107

S108 108

S109 109

S110 110

S111 111

S112 112

S113 113

S114 114

S115 115

S116 116

S117 117

S118 118

S119 119

S120 120

S121 121

S122 122

S125 125

S126 126

S127 127

S128 128

M136 136

C532

0.1U_0603_50V4Z~D

1

2

G

D

S

Q35

2N7002W-7-F_SOT323~D

2

13

C537

22P_0402_50V8J~D

@

1

2

R440

0_0402_5%~D

12 R441 150_0402_1%~D 1 2

C651

0.1U_0402_16V4Z~D

1 2

R439 150_0402_1%~D 1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RBIAS

IRQ_SERIRQ

CLK_SIO_14M

D_LAD1

D_LAD3

LPC_LDRQ1#

D_LAD0

D_LAD2

D_DLDRQ1#

D_LFRAME#

IRTX

D_SERIRQ

D_CLKRUN#

IRRX

REG_EN

CLKRUN#

LPC_LDRQ0#

SIO_VDDA

USB_HUBP4+

USB_HUBP4-

USBP1+

USBP1-

USB_HUBP1+

USB_HUBP1-

USB_HUBP2+

USB_HUBP2-

ECE5018_XTAL1

ECE5018_XTAL2

LPC_LAD1

LPC_LAD0

LPC_LAD2

LPC_LAD3

PLTRST2#

CLK_PCI_SIO

LPC_LFRAME#

RUNPWROK

D_IRMODE

PCIE_WAKE#

PCIE_WAKE#

SYS_PME#

DOCK_SIO_ALERT#

DOCK_SIO_ALERT#

PBAT_PRES#

BEEP

DOCKED

QBUFEN#

DOCK_PWR_EN

BC_CLK

BC_DAT

BC_INT#

PBAT_ALARM#

PBAT_ALARM#

LOM_TPM_EN#

AUDIO_AVDD_ON

ICH_PME#

ICH_PCIE_WAKE#

FPBACK_EN

CPU_PROCHOT#

BID3

BID2

BID1

BID0

BID1

BID2

BID0

BID3

CLK_PCI_SIO

CLK_SIO_14M

THERMTRIP_SIO

WLAN_RADIO_DIS#

SINFFER_WIRELESS_ON/OFF#

SC_DET#

USB_BACK_EN#

D_CLKRUN#

D_SERIRQ

D_DLDRQ1#

MDC_RST_DIS#

LOM_TPM_EN#

SYS_PME#

PWRUSB_OC#

DBAY_MODPRES#

CB_HWSPND#

SPDIF_SHDN

DBAY_MODPRES#

PWRUSB_OC#

PWRUSB_EN

IMVP6_PROCHOT#

NB_MUTE

IMVP6_PROCHOT#

HP_NB_SENSE

USB_HUBP3+

USB_HUBP3-

HDDC_EN#

HDDC_EN#

EXUSB_EN#

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_RUN

+3.3V_RUN

USBP1+ <24>

USBP1- <24>

USB_HUBP1+ <31,32>

USB_HUBP1- <31,32>

USB_HUBP2+ <36>

USB_HUBP2- <36>

USB_HUBP4+ <34>

USB_HUBP4- <34>

LPC_LAD[0..3] <23,29,40>

PLTRST2# <22,40>

CLK_PCI_SIO <6>

CLKRUN# <24,31,40>

IRQ_SERIRQ <24,29,31,40>

LPC_LFRAME# <23,29,40>

LPC_LDRQ1# <23>

LPC_LDRQ0# <23>

CLK_SIO_14M <6>

D_DLDRQ1# <38>

D_LAD1 <38>

D_LAD2 <38>

D_LAD3 <38>

D_LAD0 <38>

D_LFRAME# <38>

D_CLKRUN# <38>

D_SERIRQ <38>

RUNPWROK <40,43,50>

IRTX<37> IRRX<37>

D_IRMODE<37>

SYS_PME#<31,37>

DOCK_SIO_ALERT#<38> PBAT_PRES#<46>

BEEP<27>

DOCKED<30,38>

QBUFEN#<37>

DOCK_PWR_EN<38>

BC_CLK<40>

BC_INT#<40> BC_DAT<40>

PBAT_ALARM#<46>

AUDIO_AVDD_ON<27>

ICH_PME#<22>

ICH_PCIE_WAKE#<24>

WLAN_RADIO_DIS# <36>

SNIFFER_WIRELESS_ON/OFF#<44>

SC_DET#<32,35>

USB_BACK_EN#<33>

PCIE_WAKE#<29,36>

FPBACK_EN<19>

MDC_RST_DIS#<34>

PWRUSB_OC#<33>

DBAY_MODPRES#<33>

CB_HWSPND#<31>

SPDIF_SHDN<27>

PWRUSB_EN<33>

IMVP6_PROCHOT#<50>

CPU_PROCHOT#<7>

NB_MUTE<28>

ADAPT_OC<51>

LOM_CABLE_DETECT<29>

HP_NB_SENSE<27,28>

LOM_LOW_PWR<29>

USB_HUBP3+ <35>

USB_HUBP3- <35>

ADAPT_TRIP_SEL<51>

HDDC_EN#<26>

EXUSB_EN#<32> CBS_CCD2#<32>

CBUS_GRST#<31>

THERMTRIP_SIO<18>

LOM_TPM_EN#<29>

DOCK_HP_MUTE#<27>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

ECE5018

39 59Friday, May 12, 2006

Compal Electronics, Inc.

Route RBIAS and its

return to pin 128 very

short.

TEST_PIN is a No Connect

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

<---Blue Tooth

<---Mini1 WWAN

A0001 X0311

1X02

1

BID0BID3

X01

X00

REV

BID2 BID1

00

0

00

0

0

0

0

00

0

0

0

Place closely pin 56

Place closely pin 64

<---PC Card Bay

120ohm,600mA,0.25ohm

Follow Travis to add that

Broadcom will be update for

next version.

<---Smart Card

*

L61

BLM18PG181SN1_0603~D

12

C554

4.7U_0603_6.3V6M~D

1

2

C638

4.7U_0603_6.3V6M~D

1

2

R457 100K_0402_5%~D

12

R459

10K_0402_5%~D

12

R473 10K_0402_5%~D

1 2

C541

0.1U_0402_16V4Z~D

1

2

C545

0.1U_0402_16V4Z~D

1

2

LPC

DLPC

USB

GPIO

ECE5018

CLK

TEST

U47

ECE5018 A0_VTQFP128~D

GPIOA[0]

97

GPIOA[1]

98

GPIOA[2]

99

GPIOA[3]

100

GPIOA[4]

101

GPIOA[5]

102

GPIOA[6]

103

GPIOA[7]

104

VDDA33 8

VSS 23

VDDA33 14

VSS 51

VDDA33 20

VSS 36

GPIOH[0]

24

GPIOH[1]

25

GPIOH[4]

26

GPIOH[5]

27

BC_INT#

58

BC_DAT

59

BC_CLK

60

VCC1 34

GPIOE[0]/RXD

1

GPIOE[1]/TXD

2

GPIOE[2]/RTS#

3

GPIOE[3]/DSR#

4

GPIOE[4]/CTS#

5

GPIOE[5]/DTR#

84

GPIOE[6]/RI#

83

GPIOE[7]/DCD#

6

CLKRUN# 37

DCLK_RUN# 38

SER_IRQ 39

DSER_IRQ 40

LRESET# 41

LFRAME# 42

DLFRAME# 43

LDRQ1# 44

DLDRQ1# 45

LDRQ0# 46

LAD3 47

DLAD3 48

LAD2 49

DLAD2 50

LAD1 52

VCC1 57

DLAD1 53

LAD0 54

DLAD0 55

PCICLK 56

GPIOB[0]/INIT#

65

GPIOB[1]/SLCTIN#

66

GPIOC[2]/SCLT

67

GPIOC[3]/PE

68

GPIOC[4]/BUSY

69

GPIOC[5]/ACK#

70

GPIOC[6]/ERROR#

71

GPIOC[7]/ALF#

73

GPIOD[0]/STROBE#

74

GPIOC[1]/PD7

75

GPIOC[0]/PD6

76

GPIOB[7]/PD5

77

GPIOB[6]/PD4

78

GPIOB[5]/PD3

79

GPIOB[4]/PD2

80

GPIOB[3]/PD1

81

GPIOB[2]/PD0

82

CLKI (14.318 MHz) 64

GPIOD[1]

61

GPIOD[2]

62

GPIOD[3]/VBUS_DET

63

CAP_LDO 86

VCC1 85

VSS 96

GPIOD[4]/OCS1_N

28

GPIOD[5]/OCS2_N

29

GPIOD[6]/OCS3_N

30

GPIOD[7]/OCS4_N

31

GPIOH[6]

32

GPIOH[7]

33

GPIOG[0]

88

GPIOG[1]

89

GPIOG[2]

90

GPIOG[3]

91

GPIOG[4]

92

GPIOG[5]

93

GPIOG[6]

94

GPIOG[7]

95

SYSOPT1/GPIOH[2]

106

SYSOPT0/GPIOH[3]

107

VCC1 108

GPIOF[7]

109

GPIOF[6]

110

GPIOF[5]

111

GPIOF[4]

112

IRTX

113

IRRX

114

GPIOF[3]/IRMODE/IRRX3B

115

GPIOF[2]/IRTX2

116

GPIOF[1]/IRRX2

117

GPIOF[0]/IRMODE/IRRX3A

118

VCC1 119

VDD18 120

VSS 17

XTAL2 122

XTAL1/CLKIN 123

VDDA18PLL 124

VDDA33PLL 125

ATEST 126

RBIAS 127

VSS 11

VSS 128

VSS 121

VSS 87

VSS 72

USBDP0 9

USBDN0 10

USBDP1 13

USBDN1 12

USBDP2 15

USBDN2 16

USBDP3 19

USBDN3 18

USBDP4 21

USBDN4 22

PWRGD 7

OUT65 105

TEST_PIN 35

R454 10K_0402_5%~D

1 2

C555

4.7U_0603_6.3V6M~D

1

2

R474 10K_0402_5%~D

1 2

R450 10K_0402_5%~D

1 2

R455 100K_0402_5%~D

12

R559 10K_0402_5%~D

1 2

C553

0.1U_0402_16V4Z~D

1

2

R596 100K_0402_5%~D

12

R458

12K_0402_1%~D

12

R456 100K_0402_5%~D

12

R469

10K_0402_5%~D

@

1 2

C542

0.1U_0402_16V4Z~D

1

2

R602 0_0402_5%~D@12

R476 10K_0402_5%~D

1 2

R653 0_0402_5%~D

12

R560

0_0402_5%~D

12

R463

22_0402_5%~D

@

12

R564 0_0402_5%~D@12

R452 10K_0402_5%~D

1 2

Y1

24MHZ_12PF_1BX24000CE1B~D

12

R644 100K_0402_5%~D

1 2

R472

10K_0402_5%~D

@

1 2

R451 10K_0402_5%~D

1 2

C548

12P_0402_50V8J~D

1 2

C551

22P_0402_50V8J~D

@

1

2

R460 100K_0402_5%~D

12

R475 10K_0402_5%~D@1 2

C543

0.1U_0402_16V4Z~D

1

2

C544

0.1U_0402_16V4Z~D

1

2

C539

0.1U_0402_16V4Z~D

1

2

C549

22P_0402_50V8J~D

@

1

2

C547

4.7U_0603_6.3V6M~D

1

2

R471

10K_0402_5%~D

1 2

C546

0.1U_0402_16V4Z~D

1

2

R461

22_0402_5%~D

@

12

R462

1M_0402_5%~D

12

R470

10K_0402_5%~D

@

1 2

C540

0.1U_0402_16V4Z~D

1

2

C550

12P_0402_50V8J~D

1 2

C552

4.7U_0603_6.3V6M~D

1

2

R453 10K_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LPC_LAD[0..3]

CLK_KBD

DAT_KBD

DAT_SMB

CLK_SMB

CLK_DOCK

DAT_DOCK

CLK_PCI_5004

+RTC_CELL_VCC0

LID_CL#

AUX_EN

SIO_EXT_SMI#

EC_FLASH_SPI_CLK

LPC_LFRAME#

KSO16

KSO5

SIO_SLP_S3#

BAT1_LED#

LPC_LAD1

CLK_PCI_5004

KSI1

KSI2

MEC5004_XOSEL

MEC5004_XTAL1

8051TX

+VR_CAP

RUNPWROK

PLTRST2#

CLK_KBD

KSO3

NUM_LED#

LID_CL_SIO#

CLKRUN#

KSI3

KSI7

KSO0

KSO8

SIO_THRM#

KSO15

SIO_SLP_S5#

SBAT_SMBCLK

IRQ_SERIRQ

ICH_EC_SPI_CLK

SIO_A20GATE

KSI0

RESET_OUT#

FAN1_TACH

SFPI_EN

MEC5004_XTAL1

SNIFFER_PWR_SW#

DAT_TP_SIO

LPC_LAD3

KSI6

PBAT_SMBCLK

SCRL_LED#

FWP#

SIO_EXT_SCI#

PS_ID

KSO1

KSO9

FWP#

RUN_ON

CLK_TP_SIO

KSO7

KSO11

PBAT_SMBDAT

BREATH_LED

BC_INT#

SBAT_SMBDAT

CLK_DOCK

KSO10 ACAV_IN

KSO14 ALWON

HOST_DEBUG_TX

LPC_LAD2

DAT_DOCK

DAT_KBD

KSI4

KSO6

CAP_LED#

DEBUG_ENABLE#

LPC_LAD0

ATF_INT#

LID_CL_SIO#

SUS_ON

HOST_DEBUG_RX

KSO2

BAT2_LED#

KSI5

KSO12

KSO13

SIO_RCIN#

SNIFFER_PWR_SW#

+3.3V_ALW_EC

BC_DAT

BC_CLK

SIO_EXT_WAKE#

KSO4

CLK_SMB

DAT_SMB

DOCK_SMB_DAT

DOCK_SMB_CLK

PS_ID_DISABLE#

DOCK_SMB_INT#

DOCK_SMB_INT#

SNIFFER_SW#

DEBUG_ENABLE#

SIO_PWRBTN#

+EC_AGND

DOCK_SMB_DAT

DOCK_SMB_CLK

SBAT_SMBDAT

SBAT_SMBCLK

PBAT_SMBDAT

PBAT_SMBCLK

MEC5004_XTAL2

ICHO_ECO_SPII_DATA

ICHI_ECI_SPIO_DATA

ECO_FLASHI_DATA

ECI_FLASHO_DATA

SFPI_EN

SPI_CS#

ECI_FLASHO_DATA

SPI_WE#

SPI_WE#

SPI_HOLD#

SPI_HOLD#

EC_FLASH_SPI_CLK

ECO_FLASHI_DATA EC_FLASH_SPI_CLK

ECO_FLASHI_DATA

ECI_FLASHO_DATA

SPI_CS#

VGA_IDENTIFY

VGA_IDENTIFY

ITP_DBRESET#

MEC5004_XTAL2

MAIN_PWR_SW#

MAIN_PWR_SW#

8051RX

INSTANT_ON_SW# INSTANT_ON_SW#

+VR_CAPALWON

SNIFFER_LED_OFF#

SPI_CS#

+3.3V_ALW

+RTC_CELL

+RTC_CELL

+5V_ALW

+RTC_CELL

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+5V_RUN

+3.3V_SUS +3.3V_SUS

+3.3V_SUS

+RTC_CELL

+3.3V_ALW

LPC_LFRAME#<23,29,39>

PLTRST2#<22,39>

LPC_LAD[0..3]<23,29,39>

CLKRUN#<24,31,39>

CLK_PCI_5004<6>

KSI[0..7]<41>

KSO[0..16]<41>

BAT1_LED# <44>

BAT2_LED# <44>

RESET_OUT# <43>

RUNPWROK <39,43,50>

ACAV_IN <18,51>

DAT_TP_SIO<41>

ALWON <47>

BREATH_LED <44>

FAN1_TACH <18>

SIO_A20GATE<23>

CLK_KBD<38> DAT_KBD<38>

DAT_DOCK<38> CLK_DOCK<38>

ICH_EC_SPI_CLK<24>

PBAT_SMBDAT <46,51>

SIO_EXT_SCI# <24>

SIO_EXT_SMI# <24>

BC_INT#<39>

BC_CLK<39> BC_DAT<39>

SIO_THRM#<24>

IRQ_SERIRQ<24,29,31,39>

SBAT_SMBDAT <19>

AUX_EN <42,47>

SUS_ON <42,43,47>

RUN_ON <19,42,43,47,48,49>

SIO_SLP_S5# <24>

SIO_SLP_S3# <24>

SIO_RCIN# <23>

SIO_EXT_WAKE# <24>

LID_CL# <41,44>

SCRL_LED# <44>

CAP_LED# <44>

NUM_LED# <44>

ATF_INT# <18>

BIA_PWM <12,19>

DAT_SMB <18,33>

DOCK_SMB_DAT <38>

PS_ID_DISABLE# <45>

DOCK_SMB_INT# <38>

POWER_SW# <18,38,44>

SNIFFER_SW# <44>

SIO_PWRBTN#<24>

ICHI_ECI_SPIO_DATA<24> ICHO_ECO_SPII_DATA<24>

ITP_DBRESET# <7,24>

PS_ID <45>

HOST_DEBUG_TX <36>

8051RX<36>

SNIFFER_LED_OFF# <44>

CLK_TP_SIO<41>

8051TX<36>

SPI_CS# <24>

HOST_DEBUG_RX <36>

CLK_SMB <18,33>

SBAT_SMBCLK <19>

DOCK_SMB_CLK <38>

PBAT_SMBCLK <46,51>

Title

Size Document Number R ev

Date: Sheet of

LA-3071P

1.0

EMC5004

40 59Friday, May 12, 2006

Compal Electronics, Inc.

32 KHz Clock

Pop for flash corruption issue.

Place closely pin 58

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1=Flash Recovery Enabled

0=Flash Recovery Disabled

Bat2 = Amber LED

Bat1 = Green LED

Flash write protect bottom 4K

of internal bootblock flash

low=write protected

20mA drive pins

150 MIL SO8

200 MIL SO8

Flash ROM

Depop 0ohm when

doing flash

recovery

120ohm,600mA,0.25ohm

120ohm,600mA,0.25ohm

The same MDC connctor

for TAA module

R484 4.7K_0402_5%~D

1 2

C558

0.1U_0402_16V4Z~D

1

2

Y3

32.768K_12.5PF_Q13MC30610003~D

1 4

2 3

C565

22P_0402_50V8J~D

@

1

2

C562

1U_0603_10V4Z~D

1

2

L62

BLM11A121S_0603~D

1 2

C559

0.1U_0402_16V4Z~D

1

2

R486 10K_0402_5%~D

12

R495

10_0402_5%~D

12

R637

0_0402_5%~D

12

R490 10K_0402_5%~D

1 2

R558 10K_0402_5%~D

1 2

R628

10K_0402_5%~D

@

12

R482 4.7K_0402_5%~D

1 2

G

D

S

Q77

2N7002W-7-F_SOT323~D

@

2

13

JP3

TYCO_1-179373-2~D

@

11

33

55

77

99

11 11

2

2

4

4

6

6

8

8

10

10

12

12

13

13 14

14 15

15 16

16 17

17 18

18 19

19 20

20

JDEBUG1

Molex_53261

@

11

22

33

55

44

U49

M25P80-VMW6TP_SO8~D

@

S#

1

Q

2

W#

3

VSS

4

VCC 8

HOLD# 7

C6

D5

C561

10U_0805_6.3V6M~D

1

2

C556

0.1U_0402_16V4Z~D

1

2

R590 0_0402_5%~D@

1 2

C563

1U_0603_10V4Z~D

1

2

C691

4.7U_0603_6.3V6M~D

@

1 2

C557

0.1U_0402_16V4Z~D

1

2

C567

0.1U_0402_16V4Z~D

12

R504

10K_0402_5%~D

12

C569

22P_0402_50V8J~D

1

2

R630

10K_0402_5%~D

@

1 2

R489 10K_0402_5%~D

1 2

R496 8.2K_0402_5%~D

1 2

R479

100K_0402_5%~D

12

R499 0_0402_5%~D

1 2

R586

0_0402_5%~D

1 2

EC_FLASH_PAD1

@SHORT PADS~D

11

2

2

C568

4.7U_0603_6.3V6M~D

1

2

R503

1K_0402_5%~D

12

R477

100K_0402_5%~D

12

R491

1M_0402_1%~D

12

R478

10K_0402_5%~D

1 2

R507

10K_0402_5%~D

12

R508

10K_0402_5%~D

12

R497

10K_0402_5%~D

12

R500

10K_0402_5%~D

@

12

R487 4.7K_0402_5%~D

1 2

R498

10K_0402_5%~D

12

R614 100K_0402_5%~D

1 2

R505

22_0402_5%~D

@

12

R506

0_0402_5%~D

12

R481

10K_0402_5%~D

1 2

L63

BLM11A121S_0603~D

12

R492 8.2K_0402_5%~D

1 2

C566

0.1U_0402_16V4Z~D

1

2

T11PAD~D

C570

22P_0402_50V8J~D

1

2

R488 4.7K_0402_5%~D

1 2

U50

M25P80-VMW6TP_SO8~D

S#

1

Q

2

W#

3

VSS

4

VCC 8

HOLD# 7

C6

D5

R493 8.2K_0402_5%~D

1 2

D22

RB751S40T1_SOD523-2~D

@

21

R494 8.2K_0402_5%~D

1 2

T10PAD~D

C560

0.1U_0402_16V4Z~D

1

2

C

B

E

Q76

PMST3906_SOT323-3~D

@

1

2

3

R511

100K_0402_5%~D

12

R483 8.2K_0402_5%~D

1 2

R485 8.2K_0402_5%~D

1 2

LPC Interface Host/8051

Keyboard and Mouse Interface

BC Bus

PWR SW

U48

MEC5004_VTQFP128~D

GPIO82/FAN_TACH3 43

SGPIO35 1

SGPIO36 (SFPI_EN) 2

SGPIO37 3

SGPIO43 4

GPIO16/FAN_TACH2 42

GPIO15/FAN_TACH1 41

GPIO5/KSO15

14

GPIO4/KSO14

15

OUT11/PWM1 46

OUT10/PWM0 45

OUT9/PWM2 47

OUT5/KBRST

50

OUT2/PWM3 48

PWRGD 49

nRESET_OUT/OUT6 53

ACAV_IN 128

POWER_ SW_IN1# 126

AB1A_DATA 5

AB1A_CLK 6

AB1B_DATA 7

AB1B_CLK 8

KSO13/GPIO18

16

KSO12/OUT8

17

KSO11/GPIOC7

18

KSO10/GPIOC6

19

KSO9/GPIOC5

20

KSO8/GPIOC4

23

KSO7/GPIO3

24

KSO6/GPIO2

25

KSO4/GPIO0

28

KSO3/GPIOC3

29

KSO2/GPIOC2

30

KSO1/GPIOC1

31

KSO0/GPIOC0

32

KSI7/GPIO19

33

KSI6/GPIO17

34

KSI5/GPIO10

35

KSI4/GPIO9

36

KSI3/GPIO8

37

KSI2/GPIO7

38

KSI1/GPIO6

39

KSI0/SGPIO30

40

KCLK

77

KDAT

78

EMCLK

79

EMDAT

80

POWER_ SW_IN0# 127

VCC1 21

KSO5/GPIO1

27

VR_CAP

22

VSS

26

KSO17/GPIOA1

12

KSO16/GPIOA0

13

VSS

51

VCC1 44

GPIO96/TOUT1 52

SGPIO44/MSCLK/SPCLK2 54

SGPIO45/MSDATA/SPDOUT2 55

SER_IRQ

56

LRESET#

57

PCICLK

58

LFRAME#

59

LAD0

60

LAD1

61

LAD2

62

LAD3

63

VSS

74

CLKRUN#

64

VCC1 65

nEC_SCI/SPDIN2 66

SGPIO31/TIN1/SPCLK1 67

SGPIO47/SPDOUT1 68

SGPIO46/SPDIN1 69

SYSOPT0/SGPIO32/LPC_TX 70

SYSOPT1/SGPIO33/LPC_RX 71

TEST_PIN 72

GPIOA3/WINDMON 73

GPIO94/IMCLK

75

GPIO95/IMDAT

76

VCC1 83

GPIO20/PS2CLK/8051RX

81

GPIO21/PS2DAT/8051TX

82

VSS

88

nFWP 84

SGPIO42 89

SGPIO41 90

SGPIO40 91

SGPIO34/A20M

92

VSS_PLL

101

HSTCLK

102

FLCLK

103

VCC_PLL

104

HSTDATAIN

105

FLDATAIN

106

HSTDATAOUT

107

FLDATAOUT

108

FLCS0

109

FLCS1

110

VSS

113

nBAT_LED 114

nPWR_LED 115

VCC1 116

OUT7/nSMI 11

GPIO83/32KHZ_OUT 117

BGPO0 118

ALWON 120

XTAL1

122

XOSEL

123

XTAL2

124

AGND

125

POWER_ SW_IN2# 119

GPIO11/AB2A_DATA 93

GPIO12/AB2A_CLK 94

GPIO13/AB2B_DATA 95

GPIO14/AB2B_CLK 96

GPIO87/AB1C_DATA 111

GPIO86/AB1C_CLK 112

GPIO85/AB1D_DATA 9

GPIO84/AB1D_CLK 10

GPIO93/AB1F_DATA 97

GPIO92/AB1F_CLK 98

GPIO91/AB1E_DATA 99

GPIO90/AB1E_CLK 100

BC_CLK

87

BC_DAT

86

BC_INT

85

VCC0 121

R629

100K_0402_5%~D

@

12

R501

10K_0402_5%~D

@

12

R512

100K_0402_5%~D

@

12

C564

0.047U_0402_16V4Z~D

1

2

R632

100K_0402_5%~D

@

12

R510

47_0402_5%~D

1 2

R509

10K_0402_5%~D

12

R642 0_0402_5%~D

12

R631 22_0402_5%~D@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAT_TP_SIO

CLK_TP_SIOTP_CLK

TP_DATA

SP_V+

KSI6

KSI7

KSO13

KSO8

KSI5

KSO4

KSO11

KSO14

KSO10

KSO6

KSO2

KSO15

KSI3

KSO12

KSI1

KSI4

KSO0

KSO16

KSI0

KSO5

KSO3

KSO7

KSI2

KSO9

KSO1

KSO8

KSO1

KSO12

KSO16

KSO6

KSO13

KSO4

KSO2

KSO0

KSO5

KSI1

KSI0

KSI3

KSO3

KSO14

KSI6

KSO7

KSO15

KSI5

KSI2

KSO11

KSO9

KSI7

KSI4

KSO10

USB_BIO-

USB_BIO+

SP_GND

TP_DATA

TP_CLK

SP_X

SP_Y

SP_GND

SP_X

SP_V+

SP_Y

LID_CL#

SP_Y

SP_V+

SP_X

SP_GND

+5V_RUN

+3.3V_RUN

+5V_RUN

+3.3V_ALW

KSI[0..7]<40>

KSO[0..16]<40>

DAT_TP_SIO <40>

USB_BIO-<35> USB_BIO+<35>

LID_CL#<40,44>

CLK_TP_SIO <40>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

INT KB & FT & LID & TOUCH PAD

41 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Touch PAD

600ohm,100mA

600ohm,100mA

Co-lay with JP4

C590

100P_0402_50V8J~D

1

2

C578

100P_0402_50V8J~D

1

2

R513

4.7K_0402_5%~D

12

C575

100P_0402_50V8J~D

1

2

C594

100P_0402_50V8J~D

1

2

Part Number Description

GC020008R00 BATT CR2025 W/CABLE 170MAH MB 00B 0FD

RTC BATT

Part Number Description

DA300001O1L FPC 00B LF-3072P REV1 T/P FPC WITH BIO

T/P FPC

C577

100P_0402_50V8J~D

1

2

C645100P_0402_50V8J~D

@

1

2

JP6

IPEX_20413-004E~D

1

12

23

34

4

GND

5GND

6

Part Number Description

DC02000980L H-CONN SET 00B M/B-B/T

Bluetooth wire set cable

C584

100P_0402_50V8J~D

1

2

Part Number Description

PK230005C0L SPK PACK 00B 1W 8OHM

SPKER1

Part Number Description

DC02000960L H-CONN SET 00B M/B-MDC

MDC wire set cable

Part Number Description

DC020008Q0L H-CONN SET 00B MB-LCD 12 WXGA

LCD cable

C593

100P_0402_50V8J~D

1

2

C572

10P_0402_50V8J~D

1

2

C592

100P_0402_50V8J~D

1

2

C588

100P_0402_50V8J~D

1

2

JP4

HRS_FH12-10(4)SA-1SH(55)~D

1

12

23

34

4

GND

5GND

6

Part Number Description

PK090003M0L TRACK PAD ALPS KGDDEN010A BIOSENSOR

Touch-PAD MODULE

C582

100P_0402_50V8J~D

1

2

R514

4.7K_0402_5%~D

12

C579

100P_0402_50V8J~D

1

2

C626

10P_0402_50V8J~D

1

2

C589

100P_0402_50V8J~D

1

2

C647100P_0402_50V8J~D

@

1

2

C587

100P_0402_50V8J~D

1

2

Part Number Description

DC000002T0L PCMCIA

FOXCONN

1CA86501-CR-4F

PCMCIA BODY

C573

0.1U_0402_16V4Z~D

1

2

JKYBRD1

HRS_FH28D-25SB-1SH~D

1

3

5

7

11

9

13

15

17

19

21

23

25

27

2

4

6

8

10

12

14

16

18

20

22

24

26

C598

100P_0402_50V8J~D

1

2

PJP13

PAD-OPEN 4x4m

1 2

C597

100P_0402_50V8J~D

1

2

Part Number Description

DA300001N1L FPC 00B LF-3071P REV1 HITACHI

HDD FPC cable

C599

100P_0402_50V8J~D

1

2

C648100P_0402_50V8J~D

@

1

2

C586

100P_0402_50V8J~D

1

2

C591

100P_0402_50V8J~D

1

2

C595

100P_0402_50V8J~D

1

2

C580

100P_0402_50V8J~D

1

2

L65

BLM11A601S_0603~D

1 2

C571

10P_0402_50V8J~D

1

2

L64

BLM11A601S_0603~D

1 2

C646100P_0402_50V8J~D

@

1

2

C644

0.1U_0402_16V4Z~D

1

2

C581

100P_0402_50V8J~D

1

2

C583

100P_0402_50V8J~D

1

2

C627

10P_0402_50V8J~D

1

2

JTPAD

HRS_FH12-30-14-SA-1SH-55~D

1

12

23

34

45

56

67

78

89

910

10 11

11 12

12 13

13 14

14 GND

15 GND

16

C576

100P_0402_50V8J~D

1

2

C585

100P_0402_50V8J~D

1

2

C596

100P_0402_50V8J~D

1

2

Part Number Description

DA300001S1L FPC 00B LF-3073P REV1 LED FPC

LED FPC cable

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RUN_ON_5V#

N21917830

SUS_ON

SUS_ENABLE

SUS_ON_5V#

+5VRUN_DIS

+3.3VRUN_DIS

+1.8VRUN_DIS

+1.5VRUN_DIS

+0.9VDDR_DIS

RUN_ON_5V#

+2.5VRUN_DIS

+1.8VSUS_DIS

SUS_ON_5V#

RUN_ENABLE

+5V_ALW

+PWR_SRC+PWR_SRC

+0.9V_DDR_VTT

+3.3V_RUN

+3.3V_RUN

+5V_RUN

+5V_RUN

+1.8V_RUN

+1.8V_RUN +2.5V_RUN

+1.8V_SUS

+3.3V_SUS

+5V_SUS

+3.3V_SRC

+3.3V_SRC

+1.5V_RUN

+15V_SUS

+15V_SUS

+5V_ALW

+1.8V_SUS

RUN_ON<19,40,43,47,48,49>

ENAB_3VLAN <29>

AUX_EN<40,47>

SUS_ON<40,43,47>

RUN_ENABLE<47>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

POWER CONTROL

42 59Friday, May 12, 2006

Compal Electronics, Inc.

+3.3V_SUS Source

Run Planes Enable

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+5V_RUN Source

DC/DC Interface

+1.8V_RUN Source

+3.3V_RUN Source

Discharge Circuit

R530

1K_0402_5%~D

@

12

R520

100K_0402_5%~D

12

R633

200K_0402_5%~D

1 2

G

D

S

Q69

2N7002W-7-F_SOT323~D

2

13

G

D

S

Q39

2N7002W-7-F_SOT323~D

2

13

R532

100K_0402_5%~D

12

R534

470K_0402_5%~D

12

R518

20K_0402_5%~D

12

R531

1K_0402_5%~D

@

12

R517

100K_0402_5%~D

12

R523

20K_0402_5%~D

12

Q37

STS11NF30L_SO8~D

36

5

7

82

4

1

C602

4700P_0402_25V7K~D

1

2

R533

100K_0402_5%~D

12

R526

1K_0402_5%~D

@

12

R619

22_0805_5%~D

12

R535

200K_0402_5%~D

12

S

GD

Q44

SI3456DV-T1-E3_TSOP6~D

3

6

245

1

G

D

S

Q48

2N7002W-7-F_SOT323~D

@

2

13

C692

470P_0402_50V7K~D

12

R525

20K_0402_5%~D

12

G

D

S

Q46

2N7002W-7-F_SOT323~D

@

2

13

D24

MMBD4148W-7-F_SOT323~D

1

3

2

C605

10U_0805_10V4Z~D

1

2

G

D

S

Q47

2N7002W-7-F_SOT323~D

@

2

13

Q43

SI4800DY-T1-E3_SO8~D

36

5

7

82

4

1

R522

20K_0402_5%~D

12

C601

10U_0805_10V4Z~D

1

2

G

D

S

Q45

2N7002W-7-F_SOT323~D

@

2

13

Q40

SI4800DY-T1-E3_SO8~D

36

5

7

82

4

1

G

D

S

Q50

2N7002W-7-F_SOT323~D

@

2

13

G

D

S

Q51

2N7002W-7-F_SOT323~D

2

13

G

D

S

Q42

2N7002W-7-F_SOT323~D

2

13

R529

1K_0402_5%~D

@

12

G

D

S

Q52

2N7002W-7-F_SOT323~D

2

13

R527

1K_0402_5%~D

@

12

R521

100K_0402_5%~D

12

C603

10U_0805_10V4Z~D

1

2

G

D

S

Q41

2N7002W-7-F_SOT323~D

2

13

C600

10U_0805_10V4Z~D

1

2

R528

1K_0402_5%~D

@

12

G

D

S

Q38

2N7002W-7-F_SOT323~D

2

13

R519

100K_0402_5%~D

12

G

D

S

Q49

2N7002W-7-F_SOT323~D

@

2

13

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RUNPWROK

IMVP_PWRGD

RESET_OUT#

Z4012

ICH_PWRGD

ICH_PWRGD#

5V_3V_RUN_PWRGD

+COINCELL

+RTC_CELL

+COINCELL

+3.3V_RTC_LDO_1

+3.3V_RUN +3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+3.3V_SUS

+5V_SUS

+5V_RUN

+3.3V_SUS

+3.3V_RUN

+1.8V_SUS

+1.8V_RUN

RUN_ON<19,40,42,47,48,49>

SUSPWROK <18,24>

RUNPWROK <39,40,50>

RESET_OUT#<40>

IMVP_PWRGD<24,50>

ICH_PWRGD# <18>

ICH_PWRGD <10,24>

SUSPWROK_1P8V<49>

SUS_ON<40,42,47>

1.5V_RUN_PWRGD<48>

1.05V_RUN_PWRGD<48>

2.5V_RUN_PWRGD<18>

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Power Good

43 59Friday, May 12, 2006

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

COIN RTC Battery

Follow Travis to

modify

At S3 step back-drive: 78mV, change to SI2303

At S3 step back-drive:198mV, change to SI2303

R539

1K_0402_5%~D

12

C624

0.1U_0402_16V4Z~D

1

2

R589

0_0402_5%~D

12

R622

4.7K_0402_5%~D

R588

0_0402_5%~D

12

U52A

74LVC3G14DC_VSSOP8~D

P8

A

1Y7

G

4

R626

100K_0402_5%~D

G

D

S

Q53

2N7002W-7-F_SOT323~D

2

13

U53D

74VHC08MTCX_NL_TSSOP14~D

IN1

13

IN2

12 OUT 11

P14

G

7

D16

BAT54CW_SOT323~D

3

2

1

R536

20K_0402_5%~D

12

R538

100K_0402_5%~D

12

U52B

74LVC3G14DC_VSSOP8~D

P8

A

6Y2

G

4

R556

100K_0402_5%~D

12

C618

1U_0603_10V4Z~D

1

2

R621

200K_0402_5%~D

E

B

C

Q75

MMST3904-7-F_SOT323~D

2

3 1

G

D

S

Q70

SI2303BDS-T1-E3_SOT23-3~D

2

1 3

E

B

C

Q73

MMST3904-7-F_SOT323~D

2

3 1

G

D

S

Q74

SI2303BDS-T1-E3_SOT23-3~D

2

1 3

R623

200K_0402_5%~D

U53A

74VHC08MTCX_NL_TSSOP14~D

IN1

1

IN2

2OUT 3

P14

G

7

R557

10K_0402_5%~D

12

C616

0.1U_0402_16V4Z~D

1 2

G

D

S

Q63

2N7002W-7-F_SOT323~D

2

13

U53C

74VHC08MTCX_NL_TSSOP14~D

IN1

10

IN2

9OUT 8

P14

G

7

R624

4.7K_0402_5%~D

E

B

C

Q71

MMST3904-7-F_SOT323~D

2

3 1

R587

0_0402_5%~D

12

U53B

74VHC08MTCX_NL_TSSOP14~D

IN1

4

IN2

5OUT 6

P14

G

7

U52C

74LVC3G14DC_VSSOP8~D

P8

A

3Y5

G

4

C617

0.01U_0402_16V7K~D

1

2

R537

0_0402_5%~D

1 2

C613

0.1U_0402_16V4Z~D

1 2

R627

4.7K_0402_5%~D

JCOIN1

MOLEX_53780-0270~D

1

1

2

2

GND

3

GND

4

Q72

DDTA114EUA-7-F_SOT323~D

2

1 3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BREATH_LED_B

BAT1_LED#

SNIFFER_Y

SNIFFER_G

SNIFFER_GREEN#

SNIFFER_YELLOW#

IDE_ACT#

BAT2_LED#

BT_ACT

WLAN_ACT

R_CAP_LED#

R_NUM_LED#

R_SCRL_LED#

POWER_SW#

BATT_AMBER_LED

BATT_GREEN_LED

POWER_SW_LED

POWER_SW_LED

BT_ACT

WLAN_ACT

R_CAP_LED#

R_NUM_LED#

R_SCRL_LED#

BT_LED_DIS#

SNIFFER_SW#

LID_CL#

BT_ACT

R_CAP_LED#

R_NUM_LED#

R_SCRL_LED#

WLAN_ACT

+3.3V_ALW

+3.3V_RUN

+3.3V_RUN

+3.3V_ALW

+3.3V_ALW

+3.3V_SUS

+3.3V_SUS

+5V_RUN

+3.3V_SUS

+3.3V_SUS

+3.3V_RUN

+3.3V_ALW

+3.3V_ALW

+3.3V_RUN

BREATH_LED<40>

BAT1_LED#<40>

SCRL_LED#<40>

CAP_LED#<40>

NUM_LED#<40>

LED_WLAN_OUT#<36>

SNIFFER_GREEN#<18>

SNIFFER_YELLOW#<18>

SNIFFER_SW#<40>

BAT2_LED#<40>

R_PIDEACT<38>

IDE_ACT#<26>

SNIFFER_WIRELESS_ON/OFF#<39>

POWER_SW#<18,38,40>

BT_ACTIVE<34,36>

LID_CL#<40,41>

SNIFFER_LED_OFF#<40>

Title

Size Document Number R ev

Date: Sheet of

LA-3071P

1.0

PAD and Standoff

44 59Friday, May 12, 2006

Compal Electronics, Inc.

Fiducial Mark

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

MDC Cable latch

Co-lay with JLED1

R544

10K_0402_5%~D

1 2

H16

@H_C472D376

1

H17

@H_C472D431X376

1

FD13

FIDUCIAL MARK~D

1

R543

51_0402_5%~D

1 2

E

B

C

Q57

MMST3904-7-F_SOT323~D

2

3 1

R615 51_0402_5%~D

1 2

Part Number Description

EL00B00070L HAU30_MYLAR_DDR2

MYLAR4

JP10

IPEX_20403-010E~D

1

1

2

2

3

3

4

4

GND

11

GND

12

5

5

6

6

7

7

8

8

9

9

10

10

H5

@H_C315D126

1

FD20

FIDUCIAL MARK~D

1

FD17

FIDUCIAL MARK~D

1

Part Number Description

FH00B00060L HAU30_MIC_RUBBER

RUBBER1

CLP4

EMI_CLIP

GND

1

Q58

DDTA114EUA-7-F_SOT323~D

2

1 3

Q67

DDTA114EUA-7-F_SOT323~D

2

1 3

Q59

DDTA114EUA-7-F_SOT323~D

2

1 3

FD15

FIDUCIAL MARK~D

1

FD26

FIDUCIAL MARK~D

1

FD11

FIDUCIAL MARK~D

1

CLP2

EMI_CLIP

GND

1

JPSW

MOLEX_53780-0370~D

1

1

2

2

3

3

GND 4

GND 5

R548 510_0402_5%~D

12

R550

330_0402_5%~D

1 2

CLP1

EMI_CLIP

GND 1

H3

@H_C315D126

1

H7

@H_C315D126

1

R540

47_0402_5%~D

1 2

H18

H_C315D126@

1

FD8

FIDUCIAL MARK~D

1

Q62

DDTA114EUA-7-F_SOT323~D

2

1 3

LED3

LTST-C190KGKT_GRN_0603~D

1 2

H10

@H_C315D126

1

Y

G

D18

12-22AUYSYGC/530-A2/TR8_G/Y~D

3

21

R545 510_0402_5%~D

12

Part Number Description

EL00B000A0L HAU30_MYLAR_FAN

MYLAR7

FD12

FIDUCIAL MARK~D

1

H6

@H_C315D126

1

FD19

FIDUCIAL MARK~D

1

FD16

FIDUCIAL MARK~D

1

FD31

FIDUCIAL MARK~D

1

FD1

FIDUCIAL MARK~D

1

H1

@H_C315D126

1

FD23

FIDUCIAL MARK~D

1

H15

H_C236D91

1

R552

220_0402_5%~D

1 2

Part Number Description

EL00B00040L HAU30_DOCKING_HOLE_MYLAR

MYLAR1

Part Number Description

EL00B00050L HAU30_DOCKING_LOCK_L_MYLAR

MYLAR2

FD30

FIDUCIAL MARK~D

1

FD5

FIDUCIAL MARK~D

1

G

O

LED5

LTST-C155KGKFKT_GRN/ORG~D

2 1

4 3

R616

10K_0402_5%~D

1 2

H11

H_C236D91

1

H4

@H_C315D126

1

FD21

FIDUCIAL MARK~D

1

E

B

C

Q68

MMST3904-7-F_SOT323~D

2

3 1

Part Number Description

EL00B000O00 HAU30_RUBBER_MDC

RUBBER2

H2

@H_C315D126

1

Q55

DDTA114EUA-7-F_SOT323~D

2

1 3

G

D

S

Q78

BSS138W-7-F_SOT323~D

2

13

JLED1

HRS_FH12-10S-0.5SH(55)~D

1

1

2

2

3

3

4

4

GND

11

GND

12

5

5

6

6

7

7

8

8

9

9

10

10

FD2

FIDUCIAL MARK~D

1

H8

@H_C315D126

1

FD3

FIDUCIAL MARK~D

1

Q61

DDTA114EUA-7-F_SOT323~D

2

1 3

Part Number Description

EL00B000X00 HAU30_MYLAR_HDD

MYLAR6

FD6

FIDUCIAL MARK~D

1

H14

H_C236D91

1

R549

10K_0402_5%~D

12

FD22

FIDUCIAL MARK~D

1

Q54

DDTA114EUA-7-F_SOT323~D

2

1 3

R547 510_0402_5%~D

12

FD4

FIDUCIAL MARK~D

1

R546 510_0402_5%~D

12

H12

@H_C236D126

1

FD27

FIDUCIAL MARK~D

1

Part Number Description

EL00B00060L HAU30_DOCKING_LOCK_R_MYLAR

MYLAR3

FD28

FIDUCIAL MARK~D

1

R636

10K_0402_5%~D

@

1 2

Part Number Description

EL00B000N00 HAU30_MYLAR_WLAN_WWAN

MYLAR5

R551 56_0402_5%~D

1 2

R553

220_0402_5%~D

1 2

C

B

E

Q56

PMST3906_SOT323-3~D

1

2

3

R541

10K_0402_5%~D

1 2

FD7

FIDUCIAL MARK~D

1

FD14

FIDUCIAL MARK~D

1

FD10

FIDUCIAL MARK~D

1

Q60

DDTA114EUA-7-F_SOT323~D

2

1 3

FD24

FIDUCIAL MARK~D

1

Part Number Description

MAAA00153G0 SCREW M M 2.0D 3.0L K 4.6D ZK NL + CR3+

SCREW1

FD9

FIDUCIAL MARK~D

1

JPLID

MOLEX_53780-0370~D

1

1

2

2

3

3

GND 4

GND 5

CLP3

EMI_CLIP

GND 1

FD29

FIDUCIAL MARK~D

1

FD25

FIDUCIAL MARK~D

1

FD32

FIDUCIAL MARK~D

1

R542 1K_0402_5%~D

1 2

JSNIFF

1BS008-13130-002-7F_4P~D

1

1

2

2

3

3

4

4

GND

5

GND

6

H9

@H_C315D126

1

LED1

LTST-C190KGKT_GRN_0603~D

12

H13

H_C236D91

1

FD18

FIDUCIAL MARK~D

1

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

AD3419_BST1

ADP3207_PWM1

ADP3207_#DCM

ADP3207_RAMPADJ

ADP3207_VRTT

AD3419_DRVH1

+CPU_PWR_SRC

AD3419_DRVL1

ADP3207_TTSENSE

ADP3207_CSSUM

ADP3207_CSREF

ADP3207_CSREF

AD3419_SW1

+VCC_CORE

GNDA_CORE

+PWR_SRC

+PWR_SRC

GNDA_COREGNDA_CORE

GNDA_CORE GNDA_CORE

GNDA_CORE

GNDA_CORE

GNDA_CORE

GNDA_COREGNDA_CORE

GNDA_CORE

GNDA_CORE

GNDA_CORE

+3.3V_RUN

+5V_RUN

+5V_RUN

GNDA_CORE

+VCC_CORE

GNDA_CORE

DPRSLPVR<24>

RUNPWROK<39,40,43>

IMVP6_PROCHOT# <39>

VSSSense <8>

VCCSense <8>

H_DPRSTP#<7,23> H_PSI#<8>

VID2<8>

VID0<8>

VID3<8> VID4<8> VID5<8> VID6<8>

VID1<8>

CLK_ENABLE#<6>

IMVP_PWRGD<24,43>

RUNPWROK<39,40,43>

Title

Size Document Number R ev

Date: Sheet of

1.0

+VCORE

50 59Friday, May 12, 2006

Compal Electronics, Inc.

LA-3071P

Rdson_typ

4.8mohms

PWM2, PWM3 pull high

DELL CONFIDENTIAL/PROPRIETARY

Thermistor PH1 should be placed

close to the hot spot of the VR

NOTE: ( Connection VCORE output Cap GND)

De-populate PR113 and PR115 when CPU is present

NOTE:PR111 is reversed for loop

gain measurement purpose

IMVP-6 solution for Yonah ULV: 1-phase/9A

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

@ 0.45U_MPC1040LR45_27A_20%~D

Single Core

(YONAH ULV)

Dual Core

(YONAH ULV)

1. Choke: PL14 is 0.88u H

2. MOS: PQ27

3 .PR104 is 309K.(OCP:14A)

4. PR114 is 2.37K.(Load Line: -5.1m)

5. PR101 is 10K.

6. PR88 is 820P ; 8. STUFF PC80

7. PR90 is 390P.

1. Choke: PL14 is 0.45u H

2. MOS: PQ27.

3. PR104 is 215K.(OCP:20A)

4. PR114 is 5.76K.(Load Line: -2.1m)

5. PR101 is 20K.

6. PR88 is 470P ; 8. NO-STUFF PC80

7. PR90 is 470P.

Dual Core

(MEROM ULV)

NOTE

@ 215K_0402_1%

@5.76K_0402_1%~D

@ 470P_0402_50V7K

@20K_0603_1%~D

@ 470P_0402_50V7K

1. Choke: PL14 is 0.45u H

2. MOS: PQ16 and PQ27

3. PR104 is 215K.(OCP:20A)

4. PR114 is 5.76K.(Load Line: -2.1m)

5. PR101 is 20K. ;8. NO-STUFF PC80

6. PR88 is 470P

7. PR90 is 470P.

PR92 0_0402_5%~D

1 2

PR82

10_0603_5%

12

PC96

1000P_0402_50V7K~D

12

PR102 0_0402_5%~D

12

PR85

0.001_2512_1%~D

4

2

1

3

PC94

1000P_0402_50V7K~D

12

PR113

100_0402_5%~D@

1 2

PR108

12K_0402_1%

1 2

PC95

1000P_0402_50V7K~D

12

PD14

RB751V-40_SOD323~D

12

PR104

309K_0402_1%

1 2

PC79

10U_1206_25V6M~D

12

PR79

7.32K_0603_1%

@

12

PC77

1000P_0402_50V7K~D

12

PH1

100K_0603_5%_TH11-4H104FT

@

12

PC75

4.7U_0805_10V6K

12

PU5

ADP3207JCP-RL_LFCSP-40

STSET

9

SS

8

EN

1

PWRGD

2

PGDELAY

3

FBRTN

5

CLKEN

4

FB

6

COMP

7

ILIMIT

11

RRPM

13

GND

20

RT

14

RAMPADJ

15

LLSET

16

CSREF

17

CSSUM

18

CSCOMP

19

PWM3 24

VRPM

12

SW1 23

PWM2 25

PWM1 26

OD 27

DCM 28

VRTT 29

TTSENSE 30

PSI 32

DPRSTP 33

VID6 34

VID5 35

VID4 36

VID3 37

VID2 38

VID0 40

VID1 39

DPRSLP

10

SW2 22

SW3 21

VCC 31

PC81

0.01U_0402_25V7K~D

@

12

PR141

499_0402_1%

1 2

PR940_0402_5%~D

12

PC89

0.015U_0402_16V7K

12

G

D

S

PQ17

2N7002_SOT23~D@

2

13

PR88

0_0402_5%~D

@

12

PR950_0402_5%~D

12

PC90

390P_0402_50V7K

PR81

0_0402_5%~D

@

12

PR87

0_0402_5%~D

1 2

PC78

0.1U_0805_25V7K~D

12

PR150

0_0402_5%~D

1 2

PR115

100_0402_5%~D@

1 2

PQ16

IRF7832_SO8~D

3 6

5

7

8

2

4

19

PQ27

FDS7088SN3_SO8~D

@

3 6

5

7

8

2

4

19

+

PC137

15U_D2_25M_R90~D

1

2

PC82

1U_0805_25V4Z~D

12

PL14

0.88UH_MPC1040LR88_17A_20%~D

1 2

PR110 280K_0402_1%

1 2

PR107

0_0402_5%~D

12

PR80

0_0603_5%~D

1 2

PR930_0402_5%~D

12

PR134

0_0603_5%~D

12

PC86

100P_0402_50V8K

12

PQ15

IRF7821_SO8~D

3 6

5

7

8

2

4

1

PR90

1.91K_0402_1%~D

12

PR100

1K_0402_1%

12

PR101

10K_0603_0.1%~D

1 2

PC87

27P_0402_50V8K

1 2

PC85

4700P_0402_25V7K

1 2

PR114

2.37K_0402_1%~D

12

PR970_0402_5%~D

@

12

PR960_0402_5%~D

12

PC80

10U_1206_25V6M~D

12

PR103

0_0402_5%~D

12

PL13

FBMA-L11-321611-800LMA40T

12

PU4

ADP3419JRM_MSOP-10

IN

1

SD#

2

DRVLSD#

3

CROWBAR

4

VCC

5DRVL 6

GND 7

SW 8

DRVH 9

BST 10

PR105

160K_0402_1%~D

1 2

PC88

820P_0402_25V8K

1 2

PR99

0_0402_5%~D

12

PR106

392K_0402_1%

1 2

PR112 0_0402_5%~D

12

PC76

0.33U_0603_10V7K

12

PR91 0_0402_5%~D

1 2

PC84

1000P_0402_50V7K~D

1 2

PR98 0_0402_5%~D

1 2

PR89

1.91K_0402_1%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 1

52 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

10.27 H/W 10/14 INTEL H_DPRSTP# & H_DPSLP# not need pull

down resistor for Intel request Remove R85,R86

2

3 41 H/W 10/14 Steve Touch PAD module issue Change JTPAD1.14 from +3.3V_RUN to GND 0.2

4 42 H/W Power sequence issue that +1.8V_RUN too

late on +VCC_CORE 0.2

Remove R524,C604

5 43 H/W 10/14 Steve Add +5V,+3V,+1.8V_RUN power sequence

schematic to control sequence Add R621,R622,R623,R624,R626,R627,Q70,Q71,Q72,Q73,Q74,Q75 0.2

15 H/W 10/14

SO-DIMMA SM Bus address define need change

from A4 to A2 for 945GMS DDR support one

channel issue.

Change R135 from pull down to pull up +3.3V_RUN

Change R136 from pull up to pull down and change from 100K to 10K 0.2

Steve

10/14 Steve

6 17 H/W 10/15 Steve 945GMS support CKE0,CS0#,ODT0 to control

on board RAM,so remove CKE1,CS1#,ODT1 Remove RN76,RN80 and add R625,previously T13,T14,T15 for

DDR_CKE1,DDR_CS1#,M_ODT1 0.2

7 39 H/W 10/15 Steve Change BID from X00 to X01 Un-pop R473,pop R469

8 44 H/W 10/15 Steve

0.2

0.2Remove CAP,NUM,SCRL,BT,WLAN LED from M/B

to FFC and CAP,NUM,SCRL direct driving LED

from MEC5004.

Remove LED6,LED7,LED8,LED9,LED10,Q64,Q65,Q66,add JLED1

9 19 H/W 10/17 Steve 945GMS control panel backlite (BIA_PWM),

the voltage level is 3.3V, so don't need

add component for voltage level shift.

Remove U54 0.2

40 H/W 10/17 Steve Resolve EC code damage issue Reserved R628,R629,R630,R631,R632,C691,Q76,Q77,D22(depop) 0.210

11 31 H/W 10/27 Steve Follow M07_R5C843 refer schematic to

modify. Change C424,C425 from 22P to 12P 0.2

12 42 H/W 10/27 Steve Resolve IMVP_PWRGD glitch during power

on/S3 resume Add R633,C692 0.2

13 9 H/W 10/27 Steve For Dual Core CPU action Reserved C693,C694,C695,C696,C697,C698,C699,

C700,C701,C702,C703,C704,C705,C706(depop) 0.2

14 H/W 10/27 Steve Support WoW function for prevent backdrive. Add D23,no pop R634 0.2

15

36

34 H/W 10/27 Steve Keep the BT LED off when the SNIFFER is

turned on. Add R635,R636,Q78 0.2

16 40 H/W 10/31 Steve Resolve EC flash corruption issue. Add R637 to pull down. 0.2

17 9 H/W 11/1 Steve Support one core CPU that follow Intel

reqeust just pop 8pcs of 22uF MLCC Cap. Pop C21,C23,C26,C28,C29,C31,C34,C36 0.2

18 42 H/W 11/3 Dell Correct C692 value Change to 470PF

19 34 H/W 11/3 Dell SNIFFER_LED_OFF# should be pull up to

+3.3V_SUS Change to pull up power source from +5V_SUS to +3.3V_SUS

0.2

0.2

20 36 H/W 11/7 CoE Nimi-Card Reset change to PLTRST# Follow CoE M07-Nimicard-a07 0.2

21 36 H/W 11/7 CoE Nimi-Card WLAN COEX2_WLAN_ACTIVE AND

COEX1_BT_ACTIVE ADD 0 ohms: R638 and

R639

Follow CoE M07-Nimicard-a07 0.2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 2

53 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

0.222 36 H/W 11/7 CoE C685 STUFFED Follow CoE M07-Nimicard-a07

23 32 H/W 11/7 CoE SIM Module C505, C506, C507, C508 Change to

33P_0402, and C508 stuffed Follow CoE M07-Nimicard-a07

24 44 H/W 11/7 Steve Sniffer LED Indicator Error Swap D18 pin2,3 of LED

25 24 H/W 11/8 CoE R370 Move to ICH7 side Follow CoE M07-ICH a07

26 31 H/W 11/8 CoE C428, C429, C430 add the note to close connector FollowM07_R5C843_REF_SCHEMATICS_A00

27 31 H/W 11/8 CoE C424, C425 add a note to change the value after

measure the starting value FollowM07_R5C843_REF_SCHEMATICS_A00

28 31 H/W 11/8 CoE C431 change from 0.01u to 0.1u FollowM07_R5C843_REF_SCHEMATICS_A00

29 31 H/W 11/8 CoE +SD_VCC change to +3.3V_RUN_CARD FollowM07_R5C843_REF_SCHEMATICS_A00

30 32 H/W 11/8 CoE VCC_PCI/ VCC_MD3V add C707_0.01u FollowM07_R5C843_REF_SCHEMATICS_A00

31 32 H/W 11/8 CoE R389_100 remove FollowM07_R5C843_REF_SCHEMATICS_A00

32 32 H/W 11/8 CoE C448/ C449 /C684 change to 0.01u_0402 FollowM07_R5C843_REF_SCHEMATICS_A00

33 32 H/W 11/8 CoE VCC_CBS add C708_10u and C709_0.01u FollowM07_R5C843_REF_SCHEMATICS_A00

34 32 H/W 11/8 CoE +VCC_CBS rename to VCC_CBS, +CBS_VPP rename to CBS_VPP FollowM07_R5C843_REF_SCHEMATICS_A00

35 44 H/W 11/8 CoE Bluetooth LED disable function when Sniffer Active

update, follow travis: R636 pull-up to +3.3_ALW,

Q56 --> 3906, R635 --> remove. But depop R636

Follow Travis

36 29 H/W 11/9 Brocadcom Change RDAC for Broadcom request. Change R338 from 1.15K to 1.18K.

37 34 H/W 12/8 Steve_Wang Resolve Bluetooth LED always light Pop R408

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.3

38 9 H/W 12/8 Steve_Wang Separate BOM type for different CPU. Pop 1@ for Signal core 1.06G

Pop 2@ for Singal core 1.2G

Pop 3@ for Dual core 1.06G

0.3

39 29 H/W 12/13 Steve_Wang Prevent Q23 damage issue for transfor +3.3V_LAN to

+2.5V_LOM Add R640,C710

40 20 H/W 12/13 Steve_Wang Resolve DVI test fail issue 1. Change C245,C236 from 0.1U to 10U

2. Change R169,R170,R171,R172 from 300ohm to 110ohm

3. Change R175 from 300ohm to 220ohm

4. Pop C238,C247

41 26 H/W 12/13 Steve_Wang Resolve HDD_EN# have spike when power on Change R279 from 100K to 4.7K

42 39 H/W 12/13 Steve_Wang Change BID from X01 to X02 Unpop R469,R474; pop R470,R473

0.3

0.3

0.3

0.3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 3

54 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

0.339 H/W 12/14 CoE C638 STUFFED Follow CoE M07_EC_Latitude_A0743

44 26 H/W 12/14 CoE Change HDD_EN# signal from ICH to SIO 1.Change HDD_EN# from ICH to ECE5018 pin106.

2.Add R644 to pull-up +3.3V_ALW

3.Delete R279 to pull-down

4.Rename signal at ICH to RSVD_HDDC_EN# and add Test Point

45 24,40 H/W 12/16 CoE SPI_CS# have spike over 4.5V when power on

0.3

Add R641,R642 damping to prevent. 0.3

46 31 H/W 12/19 MikeCC_Huang Measure SD EA find Data overshot,undershot over 3.3V Add R645,R646,R647,R648 damping to meliorate. 0.3

47 21 H/W 12/20 DELL +CRT_VCC current limit issue Add 1206 Res of R649. 0.3

48 28 H/W 12/21 DELL Fine tuning AUD_LINE_OUT signal Change C368 from 0.0047u(X5R) to 4700P(X7R) 0.3

49 24 H/W 12/21 DELL Follow DELL request Change R265 contact from R641 pin1 to pin2 0.3

50 27,28 H/W 12/21 DELL Follow DELL request Change Auido by-pass cap to X5R 0.3

51 18 H/W 12/21 DELL Follow DELL request Add VSET,LDO_SET note 0.3

52 21 H/W 12/21 COE Follow COE M07_CRT_LVDS_DVI rev A07schematic Add R650,R651 0.3

53 42 H/W 12/21 COE Follow COE M07_System power sequence_A07 schematic Add D24 for fast turn Off FET 0.3

54 43 H/W 12/21 COE Follow COE M07_System power sequence_A07 schematic Change Q63 from MMBT3904 to 2N7002 that it

has good margin to turn 0.3

55 28 H/W 12/22 COE Follow COE M07_AUDIO_A05 schematic Add EAPD signal & Q79 for power saving control 0.3

56 29 H/W 12/23 Crystal EA Follow vendor suggest to modify resistor to match

crystal negative resistor EA Change R334 from 200 to 330ohm 0.3

57 31 H/W 12/23 Crystal EA Follow vendor suggest to modify cap to match

crystal EA Change C424,C425 from 12P to 18P.

58 21 H/W 12/23 RGA EA For 1pix 1600x1200 rising/falling time over spec issue Change L18,L19,L20 from 60ohm to 22ohm

0.3

0.3

59 39 H/W 12/23 Crystal EA Follow vendor suggest to modify crystal Change Y1 from 24MHz_20pF to 24MHz_12pF 0.3

60 30 H/W 12/26 DELL Follow DELL resolution of test Media Slice,APR,DAPR

return loss issue

1.Change R342,R343,R344,R345,R346,R347,R348,R349 from

49.9 to 48.7ohm

2.Change L39,L40,L41,L42,L43,L44,L45,L46 from 24NH to

39NH

0.3

61 30 H/W 2/18 EMI EMI test ISN of LAN on 10/100 item fail.The solution

are pop C421,C422 and change C419~C422 character from

Y5Vto X5R

1.Pop C421,C422

2.Change C419~C422 character from Y5V to X5R 0.4

62 31 H/W 2/18 STEVE_WANG System can't boot issue. Unpop R609 0.4

63 28 H/W 2/27 DELL Follow DELL request to modify amplifier gain from

10db to 15.6db for fix small sound on speaker issue Unpop R311,R312; pop R310,R313 0.4

64 28 H/W 2/27 DELL Follow DELL request to modify cap value from

0.047u to 4700p for best pop and click performance Change C367,C369,C371 from 0.047U to 4700P 0.4

65 9 H/W 3/2 DELL Follow Intel document to modify 330u 7mohm to 6mohm Change C41,C42,C43,C44,C705,C706 from 330U 7mohm to 6mohm 0.4

66 12 H/W 3/2 DELL Follow DELL request to add shunt caps between LVDS signal. Add 10P_0402 of C711,C712,C713,C714 0.4

67 32 H/W 3/6 DELL DELL support Express USB Card can't work on R5C843

issue.

Add schematic of

U62,U63,U64,U65,C715,C716,C722,C723,R652,R654,R655 0.4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 4

55 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

0.439 H/W 3/7 DELL DELL support Express USB Card can't work on R5C843

issue.

68

69 18 H/W 3/9 Thermal Modify OTP thermal shut down to 91 degree.

Reserve 0ohm of R653 for control Express card detect.

Change R157 from 41.2K to 68K 0.4

70 31 H/W 3/10 Mikecc_Huang SD bus signal overshoot/undershoot over spec. Add C717,C718,C719C720 0.4

71 27 H/W 3/10 SIGMATEL Follow sigmatel request to add cap for SENSE_A signal Add 1000P cap 0.4

72 28 H/W 3/10 SIGMATEL Follow sigmatel request to add NB_MUTE signal for

control MAX4411 shutdown. Add Q80 of NB_SENSE signal to control MAX4411 shutdown 0.4

73 28 H/W 3/10 SIGMATEL Follow sigmatel request to add ESD diode for avoid

High pol Reserve D25 0.4

74 28 H/W 3/10 SIGMATEL Follow sigmatel request for MIC BIAS. Unpop R299,R300 0.4

75 35 H/W 3/10 DELL Modiy USB_BIO-/USB_BIO+ ESD IC to choke Add R657,R658; reserve L67,C724,C725; delete U55 0.4

76 35 H/W 3/10 Mikecc_Huang Advoid LID_CL# have some error on ALPS touchpad module. Add PJP13 0.4

77 32 H/W 4/10 Mikecc_Huang Result remove PCMCIA Card can't reduce default issue Add R659

78 41 H/W 4/10 DELL Improve LVDS for 3 dB (CDMA, GSM) at 1900 band Pop C575~C599

Change C712,C713,C714 from 10P to 3.3P.

79 39 H/W 4/10 Steve_Wang Change Board ID from X02 to A00 Pop R473,R474,R471;unpop R469,R470,R475

80 6 H/W 4/17 Steve_Wang Result WWAN noise issue Change R35,R36,R32,R34,R605 from 15ohm to 39ohm

Change R37,R38,R39,R48 from 33ohm to 56ohm

81 29 H/W 4/21 DELL Add cap for damp power-up surge current Add C726 of 4700P Cap.

82 6 H/W 4/28 DELL Result WWAN noise issue Unpop R561

83 6 ME 4/28 CT_Huang Avoid FPC easy to remove from connector Add JP6,JP10 that co-lay with JP4,JLED1

84 9 Power 4/28 Kenneth_Chang Result DC CPU noise Remove C24,C32,C695,C696,C701,C702

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

85 44 H/W 5/9 Steve_Wang Result HDD,Power,Battery Charger,Bluetooth,WLAN LED

lightness irregularity issue Change R615,R543 to 51ohm,R540 to 47ohm;R542,R547

to 330ohm,R551 to 56ohm 1.0

86 44 H/W 5/12 Steve_Wang Result NUM,CAP,SCRL,Bluetooth,WLAN LED

brightness irregularity issue Change R545,R546,R547,R548 to 510ohm,R542 to 1Kohm 1.0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 2

56 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

1 PWR 10/14 0.2

For support Adapter 45W

51 Kenny Add PR154 154K_0402_1% (SD03415438L) connect

net (ADAPT_TRIP_SEL) to PU9_2

Add net name "ADAPT_TRIP_SEL"

2 51 PWR 10/14 Kenny Add PC135 0.01U_0603_25V (SD03415438L) connect FBSA to GNDFBSA of the MAX8731 for dV/dt filtering

per DELL's recommendation

3

4

5

6

51

51

51

PWR

PWR

PWR

10/27

10/27

10/27

Kenny

Kenny

Kenny

Moved battery voltage feedback to charge

states Connected pins 15 and 16 together changed connection to +VCHGR.

Add PR155

Added layout notes for PC135 and PC136

Adjusted the current setting of the "UL"

circuit and added hysteresis change value of the PR142 from 499K to 4.32M,

change value of the PR148 from 33.2K to 27.4K

7

50

50

PWR

PWR

10/27

10/27

Kenny

Kenny

Adjusted the Load line setting change value of the PR108 from 249K to 12K,

change value of the PR114 from 48.7K to 2.37K

Remove PC93

Adjusted the transient setting Change value of the PR106 from511K to 392K,

Change value of the PR114 from 82.5K to 160K

Add PC94 as originally 1000pF

0.2

0.2

0.2

0.2

0.2

847 PWR 10/31 Kenny When AC souce plug in, the suson turn on

about 120ms immediately.

Change value of the PR27 from10K to 0,

Change value of the PR30 from 10K to 0.

Add PR156 and PR157

947 PWR 11/02 Kenny Remove PR156 and change PR157 location

from PR30_1 to PR30_2.

10 51 11/02 Kenny Vcore noise issue and ME's high limit

Remove PC74 and add PC

Change value of the PC79 from 1210 type to 1206,

Change value of the PC80 from 1210 type to 1206

11 51

PWR

PWR 11/07 Kenny Follow MAX8731 reference schematic of

A07 version

Add Table1 for ADP_OCP circuit.

Modify value of PR147 from 59K to 56.2K

12 47 PWR 11/07 Kenny

Follow TPS51120 reference schematic of

A06 version

Change value of the PR27 from 0 to 10K,

Change value of the PR30 from 0 to 10K.

13

14

51

51

PWR

PWR

11/29

11/29

Kenny

Kenny

Follow COE reference schematic of

A09 version. PC135 may not be needed

Change PC135 to "NO STUFF"

Follow COE reference schematic of

A09 version. PC138 may be needed Add PC138

0.2

0.2

0.2

0.2

0.2

0.2

0.3

15 51 PWR 12/12 Kenny Deeply discharged battery problem Add PR158 and PD19

0.3

0.3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 2

57 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

1 PWR 12/15 0.3

Resolve a Choke for Dual Core CPU

Kenny Add PL17 and POP 4@ for Dual core

50

246 PWR 12/15 Kenny Modify battery connecter the same pine

length for P+ and GND Change P/N form DC040001R0L to DC04000380L

351 PWR

PWR

12/20 Kenny

Kenny4

Add PC139 and PC140 for "NO STUFF"

Solve Inaccuracte CP point for 65W

adapter-in current

47 TDC requirement Add PR159

550 PWR

12/20

12/20 Kenny We plan to add MOSFET for dual core CPU

and have layout space limitation. So change

PL13 size from 1810 to 1206.

Change PL13 size from 1810 to 1206.

0.3

0.3

0.3

0.3

Delay the 1.5VRUN to meet Intel spec

for the 3VRUN vs 1.5VRUN specification.

6

7

8

48

47

50

PWR

PWR

PWR

12/21

12/21

12/21

Kenny

Kenny

Kenny

Add PD20 and PC141

Change to 0 ohms for PR159

Del PR151 and PC83

GG Issue item 19

EMI test is ok, and have layout limitation

issue for Dual core after adding

low side MOS

9 49 PWR 12/21 Kenny

Follow MO7_DDRII_SC480_TPS51116_A04 circuit Change PR78 to 27.4K, PR77 to 17.4K.

0.3

0.3

0.3

0.3

10

11

12

47

48

49

PWR

PWR

PWR

12/22

12/22

12/22

Kenny

Kenny

Kenny

TDC requirement Change to 470K ohms for PR159

Follow M07_1_05V1_5V_SC483_TPS51483_A07

circuit "NO STUFF" for PC141

Modify single and dual core note

0.3

0.3

0.3

13 50 PWR 12/23 Kenny TDC requirement Change PC90 from 680p to 390pF 0.3

14 50 PWR 12/26 Kenny Modify the Footprint for PQ16 0.3

15 PWR 12/27 Kenny

47 Kemet CAP quantity issue Change from SGA00000N8L to SGA00001A8L for 2 pcs. (PC25)

Change from SGA00000N8L to SGA1933131L for 2 pcs. ( PC23) 0.3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 2

58 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

1 PWR 2/11 Footprint error for PD20

Kenny Modify footprint fron SOD323 to SOT323

48

2 51 PWR 2/11 Kenny Location error for MOSFET STUFF for PQ27, NO-STUFF for PQ16

3 50 PWR 2/20 Kenny The OCP setting is 20 A for Dual Core CPU Adding NO-stuff for 215K on PR104

0.4

0.4

0.4

450 PWR 2/21 Kenny The load line is "-2.1m" for Dual Core CPU. Adding NO-stuff for 5.76K on PR114

5

6

48

49

PWR

PWR

2/22

2/22

Kenny

Kenny

CYNTEC is not on DELL's AVL

CYNTEC is not on DELL's AVL

Change the vender from DELTA to CYNTEC on PL9 and PL10

Change the vender from DELTA to CYNTEC on PL12

0.4

0.4

0.4

747 PWR 2/22 Kenny Follow COE schetmatic for A06 version Modify net name from +3.3V_ALW to +3.3V_RTC_LDO for PU7_PIN5 0.4

8 51 PWR 2/23 Kenny Follow COE schetmatic for A11 version Modify PQ18 and PQ19 from SI4825 to SI4835

9 47 PWR 2/24 Kenny No 2nd source for PC25 Change from SGA00001A8L to SGA1933131L for 2 pcs. (PC25)

0.4

0.4

10 47 PWR 3/6 Kenny +3.3V_RTC_LDO voltage drop issue Add PU10, PC143, PC142, PR160, PR162 and PR161 0.4

11 45 PWR 3/8 Kenny +3.3V_RTC_LDO voltage drop issue Move PU10, PC143 and PC142 from page47 to page45

12 50 PWR 3/17 Mike Error description for Dual Core load line Dual Core Load Line change to 2.1mohm

13

0.4

0.4

0.5

47 PWR 4/25 Kenny +3.3V_RTC_LDO voltage drop issue change PR40 from 470K to 4.7K,

- change PR159 from 470K to 2.2M,

- change PC32 from 0.1U to 0.01uF,

- add UN-STYFF Schottky diode PD21 in parallel to PR159

14 48

15 49

PWR 4/25

PWR 4/25

Kenny

Kenny

Delta ckoke has dimension issue

Delta ckoke has dimension issue

Change the vender from CYNTEC to DELTA on PL9 and PL10

Change the vender from CYNTEC to DELTA on PL9 and PL10

0.5

0.5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

LA-3071P

1.0

Changed-List History 2

59 59Friday, May 12, 2006

Version Change List ( P. I. R. List )

Item Issue DescriptionDate Request

Owner Solution Description Rev.Page# Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

1 PWR 4/25 CPU noise issue Kenny For Dual CPU: Modify PR101 from 10K to 20K

PC88 from 820P to 470P

PC90 from 390P to 470P

50 0.5

2 50 PWR 4/28 Kenny CPU noise issue No STUFF PC80 for DUAL CORE CPU

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