Compal LA 3071P Schematics. Www.s Manuals.com. R1.0 Schematics
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : HAU30
PCB NO : LA-3071P
COMPAL P/N : DA800004H1L
1
Crockett Schematics Document
2
2
uFCBGA Mobile Yonah-ULV
Intel Calistoga-GMS + ICH7M
2006-5-12
REV : 1.0 (DELL: A00)
3
3
4
4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number
DA800004H1L
Description
PCB 00B LA-3071P REV1 M/B
Compal Electronics, Inc.
BOM NO. 43140131L01
PCB P/N: DA800004H1L
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Cover Sheet
Size
B
C
D
Rev
1.0
LA-3071P
Date:
A
Document Number
Friday, May 12, 2006
Sheet
E
1
of
59
5
4
3
2
1
PS_ID Detector
D
D
S
3
2
+3.3VX
Source
+3.3V_RTC_LDO_1
PU10
PS_ID
PS_ID
1
<40>
IN
OUT
5
NC
4
EN
2
1
3
1
MIC5235-3.3BM5_SOT23-5~D
2
PC142
2.2U_0603_6.3V6K~D
2
PC143
1U_0805_25V4Z~D
2
3
1
PR6
@ 100_0402_5%~D
1
2
PD2
DA204U_SOT323~D
PR5
10K_0402_1%~D
2
1
+5V_ALW
GND
+5V_ALW
2
G
PR4
100K_0402_1%~D
1
2
3
2
1
+PWR_SRC
@
PS_ID_DISABLE# <40>
1
@
D
PS_ID_IN
PR3
33_0402_5%~D
1
2
1
PS_ID_IN
PD3
SM24_SOT23
<38>
PR1
2.2K_0402_5%~D
1
2
PQ1
FDV301N_SOT23
+3.3V_ALW
1
PR2
0_0402_5%~D
1
2
@
3
PD1
DA204U_SOT323~D
+5V_ALW
2
B
PR7
15K_0402_1%~D
1
2
C
C
PQ2
PMBT3904_SOT23~D
C
3
E
+DC_IN Source
+DOCK_DC_IN
DC-_1
3
GND1
DC-_2
4
+ DCIN_JACK
@
FOX_JPD113E-LB103-7F
-D CIN_JACK
PL3
FBM-L11-453215-900LMAT_1812~D
1
2
PQ_G
PC5
10U_1206_25V6M~D
2
1
DC+_2
GND2
PR9
4.7K_0603_5%~D
2
1
GND3
2
PC4
0.1U_0603_25V7K~D
2
1
1
PC3
0.1U_0603_25V7K~D
2
1
6
5
DC+_1
PR8
240K_0402_5%~D
2
1
7
SINGAL
GND4
PC1
0.47U_0805_25V7k
1
2
8
PC6
0.01U_0402_25V7K~D
2
1
9
B
+DC_IN_SS
4
1
2
3
PL2
FBM-L11-453215-900LMAT_1812~D
1
2
PJDCIN
PQ3
SI4825DY_SO8~D
8
7
6
5
<38>
PC2
0.01U_0402_25V7K~D
2
1
PS_ID_IN
PR10
47K_0402_5%~D
2
1
PL1
BLM11B102S 0603~D
PWR_ID2
1
B
THE POINT
NOTE: "THE POINT LOCATED
AT PS MODULE
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+DCIN
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
1
1
of
10
A
B
C
D
E
Compal confidential
Block Diagram
Model : HAU30
CPU ITP Port
FAN
+FAN1_VOUT
GUARDIAN
EMC4000
pg 18
1
+3.3V_SUS
Clock Generator
SLG84450VTR
Pentium-M
Yonah-2M ULV
uFCBGA CPU
Thermal
+1.05V_VCCP
+3.3V_RUN
pg 7
1
+1.05V_VCCP
pg 18
+VCC_CORE
+2.5V_RUN
pg 6
DDRII 512MB on Board
+0.9V_DDR_VTT
pg 7,8
479pin
+1.8V_SUS
pg 18
H_A#(3..31)
CRT CONN
+5V_RUN
LVDS CONN
+LCDVDD
+GFX_PWR_SRC
DVI
INTEL
LVDS
DVI Bridge SI1362
DDRII-DIMM X1
BANK 2, 3
400/533MHz
pg 15
+0.9V_DDR_VTT
Calistoga-GMS
pg 19
+3.3V_RUN
+1.8V_RUN
Memory BUS
(DDR2) +1.8V_SUS
FSB 400/533 MHz
RGB
pg 16,17
H_D#(0..63)
System Bus
pg 21
+1.8V_SUS
+1.5V_RUN
+1.8V_SUS
DVO
998pin BGA
+1.05V_VCCP
pg 20
+3.3V_RUN
TV
+2.5V_RUN
pg 10,11,12,13,14
DMI
2
+1.5V_RUN
100MHz
PCI BUS
IDSEL:AD24
(PIRQA#,GNT0#,REQ0#)
DOCKING PORT
+DOCK_PWR_SRC
+3.3V_RUN
+2.5V_LOM
DOCKING
BUFFER
+5V_RUN
pg 38
pg 37
HUB USB[1]
3
pg 36
USB[0]
Mini Card 1
WWAN
+3.3V_RUN
+3.3V_LAN
+1.5V_RUN
+SD_VCC
pg 32
+3.3V_RUN
1394 CONN
pg 31
48MHz
+1.5V_RUN
REAR
pg 36
pg 29
+SIM_PWR
pg 36
M DC
pg 30
SMSC SIO
ECE5018
HUB USB[4]
+3.3V_ALW
+3.3V_LAN pg 30
RJ45
Transformer
+2.5V_LOM pg 30
+3.3V_SUS
pg 34
Cable
HUB USB[2]
3V/5V/15V
pg 47
Power On/Off
SW & LED
PATA HDD
pg 39
+3.3V_HDD
pg 26
HUB_USB[3]
Bluetooth
4
pg 45
SMSC KBC
MEC5004
Fingerprint
SLOT
+RTC_CELL
+3.3V_ALW
pg 35
+3.3V_RUN pg 41
CHARGER
pg 46
AMP & INT.
Speaker
pg 40
pg 48
pg 51
pg 49
RJ11
pg 30
pg 27
SPI
+5V_SUS
DC/DC Interface
INT MIC
+5V_SUS
HeadPhone &
MIC Jack
+3.3V_RUN
pg 28
pg 28
4
ST M25P80
Int.KBD &
Stick pg 41
+3.3V_RUN pg 37
1.8V/0.9V
+3.3V_RUN
+VDDA
+5V_RUN pg 35
FIR
BATT IN
Azalia Codec
STAC9200
Smart Card
OZ77C6
+3.3V_RUN
pg 34
pg 44
1.5V/1.05V
3
HUB USB[1]
USB_BIO
DC IN
PWR USB X1
SPI
+3.3V_RUN
33MHz
USB[1]
LAN SWITCH
PI3L500E
pg 33
+5V_SUS
DH_PORT_PWRSRC pg 33
+3.3V_LAN
SIM Card
pg 42,43
USB[5]
+5V_SUS
ATA100
pg 22,23,24,25
HUB USB[2]
Power Sequence
REAR
Azalia I/F
+1.05V_VCCP
PCI Express BUS
LPC BUS
GIGA Enthernet
BCM5752
pg 33
USB Ports X1
USB[6]
+3.3V_SUS
Card Bus SLOT
pg 32
+3.3V_RUN/ +1.5V_RUN 100MHz
Mini Card2
WLAN
SD card SLOT
pg 31,32
USB[7]
+3.3V_RUN
+3.3V_LAN
+1.5V_RUN
+5V_SUS
INTEL
ICH7-M
652pin BGA
2
USB Ports X1
REAR
+3.3V_RUN 33MHz
IDSEL:AD17
(PIRQB,C,D#,GNT2#,REQ2#)
CardBus & 1394 & SD
R5C843 CSP208
+3.3V_RUN
+3.3V_SUS
USB[4]
+3.3V_ALW
pg 40
DELL CONFIDENTIAL/PROPRIETARY
pg 45
Compal Electronics, Inc.
Stick
VCORE (IMVP-6)
+5V_RUN
pg 50
Title
Touch Pad
Block Diagram
Size
pg 41
Document Number
Rev
1.0
LA-3071P
Date:
A
B
C
D
Friday, May 12, 2006
Sheet
E
2
of
59
5
4
3
2
1
ESD Diodes
+3.3V_ALW
D
D
9
7
2
3
2
3
2
3
2
3
8
6
+VCHGR
PC8
2200P_0402_50V7K~D
2
1
+PBATT
PJBAT1
SUYIN200277MR009G508ZR~D
BATT1+ 9
BATT2+ 8
SMB_CLK 7
SMB_DAT 6
BATT_PRES# 5
SYSPRES# 4
BATT_VOLT 3
10 GND
BATT1- 2
11 GND
BATT2- 1
5
Z4304
Z4305
Z4306
PR12
100_0402_5%~D
1
2
PR13
100_0402_5%~D
1
2
Z4307
PR14
100_0402_5%~D
1
2
PR15
100_0402_5%~D
1
2
PBAT_SMBCLK <40,51>
PBAT_SMBDAT <40,51>
4
PL4
FBM-L11-453215-900LMAT_1812~D
1
2
PR11
10K_0402_1%~D
2
1
PD7
@ DA204U_SOT323~D
PC7
0.1U_0603_25V7K~D
2
1
PD6
@ DA204U_SOT323~D
1
PD5
@ DA204U_SOT323~D
1
PD4
@ DA204U_SOT323~D
1
+PBATT
1
Battery Connector
+3.3V_ALW
3
2
1
PBAT_PRES# <39>
SUYIN_200028MR009G502ZL
TOP view
PBAT_ALARM# <39>
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
Battery Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
1
2
of
10
5
4
3
2
Ceramic Capacitors :
PCI TABLE
IDSEL
REQ#/GNT#
PIRQ
CARD BUS
AD17
2
B,C,D
DOCKING
AD24
0
A
PCI DEVICE
0.1U_0402_6.3VXX
Tolerance
Temperature Characteristics
Rated Voltage
D
1
D
Package Size
Value
PM TABLE
+5V_RUN
Tantalum or Polymer Capacitors :
power
plane
+3.3V_ALW
+5V_ALW
10U_D2_10VX_R45
State
+1.8V_RUN
+5V_SUS
+0.9V_DDR_VTT
+1.8V_SUS
+1.5V_RUN
+15V_SUS
+VCC_CORE
+1.05V_VCCP
Tolerance
S0
ON
ON
ON
Rated Voltage
S1
ON
ON
ON
Package Size
S3
ON
ON
OFF
Value
S5 S4/AC
ON
OFF
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
USB
Temperature Characteristics:
Symbol
3
4
5
6
7
Z5P
Y5U
Y5V
Y5P
X5R
X7R
A
B
C
D
E
F
G
X6S
BJ
CH
CJ
CK
SH
SJ
0
1
Z5U
Z5V
8
9
NPO
COG
CODE
2
H
I
J
K
UJ
UK
SL
X5S
Tolerance:
Symbol
A
CODE
K
+-10%
B
C
D
+-0.05PF +-0.1PF +-0.25PF +-0.5PF
N
M
+-20%
+-30%
P
Q
F
G
+-1PF
+-2%
+-3%
V
X
Z
H
TABLE
USB PORT#
DESTINATION
USB HUB
DESTINATION
0
Mini 2(WLAN)
1
PC Card Bay
1
USB Hub (5018)
2
Mini 1(WWAN)
2
N/A
3
SMART CARD
3
N/A
4
Blue tooth
4,6
REAR
USB HUB on
OZ77C6LN
DP_HUB
J
+-5%
NOTE1:
@XX :
C
+2.5V_RUN
Capacitor Spec Guide:
A
+3.3V_RUN
+3.3V_SUS
Low ESR Mark : 45 m ohm
C
B
+3.3V_SRC
Depop component
5
PWR USB
7
Docking
B
DESTINATION
Fingerprint
A
+100,-0% +30,-10% +20,-10% +40,-20% +80,-20%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Index and Config.
Size
4
3
2
Rev
1.0
LA-3071P
Date:
5
Document Number
Friday, May 12, 2006
Sheet
1
3
of
59
5
4
3
2
1
@ PJP2
1
2
15 Volt
Maximum Current: 10mA
DC/DC +3V/ +5V/ +15V
PAD-OPEN 4x4m
+DC1_PWR_SRC
+15VP
TPS51120_DRVL1
TPS51120_LL2
15
LL2
PGND1
24
TPS51120_DRVL2
16
DRVL2
VO1
17
PGND2
VFB1
COMP1
COMP2
CS1
CS2
VREF2
TONSEL
GND
PGOOD1
PGOOD2
PC30
10U_0805_6.3V5K~D
2
1
<40>
ALWON
PR36
1K_0402_5%~D
2
1
PR38
0_0402_5%~D
2
1
+3.3V_RTC_LDO_1
+3.3V_RTC_LDO
4
<18> THERM_STP#
S
3
RUN_ENABLE <42>
3
1
1
2
1
3
PC16
2.2U_1206_25V7M~D
E
C
2
B
1
2
2
PR137
10K_0805_5%~D
2
1
PC9
2.2U_1206_25V7M~D
PD9
EC11FS2_SOD106~D
+15VS
2
1
PC15
2200P_0402_50V7K~D
2
1
PC14
0.1U_0603_25V7K~D
2
1
5
6
7
8
4
2
+
2
C
+VCC_TPS51120
PR32
0_0402_5%~D
1
2
@
0_0402_5%~D
1
2
GNDA_DCDC1
5V OCP
Fsw=290 KHZ
Rds_on_MAX=20m; Itrip_MIN=8.5uA;L=4.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=5/4.7u * 1/290K *(1-5/19)=2.7A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*10K/20m=4.25A
Ivalley= Itrip*Rtrip/Rds_on=10u*10K/20m=5A
Iocp_MIN=4.25+2.7/2=5.6A
Iocp=5+2.7/2=6.35A
PR35
B
@ 0_0402_5%~D
1
2
PR37
+VCC_TPS51120
PR133
0_0603_5%~D
2
1
@ 0_0402_5%~D
1
2
GNDA_DCDC1
PR39
G
D
6
5
2
1
3
2
1
PR31
100K_0402_1%~D
1
2
PC31
1000P_0402_50V7K~D
2
1
PR157
100K_0402_1%~D
1
2
3
+3.3V_SRCP
PR34
@
1
@
SUSPWROK_5V <49>
@
1
PR160
0_0402_5%~D
@
+3.3V_SRCP
TPS51120_SKIP#
B
GNDA_DCDC1
GNDA_DCDC1
1
4
PU7
SN74AHC1G32DCKR_SSOP5~D
2
5
O
PC118
0.1U_0603_25V7K~D
2
1
PD18
BAT54CW_SOT323~D
2
G
I0
P
3
I1
PQ4
SI4800DY-T1_SO8~D
+3.3V_RTC_LDO
PR30
10K_0402_5%~D
2
1
5 Volt +/- 5%
Design Current:3.63A
Maximum current: 5.191 A
OCP: 6.35A
PR29
0_0402_5%~D
1
2
32
EN3
PR28
0_0402_5%~D
1
2
VREG3
D
@
GNDA_DCDC1
PC29
1000P_0402_50V7K~D
2
1
PR162
19
@ 0_0402_5%~D
2
1 10
TPS51120_CS1
TPS51120_CS2
PR26
14.7K_0402_1%~D
1
2
EN2
EN1
PC28
1000P_0402_50V7K~D
2
1
VFB2
12
29
PR25
10K_0402_1%~D
1
2
VO2
6
TPS51120_VFB1
PC27
1000P_0402_50V7K~D
2
1
8
TPS51120_VO1
3
2
7
23
18
4
31
5
30
11
PAD
TPS51120_VO2
1
@
4
PC23
330U_D3L_6.3VM_R25~D
25
PC24
0.1U_0603_25V7K~D
2
1
TPS51120_LL1
DRVL1
PR23
0_0402_5%~D
1
2
26
DRVH2
PR19
0_0402_5%~D
2
TPS51120
32 QFN 5X5LL1
TPS51120_VFB2
@
+5V_SUSP
1
VBST2
14
+5V_SUSP_L
PR22
0_0402_5%~D
1
2
DRVH1
13
PC21
0.1U_0603_25V7K~D
1
2
3
2
1
TPS51120_DRVH1
EN5
PQ25
2N2222_SOT23~D
1
3
PL6
+5V_SUSP
4.7U_SDT-1204P-4R7D-122GP_20%
5
6
7
8
PR18
0_0603_5%~D
1
2
PQ6
SI4810BDY_SO8~D
28
4
<40,42,43> SUS_ON
2
PC18
1U_0603_10V6K~D
2
1
21
VBST1
TPS51120_DRVH2
PR136
0_0402_5%~D
2
1
1
PC17
10U_1206_25V6M~D
2
1
VREG5
V5FILT
27
PR27
10K_0402_5%~D
2
1
<40,42> AUX_EN
1
VIN
20
GNDA_DCDC1
<40,42,43> SUS_ON
3
22
9
PR16
0_0805_5%~D
1
2
4
PR20
0_0603_5%~D
1
2
@
@
2
PC19
1U_0603_10V6K~D
2
1
PC20
0.1U_0603_25V7K~D
2
1
PC22
0.1U_0603_25V7K~D
2
1
1
2
3
@
Place these CAPs
close to FETs
PU1
8
7
6
5
+3.3V_SRCP_L
@
33
+VCC_TPS51120
PQ7
FDS6690AS_NL_SO8~D
PR21
0_0402_5%~D
1
2
2
2
PR24
0_0402_5%~D
1
2
+
PR135
0_0402_5%~D
1
2
C
1
PC26
0.1U_0603_25V7K~D
2
1
PC25
330U_D3L_6.3VM_R25~D
+3.3V_SRCP
@
SKIPSEL
PL7
2.7U_SIL1055R-2R7PF_9A
1
GNDA_DCDC1
4
1
2
3
+3.3V_SRCP
8
7
6
5
PQ5
SI4800DY-T1_SO8~D
3.3 Volt +/- 5%
Design Current: 6.5 A
Maximum current: 9.1A
OCP: 10.95A
+5V_ALW
PD10
RB717F_SOT323~D
PR17
5.1_0603_5%~D
2
1
PC13
10U_1206_25V6M~D
2
1
+VCC_TPS51120
@
Place these CAPs
close to FETs
PC134
10U_1206_25V6M~D
2
1
PC120
10U_1206_25V6M~D
2
1
PC12
10U_1206_25V6M~D
2
1
D
PC11
0.1U_0603_25V7K~D
2
1
PC10
2200P_0402_50V7K~D
2
1
+15VS_L
PR138
0_0805_5%~D
PD8
1
2
MMBZ5245B_SOT23~D
PL5
FBM-L11-453215-900LMAT_1812~D
1
2
+PWR_SRC
@
+3.3V_RTC_LDO
PQ24
FDC655BN_NL_SSOT-6~D
<19,40,42,43,48,49> RUN_ON
0_0402_5%~D
1
2
+VCC_TPS51120
+15VP
1
2
3
@
D
2
PQ8
@ SI2301BDS-T1-E3 _SOT23~D
@ PJP4
1
3
2
+5V_SUS
PAD-OPEN 4x4m
1
3
@ PJP5
PQ10
S @ RHU002N06_SOT323
+3.3V_SRCP
1
2
+3.3V_SRC
PAD-OPEN 4x4m
@ PJP12
1
A
2
PAD-OPEN 4x4m
DELL CONFIDENTIAL/PROPRIETARY
PQ11
RHU002N06_SOT323
2
G
+15V_SUS
+5V_SUSP
D
2
G
PC33
4.7U_1206_10V7K~D
2
1
1
2
PR159
2.2M_0402_5%~D
1
2
1
PD21
BAT54CW_SOT323~D
2
PAD-OPEN 4x4m
@
PQ9
SI2301BDS-T1-E3 _SOT23~D
G
PR40
4.7K_0402_5%~D
2
1
PC32
0.01U_0603_25V7K~D
2
1
D
S
3
1
G
+3.3V_ALW
PR41
200K_0402_1%~D
2
1
3
+3.3V_ALW
3.3V OCP
Fsw=440 KHZ
Rds_on_MAX=15m; Itrip_MIN=8.5uA;L=2.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=3.3/2.7u * 1/440K *(1-3.3/19)=2.3A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*14.7K/15m=8.33A
Ivalley=
Itrip*Rtrip/Rds_on=10u*14.7K/15m=9.8A
A
Iocp_MIN=8.33+2.3/2=9.48A
Iocp=9.8+2.3/2=10.95A
1
D
S
PR161
0_0805_5%~D
2
1
@ PJP3
@
Compal Electronics, Inc.
S
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+3.3V/+5V/+15V
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
1
3
of
10
5
4
3
ALWON
D
2
1
+5V_ALW
D
ALWON
ADAPTER
+3.3V_ALW
+PWR_SRC
RUN_ON
FDS4435
+GFX_PWR_SRC
BATTERY
TPS51120
AD3207
SC483
SC480
+5V_RUN
+15V_SUS
VDDA
L47
+3.3V_RUN
+VCC_CORE +1.5V_RUN
RUN_ON
SUSPWROK_5V
RUNPWROK
+VCCP +1.8V_SUS +0.9V_DDR_VTT
RUN_ON
SI4800
ENAB_3VLAN
RUN_ON
793475
(Option)
PL8
AUDIO_AVDD_ON
RUN_ON
SI4800
RUNPWROK
SUS_ON
+3.3V_SRC
+5V_SUS
B
RUNPWROK
C
SUS_ON
C
SI3456
+3.3V_LAN
B
SI3456
+1.8V_RUN
EMC4000
A
A
DELL CONFIDENTIAL/PROPRIETARY
+2.5V_RUN
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Power Rail
Size
4
3
2
Rev
1.0
LA-3071P
Date:
5
Document Number
Friday, May 12, 2006
Sheet
1
4
of
59
A
B
C
@ PJP6
1
D
+5V_SUS
2
PR140
100K_0402_1%~D
2
1
<19,40,42,43,47,49> RUN_ON
<43> 1.5V_RUN_PWRGD
+1.5V_RUN_P
1
PR63
AGND2
14
6
DH1
5
LX1
4
ILIM1
DL1
TON2
9
BST2
21
DH2
20
LX2
19
ILIM2
18
DL2
16
VOUT2
10
FBK2
12
24
VOUT1
26
FBK1
22
EN/PSV1
EN/PSV2
8
27
PGOOD1
PGOOD2
13
PC40
10U_1206_25V6M~D
2
1
PC39
0.1U_0603_25V7K~D
2
1
PR44
750K_0402_1%~D
2
PC38
2200P_0402_50V7K~D
2
1
5@ PR48
499K_0402_1%
1
2
GNDA_DC2B
PC48
0.1U_0603_25V7K~D
2
1
2
1
PR50
0_0603_5%~D
PR52
12.7K_0402_1%
1
2
PR53
5@ 10K_0402_1%~D
1
2
+1.05V_VCCP_P
PQ13
FDS6994S_SO8~D
5 D1
G1 4
6 D1
S1 3
7 D2
G2 2
8 D2
S2 1
PL10
3.3uH_PCMC063T-3R3MN_6A_20%
2
1
1
+
2
PC53
@ 1U_0603_10V6K~D
2
1
VCCA2
AGND1
Place these CAPs
close to FETs
PC51
330U_D2E_2.5VM_R9
VCCA1
28
1.05V +/- 5%
Thermal Design Current: 3.36A
Maximum Current:4.8A
MIN_OCP:5.2A
PR55
16.5K_0402_1%
2
1
15
11
PC46
1000P_0402_50V7K~D
2
1
1
PC42
1U_0603_10V6K~D
2
1
PC41
1U_0603_10V6K~D
2
1
PGND2
1
2
1
PR60
1K_0402_1%~D
2
1
2
+3.3V_RUN
2
PC141
0.1U_0603_25V7K~D
PR57
15K_0402_1%~D
2
1
SC1485ITSTR-TPS51483_TSSOP28
Use PR55 and P57 for
Voltage Margining.
GNDA_DC2B
PR139
@ 0_0402_5%~D
1
2
1.05V_RUN_PWRGD <43>
PR62
1K_0402_1%~D
1
2
0_0603_5%~D
2
1
@ PJP7
3
PGND1
2
1
+3.3V_RUN
1
BST1
@
MMBD4148W-7-F_SOD323~D
GNDA_DC2A
17
25
TON1
PC55
18P_0402_50V8J
2
1
PR58
15K_0402_1%
2
1
PD20
Use PR56 and PR58 for
Voltage Margining.
PR56
30K_0402_1%
1
2
VDDP2
7
PR51
8.45K_0402_1%
1
2
PR54
5@ 9.09K_0603_1%~D
1
2
+
VDDP1
GNDA_DC2A 23
1
PR49
0_0603_5%~D
1
3
Create new P/N
PC54
82P_0402_50V8J
2
1
PC47
0.1U_0603_25V7K~D
2
1
2
PU2
PC45
PR46
1U_0603_6.3V6M 10_0402_5%
1
2
1
2
1
PR47
5@ 453K_0402_1%~D
2
1
PQ12
FDS6994S_SO8~D
4 G1
D1 5
3 S1
D1 6
2 G2
D2 7
1 S2
D2 8
2
PC49
330U_D2E_2.5VM_R9
2
PC50
@ 1U_0603_10V6K~D
2
1
PL9
3.3uH_PCMC063T-3R3MN_6A_20%
2
1
Place these CAPs
close to FETs
3
PD17
BAT54A-7-F_SOT23~L
PR61
100K_0402_1%~D
2
1
+1.5V_RUN_P
2
PC43
PR43
1000P_0402_50V7K~D
1M_0402_5%~D
2
1
1
2
PC44
PR45
1U_0603_6.3V6M 10_0402_5%
1
2
1
2
1.5V +/- 5%
Thermal Design Current: 2.5A
Maximum Current: 3.6A
MIN_OCP: 3.7A
PC37
2200P_0402_50V7K~D
2
1
1
PC36
0.1U_0603_25V7K~D
2
1
PC35
10U_1206_25V6M~D
2
1
+DC2_PW R_SRC
SC483/TPS51483
PL8
FBM-L11-453215-900LMAT_1812~D
1
2
+PWR_SRC
PC34
1U_0603_10V6K~D
2
1
PAD-OPEN 4x4m
2
3
+1.5V_RUN
PAD-OPEN 4x4m
GNDA_DC2A
PR64
@ PJP8
+1.05V_VCCP_P
1
2
+1.05V_VCCP
0_0603_5%~D
2
1
PAD-OPEN 4x4m
GNDA_DC2B
BOM
Structure
Description
----------------------------------------------@
Do Not Populate
4@
Populate for Semtech - SC483 Only
5@
Populate for Ti - TPS51483 Only
4
4
Ref Des
SC483
TPS52483
--------------------------------PR56
30.0K
15.0K
PR58
15.0K
15.0K
PR55
16.5K
11.8K
PR57
15.0K
29.4K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
+1.5VRUNP /+VCCP_1P05VP
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
D
4
of
10
5
4
3
2
1
+3.3V_SUS
2.2K
D
ICH7-M
C22
ICH_SMBCLK
B22
ICH_SMBDATA
+3.3V_RUN
2.2K
2N7002
2N7002
+3.3V_ALW
10K
5
2.2K
CLK_SCLK
16
+3.3V_SUS
32
6
2.2K
10K
30
C7
C8
32
5752M
LOM
WWAN
SMBUS Address [TBD]
30
SMBUS Address [D2]
DDR II 512M
ON Board
SMBUS Address [TBD]
SMBUS Address [A0]
8
DAT_SMB
+3.3V_ALW
GUARDIAN
7
197
SMBUS Address [2F]
195
+5V_ALW
Power USB
C
10K
10
DOCK_SMB_CLK
9
DOCK_SMB_DAT
DOG house
10K
DIMM1
SMBUS Address [A2]
SMBUS Address [5A]
C
39
+5V_ALW
SIO
40
DOCKING
SMBUS Address [C4, 72, 70, 48]
+3.3V_ALW
8.2K
Macallan IV
17
WLAN
SMBUS Address [C8]
CLK_SMB
CLK_SDATA
D
CLK GEN.
112
SBAT_SMBCLK
111
SBAT_SMBDAT
8.2K
6
+3.3V_ALW
INV
5
Inverter
SMBUS Address [58]
B
B
+3.3V_ALW
8.2K
8
PBAT_SMBCLK
7
PBAT_SMBDAT
8.2K
100
3
4
BATTERY
CONN
SMBUS Address [16]
10
CHARGER
SMBUS Address [12]
+3.3V_ALW
100
9
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
SMBUS TOPOLOGY
Size
4
3
2
Rev
1.0
LA-3071P
Date:
5
Document Number
Friday, May 12, 2006
Sheet
1
5
of
59
5
4
3
2
1
NOTE: Component Values Shown for SEMTECH SC480 ONLY.
For Texas Instruments TPS51116, Please USE Reference BOM.
@ PJP9
D
2
PAD-OPEN 4x4m
+5V_SUS
VDDP
15
REF
VDDP
14
6
VCCA
PGD
13
@
@ GNDA_DDR
PR74
100_0402_5%~D
GNDA_DDR
1
2
PC58
10U_1206_25V6M~D
2
1
PC132
@ 10U_1206_25V6M~D
2
1
2
1
+
2
PC62
0.1U_0402_10V7K~D
2
1
@
PC69
1U_0603_10V6K~D
2
1
NC
PAD
25 PAD
12
VTTEN
EN/PSV
11
10
FB
9
NC
TPS51116
20 QFN 4 X 4
+
PC60
220U_D2_4VM~D
TON
5
PC133
220U_D2_4VM~D
4
16
1
C
PR69
0_0402_5%~D
1
2
PC70
1U_0603_10V6K~D
2
1
17
3
PR70
100K_0402_1%~D
2
1
18
7
PR66
12.4K_0402_1%~D
2
1
19
DL
21
20
LX
DH
PGND1
PGND1
PU3
SC480ITSTR_MLPQ24~D
VSSA
ILIM
+5V_SUS
SUSPWROK_1P8V <43>
GNDA_DDR
SUSPWROK_5V <47>
<5V_3V regulator>
<19,40,42,43,47,48>
1
PR76
Create new P/N
@ 27.4K_0603_1%~D
PR77
B
@17.4K_0603_1%~D
2
@
2
PR75
0_0402_5%~D
1
2
PC73
0.1U_0402_10V7K~D
2
1
B
PL12
3.3uH_PCMC063T-3R3MN_6A_20%
2
1
RUN_ON
+1.8V_SUSP
+1.8V_SUSP
22
23
PR65
0_0603_5%~D
2
1
VTTS
+1.8V_SUSP
PQ14
FDS6994S_SO8~D
5 D1
G1 4
6 D1
S1 3
7 D2
G2 2
8 D2
S2 1
+1.8V_SUSP
GNDA_DDR
@
PGND2
2
1.8 Volt +/- 5%
Design Current:3.5A
Maximum current:4.9A
MIN_OCP:5A
1
PR73
0_0402_5%~D
2
1
PC71
1U_0603_10V6K~D
2
1
<10,15,16,17> V_DDR_MCH_REF
PR72
10_0402_1%~D
1
2
GNDA_DDR
PC72
PR71
1U_0603_10V6K~D
10_0402_1%~D
2
1
1
2
GNDA_DDR
1
BST
24
VTT
@
VTTIN
2
VDDQS
2
1
8
2
1
PC66
1U_0603_10V6K~D
2
1
1
PC65
10U_0805_6.3V5K~D
PC68
PR67
1000P_0402_50V7K~D 1M_0402_5%~D
1
2
1
2
+DDR_PWR_SRC
PC64
10U_0805_6.3V5K~D
PC63
10U_0805_6.3V5K~D
+1.8V_SUSP
+0.9V_DDR_VTTP
C
PD13
RB751V-40_SOD323~D
2
1
+5V_SUS
PC119
18P_0402_50V8J
2
1
.9 Volt +/- 5%
Design Current:1.05A
Maximum current:1.5A
PC59
0.1U_0603_25V7K~D
2
1
Place these CAPs
close to FETs
PC57
0.1U_0603_25V7K~D
2
1
PL11
FBM-L11-453215-900LMAT_1812~D
1
2
PC56
2200P_0402_50V7K~D
2
1
+PWR_SRC
+DDR_PWR_SRC
PC67
1U_0603_10V6K~D
2
1
1
PR68
10K_0402_1%~D
2
1
D
GNDA_DDR
NOTE: For Test purposes only
GNDA_DDR
@ PJP10
PAD-OPEN 4x4m
1
2
+1.8V_SUSP
+1.8V_SUS
GNDA_DDR
@ PJP11
+0.9V_DDR_VTTP
1
2
+0.9V_DDR_VTT
PAD-OPEN 43X79
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
+1.8VSUSP/ +0.9V_DDR_VT
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
1
5
of
10
5
4
3
+3.3V_RUN
D
D
ICH_SMBDATA
1
3
1
R5
2.2K_0402_5%~D
1
C6
0.1U_0402_16V4Z~D
1
2
C1
10U_0805_10V4Z~D
2
1
C2
0.1U_0402_16V4Z~D
2
1
C3
0.1U_0402_16V4Z~D
2
1
C4
0.1U_0402_16V4Z~D
2
2
G
1
1
2
C7
10U_0805_10V4Z~D
2
C9
0.1U_0402_16V4Z~D
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
1
0
0
1
0
1
1
0
1
1
1
CPU_BSEL
33.3
100
100
33.3
100
400
Place crystal within
500 mils of CK410
0
<31> CLK_SD_48M
<24> CLK_ICH_48M
<35> CLK_SMCARD_48M
<8,10> CPU_MCH_BSEL0
<8,10> CPU_MCH_BSEL1
<8,10> CPU_MCH_BSEL2
<40> CLK_PCI_5004
<38> CLK_PCI_DOCK
166
0
<29> CLK_PCI_LOM
1
1
49
54
65
VDDSRC
VDDSRC
VDDSRC
VDDSRC
30
36
VDDPCI
VDDPCI
12
VDDCPU
2 +CK_VDD_REF 18
1_0603_5%~D
2 +CK_VDD_48 40
2.2_0603_5%~D
1
R25
1
R27
CLK_XTAL_IN
<31> CLK_PCI_PCCARD
0
1
CLK_ICH_14M
CLK_SIO_14M
<24> CLK_ICH_14M
<39> CLK_SIO_14M
R40
R41
MCH_DREFCLK
<10> MCH_DREFCLK
R42
MCH_DREFCLK#
<10> MCH_DREFCLK#
R43
1
1
2
2 15_0402_5%~D
15_0402_5%~D
2
33_0402_5%~D
2
33_0402_5%~D
1
1
1
R46
+3.3V_RUN
B
CLK_PCI_ICH
CLK_ENABLE#
<22> CLK_PCI_ICH
<50> CLK_ENABLE#
R48
1
2
20
CLK_XTAL_OUT 19
FSA
FSC
FCTSEL1
USB_48MHz/FSLA
45
FSLB/TEST_MODE
23
REF0/FSLC/TEST_SEL
33
PCI_DOCK
32
PCI_LOM
27
96/100M_T
96/100M_C
1
27M_out 27M SSout
SRCT0
SRCC0
CPU_BCLK#
CPUT_ITP/SRCT10
6
CPU_ITP
CPUC_ITP/SRCC10
5
CPU_ITP#
SRCT9
3
PCIE_LOM
SRCC9
2
PCIE_LOM#
R28
R29
R31
R33
R53
R54
PCICLK1
CLKREQ8#
71
SRCT7
66
SRCC7
67
R49
R50
R52
CLKREQ7#
38
SRCT6
63
PCIE_ICH
SRCC6
64
PCIE_ICH#
CLKREQ6#
62
SRCT5
60
SRCC5
61
ITP_EN/PCICLK_F0
Vtt_PwrGd#/PD
R55
IREF
CLKREQ5#
29
SRCT4
58
SRCC4
59
SMBCLK
CLKREQ4#
57
SRCT3
55
56
SMBDAT
R44
R45
R47
4
GNDSRC
SRCC3
GNDCPU
CLKREQ3#
28
21
GNDREF
SRCT2
52
PCIE_MINI2
31
GNDPCI
SRCC2
53
PCIE_MINI2#
35
GNDPCI
CLKREQ2#
26
R61
R62
R63
42
GND48
SRCT1
50
PCIE_MINI1
68
GNDSRC
SRCC1
51
PCIE_MINI1#
CLKREQ1#
46
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
R64
R65
LCD100/96/SRC0_T
47
DOT96_SSC
LCD100/96/SRC0_C
48
DOT96_SSC#
R66
R68
R70
1
1
1
1
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
CLK_CPU_BCLK
33_0402_5%~D
CLK_CPU_BCLK#
2
33_0402_5%~D
2
CLK_CPU_ITP
33_0402_5%~D
CLK_CPU_ITP#
33_0402_5%~D
1
2
1
2
1
CLK_PCIE_LOM
2
33_0402_5%~D
CLK_PCIE_LOM#
2
33_0402_5%~D
2
10K_0402_5%~D
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
1
1
1
1
2 10K_0402_5%~D
1
2
1
2
1
2
1
2
1
2
1
1
2 10K_0402_5%~D
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1#
2
33_0402_5%~D
1
1
1
1
FCTSEL1
CLK_PCIE_ICH
33_0402_5%~D
CLK_PCIE_ICH#
33_0402_5%~D
2
4
CLK_MCH_BCLK# <10>
C
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_LOM <29>
CLK_PCIE_LOM# <29>
LOM_CLKREQ# <29>
+3.3V_RUN
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
B
CLK_PCIE_MINI2
33_0402_5%~D
CLK_PCIE_MINI2#
33_0402_5%~D
CLK_PCIE_MINI2 <36>
CLK_PCIE_MINI2# <36>
MINI2CLK_REQ# <36>
+3.3V_RUN
CLK_PCIE_MINI1 <36>
CLK_PCIE_MINI1# <36>
MINI1CLK_REQ# <36>
+3.3V_RUN
DREF_SSCLK <10>
2
2 10K_0402_5%~D
33_0402_5%~D
2
33_0402_5%~D
A
DREF_SSCLK# <10>
DELL CONFIDENTIAL/PROPRIETARY
SLG84450VTR_QFN72~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
D
CLK_MCH_BCLK <10>
+3.3V_RUN
10K_0402_5%~D
Title
Clock Generator
Size
Document Number
Rev
1.0
LA-3071P
Date:
5
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
R2
CLK_MCH_BCLK 2
R3
CLK_MCH_BCLK# 2
R6
CLK_CPU_BCLK
2
R7
CLK_CPU_BCLK# 2
R8
CLK_MCH_3GPLL 1
R9
CLK_MCH_3GPLL# 1
R10
CLK_PCIE_ICH
1
R11
CLK_PCIE_ICH#
1
R12
CLK_PCIE_LOM
1
R13
CLK_PCIE_LOM# 1
R14
CLK_PCIE_MINI2 1
R16
CLK_PCIE_MINI2# 1
R17
CLK_PCIE_MINI1 1
R18
CLK_PCIE_MINI1# 1
R19
MCH_DREFCLK
1
R20
MCH_DREFCLK# 1
R21
DREF_SSCLK
1
R22
<24>
DREF_SSCLK#
1
R23
<24>
CLK_3GPLLREQ# <10>
+3.3V_RUN
1
R71
10K_0402_5%~D
@ R72
10K_0402_5%~D
2
13
15
73
74
75
76
@ R67
10K_0402_5%~D
PIN48
CPUC0
MCH_3GPLL#
2
DOT96T DOT96C
PIN47
1
PIN44
FSA
1
1
0
PIN43
CPU_BCLK
H_STP_CPU#
R26
MCH_3GPLL
DOTC_96MHz/27MHz(SS)
1
2
FCTSEL1
CPUT0
14
H_STP_PCI#
R24
69
44
+3.3V_RUN
MCH_BCLK#
70
DOT96#
17
10
SRCT8
DOTT_96MHz/27MHz
CLK_SDATA
11
CPUC1
SRCC8
REF1
16
CPUT1
MCH_BCLK
PCICLK2
43
CLK_SCLK
H_STP_CPU#
PCICLK3
DOT96
9
H_STP_PCI#
24
72
22
CLKIREF
2
475_0402_1%~D
25
CPU_STOP#
CLKREQ9#
CLK14M_REF
39
PCI_SRC_STOP#
X2
41
37
7
8
X1
PCI_PCCARD
2
10K_0402_5%~D
PCI_ICH
VDDA
VDD48
PCICLK4/FCTSEL1
+3.3V_RUN
R69
10K_0402_5%~D
Place near CK410+
GNDA
VDDREF
34
56_0402_5%~D
1
R51
A
+CK_VDD_A
2
2.2_0603_5%~D
U1
X1
14.31818MHz_20P_1BX14318CC1A~D
1
2
R30
0_0402_5%~D
CLK_SD_48M
2
1
CLK_ICH_48M
R605 2
1 39_0402_5%~D
CLK_SMCARD_48M R32 1
2 39_0402_5%~D
R34 2
1 39_0402_5%~D
@ R561
8.2K_0402_5%~D
2
1
CLK_PCI_5004
R56 2
1 8.2K_0402_5%~D
R35
39_0402_5%~D
CLK_PCI_SIO
2
1
R36
39_0402_5%~D
CLK_PCI_PCCARD
1
2
R38
56_0402_5%~D
CLK_PCI_DOCK
1
2
R39
56_0402_5%~D
CLK_PCI_LOM
1
2
R37
56_0402_5%~D
<39> CLK_PCI_SIO
133
R15
C16
27P_0402_50V8J~D
2
1
Reserve
CPU_BSEL2(FSC) CPU_BSEL1(FSB)
2
C15
27P_0402_50V8J~D
2
1
33.3
100
333
2
C14
0.047U_0402_16V7K~D
S
100
2
C13
0.047U_0402_16V7K~D
266
2
1
1
0
2
+CK_VDD_REF
1
2
CLKSEL0
0
PCI
MHz
Place near each pin
W>40 mil
<15,17>
+CK_VDD_48
1
C12
4.7U_0603_6.3V6M~D
CLKSEL1
0
SRC
MHz
C10
4.7U_0603_6.3V6M~D
CLKSEL2
CPU
MHz
1
C
FSA
CLK_SCLK
C11
0.047U_0402_16V7K~D
*
FSB
3
C643
0.1U_0402_16V4Z~D
1
C8
0.1U_0402_16V4Z~D
2
2
G
FSC
CLK_SCLK
Q2
2N7002W-7-F_SOT323~D
+CK_VDD_A
1
1
1
2
2
L2
BLM18PG600SN1_0603~D
60ohm,500mA,0.1ohm
D
ICH_SMBCLK
C5
0.1U_0402_16V4Z~D
CLK_SDATA <15,17>
+3.3V_RUN
<24,29,36> ICH_SMBCLK
1
+CK_VDD_MAIN2
CLK_SDATA
2
CLK_CPU_ITP#
1
2
1
D
+CK_VDD_MAIN
1
2
L1
BLM18PG600SN1_0603~D
60ohm,500mA,0.1ohm
2
1
2N7002
<24,29,36> ICH_SMBDATA
S
Q1
2N7002W-7-F_SOT323~D
2
S
R4
2.2K_0402_5%~D
1
3
1
CLK_CPU_ITP
R1
+3.3V_RUN
G 2
2
+CK_VDD_MAIN
Friday, May 12, 2006
Sheet
1
6
of
59
4
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
K3
H2
K2
J3
L5
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H_ADSTB#0
H_ADSTB#1
L2
V4
ADSTB0#
ADSTB1#
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
DINV0#
DINV1#
DINV2#
DINV3#
J26
M26
V23
AC20
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
H23
M24
W24
AD23
G22
N25
Y25
AE24
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
A6
A5
C4
B3
C6
B4
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
STPCLK#
SMI#
D5
A3
H_STPCLK#
H_SMI#
YONAH-ULV
ADDR GROUP
DATA GROUP
C
<6> CLK_CPU_BCLK
<6> CLK_CPU_BCLK#
+1.05V_VCCP
R82
56_0402_5%~D
1
2
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
<10>
H_LOCK#
<10> H_RESET#
<10> H_RS#[0..2]
<10>
H_TRDY#
B
<24,40> ITP_DBRESET#
<10>
H_DBSY#
<23> H_DPSLP#
<23,50> H_DPRSTP#
<10> H_DPWR#
<39> CPU_PROCHOT#
<23> H_PWRGOOD
<10,23> H_CPUSLP#
<18> H_THERMDA
@ C18
2200P_0402_50V7K~D
1
CLK_CPU_BCLK
CLK_CPU_BCLK#
A22
A21
BCLK0
BCLK1
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRD Y#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
F3
F4
G3
G2
RS0#
RS1#
RS2#
TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
AD4
AD3
AD1
AC4
BPM0#
BPM1#
BPM2#
BPM3#
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
CPU_PROCHOT#
C20
E1
B5
E5
D24
AC2
AC1
D21
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
A24
A25
C7
THERMDA DIODE
THERMDC
THERMTRIP#
2
<18> H_THERMTRIP#
CONTROL
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_THERMDA
H_THERMDC
<18> H_THERMDC
HOST CLK
MISC
THERMAL
ITP_DBRESET#
2
150_0402_1%~D
1
R73
J2
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
R77
22.6_0402_1%~D
H_RESET# 1
2
ITP_TDO
1
R80
<6> CLK_CPU_ITP
<6> CLK_CPU_ITP#
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
2
22.6_0402_1%~D
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+1.05V_VCCP
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
1
R74
ITP_TDO
2
51_0402_5%~D
1
R75
H_RESET#
2
54.9_0402_1%~D
1
R76
ITP_TMS
2
39_0402_5%~D
1
R78
ITP_TDI
2
150_0402_1%~D
D
ITP_BPM#5
2
54.9_0402_1%~D
1
@ R575
1
R79
This shall place near CPU
ITP_TRST#
2
680_0402_5%~D
1
R81
ITP_TCK
2
27.4_0402_1%~D
@ MOLEX_52435-2891_28P~D
C
+1.05V_VCCP
1
2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
LEGACY CPU
+3.3V_SUS
+1.05V_VCCP
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
C17
0.1U_0402_16V4Z~D
<10> H_ADSTB#0
<10> H_ADSTB#1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
30
<10> H_REQ#[0..4]
1
H_D#[0..63] <10>
U2A
D
2
GND7
<10> H_A#[3..31]
3
1
2
C633
0.1U_0402_16V4Z~D
5
<10>
<10>
<10>
<10>
B
H_DSTBN#[0..3] <10>
H_DSTBP#[0..3] <10>
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
<23>
<23>
<23>
<23>
<23>
<23>
H_STPCLK#
H_SMI#
<23>
<23>
H_THERMTRIP#
1@ Yonah-ULV_1.06G SC_UFCBGA479~D
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
+1.05V_VCCP
A
A
TEST2
TEST1
1
R84
1
@ R579
2
51_0402_5%~D
2
1K_0402_5%~D
For Yonah B0
1
R83
1
R468
2 H_THERMTRIP#
56_0402_5%~D
2 CPU_PROCHOT#
75_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Yonah-ULV in mFCPGA479
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
7
of
59
5
4
3
+DC_IN discharge path
2
1
Smart Charger
+PWR_SRC
6
CCV
MAX8731_CCI
5
CCI
MAX8731_CCS
4
CCS
DLO
20
3
REF
PGND
CSIP
19
18
7
DAC
23 MAX8731_LX
12
CSIN
17
FBSA
15
1
FBSB
16
100_0402_5%~D
PR155
GND
MAX8731_TQFN28~D
PR129
0.01_2512_1%~D
4
1
3
2
PC108
0.1U_0805_50V7M~D
2
1
MAX8731_DLO
PD19
1SS355_SOD323~D
1
2
PC103
10U_1206_25V6M~D
2
1
5
6
7
8
PC117
0.1U_0402_10V7K~D
2
1MAX8731_DAC
GNDA_CHGR
LX
4
PL16
5.6U_HMU1356-5R6_8.8A_20%~D
2
1 +VCHGR_L
4
C
+VCHGR
PC110
10U_1206_25V6M~D
2
1
MAX8731_CCV
PR128
1_0603_5%~D
1
2
PC102
10U_1206_25V6M~D
2
1
24 MAX8731_DHI
PC107
1U_0603_10V6K~D
1
2
PC100
2200P_0402_50V7K~D
2
1
DHI
IINP
GNDA_CHGR
5
6
7
8
27 MAX8731_CSSN
CSSN
LDO
BATSEL
8
PC114
1U_0603_10V6K~D
2
1
PC113
0.01U_0402_25V7K~D
2
1
SDA
21 MAX8731_LDO
MAX8731_IINP
MAX8731_REF
PC112
0.01U_0402_25V7K~D
2
1
PC116
0.01U_0402_25V7K~D
2
1
PR132
10K_0402_1%~D
2
1
PR131
PC115
0.1U_0402_10V7K~D
2
1
PR130
4.7K_0402_5%~D
2
1
<40,46> PBAT_SMBDAT
1
SCL
14
GNDA_CHGR
B
VDD
10
25
PR158
1K_0603_1%~D
2
GNDA_CHGR
0_0603_5%~D
2
1 GNDA_CHGR
ACOK
11
9
<40,46> PBAT_SMBCLK
GND
13
BST
1
PC106
0.1U_0402_10V7K~D
2
1
ACIN
PC109
10U_1206_25V6M~D
2
1
+5V_ALW
2
26
3
2
1
MAX8731_ACOK
PC99
1U_0603_10V6K~D
1
2
MAX8731_VCC
PR125
0_0603_5%~D
1
2MAX8731_BSTB
VCC
3
2
1
<18,40> ACAV_IN
MAX8731_ACIN
DCIN
PQ23
SI4810BDY_SO8~D
PR126
0_0402_5%~D
1
2
PU6
22
+5V_ALW
Place these CAPs
close to FETs
GNDA_CHGR
PC111
220P_0603_50V8J~D
1
2
PC104
0.01U_0402_25V7K~D
2
1
PC98
1U_0805_25V4Z~D
2
1
GND
PR124
49.9K_0402_1%~D
2
1
CSSP
GNDA_CHGR
28 MAX8731_CSSP
GNDA_CHGR
PR122
PR123
15.8K_0402_1%~D
10K_0402_1%~D
ACAV_IN
2
1
1
2MAX8731_LDO
+DC_IN_SS
@
PR127
33_0603_1%~D
1
2
@
PD15
RB751V-40_SOD323~D
2
1
PR120
100K_0402_1%~D
2
1
PC135
0.01U_0603_25V7M~D
2
1
PR119
10K_0402_1%~D
2
1
PC105
0.1U_0603_25V7K~D
2
1
S
2
G
PC140
0.01U_0402_50V7K~D
2
1
PQ20
RHU002N06_SOT323
4
2
+VCHGR
PR118
470K_0402_5%~D
2
1
3
D
8
7
6
5
PC101
0.1U_0603_25V7M~D
2
1
1
1
2
3
PC122
0.1U_0603_25V7M~D
2
1
4
4
N657586
PC139
0.01U_0402_50V7K~D
2
1
S
D
2
G
3
1
PR117
10K_0402_1%~D
1
2
1
PR121
365K_0402_1%~D
1
2
ACAV_IN
C
D
3
PC97
10U_1206_25V6M~D
2
1
PQ21
RHU002N06_SOT323
1
2
3
PL15
FBM-L11-453215-900LMAT_1812~D
1
2
PC138
3300P_0402_50V7K~D
PQ22
IRF7821_SO8~D
1
2
8
7
6
5
+DC_IN_SS
PQ18
SI4835BDY_SO8~D
+CHRG_IN
PR116
0.01_2512_1%~D
PC121
2200P_0402_50V7K~D
2
1
PQ19
SI4835BDY_SO8~D
D
2
B
MAX8731_CSIP
@
MAX8731_CSIN
+VCHGR
Need double confirm
GNDA_CHGR
+5V_ALW
MAX8731_REF
PC130
100P_0402_50V8J
2
1
+5V_ALW
8
P
O
IN-
PU9B
LM393DR_SO8~D
Table1
65
TRIP CURRENT
(A)
3.17
90
4.43
976K
49.9K 13.3K 9.31K 38.3K
130
6.44
976K
33.2K 13.3K 15K
33.2K
150
7.44
649K
20K
66.1K
ADAPTER(W)
1
D
3
S
2
G
PR149
100K_0402_1%~D
1
2
PC131
0.01U_0402_25V8K
2
1
P
O
PQ26
RHU002N06_SOT323
IN+
PU9A
LM393DR_SO8~D
1
PC125
10P_0402_50V8J~D
2
1
4
3
G
IN-
8
PC128
100P_0402_50V8J
2
1
PC127
100P_0402_50V8J
2
1
PC129
0.01U_0402_25V8K
2
1
PR147
56.2K_0402_1%
2
1
2
Maximum Battery Charge current = 3.15A
when system off, S3, S4.
7
4
6
IN+
G
5
PR144
100K_0402_1%~D
2
1
PR145
301K_0402_1%~D
2
1
+3.3V_ALW
Need modify
PR148
27.4K_0402_1%
2
1
PR154
@ 154K_0402_1%
2
1
A
PR142
4.32M_0402_1%
1
2
PR146
0_0402_5%
1
2
PC126
0.01U_0402_25V8K
2
1
MAX8731_IINP
+5V_ALW
PR143
100K_0402_1%~D
2
1
GNDA_CHGR
Battery Type:
4cell: Charging Voltage=17.325V;Charging Current =1.6A
6cell: Charging Voltage=12.975V;Charging Current =3.15A
9cell:Charging Voltage=12.975V;Charging Current =3.15A
ADAPT_OC <39>
PR142 PR145 PR147 PR148 PR154
4.32M 301K
56.2K 27.4K NA
13K
10K
＠
A
DELL CONFIDENTIAL/PROPRIETARY
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
<39> ADAPT_TRIP_SEL
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Charger
Size
Document Number
Date:
Friday, May 12, 2006
Rev
0.4
LA-3071P
Sheet
1
7
of
10
5
4
3
2
1
Length match within 25 mils
+VCC_CORE
U2B
VCCSENSE
VSSSENSE
VCCSENSE
VSSSENSE
B26
VCCA
K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
H_PSI#
AE6
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
+1.5V_RUN
+1.05V_VCCP
D
1
R88
VCCSENSE
2
100_0402_1%~D
1
R89
VSSSENSE
2
100_0402_1%~D
R87
1K_0402_1%~D
1
2
V_CPU_GTLREF
R_B
2
R90
2K_0402_1%~D
Layout close CPU PIN AD26
0.5 inch (max)
1
2
C20
10U_0805_6.3V6M~D
+VCC_CORE
R_A
C19
0.01U_0402_16V7K~D
1
+1.05V_VCCP
Close to U2.B26
Layout close CPU
VCCSENSE/VSSSENSE
trace width 18mil,
space 7mil, for
other signal 15mil
1
2
<50>
H_PSI#
<50>
<50>
<50>
<50>
<50>
<50>
<50>
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD26
V_CPU_GTLREF
<6,10> CPU_MCH_BSEL0
<6,10> CPU_MCH_BSEL1
<6,10> CPU_MCH_BSEL2
C
COMP0
COMP1
COMP2
COMP3
R91
27.4_0402_1%~D
1
R92
54.9_0402_1%~D
1
R93
27.4_0402_1%~D
1
R94
54.9_0402_1%~D
1
2
2
2
2
+VCC_CORE
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
133
0
0
1
166
0
1
1
YONAH-ULV
GTLREF
B22
B23
C21
BSEL0
BSEL1
BSEL2
R26
U26
U1
V1
COMP0
COMP1
COMP2
COMP3
E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25
B
U2C
AF7
AE7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
POWER, GROUNG, RESERVED SIGNALS AND NC
<50> VCCSENSE
<50> VSSSENSE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7
1@ Yonah-ULV_1.06G SC_UFCBGA479~D
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
YONAH-ULV
POWER, GROUND
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
D
C
B
1@ Yonah-ULV_1.06G SC_UFCBGA479~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Yonah-ULV in mFCBGA479
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
8
of
59
5
4
3
2
1
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
1
1
C21
22U_0805_6.3V6M~D
2
2
1
4@ C22
10U_0805_4VAM~D
2
1
C23
22U_0805_6.3V6M~D
2
1
@ C24
10U_0805_4VAM~D
2
1
4@ C25
10U_0805_4VAM~D
2
1
C26
22U_0805_6.3V6M~D
2
1
4@ C27
10U_0805_4VAM~D
2
1
C28
22U_0805_6.3V6M~D
2
1
C29
22U_0805_6.3V6M~D
2
4@ C30
10U_0805_4VAM~D
+VCC_CORE
D
Place these inside
socket cavity on L8
(Sorth side
Secondary)
1
1
C31
22U_0805_6.3V6M~D
2
2
1
@ C32
10U_0805_4VAM~D
2
1
4@ C33
10U_0805_4VAM~D
2
1
C34
22U_0805_6.3V6M~D
2
1
4@ C35
10U_0805_4VAM~D
2
1
C36
22U_0805_6.3V6M~D
2
1
4@ C37
10U_0805_4VAM~D
2
1
4@ C38
10U_0805_4VAM~D
2
D
1
4@ C39
10U_0805_4VAM~D
2
4@ C40
10U_0805_4VAM~D
+VCC_CORE
1
1
4@ C693
10U_0805_4VAM~D
2
2
1
4@ C694
10U_0805_4VAM~D
2
1
@ C695
10U_0805_4VAM~D
2
1
@ C696
10U_0805_4VAM~D
2
4@ C697
10U_0805_4VAM~D
1
1
2
4@ C698
10U_0805_4VAM~D
2
1
4@ C699
10U_0805_4VAM~D
2
1
4@ C700
10U_0805_4VAM~D
2
1
@ C701
10U_0805_4VAM~D
2
@ C702
10U_0805_4VAM~D
+VCC_CORE
1
Note:
C21,C23,C26,C28,C29,C31,C34,C36
use 22U on Single Core CPU and
use 10U on Dual Core CPU.
1
4@ C703
10U_0805_4VAM~D
2
2
4@ C704
10U_0805_4VAM~D
High Frequence Decoupling
Temp. characteristics: X5R
Operating range: -55~+85degree
C
C
BOM introduction
BOM
1@
2@
3@
4@
5@
6@
8@
Near VCORE regulator.
+
2
1
+
2
7mOhm 7mOhm 6mOhm
PS CAP PS CAP PS CAP
B
1
+
2
1
+
2
6/7mOhm 6/7mOhm
PS CAP PS CAP
@ C706
330U_D_2.5VM_R6M~D
2
1
C44
330U_D_2.5VM_R6M~D
+
C41
330U_D_2.5VM_R6M~D
1
@ C705
330U_D_2.5VM_R6M~D
South Side Secondary
4@ C43
220U_D_2VM_R7M~D
4@ C42
220U_D_2VM_R7M~D
+VCC_CORE
1
North Side Secondary
+
Note:
C42,C43,C41,C44
will change to
220U 2.5V 6M on
Dual Core CPU for
CPU transition
noise
CPU speed
1.06G 5.5W
1.2G 5.5W
1.06G 7.5W
CPU type
Signal core
W/O
1. 220uF poly cap 2pcs
2. 22uF MLCC cap 8pcs
SA00001CF1L
W/O
W
1.2G
1.06G 5.5W
Signal core
SA000017Z2L
SA00000Z33L
W
SA000017Z2L
Part Number
SA00001CF1L
1.
2.
1.
2.
220uF poly cap 4pcs
10uF MLCC cap 26pcs
220uF poly cap 2pcs
22uF MLCC cap 8pcs
6@ Yonah-ULV_1.2G SC_UFCBGA479~D
Description
Part Number
S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA
4@ Yonah-ULV_1.2G DC_UFCBGA479~D
6mOhm
PS CAP
Use of decoupling
Dual core
Part Number
ESR <= 1.5m ohm
Capacitor = 1320uF
TAA
1.2G 9.5W
2@ Yonah-ULV_1.2G SC_UFCBGA479~D
2
P/N
SA00000Z33L
SA000017Z2L
SA00000Z30L
SA000017Z2L
Description
S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA
8@ Yonah-ULV_1.06G SC_UFCBGA479~D
Description
Part Number
S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P
SA00000Z33L
Description
B
S IC LE80538UE0042M SL8W7 1.06G C0 FCBGA
5@ Yonah-ULV_1.2G DC_UFCBGA479~D
Part Number
SA00001CF1L
Description
S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P
@ C45
330U_D2E_2.5VM_R9~D
+1.05V_VCCP
1
1
+
2
2
1
C46
0.1U_0402_10V7K~D
2
1
C47
0.1U_0402_10V7K~D
2
1
C48
0.1U_0402_16V4Z~D
2
1
C49
0.1U_0402_16V4Z~D
2
1
C50
0.1U_0402_10V7K~D
2
C51
0.1U_0402_10V7K~D
Place these inside
socket cavity on L8
(North side
Secondary)
CRB was 270uF
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU Bypass
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
9
of
59
5
4
3
2
1
U3B
H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
V28
V31
V29
V32
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
<16,17> DDR_CS0#
T14 PAD~D
<15> DDR_CS2_DIMMA#
<15> DDR_CS3_DIMMA#
0.1U_0402_10V6K~D
C53
H_SWNG0
1
2
<16,17> M_ODT0
T15 PAD~D
<15>
M_ODT2
<15>
M_ODT3
+1.8V_SUS
1
R99 1
R101
2
2
80.6_0402_1%~D
80.6_0402_1%~D
V_DDR_MCH_REF
SM_CK_0
SM_CK_1
AJ1
AM30
SM_CK_2
SM_CK_3
M_CLK_DDR#0
M_CLK_DDR#1
AG33
AF1
SM_CK#_0
SM_CK#_1
M_CLK_DDR#2
M_CLK_DDR#3
AK1
AN30
SM_CK#_2
SM_CK#_3
DDR_CKE0
DDR_CKE1
DDR_CKE2_DIMMA
DDR_CKE3_DIMMA
AN21
AN22
AF26
AF25
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
DDR_CS0#
DDR_CS1#
DDR_CS2_DIMMA#
DDR_CS3_DIMMA#
AG14
AF12
AK14
AH12
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
M_OCDOCMP0
M_OCDOCMP1
AJ21
AF11
SM_OCDCOMP_0
SM_OCDCOMP_1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
AE12
AF14
AJ14
AJ12
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SMRCOMPN
SMRCOMPP
AN12
AN14
AA33
AE1
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
CFG/RSVD
AF33
AG1
M_CLK_DDR2
M_CLK_DDR3
PM
<15> M_CLK_DDR#2
<15> M_CLK_DDR#3
M_CLK_DDR0
M_CLK_DDR1
CLK
<15> M_CLK_DDR2
<15> M_CLK_DDR3
<16,17> M_CLK_DDR#0
<16,17> M_CLK_DDR#1
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
C18
E18
G20
G18
J20
J18
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
K32
K31
C17
F18
A3
DMI
Y29
Y32
Y28
Y31
DDR2 MUXING
<16,17> M_CLK_DDR0
<16,17> M_CLK_DDR1
0.1U_0402_10V6K~D
C52
1
221_0402_1%~D
R95
2
1
100_0402_1%~D
R96
2
1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
E31
G21
F26
H26
J15
AB29
W27
D_REFCLKN
D_REFCLKP
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
A27
A26
J33
H33
J22
H_DSTBN#[0..3] <7>
H_HIT#
<7>
H_HITM# <7>
H_LOCK# <7>
H_REQ#[0..4] <7>
CFG5
H_VREF
1
2
H_RS#[0..2] <7>
H_CPUSLP# <7,23>
H_TRDY# <7>
PLTRST#
<20,22,24,29,36>
Low
= DMI x 2
*
High = DMI x 4
High = Reverse Lane
B
Calistoga-GMS not have CFG4,CFG[7..18],CFG[20]
Need to double check
+3.3V_RUN
CFG19
@ R112
40.2_0402_1%~D
2
1
@ R111
40.2_0402_1%~D
2
1
C55
0.1U_0402_10V6K~D
2
R100
MCH_DREFCLK# <6>
MCH_DREFCLK <6>
DREF_SSCLK# <6>
DREF_SSCLK <6>
CLK_3GPLLREQ# <6>
Layout Note:
Route as short
as possible
V_DDR_MCH_REF
@
PLTRST_R# 1
100_0402_1%~D
C
Low = Normal
CFG19
(DMI Lane Reversal) Operation (Default):
Lane number in Order
<13>
A
ICH_PWRGD
MCH_ICH_SYNC# <22>
PM_BMBUSY# <24>
PM_EXTTS#0 <15>
PM_EXTTS#1 <24>
THERMTRIP_MCH# <18>
ICH_PWRGD <24,43>
Strap Pin Table
M_OCDOCMP0
M_OCDOCMP1
Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20
PM_EXTTS#0
PM_EXTTS#1
D
Calistoga-GMS_FCBGA998~D
Calistoga-GMS_FCBGA998~D
<15,16,17,49> V_DDR_MCH_REF
CPU_MCH_BSEL0
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2
CPU_MCH_BSEL2 <6,8>
CFG3
PAD~D
T2
CFG5
CFG6
PAD~D
T3
+1.05V_VCCP
H_DSTBP#[0..3] <7>
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
<24>
<24>
<24>
<24>
<16,17> DDR_CKE0
T13 PAD~D
<15> DDR_CKE2_DIMMA
<15> DDR_CKE3_DIMMA
221_0402_1%~D
R97
2
1
CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>
H_DBSY# <7>
H_DEFER# <7>
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_DPWR# <7>
H_DRDY# <7>
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
0.1U_0402_10V6K~D
H_DPWR#
H_DRD Y#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
2
C54
H_DBSY#
H_DEFER#
H_BNR# <7>
H_BPRI# <7>
H_BR0#
<7>
H_RESET# <7>
2
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
1
100_0402_1%~D
R98
HCLKN
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
1
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
H_VREF
<24>
<24>
<24>
<24>
H_SWNG1
+1.05V_VCCP
2
A10
A6
C15
J1
K1
H1
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
F10
C12
H16
E2
B9
C7
G8
B10
E1
+1.05V_VCCP
100_0402_1%~D
R102
H_XRCOMP
H_XSCOMP
H_SWNG0
H_YRCOMP
H_YSCOMP
H_SWNG1
24.9_0402_1%~D
R107
24.9_0402_1%~D
R106
2
1
2
1
B
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
1
1
2
54.9_0402_1%~D
R104
2
1
+1.05V_VCCP
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
200_0402_1%~D
C
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
R105
D
54.9_0402_1%~D
R103
H_A#[3..31] <7>
U3A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
2
H_D#[0..63]
HOST
<7>
PM_EXTTS#0
2
R108
1
10K_0402_5%~D
PM_EXTTS#1
2
@ R109
1
10K_0402_5%~D
1
@R110
2
1K_0402_5%~D
CPU_MCH_BSEL0 1
@R113
2
1K_0402_5%~D
THERMTRIP_MCH# 1
R114
CFG5
1
R115
2
75_0402_5%~D
2
2.2K_0402_5%~D
+1.05V_VCCP
1
Stuff R111 & R112 for A1 Calistoga
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Calistoga(1 of 5)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
10
of
59
5
4
3
2
1
D
D
<16,17> DDR_A_BS0
<16,17> DDR_A_BS1
<15,16> DDR_A_DM[0..7]
<15,16> DDR_A_DQS[0..7]
<15,16> DDR_A_DQS#[0..7]
DDR_A_BS0
DDR_A_BS1
AK12
AH11
AG17
SA_BS_0
SA_BS_1
SA_BS_2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AB30
AL31
AF30
AK26
AL9
AG7
AK5
AH3
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AC28
AJ30
AK33
AL25
AN9
AH8
AM2
AE3
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
DDR_A_DQS#0 AC29
DDR_A_DQS#1 AK30
DDR_A_DQS#2 AJ33
DDR_A_DQS#3 AM25
DDR_A_DQS#4 AN8
DDR_A_DQS#5 AJ8
DDR_A_DQS#6 AM3
DDR_A_DQS#7 AE2
C
<16,17> DDR_A_MA[0..13]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
<16,17> DDR_A_CAS#
<16,17> DDR_A_RAS#
T4 PAD~D
T5 PAD~D
<16,17> DDR_A_WE#
<15> DDR_B_BS0
<15> DDR_B_BS1
<15> DDR_B_BS2
<15> DDR_B_MA[0..13]
B
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
AJ17
AK18
AN28
AM28
AH17
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AH21
AJ20
AE27
SB_BS_0
SB_BS_1
SB_BS_2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
DDR2 SYSTEM MEMORY
U3C
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SB_CAS#
SB_RAS#
SB_WE#
AG19
AG21
AG20
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
DDR_A_D[0..63] <15,16>
C
B
DDR_B_CAS# <15>
DDR_B_RAS# <15>
DDR_B_WE# <15>
Calistoga-GMS_FCBGA998~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Calistogo(2 of 5)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
11
of
59
5
4
3
2
1
D
D
+1.5VRUN_PCIE
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LCD_ACLKLCD_ACLK+
D30
C30
A30
A29
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LCD_A0LCD_A1LCD_A2-
G31
F32
D31
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LCD_A0+
LCD_A1+
LCD_A2+
H31
G32
C31
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
F33
D33
F30
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
E33
D32
F29
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
2
2
2
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
N28
M32
P33
R32
DVO_RED_C
DVO_GREEN_C
DVO_BLUE_C
DVO_CLK_C
C60
C61
C62
C63
1
1
1
1
2
2
2
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
A21
C20
E20
G23
B21
C21
D21
TV_DCONSEL0
TV_DCONSEL1
G26
J26
SDVOB_RED- <20>
SDVOB_GREEN- <20>
SDVOB_BLUE- <20>
SDVOB_CLK- <20>
R120
150_0402_1%~D
2
1
1
2
<38>
<38>
<38>
Close to U3.G23
B
Calistoga-GMS_FCBGA998~D
1
D
G_CLK_DDC2
S
LCD_A1-
1
2
2
R130
2.2K_0402_5%~D
+3.3V_RUN
LCD_ACLKC711
8.2P_0402_50V8J~D
LCD_ACLK+
C
SDVOB_RED+ <20>
SDVOB_GREEN+ <20>
SDVOB_BLUE+ <20>
SDVOB_CLK+ <20>
TV_CVBS
TV_Y
TV_C
TVIREF
R119
150_0402_1%~D
2
1
LCD_A0+
LCD_A1+
LCD_A2+
1
1
1
1
1
<19>
<19>
<19>
C56
C57
C58
C59
2
VGA_RED
1
150_0402_1%~D
VGA_GRN
1
150_0402_1%~D
VGA_BLU
1
150_0402_1%~D
LCD_A0LCD_A1LCD_A2-
DVO_RED#_C
DVO_GREEN#_C
DVO_BLUE#_C
DVO_CLK#_C
R122
4.99K_0402_1%~D
2
R126
2
R127
2
R128
<19>
<19>
<19>
P28
N32
P32
T32
R129
2.2K_0402_5%~D
2
1
B
LCD_DDCCLK
2
2.2K_0402_5%~D
LCD_DDCDATA
2
2.2K_0402_5%~D
LCTLA_CLK
2
10K_0402_5%~D
LCTLB_DATA
2
10K_0402_5%~D
<20>
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
TV
CRT_IREF
+3.3V_RUN
1
R580
1
R581
1
R123
1
R124
SDVOB_INT+ <20>
BIA_PWM
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDATA
<19> LCD_DDCCLK
<19> LCD_DDCDATA
<19>
ENVDD
L_IBG
2
1
R118
1.5K_0402_1%~D
<19> LCD_ACLK<19> LCD_ACLK+
M30
P30
T30
MISC
<19,40> BIA_PWM
<19> PANEL_BKEN
SDVOB_INT-
SDVO
1
255_0402_1%~D
VGA
2
R117
N30
R30
T29
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
<21,38> VGA_RED
C
R28
M28
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
<21,38> VGA_GRN
R116
24.9_0402_1%~D
1
2
EXP_A_COMPI
EXP_A_ICOMPO
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
G_CLK_DDC2
G_DAT_DDC2
<21> VGA_VSYNC
<21> VGA_HSYNC
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
<21,38> VGA_BLU
Close to U3.H25
H27
J27
Y26
AA26
LVDS
<20> SDVO_CTRLDATA
<20> SDVO_CTRLCLK
<6> CLK_MCH_3GPLL#
<6> CLK_MCH_3GPLL
+PEGCOMP
R121
150_0402_1%~D
U3F
SDVO_CTRLDATA
SDVO_CTRLCLK
3
1
1
2
G
C712
3.3P_0402_50VJ~D
2
LCD_A1+
CLK_DDC2
CLK_DDC2
<21,38>
Q3
2N7002W-7-F_SOT323~D
G
2
+3.3V_RUN
LCD_A01
3
1
S
D
G_DAT_DDC2
C713
3.3P_0402_50VJ~D
2
LCD_A0+
DAT_DDC2
DAT_DDC2 <21,38>
Q4
2N7002W-7-F_SOT323~D
LCD_A21
C714
3.3P_0402_50VJ~D
2
LCD_A2+
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Calistoga(3 of 5)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
12
of
59
5
4
3
2
1
+1.5V_RUN
1
2
C66
0.1U_0402_10V6K~D
1
2
C68
10U_0805_6.3V6M~D
2
C65
0.1U_0402_10V6K~D
1
C67
10U_0805_6.3V6M~D
C64
0.1U_0402_10V6K~D
D
1
2
1
2
C70
220U_D2_4M_R45~D
C
1
+
2
B
C71
220U_D2_4M_R45~D
CRB 270uF
+1.05V_VCCP
T25
R25
P25
N25
M25
P24
N24
M24
Y22
W22
V22
U22
T22
R22
P22
N22
M22
Y21
W21
V21
U21
T21
R21
P21
N21
M21
Y20
W20
V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
T10
R10
P10
N10
L10
D1
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
1
+
2
M10
A18
AB10
AA10
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
CFG_19
K28
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
Calistoga-GMS_FCBGA998~D
A
CFG19
CFG19
<10>
AH33
Y33
V33
R33
G33
AK32
AG32
AE32
AC32
AA32
U32
H32
E32
C32
AM31
AJ31
AA31
U31
T31
R31
P31
N31
M31
J31
F31
AL30
AG30
AE30
AC30
AA30
Y30
V30
U30
G30
E30
B30
AA29
U29
R29
P29
N29
M29
H29
E29
B29
AK28
AH28
AE28
AA28
U28
T28
J28
D28
AM27
AF27
AB27
AA27
Y27
U27
T27
R27
P27
N27
M27
G27
E27
C27
B27
AL26
AH26
W26
U26
AN25
AK25
AG25
AE25
J25
G25
A25
H23
F23
B23
AM22
AJ22
AF22
G22
E22
J21
H21
F21
AM20
AK20
AH20
AF20
D20
W19
R19
AM18
AH18
AF18
U18
H18
D18
AK17
V17
T17
F17
B17
AH16
U16
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
U3G
VSS
U3E
U3H
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
W33
AM33
AL33
C33
B33
AN32
A32
AN31
W28
V27
W29
J24
H24
W32
G24
F24
E24
D24
K33
A31
E21
C23
AN19
AM19
AL19
AK19
AJ19
AH19
AN3
Y9
J19
H19
G19
F19
E19
D19
C19
B19
A19
Y8
G16
F16
E16
D16
C16
B16
AN2
A16
Y7
AM4
AF4
AD4
AL4
AK4
W31
AJ4
AH4
AG4
AE4
AM1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
D
NC
+1.05V_VCCP
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
C
Calistoga-GMS_FCBGA998~D
B
A
DELL CONFIDENTIAL/PROPRIETARY
Calistoga-GMS_FCBGA998~D
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Calistoga(4 of 5)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
13
of
59
5
4
3
2
1
+1.05V_VCCP
3
D2
MMBD4148W-7-F_SOT323~D
CRT DAC Voltge Follower Circuit - 700mV
5
C74
10U_0805_6.3V6M~D
2
1
R131
0_0603_5%~D
2
2
3
0_0805_5%~D
1
C83
4.7U_0603_6.3V6M~D
2
@ C90
1
45mA Max.
1
2
C
2
1
2
1
C100
22U_0805_6.3V6M~D
2
+2.5V_RUN
1
C104
0.1U_0402_10V6K~D
+1.5VRUN_PCIE
2
1
2
1
2
+2.5V_RUN
L9
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
1
2
CRTDAC: Route FB
within 3" of Calistoga
1
+
2
1
2
C114
10U_0805_6.3V6M~D
+2.5V_RUN
R582 +1.5V_RUN
0_0805_5%~D
+VCC3G_R 1
2
1
L8
BLM21PG600SN1D_0805~D
60ohm,3000mA,0.025ohm
1
1
1
2
2
C130
10U_0805_6.3V6M~D
2
1
1
2
2
B
C109
22U_0805_6.3V6M~D
40mA Max.
L10
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
2
1
+1.5V_RUN
+1.5V_RUN
2+3GPLL_R 2
1+3GPLL_L 1
2
L11
BLM18PG181SN1_0603~D
R132
R583
0.5_0805_1%~D 180ohm,1500mA,0.09ohm 0_0805_5%~D
1
2
2
+2.5V_RUN
1
2
1
+1.5V_RUN
L7
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
+
+1.5VRUN_DPLLB
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
+1.5VRUN_3GPLL
45mA Max.
+2.5V_RUN
1
1
2
2
1
2
1
1
2
2
1
+
2
C121
470U_D2_2.5VM~D
2
+1.5VRUN_MPLL
2
1
C122
0.1U_0402_10V6K~D
Route +2.5VRUN from GMCH pinN33 to
decoupling cap (C66)<200mil to the edge.
1
+
C101
470U_D2_2.5VM~D
2
2
1
+1.5V_RUN
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
C102
0.1U_0402_10V6K~D
1
L6
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
2
1
+1.5V_RUN
C108
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
1
40mA Max.
+1.5VRUN_DPLLA
L5
C99
1
+1.05V_VCCP
TV DAC Voltge Follower Circuit - 700mV
3
C91
0.1U_0402_10V6K~D
Close to U3.F20
+1.5VRUN_HPLL
1
+3.3V_TV
1
2
R133
10_0402_5%~D
2
VSSA_TVBG
+2.5V_RUN
P1
L1
G1
U1
Y1
1
1
C88
0_0805_5%~D
2
0.1U_0402_10V6K~D
C87
C86
0.022U_0402_16V7K~D
C85
0.1U_0402_10V6K~D
C84
0.022U_0402_16V7K~D
C82
4.7U_0603_6.3V6M~D
C81
4.7U_0603_6.3V6M~D
2
+3VRUN_ATV
2
C92
0.1U_0402_10V6K~D
C72
0_0805_5%~D
C77
0_0805_5%~D
1
C80
0.1U_0402_10V6K~D
C76
0.1U_0402_10V6K~D
C75
10U_0805_6.3V6M~D
C79
10U_0805_6.3V6M~D
C78
0.1U_0402_10V6K~D
2
3
+3VRUN_TVDACC
close pin C29/D29
close pin B31
A
DELL CONFIDENTIAL/PROPRIETARY
D1
MMBD4148W-7-F_SOT323~D
4
D
C65, C73, C83 replace by 0
ohm 0805 resistor
Follow 945GMS desgin
guild to modify
+2.5V_CRTDAC
+3.3V_RUN
1
2
2
2
+1.5VRUN_3GPLL
+2.5V_RUN
+1.05V_VCCP
3
2
1
1
1
2
2
+2.5V_CRT 1
2
R134
10_0402_5%~D
2
1
1
@ C105
330U_D2E_2.5VM_R9~D
+2.5V_RUN
A
1
1
+1.5VRUN_MPLL
+1.5VRUN_HPLL
+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5V_RUN
2
+2.5V_RUN
1
U3_AH1
+1.5V_RUN
2
2
+3VRUN_ATVBG
U3_AN4
1
2
C94
1U_0402_6.3V4Z~D
C95
1U_0402_6.3V4Z~D
U3_AN18
+1.5VRUN_QTVDAC
+1.5V_RUN
L4
BLM18PG181SN1_0603~D
2
1
180ohm,1500mA,0.09ohm
C127
0.1U_0402_10V6K~D
2
2
180ohm,1500mA,0.09ohm
1
+1.5V_RUN
Calistoga-GMS_FCBGA998~D
1
1
+1.8V_SUS
C126
4.7U_0603_6.3V6M~D
1
C120
0.47U_0402_16V4Z~D
C118
0.47U_0402_16V4Z~D
U3_AA1
U3_F1
VTT41
VTT42
VTT43
VTT44
VTT45
3
1
C125
0.01U_0402_16V7K~D
2
2
L3
BLM18PG181SN1_0603~D
2
1
+3.3V_RUN
2
+3VRUN_TVDACB
2
C113
10U_0805_6.3V6M~D
2
1
2
2
2
C110
220U_D2_4M_R45~D
1
2
1
1
1
C124
0.1U_0402_10V6K~D
2
1
1
1
C128
0.1U_0402_10V6K~D
C123
220U_D2_4M_R45~D
C111
4.7U_0603_6.3V6M~D
B
+
C112
4.7U_0603_6.3V6M~D
CRB 270uF
1
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
U3_AB33
U3_AM32
+1.5V_RUN
C115
0.1U_0402_10V6K~D
U3_A7
1
2
C632
0.47U_0402_16V4Z~D
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1
+3.3V_RUN
C117
0.1U_0402_10V6K~D
U3_A14
+1.5V_RUN
+1.5VRUN_QTVDAC
C116
0.022U_0402_16V7K~D
+1.05V_VCCP
1
2
C631
0.47U_0402_16V4Z~D
Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to the GND plane.
+3VRUN_ATVBG
+3V_TVDAC
1
+3VRUN_TVDACC
VSSA_TVBG
C97
1U_0402_6.3V4Z~D
C
Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to the GND plane.
+3VRUN_TVDACB
C129
0.1U_0402_10V6K~D
2
+3VRUN_TVDACA
+3VRUN_TVDACA
C93
1U_0402_6.3V4Z~D
1
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
C96
1U_0402_6.3V4Z~D
0.1U_0402_10V6K~D
C89
+1.5V_RUN
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS
C119
0.1U_0402_10V6K~D
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
J14
J10
H10
AE9
AD9
U9
AD8
AD7
AD6
POWER
D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
C73
0.1U_0402_10V6K~D
U3D
T26
R26
P26
N26
M26
V19
U19
T19
W18
V18
T18
R18
W17
U17
R17
W16
V16
T16
R16
V15
U15
T15
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Calistoga(5 of 5)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
14
of
59
3
2
1
+1.8V_SUS
+1.8V_SUS
ON Bottom SIDE
<11,16> DDR_A_DQS#[0..7]
DDR_A_D6
DDR_A_D5
Layout Note:
Place near JDIM1
<11,16> DDR_A_DQS[0..7]
<11> DDR_B_MA[0..13]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D7
DDR_A_D3
D
DDR_A_D9
DDR_A_D13
+1.8V_SUS
DDR_A_DQS#1
DDR_A_DQS1
2
1
DDR_A_D15
DDR_A_D14
C137
C136
1
2.2U_0603_6.3V6K~D
2
2.2U_0603_6.3V6K~D
2
1
C135
C134
1
2.2U_0603_6.3V6K~D
C133
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D17
DDR_A_D21
2
1
DDR_A_D19
DDR_A_D23
C141
0.1U_0402_16V4Z~D
1
C140
C139
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C138
0.1U_0402_16V4Z~D
2
1
DDR_A_D28
DDR_A_D24
2
DDR_A_DM3
DDR_A_D26
DDR_A_D27
C
<10> DDR_CKE2_DIMMA
<11> DDR_B_BS2
DDR_CKE2_DIMMA
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<11> DDR_B_BS0
<11> DDR_B_WE#
<11> DDR_B_CAS#
<10> DDR_CS3_DIMMA#
+0.9V_DDR_VTT
<10>
M_ODT3
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMA#
M_ODT3
DDR_A_D32
DDR_A_D36
2
1
2
DDR_A_DQS#4
DDR_A_DQS4
1
DDR_A_D38
DDR_A_D35
2
C154
C153
C152
C151
C150
C149
C148
C147
C146
C145
C144
C143
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C142
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B
2
1
DDR_A_D42
DDR_A_D40
DDR_A_DM5
DDR_A_D44
DDR_A_D43
DDR_A_D48
DDR_A_D49
+0.9V_DDR_VTT
RN1
DDR_B_MA3
1
DDR_B_MA1
2
56_0404_4P2R_5%~D
RN4
4
3
RN6
4
3
4
3
4
3
4
3
DDR_A_DM7
DDR_A_D62
DDR_A_D63
1 DDR_B_MA4
2 DDR_B_MA2
56_0404_4P2R_5%~D
CLK_SDATA
<6,17> CLK_SDATA
CLK_SCLK
<6,17> CLK_SCLK
+3.3V_RUN
4
3
RN11
1 M_ODT2
2 DDR_B_MA13
56_0404_4P2R_5%~D
4
3
RN13
RN12
DDR_B_BS2
2
DDR_CKE2_DIMMA 1
56_0404_4P2R_5%~D
5
3
4
4
3
1 DDR_CKE3_DIMMA
2 DDR_B_MA11
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
4
1
2
1
2
C156
2.2U_0603_6.3V6K~D
1 DDR_B_MA0
2 DDR_B_BS1
56_0404_4P2R_5%~D
C155
4
3
0.1U_0402_16V4Z~D
A
DDR_A_D60
DDR_A_D61
1 DDR_B_MA8
2 DDR_B_MA5
56_0404_4P2R_5%~D
RN10
RN9
DDR_CS3_DIMMA# 1
M_ODT3
2
56_0404_4P2R_5%~D
DDR_A_D54
DDR_A_D55
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
RN8
RN7
DDR_B_WE#
1
DDR_B_CAS#
2
56_0404_4P2R_5%~D
1 DDR_B_MA7
2 DDR_B_MA6
56_0404_4P2R_5%~D
4
3
RN5
DDR_B_RAS#
1
DDR_CS2_DIMMA# 2
56_0404_4P2R_5%~D
1 DDR_B_MA12
2 DDR_B_MA9
56_0404_4P2R_5%~D
4
3
RN3
DDR_B_MA10
1
DDR_B_BS0
2
56_0404_4P2R_5%~D
DDR_A_DQS#6
DDR_A_DQS6
RN2
4
3
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
V_DDR_MCH_REF <10,16,17,49>
DDR_A_D0
DDR_A_D4
1
DDR_A_DM0
2
DDR_A_D1
DDR_A_D2
1
2
@ R597
100K_0402_5%~D
D
DDR_A_D12
DDR_A_D8
DDR_A_DM1
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_A_D10
DDR_A_D11
2
DDR_A_DQS#2
DDR_A_DQS2
1
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C132
0.1U_0402_16V4Z~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<11,16> DDR_A_DM[0..7]
1
V_DDR_MCH_REF
JDIMB
C131
2.2U_0603_6.3V6K~D
<11,16> DDR_A_D[0..63]
2
4
1
5
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_A_D16
DDR_A_D20
2
R565
DDR_A_DM2
1 PM_EXTTS#0
0_0402_5%~D
PM_EXTTS#0
<10>
DDR_A_D22
DDR_A_D18
DDR_A_D25
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE3_DIMMA
C
DDR_CKE3_DIMMA <10>
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMA#
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMA# <10>
M_ODT2
DDR_B_MA13
M_ODT2
<10>
DDR_A_D33
DDR_A_D37
DDR_A_DM4
DDR_A_D39
DDR_A_D34
DDR_A_D45
DDR_A_D41
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
DDR_A_DM6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D59
DDR_A_D58
R135 1
R136 1
2 10K_0402_5%~D
2 10K_0402_5%~D
+3.3V_RUN
TYCO_1775803-2~D
A
DIMMA
STANDARD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
DDRII-SODIMM SLOT1
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
15
of
59
5
4
3
2
1
<11,15> DDR_A_DQS#[0..7]
<11,15> DDR_A_D[0..63]
RN14
DDR_A_D5
DDR_A_D6
4 DDR_SDQ5
3 DDR_SDQ6
10_0404_4P2R_5%~D
1
2
DDR_A_DQS#41
DDR_A_DQS4 2
RN20
D
1
2
4 DDR_SDQ4
3 DDR_SDQ0
10_0404_4P2R_5%~D
DDR_A_D36
DDR_A_D32
1
2
4 DDR_SDQ3
3 DDR_SDQ7
10_0404_4P2R_5%~D
DDR_A_D37
DDR_A_D33
1
2
4 DDR_SDQ8
3 DDR_SDQ12
10_0404_4P2R_5%~D
DDR_A_D34
DDR_A_D39
RN18
DDR_A_D40
DDR_A_D42
1
2
DDR_A_D20
DDR_A_D16
1
2
DDR_A_D18
DDR_A_D22
1
2
DDR_A_D21
DDR_A_D17
1
2
DDR_A_D23
DDR_A_D19
1
2
DDR_A_D29
DDR_A_D25
1
2
DDR_A_D27
DDR_A_D26
1
2
4 DDR_SDQ34
3 DDR_SDQ39
10_0404_4P2R_5%~D
4 DDR_SDQ40
3 DDR_SDQ42
10_0404_4P2R_5%~D
1
2
DDR_A_D47
DDR_A_D46
4 DDR_SDQ47
3 DDR_SDQ46
10_0404_4P2R_5%~D
1
2
RN32
DDR_A_D11
DDR_A_D10
<10,15,17,49> V_DDR_MCH_REF
1
1
2
2
1
2
1
2
1
2
RN30
4 DDR_SDQ13
3 DDR_SDQ9
10_0404_4P2R_5%~D
1
2
4 DDR_SDQ37
3 DDR_SDQ33
10_0404_4P2R_5%~D
RN33
RN29
DDR_A_D13
DDR_A_D9
<17> DDR_SDM[0..7]
RN24
4 DDR_SDQ14
3 DDR_SDQ15
10_0404_4P2R_5%~D
1
2
4 DDR_SDQ36
3 DDR_SDQ32
10_0404_4P2R_5%~D
1
2
RN26
DDR_A_D14
DDR_A_D15
<17> DDR_SDQS[0..7]
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V_DDR_MCH_REF
E2
VREF
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
RN21
RN23
1
2
<17> DDR_SDQS#[0..7]
<17> DDR_SDQ[0..63]
RN19
RN16
DDR_A_D8
DDR_A_D12
4 DDR_SDQ35
3 DDR_SDQ38
10_0404_4P2R_5%~D
C629
0.1U_0402_16V4Z~D
DDR_A_D3
DDR_A_D7
1
2
DDR_SDQS0
DDR_SDQS#0
DDR_SDM0
DDR_SDQ0
DDR_SDQ1
DDR_SDQ4
DDR_SDQ2
DDR_SDQ3
DDR_SDQ5
DDR_SDQ7
DDR_SDQ6
C160
0.1U_0402_16V4Z~D
1
2
DDR_A_D35
DDR_A_D38
+1.8V_SUS
Place clost to each VREF pin
RN27
4 DDR_SDQ11
3 DDR_SDQ10
10_0404_4P2R_5%~D
DDR_A_D41
DDR_A_D45
1
2
4 DDR_SDQ20
3 DDR_SDQ16
10_0404_4P2R_5%~D
DDR_A_D43
DDR_A_D44
1
2
4 DDR_SDQ18
3 DDR_SDQ22
10_0404_4P2R_5%~D
DDR_A_D49
DDR_A_D48
1
2
4 DDR_SDQ21
3 DDR_SDQ17
10_0404_4P2R_5%~D
DDR_A_D55
DDR_A_D54
1
2
4 DDR_SDQ23
3 DDR_SDQ19
10_0404_4P2R_5%~D
DDR_A_D53
DDR_A_D52
1
2
4 DDR_SDQ29
3 DDR_SDQ25
10_0404_4P2R_5%~D
DDR_A_D51
DDR_A_D50
1
2
4 DDR_SDQ27
3 DDR_SDQ26
10_0404_4P2R_5%~D
DDR_A_D57
DDR_A_D56
1
2
+1.8V_SUS
U4
<11,17> DDR_A_MA[0..13]
C159
0.1U_0402_16V4Z~D
DDR_A_D4
DDR_A_D0
RN17
4 DDR_SDQ2
3 DDR_SDQ1
10_0404_4P2R_5%~D
<11,15> DDR_A_DQS[0..7]
C158
2.2U_0603_6.3V6K~D
1
2
4 DDR_SDQS#4
3 DDR_SDQS4
10_0404_4P2R_5%~D
C157
0.1U_0402_16V4Z~D
DDR_A_D2
DDR_A_D1
<11,15> DDR_A_DM[0..7]
RN15
4 DDR_SDQ41
3 DDR_SDQ45
10_0404_4P2R_5%~D
U5
DDR_SDQS2
DDR_SDQS#2
DDR_SDM2
DDR_SDQ16
DDR_SDQ23
DDR_SDQ20
DDR_SDQ19
DDR_SDQ22
DDR_SDQ17
DDR_SDQ18
DDR_SDQ21
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
<10,17>
V_DDR_MCH_REF E2
<10,17>
<10,17>
DDR_A_MA0
H8
<10,17>
DDR_A_MA1
H3
<11,17>
DDR_A_MA2
H7
<11,17>
DDR_A_MA3
J2
DDR_A_MA4
J8
<10,17>
DDR_A_MA5
J3
<11,17>
DDR_A_MA6
J7
<11,17>
DDR_A_MA7
K2
<11,17>
DDR_A_MA8
K8
DDR_A_MA9
K3
DDR_A_MA10 H2
DDR_A_MA11 K7
DDR_A_MA12 L2
DDR_A_MA13 L8
A2
G1
L3
L7
K4T51083QC-ZCLD5_FBGA60~D
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NU/RDQS
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
D
K4T51083QC-ZCLD5_FBGA60~D
C
C
RN35
RN36
RN38
4 DDR_SDQ43
3 DDR_SDQ44
10_0404_4P2R_5%~D
RN39
RN41
4 DDR_SDQ49
3 DDR_SDQ48
10_0404_4P2R_5%~D
Layout Note:
Place near U4,U5,U6,U7
RN42
4 DDR_SDQ55
3 DDR_SDQ54
10_0404_4P2R_5%~D
+1.8V_SUS
RN44
1
C658
2
2
2
1
2
C672
2
C671
1
2700P_0402_50V7K~D
2
C670
1
2700P_0402_50V7K~D
C669
2
2700P_0402_50V7K~D
1
1
C664
C663
2
C668
1
1
0.1U_0402_16V4Z~D
2
2700P_0402_50V7K~D
2 DDR_SDM4
10_0402_5%~D
2 DDR_SDM5
10_0402_5%~D
2 DDR_SDM6
10_0402_5%~D
2 DDR_SDM7
10_0402_5%~D
2
1
C662
DDR_A_DM4 1
R570
DDR_A_DM5 1
R571
DDR_A_DM6 1
R572
DDR_A_DM7 1
R573
2
0.1U_0402_16V4Z~D
2 DDR_SDM0
10_0402_5%~D
2 DDR_SDM1
10_0402_5%~D
2 DDR_SDM2
10_0402_5%~D
2 DDR_SDM3
10_0402_5%~D
C657
DDR_A_DM0 1
R566
DDR_A_DM1 1
R567
DDR_A_DM2 1
R568
DDR_A_DM3 1
R569
2700P_0402_50V7K~D
A
1
2.2U_0603_6.3V6K~D
4 DDR_SDQS7
3 DDR_SDQS#7
10_0404_4P2R_5%~D
RN68
2
1
C667
DDR_A_DQS7 1
DDR_A_DQS#72
RN66
2
1
2
2700P_0402_50V7K~D
4 DDR_SDQS3
3 DDR_SDQS#3
10_0404_4P2R_5%~D
4 DDR_SDQS5
3 DDR_SDQS#5
10_0404_4P2R_5%~D
1
1
C661
DDR_A_DQS3 1
DDR_A_DQS#32
2
0.1U_0402_16V4Z~D
DDR_A_DQS6 1
DDR_A_DQS#62
C656
4 DDR_SDQS2
3 DDR_SDQS#2
10_0404_4P2R_5%~D
RN63
RN65
DDR_A_DQS2 1
DDR_A_DQS#22
1
2.2U_0603_6.3V6K~D
DDR_A_DQS5 1
DDR_A_DQS#52
RN62
DDR_A_DQS1 1
DDR_A_DQS#12
4 DDR_SDQ58
3 DDR_SDQ59
10_0404_4P2R_5%~D
C666
4 DDR_SDQS1
3 DDR_SDQS#1
10_0404_4P2R_5%~D
RN60
2
2700P_0402_50V7K~D
1
2
2
C660
DDR_A_D58
DDR_A_D59
4 DDR_SDQ61
3 DDR_SDQ60
10_0404_4P2R_5%~D
1
0.1U_0402_16V4Z~D
4 DDR_SDQS0
3 DDR_SDQS#0
10_0404_4P2R_5%~D
RN57
RN59
DDR_A_DQS0 1
DDR_A_DQS#02
C655
1
2
2
2.2U_0603_6.3V6K~D
DDR_A_D61
DDR_A_D60
1
C665
4 DDR_SDQ31
3 DDR_SDQ30
10_0404_4P2R_5%~D
RN56
4 DDR_SDQ63
3 DDR_SDQ62
10_0404_4P2R_5%~D
2700P_0402_50V7K~D
1
2
C659
DDR_A_D63
DDR_A_D62
0.1U_0402_16V4Z~D
1
2
RN54
4 DDR_SDQ24
3 DDR_SDQ28
10_0404_4P2R_5%~D
2
1
DDR_SDQS4
DDR_SDQS#4
DDR_SDM4
DDR_SDQ33
DDR_SDQ35
DDR_SDQ37
DDR_SDQ38
DDR_SDQ34
DDR_SDQ32
DDR_SDQ39
DDR_SDQ36
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
V_DDR_MCH_REF E2
0.1U_0402_16V4Z~D
DDR_A_D31
DDR_A_D30
4 DDR_SDQ57
3 DDR_SDQ56
10_0404_4P2R_5%~D
1
C654
RN51
RN53
1
2
4 DDR_SDQ51
3 DDR_SDQ50
10_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
RN48
RN50
DDR_A_D24
DDR_A_D28
4 DDR_SDQ53
3 DDR_SDQ52
10_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
RN47
B
+1.8V_SUS
+1.8V_SUS
U6
RN45
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
U7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
DDR_SDQS6
DDR_SDQS#6
DDR_SDM6
DDR_SDQ52
DDR_SDQ51
DDR_SDQ53
DDR_SDQ50
DDR_SDQ55
DDR_SDQ48
DDR_SDQ54
DDR_SDQ49
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V_DDR_MCH_REF
M_CLK_DDR1 <10,17>
M_CLK_DDR#1 <10,17>
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
E2
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
K4T51083QC-ZCLD5_FBGA60~D
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
B
K4T51083QC-ZCLD5_FBGA60~D
4 DDR_SDQS6
3 DDR_SDQS#6
10_0404_4P2R_5%~D
RN69
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DDRII-ON BOARD I
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
16
of
59
5
4
3
2
1
Layout Note:
Place near U8,U9,U10,U11
+1.8V_SUS
+1.8V_SUS
U9
DDR_SDQS3
DDR_SDQS#3
DDR_SDM3
DDR_SDQ27
DDR_SDQ25
DDR_SDQ26
DDR_SDQ29
DDR_SDQ28
DDR_SDQ31
DDR_SDQ24
DDR_SDQ30
U8
DDR_SDQS1
DDR_SDQS#1
DDR_SDM1
DDR_SDQ14
DDR_SDQ9
DDR_SDQ15
DDR_SDQ13
DDR_SDQ12
DDR_SDQ11
DDR_SDQ8
DDR_SDQ10
<16> DDR_SDQS#[0..7]
+1.8V_SUS
<16> DDR_SDQS[0..7]
C630
0.1U_0402_16V4Z~D
C173
0.1U_0402_16V4Z~D
C172
0.1U_0402_16V4Z~D
1
1 10K_0402_5%~D
10K_0402_5%~D
1
1
2
2
2
1
R577
200_0402_5%~D
2
R138
200_0402_5%~D
1
C186
C185
C184
C183
C182
C181
C180
C179
C178
4
3
4
3
4
3
4
3
RN72
DDR_A_MA3
1
DDR_A_MA10
2
56_0404_4P2R_5%~D
M_CLK_DDR#1
EEPROM
7
6
5
WP
SCL
SDA
1
2
3
SA0
SA1
SA2
VDD
GND
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
8
1
4
@ C189
0.1U_0402_16V4Z~D
2
DDR_CS0#
1
M_ODT0
2
56_0404_4P2R_5%~D
1 DDR_A_MA12
2 DDR_A_MA7
56_0404_4P2R_5%~D
1 DDR_A_MA6
2 DDR_CKE0
56_0404_4P2R_5%~D
DDR_CKE0
<10,16>
RN75
<11,16> DDR_A_BS0
<11,16> DDR_A_BS1
DDR_A_WE#
2
1
R625
56_0402_5%~D
RN78
DDR_A_BS0
1
4
DDR_A_BS1
2
3
56_0404_4P2R_5%~D
1 DDR_A_RAS#
2 DDR_A_MA11
56_0404_4P2R_5%~D
4
3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
<10,16>
<11,16>
<11,16>
<11,16>
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
D
K4T51083QC-ZCLD5_FBGA60~D
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
+1.8V_SUS
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
U11
DDR_SDQS7
DDR_SDQS#7
DDR_SDM7
DDR_SDQ63
DDR_SDQ56
DDR_SDQ62
DDR_SDQ57
DDR_SDQ60
DDR_SDQ58
DDR_SDQ61
DDR_SDQ59
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
M_CLK_DDR1 <10,16>
M_CLK_DDR#1 <10,16>
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
V_DDR_MCH_REF E2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
K4T51083QC-ZCLD5_FBGA60~D
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
CS#
RAS#
CAS#
WE#
G8
F7
G7
F3
DDR_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
G1
L3
L7
NU/RDQS
NC
NC
NC
B
K4T51083QC-ZCLD5_FBGA60~D
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
1 DDR_A_MA4
2 DDR_A_MA2
56_0404_4P2R_5%~D
RN77
<11,16> DDR_A_WE#
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
V_DDR_MCH_REF E2
+3.3V_RUN
U12
RN73
RN74
<10,16> DDR_CS0#
<10,16> M_ODT0
G8
F7
G7
F3
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
ODT
CK
CK#
CKE
BA0
BA1
+1.8V_SUS
RN71
4
3
CS#
RAS#
CAS#
WE#
M_ODT0
<10,16>
M_CLK_DDR0 <10,16>
M_CLK_DDR#0 <10,16>
DDR_CKE0 <10,16>
DDR_A_BS0 <11,16>
DDR_A_BS1 <11,16>
V_DDR_MCH_REF E2
U10
DDR_SDQS5
DDR_SDQS#5
DDR_SDM5
DDR_SDQ43
DDR_SDQ42
DDR_SDQ44
DDR_SDQ40
DDR_SDQ45
DDR_SDQ47
DDR_SDQ41
DDR_SDQ46
@ 24LC256T-I/ST_TSSOP8~D
4
3
NU/RDQS
NC
NC
NC
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
M_CLK_DDR#0
+0.9V_DDR_VTT
RN70
A2
G1
L3
L7
ODT
CK
CK#
CKE
BA0
BA1
F9
E8
F8
F2
G2
G3
1
2
1
2
2
R576
200_0402_5%~D
R137
200_0402_5%~D
2
C188
3.3P_0402_50VJ~D
1
1
M_CLK_DDR1
2
@ R140 2
@ R141
DDR_A_MA1
1
DDR_A_MA8
2
56_0404_4P2R_5%~D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
C
@ R139
10K_0402_5%~D
2
1
+3.3V_RUN
CLK_SCLK
<6,15> CLK_SCLK
CLK_SDATA
<6,15> CLK_SDATA
B
2
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
K4T51083QC-ZCLD5_FBGA60~D
C174
3.3P_0402_50VJ~D
2
2
1
2
0.1U_0402_16V4Z~D
2
1
2
1
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
DQS
DQS#
DM/RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
M_CLK_DDR0
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
C177
C176
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C175
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
C171
2.2U_0603_6.3V6K~D
1
+0.9V_DDR_VTT
1
2
1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
C682
2
1
Place clost to each VREF pin
2700P_0402_50V7K~D
1
C681
2
2700P_0402_50V7K~D
1
C680
C679
2
2
2
2700P_0402_50V7K~D
1
C170
0.1U_0402_16V4Z~D
2
1
C674
C673
1
1
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
1
V_DDR_MCH_REF E2
<10,15,16,49> V_DDR_MCH_REF
0.1U_0402_16V4Z~D
2
C165
C678
1
<16> DDR_SDM[0..7]
<11,16> DDR_A_MA[0..13]
2
2700P_0402_50V7K~D
C677
2700P_0402_50V7K~D
2
C169
2
1
0.1U_0402_16V4Z~D
1
<16> DDR_SDQ[0..63]
2.2U_0603_6.3V6K~D
C168
2
1
2
0.1U_0402_16V4Z~D
1
1
C164
2.2U_0603_6.3V6K~D
2
2700P_0402_50V7K~D
C676
2700P_0402_50V7K~D
C675
2700P_0402_50V7K~D
2
1
2
0.1U_0402_16V4Z~D
2
1
C163
1
C167
2
1
2
0.1U_0402_16V4Z~D
C166
0.1U_0402_16V4Z~D
C
1
2.2U_0603_6.3V6K~D
2
1
C162
C161
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
D
1
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
C8
C2
D7
D3
D1
D9
B1
B9
DDR_A_RAS#
<11,16>
DDR_A_CAS#
<11,16>
RN79
1 DDR_A_MA0
2 DDR_A_MA5
56_0404_4P2R_5%~D
4
3
A
RN81
4
3
1 DDR_A_CAS#
2 DDR_A_MA9
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
DDRII-ON BOARD II
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
17
of
59
5
4
3
2
1
FAN1 Control and Tachometer
1
+3.3V_RUN
R142
10K_0402_5%~D
D
2
D
FAN1_TACH
1
2
<40>
C190
100P_0402_50V8J~D
@
JFAN1
1
2
1
2
3
22U_0805_6.3V6M~D
2
2
@ C192
C191
@ D3
RB751S40T1_SOD523-2~D
1
22U_0805_6.3V6M~D
1
+FAN1_VOUT
FAN1_TACH
1 GND
2 GND
3
4
5
MOLEX_53780-0370~D
C
C
Place C341 close to the Guardian
pins as possible
<7> H_THERMDA
1
18
+RTC_PWR3V
13
2
1K_0402_5%~D
38
+3V_PWROK#
SET local temperature on M/B
VSET=(Tp-70)/21
=3.3V*R157/(R152+R157)
=1.044
Tp=92 degree
C196
<43> ICH_PWRGD#
0.1U_0402_16V4Z~D
1
1
R150
<38,40,44> POWER_SW#
2
1
R151
+3.3V_SUS
+3.3V_SUS
1
14
THERMTRIP1#
THERMATRIP2#
15
THERMTRIP2#
R155
1K_0402_5%~D
1
2
2
2
2
+FAN1_VOUT
2
MMST3904-7-F_SOT323~D
2
1
Place near the bottom SODIMM
39
29
9
VSET
HW_LOCK#
VSS
6
10
11
19
20
32
DN1
DP1
REM_DIODE1_N
REM_DIODE1_P
THERMTRIP_SIO
ACAV_CLR
30
4
SYS_SHDN#
22
DP3
DN3
FAN_OUT
LDO_SET
24
LDO_OUT
LDO_OUT
25
27
LDO_IN
LDO_IN
26
28
VDD_5V
5
FAN_DAC
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
EMC4000_QFN40~D
Place cap close to the
Guardian pins as possible.
<44> SNIFFER_GREEN#
<44> SNIFFER_YELLOW#
SNIFFER_GREEN#
SNIFFER_YELLOW#
1
+3.3V_ALW
THERMAL PAD
REM_DIODE3_N
REM_DIODE3_P
36
37
LDO_SET
2
ACAV_IN
B
@ C198
2 2200P_0402_50V7K~D
@ R156
10K_0402_5%~D
2
1
<40,51>
+RTC_CELL
THERM_STP#
41
<47>
+2.5V_RUN
1
2
1
Place under CPU
THERMTRIP_SIO <39>
+2.5V_RUN
1
@ R578
31.6K_0402_1%~D
1
2
2
@ C203
0.1U_0402_16V4Z~D
LDO_SET
2
R160
1
2
C197
2 2200P_0402_50V7K~D
R153
10K_0402_5%~D
SMBUS ADDRESS : 2F
C204
2200P_0402_50V7K~D 2
C
@ C205
2200P_0402_50V7K~D
Q8
THERMTRIP3#
33
2.5V_RUN_PWRGD <43>
Place C197 close to the Guardian
pins as possible
+3V_LDOIN
1
A
1
16
1
2
REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil
3
2
C201
0.1U_0402_16V4Z~D
1
1
R157
68K_0402_1%~D
1
C200
2200P_0402_50V7K~D
2
<10> THERMTRIP_MCH#
E
3
2.2K_0402_5%~D
2
B
THERMATRIP2#
Q7
MMST3904-7-F_SOT323~D
2
2
E
C
R159
1
R152
147K_0402_1%~D
B
+1.05V_VCCP
C199
0.1U_0402_16V4Z~D
1
1
1
R154
8.2K_0402_5%~D
31
POWER_SW#
THERMATRIP1#
THERMATRIP3#
2
8.2K_0402_5%~D
LDO_POK
R147
10K_0402_5%~D
1
+RTC_CELL
C195
0.1U_0402_16V4Z~D
3
40
+5V_RUN
C209
0.1U_0402_16V4Z~D
2
2
VCP
VCP
1
+3V_SUS
VSUS_PWRGD
2
1K_0402_5%~D
1
1
1
R148
1
1
2
2
1
+3.3V_RUN
0.27_1210_5%~D
R158
1K_0603_5%~D
2
<24,43> SUSPWROK
3
THERMATRIP1#
2
DP2
DN2
12
21
<40>
Q6
MMST3904-7-F_SOT323~D
3
<7> H_THERMTRIP#
B
35
34
2
ATF_INT#
+3.3V_RUN
1
E
LDO_SHDN#_ADDR
1
2
B
23
+3.3V_SUS
17
2
2
7.5K_0402_5%~D
ATF_INT#
C206
1U_0603_10V4Z~D
1
2.2K_0402_5%~D
2
SMDATA
SMBCLK
C208
10U_0805_10V4Z~D
1
2
1
C
R149
1
+3VSUS_THRM
Q5
MMST3904-7-F_SOT323~D
+1.05V_VCCP
C194
0.1U_0402_16V4Z~D
+3.3V_SUS
7
8
<33,40> DAT_SMB
<33,40> CLK_SMB
R145
C202
10U_0805_6.3V6M~D
R144
49.9_0603_1%~D
2
1
1
B
R146
8.2K_0402_5%~D
R143
10K_0402_5%~D
2
1
U13
+3.3V_SUS
+3.3V_SUS
Use Rev:C
Need create P/N
2
E
<7> H_THERMDC
C
C193
2200P_0402_50V7K~D
@ C207
0.1U_0402_16V4Z~D
A
For Vmargin pop R578 and
R158=30K,R158=1K for production.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
FAN & Thermal Sensor
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
18
of
59
5
4
3
2
1
D
D
Q9
SI3456DV-T1-E3_TSOP6~D
+LCDVDD
S
1
2
<12>
<12>
S
LCD_A1LCD_A1+
<12>
<12>
LCD_A0LCD_A0+
<12>
<12>
Q10
2
G
2N7002W-7-F_SOT323~D
2
G
LCD_A0LCD_A0+
LCD_DDCCLK
LCD_DDCDATA
O
LCD_A1LCD_A1+
<12>
2
ENVDD
D
S
2
C211
0.1U_0603_50V4Z~D
LCD_A2LCD_A2+
1
D
3
<12>
<12>
1
LCD_A2LCD_A2+
LCD_ACLKLCD_ACLK+
Q11
2N7002W-7-F_SOT323~D
2
LCD_ACLKLCD_ACLK+
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
I
LCD_DDCCLK <12>
LCD_DDCDATA <12>
C
Q12
DDTC124EUA-7-F_SOT323~D
G
C
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3
MGND3
MGND4
3
1
1
1
2
33
34
MGND1
MGND2
3
31
32
G
JP1
R161
100K_0402_5%~D
R162
100K_0402_5%~D
R163
470_0402_5%~D
+3.3V_RUN
6
5
2
1
4
+LCDVDD
C210
0.1U_0402_16V4Z~D
+15V_SUS
D
+15V_SUS
+3.3V_RUN
+LCDVDD
1
LCD_TST
LCD_TST
<24>
C212
0.1U_0402_16V4Z~D
BIA_PWM
1
2
2
C213
0.1U_0402_16V4Z~D
BIA_PWM
<12,40>
SBAT_SMBCLK <40>
SBAT_SMBDAT <40>
LAMP_D_STAT#
I-PEX_20143-030E-20F~D
+5V_ALW
1
1
2
@ D19
RB751S40T1_SOD523-2~D
2
C214
0.1U_0402_16V4Z~D
LAMP_STAT#
LAMP_STAT# <24>
M'07 inverter support - Depop D19.
D'05 inverter support - Populate D19
Q13
FDS4435_NL_SO8~D
+PWR_SRC
+GFX_PWR_SRC
40mil
40mil
1
+3.3V_RUN
5
2
1
IN1
PANEL_BKEN
2
IN2
Ua
R167
1
2
1
100K_0402_5%~D
R168
100K_0402_5%~D
2
Q14
3 2N7002W-7-F_SOT323~D
2
G
1
BIA_PWM
4
@ U14
SN74AHC1G08DCKR_SC70-5~D
S
O
3
<12> PANEL_BKEN
C216
0.1U_0603_50V4Z~D
2
D
2
0_0402_5%~D
R165
200K_0402_5%~D
P
FPBACK_EN
Ra
1
R166
G
<39> FPBACK_EN
1
C215
0.1U_0603_50V4Z~D
4
2
B
1
2
1
C217
1000P_0402_50V7K~D
B
+GFX_PWR_SRC
8
7
6
5
1
2
3
M00 support D05 inverter
<40,42,43,47,48,49> RUN_ON
FDS4435: P CHANNAL
M'07 inverter support - Populate Ra,U54 Depop Ua.
D'05 inverter support - Populate Ua, Depop Ra,U54
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Internal LVDS
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
19
of
59
5
4
3
2
1
D
D
DVI_TX2-
DVI_TX21 C218
1
0.1U_0402_16V4Z~D
2
DVI_TX2+
DVI_TX1-
1 C219
1
0.1U_0402_16V4Z~D
2
DVI_TX01 C220
1
0.1U_0402_16V4Z~D
DVI_CLK1 C221
1
0.1U_0402_16V4Z~D
+AVCC_TMDS
<12> SDVOB_BLUE+
<12> SDVOB_BLUE-
R174
2.2K_0402_5%~D
1
R173
2.2K_0402_5%~D
2
1
2
DVI_SCLK
<12> SDVOB_CLK+
<12> SDVOB_CLK-
DVI_CLKDVI_CLK+
TX0TX0+
16
17
DVI_TX0DVI_TX0+
SDG+
SDG-
TX1TX1+
19
20
DVI_TX1DVI_TX1+
43
44
SDB+
SDB-
TX2TX2+
22
23
DVI_TX2DVI_TX2+
46
47
SDC+
SDC-
SDADDC
SCLDDC
9
8
SDSCL
SDSDA
A1
5
4
6
37
38
SDR+
SDR-
1 +VSWING
220_0402_5%~D
RESET#
25
35
EXT_SWING
EXT_RES
30
29
TEST
HTPLG
7
31
27
18
24
12
39
45
3
1
R180
4.7K_0402_5%~D
R178
1K_0402_5%~D
L15
BLM18PG181SN1_0603~D
2
1
1
2 @
1
2
C238
1000P_0402_50V7K~D
1
1
2
2
1
2 @
1
2
180ohm,1500mA,0.09ohm
C239
0.1U_0402_16V4Z~D
L17
BLM18PG181SN1_0603~D
2
1
1
2
180ohm,1500mA,0.09ohm
B
SDVO_CTRLCLK <12>
SDVO_CTRLDATA <12>
1
2
+3.3V_RUN
@ R176
1K_0402_5%~D
A1 LOW: Address = 0x70
1
HIGH: Address = 0x72
SII1362CLU_LQFP48~D
2
1
SDVO_CTRLCLK
R179
4.7K_0402_5%~D
2
1
2
A
C
+3.3V_RUN
+PVCC1_TMDS
R177
1K_0402_5%~D
GND
GND
PGND2
AGND
AGND
AGND
SGND
SGND
SPGND
<38> DVI_DETECT
+2.5V_RUN
+1.8V_RUN
DVI_SDATA <38>
DVI_SCLK
<38>
2
2
R175
2
1
13
14
SDI+
SDI-
2
<10,22,24,29,36> PLTRST#
+AVCC_TMDS
DVI_SDATA
SDVOB_BLUE+
SDVOB_BLUE-
<38>
+PVCC2_TMDS
TXCTXC+
32
33
SDVOB_GREEN+ 40
SDVOB_GREEN- 41
<12> SDVOB_GREEN+
<12> SDVOB_GREEN-
DVI_CLK+
C248
0.1U_0402_16V4Z~D
<12> SDVOB_RED+
<12> SDVOB_RED-
+5V_RUN
0.1U_0402_16V4Z~D
2 INT+
2 INT0.1U_0402_16V4Z~D
SDVOB_RED+
SDVOB_RED-
<38>
C247
1000P_0402_50V7K~D
<12> SDVOB_INT+
<12> SDVOB_INT-
2 @
1
2
VCC
VCC
VCC
C244
1
1
C249
<38>
DVI_CLK-
L14
BLM18PG181SN1_0603~D
2
1
180ohm,1500mA,0.09ohm
0.1U_0402_16V4Z~D
U15
B
2 @
1
2
11
26
2
PVCC1
PVCC2
0.1U_0402_16V4Z~D
36
42
2
48
0.1U_0402_16V4Z~D
C243
SVCC
SVCC
2
1
C242
SPVCC
10U_0805_10V4Z~D
1
C241
15
21
2
1
1
+VCC_TMDS
1
C240
1
C233
1000P_0402_50V7K~D
2
AVCC
AVCC
180ohm,1500mA,0.09ohm
1
10U_0805_10V4Z~D
OVCC
+1.8V_RUN
2
10
34
28
L16
BLM18PG181SN1_0603~D
2
1
0.1U_0402_16V4Z~D
DVI_TX0+
10U_0805_10V4Z~D
C237
100P_0402_50V8J~D
1
0.1U_0402_16V4Z~D
+SPVCC_TMDS
C231
C232
10U_0805_10V4Z~D
2
1
C230
<38>
180ohm,1500mA,0.09ohm
C246
100P_0402_50V8J~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_RUN
1
C224
C236
10U_0805_10V4Z~D
1
1
C223
C245
10U_0805_10V4Z~D
2
2
C222
<38>
DVI_TX0-
C229
C235
0.1U_0402_16V4Z~D
2 @
1
2
C234
100P_0402_50V8J~D
2 @
1
C228
0.1U_0402_16V4Z~D
1
C227
1000P_0402_50V7K~D
C226
100P_0402_50V8J~D
2
1
DVI_TX1+
L13
BLM18PG181SN1_0603~D
2
1
+SVCC_TMDS
1
C225
10U_0805_10V4Z~D
2
1
L12
BLM18PG181SN1_0603~D
180ohm,1500mA,0.09ohm
C
<38>
2 R172
110_0402_1%~D
DVI_CLK+
+3.3V_RUN
<38>
DVI_TX1-
2 R171
110_0402_1%~D
DVI_TX0+
2
DVI_TX2+
2 R170
110_0402_1%~D
DVI_TX1+
2
<38>
2 R169
110_0402_1%~D
A
SDVO_CTRLDATA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Internal LVDS
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
20
of
59
5
4
3
2
1
D
D
@ D6
DA204U_SOT323~D
@
2
+CRT_VCC
3
2
3
2
1
2
1
@ C253
10P_0402_50V8J~D
2
C256
0.01U_0402_16V7K~D
1
C252
@
2
22P_0402_50V8J~D
1
C251
C250
@
2
22P_0402_50V8J~D
C
1
22P_0402_50V8J~D
VGA_BLU
R649
0_1206_5%~D
2
VGA_GRN
R181
150_0402_1%~D
2
1
<12,38> VGA_BLU
R183
150_0402_1%~D
2
1
<12,38> VGA_GRN
L18
BLM18BB220SN1D_0603~D
1
2
22ohm,500mA,0.1ohm
L19
BLM18BB220SN1D_0603~D
1
2
22ohm,500mA,0.1ohm
L20
BLM18BB220SN1D_0603~D
1
2
22ohm,500mA,0.1ohm
VGA_RED
R182
150_0402_1%~D
2
1
<12,38> VGA_RED
3
2
+3.3V_RUN
D7
RB751S40T1_SOD523-2~D
1
1
2
@ D5
DA204U_SOT323~D
1
1
1
+5V_RUN
@ D4
DA204U_SOT323~D
1
@ C254
10P_0402_50V8J~D
@ C255
10P_0402_50V8J~D
2
1
2
RED
DAT_DDC2
GREEN
2
PAD~D
R187
2.2K_0402_5%~D
JVGA_HS
BLUE
+CRT_VCC
JVGA_VS
M_ID2#
1
C637
0.1U_0402_16V4Z~D
2
1
2
1
R186
2.2K_0402_5%~D
@ R185
1K_0402_5%~D
2
1
@R184
1K_0402_5%~D
2
1
T12
C
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+CRT_VCC
CLK_DDC2
<12,38> DAT_DDC2
16
17
SUYIN_070546FR015S2307R~D
<12,38> CLK_DDC2
+CRT_VCC
2
A
Y
4
1
2
R650
0_0402_5%~D
1
3
39_0402_5%~D
SN74AHCT1G125GW_SOT-353~D
120ohm,600mA,0.25ohm
L21
BLM11A121S_0603~D
1
2
L22
BLM11A121S_0603~D
HSYNC_R
<38>
1
2
1
120ohm,600mA,0.25ohm
5
P
2
VGA_VSYNC_B
2
A
3
39_0402_5%~D
G
1
VSYNC_R
U17
OE#
R190
<12> VGA_VSYNC
1
B
1
2
Y 4
R651
0_0402_5%~D
SN74AHCT1G125GW_SOT-353~D
<38>
2
C258
22P_0402_50V8J~D
2
U16
C257
22P_0402_50V8J~D
1
VGA_HSYNC_B
G
<12> VGA_HSYNC
P
R189
OE#
5
R188
1K_0402_5%~D
1
2
1
B
2
DA204U
K1 A2
A
A1
A
K2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CRT Connector
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
21
of
59
5
4
3
2
1
14
+3.3V_SUS
+3.3V_RUN
ICH_GPIO2_PIRQE#
2
8.2K_0402_5%~D
ICH_GPIO3_PIRQF#
2
8.2K_0402_5%~D
ICH_GPIO4_PIRQG#
2
8.2K_0402_5%~D
ICH_GPIO5_PIRQH#
2
8.2K_0402_5%~D
1
R207
1
R208
1
R209
1
R211
1
R214
1
R215
PCI_REQ0#
2
8.2K_0402_5%~D
PCI_REQ1#
2
8.2K_0402_5%~D
PCI_REQ2#
2
8.2K_0402_5%~D
PCI_REQ3#
2
8.2K_0402_5%~D
PCI_REQ4#
2
8.2K_0402_5%~D
PCI_REQ5#
2
8.2K_0402_5%~D
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
<31>
<31>
C/BE0#
C/BE1#
C/BE2#
C/BE3#
B15
C12
D12
C15
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C26
A9
B19
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
G8
F7
F8
G7
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
Interrupt
A3
B4
C5
B5
PIRQA#
PIRQB#
PIRQC#
PIRQD#
AE5
AD5
AG4
AH4
AD9
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
I/F
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
P
D
14
+3.3V_SUS
4
5
IN1
OUT
AE9
AG8
AH8
F21
AH20
PCI_RST#
PCI_RST#
<31,35,37>
74VHC08MTCX_NL_TSSOP14~D
7
PCI_IRDY# <31,37,38>
PCI_PAR <31,37>
6
IN2
<31,37>
<31,37>
<31,37>
<31,37>
14
+3.3V_SUS
PCI_PLTRST#
10
IN1
OUT
CLK_PCI_ICH <6>
ICH_PME#
<39>
8
PLTRST#
PLTRST#
<10,20,24,29,36>
IN2
74VHC08MTCX_NL_TSSOP14~D
7
9
U18C
P
PCI_DEVSEL# <31,37>
PCI_PERR# <31,37>
PCI_PLOCK# <37>
PCI_SERR# <31,37>
PCI_STOP# <31,37>
PCI_TRDY# <31,37>
PCI_FRAME# <31,37,38>
G
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
U18B
P
PCI_PCIRST#
G
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
+3.3V_SUS
13
12
C
U18D
IN1
OUT
11
PLTRST2#
PLTRST2#
<39,40>
IN2
74VHC08MTCX_NL_TSSOP14~D
MCH_ICH_SYNC# <10>
82801GHM SL8YB B0_BGA652~D
Place closely pin U45.A9
PCI_GNT5#
PCI_GNT4#
CLK_PCI_ICH
2
1
R203
1
R204
1
R205
1
R206
<37>
<31>
<31>
<31>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ2#
PCI_GNT2#
R212
1K_0402_5%~D
@R210
10_0402_5%~D
@ R213
1K_0402_5%~D
1
PCI_PIRQA#
2
8.2K_0402_5%~D
PCI_PIRQB#
2
8.2K_0402_5%~D
PCI_PIRQC#
2
8.2K_0402_5%~D
PCI_PIRQD#
2
8.2K_0402_5%~D
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
1
1
R199
1
R200
1
R201
1
R202
<38>
<37,38>
2
C
PCI_REQ0#
PCI_GNT0#
14
PCI_PLOCK#
2
8.2K_0402_5%~D
PCI _IRDY#
2
8.2K_0402_5%~D
PCI_SERR#
2
8.2K_0402_5%~D
PCI_PERR#
2
8.2K_0402_5%~D
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
1
1
R195
1
R196
1
R197
1
R198
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
2
PCI_DEVSEL#
2
8.2K_0402_5%~D
PCI_STOP#
2
8.2K_0402_5%~D
PCI_TRDY#
2
8.2K_0402_5%~D
PCI_FRAME#
2
8.2K_0402_5%~D
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
PCI
P
+3.3V_RUN
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
74VHC08MTCX_NL_TSSOP14~D
G
D
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
7
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
3
IN2
U19B
<31,37> PCI_AD[0..31]
1
R191
1
R192
1
R193
1
R194
OUT
7
2
U18A
IN1
G
1
1
B
@C259
8.2P_0402_50V8J~D
GNT5#
R214
GNT4#
R213
LPC (11)
unstuff unstuff
PCI (10)
unstuff stuff
SPI (01)
B
2
stuff unstuff
*
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ICH7(1/4)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
22
of
59
5
4
C260
12P_0402_50V8J~D
2
1
U19A
RTCX1
RTCX2
AA3
RTCRST#
CMOS1
@SHORT PADS~D
1
2
@ C263 27P_0402_50V8J~D
<34> ICH_AZ_MDC_RST#
W1
Y1
Y2
W3
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
1
ICH_AC_BITCLK_R
2
2 R223 ICH_AC_SYNC_R
R224
ICH_AC_RST_R#
2
R225
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
1
33_0402_5%~D
1
33_0402_5%~D
1
33_0402_5%~D
<27> ICH_AZ_CODEC_SDIN0
<34> ICH_AZ_MDC_SDIN1
R227
1
<34> ICH_AZ_MDC_SDOUT
LDRQ0#
LDRQ1# / GPIO23
AC3
AA5
LPC_LDRQ0#
LPC_LDRQ1#
LFRAME#
AB3
LPC_LFRAME#
A20GATE
A20M#
AE22
AH28
CPUSLP#
AG27
H_CPUSLP_R#
TP1 / DPRSTP#
TP2 / DPSLP#
AF24
AH25
DPRSLP#
FERR#
AG26
H_FERR#
GPIO49 / CPUPWRGD
AG24
H_PW RGOOD
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
H_IGNNE#
RCIN#
AG23
SIO_RCIN#
SMI#
NMI
AF23
AH24
H_SMI#
H_NMI
H_STPCLK#
V3
LAN_CLK
U3
LAN_RSTSYNC
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
U7
V6
V7
LAN_TXD0
LAN_TXD1
LAN_TXD2
U1
R6
ACZ_BCLK
ACZ_SYNC
R5
ACZ_RST#
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ICH_AC_SDOUT_R T4
2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
AC-97/AZALIA
2
C
INTVRMEN
INTRUDER#
2
C262
1U_0603_10V4Z~D
1
2
<34> ICH_AZ_MDC_BITCLK
<34> ICH_AZ_MDC_SYNC
W4
Y5
AH22
AF26
THRMTRIP_ICH#
DA0
DA1
DA2
AH17
AE17
AF17
IDE_DA0
IDE_DA1
IDE_DA2
AF3
AE3
AG2
AH2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
DCS1#
DCS3#
AE16
AD16
IDE_DSC1#
IDE_DSC3#
AF7
AE7
AG6
AH6
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF1
AE1
SATA_CLKN
SATA_CLKP
AH10
AG10
SATARBIASN
SATARBIASP
AG16
AH16
AF16
AH15
AF15
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
+3.3V_RUN
B
R229
2
1
IDE_IRQ
8.2K_0402_5%~D
<26>
<26>
<26>
<26>
<26>
IDE_ DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
DDREQ
AE15
IDE_DDREQ
SATA
SATALED#
IDE
SIO_A20GATE
<39>
<39>
SIO_RCIN#
LPC_LFRAME# <29,39,40>
@ R221
2
1
0_0402_5%~D
SIO_A20GATE
H_A20M#
H_CPUSLP#
R222
2
1
0_0402_5%~D
H_DPRSTP#
H_INIT#
H_INTR
STPCLK#
33_0402_5%~D
+3.3V_RUN
LPC_LDRQ0#
LPC_LDRQ1#
H_DPSLP#
THERMTRIP#
ACZ_SDOUT
AF18
D
AA6
AB5
AC4
Y6
LAN
1
1
LPC_LAD[0..3] <29,39,40>
LAD0
LAD1
LAD2
LAD3
LPC
AB1
AB2
RTC
C261
12P_0402_50V8J~D 32.768K_12.5PF_Q13MC30610003~D
2
1
2
1 ICH_RTCX2
R643
0_0402_5%~D
ICH_RTCRST#
1
2
+RTC_CELL
R218
R219
20K_0402_5%~D
1
2 ICH_INTVRMEN
332K_0402_1%~D SM_INTRUDER#
CPU
1
2
R217
10M_0402_5%~D
Y2
3
SM_INTRUDER#
2
1
Package
9.6X4.06 mm
4
D
2
R216
1M_0402_5%~D
2
ICH_RTCX1
1
+RTC_CELL
3
R226 1
IDE_DA[0..2]
2 56_0402_5%~D
SIO_A20GATE <40>
H_A20M#
<7>
H_CPUSLP#
<7,10>
H_DPRSTP#
<7,50>
H_DPSLP#
<7>
H_FERR#
<7>
2
R220
2
R584
1
10K_0402_5%~D
1
10K_0402_5%~D
DPRSTP# daisy
ICH7-M --> IMVP6 -->Yonah
H_PWRGOOD <7>
H_IGNNE#
<7>
H_INIT#
H_INTR
<7>
<7>
SIO_RCIN#
<40>
H_SMI#
H_NMI
<7>
<7>
H_STPCLK#
<7>
C
+1.05V_VCCP
<26>
+1.05V_VCCP
IDE_DSC1#
IDE_DSC3#
<26>
<26>
IDE_DD[0..15]
R228
56_0402_5%~D
2
1
H_FERR#
IDE_DD[0..15] <26>
B
IDE_DDREQ
<26>
82801GHM SL8YB B0_BGA652~D
Close to U19
<27> ICH_AZ_CODEC_SDOUT
1
R230
33_0402_5%~D
2 ICH_AC_SDOUT_R
<27> ICH_AZ_CODEC_SYNC
1
R231
33_0402_5%~D
2 ICH_AC_SYNC_R
<27> ICH_AZ_CODEC_RST#
1
R232
33_0402_5%~D
2 ICH_AC_RST_R#
<27> ICH_AZ_CODEC_BITCLK
1
R233
33_0402_5%~D
2 ICH_AC_BITCLK_R
A
A
1
2
@ C264
27P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ICH7(2/4)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
23
of
59
5
4
3
2
1
+3.3V_SUS
BT_RADIO_DIS#
2
10K_0402_5%~D
1
R247
WWAN_RADIO_DIS#
2
10K_0402_5%~D
1
R254
<27>
LAMP_STAT#
2
10K_0402_5%~D
I CH_RI#
2
8.2K_0402_5%~D
SPKR
1
R246
+3.3V_SUS
SPKR
ITP_DBRESET#
+3.3V_SUS
PM_BMBUSY#
<10> PM_BMBUSY#
1
R250
SMBALERT#
2
10K_0402_5%~D
1
R251
ICH_BATLOW#
2
8.2K_0402_5%~D
1
R253
ICH_PCIE_WAKE#
2
680_0402_5%~D
SIO_EXT_SMI#
2
10K_0402_5%~D
1
R234
SIO_EXT_SCI#
2
10K_0402_5%~D
1
R255
DPRSLPVR
2
100K_0402_5%~D
<19>
LCD_TST
<26> IDE_HRESET#
AC20
AF21
2
<43,50> IMVP_PWRGD
<40> SIO_EXT_WAKE#
<19> LAMP_STAT#
<40> SIO_EXT_SMI#
GPIO18 / STPPCI#
GPIO20 / STPCPU#
GPIO26
IDE_HRESET#
B21
E23
GPIO27
GPIO28
GPIO32 / CLKRUN#
BT_RADIO_DIS#
AC19
U2
GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#
ICH_PCIE_WAKE#
IRQ_SERIRQ
SIO_THRM#
F20
AH21
AF20
WAKE#
SERIRQ
THRM#
IMVP_PWRGD
AD22
VRMPWRGD
SIO_EXT_WAKE#
LAMP_STAT#
SIO_EXT_SMI#
AC21
AC18
E21
GPIO6
GPIO7
GPIO8
AC1
B2
CLK_ICH_14M
CLK_ICH_48M
SUSCLK
C20
ICH_SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
B24
D23
F22
SIO_SLP_S3#
PWROK
AA4
ICH_PWRGD
AC22
DPRSLPVR
TP0 / BATLOW#
C21
ICH_BATLOW#
PWRBTN#
C23
SIO_PWRBTN#
LAN_RST#
C19
PLTRST#
RSMRST#
Y4
SUSPWROK
2
10K_0402_5%~D
GPIO16 / DPRSLPVR
D
CLK_ICH_14M <6>
CLK_ICH_48M <6>
PAD~D
1
T6
2
@ C265
4.7P_0402_50V8C~D
SIO_SLP_S3# <40>
SIO_SLP_S5#
1
R252
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
CLK_ICH_14M
@ R243
10_0402_5%~D
CLK14
CLK48
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
SATACLKREQ#/GPIO35
GPIO38
GPIO39
GPIO
AF19
AH18
AH19
AE19
1
GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
GPIO11 / SMBALERT#
A21
AG18
<34> BT_RADIO_DIS#
R370
10K_0402_5%~D
@
<39> ICH_PCIE_WAKE#
<29,31,39,40> IRQ_SERIRQ
<40> SIO_THRM#
GPIO0 / BM_BUSY#
LCD_TST
CLKRUN#
(PCI Express Wake Event)
1
1
R240
<31,39,40> CLKRUN#
B23
H_STP_PCI#
H_STP_CPU#
<6> H_STP_PCI#
<6> H_STP_CPU#
SPKR
SUS_STAT#
SYS_RST#
GPIO
C
LINKALERT#
2
10K_0402_5%~D
RI#
A19
A27
A22
AB18
SMBALERT#
1
R249
A28
SYS
<7,40> ITP_DBRESET#
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
R241
8.2K_0402_5%~D
1
2
2
1
R245
ICH_SMLINK0
ICH_SMLINK1
C22
B22
A26
B25
A25
SATA
GPIO
CLKRUN#
2
8.2K_0402_5%~D
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
<6,29,36> ICH_SMBCLK
<6,29,36> ICH_SMBDATA
Clocks
1
R244
D
Place closely pin U45.AC1
+3.3V_RUN
U19C
POWER MGT
1
R242
IRQ_SERIRQ
2
10K_0402_5%~D
R236
2.2K_0402_5%~D
2
SIO_THRM#
2
8.2K_0402_5%~D
SMB
1
R237
R239
10K_0402_5%~D
1
2
@
R238
10K_0402_5%~D
1
2
+3.3V_RUN
1
R235
2.2K_0402_5%~D
2
1
+3.3V_SUS
SIO_SLP_S5# <40>
ICH_PWRGD
<6>
DPRSLPVR
<50>
1
R248
2
R574
2
10K_0402_5%~D
1
0_0402_5%~D
PM_EXTTS#1
<10>
SIO_PWRBTN# <40>
PLTRST#
SIO_EXT_SCI#
<10,20,22,29,36>
SUSPWROK
<18,43>
SIO_EXT_SCI# <40>
C
RSVD_HDDC_EN#
GPIO24
WWAN_RADIO_DIS#
PAD~D
T17
PAD~D
T7
WWAN_RADIO_DIS# <36>
82801GHM SL8YB B0_BGA652~D
close to ICH7-M
C270 1
2 0.1U_0402_10V6K~D
C271 1
2 0.1U_0402_10V6K~D
ICH_EC_SPI_CLK
SPI_CS#
<40> ICHO_ECO_SPII_DATA
<40> ICHI_ECI_SPIO_DATA
ICHO_ECO_SPII_DATA
ICHI_ECI_SPIO_DATA
R268
47_0402_5%~D
1
2
K26
K25
J28
J27
PERn3
PERp3
PETn3
PETp3
+3.3V_SUS
ICH_SPI_CLK
2
R641
1
R269
PCIE_IRX_LOMTX_N3
PCIE_IRX_LOMTX_P3
PCIE_ITX_LOMRX_N3
PCIE_ITX_LOMRX_P3
1
47_0402_5%~D
2
47_0402_5%~D
ICHO_SPII
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
SPI
<40> ICH_EC_SPI_CLK
<40>
SPI_CS#
+3.3V_SUS
2
R266
10K_0402_5%~D
1
2
+3.3V_SUS
PERn2
PERp2
PETn2
PETp2
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31
USB
V26
V25
U28
U27
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25
AD24
AC28
AC27
DMI_CLKN
DMI_CLKP
AE28
AE27
CLK_PCIE_ICH#
CLK_PCIE_ICH
C25
D25
DMI_IRCOMP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
D1
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
<10>
<10>
<10>
<10>
USB_OC5#
USB_OC3#
1
R256
1
R257
1
R258
1
R259
1
R260
1
R261
1
R262
1
R263
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC7#
USB_OC5#
USB_OC6#
USB_OC4#
<33>
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
+3.3V_SUS
B
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
R264 24.9_0402_1%~D
1
2
USBP0USBP0+
USBP1USBP1+
USBP0USBP0+
USBP1USBP1+
+1.5V_RUNWithin
<36>
<36>
<39>
<39>
USB_OC6#
USB_OC4#
500 mils
<33>
<33>
<---Mini2 WLAN
Place closely pin U45.B2
<---SIO USB Hub
CLK_ICH_48M
1
2 0.1U_0402_10V6K~D
H26
H25
G28
G27
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
<33>
<33>
<33>
<33>
<33>
<33>
<38>
<38>
@ R270
10_0402_5%~D
<---REAR
<---PWR USB
2
C269 1
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
DIRECT MEDIA INTERFACE
2 0.1U_0402_10V6K~D
2
<29> PCIE_ITX_LOMRX_P3_C
B
2 0.1U_0402_10V6K~D
C268 1
1
GIGA LAN--->
<36> PCIE_ITX_WLANRX_P2_C
<29> PCIE_IRX_LOMTX_N3
<29> PCIE_IRX_LOMTX_P3
<29> PCIE_ITX_LOMRX_N3_C
C267 1
PERn1
PERp1
PETn1
PETp1
R267
10K_0402_5%~D
PCIE_ITX_WANRX_P1_C
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
2 0.1U_0402_10V6K~D
1
<36>
<36>
<36>
<36>
C266 1
F26
F25
E28
E27
PCI-EXPRESS
Mini Card 1--->
USB_OC3#
U19D
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
R265
10K_0402_5%~D
Mini Card 2--->
<36> PCIE_IRX_WANTX_N1
<36> PCIE_IRX_WANTX_P1
<36> PCIE_ITX_WANRX_N1_C
<---REAR
1
<---Docking
R271 22.6_0402_1%~D
1
2
USBRBIAS
2
@ C272
4.7P_0402_50V8C~D
Within 500 mils
A
A
82801GHM SL8YB B0_BGA652~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ICH7(3/4)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
24
of
59
5
4
3
2
1
+1.05V_VCCP
U19F
2
C
D9
RB751S40T1_SOD523-2~D
1
2
R273
10_0402_5%~D
ICH_V5REF_SUS
1
2
C289
0.1U_0402_10V6K~D
+3.3V_RUN
0.1U_0402_10V6K~D
1
+5V_SUS +3.3V_SUS
C293
1
2
R585
0.5_0805_1%~D
1
2
B
C299
10U_0805_6.3V6M~D
1
+1.5V_DMIPLL
L24
BLM11A601S_0603~D
+DMIPLL_R 1
2
600ohm,100mA
C298
0.01U_0402_16V7K~D
+1.5V_RUN
2
B27
+1.5V_DMIPLL AG28
1
+1.5V_RUN
2
1
C302
0.1U_0402_10V6K~D
2
+3.3V_RUN
1
2
C303
0.1U_0402_10V6K~D
+1.5V_RUN
+1.5V_RUN
C304
1U_0603_10V4Z~D
1
2
+3.3V_SUS
+1.5V_RUN
2
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
Y7
C308
0.1U_0402_10V6K~D
2
+3.3V_SUS
1
C309
0.1U_0402_10V6K~D
A
V5
V1
W2
W7
R7
VccDMIPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
1
U6
Vcc3_3[1]
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
1
C306
0.1U_0402_10V6K~D
Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
AE23
AE26
AH26
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
VccRTC
W5
VccSus3_3[1]
P7
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
A24
C24
D19
D22
G19
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
C274
2
+3.3V_RUN
+3.3V_SUS
2
1
2
1
2
2
C294
0.1U_0402_10V6K~D
1
2
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
+1.5V_RUN
Vcc1_5_A[24]
Vcc1_5_A[25]
AB8
AC8
2
1
2
C295
0.1U_0402_10V6K~D
+3.3V_SUS
1
1
2
2
+1.5V_RUN
+1.5V_RUN
1
A1
H6
H7
J6
J7
+3.3V_RUN
+RTC_CELL
+1.5V_RUN
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
2
+3.3V_SUS
T7
F17
G17
C28
G20
2
1
2
C283
0.1U_0402_10V6K~D
C285
0.1U_0402_10V6K~D
C286
1
2
0.1U_0402_10V6K~D
C287
4.7U_0603_6.3V6M~D
1
AB17
AC17
VccSus1_05[2]
VccSus1_05[3]
1
1
+1.05V_VCCP
C284
0.1U_0402_10V6K~D
1
2
+3.3V_RUN
1
Vcc1_5_A[19]
Vcc1_5_A[20]
VccSus1_05[1]
2
CRB is 270uF
1
K7
+
C275
330U_V_6.3VM_R25M~D
0.1U_0402_10V6K~D
2
1
C297
0.1U_0402_10V6K~D
C282
0.1U_0402_10V6K~D
1
C296
0.1U_0402_10V6K~D
2
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
C292
0.1U_0402_10V6K~D
ICH_V5REF_RUN
1
V5REF_Sus
1
C301
0.1U_0402_10V6K~D
2
V5REF[2]
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C291
0.1U_0402_10V6K~D
2
F6
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
C300
0.1U_0402_10V6K~D
2
1
0.1U_0402_10V6K~D
1
2
D8
RB751S40T1_SOD523-2~D
1
0.1U_0402_10V6K~D
C279
2
R272
100_0402_5%~D
ICH_V5REF_SUS
0.1U_0402_10V6K~D
C278
C276
2
1
+5V_RUN +3.3V_RUN
+1.5V_RUN_L
L23
+1.5V_RUN_L
1
2
BLM21PG600SN1D_0805~D 1
60ohm,3000mA,0.025ohm
1
+
C277
+1.5V_RUN
220U_D2_4M_R45~D
D
V5REF[1]
C290
0.1U_0402_10V6K~D
G10
AD17
C273
1U_0603_10V4Z~D
U19E
ICH_V5REF_RUN
2
C305
0.1U_0402_10V6K~D
+1.5V_RUN
1
2
C307
0.1U_0402_10V6K~D
VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
D
C
B
82801GHM SL8YB B0_BGA652~D
82801GHM SL8YB B0_BGA652~D
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ICH7(4/4)
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
25
of
59
5
4
3
2
1
D
D
HDD Connector
JHDD1
<23> IDE_DA[0..2]
+3.3V_RUN
1
R276
2 IDE_ DIORDY
4.7K_0402_5%~D
<23> IDE_DIOR#
<23> IDE_DIORDY
<23> IDE_DDACK#
+3.3V_HDD
2
@ R278
1 IDE_ACT#
510_0402_5%~D
<23> IDE_DSC1#
<44> IDE_ACT#
C
IDE_DIOR#
IDE_ DIORDY
IDE_DDACK#
IDE_DA1
IDE_DA0
IDE_ACT#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
GND
42
44
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOW#
+3.3V_HDD
0.1U_0402_16V4Z~D
IDE_DDREQ
IDE_DIOW#
IDE_IRQ
PDIAG#
IDE_DA2
IDE_IRQ
<23>
<23>
<23>
IDE_DSC3#
<23>
+3.3V_HDD
1
2
R275
10K_0402_5%~D
1
1
2
2
1
C311
1
C312
2
1U_0603_10V4Z~D
2
C313
0.1U_0402_16V4Z~D
<23> IDE_DD[0..15]
IDE_HRESET#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
C310
1000P_0402_50V7K~D
<24> IDE_HRESET#
Pleace near HD CONN
C
+3.3V_HDD
FOX_QT510406-2101-7F~D
Need to modify of FPC ZIP connector
HDD PWR
+15V_SUS
+3.3V_SUS
B
D @ Q15
SI3456DV-T1-E3_TSOP6~D
G
HDD_EN_3.3V
3
S
2
1
1
1
2
2
@
PJP1
R281
100K_0402_5%~D
@ Q16
2N7002W-7-F_SOT323~D
+3.3V_RUN
+3.3V_HDD
1
C315
10U_0805_10V4Z~D
S
2
G
<39> HDDC_EN#
C314
0.1U_0402_16V4Z~D
1
D
3
4
2
@ R280
100K_0402_5%~D
1
2
5
6
1
B
2
PAD-OPEN 4x4m
+3.3V_HDD Source
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
IDE HDD Connector
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
26
of
59
5
4
3
2
1
5
+5V_RUN
+VDDA
+5V_SUS
+VDDA
TPS793475_BYPASS
TPS793475DBVRG4_SOT23-5~D
2
2
1
2
2
single gate TTL
1
2
<24>
<39>
1
SPKR
A
Y
2
BEEP
B
4
D
3
C323
0.1U_0402_10V6K~D
2
R282
10K_0402_5%~D
Z2402
Z2403
1
2
1
C325
0.1U_0402_10V6K~D
PC_BEEP
2
U23
SN74AHCT1G86DCKR_SC70-5~D
PC_BEEP
<28>
TRACE>15 mil
R283
2.2K_0402_5%~D
2
When L47 is popped, no pop U22.
1
1
2
1
4
5
EN BYPASS
P
AUDIO_AVDD_ON 3
G
GND
3
IN
2
1
1
2
@ L26
BLM11A601S_0603~D
600ohm,100mA
1
C322
0.047U_0402_16V7K~D
<39> AUDIO_AVDD_ON
OUT
5
C321
0.1U_0402_10V6K~D
2
1
1
+VDDA=4.75V
C324
0.1U_0402_10V6K~D
2
1
C318
1U_0603_10V6K~D
1
C317
0.047U_0402_16V7K~D
C316
0.1U_0402_10V6K~D
U22
C320
2.2U_0603_6.3V6K~D
D
4
+3.3V_RUN
+VDDA
8
RESET#
<23> ICH_AZ_CODEC_SYNC
7
SYNC
<23> ICH_AZ_CODEC_SDOUT
2
SDATA_OUT
<23> ICH_AZ_CODEC_BITCLK
3
BIT_CLK
5
SDATA_IN
19
VREF_OUT
AC97VREFI
18
VREF_IN
CAP2
20
CAP2
21
1
0_0402_5%~D
1
22
GPIO1
DOCK_HP_MUTE#
30
GPIO2
<28>
<38> SPDIF_DOCK
ICH_AZ_CODEC_SDOUT
2
@ C337
22P_0402_50V8J~D
SPDIF _OUT
C620
10U_0805_10V6M~D
10
CD_R
12
MIC1
13
NB_MICIN_L
<28>
MIC2
14
NB_MICIN_R
<28>
HP_L
27
HP_OUT_L
<28>
HP_R
28
HP_OUT_R
<28>
LOUT_L
23
LOUT_R
24
MONO_OUT
1
11
NC1
NC2
1
4
C336
1U_0603_10V6K~D
1
2
1
32
1
0_0402_5%~D
SENSE_A
C332 0.1U_0402_10V6K~D
1
2
1
R287
C333
1
2
1
R288
0.1U_0402_10V6K~D
ICH_AZ_CODEC_SYNC
@ C339
10P_0402_50V8J~D
1
2
ICH_AZ_CODEC_SDOUT 1
@ C342
10P_0402_50V8J~D
2
20K
+VDDA
SENSE_A 2
R286
1
5.1K_0402_1%~D
AUD_LINE_OUT <28>
STAC9200X5NAEB1XR_QFN32~D
D
D
S
S
2
G
Q17
2N7002W-7-F_SOT323~D
2
MIC_SWITCH <28>
G
Q18
2N7002W-7-F_SOT323~D
1
2
1
Note: C336,C340,C341,C326,C327,C328,C619,C620 use
Temp. characteristics: X5R
Operating range: -55~+85degree
A
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
10K
39.2K
CAP2
C341
0.1U_0402_10V6K~D
1
C340
1U_0603_10V6K~D
@ C338
10P_0402_50V8J~D
2
ICH_AZ_CODEC_RST#
A
5.11K
B1
2
2.2K_0402_5%~D
1
2
C334
1000P_0402_50V7K~D
1
2
C335
1000P_0402_50V7K~D
1
2
C721
1000P_0402_50V7K~D
SENSE_A
2
Close to U24.20
2
2.2K_0402_5%~D
25
9
HP_NB_SENSE
Close to U24
CA1
C
B
Close to U24.18
AC97VREFI
R289
47_0402_5%~D
@
2
R591
CD_L
SPDIF _ IN/EAPD /GPIO3
AVSS1
AVSS2
Close to U24.5
31
EAPD
17
29
2
@ C331
22P_0402_50V8J~D
DVSS
B
<39> DOCK_HP_MUTE#
C619
0.1U_0402_10V6K~D
26
GPIO0
SPDIF_SHDN
R109
This signal must be under 1V.
STAC9200
2
<39> SPDIF_SHDN
2
@ R554
R22
<28>
1
<28,39> HP_NB_SENSE
HP_NB_SENSE
INT_MIC
2
1
ICH_AZ_CODEC_BITCLK
LINE_IN_R
16
STAC9200 Rev.
R291
20K_0402_1%~D
+VREFOUT
Close to U24.3
15
2
1
ICH_AC_SDIN0_R
2
33_0402_5%~D
LINE_IN_L
1
3
1
R284
AVDD
6
U24
<23> ICH_AZ_CODEC_RST#
<23> ICH_AZ_CODEC_SDIN0
@R285
22_0402_5%~D
2
2
DVDD
2
1
1
R290
39.2K_0402_1%~D
1
2
1
DOCK_HP_MUTE#
1
100K_0402_5%~D
2
R604
2
1
W=20 mil
3
+3.3V_RUN
1
C328
10U_0805_10V6M~D
C
C327
0.1U_0402_10V6K~D
C326
1U_0603_10V6K~D
W=30 mil
4
3
2
Title
Azalia (HD) Codec
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
27
of
59
3
2
1
C343
1
2
+VREFOUT
+VDDA
SGND
PGND
17
2
2
1
2
R305
10K_0402_5%~D
5
1
2
IN+
6
IN-
1
C356
0.1U_0402_10V6K~D
2
O
R306
10K_0402_5%~D
7
2
1
INT_MIC
HP_SPK_L1
1
1
2
HP_SPK_R1
2
1
L31
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
2
3
2
1
3
2
1
2
9
1
C369
4700P_0402_25V7K~D
LIN+
2
5
1
C371
4700P_0402_25V7K~D
LIN-
2
2
1
R293
4.7K_0402_5%~D
C366
0.1U_0402_10V6K~D
R310
1K_0402_5%~D
AUD_GAIN0
GAIN1
3
AUD_GAIN1
ROUT+
18
INT_SPK_R1
ROUT-
14
INT_SPK_R2
LOUT+
4
LOUT-
8
D
2
G
<27>
S
EAPD
Q21
2N7002W-7-F_SOT323~D
D
2
G
S
19
AUD_GAIN1
@ R312
1K_0402_5%~D
GAIN0
NC
12
BYPASS
10
@ Q79
2N7002W-7-F_SOT323~D
B
@ R311
1K_0402_5%~D
2
2
GAIN1
R313
1K_0402_5%~D
AV(inv)
INPUT
IMPEDANCE
0
0
6dB
90K ohm
0
1
10dB
70K ohm
1
0
15.6dB
45K ohm
1
1
21.6dB
25K ohm
BYPASS
SHUTDOWN
GND_T
GND1
GND2
GND3
GND4
1
SPK_SHUTDOWN#
3
1
NB_MUTE
3
<39>
C365
0.1U_0402_10V6K~D
AUD_GAIN0
GAIN0
RIN-
100K_0402_5%~D
A
2
R314
@ D25
SM24_SOT23~D
1
17
RIN+
21
20
13
11
1
2
+3.3V_RUN
C370
47P_0402_50V8J~D
2
INT_MIC+
INT_MIC-
1
7
RI N-
1
C364
10U_0805_10V6M~D
Gain Setting
1
1
1
C621
47P_0402_50V8J~D
1
C367
4700P_0402_25V7K~D
C368
2
1
2
1
2
U27
2
MIC1
C363
1U_0603_10V6K~D
+5V_AMPVCC
1
1
PC_BEEP
1
+5V_AMPVCC
2
<27>
4700P_0402_25V7K~D
2
SUYIN_010030FR006G103ZL~D
1
2
Speaker Connector
<27> AUD_LINE_OUT
@ C652
100P_0402_50V8J~D
5
7
8
2
2
GND
GND
2
WM-63PCY_2P~D
2
4
<27,39> HP_NB_SENSE
1
1
W=40mils
MOLEX_53780-0270~D
2 @
L32
1
2
+5V_SUS
BLM21PG600SN1D_0805~D
60ohm,3000mA,0.025ohm
+5V_AMPVCC
1
2
16
15
6
1
C362
1000P_0402_50V7K~D
C361
1000P_0402_50V7K~D
3
4
1
2
HP_SPK_R2
1
VDD
PVDD1
PVDD2
3
2
1
15 mils trace
2 @
JP8
1
2
6
3
HP_SPK_L2
JSPK1
1
2
B
C
120ohm,600mA,0.25ohm
L30
BLM11A121S_0603~D
2
1
@ D21
DA204U_SOT323~D
INT_SPK_R1
INT_SPK_R2
1
1
<27>
R309
1K_0402_5%~D
@ D20
DA204U_SOT323~D
SUYIN_010030FR006G103ZL~D
2
C355
0.1U_0402_10V6K~D
1
2
R307
100K_0402_5%~D
R308
1K_0402_5%~D
+5V_SUS
2
5
7
8
1
U25B
LM358DR2G_SOIC8~D
C
C358
2.2U_0603_6.3V6K~D
1
2
1
C625
0.1U_0402_10V6K~D
2
1
C354
0.1U_0402_10V6K~D
1
2
INT_MIC-
2
4
<27> MIC_SWITCH
MAX4411ETP+_TQFN20~D
1
C357
2.2U_0603_10V6K~D
@
D
+VDDA
R304
1K_0402_5%~D
INT_MIC+
2
C352
2.2U_0603_6.3V6K~D
1
2
@
2
NC-20
20
R303
100K_0402_5%~D
MIC_BIAS
1
2
R300
20K_0402_1%~D
16
R299
20K_0402_1%~D
2
1
12
NC-16
R302
1K_0402_5%~D
C359
100P_0402_50V8J~D
NC-12
1
8
PVSS
C1N
2
PVss
5
C1N
C353
2.2U_0603_10V6K~D
SVss
C1P
3
2
6
NC-8
+VDDA
R301
100K_0402_5%~D
1
7
C1P
1
NC-6
+3.3V_RUN
8
INL
4
JP7
1
2
6
3
P
13
NC-4
C347
2.2U_0603_6.3V6K~D
2
C360
100P_0402_50V8J~D
HP_SPK_L1
1
9
120ohm,600mA,0.25ohm
L28
BLM11A121S_0603~D
2
1
C346
MIC_R2
2
1 MIC_R1 1
2
2
1
R297
L29
4.99_0402_1%~D 2.2U_0603_6.3V6K~D
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
<27> NB_MICIN_R
G
INR
AUD_LINE_IN_L
2
OUTL
<27> NB_MICIN_L
1
4
15
C640
47P_0402_50V8J~D
C639
47P_0402_50V8J~D
2
2
Q80
2N7002W-7-F_SOT323~D
AUD_LINE_IN_R
1
IN-
O
2
SHDNL#
C351
1U_0603_10V6K~D
1
1
G
18
OUTR
HP_SPK_R1
4
SHDNR#
11
1
2
14
R295
C345
4.99_0402_1%~D 2.2U_0603_6.3V6K~D
MIC_L2
2
1 MIC_L1 1
2
2
1
<27> HP_OUT_L
3
1
3
C350
1U_0603_10V6K~D
1
2
<27> HP_OUT_R
IN+
R298
100K_0402_5%~D
D
NB_MUTE 2
G
U25A
LM358DR2G_SOIC8~D
MIC_BIAS
SVDD
1
HP_NB_SENSE
R294
100K_0402_5%~D
C344
1U_0603_10V6K~D
10
19
U26
D
PVDD
2
2
+VDDA
+3.3V_RUN
P
1
R296
100K_0402_5%~D
2
600ohm,100mA
8
1
1
1
L27
BLM11A601S_0603~D
+3.3V_RUN
S
1000P_0402_50V7K~D
R292
4.7K_0402_5%~D
2
1
+3VRUN_4411
C349
100P_0402_50V8J~D
4
C348
100P_0402_50V8J~D
5
1
TPA6017A2PWP_TSSOP20~D
2
C372
*
0.47U_0402_16V4Z~D
A
DELL CONFIDENTIAL/PROPRIETARY
Note:
C343,C344,C345,C346,C350,C351,C353,C354,C355,C356,C357 use
Temp. characteristics: X5R
Operating range: -55~+85degree
5
4
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
AMP and PHONE JACK
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
28
of
59
4
3
Layout Notice : 1.2V filter. Place as close
chip as possible.
Q24
MMJT9435T1G_SOT223~D
1
M9
1
XTALI
REGSEN25
M12
0
0
1
SO
SI
1
0
1
0
1
@
2
@
PCIE_IRX_LOMTX_P3_C 1
0.1U_0402_16V4Z~D
PCIE_RXDN
L7
PCIE_ITX_LOMRX_N3_C <24>
PCIE_RXDP
M7
PCIE_ITX_LOMRX_P3_C <24>
B5
F3
B4
E3
D4
J1
M4
C6
RDAC
A8
CS#
SCLK
1
1
0
1
4
PCIE_IRX_LOMTX_N3 <24>
2
1
BLM11A601S_0603~D
600ohm,100mA
C403
0.1U_0402_16V4Z~D
PCIE_IRX_LOMTX_P3 <24>
@ R333
4.7K_0402_5%~D
1
2
1
@ R335
1
R336
1
@ R337
U29
D
C
RESET#
S#
+3.3V_LAN
1
2
3
4
+3.3V_LAN
U30
2
8
7
6
5
SO
GND
VCC
WP#
K4
+2.5V_BIASVDD +2.5V_BIASVDD
SI
SCK
RESET#
CS#
A12
BIASVDD
F10
F11
AVDDL_0
AVDDL_1
+2.5V_AVDD
A11
F12
AVDD_0
AVDD_1
2
+2.5V_AVDD
BIAS
Analog
power
1
K6
+1.2V_PCIE_PLLVDD
+1.2V_GPHY_PLLVDD
G12
PCIE_PLLVDD
PLL
GPHY_PLLVDD
1
2
3
4
+1.2V_AVDDL
1
2
LOM_SO
LOM_SCLK
LOM_CS#
C405
0.1U_0402_16V4Z~D
C407
0.1U_0402_16V4Z~D
+1.2V_PCIE_PLLVDD
R341
2
1
BLM11A601S_0603~D 1
@ C412
4.7U_0603_6.3V6M~D
+1.2V_PCIE_SDS_VDD
2
C383
0.1U_0402_16V4Z~D
C
BCM5752_K5
B
2
@ R601
1
0_0402_5%~D
@ C413
0.1U_0402_16V4Z~D
+3.3V_LAN
BCM5752_K5
@ R600
39K_0402_5%~D
C411
0.1U_0402_16V4Z~D
1
2
D
1
@ R599
20K_0402_5%~D
1
2
1
2
LOM_LOW_PWR
1
L38
2
1
BLM11A601S_0603~D 1
600ohm,100mA
C410
4.7U_0603_6.3V6M~D
2
2
BCM5752KFBG A2_FPBGA144~D
<6> LOM_CLKREQ#
+1.2V_GPHY_PLLVDD
2
C382
0.1U_0402_16V4Z~D
C380
0.1U_0402_16V4Z~D
C379
0.1U_0402_16V4Z~D
C378
0.1U_0402_16V4Z~D
C381
0.1U_0402_16V4Z~D
A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
E2
F2
G1
G2
G9
H1
H2
H10
J10
K1
K2
K3
K5
K7
K8
K10
K11
L4
L8
M8
PCIE_SDSVDD
+1.2V_AVDDL
1
L37
2
1
BLM11A601S_0603~D 1
600ohm,100mA
C406
4.7U_0603_6.3V6M~D
2
@ M45PE20-VMN6TP_SO8~D
LOM_SI
H12
L36
2
1
BLM11A601S_0603~D 1
600ohm,100mA
C404
4.7U_0603_6.3V6M~D
2
2
4.7K_0402_5%~D
2
4.7K_0402_5%~D
2
0_0402_5%~D
Q
VSS
VCC
W#
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
+1.2V_LOM
+3.3V_LAN
8
7
6
5
XTALVDD
+2.5V_XTALVDD
+1.2V_PCIE_SDS_VDD
2
1
B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6
1
L35
PCIE_WAKE#
PCIE_WAKE# <36,39>
CLK_PCIE_LOM#
CLK_PCIE_LOM# <6>
CLK_PCIE_LOM
CLK_PCIE_LOM <6>
1
2
@ R332
4.7K_0402_5%~D
PLTRST#
PLTRST#
<10,20,22,24,36>
C414
0
NV_STRAP0
2
1
BLM11A601S_0603~D
600ohm,100mA
C400
0.1U_0402_16V4Z~D
+2.5V_LOM
M3
TCK
TDI
TDO
TMS
TRST
SERIAL_DI
SERIAL_DO
GPHY_TVCOI
VDDP_0
VDDP_1
VDDP_2
+2.5V_XTALVDD
2
2
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
L34
L3
B1
A5
G3
L11
GND
+2.5V_LOM
2
1
BLM11A601S_0603~D
600ohm,100mA
C399
0.1U_0402_16V4Z~D
PCIE_TXDP
PERST
VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
L33
PCIE_TXDN
A4
L5
M5
B3
A3
C2
D10
F1
G10
J2
L1
L12
+2.5V_LOM
PCIE_IRX_LOMTX_N3_C 1
0.1U_0402_16V4Z~D
WAKE
REFCLKREFCLK+
REFCLK_SEL
1
Digial power
2
+1.2V_LOM
2
C401
2
C402
1
2
1
Regulator
Control
REGCTL25
M11 REGCTL_PNP25
+3.3V_LAN
LOM_LOW_PWR <39>
+3.3V_LAN
+3.3V_RUN
+3.3V_LAN
REGCTL_PNP12
0.1U_0402_16V4Z~D
5
J12
Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC
NV_STRAP1
ST M45PE20
REGSEN12
BCM5752KFBG A2_FPBGA144~D
A
Atmel AT45BCM021B
K12
J11
Bias
2
L9
27P_0402_50V8J~D
1
C409
C408
2
27P_0402_50V8J~D
25MHZ_18PF_1BX25000CK1D~D
X3
XTALI
1
2
XTALO
Clock
XTALO
1
330_0402_5%~D
2
R334
REGSUP12
REGCTL12
2
1
2
BCM5752
VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
2
LAN_ACT#
LAN_ACT#
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED
LOM_LOW_PWR
1
0_0402_5%~D
1
1 4.7K_0402_5%~D
1K_0402_5%~D
1
1K_0402_5%~D
2
R603
2
R322 2
R323
2
R325
1
2
U28B
D5
D6
D7
D8
H5
H6
H8
J4
2
A9
B9
A10
B8
B6
C398
22P_0402_50V8J~D
1
LINK_10#
LINK_100#
LED
<30>
LINK_10#
LINK_100#
SCLK
SI
SO
CS
NV_STRAP0
NV_STRAP1
VAUXPRSNT
H4
A2
G11
1
R340
4.7K_0402_5%~D
@ R330
4.7K_0402_5%~D
1
2
1
2
@ R331
4.7K_0402_5%~D
ATTN_BTTN
VMAINPRSNT
2
2
C9
E10
D9
C10
M2
M1
SPI
LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#
SMB_CLK
SMB_DATA
SMBUS
+3.3V_LAN
GPIO
C8
C7
<6,24,36> ICH_SMBCLK
<6,24,36> ICH_SMBDATA
<30>
<30>
GPIO0
GPIO1
GPIO2
GPIO3
PCI-E
H9
H11
C5
C4
<39> LOM_CABLE_DETECT
B
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2
TPM_EN
TEST
2
R324
LOW_PWR
G4
J3
H3
J6
Power
Control
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2
1 TPM_EN#
0_0402_5%~D
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
R339
4.7K_0402_5%~D
2
1
LFRAME
LRESET
SERIRQ
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
R620
@ 4.7K_0402_5%~D
2
1
J9
M10
H7
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
1
2
R338
1.18K_0402_1%~D
LPC_LFRAME#
PLTRST#
IRQ_SERIRQ
Media
LAD0
LAD1
LAD2
LAD3
B11
B12
C11
C12
D11
D12
E11
E12
1
C397
J7
L10
J5
K9
TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-
+1.2V_LOM
0.1U_0402_16V4Z~D
<39> LOM_TPM_EN#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
C396
<23,39,40> LPC_LFRAME#
<10,20,22,24,36> PLTRST#
<24,31,39,40> IRQ_SERIRQ
LCLK
LPC/TPM
C
J8
+2.5V_LOM
CLK_PCI_LOM
R321
33_0402_5%~D
BCM5752
CLK_PCI_LOM
<6> CLK_PCI_LOM
2
1
2
Place closely pin J8
0.1U_0402_16V4Z~D
2
1
C392
C395
2
1
10U_0805_10V4Z~D
1
0.1U_0402_16V4Z~D
2
U28A
<23,39,40> LPC_LAD[0..3]
C391
2
C393
470P_0402_50V7K~D
C394
@
1
+1.2V_LOM
1
TPM_GPIO0
2
10K_0402_5%~D
TPM_GPIO1
2
10K_0402_5%~D
TPM_GPIO2
2
10K_0402_5%~D
TPM_EN#
2
4.7K_0402_5%~D
1
R328
1
R327
1
R326
1
R329
+2.5V_LOM
2
2
1
REGCTL_PNP12
2
Q23
MMJT9435T1G_SOT223~D
1
1
C710
0.1U_0402_16V4Z~D
2
C377
0.1U_0402_16V4Z~D
2
3
R316
2_1210_5%~D
2
1
R315
2
2
3
1
2
4
C390
0.1U_0402_16V4Z~D
C389
0.1U_0402_16V4Z~D
C388
0.1U_0402_16V4Z~D
C387
0.1U_0402_16V4Z~D
C386
4.7U_0603_6.3V6M~D
G
3
Rc, Rd are 1/2 W rating
2_1210_5%~D
S
1
2
1
D
1
2
R640
2K_0402_5%~D
REGCTL_PNP25 1
2
+1.2V_LOM
10U_0805_10V4Z~D
C726
4700P_0402_25V7K~D
1
2
1
0.1U_0402_16V4Z~D
2
1
2
1
C385
1
2
Rd
C384
<42> ENAB_3VLAN
Rc
+3.3V_LAN
1
C375
4
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
6
5
2
1
D
1
4.7U_0603_6.3V6M~D
+3.3V_LAN
E
3
C374
C
4
+3.3V_LAN
0.1U_0402_16V4Z~D
B
1
Q22
SI3456DV-T1-E3_TSOP6~D
1
2
4
Layout Notice : Place as close
chip as possible.
+3.3V_SRC
2
MMJT9435
C
2
C376
0.1U_0402_16V4Z~D
5
Follow Travis to add that
Broadcom will be update for
next version.
Follow M07 schematic
Pop R341 to use BLM11A601S
If noise margin on SDSVDD so that
pop C412,C413
A
AT45BCM021B-SU_SO8~D
DELL CONFIDENTIAL/PROPRIETARY
1
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
BCM5751M
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
29
of
59
4
1
2 0.1U_0402_16V4Z~D
C416
1
2 0.1U_0402_16V4Z~D
C417
1
2 0.1U_0402_16V4Z~D
C418
1
2 0.1U_0402_16V4Z~D
R342
R343
R344
R345
R346
R347
R348
R349
1
1
1
1
1
1
1
1
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
48.7_0402_1%~D
2
2
2
2
2
2
2
2
2
LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+
1
LAN ANALOG
SWITCH
+3.3V_LAN
56
50
38
27
18
10
4
C415
3
U31
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
5
<29>
LAN_TX0-
<29>
LAN_TX0+
<29>
LAN_TX1-
<29>
LAN_TX1+
<29>
LAN_TX2-
<29>
LAN_TX2+
<29>
LAN_TX3-
<29>
LAN_TX3+
0B1
1B1
48
47
SW_LAN_TX0SW_LAN_TX0+
A1
2B1
3B1
43
42
SW_LAN_TX1SW_LAN_TX1+
7
A2
4B1
5B1
37
36
SW_LAN_TX2SW_LAN_TX2+
8
A3
6B1
7B1
32
31
SW_LAN_TX3SW_LAN_TX3+
LAN_TX2LAN_TX2-R
1
2
L43
39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX2+ 1
LAN_TX2+R
2
L44
39NH_ 0603CS-390EJTS_5%_2P~D
11
A4
12
A5
0LED1
1LED1
2LED1
22
23
52
LAN_LEDACT#
LINK_LED10#
LINK_LED100#
LAN_TX3LAN_TX3-R
1
2
L45
39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX3+ 1
LAN_TX3+R
2
L46
39NH_ 0603CS-390EJTS_5%_2P~D
14
A6
0B2
1B2
46
45
DOCK_LAN_TX0DOCK_LAN_TX0+
15
A7
2B2
3B2
41
40
DOCK_LAN_TX1DOCK_LAN_TX1+
DOCKED
17
SEL
4B2
5B2
35
34
DOCK_LAN_TX2DOCK_LAN_TX2+
19
20
54
LED0
LED1
LED2
6B2
7B2
30
29
DOCK_LAN_TX3DOCK_LAN_TX3+
0LED2
1LED2
2LED2
25
26
51
DOCK_LAN_ACTLED_YEL#
DOCK_LED_10#
DOCK_LED_100#
LAN_TX0LAN_TX0-R
1
2
L39
39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX0+ 1
LAN_TX0+R
2
L40
39NH_ 0603CS-390EJTS_5%_2P~D
2
3
LAN_TX1LAN_TX1-R
1
2
L41
39NH_ 0603CS-390EJTS_5%_2P~D
LAN_TX1+ 1
LAN_TX1+R
2
L42
39NH_ 0603CS-390EJTS_5%_2P~D
A0
D
Layout Notice : Place
termination as close as
ASIC as possible
The resistors need at
least 1/16W
<38,39> DOCKED
<29> LAN_ACT#
<29> LINK_10#
<29> LINK_100#
Layout Notice : Place bead as
close PI3L500 as possible
DOCK_LAN_TX1- <38>
DOCK_LAN_TX1+ <38>
DOCK_LAN_TX2- <38>
DOCK_LAN_TX2+ <38>
DOCK_LAN_TX3- <38>
DOCK_LAN_TX3+ <38>
DOCK_LAN_ACTLED_YEL# <38>
DOCK_LED_10# <38>
DOCK_LED_100# <38>
NC
1
FROM NIC
2
L66
BLM11A601S_0603~D
DOCKED
57
1
6
9
13
16
21
24
28
33
39
44
49
53
55
+2.5V_LOM
1: TO DOCK
PI3L500E_TQFN56~D
TO
DOCK
C
0: TO RJ45
TR8
MX1-
22
NB_LAN_TX0+
MCT2
21
Z2806
MX2+
20
NB_LAN_TX1NB_LAN_TX0+
1
PR1+
NB_LAN_TX1+
NB_LAN_TX0-
2
PR1-
LAN_ACTLED_YEL_R#
+3.3V_LAN
3
PR2+
SW_LAN_TX2- 8
TD3+
MX3+
17
NB_LAN_TX2-
NB_LAN_TX2+
4
PR3+
NB_LAN_TX2-
5
PR3-
NB_LAN_TX1-
6
PR2-
NB_LAN_TX3+
7
PR4+
NB_LAN_TX3-
8
PR4-
1:1
C421
0.1U_0402_10V6K~D
SW_LAN_TX2+ 9
TD3-
MX3-
16
NB_LAN_TX2+
10
TCT4
MCT4
15
Z2808
SW_LAN_TX3-11
TD4+
MX4+
14
NB_LAN_TX3-
MX4-
13
NB_LAN_TX3+
<38>
1
C423
R360 2
R359 2
R358 2
R357 2
JP9
GND
CHASIS
2
1000P_1808_3KV7K~D
1
2
1
2
GND
GND
3
4
L47
FBMA-L11-160808-301LMA20T_2P~D
RJ_TIP_L
RJ_TIP
2
1
RJ_RING_L
R J_RING
2
1
L48
FBMA-L11-160808-301LMA20T_2P~D
2
2
MOLEX_53780-0270~D
<38> RJ_RING_L
1
1
1
14
NC
12
A2
13
FOX_JM36113-P2651-7F~D
LAN_LEDACT#
1
R354
LAN_ACTLED_YEL_R#
2
150_0402_5%~D
LINK_LED10#
1
R355
LED_10_GRN_R#
2
150_0402_5%~D
LINK_LED100#
1
R356
LED_100_ORG_R#
2
150_0402_5%~D
RJ_TIP_L
@
C642
300P_1808_3000V8K~D
TD4H5015NLT_24P~D
A
11
C422
0.1U_0402_10V6K~D
SW_LAN_TX3+12
LAN_ACT#
LINK_10#
LINK_100#
B
15
1:1
@R353
2
NB_LAN_TX1+
@R352
2
Z2807
10K_0402_5%~D
18
10K_0402_5%~D
MCT3
@R351
2
TCT3
LED_YELLOW-
7
SHLD2
MX2-
SHLD1
TD2-
19
LED_YELLOW+
JP2
SW_LAN_TX1+ 6
LDE_ORANGE-
C420
0.1U_0402_10V6K~D
16
TD21+
1:1
9
TCT2
10
TD1-
4
SW_LAN_TX1- 5
+3.3V_LAN
LED_10_GRN_R#
LED_100_ORG_R#
LDE_GREEN-
SW_LAN_TX0+ 3
75_0402_1%~D
2
NB_LAN_TX0-
C419
0.1U_0402_10V6K~D
75_0402_1%~D
1
Z2805
23
1
2
B
24
MX1+
75_0402_1%~D
1
MCT1
1
2
1:1
75_0402_1%~D
1
TD1+
1
2
TCT1
1
1
1
SW_LAN_TX0- 2
10K_0402_5%~D
TRM_CT
C641
300P_1808_3000V8K~D
C
DOCK_LAN_TX0- <38>
DOCK_LAN_TX0+ <38>
GND P
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
5
D
1 @
JPHON1
1
2
3
4
1
2
GND1
GND2
FOX_JM74613-P2002-7F~D
1
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
LAN TRANSFOMER
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
30
of
59
5
4
2 100K_0402_5%~D
INTA#
INTB#
INTC#
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#
T14
D15
R16
H16
CBS_CCD1#_R5C843
CBS_CCD2#_R5C843
CBS_CVS1
CBS_CVS2
J4
H1
H2
H4
H5
G1
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
RESERVED/CDATA14
RESERVED/CDATA2
RESERVED/CADR18
W18
C19
N16
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
G4
F1
F2
F4
RI_OUT#/PME#
SPKROUT
HWSPND#
TEST
TPBP0
TPBN0
B10
A10
TPAP1
TPAN1
B11
A11
TPBP1
TPBN1
<32>
<32>
<32>
<32>
D12
D10
TPBIAS0
TPBIAS1
D13
B14
VREF
REXT
IEEE1394_TPBIAS0
2
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
1
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>Close
CBS_CCLKRUN# <32>
2
1
R365
22_0402_5%~D
USB_HUBP1+ V14
USB_HUBP1- W14
<32,39> USB_HUBP1+
<32,39> USB_HUBP1VPPEN0
VPPEN1
<32>
<32>
VCC5EN#
VCC3EN#
R13
T13
VCC5EN#
VCC3EN#
R7
REGEN#
<32>
<32>
2
C717
2
C718
2
C719
2
C720
VPPEN0
VPPEN1
R5C843-CSP208P_CSP208~D
CLK_SD_48M
SD_CLK
C428 Close Cardbus connector
@
@
CBS_CCD1#_R5C843 <32>
CBS_CCD2#_R5C843 <32>
CBS_CVS1
<32>
CBS_CVS2
<32>
CBS_RSVD/D14 <32>
CBS_RSVD/D2 <32>
CBS_RSVD/A18 <32>
+3.3V_RUN_CARD
1
2
2
Z3008
R385
1
5
5
3
2
6
7
6
7
1
8
8
4
J1
TPA0+
TPA0TPB0+
TPB0-
R382
2
1 0_0402_5%~D
R383
2
1 0_0402_5%~D
R384
2
1 0_0402_5%~D
R386
2
1 0_0402_5%~D
6
5
4
3
2
1
2
GND
GND
A+
AB+
B-
ON/OFF#
OUT
GND
N.C
1
AAT4250IGV-T1_SOT23-5~D
2
Close to JP5 pin5
1
2
Close to JP5 pin5
FOX_UV31413-4TA-7F~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Close to J1
Close to U32
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
CardBus Controller(R5C843)
Size
4
3
2
Document Number
Rev
1.0
LA-3071P
Date:
5
1
2
3
R618
150K_0402_5%~D
3
2
IN
C432
1U_0603_10V4Z~D
1
2
4
4
1
C683
0.1U_0402_16V4Z~D
1
2
1
2
1
2
SD_EN
@ L49
857CM-0009~D
5.1K_0402_1%~D
C437
1
270P_0402_50V7K~D
2
R381
2
1
1
2
2
56.2_0402_1%~D
R380
CK33M_CBS_TERM
1
0.33U_0603_10V7K~D
C433
R377
2
C434
0.01U_0402_16V7K~D
1
5
1
56.2_0402_1%~D
2
56.2_0402_1%~D
R376
1U_0603_10V4Z~D
C435
1
4.7P_0402_50V8C~D
C436
2
1
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
CBUS_GRST#
B
U33
56.2_0402_1%~D
100K_0402_5%~D
R379
10_0402_5%~D
R378
A
+3.3V_R5C843
@
2
R5C843-CSP208P_CSP208~D
+3.3V_R5C843
@
@
1
IEEE1394_TPBIAS0
CLK_PCI_PCCARD
<32>
SD_EN
1
0_0402_5%~D
1 CLK_SD_48M
CLK_SD_48M <6>
0_0402_5%~D
SD_CMD
<32>
1
SD_CLK
<32>
1 33_0402_5%~D
SD_DATA0 <32>
1 33_0402_5%~D
SD_DATA1 <32>
1 33_0402_5%~D
SD_DATA2 <32>
1 33_0402_5%~D
SD_DATA3 <32>
33_0402_5%~D
1
100P_0402_50V8J~D
1
100P_0402_50V8J~D
1
100P_0402_50V8J~D
1
100P_0402_50V8J~D
C
<32>
<32>
CBS_CCLK
2
@ R609
2
R606
2
R594 2
R645 2
R646 2
R647 2
R648
USBDP
USBDM
V13
W13
to U32.D13,B14
<32>
SD_WP#
1
F19
B13
A13
SD_DET#
2
J2
K4
K2
TPAP0
TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
1
CAUDIO/BVD2(SPKR#/LED)
CBS_CRST#
CBS_CRST#
<32>
1
2
C428
0.01U_0402_16V7K~D
CBS_CAUDIO
CBS_CAUDIO <32>
Close to U32.A14
1
H19
2
CRST#/RESET
B12
A12
B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
CK48M_SD
PCICLK
PCIRST#
GBRST#
CLKRUN#
IEEE1394_TPAP0
IEEE1394_TPAN0
R5C843
2
K1
L4
G2
L5
XI
XO
FIL0
2
C426
0.01U_0402_16V7K~D
CBS_CPAR <32>
CBS_CINT#
1
CBS_CINT#
CPS
A16
B16
A14
C431
0.1U_0402_16V4Z~D
R374 1
M18
1
D11
R5C843XI
R5C843XO
4.7P_0402_50V8C~D
@ R595 2
<39> CB_HWSPND#
+3.3V_R5C843
1 0_0402_5%~D
CBS_SPK
1 0_0402_5%~D
CINT#/RDY(IREQ#)
D
U32B
10_0402_5%~D
@ R593 2
<37,39> SYS_PME#
REQ#
GNT#
T16
+3.3V_RUN_PHY
C653
2 10K_0402_5%~D
CBS_CFRAME#
CBS_CTRDY#
C BS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_INTERNAL
PAD~D
R607
R373 1
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
MDIO06
Close to U32.A16,B16
R366
100K_0402_5%~D
2 10K_0402_5%~D
2 10K_0402_5%~D
CFRAME#/CADR23
CTRDY#/CADR22
CIRDY#/CADR15
CSTOP#/CADR20
CDEVSEL#/CADR21
RESERVED/CADR19
CPERR#/CADR14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/CADR16
R5C843XO
1
0_0402_5%~D
2
R617
R364
+3.3V_R5C843
B
R371 1
R372 1
CBS_CPAR
1
2
PERR#
SERR#
<22> PCI_PIRQD#
<22> PCI_PIRQB#
<22> PCI_PIRQC#
<24,29,39,40> IRQ_SERIRQ
+3.3V_R5C843
N15
C425
2
C424, C425 need to
test the starting
vaule, then modify
the value
18P_0402_50V8J~D
1
W5
T6
0_0402_5%~D
CPAR/CADR13
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
X4
24.576MHz_16P_1BG24576CKIA~D
2
PCI_PERR#
PCI_SERR#
CLK_PCI_PCCARD
PCI_RST#
CBUS_GRST#
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
R5C843XI
1
100K_0402_5%~D
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
M4
M5
F16
K18
P15
V19
PAR
V3
W4
V4
V5
T5
P1
PCI_REQ2#
PCI_GNT2#
CC/BE3#/REG#
CC/BE2#/CADR12
CC/BE1#/CADR8
CC/BE0#/CE1#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
CBS_CAD13
2
18P_0402_50V8J~D
R363
<6> CLK_PCI_PCCARD
<22,35,37> PCI_RST#
<39> CBUS_GRST#
2
1
C424
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <32>
CBS_CAD14 <32>
CBS_CAD13 <32>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
100K_0402_5%~D
<22> PCI_REQ2#
<22> PCI_GNT2#
CBS_CAD15
R5C843
PCI_FRAME#
PCI_TRDY#
PCI _IRDY#
PCI_STOP#
PCI_DEVSEL#
CBS_IDSEL
R362
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
R361
10K_0402_5%~D
2
<22,37> PCI_PERR#
<22,37> PCI_SERR#
V6
CAD31/CDATA10
CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0
CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6
CAD19/CADR25
CAD18/CADR7
CAD17/CADR24
CAD16/CADR17
CAD15/IOWR#
CAD14/CADR9
CAD13/IORD#
CAD12/CADR11
CAD11/OE#
CAD10/CE2#
CAD9/CADR10
CAD8/CDATA15
CAD7/CDATA7
CAD6/CDATA13
CAD5/CDATA6
CAD4/CDATA12
CAD3/CDATA5
CAD2/CDATA11
CAD1/CDATA4
CAD0/CDATA3
C427
0.01U_0402_16V7K~D
PCI_PAR
<22,37,38> PCI_FRAME#
<22,37> PCI_TRDY#
<22,37,38> PCI_IRDY#
<22,37> PCI_STOP#
<22,37> PCI_DEVSEL#
PCI_AD17
1
100_0402_5%~D
R367 1
P2
W2
W6
T9
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
<22,37> PCI_PAR
<24,39,40> CLKRUN#
M2
M1
N5
N4
N2
N1
P5
P4
R4
R2
R1
T2
T1
U2
U1
V1
T7
V7
W7
R8
T8
V8
W8
R9
V9
W9
T11
V11
W11
T12
V12
W12
2
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
D
C
2
U32A
<22,37> PCI_AD[0..31]
<22,37>
<22,37>
<22,37>
<22,37>
3
Friday, May 12, 2006
Sheet
1
31
of
59
3
2
1
+3.3V_RUN_PHY
R5C843
2
EN0
EN1
2
1
VPPEN0
VPPEN1
<31>
VCC5EN#
1
2
FLG
GND
NC
NC
NC
2
G
3
1A 1B
7
EXUSB_EN#_CCD
EXUSB_EN#
U64
NC7SZ04P5X_NL_SC70-5~D
CBS_CCD2# 5
CBS_CCD1#_R5C843
3
U65B
2A 2B
6
CBS_CCD2#_R5C843
CBS_CCD2#_R5C843 <31>
SN74CB3Q3306APWR_TSSOP8~D
CBS_CCD1#_R5C843 <31>
G
SN74CB3Q3306APWR_TSSOP8~D
1
2
R659
10K_0402_5%~D
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
2
@ R654
C
1
0_0402_5%~D
1
1
IN1
2
IN2
CBS_CAD13 2
4VCC3EN#_R5531
74AHC1G08GW_SOT353-5~D
1
0_0402_5%~D
+3.3V_R5C843
EXUSB_EN#
<39>
8
EXUSB_EN#
U63A
P
1OE
1
3
USB_HUBP1+
USB_HUBP1+ <31,39>
<31,39> USB_HUBP1-
USB_HUBP1- 5
2A 2B
SN74CB3Q3306APWR_TSSOP8~D
4
4
G
1A 1B
+3.3V_R5C843
U63B
6
EXUSB_EN# 1
2
R652
10K_0402_5%~D
CBS_CAD15
G
C716
0.1U_0402_16V4Z~D
R5C843-CSP208P_CSP208~D
2
@ R656
EXUSB_EN#
2
2
C715
0.1U_0402_16V4Z~D
U62
O
3
VCC3EN#
+3.3V_R5C843
1
2
1
@ R655
0_0402_5%~D
7
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
+3.3V_R5C843
2OE
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
5
A9
B9
D9
D14
A15
B15
8
2
Close to JCBUS1 pin22,62
+3.3V_R5C843
P
1
2
D
G
P
C723
0.1U_0402_16V4Z~D
CBS_CCD1#
A
U65A
1
2
8
1
Y
8
AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4
4
2
2
+3.3V_R5C843
2
C722
0.1U_0402_16V4Z~D
P
E10
E11
A17
B17
EXUSB_EN#_CCD
7
6
10
1
2
R5531V002-E2-FA_SSOP16~D
2OE
VCC_ROUT1
VCC_ROUT2
8
VCC3_EN
VCC5_EN
5
16
<31>
<31>
VPPOUT
1
C708
10U_0805_10V4Z~D
3
4
1
1
P
2
+3.3V_RUN_PHY
0.47U_0603_16V4Z~D
2
C461
0.47U_0603_16V4Z~D
2
C460
0.01U_0402_16V7K~D
C458
C459
0.01U_0402_16V7K~D
2
1
2
CBS_VPP
4
L1
E14
1
1
VCC_RIN1
VCC_RIN2
5
R6
E13
+3.3V_R5C843
<31>
1
VCC5IN
VCC5IN
+5V_RUN
9
14
12
G
C
1
13
15
VCCOUT
VCCOUT
VCCOUT
1
4
2
1
0.01U_0402_16V7K~D
1
C457
0.01U_0402_16V7K~D
2
C456
0.1U_0402_16V4Z~D
C455
10U_0805_10V4Z~D
C454
1
VCC3IN
P
VCC_MD3V
1OE
+3.3V_R5C843
1
2
CBS_VCC
11
VCC3EN#_R5531
A4
+3.3V_R5C843
2
2
1
C465
0.1U_0402_16V4Z~D
VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3
L2
C1
D1
E1
C2
D2
E2
E4
E12
2
1
C462
0.1U_0402_16V4Z~D
W3
R11
R12
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
1
C451
1000P_0402_50V7K~D
VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4
2
C450
1000P_0402_50V7K~D
C447
10U_0805_10V4Z~D
U32C
F5
G5
J19
K19
2
1
U34
0.01U_0402_16V7K~D
C684
2
1
0.01U_0402_16V7K~D
C449
2
1
0.01U_0402_16V7K~D
2
1
C442
0.01U_0402_16V7K~D
C707
1
2
C441
0.01U_0402_16V7K~D
2
2
1
0.01U_0402_16V7K~D
2
1
1
C440
0.01U_0402_16V7K~D
1
0.01U_0402_16V7K~D
C453
0.01U_0402_16V7K~D
2
C446
0.01U_0402_16V7K~D
2
C445
0.01U_0402_16V7K~D
C443
C444
10U_0805_10V4Z~D
2
1
C439
10U_0805_10V4Z~D
C438
1
2
+3.3V_R5C843
1
+3.3V_R5C843
2
BLM21A601SPT_0805~D
2
0_0805_5%~D
D
1
1
+3.3V_R5C843
0.01U_0402_16V7K~D
C448
1
R592
Close to U32
L50
+3.3V_R5C843 +3.3V_R5C843
NC
+3.3V_RUN
C467
0.01U_0402_16V7K~D
4
C466
0.1U_0402_16V4Z~D
5
SN74CB3Q3306APWR_TSSOP8~D
C429, C430 Close Cardbus connector
+UIM_VPP
<36> UIM_DATA
<36> UIM_RESET
<36>
UIM_CLK
<31> CBS_CRST#
<31> CBS_CVS2
+SC_PWR
<35> SC_IO_R
<31> CBS_CFRAME#
<31> CBS_CTRDY#
<35>
SCCDCBS_VPP
CBS_VCC
<31> CBS_CDEVSEL#
<31> CBS_CSTOP#
<31> CBS_CBLOCK#
<31> CBS_RSVD/A18
USB signal,impedance
90ohm,trace
width/space=5/6
3
2
<31> CBS_CAUDIO
<31> CBS_CC/BE3#
<31> CBS_CREQ#
<31> CBS_CSERR#
HRS_FH12-40(19)SA-1SH(55) ~D
2
2
1
C506
33P_0402_50V8J~D
2
C505
33P_0402_50V8J~D
2
1
1
<31> CBS_CVS1
@ D12
<31> CBS_RSVD/D14
NNCD5.6LG~D
2
5
A
1
1
C504
1U_0603_10V4Z~D
+SIM_PWR
1
C508
33P_0402_50V8J~D
C507
33P_0402_50V8J~D
+SIM_PWR
<31> CBS_CSTSCHNG
CBS_CCD2#
CBS_CAD31
CBS_CAD30
CBS_CAD28
CBS_CSTSCHNG
CBS_CAUDIO
CBS_CC/BE3#
CBS_CREQ#
CBS_CSERR#
CBS_CRST#
CBS_CVS2
CBS_CAD19
CBS_CAD17
CBS_CFRAME#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CBLOCK#
CBS_RSVD/A18
CBS_CAD16
CBS_CAD15
CBS_CAD13
CBS_CVS1
CBS_CAD10
CBS_CAD8
CBS_RSVD/D14
CBS_CAD6
CBS_CAD4
CBS_CAD2
CBS_CCD1#
1
2
JCBUS1
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
CBS_CCLKRUN#
CBS_RSVD/D2
CBS_CAD29
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD18
CBS_CC/BE2#
C BS_CIRDY#
CBS_CCLK
CBS_CINT#
CBS_CGNT#
CBS_CPERR#
CBS_CPAR
CBS_CC/BE1#
CBS_CAD14
CBS_CAD12
CBS_CAD11
CBS_CAD9
CBS_CC/BE0#
CBS_CAD7
CBS_CAD5
CBS_CAD3
CBS_CAD1
CBS_CAD0
FOX_QTS0080A-1021-9F~D
@ C430
270P_0402_50V7K~D
SIM & SD CARD will combine together,
the connector will update to 18pin
CBS_CCLKRUN# <31>
CBS_RSVD/D2 <31>
B
SC_DET#
+SC_PWR
SC_RST#_R
3
CBS_VCC
1
2
CBS_CC/BE0# <31>
1
2
1
2
A
Close to JCBUS1 pin23,63
DELL CONFIDENTIAL/PROPRIETARY
Title
CardBus/SD card Socket
Size
2
Document Number
Rev
1.0
LA-3071P
Date:
4
<35>
CBS_CC/BE2# <31>
SC_CLK_R
<35>
CBS_CIRDY# <31>
CBS_CCLK <31>
SCCD+
<35>
CBS_VPP
CBS_VCC
CBS_CINT# <31>
CBS_CGNT# <31>
CBS_CPERR# <31>
CBS_CPAR <31>
CBS_CC/BE1# <31>
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
<35,39>
C464
10U_0805_10V4Z~D
<31> SD_CMD
<31> SD_DATA3
<31> SD_DATA2
<31> SD_DET#
<31> SD_WP#
<39> CBS_CCD2#
C463
0.01U_0402_16V7K~D
<31> SD_CLK
B
<31> CBS_CAD[0..31]
C709
0.01U_0402_16V7K~D
SD_DATA1
SD_DATA0
1
2
@C429
270P_0402_50V7K~D
4
<31>
<31>
+3.3V_RUN_CARD JP5
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
SD_WP#
11 11
12 12
13 13
+UIM_VPP
14 14
UIM_DATA
15 15
UIM_RESET
16 16
UIM_CLK
17 17
18 18
19 19
20 GND
21 GND
Friday, May 12, 2006
Sheet
1
32
of
59
5
USBP4-
@ L53 DLW21SN900SQ2_0805~D
4 4
3 3
USBP4-
1
1
D
<24>
USBP6+
<24>
USBP6-
<24>
USBP5+
<24>
USBP5-
USBP6+
2
R393
0_0402_5%~D
1
2
R394
0_0402_5%~D
1
2
@ L56 DLW21SN900SQ2_0805~D
4 4
3 3
USBP6-
1
1
2
R395
0_0402_5%~D
1
2
R396
0_0402_5%~D
1
2
USBP4_D+
USBP4_D-
2
1
+
2
USBP5+
1
USBP5-
4
4
2
3
R397
0_0402_5%~D
1
2
R398
0_0402_5%~D
1
2
1
JP11
2
4
3
2
1
USBP6_DUSBP6_D+
5
6
7
8
VCC GND
D- GND
D+ GND
GNDGND
D
SUYIN_020173MR004S558ZL~D
USBP6_D+
USBP6_D-
2
JP12
DLW21SN900SQ2_0805~D
@ L57
1
1
+USB_BACK_PWR
C469
0.1U_0402_16V4Z~D
<24>
USBP4+
2
C472
0.1U_0402_16V4Z~D
USBP4+
3
C468
150U_D_6.3VM_R55~D
<24>
4
2
USBP5_D+
3
USBP5_D-
4
3
2
1
USBP4_DUSBP4_D+
1
5
6
7
8
VCC GND
D- GND
D+ GND
GNDGND
+USBP5_PWR
1
SUYIN_020173MR004S558ZL~D
C473
150U_D_6.3VM_R55~D
2
2
+
2
Rear USB Ports
1
<39> DBAY_MODPRES#
1
@ C622
1000P_0402_50V7K~D
JDOG1
C474
0.1U_0402_16V4Z~D
1
2
3
4
USBP5_DUSBP5_D+
T1
T2
T3
T4
PORT_PWRUSB_SRC5
DH_SMBDAT
6
7
DH_SMBCLK
8
9
1
2
R403
150_0402_5%~D
10
11
12
13
SHLD1
SHLD2
SHLD3
SHLD4
PWR_SRC
SMB_DATA
SMB_ALERT
SMB_CLK
GND2
FOX_UB1112C-PB202-7F_9P~D
2
USB Port
C
C
+USBP5_PWR
+5V_SUS
U35
C475
0.1U_0402_16V4Z~D
+USBP5_PWR
USBP5+
2
GND IO2
3
IO1
4
VIN
<39> USB_BACK_EN#
1
2
@ U20
1
1
USB_BACK_EN#
1
2
3
4
GND
IN
EN1#
EN2#
8
7
6
5
OC1#
OUT1
OUT2
OC2#
USB_OC5#
USB_OC5#
<24>
USB_OC4#
<24>
USB_OC6#
<24>
TPS2062DR_SO8~D
C476
10U_0805_10V4Z~D
2
USBP5+USB_BACK_PWR
PRTR5V0U2X_SOT143-4~D
+5V_SUS
U37
+USB_BACK_PWR
@ U21
USBP4+
USBP6+
1
D1+
D2+
4
2
GND
VCC
5
D1-
6
3
D2-
USBP6C479
0.1U_0402_16V4Z~D
1
2
USBP4-
<39> USB_BACK_EN#
1
2
USB_BACK_EN#
1
2
3
4
GND
IN
EN1#
EN2#
8
7
6
5
OC1#
OUT1
OUT2
OC2#
USB_OC4#
USB_OC6#
TPS2062DR_SO8~D
C480
10U_0805_10V4Z~D
IP4220CZ6_SO6~D
B
B
F1
PWRUSB_SRC1
PORT_PWRUSB_SRC
2
1
2
L58
1.5A_24V_MINISMDC150F/24~D MURATA BLM31PG500SNI_1206~D
DH_SMBDAT
S
1
3
2
G
DAT_SMB
D
R404
100K_0402_5%~D
2
1
C482
0.1U_0603_50V4Z~D
<18,40> DAT_SMB
Q26
2N7002W-7-F_SOT323~D
PWRUSB_SMBEN
2
CLK_SMB
1
3
S
2
G
<18,40> CLK_SMB
D
1
1
2
G
S
R406
200K_0402_5%~D
A
@ Q30
2N7002W-7-F_SOT323~D
2
3
2
D
2
PWRUSB_EN <39>
G
Q29
2N7002W-7-F_SOT323~D
C623
0.1U_0603_50V4Z~D
D
S
1
1
<39> PWRUSB_OC#
1
R401
Q25
FDS4435_NL_SO8~D
4
100K_0402_5%~D
Z2502
1
2
Z2501
3
2
5
6
7
8
1
C481
0.1U_0603_50V4Z~D
3
2
1
R399
100K_0402_5%~D
2
1
+PWR_SRC
A
DH_SMBCLK
Q27
2N7002W-7-F_SOT323~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB 2.0 Port
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
33
of
59
5
4
3
2
1
+3.3V_RUN
D
D
C483
0.1U_0402_16V4Z~D
1
Bluetooth
2
JBT1
1
2
3
4
5
6
7
8
9
10
BT_ACTIVE
<36,44> BT_ACTIVE
COEX2_WLAN_ACTIVE
<36> COEX2_WLAN_ACTIVE
BT_RADIO_DIS#
<24> BT_RADIO_DIS#
COEX1_BT_ACTIVE
<36> COEX1_BT_ACTIVE
COEX3
T9
PAD~D
<39> USB_HUBP4-
1
2
3
4
5 GND
6 GND
7
8
9
10
11
12
2 @
R408
10K_0402_5%~D
2
1
C485
100P_0402_50V8J~D
2
1
1
C484
33P_0402_50V8J~D
R407
10K_0402_5%~D
2
1
JST_SM10B-SRSS-TB1(LF)(SN)~D
<39> USB_HUBP4+
C
C
@ R409
0_0402_5%~D
1
2
RES 2
3 IAC_SDATA0
RES 4
5 GND
3.3V 6
7 IAC_SYNC
GND 8
9 IAC_SDATAIN
GND 10
S
D
ICH_RST_MDC_R#
3
Q32
BSS138W-7-F_SOT323~D
1
1
<23> ICH_AZ_MDC_RST#
New MDC connector.
1 GND
2
G
+5V_SUS
1
R410
100K_0402_5%~D
2
2
R411
10K_0402_5%~D
<39> MDC_RST_DIS#
11 IAC_RESET#
IAC_BITCLK 12
B
B
2
2
C488
@ 10P_0402_50V8J~D
1
2
ICH_AZ_MDC_SYNC
C491
@ 10P_0402_50V8J~D
1
2
ICH_AZ_MDC_RST#
C492
@ 10P_0402_50V8J~D
1
2
A
@
Connector for MDC Rev1.5
ICH_AZ_MDC_SDOUT
C489
10P_0402_50V8J~D
2
1
2
1
1
ICH_AC_SDOUT_MDCTERM
TYCO_1-179397-2~D
1
1
1
2
2
C490
10P_0402_50V8J~D
A
@
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
ICH_AZ_MDC_BITCLK
MDC_AC_BITCLK_TERM
ICH_AZ_MDC_SYNC
MDC_SDIN
ICH_RST_MDC_R#
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK
<23> ICH_AZ_MDC_BITCLK
W=20 mil
R412
@ 10_0402_5%~D
<23> ICH_AZ_MDC_SYNC
2
R414
33_0402_5%~D
2
4
6
8
10
12
C487
0.1U_0402_16V4Z~D
1
+3.3V_SUS
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
C486
4.7U_0603_6.3V6M~D
<23> ICH_AZ_MDC_SDOUT
<23> ICH_AZ_MDC_SDIN1
1
3
5
7
9
11
R413
@ 10_0402_5%~D
JMDC1
ICH_AZ_MDC_SDOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
BT PORT & MDC
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
34
of
59
8
7
6
5
4
3
2
1
D
D
1
R657
1
R658
USB SMARTCARD READER.
TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.
2
33_0402_5%~D
2
33_0402_5%~D
@ L67
HUB_USB_BIO-
1
1
2
2
USB_BIO-
<41>
HUB_USB_BIO+
4
4
3
3
USB_BIO+
<41>
<---Fingerprint
3
4
2
32
1
2
MODE0/SC_LED#
MODE1
MODE2
11
13
26
4.7K_0402_5%~D
R426
1
MD0
XI/48M_IN
XO
GND
GND
GND
C502
2
@ C725
47P_0402_50V8J~D
2
@C724
47P_0402_50V8J~D
2
2
1
1
R420
2
1
2
2
1
+SC_PWR
2
C
SC_VCC
27
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
24
23
22
25
15
SC_RST#
SC_CLK
SC_C4
R422
R423
R424
2
2
2
1 220_0402_5%~D
1 33_0402_5%~D
1 220_0402_5%~D
SC_RST#_R
SC_CLK_R
SCCD+
SC_IO
R425
2
1 220_0402_5%~D
SC_IO_R
SCCD-
RF_OUT
RF_IN/RX
RF_CLK
RF_AUX
8
7
9
10
SC_DET#
OZ77C6LN-B1_QFN32~D
Close to Smart Card Conn.
1 VRCPR
C501
0.1U_0402_16V4Z~D
<6> CLK_SMCARD_48M
SCCDSCCD+
2
47K_0402_5%~D
NC
NC
21
20
1
C500
1U_0603_10V4Z~D
30
31
CLK_SMCARD_48M
EGATEDEGATED+
1
C499
0.1U_0402_16V4Z~D
RST#
1
2
UPDUPD+
14
DPDDPD+
R418
10K_0402_5%~D
17
16
PCI_RST#
29
19
18
1
+SC_PWR
C498
4.7U_0603_6.3V6M~D
USB_HUBP3USB_HUBP3+
+3.3V_OUT
R563
15K_0402_5%~D
1
VCC5V_IN
VCC5V_IN
2
C497
0.1U_0402_16V4Z~D
5
28
1
C496
0.1U_0402_16V4Z~D
2
U38
C495
4.7U_0603_6.3V6M~D
C494
0.1U_0402_16V4Z~D
C493
4.7U_0603_6.3V6M~D
2
1
VR_CPR
VR_CPR
<39> USB_HUBP3<39> USB_HUBP3+
<22,31,37> PCI_RST#
2
1
6
12
2
C
1
R417
1.5K_0402_1%~D
1
+3.3V_RUN
R562
15K_0402_5%~D
1
2
+3.3V_OUT
R415
15K_0402_5%~D
2
1
+5V_RUN
R416
15K_0402_5%~D
1
2
DLW21SN900SQ2_0805~D
SC_RST#_R
SC_CLK_R
SCCD+
<32>
<32>
<32>
SC_IO_R
SCCDSC_DET#
<32>
<32>
<32,39>
1
2
1U_0603_10V4Z~D
B
B
Place closely pin 3
1
CLK_SMCARD_48M
2
@ R427
10_0402_5%~D
1
@ C503
4.7P_0402_50V8C~D
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
8
7
6
5
4
3
Title
Smart Card OZ77C6
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
2
Sheet
35
1
of
59
5
4
3
2
1
JCLIP1
1
2
3
4
Mini Card
Wire less WAN
1
2
3
4
MOLEX_48099-5200~D
D
D
Mini-Card Latch
+3.3V_RUN
+3.3V_RUN
JMINI1
PCIE_WAKE#
<29,39> PCIE_WAKE#
<39> USB_HUBP2-
@ L60
1 1
<39> USB_HUBP2+
4
4
USB_HUBP2_D-
3
USB_HUBP2_D+
3
R430
0_0402_5%~D
1
2
R431
0_0402_5%~D
1
2
MINI1CLK_REQ#
<6> MINI1CLK_REQ#
DLW21SN900SQ2_0805~D
2 2
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<6> CLK_PCIE_MINI1#
<6> CLK_PCIE_MINI1
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
<24> PCIE_IRX_WANTX_N1
<24> PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
<24> PCIE_ITX_WANRX_N1_C
<24> PCIE_ITX_WANRX_P1_C
C
Mini Card
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
JCLIP2
1
2
3
4
Wire less LAN
1
2
3
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
+1.5V_RUN
+SIM_PWR
UIM_DATA <32>
UIM_CLK
<32>
UIM_RESET <32>
+UIM_VPP
UIM_DATA
UIM_CLK
UIM_RESET
+UIM_VPP
WWAN_RADIO_DIS#
PLTRST#
WWAN_RADIO_DIS# <24>
PLTRST#
<10,20,22,24,29>
+3.3V_LAN
ICH_SMBCLK
ICH_SMBDATA
ICH_SMBCLK <6,24,29>
ICH_SMBDATA <6,24,29>
USB_HUBP2_DUSB_HUBP2_D+
C
MOLEX_67910-5200~D
MOLEX_48099-5200~D
Mini-Card Latch
+3.3V_RUN
R638
0_0402_5%~D
<6> CLK_PCIE_MINI2#
<6> CLK_PCIE_MINI2
<40> HOST_DEBUG_RX
<40>
8051TX
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
<24> PCIE_IRX_WLANTX_N2
<24> PCIE_IRX_WLANTX_P2
B
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
<24> PCIE_ITX_WLANRX_N2_C
<24> PCIE_ITX_WLANRX_P2_C
53
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
+1.5V_RUN
HOST_DEBUG_TX <40>
WLAN_RADIO_OFF#
PLTRST#
PLTRST#
<10,20,22,24,29>
+3.3V_LAN
ICH_SMBCLK <6,24,29>
ICH_SMBDATA <6,24,29>
USBP0USBP0+
LED_WLAN_OUT#
1
2
@ R555
0_0402_5%~D
B
+3.3V_LAN
+1.5V_RUN
+3.3V_RUN
<24>
<24>
8051RX
<40>
LED_WLAN_OUT# <44>
BT_ACTIVE
<34,44>
1
1
2
1
C513
0.047U_0402_16V4Z~D
2
1
C514
0.047U_0402_16V4Z~D
2
1
C515
33P_0402_50V8J~D
1
+
C516
33P_0402_50V8J~D
2
+
C509
330U_V_6.3VM_R25M~D
2
2
C685
330U_V_6.3VM_R25M~D
1
2
1
2
C512
33P_0402_50V8J~D
COEX2
COEX1
C511
0.047U_0402_16V4Z~D
1
2
1
2
R6390_0402_5%~D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
C510
0.1U_0402_16V4Z~D
<29,39> PCIE_WAKE#
<34> COEX2_WLAN_ACTIVE
<34> COEX1_BT_ACTIVE
<6> MINI2CLK_REQ#
+3.3V_RUN
JMINI2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
2
MOLEX_67910-5200~D
D23
1
<39> WLAN_RADIO_DIS#
2
PWR
Rail
WLAN_RADIO_OFF#
Voltage
Tolerance
Primary Power
Peak
Normal
Aux Power
Normal
RB751S40T1_SOD523-2~D
1
2
@ R634
0_0402_5%~D
+1.5V_RUN
+3.3V
+-9%
1000
750
+3.3Vaux
+-9%
330
250
+1.5V
+-5%
500
375
250 (Wake enable)
5 (Not wake enable)
1
2
1
2
C519
0.047U_0402_16V4Z~D
+3.3V_RUN
C518
0.047U_0402_16V4Z~D
A
C517
0.1U_0402_16V4Z~D
+3.3V_LAN
A
1
2
2
C520
0.047U_0402_16V4Z~D
1
2
1
C521
0.047U_0402_16V4Z~D
2
C522
0.1U_0402_16V4Z~D
1
2
C523
0.1U_0402_16V4Z~D
1
2
C524
4.7U_0603_6.3V6M~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
NA
1
4
3
2
Title
Mini Card
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
36
of
59
5
4
3
+5V_RUN
2
1
+VCC_QBUF
QUIETE#
U39
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9
C
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC1
A1
A2
A3
A4
A5
A6
A7
A8
GND1
NC2
A9
A10
A11
A12
A13
A14
A15
A16
GND2
NC3
A17
A18
A19
A20
A21
A22
A23
A24
GND3
NC4
A25
A26
A27
A28
A29
A30
A31
A32
GND4
VCC4
OE1#
B1
B2
B3
B4
B5
B6
B7
B8
VCC3
OE2#
B9
B10
B11
B12
B13
B14
B15
B16
VCC2
OE3#
B17
B18
B19
B20
B21
B22
B23
B24
VCC1
OE4#
B25
B26
B27
B28
B29
B30
B31
B32
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R432
1K_0402_5%~D
D
C525
0.1U_0402_16V4Z~D
1
2
FIR
DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24
+3.3V_RUN
R433
47_0805_5%~D
2
1 +IRVCC
+3.3V_RUN
U40
DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16
<39> D_IRMODE
<39>
DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9
6
VCC
5
SD_MODE
2
IRED_CATHODE
3
IRTX
IRED_ANODE
TXD
1
RXD
4
MODE
7
GND
8
IRRX
TFDU6102-TR3_8P~D
C527
0.1U_0402_16V4Z~D
D
2
2
1
1
C526
4.7U_0603_6.3V6M~D
2
1
R436
10K_0402_5%~D
2
1
1
C528
4.7U_0603_6.3V6M~D
RB751S40T1_SOD523-2~D
R435
10K_0402_5%~D
2
1
RB751S40T1_SOD523-2~D
1
1
2
2
C687
0.47U_0402_16V4Z~D
D14
+VCC_QBUFD
1
C686
0.1U_0402_16V4Z~D
D13
2
<39>
1
2
2
C
DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0
PI5C34X2245BE_BQSOP80~D
<22,31> PCI_AD[0..31]
DOCK_AD[0..31] <38>
+3.3V_RUN
C688
0.47U_0402_16V4Z~D
1
2
2
3
4
5
6
7
8
9
10
11
<22,31>
<22,31>
<22>
<22,31>
<22,31>
<22,31>
<22,31>
PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
46
45
44
43
42
41
40
39
38
37
DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#
14
15
16
17
18
19
20
21
22
23
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
34
33
32
31
30
29
28
27
26
25
DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL
1
13
NC1
NC2
GND1
GND2
12
24
2
DOCK_PIRQA# <38>
DOCK_GNT0# <38>
DOCK_PCIRST# <38>
DOCK_SPME# <38>
DOCK_C_BE3# <38>
DOCK_C_BE2# <38>
DOCK_C_BE1# <38>
DOCK_C_BE0# <38>
DOCK_IRDY# <38>
DOCK_FRAME# <38>
B
5
<22> PCI_PIRQA#
<22,38> PCI_GNT0#
<22,31,35> PCI_RST#
<31,39> SYS_PME#
<22,31> PCI_C_BE3#
<22,31> PCI_C_BE2#
<22,31> PCI_C_BE1#
<22,31> PCI_C_BE0#
<22,31,38> PCI_IRDY#
<22,31,38> PCI_FRAME#
C529
0.1U_0402_16V4Z~D
2
<38> DOCK_PCI_EN#
<39> QBUFEN#
DOCK_PCI_EN#
1
INA
QBUFEN#
2
INB
U42
P
PCI_PIRQA#
PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI _IRDY#
PCI_FRAME#
B
VCC1
VCC2
1
R437
100K_0402_5%~D
O
QUIETE#
4
G
OE1
OE2
C530
0.1U_0402_16V4Z~D
1
2
36
48
SN74AHC1G32DCKR_SC70-5~D
3
47
35
1
U41
QUIETE#
DOCK_TRDY# <38>
DOCK_STOP# <38>
DOCK_LOCK# <38>
DOCK_DEVSEL# <38>
DOCK_PERR# <38>
DOCK_SERR# <38>
DOCK_PAR <38>
DOCK_PCI_IDSEL <38>
PI5C162861BE_BQSOP48~D
Need to modify PAD width from 9mil to 8mil
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DOCKING BUFFER & FIR
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
37
of
59
3
2
1
+DOCK_DC_IN
+DOCK_PWR_SRC
DVI_TX4DVI_TX4+
D
DVI_TX3+
DVI_TX3-
<45>
PS_ID_IN
DVI_TX5+
DVI_TX5-
<20>
<20>
<20>
<20>
<20>
<20>
DVI_TX2+
DVI_TX2DVI_TX1+
DVI_TX1DVI_TX0+
DVI_TX0DOCK_AD31
<6> CLK_PCI_DOCK
<37> DOCK_PIRQA#
C
<40> DOCK_SMB_CLK
<40> DOCK_SMB_DAT
<40> CLK_DOCK
<40>
DAT_DOCK
<18,40,44> POWER_SW#
15
S15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
45
S45
47
48
49
50
51
52
53
54
55
S47
S48
S49
S50
S51
S52
S53
S54
S55
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
S125
S126
S127
S128
125
126
127
128
M136
136
DOCK_DET#
VGA_GRN
+2.5V_LOM_DOCK
C533
0.01U_0402_16V7K~D
1
2
C534
0.01U_0402_16V7K~D
2
1
C535
0.01U_0402_16V7K~D
1
2
C536
0.01U_0402_16V7K~D
2
1
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
DOCK_LAN_TX3DOCK_LAN_TX3+
DOCK_LAN_TX2DOCK_LAN_TX2+
<30>
<30>
<30>
<30>
193
194
195
196
VGA_RED
VGA_BLU
D_SERIRQ <39>
DOCK_PCI_IDSEL <37>
<39>
<39>
<39>
D_LAD1
D_LAD2
D_LAD3
D_DLDRQ1# <39>
D_LFRAME# <39>
DOCK_AD1
DOCK_AD0
DOCK_AD3
DOCK_AD4
DOCK_AD7
DVI_SCLK <20>
DVI_SDATA <20>
DVI_DETECT <20>
DOCK_AD8
DOCK_C_BE0#
D_LAD1
D_LAD2
D_LAD3
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_C_BE0# <37>
DOCK_AD14
DOCK_AD15
<37> DOCK_PAR
<37> DOCK_SERR#
<37> DOCK_LOCK#
DOCK_DEVSEL# <37>
DOCK_IRDY# <37>
<37> DOCK_FRAME#
<37> DOCK_C_BE2#
DOCK_AD19
DOCK_AD20
DOCK_C_BE2#
DOCK_AD16
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD27
DOCK_AD28
DOCK_AD30
DOCK_AD29
<37> DOCK_SPME#
DOCK_GNT0# <37>
USBP7USBP7+
USBP7USBP7+
TV_C
<24>
<24>
<37> DOCK_PCI_EN#
<27> SPDIF_DOCK
DOCK_SMB_INT# <40>
CLK_KBD <40>
DAT_KBD <40>
<30> DOCK_LED_10#
<30> DOCK_LED_100#
+2.5V_LOM
R440
0_0402_5%~D
2
1
+3.3V_RUN
RJ_RING_L
<30>
<30>
<30>
<30>
<30>
@
2
R438
SPDIF_DOCK
DOCK_LED_10#
DOCK_LED_100#
1DOCK_OWNS_PCI
100K_0402_5%~D
DOCK_LAN_TX1DOCK_LAN_TX1+
DOCK_LAN_TX0DOCK_LAN_TX0+
<30>
204
RJ_TIP_L
TYCO_2-1612415-3~D
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
S175
S176
S177
S178
S179
S180
S181
S182
S183
S184
S185
S186
S187
S188
S189
S190
S193
S194
S195
S196
JDOCK1C
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
205
206
207
208
209
210
211
212
213
214
215
216
217
218
S220
220
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
S250
250
S252
S253
S254
S255
S256
S257
S258
S259
252
253
254
255
256
257
258
259
DOCK_DET#
DAT_DDC2 <12,21>
CLK_DDC2
<12,21>
HSYNC_R
VSYNC_R
HSYNC_R
VSYNC_R
<21>
<21>
D_CLKRUN# <39>
D_LAD0 <39>
DOCK_SIO_ALERT# <39>
D_LAD0
DOCK_SIO_ALERT#
DOCK_AD2
DOCK_AD5
DOCK_AD6
DOCK_AD12
DOCK_AD13
DOCK_C_BE1#
DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#
DOCK_C_BE3#
DOCK_AD25
DOCK_AD26
PCI_REQ0#
DOCK_PCIRST#
TV_Y
DOCK_LAN_ACTLED_YEL#
R_PIDEACT
DOCK_LAN_ACTLED_YEL# <30>
R_PIDEACT
<44>
<12>
TV_Y
<12>
TV_CVBS
2
A
SHLD1
SHLD3
MH7
SHLD2
SHLD4
MH8
MH9
SHLD5
SHLD7
MH11
MH10
SHLD6
SHLD8
MH12
MH13
MH15
MH14
MH16
MH14
MH16
2
D
SIGNAL 218P
RJ11
2P
VOID
52P
POWER
8P
VOID PIN: V14 V16 V44 V46 V56~V68 V123 V124
V129~V135 V191 V192 V197~V203 V219
V221 V249 V251 V260~V272
TYCO_2-1612415-3~D
TV_C
1
R439
1
R441
1
R442
TV_CVBS
TV_Y
2
150_0402_1%~D
2
150_0402_1%~D
2
150_0402_1%~D
1
C690
1000P_0402_50V7K~D
B
1
2
3
no power dock
2
1
3
DOCK_PWR_EN
1
IN1
U46
74AHC1G08GW_SOT353-5~D
G
IN2
O
Z3308
4
+3.3V_SUS
1
VGA_RED
2
PWR_SRC
D
S
self power dock
Q35
2N7002W-7-F_SOT323~D
2
G
P
<39> DOCK_PWR_EN
2
TV_CVBS
@ R449
0_0402_5%~D
VGA_GRN
A
DELL CONFIDENTIAL/PROPRIETARY
DOCKING CONN.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VGA_BLU
<12,21> VGA_BLU
5
C
DOCK_AD[0..31] <37>
Q34
DDTC144EUA-7-F_SOT323~D
74AHC1G08GW_SOT353-5~D
TV_Y
<12,21> VGA_GRN
MH6
NB
@ D15
SM05_SOT23~D
2
IN2
TV_C
<12,21> VGA_RED
MH2
Z3306
3
O
MH5
1
MH2
4
1
2
1
DOCK_DET#
4
MH1
1
R446
100K_0402_5%~D
1
R447
100K_0402_5%~D
U45
IN1
MH1
2
<30,39>
R448
100K_0402_5%~D
1
2
TV_C
74AHC1G08GW_SOT353-5~D
P8
G_DOC_PWRSRC
DOCKED
5
<12>
DOCK_OWNS_PCI
IN2
P8
+DOCK_PWR_SRC
2
P
5
PCI_FRAME# 2
4
G
1
3
<22,31,37> PCI_FRAME#
PCI _IRDY#
O
8
7
6
5
1
2
3
1
2
2
IN1
P4
1
U43
NC7SZ04P5X_NL_SC70-5~D
+3.3V_RUN
R444
100K_0402_5%~D
+5V_ALW
P
1
1
2
C651
0.1U_0402_16V4Z~D
<22,31,37> PCI_IRDY#
2
R445
100K_0402_5%~D
U44
G
Z3305
4
3
3
Y
P7
P4
JDOCK1D
TV_CVBS
C538
0.1U_0603_50V4Z~D
1
2
C650
0.1U_0402_16V4Z~D
5
5
A
P6
P7
DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31
PCI_REQ0# <22>
DOCK_PCIRST# <37>
+3.3V_ALW
1
P
NC
PCI_GNT0# 2
G
<22,37> PCI_GNT0#
P6
P3
Z3307
1
2
2
P2
P3
Q33
FDS4435_NL_SO8~D
1
@ C537
22P_0402_50V8J~D
P2
TYCO_2-1612415-3~D
M204
+3.3V_RUN
C649
0.1U_0402_16V4Z~D
P5
DOCK_C_BE3# <37>
+PWR_SRC
2
P5
DOCK_AD17
DOCK_AD18
DOCK_AD21
+3.3V_RUN
@ R443
33_0402_5%~D
P1
MH13
MH15
TYCO_2-1612415-3~D
CLK_PCI_DOCK
1
1
DOCK_PERR# <37>
DOCK_STOP# <37>
DOCK_TRDY# <37>
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR
B
2
P1
DOCK_C_BE1# <37>
1
DVI_CLKDVI_CLK+
JDOCK1B
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
3
<20>
<20>
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
C532
0.1U_0603_50V4Z~D
JDOCK1A
1
2
3
4
5
6
7
8
9
10
11
12
13
C689
1000P_0402_50V7K~D
4
C531
0.1U_0603_50V4Z~D
5
4
3
2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
38
of
59
5
4
3
2
1
+3.3V_ALW
+3.3V_ALW
2
1
2
<32,35> SC_DET#
<24> ICH_PCIE_WAKE#
<22> ICH_PME#
<18> THERMTRIP_SIO
<31> CBUS_GRST#
B
<19> FPBACK_EN
<31> CB_HWSPND#
<7> CPU_PROCHOT#
<26> HDDC_EN#
<37>
<37>
IRTX
IRRX
<37>
D_IRMODE
<33> USB_BACK_EN#
<33> DBAY_MODPRES#
PBAT_ALARM#
LOM_TPM_EN#
AUDIO_AVDD_ON
BEEP
SC_DET#
ICH_PCIE_WAKE#
ICH_PME#
THERMTRIP_SIO
@ R564 2
1 0_0402_5%~D
FPBACK_EN
CB_HWSPND#
CPU_PROCHOT#
HDDC_EN#
61
62
GPIOD[1]
GPIOD[2]
63
28
29
30
31
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
32
33
GPIOH[6]
GPIOH[7]
88
89
90
91
92
93
94
95
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
106
107
SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]
BID3
BID2
BID1
BID0
109
110
111
112
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
IRTX
IRRX
113
114
IRTX
IRRX
D_IRMODE
115
116
117
118
GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A
USB_BACK_EN#
DBAY_MODPRES#
CLKI (14.318 MHz)
64
CLK_SIO_14M
VSS
96
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
55
53
50
48
43
38
45
40
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
R469
10K_0402_5%~D
1
2
R470
10K_0402_5%~D
1
2
R471
10K_0402_5%~D
1
2
R472
10K_0402_5%~D
1
2
@
C638
4.7U_0603_6.3V6M~D
C547
4.7U_0603_6.3V6M~D
C546
0.1U_0402_16V4Z~D
C545
0.1U_0402_16V4Z~D
1
2
C
1
100K_0402_5%~D
LPC_LFRAME# <23,29,40>
PLTRST2# <22,40>
CLK_PCI_SIO <6>
CLKRUN# <24,31,40>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,29,31,40>
1
C548
12P_0402_50V8J~D
1
2
Y1
24MHZ_12PF_1BX24000CE1B~D
C550
1
2
12P_0402_50V8J~D
Place closely pin 56
CLK_PCI_SIO
CLK_SIO_14M <6>
7
OUT65
105
WLAN_RADIO_DIS#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
17
23
36
51
72
87
121
128
1
1
2
R463
22_0402_5%~D
D_LAD0 <38>
D_LAD1 <38>
D_LAD2 <38>
D_LAD3 <38>
D_LFRAME# <38>
D_CLKRUN# <38>
D_DLDRQ1# <38>
D_SERIRQ <38>
RUNPWROK
1
2
B
1
C551
22P_0402_50V8J~D
2
<40,43,50>
WLAN_RADIO_DIS# <36>
1
2
BID3 BID2 BID1 BID0 REV
@
BID0
R473
1
2
10K_0402_5%~D
BID1
R474
1
2
10K_0402_5%~D
BID2
@ R475
1
2
10K_0402_5%~D
BID3
R476
1
2
10K_0402_5%~D
*
5
LPC_LAD[0..3] <23,29,40>
RUNPWROK
2
ECE5018 A0_VTQFP128~D
+3.3V_ALW
R460
ECE5018_XTAL1
ECE5018_XTAL2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_SIO
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
PWRGD
LOM_TPM_EN#
R459
10K_0402_5%~D
Route RBIAS and its
return to pin 128 very
short.
REG_EN
54
52
49
47
42
41
56
37
46
44
39
DLPC
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
+3.3V_ALW
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
LPC
2
R455
2
R456
2
R457
1
2
<29> LOM_TPM_EN#
<29> LOM_LOW_PWR
<27> AUDIO_AVDD_ON
<27>
BEEP
<51> ADAPT_TRIP_SEL
D_SERIRQ
2
<46> PBAT_ALARM#
126
123
122
D_CLKRUN#
2
CLK
ATEST
+3.3V_RUN
RBIAS
35
XTAL1/CLKIN
XTAL2
<31,32>
<---PC Card Bay
<31,32>
<36>
<36> <---Mini1 WWAN
<35>
<35> <---Smart Card
<34>
<34> <---Blue Tooth
2
2
TEST
2
+3.3V_ALW
1
GPIO
2
1
L61
BLM18PG181SN1_0603~D
120ohm,600mA,0.25ohm
D_DLDRQ1#
125
124
120
86
127
TEST_PIN is a No Connect
TEST_PIN
2
1
@
@R461
22_0402_5%~D
USBP1+ <24>
USBP1- <24>
USB_HUBP1+
USB_HUBP1USB_HUBP2+
USB_HUBP2USB_HUBP3+
USB_HUBP3USB_HUBP4+
USB_HUBP4-
2
1
@
HP_NB_SENSE
GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0
1
<27> DOCK_HP_MUTE#
<27,28> HP_NB_SENSE
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
VDDA33PLL
VDDA18PLL
VDD18
CAP_LDO
RBIAS
2
USBP1+
USBP1USB_HUBP1+
USB_HUBP1USB_HUBP2+
USB_HUBP2USB_HUBP3+
USB_HUBP3USB_HUBP4+
USB_HUBP4-
1
1
<29> LOM_CABLE_DETECT
<27> SPDIF_SHDN
<50> IMVP6_PROCHOT#
<32> CBS_CCD2#
<32> EXUSB_EN#
NB_MUTE
@ R602 2
1 0_0402_5%~D
SPDIF_SHDN
IMVP6_PROCHOT#
R653 2
1 0_0402_5%~D
EXUSB_EN#
GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#
USB
119
9
10
13
12
15
16
19
18
21
22
1
R462
NB_MUTE
1
2
3
4
5
84
83
6
VCC1
USBDP0
USBDN0
USBDP1
USBDN1
USBDP2
USBDN2
USBDP3
USBDN3
USBDP4
USBDN4
1
2
<28>
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK
SIO_VDDA
8
14
20
1M_0402_5%~D
CLK_SIO_14M
@
C542
0.1U_0402_16V4Z~D
+3.3V_ALW
C543
0.1U_0402_16V4Z~D
R560
0_0402_5%~D
2
1
Place closely pin 64
A
2
C555
4.7U_0603_6.3V6M~D
Follow Travis to add that
Broadcom will be update for
next version.
PWRUSB_OC#
PWRUSB_EN
MDC_RST_DIS#
24
25
26
27
58
59
60
VDDA33
VDDA33
VDDA33
ECE5018
C554
4.7U_0603_6.3V6M~D
<33> PWRUSB_OC#
<33> PWRUSB_EN
<34> MDC_RST_DIS#
<51> ADAPT_OC
DOCKED
QBUFEN#
DOCK_PWR_EN
SINFFER_WIRELESS_ON/OFF#
BC_INT#
BC_DAT
BC_CLK
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
R458
12K_0402_1%~D
<30,38> DOCKED
<37> QBUFEN#
<38> DOCK_PWR_EN
<44> SNIFFER_WIRELESS_ON/OFF#
<40> BC_INT#
<40>
BC_DAT
<40> BC_CLK
97
98
99
100
101
102
103
104
2
PCIE_WAKE#
SYS_PME#
DOCK_SIO_ALERT#
PBAT_PRES#
C553
0.1U_0402_16V4Z~D
<29,36> PCIE_WAKE#
<31,37> SYS_PME#
<38> DOCK_SIO_ALERT#
<46> PBAT_PRES#
2
C544
0.1U_0402_16V4Z~D
34
57
85
108
U47
C
@C549
22P_0402_50V8J~D
2
1
C541
0.1U_0402_16V4Z~D
1
C552
4.7U_0603_6.3V6M~D
IMVP6_PROCHOT#
1
100K_0402_5%~D
2
1
C540
0.1U_0402_16V4Z~D
D
+3.3V_RUN
2
R596
1
C539
0.1U_0402_16V4Z~D
VCC1
VCC1
VCC1
VCC1
D
1
DOCK_SIO_ALERT#
2
10K_0402_5%~D
PCIE_WAKE#
2
10K_0402_5%~D
PBAT_ALARM#
2
10K_0402_5%~D
DBAY_MODPRES#
2
10K_0402_5%~D
PWRUSB_OC#
2
10K_0402_5%~D
SYS_PME#
2
10K_0402_5%~D
HDDC_EN#
2
100K_0402_5%~D
1
R450
1
R452
1
R453
1
R454
1
R559
1
R451
1
R644
0
0
0
0
0
0
0
0
0
1
4
0
0
1
1
0
0
1
0
1
0
X00
X01
X02
X03
A00
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ECE5018
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
39
of
59
5
4
3
2
1
+RTC_CELL
+3.3V_ALW
1
+RTC_CELL
R586
109
110
FLCS0
FLCS1
BC_CLK
BC_DAT
BC_INT#
<39> BC_CLK
<39>
BC_DAT
<39> BC_INT#
BC_CLK
BC_DAT
BC_INT
1
2
3
CAP_LED#
SCRL_LED#
NUM_LED#
1 SPI_CS#
0_0402_5%~D
DOCK_SMB_INT#
SFPI_EN
PS_ID_DISABLE#
52
ATF_INT#
11
115
114
SIO_EXT_SMI#
BAT2_LED#
BAT1_LED#
FW P#
GPIO96/TOUT1
OUT7/nSMI
nPWR_LED
nBAT_LED
BC Bus
nFWP
84
GPIOA3/WINDMON
73
GPIO83/32KHZ_OUT
117
2
0_0402_5%~D
RUNPW ROK
104
101
MEC5004_VTQFP128~D
RUNPWROK
<39,43,50>
R511
100K_0402_5%~D
SPI_CS#
1
2
BLM11A121S_0603~D
120ohm,600mA,0.25ohm
1
2
1
2
@ R630
@ D22
10K_0402_5%~D
RB751S40T1_SOD523-2~D
@ U49
1
2
3
4
@
1
ECO_FLASHI_DATA
FW P#
low=write protected
@ C691
4.7U_0603_6.3V6M~D
@ Q76
1
PMST3906_SOT323-3~D @ R631
D
VCC
HOLD#
C
D
2
8
7
6
5
Flash ROM
150 MIL SO8
2 +VR_CAP
22_0402_5%~D
@ Q77
2N7002W-7-F_SOT323~D
2
G
S
R510
47_0402_5%~D
SPI_CS#
ECI_FLASHO_DATA 1
2
SPI_WE#
@
U50
1
2
3
4
EC_FLASH_SPI_CLK
SPI_HOLD#
S#
Q
W#
VSS
VCC
HOLD#
C
D
8
7
6
5
SPI_HOLD#
EC_FLASH_SPI_CLK
ECO_FLASHI_DATA
M25P80-VMW6TP_SO8~D
A
200 MIL SO8
+3.3V_SUS
TYCO_1-179373-2~D
The same MDC connctor
for TAA module
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
2
R512
100K_0402_5%~D
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Flash write protect bottom 4K
of internal bootblock flash
5
S#
Q
W#
VSS
1
M25P80-VMW6TP_SO8~D
2
@
2
B
+3.3V_SUS
R508
10K_0402_5%~D
2
1
3
5
7
9
11
1
3
5
7
9
11
1
1=Flash Recovery Enabled
0=Flash Recovery Disabled
+3.3V_ALW
L62
+3.3V_ALW_EC 1
1
R504
10K_0402_5%~D
+3.3V_SUS
1
2
@
20
19
18
17
16
15
14
13
2
EC_FLASH_PAD1
@SHORT PADS~D
T11
RESET_OUT# <43>
@ JP3
SPI_WE#
ECI_FLASHO_DATA
PAD~D
+3.3V_ALW
20
19
18
17
16
15
14
13
1
1
1
1
3
HOST_DEBUG_TX <36>
HOST_DEBUG_RX <36>
Bat2 = Amber LED
Bat1 = Green LED
<12,19>
RESET_OUT#
2
4
6
8
10
12
@
T10
R503
1K_0402_5%~D
SFPI_EN 2
1
BIA_PWM
2
1
R637
0_0402_5%~D
Pop for flash corruption issue.
0.1U_0402_16V4Z~D
2
4
6
8
10
12
C
2
20mA drive pins
72
A LWON
+3.3V_ALW
PBAT_SMBCLK
VGA_IDENTIFY
C564
0.047U_0402_16V4Z~D
<18>
SIO_EXT_SMI# <24>
BAT2_LED#
<44>
BAT1_LED#
<44>
53
2
2
Y3
32.768K_12.5PF_Q13MC30610003~D
4
C570
22P_0402_50V8J~D
C569
22P_0402_50V8J~D
A
1
<41,44>
PS_ID_DISABLE# <45>
MEC5004_XTAL1
MEC5004_XTAL2 2
1
R506
0_0402_5%~D
<44>
<44>
<44>
<24>
DOCK_SMB_INT# <38>
TEST_PIN
C567
1
PBAT_SMBDAT
LID_CL#
2
CAP_LED#
SCRL_LED#
NUM_LED#
SPI_CS#
3
2
2
1
LID_CL#
<45>
ATF_INT#
2
1
C568
4.7U_0603_6.3V6M~D
32 KHz Clock
+VR_CAP 22
2
R507
10K_0402_5%~D
26
51
74
88
113
L63
BLM11A121S_0603~D
2
1 +EC_AGND 125
120ohm,600mA,0.25ohm
2
SBAT_SMBDAT
SBAT_SMBCLK
LID_CL_SIO#
R495
10_0402_5%~D
2
1
+3.3V_ALW
nRESET_OUT/OUT6
1
1
@ C565
22P_0402_50V8J~D
CLK_SMB
R491
1M_0402_1%~D
PAD~D
49
VCC_PLL
XOSEL
1
@ R590
PS_ID
PWRGD
VSS_PLL
XTAL1
XTAL2
123
VR_CAP
122
124
AGND
2
MEC5004_XOSEL
VSS
VSS
VSS
VSS
VSS
MEC5004_XTAL1
MEC5004_XTAL2
@ R505
22_0402_5%~D
2
R642
+3.3V_ALW
2
SGPIO35
SGPIO36 (SFPI_EN)
SGPIO37
2
10K_0402_5%~D
2
10K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
10K_0402_5%~D
SIO_EXT_SCI# <24>
E
B
2
1
91
90
89
4
2
70
71
SGPIO40
SGPIO41
SGPIO42
SGPIO43
1
87
86
85
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
HOST_DEBUG_TX
HOST_DEBUG_RX
1
R489
1
R490
1
R492
1
R493
1
R494
1
R496
1
R558
DAT_SMB
1
FLCLK
FLDATAIN
FLDATAOUT
SIO_PWRBTN#
PS_ID
VGA_IDENTIFY
LID_CL_SIO#
DEBUG_ENABLE#
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
1
10K_0402_5%~D
+3.3V_ALW
BREATH_LED <44>
SIO_EXT_SCI#
1
R483
1
R485
2
R486
2
103
106
108
66
55
54
69
68
67
DOCK_SMB_DAT
C566
0.1U_0402_16V4Z~D
Place closely pin 58
EC_FLASH_SPI_CLK
ECI_FLASHO_DATA
ECO_FLASHI_DATA
nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1
2
100K_0402_5%~D
+5V_ALW
DOCK_SMB_INT#
FAN1_TACH <18>
BREATH_LED
1
R614
1
<24> SIO_PWRBTN#
HSTCLK
HSTDATAIN
HSTDATAOUT
48
47
46
45
FAN1_TACH
INSTANT_ON_SW#
DOCK_SMB_CLK
PBAT_SMBCLK <46,51>
PBAT_SMBDAT <46,51>
DOCK_SMB_CLK <38>
DOCK_SMB_DAT <38>
AUX_EN <42,47>
SUS_ON <42,43,47>
RUN_ON <19,42,43,47,48,49>
ITP_DBRESET# <7,24>
SBAT_SMBDAT <19>
SBAT_SMBCLK <19>
DAT_SMB <18,33>
CLK_SMB <18,33>
SIO_SLP_S5# <24>
SIO_SLP_S3# <24>
SIO_RCIN# <23>
SIO_EXT_WAKE# <24>
SNIFFER_LED_OFF# <44>
+RTC_CELL
SNIFFER_SW# <44>
C563
1U_0603_10V4Z~D
<18,51>
2
SNIFFER_LED_OFF#
R481
10K_0402_5%~D
2 S NIFFER_SW#
R509
10K_0402_5%~D
LRESET#
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ
OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0
Host/8051
<24> ICH_EC_SPI_CLK
<24> ICHI_ECI_SPIO_DATA
<24> ICHO_ECO_SPII_DATA
D
2
57
58
59
60
61
62
63
64
56
ICH_EC_SPI_CLK
102
ICHI_ECI_SPIO_DATA 105
ICHO_ECO_SPII_DATA 107
R478
10K_0402_5%~D
2
POWER_SW# <18,38,44>
1
<24,31,39> CLKRUN#
<24,29,31,39> IRQ_SERIRQ
1
2
PLTRST2#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLK RUN#
IRQ_SERIRQ
43
42
41
ACAV_IN
2
GPIO94/IMCLK
GPIO95/IMDAT
KCLK
KDAT
EMCLK
EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
1
1
R501
10K_0402_5%~D
LPC_LAD[0..3]
<23,29,39> LPC_LAD[0..3]
MAIN_PWR_SW#
1
S NIFFER_PWR_SW#
1
75
76
77
78
79
80
81
82
8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100
<47>
R500
10K_0402_5%~D
2
1
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051RX
8051TX
8051RX
8051TX
<22,39> PLTRST2#
<6> CLK_PCI_5004
<23,29,39> LPC_LFRAME#
CLK_PCI_5004
SGPIO34/A20M
OUT5/KBRST
LPC Interface
Depop 0ohm when
doing flash
recovery
92
50
AB1B_CLK
AB1B_DATA
AB1A_CLK
AB1A_DATA
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
PBAT_SMBCLK
PBAT_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT
AUX_EN
SUS_ON
RUN_ON
ITP_DBRESET#
SBAT_SMBDAT
SBAT_SMBCLK
DAT_SMB
CLK_SMB
SIO_SLP_S5#
SIO_SLP_S3#
S IO_RCIN#
SIO_EXT_WAKE#
PWR SW
ALWON
2
DEBUG_ENABLE#
2
<36>
0_0402_5%~D
<36>
1
R499
SIO_A20GATE
SIO_THRM#
A LWON
S NIFFER_PWR_SW#
INSTANT_ON_SW#
MAIN_PWR_SW#
ACAV_IN
1
<41> CLK_TP_SIO
<41> DAT_TP_SIO
<38> CLK_KBD
<38> DAT_KBD
<38> CLK_DOCK
<38> DAT_DOCK
KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7
KSI1/GPIO6
KSI0/SGPIO30
120
119
126
127
128
118
ALWON
POWER_ SW_IN2#
POWER_ SW_IN1#
POWER_ SW_IN0#
ACAV_IN
BGPO0
3
<23> SIO_A20GATE
<24> SIO_THRM#
33
34
35
36
37
38
39
40
C561
10U_0805_6.3V6M~D
R479
100K_0402_5%~D
R632
100K_0402_5%~D
5
4
3
2
1
R498
10K_0402_5%~D
1
5
4
3
Molex_53261
@ JDEBUG1 2
1
2
+3.3V_ALW
C
R497
10K_0402_5%~D
2
1
+3.3V_ALW +3.3V_ALW
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
1
2
1
KSI[0..7]
C560
0.1U_0402_16V4Z~D
2
R628
10K_0402_5%~D
<41>
2
+RTC_CELL
2
DAT_DOCK
2
4.7K_0402_5%~D
C559
0.1U_0402_16V4Z~D
1
CLK_DOCK
2
4.7K_0402_5%~D
1
R488
2
1
1
R487
KSO17/GPIOA1
KSO16/GPIOA0
GPIO5/KSO15
GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KSO6/GPIO2
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0
Keyboard and Mouse Interface
1
R484
DAT_KBD
2
4.7K_0402_5%~D
12
13
14
15
16
17
18
19
20
23
24
25
27
28
29
30
31
32
C558
0.1U_0402_16V4Z~D
R629
100K_0402_5%~D
+5V_RUN
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
2
1
21
44
65
83
116
VCC0
<41> KSO[0..16]
C557
0.1U_0402_16V4Z~D
1
VCC1
VCC1
VCC1
VCC1
VCC1
U48
2
1
C562
1U_0603_10V4Z~D
C556
0.1U_0402_16V4Z~D
D
CLK_KBD
2
4.7K_0402_5%~D
1
121
2
1
R482
R477
100K_0402_5%~D
+RTC_CELL_VCC0
1
B
2
0_0402_5%~D
C
1
4
3
2
Title
EMC5004
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
40
of
59
5
4
3
2
1
+5V_RUN
Touch PAD
TP_CLK
TP_DATA
+5V_RUN
<35>
1 <35>
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
C573
2 0.1U_0402_16V4Z~D
@
2
@
100P_0402_50V8J~D
100P_0402_50V8J~D
2
1
1
2
@
6
5
GND
GND
4
3
2
1
4
3
2
1
2
1
1
2
1
2
4.7K_0402_5%~D
R514
1
1
HRS_FH12-30-14-SA-1SH-55~D
2
DAT_TP_SIO
DAT_TP_SIO <40>
CLK_TP_SIO
1
2
1
2
CLK_TP_SIO <40>
JP6
SP_Y
SP_V+
SP_X
SP_GND
6
5
GND
GND
4
3
2
1
4
3
2
1
HRS_FH12-10(4)SA-1SH(55)~D
IPEX_20413-004E~D
C
SPKER1
Co-lay with JP4
Part Number
PK230005C0L
Description
SPK PACK 00B 1W 8OHM
PCMCIA BODY
Part Number
C648
1
C645
2
100P_0402_50V8J~D
1
C647
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
100P_0402_50V8J~D
SP_Y
SP_V+
SP_X
SP_GND
KSI[0..7]
C
TP_CLK
JP4
C646
<40>
USB_BIOUSB_BIO+
USB_BIOUSB_BIO+
+3.3V_RUN
C644
0.1U_0402_16V4Z~D
<40> KSO[0..16]
L64
BLM11A601S_0603~D
1
2
600ohm,100mA
1
2
L65
BLM11A601S_0603~D
600ohm,100mA
TP_DATA
D
10P_0402_50V8J~D
C627
+3.3V_ALW
PAD-OPEN 4x4m
10P_0402_50V8J~D
C626
2
2
PJP13
LID_CL#1
<40,44> LID_CL#
GND
GND
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10P_0402_50V8J~D
C572
SP_X
SP_Y
SP_GND
SP_V+
10P_0402_50V8J~D
C571
D
4.7K_0402_5%~D
R513
JTPAD
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
@
DC000002T0L
Description
PCMCIA
FOXCONN
1CA86501-CR-4F
Bluetooth wire set cable
Part Number
DC02000980L
Description
H-CONN SET 00B M/B-B/T
MDC wire set cable
Part Number
JKYBRD1
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
B
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DC02000960L
T/P FPC
Part Number
DA300001O1L
Part Number
DC020008Q0L
27
26
2
2
1
2
1
2
Description
B
H-CONN SET 00B MB-LCD 12 WXGA
HDD FPC cable
Part Number
DA300001N1L
Description
FPC 00B LF-3071P REV1 HITACHI
RTC BATT
Part Number
GC020008R00
Description
BATT CR2025 W/CABLE 170MAH MB 00B 0FD
Touch-PAD MODULE
Part Number
Description
PK090003M0L TRACK PAD ALPS KGDDEN010A BIOSENSOR
LED FPC cable
C599
100P_0402_50V8J~D
2
1
C598
100P_0402_50V8J~D
2
1
C597
100P_0402_50V8J~D
2
1
C596
100P_0402_50V8J~D
2
1
C595
100P_0402_50V8J~D
2
1
C594
100P_0402_50V8J~D
2
1
C593
100P_0402_50V8J~D
2
1
C592
100P_0402_50V8J~D
2
1
C591
100P_0402_50V8J~D
2
1
C590
100P_0402_50V8J~D
2
1
C589
100P_0402_50V8J~D
2
1
C588
100P_0402_50V8J~D
1
C587
100P_0402_50V8J~D
1
C586
100P_0402_50V8J~D
2
C585
100P_0402_50V8J~D
2
1
C584
100P_0402_50V8J~D
2
1
C583
100P_0402_50V8J~D
2
1
C582
100P_0402_50V8J~D
2
1
C581
100P_0402_50V8J~D
2
1
C580
100P_0402_50V8J~D
2
1
C579
100P_0402_50V8J~D
1
C578
100P_0402_50V8J~D
2
C577
100P_0402_50V8J~D
C576
100P_0402_50V8J~D
C575
100P_0402_50V8J~D
2
1
Description
FPC 00B LF-3072P REV1 T/P FPC WITH BIO
LCD cable
HRS_FH28D-25SB-1SH~D
1
Description
H-CONN SET 00B M/B-MDC
Part Number
Description
1
DA300001S1L
FPC 00B LF-3073P REV1 LED FPC
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
INT KB & FT & LID & TOUCH PAD
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
41
of
59
5
4
3
2
1
DC/DC Interface
+3.3V_SUS Source
+15V_SUS
+3.3V_SUS
+3.3V_SRC
1
SUS_ON 2
G
S
SUS_ON_5V# 2
G
Q38
2N7002W-7-F_SOT323~D
Q39
2N7002W-7-F_SOT323~D
R518
20K_0402_5%~D
2
S
Run Planes Enable
+5V_RUN Source
1
+3.3V_RUN
Q43
SI4800DY-T1-E3_SO8~D
S
@
S
1
R531
1K_0402_5%~D
2
+2.5VRUN_DIS
2
+0.9VDDR_DIS
1
2
+1.5VRUN_DIS
@
D
S
2
G
@
Q50
2N7002W-7-F_SOT323~D
S
D
2
G
@
1
@
@
3
S
1
2
+3.3VRUN_DIS
@
D
2
G
+2.5V_RUN
3
1
S
D
2
G
@
Q48
2N7002W-7-F_SOT323~D
2
D
2
G
1
1
D
2
G
@
3
RUN_ON_5V#
3
R525
20K_0402_5%~D
1
1
1
1
2
C605
10U_0805_10V4Z~D
Q44
SI3456DV-T1-E3_TSOP6~D
3
G
4
3
D
S
6
5
2
1
B
Q45
2N7002W-7-F_SOT323~D
+1.8V_RUN Source
+1.8V_RUN
+1.8V_SUS
@
+5VRUN_DIS
2
@
+0.9V_DDR_VTT
R530
1K_0402_5%~D
+1.5V_RUN
Q49
2N7002W-7-F_SOT323~D
+1.8V_RUN
R529
1K_0402_5%~D
+3.3V_RUN
2
C692
470P_0402_50V7K~D
+5V_RUN
R528
1K_0402_5%~D
1
Discharge Circuit
R523
20K_0402_5%~D
2
+1.8VRUN_DIS
2
1
1
1
4
R633
200K_0402_5%~D
1
2
3
Q47
2N7002W-7-F_SOT323~D
8
7
6
5
2
3
1
Q42
2N7002W-7-F_SOT323~D
+3.3V_RUN Source
+3.3V_SRC
1
3
C
R527
1K_0402_5%~D
2
2
3
S
D24
MMBD4148W-7-F_SOT323~D
Q46
2N7002W-7-F_SOT323~D
3
1
D
2
G
<19,40,43,47,48,49> RUN_ON
1
R522
20K_0402_5%~D
2
1
D
2
G
Q41
S
2N7002W-7-F_SOT323~D
C602
4700P_0402_25V7K~D
1
RUN_ENABLE
RUN_ON_5V#
1
1
4
2
2
<47> RUN_ENABLE
2
R521
100K_0402_5%~D
+5V_RUN
C603
10U_0805_10V4Z~D
R520
100K_0402_5%~D
C601
10U_0805_10V4Z~D
Q40
SI4800DY-T1-E3_SO8~D
8
1
7
2
6
3
5
1
1
+5V_SUS
R526
1K_0402_5%~D
+15V_SUS
+5V_ALW
C
D
2
3
<40,43,47> SUS_ON
D
3
1
2
SUS_ENABLE
D
1
4
2
R519
100K_0402_5%~D
D
1
2
1
R517
100K_0402_5%~D
C600
10U_0805_10V4Z~D
1
+5V_ALW
Q37
STS11NF30L_SO8~D
8
1
7
2
6
3
5
B
@
+1.8V_SUS
+PWR_SRC
1
1
+PWR_SRC
R619
22_0805_5%~D
1
R532
100K_0402_5%~D
+1.8VSUS_DIS
1
1
SUS_ON_5V#
D
3
S
R534
470K_0402_5%~D
2
3
1
3
S
R535
200K_0402_5%~D
2
1
A
D
2
G
Q52
2N7002W-7-F_SOT323~D
<40,47> AUX_EN
D
2
G
Q51
2N7002W-7-F_SOT323~D
1
2
ENAB_3VLAN <29>
N21917830
S
2
G
Q69
2N7002W-7-F_SOT323~D
2
2
R533
100K_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
POWER CONTROL
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
42
of
59
5
4
+5V_SUS
3
2
1
At S3 step back-drive: 78mV, change to SI2303
SI2303BDS-T1-E3_SOT23-3~D
3
R621
S
+5V_RUN
G
2
Q70
1
1
D
200K_0402_5%~D
C
R622
Q71
MMST3904-7-F_SOT323~D
2
B
4.7K_0402_5%~D
3
E
D
D
3
+3.3V_SUS
Q72
DDTA114EUA-7-F_SOT323~D
Follow Travis to
modify
C617
0.01U_0402_16V7K~D
8
U52C
P
3
+3.3V_SUS
5
Y
G
A
74LVC3G14DC_VSSOP8~D
1
1
2
D
OUT
U53A
74VHC08MTCX_NL_TSSOP14~D
3
IN2
+3.3V_SUS
14
5
<19,40,42,47,48,49> RUN_ON
IN1
OUT
At S3 step back-drive:198mV, change to SI2303
6
RUNPWROK
RUNPWROK <39,40,50>
IN2
7
C
U53B
P
4
<48> 1.05V_RUN_PWRGD
G
<48> 1.5V_RUN_PWRGD
E
3
2
B
4.7K_0402_5%~D
Q75
MMST3904-7-F_SOT323~D
IN1
C616
0.1U_0402_16V4Z~D
2
7
1
<18> 2.5V_RUN_PWRGD
C
R627
P
14
74LVC3G14DC_VSSOP8~D
G
2
2
Y
G
A
4
R589
0_0402_5%~D
R588
0_0402_5%~D
2
1
1
2
G
Q74
R587
0_0402_5%~D
2
1
S
3
6
1
SI2303BDS-T1-E3_SOT23-3~D
1
8
5V_3V_RUN_PWRGD
E
+1.8V_SUS
100K_0402_5%~D
U52B
P
Q73
MMST3904-7-F_SOT323~D
3
1
2
B
4.7K_0402_5%~D
2
+3.3V_SUS
2
C
R624
+1.8V_RUN
R626
R536
20K_0402_5%~D
1
200K_0402_5%~D
+3.3V_SUS C613
0.1U_0402_16V4Z~D
1
2
4
2
1
+3.3V_RUN
+3.3V_RUN
R623
C
74VHC08MTCX_NL_TSSOP14~D
<40,42,47> SUS_ON
+3.3V_SUS
1
<49> SUSPWROK_1P8V
1
C624
0.1U_0402_16V4Z~D
14
1
S
A
Y
7
12
IN1
OUT
4
2
G
74LVC3G14DC_VSSOP8~D
11
SUSPWROK <18,24>
IN2
G
D
U53D
P
13
74VHC08MTCX_NL_TSSOP14~D
Q63
2N7002W-7-F_SOT323~D
2
1
+3.3V_SUS
U52A
G
2
R557
10K_0402_5%~D
U53C
74VHC08MTCX_NL_TSSOP14~D
+3.3V_SUS
P
ICH_PWRGD <10,24>
1
IN2
8
3
OUT
8
1
IN1
7
9
+3.3V_SUS
R556
100K_0402_5%~D
2
14
RESET_OUT#
<40> RESET_OUT#
P
10
G
IMVP_PWRGD
<24,50> IMVP_PWRGD
R537
0_0402_5%~D
1
2
7
+3.3V_SUS
1
2
R538
100K_0402_5%~D
B
ICH_PWRGD# <18>
B
2
G
S
+COINCELL
Q53
2N7002W-7-F_SOT323~D
COIN RTC Battery
1
3
ICH_PWRGD
ICH_PWRGD#
D
JCOIN1
+COINCELL
3
2
Z4012
+3.3V_RTC_LDO_1
2
R539
1K_0402_5%~D
+RTC_CELL
1
2
1
2
3
4
GND
GND
MOLEX_53780-0270~D
1
D16
BAT54CW_SOT323~D
1
2
C618
1U_0603_10V4Z~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power Good
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
43
of
59
5
4
H1
H2
H3
H4
H5
H6
H7
@H_C315D126 @H_C315D126 @H_C315D126 @H_C315D126 @H_C315D126 @H_C315D126 @H_C315D126
H8
@H_C315D126
3
2
FD1
FD2
FD7
H14
H_C236D91
H15
H_C236D91
MYLAR1
FD8
Part Number
FD13
Description
HAU30_DOCKING_HOLE_MYLAR
MYLAR2
H18
@ H_C315D126
EL00B00050L
Part Number
EL00B00060L
FD11
FD12
1
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD15
1
FIDUCIAL MARK~D
FD16
1
FIDUCIAL MARK~D
FD17
1
FD18
1
FIDUCIAL MARK~D FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
D
MYLAR6
Description
Part Number
HAU30_DOCKING_LOCK_L_MYLAR
FD19
FIDUCIAL
MARK~D
1
Description
FD20
FIDUCIAL
MARK~D
1
FD21
FD22
1
FD23
1
FD24
1
1
HAU30_MYLAR_HDD
EL00B000X00
MYLAR3
1
H17
@H_C472D431X376
1
1
H16
@H_C472D376
1
FIDUCIAL MARK~D
HAU30_MYLAR_WLAN_WWAN
EL00B000N00
D
Part Number
FD10
1
FIDUCIAL MARK~D FIDUCIAL MARK~D
FD14
1
EL00B00040L
FD9
1
FIDUCIAL MARK~D
FD6
1
FIDUCIAL MARK~D
MYLAR5
Description
1
1
1
1
1
Part Number
FD5
1
FIDUCIAL MARK~D FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
FD4
1
FIDUCIAL MARK~D
1
H12
H13
@H_C236D126 H_C236D91
FD3
1
FIDUCIAL MARK~D
1
1
1
1
1
1
1
1
1
1
1
H11
H_C236D91
1
Fiducial Mark
H9
H10
@H_C315D126 @H_C315D126
FIDUCIAL MARK~D FIDUCIAL MARK~D
FIDUCIAL MARK~D
FIDUCIAL MARK~D
MYLAR7
Description
Part Number
HAU30_DOCKING_LOCK_R_MYLAR
Description
FD25
FD26
1
HAU30_MYLAR_FAN
EL00B000A0L
FD27
1
FIDUCIAL MARK~D
FD28
1
FIDUCIAL MARK~D
FD29
1
FD30
1
FIDUCIAL MARK~D FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
MYLAR4
Part Number
MDC Cable latch
EL00B00070L
Description
FD31
+3.3V_RUN
HAU30_MYLAR_DDR2
FD32
1
JPSW
POWER_SW_LED 1
POWER_SW#
2
3
1
<18,38,40> POWER_SW#
FIDUCIAL MARK~D
4
5
1 GND
2 GND
3
3
FIDUCIAL MARK~D
MOLEX_53780-0370~D
CLP1
EMI_CLIP
CLP2
EMI_CLIP
1
GND
1
IDE_ACT#
<26> IDE_ACT#
2
Q54
DDTA114EUA-7-F_SOT323~D
GND
CLP4
EMI_CLIP
1
GND
1
2
R540
47_0402_5%~D
<38> R_PIDEACT
1
LED1
LTST-C190KGKT_GRN_0603~D
1
1
CLP3
EMI_CLIP
GND
2
JPLID
+3.3V_ALW
<40,41> LID_CL#
1
2
3
LID_CL#
4
5
1 GND
2 GND
3
MOLEX_53780-0370~D
RUBBER1
HAU30_MIC_RUBBER
RUBBER2
EL00B000O00
2
R546
R_NUM_LED#
1
510_0402_5%~D
<40> SCRL_LED#
2
R548
R_SCRL_LED#
1
510_0402_5%~D
2
DDTA114EUA-7-F_SOT323~D
Q55
SCREW1
Part Number
MAAA00153G0
Description
R541
10K_0402_5%~D
1
2
SCREW M M 2.0D 3.0L K 4.6D ZK NL + CR3+
+3.3V_ALW
Q67
DDTA114EUA-7-F_SOT323~D
2
11
12
GND
GND
HRS_FH12-10S-0.5SH(55)~D
3
Q56
PMST3906_SOT323-3~D
1
C
2 POWER_SW_LED
51_0402_5%~D
1
Q68
R615
MMST3904-7-F_SOT323~D
E
3
2
<40> SNIFFER_LED_OFF#
+3.3V_SUS
+3.3V_RUN
2
R543
51_0402_5%~D
3
R_SCRL_LED#
R_CAP_LED#
R_NUM_LED#
1
2
3
4
5
6
7
8
9
10
1
+3.3V_RUN
1
2
3
4
5
6
7
8
9
10
R616
10K_0402_5%~D
1
2
2
B
<36> LED_WLAN_OUT#
GND
GND
IPEX_20403-010E~D
2 1
11
12
B
JP10
BT_ACT
WLAN_ACT
2
B
R_SCRL_LED#
R_CAP_LED#
R_NUM_LED#
1
2
3
4
5
6
7
8
9
10
BSS138W-7-F_SOT323~D
Q78
BT_LED_DIS#
E
+3.3V_RUN
1
2
3
4
5
6
7
8
9
10
S
2 BT_ACT
1K_0402_5%~D
1
R542
@ R636
10K_0402_5%~D
C
JLED1
BT_ACT
WLAN_ACT
D
2
G
3
<34,36> BT_ACTIVE
+3.3V_SUS
1
<40> NUM_LED#
CAP_LED#
1
2
R545
<40>
Description
HAU30_RUBBER_MDC
3
Part Number
R_CAP_LED#
1
510_0402_5%~D
C
+5V_RUN
1
FH00B00060L
Description
1
Part Number
3
C
2
Q58
DDTA114EUA-7-F_SOT323~D
B
LED3
LTST-C190KGKT_GRN_0603~D
2
R547
WLAN_ACT
1
510_0402_5%~D
1 1
1
Co-lay with JLED1
R544
10K_0402_5%~D
1
2 BREATH_LED_B
<40> BREATH_LED
C
Q57
MMST3904-7-F_SOT323~D
2
B
+3.3V_ALW
3
E
+3.3V_ALW
1
JSNIFF
2
3
R549
10K_0402_5%~D
2
<39> SNIFFER_WIRELESS_ON/OFF#
GND
4
4
3
3
2
2
1
1
<40> BAT2_LED#
BAT2_LED#
2
Q59
DDTA114EUA-7-F_SOT323~D
1
1
DDTA114EUA-7-F_SOT323~D
Q60
GND
5
<40> SNIFFER_SW#
S NIFFER_SW#
+3.3V_ALW
1BS008-13130-002-7F_4P~D
<40> BAT1_LED#
+3.3V_SUS
R550
1
3
<18> SNIFFER_GREEN#
SNIFFER_GREEN#
6
3
+3.3V_SUS
BAT1_LED#
BATT_AMBER_LED
2
330_0402_5%~D
2
LED5
3
2
G
1
1
4
O
3
Q61
DDTA114EUA-7-F_SOT323~D
A
A
2
SNIFFER_G
2
1
SNIFFE R_Y
3
1
Q62
DDTA114EUA-7-F_SOT323~D
R552
220_0402_5%~D
1
2
2
LTST-C155KGKFKT_GRN/ORG~D
12-22AUYSYGC/530-A2/TR8_G/Y~D
1
DELL CONFIDENTIAL/PROPRIETARY
Y
SNIFFER_YELLOW#
D18
R553
220_0402_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
BATT_GREEN_LED
2
56_0402_5%~D
G
<18> SNIFFER_YELLOW#
1
R551
4
3
2
Title
PAD and Standoff
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
44
of
59
8
7
6
5
4
3
2
1
IMVP-6 solution for Yonah ULV: 1-phase/9A
PL13
FBMA-L11-321611-800LMA40T
+PWR_SRC
H
H
1
PC85
4700P_0402_25V7K
1
2
GNDA_CORE
PWRGD
DCM
28
OD
27
5
FBRTN
PWM1
26
6
FB
PWM2
25
7
COMP
PWM3
24
8
SS
SW1
23
STSET
SW2
22
DPRSLP
SW3
21
ADP3207JCP-RL_LFCSP-40
B
PR115
@ 100_0402_5%~D
1
2
6
1
4
2
3
3
2
1
PC137
15U_D2_25M_R90~D
4
F
1
2
3
1
3
PC80
10U_1206_25V6M~D
2
1
PC79
10U_1206_25V6M~D
2
1
PC78
0.1U_0805_25V7K~D
2
1
PC77
1000P_0402_50V7K~D
2
1
5
6
7
8
PQ15
IRF7821_SO8~D
4
PR85
0.001_2512_1%~D
ADP3207_CSREF
DRVL
@ PQ27
FDS7088SN3_SO8~D
7
ADP3419JRM_MSOP-10
PQ17
@ 2N7002_SOT23~D
Rdson_typ
4.8mohms
ADP3207_VRTT
ADP3207_#DCM
ADP3207_PWM1
PWM2, PWM3 pull high
PR102
2
0_0402_5%~D
1
Single Core
(YONAH ULV)
GND
NOTE
Dual Core
(YONAH ULV)
PR108
12K_0402_1%
1
2
Dual Core
(MEROM ULV)
@5.76K_0402_1%~D
GNDA_CORE
SW
GND
9
8
7
6
5
VCC
PC76
0.33U_0603_10V7K
2
1
PR80
0_0603_5%~D
1
2
5
20
CSCOMP
19
CSSUM
18
ADP3207_CSSUM
CSREF
17
ADP3207_CSREF
RAMPADJ
RT
LLSET
16
ADP3207_RAMPADJ 15
1
2
PC95
1000P_0402_50V7K~D
2
1
GNDA_CORE
PR113
@ 100_0402_5%~D
1
2
+VCC_CORE
CROWBAR
0.88UH_MPC1040LR88_17A_20%~D
PL14
1
2
AD3419_SW1
1. Choke: PL14 is 0.88u H
2. MOS: PQ27
3 .PR104 is 309K.(OCP:14A)
4. PR114 is 2.37K.(Load Line: -5.1m)
5. PR101 is 10K.
6. PR88 is 820P ; 8. STUFF PC80
7. PR90 is 390P.
D
GNDA_CORE
1
2
PR110 280K_0402_1%
14
GNDA_CORE
VSSSense <8>
S
0_0402_5%~D
RRPM
VRPM
VCCSense <8>
D
PR112
2
GNDA_CORE
NOTE:PR111 is reversed for loop
gain measurement purpose
13
11
PR104
@ 215K_0402_1%
2
1
PR107
0_0402_5%~D
C
309K_0402_1%
PC94
1
2
1000P_0402_50V7K~D
2
1
PR105
160K_0402_1%~D
1
2
PR106
392K_0402_1%
1
2
GNDA_CORE
12
ILIMIT
2
1
@ 470P_0402_50V7K
PC90
390P_0402_50V7K
PC89
0.015U_0402_16V7K
2
1
1
GNDA_CORE
PR103
0_0402_5%~D
DRVLSD#
4
8
G
+VCC_CORE
@ 0.45U_MPC1040LR45_27A_20%~D
AD3419_DRVH1
9
8
7
6
5
VRTT
29
CLKEN
PR141
3
10
9
1
2
3
30
PGDELAY
499_0402_1%
<24> DPRSLPVR
BST
DRVH
+
2
E
TTSENSE
3
10
SD#
ADP3207_TTSENSE
31
GNDA_CORE
VCC
2
2
32
PSI
33
2
@
DPRSTP
34
VID6
2
36
35
VID5
VID4
VID3
PR150
0_0402_5%~D
1
2
4
9
IN
2
1
2
G
EN
2
1
4
AD3419_DRVL1
1
2
PC86
100P_0402_50V8K
2
1
PR100
PC88
PC87
1K_0402_1%
820P_0402_25V8K
2
1
1
2 1
2 27P_0402_50V8K
@ 470P_0402_50V7K
PR101
10K_0603_0.1%~D
@20K_0603_1%~D
D
PC75
4.7U_0805_10V6K
2
1
PC82
1U_0805_25V4Z~D
2
1
E
PC84
1000P_0402_50V7K~D
1
2
GNDA_CORE
PU4
1
+CPU_PWR_SRC
0_0402_5%~D
1
2
1
PR930_0402_5%~D
1
PR940_0402_5%~D
1
PR950_0402_5%~D
1
PR960_0402_5%~D
1
PR970_0402_5%~D
2
37
38
40
PU5
VID0
<39,40,43> RUNPWROK
PR99
0_0402_5%~D
2
1
39
VID0
PR91
0_0402_5%~D
1
2
1
2
PR92
0_0402_5%~D
1
2
PR98
0_0402_5%~D
VID2
<8>
PR88
0_0402_5%~D
2
1
VID1
1
IMVP6_PROCHOT# <39>
PR87
@
<24,43> IMVP_PWRGD
<6> CLK_ENABLE#
<39,40,43> RUNPWROK
GNDA_CORE
<8>
H_PSI#
<7,23> H_DPRSTP#
<8>
VID6
<8>
VID5
<8>
VID4
<8>
VID3
<8>
VID2
<8>
VID1
1.91K_0402_1%~D
2 PR90
@
GNDA_CORE
GNDA_CORE
@
+3.3V_RUN
F
PR89
1.91K_0402_1%~D
2
1
PR82
10_0603_5%
2
1
PC81
0.01U_0402_25V7K~D
2
1
PR81
0_0402_5%~D
1
Thermistor PH1 should be placed
close to the hot spot of the VR
PH1
100K_0603_5%_TH11-4H104FT
2
1
@
2
G
PD14
RB751V-40_SOD323~D
AD3419_BST1
2
1
+5V_RUN
PQ16
+5V_RUN
@
IRF7832_SO8~D
PR79
7.32K_0603_1%
2
1
2
+PWR_SRC
PR114
1.
2.
3.
4.
5.
6.
7.
Choke: PL14 is 0.45u H
MOS: PQ27.
PR104 is 215K.(OCP:20A)
PR114 is 5.76K.(Load Line: -2.1m)
PR101 is 20K.
PR88 is 470P ; 8. NO-STUFF PC80
PR90 is 470P.
1.
2.
3.
4.
5.
6.
7.
Choke: PL14 is 0.45u H
MOS: PQ16 and PQ27
PR104 is 215K.(OCP:20A)
PR114 is 5.76K.(Load Line: -2.1m)
PR101 is 20K. ;8. NO-STUFF PC80
PR88 is 470P
PR90 is 470P.
C
B
NOTE: ( Connection VCORE output Cap GND)
De-populate PR113 and PR115 when CPU is present
PR134
0_0603_5%~D
2
1
A
PC96
1000P_0402_50V7K~D
2
1
2.37K_0402_1%~D
2
1
DELL CONFIDENTIAL/PROPRIETARY
A
Compal Electronics, Inc.
Title
GNDA_CORE
+VCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GNDA_CORE
Size
7
6
5
4
3
Rev
1.0
LA-3071P
Date:
8
Document Number
2
Friday, May 12, 2006
50
Sheet
1
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
C
B
A
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
H_DPRSTP# & H_DPSLP# not need pull
down resistor for Intel request
SO-DIMMA SM Bus address define need change
from A4 to A2 for 945GMS DDR support one
channel issue.
Remove R85,R86
0.2
Change R135 from pull down to pull up +3.3V_RUN
Change R136 from pull up to pull down and change from 100K to 10K
0.2
Steve
Touch PAD module issue
Change JTPAD1.14 from +3.3V_RUN to GND
0.2
Steve
Power sequence issue that +1.8V_RUN too
late on +VCC_CORE
Remove R524,C604
1
7
H/W
10/14
INTEL
2
15
H/W
10/14
Steve
3
41
H/W
10/14
4
42
H/W
10/14
0.2
5
43
H/W
10/14
Steve
Add +5V,+3V,+1.8V_RUN power sequence
schematic to control sequence
Add R621,R622,R623,R624,R626,R627,Q70,Q71,Q72,Q73,Q74,Q75
0.2
6
17
H/W
10/15
Steve
945GMS support CKE0,CS0#,ODT0 to control
on board RAM,so remove CKE1,CS1#,ODT1
Remove RN76,RN80 and add R625,previously T13,T14,T15 for
DDR_CKE1,DDR_CS1#,M_ODT1
0.2
7
39
H/W
10/15
Steve
Change BID from X00 to X01
Un-pop R473,pop R469
0.2
8
44
H/W
10/15
Steve
Remove CAP,NUM,SCRL,BT,WLAN LED from M/B
to FFC and CAP,NUM,SCRL direct driving LED
from MEC5004.
Remove LED6,LED7,LED8,LED9,LED10,Q64,Q65,Q66,add JLED1
0.2
9
19
H/W
10/17
Steve
945GMS control panel backlite (BIA_PWM),
the voltage level is 3.3V, so don't need
add component for voltage level shift.
Remove U54
0.2
10
40
H/W
10/17
Steve
Resolve EC code damage issue
Reserved R628,R629,R630,R631,R632,C691,Q76,Q77,D22(depop)
0.2
11
31
H/W
10/27
Steve
Follow M07_R5C843 refer schematic to
modify.
Change C424,C425 from 22P to 12P
0.2
12
42
H/W
10/27
Steve
Resolve IMVP_PWRGD glitch during power
on/S3 resume
Add R633,C692
0.2
13
9
H/W
10/27
Steve
For Dual Core CPU action
Reserved C693,C694,C695,C696,C697,C698,C699,
C700,C701,C702,C703,C704,C705,C706(depop)
0.2
14
36
H/W
10/27
Steve
Support WoW function for prevent backdrive. Add D23,no pop R634
0.2
15
34
H/W
10/27
Steve
Keep the BT LED off when the SNIFFER is
turned on.
Add R635,R636,Q78
0.2
16
40
H/W
10/31
Steve
Resolve EC flash corruption issue.
Add R637 to pull down.
0.2
17
9
H/W
11/1
Steve
Support one core CPU that follow Intel
reqeust just pop 8pcs of 22uF MLCC Cap.
Pop C21,C23,C26,C28,C29,C31,C34,C36
0.2
18
42
H/W
11/3
Dell
Correct C692 value
Change to 470PF
0.2
19
34
H/W
11/3
Dell
SNIFFER_LED_OFF# should be pull up to
+3.3V_SUS
Change to pull up power source from +5V_SUS to +3.3V_SUS
0.2
20
36
H/W
11/7
CoE
Nimi-Card Reset change to PLTRST#
Follow CoE M07-Nimicard-a07
0.2
21
36
H/W
11/7
CoE
Nimi-Card WLAN COEX2_WLAN_ACTIVE AND
COEX1_BT_ACTIVE ADD 0 ohms: R638 and
R639
Follow CoE M07-Nimicard-a07
B
A
0.2
Title
4
C
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
D
3
2
Changed-List History 1
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
52
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
C
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
22
36
H/W
11/7
CoE
C685 STUFFED
Follow CoE M07-Nimicard-a07
0.2
23
32
H/W
11/7
CoE
SIM Module C505, C506, C507, C508 Change to
33P_0402, and C508 stuffed
Follow CoE M07-Nimicard-a07
0.2
24
44
H/W
11/7
Steve
Sniffer LED Indicator Error
Swap D18 pin2,3 of LED
0.2
25
24
H/W
11/8
CoE
R370 Move to ICH7 side
Follow CoE M07-ICH a07
0.2
26
31
H/W
11/8
CoE
C428, C429, C430 add the note to close connector
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
27
31
H/W
11/8
CoE
C424, C425 add a note to change the value after
measure the starting value
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
28
31
H/W
11/8
CoE
C431 change from 0.01u to 0.1u
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
29
31
H/W
11/8
CoE
+SD_VCC change to +3.3V_RUN_CARD
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
30
32
H/W
CoE
VCC_PCI/ VCC_MD3V add C707_0.01u
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
31
32
H/W
11/8
CoE
R389_100 remove
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
32
32
H/W
11/8
CoE
C448/ C449 /C684 change to 0.01u_0402
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
33
32
H/W
11/8
CoE
VCC_CBS add C708_10u and C709_0.01u
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
34
32
H/W
11/8
CoE
FollowM07_R5C843_REF_SCHEMATICS_A00
0.2
35
44
H/W
11/8
CoE
Bluetooth LED disable function when Sniffer Active
update, follow travis: R636 pull-up to +3.3_ALW,
Q56 --> 3906, R635 --> remove. But depop R636
Follow Travis
0.2
36
29
H/W
11/9
Brocadcom
Change RDAC for Broadcom request.
Change R338 from 1.15K to 1.18K.
0.2
37
34
H/W
12/8
Steve_Wang
Resolve Bluetooth LED always light
Pop R408
0.3
38
9
H/W
12/8
Steve_Wang
Separate BOM type for different CPU.
Pop 1@ for Signal core 1.06G
Pop 2@ for Singal core 1.2G
Pop 3@ for Dual core 1.06G
0.3
39
29
H/W
12/13
Steve_Wang
Prevent Q23 damage issue for transfor +3.3V_LAN to
+2.5V_LOM
Add R640,C710
0.3
40
20
H/W
12/13
Steve_Wang
Resolve DVI test fail issue
41
26
H/W
12/13
Steve_Wang
Resolve HDD_EN# have spike when power on
Change R279 from 100K to 4.7K
0.3
42
39
H/W
12/13
Steve_Wang
Change BID from X01 to X02
Unpop R469,R474; pop R470,R473
0.3
11/8
+VCC_CBS rename to VCC_CBS, +CBS_VPP rename to CBS_VPP
D
C
B
A
B
1.
2.
3.
4.
Change C245,C236 from 0.1U to 10U
Change R169,R170,R171,R172 from 300ohm to 110ohm
Change R175 from 300ohm to 220ohm
Pop C238,C247
0.3
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Changed-List History 2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
53
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
C
B
A
Title
Date
Request
Owner
Issue Description
Solution Description
43
39
H/W
12/14
CoE
C638 STUFFED
44
26
H/W
12/14
CoE
Change HDD_EN# signal from ICH to SIO
45
24,40
H/W
12/16
46
31
H/W
12/19
CoE
MikeCC_Huang
Rev.
Follow CoE M07_EC_Latitude_A07
1.Change HDD_EN# from ICH to ECE5018 pin106.
2.Add R644 to pull-up +3.3V_ALW
3.Delete R279 to pull-down
4.Rename signal at ICH to RSVD_HDDC_EN# and add Test Point
0.3
SPI_CS# have spike over 4.5V when power on
Add R641,R642 damping to prevent.
0.3
Measure SD EA find Data overshot,undershot over 3.3V
Add R645,R646,R647,R648 damping to meliorate.
0.3
47
21
H/W
12/20
DELL
+CRT_VCC current limit issue
Add 1206 Res of R649.
0.3
48
28
H/W
12/21
DELL
Fine tuning AUD_LINE_OUT signal
Change C368 from 0.0047u(X5R) to 4700P(X7R)
0.3
49
24
H/W
12/21
DELL
Follow DELL request
Change R265 contact from R641 pin1 to pin2
0.3
50
27,28
H/W
12/21
DELL
Follow DELL request
Change Auido by-pass cap to X5R
0.3
51
18
H/W
12/21
DELL
Follow DELL request
Add VSET,LDO_SET note
0.3
52
21
H/W
12/21
COE
Follow COE M07_CRT_LVDS_DVI rev A07schematic
Add R650,R651
0.3
53
42
H/W
12/21
COE
Follow COE M07_System power sequence_A07 schematic
0.3
54
43
H/W
12/21
COE
Follow COE M07_System power sequence_A07 schematic
Add D24 for fast turn Off FET
Change Q63 from MMBT3904 to 2N7002 that it
has good margin to turn
55
28
H/W
12/22
COE
Follow COE M07_AUDIO_A05 schematic
Add EAPD signal & Q79 for power saving control
0.3
56
29
H/W
12/23
Crystal EA
Follow vendor suggest to modify resistor to match
crystal negative resistor EA
Change R334 from 200 to 330ohm
0.3
57
31
H/W
12/23
Crystal EA
Follow vendor suggest to modify cap to match
crystal EA
Change C424,C425 from 12P to 18P.
0.3
58
21
H/W
12/23
RGA EA
For 1pix 1600x1200 rising/falling time over spec issue
Change L18,L19,L20 from 60ohm to 22ohm
0.3
Crystal EA
Follow vendor suggest to modify crystal
Change Y1 from 24MHz_20pF to 24MHz_12pF
1.Change R342,R343,R344,R345,R346,R347,R348,R349 from
49.9 to 48.7ohm
2.Change L39,L40,L41,L42,L43,L44,L45,L46 from 24NH to
39NH
0.3
39
H/W
12/23
60
30
H/W
12/26
DELL
Follow DELL resolution of test Media Slice,APR,DAPR
return loss issue
61
30
H/W
2/18
EMI
EMI test ISN of LAN on 10/100 item fail.The solution
are pop C421,C422 and change C419~C422 character from
Y5Vto X5R
1.Pop C421,C422
2.Change C419~C422 character from Y5V to X5R
0.4
62
31
H/W
2/18
System can't boot issue.
Unpop R609
0.4
63
28
H/W
2/27
DELL
Follow DELL request to modify amplifier gain from
10db to 15.6db for fix small sound on speaker issue
Unpop R311,R312; pop R310,R313
0.4
64
28
H/W
2/27
DELL
Follow DELL request to modify cap value from
0.047u to 4700p for best pop and click performance
65
9
H/W
3/2
DELL
66
12
H/W
3/2
DELL
67
32
H/W
3/6
DELL
Follow Intel document to modify 330u 7mohm to 6mohm
C
0.3
59
STEVE_WANG
D
0.3
B
0.3
0.4
Change C367,C369,C371 from 0.047U to 4700P
Change C41,C42,C43,C44,C705,C706 from 330U 7mohm to 6mohm
Follow DELL request to add shunt caps between LVDS signal. Add 10P_0402 of C711,C712,C713,C714
Add schematic of
DELL support Express USB Card can't work on R5C843
U62,U63,U64,U65,C715,C716,C722,C723,R652,R654,R655
issue.
0.4
A
0.4
0.4
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Changed-List History 3
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
54
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
C
B
Title
Date
3/7
Request
Owner
68
39
H/W
69
18
H/W
3/9
70
31
H/W
3/10
71
27
H/W
3/10
72
28
H/W
3/10
73
28
H/W
3/10
74
28
H/W
3/10
75
35
H/W
3/10
76
35
H/W
3/10
Mikecc_Huang
77
32
H/W
4/10
Mikecc_Huang
78
41
H/W
4/10
79
39
H/W
4/10
80
6
H/W
4/17
81
29
H/W
4/21
Issue Description
DELL
Thermal
Solution Description
Rev.
DELL support Express USB Card can't work on R5C843
issue.
Reserve 0ohm of R653 for control Express card detect.
0.4
Modify OTP thermal shut down to 91 degree.
Change R157 from 41.2K to 68K
0.4
SD bus signal overshoot/undershoot over spec.
Add C717,C718,C719C720
0.4
SIGMATEL
Follow sigmatel request to add cap for SENSE_A signal
Add 1000P cap
0.4
SIGMATEL
Follow sigmatel request to add NB_MUTE signal for
control MAX4411 shutdown.
Add Q80 of NB_SENSE signal to control MAX4411 shutdown
0.4
SIGMATEL
Follow sigmatel request to add ESD diode for avoid
High pol
Reserve D25
0.4
SIGMATEL
Follow sigmatel request for MIC BIAS.
Unpop
0.4
Modiy USB_BIO-/USB_BIO+ ESD IC to choke
Add R657,R658; reserve L67,C724,C725; delete U55
0.4
Advoid LID_CL# have some error on ALPS touchpad module.
Add PJP13
0.4
Result remove PCMCIA Card can't reduce default issue
Add R659
1.0
Improve LVDS for 3 dB (CDMA, GSM) at 1900 band
1.0
Mikecc_Huang
DELL
DELL
R299,R300
Steve_Wang
Change Board ID from X02 to A00
Pop C575~C599
Change C712,C713,C714 from 10P to 3.3P.
Pop R473,R474,R471;unpop R469,R470,R475
Steve_Wang
Result WWAN noise issue
Change R35,R36,R32,R34,R605 from 15ohm to 39ohm
Change R37,R38,R39,R48 from 33ohm to 56ohm
1.0
Add cap for damp power-up surge current
Add C726 of 4700P Cap.
1.0
DELL
82
6
H/W
4/28
DELL
83
6
ME
4/28
CT_Huang
84
9
Power
4/28
Kenneth_Chang
85
44
H/W
5/9
Steve_Wang
86
44
H/W
5/12
Steve_Wang
D
C
1.0
Result WWAN noise issue
Unpop R561
1.0
Avoid FPC easy to remove from connector
Add JP6,JP10 that co-lay with JP4,JLED1
1.0
Result DC CPU noise
Remove C24,C32,C695,C696,C701,C702
1.0
Result HDD,Power,Battery Charger,Bluetooth,WLAN LED
lightness irregularity issue
Change R615,R543 to 51ohm,R540 to 47ohm;R542,R547
to 330ohm,R551 to 56ohm
1.0
Result NUM,CAP,SCRL,Bluetooth,WLAN LED
brightness irregularity issue
Change R545,R546,R547,R548 to 510ohm,R542 to 1Kohm
1.0
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Changed-List History 4
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
55
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
1
51
PWR
10/14
Kenny
2
51
PWR
10/14
Kenny
PWR
10/27
3
4
5
51
51
PWR
51
PWR
10/27
10/27
Kenny
Kenny
Kenny
Issue Description
Solution Description
Rev.
Add PR154 154K_0402_1% (SD03415438L) connect
net (ADAPT_TRIP_SEL) to PU9_2
Add net name "ADAPT_TRIP_SEL"
0.2
FBSA of the MAX8731 for dV/dt filtering
per DELL's recommendation
Add PC135 0.01U_0603_25V (SD03415438L) connect FBSA to GND
0.2
Moved battery voltage feedback to charge
states
Connected pins 15 and 16 together changed connection to +VCHGR.
Add PR155
0.2
For support Adapter 45W
Added layout notes for PC135 and PC136
D
0.2
Adjusted the current setting of the "UL"
circuit and added hysteresis
change value of the PR142 from 499K to 4.32M,
change value of the PR148 from 33.2K to 27.4K
Adjusted the Load line setting
change value of the PR108 from 249K to 12K,
change value of the PR114 from 48.7K to 2.37K
Remove PC93
0.2
Change value of the PR106 from511K to 392K,
Change value of the PR114 from 82.5K to 160K
Add PC94 as originally 1000pF
0.2
0.2
C
C
6
50
PWR
10/27
Kenny
Adjusted the transient
7
8
9
50
PWR
10/27
setting
Kenny
47
PWR
10/31
Kenny
When AC souce plug in, the suson turn on
about 120ms immediately.
47
PWR
11/02
Kenny
Remove PR156 and change PR157 location
from PR30_1 to PR30_2.
Change value of the PR27 from10K to 0,
Change value of the PR30 from 10K to 0.
Add PR156 and PR157
0.2
0.2
B
B
10
51
11
51
12
13
A
14
15
PWR
PWR
47
PWR
51
PWR
51
PWR
PWR
51
11/02
11/07
11/07
11/29
11/29
12/12
Kenny
Kenny
Kenny
Vcore noise issue and ME's high limit
Follow TPS51120 reference schematic of
A06 version
Follow COE reference schematic of
A09 version. PC135 may not be needed
Kenny
Follow COE reference schematic of
A09 version. PC138 may be needed
Kenny
0.2
Add Table1 for ADP_OCP circuit.
Modify value of PR147 from 59K to 56.2K
Follow MAX8731 reference schematic of
A07 version
Kenny
Remove PC74 and add PC
Change value of the PC79 from 1210 type to 1206,
Change value of the PC80 from 1210 type to 1206
0.2
Change value of the PR27 from 0 to 10K,
Change value of the PR30 from 0 to 10K.
0.2
Change PC135 to "NO STUFF"
0.3
Add PC138
0.3
Deeply discharged battery problem
Add PR158 and PD19
A
0.3
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Changed-List History 2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
56
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
1
50
Title
Date
PWR
12/15
Request
Owner
12/15
Kenny
Modify battery connecter the same pine
length for P+ and GND
Solve Inaccuracte CP point for 65W
adapter-in current
PWR
3
51
PWR
12/20
Kenny
4
47
PWR
12/20
Kenny
PWR
12/20
Kenny
Rev.
Add PL17 and POP 4@ for Dual core
Resolve a Choke for Dual
46
50
Solution Description
Kenny
2
5
Issue Description
Core CPU
Change P/N form DC040001R0L to DC04000380L
0.3
Add PC139 and PC140 for "NO STUFF"
TDC requirement
D
0.3
0.3
Add PR159
0.3
Change PL13 size from 1810 to 1206.
We plan to add MOSFET for dual core CPU
and have layout space limitation. So change
PL13 size from 1810 to 1206.
0.3
C
C
6
7
8
48
PWR
47
PWR
50
PWR
12/21
12/21
Kenny
Kenny
Delay the 1.5VRUN to meet Intel spec
for the 3VRUN vs 1.5VRUN specification.
Add PD20 and PC141
0.3
Change to 0 ohms for PR159
GG Issue item 19
0.3
12/21
Kenny
12/21
Kenny
EMI test is ok, and have layout limitation
issue for Dual core after adding
low side MOS
Del PR151 and PC83
0.3
Follow MO7_DDRII_SC480_TPS51116_A04 circuit Change PR78 to 27.4K, PR77 to 17.4K.
9
49
PWR
0.3
B
B
10
11
12
47
PWR
12/22
48
PWR
12/22
Kenny
Kenny
Change to 470K ohms for PR159
TDC requirement
0.3
Follow M07_1_05V1_5V_SC483_TPS51483_A07
circuit
"NO STUFF" for PC141
0.3
Modify single and dual core note
49
PWR
12/22
Kenny
Kenny
13
50
PWR
12/23
14
50
PWR
12/26
Kenny
0.3
TDC requirement
Change PC90 from 680p to 390pF
0.3
Modify the Footprint for PQ16
0.3
A
A
15
47
PWR
12/27
Kenny
Change from SGA00000N8L to SGA00001A8L for 2 pcs. (PC25)
Change from SGA00000N8L to SGA1933131L for 2 pcs. ( PC23)
Kemet CAP quantity issue
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
0.3
DELL CONFIDENTIAL/PROPRIETARY
4
3
2
Changed-List History 2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
57
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
1
48
PWR
2/11
2
51
PWR
2/11
3
50
PWR
2/20
4
50
5
PWR
PWR
48
Request
Owner
Issue Description
Solution Description
Rev.
D
Kenny
Footprint error for PD20
Modify footprint fron SOD323 to SOT323
0.4
Kenny
Location error for MOSFET
STUFF for PQ27, NO-STUFF for PQ16
0.4
The OCP setting is 20 A for Dual Core CPU
Adding NO-stuff for 215K on PR104
0.4
Kenny
2/21
Kenny
2/22
Kenny
The load line is "-2.1m" for Dual Core CPU. Adding NO-stuff for 5.76K on PR114
0.4
CYNTEC is not on DELL's AVL
Change the vender from DELTA to CYNTEC on PL9 and PL10
0.4
C
C
6
49
PWR
7
47
PWR
8
51
9
47
2/22
Kenny
2/22
Kenny
PWR
2/23
Kenny
PWR
2/24
Kenny
Change the vender from DELTA to CYNTEC on PL12
CYNTEC is not on DELL's AVL
0.4
Follow COE schetmatic for A06 version
Modify net name from +3.3V_ALW to +3.3V_RTC_LDO for PU7_PIN5
Follow COE schetmatic for A11 version
Modify PQ18 and PQ19 from SI4825 to SI4835
No 2nd source for PC25
Change from SGA00001A8L to SGA1933131L for 2 pcs. (PC25)
0.4
0.4
0.4
B
B
10
11
12
47
45
50
+3.3V_RTC_LDO voltage drop issue
Add PU10, PC143, PC142, PR160, PR162 and PR161
0.4
Kenny
+3.3V_RTC_LDO voltage drop issue
Move PU10, PC143 and PC142 from page47 to page45
0.4
Mike
Error description for Dual Core load line
Dual Core Load Line change to 2.1mohm
PWR
3/6
Kenny
PWR
3/8
PWR
3/17
0.4
13
A
47
PWR
4/25
Kenny
14
48
PWR
4/25
Kenny
15
49
PWR
4/25
Kenny
+3.3V_RTC_LDO voltage drop issue
change PR40 from 470K to 4.7K,
- change PR159 from 470K to 2.2M,
- change PC32 from 0.1U to 0.01uF,
- add UN-STYFF Schottky diode PD21 in parallel to PR159
0.5
Delta ckoke has dimension issue
Change the vender from CYNTEC
to DELTA on PL9 and PL10
0.5
Delta ckoke has dimension issue
Change the vender from CYNTEC
to DELTA on PL9 and PL10
5
4
3
2
0.5
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
Changed-List History 2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
58
of
59
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
1
50
PWR
4/25
2
50
PWR
4/28
Request
Owner
Issue Description
Solution Description
Rev.
D
Kenny
Kenny
CPU noise issue
0.5
For Dual CPU: Modify PR101 from 10K to 20K
PC88 from 820P to 470P
PC90 from 390P to 470P
CPU noise issue
No STUFF PC80 for DUAL CORE CPU
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Changed-List History 2
Size
Document Number
Date:
Friday, May 12, 2006
Rev
1.0
LA-3071P
Sheet
1
59
of
59
www.s-manuals.com
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