Compal LA 6032P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-6032P NDU01, NDU11 - Schematics. Free.
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Page Count: 46
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A
B
B
C
C
D
D
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E
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2 2
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
Cover Sheet
Custom
145Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
NDU01/NDU11 LA-6032P REV 1.0 Schematics Document
2010-03-22 Rev. 1.0
Mobile AMD ASB2/RS880M/SB820M
Compal confidential
Thin & Light
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-6032P
1.0
Block Diagram
Custom
245Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
1.5V 2.5GHz(250MB/s)
page 33
page 20
page 37,38,39.40
41,42,43,44
Power On/Off CKT.
page 20,21,22,23,24
page 34
RTC CKT.
page 5,6,7,8
DC/DC Interface CKT.
Power Circuit DC/DC
PCIe 4x
ADM1032ARMZ
page 9,10
Thermal Sensor
Fan Control
1.5V DDRIII 800MHZ
SB820M
Model Name : NDU01(11.3)-S/NDU11(13.6)-M
page 7
BANK 0, 1, 2, 3
page 11,12,13,14,15
PCIe Port 2
File Name : LA-6032P
Dual Channel
page 5
PCIeMini Card
WLAN (Slot 1)
page 26
Clock Generator
RS880M
Memory BUS(DDRIII)
AMD ASB2 CPU
200pin DDRIII-SO-DIMM X2
BGA-812 Package
page 16
Compal Confidential
SLG8SP626
A-Link Express II
4X PCI-E
Hyper Transport Link 2.6GHz
16X16
Right USB&Audio/B
LS-6031P
page 29
ATI
ATI
page 17
RJ45
page 27
RTL8105E
LAN 10/100M
PCIe port 3
page 30
5IN1
5IN1
PCIe port 1
page 30
FUJIN OZ600FJ1
MIC CONN
page 18
Int.
page 32
GSENSOR
page 28
Int.KBD
page 32
ALC259Q
page 31
SPI ROM
page 32
HDA Codec
ENE KB926 D3
page 32
Debug Port
LPC BUS
3.3V 33 MHz
HP CONN
HD Audio
3.3V 24.576MHz/48Mhz
SPK CONNMIC CONN
USB
5V 480MHz
page 25
SATA HDD0
5V 1.5GHz(150MB/s)
SATA port 0
LCD Conn.
CRT
page 17
page 18
HDMI Conn.
page 19
USB Port 8
USB Port 10 for 3G card
page 26
PCIeMini Card
WWAN / 3G (Slot2)
R5F211B4D34SP
G-Sensor Controller
page 32
EC
SMBUS
USB port 9
page 18
Int. Camera
USB port 6
page 29
BT conn
USB port 0,1
page 29
USB/B Right
5V 1.5GHz(150MB/s)
SATA port 3
page 25
eSATA
USB port 2
5V 480MHz
page 34
SPI ROM
RJ45&VGA/B
LS-6032P
page 17
HD/B
LS-6033P
page 25
LED/B
LS-6034P
page 33
page 33
Touch Pad BTN/B
LS-6035P(13.3)
page 33
PWR BTN
LS-6036P
page 29 page 29 page 29
page 33
Touch Pad BTN/B
LS-6037P(11.6)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-5381P
1.0
Power Map
Custom
345Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
B+
TPS51125RGER
AO-3413
+LCD_VDD
DESIGN CURRENT 1.0A
ENVDD
AO-3413
BT_PWR#
P-CHANNEL
+3VALW
DESIGN CURRENT 1A
+5VALW
DESIGN CURRENT 4.5A
RT8209BGQW
+BT_VCC
+1.1VALW
DESIGN CURRENT 0.3A
POK
N-CHANNEL
N-CHANNEL
SI4800BDY
SUSP
+5VS
DESIGN CURRENT 2A
DESIGN CURRENT 180mA
+3VL
+5VL
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A
SI4800BDY
+3VS
DESIGN CURRENT 4A
SUSP
N-CHANNEL
IRF8113PBF
VGATE#
+1.1VS
DESIGN CURRENT 6.5A
P-CHANNEL
+2.5VS
DESIGN CURRENT 300mA
G9191
+3VS_HDP
DESIGN CURRENT 300mA
+5VS
LDO
APL5508
LDO
ISL6265
DESIGN CURRENT 1A
+1.5VS
SUSP
IRF8113PBF
N-CHANNEL
+VDDNB
DESIGN CURRENT 15A
+CPU_CORE0
SUSP
DESIGN CURRENT 2A
DESIGN CURRENT 0.5A
+0.75VS
DESIGN CURRENT 7A
+1.5V
RT8209BGQW
SYSON
G2992F1U
LDO
VR_ON
N-CHANNEL
IRF8113PBF
VLDT_EN#
+NB_CORE
DESIGN CURRENT 7.6A
VR_ON#
DESIGN CURRENT 1.5A
+0.9V
G2992F1U
LDO
MP2121DQ
SUSP#
+1.8VS
DESIGN CURRENT 1.5A
AO-3413
WOL_EN#
P-CHANNEL
+3V_LAN
DESIGN CURRENT 500mA
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
Notes List
Custom
445Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Voltage Rails
O MEANS ON X MEANS OFF
O
O
X
S3
X
X
S1
O
OO
OO
X
XX
power
plane
O
O
O
O
O
X
S5 S4/ Battery only
XX X
State
S5 S4/AC & Battery
don't exist
S5 S4/AC
S0
O
O
Symbol Note :
: means Digital Ground : means Analog Ground
1010 0100 bA4 H
SB SM Bus1 Address
1010 0000 b
D2 H
A0 H
Clock Generator
HEX
DDR SO-DIMM 1
Address
DDR SO-DIMM 0
1101 0010 b
Device
+3VS
+3VALW
+5VS
+2.5VS
B+
+1.5VS
+1.5V+5VALW +0.9VS
+1.8VS
+NB_CORE
+3VL
+1.1VS
+1.1VALW
+VDDNB
HEX HEX
16 H
EC SM Bus1 Address
Device Address Address
EC SM Bus2 Address
Device
0001 011X bSmart Battery
98 H
1001 100X bCPU_ADM1032-1
+CPU_CORE_0
+5VL
+RTCVCC
G-Sensor
Power
+3VS
+3VS
+3VS
SB SM Bus2 Address
HEX Address
WLAN/WIMAX
DevicePower
+3VALW
PowerPower
+3VL +3VS
+3VS
+0.75VS
CPU
SENSOR
EC_SMB_CK2
BATT
KB926
SOURCE
SMBUS Control Table
CLK
GEN
SODIMM
THERMAL
EC_SMB_CK1
EC_SMB_DA2
WLAN
KB926
EC_SMB_DA1
LCD
DDC
ROM
I / II
V
V
V
RS880M
I2C_DATA
I2C_CLK
HDMI
DDC
ROM
RS880M
DDC_DATA0
DDC_CLK0
V
V
SCL0
SDA0 SB820
VV
SB820
SDA1
SCL1
G-sensor
V
For 11.6 and 13.3 DAZ
K125 mean 1.7G CPU
GSENSOR@ : means just reserve for G sensor part
1ST@ : means just reserve 1st G sensor IC
K625R3@ : means just for 1.5G CPU
@ : means just reserve , no build
K125R3@ : means just for 1.7G CPU
M@ : means just reserve for 13.3 control
S@ : means just reserve for 11.6 control
1STGSENSOR@ : means just reserve 1st G sensor IC
2NDGSENSOR@ : means just reserve 2nd G sensor IC
2ND@ : means just reserve 2nd G sensor IC
NOSIDE@ : means just reserve NOSIDE
SIDE@ : means just reserve SIDE port
RS880MR1@ : means just for RS880MR1
K325 mean 1.3G CPU
K325R3@ : means just for 1.3G CPU
RS880M SB820M
RS880MR3@ : means just for RS880MR3
SB820MR3@ : means just for SB820MR3
SB820MR1@ : means just for SB820MR1
K125 mean 1.7G CPU K325 mean 1.3G CPUK625 mean 1.7G CPU
K325R1@ : means just for 1.3G CPU
K625R1@ : means just for 1.5G CPU
K125R1@ : means just for 1.7G CPU
U1
K125 CPU
K625R3@
U7
SB820M
SB820MR3@
U1
K125 CPU
K125R3@
U1
K325 CPU
K325R3@
U5
RS880M
RS880MR3@
U1
K325 CPU
K325R1@
U1
K125 CPU
K125R1@
ZZZ
PCB-MB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADON15
H_CTLON0
H_CTLOP0
H_CTLON1
H_CTLOP1
H_CLKON1
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CLKOP0
H_CLKOP1
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CLKON0
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
+FAN1
+FAN1
H_CADIN9
H_CADIP7
H_CADIN6
H_CADIN4
H_CADIN2
H_CADIP8
H_CADIN3
H_CADIN5
H_CADIN0
H_CADIP0
H_CADIP3
H_CADIP10
H_CADIN7
H_CADIP5
H_CADIP1
H_CADIP15
H_CADIN12
H_CADIP4
H_CADIP13
H_CADIN15
H_CADIN14
H_CADIP6
H_CADIP2
H_CADIN1
H_CADIN11
H_CADIP14
H_CADIP12
H_CADIN13
H_CADIN10
H_CADIP11
H_CADIP9
H_CADIN8
H_CLKIN0
H_CLKIN1
H_CLKIP0
H_CLKIP1
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
H_CADON[0..15] 11H_CADIN[0..15]11
H_CADOP[0..15] 11
H_CTLOP1 11
H_CLKOP1 11
H_CADIP[0..15]11
H_CLKOP0 11
H_CLKON0 11
H_CLKON1 11
H_CTLON1 11
H_CTLOP0 11
H_CTLON0 11
FAN_SPEED1 31
EN_DFAN131
H_CLKIN011
H_CLKIN111
H_CLKIP111
H_CLKIP011
H_CTLIN111
H_CTLIP111
H_CTLIN011
H_CTLIP011
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
AMD CPU S1G2 HT I/F
Custom
545Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
1A
FAN Control Circuit
U1A
HT LINK
TMK625DBV23GM_FCBGA812
K625@
L0_CADIN_H15
W7
L0_CADIN_L15
W6
L0_CADIN_H14
U6
L0_CADIN_L14
U5
L0_CADIN_H13
R7
L0_CADIN_L13
R6
L0_CADIN_H12
P6
L0_CADIN_L12
P5
L0_CADIN_H11
L6
L0_CADIN_L11
L5
L0_CADIN_H10
J6
L0_CADIN_L10
J5
L0_CADIN_H9
H4
L0_CADIN_L9
H3
L0_CADIN_H8
G6
L0_CADIN_L8
G5
L0_CADIN_H7
T3
L0_CADIN_L7
T4
L0_CADIN_H6
T2
L0_CADIN_L6
T1
L0_CADIN_H5
P3
L0_CADIN_L5
P4
L0_CADIN_H4
P2
L0_CADIN_L4
P1
L0_CADIN_H3
M2
L0_CADIN_L3
M1
L0_CADIN_H2
K3
L0_CADIN_L2
K4
L0_CADIN_H1
K2
L0_CADIN_L1
K1
L0_CADIN_H0
H2
L0_CADIN_L0
H1
L0_CADOUT_H15 AB6
L0_CADOUT_L15 AB5
L0_CADOUT_H14 AB9
L0_CADOUT_L14 AB8
L0_CADOUT_H13 AC7
L0_CADOUT_L13 AC6
L0_CADOUT_H12 AE6
L0_CADOUT_L12 AE5
L0_CADOUT_H11 AE9
L0_CADOUT_L11 AE8
L0_CADOUT_H10 AH3
L0_CADOUT_L10 AH4
L0_CADOUT_H9 AK3
L0_CADOUT_L9 AK4
L0_CADOUT_H8 AH1
L0_CADOUT_L8 AH2
L0_CADOUT_H7 Y1
L0_CADOUT_L7 Y2
L0_CADOUT_H6 Y4
L0_CADOUT_L6 Y3
L0_CADOUT_H5 AB1
L0_CADOUT_L5 AB2
L0_CADOUT_H4 AB4
L0_CADOUT_L4 AB3
L0_CADOUT_H3 AD4
L0_CADOUT_L3 AD3
L0_CADOUT_H2 AF1
L0_CADOUT_L2 AF2
L0_CADOUT_H1 AF4
L0_CADOUT_L1 AF3
L0_CADOUT_H0 AK1
L0_CADOUT_L0 AK2
L0_CLKIN_H1
M8
L0_CLKIN_L1
M7
L0_CLKIN_H0
M3
L0_CLKIN_L0
M4
L0_CTLIN_H0
V2
L0_CTLIN_L0
V1 L0_CTLOUT_H0 V4
L0_CTLOUT_L0 V3
L0_CLKOUT_H0 AD1
L0_CLKOUT_L0 AD2
L0_CLKOUT_H1 AF6
L0_CLKOUT_L1 AF5
L0_CTLIN_H1
Y6
L0_CTLIN_L1
Y5 L0_CTLOUT_H1 Y8
L0_CTLOUT_L1 Y9
R1
10K_0402_5%
12
JFAN1
ACES_88231-03041
@
1
1
2
2
3
3
GND
4
GND
5
D1
1SS355_SOD323-2
@
12
C4
0.01U_0402_25V7K
@
1
2
D2
1SS355_SOD323-2
@
12
C1
10U_0805_10V6K 1
2
C3
10U_0805_10V6K
1
2
C2
1000P_0402_50V7K
@
1
2
U2
APL5607KI-TRG_SO8
EN
1
VIN
2
VOUT
3
VSET
4
GND 8
GND 7
GND 6
GND 5
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_MA15
DDR_B_MA9
DDR_B_MA7
DDR_B_MA1
DDR_B_MA2
DDR_B_MA11
DDR_B_MA5
DDR_B_MA13
DDR_B_MA12
DDR_B_MA6
DDR_B_MA0
DDR_B_MA10
DDR_B_MA8
DDR_B_MA3
DDR_B_MA4
DDR_B_MA14
DDR_B_BS#1
DDR_B_BS#2
DDR_B_BS#0
DDR_A_D2
DDR_A_D18
DDR_A_D57
DDR_A_CAS#
DDR_A_DQS#2
DDR_A_MA0
DDR_A_D33
DDR_A_D46
DDR_A_RAS#
DDR_A_DQS6
DDR_A_MA15
DDR_A_D32
DDR_A_D38
DDR_A_D47
DDR_A_D51
DDR_A_DQS7
DDR_A_MA4
DDR_A_MA5
DDR_A_D21
DDR_A_D29
DDR_A_DM4
DDR_A_DQS0
DDR_A_MA6
DDR_A_D0
DDR_A_D31
DDR_A_D35
DDR_A_D45
DDR_A_D60
DDR_A_ODT1
DDR_A_MA9
DDR_A_MA13
DDR_A_D11
DDR_A_D15
DDR_A_D54
DDR_A_DM1DDR_A_ODT0
DDR_A_DQS#3
DDR_A_MA3
DDR_A_D43
DDR_A_D48
DDR_A_D1
DDR_A_D4
DDR_A_D8
DDR_A_D37
DDR_A_D40
DDR_A_D59
DDR_A_DM6
DDR_A_D5
DDR_A_D17
DDR_A_D23
DDR_A_D41
DDR_A_D63
DDR_A_DM5
DDR_A_MA11
DDR_A_D7
DDR_A_D36
DDR_A_WE#
DDR_A_MA7
DDR_A_D34
DDR_A_DM7
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_DQS1
DDR_A_D24
DDR_A_D53
DDR_A_D56
DDR_A_D61
DDR_A_D62
DDR_A_DQS#0
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA8
DDR_A_MA10
DDR_A_MA12
DDR_A_D10
DDR_A_D28
DDR_A_D39
DDR_A_D44
DDR_A_D52
DDR_A_DM2
DDR_A_D16
DDR_A_D12
DDR_A_D14
DDR_A_D27
DDR_A_D42
DDR_A_DM0
DDR_A_BS#1
DDR_A_D6
DDR_A_D13
DDR_A_D19
DDR_A_D20
DDR_A_D26
DDR_A_D30
DDR_A_D49
DDR_A_D55
DDR_A_D58
DDR_A_DM3
DDR_A_CLK#0
DDR_A_MA14
DDR_A_D3
DDR_A_D9
DDR_A_D22
DDR_A_D25
DDR_A_D50
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_ODT0
DDR_B_ODT1
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_B_DM1
DDR_B_DM3
DDR_B_DM5
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM6
DDR_B_DM0
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_A_CLK0
DDR_A_DQS4
DDR_A_DQS5
DDR_A_MA2
DDR_A_DQS2
DDR_A_DQS#1
DDR_A_DQS3
DDR_A_BS#2
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_MA1
DDR_A_BS#0
MB_EVENT_L
MA_EVENT_L
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_A_D[63..0] 9
DDR_A_DM[7..0] 9
DDR_A_MA[15..0]9
DDR_A_BS#09
DDR_A_BS#29
DDR_A_BS#19
DDR_A_DQS39
DDR_A_DQS29
DDR_A_DQS19
DDR_A_DQS09
DDR_A_DQS#39
DDR_A_DQS#29
DDR_A_DQS#19
DDR_A_DQS#09
DDR_A_DQS49
DDR_A_DQS#49
DDR_A_DQS59
DDR_A_DQS#59
DDR_A_DQS69
DDR_A_DQS#69
DDR_A_DQS79
DDR_A_DQS#79
DDR_A_CLK09
DDR_A_CLK#09
DDR_A_CLK19
DDR_A_CLK#19
DDR_A_ODT09
DDR_A_ODT19
DDR_A_RAS#9
DDR_A_CAS#9
DDR_A_WE#9
DDR_B_D[63..0] 10
DDR_B_MA[15..0]10
DDR_B_BS#110
DDR_B_BS#210
DDR_B_BS#010
DDR_B_DQS710
DDR_B_DQS#710
DDR_B_DQS610
DDR_B_DQS510
DDR_B_DQS410
DDR_B_DQS310
DDR_B_DQS210
DDR_B_DQS110
DDR_B_DQS010
DDR_B_DQS#610
DDR_B_DQS#510
DDR_B_DQS#410
DDR_B_DQS#310
DDR_B_DQS#210
DDR_B_DQS#110
DDR_B_DQS#010
DDR_B_CLK010
DDR_B_CLK#010
DDR_B_CLK110
DDR_B_CLK#110
DDR_B_RAS#10
DDR_B_CAS#10
DDR_B_WE#10
DDR_B_ODT010
DDR_B_ODT110
DDR_CKE1_DIMMB10
DDR_CKE0_DIMMB10
DDR_B_DM[7..0] 10
DDR_CS0_DIMMA#9
DDR_CS1_DIMMA#9
MEM_MB_RST#10 MEM_MA_RST#9
DDR_CS0_DIMMB#10
DDR_CS1_DIMMB#10
DDR_CKE0_DIMMA9
DDR_CKE1_DIMMA9
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
AMD CPU S1G2 DDRII I/F
Custom
645Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
U1B
DDR III: CHANNEL A
TMK625DBV23GM_FCBGA812
K625@
MA_DATA63 AG11
MA_DATA62 AH11
MA_DATA61 AJ12
MA_DATA60 AJ14
MA_DATA59 AF11
MA_DATA58 AF12
MA_DATA57 AG12
MA_DATA56 AH12
MA_DATA55 AK14
MA_DATA54 AF15
MA_DATA53 AH19
MA_DATA52 AK20
MA_DATA51 AF14
MA_DATA50 AG14
MA_DATA49 AF17
MA_DATA48 AG19
MA_DATA47 AG20
MA_DATA46 AJ20
MA_DATA45 AF22
MA_DATA44 AK24
MA_DATA43 AF19
MA_DATA42 AF20
MA_DATA41 AJ23
MA_DATA40 AG23
MA_DATA39 AF23
MA_DATA38 AF25
MA_DATA37 AH27
MA_DATA36 AK30
MA_DATA35 AJ25
MA_DATA34 AG25
MA_DATA33 AJ26
MA_DATA32 AJ28
MA_DATA31 D28
MA_DATA30 G28
MA_DATA29 D26
MA_DATA28 E26
MA_DATA27 F30
MA_DATA26 E29
MA_DATA25 F27
MA_DATA24 H26
MA_DATA23 H25
MA_DATA22 D24
MA_DATA21 H22
MA_DATA20 E22
MA_DATA19 F26
MA_DATA18 G26
MA_DATA17 D22
MA_DATA16 G23
MA_DATA15 G22
MA_DATA14 G20
MA_DATA13 G15
MA_DATA12 F15
MA_DATA11 D20
MA_DATA10 F22
MA_DATA9 D16
MA_DATA8 E17
MA_DATA7 H15
MA_DATA6 H14
MA_DATA5 G12
MA_DATA4 H12
MA_DATA3 E15
MA_DATA2 E14
MA_DATA1 E11
MA_DATA0 F11
MA_ADD15
P30
MA_ADD14
M29
MA_ADD13
AG28
MA_ADD12
P28
MA_ADD11
T30
MA_ADD10
AC28
MA_ADD9
P27
MA_ADD8
R26
MA_ADD7
R27
MA_ADD6
U28
MA_ADD5
V30
MA_ADD4
U27
MA_ADD3
Y30
MA_ADD2
AB29
MA_ADD1
W29
MA_ADD0
AC26
MA_BANK2
R29
MA_BANK1
AC29
MA_BANK0
AE28
MA_DM8 H30
MA_CHECK7
K30
MA_CHECK6
J29
MA_CHECK5
G29
MA_CHECK4
F29
MA_CHECK3
L28
MA_CHECK2
L29
MA_CHECK1
H29
MA_CHECK0
H27
MA_DQS_H8
J27
MA_DQS_L8
J26
MA_DQS_H7
AJ11
MA_DQS_L7
AK12
MA_DQS_H6
AG15
MA_DQS_L6
AH15
MA_DQS_H5
AH22
MA_DQS_L5
AG22
MA_DQS_H4
AG26
MA_DQS_L4
AH26
MA_DQS_H3
E28
MA_DQS_L3
F28
MA_DQS_H2
E25
MA_DQS_L2
F25
MA_DQS_H1
G17
MA_DQS_L1
H17
MA_DQS_H0
E12
MA_DQS_L0
F12
MA_CLK_H7
AK18
MA_CLK_L7
AJ17
MA_CLK_H6
AH17
MA_CLK_L6
AG17
MA_CLK_H5
Y28
MA_CLK_L5
Y27
MA_CLK_H4
AB27
MA_CLK_L4
AB26
MA_CLK_H3
W27
MA_CLK_L3
W26
MA_CLK_H2
P26
MA_CLK_L2
M26
MA_CLK_H1
D18
MA_CLK_L1
F19
MA_CLK_H0
E20
MA_CLK_L0
E19
MA_CKE1
M30
MA_CKE0
M28
MA1_ODT0
AF27 MA1_ODT1
AJ29
MA0_ODT0
AG29 MA0_ODT1
AJ30
MA1_CS_L1
AH29
MA1_CS_L0
AE29
MA0_CS_L1
AH30
MA0_CS_L0
AF29
MA_RAS_L
AC27
MA_CAS_L
AF30
MA_WE_L
AE27
MA_RESET_L
L27
FREE|MA_EVENT_L
M32
MA_DM7 AL12
MA_DM6 AK16
MA_DM5 AK22
MA_DM4 AJ27
MA_DM3 E27
MA_DM2 E23
MA_DM1 H19
MA_DM0 G14
U1C
DDR III: CHANNEL B
TMK625DBV23GM_FCBGA812
K625@
MB_ADD15
P33
MB_ADD14
P31
MB_ADD13
AJ33
MB_ADD12
T32
MB_ADD11
T31
MB_ADD10
AD32
MB_ADD9
T33
MB_ADD8
V32
MB_ADD7
U33
MB_ADD6
V33
MB_ADD5
V31
MB_ADD4
W33
MB_ADD3
Y31
MB_ADD2
Y33
MB_ADD1
Y32
MB_ADD0
AC33
MB_BANK2
R33
MB_BANK1
AD33
MB_BANK0
AE33
MB_CHECK7
K33
MB_CHECK6
K31
MB_CHECK5
G32
MB_CHECK4
F32
MB_CHECK3
L33
MB_CHECK2
K32
MB_CHECK1
H31
MB_CHECK0
G33
MB_DQS_H8
J33
MB_DQS_L8
H32
MB_DQS_H7
AM14
MB_DQS_L7
AN14
MB_DQS_H6
AL20
MB_DQS_L6
AM20
MB_DQS_H5
AN26
MB_DQS_L5
AM26
MB_DQS_H4
AN30
MB_DQS_L4
AM30
MB_DQS_H3
D33
MB_DQS_L3
D32
MB_DQS_H2
B28
MB_DQS_L2
A28
MB_DQS_H1
A21
MB_DQS_L1
B20
MB_DQS_H0
B16
MB_DQS_L0
A15
MB_CLK_H7
AN22
MB_CLK_L7
AM22
MB_CLK_H6
AN21
MB_CLK_L6
AM21
MB_CLK_H5
AA32
MB_CLK_L5
AA33
MB_CLK_H4
AB33
MB_CLK_L4
AB32
MB_CLK_H3
AB31
MB_CLK_L3
AB30
MB_CLK_H2
AD31
MB_CLK_L2
AD30
MB_CLK_H1
C22
MB_CLK_L1
B22
MB_CLK_H0
A22
MB_CLK_L0
A23
MB_CKE1
N33
MB_CKE0
P32
MB1_ODT0
AH31 MB1_ODT1
AK31
MB0_ODT0
AH33 MB0_ODT1
AK32
MB1_CS_L1
AK33
MB1_CS_L0
AF33
MB0_CS_L1
AJ32
MB0_CS_L0
AF31
MB_RAS_L
AF32
MB_CAS_L
AH32
MB_WE_L
AG33
MB_RESET_L
L32
FREE|MB_EVENT_L
M33
MB_DATA63 AN13
MB_DATA62 AL14
MB_DATA61 AL16
MB_DATA60 AN17
MB_DATA59 AN12
MB_DATA58 AM12
MB_DATA57 AM16
MB_DATA56 AN16
MB_DATA55 AL18
MB_DATA54 AN19
MB_DATA53 AM24
MB_DATA52 AN24
MB_DATA51 AM18
MB_DATA50 AN18
MB_DATA49 AL22
MB_DATA48 AN23
MB_DATA47 AM25
MB_DATA46 AL26
MB_DATA45 AN28
MB_DATA44 AL28
MB_DATA43 AL24
MB_DATA42 AN25
MB_DATA41 AN27
MB_DATA40 AM28
MB_DATA39 AM29
MB_DATA38 AL30
MB_DATA37 AL32
MB_DATA36 AL33
MB_DATA35 AK28
MB_DATA34 AN29
MB_DATA33 AM31
MB_DATA32 AM32
MB_DATA31 E33
MB_DATA30 D31
MB_DATA29 B31
MB_DATA28 A31
MB_DATA27 F33
MB_DATA26 F31
MB_DATA25 C32
MB_DATA24 B32
MB_DATA23 C30
MB_DATA22 A29
MB_DATA21 B26
MB_DATA20 A26
MB_DATA19 B30
MB_DATA18 A30
MB_DATA17 A27
MB_DATA16 C26
MB_DATA15 A24
MB_DATA14 B24
MB_DATA13 C18
MB_DATA12 A18
MB_DATA11 A25
MB_DATA10 C24
MB_DATA9 C20
MB_DATA8 A19
MB_DATA7 C16
MB_DATA6 A16
MB_DATA5 B14
MB_DATA4 A13
MB_DATA3 B18
MB_DATA2 A17
MB_DATA1 C14
MB_DATA0 A14
MB_DM8 H33
MB_DM7 AN15
MB_DM6 AN20
MB_DM5 AK26
MB_DM4 AN31
MB_DM3 C33
MB_DM2 C28
MB_DM1 A20
MB_DM0 D14
R793 1K_0402_5%
1 2
R792 1K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_CLKIN_SC_P
LDT_RST#
H_PWRGD
LDT_STOP#
CPU_CLKIN_SC_N
CPU_SVC
CPU_SVD
THERMDA_CPU
THERMDC_CPU
CPU_VDDNB_RUN_FB_H
CPU_THERMTRIP#_R
LDT_STOP#
H_PWRGD
LDT_RST#
CPU_SID
CPU_SIC
CPU_TMS
CPU_DBRDY
CPU_TRST#
CPU_TDI
CPU_TCK
CPU_DBREQ#
CPU_TDO
THERMDA_CPU
THERMDC_CPU
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_SVC
CPU_SVD
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST6_DIECRACKMON
CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST2
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST14_BP0
CPU_TEST15_BP1
CPU_TEST7_ANALOG_T
CPU_TEST9_ANALOGIN
CPU_TEST3
CPU_TEST27_SINGLECHAIN
CPU_TEST20_SCANCLK2
CPU_TEST21_SCANEN
CPU_TEST23_TSTUPD
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST8_DIG_T
CPU_TEST10_ANALOGOUT
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST26_BURNIN_L
CPU_TEST29_H_FBCLKOUT_P
CPU_PROCHOT#_1.8
CPU_TEST23_TSTUPD
CPU_DBRDY
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST24_SCANCLK1
CPU_TEST15_BP1
CPU_TEST20_SCANCLK2
CPU_TEST22_SCANSHIFTEN
CPU_TEST14_BP0
CPU_TEST21_SCANEN
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN_L
CPU_HTREF1
CPU_HTREF0
M_ZN
M_ZP
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_VDD0_RUN_FB_L
CPU_VDD0_RUN_FB_H
CPU_VDDNB_RUN_FB_H
CPU_VLDT_SENSE
CPU_VLDT_SENSE
CPU_VDDIO_SENSE
CPU_VDDIO_SENSE
CPU_VDDR_SENSECPU_VDDR_SENSE
CPU_DBREQ#
CPU_PRESENT_L
M_VREF
M_VREF
CPU_TDI_R
CPU_TMS_R
CPU_TRST#_R
CPU_TCK_R
LDT_RST#
CPU_TDO
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_DBREQ#
CPU_TDO_R
CPU_DBRDY
LDT_STOP#12,20
LDT_RST#20
CLK_CPU_BCLK#20
EC_SMB_DA2 31,32
EC_SMB_CK2 31,32
H_PROCHOT# 20
H_THERMTRIP# 21
H_PWRGD20,42
CPU_SVD 42
CPU_SVC 42
CLK_CPU_BCLK20
CPU_VDD0_RUN_FB_L42
CPU_VDD0_RUN_FB_H42
CPU_VDDNB_RUN_FB_H42
+2.5VDDA
+2.5VS
+1.5V
+1.5VS
+1.5VS
+1.5VS
+3VS
+1.5V
+1.5V
+VDDNB
+1.5V
+1.5V
+1.5V
+1.1VS
+1.1VALW
+1.5V
+0.9V
+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
AMD CPU S1G2 CTRL
Custom
745Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Close to CPU
Thermal Sensor
Close to CPU within
1"
L
R8 Close to CPU within 0.6"
C9 C10 Close to CPU within 1.2"
L
+2.5VDDA@250mA
R14 R15 Close to CPU within 1.5"
L
E
B
C
Q1
MMBT3904_NL_SOT23-3
2
3 1
U1D
MISC
TMK625DBV23GM_FCBGA812 K625@
VDDA_1
A8
VDDA_2
B8
RESET_L
F9
PWROK
D10
LDTSTOP_L
E9
RSVD3 AM6
CLKIN_H
A6
CLKIN_L
A7
DBRDY H9
TMS
AN8 TCK
AK8 TRST_L
AL8 TDI
AM8 TDO AN7
DBREQ_L
G9
SVD B2
VDDNB_SENSE
D1
VDDIO_SENSE
D3
THERMTRIP_L AK6
RSVD_SA0
AM2
SIC
AN4
SID
AN5
VLDT_SENSE
E2
VDD_SENSE
E1
PROCHOT_L AN6
GATE0
AK5
DRAIN0
AJ7
DIECRACKMON
AH7 ANALOG_T
C6
DIG_T B5
ANALOGOUT D7
BURNIN_L AM4
SINGLECHAIN AJ8
SCANCLK2 AM7
SCANSHIFTEN AK9
TSTUPD AG8
SCANCLK1 AK7
BP0
E8 BP1
D9 BP2
C8 BP3
F8
ANALOGIN
G8
SCANEN AH9
PLLTEST1
B6 PLLTEST0
A5
FBCLKOUT_H B10
FBCLKOUT_L A10
RSVD|CORE_TYPE M31
ALERT_L
AN3
VSS_SENSE
D2
THERMDC AL6
THERMDA AM5
M_ZN_H
AM9
VDDR_SENSE
C2
M_VREF
A11
BYPASSCLK_H
A9
BYPASSCLK_L
B9
HTREF1 V10
HTREF0 V9
PLLCHRZ_L H11
PLLCHRZ_H G11
SVC C1
M_ZN_L
AN9
CPU_PRESENT_L AJ9
M_TEST AG9
R13 1K_0402_5%
1 2
R14 44.2_0402_1%
1 2
R851 0_0402_5%
1 2
R9 10_0402_5%
1 2
R850 0_0402_5%
1 2
C10
3900P_0402_50V7K
1 2
R4 300_0402_5%
1 2
R27 1K_0402_5%
1 2
C13
0.1U_0402_16V7K
1
2
R39
510_0402_5%
@
1 2
C16
0.1U_0402_16V4Z
1
2
R43220_0402_5%
@
12
R20 1K_0402_5%
1 2
L1
FBM_L11_201209_300L_0805
1 2
T10 PAD @
R31 1K_0402_5%
1 2
R852 0_0402_5%
1 2
R15 44.2_0402_1%
1 2
R8
169_0402_1%
12
R21 1K_0402_5%
1 2
R355 10_0402_5%
@
R5
0_0402_5%
@
1 2
R36
510_0402_5%
1 2
C7
3300P_0402_50V7K
1
2
R802
1K_0402_1%
1 2
R45300_0402_5%
1 2
R23 300_0402_5% @
1 2
R28 300_0402_5% @
1 2
T1 PAD @
+
C5
100U_D2_10VM
@
1
2
R853 0_0402_5%
1 2
R38
510_0402_5%
1 2
T11 PAD @
R801 1K_0402_5%
1 2
C11
0.01U_0402_25V7K
@
1
2
T12 PAD
@
R32 1K_0402_5%
1 2
R3 1K_0402_5%
1 2
R10 1K_0402_5%
1 2
R18
80.6_0402_1%
1 2
C9 3900P_0402_50V7K
1 2
R854 0_0402_5%
1 2
R803
1K_0402_1%
1 2
U4
ADM1032ARM-1 ZREEL_MSOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R19 300_0402_5%
@
1 2
R7 1K_0402_5%
1 2
T14 PAD
@
R12 1K_0402_5%
1 2
R35
510_0402_5%
@
1 2
R33
300_0402_5%
1 2
R2 10K_0402_5%
1 2
C8
0.22U_0603_16V4Z
1
2
C17
2200P_0402_50V7K
1 2
C655
1000P_0402_25V8J
1
2
T16 PAD @
R42220_0402_5%
@
12
R24 1K_0402_5%
1 2
R17
300_0402_5%
1 2
R22
0_0402_5%
1 2
R29 300_0402_5% @
1 2
C12
0.1U_0402_16V7K
@
1 2
T15 PAD
@
C654
0.01U_0402_25V7K
1
2
R41220_0402_5%
@
12
R34 300_0402_5% @
1 2
R11
300_0402_5%
1 2
SAMTEC_ASP-68200-07
JP1
CONN@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
C14
0.01U_0402_25V7K
@
1
2
T18 PAD @
R26 1K_0402_5%
1 2
T22PAD@
C64.7U_0805_10V4Z
1
2
D4 CH751H-40PT_SOD323-2
21
R16
39.2_0402_1~D
1 2
T17 PAD
@R30 1K_0402_5%
1 2
R356 10_0402_5%
@
T23PAD@R25 1K_0402_5%
1 2
R44300_0402_5%
@
12
R357 10_0402_5%
@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+CPU_CORE_0 +CPU_CORE_0
+1.5V
+VDDNB
+0.9V
+CPU_CORE_0
+CPU_CORE_0
+1.5V
+0.9V
+0.9V
+1.1VS
+1.1VS
+1.5V
+VDDNB
+CPU_CORE_0
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
AMD CPU S1G2 PWR & GND
Custom
845Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
VLDT_A&VLDT_B(+1.1VS) decoupling.
VDDR(+0.9V) decoupling.
VDD(+CPU_CORE_0) decoupling.
+CPU_CORE_0@15000mA
+VDDNB@2000mA
+0.9V@1250mA
+1.1VS@1500mA
3000mA
CPU BOT site
L
VDDIO(+1.5V) decoupling.
VDD(+CPU_CORE_0) decoupling. VDDNB(+VDDNB) decoupling.
C27
4.7U_0805_10V4Z
1
2
+
C496
330U_SX_2VY~D
1
2
C24
180P_0402_50V8J
1
2
C42
180P_0402_50V8J
1
2
C63
0.22U_0603_16V4Z
1
2
C58
4.7U_0805_10V4Z
1
2
C50
22U_0805_6.3V6M
1
2
C36
1000P_0402_50V7K
1
2
C625
0.22U_0603_16V4Z
1
2
C43
180P_0402_50V8J
1
2
+
C497
330U_SX_2VY~D
@
1
2
C56
180P_0402_50V8J
1
2
C28
4.7U_0805_10V4Z
1
2
C51
22U_0805_6.3V6M
1
2
C37
1000P_0402_50V7K
1
2
U1F
POWER2
TMK625DBV23GM_FCBGA812
K625@
VDDR_3 C12
VDDR_4 D12
VDDR_5 AK10
VDDR_8 AN10
VDDR_6 AL10
VDDR_7 AM10
VDDNB_1 A3
VDDNB_2 A4
VDDNB_3 B3
VDDNB_4 B4
VDDNB_5 C3
VDDNB_6 C4
VLDT_A_1 F1
VLDT_A_2 F2
VLDT_A_3 F3
VLDT_A_4 F4
VLDT_B_1 AL1
VLDT_B_2 AL2
VLDT_B_3 AL3
VLDT_B_4 AL4
VDDIO_1
M27
VDDIO_2
Y26
VDDIO_3
U26
VDDIO_4
N32
VDDIO_5
U32
VDDIO_6
N30
VDDIO_7
P29
VDDIO_8
R28
VDDIO_9
R30
VDDIO_10
R32
VDDIO_11
U29
VDDIO_12
U30
VDDIO_13
W28
VDDIO_14
W30
VDDIO_19
AE32
VDDIO_20
AC30
VDDIO_15
W32
VDDIO_16
Y29
VDDIO_22
AE26
VDDIO_23
AE30
VDDIO_24
AF28
VDDIO_25
AG30
VDDIO_17
AA30
VDDIO_18
AB28
VDDIO_21
AC32
VDDIO_26
AG32
VDDIO_27
AD25
VDDIO_28
AA25
VDDIO_29
AC25
VDDIO_30
V25
VDDIO_31
P25
VDDIO_32
N25
VDDIO_33
M25
VDDIO_34
K25
VDDIO_38
AB25 VDDIO_37
Y25 VDDIO_36
T25 VDDIO_35
L25
VDDR_1 A12
VDDR_2 B12
PROGEN_L B11
FREE_1 G7
FREE_2 B7
FREE_3 AH8
FREE_4 AJ6
FREE_5 B25
FREE_6 AM3
FREE_8 P9
FREE_9 P8
FREE_7 AN11
C651
0.22U_0603_16V4Z
1
2
C629
0.01U_0402_25V7K
1
2
C33
22U_0805_6.3V6M
1
2
C29
0.22U_0603_16V4Z
1
2
C65
180P_0402_50V8J
1
2
C626
0.22U_0603_16V4Z
1
2
C52
22U_0805_6.3V6M
1
2
C53
22U_0805_6.3V6M
1
2
U1E
POWER1
TMK625DBV23GM_FCBGA812
K625@
VDD_3
D6
VDD_4
E5
VDD_5
E6
VDD_6
E7
VDD_9
F7
VDD_10
H7
VDD_11
H8
VDD_12
J8
VDD_13
E4
VDD_21
J9
VDD_14
J10
VDD_22
K10
VDD_30
L11
VDD_31
L13
VDD_15
J12
VDD_16
J14
VDD_17
J18
VDD_27
K21
VDD_28
K23
VDD_23
K12
VDD_24
K14
VDD_25
K18
VDD_18
J20
VDD_26
K20
VDD_32
L7
VDD_33
L9
VDD_76 AE18
VDD_70 AE14
VDD_85 AE12
VDD_84 AD9
VDD_39
N24
VDD_34
M10
VDD_35
M12
VDD_37
M5
VDD_41
N9
VDD_38
N11
VDD_42
P15
VDD_50 R5
VDD_43
P18
VDD_45 P24
VDD_63 W5
VDD_44 P20
VDD_47 R14
VDD_48 R16
VDD_58 V24
VDD_82 AD21
VDD_81 AD18
VDD_80 AD14
VDD_79 AD12
VDD_78 AD11
VDD_75 AC24
VDD_74 AC12
VDD_73 AC10
VDD_72 AB13
VDD_71 AB11
VDD_69 AA24
VDD_68 AA12
VDD_67 AA10
VDD_59 AE23
VDD_83 AE21
VDD_64 Y14
VDD_7
F5
VDD_8
F6
VDD_65 Y16
VDD_66 Y19
VDD_62 W20
VDD_20
J23 VDD_19
J21
VDD_61 W18
VDD_60 W15
VDD_57 V19
VDD_56 V16
VDD_55 V14
VDD_54 T20
VDD_53 T18
VDD_77 AC5
VDD_52 T15
VDD_51 T10
VDD_49 R19
VDD_29
N4
VDD_36
R4
VDD_40
W4 VDD_46 AC4
VDD_1
D4
VDD_2
D5
C38
1000P_0402_50V7K
1
2
C652
0.22U_0603_16V4Z
1
2
C623
4.7U_0805_10V4Z
1
2
C653
180P_0402_50V8J
1
2
C30
0.22U_0603_16V4Z
1
2
+
C494
330U_SX_2VY~D
1
2
+
C526
330U_2.5V_M
1
2
C59
22U_0805_6.3V6M
1
2
C34
22U_0805_6.3V6M
1
2
C627
0.22U_0603_16V4Z
1
2
C630
0.1U_0402_16V7K
1
2
U1G
GND1
TMK625DBV23GM_FCBGA812
K625@
VSS_1
B1
VSS_2
B13
VSS_3
B15
VSS_4
B17
VSS_5
B19
VSS_6
B21
VSS_7
B23
VSS_8
B27
VSS_9
B29
VSS_10
B33
VSS_11
C10
VSS_12
C31
VSS_13
D11
VSS_14
D13
VSS_15
D15
VSS_16
D17
VSS_17
D19
VSS_18
D21
VSS_19
D23
VSS_20
D25
VSS_21
D27
VSS_22 L26
VSS_23 L30
VSS_24 L4
VSS_25 L8
VSS_26 M11
VSS_27
M21
VSS_28
N2
VSS_29
N22
VSS_30
N23
VSS_31
P10
VSS_32
P14
VSS_33
P16
VSS_34
P19
VSS_35
P7
VSS_36
R1
VSS_37
R15
VSS_38
R18
VSS_39
R2
VSS_40
R20
VSS_41 V15
VSS_42 V18
VSS_43 V20
VSS_44 W1
VSS_45 W19
VSS_46
D29
VSS_47
D30
VSS_48
D8
VSS_49
E30
VSS_50
E32
VSS_51
F14
VSS_52
F17
VSS_53
R8
VSS_54
T14
VSS_55
T16
VSS_56
F20
VSS_57
T19
VSS_58
T24
VSS_59
T9
VSS_60
U1
VSS_61
F23
VSS_62
N1
VSS_63
G1
VSS_64
G19
VSS_65
G2
VSS_66
G25
VSS_67
G27
VSS_68 L24
VSS_69 L23
VSS_70 L22
VSS_71 L21
VSS_72 L2
VSS_73 L12
VSS_74 L10
VSS_75 L1
VSS_76 K9
VSS_77 M6
VSS_78 K24
VSS_79 K22
VSS_80 K16
VSS_81 M22
VSS_82 K13
VSS_83 M24
VSS_84 K11
VSS_85 M23
VSS_86 J7
VSS_87 W16
VSS_88 J4
VSS_89 W14
VSS_90 J32
VSS_91 J30
VSS_92 M13
VSS_93 J28
VSS_94 U8
VSS_95 J25
VSS_96 U4
VSS_97 J24
VSS_98 U7
VSS_99 U2
VSS_100 J2
VSS_101 J16
VSS_102 J13
VSS_103 J11
VSS_104 J1
VSS_105 H6
VSS_106 H5
VSS_107 H28
VSS_108 H23
VSS_109 H20
VSS_110 J22
VSS_111 M9
VSS_112 G4
VSS_113 G30
VSS_114 N12
VSS_115
N10
C39
1000P_0402_50V7K
1
2
C20
22U_0805_6.3V6M
1
2
C31
0.22U_0603_16V4Z
1
2
C624
4.7U_0805_10V4Z
1
2
C649
4.7U_0805_10V4Z
1
2
C60
22U_0805_6.3V6M
1
2
C631
0.1U_0402_16V7K
1
2
C25
4.7U_0805_10V4Z
1
2
C628
0.22U_0603_16V4Z
1
2
C35
22U_0805_6.3V6M
1
2
C55
0.01U_0402_25V7K
1
2
C18
4.7U_0805_10V4Z
1
2
C46
0.22U_0603_16V4Z
1
2
C44
22U_0805_6.3V6M
1
2
C32
0.22U_0603_16V4Z
1
2
C21
0.22U_0603_16V4Z
1
2
C61
22U_0805_6.3V6M
1
2
C650
4.7U_0805_10V4Z
1
2
C19
4.7U_0805_10V4Z
1
2
C26
4.7U_0805_10V4Z
1
2
C47
0.22U_0603_16V4Z
1
2
C45
22U_0805_6.3V6M
1
2
C48
180P_0402_50V8J
1
2
C40
180P_0402_50V8J
1
2
C62
22U_0805_6.3V6M
1
2
C22
0.22U_0603_16V4Z
1
2
+
C495
330U_SX_2VY~D
1
2
C64
0.01U_0402_25V7K
1
2
U1H
GND2
TMK625DBV23GM_FCBGA812
K625@
VSS_116
W2
VSS_117
W8
VSS_118
Y10
VSS_119
Y15
VSS_120
Y18
VSS_121
Y20
VSS_122
Y24
VSS_123
Y7
VSS_124
AA1
VSS_125
AA11
VSS_126 AA2
VSS_127 AA22
VSS_128 AA23
VSS_129 AA4
VSS_130 AA9
VSS_131 AB10
VSS_132 AB12
VSS_133 AB21
VSS_134 AB22
VSS_135 AB23
VSS_136 AB24
VSS_137 AB7
VSS_138 AC1
VSS_139 AC11
VSS_140 AC13
VSS_141 AC2
VSS_142 AC21
VSS_143 AC22
VSS_144
AC23
VSS_145
AC8 VSS_146
AC9 VSS_147
AD10 VSS_148
AD13 VSS_149
AD16 VSS_150
AD20
VSS_151
AD22 VSS_152
AD23 VSS_153
AD24 VSS_154
AE1 VSS_155
AE10 VSS_156
AE11
VSS_157
AE13 VSS_158
AE16 VSS_159
AE2 VSS_160
AE20 VSS_161
AE22 VSS_162
AE24 VSS_163
AE25 VSS_164
AE4
VSS_165
AE7 VSS_166
AF26 VSS_167
AF7
VSS_168
AF8
VSS_169
AF9
VSS_170
AG1
VSS_171
AG2
VSS_172
AG27
VSS_173
AG4
VSS_174
AG5
VSS_175
AG6
VSS_176
AG7
VSS_177
AH14
VSS_178
AH20
VSS_179
AH23
VSS_180
AH25
VSS_181
AH28
VSS_182
AH5
VSS_183
AJ1
VSS_184
AJ15
VSS_185
AJ19
VSS_186
AJ2
VSS_187
AJ22
VSS_188
AJ4
VSS_189
AK11
VSS_190
AK13
VSS_191 AK15
VSS_192 AK17
VSS_193 AK19
VSS_194 AK21
VSS_195 AK23
VSS_196 AK25
VSS_197 AK27
VSS_198 AK29
VSS_199 AJ5
VSS_200 AH6
VSS_201 AL31
VSS_202 AM1
VSS_203 AM13
VSS_205 AM15
VSS_206 AM17
VSS_207
AM19
VSS_208 AM23
VSS_209 AM27
VSS_210 AM33
VSS_211 AN2
VSS_212 AN32
VSS_213
A32
VSS_214
A2 VSS_215 AM11
C23
180P_0402_50V8J
1
2
C41
180P_0402_50V8J
1
2
C49
180P_0402_50V8J
1
2
C54
0.22U_0603_16V4Z
1
2
C57
4.7U_0805_10V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_D36
DDR_A_D63
DDR_A_D26
DDR_A_DQS6
DDR_A_D2
DDR_A_D5
DDR_A_D22
DDR_A_D25
DDR_A_D35
DDR_A_MA12
DDR_A_D14
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_CKE1_DIMMA
DDR_A_D27
DDR_A_MA15
DDR_A_D31
DDR_CKE0_DIMMA
DDR_A_D12
DDR_A_D59
DDR_A_MA3
DDR_A_D6
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_BS#1
DDR_A_WE#
DDR_A_MA7
DDR_A_DQS0
DDR_A_MA0
DDR_A_DM2
DDR_A_DQS7
DDR_A_DM1
DDR_A_D57
DDR_A_D46
DDR_A_D0
DDR_A_D28
DDR_A_DM0
DDR_A_DQS#5
DDR_A_D51
DDR_A_D19
DDR_A_DM4
DDR_A_D4
DDR_A_D30
DDR_A_DQS2
DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D10
DDR_A_MA6
DDR_A_MA10
DDR_A_D3
MEM_MA_RST#
DDR_A_DQS#7
DDR_A_DQS#6
DDR_A_D1
DDR_A_D40
DDR_A_MA9
DDR_A_D16
DDR_A_D29
DDR_A_DQS#4
DDR_A_D52
DDR_A_DM3
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS#2
DDR_A_D45
DDR_A_D9
DDR_A_DM7
DDR_A_MA1
DDR_A_D7
DDR_A_D13
DDR_A_D20
DDR_A_D60
DDR_A_BS#0
DDR_A_CAS# DDR_A_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_DQS#1
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D21
DDR_A_D62
DDR_A_D24
DDR_A_D15
DDR_A_D56
DDR_A_D23
DDR_A_D53
DDR_A_D47
DDR_A_ODT1
DDR_A_D18
DDR_A_D43
DDR_A_D34
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D48
DDR_A_DQS#2
DDR_A_D11
DDR_A_D38
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_D32
DDR_A_DQS#3
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D8
DDR_A_DQS1
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D17
+VREF_DQ
EVENT#_A
+VREF_CA
DDR_A_MA[0..15] 6
DDR_A_D[0..63] 6
DDR_A_DM[0..7] 6
DDR_CKE0_DIMMA6
DDR_CS1_DIMMA#6
DDR_A_BS#1 6
DDR_A_WE#6
DDR_A_RAS# 6
DDR_CS0_DIMMA# 6
MEM_MA_RST# 6
DDR_A_BS#26
DDR_A_BS#06
DDR_A_CAS#6DDR_A_ODT0 6
DDR_A_ODT1 6
DDR_A_CLK#1 6
DDR_A_CLK1 6
DDR_A_CLK06
DDR_A_CLK#06
DDR_CKE1_DIMMA 6
SMB_CK_DAT0 10,21
SMB_CK_CLK0 10,21
DDR_A_DQS3 6
DDR_A_DQS0 6
DDR_A_DQS#3 6
DDR_A_DQS#0 6
DDR_A_DQS5 6
DDR_A_DQS#5 6
DDR_A_DQS7 6
DDR_A_DQS#7 6
DDR_A_DQS#16
DDR_A_DQS16
DDR_A_DQS#26
DDR_A_DQS26
DDR_A_DQS#46
DDR_A_DQS46
DDR_A_DQS#66
DDR_A_DQS66
+1.5V
+0.75VS
+3VS
+1.5V +1.5V
+3VS
+VREF_DQ
+VREF_DQ
+VREF_CA
+1.5V
+0.75VS
+1.5V+VREF_CA
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
DDRII SO-DIMM 1
Custom
945Tuesday, March 23, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
DIMM_A STD H:4mm
<Address: 00>
Place near DIMM1
12/25 Solve layout test point issue
C431
1000P_0402_25V8J
1
2
R281
1K_0402_1%
1 2
C436
0.1U_0402_16V4Z
1
2
C425
4.7U_0805_10V4Z
@
1
2
C701
180P_0402_50V8J
1
2
C427
1000P_0402_25V8J
1
2
R283
1K_0402_1%
1 2
C443
0.1U_0402_16V4Z
1
2
C442
0.1U_0402_16V4Z
1
2
C437
0.1U_0402_16V4Z
1
2
C434
0.1U_0402_16V4Z
1
2
C439
0.1U_0402_16V4Z
1
2
R285 10K_0402_5%
1 2
C441
0.1U_0402_16V4Z
1
2
C429
0.01U_0402_25V7K
1
2
C702
180P_0402_50V8J
1
2
C428
4.7U_0805_10V4Z
@
1
2
R282
1K_0402_1%
1 2
C440
0.1U_0402_16V4Z
1
2
C438
0.1U_0402_16V4Z
1
2
R284
1K_0402_1%
1 2
C430
1000P_0402_25V8J
1
2
R286
10K_0402_5%
12
C700
180P_0402_50V8J
1
2
C444
4.7U_0603_6.3V6K
1
2
C435
0.1U_0402_16V4Z
1
2
C703
180P_0402_50V8J
1
2
C446
0.1U_0402_16V4Z
1
2
C445
2.2U_0805_10V6K
1
2
C433
0.1U_0402_16V4Z
1
2
C432
0.1U_0402_16V4Z
1
2
JDIMM1
FOX_AS0A626-U4RN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C426
0.01U_0402_25V7K
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
+VREF_DQ
DDR_B_DQS6
DDR_B_D26
DDR_B_D63
DDR_B_D36
DDR_B_D35
DDR_B_D25
DDR_B_D22
DDR_B_D5
DDR_B_D2
DDR_B_DQS#0
DDR_B_D14
DDR_B_MA12
DDR_CKE1_DIMMB
DDR_B_D42
DDR_B_DM6
DDR_B_DQS4
DDR_B_MA15
DDR_B_D27
DDR_B_D12
DDR_CKE0_DIMMB
DDR_B_D31
DDR_B_MA3
DDR_B_D59
DDR_B_BS#1
DDR_B_D39
DDR_CS1_DIMMB#
DDR_B_D6
DDR_B_DQS0
DDR_B_MA7
DDR_B_WE#
DDR_B_MA0
DDR_B_DM2
DDR_B_D0
DDR_B_D46
DDR_B_D57
DDR_B_DM1
DDR_B_DQS7
DDR_B_DM0
DDR_B_D28
DDR_B_DM4
DDR_B_D19
DDR_B_D51
DDR_B_DQS#5
DDR_B_DQS2
DDR_B_D30
DDR_B_D4
DDR_B_D33
DDR_B_RAS#
DDR_B_D44
DDR_B_DQS3
DDR_B_DM5
DDR_B_D58
DDR_B_MA8
DDR_CS0_DIMMB#
DDR_B_MA10
DDR_B_MA6
DDR_B_D10
DDR_B_DQS#6
DDR_B_DQS#7
MEM_MB_RST#
DDR_B_D3
DDR_B_D16
DDR_B_MA9
DDR_B_D1
DDR_B_DQS#4
DDR_B_D29
DDR_B_D49
DDR_B_D54
DDR_B_DQS5
DDR_B_DM3
DDR_B_D9
DDR_B_D45
DDR_B_BS#2
DDR_B_D20
DDR_B_D13
DDR_B_D7
DDR_B_MA1
DDR_B_DM7
DDR_B_BS#0
DDR_B_D60
DDR_B_D37
DDR_B_ODT0DDR_B_CAS#
DDR_B_D55
DDR_B_MA14
DDR_B_DQS#1
DDR_B_MA5
DDR_B_D21
DDR_B_MA4
DDR_B_D62
DDR_B_D15
DDR_B_D24
DDR_B_D47
DDR_B_D53
DDR_B_D23
DDR_B_D56
DDR_B_D43
DDR_B_D18
DDR_B_ODT1
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_D34
DDR_B_DQS#2
DDR_B_D48
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_D11
DDR_B_D50
DDR_B_MA11
DDR_B_MA13
DDR_B_DQS#3
DDR_B_D32
DDR_B_MA2
DDR_B_D61
DDR_B_DQS1
DDR_B_D8
DDR_B_D17
DDR_B_D41
EVENT#_B
DDR_B_D40
DDR_B_D38
DDR_B_D52
+VREF_CA
DDR_B_MA[0..15] 6
DDR_B_D[0..63] 6
DDR_B_DM[0..7] 6
DDR_CS1_DIMMB#6
DDR_CKE0_DIMMB6
DDR_CS0_DIMMB# 6
DDR_B_RAS# 6
DDR_B_WE#6
DDR_B_BS#1 6
DDR_B_CAS#6
DDR_B_BS#06
DDR_B_BS#26
MEM_MB_RST# 6
DDR_B_CLK1 6
DDR_B_CLK#1 6
DDR_B_ODT1 6
DDR_B_ODT0 6
DDR_CKE1_DIMMB 6
DDR_B_CLK#06
DDR_B_CLK06
DDR_B_DQS26
DDR_B_DQS#26
DDR_B_DQS46
DDR_B_DQS#46
DDR_B_DQS66
DDR_B_DQS#66
DDR_B_DQS#0 6
DDR_B_DQS0 6
DDR_B_DQS#3 6
DDR_B_DQS3 6
DDR_B_DQS5 6
DDR_B_DQS#5 6
DDR_B_DQS7 6
DDR_B_DQS#7 6
DDR_B_DQS#16
DDR_B_DQS16
SMB_CK_DAT0 9,21
SMB_CK_CLK0 9,21
+VREF_DQ
+0.75VS
+1.5V+1.5V
+3VS
+VREF_DQ
+VREF_CA
+1.5V
+0.75VS
+VREF_CA
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
DDRII SO-DIMM 2
Custom
10 45Tuesday, March 23, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
DIMM_B STD H:4mm
<Address: 01>
Place near DIMM2
C468 Co-layout with C467
12/25 Solve layout test point issue
C463
0.1U_0402_16V4Z
1
2
C462
0.1U_0402_16V4Z
1
2
C460
0.1U_0402_16V4Z
1
2
C458
0.1U_0402_16V4Z
1
2
C456
0.1U_0402_16V4Z
1
2
C451
0.1U_0402_16V4Z
1
2
C457
0.1U_0402_16V4Z
1
2
C449
1000P_0402_25V8J
1
2
C453
1000P_0402_25V8J
1
2
C454
0.1U_0402_16V4Z
1
2
C466
4.7U_0603_6.3V6K
1
2
R287 10K_0402_5%
1 2
C464
0.1U_0402_16V4Z
1
2
C448
0.1U_0402_16V4Z
1
2
C447
4.7U_0805_10V4Z
1
2
C459
0.1U_0402_16V4Z
1
2
JDIMM2
FOX_AS0A626-U4SN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C455
0.1U_0402_16V4Z
1
2
C450
4.7U_0805_10V4Z
1
2
R288
10K_0402_5%
12
C465
0.1U_0402_16V4Z
1
2
+
C468
330U_2.5V_M
1
2
C452
1000P_0402_25V8J
1
2
C461
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADOP5
H_CTLIN1
H_CLKIP1
H_CADIN4
H_CADOP9
H_CADOP12
H_CTLIP0
H_CADIP7
H_CTLON1
H_CADON6
H_CADON12
H_CADIP9
H_CADIN11
H_CADIP3
H_CADIP13
H_CADOP4
H_CADOP10
H_CADON15
H_CTLIP1
H_CLKIN0
H_CTLON0
H_CADON0
H_CADON9
H_CADON13
H_CTLIN0
H_CADIP0
H_CADIN7
H_CADOP2
H_CADOP6
H_CADIP11
H_CADOP0
H_CADIN2
H_CADIN3
H_CADIN13
H_CADOP1
H_CADON4
H_CADON10
H_CADOP15
H_CLKIN1
H_CLKOP1
H_CADON1
H_CADOP13
H_CADIN5
H_CADIP6
H_CTLOP1
H_CADON5
H_CADON8
H_CADIP15
H_CTLOP0
H_CADON3
H_CADON7
H_CADIP1
H_CADIP5
H_CADIN9
H_CADIP10
H_CADIN12
H_CADON11
H_CADOP14
H_CADIN1
H_CADIN6
H_CLKOP0
H_CADON14
H_CADIP4
H_CADIN14
H_CADIP14
H_CADON2
H_CADOP8
H_CLKIP0
H_CADIN8
H_CADIN15
H_CLKON0
H_CLKON1
H_CADOP3
H_CADOP7
H_CADIN0
H_CADIP2
H_CADIP8
H_CADIN10
H_CADIP12
H_CADOP11
PCIE_ITX_PRX_P1
HDMI_TXD0-
PCIE_ITX_PRX_N1
SB_TX1N_C
PCIE_ITX_PRX_P2
SB_TX1P_C
SB_TX0P_C
HDMI_CLK0-
HDMI_TXD0+
SB_TX0N_C
HDMI_TXD1+
PCIE_ITX_PRX_N3
SB_TX3N_C
HDMI_TXD2-
HDMI_TXD2+
PCIE_ITX_PRX_N2
SB_TX2P_C
SB_TX2N_C
HDMI_CLK0+
PCIE_ITX_PRX_P3
SB_TX3P_C
HDMI_TXD1-
H_CADON[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
H_CLKOP05
H_CTLON05
H_CTLIN1 5
H_CLKIP1 5
H_CLKON05
H_CTLOP05
H_CTLON15
H_CLKIN0 5
H_CTLIP0 5
H_CLKON15
H_CTLOP15
H_CTLIN0 5
H_CLKOP15
H_CLKIN1 5
H_CTLIP1 5
H_CLKIP0 5
HDMI_TXD1+ 19
SB_RX3N20
SB_TX0N 20
PCIE_PTX_C_IRX_P327
PCIE_ITX_C_PRX_N1 30
SB_TX2N 20
PCIE_ITX_C_PRX_N2 26
SB_RX1N20
HDMI_CLK0+ 19
SB_TX1N 20
HDMI_TXD2+ 19
HDMI_TXD2- 19
SB_RX3P20
PCIE_PTX_C_IRX_N130
HDMI_TXD0- 19
SB_TX2P 20
PCIE_PTX_C_IRX_N226
SB_RX1P20
SB_TX0P 20
SB_TX1P 20
PCIE_PTX_C_IRX_P130
HDMI_TXD0+ 19
SB_RX2N20
PCIE_PTX_C_IRX_P226
SB_TX3P 20
PCIE_ITX_C_PRX_P2 26
HDMI_CLK0- 19
SB_RX0N20
PCIE_ITX_C_PRX_N3 27
HDMI_TXD1- 19
SB_RX2P20
PCIE_PTX_C_IRX_N327
PCIE_ITX_C_PRX_P1 30
SB_TX3N 20
PCIE_ITX_C_PRX_P3 27
SB_RX0P20
H_CADOP[0..15]5
H_CADON[0..15]5
H_CADIP[0..15] 5
H_CADIN[0..15] 5
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
11 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
RS880M HT/PCIE
L L
Place within 1" layout 1:2Place within 1" layout 1:2
AUX1 and HPD1
GFX_TX0,TX1,TX2 and TX3
HDMI
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
RS880M Display Port Support (muxed on GFX)
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
R51 within U5 1"
R54 within U5 1"
L
< TX Impedance Calibration. Connect to GND >
< RX Impedance Calibration. Connect to VDDPCIE >
< To LAN >
< To WLAN >
< To SB820 : x4 PCEI A-link>< From SB820 : x4 PCIE A-link >
< To Card crader >
< To WWAN >
< To LAN >
< To WLAN >
< To Card crader >
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
C123 0.1U_0402_16V7K
1 2
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U5A
RS880M_FCBGA528 RS880MR1@
HT_RXCAD15P
U19
HT_RXCAD15N
U18
HT_RXCAD14P
U20
HT_RXCAD14N
U21
HT_RXCAD13P
V21
HT_RXCAD13N
V20
HT_RXCAD12P
W21
HT_RXCAD12N
W20
HT_RXCAD11P
Y22
HT_RXCAD11N
Y23
HT_RXCAD10P
AA24
HT_RXCAD10N
AA25
HT_RXCAD9P
AB25
HT_RXCAD9N
AB24
HT_RXCAD8P
AC24
HT_RXCAD8N
AC25
HT_RXCAD7P
N24
HT_RXCAD7N
N25
HT_RXCAD6P
P25
HT_RXCAD6N
P24
HT_RXCAD5P
P22
HT_RXCAD5N
P23
HT_RXCAD4P
T25
HT_RXCAD4N
T24
HT_RXCAD3P
U24
HT_RXCAD3N
U25
HT_RXCAD2P
V25
HT_RXCAD2N
V24
HT_RXCAD1P
V22
HT_RXCAD1N
V23
HT_RXCAD0P
Y25
HT_RXCAD0N
Y24
HT_RXCLK1P
AB23
HT_RXCLK1N
AA22
HT_RXCLK0P
T22
HT_RXCLK0N
T23
HT_RXCTL0P
M22
HT_RXCTL0N
M23
HT_RXCTL1P
R21
HT_RXCTL1N
R20
HT_RXCALP
C23
HT_RXCALN
A24
HT_TXCAD15P P18
HT_TXCAD15N M18
HT_TXCAD14P M21
HT_TXCAD14N P21
HT_TXCAD13P M19
HT_TXCAD13N L18
HT_TXCAD12P L19
HT_TXCAD12N J19
HT_TXCAD11P J18
HT_TXCAD11N K17
HT_TXCAD10P J20
HT_TXCAD10N J21
HT_TXCAD9P G20
HT_TXCAD9N H21
HT_TXCAD8P F21
HT_TXCAD8N G21
HT_TXCAD7P K23
HT_TXCAD7N K22
HT_TXCAD6P K24
HT_TXCAD6N K25
HT_TXCAD5P J25
HT_TXCAD5N J24
HT_TXCAD4P H23
HT_TXCAD4N H22
HT_TXCAD3P F23
HT_TXCAD3N F22
HT_TXCAD2P F24
HT_TXCAD2N F25
HT_TXCAD1P E24
HT_TXCAD1N E25
HT_TXCAD0P D24
HT_TXCAD0N D25
HT_TXCLK1P L21
HT_TXCLK1N L20
HT_TXCLK0P H24
HT_TXCLK0N H25
HT_TXCTL0P M24
HT_TXCTL0N M25
HT_TXCTL1P P19
HT_TXCTL1N R18
HT_TXCALP B24
HT_TXCALN B25
C136 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7K
1 2
R53 301_0402_1%
1 2
C126 0.1U_0402_16V7K
1 2
C124 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7K
1 2
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U5B
RS880M_FCBGA528
RS880MR1@
SB_TX3P AD5
SB_TX3N AE5
GPP_TX2P AA2
GPP_TX2N AA1
GPP_TX3P Y1
GPP_TX3N Y2
SB_RX3P
W5
SB_RX3N
Y5
GPP_RX2P
AD1
GPP_RX2N
AD2
GPP_RX3P
V5
GPP_RX3N
W6
SB_TX0P AD7
SB_TX0N AE7
SB_TX1P AE6
SB_TX1N AD6
SB_RX0P
AA8
SB_RX0N
Y8
SB_RX1P
AA7
SB_RX1N
Y7
PCE_CALRP(PCE_BCALRP) AC8
PCE_CALRN(PCE_BCALRN) AB8
SB_TX2N AC6
SB_RX2P
AA5
SB_RX2N
AA6 SB_TX2P AB6
GPP_RX0P
AE3
GPP_RX0N
AD4
GPP_RX1P
AE2
GPP_RX1N
AD3
GPP_TX0P AC1
GPP_TX0N AC2
GPP_TX1P AB4
GPP_TX1N AB3
GFX_RX0P
D4
GFX_RX0N
C4
GFX_RX1P
A3
GFX_RX1N
B3
GFX_RX2P
C2
GFX_RX2N
C1
GFX_RX3P
E5
GFX_RX3N
F5
GFX_RX4P
G5
GFX_RX4N
G6
GFX_RX5P
H5
GFX_RX5N
H6
GFX_RX6P
J6
GFX_RX6N
J5
GFX_RX7P
J7
GFX_RX7N
J8
GFX_RX8P
L5
GFX_RX8N
L6
GFX_RX9P
M8
GFX_RX9N
L8
GFX_RX10P
P7
GFX_RX10N
M7
GFX_RX11P
P5
GFX_RX11N
M5
GFX_RX12P
R8
GFX_RX12N
P8
GFX_RX13P
R6
GFX_RX13N
R5
GFX_RX14P
P4
GFX_RX14N
P3
GFX_RX15P
T4
GFX_RX15N
T3
GFX_TX0P A5
GFX_TX0N B5
GFX_TX1P A4
GFX_TX1N B4
GFX_TX2P C3
GFX_TX2N B2
GFX_TX3P D1
GFX_TX3N D2
GFX_TX4P E2
GFX_TX4N E1
GFX_TX5P F4
GFX_TX5N F3
GFX_TX6P F1
GFX_TX6N F2
GFX_TX7P H4
GFX_TX7N H3
GFX_TX8P H1
GFX_TX8N H2
GFX_TX9P J2
GFX_TX9N J1
GFX_TX10P K4
GFX_TX10N K3
GFX_TX11P K1
GFX_TX11N K2
GFX_TX12P M4
GFX_TX12N M3
GFX_TX13P M1
GFX_TX13N M2
GFX_TX14P N2
GFX_TX14N N1
GFX_TX15P P1
GFX_TX15N P2
GPP_TX4P Y4
GPP_TX4N Y3
GPP_TX5P V1
GPP_TX5N V2
GPP_RX4P
U5
GPP_RX4N
U6
GPP_RX5P
U8
GPP_RX5N
U7
C134 0.1U_0402_16V7K
1 2
R54 2K_0402_1%
1 2
C131 0.1U_0402_16V7K
1 2
C122 0.1U_0402_16V7K
1 2
C125 0.1U_0402_16V7K
1 2
R52 301_0402_1%
1 2
C135 0.1U_0402_16V7K
1 2
C127 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7K
1 2
R51 1.27K_0402_1%
1 2
C130 0.1U_0402_16V7K
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CRT_R_R
CRT_G_R
CRT_B_R
+AVDD2
CLK_NBHT#
HPD
CRT_R_R
+AVDDQ
LCD_EDID_DATA
NBGFX_CLK
LCD_EDID_CLK
NBGFX_CLK#
CPU_LDT_REQ#
AUX_CAL
+VDDLT18
+AVDD1
HDMICLK_UMA
NB_LDTSTOP#
CRT_B_R
+VDDLTP18
UMA_CRT_DATA
CRT_G_R
+AVDD1
CLK_SBLINK_BCLK#
NB_PWRGD
+AVDDQ
+VDDLTP18
HDMIDAT_UMA
+VDDLT18
CLK_SBLINK_BCLK
+AVDD2
UMA_CRT_CLK
SUS_STAT#
CLK_NBHT
NB_RESET#
VARY_ENBKL
NB_LDTSTOP#
NB_PWRGD
CPU_LDT_REQ#
CLK_NB_REFCLK
CLK_NB_REFCLK#
NBGFX_CLK
NBGFX_CLK#
CRT_R_R
CRT_G_R
CRT_B_R
LCD_TXOUT0- 18
CLK_SBLINK_BCLK20
NB_PWRGD21
LCD_TXOUT1+ 18
PLT_RST#15,20,26,27,30,31,32
SUS_STAT# 15,21
LCD_EDID_DATA18
LCD_TXOUT2- 18
CRT_VSYNC15,17
LCD_TXOUT0+ 18
UMA_CRT_DATA17
CLK_NBHT#20
HDMIDAT_UMA19
HDMICLK_UMA19
LCD_EDID_CLK18
LCD_TXOUT2+ 18
CLK_NBHT20
LCD_TXCLK+ 18
UMA_CRT_CLK17
HPD 19
CRT_HSYNC15,17
LCD_TXOUT1- 18
CLK_SBLINK_BCLK#20
CPU_LDT_REQ#20
LCD_TXCLK- 18
UMA_ENBKL 31
UMA_ENVDD 18
GMCH_INVT_PWM 18
LDT_STOP#7,20
CLK_NB_REFCLK20
CLK_NB_REFCLK#20
CRT_G 17
CRT_R 17
CRT_B 17
+1.8VS +VDDA18PCIEPLL
+1.8VS +VDDA18HTPLL
+1.1VS
+NB_PLLVDD
+1.8VS
+NB_HTPVDD+1.8VS
+1.8VS
+3VS
+VDDA18PCIEPLL
+1.8VS
+NB_PLLVDD
+VDDA18HTPLL
+1.8VS
+NB_HTPVDD
+3VS
+1.8VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
RS880M VEDIO/CLK GEN
Custom
12 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
+AVDD1@125mA
Total +1.8VS PLL@100mA
Total +1.1VS_PLL@230mA
+VDDLT18@220mA
Strap pin
If support VB, R780 R777->SMT, R776->@
If no support VB, R776-->SMT, R780 R777->@
< LVDS dual channel : channel 1 >
< Strap option pin or gate side-port memory IO >
< HDMI hot-plug detection >
Strap pin
CPU_LDT_REQ# Pull +1.8VS on page 20
12/07 Internal clock gen
PS:Need to fine tune R783 and R784 on Page17
2/2 Fine tune pin define
2/2 Add L41 L42 L43 C911 C912 C913 for EMI request
Contact with NB signal Contact to CRT conn signal
C913
2.2P_0402_50V8C
1
2
R806
2.2K_0402_5%
12
R58 715_0402_1%
1 2
R778
4.7K_0402_5%
@
12
L41 NBQ100505T-800Y-N_2P
1 2
R781
4.7K_0402_5%
@
12
R780 0_0402_5%
1 2
R64 10K_0402_5%
@12
L10
BLM18PG121SN1D_0603
1 2
L43 NBQ100505T-800Y-N_2P
1 2
RS16
4.7K_0402_5%
12
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U5C
RS880M_FCBGA528
RS880MR1@
VDDA18HTPLL
H17
SYSRESETb
D8
POWERGOOD
A10
LDTSTOPb
C10
ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC) D10
DDC_CLK0/AUX0P(NC)
A8 DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P AE8
THERMALDIODE_N AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2
GFX_REFCLKN
T1
GPP_REFCLKP
U1
GPP_REFCLKN
U2
PLLVDD18(NC)
D14
PLLVSS(NC)
B12
TXOUT_L0P(NC) A22
TXOUT_L0N(NC) B22
TXOUT_L1P(NC) A21
TXOUT_L1N(NC) B21
TXOUT_L2P(NC) B20
TXOUT_L2N(DBG_GPIO0) A20
TXOUT_L3P(NC) A19
TXOUT_U0P(NC) B18
TXOUT_L3N(DBG_GPIO2) B19
TXOUT_U0N(NC) A18
TXOUT_U1P(PCIE_RESET_GPIO3) A17
TXOUT_U1N(PCIE_RESET_GPIO2) B17
TXOUT_U2P(NC) D20
TXOUT_U2N(NC) D21
TXOUT_U3P(PCIE_RESET_GPIO5) D18
TXOUT_U3N(NC) D19
TXCLK_LP(DBG_GPIO1) B16
TXCLK_LN(DBG_GPIO3) A16
TXCLK_UP(PCIE_RESET_GPIO4) D16
TXCLK_UN(PCIE_RESET_GPIO1) D17
VDDLTP18(NC) A13
VSSLTP18(NC) B13
C_Pr(DFT_GPIO5)
E17
Y(DFT_GPIO2)
F17
COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC) D9
I2C_DATA
A9
TESTMODE D13
HT_REFCLKN
C24 HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5) D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11 DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12
AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14
AVSSDI(NC)
G15
AVDDQ(NC)
H15
AVSSQ(NC)
H14
VDDLT18_2(NC) B15
VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
VSSLT1(VSS) C14
VSSLT2(VSS) D15
VDDLT18_1(NC) A15
VSSLT3(VSS) C16
VSSLT4(VSS) C18
VSSLT5(VSS) C20
LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
LVDS_ENA_BL(PWM_GPIO2) G12
VSSLT6(VSS) E20
VDDA18PCIEPLL1
D7
VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4
GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7 DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8
DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS) C22
RSVD
G11
L5
0_0603_5%
C143
0.1U_0402_16V4Z
1
2
C147
2.2U_0603_6.3V6K
1
2
R776 0_0402_5% @
1 2
R822 0_0402_5%
@
1 2
R66 150_0402_1%
@12
R59
0_0402_5%
1 2
L3
BLM18PG121SN1D_0603
1 2
R805
2.2K_0402_5%
12
R65 1.8K_0402_5%
1 2
L8
BLM18PG121SN1D_0603
1 2
RS15
4.7K_0402_5%
12
L2
BLM18PG121SN1D_0603
1 2
L7
BLM18PG121SN1D_0603
1 2
C140
0.1U_0402_16V4Z
1
2
R56 150_0402_1%
1 2
C912
2.2P_0402_50V8C
1
2
R57 150_0402_1%
1 2
R63 300_0402_5%
1 2
L6
BLM18PG121SN1D_0603
1 2
R55 140_0402_1%
1 2
R779
4.7K_0402_5%
@
12
C138
2.2U_0603_6.3V6K
1
2
C146
2.2U_0603_6.3V6K
1
2
R804
1K_0402_5%
12
C139
2.2U_0603_6.3V6K
1
2
C145
2.2U_0603_6.3V6K
1
2
C144
2.2U_0603_6.3V6K
1
2
E
B
C
Q36
MMBT3904_NL_SOT23-3
2
3 1
R777 0_0402_5%
1 2
L9
BLM18PG121SN1D_0603
1 2
C141
4.7U_0805_10V4Z
1
2
L4
BLM18PG121SN1D_0603
1 2
L42 NBQ100505T-800Y-N_2P
1 2
C142
2.2U_0603_6.3V6K
1
2
C148
2.2U_0603_6.3V6K
1
2
C911
2.2P_0402_50V8C
1
2
2
2
1
1
B B
A A
MEM_DQ2
MEM_DQ0
MEM_DQ1
MEM_DQ3
MEM_DQ10
MEM_DQ7
MEM_DQ11
MEM_DQ8
MEM_DQ5
MEM_DQ6
MEM_DQ9
MEM_DQ15
MEM_DQ13
MEM_DQ14
MEM_DQ4
MEM_DQ12
+MEM_VREF1
+NB_IOPLLVDD
+1.8V_IOPLLVDD
MEM_DQS_P0
MEM_DQS_P1
MEM_DQS_N0
MEM_DQS_N1
MEM_DM1
MEM_DM0
MEM_CLKP
MEM_CLKN
MEM_BA0
MEM_BA1
MEM_BA2
+MEM_VREF
+MEM_VREF1
MEM_COMP_P
MEM_COMP_N
MEM_A12
MEM_A2
MEM_A3
MEM_A0
MEM_A10
MEM_A11
MEM_A8
MEM_A9
MEM_A1
MEM_A6
MEM_A7
MEM_A4
MEM_A5
MEM_CKE
MEM_WE#
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_ODT
MEM_A10
MEM_A11
MEM_A12
MEM_BA0
MEM_BA1
MEM_BA2
MEM_DM1
MEM_DM0
MEM_ODT
MEM_DQS_P0
MEM_DQS_P1
MEM_DQS_N0
MEM_A13
MEM_DQS_N1
+MEM_VREF MEM_DQ0
MEM_DQ2
MEM_DQ4
MEM_DQ7
MEM_DQ6
MEM_DQ12
MEM_DQ5
MEM_DQ1
MEM_DQ3
MEM_DQ11
MEM_DQ9
MEM_CLKP
MEM_CLKN
MEM_DQ8
MEM_CKE
MEM_DQ15
MEM_DQ10
MEM_DQ13
MEM_CS#
MEM_DQ14
MEM_RAS#
MEM_WE#
MEM_CAS#
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A13
SP_DDR3_RST#21
+1.8VS
+1.1VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
RS880M SIDE PORT
Custom
13 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions
For Side port only
R342
243_0402_1%
SIDE@
1 2
C611
0.1U_0402_16V4Z
SIDE@
1
2
R338
1K_0402_1%
SIDE@
1 2
C605
2.2U_0603_6.3V4Z
SIDE@
1
2
R335
1K_0402_1%
SIDE@
1 2
C600
1U_0402_6.3V4Z
SIDE@
1
2
R341 10K_0402_5%SIDE@ 12
C602
0.1U_0402_16V4Z
SIDE@
1
2
C606
2.2U_0603_6.3V4Z
SIDE@
1
2
R340 100_0402_1%
@12
R339
1K_0402_1%
SIDE@
1 2
R337
1K_0402_1%
SIDE@
1 2
100-BALL
SDRAM DDR3
U27
K4W1G1646D-EC15_FBGA100
SIDE@
WE
L4
RAS
J4
CAS
K4
CS/CS0
L3
CKE/CKE0
K10
CK
J8
CK
K8
DQSU
B8
BA0
M3
BA1
N9
A2
P4
A3
N3
A4
P9
A5
P3
A6
R9
A7
R3
A8
T9
A9
R4
A10/AP
L8
A11
R8
DQL0 E4
DQL1 F8
DQL2 F3
DQL3 F9
DQL4 H4
DQL5 H9
DQL6 G3
DQL7 H8
VSSQ D2
VSS A10
VSS E2
VSS B4
NC/ODT1
J2
VDD B3
VDD D10
VDDQ A2
VDDQ A9
VDDQ C2
VDDQ C10
NC/CS1
L2
NC/CE1
J10
VDDQ E10
ZQ/ZQ0
L9
RESET
T3
DQSL
F4
DMU
D4 DML
E8
VSSQ B2
VSSQ B10
VSSQ D9
VSSQ E3
DQSU
C8
VSSQ E9
DQSL
G4
VDDQ F2
VSSQ F10
VSSQ G2
VDDQ H3
VDDQ H10
VSSQ G10
VREFCA
M9
VSS G9
VDD G8
ODT/ODT0
K2
A0
N4
A1
P8
VDD K3
A12
N8
VSS J3
VDD K9
DQU1 C4
DQU2 C9
DQU3 C3
DQU4 A8
DQU5 A3
DQU6 B9
DQU7 A4
DQU0 D8
A13
T4
A14
T8
A15/BA3
M8
BA2
M4
VREFDQ
H2
NC/ZQ1
L10
VDD N2
VDD N10
VDD R2
VDD R10
VSS J9
VSS M2
VSS M10
VSS P2
VSS P10
VSS T2
VSS T10
VDDQ D3
NC
A1
NC
A11
NC
T1
NC
T11
R333
0_0603_5%
1 2
C614
10U_0603_6.3V6M
SIDE@
1
2
C601
1U_0402_6.3V4Z
SIDE@
1
2
SBD_MEM/DVO_I/F
PAR 4 OF 6
U5D
RS880M_FCBGA528RS880MR1@
MEM_A0(NC)
AB12
MEM_A1(NC)
AE16
MEM_A2(NC)
V11
MEM_A3(NC)
AE15
MEM_A4(NC)
AA12
MEM_A5(NC)
AB16
MEM_A6(NC)
AB14
MEM_A7(NC)
AD14
MEM_A8(NC)
AD13
MEM_A9(NC)
AD15
MEM_A10(NC)
AC16
MEM_A11(NC)
AE13
MEM_A12(NC)
AC14
MEM_A13(NC)
Y14
MEM_BA0(NC)
AD16
MEM_BA1(NC)
AE17
MEM_BA2(NC)
AD17
MEM_RASb(NC)
W12
MEM_CASb(NC)
Y12
MEM_WEb(NC)
AD18
MEM_CSb(NC)
AB13
MEM_CKE(NC)
AB18
MEM_ODT(NC)
V14
MEM_CKP(NC)
V15
MEM_CKN(NC)
W14
MEM_DM0(NC) W17
MEM_DM1/DVO_D8(NC) AE19
MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
MEM_DQS1P(NC) AD20
MEM_DQS1N(NC) AE21
MEM_DQ0/DVO_VSYNC(NC) AA18
MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_DQ2/DVO_DE(NC) AA19
MEM_DQ3/DVO_D0(NC) Y19
MEM_DQ4(NC) V17
MEM_DQ5/DVO_D1(NC) AA17
MEM_DQ6/DVO_D2(NC) AA15
MEM_DQ7/DVO_D4(NC) Y15
MEM_DQ8/DVO_D3(NC) AC20
MEM_DQ9/DVO_D5(NC) AD19
MEM_DQ10/DVO_D6(NC) AE22
MEM_DQ11/DVO_D7(NC) AC18
MEM_DQ12(NC) AB20
MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
MEM_DQ15/DVO_D11(NC) AD21
MEM_COMPP(NC)
AE12
MEM_COMPN(NC)
AD12 MEM_VREF(NC) AE18
IOPLLVDD18(NC) AE23
IOPLLVSS(NC) AD23
IOPLLVDD(NC) AE24
R332
0_0603_5%
1 2
C604
10U_0603_6.3V6M
SIDE@
1
2
C609
0.1U_0402_16V4Z
SIDE@
1
2
C610
0.1U_0402_16V4Z
SIDE@
1
2
C608
0.1U_0402_16V4Z
SIDE@
1
2R336
40.2_0402_1%
SIDE@
12
R334
40.2_0402_1%
SIDE@
12
C603
0.1U_0402_16V4Z
SIDE@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTTX
+VDDHTRX
+VDDHT
+VDDA18PCIE
+1.1VS
+1.8VS
+3VS
+1.8VS
+1.1VS
+1.1VS
+1.8VS
+NB_CORE
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
14 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
RS880MPWR/GND
2A
+VDDHTTX@680mA
+VDDHT/+VDDHTRX@680mA
+VDDA11PCIE@2500mA
+VDDA18PCIE@640mA
+NB_CORE@7600mA
50mA
60mA
5mA
L13
0_0805_5%
12
C193
1U_0402_6.3V4Z
SIDE@
1
2
C170
0.1U_0402_16V4Z
1
2
C167 0.1U_0402_16V4Z
12
C160 1U_0402_6.3V4Z
1 2
C1840.1U_0402_16V4Z
1
2
C169
0.1U_0402_16V4Z
1
2
C162
0.1U_0402_16V4Z
1
2
C180
0.1U_0402_16V4Z
1
2
C2000.1U_0402_16V4Z
1 2
C166 0.1U_0402_16V4Z
12
C1870.1U_0402_16V4Z
1
2
C159 10U_0805_10V6K
C1830.1U_0402_16V4Z
1
2
C1850.1U_0402_16V4Z
1
2
C161 1U_0402_6.3V4Z
1 2
C163
0.1U_0402_16V4Z
1
2
C165 1U_0402_6.3V4Z
1 2
C154
0.1U_0402_16V4Z
1
2
C1860.1U_0402_16V4Z
1
2
L14
0_0805_5%
12
L12
0_0805_5%
12
C172
0.1U_0402_16V4Z
1
2
C1820.1U_0402_16V4Z
1
2
PART 6/6
GROUND
U5F
RS880M_FCBGA528 RS880MR1@
VSSAHT1
A25
VSSAHT2
D23
VSSAHT3
E22
VSSAHT4
G22
VSSAHT5
G24
VSSAHT6
G25
VSSAHT7
H19
VSSAHT8
J22
VSSAHT9
L17
VSSAHT10
L22
VSSAHT11
L24
VSSAHT12
L25
VSSAHT13
M20
VSSAHT14
N22
VSSAHT15
P20
VSSAHT16
R19
VSSAHT17
R22
VSSAHT18
R24
VSSAHT19
R25
VSSAHT21
U22
VSSAHT22
V19
VSSAHT23
W22
VSSAHT24
W24
VSSAHT25
W25
VSSAHT26
Y21
VSSAHT27
AD25
VSS2 D11
VSS3 G8
VSS4 E14
VSS5 E15
VSS7 J12
VSS8 K14
VSS9 M11
VSS10 L15
VSS11
L12
VSS12
M14
VSS13
N13
VSS14
P12
VSS15
P15
VSS16
R11
VSS17
R14
VSS18
T12
VSS19
U14
VSS20
U11
VSS21
U15
VSS22
V12
VSS23
W11
VSS24
W15
VSS25
AC12
VSS26
AA14
VSS27
Y18
VSS28
AB11
VSS29
AB15
VSS30
AB17
VSS31
AB19
VSS32
AE20
VSSAPCIE1 A2
VSSAPCIE2 B1
VSSAPCIE3 D3
VSSAPCIE4 D5
VSSAPCIE5 E4
VSSAPCIE6 G1
VSSAPCIE7 G2
VSSAPCIE8 G4
VSSAPCIE9 H7
VSSAPCIE10 J4
VSSAPCIE11 R7
VSSAPCIE12 L1
VSSAPCIE13 L2
VSSAPCIE14 L4
VSSAPCIE15 L7
VSS34
K11
VSSAPCIE16 M6
VSSAPCIE17 N4
VSSAPCIE18 P6
VSSAPCIE19 R1
VSSAPCIE20 R2
VSSAPCIE21 R4
VSSAPCIE22 V7
VSSAPCIE23 U4
VSSAPCIE24 V8
VSSAPCIE25 V6
VSSAPCIE26 W1
VSSAPCIE27 W2
VSSAPCIE28 W4
VSSAPCIE29 W7
VSSAPCIE30 W8
VSSAPCIE31 Y6
VSSAPCIE32 AA4
VSSAPCIE33 AB5
VSSAPCIE34 AB1
VSSAPCIE35 AB7
VSSAPCIE36 AC3
VSSAPCIE37 AC4
VSSAPCIE38 AE1
VSSAPCIE39 AE4
VSSAPCIE40 AB2
VSS1 AE14
VSSAHT20
H20
VSS33
AB21
VSS6 J15
C192
1U_0402_6.3V4Z
1
2
L82
0_0603_5%
SIDE@
1 2
PART 5/6
POWER
U5E
RS880M_FCBGA528 RS880MR1@
VDDHT_1
J17
VDDHT_2
K16
VDDHT_3
L16
VDDHT_4
M16
VDDHT_5
P16
VDDHT_6
R16
VDDHT_7
T16
VDDHTTX_1
AE25
VDDHTTX_2
AD24
VDDHTTX_3
AC23
VDDHTTX_4
AB22
VDDHTTX_5
AA21
VDDHTTX_6
Y20
VDDHTTX_7
W19
VDDHTTX_8
V18
VDDHTRX_1
H18
VDDHTRX_2
G19
VDDHTRX_3
F20
VDDHTRX_4
E21
VDDHTRX_5
D22
VDD18_1
F9
VDD18_2
G9
VDD18_MEM1(NC)
AE11
VDD18_MEM2(NC)
AD11
VDDA18PCIE_1
J10
VDDA18PCIE_2
P10
VDDA18PCIE_3
K10
VDDA18PCIE_10
Y9
VDDA18PCIE_11
AA9
VDDA18PCIE_12
AB9
VDDA18PCIE_13
AD9
VDDA18PCIE_14
AE9
VDDA18PCIE_6
W9
VDDA18PCIE_7
H9
VDDPCIE_1 A6
VDDPCIE_2 B6
VDDPCIE_3 C6
VDDPCIE_4 D6
VDDPCIE_5 E6
VDDPCIE_6 F6
VDDPCIE_7 G7
VDDPCIE_8 H8
VDDPCIE_9 J9
VDDA18PCIE_4
M10
VDDA18PCIE_5
L10
VDDC_1 K12
VDDC_2 J14
VDDC_3 U16
VDDPCIE_11 M9
VDDC_4 J11
VDDC_5 K15
VDDPCIE_10 K9
VDDC_6 M12
VDDC_7 L14
VDDC_8 L11
VDDC_9 M13
VDDC_10 M15
VDDC_11 N12
VDDC_12 N14
VDDC_13 P11
VDDC_14 P13
VDDC_15 P14
VDDC_16 R12
VDDC_17 R15
VDDC_18 T11
VDDC_19 T15
VDDC_20 U12
VDDC_21 T14
VDD33_1(NC) H11
VDD33_2(NC) H12
VDD_MEM1(NC) AE10
VDD_MEM2(NC) AA11
VDD_MEM3(NC) Y11
VDD_MEM4(NC) AD10
VDD_MEM6(NC) AC10
VDD_MEM5(NC) AB10
VDDA18PCIE_8
T10
VDDC_22 J16
VDDPCIE_12 L9
VDDA18PCIE_9
R10
VDDPCIE_13 P9
VDDPCIE_14 R9
VDDPCIE_15 T9
VDDPCIE_16 V9
VDDPCIE_17 U9
VDDA18PCIE_15
U10
VDDHTRX_6
B23
VDDHTRX_7
A23
VDDHTTX_9
U17
VDDHTTX_10
T17
VDDHTTX_11
R17
VDDHTTX_12
P17
VDDHTTX_13
M17
C157
0.1U_0402_16V4Z
1
2
C191
1000P_0402_50V7K
1
2
C155 10U_0805_10V6K
L18
0_0603_5%
1 2
C156
10U_0805_10V6K
C1810.1U_0402_16V4Z
1
2
C5990.1U_0402_16V4Z SIDE@
1
2
C158
0.1U_0402_16V4Z
1
2
C171
0.1U_0402_16V4Z
1
2
C18810U_0805_10V6K
1
2
C1940.1U_0402_16V4Z
1 2
C175
0.1U_0402_16V4Z
1
2
L16
0_0805_5%
12
C18910U_0805_10V6K
1
2
C6131U_0402_6.3V4Z SIDE@
1
2
C179
0.1U_0402_16V4Z
1
2
C150
4.7U_0805_10V4Z
1
2
C164 1U_0402_6.3V4Z
1 2
L11
FBMA-L11-201209-221LMA30T_0805
1 2
C6124.7U_0805_10V4Z SIDE@
1
2
C1780.1U_0402_16V4Z
1
2
C5970.1U_0402_16V4Z SIDE@
1
2
C153
0.1U_0402_16V4Z
1
2
C1770.1U_0402_16V4Z
1
2
C176
0.1U_0402_16V4Z
1
2
C173
4.7U_0805_10V4Z
1
2
C152
0.1U_0402_16V4Z
1
2
R67
0_0402_5%
NOSIDE@
12
C174
4.7U_0805_10V4Z
1
2
C5980.1U_0402_16V4Z SIDE@
1
2
C168
4.7U_0805_10V4Z
1
2
C151
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PLT_RST# 12,20,26,27,30,31,32
CRT_HSYNC12,17
CRT_VSYNC12,17
SUS_STAT#12,21
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
15 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
RS880M STRAPS
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
These pin straps are used to configure PCI-E GPP mode.
000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS880:SUS_STAT#
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS880 use HSYNC to enable SIDE PORT (internal pull high)
RS780 use register to control PCI-E configure
RS880: Enables Side port memory ( RS780 use HSYNC#)
RX881: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
Enables the Test Debug Bus using GPIO.
1 : Disable (RS880)
0 : Enable (RS880)
PIN: RS880-->VSYNC#
RS880 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K
1. Disable (RS880)
0 : Enable (RS880)
R69 3K_0402_5%@
12
R68 3K_0402_5%
12
R70 3K_0402_5%
12
D5
CH751H-40PT_SOD323-2
@
2 1
R71 3K_0402_5%
SIDE@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6051P
1.0
CLOCK GENERATOR
Custom
16 45Tuesday, March 23, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Use SB820M internal clock gen
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RJ45_GND
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI1-
RJ45_GND27
UMA_CRT_CLK12
UMA_CRT_DATA12
CRT_VSYNC12,15
CRT_HSYNC12,15
RJ45_MIDI0+27
RJ45_MIDI0-27
CRT_R12
CRT_G12
CRT_B12
RJ45_MIDI1+27
RJ45_MIDI1-27
+3VS
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
17 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
CRT/TV-OUT Connector
CRT+RJ45 FFC conn
Pin=20pin, pitch=0.5
1/28 Fine tune JP4 pin define
1/31 EMI request
3/23 switch noise soluation
C914
10P_0402_25V8K
@
1
2
C915
10P_0402_25V8K
@
1
2
C909
0.1U_0402_16V4Z
1
2
JP4
STARC_107K20-000000-G4
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20 GND1 21
GND2 22
C910
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC_INVT_PWM
GMCH_INVT_PWM
ENVDD
LCD_TXOUT2-
USB20_P9_R
LCD_TXCLK-
INVT_PWM
LCD_TXOUT1+
LCD_TXOUT0+
LCD_TXOUT2+
LCD_EDID_DATA
INVT_PWM
LCD_EDID_CLK
LCD_TXOUT1-
INVT_PWM
USB20_N9_R
+3VS_USB
+LCDVDD_R
LCD_TXOUT0-
LCD_TXCLK+
LCD_EDID_DATA
LCD_EDID_CLK
+LCD_INV
+LCDVDD_R
INT_MIC_CLK
INT_MIC_DATA
USB20_N9 USB20_N9_R
USB20_P9_RUSB20_P9
BKOFF# BKOFF#_R
GMCH_INVT_PWM12
EC_INVT_PWM31
UMA_ENVDD12
LCD_TXOUT1-12
LCD_TXOUT0-12
LCD_TXOUT0+12
INT_MIC_DATA28
LCD_TXCLK+12
INT_MIC_CLK28
LCD_TXOUT1+12
LCD_EDID_CLK12
LCD_TXOUT2+12
LCD_TXOUT2-12
LCD_EDID_DATA12
LCD_TXCLK-12
USB20_N921
USB20_P921
BKOFF#31
+LCD_VDD
+3VS
+LCD_VDD
+LCD_VDD +3VS
+3VS
+3VS
+3VS
B+
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
LCD CONN.
Custom
18 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
1.5A
LCD/PANEL BD. Conn.
< LVDS Connector >
Inrush current = 0A
W= 60 mils
W= 60 mils
1/19 R782-->@ and R783/R784-->SMT for VB function
1/25 Pin24 +LCD_INV-->NC
R784
10K_0402_5%
12
R81 4.7K_0402_5%
1 2
R919
22_0402_5%
1 2
C204
0.1U_0402_16V4Z
1
2
D16
PACDN042Y3R_SOT23-3
2
3
1
R783 0_0402_5%
1 2
C215
0.1U_0402_16V4Z
@
1
2
R80 4.7K_0402_5%
1 2
R73
100K_0402_5%
12
C212
68P_0402_50V8J
1
2
R75 0_0402_5%
1 2
C208
0.1U_0402_16V4Z
1
2
L19
0_0805_5%
12
R7910K_0402_5% 12
C203
4.7U_0805_10V4Z
@
1
2
C206
4.7U_0805_10V4Z
1
2
L83
WCM-2012-900T_0805
1
122
33
4
4
G
D
S
Q3
AO3413_SOT23
2
1 3
C211
1000P_0402_50V7K
@
1
2
C214
0.1U_0402_25V4K
@1
2
L20
FBMA-L11-201209-221LMA30T_0805
1 2
C202
0.01U_0402_25V7K
1
2
C205
0.1U_0402_16V4Z
1
2
Q2A
2N7002DW-T/R7_SOT363-6
61
2
R798 0_0402_5%
@
1 2
R77 0_0603_5%
1 2
Q2B
2N7002DW-T/R7_SOT363-6
3
5
4
R74
47K_0402_5%
1 2
R799 0_0402_5%
@
1 2
JLVDS1
I-PEX_20143-030E-20F~D
CONN@
29
29
27
27
25
25
23
23
21
21
19
19
16
16 15
15
13
13
11
11
9
9
7
7
2
2
4
4
5
5
30
30
28
28
26
26
24
24
22
22
20
20
18
18 17
17
14
14
12
12
10
10
8
8
6
6
1
1
3
3
MGND1 31
MGND2 32
MGND3 33
MGND4 34
R76
100K_0402_5%
12
R72
150_0603_5%
12
R782 0_0402_5%
@
1 2
C201
0.1U_0402_16V7K
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDMI_TX0+
HDMI_TX1-
HDMI_TX0-
HDMI_TX2+
HDMI_TX2-
HDMI_CLK+
HDMI_TX1+
HDMI_CLK-
HDMI_HPD
HDMI_R_D0+
HDMI_R_CK-
HDMI_R_CK+HDMI_CLK+
HDMI_CLK-
HDMI_TX0-
HDMI_TX0+
HDMI_R_D0-
HDMI_TX1+
HDMI_R_D2-
HDMI_R_D2+
HDMI_TX2-
HDMI_TX2+
HDMI_TX1- HDMI_R_D1-
HDMI_R_D1+
+5VS_HDMI+5VS_HDMI
HDMI_HPD
HDMI_R_D1-
HDMI_SCLK
HDMI_R_D1+
HDMI_R_D2+
HDMI_R_CK+
HDMI_R_D0+
HDMI_R_D2-
HDMI_R_CK-
HDMI_SDATA
HDMI_R_D0-
HDMI_SDATA
HDMI_SCLK
HDMI_CLK+
HDMI_CLK-
HDMI_TX0-
HDMI_TX0+
HDMI_TX1+
HDMI_TX2-
HDMI_TX2+
HDMI_TX1-
HDMI_CLK0+11
HDMI_CLK0-11
HDMI_TXD0+11
HDMI_TXD1+11
HDMI_TXD2+11
HDMI_TXD2-11
HDMI_TXD0-11
HDMI_TXD1-11
HPD 12
HDMICLK_UMA12
HDMIDAT_UMA12
+HDMI_5V_OUT+5VS
+HDMI_5V_OUT
+3VS +3VS
+3VS
+HDMI_5V_OUT
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
19 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
HDMI/CEC
< HDMI Connector >
1/28 Update JHDMI1 footprint
F1
1.1A_6V_MINISMDC110F-2
2 1
L24
WCM-2012-900T_0805
1
122
33
4
4
C225 0.1U_0402_16V7K
1 2
JHDMI1
SUYIN_100042GR019M23BZR_19P-T
CONN@
D2+
1D2_shield
2D2-
3D1+
4D1_shield
5D1-
6D0+
7D0_shield
8D0-
9CK+
10 CK_shield
11 CK-
12 CEC
13 Reserved
14 SCL
15 SDA
16 DDC/CEC_GND
17 +5V
18 HP_DET
19
GND 20
GND 21
GND 22
GND 23
R98 715_0402_1%
1 2
R85
4.7K_0402_5%
1 2
C218
0.1U_0402_16V4Z
1
2
R91 0_0402_5%
@1 2
C216
0.1U_0402_16V4Z
1
2
R855
2.2K_0402_5%
12
R99 0_0402_5%
@1 2
R86
100K_0402_5%
1 2
R93 715_0402_1%
1 2
R96 0_0402_5%
@1 2
R856
2.2K_0402_5%
12
L22
WCM-2012-900T_0805
1
122
33
4
4
R94 715_0402_1%
1 2
R92 0_0402_5%
@1 2
C223 0.1U_0402_16V7K
1 2
Q4A
2N7002DW-T/R7_SOT363-6
61
2
R89 715_0402_1%
1 2
R100 0_0402_5%
@1 2
R88 0_0402_5%
@1 2
C224 0.1U_0402_16V7K
1 2
C221 0.1U_0402_16V7K
1 2
R83
2.2K_0402_5%
12
Q4B
2N7002DW-T/R7_SOT363-6
3
5
4
R101 715_0402_1%
1 2
L21
WCM-2012-900T_0805
1
122
33
4
4
R103 0_0402_5%
@1 2
R87
100K_0402_5%
1 2
R90 715_0402_1%
1 2
C222 0.1U_0402_16V7K
1 2
C220 0.1U_0402_16V7K
1 2
C226 0.1U_0402_16V7K
1 2
R97 715_0402_1%
1 2
C219 0.1U_0402_16V7K
1 2
U6
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R84
4.7K_0402_5%
12
L23
WCM-2012-900T_0805
1
122
33
4
4
D8
RB161M-20_SOD123-2
2 1
G
D
S
Q6
2N7002_SOT23-3
2
13
R102 715_0402_1%
1 2
C217
0.1U_0402_16V4Z
1
2
R95 0_0402_5%
@1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
A_RST#
H_PW RGD
SB_32KHO
25M_CLK_X1
SB_RX3P_C
SB_TX2N
SB_RX3N_C
BT_RST#
25M_CLK_X2
SB_TX3P
SB_TX1N
SB_RX0P_C
CLK_PCIE_LAN#_R
PCI_AD23
H_PW RGD
SB_TX0N
CLK_SBLINK_BCLK#_R
LPC_AD1
LPC_FRAME#
PCI_AD25
PCI_AD29
SB_TX1P
PCI_CLK1
LPC_AD0
LDT_RST#
SB_RX2P_C
SB_TX0P
CLK_SBLINK_BCLK_R
PCI_AD27
CLK_PCIE_MCARD2_R
CLK_NBHT_R
SB_32KHI
SB_RX1N_C
PCI_CLK2
PCI_AD26
BT_DET#
CLK_NBHT#_R
CLK_CPU_BCLK#_R
PCI_AD24
LDT_STOP#
LPC_AD2
CLK_PCI_EC1
PCI_AD28
SB_RX1P_C
CLK_PCIE_MCARD2#_R
SERIRQ
CLK_NB_REFCLK#_R
SB_32KHI
LPC_AD3
25M_CLK_X1
SB_RX0N_C
CLK_CPU_BCLK_R
SB_TX2P
CPU_LDT_REQ#
25M_CLK_X2
PCI_CLK4
BT_PWR#
SB_RX2N_C
PCI_CLK3
SB_TX3N
CLK_PCIE_LAN_R
SB_32KHO
H_PROCHOT#
CLK_NB_REFCLK_R
CLK_PCIE_MCARD0_R
CLK_PCIE_MCARD0#_R
PLT_RST#
A_RST#
RTCCLK
SB_RX0P11
SB_RX0N11
SB_RX1P11
SB_RX1N11
SB_RX2P11
SB_RX2N11
SB_RX3P11
SB_RX3N11
CLK_PCI_EC 24,31
H_PW RGD_L 42
CLK_PCIE_MCARD226
CLK_PCIE_MCARD2#26
CLK_SBLINK_BCLK12
CLK_SBLINK_BCLK#12
CLK_CPU_BCLK7
CLK_CPU_BCLK#7
CLK_PCIE_LAN27
CLK_PCIE_LAN#27
CLK_NB_REFCLK12
CLK_NB_REFCLK#12
CLK_NBHT12
CLK_NBHT#12
BT_PW R# 26,29
LPC_AD2 31,32
PCI_AD28 24
LPC_FRAME# 31,32
SB_TX2N11
H_PROCHOT# 7
SB_TX2P11
PCI_AD29 24
PCI_AD27 24
LPC_AD1 31,32
CPU_LDT_REQ# 12
PCI_AD24 24
SB_TX1P11
PCI_CLK1 24
SB_TX0N11
PCI_AD26 24
LDT_RST# 7
LPC_CLK1 24,32
LPC_AD3 31,32
PCI_CLK3 24
LDT_STOP# 7,12
SB_TX0P11
PCI_AD23 24
BT_RST# 29
PCI_AD25 24
SB_TX3N11
PCI_CLK2 24
LPC_AD0 31,32
PCI_CLK4 24
SERIRQ 31,32
SB_TX3P11
SB_TX1N11
BT_DET# 29
H_PW RGD 7,42
CLK_PCIE_MCARD030
CLK_PCIE_MCARD0#30
PLT_RST# 12,15,26,27,30,31,32
3G_OFF# 26
RTCCLK 31
+RTCVCC
+CHGRTC
+RTCBATT
+PCIE_VDDR
+1.8VS
+3VS
+SB_VBAT
+3VALW
+RTCVCC_R
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-6032P
1.0
SB820-PCIE/PCI/ACPI/LPC/RTC
Custom
20 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
W=20mils
Close to SB within 1"
L
ISL6265 PWROK input, TTL level: 0.8V~2.0V
When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
level shift to ISL6265
LAN
WLAN
CPU
NB
Card reader
NB
NB
12/7 Add RS1~RS14 for internal clock gen
2/2 C240 C244 22P-->18P for RTC fail issue
2/8 GPIO35-->GPIO40 for 3G_OFF#
W=20mils
W=20milsW=20milsW=20mils
3/22 add RTCCLK to KBC 32.768
RS7 0_0402_5%
12
RS14 0_0402_5%
12
G
D
S
Q29
FDV301N_NL_SOT23-3
2
13
R104 590_0402_1%
12
C705 22P_0402_50V8J
12
C230 0.1U_0402_16V7K
1 2
J1
JUMP_43X39
@
1
122
D9
BAS40-04_SOT23-3
1
2
3
R918
1K_0402_5%
1 2
RS2 0_0402_5%
12
C234 0.1U_0402_16V7K
1 2
R326 33_0402_5%
12
R314
4.7K_0402_5%
1 2
RS1 0_0402_5%
12
R129
120_0402_5%
1 2
T31 PAD @
R106 8.2K_0402_5%
@
12
C233 0.1U_0402_16V7K
1 2
RS11 0_0402_5%
12
C524 150P_0402_50V8J
1 2
C242
1U_0402_6.3V4Z
1
2
RS5 0_0402_5%
12
C241
0.1U_0402_16V4Z
1
2
RS8 0_0402_5%
12
C231 0.1U_0402_16V7K
1 2
T34 PAD@
RS6 0_0402_5%
12
C640
22P_0402_50V8J
1
2
RS4 0_0402_5%
12
T32 PAD @
C229 0.1U_0402_16V7K
1 2
C235
0.1U_0402_16V4Z
12
C240 18P_0402_50V8J
12
R917
120_0402_5%
1 2
RS9 0_0402_5%
12
Y6
25MHZ_20PF_7A25000012
12
R920 0_0402_5%
@
1 2
RS12 0_0402_5%
12
R829
1M_0402_5%
12
Y2
32.768KHZ_12.5PF_Q13MC14610002
OSC 4
OSC 1
NC
3
NC
2
C232 0.1U_0402_16V7K
1 2
U8
NC7SZ08P5X_NL_SC70-5
B
2
A
1Y4
P5
G
3
RS3 0_0402_5%
12
RS13 0_0402_5%
12
PCI EXPRESS INTERFACES
Part 1 of 5
SB800
PCI INTERFACELPC
RTC
PCI CLKS
CLOCK GENERATOR
CPU
U7A
SB820M_FCBGA605 SB820MR1@
A_RST#
L1
A_RX2P
AC24
A_RX2N
AC25
A_RX3P
AB25
A_TX3N
AB27 A_TX3P
AB26 A_TX2N
AB28 A_TX2P
AB29
A_RX1P
AD25
A_RX1N
AD24
A_RX0P
AE24
A_RX0N
AE23
A_TX1N
AC29 A_TX1P
AC28 A_TX0N
AD27 A_TX0P
AD26
PCIE_RCLKP/NB_LNK_CLKP
M23
PCIE_RCLKN/NB_LNK_CLKN
P23
PCIE_CALRP
AD29
PCIE_CALRN
AD28
GPP_CLK1N
N28
VDDBT_RTC_G B1
GPP_CLK0N
L28
GPP_CLK2P
M29
CPU_HT_CLKN
T21
GPP_CLK2N
M28
SLT_GFX_CLKP
V23
CPU_HT_CLKP
V21
PCICLK0 W2
PCICLK1/GPO36 W1
PCICLK2/GPO37 W3
PCICLK3/GPO38 W4
PCIRST# V2
CBE0# AA8
CBE1# AD5
CBE2# AD8
CBE3# AA10
FRAME# AE8
DEVSEL# AB9
IRDY# AJ3
TRDY# AE7
PAR AC5
STOP# AF5
PERR# AE6
REQ0# AE11
REQ1#/GPIO40 AH5
REQ2#/CLK_REQ8#/GPIO41 AH4
REQ3#/CLK_REQ5#/GPIO42 AC12
GNT0# AD12
GNT1#/GPO44 AJ5
GNT2#/GPO45 AH6
GNT3#/CLK_REQ7#/GPIO46 AB12
SERR# AE4
CLKRUN# AB11
LAD0 J27
LAD1 J26
LAD2 H29
LAD3 H28
LFRAME# G28
LDRQ0# J25
SERIRQ/GPIO48 AB19
PCICLK4/14M_OSC/GPO39 Y1
LPCCLK0 H24
LPCCLK1 H25
AD0/GPIO0 AA1
AD1/GPIO1 AA4
AD2/GPIO2 AA3
AD3/GPIO3 AB1
AD4/GPIO4 AA5
AD5/GPIO5 AB2
AD6/GPIO6 AB6
AD7/GPIO7 AB5
AD8/GPIO8 AA6
AD9/GPIO9 AC2
AD10/GPIO10 AC3
AD12/GPIO12 AC1
AD13/GPIO13 AD1
AD14/GPIO14 AD2
AD15/GPIO15 AC6
AD16/GPIO16 AE2
AD17/GPIO17 AE1
AD18/GPIO18 AF8
AD19/GPIO19 AE3
AD20/GPIO20 AF1
AD21/GPIO21 AG1
AD22/GPIO22 AF2
AD23/GPIO23 AE9
AD24/GPIO24 AD9
AD25/GPIO25 AC11
AD26/GPIO26 AF6
AD27/GPIO27 AF4
AD28/GPIO28 AF3
AD29/GPIO29 AH2
AD30/GPIO30 AG2
AD31/GPIO31 AH3
AD11/GPIO11 AC4
LDRQ1#/CLK_REQ6#/GPIO49 AA18
GPP_CLK1P
N29
RTCCLK D2
A_RX3N
AB24
INTE#/GPIO32 AJ6
INTF#/GPIO33 AG6
INTG#/GPIO34 AG4
INTH#/GPIO35 AJ4
LOCK# AD7
NB_HT_CLKP
T26
GPP_CLK3N
V25
INTRUDER_ALERT# B2
NB_DISP_CLKP
U29
14M_25M_48M_OSC
L25
GPP_CLK0P
L29
NB_HT_CLKN
T27
SLT_GFX_CLKN
T23
GPP_CLK3P
T25
25M_X1
L26
25M_X2
L27
NB_DISP_CLKN
U28
GPP_CLK4P
L24
GPP_CLK4N
L23
GPP_CLK5P
P25
GPP_CLK5N
M25
GPP_CLK6P
P29
GPP_CLK6N
P28
GPP_CLK7P
N26
GPP_CLK7N
N27
GPP_CLK8P
T29
GPP_CLK8N
T28
GPP_TX0P
AA28
GPP_TX0N
AA29
GPP_TX1P
Y29
GPP_TX1N
Y28
GPP_TX2P
Y26
GPP_TX2N
Y27
GPP_TX3P
W28
GPP_TX3N
W29
GPP_RX0P
AA22
GPP_RX0N
Y21
GPP_RX1P
AA25
GPP_RX1N
AA24
GPP_RX2P
W23
GPP_RX2N
V24
GPP_RX3P
W24
GPP_RX3N
W25
PCIE_RST#
P1
ALLOW_LDTSTP/DMA_ACTIVE# G21
LDT_RST# J24
32K_X1 C1
32K_X2 C2
PROCHOT# H21
LDT_STP# G22
LDT_PG K19
C227 0.1U_0402_16V7K
1 2
C244
18P_0402_50V8J
12
C243
0.1U_0402_16V4Z
1
2
RS10 0_0402_5%
12
C704
22P_0402_50V8J
12
R125 22_0402_5%
1 2
R132
20M_0402_5%
12
R105 2K_0402_1%
12
C228 0.1U_0402_16V7K
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC_SCI#
KB_RST#
GATEA20
EC_SMI#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SUS_STAT#
SB_PWRGD
NB_PWRGD
H_THERMTRIP#
EC_RSMRST#
SMB_CK_DAT1
SMB_CK_CLK1
PCH_SPKR
SMB_CK_DAT0
SMB_CK_CLK0
EC_LID_OUT#
USB_OC#0
USB_RCOMP
USB20_N9
USB20_N2
USB20_P2
USB20_P1
USB20_N1
USB20_P0
USB20_N0
USB20_P6
USB20_N6
USB20_P9
USB20_N8
USB20_P8
SUS_STAT#
EC_RSMRST#
SMB_CK_CLK0
SMB_CK_DAT0
GBE_PHY_INTR
GBE_MDIO
GBE_COL
GBE_CRS
GBE_RXERR
GBE_PHY_INTR
GBE_MDIO
SB_SIC
SB_SID
SMB_CK_CLK1
SMB_CK_DAT1
H_THERMTRIP#
EC_LID_OUT#
SB_SIC
SB_SID
SP_DDR3_RST#_R
USB_OC#2
EC_SWI#
EC_SWI#
GPIO201
GPIO202
GPIO203
GPIO201
GPIO202
GPIO203
GBE_COL
GBE_CRS
GBE_RXERR
USBCLK
CIR_EN#
CIR_EN#
USB20_N5
USB20_P5
SUS_STAT#12,15
PBTN_OUT#31
KB_RST#31
GATEA2031
EC_SMI#31
EC_SCI#31
PM_SLP_S3#31
PM_SLP_S5#31
SB_PWRGD31
H_THERMTRIP#7
NB_PWRGD12
EC_RSMRST#31
PCH_SPKR28
SMB_CK_DAT126
SMB_CK_CLK126
EC_LID_OUT#31
USB_OC#029,31
USB20_P0 29
USB20_N0 29
USB20_N2 25
USB20_P2 25
USB20_P1 29
USB20_N1 29
USB20_P6 29
USB20_N6 29
USB20_N8 26
USB20_P8 26
USB20_N9 18
USB20_P9 18
AZ_SDIN0_HD28
AZ_SDOUT_HD28
AZ_BITCLK_HD28
HDA_SDOUT24
SMB_CK_CLK09,10
SMB_CK_DAT09,10
SP_DDR3_RST#13
GPIO199 24
GPIO200 24
USB_OC#225,31
EC_SWI#27
AZ_SYNC_HD28
AZ_RST_HD#28
CLKREQ_LAN27
CLKREQ_MCARD2#26
USB20_N5 26
USB20_P5 26
CR_CPPE#_SB30
+3VS
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
21 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
SB820 USB/HD Audio
STRAP PIN
STRAP PIN
Close to SB within 1"
USB-9 Int Camera
USB-2 USB/eSATA
USB-6 Bluetooth
USB-1 Right side
USB-8 WLAN
EHCI2 / OHCI2
EHCI13 / OHCI3
<Wake Up support>
EHCI1 / OHCI1
OHCI4
GPIO201 GPIO202 GPIO203
AMD-S 11.6
AMD-M 13.3
111
110
12/7 Internal clock gen
LAN
3/17 del CLKREQ_CR#
WLAN
L
USB-0 Right side
USB-5 WWAN
1/21 Change USB port10 to USB port5 on WWAN
1/31 R133 8.2K-->11.8K
3/17 for JMB389
R134 4.7K_0402_5%
1 2 R343
0_0402_5%
SIDE@
1 2
R827
10K_0402_5%
@
12
R320 2.2K_0402_5%
1 2
R310 33_0402_5%
1 2
R319 2.2K_0402_5%
1 2
R863 10K_0402_5%
12
R155 10K_0402_5%
12
R311 33_0402_5%
1 2
T28PAD@
R315 100K_0402_5%
@
1 2
R152 10K_0402_5%
12
R828
10K_0402_5%
M@
12
R318 10K_0402_5%
1 2
R306 33_0402_5%
1 2
R825
10K_0402_5%
S@
12
R151 10K_0402_5%
12
T30PAD@
R140 100K_0402_5%
12
C632
33P_0402_50V8J
1
2R824
10K_0402_5%
12
R316 2.2K_0402_5%
1 2
R141 2.2K_0402_5%
1 2
R823
10K_0402_5%
12
R317 2.2K_0402_5%
1 2
R826
10K_0402_5%
@
12
R153 10K_0402_5%
12
T29PAD@
R307 33_0402_5%
1 2
R13311.8K_0402_1%
1 2
R154 10K_0402_5%
12
USB 2.0
Part 4 of 5
SB800
ACPI / WAKE UP EVENTS
GPIO
HD AUDIO
USB OC USB 1.1 USB MISCEMBEDDED CTRL
EMBEDDED CTRL
GBE LAN
U7D
SB820M_FCBGA605 SB820MR1@
USBCLK/14M_25M_48M_OSC A10
USB_OC6#/IR_TX1/GEVENT6#
D1
USB_HSD5P D16
USB_HSD5N C16
USB_HSD4P B14
USB_HSD4N A14
USB_HSD3P E18
USB_HSD3N E16
USB_HSD2P J16
USB_HSD2N J18
USB_HSD1P B17
USB_HSD1N A17
USB_HSD0P A16
USB_HSD0N B16
USB_OC4#/IR_RX0/GEVENT16#
D4
USB_OC3#/AC_PRES/TDO/GEVENT15#
E8
USB_OC1#/TDI/GEVENT13#
E7 USB_OC2#/TCK/GEVENT14#
F7
USB_HSD7P G12
USB_HSD7N G14
USB_HSD6P G16
USB_HSD6N G18
USB_OC0#/TRST#/GEVENT12#
F8
DDR3_RST#/GEVENT7#
H4
CLK_REQ4#/SATA_IS0#/GPIO64
AD19
AZ_SDIN3/GPIO170
M4
PCI_PME#/GEVENT4#
J2
RI#/GEVENT22#
K1
SLP_S3#
F1
SLP_S5#
H1
PWR_BTN#
F2
PWR_GOOD
H5
SUS_STAT#
G6
GBE_LED1/GEVENT9#
D7 GBE_LED0/GPIO183
D5
GA20IN/GEVENT0#
AD21
KBRST#/GEVENT1#
AE21
THRMTRIP#/SMBALERT#/GEVENT2#
J6
LPC_PME#/GEVENT3#
K2
LPC_SMI#/GEVENT23#
J29
GEVENT5#
H2
SYS_RESET#/GEVENT19#
J1
WAKE#/GEVENT8#
H6
RSMRST#
G1
CLK_REQ3#/SATA_IS1#/GPIO63
AA16
NB_PWRGD
AC19
SMARTVOLT1/SATA_IS2#/GPIO50
AB21
SMARTVOLT2/SHUTDOWN#/GPIO51
AJ21
SPKR/GPIO66
AF19
SCL0/GPIO43
AD22
SDA0/GPIO47
AE22
CLK_REQ2#/FANIN4/GPIO62
AH21
CLK_REQ1#/FANOUT4/GPIO61
AB18
GBE_CRS
T4 GBE_COL
T1
AZ_SYNC
N2
USB_HSD9P A13
USB_HSD9N B13
USB_HSD8P D13
USB_HSD8N C13
IR_LED#/LLB#/GPIO184
E1
IR_RX1/GEVENT20#
F3
USB_OC5#/IR_TX0/GEVENT17#
E4
BLINK/USB_OC7#/GEVENT18#
H3
SCL1/GPIO227
F5
SDA1/GPIO228
F4
CLK_REQ0#/SATA_IS3#/GPIO60
AC18
AZ_SDIN2/GPIO169
M1
AZ_SDIN0/GPIO167
L2
SATA_IS4#/FANOUT3/GPIO55
AF20
SATA_IS5#/FANIN3/GPIO59
AE19
USB_FSD1P/GPIO186 J10
USB_FSD1N H11
USB_FSD0P/GPIO185 H9
USB_FSD0N J8
USB_HSD11P E14
USB_HSD11N E12
USB_HSD10P J12
USB_HSD10N J14
KSO_17/GPIO226 B22
EC_PWM0/EC_TIMER0/GPIO197 F25
SCL2/GPIO193 D25
SDA2/GPIO194 F23
SCL3_LV/GPIO195 B26
SDA3_LV/GPIO196 E26
EC_PWM1/EC_TIMER1/GPIO198 E22
EC_PWM2/EC_TIMER2/GPIO199 F22
EC_PWM3/EC_TIMER3/GPIO200 E21
KSI_0/GPIO201 G24
KSI_1/GPIO202 G25
KSI_2/GPIO203 E28
KSI_3/GPIO204 E29
KSI_4/GPIO205 D29
KSI_5/GPIO206 D28
KSI_6/GPIO207 C29
KSI_7/GPIO208 C28
PS2_DAT/SDA4/GPIO187
E23
PS2_CLK/SCL4/GPIO188
E24
SPI_CS2#/GBE_STAT2/GPIO166
F21
FC_RST#/GPO160
G29
PS2KB_DAT/GPIO189
D27
PS2KB_CLK/GPIO190
F28
PS2M_DAT/GPIO191
F29
PS2M_CLK/GPIO192
E27
KSO_16/GPIO225 A22
KSO_0/GPIO209 B28
KSO_1/GPIO210 A27
KSO_2/GPIO211 B27
KSO_3/GPIO212 D26
KSO_4/GPIO213 A26
KSO_5/GPIO214 C26
KSO_6/GPIO215 A24
KSO_7/GPIO216 B25
KSO_8/GPIO217 A25
KSO_9/GPIO218 D24
KSO_10/GPIO219 B24
KSO_11/GPIO220 C24
KSO_12/GPIO221 B23
KSO_13/GPIO222 A23
KSO_14/GPIO223 D22
KSO_15/GPIO224 C22
USB_HSD13P B12
USB_HSD13N A12
USB_HSD12P F11
USB_HSD12N E11
GBE_TXD2
P9 GBE_TXD3
M5
GBE_MDCK
L6
GBE_MDIO
L5
GBE_RXCLK
T9
AZ_BITCLK
M3
AZ_SDOUT
N1
AZ_SDIN1/GPIO168
M2
AZ_RST#
P2
GBE_RXCTL/RXDV
T5
GBE_RXERR
V5
GBE_TXCLK
P5
GBE_RXD0
U2
GBE_RXD2
U3 GBE_RXD3
U1
GBE_TXCTL/TXEN
M7
GBE_PHY_PD
P4
GBE_PHY_RST#
M9
GBE_PHY_INTR
V7
SPI_CS3#/GBE_STAT1/GEVENT21#
D3
GBE_LED2/GEVENT10#
G5
GBE_TXD1
T7
GBE_RXD1
T2
GBE_TXD0
P7
GBE_STAT0/GEVENT11#
K3
TEST0
B3
TEST1/TMS
C4
TEST2
F6
CLK_REQG#/GPIO65/OSCIN
AA20
USB_RCOMP G19
T35 PAD @
R797 10K_0402_5%
1 2
R807
10K_0402_5% @
1 2
R142 2.2K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SLP_CHG_M3
SLP_CHG_M4
SATA_CALRP
SATA_CALRN
SATA_TX0+
SATA_TX0-
SATA_RX0-
SATA_RX0+
SATA_TX3+
SATA_TX3-
SATA_RX3-
SATA_RX3+
CS#
CLK
DI DO
CS#
DI
DO
CLK
ACIN_SB
WWAN_PWR_EN#
WLAN_PWR_EN#
CLK
SLP_CHG_M3
SLP_CHG_M4
SLP_CHG_M3_SB
SLP_CHG_M4_SB
SATA_X1
SATA_X2
SLP_CHG_M3_SB_NEW
SATA_LED#33
SATA_RX0+25
SATA_RX0-25
SATA_TX0+25
SATA_TX0-25
SATA_TX3+25
SATA_TX3-25
SATA_RX3+25
SATA_RX3-25
ACIN 31,33,35
WWAN_PWR_EN# 26
WLAN_PWR_EN# 26
SLP_CHG_M4 25,31
SLP_CHG_M3 25,31
CR_WAKE# 30
+3VALW
+3VS
+1.1VS_SATA +3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
SB820 SATA/IDE/SPI
Custom
22 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Close to SB within 1"
L
HDD
eSATA
20mils
1/20 Colay USB charger net
12/31 SMT memo control (256KB MX25L1605DM2I-12G SOP 8P)
1/25 Del R164 Y3 C246 C247 add TP36 TP37
3/17 for JMB389
R162 100K_0402_5%
1 2
C470
0.1U_0402_16V4Z
@
1
2
R916 0_0402_5%
1 2
T37 PAD@
R322 931_0402_1%
12
R865 0_0402_5%@1 2
C707
22P_0402_50V8J
@
1
2
R859
0_0402_5%
@
12
R321 1K_0402_1%
12
R866 0_0402_5%
1 2
R163 100K_0402_5%
1 2
T36 PAD@
U47
SST25LF080A_SO8-200mil
S
1
VCC
8
Q2
HOLD
7
VSS 4
D
5
C
6
W
3
FLASH
Part 2 of 5
SB800
SERIAL ATA
SPI ROM
HW MONITOR
U7B
SB820M_FCBGA605 SB820MR1@
FC_CLK AH28
FC_FBCLKOUT AG28
FC_FBCLKIN AF26
FC_INT1/GPIOD144 AF29
FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
FC_INT2/GPIOD147 AH27
FC_WE#/GPIOD148 AG26
FC_CE1#/GPIOD149 AF27
FC_CE2#/GPIOD150 AE29
FC_ADQ0/GPIOD128 AJ27
FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
FC_ADQ3/GPIOD131 AH24
FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
FC_ADQ6/GPIOD134 AJ22
FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
FC_ADQ9/GPIOD137 AH22
FC_ADQ10/GPIOD138 AJ23
FC_ADQ11/GPIOD139 AF23
FC_ADQ12/GPIOD140 AJ24
FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
FC_ADQ15/GPIOD143 AH26
SATA_TX2P
AG12
SATA_TX2N
AF12
SATA_RX2P
AH12 SATA_RX2N
AJ12
SATA_TX3P
AH14
SATA_TX3N
AJ14
SATA_RX3P
AF14 SATA_RX3N
AG14
SATA_TX0P
AH9
SATA_TX0N
AJ9
SATA_RX0N
AJ8
SATA_RX0P
AH8
SATA_TX1P
AH10
SATA_TX1N
AJ10
SATA_RX1N
AG10
SATA_RX1P
AF10
SATA_CALRN
AA14
SATA_X1
AD16
SATA_X2
AC16
SATA_ACT#/GPIO67
AD11
FANOUT1/GPIO53 W6
FANOUT2/GPIO54 Y9
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
FANIN2/GPIO58 W8
VIN0/GPIO175 A3
VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
VIN4/GPIO179 A7
VIN5/GPIO180 B7
VIN6/GBE_STAT3/GPIO181 B8
VIN7/GBE_LED3/GPIO182 A8
TEMPIN0/GPIO171 B6
TEMPIN1/GPIO172 A6
TEMPIN2/GPIO173 A5
TEMPIN3/TALERT#/GPIO174 B5
FANOUT0/GPIO52 W5
TEMP_COMM C7
SATA_TX4P
AG17
SATA_TX4N
AF17
SATA_RX4N
AJ17
SATA_RX4P
AH17
SATA_TX5P
AJ18
SATA_TX5N
AH18
SATA_RX5N
AH19
SATA_RX5P
AJ19
SPI_DI/GPIO164
J5
SPI_DO/GPIO163
E2
SPI_CLK/GPIO162
K4
SPI_CS1#/GPIO165
K9
ROM_RST#/GPIO161
G2
NC2 Y2
NC1 G27
SATA_CALRP
AB14
R157 150K_0402_5%
1 2
D10
CH751H-40PT_SOD323-2
2 1
R156 10K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VDDAN_1.1V_USB
VDDPL_3.3V
VDDPL_3.3V_USB
VDDPL_1.1V
VDDCR_1.1V_USB
VDDXL_3.3V
VDDPL_3.3V
VDDPL_3.3V_SATA
VDDPL_3.3V_PCIE
VDDPL_1.1V
VDDPL_3.3V_USB
+3VS
VDDPL_3.3V_PCIE
+PCIE_VDDR
VDDPL_3.3V_SATA
+AVDD_USB+3VALW
+1.1VALW
+1.1VS+1.1V_CKVDD
+3VALW
+1.1VALW
+3VALW
+1.1VALW
+3VALW
+3VS
+3VS
+3VALW
+1.1VS
+1.1VS
+1.1VS_SATA
+1.1V_USB
+1.1VS
+1.1VS_VDDC
+3VS
+1.1VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
23 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
SB820 Power/GND
TBDmA
131mA
43mA
600mA
93mA
567mA
658mA
TBDmA
510mA
400mA
32mA
113mA
197mA
47mA
C298 near U7.M8
L
62mA 17mA
C274 0.1U_0402_16V4Z
1 2
C298
2.2U_0603_6.3V4Z
1
2
C266 1U_0402_6.3V4Z@
1 2
C281 0.1U_0402_16V4Z
1 2
C284 10U_0805_10V6K
1 2
L25
FBMA-L11-201209-221LMA30T_0805
1 2
C292
10U_0603_6.3V6M
1
2
C2671U_0402_6.3V4Z 12
C299
2.2U_0603_6.3V4Z
1
2
C279 1U_0402_6.3V4Z
1 2
C2962.2U_0603_6.3V4Z
1
2
C289 0.1U_0402_16V4Z
@
1 2
C2681U_0402_6.3V4Z
1
2
L29
FBMA-L11-160808-221LMT_0603
1 2
Part 3 of 5
SB800
POWER
PCI/GPIO I/O
CORE S03.3V_S5 I/O
CORE S5
PCI EXPRESSSERIAL ATA
USB I/O
PLL CLKGEN I/O
FLASH I/O
GBE LAN
U7C
SB820M_FCBGA605 SB820MR1@
VDDIO_33_PCIGP_2
V6
VDDIO_33_PCIGP_6
AA2
VDDIO_33_PCIGP_3
Y19
VDDIO_33_PCIGP_11
AF7
VDDIO_33_PCIGP_1
AH1
VDDIO_33_PCIGP_4
AE5
VDDIO_33_PCIGP_5
AC21
VDDIO_33_PCIGP_12
AA19
VDDIO_33_PCIGP_10
AA9
VDDIO_33_PCIGP_7
AB4
VDDIO_33_PCIGP_8
AC8
VDDIO_33_PCIGP_9
AA7
VDDIO_33_S_1 A21
VDDIO_33_S_2 D21
VDDIO_33_S_3 B21
VDDIO_33_S_4 K10
VDDIO_33_S_5 L10
VDDCR_11_S_2 G26
VDDCR_11_S_1 F26
VDDCR_11_USB_S_1 A11
VDDCR_11_USB_S_2 B11
VDDPL_33_SYS M21
VDDPL_11_SYS_S L22
VDDAN_33_USB_S_1
A18
VDDAN_33_USB_S_4
B18
VDDAN_33_USB_S_2
A19
VDDAN_33_USB_S_5
B19
VDDPL_33_USB_S F19
VDDAN_33_USB_S_9
D18 VDDAN_33_USB_S_8
C20
VDDAN_33_USB_S_3
A20
VDDAN_33_USB_S_11
D20 VDDAN_33_USB_S_10
D19
VDDAN_11_PCIE_4
V27 VDDAN_11_PCIE_3
V26
VDDAN_11_PCIE_7
W22
VDDAN_11_PCIE_2
V22
VDDAN_11_PCIE_5
V28
VDDAN_11_PCIE_1
U26
VDDAN_11_PCIE_6
V29
VDDAN_11_SATA_1
AJ20
VDDAN_11_SATA_4
AF18
VDDAN_11_SATA_2
AH20
VDDAN_11_SATA_3
AG19
VDDAN_11_SATA_5
AE18
VDDAN_11_SATA_6
AD18
VDDAN_11_SATA_7
AE16
VDDCR_11_1 N13
VDDCR_11_2 R15
VDDCR_11_3 N17
VDDCR_11_4 U13
VDDCR_11_5 U17
VDDCR_11_6 V12
VDDCR_11_7 V18
VDDCR_11_9 W18
VDDCR_11_8 W12
VDDAN_33_USB_S_6
B20
VDDAN_33_USB_S_7
C18
VDDIO_18_FC_2
AE25
VDDIO_18_FC_4
AC22
VDDIO_18_FC_1
AF22
VDDAN_11_CLK_2 K29
VDDAN_11_CLK_1 K28
VDDAN_11_CLK_4 K26
VDDAN_11_CLK_3 J28
VDDCR_11_GBE_S_2 L9
VDDIO_33_S_6 J9
VDDAN_11_PCIE_8
W26
VDDPL_33_PCIE
AE28
VDDPL_33_SATA
AD14
VDDAN_33_HWM_S D6
VDDAN_11_CLK_5 J21
VDDAN_11_CLK_7 K21
VDDAN_11_USB_S_1
C11
VDDAN_11_USB_S_2
D11
VDDCR_11_GBE_S_1 L7
VDDIO_GBE_S_1 M6
VDDIO_33_GBE_S M10
VDDIO_GBE_S_2 P8
VDDIO_33_S_7 T6
VDDIO_33_S_8 T8
VDDXL_33_S L20
VDDRF_GBE_S V1
VDDIO_AZ_S M8
VDDIO_18_FC_3
AF24
VDDAN_11_CLK_6 J20
VDDAN_11_CLK_8 J22
VDDAN_33_USB_S_12
E19
R166 0_0402_5%
1 2
L32
FBMA-L11-160808-221LMT_0603
1 2
C257 1U_0402_6.3V4Z@
1 2
C272 1U_0402_6.3V4Z
1 2
C2950.1U_0402_16V4Z
1
2
C287 1U_0402_6.3V4Z
1 2
C24910U_0805_10V6K
1 2
C2630.1U_0402_10V6K
1
2
C285 10U_0805_10V6K
1 2
C3012.2U
1
2
C300
2.2U_0603_6.3V4Z
1
2
L33
FBMA-L11-160808-221LMT_0603
1 2
C270 1U_0402_6.3V4Z @
1 2
C256 1U_0402_6.3V4Z@
1 2
C288 1U_0402_6.3V4Z
1 2
C2621U_0402_6.3V4Z
1
2
C2551U_0402_6.3V4Z 12
L28
0_0805_5%
12
L34
FBMA-L11-160808-221LMT_0603
1 2
C2782.2U_0603_6.3V4Z
1 2
C304
2.2U_0603_6.3V4Z
1
2
C293
0.1U_0402_10V6K
1
2
L26
0_0805_5%
12
C269 22U_0805_6.3V6M
12
C248 22U_0805_6.3V6M
12
L27
0_0805_5%
12
C2831U_0402_6.3V4Z
12
C2600.1U_0402_16V4Z 12
C303
2.2U_0603_6.3V4Z
1
2
C294
0.1U_0402_10V6K
1
2
C261 0.1U_0402_16V4Z
1 2
C3020.1U
1
2
C280 1U_0402_6.3V4Z
1 2
C2861U_0402_6.3V4Z
12
C2580.1U_0402_16V4Z 12
L30
0_0805_5%
12
L35
FBMA-L11-160808-221LMT_0603
1 2
L31
FBMA-L11-160808-221LMT_0603
1 2
C275 0.1U_0402_16V4Z
1 2
C259 0.1U_0402_16V4Z
1 2
SB800
GROUND
Part 5 of 5
U7E
SB820M_FCBGA605 SB820MR1@
VSS_4 E5
VSS_2 A28
VSS_21 J7
VSS_10 R13
VSS_11 R17
VSS_1 AJ2
VSS_17 V19
VSS_8 F24
VSS_9 N15
VSS_46 H7
VSS_13 P10
VSS_14 V11
VSS_15 U15
VSS_16 M18
VSS_18 M11
VSS_19 L12
VSS_20 L18
VSS_22 P3
VSS_23 V4
VSS_26 AB7
VSS_27 AC9
VSS_28 V8
VSS_29 W9
VSS_32 B29
VSS_33 U4
VSS_34 Y18
VSS_36 Y12
VSS_37 Y11
VSS_3 A2
VSS_35 Y10
VSS_30 W10
VSSIO_SATA_15
AH16
VSSIO_USB_25
K14
VSSIO_SATA_5
AE12
VSSIO_SATA_11
AG8
VSSIO_USB_26
K16
VSS_31 AJ28
VSS_24 AD6
VSSIO_SATA_14
AH13
VSSIO_SATA_2
Y16
VSSIO_SATA_3
AB16
VSSIO_SATA_1
Y14
VSSIO_SATA_17
AJ11
VSSIO_SATA_4
AC14
VSSIO_SATA_12
AH7
VSSIO_SATA_6
AE14
VSSIO_SATA_10
AF16
VSSIO_SATA_7
AF9
VSSIO_SATA_8
AF11
VSSIO_SATA_16
AJ7
VSSIO_USB_27
K18
VSSIO_SATA_13
AH11
VSSIO_USB_5
D10
VSSIO_USB_8
D17
VSSIO_USB_4
B9 VSSIO_USB_3
K11
VSSIO_USB_6
D12
VSSIO_USB_7
D14
VSSIO_USB_2
B10
VSSIO_USB_21
H18
VSSIO_USB_10
F9
VSSIO_USB_20
H16
VSSIO_USB_22
J11
VSSIO_USB_11
F12
VSSIO_USB_12
F14
VSSIO_USB_23
J19
VSSIO_USB_16
F18 VSSIO_USB_15
G11
VSSIO_USB_19
H14
VSSIO_USB_1
A9
VSSIO_USB_24
K12
VSS_12 T10
VSSIO_USB_18
H12
VSS_7 E6
VSS_25 AD4
VSS_6 E25
VSSIO_USB_13
F16
VSSIO_USB_9
E9
VSSPL_SYS M20
VSSIO_PCIECLK_3
M22
VSSIO_PCIECLK_14 H23
VSSIO_PCIECLK_13
J23
VSSIO_PCIECLK_18 AB23
VSSIO_PCIECLK_6
P22
VSSIO_PCIECLK_8
P26 VSSIO_PCIECLK_7
P24
VSSIO_PCIECLK_17 AA23
VSSIO_PCIECLK_16 AA21
VSSIO_PCIECLK_15 H26
VSS_50 N4
VSSIO_PCIECLK_21 AC26
VSSIO_PCIECLK_19 AD23
VSSIO_PCIECLK_20 AA26
VSSIO_PCIECLK_2
P20 VSSIO_PCIECLK_1
P21
VSSIO_PCIECLK_4
M24
VSS_5 D23
VSSIO_PCIECLK_5
M26
VSS_49 P6
VSS_44 M12
VSS_45 AF25
VSS_42 G8
VSS_48 V10
VSS_41 J4
VSS_43 G9
VSS_38 AA11
VSS_39 AA12
VSS_40 G4
VSSIO_SATA_9
AF13
EFUSE
Y4
VSSAN_HWM
D8
VSSIO_PCIECLK_25 AE26
VSSIO_USB_28
H19
VSSIO_PCIECLK_22 Y20
VSSIO_PCIECLK_23 W21
VSSIO_PCIECLK_24 W20
VSSIO_PCIECLK_9
T20
VSSIO_PCIECLK_10
T22
VSSIO_PCIECLK_11
T24
VSSIO_PCIECLK_12
V20
VSS_51 L4
VSS_52 L8
VSSXL
M19
VSS_47 AH29
VSSIO_PCIECLK_27 K20
VSSIO_PCIECLK_26 L21
VSSIO_USB_14
C9
VSSIO_USB_17
D9
VSSIO_SATA_19
AJ16 VSSIO_SATA_18
AJ13
C277 22U_0805_6.3V6M
12
L36
FBMA-L11-160808-221LMT_0603
1 2
C25422U_0805_6.3V6M
1
2
C273 1U_0402_6.3V4Z
1 2
C282 0.1U_0402_16V4Z
1 2
C252 0.1U_0402_16V4Z
1 2
C2530.1U_0402_10V6K
1
2
C2972.2U
1
2
C2762.2U_0603_6.3V4Z
1 2
R165 0_0805_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI_CLK220
PCI_CLK320
PCI_CLK420
CLK_PCI_EC20,31
LPC_CLK120,32
GPIO20021
GPIO19921
HDA_SDOUT21
PCI_CLK120
PCI_AD2820
PCI_AD2720
PCI_AD2620
PCI_AD2520
PCI_AD2420
PCI_AD2320
PCI_AD2920
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW+3VALW
+3VS+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
SB820 STRAPS
Custom
24 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
WATCHDOG
TIMER
DISABLE
DEFAULT
USE
DEBUG
STRAP
Inter CLK
Gen Mode
IGNORE
DEBUG
STRAP
DEFAULT
Check Internal PU/PD
EC
ENABLE
EC
DISABLE
CLOCKGEN
DISABLE
Enable
Inter CLK
Gen Mode
Disable
check default
Check AD29,AD28 strap function
PCI_CLK4
DISABLE PCI
MEM BOOT
DEFAULT
AZ_SDOUT
ENABLE PCI
MEM BOOT
LOW POWER
MODE
DEBUG STRAPS
PCI_AD25 PCI_AD24
USE EEPROM
PCIE STRAPS
USE DEFAULT
PCIE STRAPS
DEFAULT
DISABLE ILA
AUTORUN
DEFAULT
USE FC PLLUSE PCI
PLL
DEFAULT
BYPASS
FC PLL
PULL
HIGH
DEFAULT
BYPASS
PCI PLL
PCI_AD27 PCI_AD26
PULL
LOW
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD23
DEFAULT
GPIO200
(EC_PWM3)
ENABLE ILA
AUTORUN
PULL
LOW
PULL
HIGH
REQUIRED STRAPS
CLOCKGEN
ENABLE
DEFAULT
LCP_CLK1LPC_CLK0
DEFAULT
GPIO199
(EC_PWM2)
ALLOW PCIE
GEN2
DEFAULT
Performance
MODE
PCI_CLK1
DEFAULT
FORCE PCIE
GEN1
PCI_CLK2 PCI_CLK3
L,H = LPC ROM
H,H = Reserved
L,L = FWH ROM
H,L = SPI ROM(Default)
WATCHDOG
TIMER
ENABLE
Option 1:SPI Flash (2MB*1) for EC
Option 2:SPI Flash (256KB*1) for EC
SPI Flash (2MB*1) for SB (set up strap pin)
L,H = LPC ROM(Default)
H,L = SPI ROM
12/12 Fine tune SB820 int clock gen strap pin 12/12 Add cC706 for EMI request
12/31 SMT memo control
12/31 SMT memo control
R244
10K_0402_5%
12
R185
2.2K_0402_5%
@
12
R209
10K_0402_5%
12
R200
10K_0402_5%
@
12
R190
2.2K_0402_5%
@
12
R189
2.2K_0402_5%
@
12
R179
10K_0402_5%
@
12
R181
10K_0402_5%
12
R167
10K_0402_5%
@
12
R191
2.2K_0402_5%
@
12
R186
2.2K_0402_5%
12
R170
10K_0402_5%
@
12
R188
2.2K_0402_5%
@
12
R177
10K_0402_5%
12
C706
22P_0402_50V8J
1
2
R349
10K_0402_5%
12
R176
2.2K_0402_5%
@
12
R175
2.2K_0402_5%
12
R221
10K_0402_5%
@
12
R180
10K_0402_5%
12
R192
2.2K_0402_5%
@
12
R169
10K_0402_5%
12
R171
10K_0402_5%
@
12
R187
10K_0402_5%
12
R168
10K_0402_5%
@
12
R178
10K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB20_P2_R
USB20_N2_R_S
USB20_N2_R_S
USB20_P2_R_S
USB20_P2_R_S USB20_N2_R
USB20_P2_R_S
USB20_N2_R_S
SATA_C_RX3+
SATA_C_RX3-
SATA_C_TX3-
SATA_C_TX3+
USB20_P2_R
USB20_N2_R
USB20_P2_S_O
USB20_N2_S_OUSB20_P2_R_U
USB20_N2_R_U
USB20_P2_S_O
USB20_N2_S_O
USB20_P2_R_U
USB20_N2_R_U
USB20_P2
USB20_N2
USB_CHG_EN#
USB_CHG_EN#
SATA_C_TX0+
SATA_C_RX0+
SATA_C_RX0-
SATA_C_TX0-
SATA_TX3+22
SATA_TX3-22
SATA_RX3+22
SATA_RX3-22
SLP_CHG# 31
SLP_CHG_M322,31
SLP_CHG_M422,31
USB20_P221
USB20_N221
USB_CHG_EN#31 USB_OC#2 21,31
SATA_TX0- 22
SATA_TX0+ 22
SATA_RX0- 22
SATA_RX0+ 22
+5VS
+USB_VCCB
+USB_VCCB
+USB_VCCB
+3VALW
+USB_VCCB
+USB_VCCB
+USB_VCCB
+3VALW
+5V_ALW
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
25 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
SATA HDD/ODD
1.2A
E-SATA/USB
2A
W=60mils
Active Low
Mode 3
Mode 4
SLP_CHG_M3
HIGH
SLP_CHG_M4
LOW
LOW HIGH
FUNCTIONSLP_CHG
LOW
HIGH
D=1D
D=2D
SATA FFC conn
Pin=12pin, pitch=1.0
SATA transfer board
Place closely JHDD SATA CONN
L
1/19 Change net name SLP_CHG-->SLP_CHG#
1/20 update JSATA1 footprint
2/2 Update JHDD1 10pin-->12pin
1/25 U9 pin1 +5VALW-->+5V_ALW for USB charger
03/11 Del JHDD2
C306
0.1U_0402_16V4Z
1
2
R195
43K_0402_1%
12
U10
TS3USB221RSER_QFN10_2x1P5
D+ 8
2D+
3
GND
5OE# 6
S9
1D-
2
VCC 10
1D+
1
D- 7
2D-
4
U9
RT9715BGS_SO8
FLG 5
VIN
3VOUT 6
GND
1
EN
4
VOUT 7
VIN
2VOUT 8
U11
SN74CBT3125PWRG4_TSSOP14
1OE#
1
1A
21B 3
2OE#
4
2A
52B 6
GND 7
3B 8
3A
9
3OE#
10
4B 11
4A
12
4OE#
13
VCC
14
R199 0_0402_5%
@
1 2
C322
0.1U_0402_16V4Z
1
2
R198 100_0402_5%
1 2
C310 0.01U_0402_25V7K
1 2
C315
1000P_0402_50V7K
1
2
+
C522
150U_B2_6.3VM_R45M
1
2
C307
0.1U_0402_16V4Z
1
2
C321 0.01U_0402_25V7K
12
R196
51K_0402_1%
12
D11
CM1293A-02SR SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
C309 0.01U_0402_25V7K
1 2
C318 0.01U_0402_25V7K
1 2
USB
ESATA
JSATA1
TAIWI_EU114-117CRL-TW_11P-T
CONN@
VBUS
1
D-
2
D+
3
GND
4
GND
5
A+
6
A-
7
GND
8
B-
9
B+
10
GND
11
GND
12
GND
13
GND
14
GND
15
R197
51K_0402_1%
12
R201 0_0402_5%
@
1 2
C316 0.1U_0402_16V4Z
1 2
R858
10K_0402_5%
12
R194
75K_0402_1%
12
C320 0.01U_0402_25V7K
12
JHDD1
ACES_85201-1205N
CONN@
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
GND
13
GND
14
C314
0.1U_0402_16V4Z
1
2
C312 0.01U_0402_25V7K
1 2
L37
WCM-2012-900T_0805
1
122
33
4
4
C319 0.01U_0402_25V7K
1 2
C308
0.1U_0402_16V4Z
1
2
C317
4.7U_0805_10V4Z
@
1
2
C311 0.01U_0402_25V7K
1 2
C305
10U_0805_10V4Z
1
2
UIM_DATA
UIM_RESET
UIM_CLK
+UIM_PWR
UIM_VPP
COMMON UIM_VPP
LED_WIMAX#
PLT_RST#
LED_WIMAX#
PLT_RST#
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
COMMON
SMB_CK_DAT1
SMB_CK_CLK1
SMB_CK_DAT1
SMB_CK_CLK1
WL_OFF#
LED_WIMAX#
BT_CTRL
WLAN_PWR_EN#_R
BT_CTRLSUSP#
CLK_PCIE_MCARD220
CLK_PCIE_MCARD2#20
PCIE_PTX_C_IRX_P211
PCIE_PTX_C_IRX_N211
PCIE_ITX_C_PRX_N211
PCIE_ITX_C_PRX_P211
E51_TXD31
E51_RXD31
USB20_P8 21
USB20_N8 21
SMB_CK_DAT1 21
SMB_CK_CLK1 21
USB20_P5 21
USB20_N5 21
3G_OFF# 20
CLKREQ_MCARD2#21
LED_WIMAX# 33
PLT_RST# 12,15,20,27,30,31,32
WL_OFF# 31
WWAN_PW R_EN#22
WLAN_PWR_EN#22
BT_PWR#20,29
SUSP#28,31,34,37,41
+1.5V_WLAN
+UIM_PWR
+UIM_PWR
+UIM_PWR
+3V_WWAN
+3VS
+3VS
+3V_WWAN
+3V_WWAN
+3V_WWAN
+3V_WLAN
+3V_WLAN
+3V_WLAN
+3V_WLAN
+1.5V_WLAN
+1.5V_WLAN
+3V_WLAN
+1.5VS
+3VS +3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
PCIe-WLAN/HDDVD/NAND/NEW
26 45
Tuesday, March 23, 2010
2008/09/05 2009/09/05
Compal Electronics, Inc.
PCIe Mini Card-3G/WWAN (Slot 2)
PCIe Mini Card-WLAN(Slot 1)
Enable Disable
LO HI
HI LO
BT
on module
BT
on module
**If +3V_WLAN is +3VS, please
remove D17.
WLAN&BT Combo module circuits
BT_CRTL
BT_PWR#
01/19 Update net name BT_CTRL-->BT_PWR#
01/21 Add D17 and Q38 for BT control
03/19 del LPC frame and LPC_AD1-LPC_AD3 trace
CM20
1000P_0402_50V7K
1
2
RM10
0_0805_5%
12
CM13
4.7U_0805_10V4Z
1
2
CM17
0.1U_0402_16V7K @
1
2
G
D
S
QM2
AO3413_SOT23
@
2
1 3
CM11
0.01U_0402_25V7K
1
2
D17
CH751H-40PT_SOD323-2
@
21
G
D
S
QM1
AO3413_SOT23
@
2
1 3
CM19
0.1U_0402_16V7K
@
1
2
RM1
4.7K_0402_5%
@
12
RM4
100K_0402_5%
12
RM8
47K_0402_5%
@
1 2
RM6
47K_0402_5%
@
1 2
RM3100K_0402_5%
12
CM6
4.7U_0805_10V4Z
1
2
CM16
4.7U_0805_10V4Z
1
2
DM3
DAN217_SC59
@
2
3
1
CM10
22P_0402_50V8J
@
1
2
R205 0_0402_5%
1 2
CM15
0.1U_0402_16V4Z
1
2
G
D
S
QM3
AO3413_SOT23
@
2
1 3
CM14
0.01U_0402_25V7K
1
2
DM4
DAN217_SC59
@
2
3
1
RM9
0_0805_5%
12
R206 0_0402_5%
1 2
CM4
0.01U_0402_25V7K
1
2
DM2
DAN217_SC59
@
2
3
1
J3G1
MOLEX_47273-0001~D
CONN@
VCC
1
RST
2
CLK
3
GND 4
VPP 5
I/O 6
NC 8
NC
7
CM8
10P_0402_50V8J
1
2
JWWAN1
P-TWO_A54402-A0G16-N_52P
CONN@
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
1
122
G1
53
G2
54 G3 55
G4 56
CM7
0.1U_0402_16V4Z
1
2
CM12
0.1U_0402_16V4Z
1
2
CM9
10P_0402_50V8J
1
2
DM1
RLZ20A_LL34
12
CM18
0.1U_0402_16V7K
@
1
2
RM11
0_0603_5%
12
CM5
0.1U_0402_16V4Z
1
2
RM7
100K_0402_5%
@
1 2
G
D
S
Q38 2N7002_SOT23-3
2
13
RM5
100K_0402_5%
@
1 2
JWLAN1
BELLW_80052-1021_52P
CONN@
1
1
22
3
3
44
5
5
66
7
7
88
9
9
10 10
11
11
12 12
14 14
16 16
13
13
15
15
GND
53
GND
54
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
R203 0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ISOLATEB
+LAN_REGOUT
+LAN_REGOUT
ISOLATEB
LAN_X2LAN_X1
PCIE_PRX_LANTX_P3
PCIE_PRX_LANTX_N3
LAN_MDI1+
LAN_MDI1-
LAN_MDI0-
LAN_MDI0+
ENSWREG
ENSWREG
+3V_AVDDXTAL
LAN_X2
LAN_X1
EC_SWI#
+3V_AVDDXTAL
RJ45_GND
LAN_MDI0-
LAN_MDI0+
LAN_MDI1+
LAN_MDI1-
RJ45_MIDI0-
RJ45_MIDI0+
RJ45_MIDI1+
RJ45_MIDI1-
PCIE_ITX_C_PRX_N311
PCIE_ITX_C_PRX_P311
PCIE_PTX_C_IRX_P311
PCIE_PTX_C_IRX_N311
CLK_PCIE_LAN#20
CLK_PCIE_LAN20
EC_SWI#21
PLT_RST#12,15,20,26,30,31,32
CLKREQ_LAN21
WOL_EN#31
RJ45_MIDI1+ 17
RJ45_MIDI1- 17
RJ45_MIDI0+ 17
RJ45_MIDI0- 17
RJ45_GND 17
+LAN_EVDD10
+3VS
+3V_LAN
+LAN_VDD10
+LAN_EVDD10
+LAN_VDD10
+LAN_VDD10
+3V_LAN
+3V_LAN
+LAN_VDDREG
+LAN_VDD10
+3V_LAN
+LAN_VDD10
+LAN_VDDREG
+LAN_VDD10
+3V_LAN
+3V_LAN
+3V_LAN
+3VALW
+3VALW
+3V_LAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Compal Electronics, Inc.
LA-6032P
1.0
RTL8103EL/RTL8111DL
27 45
Tuesday, March 23, 2010
2008/10/06 2009/10/06
Close to Pin 21
Close to Pin 3,6,9,13,29,41,45
Close to Pin 27,39,12,47,48
Layout Note: LL1 must be
within 200mil to Pin36
CL8,CL9 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
Reserved For 1.05V Crystal
Can change to 2.2uH&4.7uF
+3VALW TO +3V_LAN
Vgs=-4.5V,Id=3A,Rds<97mohm
3/10 Change CL13 0805-->0603
LL20_0603_5%
12
CL50.1U_0402_16V4Z
1 2
CL18
1U_0402_6.3V4Z
1
2
RL27
75_0402_1%
1 2
CL28
4.7U_0603_6.3V6K
1
2
RL23
0_0402_5%
@
G
D
S
QL1
AO3413_SOT23
2
1 3
CL200.1U_0402_16V4Z
1 2
RL1 10K_0402_5%
12
CL190.1U_0402_16V4Z
1 2
CL220.1U_0402_16V4Z
1 2
CL32 1000P_0402_50V7K
1 2
CL11 0.1U_0402_16V4Z@
12
PJ20
JUMP_43X39
@
11
2
2
CL2 0.1U_0402_16V7K
1 2
RL2 10K_0402_5%
12
CL15
4.7U_0805_10V4Z
@
1
2
CL70.1U_0402_16V4Z
1 2
RL19 0_0402_5%
RL16 47K_0402_5%
1 2
CL27
27P_0402_50V8J
1
2
RL21 1K_0402_5%@1 2
UL1
RTL8105E-VB-GR_QFN48_6X6
PERSTB
25
HSOP
22
HSON
23
HSIP
17
HSIN
18
REFCLK_P
19
REFCLK_N
20 NC/MDIP2 7
NC/MDIN2 8
NC/MDIP3 10
NC/MDIN3 11
LED3/EEDO 31
LED1/EESK 37
EECS/SCL 30
LED0 40
MDIN1 5
MDIP1 4
MDIN0 2
MDIP0 1
RSET
46
LANWAKEB
28
ISOLATEB
26
CKXTAL1
43
CKXTAL2
44
AVDD10 3
EVDD10 21
DVDD10 29
DVDD10 41
VDDREG
34
ENSWREG
33
DVDD33 27
DVDD33 39
AVDD33 12
DVDD10 13
AVDD33 42
CLKREQB
16
EEDI/SDA 32
AVDD33 47
AVDD33 48
AVDD10 6
AVDD10 9
AVDD10 45
NC/SMBCLK
14
NC/SMBDATA
15
GPO/SMBALERT
38
GND
24
PGND
49 REGOUT 36
VDDREG
35
RL20 1K_0402_5%@1 2
RL7
15K_0402_5%
UL2
NS681680
TD+
1
TD-
2
CT
3
CT
6
RD+
7
RD-
8RX- 9
RX+ 10
CT 11
CT 14
TX- 15
TX+ 16
NC
4
NC
5NC 13
NC 12
CL8 1U_0402_6.3V4Z
1
2
CL210.1U_0402_16V4Z
1 2
CL17
0.1U_0402_16V4Z
1
2
CL40.1U_0402_16V4Z
1 2
CL100.1U_0402_16V4Z
1 2
CL1 0.1U_0402_16V7K
1 2
CL31 1000P_0402_50V7K
1 2
RL8
0_0402_5%
CL14
0.01U_0402_25V7K
1
2
LL1
2.2UH +-5% NLC252018T
1 2
CL60.1U_0402_16V4Z
1 2
CL29
0.1U_0402_16V4Z
1
2
YL1
25MHZ_20PF_7A25000012
12
RL6
1K_0402_1%
12
RL26
75_0402_1%
1 2
CL13
4.7U_0603_6.3V6K
1
2
RL25
100K_0402_5%
1 2
RL4
0_0402_5%
CL26
27P_0402_50V8J
1
2
CL9
0.1U_0402_16V4Z
1
2
LL30_0603_5%
12
RL22 1K_0402_5%
1 2
CL30 0.01U_0402_16V7K
12
RL9
0_0402_5%@
CL12
0.1U_0402_16V7K
1
2
RL5 2.49K_0402_1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
AC_VREF
AZ_RST_HD#
MONO_IN
AC_JDREF
MONO_IN
+PVDD2
SENSE_A
SENSE_A
AZ_SDIN0_HD_R
+PVDD1
MIC1_R_L
MIC1_R_R
INT_MIC_CLK_R
AZ_RST_HD#
INT_MIC_CLK_R
MIC1_R_R
MIC1_R_LMIC1_L
MIC1_R
EC_MUTE#
AZ_RST_HD#21
HP_L 29
HP_R 29
SPKL+ 29
EC_BEEP31
PCH_SPKR21
SPKR+ 29
SPKL- 29
SPKR- 29
AZ_SYNC_HD 21
AZ_BITCLK_HD 21
AZ_SDOUT_HD 21
AZ_SDIN0_HD 21
MIC_SENSE29
NBA_PLUG29
MIC1_R29
MIC1_L29
INT_MIC_DATA18
INT_MIC_CLK18
SUSP#26,31,34,37,41
EC_MUTE#31
+3VS_DVDD
+5VS
+5VS
+5VS
+MIC1_VREFO_R
+MIC1_VREFO_L
+AVDD
+3VS
+3VS
+5VALW +AVDD
+MIC1_VREFO_L
+MIC1_VREFO_R
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
28 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
HD Audio ALC272 Codec
Beep sound
place close to chip
place close to chip
place close to chip
PCI Beep
EC Beep
AGND
place close to chip
DGND
Ext. MIC
Function
Headphone out
10K
20K
39.2K
SENSE A
5.1K
10K
20K
39.2K
PORT-H (PIN 20)
Sense Pin Impedance
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)SENSE B
PORT-D (PIN 48)
PORT-C (PIN 23, 24)
PORT-B (PIN 21, 22)
PORT-I (PIN 32, 33)
Codec Signals
place close to chip
Ext. HP
Digital Mic
Ext. Mic
12/18 RA26 0ohm-->Bead for EMI request
300mA
(4.75V(4.56~4.94V))
W=40Mil
1/21 UA2 pin5 +PVDD1--->+AVDD
3/17 Add RA45
03/12 CA15 SMT-->@ for Audio noise
03/17 DGND-->AGND for Audio noise
03/17 DGND-->AGND forAudio noise
3/17 Del R861 R910
CA60
10U_0805_10V4Z
@
1
2
CA61
0.1U_0402_16V4Z
1
2
CA8
10U_0805_10V4Z
1
2
RA28
0_0402_5%
@
1 2
RA3
0_0603_5%
12
RA1
FBMH1608HM601-T_0603~D
12
CA48 0.1U_0603_50V7K
1 2
CA14 2.2U_0603_6.3V4Z
1 2
CA13
0.1U_0402_16V4Z
1 2
CA67
0.1U_0402_16V4Z
@1 2
CA12 100P_0402_50V8J
1 2
RA9 20K_0402_1%
12
CA58
10U_0805_10V4Z
@
1
2
CA6
0.1U_0402_16V4Z
1
2
RA22 2.2K_0402_5%
1 2
RA7
47K_0402_5%
1 2
CA49 0.1U_0603_50V7K
1 2
CA17
0.1U_0402_16V4Z
1
2
CA62
0.1U_0402_16V7K
@
1
2
CA16
10U_0805_10V4Z
@
1
2
CA15
2.2U_0603_6.3V4Z
1 2
CA43
10U_0805_10V4Z
1
2
CA2
10U_0805_10V4Z
1
2
CA18
0.1U_0402_16V4Z
1
2
CA700.1U_0402_16V4Z
@
1
2
CA59
0.1U_0402_16V4Z
@
1
2
RA2
0_0603_5%
12
CA63
22P_0402_50V8J
1 2
RA45
4.7K_0402_5%
12
CA224.7U_0805_10V4Z
12
RA24 1K_0402_5%
1 2
CA1
0.1U_0402_16V4Z
1
2
RA11
0_0603_5%
@
12
RA27
4.7K_0402_5%
@
12
RA252.2K_0402_5%
1 2
RA21 39.2K_0402_1%
CA44
0.1U_0402_16V4Z
1
2
CA56
10U_0805_10V4Z
1
2
RA26
FBMA-L10-160808-301LMT 0603
1 2
JA1
JUMP_43X39
@
1
122
RA12
10K_0402_5%
12
CA4
10U_0805_10V4Z
1
2
UA2
G9191-475T1U_SOT23-5
@
IN
1
GND
2
SHDN
3
OUT 5
BYP 4
RA6 33_0402_5%
12
RA10 20K_0402_1%
12
CA57
0.1U_0402_16V4Z
1
2
CA50 0.1U_0603_50V7K
1 2
RA23 1K_0402_5%
1 2
CA5
0.1U_0402_16V4Z
1
2
RA8
47K_0402_5%
1 2
UA1
ALC259-VB5-GR_QFN48_7X7
AVDD1 25
AVDD2 38
AVSS1 26
AVSS2 37
DVDD 1
DVDD_IO 9
DVSS1
7
PVDD1 39
PVDD2 46
PVSS1
42 PVSS2
43 CPVEE 34
JDREF 19
VREF 27
LDO_CAP 28
MIC1_VREFO_R 30
MIC2_VREFO 29
MIC1_VREFO_L
31
CBN
35
CBP
36
SENSE A
13
SENSE B
18
SPK_OUT_L+ 40
SPK_OUT_L- 41
SPK_OUT_R+ 45
SPK_OUT_R- 44
HP_OUT_L 32
HP_OUT_R 33
PCBEEP
12
LINE1_L
23
LINE1_R
24
LINE2_L
14
LINE2_R
15
MIC1_L
21
MIC1_R
22
MIC2_L
16
MIC2_R
17
MONO_OUT 20
RESET#
11
GPIO0/DMIC_DATA
2
GPIO1/DMIC_CLK
3
PD#
4
SYNC 10
BCLK 6
SDATA_OUT 5
SDATA_IN 8
EAPD 47
SPDIFO 48
DVSS2
49
CA68
2.2U_0805_16V4Z
@
1
2
CA214.7U_0805_10V4Z
12
CA23 10U_0805_10V4Z
1 2
CA3
10U_0805_10V4Z
1
2
CA47 0.1U_0603_50V7K
1 2
RA18
FBMH1608HM601-T_0603~D
1 2
CA7
0.1U_0402_16V4Z
1
2
CA69
0.1U_0402_16V4Z
@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPKL-
SPKL+
SPKR-
SPKR+
SPK_R1
SPK_R2
SPK_L1
SPK_L2
SPK_L2
SPK_R1
SPK_L1
SPK_R2MIC1_L
MIC1_R
HP_L
HP_R
USB_EN#
MIC1_L
MIC1_R
HP_R
HP_L
USB20_P1
USB20_N1
USB20_P0
USB20_N0
SPKL+28
SPKL-28
SPKR+28
SPKR-28
USB_EN#31 USB_OC#0 21,31
BT_PWR#20,26
USB20_N621
USB20_P621
BT_RST#20
BT_DET#20
NBA_PLUG28
MIC_SENSE28
MIC1_R28
MIC1_L28
HP_R28
HP_L28
USB20_P121
USB20_N121
USB20_P021
USB20_N021
+USB_VCCA
+5VALW
+BT_VCC
+3VS
+3VS
+BT_VCC
+5VS +5VS +5VS +5VS +5VS+5VS
+3VS
+3VALW
+5VS
+5VALW
+USB_VCCA
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
29 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
AMP/Audio Jack/HP/SPEAKER/VR
USB+Audio FFC conn
Pin=20pin, pitch=0.5
Speaker Connector
placement near Audio Codec
CPU
Screw Hole
(MAX=200mA)
BlueTooth Interface
1/27 Add R907 for USB_EN# PH
1/27 Update P/N
02/04 Update JP5 pin define
LA3
FBMA-L11-160808-800LMT_0603
1 2
FD3
@
1
R212
47K_0402_5%
<>
1 2
H4
H_4P0
@
1
LA2
FBMA-L11-160808-800LMT_0603
1 2
H19
H_5P0N
@
1
R214 0_0402_5%
1 2
JP5
ACES_87151-2005N
CONN@
4
4
7
7
10
10
13
13
1
1
6
6
2
2
3
3
5
5
8
8
9
9
11
11
12
12
14
14
15
15
16
16
17
17
18
18
19
19
20
20
GND
21
GND
22
CA19
10U_0805_10V4Z@
1
2
JBT1
ACES_87213-0600G
CONN@
1
1
2
2
3
3
4
4
5
5
6
6G1 7
G2 8
FD4
@
1
H17
H_2P6X2P1N
@
1
H18
H_2P3
@
1
C325
0.1U_0402_16V4Z
FD2
@
1
H12
H_2P3
@
1
C330
0.1U_0402_16V4Z
DA4 PACDN042Y3R_SOT23-3
2
3
1
H6
H_4P0
@
1
JP6
JST_SM06B-XSRK-ETB(HF)
CONN@
11
22
33
44
55
66
GND 7
GND 8
R907
100K_0402_5%
12
FD1
@
1
H13
H_2P3
@
1
C646
0.1U_0402_16V4Z
1
2
CA26
10U_0805_10V4Z@
1
2
C643
0.1U_0402_16V4Z
1
2
C645
0.1U_0402_16V4Z
1
2
H7
H_4P0
@
1
C708
1U_0402_6.3V4Z
1
2
C642
0.1U_0402_16V4Z
@
1
2
C329
4.7U_0805_10V4Z
1
2
CA25
10U_0805_10V4Z@
1
2
H3
H_2P8
@
1
Q15B
2N7002DW-T/R7_SOT363-6
3
5
4
H16
H_2P3
@
1
H5
H_4P0
@
1
C327
0.01U_0402_25V7K1
2
H2
H_2P1N
@
1
CA20
10U_0805_10V4Z@
1
2
R211
100K_0402_5%
1 2
CA24
1U_0402_6.3V4Z
@
1
2
U48
APL3510BXI-TRG MSOP 8
GND
1
IN
2
OC# 5
OUT 6
OUT 8
IN
3
EN#
4
OUT 7
R213 0_0402_5%
1 2
JSPK1
ACES_88231-04001
CONN@
1
1
2
2
3
3
4
4
GND1
5
GND2
6
H8
H_2P3
@
1
DA5
PACDN042Y3R_SOT23-3
2
3
1
C648
0.1U_0402_16V4Z
1
2
R857
10K_0402_5%
12
C326
0.1U_0402_16V7K
1
2
C644
0.1U_0402_16V4Z
1
2
CA27
1U_0402_6.3V4Z
@
1
2
H15
H_2P3
@
1
LA5
FBMA-L11-160808-800LMT_0603
1 2
G
D
S
Q17
AO3413_SOT23
2
1 3
H10
H_2P3
@
1
C636
4.7U_0805_10V4Z
1
2
C328
0.1U_0402_16V4Z
LA4
FBMA-L11-160808-800LMT_0603
1 2
C647
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
SD_CLK
MS_CLK
CR_LED#
SD_CD#
MS_CD#
XD_RE#
XD_ALE
XD_SD_MMC_D6
XD_SD_MMC_D7
XD_RB#
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_CLE
SDCLK_MSCLK_XDCE#
SEL24
SEL41
XD_SD_MS_D0
XD_SD_MS_D3
XD_SD_MS_D1
XD_SD_MS_D2
XDWP#_SDW P#
PCIE_ITX_C_PRX_N1
CLK_PCIE_MCARD0
PCIE_PTX_IRX_N1
CLK_PCIE_MCARD0#
PCIE_ITX_C_PRX_P1
CPPE#
XD_CD#
SEL43
XD_CE#
XD_RB#
SDCLK_MSCLK_XDCE#
PCIE_PTX_IRX_P1
SD_CLK
XD_CD#
SDCMD_MSBS_XDWE#
XD_SD_MMC_D4
XD_SD_MS_D2
XDWP#_SDW P#
XD_CLE
XD_RE#
SDCMD_MSBS_XDWE#
XD_CD#
XD_SD_MMC_D6
XD_SD_MS_D0
SD_CLK
XD_SD_MS_D1
XDWP#_SDW P#
MS_CLK
XD_SD_MMC_D5
XD_SD_MS_D3
XD_SD_MS_D3
XD_SD_MS_D2
XD_SD_MMC_D6
XD_ALE
MS_CD#
XD_SD_MS_D0
SDCMD_MSBS_XDWE#
XD_SD_MS_D1
XD_SD_MMC_D7
XD_SD_MS_D2
XD_SD_MS_D1
XD_CE#
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MS_D0
XD_RB#
XD_SD_MMC_D7SD_CD#
XD_SD_MS_D3
XD_ALE
XD_CLE
SDCMD_MSBS_XDWE#
SD_CD#
MS_CLK
MS_CD#
XD_CE#
XD_CD#
SEL33
XDWP#_SDW P#
SDCMD_MSBS_XDWE#
SEL41
SEL24
SEL43
SEL33
CPPE#
SD_CD#
SD_CD#
CLK_PCIE_MCARD0#20
PLT_RST#12,15,20,26,27,31,32
PCIE_ITX_C_PRX_P111
CLK_PCIE_MCARD020
PCIE_PTX_C_IRX_N111
PCIE_ITX_C_PRX_N111
PCIE_PTX_C_IRX_P111
CR_LED#33
CR_WAKE#22
CR_CPPE#_SB21
CR_CPPE#_EC31
+VCC_OUT
+3VS
+VCC_OUT
+VCC_OUT
+1.8VS_OUT
+1.8VS_OUT
+3VS
+TVA33
+TVA33
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.1
Card Reader JMB389
Custom
30 45Tuesday, March 23, 2010
2010/01/22 2011/01/22
Compal Electronics, Inc.
Strapping setting
Pin name
MDIO14
Description
High
CR_LED
high active
CR_LED
low active
low
20mil
Power Circuit
place near pin 10
40 mils
40mil
20mil
Place RC5, RC17, RC19 close to pin42
For EMI close to JREAD
12mil
place near pin 19,20 and 44.
place near pin37
place 6 GND vias
MDIO14
MDIO7
MDIO14
on board add-in card
3/17 JMB385 co-lay
3/17 JMB385 co-lay
3/17 JMB385 co-lay
CC12 close to pin43
For internal LDO in SD3.0
3/17 JMB385 co-lay
3/18 22U change to 10U
3/18 10K change to 200K
place near pin 5
place near pin18
3/19 remove 22P_0402
place near pin 36
D3E suport
3/19 co-lay 0 ohm
3/22 co-lay 0 ohm
3/23 JMB385 co-lay
3/23 JMB385 co-lay
CC10
0.22U_0402_6.3V6K
1
2
RC3
100_0402_5%
JMB389@
1 2
RC22 4.7K_0402_5%
JMB385@
1 2
RC13 0_0402_5%
1 2
CC5 0.1U_0402_16V4Z
1 2
RC5 200K_0402_5%
1 2
RC127
0_0402_5%@
1 2
R922 0_0402_5%
1 2
CC17
10U_0805_10V6K
1
2
CC18
0.1U_0402_16V4Z
1
2
CC16
0.1U_0402_16V4Z
JMB389@
1
2
CC15
0.1U_0402_16V4Z
@
1
2
RC16
100_0402_5%
@
1 2
RC3
0_0402_5%
JMB385@
CC3
1000P_0402_50V7K
1
2
RC125
0_0402_5%
JMB389@
1 2
RC11 0_0402_5%
1 2
RC23 4.7K_0402_5%
JMB385@
1 2
CC20
100P_0402_50V8J
@
1 2
RC12 0_0402_5%
1 2
RC124
10K_0402_5%
12
RC126 0_0402_5%@
1 2
RC17 10K_0402_5%
@
1 2
RC2
9.1K_0402_1%
JMB385@
JMB389
UC1
JMB389-QGAZ0C_QFN48_7X7
JMB389@
XRSTN
1
XTEST
2
APCLKN
3
APCLKP
4APVDD 5
NC/SPI_SCK 30
APREXT
7
APRXP
8APRXN
9
APV18 10
APTXN
11
APTXP
12
CPPE_N
13
CR1_CD2N
14
CR1_CD1N
15
CR1_CD0N
16
CR1_PCTLN
17
DV18 18
DV33 19
DV33 20
CR1_LEDN
21
MDIO14 22
MDIO13 23
APGND 6
MDIO12 25
MDIO11 26
MDIO10 27
MDIO9 28
MDIO8 29
NC/TAV33 36
NC/GND 31
NC/GND 32
NC/GND 38
NC/SPI_CSN 33
NC/SPI_SO 34
NC/SPI_SI 35
DV18 37
SDDV/MDIO4
43
TXIN/NC
39
MDIO7 40
G/MDIO6 24
MDIO5 42
MDIO6/4 41
DV33 44
MDIO3 45
MDIO2 46
MDIO1 47
MDIO0 48
GND 49
RC24 4.7K_0402_5%
JMB385@
1 2
RC9 1K_0402_5%
12
CC7 0.1U_0402_16V4Z
1 2
RC2 12K_0402_1%
JMB389@
12
RC20 10K_0402_5%
12
DC1
CH751H-40PT_SOD323-2
21
CC14
0.1U_0402_16V4Z
@
1
2
CC2
0.22U_0402_6.3V6K
1
2
RC19 10K_0402_5%
1 2
UC1
JMB385-QGAZ0C QFN 48P
JMB385@
RC128
10K_0402_5%
@
12
CC8 0.1U_0402_16V7K
1 2
RC28 0_0402_5%
JMB385@
1 2
RC15
100_0402_5%
@
1 2
RC25 0_0402_5%
JMB385@
1 2
CC130.1U_0402_16V4Z
JMB389@
1
2
CC11
10U_0603_6.3V6M
1
2
RC29 0_0402_5%
JMB389@
1 2
JREAD1
TAITW_R013-P12-HM_44P_NR-T
CONN@
SD_VCC
13
MS_VCC
22
XD_VCC
43
XD_D0 35
XD_D1 36
XD_D2 37
XD_D3 38
XD_D4 39
XD_D5 40
XD_D6 41
XD_D7 42
XD_CD 26
XD_R/B 27
XD_RE 28
XD_CE 29
XD_CLE 30
XD_ALE 31
XD_WE 32
XD_WP 33
SD_GND 7
SD_GND 15
MS_GND 6
MS_GND 24
XD_GND 34
XD_GND 44
GND 45
GND 46
MS_DATA0
12
MS_DATA1
11
MS_DATA2
14
MS_DATA3
18
MS_SCLK
20
MS_INS
16
MS_BS
9
SD_WP
2
SD/MMC_DAT0
4
SD/MMC_DAT1
3
SD/MMC_DAT2
25
SD/MMC_DAT3
23
MMC_DATA4
21
MMC_DATA5
17
MMC_DATA6
8
MMC_DATA7
5
SD_CLK
10
SD_CMD
19
SD_CD
1
CC9 0.1U_0402_16V7K
1 2
RC26 0_0402_5%
JMB385@
1 2
R921 0_0402_5%
@
1 2
CC4
0.1U_0402_16V4Z
1
2
CC1
10U_0603_6.3V6M
1
2
CC12
2.2U_0603_6.3V6K
JMB389@
12
RC14
100_0402_5%
@
1 2
RC30 0_0402_5%
JMB385@
1 2
CC6 0.1U_0402_16V4Z
1 2
RC27 0_0402_5%
JMB389@
1 2
CC19
100P_0402_50V8J
@
1 2
G
D
S
QC1
2N7002_SOT23-3
2
1 3
RC21 10K_0402_5%
JMB385@
12
CC21
100P_0402_50V8J
@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SYSON
KSI[0..7]
KSO[0..17]
SUSP#
ECAGND
EC_SMB_CK2
EC_SMB_DA1
TP_CLK
TP_DATA
LID_SW#
KSO1
KSO2
ON/OFFBTN#
ACIN_D
EC_SMB_DA2
EC_SMB_CK1
SLP_CHG#
SLP_CHG_M4
SB_PWRGD
EC_RSMRST#
EC_SMB_CK1
KSO7
WOL_EN#
VGATE
EC_MUTE#
CHGVADJ
BATT_TEMPA
KSI1
KSI0
KSO14
E51_RXD
PM_SLP_S3#
KB_RST#
HDPINT
IREF
ADP_V
KSO6
ON/OFFBTN#
VR_ON
SYSON
KSO9
LPC_AD0
EC_SEL
TP_DATA
KSO15
CURS_LED#
BATT_LOW_LED#
KSI3
FAN_SPEED1
SLP_CHG_M4_EC
KSO10
KSO8
SPI_CS#
TP_CLK
EC_SMB_DA2
EC_SMB_CK2
KSI2
KSO12
LPC_AD3
EC_LID_OUT#
KSI4
EC_BEEP
EC_SCI#
LPC_FRAME#
ACIN_D
SUSP#
BATT_FULL_LED#
HDPACT
CLK_PCI_EC
PLT_RST#
CRY2
VLDT_EN
CAPS_LED#
USB_EN#
KSO11
EN_DFAN1
KSI5
PLT_RST#
LPC_AD1
GATEA20
CRY1
EC_SI_SPI_SO
PBTN_OUT#
USB_OC#2
LID_SW#
UMA_ENBKL
BKOFF#
PWR_ON_LED#EC_SMB_DA1
ACOFF
EC_SEL
SPI_CLK
SLP_CHG#
SLP_CHG_M3_EC
NUM_LED#
PWR_SUSP_LED#
EC_INVT_PWM
EC_SO_SPI_SI
FSTCHG
USB_CHG_EN#
KSO3
WL_BT_LED#
LPC_AD2
SERIRQ
SLP_CHG_M3
USB_OC#0
WL_OFF#
EC_ON
ECAGND
KSO4
KSO2
ECRST#
KSO17
E51_TXD
EC_SMI#
KSO13
KSO1
KSO16
HDPLOCK
KSO0
PM_SLP_S5#
KSO5
KSI6
KSI7
ADAPTOR_SEL
ADAPTOR_SEL
PLT_RST#12,15,20,26,27,30,32
LPC_FRAME#20,32
SERIRQ20,32
LPC_AD120,32
LPC_AD220,32
LPC_AD020,32
LPC_AD320,32
CLK_PCI_EC20,24
EC_SCI#21
BATT_TEMPA 36
SYSON 34,40
EC_RSMRST# 21
VR_ON 34,42
GATEA2021
KB_RST#21
ACOFF 37
SUSP# 26,28,34,37,41
USB_EN# 29
PBTN_OUT# 21
CHGVADJ 37
FSTCHG 37
IREF 37
CAPS_LED# 32
SB_PWRGD 21
EN_DFAN1 5
TP_CLK 33
TP_DATA 33
EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
SPI_CS# 32
EC_ON 33,34
BKOFF# 18
WL_OFF# 26
BATT_FULL_LED# 33
BATT_LOW_LED# 33
WL_BT_LED#33
KSI[0..7]32
KSO[0..17]32
EC_BEEP 28
ADP_I 37
LID_SW# 33
EC_INVT_PWM18
VLDT_EN 34,39
USB_OC#0 21,29
ACIN 22,33,35
UMA_ENBKL 12
HDPACT 32
USB_OC#2 21,25
HDPINT 32
CURS_LED# 32
WOL_EN# 27
PWR_ON_LED# 33
SPI_CLK 32
EC_MUTE# 28
SLP_CHG# 25
SLP_CHG_M3 22,25
SLP_CHG_M4 22,25
E51_RXD26
PM_SLP_S5#21
PCH_OFF 34
VGATE 34,42
EC_SMB_CK27,32
PWR_SUSP_LED#33
ON/OFFBTN#33
PM_SLP_S3#21
FAN_SPEED15
EC_SMB_CK136
E51_TXD26
NUM_LED#32
EC_SMI#21
USB_CHG_EN# 25
EC_SMB_DA136
ADP_V 37
HDPLOCK32
EC_SMB_DA27,32
EC_LID_OUT# 21
RTCCLK20
CR_CPPE#_EC30
+EC_AVCC+3VL +3VL_EC
+5VL
+3VS
+5VS
+3V_ALW
+3VL
+3VL
+3VL
+3VL_EC
+3VL
+3VL
+3VALW
+3VL_EC
+EC_AVCC
+3VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
31 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
/
ENE KB926C
E51_TXD PL on Page 26
G-Sensor
WOL_EN#
USB Charger
CURS_LED#
Add PWR_ON_LED#
G-Sensor
G-Sensor
1/21 Add SLP_CHG_M3
EC_SEL EC_VERSION
HIGH
LOW
KB926D3
KB926E0
12/18 Add EC_MUTE#
1/19 Change net name SLP_CHG-->SLP_CHG#
1/21 Add SLP_CHG_M4
1/25 Add net PCH_OFF
1/27 +3VALW-->+3V_ALW
3/22 Add CPPE to KBC
3/22 Add CPPE to KBC
C341 0.1U_0402_16V4Z
1 2
R785
100K_0402_5%
@
12
R235 47K_0402_5%
12
C334
0.1U_0402_16V4Z
1
2
R223 10K_0402_5%
1 2
L39
0_0603_5%
12
R238 100K_0402_5%
12
C336 0.01U_0402_25V7K
1 2
C343
15P_0402_50V8J
12
R231 2.2K_0402_5%
12
R230 10K_0402_5%
12
C342
15P_0402_50V8J
12
R773 10K_0402_5%
1 2
C340 4.7U_0805_10V4Z
12
LPC & MISC
Int. K/B
Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U12
KB926QFE0_LQFP128_14X14
GA20/GPIO00
1
KBRST#/GPIO01
2
SERIRQ#
3
LFRAME#
4
LAD3
5
PM_SLP_S3#/GPIO04
6
LAD2
7
LAD1
8
VCC 9
LAD0
10
GND
11
PCICLK
12
PCIRST#/GPIO05
13
PM_SLP_S5#/GPIO07
14
EC_SMI#/GPIO08
15
LID_SW#/GPIO0A
16
SUSP#/GPIO0B
17
PBTN_OUT#/GPIO0C
18
EC_PME#/GPIO0D
19
SCI#/GPIO0E
20
INVT_PWM/PWM1/GPIO0F 21
VCC 22
BEEP#/PWM2/GPIO10 23
GND
24
EC_THERM#/GPIO11
25
FANPWM1/GPIO12 26
ACOFF/FANPWM2/GPIO13 27
FAN_SPEED1/FANFB1/GPIO14
28
FANFB2/GPIO15
29
EC_TX/GPIO16
30
EC_RX/GPIO17
31
ON_OFF/GPIO18
32
VCC 33
PWR_LED#/GPIO19
34
GND
35
NUMLED#/GPIO1A
36
ECRST#
37
CLKRUN#/GPIO1D
38
KSO0/GPIO20
39
KSO1/GPIO21
40
KSO2/GPIO22
41
KSO3/GPIO23
42
KSO4/GPIO24
43
KSO5/GPIO25
44
KSO6/GPIO26
45
KSO7/GPIO27
46
KSO8/GPIO28
47
KSO9/GPIO29
48
KSO10/GPIO2A
49
KSO11/GPIO2B
50
KSO12/GPIO2C
51
KSO13/GPIO2D
52
KSO14/GPIO2E
53
KSO15/GPIO2F
54
KSI0/GPIO30
55
KSI1/GPIO31
56
KSI2/GPIO32
57
KSI3/GPIO33
58
KSI4/GPIO34
59
KSI5/GPIO35
60
KSI6/GPIO36
61
KSI7/GPIO37
62
BATT_TEMP/AD0/GPIO38 63
BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65
AD3/GPIO3B 66
AVCC 67
DAC_BRIG/DA0/GPIO3C 68
AGND
69
EN_DFAN1/DA1/GPIO3D 70
IREF/DA2/GPIO3E 71
DA3/GPIO3F 72
CIR_RX/GPIO40 73
CIR_RLC_TX/GPIO41 74
AD4/GPIO42 75
SELIO2#/AD5/GPIO43 76
SCL1/GPIO44
77
SDA1/GPIO45
78
SCL2/GPIO46
79
SDA2/GPIO47
80
KSO16/GPIO48
81
KSO17/GPIO49
82
PSCLK1/GPIO4A 83
PSDAT1/GPIO4B 84
PSCLK2/GPIO4C 85
PSDAT2/GPIO4D 86
TP_CLK/PSCLK3/GPIO4E 87
TP_DATA/PSDAT3/GPIO4F 88
FSTCHG/SELIO#/GPIO50 89
BATT_CHGI_LED#/GPIO52 90
CAPS_LED#/GPIO53 91
BATT_LOW_LED#/GPIO54 92
SUSP_LED#/GPIO55 93
GND
94
SYSON/GPIO56 95
VCC 96
SDICS#/GPXOA00 97
SDICLK/GPXOA01 98
SDIDO/GPXOA02 99
EC_RSMRST#/GPXO03 100
EC_LID_OUT#/GPXO04 101
EC_ON/GPXO05 102
EC_SWI#/GPXO06 103
ICH_PWROK/GPXO06 104
BKOFF#/GPXO08 105
WL_OFF#/GPXO09 106
GPXO10 107
GPXO11 108
SDIDI/GPXID0 109
PM_SLP_S4#/GPXID1 110
VCC 111
ENBKL/GPXID2 112
GND
113
GPXID3 114
GPXID4 115
GPXID5 116
GPXID6 117
GPXID7 118
SPIDI/RD# 119
SPIDO/WR# 120
VR_ON/XCLK32K/GPIO57 121
XCLK1
122
XCLK0
123 V18R 124
VCC 125
SPICLK/GPIO58 126
AC_IN/GPIO59 127
SPICS# 128
R868 0_0402_5%
@
1 2
D12
CH751H-40PT_SOD323-2
2 1
R909
100K_0402_5%
@
12
C331
0.1U_0402_16V4Z
1
2
R862 100K_0402_5%
1 2
R775 100K_0402_5%
1 2
R786
100K_0402_5%
12
R233 150K_0402_5%
1 2
R910
100K_0402_5%
12
L38
0_0603_5%
12
C641 0.1U_0402_16V4Z
@
12
L40
0_0603_5%
12
C335
1000P_0402_50V7K
1
2
C339 100P_0402_50V8J
12
R240
20M_0402_5%
@
12
R227 2.2K_0402_5%
12
R867 0_0402_5%@
1 2
C333
1000P_0402_50V7K
1
2
R225 4.7K_0402_5%
1 2
R323
100K_0402_5%
1 2
Y4
32.768KHZ_12.5PF_Q13MC14610002
OSC 4
OSC 1
NC
3
NC
2
R232 100K_0402_5%
12
R229 2.2K_0402_5%
12
R226 4.7K_0402_5%
1 2
C332
0.1U_0402_16V4Z
1
2
R923 0_0402_5%
@
1 2
C337
0.1U_0402_16V4Z
12
C469 0.22U_0603_16V4Z
1 2
R234 47K_0402_5%
12
R224 10K_0402_5%
1 2
R228 2.2K_0402_5%
12
R236
47K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LPC_AD2
LPC_AD1
PLT_RST#
LPC_FRAME#
LPC_AD0
LPC_AD3
KSI[0..7]
KSO[0..17]
KSO12
KSO11
KSO10
KSI4
KSI3
KSI2
KSI7
KSO15
KSO14
KSI1
KSI6
KSI5
KSI0
KSO1
KSO0
KSO5
KSO4
KSO2
KSO8
KSO7
KSO3
KSO13
KSO6
CAPS_LED#
NUM_LED#
KSO9
KSO16
KSO17
SPI_CS#
SPI_CLK
EC_SO_SPI_SI EC_SI_SPI_SO
CURS_LED#
NUM_LED#
CAPS_LED#
+3VS_MUM
KSO5
KSO4
KSO2
KSO14
KSO15
KSO13
KSO6
KSO12
KSO1
KSO0
KSO8
KSO11
KSO10
KSO7
KSO3
KSI1
KSI7
KSI3
KSI2
KSI0
KSO9
+3VS_CAPS
KSI4
KSI6
KSI5
+3VS_CURS
CURS_LED# NUM_LED#
CAPS_LED#
+3VS_MUM
KSO5
KSO4
KSO2
KSO14
KSO15
KSO13
KSO6
KSO12
KSO1
KSO0
KSO8
KSO11
KSO10
KSO7
KSO3
KSI1
KSI7
KSI3
KSI2
KSI0
KSO9
+3VS_CAPS
KSI4
KSI6
KSI5
+3VS_CURS
CURS_LED#
GXIN
GXOUT
SELF_TEST
VOUTX
VOUTY
VOUTZ
VOUTX
VOUTY
VOUTZ
SELF_TEST
VOUTX
SELF_TEST
VOUTY
VOUTZ
SPI_CLK
LPC_FRAME#20,31
SERIRQ20,31
LPC_AD2 20,31
LPC_AD0 20,31
LPC_AD320,31
LPC_AD120,31
PLT_RST# 12,15,20,26,27,30,31
LPC_CLK1 20,24
KSI[0..7] 31
KSO[0..17] 31
SPI_CLK31
EC_SO_SPI_SI31
SPI_CS#31
EC_SI_SPI_SO 31
NUM_LED# 31
CAPS_LED# 31
CURS_LED# 31
HDPLOCK 31
HDPINT31
HDPACT 31
EC_SMB_CK27,31
EC_SMB_DA2 7,31
+3VS
+3VL
+3VS
+3VS
+3VS
+3VS_HDP
+3VS_HDP
+5VS +3VS_HDP
+3VS_HDP+3VS
+3VS_HDP
+3VS_HDP
+3VS_HDP
+3VS_HDP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0Custom
32 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
SPI/LPC/PS2/MDC/FM/CIR
(Please place the PAD under DDR DIMM)
Option 1:SPI Flash (2MB*1) for EC
11.6 KEYBOARD CONN.
13.3 KEYBOARD CONN.
10/10 New CURS_LED## for 11.3&13.6
10/10 New CURS_LED# cap for 11.3&13.6
SPI Socket: SP07000F500 & SP07000H900
2MB P/N:MXIC SA00002TO00 S IC FL 16M MX25L1605DM2I-12G SOP 8P ROM
256KB P/N:MXIC SA00003GK00 S IC FL 2M MX25L2005CMI-12G SOP 8P
Change U55 to G9191-330T1U
Reserve Freescale
20mil
LPC Debug Port
Option 2:SPI Flash (256KB*1) for EC
SPI Flash (2MB*1) for SB (set up strap pin)
New keyboard
12/18 <BOM>R788 @-->100ohm and C634 @-->100P for RF request
G-Sensor
12/31 SMT memo control
12/31 SMT memo control
1/27 Del R246
03/11 update G-sensor P/N
CG11 0.1U_0402_16V4Z
2ND@ 12
C363 100P_0402_50V8J
1 2
C360 100P_0402_50V8J
1 2
C352 100P_0402_50V8J
1 2
C355 100P_0402_50V8J
1 2
C345
0.1U_0402_16V4Z
1
2
C362 100P_0402_50V8J
1 2
RG9
47K_0402_5%
GSENSOR@
1 2
C368 100P_0402_50V8J
1 2
C357 100P_0402_50V8J
1 2
C350 100P_0402_50V8J
1 2
C366 100P_0402_50V8J
1 2
U13
MX25L2005CMI-12G SO8
S
1
VCC
8
Q2
HOLD
7
VSS 4
D
5
C
6
W
3
CG13
1U_0402_6.3V4Z
GSENSOR@
1
2
JKB2
ACES_88170-3400
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C354 100P_0402_50V8J
1 2
C372 100P_0402_50V8J
1 2
RG10 47K_0402_5%
GSENSOR@
12
C615 100P_0402_50V8J
1 2
CG6
0.1U_0402_16V4Z
GSENSOR@
1
2
C370 100P_0402_50V8J
1 2
R245 300_0402_5%
12
C367 100P_0402_50V8J
1 2
DG1 CH751H-40PT_SOD323-2GSENSOR@
21
UG1
TSH35TR_LGA16
1ST@
GND1 1
Vdd1
2Voutx 3
ST
4
Vouty 5
PD
6
Voutz 7
FS
8
Rev
9
NC1 10
NC2 11
Vdd2
12
GND2 13
NC3 14
NC4 15
NC5 16
UG4
MMA7360LR2_LGA14
2ND@
XOUT
2
YOUT
3
ZOUT
4
VSS 5
VDD 6
SLEEP#
7
0G-DET
9
G-SELECT
10
ST
13
NC 1
NC 8
NC 11
NC 12
NC 14
C356 100P_0402_50V8J
1 2
RG3
4.7K_0402_5%GSENSOR@
12
RG5
4.7K_0402_5%GSENSOR@
12
C347 100P_0402_50V8J
1 2
RG2
0_0603_5%
@
12
CG2 0.033U_0402_16V7K1ST@
1 2
C358 100P_0402_50V8J
1 2
C361 100P_0402_50V8J
1 2
CG10 0.1U_0402_16V4Z
2ND@ 12
C349 100P_0402_50V8J
1 2
C371
22P_0402_50V8J
@
1
2
C373 100P_0402_50V8J
1 2
RG6
4.7K_0402_5%
GSENSOR@
12
RG7
1K_0402_5%
GSENSOR@
12
CG1 0.033U_0402_16V7K1ST@
1 2
UG6
R5F211B4D34SP_LSSOP20
1STGSENSOR@
P3_7/CNTR0#/SSO/TXD1
2
XOUT/P4_7
4
P1_0/KI0#/AN8/CMP0_0 18
VSS/AVSS
5
P1_1/KI1#/AN9/CMP0_1 17
XIN/P4_6
6
P3_5/SSCK/SCL/CMP1_2
1
P1_5/RXD0/CNTR01/INT11# 12
RESET#
3
P1_3/KI3#/AN11/TZOUT 14
MODE
8
P1_7/CNTR00/INT10#
10
P4_2/VREF 16
P3_3/TCIN/INT3#/SSI00/CMP1_0 19
P1_6/CLK0/SSI01 11
P1_2/KI2#/AN10/CMP0_2 15
P1_4/TXD0 13
P3_4/SCS#/SDA/CMP1_1 20
P4_5/INT0#/RXD1
9
VCC/AVCC
7
CG9 0.1U_0402_16V4Z
2ND@ 12
C344 100P_0402_50V8J
1 2
C365 100P_0402_50V8J
1 2
H1
DEBUG_PAD
@
1
2
3
4
56
7
8
9
10
C353 100P_0402_50V8J
1 2
UG3
G9191-330T1U_SOT23-5
GSENSOR@
VIN
1
SHDN#
3
VOUT 5
GND
2
BP 4
CG8
0.1U_0402_16V4Z
GSENSOR@
1
2
C634 100P_0402_50V8J
1 2
C351 100P_0402_50V8J
1 2
JKB1
ACES_88170-3400
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C359 100P_0402_50V8J
1 2
C348 100P_0402_50V8J
1 2
CG3 0.033U_0402_16V7K1ST@
1 2
C346 100P_0402_50V8J
1 2
CG14
0.22U_0402_10V4Z
GSENSOR@
12
R248
22_0402_5%
@
1 2
RG4
4.7K_0402_5%GSENSOR@
12
R247 300_0402_5%
12
C369 100P_0402_50V8J
1 2
R344 300_0402_5%
12
C364 100P_0402_50V8J
1 2
CG12
1U_0402_6.3V4Z
GSENSOR@ 1
2
R788 100_0402_5%
1 2
CG7
0.1U_0402_16V4Z
GSENSOR@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DC_IN
ON/OFFBTN#
MEDIA_LED
HDD_LED
WIMAX_LED
PWR_SUSP_LED#
BATT_LOW_LED#
BATT_FULL_LED#
HDD_LED
MEDIA_LED
DC_IN DC_IN_R
PWR_ON_LED# PWR_ON_LED#_R
PWR_SUSP_LED#_R
BATT_FULL_LED#_R
BATT_LOW_LED#_R
HDD_LED_R
WIMAX_LED WIMAX_LED_R
WL_BT_LED# WL_BT_LED#_R
MEDIA_LED_R
TP_DATA
TP_CLK
LID_SW# LID_SW#_R
51_ON# 35
ACIN 22,31,35
SATA_LED# 22
TP_DATA31
TP_CLK31
EC_ON31,34
ON/OFFBTN#31
LED_WIMAX# 26
CR_LED# 30
BATT_LOW_LED#31
BATT_FULL_LED#31
WL_BT_LED#31
PWR_ON_LED#31
PWR_SUSP_LED#31
LID_SW#31
+5VS
+5VS
+5V_ALW
+3V_ALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
LED/LID/PB/FB/SCREW HOLE
Custom
33 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Power Button & Lid switch
Touch/B Connector
LED/B Connector
Check control pin?
DC-IN LED
HDD LED
12/15<BOM> C386 @-->0.1u
12/17 Q8 Q9 R258 R259-->@, R790 R791-->SMT
12/24 Add R864
03/11 Update JTP1 footprint
1/27 +3VALW-->+3V_ALW and +5VALW-->+5V_ALW
1/27 Del R808 R809 R810 R811
1/27 +3VALW-->+3V_ALW
1/27 Update footprint
03/10 Q15-->@ and R260 @-->SMT (memo)
03/10 Fine tune R813 R815 120ohm-->220ohm
R815 220_0402_5%
1 2
R813 220_0402_5%
1 2
R790
0_0402_5%
1 2
R260
0_0402_5%
1 2
R257
10K_0402_5%
1 2
C386
0.1U_0402_16V4Z
1
2
R820 120_0402_5%
1 2
R812 120_0402_5%
1 2
R818 120_0402_5%
1 2
Q14A
2N7002DW-T/R7_SOT363-6
6 1
2
R791
0_0402_5%
1 2
R816 120_0402_5%
1 2
R814 120_0402_5%
1 2
RC4
4.7K_0402_5%
@
1 2
Q14B
2N7002DW-T/R7_SOT363-6
3
5
4
D15
PACDN042Y3R_SOT23-3
2
3
1
R864 0_0402_5%
1 2
Q15A
2N7002DW-T/R7_SOT363-6@
6 1
2
JLED1
ACES_87213-1200G
@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
GND1
13
GND2
14
JTP1
P-TWO_161021-06021_6P-T
CONN@
GND
7
GND
8
1
1
2
2
3
3
4
4
5
5
6
6
JPB1
P-TWO_161011-04021_4P-T
CONN@
1
2
3
4
5
6
R819 120_0402_5%
1 2
R817 120_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RUNON
RUNON
SUSP
EC_ON#
EC_ON#
VLDT_EN
VLDT_EN#
1.5VS_ENABLE
SUSP
SYSON#SUSP SUSP
SUSP
VGATE#
VGATE# VR_ON#
SUSP
VLDT_EN#
PCH_OFF_R
PCH_OFF_R
SYSON# SUSP
PCH_OFF_R
PCH_OFF_R
EC_ON 31,33VLDT_EN31,39
VGATE31,42
VR_ON# 41
VR_ON 31,42
PCH_OFF31
SUSP# 26,28,31,37,41
SUSP 41
SYSON31,40
+0.75VS
+1.1VALW
+1.1VS
+3VALW +3VS
+5VALW
+5VS
+VSB
+VSB
+1.1VALW
+5VL+5VL
+1.5V
+VSB
+1.5VS
+5VS +3VS +1.8VS +1.5V
+5VL +5VL
+NB_CORE
+5V_ALW +5VALW
+5VL+5VL
+3VALW+3V_ALW
+VSB
+VSB
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
DC/DC Circuits
Custom
34 45Tuesday, March 23, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Inrush current = 0A
Inrush current = 0A
Inrush current = 0A
< +5VALW TO +5VS > < +1.5V TO +1.5VS >
< +1.1VALW TO +1.1VS >< +3VALW TO +3VS >
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
< Discharge circuit >
12/18 SYSON#-->SUSP
+5V_ALW to +5VALW Transfer +3V_ALW to +3VALW Transfer
(5A,200mils ,Via NO.= 10)
(OCP min=7.9A)
1/25 Add +5V_ALW to +5VALW Transfer
+3V_ALW to +3VALW Transfer
3/23 install C9063/23 install C901
Q22
IRF8113PBF_SO8
36
5
7
8
2
4
1
R900
330K_0402_5%
@
12
C905
10U_0805_10V4Z
@
1
2
Q19
SI4800BDY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C402
1U_0402_6.3V4Z
1
2
Q12A
2N7002DW-T/R7_SOT363-6
61
2
Q10B
2N7002DW-T/R7_SOT363-6
3
5
4
C408
4.7U_0805_10V4Z
1
2
R271
470_0805_5%
1 2
C396
0.01U_0402_25V7K
1
2
R902
10K_0402_5%
@
12
R331
470_0805_5%
@
1 2
C405
1U_0402_6.3V4Z
1
2
C900
10U_0805_10V4Z
@
1
2
R795 0_0402_5%
1 2
Q25A
2N7002DW-T/R7_SOT363-6
61
2
R262
10M_0402_5%
@
12
R268
10M_0402_5%
12
R270
470_0805_5%
1 2
C392
4.7U_0805_10V4Z
1
2
G
D
S
Q26
2N7002_SOT23-3
2
13
R279
470_0805_5%
1 2
G
D
S
Q28
2N7002_SOT23-3
2
13
J3 JUMP_43X118
@
11
2
2
C395
4.7U_0805_10V4Z
1
2
Q32B
2N7002DW-T/R7_SOT363-6
@
3
5
4
G
D
S
Q27
2N7002_SOT23-3
2
13
C903
0.1U_0402_16V4Z @
1
2
U50
SI7326DN-T1-E3_PAK1212-8
@
35
2
4
1
J2 JUMP_43X118
@11
2
2
Q25B
2N7002DW-T/R7_SOT363-6
3
5
4
Q13B
2N7002DW-T/R7_SOT363-6
3
5
4
C407
4.7U_0805_10V4Z
1
2
C390
1U_0402_6.3V4Z
1
2
R266
330K_0402_5%
12
C403
10U_0805_10V6K
1
2
U49
SI7326DN-T1-E3_PAK1212-8
@
35
2
4
1
R272
470_0805_5%
1 2
+
C622
330U_2.5V_M
1
2
Q11A
2N7002DW-T/R7_SOT363-6
61
2
R267
1M_0402_5%
1 2
Q35A
2N7002DW-T/R7_SOT363-6
61
2
Q40B
2N7002DW-7-F_SOT363-6
@
3
5
4
Q21
IRF8113PBF_SO8
36
5
7
8
2
4
1
R800
100K_0402_5%
12
Q12B
2N7002DW-T/R7_SOT363-6
3
5
4
R278
470_0805_5%
1 2
R269
10M_0402_5%
12
R276
100K_0402_5%
12
Q41A
2N7002DW-7-F_SOT363-6
@
61
2
G
D
S
Q23
2N7002_SOT23-3
2
13
Q35B
2N7002DW-T/R7_SOT363-6
3
5
4
C908
4700P_0402_25V7K
@
1
2
Q18
SI4800BDY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C904
4700P_0402_25V7K
@
1
2
R901
470_0805_5%
@
1 2
R796
100K_0402_5%
12
R329
100K_0402_5%
12
C388
4.7U_0805_10V4Z
1
2
Q10A
2N7002DW-T/R7_SOT363-6
61
2
Q41B
2N7002DW-7-F_SOT363-6
@
3
5
4
C387
1U_0402_6.3V4Z
1
2
Q11B
2N7002DW-T/R7_SOT363-6
3
5
4
R261
750K_0402_1%
12
Q40A
2N7002DW-7-F_SOT363-6
@
61
2
C394
4.7U_0805_10V4Z
1
2
R906
470_0402_5%
@
12
R330
470_0805_5%
@
1 2
R275
100K_0402_5%
12
R277
470_0805_5%
1 2
R280
470_0805_5%
1 2
G
D
S
Q31
2N7002_SOT23-3
@
2
13
C906
0.1U_0402_16V4Z
1
2
C406
4.7U_0805_10V4Z
1
2
C901
0.1U_0402_16V4Z
1
2
C409
0.01U_0402_25V7K
1
2
R903
470_0402_5%
@
12
C410
0.1U_0603_25V7M
1
2
Q13A
2N7002DW-T/R7_SOT363-6
61
2
R904
330K_0402_5%
@
12
R905
470_0805_5%
@
1 2
R274
100K_0402_5%
12
C902
10U_0805_10V4Z
@
1
2
C907
10U_0805_10V4Z
@
1
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
N1
N2
CHGRTCP
DC_IN_S1
PACIN
PACIN
N3
DC_IN_S2
51_ON#33
ACON37
EN038
ACIN 22,31,33
PACIN 37
+3VALWP +3V_ALW
+5VALWP
+VSBP +VSB
+0.9V+0.9VP
+1.5V
+1.1VALWP +1.1VALW
+5V_ALW
+VDDNB+VDDNBP +1.8VS+1.8VSP
+1.5VP
+2.5VS+2.5VSP
+RTCBATT
VIN
VIN
VS
BATT+
+CHGRTC
+CHGRTC
VIN
VS
N1
+CHGRTC
B+
VL
+5VALWP
VIN
+0.75VS+0.75VSP
VL +5VL
+3VLP +3VL
+NB_COREP +NB_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
DCIN/DECTOR
35 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
(4.6A,180mils ,Via NO.= 9)
OCP(min)=5.26A
(0.25A,10mils ,Via NO.=1)
(120mA,40mils ,Via NO.= 1)
(5A,200mils ,Via NO.= 10)
OCP(min)=7.9A
(1.3A,52mils ,Via NO.= 3)
(5A,200mils ,Via NO.= 10)
OCP(min)=8.1A
-+
RTC Battery
3.3V
X7999651L01
DC30100A900
Vin Detector
High 18.384 17.901 17.430
Low 17.728 17.257 16.976
3.3V
Precharge detector
15.97V/14.84V FOR
ADAPTOR
(8A,320mils ,Via NO.= 16)
OCP(min)=8.55A
(0.5A,20mils ,Via NO.= 1)
(100mA,40mils ,Via NO.= 2)
(100mA,40mils ,Via NO.= 2)
(1.3A,52mils ,Via NO.= 3)
OCP(min)=3A
(2A,80mils ,Via NO.= 4)
OCP(min)=3A
(7.6A,300mils ,Via NO.= 15)
OCP(min)=9.38A
PJ3
JUMP_43X118@
11
2
2
PC12
1000P_0402_50V7K
12
PR19
560_0603_5%
1 2
PR17
200_0603_5%
12
PR13
1K_1206_5%
1 2
PJ8
JUMP_43X118@
11
2
2
PC13
1000P_0402_50V7K
12
PR25
66.5K_0402_1%
@
12
PJ2
JUMP_43X118@
11
2
2
PC6
.1U_0402_16V7K
12
PQ3
DTC115EUA_SC70-3
2
13
PC7
0.22U_0603_25V7K
12
PR4
10K_0402_1%
1 2
PR26
191K_0402_1%
12
PU1B
LM393DG_SO8
+5
-6
O
7
P8
G
4
PJ12
JUMP_43X39@
11
2
2
PR9
68_1206_5%
12
PJ10
JUMP_43X79@
11
2
2
PD1
GLZ4.3B_LL34-2
12
G
D
S
PQ2
SSM3K7002FU_SC70-3
2
13
PR6
20K_0402_1%
12
PC1
1000P_0402_50V7K
12
PD2
RLS4148_LL34-2
1 2
PJ5
JUMP_43X118@
11
2
2
PL1
SMB3025500YA_2P
1 2
PC3
100P_0402_50V8J
12
PR21
100K_0402_1%
1 2
PBJ1
MAXEL_ML1220T10@
12
PJ1
JUMP_43X118@
11
2
2
PR7
10K_0402_1%
12
PR5
22K_0402_1%
1 2
PD3
RLS4148_LL34-2
12
PJP1
SINGA_2DW-0005-B03@
+1
-3
-4
+2
PR22
2.2M_0402_5%
12
PR8
10K_0402_1%
12
PC2
1000P_0402_50V7K
12
PU2 G920AT24U_SOT89-3
IN 2
GND
1
OUT
3
PD4
RLS4148_LL34-2
12
PU1A
LM393DG_SO8
+
3
-
2O1
P8
G
4
PR2
5.6K_0402_5%
12
PC5
0.068U_0402_10V6K
12
PC11
1000P_0402_50V7K
12
PR16
1K_1206_5%
1 2
PR10
68_1206_5%
12
PC19
680P_0402_50V7K
@
12
PJ4
JUMP_43X118@
11
2
2
PJ9
JUMP_43X79@
11
2
2
PD5
RB715F_SOT323-3
2
3
1
PR15
1K_1206_5%
1 2
PC9
10U_0805_10V4Z
12
PJ15
JUMP_43X79@
11
2
2
PJ17
JUMP_43X39@
11
2
2
PC10
1U_0805_25V4Z
12
PR14
22K_0402_1%
1 2
PR23
10K_0402_1%
12
PR3
84.5K_0402_1%
12
PR1
1M_0402_1%
1 2
PR11
200_0603_5%
1 2
PC18
680P_0402_50V7K
@
12
PR27
47K_0402_1%
12
PR20
499K_0402_1%
12
PJ7
JUMP_43X39@
11
2
2
PR18
560_0603_5%
1 2
PR24
499K_0402_1%
12
PC8
0.1U_0603_25V7K
12
PQ1
TP0610K-T1-E3_SOT23-3
2
13
PR12
100K_0402_1%
12
PC4
100P_0402_50V8J
12
PJ6
JUMP_43X39@
11
2
2
PF1
7A_24VDC_429007.WRML
21
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMDA
BATT_S1
EC_SMCA
BATT_P3
BATT_P4
BATT_P5
BATT_P4
BATT_P5
BATT_S1
BATT_P3
EC_SMDA
EC_SMCA
BATT_S1
BATT_TEMPA 31
POK38,39
EC_SMB_DA1 31
EC_SMB_CK1 31
VS_ON38
BATT+
+3VLP
VMB
+3VLP
B+ +VSBP
VL
VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
BATTERY CONN / OTP
36 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
For 11.6"
For 13.3"
Recovery at 56 degree C
CPU thermal protection at 92 degree C
PH1 under CPU botten side :
Recovery at 42 degree C
BAT thermal protection at 78 degree C
PH2 near main Battery CONN:
Rset = 3*Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 92C = 7.71K,Rtml at 56C = 26.1K
Rset = 3* 7.31 = 21.9K ==> PR37 = 22K
Rhyst = ( 22K* 26.1K ) / ( 3* 26.1K - 22K) = 10.199K ==> PR38 = 10.2K
Rtmh at 78C = 11.635.K,Rtml at 42C = 46.38K
Rset = 3* 11.635 = 34.91K ==> PR31 = 34.8K
Rhyst = ( 34.8K* 46.38K ) / ( 3* 46.38K - 34.8K) = 15.468K ==> PR32 = 15.4K
PR47
100K_0402_1%
1 2
PD17
PJSOT24C_SOT23-3
@
2
3
1
PR39
1K_0402_1%
12
PR38
10.2K_0402_1%
1 2
PC17
0.1U_0603_25V7K
12
PH2
100K_0402_1%_NCP15WF104F03RC
12
PR28
1K_0402_1%
1 2
PJP2
SUYIN_200045MR009G171ZR@
11
33
44
55
66
88
99
22
77
GND
11 GND
10
GND
12
GND
13
PR46
22K_0402_1%
1 2
PC16
0.01U_0402_25V7K
12
PF2
10A_125V_451010MRL
21
PC15
1000P_0402_50V7K
12
PR34
100_0402_1%
1 2
PR36
6.49K_0402_1%
12
PR30
1K_0402_1%
12
PR37
22K_0402_1%
12
PD16
PJSOT24C_SOT23-3
@
2
3
1
PQ5
TP0610K-T1-E3_SOT23-3
2
13
PL2
SMB3025500YA_2P
1 2
PR31
34.8K_0402_1%
1 2
PC14
0.1U_0402_25V6
@
12
PR48
0_0402_5%
1 2
G
D
S
PQ6
SSM3K7002FU_SC70-3
2
13
PU3
G718TM1U_SOT23-8
RHYST2 5
OT1
3
OT2
4
GND
2
VCC
1
TMSNS2 6
RHYST1 7
TMSNS1 8
PJP3
SUYIN_200045MR009G171ZR@
11
33
44
55
66
88
99
22
77
GND
11 GND
10
GND
12
GND
13
PC22
0.1U_0603_25V7K
@
12
PR29
47K_0402_1%
1 2
PR45
100K_0402_1%
12
PH1
100K_0402_1%_NCP15WF104F03RC
12
PR32
15.4K_0402_1%
12
PR35
100_0402_1%
1 2
PC21
0.22U_0603_25V7K
@
12
PC23
.1U_0402_16V7K
@
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ACOFF
CSON
6251_EN CSON
ACOFF
6251VDD
6251VDD
6251VREF
CSOP
6251VREF
DCIN
PACIN
FSTCHG
BST_CHG
PACIN
6251aclim
DH_CHG
CSIP
DL_CHG
CSIN
LX_CHG
6251VDDP
BST_CHGA
CHG
DCIN
IREF31
FSTCHG31
PACIN35
ACOFF31
SUSP# 26,28,31,34,41
CHGVADJ31
ACON35
ADP_I31
ADP_V 31
VIN
VIN
BATT+
P2 P3
B+
CHG_B+
P3
VIN
B+
VIN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
CHARGER
Custom
37 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
CC=0.25A~3A
IREF=0.254V~3.048V
IREF=1.096*Icharge
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.04596V, Iinput=2.178A
CP mode
Vaclim=2.39*(20K//152K/(20K//152K+26.7K//152K))=1.04596V
VCHLIM need over 95mV
CHGVADJ=(Vcell-4)*9.445
Vcell CHGVADJ
4V
4.2V
4.35V
0V
1.882V
3.2935V
Iadapter=0~2.368A(45W) CP=Iadapter*0.92 CP=2.178A
PR58
150K_0402_1%
12
PC35 6800P_0402_25V7K
1 2
PL4
10U_LF919AS-100M-P3_4.5A_20%
1 2
PR61
20_0603_5%
1 2
PR57
10K_0402_1%
12
PR71
174K_0402_1%
12
PC69
10U_1206_25V6M
12
PD11
1SS355_SOD323-2
1 2
PC45
4.7U_0805_6.3V6K
1 2
PQ13
DTC115EUA_SC70-3
2
13
PC44
680P_0603_50V7K
@
12
PR60
200K_0402_1%
1 2
PR55
100K_0402_1%
12
PC32
0.047U_0603_16V7K
1 2
PR63
20_0603_5%
12
PR76
15.4K_0402_1%
1 2
PR79
10K_0402_1%
1 2
PD9
1SS355_SOD323-2
1 2
PD10
1SS355_SOD323-2
1 2
PR78
309K_0402_1%
12
PR49
0.033_1206_1%
1
3
4
2
PQ10 TP0610K-T1-E3_SOT23-3
2
13
PR74
4.7_0603_5%
1 2
PC127
10U_1206_25V6M
12
PR69
4.7_1206_5%
@
12
PC41
10U_1206_25V6M
12
PQ20
DTC115EUA_SC70-3
2
13
PR50
200K_0402_1%
12
PR52
47K_0402_1%
12
PR59
100K_0402_1%
12
PC46
.1U_0402_16V7K
12
PC28
5600P_0402_25V7K
1 2
PQ8
AO4407A_SO8
3 6
5
7
8
2
4
1
PR53
100K_0402_1%
12
G
D
S
PQ17
SSM3K7002FU_SC70-3
2
13
PC42
10U_1206_25V6M
12
PC27
0.1U_0603_25V7K
12
PD8
RB715F_SOT323-3
2
3
1
PC39
.1U_0402_16V7K
1 2
PC40
0.1U_0603_25V7K
12
PR80
47K_0402_1%
12
PQ7
AO4435_SO8
4
7
8
6
5
1
2
3
PR51
10_0603_5%
1 2
PC31
.1U_0402_16V7K
1 2
G
D
S
PQ15
SSM3K7002FU_SC70-3
2
13
PC43
0.01U_0402_25V7K
12
PR65
2.2_0603_5%
1 2
PR68
22K_0402_5%
1 2
PR72
100K_0402_1%
12
PR66
47K_0402_1%
1 2
PC47
10U_1206_25V6M
12
PC33
0.1U_0603_25V7K
12
G
D
S
PQ18
SSM3K7002FU_SC70-3
2
13
PC34
680P_0402_50V7K
@
1 2
PQ19
AO4466_SO8
3 6
5
7
8
2
4
1
PR54
47K_0402_1%
1 2
PR62
20_0603_5%
1 2
PD12
RB751V-40TE17_SOD323-2
12
PR77
31.6K_0402_1%
12
PR64 6.81K_0402_1%
1 2
PU5
ISL6251AHAZ-T_QSOP24
EN
3
CELLS
4
VDD
1
ACSET
2
ICOMP
5
VCOMP
6
CHLIM
9
ACPRN 23
CSIP 19
UGATE 17
PHASE 18
BOOT 16
PGND 13
GND
12
ICM
7
VREF
8
VADJ
11
DCIN 24
CSIN 20
ACLIM
10
LGATE 14
VDDP 15
CSOP 21
CSON 22
PQ16
AO4466_SO8
3 6
5
7
8
2
4
1
PC37
0.1U_0603_25V7K
1 2
PC29
2.2U_0603_6.3V6K
12
PR75
20K_0402_1%
12
PR67
0.02_1206_1%
1
3
4
2
PQ11
DTA144EUA_SC70-3
2
1 3
PL3
HCB2012KF-121T50_0805
12
PC24
4.7U_0805_25V6-K
12
PC68
10U_1206_25V6M
12
PC38
100P_0402_50V8J
@
1 2
PC30
0.1U_0603_25V7K
12
PQ12
DTC115EUA_SC70-3
2
13
PQ9 AO4435_SO8
4
7
8
6
5
1
2
3
PQ14
DTC115EUA_SC70-3
2
13
PC36
0.01U_0402_25V7K
1 2
PR73
26.7K_0402_1%
1 2
PC25
4.7U_0805_25V6-K
12
PR70
0_0603_5%
1 2
PR56
10K_0402_1%
1 2
PC26
4.7U_0805_25V6-K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BST_5V
ENTRIP2
LX_5V
UG_5V
ENTRIP1
LG_5V
ENTRIP2ENTRIP1
LG_3V
LX_3V
UG_3V
BST_3V
POK 36,39
VS_ON36
EN035
+5VALWP
B++
B++
+3VALWP
B+
2VREF_51125
B++
+3VLP
VL
2VREF_51125
VS
VL
B+
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6032P
1.0
+5VALWP/+3VALWP
38 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
Imax = 3.5A
F = 245kHz
Total Capacitor = 150 uF
ESR = 18m Ohm
Total Capacitor = 150 uF
ESR = 18m Ohm
F = 305kHz
Imax = 3.5A
Ipeak = 5A
Ipeak = 5A
PR81
100K_0402_1%
12
PR82
4.7_1206_5%
12
PC62
680P_0603_50V8J
12
PC54
.1U_0402_16V7K
1 2
PR89
19.6K_0402_1%
1 2
PC49
2200P_0402_50V7K
12
PR91
121K_0402_1%
1 2
PR83
100K_0402_1%
1 2
PR95
100K_0402_5%
12
PC59
0.01U_0402_16V7K
@
12
PC56
1U_0603_25V6K
@
12
+
PC64
150U_V_6.3VM_R18
1
2
PC65
.1U_0402_16V7K
12
PL5
HCB4532KF-800T90_1812
1 2
PQ24
AON7702L_DFN8-5
4
5
1
2
3
PR87
30K_0402_1%
1 2
PQ22
AON7408L_DFN8-5
3 5
2
4
1
G
D
S
PQ38
SSM3K7002FU_SC70-3
2
13
PC52
10U_1206_25V6M
12
PC51
2200P_0402_50V7K
12
G
D
S
PQ37
SSM3K7002FU_SC70-3
2
13
PU6
RT8205EGQW_WQFN24_4X4
FB1 2
REF 3
VO1 24
ENTRIP1 1
TONSEL 4
FB2 5
SKIPSEL
14
NC
18
VREG5
17
VO2
7
VREG3
8
VIN
16
GND
15
UGATE1 21
BOOT1 22
ENTRIP2 6
PGOOD 23
PHASE1 20
LGATE1 19
EN
13
BOOT2
9
UGATE2
10
PHASE2
11
LGATE2
12
P PAD
25
PR86
13K_0402_1%
1 2
PC48
1U_0603_10V6K
12
PL6
4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2
PC50
10U_1206_25V6M
12
PC55
.1U_0402_16V7K
1 2
PC60
4.7U_0805_10V6K
12
PR92
2.2_0603_1%
1 2
PC61
0.1U_0603_25V7K
12
PR93
2.2_0603_1%
1 2
PC66
.1U_0402_16V7K
12
PC63
680P_0603_50V8J
12
PR88
20K_0402_1%
1 2
PL7
4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2
PQ23
AON7702L_DFN8-5
4
5
1
2
3
PR96
0_0402_5%@
1 2
PR90
121K_0402_1%
1 2
G
D
S
PQ36
SSM3K7002FU_SC70-3
2
13
PQ21
AON7408L_DFN8-5
3 5
2
4
1
PR84
4.7_1206_5%
12
PC53
4.7U_0805_10V6K
12
PR94
499K_0402_1%
1 2
PR85
42.2K_0402_1%
12
+
PC58
150U_V_6.3VM_R18
1
2
PC67
1U_0402_6.3V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LX_1.1V
DH_1.1V
1.1V_B+
BST_1.1V
DL_NB_CORE
LX_NB_CORE
DH_NB_CORE
NB_CORE_B+
BST_NB_CORE
DL_1.1V
POK36,38
VLDT_EN31,34
+5V_ALW
+1.1VALWP
+5V_ALW
B+
+5V_ALW
+NB_COREP
+5V_ALW
B+
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
+1.1VALWP/+NB_COREP
39 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
Imax = 3.22A
F = 314kHz
ESR = 8.5m Ohm
Total Capacitor = 550 uF
Ipeak = 4.6A
Imax = 5.32A
F = 315kHz
ESR = 5.63m Ohm
Total Capacitor = 550 uF
Ipeak = 7.6A
PC89
4.7U_0603_6.3V6K
12
PQ26
AO4466_SO8
3 6
5
7
8
2
4
1
PC90
0.1U_0603_25V7K
1 2
PC95
4.7U_0805_25V6-K
12
PL8
HCB2012KF-121T50_0805
12
+
PC74
220U_6.3V_M
1
2
PC77
680P_0603_50V7K
12
PC73
0.1U_0603_25V7K
1 2
PR122
13.7K_0402_1%
1 2
PR106
100_0603_1%
1 2
PQ40
AON7702L_DFN8-5
4
5
1
2
3
PL16
HCB2012KF-121T50_0805
12
PU7
RT8209BGQW_WQFN14_3P5X3P5
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PC124
4.7U_0805_10V6K
12
PR107
9.1K_0402_1%
1 2
PU14
RT8209BGQW_WQFN14_3P5X3P5
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PR103
0_0402_5%
1 2
PR119
10K_0402_1%
12
PR108
4.7K_0402_1%
1 2
PL15
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1 2
PR102
255K_0402_1%
1 2
PQ39
AON7408L_DFN8-5
3 5
2
4
1
PC125
.1U_0402_16V7K
@
12
PC70
4.7U_0805_25V6-K
12
PC93
4.7U_0805_25V6-K
12
PC71
4.7U_0805_25V6-K
12
PR142
100_0603_1%
1 2
PR166
2.7K_0402_1%
1 2
PR123
0_0402_5%
1 2
PR120
2.2_0603_5%
1 2
PC75
4.7U_0603_6.3V6K
12
PR109
10K_0402_1%
12
PR165
255K_0402_1%
1 2
PR105
4.7_1206_5%
12
PR161
4.7_1206_5%
12
+
PC94
220U_D2_4VM
1
2
PL9
1.8UH_1164AY-1R8N=P3_9.5A_30%
1 2
PC85
680P_0603_50V7K
12
PR104
2.2_0603_5%
1 2
PQ27
AO4712_SO8
3 6
5
7
8
2
4
1
PC76
4.7U_0805_10V6K
12
PC72
.1U_0402_16V7K
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DL_1.5VP
LX_1.5VP
DH_1.5VP
1.5V_B+
BST_1.5VP
SYSON31,34
+5V_ALW
+1.5VP
+5V_ALW
B+
+2.5VSP
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
1.5VP/2.5VSP
40 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
Imax = 5.6A
F = 313kHz
ESR = 5.67m Ohm
Total Capacitor = 880 uF
Ipeak = 8A
PL10
HCB2012KF-121T50_0805
12
PQ29
AO4712_SO8
3 6
5
7
8
2
4
1
PR113
4.7_1206_5%
12
PC88
4.7U_0805_6.3V6K
12
PC81
0.1U_0603_25V7K
1 2
PJ11
JUMP_43X39@
1
122
PC84
680P_0603_50V7K
12
PR114
100_0603_1%
1 2
+
PC82
220U_6.3V_M
1
2
PC87
1U_0603_10V6K
12
PQ28
AO4466_SO8
3 6
5
7
8
2
4
1
PR116
10K_0402_1%
1 2
PR110
255K_0402_1%
1 2
PC79
4.7U_0805_25V6-K
12
+
PC128
47U_25V_M
1
2
PC78
4.7U_0805_25V6-K
12
PR111
0_0402_5%
1 2
PC57
1U_0603_25V6K
@
12
PU9
APL5508-25DC-TRL_SOT89-3
IN
2
GND
1
OUT 3
PR117
10K_0402_1%
12
PR115
15.4K_0402_1%
1 2
PC83
4.7U_0603_6.3V6K
12
PU8
RT8209BGQW_WQFN14_3P5X3P5
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PC86
4.7U_0805_10V6K
12
PL11
1.8UH_1164AY-1R8N=P3_9.5A_30%
1 2
PC80
.1U_0402_16V7K
@
12
PR112
2.2_0603_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VR_ON#34
SUSP34
SUSP# 26,28,31,34,37
+1.5V
+3V_ALW
+0.9VP
+0.75VSP
+5V_ALW
+1.5V
+5V_ALW
+1.8VSP
+1.8VSP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
0.75VSP/0.9VP/1.8VSP
41 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
Imax = 0.91A
ESR = 2.5m Ohm
Total Capacitor = 44 uF
Ipeak = 1.3A
PC99
4.7U_0805_6.3V6K
12
PC141
10U_0805_10V4Z
12
PR118
1K_0402_1%
12
PU10
G2992F1U_SO8
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
PC143
680P_0603_50V7K
12
PC101
.1U_0402_16V7K
12
PR127
1.5K_0402_1%
12
PR182
4.7_1206_5%
12
PC102
.1U_0402_16V7K
@
12
PJ16
JUMP_43X79
@
1
122
G
D
S
PQ31
SSM3K7002FU_SC70-3
2
13
PJ13
JUMP_43X79
@
11
2
2
PC97
0.1U_0402_10V7K
12
PJ14
JUMP_43X79@
11
2
2
PC138
0.22U_0402_10V4Z
12
PC91
4.7U_0805_6.3V6K
12
PC92
1U_0603_10V6K
12
PR121
300K_0402_1%
PC98
10U_0805_6.3V6M
12
PC96
0.22U_0402_10V4Z
12
PU12
G2992F1U_SO8
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
PR178
200K_0402_1%
1 2
PC103
10U_0805_6.3V6M
12
PC145
22U_0805_6.3V6M
12
PU11
MP2121DQ-LF-Z_QFN10_3X3
SW
3
GND
2
IN 7
GND 9
SW 8
POK 6
EN/SYNC 10
BS
5
IN
4
FB
1
TP 11
PD15
B340A_SMA2
@
12
PC140
0.1U_0402_25V6
12
PC139
.1U_0402_16V7K
1 2
G
D
S
PQ30
SSM3K7002FU_SC70-3
2
13
PC100
1U_0603_6.3V6M
12
PR124
1K_0402_1%
12
PR125
1K_0402_1%
12
PR180
402K_0402_1%
12
PL17
2.2UH_SILM320A-2R2_1.6A_30%
1 2
PR181
0_0402_5%
1 2
PC144
22U_0805_6.3V6M
12
PR179
316K_0402_1%
1 2
PC142
10U_0805_10V4Z
1 2
PR126
0_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
COMP0
UGATE_NB
+CPU_CORE_0
PHASE_NB
LGATE_NB
BOOT_NB
+VDDNBP
PHASE0
ISP0
UGATE0
UGATE_NB
LGATE_NB
DIFF_0
BOOT0
UGATE0
PHASE0
LGATE0
PHASE_NB
ISL6265_PWROK
VSEN0
BOOT0
ISN0
LGATE0
ISP0
ISN0
BOOT_NB
FB_0
PHASE_NB
RTN0
VW0
VSEN1
VSEN1
ISN0
ISP0
CPU_VDDNB_RUN_FB_H 7
CPU_VDD0_RUN_FB_H7
CPU_VDD0_RUN_FB_L7
CPU_SVD7
CPU_SVC7
VR_ON31,34
VGATE31,34
H_PWRGD7,20
H_PWRGD_L20
+CPU_CORE_0
CPU_B+
+VDDNBP
CPU_B+
CPU_B+
+5VS +3VS
B+
+5VS
+5VS
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA6032P
1.0
+CPU_CORE
Custom
42 45Tuesday, March 23, 2010
2009/10/02 2010/10/02
Compal Electronics, Inc.
PR131
2.2_0603_1%
1 2
PQ33
AO4712_SO8
3 6
5
7
8
2
4
1
PR163
54.9K_0402_1%
12
PR155
0_0402_5%
1 2
PR140
105K_0402_1%
12
PR129
2_0603_5%
1 2
PC117
680P_0603_50V7K
12
PR160
255_0402_1%
12
PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
3
4
2
PR135
0_0402_5%
12
PR159
1K_0402_5%
@
12
PC116
0.22U_0603_10V7K
1 2
PR132
4.7_1206_5%
12
PR130
22K_0402_1%
12
PR143
105K_0402_1%
@
12
PR148
4.7_1206_5%
12
PR138
105K_0402_1%
@
12
PR164
6.81K_0402_1%
12
+
PC111
220U_D2_4VM
1
2
PC115
10U_1206_25V6M
12
PR144 100K_0402_5%
1 2
PR145
2.2_0603_1%
1 2
PC119
1U_0603_16V6K
12
PC106
10U_1206_25V6M
12
PC109
0.1U_0603_16V7K
12
PR146 100K_0402_5%@
1 2
PC126
1200P_0402_50V7K
12
PC104
33P_0402_50V8J
12
PC118
0.1U_0603_16V7K
12
PQ35
TPCA8028-H_SOP-ADVANCE8-5
4
1
2
3 5
PR154
10_0402_5%
12
PU13
ISL6265AHRTZ-T_TQFN48_6X6
PWROK
3
SVD
4
OFS/VFIXEN
1
PGOOD
2
SVC
5
ENABLE
6
OCSET
8
VDIFF1
19
RTN1
17
VSEN0
15
VW1
22
RTN0
16
ISN0
14
VW0
12
COMP0
11
RBIAS
7
FB0
10
COMP1
21
ISP1
23
FB1
20
VSEN1
18
VDIFF0
9
ISN1
24
ISP0
13
BOOT1 25
UGATE1 26
PHASE1 27
PGND1 28
LGATE1 29
PVCC 30
LGATE0 31
PGND0 32
PHASE0 33
UGATE0 34
BOOT0 35
BOOT_NB 36
UGATE_NB 37
PHASE_NB 38
LGATE_NB 39
PGND_NB 40
OCSET_NB 41
RTN_NB 42
VSEN_NB 43
FSET_NB 44
COMP_NB 45
FB_NB 46
VCC 47
VIN 48
TP
49
PR150
0_0402_5%
12
PR153
4.53K_0402_1%
12
PC112
680P_0603_50V7K
12
PR141
10K_0402_1%
@
12
PR152
95.3K_0402_1%
12
PR139
0_0402_5%
12
PR128
44.2K_0402_1%
12
PC121
180P_0402_50V8J
12
PC110
0.22U_0603_10V7K
1 2
PR137
0_0402_5%
12
PL12
HCB2012KF-121T50_0805
12
PR134
2_0603_5%
1 2
PL13
4.7UH_SIQB74B-4R7PF_4A_20%
1 2
PR168
36.5K_0402_1%
@
12
PC122
1000P_0402_50V7K
12
PC108
1000P_0402_50V7K
12
PR156
0_0402_5%
12
PQ34
TPCA8030-H_SOP-ADV8-5
4
5
1
2
3
PC120
4700P_0402_25V7K
12
PR162
1K_0402_5%
12
PR149
12.7K_0402_1%
1 2
+
PC107
47U_25V_M
1
2
PR133
10_0402_5%
@
1 2
PR147
0_0402_5%
12
PR136
5.49K_0402_1%
12
PC113
0.1U_0603_25V7K
12
PQ32
AO4466_SO8
3 6
5
7
8
2
4
1
PR157
0_0402_5%
12
+
PC123
47U_25V_M
@
1
2
PC114
10U_1206_25V6M
12
PR151
21.5K_0402_1%
12
PR158
10_0402_5%
1 2
PC105
1000P_0402_50V7K
12
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Compal Electronics, Inc.
LA6032P
1.0
Power PIR
Custom
43 45
Tuesday, March 23, 2010
2009/10/02 2010/10/02
Version Change List ( P. I. R. List ) for Power Circuit
Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit
Version Change List ( P. I. R. List ) for Power Circuit
Page#
Page#Page#
Page#
Title
TitleTitle
Title
Issue Description
Issue DescriptionIssue Description
Issue Description
Request
RequestRequest
Request
Owner
OwnerOwner
Owner
Date
DateDate
Date
Solution Description
Solution DescriptionSolution Description
Solution Description
POWER Release2009/11/10
2009/12/03
2009/12/03
2009/12/03
2009/12/03
2009/12/03
POWER
POWER
POWER
POWER
POWER
P38 BATTERY CONN / OTP
P38 BATTERY CONN / OTP
P38 BATTERY CONN / OTP
P38 BATTERY CONN / OTP
PR121 change to 300k
PC96 change to 0.22uf
DVT
DVT
DVT
DVT
DVT
PR125 change to 1k
PR127 change to 1.5k
Delete PR142
2009/12/03
2009/12/03
2009/12/03
2009/12/03
POWER
POWER
POWER
POWER
0.75VSP/0.9VP/1.8VSP
0.75VSP/0.9VP/1.8VSPP43
P43
0.75VSP/0.9VP/1.8VSP
0.75VSP/0.9VP/1.8VSPP43
P43
+CPU_COREP44
DVT
DVT
DVT
DVT
PR31 change to 34.8k
PR32 change to 15.4k
PR37 change to 22k
PR38 change to 10.2k
CHARGERP39 2009/12/03 POWER DVTPC24,25,26 size change to 4.7uf 0805
DVTPR131, PR145 change to 2.2 ohm2009/12/03 POWER+CPU_COREP44
DVTPR132 change to 4.7_1206_5%2009/12/03 POWER+CPU_COREP44
DVTPC112 change to 680P_0603_50V7K2009/12/03 POWER+CPU_COREP44
CHARGERP39 2010/01/29 POWER PVTAdd PC47,68,69,127 10U_1206_25V6M
PVTAdd PC70 4.7U_0805_25V6-KPOWERP41
PVTPL9 change to 1.8UH_9.5A_30%POWER+1.1VALWP/+NB_COREPP41
2010/02/03
2010/02/03
+1.1VALWP/+NB_COREP
PVTPL13 change to 4.7UH_4A_20%2009/12/03 POWER+CPU_COREP44
PVT2Move PR18,PR19 to connect PBJ12009/02/08 POWERCHARGERP37
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
EE change list-1
Custom
44 45Tuesday, March 23, 2010
2005/03/10 2006/03/10
Compal Electronics, Inc.
EVT to DVT Version change list (P.I.R. List) Page 1 of 2
Item Reason for change PG# Modify List Date Phase
1Update JSATA1, JHDMI1 and JREAD1 footprint ME request
2
3
R41~R44 SMT-->@4
5
6
7
EVT->DVT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
49
50
51
52
Update DDR_CS0_DIMMB#, DDR_CS1_DIMMB# net P06
Update DDR_CKE0_DIMMA, DDR_CKE1_DIMMA net P06
Net contact error on DIMMB
Net contact error on DIMMA
P07 Fine tune HDT debug pull high R
Del R46 and add R850~R854 P07 For ESD request
Add RS15 RS16 for NBGFX_CLK,NBGFX_CLK# P12 For internal clock gen
Fine tune RS880M clock P12 For internal clock gen
Del external clock gen P16 For internal clock gen
Fine tune pin define JP4 Pin1 Pin2 Pin8-->GND P17 Add more GND pin
Add R855 R856 for HDMI_SDATA,HDMI_SCLK pull high R Solve HDMI can not detect
U6 pin5 +5VL-->+5VS and HDMI Dual NMOSx2(Q6 Q7)->Single NMOS (Q6)
P19
P19 Cost down plan
Add RS1~RS14 near SB820M and TP34 TP35 P20 For internal clock gen
C640 @-->22P on CLK_PCI_EC P20 EMI request
C705 C705 @-->SMT on Y6 P20
R152 R153 R154 pull +3VALW-->pull GND P21 Follow AMD check list 1.03
Add device clock request pin on SB820M P21 For internal clock gen
C632 @-->33P on AZ_BITCLK_HD P21 EMI request
Add WLAN_PWR_EN# and WWAN_PWR_EN# net on SB820M
U47 +3VL-->+3VALW and Y3 R164 C246 C247 SMT->@
P22
P22
Power saving request
25MHz by default
Reaserved R859 C707 on CLK net P22 EMI request
Fine tune SB820M strap pin P24 For internal clock gen
Add C706 0.1u on CLK_PCI_EC P24 EMI request
Del R193 and Add R858 PH on USB_OC#2 P25 Solve the USB hang up issue
Reserved RM5 RM6 CM17 QM1 RM9 for +3V_WWAN power saving
Reserved RM7 RM8 CM18 QM2 RM10 for +3V_WLAN power saving
Reserved CM19 QM3 RM11 for +1.5V_WLAN power saving
RL21 pin2 +3V_LAN-->GND
Del RA4 RA5
P26
P26
P26
P27
Power saving request
Power saving request
Power saving request
LAN vender request
Reserved RA27 CA26 on AZ_RST_HD#
Add Q37 R860 R861 and PD# net
P28 Fine tune Audio HP out voltage
P28
P28
ESD request
Solve Audio PD# control issue
Fine tune JP5 pin define
Fine tune SPK_L1,SPK_L2,SPK_R1 and SPK_R2 for SPK
Add R857 PH USB_OC#0 net
Add C708 on +5VS
Fine tune card reader pin define
Add EC_MUTE# on KBC926 (U12) 83pin
P29
P29
Solve the USB hnag up issue
Solve SPK pin issue
P29 Solve the USB hnag up issue
P29 ESD request
P30 ME use new card reader connector
P31 Solve Audio PD# control issue
Q8 Q9 R258 R259-->@, R790 R791-->SMT P33 Cost down plan
C386 @-->0.1u on ON/OFFBTN# P33 EMI request
C410 0.01u_0402_16V-->0.1u_0603_25V and R267 330k->1M P34 SMT memo
SYSON#-->SUSP on Q26 Pin2 P34 +0.75VS discharge control pin
RA26 0ohm-->Bead (SM010017710) on INT_MIC_CLK P28 EMI request
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12
2009/12/18
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
C632 @-->33P on AZ_BITCLK_HD P21 EMI request
R788 @-->100ohm and C634 @-->100P on SPI_CLK
R789 @-->100ohm and C635 @-->100P on AZ_BITCLK_HD
Add CA63 on INT_MIC_CLK_R
RA1 0ohm-->Bead on Audio power
P32 RF request
P28 RF request
P28 RF request
P28 RF request
Add CM20 1000P on +3V_WWAN P26 RF request
2009/12/18
2009/12/18
2009/12/18
2009/12/18
2009/12/18
2009/12/18
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
EVT->DVT
Fine tune R133 R value 11.8K-->8.2K P21 2009/12/22Fine tune USB signal EVT->DVT
Add C709 on 27M_SEL P16 RF request (EXT only)49 2009/12/19 EVT->DVT
<BOM>RA22 RA25 4.7K-->2.2K and CA16 10u-->@ P28 Audio vender request 2009/12/22 EVT->DVT
53
Add BT_PWR# net contact to JWLAN1 pin5
Del R161 and SLP_CHG on SB
Add SLP_CHG on pin115 and add R862
P26 Follow common design
P22 Follow common design
P31 Follow common design
2009/12/23
2009/12/23
2009/12/23
EVT->DVT
EVT->DVT
EVT->DVT
54
55
56
Add UA2 CA67 CA68 CA69 P28 Audio power reserved 2009/12/23 EVT->DVT
57
Add F2 for card reader proetct
Reserved RA28 CA70
Add R863 PH on CIR_EN#
P30 H/W request 2009/12/24 EVT->DVT
P28 Reserved for fin tune aduio power control
P21 Follow common design
2009/12/24
2009/12/24
EVT->DVT
EVT->DVT
58 Add R864 on LID_SW# P33 Reserved for ESD protect 2009/12/24 EVT->DVT
59 Modify TP26 TP27-->EVENT#_A and EVENT#_B
P09 P10
Solve layout test point issue 2009/12/25 EVT->DVT
60 C497 SMT-->@ P08 Fine tune CPU_CORE cap 2009/12/25 EVT->DVT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
EE change list-2
Custom
45 45Tuesday, March 23, 2010
2005/03/10 2006/03/10
Compal Electronics, Inc.
DVT to PVT Version change list (P.I.R. List) Page 2 of 2
Item Reason for change PG# Modify List Date Phase
1Follow common design
2
3
4
5
6
7
DVT->PVT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
49
50
51
52
P26 2010/1/20
49
53
54
55
56
57
58
59
60
Add D17 and Q38 for BT power control
Change net name SLP_CHG-->SLP_CHG#
Need to fine tune R783 and R784
<BOM> SB use 2MB SPI ROM SA00002TO00
<BOM> Update LAN P/N for LAN VB P/N
P25 P31
P18
P22
P27
Follow net rule
VB function
Non share ROM
Vender update P/N
<BOM> EC SPI use 256KB SPI ROM SA00003GK00
BT part SMT-->@
Update JREAD1 footprint (Same as EVT)t
Update JSATA1 footprint TAIWI_EU114-117CRL-TW_11P-T
Update JHDD1 pin4 +5VS-->GND
Del DC to DC +NB_CORE part
Change USB port10 to USB port5 on WWAN
Add R865 R866 for SLP_CHGX_M3/M4 on SB
Add R867 R868 for SLP_CHGM3/M4 on EC
UA2 pin5 +PVDD1--->+AVDD
P32 Non share ROM
P29 IUR no BT device
P30 ME request
P25 ME request
P25 HW request
P34 HW request
P21 Follow common design
P21
P31
Follow common design
Follow common design
P28 Reserved for Audio analog power
<BOM> U48 SA000008G00-->SA00003DR00 (Same as intel)
Del R164 Y3 C246 C247 and add TP36 TP37
JLVDS1 pin24 +LCD_INV-->NG
U9 pin1 +5VALW-->+5V_ALW for USB charge
Add C900~C908,R900~R906 Q40 Q41 U49 U50 for power save
Update JTP1 footprint--> E-T_6916-Q06N-00R_6P
Update USB20_P10-->USB20_P5 ,USB20_N10-->USB20_N5
Update JHDMI1footprint-->SUYIN_100042GR019M23BZR_19P-T
R900 pin 1 and R904 pin1 +B-->+VSB
Add J2 J3 for +3V_ALW and +5V_ALW
P29 HW request
P22 HW request
P18 Follow common design
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/20
2010/1/22
2010/1/22
2010/1/21
2010/1/21
2010/1/21
P25
P34
P33
P21 P26
P19
P34
P34
Follow common design
Follow common design
2010/1/22
2010/1/22
ME request
Follow common design
ME request
2010/1/25
2010/1/25
2010/1/25
HW request
HW request
2010/1/27
2010/1/27
R808 pin 1,R809 pin2 +3VALW-->+3V_ALW and +5VALW-->+5V_ALW
Add R907 for USB_EN# PH
Del R808 R809 R811 R810 R258 Q8 R259 Q9
R238 pin1 +3VALW-->+3V_ALW
JTP1 pin1 +3VALW-->+3V_ALW
Del R246
Add LPC_FRAME#, LPC_AD, LPC_AD1,LPC_AD2,LPC_AD3 JWAN1
Update JPB1 footprint P-TWO_161011-04021_4P-T
Add JHDD2 ACES_87036-1001-CP_10P
Fine tune JP4 pin define for EMI request
<BOM> Update UA1 P/N for Audio VB version
Update JP5 pin define and 20pin-->22pin
P33
P29
HW request
P33
HW request
HW request
2010/1/27
2010/1/27
2010/1/27
P31
P33 Follow common design
HW request
P32 HW request
P26 HW request
P33 ME request
P25
P17 EMI request
HW request
P28 Vender update P/N
P29 HW request
2010/1/29
2010/1/29
2010/1/29
2010/1/29
2010/1/29
2010/1/29
2010/1/29
2010/1/29
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT2010/1/30
<BOM> R133 8.2K-->11.8K same as EVT P21 HW request 2010/1/31 DVT->PVT
Add C909 C910
Add D18 and R908 on RTC circuit
JHDD1 10pin-->12pin
Add R909 R910 for ADAPTOR_SEL
Add L41 L42 L43 C911 C912 C913 for EMI request
C240 C244 22P to 18P
P17 EMI request
P20 Follow common design
P29 Add more power and GND pin on HDD conn
P31 Follow common design
P12 EMI request
P20 Solve RTC fial issue
2010/1/31
2010/1/31
2010/1/31
2010/1/31
2010/2/2
2010/2/2
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
DVT->PVT
