Compal LA 6032P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-6032P NDU01, NDU11 - Schematics. Free.

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Compal confidential
Thin & Light

2

2

NDU01/NDU11 LA-6032P REV 1.0 Schematics Document
Mobile AMD ASB2/RS880M/SB820M
2010-03-22 Rev. 1.0
3

3

4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
Cover Sheet

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

1

of

45

A

B

C

D

E

Thermal Sensor

Compal Confidential

Fan Control

Memory BUS(DDRIII)

AMD ASB2 CPU

page 5

Model Name : NDU01(11.3)-S/NDU11(13.6)-M

Dual Channel

BGA-812 Package

File Name : LA-6032P

ADM1032ARMZ

1.5V DDRIII 800MHZ

Clock Generator

page 7

SLG8SP626

page 16

200pin DDRIII-SO-DIMM X2

page 5,6,7,8

page 9,10

BANK 0, 1, 2, 3

Hyper Transport Link 2.6GHz
16X16

1

CRT

1

FUJIN OZ600FJ1
5IN1

ATI

page 17

LCD Conn.

RS880M

page 18

PCIeMini Card
WLAN (Slot 1)

PCIe 4x

USB Port 8

1.5V 2.5GHz(250MB/s)

HDMI Conn.

5IN1

page 30

page 30

PCIe port 1

PCIe Port 2
page 26

RTL8105E
LAN 10/100M

page 19

RJ45

page 17

page 27

PCIe port 3
page 11,12,13,14,15

2

PCIeMini Card
WWAN / 3G (Slot2)

A-Link Express II
4X PCI-E

2

USB Port 10 for 3G card
page 26

USB/B Right
USB port 0,1
page 29

BT conn

Int. Camera

USB port 6

USB port 9

page 29

SATA port 0

ATI

USB
5V 480MHz

5V 1.5GHz(150MB/s)

SATA HDD0

page 25

SB820M

page 18

SATA port 3
5V 1.5GHz(150MB/s)

USB port 2
5V 480MHz

page 20,21,22,23,24

eSATA
page 25

SPI ROM

3

3

page 34

HD Audio

RTC CKT.
page 20

Power On/Off CKT.

LPC BUS

Right USB&Audio/B
LS-6031P page 29
RJ45&VGA/B
LS-6032P page

3.3V 24.576MHz/48Mhz

3.3V 33 MHz

HDA Codec
ALC259Q

Debug Port

page 28

ENE KB926 D3

page 32

page 31

17

page 33

DC/DC Interface CKT.
page 34

Power Circuit DC/DC
4

page 37,38,39.40
41,42,43,44

HD/B
LS-6033P

page 25

LED/B
LS-6034P

page 33

Touch Pad BTN/B
LS-6035P(13.3) page
PWR BTN
LS-6036P

Int.KBD

SPI ROM

page 32

33

Touch Pad BTN/B
LS-6037P(11.6) page

page 32

EC
SMBUS

33

Int.
MIC CONN
page 18

GSENSOR

page 32

MIC CONN
page 29

HP CONN
page 29

G-Sensor Controller
4

R5F211B4D34SP
page 32

page 33
Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

SPK CONN
page 29

B

C

D

Block Diagram
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

2

of

45

A

B

C

DESIGN CURRENT 0.1A

DESIGN CURRENT 4.5A

+3VL
+5VL
+5VALW

DESIGN CURRENT 2A

+5VS

DESIGN CURRENT 0.1A

B+

D

E

SUSP

N-CHANNEL
SI4800BDY
+5VS
1

DESIGN CURRENT 300mA

LDO
G9191

1

+3VS_HDP

SUSP#
DESIGN CURRENT 1.5A

+1.8VS

DESIGN CURRENT 1A

+3VALW

MP2121DQ

TPS51125RGER

SUSP

N-CHANNEL

DESIGN CURRENT 4A

+3VS

DESIGN CURRENT 1.0A

+LCD_VDD

DESIGN CURRENT 180mA

+BT_VCC

SI4800BDY
ENVDD

P-CHANNEL
AO-3413
BT_PWR#

P-CHANNEL
AO-3413
2

2

WOL_EN#
DESIGN CURRENT 500mA

+3V_LAN

DESIGN CURRENT 300mA

+2.5VS

DESIGN CURRENT 0.3A

+1.1VALW

DESIGN CURRENT 6.5A

+1.1VS

DESIGN CURRENT 7.6A

+NB_CORE

DESIGN CURRENT 15A

+CPU_CORE0

DESIGN CURRENT 2A

+VDDNB

DESIGN CURRENT 7A

+1.5V

DESIGN CURRENT 1A

+1.5VS

DESIGN CURRENT 0.5A

+0.75VS

DESIGN CURRENT 1.5A

+0.9V

P-CHANNEL
AO-3413

LDO
APL5508

POK

RT8209BGQW

VGATE#

N-CHANNEL
IRF8113PBF
VLDT_EN#

N-CHANNEL
IRF8113PBF
3

3

VR_ON

ISL6265
SYSON

SUSP

RT8209BGQW

N-CHANNEL
IRF8113PBF
SUSP

LDO
G2992F1U
VR_ON#

LDO
G2992F1U
4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
Power Map

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-5381P
Sheet

Tuesday, March 23, 2010
E

3

of

45

A

B

C

D

E

For 11.6 and 13.3 DAZ

Symbol Note :
O MEANS ON

Voltage Rails

ZZZ

X MEANS OFF

: means Digital Ground

: means Analog Ground
PCB-MB

+5VS
1

+3VS
power
plane

+2.5VS
+1.8VS
+1.5VS
+1.1VS
B+

+5VALW

+1.5V
+0.9VS

+3VL

+3VALW

+5VL

+1.1VALW

+0.75VS
+NB_CORE

State
+VDDNB

+RTCVCC

+CPU_CORE_0

S0

O

O

O

O

S1

O

O

O

O

S3

O

O

O

X

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

2

S5 S4/AC

SB SM Bus1 Address

3

@ : means just reserve , no build
K625R3@ : means just for 1.5G CPU
K125R3@ : means just for 1.7G CPU
K325R3@ : means just for 1.3G CPU
K625R1@ : means just for 1.5G CPU
K125R1@ : means just for 1.7G CPU
K325R1@ : means just for 1.3G CPU
M@ : means just reserve for 13.3 control
S@ : means just reserve for 11.6 control
GSENSOR@ : means just reserve for G sensor part
1ST@ : means just reserve 1st G sensor IC
1STGSENSOR@ : means just reserve 1st G sensor IC
2ND@ : means just reserve 2nd G sensor IC
2NDGSENSOR@ : means just reserve 2nd G sensor IC
NOSIDE@ : means just reserve NOSIDE
SIDE@ : means just reserve SIDE port
RS880MR1@ : means just for RS880MR1
RS880MR3@ : means just for RS880MR3
SB820MR1@ : means just for SB820MR1
SB820MR3@ : means just for SB820MR3

U1
K125R1@
K125 CPU

K625 mean 1.7G CPU

Device

HEX

Address

Power

Device

+3VS

DDR SO-DIMM 0

A0 H

1010 0000 b

+3VALW

WLAN/WIMAX

+3VS

DDR SO-DIMM 1

A4 H

1010 0100 b

+3VS

Clock Generator

D2 H

1101 0010 b

HEX

EC_SMB_CK2

EC SM Bus1 Address

EC SM Bus2 Address

EC_SMB_DA2
I2C_CLK

16 H

Address
0001 011X b

Power

Device

HEX

+3VS

CPU_ADM1032-1

+3VS

G-Sensor

98 H

I2C_DATA

Address

DDC_CLK0

1001 100X b

DDC_DATA0
SCL0

4

2

BATT

CPU
THERMAL

SCL1

SODIMM
I / II

CLK
GEN

WLAN

2008/04/14

RS880M

V

RS880M

V
V

V

4

V
2009/04/14

Deciphered Date

Title

Date:

C

G-sensor

V

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

HDMI
DDC
ROM

V

Compal Secret Data

Security Classification

LCD
DDC
ROM

V

KB926

SB820

SDA1

Issued Date

KB926

SB820

SDA0

A

U7
SB820MR3@
SB820M

SMBUS Control Table

EC_SMB_DA1

Smart Battery

SB820M

U5
RS880MR3@
RS880M

3

EC_SMB_CK1

+3VL

U1
K325R3@
K325 CPU

RS880M

SENSOR

HEX

K325 mean 1.3G CPU

U1
K125R3@
K125 CPU

Address

SOURCE

Device

K125 mean 1.7G CPU

U1
K625R3@
K125 CPU

1

U1
K325R1@
K325 CPU

SB SM Bus2 Address

Power

Power

K325 mean 1.3G CPU

K125 mean 1.7G CPU

D

Notes List
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

4

of

45

A

B

C

D

E

1

1

11 H_CADIP[0..15]
11 H_CADIN[0..15]

H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15]

11

H_CADON[0..15]

11

2

2

11
11

H_CLKIP0
H_CLKIN0

11
11

H_CTLIP1
H_CTLIN1

11
11

H_CTLIP0
H_CTLIN0

H_CLKIP0
H_CLKIN0

M3
M4

H_CTLIP1
H_CTLIN1

Y6
Y5

H_CTLIP0
H_CTLIN0

V2
V1

L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CLKIN_H0
L0_CLKIN_L0

L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H1
L0_CTLOUT_L1

L0_CTLIN_H0
L0_CTLIN_L0

L0_CTLOUT_H0
L0_CTLOUT_L0

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

FAN Control Circuit
+5VS

1A

H_CLKOP1 11
H_CLKON1 11

AD1 H_CLKOP0
AD2 H_CLKON0

H_CLKOP0 11
H_CLKON0 11

H_CTLOP1
H_CTLON1

V4
V3

H_CTLOP0
H_CTLON0

C1
10U_0805_10V6K

@
1SS355_SOD323-2
D1

2

AF6 H_CLKOP1
AF5 H_CLKON1

Y8
Y9

3

1

AB6
AB5
AB9
AB8
AC7
AC6
AE6
AE5
AE9
AE8
AH3
AH4
AK3
AK4
AH1
AH2
Y1
Y2
Y4
Y3
AB1
AB2
AB4
AB3
AD4
AD3
AF1
AF2
AF4
AF3
AK1
AK2

JFAN1 @

2

H_CLKIP1
H_CLKIN1

M8
M7

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

+FAN1

1

1
2
3

1

11
11

H_CLKIP1
H_CLKIN1

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

@

U2

H_CTLOP1 11
H_CTLON1 11

1
2
3
4

+FAN1
31 EN_DFAN1

H_CTLOP0 11
H_CTLON0 11

1

2

EN
VIN
VOUT
VSET

GND
GND
GND
GND

8
7
6
5

2

3

W7
W6
U6
U5
R7
R6
P6
P5
L6
L5
J6
J5
H4
H3
G6
G5
T3
T4
T2
T1
P3
P4
P2
P1
M2
M1
K3
K4
K2
K1
H2
H1

HT LINK

U1A
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

2

C2
1000P_0402_50V7K
D2
@
1
1SS355_SOD323-2

4
5

1
2
3
GND
GND

ACES_88231-03041

APL5607KI-TRG_SO8
C3
10U_0805_10V6K

R1
2
1
10K_0402_5%

TMK625DBV23GM_FCBGA812
K625@

+3VS

FAN_SPEED1 31
2
@
1

C4
0.01U_0402_25V7K

4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 HT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

5

of

45

A

B

C

D

E

1

10
10
10

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

R33
AD33
AE33
K33
K31
G32
F32
L33
K32
H31
G33

2

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

10
10
10
10

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

10 DDR_CKE1_DIMMB
10 DDR_CKE0_DIMMB

3

J33
H32
AM14
AN14
AL20
AM20
AN26
AM26
AN30
AM30
D33
D32
B28
A28
A21
B20
B16
A15
AN22
AM22
AN21
AM21
AA32
AA33
AB33
AB32
AB31
AB30
AD31
AD30
C22
B22
A22
A23
N33
P32

10 DDR_B_ODT1
10 DDR_B_ODT0

AK31
AH31
DDR_B_ODT1 AK32
DDR_B_ODT0 AH33

10 DDR_CS1_DIMMB#
10 DDR_CS0_DIMMB#

AK33
AF33
DDR_CS1_DIMMB# AJ32
DDR_CS0_DIMMB# AF31

10 DDR_B_RAS#
10 DDR_B_CAS#
10 DDR_B_WE#

DDR_B_RAS# AF32
DDR_B_CAS# AH32
DDR_B_WE# AG33

10 MEM_MB_RST#
+1.5V

L32
M33

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0

U1B

MB_DQS_H8
MB_DQS_L8
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_CKE1
MB_CKE0
MB1_ODT1
MB1_ODT0
MB0_ODT1
MB0_ODT0

AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14
H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_D[63..0]

9 DDR_A_MA[15..0]

10

9 DDR_A_BS#2
9 DDR_A_BS#1
9 DDR_A_BS#0

P30
M29
AG28
P28
T30
AC28
P27
R26
R27
U28
V30
U27
Y30
AB29
W29
AC26

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

R29
AC29
AE28
K30
J29
G29
F29
L28
L29
H29
H27

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

9 DDR_CKE1_DIMMA
9 DDR_CKE0_DIMMA

DDR_A_ODT1
DDR_A_ODT0

9 DDR_A_RAS#
9 DDR_A_CAS#
9 DDR_A_WE#

AJ29
AF27
AJ30
AG29

DDR_A_ODT1
DDR_A_ODT0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AC27
AF30
AE27
L27
M32

9 MEM_MA_RST#

K625@

M30
M28

AH29
AE29
DDR_CS1_DIMMA# AH30
DDR_CS0_DIMMA# AF29

9 DDR_CS1_DIMMA#
9 DDR_CS0_DIMMA#

MB_RAS_L
MB_CAS_L
MB_WE_L

AK18
AJ17
AH17
AG17
Y28
Y27
AB27
AB26
W27
W26
P26
M26
D18
F19
E20
E19

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_DM[7..0] 10

9
9

J27
J26
AJ11
AK12
AG15
AH15
AH22
AG22
AG26
AH26
E28
F28
E25
F25
G17
H17
E12
F12

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

9 DDR_A_CLK0
9 DDR_A_CLK#0
9 DDR_A_CLK1
9 DDR_A_CLK#1

MB1_CS_L1
MB1_CS_L0
MB0_CS_L1
MB0_CS_L0

MB_RESET_L
FREE|MB_EVENT_L

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0

DDR III: CHANNEL A

DDR_B_MA15
P33
DDR_B_MA14
P31
DDR_B_MA13 AJ33
DDR_B_MA12
T32
DDR_B_MA11
T31
DDR_B_MA10 AD32
DDR_B_MA9
T33
DDR_B_MA8
V32
DDR_B_MA7
U33
DDR_B_MA6
V33
DDR_B_MA5
V31
DDR_B_MA4
W33
DDR_B_MA3
Y31
DDR_B_MA2
Y33
DDR_B_MA1
Y32
DDR_B_MA0
AC33

DDR III: CHANNEL B

U1C
10 DDR_B_MA[15..0]

MA_DQS_H8
MA_DQS_L8
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_CLK_H7
MA_CLK_L7
MA_CLK_H6
MA_CLK_L6
MA_CLK_H5
MA_CLK_L5
MA_CLK_H4
MA_CLK_L4
MA_CLK_H3
MA_CLK_L3
MA_CLK_H2
MA_CLK_L2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
MA_CKE1
MA_CKE0
MA1_ODT1
MA1_ODT0
MA0_ODT1
MA0_ODT0

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

DDR_A_D[63..0]

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

AG11
AH11
AJ12
AJ14
AF11
AF12
AG12
AH12
AK14
AF15
AH19
AK20
AF14
AG14
AF17
AG19
AG20
AJ20
AF22
AK24
AF19
AF20
AJ23
AG23
AF23
AF25
AH27
AK30
AJ25
AG25
AJ26
AJ28
D28
G28
D26
E26
F30
E29
F27
H26
H25
D24
H22
E22
F26
G26
D22
G23
G22
G20
G15
F15
D20
F22
D16
E17
H15
H14
G12
H12
E15
E14
E11
F11
H30
AL12
AK16
AK22
AJ27
E27
E23
H19
G14

9

1

2

DDR_A_DM[7..0] 9

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

3

MA1_CS_L1
MA1_CS_L0
MA0_CS_L1
MA0_CS_L0
MA_RAS_L
MA_CAS_L
MA_WE_L
MA_RESET_L
FREE|MA_EVENT_L

K625@

+1.5V
1
R792

MB_EVENT_L
2
1K_0402_5%

1
R793

TMK625DBV23GM_FCBGA812

MA_EVENT_L
2
1K_0402_5%

TMK625DBV23GM_FCBGA812

4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

6

of

45

A

B

C

D

E

1

+1.5V

100U_D2_10VM

2

C6

C7

2

2

1

2

2

CPU_THERMTRIP#_R
C8
0.22U_0603_16V4Z

D4
Q1
1

3

CH751H-40PT_SOD323-2

1

C

4.7U_0805_10V4Z

1

E

1

+ C5

@

+2.5VDDA@250mA

3300P_0402_50V7K

1
2
1 FBM_L11_201209_300L_0805

B

+2.5VS

2
10K_0402_5%
2
1K_0402_5%

R2
1
R3

+2.5VDDA
L1

2

H_THERMTRIP# 21

MMBT3904_NL_SOT23-3
1
R4

+1.5V

2
300_0402_5%
R5 @

1

CPU_PROCHOT#_1.8

U1D
A8
B8
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

1

20 CLK_CPU_BCLK

1

C10

H_PWRGD
LDT_STOP#
LDT_RST#

D10
E9
F9

CLKIN_H
CLKIN_L

RSVD|CORE_TYPE

PWROK
LDTSTOP_L
RESET_L

20 CLK_CPU_BCLK#

L

C9

R8 Close to CPU within 0.6"
C9 C10 Close to CPU within 1.2"

2

+1.5VS

R7 1
R10 1

+1.5V

2 1K_0402_5%CPU_SIC
2 1K_0402_5%CPU_SID

AN4
AN5
AM2
AN3

SIC
SID
RSVD_SA0
ALERT_L

CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS

AM8
AL8
AK8
AN8

TDI
TRST_L
TCK
TMS

+1.1VALW

1

R11
300_0402_5%

20

2
3900P_0402_50V7K

CPU_VLDT_SENSE

@
R355
+1.5V

10_0402_5%

LDT_RST#

LDT_RST#

CPU_VDDIO_SENSE

@
1

2

R356
C11
0.01U_0402_25V7K
@

42 CPU_VDD0_RUN_FB_L
42 CPU_VDD0_RUN_FB_H
42 CPU_VDDNB_RUN_FB_H

+0.9V

CPU_VDDR_SENSE

@
2

R357

CPU_DBREQ#

CPU_VDD0_RUN_FB_L D2
CPU_VLDT_SENSE
E2
CPU_VDD0_RUN_FB_H E1
CPU_VDDNB_RUN_FB_HD1
CPU_VDDIO_SENSE
D3
CPU_VDDR_SENSE
C2

10_0402_5%
M_VREF
M_ZP
M_ZN
1 R16
2
0.1U_0402_16V7K
39.2_0402_1~D
C12 @
1
2

Close to CPU within
1"

L

2

+1.5VS

1 R22
2
0_0402_5%
@ PAD T22
@ PAD T23

1

R17
300_0402_5%
H_PWRGD

20,42 H_PWRGD

@
@
@
@

1
C13
0.1U_0402_16V7K

2

G9

10_0402_5%

T12
T14
T15
T17

PAD
PAD
PAD
PAD

A11
AM9
AN9

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

A9
B9
A5
B6

CPU_TEST9_ANALOGIN

G8

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

F8
C8
D9
E8

CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2

C6
AH7
AK5
AJ7

MISC

1

1

2
0_0402_5%

1

H_PROCHOT# 20

M31
+VDDNB

SVC
SVD

2

R8
169_0402_1%

A6
A7

VDDA_1
VDDA_2

C1
B2

CPU_SVC
CPU_SVD

CPU_SVC 42
CPU_SVD 42

THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L

AL6
AM5
AK6
AN6

THERMDC_CPU
THERMDA_CPU
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8

TDO

AN7

CPU_TDO

R9
CPU_VDDNB_RUN_FB_H 1

10_0402_5%
2

Close to CPU

+1.5V

DBREQ_L

DBRDY

VSS_SENSE
VLDT_SENSE
VDD_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDDR_SENSE

RSVD3
CPU_PRESENT_L

CPU_DBRDY

H9
AM6
AJ9

T1

PAD @

CPU_PRESENT_L

R801 1

HTREF1
HTREF0

V10
V9

BYPASSCLK_H
BYPASSCLK_L
PLLTEST0
PLLTEST1

FBCLKOUT_H
FBCLKOUT_L

B10
A10

SCANCLK1
TSTUPD
SCANSHIFTEN
SCANEN
SCANCLK2

ANALOGIN
BP3
BP2
BP1
BP0

PLLCHRZ_H
PLLCHRZ_L
SINGLECHAIN
BURNIN_L
ANALOGOUT
DIG_T

ANALOG_T
DIECRACKMON
GATE0
DRAIN0

M_TEST

CPU_HTREF1
CPU_HTREF0

1

2 1K_0402_5%

R13

1

2 1K_0402_5%

2 1K_0402_5%

R14
R15

2 44.2_0402_1%
2 44.2_0402_1%

1
1

CPU_TEST29_H_FBCLKOUT_P 1
CPU_TEST29_L_FBCLKOUT_N

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN_L
CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T

2

+1.1VS

R18
80.6_0402_1%
2

+1.5V
CPU_TEST26_BURNIN_L

CPU_TEST24_SCANCLK1
AK7
CPU_TEST23_TSTUPD
AG8
AK9 CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
AH9
CPU_TEST20_SCANCLK2
AM7
G11
H11
AJ8
AM4
D7
B5

R12

CPU_SVD

R14 R15 Close to CPU within 1.5"

L

M_VREF
M_ZN_H
M_ZN_L

CPU_SVC
+1.5V

T10 PAD @
T11 PAD @
T16 PAD @
T18 PAD @

AG9

CPU_DBREQ#
R19 1
CPU_TEST27_SINGLECHAIN R21 1
R23 1

@
2 300_0402_5% R20 1
2 1K_0402_5%
2 300_0402_5% @

CPU_TEST21_SCANEN
R24 1
CPU_TEST20_SCANCLK2
R25 1
CPU_TEST24_SCANCLK1
R26 1
CPU_TEST22_SCANSHIFTEN R27 1

2
2
2
2

CPU_TEST15_BP1
CPU_TEST14_BP0

R28 1
R29 1

2 300_0402_5% @
2 300_0402_5% @

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST23_TSTUPD
CPU_DBRDY

R30 1
R31 1
R32 1
R34 1

2
2
2
2

2 1K_0402_5%

1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%

1K_0402_5%
1K_0402_5%
1K_0402_5%
300_0402_5% @

+1.5VS
2

+1.5V

1

M_VREF
+1.5V

1

R803
1K_0402_1%

2

1

C654

1

C655

@

2
+1.5V
@ R35
R36
1
2 CPU_TEST25_H_BYPASSCLK_H 1
2
510_0402_5%
510_0402_5%
R38
1
2 CPU_TEST25_L_BYPASSCLK_L
510_0402_5%

0.1U_0402_16V4Z

4

@

@

1
1
1
1
1

2
2
2
2
2

JP1

CPU_TCK_R
CPU_TMS_R
CPU_TDI_R
CPU_TRST#_R
CPU_TDO_R

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

1
C16
2

1
3
5
7
9
11
13
15
17
19
21
23

2
4
6
8
10
12
14
16
18
20
22
24
26

LDT_RST#

CONN@ SAMTEC_ASP-68200-07
4

U4

THERMDA_CPU
C17
1

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
R850
CPU_TMS
R851
CPU_TDI
R852
CPU_TRST# R853
CPU_TDO
R854

R39
1
2
510_0402_5%
@

Thermal Sensor

+3VS

@

2
1
220_0402_5% R41
2
1
220_0402_5% R42
2
1
220_0402_5% R43
2
1
300_0402_5% R44
1
2
300_0402_5% R45

2

C14
0.01U_0402_25V7K
@

1000P_0402_25V8J

1
2

3

0.01U_0402_25V7K

1

K625@

R802
1K_0402_1%

LDT_STOP#

12,20 LDT_STOP#

TMK625DBV23GM_FCBGA812

2

R33
300_0402_5%

3

2 THERMDC_CPU
2200P_0402_50V7K

1

VDD

8

EC_SMB_CK2 31,32

2

D+

3

D-

SDATA

7

EC_SMB_DA2 31,32

ALERT#

6

4

THERM#

GND

5

SCLK

Compal Secret Data

Security Classification
2008/04/14

Issued Date

ADM1032ARM-1 ZREEL_MSOP8

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 CTRL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

7

of

45

+CPU_CORE_0

C

+1.1VS

+1.5V

2

U1F
VDD_85
VDD_84
VDD_83
VDD_82
VDD_81
VDD_80
VDD_79
VDD_78
VDD_77
VDD_76
VDD_75
VDD_74
VDD_73
VDD_72
VDD_71
VDD_70
VDD_69
VDD_68
VDD_67
VDD_66
VDD_65
VDD_64
VDD_63
VDD_62
VDD_61
VDD_60
VDD_59
VDD_58
VDD_57
VDD_56
VDD_55
VDD_54
VDD_53
VDD_52
VDD_51
VDD_50
VDD_49
VDD_48
VDD_47
VDD_46
VDD_45
VDD_44

AE12
AD9
AE21
AD21
AD18
AD14
AD12
AD11
AC5
AE18
AC24
AC12
AC10
AB13
AB11
AE14
AA24
AA12
AA10
Y19
Y16
Y14
W5
W20
W18
W15
AE23
V24
V19
V16
V14
T20
T18
T15
T10
R5
R19
R16
R14
AC4
P24
P20

M27
Y26
U26
N32
U32
N30
P29
R28
R30
R32
U29
U30
W28
W30
W32
Y29
AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25
V25
P25
N25
M25
K25
L25
T25
Y25
AB25

3000mA

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38

VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_1
VDDR_2
VDDR_3
VDDR_4
POWER2

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43

POWER1

1

B1
N2
N22
N23
B13
B15
B17
M21
B19
B21
B23
B27
B29
B33
C10
P10
P14
P16
P19
P7
C31
D11
D13
D15
R1
D17
D19
D21
D23
D25
D27
R15
R18
R2
R20
D29
D30
D8
E30
E32
F14
F17
R8
T14
T16
F20
T19
T24
T9
U1
F23
N1
G1
G19
G2
G25
G27
N10

+CPU_CORE_0
U1E

D4
D5
D6
E5
E6
E7
F5
F6
F7
H7
H8
J8
E4
J10
J12
J14
J18
J20
J21
J23
J9
K10
K12
K14
K18
K20
K21
K23
N4
L11
L13
L7
L9
M10
M12
R4
M5
N11
N24
W4
N9
P15
P18

D

VDDR_5
VDDR_6
VDDR_7
VDDR_8

F1
F2
F3
F4

+1.1VS@1500mA

AL1
AL2
AL3
AL4

+0.9V

A12
B12
C12
D12

+0.9V@1250mA

AK10
AL10
AM10
AN10
+VDDNB

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
PROGEN_L
FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9

A3
A4
B3
B4
C3
C4

+VDDNB@2000mA

B11
G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8

TMK625DBV23GM_FCBGA812
TMK625DBV23GM_FCBGA812
K625@

K625@

VLDT_A&VLDT_B(+1.1VS) decoupling.
+1.1VS

1

2

1
C18
4.7U_0805_10V4Z

2

1
C19
4.7U_0805_10V4Z

2

1
C20
22U_0805_6.3V6M

1

1

E

U1G

U1H

VSS_1
VSS_28
VSS_29
VSS_30
VSS_2
VSS_3
VSS_4
VSS_27
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_12
VSS_13
VSS_14
VSS_15
VSS_36
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_37
VSS_38
VSS_39
VSS_40
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_115

VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114

W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12

AM19
AF7
AF26
AE7
AF8
AF9
AG1
AG2
AG27
AG4
AG5
AG6
AG7
AE4
AE25
AE24
AE22
AE20
AE2
AE16
AE13
AH14
AE11
AE10
AE1
AD24
AD23
AD22
AH20
AH23
AH25
AH28
AD20
AD16
AD13
AD10
AC9
AC8
A2
AC23
AH5
AJ1
AJ15
W2
A32
W8
Y10
Y15
Y18
AJ19
AJ2
AJ22
AJ4
Y20
Y24
AK11
AK13
Y7
AA1
AA11

1

C21
C22
C23
C24
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2
2
2
2

VSS_207
VSS_167
VSS_166
VSS_165
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_177
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_178
VSS_179
VSS_180
VSS_181
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_214
VSS_144
VSS_182
VSS_183
VSS_184
VSS_116
VSS_213
VSS_117
VSS_118
VSS_119
VSS_120
VSS_185
VSS_186
VSS_187
VSS_188
VSS_121
VSS_122
VSS_189
VSS_190
VSS_123
VSS_124
VSS_125

VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_215

GND2

B

GND1

A

+CPU_CORE_0@15000mA

K625@

K625@

TMK625DBV23GM_FCBGA812

VDD(+CPU_CORE_0) decoupling.

+0.9V

1

2

TMK625DBV23GM_FCBGA812

VDDR(+0.9V) decoupling.

AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11

VDDNB(+VDDNB) decoupling.

+CPU_CORE_0
+VDDNB
1

3

2

1
C25
4.7U_0805_10V4Z

2

1
C26
4.7U_0805_10V4Z

2

1
C27
4.7U_0805_10V4Z

2

1
C28
4.7U_0805_10V4Z

1

1

1
1

C29
C30
C31
C32
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z
2
2
2
2

+

1
C494
330U_SX_2VY~D

2

1

+

C495
330U_SX_2VY~D

2

1

+

C496
330U_SX_2VY~D

2

+

C497
330U_SX_2VY~D
@

2

1

2

1
C649
4.7U_0805_10V4Z

2

1
C650
4.7U_0805_10V4Z

2

1
C33
22U_0805_6.3V6M

2

1
C34
22U_0805_6.3V6M

2

C35
22U_0805_6.3V6M

3

+0.9V

1

1

1

1

1

1

1

VDDIO(+1.5V) decoupling.

1

C36
C37
C38
C39
C40
C41
C42
C43
1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
2
2
2
2
2
2
2
2
+1.5V

1
C526
330U_2.5V_M

VDD(+CPU_CORE_0) decoupling.

+
2

1

2

1
C44
22U_0805_6.3V6M

2

1
C45
22U_0805_6.3V6M

2

1
C57
4.7U_0805_10V4Z

2

1
C58
4.7U_0805_10V4Z

2

1
C623
4.7U_0805_10V4Z

2

1
C624
4.7U_0805_10V4Z

2

1
C48
180P_0402_50V8J

2

1
C49
180P_0402_50V8J

2

1
C653
180P_0402_50V8J

2

C629
0.01U_0402_25V7K

+CPU_CORE_0

1

2

1
C50
22U_0805_6.3V6M

2

1
C51
22U_0805_6.3V6M

2

1
C52
22U_0805_6.3V6M

2

1
C53
22U_0805_6.3V6M

1

1

+1.5V

C54
C55
C56
0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J
2
2
2
1

4

+CPU_CORE_0

1

2

1
C59
22U_0805_6.3V6M

1

1

C651
C652
0.22U_0603_16V4Z 0.22U_0603_16V4Z
2
2

2

1
C60
22U_0805_6.3V6M

2

1
C61
22U_0805_6.3V6M

2

1
C62
22U_0805_6.3V6M

1

1

1

1

Compal Secret Data

Security Classification
2008/04/14

Issued Date

L

1

C626
C627
C628
C46
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z
2
2
2
2

2

C47
0.22U_0603_16V4Z

2009/04/14

Deciphered Date

Title

Date:

B

1

2

C631
0.1U_0402_16V7K

Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1
C630
0.1U_0402_16V7K
2

1

C63
C64
C65
0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J
2
2
2

CPU BOT site

2

1
C625
0.22U_0603_16V4Z

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

8

of

45

4

A

B

+VREF_DQ

+1.5V

C

D

E

+1.5V
JDIMM1

DDR_A_DQS#2
DDR_A_DQS2

6 DDR_A_DQS#2
6 DDR_A_DQS2

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

DDR_A_D[0..63]

6

DDR_A_DM[0..7]

6
1

DDR_A_D12
DDR_A_D13
DDR_A_MA[0..15]
DDR_A_DM1
MEM_MA_RST#

DDR_A_MA[0..15] 6

MEM_MA_RST# 6

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29

+VREF_CA
+VREF_DQ

DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_A_MA3
DDR_A_MA1
6
6

DDR_A_CLK0
DDR_A_CLK#0

6

DDR_A_BS#0

6
6

DDR_A_WE#
DDR_A_CAS#

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#

6 DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4

6 DDR_A_DQS#4
6 DDR_A_DQS4

DDR_A_D34
DDR_A_D35

3

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6

6 DDR_A_DQS#6
6 DDR_A_DQS6

DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
R285
10K_0402_5%
1
2

1

+3VS

4

R286

+3VS

205

2

10K_0402_5%

C445

1

2
2.2U_0805_10V6K

C446

G1

G2

DDR_CKE1_DIMMA 6

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

1

C425
@

2

2

C426

1

1

2

DDR_CKE1_DIMMA

C427

R283
1K_0402_1%

2

1

C428
@

2

2
C429
1

C430

2

R284
1K_0402_1%

2

DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_ODT1

DDR_A_CLK1 6
DDR_A_CLK#1 6
DDR_A_BS#1 6
DDR_A_RAS# 6
DDR_CS0_DIMMA# 6
DDR_A_ODT0 6
DDR_A_ODT1 6

+1.5V
0.1U_0402_16V4Z
2

+VREF_CA
DDR_A_D36
DDR_A_D37

1

DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

2

2

C432

0.1U_0402_16V4Z
2

2

C433

1
0.1U_0402_16V4Z

1

C434

1
0.1U_0402_16V4Z

C435
1

0.1U_0402_16V4Z
2

2

C436

C437

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C438

1
0.1U_0402_16V4Z

C439
1

2

0.1U_0402_16V4Z
2
C440

1
0.1U_0402_16V4Z

C441
1

3

+0.75VS
DDR_A_DQS#5
DDR_A_DQS5

DDR_A_DQS#5 6
DDR_A_DQS5 6

2

DDR_A_D46
DDR_A_D47

0.1U_0402_16V4Z
2
C442

1
0.1U_0402_16V4Z

DDR_A_D52
DDR_A_D53

C443
1

1
C444

2
4.7U_0603_6.3V6K

Place near DIMM1

DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

DDR_A_DQS#7 6
DDR_A_DQS7 6

+1.5V

12/25 Solve layout test point issue

EVENT#_A

1
SMB_CK_DAT0 10,21
SMB_CK_CLK0 10,21
+0.75VS

2

1
C700
180P_0402_50V8J

2

1
C701
180P_0402_50V8J

2

1
C702
180P_0402_50V8J

2

C703
180P_0402_50V8J
4

206

FOX_AS0A626-U4RN-7F
CONN@

1

0.1U_0402_16V4Z
2

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_A STD H:4mm

2010/03/12

Deciphered Date

Title

DDRII SO-DIMM 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.



Date:

A

1

1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1000P_0402_25V8J

DDR_A_MA8
DDR_A_MA5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

4.7U_0805_10V4Z

DDR_A_MA12
DDR_A_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

C431
1000P_0402_25V8J

6 DDR_A_BS#2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

+VREF_CA
0.01U_0402_25V7K

DDR_A_BS#2

0.01U_0402_25V7K

DDR_CKE0_DIMMA

6 DDR_CKE0_DIMMA

R282
1K_0402_1%

R281
1K_0402_1%
+VREF_DQ

2

+1.5V

+1.5V

DDR_A_DQS#3 6
DDR_A_DQS3 6

2

DDR_A_D16
DDR_A_D17

DDR_A_D[0..63]
DDR_A_DM[0..7]

1

DDR_A_D10
DDR_A_D11

DDR_A_DQS#0 6
DDR_A_DQS0 6

DDR_A_D6
DDR_A_D7

2

DDR_A_DQS#1
DDR_A_DQS1

6 DDR_A_DQS#1
6 DDR_A_DQS1

DDR_A_DQS#0
DDR_A_DQS0

1

DDR_A_D8
DDR_A_D9

DDR_A_D4
DDR_A_D5

1000P_0402_25V8J

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

4.7U_0805_10V4Z

DDR_A_D2
DDR_A_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_A_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D0
DDR_A_D1

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

9

of

45

A

B

+VREF_DQ

C

+1.5V

D

E

+1.5V
JDIMM2

6 DDR_B_DQS#1
6 DDR_B_DQS1

DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17

6 DDR_B_DQS#2
6 DDR_B_DQS2

DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

6 DDR_CKE0_DIMMB
2

6

DDR_B_BS#2

DDR_CKE0_DIMMB

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0

6

DDR_B_BS#0

6
6

DDR_B_WE#
DDR_B_CAS#

6 DDR_CS1_DIMMB#

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS1_DIMMB#

DDR_B_D32
DDR_B_D33
6 DDR_B_DQS#4
6 DDR_B_DQS4

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

3

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
6 DDR_B_DQS#6
6 DDR_B_DQS6

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R287
10K_0402_5%
1
2

1

+3VS

4

R288

205

2

10K_0402_5%

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D[0..63]

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_DM[0..7]

6
6
1

DDR_B_D12
DDR_B_D13

DDR_B_MA[0..15] 6

DDR_B_MA[0..15]
DDR_B_DM1
MEM_MB_RST#

MEM_MB_RST# 6

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

DDR_B_DQS#3 6
DDR_B_DQS3 6

DDR_B_D30
DDR_B_D31

DDR_CKE1_DIMMB

DDR_CKE1_DIMMB 6

DDR_B_MA15
DDR_B_MA14

2

DDR_B_MA11
DDR_B_MA7
+VREF_DQ

DDR_B_MA6
DDR_B_MA4

+VREF_CA

DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_ODT1

+VREF_DQ

DDR_B_CLK1 6
DDR_B_CLK#1 6
DDR_B_BS#1 6
DDR_B_RAS# 6
DDR_CS0_DIMMB# 6
DDR_B_ODT0 6

1

C447

2

1

C448

2

+VREF_CA

1

C449

2

1

C450

2

0.1U_0402_16V4Z

6
6

DDR_B_CLK0
DDR_B_CLK#0

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_DQS#0 6
DDR_B_DQS0 6

DDR_B_D6
DDR_B_D7

0.1U_0402_16V4Z

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_B_BS#2

DDR_B_DQS#0
DDR_B_DQS0

1

C451

2

1000P_0402_25V8J

DDR_B_D8
DDR_B_D9

DDR_B_D4
DDR_B_D5

4.7U_0805_10V4Z

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1000P_0402_25V8J

DDR_B_D2
DDR_B_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

4.7U_0805_10V4Z

DDR_B_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C452

2

DDR_B_ODT1 6
+VREF_CA

DDR_B_D36
DDR_B_D37

1

DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5

2

3

DDR_B_DQS#5 6
DDR_B_DQS5 6

+1.5V

DDR_B_D46
DDR_B_D47

0.1U_0402_16V4Z
2

2

DDR_B_D52
DDR_B_D53

C454

0.1U_0402_16V4Z
2

2

C455

1
0.1U_0402_16V4Z

DDR_B_DM6

1

C456

C457

1
0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z
2
C458

1
0.1U_0402_16V4Z

C459
1

2

0.1U_0402_16V4Z
2
C460

C461

1
0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z
2
C462

C463

1
0.1U_0402_16V4Z

1

DDR_B_D54
DDR_B_D55

C468 Co-layout with C467

DDR_B_D60
DDR_B_D61

+0.75VS
+1.5V

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_DQS#7 6
DDR_B_DQS7 6

2

DDR_B_D62
DDR_B_D63

12/25 Solve layout test point issue

EVENT#_B

0.1U_0402_16V4Z
2
C464

1
0.1U_0402_16V4Z

C465
1

1

1
+

C466

2
4.7U_0603_6.3V6K

SMB_CK_DAT0 9,21
SMB_CK_CLK0 9,21

C468
330U_2.5V_M

2

Place near DIMM2

+0.75VS

4

206

FOX_AS0A626-U4SN-7F
CONN@

DIMM_B STD H:4mm


2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/03/12

Deciphered Date

Title

DDRII SO-DIMM 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

1

C453
1000P_0402_25V8J

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_B_D0
DDR_B_D1

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

10

of

45

A

B

C

D

E

U5B

< To Card crader >

30
30
26
26
27
27

< To WLAN >
< To LAN >

PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

2

20
20
20
20
20
20
20
20

< From SB820 : x4 PCIE A-link >

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

HDMI_TXD2+
HDMI_TXD2HDMI_TXD1+
HDMI_TXD1HDMI_TXD0+
HDMI_TXD0HDMI_CLK0+
HDMI_CLK0-

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

R51
R54

PART 2 OF 6

PCIE I/F GFX

1

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GPP

PCIE I/F SB

19
19
19
19
19
19
19
19

HDMI

< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
RS880M Display Port Support (muxed on GFX)
1

GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1

PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

C122
C123
C124
C125
C126
C127

1
1
1
1
1
1

2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

C130
C131
C132
C133
C134
C135
C136
C137

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3

30
30
26
26
27
27

< To Card crader >
< To WLAN >
< To LAN >

< To WWAN >

1
1

2
2

RS880MR1@

RS880M_FCBGA528

HDMI_TXD2+
HDMI_TXD2HDMI_TXD1+
HDMI_TXD1HDMI_TXD0+
HDMI_TXD0HDMI_CLK0+
HDMI_CLK0-

L

1.27K_0402_1%
2K_0402_1%

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

2

20
20
20
20
20
20
20
20

< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND >
< RX Impedance Calibration. Connect to VDDPCIE >

+1.1VS

R51 within U5 1"
R54 within U5 1"

U5A

H_CADIN[0..15]

H_CADIP[0..15]

5

H_CADIN[0..15]

5

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

3

< From S1G4 CPU : x16 HT>

5
5
5
5

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

5
5
5
5

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
R52

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

T22
T23
AB23
AA22

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

M22
M23
R21
R20

2 301_0402_1% C23
A24

1

4

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HYPER TRANSPORT CPU I/F

H_CADIP[0..15]

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H24
H25
L21
L20

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

RS880M_FCBGA528

L

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

R53

5 H_CADOP[0..15]
5 H_CADON[0..15]

H_CADOP[0..15]
H_CADON[0..15]

3

< To S1G4 CPU : x16 HT>

1

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

5
5
5
5

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

5
5
5
5

2 301_0402_1%
4

RS880MR1@

Place within 1" layout 1:2

L
/

Place within 1" layout 1:2

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
RS880M HT/PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

11

of

45

A

B

+AVDD1@125mA

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

L5
+AVDD2
1

0_0603_5%

1

C142
2.2U_0603_6.3V6K

CRT_R_R

1

2

2

G18
G17
E18
F18
E19
F19

CRT_G_R

C143
0.1U_0402_16V4Z

CRT_B_R

+1.8VS
L6
+AVDDQ

1
2
BLM18PG121SN1D_0603

1

C144
2.2U_0603_6.3V6K

15,17 CRT_HSYNC
15,17 CRT_VSYNC
17 UMA_CRT_CLK
17 UMA_CRT_DATA

A11
B11
UMA_CRT_CLK
F8
UMA_CRT_DATA E8

R58

2 715_0402_1% G14

2

Total +1.1VS_PLL@230mA
+1.1VS
+NB_PLLVDD

L7
1
2
BLM18PG121SN1D_0603
C145
2.2U_0603_6.3V6K

1

15,20,26,27,30,31,32

12/07 Internal clock gen

2

C146
2.2U_0603_6.3V6K

NBGFX_CLK
NBGFX_CLK#

2

RS15

+1.8VS

VDDA18PCIEPLL1
VDDA18PCIEPLL2

NB_RESET# D8
NB_PWRGD
A10
NB_LDTSTOP# C10
CPU_LDT_REQ# C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

1

0_0402_5%
2

CLK_NBHT
CLK_NBHT#

CLK_NBHT
CLK_NBHT#

NBGFX_CLK
NBGFX_CLK#

LCD_EDID_CLK
LCD_EDID_DATA
HDMIDAT_UMA
HDMICLK_UMA

1

C147
2.2U_0603_6.3V6K

2

+3VS
2
R66

+1.8VS

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

U1
U2

GPP_REFCLKP
GPP_REFCLKN

B9
A9
B8
A8
B7
A7

C8

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

L2
1
2
1 BLM18PG121SN1D_0603

+VDDLTP18

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

+VDDLTP18

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

+VDDLT18

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

LCD_TXCLK+ 18
LCD_TXCLK- 18

+1.8VS

C138
2 2.2U_0603_6.3V6K

1

L4
1
2
1 BLM18PG121SN1D_0603

2

C141
2 4.7U_0805_10V4Z

+VDDLT18

C140
0.1U_0402_16V4Z

+1.8VS

If support VB, R780 R777->SMT, R776->@
If no support VB, R776-->SMT, R780 R777->@
VARY_ENBKL

@

@

R776 1
R780 1

2 0_0402_5% @
2 0_0402_5%

R777 1

2 0_0402_5%

2

UMA_ENVDD 18
UMA_ENBKL 31
GMCH_INVT_PWM 18

@

PS:Need to fine tune R783 and R784 on Page17

R778 R781 R779

MIS.

TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N

STRP_DATA
RSVD

TESTMODE

D9
D10

HPD

D12

SUS_STAT#

HPD

< HDMI hot-plug detection >

SUS_STAT# 15,21

< Strap option pin or gate side-port memory IO >

Strap pin

AE8
AD8
D13

19

1
R65

2
1.8K_0402_5%

AUX_CAL(NC)
RS880MR1@

+1.8VS
+1.8VS

1
2

3

R805
2.2K_0402_5%

R806
2.2K_0402_5%

E

Q36
1

NB_LDTSTOP#

C

3

7,20 LDT_STOP#
+1.8VS

2

B

2 2

3

1

+VDDLT18@220mA

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

1

C148
2.2U_0603_6.3V6K

< LVDS dual channel : channel 1 >

B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17

RS880M_FCBGA528

Strap pin

L10

HT_REFCLKP
HT_REFCLKN

GFX_REFCLKP
GFX_REFCLKN

B10
1
10K_0402_5%
G11

AUX_CAL
2 @
1
150_0402_1%

+VDDA18PCIEPLL

1
2
BLM18PG121SN1D_0603

@

R64

VDDA18HTPLL

T2
T1

CLK_SBLINK_BCLK V4
CLK_SBLINK_BCLK# V3

18 LCD_EDID_CLK
18 LCD_EDID_DATA
19 HDMIDAT_UMA
19 HDMICLK_UMA

+VDDA18HTPLL

C25
C24

CLK_NB_REFCLK E11
CLK_NB_REFCLK# F11

20 CLK_SBLINK_BCLK
20 CLK_SBLINK_BCLK#

RS16

L9
1
2
BLM18PG121SN1D_0603

D7
E7

20 CLK_NB_REFCLK
20 CLK_NB_REFCLK#

+NB_HTPVDD
1

2
1
4.7K_0402_5%

L8
1
2
BLM18PG121SN1D_0603

+VDDA18HTPLL

20 CPU_LDT_REQ#
20
20

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

LCD_TXOUT0+ 18
LCD_TXOUT0- 18
LCD_TXOUT1+ 18
LCD_TXOUT1- 18
LCD_TXOUT2+ 18
LCD_TXOUT2- 18

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

DAC_RSET(PWM_GPIO1)

+VDDA18PCIEPLL

21 NB_PWRGD

2
1
4.7K_0402_5%

+1.8VS

A12
D14
B12

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

H17

R59

PLT_RST#

Total +1.8VS PLL@100mA
2

1

+NB_PLLVDD
+NB_HTPVDD

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

A22
B22
A21
B21
B20
A20
A19
B19

2
1
4.7K_0402_5%

E17
F17
F15

2/2 Fine tune pin define

+1.8VS

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

2
1
4.7K_0402_5%

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

2
1
4.7K_0402_5%

+AVDDQ

2

F12
E12
F14
G15
H15
H14

CRT/TVOUT

+AVDD2

PLL PWR
LVTM

+AVDD1

PM

C139
2.2U_0603_6.3V6K

E

U5C

+AVDD1
1

CLOCKs

L3
1
2
BLM18PG121SN1D_0603

D

1

+3VS

C

MMBT3904_NL_SOT23-3
@

R804 2
1
R63

CPU_LDT_REQ#
1
1K_0402_5%
NB_PWRGD
2
300_0402_5%

R822

R55
1
R56
1
R57

2
140_0402_1%
2
150_0402_1%
2
150_0402_1%

2

0_0402_5%

Contact with NB signal

CPU_LDT_REQ# Pull +1.8VS on page 20
1

1

Contact to CRT conn signal

CRT_R_R

L41 1

2

NBQ100505T-800Y-N_2P

CRT_G_R

L42 1

2

NBQ100505T-800Y-N_2P

CRT_B_R

L43 1

2

NBQ100505T-800Y-N_2P

CRT_R_R
CRT_G_R

CRT_R 17
CRT_G 17
CRT_B 17

CRT_B_R

1

2

1
C913
2.2P_0402_50V8C

2

1
C912
2.2P_0402_50V8C

2

C911
2.2P_0402_50V8C

4

4

2/2 Add L41 L42 L43 C911 C912 C913 for EMI request
/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
RS880M VEDIO/CLK GEN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

12

of

45

2

1

U5D

2

1

2

1

SIDE@
C601
1U_0402_6.3V4Z

1

2

SIDE@
C602
0.1U_0402_16V4Z

1

2

SIDE@
C603
0.1U_0402_16V4Z

1
SIDE@
C614
10U_0603_6.3V6M
2

1

2

SIDE@
C604
10U_0603_6.3V6M

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0
MEM_BA1
MEM_BA2

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CLKP
MEM_CLKN

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

+1.5VS
SIDE@
2

2

B

SIDE@
C600
1U_0402_6.3V4Z

SIDE@
R335
1K_0402_1%
+1.5VS

+MEM_VREF

SIDE@
2

R334
MEM_COMP_P

1 40.2_0402_1%

R336

2

SIDE@
C609
0.1U_0402_16V4Z

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

MEM_DM0
MEM_DM1

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

+1.8V_IOPLLVDD
+NB_IOPLLVDD

R332

2

AE18

+1.8VS

SIDE@
C605
2.2U_0603_6.3V4Z

R333
1
1

AD23

MEM_VREF(NC)

2 0_0603_5%

1
1

+MEM_VREF1

2

2 0_0603_5%

B

+1.1VS

SIDE@
C606
2.2U_0603_6.3V4Z

RS880M_FCBGA528

MEM_COMP_N

1 40.2_0402_1%

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

+MEM_VREF
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

2
SIDE@
R338
1K_0402_1%
1

SIDE@
C610
0.1U_0402_16V4Z

Y17
W18
AD20
AE21

+MEM_VREF1

M9
H2
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E4
F8
F3
F9
H4
H9
G3
H8

MEM_DQ0
MEM_DQ6
MEM_DQ2
MEM_DQ5
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ4

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MEM_DQ11
MEM_DQ15
MEM_DQ9
MEM_DQ10
MEM_DQ12
MEM_DQ14
MEM_DQ8
MEM_DQ13

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A2
A9
C2
C10
D3
E10
F2
H3
H10

2

2

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)
RS880MR1@

+1.5VS

1

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

U27
SIDE@
R337
1K_0402_1%

1

1

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

IOPLLVSS(NC)

AE12
AD12

2

2

SIDE@
C608
0.1U_0402_16V4Z
1

1

PAR 4 OF 6

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

SBD_MEM/DVO_I/F

+1.5VS

2

SIDE@
C611
0.1U_0402_16V4Z

MEM_BA0
MEM_BA1
MEM_BA2

SIDE@
R339
1K_0402_1%

M3
N9
M4

BA0
BA1
BA2

1

1

2
R340

@

For Side port only

J8
K8
K10

MEM_ODT
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#

K2
L3
J4
K4
L4

MEM_DQS_P0
MEM_DQS_P1

F4
C8

MEM_DM0
MEM_DM1

E8
D4

MEM_DQS_N0
MEM_DQS_N1

G4
B8

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

R341 2 SIDE@ 1 10K_0402_5%

+1.5VS

A

MEM_CLKP
MEM_CLKN
100_0402_1%
MEM_CKE

1

T3

21 SP_DDR3_RST#

2

L9

1

R342
243_0402_1%
SIDE@

J2
L2
J10
L10
A1
A11
T1
T11

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NC/ZQ1
NC
NC
NC
NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

A

B2
B10
D2
D9
E3
E9
F10
G2
G10

100-BALL
SDRAM DDR3
K4W1G1646D-EC15_FBGA100
SIDE@
/

Compal Secret Data

Security Classification
Issued Date

2008/04/14

Deciphered Date

2009/04/14

Title

Compal Electronics, Inc.
RS880M SIDE PORT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

2

1

Tuesday, March 23, 2010

Rev
1.0

LA-6032P
Sheet

13

of

45

A

B

C

D

E

U5F

L12
2
1
0_0805_5%

+VDDHT

+1.8VS

C192
1U_0402_6.3V4Z

1

1

F9
G9
AE11
AD11

2

L18
0_0603_5%

50mA

2

1

2

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS880M_FCBGA528
SIDE@
C193
1U_0402_6.3V4Z

VDD33_1(NC)
VDD33_2(NC)

2

2

2

2

2

2

1

AE10
AA11
Y11
AD10
AB10
AC10

2

1

2

1

2

1 C191

2

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

1

H11
H12

RS880MR1@

+3VS
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z

3

R67
0_0402_5%

2
C194

NOSIDE@

2

PART 6/6

C200

60mA

1

2

1

2

1

2

1

2

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

RS880M_FCBGA528

C599SIDE@

5mA

+1.8VS

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

2

1

C598SIDE@

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

C597SIDE@

2

1

0.1U_0402_16V4Z

2

C176

1

C613SIDE@

2

1
C180

1

1U_0402_6.3V4Z

2

1
C179

1

0.1U_0402_16V4Z

2

1
C175

1

1000P_0402_50V7K

1

1
C174

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

1

1

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

C612SIDE@

+VDDA18PCIE

2

C173
4.7U_0805_10V4Z

+VDDA18PCIE@640mA

4.7U_0805_10V4Z

L16
1
0_0805_5%

C189

2

C188

+1.8VS

+NB_CORE

+NB_CORE@7600mA

10U_0805_10V6K

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C178

2

10U_0805_10V6K

2

2

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C187

2

1
C172

0.1U_0402_16V4Z

2

1
C171

C186

2

1
C170

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

0.1U_0402_16V4Z

1
C169

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C185

1
C168

+VDDHTTX

2
2
2
2
1
1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VDDHTTX@680mA

1
0_0805_5%

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

1
1
1
1
2
2

C177

2
0.1U_0402_16V4Z

H18
G19
F20
E21
D22
B23
A23

C160
C161
C164
C165
C166
C167

0.1U_0402_16V4Z

1
C158

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
L14
2

1
C163

10U_0805_10V6K

C155

C184

2
10U_0805_10V6K

1
C157

10U_0805_10V6K

C159

0.1U_0402_16V4Z

C162

PART 5/6

+1.1VS

+VDDA11PCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

C183

1
C156

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

0.1U_0402_16V4Z

2
0_0805_5%

J17
K16
L16
M16
P16
R16
T16

L11
1
2
FBMA-L11-201209-221LMA30T_0805

+VDDA11PCIE@2500mA

U5E

2

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2A
+VDDHTRX
1

L13

+1.1VS

2

C182

2

1
C154

0.1U_0402_16V4Z

2

1
C153

C181

2

1
C152

0.1U_0402_16V4Z

1
C151

0.1U_0402_16V4Z

1
C150

POWER

+1.1VS

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

GROUND

+VDDHT/+VDDHTRX@680mA
1

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

L82 SIDE@
2

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

1

2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS880MR1@

+1.8VS

0_0603_5%

1

2

3

4

4

/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
RS880MPWR/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

14

of

45

A

B

C

2
R68
2
R69

12,17 CRT_VSYNC

@

1
3K_0402_5%
1
3K_0402_5%

E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS880 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K

1

D

Enables the Test Debug Bus using GPIO.
1 : Disable (RS880)
0 : Enable (RS880)
PIN: RS880-->VSYNC#

+3VS

1

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These
000 :
001 :
010 :
011 :
100 :
101 :
111 :

RS780 use register to control PCI-E configure

pin straps are used to configure PCI-E GPP mode.
00001
00010
01011
00100
01010
01100
01011

2

2

DFT_GPIO1: LOAD_EEPROM_STRAPS

2

12,21 SUS_STAT#

D5 @
1

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS880:SUS_STAT#

PLT_RST# 12,20,26,27,30,31,32

CH751H-40PT_SOD323-2

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

3

3

RX881: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS880 use HSYNC to enable SIDE PORT (internal pull high)
2
R70

12,17 CRT_HSYNC

1
3K_0402_5%

RS880: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS880)

+3VS

0 : Enable (RS880)
SIDE@
2
R71

1
3K_0402_5%

4

4

/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
RS880M STRAPS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

15

of

45

A

B

C

D

E

Use SB820M internal clock gen

1

1

2

2

3

3

4

4

Compal Secret Data

Security Classification
2009-02-12

Issued Date

2009-02-12

Deciphered Date

Title

Compal Electronics, Inc.
CLOCK GENERATOR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6051P

Tuesday, March 23, 2010

Sheet
E

16

of

45

A

B

C

D

E

CRT+RJ45 FFC conn
Pin=20pin, pitch=0.5
1

1

1/28 Fine tune JP4 pin define

JP4
RJ45_GND
RJ45_MIDI1+
RJ45_MIDI1-

27 RJ45_GND
27 RJ45_MIDI1+
27 RJ45_MIDI127
27

3/23 switch noise soluation

@

2

10P_0402_25V8K

C914

1

2

C915
10P_0402_25V8K

12 UMA_CRT_CLK
12 UMA_CRT_DATA

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

RJ45_MIDI0+
RJ45_MIDI0-

RJ45_MIDI0+
RJ45_MIDI0-

12,15 CRT_VSYNC
12,15 CRT_HSYNC

@

12
12
12

2

CRT_R
CRT_G
CRT_B

+3VS
+5VS
C909

1

C910

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 GND1
20 GND2

2

21
22

STARC_107K20-000000-G4
0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2
CONN@

1/31 EMI request

3

3

4

4

/

Compal Secret Data

Security Classification
Issued Date

2008/04/14

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
CRT/TV-OUT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

17

of

45

A

B

C

D

E

LCD/PANEL BD. Conn.
+LCD_VDD

1

1

+3VS

R72
150_0603_5%

+3VS
R73
100K_0402_5%

1

ENVDD

Q2B
2N7002DW-T/R7_SOT363-6

5

Q3
AO3413_SOT23

2
2

1

1

+LCD_VDD

C202
0.01U_0402_25V7K

Inrush current = 0A
1

4

2
0_0402_5%

R75

2

47K_0402_5%

1
1

UMA_ENVDD

R74

1

3

1

G

2

12

3

Q2A
2N7002DW-T/R7_SOT363-6

1

2

D

6 2

C201
0.1U_0402_16V7K

S

2

W= 60 mils

1

R76
100K_0402_5%

2

C204
0.1U_0402_16V4Z

2

2

W= 60 mils
1

C203
@
4.7U_0805_10V4Z

< LVDS Connector >

+3VS

2

2

JLVDS1

2

1

@
C211

2

LCD_EDID_CLK
LCD_EDID_DATA
LCD_TXOUT0LCD_TXOUT0+

12
12
12
12

LCD_TXOUT1LCD_TXOUT1+
LCD_TXOUT2LCD_TXOUT2+

12 LCD_TXCLK12 LCD_TXCLK+
10K_0402_5%2 R79

B+

R919
1
2
22_0402_5%

31 BKOFF#

@
C214

C212

2
0.1U_0402_16V4Z

68P_0402_50V8J2

1

0.1U_0402_25V4K 2

+3VS

R77

1

2

0_0603_5%

+3VS_USB
USB20_N9_R
USB20_P9_R

INT_MIC_CLK
INT_MIC_DATA

28 INT_MIC_CLK
28 INT_MIC_DATA

1
R80
1
R81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

2
4.7K_0402_5%
2
4.7K_0402_5%

LCD_EDID_CLK
LCD_EDID_DATA

@
EC_INVT_PWM

1
R782

2
0_0402_5%

GMCH_INVT_PWM

1
R783

2
0_0402_5%

31 EC_INVT_PWM

1/25 Pin24 +LCD_INV-->NC
MGND4
MGND3
MGND2
MGND1

12 GMCH_INVT_PWM

INVT_PWM

R784
10K_0402_5%

34
33

3

32
31

1/19 R782-->@ and R783/R784-->SMT for VB function

I-PEX_20143-030E-20F~D
CONN@
D16
PACDN042Y3R_SOT23-3

1

3

3

1

@
C215

INVT_PWM
BKOFF#_R
+LCD_INV

1
2
FBMA-L11-201209-221LMA30T_0805
1

LCD_TXCLKLCD_TXCLK+

2

L20

1

BKOFF#

LCD_TXOUT1LCD_TXOUT1+
LCD_TXOUT2LCD_TXOUT2+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

C208

1000P_0402_50V7K

0.1U_0402_16V4Z

1

12
12
12
12

LCD_EDID_CLK
LCD_EDID_DATA
LCD_TXOUT0LCD_TXOUT0+

2

+LCDVDD_R
+3VS

@
R798 1

2 0_0402_5%

1.5A
+LCDVDD_R

2 L19
1
0_0805_5%

L83
21 USB20_N9
21 USB20_P9

USB20_N9

4

4

USB20_P9

1

1

3

3

USB20_N9_R

2

2

USB20_P9_R

1

2

+LCD_VDD
1

C205
0.1U_0402_16V4Z

2

C206
4.7U_0805_10V4Z

WCM-2012-900T_0805
R799 1

2 0_0402_5%
@

4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

LCD CONN.
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

18

of

45

A

B

C

HDMI_CLK-

@

1

D

E

HDMI_R_CK-

2
R88

0_0402_5%

L21

1

HDMI_CLK+

@

HDMI_TX0-

@

1

1

2

2

4

4

3

3

D8
2

+5VS

1

RB161M-20_SOD123-2

WCM-2012-900T_0805
1
2
R91
0_0402_5%
1
2
R92
0_0402_5%

F1
+5VS_HDMI
2
1
1.1A_6V_MINISMDC110F-2
1
C216

HDMI_R_CK+

2

+HDMI_5V_OUT

0.1U_0402_16V4Z
1

HDMI_R_D0-

L22
1

1

2

4

3

< HDMI Connector >

2

JHDMI1
4
11 HDMI_TXD0+
11 HDMI_TXD011 HDMI_TXD1+
11 HDMI_TXD1-

C219
C220
C221
C222

1
1
1
1

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX0+
HDMI_TX0HDMI_TX1+
HDMI_TX1-

C223
C224
C225
C226

1
1
1
1

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX2+
HDMI_TX2HDMI_CLK+
HDMI_CLK-

HDMI_TX0+

@

HDMI_TX1-

@

HDMI_HPD

3

WCM-2012-900T_0805
1
2
R95
0_0402_5%
1
2
R96
0_0402_5%

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT
HDMI_R_D0+

HDMI_SDATA
HDMI_SCLK

HDMI_R_D1HDMI_R_CK-

11
11
11
11

HDMI_TXD2+
HDMI_TXD2HDMI_CLK0+
HDMI_CLK0-

L23
1
4
HDMI_TX1+

@

HDMI_TX2-

@

1

2

2

HDMI_R_CK+
HDMI_R_D0-

4

3

3

HDMI_R_D0+
HDMI_R_D1-

WCM-2012-900T_0805
1
2
R99
0_0402_5%
1
2
R100
0_0402_5%

HDMI_R_D1+

HDMI_R_D1+
HDMI_R_D2-

HDMI_R_D2HDMI_R_D2+

4

2

HDMI_TX2+

3

3

WCM-2012-900T_0805
1
2
R103
0_0402_5%

2

HDMI_R_D2+

1/28 Update JHDMI1 footprint

1

2

1

1

12 HDMIDAT_UMA

4

2

R855
2.2K_0402_5%
2

R856
2.2K_0402_5%

2

R85
4.7K_0402_5%
2

R84
4.7K_0402_5%

2

+HDMI_5V_OUT

1

+3VS

2

1

+3VS

@

1

20
21
22
23

SUYIN_100042GR019M23BZR_19P-T
CONN@

L24
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

6

HDMI_SDATA

HDMI_CLK+
HDMI_CLK-

1
R89
1
R90

2
715_0402_1%
2
715_0402_1%

1
R93
1
R94

2
715_0402_1%
2
715_0402_1%

1
R97
1
R98

2
715_0402_1%
2
715_0402_1%

1
R101
1
R102

2
715_0402_1%
2
715_0402_1%

5

2N7002DW-T/R7_SOT363-6
Q4A

HDMI_TX03

4

12 HDMICLK_UMA

HDMI_SCLK

3

HDMI_TX0+

2N7002DW-T/R7_SOT363-6
Q4B
HDMI_TX1HDMI_TX1+

HDMI_TX2+

1

HDMI_TX2-

3

+5VS
+5VS

D

2
G
3

Q6
S
2N7002_SOT23-3

2

HDMI_HPD

+3VS

R87
100K_0402_5%

2 C218
0.1U_0402_16V4Z

2
1

1

C217
0.1U_0402_16V4Z

4

2

5
1
P
OE#

A

Y

4

HPD

12

U6
SN74AHCT1G125GW_SOT353-5

R86
100K_0402_5%

Compal Secret Data

Security Classification
2008/04/14

Issued Date

1

3

2

G

2

1

R83
2.2K_0402_5%

1
4

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

HDMI/CEC
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

19

of

45

B

1

11
11
11
11
11
11
11
11

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

11
11
11
11
11
11
11
11

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

C227
C229
C230
C231
C232
C228
C233
C234

L

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

R104
R105

1 590_0402_1%
1 2K_0402_1%

2
2

Close to SB within 1"

5

1

A_RST#

1

B

U8

Y
A

4

PLT_RST#

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

NC7SZ08P5X_NL_SC70-5

1
8.2K_0402_5%

SB800
PCIE_RST#
A_RST#
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N

AD29
AD28

PCIE_CALRP
PCIE_CALRN

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

AA22
Y21
AA25
AA24
W23
V24
W24
W25

PLT_RST# 12,15,26,27,30,31,32

3

@

G

2

P

0.1U_0402_16V4Z

P1
L1

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

+3VALW

C235

2
R106

2
2
2
2
2
2
2
2

U7A
33_0402_5%
1

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

+PCIE_VDDR

2

1
1
1
1
1
1
1
1

Part 1 of 5
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

12/7 Add RS1~RS14 for internal clock gen
2

CLK_SBLINK_BCLK_R
CLK_SBLINK_BCLK#_R

M23
P23

RS3
RS4

2
2

1 0_0402_5%
1 0_0402_5%

CLK_NB_REFCLK_R
CLK_NB_REFCLK#_R

U29
U28

RS5
RS6

2
2

1 0_0402_5%
1 0_0402_5%

CLK_NBHT_R
CLK_NBHT#_R

T26
T27

RS7
RS8

2
2

1 0_0402_5%
1 0_0402_5%

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R

V21
T21

27 CLK_PCIE_LAN
27 CLK_PCIE_LAN#

RS9 2
RS10 2

1 0_0402_5%
1 0_0402_5%

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

L29
L28

26 CLK_PCIE_MCARD2
26 CLK_PCIE_MCARD2#

RS11 2
RS12 2

1 0_0402_5%
1 0_0402_5%

CLK_PCIE_MCARD2_R
CLK_PCIE_MCARD2#_R

N29
N28

30 CLK_PCIE_MCARD0
30 CLK_PCIE_MCARD0#

RS13 2
RS14 2

1 0_0402_5%
1 0_0402_5%

CLK_PCIE_MCARD0_R
CLK_PCIE_MCARD0#_R

M29
M28

NB

12 CLK_NB_REFCLK
12 CLK_NB_REFCLK#
12
12

NB

CLK_NBHT
CLK_NBHT#

7 CLK_CPU_BCLK
7 CLK_CPU_BCLK#

CPU

V23
T23

LAN
WLAN
Card reader

T25
V25
L24
L23

+3VS
+1.8VS

2

P25
M25
R314
4.7K_0402_5%

H_PWRGD

P29
P28
N26
N27

1

G

2

3

3

1
D

S

H_PWRGD_L

42

Q29

T29
T28

FDV301N_NL_SOT23-3
@

level shift to ISL6265

T34

PAD

L25

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
NB_DISP_CLKP
NB_DISP_CLKN
NB_HT_CLKP
NB_HT_CLKN
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

GPP_CLK1P
GPP_CLK1N

GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

GPP_CLK7P
GPP_CLK7N
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

GPP_CLK8P
GPP_CLK8N

32K_X1
L26

25M_CLK_X2

L27

25M_X1

32K_X2

RTC

25M_CLK_X1

PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

24
24
24
24

V2
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
AJ6
AG6
AG4
AJ4

1

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

24
24
24
24
24
24
24

2

3G_OFF#
T31

PAD

@

T32

PAD

@

BT_PWR#
BT_DET#
BT_RST#

2/8 GPIO35-->GPIO40 for 3G_OFF#

26

BT_PWR# 26,29
BT_DET# 29
BT_RST# 29

R125

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

CLK_PCI_EC1

G21
H21
K19
G22
J24

CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD
LDT_STOP#
LDT_RST#

1

2

22_0402_5%

2

LPC_CLK1 24,32
LPC_AD0 31,32
LPC_AD1 31,32
LPC_AD2 31,32
LPC_AD3 31,32
LPC_FRAME# 31,32

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

1

25M_X2

RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

SB820M_FCBGA605

C1

SB_32KHI

C2

SB_32KHO

CPU_LDT_REQ# 12
H_PROCHOT# 7
H_PWRGD 7,42
LDT_STOP# 7,12
LDT_RST# 7

@

D2
B2
B1

R920 1

2 0_0402_5%

SB820MR1@

RTCCLK

W=20mils

RTCCLK 31

W=20mils
+RTCVCC_R

+SB_VBAT

3/22 add RTCCLK to KBC 32.768

W=20mils
+RTCVCC
+RTCBATT

R129

2

2

NC

OSC

NC

OSC

4
R132
20M_0402_5%

1

25M_CLK_X2

2

2

2
1U_0402_6.3V4Z

1

2
120_0402_5%

1
2
1K_0402_5%

3

2

2

120_0402_5%

W=20mils
J1
JUMP_43X39

C243

@

D9

1

2

1
2
BAS40-04_SOT23-3

4

+CHGRTC

2

2

32.768KHZ_12.5PF_Q13MC14610002

1
22P_0402_50V8J

1
C242

1

R829
1M_0402_5%

Y6

C241
0.1U_0402_16V4Z

1

1

1

Y2

3

2
C705

1
1

SB_32KHI

1

25M_CLK_X1

W=20mils

R918

2

2

18P_0402_50V8J

1

C240

25MHZ_20PF_7A25000012

22P_0402_50V8J

SERIRQ 31,32

R917

4

24,31

3

SERIRQ

2/2 C240 C244 22P-->18P for RTC fail issue
C704
22P_0402_50V8J
2
1

CLK_PCI_EC
C640

14M_25M_48M_OSC

ISL6265 PWROK input, TTL level: 0.8V~2.0V
When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high

W2
W1
W3
W4
Y1

GPP_CLK2P
GPP_CLK2N

LPC

1 0_0402_5%
1 0_0402_5%

CPU

2
2

12 CLK_SBLINK_BCLK
12 CLK_SBLINK_BCLK#

CLOCK GENERATOR

RS1
RS2

NB

E

0.1U_0402_16V4Z

R326
2

D

PCI INTERFACE

2 150P_0402_50V8J
A_RST#

PCI CLKS

C524 1

C

PCI EXPRESS INTERFACES

A

SB_32KHO

1
18P_0402_50V8J

C244

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

SB820-PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

20

of

45

A

B

C

D

E

2.2K_0402_5% SMB_CK_DAT0

R134

1

2 4.7K_0402_5%

3/17 del CLKREQ_CR#

26 CLKREQ_MCARD2#

WLAN

SUS_STAT#

R343 2
1
0_0402_5%
SIDE@

13 SP_DDR3_RST#

SP_DDR3_RST#_R

2

3/17 for JMB389

USB_OC#2

25,31 USB_OC#2
30 CR_CPPE#_SB
29,31 USB_OC#0

USB_OC#0

28 AZ_BITCLK_HD
1
C632
33P_0402_50V8J

H3
D1
E4
D4
E8
F7
E7
F8

EC_LID_OUT#

31 EC_LID_OUT#

28 AZ_SDOUT_HD
24
HDA_SDOUT
28 AZ_SDIN0_HD

R306

1

2

33_0402_5%

R307

1

2

33_0402_5%

2
R310
R311

28 AZ_SYNC_HD
28 AZ_RST_HD#

2
2

33_0402_5%
33_0402_5%

2

GBE_COL
GBE_CRS
@

GBE_MDIO

1

R807
10K_0402_5%

1
1

+3VALW
3

2

1
10K_0402_5%

2

1
10K_0402_5%

R151

R155

GBE_MDIO
GBE_RXERR

GBE_PHY_INTR
+3VALW
GBE_PHY_INTR

2
R152
2
R153
2
R154

1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

GBE_COL

2
R863

1 CIR_EN#
10K_0402_5%

GBE_CRS
GBE_RXERR

CIR_EN#

M3
N1
L2
M2
M1
M4
N2
P2
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
E23
E24
F21
G29
D27
F28
F29
E27

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

USB_HSD7P
USB_HSD7N

G12
G14

USB_HSD6P
USB_HSD6N

G16
G18

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

D16
C16

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B14
A14

USB_HSD3P
USB_HSD3N

E18
E16

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

USB20_P9 18
USB20_N9 18

USB-9 Int Camera

USB20_P8 26
USB20_N8 26

USB-8 WLAN

USB20_P6 29
USB20_N6 29

USB-6 Bluetooth

USB20_P5 26
USB20_N5 26

USB-5 WWAN

EHCI2 / OHCI2

1/21 Change USB port10 to USB port5 on WWAN
2

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

A16
B16

USB20_P0
USB20_N0

EHCI1 / OHCI1
USB20_P2 25
USB20_N2 25

USB-2 USB/eSATA

USB20_P1 29
USB20_N1 29

USB-1 Right side

USB20_P0 29
USB20_N0 29

USB-0 Right side



USB 1.1 USB MISC

+3VALW

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160

USB20_P8
USB20_N8

SB820M_FCBGA605

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

D25
F23
B26
E26
F25
E22
F22
E21
G24
G25
E28
E29
D29
D28
C29
C28

SB_SIC
SB_SID

R823
10K_0402_5%
GPIO199
GPIO200

24
24

GPIO201
GPIO202
GPIO203

STRAP PIN
STRAP PIN

1

2.2K_0402_5% SMB_CK_CLK0

2

USB20_P9
USB20_N9

D13
C13

R824
10K_0402_5%

R825
10K_0402_5%
S@
2

2

1

USB_HSD8P
USB_HSD8N

A13
B13

1

1

R142

PCH_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

28
PCH_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

USB_HSD9P
USB_HSD9N

J12
J14

GPIO201
GPIO202
GPIO203

R826
10K_0402_5%
@

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

GPIO201

R827
10K_0402_5%
@

GPIO202

GPIO203

AMD-S 11.6

1

1

1

AMD-M 13.3

1

1

0

R828
10K_0402_5%
M@

3

2

R141

9,10
9,10
26
26

USB_HSD10P
USB_HSD10N

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN

EHCI13 / OHCI3

1

+3VS

E14
E12

2

27 CLKREQ_LAN

RSMRST#

F11
E11

USB_HSD11P
USB_HSD11N

1

LAN

G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20

USB_HSD12P
USB_HSD12N

1

2

EC_RSMRST#

31 EC_RSMRST#

12/7 Internal clock gen

USB_HSD13P
USB_HSD13N

B12
A12

OHCI4

1

1 EC_RSMRST#
100K_0402_5%

H9
J8

L
Close to SB within 1"

2

2
R140

USB_FSD0P/GPIO185
USB_FSD0N

1/31 R133 8.2K-->11.8K

1

EC_SWI#

J10
H11

T35 PAD @
2
R133

2

27

7 H_THERMTRIP#
12 NB_PWRGD

USB_FSD1P/GPIO186
USB_FSD1N

USB 2.0

EC_SWI#
10K_0402_5%

USB_RCOMP 1
11.8K_0402_1%

GPIO

2

USBCLK

G19

USB OC

1
R797

SB800

A10

USB_RCOMP

EMBEDDED CTRL

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

1

@
@
@

USBCLK/14M_25M_48M_OSC

EMBEDDED CTRL

31
31
31
31

+3VALW

HD AUDIO

PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#

GBE LAN

31
31
31
31
12,15

PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD

ACPI / WAKE UP EVENTS

U7D
J2
K1
D3
PM_SLP_S3#
F1
PM_SLP_S5#
H1
PBTN_OUT#
F2
SB_PWRGD
H5
SUS_STAT#
G6
PAD T28
B3
PAD T29
C4
PAD T30
F6
GATEA20
AD21
KB_RST#
AE21
EC_SCI#
K2
EC_SMI#
J29
H2
J1
EC_SWI#
H6
F3
H_THERMTRIP# J6
NB_PWRGD
AC19

SB820MR1@

+3VALW
4

4

@
1
R315
1
R316
1
R317
1
R318
1
R319
1
R320

2
100K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

EC_LID_OUT#
SB_SIC
SB_SID
/
H_THERMTRIP#

Compal Secret Data

Security Classification
2008/04/14

Issued Date

SMB_CK_CLK1

2009/04/14

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMB_CK_DAT1

Date:

A

Compal Electronics, Inc.

B

C

D

SB820 USB/HD Audio
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

21

of

45

A

B

C

D

E

U7B

25 SATA_RX025 SATA_RX0+

SB800

SATA_TX0+
SATA_TX0-

AH9
AJ9

SATA_TX0P
SATA_TX0N

SATA_RX0SATA_RX0+

AJ8
AH8

SATA_RX0N
SATA_RX0P

AH10
AJ10

1

SATA_TX1P
SATA_TX1N

AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12
25 SATA_TX3+
25 SATA_TX3-

eSATA

25 SATA_RX325 SATA_RX3+

R321
2
2
R322

+1.1VS_SATA

SATA_RX2N
SATA_RX2P

SATA_TX3+
SATA_TX3-

AH14
AJ14

SATA_RX3SATA_RX3+

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX4N
SATA_RX4P

AJ18
AH18

SATA_TX5P
SATA_TX5N

AH19
AJ19

SATA_RX5N
SATA_RX5P

AB14
AA14

SATA_CALRP
SATA_CALRN

Close to SB within 1"

L

1K_0402_1%
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%

Part 2 of 5

SATA_TX3P
SATA_TX3N

FLASH

25 SATA_TX0+
25 SATA_TX0-

SERIAL ATA

HDD

2

SATA_LED#

+3VS

SATA_ACT#/GPIO67

2 10K_0402_5%
@

@

SATA_X1 AD16

T36 PAD

SATA_X1

SATA_X2 AC16

T37 PAD

DO
DI
CLK
CS#

HW MONITOR

R156 1

SATA_X2

J5
E2
K4
K9
G2

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161

ࡉ add TP36 TP37

1/25 Del R164 Y3 C246 C247

SPI ROM

33

AD11

SB820M_FCBGA605

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

AH28
AG28
AF26

FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

AF28
AG29
AG26
AF27
AE29
AF29
AH27

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

W5
W6
Y9

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

W7
V9
W8

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM

B6
A6
A5
B5
C7

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

A3
B4
A4
C5
A7
B7
B8
A8

NC1
NC2

1

3/17 for JMB389
CR_WAKE# 30

1
R157

2
150K_0402_5%

+3VALW
2

WLAN_PWR_EN#
ACIN_SB
WWAN_PWR_EN#

WLAN_PWR_EN# 26

D10
2

WWAN_PWR_EN# 26

SLP_CHG_M3_SB_NEW
R916 1
SLP_CHG_M3_SB
@ R865 1
SLP_CHG_M4_SB
R866 1

1

ACIN

31,33,35

CH751H-40PT_SOD323-2

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

SLP_CHG_M3
SLP_CHG_M4

SLP_CHG_M3 25,31
SLP_CHG_M4 25,31

1/20 Colay USB charger net

G27
Y2

+3VALW

SLP_CHG_M3
SLP_CHG_M4

SB820MR1@

1
R162
1
R163

2
100K_0402_5%
2
100K_0402_5%

3

3

1

CLK
+3VALW

R859
0_0402_5%

@
U47
8
1

2

C470

3

0.1U_0402_16V4Z
@

7
CS#

1

CLK

6

DI

5

VCC

VSS

4

2

20mils

2

W

C707

@

HOLD

1

22P_0402_50V8J

S
C
D

Q

2

DO

SST25LF080A_SO8-200mil

12/31 SMT memo control (256KB MX25L1605DM2I-12G SOP 8P)
4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
SB820 SATA/IDE/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

22

of

45

B

+1.1VS_SATA

AD14

2
1
0_0805_5%

+1.1VS

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

567mA

C277
C279
C280
C281
C282

2

1

1
1
1
1

2
2
2
2

+3VALW

22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2

1
0_0805_5%

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

658mA

C284
C285
C287
C288
C289

2 10U_0805_10V6K
2 10U_0805_10V6K
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
@

1
1
1
1
1

+1.1VALW
+1.1V_USB
VDDAN_1.1V_USB

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

0.1U_0402_16V4Z

1

VDDIO_GBE_S_1
VDDIO_GBE_S_2

M6
P8

TBDmA

2

C254

C263

C253

C268

C262

PCI/GPIO I/O

CORE S0

L7
L9

2

2

1

2

1

1

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDIO_AZ_S

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
VDDPL_33_SYS

VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S

SB820M_FCBGA605

2

1
2.2U_0603_6.3V4Z
1
2.2U_0603_6.3V4Z

2
C276
2
C278

+1.1VALW
VDDCR_11_S_1
VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

32mA

A21
D21
B21
K10
L10
J9
T6
T8

113mA

F26
G26
TBDmA

M8

+3VALW

1U_0402_6.3V4Z

2

1U_0402_6.3V4Z

2

VDDCR_1.1V_USB

A11
B11

VDDPL_3.3V

L22

VDDPL_1.1V

F19

VDDPL_3.3V_USB

C292

D6

1

2

2

+1.1VALW

Y4

1
2
FBMA-L11-160808-221LMT_0603

D8

C293

2

C294

M19

1
1 0.1U_0402_10V6K
0.1U_0402_10V6K

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

+3VALW

10U_0603_6.3V6M

+3VALW

L31
1
2
FBMA-L11-160808-221LMT_0603

VDDXL_3.3V

L20

1 C286
L29

197mA
M21

1 C283

1

SB820MR1@

2

2.2U

2

3

C296

1

C11
D11

2.2U_0603_6.3V4Z

C295

1
0_0805_5%

1

+3VALW

L30
2

M10

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

VDDPL_33_SATA

+AVDD_USB

L28

1

93mA

VDDPL_3.3V_SATA
L27
2

L25
1
2
FBMA-L11-201209-221LMA30T_0805

400mA

V1

+1.1VS

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

GROUND

1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2
2
2

+1.1V_CKVDD

K28
K29
J28
K26
J21
J20
K21
J22

C297

1
1
1
1

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

3.3V_S5 I/O

C272
C273
C274
C275

U26
V22
V26
V27
V28
V29
W22
W26

U7E

22U_0805_6.3V6M

600mA

VDDIO_33_GBE_S

CORE S5

+1.1VS

2
2
2
2

2
VDDRF_GBE_S

VDDPL_33_PCIE

2
+1.1VS
0_0805_5%
2
C249
C255
1
C267
1
C258
1
C260
1

1

0.1U_0402_10V6K

AE28

1
0_0805_5%
2
1
C269
22U_0805_6.3V6M
C270 1
2 1U_0402_6.3V4Z @

1
R165
10U_0805_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_10V6K

+PCIE_VDDR
L26
2

POWER

N13
R15
N17
U13
U17
V12
V18
W12
W18

1U_0402_6.3V4Z

43mA

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

CLKGEN I/O

VDDPL_3.3V_PCIE

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

FLASH I/O

AF22
AE25
AF24
AC22

2
0_0402_5%

SERIAL ATA

1
R166

GBE LAN

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

USB I/O

1

1 @ 2
1 @ 2
1 @ 2
1
2
1
2
1
2

PLL

C266
C256
C257
C259
C261
C252

1 22U_0805_6.3V6M

E

+1.1VS_VDDC

Part 3 of 5

SB800
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

PCI EXPRESS

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

D

510mA

U7C

131mA
+3VS
C248 2

C

1U_0402_6.3V4Z

A

EFUSE

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

1

2

VSSAN_HWM
VSSXL

VSSPL_SYS

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

3

Part 5 of 5
+3VALW

VDDPL_3.3V_PCIE

1
2
FBMA-L11-160808-221LMT_0603
1

2

1
1

C304

47mA
2

2.2U_0603_6.3V4Z

L34
1
2
FBMA-L11-160808-221LMT_0603

62mA

VDDPL_3.3V

1
2
FBMA-L11-160808-221LMT_0603

C303

VDDPL_1.1V

VDDPL_3.3V_USB

C301

L36

2

C300
2.2U_0603_6.3V4Z

1

2 2.2U_0603_6.3V4Z

SB820M_FCBGA605

SB820MR1@

17mA

C302

L32
1
2
FBMA-L11-160808-221LMT_0603

+3VS
L35

2.2U

+3VS

2

1

0.1U

+1.1VALW

+3VALW
+3VS
L33
VDDPL_3.3V_SATA

1
2
FBMA-L11-160808-221LMT_0603

1
1

4

2

C299
2.2U_0603_6.3V4Z

C298

L

C298 near U7.M8

2 2.2U_0603_6.3V4Z

4

/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SB820 Power/GND
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

23

of

45

B

C

REQUIRED STRAPS

Check Internal PU/PD

AZ_SDOUT

PCI_CLK1

PCI_CLK2

LOW POWER
MODE

ALLOW PCIE
GEN2

WATCHDOG
TIMER
ENABLE

PCI_CLK3
USE
DEBUG
STRAP

PCI_CLK4

LPC_CLK0

LCP_CLK1

GPIO200
(EC_PWM3)

Inter CLK
Gen Mode

EC
ENABLE

CLOCKGEN
ENABLE

H,H = Reserved

Enable
DEFAULT

DEFAULT

R168
10K_0402_5%
2
1

+3VS

R167
10K_0402_5%
2
1

+3VS

R170
10K_0402_5%
2
1

+3VS

EC
DISABLE

@

@

@

@

L,H = LPC ROM
L,L = FWH ROM

CLOCKGEN
DISABLE

DEFAULT

+3VS

+3VALW

+3VALW

+3VALW

+3VALW

@

H,L = SPI ROM
Option 2:SPI Flash (256KB*1) for EC
SPI Flash (2MB*1) for SB (set up strap pin)

@

R244
10K_0402_5%
2
1

SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

DISABLE ILA
AUTORUN

USE FC PLL

USE DEFAULT
PCIE STRAPS

DISABLE PCI
MEM BOOT

PULL
LOW

BYPASS
PCI PLL

DEFAULT

DEFAULT

DEFAULT

DEFAULT

ENABLE ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

Check AD29,AD28 strap function

20
20
20
20
20
20
20

R185
2.2K_0402_5%
2
1

R186
2.2K_0402_5%
2
1

3

PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

check default

R192
2.2K_0402_5%
2
1

USE PCI
PLL
DEFAULT

PCI_AD23

R191
2.2K_0402_5%
2
1

PCI_AD24

R190
2.2K_0402_5%
2
1

PCI_AD25

R189
2.2K_0402_5%
2
1

PCI_AD26

+3VS

R188
2.2K_0402_5%
2
1

PCI_AD27

12/31 SMT memo control

12/12 Add cC706 for EMI request

+3VS

DEBUG STRAPS

@

R187
10K_0402_5%
2
1

C706

2

22P_0402_50V8J

R221
10K_0402_5%
2
1

R181
10K_0402_5%
2
1

R179
10K_0402_5%
2
1

R178
10K_0402_5%
2
1

R177
10K_0402_5%
2
1

R180
10K_0402_5%
2
1

R209
10K_0402_5%
2
1

1

12/12 Fine tune SB820 int clock gen strap pin

PULL
HIGH

2

12/31 SMT memo control

@

3

L,H = LPC ROM(Default)
Option 1:SPI Flash (2MB*1) for EC

@

21
HDA_SDOUT
20
PCI_CLK1
20
PCI_CLK2
20
PCI_CLK3
20
PCI_CLK4
20,31 CLK_PCI_EC
20,32 LPC_CLK1
21
GPIO200
21
GPIO199

2

1

Disable

DEFAULT

R200
10K_0402_5%
2
1

+3VALW

DEFAULT

DEFAULT

Inter CLK
Gen Mode

IGNORE
DEBUG
STRAP

GPIO199
(EC_PWM2)

H,L = SPI ROM(Default)

R349
10K_0402_5%
2
1

DEFAULT

WATCHDOG
TIMER
DISABLE

R171
10K_0402_5%
2
1

FORCE PCIE
GEN1

R169
10K_0402_5%
2
1

Performance
MODE

PULL
LOW

E

R176
2.2K_0402_5%
2
1

PULL
HIGH

1

D

R175
2.2K_0402_5%
2
1

A

@

@

@

@

@

4

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SB820 STRAPS
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

24

of

45

A

B

C

D

E

SATA transfer board
+5VS

Place closely JHDD SATA CONN

L

1.2A
1

1

C305
10U_0805_10V4Z

2

2

1

C306
0.1U_0402_16V4Z

2

1

C307
0.1U_0402_16V4Z

2

C308
0.1U_0402_16V4Z

03/11 Del JHDD2

1

1

JHDD1

13
14

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

+5VS

SATA_C_TX0+ C309 1
SATA_C_TX0- C310 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_C_RX0- C311 1
SATA_C_RX0+ C312 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_TX0+ 22
SATA_TX0- 22
SATA_RX0- 22
SATA_RX0+ 22

2/2 Update JHDD1 10pin-->12pin

ACES_85201-1205N
CONN@

SATA FFC conn
Pin=12pin, pitch=1.0
2

2

E-SATA/USB
+3VALW
+USB_VCCB

21

USB20_P2

21

USB20_N2

USB20_P2_R_U

1

1D+

VCC

USB20_N2_R_U

2

1D-

S

USB20_P2

3

USB20_N2

4
5

2D+

D+

2D-

D-

GND

OE#

10

1

0.1U_0402_16V4Z
+3VALW

1/19 Change net name SLP_CHG-->SLP_CHG#

2

9

Active Low

SLP_CHG# 31
+5V_ALW

USB20_P2_R

8

U9
7

USB20_N2_R

6

USB_CHG_EN#
USB_CHG_EN#

31 USB_CHG_EN#

0.1U_0402_16V4Z

1
2
3
4

+USB_VCCB

2A

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

1
1

C316

C314
150U_B2_6.3VM_R45M

R858

8
7
6
5

RT9715BGS_SO8
TS3USB221RSER_QFN10_2x1P5

1/25 U9 pin1 +5VALW-->+5V_ALW for USB charger

1

1

2

C315
2

+

C522

10K_0402_5%
2

1000P_0402_50V7K

2

U10

USB_OC#2 21,31

1

C317
@
4.7U_0805_10V4Z
2

1/20 update JSATA1 footprint

3

3

+USB_VCCB
+USB_VCCB

2

1

VCC

GND

USB20_P2_S_O
3
USB20_N2_S_O
6
8 R198 1
2 100_0402_5%
11

2

1B
2B
3B
4B

SATA_TX3+
SATA_TX3-

22
22

SATA_RX3SATA_RX3+

C318
C319

1
1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_C_TX3+
SATA_C_TX3-

C320
C321

2
2

1 0.01U_0402_25V7K
1 0.01U_0402_25V7K

SATA_C_RX3SATA_C_RX3+

USB20_P2_S_O
USB20_N2_S_O
R196
51K_0402_1%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

R197
51K_0402_1%
@

SN74CBT3125PWRG4_TSSOP14

R199 1

C322
0.1U_0402_16V4Z

VBUS
DD+
GND

USB

GND
A+
ESATA
AGND
BB+
GND
GND
GND
GND
GND
TAIWI_EU114-117CRL-TW_11P-T
CONN@

7
2

14

+USB_VCCB

1A
2A
3A
4A

1

2
5
9
12

1OE#
2OE#
3OE#
4OE#

22
22

2

USB20_P2_R_U
USB20_N2_R_U

1

1
22,31 SLP_CHG_M4

R195
43K_0402_1%

2

22,31 SLP_CHG_M3

R194
75K_0402_1%

1

U11
1
4
10
13

JSATA1

W=60mils
USB20_N2_R_S
USB20_P2_R_S

2 0_0402_5%

+USB_VCCB
L37

D11
4
USB20_P2_R_S

4

3

VIN

IO1

IO2 GND

2

USB20_P2_R

1

USB20_N2_R

4

USB20_N2_R_S

1

CM1293A-02SR SOT143-4

1

2

4

3

2

USB20_P2_R_S

3

USB20_N2_R_S
4

WCM-2012-900T_0805
R201 1

2 0_0402_5%
@

SLP_CHG_M3

SLP_CHG_M4

SLP_CHG

Mode 3

HIGH

LOW

LOW

FUNCTION
D=1D

Mode 4

LOW

HIGH

HIGH

D=2D

/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

Compal Electronics, Inc.

C

D

SATA HDD/ODD
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

25

of

45

PCIe Mini Card-3G/WWAN (Slot 2)
+3V_W W AN
+3VS

JW W AN1

2
22 W W AN_PW R_EN#

@

COMMON R203 1

2 0_0402_5%UIM_VPP

USB20_N5 21
USB20_P5 21

+3V_W W AN

LED_W IMAX#

WLAN&BT Combo module circuits
+UIM_PW R

1

RM1
4.7K_0402_5%
@

2
8

UIM_DATA

MOLEX_47273-0001~D
CONN@
DM3
DM4
DAN217_SC59
DAN217_SC59
@
@

CM10
22P_0402_50V8J
2 @

@
D17
28,31,34,37,41 SUSP#

+3V_W LAN

R205 0_0402_5%
1
2
1
2
R206 0_0402_5%

53
54

GND
GND

1

E51_TXD
E51_RXD

RM4
100K_0402_5%

2

31
31

S 2N7002_SOT23-3

1

CM13

2
4.7U_0805_10V4Z

CM14

CM15

2
0.01U_0402_25V7K

01/21 Add D17 and Q38 for BT control
1

CM16

2

+3VS

+3VS

2
4.7U_0805_10V4Z
2

2

0.1U_0402_16V4Z
1

RM8
1
2
47K_0402_5%

1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

22 W LAN_PW R_EN#

03/19 del LPC frame and LPC_AD1-LPC_AD3 trace

2

@
CM18
0.1U_0402_16V7K

1
W LAN_PW R_EN#_R

@

BELLW _80052-1021_52P
CONN@

W L_OFF#
PLT_RST#

RM10
0_0805_5%

QM2

2

AO3413_SOT23

2

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

@
RM7
100K_0402_5%

3

2
4
6
8
10
12
14
16

1

2
4
6
8
10
12
14
16

@
+3V_W LAN

W L_OFF# 31
PLT_RST# 12,15,20,27,30,31,32
+1.5VS

SMB_CK_CLK1
SMB_CK_DAT1

SMB_CK_CLK1 21
SMB_CK_DAT1 21
USB20_N8 21
USB20_P8 21

LED_W IMAX#

@ 2
CM19
0.1U_0402_16V7K

+3V_W LAN

1

11 PCIE_ITX_C_PRX_N2
11 PCIE_ITX_C_PRX_P2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

D

1

LED_W IMAX# 33

QM3

2
LED_W IMAX#

2

100K_0402_5%

RM11
0_0603_5%

@

2

11 PCIE_PTX_C_IRX_N2
11 PCIE_PTX_C_IRX_P2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

CM12

2
0.01U_0402_25V7K

1

3

20 CLK_PCIE_MCARD2#
20 CLK_PCIE_MCARD2

1
3
5
7
9
11
13
15

2
G
Q38

1
1

21 CLKREQ_MCARD2#

1
3
5
7
9
11
13
15

BT_CTRL

2

20,29 BT_PW R#

1

BT_CTRL

+1.5V_W LAN

1

G

01/19 Update net name BT_CTRL-->BT_PWR#

CM11

SUSP#

+3V_W LAN

0.1U_0402_16V4Z
1
1

+3V_W LAN

HI

CH751H-40PT_SOD323-2

+1.5V_W LAN

JW LAN1

LO

**If +3V_WLAN is +3VS, please
remove D17.

1

+UIM_PW R

PCIe Mini Card-WLAN(Slot 1)

BT_PWR#

1

NC

LO

UIM_VPP

1

NC

HI

3

2

3

2

DM2
DAN217_SC59
@

7

4
5
6

Disable

BT_CRTL

2

1

1
2

CM9
10P_0402_50V8J

2

CM8
10P_0402_50V8J

3

2

2

1

GND
VPP
I/O

Enable

RM3

D

1

VCC
RST
CLK

BT
on module

S

DM1
RLZ20A_LL34

1
2
3

BT
on module

G

1

UIM_RESET
UIM_CLK

3

+UIM_PW R

1

1

@

J3G1

CM7
0.1U_0402_16V4Z

AO3413_SOT23

SMB_CK_CLK1
SMB_CK_DAT1

P-TW O_A54402-A0G16-N_52P
CONN@

+UIM_PW R

RM9
0_0805_5%

QM1

2

2

CM20
1000P_0402_50V7K
2

2
4.7U_0805_10V4Z

@

1

1

2

RM6
1
2
47K_0402_5%

2

3

1

CM6

2
0.01U_0402_25V7K

3G_OFF# 20

PLT_RST#

CM5

1

CM17
0.1U_0402_16V7K

1

CM4

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
55
56

@
RM5
100K_0402_5%

0.1U_0402_16V4Z
1
1

D

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G3
G4

+3V_W W AN
+UIM_PW R
UIM_DATA
UIM_CLK
UIM_RESET
COMMON

S

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G2

+3VS

2
4
6
8
10
12
14
16

G

+3V_W W AN

2
4
6
8
10
12
14
16

D

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54

1
3
5
7
9
11
13
15

S

1
3
5
7
9
11
13
15

AO3413_SOT23
+1.5V_W LAN

Compal Secret Data

Security Classification
Issued Date

2008/09/05

Deciphered Date

2009/09/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
PCIe-WLAN/HDDVD/NAND/NEW

Size

Document Number

Rev
1.0

LA-6032P
Date:

Tuesday, March 23, 2010

Sheet

26

of

45

5

4

3

2

3/10 Change CL13 0805-->0603

UL1
11 PCIE_PTX_C_IRX_P3

CL1

11 PCIE_PTX_C_IRX_N3

CL2

2 0.1U_0402_16V7K PCIE_PRX_LANTX_P3

1

2 0.1U_0402_16V7K PCIE_PRX_LANTX_N3

1

11 PCIE_ITX_C_PRX_P3
11 PCIE_ITX_C_PRX_N3
RL19

21 CLKREQ_LAN
D

12,15,20,26,30,31,32

@
@

+3V_LAN

EECS/SCL
EEDI/SDA

CLKREQB

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

CKXTAL1

44

1
RL5

CKXTAL2

28

ENSWREG

+3VS

PERSTB

43

+LAN_VDDREG

2
2.49K_0402_1%

1
2
4
5
7
8
10
11

1
RL2 2
RL1 2

LL1
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T

1 10K_0402_5%
1 10K_0402_5%

+LAN_VDD10

ISOLATEB

14
15
38

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

33

ENSWREG

34
35

VDDREG
VDDREG

46

RSET

24
49

GND
PGND

2

1

0.1U_0402_16V4Z
CL9
0.1U_0402_16V4Z

1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z

D

Close to Pin 3,6,9,13,29,41,45
+LAN_VDD10

DVDD33
DVDD33

27
39

AVDD33
AVDD33
AVDD33
AVDD33

12
42
47
48

EVDD10

21

+LAN_EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

3
6
9
45

+LAN_VDD10

+3V_LAN

1
LL2
CL18
1U_0402_6.3V4Z

+3V_LAN

+3V_AVDDXTAL

1

1

2

2

CL17
0.1U_0402_16V4Z
1

0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1

Close to Pin 21

1
0.1U_0402_16V4Z

+3V_LAN

+LAN_VDDREG
2
0_0603_5%

+LAN_REGOUT

36

2
CL19
2
CL20
2
CL21
2
CL22

0.1U_0402_16V4Z

1
LL3

CL28
4.7U_0603_6.3V6K

RTL8105E-VB-GR_QFN48_6X6

RL6
1K_0402_1%

1

2

+LAN_EVDD10

2
0_0603_5%

REGOUT

1
0.1U_0402_16V4Z

+LAN_VDD10

LANWAKEB

26

2
CL10
2
CL4
2
CL5
2
CL6
2
CL7

0.1U_0402_16V4Z

1
Layout Note: LL1 must be
within 200mil to Pin36
CL13
CL8,CL9 must be within
4.7U_0603_6.3V6K
2
200mil to LL1
+LAN_REGOUT: Width =60mil

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

13
29
41

DVDD10
DVDD10
DVDD10

+LAN_VDD10

Can change to 2.2uH&4.7uF

1

C

HSIP
HSIN

LAN_X2

2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%

30
32

HSON

REFCLK_P
REFCLK_N

1 RL20
1 RL21
1 RL22

31
37
40

17
18

LAN_X1

ISOLATEB

LED3/EEDO
LED1/EESK
LED0

23

19
20

EC_SWI#

21 EC_SWI#

HSOP

25

20 CLK_PCIE_LAN
20 CLK_PCIE_LAN#

+3V_LAN

Close to Pin 27,39,12,47,48
22

0_0402_5% 16

PLT_RST#

1

1

2

2

CL29
0.1U_0402_16V4Z
1

C

ISOLATEB
+3V_LAN

31

WOL_EN#

1

QL1

1
2
2
47K_0402_5%
1
CL14
AO3413_SOT23
0.01U_0402_25V7K

1
RL16

1

25MHZ_20PF_7A25000012
1
1
CL27
27P_0402_50V8J

2
1

CL12
0.1U_0402_16V7K

2

2

RL23
0_0402_5%
@

1 LAN_X2

2

Reserved For 1.05V Crystal

CL26
27P_0402_50V8J
2

Vgs=-4.5V,Id=3A,Rds<97mohm

RL25
100K_0402_5%

YL1
LAN_X1 2

+3VALW

ENSWREG

3

1
0.1U_0402_16V4Z

+3VALW
2

2
CL11@

+3VALW TO +3V_LAN
RL4
0_0402_5%

+LAN_VDD10

1

RL9
@ 0_0402_5%

+3V_LAN

G

0_0402_5%

D

RL8

S

+3V_AVDDXTAL

RL7
15K_0402_5%

PJ20
JUMP_43X39
@
+3V_LAN

2
1

B

CL15
4.7U_0805_10V4Z
@ 2

1
CL8

B

1U_0402_6.3V4Z
2

UL2
LAN_MDI1+
LAN_MDI12
CL30

1
0.01U_0402_16V7K
LAN_MDI0+
LAN_MDI0-

1
2
3
4
5
6
7
8

TD+
TDCT
NC
NC
CT
RD+
RD-

TX+
TXCT
NC
NC
CT
RX+
RX-

16
15
14
13
12
11
10
9

RJ45_MIDI1+
RJ45_MIDI1CL31 1
1
CL32
RJ45_MIDI0+
RJ45_MIDI0-

RJ45_MIDI1+ 17
RJ45_MIDI1- 17
2 1000P_0402_50V7K 1
2
1
1000P_0402_50V7K
RJ45_MIDI0+ 17
RJ45_MIDI0- 17

RL26
2 75_0402_1%
2
75_0402_1%
RL27

RJ45_GND

RJ45_GND 17

NS681680

A

A

Compal Secret Data

Security Classification
Issued Date

2008/10/06

2009/10/06

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
RTL8103EL/RTL8111DL
Document Number

Rev
1.0

LA-6032P
Tuesday, March 23, 2010

Sheet
1

27

of

45

A

B

C

+PVDD1

2
JA1
JUMP_43X39

10U_0805_10V4Z
2
2

@

CA8

place close to chip

MIC1_L

29 MIC1_L
+MIC1_VREFO_L

RA24

MIC1_R_L
23
24

1
2
2.2K_0402_5% RA25
4.7U_0805_10V4Z
MIC1_R_L
2

CA21
1

MIC1_R_R

1

4.7U_0805_10V4Z

Digital Mic

CA22

2

RA26 1
2 INT_MIC_CLK_R
FBMA-L10-160808-301LMT 0603

18 INT_MIC_CLK

EC_MUTE#

1

31 EC_MUTE#

AZ_RST_HD#

21 AZ_RST_HD#

RA45
4.7K_0402_5%
2

1
CA12

MONO_IN
2
100P_0402_50V8J
SENSE_A

3/17 Add RA45
03/17 DGND-->AGND forAudio noise
+3VS

1

+MIC1_VREFO_L
@

2
1

25

38
AVDD2

AVDD1

46

39

PVDD2

3

GPIO1/DMIC_CLK

6

SDATA_OUT

5

RESET#

EAPD
SPDIFO

PCBEEP
MONO_OUT

36
35
31

SENSE A
MIC2_VREFO
SENSE B
MIC1_VREFO_R
LDO_CAP

CBP

10

BCLK

SDATA_IN

CBN

VREF

MIC1_VREFO_L

JDREF

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE
AVSS1
AVSS2

HP_L
HP_R

20K

PORT-B (PIN 21, 22)

Ext. MIC

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 48)

SENSE B

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-H (PIN 20)

29
29

Ext. HP

AZ_SYNC_HD

29

MIC_SENSE

29

NBA_PLUG

SENSE_A

2
RA10

1
20K_0402_1%

RA21

39.2K_0402_1%

21

AZ_BITCLK_HD 21
AZ_SDOUT_HD 21
AZ_SDIN0_HD_R

8

2
RA6

1
33_0402_5%

2

Beep sound

AZ_SDIN0_HD 21

EC Beep

47
48

31

EC_BEEP

21

PCH_SPKR

RA7
1
2
47K_0402_5%

20

PCI Beep
29

27

AC_VREF

19

AC_JDREF2 RA9

1 20K_0402_1%
1

34

1
CA14

2
2.2U_0603_6.3V4Z

26
37

1

CA17
2
2
0.1U_0402_16V4Z

03/12 CA15 SMT-->@ for Audio noise

@

CA13
1
2

RA8
1
2
47K_0402_5%

+MIC1_VREFO_R CA23 10U_0805_10V4Z
1
2

30
28

MONO_IN

0.1U_0402_16V4Z

1
RA12
10K_0402_5%

CA16
10U_0805_10V4Z

CA18
0.1U_0402_16V4Z

2

ALC259-VB5-GR_QFN48_7X7
AZ_RST_HD#

place close to chip

DGND

2
3

SYNC
GPIO0/DMIC_DATA

43
42
49
7

RA27
4.7K_0402_5%

32
33

2

18
1
2
CA15
2.2U_0603_6.3V4Z

HP_OUT_L
HP_OUT_R

MIC2_L
MIC2_R

Headphone out

place close to chip

29
29

MIC1_L
MIC1_R

Function

PORT-I (PIN 32, 33)

place close to chip

SPKR+
SPKR-

16
17

13

CA6

2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z

45
44

21
22

12

CA5

Codec Signals

39.2K

1

1

SPK_OUT_R+
SPK_OUT_R-

LINE2_L
LINE2_R

PD#

CA4

1

29
29

14
15

4

CA3

1

SPKL+
SPKL-

SPK_OUT_L+
SPK_OUT_L-

11

UA1

1

40
41

LINE1_L
LINE1_R

12/18 RA26 0ohm-->Bead for EMI request

18 INT_MIC_DATA

PVDD1

MIC1_R_R

1
2
1K_0402_5%

2

9

1

1K_0402_5%
1
2

DVDD

RA23
MIC1_R

29 MIC1_R

Impedance

SENSE A
@
0.1U_0402_16V4Z
2
1 0.1U_0402_16V4Z
+5VS
1
1
1
1
CA61
@
CA60 0_0603_5% CA59
@
CA58
@
2
2
2
2
10U_0805_10V4Z
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VS
0_0603_5%

+PVDD2

1

DVDD_IO

+MIC1_VREFO_R

Sense Pin

2
10U_0805_10V4Z

RA11

CA7
10U_0805_10V4Z
2
2

RA22 2.2K_0402_5%
2

2

place close to chip

+AVDD

1

2
10U_0805_10V4Z

1

1

1

2

+5VS
CA43

1

+3VS_DVDD
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1
CA44

CA56

2

1

CA1

1

1

CA2

Ext. Mic

RA2
2
1
0_0603_5%

0.1U_0402_16V4Z
1
1
CA57

0.1U_0402_16V4Z

E

2

RA1
2
1
+3VS
FBMH1608HM601-T_0603~D

D

03/17 DGND-->AGND for Audio noise

AGND

3

CA62
0.1U_0402_16V7K
@
CA63
INT_MIC_CLK_R 1

2
22P_0402_50V8J

2 0.1U_0603_50V7K

CA48 1

2 0.1U_0603_50V7K

CA49 1

2 0.1U_0603_50V7K

CA50 1

2 0.1U_0603_50V7K

(4.75V(4.56~4.94V))
300mA

1/21 UA2 pin5 +PVDD1--->+AVDD
+5VALW

W=40Mil
@ CA67

1

+AVDD
@ UA2

2
0.1U_0402_16V4Z

3/17 Del R861 R910

1
2

26,31,34,37,41 SUSP#

1
2
0_0402_5%
RA28
@
0.1U_0402_16V4Z CA70
@

3

IN
OUT

5

GND
SHDN

BYP

1

4
@

G9191-475T1U_SOT23-5 1
1
2

2

@ CA69

2.2U_0805_16V4Z

RA18 1
2
FBMH1608HM601-T_0603~D

CA68

CA47 1

0.1U_0402_16V4Z

2

4

4

/

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
HD Audio ALC272 Codec

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

28

of

45

A

B

C

USB+Audio FFC conn
Pin=20pin, pitch=0.5

D

Speaker Connector

+USB_VCCA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1

USB20_P1
USB20_N1

21
21

USB20_P0
USB20_N0

28
28
28
28
28
28

USB20_P1
USB20_N1
USB20_P0
USB20_N0

NBA_PLUG
MIC_SENSE
HP_R
HP_L
MIC1_R
MIC1_L

HP_R
HP_L
MIC1_R
MIC1_L

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
GND

28

SPKL+

SPKL+

FBMA-L11-160808-800LMT_0603
LA2 1
2
1

SPK_L1
1

JSPK1

CA19
@ 10U_0805_10V4Z
2

2

1

28

CA20
@ 10U_0805_10V4Z
2
LA3 1
2
FBMA-L11-160808-800LMT_0603

SPKL-

SPKL-

1

CA24
1U_0402_6.3V4Z
@

1
2
3
4
5
6

DA5

1
2
3
4
GND1
GND2
ACES_88231-04001
CONN@

3
1
2
28

SPKR+

SPKR+

FBMA-L11-160808-800LMT_0603
LA4 1
2
1

SPK_R1

CA25
@ 10U_0805_10V4Z
2

JP6

2

SPK_R1
SPK_R2
SPK_L1
SPK_L2

SPK_L2

2

1
1
2
3
4
5
6
7
8

PACDN042Y3R_SOT23-3
3

1

ACES_87151-2005N
CONN@

1
2
3
4
5
6
GND
GND

DA4

placement near Audio Codec
02/04 Update JP5 pin define

JP5

21
21

E

MIC1_L
MIC1_R
HP_L
HP_R

28

SPKR-

SPKR-

CA26
@ 10U_0805_10V4Z
2
LA5 1
2
FBMA-L11-160808-800LMT_0603

1

PACDN042Y3R_SOT23-3

CA27
1U_0402_6.3V4Z
@
SPK_R2

2

CONN@
JST_SM06B-XSRK-ETB(HF)

+3VALW

+USB_VCCA

R907
100K_0402_5%

10K_0402_5%

U48
8
7
6
5

+3VS
+3VS

USB_OC#0 21,31

2

R211
100K_0402_5%
1

1/27 Update P/N
FD4

H4

H5

H6

H7

20,26 BT_PWR#

H_4P0
@

1

H_4P0
@

1

1

H_4P0
@

H15

H3

C325
0.1U_0402_16V4Z

2

1

Q17

2
2

H_4P0
@

AO3413_SOT23

<>

C327
0.01U_0402_25V7K
1

CPU

Screw Hole

3

R212
1
2
47K_0402_5%

@
1

@
1

@
1

@

FD3

1

FD2

1

FD1

C326
0.1U_0402_16V7K

3

4.7U_0805_10V4Z

2

APL3510BXI-TRG MSOP 8

1

OUT
OUT
OUT
OC#

2

2
USB_EN#

USB_EN#

R857

GND
IN
IN
EN#

G

1
2
3
4

D

1
31

C636

BlueTooth Interface

1

1

1/27 Add R907 for USB_EN# PH

S

+5VALW
+5VALW

+BT_VCC
3

H8

H10

H12

H13

H16

H18

H2

H17

H19
H_2P6X2P1N
@

1

H_2P1N
@

1

H_2P3
@

1

H_2P3
@

1

H_2P3
@

1

H_2P3
@

1

H_2P3
@

1

H_2P3
@

1

H_2P8
@

1

1

1

(MAX=200mA)
H_2P3
@

H_5P0N
@
+BT_VCC

+5VS

+5VS

+5VS

+5VS

+5VS

+5VS

+5VS

1

1

1

1

1

1

1

2

C645
0.1U_0402_16V4Z
2

C708
1U_0402_6.3V4Z

2

2

@
C642
0.1U_0402_16V4Z

2

C643
0.1U_0402_16V4Z

2

C644
0.1U_0402_16V4Z

C647
0.1U_0402_16V4Z

2

1
C329
4.7U_0805_10V4Z

JBT1

20

BT_RST#

+3VS

1
R214

2
0_0402_5%

21
21

USB20_P6
USB20_N6

20

BT_DET#

1
R213

1
2
3
4
5
6

2
0_0402_5%

1
2
3
4
5 G1
6 G2

7
8

ACES_87213-0600G
CONN@

C328
0.1U_0402_16V4Z

1

2

C330
0.1U_0402_16V4Z

2

C648
0.1U_0402_16V4Z

C646
0.1U_0402_16V4Z

4

5

4

/
3

4

Compal Secret Data

Security Classification
2008/04/14

Issued Date

Q15B
2N7002DW-T/R7_SOT363-6

2009/04/14

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.
AMP/Audio Jack/HP/SPEAKER/VR

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

29

of

45

A

B

C

D

D3E suport
+3VALW
+1.8VS_OUT

UC1

11 PCIE_ITX_C_PRX_N1
11 PCIE_ITX_C_PRX_P1
CC8
CC9

11 PCIE_PTX_C_IRX_N1
11 PCIE_PTX_C_IRX_P1

1
1

2
2

3
4

PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

9
8

APRXN
APRXP

11
12

APTXN
APTXP

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

1 12mil 7
RC2
12K_0402_1%
JMB389@
SEL43
43
39
2

RC2 JMB385@
9.1K_0402_1%

APVDD
APV18
NC/TAV33

5
10
36

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO6/4
MDIO5
G/MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
41
42
24
40
29
28
27
26
25
23
22

NC/SPI_SCK
NC/SPI_CSN
NC/SPI_SO
NC/SPI_SI

30
33
34
35

APGND
NC/GND
NC/GND
NC/GND

6
31
32
38

GND

49

APCLKN
APCLKP

APREXT
SDDV/MDIO4
TXIN/NC

3/17 JMB385 co-lay

JMB389
RC3
12,15,20,26,27,31,32

1

PLT_RST#

1
2

2
1

100_0402_5%
0.1U_0402_16V4Z
JMB389@

2

CC13
JMB389@

RC3 JMB385@
0_0402_5%
2

3/23 JMB385 co-lay

XRSTN
XTEST

CPPE#
XD_CD#

13
14

MS_CD#
SD_CD#

15
16

CR1_CD1N
CR1_CD0N

17

CR1_PCTLN

CPPE_N
CR1_CD2N

40 mils
+VCC_OUT
33 CR_LED#

CR_LED#

21

+3VS

CR1_LEDN

21 CR_CPPE#_SB

R922 1

31 CR_CPPE#_EC

R921 1

2 0_0402_5%

QC1
1

3

CPPE#
1

place near pin 19,20 and 44.
CC5

0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2

1
RC125 JMB389@
1
2

RC124

@

S

2

RC128

D

CC4

0.1U_0402_16V4Z

2

+TVA33

CLK_PCIE_MCARD0#
CLK_PCIE_MCARD0

0.1U_0402_16V7K
0.1U_0402_16V7K

2

1

CC6
1
CC7

40mil 0_0402_5%

1

+TVA33

2 0_0402_5%
@
RC126

CC16

2

1

2N7002_SOT23-3
1
2
@ 0_0402_5%

JMB389@
0.1U_0402_16V4Z

place near pin 36
+1.8VS_OUT

3/19 co-lay 0 ohm
CH751H-40PT_SOD323-2

20mil
DC1
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SEL41
SDCLK_MSCLK_XDCE#
SEL24
XD_CLE
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MMC_D6
XD_SD_MMC_D7
XD_RE#
XD_RB#
XD_ALE

CC10

2

1

CC11
10U_0603_6.3V6M

20 CLK_PCIE_MCARD0#
20 CLK_PCIE_MCARD0

2

CC3

0.22U_0402_6.3V6K

1

CC2

1

1000P_0402_50V7K

10U_0603_6.3V6M

Power Circuit

1

0.22U_0402_6.3V6K

place near pin 10
1

CC1

22
1
G
10K_0402_5%

3/22 co-lay 0 ohm

place near pin 5

2
1
10K_0402_5%

20mil

1

22

1

CR_W AKE#

RC127
1

2

@

place near pin18

SD_CD#

2

2
0_0402_5%

place near pin37

Strapping setting

SEL33

Description

Pin name

High

low

Ϫ

MDIO14

on board

MDIO14

CR_LED
high active

2

add-in card

Ϫ

CR_LED
low active

JMB389-QGAZ0C_QFN48_7X7
JMB389@

+3VS

place 6 GND vias
XD_CLE

UC1 JMB385@
JMB385-QGAZ0C QFN 48P
+3VS

MDIO7
SD_CLK

3/23 JMB385 co-lay

@ RC14
1
100_0402_5%

SD_CD#
2
4.7K_0402_5%
MS_CD#
2
4.7K_0402_5%
XD_CD#
2
4.7K_0402_5%

JMB385@ 1
RC22
JMB385@ 1
RC23
JMB385@ 1
RC24

SDCLK_MSCLK_XDCE#

3/17 JMB385 co-lay
3

2
RC20

2
RC9

+VCC_OUT
3/18 22U change to 10U

1
@ CC14
2

1
CC15
2

0.1U_0402_16V4Z

XD_CD#

0.1U_0402_16V4Z

SD_CD#

@

10U_0805_10V6K

CC17

3/17 JMB385 co-lay

2

100_0402_5%

@ CC20
1
2

1

2

1

XD_CE#

2

2

1
RC17

2 @
10K_0402_5%

1
RC5

2

10K_0402_5%

200K_0402_5%

3/18 10K change to 200K

XD_CE#

@ RC16
1

100P_0402_50V8J

2

Place RC5, RC17, RC19 close to pin42

@ CC21
1
2
100P_0402_50V8J

SD_VCC
MS_VCC
XD_VCC

SD_CLK
SDCMD_MSBS_XDW E#
SD_CD#
XDW P#_SDW P#
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MMC_D6
XD_SD_MMC_D7

10
19
1
2
4
3
25
23
21
17
8
5

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3
MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
MS_CLK
MS_CD#
SDCMD_MSBS_XDW E#

12
11
14
18
20
16
9

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS

3

3/17 JMB385 co-lay

For EMI close to JREAD

13
22
43
CC18

1
RC19

MS_CLK

JREAD1

1
1K_0402_5%

SDCMD_MSBS_XDW E#
2
1
RC21
10K_0402_5%
JMB385@

SD_CLK

@ RC15
1

MDIO14

100P_0402_50V8J

3/19 remove 22P_0402

0.1U_0402_16V4Z

XD_RB#

1
10K_0402_5%

MS_CLK

0_0402_5%
2
0_0402_5%
2
0_0402_5%
2

100_0402_5%

+VCC_OUT

XDW P#_SDW P#

4

RC11
1
RC12
1
RC13
1

XD_ALE

@ CC19
2
1
2

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

35
36
37
38
39
40
41
42

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MMC_D6
XD_SD_MMC_D7

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP

26
27
28
29
30
31
32
33

XD_CD#
XD_RB#
XD_RE#
XD_CE#
XD_CLE
XD_ALE
SDCMD_MSBS_XDW E#
XDW P#_SDW P#

SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND

7
15
6
24
34
44
45
46

SEL33

RC25
1

0_0402_5%
2
JMB385@

SEL24

RC26
1

0_0402_5%
2
JMB385@

RC27
1

0_0402_5%
2
JMB389@

RC28
1

0_0402_5%
2
JMB385@

RC29
1

0_0402_5%
2
JMB389@

RC30
1

0_0402_5%
2
JMB385@

SEL41

SEL43

1
4

2.2U_0603_6.3V6K

CC12 close to pin43
For internal LDO in SD3.0

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/22

Deciphered Date

2011/01/22

Title

Card Reader JMB389

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

SDCMD_MSBS_XDW E#

CC12
2
JMB389@

TAITW_R013-P12-HM_44P_NR-T
CONN@

Issued Date

XDW P#_SDW P#

C

Rev
0.1
Sheet

Tuesday, March 23, 2010
D

30

of

45

A

B

C

D

E

+3VL_EC
KSI[0..7]

32 KSI[0..7]

+3VL

KSO[0..17]

32 KSO[0..17]

+3VL_EC

+EC_AVCC

C331

21
EC_SCI#
33 WL_BT_LED#

2

EC_SMB_CK2

R229 2

1 2.2K_0402_5%

EC_SMB_DA1

R228 2

1 2.2K_0402_5%

EC_SMB_CK1

R227 2

1 2.2K_0402_5%

TP_CLK

R225

1

2 4.7K_0402_5%

TP_DATA

R226

1

2 4.7K_0402_5%

+3VL

+5VS

2 10K_0402_5%
2 10K_0402_5%

1/27 +3VALW-->+3V_ALW
1 100K_0402_5%

+3V_ALW

21
21
21

3/22 Add CPPE to KBC
ON/OFFBTN#

R232 2

1 100K_0402_5%

KSO1

R234 2

1 47K_0402_5%

KSO2

R235 2

1 47K_0402_5%

3

30 CR_CPPE#_EC
18 EC_INVT_PWM
5 FAN_SPEED1
32
HDPLOCK
26 E51_TXD
26 E51_RXD
33 ON/OFFBTN#
33 PWR_SUSP_LED#
32 NUM_LED#

E51_TXD PL on Page 26
R775

2 100K_0402_5% PLT_RST#

1

R923 1

20 RTCCLK
2

1

C641

@
0.1U_0402_16V4Z

3/22 Add CPPE to KBC

1
R233

2
150K_0402_5%

3

+3VL

1

ACIN

22,33,35

CH751H-40PT_SOD323-2

OSC

EC_MUTE#
USB_EN#
USB_CHG_EN#
HDPINT
TP_CLK
TP_DATA

97
98
99
109

VGATE
WOL_EN#
VLDT_EN
LID_SW#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

SLP_CHG_M4_EC
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON
ACIN_D

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
SLP_CHG_M3_EC
SB_PWRGD
BKOFF#
WL_OFF#
CURS_LED#
EC_SEL

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

UMA_ENBKL
USB_OC#2
SLP_CHG#
SUSP#
PBTN_OUT#
USB_OC#0

V18R

124

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

XCLK1
XCLK0

R240
20M_0402_5%

4

37

G-Sensor

12/18 Add EC_MUTE#
EC_MUTE# 28
USB_EN# 29
USB_CHG_EN# 25
HDPINT 32
TP_CLK 33
TP_DATA 33

USB Charger
G-Sensor
2

VGATE 34,42
WOL_EN# 27
VLDT_EN 34,39
LID_SW# 33

WOL_EN#

EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
SPI_CLK 32
SPI_CS# 32
R773 1
R867 1 @

+5VL
2 10K_0402_5%
2 0_0402_5% SLP_CHG_M4

FSTCHG 37
BATT_FULL_LED# 33
CAPS_LED# 32
BATT_LOW_LED# 33
PWR_ON_LED# 33
SYSON 34,40

SLP_CHG_M4 22,25

1/21 Add SLP_CHG_M4

Add PWR_ON_LED#
VR_ON

34,42

2
1
R230 10K_0402_5%
EC_RSMRST# 21
EC_LID_OUT# 21
@
EC_ON 33,34
R868 1
2 0_0402_5% SLP_CHG_M3
SB_PWRGD 21
BKOFF# 18
WL_OFF# 26
CURS_LED# 32

3

SLP_CHG#

2
C340

UMA_ENBKL 12
USB_OC#2 21,25
SLP_CHG# 25
SUSP# 26,28,34,37,41
PBTN_OUT# 21
USB_OC#0 21,29

1/21 Add SLP_CHG_M3

SLP_CHG_M3 22,25

CURS_LED#
1
R862

2
100K_0402_5%

+3VALW

1/19 Change net name SLP_CHG-->SLP_CHG#
+3VL

1
4.7U_0805_10V4Z

EC_SEL

EC_VERSION

HIGH

KB926D3

LOW

KB926E0

R785
100K_0402_5%

@
KB926QFE0_LQFP128_14X14

@
2

EC_SEL

1

+3VL_EC

C343
15P_0402_50V8J

1
100P_0402_50V8J

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

ADP_I

0.22U_0603_16V4Z

EN_DFAN1 5
IREF
37
CHGVADJ 37

SPI Device Interface
SPI Flash ROM

2 C469

1

HDPACT 32

83
84
85
86
87
88

GPIO

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

HDPACT

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

1

2
C339

NC

15P_0402_50V8J
1
OSC

32.768KHZ_12.5PF_Q13MC14610002

D12
2

NC

CRY1 122
CRY2 123

1 C342

2

Y4
2

ACIN_D

PM_SLP_S3#
6
PM_SLP_S5#
14
EC_SMI#
15
ADAPTOR_SEL 16
17
18
19
EC_INVT_PWM
25
FAN_SPEED1
28
HDPLOCK
29
E51_TXD
30
E51_RXD
31
ON/OFFBTN#
32
PWR_SUSP_LED# 34
NUM_LED#
36
@
2 0_0402_5%

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

+3VL

G-Sensor

77
78
79
80

ADP_V 37

EN_DFAN1
IREF
CHGVADJ

PS2 Interface

R323
2 100K_0402_5%

1

ADP_V

ECAGND

20.01U_0402_25V7K

1

1

R238 2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

C336

BATT_TEMPA 36

ECAGND

LID_SW#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

ACOFF 37

BATT_TEMPA

68
70
71
72

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ACOFF

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

1

R223 1

36
36
7,32
7,32

AD

2

SUSP#

R224 1

+3VS

MISC

63
64
65
66
75
76

1/25 Add net PCH_OFF

PCH_OFF 34
EC_BEEP 28

EC_BEEP

2

1 2.2K_0402_5%

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

AGND

R231 2

12
13
37
20
38

21
23
26
27

PWM Output

69

EC_SMB_DA2

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
WL_BT_LED#

C335
2

1

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

GND
GND
GND
GND
GND

2 R236
47K_0402_5%
C337
2
1
0.1U_0402_16V4Z

1

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

C334

2
2
1000P_0402_50V7K

1

20,24 CLK_PCI_EC
12,15,20,26,27,30,32 PLT_RST#

1
2
3
4
5
7
8
10

11
24
35
94
113

+3VL

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

C333

1000P_0402_50V7K
1

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U12

0.1U_0402_16V4Z
1

67

9
22
33
96
111
125

1

21
GATEA20
21
KB_RST#
20,32
SERIRQ
20,32 LPC_FRAME#
20,32 LPC_AD3
20,32 LPC_AD2
20,32 LPC_AD1
20,32 LPC_AD0

C332

2
2
0.1U_0402_16V4Z

L38
2
1
0_0603_5%

SYSON

0.1U_0402_16V4Z
1
1

1

+3VL

L39
0_0603_5%

R786
100K_0402_5%

1

2

2

+EC_AVCC

4

1
C341

R909
100K_0402_5%

L40
2
1
0_0603_5%

4

2

@

2
0.1U_0402_16V4Z

1

ADAPTOR_SEL
/
R910
100K_0402_5%

2008/04/14

Issued Date

2

Compal Secret Data

Security Classification

2009/04/14

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.

B

C

D

ENE KB926C
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

31

of

45

A

B

C

Option 1:SPI Flash (2MB*1) for EC
Option 2:SPI Flash (256KB*1) for EC
SPI Flash (2MB*1) for SB (set up strap pin)

D

E

KSI[0..7]
KSO[0..17]

KSI[0..7] 31

KSO16

KSO[0..17] 31

KSO17

12/31 SMT memo control

KSO2

13.3 KEYBOARD CONN.

KSO1

11.6 KEYBOARD CONN.
1

SPI Socket: SP07000F500 & SP07000H900
2MB P/N:MXIC SA00002TO00 S IC FL 16M MX25L1605DM2I-12G SOP 8P ROM
256KB P/N:MXIC SA00003GK00 S IC FL 2M MX25L2005CMI-12G SOP 8P
+3VL

8

1
7

0.1U_0402_16V4Z

SPI_CS#

31 SPI_CS#

2

SPI_CLK

31 SPI_CLK

EC_SO_SPI_SI

31 EC_SO_SPI_SI

VCC

4

W
HOLD

1

S

6

C

5

VSS

D

Q

EC_SI_SPI_SO

2

EC_SI_SPI_SO 31

MX25L2005CMI-12G SO8
SPI_CLK

C634 1
2
100_0402_5%

1
R788

2 100P_0402_50V8J

12/18 R788 @-->100ohm and C634 @-->100P for RF request

LPC Debug Port

(Please place the PAD under DDR DIMM)

2

+3VS

+3VS_CURS
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
+3VS_CAPS
CAPS_LED#
CURS_LED#
NUM_LED#

@

H1

+3VS_MUM

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS_MUM

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

U13

3
C345

JKB2

12/31 SMT memo control

20mil

KSO0
JKB1
2
R247

1
300_0402_5%

+3VS_CURS
2
KSO2
R344
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
+3VS_CAPS R245 2
CAPS_LED#
CURS_LED#
NUM_LED#

1
300_0402_5%

KSO3
KSO5

6

5

7

4

PLT_RST#

LPC_AD3

8

3

LPC_AD2

LPC_AD1

9

2

LPC_AD0

LPC_FRAME# 10

1

+3VS

KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2

1 300_0402_5%

KSI3

+3VS

CAPS_LED# 31
CURS_LED# 31
NUM_LED# 31

KSI4
KSI0

10/10 New CURS_LED## for 11.3&13.6

ACES_88170-3400
ACES_88170-3400
CONN@

KSO4

+3VS

KSI5
KSI6

CONN@

1/27 Del R246
20,31

KSI1

SERIRQ
20,31

LPC_AD3

20,31

LPC_AD1

CAPS_LED#
NUM_LED#

LPC_AD2 20,31
LPC_AD0 20,31

CURS_LED#

10/10 New CURS_LED# cap for 11.3&13.6

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

1
C615

2
100P_0402_50V8J

1

2

LPC_CLK1 20,24
2

20,31 LPC_FRAME#

New keyboard

PLT_RST# 12,15,20,26,27,30,31

1
C344
1
C346
1
C347
1
C348
1
C349
1
C350
1
C351
1
C352
1
C353
1
C354
1
C355
1
C356
1
C357
1
C358
1
C359
1
C360
1
C361
1
C362
1
C363
1
C364
1
C365
1
C366
1
C367
1
C368
1
C369
1
C370
1
C372
1
C373

@

R248
22_0402_5%
1

DEBUG_PAD

@

2

1

3

C371
22P_0402_50V8J

G-Sensor

3

UG6
1

P3_5/SSCK/SCL/CMP1_2

P1_6/CLK0/SSI01

P3_7/CNTR0#/SSO/TXD1

P1_5/RXD0/CNTR01/INT11#

11

HDPACT

RG2 @
2

+3VS

1

SELF_TEST

2

RG3 2
GSENSOR@

1
4.7K_0402_5%

3

RG4 2
GSENSOR@

1GXOUT
4.7K_0402_5%

4

+3VS_HDP

RG9
47K_0402_5%
GSENSOR@

12

0_0603_5%
+3VS_HDP
GSENSOR@ DG1 CH751H-40PT_SOD323-2
1
2
2
2
CG12
UG3 GSENSOR@
1U_0402_6.3V4Z
CG13
GSENSOR@
1U_0402_6.3V4Z
1
5
VIN
VOUT
1
1
GSENSOR@

3

GND
SHDN#

BP

4

G9191-330T1U_SOT23-5

RG5 2
GSENSOR@

4

SELF_TEST

+3VS_HDP

4
6
8

9

Vdd1
Vdd2

Voutx
Vouty
Voutz
NC1
NC2
NC3
NC4
NC5

10
11
14
15
16

GND1
GND2

1
13

ST
PD
FS

Rev

3
5
7

VOUTXCG1
VOUTYCG2
VOUTZCG3

1
1
1

1GXIN
4.7K_0402_5%

Reserve Freescale

GSENSOR@
0.22U_0402_10V4Z

6
7

RESET#

P1_4/TXD0

XOUT/P4_7

P1_3/KI3#/AN11/TZOUT

VSS/AVSS

P1_2/KI2#/AN10/CMP0_2

XIN/P4_6

P4_2/VREF

VCC/AVCC

P1_1/KI1#/AN9/CMP0_1

MODE

P1_0/KI0#/AN8/CMP0_0

2 1ST@ 0.033U_0402_16V7K
2 1ST@ 0.033U_0402_16V7K
2 1ST@ 0.033U_0402_16V7K

CG9 0.1U_0402_16V4Z UG4
2ND@ 2
1VOUTX
2
CG10 0.1U_0402_16V4Z XOUT
2ND@ 2
3
1VOUTY
CG11
0.1U_0402_16V4ZYOUT
2ND@ 2
1VOUTZ4 ZOUT
9
+3VS_HDP
SELF_TEST

7
10
13

2ND@

0G-DET
SLEEP#
G-SELECT
ST

VDD

6

NC
NC
NC
NC
NC

1
8
11
12
14

VSS

5

31

HDPINT

RG6 2
GSENSOR@
4.7K_0402_5%
RG7 2
GSENSOR@
1K_0402_5%

1

8
9

1

1
CG7
0.1U_0402_16V4Z
GSENSOR@ 2

P4_5/INT0#/RXD1

10

1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_16V4Z
R5F211B4D34SP_LSSOP20
2
1STGSENSOR@

P3_3/TCIN/INT3#/SSI00/CMP1_0
P3_4/SCS#/SDA/CMP1_1

14
15

HDPLOCK 31
RG10 47K_0402_5%
2
1
GSENSOR@

VOUTZ

16

+3VS_HDP

17

VOUTX

18

VOUTY

1

19
20

EC_SMB_DA2 7,31

03/11 update G-sensor P/N
Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

Title

Compal Electronics, Inc.
SPI/LPC/PS2/MDC/FM/CIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

2

CG6
0.1U_0402_16V4Z
GSENSOR@

4

MMA7360LR2_LGA14

TSH35TR_LGA16

A

13

+3VS_HDP

1ST@

UG1
2
12

5

CG14
2
1

Change U55 to G9191-330T1U

+3VS_HDP

+3VS_HDP

1

+5VS

2

31

2

7,31 EC_SMB_CK2

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

32

of

45

A

B

C

D

E

Power Button & Lid switch
JPB1
1
2
3
4

ON/OFFBTN#

31 ON/OFFBTN#
1
1

2

+5VS

5
6

C386
0.1U_0402_16V4Z

P-TWO_161011-04021_4P-T
CONN@

12/15 C386 @-->0.1u

JLED1

03/10 Fine tune R813 R815 120ohm-->220ohm
31
31
31
31

1/27 Update footprint
51_ON#

LED/B Connector

+5V_ALW

35

DC_IN
PWR_ON_LED#
PWR_SUSP_LED#
BATT_FULL_LED#
BATT_LOW_LED#
HDD_LED
WIMAX_LED
WL_BT_LED#
MEDIA_LED

PWR_ON_LED#
PWR_SUSP_LED#
BATT_FULL_LED#
BATT_LOW_LED#

3

31 WL_BT_LED#

R812
R813
R814
R815
R816
R817
R818
R819
R820

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2

DC_IN_R
PWR_ON_LED#_R
PWR_SUSP_LED#_R
BATT_FULL_LED#_R
BATT_LOW_LED#_R
HDD_LED_R
WIMAX_LED_R
WL_BT_LED#_R
MEDIA_LED_R

120_0402_5%
220_0402_5%
120_0402_5%
220_0402_5%
120_0402_5%
120_0402_5%
120_0402_5%
120_0402_5%
120_0402_5%

Q14B

13
14

4

R257
10K_0402_5%

1

@

1
2
3
4
5
6
7
8
9
10
11
12

2N7002DW-T/R7_SOT363-6

5

EC_ON
2

31,34

1
2
3
4
5
6
7
8
9
10
11
12

GND1
GND2

1

ACES_87213-1200G

DC-IN LED

1/27 Del R808 R809 R810 R811

22,31,35

2

ACIN

1/27 +3VALW-->+3V_ALW and +5VALW-->+5V_ALW

2

DC_IN

6

Touch/B Connector
1/27 +3VALW-->+3V_ALW

03/11 Update JTP1 footprint

+3V_ALW

HDD LED

JTP1

TP_CLK
TP_DATA

LID_SW#

1
R864

LID_SW#_R
2
0_0402_5%
3

31 LID_SW#

TP_CLK
TP_DATA

12/24 Add R864

1
2
3
4
5
6
7
8

+5VS

2

31
31

2

1
Q14A
2N7002DW-T/R7_SOT363-6

D15

1
2
3
4
5
6
GND
GND

SATA_LED# 22

R790
HDD_LED

P-TWO_161021-06021_6P-T
CONN@

1

2
0_0402_5%

1

PACDN042Y3R_SOT23-3

12/17 Q8 Q9 R258 R259-->@, R790 R791-->SMT
LED_WIMAX# 26
3

3

WIMAX_LED

R791
1

2
0_0402_5%

Check control pin?

03/10 Q15-->@ and R260 @-->SMT (memo)
R260
2
0_0402_5%

CR_LED# 30

2

2

1

MEDIA_LED

6
@

Compal Secret Data

Security Classification
2008/04/14

Issued Date

2009/04/14

Deciphered Date

4

RC4
4.7K_0402_5%
@

1
Q15A
2N7002DW-T/R7_SOT363-6

1

4

Title

Compal Electronics, Inc.
LED/LID/PB/FB/SCREW HOLE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

33

of

45

A

B

C

D

+1.5V

+1.5VS

+5VALW

Inrush current = 0A

8
7
6
5

RUNON
1U_0402_6.3V4Z

2

SI4800BDY_SO8

4.7U_0805_10V4Z

2

2

2

C402

2

IRF8113PBF_SO8
C407

1

10U_0805_10V6K

2

R267
1.5VS_ENABLE

1
1

2

C410
0.1U_0603_25V7M
2
1

2

SUSP
2
Q11A
2N7002DW-T/R7_SOT363-6

+1.1VALW

1

1
3

6

4
1

1

5

2

2
6
2

1

2

2

2

1
1

D

EC_ON#

2
G
Q31
S
2N7002_SOT23-3

5

VGATE

Compal Secret Data

Security Classification
2008/04/14

Issued Date

1

2N7002DW-T/R7_SOT363-6

2009/04/14

Deciphered Date

Title

4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2
G
Q26
S
2N7002_SOT23-3

12/18 SYSON#-->SUSP
Q35A
2N7002DW-T/R7_SOT363-6
2
VR_ON 31,42

4

31,42

D

SUSP

@

3

2
G
Q28
S
2N7002_SOT23-3

6

Q35B

R278
470_0805_5%

1
1

D

SYSON#

3

2
G
Q27
S
2N7002_SOT23-3
2N7002DW-T/R7_SOT363-6

R330
470_0805_5%

@

1
1

1
1

D

SUSP

3

3

5

4

5
Q32B
2N7002DW-T/R7_SOT363-6

Q13B

SUSP

R280
470_0805_5%

4

41

D

2
G
Q23
S
2N7002_SOT23-3

+0.75VS

+1.1VALW

3

VR_ON#

R271
470_0805_5%

3 1

1
1

3

2

@
VLDT_EN#

VR_ON#

Q25B
2N7002DW-T/R7_SOT363-6
5
EC_ON 31,33

+1.5V

2

2

2
1

1

1

R277
470_0805_5%

SUSP

100K_0402_5%

2

R270
470_0805_5%

R331
470_0805_5%
@

2

Q25A
2N7002DW-T/R7_SOT363-6
VLDT_EN 2

VLDT_EN

+1.8VS

+3VS

2

+5VS

EC_ON#

3

31,39

3

2

R329
100K_0402_5%

6

R276
100K_0402_5%
VLDT_EN#

(OCP min=7.9A)

R800

VGATE#

3

4

(5A,200mils ,Via NO.= 10)

2

+5VL

R796

3

+5VL +5VL

@
PCH_OFF_R

Q41B
2N7002DW-7-F_SOT363-6
1 @
C908
4700P_0402_25V7K

< Discharge circuit >

100K_0402_5%

41

2

2

Q41A
2N7002DW-7-F_SOT363-6

1

Q40B
@
2N7002DW-7-F_SOT363-6
C904
4700P_0402_25V7K

+NB_CORE

+5VL

SUSP

Q10A
2N7002DW-T/R7_SOT363-6
2
SUSP# 26,28,31,37,41

1

6
PCH_OFF_R

5

SUSP

Q10B
2N7002DW-T/R7_SOT363-6
5
31,40
SYSON
4

2

100K_0402_5%

@

@
R906
470_0402_5%

@

4

1

2

@

4

2

@
PCH_OFF_R

3/23 install C906

R275

1

2

1

SYSON#

1
2
470_0805_5%
R905

1

R274
100K_0402_5%

1

VGATE#

0_0402_5%

2

+5VL +5VL

1/25 Add +5V_ALW to +5VALW Transfer
+3V_ALW to +3VALW Transfer

4

Q12B
2N7002DW-T/R7_SOT363-6

5

< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >

+3VALW
JUMP_43X118
1

4

1

@

@

2

2N7002DW-7-F_SOT363-6

1

1PCH_OFF_R 2
10K_0402_5%
Q40A
1

C903
0.1U_0402_16V4Z @

330K_0402_5%
@

3
@
R903
470_0402_5%

6
@
2

C905

@

@

@ R902
PCH_OFF

2

2
Q12A
2N7002DW-T/R7_SOT363-6

3

2

10U_0805_10V4Z

1

R904

2

2

R901
1
2
470_0805_5%

3/23 install C901

C902
10U_0805_10V4Z

1

4

@

1

@
SI7326DN-T1-E3_PAK1212-8
U50
1
2
5
3

+VSB

C901
0.1U_0402_16V4Z

2

2

C907
10U_0805_10V4Z

J3
2

1

2

+3V_ALW

JUMP_43X118
1 1

3

31

2

+3V_ALW to +3VALW Transfer

+5VALW

10U_0805_10V4Z

1

+VSB

2

+VSB

2N7002DW-T/R7_SOT363-6

SI7326DN-T1-E3_PAK1212-8
U49
1
2
5
3

@

4
2

2 SUSP

2 R266
1
330K_0402_5%
C409

R795 1

@

1

R268
10M_0402_5%

1

1

@

+VSB

Q13A

J2
2

C900

R272
470_0805_5%

1

C396
R262
10M_0402_5%

+5V_ALW

@

+ C622
330U_2.5V_M

C408
2

1

1

2

6

1

2 R261
1
750K_0402_1%

+5V_ALW to +5VALW Transfer

R900

1
4.7U_0805_10V4Z
2

1

0.01U_0402_25V7K

2

1

2

RUNON

330K_0402_5%

1

C406

1U_0402_6.3V4Z
2

2

2

2

2

1
2
3
IRF8113PBF_SO8

C395
0.01U_0402_25V7K

4.7U_0805_10V4Z

SI4800BDY_SO8
1

1 C392
4.7U_0805_10V4Z

1
C390

C906
0.1U_0402_16V4Z

S
S
S
G

8
7
6
5
4.7U_0805_10V4Z

1U_0402_6.3V4Z

1
2
3
4

Inrush current = 0A

Q11B
2N7002DW-T/R7_SOT363-6

5

Inrush current = 0A

1
C405

Q22
+3VS

1

+VSB

1M_0402_5%

+1.1VS

< +1.1VALW TO +1.1VS >

+3VALW
Q19
8 D
7 D
6 D
5 D

R279
470_0805_5%

1U_0402_6.3V4Z

R269
10M_0402_5%

< +3VALW TO +3VS >

C403

2

C388

1

1

C387

1

4

1

6

C394
4.7U_0805_10V4Z

1
2
3
4

S
S
S
G

1

1

1
1

D
D
D
D

4.7U_0805_10V4Z

Q18

1
2
3

3

+5VS

2

Q21

8
7
6
5

E

< +1.5V TO +1.5VS >

4

< +5VALW TO +5VS >

B

C

D

DC/DC Circuits
Rev
1.0

LA-6032P

Tuesday, March 23, 2010

Sheet
E

34

of

45

A

B

C

D

VIN

1

DC_IN_S2

2

PR1
1M_0402_1%
1
2

VIN

1
1

N1

1

PR2
5.6K_0402_5%

+

P

2

-

G

O

PACIN

37

4

LM393DG_SO8
PD1
GLZ4.3B_LL34-2

PR7
10K_0402_1%

VIN

1
PR8
10K_0402_1%

2

2

2

2

2

2

PACIN

1
1

3

PC6
.1U_0402_16V7K

22,31,33

PU1A

1

1
1
2

PC5
0.068U_0402_10V6K

ACIN

1

8

PR5
22K_0402_1%
1
2

PR6
20K_0402_1%

PR4
10K_0402_1%
1
2

2

PR3
84.5K_0402_1%

PC4
100P_0402_50V8J

2

2

1
2

@ PC19
680P_0402_50V7K

1

PC2
1000P_0402_50V7K

PC3
100P_0402_50V8J

2

PC1

2

@ SINGA_2DW -0005-B03

1

-

4

1

2

3

680P_0402_50V7K

-

1

2

2

+

@ PC18

1
1

+

1000P_0402_50V7K

7A_24VDC_429007.W RML

PJP1

1

DC_IN_S1

VS

PL1
SMB3025500YA_2P
1
2

PF1

DC30100A900

+CHGRTC

3.3V

PD2
RLS4148_LL34-2

Vin Detector

PR9
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3
N1

3

1

VS
2

PR13
1K_1206_5%

2

VIN

1

2
PR14
22K_0402_1%

51_ON#

N3

1

1

RLS4148_LL34-2

1

2

IN

+

PBJ1

2

2

PR18
560_0603_5%
1
2

1

PR19
560_0603_5%
1
2

PR21
100K_0402_1%
1
2

+RTCBATT
VL

PR22
2.2M_0402_5%
2
1

PR20
499K_0402_1%

1

@ MAXEL_ML1220T10

2

2

1

+3V_ALW

2

+1.1VALW P

@ JUMP_43X118

2

PJ3

1

1

+1.1VALW

2

+NB_COREP

@ JUMP_43X118

1

1

+NB_CORE

@ JUMP_43X118

(4.6A,180mils ,Via NO.= 9)
OCP(min)=5.26A

(7.6A,300mils ,Via NO.= 15)
OCP(min)=9.38A

1

@ PR25
66.5K_0402_1%

8

D

2

1

1

+5V_ALW

+1.5VP

2

@ JUMP_43X118

2

1

+VSB

+2.5VSP

2

2

2

+VDDNB

1

@ JUMP_43X118

+1.8VSP

2

2

1

+2.5VS

+3VLP

2

2

1

2

2

1

1

PACIN

Precharge detector
15.97V/14.84V FOR
ADAPTOR

+3VL

2

+5VALW P

PQ3
DTC115EUA_SC70-3

PJ15

1

1

+1.8VS

2

+0.75VSP

2

4

1

1

+0.75VS

@ JUMP_43X79

(1.3A,52mils ,Via NO.= 3)
OCP(min)=3A
+0.9V

(0.5A,20mils ,Via NO.= 1)
Compal Secret Data

Security Classification
2009/10/02

Deciphered Date

2010/10/02

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@ JUMP_43X79

(1.3A,52mils ,Via NO.= 3)
A

S

(100mA,40mils ,Via NO.= 2)

Issued Date

1

+5VL

@ JUMP_43X39

PJ10
+0.9VP

1

PJ17

1

@ JUMP_43X79

(2A,80mils ,Via NO.= 4)
OCP(min)=3A

1

@ JUMP_43X39

PJ9

1

2

(100mA,40mils ,Via NO.= 2)

(0.25A,10mils ,Via NO.=1)

PJ8

2

2

VL

@ JUMP_43X39

(120mA,40mils ,Via NO.= 1)
+VDDNBP

+1.5V

PJ7

1

@ JUMP_43X39

4

1

@ JUMP_43X118

PJ6

2

1

(8A,320mils ,Via NO.= 16)
OCP(min)=8.55A

(5A,200mils ,Via NO.= 10)
OCP(min)=8.1A

+VSBP

2

B

3

1

2

PC13
1000P_0402_50V7K

PR27
47K_0402_1%
2
2
1
G
PQ2
SSM3K7002FU_SC70-3

3

+5VALW P

PJ12

PJ5

3

PJ4

PR24
499K_0402_1%
PR26
191K_0402_1%

1

+CHGRTC

2

1

PR23
10K_0402_1%

1

2

1

(5A,200mils ,Via NO.= 10)
OCP(min)=7.9A

2

6

2

PJ2

1

5

-

2

PJ1
+3VALW P

2

1

3

+

O

1

7

1

2

3

1

ACON

2

EN0

37

LM393DG_SO8

P

38

PU1B

G

X7999651L01

2

4

PD5
RB715F_SOT323-3

1U_0805_25V4Z

PC12
1000P_0402_50V7K

PC10

1

PC11
1000P_0402_50V7K

GND
PC9
10U_0805_10V4Z

2

2

1

2

OUT

2

1

1
3

+CHGRTC

-

G920AT24U_SOT89-3
N2

B+

PR16
1K_1206_5%
PR17
200_0603_5%

3.3V

2

PR15
1K_1206_5%

RTC Battery
PU2

2

PD4

2

2
33

1
PC8
0.1U_0603_25V7K

2

PC7
0.22U_0603_25V7K

2

PR12
100K_0402_1%

1

1

1

2

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

PR10
68_1206_5%

2

PR11
200_0603_5%
CHGRTCP 1
2

2

PD3
RLS4148_LL34-2

1

1
1

1

2

BATT+

C

Title

Compal Electronics, Inc.
DCIN/DECTOR

Size

Document Number

Rev
1.0

LA6032P
Date:

Sheet

Tuesday, March 23, 2010
D

35

of

45

A

B

PL2
SMB3025500YA_2P
1
2
1

2
PR29
47K_0402_1%

+3VLP

PC15
1000P_0402_50V7K

@
PR30
1K_0402_1%

PH2 near main Battery CONN:
BAT thermal protection at 78 degree C
Recovery at 42 degree C

@ PD16
PJSOT24C_SOT23-3

1

For 13.3"

VL

1
3

1

1

PR36
6.49K_0402_1%
2
1

PC17
0.1U_0603_25V7K

2
2

2

@ SUYIN_200045MR009G171ZR

PR37
22K_0402_1%
PR31
34.8K_0402_1%

2

+3VLP

PR39
1K_0402_1%

2

3

2

BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA

1

GND
GND
GND
GND

@ PD17
PJSOT24C_SOT23-3

2

10
11
12
13

1
2
3
4
5
6
7
8
9

2

BATT_S1

1
2
3
4
5
6
7
8
9

2

PJP3

1

Rset = 3*Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)

2

@ SUYIN_200045MR009G171ZR

BATT+

1

2
PR28
1K_0402_1%

1

1

2

BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA

2

2

1

1

2

GND
GND
GND
GND

1
2
3
4
5
6
7
8
9

PC14
0.1U_0402_25V6

10
11
12
13

1
2
3
4
5
6
7
8
9

BATT_S1

1

1

VMB

PF2
10A_125V_451010MRL

PJP2

D

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C

PC16
0.01U_0402_25V7K

For 11.6"

C

PR38
10.2K_0402_1%

1
BATT_TEMPA 31

PR35
100_0402_1%

PU3
VCC TMSNS1

8

1

1

1

1

1

PR34
100_0402_1%

EC_SMB_DA1 31

GND RHYST1

7

3

OT1 TMSNS2

6

2

PH1
100K_0402_1%_NCP15WF104F03RC

1

EC_SMB_CK1 31

2

38

4

VS_ON

OT2 RHYST2

5

2

2

PR32
15.4K_0402_1%

1

2

G718TM1U_SOT23-8

2

PH2
100K_0402_1%_NCP15WF104F03RC

Rtmh at 92C = 7.71K,Rtml at 56C = 26.1K
Rset = 3* 7.31 = 21.9K ==> PR37 = 22K
PQ5
TP0610K-T1-E3_SOT23-3

3

B+

2

PR46
22K_0402_1%
1
2

1
2

Rtmh at 78C = 11.635.K,Rtml at 42C = 46.38K
Rset = 3* 11.635 = 34.91K ==> PR31 = 34.8K

@

2

1
2

PC22
0.1U_0603_25V7K

VL

+VSBP

1

3

@ PC21
0.22U_0603_25V7K

2

1
PR45
100K_0402_1%

3

Rhyst = ( 22K* 26.1K ) / ( 3* 26.1K - 22K) = 10.199K ==> PR38 = 10.2K

Rhyst = ( 34.8K* 46.38K ) / ( 3* 46.38K - 34.8K) = 15.468K ==> PR32

= 15.4K

D

S

PQ6
SSM3K7002FU_SC70-3

2
G

2

PC23
.1U_0402_16V7K

1

1

POK

1

PR48
0_0402_5%
2

1
38,39

3

PR47
100K_0402_1%

@

4

4

Compal Secret Data

Security Classification
Issued Date

2009/10/02

Deciphered Date

2010/10/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Compal Electronics, Inc.
BATTERY CONN / OTP
Document Number

Rev
1.0

LA6032P
Tuesday, March 23, 2010
D

Sheet

36

of

45

PC68
10U_1206_25V6M
2
1

4
PC26
4.7U_0805_25V6-K
2
1

PC25
4.7U_0805_25V6-K
2
1

PC24
4.7U_0805_25V6-K
2
1

2
1

ICOMP

CSIN

20

VCOMP

CSIP

19

LX_CHG
DH_CHG

PHASE

8

VREF

UGATE

17

1

D

2
1

CSOP

PC33
0.1U_0603_25V7K

PQ16
AO4466_SO8

S

2 PACIN
G
PQ17
SSM3K7002FU_SC70-3

2

4

PR65
2.2_0603_5%

PL4
10U_LF919AS-100M-P3_4.5A_20%
1
2CHG

PR67
0.02_1206_1%
1

4

2

3

BATT+

10

ACLIM

VDDP

15

PR75
20K_0402_1%

11

VADJ

LGATE

14

GND

PGND

13

2

12

PQ19
AO4466_SO8

4

26251VDD

1

2

DL_CHG

1

PD12
RB751V-40TE17_SOD323-2

6251VDDP

3
2
1

6251aclim

2

PR74
4.7_0603_5%
PC45
4.7U_0805_6.3V6K

PC42
10U_1206_25V6M
2
1

16

PC41
10U_1206_25V6M
2
1

BOOT

PC40
0.1U_0603_25V7K
BST_CHGA 2
1
2

CHLIM

PR70
0_0603_5%
BST_CHG 1

1

9

1

5
6
7
8

ICM

18

PC32
0.047U_0603_16V7K
1
2
PR62
20_0603_5%
2
1
PR63
20_0603_5%
PC37
0.1U_0603_25V7K
1
2

1

21

2

3

CSOP

1

1SS355_SOD323-2

1

CELLS

2

CSON

2

CSON

4

PR61
20_0603_5%
1
2

VIN

PD11

3

EN

22

7

PR60
200K_0402_1%
1
2

PQ14
DTC115EUA_SC70-3

5
6
7
8

DCIN

PC30
0.1U_0603_25V7K
2
1

3
2
1

2
PC29
2.2U_0603_6.3V6K
2
1

ACOFF

2

1SS355_SOD323-2

@ PC44
@ PR69
680P_0603_50V7K 4.7_1206_5%

2
3

PR73
26.7K_0402_1%
6251VREF
1
2

ISL6251AHAZ-T_QSOP24

PR76
15.4K_0402_1%
1
2
1

31 CHGVADJ

VDD

DCIN

24
23

1

PR72
100K_0402_1%

2

6251VREF

1

ACOFF

PD9

PR56
10K_0402_1%

SUSP# 26,28,31,34,41

2

ADP_I

VIN

1

ACSET ACPRN

6

PR66
47K_0402_1%
1
2

PR54
47K_0402_1%
1
2

1

3

PC39
.1U_0402_16V7K

1

2

IREF

1

31

PU5
1

5

6.81K_0402_1%
2

1
2
@ PC38
100P_0402_50V8J
1
2

2

1

PR71
31
174K_0402_1%

2

2

1

0.01U_0402_25V7K

8
7
6
5

RB715F_SOT323-3

2
6251_EN

6800P_0402_25V7K
2

S

PC43
0.01U_0402_25V7K

ACOFF

PR64

AO4435_SO8

1

2FSTCHG

1

3

PC36
1
2

PR68
22K_0402_5%
1
2

PQ20
DTC115EUA_SC70-3

31

1
2

PQ18
SSM3K7002FU_SC70-3

PQ9
1
2
3

PD8

2

1

D

2
G

ACON

PR59
100K_0402_1%

1
2

PC35
1

2

PQ12
DTC115EUA_SC70-3

3

@ PC34
680P_0402_50V7K
1
2

CSON

DCIN

PR55
100K_0402_1%
2
1

2
1
1
3

1
3

PC31
.1U_0402_16V7K

S

PACIN

2

CHG_B+

1

6251VDD

PR57
10K_0402_1%
2
1

FSTCHG

B+

CSIN

1

2

2

PC28
5600P_0402_25V7K

PR58
150K_0402_1%

PQ15
SSM3K7002FU_SC70-3

2

PR53
100K_0402_1%

1

D

2
G

PACIN

3

PD10
1SS355_SOD323-2
1
2

PQ13
DTC115EUA_SC70-3

35

2

1

1
2

3

1

P3

31

B+

PQ10 TP0610K-T1-E3_SOT23-3 PR51
10_0603_5%
3
1
1
2

2

PC27
0.1U_0603_25V7K

2

35

4

CSIP

PR50
200K_0402_1%
PQ11
DTA144EUA_SC70-3
PR52
47K_0402_1% 2

1

1

1

1

P3
8
7
6
5

PC127
10U_1206_25V6M
2
1

PQ8
AO4407A_SO8
1
2
3

PL3
HCB2012KF-121T50_0805

3

P2
1
2
3

4

8
7
6
5

4

VIN

PR49
0.033_1206_1%

D

1

PQ7
AO4435_SO8

C

PC47
10U_1206_25V6M
2
1

B

PC69
10U_1206_25V6M
2
1

A

PR77
31.6K_0402_1%

3

2

3

VIN

1

Iadapter=0~2.368A(45W) CP=Iadapter*0.92 CP=2.178A

CC=0.25A~3A

PR78
309K_0402_1%

CHGVADJ=(Vcell-4)*9.445

IREF=1.096*Icharge

Vcell

IREF=0.254V~3.048V

4V

VCHLIM need over 95mV

4.2V

1.882V

4.35V

3.2935V

CHGVADJ
2

PR79
10K_0402_1%
1
2

ADP_V 31

1

1

0V

PC46
.1U_0402_16V7K

2

2

PR80
47K_0402_1%

CP mode
Vaclim=2.39*(20K//152K/(20K//152K+26.7K//152K))=1.04596V
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.04596V, Iinput=2.178A

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/02

Deciphered Date

2010/10/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

CHARGER
Rev
1.0

LA6032P

Tuesday, March 23, 2010
D

Sheet

37

of

45

5

4

3

2

1

2

1

PC48
1U_0603_10V6K

2VREF_51125

D

D

B++

PL5

PR86
13K_0402_1%
1
2

PR87
30K_0402_1%
1
2

PR88
20K_0402_1%
1
2

PR89
19.6K_0402_1%
1
2

B++

5

1

PC52
10U_1206_25V6M

3
2
1

C

1

4

1

PC64
150U_V_6.3VM_R18

PC62
680P_0603_50V8J

2

1
1

PC66
.1U_0402_16V7K

VL

2

+5VALWP

+

3
2
1

S

PR82
4.7_1206_5%

5

2

NC

AON7702L_DFN8-5

18

VREG5

VIN

4

36,39

PL7
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

RT8205EGQW _W QFN24_4X4

2

PR96
@ 0_0402_5%

1
3

3

S

POK

PQ24

PC60
4.7U_0805_10V6K

1

2VREF_51125

PQ37
SSM3K7002FU_SC70-3

2

LG_5V

B++

D

2
G

1

19

2
PC61
0.1U_0603_25V7K

1

1
2
G

2

LGATE1

ENTRIP2

D

1

LGATE2

ESR = 18m Ohm
PQ36
SSM3K7002FU_SC70-3

ENTRIP1

3

2
FB1

REF

4

FB2

LX_5V

13
2

1

1

TONSEL

UG_5V

20

2
ENTRIP1

Total Capacitor = 150 uF
B

PC51
2200P_0402_50V7K

ENTRIP2

6

21

PHASE1

PC67
1U_0402_6.3V6K

F = 305kHz

2

B+

5

UGATE1

PHASE2

PR94
499K_0402_1%
1
2
PR95
100K_0402_5%

Imax = 3.5A

UGATE2

EN0

1
2
3

2

PR93
PC55
2.2_0603_1% .1U_0402_16V7K
BST_5V 1
2 1
2

4

PC63
680P_0603_50V8J
2
1

150U_V_6.3VM_R18

35

22

EN

AON7702L_DFN8-5

+

Ipeak = 5A

12

23

BOOT1

17

LG_3V
PQ23

PGOOD

BOOT2

16

1
2
3

1

PC58

5

PR84
4.7_1206_5%
2
1

PL6
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

+3VALWP

VREG3

1

8
PR92
2 1
2 BST_3V 9
2.2_0603_1%
PC54
UG_3V
10
.1U_0402_16V7K
LX_3V
11
1

PQ22
AON7408L_DFN8-5

24

GND

4
C

PR91
121K_0402_1%
2

VO1

VO2

SKIPSEL

7

P PAD

15

25

ENTRIP2

PU6

1

14

2

AON7408L_DFN8-5

PR90
121K_0402_1%
1
2
PC53
4.7U_0805_10V6K
2
1

PQ21

PC65
.1U_0402_16V7K
1

5

1
2

PC50
10U_1206_25V6M

1
2

1
2

@ PC56
1U_0603_25V6K

+3VLP

2
PC49
2200P_0402_50V7K

1

B+

ENTRIP1

HCB4532KF-800T90_1812

2

Ipeak = 5A

B

Imax = 3.5A
F = 245kHz
Total Capacitor = 150 uF

2

VL

1
2

D

S

PQ38
SSM3K7002FU_SC70-3

2
G
2
1
PR85
42.2K_0402_1%

PR83
100K_0402_1%

1

1

2

VS

3

VS_ON

@ PC59
0.01U_0402_16V7K

36

ESR = 18m Ohm

1

PR81
100K_0402_1%

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/02

Issued Date

Deciphered Date

2010/10/02

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

+5VALWP/+3VALWP
Size

Document Number

Rev
1.0

LA-6032P
Date:

Tuesday, March 23, 2010

Sheet
1

38

of

45

5

4

3

2

1

PL8
HCB2012KF-121T50_0805

1

NC

4
1

PGND

RT8209BGQW_WQFN14_3P5X3P5

8

GND
7

1

PC71
4.7U_0805_25V6-K

B+

D

PC76
4.7U_0805_10V6K

+1.1VALWP

PC74
220U_6.3V_M

DL_1.1V

2

9

PR105
4.7_1206_5%

10

PR108
4.7K_0402_1%
1
2

Ipeak = 4.6A

1
+

Imax = 3.22A
2

F = 314kHz
Total Capacitor = 550 uF
ESR = 8.5m Ohm
C

1

C

1

3
2
1

VDDP
LGATE

+5V_ALW

1

PGOOD

2

PC75
4.7U_0603_6.3V6K

1

2

15

1

FB

6

1

5

11

LX_1.1V
2
PR107
9.1K_0402_1%

CS

PC77
680P_0603_50V7K

12

VDD

0.1U_0603_25V7K

PQ27

PHASE

DH_1.1V

AO4712_SO8

VOUT

4

13

2

5
6
7
8

3

UGATE

1

3
2
1

TON

BOOT

2

2

PL9
1.8UH_1164AY-1R8N=P3_9.5A_30%
1
2

PC73
BST_1.1V

2

PR106
100_0603_1%
1
2

+5V_ALW

PU7

EN/DEM

2

PC72
@.1U_0402_16V7K

14

POK

PR104
2.2_0603_5%
1
2

2

1
4

PR103
0_0402_5%
1
2
1

36,38

PQ26

PR102
255K_0402_1%
1
2

AO4466_SO8

2

5
6
7
8
D

PC70
4.7U_0805_25V6-K

1.1V_B+

2

PR109
10K_0402_1%

PL16
HCB2012KF-121T50_0805

1

B+

PC95
4.7U_0805_25V6-K

2
1

4

RT8209BGQW_WQFN14_3P5X3P5

PC124
4.7U_0805_10V6K

+NB_COREP

Ipeak = 7.6A

1
+

Imax = 5.32A
2

F = 315kHz
Total Capacitor = 550 uF
ESR = 5.63m Ohm

1

PR166
2.7K_0402_1%
1
2

PC94
220U_D2_4VM

DL_NB_CORE

2

9

+5V_ALW

PR161
4.7_1206_5%

2
PR122
13.7K_0402_1%

1

10

1

PGND

LGATE

2

1
7

8

GND

PGOOD

1

2

VDDP

11

PQ40

FB

2

6
PC89
4.7U_0603_6.3V6K

LX_NB_CORE

12

5

NC

CS

PC85
680P_0603_50V7K

14

15

PHASE

VDD

1

5

VOUT

DH_NB_CORE 0.1U_0603_25V7K

13

AON7702L_DFN8-5

4

PL15
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2

2

3
2
1

3

UGATE

2

PR142
100_0603_1%
1
2

+5V_ALW

TON

1

B

PC90
BST_NB_CORE1

BOOT

2

1

PU14

EN/DEM

2

PC125
@.1U_0402_16V7K

2

3
2
1

31,34 VLDT_EN

AON7408L_DFN8-5

4
PR120
2.2_0603_5%
1
2

1

B

PQ39

5
PR165
255K_0402_1%
1
2
PR123
0_0402_5%
1
2

PC93
4.7U_0805_25V6-K

NB_CORE_B+

PR119
10K_0402_1%
A

2

A

Compal Secret Data

Security Classification
2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
+1.1VALWP/+NB_COREP
Document Number

Rev
1.0

LA6032P
Tuesday, March 23, 2010

Sheet
1

39

of

45

5

4

3

2

1

PL10
HCB2012KF-121T50_0805

PR110
255K_0402_1%
1
2

10
9

DL_1.5VP

+5V_ALW

PQ29
AO4712_SO8

4

RT8209BGQW_WQFN14_3P5X3P5
2

C

LGATE

1

1

PGND

7

2

GND

PGOOD

8

6
PC83
4.7U_0603_6.3V6K

1

NC

VDDP

LX_1.5VP
2
PR115
15.4K_0402_1%

1

FB

1
2

@ PC57
1U_0603_25V6K

1
2

D

PC86
4.7U_0805_10V6K

+1.5VP

PC82
220U_6.3V_M

5

11

2

12

CS

0.1U_0603_25V7K

PR113
4.7_1206_5%

14
PHASE

VDD

DH_1.5VP

1

VOUT

4

13

2

3

UGATE

2

PC84
680P_0603_50V7K

TON

1

5
6
7
8

2

+
2

PL11
1.8UH_1164AY-1R8N=P3_9.5A_30%
1
2

PC81
BST_1.5VP

3
2
1

PR114
100_0603_1%
1
2

15

1

PU8

EN/DEM

2
+5V_ALW

PC80
@.1U_0402_16V7K

1

B+

3
2
1

PR112
2.2_0603_5%
1
2

BOOT

SYSON

1

4

PR111
0_0402_5%
1
2
1

31,34

PC128
47U_25V_M

PQ28
AO4466_SO8

2
PC79
4.7U_0805_25V6-K

2

5
6
7
8

1

D

PC78
4.7U_0805_25V6-K

1.5V_B+

1
+
2

Ipeak = 8A
Imax = 5.6A
F = 313kHz
C

Total Capacitor = 880 uF

PR116
10K_0402_1%
1
2
1

ESR = 5.67m Ohm

2

PR117
10K_0402_1%

B

B

PU9
APL5508-25DC-TRL_SOT89-3

PJ11
1

1

2

2

2

@ JUMP_43X39

IN

OUT

3

1

2

1
2

PC87
1U_0603_10V6K

+2.5VSP

GND
1

+3VS

PC88
4.7U_0805_6.3V6K

A

A

Compal Secret Data

Security Classification
2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
1.5VP/2.5VSP
Document Number

Rev
1.0

LA6032P
Tuesday, March 23, 2010

Sheet
1

40

of

45

5

4

3

2

1

+1.5V
D

PJ13
@ JUMP_43X79

+1.5V

2

2

1

1

D

VREF

NC

4

VOUT

NC

+5V_ALW

2
1

7

PU12

2

1
PC99
4.7U_0805_6.3V6K

PR125
1K_0402_1%

2

G2992F1U_SO8

2

VCNTL

6

+3V_ALW

5

GND

NC

3

VREF

NC

7

4

VOUT

NC

8

TP

9

2

PC100
1U_0603_6.3V6M

2
PQ31

1

+0.9VP

2

1

S

PR127
1.5K_0402_1%

PC101
.1U_0402_16V7K

@ PC102
.1U_0402_16V7K

SSM3K7002FU_SC70-3

2

C

D

2
G

2

PR126
0_0402_5%
1
2

VR_ON#

1

34

1

PC98
10U_0805_6.3V6M

1

1

G2992F1U_SO8

3

2
PQ30

2

PC96
0.22U_0402_10V4Z

+0.75VSP

2

PR124
1K_0402_1%

2
G
1

2
1
PC97
0.1U_0402_10V7K

S

1

1

D

3

300K_0402_1%

VIN

2

2

TP

PC92
1U_0603_10V6K

9

1

8
2

PR118
1K_0402_1%

PR121

34 SUSP

PJ14
@ JUMP_43X79

1

3

6
5

1

NC

1

VCNTL

GND

1

PC91
4.7U_0805_6.3V6K

1
2

VIN

2

1

PU10
1

C

PC103
10U_0805_6.3V6M

SSM3K7002FU_SC70-3

PR178
200K_0402_1%
1
2

SUSP# 26,28,31,34,37

1

B

PR179
316K_0402_1%

PC138
0.22U_0402_10V4Z

2
11

MP2121DQ-LF-Z_QFN10_3X3

1

PR182
4.7_1206_5%

2

TP

+1.8VSP
PC145
22U_0805_6.3V6M

POK

6

1

BS

7

1

IN

8

2

PR181
0_0402_5%

5

IN

PL17
2.2UH_SILM320A-2R2_1.6A_30%
1
2

9

PC144
22U_0805_6.3V6M

2

SW

2

1

SW

10

2

PC142
10U_0805_10V4Z

2

JUMP_43X79
@

4

GND

1

3

EN/SYNC

GND

1

2

FB

2

2

2
PC141
10U_0805_10V4Z
1
2

2

1

1

PC140
0.1U_0402_25V6
2
1

1

1

PC139
.1U_0402_16V7K
1

PJ16
+5V_ALW

PU11

1

PR180
402K_0402_1%
2
1

+1.8VSP

@ PD15
B340A_SMA2

2

B

PC143
680P_0603_50V7K

Ipeak = 1.3A
Imax = 0.91A

Total Capacitor = 44 uF
ESR = 2.5m Ohm

A

A

Compal Secret Data

Security Classification
2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
0.75VSP/0.9VP/1.8VSP
Document Number

Rev
1.0

LA6032P
Tuesday, March 23, 2010

Sheet
1

41

of

45

B

C

D

E

PL12
HCB2012KF-121T50_0805

CPU_B+
PC104
33P_0402_50V8J
2
1

PR129
2_0603_5%
1
2

UGATE_NB

1

7

PHASE0

SVC

PGND0

5
6
7

ENABLE

LGATE0

ISL6265AHRTZ-T_TQFN48_6X6

RBIAS

PVCC

32

3
2
1
4

+5VS
LGATE0

31
30

8

OCSET

LGATE1

29

9

VDIFF0

PGND1

28

PC119
1U_0603_16V6K

LGATE0

1

PC115
10U_1206_25V6M
2
1
PR148
4.7_1206_5%

PR149
12.7K_0402_1%

PC117
680P_0603_50V7K

PC118
2
1
0.1U_0603_16V7K
2

ISP0

27

1

PR153
4.53K_0402_1%

26

TP

25

49

ISN1
24

ISP1
23

COMP1

VW1
22

21

VDIFF1

FB1
20

19

VSEN1
18

RTN1
17

VSEN0

RTN0
16

ISP0

+CPU_CORE_0

3

ISP0
ISN0
VSEN0

ISN0

PR156
2
0_0402_5%

15

PR155
0_0402_5%

BOOT1

ISP0

CPU_VDD0_RUN_FB_H

VW0

VSEN1

7

UGATE1

13

PR154
2
1
10_0402_5%

3

1

+CPU_CORE_0

PHASE1

COMP0

2 VSEN1

12

FB0

ISN0

11

14

10

3

ISN0

UGATE0

33

4

2
2

34

PHASE0

1

1

UGATE0

SVD

2

PC116
0.22U_0603_10V7K

5

PWROK

PC114
10U_1206_25V6M
2
1

37
UGATE_NB

39

38
PHASE_NB

40
PGND_NB

LGATE_NB

41

42
RTN_NB

OCSET_NB

44

43
VSEN_NB

45

46

BOOT0

4
1

FB_NB

35

3

PR150
0_0402_5%

PR152
95.3K_0402_1%
2
1

36

BOOT0

1 2

VR_ON
PR151
21.5K_0402_1%
2
1

1
PR147
0_0402_5%2

BOOT_NB

PGOOD

2

PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%

2

ISL6265_PWROK
2

PC111
220U_D2_4VM

2

31,34

CPU_SVD
CPU_SVC

OFS/VFIXEN

2

PR145
2.2_0603_1%
BOOT0 1
2 1

PQ35
TPCA8028-H_SOP-ADVANCE8-5

7
7

1

BOOT_NB

3
2
1

H_PWRGD_L

2
@ PR146 100K_0402_5%
2
PR144 100K_0402_5%

4

PHASE0

1

20

1

FSET_NB

1

COMP_NB

47
VCC

VIN

48

1
2

2
VGATE

+

PQ34
TPCA8030-H_SOP-ADV8-5

2

2

1

1
2
31,34

2

LGATE_NB

UGATE0
PU13

PC112
680P_0603_50V7K

CPU_B+

UGATE_NB

@ PR143
105K_0402_1%

1

PHASE_NB

@ PR141
10K_0402_1%

2

7,20 H_PWRGD

1 2

PQ33
AO4712_SO8

PHASE_NB

PR140
105K_0402_1%

+VDDNBP

PR132
4.7_1206_5%

3
2
1

PR136
5.49K_0402_1%
2
1

1

PC110
0.22U_0603_10V7K
4

5

@ PR138
105K_0402_1%

2

2

2
PR137
0_0402_5%

LGATE_NB

CPU_VDDNB_RUN_FB_H

2

1

PC113
0.1U_0603_25V7K

+
2

PL13
4.7UH_SIQB74B-4R7PF_4A_20%
1
2

3
2
1

PR131
2.2_0603_1%
BOOT_NB 1
2 1

PR135
0_0402_5%
2
1
PR139
0_0402_5%
2
1

2

PR134
2_0603_5%

+3VS

1

+5VS

B+

PQ32
AO4466_SO8

4

PHASE_NB

PR130
22K_0402_1%
2
1
@ PR133
10_0402_5%
1
2 +VDDNBP

1

+
2

1

1

1

PC108
1000P_0402_50V7K
2
1

PC109
0.1U_0603_16V7K

CPU_B+

@ PC123
47U_25V_M

1

PC105
1000P_0402_50V7K

5
6
7
8

+5VS

1

1

5
6
7
8

2

PC107
47U_25V_M

1

PR128
44.2K_0402_1%

PC106
10U_1206_25V6M
2
1

2

2
1

1

A

0_0402_5%
2
1 RTN0
CPU_VDD0_RUN_FB_L

PR157

PR158
10_0402_5%
1
2

7

DIFF_0

2

1
@ PR159
1K_0402_5%

VW0

PR160
PC120
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1

2

1

COMP0

PC121
180P_0402_50V8J
PR162
1K_0402_5%
2
1

PR163
2

1

PC126
2
1

2

1

PC122
1000P_0402_50V7K
4

PR164
6.81K_0402_1%
2
1

1

54.9K_0402_1% 1200P_0402_50V7K
@

PR168
36.5K_0402_1%

Compal Secret Data

Security Classification
2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

Compal Electronics, Inc.

2

4

+1.5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

+CPU_CORE
Rev
1.0

LA6032P

Tuesday, March 23, 2010

Sheet
E

42

of

45

V ersion Change L ist ( P. I. R . L ist ) for Pow er Circuit
P age#

T itle

D ate

R equest
O w ner

2009/11/10

POWER

Issue D escription

Solution D escription
Release

P38

BATTERY CONN / OTP

2009/12/03

POWER

PR31 change to 34.8k

DVT

P38

BATTERY CONN / OTP

2009/12/03

POWER

PR32 change to 15.4k

DVT

P38

BATTERY CONN / OTP

2009/12/03

POWER

PR37 change to 22k

DVT

P38

BATTERY CONN / OTP

2009/12/03

POWER

PR38 change to 10.2k

DVT

P39

CHARGER

2009/12/03

POWER

PC24,25,26 size change to 4.7uf 0805

DVT

P43

0.75VSP/0.9VP/1.8VSP

2009/12/03

POWER

PR121 change to 300k

DVT

P43

0.75VSP/0.9VP/1.8VSP

2009/12/03

POWER

PC96 change to 0.22uf

DVT

P43

0.75VSP/0.9VP/1.8VSP

2009/12/03

POWER

PR125 change to 1k

DVT

P43

0.75VSP/0.9VP/1.8VSP

2009/12/03

POWER

PR127 change to 1.5k

DVT

P44

+CPU_CORE

2009/12/03

POWER

Delete PR142

DVT

P44

+CPU_CORE

2009/12/03

POWER

PR131, PR145 change to 2.2 ohm

DVT

P44

+CPU_CORE

2009/12/03

POWER

PR132 change to 4.7_1206_5%

DVT

P44

+CPU_CORE

2009/12/03

POWER

PC112 change to 680P_0603_50V7K

DVT

P39

CHARGER

2010/01/29

POWER

Add PC47,68,69,127 10U_1206_25V6M

PVT

P41

+1.1VALWP/+NB_COREP

2010/02/03

POWER

Add PC70 4.7U_0805_25V6-K

PVT

P41

+1.1VALWP/+NB_COREP

2010/02/03

POWER

PL9 change to 1.8UH_9.5A_30%

PVT

P44

+CPU_CORE

2009/12/03

POWER

PL13 change to 4.7UH_4A_20%

PVT

P37

CHARGER

2009/02/08

POWER

Move PR18,PR19 to connect PBJ1

PVT2

Compal Secret Data

Security Classification
Issued Date

2009/10/02

Deciphered Date

2010/10/02

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
Power PIR

Size
Document Number
Custom
Date:

Tuesday, March 23, 2010

Rev
1.0

LA6032P
Sheet

43

of

45

5

4

3

2

EVT to DVT Version change list (P.I.R. List)
Item

D

C

B

A

1

Page 1 of 2

Reason for change

PG#

Modify List

Date

Phase

ME request

2009/12

EVT->DVT

P06

Net contact error on DIMMB

2009/12

EVT->DVT

Update DDR_CKE0_DIMMA, DDR_CKE1_DIMMA net

P06

Net contact error on DIMMA

2009/12

EVT->DVT

4

R41~R44 SMT-->@

P07

Fine tune HDT debug pull high R

2009/12

EVT->DVT

5

Del R46 and add R850~R854

P07

For ESD request

2009/12

EVT->DVT

6

Add RS15 RS16 for NBGFX_CLK,NBGFX_CLK#

P12

For internal clock gen

2009/12

EVT->DVT

7

Fine tune RS880M clock

P12

For internal clock gen

2009/12

EVT->DVT

8

Del external clock gen

P16

For internal clock gen

2009/12

EVT->DVT

9

Fine tune pin define JP4 Pin1 Pin2 Pin8-->GND

P17

Add more GND pin

2009/12

EVT->DVT

10

Add R855 R856 for HDMI_SDATA,HDMI_SCLK pull high R

P19

Solve HDMI can not detect

2009/12

EVT->DVT

11

U6 pin5 +5VL-->+5VS and HDMI Dual NMOSx2(Q6 Q7)->Single NMOS (Q6) P19

Cost down plan

2009/12

EVT->DVT

12

Add RS1~RS14 near SB820M and TP34 TP35

P20

For internal clock gen

2009/12

EVT->DVT

13

C640 @-->22P on CLK_PCI_EC

P20

EMI request

2009/12

EVT->DVT

14

C705 C705 @-->SMT on Y6

P20

2009/12

EVT->DVT

15

R152 R153 R154 pull +3VALW-->pull GND

P21

Follow AMD check list 1.03

2009/12

EVT->DVT

16

Add device clock request pin on SB820M

P21

For internal clock gen

2009/12

EVT->DVT

17

C632 @-->33P on AZ_BITCLK_HD

P21

EMI request

2009/12

EVT->DVT

18

Add WLAN_PWR_EN# and WWAN_PWR_EN# net on SB820M

P22

Power saving request

2009/12

EVT->DVT

19

U47 +3VL-->+3VALW and Y3 R164 C246 C247 SMT->@

P22

25MHz by default

2009/12

EVT->DVT

20

Reaserved R859 C707 on CLK net

P22

EMI request

2009/12

EVT->DVT

21

Fine tune SB820M strap pin

P24

For internal clock gen

2009/12

EVT->DVT

22

Add C706 0.1u on CLK_PCI_EC

P24

EMI request

2009/12

EVT->DVT

23

Del R193 and Add R858 PH on USB_OC#2

P25

Solve the USB hang up issue

2009/12

EVT->DVT

24

Reserved RM5 RM6 CM17 QM1 RM9 for +3V_WWAN power saving

P26

Power saving request

2009/12

EVT->DVT

25

Reserved RM7 RM8 CM18 QM2 RM10 for +3V_WLAN power saving

P26

Power saving request

2009/12

EVT->DVT

26

Reserved CM19 QM3 RM11 for +1.5V_WLAN power saving

P26

Power saving request

2009/12

EVT->DVT

27

RL21 pin2 +3V_LAN-->GND

P27

LAN vender request

2009/12

EVT->DVT

28

Del RA4 RA5

P28

Fine tune Audio HP out voltage

2009/12

EVT->DVT

29

Reserved RA27 CA26 on AZ_RST_HD#

P28

ESD request

2009/12

EVT->DVT

30

Add Q37 R860 R861 and PD# net

P28

Solve Audio PD# control issue

2009/12

EVT->DVT

31

Fine tune JP5 pin define

P29

Solve the USB hnag up issue

2009/12

EVT->DVT

32

Fine tune SPK_L1,SPK_L2,SPK_R1 and SPK_R2 for SPK

P29

Solve SPK pin issue

2009/12

EVT->DVT

33

Add R857 PH USB_OC#0 net

P29

Solve the USB hnag up issue

2009/12

EVT->DVT

34

Add C708 on +5VS

P29

ESD request

2009/12

EVT->DVT

35

Fine tune card reader pin define

P30

ME use new card reader connector

2009/12

EVT->DVT

36

Add EC_MUTE# on KBC926 (U12) 83pin

P31

Solve Audio PD# control issue

2009/12

EVT->DVT

37

Q8 Q9 R258 R259-->@, R790 R791-->SMT

P33

Cost down plan

2009/12

EVT->DVT

38

C386 @-->0.1u on ON/OFFBTN#

P33

EMI request

2009/12

EVT->DVT

39

C410 0.01u_0402_16V-->0.1u_0603_25V and R267 330k->1M

P34

SMT memo

2009/12

EVT->DVT

40

SYSON#-->SUSP on Q26 Pin2

P34

+0.75VS discharge control pin

2009/12

EVT->DVT

41

RA26 0ohm-->Bead (SM010017710) on INT_MIC_CLK

P28

EMI request

2009/12/18

EVT->DVT

42

C632 @-->33P on AZ_BITCLK_HD

P21

EMI request

2009/12/18

EVT->DVT

43

R788 @-->100ohm and C634 @-->100P on SPI_CLK

P32

RF request

2009/12/18

EVT->DVT

44

R789 @-->100ohm and C635 @-->100P on AZ_BITCLK_HD

P28

RF request

2009/12/18

EVT->DVT

45

Add CA63 on INT_MIC_CLK_R

P28

RF request

2009/12/18

EVT->DVT

46

RA1 0ohm-->Bead on Audio power

P28

RF request

2009/12/18

EVT->DVT

47

Add CM20 1000P on +3V_WWAN

P26

RF request

2009/12/18

EVT->DVT

49

Add C709 on 27M_SEL

P16

RF request (EXT only)

2009/12/19

EVT->DVT

49

Fine tune R133 R value 11.8K-->8.2K

P21

Fine tune USB signal

2009/12/22

EVT->DVT

50

RA22 RA25 4.7K-->2.2K and CA16 10u-->@

P28

Audio vender request

2009/12/22

EVT->DVT

51

Add BT_PWR# net contact to JWLAN1 pin5

P26

Follow common design

2009/12/23

EVT->DVT

52

Del R161 and SLP_CHG on SB

P22

Follow common design

2009/12/23

EVT->DVT

53

Add SLP_CHG on pin115 and add R862

P31

Follow common design

2009/12/23

EVT->DVT

54

Add UA2 CA67 CA68 CA69

P28

Audio power reserved

2009/12/23

EVT->DVT

55

Add F2 for card reader proetct

P30

H/W request

2009/12/24

EVT->DVT

56

Reserved RA28 CA70

P28

Reserved for fin tune aduio power control

2009/12/24

EVT->DVT

57

Add R863 PH on CIR_EN#

P21

Follow common design

2009/12/24

EVT->DVT

58

Add R864 on LID_SW#

P33

Reserved for ESD protect

2009/12/24

EVT->DVT

59

Modify TP26 TP27-->EVENT#_A and EVENT#_B

P09 P10

Solve layout test point issue

2009/12/25

EVT->DVT

60

C497 SMT-->@

P08

Fine tune CPU_CORE cap

2009/12/25

EVT->DVT

1

Update JSATA1, JHDMI1 and JREAD1 footprint

2

Update DDR_CS0_DIMMB#, DDR_CS1_DIMMB# net

3

Issued Date

2005/03/10

Deciphered Date

2006/03/10

Date:

4

3

2

B

A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C

Compal Electronics, Inc.

Compal Secret Data

Security Classification

D

EE change list-1
Rev

Tuesday, March 23, 2010

Sheet
1

44

of

45

5

4

3

2

DVT to PVT Version change list (P.I.R. List)
Item

D

C

B

1

Page 2 of 2

Reason for change

PG#

Modify List

Date

Phase

1

Add D17 and Q38 for BT power control

P26

Follow common design

2010/1/20

DVT->PVT

2

Change net name SLP_CHG-->SLP_CHG#

P25 P31

Follow net rule

2010/1/20

DVT->PVT

3

Need to fine tune R783 and R784

P18

VB function

2010/1/20

DVT->PVT

4

 SB use 2MB SPI ROM SA00002TO00

P22

Non share ROM

2010/1/20

DVT->PVT

5

 Update LAN P/N for LAN VB P/N

P27

Vender update P/N

2010/1/20

DVT->PVT

6

 EC SPI use 256KB SPI ROM SA00003GK00

P32

Non share ROM

2010/1/20

DVT->PVT

7

BT part SMT-->@

P29

IUR no BT device

2010/1/20

DVT->PVT

8

Update JREAD1 footprint (Same as EVT)t

P30

ME request

2010/1/20

DVT->PVT

9

Update JSATA1 footprint TAIWI_EU114-117CRL-TW_11P-T

P25

ME request

2010/1/20

DVT->PVT

10

Update JHDD1 pin4 +5VS-->GND

P25

HW request

2010/1/20

DVT->PVT

11

Del DC to DC +NB_CORE part

P34

HW request

2010/1/20

DVT->PVT

12

Change USB port10 to USB port5 on WWAN

P21

Follow common design

2010/1/20

DVT->PVT

13

Add R865 R866 for SLP_CHGX_M3/M4 on SB

P21

Follow common design

2010/1/20

DVT->PVT

14

Add R867 R868 for SLP_CHGM3/M4 on EC

P31

Follow common design

2010/1/21

DVT->PVT

15

UA2 pin5 +PVDD1--->+AVDD

P28

Reserved for Audio analog power

2010/1/21

DVT->PVT

16

 U48 SA000008G00-->SA00003DR00 (Same as intel)

P29

HW request

2010/1/21

DVT->PVT

17

Del R164 Y3 C246 C247 and add TP36 TP37

P22

HW request

2010/1/22

DVT->PVT

18

JLVDS1 pin24 +LCD_INV-->NG

P18

Follow common design

2010/1/22

DVT->PVT

19

U9 pin1 +5VALW-->+5V_ALW for USB charge

P25

Follow common design

2010/1/22

DVT->PVT

20

Add C900~C908,R900~R906 Q40 Q41 U49 U50 for power save

P34

Follow common design

2010/1/22

DVT->PVT

21

Update JTP1 footprint--> E-T_6916-Q06N-00R_6P

P33

ME request

2010/1/25

DVT->PVT

22

Update USB20_P10-->USB20_P5 ,USB20_N10-->USB20_N5

P21 P26

Follow common design

2010/1/25

DVT->PVT

23

Update JHDMI1footprint-->SUYIN_100042GR019M23BZR_19P-T

P19

ME request

2010/1/25

DVT->PVT

24

R900 pin 1 and R904 pin1 +B-->+VSB

P34

HW request

2010/1/27

DVT->PVT

25

Add J2 J3 for +3V_ALW and +5V_ALW

P34

HW request

2010/1/27

DVT->PVT

26

R808 pin 1,R809 pin2 +3VALW-->+3V_ALW and +5VALW-->+5V_ALW

P33

HW request

2010/1/27

DVT->PVT

27

Add R907 for USB_EN# PH

P29

HW request

2010/1/27

DVT->PVT

28

Del R808 R809 R811 R810 R258 Q8 R259 Q9

P33

HW request

2010/1/27

DVT->PVT

29

R238 pin1 +3VALW-->+3V_ALW

P31

HW request

2010/1/29

DVT->PVT

30

JTP1 pin1 +3VALW-->+3V_ALW

P33

Follow common design

2010/1/29

DVT->PVT

31

Del R246

P32

HW request

2010/1/29

DVT->PVT

32

Add LPC_FRAME#, LPC_AD, LPC_AD1,LPC_AD2,LPC_AD3 JWAN1

P26

HW request

2010/1/29

DVT->PVT

33

Update JPB1 footprint P-TWO_161011-04021_4P-T

P33

ME request

2010/1/29

DVT->PVT

34

Add JHDD2 ACES_87036-1001-CP_10P

P25

HW request

2010/1/29

DVT->PVT

35

Fine tune JP4 pin define for EMI request

P17

EMI request

2010/1/29

DVT->PVT

36

 Update UA1 P/N for Audio VB version

P28

Vender update P/N

2010/1/29

DVT->PVT

37

Update JP5 pin define and 20pin-->22pin

P29

HW request

2010/1/30

DVT->PVT

38

 R133 8.2K-->11.8K same as EVT

P21

HW request

2010/1/31

DVT->PVT

39

Add C909 C910

P17

EMI request

2010/1/31

DVT->PVT

40

Add D18 and R908 on RTC circuit

P20

Follow common design

2010/1/31

DVT->PVT

41

JHDD1 10pin-->12pin

P29

Add more power and GND pin on HDD conn

2010/1/31

DVT->PVT

42

Add R909 R910 for ADAPTOR_SEL

P31

Follow common design

2010/1/31

DVT->PVT

43

Add L41 L42 L43 C911 C912 C913 for EMI request

P12

EMI request

2010/2/2

DVT->PVT

44

C240 C244 22P to 18P

P20

Solve RTC fial issue

2010/2/2

DVT->PVT

D

C

B

45
46
47
49
49
50
51
52
53
54
55
56
57
A

A

58
59
60

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/03/10

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

EE change list-2
Rev

Tuesday, March 23, 2010

Sheet
1

45

of

45

www.s-manuals.com



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