Compal LA 6141P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Notebook Gateway ID43 - Service manuals and Schematics, Disassembly / Assembly. Free.
Open the PDF directly: View PDF .Page Count: 55
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Compal Confidential
2
2
NELA5 Schematics Document
AMD Danube
Champlain Processor with RS880M/SB820M/Park VGA
2010-04-15
LA6141P REV: 1.0
3
3
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Cover Page
Document Number
Rev
1.0
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
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of
54
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Compal Confidential
Model Name : NELA5
C
D
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Danube
VRAM 1GB/512MB
128M/64M x16 x 4
AMD S1G4 Processor
DDR3
ATI M97
Park-XT
uFCBGA-962
1
Page 16,17,18,19,20
Memory BUS(DDR3)
uPGA-638 Package
Champlain page 6,7,8,9
page 21
204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
page 10,11
1.5V DDRIII 800~1333MHz
1
Hyper Transport Link
16 x 16
PCI-Express x 16
Side Port
Gen2
Side Port Memory
128MB
64M16 x 1
ATI RS880M
LVDS
uFCBGA-528
page 22
Thermal Sensor
ADM1032
page 8
page 15
page 12,13,14,15
page 33
page 22
page 33
page 32
page 31
Bluetooth
Conn
Mini
card
(WL)X1
Card Reader
CRT
page 24
USB
conn
X3
A link Express2
Gen1
HDMI Conn.
page 23
ATI SB820M
LAN Conn.
AR8131L
WLAN
page 32
3.3V 48MHz
page 25,26,27,28,29
S-ATA
USB port 8
USB port 6
2
HD Audio
Gen2
page 33
HDA Codec
CX20672
page 37
GPP1
LPC BUS
LED
3
USB port 14
Realtek
RTS5138
USB
3.3V 24.576MHz/48Mhz
uFCBGA-605
LAN(GbE)
MINI Card 1
SATA HDD
Conn. page 30
CDROM
Conn.
page 30
port 0
port 1
Phone Jack x2
page 38
ENE KB926
Fan Control
page 35
USB port 1,2,3 USB port 5
2
GPP5
CMOS
Camera
page 36
page 40
RTC CKT.
Int.KBD
Touch Pad
page 25
page 35
LID SW / BTN/B
page 35
EC I/O Buffer
page 36
3
BIOS
page 36
page 35
Power On/Off CKT.
page 37
DC/DC Interface CKT.
4
4
page 41
Power Circuit
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
page 41,42,43,44,45,46,
47,48,49,50,51
2009/10/06
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
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D
Block Diagrams
Document Number
Rev
1.0
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
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of
54
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1
AMD
VGA
ATI
Park
D
D
CLK_PEG_VGA
100MHz
14.31818MHz
CLK_SBLINK_BCLK
MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N
A_SODIMM
100MHz
AMD
1066MHz
C
AMD
CLK_NBGFX
100MHz
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
B_SODIMM
S1G4
CPU SOCKET
CPU_CLKP/N
200MHz
1066MHz
EXTERNAL
CLK GEN.
SLG8SP626 / ICS9LPRS488
C
ATI
NB
RS880M
CLK_NBHT
100MHz
CLK_NB_14.318M
CLK_PCIE_WWAN
100MHz
CLK_PCIE_MINI1
48MHz
48MHz
100MHz
CLK_48M_SD
CLK_48M_USB
CLK_SBSRC_BCLK
14.318MHZ
100MHz
CLK_PCIE_LAN
B
B
100MHz
CardReader
WWAN
Mini PCI Socket
WLAN
Mini PCI Socket
GbE LAN
Atheros
AR8151
AMD
ATI
SB
SB820M
RTC
SATA
A
A
32.768K Hz
Compal Secret Data
Security Classification
2005/10/10
Issued Date
25MHz
2010/03/12
Deciphered Date
Title
CLOCK DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom NELA5 LA-6141P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Sheet
W ednesday, April 21, 2010
1
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54
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SIGNAL
STATE
Voltage Rails
Power Plane
1
2
HIGH
HIGH
HIGH
ON
ON
ON
ON
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
N/A
N/A
N/A
N/A
N/A
N/A
+CPU_CORE_0
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
+CPU_CORE_1
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
+CPU_CORE_NB
Voltage for On-die Northbridge of CPU(0.8-1.1V) ON
OFF
OFF
+0.9V
0.9V switched power rail for DDR terminator
ON
ON
OFF
+1.1VS
1.1V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+1.2V_HT
1.2V switched power rail
ON
OFF
OFF
Vcc
Ra/Rc/Re
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
Board ID
+1.5VS
1.5V power rail for PCIE Card
ON
OFF
OFF
+1.8V
1.8V power rail for CPU VDDIO and DDR
ON
ON
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V_LAN
3.3V power rail for LAN
ON
ON
ON
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
0
1
2
3
4
5
6
7
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Board ID
0
1
2
3
4
5
6
7
Interrupts
Smart Battery
0001 011X b
16H
Address
HEX
ADI ADM1032 (CPU)
1001 100X b
98H
GMT G781-1 (GPU)
1001 101X b
9AH
SB-Temp Sensor
SB820
SM Bus 0 address
Address
HEX
Clock Generator
(SILEGO SLG8SP626)
1101 001Xb
D2
DDR DIMM1
1001 000Xb
90
DDR DIMM2
1001 010Xb
94
Device
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BTO Option Table
BTO Item
PCB Revision
BOM Structure
0.1
0.2
0.3
1.0
Board ID
0
1
2
3
4
5
6
7
98H
SB820
SM Bus 1 address
Device
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
Project ID Table
EC SM Bus2 address
Device
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
BOARD ID Table
3
HEX
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
2
External PCI Devices
Address
1
Board ID / SKU ID Table for AD channel
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device
Clock
HIGH
Adapter power supply (19V)
EC SM Bus1 address
+VS
S1(Power On Suspend)
AC or battery power rail for power circuit.
REQ#/GNT#
+V
S5
B+
IDSEL#
+VALW
S3
VIN
Device
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
S1
Full ON
Description
E
3
PCB Revision
Address
BOM Config
PowerXpress (MUX): VGA@/PARK@/MUX@/BT@/SP@/VB@
UMA : VB@/UMALVDS@/UMAHDMI@/UMACRT@/UMA@/SP@/BT@
PowerXpress(Muxless):VB@/UMALVDS@/UMAHDMI@/UMACRT@/SP@/BT@/VGA@/MUXLESS@/PARK@
Mini card
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Notes List
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
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of
54
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AMD CPU S1G4
+CPU_CORE
BATTERY
12.6V
BATT+
PU5
CHARGER
ISL6261AHAZ-T
PU15
ISL6265IRZ-T
PU16
APL5508-25DC
AC ADAPTOR
19V 90W
+CPU_CORE
0.7~1.3V
VDD CORE 36A
+CPU_CORE_NB
0.8~1.2V
VDDNB 4A
2.5V
VDDA 250mA
1.5V
VDDIO 3A
1.05V
VDDR 1.5A
1.1V
VLDT 1.5A
+CPU_CORE_NB
+2.5VS
+1.05VS
+1.05VS
PU12
APL5915
VIN
+1.1VS
D
D
RAM DDRIII SODIMMX2
+1.5V
PU7
RT8209BGQW
B+
+1.5V
1.5V
VDD_MEM 4A
0.75V
VTT_MEM 0.5A
+0.75VS
PU10
APL5913
NorthBridge AMD RS880M
PU8
RT8209BGQW
PU6
RT8209BGQW
1.0~1.1V
VDDC 1.0V-1.1V 7.6A
1.1V_S0
VDDHTRX+HT 0.68A
VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.23A
1.8V_S0
VDDA18 0.64A
VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A
3.3V_S0
VDDG33 0.06A
AVDD 0.125A
VDDLT33 0A
No Use
VDD18_MEM 1.8V 0.005A
VDD_MEM 1.8V 0.23A
+NB_CORE
+1.1VS
+1.1VALW
+1.1VALW
U36
SI4800BDY
+1.1VS
+1.5V
C
+1.5VS
PU19
TSP51117RGYR
C
U35
SI4800BDY
VGA ATI Madison / Park
PU17
APW7138NITRL
+GPU_CORE
+VDDCI
0.85~1.1V
+1VSG
PU10
APL5913
+1.8VS
PU14
APL5913
PU11
MP2121DQ
+1.8VSP2
1.0V
PCIE_VDDC 2 A
DP[F:A]_VDD10 230 mA
DPLL_VDDC 125 mA
SPV10 100 mA
1.5V
VDDR1 TBD A
1.8V
PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
TSVDD 5 mA
VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
DP[F:A]_VDD18 330 mA
AVDD 70 mA
VDD1DI 45 mA
A2VDDQ 1.5 mA
VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
3.3V
VDDR3 60 mA
A2VDD 130 mA
+1.8VSP1
PU4
SN0806081 RHBR
+5VALW
B
U37
SI1800BDY
+3VS
LCD panel
15.6"
Delay
+3VS_DELAY
U34
SI4800BDY +5VS
B+ 300mA
VRAM 1GB
64Mx16 (K4B1G1646E) * 8
+1.5VS
+3VALW
+INVPWR_B+
VDDC 29 A
VDDCI 4 A
+3.3 350mA
1.5V
2.4 A
B
SouthBridge AMD SB820M
1.1V_S0
+1.1VALW
FAN Control
APL5607
1.1V_S5
+5VS 500mA
VDDIO_33_PCIGP 0.020A
VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS
3.3V_S5
VDDIO_33_S
VDDPL_33_USB_S
VDDAN_33_USB_S 0.2A
VDDAN_33_S
VDDXL_33_S
VDDIO_AZ_S
No Use
VDDCR_11_GBE_S
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDIO_GBE_S
VDDIO_18_FC
+USB_VCCB
Audio AMP
TPA6017A2
A
USB X3
+5V
Dual+1
2.5A
+5V 25mA
SATA
Audio Codec
ALC272
+5V 3A
+5V 45mA
+3.3V
+3.3VS 25mA
Realtek
RTS5159
EC
ENE KB926
LAN
Atheros AR8114
ICS9LPRS488B
+3.3VS 300mA
+3.3VALW 30mA
+3.3VS 3mA
+3.3VALW 201mA
+3.3V 400mA
Mini Card
RTC
Bettary
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+1.1V
2.5~3.6V
BAT
2009/3/8
Deciphered Date
2010/03/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VDDBT_RTC_G
Title
POWER DELIVERY CHART
Size
Document Number
Custom NELA5 LA-6141P
Date:
5
4
3
A
Compal Secret Data
Security Classification
Issued Date
VDDCR_11_S 113mA
VDDAN_11_USB_S 200mA
VDDCR_11_USB_S 197mA
VDDPL_11_SYS_S
3.3V_S0
+3VALW
U25/U40
TPS2061DRG4 +USB_VCCA
VDDCR_11 1.1V 0.5A
VDDAN_11_PCIE 1A
VDDAN_11_SATA 0.8A
VDDAN_11_CLK 0.4A
2
Rev
0.1
Wednesday, April 21, 2010
1
Sheet
5
of
54
A
B
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D
E
1
1
VLDT CAP.
+1.1VS
250 mil
2
12 H_CADIP[0..15]
12 H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADON[0..15]
12
1
12
2
C1
10U_0805_10V4Z
1
1
C2
10U_0805_10V4Z
C3
0.22U_0603_16V4Z
2
1
C4
0.22U_0603_16V4Z
2
1
C5
180P_0402_50V8J
2
1
C6
180P_0402_50V8J
2
Near CPU Socket
+1.1VS
+1.1VS
JCPU1A
TBD
2
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
3
C7
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
12
12
12
12
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
12
12
12
12
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
2
2
1
10U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
3
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
12
12
12
12
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
12
12
12
12
FOX_PZ6382A-284S-41F_Champlian
CONN@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G3 HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
6
of
54
A
B
C
D
E
Processor DDR3 Memory Interface
JCPU1C
11 DDRB_SDQ[63..0]
1
MEM:DATA
2
+1.5V
1
R1
1K_0402_1%
C8
1000P_0402_25V8J
1
2
C9
0.01U_0402_25V7K
2
MEM_VREF
1
R2
1K_0402_1%
1
2
12/07 reseve 10uF cap.(AMD)
+1.5V
+CPU_VDDR
+CPU_VDDR
JCPU1B
2
2
Place them
close to CPU
within 1"
R1059
0_0402_5%
1
R4
1
1
R5
C1250
2
10U_0805_10V4Z
@ 1
10 MEM_MA_RST#
10 DDRA_ODT0
10 DDRA_ODT1
10 DDRA_SCS0#
10 DDRA_SCS1#
10 DDRA_CKE0
10 DDRA_CKE1
10 DDRA_CLK0
10 DDRA_CLK0#
3
10 DDRA_CLK1
10 DDRA_CLK1#
10 DDRA_SMA[15..0]
10 DDRA_SBS0#
10 DDRA_SBS1#
10 DDRA_SBS2#
10 DDRA_SRAS#
10 DDRA_SCAS#
10 DDRA_SWE#
1.5A
D10
C10
B10
AD10
39.2_0402_1%
MEMZP AF10
2
MEMZN AE10
2
39.2_0402_1%
MEM_MA_RST#
H16
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
R20
R23
J21
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
R19
T22
T24
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
MA_RESET_L
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MEMVREF
MB_RESET_L
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
W10
AC10
AB10
AA10
A10
Y10
VDDR: DDR3 under 1033MHz
set to 0.9V to save power
VTT_SENSE
W17
MEM_VREF
B18
MEM_MB_RST#
W26
W23
Y26
DDRB_ODT0
DDRB_ODT1
V26
W25
U22
DDRB_SCS0#
DDRB_SCS1#
J25
H26
DDRB_CKE0
DDRB_CKE1
P22
R22
A17
A18
AF18
AF17
R26
R25
DDRB_CLK0
DDRB_CLK0#
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
R24
U26
J26
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
U25
U24
U23
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_CLK1
DDRB_CLK1#
PAD
T1
MEM_MB_RST# 11
DDRB_ODT0 11
DDRB_ODT1 11
DDRB_SCS0# 11
DDRB_SCS1# 11
DDRB_CKE0 11
DDRB_CKE1 11
DDRB_CLK0 11
DDRB_CLK0# 11
DDRB_CLK1 11
DDRB_CLK1# 11
DDRB_SMA[15..0] 11
11 DDRB_SDM[7..0]
DDRB_SBS0# 11
DDRB_SBS1# 11
DDRB_SBS2# 11
DDRB_SRAS# 11
DDRB_SCAS# 11
DDRB_SWE# 11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
DDRA_SDQ[63..0]
10
1
2
DDRA_SDM[7..0]
10
3
DDRA_SDQS0 10
DDRA_SDQS0# 10
DDRA_SDQS1 10
DDRA_SDQS1# 10
DDRA_SDQS2 10
DDRA_SDQS2# 10
DDRA_SDQS3 10
DDRA_SDQS3# 10
DDRA_SDQS4 10
DDRA_SDQS4# 10
DDRA_SDQS5 10
DDRA_SDQS5# 10
DDRA_SDQS6 10
DDRA_SDQS6# 10
DDRA_SDQS7 10
DDRA_SDQS7# 10
FOX_PZ6382A-284S-41F_Champlian
CONN@
FOX_PZ6382A-284S-41F_Champlian
CONN@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G3 DDRII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
7
of
54
B
C
FBMA-L11-201209-221LMA30T_0805 1
1
+
C11
4.7U_0805_10V4Z
1
C12
2
2
C14
0.22U_0603_16V4Z
R6
10K_0402_5%
R7
1K_0402_5%
1
1
JCPU1D
B
DVT 0131 update C11 to SGA00002N80
1
+1.5V
LDT_RES# / MEMHOT#
no support in S1g4
1
C13
2
150U_B2_6.3VM_R35M
2
VDDA=0.25A
3300P_0402_50V7K
2
1
1
2
+2.5VS
E
Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB
+2.5VDDA
L1
D
2 2
A
1
C16
LDT_RST#
H_PWRGD
LDT_STOP#
R10
169_0402_1%
12/03 add CPU_ALERT
2
1
25 CLK_CPU_BCLK#
2
3900P_0402_50V7K
C15
+1.5VS
+1.5V
+1.5V
+1.5V
R12
R14
R36
2
+1.1VS
1
R17
300_0402_5%
LDT_RST#
25 LDT_RST#
1
1
1
@
R15 1
R16 1
1
13,25 LDT_STOP#
+1.5VS
2
1
1
R21
300_0402_5%
2
1
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
SIC
SID
ALERT_L
R6
P6
HT_REF0
HT_REF1
CPU_SVC 50
CPU_SVD 50
+1.5V
PAD
THERMDC
THERMDA
W7
W8
THERMDC_CPU
THERMDA_CPU
T3
VDD0_FB_H
VDD0_FB_L
VDDIO_FB_H
VDDIO_FB_L
W9
Y9
CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
LDT_STOP#
G10
AA9
AC9
AD9
AF9
CPU_TEST23
AD7
CPU_TEST18
CPU_TEST19
H10
G9
CPU_TEST25H
CPU_TEST25L
C18
0.01U_0402_25V4Z
@
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
1
R24
2
0_0402_5%
E9
E8
AB8
AF7
AE7
AE8
AC8
AF8
C2
AA6
A3
A5
B3
B5
C1
+3VS
DBRDY
TMS
TCK
TRST_L
TDI
2
0_0402_5%
H_THERMTRIP# 26
1
R9
2
0_0402_5%
1
R11
MAINPWON 42,43,47
@
2
300_0402_5%
CPU_THERMTRIP#_R
H_PROCHOT#
AF6
AC7
AA8
THERMTRIP_L
PROCHOT_L
MEMHOT_L
1
R8
MMBT3904_NL_SOT23-3
CPU_SVC
CPU_SVD
A6
A4
50 CPU_VDD1_FB_H
50 CPU_VDD1_FB_L
C19
0.01U_0402_25V4Z
@
2
SVC
SVD
F6
E6
H_PWRGD
25 H_PWRGD
AF4
AF5
AE6
VSS
RSVD11
CLKIN_H
CLKIN_L
50 CPU_VDD0_FB_H
50 CPU_VDD0_FB_L
R18
300_0402_5%
2
T2 PAD
CPU_SIC
CPU_SID
CPU_ALERT
VDDA1
VDDA2
CPU_VDD0_FB_H
CPU_VDD0_FB_L
2
C17
0.01U_0402_25V4Z
@
2
B7
A7
F10
C6
2
2 1K_0402_5%
2 1K_0402_5%
1K_0402_5%
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
+1.5VS
1
A9
A8
3
C
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
1
25 CLK_CPU_BCLK
CPU_THERMTRIP#_R
M11
W18
Q1
1
E
F8
F9
H_PROCHOT#
1
R13
2
0_0402_5%
H_PROCHOT_R# 25
PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition
CPU_VDDNB_FB_H 50
CPU_VDDNB_FB_L 50
+1.5V
TEST23
TEST28_H
TEST28_L
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
TEST9
TEST6
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
2
J7
H8
CPU_SVC
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
D7
E7
F7
C7
PAD
PAD
PAD
PAD
T5
T6
T7
T8
1
R19
1
R20
CPU_SVD
2
1K_0402_5%
2
1K_0402_5%
+1.5V
C3
K8
CPU_TEST25H
1
R22
1
R23
CPU_TEST25L
1
R26
1
R27
C4
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
C9
C8
2
R25
1
80.6_0402_1%
H18
H19
AA7
D5
C5
@
@
2
510_0402_5%
2
510_0402_5%
+1.5V
2
510_0402_5%
2
510_0402_5%
0.1U_0402_16V4Z
+1.5V
3
1
FOX_PZ6382A-284S-41F_Champlian
CONN@
PVT 20100312 add Res.
C20
2
CPU_TEST27
1
THERMDA_CPU
2
THERMDC_CPU
3
2
C21
1.5P_0402_50V9C
4
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
8
1
R1135
1
R1136
7
2
0_0402_5%
2
0_0402_5%
CPU_TEST12
5
CPU_TEST18
+1.5V
CPU_TEST21
G
2
2.09V for Gate
@
1
CPU_SID 3
EC_SMB_DA
D
S
Q85
FDV301N_NL_SOT23-3
@
1
R1121
@
1
R1122
2
0_0402_5%
2
0_0402_5%
SB_SID
SB_SID 26
EC_SMB_DA2
T0 SB
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
TO EC
CPU_TEST23
1
3
5
7
9
11
13
15
17
19
21
23
R43
@
1
2
G
D
S
Q86
EC_SMB_CK
FDV301N_NL_SOT23-3
@
1
R1123
@
1
R1124
SB_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%
SB_SIC 26
U2
HDT_RST#
4
B
A
LDT_RST#
2
Y
1
SB_PWRGD 13,26,34
TO EC
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
2010/03/12
Deciphered Date
Title
AMD CPU S1G3 CTRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PVT 20100304 Add CPU Int. Thermal sensor circuit
Pre MP unstuff CPU Int. Thermal sensor circuit
Date:
B
4
NC7SZ08P5X_NL_SC70-5
HDT@
T0 SB
Issued Date
A
2
0_0402_5%
+3VS
3
2
4
6
8
10
12
14
16
18
20
22
24
26
CONN@ SAMTEC_ASP-68200-07
@
1
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
JP2
4
CPU_SIC 3
1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R265
5
HDT@
2
20K_0402_5%
CPU_TEST24
P
R1120
1
@
34.8K_0402_1%
1
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
CPU_TEST22
G
@
11/10 Remove R36,R37,R38,R39
Follow CRB HDT design
1
2
300_0402_5% R40
@ 0.1U_0402_16V4Z
R1119
CPU_TEST20
1001 100X b
CPU internal thermal sensor
C1267
1
2
3
For SCAN connect use
EC_SMB_DA2 17,34
6
ADM1032ARMZ_MSOP8
Address
2
2
1K_0402_5%
EC_SMB_CK2 17,34
CPU_TEST19
PVT 20100304 change to 100pF
+3VS
1
R28
U1
1
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
8
of
54
A
B
C
D
JCPU1F
VDD(+CPU_CORE) decoupling.
JCPU1E
+CPU_CORE
+CPU_CORE
1
1
+
1
+
C23
330U_X_2VM_R6M
1
2
1
+
C24
330U_X_2VM_R6M
2
C25
330U_X_2VM_R6M
2
1
+
C26
330U_X_2VM_R6M
2
+
2
C27
330U_X_2VM_R6M
@
Near CPU Socket
+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
1
C28
22U_0805_6.3V6M
2
1
C29
22U_0805_6.3V6M
2
1
C30
22U_0805_6.3V6M
2
1
4A
C35
22U_0805_6.3V6M
1
2
1
C31
22U_0805_6.3V6M
2
C32
22U_0805_6.3V6M
2
+CPU_CORE
1
1
C33
22U_0805_6.3V6M
2
1
C34
22U_0805_6.3V6M
2
+1.5V
+CPU_CORE
C36
0.22U_0603_16V4Z
2
1
C37
0.01U_0402_25V4Z
2
1
E
1
C38
180P_0402_50V8J
2
C39
0.22U_0603_16V4Z
2
1
C40
0.01U_0402_25V4Z
2
1
C41
180P_0402_50V8J
2
Under CPU Socket
2
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
36A
+1.5V
TBD
FOX_PZ6382A-284S-41F_Champlian
Athlon 64 S1
CONN@
VDDIO decoupling.
Processor Socket
+CPU_CORE_NB
decoupling.
+1.5V
+CPU_CORE_NB
1
C44
22U_0805_6.3V6M
2
1
C45
22U_0805_6.3V6M
1
1
C46
0.22U_0603_16V4Z
2
2
1
C47
0.22U_0603_16V4Z
2
1
C48
C50
1
180P_0402_50V8J 180P_0402_50V8J
2
2
C42
22U_0805_6.3V6M
2
1
C43
22U_0805_6.3V6M
2
1
C49
22U_0805_6.3V6M
2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
1
2
FOX_PZ6382A-284S-41F_Champlian
Athlon 64 S1 CONN@
Under CPU Socket
Processor Socket
Between CPU Socket and DIMM
+1.5V
+CPU_VDDR
3
1
C51
0.22U_0603_16V4Z
2
1
C52
0.22U_0603_16V4Z
2
1
C53
0.22U_0603_16V4Z
2
1
1
C54
0.22U_0603_16V4Z
2
C354
0.22U_0603_16V4Z
2
1
VDDR decoupling.
C355
0.22U_0603_16V4Z
+
2
DVT 0131 change C56 to SGA00002N80
180PF Qt'y follow the distance between
+1.5V CPU socket and DIMM0. <2.5inch>
+1.5V
1
C64
0.01U_0402_25V4Z
2
1
2
C65
0.01U_0402_25V4Z
2
1
2
C66
0.1U_0402_16V7K
1
1
C67
0.1U_0402_16V7K
C68
180P_0402_50V8J
2
3
Near Power Supply
1
2
1
C56
150U_B2_6.3VM_R35M
C55
22U_0805_6.3V6M
2
+CPU_VDDR
1
C69
1
180P_0402_50V8J
2
C57
4.7U_0805_10V4Z
2
1
C58
4.7U_0805_10V4Z
2
+1.5V
1
C59
0.22U_0603_16V4Z
2
1
C60
0.22U_0603_16V4Z
2
1
C61
1000P_0402_25V8J
2
1
C62
1000P_0402_25V8J
2
1
C63
180P_0402_50V8J
2
1
C70
180P_0402_50V8J
2
Near CPU Socket Right side.
+CPU_VDDR
1
1
2
1
C71
4.7U_0805_10V4Z
2
1
C72
4.7U_0805_10V4Z
2
1
C73
4.7U_0805_10V4Z
2
C74
4.7U_0805_10V4Z
+ C75
330U_X_2VM_R6M
1
2
2
C76
4.7U_0805_10V4Z
1
C77
4.7U_0805_10V4Z
2
1
C78
0.22U_0603_16V4Z
2
1
C79
0.22U_0603_16V4Z
2
1
C80
1000P_0402_25V8J
2
1
C81
1000P_0402_25V8J
2
1
C82
180P_0402_50V8J
2
1
C83
180P_0402_50V8J
2
4
4
Near CPU Socket Left side.
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G3 PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
9
of
54
B
11/28 update DIMM conn (same as NEW70)
11/30 update DIMM conn(same as NEW75)
+1.5V
JDIMM1
DDRA_SDQ26
DDRA_SDQ27
DDRA_SMA[0..15] 7
MEM_MA_RST# 7
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
+VREF_CA
+VREF_DQ
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_SMA3
DDRA_SMA1
7 DDRA_CLK0
7 DDRA_CLK0#
7 DDRA_SBS0#
7 DDRA_SWE#
7 DDRA_SCAS#
7 DDRA_SCS1#
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
7 DDRA_SDQS4#
7 DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
3
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
7 DDRA_SDQS6#
7 DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R50
10K_0402_5%
1
2
1
+3VS
4
R51
+3VS
2
10K_0402_5%
G2
206
DDRA_CKE1
DDRA_CKE1 7
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
1
C84
2 @
2
C85
1
1
2
G1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
C10
R49
1K_0402_1%
2
1
205
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1000P_0402_25V8J
DDRA_SMA8
DDRA_SMA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
4.7U_0603_6.3V6K
DDRA_SMA12
DDRA_SMA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
1
C235
2 @
2
C351
1
1
C680
2
R315
1K_0402_1%
2
DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
11/27 update
(0805 to 0603)
DDRA_CLK1 7
DDRA_CLK1# 7
11/27 update
(0805 to 0603)
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
DDRA_ODT0 7
DDRA_ODT1 7
+VREF_CA
DDRA_SDQ36
DDRA_SDQ37
1
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
2
C89
1000P_0402_25V8J
DDRA_SBS2#
+VREF_CA
0.01U_0402_25V7K
7 DDRA_SBS2#
DDRA_CKE0
0.01U_0402_25V7K
7 DDRA_CKE0
R310
1K_0402_1%
R48
1K_0402_1%
+VREF_DQ
2
+1.5V
+1.5V
DDRA_SDQS3# 7
DDRA_SDQS3 7
2
DDRA_SDM3
DDRA_SDM1
MEM_MA_RST#
1
DDRA_SDQ24
DDRA_SDQ25
DDRA_SMA[0..15]
2
DDRA_SDQ18
DDRA_SDQ19
1
DDRA_SDQ12
DDRA_SDQ13
1
7 DDRA_SDQS2#
7 DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS2
7
DDRA_SDM[0..7] 7
+1.5V
0.1U_0402_16V4Z
2
2
C87
C643
1
0.1U_0402_16V4Z
DDRA_SDQS5# 7
DDRA_SDQS5 7
0.1U_0402_16V4Z
2
2
1
C88
1
0.1U_0402_16V4Z
C644
1
0.1U_0402_16V4Z
2
2
C640
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C645
1
C641
C646
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
2
C642
1
0.1U_0402_16V4Z
3
C647
1
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
+0.75VS
DDRA_SDM6
2
DDRA_SDQ54
DDRA_SDQ55
1
0.1U_0402_16V4Z
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
1
C664
1
C961
2
2.2U_0402_6.3V6M
Place near DIMM1
DDRA_SDQS7# 7
DDRA_SDQS7 7
DDRA_SDQ62
DDRA_SDQ63
PAD
0.1U_0402_16V4Z
2
C665
11/27 update
(0603 to 0402)
4.7u to 2.2u
+1.5V
T9
SB_SMDAT0 11,26,32
SB_SMCLK0 11,26,32
12/16 add Cap.
for +1.5V
+0.75VS
FOX_AS0A626-U8SN-7F
CONN@
2
1
2
1
2
1
2
1
C1259
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ[0..63]
C1258
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
0.1U_0402_16V4Z
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQS0# 7
DDRA_SDQS0 7
DDRA_SDQ6
DDRA_SDQ7
1000P_0402_25V8J
7 DDRA_SDQS1#
7 DDRA_SDQS1
DDRA_SDQS0#
DDRA_SDQS0
C1257
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ4
DDRA_SDQ5
0.1U_0402_16V4Z
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C1256
DDRA_SDQ2
DDRA_SDQ3
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
0.1U_0402_16V4Z
DDRA_SDM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDRA_SDQ0
DDRA_SDQ1
E
4.7U_0603_6.3V6K
+1.5V
D
2
+VREF_DQ
C
1
A
4
1
2
C90
1U_0402_6.3V6K
11/27 remove 2.2U/0.1U
add 1u_0402
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
DIMM_A STD H:8mm
2010/03/12
Deciphered Date
Title
DDRII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
10
of
54
B
DDRB_SDQ2
DDRB_SDQ3
1
DDRB_SDQ8
DDRB_SDQ9
7 DDRB_SDQS1#
7 DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
7 DDRB_SDQS2#
7 DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
7 DDRB_CKE0
2
7 DDRB_SBS2#
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
7 DDRB_SWE#
7 DDRB_SCAS#
7 DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
7 DDRB_SDQS4#
7 DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
3
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
7 DDRB_SDQS6#
7 DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R52
10K_0402_5%
1
2
1
+3VS
+3VS
4
R53
2
2
205
10K_0402_5%
1
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
G1
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQS0# 7
DDRB_SDQS0 7
DDRB_SDQ[0..63]
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
7
DDRB_SDM[0..7] 7
1
DDRB_SDQ12
DDRB_SDQ13
DDRB_SMA[0..15]
DDRB_SDM1
MEM_MB_RST#
DDRB_SMA[0..15] 7
MEM_MB_RST# 7
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_CKE1 7
DDRB_SMA15
DDRB_SMA14
2
DDRB_SMA11
DDRB_SMA7
+VREF_DQ
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
1
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
1
C92
2 @
+VREF_CA
1
C93
2
1
C682
2
1
C352
2 @
1
C353
2
1
C683
2
DDRB_ODT1 7
11/27 update
(0805 to 0603)
+VREF_CA
DDRB_SDQ36
DDRB_SDQ37
+VREF_CA
+VREF_DQ
0.1U_0402_16V4Z
7 DDRB_SBS0#
DDRB_SMA10
DDRB_SBS0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
0.1U_0402_16V4Z
7 DDRB_CLK0
7 DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_25V8J
DDRB_SDM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4.7U_0603_6.3V6K
DDRB_SDQ0
DDRB_SDQ1
E
11/28 update DIMM conn(same as NEW70)
11/30 Update DIMM conn(same as NEW75)
+1.5V
JDIMM2
1000P_0402_25V8J
+1.5V
D
4.7U_0603_6.3V6K
+VREF_DQ
C
2
C94
1000P_0402_25V8J
A
11/27 update
(0805 to 0603)
3
DDRB_SDQS5# 7
DDRB_SDQS5 7
+1.5V
DDRB_SDQ46
DDRB_SDQ47
0.1U_0402_16V4Z
2
2
DDRB_SDQ52
DDRB_SDQ53
C677
C670
1
0.1U_0402_16V4Z
DDRB_SDM6
0.1U_0402_16V4Z
2
2
1
C666
2
C671
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
C667
1
0.1U_0402_16V4Z
C672
1
2
0.1U_0402_16V4Z
2
C668
C673
1
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
2
C669
C674
1
0.1U_0402_16V4Z
1
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
+0.75VS
+1.5V
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQS7# 7
DDRB_SDQS7 7
2
DDRB_SDQ62
DDRB_SDQ63
PAD
0.1U_0402_16V4Z
2
C676
1
0.1U_0402_16V4Z
T10
1
C675
1
1
+
C925
@
2
2.2U_0402_6.3V6M
SB_SMDAT0 10,26,32
SB_SMCLK0 10,26,32
C86
330U_X_2VM_R6M
2
Place near DIMM2
+0.75VS
4
11/27 update
(0603 to 0402)
4.7u to 2.2u
FOX_AS0A626-U4SN-7F
CONN@
C91
1U_0402_6.3V6K
DIMM_B STD H:4mm
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
11/27 add 1u_0402
2010/03/12
Deciphered Date
Title
DDRII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
11
of
54
A
B
C
PCIE_GTX_C_MRX_P[0..15]
16 PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15]
11/30
exchange net name
from PCIE_MTX_GRX_N(4~13,15)
to
PCIE_MTX_GRX_P(4~13,15)
PCIE_GTX_C_MRX_N[0..15]
16 PCIE_GTX_C_MRX_N[0..15]
D
PCIE_MTX_GRX_P[0..3]
PCIE_MTX_C_GRX_P[0..15] 16
PCIE_MTX_C_GRX_N[0..15]
E
PCIE_MTX_GRX_P[0..3] 23
PCIE_MTX_GRX_N[0..3]
PCIE_MTX_C_GRX_N[0..15] 16
PCIE_MTX_GRX_N[0..3] 23
11/06 for UMA HDMI signal
U3B
2
1
2 GPP0P AE3
R54 1 0_0402_5%
2 GPP0N AD4
R55
0_0402_5%
AE2
AD3
AD1
AD2
PCIE_PTX_C_IRX_P0 1
PCIE_PTX_C_IRX_P3V5
@
2
PCIE_PTX_C_IRX_N0 1R56 @ 0_0402_5%
PCIE_PTX_C_IRX_N3
2
W6
R57
0_0402_5%
U5
U6
R56,R57 close to R54,R55
U8
U7
33 PCIE_PTX_C_IRX_P0
33 PCIE_PTX_C_IRX_N0
32 PCIE_PTX_C_IRX_P1
32 PCIE_PTX_C_IRX_N1
25
25
25
25
25
25
25
25
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
C96
C98
2MUX@
1
1
2MUX@
C100 1
2MUX@
C102 1
C104 1
2MUX@
2MUX@
C106 1
2MUX@
C108 1
2MUX@
C110 1
2MUX@
C112 1
2VGA@
C114 1
2VGA@
C116 1
2VGA@
C118 1
2VGA@
C120 1
2VGA@
C122 1
2VGA@
C124 1
C126 1
2VGA@
2VGA@
C127 1
C128
1
C129 1
C130
1
PCIE_ITX_PRX_P3 C131 1@
PCIE_ITX_PRX_N3 C132 @1
@
2
2
2
2
C95 1
0.1U_0402_16V7K
C97 1
0.1U_0402_16V7K
C99 1
0.1U_0402_16V7K
C101 1
0.1U_0402_16V7K
0.1U_0402_16V7K
C103 1
0.1U_0402_16V7K
C105 1
0.1U_0402_16V7K
C107 1
0.1U_0402_16V7K
C109 1
0.1U_0402_16V7K
C111 1
0.1U_0402_16V7K
C113 1
0.1U_0402_16V7K
C115 1
0.1U_0402_16V7K
C117 1
0.1U_0402_16V7K
C119 1
0.1U_0402_16V7K
C121 1
C123 1
0.1U_0402_16V7K
0.1U_0402_16V7K
C125 1
2MUX@
2MUX@
2MUX@
2MUX@
2MUX@
2MUX@
2MUX@
2MUX@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N5
0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N6
0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N7
0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N8
0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N9
0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N10
0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N11
0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N12
0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N13
0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
33
33
32
32
1
GLAN
2
WLAN
Reserve for LAN debug
C131,C132 close to C127,C128
6 H_CADOP[0..15]
6 H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R59
R58
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
25
25
25
25
25
25
25
25
H_CADIP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
6
H_CADIN[0..15]
6
U3A
+1.1VS
RS780M_FCBGA528
RS880 A11(SA000032710)
3
6
6
6
6
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
6
6
6
6
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1
R60
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2
HT_RXCALP
HT_RXCALN
M22
M23
R21
R20
C23
A24
301_0402_1%~D
0718 Place within 1"
layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
2008/10/06
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
B24
B25
HT_TXCALP
HT_TXCALN
C
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
6
6
6
6
1
R61
2
4
Compal Electronics, Inc.
2010/03/12
Deciphered Date
Title
RS880-HT/PCIE
Date:
B
6
6
6
6
301_0402_1%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
0718 Place within 1"
layout 1:2
RS880 A11(SA000032710)
Compal Secret Data
Security Classification
3
H24
H25
L21
L20
RS780M_FCBGA528
4
Issued Date
H_CADOP[0..15]
H_CADON[0..15]
HYPER TRANSPORT CPU I/F
1
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
PCIE I/F GFX
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
12
of
54
C
D
2
1
C147
1U_0402_6.3V6K
2
+1.8VS
1
+VDDA18HTPLL
L7
1
2
2
C149
1U_0402_6.3V6K
2
1
1
2
2
C151
1U_0402_6.3V6K
2
1
2
C155
1U_0402_6.3V6K
20mA
12/14 update net name
R66
1
1
R67
+1.8VS
2
1
300_0402_5%
R68
0_0402_5%
REFCLK_P
REFCLK_N
CLK_NBGFX
CLK_NBGFX#
R9671
R9681
11/15 close to NB, for internal CLK Gen
R77
2 4.7K_0402_5%
1
2 4.7K_0402_5% GMCH_LCD_DATA
R78
1
R79
1 MUX@ 2 4.7K_0402_5%
R80
1 MUX@ 2 4.7K_0402_5% GMCH_CRT_DATA
R173 2
@
1 4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
2
11/10 for HDMI
AUX0N
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
H17
D7
E7
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_HDMI_CLK
GMCH_HDMI_DATA
23 GMCH_HDMI_CLK
23 GMCH_HDMI_DATA
46 POWER_SEL
T2
T1
V4
V3
22 GMCH_LCD_CLK
22,36 GMCH_LCD_DATA
36 AUX0N
GMCH_CRT_CLK
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
U1
U2
25 CLK_SBLINK_BCLK
25 CLK_SBLINK_BCLK#
GMCH_LCD_CLK
G18
G17
E18
F18
E19
F19
E11
F11
12/14 remove ext clk
3
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
C25
C24
25 CLK_NBHT
25 CLK_NBHT#
+3VS
E17
F17
F15
NB_RESET#
D8
NB_PWRGD_R A10
NB_LDTSTOP#
C10
NB_ALLOW_LDTSTOP C12
@
11/15 for internal CLK gen
2 0_0402_5%
2 0_0402_5%
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
0_0402_5%
2
2
POWER_SEL
1
R82
1
R85
B9
A9
B8
A8
B7
A7
B10
2
2K_0402_5%
2
150_0402_1%
12/08 remove EMI(Int. CLK Gen)
G11
C8
2
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
A22
B22
A21
B21
B20
A20
A19
B19
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
PART 3 OF 6
DAC_RSET(PWM_GPIO1)
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
5
C152
1U_0402_6.3V6K
GMCH_TXCLK+ 22
GMCH_TXCLK- 22
15mA
C156
0.1U_0402_16V4Z
+VDDLT18
2
1
2
E9
F7
G12
+1.8VS
L10
1
2
BLM18AG601SN1D_2P
1
2
+1.8VS
C157
4.7U_0805_10V4Z
12/08 update BOM structure
PVT 20100309 update ENBKL_WOVB net
GMCH_ENVDD 22
ENBKL_WOVB
ENBKL_VB
R73
R74
GMCH_ENBKL
R71 1 WOVB@2 0_0402_5%
R72 1 VB@
2 0_0402_5%
R76 1 VB@
2 0_0402_5%
GMCH_INVT_PWM 22
3
If support VB, pop VB@ and reserve R71
R75
11/10 FOR UMA HDMI DET.
MIS.
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
STRP_DATA
RSVD
TESTMODE
UMA_HDMI_DET
D9
D10
UMA_HDMI_DET 23
D12
1
R81
2
0_0402_5%
AE8
AD8
D13
AUX_CAL(NC)
SUS_STAT# 26
To SB
SUS_STAT_R# 15
Strap pin
12/14 update to Dual MOS
DVT 0131 change Q62 to SB570020410
1
2
R84
1.8K_0402_5%
+3VS
Wire-OR
RS880 A11(SA000032710)
+3VS
2
R106
1
4.7K_0402_5%
R149
4.7K_0402_5%
0.95V
2
+1.8VS
1.1V
0_0402_5%
NB_ALLOW_LDTSTOP
2
GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%
ENBKL 22,34
Q41B
GMCH_ENBKL 5
4
Q41A
2
PD on chip side
DMN66D0LDW-7_SOT363-6
1
R91
1
DMN66D0LDW-7_SOT363-6
1
R87
1
R88
1
R89
1
LOW
R90
1K_0402_5%
2
2
2
FBMA-L11-160808-221LMT 0603
C153
2.2U_0603_6.3V6K
+VDDLT18
12/14 ADD net name
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
1
2
+VDDLTP18
300mA
1
1
3
HIGH
POWER_SEL
P
L8
+VDDLTP18
C14
D15
C16
C18
C20
E20
C22
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
GMCH_TXOUT0+ 22
GMCH_TXOUT0- 22
GMCH_TXOUT1+ 22
GMCH_TXOUT1- 22
GMCH_TXOUT2+ 22
GMCH_TXOUT2- 22
RS780M_FCBGA528
RS880
25 ALLOW_LDTSTOP
Check if needed?
U3C
120mA
+VDDA18PCIEPLL
15,25,34 A_RST#
26 NB_PWRGD
11/15 close to NB
25 NB_DISP_CLKP
25 NB_DISP_CLKN
2
0_0402_5%
AMD suggest
F12
E12
F14
G15
H15
H14
+NB_PLLVDD
+NB_HTPVDD
12/07 remove net CLK_NB_14.318M
remove CLK_NBGFX
(remove Ext. CLK)
+VDDA18HTPLL
R965 1
R966 1
@
11/07
checklist
is 110mA
DAC_RSET
2
G14
715_0402_1%
65mA
+NB_PLLVDD
A12
+NB_HTPVDD 20mA
D14
B12
1
R65
1
2
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
15,24 GMCH_CRT_HSYNC
15,24 GMCH_CRT_VSYNC
24 GMCH_CRT_CLK
24 GMCH_CRT_DATA
L9
1
GMCH_CRT_B
24 GMCH_CRT_B
+VDDA18PCIEPLL
FBMA-L11-160808-221LMT 0603
C154
2.2U_0603_6.3V6K
GMCH_CRT_G
24 GMCH_CRT_G
2
+1.8VS
GMCH_CRT_R
24 GMCH_CRT_R
4 NB_PWRGD_R
1
FBMA-L11-160808-221LMT 0603
C150
2.2U_0603_6.3V6K
Y
6
1
1
A
4
VGA_ENBKL
D
4
Q62
MUX@
2
G
3
17 VGA_ENBKL
1
+1.8VS
4mA
+AVDDQ
2
FBMA-L11-160808-221LMT 0603
C148
2.2U_0603_6.3V6K
1
ĺ
20mA
L6
8,26,34 SB_PWRGD
U4
NC7SZ08P5X_NL_SC70-5
1
2
1
4.7K_0402_5%
2
NB_LDTSTOP#
4
U8
2
1
4.7K_0402_5%
1
2
1
R64
+AVDDDI
2
125mA
1
Y
A
B
NC7SZ08P5X_NL_SC70-5
CRT/TVOUT
1
FBMA-L11-160808-221LMT 0603
C145
0.1U_0402_16V4Z
2
FBMA-L11-160808-221LMT 0603
C146
2.2U_0603_6.3V6K
B
L4
+NB_HTPVDD
L5
1
1
8,25 LDT_STOP#
2.2U_0603_6.3V6K
2
2
2
22U_0805_10V4Z
1U_0402_6.3V6K
+1.8VS
+1.8VS
C143
1
2
3
1
FBMA-L11-160808-221LMT 0603
C144
1
PLL PWR
LVTM
2
C679
1
PM
2
L3
C142
1U_0402_6.3V6K
NB_PWRGD
G
+3VS
1
CLOCKs
1
1
2
+AVDD1
FBMA-L11-160808-221LMT 0603
C141
2.2U_0603_6.3V6K
C684
1
2
3
+NB_PLLVDD
L2
1
+1.8VS
R63
2.2K_0402_5%
1
R417
@
300_0402_5%
E
+1.8VS
2
1
4.7K_0402_5%
+1.1VS
+1.8VS
0.1U_0402_16V4Z
1
2
5
2
+1.8VS
P
B
G
A
S
2N7002-7-F_SOT23
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
RS880 VEDIO/CLK GEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
13
of
54
A
B
0.1U_0402_16V4Z
+VDDHT
1
C177
1
C178
2
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K
+1.8VS
2
2
1
FBMA-L11-201209-221LMA30T_0805
1
C181
4.7U_0805_10V4Z
C179
2
700mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE
1
1
C192
1
C185
1
C190
C186
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1
1
2
2
1
1
+
2
2
12/11 update
1
23mA
2
C1159 C1160 C1161 C1162 C1163
2
1
1
1
2
2
2
2
SP@ SP@ SP@ SP@
11/07 100mA
1
1
R927
SP@
+1.5VS
0_0402_5%
RS880 A11(SA000032710)
2
1
4.7U_0805_10V4Z
2
+VDD_MEM
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
11/04 for Side Port power
60mA
C198
0.1U_0402_16V4Z
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
1
2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
+3VS
1
5mA
2
1
0.1U_0402_16V4Z
1
H11
H12
VDD33_1(NC)
VDD33_2(NC)
RS780M_FCBGA528
ĺ
C197
1U_0402_6.3V6K
1
C1164
1U_0402_6.3V6K
SP@
2
2
1
0.1U_0402_16V4Z
+1.8VS
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
2
1
0.1U_0402_16V4Z
F9
G9
AE11
AD11
2
1
SP@
AE10
AA11
Y11
AD10
AB10
AC10
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
2
1
0.1U_0402_16V4Z
10mA
+1.8VS
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
2
1
ĺ
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
1
1
330U_D2E_2.5VM
L15
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
C196
1
C176
C189
1
1
C175
+NB_CORE
10A
C184
1
C174
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
10U_0805_10V4Z
2
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C195
@
C261
680mA
1
1
C172
C173
10U_0805_10V4Z
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
C183
10U_0603_6.3V6M
1
2 4.7U_0805_10V4Z
1
1
0.1U_0402_16V4Z
2
1
C168
C171
C188
L14
+1.1VS
C163
0.1U_0402_16V4Z
11/07
checklist
is 400mA
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
2 10U_0805_10V4Z
2 10U_0805_10V4Z
C180
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
H18
G19
F20
E21
D22
B23
A23
1
1
0.1U_0402_16V4Z
700mA
C161
C160
C162
C194
C170
1
+VDDA11PCIE
0.1U_0402_16V4Z
C169
1
2.5A
C193
C164
1
ĺ
1
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
0.1U_0402_16V4Z
+VDDHTRX
0.1U_0402_16V4Z
1
FBMA-L11-201209-221LMA30T_0805
PART 5/6
C187
1U_0402_6.3V6K
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
0.1U_0402_16V4Z
L13
U3E
J17
K16
L16
M16
P16
R16
T16
+1.1VS
C182
2
2
2
0.1U_0402_16V4Z
1
1
2
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
C167
L12
C191
2
4.7U_0805_10V4Z
C159
U3F
1
0.1U_0402_16V4Z
C166
1
0.1U_0402_16V4Z
1
600mA
1
C165
2
E
1U_0402_6.3V6K
1
FBMA-L11-201209-221LMA30T_0805
POWER
2
D
GROUND
L11
1.3A
+1.1VS
C
RS880 A11(SA000032710)
1
C199
2
2
0.1U_0402_16V4Z
11/07
25mA
11/04 for Side Port power
11/03 follow CRB
15 SPM_MA[0..13]
3
2
R928
1K_0402_1%
SP@
1
2
SPM_MA0
SPM_MA1
SPM_MA2
SPM_MA3
SPM_MA4
SPM_MA5
SPM_MA6
SPM_MA7
SPM_MA8
SPM_MA9
SPM_MA10
SPM_MA11
SPM_MA12
SPM_MA13
C1165
0.1U_0402_16V4Z
SP@
2
VREFDA
1
R929
1K_0402_1%
SP@
C1166
0.1U_0402_16V4Z
SP@
1
2
U3D
SPM_MA[0..13]
1
12/11 follow CRB
15 SPM_BA0
15 SPM_BA1
15 SPM_BA2
SPM_BA0
SPM_BA1
SPM_BA2
AD16
AE17
AD17
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
15 SPM_CLK
15 SPM_CLK#
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
3
SPM_DQ[0..15] 15
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15
SPM_DQS0
SPM_DQS0 15
MEM_DQS0P/DVO_IDCKP(NC) Y17
SPM_DQS0#
SPM_DQS0# 15
MEM_DQS0N/DVO_IDCKN(NC) W18
SPM_RAS#
SPM_DQS1
W12 MEM_RASb(NC)
SPM_DQS1 15
SPM_RAS#
MEM_DQS1P(NC) AD20
SPM_CAS#
SPM_DQS1#
Y12
AE21
SPM_DQS1# 15
SPM_CAS#
MEM_CASb(NC)
MEM_DQS1N(NC)
SPM_WE#
AD18 MEM_WEb(NC)
SPM_WE#
+1.8VS
SPM_CS#
SPM_DM0
AB13 MEM_CSb(NC)
W17
SPM_DM0 15
SPM_CS#
MEM_DM0(NC)
SPM_CKE
SPM_DM1
AB18 MEM_CKE(NC)
AE19
SPM_DM1 15
SPM_CKE
MEM_DM1/DVO_D8(NC)
SPM_ODT
L107 SP@
V14 MEM_ODT(NC)
15mA +IOPLLVDD18
SPM_ODT
1
2
2
1
IOPLLVDD18(NC) AE23
SPM_CLK
+IOPLLVDD
FBMA-L11-160808-221LMT 0603
100_0402_1% SP@
V15 MEM_CKP(NC)
IOPLLVDD(NC) AE24
SPM_CLK#
R930
W14 MEM_CKN(NC)
1
2
26mA
40.2_0402_1%SP@
SP@C1167
SP@
C1167
IOPLLVSS(NC) AD23
MEM_COMPP AE12
R9311
2.2U_0603_6.3V6K
2
MEM_COMPN AD12 MEM_COMPP(NC)
VREFDA
SP@ L108
1
2
+1.5VS
+1.1VS
MEM_COMPN(NC)
MEM_VREF(NC) AE18
40.2_0402_1%SP@
2
1
R932
RS780M_FCBGA528
FBMA-L11-160808-221LMT 0603
12/11 update
11/24 Add net name
1
2
11/04 checklist and CRB is different , check again
C1168
SP@
2.2U_0603_6.3V6K
15
15
15
15
15
15
4
SPM_DQ[0..15]
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
SBD_MEM/DVO_I/F
+1.5VS
4
RS880 A11(SA000032710)
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
RS880 PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
14
of
54
5
4
3
2
1
U9
SPM_MA[0..13]
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
SPM_DQ13
SPM_DQ8
SPM_DQ10
SPM_DQ12
SPM_DQ15
SPM_DQ11
SPM_DQ14
SPM_DQ9
+1.5VS
12/11 update +1.5VS
12/11 update +1.5VS
+1.5VS
12/11 update Res.
same as CRB
+1.5VS
12/11 update Res.
same as CRB
1
R184
1K_0402_1%
SP@
C1169
SP@
12/11 update +1.5VS
R196
1K_0402_1%
SP@
C439
SP@
0.1U_0402_16V4Z
2
2
SPM_DQ2
SPM_DQ1
SPM_DQ5
SPM_DQ3
SPM_DQ7
SPM_DQ0
SPM_DQ4
SPM_DQ6
M2
N8
M3
14 SPM_BA0
14 SPM_BA1
14 SPM_BA2
SPM_CLK
SPM_CLK#
14 SPM_CLK
14 SPM_CLK#
14 SPM_CKE
DQSL
DQSU
SPM_DM0
SPM_DM1
E7
D3
DML
DMU
SP_VREFDQ
1
0.1U_0402_16V4Z
2
R197
1K_0402_1%
SP@
RESET
11/06 Side Port Memory Vendor List
Reference AMD Recommended Vendor List
Document Number: RVL_RS880SPA9
September 16, 2009
+1.5VS
0.1U_0402_16V4Z
1
2
1
2
+1.5VS
1
2
11/03 follow CRB
1
2
C1171
1
2
C1172
Vendor and Part Number
Speed
64Mx16
Samsung K4W1G1646E-HC15
600 MHz
64Mx16
Samsung K4W1G1646E-HC12
600 MHz
64Mx16
Hynix H5TQ1G63BFR-14C
600 MHz
64Mx16
Hynix H5TQ1G63BFR-12C
600 MHz
0.1U_0402_16V4Z
C
12/11 update +1.5VS
1
2
1
2
1
2
1
ZQ/ZQ0
J1
L1
J9
L9
R180 SP@
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
11/10 follow CRB
12/11 update +1.5VS
L8
0.1U_0402_16V4Z
C471 SP@
10U_0603_6.3V6M
1
2
R933
10K_0402_5%
SP@
SP@ 2
Memory Configuration
C470 SP@
10U_0603_6.3V6M
26 SP_DDR3_RST#
T2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
C440
12/11 update +1.5VS
C469 SP@
10U_0603_6.3V6M
SP_DDR3_RST#
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
SP_VREFCA
+1.5VS
C468 SP@
10U_0603_6.3V6M
SPM_DQS0# G3
SPM_DQS1# B7
14 SPM_DQS0#
14 SPM_DQS1#
+1.5VS
F3
C7
A1
A8
C1
C9
D2
E9
F1
H2
H9
0.1U_0402_16V4Z
2
SP@
14 SPM_DM0
14 SPM_DM1
C
SPM_DQS0
SPM_DQS1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
12/11 update +1.5VS
C1170
SP@
1
SP@
14 SPM_DQS0
14 SPM_DQS1
ODT/ODT0
CS/CS0
RAS
CAS
WE
B2
D9
G7
K2
K8
N1
N9
R1
R9
C448 SP@
1U_0402_6.3V6K
SPM_ODT K1
L2
SPM_CS#
J3
SPM_RAS#
K3
SPM_CAS#
L3
SPM_WE#
CK
CK
CKE/CKE0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C447 SP@
1U_0402_6.3V6K
14 SPM_ODT
14
14
14
14
J7
K7
K9
BA0
BA1
BA2
1
R185
1K_0402_1%
SP@
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
1
D
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VREFCA
VREFDQ
1
SPM_MA0
SPM_MA1
SPM_MA2
SPM_MA3
SPM_MA4
SPM_MA5
SPM_MA6
SPM_MA7
SPM_MA8
SPM_MA9
SPM_MA10
SPM_MA11
SPM_MA12
SPM_MA13
2
SP_VREFCA M8
SP_VREFDQ H1
SPM_DQ[0..15]
1
14 SPM_DQ[0..15]
2
14 SPM_MA[0..13]
B1
B9
D1
D8
E2
E8
F9
G1
G9
VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
DVT 0119 update U9 BOM Structure
Side port and Strap setting
B
B
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Debug Mode
2
R92
2
R93
13,24 GMCH_CRT_VSYNC
@
1
3K_0402_5%
1
3K_0402_5%
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
Load EEPROM Strap
13 SUS_STAT_R#
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable
0 : Enable
D1 @
CH751H-40_SC76
2
1
2
R264 @
A_RST# 13,25,34
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
1
3K_0402_5%
11/04 check strap for side port again
Enable Side Port Memory
Enable Side Port Memory
13,24 GMCH_CRT_HSYNC
2
R94
2
R95
1 WOSP@
3K_0402_5%
SP@ 1
3K_0402_5%
+3VS
RS880: HSYNC#
0:
Enable
1 : Disable
Register Readback of strap:
NB_CLKCFG:CLK_TOP_SPARE_D[1]
A
A
11/04 change bom structure for enable side port
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/7/14
2010/03/12
Deciphered Date
Title
Side Port Memory
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
NELA5 LA-6141P
Date:
5
4
3
2
Sheet
Wednesday, April 21, 2010
1
15
of
54
4
12 PCIE_GTX_C_MRX_P[0..15]
12 PCIE_GTX_C_MRX_N[0..15]
3
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
2
1
PCIE_MTX_C_GRX_P[0..15] 12
PCIE_MTX_C_GRX_N[0..15] 12
add for VB support.
R96
10K_0402_5%
1
2
@
U5G
LVDS CONTROL
GFX PCIE LANE REVERSAL
D
AK27
AJ27
VARY_BL
DIGON
U5A
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
Y33
Y32
PCIE_MTX_C_GRX_P14 Y35
PCIE_MTX_C_GRX_N14 W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
PCIE_MTX_C_GRX_P13 W38
PCIE_MTX_C_GRX_N13 V37
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
B
U38
T37
T35
R36
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
R38
P37
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
P35
N36
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
N38
M37
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
M35
L36
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
L38
K37
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
K35
J36
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
J38
H37
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
H35
G36
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
G38
F37
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
F35
E37
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_TX4P
PCIE_TX4N
PCI EXPRESS INTERFACE
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
C
V35
U36
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
T33
T32
T30
T29
P33
P32
P30
P29
N33
N32
N30
N29
L33
L32
L30
L29
K33
K32
J33
J32
K30
K29
H33
H32
PCIE_GTX_MRX_P15C200 1
2
PCIE_GTX_MRX_N15C201
1
2
VGA@
VGA@
PCIE_GTX_MRX_P14C202 1
2
PCIE_GTX_MRX_N14C203
1
2
VGA@
VGA@
PCIE_GTX_MRX_P13C204 1
2
PCIE_GTX_MRX_N13C205
1
2
VGA@
VGA@
PCIE_GTX_MRX_P12C206 1
2
PCIE_GTX_MRX_N12C207
1
2
VGA@
VGA@
PCIE_GTX_MRX_P11C208 1
2
PCIE_GTX_MRX_N11C209
1
2
VGA@
VGA@
PCIE_GTX_MRX_P10C210 1
2
PCIE_GTX_MRX_N10C211
1
2
VGA@
VGA@
PCIE_GTX_MRX_P9 C212 1
2
PCIE_GTX_MRX_N9 C213
1
2
VGA@
VGA@
PCIE_GTX_MRX_P8 C214 1
2
PCIE_GTX_MRX_N8 C215
1
2
VGA@
VGA@
PCIE_GTX_MRX_P7 C216 1
2
PCIE_GTX_MRX_N7 C217
1
2
VGA@
VGA@
PCIE_GTX_MRX_P6 C218 1
2
PCIE_GTX_MRX_N6 C219
1
2
VGA@
VGA@
PCIE_GTX_MRX_P5 C220 1
2
PCIE_GTX_MRX_N5 C221
1
2
VGA@
VGA@
PCIE_GTX_MRX_P4 C222 1
2
PCIE_GTX_MRX_N4 C223
1
2
VGA@
VGA@
PCIE_GTX_MRX_P3 C224 1
2
PCIE_GTX_MRX_N3 C225
1
2
VGA@
VGA@
PCIE_GTX_MRX_P2 C226 1
2
PCIE_GTX_MRX_N2 C227
1
2
VGA@
VGA@
PCIE_GTX_MRX_P1 C228 1
2
PCIE_GTX_MRX_N1 C229
1
2
VGA@
VGA@
PCIE_GTX_MRX_P0 C230 1
2
PCIE_GTX_MRX_N0 C231
1
2
VGA@
VGA@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P15
0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
AJ38
AK37
0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
0.1U_0402_16V7K PCIE_GTX_C_MRX_N13
For M96, AH16 is NC
For Mahatten need PD
2
R99
1
VGA@ 10K_0402_5%
0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
0.1U_0402_16V7K PCIE_GTX_C_MRX_N12
0.1U_0402_16V7K PCIE_GTX_C_MRX_P11
0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
0.1U_0402_16V7K PCIE_GTX_C_MRX_N10
0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
0.1U_0402_16V7K PCIE_GTX_C_MRX_N9
AA30
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
VGA_TXCLK+
VGA_TXCLK-
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AW37
AU35
VGA_TXOUT0+
VGA_TXOUT0-
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AR37
AU39
VGA_TXOUT1+
VGA_TXOUT1-
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AP35
AR35
VGA_TXOUT2+
VGA_TXOUT2-
TXOUT_L3P
TXOUT_L3N
AN36
AP37
VGA_TXCLK+ 22
VGA_TXCLK- 22
VGA_TXOUT0+ 22
VGA_TXOUT0- 22
VGA_TXOUT1+ 22
VGA_TXOUT1- 22
C
VGA_TXOUT2+ 22
VGA_TXOUT2- 22
216-0729002 A12 M96_BGA962
MAD@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P7
0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
0.1U_0402_16V7K PCIE_GTX_C_MRX_N5
0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
0.1U_0402_16V7K PCIE_GTX_C_MRX_N4
U5 PARK@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
0.1U_0402_16V7K PCIE_GTX_C_MRX_N3
PARK XT-M2 A11
PARK A11 (SA00003MC10)
0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
0.1U_0402_16V7K PCIE_GTX_C_MRX_N2
B
Pre MP
PARK A11 (SA00003MC70)-R3
0.1U_0402_16V7K PCIE_GTX_C_MRX_P1
0.1U_0402_16V7K PCIE_GTX_C_MRX_N1
0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
0.1U_0402_16V7K PCIE_GTX_C_MRX_N0
+3VSG
DVT 0121 update D44,D45 to SC1H751H010
PCIE_REFCLKP
PCIE_REFCLKN
NC#1
NC#2
NC_PWRGOOD
PCIE_CALRP
PCIE_CALRN
Y30
R98
Y29
R100 1 VGA@ 2
1 VGA@ 2
1.27K_0402_1%
2K_0402_1%
R491
10K_0402_5%
VGA@
VGA@
D45
CH751H-40PT_SOD323-2
1
25,32,33 PLT_RST#
+1.0VSG
2
VGA_RST#
D44
1
25 PE_GPIO0
PERSTB
1
VGA_RST#
TXOUT_U3P
TXOUT_U3N
0.1U_0402_16V7K PCIE_GTX_C_MRX_P8
0.1U_0402_16V7K PCIE_GTX_C_MRX_N8
CALIBRATION
AJ21
AK21
AH16
AG38
AH37
AF35
AG36
1
25 CLK_PEG_VGA
25 CLK_PEG_VGA#
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
LVTMDP
CLOCK
AB35
AA36
AH35
AJ36
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
0.1U_0402_16V7K PCIE_GTX_C_MRX_P14
0.1U_0402_16V7K PCIE_GTX_C_MRX_N14
D
AK35
AL36
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
PCIE_MTX_C_GRX_P15 AA38
PCIE_MTX_C_GRX_N15 Y37
VGA_PNL_PWM 22
VGA_ENVDD 22
R97
1
2
10K_0402_5%
VGA@
2
5
216-0729002 A12 M96_BGA962
MAD@
2
CH751H-40PT_SOD323-2
VGA@
R492
2.2K_0402_5%
@
Pop for PX verify
2
MAD A12 (SA00003M300)
+3VSG
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/7/14
2010/03/12
Deciphered Date
Title
M96_ PCIE / LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
NELA5 LA-6141P
Date:
5
4
3
2
Sheet
Wednesday, April 21, 2010
1
16
of
54
5
4
3
2
1
U5B
Setting
VGA_DIS
GPIO9
VGA Disable determines
0: VGA Controller capacity enabled
1: The device will not be recognized as the system’s VGA controller
0
TX_DEEMPH_EN
Transmitter Power Saving Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO0
D
GPIO13,12,11 (config 2,1,0) :
a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.
GPIO13
GPIO12
GPIO11
CONFIG[2]
CONFIG[1]
CONFIG[0]
BIOS_ROM_EN
GPIO22
AUD[1]
AUD(0)
GPIO2
RESERVED
H2SYNC
GPIO8
GPIO21
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
0
00: No audio function;
10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software
BIF_GEN2_EN
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
NC on Park
001
Enable external BIOS ROM device
0: Diable, 1: Enable
HSYNC
VSYNC
TX1P_DPA1P
TX1M_DPA1N
1
memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010
b) If BIOS_ROM_EN = 0, then Config[2:0] defines
the primary memory aperture size.
DPA
1
PCI Express Transmitter De-emphasis Enable
0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
GPIO1
TX0P_DPA2P
TX0M_DPA2N
MUTI GFX
11
0
Internal use only. THIS PAD HAS AN INTERNAL
PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
NC on Park
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
DVT 0125 unstuff R117,R110,D2,R1096
+3VSG
+3VSG
VGA@ R104 1
VGA@ R107 1
@ R109 1
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
12/23 change Res. to 10k Ohm
@ R110 1
2 10K_0402_5%
VGA_AC_DET
@ R111 1
2 10K_0402_5%
SOUT_GPIO8
DPD
R105
R108
1 VGA@
1 VGA@
2 4.7K_0402_5%
2 4.7K_0402_5%
TX4P_DPD1P
TX4M_DPD1N
I2C
VGA_LCD_CLK
VGA_LCD_DAT
22 VGA_LCD_CLK
22 VGA_LCD_DAT
AK26
AJ26
TX5P_DPD0P
TX5M_DPD0N
SCL
SDA
@ R113 1
SIN_GPIO9
2 10K_0402_5%
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
12/17 add ACIN net
VGA@ R115
@ R116
@ R117
@ R118
@ R119
1
1
1
1
1
2
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
ROMSE_GPIO22
GENERICC
34,41 ACIN
34 EC_ACIN
R1096
1 @
1
R1097
@
0_0402_5%
2
ACIN_R
2
0_0402_5%
2
1
R120
VGA@
10K_0402_5%
THM_ALERT#
VRAM
1
O
O
1
1
O
O
Samsung (SA00003MQ00/K4W2G1646B-HC12)
1
1
1
O
Hynix (SA00003VS00/H5TQ2G63BFR-12C)
1
1
1
1
49 GPU_VID1
ROMSE_GPIO22
T12
TRSTB
T14
128MX16
<4 pcs>
TCK
TMS
T17
GENERICC
1
1
2
1
2
1
@
2
@
TMS
2 249_0402_1%
+1.0VSG
L21
BLM18AG121SN1D_0603
2
1
VGA@
2
VGA@
XTALOUT
27MCLK
1M_0603_5%
R148
1
2
VGA@
2
VGA@
1
2
VGA@
1
2
VGA@
VDD1DI
VSS1DI
R2
R2B
G2
G2B
B2
B2B
C
Y
COMP
AH13
AV31
AU30
H2SYNC
V2SYNC
HPD1
A2VDDQ
VREFG
DDC/AUX
PLL/CLOCK
120mA
AM32
AN32
DPLL_PVDD
DPLL_PVSS
AN31
AV33
AU34
2
VGA@
C263
VGA@
18P_0402_50V8J
2
VGA@
1
2
VGA@
DDC1CLK
DDC1DATA
AUX1P
AUX1N
150mA
27MCLK
XTALOUT
DPLL_VDDC
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
AF29
AG29
AK32
AJ32
AJ33
U6 VGA@
1
2
3
4
VDD
SDATA
D-
ALERT#
THERM#
GND
6
2
5
R597
0_0402_5%
THM_ALERT#
1
D
VGA@
1
R101
VGA@
Address 1001 101X b
AT33
AU32
2
2.2K_0402_5%
+3VSG
12/23 change Res. to 2.2kOhm
+3VSG
AU14
AV13
+3VSG
AT15
AR14
R102
4.7K_0402_5%
VGA@
AU16
AV15
VGA_SMB_CK2
AT17
AR16
R103
4.7K_0402_5%
VGA@
4
AU20
AT19
VGA_SMB_DA2
3
EC_SMB_CK2
EC_SMB_CK2
8,34
EC_SMB_DA2
8,34
Q5B VGA@
DMN66D0LDW-7_SOT363-6
EC_SMB_DA2
6
VGA@
DMN66D0LDW-7_SOT363-6
1
AT21
AR20
Q5A
NC on Park
AU22
AV21
DVT 0128 change to SB00000DH00
AT23
AR22
AD39
AD37
VGA_CRT_R
24
AE36
AD35
VGA_CRT_G
24
AF37
AE38
VGA_CRT_B
24
AC36
AC38
VGA_CRT_HSYNC
VGA_CRT_VSYNC
AB34
R122
DPLUS
DMINUS
1 VGA@
AD34
AE34
+AVDD
AC33
AC34
+VDD1DI
2
C
24
24
499_0402_1%
70mA
45mA
1
2
VGA@
AC30
AC31
AD30
AD31
AF30
AF31
1
AC32
AD32
AF32
2
VGA@
1
2
VGA@
1
2
VGA@
2
1
2
VGA@
2
1
L16
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@
L17
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@
12/08 remove AND gate,add EC_ACIN net
2
VGA@
AD29
AC29
THERMAL
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
TSVDD
TSVSS
DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
216-0729002 A12 M96_BGA962
MAD@
+3VSG
H2SYNC
V2SYNC
AG31
AG32
+VDD1DI
AG33
+A2VDD
AD33
+AVDD
B
50mA
V2SYNC
H2SYNC
12/15 update
12/15 update
AM26
AN26
Strap
R140
715_0402_1%
1
2
VGA@
12/15 update
@ R132 1
@ R134 1
VGA_CRT_VSYNC
VGA_CRT_HSYNC
+3VSG
VGA_HDMI_SCLK 23
VGA_HDMI_SDATA 23
2 10K_0402_5%
2 10K_0402_5%
12/23 update R141.R142 Res.
VGA_CRT_CLK
VGA_CRT_DATA
MUX@
MUX@
FLASH ROM
HDMI
DVT 0128
Set to MUX@
R141 1
R142 1
2 4.7K_0402_5%
2 4.7K_0402_5%
MUX@ R143 1
MUX@ R144 1
MUX@ R145 1
2 150_0402_1%
2 150_0402_1%
2 150_0402_1%
A 1-Mbit serial EEPROM is
required on GDDR5 designs
DDR3 can be removed
DVT 0131 R143,R144,R145
with MUX@
AM27
AL27
AM19
AL19
FLASH ROM
11/12 ADD VGA ROM
DVT 0119 SET TO @
U901
AN20
AM20
SIN_GPIO9
5
CLK_GPIO10
6
ROMSE_GPIO22
1
AL30
AM30
AL29
AM29
AN21
AM21
NC on Park
VGA_CRT_CLK
VGA_CRT_DATA
VGA_CRT_CLK 24
VGA_CRT_DATA 24
@
R969
0_0402_5%
R970
CRT
AJ30
AJ31
AK30
AK29
7
+3VSG
3
8
NC on Park
Deciphered Date
2010/03/12
SOUT_GPIO8
2
S
TYPE 1
HOLD
W
VCC
VSS
4
A
Title
M96_Strape/DP/HDMI//CRT
Size
C
Date:
2
Q
C
Compal Electronics, Inc.
Compal Secret Data
2009/7/14
@
D
M25P10-AVMN6P
C1182
.1U_0402_16V7K
@
0_0402_5%@
Security Classification
3
MUX@ R136 1
MUX@ R137 1
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_HDMI_SCLK
VGA_HDMI_SDATA
2 10K_0402_5%
2 10K_0402_5%
DVT 0119
Remove R138,R139(NO NEED)
20mA
AF33
AA29
VGA@
2
1
R1088
0_0603_5%
130mA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
VGA_SMB_DA2
7
ADM1032ARMZ-2REEL_MSOP8
AR32
AT31
Issued Date
5
VGA_SMB_CK2
8
SCLK
D+
DAC2
R2SET
20mA
+TSVDD
1
C260
0.1U_0402_16V4Z
C262
VGA@
18P_0402_50V8J
L23
BLM18AG121SN1D_0603
2
1
VGA@
1
C259
1U_0402_6.3V6K
VGA@
1
RSET
AVDD
AVSSQ
+1.8VSG
C258
10U_0603_6.3V6M
Y1
2
27MHZ_16PF_X5H027000FG1H
HSYNC
VSYNC
+DPLL_PVDD
1
GPU_THERM_D+
GPU_THERM_D-
A
B
BB
DAC1
A2VSSQ
+DPLL_VDDC
1
2
VGA@
TESTEN 18
For VGA boot unstable issue
VGA@
G
GB
A2VDD
+VGA_VREF
2 VGA@
0.1U_0402_16V4Z
1
C245
L20
BLM18AG121SN1D_0603
2
1
VGA@
1
C253
0.1U_0402_16V4Z
TESTEN
2 499_0402_1%
1 VGA@
AR30
AT29
+1.8VSG
TCK
2
10K_0402_5%
1 VGA@
R135
C256
1U_0402_6.3V6K
2
10K_0402_5%
R133
C251
1U_0402_6.3V6K
1 @
R420
+1.8VSG
C250
0.1U_0402_16V4Z
TRSTB
1 @
R421
Internal PD
PD-Reset
C249
10U_0603_6.3V6M
2
10K_0402_5%
AK24
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
VDD2DI
VSS2DI
C252
10U_0603_6.3V6M
+3VSG
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
1 @
R147
1 @
2
R146 0_0402_5%
34 VGA_DBCLK
VGA_HDMI_DET
23,26 VGA_HDMI_DET
@
2
1
2
2
1
1
2
@
Park NC pins
R131
10K_0402_5%
2
@
R130
10K_0402_5%
+3VSG
R129
10K_0402_5%
R128
10K_0402_5%
@
R126
10K_0402_5%
@
R125
10K_0402_5%
@
R124
10K_0402_5%
B
R123
10K_0402_5%
1
+1.8VSG
2
GPU_THERM_D+
2200P_0402_50V7K
VGA@ 1
2
C233
GPU_THERM_D-
C241
10U_0603_6.3V6M
O
Hynix (SA000032420/H5TQ1G63BFR-12C)
VGA_HDMI_TXD2+ 23
VGA_HDMI_TXD2- 23
C239
0.1U_0402_16V4Z
Samsung (SA000035720/K4W1G1646E-HC12)
GPU_VID1
AT27
AR26
1
C232
VGA@
C240
1U_0402_6.3V6K
64MX16
<4 pcs>
T11
VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0
VGA_HDMI_TXD1+ 23
VGA_HDMI_TXD1- 23
C238
22U_0805_6.3V6M
GPU_VID0
49 GPU_VID0
Location
Park
(XT)
VGA_HDMI_TXD0+ 23
VGA_HDMI_TXD0- 23
AU26
AV25
C237
0.1U_0402_16V4Z
11/12 FOR VGA ROM
AT25
AR24
+3VSG
C236
1U_0402_6.3V6K
CH751H-40PT_SOD323-2
2VGA_AC_DET
@
VGA_ENBKL
SOUT_GPIO8
SIN_GPIO9
CLK_GPIO10
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
1
D2
13 VGA_ENBKL
12/08 add EC_ACIN net
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
VGA_HDMI_TXC+ 23
VGA_HDMI_TXC- 23
Not share via for other GND
R
RB
GENERAL PURPOSE I/O
C
AU24
AV23
2
TX_PWRS_ENB
External VGA Thermal Sensor
TXCAP_DPA3P
TXCAM_DPA3N
5
0
2
VIP Device Strap Enable indicates to the software driver
0: Driver would ignore the value sampled on VHAD_0 during reset
1: VHAD_0 to determine whether or not a VIP slave device
2
V2SYNC
0.1U_0402_16V4Z
VIP_DEVICE_EN
1
Pin Straps description
1
Strap Name
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
1
17
of
54
5
4
3
2
1
Park only support single channel
memory (channel B only)
11/04 delete channelA
U5D
U5C
+1.5VSG
R155
R158
R159
L18
L20
1 VGA@ 2
L27
1 VGA@ 2 240_0402_1% N12
1 VGA@ 2 240_0402_1% AG12
240_0402_1%
1 VGA@ 2
M12
1 VGA@ 2 240_0402_1% M27
1 VGA@ 2 240_0402_1% AH12
240_0402_1%
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
MVREFDA
MVREFSA
CKEA0
CKEA1
NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
WEA0B
WEA1B
MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2
RSVD#1
RSVD#2
RSVD#3
216-0729002 A12 M96_BGA962
MAD@
If use M96 upper resistor will
change to 100ohm for
MVREFDA/B and MVREFSA/B
Mahatten upper resistor use 40.2ohm
R153
VGA@
100_0402_1%
K20
K17
C265
VGA@
1
2
K24
K27
M13
K16
+1.5VSG
K21
J20
MVREFDB Y12
MVREFSB AA12
R156
VGA@
40.2_0402_1%
K26
L15
GCORE_SEN
AF28
AG28
AL31
GCORE_SEN 49
R165
VGA@
100_0402_1%
H23
J19
T8
W8
MAB13 21
M96 no support
In M97, Medison and Park, AF28 is
FB_VDDC, AG28 is FB_VDDCI, AH29 is
FB_GND. GCORE_SEN and FB_GND
should route as differential pair Same
as VDDCI_SEN and FB_GND
MEMORY INTERFACE B
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
T7
W7
ODTB0
ODTB1
QSB_0B/WDQSB_0
QSB_1B/WDQSB_1
QSB_2B/WDQSB_2
QSB_3B/WDQSB_3
QSB_4B/WDQSB_4
QSB_5B/WDQSB_5
QSB_6B/WDQSB_6
QSB_7B/WDQSB_7
ODTB0
ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
17 TESTEN
MVREFSB
TESTEN
VGA@2
1
R161
10K_0402_5%
TEST_MCLK
TEST_YCLK
C267
VGA@
1
2
If use M96 upper resistor will
change to 100ohm for
MVREFDA/B and MVREFSA/B
Mahatten upper resistor use
40.2ohm
2
2
1
1
R169
VGA@
51.1_0402_1%
AD28
AK10
AL10
C269 VGA@
0.1U_0402_16V4Z
RSVD#9
RSVD#11
MVREFDB
K23
K19
C268 VGA@
0.1U_0402_16V4Z
RSVD#5
RSVD#6
J14
H14
0.1U_0402_16V4Z
R160
R162
R164
MVREFDA
MVREFSA
RASA0B
RASA1B
R151
VGA@
40.2_0402_1%
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
DRAM_RST
QSB[0..7] 21
C
QSB#[0..7]
AD8
AD7
CLKB1
CLKB1#
T10
Y10
RASB0#
RASB1#
W10
AA10
CASB0#
CASB1#
P10
L10
CSB0#_0
AD10
AC10
CSB1#_0
U10
AA11
CKEB0
CKEB1
N10
AB11
WEB0#
WEB1#
CLKB0 21
CLKB0# 21
CLKB1 21
CLKB1# 21
RASB0# 21
RASB1# 21
CASB0# 21
CASB1# 21
CSB0#_0 21
CSB1#_0 21
B
CKEB0 21
CKEB1 21
WEB0# 21
WEB1# 21
R163
4.7K_0402_5%
1
2
VGA@
R166 VGA@
51.1_0402_1%
1
2
AH11
1 C270
VGA@
2
VRAM_RST# 21
68P_0402_50V8J
10K_0402_5%
12/07 change R166 to 51.1Ohm
change C270,R168 connection
R170
VGA@
51.1_0402_1%
M96
Broadway
4.7k Ohm
SD028470180
0 Ohm
SD028000080
4.7k Ohm
SD028470180
1000 pF
SE074102K80
R166
C270
10k Ohm
SD028100280
680 Ohm
SD028680080
2010/03/12
Deciphered Date
68 pF
SE071680J80
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Memory
Rev
0.1
NELA5 LA-6141P
Date:
5
4
3
A
DNI
Compal Electronics, Inc.
Compal Secret Data
2009/7/14
+1.5VSG
R168
VGA@
R163
Security Classification
QSB#[0..7] 21
ODTB0 21
ODTB1 21
CLKB0
CLKB0#
M96 use 4.7K to
PD directly.
A
DQMB#[0..7] 21
QSB[0..7]
L9
L8
216-0729002 A12 M96_BGA962
MAD@
B_BA[0..2] 21
DQMB#[0..7]
TESTEN
CLKTESTA
CLKTESTB
B_BA[0..2]
R168
Issued Date
MAB[0..12] 21
D
2
B
CLKA1
CLKA1B
H27
G27
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
1
2
CLKA0
CLKA0B
+1.5VSG
1
2
VGA@
1
J21
G19
2
C1255
0.1U_0402_16V4Z
R1092
VGA@
100_0402_1%
ODTA0
ODTA1
1
1
MVREFSA
A34
E30
E26
C20
C16
C12
J11
F8
2
2
R1091
VGA@
40.2_0402_1%
QSA_0B/WDQSA_0
QSA_1B/WDQSA_1
QSA_2B/WDQSA_2
QSA_3B/WDQSA_3
QSA_4B/WDQSA_4
QSA_5B/WDQSA_5
QSA_6B/WDQSA_6
QSA_7B/WDQSA_7
1
1
+1.5VSG
2
2
C34
D29
D25
E20
E16
E12
J10
D7
1
VGA@
QSA_0/RDQSA_0
QSA_1/RDQSA_1
QSA_2/RDQSA_2
QSA_3/RDQSA_3
QSA_4/RDQSA_4
QSA_5/RDQSA_5
QSA_6/RDQSA_6
QSA_7/RDQSA_7
2
C1254
2
C
1
A32
C32
D23
E22
C14
A14
E10
D9
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
1
R1090
VGA@
100_0402_1%
0.1U_0402_16V4Z
1
MVREFDA
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
21 MDB[0..63]
2
2
R1089
VGA@
40.2_0402_1%
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
1
1
+1.5VSG
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
2
12/15 update
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
0.1U_0402_16V4Z
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MEMORY INTERFACE A
MAB[0..12]
D
MDB[0..63]
2
Sheet
Wednesday, April 21, 2010
1
18
of
54
5
4
3
2
1
U5E
+1.5VSG
2
C335 VGA@
1U_0402_6.3V6K
C
330U_B2_2VM_R15M
+
2
12/08 remove Cap.---ok
update C340 to 220u_B2
PVT 20100304 change to 330U
12/09 remove Cap.---ok
+VGA_CORE
B
2
5A
1
2
+VDDCI
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
FBMA-L11-201209-221LMA30T_0805
L96
VGA@
2
1
FBMA-L11-201209-221LMA30T_0805
L97
VGA@
1
2
1
2
1
2
1
2
C376 VGA@
1U_0402_6.3V6K
1
C375 VGA@
1U_0402_6.3V6K
2009/7/14
C340
C374 VGA@
1U_0402_6.3V6K
Issued Date
2
1
1
VGA@
+VGA_CORE
A
Confirm ATI, for
Mahattan, it could be
connected to VGA_CORE
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2
1
2
+VGA_CORE
M97 and Mahattan VDDC and
VDDCI ball assignments are
different from M96, If M96 is
populated on this
design,VDDC and VDDCI
shoudl be shorted.
C384 VGA@
10U_0805_6.3V6M
216-0729002 A12 M96_BGA962
MAD@
2
1
2
1
BIF_VDDCI (T27,N27) need
isolate VGA_CORE
*Confirm with AMD
2
SPV18 For
Mahattan only
VGA@
2
1
R569
0_0603_5%
+VGA_BIF
C383 VGA@
10U_0805_6.3V6M
M15
N13
R12
T12
1
2
1
11/05 for layout guideline
C382 VGA@
10U_0805_6.3V6M
ISOLATED VDDCI#1
CORE I/O VDDCI#2
VDDCI#3
VDDCI#4
2
2
2
1
C373 VGA@
1U_0402_6.3V6K
12/08 remove Cap.
1
1
1
C372 VGA@
1U_0402_6.3V6K
BBP#1
BBP#2
2
2
2
C371 VGA@
1U_0402_6.3V6K
BACK BIAS
2
1
1
C370 VGA@
1U_0402_6.3V6K
AA13
Y13
SPVSS
2
1
2
C369 VGA@
1U_0402_6.3V6K
32mA
SPV10
2
1
2
1
2
1
C325 VGA@
1U_0402_6.3V6K
AN10
NC_SPV18
1
2
1
2
1
C334 VGA@
1U_0402_6.3V6K
AN9
2
1
2
1
C324 VGA@
1U_0402_6.3V6K
AM10
136mA
NC_MPV18#1
NC_MPV18#2
1
2
1
C368 VGA@
1U_0402_6.3V6K
2
50mA
PCIE_PVDD
2
1
C367 VGA@
1U_0402_6.3V6K
2
1
C365 VGA@
0.1U_0402_16V4Z
2
2
1
C364 VGA@
1U_0402_6.3V6K
1
C379 VGA@
0.1U_0402_16V4Z
2
C378 VGA@
1U_0402_6.3V6K
A
C377 VGA@
10U_0603_6.3V6M
2
For M96 SPV10=+GPU_CORE
For M97,Nahattan SPV10=+1.0VS
+SPV10
C366 VGA@
10U_0603_6.3V6M
+1.8VSG
BLM18AG121SN1D_0603
2
1
L35
VGA@
1
1
2
1
L34
VGA@
BLM18AG121SN1D_0603 1
150mA
H7
H8
1
C333 VGA@
1U_0402_6.3V6K
+MPV_18
PLL
AB37
34.6A
C323 VGA@
1U_0402_6.3V6K
68mA
+PCIE_PVDD
+SPV_18
+1.0VSG
VDDRHB
VSSRHB
For M96 only,
Manhattan are NC pin
2
C332 VGA@
1U_0402_6.3V6K
V12
U12
VDDRHA
VSSRHA
VGA@
D
C322 VGA@
1U_0402_6.3V6K
M20
M21
L24
C304 VGA@
10U_0805_6.3V6M
2
MEM CLK
C358 VGA@
0.1U_0402_16V4Z
2
C357 VGA@
1U_0402_6.3V6K
2
1
2
1
C363 VGA@
0.1U_0402_16V4Z
1
C362 VGA@
1U_0402_6.3V6K
2
C361 VGA@
0.1U_0402_16V4Z
2
C360 VGA@
1U_0402_6.3V6K
2
C359 VGA@
10U_0603_6.3V6M
MPV18 For
Mahattan only
1
C356 VGA@
10U_0603_6.3V6M
2
BLM18AG121SN1D_0603
2
1
L32
VGA@
1
1
+1.8VSG
B
1
2
1
C331 VGA@
1U_0402_6.3V6K
+1.8VSG
2
1
C321 VGA@
1U_0402_6.3V6K
2
1
L31 VGA@
BLM18AG121SN1D_0603
1
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4
2
1
C303 VGA@
1U_0402_6.3V6K
AD12
AF11
AF12
AG11
2
1
C330 VGA@
C345 VGA@
1U_0402_6.3V6K 10U_0805_6.3V6M
170mA
1
2
C320 VGA@
1U_0402_6.3V6K
VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4
12/08 remove
Cap.
C302 VGA@
1U_0402_6.3V6K
AF13
AF15
AG13
AG15
2
1
C272 VGA@
1U_0402_6.3V6K
170mA
2
1
C329 VGA@
C344 VGA@
1U_0402_6.3V6K 10U_0805_6.3V6M
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
2
C319 VGA@
1U_0402_6.3V6K
AF23
AF24
AG23
AG24
1
C301 VGA@
1U_0402_6.3V6K
I/O
60mA
2
1
C328 VGA@
C343 VGA@
1U_0402_6.3V6K 10U_0805_6.3V6M
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
2
C318 VGA@
1U_0402_6.3V6K
LEVEL
TRANSLATION
1
C300 VGA@
1U_0402_6.3V6K
+VDDR4_5
AF26
AF27
AG26
AG27
1
+1.0VSG
C327 VGA@
C342 VGA@
1U_0402_6.3V6K 10U_0805_6.3V6M
+VDDR3
136mA
AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28
2
C317 VGA@
1U_0402_6.3V6K
+VDD_CT
2A
2
1
C299 VGA@
1U_0402_6.3V6K
2
2
1
C326 VGA@
C341 VGA@
1U_0402_6.3V6K 10U_0805_6.3V6M
2
1
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74
1
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
BLM18AG601SN1D_2P
2
1
+1.8VSG
+PCIE_VDDR
C316 VGA@
1U_0402_6.3V6K
2
12/08 remove Cap.
1
C350 VGA@
0.1U_0402_16V4Z
1
C349 VGA@
1U_0402_6.3V6K
BLM18AG601SN1D_2P
2
CORE
400mA
C298 VGA@
1U_0402_6.3V6K
+1.8VSG
VGA@
1
1
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
POWER
L27
2
2
2
C338 VGA@
0.1U_0402_16V4Z
C
1
1
C315 VGA@
0.1U_0402_16V4Z
2
2
C337 VGA@
1U_0402_6.3V6K
1
C336 VGA@
10U_0603_6.3V6M
2
1
L26
VGA@
BLM18AG121SN1D_0603
1
2
C312 VGA@
1U_0402_6.3V6K
+3VSG
2
1
C297VGA@
1U_0402_6.3V6K
2
1
C314 VGA@
1U_0402_6.3V6K
1
2
C311 VGA@
1U_0402_6.3V6K
2
C313 VGA@
10U_0603_6.3V6M
2
1
L25
VGA@
BLM18AG121SN1D_0603
1
1
C296VGA@
1U_0402_6.3V6K
2
2
C310 VGA@
1U_0402_6.3V6K
1
1
C295VGA@
1U_0402_6.3V6K
2
2
C273 VGA@
1U_0402_6.3V6K
1
1
C294VGA@
1U_0402_6.3V6K
2
C309 VGA@
10U_0805_6.3V6M
2
1
C293VGA@
1U_0402_6.3V6K
1
C308 VGA@
10U_0805_6.3V6M
+1.8VSG
2
2
C292VGA@
1U_0402_6.3V6K
2
1
1
C307 VGA@
10U_0805_6.3V6M
1
2
C306 VGA@
10U_0805_6.3V6M
2
C305 VGA@
10U_0805_6.3V6M
1
1
C291VGA@
1U_0402_6.3V6K
2
C290VGA@
1U_0402_6.3V6K
1
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
C289 VGA@
10U_0805_6.3V6M
12/08 update C274 to 220u_B2
D
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
C286 VGA@
1U_0402_6.3V6K
2
PCIE
C285 VGA@
1U_0402_6.3V6K
2
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
MEM I/O
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
C284 VGA@
1U_0402_6.3V6K
2
1
C283 VGA@
0.1U_0402_16V4Z
2
1
C282 VGA@
0.1U_0402_16V4Z
2
1
2900mA
TBD AC7
C281 VGA@
1U_0402_6.3V6K
2
1
C280 VGA@
1U_0402_6.3V6K
2
1
C279 VGA@
1U_0402_6.3V6K
2
1
C278 VGA@
1U_0402_6.3V6K
2
1
C277 VGA@
1U_0402_6.3V6K
220U_B2_2.5VM_R15M
1
+
C276 VGA@
1U_0402_6.3V6K
C274
C271 VGA@
1U_0402_6.3V6K
VGA@
C275 VGA@
1U_0402_6.3V6K
1
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
M96_Power/GND
Rev
0.1
NELA5 LA-6141P
Date:
5
4
3
2
Sheet
Wednesday, April 21, 2010
1
19
of
54
5
4
3
U5F
+1.8VSG
DPC_VDD10#1
DPC_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
AP31
AP32
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AN27
AP27
AP28
AW24
AW26
+DPD_VDD18
AP14
AP15
AW18
+DPE_VDD18
L47
VGA@
BLM18AG121SN1D_0603
2
1
130mA
NC_DPD_VDD18#1
NC_DPD_VDD18#2
NC_DPB_VDD18#1
NC_DPB_VDD18#2
DPB_VDD10#1
DPB_VDD10#2
AN33
AP33
1
2
C420 VGA@
1U_0402_6.3V6K
Ball AW34 and AW35
are GND ball in M96,
but have another ball
name in Broadway,
that is XO_IN and
X0_IN2.
2
C419 VGA@
0.1U_0402_16V4Z
2
1
AL33
AM33
DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
DPCD_CALR
DPAB_CALR
AF34
AG34
+DPF_VDD18
12/08 remove Res.
+DPF_VDD10
AK33
AK34
L50
VGA@
BLM18AG121SN1D_0603
2
1
DPE_VDD10#1
DPE_VDD10#2
DPB_PVDD
DPB_PVSS
AV29
AR28
AF39
AH39
AK39
AL34
AM34
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPC_PVDD
DPC_PVSS
AU18
AV17
AV19
AR18
+DPA_PVDD
B
20mA
DPF_VDD18#1
DPF_VDD18#2
DPE_PVDD
DPE_PVSS
AM37
AN38
+DPE_PVDD
20mA
DPF_VDD10#1
DPF_VDD10#2
AL38
AM35
+DPF_PVDD
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
DPEF_CALR
2
216-0729002 A12 M96_BGA962
MAD@
2
2
1
2
1
2
+1.8VSG
L53
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
C438
VGA@
10U_0603_6.3V6M
1
C437
VGA@
1U_0402_6.3V6K
2009/7/14
1
L51
VGA@
BLM18AG121SN1D_0603
2
1
For M96 are NC pins
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
216-0729002 A12 M96_BGA962
2
+1.8VSG
20mA
DPD_PVDD
DPD_PVSS
1
Issued Date
1
12/15 update
C436
VGA@
0.1U_0402_16V4Z
A39
AW1
AW39
C
L44
VGA@
BLM18AG121SN1D_0603
2
1
+DPA_PVDD
2
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
2
+1.0VSG
C432
VGA@
10U_0603_6.3V6M
2
2
C431
VGA@
1U_0402_6.3V6K
2
1
1
1
+DPA_PVDD
C435 VGA@
1U_0402_6.3V6K
1
2
L43
VGA@
BLM18AG121SN1D_0603
2
1
VGA@
1
1 AM39
1
2
+1.8VSG
For M96 are NC pins
+DPA_PVDD
150_0402_1%
C434 VGA@
0.1U_0402_16V4Z
C433 VGA@
10U_0603_6.3V6M
2
2
R176
150_0402_1%
2
R179
2
VGA@
1
1
C430
VGA@
0.1U_0402_16V4Z
L52
VGA@
BLM18AG121SN1D_0603
2
1
2
C429 VGA@
1U_0402_6.3V6K
2
1
2
1
M96_Power/GND
Rev
0.1
NELA5 LA-6141P
MAD@
Date:
5
4
3
D
20mA
NC_DPF_PVDD
NC_DPF_PVSS
C428 VGA@
0.1U_0402_16V4Z
C427 VGA@
10U_0603_6.3V6M
2
AW28
AU28
AV27
120mA
1
AN29
AP29
AP30
AW30
AW32
DP PLL POWER
DPA_PVDD
DPA_PVSS
200mA
1
2
20mA
AN34
AP39
AR39
AU37
AW35
1
+DPB_VDD10
20mA
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
12/08 remove Res.
1
+DPB_VDD18
200mA
DPD_VDD10#1
DPD_VDD10#2
120mA
+DPE_VDD10
C418 VGA@
10U_0603_6.3V6M
1
AH34
AJ34
2
1
C414
VGA@
10U_0603_6.3V6M
R175
150_0402_1%
2
1
VGA@
+DPA_VDD10
C413
VGA@
1U_0402_6.3V6K
AN19
AP18
AP19
AW20
AW22
L41
VGA@
BLM18AG121SN1D_0603
2
1
1
AP25
AP26
200mA
+DPD_VDD10
2
L38
VGA@
BLM18AG121SN1D_0603
1
+1.0VSG
C408
VGA@
10U_0603_6.3V6M
130mA
AP22
AP23
2
1
200mA
200mA
+1.0VSG
2
+1.8VSG
For M96 are NC pins
C402
VGA@
10U_0603_6.3V6M
AN17
AP16
AP17
AW14
AW16
2
+DPA_VDD18
1
C407
VGA@
1U_0402_6.3V6K
2
For PX, leave NC when
SBIOS control PWR on/off
+1.8VSG
1
C397
VGA@
10U_0603_6.3V6M
AP13
AT13
130mA
AN24
AP24
C412
VGA@
0.1U_0402_16V4Z
2
1
NC_DPA_VDD18#1
NC_DPA_VDD18#2
200mA
C411
VGA@
1U_0402_6.3V6K
12/08 update BOM structure
1
C410
VGA@
0.1U_0402_16V4Z
2
C409
VGA@
10U_0603_6.3V6M
1
NC_DPC_VDD18#1
NC_DPC_VDD18#2
DP A/B POWER
C406
VGA@
0.1U_0402_16V4Z
2
DP C/D POWER
C401
VGA@
1U_0402_6.3V6K
1
AP20
AP21
L45
VGA@
BLM18AG121SN1D_0603
2
1
FB_GND 1 VGA@ 2
R1098
0_0402_5%
+1.0VSG
2
C396
VGA@
1U_0402_6.3V6K
2
130mA
C405 VGA@
1U_0402_6.3V6K
2
C404 VGA@
0.1U_0402_16V4Z
2
1
1
1
U5H
C400
VGA@
0.1U_0402_16V4Z
2
2
C399 VGA@
1U_0402_6.3V6K
1
1
C395
VGA@
0.1U_0402_16V4Z
2
L42
VGA@
BLM18AG121SN1D_0603
2
1
1
1 VGA@ 2
R402
0_0402_5%
1
C390 VGA@
1U_0402_6.3V6K
2
C393
VGA@
1U_0402_6.3V6K
1
C398 VGA@
0.1U_0402_16V4Z
2
+1.8VSG
2
1
+DPC_VDD10
C392
VGA@
0.1U_0402_16V4Z
L40
VGA@
BLM18AG121SN1D_0603
2
1
1
For M96 are NC pins
DVT 0119 add FB_GND
1
2
2
+1.0VSG
2
L39
VGA@
BLM18AG121SN1D_0603
2
1
1
+1.8VSG
+DPC_VDD18
1
C389 VGA@
0.1U_0402_16V4Z
+1.0VSG
1
L37
VGA@
BLM18AG121SN1D_0603
2
1
C388 VGA@
10U_0603_6.3V6M
2
2
C387 VGA@
1U_0402_6.3V6K
1
C386 VGA@
0.1U_0402_16V4Z
For M96 are NC pins
C403 VGA@
10U_0603_6.3V6M
A
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AH29
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
C394 VGA@
10U_0603_6.3V6M
B
GND
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#152
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#162
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#176
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
GND#100
C391
VGA@
10U_0603_6.3V6M
C
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
C385 VGA@
10U_0603_6.3V6M
D
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
L36
VGA@
BLM18AG121SN1D_0603
2
1
2
Sheet
Wednesday, April 21, 2010
1
20
of
54
5
4
3
U13
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
D
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
18 B_BA0
18 B_BA1
18 B_BA2
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
CLKB0
CLKB0#
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB3
QSB1
F3
C7
DQSL
DQSU
DQMB#3
DQMB#1
E7
D3
DML
DMU
QSB#3
QSB#1
G3
B7
DQSL
DQSU
18 MAB[13..0]
ODTB0_1
18
18
18
18
18 DQMB#[7..0]
CSB0#_0
RASB0#
CASB0#
WEB0#
MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29
D7
C3
C8
C2
A7
A2
B8
A3
MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8
VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
+1.5VSG
J7
K7
K9
18 CKEB0
E3
F7
F2
F8
H3
H8
G2
H7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
BA0
BA1
BA2
MDB[0..63]
18 MDB[0..63]
2
U14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
M2
N8
M3
CLKB0
CLKB0#
CKEB0
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB2
QSB0
F3
C7
DQSL
DQSU
DQMB#2
DQMB#0
E7
D3
DML
DMU
QSB#2
QSB#0
G3
B7
DQSL
DQSU
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#
E3
F7
F2
F8
H3
H8
G2
H7
MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16
D7
C3
C8
C2
A7
A2
B8
A3
MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5
VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
+1.5VSG
B_BA0
B_BA1
B_BA2
+1.5VSG
1
U15
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
CLKB1
CLKB1#
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB4
QSB5
F3
C7
DQSL
DQSU
DQMB#4
DQMB#5
E7
D3
DML
DMU
QSB#4
QSB#5
G3
B7
DQSL
DQSU
CSB1#_0
RASB1#
CASB1#
WEB1#
E3
F7
F2
F8
H3
H8
G2
H7
MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36
D7
C3
C8
C2
A7
A2
B8
A3
MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42
VREFCB_A4 M8
VREFDB_Q4 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
+1.5VSG
M2
N8
M3
ODTB1_1
18
18
18
18
VREFCA
VREFDQ
B_BA0
B_BA1
B_BA2
18 CKEB1
+1.5VSG
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
U16
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
BA0
BA1
BA2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51
D7
C3
C8
C2
A7
A2
B8
A3
MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60
D
+1.5VSG
B_BA0
B_BA1
B_BA2
M2
N8
M3
CLKB1
CLKB1#
CKEB1
J7
K7
K9
CK
CK
CKE/CKE0
ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB6
QSB7
F3
C7
DQSL
DQSU
DQMB#6
DQMB#7
E7
D3
DML
DMU
QSB#6
QSB#7
G3
B7
DQSL
DQSU
+1.5VSG
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
+1.5VSG
18 QSB[7..0]
ZQ/ZQ0
VRAM_RST#
L8
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VSG
J1
L1
J9
L9
R210
VGA@
243_0402_1%
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
1
VGA@ 2
2
2
VREFCB_A3
1
R228
VGA@
4.99K_0402_1%
C481
VGA@ 2
VREFDB_Q3
1
1
C480
1
1
VREFDB_Q2
1
R218
VGA@
4.99K_0402_1%
R229
VGA@
4.99K_0402_1%
C482
VGA@ 2
2
2
VGA@ 2
R227
VGA@
4.99K_0402_1%
R217
VGA@
4.99K_0402_1%
2
C479
2
1
VREFCB_A2
1
R226
VGA@
4.99K_0402_1%
R219
VGA@
4.99K_0402_1%
R230
VGA@
4.99K_0402_1%
B
VREFCB_A4
1
C483
VGA@ 2
R231
VGA@
4.99K_0402_1%
VREFDB_Q4
1
C484
VGA@ 2
2
1
2
1
2
1
2
1
2
C505 VGA@
1U_0402_6.3V6K
2
1
C504 VGA@
1U_0402_6.3V6K
2
1
C503 VGA@
1U_0402_6.3V6K
2
1
C500 VGA@
1U_0402_6.3V6K
2
1
C499 VGA@
1U_0402_6.3V6K
2
1
C498 VGA@
1U_0402_6.3V6K
1
+1.5VSG
C497 VGA@
1U_0402_6.3V6K
2
C496 VGA@
1U_0402_6.3V6K
2
1
C495 VGA@
1U_0402_6.3V6K
2
1
C494 VGA@
1U_0402_6.3V6K
2
1
C493 VGA@
1U_0402_6.3V6K
2
1
C492 VGA@
1U_0402_6.3V6K
2
1
C491 VGA@
1U_0402_6.3V6K
2
1
C490 VGA@
1U_0402_6.3V6K
2
1
C489 VGA@
1U_0402_6.3V6K
2
1
C488 VGA@
1U_0402_6.3V6K
2
1
C487 VGA@
1U_0402_6.3V6K
+1.5VSG
+1.5VSG
2
C514 VGA@
10U_0603_6.3V6M
2
1
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
2
1
C513 VGA@
10U_0603_6.3V6M
2
2
1
C512 VGA@
10U_0603_6.3V6M
2
1
C510 VGA@
10U_0603_6.3V6M
2
1
C509 VGA@
10U_0603_6.3V6M
2
1
C508 VGA@
10U_0603_6.3V6M
2
1
C511 VGA@
10U_0603_6.3V6M
1
1
C507 VGA@
10U_0603_6.3V6M
18 CLKB1#
R235 VGA@
56_0402_1%
1
2
C506 VGA@
0.01U_0402_25V7K
18 CLKB1
R234 VGA@
56_0402_1%
1
2
1
+1.5VSG
+1.5VSG
C486 VGA@
1U_0402_6.3V6K
1
B1
B9
D1
D8
E2
E8
F9
G1
G9
1
2
2
2
1
R216
VGA@
4.99K_0402_1%
+1.5VSG
2
A
2
+1.5VSG
+1.5VSG
C502 VGA@
1U_0402_6.3V6K
1
R233 VGA@
56_0402_1%
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
C501 VGA@
1U_0402_6.3V6K
R232 VGA@
56_0402_1%
2
C485 VGA@
0.01U_0402_25V7K
18 CLKB0#
1
VGA@ 2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
0.1U_0402_16V4Z
18 CLKB0
VGA@ 2
ZQ/ZQ0
0.1U_0402_16V4Z
ODTB1_1
VREFDB_Q1
1
C478
R211
VGA@
243_0402_1%
0.1U_0402_16V4Z
R224
VGA@
4.99K_0402_1%
R225
VGA@
4.99K_0402_1%
J1
L1
J9
L9
+1.5VSG
0.1U_0402_16V4Z
18 ODTB1
1
1
1
VREFCB_A1
1
C477
R215
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R223 VGA@
56_0402_1%
2
0_0402_5%
VGA@
ODTB1 R222
0_0402_5%
RESET
+1.5VSG
0.1U_0402_16V4Z
1
R212
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R221 VGA@
56_0402_1%
2
0.1U_0402_16V4Z
1
L8
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
R214
VGA@
4.99K_0402_1%
1
VGA@
ODTB0 R220
2
18 ODTB0
2
B
R213
VGA@
4.99K_0402_1%
T2
1
J1
L1
J9
L9
+1.5VSG
ODTB0_1
VRAM_RST#
2
+1.5VSG
ZQ/ZQ0
1
R209
VGA@
243_0402_1%
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG
RESET
2
B1
B9
D1
D8
E2
E8
F9
G1
G9
T2
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
J1
L1
J9
L9
R208
VGA@
243_0402_1%
Pull high for Madison and Park...
RESET
1
L8
2
VRAM_RST# T2
1
ZQ/ZQ0
1
RESET
1
L8
2
T2
C
1
VRAM_RST#
18 VRAM_RST#
2
18 QSB#[7..0]
1
C
2009/7/14
2010/03/12
Deciphered Date
Title
VRAM_DDR3 / Channel B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
NELA5 LA-6141P
Date:
5
4
3
2
Sheet
Wednesday, April 21, 2010
1
21
of
54
5
4
3
2
1
LCD POWER CIRCUIT
+LCDVDD
LCD/LED PANEL Conn.
1
JLVDS1
Pre MP
change to 10k
1
R251
10K_0402_5%
2
2
3
DVT 0121 update Q13 to SB934130020
3
6
2
1
4
1
1K_0402_5%
1
C539
1
C540
1
4.7U_0805_10V4Z
2
1
VGA_ENVDD
Q29
MUX@
2
G
3
12/14 remove
DVT 0131
update Q29 to SB570020410
2
TXOUT2TXOUT2+
+3VS
1
TXOUT1+
TXOUT1R121
@
4.7K_0402_5%
BKOFF#
I2CC_SCL
I2CC_SDA
1
1
R260
VGA_PNL_PWM
@
1
2
R261
0_0402_5%
UMALVDS@
1
2
R262
0_0402_5%
2
1
3
4
VGA_TXOUT2- 16
VGA_TXOUT2+ 16
26 USB20_N5
26 USB20_P5
VGA_TXOUT1+ 16
VGA_TXOUT1- 16
11/30 update LVDS conn.
12/01 invert conn
LVDS conn: ACES_50406-03071-001_30P-T
VGA_TXOUT0+ 16
VGA_TXOUT0- 16
VGA_LCD_CLK
VGA_LCD_DAT
RP1 1
2
INVT_PWM
R319
10K_0402_5%
1 0_0402_5% USB20_CMOS_N5
1 0_0402_5% USB20_CMOS_P5
R298 2
R359 2
+3VS
VGA_LCD_CLK 17
VGA_LCD_DAT 17
GMCH_TXCLKGMCH_TXCLK+
0_0404_4P2R_5%
GMCH_TXOUT2GMCH_TXOUT2+
0_0404_4P2R_5%
GMCH_TXOUT1+
GMCH_TXOUT10_0404_4P2R_5%
GMCH_TXOUT0+
GMCH_TXOUT00_0404_4P2R_5%
D
35
34
33
32
31
G5
G4
G3
G2
G1
ACES_50406-03071-001
CONN@
11/30 remove DAC_BRIG
INVT_PWM
4
3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DISPOFF#
GMCH_TXCLK- 13
GMCH_TXCLK+ 13
GMCH_TXOUT2- 13
GMCH_TXOUT2+ 13
1
C543
1
C548
2
220P_0402_50V7K
C
2
220P_0402_50V7K
D14 @
6
CH3
CH2
USB20_CMOS_N5
3
GMCH_TXOUT1+ 13
GMCH_TXOUT1- 13
GMCH_LCD_CLK
GMCH_LCD_DATA
5
+3VS
GMCH_TXOUT0+ 13
GMCH_TXOUT0- 13
USB20_CMOS_P5
GMCH_LCD_CLK 13
GMCH_LCD_DATA 13,36
Vp
4
Vn
CH4
CH1
2
1
CM1293-04SO_SOT23-6
@
DVT 0131 change D14 to SC300000B00
2
GMCH_INVT_PWM
2
0_0402_5%
1
EC_INVT_PWM
2
2
1
BUS_SEL# 24,34
R253
UMALVDS@
4.7K_0402_5%
12/02 update schematic
remove inverter
check BOM structure
3
4
UMALVDS@
TXOUT21
4
TXOUT2+
2
3
UMALVDS@ RP3
TXOUT1+
1
4
TXOUT12
3
UMALVDS@ RP5
TXOUT0+
1
4
TXOUT02
3
UMALVDS@ RP7
UMALVDS@
I2CC_SCL
0_0402_5% 2
1 R269
I2CC_SDA
0_0402_5% 2
1 R271
UMALVDS@
@
12/23 change R1052 Res. to 1.5k
BUS_SEL#
2
1
0_0402_5% 2 DISO@ 1 R270
0_0402_5% 2
1 R272
DISO@
TXCLKTXCLK+
2 0_0402_5%
+3VS
0_0402_5%
3
4
TXCLKTXCLK+
VGA_TXCLK- 16
VGA_TXCLK+ 16
UMA ONLY
DISPOFF#
12/14 modify
1 MUX@ 2
2
1
DISO@RP8
DISO@
RP8
CH751H-40PT_SOD323-2
@
D9
1
2
R172 1
R1053
3
4
DISO@RP6
DISO@
RP6
TXOUT0+
TXOUT0-
2
0_0402_5%
ENBKL R174 1 @
2
C
36 PE_GPIO2
2
1
VGA_TXCLKVGA_TXCLK+
0_0404_4P2R_5%
VGA_TXOUT2VGA_TXOUT2+
0_0404_4P2R_5%
VGA_TXOUT1+
VGA_TXOUT10_0404_4P2R_5%
VGA_TXOUT0+
VGA_TXOUT00_0404_4P2R_5%
DISO@RP4
DISO@
RP4
12/14 ADD
R1052
1.5K_0402_5%
MUX@
TXOUT2TXOUT2+
VGA ONLY
0.1U_0402_16V4Z
DISO@RP2
DISO@
RP2
2N7002-7-F_SOT23
34 BKOFF#
TXOUT0TXOUT0+
TXOUT1TXOUT1+
S
13,34 ENBKL
34 COLOR_ENG_EN
34 LOCAL_DIM
C541
R507 2.7K_0402_5%
16 VGA_ENVDD
I2CC_SCL
I2CC_SDA
INVT_PWM
DISPOFF#
COLOR_ENG_EN
LOCAL_DIM
12/08 update net name
PWR_SAVING to LOCAL_DIM
TXCLKTXCLK+
D
+3VS
C545
W=60mils
1
2
1
680P_0402_50V7K 68P_0402_50V8J
2
2
DMN66D0LDW-7_SOT363-6
1
1
+LCDVDD
0.047U_0402_16V7K
2
Q11A
2
GMCH_ENVDD
13 GMCH_ENVDD
AO3413_SOT23-3
Q13
G
2
R252
C544
D
5
+LCDVDD
L59 2
1
FBMA-L11-201209-221LMA30T_0805
4.7U_0805_10V4Z
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+INVPWR_B+
B+
L58 2
1
FBMA-L11-201209-221LMA30T_0805
W=40mils
C538
S
Q11B
DMN66D0LDW-7_SOT363-6
D
+INVPWR_B+
W=60mils
1
2
12/14 update to dual MOS
update R507 to 2.7K Ohm
+3VS
+3VALW
R250
300_0603_5%
Place under U33
L
B1
UMA
H
B2
DIS
SEL2
L
B1
UMA
H
B2
DIS
+3VS
For Layout
12/07 update SEL Table
1
SEL1
2
1
1
1
Q88A
DMN66D0LDW-7_SOT363-6
MUX@
R1060
4.7K_0402_5%
MUX@
R1062
220_0402_5%
MUX@
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
6
MUX@
4
52
5
51
1
R1065
10K_0402_5%
MUX@
4
2
MUX@
54
57
DVT 0128 set R1065 to MUX@
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
SEL
SEL2
NC
NC
NC
Thermal_GND
+3VS_SWITCH
2
1
MUX@
1
2
1
MUX@
46
45
41
40
35
34
30
29
25
26
BUS_SEL#
12/02
SW input1/input2 exchange
DMN66D0LDW-7_SOT363-6
2
DMN66D0LDW-7_SOT363-6
5
Q82A
DMN66D0LDW-7_SOT363-6
MUX@
1
3
BUS_SEL
Q87B
BUS_SEL#
Q83B
DMN66D0LDW-7_SOT363-6
MUX@
5
1
2
2
0_0402_5%
2
Q87A
A
3
3
R1063
100K_0402_5%
MUX@
6
1
R1064
1
2 INVT_PWM
R316 MUX@ 0_0402_5%
5
0_0402_5%
@
16 VGA_PNL_PWM
INVT_PWM_L
Q82B
DMN66D0LDW-7_SOT363-6
MUX@
4
R1068
3
Q88B
DMN66D0LDW-7_SOT363-6
MUX@
4
1
1
VGA_TXCLKVGA_TXCLK+
VGA_TXOUT2VGA_TXOUT2+
VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT0+
VGA_TXOUT0VGA_LCD_DAT
VGA_LCD_CLK
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
2
5
34 EC_INVT_PWM
MUX@
2
Pop for PX verify
4
10
18
27
38
50
56
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
2
R1061
100K_0402_5%
MUX@
Q83A
DMN66D0LDW-7_SOT363-6
MUX@
1
1
12/11 update Res.
6
13 GMCH_INVT_PWM
48
47
43
42
37
36
32
31
22
23
MUX@
2
6
+3VS
GMCH_TXCLKGMCH_TXCLK+
GMCH_TXOUT2GMCH_TXOUT2+
GMCH_TXOUT1+
GMCH_TXOUT1GMCH_TXOUT0+
GMCH_TXOUT0GMCH_LCD_DATA
GMCH_LCD_CLK
2
2
3
7
8
11
12
14
15
19
20
C1152 C1153 C1154
TXCLKTXCLK+
TXOUT2TXOUT2+
TXOUT1+
TXOUT1TXOUT0+
TXOUT0I2CC_SDA
I2CC_SCL
17
BUS_SEL#
0.1U_0402_16V4Z
U68
12/07 update PX/VB support schematic
12/14 update dual MOS
2
BUS_SEL
R1128
10K_0402_5%
MUX@
2
R1127
10K_0402_5%
MUX@
B
4.7U_0603_6.3V6K
R926
0_0603_5%
2
1
1
+5VS
0.1U_0402_16V4Z
PVT 20100311 update R253 to UMALVDS@
1
6
9
13
16
21
24
28
33
39
44
49
53
55
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A
PI3LVD400ZFEX_TQFN56_11X5
MUX@
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
LVDS Connector
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
1
B
22
of
54
3
2
1
R281
HDMI_HPD
2
150K_0402_5%
E
Q18
MMBT3904_NL_SOT23-3
1
2K_0402_5%
2
HDMI_R_D0+
HDMI_R_D1HDMI_SCLK
HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
HDMI_SDATA
1
20
21
22
23
D
SUYIN-100042GR019M23DZL
CONN@
@
2
R278
1
0_0402_5%
HDMI conn: SUYIN_100042GR019M22LZR_19P-T
@
2
R279
1
0_0402_5%
11/30 update HDMI conn.
PVT 20100311 update HDMI conn.
(SUYIN_100042GR019M23DZL_19P-T)
11/03 change BOM structure
12/08 for UMA
Place closed to JHDMI1
2
1
1
0_0402_5%
HDMI_R_CK+
HDMI_R_D0-
Q16
BSH111 1N_SOT23-3
Check 5V tolerant
R283
365K_0402_1%
@
UMA_HDMI_DET 2
R938
13 UMA_HDMI_DET
1
1
3
VGA_HDMI_DET 2 MUX@ 1
R282
0_0402_5%
1
2
2
1
C
17,26 VGA_HDMI_DET
R277
Q17
BSH111 1N_SOT23-3
1
1
2
2
1
2
2
3
2
2
R1071 2 MUX@ 1 0_0402_5%
R280
0_0402_5%
@
2
B
HDMI_R_CKR276
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
D
R1072
0_0402_5%
R1069
D
UMAHDMI@
1 0_0402_5%
S
17 VGA_HDMI_SDATA
R937 2
HDMI_SDATA
HDMI_SCLK
+HDMI_5V_OUT
3
S
13 GMCH_HDMI_DATA
12/08 for UMA
@
G
<5V tolerant>
+3VSG
@
R1070 2 MUX@ 1 0_0402_5%
17 VGA_HDMI_SCLK
+3VS
UMAHDMI@
1 0_0402_5%
R275
10K_0402_5%
R936 2
13 GMCH_HDMI_CLK
R274
1
2
DVT 0120 add Bypass Res.
DVT 0131 D3 with @, R1105 stuff,set D3 to SCSH491D010
R935
10K_0402_5%
2
0_0603_5%
R934
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
G
D
11/03 for UMA HDMI
12/08 add VGA 0Ohm Res.
C549
0.1U_0402_16V4Z
1
1
R1105
1
1.1A_6VDC_FUSE
+3VSG
4.7K_0402_5%
CH491DPT_SOT23-3
W=40mils
2
2
F1
1+HDMI_5V_OUT_1 1
1
2
4.7K_0402_5%
D3 @
+5VS
+3VS
HDMI_HPD
+3VS
2K_0402_5%
+HDMI_5V_OUT
1
JHDMI1
DVT 0119 remove R1068
PVT 20100311 update BOM structure
11/03 fchange BOM structure
2
4
0_0402_5%
1
5
R284
2
11/03 for UMA HDMI DET 10K_0402_5%
DVT 0128 change to UMAHDMI@
Pre MP 20100406 stuff R938
C
C
12/04 remove GPU 0Ohm resistor
12 PCIE_MTX_GRX_N0
12 PCIE_MTX_GRX_P0
C1173 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX2C1174 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX2+
12 PCIE_MTX_GRX_N1
12 PCIE_MTX_GRX_P1
C1175 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX1C1176 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX1+
12 PCIE_MTX_GRX_N2
12 PCIE_MTX_GRX_P2
C1177 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX0C1178 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_TX0+
12 PCIE_MTX_GRX_N3
12 PCIE_MTX_GRX_P3
C1179 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_CLKC1180 UMAHDMI@
2
1 0.1U_0402_16V7K HDMI_CLK+
12/23 UMAHDMI@ USE 715Ohm
2 UMAHDMI@
1 0_0402_5%
R947
2
1
R948UMAHDMI@0_0402_5%
2 UMAHDMI@
1 0_0402_5%
R949
2
1
R950UMAHDMI@0_0402_5%
2 UMAHDMI@
1 0_0402_5%
R951
2
1
R952UMAHDMI@0_0402_5%
2 UMAHDMI@
1 0_0402_5%
R954
2
1
R955UMAHDMI@0_0402_5%
HDMI_C_TX2HDMI_C_TX2+
HDMI_C_TX2HDMI_C_TX2+
R286 1
R287 1
MUX@ 499_0402_1%
2
2
HDMI_C_TX1HDMI_C_TX1+
R289 1
R290 1
MUX@ 499_0402_1%
MUX@ 499_0402_1%
2
2
HDMI_C_TX0HDMI_C_TX0+
R292 1
R293 1
MUX@ 499_0402_1%
MUX@ 499_0402_1%
2
2
HDMI_C_CLKHDMI_C_CLK+
R294 1
R295 1
MUX@ 499_0402_1%
MUX@ 499_0402_1%
2
2
HDMI_C_TX1HDMI_C_TX1+
HDMI_C_TX0HDMI_C_TX0+
HDMI_C_CLKHDMI_C_CLK+
17 VGA_HDMI_TXD217 VGA_HDMI_TXD2+
C550 MUX@2
C551 MUX@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_TX2HDMI_C_TX2+
17 VGA_HDMI_TXD117 VGA_HDMI_TXD1+
C552 MUX@2
C553 MUX@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_TX1HDMI_C_TX1+
DVT 0131
change D19 to SB570020410
HDMI_C_CLK-
R285 1
HDMI_R_CK-
0_0402_5%
2
C554 MUX@2
C555 MUX@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
17 VGA_HDMI_TXC17 VGA_HDMI_TXC+
C556 MUX@2
C557 MUX@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_CLKHDMI_C_CLK+
R953
1
+HDMI_5V_OUT
2
4.7K_0402_5%
1
17 VGA_HDMI_TXD017 VGA_HDMI_TXD0+
D
3
MUX@ 499_0402_1%
HDMI_C_TX0HDMI_C_TX0+
S
1
L60
WCM-2012-900T_0805
@
4
2N7002-7-F_SOT23
Q19
2
G
12/02 update HDMI_C_TX+ to HDMI_C_TX-
4
3
2
3
R288 1
2
0_0402_5%
HDMI_R_CK+
HDMI_C_TX0-
R291 1
2
0_0402_5%
HDMI_R_D0-
1
L61
WCM-2012-900T_0805
@
4
11/03 ADD UMA HDMI / change BOM structure
VGA resistor is 499ohm, and UMA resistor is 715ohm?
Switchable connection?
2
HDMI_C_CLK+
B
11/10 Add 4.7k Ohm
1
1
2
4
3
HDMI_C_TX0+
R296 1
2
HDMI_C_TX1-
R297 1
2
1
L62
WCM-2012-900T_0805
@
4
B
1
2
4
3
2
3
0_0402_5%
HDMI_R_D0+
0_0402_5%
HDMI_R_D1-
2
3
HDMI_C_TX1+
R299
1
2
0_0402_5%
HDMI_R_D1+
HDMI_C_TX2-
R300
1
2
0_0402_5%
HDMI_R_D2-
1
L63
WCM-2012-900T_0805
@
4
HDMI_C_TX2+
1
2
4
R301 1
3
2
2
3
0_0402_5%
HDMI_R_D2+
Place closed to JHDMI1
A
A
11/03 Change BOM structure
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
HDMI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
1
23
of
54
A
B
C
D
E
CRT Connector
W=40mils
+R_CRT_VCC
2
3
2
3
+5VS
D7
2
1
1
CH491DPT_SOT23-3
W=40mils
2
1.1A_6VDC_FUSE
1
1
D5
DVT 0131 change D7 to SCSH491D010
PJDLC05C_SOT23-3
C558
0.1U_0402_16V4Z
1
D4
PJDLC05C_SOT23-3
+CRT_VCC
F2
2
1
1
CRT_R_1
2
R408
1
0_0402_5%
CRT_G_1
2
R409
1
0_0402_5%
CRT_B_1
R305
R307
R308
C559
1
C560
2
10P_0402_50V8J
2
2
2
150_0402_1%
140_0402_1%
2 FCM2012CF-800T06_2P
CRT_R_2
L65 1
2 FCM2012CF-800T06_2P
CRT_G_2
L66 1
2 FCM2012CF-800T06_2P
CRT_B_2
L64 1
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
CRT_B
1
0_0402_5%
2
R407
1
CRT_G
1
CRT_R
150_0402_1%
1
2
C561
1
C562
2
10P_0402_50V8J
1
C563
2
10P_0402_50V8J
1
C564
1
2
2
10P_0402_50V8J
10P_0402_50V8J
1
10P_0402_50V8J
2
11/28
change to NAL00-CRT
16
17
G
G
C565
SUYIN_070546FR015S297ZR
CONN@
100P_0402_50V8J
+CRT_VCC
2
A
CRT_HSYNC_1
4
Y
C566
10P_0402_50V8J
G
CRT_HSYNC
L68 1
2
FCM2012CF-800T06_2P
U18
3
2
CRT_DET# 26
CRT_HSYNC_2
L67 1
2
FCM2012CF-800T06_2P
DSUB_12
CRT_VSYNC_2
1
1
2
2
R311
100K_0402_5%
@
1
C567
10P_0402_50V8J
74AHCT1G125GW_SOT353-5
C568 2
68P_0402_50V8J 1
+CRT_VCC
2
DSUB_15
2
C570
68P_0402_50V8J
+CRT_VCC
P
A
OE#
2
U19
Y
CRT_VSYNC_1
4
3
G
CRT_VSYNC
1
2 0.1U_0402_16V4Z
5
C571 1
2
1 10K_0402_5%
1
P
5
R312 2
1
2 0.1U_0402_16V4Z
OE#
C569 1
74AHCT1G125GW_SOT353-5
+3VS
13,15 GMCH_CRT_VSYNC
13 GMCH_CRT_DATA
R266 2 UMACRT@
1 0_0402_5%
CRT_R
GMCH_CRT_G
R83
2 UMACRT@
1 0_0402_5%
CRT_G
GMCH_CRT_B
R268 2 UMACRT@
1 0_0402_5%
CRT_B
GMCH_CRT_HSYNC
R273 2 UMACRT@
1 0_0402_5%
CRT_HSYNC
GMCH_CRT_VSYNC
R267 2 UMACRT@
1 0_0402_5%
CRT_VSYNC
GMCH_CRT_DATA
R410 2 UMACRT@
1 0_0402_5%
CRT_DATA
GMCH_CRT_CLK
13 GMCH_CRT_CLK
R406 2 UMACRT@
1 0_0402_5%
For VGA Only
17 VGA_CRT_R
17 VGA_CRT_G
17 VGA_CRT_B
17 VGA_CRT_HSYNC
17 VGA_CRT_VSYNC
4
17 VGA_CRT_DATA
17 VGA_CRT_CLK
R306 2 DISO@ 1 0_0402_5%
CRT_R
VGA_CRT_G
R302 2 DISO@ 1 0_0402_5%
CRT_G
VGA_CRT_B
R304 2 DISO@ 1 0_0402_5%
CRT_B
VGA_CRT_HSYNC
R303 2 DISO@ 1 0_0402_5%
CRT_HSYNC
VGA_CRT_VSYNC
R309 2 DISO@ 1 0_0402_5%
CRT_VSYNC
VGA_CRT_DATA
R411 2 DISO@ 1 0_0402_5%
CRT_DATA
VGA_CRT_CLK
R412 2 DISO@ 1 0_0402_5%
CRT_CLK
27
25
22
20
18
12
14
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_CLK
VGA_CRT_DATA
26
24
21
19
17
13
15
0B1
1B1
2B1
3B1
4B1
5B1
6B1
SEL1
A5
A6
SEL2
8
+CRT_VCC
+3VS
BUS_SEL# 22,34
9
10
CRT_CLK
CRT_DATA
30
BUS_SEL#
3
R317
4.7K_0402_5%
R318
4.7K_0402_5%
DSUB_12
CRT_CLK
VGA_CRT_R
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
0B2
1B2
2B2
3B2
4B2
5B2
6B2
GND
GND
GND
GND
GPAD
3
11
28
31
33
6
DSUB_15
L
B1
UMA
H
B2
DIS
SEL2
L
B1
UMA
H
B2
DIS
CRT_CLK
4
Q6B
DMN66D0LDW-7_SOT363-6
MUX@
UMACRT@
2
1
R321
0_0402_5%
PI3V712-AZLEX_TQFN32_6X3~D
MUX@
SEL1
CRT_DATA
1
Q6A
DMN66D0LDW-7_SOT363-6
MUX@
3
5
13 GMCH_CRT_B
13,15 GMCH_CRT_HSYNC
GMCH_CRT_R
1
2
5
6
7
2
13 GMCH_CRT_G
2
2
0.1U_0402_16V4Z
A0
A1
A2
A3
A4
1
13 GMCH_CRT_R
2
2
0.1U_0402_16V4Z
VDD
VDD
VDD
VDD
VDD
2
For UMA Only
Close to Conn side
U69
4
16
23
29
32
1
3
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C1155
C1156
C1157
C1158
MUX@
MUX@
MUX@
MUX@
12/02 SW input1/input2 exchange
12/07 update SEL table
UMACRT@
2
1
R323
0_0402_5%
Check 5V tolerant for DISO state
4
11/06 USE DUAL CHANNEL MOSFET , update BOM structure
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
CRT Connector
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
24
of
54
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
AA22
Y21
AA25
AA24
W23
V24
W24
W25
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
2
+1.5VS
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
Q21
FDV301N_NL_SOT23-3
2
level shift to ISL6265
12/07 ok
When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
13 CLK_SBLINK_BCLK
13 CLK_SBLINK_BCLK#
M23
P23
13 NB_DISP_CLKP
13 NB_DISP_CLKN
U29
U28
13 CLK_NBHT
13 CLK_NBHT#
T26
T27
NB_HT_CLKP
NB_HT_CLKN
V21
T21
CPU_HT_CLKP
CPU_HT_CLKN
12/07 ok
8 CLK_CPU_BCLK
8 CLK_CPU_BCLK#
12/07 ok
V23
T23
16 CLK_PEG_VGA
16 CLK_PEG_VGA#
12/07 ok
11/15 for internal CLK gen
L29
L28
N29
N28
33 CLK_PCIE_LAN
33 CLK_PCIE_LAN#
12/07 ok
M29
M28
DVT 0119 remove WLAN CLK port3
T25
V25
32 CLK_PCIE_MINI1
32 CLK_PCIE_MINI1#
L24
L23
3
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
25M_CLK_X1
1
1
2
C689
27P_0402_50V8J
Y6
N26
N27
2
25MHZ_20PF_7A25000012
P29
P28
12/08 add GPP_CLK5
DVT 0127 update
R426
1M_0603_5%
25M_CLK_X2
1
2
C688
27P_0402_50V8J
P25
M25
T29
T28
AMD suggest add Crystal for Internal CLK GEN
L25
31 CLK_SD_48M
12/07 ok
NB_DISP_CLKP
NB_DISP_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
GPP_CLK1P
GPP_CLK1N
@ R332 20M_0402_5%
1
2
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
1
R320
2 10K_0402_5%
@
2 10K_0402_5%
R1130
1
@
2 10K_0402_5%
R1131
1
@
2 10K_0402_5%
INT_VGA_EN# 36
VGA_PWRGD
2
B
1
A
4
Y
29
27,29
29
29
29
29
29
OSC
4
NC
OSC
1
NC7SZ08P5X_NL_SC70-5
1
2
R1132 @
0_0402_5%
U904
2
0_0402_5%
+3VALW
C581
1
2
AMD suggest add GPIO control gate
1
R427
1
R425
2
@ 0_0402_5%
2
0_0402_5%
A_RST#
2
0.1U_0402_16V4Z
1
B
100K_0402_5%
A
2
4
PLT_RST#
PLT_RST# 16,32,33
NC7SZ08P5X_NL_SC70-5
R328
12/14 remove bypass Res.
12/17 update Res.to 100k ohm
PX_EN# 36
2 0_0402_5% MINI1_CLKREQ#
R1075 1
MINI1_CLKREQ# 32
different to NEW75
PE_GPIO1 36
Power Xpress Support
PE_GPIO0 VGA RESET,
AJ6
AG6
AG4
AJ4
PE_GPIO0 16
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
LPCCLK0
LPC_CLK0_EC
2
22_0402_5%
1
R330
LPC_AD0 34
LPC_AD1 34
LPC_AD2 34
LPC_AD3 34
LPC_FRAME# 34
H: Enable
PE_GPIO1 VGA PWR Enable,
H: Enable
PE_GPIO2 MODE Switch,
H: VGA , L: NB
LPC_CLK0_EC 29,34
LPC_CLK1 29
3
G21
H21
K19
G22
J24
Location
RS880M
SPM_ID0
(AD12)
SPM_ID1
(AD17)
Samsung (SA000035720/K4W1G1646E-HC12)
O
1
Hynix (SA000032420/H5TQ1G63BFR-12C)
1
O
Samsung (SA00003MQ00/K4W2G1646B-HC12)
O
O
Hynix (SA00003VS00/H5TQ2G63BFR-12C)
1
1
SIDE PORE MEM
64MX16
<1 pcs>
SERIRQ 34
ALLOW_LDTSTOP 13
H_PROCHOT_R# 8
H_PWRGD 8
LDT_STOP# 8,13
LDT_RST# 8
128MX16
<1 pcs>
+RTCBATT
25M_X1
25M_X2
32K_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
C1
SB_32KHI
C2
SB_32KHO
D2
B2
B1
PAD
R331
1K_0402_5%
T21
+RTCVCC
D8
1
R333
C584 1
32.768KHZ_12.5PF_Q13MC14610002
2008/10/06
Issued Date
2
W=20mils
1 C585
2
2
510_0402_5%
3
R334
C583
1
@
for Clear CMOS
0_0603_5%
2
1
2
2010/03/12
Deciphered Date
+CHGRTC
Title
SB710-PCIE/PCI/ACPI/LPC/RTC
Date:
C
4
BAS40-04_SOT23-3
Compal Electronics, Inc.
Compal Secret Data
Security Classification
B
U21
Y
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
VGA_PWRGD_R
PCI_AD24 : VDDR Voltage SW
26 SB_GPIO_A_RST#
Close to SB
18P_0402_50V8J
1
1
2
R1133 @ 100K_0402_5%
1
R1134
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
FN_RESERVE1
C1272
1
2
@
0.1U_0402_16V4Z
@
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
VGA_PWRGD_R
+3VALW
PVT 20100311
add AND gate circuit
Pre MP unstuff AND gate
VGA_PWRGD_R
SPM_ID1
0.1U_0402_16V4Z
1
2
2
NC
SB_32KHO
2
MUX@
2
0_0402_5%
49 VGA_PWRGD
Y3
3
C586
@
1
SPM_ID0
SB820 A12(SA00003IW10)
R335
20M_0603_5%
1
R1104
SPM_ID1
14M_25M_48M_OSC
RTC
L27
+3VS
SB_32KHI
2
18P_0402_50V8J
1
25M_CLK_X2
R1103
SB820M_FCBGA605
C582
1
4
L26
2 10K_0402_5%
GPP_CLK2P
GPP_CLK2N
32K_X1
25M_CLK_X1
2 10K_0402_5%
@
0.1U_0402_16V4Z
12/07 ok
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
CLOCK GENERATOR
ISL6265 PWROK input, TTL level: 0.8V~2.0V
@
1
2
D
H_PWRGD_L 50
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
1
1
+3VS
1
R1102
FN_RESERVE1
1U_0402_6.3V6K
3
S
H_PWRGD
1
G
2
R329
4.7K_0402_5%
V2
R1101
1
+3VS
PCIE_CALRP
PCIE_CALRN
+3VS
SPM_ID0
2
590_0402_1% AD29
2K_0402_1% AD28
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
29
29
29
29
2 10K_0402_5%
5
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
PCIRST#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
2 10K_0402_5%
@
P
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
@
1
5
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
1
R1100
G
1
1
PCIE_RST#
A_RST#
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
R1099
3
2
2
PAD
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
+3VS
P
R326
R327
+1.1VS_PCIE
T4
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
W2
W1
W3
W4
Y1
G
2
2
2
2
2
2
2
2
E
1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1
1
1
1
1
1
1
1
Part 1 of 5
PCI INTERFACE
12
12
12
12
12
12
12
12
C579
C573
C574
C575
C576
C580
C577
C578
SB800
LPC
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
P1
L1
CPU
12
12
12
12
12
12
12
12
D
DVT 0119
FOR Side port mem / function reserve
PVT 20100310
Add /update net for VGA_PWRGD/function reserve
U20A
33_0402_5%
1
PCI CLKS
R325
2
A_RST#
13,15,34 A_RST#
1
2 150P_0402_50V8J
PCI EXPRESS INTERFACES
C572 1
C
3
B
2
A
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
25
of
54
A
B
2
R342 1
2 2.2K_0402_5% SB_SMCLK0
R343 1
2 2.2K_0402_5% SB_SMDAT0
R344 1
2 4.7K_0402_5%
8 H_THERMTRIP#
13 NB_PWRGD
EC_RSMRST#
34 EC_RSMRST#
12/02 add net for ODD EJECT
ACF_EN
SATA_IS1#
SB_GPIO_A_RST#
SKU_ID
MUXLESS_SEL
PX_FN
34 SATA_IS1#
25 SB_GPIO_A_RST#
SUS_STAT#
+3VS
R340 1 VGA@ 2 2.2K_0402_5%
R341 1
SKU ID: 1-> VGA *
0-> UMA
SKU_ID
Pop for PX verify
2
2
15 SP_DDR3_RST#
100K_0402_5%
R418 1 VB@
2 2.2K_0402_5%
33 LAN_CLKREQ#
PX Function: 1-> PX Enable
0-> PX Disable *
PX_FN
1
R370
SB_SMCLK0
SB_SMDAT0
SB_SMCLK1
SB_SMDAT1
VB_EN
LAN_CLKREQ#
Cinfigure to output or Internal PU/PD
Check SW:
2 100K_0402_5%
R416 1 VGA@ 2 2.2K_0402_5%
37 SB_SPKR
10,11,32 SB_SMCLK0
10,11,32 SB_SMDAT0
2
1
R588
100K_0402_5%
R1066 1
2 2.2K_0402_5% MUXLESS_SEL
MUXLESS@
2
1
R1067
100K_0402_5%
1
SP_DDR3_RST#_R
R956 0_0402_5%
11/10 For Side Port Memory Reset signal
VB Function: 1-> VB Enable
0-> VB Disable *
VB_EN
2 SP@
Muxless SEL: 1-> PX with Muxless
0-> PX with Mux *
G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
EC_LID_OUT#
34 EC_LID_OUT#
VGA_HDMI_DET#
R1073 1
2 2.2K_0402_5%
ACF_EN
ACF MODE SEL: 1-> ACF Enable
0->ACF Disable
MUX@
2
1
R1074
11/10 Remove OC#1/OC#2
100K_0402_5%
37
12/07 for muxless sel
12/08 add CLK_MODE
29
DVT 0119 change CLK MODE to ACF_EN
DVT 0128 set R1066 to MUXLESS@
37
set R1073 to MUX@
37
HDA_BITCLK_AUDIO
R345 1
2 33_0402_5%
R346 1
2 33_0402_5%
33 USB_OC#0
HDA_SDOUT
HDA_SDOUT_AUDIO
HDA_SDIN0
37 HDA_SYNC_AUDIO
37 HDA_RST_AUDIO#
USB_OC#0
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
R347 1
2 33_0402_5%
HDA_SYNC
R348 1
2 33_0402_5%
HDA_RST#
GBE_COL
GBE_CRS
12/09 Follow AMD checklist
3
GBE_MDIO
+3VALW
1
R353
1
R354
1
R356
GBE_COL
2
10K_0402_5%
GBE_CRS
2
10K_0402_5%
GBE_RXERR
2
10K_0402_5%
@
1
R349
@
1
R350
@
1
R351
1
R352
1
R358
2
2
GBE_MDIO
10K_0402_5%
GBE_PHY_INTR
10K_0402_5%
GBE_RXERR
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDIN1
2
10K_0402_5%
GBE_PHY_INTR
H3
D1
E4
D4
E8
F7
E7
F8
M3
N1
L2
M2
M1
M4
N2
P2
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
E23
E24
F21
G29
D27
F28
F29
E27
+3VALW
4
1
R355
1
R357
1
R1080
1
R1081
1
R361
1
R362
1
R363
@
@
@
@
SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SB_SMCLK1
2
2.2K_0402_5%
SB_SMDAT1
2
2.2K_0402_5%
J10
H11
USB 1.1 USB MISC
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
2 100P_0402_25V8K
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605
USB20_P14 33
USB20_N14 33
BT
B12
A12
E14
E12
USB_HSD10P
USB_HSD10N
J12
J14
USB_HSD9P
USB_HSD9N
A13
B13
USB_HSD8P
USB_HSD8N
D13
C13
USB_HSD7P
USB_HSD7N
G12
G14
USB_HSD6P
USB_HSD6N
G16
G18
USB20_P6
USB20_N6
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB20_P3
USB20_N3
J16
J18
USB20_P2
USB20_N2
USB_HSD1P
USB_HSD1N
B17
A17
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
A16
B16
USB20_P0
USB20_N0
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
D25
F23
B26
E26
F25
E22
F22
E21
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
G24
G25
E28
E29
D29
D28
C29
C28
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
EHCI13 / OHCI3
11/06 delete 3G USB
USB20_P8
USB20_N8
USB20_P8 32
USB20_N8 32
Mini1-WLAN
USB20_P6 31
USB20_N6 31
CardReader
USB20_P5 22
USB20_N5 22
Camera
EHCI2 / OHCI2
2
11/05 add USB20_P3/N3
USB20_P3 33
USB20_N3 33
Ext USB4
USB20_P2 33
USB20_N2 33
Ext USB3
USB20_P1 33
USB20_N1 33
Ext USB2
USB20_P0 33
USB20_N0 33
Ext USB1
Check SW:
Cinfigure to output or Internal PU/PD
SB_SIC
SB_SIC 8
SB_SID
12/09
SB_SID 8
GPIO199 29
GPIO200 29
EHCI1 / OHCI1
11/05 port 1~3 supply for EXT. USB/B
set net back
STRAP PIN
3
SB820 A12(SA00003IW10)
4
11/11 SB820M internal PU , add or not?
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB710 USB/HD audio
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
12/07 for Int. CLK gen
(update net name)
OHCI4
USB20_P14
USB20_N14
USB_HSD11P
USB_HSD11N
USB_HSD2P
USB_HSD2N
2
R338
1
F11
E11
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
H9
J8
CLK_48M_LAN 33
USB_RCOMP 1
11.8K_0402_1%
USB_HSD12P
USB_HSD12N
USB 2.0
+3VS
32,33 SB_PCIE_WAKE#
DVT 0119
move net,
add
ACF_EN
net.
ACPI / WAKE UP EVENTS
34 EC_GA20
34 EC_KBRST#
34 EC_SCI#
34 EC_SMI#
EC_RSMRST#
SB800
G19
GPIO
DVT 0128 set Q64 to MUX@
DVT 0131 set Q64 to SB570020410
A10
USB_RCOMP
USB OC
Q64
MUX@
2N7002-7-F_SOT23
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
USBCLK/14M_25M_48M_OSC
EMBEDDED CTRL
HPD for PX
0 -> DGPU
1 -> IGPU
34
34
34
8,13,34
13
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
EMBEDDED CTRL
CRT_DET
HD AUDIO
2
2.2K_0402_5%
J2
K1
D3
F1
H1
F2
H5
SUS_STAT#
G6
B3
T24
PAD
C4
T22
PAD
F6
T23
PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
H_THERMTRIP#
J6
NB_PWRGD
AC19
34 EC_SWI#
VGA_HDMI_DET#
S
@
C587 1
2
100_0402_5%
U20D
GBE LAN
1
2N7002-7-F_SOT23
DVT 0131 set Q22 to SB570020410
1
R337
D
2
G
17,23 VGA_HDMI_DET
S
3
3
1
R339
1
1
1
CRT_DET
Q22
@
R413
100K_0402_5%
VGA@
D
2
G
24 CRT_DET#
E
@
R336
100K_0402_5%
@
1
D
+3VALW
2
+3VALW
C
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
26
of
54
A
B
C
D
E
U20B
AH10
AJ10
30 SATA_STX_DRX_P1
30 SATA_STX_DRX_N1
AG10
AF10
30 SATA_DTX_C_SRX_N1
30 SATA_DTX_C_SRX_P1
2
+1.1VS_SATA
R364
2
2
R365
1K_0402_1%
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%
+3VS
R367 1
SATA_RX1N
SATA_RX1P
SATA_TX2P
SATA_TX2N
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
AB14
AA14
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
SATA_TX1P
SATA_TX1N
AG12
AF12
AD11
35 SATA_LED#
SATA_RX0N
SATA_RX0P
FLASH
30 SATA_DTX_C_SRX_N0
30 SATA_DTX_C_SRX_P0
SATA_ACT#/GPIO67
12/07 remove SB sata Xtal(AMD)
T26 PAD
AD16
AC16
J5
E2
K4
K9
G2
SATA_X1
SATA_X2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AH28
AG28
AF26
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC1
NC2
1
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
SATA_CALRP
SATA_CALRN
2 10K_0402_5%
T25 PAD
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
Part 2 of 5
SERIAL ATA
ODD
AJ8
AH8
SB800
SATA_TX0P
SATA_TX0N
HW MONITOR
HDD
AH9
AJ9
30 SATA_STX_DRX_P0
30 SATA_STX_DRX_N0
SPI ROM
1
2
@ R366
1
2
0_0402_5%
EC_THERM# 34
Check SW:
Cinfigure to output or Internal PU/PD
A3
B4
A4
C5
A7
B7
B8
A8
MEM_1V5
G27
Y2
SB820M_FCBGA605
3
3
SB820 A12(SA00003IW10)
MEM_1V5 is for gating the
glitch on PCI_AD24
+3VS
C685
2
1
5
0.1U_0402_16V4Z
2
0_0402_5%
1
Y
A
1 @
R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
U22
Verify when PCBA back
(Pop R424 and remove PR160)
P
B
3
25,29 PCI_AD24
1
R422
2
4
G
MEM_1V5
1
R424
2
33_0402_5%
VDDR_SW 46
2
NC7SZ08P5X_NL_SC70-5
1
2
0_0402_5%
C686
150P_0402_50V8J
For VDDR Voltage Switch, AMD suggest
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB710 SATA/IDE/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
27
of
54
B
C
D
E
11/07 790mA
ĺ
U20E
+1.1VS_VDDC
510mA
POWER
43mA
AE28
+VDDPL_3V_PCIE
ĺ
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
C604
C605
C606
C607
1
1
1
1
2
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
600mA
11/07
690mA
2
+VDDPL_3V_SATA
2
2
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
check 220ohm bead
11/07
1350mA
11/07 534mA
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
+3VALW
C617
C618
C619
C620
C621
1
1
1
1
1
2
2
2
2
2
AD14
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
200mA
C11
D11
3
1
R372
1
R373
2
0_0402_5%
2
0_0402_5%
CORE S0
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
L7
L9
1
R374
2
0_0402_5%
2
2
2
2
1
1
1
1
C596
C594
C597
C598
VDDIO_GBE_S_1
VDDIO_GBE_S_2
M6
P8
1
R375
2
0_0402_5%
1
2
2
2
2
+1.1VS
2
C595
External Clock, connect to +1.1VS
directly, no need thick trace
1
1
1
1
C600
C601
C602
C603
check can be removed?
Pre MP 0409
Add LDO
+3VALW
U905
VIN 1
+VDDCR_USB
L122
2
1
5
FBMA-L11-160808-221LMT 0603
1U_0402_6.3V6K
2
1
2
VOUT
GND
C678
FB
3
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
VDDCR_11_S_1
VDDCR_11_S_2
VDDIO_AZ_S
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
VDDPL_33_SYS
VDDPL_11_SYS_S
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V6K
1 0.1U_0402_16V4Z
SB820M_FCBGA605
32mA
A21
D21
B21
K10
L10
J9
T6
T8
ĺ11/07
+3VALW
APL5317
49mA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
C608
C609
2
2
SB800
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
Y4
113mA
F26
G26
1 1U_0402_6.3V6K
1 1U_0402_6.3V6K
+VDDIO_AZ
ĺ
47mAĺ11/07 46mA
M21
+VDDPL_3V
11/07 65mA
ĺ+VDDPL_11V
16mA
ĺ11/07
+VDDPL_3V_USB
11/07 12mA
5mA
ĺ+3V_HWM
+VDDLX_3V
62mA
L22
C623
C624
2
2
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
17mA
F19
D6
+3VALW
197mA
L20
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
+1.1VALW
@
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
197mA 11/07 58mA+VDDCR_USB
A11
B11
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V6K
+VDDPL_3V
SB820M_FCBGA605
SB820 A12(SA00003IW10)
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
+VDDPL_3V_USB
L76
2
1
FBMA-L11-160808-221LMT 0603
L80
2
1
FBMA-L11-160808-221LMT 0603
0.1U_0402_16V4Z
2
2
1
C634
2.2U_0603_6.3V6K
+VDDPL_3V_SATA
2
+3VS
+3VALW
+3V_HWM
+3VALW
L77
2
1
FBMA-L11-160808-221LMT 0603
1
C628
1
3
+3VS
L79
1
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
Part 5 of 5
11/07 5mA
+VDDPL_11V
+3VS
2
M20
VSSPL_SYS
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
SB820 A12(SA00003IW10)
+VDDPL_3V_PCIE
1
VSSAN_HWM
M19
TBD
M8
EFUSE
D8
C615 2
C616 2
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
+1.1VALW
11/07 115mA
ĺ
C625 2
C626 2
PCI/GPIO I/O
658mA
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M10
C590
L69
2
1
FBMA-L11-201209-221LMA30T_0805
22U_0805_6.3V6M
V1
2
4
ĺ
1
1
1
1
1
382mA
ĺ11/10
+1.1VS_CKVDD
400mA
93mA
+1.1VS_SATA
L71
2
1
567mA
FBMA-L11-201209-221LMA30T_0805
C610
C611
C612
C613
C614
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+1.1VS
EN
ĺ
+1.1VS
ĺ
11/07 15mA
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
K28
K29
J28
K26
J21
J20
K21
J22
2
0_0805_5%
10U_0805_10V4Z
N13
R15
N17
U13
U17
V12
V18
W12
W18
ĺ
+1.1VS_PCIE
L70
VDDRF_GBE_S
VDDIO_33_GBE_S
3.3V_S5 I/O
11/07 11mA
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
CLKGEN I/O
AF22
AE25
AF24
AC22
2
0_0402_5%
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
CORE S5
ĺ
1
R371
GBE LAN
71mA
PLL
11/07 0.15mA
FLASH I/O
2
2
2
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
SERIAL ATA
1
1
1
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCI EXPRESS
2
ĺ
1
C591
C592
C593
C599
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
+3VS
1
1
R369
U20C
131mA
USB I/O
ĺ
11/07 78mA
GROUND
A
C635
2.2U_0603_6.3V6K
2
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
1
2
L78
2
1
FBMA-L11-160808-221LMT 0603
1
2
C632
C631
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
1
1
2
2
C633
2.2U_0603_6.3V6K
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
2
1
2
1
R376
4
2
0_0402_5%
1
C637
2.2U_0603_6.3V6K
2
C638
2.2U_0603_6.3V6K
For 3V AZ device
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB710 power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
28
of
54
A
B
C
REQUIRED STRAPS
PULL
HIGH
D
E
Check Internal PU/PD
AZ_SDOUT
PCI_CLK1
PCI_CLK2
LOW POWER
MODE
ALLOW PCIE
GEN2
WATCHDOG
TIMER
ENABLE
PCI_CLK3
PCI_CLK4
LPC_CLK0
LCP_CLK1
USE
DEBUG
STRAP
Inter CLK
Gen Mode
EC
ENABLE
CLOCKGEN
ENABLE
1
GPIO200
GPIO199
H,H = Reserved
Enable
H,L = SPI ROM
DEFAULT
1
DEFAULT
L,H = LPC ROM (Default L,NC)
+3VS
@
@
@
@
EC
DISABLE
CLOCKGEN
DISABLE
L,L = FWH ROM
Disable
DEFAULT
+3VS
+3VALW
+3VALW
+3VALW
@
+3VALW
R385
2.2K_0402_5%
2
1
+3VS
Inter CLK
Gen Mode
R384
10K_0402_5%
2
1
+3VS
R380
10K_0402_5%
2
1
DEFAULT
R379
10K_0402_5%
2
1
DEFAULT
R378
10K_0402_5%
2
1
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
IGNORE
DEBUG
STRAP
R383
10K_0402_5%
2
1
DEFAULT
WATCHDOG
TIMER
DISABLE
R382
10K_0402_5%
2
1
FORCE PCIE
GEN1
R381
10K_0402_5%
2
1
Performance
MODE
PULL
LOW
@
26 HDA_SDOUT
25 PCI_CLK1
25 PCI_CLK2
25 PCI_CLK3
25 PCI_CLK4
25,34 LPC_CLK0_EC
25 LPC_CLK1
26 GPIO200
26 GPIO199
R394
2.2K_0402_5%
2
1
R393
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
@
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
2
R386
10K_0402_5%
2
1
2
@
@
12/08 for Int. CLK Gen
R395
10K_0402_5%
2
1
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
PCI_AD23
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
25
25
25
25
25
25,27
25
3
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
@
check default
@
@
R401
2.2K_0402_5%
2
1
PCI_AD24
R400
2.2K_0402_5%
2
1
PCI_AD25
R399
2.2K_0402_5%
2
1
PCI_AD26
R398
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD27
R397
2.2K_0402_5%
2
1
3
+3VS
R396
10K_0402_5%
2
1
+3VS
@
@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB710 STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
29
of
54
A
B
C
D
E
F
G
H
SATA HDD Conn.
JHDD1
1
1
27 SATA_STX_DRX_P0
27 SATA_STX_DRX_N0
27 SATA_DTX_C_SRX_N0
27 SATA_DTX_C_SRX_P0
C656 1
C658 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
C657 1
C659 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+3VS
1
2
R405 1
+5VS
0.1U_0402_16V4Z
+5VS_HDD
2 0_0805_5%
10U_0805_10V4Z
OS
virtual BTN
1
C660
ODD_EJECT# Keep LOW
ODD power turn on
SATA PORT turn on
C661
2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
C639
0.1U_0402_16V4Z
1
1
C662
2
C663
2
1U_0402_6.3V6K
1
2
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
GND
GND
24
23
SANTA_192301-1
CONN@
1000P_0402_50V7K
Cap sense ODD_BOT# : LOW
2
2
OPEN ODD DOOR
CAP Sense
EJECT BTN
NO DISK
ODD_EJECT# SET HIGH
ODD power off
SATA PORT turn off
HAVE DISK
ODD_EJECT# SET LOW
ODD power still ON
SATA PORT turn on
SATA ODD Conn.
JODD1
SYSTEM determine
NO ACTION
27 SATA_STX_DRX_P1
27 SATA_STX_DRX_N1
C648 1
C649 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
27 SATA_DTX_C_SRX_N1
27 SATA_DTX_C_SRX_P1
C650 1
C651 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+5VS
R403 1
12/02 add ODD EJECT
DVT 0119 update R1054,Q80,Q81 PN
DVT 0131 update Q80,Q81 to SB570020410
C652
S
1
200K_0402_5%
1
2
SI3456BDV-T1-E3_TSOP6
C1246
0.1U_0402_16V4Z
DP
+5V
+5V
MD
GND
GND
GND
GND
3
15
14
0.1U_0402_16V4Z
1
C653
2
1
C654
1
C655
1
2
80mils
2
CONN@
2
11/30 update ODD conn.
1U_0402_6.3V6K
1000P_0402_50V7K
+5VS_ODD
ODD conn: SANTA_202801-1_13P-T
D
Place caps. near ODD CONN.
2
Q80
2
G
34 ODD_EJECT
8
9
10
11
12
13
3
4
+VSB
+5VSODD_GATE
2 1K_0402_1%
SANTA_202801-1
G
1
@
+5VS_ODD
2 0_0805_5%
D Q79
R1054
2
R404 1 @
10U_0805_10V4Z
1
2
5
6
3
+5VS
R1055
470_0603_5%
1 1
1
ODD_EJECT
D
3
3
S
2N7002-7-F_SOT23
S
Q81
2
G
R1109
2N7002-7-F_SOT23
4.7K_0402_5%
2
DVT 0125 add PD Res.
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDD & ODD Connector
Document Number
Date:
A
B
C
D
E
F
Rev
0.1
NELA5 LA-6141P
Wednesday, April 21, 2010
G
Sheet
30
H
of
54
5
4
3
Card Reader Connector
2
1
RTS5138
Card Reader Connector
+3VS
D
+3VS_CR
D
JREAD1
XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7
33
32
34
39
38
37
36
35
XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE
31
40
41
42
11
18
SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP
9
4
3
21
19
16
1
2
SD6-VSS
SD3-VSS
6
13
SD CD/WP GND
SD CD/WP GND
R1043
2 0_0805_5%
1
30mil
XDD0_SDCLK_MSD2
XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2
XDD4_SDD3_MSD1
XDD2_SDCMD
XDWE#_SDCD#
XDDRY_SDWP_MSCLK
@
1
R1042
+3VS
5IN1_LED#
2
10K_0402_5%
12/15 UPDATE
12/02 add net CLK_SD_48M_R
C1237
2
12mil
1 100P_0402_50V8J
U903
R1044
1
RREF
1
REFE
2
3
DM
DP
+3VS_CR
+CARDPWR
VREG
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
7
XD_CD#
2
6.2K_0603_1%
26 USB20_N6
26 USB20_P6
XDDRY_SDWP_MSCLK
XDD1_MSD0
XDD4_SDD3_MSD1
XDD0_SDCLK_MSD2
XDALE_MSD3
XDRE#_MSINS#
XDD6_MSBS
17
10
8
12
15
14
7
5
20
MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS
XD GND
XD GND
+XDPWR_SDPWR_MSPWR
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1
C1239
2
30mil
2
C1240
1
10mil
C1238
1 1U_0402_6.3V6K
2
T-SOL_144-1300302600_NR
CONN@
XDDRY_SDWP_MSCLK
XDRE#_MSINS#
XDCE#_SDD1
XDCLE_SDD0
XDALE_MSD3
8
9
10
11
12
SP1
SP2
SP3
SP4
SP5
25
C
5IN1_LED#
GPIO0
17
CLK_IN
24
XD_D7
23
XD_D7
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
XDD6_MSBS
XDD5_SDD2
XDD4_SDD3_MSD1
XDD3
XDD2_SDCMD
XDD1_MSD0
XDD0_SDCLK_MSD2
XDWP#
XDWE#_SDCD#
CLK_SD_48M_R
5IN1_LED#
2 R1045 1
0_0402_5%
35
CLK_SD_48M
25
CLK_SD_48M_R
1
XDWE#_SDCD#
XDWP#
XDALE_MSD3
XD_CD#
XDDRY_SDWP_MSCLK
XDRE#_MSINS#
XDCE#_SDD1
XDCLE_SDD0
30
29
28
27
26
25
24
23
SD4-VDD
MS9-VCC
R1086
10_0402_5%
@
RTS5138-GR_QFN24_4X4
C
2
XDD0_SDCLK_MSD2
XDD1_MSD0
XDD2_SDCMD
XDD3
XDD4_SDD3_MSD1
XDD5_SDD2
XDD6_MSBS
XD_D7
XD-VCC
EPAD
22
+XDPWR_SDPWR_MSPWR
1
C1252
10P_0402_50V8J
2 @
12/14 C1241 close to JREAD1.11
C1242 close to JREAD1.18
12/14 add close to JREAD1.22
+XDPWR_SDPWR_MSPWR
+CARDPWR
+XDPWR_SDPWR_MSPWR
C1241
2
0_0805_5%
12/15 for EMI request
30mil
1
C1242
2
@
1
R1047
100K_0402_5%
1
2
1
R1046
2
C1251
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
30mil
2
C1243
0.1U_0402_16V4Z
Share Pin
EMI reserve
C6, C7 close to connector
XDDRY_SDWP_MSCLK
B
C1244
2
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
12/15 update for EMI
close to JREAD1.17
R1048
1 2
1
@
@
0_0402_5%
10P_0402_50V8J
XDD0_SDCLK_MSD2
C1245
2
12/15 update for EMI
close to JREAD1.9
XD
XD_CD#
XD_RDY
XD_RE#
XD_CE#
XD_CLE
XD_ALE
XD_WE#
XD_WP
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
SD
SD_WP
MS
MS_CLK
MS_INS#
SD_D1
SD_D0
MS_D3
B
SD_CD#
SD_CLK
MS_D2
MS_D0
SD_CMD
SD_D3
SD_D2
MS_D1
MS_BS
R1049
1 2
1
@
@
0_0402_5%
10P_0402_50V8J
A
A
Compal Secret Data
Security Classification
Issued Date
2007/08/28
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
USB CardReader&CONN
Size Document Number
Custom
Date:
Rev
1.0
NELA5 LA-6141P
Wednesday, April 21, 2010
Sheet
1
31
of
54
A
B
C
D
E
1
1
Mini-Express Card for WLAN
+3VS
Mini Card Power Rating
+1.5VS
Power
1
2
1
C705
4.7U_0805_10V4Z
2
1
C706
0.1U_0402_16V4Z
2
1
C707
0.1U_0402_16V4Z
2
1
C708
4.7U_0805_10V4Z
2
1
C709
0.1U_0402_16V4Z
2
Primary Power (mA)
0.1U_0402_16V4Z
Auxiliary Power (mA)
Normal
Peak
Normal
+3VS
1000
750
+3V
330
250
250 (wake enable)
+1.5VS
500
375
5 (Not wake enable)
C710
JMINI1
26,33 SB_PCIE_WAKE#
SB_PCIE_WAKE#
R440 1
@
2 0_0402_5%
25 MINI1_CLKREQ#
25 CLK_PCIE_MINI1#
25 CLK_PCIE_MINI1
12 PCIE_PTX_C_IRX_N1
12 PCIE_PTX_C_IRX_P1
2
12 PCIE_ITX_C_PRX_N1
12 PCIE_ITX_C_PRX_P1
3VS_MINI
E51TXD_P80DATA_R
E51RXD_P80CLK
53
1
34 E51TXD_P80DATA
34 E51RXD_P80CLK
0_0402_5%
R445 1
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND1
GND2
1
R1129
2
0_0603_5%
+3VS
PVT 20100310 Add Res.
PVT 20100312 connect to pin39,41
+1.5VS
WL_OFF#
PLT_RST#
+3V_WLAN
1
R441 1
R442
@
MINI1_SMBCLK
@
1
MINI1_SMBDAT R443
@
1
R444
2
2 0_0603_5%
0_0603_5%
2
0_0603_5%
2
0_0603_5%
WL_OFF# 34
PLT_RST# 16,25,33
+3VS
+3VALW
2
SB_SMDAT0 10,11,26
SB_SMCLK0 10,11,26
USB20_N8 26
USB20_P8 26
(MINI1_LED#) WIMAX_LED#
2
WLAN_LED#
1
MINI1_LED#
MINI1_LED# 35
3
CHP202UPT_SOT323-3
D47
(9~16mA)
54
11/09 FOR WiMax/Wlan LED request
ACES_88913-5204
CONN@
2
R1113
100K_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
3VS_MINI
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
HAT00_MINI
SP01000I200
ACES_88913-5204_52P
DVT 0126 add PD Res(For EC)
11/28 update MINI conn.
11/30 update MINI footprint
3
3
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
MINI CARD (WLAN) / FP / Ext USB
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
32
of
54
A
B
C
D
E
12/02 update C711 capa.
+USB_VCCA
12/02 change USB pwr sw
+USB_VCCA
C713
1
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
R447 1
2 10K_0402_5%
USB_OC#0 26
RT9715BGS_SO8
+USB_VCCA
1
+
C712
2
1
4.7U_0805_10V4Z
2
C714
0.1U_0402_16V4Z
1
11/28 check conn. OK
(same as NAL00)
L83
2
40 SYSON#
2
470P_0402_50V7K
2
@ 0_0402_5%
R448
1
1
C711
W=80mils
1
1
2
3
4
R446
100K_0402_5%
80mil
2
U24
SVPE, 4.4m, 17mohm
1
+5VALW
150U_B2_6.3VM_R35M
+3VALW
USB20_N0
26 USB20_N0
USB20_P0
26 USB20_P0
1
JUSB1
1
4
2
2
4
1
2
3
4
5
6
7
8
USB20_N0_R
USB20_P0_R
3
3
WCM2012F2S-900T04_0805
1
2
@ 0_0402_5%
R451
To USB/B Connector
1
2
3
4
GND
GND
GND
GND
SUYIN_020133MB004S580ZL-C
CONN@
NAL00-USB
11/05 remove Card Reader/B,3G/B,3G power,JUSB2 power switch(it will be build on JUSB2/B) ,
change JUSB2 conn. for NELA1 , add SB USB20_P/N3 for External USB port
D10
+USB_VCCA
6
CH3
5
Vp
CH2
3
Vn
2
CH1
1
USB20_N0_R
+5VALW
JUSB2
USB20_P0_R
2
17
18
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
CH4
2
CM1293-04SO_SOT23-6
12/02 reverse USB signal
DVT 0131 change D10 to SC300000B00
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N1 26
USB20_P1 26
USB20_N2 26
USB20_P2 26
USB20_N3 26
USB20_P3 26
SYSON#
Bluetooth Conn.
ACES_85201-1605N
CONN@
+3VALW
+3VS
DVT 0121 update Q24 to SB934130020
1
C718
+3VALW
+BT_VCC
R1036 1
R1037 1
CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25
PCIE_PTX_C_IRX_P0 12
PCIE_PTX_C_IRX_N0 12
1
2
C1268
0.1U_0402_16V4Z
C1269
2 0_0402_5%
2 0_0402_5%
CLK_48M_LAN 26
LAN_CLKREQ# 26
EC_PME# 34
SB_PCIE_WAKE# 26,32
R1002 1
@
2
0_0402_5%
PLT_RST# 16,25,32
ACES_88460-1601
CONN@
4
@
1
2
1
2
C722
5
6
1
2
GND 3
GND 4
BT@
R454
300_0603_5%
3
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
JBT1
1
2
3
4
USB20_P14 26
USB20_N14 26
D
S
2
G
ACES_87213-0400G
CONN@
C1270
BT@
1
BT@
2
CLK_48M_LAN_R
PCIE_ITX_C_PRX_N0 12
PCIE_ITX_C_PRX_P0 12
+BT_VCC
1
1
G2
G1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.1U_0402_16V4Z
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AO3413_SOT23-3
W=40mils
BT@
0.1U_0402_16V4Z
C721
0.1U_0402_16V4Z
JLAN1
1U_0402_6.3V6K
3
C720
DVT 0119 update BT conn.
2
BT@
C719
3
12/01 update conn. footprint
12/02 add net name on JLAN1.13 (CLK_48M_LAN_R)
12/15 swap net
PVT 20100310 add Cap. for EMI request
BT@
Q24
2
1
11/20 update pin Def.
G
LAN CONN. 11/12 add Lan conn.
BT@ 2
1
R453
10K_0402_5%
34 BT_ON#
D
3
S
BT@
0.1U_0402_16V4Z
BT@
Q25
2N7002-7-F_SOT23
@
DVT 0131 change Q25 to SB570020410
4
CONFIRM LAN CON.
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
BlueTooth / Int USB x2 /eSATA
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
33
of
54
5
4
3
2
1
For EC Tools
+3VALW
L84
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1 C725
1
C724
C726
KSO[0..17]
2
2
0.1U_0402_16V4Z
KSO[0..17] 35
KSI[0..7]
KSI[0..7]
C727
2
2
0.1U_0402_16V4Z
C728
1000P_0402_50V7K
1
1
+3VALW
1
2+EC_VCCA
BLM18AG601SN1D_2P
1
2
35
0.1U_0402_16V4Z
E51RXD_P80CLK
E51TXD_P80DATA
ACES_85205-0400
@
67
9
22
33
96
111
125
65W /90W #
2
AVCC
2
R459
EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW #
1
100K_0402_5%
EC_PME#
2
10K_0402_5%
ENBKL
1
100K_0402_5%
R1137
@
1
1
R1138
@
+3VS
11/20 For AL8131L
2 2.2K_0402_5%
2
2.2K_0402_5%
Pre MP for EMI request
change to SM01000CP00
EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
42 EC_SMB_CK1
15P_0402_50V8J
2.2K_0402_5%
42 EC_SMB_DA1
2 EC_ESB_CK_R 2
1
8,17 EC_SMB_CK2
4.7K_0402_5%
C1181
8,17 EC_SMB_DA2
11/06 for cap sensor
2 EC_ESB_DA_R
4.7K_0402_5%
2 EC_ESB_INT
2.2K_0402_5%
26 PM_SLP_S3#
2 SATA_IS1#
26 PM_SLP_S5#
4.7K_0402_5%
26 EC_SMI#
12/02 for odd eject
26 SATA_IS1#
R960 2
FBMA-11-100505-801T 0402
1
35 EC_ESB_CK
R961 2
FBMA-11-100505-801T
0402
1
35 EC_ESB_DA
22 COLOR_ENG_EN
22 EC_INVT_PW M
For Panel INV_PWM high
39 FAN_SPEED1
resolution request
33 BT_ON#
1
R467
1
R468
1
R957
1
R958
1
R959
1
R1056
+5VS
TP_CLK
2
4.7K_0402_5%
TP_DATA
2
4.7K_0402_5%
2
R1082
2
R1083
LOCAL_DIM
1
100K_0402_5%
COLOR_ENG_EN
1
100K_0402_5%
36 ON/OFF
35 TP_PW M
30 ODD_EJECT
EC_CRY1
EC_CRY2
12/02 add ODD_EJECT
12/10 for low PWR panel
+3VALW
5
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
OSC
NC
4
OSC
X1
83
84
85
86
87
88
EC_MUTE#
LOCAL_DIM
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
3S/4S#
65W /90W #
VLDT_EN
LID_SW #
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SPICLK_L
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_ACIN
EC_ESB_INT
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SW I#
EC_PW ROK
BKOFF#
W L_OFF#
KB926_ID
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#
V18R
124
1
C740
15P_0402_50V8J
32.768KHZ_12.5PF_Q13MC14610002
2
R1084 @
1
R1085
EC Version control
4
VGA_PW R_ON 36,40,48,49
+3VALW
DVT 0125
reserve Res.
R463
@
100K_0402_5%
Ra
12/01 remove EN_DFAN1
1
IREF 44
CALIBRATE# 44
AD_PID0
2
IREF
CALIBRATE#
11/06 add GPIO for Power save function
EC_MUTE# 37
LOCAL_DIM 22
PW R_SUSP_LED
TP_CLK
TP_DATA
C734
C
100K_0402_5%
PW R_SUSP_LED 35
TP_CLK 35
TP_DATA 35
3S/4S# 44
65W /90W # 44
VLDT_EN 40,46
LID_SW # 35
1
R464
Rb
PW R_SAVE_LED# 35
SPI Device Interface
SPI Flash ROM
GPIO
SM Bus
GPI
XCLK1
XCLK0
High : D3
Low : E0
1 VGA_PW R_ON
0_0402_5%
Analog Project ID definition
PVT 2010 add net for PWM
2
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
PS2 Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
12/10 add EC id
DVT 0131 update EC version
1
100K_0402_5%
KB926_ID
2
100K_0402_5%
3
2
1
NC
1
2
C739
122
123
68
70
71
72
DA Output
EC_CRY2
2
15P_0402_50V8J
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
BATT_TEMP 42
BUS_SEL# 22,24
ADP_I 44
PVT 20100309 add net for PWM
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
12/03 add TP_PWM
EC_CRY1
A
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
SATA_IS1#
EC_ESB_CK_R
EC_ESB_DA_R
COLOR_ENG_EN
EC_INVT_PW M
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
TP_PW M
ODD_EJECT
77
78
79
80
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
GND
GND
GND
GND
GND
1
R465
1
R466
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
AD
ECAGND
2
1
C731 0.01U_0402_16V7K
1
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
BATT_TEMP
BUS_SEL#
ADP_I
AD_BID0
AD_PID0
2
R1110 VGA@
1
R460
12/01 add FANPWM for FAN
2
0.1U_0402_16V4Z
Analog Board ID definition
12/08 move PWR_SUSP_LED
+3VALW
2
2
1
R462
47K_0402_5%
2
1
C733
0.1U_0402_16V4Z
+3VALW
1
R471
1
R472
1
R473
1
R474
2
R475
1
R476
2
R488
+3VALW
B
26 EC_SCI#
63
64
65
66
75
76
11
24
35
94
113
C
1
470P_0402_50V7K
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
PWM Output
VGA_DBCLK 17
BEEP# 37
FANPW M 39
ACOFF 44,47
KB926QFE0_LQFP128_14X14
EC_SI_SPI_SO 35
EC_SO_SPI_SI 35
EC_SPICS#/FSEL#
R469
35
EC_ACIN 17
EC_ESB_INT 35
FSTCHG 44
BATT_BLUE_LED# 35
INT_VGAPW R_ON 36
BATT_AMB_LED# 35
PW R_LED 35
SYSON 40,45
VR_ON 50
ACIN 17,41
BATT_BLUE_LED#
INT_VGAPW R_ON
BATT_AMB_LED#
PW R_LED
SYSON
VR_ON
ACIN
BKOFF# 22
W L_OFF# 32
2
Ra
11/30 add net for LVDS
12/10 update net name
DVT 0125 update Board ID
Pre MP 0406 update Board ID
100K_0402_5%
AD_BID0
1
R470
Rb
56K_0402_5%
11/30 add INT_VGAPWR_ON net
2
C735
0.1U_0402_16V4Z
B
11/20 add EC_ESB_RST
EC_RSMRST# 26
EC_LID_OUT# 26 to cap. sensor
12/12 REMOVE VGA_ON
EC_ON 36
EC_SW I# 26
EC_SPICLK 35
EC_SPICLK_L 1
R419
2
0_0402_5%
@
C783 33P_0402_50V8K
Reserve for EMI, close to EC
12/10 add EC ID
EC_ESB_RST 35
1
11/10 Remove WWAN_OFF#
12/08 add EC_ACIN
different to NEW75
1
2
C1262
@
DVT 0121
+3VALW
reserve Cap.(EMI request)
close to EC
A_RST#
12
13
37
EC_SCI#
20
38
1
2
@ R428
10K_0402_5%
VGA_DBCLK
BEEP#
FANPW M
ACOFF
1
LPC_CLK0_EC
25,29 LPC_CLK0_EC
13,15,25 A_RST#
21
23
26
27
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
2
1
33_0402_5%
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
AGND
@
2
R461
1
2
3
4
5
7
8
10
69
C732
@ 22P_0402_50V8J
2
1
EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
D
1
100K_0402_5%
1
100K_0402_5%
2
4.7K_0402_5%
R458
VR_ON
12/07 add VGA_DBCLK
3S/4S#
26 EC_GA20
26 EC_KBRST#
25 SERIRQ
25 LPC_FRAME#
25 LPC_AD3
25 LPC_AD2
25 LPC_AD1
25 LPC_AD0
E51RXD_P80CLK 32
E51TXD_P80DATA 32
+3VALW
VCC
VCC
VCC
VCC
VCC
VCC
U26
2
1
2
3
4
1
2
3
4
C730
D
Place on MiniCard door
JP7
C729
1000P_0402_50V7K
ECAGND
1
Delay SUSP# 10ms
VGATE 50
ENBKL 13,22
EAPD 37
EC_THERM# 27
SUSP# 40,44,48
PBTN_OUT# 26
EC_PME# 33
EC_PW ROK 1
R254
2
0_0402_5%
SB_PW RGD 8,13,26
C736
4.7U_0805_10V4Z
BATT_TEMP
C737
2
100P_0402_50V8J
1
ACIN
C741
2
100P_0402_50V8J
1
11/26 remove BATT_OVP for PWR request
20mil
ECAGND 2
L85
1
BLM18AG601SN1D_2P
A
KB926 Rev:E0(SA00001J5A0)
DVT 0131 update EC to E0
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Issued Date
Deciphered Date
2010/03/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
EC ENE KB926
Size
B
Date:
Document Number
Rev
0.1
NELA5 LA-6141P
W ednesday, April 21, 2010
Sheet
1
34
of
54
11/28 update JTP1 Conn.
(change to KALH0 6p conn.)
11/30 update pcb footprint
DVT 0125 Resever JTP1
PVT 0310 Resever JTP1
C742 1
2
0_0603_5%
2 0.1U_0402_16V4Z
+SPI_VCC
U27
34 EC_SPICS#/FSEL#
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#
R480 1
R482 1
+3VALW
1
3
7
4
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R
R481 1
R483 1
R484 1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
EC_SPICLK 34
EC_SO_SPI_SI 34
EC_SI_SPI_SO 34
ACES_85201-0605N_6P
KALH0_TP
SP01000LB00
+3VS
+5VS
6
5
4
3
2
1
C1247
C745
0.1U_0402_16V4Z
0.1U_0402_16V4Z
TP_CLK 34
TP_DATA 34
TP_PWM 34
ACES_85201-0605N
CONN@
1
MX25L1605DM2I-12G SOP 8P
SA00002TO00
1
C1248
@
C1249
@
2
2
100P_0402_50V8J 100P_0402_50V8J
1
2
TP_CLK
C1271
2.2U_0603_6.3V6K
@
TP_DATA
U28 @
CE#
WP#
HOLD#
VSS
VDD
SCK
SI
SO
+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R
8
6
5
2
D13
@
PVT 20100310 add Cap.
MX25L1005AMC-12G_SOP8
PJDLC05C_SOT23-3
@
R485
12/03 update TP schematic,JTP1 same as NELA0
1
0_0402_5%
1
1
3
7
4
2
EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#
2
1
R479
GND
GND
6
5
4
3
2
1
3
+3VALW
+5VS +3VS
JTP1
8
7
@
C746
33P_0402_50V8K
+3VS
12/03 add led for project id
KSO0
KSI1
LED5
PWR SAVE BTN
MEDIA_LED#
KSI[0..7]
KSI2
KSI[0..7] 34
KSO[0..17]
WLAN BTN
21
B
2
R1058 300_0402_5%
HT-110NB5_BLUE
3
12/07 invert
KB pin
1
KSO[0..17] 34
KSI3
JKB1
KSI4
1
2
3
4
5
6
7
8
9
10
11
12
+3VS
PWR_SAVE_LED#
MINI1_LED#
KSO0
KSI1
KSI2
ACES_85201-1205
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
PWR_SAVE_LED# 34
MINI1_LED# 32
JALA0-I/O 12P
+3VALW
PWR_LED#
PWR_SUSP_LED#
ON/OFFBTN#
LID_SW#
MEDIA_LED#
2
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
0_0402_5%
EC_ESB_RST 34
EC_ESB_CK 34
EC_ESB_DA 34
EC_ESB_INT 34
ACES_85201-1205
Conn. CONN@
+3VALW
11/28 update JLED1/JBTN1
(change to JALA0 12p conn.)
12/03 update net for project id
A
Y
1
100K_0402_5%
U29
2
B
5IN1_LED# 31
1
SATA_LED# 27
NC7SZ08P5X_NL_SC70-5
LED1
2
1
R477
3
1
R478
BATT_BLUE_LED#
2
100_0402_5%
BATT_BLUE_LED# 34
1
BATT_AMB_LED#
2
300_0402_5%
BATT_AMB_LED# 34
HT-210UD5/NB5 1206 AMBER/BLUE
(Left)
LED2
100P_0402_50V8J
C750 1
2
100P_0402_50V8J
KSO14
C751 1
2
100P_0402_50V8J
KSO6
C752 1
2
100P_0402_50V8J
KSO13
C753 1
2
100P_0402_50V8J
KSO5
C754 1
2
100P_0402_50V8J
KSO12
C755 1
2
100P_0402_50V8J
KSO4
C756 1
2
100P_0402_50V8J
KSI0
C757 1
2
100P_0402_50V8J
KSO3
C758 1
2
100P_0402_50V8J
KSO11
C759 1
2
100P_0402_50V8J
KSI4
C760 1
2
100P_0402_50V8J
KSO10
C761 1
2
100P_0402_50V8J
KSO2
C762 1
2
100P_0402_50V8J
KSI1
C763 1
2
100P_0402_50V8J
KSO1
C764 1
2
100P_0402_50V8J
KSI2
C765 1
2
100P_0402_50V8J
KSO0
C766 1
2
100P_0402_50V8J
KSO9
C767 1
2
100P_0402_50V8J
KSI5
C768 1
2
100P_0402_50V8J
KSI3
C769 1
2
100P_0402_50V8J
KSI6
C770 1
2
100P_0402_50V8J
KSO8
C771 1
2
100P_0402_50V8J
KSI7
C772 1
2
100P_0402_50V8J
PWR_LED#
2
1
R499
3
1
R498
6
KSO7
+3VALW
DMN66D0LDW-7_SOT363-6
Q26A
2
34 PWR_LED
R487
100K_0402_5%
BATT_BLUE_LED#
2
100_0402_5%
DVT 0126 update LED part
DVT 0131 update Blue LED
resistor to 100 Ohm
1
1
100P_0402_50V8J
2
100P_0402_50V8J
2
BATT_AMB_LED#
2
300_0402_5%
HT-210UD5/NB5 1206 AMBER/BLUE
LED3
1
2
C749 1
+3VALW
2
1
R1115
UD
KSO17 C748 1
KSO15
11/05 check PWR/B and MB side led qty
12/11 update LED (follow LED SPEC)
NB
3
1
R1116
BATT_BLUE_LED#
2
100_0402_5%
1
BATT_AMB_LED#
2
300_0402_5%
PWR_SUSP_LED#
3
HT-210UD5/NB5 1206 AMBER/BLUE
LED4
5
2
1
R1117
3
1
R1118
4
2
34 PWR_SUSP_LED
UD
DMN66D0LDW-7_SOT363-6
Q26B
NB
2
UD
KSO16 C747 1
NB
R490
100K_0402_5%
+3VALW
1
ACES_88747-2601
CONN@
4
ON/OFFBTN# 36
LID_SW# 34
+3VS
1
R1038 1
R1039 1
R1040 1
R1041
2
R486
5
JBTN1
11/20 update conn. def.
(ODD_LED#/EC_ESB_RST)
P
JLED1
PWR/B RIGHT
+3VS
G
LED/B LEFT
+3VS
11/05 add JLED1/JBTN1 for NELA1
remove JLED1 conn. pin4(Danube w/o 3G)
3
(Right)
UD
G1
G2
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NB
27
28
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
BATT_BLUE_LED#
2
100_0402_5%
1
BATT_AMB_LED#
2
300_0402_5%
HT-210UD5/NB5 1206 AMBER/BLUE
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
BIOS, I/O Port & K/B Connector
Document Number
Rev
0.1
NELA5 LA-6141P
Wednesday, April 21, 2010
Sheet
35
of
54
A
B
ON/OFF switch
C
D
Power Button
E
PX MODE SELECT CONTROL
+3VALW
7236LGH
+3VS
R500
DVT 0131 change Q70 to SB570020410
6
D12
CHN202UPT_SC70-3
Q70
@
S 2N7002-7-F_SOT23
2
G
C773
2
Q73A
@
2
25 PX_EN#
1000P_0402_50V7K
1
EN1
3
51ON# 41
1
EC_ON
D
3
1
DMN66D0LDW-7_SOT363-6
S 2N7002-7-F_SOT23
1
4
DMN66D0LDW-7_SOT363-6
Q75A @
3
DMN66D0LDW-7_SOT363-6
Q75B
@
Q27
2
G
2
34 EC_ON
6
13,22 GMCH_LCD_DATA
PE_GPIO2 22
Pop for PX verify
EN1#
Q73B
@
5
DMN66D0LDW-7_SOT363-6
12/14 update
Q74A
@
Q74B @
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
6
1
4
3
5
EN1
3
13 AUX0N
D
5
EN1#
2
1
Pre MP unstuff
1
PVT 20100310 Remove SW3
100K_0402_5%
@
ON/OFF 34
2
1
100K_0402_5%
@
DVT 0131 change D12 to SC1N202U010
2
4
35 ON/OFFBTN#
1
25 INT_VGA_EN#
R502
100K_0402_5%
%RWWRP6LGH
ON/OFFBTN#
2
R495
1
2
@ 10K_0603_5%
1
MUX@
CH751H-40PT_SOD323-2
2
D46
1
1
R494
INT_VGA_EN# keeps HIGH if PX is enable
3
2
@ 10K_0603_5%
2
1
R493
DVT 0121 update D46 to SC1H751H010
DVT 0131 Q74,Q75 with @
+3VS
2
1
AUX0N
R496
@
1
R514
PE_GPIO2
2
0_0402_5%
Verify only
DVT 0131 change Q27 to SB570020410
1
10K_0402_5%
2
PX_EN#
VGA Power ON Circuit
14
U30A
SN74LVC14APWLE_TSSOP14
2
O
3
I
VGA@
6
I
VGA@
1
O
8
X
1
VGA( LVDS,EDP,CRT,DP)
PX (MUXED)
0
0/1
0/1
1
PX (MUXLESS)
0
X
X
0
VGA/IGP(CRT, LVDS, EDP); MXM(DP)
IGP( LVDS,EDP,CRT,DP)
VGA_PWR_ON_L
VGA@
2
For PX sequence, >1mS delay is required between
PE_GPIO1 and VGA_PWR_ON
R509
0_0402_5%
1
14
U30F
SN74LVC14APWLE_TSSOP14
10
13
I
O
12
G
O
VGA@
7
7
2
C778
X
PE_GPIO1
For VGA Power on control
>1ms
P
14
I
1
2 0.1U_0402_16V4Z
U30E
SN74LVC14APWLE_TSSOP14
P
2
11
VGA only mode
U30D
SN74LVC14APWLE_TSSOP14
VGA@
G
25 PE_GPIO1
IGP( LVDS,EDP,VGA,DP)
3
+3VALW
1
R415
31.6K_0402_1%
@
0
4
@
+3VALW
C776
R414 VGA@
10K_0402_1%
1
2
X
VGA@
GPIO1_DELAY
+3VS
X
G
O
9
G
I
1
P
14
U30C
SN74LVC14APWLE_TSSOP14
7
@
5
7
34 INT_VGAPWR_ON
2
0_0402_5%
2
C775
@
0.1U_0402_16V4Z
1
IGP only mode
+3VALW
P
14
+3VALW
1
R501
U30B
SN74LVC14APWLE_TSSOP14
O
7
7
3
2
DISPLAY OUTPUT
G
I
G
1
INT_VGA_EN#
+3VALW
P
12/14 remove
I2C_DATA
EDP_ENABLED
P
14
+3VALW
AUX0N
EDP_DISABLED
12/14 remove MOS
0.1U_0402_16V4Z
1
VGA@
1
R505
VGA@2
0_0402_5%
Pop for PX verify
VGA_PWR_ON 34,40,48,49
2
1
VGA_PWR_ON
C777
0.1U_0402_16V4Z
@
4
1
4
D
VGA@
3
GPIO1_DELAY 2
G
@
Q71
S
2N7002-7-F_SOT23
12/08 for VGA SEQ.
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
DVT 0125 unstuff Q71
DVT 0131 change Q71 to SB570020410
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
PBTN / VGA SEQUENCE
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
36
of
54
5
4
3
2
1
+5VS_AVDD
1
12/15 update
Pre MP 0410 stuff D48,R1004
R1003
10K_0402_5%
1
D48
CH751H-40PT_SOD323-2
1
1
1
2
+3VS
R1004
10K_0402_5%
1
+3VS
20mil
+3VS_DVDD
1
1
0.1U_0402_16V4Z
C1202
C1203
0.1U_0402_16V4Z
C1204
10U_0805_10V4Z
2
2
2
1U_0603_10V6K
C1198
+FILT_1.65V
C1201
+3VS_LDO_OUT
1
C1200 1
26 SB_SPKR
1
1
C1205
1
C1206
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
10U_0805_10V4Z
2
2
C1207
C
2
2
B
2
1
R1008
1
R1007
2
30K_0402_1%
2SC2411K_SOT23-3
DVT 0122 update R1007 to 30k
2
560_0402_5%
1U_0402_6.3V6K
Q76
E
560_0402_5%
1U_0402_6.3V6K
10mil
R1006
D49
CH751H-40PT_SOD323-2
2
1
10mil
1
3
0_0603_5%
2
2
1
34 BEEP#
12/15 update
R1093
C1199 1
D
MONO_IN
2
1U_0402_6.3V6K
1
1
12/15 change Bead to 0Ohm
2
AVDD_3.3 pin is output of
internal LDO. Do NOT connect
to external supply.
2
2
D
2
1U_0402_6.3V6K
C1197
R1005
10K_0402_5%
DVT 0125 update
10mil
+3VS_AUX
2
0_0402_5%
C1208
0.1U_0402_16V4Z
1
1
2
2
Layout Note: Path from +5V to LPWR_5.0 and
RPWR_5.0 must be very low resistance ( <0.01 ohms).
Place bypass caps very close to device.
C1209
10U_0805_10V4Z
80mil
1
10mil
+3VS_DVDD
R1010
C
10mil
12/15 update schematic
C1215
10U_0805_10V4Z
2
U902
if supply to VAUX_3.3 is
removed during system re-start.
26 HDA_RST_AUDIO#
9
26 HDA_BITCLK_AUDIO
26 HDA_SYNC_AUDIO
26 HDA_SDIN0
26 HDA_SDOUT_AUDIO
5
8
6
4
1
R1012
2
33_0402_5%
MONO_IN
1
R1014
38 SPDIF
34 EAPD
EAPD active low
0=power down ex AMP 34 EC_MUTE#
1=power up ex AMP
Pre MP 0409
R1015
1
1
R1013
2
R1144
@
10
PC_BEEP
39
SPDIF
20_0402_5%
EC_MUTE#_R
2
0_0402_5%
1
10K_0402_5%
38
37
GPIO0/EAPD#
GPIO1/SPK_MUTE#
40
1
1
R1017
2
0_0805_5%
SENSE_A
36
PORTB_R
PORTB_L
B_BIAS
35
34
33
C_BIAS
PORTC_R
PORTC_L
32
31
30
+5VS
C
1
R1095
2
0_0603_5%
12/15 update
1
1
1
C1217
C1218
C1219
0.1U_0402_16V4Z
+CLASSD_REF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
40mil
SENSE_A
C1220
2
1
2
C1221
10U_0805_10V4Z
Port
Port
Port
Port
Port
Port
Port
10mil
PORTA_R
PORTA_L
23
22
NC
NC
24
25
AVEE
FLY_P
FLY_N
21
19
20
LEFT+
LEFTRIGHT+
RIGHT-
+MIC_BIASC
MIC_R 38
MIC_L 38
MIC JACK
HP_RIGHT 38
HP_LEFT 38
@
1
R1114
+AVEE
2
100_0603_1%
B
Headphone
DVT 0126 reserve
10mil
1
1
C1227
2
1U_0402_6.3V6K
C1225
1
+3VS_AUX
C1226
0.1U_0402_16V4Z
10U_0805_10V4Z
2
2
12/15 update
HDA_BITCLK_AUDIO
0.1U_0402_16V4Z
2
C1275
1
0.1U_0402_16V4Z
2
C1276
1
0.1U_0402_16V4Z
2
C1277
1
0.1U_0402_16V4Z
2
C1278
0.1U_0402_16V4Z
R1087
10_0402_5%
@
SENSE_A
MIC_PLUG# 38
1
R1023 10K_0402_5%
2
C1253
22P_0402_50V8J
A
12/15 FOR EMI request
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/11/23
Issued Date
GNDA
Deciphered Date
2010/11/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
2
HP_PLUG# 38
1
@
GND
R1021
2
1
39.2K_0402_1%
1
C1274
1
1202 update Audio footprint
2
A
0.1U_0402_16V4Z
2
Sense resistors must be
connected same power
that is used for VAUX_3.3
R1018
5.11K_0402_1%
CX20672-11Z_QFN40_6X6
2
C1273
1
Configuration
A: Headphone jack (jack shared with S/PDIF)
B: Internal analog mono mic (stereo option)
C: Microphone jack
G: Internal stereo speakers
J: Optional Internal stereo digital mic
H: S/PDIF (jack shared with headphone)
2
1
16
14
38 SPKR+
38 SPKR-
12
15
17
GND
2
0_0805_5%
11
13
38 SPKL+
38 SPKL-
LPWR_5.0
RPWR_5.0
CLASS-D_REF
0_0603_5%
2
+CLASSD_5V
1
DMIC_CLK
DMIC_1/2
41
1
R1107
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
2
0_0402_5%
38 DMIC_CLK
38 DMIC_DATA
DVT 0121 add Res./Short pad (for EMI)
PVT for EMI request, Remove J1,J2,J3
,R1019,R1020,R1022, add 6 Caps.
RESET#
R1094
1
+5VS_AVDD
1
C1210
C1211
10U_0805_10V4Z 0.1U_0402_16V4Z
2
2
80mil
28
1
0.1U_0402_16V4Z
2
2
10K_0402_5%
1
AVDD_5V
2
C1214
29
27
2
R1011
FILT_1.65
AVDD_3.3
1
C1213
3
7
2
18
26
1
0.1U_0402_16V4Z
1U_0402_6.3V6K
C1212
0.1_1206_1%
2
1
+FILT_1.8
FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3
AVDD_HP
12/15 update
B
1
12/15 change Bead to 0Ohm
1
1
R1009
+3VS
10U_0805_10V4Z
Note:
To support Wake-on-Jack,
the CODEC VAUX_3.3 pins
must be powered by a Standby supply.
4
3
2
Title
HD Audio Codec
Size
Document Number
Custom
Rev
0.1
NELA5 M/B LA-6141P Schematic
Date:
W ednesday, April 21, 2010
Sheet
1
37
of
54
5
4
3
2
1
S/PDIF Out JACK
Headphone Out
12/17 update GNDA
1202 update HP connection
12/15 update Res.
PVT 20100304 change to 39 Ohm
C1228
2
2
1215 update
@
C1230
1
2
C1229
2 HPOUT_R_1 1
39_0603_1% L113
2 HPOUT_L_1 1
39_0603_1% L112
1
37 HP_RIGHT
R1025
1
37 HP_LEFT
R1024
PJDLC05_SOT23~D
@
1
3
0.1U_0402_16V4Z
330P_0402_50V7K 330P_0402_50V7K
1
1
D
2
D50
JHP1
D
6
4
2 HPOUT_R_2
FBMA-L11-160808-700LMT_2P
2 HPOUT_L_2
FBMA-L11-160808-700LMT_2P
1
5
SPDIF_PLUG#
1
R1108
37 SPDIF
2
0_0402_5%
1
+5VS_AVDD
2
2
HP_PLUG# 37
TAITW _PJKAT1-08FNBT1TT4N0
CONN@
1202 update HP conn.
Q77B
DMN66D0LDW -7_SOT363-6
5
12/15 update , close to conn.
4
6 1
1
S
G
SPDIF_PLUG#
2
@
2
3
2
HP_PLUG#
R1026
100K_0402_5%
Q78
AO3413_SOT23-3
3
C1224
100P_0402_50V8J
DVT 0121 reserve Res.(for EMI)
+5VS_AVDD
R1027
100K_0402_5%
7
3
8
+5VSPDIF
+MIC_BIASC
Q77A
DMN66D0LDW -7_SOT363-6
2
MIC_PLUG#
HP_PLUG#
1
3
12/15 remove/bypass
+5VSPDIF
C
2
1
D
C
D53
PJDLC05C_SOT23-3
@
DVT 0121 update Q78 to SB934130020
37 MIC_R
1
2 MIC_L_C
1
C1260
R1030
MIC_L_1
2
100_0603_1%
L1151
2
FBMA-L11-160808-700LMT_2P
2.2U_0603_6.3V6K
1
2 MIC_R_C
1
C1261
R1031
MIC_R_1
2
100_0603_1%
L1141
2
FBMA-L11-160808-700LMT_2P
2
2.2U_0603_6.3V6K
SM010004010 300ma 70ohm@100mhz DCR 0.3
1
JMIC1
MIC_L_R
MIC_R_R
3
4
1
1
2
C1232
220P_0402_50V7K @
2
D54
PJDLC05C_SOT23-3
MIC_PLUG#
37 MIC_PLUG#
5
6
CONN@
SUYIN_010030FR006G109ZL
1
C1231
220P_0402_50V7K
MIC JACK
12/17 update GNDA
1
2
2
37 MIC_L
1202 update MIC conn.
R1029
2.2K_0402_5%
2
R1028
2.2K_0402_5%
3
12/15 update to 0603(PWR part)
DVT 0119 add 2.2u_0603 Cap.
1
1
20mil
12/17 update GNDA
22P_0402_50V8J
22P_0402_50V8J
2
2
11/28 check conn. OK
(same as JALA0)
37 SPKR+
37 SPKR-
SPK_R+
SPK_R-
L119
1
1
L120
2 MBC1608121YZF_0603
2
MBC1608121YZF_0603
PJSOT05C_SOT23-3
2
For ESD 10/11
C1235
2
C1236
1000P_0402_50V7K
1
1
1000P_0402_50V7K
11/28 check conn. OK
(same as JALA0)
Int. Speaker Conn.
1
2009/11/23
Issued Date
Deciphered Date
Compal Electronics, Inc.
2010/11/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
5
6
D57
PJDLC05C_SOT23-3
@
Compal Secret Data
Security Classification
5
G1
G2
ACES_88266-04001
CONN@
SPK_L_R+
SPK_L_R-
DVT 0121 reserve Cap.(for EMI)
change D56 to SCA00000200
PVT 20100311 change Cap to 22p(EMI/Audio)
A
1
2
3
4
SM010012010 300ma 120ohm@100mhz DCR 0.4
30mil
D56
JSPK1
1
2
3
4
5
6
C1264
@
2
C1234
D55
1000P_0402_50V7K
1
1
PJDLC05C_SOT23-3
@
1000P_0402_50V7K
ACES_88266-04001
CONN@
1
C1233
1
1
2
SPK_L_L+
SPK_L_L-
3
C1263
B
2 MBC1608121YZF_0603
2
MBC1608121YZF_0603
2
0_0402_5%
2
R1033
3
DMIC_CLK
DMIC_DATA
1
37 DMIC_CLK
37 DMIC_DATA
L118
MBK1608121YZF_0603
JDMIC1
1 1
1
2
2 2
3 3 G1
4 4 G2
0_0402_5%
DMIC_CLK_R
2
DMIC_DATA_R
2
L116
1
1
L117
Digital MIC
+3VS
L121
1
1
SPK_L+
SPK_L-
37 SPKL+
37 SPKL-
3
12/15 for EMI request
DVT 0131 change L121 to 0Ohm Resistor
12/14 for layout
2
30mil
B
3
2
Title
Amplifier & Audio Jack
Size
Document Number
Custom
Rev
0.1
NELA5 M/B LA-6141P Schematic
Date:
W ednesday, April 21, 2010
Sheet
1
38
of
54
A
FAN1 Conn
12/01 update FAN conn.
+5VS
D25
1SS355_SOD323-2
@
2
0_0603_5%
C821
10U_0805_10V4Z
@ D26 BAS16_SOT23-3
1
2
C823
10U_0805_10V4Z
1
2
+3VS
C824
1000P_0402_50V7K
1
2
1
R568
10K_0402_5%
40mil
ACES_85205-0400
CONN@
PWM FAN
H18
H_3P4
2008/10/06
1
1
H26
H_4P2
FD4
1
FD3
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
Deciphered Date
1
1
1
H23
H25
H_4P1X4P4N H_3P0
12/02 add H6
12/07 Remove H19/H20
Compal Electronics, Inc.
Compal Secret Data
Security Classification
H10
H_3P0
1
FD2
H9
H_4P2
H6
H_6P0N
1
H16
H_3P0
1
H21
H_3P0
1
H24
H_3P0
H8
H_4P2
1
1
1
1
H7
H_4P2
1
FD1
Issued Date
1
1
H12
H_3P0
H15
H_4P2
H5
H_4P2
1
H14
H_4P2
H4
H_3P0
1
H13
H_3P0
H2
H3
H_3P0 H_4P0N
1
H1
H_3P0
1
C825
1000P_0402_50V7K
1
2
3
4
1
2
34 FANPWM
1
1
JFAN1
1
2
3
4
1
+VCC_FAN1
34 FAN_SPEED1
1
1
+VCC_FAN1
2
2
2
1
R566
1
+5VS
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
FAN & Screw Hole
Document Number
Rev
0.1
NELA5 LA-6141P
Wednesday, April 21, 2010
Sheet
39
of
54
C
2
2
1
SYSON#
6
33 SYSON#
470_0603_5%
D
S
2N7002-7-F_SOT23
Q40
Q30A
R573
100K_0402_5%
12/14 update
DVT 0131 change Q40 to SB570020410
2
5 VLDT_EN#
2
34,45 SYSON
R584
10K_0402_5%
1
2
G
1
1
3
34,46 VLDT_EN
Q39B
+5VALW
C844
2
R576
100K_0402_5%
12/08 change to Dual channel MOS
1
+3VALW TO +3VS
0.1U_0603_25V7K
12/07 remove vga_on inverse circuit
SUSP
47 SUSP
3
+3VS
+3VALW
2
C843
10U_0805_10V4Z
2
2
10U_0805_10V4Z
0.1U_0603_25V7K
PVT 20100312 Add
1 VGA@ 2
R575
100K_0402_5%
+VSB
+1.5VS
2
4
5 VGA_PWR_ON#
+5VALW
1
VGA_PWR_ON# 2 VGA@ 1
R503 47K_0402_5%
R602
100K_0402_5%
C835
VGA@
0.1U_0603_25V7K
VGA_PWR_ON#
Q34A
VGA@
2
1
12/12 update
DVT 0131 change Q42 to SB570020410
34,36,48,49 VGA_PWR_ON
0.1U_0402_16V4Z
Q9B
5
SUSP
1
1
C848
12/12 update
6
2
DMN66D0LDW-7_SOT363-6
R313
470_0603_5%
3
1
VGA@
VGA@
VGA@
D
2
G
Q42
R608
100K_0402_5%
VGA@
2
VGA@
S
2
2
C690
10U_0805_6.3V6M
2
DMN66D0LDW-7_SOT363-6
R511
2
1
2
47K_0402_5%
1
12/07 remove PE_GPIO1 inverse circuit
1
2
1
G
Q9A
4
+1.8VS to +1.8VSG
DMN66D0LDW-7_SOT363-6
3
1
3
1
2
R1142
0_0402_5%
6
1
100K_0402_5%
12/12 update
SUSP#
Q34B
VGA@
D
S
R314
2
R572
VGA@
470_0603_5%
DMN66D0LDW-7_SOT363-6
Q59
AO3413_SOT23-3
3
2
VGA@
+1.5VS
+1.5V
1
1
C832
C833
VGA@
VGA@
10U_0805_10V4Z
2
2
1U_0402_6.3V6K
2
1
2
1
1
PVT 20100312 Add
C831
3
1
Q38A
1
1
C830
VGA@
2
SUSP
1
5
DMN66D0LDW-7_SOT363-6
3
6
DMN66D0LDW-7_SOT363-6
SUSP
Q38B
12/08 change to Dual channel MOS
R580
10K_0402_5%
+1.5VSG
U37 VGA@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
4
1
2
R1141
0_0402_5%
+1.5V
4
1
200K_0402_5%
3VS_GATE
2
R582
+VSB
1
2
C836
10U_0805_10V4Z
2
2
1U_0402_6.3V6K
Q30B
+1.5V to +1.5VSG
R579
470_0603_5%
4
2
1
1.5VSG_GATE
C841
10U_0805_10V4Z
2
2
10U_0805_10V4Z
5
34,44,48 SUSP#
1
C842
4
C840
1
3 1
1
U39
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
DMN66D0LDW-7_SOT363-6
2
1
1
Q39A
2N7002-7-F_SOT23
PVT 20100312 Add
DMN66D0LDW-7_SOT363-6
VLDT_EN#
1
2
DMN66D0LDW-7_SOT363-6
1
DMN66D0LDW-7_SOT363-6
VLDT_EN#
R578
1
1
1
2
R1140
0_0402_5%
0.1U_0603_25V7K
PVT 20100312 Add
1
2
2
47K_0402_5%
6
2
1
R581
+VSB
2
4
SUSP
C834
C838
4
0_0402_5% 1
Q33A
2
10U_0805_10V4Z
R570
100K_0402_5%
R583
100K_0402_5%
C839
10U_0805_10V4Z
2
2
1U_0402_6.3V6K
Q33B
5
2
1
12/08 change to Dual channel MOS
1
1
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
SUSP
U38
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
2
R577
C837
1K_0402_5%
2
R1139
6
+VSB
1
+5VALW
+5VALW
+1.1VS
4
R574
1
2
226K_0402_1%
R571
470_0603_5%
3
Pre MP update
1
1
C829
10U_0805_10V4Z
2
2
1U_0402_6.3V6K
5VS_GATE
10U_0805_10V4Z
2
2
10U_0805_10V4Z
1
C827
2
1
C828
+1.1VALW
1
1
4
C826
E
+1.1VALW TO +1.1VS
+5VS
U36
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
1.1VS_GATE
+5VALW
D
1
B
+5VALW TO +5VS
3
A
C691
6
Q46A
+0.75VS
12/08 change to Dual channel MOS
+CPU_VDDR
Q47A
VGA@
2
2
2
3
VGA@
R1111
VGA@
100K_0402_5%
R611 VGA@
33K_0402_5%
2
1
2
VGA@
C852
VGA@
0.1U_0603_25V7K
VGA_PWR_ON 1
10K_0402_5%
2
R607 1
C846
VGA@
0.1U_0603_25V7K 2
D
S
2
G
1
C1266
10U_0805_6.3V6M
2
R1112
470_0603_5%
VGA@
1
VGA_PWR_ON#
4
1
DMN66D0LDW-7_SOT363-6
VGA_PWR_ON# 1 VGA@ 2
R489 200K_0402_5%
+NB_CORE
1
C692
5
1
2
R1143
0_0402_5%
VGA@
1
1
1 VGA@ 2
R510 200K_0402_5%
Q47B
VGA@
DMN66D0LDW-7_SOT363-6
1
+VSB
SUSP
1.8VSG_GATE
2
+2.5VS
12/12 update
2
+3VSG
AO3413_SOT23-3
3
1
+1.5V
VGA@
Q51B
DMN66D0LDW-7_SOT363-6
1
6
1
2
DMN66D0LDW-7_SOT363-6
4
3
1
DMN66D0LDW-7_SOT363-6
1
6
1
2
VGA@
Q51A
VGA_PWR_ON#
5
PVT 20100312 Add
Q58
+3VS
G
VGA_PWR_ON#
R592
470_0603_5%
VGA@
D
2
R603
470_0603_5%
VGA@
R594
VGA@
470_0603_5%
S
R598
470_0603_5%
VGA@
VGA@ VGA@
2
2
10U_0805_10V4Z 10U_0805_10V4Z
C855
VGA@
C853
10U_0805_10V4Z
2
2 VGA@
1U_0402_6.3V6K
D
2
S
3
1
2
C854
+3VSG
3VSG_GATE
1
1
2
C856
1
1
+1.8VS
DVT 0131 update Q58 part to SB934130020
DVT 0125 update +3VSG circuit same as NEW75
PVT 20100311 update C1265 to GND
3
+VGA_CORE
+1.8VSG
U45
VGA@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
4
+1.0VSG
+1.8VS
12/08 change to Dual channel MOS
DVT 0131 update Q59 part to SB934130020
1
0.22U_0603_16V4Z2
Q8
VGA@
SSM3K7002FU_SC70-3
VGA@
1 C1265
0.1U_0603_25V7K
VGA@
2 VGA_PWR_ON#
G
Q84
2N7002-7-F_SOT23
DVT 0131 change Q84 to SB570020410
Q57A
2
SUSP
Q44A
5
SUSP
Q57B
R604
470_0603_5%
5
VLDT_EN#
Q44B
DMN66D0LDW-7_SOT363-6
4
3 1
2
SYSON#
R591
470_0603_5%
DMN66D0LDW-7_SOT363-6
4
3 1
2
2
R590
470_0603_5%
DMN66D0LDW-7_SOT363-6
4
3 1
2
R605
470_0603_5%
DMN66D0LDW-7_SOT363-6
1
6 1
2
4
DMN66D0LDW-7_SOT363-6
1
6 1
2
4
0.1U_0402_16V4Z
R610
470_0603_5%
2
VGA@
VLDT_EN#
Q46B
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
5
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
DC Interface
Document Number
Rev
0.1
NELA5 LA-6141P
Sheet
Wednesday, April 21, 2010
E
40
of
54
A
B
C
D
PR1
1M_0402_1%
1
2
VIN
VIN
VIN
2
1
1
2
8
-
PC1
PR7
1000P_0402_50V7K
20K_0402_1%
1
LM393DR_SO8
2
2
PC2
0.1U_0603_25V7K
2
PR8
10K_0402_5%
PC6
1000P_0402_50V7K
3
2
1
PC5
100P_0402_50V8J
+
O
PD1
RLZ4.3B_LL34
2
2
PC4
100P_0402_50V8J
2
1
1
PC3
1000P_0402_50V7K
2
2
PJP1
1
P
PACIN
1
17,34 ACIN
PR4
22K_0402_5%
1
2
PU1A
G
PR5
10K_0402_1%
1
2
4
DC_IN_S1
1
2
3
4
5
6
PR3
84.5K_0402_1%
2
PL1
SMB3025500YA_2P
1
2
1
1
2
3
4
GND
GND
1
PR2
10K_0402_5%
1
SP02000GC00
ACES_50305-00441-001
1
VS
1
1
PR9
10K_0402_5%
1
2
RTCVREF
44,47 PACIN
Vin Dectector
Min.
H-->L 16.976V
L-->H 17.430V
Typ
17.525V
17.901V
Max.
17.728V
18.384V
2
2
PJ32
1
1
+1.0VSG
(3A,120mils ,Via NO.=6)
+RTCBATT
+RTCBATT
ML1220T13RE
45@
2
+1.8VSP1
@ PC71
0.1U_0402_16V7K
2
2
2
JUMP_43X118
2
1
1
+1.8VS
JUMP_43X118
(3A,120mils ,Via NO.=6)
1
1
@ PC148
0.1U_0402_16V7K
1
2
2
+1.0VSGP
+
PBJ1
PJ1
@ PC7
0.1U_0402_16V7K
2
1
1
PJ26
+3VALW
2
+1.1VALWP
JUMP_43X118
@ PC8
0.1U_0402_16V7K
2
1
1
+1.1VALW
JUMP_43X118
(5.2A,220mils ,Via NO.=11)
1
1
(3.9A,160mils ,Via NO.= 8)
2
2
+3VALWP
2
-
PJ22
PJ11
PJ3
2
2
+5VALWP
1
1
+VSB
1
@ PC15
0.1U_0402_16V7K
2
3
2
PJ19
2
1
1
1
+NB_CORE
PJ9
+2.5VSP
2
@ PC16
0.1U_0402_16V7K
2
1
1
+2.5VS
JUMP_43X39
(5A,200mils ,Via NO.=10)
1
1
2
+CPU_VDDRP
+VGA_CORE
JUMP_43X118
PJ13
2 2
1 1
PC70
0.1U_0402_25V6
2
1
1
+CPU_VDDR
JUMP_43X39
(1.5A,60mils ,Via NO.= 3)
1
2
1
1
@ PC69
0.1U_0402_16V7K
2
2
2
JUMP_43X118
PU2
IN
GND
G920AT24U_SOT89-3
PC17
1
10U_0805_10V4Z
(25A,1000mils ,Via NO.=50)
2
N2
1
OUT
2
PC18
1U_0805_25V4Z
4
2
3
1
+1.5V
1
PJ21
3.3V
2
1
(9.5A,400mils ,Via NO.=20)
1
JUMP_43X118
1
PC14
0.1U_0603_25V7K
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/09/20
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
2
2
2
2
+NB_COREP
PR15
200_0603_5%
+CHGRTC
+0.75VS
JUMP_43X118
2
TP0610K-T1-E3_SOT23-3
RTCVREF
4
1
JUMP_43X118
1
JUMP_43X39
PJ20
PR17
560_0603_5%
1
2
2
PJ8
VS
2
1
2
2
@ PC12
0.1U_0402_16V7K
(120mA,40mils ,Via NO.= 2)
+VGA_COREP
PR16
560_0603_5%
1
2
1
1
1
PC13
0.22U_0603_25V7K
2
+1.5VP
2
3
1
PR13
100K_0402_1%
2
PC11
0.1U_0402_25V6
PJ5
2
PQ1
N1
2
+VSBP
PR11
68_1206_5%
2
PR12
200_0603_5%
CHGRTCP 1
2
PR14
22K_0402_1%
1
2
2
JUMP_43X118
(3A,120mils ,Via NO.=6)
1
PR10
68_1206_5%
36 51ON#
@ PC10
0.1U_0402_16V7K
1
1
1
1
2
+5VALW
PJ6
1
BATT+
3
1
(5A,200mils ,Via NO.= 10)
PD2
RLS4148_LL34-2
PD3
RLS4148_LL34-2
2
JUMP_43X118
1
2
@ PC9
0.1U_0402_16V7K
2
+0.75VSP
1
2
VIN
B
C
DCIN & DETECTOR
Rev
0.1
NELA5
W ednesday, April 21, 2010
D
Sheet
41
of
54
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
10
9
8
7
6
5
4
3
2
1
1
2
1
8
7
3
OT1 TMSNS2
6
OT2 RHYST2
5
2
1
PR30 9.53K_0402_1%
G718TM1U_SOT23-8
PR261
1K_0402_5%
PR24
6.49K_0402_1%
2
1
2
1
GND RHYST1
1
2
2
1
1
2
EC_SMB_CK1 34
PC19
0.01U_0402_25V7K
1
VCC TMSNS1
2
4
PC20
1000P_0402_50V7K
PR21 @
100K_0402_1%
1
EC_SMB_DA1 34
1
2
<40,41>
BATT+
PR28
21K_0402_1%
1
1
2
PR32
100_0402_1%
PL2
SMB3025500YA_2P
1
2
BATT_S1
PU3
2
CONN@
PR27
10K_0402_1%
2
PR29
100_0402_1%
<40,41>
VMB
PJP2
SUYIN_200275GR008G13GZR
PC21
0.1U_0603_25V7K
2
TS
B/I
2
VL
EC_SMDA
EC_SMCA
1
GND
GND
8
7
6
5
4
3
2
1
1
1
PH1
100K_0402_1%_NCP15W F104F03RC
@ PR169
47K_0402_1%
+3VALW P
2
PR33
1K_0402_1%
2
BATT_TEMP 34
2
1
100K_0402_1%_NCP15WF104F03RC
1
MAINPW ON 8,43,47
PH2 @
2
PQ3 TP0610K-T1-E3_SOT23-3
1
1
2
@
2
PC25
0.1U_0603_25V7K
2
2
VL
+VSBP
1
2
1
1
PR34
100K_0402_1%
3
PC24
0.22U_1206_25V7K
3
B+
@
3
2
PR36
22K_0402_1%
1
PR39
0_0402_5%
2
D
3
1
S
PQ4
2N7002W -T/R7_SOT323-3
2
G
2
1
43,45 SPOK
PC27
0.1U_0402_16V7K
1
PR38
100K_0402_1%
@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/09/20
Deciphered Date
2010/03/12
Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Rev
0.1
NELA5
W ednesday, April 21, 2010
D
Sheet
42
of
54
5
4
3
2
1
TPS51427_B+
TPS51427_B+
5
6
7
8
PC29
4.7U_0603_6.3V6M
2
1
3
2
1
16
DRVL1
18
PGND
22
VOUT1
10
FB1
11
VSW
9
LX5
1
2
3
DL3
23
DRVL2
30
VOUT2
32
REFIN2
DL5
PQ8
AO4712_SO8
VL
1
C
2VREF_TPS51427
1
2
1
2
1
4.7_1206_5%
@
+ PC35
150U_V_6.3VM_R18
2
C
1
FB3
@ PR44
10K_0402_1%
1
@
PR49
66.5K_0402_1%
LL1
LL2
1
25
@
4
680P_0402_50V7K
DH5
PR47 0_0603_5%
BST5A 2
1
PC42
0.1U_0603_25V7K
LX3
PR43
17
2
15
VBST1
1
DRVH1
VBST2
PC34
2
DRVH2
PC36
1U_0603_10V6K
1
2
PL4
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1
5
6
7
8
3
7
LDO
24
V5FILT
26
VIN
19
2
PC41
1U_0603_10V6K
1
2
2
V5DRV
3
2
1
1
@ PC37
680P_0402_50V7K
DH3
BST3A
D
+5VALWP
1
PC43
0.1U_0603_25V7K
4
2
2
PR40
2
1
0_0603_5%
PQ6
AO4466_SO8
4
2
2
1
PQ7
AO4712_SO8
2
PR42
0_0402_5%
+
2
@ PR41
4.7_1206_5%
1
1
PC39
330U_D2E_6.3VM_R25M
TP
8
7
6
5
1
PU4
33
6
PL3
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
+3VALWP
PC40
0.1U_0603_25V7K
VL
PR48
0_0402_5%
2
8
7
6
5
PQ5
AO4466_SO8
4
1
PC31
10U_1206_25V6M
2
1
2
1
PC120
2200P_0402_25V7K
2
1
D
PC122
2200P_0402_25V7K
JUMP_43X118
PC30
2200P_0402_50V7K
2
1
1
1
2
3
1
PC45
2200P_0402_50V7K
2
1
2
PC28
10U_1206_25V6M
2
1
PR50
0_0805_5%
1
2
PJ12
2
B+
FB5
VREF2
PC47 0.22U_0603_10V7K
8
SKIPSEL
20
PR46
100K_0402_1%
2
PGOOD1
13
TRIP1
12
TRIP2
31
2
2
1
GND
21
5
PC143
1U_0603_10V6K
1
2
0_0402_5%
1
PR45
1
0_0402_5%
2
VL
SPOK 42,45
PR60
330K_0402_1%
2
1
ILIM2
2
SN0806081RHBR_QFN32_5X5
1
PR57
294K_0402_1%
B
PR53
0_0402_5%
2VREF_TPS51427 2
1
2
PC38
0.047U_0402_16V7-K
1
1
TONSE
EN2
VREF3
EN1
27
1
@ PR55
47K_0402_5%
1
2
1
PR54
0_0402_5%
2
3
EN_LDO
2
PR51
0_0402_5%
2
2
2
28
@ PR56
0_0402_5%
PR52
806K_0603_1%
8,42,47 MAINPWON
PGOOD2
@ PR59
2
2
VL
B
29
NC
14
PC44
0.22U_0603_25V7K
2VREF_TPS51427 1
PD16
1SS355_SOD323-2
4
1
1
PR58
200K_0402_5%
1
2
VS
PD17
GLZ5.1B_LL34-2
1
2
1
+3.3VALWP Ipeak=5.9A ; Imax=4.1A;Iocp=6.6A
Choke DCRmax=23m ohm,
Rds(on)=18m ohm(max) ; Rds(on)=15m
ohm(typical)
Vlimit=(5E-06 * 294K)/10=147mV
Ilimit=147mV/18m ~ 147mV/15m
=8.17A ~ 9.8A
Delta I=1.94A (Freq=300KHz)
Iocp=Ilimit+Delta I/2
=9.14A ~ 10.77A
LDOREFIN
+5VALWP Ipeak=7A ; Imax=5A;Iocp=8.4A
Choke DCRmax=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Delta I=1.96A (Freq=400KHz)
Iocp=Ilimit+Delta I/2
=9.729A ~ 11.562A
@ PC46
0.047U_0402_16V7K
PQ37
TP0610K-T1-E3_SOT23-3
1
2
A
A
2007/09/20
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/03/12
Title
+5VALWP/+3VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
NELA5
Sheet
W ednesday, April 21, 2010
1
43
of
54
B
C
D
B+
Iada=0~4.74A(90W/19V=4.736A)
CP = 85%*Iada ; CP = 4.03A
CELLS
CSOP
ICOMP
CSIN
20
CSIP
19
PHASE
18
UGATE
17
CHLIM
BOOT
16
6251aclim
20K_0402_1%
PR87
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
34 65W/90W#
PQ54
2
G
D
GND
PGND
13
S
12
2
2
4
PL5
10UH_MMD-10DZ-100M-X1_6A_20%
CHG
1
2
4
2
2
DL_CHG
26251VDD
1
1
3
PC61
2200P_0402_25V7K
2
1
PC48
0.1U_0603_25V7K
2
1
PC51
10U_1206_25V6M
2
1
3
1
<40,41>
PD12
RB751V-40TE17_SOD323-2
6251VDDP
2
4
PR300 2.2_0603_5%
DH_CHG
1
2
PR82
PC59
2.2_0603_5%
0.1U_0603_25V7K
BST_CHG 1
2 BST_CHGA 2
1
1
2
12.1K_0402_1%
1
1
2
S
PQ55
AO4466_SO8
1
9
CSOP
2
ICM
VREF
2
3
PQ53
PDTC115EU_SOT323
VCOMP
PR84
6251VREF 1
PR85
2.55K_0402_1%
2
5
CSON
PC53
0.047U_0603_16V7K
1
2
PR73
20_0402_5%
2
1
PR74
PC129
20_0402_5%
0.1U_0603_25V7K
1
2
PR76
2_0402_5%
LX_CHG
PQ23
2N7002W -T/R7_SOT323-3
2 PACIN
G
PR86
4.7_0603_5%
PC64
4.7U_0805_6.3V6K
PQ57
AO4466_SO8
BATT+
1
4
2
3
PR78
0.02_1206_1%
PC63
10U_1206_25V6M
2
1
22
21
D
PC68
10U_1206_25V6M
2
1
CSON
EN
8
0.1U_0402_16V7K
1
34 IREF
4
3
2
1
3
PR72
20_0402_5%
1
2
1
23
2
ACSET ACPRN
PR80
4.7_1206_5%
2
DCIN
VIN
PD11
1SS355TE-17_SOD323-2
2
1
2
PC128
680P_0402_50V7K
24
PR67
200K_0402_1%
1
2
PQ20
PDTC115EU_SOT323
wrong Value
PC127
0.1U_0603_25V7K
2
1
ACOFF
5
6
7
8
DCIN
7
6251VREF
PC58
1
2
PR81
80.6K_0402_1%
2
1
SUSP# 34,40,48
3
2
1
VDD
6
PR77
100_0402_1%
1
2
3
PR79
22K_0402_5%
1
2
ACOFF
2 10K_0402_1%
1
2
PC57
@ 100P_0402_50V8J
34 ADP_I
PR83
100K_0402_1%
34,47 ACOFF
1 PR75
SUSP#
1
PC55
0.01U_0402_25V7K
2
1
PC60
0.01U_0402_25V7K
2
1
PACIN
2
6800P_0402_25V7K
2
S
ACON
1
41,47 PACIN
PQ56
2N7002W -T/R7_SOT323-3
1
3
47 ACON
3
D
2
G
PC54
1
3
VIN
PD8
1SS355TE-17_SOD323-2
1
2
FSTCHG 34
5
6
7
8
3
6251_EN
1
1
PQ22
2N7002W -T/R7_SOT323-3
FSTCHG
1
PR63
47K_0402_1%
1
2
PR65
10K_0402_1%
BAS40CW _SOT323-3
PU5
2
34 3S/4S#
1
2
2
1
100K_0402_1%
3
2
2
2
PR71
1
1
8
7
6
5
1 1
1
2
1
2
PC67
0.1U_0402_16V7K
PQ24
PDTC115EU_SOT323
2
1
3
S
2
G
1
PQ18
PDTC115EU_SOT323
PR66
6251VDD
2
100K_0402_1%
1
1
1
6251VDD
PR69
150K_0402_1%
PQ21
PDTC115EU_SOT323
1
2
3
PD9
1
PR70 47K_0402_5%
2
PQ16
AO4407A_SO8
2
CSIN
2
PR68
10K_0402_5%
2
1
FSTCHG
CHG_B+
FBMA-L18-453215-900LMA90T_1812
DCIN
1
PC49
2.2U_0603_6.3V6K
2
1
2
PD10
1SS355TE-17_SOD323-2
1
2
D
3
P3
PQ19
PDTA144EU_SOT323-3
47K
2
PR61
3 0.02_2512_1%
PL21
1
PQ17 TP0610K-T1-E3_SOT23-3
47K
2
4
CSIP
PC56
5600P_0402_25V7K
1
2
1
PC62
0.1U_0603_25V7K
2
1
3
2
PR94
200K_0402_1%
1
PC50
10U_1206_25V6M
2
1
8
7
6
5
1
PR62
47K_0402_1%
B+
P3
PQ15
AO4407A_SO8
1
2
3
4
1
1
2
3
4
8
7
6
5
PR64
100K_0402_1%
2
1
P2
PQ14
AO4407A_SO8
VIN
PC52
0.1U_0603_25V7K
2
1
A
ISL6251AHAZ-T_QSOP24
2N7002W -T/R7_SOT323-3
3
3
Iada=0~3.42A(65W)
CP= 85%*Iada; CP=2.91A
34 CALIBRATE#
PR88
15.4K_0402_1%
1
2
2
CP= 85%*Iada; CP=4.03A
PR90
31.6K_0402_1%
1
Iada=0~4.74A(90W)
CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.464V (90W), Iinput=4.03A
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A
PR84=12.1K;PR85=2.55K
IREF=0.7224*Icharge
ADP_I = 19.9*3.42*0.95*0.02=1.29V
4
4
BATT Type
Charging Voltage
(0x15)
CV mode
12600mV
12.60V
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Normal 3S LI-ON Cells
2007/09/20
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
-
Date:
A
B
C
CHARGER
Rev
0.1
NELA5
W ednesday, April 21, 2010
D
Sheet
44
of
54
A
B
C
D
PL19
PR96
255K_0402_1%
1
2
14
11
VDDP
10
LX_1.1VALW
LGATE
2
PR102
10K_0402_1%
DL_1.1VALW
9
1
PC73
4.7U_0805_25V6-K
2
1
PR100
4.7_1206_5%
+5VALW
1
1
+ PC76
330U_D2_2.5VY_R15M
2
4
1
PGND
RT8209BGQW _W QFN14_3P5X3P5
2
8
7
2
VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
GND
PGOOD
PC79
@ 47P_0402_50V8J
1
2
1
FB
12
CS
+1.1VALWP
2
5
PHASE
0.1U_0603_25V7K
1
VDD
DH_1.1VALW
2
VOUT
4
13
5
6
7
8
3
UGATE
PC80
4.7U_0805_10V6K
3
2
1
TON
BOOT
NC
1
EN/DEM
2
6
PC78
680P_0603_50V7K
PQ26
AO4456_SO8
PR103
4.7K_0402_1%
1
2
2
2
1
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=9.61A, Imax=6.73A, Iocp=11.53A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=11.53*5.6*1.3=0.084V
Rcs=Vtrip/9uA=0.084V/9uA=9.3K
choose Rcs=10K
Iocpmax=((10K*11uA)/0.0045)+1.03A=25A
Iocpmin=((10K*9uA)/(0.0056*1.3))+1.03A=13.39A
Iocp=13.39A~25A
2
PR104
8.45K_0402_1%
PL20
1
FBMA-L18-453215-900LMA90T_1812
2
B+
PC83
4.7U_0805_25V6-K
2
1
PC82
4.7U_0805_25V6-K
1
4
PQ27
AO4466_SO8
3
11
VDDP
10
LGATE
9
2
PR112
13K_0402_1%
1
DL_1.5V
4
RT8209BGQW _W QFN14_3P5X3P5
2
4
Cout ESR=17 mohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm
Ipeak=14.4A, Imax=10.08A, Iocp=17.28A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
=>1/2Delta I=1.95A
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V
Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A
Iocp=18A~32A
+1.5VP
PC90
4.7U_0805_10V6K
PQ28
AO4726L_SO8
1
+ PC86
330U_D2_2.5VY_R15M
PC88
680P_0603_50V7K
2
1
PR113
10K_0402_1%
1
2
PR114
10K_0402_1%
2
VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=280KHz
PR110
4.7_1206_5%
+5VALW
1
PGND
8
PGOOD
7
2
PC89
@ 47P_0402_50V8J
1
2
GND
6
PC87
4.7U_0603_6.3V6K
LX_1.5V
1
2
NC
FB
12
CS
1
5
PHASE
1
VDD
DH_1.5V
13
2
VOUT
4
UGATE
5
6
7
8
3
BOOT
TON
PL7
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
3
2
1
PR111
100_0603_1%
1
2
2
PC84
0.1U_0603_25V7K
BST_1.5V-1
1
2
14
1
PU7
2
+5VALW
15
@PC85
@
PC85
0.1U_0402_16V7K
2
@ PR109
30K_0402_5%
EN/DEM
3
1
1
3
2
1
PR108
2.2_0603_5%
BST_1.5V 1
2
0_0402_5%
2
2
2
5
6
7
8
1
PC81
2200P_0402_50V7K
1.5V_B+
PR106
226K_0402_1%
1
2
34,40 SYSON
1
PL6
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
PC75
BST_1.1VALW -11
2
1
PR101
100_0603_1%
1
2
15
1
PU6
2
2
@PC74
@
PC74
0.1U_0402_16V7K
PC77
4.7U_0603_6.3V6K
PR105
1
B+
DCR= 7.5 mohm
@ PR99
30K_0402_5%
+5VALW
2
PQ25
AO4466_SO8
1
42,43 SPOK
FBMA-L18-453215-900LMA90T_1812
1
4
PR98
2.2_0603_5%
BST_1.1VALW
1
2
3
2
1
PR97
0_0402_5%
1
2
PC72
4.7U_0805_25V6-K
1
2
2
5
6
7
8
1
PC139
2200P_0402_50V7K
1.1VALW _B+
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/09/20
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
1.5VP / 1.1VALWP
Rev
0.1
NELA5
W ednesday, April 21, 2010
Sheet
D
45
of
54
A
B
C
D
FB1_NB_COREP
2
+5VALW
PR158
23.2K_0402_1%
1
PR117
0_0603_5%
BST_NB_CORE
1
2
2
14
11
VDDP
10
9
DL_NB_CORE
RT8209BGQW _W QFN14_3P5X3P5
2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m
Ipeak=10A, Imax=7A, Iocp=12A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=12*5.6*1.3=0.087V
Rcs=Vtrip/9uA=0.087V/9uA=9.67K
choose Rcs=10K
Iocpmax=((10K*11uA)/0.0045)+1.03A=25A
Iocpmin=((10K*9uA)/(0.018*1.3))+1.03A=13.39A
Iocp=13.39A~25A
1
1
2
1
+ PC95
330U_D2_2.5VY_R15M
2
4
1
PGND
2
LGATE
PR119 @
4.7_1206_5%
+5VALW
2
PR121
10K_0402_1%
+NB_COREP
1
NC
7
8
PGOOD
PC98
@ 47P_0402_50V8J
1
2
GND
6
PC96
4.7U_0603_6.3V6K
LX_NB_CORE
1
2
12
CS
1
FB
PHASE
1
VDD
DH_NB_CORE 0.1U_0603_25V7K
13
2
VOUT
4
UGATE
5
6
7
8
3
BOOT
TON
5
15
1
2
PL8
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
PC93
BST_NB_CORE-1
1
2
PC97 @
680P_0603_50V7K
2
PC99
4.7U_0805_10V6K
3
2
1
PR120
100_0603_1%
1
2
VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
+
PQ29
AO4466_SO8
1
PU8
2
2
PC94
0.1U_0402_16V7K
FB1_NB_COREP
2
1
DCR= 7.5 mohm
@ PR118
30K_0402_5%
+5VALW
1
4
3
2
1
PR116
100K_0402_5%
1
2
34,40 VLDT_EN
B+
2
FBMA-L18-453215-900LMA90T_1812
PC218
100U_25V_M
PR115
309K_0402_1%
1
2
1
PC92
4.7U_0805_25V6-K
PC125
0.1U_0402_25V6
2
2
5
6
7
8
1
1
3
S
S
PC91
4.7U_0805_25V6-K
1
PQ44
SSM3K7002F_SC59-3
2
G
EN/DEM
PC126
0.01U_0402_25V7K
PL22
NB_CORE_B+
D
2
3
1
PR157
0_0402_5%
10K_0402_5%
PR159
1
2
D
SSM3K7002F_SC59-3
13 POW ER_SEL
PQ43
2
G
2
2
1
1
1
1
PR131
10K_0402_1%
1.1V
2
LOW
1
HIGH
PC140
2200P_0402_50V7K
POWER_SEL
0.95V
PR123= 17.4 Kohm
PQ30
AO4456_SO8
1
PR122
4.7K_0402_1%
1
2
2
PR123
17.4K_0402_1%
+1.5V
PU16
APL5508-25DC-TRL_SOT89-3
1
+5VALW
VIN
9
2
2
1
2
1
1
2
1
2
VDDR_SW
HIGH
1
SSM3K7002F_SC59-3
PQ58
D
3
1
2
@ PR153
150_1206_5%
+CPU_VDDRP
PR156
249K_0402_1%
2
PR161
165K_0402_1%
PC118
0.01U_0402_25V7K
GND
PR154
31.6K_0402_1%
APL5915KAI-TRL_SO8
@ PR152
10K_0402_1%
S
LOW
1.05V
0.9V
4
2
G
1
27 VDDR_SW
1
2
2
+2.5VSP
PC119
22U_0805_6.3V6M
3
FB
+5VALW
4
1
2
1
2
1
VOUT
3
PC116
4.7U_0805_6.3V6K
2
PR188 @
47K_0402_5%
EN
1
1
1
8
PC114
1U_0402_6.3V6K
6
4
2
PC121
0.1U_0402_16V7K
5
1
10K_0402_1%
1
2
VIN
VOUT
1
PR155
VLDT_EN
OUT
2
POK
VCNTL
PU12
7
IN
GND
2
PC115
1U_0402_6.3V6K
2
1
3
2
+3VS
PJ24
@ JUMP_43X79
PC113
4.7U_0805_6.3V6K
1
3
PR160
10K_0402_1%
2007/09/20
Deciphered Date
2010/03/12
Title
+NB_COREP/+2.5VS/+CPU_VDDRP
2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Rev
0.1
NELA5
W ednesday, April 21, 2010
D
Sheet
46
of
54
5
4
3
2
PR124
1K_1206_5%
1
2
7
4
VOUT
NC
8
TP
9
PC101
1U_0603_6.3V6M
2
D
2
NC
1
VREF
2
PR130
1K_0402_1%
PR127
1K_1206_5%
1
2
PR129
3
+3VALW
2
5
1
PR132
100K_0402_5%
1
+0.75VSP
34,44 ACOFF
DTC115EUA_SC70-3
PC103
10U_0805_6.3V6M
PQ34
DTC115EUA_SC70-3
2
3
3
2
1 2
PQ33
1
2
1
PC102
0.1U_0402_16V7K
2
1
S
PR134
2
D
1K_0402_1%
3
1
2
PC104
0.22U_0402_10V4Z
PQ32
2
G
2N7002W-T/R7_SOT323-3
PR133
300K_0402_5%
1
2
1
APL5336KAI-TRL SOP
40 SUSP
B+
1
100K_0402_5%
6
NC
2
VCNTL
GND
1
VIN
2
1
2
2
1
3
PR126
1K_1206_5%
1
2
LL4148_LL34-2
PU9
1
PC100
4.7U_0805_6.3V6K
1
PR128
1
2
1
2
PJ17
JUMP_43X79
PQ31
TP0610K-T1-E3_SOT23-3
PR125
1K_1206_5%
1
2
PD13
VIN
100K_0402_5%
1
+1.5V
D
1
Ipeak=1A, Imax=0.7A
C
C
VL
B+
PR135
2.2M_0402_5%
1
1
2
PR136
499K_0402_1%
1
VS
8
2
RTCVREF
1
D
1
499K_0402_1%
PQ35
SSM3K7002FU_SC70-3
2
G
2
2
2
PR139
PR140
34K_0402_1%
2
1
PC107
0.01U_0402_25V7K
1
PR138
191K_0402_1%
PRG++ 2
1
2
PC105
0.1U_0603_25V7K
B
PR141
47K_0402_5%
1
PACIN 41,44
1
6
LM393DR_SO8
1
2
5
-
4
RB715F_SOT323-3
B
+
32.4
3
O
PC106
1000P_0402_50V7K
44 ACON
7
1
PU1B
1
P
PD14
2
G
8,42,43 MAINPWON
2
PR137
100K_0402_1%
3
S
PQ36
DTC115EUA_SC70-3
1
ACIN
+5VALW
2
3
2
66.5K_0402_1%
@ PR142
Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/09/20
Issued Date
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Percharge/+0.75VSP
Rev
0.1
NELA5
W ednesday, April 21, 2010
Sheet
1
47
of
54
5
4
3
2
1
D
D
1
2
1
PC124
22U_0805_6.3V6M
1
PR145
61.9K_0402_1%
2
1
2
SY8033BDBC_DFN10_3X3
PC155
680P_0603_50V7K
1
@
2
@
PC117
22U_0805_6.3V6M
2
1
PR147
124K_0402_1%
+1.8VSP1
PC153
22P_0402_50V8J
6
1
FB
2
3
1
LX
LX_1.8V
PR143
4.7_1206_5%
2
2
SVIN
LX
NC
8
EN
PL9
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
4
PVIN
PG
9
TP
@
12/14 Update by HW requuest
PVIN
11
EN_1.8V
1
1
0_0402_5%
2
2
PR144
PC157
0.1U_0402_25V6
34,40,44 SUSP#
10
5
1
2
PR148
47K_0402_5%
1
JUMP_43X79
2
2
2
PC154
22U_0805_6.3V6M
1
NC
PJ28
PU11
1
7
@
+3VALW
20100308 Change MP2121 to SY8033
C
C
+3VALW
2
1
+1.5V
PC147
1U_0402_6.3V6K
VGA@
B
PJ31
JUMP_43X79
VGA@
1
1
1
PC145
0.022U_0402_25V7K
VGA@
2
GND
2
APL5913-KAC-TRL_SO8
PC144
22U_0805_6.3V6M
VGA@
VGA@ PR175
6.04K_0402_1%
VGA@ PR173
2
10K_0402_5%
2
VGA_PW R_ON
+1.0VSGP
VGA@ PC146
1U_0402_6.3V6K
@ PR172
22K_0402_5%
2
2
A
1
1
34,36,40,49 VGA_PW R_ON
FB
PR174
1.54K_0402_1%
VGA@
1
VGA@
1
PC142
4.7U_0603_6.3V6K
VGA@
FB=0.8V
2
EN
POK
3
4
1
8
7
VOUT
VOUT
2
VCNTL
VIN
VIN
2
2
PU10
6
5
9
1
2
1
1
B
2008/08/10
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW
2
+1.8VSP/+1.0VSGP
Rev
B
NELA5
Sheet
W ednesday, April 21, 2010
1
48
of
54
A
B
C
D
E
F
G
H
1
1
VGA_CORE
F=1/(75*e-12*44.2)=300K
Ipeak=33A Imax=23.1A Iocp=39.6A
Rsenmax=(3.2*1.3*35)/20=8.112 Kohm choose
Rsen=8.2Kohm
Iocpmin=(8.2*20)/(3.2*1.3)=39.5A
PL13
B+_core
DH_VCORE
BST_VCORE
1
VGA@
1 PR183 2
PR184 0_0603_5%
2
0_0603_5%
+5VS VGA@
PC166
2
VGA@
0.1U_0603_25V7K
1
BOOT
PVCC
PC168
2.2U_0603_6.3V6K
VGA@
4
VCC
LG
13
2
12
VGA@ PQ39
AO4726L_SO8
1
PGND
ISEN
PR190
ISEN_VCORE
1
11
VGA@ PQ40
AO4726L_SO8
PR191
@ 4.7_1206_5%
2
4
4
2
VGA@
3
2
1
2
+VGA_COREP
PC171
PR298
0_0402_5%
VGA@
PR297
1
@ 680P_0603_50V7K
VFB=0.6V
+
GCORE_SEN
2
GCORE_SEN
18
MAD@ PR197
68.1K_0402_1%
Rds(TYP)=2.3mohm;
Rds(max)=3.2mohm
+3VS
2
2
PC998
0.01U_0402_25V7K
@
2
1
VGA@
PR196
2
PAK@
PR197
43.2K_0402_1%
1
3
1
1
PR200 @
10K_0402_1%
PC175
4700P_0402_25V7K
3
VGA@
+3VS
2
PAK@
PR201
25.5K_0402_1%
S
1
MAD@ PR201
31.6K_0402_1%
PR199
10K_0402_5%
1
2
VGA@
2
G
2
2
2N7002W-T/R7_SOT323-3
PAK@
PR198
8.87K_0402_1%
2
VGA@
PQ41 D
VGA@
VGA@
PR211
10K_0402_5%
1 1
MAD@ PR198
9.53K_0402_1%
3
44.2K_0402_1%
1
2
1
PR195
VGA@
22K_0402_1%
PC174
2
VGA@
2200P_0402_25V7K
1
2
PC172
22P_0402_50V8J
1
1
1
2
0.1U_0402_10V7K
2
ESR=15 mohm
VGA@
PR193
4.99K_0402_1%
VGA@
PC170
VGA@
PC169
330U_D2_2.5VY_R15M
1
10_0402_5%
VGA@
2
10
VO
8.2K_0402_1%
9
FB
7
6
VGA@
FSET
EN
NC
5
VGA@
1
5
6
7
8
APW7138NITRL_SSOP16
2
20K_0402_1%
1
PL14
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
VGA@
1
PR177
DCR=2.2m OHM
2.2U_0603_6.3V6K
VGA@
DL_VCORE
1 2
@ PR187
10K_0402_5%
34,36,40,48 VGA_PWR_ON
4
1
2
2
7138_VCORE
4.7_0603_5% VGA@
1
2 PC167
14
7138_VCORE
PR186 2
TPCA8030-H_SOP-ADV8-5
PQ38 VGA@
1
UG
2
15
1
2
8
VGA@
PR185
0_0603_5%
3
2
1
+3VS
VIN
PHASE
3
PGOOD
GND
PU998
16
1
25 VGA_PWRGD
DH_VCORE-1
1
2
1
LX_VCORE
VGA@
PR301
10K_0402_5%
2
2
1
PC165
10U_1206_25V6M
2
1
VGA@
PC164
10U_1206_25V6M
1
2
VGA@
PC1000
2200P_0402_50V7K
+3VS
VGA@
5
6
7
8
2
3
2
1
1
HCB4532KF-800T90_1812
VGA@
5
B+
2
+3VS
2
@ PR212
PR210
10K_0402_5%
Core Voltage Level
GPU_VID1
Core Voltage Level
0.93 V
1
1
0.9 V
1
0
1.0 V
1
0
0.95 V
0
1
1.05V
0
1
1.0V
0
0
1.12 V
0
0
1.05 V
1
2
1
1
PR205 VGA@
10K_0402_1%
1
10K_0402_5%
VGA@
PC177
4700P_0402_25V7K
GPU_VID1 17
S
@ PR204
@PR204
10K_0402_1%
1
GPU_VID0
1
D
PQ60
2N7002W-T/R7_SOT323-3
VGA@
2
VGA@ PR203
10K_0402_1%
2
1
2
G
2
GPU_VID1
1
S
1
2
GPU_VID0
2
G
1
Madison
D
3
Park XT
VGA@
PR202
1
PQ42
2N7002W-T/R7_SOT323-3
VGA@
10K_0402_5%
3
VGA@
2
+3VS
@ PR213
PQ61
2N7002W-T/R7_SOT323-3
4
2
G
1
VGA@ PR206
10K_0402_1%
1
2
GPU_VID0 17
2
1
10K_0402_5%
D
4
VGA@
PR207 VGA@
10K_0402_1%
1
3
S
Compal Secret Data
Security Classification
2007/12/18
Issued Date
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VGA_COREP
Size
C
Date:
A
B
C
D
E
F
G
Compal Electronics, Inc.
Document Number
Rev
0.1
NELA5
Wednesday, April 21, 2010
Sheet
49
H
of
54
D
E
F
CPU_B+
PL15
HCB4532KF-800T90_1812
1
2
1
2
PR214
44.2K_0402_1%
PR215
2_0603_5%
1
2
1
1
27
PHASE1
26
UGATE1
25
BOOT1
PC202
1U_0603_16V6K
COMP0
PC211
180P_0402_50V8J
PR255
1K_0402_5%
2
1
PR256
2
1
PC216
2
1
1
3
2
1
PR251
10_0402_5%
1
VW1
PR254
PC213
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
2
1
COMP1
PC214
180P_0402_50V8J
PR258
1K_0402_5%
2
1
PR259
2
PC217
2
1
PC197
0.01U_0402_25V7K
2
1
PC196
10U_1206_25V6M
2
1
PC198
2200P_0402_50V7K
2
1
2
3
PC206
2200P_0402_50V7K
2
1
2
+CPU_CORE
1
PR247
16.2K_0402_1%
1 2
PR248
4.7_1206_5%
PC208
680P_0603_50V7K
1 PR249 2
4.02K_0402_1%
PC209
2
1
0.1U_0402_16V7K
1
PC215
1000P_0402_50V7K
PR260
6.81K_0402_1%
2
1
1
54.9K_0402_1% 1200P_0402_50V7K
1
54.9K_0402_1% 1200P_0402_50V7K
1
2
3
2
1
VSEN1
PC212
1000P_0402_50V7K
PR257
6.81K_0402_1%
2
1
5
4
TPCA8028-H_SOP-ADVANCE8-5
4
DIFF_1
2
@
PQ52
TPCA8028-H_SOP-ADVANCE8-5
PQ49
ISP1
1
PL18
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
2
@ PR252 1K_0402_1%
2
1
+CPU_CORE_0
Design Current: 25A
Max current: 35A
OCP_min:42A
1
3
2
1
PR243
2.2_0603_1%
BOOT1 1
2 1
PC204
10U_1206_25V6M
2
1
4
PHASE1
PC203
10U_1206_25V6M
2
1
PQ51
TPCA8030-H_SOP-ADV8-5
5
UGATE1
PC207
0.22U_0603_10V7K
2
PC201
2
1
0.1U_0402_16V7K
CPU_B+
LGATE1
2
3
2
1
LGATE0
2
28
1 PR235 2
4.02K_0402_1%
ISP0
LGATE1
29
1
3
2
1
30
PC200
680P_0603_50V7K
ISN0
4
PR232
16.2K_0402_1%
PR233
4.7_1206_5%
1
3
2
1
4
+5VS
LGATE0
31
10_0402_5%
1
+CPU_CORE
PR253
PC210
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
@
PQ47
PQ48
TPCA8028-H_SOP-ADVANCE8-5
ISN1
32
PC199
0.22U_0603_10V7K
1
33
PHASE0
1 2
UGATE0
+CPU_CORE
2
BOOT0
2
PL17
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
2
TPCA8028-H_SOP-ADVANCE8-5
35
34
PR229
2.2_0603_1%
BOOT0 1
2 1
5
BOOT_NB
PC195
10U_1206_25V6M
2
1
4
5
36
RTN1
PR246 10K_0402_1%
2
1
8 CPU_VDD1_FB_H
PC192
220U_D2_4VM
2
2
UGATE0
TP
VW1
ISN1
24
ISP1
23
ISN1
22
21
FB1
COMP1
BOOT1
ISP1
0_0402_5%
PR240
2
RTN0
+1.5VS
+
5
1
20
14
ISP0
13
PR241
2
1
10_0402_5%
2
TPCA8030-H_SOP-ADV8-5
5
UGATE1
VW0
PQ46
1
38
37
UGATE_NB
LGATE_NB
PHASE_NB
41
39
40
PGND_NB
OCSET_NB
43
42
COMP0
VSEN0
VW0
RTN_NB
PHASE1
8 CPU_VDD0_FB_L
DIFF_0
VSEN_NB
FB0
ISP0
ISN0
PR245
2
45
PGND1
VDIFF1
12
8 CPU_VDD1_FB_L
LGATE1
ISL6265IRZ-T_QFN48_6X6~D
VSEN1
11
+CPU_CORE
44
PVCC
VDIFF0
10
8 CPU_VDD0_FB_H
FSET_NB
46
LGATE0
OCSET
9
3
FB_NB
VCC
PGND0
RBIAS
8
PR239
1
95.3K_0402_1%
SVC
19
34 VR_ON
PHASE0
ENABLE
7
8
49
6
COMP_NB
47
48
VIN
5
SVD
RTN1
1
0_0402_5%
BOOT0
UGATE0
RTN0
2
PR236
4
BOOT_NB
PWROK
VSEN0
8 CPU_SVC
2
CPU_VDDNB_FB_L
PHASE0
PGOOD
15
PR242 0_0402_5%
2
1
16
0_0402_5%
2 PR244 1
17
0_0402_5%
2 PR250 1
18
1
0_0402_5%
3
ISN0
2
PR234
PR238
2
1
21.5K_0402_1%
1
1
2
8 CPU_SVD
2
PC193
680P_0603_50V7K
CPU_B+
PR226
10_0402_5%
OFS/VFIXEN
+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A
LGATE_NB
2
2
1
1
PR237 0_0402_5%
1
2
1
2
PR231 0_0402_5% @
25 H_PWRGD_L
1
PHASE_NB
PR224
0_0402_5%
1
34 VGATE
8
1
UGATE_NB
PU15
2
+
2
PHASE_NB
2
PR223
@ 105K_0402_1%
PR228
@ 105K_0402_1%
2
2
PR227
105K_0402_1%
B+
1
+CPU_CORE_NB
PR217
4.7_1206_5%
PC205
0.01U_0402_25V7K
2
1
1
PC194
0.1U_0603_16V7K
CPU_VDDNB_FB_H
PR221
13.7K_0402_1%
2
1
PR220
0_0402_5%
2
PR225
@ 10K_0402_1%
1 2
+CPU_CORE_NB
2
PR222
0_0402_5%
2
PC191
0.22U_0603_10V7K
2
PR219
2_0603_5%
+3VS
1
+5VS
1
+3VS
1
2
3
4
D2
D2
G1
S1
PL16
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2
PR230
0_0603_5%
BOOT_NB 1
2 1
PR218
10_0402_5%
1
2
1
G2
S2/D1
S2/D1
S2/D1
PHASE_NB
PR216
22K_0402_1%
2
1
2
PC190
0.1U_0603_16V7K
CPU_B+
8
7
6
5
H
AO4932_SO8
PC189
1000P_0402_50V7K
2
1
1
+5VS
UGATE_NB
1
PC184
1200P_0402_50V7K
PC1001
1000P_0402_50V7K
2
1
2
PC186
0.01U_0402_25V7K
2
1
PC185
10U_1206_25V6M
2
1
PQ50
1
PC187
2200P_0402_50V7K
2
1
LGATE_NB
PC183
33P_0402_50V8K
2
1
G
PC188
100U_25V_M
C
PC1002
680P_0402_50V7K
2
1
B
2
A
2
PR263 @
1K_0402_5%
2
PR262 @
1K_0402_5%
4
4
2008/04/16
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/03/12
Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
C
Date:
A
B
C
D
E
F
G
Document Number
Rev
1.0
NELA5
Wednesday, April 21, 2010
Sheet
50
H
of
54
5
4
3
2
9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP
D
)L[HG,VVXH
5HDVRQIRUFKDQJH
5HY
3*
Combine the 2N7002 main source
to TOSHIBA
0.1
49
Combine the PDTC115EU main source
to Philip
Combine the PDTC115EU main source
to Philip
0.1
Combine the 1SS355 main source
to PANJIT
Combine the 1SS355 main source
to PANJIT
Combine the 4148 main source
to PANJIT
3DJHRI
IRU3:5
'DWH
3KDVH
Change PQ35 to P/N SB000009610
2010/02/01
EVT_NELA5
49
Change PQ33,PQ34,PQ36 to P/N SB301150200
2010/02/01
EVT_NELA5
0.1
45
Change PD16 to P/N SC100001K00
2010/02/01
EVT_NELA5
Combine the 4148 main source
to PANJIT
0.1
49
Change PD13 to P/N SC100001Y80
2010/02/01
EVT_NELA5
Combine the BAS40CW main source
to PANJIT
Combine the BAS40CW main source
to PANJIT
0.1
49
2010/02/01
EVT_NELA5
Change PR78 to meet the spec.
200PPM/C==>75PPM/C
Change PR78 to meet the spec.
200PPM/C==>75PPM/C
0.1
46
2010/02/01
EVT_NELA5
Meet ACER timeline efficiency spec
Decrease the CISS of L/S MOSFET
change the value from 6430 to 3940 pF
0.1
47
2010/02/01
EVT_NELA5
Meet ACER timeline efficiency spec
2010/02/01
EVT_NELA5
Combine the 2N7002 main source
to TOSHIBA
0RGLI\/LVW
1
Change PD14 to P/N SCS00001200
D
C
C
B
Change PC169 cap. to 470uF
Change PR78 to SD00000S110
Change PQ28,PQ39,PQ40 to SB00000IP00(AO4726L)
Change the Choke from wire type to molding type
to improve the light load efficiency
0.1
47
Change PL6,PL8,PL14 to SH00000CN00(1.0uH)
Prevent the output OVP when system change
from F/L==>N/L
0.1
51
Change PC169 to SGA20471D20
2010/02/01
EVT_NELA5
0.2
46
Change PJ23 to 90ohm Bead
Add PR80 PC128 snubber
Add resistor for H/L MOSFET Driver
Change boost resistor to 2.2ohm
2010/03/15
DVT_NELA5
Change PJ23 to 90ohm Bead
Add PR80 PC128 snubber
Add resistor for H/L MOSFET Driver
Change boost resistor to 2.2ohm
Charger EMI solution
Change PJ14 to 90ohm Bead
Add PR100 PC78 snubber
Change boost resistor to 2.2ohm
1.1VALW EMI solution
0.2
47
Change PJ14 to 90ohm Bead
Add PR100 PC78 snubber
Change boost resistor to 2.2ohm
2010/03/15
DVT_NELA5
Change PJ15 to 90ohm Bead
Add PR110 PC88 snubber
Change boost resistor to 2.2ohm
1.5VP EMI solution
0.2
47
Change PJ15 to 90ohm Bead
Add PR110 PC88 snubber
Change boost resistor to 2.2ohm
2010/03/15
DVT_NELA5
ADD PC1001.PC1002 to CPU_B+ plane
for noise bypass
CPU_CORE EMI solution
0.2
52
ADD PC1001.PC1002 to CPU_B+ plane
for noise bypass
2010/03/15
DVT_NELA5
Prevent the MP2121 ESD shutdown issue
0.2
50
Change 1.8VP solution from MP2121
to SY8033
2010/03/15
DVT_NELA5
Change 1.8VP solution from MP2121
to SY8033
B
A
A
2007/09/20
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2008/09/20
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR (PWR)
Rev
0.1
NELA5
Sheet
W ednesday, April 21, 2010
1
51
of
54
5
4
D
3
2
1
R286 UMAHDMI@
715_0402_1%
2
1
R287 UMAHDMI@
715_0402_1%
2
1
D
ZZZ
2
1
R289 UMAHDMI@
2
1
R290 UMAHDMI@
715_0402_1%
PCB
715_0402_1%
PCB 047 LA-6141P REV0 M/B
2
1
R292 UMAHDMI@
2
1
R293 UMAHDMI@
2
1
R294 UMAHDMI@
2
1
R295 UMAHDMI@
715_0402_1%
LA6141MB Rev0: DA80000IF00
715_0402_1%
U9 X76@
715_0402_1%
715_0402_1%
H5TQ1G63BFR-12C_FBGA96
FOR UMA HDMI
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
1
L107
0_0603_5%
WOSP@
C1159
0_0402_5%
WOSP@
2
2
2
L108
0_0603_5%
WOSP@
1
C
1
C
W/O SP
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
HW PIR
Document Number
Rev
0.1
NELA5
Wednesday, April 21, 2010
Sheet
1
52
of
54
5
4
MODIFICATION LIST
3
2
PHASE
PAGE
DVT
P.33
Change JBT1 Conn.
NA
P.25
Delete R1076,R1077,R1078,R1079
Wlan clk port set to GPP5
P.30
Change Q80,Q81 part to SB570020110 , R1054 to SD028200380
NA
P.20
Add R1098 to GND on U5.AH29
AG28(FB_VDDC)/AH29(FB_GND) should route as differential pair
P.17
Delete R138,R139 ,R1068
Use R274,R275 ,R1069
P.17
U901,C1182,R970,Q74,Q75,U9with @
NA
Change Q19,Q22,Q25,Q27,Q29,Q40,Q42,Q62,Q64,Q70,Q71,Q80,Q81,Q84 to SB570020410
NA
Add R1099 - R1104
For Side port memory type detect, reserve for unknow function
Change Q58,Q59,D3,D7,D12,D10,D14,C11,C56 Main source
Q58,Q59 to SB934130020, D3,D7 to SCSH491D010, D12 to SC1N202U010, D10,D14 to SC300000B00, C11,C56 to SGA00002N80
P.34
Stuff R469,change R470 to 18k ohm
DVT Board ID
P.38
Add C1260,C1261 2.2uF_0603 Cap.
Audio codec (Ext. Mic)
Change Dual-Mosfet part to SB00000DH00
PANJIT Disqualitfy,(change Q5,Q34,Q47,Q51,Q6,Q82,Q30,Q33,Q38,Q73,Q74,Q75,Q9,Q39,Q44,Q46,Q57,Q11,Q83,Q26,Q41,Q77)
Add R1105,D3 with @
NA
Add/Reserve C1262,R1107,R1108,J2,J3,C1263,C1264
FOR EMI Request
P.37
Change R1007 to 30k ohm , C1198 to 1u_0402
Audio vender suggest
P.37
Reserve JTP1
NA
Set R136,R137,R1065,Q64,R1073,R143,R144,R145 to MUX@, R938 to UMAHDMI@
NA
P.30
Add R1109
ODD_EJECT PD Res.
P.34
Add R1110 with VGA@
for EC detect Muxless IGPU/DGPU mode
P.38
Change D56 to SCA00000200
FOR EMI Request
P.40
Update +3VSG circuit
For VGA thermal sensor function
P.19
Update C340,C274 part Description/value
NA
unstuff Q71,R117,R110,D2,R1096
NA
P.35
update Battery status LED circuit
Dual LED module
P.32
add PD Res on JMINI1.49
EC Request
P.37
Reserve Res. to Audio Codec
Reserve for Amp.
P.26
Set R1066 to MUXLESS@
MUXLESS Function
P.34
update U26(EC) version to E0,stuff R0185 and unstuff R1084
P.38
Change L121 to 0 Ohm resistor
1
PURPOSE
D
D
P.25
C
C
P.23
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
HW PIR
Document Number
Rev
0.1
NELA5
Wednesday, April 21, 2010
Sheet
1
53
of
54
5
4
MODIFICATION LIST
3
PHASE
PAGE
PVT
P.38
change R1024,R1025 to 39Ohm
Audio spec
P.40
change Q58 with VGA@
+3VSG circuit
P.19
change C340 to 330U
P.8
change C21 to 1.5pF
CPU Ext. thermal sensor temp carzy issue-short solution
P.8
Reserve CPU internal thermal circuit
Reserve Internal thermal sensor circuit
P.22
Update LVDS PWM switch circuit,set R253 to UMALVDS@
For LVDS PWM
P.35
Reverse JTP1 pin , reserve C1271(2.2u_0603) to TP_PWM with GND
TP module design
P.36
Remove SW3
ME interfere
P.32
Add R1129(0_0603) to Wlan
For Wlan power consumption measure
P.25
Add VGA_PWRGD circuit,change FN_RESERVE to VGA_PWRGD_R
AMD recomment
P.25
Reserve FN_RESERVE1 net
P.40
Update +3VSG circuit,Add 0 Ohm Res. to PWR SW MOSFET
P.23
R274,R275 with @,stuff R934,R935
P.37
Change R1019,R1020,R1022,J1,J2,J3 to 0.1u_0402 Cap.
For EMI request
P.38
change C1263,C1264 to 22pF
For EMI request
P.23
update JHDMI1 conn. footprint
2
1
PURPOSE
D
D
C
C
Pre MP
change SE100105Z80 to SE000000K80(1u/6.3v/0402 Y5V to X5R)
HW Standard Part
change SE103225Z80 to SE107225K80 (2.2u/6.3v/0603 Y5V to X5R)
HW Standard Part
P.34
Change R969,R961 to Bead(SM01000CP00)
For EMI request
P.23
Stuff R938
PX MUX HDMI DGPU/IGPU SW
P.34
Change R470 to 56k Ohm
Board ID
P.37
Reserve EC_MUTE# PD Res.(R1144), stuff D48,R1004
Audio vender suggestion
P.28
Add SB VDDCR_11_USB_S LDO circuit(Add U905,C678,L122), unstuff L73
AMD suggestion
P.40
Change R574 to 226k
Audio bobo sound issue,Fine tune +5VS sequence
P.16
Change U5 PN to SA00003MC70
update PARK PN to SA00003MC70(R3)
unstuff U904,C1272,R1133,Q70,Q73,R500,R502,Q85,Q86,R1119,R1120,C1267
For Pre MP , unstuff unused part (VGA_PWRGD AND gate,CPU internal thermal sensor circuit)
Change R251 to 10k
CMO panel +LCDVDD issue (garbage)
B
B
P.22
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
HW PIR
Document Number
Rev
0.1
NELA5
Wednesday, April 21, 2010
Sheet
1
54
of
54
www.s-manuals.com
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.5
Linearized : No
XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date : 2011:11:27 11:33:23+07:00
Creator Tool : PScript5.dll Version 5.2.2
Modify Date : 2014:10:13 21:43:28+03:00
Metadata Date : 2014:10:13 21:43:28+03:00
Producer : Acrobat Distiller 10.0.0 (Windows)
Format : application/pdf
Creator :
Title : Compal LA-6141P - Schematics. www.s-manuals.com.
Subject : Compal LA-6141P - Schematics. www.s-manuals.com.
Document ID : uuid:f448d8bb-c7b6-475d-a039-ffad3ef576e7
Instance ID : uuid:fd3ef595-19f0-4b2b-a1c5-52c76a2baf3f
Page Count : 55
Keywords : Compal, LA-6141P, -, Schematics., www.s-manuals.com.
Warning : [Minor] Ignored duplicate Info dictionary
EXIF Metadata provided by EXIF.tools
.