Compal LA 6161P Schematics. Www.s Manuals.com. R0.5 Schematics

User Manual: Motherboard Compal LA-6161P Fossil 2.0 UMA - Schematics. Free.

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

Cover Sheet

Custom

1 41Tuesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

Compal Confidential

Schematics Document

INTEL Auburndale BGA with IBEX core logic

2010-05-18

REV:0.5

LA-6161P

Fossil 2.0 UMA

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

Block Diagram

Custom

2 41Tuesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

File Name : LA-6161P

Compal Confidential

Clock Generator

SLG8SP585VTR

Fan Control

Mobile

BGA 1288pins

Power On/Off CKT.

SPI BUS

DC/DC Interface CKT.

RTC CKT.

Intel Ibex Peak M

Page 19

Power OK CKT.

page 28

Touch Pad CONN. Int.KBD

Page 29

Page 30

Page 25

LED Board

SMSC KBC 1098

10/100/1000 LAN

RTL8151DH-GR

RJ45 CONN

PCI-E BUS

LED

SATA HDD Connector

SATA0

Fossil 2.0 UMA

Page 11

Page 9

Page 4

Page 4,5,6,7,8

Page 21

Page 21

Page 11,12,13,14,15,16

CK505

BANK 2, 3

DDR3-SO-DIMM X 1DDR3 1066/1333MHz 1.5V

Single Channel

Page 11

USB2.0

Azalia

DMI X4

Arrandale CPU

WWAN

+SIM Card

Page 25

Page 25

LIS302DLTR

Page 22

Accelerometer

WLAN Card

Page 22

PCIE*1

Page 22

XDP Conn.

Page 4

1071pins

25mm*27mm

Page 27

SPI ROM 4 MB

USB*1

USB2.0

FDI

DDI

Display port

Page 17

Page 20

ONFI Interface

DDI_D

daughter board

LVDS

SPI BUS

MX25L6445EM2I-10G

USB conn x 3(For I/O)

page 24

page 26

BT(SoftBreeze) Conn USB x 1

Page 23

Audio Jack

Audio CKT

IDT 92HD80

sub/B Page 3

RealTek RTS5159

CardReader Controller

SD/MMC Slot

Page 18

USB x1(Camara)

Page 19

FPR conn x1

CRT

Page 19

Page 18

daughter board

sub/B Page 2

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

Notes List

Custom

3 41Tuesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

Voltage Rails

O

O

X

S3

+3VS

X

X

+3VALW

+5VS

S1

O

+CPU_CORE

OO

OO

X

X X

+VCCP

power

plane

O

O

O

O

O

X

S5 S4/ Battery only

X X X

+B

State

+1.5VS

+1.5V

S5 S4/AC & Battery

don't exist

S5 S4/AC

+5VALW

S0

O

O

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

V V

V

V

SENSOR

SMBCLK

SOURCE

SMSC1098

BATT THERMAL

SODIMM CLK CHIP

SMBUS Control Table

SML0CLK

SML0DATA

MINI CARD

SMBDATA

SMB_EC_CK1

SMB_EC_DA1

Calpella

SML1CLK

SML1DATA

NIC

X

X

X

X

X

X X

X

X X

X

X X

X

X

X

X

X X

X

X

V

V V

+1.05VS

CONN@ : means ME part.

Calpella

Calpella

XDP G-SENSOR

V

X

X

DOCK

V

X

X

X

+3VL +0.75V

+1.8VS

DEBUG@ : means just build when PCIE port 80 CARD function enable.

45@ : means just put it in the BOM of 45 level.

Install below 45 level BOM structure for ver. 0.1

Install below 43 level BOM structure for ver. 0.1

Remove before MP

+RTCVCC

O

O

O

O

O

O

V

L

Layout Notes

07/24 update

: Question Area Mark.(Wait check)

ULV@ : means just install for ULV CPU

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

XDP _DBRESET#

H_COM P3

H_COM P2

H_COM P1

H_COM P0

TP_SKTOCC#

H _C AT ERR#

H_PECI_ISO

H _ PROC HO T#_ D

H_THERM T RI P#_R

PM_EXTTS#1

PM_EXTTS#0

SM_RCOMP0

SM_RCO MP1 H _C AT ERR#

H _ PROC HO T#_ D

H _ CPUR ST #_R

XDP_TRST#

XDP_BPM#7

XDP_TDO

SM_RCOMP2

V DD PW R GOOD_R

PM_EXTTS#1

PM_P W RBT N#_R

XDP _DB RESET#_R

XDP_TCK

XDP_TRST#

H _C PURST#

XDP_TDI

XDP_TDO

H_C PU PW RG D_R

XDP_TMS

H_C PU PW RG D

CLK_CPU_ XDP#

CLK_CPU_ XDP

XDP _ RST#_R

PLT_RST#

XDP _DBRESET#

XDP _ RST#_R

XDP_BPM#5_R

XDP_BPM#4_R

XDP_BPM#7_R

XDP_BPM#6_R

XDP _PREQ#

XDP_TRST#

XDP _PR EQ#_R

SM_RCOMP2

CLK_CPU_ XDP#

H _C PURST#

H_C PU PW RG D

H _ CPUR ST #_R

H_P M_SYNC _R

V CC P WR GOOD_ 0

SYS_A G E NT_PWROK

V DD PW R GOOD_R

H _P WR GD_X DP _RH_ PW RGD_ XDP

PLT _ RST#_R

X DP _PRDY #_R

XDP_TDI

SM_RCOMP0

CLK_CPU_ XDP

XDP_TCK

XDP_BPM#1

XDP_TMS

XDP_BPM#0

XDP_BPM#4

XDP_BPM#6

XDP_TDO

XDP_BPM#2

PM_EXTTS#0

XDP _PRDY#

XDP_BPM#3

SM_RCOMP1

XDP_BPM#5

SM_D RAMRST#

CLK_EXP#

CLK_EXP

CLK_CPU_BCLK #

C LK _CPU_ BC LK

XDP_TDI_M

XDP_BPM#1

XDP_BPM#0

XDP_BPM#3

XDP_BPM#2

XDP_BPM#5

XDP_BPM#4

XDP_BPM#6

XDP_BPM#7

SM_D RAMRST#

H _P RO CHO T#

FAN_PWM

PM_P W RBT N#_R

H_PWRGD_XDP

XDP _PR EQ#_R

X DP _PRDY #_R

H _ PE CI<14 >

H_THERM T RIP#<14>

PM_EXTTS#1_R <9>

H _P RO C HO T#<3 7>

XDP _DBRESET# <13>

PM_P W RBTN#_R<13>

PLT_RST# <14,21,22,27>

CFG 0 <5>

CFG 1 <5>

CFG 2 <5>

CFG 3 <5>

CFG 8 <5>

CFG 9 <5>

CFG 6 <5>

CFG 7 <5>

H _ PM _S Y NC<1 3>

PM_DRAM_PWRGD<13>

VTTP W RGOOD<29>

BUF _PLT_RST#<14>

H _C P UP W R GD<14 >

CLK_DP# <12>

C LK _D P <12 >

CLK_CPU_BCLK # <14>

CLK_EXP <12>

CLK_EXP# <12>

CLK_CPU_BCLK <14>

C F G1 7<5>

C F G1 6<5>

C FG 1 3<5>

C FG 1 2<5>

C FG 1 5<5>

C FG 1 4<5>

C FG 1 0 <5>

CFG 4 <5>

CFG 5 <5>

C FG 1 1 <5>

V CC P_ 1.5V SP WRG D <29>

DRAM RST# <9>

P C H_ D DR _R ST < 14>

FAN_PWM<28>

+ V CC P

+ V CC P

+V C CP

+V C CP

+ V CC P

+3VS

+V C CP

+1.5V

+V C CP

+5VS

+3VS

+3VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0.5

Auburndale(1/5)-Thermal/XDP

C us t om

4 41Tuesday , May 18, 201 0

2008/09/15 2009/09/03

Compal Electronics, Inc.

DDR3 Compensation Signals

Processor Pullups

to power; PU to VCCP at power side also

from DDR

This shall place near XDP

Layout rule 10mil width trace

length < 0.5", spacing 20mil

Close to XDP

CPU XDP Connector

from power

DDR Pullups

0112 Remove uninstall parts

Add test points

Layout Note:Please these

resistors near Processor

ESD request to add

PWM Fan Control circuit

for RF

Intel S3 power reduction circuit for Calpella. 11/09

Intel S3 power reduction circuit for Calpella. 11/09

reserve for ESD, Compal SI 1/19

2nd Source :

SV - i5-540M CPU : 2.53G (K0)

SV - i5-450M CPU : 2.4G (K0)

SV - i3-350M CPU : 2.26G (K0)

SV- i3-370M CPU : 2.4G (K0)

ULV -U3400 CPU : 1.06G (K0)

Q52A

2N7002DW-7-F_SOT363-6

61

2

C3

0.1U_0402_10V6K@

1 2

R 14

0_0402_5%

1 2

R 22

0_0402_5%

1 2

R400_0402_5%

1 2

R35

750_0402_1%

12

C

B

E

Q26

PMBT3904_SOT23

1

2

3

R 19

0_0402_5%

1 2

J FA N 1

ACE S _85204-03001

C O NN @

1

1

2

2

3

3G1 4

G2 5

R 20 1K _0402_5%

@

1 2

JP4

SAMTE_BSH-030-01-L-D-A C O N N@

GND0

1

OBSFN_A0

3

OBSFN_A1

5

GND2

7

OBSDATA_A0

9

OBSDATA_A1

11

GND4

13

OBSDATA_A2

15

OBSDATA_A3

17

GND6

19

OBSFN_B0

21

OBSFN_B1

23

GND8

25

OBSDATA_B0

27

OBSDATA_B1

29

GND10

31

OBSDATA_B2

33

OBSDATA_B3

35

GND12

37

PWRGOOD/HOOK0

39

HOOK1

41

VCC_OBS_AB

43

HOOK2

45

HOOK3

47

GND14

49

SDA

51

SCL

53

TCK1

55

TCK0

57

GND16

59

GND1 2

OBSFN_C0 4

OBSFN_C1 6

GND3 8

OBSDATA_C0 10

OBSDATA_C1 12

GND5 14

OBSDATA_C2 16

OBSDATA_C3 18

GND7 20

OBSFN_D0 22

OBSFN_D1 24

GND9 26

OBSDATA_D0 28

OBSDATA_D1 30

GND11 32

OBSDATA_D2 34

OBSDATA_D3 36

GND13 38

ITPCLK/HOOK4 40

ITPCLK#/HOOK5 42

VCC_OBS_CD 44

RESET#/HOOK6 46

DBR#/HOOK7 48

GND15 50

TD0 52

TRST# 54

TDI 56

TMS 58

GND17 60

R1092

100K_0402_5%

@

12

R949.9_ 0402_1%

1 2

R45 68_0402_5%

1 2

R16

0_0402_5%

1 2

R28 0_0402_5%

1 2

R38

1K _0402_5%@

1 2

R 89 6

10K_0402_5%

1 2

R23 0_0402_5%

1 2

R220_0402_1%

1 2

R29 0_0402_5%@

1 2

R480_0402_5%

1 2

R 32

0_0402_5%@

1 2

T113P AD

R13 750_0402_1%

1 2

R749.9_ 0402_1%

1 2

R520_0402_1%

1 2

R891 0_0402_5%

12

Clocks

Misc Thermal Power Management

DDR3

Misc

JTAG & MBP

U1B

IN TEL_A UBURNDALE_1288

BCLK AK7

BCLK# AK8

BCLK_ITP K71

BCLK_ITP# J70

PEG_CLK# J21

PEG_CLK L21

DPLL_REF_SSCLK Y2

DPLL_REF_SSCLK# W4

CATERR#

N61

COMP1

AD69

PECI

N19

PROCHOT#

N67

THERMTRIP#

N17

RESET_OBS#

N70

VCCPWRGOOD_1

AM7

VCCPWRGOOD_0

Y67

SM_DRAMPW ROK

AM5

VTTPWRGOOD

H15

RSTIN#

G3

PM_EXT_TS#[0] AV66

PM_EXT_TS#[1] AV64

PRDY# U71

PREQ# U69

TCK T67

TMS N65

TRST# P69

TDI T69

TDO T71

TDI_M P71

TDO_M T70

DBR# W71

BPM#[0] J69

BPM#[1] J67

BPM#[2] J62

BPM#[3] K65

BPM#[4] K62

BPM#[5] J64

BPM#[6] K69

BPM#[7] M69

COMP0

AE66

PM_SYNC

M17

TAPPWRGOOD

Y70

PROC_DETECT

M71

SM_RCOMP[0] BV33

SM_RCOMP[1] BP39

SM_RCOMP[2] BV40

SM_DRAMRST# BJ12

COMP3

AD71

COMP2

AC70

T49 P AD

R 18

0_0402_5%

@

1 2

R12 1.5K_0402_1%

1 2

C1

0.1U_0402_16V4Z

@

1

2

R 59 51 _04 02_5%

1 2

R47 68_0402_5%@

1 2

R58 130_0402_1%

1 2

R 39 0_04 02_5%

1 2

R34

1K _0402_5%

1 2

R33

1.5K_0 402_1%

1 2

R21

0_0402_5%

1 2

R36

1K _0402_5%

1 2

R25 0_0402_5%

1 2

R30 0_0402_5%

1 2

T112P AD

R44 49.9_0402_1%

1 2

R31 0_0402_5%@

1 2

R 37

0_0402_5%

1 2

C6 470P_0402_50V7K

1 2

R 26

0_0402_5%

1 2

R10 51_0402_5%

1 2

R 17

0_0402_5%

1 2

R42 0_0402_5%

@

1 2

R24 0_0402_5%@

1 2

R1493 0_0402_5%@

1 2

R410_0402_5%

1 2

R1

10K_0402_5%

1 2

R3

10K_0402_5%

1 2

R52 100_0402_1%

1 2

R27 0_0402_5%@

1 2

R56 24.9_0402_1%

1 2

U50

TC7SH00FUF_ S SOP5

INB

1

INA

2O4

G

3P5

R 46 0_04 02_5%

@

1 2

C1316

47P_0402_50V8J

@

1

2

R1093

1K _0402_5%

12

T48P AD

R1494 0_0402_5%@

1 2

R 15

0_0402_5%

1 2

R430_0402_5%

1 2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

CF G14

CF G15

CF G16

CF G17

CFG 0

CFG 7

CF G10

CFG 8

CFG 4

CFG 6

CF G13

CFG 3

CFG 5

CFG 9

CF G12

CFG 2

CF G11

CFG 1

EXP_ICOMPI

EXP_RBIAS

FD I_ LS Y NC0

F DI _F S YN C 0

FD I_ LS Y NC1

F DI _F S YN C 1

F DI _INT

FDI_CT X_PRX_N0

FDI_CT X_PRX_N1

FDI_CT X_PRX_N2

FDI_CT X_PRX_N3

FDI_CT X_PRX_N4

FDI_CT X_PRX_N5

FDI_CT X_PRX_N6

FDI_CT X_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

CFG 0

CFG 3

CFG 4

DMI_CTX_PRX_P0<13>

DMI_CRX_PTX_P0<13>

DM I _CTX_PRX_N1<13>

DM I _CRX_PTX_N1<13>

DMI_CTX_PRX_P3<13>

DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_P2<13>

DM I _CTX_PRX_N0<13>

DM I _CRX_PTX_N3<13>

DMI_CRX_PTX_P2<13>

DM I _CTX_PRX_N3<13>

DMI_CTX_PRX_P1<13>

DM I _CRX_PTX_N0<13>

DM I _CRX_PTX_N2<13>

DMI_CRX_PTX_P1<13>

DM I _CTX_PRX_N2<13>

FDI_CT X _PRX_N0<13>

FDI_CT X _PRX_N1<13>

FDI_CT X _PRX_N2<13>

FDI_CT X _PRX_N3<13>

FDI_CT X _PRX_N4<13>

FDI_CT X _PRX_N5<13>

FDI_CT X _PRX_N6<13>

FDI_CT X _PRX_N7<13>

FDI_CTX_PRX_P0<13>

FDI_CTX_PRX_P1<13>

FDI_CTX_PRX_P2<13>

FDI_CTX_PRX_P3<13>

FDI_CTX_PRX_P4<13>

FDI_CTX_PRX_P5<13>

FDI_CTX_PRX_P6<13>

FDI_CTX_PRX_P7<13>

FDI _ F SY N C0<13>

FDI _ F SY N C1<13>

F D I_ I NT<13 >

F DI _ LS Y NC 0<13>

F DI _ LS Y NC 1<13>

C F G1 2<4>

C F G1 3<4>

C F G1 4<4>

C F G1 5<4>

C F G1 6<4>

C F G1 7<4>

CFG 0<4>

CFG 1<4>

CFG 2<4>

CFG 3<4>

CFG 4<4>

CFG 5<4>

CFG 6<4>

CFG 7<4>

CFG 8<4>

CFG 9<4>

C F G1 0<4>

C F G1 1<4>

VSS_NCTF6_R <8>

VSS_NCTF1_R <8>

VSS_NCTF2_R <8>

VSS_NCTF7_R <8>

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0.5

Auburndale(2/5)-DMI/PEG/FDI

C us t om

5 41Tuesday , May 18, 201 0

2008/09/15 2009/09/03

Compal Electronics, Inc.

ES1 sample need negative voltage

ES2 sample contact to GND

Not applicable for Clarksfield Processor

0: Bifurcation enabled

PCI-Express Configuration Select

CFG0

1: Single PEG

0: Lane Numbers Reversed

CFG3-PCI Express Static Lane Reversal

CFG3

1: Normal Operation

15 -> 0, 14 ->1, .....

0: Enabled; An external Display Port

CFG4-Display Port Presence

CFG4

1: Disabled; No Physical Display Port

device is connected to the Embedded

Display Port

attached to Embedded Display Port

CFG Straps for PROCESSOR

T52 P AD

T120 P A D

R64

49.9_ 0402_1%

1 2

T116 P A D

R69 3.01K_0402_1%@

1 2

R68 3.01K_0402_1%@

1 2

T117 P A D

PCI EXPRESS -- GRAPHICS

DMI Intel(R) FDI

U 1A

IN TEL_A UBURNDALE_1288

DMI_RX#[0]

F7

DMI_RX#[1]

J8

DMI_RX#[2]

K8

DMI_RX#[3]

J4

DMI_RX[0]

F9

DMI_RX[1]

J6

DMI_RX[2]

K9

DMI_RX[3]

J2

DMI_TX#[0]

H17

DMI_TX#[1]

K15

DMI_TX#[2]

J13

DMI_TX#[3]

F10

DMI_TX[0]

G17

DMI_TX[1]

M15

DMI_TX[3]

J11 DMI_TX[2]

G13

PEG_ICOMPI B12

PEG_ICOMPO A13

PEG_RBIAS B11

PEG_RCOMPO D12

PEG_RX#[0] G40

PEG_RX#[1] G38

PEG_RX#[2] H34

PEG_RX#[3] P34

PEG_RX#[4] G28

PEG_RX#[5] H25

PEG_RX#[6] H24

PEG_RX#[7] D29

PEG_RX#[8] B26

PEG_RX#[9] D26

PEG_RX#[10] B23

PEG_RX#[11] D22

PEG_RX#[12] A20

PEG_RX#[13] D19

PEG_RX#[14] A17

PEG_RX#[15] B14

PEG_RX[0] F40

PEG_RX[1] J38

PEG_RX[2] G34

PEG_RX[3] M34

PEG_RX[4] J28

PEG_RX[5] G25

PEG_RX[6] K24

PEG_RX[7] B28

PEG_RX[8] A27

PEG_RX[9] B25

PEG_RX[10] A24

PEG_RX[11] B21

PEG_RX[12] B19

PEG_RX[13] B18

PEG_RX[14] B16

PEG_RX[15] D15

PEG_TX#[0] N40

PEG_TX#[1] L38

PEG_TX#[2] M32

PEG_TX#[3] D40

PEG_TX#[4] A38

PEG_TX#[5] G32

PEG_TX#[6] B33

PEG_TX#[7] B35

PEG_TX#[8] L30

PEG_TX#[9] A31

PEG_TX#[10] B32

PEG_TX#[11] L28

PEG_TX#[12] N26

PEG_TX#[13] M24

PEG_TX#[14] G21

PEG_TX#[15] J20

PEG_TX[0] L40

PEG_TX[1] N38

PEG_TX[2] N32

PEG_TX[3] B39

PEG_TX[4] B37

PEG_TX[5] H32

PEG_TX[6] A34

PEG_TX[7] D36

PEG_TX[8] J30

PEG_TX[9] B30

PEG_TX[10] D33

PEG_TX[11] N28

PEG_TX[12] M25

PEG_TX[13] N24

PEG_TX[14] F21

PEG_TX[15] L20

FDI_TX#[0]

L2

FDI_TX#[1]

N7

FDI_TX#[2]

M4

FDI_TX#[3]

P1

FDI_TX#[4]

N10

FDI_TX#[5]

R7

FDI_TX#[6]

U7

FDI_TX#[7]

W8

FDI_TX[0]

K1

FDI_TX[1]

N5

FDI_TX[2]

N2

FDI_TX[3]

R2

FDI_TX[4]

N9

FDI_TX[5]

R8

FDI_TX[6]

U6

FDI_TX[7]

W10

FDI_FSYNC[0]

AC7

FDI_FSYNC[1]

AC9

FDI_INT

AB5

FDI_LSYNC[0]

AA1

FDI_LSYNC[1]

AB2

RESERVED

U1E

IN TEL_A UBURNDALE_1288

CFG[0]

AL4

CFG[1]

AM2

CFG[2]

AK1

CFG[3]

AK2

CFG[4]

AK4

CFG[5]

AJ2

CFG[6]

AT2

CFG[7]

AG7

CFG[8]

AF4

CFG[9]

AG2

CFG[10]

AH1

CFG[11]

AC2

CFG[12]

AC4

CFG[13]

AE2

CFG[14]

AD1

CFG[15]

AF8

CFG[16]

AF6

CFG[17]

AB7

RSVD34 AC69

RSVD35 AC71

RSVD38 R66

RSVD_NCTF[2] BV6

RSVD39 R64

RSVD_NCTF[3] BT5

RSVD_NCTF[4] BR5

RSVD_NCTF[1] BV8

RSVD_TP[0]

AU1

RSVD45 AV69

RSVD46 AK71

RSVD47 AN69

RSVD48 AP66

RSVD49 AH66

RSVD50 AK66

RSVD51 AR71

RSVD52 AM66

RSVD53 AK69

RSVD54 AU71

RSVD55 AT70

RSVD56 AR69

RSVD57 AU69

RSVD58 AT67

RSVD_NCTF[6]

E3

RSVD_NCTF[5]

F1

RSVD_NCTF[7]

C5

RSVD_NCTF[8]

A6

RSVD27

B9 RSVD26

A10

RSVD62 AV4

RSVD63 AU2

RSVD16

T2 RSVD15

T4

RSVD17

U1

RSVD18

V2

RSVD20

AW70 RSVD19

AV71

RSVD22

BB69 RSVD21

AY69

RSVD23

D8

RSVD24

B7

RSVD36 AA71

RSVD37 AA69

RSVD_TP[1] AN7

RSVD_TP[2] AP2

RSVD32 W66

RSVD33 W64

DC_TEST_BT3 BT3

DC_TEST_BT1 BT1

DC_TEST_BR71 BR71

DC_TEST_BR1 BR1

DC_TEST_E71 E71

DC_TEST_E1 E1

DC_TEST_C71 C71

DC_TEST_C69 C69

DC_TEST_C3 C3

DC_TEST_A71 A71

DC_TEST_A69 A69

DC_TEST_A68 A68

DC_TEST_A5 A5

RSVD64 BE69

RSVD65 BE71

DC_TEST_BT69 BT69

DC_TEST_BV5 BV5

DC_TEST_BV3 BV3

DC_TEST_BV1 BV1

DC_TEST_BT71 BT71

DC_TEST_BV71 BV71

DC_TEST_BV69 BV69

DC_TEST_BV68 BV68

T118 P A D

T50P AD T51 P AD

T119 P A D

R70 3.01K_0402_1%

1 2

R65

750_0402_1%

1 2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

D DR _ A_ D63

D DR _ A_ D62

DDR _A _D8

DDR _A _D3

DDR _A _D4

DDR _A _D7

DDR _A _D5

DDR _A _D6

D DR _ A_ D59

D DR _ A_ D58

D DR _ A_ D57

D DR _ A_ D56

D DR _ A_ D47

D DR _ A_ D46

D DR _ A_ D42

D DR _ A_ D43

D DR _ A_ D34

D DR _ A_ D39

D DR _ A_ D44

D DR _ A_ D45

D DR _ A_ D35

D DR _ A_ D41

D DR _ A_ D40

D DR _ A_ D38

D DR _ A_ D36

D DR _ A_ D37

D DR _ A_ D32

D DR _ A_ D33

D DR _ A_ D61

D DR _ A_ D60

DDR _A _D2

DDR _A _D1

DDR _A _D0

D DR _ A_ D55

D DR _ A_ D54

D DR _ A_ D51

D DR _ A_ D48

D DR _ A_ D50

D DR _ A_ D49

D DR _ A_ D52

D DR _ A_ D53

D DR _ A_ D31

D DR _ A_ D14

D DR _ A_ D15

D DR _ A_ D25

D DR _ A_ D24

D DR _ A_ D26

D DR _ A_ D27

D DR _ A_ D30

DDR _A _D9

D DR _ A_ D13

D DR _ A_ D12

D DR _ A_ D10

D DR _ A_ D11

D DR _ A_ D29

D DR _ A_ D28

D DR _ A_ D19

D DR _ A_ D20

D DR _ A_ D16

D DR _ A_ D21

D DR _ A_ D17

D DR _ A_ D22

D DR _ A_ D18

D DR _ A_ D23

DDR_A_M A 15

DD R _A_D QS 0

DD R _A_D QS 2

DD R _A_D QS 1

DD R _A_D QS 6

DD R _A_D QS 5

DD R _A_D QS 4

DD R _A_D QS 3

DD R _A_D QS 7

DD R_A _DQS#7

DD R_A _DQS#0

DD R_A _DQS#2

DD R_A _DQS#5

DD R_A _DQS#3

DD R_A _DQS#1

DD R_A _DQS#4

DD R_A _DQS#6

DD R_A _DM7

DD R_A _DM2

DD R_A _DM5

DD R_A _DM4

DD R_A _DM1

DD R_A _DM6

DD R_A _DM3

DD R_A _DM0

DDR_A_M A0

DDR_A_M A 14

DDR_A_M A5

DDR_A_M A4

DDR_A_M A1

DDR_A_M A2

DDR_A_M A3

DDR_A_M A9

DDR_A_M A7

DDR_A_M A6

DDR_A_M A 12

DDR_A_M A 13

DDR_A_M A8

DDR_A_M A 11

DDR_A_M A 10

D DR _A _D [0.. 63 ]<9 >

D DR _A _B S 0<9>

D DR _A _B S 1<9>

D DR _A _B S 2<9>

D DR _ A_ W E#<9>

D D R_ A_ RA S#<9>

D D R_ A_ CA S#<9>

DDR_A_M A [0..15] <9>

D DR _ A_ DM [ 0.. 7] <9>

M _C LK _DD R0 <9 >

M _C LK _DD R#0 <9>

DDR_CK E 0_DI M MA <9>

M _C LK _DD R1 <9 >

M _C LK _DD R#1 <9>

DDR_CK E 1_DI M MA <9>

DDR_CS 0_DI M M A# <9>

DDR_CS 1_DI M M A# <9>

M_ODT0 <9>

M_ODT1 <9>

D DR _ A_ DQ S #[ 0.. 7] < 9>

D DR _ A _D QS [ 0.. 7] <9>

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

Auburndale(3/5)-DDR3

C us t o m

6 4 1Tues day, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

DDR SYSTEM MEMORY - B

U1D

IN TEL_A UBURNDALE_1288

SB_BS[0]

BV43

SB_BS[1]

BV41

SB_BS[2]

BV24

SB_CAS#

BU46

SB_RAS#

BT40

SB_WE#

BT41

SB_CK[0] BU33

SB_CK[1] BV38

SB_CK#[0] BV34

SB_CK#[1] BU39

SB_CKE[0] BT26

SB_CKE[1] BT24

SB_CS#[0] BP46

SB_CS#[1] BT43

SB_ODT[0] BV45

SB_ODT[1] BU49

SB_DM[0] BB4

SB_DM[1] BL4

SB_DM[2] BT13

SB_DM[3] BP22

SB_DM[4] BV47

SB_DM[5] BV57

SB_DM[6] BU65

SB_DM[7] BF67

SB_DQS[4] BT50

SB_DQS#[4] BT52

SB_DQS[5] BU56

SB_DQS#[5] BV55

SB_DQS[6] BV62

SB_DQS#[6] BU63

SB_DQS[7] BJ69

SB_DQS#[7] BG69

SB_DQS[0] BD4

SB_DQS#[0] BE2

SB_DQS[1] BN4

SB_DQS#[1] BM3

SB_DQS[2] BV13

SB_DQS#[2] BU12

SB_DQS[3] BT17

SB_DQS#[3] BT19

SB_MA[0] BT34

SB_MA[1] BP30

SB_MA[2] BV29

SB_MA[3] BU30

SB_MA[4] BV31

SB_MA[5] BT33

SB_MA[6] BT31

SB_MA[7] BP26

SB_MA[8] BV27

SB_MA[9] BT27

SB_MA[10] BU42

SB_MA[11] BU26

SB_MA[12] BT29

SB_MA[13] BT45

SB_MA[14] BV26

SB_MA[15] BU23

SB_DQ[0]

BA2

SB_DQ[1]

AW2

SB_DQ[2]

BD1

SB_DQ[3]

BE4

SB_DQ[4]

AY1

SB_DQ[5]

BC2

SB_DQ[6]

BF2

SB_DQ[7]

BH2

SB_DQ[8]

BG4

SB_DQ[9]

BG1

SB_DQ[10]

BR6

SB_DQ[11]

BR8

SB_DQ[12]

BJ4

SB_DQ[13]

BK2

SB_DQ[14]

BU9

SB_DQ[15]

BV10

SB_DQ[16]

BR10

SB_DQ[17]

BT12

SB_DQ[18]

BT15

SB_DQ[19]

BV15

SB_DQ[20]

BV12

SB_DQ[21]

BP12

SB_DQ[22]

BV17

SB_DQ[23]

BU16

SB_DQ[24]

BP15

SB_DQ[25]

BU19

SB_DQ[26]

BV22

SB_DQ[27]

BT22

SB_DQ[28]

BP19

SB_DQ[29]

BV19

SB_DQ[30]

BV20

SB_DQ[31]

BT20

SB_DQ[32]

BT48

SB_DQ[33]

BV48

SB_DQ[34]

BV50

SB_DQ[35]

BP49

SB_DQ[36]

BT47

SB_DQ[37]

BV52

SB_DQ[38]

BV54

SB_DQ[39]

BT54

SB_DQ[40]

BP53

SB_DQ[41]

BU53

SB_DQ[42]

BT59

SB_DQ[43]

BT57

SB_DQ[44]

BP56

SB_DQ[45]

BT55

SB_DQ[46]

BU60

SB_DQ[47]

BV59

SB_DQ[48]

BV61

SB_DQ[49]

BP60

SB_DQ[50]

BR66

SB_DQ[51]

BR64

SB_DQ[52]

BR62

SB_DQ[53]

BT61

SB_DQ[54]

BN68

SB_DQ[55]

BL69

SB_DQ[56]

BJ71

SB_DQ[57]

BF70

SB_DQ[58]

BG71

SB_DQ[59]

BC67

SB_DQ[60]

BK70

SB_DQ[61]

BK67

SB_DQ[62]

BD71

SB_DQ[63]

BD69

DDR SYSTEM MEMORY A

U1C

IN TEL_A UBURNDALE_1288

SA_BS[0]

BT38

SA_BS[1]

BH38

SA_BS[2]

BF21

SA_CAS#

BK43

SA_RAS#

BL38

SA_WE#

BF38

SA_CK[0] BM34

SA_CK[1] BK36

SA_CK#[0] BP35

SA_CK#[1] BH36

SA_CKE[0] BF20

SA_CKE[1] BK24

SA_CS#[0] BH40

SA_CS#[1] BJ47

SA_ODT[0] BF43

SA_ODT[1] BL47

SA_DM[0] BB10

SA_DM[1] BJ10

SA_DM[2] BM15

SA_DM[3] BN24

SA_DM[4] BG44

SA_DM[5] BG53

SA_DM[6] BN62

SA_DM[7] BH59

SA_DQS[0] AY7

SA_DQS#[0] AY5

SA_DQS[1] BJ5

SA_DQS#[1] BJ7

SA_DQS[2] BL13

SA_DQS#[2] BN13

SA_DQS[3] BN21

SA_DQS#[3] BL21

SA_DQS[4] BK44

SA_DQS#[4] BH44

SA_DQS[5] BH51

SA_DQS#[5] BK51

SA_DQS[6] BM60

SA_DQS#[6] BP58

SA_DQS[7] BE64

SA_DQS#[7] BE62

SA_MA[0] BT36

SA_MA[1] BP33

SA_MA[2] BV36

SA_MA[3] BG34

SA_MA[4] BG32

SA_MA[5] BN32

SA_MA[6] BK32

SA_MA[7] BJ30

SA_MA[8] BN30

SA_MA[9] BF28

SA_MA[10] BH34

SA_MA[11] BH30

SA_MA[12] BJ28

SA_MA[13] BF40

SA_MA[14] BN28

SA_MA[15] BN25

SA_DQ[0]

AT8

SA_DQ[1]

AT6

SA_DQ[2]

BB5

SA_DQ[3]

BB9

SA_DQ[4]

AV7

SA_DQ[5]

AV6

SA_DQ[6]

BE6

SA_DQ[7]

BE8

SA_DQ[8]

BF11

SA_DQ[9]

BE11

SA_DQ[10]

BK5

SA_DQ[11]

BH13

SA_DQ[12]

BF9

SA_DQ[13]

BF6

SA_DQ[14]

BK7

SA_DQ[15]

BN8

SA_DQ[16]

BN11

SA_DQ[17]

BN9

SA_DQ[18]

BG17

SA_DQ[19]

BK15

SA_DQ[20]

BK9

SA_DQ[21]

BG15

SA_DQ[22]

BH17

SA_DQ[23]

BK17

SA_DQ[24]

BN20

SA_DQ[25]

BN17

SA_DQ[26]

BK25

SA_DQ[27]

BH25

SA_DQ[28]

BJ20

SA_DQ[29]

BH21

SA_DQ[30]

BG24

SA_DQ[31]

BG25

SA_DQ[32]

BJ40

SA_DQ[33]

BM43

SA_DQ[34]

BF47

SA_DQ[35]

BF48

SA_DQ[36]

BN40

SA_DQ[37]

BH43

SA_DQ[38]

BN44

SA_DQ[39]

BN47

SA_DQ[40]

BN48

SA_DQ[41]

BN51

SA_DQ[42]

BH53

SA_DQ[43]

BJ55

SA_DQ[44]

BH48

SA_DQ[45]

BJ48

SA_DQ[46]

BM53

SA_DQ[47]

BN55

SA_DQ[48]

BF55

SA_DQ[49]

BN57

SA_DQ[50]

BN65

SA_DQ[51]

BJ61

SA_DQ[52]

BF57

SA_DQ[53]

BJ57

SA_DQ[54]

BK64

SA_DQ[55]

BK61

SA_DQ[56]

BJ63

SA_DQ[57]

BF64

SA_DQ[58]

BB64

SA_DQ[59]

BB66

SA_DQ[60]

BJ66

SA_DQ[61]

BF65

SA_DQ[62]

AY64

SA_DQ[63]

BC70

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

H_V ID3

H_V ID0

H_V ID5

H_V ID2

H_V ID4

H_V ID1

H_V ID6

PM_DPRSLPVR_R

VSS_SENSE_VTT

VCCSENSE

VSSSENSE

VCCSENSE

VSSSENSE

+ VDD Q_CK

VTT0_72

VTT0_73

VTT0_72

VTT0_73

GFX V R _EN

H_VTT VID1

VCC_A XG_SENSE

GFX _DPRSLPVR

+V T T_ DDR

VSS_AXG_SENSE

GFX _DPRSLPVR

VCC_AXG_SENSE <39>

VSS_AXG_SENSE <39>

GFX V R_EN <39>

GFX V R_IMON <39>

H _V I D [0 .. 6]< 37>

PSI#<37>

P RO C_ DP RSLP VR<3 7>

IM V P_IMON<37>

VTT_SENSE<34>

VCCSENSE<37>

VSSSENSE<37>

GFX V R_VID_0 <39>

GFX V R_VID_1 <39>

GFX V R_VID_2 <39>

GFX V R_VID_3 <39>

GFX V R_VID_4 <39>

GFX V R_VID_5 <39>

GFX V R_VID_6 <39>

+G F X_CORE

+ V CC P

+ CP U _CO RE

+ V CC P

+ V CC P

+1.5VS_CPU_V DDQ

+V C AP2 +1.8VS

+ C PU _C OR E

+V C CP

+ V CC P

+V CAP0 +VCAP1

+1.5VS_CPU_V DDQ

+ V CC P

+ V CC P

+ V CC P

+ C PU _C OR E

+ CP U _CO RE

+V C AP0

+V C AP1

+ CP U _CO RE

+G F X_CORE

+G F X_CORE

+ V CC P

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0.5

Auburndale(4/5)-PWR

C us t om

7 41Tuesday , May 18, 201 0

2008/09/15 2009/09/03

Compal Electronics, Inc.

Close to CPU

Follow SCH check list

add 7pcs Caps to follow Design guide add 7pcs Caps to follow Design guide

for RF

for RF

for RF

12/05 HP

R72

0_0402_5%

12

C 6 52

1U_0402_6.3V6K

1

2

C46

10U_0805_6.3V6M

1

2

C1319

12P_0402_50V8J

@

1

2

C 3 83

1U_0402_6.3V6K

1

2

C 6 43

1U_0402_6.3V6K

1

2

C 3 81

1U_0402_6.3V6K

1

2

C22

1U_0402_6.3V6K

1

2

C34

1U_0402_6.3V6K

1

2

C 6 44

1U_0402_6.3V6K

1

2

C30

10U_0805_6.3V6M

1

2

C48

10U_0805_6.3V6M

1

2

R78 0_0402_5%

1 2

C 71

1U_0402_6.3V6K

1

2

C 6 15

1U_0402_6.3V6K

1

2

C1322

12P_0402_50V8J

@

1

2

C23

1U_0402_6.3V6K

1

2

C28

10U_0805_6.3V6M

1

2

C 52

47P_0402_50V8J

@

1

2

C 6 14

1U_0402_6.3V6K

1

2

C29

10U_0805_6.3V6M

1

2

C56

47P_0402_50V8J

@

1

2

C 2 14

1U_0402_6.3V6K

1

2

C 6 53

1U_0402_6.3V6K

1

2

C 6 13

1U_0402_6.3V6K

1

2

C 2 15

1U_0402_6.3V6K

1

2

C47

10U_0805_6.3V6M

1

2

C 2 12

1U_0402_6.3V6K

1

2

C 1 13

1U_0402_6.3V6K

1

2

POWER

CPU CORE SUPPLY

U1H

IN TEL_A UBURNDALE_1288

VCAP0_1 BD55

VCAP0_2 BD51

VCAP0_3 BD48

VCAP0_4 BB55

VCAP0_5 BB51

VCAP0_6 BB48

VCAP0_7 AY57

VCAP0_8 AY53

VCAP0_9 AY50

VCAP0_10 AW57

VCAP0_11 AW53

VCAP0_12 AW50

VCAP0_13 AU55

VCAP0_14 AU51

VCAP0_15 AU48

VCAP0_16 AR55

VCAP0_17 AR51

VCAP0_18 AR48

VCAP0_19 AN57

VCAP0_20 AN53

VCAP0_21 AN50

VCAP0_22 AL57

VCAP0_23 AL53

VCAP0_24 AL50

VCAP0_25 AK57

VCAP0_26 AK53

VCAP0_27 AK50

VCAP1_1 BD44

VCAP1_2 BD41

VCAP1_3 BD37

VCAP1_4 BB44

VCAP1_5 BB41

VCAP1_6 BB37

VCAP1_7 AY46

VCAP1_8 AY42

VCAP1_9 AY39

VCAP1_10 AW46

VCAP1_11 AW42

VCAP1_12 AW39

VCAP1_13 AU44

VCAP1_14 AU41

VCAP1_15 AU37

VCAP1_16 AR44

VCAP1_17 AR41

VCAP1_18 AR37

VCAP1_19 AN46

VCAP1_20 AN42

VCAP1_21 AN39

VCAP1_22 AL46

VCAP1_23 AL42

VCAP1_24 AL39

VCAP1_25 AK46

VCAP1_26 AK42

VCAP1_27 AK39

VCC_20

AB41

VCC_21

AA55

VCC_22

AA51

VCC_23

AA48

VCC_24

AA44

VCC_25

AA41

VCC_26

W55

VCC_27

W51

VCC_28

W48

VCC_29

W44

VCC_30

W41

VCC_31

U55

VCC_32

U51

VCC_33

U48

VCC_34

U44

VCC_35

U41

VCC_36

R55

VCC_37

R51

VCC_38

R48

VCC_39

R44

VCC_40

R41

VCC_41

P60

VCC_42

N55

VCC_43

N51

VCC_44

N48

VCC_45

N44

VCC_46

N42

VCC_47

M60

VCC_48

M51

VCC_49

M44

VCC_50

L55

VCC_51

K60

VCC_52

K51

VCC_53

K44

VCC_54

J55

VCC_55

H60

VCC_56

H51

VCC_57

H44

VCC_58

G60

VCC_59

G55

VCC_60

G51

VCC_61

G44

VCC_62

F55

VCC_63

E60

VCC_64

E57

VCC_65

E53

VCC_66

E50

VCC_67

E46

VCC_68

E42

VCC_69

D59

VCC_70

D57

VCC_71

D55

VCC_72

D54

VCC_73

D52

VCC_74

D50

VCC_75

D48

VCC_76

D47

VCC_77

D45

VCC_78

D43

VCC_79

B60

VCC_80

B56

VCC_81

B53

VCC_82

B49

VCC_83

B46

VCC_84

B42

VCC_85

A57

VCC_86

A54

VCC_87

A50

VCC_88

A47

VCC_89

A43

VCC_1

AF57

VCC_2

AF55

VCC_3

AF53

VCC_4

AF51

VCC_5

AF50

VCC_6

AF48

VCC_7

AF46

VCC_8

AF44

VCC_9

AF42

VCC_10

AF41

VCC_11

AD55

VCC_12

AD51

VCC_13

AD48

VCC_14

AD44

VCC_15

AD41

VCC_16

AB55

VCC_17

AB51

VCC_18

AB48

VCC_19

AB44

C 42

1U_0402_6.3V6K

1

2

C 66

1U_0402_6.3V6K

1

2

C57

47P_0402_50V8J

@

1

2

C374.7U_0603_6.3V6K

1

2

C1321

12P_0402_50V8J

@

1

2

R77 0_0402_5%

1 2

R 14 84 4. 7K _0 402 _5% @

1 2

C63

1U_0402_6.3V6K

1

2

C69

1U_0402_6.3V6K

1

2

C89

1U_0402_6.3V6K

1

2

C18

22U_0805_6.3V6M

1

2

C38

22U_0805_6.3V6M

1

2

C 6 46

1U_0402_6.3V6K

1

2

C16

1U_0402_6.3V6K

1

2

C60

10U_0805_6.3V6M

1

2

POWER

1.1V RAIL POWER

SENSE LINESCPU VIDS

1.8V

U 1F

IN TEL_A UBURNDALE_1288

VTT0_1 BF60

VTT0_2 BF59

VTT0_3 BD60

VTT0_4 BD59

VTT0_5 BB60

VTT0_6 BB59

VTT0_7 AY60

VTT0_8 AW60

VTT0_9 AW35

VTT0_10 AW33

VTT0_11 AW14

VTT0_12 AW12

VTT0_13 AU60

VTT0_14 AU59

VTT0_15 AU12

VTT0_16 AR60

VTT0_17 AR59

VTT0_18 AR12

VTT0_19 AN60

VTT0_20 AN59

VTT0_21 AN35

VTT0_22 AN33

VTT0_23 AN17

VTT0_24 AN15

VTT0_25 AN14

VTT0_26 AN12

VTT0_27 AM10

VTT0_28 AL60

VTT0_29 AL59

VTT0_30 AL17

VTT0_31 AL15

VTT0_32 AL14

VTT0_33 AL12

VTT0_34 AK35

VTT0_35 AK33

VTT0_36 AF39

VTT0_37 AF37

VTT0_38 AF35

VTT0_39 AF33

VTT0_40 AF32

VTT0_41 AF30

VTT0_42 AD39

VTT0_43 AD37

VTT0_44 AD35

VTT0_45 AD33

VTT0_46 AD32

VTT0_47 AD30

VTT0_48 W35

VTT0_49 W33

VTT0_50 W32

VTT0_51 W30

VTT0_52 W28

VTT0_53 W26

VTT0_54 W24

VTT0_55 W23

VTT0_56 U35

VTT0_57 U33

VTT0_58 U32

VTT0_59 U30

VTT0_60 U28

VTT0_61 U26

VTT0_62 U24

VTT0_63 U23

VTT0_64 R35

VTT0_65 R33

VTT0_66 R32

VTT0_67 R30

VTT0_68 R28

VTT0_69 R26

VTT0_70 R24

VTT0_71 R23

PSI#

F68

VID[0]

A61

VID[1]

D61

VID[2]

D62

VID[3]

A62

VID[4]

B63

VID[5]

D64

VID[6]

D66

PROC_DPRSLPVR

F66

ISENSE

A41

VCC_SENSE

F64

VSS_SENSE

F63

VTT_SENSE

N13

VSS_SENSE_VTT

R12

VCCPLL1

W39

VCCPLL2

W37

VCCPLL3

U37

VCCPLL4

R39

VCCPLL5

R37

VDDQ_CK[1]

BB14

VDDQ_CK[2]

BB12

VTT0_73 AN9

VTT0_72 AY10

VTT_SELECT[1]

AN1

C 5 33

1U_0402_6.3V6K

1

2

C27

22U_0805_6.3V6M

1

2

C 1 79

1U_0402_6.3V6K

1

2

C31

10U_0805_6.3V6M

1

2

C55

47P_0402_50V8J

@

1

2

C65

1U_0402_6.3V6K

1

2

C21

1U_0402_6.3V6K

1

2

C 6 12

1U_0402_6.3V6K

1

2

C72

1U_0402_6.3V6K

1

2

C1320

12P_0402_50V8J

@

1

2

C67

1U_0402_6.3V6K

1

2

C 6 23

1U_0402_6.3V6K

1

2

C1325

12P_0402_50V8J

@

1

2

C 2 13

1U_0402_6.3V6KZ

1

2

C 44

1U_0402_6.3V6K

1

2

C 5 34

1U_0402_6.3V6K

1

2

C85

1U_0402_6.3V6K

1

2

C20

1U_0402_6.3V6K

1

2

C 1 15

1U_0402_6.3V6K

1

2

R 14 83 4 .7 K_ 040 2_5%@

1 2

C91

1U_0402_6.3V6K

1

2

L32

0_0805_5%

12

C19

22U_0805_6.3V6M

1

2

C92

1U_0402_6.3V6K

1

2

C24

1U_0402_6.3V6K

1

2

R 7 00 4. 7K _0 40 2_5%

1 2

R76 100_0402_1%

1 2

R75 100_0402_1%

1 2

C 6 17

1U_0402_6.3V6K

1

2

C33

1U_0402_6.3V6K

1

2

+

C25

330U_B2_2.5VM_R15M

@

1

2

C 6 16

1U_0402_6.3V6K

1

2

C26

22U_0805_6.3V6M

1

2

C58

47P_0402_50V8J

@

1

2

POWER

GRAPHICS VIDs

GRAPHICS

DDR3 - 1.5V RAILS

PEG & DMI

SENSE

LINES

U 1G

IN TEL_A UBURNDALE_1288

GFX_VID[0] AF71

GFX_VID[1] AG67

GFX_VID[2] AG70

GFX_VID[3] AH71

GFX_VID[4] AN71

GFX_VID[5] AM67

GFX_VID[6] AM70

GFX_VR_EN AH69

GFX_DPRSLPVR AL71

GFX_IMON AL69

VAXG_SENSE AF12

VSSAXG_SENSE AF10

VAXG1

AN32

VAXG2

AN30

VAXG3

AN28

VAXG4

AN26

VAXG5

AN24

VAXG6

AN23

VAXG7

AN21

VAXG8

AN19

VAXG9

AL32

VAXG10

AL30

VAXG11

AL28

VAXG12

AL26

VAXG13

AL24

VAXG14

AL23

VAXG15

AL21

VAXG16

AL19

VAXG17

AK14

VAXG18

AK12

VAXG19

AJ10

VAXG20

AH14

VAXG21

AH12

VAXG22

AF28

VAXG23

AF26

VAXG24

AF24

VAXG25

AF23

VAXG26

AF21

VAXG27

AF19

VAXG28

AF17

VAXG29

AF15

VAXG30

AF14

VAXG31

AD28

VAXG32

AD26

VAXG33

AD24

VAXG34

AD23

VAXG35

AD21

VAXG36

AD19

VTT1_1

W21

VTT1_2

W19

VTT1_3

U21

VTT1_4

U19

VTT1_5

U17

VTT1_6

U15

VTT1_7

U14

VTT1_8

U12

VTT1_9

R21

VTT1_10

R19

VTT1_11

R17

VDDQ1 BU40

VDDQ2 BU35

VDDQ3 BU28

VDDQ4 BN38

VDDQ5 BM25

VDDQ6 BL30

VDDQ7 BJ38

VDDQ8 BH32

VDDQ9 BH28

VDDQ10 BG43

VDDQ11 BF16

VDDQ12 BF15

VDDQ13 BD35

VDDQ14 BD33

VDDQ15 BD32

VDDQ16 BD30

VDDQ17 BD28

VDDQ18 BD26

VAXG37

AD17

VTT1_21 R15

VDDQ19 BD24

VDDQ20 BD23

VDDQ21 BD21

VDDQ22 BD19

VDDQ23 BD17

VDDQ24 BD15

VDDQ25 BB35

VDDQ26 BB33

VDDQ27 BB32

VDDQ28 BB30

VDDQ29 BB28

VDDQ30 BB26

VDDQ31 BB24

VDDQ32 BB23

VDDQ33 BB21

VDDQ34 BB19

VDDQ35 BB17

VDDQ36 BB15

VCAP2_1

AK62

VCAP2_2

AK60

VCAP2_3

AK59

VCAP2_4

AH60

VCAP2_5

AH59

VCAP2_6

AF60

VCAP2_7

AF59

VCAP2_8

AD60

VCAP2_9

AD59

VCAP2_10

AB60

VCAP2_11

AB59

VCAP2_12

AA60

VCAP2_13

AA59

VCAP2_14

W60

VCAP2_15

W59

VCAP2_16

U60

VCAP2_17

U59

VCAP2_18

R60

VCAP2_19

R59

VTT0_DDR AW32

VTT0_DDR[1] AW30

VTT0_DDR[2] AW28

VTT0_DDR[3] AW26

VTT0_DDR[4] AW24

VTT0_DDR[5] AW23

VTT0_DDR[6] AW21

VTT0_DDR[7] AW19

VTT0_DDR[8] AW17

VTT0_DDR[9] AW15

VTT1_12 AD15

VTT1_13 AD14

VTT1_14 AD12

VTT1_15 AB12

VTT1_16 AA12

VTT1_17 W17

VTT1_18 W15

VTT1_19 W14

VTT1_20 W12

C 43

1U_0402_6.3V6K

1

2

C 2 18

1U_0402_6.3V6K

1

2

C 2 19

1U_0402_6.3V6K

1

2

R73

0_0402_5%

12

R74 0_0402_5%

12

C 3 80

1U_0402_6.3V6K

1

2

C59

10U_0805_6.3V6M

1

2

+

C1312

330U_D2_2.5VM_R6M

1

2

C 50

1U_0402_6.3V6K

1

2

C86

1U_0402_6.3V6K

1

2

C35

1U_0402_6.3V6K

1

2

C64

1U_0402_6.3V6K

1

2

C 3 82

1U_0402_6.3V6K

1

2

C90

1U_0402_6.3V6K

1

2

C88

1U_0402_6.3V6K

1

2

C17

1U_0402_6.3V6K

1

2

C62

10U_0805_6.3V6M

1

2

C 6 47

1U_0402_6.3V6K

1

2

C93

1U_0402_6.3V6K

1

2

C 53

47P_0402_50V8J

@

1

2

C68

1U_0402_6.3V6K

1

2

C 54

47P_0402_50V8J

@

1

2

C 6 49

1U_0402_6.3V6K

1

2

C70

1U_0402_6.3V6K

1

2

L31

0_0805_5%

12

C 1 14

1U_0402_6.3V6K

1

2

C32

1U_0402_6.3V6K

1

2

C 6 50

1U_0402_6.3V6K

1

2

C 94

1U_0402_6.3V6K

1

2

C 2 17

1U_0402_6.3V6K

1

2

C 14 0

1U_0402_6.3V6K

1

2

C 87

1U_0402_6.3V6K

1

2

C 2 21

1U_0402_6.3V6K

1

2

C49

10U_0805_6.3V6M

1

2

R 7 05 4. 7K _0 40 2_5%@

1 2

C 6 48

1U_0402_6.3V6K

1

2

T135

P AD

R1478 0_0402_5%

12

R1481 0_0402_5%

12

C 6 45

1U_0402_6.3V6K

1

2

C1326

12P_0402_50V8J

@

1

2

+

C1313

330U_D2_2.5VM_R6M

1

2

C 6 51

1U_0402_6.3V6K

1

2

C 2 16

1U_0402_6.3V6K

1

2

C36

1U_0402_6.3V6K

1

2

C61

10U_0805_6.3V6M

1

2

C 2 20

1U_0402_6.3V6K

1

2

C 51

47P_0402_50V8J

@

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

CRACK_BGA

CRACK_BGA

CRACK_BGA C RACK_B G A <16,28>

VSS_NCTF1_R<5>

VSS_NCTF6_R<5> VS S _NCT F 7_R<5>

VSS_NCTF2_R<5>

+ CP U _CO RE

+3VS

+3VS

+3VS +3VS

+ V CC P

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0.5

Auburndale(5/5)-GND/Bypass

C us t om

8 41Tuesday , May 18, 201 0

2008/09/15 2009/09/03

Compal Electronics, Inc.

Inside cavity

Under cavity

CPU CORE

BGA Ball Cracking Prevention and Detection

Under cavity

Add to follow design guide

Q4B

2N7002DW-T /R7_SOT363-6

3

5

4

C78

22U_0805_6.3V6M

1

2

C75

22U_0805_6.3V6M

1

2

C 3 07

1U_0402_6.3V6K

1

2

C 6 28

1U_0402_6.3V6K

1

2

+

C 97

330U_D2_2.5VM_R6M

1

2

Q3A

2N7002DW-T /R7_SOT363-6

61

2

Q4A

2N7002DW-T /R7_SOT363-6

61

2

C76

22U_0805_6.3V6M

1

2

C81

22U_0805_6.3V6M

1

2

C 3 02

1U_0402_6.3V6K

1

2

VSS

U1J

IN TEL_A UBURNDALE_1288

VSS202

AH53

VSS203

AH51

VSS204

AH50

VSS205

AH48

VSS206

AH46

VSS207

AH44

VSS208

AH42

VSS209

AH41

VSS210

AH39

VSS211

AH37

VSS212

AH35

VSS213

AH33

VSS214

AH32

VSS215

AH30

VSS216

AH28

VSS217

AH26

VSS218

AH24

VSS219

AH23

VSS220

AH21

VSS221

AH19

VSS222

AH17

VSS223

AH15

VSS224

AH4

VSS225

AG64

VSS226

AG9

VSS227

AG6

VSS228

AF69

VSS229

AF62

VSS230

AF1

VSS231

AE70

VSS232

AE64

VSS233

AD62

VSS234

AD57

VSS235

AD53

VSS236

AD50

VSS237

AD46

VSS238

AD42

VSS239

AD4

VSS240

AC67

VSS241

AC64

VSS242

AC10

VSS243

AC5

VSS244

AC1

VSS245

AB70

VSS246

AB62

VSS247

AB57

VSS248

AB53

VSS249

AB50

VSS250

AB46

VSS251

AB42

VSS252

AB39

VSS253

AB37

VSS254

AB35

VSS255

AB33

VSS256

AB32

VSS257

AB30

VSS258

AB28

VSS259

AB26

VSS260

AB24

VSS261

AB23

VSS262

AB21

VSS263

AB19

VSS264

AB17

VSS265

AB15

VSS266

AB14

VSS267

AB9

VSS268

AA66

VSS269

AA64

VSS270

AA62

VSS271

AA57

VSS272

AA53

VSS273

AA50

VSS274

AA46

VSS275

AA42

VSS276

AA39

VSS277

AA37

VSS278

AA35

VSS279

AA33

VSS280

AA32

VSS281

AA30

VSS282

AA28

VSS283

AA26

VSS284

AA24

VSS285

AA23

VSS286

AA21

VSS287

AA19

VSS288 AA17

VSS289 AA15

VSS290 AA14

VSS291 AA4

VSS292 W69

VSS293 W62

VSS294 W57

VSS295 W53

VSS296 W50

VSS297 W46

VSS298 W42

VSS299 W6

VSS300 W1

VSS301 V70

VSS302 U64

VSS303 U62

VSS304 U57

VSS305 U53

VSS306 U50

VSS307 U46

VSS308 U42

VSS309 U39

VSS310 U9

VSS311 U4

VSS312 T1

VSS313 R70

VSS314 R62

VSS315 R57

VSS316 R53

VSS317 R50

VSS318 R46

VSS319 R42

VSS320 R5

VSS321 P4

VSS322 N63

VSS323 N57

VSS324 N53

VSS325 N50

VSS326 N46

VSS327 N30

VSS328 N21

VSS329 N15

VSS330 M53

VSS331 M42

VSS332 M36

VSS333 M1

VSS334 L70

VSS335 L57

VSS336 L48

VSS337 L47

VSS338 L13

VSS339 K64

VSS340 K53

VSS341 K43

VSS342 K36

VSS343 K34

VSS344 K32

VSS345 K25

VSS346 K17

VSS347 K11

VSS348 K6

VSS349 K4

VSS350 J65

VSS351 J57

VSS352 J48

VSS353 J47

VSS354 J40

VSS355 J9

VSS356 H53

VSS357 H43

VSS358 H36

VSS359 H1

VSS360 G70

VSS361 G57

VSS362 G53

VSS363 G48

VSS364 G47

VSS365 G43

VSS366 G30

VSS367 G24

VSS368 G20

VSS369 G15

VSS370 F61

VSS371 F48

VSS372 F47

VSS373 F28

VSS374

F20

VSS375

F4

VSS376

E37

VSS377

E33

VSS378

E30

VSS379

E16

VSS380

E12

VSS381

D41

VSS382

D38

VSS383

D34

VSS384

D31

VSS385

D27

VSS386

D24

VSS387

D20

VSS388

D17

VSS389

D13

VSS390

D10

VSS391

D6

VSS392

B65

VSS393 B62

VSS394 B58

VSS395 B55

VSS396 B51

VSS397 B48

VSS398 B44

VSS399 A59

VSS400 A55

VSS401 A52

VSS402 A48

VSS403 A45

VSS404 A40

VSS405 A36

VSS406 A33

VSS407 A29

VSS408 A26

VSS409 A22

VSS410 A19

VSS411 A15

VSS412 A12

VSS413 A8

VSS415

B40

VSS

U 1I

IN TEL_A UBURNDALE_1288

VSS1

BU62

VSS2

BU58

VSS3

BU55

VSS4

BU51

VSS5

BU48

VSS6

BU44

VSS7

BU37

VSS8

BU32

VSS9

BU25

VSS10

BU21

VSS11

BU18

VSS12

BU14

VSS13

BU11

VSS14

BU7

VSS15

BP42

VSS16

BN64

VSS17

BN6

VSS18

BM70

VSS19

BM51

VSS20

BM44

VSS21

BM32

VSS22

BM24

VSS23

BM17

VSS24

BL57

VSS25

BL55

VSS26

BL48

VSS27

BL40

VSS28

BL28

VSS29

BL20

VSS30

BK63

VSS31

BK60

VSS32

BK53

VSS33

BK34

VSS34

BK10

VSS35

BJ64

VSS36

BJ21

VSS37

BJ9

VSS38

BJ1

VSS39

BH70

VSS40

BH57

VSS41

BH55

VSS42

BH47

VSS43

BH24

VSS44

BH20

VSS45

BH15

VSS46

BG51

VSS47

BG36

VSS48

BF62

VSS49

BF30

VSS50

BF13

VSS51

BF8

VSS52

BE70

VSS53

BE65

VSS54

BE9

VSS55

BE1

VSS56

BD57

VSS57

BD53

VSS58

BD50

VSS59

BD46

VSS60

BD42

VSS61

BD39

VSS62

BD14

VSS63

BB71

VSS64

BB62

VSS65

BB57

VSS66

BB53

VSS67

BB50

VSS68

BB46

VSS69

BB42

VSS70

BB39

VSS71

BB7

VSS72

BB1

VSS73

BA70

VSS74

AY71

VSS75

AY66

VSS76

AY62

VSS77

AY59

VSS78

AY55

VSS79

AY51

VSS80

AY48

VSS94 AY17

VSS95 AY15

VSS96 AY14

VSS97 AY12

VSS98 AY8

VSS99 AY4

VSS100 AW67

VSS101 AW62

VSS102 AW59

VSS103 AW55

VSS104 AW51

VSS105 AW48

VSS106 AW44

VSS107 AW41

VSS108 AW37

VSS109 AV9

VSS110 AV1

VSS111 AU70

VSS112 AU62

VSS113 AU57

VSS114 AU53

VSS115 AU50

VSS116 AU46

VSS117 AU42

VSS118 AU39

VSS119 AU35

VSS120 AU33

VSS121 AU32

VSS122 AU30

VSS123 AU28

VSS124 AU26

VSS125 AU24

VSS126 AU23

VSS127 AU21

VSS128 AU19

VSS129 AU17

VSS130 AU15

VSS131 AU14

VSS132 AU4

VSS133 AT64

VSS134 AT10

VSS135 AR62

VSS136 AR57

VSS137 AR53

VSS138 AR50

VSS139 AR46

VSS140

AR42

VSS141

AR39

VSS142

AR35

VSS143

AR33

VSS144

AR32

VSS145

AR30

VSS146

AR28

VSS147

AR26

VSS148

AR24

VSS149

AR23

VSS150

AR21

VSS151

AR19

VSS152

AR17

VSS153

AR15

VSS154

AR14

VSS155

AR4

VSS156

AR1

VSS157

AP70

VSS158

AP64

VSS159

AN62

VSS160

AN55

VSS161 AN51

VSS162 AN48

VSS163 AN44

VSS164 AN41

VSS165 AN37

VSS166 AN5

VSS167 AN4

VSS168 AM64

VSS169 AM8

VSS170 AL62

VSS171 AL55

VSS172 AL51

VSS173 AL48

VSS174 AL44

VSS175 AL41

VSS176 AL37

VSS177 AL35

VSS178 AL33

VSS179 AL1

VSS180 AK70

VSS181 AK64

VSS182 AK55

VSS183 AK51

VSS184 AK48

VSS185 AK44

VSS186 AK41

VSS187 AK37

VSS188 AK32

VSS189 AK30

VSS190 AK28

VSS191 AK26

VSS192 AK24

VSS193 AK23

VSS194 AK21

VSS195 AK19

VSS196 AK17

VSS197 AK15

VSS198 AJ70

VSS199 AH62

VSS200 AH57

VSS201 AH55

VSS81

AY44

VSS82

AY41

VSS83

AY37

VSS84

AY35

VSS85

AY33

VSS86

AY32

VSS87

AY30

VSS88

AY28

VSS89

AY26

VSS202 BV66

VSS203 BV64

VSS204 BT68

VSS205 BR69

VSS206 BR68

VSS207 BR3

VSS208 BN71

VSS209 BN1

VSS210 BL71

VSS211 BL1

VSS212 R14

VSS213 H71

VSS214 F71

VSS215 E69

VSS216 E68

VSS217 A66

VSS218 A64

VSS219 E5

VSS220 C68

VSS90 AY24

VSS91 AY23

VSS92 AY21

VSS93 AY19

+

C 98

330U_D2_2.5VM_R6M

1

2

C 1 06

22U_0805_6.3V6M

U LV @

1

2

C 18 9

1U_0402_6.3V6K

1

2

C 1 91

1U_0402_6.3V6K

1

2

C 6 36

1U_0402_6.3V6K

1

2

R81

100K_0402_5%

12

C 1 02

22U_0805_6.3V6M

U LV @

1

2

C 51 0

1U_0402_6.3V6K

1

2

C 1 41

1U_0402_6.3V6K

1

2

C 50 9

1U_0402_6.3V6K

1

2

C 1 03

22U_0805_6.3V6M

1

2

C 5 12

1U_0402_6.3V6K

1

2

C77

22U_0805_6.3V6M

1

2

+

C 96

330U_D2_2.5VM_R6M

U LV @

1

2

C 19 0

1U_0402_6.3V6K

1

2

C 51 5

1U_0402_6.3V6K

1

2

R80

100K_0402_5%

12

C 61 8

1U_0402_6.3V6K

1

2

C74

22U_0805_6.3V6M

U LV @

1

2

C79

22U_0805_6.3V6M

1

2

C 30 6

1U_0402_6.3V6K

1

2

C 1 09

22U_0805_6.3V6M

1

2

C 1 07

22U_0805_6.3V6M

1

2

C 5 13

1U_0402_6.3V6K

1

2

C 3 03

1U_0402_6.3V6K

1

2

C 1 92

1U_0402_6.3V6K

1

2

C 20 1

1U_0402_6.3V6K

1

2

C 6 19

1U_0402_6.3V6K

1

2

R82

100K_0402_5%

12

C83

22U_0805_6.3V6M

U LV @

1

2

C 1 42

1U_0402_6.3V6K

1

2

C 30 5

1U_0402_6.3V6K

1

2

C84

22U_0805_6.3V6M

U LV @

1

2

Q3B

2N7002DW-T /R7_SOT363-6

3

5

4

C 1 08

22U_0805_6.3V6M

1

2

C 1 10

22U_0805_6.3V6M

1

2

+

C 95

330U_D2_2.5VM_R6M

1

2

R79

100K_0402_5%

12

C 1 04

22U_0805_6.3V6M

1

2

C73

22U_0805_6.3V6M

1

2

C 30 4

1U_0402_6.3V6K

1

2

C 1 01

22U_0805_6.3V6M

1

2

C80

22U_0805_6.3V6M

1

2

C 5 08

1U_0402_6.3V6K

1

2

C82

22U_0805_6.3V6M

U LV @

1

2

C 1 05

22U_0805_6.3V6M

1

2

C 51 1

1U_0402_6.3V6K

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

+ V_ D DR _CP U_RE F

PM_EXTTS#1_R

SMB_CLK_S3

SMB_DATA_S3

D DR _ A_ D26

DDR _A _D6

D DR _ A_ D31

DDR _A _D2

DD R_A _DM0

D DR _ A_ D23

DD R _A_D QS 2

DDR _A _D8

D DR _ A_ D27

DDR _A _D7

DDR _A _D5

D DR _ A_ D17

DD R_A _DM3

D DR _ A_ D11

DD R_A _DQS#1

D DR _ A_ D24

D DR _ A_ D16

DD R_A _DQS#2

D DR _ A_ D10

DDR _A _D9

DD R _A_D QS 1

D DR _ A_ D20

DDR _A _D1

DD R_A _DQS#0

D DR _ A_ D12

DDR _A _D4

DD R _A_D QS 0

DDR _A _D3

DDR _A _D0

D DR _ A_ D13

D DR _ A_ D22

D DR _ A_ D14

D DR _ A_ D30

DD R_A _DM2

DD R_A _DM1

D DR _ A_ D25

D DR _ A_ D29

DD R _A_D QS 3

DRAM R ST#

D DR _ A_ D28

D DR _ A_ D19

D DR _ A_ D21

D DR _ A_ D15

D DR _ A_ D18

DD R_A _DQS#3

DDR_A_M A3

DDR_A_M A1

DDR_A_M A 10

D DR _A_B S0

DD R _A_W E#

DD R_A _CAS#

DDR_CS 1_DI M M A#

DDR_A_M A 13

D DR _A_B S2

DDR_CK E 0_DI M MA

DDR_A_M A 12

DDR_A_M A9

DDR_A_M A8

DDR_A_M A5

M _CLK_D DR0

M _CLK_D DR#0

DDR_CK E 1_DI M MA

DDR_A_M A 15

D DR _A_B S1

DDR_A_M A7

DDR_A_M A0

DD R_A _RAS#

DDR_CS 0_DI M M A#

DDR_A_MA6

M_ODT0

DDR_A_M A 14

DDR_A_M A4

M_ODT1

M _CLK_D DR1

M _CLK_D DR#1

DDR_A_MA11

DDR_A_M A2

DD R _A_D QS 6

D DR _ A_ D35

DD R _A_D QS 4

D DR _ A_ D42

D DR _ A_ D58

D DR _ A_ D61

D DR _ A_ D51

D DR _ A_ D33

D DR _ A_ D62

DD R_A _DM5

DD R_A _DQS#6

D DR _ A_ D44

DD R_A _DQS#4

D DR _ A_ D49

DD R_A _DM7

D DR _ A_ D56

D DR _ A_ D43

D DR _ A_ D34

D DR _ A_ D50

D DR _ A_ D32

D DR _ A_ D54

D DR _ A_ D45

D DR _ A_ D63

D DR _ A_ D36

DD R_A _DM6

D DR _ A_ D39

DD R _A_D QS 7

D DR _ A_ D46

DD R_A _DQS#5

DD R_A _DM4

D DR _ A_ D41

DD R_A _DQS#7

D DR _ A_ D55

DD R _A_D QS 5

D DR _ A_ D52

D DR _ A_ D40

D DR _ A_ D60

D DR _ A_ D38

D DR _ A_ D48

D DR _ A_ D59

D DR _ A_ D53

D DR _ A_ D47

D DR _ A_ D37

D DR _ A_ D57

SMB_DATA_S3

SMB_CLK_S3

PM_EXTTS#1_R

DDR_CK E 0_DI M MA<6>

D DR _A _B S 2<6>

M _ CL K_ DD R0<6>

M _C LK _DD R#0<6>

D DR _A _B S 0<6>

D DR _ A _W E #<6>

D DR _ A_ CA S #<6>

DDR_CS 1_DI M M A #<6>

DRAM RST# <4>

PM_EXTTS#1_R <4>

SMB_DATA_S3 < 10,12,22>

SMB_CLK_S3 <10,12,22>

DDR_CK E 1_DI MMA <6>

M _C LK _DD R1 <6>

M_CLK_DDR#1 <6>

DDR_A_B S 1 <6>

D D R_ A_ RA S# <6>

DDR_CS 0_DI M M A# <6>

M_ODT0 <6>

M_ODT1 <6>

D DR _A _D [0.. 63 ]<6>

D DR _ A_ DM [ 0.. 7]< 6>

D DR _ A _D QS [ 0.. 7]<6 >

D DR _ A _D QS #[ 0. .7 ]< 6>

DDR_A_M A [0..15]<6>

+1.5V +1.5V

+ V _D D R_ CP U_ RE F

+ V _D D R_ CP U_ RE F+V R EF _C A

+1.5V

+0.75VS

+1.5V

+0.75VS

+3VS

+3VS

+3VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

DDRIII-SODIMM SLOT1

C us t o m

9 4 1Tuesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

DDR3 SO-DIMM A

Layout Note:

Place near JD IMM1

Layout Note:

Place near JDIMB1

reserve for memory thermal sensor, HP.

open

R96

10K_0402_5%

1 2

R94 0_0402_5%

1 2

C 11 1

0.1U_0402_16V4Z

1

2

C 11 7

2.2U_0805_16V4Z

1

2

R 86

1K _0402_1%

12

C1338

0.1U_0402_16V4Z

@

1

2

C 12 6

10U_0603_6.3V6M

1

2

C 1 34

1U_0402_6.3V6K

1

2

R 95

10K_0402_5%

1 2

C1315

10U_0603_6.3V6M

1

2

C 12 4

10U_0603_6.3V6M

1

2

U59

NS_LM77CIMMX_3_MSOP8P

@

T_CRIT_A

3

SCL

2

SDA

1

A1 6

+VS 8

GND

4INT 5

A0 7

JDIMM1

FOX _AS0A626-U4SN-7F~D

C O NN @

VREF_DQ

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DM0

11

VSS

13

DQ2

15

DQ3

17

VSS

19

DQ8

21

DQ9

23

VSS

25

DQS1#

27

DQS1

29

VSS

31

DQ10

33

DQ11

35

VSS

37

DQ16

39

VSS 2

DQ4 4

DQ5 6

VSS 8

DQS0# 10

DQS0 12

VSS 14

DQ6 16

DQ7 18

VSS 20

DQ12 22

DQ13 24

VSS 26

DM1 28

RESET# 30

VSS 32

DQ14 34

DQ15 36

VSS 38

DQ20 40

DQ17

41

VSS

43

DQS2#

45

DQS2

47

VSS

49

DQ18

51

DQ19

53

VSS

55

DQ24

57

DQ25

59

VSS

61

DM3

63

VSS

65

DQ26

67

DQ27

69

VSS

71

CKE0

73

VDD

75

NC

77

BA2

79

VDD

81

A12/BC#

83

A9

85

VDD

87

A8

89

A5

91

VDD

93

A3

95

A1

97

VDD

99

CK0

101

CK0#

103

VDD

105

A10/AP

107

BA0

109

VDD

111

WE#

113

CAS#

115

VDD

117

A13

119

S1#

121

VDD

123

TEST

125

VSS

127

DQ32

129

DQ33

131

VSS

133

DQS4#

135

DQS4

137

VSS

139

DQ34

141

DQ35

143

VSS

145

DQ40

147

DQ41

149

VSS

151

DM5

153

VSS

155

DQ42

157

DQ43

159

VSS

161

DQ48

163

DQ49

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SA0

197

VDDSPD

199

DQ21 42

VSS 44

DM2 46

VSS 48

DQ22 50

DQ23 52

VSS 54

DQ28 56

DQ29 58

VSS 60

DQS3# 62

DQS3 64

VSS 66

DQ30 68

DQ31 70

VSS 72

CKE1 74

VDD 76

A15 78

A14 80

VDD 82

A11 84

A7 86

VDD 88

A6 90

A4 92

VDD 94

A2 96

A0 98

VDD 100

CK1 102

CK1# 104

VDD 106

BA1 108

RAS# 110

VDD 112

S0# 114

ODT0 116

VDD 118

ODT1 120

NC 122

VDD 124

VREF_CA 126

VSS 128

DQ36 130

DQ37 132

VSS 134

DM4 136

VSS 138

DQ38 140

DQ39 142

VSS 144

DQ44 146

DQ45 148

VSS 150

DQS5# 152

DQS5 154

VSS 156

DQ46 158

DQ47 160

VSS 162

DQ52 164

DQ53 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

EVENT# 198

SDA 200

SA1

201

VTT

203

GND1

205

SCL 202

VTT 204

BOSS1 206

GND2

207 BOSS2 208

C 1 35

10U_0805_6.3V6M

1

2

C 12 1

10U_0603_6.3V6M

1

2

C 13 7

0.1U_0402_16V4Z

1

2

C 11 2

2.2U_0805_16V4Z

1

2

C 12 5

10U_0603_6.3V6M

1

2

C 1 33

1U_0402_6.3V6K

1

2

C 1 31

1U_0402_6.3V6K

1

2

R1497

0_0402_5%

@

1 2

R 83

1K _0402_1%

12

C 1 32

1U_0402_6.3V6K

1

2

+

C 11 8

330U_B2_2.5VM_R15M

1

2

C 13 6

2.2U_0402_6.3V6M

1

2

C 12 2

10U_0603_6.3V6M

1

2

R1495

10K_0402_5%

@

1 2

C 12 3

10U_0603_6.3V6M

1

2

R1496

0_0402_5%

@

1 2

C1314

10U_0603_6.3V6M

1

2

C 11 6

0.1U_0402_16V4Z

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

CP U_S TOP#

SMB_CLK_S3

SMB_DATA_S3

R EF_0 /CP U_SEL

CK _P WRGD

CP U_S TOP#

CLK_BUF_DOT96#

CLK_BUF_DOT96

L_CLK _BUF_DO T96#

L_CLK _BUF_D OT96

CLK_DMI#

CLK_DMI

L_CLK _D MI#

C L K_BUF _CKSSCD

C L K_BUF _CKSSCD #

L_CLK _D MI

L_CLK _BUF_CKSSCD#

L _C LK _BUF _CKSSCD

CLK_14M _ PCH

CLK _XTAL_IN

CLK_XTAL_OUT

CK _P WRGD

R _C LK_B UF _BCL K CLK _B UF_B CLK

CLK_BUF_BCLK#

CLK _XTAL_IN

CLK_XTAL_OUT

R_CLK_B UF_B C LK#

R EF_0 /CP U_SEL

SMB_CLK_S3 <9, 12,22>

CLK_DMI<12>

CLK_DMI#<12>

C L K_ BU F_ CK S SC D<1 2>

C L K_ BU F_ CK S SC D#<1 2>

CLK_BUF_DOT96<12>

CLK_BUF_DOT96#<12>

SMB_DATA_S3 < 9,12,22>

CLK_14M _PCH <12>

C LK _E N # <37 >

CLK_BUF_BCLK# <12>

CLK_BUF_BCLK <12>

+1.05V S _CK505+1.05VS

+3VS_CK505

+3VS_CK505

+3VS_CK505

+3VS +3V S _CK505

+3VS_CK505

+3VS_CK505_G +3VS +1.5VS

+1.05V S _CK505

+3VS_CK505_G

+1.05V S _CK505

+3VS_CK505_G

+1.05VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

CLOCK GENERATOR

10 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

Close to U6 Close to U6

Close to U2 within 500mil

1

CPU_1PIN 30 CPU_0

0 133MHz

(Default)

133MHz

100MHz 100MHz

install R120 for low power CLKGENEMI request, Compal SI, 1/19

2nd Source :

IDT ICS9LVS3197BKLFT MLF 32P

REALTEK RTM890N-632-VB-GRT QFN 32P

C 1 65

0.1U_0402_16V4Z

1

2

C 1 68

0.1U_0402_16V4Z

1

2

C 1 67

0.1U_0402_16V4Z

1

2

R 1 14 0_ 04 02_ 5%

1 2

R 1 11 0_ 04 02_ 5%

1 2

R 14 66 1 0K _0 402_5 %

1 2

SLG 8LV595VTR_QFN_32P_5X5

U6

CPU_1# 19

SRC_1/SATA

10

CKPWRGD/PD# 25

DOT_96

3

CPU_0# 22

XTAL_OUT 27

VSS_REF 26

VDD_CPU 24

CPU_0 23

27MHZ

6XTAL_IN 28

VDD_27

5

27MHZ_SS

7

CPU_1 20

VSS_CPU 21

VDD_CPU_IO 18

VDD_DOT

1

REF_0/CPU_SEL 30

SDA 31

SCL 32

DOT_96#

4

VSS_SATA

9

SRC_1#/SATA#

11

VSS_SRC

12

SRC_2

13

SRC_2#

14

VDD_SRC_IO

15

VDD_SRC 17

VDD_REF 29

VSS_DOT

2

CPU_STOP#

16

TGND

33

VSS_27

8

R112 0_0402_5%

1 2

C 1 78

33P_0402_50V8J

1

2

C 17 2

10U_0805_10V4Z

1

2

C 1 64

10U_0805_10V4Z

1

2

C 1 70

47P_0402_50V8J

1

2

R 1 08 0_ 04 02_ 5%

1 2

R 10 7 33 _04 02_5%

1 2

R110 0_0402_5%

1 2

C 17 4

0.1U_0402_16V4Z

1

2

R 1 09 0_ 04 02_ 5%

1 2

R 1 06 0_ 04 02_ 5%

1 2

C 1 69

0.1U_0402_16V4Z

1

2

C 1 66

0.1U_0402_16V4Z

1

2

C 17 5

0.1U_0402_16V4Z

1

2

R 1 17

FBMA-L11-160808-301LMA20T_0603~D

1 2

C 17 1

10U_0805_10V4Z

1

2

R 14 65 1 0K _0 402_5 %@

1 2

R 11 5

10K_0402_5%

1 2

C 17 7

33P_0402_50V8J

1

2

R 1 13 0_ 04 02_ 5%

1 2

C 17 3

0.1U_0402_16V4Z

1

2

C 17 6

47P_0402_50V8J

1

2

Y114.31 8MHZ 16PF 7A14300083

12

Q7A

2N7002DW-7-F_SOT363-6

61

2

R 11 6

10K_0402_5%

1 2

R 1 20 0_ 06 03_ 5%

1 2

R 1 43 0_ 06 03_ 5%@

1 2

C 1 63

10P_0402_50V8C@

1

2

R 1 18 0_ 06 03_ 5%

1 2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

PCH_RTCX2

S M _IN TRUD ER# SI RQ

SB_SPKRPCH_INT V RMEN

HDA_BIT_CLK_CODEC

HDA _SDO UT_CODEC

PCH_JTAG_TDI

SATA_PRX_DTX_P0

SATA_PRX_DTX_N0

PCH _JTAG_TMS

S M_I NTR UDE R#

PCH_RTCX2

SATAICOMPIPCH_TRST#

SB_SPKR

PCH_JTAG_TCK

PCH_RTCX1

H DA _ SD IN0

H DA _S DOUT

HD D_H ALTLE D

S I RQ

KBC_SPI_CS0#

SATA_PTX_DRX_P0

HDA_RST#

KBC_SPI_CS1#

PCH_RTCX1

HDA_BIT_C LK

PCH_JTAG_TDO

SATA_PTX_DRX_N0

PCH_INT V RMEN

HDA _ SY N C

PCH_JTAG_TDO

PCH_JTAG_TCK

GPIO 21

PCH_RTCRST#

PCH_JTAG_TDI

GPIO 21

RT C1 RT C2

PCH_SRTCRS T#

AQUA W HITE_BATLED

PCH_GPIO 33AQUA W HITE_BATLED

GPIO 23

PCH _JTAG_TMS

H D A_ RS T# _C OD EC<2 3>

H D D_ HA LT LE D < 20>

KBC_SPI_CS 0#_R<28>

LP C_LF RAME# <27,28>

H DA _ S D IN 0<2 3>

KBC_SPI_CLK_R<28>

HDA_BIT_CLK_CODEC<23>

LP C_LA D 3 <27,28>

LP C_LA D 0 <27,28>

SATA_LED# <20>

H DA _ SD OUT _C OD EC<2 3>

LP C_LA D 2 <27,28>

KBC_SPI_SO<28>

KBC_SPI_CS 1#_R<28>

S I RQ < 27 ,28>

H DA _ S Y N C_ C O DE C<2 3>

SB_SPKR<23>

LP C_LA D 1 <27,28>

KBC_SPI_SI_R<28>

SATA_PTX_DRX_N0 <19>

SATA_PRX_DTX_N0 <19>

SATA_PTX_DRX_P0 <19>

SATA_PRX_DTX_P0 <19>

AQUA W HITE_BATLED#<25,28>

+ R TC VC C + 3VS

+1.05VS

+3VS

+3VS

+3VALW+3VALW+3VALW

+ R TC VC C

+ R TC VC C +V R EG _511 25

+3VS

+3VALW

+3VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(1/6)-HDA/JTAG/SATA

C us t o m

11 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

R158

R167

R165

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff100 ohm

200 ohm

100 ohm

200 ohm

100 ohm

200 ohm

100 ohm

200 ohm

51 ohm 5%51 ohm 5%

PCH _JTAG_TDO

ES1 AllES2

PCH _JTAG_TDI

PCH _JTAG_TCK

R157

R166

R156

R176

Uns tuff

100 ohm

51 ohm 5%

200 ohm

PCH _JTAG_TMS

Pre-Production Units Production

Ref.PCH Pin

L

+ -

W=20m ils

GPIO33 iAMT Enable /Disable

Hi

DisableLo

Enable (Default)

iAMT setting

for i-AMT setting. 11/20 HP

for i-AMT setting. 11/20 HP

11/20 HP

11/20 HP

for RF

C 1 88 47 P_ 04 02_ 50V8 J

@

1 2

R 1 66

100_0402_1%@

12

Y2

32.76 8KHZ_12.5PF_Q13MC14610002

OSC 4

OSC 1

NC

3

NC

2

R1459

330K_0402_5% @

1 2

RTCIHDA

SATA LPC

SPI JTAG

U7A

IB EXPEAK-M_FCBGA1071

RTCX1

B13

RTCX2

D13

INTVRMEN

A14

INTRUDER#

A16

HDA_BCLK

A30

HDA_SYNC

D29

HDA_RST#

C30

HDA_SDIN0

G30

HDA_SDIN1

F30

HDA_SDIN2

E32

HDA_SDO

B29

SATALED# T3

FWH0 / LAD0 D33

FWH1 / LAD1 B33

FWH2 / LAD2 C32

FWH3 / LAD3 A32

LDRQ1# / GPIO23 F34

FWH4 / LFRAME# C34

LDRQ0# A34

RTCRST#

C14

HDA_SDIN3

F32

HDA_DOCK_EN# / GPIO33

H32

HDA_DOCK_RST# / GPIO13

J30

SRTCRST#

D17

SATA0RXN AK7

SATA0RXP AK6

SATA0TXN AK11

SATA0TXP AK9

SATA1RXN AH6

SATA1RXP AH5

SATA1TXN AH9

SATA1TXP AH8

SATA2RXN AF11

SATA2RXP AF9

SATA2TXN AF7

SATA2TXP AF6

SATA3RXN AH3

SATA3RXP AH1

SATA3TXN AF3

SATA3TXP AF1

SATA4RXN AD9

SATA4RXP AD8

SATA4TXN AD6

SATA4TXP AD5

SATA5RXN AD3

SATA5RXP AD1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI AF15

SPI_CLK

BA2

SPI_CS0#

AV3

SPI_CS1#

AY3

SPI_MOSI

AY1

SPI_MISO

AV1

SATA0GP / GPIO21 Y9

SATA1GP / GPIO19 V1

JTAG_TCK

M3

JTAG_TMS

K3

JTAG_TDI

K1

JTAG_TDO

J2

JTAG_RST#

J4

SERIRQ AB9

SPKR

P1

SATAICOMPO AF16

R 1 26 20K _0 402_ 1%

1 2

C 1 82

18P_0402_50V8J

1

2

R 1 57

200_0402_5%@

12

T150P A D

T149P A D

R 1 58

200_0402_5%

@

1 2

R 1 25 10 K_ 04 02_5%@

12

R 1 21 1M _ 0402_ 5%

1 2

R 1 34 33 _04 02 _5%

1 2

C 21 0

1U_0603_10V4Z

1

2

T121P A D

C 18 3

1U_0603_10V4Z

1

2

R 1 48 0_ 04 02_ 5%

1 2

R 26 1

1K _0402_5%

1 2

R 1 37 33 _04 02 _5%

1 2

R 1 32 33 _04 02 _5%

1 2

R 14 61 100 K_ 040 2_5%

1 2

D36

CHN202UPT_S C-70

2

3

1

R1458

10K_0402_5%

@

1 2

R 1 24 33 0K _0 402_ 5%

1 2

R 1 30 33 _04 02 _5%

1 2

R 15 6

200_0402_5%

@

12

R 12 3 10 M_ 0402 _5%

1 2

JBATT1

LOTES_AAA-BAT-019-K01_2P

C O NN @

+

1-2

R 1 44 0_ 04 02_ 5%

1 2

C 18 0

1U_0603_10V4Z

1

2

T147P A D

R 14 5 10 K_ 0402_ 5%

1 2

T148P A D

R 1 22 10 K_ 04 02_5%

1 2

R 1 47

10K_0402_5%

1 2

C 18 1

18P_0402_50V8J

1

2

R 14 57 1 K_ 04 02_5%

1 2

C 1 86 47 P_ 04 02_ 50V8 J

@

1 2

R 1 76 51 _0 40 2_5%

1 2

R 1 67

100_0402_1%

@

12

R 14 60 1 0K _0 402_5%

12

R 1 27 20K _0 402_ 1%

1 2

Q86A

2N7002DWH 2N S OT363-6

61

2

C LR P 2

SHO RT PADS@

12

R 2 34 0_ 04 02_ 5%

1 2

C LR P 1

SHO RT PADS@

12

R 16 5

100_0402_1%

@

12

R142 37.4_0402_1%

1 2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

SMBCLK

SMBDATA S MB_DATA_S3

SMB_CLK_S3

SMBCLK

SMBDATA

PCIE_PTX_DRX_P6

SML0ALERT#

PCI E _PTX_DRX_N6

PCIE_PRX_DTX_P6

PCI E _PRX_DTX_N6

SML1CLK

SML1DATA

SML1ALERT#

XTAL25_IN

XTAL25_OUT

R _C LK_D P#

R _ CLK _DP

XCLK _RCOMP

R_C LK_EXP#

R_C LK_EXP

SML1CLK

SML0DATA

SML0ALERT#

SML0CLK

SMB_DATA_S3

CLK_PCIE _MCARD #_R

SMBCLKSMB_CLK_S3

SMBDATA

SML1ALERT#

C LK _P CIE_M CA RD_ R

SML1CLK

SML1DATA

SML1DATA

XTAL25_IN

XTAL25_OUT

CA P _CLK

CA P _ DAT

SML0CLK

SML0DATA

LI D _SW_P CH#

LI D _SW_P CH#

PCIE_PTX_DRX_P4

PCI E _PTX_DRX_N4

PCIE_PRX_DTX_P4

PCI E _PRX_DTX_N4

PCIE_PTX_DRX_P7

PCI E _PTX_DRX_N7

PCIE_PRX_DTX_P7

PCI E _PRX_DTX_N7

CLK_PCIE _MCARD 2_R

CLK_PCIE _MCARD 2#_R

SMB_DATA_S3 <9,10,22>

SMB_CLK_S3 <9, 10,22>

C LK _P C I_F B < 14>

CLK_14M _PCH <10>

CLK_EXP <4>

CLK_EXP# <4>

CLK_DMI# <10>

CLK_DMI <10>

CLK_BUF_BCLK < 10>

CLK_BUF_BCLK # <10>

CLK_BUF_DOT96 <10>

CLK_BUF_DOT96# <10>

C L K_ BU F_ CK S SC D < 10>

C L K_ BU F_ CK S SC D# <1 0>

PCI E _PTX_C_DRX_P6<21>

PCI E _PRX_DTX_N6<21>

PCI E _PTX_C_DRX_N6<21>

PCIE_PRX_DTX_P6<21>

CLK_DP# <4>

C LK _D P <4>

CLK_PCIE _MCARD<22>

CA P _DAT <28>

C LK RE Q _W LA N#<22>

CA P _CLK <28>

CLK_PCIE _MCARD#<22>

PCI E _PTX_C_DRX_P4<22>

PCI E _PRX_DTX_N4<22>

PCI E _PTX_C_DRX_N4<22>

PCIE_PRX_DTX_P4<22>

PCI E _PTX_C_DRX_P7<22>

PCI E _PRX_DTX_N7<22>

PCI E _PTX_C_DRX_N7<22>

PCIE_PRX_DTX_P7<22>

CLK_PCIE _MCARD2<22>

CLK_PCIE _MCARD 2#<22>

C LK R EQ _WWAN#<2 2>

+3VS

+3VALW

+1.05VS

+3VALW

+3VS

+3VS

+3VS

+3VALW

+3VALW

+3VALW

+3VL

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(2/6)-PCI-E/SMBUS/CLK

C us t o m

12 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

change from poert2 to port4. 11/20 HP

11/20 HP

11/21 HP

WLAN

GLAN

WWAN

WLAN

WWAN

12/05 HP

R1480 0_0402_5%

1 2

C198 0.1U_0402_16V4Z

1 2

R 1 88 2. 2K _0 40 2_5%

1 2

R208 0_0402_5%

1 2

R 1 87 2. 2K _0 40 2_5%

1 2

R 1 84 2. 2K _0 40 2_5%

1 2

C 19 9

18P_0402_50V8J

1

2

R197 0_0402_5%

1 2

C193 0.1U_0402_16V4Z

1 2

T56 P A D

R 1 85 10 K_ 04 02_5%

1 2

R 69 4

5.1K_0 402_5%

1 2

Q8B

2N7002DW-T /R7_SOT363-6

3

5

4

C1301 0.1U_0402_16V4Z

1 2

R209 0_0402_5%

1 2

R1479 0_0402_5%

1 2

R 7 01 10 K_ 04 02_5%

1 2

R 2 64

0_0402_5%

1 2

C 2 00

18P_0402_50V8J

1

2

PCI-E*

SMBus

Con troller

From CLK BUFFER PEG

Clock Flex

Link

U 7B

IB EXPEAK-M_FCBGA1071

PERN1

BG30

PERP1

BJ30

PERN2

AW30

PERP2

BA30

PERN3

AU30

PERP3

AT30

PERN4

BA32

PERP4

BB32

PERN5

BF33

PERP5

BH33

PERN6

BA34

PERP6

AW34

PERN7

AT34

PERP7

AU34

PERN8

BG34

PERP8

BJ34

PETN1

BF29

PETP1

BH29

PETN2

BC30

PETP2

BD30

PETN3

AU32

PETP3

AV32

PETN4

BD32

PETP4

BE32

PETN5

BG32

PETP5

BJ32

PETN6

BC34

PETP6

BD34

PETN7

AU36

PETP7

AV36

PETN8

BG36

PETP8

BJ36

SMBALERT# / GPIO11 B9

SMBCLK H14

SMBDATA C8

SML0CLK C6

SML0DATA G8

CLKOUT_PCIE0N

AK48

CLKOUT_PCIE0P

AK47

CLKOUT_PCIE1N

AM43

CLKOUT_PCIE1P

AM45

CLKOUT_PCIE2N

AM47

CLKOUT_PCIE2P

AM48

CLKOUT_PCIE3N

AH42

CLKOUT_PCIE3P

AH41

CLKOUT_PCIE4N

AM51

CLKOUT_PCIE4P

AM53

CLKOUT_PCIE5N

AJ50

CLKOUT_PCIE5P

AJ52

SML0ALERT# / GPIO60 J14

CL_CLK1 T13

CL_DATA1 T11

CL_RST1# T9

CLKIN_BCLK_N AP3

CLKIN_BCLK_P AP1

CLKIN_DMI_N AW24

CLKIN_DMI_P BA24

CLKIN_DOT_96N F18

CLKIN_DOT_96P E18

CLKIN_SATA_N / CKSSCD_N AH13

CLKIN_SATA_P / CKSSCD_P AH12

XTAL25_IN AH51

XTAL25_OUT AH53

REFCLK14IN P41

CLKIN_PCILOOPBACK J42

CLKOUT_PEG_A_N AD43

CLKOUT_PEG_A_P AD45

PEG_A_CLKRQ# / GPIO47 H1

PCIECLKRQ0# / GPIO73

P9

PCIECLKRQ1# / GPIO18

U4

PCIECLKRQ2# / GPIO20

N4

PCIECLKRQ3# / GPIO25

A8

PCIECLKRQ4# / GPIO26

M9

PCIECLKRQ5# / GPIO44

H6

CLKOUTFLEX0 / GPIO64 T45

CLKOUTFLEX1 / GPIO65 P43

CLKOUTFLEX2 / GPIO66 T42

CLKOUTFLEX3 / GPIO67 N50

CLKOUT_DMI_N AN4

CLKOUT_DMI_P AN2

PEG_B_CLKRQ# / GPIO56

P13

CLKOUT_PEG_B_P

AK51 CLKOUT_PEG_B_N

AK53

SML1ALERT# / GPIO74 M14

SML1CLK / GPIO58 E10

SML1DATA / GPIO75 G12

XCLK_RCOMP AF38

CLKOUT_DP_P / CLKOUT_BCLK1_P AT3

CLKOUT_DP_N / CLKOUT_BCLK1_N AT1

C197 0.1U_0402_16V4Z

1 2

T139 P A D

R 2 11 90 .9 _0 402_ 1%

1 2

R 2 00 10 K_ 04 02_5%

1 2

Q2B

2N7002DW-T /R7_SOT363-6

3

5

4

R 1 89 2. 2K _0 40 2_5%

1 2

R 1 91 2. 2K _0 40 2_5%

1 2

R 2 63

0_0402_5%

1 2

T55 P A D Y3

25MHZ_20PF_7A25000012

1 2

R 2 02 10 K_ 04 02_5%

1 2

R196 0_0402_5%

1 2

R195 0_0402_5%

1 2

R 1 83 10 K_ 04 02_5%

1 2

R 2 05 10 K_ 04 02_5%

1 2

C1302 0.1U_0402_16V4Z

1 2

R 2 13 10 K_ 04 02_5%

1 2

R 19 2 10 K_ 0402_ 5%

1 2

C194 0.1U_0402_16V4Z

1 2

R 1 86 2. 2K _0 40 2_5%

1 2

R 19 4 10 K_ 0402_ 5%

1 2

Q8A

2N7002DW-T /R7_SOT363-6

6 1

2

T140 P A D

R 69 5

5.1K_0 402_5%

1 2

R 19 9 10 K_ 0402_ 5%

1 2

R198 0_0402_5%

1 2

Q2A

2N7002DW-T /R7_SOT363-6

61

2

R 14 62 10K _0 402 _5%

1 2

R 21 0 1M _0 402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DM I _CTX_PRX_N2

DM I _CRX_PTX_N0

DM I _CRX_PTX_N1

DM I _CRX_PTX_N2

DM I _CRX_PTX_N3

DMI_CRX_PTX_P0

DMI_CRX_PTX_P1

DMI_CRX_PTX_P2

DMI_CRX_PTX_P3

DM I _CTX_PRX_N1

DM I _CTX_PRX_N0

DM I _CTX_PRX_N3

DMI_CTX_PRX_P1

DMI_CTX_PRX_P2

DMI_CTX_PRX_P0

DMI_CTX_PRX_P3

DM I _IRCO MP

M_P W R OK

AUX P WROK

PM_DRAM_PWRGD

LO W _B AT_R

IB EX_R#

PCI E _WA KE#

P M_C LKRUN#

SLP_S5#

SLP _LAN#

DA C_ I RE F

SYS_RS T#

SLP _LAN#

IB EX_R#

LO W _B AT_R

PCI E _WA KE#

SUS _CLK

FDI_CT X_PRX_N0

FDI_CT X_PRX_N1

FDI_CT X_PRX_N2

FDI_CT X_PRX_N3

FDI_CT X_PRX_N4

FDI_CT X_PRX_N5

FDI_CT X_PRX_N6

FDI_CT X_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

F DI _INT

F DI _F S YN C 0

F DI _F S YN C 1

FD I_ LS Y NC0

FD I_ LS Y NC1

DP D_ H PD

AC_PRE SENT

SLP_S4#

SLP_S5#

SLP_S3#

VGATE

DPD_TXP1

DP D_A UX

DP D_A UX#

DP D_ TXN0

DPD_TXP0

VGATE

D DC 2_ C LK

D DC 2_D AT A

SYS_RS T#

P M_C LKRUN#

M_RED

M_BLUE

M_G RE EN

3V DD C CL

3V DD C DA

CRT _H SY N C

C RT _ VS YN C

DPD_TXP3

DP D_ TXN3

DPD_TXP2

DP D_ TXN2

DP D_ TXN1

PM_P W RBTN#_R<4>

O N/ OF FB TN #<2 5,28 >

DM I _CRX_PTX_N0<5>

DM I _CTX_PRX_N0<5>

DM I _CTX_PRX_N1<5>

DM I _CTX_PRX_N2<5>

DM I _CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>

DMI_CTX_PRX_P1<5>

DMI_CTX_PRX_P2<5>

DMI_CTX_PRX_P3<5>

DM I _CRX_PTX_N1<5>

DM I _CRX_PTX_N2<5>

DM I _CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>

DMI_CRX_PTX_P1<5>

DMI_CRX_PTX_P2<5>

DMI_CRX_PTX_P3<5>

XDP _DBRESET#<4>

VGATE<37>

PM_RSMRST#<28>

PM_DRAM_PWRGD<4>

AC_PRESENT<28>

PCI E _WAKE# <21,22>

P M _CL KR UN# <28>

H _ PM _S Y NC <4>

SLP_S4# <30,36>

SLP_S3# <21,23,28, 29,30,32,34,35>

R P GO OD<33>

FDI_CT X _PRX_N0 <5>

FDI_CT X _PRX_N1 <5>

FDI_CT X _PRX_N2 <5>

FDI_CT X _PRX_N3 <5>

FDI_CT X _PRX_N4 <5>

FDI_CT X _PRX_N5 <5>

FDI_CT X _PRX_N6 <5>

FDI_CT X _PRX_N7 <5>

FDI_CTX_PRX_P0 <5>

FDI_CTX_PRX_P1 <5>

FDI_CTX_PRX_P2 <5>

FDI_CTX_PRX_P3 <5>

FDI_CTX_PRX_P4 <5>

FDI_CTX_PRX_P5 <5>

FDI_CTX_PRX_P6 <5>

FDI_CTX_PRX_P7 <5>

F DI _ IN T <5>

F D I_ F S Y N C0 < 5>

F D I_ F S Y N C1 < 5>

F DI _ LS Y NC 0 <5>

F DI _ LS Y NC 1 <5>

IN V _PWM<18>

ENABLT<18>

E NA V DD<18>

SUS _PWR_A C K<28>

DP D_TXN0 <17>

DPD_TXP0 <17>

DP D_TXN1 <17>

DPD_TXP1 <17>

DP D_TXN2 <17>

DPD_TXP2 <17>

DP D_TXN3 <17>

DPD_TXP3 <17>

D P D_ H P D <17 >

DP D_AUX# <17>

DP D_AUX <17>

D P D_C TR LCL K < 17>

DP D_CTRLDATA <17>

P G D _I N<2 8,37>

LV DS_ACLK N<18>

LV DS_ACLKP<18>

LV DS_A0N<18>

LV DS_A1N<18>

LV DS_A2N<18>

LV DS_A0P<18>

LV DS_A1P<18>

LV DS_A2P<18>

D DC 2_ DA TA<1 8>

D DC 2 _ CL K< 18>

C RT _ V S YN C< 19>

3 V DD C DA< 19>

3 V DD C CL<1 9>

M_BLUE<19>

M_G REEN< 19>

M_RED<19>

C RT _ HS Y NC<19>

+1.05VS

+3VS

+3VALW

+3VS

+3VS

+3VALW

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(3/6)-DMI/GPIO/LVDS

C us t o m

13 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

Close PCH and mini space 20mil

Display Port B

SDVO

Display Port C

delete R84, R66,R67

11/20 HP

11/20 HP

R 2 37 1 0K _0 402_5 %

1 2

R 2 43 1 0K _0 402_5 %

1 2

R 23 5 10 0K _04 02_5%

1 2

R 24 2 10 K_ 04 02_5%@

1 2

R1467

10K_0402_5%

1 2

R 7 72 10 K_ 04 02_5 %

1 2

T58 P AD

T57P AD

R 2 36 1 0K _0 402_5 %

1 2

R 24 0 10 K_ 04 02_5%@

1 2

R 2 25 10 K_ 04 02_5%

1 2

R 22 6

2.2K_0402_5%

R 2 46 1 0K _0 402_5 %

1 2

R 2 31 0_ 04 02_ 5%

1 2

R 7 71 10 K_ 04 02_5 %

1 2

T144 P A D

R 40 8 1K _0 402_5 %

1 2

R 2 45 1 K_ 04 02_5%

1 2

R 2 20 49 .9 _0 402_ 1%

1 2

R 7 73 2. 37 K_ 04 02_1%

1 2

R 2 41 1 0K _0 402_5 %@

1 2

R 2 28 0_ 040 2_5%

1 2

R 22 7

2.2K_0402_5%

R 2 24 0_ 04 02_ 5%

1 2

R 2 39 1 0K _0 402_5 %

1 2

R 24 4 10 K_ 04 02_5%@

1 2

R 2 38 1 0K _0 402_5 %@

1 2

R 2 29 10 K_ 04 02_5 %

1 2

DMI

FDI

System Power Management

U7C

IB EXPEAK-M_FCBGA1071

DMI0RXN

BC24

DMI1RXN

BJ22

DMI2RXN

AW20

DMI3RXN

BJ20

DMI0RXP

BD24

DMI1RXP

BG22

DMI2RXP

BA20

DMI3RXP

BG20

DMI0TXN

BE22

DMI1TXN

BF21

DMI2TXN

BD20

DMI3TXN

BE18

DMI0TXP

BD22

DMI1TXP

BH21

DMI2TXP

BC20

DMI3TXP

BD18

DMI_ZCOMP

BH25

DMI_IRCOMP

BF25

FDI_RXN0 BA18

FDI_RXN1 BH17

FDI_RXN2 BD16

FDI_RXN3 BJ16

FDI_RXN4 BA16

FDI_RXN5 BE14

FDI_RXN6 BA14

FDI_RXN7 BC12

FDI_RXP0 BB18

FDI_RXP1 BF17

FDI_RXP2 BC16

FDI_RXP3 BG16

FDI_RXP4 AW16

FDI_RXP5 BD14

FDI_RXP6 BB14

FDI_RXP7 BD12

FDI_FSYNC0 BF13

FDI_FSYNC1 BH13

FDI_LSYNC0 BJ12

FDI_LSYNC1 BG14

FDI_INT BJ14

PMSYNCH BJ10

TP23 N2

SLP_M# K8

SLP_S3# P12

SLP_S4# H7

SLP_S5# / GPIO63 E4

SYS_RESET#

T6

SYS_PW ROK

M6

PWRBTN#

P5

RI#

F14

WAKE# J12

SUS_STAT# / GPIO61 P8

SUSCLK / GPIO62 F3

ACPRESENT / GPIO31

P7

LAN_RST#

A10

MEPWROK

K5

BATLOW# / GPIO72

A6

PWROK

B17

CLKRUN# / GPIO32 Y1

SUS_PWR_ACK / GPIO30

M1

RSMRST#

C16

DRAMPWROK

D9

SLP_LAN# F6

R 2 23 0_ 04 02_ 5%

1 2

R 23 2

1K_0402_0.5%

LVDS

Digital Display Interface

CRT

U7D

IB E XPEAK-M_FCBGA1071

L_BKLTCTL

Y48

L_BKLTEN

T48

L_CTRL_CLK

AB46

L_CTRL_DATA

V48

L_DDC_CLK

AB48

L_DDC_DATA

Y45

L_VDD_EN

T47

LVDSA_CLK#

AV53

LVDSA_CLK

AV51

LVDSA_DATA#0

BB47

LVDSA_DATA#1

BA52

LVDSA_DATA#2

AY48

LVDSA_DATA#3

AV47

LVDSA_DATA0

BB48

LVDSA_DATA1

BA50

LVDSA_DATA2

AY49

LVDSA_DATA3

AV48

LVDSB_CLK#

AP48

LVDSB_CLK

AP47

LVDSB_DATA#0

AY53

LVDSB_DATA#1

AT49

LVDSB_DATA#2

AU52

LVDSB_DATA#3

AT53

LVDSB_DATA0

AY51

DDPB_0N BD42

DDPB_1N BJ42

LVD_VREFH

AT43

LVD_VREFL

AT42

DDPD_2N BF37

DDPD_3N BE36

DDPB_2N BB40

DDPB_3N AW38

DDPC_0N BE40

DDPC_1N BF41

DDPC_2N BD38

DDPC_3N BB36

DDPD_0N BJ40

DDPD_1N BJ38

DDPB_0P BC42

DDPB_1P BG42

DDPD_2P BH37

DDPD_3P BD36

DDPB_2P BA40

DDPB_3P BA38

LVDSB_DATA1

AT48

LVDSB_DATA2

AU50

LVDSB_DATA3

AT51

LVD_IBG

AP39

LVD_VBG

AP41

DDPC_1P BH41

DDPC_0P BD40

DDPC_2P BC38

DDPC_3P BA36

DDPD_0P BG40

DDPD_1P BG38

CRT_BLUE

AA52

CRT_DDC_CLK

V51

CRT_DDC_DATA

V53

CRT_GREEN

AB53

CRT_HSYNC

Y53

CRT_IRTN

AB51

CRT_RED

AD53

CRT_VSYNC

Y51

DAC_IREF

AD48

SDVO_CTRLCLK T51

SDVO_CTRLDATA T53

DDPC_CTRLCLK Y49

DDPC_CTRLDATA AB49

DDPD_CTRLCLK U50

DDPD_CTRLDATA U52

DDPB_AUXN BG44

DDPC_AUXN BE44

DDPD_AUXN BC46

DDPB_AUXP BJ44

DDPC_AUXP BD44

DDPD_AUXP BD46

DDPB_HPD AU38

DDPC_HPD AV40

DDPD_HPD AT38

SDVO_TVCLKINP BG46

SDVO_TVCLKINN BJ46

SDVO_STALLP BG48

SDVO_STALLN BJ48

SDVO_INTP BH45

SDVO_INTN BF45

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

P C I_SERR #

ACCEL_INT#

US B RBIAS

PLT_RST#

US B 20_N 0

US B 20 _P0

US B 20_N 1

US B 20 _P1

US B _OC#0

C LK _P CI_K BC _R

C L K_PCI _FB_R

C LK _P CI_K BC _R

C L K_PCI _FB_R

CLK_PCI_DB_P

GPIO 24

GPIO 15

ALS _ EN#

WEBCA M _O FF

PCH_XDP_GPIO16

RU NS CI _E C#

PCH_XDP_GPIO49

GPIO 48

P CH _ DD R_R ST

US B _OC#0

NP CI_RS T #

IS O _P REP#

WLA N_TRA NSMI T_OFF#

CLK_PCI_DB_P

US B _OC#4

US B _OC#4

CP P E#

STP_PCI#

US B _OC#2

US B 20_N 3

US B 20 _P3

CP P E#

PCH_XDP_GPIO0

ALS _ EN#

CLK_PCIE _LAN#_R

GPIO 24

PCH_XDP_GPIO49

CLK_PCIE _LAN_R EQ#

RU NS CI _E C#

SATA_CLKREQ#

STP_PCI#

CLK_PCIE _LAN_R

WEBCA M _O FF

P CH _ DD R_R ST

H_THERM T RIP#_L

WLA N_TRA NSMI T_OFF#

P CH _ PE CI_ R

WWAN_TRANS M IT_OFF#

GPIO 15

PCH_XDP_GPIO16

GPIO 48

KB_RST#

LA NLINK _STATUS#

C LK _P CI_F B

CLK_PCI_KBC

SATA_CLKREQ#

US B _OC#2

GPIO 15

NV _RCOM P

US B 20_N 5

US B 20 _P5

F PR _ OF F

IS O _P REP#

PCI _PIRQ E #

P CI _ PIRQ D#

PCI _PIRQ A #

P CI _ PIRQ C#

PCI _PIRQ B #

P C I_PIR QF#

P CI _PIR QG#

PCI _REQ2 #

PCI _REQ3 #

PCI _REQ0 #

PCI _REQ1 #

PCI _GNT 0#

MODE M_DISABLE

PCI _GNT 2#

PCI _GNT 3#

PCI _FRA M E#

PCI _DEVSEL#

PCI _ STOP#

PCI _LOC K #

P CI _PAR

P CI _ TR DY #

P CI _IR D Y#

P C I_PERR #

N V_C LE

NV _A LE

N V_C LE

NV _A LE

PCI _REQ2 #

PCI _REQ1 #

P CI _ TR DY #

PCI _FRA M E#

P CI _IR D Y#

PCI _DEVSEL#

P C I_SERR #

P C I_PERR #

PCI _PIRQ B #

PCI _REQ0 #

P C I_PIR QF#

PCI _REQ3 #

PCI _GNT 3#

P CI _PIR QG#

PCI _PIRQ A #

P CI _ PIRQ C#

PCI _ STOP#

P CI _ PIRQ D#

PCI _PIRQ E #

PCI _GNT 0#

MODE M_DISABLE

ACCEL_INT#

PCI _LOC K #

GPIO7

GPIO7

US B 20_N 9

US B 20 _P9

US B 20_N 8

US B 20 _P8

W WAN_DET#

US B 20_N 10

US B 20 _P10

US B 20_N 12

US B 20 _P12

US B 20_N 6

US B 20 _P6

WWAN_TRANS M IT_OFF#

L AN_ DIS#

GPIO 46

GPIO 46

PLT_RST#< 4,21,22,27>

BUF _PLT_RST#< 4>

GATEA20 <28>

H _P E CI <4>

H_THERM T RIP# <4>

ACCEL_INT#<22>

US B 20_N 0 <24>

US B 20_P0 <24>

US B 20_N 1 <24>

US B 20_P1 <24>

C LK _P C I_F B<12>

C L K_ PC I_ DB<2 7>

CLK_PCI_KBC<28>

P C H _NC TF 6< 16>

P C H _NC TF 7< 16>

P C H_ NC TF 26< 16>

P C H_ NC TF 19< 16>

WLA N_TRA NSMIT_OFF#<22>

WWAN_TRANS M IT_OFF#<20,22>

P C I_ SE R R#< 27 ,28>

BT_OFF <26>

NP CI_RS T #<28>

US B 20_N 3 <24>

US B 20_P3 <24>

CLK_PCIE _LAN <21>

CLK_PCIE _LAN# <21>

CLK_PCIE _LAN_REQ#<21>

CLK_CPU_BCLK # <4>

C LK _C P U_B C LK <4>

KB_RST# <28>

H _C P UP W R GD <4>

O CP #< 38>

R UN S C I _E C#<2 8>

WEBCA M _OFF<18>

P C H_ D DR _R ST< 4>

US B 20_N 5 <24>

US B 20_P5 <24>

US B 20_N 8 <26>

US B 20_P8 <26>

US B 20_N 9 <22>

US B 20_P9 <22>

LA NLINK _STATUS# < 21>

C B _ IN #<2 1>

W WAN_ DE T#< 22>

L A N_ DI S#<21>

US B 20_N 10 < 19>

US B 20_P10 <19>

US B 20_N 12 < 18>

US B 20_P12 <18>

F P R _O FF < 19>

US B 20_N 6 <22>

US B 20_P6 <22>

+3VS

+ V CC P

+3VS

+3VS

+3VALW +3VS

+3VS

+3VS

+1.8VS

+3VS

+3VALW

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(4/6)-PCI/USB/RSVD

C us t o m

14 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

Power USB

USB_SB

USB_SB

Card Reader

Int el Anti-Theft Techonlogy

*

Wea k internal

PU,Do not pull low

Set to Vcc when HIGH

DMI Termination Voltage

NV_ALE

High=Endabled

Low=Disable(floating)

NV_CLE

Set to Vss when LOW

WWAN

BT

FPR

USB_CAM

WLAN

11/21 HP

for RF, SI

CPU Type Detect :

High-->SV , Low-->ULV

L

2/24

2/24

R 13 88 8 .2 K_ 04 02_5%

1 2

T146

P AD

R 13 71 8 .2 K_ 04 02_5%

1 2

T71 P AD

C 6 58

12P_0402_50V8J

1

2

R 3 00 1K _ 040 2_5%@

1 2

R 13 69 8 .2 K_ 04 02_5%

1 2

R 2 60

10K_0402_5%

1 2

GPIO

MISC

NCTF

RSVD

CPU

U 7F

IB E XPEAK-M_FCBGA1071

GPIO27

AB12

GPIO28

V13

MEM_LED / GPIO24

H10

GPIO57

F8

LAN_PHY_PWR_CTRL / GPIO12

K9

VSS_NCTF_1

A4

VSS_NCTF_2

A49

VSS_NCTF_3

A5

VSS_NCTF_4

A50

VSS_NCTF_5

A52

VSS_NCTF_6

A53

VSS_NCTF_7

B2

VSS_NCTF_8

B4

VSS_NCTF_9

B52

VSS_NCTF_10

B53

VSS_NCTF_11

BE1

VSS_NCTF_12

BE53

VSS_NCTF_13

BF1

VSS_NCTF_14

BF53

VSS_NCTF_15

BH1

VSS_NCTF_16

BH2

VSS_NCTF_17

BH52

VSS_NCTF_18

BH53

VSS_NCTF_19

BJ1

VSS_NCTF_20

BJ2

VSS_NCTF_21

BJ4

VSS_NCTF_22

BJ49

VSS_NCTF_23

BJ5

VSS_NCTF_24

BJ50

VSS_NCTF_25

BJ52

VSS_NCTF_26

BJ53

VSS_NCTF_27

D1

VSS_NCTF_28

D2

VSS_NCTF_29

D53

VSS_NCTF_30

E1

VSS_NCTF_31

E53

TACH2 / GPIO6

D37

TACH0 / GPIO17

F38

TACH3 / GPIO7

J32

TP9 M18

TP10 N18

TP11 AJ24

TP12 AK41

SATA3GP / GPIO37

AB13

SATA5GP / GPIO49

AA4

SCLOCK / GPIO22

Y7

SLOAD / GPIO38

V3

SDATAOUT0 / GPIO39

P3

SDATAOUT1 / GPIO48

AB6

A20GATE U2

PROCPWRGD BE10

RCIN# T1

PECI BG10

THRMTRIP# BD10

GPIO8

F10

CLKOUT_PCIE6N AH45

CLKOUT_PCIE6P AH46

PCIECLKRQ6# / GPIO45

H3

CLKOUT_PCIE7N AF48

CLKOUT_PCIE7P AF47

PCIECLKRQ7# / GPIO46

F1

TP5 AY46

TP4 AY45

TP6 AV43

TP7 AV45

BMBUSY# / GPIO0

Y3

TP16 M30

TP17 N30

NC_1 AB45

NC_2 AB38

NC_3 AB42

NC_4 AB41

GPIO15

T7

TACH1 / GPIO1

C38

TP13 AK42

TP3 BB22

TP1 BA22

TP2 AW22

TP14 M32

TP15 N32

SATA2GP / GPIO36

AB7

NC_5 T39

INIT3_3V# P6

STP_PCI# / GPIO34

M11

SATACLKREQ# / GPIO35

V6

SATA4GP / GPIO16

AA2

TP24 C10

TP8 AF13

CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3

CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1

TP19 AA23

TP18 H12

T132

P AD

R 26 9 10 K_ 040 2_5%

1 2

T59 P AD

T62 P AD

R 4 30

10K_0402_5%

12

R 13 81 8 .2 K_ 04 02_5%

1 2

T63 P AD

T84 P AD

T78 P AD

R 13 83 8 .2 K_ 04 02_5%

1 2

R 28 0 1K _0 402 _5%

1 2

R 2 88 0_ 040 2_5%

1 2

T76 P AD

R 30 1 10 K_ 040 2_5%

1 2

T64 P AD

T60 P AD

R 2 50 10 K _04 02_5%

1 2

R 2 99 10 K _04 02_5 %

1 2

R 2 81 10 K _04 02_5 %

1 2

R 29 1 10 K_ 040 2_5%

1 2

R 28 9 10 K_ 040 2_5%

1 2

T68 P AD

T67 P AD

R 29 5 10 K_ 040 2_5%

1 2

R 27 6 22 _04 02_5%

1 2

R 2 56

56_0402_5%

12

R 13 84 8 .2 K_ 04 02_5%

1 2

R 2 68 10 K _04 02_5 %

1 2

T77 P AD

R251 0_0402_5%

12

R 13 85 8 .2 K_ 04 02_5%

1 2

T65 P AD

R 13 80 8 .2 K_ 04 02_5%

1 2

R 2 55 5 6_ 040 2_5%

1 2

T70 P AD

R1470

100K_0402_5%

@

12

T74 P AD

R1504

10K_0402_5%

@

12

R 2 78 10 K_ 04 02_5 %

@

1 2

R 13 79 8 .2 K_ 04 02_5%

1 2

T80 P AD

R252 0_0402_5%

12

T61 P AD

R 13 70 8 .2 K_ 04 02_5%

1 2

R 13 67 8 .2 K_ 04 02_5%

1 2

R 13 68 8 .2 K_ 04 02_5%

1 2

T114P AD

R 2 87 10 K _04 02_5 %@

1 2

T133

P AD

R 2 90 10 K _04 02_5 %

1 2

R 1 74 1K _0 40 2_5%@

1 2

R 25 3

10K_0402_5%

1 2

R 25 9 22 .6 _0 402_1 %

1 2

R 2 96 10 K _04 02_5 %

1 2

R 27 4 22 _04 02_5%

1 2

T83 P AD

R 13 89 8 .2 K_ 04 02_5%

1 2

T82 P AD

R 27 3 10 K_ 040 2_5%

1 2

R 30 2 10 K_ 040 2_5%@

1 2

T134

P AD

T75 P AD

C 6 35

12P_0402_50V8J

1

2

R1482 0_0402_5%@

1 2

PCI

NVRAM

USB

U7E

IB EXPEAK-M_FCBGA1071

AD0

H40

AD1

N34

AD2

C44

AD20

C42

AD21

K46

AD22

M51

AD23

J52

AD24

K51

AD25

L34

AD26

F42

AD27

J40

AD28

G46

AD29

F44

AD3

A38

AD30

M47

AD31

H36

AD4

C36

AD5

J34

AD6

A40

AD7

D45

AD8

E36

AD9

H48

C/BE0#

J50

C/BE1#

G42

C/BE2#

H47

C/BE3#

G34

PCIRST#

K6

PERR#

E50

PIRQA#

G38

PIRQB#

H51

PIRQC#

B37

PIRQD#

A44

PLOCK#

D49

PLTRST#

D5

PME#

M7

REQ0#

F51

REQ1# / GPIO50

A46

REQ2# / GPIO52

B45

REQ3# / GPIO54

M53

SERR#

E44

STOP#

D41

TRDY#

C48

NV_ALE BD3

NV_CE#0 AY9

NV_CE#1 BD1

NV_CE#2 AP15

NV_CE#3 BD8

NV_CLE AY6

NV_DQS0 AV9

NV_DQS1 BG8

NV_DQ0 / NV_IO0 AP7

NV_DQ1 / NV_IO1 AP6

NV_DQ10 / NV_IO10 BD6

NV_DQ11 / NV_IO11 BB7

NV_DQ12 / NV_IO12 BC8

NV_DQ13 / NV_IO13 BJ8

NV_DQ14 / NV_IO14 BJ6

NV_DQ15 / NV_IO15 BG6

NV_DQ2 / NV_IO2 AT6

NV_DQ3 / NV_IO3 AT9

NV_DQ4 / NV_IO4 BB1

NV_DQ5 / NV_IO5 AV6

NV_DQ6 / NV_IO6 BB3

NV_DQ7 / NV_IO7 BA4

NV_DQ8 / NV_IO8 BE4

NV_DQ9 / NV_IO9 BB6

NV_RB# AV7

NV_RCOMP AU2

NV_WR#0_RE# AY8

NV_WR#1_RE# AY5

NV_WE#_CK0 AV11

NV_WE#_CK1 BF5

USBP0N H18

USBP0P J18

USBP10N A22

USBP10P C22

USBP11N G24

USBP11P H24

USBP12N L24

USBP12P M24

USBP13N A24

USBP13P C24

USBP1N A18

USBP1P C18

USBP2N N20

USBP2P P20

USBP3N J20

USBP3P L20

USBP4N F20

USBP4P G20

USBP5N A20

USBP5P C20

USBP6N M22

USBP7N B21

USBP7P D21

USBP8N H22

USBP8P J22

USBP9N E22

USBP9P F22

USBRBIAS# B25

USBRBIAS D25

USBP6P N22

AD10

E40

AD11

C40

AD12

M48

AD13

M45

AD14

F53

AD15

M40

AD16

M43

AD17

J36

AD18

K48

AD19

F40

DEVSEL#

F46

FRAME#

C46

GNT0#

F48

GNT1# / GPIO51

K45

GNT2# / GPIO53

F36

GNT3# / GPIO55

H53

PIRQE# / GPIO2

B41

PIRQF# / GPIO3

K53

PIRQG# / GPIO4

A36

PIRQH# / GPIO5

A48

IRDY#

A42

PAR

H44

OC0# / GPIO59 N16

OC1# / GPIO40 J16

OC2# / GPIO41 F16

OC3# / GPIO42 L16

OC4# / GPIO43 E14

OC5# / GPIO9 G16

OC6# / GPIO10 F12

OC7# / GPIO14 T15

CLKOUT_PCI0

N52

CLKOUT_PCI1

P53

CLKOUT_PCI2

P46

CLKOUT_PCI3

P51

CLKOUT_PCI4

P48

R 27 7 10 K_ 040 2_5%

1 2

R 2 75 10 K _04 02_5 %

1 2

R 3 04 10 K _04 02_5 %

1 2

T115P AD

R 2 85 10 K _04 02_5 %

1 2

R 13 74 8 .2 K_ 04 02_5%

1 2

T69 P AD

T138P AD

R 13 72 8 .2 K_ 04 02_5%

1 2

R 29 3 10 K_ 040 2_5%

1 2

R 13 86 8 .2 K_ 04 02_5%

1 2

R 2 67 1K _ 040 2_5%@

1 2

T66 P AD

T145

P AD

T79 P AD

R 2 54

0_0402_5%

1 2

R 25 7 32 .4 _0 402_1 %@

1 2

R 2 71 1K _ 040 2_5%@

1 2

R 13 90 8 .2 K_ 04 02_5%

1 2

R 26 6 22 _04 02_5%

1 2

R 13 87 8 .2 K_ 04 02_5%

1 2

R 1 90 1K _0 40 2_5%@

1 2

T72 P AD

U10

SN74AHC1G08DCKR_SC70-5@

IN1 1

IN2 2

G

3

O

4

P5

T81 P AD

R 13 76 8 .2 K_ 04 02_5%

1 2

R 28 3 10 K_ 040 2_5%

1 2

R 13 82 8 .2 K_ 04 02_5%

1 2

R 2 72 10 K _04 02_5 %

1 2

T73 P AD

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

+1.05V S _VCCF DI PLL

I C H_V 5REF_S US

I C H_V 5REF_S US

+V 1.1A_INT_V CCSUS

+V C CSST

+V C CRTCEXT

I CH _V 5R EF_R UN

+V 1.05S _VCCA_A_DPL

+V 1.05S _VCCA_B_DPL

+V 1.05S _VCCA_A_DPL

+P C H_VCC1_1_ 20

+P C H_VCC1_1_ 21

+P C H_VCC1_1_ 22

+P C H_VCC1_1_ 23

I CH _V 5R EF_R UN

+V 1.05S _VCCA_B_DPL

+1.05VS_APLL

+1.05VS

+1.05VS

+1.05VS

+3VS

+1.8VS

+V C CP

+1.8VS

+1.05VS

+3VALW

+3VS

+ V CC P

+ R TC VC C

+1.05VS

+3VS

+1.05VS

+3VALW

+1.05VS

+5VS +3VS+3VALW+5VALW

+3VS

+3VS

+1.05VS

+1.8VS

+1.05VS

+1.05VS

+1.8VS

+3VS

+1.05VS

+3VALW

+3VS

+1.8VS

+1.8VS

+3VS

+3VS

+3VS+3VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(5/6)-PWR

C us t o m

15 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

20 mils20 mils

3.208A

0.163A

1.998A

0.344A

0.052A

0.035A

0.072A

0.073A 0.357A

2mA

>1mA

>1mA

6mA

0.032A

0.069A

0.030A

0.156A

6mA

0.035A

0.061A

0.059A

0.085A

0.042A

1.524A

>1mA

Don't need extra-power

Don't need extra-power

add 0.1uf(0402) on +3VS to GND near D3 & R1386

and R1386 (for 33MHz harmonic)for EMI request, Compal SI, 1/19

C 29 0

1U_0402_6.3V4Z

1

2

C 29 3

1U_0603_6.3V6M

1

2

C 2 67

1U_0402_6.3V4Z

1

2

C 2 66

0.1U_0402_16V4Z

1

2

C 26 5

10U_0603_6.3V6M

1

2

L10

10UH_LB2012T1 00MR_20%_0805

1 2

C 27 8

0.1U_0402_16V4Z

1 2

T111P A D

R 3 10

100_0402_5%

12

C1337

0.1U_0402_16V4Z

1

2

D3

CH751H-40P T_SOD323-2

21

C 28 2

1U_0402_6.3V4Z

@

1

2

C 25 0

0.1U_0402_16V4Z

1

2

C254 0.1U_0402_16V4Z

1 2

C 26 4

1U_0402_6.3V4Z

1

2

C 2 41

10U_0805_6.3V6M

1

2

C 99 9

0.01U _0603_16V7K

@

1

2

C 2 68

1U_0402_6.3V4Z

1

2

T126 P A D

C247 0.1U_0402_16V4Z

1 2

C261 1U_0603_10V4Z

1 2

C 25 1

0.1U_0402_16V4Z

1

2

C 28 9

1U_0402_6.3V4Z

1

2

R1256 0_0402_5%

1 2

T127 P A D

T124P A D

L7

10UH_LB2012T1 00MR_20%_0805

1 2

C 28 8

1U_0402_6.3V4Z

@

1

2

R 6 73 0_ 04 02_ 5%

1 2

C 2 86

0.1U_0402_16V4Z

1

2

C 2 40

1U_0603_10V4Z

1

2

C 25 8

0.1U_0402_16V4Z

1 2

T125P A D

C 2 69

1U_0402_6.3V4Z

1

2

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

PCI/GPIO/LPC

RTC PCI/GPIO/LPC

U 7J

IB EXPEAK-M_FCBGA1071

DCPSUSBYP

Y20

VCCME[1]

AD38

VCCME[2]

AD39

VCCME[3]

AD41

VCCME[5]

AF41

VCCME[6]

AF42

VCCSUSHDA L30

VCCSUS3_3[28] U23

VCCIO[56] V23

VCCIO[13] AD19

VCCIO[14] AF20

VCCIO[15] AF19

VCCME[7]

V39

VCCME[8]

V41

VCCME[9]

V42

VCCME[10]

Y39

VCCME[11]

Y41

VCCME[12]

Y42

V5REF K49

VCC3_3[8] J38

VCC3_3[9] L38

VCC3_3[10] M36

VCC3_3[11] N36

VCC3_3[12] P36

VCC3_3[13] U35

VCCRTC

A12

VCCSUS3_3[27] A26

VCCSUS3_3[26] A28

VCCSUS3_3[25] B27

VCCSUS3_3[24] C26

VCCSUS3_3[23] C28

VCCSUS3_3[22] E26

VCCSUS3_3[21] E28

VCCSUS3_3[20] F26

VCCSUS3_3[19] F28

VCCSUS3_3[18] G26

VCCSUS3_3[17] G28

VCCSUS3_3[16] H26

VCCSUS3_3[15] H28

VCCSUS3_3[14] J26

VCCSUS3_3[13] J28

VCCSUS3_3[12] L26

VCCSUS3_3[11] L28

VCCSUS3_3[10] M26

VCCSUS3_3[9] M28

VCCSUS3_3[8] N26

VCCSUS3_3[7] N28

VCCSUS3_3[6] P26

VCCSUS3_3[5] P28

VCCSUS3_3[4] U24

VCCSUS3_3[3] U26

VCCSUS3_3[2] U28

VCCSUS3_3[1] V28

VCCIO[11] AD20

VCCIO[20] AD22

VCCIO[10] AH19

VCCADPLLA[2]

BB53

VCCADPLLB[1]

BD51

VCCIO[22]

AJ35

V5REF_SUS F24

VCCIO[16] AH20

VCCIO[17] AB19

VCCIO[18] AB20

VCCIO[19] AB22

VCCIO[12] AF22

VCC3_3[14] AD13

VCCIO[9] AH22

VCCVRM[4] AT20

DCPSUS

Y22

VCCIO[2]

AF34

VCCIO[3]

AH34

VCCLAN[1]

AF23

VCCLAN[2]

AF24

VCCADPLLA[1]

BB51

VCCADPLLB[2]

BD53

VCCVRM[3]

AU24

VCCACLK[1]

AP51

VCCACLK[2]

AP53

DCPRTC

V9

VCCIO[4]

AF32

VCCME[4]

AF43

VCCIO[23]

AH35

VCCIO[21]

AH23

DCPSST

V12 VCCSATAPLL[2] AK1

VCCSATAPLL[1] AK3

VCCME[13] AA34

VCCME[14] Y34

VCCME[15] Y35

VCCME[16] AA35

VCC3_3[5]

V15

VCC3_3[6]

V16

VCC3_3[7]

Y16

VCCSUS3_3[29]

P18

VCCSUS3_3[30]

U19

VCCSUS3_3[31]

U20

VCCSUS3_3[32]

U22

VCCIO[5] V24

VCCIO[6] V26

VCCIO[7] Y24

VCCIO[8] Y26

V_CPU_IO[1]

AT18

V_CPU_IO[2]

AU18

C1336

0.1U_0402_16V4Z

1

2

C 2 75

0.1U_0402_16V4Z

1

2

C 28 0

0.1U_0402_16V4Z

1 2

C 25 9

1U_0402_6.3V4Z

1

2

R311 0_0402_5%

1 2

C 24 6

1U_0402_6.3V4Z

1

2

POWER

VCC CORE

DMI

PCI E*

CRTLVDS

FDI

NAND / SPI HVCMOS

U7G

IB EXPEAK-M_FCBGA1071

VCCCORE[1]

AB24

VCCCORE[2]

AB26

VCCCORE[3]

AB28

VCCCORE[4]

AD26

VCCCORE[5]

AD28

VCCCORE[6]

AF26

VCCCORE[7]

AF28

VCCCORE[8]

AF30

VCCCORE[9]

AF31

VCCCORE[10]

AH26

VCCCORE[11]

AH28

VCCCORE[12]

AH30

VCCCORE[13]

AH31

VCCCORE[14]

AJ30

VCCCORE[15]

AJ31

VCCPNAND[4] AK19

VCCPNAND[3] AK20

VCCIO[27]

AN23

VCCIO[28]

AN24

VCCIO[29]

AN26

VCCIO[30]

AN28

VCCIO[54]

AN30

VCCIO[55]

AN31

VCCIO[33]

AT26

VCCIO[34]

AT28

VCCIO[35]

AU26

VCCIO[36]

AU28

VCCIO[37]

AV26

VCCIO[38]

AV28

VCCIO[39]

AW26

VCCIO[40]

AW28

VCCIO[41]

BA26

VCCIO[42]

BA28

VCCIO[43]

BB26

VCCIO[44]

BB28

VCCIO[45]

BC26

VCCIO[46]

BC28

VCCIO[47]

BD26

VCCIO[48]

BD28

VCCIO[49]

BE26

VCCIO[50]

BE28

VCCIO[51]

BG26

VCCIO[52]

BG28

VCCIO[53]

BH27

VCCIO[31]

BJ26

VCCIO[32]

BJ28

VCCADAC[1] AE50

VCCADAC[2] AE52

VCCTX_LVDS[1] AP43

VCCTX_LVDS[2] AP45

VCCALVDS AH38

VCCVRM[2] AT24

VCCVRM[1]

AT22

VCCAPLLEXP

BJ24

VCCFDIPLL

BJ18

VCCPNAND[6] AK13

VCCPNAND[5] AK15

VCCPNAND[7] AM12

VCCPNAND[8] AM13

VCCIO[24]

AK24 VCCTX_LVDS[4] AT45

VCCTX_LVDS[3] AT46

VSSA_DAC[1] AF53

VSSA_LVDS AH39

VSSA_DAC[2] AF51

VCCIO[1]

AM23

VCC3_3[2] AB34

VCC3_3[3] AB35

VCC3_3[4] AD35

VCC3_3[1]

AN35

VCCME3_3[1] AM8

VCCME3_3[2] AM9

VCCME3_3[3] AP11

VCCME3_3[4] AP9

VCCPNAND[2] AK16

VCCPNAND[9] AM15

VCCPNAND[1] AM16

VCCDMI[1] AT16

VCCDMI[2] AU16

VCCIO[25]

AN20

VCCIO[26]

AN22

C 2 91

0.1U_0402_16V4Z

1

2

C 2 43

10U_0805_6.3V6M

1

2

R 3 05 0_ 04 02_ 5%

1 2

C2710.1U_0402_16V4Z

1 2

R671 0_0402_5%

1 2

R 3 08 0_ 04 02_ 5%

1 2

T123P A D

C 27 4

0.1U_0402_16V4Z

1 2

C 25 6

22U_0805_6.3V6M

1

2

C 99 8

0.01U _0603_16V7K

@

1

2

C 26 3

1U_0402_6.3V4Z

1

2

R672 0_0402_5%@

1 2

C 26 0

1U_0402_6.3V4Z

1

2

C 29 2

1U_0402_6.3V4Z

1

2

R 3 09

100_0402_5%

12

C 2 44

0.1U_0402_16V4Z

@

1

2

C 2 85

0.1U_0402_16V4Z

1

2

C 27 2

0.1U_0402_16V4Z

1 2

R303 0_0402_5%

1 2

C 25 7

1U_0402_6.3V4Z

1

2

C 27 9

1U_0402_6.3V4Z

<B O M Structure>

1

2

D2

CH751H-40P T_SOD323-2

21

C 2 62

0.1U_0402_16V4Z

1

2

R 3 06 0_ 04 02_ 5%

1 2

R 3 07 0_ 04 02_ 5%

1 2

+

C 2 81

220U_B2_2.5VM_R35M

1

2

C270 0.1U_0402_16V4Z

1 2

C 2 55

22U_0805_6.3V6M

1

2

L43

0.1UH_MLF1608DR10KT_10%

1 2

C 2 52

1U_0402_6.3V4Z

1

2

+

C 2 87

220U_B2_2.5VM_R35M

1

2

C1000

22U_0805_6.3V6M

1

2

C 2 84

4.7U_0603_6.3V6K

1

2

L11

10UH_LB2012T1 00MR_20%_0805

1 2

C 2 42

0.01U _0603_16V7K

@

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

CRACK_BGA

CRACK_BGA

CRACK_BGA

P C H _NC TF 6< 14>

P C H _NC TF 7< 14>

P C H _NC TF 19< 14>

P C H _NC TF 26< 14>

CRACK_BGA < 8,28>

+3VS

+3VS

+3VS

+3VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0 .5

IBEX-M(6/6)-GND

C us t o m

16 41T uesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

BGA Ball Cracking Prevention and Detection

U7H

IB EXPEAK-M_FCBGA1071

VSS[1]

AA19

VSS[2]

AA20

VSS[3]

AA22

VSS[5]

AA24

VSS[6]

AA26

VSS[7]

AA28

VSS[8]

AA30

VSS[9]

AA31

VSS[10]

AA32

VSS[11]

AB11

VSS[12]

AB15

VSS[13]

AB23

VSS[14]

AB30

VSS[15]

AB31

VSS[16]

AB32

VSS[17]

AB39

VSS[18]

AB43

VSS[19]

AB47

VSS[20]

AB5

VSS[21]

AB8

VSS[22]

AC2

VSS[23]

AC52

VSS[24]

AD11

VSS[25]

AD12

VSS[26]

AD16

VSS[27]

AD23

VSS[28]

AD30

VSS[29]

AD31

VSS[30]

AD32

VSS[31]

AD34

VSS[33]

AD42

VSS[34]

AD46

VSS[35]

AD49

VSS[36]

AD7

VSS[37]

AE2

VSS[38]

AE4

VSS[39]

AF12

VSS[43]

AF35

VSS[44]

AP13

VSS[46]

AF45

VSS[47]

AF46

VSS[48]

AF49

VSS[49]

AF5

VSS[50]

AF8

VSS[51]

AG2

VSS[52]

AG52

VSS[53]

AH11

VSS[54]

AH15

VSS[55]

AH16

VSS[56]

AH24

VSS[57]

AH32

VSS[59]

AH43

VSS[60]

AH47

VSS[61]

AH7

VSS[62]

AJ19

VSS[63]

AJ2

VSS[64]

AJ20

VSS[65]

AJ22

VSS[66]

AJ23

VSS[67]

AJ26

VSS[68]

AJ28

VSS[69]

AJ32

VSS[70]

AJ34

VSS[71]

AT5

VSS[72]

AJ4

VSS[73]

AK12

VSS[76]

AK26

VSS[77]

AK22

VSS[78]

AK23

VSS[79]

AK28

VSS[80] AK30

VSS[81] AK31

VSS[82] AK32

VSS[83] AK34

VSS[84] AK35

VSS[85] AK38

VSS[86] AK43

VSS[87] AK46

VSS[88] AK49

VSS[89] AK5

VSS[90] AK8

VSS[91] AL2

VSS[92] AL52

VSS[93] AM11

VSS[96] AM20

VSS[97] AM22

VSS[98] AM24

VSS[99] AM26

VSS[100] AM28

VSS[102] AM30

VSS[103] AM31

VSS[104] AM32

VSS[105] AM34

VSS[106] AM35

VSS[107] AM38

VSS[108] AM39

VSS[109] AM42

VSS[110] AU20

VSS[111] AM46

VSS[112] AV22

VSS[113] AM49

VSS[114] AM7

VSS[116] BB10

VSS[117] AN32

VSS[118] AN50

VSS[119] AN52

VSS[120] AP12

VSS[121] AP42

VSS[122] AP46

VSS[123] AP49

VSS[124] AP5

VSS[125] AP8

VSS[126] AR2

VSS[127] AR52

VSS[128] AT11

VSS[131] AT32

VSS[132] AT36

VSS[133] AT41

VSS[134] AT47

VSS[135] AT7

VSS[136] AV12

VSS[137] AV16

VSS[138] AV20

VSS[139] AV24

VSS[140] AV30

VSS[141] AV34

VSS[142] AV38

VSS[143] AV42

VSS[144] AV46

VSS[145] AV49

VSS[146] AV5

VSS[147] AV8

VSS[148] AW14

VSS[149] AW18

VSS[150] AW2

VSS[151] BF9

VSS[152] AW32

VSS[153] AW36

VSS[154] AW40

VSS[155] AW52

VSS[156] AY11

VSS[157] AY43

VSS[158] AY47

VSS[40]

Y13

VSS[42]

AU4

VSS[45]

AN34

VSS[115] AA50

VSS[0]

AB16

VSS[58]

AV18

VSS[32]

AU22

VSS[4]

AM19

VSS[74]

AM41

VSS[75]

AN19

VSS[41]

AH49

VSS[129] BA12

VSS[130] AH48

VSS[101] BA42

VSS[95] AD24

VSS[94] BB44

Q11A

2N7002DW-T /R7_SOT363-6

61

2

U 7I

IB EXPEAK-M_FCBGA1071

VSS[159]

AY7

VSS[160]

B11

VSS[161]

B15

VSS[162]

B19

VSS[163]

B23

VSS[164]

B31

VSS[165]

B35

VSS[166]

B39

VSS[167]

B43

VSS[168]

B47

VSS[169]

B7

VSS[170]

BG12

VSS[171]

BB12

VSS[172]

BB16

VSS[173]

BB20

VSS[174]

BB24

VSS[175]

BB30

VSS[176]

BB34

VSS[177]

BB38

VSS[178]

BB42

VSS[179]

BB49

VSS[180]

BB5

VSS[181]

BC10

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC32

VSS[187]

BC36

VSS[188]

BC40

VSS[189]

BC44

VSS[190]

BC52

VSS[191]

BH9

VSS[192]

BD48

VSS[193]

BD49

VSS[194]

BD5

VSS[195]

BE12

VSS[196]

BE16

VSS[197]

BE20

VSS[198]

BE24

VSS[199]

BE30

VSS[200]

BE34

VSS[201]

BE38

VSS[202]

BE42

VSS[203]

BE46

VSS[204]

BE48

VSS[205]

BE50

VSS[206]

BE6

VSS[207]

BE8

VSS[208]

BF3

VSS[209]

BF49

VSS[210]

BF51

VSS[211]

BG18

VSS[212]

BG24

VSS[213]

BG4

VSS[214]

BG50

VSS[215]

BH11

VSS[216]

BH15

VSS[217]

BH19

VSS[218]

BH23

VSS[219]

BH31

VSS[220]

BH35

VSS[221]

BH39

VSS[222]

BH43

VSS[223]

BH47

VSS[224]

BH7

VSS[225]

C12

VSS[226]

C50

VSS[227]

D51

VSS[228]

E12

VSS[229]

E16

VSS[230]

E20

VSS[231]

E24

VSS[232]

E30

VSS[233]

E34

VSS[234]

E38

VSS[235]

E42

VSS[236]

E46

VSS[237]

E48

VSS[264] K47

VSS[265] K7

VSS[266] L14

VSS[267] L18

VSS[268] L2

VSS[269] L22

VSS[270] L32

VSS[271] L36

VSS[272] L40

VSS[273] L52

VSS[274] M12

VSS[275] M16

VSS[276] M20

VSS[277] N38

VSS[278] M34

VSS[279] M38

VSS[280] M42

VSS[281] M46

VSS[282] M49

VSS[283] M5

VSS[284] M8

VSS[285] N24

VSS[286] P11

VSS[288] P22

VSS[289] P30

VSS[290] P32

VSS[291] P34

VSS[292] P42

VSS[293] P45

VSS[294] P47

VSS[295] R2

VSS[296] R52

VSS[297] T12

VSS[298] T41

VSS[299] T46

VSS[300] T49

VSS[301] T5

VSS[302] T8

VSS[303] U30

VSS[304] U31

VSS[305] U32

VSS[306] U34

VSS[307] P38

VSS[308] V11

VSS[309] P16

VSS[310] V19

VSS[311] V20

VSS[312] V22

VSS[313] V30

VSS[314] V31

VSS[315] V32

VSS[316] V34

VSS[238]

E6

VSS[239]

E8

VSS[240]

F49

VSS[241]

F5

VSS[242]

G10

VSS[243]

G14

VSS[244]

G18

VSS[245]

G2

VSS[246]

G22

VSS[247]

G32

VSS[248]

G36

VSS[249]

G40

VSS[250]

G44

VSS[251]

G52

VSS[317] V35

VSS[318] V38

VSS[319] V43

VSS[320] V45

VSS[321] V46

VSS[322] V47

VSS[323] V49

VSS[324] V5

VSS[325] V7

VSS[326] V8

VSS[327] W2

VSS[328] W52

VSS[329] Y11

VSS[330] Y12

VSS[331] Y15

VSS[332] Y19

VSS[333] Y23

VSS[334] Y28

VSS[335] Y30

VSS[336] Y31

VSS[337] Y32

VSS[338] Y38

VSS[339] Y43

VSS[340] Y46

VSS[342] Y5

VSS[343] Y6

VSS[344] Y8

VSS[341] P49

VSS[345] P24

VSS[287] AD15

VSS[252]

AF39

VSS[253]

H16

VSS[254]

H20

VSS[255]

H30

VSS[256]

H34

VSS[257]

H38

VSS[258]

H42

VSS[346] T43

VSS[347] AD51

VSS[348] AT8

VSS[349] AD47

VSS[350] Y47

VSS[351] AT12

VSS[352] AM6

VSS[353] AT13

VSS[354] AM5

VSS[355] AK45

VSS[356] AK39

VSS[366] AV14

VSS[262] K11

VSS[263] K43

VSS[259] H49

VSS[260] H5

VSS[261] J24

R 3 13

100K_0402_5%

12

Q11B

2N7002DW-T /R7_SOT363-6

3

5

4

R 3 15

100K_0402_5%

12

R 3 14

100K_0402_5%

12

Q10B

2N7002DW-T /R7_SOT363-6

3

5

4

Q10A

2N7002DW-T /R7_SOT363-6

61

2

R 3 12

100K_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DP _DATA3R_P

DP D_ TXN3

DP _DATA2R_P

DP _DATA2R_N

DP _DATA1R_PDPD_TXP1

DP _DATA0R_P

DP _DATA0R_N

DP _DATA0R_P

DP _D C AD

DP _DATA2R_N

DP _DATA3R_P

DP D_ TXN0

DP _DATA1R_N

DP _DATA3R_N

DPD_TXP0

D P_ H PD

DP D_C_A UX

DP _DATA0R_N

DP _DATA2R_P

DP D_ TXN2

DP _DATA1R_P

DP D_C_A U X#

DP _EN D D C_ EN

DP _D C AD

N2944 1889D P D_CTRLCLK DP D_C_A UX

DP D_C_A U X#DP D_CTRLDATA N29441921

D DC_E N

D DC_E N

DP D_A UX#

DP D_A UX

DP D_AUX#_1

DP D_A UX_1

DP _EN

DP _EN

DP _DATA1R_N

DP _DATA3R_N

DPD_TXP3

DPD_TXP2

DP D_ TXN1

D P_ H PD

DP D_TXN1<13>

DP D_TXP0<13>

DP D_TXN0<13>

DP D_TXN2<13>

DP D_TXP1<13>

DP D_TXN3<13>

DP D_TXP2<13>

DP D_TXP3<13>

D P D_C TR LCL K<13>

DP D_CTRLDATA<13>

DP D_AUX#<13>

DP D_AUX< 13>

D P D_ H P D <13 >

+3VS_DP

+5VS+5VS

+3VS

+3VS

+3VS

+5VS

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0 .5

Display Port Connector

17 41T uesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

Q5A

2N7002DW-7-F_SOT363-6

61

2

R1107

10K_0402_5%

1 2

Q22A

2N7002DW-7-F_SOT363-6

61

2

Q23A

2N7002DW-7-F_SOT363-6

61

2

Q24A

2N7002DW-7-F_SOT363-6

6 1

2

C13050.1U_0402_16V4Z

12

C13070.1U_0402_16V4Z

12

Q21A

2N7002DW-7-F_SOT363-6

61

2

C13110.1U_0402_16V4Z

12

R1106

10K_0402_5%

1 2

R1099

100K_0402_5%

1 2

C13090.1U_0402_16V4Z

12

R1115

1M _0402_5%

12

C 66 4

0.1U_0402_16V4Z

1

2

Q12B

TR 2N7002DW-7- F 2N SOT-363

3

5

4

R1101

100K_0402_5%

@

1 2

C13040.1U_0402_16V4Z

12

Q5B

2N7002DW-7-F_SOT363-6

3

5

4

R1114

5.1M_0402_5%

12

Q24B

2N7002DW-7-F_SOT363-6

3

5

4

R1097

100K_0402_5%

1 2

F1

NA NOSMDC050F 0.5A 13.2V POLY - FUSE

21

C13060.1U_0402_16V4Z

12

R1105

100K_0402_5%

@

1 2

Q23B

2N7002DW-7-F_SOT363-6

3

5

4

C13080.1U_0402_16V4Z

12

C 66 5

10U_0805_10V4Z

1

2

Q21B

2N7002DW-7-F_SOT363-6

3

5

4

C13100.1U_0402_16V4Z

12

J D P1

MOLEX_105062-0001_20P-T

C O NN @

GND 24

GND 23

GND 22

GND 21

DP_PWR

20

RTN

19

HP_DET

18

AUX_CH-

17

GND

16

AUX_CH+

15

GND

14

CA_DET

13

LANE3-

12

LANE3_shield

11

LANE3+

10

LANE2-

9

LANE2_shield

8

LANE2+

7

LANE1-

6

LANE1_shield

5

LANE1+

4

LANE0-

3

LANE0_shield

2

LANE0+

1

Q22B

2N7002DW-7-F_SOT363-6

3

5

4

R11170_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB20_P12_R

USB20_N12_R

USB20_N12_R

USB20_P12_R

DISPLAY_OFF#

BLON_PWM_R

INV_PWM

USB20_P12_R

USB20_N12_R

ENAVDD<13>

WEBCAM_OFF<14>

ENABLT<13>

LID_SW#<25,28>

LVDS_A0N <13>

LVDS_A0P <13>

LVDS_A1N <13>

LVDS_A1P <13>

LVDS_A2N <13>

LVDS_A2P <13>

LVDS_ACLKN <13>

LVDS_ACLKP <13>

DDC2_DATA <13>

DDC2_CLK <13>

INV_PWM<13>

USB20_P12<14>

USB20_N12<14>

LCDVDDLCDVDD +3VS

+5VS +5V_WEBCAM

+3VS

+5VS

+3VS

+3VS

B+

LCDVDD

+5V_WEBCAM

+3VS

+3VALW

+5V_WEBCAM

+5VS

B+_LCD B+

B+_LCD

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

LCD CONN & Q-Switch & GPIO Ext.

18 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

LCD POWER CIRCUIT

LED/PANEL BD. CONN.

for EMI for RF

for ESD

12/05 HP

for RF

for RF

12/10 HP

3/23 for EMI

5/11

5/18

C666 0.1U_0603_50V

12

R1126 47K_0402_5%

1 2

R1472 0_0402_5%

1 2

L38

LQM21FN4R7N00L_0805

@

1 2

C683

4.7U_0805_10V4Z@

1

2

R1121

33_0402_5%

1 2

D5

CH751H-40_SC76

21

G

D

S

Q54

SI2301BDS_SOT23

2

13

R1123

10K_0402_5%

12

C1327

47P_0402_50V8J

@

12

Q6A

2N7002DW-7-F_SOT363-6

61

2

R1129 47K_0402_5%

1 2

C679

0.1U_0402_16V4Z

1

2

R1471 0_0402_5%

1 2

R1125 1M_0402_5%

1 2

C681

0.1U_0402_16V4Z

1

2

C682

2.2U_0805_10V5R

1

2

R1487

220K_0402_1%

1 2

R1130

100K_0402_1%

1 2

Q6B

2N7002DW-7-F_SOT363-6

3

5

4

R1128

10K_0402_5%

1 2

R1127

100K_0402_5%

1 2

D6

CM1293A-02SR_SOT143-4

@

GND 1

IO1 2

IO2

3

VIN

4

R1124

100_0402_1%

12

L44

WCM2012F2S-900T04_0805

@

1

122

33

4

4

C1318

0.1U_0402_16V4Z

1

2

C1328

47P_0402_50V8J

@

12

C676 0.22U_0402_10V4Z

1 2

G

D

S

Q90

SI2307CDS-T1-GE3 1P

2

1 3

C684

0.1U_0402_16V4Z

1

2

Q55

DTC124EKAGZT146_SC59-3

IN

2

OUT 1

GND

3

G

D

S

Q53

SI2301 1P_SOT23

2

1 3

C677

1U_0603_10V4Z

1

2

R11182.2K_0402_5% 1 2

R1120

10K_0402_5%

1 2

C680

4.7U_0805_10V4Z

1

2

R11192.2K_0402_5% 1 2

C1332

0.22U_0603_25V7K

12

R1506

10K_0402_5%

@

12

R1488

100K_0402_5%

12

C1333

1U_0603_25V4Z

1

2

D4

CH751H-40_SC76

21

C667 68P_0402_50V8J

12

JLVDS1

ACES_88242-3001_30P

CONN@

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

3132

C678

0.01U_0402_16V7K

1

2

R1122

100K_0402_1%

12

C1339

0.1U_0402_16V4Z

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

SATA_PRX_DTX_P0SATA_RXP0

SATA_PRX_DTX_N0

SATA_PTX_DRX_N0

SATA_PTX_DRX_P0

SATA_RXN0

SATA_TXP0_C

SATA_TXN0_C

B LUE

G R EE N

R E D

3V DD C CL

3V DD C DA

CR T_ HS Y NC HS YN C_ G_A

VS YNC_G _A

D _ H S Y N C

D_ DD CC L K

VGA_G

VGA_R

VGA_B

D_ D DCD AT A

C RT _ VS YN C

USB20_N10_R

US B 20_P 1 0_R

D_V S Y N C

US B 20_P 1 0_R

USB20_N10_R

M_BLUE

M_RED

M_G RE EN

V GA _R ER E D

VGA_BL

VGA_R

VGA_B

G R EE N

B LUE

VGA_G

+ FP_P WR

VGA_GR

SATA_PTX_DRX_P0 <11>

SATA_PTX_DRX_N0 <11>

SATA_PRX_DTX_P0 <11>

SATA_PRX_DTX_N0 <11>

M_G REEN<13>

M_RED<13>

M_BLUE<13>

C RT _ HS Y NC< 13>

C RT _ V S YN C< 13>

3 V DD C DA <1 3>

3 V DD C CL < 13>

F P R_ O F F<1 4>

US B 20_N 10<14>

US B 20_P10<14>

+5VS

+ C RT VD D+ RC R T_ V CC+5V S

+ C RT VD D

+3 VS+ CR T V DD + C RT VD D

+5VS +5VS

+3VS

+5VALW

+3VALW

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0.5

WLAN/ODD/HDD

19 41Tuesday , May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

2.5' SATA HDD Connector

Place component's

closely SATA

CONN.(JHDD1)

CRT Termination/EMI Filter close to PCH (U7)

W=40mils

Place close to

JCRT1

Finger printer

close to JCRT1

close to PCH (U7)

close to PCH (U7)

for ESD

3/24 for EMI

C 2 36

18P_0402_50V8J

1

2

C 23 8

0.1U_0402_16V4Z

1

2

R1463

10K_0402_5%

1 2

R1454

75_0402_1%

1 2

L2

HLC0603CSCC27NJT_0603

1 2

R1450

0_0603_5%

1 2

U4

SN74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

R 2 17 0_ 04 02_ 5%

12

C 23 5

27P_0402_50V8J

1

2

C 24 5

0.1U_0402_16V4Z

1

2

R1456

75_0402_1%

1 2

Q17A

2N7002DW-7-F_SOT363-6

6 1

2

C 25 3

5P _0402_50V8C

@

1

2

R 2 06 0_ 04 02_ 5%

12

C 21 1

10U_0805_10V4Z

1

2

R1464

220K_0402_1%

1 2

R1452

0_0603_5%

1 2

R 1 93

2.2K_0 402_5%

12

J FP R 1

ACE S _87151-04051_4P

C O NN @

1

2

3

4

5

6

R1451 0_0603_5%

1 2

L3

HLC0603CSCC27NJT_0603

1 2

C 8 73 0. 01 U_ 04 02_1 6V7K

1 2

G

G

J C RT 1

SU YIN_070546FR015S290ZR

CONN@

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

16

17

F2

1.1A_6 V DC_F USE

21

C 23 9

0.1U_0402_16V4Z

1

2

R1455

75_0402_1%

1 2

R1448

0_0603_5%

1 2

D35

PRT R5V0U2X_SOT143-4

GND 1

IO1 2

IO2

3

VIN

4

R 2 16

2.2K_0 402_5%

12

R 2 15

2.2K_0 402_5%

12

C 8 70 0. 01 U_ 04 02_1 6V7K

1 2

C1296

10P_0402_50V8J@

1

2

R 21 8

2.2K_0 402_5%

12

D17

DA N217T146_SC59-3

@

2

3

1

L4

HLC0603CSCC27NJT_0603

1 2

R 6 39 0_ 040 2_5%

1 2

R1449 0_0603_5%

1 2

R 6 38 0_ 040 2_5%

1 2

C 2 37

27P_0402_50V8J

1

2

C 2 34

27P_0402_50V8J

1

2

J H D D1

SANTA_192701-1_22P-T

C O NN @

GND 1

A+ 2

A- 3

GND 4

B- 5

B+ 6

GND 7

V33 8

V33 9

V33 10

GND 11

GND 12

GND 13

V5 14

V5 15

V5 16

GND 17

Reserved 18

GND 19

V12 20

V12 21

V12 22

NC

23 NC

24

GND

25 GND

26

D32

RB 491D _SC59-3

2 1

C 8 71 0. 01 U_ 04 02_1 6V7K

1 2

C 2 32

18P_0402_50V8J

1

2

C 27 6

5P _0402_50V8C

@

1

2

R1453 0_0603_5%

1 2

C 24 8

0.1U_0402_16V4Z

1

2

C 27 3

0.1U_0402_16V4Z

1 2

Q17B

2N7002DW-7-F_SOT363-6

3

5

4

D18

DA N217T146_SC59-3

@

2

3

1

C1298

10P_0402_50V8J@

1

2

C1297

10P_0402_50V8J@

1

2

C 23 3

18P_0402_50V8J

1

2

C 24 9

0.1U_0402_16V4Z

1 2

G

D

S

Q87

SI2301 BDS_SOT23

2

13

D34

DA N217T146_SC59-3

@

2

3

1

C1299

0.1U_0402_10V6K

1

2

C1300

10U_0805_10V4K

1

2

U5

SN74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

C 8 72 0. 01 U_ 04 02_1 6V7K

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BT_LED

WL/BT_LED#

SATA_LED#

WL_BLUE_BTN

WL/BT_LED#

APP_BUTTON_1

APP_BUTTON_1_LED#

APP_BUTTON_2

APP_BUTTON_2_LED#

APP_BUTTON_2

APP_BUTTON_2_LED#

APP_BUTTON_1

APP_BUTTON_1_LED#

WW_LED#

HDD_HALTLED#

HDD_HALTLED

BT_LED

WL_LED#

SATA_LED#<11>

HDD_HALTLED<11>

APP_BUTTON_2 <28>

APP_BUTTON_1 <28>

WL_BLUE_BTN <28>

CAPS_LOCK_KBC<28>

CAPS_LED#<25>

WW_LED#<22>

BT_LED<26>

WL_LED#<22>

WWAN_TRANSMIT_OFF#<14,22>

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

LEDS & LID

Custom

20 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

whiteAMBER

HDD active LED

To LED small board

9/1 Del Q58

12/04, HP

C686

0.22U_0402_10V4Z

1

2

Q16B

TR 2N7002DW -7-F 2N SOT-363

3

5

4

Q12A

TR 2N7002DW -7-F 2N SOT-363

61

2

Q14B

TR 2N7002DW -7-F 2N SOT-363

3

5

4

C685

1U_0402_6.3V6K

1

2

R1139

10K_0402_5%

@

1 2

C689

0.22U_0402_10V4Z

1

2

R1144

1M_0402_5%

1 2

R1137

0_0402_5%

1 2

Q13A

TR 2N7002DW -7-F 2N SOT-363

61

2

JLED1

ACES_85201-1005N CONN@

11

22

33

44

55

66

77

88

99

10 10

GND 11

GND 12

R1143

470_0402_5%

12

R1141

470_0402_5%

12

R1136

1K_0402_5%

12

WHITE

YELLOW

D7

HT-297UY5/BP5_YELLOW-WHITE

21

43

R1133 0_0402_5%

1 2

R1131

47K_0402_5%

12

R1135

255_0402_1%

12

Q15B

TR 2N7002DW -7-F 2N SOT-363

3

5

4

R1138 100K_0402_5%

1 2

D8

CH751H-40_SC76

2 1

Q14A

TR 2N7002DW-7-F 2N SOT-363

61

2

Q16A

TR 2N7002DW-7-F 2N SOT-363

61

2

R1132 0_0402_5%

1 2

R1134

255_0402_1%

12

R1142

1M_0402_5%

1 2

D9

CH751H-40_SC76

2 1

Q13B

TR 2N7002DW -7-F 2N SOT-363

3

5

4

C688

1U_0402_6.3V6K

1

2

C687

0.1U_0402_16V4Z

1

2

R1140 0_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCT RL12 +EVDD12

+LAN_VDD12

LA N _DI

L AN_ CS

LA N_MDI2-

LA N_MDI3+

LA N_MDI3-

LA N_MDI2+

LA N_MDI0-

LA N_MDI1+

VCT RL12

C TRL 15/ VDD33

L AN_ CS

LA N _DI

LA N_ACTIVI TY#

LA N_MDI0+

LA N_MDI1-

L AN_ DIS#

LAN_X1

LAN_X2

L AN_ DIS#

PCI E _RXP6_LAN

PCI E _RXN6_LAN

LAN_X1 L AN_X2

C TRL 15/ VDD33

RJ 45_M I DI 3-

RJ 45_M I DI 3+

RJ 45_M I DI 2+

RJ 45_M I DI 2-

RJ 45_M I DI 1+

RJ 45_M I DI 1-

RJ 45_M I DI 0+

RJ 45_M I DI 0-

R J4 5 _G ND

LA NLINK _STATUS#

LA NLED_LINK #

LA N_ACTIVI TY#

CLK_PCIE _LAN_R EQ1#

CLK_PCIE _LAN_R EQ1#

LA NLED_A CT#

LA NLED_LINK #

RJ 45_M I DI 3+

RJ 45_M I DI 3-

RJ 45_M I DI 2-

RJ 45_M I DI 2+

RJ 45_M I DI 1-

RJ 45_M I DI 0+

RJ 45_M I DI 1+

RJ 45_M I DI 0-

LA NLINK _STATUS#

LA NLED_A CT#

C B_ I N#

LA N_MDI1-

LA N_MDI1+

LA N_MDI2-

LA N_MDI2+

LA N_MDI0-

LA N_MDI0+

LA N_MDI3-

LA N_MDI3+

C B_ I N#

PCI E _PTX_C_DRX_N6<12>

PCI E _PTX_C_DRX_P6<12>

CLK_PCIE _LAN#<14>

CLK_PCIE _LAN<14>

PLT_RST#<4,14,22,27>

PCI E _WAKE#<13,22>

PCIE_PRX_DTX_P6<12>

PCI E _PRX_DTX_N6<12>

SLP_S3#<13,23,28,29,30, 32,34,35>

ADP _PRES<28,31, 32,38>

CLK_PCIE _LAN_REQ#<14>

LA NLINK _STATUS# <14>

C B _ IN # <14 >

L A N_D IS #< 14>

+3V_LAN

+E V DD12

+LAN_VDD12

+3V_LAN

+E V DD12

+3VS

+LAN_VDD12

+LAN_VDD12

+3V_LAN

+3VALW +3V_LAN

+3V_LAN

+3VS

+3VS

+3V_LAN

+3V_LAN

+3V_LAN

+3V_LAN

+3V_LAN

+3V_LAN

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1P

0.5

GLAN RTL8111DL

C us t om

21 41Tuesday , May 18, 201 0

2007/08/28 2006/10/06

Compal Electronics, Inc.

10/100 and Giga Transformer

Close to Pin19

Close to Pin1,37,29

Close to Pin48

Close to Pin10,13,30,36

Note 1: The Trace length

between L1 and 8111DL's Pin

1 must be within 0.5 cm. C262

and C263 to L1 must be within

0.5cm. Refer to Layout guide

for more detail.

Close to Pin39 for 8111DL Close to Pin40 for 8111DL

Close to Pin45,44

Place Close to Chip

LAN Conn.

370mA

Th e +3V_LAN Rising time (10%~90%) need >1mS and <100mS

change to 22U by realtek request

for internal regular

Swap the signal 0<-->3, 1<-->2 for layout routing, Compal SI 1/14

reserve for switch WLAN

and on board LAN,

Compal SI 1/19

For ESD

2nd Source :

HDT BA30-A66 1G LAN

R1146

47K_0402_5%

12

C1290

1U_0402_6.3V4Z

1

2

L42

4.7UH_1008HC -472 E JFS-A_5%_1008

1 2

R1445

10K_0402_5%

12

R1165

300_0603_5%

1 2

C1249

27P_0402_50V8J

1

2

R1145

10K_0402_5%

12

C 4 82

0.1U_0402_16V4Z

1

2

C 4 79 0. 1U _0 402 _16V 7K

12

C1289

1U_0402_6.3V4Z

1

2

R1028

0_0402_5%

12

C1278

0.1U_0402_16V4Z

1

2

C1247

0.1U_0402_25V6

1

2

R 8 22 75 _0 40 2_1%

1 2

Y4

25MHZ_20PF_7A25000012

12

C 12 91 0 .0 1U_ 04 02_ 16V7K

1 2

R 9 23 75 _0 40 2_1%

1 2

C1276

27P_0402_50V8J

1

2

C 10 41 1 00 0P _0402 _50V 7K

12

Q27B

2N7002DW-7-F_SOT363-6

3

5

4

C1288

0.1U_0402_16V4Z

1

2

G

D

S

Q 59

SI2301 BDS_SOT23

2

13

R1492 0_0402_5%@

1 2

R1166

300_0603_5%

1 2

C1285

0.1U_0402_16V4Z

1

2

R 8 19

0_0603_5%

12

R 10 24 3. 6K _0 402_5 %

1 2

RTL8111DL

U57

RT L8111DL-VB-GR_LQFP48_7X7

AVDD33 1

MDIP0 2

MDIN0 3

FB12 4

MDIP1 5

MDIN1 6

GND

7

MDIP2 8

MDIN2 9

AVDD12 10

MDIP3 11

MDIN3 12

RSET

46

SROUT12 48

GND

47

CKTAL2

42 CKTAL1

41

AVDD33 40

VDDSR 44

LED0 38

VDD33 37

ENSR 43

DVDD12 13

GND

14

HSIP

15

HSIN

16

REFCLK_P

17

REFCLK_N

18

EVDD12 19

HSOP

20

HSON

21

EGND

22

GPO

23

NC

24

LED1/EESK 35

LED2/EEDI/AUX 34

LED3/EEDO 33

EECS 32

DVDD12 36

GND

31

DVDD12 30

VDD33 29

ISOLATEB

28

PERSTB

27

LANWAKEB

26

CLKREQB

25

AVDD12 39

VDDSR 45

C 4 80

0.1U_0402_16V4Z

1

2

C1279

0.1U_0402_16V4Z

1

2

C1282

0.1U_0402_16V4Z

1

2

C 12 77 0 .0 1U_ 04 02_ 16V7K

1 2

R 9 22 75 _0 40 2_1%

1 2

U 56

SUP E RWORLD_SWG150401

TCT1

1

TD1+

2

TD1-

3

TCT2

4

TD2+

5

TD2-

6MX2- 19

MX2+ 20

MCT2 21

MX1- 22

MX1+ 23

MCT1 24

TCT3

7

TD3+

8

TD3-

9

TCT4

10

TD4+

11

TD4-

12

MCT3 18

MX3+ 17

MX3- 16

MCT4 15

MX4+ 14

MX4- 13

D43

PACDN042_SOT23~D

@

2

3

1

R 2 58

10K_0402_5%

@

1 2

G

D

S

Q60

2N7002_SOT23-3

2

13

R 10 26 2.4 9K _0 402_1 %

1 2

R1027

1K _0402_5%

12

C1248

22U_0805_6.3V6M

1

2

C1287

22U_0805_6.3V6M

1

2

R1150 0_0402_5%

@

12

C1045

1000P _1808_3KV7K

1

2

R1030

0_0402_5%

@

12

C 71 9

0.1U_0402_10V6K@

1

2

C1286

0.1U_0402_16V4Z

1

2

C1281

0.1U_0402_16V4Z

1

2

C 12 92 0 .0 1U_ 04 02_ 16V7K

1 2

Q27A

2N7002DW-7-F_SOT363-6

6 1

2

C 10 39 1 00 0P _0402 _50V 7K

12

C 10 83 1 00 0P _0402 _50V 7K

12

R 81 7

0_0603_5%

1 2

R1029

15K_0402_5%

R 8 21 75 _0 40 2_1%

1 2

R1148

10K_0402_5%

12

R1147

10K_0402_5%

12

C 10 42 0 .0 1U_ 04 02_ 16V7K

1 2

C 10 85 1 00 0P _0402 _50V 7K

12

C1283

0.1U_0402_16V4Z

1

2

C 4 81 0. 1U _0 402 _16V 7K

12

C1280

0.1U_0402_16V4Z

1

2

J RJ 4 5

SANTA_130452-3_13P-T

PR1-

2

PR1+

1

PR2+

3

PR3+

4

PR3-

5

PR2-

6

PR4+

7

PR4-

8

Green LED-

10

Green LED+

9

Yellow LED-

12

Yellow LED+

11

SHLD1 14

SHLD1 15

DETECT PIN1 13

R1149

47K_0402_5%

12

C1284

0.1U_0402_16V4Z

1

2

R 10 25 1K _0 402 _5%@

12

R1446

0_0805_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

UIM_CLK

UIM_RST

M_WXMIT_OFF#

UIM_CLK

UIM_VPP

UIM_RSTUIM_VPP

XMIT_D_OFF#

PCIE_C_RXP4

PCIE_C_RXN4

WL_LED#

XMIT_D_OFF#

UIM_PWR

M_WXMIT_OFF#

PLT_RST#

UIM_DATA

UIM_PWR

UIM_DATA

UIM_PWR

PCIE_C_RXP7

PCIE_C_RXN7

PCIE_WAKE#

WW_LED#

SPI_SO_R0_DB

SPI_CS0#_DB

SPI_SI_DB

SPI_CLK_DB

SPI_HOLD#_MB

SPI_SO_R0_DBSPI_SO_JP

SPI_HOLD#_0

SPI_CLK_JP SPI_CLK_DB

SPI_SI_JP SPI_SI_DB

SPI_HOLD#_MB

SPI_CS0#_DBSPI_CS0#_JP

WWAN_TRANSMIT_OFF#<14,20>

USB20_N9 <14>

USB20_P9 <14>

PLT_RST# <4,14,21,27>

WL_LED# <20>

WLAN_TRANSMIT_OFF# <14>

WW_LED# <20>

WWAN_DET# <14>

PCIE_PTX_C_DRX_P4<12>

PCIE_PTX_C_DRX_N4<12>

PCIE_PRX_DTX_P4<12>

PCIE_PRX_DTX_N4<12>

ACCEL_INT#<14>

SMB_CLK_S3<9,10,12>

SMB_DATA_S3<9,10,12>

MC1_DISABLE<28>

USB20_N6 <14>

USB20_P6 <14>

PCIE_PTX_C_DRX_P7<12>

PCIE_PTX_C_DRX_N7<12>

PCIE_PRX_DTX_P7<12>

PCIE_PRX_DTX_N7<12>

PCIE_WAKE#<13,21>

CLKREQ_WLAN#<12>

CLK_PCIE_MCARD<12>

CLK_PCIE_MCARD#<12>

CLK_PCIE_MCARD2<12>

CLK_PCIE_MCARD2#<12>

CLKREQ_WWAN#<12>

SPI_RECOVERY<28>

SPI_HOLD#_0<27>

SPI_CLK_JP<27>

SPI_SI_JP<27>

SPI_CS0#_JP<27>

SPI_SO_JP<27>

+3V_WWAN

+3V_WWAN

+3V_WWAN

+1.5VS

+1.5VS

+3VS

+3VS

+3VS

+3V_WWAN

+3V_WWAN

+3V_WWAN

+3VS

+3VS

+3VS

+3VS

+3VS

+3VALW

+3V_WWAN

+3VALW

+3VALW

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

WLAN&WWAN Mini-Card/Accelerometer

22 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

Mini-Express Card--WWAN

WWLAN/WiMax Mini-Express Card

Add to prevent leakage issue.

Note2

Close to JP14

half size

Full size

0 0 1 1 1 0 1 b

ACCELEROMETER

L

Must be placed in the center of the system.

L

Place C933 between R1077.1 and R1079.2 for limit inrush current.

WWAN power control by F10. 11/09

11/21 HP

11/21 HP

12/04, HP

12/04, HP

12/05 HP

for RF

Compal,SI 1/4

delete port 80

02/23

02/23

02/23

03/29

04/19

C734

39P_0402_50V8J

@

1

2

Q77

SI2305DS-T1-E3_SOT23-3

2

31

C729

0.01U_0402_16V7K

1

2

R1175 0_0603_5%

1 2

LIS302DL

U14

HP302DLTR8_LGA14_3X5

VDD_IO

1

GND 2

RSVD 3

GND 4

GND 5

VDD

6

CS

7

INT 1

8

INT 2

9GND 10

RSVD 11

SDO

12

SDA / SDI / SDO

13

SCL / SPC

14

C736

0.1U_0402_16V4Z

1

2

R207 10K_0402_5%

12

T129PAD

R1499 0_0402_5%@

1 2

C738

0.1U_0402_16V4Z

1

2

J3

SHORT PADS

1 2

R1077

10K_0402_5%

12

C728

4.7U_0805_10V4Z

1

2

JWW AN1

MOLEX_67910-5700CONN@

1

122

3

344

5

566

7

788

9

910 10

11

11 12 12

13

13 14 14

15

15 16 16

17

17 18 18

19

19 20 20

21

21 22 22

23

23 24 24

25

25 26 26

27

27 28 28

29

29 30 30

31

31 32 32

33

33 34 34

35

35 36 36

37

37 38 38

39

39 40 40

41

41 42 42

43

43 44 44

45

45 46 46

47

47 48 48

49

49 50 50

51

51 52 52

GND1

53 GND2 54

R1505 0_0402_5%@

1 2

C740

18P_0402_50V8J

1

2

R1173

10K_0402_5%

@

12

T130PAD

R1500 0_0402_5%@

1 2

U13

S DIO(BR) NUP4301MR6T1 TSOP-6@

CH1

1

Vn

2

CH2

3CH3 4

Vp 5

CH4 6

R1174 0_0603_5%

1 2

C741

4.7U_0805_10V4Z

1

2

C733

10P_0402_25V8J

@

1

2

JWLAN1

FOX_AS0B226-S40N-7F

CONN@

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

GND1

53

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

42 42

44 44

46 46

48 48

50 50

52 52

GND2 54

R1501 0_0402_5%@

1 2

D14

CH751H-40_SC76

21

C933

1000P_0402_50V7K

1

2

R1476 10K_0402_5%

12

R1079 220K_0402_1%

1 2

R1469 0_0402_5%

1 2

C737

4.7U_0805_10V4Z

1

2

R1177

47K_0402_5%

@

1 2

D12 CH751H-40_SC76

2 1

R1498 0_0402_5%@

1 2

R1468 0_0402_5%

1 2

D13

DAN217T146_SC59-3@

2

3

1

JSIM1

TAITW_PMPAT6-06GLBS7N14N0CONN@

VCC 1

RST 2

CLK 3

GND

4

VPP

5

I/O

6

GND 8

GND 9

DET

7

R1176 10K_0402_5%

12

C742

0.1U_0402_16V4Z

1

2

R1168 0_0402_5%

1 2

R1502 0_0402_5%@

1 2

T131PAD

C726

0.01U_0402_16V7K

1

2

C739

10U_0805_6.3V6M

1

2

R1080

0_0805_5%

12

R1172

10K_0402_5%

12

C735

0.01U_0402_16V7K

1

2

R1167 0_0402_5%

1 2

C727

0.1U_0402_16V4Z

1

2

C730

0.1U_0402_16V4Z

1

2

C732

10P_0402_25V8J

@

1

2

C731

4.7U_0805_10V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

HDA_SYNC_CODEC

HDA_RST#_CODEC

HDA_SDOUT_CODEC

HDA_BIT_CLK_CODEC

HDA_SDIN0_CODEC

HP_OUTL

HP_OUTR

SB_SPKR

MONO_INR MONO_IN

SPKL+

SPKL-

SPKR+

SPKR-

SENSEA

MUTE_LED_CNTL

+VREFOUT_EXTMIC

MIC_EXTR

MIC_EXTL

+VREFOUT_INTMIC

MIC_INL

MIC_INR MIC_IN_R

MIC_IN_L

HP_OUTL HP_OUTR

EC_MUTE#

HP_DET#

HP_DET

SENSEA

SPKL+

SPKL-

SPKR+

SPKR-

MIC1

EC_MUTE#

MUTE_LED_CNTL

GNDA <24>

HDA_SDOUT_CODEC<11>

HDA_SYNC_CODEC<11>

HDA_RST#_CODEC<11>

HDA_SDIN0<11>

HP_OUTL <24>

HP_OUTR <24>

SB_SPKR <11>

MIC1 <24>

MIC_IN_L <24>

MIC_IN_R <24>

HP_DET<24>

MIC_SENSE<24>

+VREFOUT_EXTMIC <24>

+VREFOUT_INTMIC <24>

EC_MUTE#<28>

MUTE_LED_CNTL<28>

SLP_S3#<13,21,28,29,30,32,34,35>

HDA_BIT_CLK_CODEC<11>

+3VS_DVDD

+3VS_HDA

+AVDD_CODEC +5VS

+3VS

+3VS

+3VS

+AVDD_CODEC

+AVDD_CODEC

+5VALW

+3VS_DVDD

+AVDD_CODEC

+AVDD_CODEC

+AVDD_CODEC

+AVDD_CODEC

+5VALW +VDDA_CODEC

+AVDD_CODEC +VDDA_CODEC

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

Codec_IDT92HD80

Custom

23 41Tuesday, May 18, 2010

2007/08/28 2009/09/03

GNDAGND

HP Jack

Internal SPKR

Int MIC

Ext MIC

Port A

Port B

Port C

Port D

Port E

Port F

DM0

Ext MIC

Int MIC

Head phone

SPKR

X

X

Digital MIC

92HD80 port define

HP de pop circuit

CODEC POWER

W=40Mil

300mA

(4.75V)

Reserve CODEC LDO for Codec.

Reserve CODEC LDO for Codec.

delete D16, Compal, SI 1/5

install for ESD request, Compal SI 1/19

for ESD

R1349 0_0402_5%

1 2

C888 2.2U_0603_6.3V4Z

1 2

C886 1000P_0402_50V7K@1 2

C898

10U_0805_10V4Z

1 2

D37

PJSOT05C_SOT23

2

3

1

R1355 0_0603_5%

1 2

C1295

0.1U_0402_16V4Z

1

2

R1354

10K_0402_5%

1 2

Q70B

2N7002DW-7-F_SOT363-6

@

3

5

4

R1339 0_0805_5%@12

R1443

0_0402_5%

@

12

C890 2.2U_0603_6.3V4Z

1 2

C897

10U_0805_10V4Z

1

2

R1365

10K_0402_5%

1 2

Q71B

2N7002DW-7-F_SOT363-6

@

3

5

4

C893 0.1U_0402_16V4Z

12

R1366

10K_0402_5%

1 2

R1345 100K_0402_5%

12

Q72B

2N7002DW-7-F_SOT363-6

3

5

4

D15

CH751H-40PT_SOD323-2

21

R1352 100K_0402_5%

1 2

C743

1000P_0402_50V7K_X7R

1

2

C889 2.2U_0603_6.3V4Z

1 2

Q70A

2N7002DW-7-F_SOT363-6

@

61

2

R1357 0_0603_5%

1 2

C1294

2.2U_0805_16V4Z

1

2

C902 1000P_0402_50V7K

1 2

C876

0.1U_0402_16V4Z

1

2

C1293

0.1U_0402_16V4Z

1 2

Q84A

2N7002DW-7-F_SOT363-6

61

2

C884

10U_0805_10V4Z

1

2

R1360

4.7K_0402_5%

12

R1362

20K_0402_1%

12

R1358 0_0603_5%

1 2

C877

1U_0402_6.3V6K

1

2

C881 10U_0805_10V4Z

12

R1342

47_0402_5%

@

12

C906

220P_0402_50V7K

1

2

R1350 10K_0402_5%

1 2

JSPK1

E-T_3806K-F04N-03R_4P-T

CONN@

1

1

2

2

3

3

4

4

GND1

5

GND2

6

C907

220P_0402_50V7K

1

2

R1364

39.2K_0402_1%

12

R1351

10K_0402_5%

1 2

C904

220P_0402_50V7K

1

2

D38

PJSOT05C_SOT23

2

3

1

C883

1U_0402_6.3V6K

1

2

R1363

10K_0402_5%

1 2

C905

220P_0402_50V7K

1

2

C882

0.1U_0402_16V4Z

1

2

C892

4.7U_0603_6.3V6M 1

2

R1361

2.49K_0402_1%

12

C900 1000P_0402_50V7K

1 2

C879

1U_0402_6.3V6K

1

2

C908

0.01U_0402_16V7K

12

R1334

BLM18BD601SN1D_0603

12

R1442 0_0805_5%

12

Q71A

2N7002DW-7-F_SOT363-6

@

61

2

C885

33P_0402_50V8K

@

12

R1356 0_0603_5%

1 2

C903 1000P_0402_50V7K

1 2

C880

0.1U_0402_16V4Z

1

2

Q84B

2N7002DW-7-F_SOT363-6

3

5

4

U49

92HD80B1X5NLGXYD38_QFN48_7X7

DVDD_CORE

1

DVDD_IO

3

DMIC_CLK/GPIO1

2

DMIC0/GPIO2

4

SPKR_PORT_D_R- 43

SPKR_PORT_D_R+ 44

PVDD 45

DMIC1/GPIO0/SPDIF_OUT_1

46

HDA_SDO

5

HDA_BITCLK

6

DVSS

7

HDA_SDI

8

DVDD

9

HDA_SYNC

10

HDA_RST#

11

SPDIF_OUT_0

48

EAPD

47

MONO_OUT 25

AVDD 38

AVSS

26

PVSS

42

AVSS

33

AVDD 27

PVDD 39

SPKR_PORT_D_L- 41

VREG 37

VREFFILT 21

CAP2 22

HP0_PORT_A_L 28

VREFOUT_A_or_F 23

VREFOUT_C 24

HP0_PORT_A_R 29

CAP-

35

CAP+

36

SENSE_B 14

PORT_E_L 15

HP1_PORT_B_L 31

PORT_E_R 16

PORT_F_L 17

AVSS

30

PORT_F_R 18

PORT_C_L 19

PORT_C_R 20

PC_BEEP 12

HP1_PORT_B_R 32

SPKR_PORT_D_L+ 40

SENSE_A 13

V- 34

DAP

49

U58

G9191-475T1U_SOT23-5

IN

1

GND

2

SHDN

3

OUT 5

BYP 4

C899

1U_0603_10V6K

1

2

R1346

33_0402_5%

1 2

C896

4.7U_0603_6.3V6M

1

2

R1340 0_0603_5%

1 2

Q72A

2N7002DW-7-F_SOT363-6

61

2

C901 1000P_0402_50V7K

1 2

C895

0.1U_0402_16V4Z

1

2

C891 2.2U_0603_6.3V4Z

1 2

C878

0.1U_0402_16V4Z

1

2

C894 0.1U_0402_16V4Z

1 2

R1359

10K_0402_5%

@

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

INT_MIC_1_3

INT_MIC_1_4

EXT_MICL_3

MIC1

EXT_MIC EXT_MIC_1

INT_MIC_2_3

INT_MIC_2_4

HP_OUTL

HP_OUTR

USB20_N5

USB20_P5USB20_P1

USB20_N1

USB20_P3

USB20_N3

EXT_MIC

INT_MIC_1_2

INT_MIC_2_2

INT_MIC_2_2

INT_MIC_1_2

INT_MIC_2_2

SLP_S4

USB20_P0

USB20_N0

EXT_MIC

HP_DET

MIC1 <23>

MIC_IN_R<23>

MIC_IN_L<23>

HP_OUTR <23>

HP_OUTL <23>

USB20_P5 <14>

USB20_N5 <14>

USB20_N1<14>

USB20_P1<14>

USB20_N3<14>

USB20_P3<14>

MIC_SENSE <23>

+VREFOUT_INTMIC<23>

+VREFOUT_EXTMIC<23>

SLP_S4 <30>

HP_DET<23>

USB20_N0 <14>

USB20_P0 <14>

+CODEC_REF

+AVDD_CODEC

+AVDD_CODEC

+AVDD_CODEC

+AVDD_CODEC

+CODEC_REF

+CODEC_REF

+CODEC_REF

+5VALW +5VALW

+3VS

+5VALW+5VALW

+AVDD_CODEC

+AVDD_CODEC

+AVDD_CODEC

+5VALW

+5VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

AMP & Audio Jack

24 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

AMP. FOR EXTERNAL MICROPHONE

AMP. FOR INTERNAL MICROPHONE

Place close to U18

USB I/O connx2 , Aduio JACK

Card reader transfer conn

To CODE-ext MIC input

To CODE-ext MIC Bias

change from 120K to 47K, HP SI 1/28

C799

1U_0603_16V6K_X5R

@

1

2

R1211

3K_0402_5%

@

12

U18A

TLV2464_TSSOP14

P4

G

11

OUT 1

+

3

-

2

R1202

47K_0402_5%

1 2

R1216

10K_0402_5%

1 2

C797 0.068U_0603_16V7K

1 2

C784

220P_0402_25V8J

1

2

D19

CHN202UPT_SC-70

2

3

1

R1199

100K_0402_5%

1 2

C794

0.1U_0402_16V4Z

1

2

L40

HLC0603CSCCR10JT_0603

1 2

C792 100P_0402_50V8J

@

1 2

C802

1U_0603_16V7_X7R

@

1

2

R1208 100K_0402_5%

1 2

C791 100P_0402_50V8J

@

1 2

R1215

3K_0402_5%

@

12

JUSB23

ACES_88242-3001_30P

CONN@

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31 32

R1204

10K_0402_5%

1 2

R1205 100K_0402_5%

1 2

C7860.1U_0402_16V4Z

1

2

C788

100P_0402_50V8J

1

2

R1203

10K_0402_5%

1 2

C7854.7U_0805_10V4Z

1

2

C789 0.47U_0402_6.3V6K_X5R

12

R1212

3K_0402_5%

@

12

C790

68P_0402_50V8J

1

2

R1200

560K_0402_5%

1 2

C783

1U_0603_10V6K

1

2

C801

68P_0402_50V8J

1

2

R1206 10K_0402_5%

1 2

U17

LMV331IDCKRG4_SC70-5~D

P5

IN+

1

IN-

3

G

2

O4

R1210

3K_0402_5%

1 2

C798 0.068U_0603_16V7K

1 2 C800

68P_0402_50V8J

1

2

C787 15P_0402_50V8K

1 2

R1201

2.2K_0402_5%

12

R1214

3K_0402_5%

@

12

C793

100P_0402_50V8J

1

2

R1209

3K_0402_5%

1 2

U18D

TLV2464_TSSOP14

P4

G

11

OUT 14

+

12

-

13

C796

0.1U_0402_16V4Z

1

2

R1213

10K_0402_5%

1 2

L39 HLC0603CSCCR11JT_0603

1 2

U18C

TLV2464_TSSOP14

P4

G

11

OUT 8

+

10

-

9

C795

100P_0402_50V8J

1

2

R1207 100K_0402_5%

1 2

U18B

TLV2464_TSSOP14

P4

G

11

OUT 7

+

5

-

6

L41

HLC0603CSCCR10JT_0603

1 2

KSI[0..7]

KSO[0..11]

KSI0

KSI1

KSI5

KSI3

KSI4

KSI2

KSI6

KSI_D_12

KSI_D_6

KSO4

KSI_D_4

KSI_D_8

KSO9

KSI_D_5

KSO8

KSI_D_14

KSI_D_9

KSO1

KSO3

KSO11

KSO5

KSI_D_11

KSO10

KSI_D_3

KSO0

KSI_D_0

KSO2

KSI_D_13

KSO6

KSI_D_1

KSI_D_10

KSI7

KSO7

KSI_D_2

STB_LED

ON/OFFBTN_KBC#

KSI_D_12

KSI_D_6

KSO4

KSI_D_4

KSI_D_8

KSO9

KSI_D_5

KSO8

KSI_D_14

KSI_D_9

KSO1

KSO3

KSO11

KSO5

KSI_D_11

KSO10

KSI_D_3

KSO0

KSI_D_0

KSO2

KSO6

KSI_D_1

KSI_D_10

KSI7

KSI_D_2

KSI_D_13

KSO7

KSI_D_11

KSI_D_1

KSI_D_3

KSI_D_13

KSI_D_8

KSI_D_4

KSI_D_5

KSI_D_0

KSI_D_6

KSI_D_9

KSI_D_12

KSI_D_14

KSI_D_10

KSI_D_2

LID_SW#

KSI[0..7]<28>

KSO[0..11]<28>

CAPS_LED#<20>

ON/OFFBTN# <13,28>

ON/OFFBTN_KBC# <28>

STB_LED <28>

LID_SW# <18,28>

AQUAWHITE_BATLED# <11,28>

TP_CLK<28>

TP_DATA<28>

AMBER_BATLED# <28>

+3VALW

+3VL

+5VS

+5VS

+3VS

+3VS

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

MDC/KBD/ON_OFF/LID

25 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

T/P BOARD.

Power BTN/LED and Lid switch BD

INT_KBD CONN.

KB LED power

20mil

Pin 1

Pin1 reserve , so net name is reserve

for Fossil down contact

For EMI

12/09 HP

add 0.1U for EMI request, Compal SI 1/19

C632 100P_0402_50V8J@1 2

C630 100P_0402_50V8J@1 2

C805

1U_0603_10V4Z

1

2

D22

DAP202U_SOT323-3

2

3

1

C656 100P_0402_50V8J@1 2

C642 100P_0402_50V8J@1 2

JTPB1

ACES_87151-04051_4P

CONN@

1

2

3

4

5

6

C626 100P_0402_50V8J@1 2

C638 100P_0402_50V8J@1 2

C745 100P_0402_50V8J@1 2

D20

DAP202U_SOT323-3

2

3

1

D23

DAP202U_SOT323-3

2

3

1

C627 100P_0402_50V8J@1 2

D25

DAP202U_SOT323-3

2

3

1

C622 100P_0402_50V8J@1 2

C634 100P_0402_50V8J@1 2

D27

PACDN042Y3R_SOT23-3

2

3

1

D26

DAP202U_SOT323-3

2

3

1

JPWR1

ACES_85201-06051CONN@

GND 7

GND 8

11

22

33

44

55

66

C1334

0.1U_0402_16V4Z

1

2

C629 100P_0402_50V8J@1 2

D28

CH751H-40_SC76

@

21

D24

DAP202U_SOT323-3

2

3

1

C659 100P_0402_50V8J@1 2

C804

0.1U_0402_16V4Z

1

2

C620 100P_0402_50V8J@1 2

C621 100P_0402_50V8J@1 2

JKB1

HRS_FH28-60(30)SB-1SH(86)

CONN@

1

12

23

34

45

56

67

78

89

910

10 11

11 12

12 13

13 14

14 15

15 16

16 17

17 18

18 19

19 20

20 21

21 22

22 23

23 24

24

31

31 32

32

25

25 26

26 27

27 28

28 29

29 30

30

GND1

33 GND2

34

R1218

100K_0402_5%

12

C657 100P_0402_50V8J@1 2

C640 100P_0402_50V8J@1 2

C660 100P_0402_50V8J@1 2

C625 100P_0402_50V8J@1 2

C633 100P_0402_50V8J@1 2

R1217 470_0402_5%

1 2

C744 100P_0402_50V8J@1 2

D21

DAP202U_SOT323-3

2

3

1

C654 100P_0402_50V8J@1 2

C631 100P_0402_50V8J@1 2

C641 100P_0402_50V8J@1 2

C624 100P_0402_50V8J@1 2

R1219 100K_0402_5%@

1 2

C637 100P_0402_50V8J@1 2

C724 100P_0402_50V8J@1 2

C639 100P_0402_50V8J@1 2

C803

0.1U_0402_16V4Z

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB20_P8_R

USB20_N8_R

USB20_P8_R

USB20_N8_R

BT_OFF<14>

USB20_N8 <14>

BT_LED <20>

USB20_P8 <14>

+3VAUX_BT+3VALW

+3VAUX_BT

+3VAUX_BT

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

USB & BT Connector

26 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

BT(SoftBreeze) Connector

For ESD

G

D

S

Q63

SI2301BDS_SOT23

2

13

R1477

470_0402_5%

12

D29

CM1293A-02SR_SOT143-4

@

GND 1

IO1 2

IO2

3

VIN

4

R1223

220K_0402_1%

1 2

R1220 0_0402_5%

12

C8140.1U_0402_16V4Z

1

2

R1221 0_0402_5%

12

C8152.2U_0805_10V5R

1

2

C1324

0.1U_0402_10V6K

@

1

2

JBT1

ACES_87213-0800G_8P

CONN@

1

2

3

4

5

6

7

8

G

D

S

Q89

2N7002_SOT23-3

2

13

R1222

10K_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PCI_DB

SPI_SI_JP

SPI_SO_JP

SPI_HOLD#_0

8051_RECOVER#

DEBUG_KBCRST

8051_RECOVER#

SPI_CLK_JP

SPI_CS0#_JP

SIRQ

CLK_PCI_DB

SPI_SO_R0 SPI_SOSPI_SI

SPI_CS0#

SPI_CLK

SPI_WP#

SPI_HOLD#_1

SPI_CLK

SPI_SO_R0SPI_SO_JP

SPI_WP#

SPI_CLK_JP SPI_CLK

SPI_SI_JP SPI_SI

SPI_CS0#SPI_CS0#_JP

SPI_HOLD#_1SPI_HOLD#_0

+3VL_SPI PWR

LPC_LFRAME#<11,28>

PLT_RST#<4,14,21,22>

SIRQ<11,28>

LPC_LAD1<11,28>

LPC_LAD0<11,28>

LPC_LAD3<11,28>

LPC_LAD2<11,28>

8051RX<28>

8051TX<28>

DEBUG_KBCRST<33>

SPI_CS1#<28>

8051_RECOVER#<28>

PCI_SERR#<14,28>

CLK_PCI_DB<14>

SPI_CLK<28>

SPI_SI<28> SPI_SO <28>

SPI_CS0#<28>

SPI_CLK_JP<22>

SPI_CS0#_JP<22>

SPI_SI_JP<22>

SPI_SO_JP<22>

SPI_HOLD#_0<22>

B+_DEBUG

+3VL

+3VL

+3VL

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

BIOS ROM/SW LPC DEBUG

27 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

LPC Debug Port

25mA

20mils

20mils

SPI ROM SCKET

4MB SPI ROM

20mils

4MB SPI

ROM

BIOS ROM(4MB)

for RF

2nd Source :

WINBOND 32M W25Q32BVSSIG

EON 32M EN25F32-100HIP

05/10 Delete SPI Socket for MV.

R635 0_0402_5%

1 2

R634 0_0402_5%

1 2

R628 100K_0402_5%

1 2

R632 0_0402_5%

@

1 2

R636 0_0402_5%

1 2

R631 3.3K_0402_5%

1 2

R627

10_0402_5%@

12

C582

4.7P_0402_50V8C

@

1

2

R629 3.3K_0402_5%

1 2

C1323

47P_0402_50V8J

@1

2

U35

MX25L3205DM2I-12G

S

1

VCC

8

Q2

HOLD

7

VSS 4

D

5

C

6

W

3

C655

39P_0402_50V8J

@

1

2

R633 0_0402_5%

1 2

R630 33_0402_5%

1 2

JP31

ACES_87216-2404_24P

CONN@

Ground

1

LPC_PCI_CLK

2

Ground

3

LPC_FRAME#

4

+V3S

5

LPC_RESET#

6

+V3S

7

LPC_AD0

8

LPC_AD1

9

LPC_AD2

10

LPC_AD3

11

VCC_3VA

12

PWR_LED#

13

CAPS_LED#

14

NUM_LED#

15

VCC1_PWRGD

16

SPI_CLK

17

SPI_CS#

18

SPI_SI

19

SPI_SO

20

SPI_HOLD#

21

Reserved

22

Reserved

23

Reserved

24

R637 0_0402_5%

1 2

C581

0.1U_0402_16V4Z

1

2

1

1

2

2

3

3

4

4

5

5

A A

B B

C C

D D

P GD _ IN

8051TX

TEST

32K_CLK

AB1B_DATA

AB1B _CLK

SMB_E C_CK1

SMB_E C_DA1

KBRST#

CRACK_BGA

KSI4

KSI3

KSI0

KSI5

KSI1

KSI2

KSI6

TP_CLK

TP_DATA

RU NS CI _E C#

CLK_PCI_KBC

C R Y 1

C R Y 2

PM_RSMRST#

PM_RSMRST#

BAT_ALARM

LI D_S W#

AB1B_DATA

SMB_E C_CK1

AB1B _CLK

SMB_E C_DA1

KB C_PWR _ON

V CC 1_ PWRG D

KBRST#

CRACK_BGA

SLP_S3#

RO M _DATIN

RO M _ DATOUT

RO M _CS #0

RO M _C LK

RO M _CS 1#

SP_DATA

SP_C LK

P WR _ GD

KSO6

KSO9

KSO11

KSO1

KSO7

KSO3

KSO5

KSO8

KSO2

KSO0

KSO4

KSO10

B D_ I D

B D_ I D

SPI_C LK

RO M _CS #0

AD C 2

O CP _A_IN

AD C 1

A D C

A D C

AD C 1

AD C 2

PWRB T N_OUT#

CP U_SV_ID_DET

CP U_SV_ID_DET

CA P S _LOCK _KBC

CLK_PCI_KBC

RO M _C LK

TP_CLK

TP_DATA

SP_DATA

SP_C LK

KSI7

KSI6

KSI2

KSI3

KSI5

KSI0

KSI4

KSI1

APP_BUTTON_1

APP_BUTTON_2

CA P _CLK

AB2A_DATA

AB2A _CLK

MUT E _LED_C NTL_R MUTE_LED_CNTL

APP_B U TTON_1_R

APP_B U TTON_2_R

CA P S _LOCK _KB C_R

WL_BLUE _ BTNWL_BLUE _BT N_R

KSI7

KSI0

KSI1

P GD _ IN

WL_BLUE _ BTN

APP_BUTTON_1

APP_BUTTON_2

WL_BLUE _ BTN

APP_BUTTON_2

APP_BUTTON_1

8051TX ST B_LED

LI D_S W#

S PI _ RE COV ER Y_R

LP C_LA D 3<11,27>

LP C_LA D 2<11,27>

LP C_LA D 1<11,27>

LP C_LA D 0<11,27>

N P CI _RS T #<1 4>

K SI[ 0. .7]<25 >

S I RQ<1 1, 27>

R UN S C I _E C#<1 4>

TP_DATA< 25>

KSO[0..11]<25>

KBC_SPI_SO<11>

SPI_SI<27>

SPI_CS0#<27>

KBC_SPI_CS 0#_R<11>

SPI_SO<27>

SPI_CLK<27>

KB_RST# <14>

K B C_PWR_ ON <33 >

AQUA W HITE_BATLED# <11,25>

BAT_PWM_OUT <32>

C HG C TR L <32>

PM_RSMRST# <13>

CRACK_BGA < 8,16>

EC_MUTE# <23>

CE LLS <32>

BAT_ID# < 31>

GATEA20 <14>

ADP _PRES <21,31,32,38>

SMB_EC_DA1 < 31>

SMB_EC_CK1 < 31>

ADP _EN <38>

V C C1 _ PW R GD < 33, 38>

AMBER_BATLED# <25>

8051TX <27>

8051RX <27>

FAN_PWM <4>

KBC_SPI_CLK_R<11>

L I D_ SW # < 18, 25>

KBC_SPI_SI_R<11>

KBC_SPI_CS 1#_R<11>

SPI_CS1#<27>

P M _CL KR UN#<13>

LP C_LF RAME#< 11,27>

TP_CLK<25>

C LK _P C I_K B C<14>

SLP_S3# <13,21,23, 29,30,32,34,35>

AC_ADP_PRES <31,32>

ADP _A_ID <38>

8051_RECOV ER# <27>

SUS _PWR_A C K <13>

O CP < 38>

ADP _DET# <38>

PMC<32>

O CP _A _I N<38>

O N /O FF B TN # <1 3,25 >

CA P S _LOCK _KBC <20>

P C I_ SE R R# < 14, 27>

CA P _CLK <12>

CA P _DAT <12>

MUT E _LED_CNTL <23>

AC_PRESENT <13>

MC1_DISABLE<22>

P G D_ IN <1 3,3 7>

ON/OFFBTN _KBC# <25>

WL_BLUE _BTN <20>

APP_BUTTON_1 <20>

APP_BUTTON_2 <20>

P W R _G D < 29>

STB_LED <25>

S P I_ RECO VE RY < 22>

+3VL

+3VL

+3VS

+3VL

+ R TC VC C

+ V CC0

+ V CC 0

+3VL

+3VL

+3VL

+3VL

+3VL

+5VS

+3VL

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0.5

KBC1098

28 41Tuesday , May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

L

07/01 update

CPU Type Detect : High-->SV , Low-->LV

L

BIOS request. 11/20 Compal

for ESD

12/10 HP

compal, SI 12/24

Compal 12/24

Compal, SI 1/18

add 0.1U for EMI request, Compal SI 1/19

02/23

C 8 34

0.1U_0402_16V4Z

1

2

R 12 74 10K _0 402_ 5%

1 2

C 8 43

22P_0402_50V8J

1

2

C1329 0.1U_0402_16V4Z @

1 2

R 2 48 0_ 04 02_ 5%

1 2

C 83 3

0.1U_0402_16V4Z

1

2

R P 11

4.7K_0804_8P4R_5%

1 8

2 7

3 6

4 5

C 8 38 4. 7U _0 80 5_10 V6K

1 2

R1503 0_0402_5%@

1 2

R1307 0_0402_5%

1 2

C 8 42

4.7P_0 402_50V8C

@

1

2

R1268 0_0402_5%

1 2

R 12 69 10 K_ 040 2_5%

1 2

C 83 1

0.1U_0402_16V4Z

1

2

R 14 0110 K_ 04 02_5%

12

R1306 0_0402_5%

1 2

R1264 300_0402_5%

1 2

R1242

100K_0402_5%@

12

R1245 0_0402_5%

1 2

R 13 9710 K_ 04 02_5%

12

C 8 462 20 0P _04 02_25V 7K

12

R1253 0_0402_5%

1 2

R 52 6 10 K_ 040 2_5%

1 2

R 13 9810 K_ 04 02_5%

12

R1290 0_0402_5%

1 2

R 12 59 100 K_ 040 2_5%@

1 2

R1251 0_0402_5%

1 2

R1252 0_0402_5%

1 2

C 8 472 20 0P _04 02_25V 7K

12

T141

P AD

R 13 9910 K_ 04 02_5%

12

R 13 9610 K_ 04 02_5%

12

R1257 0_0402_5%

1 2

R1308 0_0402_5%

1 2

T143P AD

C 8 49

0.1U_0402_16V4Z

1

2

C1335 0.1U_0402_16V4Z

1 2

C1330 0.1U_0402_16V4Z@

1 2

T136

P AD

R 14 90 10 0K _0 402_5 %

12

D31

CH751H-40P T_SOD323-2

21

R1279

0_0402_5%@

12

R 12 77 10 K_ 04 02_5%

@

1 2

R1248 0_0402_5%

1 2

R1247 0_0402_5%

1 2

R1267 0_0402_5%

1 2

C1303 0.1U_0402_10V6K

1 2

R1249 0_0402_5%

1 2

R 12 72 10 K_ 040 2_5%

1 2

C 8 39

4.7P_0 402_50V8C@

1

2

R 14 89 10 0K _0 402_5 %

12

R 12 78 10K _0 402 _5%

1 2

R1250 0_0402_5%

1 2

R 12 58 100 K_ 040 2_5%@

1 2

C 8 40

4.7P_0 402_50V8C

@

1

2

C1331 0.1U_0402_16V4Z@

1 2

R 12 70 3 00 _04 02_5%

1 2

C 8 452 20 0P _04 02_25V 7K

12

R1486 0_0402_5%

1 2

R 12 73 3 00 _04 02_5%

1 2

C 8 35

4.7U_0805_10V4Z

1

2

R1275

0_0402_5%

12

R 52 8 10 K_ 040 2_5%@

1 2

C 83 7

0.1U_0402_16V4Z

1

2

R1240 0_0402_5%

1 2

Y5

32.76 8KHZ 1TJS125DJ4A420P

OUT 4

IN 1

NC

3

NC

2

C 8 48

1U_0603_10V4Z

1

2

T142

P AD

R1255

10_0402_5%

@

12

C 83 6

0.1U_0402_16V4Z

1

2

R 12 62 10 0K _0 402_5 %

1 2

C 8 41

4.7P_0 402_50V8C

@

1

2

R 52 7 10 K_ 040 2_5%@

1 2

R 52 5 10 K_ 040 2_5%

1 2

R1276

0_0402_5%

12

R1263 0_0402_5%

1 2

R 13 9510 K_ 04 02_5%

12

R 12 66 10 K_ 040 2_5%

1 2

General Purpose I/O Interface

Keyboard/Mouse Interface

LPC

Bus

Power Mgmt/SIRQ

Miscellaneous

Access Bus Interface

SMSC_1098-NU_TQFP-128P

U 21

KBC1098-NU_VTQFP128_14X14

AGND

72

KSO0

21

KSO1

20

KSO2

19

KSO3

18

KSO4

17

KSO5

16

KSO6

13

KSO7

12

KSO8

10

KSO9

9

KSO10

8

KSO11

7

KSO12/GPIO00/KBRST

6

KSO13/GPIO18

5

KSI0

29

KSI1

28

KSI2

27

KSI3

26

KSI4

25

KSI5

24

KSI6

23

KSI7

22

IMCLK

35

IMDAT

36

KCLK

61

KDAT

62

EMCLK

66

EMDAT

67

CLKRUN#

55

SER_IRQ

57

PCI_CLK

54

EC_SCI#

76

LAD[3]

51

LAD[2]

50

LAD[1]

48

LAD[0]

46

LFRAME#

52

LRESET#

53

AVSS

45

XTAL1

70

XTAL2

71

VCC1 14

TEST PIN 69

VSS

11

VSS

37

VSS

47

VSS

56

VSS

104

VSS

82

VSS

117

VCC1 39

VCC1 58

VCC1 84

VCC1 106

VCC1 119

VCC2 49

OUT0/(SCI) 124

OUT1/IRQ8# 125

CFETA/OUT7/nSMI 123

OUT8/KBRST 122

OUT9/PWM2 121

OUT10/PWM0 120

PWM_CHRGCTL 118

GPIO02 79

GPIO03 80

GPIO04/KSO14 81

GPIO05/KSO15 83

GPIO07/PWM3 85

GPIO08/RXD 86

GPIO09/TXD 87

GPIO11/AB2A_DATA 88

GPIO12/AB2A_CLK 89

GPIO13/AB2B_DATA 90

GPIO14/AB2B_CLK 91

GPIO15/FAN_TACH1 92

GPIO16/FAN_TACH2 101

GPIO17/A20M 102

GPIO20/PS2CLK 103

GPIO21/PS2DAT 105

AB1A_DATA 111

AB1A_CLK 112

AB1B_DATA 109

AB1B_CLK 110

GPIO25 73

GPIO01 107

GPIO26/KSO17 108

NC_CLOCKI 59

32KHZ_OUT/GPIO22/WK_SE01 75

RESET_OUT#/GPIO06 60

PWRGD 78

VCC1_RST# 77

ADC_TO_PWM_OUT/GPIO19 38

GPIO24/KSO16 4

ADP_PRES[CKT#2]/GPIO27/W K_SE05 74

CFETB/GPIO10 116

BAT_LED# 113

PWR_LED#/8051TX 115

FDD_LED#/8051RX 114

Alarm [CKT#2]/GPIO36

1

HSTCLK/GPIO41

2

FLCLK

3

GPIO39

30

HSTCS1#/GPIO42

31

FLCS1#

32

GPIO38

33

GPIO37

34

ADC1/GPIO46

43

ADC_TO_PWM_IN

44

AVCC 40

GPIO35 63

GPIO34 64

Q/GPIO33 65

ADC2/GPIO40 42

AC[CKT#2]/GPIO23 41

HSTDATAIN/GPIO43

94 FLDATAIN

95 HSTCS0#/GPIO44

96 FLCS0#

97 HSTDATAOUT/GPIO45

127 FLDATAOUT

128 CAP 15

GPIO28 93

GPIO29 98

GPIO30 99

GPIO31 100

GPIO32 126

VCC0

68

R1246 0_0402_5%

1 2

R 12 61 1K _0 402 _5%

1 2

R 14 91 10 0K _0 402_5 %

12

R1238

0_0603_5%

12

R 14 0010 K_ 04 02_5%

12

R1485

0_0402_5%

@

1 2

R 12 65 10 K_ 040 2_5%

@

1 2

C 8 44

22P_0402_50V8J

1

2

R 14 0210 K_ 04 02_5%

12

C 83 2

0.1U_0402_16V4Z

1

2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

2V REF_393

2V REF_393

SLP_S3#

VTTP W RGOOD <4>

P W R _ GD <2 8>

VCCP_POK<34>

SLP_S3#<13,21,23,28,30, 32,34,35>

1.8VS_POK<35>

V C CP _E N < 34>

V CC P_ 1.5V SP WRG D <4>

+5VALW

+1.5VS

+3VALW

+3VS

+5VALW

+0.75VS

+5VS

2V REF_51125

+3VS

2V REF_393

+3VALW

+1.5VS_CPU_V DDQ

Title

Size Docum ent Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

L A -6 16 1 P

0.5

POK CKT

29 41Tuesday , May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

WWLAN Card STANDOFF

CPU supportWWAN Card STANDOFF

Intel S3 power reduction circuit for Calpella. 11/09

H 20

HO LEA

1

U24

MC74VHC1G08DFT2G_SC70-5

IN1

1

IN2

2OUT 4

VCC 5

GND

3

FM4

1

FM2

1

R1283

0_0402_5%@

12

H10

HO LEA

1

U 23 B

LM 393DT_SO8

+

5

-

6O7

P8

G

4

H6

HO LEA

1

H3

HO LEA

1

U25

MC74VHC1G08DFT2G_SC70-5

IN1

1

IN2

2OUT 4

VCC 5

GND

3

C 8 52

3300P _0402_25V7K

1

2

R 12 96 3 4K _0 402_ 1%

1 2

U 23 A

LM 393DT_SO8

+

3

-

2O1

P8

G

4

H15

HO LEA

1

H4

HO LEA

1

H14

HO LEA

1

J1

SHO RT PADS

1 2

H19

HO LEA

1

H11

HO LEA

1

R1299

34.8K _ 0402_1%

12

D33

CH751H-40P T_SOD323-2

21

R 12 88 1 1. 5K _0 402_1%

1 2

H1

HO LEA

1

R 12 97 10 K_ 040 2_5%

1 2

FM1

1

H 17

HO LEA

1

FM3

1

R 12 94 34 K_ 040 2_1%

1 2

R1292

1M_0402_1%

1 2

R 12 81 3 .3 K_ 04 02_5%

1 2

H 16

HO LEA

1

R1298

2.49K _ 0402_1%

12

H9

HO LEA

1

ZZZ

LA-6161P_PCB

C 8 51

3300P _0402_25V7K

1

2

R1293

4.99K _ 0402_1%

12

R 12 95 7 5K _0 402_ 1%

1 2

R1284

8.2K_0 402_5%

12

H5

HO LEA

1

C 8 50

1000P _0402_50V7K

1

2

H2

HO LEA

1

R1280

1M_0402_1%

1 2

R 12 89 4 9. 9K _0 402_ 1%

1 2

R 12 85 7 6. 8K _0 402_1 %

1 2

R 12 86 10 K_ 040 2_5%

1 2

H 12

HO LEA

1

R 12 87 3 4. 8K _0 402_ 1%

1 2

R1282

10K_0402_5%

12

H13

HO LEA

1

R 12 91 3 .3 K_ 04 02_5%

1 2

H18

HO LEA

1

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SLP_S3

SLP_S3 SLP_S3SLP_S3

RUNON

SLP_S3

SLP_S3

RUNON

RUNON

RUNON

SLP_S3

SLP_S3

SLP_S4

SLP_S3 SLP_S3

SLP_S3

SLP_S3#<13,21,23,28,29,32,34,35>

SLP_S4#<13,36>

SLP_S4<24>

+3VS +5VS

+3VS+3VALW

+1.8VS

B+

+3VL

+1.5VS+1.5V

+1.5VS

+5VS+5VALW

+1.5V +1.5VS_CPU_VDDQ

+1.5V

+1.5VS_CPU_VDDQ

+1.5VS_CPU_VDDQ

+0.75VS

+3VL

+VCCP +GFX_CORE +1.5V

+1.5VS+1.5VS_CPU_VDDQ

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

DC/DC Circuits

30 41Tuesday, May 18, 2010

2009/08/03 2009/09/03

Compal Electronics, Inc.

Discharge circuit-1

+3VALW to +3VS Transfer

+1.5V to +1.5VS Transfer

+5VALW to +5VS Transfer

L

Add C626,C664 close to JDIMA1;

C656,C657 close to JDIMB1.

Intel S3 power reduction circuit for Calpella. 11/09

discharge circuit-2

Compal, SI 1/11

R1475

470_0402_5%

12

C866

10U_0805_6.3V4K

@

1

2

C1027 0.1U_0402_16V4Z

1 2

C1025 0.1U_0402_16V4Z

1 2

R1323 0_0402_5%

1 2

Q15A

TR 2N7002DW -7-F 2N SOT-363

61

2

R1326

100K_0402_5%

12

C865

10U_0805_10V4Z

1

2

R1474

470_0402_5%

12

J4

PAD-OPEN 2x2m

2 1

Q85B

2N7002DW-7-F_SOT363-6

3

5

4

C861

10U_0805_10V4Z

1

2

Q88B

2N7002DW-7-F_SOT363-6

3

5

4

U28

SI7326DN-T1-E3_PAK1212-8

35

2

4

1

C1024 0.1U_0402_16V4Z

1 2

C868

0.1U_0402_16V7K

1

2

R1444

100K_0402_5%

12

Q30A

2N7002DW-7-F_SOT363-6

61

2

U29

SI7326DN-T1-E3_PAK1212-8

35

2

4

1

Q52B

2N7002DW-7-F_SOT363-6

3

5

4

R1331

470_0402_5%

12

C863

10U_0805_10V4M

1

2

C1026 0.1U_0402_16V4Z

1 2

C1023

0.1U_0402_16V4Z

1

2

Q7B

2N7002DW-7-F_SOT363-6

3

5

4

R1329

470_0402_5%

12

Q9A

2N7002DW-7-F_SOT363-6

61

2

C869

10U_0805_6.3V4K

1

2

Q88A

2N7002DW-7-F_SOT363-6

61

2

C862

0.01U_0402_25V7K

1

2

R1441

0_0402_5%

12

Q64

SI7326DN-T1-E3_PAK1212-8

@

35

2

4

1

Q30B

2N7002DW-7-F_SOT363-6

3

5

4

R693

22_0402_5%

12

R1328

470_0402_5%

12

R1330

470_0402_5%

12

C505

0.01U_0402_16V7K

@

1

2

R1322

330K_0402_5%

12

C867

0.1U_0402_16V7K

@

1

2

C1022

0.1U_0402_16V4Z

1

2

C864

0.1U_0402_16V4Z

1

2

U45

SI7326DN-T1-E3_PAK1212-8

35

2

4

1

R1324

470_0402_5%

12

C860

0.1U_0402_16V4Z

1

2

R1327

0_0402_5%

@

1 2

Q86B

2N7002DWH 2N SOT363-6

3

5

4

C859

10U_0805_10V4Z

1

2

R1473

470_0402_5%

12

Q85A

2N7002DW-7-F_SOT363-6

61

2

Q9B

2N7002DW-7-F_SOT363-6

3

5

4

R1440

220_0402_5%

12

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

SMB_EC_CK1

SMB_EC_DA1

A DPIN

EC_SMD

EC_SMC

B+_DEBUG

SMB_EC_CK1 <29>

SMB_EC_DA1<29>

BAT_ID#<29>

ADP_SIGNAL <39>

ADP_PRES

<22,29,33>

AC_ADP_PRES

<29,33>

EN0 <34>

VIN

VMB BATT_1

+3VL

+3VL

+3VL

BATT

+3VL

VL

2VREF_51125

2VREF_51125

VL

BATT

VIN

B++ 51125_PWR

B+_DEBUG

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

DCIN/BATT/CPU OTP

C u sto m

31 40Tuesday, M ay 18, 2010

2005/03/10 2009/09/03

Compal Electronics, Inc.

Recovery at 47 +-3 degree C

CPU

CPU thermal protection at 90 +-3 degree C

PH1 under CPU botten side :

PU103A

LM393DR_SO8

+

3

-

2O1

P8

G

4

PC6

1000P_0402_50V7K

12

PD4

BAV99WT1G_SC70-3

2

3

1

PQ2A

2N 7002 KDW H-2N_SOT363-6

61

2

PL1

HCB2012KF-121T50_0805

1 2

PR23

100_0805_5%

1 2

PCN2

ACES_51976-00571-001

11

33

44

55

GND 6

GND 7

22

PD7

CH751H-40PT_SOD323-2

2 1

PR8

100_0402_5%

12

PC9

@100P_0402_50V8J

12

G

D

S

PQ3

SSM3K7002FU_SC70-3

2

13

PH1

100K_0402_1%_TSM0B104F4251RZ

12

PC10

@100P_0402_50V8J

12

PD8

RLZ27V

2 1

PC7

0.01U_0402_50V7K

12

PD5

PJSOT24CH_SOT23-3

2

3

1

PR11 470K_0402_5%

12

PD12

1SS355_SOD323-2

12

PR6 210K_0402_1%

1 2

PD6

PJSOT24CH_SOT23-3

2

3

1

PC3

100P_0402_50V8J

12

PR2

470K_0402_1%

1 2

PC2

1000P_0402_50V7K

12

PR9

100_0402_5%

12

PQ2B

2N7002KDWH-2N_SOT363-6

34

5

PR1

@15K_0402_5%

12

G

D

S

PQ4

SSM3K7002FU_SC70-3

2

13

PC15

0.1U_0603_50V7K

12

PR37

0_0402_5%

1 2

PC1

100P_0402_50V8J

12

PL3

HCB2012KF-121T50_0805

1 2

PR14

470K_0402_5%

12

PCN1

ACES_87302-0441

11

33

44

GND 5

22

GND 6

PD1

@PJSOT24C_SOT23-3

2

3

1

PL2

HCB2012KF-121T50_0805

1 2

PR10

21K_0402_1%

12

PC12

1000P_0402_50V7K

12

PR4 1K_0402_1%

12

PR15

150K_0402_1%

12

PD22

1SS355_SOD323-2

12

PR7

75K_0402_1%

1 2

PD3

BAV99WT1G_SC70-3

2

3

1

PU1

74LVC1G14GW _SOT353-5

A2

Y

4

P5

NC 1

G

3

PC11

0.1U_0603_25V7K

12

PQ1

AO4407AL_SO8

3 6

5

7

8

2

4

1

PR12

4.7K_0402_5%

12

PC8

@100P_0402_50V8J

12

PR5

53.6K_0603_1%

1 2

PR13

220K_0402_5%

12

PR3

100K_0402_5%

1 2

PC5

@100P_0402_50V8J

12

PL4

HCB2012KF-121T50_0805

1 2

PC4

1000P_0402_50V7K

12

PD2

BAV99WT1G_SC70-3

2

3

1

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

REGN

DL_ CHG

DH_CHG

LX_CHG

CHG EN#

VADJ

BATT

ACDET

CHGCTRL

ACDET

IADAPT

BST_CHG

CHG EN#

IADAPT

ADP_PRES<22,29,32>

CHGCTRL <29>

BAT_PW M_OUT<29>

SRSET <39>

CELLS

<29>

IADAPT<39>

SLP_S3#

<14,22,29,30,31,35>

AC_ADP_PRES<29,32> PMC <29>

ADP_EN#

<39>

VIN

BATT

VIN

+3VL

VL

CHG_B+

P2

P2

P2

+3VL

BQ24740VREF

+3VL

+3VL

+3VL

B+

CHG_B+

2VREF_51125

2VREF_51125

VL

P2BATT

P4

P4

+3VL

+5VALW

B+

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

Charger

32 40Tuesday, M ay 18, 2010

2007/05/29 2009/09/03

Compal Electronics, Inc.

Charge Detector

High 17.614

Low 17.201

AC Detector

High 13.277

Low 10.770

12/2 For RF request

PC104

4.7U_0805_25V6-K

12

PR135

100K_0402_1%

12

PC134 68P_0402_50V8J

1 2

PR145

49.9K_0402_1%

12

PR103

150K_0402_5%

12

PU102B

LM393DR_SO8

+

5

-

6O7

P8

G

4

C

B

E

PQ108

MMBT3906_SOT23-3

1

2

3

PC106

@0.1U_0603_25V7K

12

PC140 68P_0402_50V8J

1 2

PR140

23.7K_0402_1%

12

PC124

0.1U_0402_10V7K

12

PC117

0.1U_0402_10V7K

1 2

PC127

@4.7U_0805_25V6-K

12

PU103B

LM393DR_SO8

+

5

-

6O7

P8

G

4

PC119

100P_0402_50V8J

12

PR133

100K_0402_5%

1 2

PR117 210K_0402_1%

12

PC121

@0.1U_0603_25V7K

12

PQ105

AO4466L 1N SO8

3 6

5

7

8

2

4

1

PR127

0_0402_5%

1 2

PR139

4.7_1206_5%

12

PR121

255K_0402_1%

1 2

PC122

1U_0603_6.3V6M

12

PC132 0.1U_0402_25V6

12

PR110

453K_0402_1%

12

PR143

100K_0402_5%

12

PC103

4.7U_0805_25V6-K

12

PC135 0.1U_0402_25V6

12

PR104

0_0402_5%

1 2

PQ100

AO4407L_SO8

3 6

5

7

8

2

4

1

PR129

10K_0603_0.1%

12

PQ106

AO4468L_SO8

3 6

5

7

8

2

4

1

PC101

1U_0603_6.3V6M

1 2

PU102A

LM393DR_SO8

+

3

-

2O1

P8

G

4

PR124

200K_0402_1%

12

PR147

11K_0402_1%

1 2

PC128

1U_0603_6.3V6M

12

PR134

0.01_2512_1%

1

3

4

2

PC109

1U_0805_25V6K

1 2

PL100

HCB2012KF-121T50_0805

1 2

PC1380.1U_0402_25V6

12

PC113

4.7U_0805_25V6-K

12

BQ24740RHDR_QFN28_5X5

PU100

ACP 3

LPMD 4

CHGEN 1

ACN 2

ACDET 5

ACSET 6

IADSLP

8

SRP

19

BAT

17

IADAPT

15

PGND 22

SRSET

16

ISYNSET

14

VADJ

12

VDAC

11

LPREF 7

VREF

10

DPMDET

21

LODRV 23

CELLS

20

SRN

18

AGND

9

REGN 24

EXTPWR

13

PH 25

HIDRV 26

BTST 27

PVCC 28

TP 29

PC114

4.7U_0805_25V6-K

12

PR102

200K_0402_5%

1 2

PC123

0.047U_0402_16V7K

12

PR119

604K_0402_1%

1 2

PC100

0.1U_0603_25V7K

1 2

PC107

0.01U_0402_16V7K

12

PC129 68P_0402_50V8J

1 2

PC131 2200P_0402_50V7K

12

PR146

39.2K_0402_1%

1 2

PR125

22K_0402_5%

12

PR100

200K_0402_5%

1 2

PC110

0.1U_0402_10V7K

1 2

PC133 2200P_0402_50V7K

12

PD101

LL4148_LL34-2

12

PC112

4.7U_0805_25V6-K

12

PR131

41.2K_0402_1%

12

PQ101

AO4407AL_SO8

36

5

7

8

2

4

1

G

D

S

PQ103

SSM3K7002FU_SC70-3

2

13

PR138

0_0402_5%

1 2

PL101

10UH +-20% #919AQ-H-100M=P3 5.3A

1 2

PC137 68P_0402_50V8J

1 2

PC108

0.1U_0603_50V7K

12

PR122

47K_0402_5%

1 2

PR136 100K_0402_1%

12

PR141

24.3K_0402_1%

12

PC120

0.1U_0603_50V7K

12

PR142

1M_0402_5%

1 2

PR132

470K_0402_5%

12

PR106

10_0805_1%

1 2

PQ102

AO4407AL_SO8

3 6

5

7

8

2

4

1

PR120

220K_0402_5%

1 2

PC139 2200P_0402_50V7K

12

PR108

0_0402_5%

1 2

PR130

22K_0402_1%

12

PR101

56K_0402_1%

1 2

PR105

150K_0402_5%

12

PC111

1U_0603_6.3V6M

1 2

PD102

1SS355_SOD323-2

12

PR109

0.01_1206_1%

1 2

PR128

1K_0402_5%

1 2

LMV321AS5X-G_SOT23-5

PU104

V-

2

+IN

1

-IN

3OUT 4

V+ 5

PR112

1M_0402_1%

12

PR118

147K_0402_1%

12

PC126

1000P_0603_50V7K

12

PC118

1U_0603_10V6K

12

PR113

43.2K_0402_1%

12

PC102

4.7U_0805_25V6-K

12

PC136 2200P_0402_50V7K

12

PC116

1U_0603_6.3V6M

12

PR123

76.8K_0402_1%

12

PC130 0.1U_0402_25V6

12

PR114

100K_0402_5%

1 2

PR111

422K_0402_1%

1 2

PC115

4.7U_0805_25V6-K

12

PR144

300K_0402_5%

1 2

G

D

S

PQ107

SSM3K7002FU_SC70-3

2

13

PR137

0_0402_5%

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

ENTRIP1

UG1_3V

ENTRIP1

ENTRIP2

DEBUG_KBCRST

BST_ 3V

UG_3V

LX_3V

LG_3V LG_5V

LX_5V

BST_5V

UG_5V

ENTRIP2

KBC_PWR_ON <29>

RPGOOD <14>

DEBUG_KBCRST <28>

VCC1_PWRGD <29,39>

EN0 <32>

B++

+5VALWP

+5VLP

B++

2VREF_51125

B+

+VREG_51125+3VLP

+3VLP

2VREF_51125

VL

+5VALWP

+3VALW

+5VALW

+3VALWP

VL+5VLP

+3VL

+3VALWP +5VALWP

+5VLP

+3VEXTLP

+5VLP

P2

+3VL+3VEXTLP

+3VALWP

B+

51125_PWR

51125_PWR

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

3.3VALWP/5VALWP

C u sto m

33 40Tuesday, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

(4.5A,180mils ,Via NO.= 9)

(3A,120mils ,Via NO.= 6)

PC303

0.1U_0402_25V6

12

PC309

4.7U_0805_6.3V6K

12

PQ302

AO4468L_SO8

3 6

5

7

8

2

4

1

PR311

@4.7_1206_5%

12

PR306 0_0402_5%

1 2

PR303

20K_0402_1%

1 2

PR316

604K_0402_1%

1 2

PR325

220K_0402_5%

12

PC317

10U_0805_10V6K

12

PC322

68P_0402_50V8J

1 2

G

D

S

PQ305

SSM3K7002FU_SC70-3

2

13

PL301

4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%

12

PC314

@680P_0603_50V8J

12

PC305

0.1U_0402_25V6

12

PR305

115K_0402_1%

1 2

PC315

@680P_0603_50V8J

12

PR308

0_0402_5%

1 2

PC320

2.2U_0805_10V6K

12

PJP300

PAD-OPEN 4x4m

1 2

PC302

2200P_0402_50V7K

12

PR302

20K_0402_1%

1 2

PR323

64.9K_0402_1%

12

PR327 20K_0402_1%

12

PR307

0_0402_5%

1 2

PC311

0.1U_0402_10V7K

1 2

PC321

1U_0603_10V6K

12

PR304

105K_0402_1%

1 2

PJP304

PAD-OPEN 2x2m

2 1

PR315 100K_0402_1%

12

PQ304A

2N 7002 KDW H-2N_SO T363-6

61

2

PL302

4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%

1 2

PJP301

PAD-OPEN 4x4m

1 2

PJP303

PAD-OPEN 2x2m

2 1

PC306

2200P_0402_50V7K

12

PC319

10U_0805_10V6K

12

PR301

30.9K_0402_1%

1 2

PD302

1SS355_SOD323-2

12

PC3100.1U_0402_10V7K

1 2

PC323

68P_0402_50V8J

1 2

PR309

0_0402_5%

1 2

PC316

0.1U_0603_25V7K

12

PJP302

PAD-OPEN 2x2m

2 1

PC307

4.7U_0805_25V6-K

12

PR300

13.7K_0402_1%

1 2

PQ301

SIS412DN-T1-GE3 1N POWERPAK1212-8

3 5

2

4

1

PR317

100K_0402_5%

1 2

PQ304B

2N 7002 KDW H-2N_SOT363-6

34

5

PQ300

SIS412DN-T1-GE3 1N POWERPAK1212-8

3 5

2

4

1

PR320

255K_0402_1%

12

PR326

470K_0402_5%

12

PC318

10U_0805_10V6K

12

PR310

@4.7_1206_5%

12

LMV321AS5X-G_SOT23-5

PU302

V-

2

+IN

1

-IN

3OUT 4

V+ 5

+

PC312

150U_B2_6.3VM_R45M

1

2

PR321

100K_0402_1%

12

PR318

330K_0402_5%

12

PC300

1U_0603_16V7

12

PL300

HCB2012KF-121T50_0805

1 2

PU300

TPS51125RGER QFN 24P

VREF 3

TONSEL 4

ENTRIP1 1

VFB1 2

VFB2 5

ENTRIP2 6

VREG3

8

DRVL1 19

VREG5

17

GND

15

VBST1 22

VIN

16

SKIPSEL

14

DRVL2

12

LL2

11

VO2

7

DRVH2

10 DRVH1 21

PGOOD 23

LL1 20

VCLK

18

VBST2

9

VO1 24

EN0

13

P PAD

25

+

PC313

150U_B2_6.3VM_R45M

1

2

APL5317

PU303

GND

2

VIN

1

EN

3FB 4

VOUT 5

PR314

@100K_0402_5%

12

PR312

@499K_0402_1%

1 2

PR324 16.5K_0402_1%

12

PR331

680K_0402_5%

1 2

PR322

11.5K_0402_1%

12

PD301

1SS355_SOD323-2

12

PD304

1SS355_SOD323-2

12

PC308

4.7U_0805_25V6-K

12

PQ303

IRF8707GTRPBF 1N SO8

4

7

8

6

5

1

2

3

PC304

4.7U_0805_25V6-K

12

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

+VCCP

LX_VCCP

D H_ VC C P

D H_ V CCP1

F B_ VCC P

VCCP_B+

BST_VCCP

DL_VCCP

SE_VCCP

+VCCP

SLP_S3#<14,22,29,30,31,33>

VCCP_POK

<30>

VCCP_EN<30>

VTT_SENSE <7>

+6269_VCC

+6269_VCC

+VCCP

+5VALW

+VCCP

B+

+3VS

+VCCP +1.05VS

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

1.05V_VCCP

34 40Tuesday, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

(18A,720mils ,Via NO.= 36)

PR405

0_0402_5%

1 2

+

PC418

220U_B2_2.5VM_R25M

1

2

PR417

0_0603_5%

1 2

+

PC409

330U_D2_2V_Y

1

2

PR406

@0_0402_5%

1 2

PC417

@0.1U_0402_25V6

12

PL401

HCB2012KF-121T50_0805

1 2

PC419

68P_0402_50V8J

1 2

PQ402

AON6718L 1N DFN

3 5

2

4

1

PR412

2.94K_0402_1%

12

PC405

0.22U_0603_10V7K

1 2

PJP401

PAD-OPEN 4x4m

1 2

PR402

2.2_0603_5%

1 2

PR407

8.06K_0402_1%

1 2

PC403

4.7U_0805_25V6-K

12

PR403

0_0402_5%

12

+

PC410

330U_D2_2V_Y

1

2

PR428

0_0402_5%

1 2

PC413

0.01U_0402_16V7K

12

PR427

10K_0402_5%

12

PC406

2.2U_0805_10V6K

1 2

PU401

ISL6269ACRZ-T_QFN16

FCCM

3

EN

4

BOOT 13

PVCC 12

VIN

1

VCC

2

PGOOD 16

PHASE 15

UG 14

LG 11

PGND 10

VO

8

COMP

5

FB

6

FSET

7

ISEN 9

GND 17

PC416

0.1U_0402_25V6

12

PC415

2200P_0603_50V7K

12

PC407

2.2U_0805_10V6K

12

PR410

49.9K_0402_1%

12

PR411

2.21K_0402_1%

1 2

PC401

2200P_0402_50V7K

12

PR404

2.2_0603_5%

1 2

PC412

680P_0603_50V7K

1 2

PR413

10_0402_5%

1 2

PL402

0.36UH 20% FDU1040J-H-R36M=P3 33A

1 2

PC404

4.7U_0805_25V6-K

12

+

PC408

330U_D2_2V_Y

1

2

PQ401

AO4474L_SO8

3 6

5

7

8

2

4

1

PC414

33P_0402_50V8J

12

PR401

@10K_0402_5%

12

PR408

2.2_1206_5%

12

PC402

4.7U_0805_25V6-K

12

PR409

25.5K_0402_1%

12

PR414

0_0402_5%

1 2

PC411

@0.1U_0402_10V7K

12

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

1.8VS_POK

<30>

SLP_S3#

<14,22,29,30,31,33>

+0.75VSP

+5VALW

+5VALW

+0.75VS

+0.75VSP

+1.8VS

+1.8VSP

+5VALW

+1.8VSP

+1.8VSP

+1.5V

+1.5VS_CPU_VDDQ

+1.5V

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

0.75VSP/1.8VSP

35 40Tuesday, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

(1.5A,60mils ,Via NO.= 3)

(2A,80mils ,Via NO.= 4)

G

D

S

PQ602

SSM3K7002FU_SC70-3

2

13

G

D

S

PQ601

SSM3K7002FU_SC70-3

2

13

PC613

0.1U_0402_16V7K

1 2

PJP601

PAD-OPEN 3x3m

1 2

PR609

0_0402_5%

1 2

PC609

10U_0805_10V6K

1 2

PR612

@0_0805_5%

1 2

PC604

0.1U_0402_10V7K

12

PC610

10U_0805_10V6K

12

PR604

20K_0402_1%

1 2

PR606

4.7_1206_5%

12

PC602

10U_0805_6.3V6M

12

PD602

@B340A_SMA2

12

PC603

1U_0603_10V6K

12

PR608

402K_0402_1%

12

PC614

22U_0805_6.3V6M

12

PC615

22U_0805_6.3V6M

12

PU601

G2992F1U_SO8

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

PC611

0.1U_0402_25V6

12

PR611

@1K_0402_1%

12

PR605

0_0402_5%

1 2

PL601

HCB1608KF-121T30_0603

1 2

PR610

0_0805_5%

1 2

PC601

10U_0805_6.3V6M

12

PR601

1K_0402_1%

12

PR603

1K_0402_1%

12

PR602

10K_0402_5%

12

PC608

@0.1U_0402_16V7K

12

PC605

10U_0805_6.3V6M

12

PL602

1.2UH +-30% 1231AS-H-1R2N=P3 2.9A

1 2

PC606

.1U_0402_16V7K

12

PD601

1SS355_SOD323-2

1 2

PC612

680P_0603_50V7K

12

PJP602

PAD-OPEN 3x3m

1 2

PU602

MP2121DQ-LF-Z_QFN10_3X3

SW

3

GND

2

IN 7

GND 9

SW 8

POK 6

EN/SYNC 10

BS

5

IN

4

FB

1

TP 11

PR607

316K_0402_1%

1 2

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

+5VALW

BST_1.5V

UG1_1.5V

LG_1.5V

+5VALW

LX_1.5V

UG_1.5V

SLP_S4#<14,25>

+1.5V

+1.5V

B+

+5VALW

+1.5V

+1.5V_B+

Title

Size D o cument Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

1.5VP

36 40Tuesday, M ay 18, 2010

2008/10/31 2009/09/03

Compal Electronics, Inc.

PQ801

SIS412DN-T1-GE3 1N POWERPAK1212-8

3 5

2

4

1

PU801

RT8209BGQW_WQFN14_3P5X3P5

VOUT

3

VDD

4

EN/DEM 1

TON

2

FB

5

PGOOD

6LGATE 9

UGATE 13

PHASE 12

GND

7

PGND

8

CS 11

VDDP 10

BOOT 14

NC 15

PC808

4.7U_0805_10V6K

12

PR803

255K_0402_1%

1 2

PR807 12.4K_0402_1%

1 2

PR806

316_0402_1%

1 2

PC809

@10P_0402_50V8J

1 2

PR805 0_0402_5%

1 2

PC807

1U_0603_10V6K

12

PC803

0.1U_0402_25V6

12

PC805

4.7U_0805_25V6-K

12

PR810 10K_0402_1%

12

PR809

@4.7_1206_5%

12

+

PC811

220U_B2_2.5VM_R25M

1

2

PL801

HCB1608KF-121T30_0603

1 2

PR808 10K_0402_1%

1 2

PL802

2.2UH 20% FDVE0630-H-2R2M=P3 8.3A

1 2

PQ802

IRF H3707TRPBF 1N PQFN

3 5

2

4

1

PR802

2.2_0402_5%

1 2

PC813

68P_0402_50V8J

1 2

PC801

@0.1U_0402_16V7K

12

PC812

@680P_0603_50V8J

12

PC804

4.7U_0805_25V6-K

12

PR804

0_0402_5%

1 2

PR801

0_0402_5%

1 2

PC806

0.1U_0402_10V7K

1 2

PC802

2200P_0402_50V7K

12

PC810

4.7U_0805_6.3V6K

12

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

H GA TE _ C PU2

H _V ID0

H _V ID1

H _V ID2

H _V ID6

H _V ID3

H _V ID0

H _V ID1

H _V ID2

H _V ID6

H _V ID3

P ROC _D PR SLP VR

H _V ID4

P ROC _D PR SLP VR

H _V ID5

H _V ID4

H _V ID5

CPU _ S N -2

C P U _ CS N 2

C PU _CSP2

CPU _ C S P2 -1

Ph a se _C P U2

C PU _SNB2

LG A T E _CPU2

C PU _PGOO D

C P U _ VR _O N

C P U _ VR EF

C P U _ CS N 2

C P U _ CS N 1

CPU _ C S P2 -2

C PU _CSP1

C PU _CSP2

CPU _ C S N 1-1

CPU _ C S N 2-1

C PU _ISLEW

CPU _ M O DE

C P U _ DR O OP

C PU _VSNS

VS S SE N SE

C PU _T R I PSE L

C P U _ GN D SN S

C PU _T O N SEL C P U _ VR EF

CPU _ C L K_EN#

CPU _ I M O N

CPU _ VR_TT#

CPU _ O SRSEL

C PU _T H ER M

H GA TE _ C PU1

CPU _ C S P1 -1

PH A S E_CPU1

LG A T E _CPU1

CPU _ S N -1

C P U _ CS N 1

C PU _CSP1

C PU _SNB1

PS I # P SI#

CPU _ 5 V FILT

CPU _ C S P1 -2

C PU _5 V FI LTPS I #_ 1

CPU _ C S N 2-1

CPU _ C S P2 -2

PS I #_ 1

V C CS EN SE<7>

P G D_ IN< 14, 29>

H _V ID 1<7>

H _V ID 0

<7>

IMVP_IMON

<7>

VS S SENSE

<7>

H_V I D 5

<7>

H _V ID 4<7>

H _V ID 3<7>

H _V ID 2

<7>

PS I#

<7>

CLK _ EN#<11>

VGATE<12,14>

H _V ID 6

<7>

H_P R O C H OT#

<4>

P R OC _D PR SL PV R

<7>

+VC C P

B+

CPU_B+

+ C PU _C OR E

+ VC C P

+5V ALW

+3V ALW

+5V ALW

+5V ALW

CPU_B+

+5V ALW

Title

Size Doc um e nt Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

L A- 61 61 P

CPU_CORE

C

37 40Tue s d ay, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

Arrandale

VID(6-0): 0100111

VID(6-0): 0011111

VID(6-0): 0010111

SV

LV

ULV

PR 21 9 0_04 02_5%

1 2

PL 202

0. 36 U H 20% FDU10 4 0J-H-R36M=P3 33A

1

3

4

2

PC225

4. 7U _ 0805_25V6-K

12

TPS 5 1621R HAR_QFN40_6X6

PU201

MODE

1

GND

2

CSP2

3

CSN2

4

CSN1

5

CSP1

6

GNDSNS

7

VSNS

8

THERM

9

VR_TT#

10

IMON

11

DPRSLPVR

12

PSI#

13

VID6

14

VID5

15

VID4

16

VID3

17

VID2

18

VID1

19

VID0

20

DRVH1 21

VBST1 22

LL1 23

DRVL1 24

PGND 25

V5IN 26

DRVL2 27

LL2 28

VBST2 29

DRVH2 30

TRIPSEL 31

OSRSEL 32

PGOOD 33

CLK_EN# 34

VR_ON 35

TONSEL 36

ISLEW 37

V5FILT 38

DROOP 39

VREF 40

GND 41

PR 2 5 3 1K_0402_5%

12

PR 2 6 7 0_0402_5%

1 2

PR 2 25 0_ 0 402_5%

12

PC207

4. 7U _ 0805_25V6-K

12

PQ 2 07

TPC A8 036-H 1N SOP-ADV

4

1

2

3 5

PR243

@0_0402_5%

12

PR 2 6 5 @ 0_0402_5%

1 2

PC 2 09

68 P _0402_50V8J

1 2

PR206 @1K_0402_5%

1 2

PR 2 1 8 2.2_0603_5%

1 2

PR 2 56 1K _ 0402_5%

12

PD 2 01

1S S 355_SOD323-2

1 2

PC226

4. 7U _ 0805_25V6-K

PR201

47K_0402_1%

1 2

PC211

680P_0402_50V7K

12

PR205 220_0402_5%

PQ 2 05

TPC A8 030-H 1N SOP-ADV

4

1

2

3 5

PR 2 58 @1K_0402_5%

12

PR 2 5 7 @ 1K_0402_5%

12

PR 2 1 0 249K_ 0402_1%

1 2

PR 22 4 2.2_0 603_5%

12

PC 20 8 2.2U_0 603_10V6K

1 2

PC224

4. 7U _ 0805_25V6-K

PR 2 2 3 470_0402_1%

12

PR 2 62 @1K_0402_5%

12

PR 2 46 1K _ 0402_5%

12

PC206

4. 7U _ 0805_25V6-K

PR227 20K_0402_1%

1 2

PC202

4. 7U _ 0805_25V6-K

PR 2 4 7 @ 1K_0402_5%

12

PR212 0_0402_5%

1 2

PC231

4. 7U _ 0805_25V6-K

12

PC 2 1 8 4.7U_06 03_10V6K

1 2

PR 2 52 @1K_0402_5%

12

PD202 1SS 3 55_SOD323-2

1 2

PC221

0. 22 U _0603_10V7K

1 2

PC228

0. 03 3U_0402_16V7K

12

PR 2 6 6 @ 0_0402_5%

1 2

PR 2 15

17 . 8 K +-1% 0603

12

PR 2 17 28 . 7 K_0402_1%

1 2

PC 2 15 33 P _0402_50V8J

1 2

PC220

10 0 P_0402_50V8J

12

PC232

68 P _0402_50V8J

1 2

PC222

0. 1U _ 0402_25V6

12

PR213 0_0 4 02_5%

1 2

PC227

680P_0402_50V7K

12

PL 203

0. 36 U H 20% FDU10 4 0J-H-R36M=P3 33A

1

3

4

2

PR 2 2 0 470_0402_1%

12

PC 219 33 P_0402_50V8J

1 2

PR 2 48 1K _ 0402_5%

12

PC229

0. 03 3U_0402_16V7K

1 2

PR242

69.8K_0402_1%

1 2

PQ 201

TPC A8 030-H 1N SOP-ADV

4

1

2

3 5

PR 2 2 8 0_0402_5%

1 2

PR 204 0_ 0402_5%

1 2

PR 2 2 1 470_0402_1%

12

+

PC 2 03

68 U _ 25V_M_R0.36

1

2

PC 2 1 7 33P_0 402_50V8J

1 2

PR 2 6 4 @ 0_0402_5%

1 2

PR 2 0 9 5.23K_0402_1%

12

PR241

17 . 8 K +-1% 0603

12

PR 2 03 0_ 0 402_5%

1 2

PC210

0. 22 U _0603_10V7K

1 2

PQ 2 03

TPC A8 036-H 1 N SOP-ADV

4

1

2

3 5

PR216

69.8K_0402_1%

1 2

PR 2 60 1K _ 0402_5%

12

PR 2 2 2 470_0402_1%

12

PL 2 04

HCB2 0 12KF-121T50_0805

1 2

PR 2 4 9 @ 1K_0402_5%

12

PC212

10 0 P_0402_50V8J

12

PC223

2200P_0402_50V7K

12

PH201

10 0 K_04 0 2_1%_TSM0B104F4251RZ

1 2

PC213

0. 03 3U_0402_16V7K

1 2

PR245 28.7K_0402_1%

1 2

PH202

10 0 K_04 0 2_1%_TSM0B104F 4251RZ

1 2

PR 2 5 5 1K_0402_5%

12

PR 2 50 1K _ 0402_5%

12

PR 2 6 3 1K_0402_5%

12

PC205

2200P_0402_50V7K

12

PR 2 5 9 1K_0402_5%

12

PR240

4.7_1206_5%

12

PR 2 5 1 @ 1K_0402_5%

12

PR 2 6 1 @ 1K_0402_5%

12

PR 2 2 9 68_0402_5%

1 2

PR 2 2 6 0_0402_5%

12

PC201

0. 1U _ 0402_25V6

12

PC230

4. 7U _ 0805_25V6-K

12

PR 2 44

12.4K_0402_1%

12

PL 2 01

HCB2 0 12KF-121T50_0805

1 2

PR 2 14

4. 7_ 1206_5%

12

PR 2 1 1 0_0402_5%

1 2

PR 2 54 @1K_0402_5%

12

PC233

68 P _0402_50V8J

1 2

PR230 0_0 4 02_5%

1 2

+

PC 2 04

68 U _ 25V_M_R0.36

1

2

PC214

0. 22 U _0603_10V7K

1 2

PC 21 6 33P_ 0402_50V8J

1 2

PR202

@1K_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADP_A_ID

ADP_A_ID

OCP_A_IN

ADP_PRES

IADAPT<33>

OCP# <15>

SRSET <33>

OCP<29>

ADP_EN# <33>

VCC1_PWRGD <29,34>

ADP_DET# <29>

ADP_A_ID <29>

OCP_A_IN <29>

ADP_EN <29>

ADP_SIGNAL<32>

ADP_PRES<33>

+3VS

+3VL

+3VS

+5VS

BQ24740VREF

+3VL

VIN

+3VL

VL

2VREF_51125

VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

ADP_OCP

Custom

38 40Tuesday, May 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

PR1017

2K_0402_5%

12

PR1067

110K_0402_1%

1 2

PR1028

100K_0402_5%

1 2

PR1059

45.3K_0402_1%

12

PR1031

80.6K_0402_1%

12

E

B

C

PQ1009

MMBT3904WH SOT323-3

2

3 1

PR1042

8.06K_0402_1%

12

PR1025

3.9K_0402_5%

12

PC1000

0.1U_0603_16V7K

1 2

PC1003

3900P_0402_50V7K

1

2

PR1040

33K_0402_5%

12

PR1066

10K_0402_5%

1 2

PR1027 100K_0402_1%

1 2

PR1026

100K_0402_1%

12

PR1029

100K_0402_1%

1 2

PR1018

105K_0402_1%

12

PR1019

10K_0402_5%

1 2

PR1030

68K_0402_5%

12

PC1001

0.01U_0402_16V7K

12

PR1062

1M_0402_5%

1 2

PD1003

GLZ4.7B_LL34-2

12

PR1034 200K_0402_1%

1 2

PU1001A

LM393DR_SO8

+

3

-

2O1

P8

G

4

LMV321AS5X-G_SOT23-5

PU1000

V-

2

+IN

1

-IN

3OUT 4

V+ 5

E

B

C

PQ1005

MMBT3904WH SOT323-3

2

3 1

PR1033 @0_0402_1%

1 2

PR1020

0_0402_5%

1 2

PU1001B

LM393DR_SO8

+

5

-

6O7

P8

G

4

PD1004

1SS355_SOD323-2

12

PR1065

10K_0402_1%

12

PQ1007B

2N7002KDW-2N_SOT363-6

34

5

PR1022

100_0402_5%

1 2

PQ1007A

2N7002KDW-2N_SOT363-6

61

2

PR1035

10K_0402_5%

<BOM Structure>

1 2

G

D

S

PQ1003

NDS0610_NL_SOT23-3

2

13

PC1004

0.01U_0402_16V7K

12

PR1045

4.7K_0402_5%

12

PR1013

10K_0402_1%

1 2

G

D

S

PQ1004

SSM3K7002FU_SC70-3

2

13

PR1064

22K_0402_5%

12

G

D

S

PQ1008

@SSM3K7002FU_SC70-3

2

13

PR1000

511K_0402_1%

12

PR1063

130K_0402_1%

12

PR1046

8.66K_0402_1%

12

PD1001

1SS355_SOD323-2

1 2

PR1032

100_0402_5%

1 2

C

B

E

PQ1006

MMBT3906_SOT23-3

1

2

3

PD1000

1SS355_SOD323-2

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GF X _I R EF

GFX_RPM

GF X _ VCC

GF X _ CSCOMP

GF X _CO MP- 1

GF X _FB

GF X _RA MP

GF X _RA MP- 1

GF X _D R VH

GFX_RT

GF X _ VCC

GF X _C S FB

GF X _EN

GF X _ CSCOMP

GF X _IM ON

GFX_BOOST

GF X _ CSCOMP

GF X _D R VL

GF X _CO MP

GFX_BOOST-1

GFX_ILIM

GF X _SW

GF X _ VID 0

GF X _ VID 1

GF X _ VID 3

GF X _ VID 2

GF X _ VID 4

GF X _ VID 5

GF X _ VID 6

+GFX_CORE

+5VALW

+GFX_B+

+5VALW

+GFX_B+

B+

+GFX_CORE

+VCCP

+GFX_CORE

GF X V R_EN <7>

GF X V R _VID_6 <7>

GF X V R _VID_5 <7>

GF X V R _VID_4 <7>

GF X V R _VID_3 <7>

GF X V R _VID_2 <7>

GF X V R _VID_1 <7>

GF X V R _VID_0 <7>

VS S _AXG_SENSE

<7>

VC C _ A XG_SENSE

<7>

GF X V R_IMON<7>

Title

Size Doc u m e nt Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

L A- 61 61 P

GFX_CORE

C

39 40Tue s d ay, M ay 18, 2010

2008/09/15 2009/09/03

Compal Electronics, Inc.

PR 7 18

1K _ 0402_1%

1 2

PC711

220P_0402_50V7K

1 2

PC717

680P_0402_50V7K

12

PQ 701

AO 4 474L_SO8

4

7

8

6

5

1

2

3

PR710 0_0402_5%

1 2

PR708 0_0402_5%

1 2

PC716

1200P_0402_50V7K

12

PC 7 12

2. 2U _ 0603_10V6K

12

PR 7 2 1 80.6K_0402_1%

1 2

PR 7 3 0 1K_0402_1%

12

PR 7 2 2 237K_0402_1%

1 2

PR709 0_0402_5%

1 2

PC 7 06

4. 7U _ 0805_25V6-K

12

PR712

10 _ 0603_1%

1 2

PC 7 05

4. 7U _ 0805_25V6-K

PC 7 03

2200P_0402_50V7K

12

PR 7 24 0_ 0 402_5%

1 2

PR707 0_0402_5%

1 2

PC710

10 0 0P_0402_50V7K

12

PR 7 29

54.9K_0603_1%

12

PR719

20K_0402_1%

1 2

PC709

0. 22 U _0603_25V7K

1 2

PR705 0_0402_5%

1 2

PC713

47 P _0402_50V8J

12

PR727

71.5K_0402_1%

12

PR 7 01 @10K_0402_1%

12

PR715

6.98K_0402_1%

12

PU701

AD P 3 211AM N R2G_QFN32_5X5

GPU

7

PWRGD

1

IMON

2

CLKEN#

3

FBRTN

4

FB

5

COMP

6

ILIM

8

IREF

9

RPM

10

RT

11

RAMP

12

LLINE

13

CSREF

14

CSFB

15

CSCOMP

16

VCC 24

BST 23

DRVH 22

SW 21

PVCC 20

DRVL 19

PGND 18

AGND 17

EN 32

VID0 31

VID1 30

VID2 29

VID3 28

VID4 27

VID5 26

VID6 25

AGND 33

PR 73 1 100_ 0402_5%

1 2

PH701 220 K _0402 _5%_ERTJ0EV224J~D

1 2

PL 701

HCB2 0 12KF-121T50_0805

1 2

PC 7 19

10 0 0P_0402_50V7K

12

PC715

680P_0603_50V7K

12

PC 7 04

4. 7U _ 0805_25V6-K

12

PC701

1U _ 0 805_25V6K

12

PC714

470P_0402_50V8J

1 2

PC708

0. 05 6U_0402_16V7K

12

PL 702

.56U H + - 20% ET Q P4LR56 WFC 21A

1

3

4

2

PR 7 32 100_0402_5%

1 2

PR717

4. 7_ 1206_5%

12

PR 7 20 10 . 7 K_0402_1%

1 2

PC720

68 P _0402_50V8J

1 2

PQ 7 02

AO N 6 718L_ D FN8-5

4

5

1

2

3

PR711 0_0402_5%

1 2

PR 7 2 6 422K_0402_1%

12

PR 7 2 5 0_0402_5%

1 2

PC 7 02

0. 1U _ 0402_25V6

12

PR704 0_0402_5%

1 2

PR728

16 5 K_0402_1%

12

PR714

0_0402_5%

1 2

PR 7 2 3 340K_0402_1%

1 2

PR 7 13

@300K_0402_1%

12

PR703

@0_0402_5%

1 2

PR716

2. 2_ 0603_5%

1 2

PC718

1000P_0402_50V7K

12

PR 7 06 0_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Do c ument Numbe r R ev

Da te : Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

DB- 5 80

Changed - List Power History

C us t om

40 <P age Co unt>Tue sday, M ay 18, 201 0

2005/03/10 2009/09/03

Compal Electronics, Inc.

P38

2

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date Phase

1

10

4

8

P38

9

3

Modify the throttling setting level and

action speed.

Change PR1013 to 10k, PR1000 to 511k,

PR1018 to 105k, and PC1000 to 0.1uF. 01/28 SI

IN AC mode, the performance will reduce

through IADAPT without PQ1008. Add PQ1008.

02/01

SI

OTP setting is setted same with other project. P31 Change PR5 to 53.6k and PR10 to 19.1k.

330uF ESR=9mOhm can pass VCCP rippe spec. P34 Change PR408, PR409, and PR410 to

330uF_9mOhm.

01/29

SI

SI

02/02

Tune Loadline and transient response of GFX. P39 Change PR729 to 54.9k, PC716 to 1200pF,

and PC717 to 680pF.

01/27 SI

Add boost resistance for RF team. P36 Change PR802 to 2.2ohm.

01/27 SI

Tune Loadline and transient response of CPU. P37 Change PR209 to 5.23k.

SI01/28

5

6

7

CPU thermal protection fine-tune. P31 Change PR10 to 21K from 19.1K 03/26 PV

For ULV CPU, need reserved some components. P37 Add PR264, PR265, PR266 locations which is

reserved.

For CPU accuracy get better.

03/26 PV

P37 Change PR215 and PR241 to 0603 size

and keep 17.8K 03/26 PV

11 For Electrical Noise Issue. P37 Add PC204, whcih is 68u

11 For EMI request. P32 Add snabber, PR139 to 4.7ohm, PC126 to 1n

03/31

03/31

PV

PV

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-6161P

0.5

HW Changed-List History-1

41 41Tuesday, May 18, 2010

2007/08/02 2009/09/15

Compal Electronics, Inc.

V ersio n C h an g e L ist

V ersio n C h an g e L istV ersio n C h an g e L ist

V ersio n C h an g e L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

It e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c rip t io n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D e s c r ip t io n

lu t io n D es c rip tio nlu t io n D e s c r ip t io n

lu t io n D es c rip tio n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

1

11

1

2 8

2 82 8

2 8

C

CC

C o m p a l

o m p a lo m p a l

o m p a l

Q u i c k

Q u i c kQ u i c k

Q u i c k l o o k / w eb

lo o k / w eb lo o k / w e b

lo o k / w eb

1 2

1 21 2

1 2 / 2 4

/ 2 4/ 2 4

/ 2 4

0 . 2

0 . 20 . 2

0 . 2

T h e L E D S ta tu s a b o u t W ir e le s s/ Q u ic k L o o k 3

T h e L E D S ta tu s a b o u t W ir e le s s/ Q u ic k L o o k 3T h e L E D S ta tu s a b o u t W ir e le s s/ Q u ic k L o o k 3

T h e L E D S ta tu s a b o u t W ir e le s s/ Q u ic k L o o k 3 /

/ /

/

Q u ic k W e b is a b n o rm a l . O T S #

Q u ic k W e b is a b n o rm a l . O T S #Q u ic k W e b is a b n o rm a l . O T S #

Q u ic k W e b is a b n o rm a l . O T S # 6 0 3 77 8

603778603778

603778

A P P _ B U T T O N _ 1 A P P _ B U T T O

A P P _ B U T T O N _ 1 A P P _ B U T T OA P P _ B U T T O N _ 1 A P P _ B U T T O

A P P _ B U T T O N _ 1 A P P _ B U T T O N _ 2 a d d 1 0 0 k o h m p u ll

N _ 2 a d d 1 0 0 k o h m p u ll N _ 2 a d d 1 0 0 k o h m p u ll

N _ 2 a d d 1 0 0 k o h m p u ll

h ig h t o

h ig h t o h ig h t o

h ig h t o + 3 V L

+ 3 V L+ 3 V L

+ 3 V L

2

22

2

2 8

2 82 8

2 8 P W

P WP W

P W R L E D

R L E DR L E D

R L E D

1 2

1 21 2

1 2 / 2 4

/ 2 4/ 2 4

/ 2 4 C

CC

C o m p a l

o m p a lo m p a l

o m p a l P

PP

P W R L E D c a n 't f la s h in S 3 . O T S # 6 0 3 7 7 4

W R L E D c a n 't f la s h in S 3 . O T S # 6 0 3 7 7 4W R L E D c a n 't f la s h in S 3 . O T S # 6 0 3 7 7 4

W R L E D c a n 't f la s h in S 3 . O T S # 6 0 3 7 7 4 C h a n g e

C h a n g e C h a n g e

C h a n g e S T B _ L E D s ig n a l f r o m K B C p in 1 0 5 t o p in 1 1 5

S T B _ L E D s ig n a l f r o m K B C p in 1 0 5 t o p in 1 1 5S T B _ L E D s ig n a l f r o m K B C p in 1 0 5 t o p in 1 1 5

S T B _ L E D s ig n a l f r o m K B C p in 1 0 5 t o p in 1 1 5

0 . 2

0 . 20 . 2

0 . 2

3

33

3

2 2

2 22 2

2 2 W

WW

W W A N

W A NW A N

W A N

1 / 4

1 / 41 / 4

1 / 4 C

CC

C o m p a l

o m p a lo m p a l

o m p a l th e L E D p a n e l w a s a u t o t u rn o n w h h e n

th e L E D p a n el w a s a u t o t u r n o n w h h e nth e L E D p a n el w a s a u t o t u r n o n w h h e n

th e L E D p a n el w a s a u t o t u r n o n w h h e n p lu g in A C .

p lu g in A C . p lu g in A C .

p lu g in A C .

O

OO

O T S # 6 0 3 7 8 6

T S # 6 0 3 7 8 6T S # 6 0 3 7 8 6

T S # 6 0 3 7 8 6

0 . 2

0 . 20 . 2

0 . 2

c

cc

c o r r e ct t h e J W W A N 1 p in 2 4 p o w e r r a il f ro m

o r re c t t h e J W W A N 1 p in 2 4 p o w e r ra il f r o m o r re c t t h e J W W A N 1 p in 2 4 p o w e r ra il f r o m

o r re c t t h e J W W A N 1 p in 2 4 p o w e r ra il f r o m

+ 3 V S

+ 3 V S + 3 V S

+ 3 V S to + 3 V _ W W A N

to + 3 V _ W W A Nt o + 3 V _ W W A N

to + 3 V _ W W A N

4

44

4

2 3

2 32 3

2 3 A u d

A u dA u d

A u d i o

i oi o

i o

1 / 5

1 / 51 / 5

1 / 5 C

CC

C o m p a l

o m p a lo m p a l

o m p a l a u d io n o f u n c t t io n . O T S # 6 0 3 7

a u d io n o f u n c t t io n . O T S # 6 0 3 7a u d io n o f u n c t t io n . O T S # 6 0 3 7

a u d io n o f u n c t t io n . O T S # 6 0 3 7 7 7

7 77 7

7 7 d

dd

d ele t D 1 6

e let D 1 6e let D 1 6

e let D 1 6

0 . 2

0 . 20 . 2

0 . 2

5

55

5

2 2

2 22 2

2 2 W L

W LW L

W L A N

A NA N

A N

1 / 6

1 / 61 / 6

1 / 6 C

CC

C o m p a l

o m p a lo m p a l

o m p a l D e

D eD e

D e b u g p o r t 8 0 is n o t u se d

b u g p o r t 8 0 is n o t u se db u g p o r t 8 0 is n o t u se d

b u g p o r t 8 0 is n o t u se d d e le t e

d e le t e d e le t e

d e le t e s ig n a l o f P C I _ R S T # ,C L K _ P C I_ D E B U G ,

sig n a l o f P C I _ R S T # ,C L K _ P C I _ D E B U G ,sig n a l o f P C I _ R S T # ,C L K _ P C I _ D E B U G ,

sig n a l o f P C I _ R S T # ,C L K _ P C I _ D E B U G ,

L P C _ L F R A M E # ,L P C _ L

L P C _ L F R A M E # ,L P C _ LL P C _ L F R A M E # ,L P C _ L

L P C _ L F R A M E # ,L P C _ L A D 3 ,2 ,1 ,0 a n d r e m o v e C 1 3 1 7 , R 2 7 0

A D 3 ,2 ,1 ,0 a n d r e m o v e C 1 3 1 7 , R 2 7 0A D 3 ,2 ,1 ,0 a n d r e m o v e C 1 3 1 7 , R 2 7 0

A D 3 ,2 ,1 ,0 a n d r e m o v e C 1 3 1 7 , R 2 7 0

0 . 2

0 . 20 . 2

0 . 2

6

66

6

1 1 , 2 1

1 1 , 2 11 1 , 2 1

1 1 , 2 1

1 / 6

1 / 61 / 6

1 / 6 C

CC

C o m p a l

o m p a lo m p a l

o m p a l re s ist a n c e to o sm a ll w ill im p a ct t h e S M T l

re s is t a n ce t o o s m a ll w ill im p a c t th e S M T lre s is t a n ce t o o s m a ll w ill im p a c t th e S M T l

re s is t a n ce t o o s m a ll w ill im p a c t th e S M T l in e

in ein e

in e

y ie ld r a t e

y ie ld r a t e yie ld r a t e

y ie ld r a t e

c h a n

c h a nc h a n

c h a n g e R 1 4 5 7 , R 1 4 5 8 ,R 1 0 2 7 f ro m 0 2 0 1 t o 0 4 0 2

g e R 1 4 5 7 , R 1 4 5 8 ,R 1 0 2 7 f r o m 0 2 0 1 t o 0 4 0 2g e R 1 4 5 7 , R 1 4 5 8 ,R 1 0 2 7 f r o m 0 2 0 1 t o 0 4 0 2

g e R 1 4 5 7 , R 1 4 5 8 ,R 1 0 2 7 f r o m 0 2 0 1 t o 0 4 0 2

0 . 2

0 . 20 . 2

0 . 2

7

77

7

2 3

2 32 3

2 3 A u d

A u dA u d

A u d i o

i oi o

i o

1 / 6

1 / 61 / 6

1 / 6 C

CC

C o m p a l

o m p a lo m p a l

o m p a l P C _ B E

P C _ B EP C _ B E

P C _ B E E P n o s o u n d in D O S m o d e. O T S # 6 0 4 3 1 4

E P n o s o u n d in D O S m o d e. O T S # 6 0 4 3 1 4E P n o s o u n d in D O S m o d e. O T S # 6 0 4 3 1 4

E P n o s o u n d in D O S m o d e. O T S # 6 0 4 3 1 4 in s t a ll Q 7 2 a n d ch a n g e R 1 3 5 2 f r o m 4 .7 K t o 1 0 0 K ,

in s t a ll Q 7 2 a n d c h a n g e R 1 3 5 2 f r o m 4 .7 K t o 1 0 0 K , in s t a ll Q 7 2 a n d c h a n g e R 1 3 5 2 f r o m 4 .7 K t o 1 0 0 K ,

in s t a ll Q 7 2 a n d c h a n g e R 1 3 5 2 f r o m 4 .7 K t o 1 0 0 K ,

c h a n

c h a nc h a n

c h a n g e C 8 9 5 f r o m 0 .1 U t o 0 .0 1 U

g e C 8 9 5 fr o m 0 .1 U t o 0 .0 1 Ug e C 8 9 5 fr o m 0 .1 U t o 0 .0 1 U

g e C 8 9 5 fr o m 0 .1 U t o 0 .0 1 U

0 . 2

0 . 20 . 2

0 . 2

8

88

8

3 0

3 03 0

3 0 D C

D CD C

D C -D C

-D C- D C

-D C

1 /

1 /1 /

1 / 1 1

1 11 1

1 1 C

CC

C o m p a l

o m p a lo m p a l

o m p a l p o w er d o w n s e q u e n c e h a v v p ro b

p o w er d o w n s e q u e n c e h a v v p ro bp o w er d o w n s e q u e n c e h a v v p ro b

p o w er d o w n s e q u e n c e h a v v p ro b lem w ith + 5 V S &

le m w ith + 5 V S &le m w ith + 5 V S &

le m w ith + 5 V S &

+ 3 V S . (+ 5 V S g o es t o lo w a ft e

+ 3 V S . (+ 5 V S g o es t o lo w a ft e+ 3 V S . (+ 5 V S g o es t o lo w a ft e

+ 3 V S . (+ 5 V S g o es t o lo w a ft e r + 3 V S )

r + 3 V S )r + 3 V S )

r + 3 V S )

0 . 2

0 . 20 . 2

0 . 2

c h a n g

c h a n gc h a n g

c h a n g e R 1 3 2 3 fro m 3 3 0 K t o 0 o h m

e R 1 3 2 3 f ro m 3 3 0 K t o 0 o h me R 1 3 2 3 f ro m 3 3 0 K t o 0 o h m

e R 1 3 2 3 f ro m 3 3 0 K t o 0 o h m

9

99

9

1 4

1 41 4

1 4 G L

G LG L

G L A N

A NA N

A N

1 /

1 /1 /

1 / 1 3

1 31 3

1 3 C

CC

C o m p a l

o m p a lo m p a l

o m p a l S y s t e m c a n 't w a k e u p fr o m S 3 & S 5 .

S y st e m c a n 't w a k e u p fr o m S 3 & S 5 .S y st e m c a n 't w a k e u p fr o m S 3 & S 5 .

S y st e m c a n 't w a k e u p fr o m S 3 & S 5 . O T S # 6 0 5 6 4 7

O T S # 6 0 5 6 4 7O T S # 6 0 5 6 4 7

O T S # 6 0 5 6 4 7 r

rr

r e m o v e R 1 4 8 2

e m o v e R 1 4 8 2e m o v e R 1 4 8 2

e m o v e R 1 4 8 2

0 . 2

0 . 20 . 2

0 . 2

T r a

T r aT r a

T r a n s f o r m e r

n s f o r m e rn s f o r m e r

n s f o r m e r

1 0

1 01 0

1 0

1 4

1 41 4

1 4

1 /

1 /1 /

1 / 1 4

1 41 4

1 4 C

CC

C o m p a l

o m p a lo m p a l

o m p a l E M I

E M I E M I

E M I n o is e

n o is en o i se

n o is e S w a p t h e

S w a p t h eS w a p t h e

S w a p t h e s ig n a l o f M I D 0 < -- > 3 , M I D 1 < --> 2 to im p ro v e

sig n a l o f M I D 0 < --> 3 , M I D 1 < - -> 2 t o im p ro v e sig n a l o f M I D 0 < --> 3 , M I D 1 < - -> 2 t o im p ro v e

sig n a l o f M I D 0 < --> 3 , M I D 1 < - -> 2 t o im p ro v e

th e la y o u t r o u tin g . (a v o id t h e t r a c e ro u t in g u n d er

th e la y o u t r o u tin g . (a v o id t h e t r a c e ro u t in g u n d er th e la y o u t r o u tin g . (a v o id t h e t r a c e ro u t in g u n d er

th e la y o u t r o u tin g . (a v o id t h e t r a c e ro u t in g u n d er t h e T )

th e T )th e T )

th e T )

0 . 2

0 . 20 . 2

0 . 2

1 1

1 11 1

1 1

9

99

9 T r a

T r aT r a

T r a n s f o r m e r

n s f o r m e rn s f o r m e r

n s f o r m e r

1 /

1 /1 /

1 / 2 1

2 12 1

2 1 H P

H PH P

H P re s e r v e m e m or y t h er m a l s e n so r b y H

re s e r v e m e m or y t h er m a l s e n so r b y Hre s e r v e m e m or y t h er m a l s e n so r b y H

re s e r v e m e m or y t h er m a l s e n so r b y H P re q u es t

P re qu estP req u e st

P re qu est r

rr

r e se r v e U 59 ,R 1 4 9 6 ,R 1 4 9 7 ,C 1 3 3 8 ,R 1 4 9 5

e se r v e U 59 ,R 1 4 9 6 ,R 1 4 9 7 ,C 1 3 3 8 ,R 1 4 9 5e se r v e U 59 ,R 1 4 9 6 ,R 1 4 9 7 ,C 1 3 3 8 ,R 1 4 9 5

e se r v e U 59 ,R 1 4 9 6 ,R 1 4 9 7 ,C 1 3 3 8 ,R 1 4 9 5

0 . 2

0 . 20 . 2

0 . 2

1 2

1 21 2

1 2

2 4

2 42 4

2 4 A u d

A u dA u d

A u d i o

i oi o

i o

1 /

1 /1 /

1 / 2 8

2 82 8

2 8 H P

H PH P

H P f

f f

f o r t h e m ic d e t e c t io n c o m p a r a t o r

o r th e m ic d e t e c t io n c o m p a r a t o ro r th e m ic d e t e c t io n c o m p a r a t o r

o r th e m ic d e t e c t io n c o m p a r a t o r c h a n

c h a nc h a n

c h a n g e R 1 2 0 2 f ro m 1 2 0 K t o 4 7 K

g e R 1 2 0 2 f r o m 1 2 0 K t o 4 7 Kg e R 1 2 0 2 f r o m 1 2 0 K t o 4 7 K

g e R 1 2 0 2 f r o m 1 2 0 K t o 4 7 K

0 . 2

0 . 20 . 2

0 . 2

1 3

1 31 3

1 3

2 2

2 22 2

2 2 S

SS

S P I

P I P I

P I

2 /

2 /2 /

2 / 2 3

2 32 3

2 3 C

CC

C o m p a l

o m p a lo m p a l

o m p a l F o r S P I R O M R e c o v

F o r S P I R O M R e c o vF o r S P I R O M R e c o v

F o r S P I R O M R e c o v er y

eryer y

ery

0 . 3

0 . 30 . 3

0 . 3

R e s

R e sR e s

R e s er v e R 1 4 9 8 , R 1 4 9 9 , R 1 5 0 0 , R 1 5 0 1 , R 1 5 0 2 , R 1 5 0 3 .

e rv e R 1 4 9 8 , R 1 4 9 9 , R 1 5 0 0 , R 1 5 0 1 , R 1 5 0 2 , R 1 5 0 3 .e rv e R 1 4 9 8 , R 1 4 9 9 , R 1 5 0 0 , R 1 5 0 1 , R 1 5 0 2 , R 1 5 0 3 .

e rv e R 1 4 9 8 , R 1 4 9 9 , R 1 5 0 0 , R 1 5 0 1 , R 1 5 0 2 , R 1 5 0 3 .

1 4

1 41 4

1 4

1 4

1 41 4

1 4

2 /

2 /2 /

2 / 2 4

2 42 4

2 4 C

CC

C o m p a l

o m p a lo m p a l

o m p a l

C

CC

C P U

P UP U

P U

F o r C P

F o r C PF o r C P

F o r C P U T y p e D et e c t

U T y p e D et e c tU T y p e D et e ct

U T y p e D et e c t A d d R 1 5 0 4 w h ic h is p u ll d o w n to G N D a n d c o n n e c t

A d d R 1 5 0 4 w h ic h is p u ll d o w n to G N D a n d c o n n e c t A d d R 1 5 0 4 w h ic h is p u ll d o w n to G N D a n d c o n n e c t

A d d R 1 5 0 4 w h ic h is p u ll d o w n to G N D a n d c o n n e c t to

toto

to

G P I O

G P I OG P I O

G P I O 4 6 .

4 6 .4 6 .

46.

0 . 3

0 . 30 . 3

0 . 3

1 5

1 51 5

1 5 C

CC

C o m p a l

o m p a lo m p a l

o m p a l

0 . 4

0 . 40 . 4

0 . 42 2

2 22 2

2 2 S

SS

S P I

P I P I

P I

3 /

3 /3 /

3 / 1 2

1 21 2

1 2 C h a

C h aC h a

C h a n g e p o w er p in + 3 V L f r o m p in 4 7 t o 5 1 .

n g e p o w e r p in + 3 V L fr o m p in 4 7 t o 5 1 .n g e p o w e r p in + 3 V L fr o m p in 4 7 t o 5 1 .

n g e p o w e r p in + 3 V L fr o m p in 4 7 t o 5 1 .C a n 't p o w er o n w it h I n t el's W L

C a n 't p o w er o n w it h I n t el's W LC a n 't p o w er o n w it h I n t el's W L

C a n 't p o w er o n w it h I n t el's W L A N ca rd .

A N ca rd .A N ca rd .

A N ca rd .

1 6

1 61 6

1 6

1 8

1 81 8

1 8 L C D

L C DL C D

L C D

C

CC

C o m p a l

o m p a lo m p a l

o m p a l3 /

3 /3 /

3 / 2 3

2 32 3

2 3 F

FF

F o r E M I 's re q u e st

o r E M I 's r e q u es to r E M I 's r e q u es t

o r E M I 's r e q u es t a d d 0 .1 u

a d d 0 .1 ua d d 0 .1 u

a d d 0 .1 u F (C 1 3 3 9 ) o n E N A B L T t o G N D n e a r R 1 1 2 2 .

F (C 1 3 3 9 ) o n E N A B L T t o G N D n e a r R 1 1 2 2 . F (C 1 3 3 9 ) o n E N A B L T t o G N D n e a r R 1 1 2 2 .

F (C 1 3 3 9 ) o n E N A B L T t o G N D n e a r R 1 1 2 2 .

0 . 4

0 . 40 . 4

0 . 4

1 7

1 71 7

1 7

1 9

1 91 9

1 9 C

CC

C R T

R TR T

R T

3 /

3 /3 /

3 / 2 4

2 42 4

2 4 C

CC

C o m p a l

o m p a lo m p a l

o m p a l F

FF

F o r E M I 's re q u e st

o r E M I 's r e q u es to r E M I 's r e q u es t

o r E M I 's r e q u es t C h a n g e C 2

C h a n g e C 2C h a n g e C 2

C h a n g e C 2 32 , C 2 3 3 , C 2 3 6 fr o m 6 .8 p F t o 1 8 p F .

3 2 , C 2 3 3 , C 2 3 6 f r o m 6 .8 p F t o 1 8 p F .3 2 , C 2 3 3 , C 2 3 6 f r o m 6 .8 p F t o 1 8 p F .

3 2 , C 2 3 3 , C 2 3 6 f r o m 6 .8 p F t o 1 8 p F .

0 . 4

0 . 40 . 4

0 . 4

0 . 5

0 . 50 . 5

0 . 5

1 8

1 81 8

1 8

1 8

1 81 8

1 8 L C D

L C DL C D

L C D

5 /

5 /5 /

5 / 1 8

1 81 8

1 8 C

CC

C o m p a l

o m p a lo m p a l

o m p a l F in e t u n e L E D p o w er o n s

F in e t u n e L E D p o w er o n sF in e t u n e L E D p o w er o n s

F in e t u n e L E D p o w er o n s eq u en c e.

e qu e n ce .e q u en c e.

e qu e n ce . C h

C hC h

C h a n g e C 6 7 6 t o 0 .2 2 u F a n d C 6 8 2 t o 2 .2 u F .

a n g e C 6 7 6 t o 0 .2 2 u F a n d C 6 8 2 t o 2 .2 u F .a n g e C 6 7 6 t o 0 .2 2 u F a n d C 6 8 2 t o 2 .2 u F .

a n g e C 6 7 6 t o 0 .2 2 u F a n d C 6 8 2 t o 2 .2 u F .

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