Compal LA 6161P Schematics. Www.s Manuals.com. R0.5 Schematics
User Manual: Motherboard Compal LA-6161P Fossil 2.0 UMA - Schematics. Free.
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A B C D E 1 1 Compal Confidential Schematics Document 2 2 INTEL Auburndale BGA with IBEX core logic Fossil 2.0 UMA LA-6161P 3 3 2010-05-18 REV:0.5 4 4 Compal Secret Data Security Classification 2008/09/15 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. Cover Sheet Size Document Number Custom LA-6161P Date: R ev 0.5 Tuesday, May 18, 2010 Sheet E 1 of 41 A B C Compal Confidential D E Fossil 2.0 UMA File Name : LA-6161P DDR3 1066/1333MHz 1.5V Mobile Accelerometer XDP Conn. Page 4 LIS302DLTR DDR3-SO-DIMM X 1 BANK 2, 3 Page 22 Page 9 Single Channel 1 1 Fan Control Arrandale CPU BGA 1288pins Page 4 Page 4,5,6,7,8 LVDS Page 18 FDI DDI_D Display port DMI X4 Page 17 BT(SoftBreeze) Conn USB x 1 page 26 CRT USB conn x 3(For I/O) Page 19 DDI page 24 daughter board 2 2 WWAN +SIM Card USB*1 USB2.0 CardReader Controller Intel Ibex Peak M USB2.0 SD/MMC Slot RealTek RTS5159 Azalia Page 22 1071pins PCI-E BUS sub/B Page 3 25mm*27mm SATA0 USB x1(Camara) Page 18 10/100/1000 LAN RTL8151DH-GR WLAN Card Page 11,12,13,14,15,16 FPR conn x1 PCIE*1 Page 22 Page 21 Page 19 ONFI Interface daughter board Audio CKT RJ45 CONN IDT 92HD80 3 Audio Jack Page 23 sub/B Page 2 3 Page 21 SATA HDD Connector SPI BUS RTC CKT. Page 11 LED SMSC KBC 1098 LED Board Page 20 Power OK CKT. Page 29 4 page 28 Touch Pad CONN. Page 25 Power On/Off CKT. Page 25 Page 19 SPI ROM 4 MB Int.KBD CK505 Page 25 Clock Generator SLG8SP585VTR SPI BUS 4 Page 11 MX25L6445EM2I-10G Page 27 Compal Secret Data Security Classification DC/DC Interface CKT. 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Page 30 A 2008/09/15 Issued Date B C D Title Compal Electronics, Inc. Block Diagram Size Document Number Custom LA-6161P Date: R ev 0.5 Tuesday, May 18, 2010 Sheet E 2 of 41 A Voltage Rails ( O MEANS ON X MEANS OFF ) Symbol Note : +RTCVCC +B +5VALW +1.5V +3VL +3VALW +0.75V +5VS +3VS : means Digital Ground +1.5VS power plane +VCCP +CPU_CORE : means Analog Ground +1.05VS +1.8VS @ : means just reserve , no build ULV@ : means just install for ULV CPU CONN@ : means ME part. State L Layout Notes 07/24 update 1 S0 O O O O O S1 O O O O O S3 O O O O X S5 S4/AC O O O X X S5 S4/ Battery only O O X X X S5 S4/AC & Battery don't exist O X X X X : Question Area Mark.(Wait check) Install below 45 level BOM structure for ver. 0.1 45@ : means just put it in the BOM of 45 level. Install below 43 level BOM structure for ver. 0.1 1 DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMSC1098 SMBCLK SMBDATA Calpella SML0CLK SML0DATA Calpella SML1CLK SML1DATA Calpella BATT XDP V X X X X V X X SODIMM X V X X CLK CHIP X V X X MINI CARD X V X X DOCK NIC THERMAL SENSOR G-SENSOR X V X X X X V X X X X V X V X V Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. Notes List Size Document Number Custom LA-6161P Date: Tuesday, May 18, 2010 R ev 0.5 Sheet 3 of 41 ： 1 2 3 4 5 Layout rule 10mil width trace length < 0.5", spacing 20mil COMP3 AC70 COMP2 49.9_0402_1% 1 R7 2 H_COM P1 AD69 COMP1 2 H_COM P0 AE66 COMP0 49.9_0402_1% 1 R9 TP_SKTOCC# P AD T48 M71 PROC_DETECT A H _CATERR# N61 CATERR# BCLK BCLK# AK7 AK8 C LK_CPU_BCLK CLK_CPU_BCLK# BCLK_ITP BCLK_ITP# K71 J70 CLK_CPU_XDP CLK_CPU_XDP# PEG_CLK PEG_CLK# L21 J21 CLK_EXP CLK_EXP# DPLL_REF_SSCLK DPLL_REF_SSCLK# Y2 W4 CLK_CPU_BCLK <14> CLK_CPU_BCLK# <14> CLK_EXP <12> CLK_EXP# <12> R 46 C LK_DP <12> CLK_DP# <12> 1 1 R 17 <14> H_THERMTRIP# H _CPURST# @ 1 R 18 H_CP UP W RGD N17 <14> H_CP UP W RGD 1 R 22 2 V CC PWRGOOD_0 0_0402_5% <13> PM_DRAM_PWRGD 1 R 26 2 V DDP W RGOOD_R 0_0402_5% THERMTRIP# N70 RESET_OBS# M17 PM_SYNC 2 SYS_AGENT_P WROK AM7 0_0402_5% 1 R21 PROCHOT# Y67 AM5 Power Management H_ CPURST#_R 2 0_0402_5% H_P M_SYNC_R 2 0_0402_5% 1 R 19 <13> H_ PM_SYNC B 2 H_THERMTRIP#_R 0_0402_5% N67 PECI VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK from power <29> VTTPWRGOOD 1 R 32 1 <14> BUF_PLT_RST# 2 H _PWRGD_XDP_R @ 0_0402_5% 2R33 PLT_RST#_R 1.5K_0402_1% H15 VTTPWRGOOD Y70 TAPPWRGOOD G3 RSTIN# 1 H_PWRGD_XDP 2 R35 750_0402_1% DDR3 Misc to power; PU to VCCP at power side also 1 R 15 2 H_ PROCHOT#_D 0_0402_5% <37> H _PROCHOT# N19 SM_DRAMRST# BJ12 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] BV33 BP39 BV40 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXT_TS#[0] PM_EXT_TS#[1] AV66 AV64 PM_EXTTS#0 PM_EXTTS#1 2 R 1092 1 6 1 DRAMRST# <9> Q52A 2N7002DW-7-F_SOT363-6 P CH_ DDR_RST <14> @ 100K_0402_5% C6 1 1 R16 T49 P AD 2 0_0402_5% PRDY# PREQ# U71 U69 XDP_PRDY# XDP _PREQ# TCK TMS TRST# T67 N65 P69 X DP_TCK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M T69 T71 P71 T70 XDP_TDI X DP_TDO X DP_TDI_M DBR# W71 XDP _DBRESET# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] J69 J67 J62 K65 K62 J64 K69 M69 @ R 1493 @ R 1494 PM_EXTTS#1_R <9> 1 1 2 2 2 470P_0402_50V7K from DDR XDP_PREQ#_R X DP_PRDY#_R 0_0402_5% 0_0402_5% reserve for ESD, Compal SI 1/19 CPU XDP Connector XDP_PREQ#_R X DP_PRDY#_R XDP_BPM#0 R23 @ R24 XDP_BPM#1 R25 @ R27 XDP_BPM#2 R28 @ R29 XDP_BPM#3 R30 @ R31 <5> CFG 12 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 <5> CFG 13 <5> CFG 14 <5> CFG 15 +VCCP C1 0.1U_0402_16V4Z 2 @ SV - i5-450M CPU : 2.4G (K0) SV - i3-350M CPU : 2.26G (K0) SV- i3-370M CPU : 2.4G (K0) ULV -U3400 CPU : 1.06G (K0) 2 2 2 2 2 2 2 2 XDP_BPM#4 0_0402_5% XDP_BPM#5 0_0402_5% 1 1 2 R43 XDP_BPM#4_R 2 R48 XDP_BPM#5_R XDP_BPM#6 0_0402_5% XDP_BPM#7 0_0402_5% 1 1 2 R40 XDP_BPM#6_R 2 R41 XDP_BPM#7_R 1 2.53G (K0) 1 1 1 1 1 1 1 1 JP4 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% <5> CF G17 <5> CF G16 ESD request to add INTEL_AUBURNDALE_1288 2nd Source : SV - i5-540M CPU : H_CP UP W RGD 1 R36 2 H_CP UP W RGD_R 1K_0402_5% PM_PWRBTN#_R <13> PM_PWRBTN#_R H_PWRGD_XDP 1 R 37 2 0_0402_5% P AD T112 P AD T113 X DP_TCK Add test points 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 SAMTE_BSH-030-01-L-D-A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CFG8 <5> CFG9 <5> CFG0 <5> CFG1 <5> 2 +VCCP 1K_0402_5% V DDP W RGOOD_R 1 R12 1 R13 2 2 CFG4 <5> CFG5 <5> CLK_CPU_XDP CLK_CPU_XDP# C ONN@ @ XDP_RST#_R 1 2 P LT_RST# R42 0_0402_5% 2 +3VS DDR Pullups 24.9_0402_1% R44 1 H_ PROCHOT#_D 130_0402_1% H_ CPURST#_R 1 R45 1 R47 5 + VCCP 2 49.9_0402_1% PM_EXTTS#0 2 68_0402_5% 2 @ 68_0402_5% PM_EXTTS#1 1 R1 1 R3 2 10K_0402_5% 2 10K_0402_5% FAN_PWM <28> FAN_PWM 1 INB 2 INA O +3VS +VCCP Layout Note:Please these resistors near Processor U50 P 100_0402_1% H _CATERR# C3 1 +VCCP R 891 2 4 0_0402_5% 1 G SM_RCOMP2 2 PLT_RST# <14,21,22,27> +5VS 3 SM_RCOMP1 2 XDP_DBRESET# <13> X DP_TDO XDP_TRST# XDP_TDI XDP_TMS C Processor Pullups 1 R52 1 R56 1 R58 + VCCP @ 1K_0402_5% H _CPURST# 1 2 XDP _DBRESET# 1 2 R 39 0_0402_5% XDP_RST#_R R38 XDP_DB RESET#_R 750_0402_1% DDR3 Compensation Signals SM_RCOMP0 R34 1K_0402_5% CFG6 <5> CFG7 <5> V CCP_1.5VSPWRGD <29> 1.5K_0402_1% +3VS CFG 10 <5> CFG 11 <5> @ PM_PWRBTN#_R 1 R 20 B CFG2 <5> CFG3 <5> PWM Fan Control circuit Intel S3 power reduction circuit for Calpella. 11/09 C A 1 Intel S3 power reduction circuit for Calpella. 11/09 JTAG & MBP 2 H_PECI_ISO 0_0402_5% Thermal 1 R 14 +1.5V R 1093 2 1K_0402_5% SM_DRAMRST# <14> H_ PECI 0_0402_5% @ 2 2 AD71 H_COM P2 1 H_COM P3 2 2 2 1 R5 Misc 1 R2 20_0402_1% Clocks U1B 20_0402_1% TC7SH00FUF_SSOP5 for RF 2 2 B D 3 C E H _PROCHOT# 51_0402_5% D 1 Q26 2 2 47P_0402_50V8J R 896 10K_0402_5% 0112 Remove uninstall parts 1 R 59 4 5 ACES_85204-03001 C ONN@ 1 C 1316 @ XDP_TRST# 2 @ 0.1U_0402_10V6K J FA N1 1 1 2 2 G1 3 3 G2 1 PMBT3904_SOT23 Close to XDP X DP_TDO 1 2 Compal Secret Data Security Classification + VCCP Issued Date 1 2 R10 51_0402_5% This shall place near XDP 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 4 Title Compal Electronics, Inc. Auburndale(1/5)-Thermal/XDP Size D ocument Number Cus tom LA -6161P Dat e: Rev 0.5 Sheet Tuesday, May 18, 2010 5 4 of 41 2 U 1A F7 J8 K8 J4 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] <13> <13> <13> <13> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 F9 J6 K9 J2 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] <13> <13> <13> <13> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 H17 K15 J13 F10 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] <13> <13> <13> <13> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G17 M15 G13 J11 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_N0 L2 FDI_CTX_PRX_N1 N7 FDI_CTX_PRX_N2 M4 FDI_CTX_PRX_N3 P1 FDI_CTX_PRX_N4 N10 FDI_CTX_PRX_N5 R7 FDI_CTX_PRX_N6 U7 FDI_CTX_PRX_N7 W8 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] <13> <13> <13> <13> <13> B <13> <13> <13> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_P0 K1 FDI_CTX_PRX_P1 N5 FDI_CTX_PRX_P2 N2 FDI_CTX_PRX_P3 R2 FDI_CTX_PRX_P4 N9 FDI_CTX_PRX_P5 R8 FDI_CTX_PRX_P6 U6 FDI_CTX_PRX_P7 W10 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] <13> FDI_FS Y NC0 <13> FDI_FS Y NC1 FDI_FS Y N C0 FDI_FS Y N C1 AC7 AC9 FDI_FSYNC[0] FDI_FSYNC[1] <13> FDI_ INT FDI _INT AB5 FDI_INT <13> FDI_LS Y NC0 <13> FDI_LS Y NC1 FDI_LS Y NC0 FDI_LS Y NC1 AA1 AB2 FDI_LSYNC[0] FDI_LSYNC[1] Intel(R) FDI <13> <13> <13> <13> <13> <13> <13> <13> PCI EXPRESS -- GRAPHICS DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI A <13> <13> <13> <13> PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B12 A13 D12 B11 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L20 E XP_ICOMPI E XP_RBIAS 3 4 5 49.9_0402_1% 1 R64 2 1 R65 2 750_0402_1% U1E <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> <4> CFG0 AL4 CFG1 AM2 CFG2 AK1 CFG3 AK2 CFG4 AK4 CFG5 AJ2 CFG6 AT2 CFG7 AG7 CFG8 AF4 CFG9 AG2 CF G10 AH1 CF G11 AC2 CF G12 AC4 CF G13 AE2 CF G14 AD1 CF G15 AF8 CF G16 AF6 CF G17 AB7 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CF G10 CF G11 CF G12 CF G13 CF G14 CF G15 CF G16 CF G17 P AD T50 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] AU1 RSVD_TP[0] T4 T2 RSVD15 RSVD16 U1 V2 RSVD17 RSVD18 AV71 AW70 RSVD19 RSVD20 AY69 BB69 RSVD21 RSVD22 D8 B7 RSVD23 RSVD24 A10 B9 RSVD26 RSVD27 C5 A6 RSVD_NCTF[7] RSVD_NCTF[8] E3 F1 RSVD_NCTF[6] RSVD_NCTF[5] C INTEL_AUBURNDALE_1288 RSVD32 RSVD33 W66 W64 T116 P AD T117 P AD RSVD34 RSVD35 AC69 AC71 T118 P AD RSVD36 RSVD37 AA71 AA69 RSVD38 RSVD39 R66 R64 RSVD_NCTF[3] RSVD_NCTF[4] BT5 BR5 RSVD_NCTF[2] RSVD_NCTF[1] BV6 BV8 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 RESERVED 1 A T119 P AD T120 P AD AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67 RSVD_TP[2] RSVD_TP[1] AP2 AN7 RSVD62 RSVD63 AV4 AU2 RSVD64 RSVD65 BE69 BE71 DC_TEST_BV71 DC_TEST_BV69 DC_TEST_BV68 DC_TEST_BV5 DC_TEST_BV3 DC_TEST_BV1 DC_TEST_BT71 DC_TEST_BT69 DC_TEST_BT3 DC_TEST_BT1 DC_TEST_BR71 DC_TEST_BR1 DC_TEST_E71 DC_TEST_E1 DC_TEST_C71 DC_TEST_C69 DC_TEST_C3 DC_TEST_A71 DC_TEST_A69 DC_TEST_A68 DC_TEST_A5 BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1 E71 E1 C71 C69 C3 A71 A69 A68 A5 B T51 P AD T52 P AD VSS_NCTF2_R <8> VSS_NCTF6_R <8> VSS_NCTF1_R <8> VSS_NCTF7_R <8> C INTEL_AUBURNDALE_1288 CFG Straps for PROCESSOR CFG0 R68 1 2 @ 3.01K_0402_1% PCI-Express Configuration Select 1: Single PEG CFG0 0: Bifurcation enabled Not applicable for Clarksfield Processor CFG3 R69 1 CFG3-PCI Express 1: CFG3 0: 15 CFG4 D R70 1 2 @ 3.01K_0402_1% Static Lane Reversal Normal Operation Lane Numbers Reversed -> 0, 14 ->1, ..... 2 3.01K_0402_1% D ES1 sample need negative voltage ES2 sample contact to GND CFG4-Display Port Presence 1: Disabled; No Physical Display Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. Auburndale(2/5)-DMI/PEG/FDI Size D ocument Number Cus tom LA -6161P Dat e: Rev 0.5 Sheet Tuesday, May 18, 2010 5 5 of 41 1 2 3 4 5 U1D U1C <9> DDR_A _D[0..63] AT8 AT6 BB5 BB9 AV7 AV6 BE6 BE8 BF11 BE11 BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 BK15 BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66 BJ66 BF65 AY64 BC70 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] <9> D DR_A_BS0 <9> D DR_A_BS1 <9> D DR_A_BS2 BT38 BH38 BF21 SA_BS[0] SA_BS[1] SA_BS[2] <9> DD R_A_CAS# <9> DD R_A_RAS# <9> DDR _A_WE# BK43 BL38 BF38 B C BM34 BP35 BF20 SA_CK[1] SA_CK#[1] SA_CKE[1] BK36 BH36 BK24 M _CLK_DDR1 <9> M _CLK_DDR#1 <9> DDR_CKE1_DIMMA <9> SA_CS#[0] SA_CS#[1] BH40 BJ47 DDR_CS0_DIMMA# <9> DDR_CS1_DIMMA# <9> SA_ODT[0] SA_ODT[1] BF43 BL47 M_ODT0 <9> M_ODT1 <9> SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A DDR_A _D0 DDR_A _D1 DDR_A _D2 DDR_A _D3 DDR_A _D4 DDR_A _D5 DDR_A _D6 DDR_A _D7 DDR_A _D8 DDR_A _D9 DDR_ A_D10 DDR_ A_D11 DDR_ A_D12 DDR_ A_D13 DDR_ A_D14 DDR_ A_D15 DDR_ A_D16 DDR_ A_D17 DDR_ A_D18 DDR_ A_D19 DDR_ A_D20 DDR_ A_D21 DDR_ A_D22 DDR_ A_D23 DDR_ A_D24 DDR_ A_D25 DDR_ A_D26 DDR_ A_D27 DDR_ A_D28 DDR_ A_D29 DDR_ A_D30 DDR_ A_D31 DDR_ A_D32 DDR_ A_D33 DDR_ A_D34 DDR_ A_D35 DDR_ A_D36 DDR_ A_D37 DDR_ A_D38 DDR_ A_D39 DDR_ A_D40 DDR_ A_D41 DDR_ A_D42 DDR_ A_D43 DDR_ A_D44 DDR_ A_D45 DDR_ A_D46 DDR_ A_D47 DDR_ A_D48 DDR_ A_D49 DDR_ A_D50 DDR_ A_D51 DDR_ A_D52 DDR_ A_D53 DDR_ A_D54 DDR_ A_D55 DDR_ A_D56 DDR_ A_D57 DDR_ A_D58 DDR_ A_D59 DDR_ A_D60 DDR_ A_D61 DDR_ A_D62 DDR_ A_D63 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_CAS# SA_RAS# SA_WE# M _CLK_DDR0 <9> M _CLK_DDR#0 <9> DDR_CKE0_DIMMA <9> DD R_A_DM0 DD R_A_DM1 DD R_A_DM2 DD R_A_DM3 DD R_A_DM4 DD R_A_DM5 DD R_A_DM6 DD R_A_DM7 BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] AY5 BJ7 BN13 BL21 BH44 BK51 BP58 BE62 DD R_A_DQS#0 DD R_A_DQS#1 DD R_A_DQS#2 DD R_A_DQS#3 DD R_A_DQS#4 DD R_A_DQS#5 DD R_A_DQS#6 DD R_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] AY7 BJ5 BL13 BN21 BK44 BH51 BM60 BE64 DDR _A_DQS0 DDR _A_DQS1 DDR _A_DQS2 DDR _A_DQS3 DDR _A_DQS4 DDR _A_DQS5 DDR _A_DQS6 DDR _A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] BT36 BP33 BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28 BH34 BH30 BJ28 BF40 BN28 BN25 DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_MA 10 DDR_A_MA 11 DDR_A_MA 12 DDR_A_MA 13 DDR_A_MA 14 DDR_A_MA 15 DDR _A_DM[0..7] <9> DDR _A_DQS#[0..7] <9> DDR_ A_DQS[0..7] <9> DDR_A_MA[0..15] <9> BA2 AW2 BD1 BE4 AY1 BC2 BF2 BH2 BG4 BG1 BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60 BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BK70 BK67 BD71 BD69 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] BV43 BV41 BV24 SB_BS[0] SB_BS[1] SB_BS[2] BU46 BT40 BT41 SB_CAS# SB_RAS# SB_WE# SB_CK[0] SB_CK#[0] SB_CKE[0] BU33 BV34 BT26 SB_CK[1] SB_CK#[1] SB_CKE[1] BV38 BU39 BT24 SB_CS#[0] SB_CS#[1] BP46 BT43 SB_ODT[0] SB_ODT[1] BV45 BU49 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] BE2 BM3 BU12 BT19 BT52 BV55 BU63 BG69 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] BD4 BN4 BV13 BT17 BT50 BU56 BV62 BJ69 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] BT34 BP30 BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27 BU42 BU26 BT29 BT45 BV26 BU23 A B DDR SYSTEM MEMORY - B A C INTEL_AUBURNDALE_1288 INTEL_AUBURNDALE_1288 D D Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. Auburndale(3/5)-DDR3 Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 5 6 of 41 1 2 3 4 5 +GFX_CORE + VCCP 2 +CP U_CORE for RF +GFX_CORE 2 1 2 1U_0402_6.3V6K C6 12 2 1 1U_0402_6.3V6K C6 14 2 1 1U_0402_6.3V6K C6 13 2 1 1U_0402_6.3V6K C3 83 2 1 1U_0402_6.3V6K C5 34 2 1 1U_0402_6.3V6K C5 33 2 1 1U_0402_6.3V6K C3 82 @ POWER <37> PSI# <37> H_V I D[0..6] H_V ID0 H_V ID1 H_V ID2 H_V ID3 H_V ID4 H_V ID5 H_V ID6 T135 P AD H_VTTVID1 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AN1 VTT_SELECT[1] A41 <37> IMVP_IMON <37> VCCSENSE <37> VSSSENSE PROC_DPRSLPVR ISENSE 0_0402_5% VCCSENSE 2 R73 F64 1 VSS SENSE 2 1 F63 R74 0_0402_5% VCC_SENSE VSS_SENSE N13 VTT_SENSE R12 VSS_SENSE_VTT <34> VTT_SENSE 2 R 1481 PSI# A61 D61 D62 A62 B63 D64 D66 2 R72 1PM_DPRSLP VR_R F66 0_0402_5% <37> P ROC_DPRSLPVR CPU CORE SUPPLY F68 VSS_SENSE_VTT 1 0_0402_5% VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59 VTT0_60 VTT0_61 VTT0_62 VTT0_63 VTT0_64 VTT0_65 VTT0_66 VTT0_67 VTT0_68 VTT0_69 VTT0_70 VTT0_71 VTT0_72 VTT0_73 +VCAP1 BD44 BD41 BD37 BB44 BB41 BB37 AY46 AY42 AY39 AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46 AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39 VCAP1_1 VCAP1_2 VCAP1_3 VCAP1_4 VCAP1_5 VCAP1_6 VCAP1_7 VCAP1_8 VCAP1_9 VCAP1_10 VCAP1_11 VCAP1_12 VCAP1_13 VCAP1_14 VCAP1_15 VCAP1_16 VCAP1_17 VCAP1_18 VCAP1_19 VCAP1_20 VCAP1_21 VCAP1_22 VCAP1_23 VCAP1_24 VCAP1_25 VCAP1_26 VCAP1_27 +C PU_CORE Close to CPU VCCSENSE 1 R75 1 R76 VSS SENSE 2 100_0402_1% 2 100_0402_1% 22U_0805_6.3V6M +1.8VS 1 4.7U_0603_6.3V6K W39 W37 U37 R39 R37 1 C37 C38 2 VCCPLL1 VCCPLL2 VCCPLL3 VCCPLL4 VCCPLL5 2 +1.5VS_CPU_VDDQ L32 2 1 0_0805_5% + VDDQ_CK C 50 1U_0402_6.3V6K BB14 BB12 VDDQ_CK[1] VDDQ_CK[2] 1 AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60 AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59 AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33 AF32 AF30 AD39 BF60 BF59 BD60 BD59 BB60 BB59 AY60 AW60 AW35 AW33 AD37 AD35 AD33 AD32 AD30 W35 W33 W32 W30 W28 W26 W24 W23 U35 U33 U32 U30 U28 U26 U24 U23 R35 R33 R32 R30 R28 R26 R24 R23 AY10 VTT0_72 AN9 VTT0_73 A B C 2 INTEL_AUBURNDALE_1288 VTT0_72 VTT0_73 R77 R78 2 0_0402_5% 2 0_0402_5% 1 1 +VCCP INTEL_AUBURNDALE_1288 1U_0402_6.3V6K C3 81 2 C58 @ 1 47P_0402_50V8J 2 C57 @ 1 47P_0402_50V8J 2 C56 2 @ 1 47P_0402_50V8J 2 @ 1 47P_0402_50V8J C55 2 @ 1 12P_0402_50V8J @ 1 C 1322 12P_0402_50V8J 2 1 C 1321 12P_0402_50V8J C 1319 @ C 1320 12P_0402_50V8J 1 +C PU_CORE + VCCP U 1F 1.1V RAIL POWER - 1.5V RAILS DDR3 for RF 10U_0805_6.3V6M C49 INTEL_AUBURNDALE_1288 10U_0805_6.3V6M C48 2 VTT1_12 VTT1_13 VTT1_14 VTT1_15 VTT1_16 VTT1_17 VTT1_18 VTT1_19 VTT1_20 VTT1_21 10U_0805_6.3V6M C47 2 2 1 10U_0805_6.3V6M C46 1 @ 12P_0402_50V8J 2 C 1326 12P_0402_50V8J C 1325 1 @ 2 1 C62 10U_0805_6.3V6M 2 1 C61 10U_0805_6.3V6M 1 C60 10U_0805_6.3V6M for RF +GFX_CORE C59 10U_0805_6.3V6M C VTT0_DDR VTT0_DDR[1] VTT0_DDR[2] VTT0_DDR[3] VTT0_DDR[4] VTT0_DDR[5] VTT0_DDR[6] VTT0_DDR[7] VTT0_DDR[8] VTT0_DDR[9] 1U_0402_6.3V6K C 44 2 +VCAP0 BD55 BD51 BD48 BB55 BB51 BB48 AY57 AY53 AY50 AW57 AW53 AW50 AU55 AU51 AU48 AR55 AR51 AR48 AN57 AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50 VCAP0_1 VCAP0_2 VCAP0_3 VCAP0_4 VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9 VCAP0_10 VCAP0_11 VCAP0_12 VCAP0_13 VCAP0_14 VCAP0_15 VCAP0_16 VCAP0_17 VCAP0_18 VCAP0_19 VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27 POWER 1 1U_0402_6.3V6K C 43 2 U1H VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 SENSE LINES 1 VCAP2_1 VCAP2_2 VCAP2_3 VCAP2_4 VCAP2_5 VCAP2_6 VCAP2_7 VCAP2_8 VCAP2_9 VCAP2_10 VCAP2_11 VCAP2_12 VCAP2_13 VCAP2_14 VCAP2_15 VCAP2_16 VCAP2_17 VCAP2_18 VCAP2_19 1U_0402_6.3V6K C 42 2 R 1484 1.8V 1 1U_0402_6.3V6K C36 2 1U_0402_6.3V6K C35 1 1U_0402_6.3V6K C34 2 1U_0402_6.3V6K C33 1U_0402_6.3V6K C32 1 AK62 AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59 AB60 AB59 AA60 AA59 W60 W59 U60 U59 R60 R59 C24 1U_0402_6.3V6K +VCAP2 C23 1U_0402_6.3V6K VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36 1 SENSE LINES GRAPHICS VIDs GFX_VR_EN GFX_DPRSLPVR GFX_IMON C27 22U_0805_6.3V6M 2 VTT1_1 VTT1_2 VTT1_3 VTT1_4 VTT1_5 VTT1_6 VTT1_7 VTT1_8 VTT1_9 VTT1_10 VTT1_11 PEG & DMI 2 1 C31 10U_0805_6.3V6M 2 1 C30 10U_0805_6.3V6M 1 C29 10U_0805_6.3V6M 2 C28 10U_0805_6.3V6M 1 W21 W19 U21 U19 U17 U15 U14 U12 R21 R19 R17 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] C22 1U_0402_6.3V6K + VCCP VAXG_SENSE VSSAXG_SENSE C26 22U_0805_6.3V6M B VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 C21 1U_0402_6.3V6K 2 @ AF57 AF55 VCC_A XG_SENSE AF12 AF53 VCC_AXG_SENSE <39> VSS_AXG_SENSE AF10 AF51 VSS_AXG_SENSE <39> AF50 AF48 AF46 AF44 AF71 AF42 GFXVR_VID_0 <39> AG67 AF41 GFXVR_VID_1 <39> AG70 AD55 GFXVR_VID_2 <39> AH71 AD51 GFXVR_VID_3 <39> AN71 AD48 GFXVR_VID_4 <39> AM67 AD44 GFXVR_VID_5 <39> AM70 AD41 GFXVR_VID_6 <39> @ R7 05 1 2 4.7K_0402_5% AB55 + VCCP AB51 GFXVR_EN <39> AH69 AB48 GFX_DPRSLPVR AL71 AB44 12/05 HP AL69 AB41 2 1 AA55 GFXVR_IMON <39> R 1478 0_0402_5% AA51 +1.5VS_CPU_VDDQ BU40 AA48 BU35 AA44 BU28 AA41 BN38 W55 1 1 1 1 1 BM25 W51 BL30 W48 BJ38 W44 2 2 2 2 2 BH32 W41 BH28 U55 BG43 U51 BF16 U48 BF15 U44 BD35 U41 1 BD33 R55 1 1 + BD32 R51 BD30 R48 @ BD28 R44 2 2 2 BD26 R41 BD24 P60 BD23 N55 BD21 N51 BD19 N48 BD17 N44 BD15 N42 BB35 M60 BB33 M51 BB32 M44 BB30 L55 + VCCP BB28 K60 BB26 K51 BB24 K44 BB23 J55 BB21 H60 L31 BB19 H51 BB17 H44 0_0805_5% BB15 G60 G55 G51 +VTT_DDR AW32 G44 AW30 F55 AW28 E60 AW26 E57 1 1 1 AW24 E53 AW23 E50 AW21 E46 2 2 2 AW19 E42 AW17 D59 AW15 D57 D55 + VCCP AD15 D54 AD14 D52 AD12 D50 AB12 D48 AA12 D47 W17 D45 1 1 1 1 W15 D43 W14 B60 W12 B56 2 2 2 2 R15 B53 B49 B46 B42 A57 A54 A50 A47 A43 C25 330U_B2_2.5VM_R15M 2 1 AN32 AN30 AN28 AN26 AN24 AN23 AN21 AN19 AL32 AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10 AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15 AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17 C20 1U_0402_6.3V6K 2 1 + VCCP 2 4.7K_0402_5% +CP U_CORE C2 21 1U_0402_6.3V6K 1 2 C3 80 1U_0402_6.3V6K 2 C2 19 1U_0402_6.3V6K C2 20 1U_0402_6.3V6K 1 2 1 2 4.7K_0402_5% 1 U 1G GRAPHICS 2 1 1 @ R 1483 GFX_DPRSLPVR 2 GFXVR_EN 4.7K_0402_5% 1 R7 00 C2 17 1U_0402_6.3V6K 1 2 C2 18 1U_0402_6.3V6K 2 C2 15 1U_0402_6.3V6K C2 16 1U_0402_6.3V6K 1 2 1 2 Follow SCH check list CPU VIDS 2 1 1 C2 13 1U_0402_6.3V6KZ 2 1 2 C2 14 1U_0402_6.3V6K 1 C1 79 1U_0402_6.3V6K C2 12 1U_0402_6.3V6K A 2 1 POWER 2 1 C19 22U_0805_6.3V6M 2 1 C18 22U_0805_6.3V6M + C17 1U_0402_6.3V6K C16 1U_0402_6.3V6K 2 C 1313 1 C 1312 + 330U_D2_2.5VM_R6M 330U_D2_2.5VM_R6M 1 1 +VCAP0 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1 1 C68 1U_0402_6.3V6K D 2 +VCAP1 add 7pcs Caps to follow Design guide 1 C69 2 1 C70 2 1 C 71 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1 C72 2 1 C93 2 1 C1 14 2 1 C1 13 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1 C 94 2 1 C92 2 1 C 140 2 2 1 C1 15 C63 1U_0402_6.3V6K add 7pcs Caps to follow Design guide 1U_0402_6.3V6K 1 C64 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 1 C65 2 1 C 66 2 1 C67 2 1 C86 2 1 C89 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1 C88 2 1 C 87 2 1 C85 2 1 C91 2 C90 2 D + VCCP +CP U_CORE 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1U_0402_6.3V6K C6 51 1 1U_0402_6.3V6K C6 53 2 1U_0402_6.3V6K C6 52 1 1U_0402_6.3V6K C6 48 2 1U_0402_6.3V6K C6 50 1 1U_0402_6.3V6K C6 49 2 1U_0402_6.3V6K C6 47 1 1U_0402_6.3V6K C6 44 2 1U_0402_6.3V6K C6 46 1 1 1U_0402_6.3V6K C6 45 2 1U_0402_6.3V6K C6 17 1 1U_0402_6.3V6K C6 43 @ 1U_0402_6.3V6K C6 23 2 1U_0402_6.3V6K C6 16 1 1U_0402_6.3V6K C6 15 @ C 54 2 47P_0402_50V8J 1 C 53 @ 47P_0402_50V8J C 52 2 47P_0402_50V8J C 51 1 47P_0402_50V8J @ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 Compal Secret Data Security Classification Issued Date 2 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 4 Title Compal Electronics, Inc. Auburndale(4/5)-PWR Size D ocument Number Cus tom LA -6161P Dat e: Rev 0.5 Sheet Tuesday, May 18, 2010 5 7 of 41 2 3 4 Add to follow design guide + VCCP CPU CORE U 1I 1 1 1 1U_0402_6.3V6K 1 1 C 304 2 C3 03 1 C3 02 2 1 C1 92 2 C 305 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1 C 509 2 1 C5 08 2 1 C3 07 2 2 + 2 2 1 2 A 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 B C6 28 Under cavity 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K BGA Ball Cracking Prevention and Detection C +3VS 1 1 +3VS R79 100K_0402_5% 2 3 2 CRACK_BGA <16,28> 6 R80 CRACK_BGA 100K_0402_5% Q3A 2N7002DW-T/R7_SOT363-6 Q3B 2 5 4 1 2N7002DW-T/R7_SOT363-6 <5> VSS_NCTF1_R <5> VSS_NCTF2_R 1 +3VS CRACK_BGA R81 100K_0402_5% 3 R82 CRACK_BGA 100K_0402_5% 6 1 +3VS 2 Q4A 2N7002DW-T/R7_SOT363-6 Q4B 2N7002DW-T/R7_SOT363-6 5 <5> VSS_NCTF6_R <5> VSS_NCTF7_R Compal Secret Data Security Classification 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 D 4 1 2 INTEL_AUBURNDALE_1288 2 2 1 C1 10 22U_0805_6.3V6M 2 C1 09 22U_0805_6.3V6M 1 C1 08 22U_0805_6.3V6M 1 C6 36 2 2 C1 07 22U_0805_6.3V6M C5 13 Issued Date 1 2 1 Under cavity C1 06 U LV@ 22U_0805_6.3V6M 1 2 2 1 C1 05 22U_0805_6.3V6M C 515 2 + C1 04 22U_0805_6.3V6M C 618 2 1 2 1 C 511 1U_0402_6.3V6K 1U_0402_6.3V6K 1 + C1 03 22U_0805_6.3V6M C6 19 2 2 1 2 1 1U_0402_6.3V6K 1 2 1 1 C5 12 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 1 C 98 330U_D2_2.5VM_R6M 1U_0402_6.3V6K 1 C 97 330U_D2_2.5VM_R6M 1 2 C 510 2 1 2 + 1 2 1 Inside cavity 1 C 306 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 1 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 2 1 C84 U LV@ 22U_0805_6.3V6M 2 1 C83 U LV@ 22U_0805_6.3V6M 1 1U_0402_6.3V6K 1U_0402_6.3V6K C82 U LV@ 22U_0805_6.3V6M C 201 2 C81 22U_0805_6.3V6M 2 C80 22U_0805_6.3V6M 2 1 C 190 C79 22U_0805_6.3V6M 2 1 C1 41 C78 22U_0805_6.3V6M 2 1 C1 91 C77 22U_0805_6.3V6M C1 42 C76 22U_0805_6.3V6M C 189 1U_0402_6.3V6K 2 C75 22U_0805_6.3V6M A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 AA17 AA15 AA14 AA4 W69 W62 W57 W53 W50 W46 W42 W6 W1 V70 U64 U62 U57 U53 U50 U46 U42 U39 U9 U4 T1 R70 R62 R57 R53 R50 R46 R42 R5 P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36 M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11 K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 C1 02 U LV@ 22U_0805_6.3V6M VSS VSS404 VSS405 VSS406 VSS407 VSS408 VSS409 VSS410 VSS411 VSS412 VSS413 VSS393 VSS394 VSS395 VSS396 VSS397 VSS398 VSS399 VSS400 VSS401 VSS402 VSS403 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360 VSS361 VSS362 VSS363 VSS364 VSS365 VSS366 VSS367 VSS368 VSS369 VSS370 VSS371 VSS372 VSS373 +CP U_CORE C 96 U LV@ 330U_D2_2.5VM_R6M INTEL_AUBURNDALE_1288 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS374 VSS375 VSS376 VSS377 VSS378 VSS379 VSS380 VSS381 VSS382 VSS383 VSS384 VSS385 VSS386 VSS387 VSS388 VSS389 VSS390 VSS391 VSS392 VSS415 1U_0402_6.3V6K C74 U LV@ 22U_0805_6.3V6M D AH53 AH51 AH50 AH48 AH46 AH44 AH42 AH41 AH39 AH37 AH35 AH33 AH32 AH30 AH28 AH26 AH24 AH23 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30 AA28 AA26 AA24 AA23 AA21 AA19 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B40 1U_0402_6.3V6K 1U_0402_6.3V6K C1 01 22U_0805_6.3V6M C VSS U1J C 95 330U_D2_2.5VM_R6M B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4 AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9 AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35 AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17 AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46 AN51 AN48 AN44 AN41 AN37 AN5 AN4 AM64 AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33 AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 BV66 BV64 BT68 BR69 BR68 BR3 BN71 BN1 BL71 BL1 R14 H71 F71 E69 E68 A66 A64 E5 C68 C73 22U_0805_6.3V6M A BU62 BU58 BU55 BU51 BU48 BU44 BU37 BU32 BU25 BU21 BU18 BU14 BU11 BU7 BP42 BN64 BN6 BM70 BM51 BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20 BK63 BK60 BK53 BK34 BK10 BJ64 BJ21 BJ9 BJ1 BH70 BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30 BF13 BF8 BE70 BE65 BE9 BE1 BD57 BD53 BD50 BD46 BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42 BB39 BB7 BB1 BA70 AY71 AY66 AY62 AY59 AY55 AY51 AY48 AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23 AR21 AR19 AR17 AR15 AR14 AR4 AR1 AP70 AP64 AN62 AN55 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 5 2 1 4 Title Compal Electronics, Inc. Auburndale(5/5)-GND/Bypass Size D ocument Number Cus tom LA -6161P Dat e: Rev 0.5 Sheet Tuesday, May 18, 2010 5 8 of 41 1 2 3 4 5 DDR3 SO-DIMM A +1.5V +1.5V 3A@ 1.5V +V _D DR_CPU_REF JDIMM1 DDR_ A_D24 DDR_ A_D31 DD R_A_DM3 DDR_ A_D26 DDR_ A_D27 <6> DDR_CKE0_DIMMA DDR_CKE0_DIM MA <6> D DR_A_BS2 D DR_A_BS2 B DDR_A_MA 12 DDR_A_M A9 DDR_A_M A8 DDR_A_M A5 DDR_A_M A3 DDR_A_M A1 <6> M _ CLK_DDR0 <6> M _CLK_DDR#0 M _CLK_DDR0 M _CLK_DDR#0 <6> D DR_A_BS0 DDR_A_MA 10 D DR_A_BS0 <6> DDR_ A_WE# <6> DDR _A_CAS# DDR _A_WE# DD R_A_CAS# <6> DDR_CS1_DIMMA# DDR_A_MA 13 DDR_CS1_DIMM A# DDR_ A_D56 DDR_ A_D61 DD R_A_DM7 R 83 1K_0402_1% DDR_A_BS1 <6> DD R_A_RAS# <6> DDR_CS0_DIMM A# M _ODT0 M _ODT1 +V _D DR_CPU_REF DDR_CS0_DIMMA# <6> M_ODT0 <6> +VREF_CA M_ODT1 <6> R94 DDR_ A_D36 DDR_ A_D38 DD R_A_DM4 1 DDR_ A_D37 DDR_ A_D39 2 DDR_ A_D41 DDR_ A_D40 1 2 Layout Note: Place near JDIMM1 +V _D DR_CPU_REF R 86 1K_0402_1% 1 2 0_0402_5% +1.5V 1 +3VS 2 DD R_A_DQS#5 DDR _A_DQS5 @ DDR_ A_D46 DDR_ A_D47 DDR_ A_D55 DDR_ A_D53 @ R 1495 10K_0402_5% @ 1 2 U59 DD R_A_DM6 DDR_ A_D52 DDR_ A_D48 S MB_DATA_S3 1 SDA +VS 8 SMB _CLK_S3 2 SCL A0 7 3 T_CRIT_A A1 6 4 GND INT 5 DDR_ A_D60 DDR_ A_D57 DD R_A_DQS#7 DDR _A_DQS7 2 @ R 1496 open 0_0402_5% 2 1 2 1 + 2 C Layout Note: Place near JDIMB1 +0.75VS @ R 1497 0_0402_5% 2 1 2 1 2 1 2 1 2 1 2 10U_0805_6.3V6M 2 reserve for memory thermal sensor, HP. +0.75VS 1 C1 35 1 PM_EXTTS#1_R <4> SMB_DATA_S3 <10,12,22> SMB_CLK_S3 <10,12,22> 2 1 1U_0402_6.3V6K NS_LM77CIMMX_3_MSOP8P PM_EXTTS#1_R S MB_DATA_S3 SMB _CLK_S3 1 +3VS PM_EXTTS#1_R D 0. 65A@0.75V FOX_AS0A626-U4SN-7F~D C ONN@ Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 1 1U_0402_6.3V6K DDR_ A_D59 DDR_ A_D63 1 C1 34 206 208 M _CLK_DDR1 <6> M_CLK_DDR#1 <6> D DR_A_BS1 DD R_A_RAS# C1 33 BOSS1 BOSS2 M _CLK_DDR1 M _CLK_DDR#1 1U_0402_6.3V6K GND1 GND2 +1.5V DDR_A_M A2 DDR_A_M A0 C1 32 205 207 DDR_A_MA6 DDR_A_M A4 1U_0402_6.3V6K 2 1 R96 2 10K_0402_5% DDR_A_MA11 DDR_A_M A7 C1 31 C 1315 10U_0603_6.3V6M 2 1 C 137 0.1U_0402_16V4Z 1 C 136 2.2U_0402_6.3V6M +3VS D B C 1314 10U_0603_6.3V6M DDR_ A_D62 DDR_ A_D58 1 R 95 2 10K_0402_5% DDR_CKE1_DIMMA <6> DDR_A_MA 15 DDR_A_MA 14 C 118 330U_B2_2.5VM_R15M DDR_ A_D54 DDR_ A_D51 DDR_CKE1_DIM MA C 126 10U_0603_6.3V6M DD R_A_DQS#6 DDR _A_DQS6 DDR_ A_D29 DDR_ A_D30 C 125 10U_0603_6.3V6M DDR_ A_D50 DDR_ A_D49 DD R_A_DQS#3 DDR _A_DQS3 C 1338 0.1U_0402_16V4Z DDR_ A_D42 DDR_ A_D43 <6> DDR_A_MA[0..15] C 124 10U_0603_6.3V6M DD R_A_DM5 <6> DDR_ A_DQS#[0..7] DDR_ A_D25 DDR_ A_D28 C 123 10U_0603_6.3V6M DDR_ A_D44 DDR_ A_D45 <6> DDR_ A_DQS[0..7] DDR_ A_D22 DDR_ A_D18 C 122 10U_0603_6.3V6M DDR_ A_D34 DDR_ A_D35 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 <6> DDR_A _D[0..63] <6> DDR _A_DM[0..7] DD R_A_DM2 C 121 10U_0603_6.3V6M C CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT DDR_ A_D19 DDR_ A_D21 C 117 2.2U_0805_16V4Z DD R_A_DQS#4 DDR _A_DQS4 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DRAMRST# <4> DDR_ A_D14 DDR_ A_D15 C 116 0.1U_0402_16V4Z DDR_ A_D32 DDR_ A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DD R_A_DM1 DRAMRST# 2 DDR_ A_D16 DDR_ A_D23 A DDR_ A_D12 DDR_ A_D13 1 DD R_A_DQS#2 DDR _A_DQS2 DDR_A _D4 DDR_A _D3 2 DDR_ A_D17 DDR_ A_D20 DD R_A_DQS#0 DDR _A_DQS0 1 DDR_A _D8 DDR_ A_D10 DDR_A _D0 DDR_A _D1 1 DD R_A_DQS#1 DDR _A_DQS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 DDR_A _D9 DDR_ A_D11 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 1 DDR_A _D6 DDR_A _D7 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 2 DD R_A_DM0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 DDR_A _D2 DDR_A _D5 1 A 1 C 112 2.2U_0805_16V4Z 2 C 111 0.1U_0402_16V4Z 1 2 3 4 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT1 Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet Tuesday, May 18, 2010 5 9 of 41 1 2 3 4 5 A A +3VS_CK505_G +3VS_CK505 U6 R1 06 1 R1 08 1 CL K_BUF_CKSSCD R1 09 1 CL K_BUF_CKSSCD# R1 11 1 <12> CL K_BUF_CKSSCD <12> CL K_BUF_CKSSCD# CLK_DMI CLK_DMI# <12> CLK_DMI <12> CLK_DMI# R1 13 1 R1 14 1 2 0_0402_5% 2 0_0402_5% +3VS_CK505 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% +1.05VS_CK505 1 2 3 4 5 6 7 8 L_CLK_BUF_DOT96 L_CLK_BUF_DOT96# 9 10 11 12 13 14 15 16 L _CLK_BUF_CKSSCD L_CLK_BUF_CKSSCD# L_CLK_DMI L_CLK_DMI# CPU_S TOP# VDD_DOT VSS_DOT DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS VSS_27 VSS_SATA SRC_1/SATA SRC_1#/SATA# VSS_SRC SRC_2 SRC_2# VDD_SRC_IO CPU_STOP# SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 TGND CLK_BUF_DOT96 CLK_BUF_DOT96# <12> CLK_BUF_DOT96 <12> CLK_BUF_DOT96# SLG8LV595VTR_QFN_32P_5X5 R 107 1 2 33_0402_5% CLK _XTAL_IN CLK_XTAL_OUT CLK_14M_PCH SMB_CLK_S3 <9,12,22> SMB_DATA_S3 <9,12,22> CLK_14M_PCH <12> 1 CK _P WRGD 2 R _CLK_BUF_BCLK R_CLK_BUF_BCLK# R 110 1 R 112 1 C1 63 @ 10P_0402_50V8C 2 0_0402_5% 2 0_0402_5% CLK_BUF_BCLK CLK_BUF_BCLK# CLK_BUF_BCLK <12> CLK_BUF_BCLK# <12> +1.05VS_CK505 +3VS_CK505_G B 33 B SMB _CLK_S3 S MB_DATA_S3 R EF_0/CPU_SEL +1.05VS CPU_1 0 (Default) 133MHz 133MHz 1 100MHz 100MHz 1 R 1465 2 @ 10K_0402_5% 1 R 1466 2 10K_0402_5% 2nd Source : IDT ICS9LVS3197BKLFT MLF 32P REALTEK RTM890N-632-VB-GRT QFN 32P R EF_0/CPU_SEL R 115 1 2 10K_0402_5% CK _P WRGD +3VS_CK505 6 CPU_0 Q7A 2 1 PIN 30 +3VS_CK505 +3VS +3VS_CK505_G +3VS C LK_EN# <37> 2N7002DW-7-F_SOT363-6 +1.5VS +3VS_CK505 +1.05VS +1.05VS_CK505 R1 17 Close to U6 Close to U6 2 2 2 1 2 1 2 1 2 2 0_0603_5% 1 R1 20 2 0_0603_5% C1 64 10U_0805_10V4Z 2 1 C1 69 0.1U_0402_16V4Z 2 1 C1 68 0.1U_0402_16V4Z EMI request, Compal SI, 1/19 1 C1 67 0.1U_0402_16V4Z FBMA-L11-160808-301LMA20T_0603~D 1 C1 66 0.1U_0402_16V4Z 2 1 C1 65 0.1U_0402_16V4Z 2 1 R 116 1 2 10K_0402_5% C 176 47P_0402_50V8J 2 1 C 175 0.1U_0402_16V4Z 2 1 C 174 0.1U_0402_16V4Z 2 1 C 173 0.1U_0402_16V4Z 1 C 172 10U_0805_10V4Z 2 C 171 10U_0805_10V4Z 1 C CPU_S TOP# 2 0_0603_5% C1 70 47P_0402_50V8J 1 R1 18 1 @ R1 43 CLK_XTAL_OUT CLK _XTAL_IN install R120 for low power CLKGEN C 14.318MHZ 16PF 7A14300083 Y1 2 C 177 33P_0402_50V8J 1 2 2 1 1 C1 78 33P_0402_50V8J Close to U2 within 500mil D D Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. CLOCK GENERATOR Size D ocument Number Rev 0 .5 L A-6161P Dat e: T uesday, May 18, 2010 Sheet 5 10 of 41 1 2 3 +R TCVCC PCH_RTCX1 R1 21 R1 24 S M_INTRUDER# 2 1M_0402_5% PCH_INTVRMEN 2 330K_0402_5% 1 1 R1 22 1 R1 25 2 2 HDA_BIT_CLK_CODEC 47P_0402_50V8J 2 @ 2 10K_0402_5% S I RQ 1 10K_0402_5% SB_SPKR 2 HDA _SDOUT_CODEC 47P_0402_50V8J RTCRST# D17 SRTCRST# S M_INTRUDER# A16 INTRUDER# PCH_INTVRMEN A14 INTVRMEN <23> HDA_BIT_CLK_CODEC R1 30 1 2 33_0402_5% HDA_BIT_CLK A30 HDA_BCLK R1 32 1 2 33_0402_5% HDA _S Y NC D29 HDA_SYNC SB_SPKR R1 34 1 <23> HD A_RST#_CODEC 2 33_0402_5% R1 37 1 <23> HDA _SDOUT_CODEC 2 33_0402_5% AQUAWHITE _BATLED B C14 <23> HDA _S Y NC_ CODEC <23> HDA _ SDIN0 for RF PCH_RTCRST# PCH_SRTCRS T# 1 R 1457 R 1461 1 for i-AMT setting. 11/20 HP +3VALW P1 SPKR HDA_RST# C30 HDA_RST# HDA _ SDIN0 G30 HDA_SDIN0 F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3 B29 HDA_SDO H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 PCH_JTA G_TCK M3 JTAG_TCK PCH_JTAG_TMS K3 JTAG_TMS PCH_JTAG_TDI K1 JTAG_TDI PCH_JTAG_TDO J2 JTAG_TDO PCH_TRST# J4 JTAG_RST# H DA_SDOUT 2 PCH_GPIO33 1K_0402_5% 2 100K_0402_5% T147 P AD T148 P AD T149 P AD T150 P AD T121 JTAG 11/20 HP P AD LAD0 LAD1 LAD2 LAD3 D33 B33 C32 A32 FWH4 / LFRAME# C34 LDRQ0# LDRQ1# / GPIO23 A34 F34 GPIO23 SERIRQ AB9 S I RQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 FWH0 / FWH1 / FWH2 / FWH3 / LPC CLR P2 @ SHORT PADS RTCX1 RTCX2 SATA 1 C 183 1U_0603_10V4Z B13 D13 RTC 1 2 1 2 R1 26 20K_0402_1% 1 2 R1 27 20K_0402_1% CLR P1 @ SHORT PADS PCH_RTCX1 PCH_RTCX2 IHDA 2 2 C1 82 18P_0402_50V8J 1 +R TCVCC 1 <23> SB_SPKR @ 1 C1 88 5 U7A C 180 1 1U_0603_10V4Z 2 4 1 @ 1 C1 86 OSC OSC 2 Y2 NC 2 NC C 181 32.768KHZ_12.5PF_Q13MC14610002 18P_0402_50V8J A 1 PCH_RTCX2 2 10M_0402_5% 3 1 R 123 4 +3VS SATAICOMPO AF16 SATAICOMPI AF15 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 +VREG_51125 2 0_0402_5% 1 2 C 210 RT C1 CHN202UPT_SC-70 - 1 + - 2 W=20mils L 1U_0603_10V4Z JBATT1 + R 261 1K_0402_5% RT C2 1 2 3 2 1 LOTES_AAA-BAT-019-K01_2P C ONN@ B SATAICOMPI SPI_CS1# SATALED# T3 <28> KBC_SPI_SI_R AY1 SPI_MOSI SATA0GP / GPIO21 Y9 GPIO21 <28> KBC_SPI_SO AV1 SPI_MISO SATA1GP / GPIO19 V1 HD D_HALTLED 1 R 142 2 37.4_0402_1% +3VS +1.05VS 2 SPI_CS0# AY3 +3VALW <19> <19> <19> <19> R2 34 1 SPI_CLK +3VALW SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 D36 AV3 R 145 1 2 10K_0402_5% +3VS R1 47 10K_0402_5% SATA_LED# <20> 1 +3VALW SPI <28> KBC_SPI_CS1#_R 11/20 HP +3VS +R TCVCC KBC_SPI_CS1# 2 0_0402_5% 2 0_0402_5% 10K_0402_5% 1 S I RQ <27,28> BA2 1 R1 44 1 R1 48 A LPC_LFRAME# <27,28> R 1460 2 KBC_SPI_CS0# <28> KBC_SPI_CLK_R <28> KBC_SPI_CS0#_R <27,28> <27,28> <27,28> <27,28> HD D_HALTLED <20> GPIO21 IBEXPEAK-M_FCBGA1071 200_0402_5% @ 200_0402_5% for i-AMT setting. 11/20 HP R 156 200_0402_5% iAMT setting +3VS 1 PCH_JTAG_TMS 2 100_0402_1% @ R 1458 10K_0402_5% R 1459 330K_0402_5% Ref. ES1 ES2 Production R157 Unstuff 200 ohm Unstuff R166 Unstuff 100ohm Unstuff Q86A 2N7002DWH 2N SOT363-6 2 <25,28> AQUAWHITE_BATLED# All 1 Pre-Production Units PCH Pin AQUAWHITE _BATLED 6 1 @ 1 @ 100_0402_1% R 165 2 100_0402_1% @ 2 2 PCH_JTA G_TCK 51_0402_5% R1 66 2 1 R1 76 R1 67 2 @ PCH_JTAG_TDO 1 PCH_JTAG_TDI @ 2 R1 57 2 R1 58 1 1 @ 1 1 C 2 C PCH_JTAG_TDO GPIO33 R158 200 ohm 200 ohm Unstuff R167 100ohm 100ohm Unstuff PCH_JTAG_TDI D R156 200 ohm 200 ohm R165 100ohm 100ohm R176 51 ohm 5% 51 ohm 5% Unstuff iAMT Enable /Disable Hi Enable (Default) Lo Disable D PCH_JTAG_TMS Unstuff Compal Secret Data Security Classification PCH_JTAG_TCK 51 ohm 5% Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. IBEX-M(1/6)-HDA/JTAG/SATA Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 5 11 of 41 1 2 3 4 SMB _CLK_S3 5 R1 83 1 2 10K_0402_5% S MB_DATA_S3 R1 85 1 2 10K_0402_5% SM BCLK 1 R1 84 SMBDATA 1 R1 86 SML0CLK 1 R1 87 S ML0DATA 1 R1 88 SML1CLK 1 R1 89 S ML1DATA 1 R1 91 S ML0ALERT# R 192 1 +3VS U 7B <22> <22> <22> <22> WWAN B C1 97 1 C1 98 1 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_C_DRX_N7 PCIE_PTX_C_DRX_P7 C 1301 1 C 1302 1 PERN4 PERP4 PETN4 PETP4 BF33 BH33 BG32 BJ32 PERN5 PERP5 PETN5 PETP5 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE _PRX_DTX_N6 BA34 PCIE_PRX_DTX_P6 AW34 PCIE _PTX_DRX_N6 BC34 PCIE_PTX_DRX_P6 BD34 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE _PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE _PTX_DRX_N7 PCIE_PTX_DRX_P7 11/21 HP +3VALW R2 00 1 2 10K_0402_5% AT34 AU34 AU36 AV36 PERN7 PERP7 PETN7 PETP7 BG34 BJ34 BG36 BJ36 PERN8 PERP8 PETN8 PETP8 AK48 AK47 CLKOUT_PCIE0N CLKOUT_PCIE0P P9 AM43 AM45 +3VS R2 02 1 2 10K_0402_5% U4 AM47 AM48 +3VS R2 05 1 2 10K_0402_5% PERN6 PERP6 PETN6 PETP6 N4 J14 S ML0ALERT# C6 SML0CLK SML0DATA G8 S ML0DATA SML1ALERT# / GPIO74 M14 S ML1ALERT# SML1CLK / GPIO58 E10 SML1CLK SML1DATA / GPIO75 G12 S ML1DATA CL_CLK1 T13 CL_DATA1 T11 CL_RST1# T9 PEG_A_CLKRQ# / GPIO47 H1 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P R 1462 1 SMBDATA 2 10K_0402_5% SMB_CLK_S3 <9,10,22> 3 S MB_DATA_S3 4 SMB_DATA_S3 <9,10,22> 2N7002DW-T/R7_SOT363-6 Q8B AD43 AD45 B AN4 R_CLK_EXP# AN2 R_CLK_EXP R 195 1 R 196 1 2 0_0402_5% 2 0_0402_5% CLK_EXP# <4> CLK_EXP <4> AT1 R _CLK_DP# AT3 R_ CLK_DP R 197 1 R 198 1 2 0_0402_5% 2 0_0402_5% CLK_DP# <4> C LK_DP <4> CLK_DMI# <10> CLK_DMI <10> CLKIN_BCLK_N CLKIN_BCLK_P AP3 AP1 CLK_BUF_BCLK# <10> CLK_BUF_BCLK <10> CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DOT96# <10> CLK_BUF_DOT96 <10> AH13 AH12 CL K_BUF_CKSSCD# <10> CL K_BUF_CKSSCD <10> CLKIN_DMI_N CLKIN_DMI_P SMB _CLK_S3 2 10K_0402_5% +3VS 2 10K_0402_5% AW24 BA24 Q2A 2N7002DW-T/R7_SOT363-6 SML1CLK 1 6 R2 63 1 2 0_0402_5% 3 R2 64 1 2 0_0402_5% CAP_CLK <28> +3VALW S ML1DATA 4 CAP_DAT <28> 2N7002DW-T/R7_SOT363-6 Q2B +3VL CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 Q8A 2N7002DW-T/R7_SOT363-6 SM BCLK 6 1 11/20 HP CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P PCIECLKRQ0# / GPIO73 A S ML1ALERT# R 194 1 LID _SW_PCH# R 199 1 2 BA32 BB32 BD32 BE32 SMBDATA SML0CLK SML0ALERT# / GPIO60 SMBus PCIE _PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE _PTX_DRX_N4 PCIE_PTX_DRX_P4 PERN3 PERP3 PETN3 PETP3 SM BCLK C8 5 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_C_DRX_N6 PCIE_PTX_C_DRX_P6 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z AU30 AT30 AU32 AV32 LID _SW_PCH# H14 2 <21> <21> <21> <21> GLAN C1 93 1 C1 94 1 PERN2 PERP2 PETN2 PETP2 B9 5.1K_0402_5% R 695 1 2 12/05 HP R 1479 1 R 1480 1 <22> CLK_PCIE_MCARD2# <22> CLK_PCIE_MCARD2 2 0_0402_5% 2 0_0402_5% CLK_PCIE_MCARD2#_R CLK_PCIE_MCARD2_R C WLAN AH42 AH41 A8 <22> CLK REQ_WWAN# R 208 1 R 209 1 <22> CLK_PCIE_MCARD# <22> CLK_PCIE_MCARD 2 0_0402_5% 2 0_0402_5% CLK_PCIE_MCARD#_R C LK_PCIE_MCARD_R AM51 AM53 M9 <22> C LKREQ_WLAN# AJ50 AJ52 +3VALW R2 13 1 +3VALW R7 01 1 2 10K_0402_5% H6 AK53 AK51 2 10K_0402_5% P13 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56 REFCLK14IN P41 CLKIN_PCILOOPBACK J42 R 694 1 2 5.1K_0402_5% CLK_14M_PCH <10> CAP_CLK CAP_DAT C LK_PCI_FB <14> XTAL25_IN XTAL25_OUT AH51 AH53 X TAL25_IN XTAL25_OUT XCLK_RCOMP AF38 XCLK _RCOMP R2 11 1 C X TAL25_IN 2 90.9_0402_1% CLKOUTFLEX0 / GPIO64 T45 T55 P A D CLKOUTFLEX1 / GPIO65 P43 T56 P A D CLKOUTFLEX2 / GPIO66 T42 T139 P A D CLKOUTFLEX3 / GPIO67 N50 T140 P A D +1.05VS XTAL25_OUT 1 R 210 2 1M_0402_5% Y3 1 Clock Flex WWAN +3VALW 5 WLAN PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 SMBDATA Link <22> <22> <22> <22> SMBCLK Controller change from poert2 to port4. 11/20 HP SMBALERT# / GPIO11 PEG AW30 BA30 BC30 BD30 PERN1 PERP1 PETN1 PETP1 PCI-E* A From CLK BUFFER BG30 BJ30 BF29 BH29 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 25MHZ_20PF_7A25000012 1 C 199 2 18P_0402_50V8J 1 C2 00 2 18P_0402_50V8J IBEXPEAK-M_FCBGA1071 D D Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. IBEX-M(2/6)-PCI-E/SMBUS/CLK Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 5 12 of 41 5 4 3 2 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BD24 BG22 BA20 BG20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP <5> <5> <5> <5> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN <5> <5> <5> <5> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP 1 R2 20 VGATE 2 1K_0402_5% 1 R2 24 C M_PWROK 2 0_0402_5% +3VALW <28> SUS_PWR_ACK <4> PM_PWRBTN#_R <25,28> O N/OFFBTN# 1 R2 31 0_0402_5% <28> AC_PRESENT FDI FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT BJ14 FDI _INT FDI_FSYNC0 BF13 FDI_FS Y N C0 FDI_FSYNC1 BH13 FDI_FS Y N C1 FDI_LSYNC0 BJ12 FDI_LS Y NC0 FDI_LSYNC1 BG14 FDI_LS Y NC1 SYS_RESET# WAKE# M6 SYS_PWROK CLKRUN# / GPIO32 K5 2 2 0_0402_5% C16 10K_0402_5% 2 10K_0402_5% M1 2 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 T6 2 AUXP WROK A10 10K_0402_5% 1 R2 28 1 R2 29 1 R 1467 DMI DMI_IRCOMP PM_DRAM_PW RGD D9 <4> PM_DRAM_PWRGD 11/20 HP BF25 B17 1 R2 25 <33> R PGOOD <28> PM_RSMRST# DMI_ZCOMP BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST# SUS_PWR_ACK / GPIO30 P5 PWRBTN# P7 ACPRESENT / GPIO31 J12 PCIE_WA KE# Y1 P M_CLKRUN# SUS_STAT# / GPIO61 P8 SUSCLK / GPIO62 F3 SUS_CLK SLP_S5# / GPIO63 E4 SLP_S5# FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <5> <5> <5> <5> <5> <5> <5> <5> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <5> <5> <5> <5> <5> <5> <5> Close <5> <18> ENABLT <18> E NA VDD T48 T47 L_BKLTEN L_VDD_EN <18> INV_PWM Y48 L_BKLTCTL DDC2_ CLK D DC2_DATA <18> DDC2 _CLK <18> D DC2_DATA 1 1 R7 71 R7 72 +3VS FDI _INT <5> FDI_FS Y N C0 <5> FDI_FS Y N C1 <5> R7 731 2 AB46 2 10K_0402_5% V48 10K_0402_5% 2 2.37K_0402_1% AP39 AP41 P AD T57 AV53 AV51 LVDSA_CLK# LVDSA_CLK BB47 BA52 AY48 AV47 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 <18> LVDS_A0P <18> LVDS_A1P <18> LVDS_A2P BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AP48 AP47 LVDSB_CLK# LVDSB_CLK AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED M_BLUE M_GRE EN M_RED T58 P AD H7 SLP_S4# <30,36> SLP_S3# P12 SLP_S3# <21,23,28,29,30,32,34,35> SLP_M# K8 TP23 N2 delete R84, R66,R67 11/20 HP <19> 3V DDC CL <19> 3V DD CDA <19> CRT_HS Y NC <19> CRT_ VSYNC SDVO_INTN SDVO_INTP BG44 BJ44 AU38 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 D C U50 U52 R 226 R 227 DP D_CTRLCLK <17> 2.2K_0402_5% 2.2K_0402_5% +3VS DPD_CTRLDATA <17> V51 V53 CRT_DDC_CLK CRT_DDC_DATA CRT_HS Y NC CRT_ VSYNC Y53 Y51 CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN T51 T53 DDPB_AUXN DDPB_AUXP DDPB_HPD DDPD_CTRLCLK DDPD_CTRLDATA 3V DDC CL 3V DDC DA DA C_I REF AD48 AB51 BJ48 BG48 BF45 BH45 SDVO_CTRLCLK SDVO_CTRLDATA <18> LVDS_A0N <18> LVDS_A1N <18> LVDS_A2N <19> M_BLUE <19> M_GREEN <19> M_RED SLP_S4# LVD_IBG LVD_VBG <18> LVDS_ACLKN <18> LVDS_ACLKP P M_CLKRUN# <28> BJ46 BG46 SDVO_STALLN SDVO_STALLP L_CTRL_CLK L_CTRL_DATA LVD_VREFH LVD_VREFL PCH and mini space 20mil PCIE_WAKE# <21,22> T144 P AD L_DDC_CLK L_DDC_DATA AT43 AT42 FDI_LS Y NC0 <5> FDI_LS Y NC1 <5> AB48 Y45 SDVO_TVCLKINN SDVO_TVCLKINP Display Port C <37> VGATE R 408 1 2 SYS_RS T# 0_0402_5% 1 R2 23 <4> XDP_DBRESET# <28,37> P GD _IN DMI_IRCOMP 2 49.9_0402_1% BH25 System Power Management +1.05VS FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 Digital Display Interface <5> <5> <5> <5> DMI0RXN DMI1RXN DMI2RXN DMI3RXN CRT DMI_CTX_PRX_N0 BC24 DMI_CTX_PRX_N1 BJ22 DMI_CTX_PRX_N2 AW20 DMI_CTX_PRX_N3 BJ20 Display Port B DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 SDVO D U7D <5> <5> <5> <5> LVDS U7C 1 R 232 DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DPD_A UX# DPD_A UX DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 DPD_TXN0 DPD_TXP0 DPD_TXN1 DPD_TXP1 DPD_TXN2 DPD_TXP2 DPD_TXN3 DPD_TXP3 DPD_AUX# <17> DPD_AUX <17> DP D_H PD <17> DPD_TXN0 DPD_TXP0 DPD_TXN1 DPD_TXP1 DPD_TXN2 DPD_TXP2 DPD_TXN3 DPD_TXP3 <17> <17> <17> <17> <17> <17> <17> <17> IBEXPEAK-M_FCBGA1071 LOW_B AT_R IB EX_R# A6 F14 BATLOW# / GPIO72 PMSYNCH BJ10 RI# SLP_LAN# F6 1K_0402_0.5% H_ PM_SYNC <4> SLP_LAN# DP D_H PD R 235 1 2 100K_0402_5% IBEXPEAK-M_FCBGA1071 +3VS P M_CLKRUN# B 1 R2 37 2 VGATE 1 R2 36 2 10K_0402_5% 10K_0402_5% B +3VALW SYS_RS T# 2 LOW_B AT_R 2 1 @ R2 38 1 R2 39 SLP_LAN# 1 @ R2 41 IB EX_R# 1 R2 43 PCIE_WA KE# 1 R2 45 AC_PRE SENT 1 R2 46 2 2 2 2 10K_0402_5% SLP_S3# 10K_0402_5% SLP_S4# 10K_0402_5% SLP_S5# 10K_0402_5% 1 R 240 1 R 242 1 R 244 @ @ @ 2 2 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 1K_0402_5% 10K_0402_5% A A Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. IBEX-M(3/6)-DMI/GPIO/LVDS Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 1 13 of 41 4 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 PCI_GNT0# MODE M_DISABLE PCI_GNT2# PCI_GNT3# F48 K45 F36 H53 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQE# P C I_PIRQF# P CI_PIRQG# ACCEL_INT# B41 K53 A36 A48 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 P C I_SERR# P C I_PERR# E44 E50 <22> ACCEL_INT# K6 <27,28> P C I_SERR# P AD T138 B IRDY# PAR DEVSEL# FRAME# PCI_LOCK# D49 PLOCK# PCI_STOP# P CI_ TRDY# D41 C48 STOP# TRDY# M7 PME# D5 PLTRST# +3VS PCI_REQ2# PCI_REQ1# PCI_FRAM E# P CI_ TRDY# 1 1 1 1 R 1367 R 1368 R 1369 R 1370 R 1371 R 1372 R 1374 R 1376 2 2 2 2 2 2 2 2 AV7 NV_WR#0_RE# NV_WR#1_RE# AY8 AY5 NV_WE#_CK0 NV_WE#_CK1 AV11 BF5 USBRBIAS# B25 USBRBIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 N16 J16 F16 L16 E14 G16 F12 T15 2 1K_0402_5% P CH_ DDR_RST DMI Termination Voltage <21> CB _ IN# GPIO15 Set to Vcc when HIGH NV_CLE Set to Vss when LOW Weak internal PU,Do not pull low N V_CLE @ R1 90 1 T134 P AD +3VS L AN_DIS# <21> L AN_DIS# @ 1 R2 78 2 0_0402_5% 2SATA_CLKREQ# 10K_0402_5% T145 P AD T146 P AD <21> CLK_PCIE_LAN_REQ# USB20_N3 USB20_P3 <24> <24> <24> <24> USB20_N3 <24> USB20_P3 <24> USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N5 USB20_P5 USB20_N6 USB20_P6 <24> <24> <22> <22> Power USB USB_SB T133 P AD Card Reader R4 30 10K_0402_5% USB20_N12 USB20_P12 USB20_N12 <18> USB20_P12 <18> USBRBIAS 1 R 259 2 22.6_0402_1% L 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% PCI_REQ0# PCI_PIRQB# P C I_PIRQF# PCI_REQ3# 1 1 1 1 R 1385 R 1387 R 1389 R 1390 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 5 CLK_PCIE_LAN# <21> CLK_PCIE_LAN <21> GATEA20 <28> 1 H_P ECI <4> KB_RST# <28> 2 56_0402_5% H_THERMTRIP# <4> R2 56 56_0402_5% SATACLKREQ# / GPIO35 SATA2GP / GPIO36 TP1 BA22 T59 P AD AB13 SATA3GP / GPIO37 TP2 AW22 T60 P AD T61 P AD + VCCP T63 P AD PCIECLKRQ7# / GPIO46 TP6 T64 P AD GPIO48 AB6 SDATAOUT1 / GPIO48 TP7 AV45 T65 P AD PCH_XDP_GPIO49 AA4 SATA5GP / GPIO49 TP8 AF13 T66 P AD GPIO57 TP9 M18 T67 P AD TP10 N18 T68 P AD TP11 AJ24 T69 P AD TP12 AK41 T70 P AD TP13 AK42 T71 P AD TP14 M32 T72 P AD TP15 N32 T73 P AD TP16 M30 T74 P AD TP17 N30 T75 P AD TP18 H12 T76 P AD VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 C LK_CPU_BCLK <4> +3VS H_CP UP W RGD <4> T62 P AD <16> P CH _NCTF6 <16> P CH _NCTF7 1 0_0402_5% 1 0_0402_5% +3VS 0_0402_5% R2 54 1 2 R2 60 1 2 10K_0402_5% R2 55 AB7 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 1 2 10K_0402_5% H_THERMTRIP#_L AV43 LANLINK_STATUS# <21> TP19 AA23 T77 P AD NC_1 AB45 T78 P AD NC_2 AB38 T79 P AD NC_3 AB42 T80 P AD NC_4 AB41 T81 P AD NC_5 T39 T82 P AD P6 T83 P AD C10 T84 P AD INIT3_3V# TP24 C CLK_PCI_KBC 1 2 C6 35 12P_0402_50V8J C LK_PCI_FB 1 2 C6 58 12P_0402_50V8J for RF, SI B IBEXPEAK-M_FCBGA1071 +3VALW WLAN_TRANSMIT_OFF# <28> CLK_PCI_KBC R 266 1 <27> CL K_PCI_DB <12> C LK_PCI_FB R 274 1 R 276 1 2 22_0402_5% 2 22_0402_5% 2 22_0402_5% C LK_PCI_KBC_R GPIO15 R 302 1 @ 2 10K_0402_5% CLK_PCI_DB_P CL K_PCI_FB_R R2 88 1 2 10K_0402_5% NPCI_RST# R2 68 1 2 10K_0402_5% WWAN_TRANSMIT_OFF# R 273 1 2 10K_0402_5% SATA_CLKREQ# R2 72 1 2 10K_0402_5% GPIO24 R 277 1 2 10K_0402_5% PCH_XDP_GPIO49 R2 75 1 2 10K_0402_5% GPIO15 R 280 1 2 1K_0402_5% ISO_P REP# R 283 1 2 10K_0402_5% ALS_EN# R2 81 1 2 10K_0402_5% RUNS CI _EC# R2 85 1 2 10K_0402_5% USB_OC#0 R 289 1 2 10K_0402_5% WEBCAM_OFF R2 87 1 2 @ 10K_0402_5% P CH_ DDR_RST R 291 1 2 10K_0402_5% PCH_XDP_GPIO16 R2 90 1 2 10K_0402_5% USB_OC#4 R 293 1 2 10K_0402_5% CPP E# R 295 1 2 10K_0402_5% GPIO48 R2 96 1 2 10K_0402_5% STP_PCI# R2 99 1 2 10K_0402_5% GPIO7 R3 04 1 2 10K_0402_5% +3VS PCI_GNT0# R2 67 1 2 @ 1K_0402_5% MODE M_DISABLE R2 71 1 2 @ 1K_0402_5% PCI_GNT3# R3 00 1 2 @ 1K_0402_5% <4> BUF_PLT_RST# 4 USB_OC#2 IN1 1 IN2 2 O @ R 1470 100K_0402_5% P LT_RST# Issued Date 4 R 301 1 2 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 A 10K_0402_5% Compal Secret Data Security Classification @ SN74AHC1G08DCKR_SC70-5 +3VS R 269 1 2 0_0402_5% P 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% BD10 IBEXPEAK-M_FCBGA1071 G 2 2 2 2 THRMTRIP# AY46 <16> P C H_NCTF26 3 R 1383 R 1384 R 1386 R 1388 BE10 F1 FP R _OFF <19> 1 1 1 1 1 PROCPWRGD GPIO46 U10 PCI_PIRQA# PCI_LOCK# P CI _PIRQC# P CI_PIRQG# T1 KB _RST# AY45 5 R 1379 R 1380 R 1381 R 1382 STP_PCI# / GPIO34 P CH _PECI_R TP5 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 1 1 1 1 RCIN# BG10 TP4 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% P CI_IRD Y# P C I_PERR# PCI_DEVS EL# P C I_SERR# PECI GPIO27 M11 V3 R 251 2 2 R 252 CLK_CPU_BCLK# <4> PCIECLKRQ6# / GPIO45 USB_OC#0 ISO_P REP# LANLINK _STATUS# CPP E# CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 TP3 CPU Type Detect : High-->SV , Low-->ULV USB_OC#2 FP R_ OFF USB_OC#4 MEM_LED / GPIO24 AM3 SDATAOUT0 / GPIO39 <16> P C H_NCTF19 BT_OFF <26> SCLOCK / GPIO22 CLKOUT_BCLK0_N / CLKOUT_PCIE8N SLOAD / GPIO38 GPIO46 2/24 U2 P3 R 1504 10K_0402_5% @ USB_CAM A20GATE H3 WLAN USB20_N8 <26> USB20_P8 <26> BT USB20_N9 <22> USB20_P9 <22> WWAN USB20_N10 <19> USB20_P10 <19> FPR AF48 AF47 CLK_PCIE_LAN_REQ# +3VALW 11/21 HP USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 TACH0 / GPIO17 GPIO28 WLAN_TRANSMIT_OFF# F8 <22> WLAN_TRANSMIT_OFF# CLKOUT_PCIE7N CLKOUT_PCIE7P CLK_PCIE_LAN#_R CLK_PCIE_LAN_R D SATA4GP / GPIO16 V13 V6 AH45 AH46 BB22 2/24 USB_SB GPIO15 Y7 CLKOUT_PCIE6N CLKOUT_PCIE6P R 253 LAN_PHY_PWR_CTRL / GPIO12 T7 H10 WEBCAM_OFF <18> WEBCAM_OFF USB20_N0 USB20_P0 USB20_N1 USB20_P1 GPIO8 K9 WWAN_TRANSMIT_OFF# AB12 <28> NPCI_RST# USB20_N0 USB20_P0 USB20_N1 USB20_P1 TACH3 / GPIO7 F38 @ R 1482 1 2 32.4_0402_1% J32 F10 AA2 STP_PCI# 1 @ R 257 TACH2 / GPIO6 ALS_EN# GPIO24 <20,22> WWAN_TRANSMIT_OFF# NV_A LE N V_CLE D37 PCH_XDP_GPIO16 W WAN_DET# <22> W WAN_DET# 2 1K_0402_5% TACH1 / GPIO1 1 @ R1 74 1 <4> P CH_D DR_RST AU2 NV_RCOMP NV_RB# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P GPIO7 NV_A LE BMBUSY# / GPIO0 2 BD3 AY6 RUNS CI _EC# <28> RUNS CI _EC# +1.8VS Y3 C38 MISC NV_ALE NV_CLE 10K_0402_5% PCH_XDP _GPIO0 2 <38> O CP# CPU AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 1 GPIO NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 R2 50 1 T132 P AD 2 A 1 1 1 1 SERR# PERR# A42 H44 F46 C46 C LK_PCI_KBC_RN52 CL K_PCI_FB_R P53 P46 P51 CLK_PCI_DB_P P48 PCI_PIRQE# PCI_STOP# P CI _PIRQD# ACCEL_INT# PCIRST# P CI_IRD Y# P CI_PAR PCI_DEVS EL# PCI_FRAM E# <4,21,22,27> PLT_RST# AV9 BG8 +3VS * 1 PIRQA# PIRQB# PIRQC# PIRQD# NV_DQS0 NV_DQS1 High=Endabled NV_ALE Low=Disable(floating) 2 G38 H51 B37 A44 NVRAM C/BE0# C/BE1# C/BE2# C/BE3# AY9 BD1 AP15 BD8 1 P AD T114 P AD T115 J50 G42 H47 G34 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_RCOMP F51 A46 B45 M53 C 2 U 7F 2 PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 USB PCI_PIRQA# PCI_PIRQB# P CI _PIRQC# P CI _PIRQD# H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 PCI D 3 Intel Anti-Theft Techonlogy NCTF U7E RSVD 5 Title Compal Electronics, Inc. IBEX-M(4/6)-PCI/USB/RSVD Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 1 14 of 41 1 2 3 4 5 +3VS VCC3_3[14] 0.032A VCCSATAPLL[1] VCCSATAPLL[2] Y22 DCPSUS U19 VCCSUS3_3[30] 1 2 1 2 +3VS 0.1U_0402_16V4Z 1 1 2 C2 70 0.1U_0402_16V4Z T126 T127 C2 71 2 R 303 1 +1.8VS P AD P AD VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 AT16 VCCDMI[2] AU16 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 P AD 2 0_0402_5% +1.05VS_VCCFDIPLL T125 VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 LVDS HVCMOS +1.8VS DMI B 0.061A 0.156A AN30 AN31 VCCIO[54] VCCIO[55] AN35 VCC3_3[1] AT22 VCCVRM[1] 0.035A BJ18 VCCFDIPLL 6mA AM23 VCCIO[1] 0.085A +VCCP 1 C 261 VCCSUS3_3[31] U22 VCCSUS3_3[32] V15 VCC3_3[5] V16 VCC3_3[6] Y16 VCC3_3[7] C2 91 1 2 VCCRTC 2mA IBEXPEAK-M_FCBGA1071 HDA A12 >1mA CPU V_CPU_IO[2] 6mA VCCSUSHDA R 671 1 2 0_0402_5% +1.8VS @ R 672 1 2 0_0402_5% +3VS R6 73 2 0_0402_5% 1 +3VS C +3VS 1 2 +PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23 L10 +V1.05S_VCCA_A_DPL 1 2 10UH_LB2012T100MR_20%_0805 1 1 + C2 81 @ C 282 1U_0402_6.3V4Z 220U_B2_2.5VM_R35M R 311 1 L30 1 1 1 1 R3 05 R3 06 R3 07 R3 08 +3VS 1 +1.05VS 22 2 1 C 1337 0.1U_0402_16V4Z C 1336 0.1U_0402_16V4Z 2 add 0.1uf(0402) on +3VS to GND near D3 & R1386 and R1386 (for 33MHz harmonic)for EMI request, Compal SI, 1/19 2 +1.05VS 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% +5VALW +3VALW L11 1 +3VALW 2 +5VS +3VS +V1.05S_VCCA_B_DPL 10UH_LB2012T100MR_20%_0805 1 @ C 288 1U_0402_6.3V4Z 1 2 2 R3 09 + C2 87 220U_B2_2.5VM_R35M D2 100_0402_5% R3 10 CH751H-40PT_SOD323-2 C 289 D3 100_0402_5% CH751H-40PT_SOD323-2 IC H_V5REF_SUS ICH_V 5R EF_RUN 20 mils 1U_0402_6.3V4Z C 292 1U_0402_6.3V4Z Issued Date Deciphered Date 2009/09/03 3 4 20 mils 1 1 2 2 Compal Secret Data 2008/09/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 2 1U_0603_10V4Z +1.05VS Security Classification 1 1 2 Don't need extra-power 1 0.1U_0402_16V4Z C 290 1U_0402_6.3V4Z 2mA @3.3V V_CPU_IO[1] RTC 2 AT18 AU18 1 2 +1.8VS C 279 2 1 0.1U_0402_16V4Z 1 C2 86 0.1U_0402_16V4Z C2 84 C2 85 4.7U_0603_6.3V6K 0. 1A@1.1V 2 2 1U_0402_6.3V4Z U20 + VCCP 1 AT20 VCCDMI[1] 2 2 0.1U_0402_16V4Z 1 VCCSUS3_3[29] +3VS 0. 4A@3.3V 2 0.1U_0402_16V4Z C 280 1 D VCCVRM[4] AT24 1 C 254 2 P18 SATA 0. 2A@3.3V 2 0.1U_0402_16V4Z C 278 1 2 1 +3VS AK3 AK1 AH22 VCCVRM[2] 2 +3VS IBEXPEAK-M_FCBGA1071 +3VALW +R TCVCC C2 62 0.1U_0402_16V4Z 2 AD13 VCCIO[9] AD35 C2 75 +V1.1A_INT_V CCSUS 2 0.1U_0402_16V4Z C 274 1 1 +1.05VS 1 AB35 VCC3_3[4] @ 2 DCPSST U35 VCC3_3[3] 2 +1.8VS 1 V12 VCC3_3[13] 3.208A +3VS VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] @ 1 VCCIO[4] P36 AB34 1 2 VCCIO[3] AF32 VCC3_3[12] VCC3_3[2] 1 2 AH34 VCC3_3[11] N36 VCCAPLLEXP0.042A 1 L43 1 2 0.1UH_MLF1608DR10KT_10% 1 VCCIO[2] M36 ICH_V 5R EF_RUN BJ24 PCI E* AF34 L38 VCCTX_LVDS[3] VCCTX_LVDS[4] AP43 AP45 AT46 AT45 NAND / SPI USB VCCIO[21] VCCIO[22] VCCIO[23] VCC3_3[9] VCC3_3[10] VCCTX_LVDS[1] 0.1U_0402_16V4Z AH23 AJ35 AH35 J38 AH39 C2 66 VCCADPLLB[1] VCCADPLLB[2] 0.357A K49 VCCALVDS VSSA_LVDS 0.1U_0402_16V4Z 0.073A BD51 BD53 V5REF VCC3_3[8] 2 C 265 VCCADPLLA[1] VCCADPLLA[2] >1mA 1 10U_0603_6.3V6M 0.072A Clock and Miscellaneous 0.035A VCCVRM[3] 1 2 PCI/GPIO/LPC DCPRTC IC H_V5REF_SUS VCCIO[24] FDI F24 0.030A 22U_0805_6.3V6M V5REF_SUS >1mA AK24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 +1.05VS +1.05VS C 260 V23 +1.05VS_APLL C 264 2 0.1U_0402_16V4Z C 272 U23 VCCIO[56] T124 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z C2 69 1U_0402_6.3V4Z C2 67 C2 68 1U_0402_6.3V4Z 1 +VCCSST 1 C V9 VCCSUS3_3[28] P AD C 263 +1.05VS 2 VCCME[12] Don't need extra-power 1U_0402_6.3V4Z +V1.05S_VCCA_B_DPL 2 VCCME[11] Y42 BB51 BB53 +V1.05S_VCCA_A_DPL 1 VCCME[10] Y41 AU24 +1.8VS 1 VCCME[9] Y39 A AH38 0.059AVCCTX_LVDS[2] 1U_0402_6.3V4Z B VCCME[8] V42 2 C 259 C 258 1 2 +VCCRTCEXT 0.1U_0402_16V4Z 1.998A 1 1U_0402_6.3V4Z 22U_0805_6.3V6M VCCME[7] V41 2 C 1000 2 V39 2 1 C 999 2 VCCME[6] 2 C 998 1 C 257 AF42 2 C 251 2 1 VCCME[5] 1 0.1U_0402_16V4Z C 256 VCCME[4] AF41 AF51 1 2 10UH_LB2012T100MR_20%_0805 @ +3VS +1.05VS C 250 1 C2 55 22U_0805_6.3V6M AF43 AF53 VSSA_DAC[2] 1 +3VALW 0.1U_0402_16V4Z 1U_0402_6.3V4Z C2 52 2 1U_0402_6.3V4Z VCCME[3] VSSA_DAC[1] @ 1 0.01U_0603_16V7K VCCME[2] AE52 0.01U_0603_16V7K AD39 AE50 VCCADAC[2] C2 44 VCCME[1] AD41 1 DCPSUSBYP AD38 VCCADAC[1] 0.1U_0402_16V4Z +1.05VS VCCLAN[2] 2 2 0.069A C2 43 2 Y20 0.1U_0402_16V4Z VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] 0.163AVCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] 2 POWER VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] 1.524A VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] 10U_0805_6.3V6M 1 C 247 0.344A C 246 1U_0402_6.3V4Z AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 C2 42 T111 VCCLAN[1] 1 1 L7 0.01U_0603_16V7K AF24 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 0.052A 1 C2 41 AF23 A P AD VCCACLK[2] V24 V26 Y24 Y26 10U_0805_6.3V6M 2 0_0402_5% AP53 VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] C2 40 1 R 1256 VCCACLK[1] 1U_0603_10V4Z POWER U 7J AP51 U7G CRT +1.05VS +1.05VS VCC CORE T123 PCI/GPIO/LPC P AD Title D C 293 1U_0603_6.3V6M Compal Electronics, Inc. IBEX-M(5/6)-PWR Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 5 15 of 41 1 2 3 AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 A +3VS 1 B R3 12 100K_0402_5% Q10A 2N7002DW-T/R7_SOT363-6 2 CRACK_BGA <8,28> 6 2 1 <14> P CH _NCTF6 +3VS CRACK_BGA 3 R3 13 100K_0402_5% Q10B 2N7002DW-T/R7_SOT363-6 5 4 <14> P CH _NCTF7 +3VS CRACK_BGA C 6 R3 14 100K_0402_5% Q11A 2N7002DW-T/R7_SOT363-6 2 <14> P CH _NCTF19 +3VS IBEXPEAK-M_FCBGA1071 1 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] 1 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] 2 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 1 AB16 CRACK_BGA 3 R3 15 100K_0402_5% Q11B 2N7002DW-T/R7_SOT363-6 5 <14> P CH _NCTF26 4 C H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 1 B U7H VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] 2 A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] 5 2 U 7I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 4 BGA Ball Cracking Prevention and Detection IBEXPEAK-M_FCBGA1071 D D Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. IBEX-M(6/6)-GND Size D ocument Number Cus t om L A-6161P Dat e: Rev 0 .5 Sheet T uesday, May 18, 2010 5 16 of 41 5 4 3 2 1 2 +3VS D DC_E N 5 D DC_E N 1 D Q5B 2N7002DW-7-F_SOT363-6 3 4 2 Q5A 2N7002DW-7-F_SOT363-6 DP D_CTRLCLK 1 6 N29441889 <13> DP D_CTRLCLK DPD_C_AUX# DPD_C_A UX 2 D N29441921 R 1097 100K_0402_5% 5 <13> DPD_CTRLDATA Q22B 2N7002DW-7-F_SOT363-6 3 4 2 Q22A 2N7002DW-7-F_SOT363-6 DPD_CTRLDA TA 1 6 1 R 1099 100K_0402_5% 2 +3VS 2 2 1 DPD_A UX# <13> DPD_AUX# DP _EN R 1101 100K_0402_5% @ 1 DPD_AUX#_1 6 6 1 DPD_A UX 4 2 <13> DPD_AUX C 3 4 2N7002DW-7-F_SOT363-6 Q24B +5VS +5VS 1 2 @ DPD_A UX_1 3 2N7002DW-7-F_SOT363-6 Q23B R 1105 100K_0402_5% 1 R 1107 10K_0402_5% D DC_E N 2 3 DP _EN 6 1 R 1106 10K_0402_5% F1 2N7002DW-7-F_SOT363-6 Q21A 2 5 1 1 Q21B 2N7002DW-7-F_SOT363-6 4 DP _DC AD NANOSMDC050F 0.5A 13.2V POLY-FUSE C 2 +3VS 5 5 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 Q23A Q24A DP _EN +3VS_DP 2 B <13> DPD_TXP0 DPD_TXP0 0.1U_0402_16V4Z 2 1 C 1304 J D P1 DP _ HPD DPD_C_AUX# DP_DATA 0R_P DPD_TXN0 0.1U_0402_16V4Z 2 1 C 1305 DP_DATA0R_N <13> DPD_TXP1 DPD_TXP1 0.1U_0402_16V4Z 2 1 C 1306 DP_DATA 1R_P DPD_TXN1 0.1U_0402_16V4Z <13> DPD_TXP2 DPD_TXP2 0.1U_0402_16V4Z 1 C 1307 DP_DATA1R_N 2 1 C 1308 DP_DATA 2R_P <13> DPD_TXN2 DPD_TXN2 0.1U_0402_16V4Z 2 1 C 1309 DP_DATA2R_N <13> DPD_TXP3 DPD_TXP3 0.1U_0402_16V4Z 2 1 C 1310 DP_DATA 3R_P <13> DPD_TXN3 DPD_TXN3 0.1U_0402_16V4Z 2 1 C 1311 DP_DATA3R_N 2 R 1115 1M_0402_5% 2 <13> DPD_TXN1 DP _DC AD DP_DATA3R_N 1 <13> DPD_TXN0 R 1114 5.1M_0402_5% 2 1 DPD_C_A UX DP_DATA 3R_P DP_DATA2R_N DP_DATA 2R_P DP_DATA1R_N DP_DATA 1R_P DP_DATA0R_N DP_DATA 0R_P 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C ONN@ DP_PWR RTN HP_DET AUX_CHGND AUX_CH+ GND CA_DET LANE3LANE3_shield LANE3+ LANE2LANE2_shield LANE2+ LANE1LANE1_shield LANE1+ LANE0LANE0_shield LANE0+ +5VS B 5 1 10U_0805_10V4Z C 665 2 0.1U_0402_16V4Z C 664 1 GND GND GND GND DP _ HPD 24 23 22 21 0_0402_5% 2 1 R 1117 3 4 DP D_H PD <13> Q12B TR 2N7002DW-7-F 2N SOT-363 MOLEX_105062-0001_20P-T A A Compal Secret Data Security Classification Issued Date 2009/08/03 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Display Port Connector Size D ocument Number Rev 0 .5 LA -6161P Dat e: T uesday, May 18, 2010 Sheet 1 17 of 41 5 4 3 2 1 LED/PANEL BD. CONN. B+_LCD 1 33_0402_5% R1121 1 2 BLON_PWM_R <13> INV_PWM +5V_WEBCAM CH751H-40_SC76 1 C1339 0.1U_0402_16V4Z 3/23 for EMI D5 C1318 0.1U_0402_16V4Z B+_LCD 3 +5V_WEBCAM 1 1 4 USB20_N12_R 3 for EMI VIN 2 @ L44 1 1 @ D6 2 0_0402_5% IO1 IO2 GND <14> USB20_P12 <14> USB20_N12 USB20_P12_R 2 4 1 C1333 2 4 3 2 USB20_P12_R USB20_N12_R 1U_0603_25V4Z C 1 2 2 R1471 B+ Q90 SI2307CDS-T1-GE3 1P 1 R1487 220K_0402_1% 1 CH751H-40_SC76 @ R1506 10K_0402_5% INV_PWM ACES_88242-3001_30P CONN@ 2 3 1 5/11 1 DDC2_CLK <13> DDC2_DATA <13> 2 +3VL R1123 10K_0402_5% 2 1 LVDS_ACLKN <13> LVDS_ACLKP <13> S 2 31 LVDS_A2N <13> LVDS_A2P <13> D +3VALW C 32 LVDS_A1N <13> LVDS_A1P <13> 1 1 <25,28> LID_SW# LVDS_A0N <13> LVDS_A0P <13> C1332 0.22U_0603_25V7K 2 USB20_P12_R USB20_N12_R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 G 2 1 R1122 100K_0402_1% D ISPLAY_OFF# 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 R1119 LCDVDD 10K_0402_5% D4 1 JLVDS1 +3VS R1120 <13> ENABLT 1 68P_0402_50V8J @ L38 1 2 LQM21FN4R7N00L_0805 2 R1118 2 B+ 1 0.1U_0603_50V C667 2 2.2K_0402_5% 1 +3VS C666 2 D +3VS 2.2K_0402_5% 1 D WCM2012F2S-900T04_0805 R1488 for RF CM1293A-02SR_SOT143-4 1 for ESD 100K_0402_5% 2 0_0402_5% 2 R1472 12/10 HP LCD POWER CIRCUIT LCDVDD LCDVDD S D R1128 10K_0402_5% 2 47K_0402_5% 2 1 @ 2 2 1 R1129 2 1 for RF 3 5/18 2 1 47P_0402_50V8J 2 1 2 R1127 100K_0402_5% 2 2.2U_0805_10V5R 2 C683 @ 4.7U_0805_10V4Z 1 4.7U_0805_10V4Z 2 G C682 +3VS Q55 DTC124EKAGZT146_SC59-3 1 1 OUT 2 1 Q6B 1 2N7002DW-7-F_SOT363-6 C684 0.1U_0402_16V4Z 5 <14> WEBCAM_OFF 2 +5VS 1 4 3 GND 2 2 0.22U_0402_10V4Z C1328 1 C680 C681 0.1U_0402_16V4Z C676 1 1 C679 1 2 47K_0402_5% C678 IN 1 1 G R1126 1 0.1U_0402_16V4Z D 1 2 Q54 SI2301BDS_SOT23 2 1M_0402_5% S 6 2 +5V_WEBCAM +5VS R1125 1 C677 1U_0603_10V4Z 2 2 2 +5VS 3 Q6A 2N7002DW-7-F_SOT363-6 R1130 100K_0402_1% 1 @ C1327 47P_0402_50V8J B Q53 3 SI2301 1P_SOT23 0.01U_0402_16V7K R1124 100_0402_1% <13> ENAVDD +3VS for RF 1 B 12/05 HP A A Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. LCD CONN & Q-Switch & GPIO Ext. Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet 1 18 of 41 1 2 3 4 5 +3VALW J FP R1 A D35 USB20_P10_R +C RTVDD W=40mils 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 0_0603_5% R 1448 1 GR EEN R 1450 1 2 B LUE R 1452 1 2 2 VGA_RE R 1449 1 2 0_0603_5% VGA_R VGA_GRR 1451 1 2 0_0603_5% VGA_G VGA_BL R 1453 1 2 0_0603_5% V GA_B 0_0603_5% 3 2 A 3 G CRT_ VSYNC Y 4 V S YNC_G_A 2 2 1 1 1 G G 16 17 +C RTVDD 1 0_0402_5% 1 R2 06 2 0_0402_5% 1 R1 93 2.2K_0402_5% D_D DCDATA 6 D_V S Y NC 1 @ C 253 U5 SN74AHCT1G125GW_SOT353-5 R 218 2.2K_0402_5% 5P_0402_50V8C 2 R2 15 2.2K_0402_5% 5P_0402_50V8C B R2 16 2.2K_0402_5% 3V DDC DA 1 2N7002DW-7-F_SOT363-6 3 D_DDCC LK 2 +C RTVDD +3VS Q17A 1 @ C 276 Place close to JCRT1 @ D34 +3VS D _ HS Y NC 2 R2 17 2 @ D18 S U YIN_070546FR015S290ZR CONN@ +CR TVDD 5 1 G <13> CRT_ VSYNC P OE# 5 1 P OE# U4 SN74AHCT1G125GW_SOT353-5 HS Y N C_G_A 4 Y 75_0402_1% R 1456 A 75_0402_1% R 1455 2 2 75_0402_1% R 1454 CRT_HS Y NC 2 1 @ 10P_0402_50V8J <13> CRT_HS Y NC 2 C 249 0.1U_0402_16V4Z 1 2 1 C 1298 @ 10P_0402_50V8J C 1296 +5VS C 273 0.1U_0402_16V4Z 1 2 C 1297 @ 10P_0402_50V8J +5VS 1 2 0_0603_5% B @ D17 1 close to JCRT1 RED V GA_B VGA_G VGA_R 1 0.1U_0402_16V4Z 2 C 245 J C RT1 3 2 1.1A_6VDC_FUSE DAN217T146_SC59-3 1 RB491D_SC59-3 2 2 for ESD F2 1 1 +RC RT_VCC D32 3 +5VS PRTR5V0U2X_SOT143-4 DAN217T146_SC59-3 1 2 2 1 IO1 IO2 GND 3 <14> FP R_ OFF VIN 3 DAN217T146_SC59-3 R 1464 220K_0402_1% 1 2 4 2 USB20_N10_R 1 1 +5VALW 2 2 2 5 6 A 3V DDC DA <13> 5 2 2 1 2 1 10U_0805_10V4K 1 C 1300 0.1U_0402_10V6K C 1299 G Q87 R 1463 10K_0402_5% 1 2 3 4 2 1 1 D S 3 2 0_0402_5% USB20_P10_R 2 0_0402_5% USB20_N10_R + FP_PWR R6 38 1 R6 39 1 <14> USB20_P10 <14> USB20_N10 2 SI2301BDS_SOT23 ACES_87151-04051_4P C ONN@ Finger printer 3V DDC CL 4 3V DDC CL <13> Q17B 2N7002DW-7-F_SOT363-6 close to PCH (U7) close to PCH (U7) C C 2.5' SATA HDD Connector CRT Termination/EMI Filter close to PCH (U7) J H DD1 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 S ATA_RXN0 SATA_RXP0 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C8 70 1 C8 71 1 SATA_PTX_DRX_P0 <11> SATA_PTX_DRX_N0 <11> SATA_PRX_DTX_N0 <11> SATA_PRX_DTX_P0 <11> <13> M_RED <13> M_GREEN <13> M_BLUE L2 1 2 HLC0603CSCC27NJT_0603 RED L3 1 2 HLC0603CSCC27NJT_0603 GR EEN M_BLUE L4 1 2 HLC0603CSCC27NJT_0603 B LUE C 248 0.1U_0402_16V4Z C 238 0.1U_0402_16V4Z C ONN@ C 239 0.1U_0402_16V4Z SANTA_192701-1_22P-T 1 1 1 1 2 2 2 2 2 C2 34 1 2 C2 37 1 2 C2 36 C 233 1 2 D C2 32 3/24 for EMI Compal Secret Data Security Classification Place component's closely SATA CONN.(JHDD1) 1 2 1 18P_0402_50V8J 2 C 235 1 18P_0402_50V8J 1 +5VS 18P_0402_50V8J 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 M_RED M_GRE EN 27P_0402_50V8J 24 23 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 27P_0402_50V8J D SATA_TXP0_C C8 72 1 SATA_TXN0_C C8 73 1 27P_0402_50V8J 26 25 V33 V33 V33 GND GND GND V5 GND V5 GND V5 GND Reserved GND V12 NC V12 NC V12 1 2 3 4 5 6 7 C 211 10U_0805_10V4Z GND A+ AGND BB+ GND Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 3 4 Title Compal Electronics, Inc. WLAN/ODD/HDD Size D ocument Number Rev 0.5 L A-6161P Dat e: Tuesday, May 18, 2010 Sheet 5 19 of 41 4 3 2 6 5 WW_LED# 2 2 0_0402_5% R1133 1 D R1131 47K_0402_5% 0_0402_5% 2 2 <22> WW_LED# 1 1 R1140 <14,22> WWAN_TRANSMIT_OFF# +3VS Q13A TR 2N7002DW-7-F 2N SOT-363 1 HDD active LED D 1 2 2 4 2 1 BT_LED <26> BT_LED Q13B TR 2N7002DW-7-F 2N SOT-363 5 4 1 3 2 WHITE YELLOW HT-297UY5/BP5_YELLOW-WHITE D7 AMBER WL/BT_LED# 0_0402_5% 2 R1135 255_0402_1% R1134 255_0402_1% R1136 1K_0402_5% R1132 1 3 +3VS WL_LED# <22> WL_LED# 1 1 +3VS white HDD_HALTLED# Q12A BT_LED 6 TR 2N7002DW-7-F 2N SOT-363 R1138 1 2 100K_0402_5% <25> CAPS_LED# C 9/1 Del Q58 2 1 R1139 10K_0402_5% SATA_LED# <11> SATA_LED# Q15B TR 2N7002DW-7-F 2N SOT-363 5 <28> CAPS_LOCK_KBC 4 1 @ 12/04, HP R1137 0_0402_5% 1 2 3 HDD_HALTLED <11> HDD_HALTLED 2 C 1 +3VS APP_BUTTON_1_LED# R1142 1M_0402_5% 2 470_0402_5% 3 2 R1141 6 +3VS 1 1 Q14A CH751H-40_SC76 APP_BUTTON_1 TR 2N7002DW-7-F 2N SOT-363 2 1 WL_BLUE_BTN <28> APP_BUTTON_1 <28> +3VS APP_BUTTON_2 <28> APP_BUTTON_2_LED# 2 R1143 C687 R1144 1M_0402_5% 470_0402_5% 0.1U_0402_16V4Z D9 6 2 1 2 3 1 B 2 1 WL_BLUE_BTN WL/BT_LED# APP_BUTTON_1 APP_BUTTON_1_LED# APP_BUTTON_2 APP_BUTTON_2_LED# C685 1U_0402_6.3V6K 2 ACES_85201-1005N CONN@ C686 0.22U_0402_10V4Z 1 1 2 JLED1 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 GND 12 GND Q14B TR 2N7002DW-7-F 2N SOT-363 5 1 Q16A CH751H-40_SC76 APP_BUTTON_2 TR 2N7002DW-7-F 2N SOT-363 2 1 C688 1U_0402_6.3V6K 2 1 2 C689 0.22U_0402_10V4Z A Q16B TR 2N7002DW-7-F 2N SOT-363 5 4 B D8 2 4 To LED small board A 1 Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. LEDS & LID Size Document Number Custom LA-6161P Date: R ev 0.5 Sheet Tuesday, May 18, 2010 1 20 of 41 5 4 3 2 1 +3V_LAN +3VS LA N _DI R 1148 10K_0402_5% 1 1 2 3.6K_0402_5% 2 1 1K_0402_5% +3V_LAN LAN_ACTIVITY# R 1165 1 C4 80 0.1U_0402_16V4Z 1 2 LANLED_A CT# 300_0603_5% S D 2 CLK_PCIE_LAN_REQ1# R 1150 2 @ 2 @ R2 58 10K_0402_5% RJ45_MIDI3+ 7 RJ45_MIDI1- 6 PR2- RJ45_MIDI2- 5 PR3- RJ45_MIDI2+ 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 PR1- RJ45_MIDI0+ 1 PR1+ 9 Green LED+ 10 Green LED- 15 HSIP <12> PCIE_PTX_C_DRX_N6 16 HSIN <14> CLK_PCIE_LAN <14> CLK_PCIE_LAN# CLK_PCIE_LAN_REQ1# <4,14,22,27> PLT_RST# R 1026 1 2 2.49K_0402_1% <13,22> PCIE_WAKE# <14> LA N_DIS# L AN_DIS# LAN_X1 LAN_X2 REFCLK_P REFCLK_N 25 CLKREQB 27 PERSTB 46 RSET 26 28 LANWAKEB ISOLATEB 41 42 LA N _DI LANLINK _STATUS# L AN_CS LED0 38 LAN_ACTIVITY# MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 2 3 5 6 8 9 11 12 LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- RTL8111DL FB12 4 SROUT12 48 EVDD12 DVDD12 DVDD12 DVDD12 AVDD12 19 30 36 13 10 AVDD12 39 CKTAL1 CKTAL2 +3V_LAN 1 R 1028 0_0402_5% 2 2 R 1027 1K_0402_5% @ R 1492 CB _ IN# 1 0_0402_5% 2 reserve for switch WLAN and on board LAN, Compal SI 1/19 C TRL15/VDD33 1 L AN_DIS# @ R 1030 0_0402_5% GPO NC VDDSR VDDSR 44 45 7 14 31 47 GND GND GND GND VDD33 VDD33 29 37 AVDD33 AVDD33 ENSR 1 40 43 22 2 R 1029 15K_0402_5% 23 24 EGND 1 CB _ IN# 2 1 SHLD1 CB _ IN# <14> C 719 @ 0.1U_0402_10V6K D 14 SANTA_130452-3_13P-T 300_0603_5% LANLINK_STATUS# <14> LANLED_A CT# LANLED_LINK# @ D43 PACDN042_SOT23~D +LAN_VDD12 VCTRL12 For ESD Close to Pin45,44 2 1 C TRL15/VDD33 U 56 R 1446 0_0805_5% for internal regular +3V_LAN C 10/100 and Giga Transformer +3V_LAN +EVDD12 +LAN_VDD12 1 +3VS 17 18 33 34 35 32 13 PR4+ 2 <12> PCIE_PTX_C_DRX_P6 LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS 3 HSON LANLED_LINK# 2 15 1 HSOP 21 LANLINK _STATUS# SHLD1 DETECT PIN1 PR4- 1 20 1 0.1U_0402_16V7K PCIE_RXN6_LAN +3V_LAN 1 R 1166 1 C 1042 C 1277 1 2 1 2 0.01U_0402_16V7K 1 2 0.01U_0402_16V7K 1 2 0.01U_0402_16V7K 1 2 0.01U_0402_16V7K 2 1 0.1U_0402_16V7K PCIE_RX P6_LAN C4 81 2 C 1248 C4 79 2 C 1247 0.1U_0402_25V6 <12> PCIE_PRX_DTX_P6 <12> PCIE_PRX_DTX_N6 2 1 U57 22U_0805_6.3V6M Place Close to Chip C C4 82 0.1U_0402_16V4Z Yellow LED- 8 +3V_LAN 1 0_0402_5% 12 RJ45_MIDI3- D 2N7002_SOT23-3 Q60 Yellow LED+ C 1291 C 1292 RTL8111DL-VB-GR_LQFP48_7X7 1 2 3 TCT1 TD1+ TD1- MCT1 MX1+ MX1- 24 23 22 C 1041 2 1 1000P_0402_50V7K RJ45_MIDI3RJ45_MIDI3+ R8 22 1 2 75_0402_1% LAN_MDI3LAN_MDI3+ 4 5 6 TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 C 1039 2 1 1000P_0402_50V7K RJ45_MIDI2RJ45_MIDI2+ R8 21 1 2 75_0402_1% LAN_MDI2LAN_MDI2+ 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 C 1085 2 1 1000P_0402_50V7K RJ45_MIDI1RJ45_MIDI1+ R9 23 1 2 75_0402_1% LAN_MDI1LAN_MDI1+ 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 C 1083 2 1 1000P_0402_50V7K RJ45_MIDI0RJ45_MIDI0+ R9 22 1 2 75_0402_1% LAN_MDI0LAN_MDI0+ change to 22U by realtek request RJ 45 _GND 2 2 3 R 1024 L AN_CS @ R 1025 11 2 1 +3V_LAN G <14> CLK_PCIE_LAN_REQ# 10K_0402_5% J RJ 45 2 2 1 R 1147 R 1145 10K_0402_5% 10K_0402_5% R 1445 LAN Conn. +3V_LAN 1 +3VS 2 C 1045 1000P_1808_3KV7K SUPERWORLD_SWG150401 Y4 LAN_X2 Swap the signal 0<-->3, 1<-->2 for layout routing, Compal SI 1/14 1 2 1 2 1 <13,23,28,29,30,32,34,35> SLP_S3# 5 4 1 2 R 1146 47K_0402_5% C 1279 0.1U_0402_16V4Z 1 2 C 1278 0.1U_0402_16V4Z 1 2 C 1286 0.1U_0402_16V4Z 2 C 1285 0.1U_0402_16V4Z 1 C 1284 0.1U_0402_16V4Z C 1283 0.1U_0402_16V4Z C 1282 0.1U_0402_16V4Z 1 2 2 1 R 1149 2 1 47K_0402_5% Q27B 2N7002DW-7-F_SOT363-6 1 Note 1: The Trace length between L1 and 8111DL's Pin 1 must be within 0.5 cm. C262 and C263 to L1 must be within 0.5cm. Refer to Layout guide for more detail. 5 2 2 1 R 817 1 2 0_0603_5% +EVDD12 A 1 C 1290 1U_0402_6.3V4Z C 1289 1U_0402_6.3V4Z 1 370mA The +3V_LAN Rising time (10%~90%) need >1mS and <100mS R8 19 0_0603_5% 2 L42 1 2 4.7UH_1008HC-472EJFS-A_5%_1008 A C 1288 0.1U_0402_16V4Z VCTRL12 2 1 Close to Pin48 +EVDD12 C 1287 22U_0805_6.3V6M Close to Pin19 3 Q 59 SI2301BDS_SOT23 D 1 2 +3V_LAN Close to Pin1,37,29 +LAN_VDD12 Q27A 2N7002DW-7-F_SOT363-6 2 <28,31,32,38> ADP_PRES G 2 Close to Pin40 for 8111DL S Close to Pin10,13,30,36 +3V_LAN +3VALW Close to Pin39 for 8111DL 2 2 6 2 B C 1249 27P_0402_50V8J 3 1 C 1281 0.1U_0402_16V4Z C 1276 27P_0402_50V8J 2 1 1 C 1280 0.1U_0402_16V4Z B 1 2 25MHZ_20PF_7A25000012 1 LAN_X1 1 2nd Source : HDT BA30-A66 1G LAN Compal Secret Data Security Classification +LAN_VDD12 Issued Date 2007/08/28 Deciphered Date 2006/10/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title Compal Electronics, Inc. GLAN RTL8111DL Size D ocument Number Cus tom LA -6161P Dat e: Rev 0.5 Sheet Tuesday, May 18, 2010 1 21 of 41 A B C D +3VS +1.5VS E SPI_HOLD#_0 <27> SPI_HOLD#_0 SPI_CLK_JP 1 2 2 1 2 C739 1 2 10U_0805_6.3V6M C738 2 0011101b 0.1U_0402_16V4Z 1 8 9 <14> ACCEL_INT# 12 13 14 <9,10,12> SMB_DATA_S3 <9,10,12> SMB_CLK_S3 +3VS R1176 2 1 10K_0402_5% 7 2 4 5 10 SDO SDA / SDI / SDO SCL / SPC RSVD CS RSVD 3 11 INT 1 INT 2 PCIE_WAKE# <12> CLK_PCIE_MCARD# <12> CLK_PCIE_MCARD 1 @ R1505 2 0_0402_5% delete port 80 03/29 R1167 1 R1168 1 <12> PCIE_PRX_DTX_N4 <12> PCIE_PRX_DTX_P4 2 0_0402_5% PCIE_C_RXN4 2 0_0402_5% PCIE_C_RXP4 <12> PCIE_PTX_C_DRX_N4 <12> PCIE_PTX_C_DRX_P4 +3VS +3VS HP302DLTR8_LGA14_3X5 L 2 SPI_SO_JP <27> SPI_SO_JP 2 110K_0402_5% 2 +3VALW <12> CLKREQ_WLAN# +3VL GND GND GND GND SPI_CS0#_JP <27> SPI_CS0#_JP 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% SPI_HOLD#_MB SPI_CLK_DB SPI_SI_DB SPI_CS0#_DB SPI_SO_R0_DB 02/23 1 +3VS JWLAN1 R1476 LIS302DL VDD_IO VDD 1 <13,21> PCIE_WAKE# U14 1 6 +3VS SPI_SI_JP <27> SPI_SI_JP 1 @ R1498 1 @ R1499 1 @ R1500 1 @ R1501 1 @ R1502 WWLAN/WiMax Mini-Express Card half size +3VS 1 4.7U_0805_10V4Z C731 2 1 0.1U_0402_16V4Z C730 2 0.01U_0402_16V7K C729 ACCELEROMETER 1 4.7U_0805_10V4Z C728 1 0.1U_0402_16V4Z C727 0.01U_0402_16V7K C726 <27> SPI_CLK_JP Must be placed in the center of the system. <28> SPI_RECOVERY 02/23 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 54 +1.5VS SPI_SO_R0_DB SPI_CS0#_DB SPI_SI_DB SPI_CLK_DB SPI_HOLD#_MB 02/23 XMIT_D_OFF# PLT_RST# PLT_RST# <4,14,21,27> USB20_N6 <14> USB20_P6 <14> WL_LED# 11/21 HP 12/04, HP WL_LED# <20> 2 FOX_AS0B226-S40N-7F CONN@ XMIT_D_OFF# 2 D12 1 CH751H-40_SC76 WLAN_TRANSMIT_OFF# <14> T131PAD 53 GND1 1 2 <14,20> WWAN_TRANSMIT_OFF# 2 3 4.7U_0805_10V4Z C737 0.1U_0402_16V4Z C736 3 UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP +3VS R1080 2 1 0_0805_5% WWAN power control by F10. 11/09 R1172 10K_0402_5% M_WXMIT_OFF# Compal,SI 1/4 U13 1 WWAN_DET# <14> 2 2 R1173 10K_0402_5% @ WW_LED# 1 3 USB20_N9 <14> USB20_P9 <14> JSIM1 WW_LED# <20> 4 5 6 7 UIM_VPP UIM_DATA 12/04, HP CONN@ MOLEX_67910-5700 4 +3V_WWAN 04/19 Q77 SI2305DS-T1-E3_SOT23-3 54 GND2 J3 SHORT PADS D14 1 2 GND VPP I/O DET M_WXMIT_OFF# 6 CH1 CH4 Vn 5 Vp +3V_WWAN D13 @ S DIO(BR) NUP4301MR6T1 TSOP-6 @ DAN217T146_SC59-3 3 UIM_PWR 1 1 VCC UIM_RST 2 2 RST UIM_CLK 3 CLK 1 GND GND 2 8 9 @ 1 CH751H-40_SC76 +3V_WWAN 4 CH2 CH3 1 2 1 C742 R1174 0_0603_5% 1 2 1 2 R1175 0_0603_5% 2 for RF 2 0.1U_0402_16V4Z +3V_WWAN <12> PCIE_PTX_C_DRX_N7 <12> PCIE_PTX_C_DRX_P7 2 2 220K_0402_1% 4.7U_0805_10V4Z 2 0_0402_5% PCIE_C_RXN7 2 0_0402_5% PCIE_C_RXP7 R1468 1 R1469 1 <12> PCIE_PRX_DTX_N7 <12> PCIE_PRX_DTX_P7 1000P_0402_50V7K 1 R1079 18P_0402_50V8J T129PAD T130PAD <28> MC1_DISABLE C741 11/21 HP 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 10K_0402_5% 2 1 C740 <12> CLK_PCIE_MCARD2# <12> CLK_PCIE_MCARD2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 C933 1 2 +3VALW <12> CLKREQ_WWAN# 1 10K_0402_5% 2 R1077 2 R1177 47K_0402_5% R207 2 1 1 12/05 HP 2 @ 1 Place C933 between R1077.1 and R1079.2 for limit inrush current. 2 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 @ 1 L 1 JWWAN1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 @ 1 0.01U_0402_16V7K C735 +3V_WWAN 1 39P_0402_50V8J C734 Full size 1 +3V_WWAN +3VALW 10P_0402_25V8J C733 Mini-Express Card--WWAN +3V_WWAN Note2 10P_0402_25V8J C732 Close to JP14 Add to prevent leakage issue. 4 CONN@ TAITW_PMPAT6-06GLBS7N14N0 UIM_PWR Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. WLAN&WWAN Mini-Card/Accelerometer Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet E 22 of 41 A B C D +AVDD_CODEC +VDDA_CODEC R1442 2 MUTE_LED_CNTL R1349 1 MIC_EXTL MIC_EXTR +VREFOUT_EXTMIC HP1_PORT_B_L HP1_PORT_B_R 31 32 HP_OUTL HP_OUTR PORT_C_L PORT_C_R VREFOUT_C 19 20 24 MIC_INL MIC_INR +VREFOUT_INTMIC 2 0_0402_5% R1350 1 +3VS DMIC_CLK/GPIO1 DMIC0/GPIO2 46 DMIC1/GPIO0/SPDIF_OUT_1 SPKR_PORT_D_L+ SPKR_PORT_D_L- 40 41 SPKL+ SPKL- 48 SPDIF_OUT_0 SPKR_PORT_D_RSPKR_PORT_D_R+ 43 44 SPKRSPKR+ 2 10K_0402_5% 47 PORT_E_L PORT_E_R 15 16 PORT_F_L PORT_F_R 17 18 PC_BEEP 12 MONO_OUT 25 EAPD EC_MUTE# 1 2 D15 CH751H-40PT_SOD323-2 delete D16, Compal, SI 1/5 <28> EC_MUTE# 2 C892 4.7U_0603_6.3V6M 1 35 CAP- 36 CAP+ 7 33 30 26 1 R1366 2 10K_0402_5% +AVDD_CODEC 42 MUTE_LED_CNTL <28> MUTE_LED_CNTL 28 29 23 2 1 C908 0.01U_0402_16V7K 2 4 2 HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_or_F 49 AVSS AVSS AVSS CAP2 VREFFILT PVSS V- DAP VREG +5VALW 2 0.1U_0402_16V4Z 1 2 3 <13,21,28,29,30,32,34,35> SLP_S3# (4.75V) 300mA GND 1 BYP R1443 @ 0_0402_5% 2 MIC_IN_L MIC_IN_R 2 2.2U_0603_6.3V4Z 2 2.2U_0603_6.3V4Z C904 220P_0402_50V7K 2 Reserve CODEC LDO for Codec. 3 2 1 1 0.1U_0402_16V4Z 22 21 34 37 2 1 1 2 MONO_IN MIC_IN_L <24> Int MIC MIC_IN_R <24> +VREFOUT_INTMIC <24> 2 1 R1352 1 2 92HD80 port define Port A Ext MIC +AVDD_CODEC 100K_0402_5%C894 1 2 2 0.1U_0402_16V4Z 2 5 SB_SPKR 1 C1294 R1361 2.49K_0402_1% 2.2U_0805_16V4Z C1295 R1364 1 2 R1363 10K_0402_5% SENSEA 39.2K_0402_1% Head phone Port C Int MIC Port D SPKR Port E X Port F X DM0 Digital MIC C900 1 2 1000P_0402_50V7K C901 1 2 1000P_0402_50V7K C902 1 2 1000P_0402_50V7K C903 1 2 1000P_0402_50V7K R1355 1 2 0_0603_5% R1356 1 2 0_0603_5% R1357 1 2 0_0603_5% R1358 1 2 0_0603_5% C743 1000P_0402_50V7K_X7R 5 1 2 GNDA <24> 2 Q84B 2N7002DW-7-F_SOT363-6 Port B SB_SPKR <11> +AVDD_CODEC +AVDD_CODEC GND1 GND2 E-T_3806K-F04N-03R_4P-T CONN@ R1351 10K_0402_5% MONO_INR C893 2 1 2 3 4 C905 220P_0402_50V7K 1 1 2 C906 C907 220P_0402_50V7K 220P_0402_50V7K 2 2 HP Jack Internal SPKR <24> MIC_SENSE 1 1 1 C890 1 C891 1 3 2 C884 10U_0805_10V4Z HP_OUTL <24> HP_OUTR <24> 4 G9191-475T1U_SOT23-5 CODEC POWER 1 5 OUT SHDN Ext MIC +VREFOUT_EXTMIC <24> 2 3 IN 5 6 MIC1 <24> 1 1 U58 1 C1293 +VDDA_CODEC MIC1 2 2.2U_0603_6.3V4Z 2 2.2U_0603_6.3V4Z DVSS 92HD80B1X5NLGXYD38_QFN48_7X7 W=40Mil C888 1 C889 1 2 HDA_RST# R1345 2 @ C886 1 1 2 3 4 1 HDA_SYNC 11 JSPK1 SPKL+ SPKLSPKR+ SPKR- 3 10 HDA_RST#_CODEC 2 1 D38 PJSOT05C_SOT23 4 HD A_SYNC_CODEC 2 Q72B 2N7002DW-7-F_SOT363-6 HDA_SDO 2 SENSEA 1 100K_0402_5% +AVDD_CODEC 1000P_0402_50V7K 2 2 2 R1360 1 4.7K_0402_5% +3VS_DVDD HDA_SDI 5 13 14 1 3 <11> HDA_RST#_CODEC HDA_BITCLK 8 39 45 1 4 <11> HDA_SYNC_CODEC SENSE_A SENSE_B 1 2 <11> HDA_SDOUT_CODEC 6 PVDD PVDD 2 1 R1346 1 2 HDA_SDIN0_CODEC 33_0402_5% HDA_SDOUT_CODEC <11> HDA_SDIN0 DVDD_IO 2 27 38 D37 PJSOT05C_SOT23 R1354 10K_0402_5% <11> HDA_BIT_CLK_CODEC 3 AVDD AVDD 2 HDA_BIT_CLK_CODEC DVDD 1 @ R1342 2 1 47_0402_5% DVDD_CORE 9 C883 1U_0402_6.3V6K 1 10U_0805_10V4Z 1 2 0.1U_0402_16V4Z C895 C881 C882 0.1U_0402_16V4Z U49 1 C879 1U_0402_6.3V6K for ESD 1 2 @ C885 2 1 33P_0402_50V8K 1 0_0805_5% C899 1U_0603_10V6K 2 C878 0.1U_0402_16V4Z 1 1 R1339 2 C898 10U_0805_10V4Z 1 2 2 C897 10U_0805_10V4Z C880 0.1U_0402_16V4Z 2 0_0603_5% +5VS @ C896 4.7U_0603_6.3V6M 1 +3VS_HDA R1340 1 Reserve CODEC LDO for Codec. +AVDD_CODEC C876 0.1U_0402_16V4Z +3VS 1 0_0805_5% 1 +3VS_DVDD R1334 BLM18BD601SN1D_0603 2 1 C877 1U_0402_6.3V6K +3VS E install for ESD request, Compal SI 1/19 GND 0.1U_0402_16V4Z 3 GNDA R1362 HP_DET# 2 1 EC_MUTE# A 2 Q84A @ 4 <24> HP_DET 5 5 6 @ HP_DET 2N7002DW-7-F_SOT363-6 2 1 1 R1365 10K_0402_5% 1 2 Q71A 2N7002DW-7-F_SOT363-6 +AVDD_CODEC 6 2 @ 1 20K_0402_1% HP_OUTR Q71B 2N7002DW-7-F_SOT363-6 6 4 2N7002DW-7-F_SOT363-6 Q72A 2 R1359 10K_0402_5% @ Q70B 2N7002DW-7-F_SOT363-6 3 4 1 +5VALW Q70A 2N7002DW-7-F_SOT363-6 1 6 HP_OUTL 3 HP de pop circuit 2 4 @ Compal Secret Data Security Classification 2007/08/28 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C D Title Codec_IDT92HD80 Size Document Number Custom Date: R ev 0.5 LA-6161P Sheet Tuesday, May 18, 2010 E 23 of 41 C D E JUSB23 <23> HP_DET INT_MIC_1_2 INT_MIC_2_2 To CODE-ext MIC Bias 2 C783 1U_0603_10V6K SLP_S4 <30> HP_OUTR HP_OUTL 2.2K_0402_5% R1201 1 USB20_N0 <14> USB20_P0 <14> SLP_S4 1 2 U17 1 IN+ O 3 Place close to U18 HP_OUTR <23> HP_OUTL <23> R1200 560K_0402_5% 1 5 +3VS USB20_N0 USB20_P0 +AVDD_CODEC 2 32 <23> +VREFOUT_EXTMIC 1 31 USB20_N5 <14> USB20_P5 <14> P EXT_MIC HP_DET USB20_N5 USB20_P5 IN- R1202 D19 1 47K_0402_5% change from 120K to 47K, HP SI 1/28 2 R1203 10K_0402_5% EXT_MIC +CODEC_REF 1 USB I/O connx2 , Aduio JACK Card reader transfer conn MIC_SENSE <23> LMV331IDCKRG4_SC70-5~D CHN202UPT_SC-70 +AVDD_CODEC ACES_88242-3001_30P CONN@ 4 2 1 R1199 100K_0402_5% 1 2 +5VALW +5VALW 1 USB20_N3 USB20_P3 <14> USB20_N3 <14> USB20_P3 +5VALW +5VALW 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 3 USB20_N1 USB20_P1 <14> USB20_N1 <14> USB20_P1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 +5VALW +5VALW G B 2 A 1 R1204 10K_0402_5% 2 220P_0402_25V8J 2 0.1U_0402_16V4ZC786 4.7U_0805_10V4Z C785 2 1 1 2 C784 1 2 2 1 C787 2 15P_0402_50V8K EXT_MICL_3 R1205 1 AMP. FOR EXTERNAL MICROPHONE 2 100K_0402_5% +CODEC_REF 1 2 10K_0402_5% OUT - + OUT - G 2 P 4 6 P 4 3 MIC1 7 MIC1 <23> U18B TLV2464_TSSOP14 11 2 C789 + 11 EXT_MIC 5 G C788 2 L39 HLC0603CSCCR11JT_0603 1 EXT_MIC_1 1 2 1 0.47U_0402_6.3V6K_X5R R1206 100P_0402_50V8J +AVDD_CODEC 1 To CODE-ext MIC input 1 U18A TLV2464_TSSOP14 C790 68P_0402_50V8J 2 3 3 @ 1 C791 1 C792 R1210 3K_0402_5% 2 1 1 C798 3K_0402_5% @ 1 @ 2 +AVDD_CODEC C802 1U_0603_16V7_X7R OUT - 2 1 3K_0402_5% @ @ 14 U18D TLV2464_TSSOP14 2 1 2 1 1 C797 3K_0402_5% @ C799 1U_0603_16V6K_X5R L40 R1213 HLC0603CSCCR10JT_0603 10K_0402_5% 2 INT_MIC_2_31 2 1 2 0.068U_0603_16V7K 1 C800 68P_0402_50V8J C794 4 9 + - 2 8 OUT TLV2464_TSSOP14 U18C 4 <23> MIC_IN_R 2 <23> MIC_IN_L 2 Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 10 0.1U_0402_16V4Z R1212 1 P C793 R1211 2 G C796 P 2 0.1U_0402_16V4Z 4 13 + INT_MIC_2_2 100P_0402_50V8J 1 +AVDD_CODEC 11 1 12 G 2 L41 HLC0603CSCCR10JT_0603 R1216 2 INT_MIC_1_31 2 1 2 0.068U_0603_16V7K 10K_0402_5% 1 C801 68P_0402_50V8J 1 11 C795 +AVDD_CODEC 100P_0402_50V8J 1 R1215 2 100K_0402_5% +CODEC_REF +AVDD_CODEC 2 3K_0402_5% @ AMP. FOR INTERNAL MICROPHONE 2 100K_0402_5% +CODEC_REF INT_MIC_2_2 INT_MIC_1_2 R1214 1 1 1 R1209 3K_0402_5% INT_MIC_2_4 1 R1207 2 100P_0402_50V8J R1208 2 2 INT_MIC_1_4 4 2 100P_0402_50V8J @ <23> +VREFOUT_INTMIC B C D Title Compal Electronics, Inc. AMP & Audio Jack Size Document Number R ev 0.5 LA-6161P Date: Sheet Tuesday, May 18, 2010 E 24 of 41 For EMI INT_KBD CONN. KSO11 @ C620 1 2 100P_0402_50V8J KSO0 @ C656 1 2 100P_0402_50V8J KSO2 @ C624 1 2 100P_0402_50V8J KSO5 @ C621 1 2 100P_0402_50V8J KSI_D_14 @ C622 1 2 100P_0402_50V8J KSI_D_8 @ C625 1 2 100P_0402_50V8J KSI_D_12 @ C626 1 2 100P_0402_50V8J KSI_D_10 @ C627 1 2 100P_0402_50V8J KSI_D_0 @ C630 1 2 100P_0402_50V8J KSI_D_4 @ C629 1 2 100P_0402_50V8J KSI_D_2 @ C631 1 2 100P_0402_50V8J KSI_D_1 @ C632 1 2 100P_0402_50V8J KSI_D_3 @ C633 1 2 100P_0402_50V8J KSO3 @ C634 1 2 100P_0402_50V8J KSO8 @ C641 1 2 100P_0402_50V8J KSO4 @ C637 1 2 100P_0402_50V8J KSO7 @ C657 1 2 100P_0402_50V8J KSO6 @ C638 1 2 100P_0402_50V8J KSO10 @ C639 1 2 100P_0402_50V8J KSO1 @ C640 1 2 100P_0402_50V8J KSI_D_5 @ C660 1 2 100P_0402_50V8J KSI_D_6 @ C642 1 2 100P_0402_50V8J KSI7 @ C659 1 2 100P_0402_50V8J KSI_D_13 @ C654 1 2 100P_0402_50V8J KSI_D_11 @ C744 1 2 100P_0402_50V8J KSI_D_9 @ C745 1 2 100P_0402_50V8J KSO9 @ C724 1 2 100P_0402_50V8J JKB1 34 33 <28> KSO[0..11] KSO11 KSO0 KSO2 KSO5 KSI_D_14 KSI_D_8 KSI_D_12 KSI_D_10 KSI_D_0 KSI_D_4 KSI_D_2 KSI_D_1 KSI_D_3 KSO3 KSO8 +3VS KSO4 KSO7 KSO6 KSO10 KSO1 1 KSI_D_5 C803 KSI_D_6 0.1U_0402_16V4Z KSI7 2 KSI_D_13 KSI_D_11 KSI_D_9 KSO9 2 470_0402_5% 20mil+3VS R1217 1 KSO[0..11] KSI[0..7] <28> KSI[0..7] <20> CAPS_LED# 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KB LED power GND2 GND1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HRS_FH28-60(30)SB-1SH(86) CONN@ Pin 1 Pin1 reserve , so net name is reserve for Fossil down contact D20 D21 2 KSI0 1 3 KSI1 1 LID_SW# <18,28> STB_LED <28> 1 ACES_85201-06051CONN@ C1334 0.1U_0402_16V4Z 2 DAP202U_SOT323-3 KSI6 1 3 Compal SI 1/19 KSI_D_14 T/P BOARD. +5VS ON/OFFBTN_KBC# JTPB1 ON/OFFBTN_KBC# <28> +3VALW C805 1U_0603_10V4Z 1 @ R1219 @ D28 1 add 0.1U for EMI request, KSI_D_13 DAP202U_SOT323-3 1 2 3 DAP202U_SOT323-3 D26 2 KSI_D_6 2 1 2 3 4 <28> TP_CLK <28> TP_DATA 2 100K_0402_5% 5 6 ON/OFFBTN# <13,28> CH751H-40_SC76 ACES_87151-04051_4P CONN@ LID_SW# STB_LED KSI5 1 KSI_D_12 2 AMBER_BATLED# <28> AQUAWHITE_BATLED# <11,28> 3 +5VS 1 C804 0.1U_0402_16V4Z 2 D27 PACDN042Y3R_SOT23-3 12/09 HP 1 JPWR1 1 1 2 2 3 3 4 4 5 5 6 6 7 GND 8 GND KSI_D_11 3 Power BTN/LED and Lid switch BD +3VL KSI_D_3 3 DAP202U_SOT323-3 D24 2 KSI_D_5 KSI_D_10 R1218 2 1 100K_0402_5% +3VL KSI4 1 2 DAP202U_SOT323-3 D22 2 KSI_D_4 KSI_D_9 DAP202U_SOT323-3 D25 2 KSI_D_2 3 KSI3 1 KSI_D_8 DAP202U_SOT323-3 D23 2 KSI_D_1 3 KSI2 1 KSI_D_0 Compal Secret Data Security Classification Issued Date 2009/08/03 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. MDC/KBD/ON_OFF/LID Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet 25 of 41 5 4 3 2 1 BT(SoftBreeze) Connector @ D29 +3VAUX_BT USB20_N8_R 4 VIN IO1 2 3 IO2 GND 1 USB20_P8_R JBT1 +3VAUX_BT 1 2 3 4 5 6 7 8 CM1293A-02SR_SOT143-4 D For ESD USB20_P8_R USB20_N8_R R1220 2 R1221 2 1 0_0402_5% 1 0_0402_5% USB20_P8 <14> USB20_N8 <14> BT_LED <20> D CONN@ ACES_87213-0800G_8P +3VALW +3VAUX_BT Q63 SI2301BDS_SOT23 D S 2 S 2 G 220K_0402_1% Q89 2N7002_SOT23-3 C815 1 <14> BT_OFF C D C814 2 R1223 1 1 2 2 0.1U_0402_16V4Z R1477 470_0402_5% 1 C1324 @ 2 3 1 1 2 1 2 G 0.1U_0402_10V6K R1222 10K_0402_5% 1 2.2U_0805_10V5R 3 C B B A A Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. USB & BT Connector Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet 1 26 of 41 5 4 3 2 1 D D +3VL C C +3VL_SPI PWR for RF BIOS ROM(4MB) 4MB SPI ROM @ C1323 1 0.1U_0402_16V4Z 1 C581 47P_0402_50V8J 25mA 2 20mils +3VL SPI ROM SCKET 20mils 1 R629 2 2 3.3K_0402_5% <28> SPI_CS0# <28> SPI_CLK <28> SPI_SI U35 8 VCC VSS SPI_WP# 3 W SPI_HOLD#_1 7 HOLD SPI_CS0# 1 S SPI_CLK 6 SPI_SI 5 4 C D Q SPI_SO_R0 1 2 R630 33_0402_5% 2 SPI_SO SPI_SO <28> MX25L3205DM2I-12G SPI_HOLD#_0 SPI_CLK_JP B SPI_SI_JP SPI_CS0#_JP SPI_SO_JP 4MB SPI ROM 1 R633 1 R634 1 R635 1 R636 1 R637 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% +3VL LPC Debug Port 2nd Source : WINBOND 32M W25Q32BVSSIG EON 32M EN25F32-100HIP SPI_HOLD#_1 SPI_CLK +3VL CLK_PCI_DB 8051_RECOVER# R628 1 2 100K_0402_5% 1 SPI_SI @ C655 39P_0402_50V8J SPI_CS0# B B+_DEBUG 2 JP31 SPI_SO_R0 CLK_PCI_DB <14> CLK_PCI_DB 20mils 1 R631 SPI_WP# 2 3.3K_0402_5% @ 1 R632 <11,28> <11,28> <4,14,21,22> <14,28> <11,28> <11,28> <11,28> <11,28> 2 0_0402_5% SIRQ 1 SPI_CLK LPC_LFRAME# SIRQ PLT_RST# PCI_SERR# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 <28> 8051TX <28> 8051RX <28> 8051_RECOVER# <33> DEBUG_KBCRST <22> SPI_CLK_JP <22> SPI_CS0#_JP <22> SPI_SI_JP <22> SPI_SO_JP <22> SPI_HOLD#_0 <28> SPI_CS1# R627 10_0402_5% 2 @ 05/10 Delete SPI Socket for MV. 1 @ C582 4.7P_0402_50V8C 8051_RECOVER# DEBUG_KBCRST SPI_CLK_JP SPI_CS0#_JP SPI_SI_JP SPI_SO_JP SPI_HOLD#_0 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved ACES_87216-2404_24P CONN@ A Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title A Compal Electronics, Inc. BIOS ROM/SW LPC DEBUG Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet 1 27 of 41 1 2 3 4 5 1 +3VL R 1238 KSI3 KSI2 KSI1 KSI0 1 @ 100K_0402_5% ROM_CS #0 1 C 832 C 831 0.1U_0402_16V4Z 2 1 C 833 2 1 C8 34 2 2 1 1 2 2 C8 35 2 0.1U_0402_16V4Z 1 1 1 1 KSI7 KSI6 KSI5 KSI4 <27> SPI_SI <11> KBC_SPI_SI_R <27> SPI_CS0# <11> KBC_SPI_CS0#_R <27> SPI_SO <11> KBC_SPI_SO 1 R 1245 1 R 1246 ROM_DATOUT 2 0_0402_5% ROM_CS #0 2 0_0402_5% 1 R 1247 ROM_DATIN 2 0_0402_5% <25> KSO[0..11] KSI0 T142 P AD KSI1 <25> K SI[0..7] KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 BIOS request. 11/20 Compal TP _CLK TP_DATA SP_CLK SP _DATA <25> TP_CLK <25> TP_DATA FLDATAOUT HSTDATAOUT/GPIO45 FLCS0# HSTCS0#/GPIO44 FLDATAIN HSTDATAIN/GPIO43 21 20 19 18 17 16 13 12 10 9 8 7 6 5 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12/GPIO00/KBRST KSO13/GPIO18 29 28 27 26 25 24 23 22 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 35 36 61 62 66 67 IMCLK IMDAT KCLK KDAT EMCLK EMDAT Keyboard/Mouse Interface B T141 P AD KS O0 KS O1 KS O2 KS O3 KS O4 KS O5 KS O6 KS O7 KS O8 KS O9 KS O10 KS O11 128 127 97 96 95 94 VCC1 VCC1 VCC1 VCC1 VCC1 R 1399 R 1400 R 1401 R 1402 SMSC_1098-NU_TQFP-128P 2 2 2 2 2 4.7U_0805_10V4Z U 21 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 1 C 836 0.1U_0402_16V4Z C 837 0.1U_0402_16V4Z A compal, SI 12/24 <13> P M_CLKRUN# <11,27> S I RQ <14> C LK_PCI_KBC <14> RUNS CI _EC# +5VS 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 CLK_PCI_KBC RUNS CI _EC# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 51 50 48 46 LAD[3] LAD[2] LAD[1] LAD[0] <11,27> LPC_LFRAME# <14> N PCI_RST# 52 53 LFRAME# LRESET# TP_DATA SP_CLK SP _DATA Compal, SI 1/18 107 79 80 81 83 APP_BUTTON_1_R GPIO07/PWM3 GPIO08/RXD GPIO09/TXD 85 86 87 P M_RSMRST# CRACK_BGA B D_ ID GPIO11/AB2A_DATA GPIO12/AB2A_CLK GPIO13/AB2B_DATA GPIO14/AB2B_CLK GPIO15/FAN_TACH1 GPIO16/FAN_TACH2 GPIO17/A20M 88 89 90 91 92 101 102 AB 2A_DATA R 1249 1 AB2A _CLK R 1250 1 R 1251 1 R 1252 1 GPIO20/PS2CLK GPIO21/PS2DAT GPIO24/KSO16 ADP_PRES[CKT#2]/GPIO27/WK_SE05 103 105 4 74 PWRBTN_OUT# AB1A_DATA AB1A_CLK 111 112 SMB_E C_DA1 SMB_E C_CK1 AB1B_DATA AB1B_CLK 109 110 AB 1B_DATA AB1B _CLK KBC1098-NU_VTQFP128_14X14 R 1275 2 0.1U_0402_16V4Z CAPS_LOCK_KB C_R R 1308 1 32K_CLK P GD _IN P W R_ GD 69 TEST 2 0_0402_5% 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 Compal SI 1/19 ON /OFFBTN# <13,25> R2 48 1 2 0_0402_5% R 1261 1 2 1K_0402_5% +3VL CPU_SV_ID_DET 02/23 8051TX R 1306 1 R 1268 1 2 0_0402_5% +3VL 2 2 0_0402_5% 0.1U_0402_10V6K 2@ 100K_0402_5% R 1259 1 2@ 100K_0402_5% C STB_LED STB_LED <25> Compal 12/24 +3VL @ KB RST# LI D_SW# <18,25> WL_BLUE_BTN WL_BLUE_BTN <20> R 1265 1 2 10K_0402_5% V CC1_ PWRGD R 1266 1 2 10K_0402_5% CRACK_BGA R 1269 1 2 10K_0402_5% 1 2 10K_0402_5% K B C_PWR_ON R 1274 1 2 10K_0402_5% B D_ ID 2 0_0402_5% 1 R 1258 1 CPU Type Detect : High-->SV , Low-->LV L S P I_RECOVERY <22> AMBER_BATLED# <25> 8051TX <27> 8051RX <27> 2 100K_0402_5% +3VL AC_ADP_PRES <31,32> 2 300_0402_5% ADP_A_ID <38> 1 C 1303 APP_BUTTON_2 <20> CAPS_LOCK_KBC <20> ADP_EN <38> P G D_IN <13,37> P W R _GD <29> V CC1 _PWRGD <33,38> O CP <38> 2 0_0402_5% 8051TX R 1264 1 LI D_SW# WL_BLUE_BTN_R APP_BUTTON_2 2 0_0402_5% CAPS_LOCK _KBC 2 0_0402_5% S P I _RECOVERY_R 1 @ R 1503 A DC2 R 1307 1 R 1257 1 1 R 1272 @ R 1485 0_0402_5% 2 2200P_0402_25V7K 2 1 C8 45 ADC 2200P_0402_25V7K 2 1 C8 46 A DC1 2200P_0402_25V7K 2 1 C8 47 A DC2 @ 1 2 SPI_CLK @ +3VL R P11 1 2 @ P GD _IN R 1277 1 2 10K_0402_5% P M_RSMRST# R 1278 1 2 10K_0402_5% 4.7K_0804_8P4R_5% SMB_E C_CK1 1 8 SMB_E C_DA1 2 7 AB1B _CLK 3 6 AB 1B_DATA 4 5 D 2 Compal Secret Data Security Classification 1U_0603_10V4Z Issued Date 2009/08/03 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 0.1U_0402_16V4Z APP_BUTTON_2 @ C 1331 2 2 2 0.1U_0402_16V4Z 1 SMB_EC_DA1 <31> SMB_EC_CK1 <31> 0_0402_5% 1 C8 39 @ 4.7P_0402_50V8C @ 0_0402_5% 2 1 2 1 2 C8 49 1 C 1335 2 0_0402_5% ADP_PRES <21,31,32,38> 1 1 2 1 @ LI D_SW# R 1253 1 C8 42 1 C 1329 APP_BUTTON_1 @ C 1330 B CAP_DAT <12> CAP_CLK <12> CELLS <32> EC_MUTE# <23> ADP_DET# <38> BAT_ID# <31> GATEA20 <14> 4.7P_0402_50V8C C8 48 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% C8 41 R 1279 1 @ 2 2 2 2 CAP_CLK R 1276 0_0402_5% ROM_CLK WL_BLUE_BTN PM_RSMRST# <13> CRACK_BGA <8,16> APP_BUTTON_2_R 1 +V CC0 for ESD APP_BUTTON_1 <20> SLP_S3# <13,21,23,29,30,32,34,35> 8051_RECOVER# <27> 4.7P_0402_50V8C 4.7P_0402_50V8C 10_0402_5% C8 40 R 1255 @ 2 0_0402_5% APP_BUTTON_1 ON/OFFBTN_KBC# <25> add 0.1U for EMI request, R 1486 D R 1290 1 12/10 HP +R TCVCC CLK_PCI_KBC 1 100K_0402_5% 1 100K_0402_5% 1 100K_0402_5% 2 2 2 KB_RST# <14> FAN_PWM <4> BAT_PWM_OUT <32> CHG CTRL <32> CPU_SV_ID_DET SLP_S3# AVSS 2 ROM_CS 1# 0_0402_5% 300_0402_5% 2 A DC1 2 ADC 300_0402_5% 2 73 41 42 65 64 63 40 AC[CKT#2]/GPIO23 ADC2/GPIO40 Q/GPIO33 GPIO34 GPIO35 AVCC VSS VSS VSS VSS VSS VSS VSS O CP_A_IN 1 R 1267 R 1270 1 1 R 1273 Alarm [CKT#2]/GPIO36 HSTCLK/GPIO41 FLCLK GPIO39 HSTCS1#/GPIO42 FLCS1# GPIO38 GPIO37 ADC1/GPIO46 ADC_TO_PWM_IN KB RST# D31 1 CH751H-40PT_SOD323-2 R 1262 AGND <32> PMC <38> O CP_A_IN 2 ROM_CLK 0_0402_5% VCC0 1 2 3 30 31 32 33 34 43 44 R 1489 R 1490 R 1491 K B C_PWR_ON <33> AQUAWHITE_BATLED# <11,25> 108 59 75 60 78 77 38 116 113 115 114 CFETB/GPIO10 BAT_LED# PWR_LED#/8051TX FDD_LED#/8051RX WL_BLUE_BTN APP_BUTTON_1 APP_BUTTON_2 MUTE_LED_CNTL <23> 45 2 <11> KBC_SPI_CS1#_R <27> SPI_CS1# <22> MC1_DISABLE 1 R 1263 68 11 37 47 56 104 82 117 1 BAT_ALARM XTAL1 XTAL2 72 4 32.768KHZ 1TJS125DJ4A420P IN NC NC 3 2 2 C8 44 1 <11> KBC_SPI_CLK_R <27> SPI_CLK 22P_0402_50V8J C8 43 22P_0402_50V8J Y5 OUT 1 + VCC0 T136 P AD 70 71 TEST PIN SUS_PWR_ACK <13> AC_PRESENT <13> MUTE_LE D_CNTL 2 0_0402_5% P C I_SERR# <14,27> MUTE_LED_CNTL_R R 1248 1 GPIO01 GPIO02 GPIO03 GPIO04/KSO14 GPIO05/KSO15 GPIO25 LPC Bus T143 123 122 121 120 118 GPIO26/KSO17 NC_CLOCKI 32KHZ_OUT/GPIO22/WK_SE01 RESET_OUT#/GPIO06 PWRGD VCC1_RST# ADC_TO_PWM_OUT/GPIO19 +3VL 2 4.7U_0805_10V6K P AD 124 125 Power Mgmt/SIRQ C CRY1 CRY2 93 98 99 100 126 OUT0/(SCI) OUT1/IRQ8# TP _CLK <11,27> <11,27> <11,27> <11,27> GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 CFETA/OUT7/nSMI OUT8/KBRST OUT9/PWM2 OUT10/PWM0 PWM_CHRGCTL Miscellaneous R 525 1 R 526 1 @ R 527 1 @ R 528 1 CLKRUN# SER_IRQ PCI_CLK EC_SCI# C8 38 1 15 CAP Access Bus Interface 55 57 54 76 +3VS 49 1 1 1 1 2 0_0402_5% VCC2 R 1395 R 1396 R 1397 R 1398 2 A 2 2 2 2 1 R 1240 119 R 1242 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z VCC1 1 0.1U_0402_16V4Z 39 58 84 106 14 +3VL L 0_0603_5% 07/01 update General Purpose I/O Interface +3VL 2 3 4 Title Compal Electronics, Inc. KBC1098 Size D ocument Number Rev 0.5 L A-6161P Dat e: Tuesday, May 18, 2010 Sheet 5 28 of 41 3 4 5 1 C8 50 1000P_0402_50V7K C8 51 3300P_0402_25V7K <34> VCCP_POK 1 2 1M_0402_1% 1 IN1 2 IN2 MC74VHC1G08DFT2G_SC70-5 1 C8 52 2 10K_0402_5% 1 5 6 2VREF_393 4 2VREF_393 + - 5 VCC 4 V CCP_1.5VSPWRGD <4> A MC74VHC1G08DFT2G_SC70-5 P W R_ GD <28> R 1293 4.99K_0402_1% 2 VTTPWRGOOD <4> U 23B O 7 R 1298 2.49K_0402_1% LM393DT_SO8 34.8K_0402_1% 2 IN2 1 R 1297 U24 OUT 2 R 1299 8 2 34K_0402_1% P 2 75K_0402_1% 1 R 1296 OUT +5VALW G 1 R 1295 1 +3VS 1 1 U25 2 34K_0402_1% +1.5VS IN1 +3VALW 4 1 3300P_0402_25V7K R 1294 1 LM393DT_SO8 R 1292 2 R 1284 8.2K_0402_5% @ 0_0402_5% V C CP_EN <34> SHORT PADS 2 1 +1.5VS_CPU_VDDQ 2 GND - R 1283 2 P J1 1 1 O 2 1 D33 2 1 2 3.3K_0402_5% CH751H-40PT_SOD323-2 U 23A 3 2 49.9K_0402_1% + 2 2 1 R 1289 3 5 2 2VREF_393 34.8K_0402_1% 1 1 R 1291 1 R 1287 2 8 A <13,21,23,28,30,32,34,35> SLP_S3# 2 10K_0402_5% 1 VCC 2 11.5K_0402_1% 2VREF_51125 +3VALW SLP_S3# R 1282 10K_0402_5% G 1 R 1288 +0.75VS R 1286 2 76.8K_0402_1% 4 1 R 1285 +5VS 2 3.3K_0402_5% 8 +3VS +5VALW 1 R 1281 7 Intel S3 power reduction circuit for Calpella. 11/09 R 1280 1 2 1M_0402_1% <35> 1.8VS_POK 6 GND 2 3 1 2 WWAN Card STANDOFF B CPU support H1 HOLEA H4 H5 HOLEA HOLEA B H6 HOLEA 1 1 1 1 1 H3 HOLEA WWLAN Card STANDOFF 1 H2 HOLEA ZZZ LA-6161P_PCB H9 HOLEA H10 HOLEA H11 H 12 HOLEA HOLEA H13 HOLEA H14 HOLEA H15 HOLEA 1 1 1 1 1 H19 HOLEA 1 H 16 HOLEA 1 1 C 1 C H 20 HOLEA H18 HOLEA 1 1 1 H 17 HOLEA D D FM1 1 FM2 1 FM3 1 FM4 Compal Secret Data Security Classification 2009/08/03 Issued Date 1 Deciphered Date 2009/09/03 Title 1 2 3 4 5 6 Compal Electronics, Inc. POK CKT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size D ocument Number Rev 0.5 L A-6161P Dat e: 7 Tuesday, May 18, 2010 29 Sheet 8 of 41 A B C +3VALW to +3VS Transfer 4 1 2 2 4 0_0402_5% R1324 470_0402_5% 2 1 2 C505 +1.5VS_CPU_VDDQ C1024 1 2 0.1U_0402_16V4Z C1025 1 2 0.1U_0402_16V4Z C1026 1 2 0.1U_0402_16V4Z C1027 1 2 0.1U_0402_16V4Z 1 @ 0.01U_0402_16V7K RU NON 2 Q30A 1 R1441 Compal, SI 1/11 2 2 6 2 0_0402_5% 2 1 1 1 R1323 1 RU NON 1 +1.5V 0.1U_0402_16V4Z 1 C859 10U_0805_10V4Z 2 E Add C626,C664 close to JDIMA1; C656,C657 close to JDIMB1. L C1022 1 R1322 330K_0402_5% 0.1U_0402_16V4Z SI7326DN-T1-E3_PAK1212-8 U28 1 2 5 3 C1023 1 +3VS C861 10U_0805_10V4Z B+ +1.5VS_CPU_VDDQ SI7326DN-T1-E3_PAK1212-8 U45 1 2 5 3 C860 0.1U_0402_16V4Z +3VALW +1.5V D SLP_S3 2 1 1 2N7002DW-7-F_SOT363-6 C862 0.01U_0402_25V7K 2 +1.5VS_CPU_VDDQ 1 +0.75VS +5VALW to +5VS Transfer 2 3 2 2 2 5 2N7002DW-7-F_SOT363-6 1 6 SLP_S3 1 C863 10U_0805_10V4M 22_0402_5% Q52B Q85A SLP_S3 C865 10U_0805_10V4Z 2 2 2N7002DW-7-F_SOT363-6 1 1 R693 4 SI7326DN-T1-E3_PAK1212-8 U29 1 2 5 3 4 2 220_0402_5% +5VS C864 0.1U_0402_16V4Z +5VALW 1 R1440 2 RU NON Intel S3 power reduction circuit for Calpella. 11/09 +1.5V to +1.5VS Transfer +1.5VS +1.5VS_CPU_VDDQ 1 2 +GFX_CORE SLP_S4 <24> SLP_S4 +1.5V 3 +VCCP R1473 1 2 discharge circuit-2 R1474 Q88B 4 1 2N7002DW-7-F_SOT363-6 4 SLP_S3 5 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 Q86B 2N7002DWH 2N SOT363-6 SLP_S3 5 Q88A SLP_S3 2 5 <13,36> SLP_S4# 470_0402_5% 3 2 470_0402_5% 6 2 470_0402_5% 3 Q85B R1475 4 0_0402_5% RU NON 2 1 32 2 R1444 100K_0402_5% 1 4 @ @ @ 1 1 10U_0805_6.3V4K 2 1 C869 R1327 +3VL PAD-OPEN 2x2m C868 1 2 0.1U_0402_16V7K 3 C867 C866 2 0.1U_0402_16V7K 10U_0805_6.3V4K 1 +1.5VS J4 @ SI7326DN-T1-E3_PAK1212-8 Q64 1 2 5 3 1 +1.5V +3VL 1 Discharge circuit-1 +1.5VS R1326 100K_0402_5% R1328 R1329 R1330 R1331 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 2 1 +5VS 1 1 +3VS 1 +1.8VS 3 3 2 3 2 Q30B Q7B SLP_S3 5 5 <13,21,23,28,29,32,34,35> SLP_S3# SLP_S3 5 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 4 2N7002DW-7-F_SOT363-6 Compal Secret Data Security Classification 2009/08/03 Issued Date 2009/09/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C 4 4 2N7002DW-7-F_SOT363-6 4 2 Q9B Q9A SLP_S3 2 1 4 Q15A TR 2N7002DW-7-F 2N SOT-363 1 SLP_S3 6 2 6 2 SLP_S3 D Title Compal Electronics, Inc. DC/DC Circuits Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet E 30 of 41 A B C VIN PCN1 PL2 HCB2012KF-121T50_0805 1 2 PL1 HCB2012KF-121T50_0805 1 2 PR37 0_0402_5% 1 2 51125_PWR 1 1 PR1 @15K_0402_5% 2 1 PD12 1SS355_SOD323-2 2 1 PD8 RLZ27V BATT PR23 100_0805_5% 1 2 PD7 2 1 B+_DEBUG 1 CH751H-40PT_SOD323-2 B+_DEBUG PC15 0.1U_0603_50V7K 2 1 PD22 1SS355_SOD323-2 2 1 2 VIN PC3 100P_0402_50V8J 2 1 1 2 PD1 @PJSOT24C_SOT23-3 2 1 3 ACES_87302-0441 PC4 1000P_0402_50V7K 2 1 ADP_SIGNAL <39> A DPIN B++ PC2 1000P_0402_50V7K 6 5 4 3 2 1 PC1 100P_0402_50V8J GND GND 4 3 2 1 2 1 D 2 2 1 O 1 PU103A LM393DR_SO8 3 EN0 <34> D 3 P - 4 + G 8 1 2 P R15 150K_0402_1% 2 1 2 P C12 1000P_0402_50V7K 2 PR3 100K_0402_5% 1 2 1 2 3 3 5 4 PQ2B 2N7002KDWH-2N_SOT363-6 3 +3VL PR13 220K_0402_5% VL PR5 53.6K_0603_1% 1 2 2VREF_51125 1 2 PR7 75K_0402_1% 2 1 P R10 21K_0402_1% 1 5 G Y 3 4 PU1 74LVC1G14GW _SOT353-5 A 2 P 1 2 G S NC 1 D P C10 @100P_0402_50V8J 2 1 3 PD4 BAV99WT1G_SC70-3 1 PQ3 SSM3K7002FU_SC70-3 SMB_EC_CK1 <29> 2 3 PD3 BAV99WT1G_SC70-3 1 2 1 3 2 1 P R12 4.7K_0402_5% 1 +3VL SMB_EC_DA1 2 +3VL VL PR2 470K_0402_1% 1 2 PH1 100K_0402_1%_TSM0B104F4251RZ PQ2A 2N7002KDW H-2N_SOT363-6 2 SMB_EC_CK1 2VREF_51125 CPU 6 2 1 P R14 470K_0402_5% 2 1 PC7 0.01U_0402_50V7K 2 1 PC6 1000P_0402_50V7K PR6 210K_0402_1% 2 1 PR8 100_0402_5% 2 1 PC8 @100P_0402_50V8J 2 1 PC9 @100P_0402_50V8J 2 1 2 1 2 PR11 470K_0402_5% 2 1 <29> SMB_EC_DA1 <29> BAT_ID# PD2 BAV99WT1G_SC70-3 PD6 PJSOT24CH_SOT23-3 3 1 2 1 PR4 1K_0402_1% 3 P D5 PJSOT24CH_SOT23-3 2 +3VL 8 7 6 5 4 1 2 3 2 PL4 HCB2012KF-121T50_0805 PR9 100_0402_5% PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C PQ1 AO4407AL_SO8 1 1 2 1 PC5 @100P_0402_50V8J BATT PL3 HCB2012KF-121T50_0805 1 2 PCN2 ACES_51976-00571-001 1 1 EC_SMD 2 2 EC_SMC 3 3 4 4 5 5 GND 6 GND 7 3 BATT_1 P C11 0.1U_0603_25V7K 2 1 VMB S PQ4 SSM3K7002FU_SC70-3 2 G <22,29,33> ADP_PRES <29,33> AC_ADP_PRES 4 4 Compal Secret Data Security Classification Issued Date 2005/03/10 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. DCIN/BATT/CPU OTP Size Document Number C ustom LA-6161P D ate: R ev Sheet Tuesday, May 18, 2010 D 31 of 40 A V IN B C P2 D B+ P4 P4 <22,29,32> ADP_PRES 2 1 CHGCTRL <29> PR117 210K_0402_1% 1 1 2 1 2 PC127 @4.7U_0805_25V6-K PC115 4.7U_0805_25V6-K 1 2 PC114 4.7U_0805_25V6-K 2 1 1 2 3 ACDET +IN 2 V- 3 -IN V+ 5 OUT 4 PMC <29> PR145 49.9K_0402_1% 2 1 1 2 PR146 39.2K_0402_1% 4 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B 1 LMV321AS5X-G_SOT23-5 Compal Secret Data 2007/05/29 +5VALW PU104 PR144 300K_0402_5% 1 2 PQ107 S SSM3K7002FU_SC70-3 Security Classification Issued Date PR147 11K_0402_1% 1 2 2 1 PC128 1U_0603_6.3V6M 1 PR120 220K_0402_5% 1 2 PR132 470K_0402_5% 1 CHG EN# D 2 G 2 PC139 2200P_0402_50V7K 2 1 PC1380.1U_0402_25V6 2 1 PC140 68P_0402_50V8J 1 2 PC136 2200P_0402_50V7K 2 1 PC135 0.1U_0402_25V6 2 1 PC137 68P_0402_50V8J 1 2 PC133 2200P_0402_50V7K 2 1 PC134 68P_0402_50V8J 1 2 PC132 0.1U_0402_25V6 2 1 PC129 68P_0402_50V8J 1 2 PC131 2200P_0402_50V7K 2 1 12/2 For RF request PR122 47K_0402_5% 1 2 1 PR128 PD102 1K_0402_5% 1SS355_SOD323-2 1 2 2 1 PC123 0.047U_0402_16V7K 2 1 CH GCTRL PC130 0.1U_0402_25V6 2 1 2 IADAPT PQ108 MMBT3906_SOT23-3 3 LM393DR_SO8 A 3 PR133 100K_0402_5% 1 2 1 <29,32> AC_ADP_PRES B+ 2 PC117 0.1U_0402_10V7K +3VL 2VREF_51125 4 1 2 +3VL +3VL PU102A O 1 4 2 PC122 1U_0603_6.3V6M PR130 22K_0402_1% 8 P G PR118 147K_0402_1% Charge Detector High 17.614 Low 17.201 2 4 - 2 PR114 100K_0402_5% SRSET <39> 2 1 PR123 76.8K_0402_1% 1 PR129 10K_0603_0.1% + 2 1 3 2 1 2 DPMDET CELLS 21 20 SRP 19 CELLS <29> BATT PR109 0.01_1206_1% 1 2 1 <39> IADAPT BAT SRSET IADAPT 18 2 PR113 43.2K_0402_1% PC113 4.7U_0805_25V6-K 22 1 PGND 4 2 ISYNSET DL_ CHG PC112 4.7U_0805_25V6-K 23 B 3 5 6 7 8 1 1 PR139 4.7_1206_5% LODRV SRN EXTPWR IADAPT 2 2 1 2 24 2 REGN PC126 1000P_0603_50V7K VADJ PQ106 AO4468L_SO8 PH 12 E 2 2 1 PC124 0.1U_0402_10V7K VL V IN 1 PL101 10UH +-20% #919AQ-H-100M=P3 5.3A 1 2 C 3 2 RE GN VDAC 25 2VREF_51125 2 PR119 604K_0402_1% PQ105 AO4466L 1N SO8 CHGEN LX_CHG 11 13 7 1 PC104 4.7U_0805_25V6-K 1 2 PC103 4.7U_0805_25V6-K 1 2 1 2 2 1 ACN ACP LPMD 3 4 5 ACDET 6 PR138 0_0402_5% DH_CHG 1 2 PC118 1U_0603_10V6K 2 1 1 26 PC121 @0.1U_0603_25V7K G 4 O PU102B LM393DR_SO8 HIDRV PU100 BQ24740RHDR_QFN28_5X5 VREF 4 1 - PC110 PR137 0.1U_0402_10V7K 0_0402_5% BST_CHG 1 2 1 2 2 6 27 PC120 0.1U_0603_50V7K 2 1 + P 2 1 PR131 41.2K_0402_1% PR127 0_0402_5% BTST 14 2 5 AGND LL4148_LL34-2 2 2 2 PD101 VA DJ PR112 1M_0402_1% AC Detector High 13.277 Low 10.770 PR125 22K_0402_5% 8 2 1 PR124 200K_0402_1% 1 PC109 1U_0805_25V6K 1 5 6 7 8 PR110 453K_0402_1% 2 1 2 PC116 1U_0603_6.3V6M 2 PR121 255K_0402_1% 29 9 10 1 1 PR111 422K_0402_1% 1 TP 28 BQ24740VREF 1 <29> BAT_PW M_OUT +3VL P2 PVCC 2 1 PC119 100P_0402_50V8J 4 2 2 P2 CHG_B+ +3VL LM393DR_SO8 PR140 23.7K_0402_1% 2 PR141 24.3K_0402_1% PC111 1U_0603_6.3V6M 1 2 O 7 PU103B 1 PR104 0_0402_5% PR106 10_0805_1% 1 2 IADSLP 1 - 8 7 6 5 3 2 1 8 + 6 P 5 1 1 PR135 100K_0402_1% 2 1 PR136 100K_0402_1% 2 1 PC106 @0.1U_0603_25V7K 8 15 P2 G BATT <14,22,29,30,31,35> SLP_S3# PR108 0_0402_5% 1 2 ACSET 3 LPREF S PR142 1M_0402_5% 1 2 1U_0603_6.3V6M 1 2 3 CHG_B+ CHG EN# 17 2 G 7 PR143 100K_0402_5% VL 2 1 D PQ103 SSM3K7002FU_SC70-3 PC107 0.01U_0402_16V7K 16 1 2 PR103 150K_0402_5% PC108 0.1U_0603_50V7K 2 1 1 2 PR101 56K_0402_1% 1 2 PR102 200K_0402_5% 1 2 1 PR105 150K_0402_5% <39> ADP_EN# +3VL 1 3 PC101 1 2 ACDET PQ102 AO4407AL_SO8 PL100 HCB2012KF-121T50_0805 1 2 PC102 4.7U_0805_25V6-K 2 1 PR100 200K_0402_5% 1 2 PR134 0.01_2512_1% 1 4 1 2 3 2 PC100 0.1U_0603_25V7K 1 2 8 7 6 5 4 8 7 6 5 4 1 2 3 PQ101 AO4407AL_SO8 BATT PQ100 AO4407L_SO8 C Title Compal Electronics, Inc. Charger Size Document Number R ev 0.5 LA-6161P D ate: Sheet Tuesday, May 18, 2010 D 32 of 40 A B C D E PC300 1U_0603_16V7 2 1 2VREF_51125 1 1 2 1 +VREG_51125 VL 1U_0603_10V6K 1 1 PR322 2 2 PC321 2 1 +3VL V- 3 -IN 1 2 1 2 V+ OUT PR331 4 1 2 680K_0402_5% 2 1 5 2 PD304 1 PC320 2.2U_0805_10V6K 1 2 APL5317 3 1SS355_SOD323-2 LMV321AS5X-G_SOT23-5 4 PAD-OPEN 2x2m VCC1_PWRGD <29,39> PD302 1SS355_SOD323-2 Compal Secret Data Security Classification 2008/09/15 Issued Date EN0 <32> Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 4 2 1 PR327 20K_0402_1% 2 FB PR323 64.9K_0402_1% 1 PU302 +IN EN 5 PR326 470K_0402_5% +5VLP 1 GND 3 VOUT 2 +3VALW VIN 2 1 DEBUG_KBCRST P2 2 2 1 11.5K_0402_1% +3VEXTLP PC315 @680P_0603_50V8J PR324 16.5K_0402_1% 3 DEBUG_KBCRST <28> PC313 2 150U_B2_6.3VM_R45M 2 1 PJP304 1 PQ303 IRF8707GTRPBF 1N SO8 3 2 1 +5VALW PR325 220K_0402_5% 2 1 1 2 PC319 10U_0805_10V6K (4.5A,180mils ,Via NO.= 9) 2 PAD-OPEN 2x2m PD301 1SS355_SOD323-2 2 1 + PU303 1 PJP303 +5VLP 5 2 1 PC308 4.7U_0805_25V6-K 2 1 PC307 4.7U_0805_25V6-K 2 1 PR321 100K_0402_1% 1 +5VLP PJP302 +3VLP PR311 @4.7_1206_5% +3VEXTLP 2 1 255K_0402_1% KBC_PWR_ON <29> PL302 4.7UH_FDVE0630-H-4R7M=P3_5.5A_20% 1 2 +5VALWP 51125_PW R PR320 +3VALW P 2 RPGOOD <14> PAD-OPEN 2x2m 2 2 1 PC306 2200P_0402_50V7K 1 4 PR314 @100K_0402_5% PAD-OPEN 4x4m S 4 2 1 PC305 0.1U_0402_25V6 5 6 7 8 VCLK 18 VREG5 VIN 16 17 GND +5VLP 2 PR315 VL 1 1 +3VL (3A,120mils ,Via NO.= 6) PR318 330K_0402_5% 2 1 PQ301 SIS412DN-T1-GE3 1N POWERPAK1212-8 LG_5V DRVL1 3 2 1 19 4 1 1 2 PC323 68P_0402_50V8J DRVL2 PAD-OPEN 4x4m PJP301 PR317 100K_0402_5% 1 2 2 G ENTRIP1 LG_3V 12 PJP300 +5VALW P PQ305 SSM3K7002FU_SC70-3 1 LX_5V 5 D 2 UG_5V 20 PQ304B 2N7002KDW H-2N_SOT363-6 2 ENTRIP1 PU300 DRVH2 DRVH1 TPS51125RGER QFN 24P LL2 LL1 21 LX_3V 11 BST_5V 2 PQ304A 2N7002KDW H-2N_SOT363-6 3 22 1 100K_0402_1% 1 2 3 1 2 3 ENTRIP2 6 ENTRIP1 3 VFB1 VBST1 UG_3V 10 4 PR307 PC311 0_0402_5% 0.1U_0402_10V7K PR309 1 2 1 2 0_0402_5% 1 2 2 1 PC318 10U_0805_10V6K B+ 2 VREF VBST2 PR312 @499K_0402_1% 1 2 4 PC314 @680P_0603_50V8J 4 23 PR316 604K_0402_1% 1 2 51125_PW R TONSEL 24 PGOOD 2 1 PC317 10U_0805_10V6K + PC310 0.1U_0402_10V7K 2 PC312 150U_B2_6.3VM_R45M ENTRIP2 VO1 VREG3 PR306 0_0402_5% 2 1 2 BST_ 3V 9 1 VFB2 VO2 15 1 PR305 115K_0402_1% 1 2 8 EN0 1 8 7 6 5 PQ302 AO4468L_SO8 PL301 4.7UH_FDVE0630-H-4R7M=P3_5.5A_20% 2 1 PR310 @4.7_1206_5% P PAD 13 1 2 3 PR308 0_0402_5% 1 2 B++ 7 2 +3VALWP ENTRIP2 25 4UG1_3V SKIPSEL PC309 4.7U_0805_6.3V6K 5 6 PR304 105K_0402_1% 1 2 PC316 0.1U_0603_25V7K 2 1 5 +3VLP 2VREF_51125 1 PC304 4.7U_0805_25V6-K 2 1 2 PC303 0.1U_0402_25V6 1 2 PC302 2200P_0402_50V7K 2 1 2 PC322 68P_0402_50V8J 1 PR303 20K_0402_1% 1 2 +5VALWP 1 PL300 HCB2012KF-121T50_0805 PR302 20K_0402_1% 1 2 2 B++ B+ PR301 30.9K_0402_1% 1 2 14 PQ300 SIS412DN-T1-GE3 1N POWERPAK1212-8 +3VALWP PR300 13.7K_0402_1% 1 2 B C D Title Compal Electronics, Inc. 3.3VALWP/5VALWP Size Document Number C ustom LA-6161P D ate: Tuesday, May 18, 2010 R ev 0.5 Sheet E 33 of 40 A B C D 1 1 PL401 HCB2012KF-121T50_0805 1 2 ISEN 9 5 6 7 8 DL _VCCP 4 + 2 3 2 1 8 ISL6269ACRZ-T_QFN16 1 2 1 + 2 2 2 VO PR407 8.06K_0402_1% +VCCP PR408 2.2_1206_5% PC412 680P_0603_50V7K 2 1 PC413 0.01U_0402_16V7K 1 2 +VCCP PR410 49.9K_0402_1% 2 1 PQ402 AO N6718L 1N DFN SE_VCCP 1 (18A,720mils ,Via NO.= 36) PL402 0.36UH 20% FDU1040J-H-R36M=P3 33A 1 2 PC410 330U_D2_2V_Y PGND 10 4 PC409 330U_D2_2V_Y 2 11 DH_V CCP1 BST_VCCP 13 BOOT 1 PR403 0_0402_5% DH_VC CP 14 UG FSET 7 FB 6 FB_ VCCP 5 PR409 25.5K_0402_1% 2 1 1 3 1 1 2 PR428 0_0402_5% 2 COMP PR406 @0_0402_5% 1 LG +6269_VCC 1 2 PC406 2.2U_0805_10V6K 2 1 PR411 2.21K_0402_1% PR412 2.94K_0402_1% 1 2 PC417 @0.1U_0402_25V6 2 1 2+VCCP PR413 10_0402_5% 2 PR414 0_0402_5% VTT_SENSE <7> PJP401 1 1 + 2 PC408 330U_D2_2V_Y +VCCP 2 +1.05VS PAD-OPEN 4x4m 1 + 2 PC418 220U_B2_2.5VM_R25M EN PVCC 12 PR404 1 2 2.2_0603_5% 5 4 2 1 PC415 2200P_0603_50V7K 3 FCCM 2 1 1 2 PC414 33P_0402_50V8J <30> VCCP_EN 1 3 1 PC405 0.22U_0603_10V7K PQ401 AO4474L_SO8 VCC 2 PR402 2.2_0603_5% +5VALW PR417 2 0_0603_5% 3 2 1 2 2 1 PC411 @0.1U_0402_10V7K <14,22,29,30,31,33> SLP_S3# PR405 0_0402_5% 1 2 2 PC407 2.2U_0805_10V6K 2 PHASE VIN +6269_VCC 1 LX_VCCP PR401 2 1 @10K_0402_5% 1 PGOOD GND PU401 17 <30> VCCP_POK 1 15 +VCCP 16 +3VS PR427 2 1 10K_0402_5% 2 1 PC404 4.7U_0805_25V6-K 2 1 PC403 4.7U_0805_25V6-K 2 1 PC402 4.7U_0805_25V6-K 2 1 PC401 2200P_0402_50V7K VCCP_B+ 2 1 PC416 0.1U_0402_25V6 1 2 PC419 68P_0402_50V8J B+ 4 4 Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 1.05V_VCCP Size Document Number R ev 0.5 LA-6161P D ate: Sheet Tuesday, May 18, 2010 D 34 of 40 A B C PR610 0_0805_5% 1 2 VIN VCNTL 6 2 GND NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 G2992F1U_SO8 2 G 2 1 PC606 .1U_0402_16V7K PR604 20K_0402_1% 2 1 PR603 1K_0402_1% 1 3 S 1 +0.75VSP 2 1 PC605 10U_0805_6.3V6M 2 2 1 PC604 0.1U_0402_10V7K 1 S 2 G D SLP_S3# D PQ601 SSM3K7002FU_SC70-3 <14,22,29,30,31,33> 3 1 2 1 PR602 PQ602 SSM3K7002FU_SC70-3 10K_0402_5% PD601 1SS355_SOD323-2 1 2 +5VALW 2 1 PC603 1U_0603_10V6K 1 2 +5VALW 1 PR611 @1K_0402_1% 1 +1.5V 2 1 PR601 1K_0402_1% PU601 2 PR612 @0_0805_5% 2 1 PC602 10U_0805_6.3V6M 1 +1.5VS_CPU_VDDQ 2 1 PC601 10U_0805_6.3V6M +1.5V D 2 2 2 PR609 0_0402_5% SW 4 IN 5 BS GND 9 SW 8 IN 7 POK 6 11 TP PL602 1.2UH +-30% 1231AS-H-1R2N=P3 2.9A 1 2 1 3 10 EN/SYNC 1.8VS_POK <30> MP2121DQ-LF-Z_QFN10_3X3 PR606 4.7_1206_5% 2 3 +1.8VSP 2 1 PC614 22U_0805_6.3V6M 1 GND 2 1 PC615 22U_0805_6.3V6M 1 2 PC609 10U_0805_10V6K 2 1 PC610 10U_0805_10V6K 2 1 PC611 0.1U_0402_25V6 HCB1608KF-121T30_0603 1 2 2 FB 2 2 1 1 1 PL601 +5VALW PU602 PC613 0.1U_0402_16V7K 2 1 PD602 @B340A_SMA2 +1.8VSP 316K_0402_1% PR607 1 PR608 402K_0402_1% 2 1 2 1 PC608 @0.1U_0402_16V7K 2 PR605 0_0402_5% 1 2 PC612 680P_0603_50V7K 3 PJP601 1 +0.75VSP 2 +0.75VS PJP602 (2A,80mils ,Via NO.= 4) 1 +1.8VSP 2 +1.8VS (1.5A,60mils ,Via NO.= 3) PAD-OPEN 3x3m PAD-OPEN 3x3m 4 4 Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 0.75VSP/1.8VSP Size Document Number R ev 0.5 LA-6161P D ate: Sheet Tuesday, May 18, 2010 D 35 of 40 A B C D 1 12.4K_0402_1% PC808 4.7U_0805_10V6K RT8209BGQW _W QFN14_3P5X3P5 4 2 1 PC805 4.7U_0805_25V6-K 2 1 PC804 4.7U_0805_25V6-K 2 1 PC803 0.1U_0402_25V6 2 1 PC802 2200P_0402_50V7K PR809 @4.7_1206_5% PC812 @680P_0603_50V8J 1 PC811 220U_B2_2.5VM_R25M LG_1.5V 2 2 1 PC810 4.7U_0805_6.3V6K 9 PR807 1 LGATE 1 2 +5VALW 1 VDDP 10 2 LX_1.5V 11 3 2 1 NC BOOT 12 CS 2 PL802 2.2UH 20% FDVE0630-H-2R2M=P3 8.3A 1 2 PQ802 IRF H3707TRPBF 1N PQFN PGOOD PHASE +1.5V UG1_1.5V + 2 3 2 1 FB 6 UG_1.5V 5 15 1 EN/DEM 5 13 B+ 4 1 VDD UGATE PR804 0_0402_5% 1 2 2 VOUT 4 PGND 1 2 PC809 @10P_0402_50V8J 2 1 PR810 10K_0402_1% +1.5V 3 8 PR808 10K_0402_1% 1 2 2 PC807 1U_0603_10V6K 1 2 PR805 0_0402_5% TON GND PR806 316_0402_1% +5VALW 1 2 1 +5VALW +1.5V 7 PU801 PR803 255K_0402_1% 1 2 2 2 14 PR802 PC806 2.2_0402_5% 0.1U_0402_10V7K BST_1.5V 1 2 1 2 HCB1608KF-121T30_0603 1 2 1 2 PC813 68P_0402_50V8J 2 PC801 @0.1U_0402_16V7K PL801 +1.5V_B+ 5 PR801 0_0402_5% 1 2 1 <14,25> SLP_S4# PQ801 SIS412DN-T1-GE3 1N POWERPAK1212-8 1 3 3 4 4 Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 1.5VP Size Document Number R ev 0.5 LA-6161P D ate: Sheet Tuesday, May 18, 2010 D 36 of 40 8 7 6 5 4 3 2 1 H H B PR266 1 @0_0402_5% 2 PC203 68U_25V_M_R0.36 PC202 4.7U_0805_25V6-K PC207 4.7U_0805_25V6-K 2 1 PC206 4.7U_0805_25V6-K PC230 4.7U_0805_25V6-K 2 1 PC205 2200P_0402_50V7K 2 1 PC204 68U_25V_M_R0.36 2 PR215 17.8K +-1% 0603 2 1 PR214 4.7_1206_5% C P U_CSN2 C PU_CSP2 1 2 PC213 0.033U_0402_16V7K E 2 +5VALW PD202 1SS355_SOD323-2 4 D 2 1PR246 1K_0402_5% H _VID0 2 1PR247 @1K_0402_5% H _VID1 2 1PR248 1K_0402_5% H _VID1 2 1PR249 @1K_0402_5% H _VID2 2 1PR250 1K_0402_5% H _VID2 2 1PR251 @1K_0402_5% H _VID3 2 1PR252 @1K_0402_5% H _VID3 2 1PR253 1K_0402_5% H _VID4 2 1PR254 @1K_0402_5% H _VID4 2 1PR255 1K_0402_5% H _VID5 2 1PR256 1K_0402_5% H _VID5 2 1PR257 @1K_0402_5% H _VID6 2 1PR258 @1K_0402_5% H _VID6 2 1PR259 1K_0402_5% P ROC_DPRSLPVR 2 1PR260 1K_0402_5% P ROC_DPRSLPVR 2 1PR261 @1K_0402_5% PSI# 1PR262 @1K_0402_5% PSI# 2 1PR263 1K_0402_5% PR241 17.8K +-1% 0603 2 1 1 3 PR242 69.8K_0402_1% 2 C PH202 100K_0402_1%_TSM0B104F4251RZ 1 2 CPU_SN-11 PR245 28.7K_0402_1% 2 1 2 PC229 0.033U_0402_16V7K C P U_CSN1 H _VID0 CPU_CSP1-1 2 C PU_CSP1 PC227 680P_0402_50V7K 1 1C PU_SNB1 2 2 5 PQ207 TPCA8036-H 1N SOP-ADV 3 2 1 PR240 4.7_1206_5% 3 2 1 PL203 0.36UH 20% FDU1040J-H-R36M=P3 33A 1 4 4 2 PC226 4.7U_0805_25V6-K 1 VID0 VID1 PC211 680P_0402_50V7K 1 2 1 C PU_SNB2 2 PQ203 TPCA8036-H 1N SOP-ADV 3 2 1 1 2 PC221 0.22U_0603_10V7K <7> H _VID0 <7> H _VID1 <7> H _VID2 <7> H _VID3 <7> H_VID5 <7> H _VID4 <7> H _VID6 F PC225 4.7U_0805_25V6-K 2 1 2 1 PR224 2.2_0603_5% Arrandale SV VID(6-0): 0100111 LV VID(6-0): 0011111 ULV VID(6-0): 0010111 A + CPU_CORE PH201 100K_0402_1%_TSM0B104F4251RZ PC224 4.7U_0805_25V6-K 22 5 CPU_CSP2-2 B A Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2009/09/03 Title 7 6 5 4 3 Compal Electronics, Inc. CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size C Date: 8 2 PR216 69.8K_0402_1% 2 PC231 4.7U_0805_25V6-K 2 1 PHASE_CPU1 PSI #_1 @0_0402_5% 2 + 3 1 PC223 2200P_0402_50V7K 2 1 LGATE_CPU1 21 G 1 CPU_B+ 24 23 2 0_0402_5% 2 CPU_IMON 0_0402_5% <4> 1 PR230 PR265 1 2 25 +VCCP @0_0402_5% CPU_5VFILT 2 + +5VALW 2 4.7U_0603_10V6K HGATE_C PU1 CPU_CSN2-1 PC201 0.1U_0402_25V6 2 1 3 2 1 5 1 PC218 20 19 VID3 VID2 18 17 VID5 VID4 16 15 VID6 14 PSI# DPRSLPVR IMON 12 11 DRVH1 13 VR_TT# 1 2 PC214 0.22U_0603_10V7K PC222 0.1U_0402_25V6 2 1 LL1 VBST1 27 26 1 2 PR218 2.2_0603_5% 1 LGATE_CPU2 PC233 68P_0402_50V8J 1 2 VSNS 28 2 CPU_CSP2-1 CPU_SN-21 1 2 PR217 28.7K_0402_1% PQ205 TPCA8030-H 1N SOP-ADV DRVL1 29 PD201 1SS355_SOD323-2 2 PGND GNDSNS PR264 1 PSI #_1 1 V5IN PU201 TPS51621RHAR_QFN40_6X6 THERM 5 +5VALW 1 2 PR213 0_0402_5% 1 2 PR212 0_0402_5% CPU_TRI PSEL CPU_OSRSEL 31 32 OSRSEL TRIPSEL CPU_CLK_EN# C PU_PGOOD 34 33 PGOOD 35 TONSEL CLK_EN# C PU_ISLEW 1 2 PR210 249K_0402_1% CPU_TON SEL 1 C P U_VREF 2 PR211 0_0402_5% C P U_VR_ON 36 CPU_5VFILT 37 VREF CSN1 VSSSEN SE 2 1 PR244 12.4K_0402_1% DROOP DRVL2 1 2 PR229 68_0402_5% + VCCP 1 2 PR227 20K_0402_1% 1 2 PR243 @0_0402_5% CSN2 1 PR267 9 CPU_TH ERM 10 LL2 30 B+ PL202 0.36UH 20% FDU1040J-H-R36M=P3 33A 1 4 Phase_C PU2 <7> PSI# C PU_VSNS 1 2CPU_VR_TT# PR228 0_0402_5% 0_0402_5% 0_0402_5% 1 2 PR225 8 <7> V CCSENSE PR226 C PU _GNDSNS CSP2 4 4 VBST2 CSP1 HGATE_C PU2 +5VALW DRVH2 GND <7> P ROC_DPRSLPVR 6 MODE 2 1 PC228 0.033U_0402_16V7K 1 2 2 <7> VSSSENSE C 3 33P_0402_50V8J 4 2 CPU_CSN1-1 5 7 1 470_0402_1% D 2 PC219 33P_0402_50V8J 1 2CPU_CSP1-2 1 C PU_CSP1 2 PR223 1 H_PROCHOT# PC220 100P_0402_50V8J 1 C P U_CSN1 2 1 PR222 470_0402_1% PC217 1 2 E PC212 100P_0402_50V8J PR221 470_0402_1% C P U_CSN2 2 1 <7> IMVP_IMON PC215 33P_0402_50V8J 1 2 CPU_CSP2-2 PC216 33P_0402_50V8J 1 2 CPU_CSN2-1 PR220 470_0402_1% C PU_CSP2 2 1 GND 1 2CPU_MODE PR219 0_0402_5% VR_ON C P U_DROOP 39 38 41 1 2 PC210 0.22U_0603_10V7K V5FILT 1 2 PC209 68P_0402_50V8J 2 1 PR209 5.23K_0402_1% F ISLEW C P U_VREF 40 1 2 PR206 @1K_0402_5% PC208 2.2U_0603_10V6K 1 2 PQ201 TPCA8030-H 1N SOP-ADV PR205 220_0402_5% <14,29> PG D_IN PL204 HCB2012KF-121T50_0805 1 2 CPU_B+ PC232 68P_0402_50V8J 1 2 <11> CLK_EN# PL201 HCB2012KF-121T50_0805 1 2 2 1 PR202 @1K_0402_5% PR203 0_0402_5% 1 2 PR204 0_0402_5% 1 2 <12,14> VGATE G PR201 47K_0402_1% 1 2 +3VALW 2 Document Number R ev L A-6161P Tuesday, May 18, 2010 Sheet 37 1 of 40 5 4 3 2 1 BQ24740VREF 1 C PQ1009 MMBT3904WH SOT323-3 PR1067 E 110K_0402_1% 1 2 3 2 B 2 PC1000 0.1U_0603_16V7K 1 PR1013 10K_0402_1% 1 2 <33> IADAPT 2 +5VS PU1000 1 +IN 2 V- 3 -IN OUT 4 1 5 2 S V+ 1 1 D 3 D LMV321AS5X-G_SOT23-5 1 2 G PQ1008 @SSM3K7002FU_SC70-3 PR1018 105K_0402_1% D PR1017 2K_0402_5% 2 2 2 <33> ADP_PRES PC1001 0.01U_0402_16V7K ADP_PRES PR1000 511K_0402_1% 1 VL PD1001 1SS355_SOD323-2 1 E PR1019 10K_0402_5% 2OCP_A_IN 1 PR1033 @0_0402_1% 1 2 <29> OCP - 4 2 1 PR1026 100K_0402_1% 1 2 3 VCC1_PWRGD <29,34> 4 2 PQ1007B 2N7002KDW-2N_SOT363-6 PQ1007A 2N7002KDW-2N_SOT363-6 PR1059 45.3K_0402_1% 1 2 O 1 PR1035 10K_0402_5% 1 2 +3VS PU1001A LM393DR_SO8 1 2 +3VL PR1027 100K_0402_1% B PR1062 1M_0402_5% 1 2 2VREF_51125 5 2 + 6 3 1 2 PQ1006 MMBT3906_SOT23-3 ADP_A_ID 1 PD1004 1SS355_SOD323-2 C 2 B B E PR1046 8.66K_0402_1% 2 1 +3VL 3 S PQ1004 SSM3K7002FU_SC70-3 2 ADP_EN <29> 1 1 2 2 1 PR1045 4.7K_0402_5% PR1042 8.06K_0402_1% PR1040 33K_0402_5% PR1029 100K_0402_1% 1 2 C D 2 G PR1034 200K_0402_1% 1 2 PC1004 0.01U_0402_16V7K PR1031 80.6K_0402_1% 2 1 ADP_EN# <33> 1 2 PR1030 68K_0402_5% 1 VIN OCP# <15> 1 PD1003 GLZ4.7B_LL34-2 2 PR1020 0_0402_5% 3 1 8 PR1032 100_0402_5% OCP_A_IN <29> P 1 2 2 2 B G 2 G C 1 2 1 3 2 C PQ1005 MMBT3904WH SOT323-3 1 1 PC1003 3900P_0402_50V7K D S 3 PQ1003 NDS0610_NL_SOT23-3 PR1028 100K_0402_5% 1 2 +3VS SRSET <33> 1 PD1000 1SS355_SOD323-2 PR1022 100_0402_5% 1 2 PR1025 3.9K_0402_5% 2 1 <32> ADP_SIGNAL 1 PR1064 22K_0402_5% P - 2 + 6 G 8 5 O 7 ADP_DET# <29> PU1001B LM393DR_SO8 A 2 A VL 4 1 2 1 PR1065 PR1063 10K_0402_1% 130K_0402_1% +3VL 2ADP_A_ID PR1066 10K_0402_5% 1 ADP_A_ID <29> Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. ADP_OCP Size Document Number Custom LA-6161P Date: Tuesday, May 18, 2010 Rev Sheet 1 38 of 40 GFXVR_VID_6 <7> GFX_DR VH GFX_SW PC706 4.7U_0805_25V6-K 2 1 PC705 4.7U_0805_25V6-K PC704 4.7U_0805_25V6-K 2 1 5 6 7 8 4 PL702 .56UH +-20% ETQP4LR56 WFC 21A 1 4 AGND 5 PC712 2.2U_0603_10V6K 18 17 4 33 C PR717 4.7_1206_5% 2 1 3 1 2 2 AGND GFX_D RVL 2 PC715 680P_0603_50V7K 3 2 1 CSCOMP 16 GFX_CSCOMP CSFB 15 GFX_C SFB PH701 220K_0402_5%_ERTJ0EV224J~D 1 2 1 PC716 PC717 1200P_0402_50V7K 680P_0402_50V7K PR728 165K_0402_1% 2 2 1 1 PR727 71.5K_0402_1% 2 1 2 LLINE CSREF 14 RAMP RT ILIM 19 +5VALW PQ702 AON6718L_DFN8-5 PGND GPU 20 B+ +GFX_CORE 1 22 21 PR716 PC709 2.2_0603_5% 0.22U_0603_25V7K 2GFX_BOOST-1 1 2 PL701 HCB2012KF-121T50_0805 1 2 PQ701 AO4474L_SO8 23 GFX_BOOST 1 3 2 1 24 PC703 2200P_0402_50V7K 2 1 PC720 68P_0402_50V8J 1 2 1 1 GFX_VCC PC701 1U_0805_25V6K PC702 0.1U_0402_25V6 2 1 2 PR711 1 VID6 25 GFX_VID6 PR710 1 VID5 2 GFXVR_VID_5 <7> GFXVR_VID_4 <7> GFXVR_VID_3 <7> 26 GFX_VID5 PR709 VID4 1 27 GFX_VID4 PR708 1 28 GFX_VID3 VID3 1 29 GFX_VID2 VID2 VID1 1 30 GFX_VID1 PR707 PR706 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 DRVL COMP 13 GFX_ILIM 8 12 1 PR719 20K_0402_1% 6 GFX_VCC 7 PVCC PU701 ADP3211AMNR2G_QFN32_5X5 IREF PC714 470P_0402_50V8J GF X_COMP 2 SW FBRTN 9 2GF X_COMP-11 DRVH CLKEN# 1 2 GFX_RPM PR722 237K_0402_1% 2 0_0402_5% 1 PR725 PR718 1K_0402_1% PC713 47P_0402_50V8J 1 BST FB +GFX_B+ PR712 10_0603_1% VCC GFX_I REF 1 2 PR721 80.6K_0402_1% 2 GFX_CSCOMP 1 2 PR720 10.7K_0402_1% 1 5 1 +5VALW IMON 11 GF X_FB 2 2 1 2 D PWRGD GFX_RT 1 2 PR723 340K_0402_1% GF X_RAMP 2 1 PR726 422K_0402_1% GFX_CSCOMP 4 PR705 1 31 GFX_VID0 EN 3 PC711 220P_0402_50V7K 1 2 PR724 0_0402_5% 2 RPM 1 GF X_IMON VID0 2 2 1 PR715 6.98K_0402_1% 1 2 PC708 0.056U_0402_16V7K PC710 1000P_0402_50V7K 2 1 C 32 PR713 @300K_0402_1% PR714 0_0402_5% 1 2 <7> GFXVR_IMON PR704 1 2 PR703 @0_0402_5% 1 +VCCP GFX_EN 1 2 PR701 @10K_0402_1% +GFX_CORE GFXVR_VID_2 <7> GFXVR_EN <7> D GFXVR_VID_1 <7> 3 GFXVR_VID_0 <7> 4 10 5 1 PR729 54.9K_0603_1% 2 1 GF X_RAMP-1 PR730 1K_0402_1% 2 2 PC718 1000P_0402_50V7K 1 B 1 +GFX_B+ PC719 1000P_0402_50V7K +GFX_CORE PR731 100_0402_5% 2 1 <7> VCC_AXG_SENSE <7> VSS_AXG_SENSE 1 2 PR732 100_0402_5% 2 B A A Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title GFX_CORE Size C Date: 5 4 3 2 Compal Electronics, Inc. Document Number R ev L A-6161P Sheet Tuesday, May 18, 2010 1 39 of 40 5 4 Version change list (P.I.R. List) Item D C 3 2 Power section Reason for change 1 Page 1 of 1 PG# Modify List Date Phase 01/27 SI 1 Tune Loadline and transient response of GFX. P39 2 Tune Loadline and transient response of CPU. P37 Change PR209 to 5.23k. 01/27 SI 3 Add boost resistance for RF team. P36 Change PR802 to 2.2ohm. 01/28 SI 4 Modify the throttling setting level and action speed. P38 Change PR1013 to 10k, PR1000 to 511k, PR1018 to 105k, and PC1000 to 0.1uF. 01/28 SI 5 IN AC mode, the performance will reduce through IADAPT without PQ1008. P38 Add PQ1008. 01/29 SI 6 OTP setting is setted same with other project. P31 Change PR5 to 53.6k and PR10 to 19.1k. 02/01 SI 7 330uF ESR=9mOhm can pass VCCP rippe spec. P34 Change PR408, PR409, and PR410 to 330uF_9mOhm. 02/02 SI 8 CPU thermal protection fine-tune. P31 Change PR10 to 21K from 19.1K 03/26 PV 9 For ULV CPU, need reserved some components. P37 Add PR264, PR265, PR266 locations which is 03/26 reserved. PV 10 For CPU accuracy get better. P37 Change PR215 and PR241 to 0603 size and keep 17.8K 03/26 PV 11 For Electrical Noise Issue. P37 Add PC204, whcih is 68u 03/31 PV 11 For EMI request. P32 Add snabber, PR139 to 4.7ohm, PC126 to 1n 03/31 PV Change PR729 to 54.9k, PC716 to 1200pF, and PC717 to 680pF. D C B B A A Compal Secret Data Security Classification Issued Date 2005/03/10 Deciphered Date 2009/09/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Changed - List Power History Size D o c ument Number C us tom DB-580 Date: R ev Sheet Tuesday, May 18, 2010 1 40 of 5 4 3 2 1 V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit Item P a ge# D 1 28 2 3 28 22 4 5 23 22 T it le B R eq uest O w n er Q u i c k lo o k / w e b 1 2 /2 4 C o m p a l PW R LED W WAN A u d io W LAN 6 11, 21 C D ate 1 2 /2 4 C o m p a l 1/4 C ompal 1/5 1/6 C ompal C ompal 1/6 C ompal C ompal 7 23 A u d io 1/6 8 30 D C -D C 1/11 C ompal 14 9 10 14 GLAN T r a n s f o rm e r 1/13 C ompal 1/14 C ompal 11 12 13 9 24 22 T r a n s f o rm e r A u d io SPI 1/21 H P 1/28 H P 2/23 C ompal 14 14 CPU 2/24 C ompal 15 16 22 18 SPI LCD 3/12 C ompal 3/23 C ompal 17 18 19 CRT 18 LCD 3/24 C ompal 5/18 C ompal I s s u e D e s c rip t io n R ev. S o lu tio n D escrip tio n 0 .2 T h e L E D S ta tu s a b o u t W ireless/Q u ick L o o k 3 / A P P _ B U T T O N _ 1 A P P _ B U T T O N _ 2 a d d 1 0 0 k o h m p u ll Q u ick W eb is a b n o rm a l . O T S # 6 0 3 7 7 8 h ig h t o + 3 V L 0 .2 P W R L E D ca n 't fla sh in S 3 . O T S # 6 0 3 7 7 4 C h a n g e S T B _ L E D sig n a l fro m K B C p in 1 0 5 to p in 1 1 5 0 .2 th e L E D p a n el w a s a u to tu rn o n w h h en p lu g in A C . c o rrect th e J W W A N 1 p in 2 4 p o w er ra il fro m O TS# 603786 + 3 V S to + 3 V _ W W A N 0 .2 a u d io n o fu n cttio n . O T S # 6 0 3 7 7 7 d elet D 1 6 0 .2 D e b u g p o rt 8 0 is n o t u sed d e le t e sig n a l o f P C I _ R S T # ,C L K _ P C I _ D E B U G , L P C _ L F R A M E # ,L P C _ L A D 3 ,2 ,1 ,0 a n d rem o v e C 1 3 1 7 , R 2 7 0 0 .2 resista n ce to o sm a ll w ill im p a ct th e S M T l in e c h a n g e R 1 4 5 7 , R 1 4 5 8 ,R 1 0 2 7 fro m 0 2 0 1 to 0 4 0 2 y ield ra te 0 .2 P C _ B E E P n o so u n d in D O S m o d e. O T S # 6 0 4 3 1 4 in sta ll Q 7 2 a n d ch a n g e R 1 3 5 2 fro m 4 .7 K to 1 0 0 K , c h a n g e C 8 9 5 fro m 0 .1 U to 0 .0 1 U 0 .2 p o w er d o w n seq u en ce h a v v p ro b lem w ith + 5 V S & c h a n g e R 1 3 2 3 fro m 3 3 0 K to 0 o h m + 3 V S . (+ 5 V S g o es to lo w a fte r + 3 V S ) 0 .2 S y stem ca n 't w a k e u p fro m S 3 & S 5 . O T S # 6 0 5 6 4 7 r em o v e R 1 4 8 2 0 .2 E M I n o ise S w a p t h e sig n a l o f M I D 0 < --> 3 , M I D 1 < --> 2 to im p ro v e th e la y o u t ro u tin g . (a v o id th e tra ce ro u tin g u n d er th e T ) 0 .2 reserv e m em o ry th erm a l sen so r b y H P requ est r eserv e U 5 9 ,R 1 4 9 6 ,R 1 4 9 7 ,C 1 3 3 8 ,R 1 4 9 5 0 .2 f o r th e m ic d etectio n co m p a ra to r c h a n g e R 1 2 0 2 fro m 1 2 0 K to 4 7 K 0 .3 F o r S P I R O M R eco v ery R e s erv e R 1 4 9 8 , R 1 4 9 9 , R 1 5 0 0 , R 1 5 0 1 , R 1 5 0 2 , R 1 5 0 3 . A d d R 1 5 0 4 w h ich is p u ll d o w n to G N D a n d co n n ect to 0 .3 F o r C P U T y p e D etect G PIO 46. 0 .4 C a n 't p o w er o n w ith I n tel's W L A N ca rd . C h a n g e p o w er p in + 3 V L fro m p in 4 7 to 5 1 . 0 .4 F o r E M I 's req u est a d d 0 .1 u F (C 1 3 3 9 ) o n E N A B L T to G N D n ea r R 1 1 2 2 . F o r E M I 's req u est F in e tu n e L E D p o w er o n s equ en ce. D C B 0 .4 C h a n g e C 2 3 2 , C 2 3 3 , C 2 3 6 fro m 6 .8 p F to 1 8 p F . C h a n g e C 6 7 6 to 0 .2 2 u F a n d C 6 8 2 to 2 .2 u F . 0 .5 A A Compal Secret Data Security Classification Issued Date 2007/08/02 2009/09/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. HW Changed-List History-1 Size Document Number R ev 0.5 LA-6161P Date: Tuesday, May 18, 2010 Sheet 1 41 of 41 www.s-manuals.com
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