Compal LA 6552P Schematics. Www.s Manuals.com. R0.2 Schematics
User Manual: Motherboard Compal LA-6552P PEW76/PEW86/PEW96 - Schematics. Free.
Open the PDF directly: View PDF .Page Count: 46
A
B
C
D
E
1
1
Compal Confidential
2
2
PEW96 M/B Schematics Document
AMD Danube Only UMA
AMD Champlain Processor with RS880M/SB820M
2010-06-11
LA6552P REV: 0.2
3
3
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Cover Page
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
1
of
45
A
B
1
D
E
Danube
Compal Confidential
AMD S1G4 Processor
PCB
Model Name : PEW96
File Name : LA-6552P
P/N : DA60000IM00
C
ZZZ
LA-6552P MB Rev0: DA60000IM00
LA-6552P RE0 M/B
Memory BUS(DDR3)
uPGA-638 Package
Champlain page 6,7,8,9
204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
page 10,11
1.5V DDRIII 1066~1333MHz
1
Hyper Transport Link
16 x 16
LVDS
page 15
Thermal Sensor
ATI RS880M
ADM1032
page 8
CRT
uFCBGA-528
page 17
page 12,13,14
HDMI Conn.
page 27
USB
conn
X3
A link Express2
Gen1
page 16
page 15
CMOS
Camera
ATI SB820M
MINI Card 1
Broadcom
BCM57780
WLAN
page 26
GPP1
3.3V 48MHz
page 18,19,20,21,22
S-ATA
page 26
Bluetooth
Conn
Mini
card
(WL)X1
Card
Reader
RTS5137
USB port 7
USB port 6
USB port 8
2
USB
3.3V 24.576MHz/48Mhz
uFCBGA-605
LAN(GbE)
page 26
USB port 0,1,2 USB port 5
2
page 27
HD Audio
Gen2
page 24
HDA Codec
ALC272X
page 30
GPP0
RJ45
LPC BUS
page 25
SATA HDD
Conn. page 23
SATA ODD
FFC Conn.
page 23
port 0
port 1
Audio AMP
page 31
LED
3
ENE KB926
Fan Control
page 29
page 28
page 32
3
Phone Jack x2
page 31
RTC CKT.
page 18
LID SW / MEDIA/B
page 28
Int.KBD
Touch Pad
Extend Card/B
page 29
page 29
1. USB X2
EC I/O Buffer
BIOS
page 29
2. ODD X1
page 29
Power On/Off CKT.
page 32
DC/DC Interface CKT.
4
4
page 33
Power Circuit
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
page 34,35,36,37,38
39,40,41,42
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Block Diagrams
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
2
of
45
5
4
3
2
1
D
D
32.768K Hz
RTC
MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N
A_SODIMM
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
B_SODIMM
S1G4
CPU SOCKET
1066MHz
SATA
ATI
SB
SB820M
CPU_CLKP/N
200MHz
CLK_SBLINK_BCLK
100MHz
AMD
AMD
1066MHz
C
25MHz
AMD
CLK_NBHT
Internal CLK GEN.
C
ATI
NB
RS880M
100MHz
CLK_48M_SD
48MHz
CLK_PCIE_WWAN
100MHz
CLK_PCIE_MINI1
100MHz
CLK_PCIE_LAN
B
B
100MHz
CardReader
RTS5137
WWAN
Mini PCI Socket
WLAN
Mini PCI Socket
GbE LAN
BCM
57780
A
A
Compal Secret Data
Security Classification
2010/04/12
Issued Date
2010/10/12
Deciphered Date
Title
CLOCK DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom PEW96 LA-6552P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.2
Friday, June 11, 2010
Sheet
1
3
of
45
A
B
C
D
SIGNAL
STATE
Voltage Rails
1
Full ON
E
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
N/A
N/A
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Power Plane
Description
S1
S3
VIN
Adapter power supply (19V)
N/A
B+
AC or battery power rail for power circuit.
N/A
+CPU_CORE
Core voltage for CPU (1.375-1.5V)
ON
OFF
OFF
+CPU_CORE_NB
Voltage for On-die Northbridge of CPU(0.8-1.1V) ON
OFF
OFF
OFF
+CPU_VDDR
1.05V switched power rail
ON
OFF
+0.75V
0.75V switched power rail for DDR terminator
ON
ON
OFF
+1.1VS
1.1V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+1.5V
1.5V power rail for CPU VDDIO and DDR
ON
ON
OFF
Vcc
Ra/Rc/Re
+1.5VS
1.5V power rail for MINI Card
ON
OFF
OFF
Board ID
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
3.3V switched power rail
ON
OFF
OFF
+3V_LAN
3.3V power rail for LAN
ON
ON
ON
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
0
1
2
3
4
5
6
7
+RTCVCC
RTC power
ON
ON
ON
1
Board ID / SKU ID Table for AD channel
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
2
2
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID
0
1
2
3
4
5
6
7
External PCI Devices
Device
IDSEL#
REQ#/GNT#
EC SM Bus1 address
Interrupts
Address
HEX
Smart Battery
0001 011X b
16H
Device
ADI ADM1032 (CPU)
Address
HEX
1001 100X b
98H
SB-Temp Sensor
SB820
SM Bus 0 address
Address
HEX
Clock Generator
(SILEGO SLG8SP626)
1101 001Xb
D2
DDR DIMM1
1001 000Xb
90
DDR DIMM2
1001 010Xb
94
Device
EVT / PVT stage (w/ pach code)
Board ID
0
1
2
3
4
5
6
7
98H
SB820
SM Bus 1 address
Device
BTO Item
PCB Revision
BOM Structure
Bluetooth
Vari-Bright
No Vari-Bright
HDMI
BT@
VB@
UNVB@
HDMI@
Project ID Table
EC SM Bus2 address
3
Device
BTO Option Table
3
PCB Revision
PEW76/86/96
Address
Mini card
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Notes List
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
4
of
45
5
4
3
2
1
AMD CPU S1G4
+CPU_CORE
BATTERY
12.6V
BATT+
PU5
CHARGER
ISL6261AHAZ-T
PU15
ISL6265IRZ-T
PU16
APL5508-25DC
AC ADAPTOR
19V 90W
+CPU_CORE
0.7~1.3V
VDD CORE 36A
+CPU_CORE_NB
0.8~1.2V
VDDNB 4A
2.5V
VDDA 250mA
1.5V
VDDIO 3A
1.05V
VDDR 1.5A
1.1V
VLDT 1.5A
+CPU_CORE_NB
+2.5VS
+1.05VS
+1.05VS
PU12
APL5915
VIN
+1.1VS
D
D
RAM DDRIII SODIMMX2
+1.5V
PU7
RT8209BGQW
B+
+1.5V
1.5V
VDD_MEM 4A
0.75V
VTT_MEM 0.5A
+0.75VS
PU10
APL5913
NorthBridge AMD RS880M
PU8
RT8209BGQW
PU6
RT8209BGQW
1.0~1.1V
VDDC 1.0V-1.1V 7.6A
1.1V_S0
VDDHTRX+HT 0.68A
VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.23A
1.8V_S0
VDDA18 0.64A
VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A
3.3V_S0
VDDG33 0.06A
AVDD 0.125A
VDDLT33 0A
No Use
VDD18_MEM 1.8V 0.005A
VDD_MEM 1.8V 0.23A
+NB_CORE
+1.1VS
+1.1VALW
+1.1VALW
U36
SI4800BDY
+1.1VS
+1.5VS
+1.5V
C
PU19
TSP51117RGYR
C
U35
SI4800BDY
VGA ATI Madison / Park
PU17
APW7138NITRL
+GPU_CORE
+VDDCI
0.85~1.1V
+1VSG
PU10
APL5913
+1.8VS
PU14
APL5913
PU11
MP2121DQ
+1.8VSP2
1.0V
PCIE_VDDC 2 A
DP[F:A]_VDD10 230 mA
DPLL_VDDC 125 mA
SPV10 100 mA
1.5V
VDDR1 TBD A
1.8V
PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
TSVDD 5 mA
VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
DP[F:A]_VDD18 330 mA
AVDD 70 mA
VDD1DI 45 mA
A2VDDQ 1.5 mA
VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
3.3V
VDDR3 60 mA
A2VDD 130 mA
+1.8VSP1
PU4
SN0806081 RHBR
+5VALW
B
U37
SI1800BDY
+3VS
LCD panel
15.6"
Delay
+3VS_DELAY
U34
SI4800BDY +5VS
B+ 300mA
VRAM 1GB
64Mx16 (K4B1G1646E) * 8
+1.5VS
+3VALW
+INVPWR_B+
VDDC 29 A
VDDCI 4 A
+3.3 350mA
1.5V
2.4 A
B
SouthBridge AMD SB820M
1.1V_S0
+1.1VALW
FAN Control
APL5607
1.1V_S5
+5VS 500mA
VDDIO_33_PCIGP 0.020A
VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS
3.3V_S5
VDDIO_33_S
VDDPL_33_USB_S
VDDAN_33_USB_S 0.2A
VDDAN_33_S
VDDXL_33_S
VDDIO_AZ_S
No Use
VDDCR_11_GBE_S
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDIO_GBE_S
VDDIO_18_FC
+USB_VCCB
Audio AMP
TPA6017A2
A
USB X3
+5V
Dual+1
2.5A
+5V 25mA
SATA
Audio Codec
ALC272X
+5V 3A
+5V 45mA
+3.3V
+3.3VS 25mA
Realtek
RTS5137
EC
ENE KB926
+3.3VS 300mA
+3.3VALW 30mA
+3.3VS 3mA
LAN
BCM57780
ICS9LPRS488B
+3.3VALW 750mA
Mini Card
RTC
Bettary
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+3.3V 400mA
+1.1V
2.5~3.6V
BAT
2010/04/12
Deciphered Date
2010/10/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VDDBT_RTC_G
Title
POWER DELIVERY CHART
Size
Document Number
Custom PEW96 LA-6552P
Date:
5
4
3
A
Compal Secret Data
Security Classification
Issued Date
VDDCR_11_S 113mA
VDDAN_11_USB_S 200mA
VDDCR_11_USB_S 197mA
VDDPL_11_SYS_S
3.3V_S0
+3VALW
U25/U40
TPS2061DRG4 +USB_VCCA
VDDCR_11 1.1V 0.5A
VDDAN_11_PCIE 1A
VDDAN_11_SATA 0.8A
VDDAN_11_CLK 0.4A
2
Rev
0.2
Friday, June 11, 2010
Sheet
1
5
of
45
A
B
C
D
E
1
1
VLDT CAP.
+1.1VS
250 mil
2
<12> H_CADIP[0..15]
<12> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADON[0..15]
<12>
1
<12>
2
C1
10U_0805_10V4Z
1
1
C2
10U_0805_10V4Z
C3
0.22U_0603_16V4Z
2
1
C4
0.22U_0603_16V4Z
2
1
C5
180P_0402_50V8J
2
1
C6
180P_0402_50V8J
2
Near CPU Socket
+1.1VS
+1.1VS
JCPU1A
TBD
2
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
3
C7
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
<12>
<12>
<12>
<12>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
<12>
<12>
<12>
<12>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
2
2
1
10U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
3
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<12>
<12>
<12>
<12>
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<12>
<12>
<12>
<12>
FOX_PZ63823-284S-41F_Champlian
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
AMD CPU S1G4 HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
6
of
45
A
B
C
D
E
Processor DDR3 Memory Interface
JCPU1C
<11> DDRB_SDQ[63..0]
1
MEM:DATA
2
+1.5V
1
R1
1K_0402_1%
C8
1000P_0402_50V7K
1
2
C9
0.01U_0402_25V7K
2
MEM_VREF
1
R2
1K_0402_1%
1
2
+CPU_VDDR
2
JCPU1B
Place them
close to CPU
within 1"
+1.5V
R4
1
1
R5
R410 0_0603_5%
2
1
1
C95
@
10U_0805_10V4Z
2
<10> MEM_MA_RST#
<10> DDRA_ODT0
<10> DDRA_ODT1
<10> DDRA_SCS0#
<10> DDRA_SCS1#
<10> DDRA_CKE0
<10> DDRA_CKE1
<10> DDRA_CLK0
<10> DDRA_CLK0#
3
+CPU_VDDR
AMD suggest
<10> DDRA_CLK1
<10> DDRA_CLK1#
<10> DDRA_SMA[15..0]
<10> DDRA_SBS0#
<10> DDRA_SBS1#
<10> DDRA_SBS2#
<10> DDRA_SRAS#
<10> DDRA_SCAS#
<10> DDRA_SWE#
1.5A
D10
C10
B10
AD10
39.2_0402_1%
MEMZP AF10
2
MEMZN AE10
2
39.2_0402_1%
MEM_MA_RST#
H16
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
MA_RESET_L
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MEMVREF
MB_RESET_L
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
W10
AC10
AB10
AA10
A10
Y10
VDDR: DDR3 under 1033MHz
set to 0.9V to save power
VTT_SENSE
W17
MEM_VREF
B18
MEM_MB_RST#
W26
W23
Y26
DDRB_ODT0
DDRB_ODT1
V26
W25
U22
DDRB_SCS0#
DDRB_SCS1#
J25
H26
DDRB_CKE0
DDRB_CKE1
P22
R22
A17
A18
AF18
AF17
R26
R25
DDRB_CLK0
DDRB_CLK0#
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_CLK1
DDRB_CLK1#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
PAD
T1
MEM_MB_RST# <11>
DDRB_ODT0 <11>
DDRB_ODT1 <11>
DDRB_SCS0# <11>
DDRB_SCS1# <11>
DDRB_CKE0 <11>
DDRB_CKE1 <11>
DDRB_CLK0 <11>
DDRB_CLK0# <11>
DDRB_CLK1 <11>
DDRB_CLK1# <11> <11> DDRB_SDM[7..0]
DDRB_SMA[15..0] <11>
DDRB_SBS0# <11>
DDRB_SBS1# <11>
DDRB_SBS2# <11>
DDRB_SRAS# <11>
DDRB_SCAS# <11>
DDRB_SWE# <11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_SDQ[63..0]
<10>
1
2
DDRA_SDM[7..0]
<10>
3
DDRA_SDQS0 <10>
DDRA_SDQS0# <10>
DDRA_SDQS1 <10>
DDRA_SDQS1# <10>
DDRA_SDQS2 <10>
DDRA_SDQS2# <10>
DDRA_SDQS3 <10>
DDRA_SDQS3# <10>
DDRA_SDQS4 <10>
DDRA_SDQS4# <10>
DDRA_SDQS5 <10>
DDRA_SDQS5# <10>
DDRA_SDQS6 <10>
DDRA_SDQS6# <10>
DDRA_SDQS7 <10>
DDRA_SDQS7# <10>
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
AMD CPU S1G4 DDRIII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
7
of
45
B
C
1
FBMA-L11-201209-221LMA30T_0805 1
2
+
C11
VDDA=0.25A
3300P_0402_50V7K
2
4.7U_0805_10V4Z
1
C12
2
220U_6.3V_M
LDT_RES# / MEMHOT#
no support in S1g4
1
C13
2
2
+1.5V
C14
0.22U_0603_16V4Z
1
1
R6
10K_0402_5%
2
+2.5VS
E
Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB
+2.5VDDA
L1
D
R7
1
B
1K_0402_5%
JCPU1D
1
2 2
A
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
1
1
C16
A9
A8
LDT_RST#
H_PWRGD
LDT_STOP#
2
R10
169_0402_1%
<18> CLK_CPU_BCLK#
1
2
3900P_0402_50V7K
C15
+1.5V
+1.5V
+1.5VS
R12
R14
2
+1.1VS
1
R17
300_0402_5%
LDT_RST#
<18> LDT_RST#
2
C17
0.01U_0402_25V4Z
@
R18
300_0402_5%
1
2
+1.5VS <13,18> LDT_STOP#
2
1
<18> H_PWRGD
1
2
R15
R16
1
1
2
AF4
AF5
AE6
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
SVC
SVD
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
SIC
SID
ALERT_L
R6
P6
HT_REF0
HT_REF1
CPU_SVC
CPU_SVD
CPU_SVC <42>
CPU_SVD <42>
+1.5V
PAD
THERMDC
THERMDA
W7
W8
THERMDC_CPU
THERMDA_CPU
T3
F6
E6
VDD0_FB_H
VDD0_FB_L
VDDIO_FB_H
VDDIO_FB_L
W9
Y9
<42> CPU_VDD1_FB_H
<42> CPU_VDD1_FB_L
CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
G10
AA9
AC9
AD9
AF9
CPU_TEST23
AD7
CPU_TEST18
CPU_TEST19
H10
G9
CPU_TEST25H
CPU_TEST25L
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
H_PWRGD
1
R24
2
0_0402_5%
E9
E8
AB8
AF7
AE7
AE8
AC8
AF8
C2
AA6
A3
A5
B3
B5
C1
+3VS
DBRDY
TMS
TCK
TRST_L
TDI
2
0_0402_5%
H_THERMTRIP# <19>
1
R9
2
0_0402_5%
1
R11
MAINPWON <35,36>
@
2
300_0402_5%
CPU_THERMTRIP#_R
H_PROCHOT#
AF6
AC7
AA8
THERMTRIP_L
PROCHOT_L
MEMHOT_L
1
1
R8
MMBT3904_NL_SOT23-3
A6
A4
<42> CPU_VDD0_FB_H
<42> CPU_VDD0_FB_L
C18
0.01U_0402_25V4Z
@
C19
0.01U_0402_25V4Z
@
VSS
RSVD11
CLKIN_H
CLKIN_L
CPU_VDD0_FB_H
CPU_VDD0_FB_L
LDT_STOP#
1
R21
300_0402_5%
2
2 1K_0402_5%
1K_0402_5%
T2 PAD
CPU_SIC
CPU_SID
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
2
1
+1.5VS
1
1
B7
A7
F10
C6
VDDA1
VDDA2
3
C
<18> CLK_CPU_BCLK
CPU_THERMTRIP#_R
M11
W18
Q1
1
E
F8
F9
PAD
PAD
H_PROCHOT#
1
R13
2
0_0402_5%
H_PROCHOT_R# <18>
PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition
T4
T11
CPU_VDDNB_FB_H <42>
CPU_VDDNB_FB_L <42>
+1.5V
TEST23
TEST28_H
TEST28_L
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
TEST9
TEST6
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
2
J7
H8
D7
E7
F7
C7
CPU_SVC
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
PAD
PAD
PAD
PAD
T5
T6
T7
T8
1
R19
1
R20
CPU_SVD
2
1K_0402_5%
2
1K_0402_5%
+1.5V
C3
K8
CPU_TEST25H
1
R22
1
R23
CPU_TEST25L
1
R26
1
R27
C4
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
C9
C8
2
R25
1
80.6_0402_1%
H18
H19
AA7
D5
C5
@
@
2
510_0402_5%
2
510_0402_5%
+1.5V
2
510_0402_5%
2
510_0402_5%
0.1U_0402_16V4Z
+1.5V
3
1
FOX_PZ63823-284S-41F_Champlian
@
C20
CPU_TEST27
@
U1
2
1
1
THERMDA_CPU
2
THERMDC_CPU
3
2
100P_0402_50V8J
C21
@
4
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
8
EC_SMB_CK2
7
EC_SMB_DA2
CPU_TEST12
5
CPU_TEST18
+1.5V
CPU_TEST21
34.8K_0402_1%
2
2.09V for Gate
G
CPU_SID 3
1
@
@
@
EC_SMB_DA2
D
S
1
3
5
7
9
11
13
15
17
19
21
23
4
Q2
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
4
6
8
10
12
14
16
18
20
22
24
26
R43
@
1
2
0_0402_5%
+3VS
5
20K_0402_5%
@
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
1
CPU_TEST23
1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R265
JP2
U2
HDT_RST#
FDV301N_NL_SOT23-3
4
B
A
LDT_RST#
2
Y
@
1
SB_PWRGD <13,19,28>
4
NC7SZ08P5X_NL_SC70-5
G
2
CONN@ SAMTEC_ASP-68200-07
P
2
CPU_TEST24
G
+3VS
0.1U_0402_16V4Z
R42
1
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
CPU_TEST22
3
2
1
220_0402_5% R36
2
1
220_0402_5% R37
2
1
220_0402_5% R38
2
1
300_0402_5% R39
1
2
300_0402_5% R40
C22
R41
2
CPU_TEST20
1001 100X b
CPU internal thermal sensor
2
3
For SCAN connect use
EC_SMB_DA2 <28>
6
CPU_TEST19
1
2
1K_0402_5%
EC_SMB_CK2 <28>
ADM1032ARMZ_MSOP8
Address
1
R28
CPU_SIC 3
EC_SMB_CK2
2010/04/12
Issued Date
FDV301N_NL_SOT23-3
Compal Electronics, Inc.
Compal Secret Data
Security Classification
D
S
Q3
1
2010/10/12
Deciphered Date
Title
AMD CPU S1G4 CTRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
8
of
45
A
B
C
D
JCPU1F
VDD(+CPU_CORE) decoupling.
JCPU1E
+CPU_CORE
+CPU_CORE
1
1
+
1
+
C23
+
C24
1
1
+
C25
+ C27
@
330U_D2_2V_Y
2
C26
1
330U_D2_2V_Y
2
330U_D2_2V_Y
2
330U_D2_2V_Y
2
330U_D2_2V_Y
2
Near CPU Socket
Change as SGA19331D10 (ESR9 ohm) for PVT
+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
1
C28
22U_0805_6.3V6M
2
1
C29
22U_0805_6.3V6M
2
1
C30
22U_0805_6.3V6M
2
1
C35
22U_0805_6.3V6M
1
2
1
C31
22U_0805_6.3V6M
2
C32
22U_0805_6.3V6M
2
+CPU_CORE
1
1
C33
22U_0805_6.3V6M
2
1
4A
C34
22U_0805_6.3V6M
2
+1.5V
+CPU_CORE
C36
0.22U_0603_16V4Z
2
1
C37
0.01U_0402_25V4Z
2
1
E
1
C38
180P_0402_50V8J
2
C39
0.22U_0603_16V4Z
2
1
C40
0.01U_0402_25V4Z
2
1
C41
180P_0402_50V8J
2
Under CPU Socket
2
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
36A
+1.5V
TBD
FOX_PZ63823-284S-41F_Champlian
Athlon 64 S1
Processor Socket
VDDIO decoupling.
+CPU_CORE_NB
decoupling.
+1.5V
+CPU_CORE_NB
1
C44
22U_0805_6.3V6M
2
1
C45
22U_0805_6.3V6M
1
1
C46
0.22U_0603_16V4Z
2
2
1
C47
0.22U_0603_16V4Z
2
1
C48
C50
1
180P_0402_50V8J 180P_0402_50V8J
2
2
C42
22U_0805_6.3V6M
2
1
C43
22U_0805_6.3V6M
2
1
C49
22U_0805_6.3V6M
2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
1
2
FOX_PZ63823-284S-41F_Champlian
Under CPU Socket
Athlon 64 S1
Processor Socket
+1.5V
C65
0.01U_0402_25V4Z
2
C66
0.1U_0402_16V7K
1
1
C67
0.1U_0402_16V7K
1
C68
180P_0402_50V8J
2
220U_6.3V_M
@
2
1
C55
22U_0805_6.3V6M
2
2
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
2
C56 +
2
1
1
C355
0.22U_0603_16V4Z
Near Power Supply
@
2
1
+CPU_VDDR
1
C69
1
180P_0402_50V8J
2
2
1
@
2
1
@
2
1
@
2
1
3
Reserve for EMI
C57
4.7U_0805_10V4Z
2
1
C58
4.7U_0805_10V4Z
2
+1.5V
@
0.1U_0402_16V7K
2
C354
0.22U_0603_16V4Z
2
1
C96
C64
0.01U_0402_25V4Z
2
C54
0.22U_0603_16V4Z
2
+1.5V
1
1
C101 0.1U_0402_16V7K
+1.5V
1
C53
0.22U_0603_16V4Z
2
1
C100 0.1U_0402_16V7K
C52
0.22U_0603_16V4Z
2
1
0.1U_0402_16V7K
C51
0.22U_0603_16V4Z
2
1
0.1U_0402_16V7K
1
C99
+CPU_VDDR
VDDR decoupling.
0.1U_0402_16V7K
+1.5V
3
C98
C97
Between CPU Socket and DIMM
1
C59
0.22U_0603_16V4Z
2
1
C60
0.22U_0603_16V4Z
2
1
C61
1000P_0402_50V7K
2
1
C62
1000P_0402_50V7K
2
1
C63
180P_0402_50V8J
2
1
C70
180P_0402_50V8J
2
Near CPU Socket Right side.
Change as SGA19331D10 (ESR9 ohm) for PVT
+CPU_VDDR
1
1
2
1
C71
4.7U_0805_10V4Z
2
1
C72
4.7U_0805_10V4Z
2
1
C73
4.7U_0805_10V4Z
2
+
C74
4.7U_0805_10V4Z
2
C75
330U_D2_2V_Y
1
2
C76
4.7U_0805_10V4Z
1
C77
4.7U_0805_10V4Z
2
1
C78
0.22U_0603_16V4Z
2
1
C79
0.22U_0603_16V4Z
2
1
C80
1000P_0402_50V7K
2
1
C81
1000P_0402_50V7K
2
1
C82
180P_0402_50V8J
2
1
C83
180P_0402_50V8J
2
4
4
Near CPU Socket Left side.
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
AMD CPU S1G4 PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
9
of
45
A
B
+VREF_DQ
+1.5V
C
D
E
+1.5V
JDIMM1
DDRA_SDQS2#
DDRA_SDQS2
<7> DDRA_SDQS2#
<7> DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ[0..63]
<7>
DDRA_SDM[0..7] <7>
1
DDRA_SDQ12
DDRA_SDQ13
DDRA_SMA[0..15]
DDRA_SDM1
MEM_MA_RST#
DDRA_SMA[0..15] <7>
MEM_MA_RST# <7>
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
+VREF_CA
+VREF_DQ
DDRA_SDQ30
DDRA_SDQ31
DDRA_SMA3
DDRA_SMA1
<7> DDRA_CLK0
<7> DDRA_CLK0#
<7> DDRA_SBS0#
<7> DDRA_SWE#
<7> DDRA_SCAS#
<7> DDRA_SCS1#
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
<7> DDRA_SDQS4#
<7> DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
3
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
<7> DDRA_SDQS6#
<7> DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R50
10K_0402_5%
1
2
1
+3VS
4
R51
+3VS
2
10K_0402_5%
C90
1
2
2.2U_0805_10V6K
C91
G2
206
DDRA_CKE1
DDRA_CKE1 <7>
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
1
C84
@
2
2
C85
1
1
2
G1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
C10
R49
1K_0402_1%
2
1
C235
@
2
2
C351
1
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDRA_SBS1# <7>
DDRA_SRAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>
+1.5V
+VREF_CA
DDRA_SDQ36
DDRA_SDQ37
1
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
2
0.1U_0402_16V4Z
2
2
C87
0.1U_0402_16V4Z
2
2
C643
1
0.1U_0402_16V4Z
1
C88
0.1U_0402_16V4Z
2
2
C644
1
0.1U_0402_16V4Z
1
C640
C645
1
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
2
C641
1
0.1U_0402_16V4Z
DDRA_SDQS5# <7>
DDRA_SDQS5 <7>
B
C642
1
0.1U_0402_16V4Z
C647
1
+0.75VS
DDRA_SDQ46
DDRA_SDQ47
0.1U_0402_16V4Z
2
2
DDRA_SDQ52
DDRA_SDQ53
C665
1
0.1U_0402_16V4Z
DDRA_SDM6
1
C664
1
C961
2
4.7U_0805_10V4Z
Place near DIMM1
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQS7# <7>
DDRA_SDQS7 <7>
+1.5V
DDRA_SDQ62
DDRA_SDQ63
+1.5V
PAD
C690
T9
2
SB_SMDAT0 <11,19,26>
SB_SMCLK0 <11,19,26>
@
+0.75VS
+0.75VS
2
C691
1
2
C692
1
2
C693
1
1
0.1U_0402_16V4Z
0.01U_0402_16V7K
4
0.01U_0402_16V7K
0.01U_0402_16V7K
Compal Electronics, Inc.
Compal Secret Data
2010/04/12
Issued Date
2010/10/12
Deciphered Date
Title
DDRIII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
C646
1
0.1U_0402_16V4Z
2
2
3
Security Classification
2
R315
1K_0402_1%
DDRA_CLK1 <7>
DDRA_CLK1# <7>
FOX_AS0A626-U8SN-7F
CONN@
DIMM_A STD H:8mm
C680
2
DDRA_SMA2
DDRA_SMA0
1
0.1U_0402_16V4Z
2
1
1
205
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1000P_0402_50V7K
DDRA_SMA8
DDRA_SMA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
0.01U_0402_25V7K
DDRA_SMA12
DDRA_SMA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
4.7U_0805_10V4Z
DDRA_SBS2#
C89
1000P_0402_50V7K
<7> DDRA_SBS2#
DDRA_CKE0
+VREF_CA
0.01U_0402_25V7K
<7> DDRA_CKE0
R310
1K_0402_1%
R48
1K_0402_1%
+VREF_DQ
2
+1.5V
+1.5V
DDRA_SDQS3# <7>
DDRA_SDQS3 <7>
2
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQS0# <7>
DDRA_SDQS0 <7>
DDRA_SDQ6
DDRA_SDQ7
2
DDRA_SDQS1#
DDRA_SDQS1
<7> DDRA_SDQS1#
<7> DDRA_SDQS1
DDRA_SDQS0#
DDRA_SDQS0
1
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ4
DDRA_SDQ5
1000P_0402_50V7K
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
4.7U_0805_10V4Z
DDRA_SDQ2
DDRA_SDQ3
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
DDRA_SDM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDRA_SDQ0
DDRA_SDQ1
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
10
of
45
A
B
+VREF_DQ
C
+1.5V
D
E
+1.5V
JDIMM2
<7> DDRB_SDQS1#
<7> DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
<7> DDRB_SDQS2#
<7> DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
<7> DDRB_CKE0
2
<7> DDRB_SBS2#
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
<7> DDRB_SWE#
<7> DDRB_SCAS#
<7> DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
<7> DDRB_SDQS4#
<7> DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
3
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
<7> DDRB_SDQS6#
<7> DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R52
10K_0402_5%
1
2
1
+3VS
4
R53
205
2
10K_0402_5%
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
G1
DDRB_SDQS0# <7>
DDRB_SDQS0 <7>
DDRB_SDQ[0..63]
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
<7>
DDRB_SDM[0..7] <7>
1
DDRB_SDQ12
DDRB_SDQ13
DDRB_SMA[0..15]
DDRB_SDM1
MEM_MB_RST#
DDRB_SMA[0..15] <7>
MEM_MB_RST# <7>
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQS3# <7>
DDRB_SDQS3 <7>
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_CKE1 <7>
DDRB_SMA15
DDRB_SMA14
2
DDRB_SMA11
DDRB_SMA7
+VREF_DQ
DDRB_SMA6
DDRB_SMA4
+VREF_CA
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
+VREF_DQ
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_SBS1# <7>
DDRB_SRAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
1
C92
2
1
C93
2
+VREF_CA
1
C682
2
1
C352
2
0.1U_0402_16V4Z
<7> DDRB_SBS0#
DDRB_SMA10
DDRB_SBS0#
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDRB_SDQS0#
DDRB_SDQS0
0.1U_0402_16V4Z
<7> DDRB_CLK0
<7> DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDRB_SDQ4
DDRB_SDQ5
1
C353
2
1000P_0402_50V7K
DDRB_SDQ8
DDRB_SDQ9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
4.7U_0805_10V4Z
1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
1000P_0402_50V7K
DDRB_SDQ2
DDRB_SDQ3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
4.7U_0805_10V4Z
DDRB_SDM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C683
2
DDRB_ODT1 <7>
+VREF_CA
DDRB_SDQ36
DDRB_SDQ37
1
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
2
3
DDRB_SDQS5# <7>
DDRB_SDQS5 <7>
+1.5V
DDRB_SDQ46
DDRB_SDQ47
0.1U_0402_16V4Z
2
2
DDRB_SDQ52
DDRB_SDQ53
C677
0.1U_0402_16V4Z
2
2
C670
1
0.1U_0402_16V4Z
DDRB_SDM6
1
C666
2
C671
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
C667
1
0.1U_0402_16V4Z
C672
1
2
0.1U_0402_16V4Z
2
C668
C673
1
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
2
C669
C674
1
0.1U_0402_16V4Z
1
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
+1.5V
+0.75VS
DDRB_SDQS7# <7>
DDRB_SDQS7 <7>
2
DDRB_SDQ62
DDRB_SDQ63
PAD
0.1U_0402_16V4Z
2
C676
1
0.1U_0402_16V4Z
T10
C675
1
1
1
+
C925
2
4.7U_0603_6.3V6K
@
SB_SMDAT0 <10,19,26>
SB_SMCLK0 <10,19,26>
C86
330U_X_2VM_R6M
2
Place near DIMM2
+0.75VS
4
FOX_AS0A626-U4SN-7F
CONN@
DIMM_B STD H:4mm
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
DDRIII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
C94
1000P_0402_50V7K
DDRB_SDQ0
DDRB_SDQ1
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
11
of
45
A
B
C
D
E
U3B
<24>
<24>
<26>
<26>
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
GMCH_HDMI_TXD2+ <16>
GMCH_HDMI_TXD2- <16>
GMCH_HDMI_TXD1+ <16>
GMCH_HDMI_TXD1- <16>
GMCH_HDMI_TXD0+ <16>
GMCH_HDMI_TXD0- <16>
GMCH_HDMI_TXC+ <16>
GMCH_HDMI_TXC- <16>
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
C127 1
C128
1
C129 1
C130
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
<24>
<24>GLAN
<26>
<26>WLAN
2
<6> H_CADOP[0..15]
<6> H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R59
R58
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
H_CADIP[0..15]
H_CADIN[0..15]
+1.1VS
RS880 A11(SA000032710)
3
<6>
<6>
<6>
<6>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<6>
<6>
<6>
<6>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1
R60
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2
HT_RXCALP
HT_RXCALN
M22
M23
R21
R20
C23
A24
301_0402_1%~D
0718 Place within 1"
layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
<6>
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
B24
B25
HT_TXCALP
HT_TXCALN
C
<6>
<6>
<6>
<6>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<6>
<6>
<6>
<6>
1
R61
2
301_0402_1%~D
4
Compal Electronics, Inc.
2010/10/12
Deciphered Date
Title
RS880-HT/PCIE
Date:
B
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
0718 Place within 1"
layout 1:2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
3
H24
H25
L21
L20
RS880 A11(SA000032710)
Compal Secret Data
2010/04/12
<6>
RS780M_FCBGA528
4
Security Classification
H_CADIP[0..15]
H_CADIN[0..15]
U3A
RS780M_FCBGA528
Issued Date
H_CADOP[0..15]
H_CADON[0..15]
HYPER TRANSPORT CPU I/F
2
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
PCIE I/F GFX
1
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
12
of
45
C
D
2
FBMA-L11-160808-221LMT 0603
C143
1
1
1
2
2.2U_0603_6.3V4Z
2
2
2
1U_0402_6.3V4Z
@
+1.8VS
2
2
C147
1U_0402_6.3V4Z
2
20mA
L6
1
+1.8VS
+VDDA18HTPLL
L7
1
4mA
+AVDDQ
2
FBMA-L11-160808-221LMT 0603
C148
2.2U_0603_6.3V4Z
1
1
2
2
C149
1U_0402_6.3V4Z
2
FBMA-L11-160808-221LMT 0603
C150
2.2U_0603_6.3V4Z
1
1
2
2
C151
1U_0402_6.3V4Z
2
1
2
20mA
+VDDA18HTPLL
<14,18,28> A_RST#
1
2
R67
0_0402_5%
<19> NB_PWRGD
+1.8VS
2
R68
1
300_0402_5%
3
R78
1
R79
1
2 4.7K_0402_5% GMCH_CRT_DATA
1
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
H17
D7
E7
<18> NB_DISP_CLKP
<18> NB_DISP_CLKN
E11
F11
4.7K_0402_5%
2 CLK_NBGFX
2 CLK_NBGFX#
4.7K_0402_5%
T2
T1
close NB
U1
U2
V4
V3
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_HDMI_DATA
GMCH_HDMI_CLK
<15> GMCH_LCD_CLK
<15> GMCH_LCD_DATA
<16> GMCH_HDMI_DATA
<16> GMCH_HDMI_CLK
GMCH_CRT_CLK
@
R80
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
D8
NB_PWRGD_R A10
NB_LDTSTOP#
C10
NB_ALLOW_LDTSTOP C12
<18> CLK_SBLINK_BCLK
<18> CLK_SBLINK_BCLK#
GMCH_LCD_CLK
2 4.7K_0402_5% GMCH_LCD_DATA
2 4.7K_0402_5%
G18
G17
E18
F18
E19
F19
C25
C24
+3VS
2 4.7K_0402_5%
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
<18> CLK_NBHT
<18> CLK_NBHT#
R106 1
R83 1
1
E17
F17
F15
120mA
+VDDA18PCIEPLL
R77
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
+NB_PLLVDD
+NB_HTPVDD
C155
1U_0402_6.3V4Z
@
<39> POWER_SEL
1
2
R82
2K_0402_5%
POWER_SEL
B9
A9
B8
A8
B7
A7
B10
G11
1
R85
2
5
A
P
1
U4
NC7SZ08P5X_NL_SC70-5
Y
4 NB_PWRGD_R
@
1
2
0_0402_5%
U3C
F12
E12
F14
G15
H15
H14
DAC_RSET
2
G14
715_0402_1%
65mA
+NB_PLLVDD
A12
+NB_HTPVDD 20mA
D14
B12
1
R65
1
2
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
<14,17> GMCH_CRT_HSYNC
<14,17> GMCH_CRT_VSYNC
<17> GMCH_CRT_CLK
<17> GMCH_CRT_DATA
L9
1
GMCH_CRT_B
<17> GMCH_CRT_B
+VDDA18PCIEPLL
FBMA-L11-160808-221LMT 0603
C154
2.2U_0603_6.3V4Z
GMCH_CRT_G
<17> GMCH_CRT_G
2
+1.8VS
GMCH_CRT_R
<17> GMCH_CRT_R
B
AMD suggest
1
+1.8VS
<8,19,28> SB_PWRGD
2
NC7SZ08P5X_NL_SC70-5
2
150_0402_1%
C8
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
A22
B22
A21
B21
B20
A20
A19
B19
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
PART 3 OF 6
DAC_RSET(PWM_GPIO1)
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
A15
B15
A14
B14
L8
+VDDLTP18
1
C152
1U_0402_6.3V4Z
TXCLK+ <15>
TXCLK- <15>
15mA
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
STRP_DATA
RSVD
TESTMODE
+VDDLT18
C156
0.1U_0402_16V4Z
+VDDLT18
1
2
E9
F7
G12
+1.8VS
1
2
L10
1
2
BLM18AG601SN1D_2P
+1.8VS
C157
4.7U_0805_10V4Z
GMCH_ENVDD <15>
VARY_ENBKL
R73
MIS.
2
2
FBMA-L11-160808-221LMT 0603
C153
2.2U_0603_6.3V4Z
2
+VDDLTP18
300mA
2
1
1
C14
D15
C16
C18
C20
E20
C22
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
TXOUT0+ <15>
TXOUT0- <15>
TXOUT1+ <15>
TXOUT1- <15>
TXOUT2+ <15>
TXOUT2- <15>
R74
2
1
4.7K_0402_5%
1
@
NB_LDTSTOP#
4
+AVDDDI
2
125mA
1
1
R64
NB_PWRGD
U8
2
1
4.7K_0402_5%
1
FBMA-L11-160808-221LMT 0603
C145
0.1U_0402_16V4Z
2
FBMA-L11-160808-221LMT 0603
C146
2.2U_0603_6.3V4Z
Y
A
L4
+NB_HTPVDD
L5
1
B
2
1
4.7K_0402_5%
+1.8VS
1
<8,18> LDT_STOP#
3
1
C144
1
CRT/TVOUT
2
4.7U_0603_6.3V6K
PLL PWR
LVTM
2
4.7U_0603_6.3V6K
L3
C142
1U_0402_6.3V4Z
2
+1.8VS
R63
2.2K_0402_5%
G
+3VS
1
PM
1
1
C684
+AVDD1
FBMA-L11-160808-221LMT 0603
C141
2.2U_0603_6.3V4Z
C679
1
C696
2
+1.8VS
3
+NB_PLLVDD
L2
1
E
1
R417
@
300_0402_5%
CLOCKs
+1.1VS
+1.8VS
0.1U_0402_16V4Z
1
2
5
2
+1.8VS
P
B
G
A
R71 1 UNVB@ 2 0_0402_5%
ENBKL <28>
R72 1 VB@
2 0_0402_5%
GMCH_INVT_PWM <15>
R76 1 VB@
2 0_0402_5%
3
If support VB, pop VB@ and reserve R71
R75
D9
D10
GMCH_HDMI_DET <16>
@
D12
1
R81
2
0_0402_5%
D13
AUX_CAL(NC)
SUS_STAT# <19>
To SB
SUS_STAT_R# <14>Strap
AE8
AD8
pin
1
2
R84
1.8K_0402_5%
RS780M_FCBGA528
RS880
HIGH
LOW
POWER_SEL
RS880 A11(SA000032710)
0.95V
1.1V
1
R87
1
R88
1
R89
GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%
4
4
1
+1.8VS
R90
1K_0402_5%
2
<18> ALLOW_LDTSTOP
R91
1
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
0_0402_5%
NB_ALLOW_LDTSTOP
2
2010/10/12
Deciphered Date
Title
RS880 VEDIO/CLK GEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
13
of
45
A
B
+VDDHT
C261
@
10U_0805_10V4Z
2
C174
1
1
C175
1
2
2
4.7U_0603_6.3V6K
1
C178
C202
2
2
2
2
0.1U_0402_16V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE
1
C179
2
C177
1
1
C192
1
C185
2
2
1
C190
2
2
0.1U_0402_16V4Z
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
700mA
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
1
C186
2
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
10mA
F9
G9
AE11
AD11
+1.8VS
C197
1U_0402_6.3V4Z
5mA
1
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
AE10
AA11
Y11
AD10
AB10
AC10
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
H11
H12
VDD33_1(NC)
VDD33_2(NC)
+NB_CORE
10A
1
2
23mA
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
+
2
220U_C6_6.3V_M_R15
C181
1
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C189
2
L15
2
1
FBMA-L11-201209-221LMA30T_0805
1
1
C176
4.7U_0603_6.3V6K
+1.8VS
680mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX
1
1
1
C172
C173
C196
L14
2
+1.1VS
FBMA-L11-201209-221LMA30T_0805
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
C184
2
0.1U_0402_16V4Z
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
10U_0805_10V4Z
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
H18
G19
F20
E21
D22
B23
A23
2 4.7U_0805_10V4Z
1
1
C195
700mA
C201
1
C168
C171
10U_0805_10V4Z
C161
C163
C183
1
2 10U_0805_10V4Z
2 10U_0805_10V4Z
0.1U_0402_16V4Z
C170
1
1
1
C188
C169
1
C160
C162
0.1U_0402_16V4Z
C164
1
+VDDA11PCIE
C180
1
2.5A
0.1U_0402_16V4Z
+VDDHTRX
0.1U_0402_16V4Z
1
FBMA-L11-201209-221LMA30T_0805
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
C194
1U_0402_6.3V4Z
PART 5/6
0.1U_0402_16V4Z
L13
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
C193
U3E
J17
K16
L16
M16
P16
R16
T16
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
+1.1VS
C187
2
2
2
0.1U_0402_16V4Z
1
2
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
C200
C182
C167
L12
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z
U3F
1
C191
C159
1
0.1U_0402_16V4Z
C166
1
0.1U_0402_16V4Z
1
600mA
1
C165
2
E
1U_0402_6.3V4Z
1
FBMA-L11-201209-221LMA30T_0805
POWER
2
D
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
60mA
RS880 A11(SA000032710)
C198
0.1U_0402_16V4Z
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
1
2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
+3VS
1
RS780M_FCBGA528
PART 6/6
GROUND
0.1U_0402_16V4Z
L11
1.3A
+1.1VS
C
RS880 A11(SA000032710)
1
C199
2
2
0.1U_0402_16V4Z
2
U3D
3
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
2
R92
2
R93
<13,17> GMCH_CRT_VSYNC
@
1
3K_0402_5%
1
3K_0402_5%
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable
0 : Enable
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
Load EEPROM Strap
D1 @
CH751H-40_SC76
2
1
<13> SUS_STAT_R#
2
R264 @
A_RST# <13,18,28>
W12
Y12
AD18
AB13
AB18
V14
1
3K_0402_5%
V15
W14
Enable Side Port Memory
Enable Side Port Memory
4
<13,17> GMCH_CRT_HSYNC
AD16
AE17
AD17
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
2
R94
2
R95
@
1
3K_0402_5%
1
3K_0402_5%
RS880: HSYNC#
0:
Enable
1 : Disable
+3VS
AE12
AD12
Register Readback of strap:
NB_CLKCFG:CLK_TOP_SPARE_D[1]
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
AE23
AE24
IOPLLVSS(NC)
MEM_VREF(NC)
AE18
15mA
26mA
+1.8VS
+1.1VS
4
Compal Electronics, Inc.
Compal Secret Data
2010/04/12
C
W17
AE19
RS880 A11(SA000032710)
2010/10/12
Deciphered Date
Title
RS880 PWR/GND
Date:
B
Y17
W18
AD20
AE21
AD23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
RS780M_FCBGA528
Security Classification
Issued Date
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
SBD_MEM/DVO_I/F
Side port and Strap setting
Debug Mode
3
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
14
of
45
5
4
3
2
LCD POWER CIRCUIT
JLVDS1
+LCDVDD
W=60mils
1
1
R250
300_0603_5%
1
2
3
1
1K_0402_5%
1
C539
1
GMCH_ENVDD
D
Q23
3
<13> GMCH_ENVDD
3
S
2N7002_SOT23
S
2N7002_SOT23
+LCDVDD
W=60mils
0.047U_0402_16V7K
2
2
G
1 R507
2
100K_0402_5%
4.7U_0805_10V4Z
AO3413_SOT23-3
Q13
2
1
2
R252
G
2
G
D
Q11
C538
G1
G2
G3
G4
G5
G6
S
1
2
2
R251
100K_0402_5%
D
D
41
42
43
44
45
46
+3VS
+3VALW
1
1
C540
4.7U_0805_10V4Z
2
2
C541
0.1U_0402_16V4Z
+3VS
+LCDVDD
W=40mils
L59 2
1
FBMA-L11-201209-221LMA30T_0805
C
C544
1
1
B+
L58 2
1
FBMA-L11-201209-221LMA30T_0805
1
BKOFF#
<28> BKOFF#
C545
680P_0402_50V7K 68P_0402_50V8J
2
2
D9
CH751H-40PT_SOD323-2
@
1
2
R121
@
4.7K_0402_5%
2
+INVPWR_B+
R172 1
2 0_0402_5%
R171 1
2 10K_0402_5%
1
1
C546
C547
DISPOFF#
2
10U_0805_10V4Z
2
INVT_PWM
DISPOFF#
INVT_PWM
DISPOFF#
GMCH_LCD_CLK
GMCH_LCD_DATA
TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+
DMIC_DATA_R
DMIC_CLK_R
+3VS_DMIC
@
2
+LCDVDD R841
1
0_0603_5%
+LCDVDD
W=60mils
+3VS
GMCH_LCD_CLK <13>
GMCH_LCD_DATA <13>
DAC_BRIG <28>
D
TXOUT0- <13>
TXOUT0+ <13>
TXOUT1- <13>
TXOUT1+ <13>
TXOUT2- <13>
TXOUT2+ <13>
TXCLK- <13>
TXCLK+ <13>
R842
R885
R886
R843
R887
@
@
@
@
@
2
2
2
2
2
1
1
1
1
1
0_0402_5%
0_0603_5%
0_0603_5%
0_0402_5%
0_0402_5%
DMIC_DATA
DMIC_CLK
LOCAL_DIM <28>
DMIC_DATA <30>
DMIC_CLK <30>
COLOY_ENG_EN <28>
+3VS
+3VS
USB20_N5 <19>
USB20_P5 <19>
INVT_PWM
@
1
2
C1024 @
1
2
C1025 @
1
2
C542
1
2
C543
1
2
C548
+3VS
220P_0402_50V7K
6
CH3
5
Vp
CH2
3
Vn
2
CH1
1
USB20_N5
220P_0402_50V7K
USB20_P5
4
CH4
220P_0402_50V7K
CM1293-04SO_SOT23-6
220P_0402_50V7K
220P_0402_50V7K
1
VB@ 2
1
R262
0_0402_5%
+LCDVDD_L
R319
10K_0402_5%
@
2
<13> GMCH_INVT_PWM
GMCH_INVT_PWM
+INVPWR_B+
C
DAC_BRIG
1 UNVB@ 2
R260
0_0402_5%
W=60mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D14 @
DMIC_CLK_R
EC_INVT_PWM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
IPEX_20143-040E-20F
CONN@
0.1U_0402_16V4Z
DMIC_DATA_R
<28> EC_INVT_PWM
1
LCD/LED PANEL Conn.
B
B
A
A
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
LVDS Connector
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
15
of
45
5
4
+3VS
3
+3VS
2
1
+HDMI_5V_OUT
2
3
1
W=40mils
2
1
1.1A_6VDC_FUSE
HDMI@
2
C549
0.1U_0402_16V4Z
HDMI@
JHDMI1
HDMI_SCLK
HDMI_HPD
+HDMI_5V_OUT
Q16
BSH111 1N_SOT23-3
HDMI_SDATA
HDMI_SCLK
HDMI_SDATA
1
D
S
@
1
D
G
<5V tolerant>
<13> GMCH_HDMI_DATA
3
S
<13> GMCH_HDMI_CLK
F1
1 +HDMI_5V_OUT_1 1
RB491D_SC59-3
HDMI@
R277
4.7K_0402_5%
HDMI@
2
1
2
@
D
4.7K_0402_5%
@
R276
HDMI@
2
2
10K_0402_5%
R275
1
2
R274
1
2
+5VS
G
@
10K_0402_5%
+HDMI_5V_OUT
D3
HDMI_R_CK-
Q17
BSH111 1N_SOT23-3
HDMI_R_CK+
HDMI_R_D0-
2 HDMI@ 1
R278
0_0402_5%
HDMI_R_D0+
HDMI_R_D1-
2 HDMI@ 1
R279
0_0402_5%
HDMI_R_D1+
HDMI_R_D2-
Check 5V tolerant
HDMI_R_D2+
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Place closed to JHDMI1
D
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
SUYIN_100042MR019S153ZL
CONN@
2
+3VS
HDMI@
R280
0_0402_5%
+HDMI_5V_OUT
C
C
GMCH_HDMI_DET
1 1
2
GMCH_HDMI_DET
<13> GMCH_HDMI_DET
U40
@
HDMI@
HDMI_HPD
2
1
2
B
R281
150K_0402_5%
E HDMI@
Q18
MMBT3904_NL_SOT23-3
R283
365K_0402_1%
HDMI@
1
4
C
R284
10K_0402_5%
HDMI@
2
3
Y
1
R411
100K_0402_5%
@
+3VS
1
A
G
2
2
4.7K_0402_5%
2
2
0.1U_0402_16V7K
P
OE#
5
1
@
C687
0.1U_0402_16V7K
@
3
@
1 R304
1
1
C681
2
HDMI_HPD
SN74AHCT1G125GW_SOT353-5
Reserve
HDMI@
HDMI_C_CLK-
UMA 715 ohm
B
HDMI_C_TX2HDMI_C_TX2+
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
R286 1 HDMI@ 2
R287 1 HDMI@ 2
R285 1
1
L60
WCM-2012-900T_0805
@
4
<12> GMCH_HDMI_TXD2<12> GMCH_HDMI_TXD2+
C550 HDMI@2
C551 HDMI@2
715_0402_1%
715_0402_1%
<12> GMCH_HDMI_TXD1<12> GMCH_HDMI_TXD1+
C552 HDMI@2
C553 HDMI@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_TX1HDMI_C_TX1+
R289 1 HDMI@ 2
R290 1 HDMI@ 2
715_0402_1%
715_0402_1%
<12> GMCH_HDMI_TXD0<12> GMCH_HDMI_TXD0+
C554 HDMI@2
C555 HDMI@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_TX0HDMI_C_TX0+
R292 1 HDMI@ 2
R293 1 HDMI@ 2
715_0402_1%
715_0402_1%
<12> GMCH_HDMI_TXC<12> GMCH_HDMI_TXC+
C556 HDMI@2
C557 HDMI@2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_C_CLKHDMI_C_CLK+
R294 1 HDMI@ 2
R295 1 HDMI@ 2
715_0402_1%
715_0402_1%
HDMI_C_CLK+
0_0402_5%
2
1
2
4
3
HDMI_R_CK-
2
3
2
0_0402_5%
HDMI_R_CK+
R291 1 HDMI@ 2
0_0402_5%
HDMI_R_D0-
R288 1
B
HDMI@
HDMI_C_TX0-
1
L61
WCM-2012-900T_0805
@
4
10mil
HDMI_C_TX0+
1
2
4
3
R296 1
2
2
3
0_0402_5%
HDMI_R_D0+
0_0402_5%
HDMI_R_D1-
1
0_0402_5%
2
HDMI@
R298
10mil
1
R302 1
+HDMI_5V_OUT
3
HDMI@
D
S
2
G
2N7002_SOT23
Q19
HDMI@
HDMI_C_TX1-
HDMI@
10mil
HDMI_C_TX1+
2
100K_0402_5%
R297 1 HDMI@ 2
1
L62
WCM-2012-900T_0805
@
4
R299
1
2
4
3
2
3
2
0_0402_5%
HDMI_R_D1+
1 HDMI@ 2
0_0402_5%
HDMI_R_D2-
1
HDMI@
HDMI_C_TX2-
R300
1
L63
WCM-2012-900T_0805
@
4
Place closed to JHDMI1
HDMI_C_TX2+
1
2
4
3
R301 1
2
3
0_0402_5%
2
HDMI_R_D2+
HDMI@
A
A
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
HDMI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
16
of
45
A
B
C
D
E
CRT Connector
W=40mils
+R_CRT_VCC
2
3
2
3
+5VS
D7
2
1
1
RB491D_SC59-3
D5
PJDLC05C_SOT23-3
@
W=40mils
2
1.1A_6VDC_FUSE
1
C558
0.1U_0402_16V4Z
1
1
D4
PJDLC05C_SOT23-3
@
+CRT_VCC
F2
2
1
1
CRT_R_1
2
R408
1
0_0402_5%
CRT_G_1
2
R409
1
0_0402_5%
CRT_B_1
1
<13> GMCH_CRT_B
GMCH_CRT_B
1
0_0402_5%
2
R407
R305
R307
R308
C559
1
C560
2
10P_0402_50V8J
2
2
2
150_0402_1%
140_0402_1%
2 FCM2012CF-800T06_2P
CRT_R_2
L65 1
2 FCM2012CF-800T06_2P
CRT_G_2
L66 1
2 FCM2012CF-800T06_2P
CRT_B_2
L64 1
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
<13> GMCH_CRT_G
GMCH_CRT_G
1
GMCH_CRT_R
<13> GMCH_CRT_R
150_0402_1%
1
2
C561
1
1
C562
2
10P_0402_50V8J
C563
2
10P_0402_50V8J
1
C564
1
2
2
10P_0402_50V8J
10P_0402_50V8J
1
10P_0402_50V8J
2
16
17
G
G
C565
C-H_13-12201513CP
CONN@
100P_0402_50V8J
+CRT_VCC
GMCH_CRT_HSYNC
2
A
CRT_HSYNC_1
4
Y
C566
10P_0402_50V8J
G
<13,14> GMCH_CRT_HSYNC
3
2
1
CRT_VSYNC_2
1
2
2
C567
10P_0402_50V8J
74AHCT1G125GW_SOT353-5
R311
100K_0402_5%
@
1
C568 2
68P_0402_50V8J 1
+CRT_VCC
2
2
C570
68P_0402_50V8J
+CRT_VCC
P
2
A
1
OE#
GMCH_CRT_VSYNC
U19
Y
4
CRT_VSYNC_1
3
G
<13,14> GMCH_CRT_VSYNC
DSUB_15
2 0.1U_0402_16V4Z
5
C571 1
2
DSUB_12
L68 1
2
FCM2012CF-800T06_2P
U18
CRT_DET# <19>
CRT_HSYNC_2
L67 1
2
FCM2012CF-800T06_2P
1 10K_0402_5%
1
P
5
R312 2
1
2 0.1U_0402_16V4Z
OE#
C569 1
74AHCT1G125GW_SOT353-5
Change as SA411250110
Close to Conn side
+CRT_VCC
+3VS
1
3
1
3
2
G
2
R318
4.7K_0402_5%
2
R317
4.7K_0402_5%
@
D
1
GMCH_CRT_DATA
3
S
DSUB_12
GMCH_CRT_DATA <13>
2
G
Q53
BSH111 1N_SOT23-3
1
3
D
S
@
DSUB_15
GMCH_CRT_CLK
GMCH_CRT_CLK <13>
Q65
BSH111 1N_SOT23-3
2
R321
1
0_0402_5%
2
R323
1
0_0402_5%
Check 5V tolerant for DISO state
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
CRT Connector
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
17
of
45
A
B
C
D
E
R370
AA22
Y21
AA25
AA24
W23
V24
W24
W25
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
2
level shift to ISL6265
U29
U28
<13> NB_DISP_CLKP
<13> NB_DISP_CLKN
ISL6265 PWROK input, TTL level: 0.8V~2.0V
When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
NB HT
CPU
T26
T27
<13> CLK_NBHT
<13> CLK_NBHT#
V21
T21
<8> CLK_CPU_BCLK
<8> CLK_CPU_BCLK#
V23
T23
L29
L28
LAN
N29
N28
<24> CLK_PCIE_LAN
<24> CLK_PCIE_LAN#
M29
M28
MINI
T25
V25
<26> CLK_PCIE_MINI1
<26> CLK_PCIE_MINI1#
L24
L23
3
P25
M25
25M_CLK_X1
1
N26
N27
2
25MHZ_20PF_7A25000012
P29
P28
25M_CLK_X2
1
2
C688
27P_0402_50V8J
T29
T28
AMD suggest add Crystal for Internal CLK GEN
L25
<26> CLK_SD_48M
NB_HT_CLKP
NB_HT_CLKN
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
GPP_CLK1P
GPP_CLK1N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
@ R332 20M_0402_5%
1
2
L27
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
2
5
P
4
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
LPCCLK0
<22>
<20,22>
<22>
<22>
<22>
<22>
<22>
+RTCBATT
4
3
NC
2
G21
H21
K19
G22
J24
ALLOW_LDTSTOP <13>
H_PROCHOT_R# <8>
H_PWRGD <8>
LDT_STOP# <8,13>
LDT_RST# <8>
+RTCBATT
C1
SB_32KHI
32K_X2
C2
SB_32KHO
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
D2
B2
B1
25M_X1
25M_X2
R331
1K_0402_5%
EC_CLK <28>
+RTCVCC
D8
2
OSC
NC
3
Close to SB
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
2010/04/12
Issued Date
2
W=20mils
1 C585
2
2
510_0402_5%
1
R334
C583
1
@
for Clear CMOS
0_0603_5%
2
3
4
2010/10/12
Deciphered Date
Title
SB820-PCIE/PCI/ACPI/LPC/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C
+CHGRTC
DAN202UT106_SC70-3
Compal Electronics, Inc.
Compal Secret Data
Security Classification
B
SUYIN_060003HA002G202ZL
SERIRQ <28>
1
OSC
CONN@
PBJ1
LPC_CLK0_EC <22,28>
LPC_CLK1 <22>
LPC_AD0 <28>
LPC_AD1 <28>
LPC_AD2 <28>
LPC_AD3 <28>
LPC_FRAME# <28>
1U_0402_6.3V4Z
1
PLT_RST# <24,26>
PCI_AD24 : VDDR Voltage SW
LPC_CLK0_EC
2
22_0402_5%
1
R330
C584 1
18P_0402_50V8J
A
PLT_RST#
NC7SZ08P5X_NL_SC70-5
CLKRUN# <28>
Y3
1
A
AJ6
AG6
AG4
AJ4
0.1U_0402_16V4Z
C586
U21
Y
2
SB_32KHI
R335
20M_0603_5%
B
SB820M_FCBGA605
2
18P_0402_50V8J
1
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
1
R333
2
4
1
R328
8.2K_0402_5%
@
C582
1
2
A_RST#
14M_25M_48M_OSC
RTC
25M_CLK_X2
L26
0.1U_0402_16V4Z
GPP_CLK2P
GPP_CLK2N
32K_X1
25M_CLK_X1
2
@ 0_0402_5%
2
0_0402_5%
0.1U_0402_16V4Z
Y6
R426
1M_0603_5%
NB_DISP_CLKP
NB_DISP_CLKN
1
R427
1
R425
2
1
2
C689
27P_0402_50V8J
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
AMD suggest add GPIO control gate
<19> SB_GPIO_A_RST#
1
M23
P23
<13> CLK_SBLINK_BCLK
<13> CLK_SBLINK_BCLK#
CLOCK GENERATOR
NB A LINK
1
C581
1
2
2
FDV301N_NL_SOT23-3
+3VALW
1
D
S
H_PWRGD_L <42>
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
T26
+
1
Q21
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
PAD
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
-
2
1
G
2
R329
4.7K_0402_5%
PCIE_CALRP
PCIE_CALRN
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
V2
<22>
<22>
<22>
<22>
2
+3VS
3
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
590_0402_1% AD29
2K_0402_1% AD28
+1.5VS
H_PWRGD
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
PCIRST#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
G
1
1
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
3
+1.1VS_PCIE
2
2
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
W2
W1
W3
W4
Y1
1
R326
R327
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
2
2
2
2
2
2
2
2
2
Part 1 of 5
PCI INTERFACE
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1
1
1
1
1
1
1
1
SB800
PCIE_RST#
A_RST#
LPC
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
C579
C573
C574
C575
C576
C580
C577
C578
U20A
33_0402_5%
1
P1
1 33_0402_5%L1
CPU
1
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
@
2
2
R325
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCI CLKS
A_RST#
<13,14,28> A_RST#
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
2 150P_0402_50V8J
PCI EXPRESS INTERFACES
C572 1
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
18
of
45
A
B
C
D
E
R340 1
@
R341 1
R415 1
2 2.2K_0402_5%
<8> H_THERMTRIP#
<13> NB_PWRGD
SKU ID: 1-> VGA
0-> UMA
SKU_ID
@
R416 1
2 2.2K_0402_5%
ACF_EN
PX Function: 1-> PX Enable
0-> PX Disable *
PX_FN
Mini Card
<26> MINI1_CLKREQ#
<18> SB_GPIO_A_RST#
2 100K_0402_5%
R418 1 VB@
2 2.2K_0402_5%
R402 1
2 2.2K_0402_5%
2
@
1 100K_0402_5%
R846 1
@
2 2.2K_0402_5%
<30> SB_SPKR
<10,11,26> SB_SMCLK0
<10,11,26> SB_SMDAT0
VB Function: 1-> VB Enable
0-> VB Disable *
VB_EN
R588 1 UNVB@ 2 100K_0402_5%
2
EC_RSMRST#
<28> EC_RSMRST#
2 100K_0402_5%
Cinfigure to output or Internal PU/PD
Check SW:
LAY_SEL: 1-> 6L*
0-> 8L
ACF_EN
LAN
SB_GPIO_A_RST#
SKU_ID
MUXLESS_SEL
PX_FN
SB_SMCLK0
SB_SMDAT0
SB_SMCLK1
SB_SMDAT1
VB_EN
<24> LAN_CLKREQ#
R406
2
MUXLESS_SEL
MUXLESS SEL: 1->PX with Muxless
0->PX with Mux
1
R847
100K_0402_5%
<28> EC_LID_OUT#
EC_LID_OUT#
T27
<27> USB_OC#2
<27> USB_OC#1
<27> USB_OC#0
<30>
<22>
<30>
<30>
HDA_BITCLK_AUDIO
HDA_SDOUT
HDA_SDOUT_AUDIO
HDA_SDIN0
<30> HDA_SYNC_AUDIO
<30> HDA_RST_AUDIO#
G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
PAD
USB_OC#2
USB_OC#1
USB_OC#0
R345 1
2 33_0402_5%
R346 1
2 33_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
R347 1
R348 1
2 33_0402_5%
2 33_0402_5%
HDA_SYNC
HDA_RST#
GBE_COL
GBE_CRS
3
GBE_MDIO
+3VS
GBE_RXERR
@
1
R349
@
1
R350
@
1
R351
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDIN1
2
10K_0402_5%
R342 1
2 2.2K_0402_5% SB_SMCLK0
R343 1
2 2.2K_0402_5% SB_SMDAT0
R344 1
2 4.7K_0402_5%
SUS_STAT#
GBE_PHY_INTR
T28
T29
+3VALW
+3VALW
R352 1
4
1
R355
@
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363
SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SB_SMCLK1
2
2.2K_0402_5%
SB_SMDAT1
2
2.2K_0402_5%
2 10K_0402_5%
R420 1
@
2 10K_0402_5%
R3531
@
2 10K_0402_5%
R428 1
R354 1
@
2 10K_0402_5%
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
E23
E24
F21
G29
D27
F28
F29
E27
USB 1.1 USB MISC
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605
H9
J8
B12
A12
F11
E11
EHCI13 / OHCI3
E14
E12
USB_HSD10P
USB_HSD10N
J12
J14
USB_HSD9P
USB_HSD9N
A13
B13
USB_HSD8P
USB_HSD8N
D13
C13
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G12
G14
USB20_P7
USB20_N7
USB_HSD6P
USB_HSD6N
G16
G18
USB20_P6
USB20_N6
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
1
OHCI4
USB_HSD11P
USB_HSD11N
USB_HSD2P
USB_HSD2N
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
2
R338
J16
J18
USB20_P2
USB20_N2
B17
A17
USB20_P1
USB20_N1
A16
B16
USB20_P0
USB20_N0
D25
F23
B26
E26
F25
E22
F22
E21
USB20_P8 <26>
USB20_N8 <26>
Mini1-WLAN
USB20_P7 <27>
USB20_N7 <27>
BT
USB20_P6 <26>
USB20_N6 <26>
CardReader
USB20_P5 <15>
USB20_N5 <15>
Camera
USB20_P2 <27>
USB20_N2 <27>
Ext USB3
USB20_P1 <27>
USB20_N1 <27>
Ext USB2
USB20_P0 <27>
USB20_N0 <27>
Ext USB1
2
EHCI1 / OHCI1
Check SW:
Cinfigure to output or Internal PU/PD
SB_SIC
SB_SID
GPIO199 <22>
GPIO200 <22>
STRAP PIN
G24
G25
E28
E29
D29
D28
C29
C28
3
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
4
GBE_CRS
2 10K_0402_5%
2 10K_0402_5%
R358 1
2 10K_0402_5%
@
2 10K_0402_5%
GBE_RXERR
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
GBE_PHY_INTR
2010/10/12
Deciphered Date
Title
SB820 USB/HD audio
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
EHCI2 / OHCI2
2 10K_0402_5%
@
R430 1
R431 1
GBE_COL
M3
N1
L2
M2
M1
M4
N2
P2
J10
H11
USB_RCOMP 1
11.8K_0402_1%
2 10K_0402_5%
R429 1
R356 1
GBE_MDIO
PAD
PAD
H3
D1
E4
D4
E8
F7
E7
F8
USB_FSD1P/GPIO186
USB_FSD1N
USB 2.0
<24,26> SB_PCIE_WAKE#
+3VS
ACPI / WAKE UP EVENTS
2
2.2K_0402_5%
<28> EC_GA20
<28> EC_KBRST#
<28> EC_SCI#
<28> EC_SMI#
EC_RSMRST#
SB800
G19
GPIO
2N7002_SOT23
A10
USB_RCOMP
USB OC
S
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
USBCLK/14M_25M_48M_OSC
EMBEDDED CTRL
3
1
R339
<28>
<28>
<28>
<8,13,28>
<13>
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
EMBEDDED CTRL
D
@
Q22
1
J2
K1
D3
F1
H1
F2
H5
SUS_STAT#
G6
B3
T24
PAD
C4
T22
PAD
F6
T23
PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
H_THERMTRIP#
J6
NB_PWRGD
AC19
CRT_DET
2
G
<17> CRT_DET#
U20D
<28> EC_SWI#
CRT_DET
HD AUDIO
1
1
@
R336
100K_0402_5%
GBE LAN
2
+3VALW
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
19
of
45
A
B
C
D
E
U20B
SATA_RX0N
SATA_RX0P
AH10
AJ10
<23> SATA_STX_DRX_P1
<23> SATA_STX_DRX_N1
AG10
AF10
<23> SATA_DTX_C_SRX_N1
<23> SATA_DTX_C_SRX_P1
2
+1.1VS_SATA
R364
2
2
R365
1K_0402_1%
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%
<29> SATA_LED#
+3VS
R367 1
@
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
AB14
AA14
SATA_CALRP
SATA_CALRN
AD11
SATA_ACT#/GPIO67
2 10K_0402_5%
1
1
@
Y4
2
2
25MHZ_20PF_7A25000012
@
1
2
C589
27P_0402_50V8J
J5
E2
K4
K9
G2
SATA_X1
3
SATA_RX1N
SATA_RX1P
SATA_TX2P
SATA_TX2N
SATA_X2 AC16
1
2
C588
27P_0402_50V8J
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
SATA_TX1P
SATA_TX1N
AG12
AF12
SATA_X1 AD16
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
Part 2 of 5
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
SATA_X1
SATA_X2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
AH28
AG28
AF26
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC1
NC2
1
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
HW MONITOR
ODD
AJ8
AH8
FLASH
<23> SATA_DTX_C_SRX_N0
<23> SATA_DTX_C_SRX_P0
SATA_TX0P
SATA_TX0N
SPI ROM
HDD
SB800
AH9
AJ9
SERIAL ATA
<23> SATA_STX_DRX_P0
<23> SATA_STX_DRX_N0
1
2
@ R366
1
2
0_0402_5%
EC_THERM# <28>
Check SW:
Cinfigure to output or Internal PU/PD
A3
B4
A4
C5
A7
B7
B8
A8
MEM_1V5
G27
Y2
SB820M_FCBGA605
3
@
R368
10M_0402_5%
SB820 A12(SA00003IW10)
SATA_X2
MEM_1V5 is for gating the
glitch on PCI_AD24
+3VS
C685
2
1
5
0.1U_0402_16V4Z
1
B
Y
A
1 @
R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
U22
P
2
2
0_0402_5%
3
<18,22> PCI_AD24
1
R422
4
G
MEM_1V5
1
R424
2
33_0402_5%
VDDR_SW <39>
2
NC7SZ08P5X_NL_SC70-5
1
2
0_0402_5%
C686
150P_0402_50V8J
For VDDR Voltage Switch, AMD suggest
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
SB820 SATA/IDE/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
20
of
45
B
C
D
U20E
+1.1VS_VDDC
510mA
1
R369
U20C
2
0_0402_5%
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
POWER
43mA
AE28
+VDDPL_3V_PCIE
C604
C605
C606
C607
1
1
1
1
2
2
2
2
600mA
U26
V22
V26
V27
V28
V29
W22
W26
22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+VDDPL_3V_SATA
+1.1VS
1
1
1
1
1
2
2
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
check 220ohm bead
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
+3VALW
C617
C618
C619
C620
C621
1
1
1
1
1
2
2
2
2
2
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
C625 2
C626 2
CORE S0
PCI/GPIO I/O
+1.1VS_CKVDD
400mA
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
R372
1
R373
M10
C590
1
1
1
1
C596
C594
C597
C598
L69
2
1
FBMA-L11-201209-221LMA30T_0805
22U_0805_6.3V6M
V1
2
+1.1VS
1
2
C595
External Clock, connect to +1.1VS
directly, no need thick trace
2
2
2
2
1
1
1
1
C600
C601
C602
C603
check can be removed?
2
0_0402_5%
2
0_0402_5%
+3VALW
@
U85
+VDDCR_USB
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
VDDIO_GBE_S_1
VDDIO_GBE_S_2
L7
L9
1
R374
M6
P8
1
R375
@
L107
2
1
5
FBMA-L11-160808-221LMT 0603
2
0_0402_5%
2
0_0402_5%
1
VIN
1U_0402_6.3V6K
2
1
2
VOUT
GND
4
FB
C989
@
3
EN
APL5317
658mA
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
200mA
C11
D11
3
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.1VS
+3VALW
AD14
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
K28
K29
J28
K26
J21
J20
K21
J22
2
0_0805_5%
10U_0805_10V4Z
N13
R15
N17
U13
U17
V12
V18
W12
W18
93mA
+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
C610
C611
C612
C613
C614
VDDIO_33_GBE_S
VDDPL_33_PCIE
3.3V_S5 I/O
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
VDDRF_GBE_S
CORE S5
1
R371
AF22
AE25
AF24
AC22
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
CLKGEN I/O
71mA
GBE LAN
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PLL
2
2
2
FLASH I/O
2
1
1
1
SERIAL ATA
1
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
USB I/O
C591
C592
C593
C599
1
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
PCI EXPRESS
131mA
+3VS
E
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
32mA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
1
2
2
C608
C609
+1.1VALW
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
Y4
VDDCR_11_S_1
VDDCR_11_S_2
VDDIO_AZ_S
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
F26
G26
M8
A11
B11
VDDPL_33_SYS
M21
VDDPL_11_SYS_S
L22
VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
A21
D21
B21
K10
L10
J9
T6
T8
SB800
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
F19
D6
L20
C615 2
C616 2
113mA
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
EFUSE
D8
TBD
17mA
+VDDPL_3V
C623
C624
+VDDPL_11V
2
2
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
+VDDPL_3V_USB
5mA
197mA
+3V_HWM
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
47mA
62mA
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
1
2
VSSPL_SYS
M20
+1.1VALW
+VDDCR_USB
197mA
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSSAN_HWM
M19
+VDDIO_AZ
GROUND
A
+3VALW
+VDDLX_3V
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
SB820M_FCBGA605
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
3
Part 5 of 5
SB820M_FCBGA605
+VDDPL_11V
+VDDPL_3V_PCIE
+3VS
+VDDPL_3V
+VDDPL_3V_USB
L76
2
1
FBMA-L11-160808-221LMT 0603
L80
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
0.1U_0402_16V4Z
1
2
1
2
1
FBMA-L11-160808-221LMT 0603
2
1
C634
2.2U_0603_6.3V4Z
+VDDPL_3V_SATA
2
+3VS
+3V_HWM
+3VALW
R414 0_0603_5%
2
1
1
C628
+3VALW
+3VS
L79
C635
2.2U_0603_6.3V4Z
2
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
1
2
AMD
1
2
L78
2
1
FBMA-L11-160808-221LMT 0603
C632
C631
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
1
1
2
2
C633
2.2U_0603_6.3V4Z
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
2
1
2
1
R376
4
2
0_0402_5%
1
C637
2.2U_0603_6.3V4Z
2
C638
2.2U_0603_6.3V4Z
For 3V AZ device
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
SB820 power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
21
of
45
B
C
REQUIRED STRAPS
WATCHDOG
TIMER
ENABLE
PCI_CLK3
PCI_CLK4
LPC_CLK0
LCP_CLK1
GPIO200
USE
DEBUG
STRAP
Inter CLK
Gen Mode
EC
ENABLE
CLOCKGEN
ENABLE
H,H = Reserved
Performance
MODE
FORCE PCIE
GEN1
DEFAULT
IGNORE
DEBUG
STRAP
Inter CLK
Gen Mode
+3VS
+3VS
+3VS
+3VS
R380
10K_0402_5%
2
1
DEFAULT
R379
10K_0402_5%
2
1
DEFAULT
R378
10K_0402_5%
2
1
DEFAULT
@
@
@
@
H,L = SPI ROM
EC
DISABLE
1
L,H = LPC ROM (Default L,NC)
CLOCKGEN
DISABLE
L,L = FWH ROM
Disable
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
WATCHDOG
TIMER
DISABLE
Enable
GPIO199
DEFAULT
+3VALW
DEFAULT
+3VALW
+3VALW
@
+3VALW
R385
2.2K_0402_5%
2
1
PCI_CLK2
ALLOW PCIE
GEN2
R384
10K_0402_5%
2
1
PCI_CLK1
R383
10K_0402_5%
2
1
AZ_SDOUT
LOW POWER
MODE
1
PULL
LOW
E
Check Internal PU/PD
R382
10K_0402_5%
2
1
PULL
HIGH
D
R381
10K_0402_5%
2
1
A
@
<19> HDA_SDOUT
<18> PCI_CLK1
<18> PCI_CLK2
<18> PCI_CLK3
<18> PCI_CLK4
<18,28> LPC_CLK0_EC
<18> LPC_CLK1
<19> GPIO200
<19> GPIO199
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
PCI_AD23
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
<18>
<18>
<18>
<18>
<18>
<18,20>
<18>
3
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
@
check default
@
@
R401
2.2K_0402_5%
2
1
PCI_AD24
R400
2.2K_0402_5%
2
1
PCI_AD25
R399
2.2K_0402_5%
2
1
PCI_AD26
R398
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD27
+3VS
R397
2.2K_0402_5%
2
1
3
@
R396
10K_0402_5%
2
1
R395
10K_0402_5%
2
1
DEBUG STRAPS
R394
2.2K_0402_5%
2
1
@
+3VS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
R393
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
@
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
2
R386
10K_0402_5%
2
1
2
@
@
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
SB820 STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
22
of
45
A
B
C
D
E
F
G
H
SATA HDD Conn.
1
1
JHDD1
<20> SATA_STX_DRX_P0
<20> SATA_STX_DRX_N0
<20> SATA_DTX_C_SRX_N0
<20> SATA_DTX_C_SRX_P0
C656 1
C658 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
C657 1
C659 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+3VS
1
2
+5VS
R405 1
+3VS
C639
0.1U_0402_16V4Z
+5VS_HDD
2 0_0805_5%
10U_0805_10V4Z
C660
1
2
C661
0.1U_0402_16V4Z
1
1
C662
2
2
C663
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
GND
GND
24
23
SANTA_192301-1
CONN@
2
1U_0402_6.3V4Z
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
2
1000P_0402_50V7K
SATA ODD FFC Conn.
JODD1
<20> SATA_STX_DRX_P1
<20> SATA_STX_DRX_N1
C648 1
C649 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
<20> SATA_DTX_C_SRX_N1
<20> SATA_DTX_C_SRX_P1
C650 1
C651 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
R403 1
@
2 1K_0402_1%
3
+5VS
80mils
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
3
GND
GND
13
14
ACES_85201-1205N
CONN@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDD & ODD Connector
Document Number
Date:
A
B
C
D
E
F
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
G
Sheet
23
H
of
45
A
B
C
D
+3V_LAN
+3VALW
R800
60mil
1
2
0_1206_5%
2
1
C902
C901
4.7U_0805_10V4Z
U70
+3V_LAN
1
2
0.1U_0402_16V4Z
+LAN_BIASVDDH
42
VDDC
BIASVDDH
25
6
15
41
VDDC
VDDC
VDDC
XTALVDDH
14
AVDDH
30
AVDDH
36
TRD3_N
37
LAN_MIDI3-
TRD3_P
38
LAN_MIDI3+
TRD2_N
35
LAN_MIDI2-
TRD2_P
34
LAN_MIDI2+
TRD1_N
31
LAN_MIDI1-
TRD1_P
32
LAN_MIDI1+
TRD0_N
29
LAN_MIDI0-
TRD0_P
28
LAN_MIDI0+
LINKLED#
48
SPD100LED#
47
1
1
2
0.1U_0402_16V4Z
+LAN_AVDDL
+LAN_GPHYPLLVDDL
24
AVDDL
AVDDL
AVDDL
LAN_MIDI3- <25>
LAN_MIDI3+ <25>
LAN_MIDI2- <25>
SPROM_CLK
(EECLK)
SPROM_DOUT
(EEDATA)
On chip
1
0
AT24C02
1
1
+3V_LAN
LAN_MIDI2+ <25>
C906 1
GPHY_PLLVDDL
18
PCIE_PLLVDDL
21
PCIE_PLLVDDL
LAN_MIDI1- <25>
LAN_MIDI0- <25>
LAN_MIDI0+ <25>
C9071
C9081
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
<19,26> SB_PCIE_W AKE#
<28> EC_PME#
+3V_LAN
R806 1
R807 1
R808 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 17
2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 16
22
23
LAN_PME#
4
LAN_RESET# 2
20
@
2 0_0402_5%
19
2 0_0402_5%
2 4.7K_0402_5%
R809 1
<18,26> PLT_RST#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
REST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SPD1000LED#
46
TRAFFICLED#
45
U71 @
8
7
6
5
2
R801
0_0402_5%
1
LAN_LINK# <25>
2
R805
0_0402_5%
1
LAN_ACTIVITY#
2
R812
1K_0402_1%
@
20mil
+LAN_XTALVDDH 1
C909
5
+3VS
R810 1
2 1K_0402_5%
40
R813 1
2 10K_0402_5%
1
SPROM_DOUT
EECLK
44
SPROM_CLK
VMAIN_PRSINT
SR_LX
T12 PAD
T13 PAD
LAN_XTALO_R
LAN_XTALI
13
XTALO
12
XTALI
+LAN_AVDDH
1
C911
C912
SR_VFB
11
+1.2V_LAN_OUT
1
2
4.7UH_PG031B-4R7MS_1.1A_20%
8
+1.2V_LAN
C913
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
2
1
2
1
2
26
RDAC
SR_VDDP
1.24K_0402_1%
3
SR_VDD
NC
7
C917
1
0.1U_0402_16V4Z
2
2
1
20mil
+LAN_GPHYPLLVDDL
1
2
C919
0.1U_0402_16V4Z
49
BCM57780A0KMLG_QFN48_7X7
0.1U_0402_16V4Z
L104
1
2
BLM18AG601SN1D_2P
+1.2V_LAN
C916
4.7U_0805_10V4Z
C918
2
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
CLKREQ#
2
+LAN_PCIEPLLVDD
1
C915
+3V_LAN
1
L102
1
2
BLM18AG601SN1D_2P
1
20mil
PAD
<19> LAN_CLKREQ#
10
9
0.1U_0402_16V4Z
3
C914
10U_0805_10V4Z
R814
LAN_RDAC
2
20mil
LOW_PWR
+3V_LAN
L101
1
2
BLM18AG601SN1D_2P
+LAN_BIASVDDH 1
C910
L103
3
L100
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
2
20mil
43
1
2
3
4
<25>
<18> CLK_PCIE_LAN
<18> CLK_PCIE_LAN#
EEDATA
A0
A1
NC
GND
AT24C02_SO8
R811
1K_0402_1%
2 0_0402_5%
MODE
VCC
WP
SCL
SDA
1
<12>
<12>
<12>
<12>
R803
1K_0402_1%
SPROM_CLK
SPROM_DOUT
1
2
2 0.1U_0402_16V4Z
@
R802
1K_0402_1%
@
LAN_MIDI1+ <25>
2
+LAN_PCIEPLLVDD
27
33
39
+LAN_AVDDH
2
2
2
0.1U_0402_16V4Z
+LAN_XTALVDDH
1
C903
1
0.1U_0402_16V4Z
1
1
C904
C905
2
4.7U_0805_10V4Z
1
2
C900
2
1
+1.2V_LAN
2
1
20mil
+LAN_AVDDL
1
C921
LAN_XTALI
0.1U_0402_16V4Z
2
2
1
L105
1
2
BLM18AG601SN1D_2P
+1.2V_LAN
C920
4.7U_0805_10V4Z
L106
1
2
BLM18AG601SN1D_2P
+1.2V_LAN
C922
4.7U_0805_10V4Z
1
LAN_XTALO_R
R815
200_0402_1%
4
1
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
C924
33P_0402_50V8K
2010/04/12
Deciphered Date
2010/10/12
Title
2
1
2 LAN_XTALO
25MHZ_20PF_7A25000012
C923
33P_0402_50V8K
2
2
Y5
1
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
BROADCOM 57780
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
D
24
of
45
5
4
3
2
1
D
D
LAN Connector
BH GS5009-D
JRJ45
<24> LAN_ACTIVITY#
LAN_MIDI0+
LAN_MIDI0-
1
2
3
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
RJ45_MIDI0+
RJ45_MIDI0-
<24> LAN_MIDI1+
<24> LAN_MIDI1-
LAN_MIDI1+
LAN_MIDI1-
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
RJ45_MIDI1+
RJ45_MIDI1-
<24> LAN_MIDI2+
<24> LAN_MIDI2-
LAN_MIDI2+
LAN_MIDI2-
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
RJ45_MIDI2+
RJ45_MIDI2-
<24> LAN_MIDI3+
<24> LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI3-
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
RJ45_MIDI3+
RJ45_MIDI3-
2
R823
1
C938
+3V_LAN
1
1K_0402_5%
2
220P_0402_50V7K
Yellow LED-
11
Yellow LED+
RJ45_MIDI3-
8
PR4-
RJ45_MIDI3+
7
PR4+
RJ45_MIDI1-
6
PR2-
RJ45_MIDI2-
5
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
350UH_IH-037-2
0.1U_0402_16V4Z
2
2
1
R819
75_0402_1%
C931
R820
75_0402_1%
0.1U_0402_16V4Z
2
R821
75_0402_1%
0.1U_0402_16V4Z
2
R824
1
C942
+3V_LAN
1
1K_0402_5%
2
220P_0402_50V7K
@
0_0805_5%
1
Green LED-
9
C
R412
0_0805_5%
@
Green LED+
SANTA_130451-K
CONN@
RJ45_GND
1
RJ45_GND
Place close to TCT pin
R413
2
13
14
R822
75_0402_1%
2
0.1U_0402_16V4Z
C930
1
1
1
C929
2
1
2
2
C928
PR1+
10
<24> LAN_LINK#
2
1
1
1
1
C
SHLD2
SHLD1
2
<24> LAN_MIDI0+
<24> LAN_MIDI0-
12
1
T25
LANGND
2
2
C940
1000P_1206_2KV7K
40mil
1
C941
2
1
0.1U_0402_16V4Z
2
3
LAN_ACTIVITY#
LAN_LINK#
40mil
C939
4.7U_0805_10V4Z
D40
PJDLC05_SOT23-3
@
LAN_ACTIVITY#
1
C943
2
220P_0402_50V7K
LAN_LINK#
1
C944
2
220P_0402_50V7K
B
1
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Issued Date
Deciphered Date
2010/10/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
LAN Magnetic & RJ45
Size
B
Date:
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
25
of
45
A
B
C
D
E
Mini-Express Card for WLAN
+3VS
1
2
+1.5VS
1
C705
4.7U_0805_10V4Z
2
1
C706
0.1U_0402_16V4Z
2
1
C707
0.1U_0402_16V4Z
2
1
C708
4.7U_0805_10V4Z
2
1
C709
0.1U_0402_16V4Z
2
C710
0.1U_0402_16V4Z
1
1
JMINI1
R440 1
@
2 0_0402_5%
<19> MINI1_CLKREQ#
<18> CLK_PCIE_MINI1#
<18> CLK_PCIE_MINI1
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<12> PCIE_PTX_C_IRX_N1
<12> PCIE_PTX_C_IRX_P1
<12> PCIE_ITX_C_PRX_N1
<12> PCIE_ITX_C_PRX_P1
+3VS
0_0402_5%
R445 1
2
<28> E51TXD_P80DATA
<28> E51RXD_P80CLK
1
3
5
7
9
11
13
15
E51TXD_P80DATA_R
E51RXD_P80CLK
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS
+1.5VS
53
54
55
56
WL_OFF#
PLT_RST#
+3V_WLAN
1
R441 1
R442
@
MINI1_SMBCLK
@
1
MINI1_SMBDAT R443
@
1
R444
2
2 0_0603_5%
0_0603_5%
2
0_0603_5%
2
0_0603_5%
WL_OFF# <28>
PLT_RST# <18,24>
+3VS
+3VALW
Normal
Peak
Normal
+3VS
1000
750
+3V
330
250
250 (wake enable)
+1.5VS
500
375
5 (Not wake enable)
SB_SMDAT0 <10,11,19>
SB_SMCLK0 <10,11,19>
USB20_N8 <19>
USB20_P8 <19>
(MINI1_LED#)
WIMAX_LED#
WLAN_LED#_L
+3VS
R835 1
+3VS
ACES_88910-5204
CONN@
WIMAX_LED#
@
1
R836
1
Auxiliary Power (mA)
Primary Power (mA)
0_0402_5%
2
R848
100K_0402_5%
2
2
2
R492
100K_0402_5%
Mini Card Power Rating
Power
G1
G2
G3
G3
2
1
3
5
7
9
11
13
15
1
SB_PCIE_WAKE#
<19,24> SB_PCIE_WAKE#
2
10K_0402_5%
WLAN_LED#_L
2
1
MINI1_LED# <28>
3
(9~16mA)
CHP202UPT_SOT323-3
D44 @
1
2
R837
0_0402_5%
Height : 4mm
Card Reader RTS5138 / RTS5137
(only SD+MMC function)
Card Reader Connector
3
3
+3VS_CR
2 0_0805_5%
1
30mil
1
10mil
100P_0402_50V8J
RREF
2
6.2K_0603_1%
USB20_N6
<19> USB20_N6
USB20_P6
<19> USB20_P6
2
C981
R855 1
1
C983
4.7U_0805_10V4Z
2
2
30mil
C984
1
0.1U_0402_16V4Z
1
2
+3VS_CR
+CARDPWR
VREG
10mil
C985
1U_0402_6.3V6K
XDDRY_SDWP_MSCLK
2
3
4
5
6
7
8
9
10
11
12
REFE
GPIO0
DM
DP
CLK_IN
3V3_IN
CARD_3V3
V18
XD_D7
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
XD_CD#
SP1
SP2
SP3
SP4
SP5
17
24
5IN1_LED# <29>
@
C982 1
1
2
2 10P_0402_50V8J
R856
10_0402_5%
@
CLK_SD_48M_R
2
1
CLK_SD_48M <18>
R857
0_0402_5%
JCR1
XDD4_SDD3_MSD1
XDD2_SDCMD
23
22
21
20
19
18
16
15
14
13
1
2
3
4
5
6
XDD0_SDCLK_MSD2
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1
+CARDPWR
XDD2_SDCMD
1
R858
XDD0_SDCLK_MSD2
XDWE#_SDCD#
@
2
0_0805_5%
30mil
1
R859
100K_0402_5%
RTS5138-GR_QFN24_4X4
XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2_MS_D5
XDDRY_SDWP_MSCLK
XDWE#_SDCD#
+SDPWR_MMCPWR
30mil
1
25
XDCE#_SDD1
XDCLE_SDD0
+SDPWR_MMCPWR
5IN1_LED#
U84
1
D3
CMD
VSS1
VDD
CLK
VSS2
7
8
9
10
11
D0
D1
D2
WP
CD
2
R854
EPAD
+3VS
2
C986
0.1U_0402_16V4Z
C987
0.1U_0402_16V4Z
1
1
2
2
C988
0.1U_0402_16V4Z
C987, C988 close to connector
Change to RTS5137 (SA000043500)
12
13
GND1
GND2
4
4
TAITW_PSDBTC09GLBS1N14N0
CONN@
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
MINI CARD / CardReader RTS5137
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
26
of
45
A
B
C
D
E
+3VALW
+USB_VCCA
1
C713
1
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
+USB_VCCA
R446
100K_0402_5%
80mil
1
8
7
6
5
2
U24
1
2
3
4
+
C712
R447 1
2 10K_0402_5%
USB_OC#0 <19>
220U_6.3V_M
C714
0.1U_0402_16V4Z
1
1
2
<33> SYSON#
+3VALW
C715
1
2
3
4
1
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
1
80mil
0_0402_5%
R449 @
0_0402_5%
1
2
USB20_N0
R450
100K_0402_5%
1
USB20_P0
<19> USB20_P0
4
USB_OC#2 <19>
JUSB1
1
2
4
3
2
1
2
3
4
5
6
7
8
USB20_N0_R
USB20_P0_R
3
WCM2012F2S-900T04_0805
2
U25
@
L83
<19> USB20_N0
+USB_VCCB
2
R448
1
W=80mils
2
470P_0402_50V7K
RT9715BGS_SO8
4.7U_0805_10V4Z
2
+5VALW
1
C711
2
+USB_VCCA
1
SVPE, 4.4m, 17mohm
+5VALW
1
2
R452
10K_0402_5%
RT9715BGS_SO8
4.7U_0805_10V4Z
2
USB_OC#1 <19>
1
2
1
2
R451
@
0_0402_5%
1
2
3
4
GND
GND
GND
GND
SUYIN_020133MB004S580ZL-C
CONN@
C716
0.1U_0402_16V4Z
SYSON#
D10
USB20_N0_R
2
+USB_VCCA
To USB/B Connector
4
3
5
2
6
USB20_P0_R
2
1
PJUSB208_SOT23-6
ESD Change P/N SC300000B00 For DVT
+USB_VCCB
(Port 1,2)
JUSB2
USB20_N2
USB20_P2
USB20_N1 <19>
USB20_P1 <19>
USB20_N2 <19>
USB20_P2 <19>
ACES_85201-1205N
CONN@
3
+3VALW
Bluetooth Conn.
+3VS
3
1
C718
3
G
BT@ 2
1
R453
10K_0402_5%
1
C720
2
BT@
C719
1U_0402_6.3V4Z
AO3413_SOT23-3
W=40mils
BT@
0.1U_0402_16V4Z
+BT_VCC
C721
+BT_VCC
BT@
Q24
2
D
<28> BT_ON#
S
BT@
0.1U_0402_16V4Z
1
BT@
C722
BT@
9
GND 8
7
6
5
4
3
2
GND 1
BT@
R454
300_0603_5%
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
JBT1
10
1
USB20_N1
USB20_P1
8
7
6
5
4
3
2
1
USB20_P7 <19>
USB20_N7 <19>
1
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
D
3
13
14
1
2
3
4
5
6
7
8
9
10
11
12
S
BT@
Q25
2N7002_SOT23
2
G
ACES_87213-0800G
CONN@
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
BlueTooth / Int USB x2 /eSATA
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
E
27
of
45
4
3
2
+3VALW
C726
KSO[0..17] <29>
KSI[0..7]
KSI[0..7]
2
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
C728
1000P_0402_50V7K
1
1
2
C729
1000P_0402_50V7K
<29>
Place on MiniCard door
JP7
1
2
3
4
1
2
3
4
E51RXD_P80CLK
E51TXD_P80DATA
ACES_85205-0400
@
65W /90W #
2
R458
VR_ON
<18> CLKRUN#
+5VS
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
TP_CLK
2
4.7K_0402_5%
TP_DATA
2
4.7K_0402_5%
1
R465
1
R466
C
R489
4.7K_0402_5%
1
@
+3VALW +3VS
2
2
For PVT 0602
@
R852
0_0402_5%
1
1
R851
0_0402_5%
EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
1
R467
1
R468
+3VALW
B
1
R471
1
R472
1
R473
1
R474
2
R475
1
R476
2
R497
@
EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW #
1
100K_0402_5%
EC_PME#
2
10K_0402_5%
PBTN_OUT#
1
100K_0402_5%
<35>
<35>
<8>
<8>
<19> PM_SLP_S3#
<19> PM_SLP_S5#
<19> EC_SMI#
<15> LOCAL_DIM
<26> MINI1_LED#
For LED INV_PWM freq to 1K
ENBKL
1
100K_0402_5%
LOCAL_DIM
1
100K_0402_5%
COLOY_ENG_EN
1
100K_0402_5%
2
R488
2
R844
2
R845
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<15> COLOY_ENG_EN
<15> EC_INVT_PW M
<32> FAN_SPEED1
<27> BT_ON#
<32> ON/OFF
<29> PW R_SUSP_LED
<29> W LAN_LED#
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LOCAL_DIM
MINI1_LED#
COLOY_ENG_EN
EC_INVT_PW M
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PW R_SUSP_LED
W LAN_LED#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
EC_CRY1
EC_CRY2
122
123
2
0_0402_5%
DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
PS2 Interface
97
98
99
109
3S/4S#
65W /90W #
VLDT_EN
LID_SW #
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPI Flash ROM
X1
1
C740
15P_0402_50V8J
Project_ID : 0-> NEW75/85/95
1-> PEW76/86/96
2-> PEW56(BA51)
100K_0402_5%
AD_PID0
TP_CLK
TP_DATA
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
3S/4S# <37>
65W /90W # <37>
VLDT_EN <33,39>
LID_SW # <29>
119
120
126
128
EC_SPICS#/FSEL#
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#
V18R
124
69
11
24
35
94
113
20mil
ECAGND 2
L85
1
BLM18AG601SN1D_2P
+3VALW
0_0402_5%
2
EC_SPICLK <29>
Ra
BATT_AMB_LED#
PW R_LED
SYSON
VR_ON
ACIN
2
AD_BID0
1
R470
Rb
8.2K_0402_5%
BATT_AMB_LED# <29>
PW R_LED <29>
Reserve
SYSON <33,38>
VR_ON <39,42>
ACIN <33,37>
2
C735
0.1U_0402_16V4Z
for EMI, close to EC
B
+3VS
EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON <32,36>
EC_SW I# <19>
@
2
R838
2
R839
EC_REV
BKOFF# <15>
W L_OFF# <26>
VGA_ON <33,41>
Board_ID : 0-> w/ pach code
1-> wo/ pach code
@
R469
100K_0402_5%
<29>
FSTCHG <37>
BATT_BLUE_LED# <29>
BATT_BLUE_LED#
1
KB926QFB1_LQFP128_14X14
0.1U_0402_16V4Z
Analog Board ID definition
C783
33P_0402_50V8K
@
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
XCLK1
XCLK0
C734
C
2
R419
EC_SI_SPI_SO <29>
EC_SO_SPI_SI <29>
1
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SW I#
EC_PW ROK
BKOFF#
W L_OFF#
EC_REV
GPI
1
R464
TP_CLK <29>
TP_DATA <29>
100
101
102
103
104
105
106
107
108
GPIO
SM Bus
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
Rb
8.2K_0402_5%
73
74
89
90
91
92
93
95
121
127
2
OSC
NC
4
OSC
1
NC
C739
EC_REV : 1-> D3
1
0-> E0
100K_0402_5%
1
100K_0402_5%
Delay SUSP# 10ms
VGATE <42>
ENBKL <13>
EAPD <30>
EC_THERM# <20>
SUSP# <33>
PBTN_OUT# <19>
EC_PME# <24>
EC_PW ROK 1
R254
2
0_0402_5%
SB_PW RGD <8,13,19>
C736
4.7U_0805_10V4Z
KB926 Rev:D3(SA00001J580)
KB926 Rev:E0(SA00001J5A0)
BATT_TEMP
C737
2
100P_0402_50V8J
1
ACIN
C741
2
100P_0402_50V8J
1
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
32.768KHZ_12.5PF_Q13MC14610002
2010/04/12
Issued Date
3
2
15P_0402_50V8J
R889
100K_0402_5%
@
2
1
2
A
For PVT 0602
EC_CRY2
Ra
EC_MUTE# <31>
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
1
EC_CRY1
+3VALW
DAC_BRIG <15>
EN_DFAN1 <32>
IREF <37>
CALIBRATE# <37>
SPI Device Interface
GND
GND
GND
GND
GND
@
Analog Project ID definition
ADP_I <37>
68
70
71
72
AGND
EC_CLK 1
R888
BATT_TEMP <35>
ADP_I
AD_BID0
AD_PID0
MB_SL
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
For Low PWR panel use
<18> EC_CLK
ECAGND
2
1
C731 0.01U_0402_16V7K
R463
DA Output
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
ACOFF <37,40>
BATT_TEMP
2
EC_SCI#
<19> EC_SCI#
1
2
@
R99
0_0402_5%
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
ACOFF
1
2
1
R462
47K_0402_5%
2
1
C733
0.1U_0402_16V4Z
2
+3VALW
AD
BEEP# <30>
2
<13,14,18> A_RST#
12
13
37
20
38
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
1
R460
BEEP#
1
LPC_CLK0_EC
<18,22> LPC_CLK0_EC
PWM Output
21
23
26
27
2
1
33_0402_5%
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
1
2
R461
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
2
@
1
2
3
4
5
7
8
10
1
100K_0402_5%
1
100K_0402_5%
2
4.7K_0402_5%
2
R459
1
C732
@ 22P_0402_50V8J
2
1
EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
D
+3VALW
4.7K_0402_5%
3S/4S#
<19> EC_GA20
<19> EC_KBRST#
<18> SERIRQ
<18> LPC_FRAME#
<18> LPC_AD3
<18> LPC_AD2
<18> LPC_AD1
<18> LPC_AD0
E51RXD_P80CLK <26>
E51TXD_P80DATA <26>
R491
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
U26
0.1U_0402_16V4Z
67
9
22
33
96
111
125
D
MB_SL
2
+3VALW
R109
0_0402_5%
@
C730
ECAGND
KSO[0..17]
C727
1
2+EC_VCCA
BLM18AG601SN1D_2P
1
2
1
0.1U_0402_16V4Z
1
2
2
0.1U_0402_16V4Z
1 C725
1
C724
For EC Tools
+3VS
L84
1
1
1
5
Deciphered Date
2010/10/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
EC ENE KB926
Size
B
Date:
Document Number
Rev
0.2
PEW96 LA-6552P
Monday, June 14, 2010
Sheet
1
28
of
45
To TP/B Conn.
+5VS
JTP1
2 0.1U_0402_16V4Z
+SPI_VCC
U27
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
EC_SPICLK_R
R481 1
2 0_0402_5%
C745
0.1U_0402_16V4Z
ACES_85201-0605N
CONN@
EC_SPICLK <28>
EC_SO_SPI_SI <28>
EC_SI_SPI_SO <28>
RIGHT_BTN#
MX25L1605DM2I-12G SOP 8P
SA00002TO00
LEFT_BTN#
SW1
SMT1-05-A_4P
3
1
RIGHT_BTN#
2
4
TP_CLK
LEFT_BTN#
TP_DATA
D11
2
5
6
4
SW2
SMT1-05-A_4P
3
1
2
1
3
7
4
+5VS
TP_CLK <28>
TP_DATA <28>
LEFT_BTN#
RIGHT_BTN#
3
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#
R480 1
R482 1
1
2
3
4
5
6
2
<28> EC_SPICS#/FSEL#
+3VALW
7
8
1
2
3
4
5
6
GND
GND
3
+3VALW
C742 1
2
0_0603_5%
5
6
1
R479
D13
PJDLC05C_SOT23-3
1
1
PJDLC05C_SOT23-3
JLED1
INT_KBD Conn.
KSI[0..7]
R486
C753 1
KSO12
C755 1
100P_0402_50V8J
KSO7
C750 1
2
100P_0402_50V8J
KSO6
C752 1
2
100P_0402_50V8J
KSO5
C754 1
KSO10
C761 1
KSI1
C763 1
2
100P_0402_50V8J
KSO4
C756 1
2
100P_0402_50V8J
KSO3
C758 1
2
100P_0402_50V8J
KSI4
C760 1
2
100P_0402_50V8J
KSO2
C762 1
2
100P_0402_50V8J
KSO1
C764 1
C769 1
2
100P_0402_50V8J
KSO0
C766 1
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
2
2.2K_0402_5%
+3VALW
1
R478
2
2
3.9K_0402_5%
+3VALW
1
R499
2
2
2.2K_0402_5%
+3VALW
1
R498
2
2
3.9K_0402_5%
B
1
PWR_LED#
LED2
HT-191UD5_AMBER
A
1
PWR_SUSP_LED#
LED3
HT-191NB5_BLUE
PWR_SUSP_LED#
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
B
1
BATT_BLUE_LED#
BATT_BLUE_LED# <28>
@
2
100P_0402_50V8J
KSI5
C768 1
2
100P_0402_50V8J
KSI6
C770 1
@
@
C771 1
100P_0402_50V8J
R487
100K_0402_5%
@
@
KSO8
2
1
R477
@
@
C767 1
100P_0402_50V8J
+3VS
@
@
KSI3
2
2
<28> PWR_LED
@
@
KSO9
100P_0402_50V8J
LED1
HT-191NB5_BLUE
DMN66D0LDW-7_SOT363-6
Q26A
@
@
C765 1
2
@
@
KSI2
2
100P_0402_50V8J
SATA_LED# <20>
NC7SZ08P5X_NL_SC70-5
PWR_LED#
@
@
C759 1
100P_0402_50V8J
5IN1_LED# <26>
1
@
@
KSO11
100P_0402_50V8J
2
1
5
2
@
C757 1
100P_0402_50V8J
2
@
@
KSI0
A
Y
1
KSO13
2
@
KSO17 C748 1
3
C751 1
100K_0402_5%
U29
2
B
2
100P_0402_50V8J
KSI7
C772 1
2
100P_0402_50V8J
A
1
BATT_AMB_LED#
BATT_AMB_LED# <28>
@
1
@
R490
100K_0402_5%
LED4
HT-191UD5_AMBER
DMN66D0LDW-7_SOT363-6
Q26B
5
<28> PWR_SUSP_LED
@
4
KSO14
4
P
MEDIA_LED#
2
C749 1
Pop R486 for RTS5137
2
+3VS
1
KSO15
KSO[0..17] <28>
+3VS
KSO16 C747 1
ACES_88747-2601
CONN@
ON/OFFBTN# <32>
ACES_85201-08051
CONN@
KSI[0..7] <28>
KSO[0..17]
+3VS
PWR_LED#
ON/OFFBTN#
3
G2
G1
+3VALW
LID_SW# <28>
WLAN_LED# <28>
LID_SW#
WLAN_LED#
MEDIA_LED#
6
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
28
27
2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10
G
JKB1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
1
2
3
4
5
6
7
8
GND
GND
For PVT 0608 Unpop Cap.
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
BIOS, I/O Port & K/B Connector
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
29
of
45
A
B
C
+3VS
D
E
F
G
1
R784
+VDDA
2
0_0805_5%
1
1
1
+5VAMP
2
2
2
1
1
R786
1
2
HD Audio Codec
2
C
2
@
2.4K_0402_1%
Q72
2
B
2
1
2
2
3
0.1U_0402_16V4Z
2
FBMA-L11-201209-221LMA30T_0805
MONO_IN
2
1
0.1U_0402_16V4Z
C936
1
1U_0402_6.3V4Z
1
22U_0805_6.3V6M
C952 1
1U_0402_6.3V4Z
<28> BEEP#
R787
FBMA-L11-201209-221LMA30T_0805
L88 1
2
1
C947
CH751H-40PT_SOD323-2
1
U81
60mil
2
C899
R789
10K_0402_5%
1
C678
D38
L87
+5VS
R783
20K_0402_1%
H
40mil
IN
OUT
5
4.75V
+VDDA
GND
SHDN
BYP
4
1
2
C949
0.01U_0402_25V7K
@ G9191-475T1U_SOT23-5
1
(output = 300 mA)
E
3
560_0402_5%
2SC2411KT146_SOT23-3
<19> SB_SPKR
2
1
R788
2
560_0402_5%
1
C946 1
1U_0402_6.3V4Z
D37
CH751H-40PT_SOD323-2
L82
BLM18AG601SN1D_2P
1
2
2
1
+AVDD_HDA
2
19
MIC1_C_R
2
4.7U_0805_10V4Z
MONO_IN
<31> MIC_PLUG#
<31> HP_PLUG#
R794 2
R795 2
1 20K_0402_1%
1 5.11K_0402_1%
1
R796
<28> EAPD
SENSE_A
SENSE_B
2
0_0402_5%
2
3
13
34
47
48
4
7
9
DMIC_CLK1/2
46
LINE1_VREFO
NC
LINE2_VREFO
DMIC_CLK3/4
MIC2_VREFO
BITCLK
SDATA_IN
PCBEEP_IN
MONO_OUT
CBP
RESET#
CPVEE
SYNC
MIC1_VREFO
SDATA_OUT
HPOUT_R
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B
EAPD
SPDIFO1
3
1
R792
2 C948
22P_0402_50V8J
2
1
0_0402_5%
1
R793
2
33_0402_5%
C951
28
32
2.2U_0805_10V6K
2
1
2
MIC1_VREFO
HP_RIGHT
1
CODEC_VREF
1
HP_LEFT
26
42
HP_RIGHT
C954
2.2U_0805_10V6K
SENSE A
4
SENSE B
39.2K
PORT-A (PIN 39, 41)
LOUT2
PORT-B (PIN 21, 22)
MIC1
10K
PORT-C (PIN 23, 24)
LINE1
5.1K
PORT-D (PIN 35, 36)
LOUT1
39.2K
PORT-E (PIN 14, 15)
LINE2
20K
PORT-F (PIN 16, 17)
MIC2
2
1
2
PORT-I (PIN 32, 33)
HP
HP_LEFT <31>
J4
J1
1
AGND
1
2
2
1
Issued Date
JUMP_43X39 @
J6
1 1
2 2
JUMP_43X39 @
JUMP_43X39 @
GNDA
GND
C
D
E
4
Title
HD Audio Codec ALC272X
Document Number
F
Rev
0.2
PEW96 LA-6552P
Date:
B
GNDA
Compal Electronics, Inc.
2010/10/12
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2
JUMP_43X39 @
J3
1
2 2
Compal Secret Data
2010/04/12
2
JUMP_43X39 @
J5
1 1
2 2
GND
Security Classification
1
JUMP_43X39 @
J2
1 1
2 2
1
10K
5.1K
HP_RIGHT <31>
HP_LEFT
10mil
40
33
3
10mil
Function
20K
D27 @
PJDLC05C_SOT23-3
HDA_SDIN0 <19>
ALC272X
Codec Signals
G1
G2
ACES_88266-02001
CONN@
29
31
ALC272-VA2-GR_LQFP48_7X7
Impedance
3
4
C980
2
For EMI
Change to ALC272X
Sense Pin
1
2
HDA_BITCLK_AUDIO <19>
8
27
DGND
C979
2
1
2
37
CBN
AVSS1
AVSS2
DMIC_CLK <15>
6
VREF
HPOUT_L
DVSS1
DVSS2
44
30
JDREF
DMIC_CLK
1
220P_0402_50V7K
43
JMIC2
0_0603_5% R849
1
2
1
2
0_0603_5% R850
1
220P_0402_50V7K
INT_MIC
15mil
2
1
DVDD
LINE1_R
MIC1_R
12
5
DMIC_DATA
SPDIFO2
MIC1_L
<19> HDA_SDOUT_AUDIO
<15> DMIC_DATA
LINE1_L
45
22
10
<19> HDA_SYNC_AUDIO
41
21
11
<19> HDA_RST_AUDIO#
3
LOUT2_R
1
1
C932
MIC2_R
C808
220P_0402_50V7K
AMP_RIGHT <31>
C937
MIC1_R
<31> MIC1_R
AMP_RIGHT
39
0.1U_0402_16V4Z
<31> MIC1_L
36
LOUT2_L
2
AMP_LEFT <31>
10U_0805_10V4Z
20
C934 1
LOUT_R
MIC2_L
17
18
MIC1_L
LINE2_R
16
24
4.7U_0805_10V4Z
MIC1_C_L
2
AMP_LEFT
15
2
1
35
LINE2_L
Close to Conn
INT_MIC
LOUT1_L
14
23
MIC2_VREFO
R585
2.2K_0402_5%
C927
MIC2_C_R
2
4.7U_0805_10V4Z
U82
1
1
C797
MIC2_VREFO
10U_0805_10V4Z
20K_0402_1%
2
R523
4.7U_0805_10V4Z
MIC2_C_L
2
1
1INT_MIC_2
1K_0402_1%
2
R797
C794
INT_MIC
2
+3VS
C926
C945
2
0.1U_0402_16V4Z
DVDD_IO
2
1
C953
0.1U_0402_16V4Z
38
2
1
25
C950
10U_0805_10V4Z
2
2
AVDD1
1
2
BLM18AG601SN1D_2P
+VDDA
40mil
AVDD2
0.1U_0402_16V4Z
1
1
C935
1
C933
2
L86
+3VS_DVDD
0.1U_0402_16V4Z
1
10mil
Friday, June 11, 2010
G
Sheet
30
H
of
45
A
B
GAIN0 GAIN1 AV(inv)
0
0
6dB
0
1
10dB
1
0
15.6dB
1
1
21.6dB
Ri
90k
70k
45k
25k
C
D
E
+5VAMP
0.1U_0402_16V4Z
1
C959
10U_0805_10V4Z
Int. Speaker Conn.
1
C960
2
2
+5VAMP
1
<30> AMP_LEFT
2
1
0.47U_0603_10V7K R828
9
AMP_C_LEFT
2
0_0603_5%
5
EC_MUTE#
19
18
SPKR+
ROUT-
14
SPKR-
LOUT+
4
SPKL+
LOUT-
8
SPKL-
@ R825
100K_0402_5%
R826
100K_0402_5%
JSPK1
SPKR+
SPKR-
R831 1
R832 1
SPK_R+
SPK_R-
2 0_0603_5%
2 0_0603_5%
20mil
LIN+
LIN-
ACES_88266-02001
CONN@
1
ROUT+
2
GAIN1
1
3
2
GAIN1
Left
G1
G2
1
2
1
2
3
4
G1
G2
2
2 0.47U_0603_10V7K
1
1
16
15
6
RIN-
GAIN0
GAIN0
1
2
D41
PJDLC05C_SOT23-3
Right
ACES_88266-02001
CONN@
1
C971
AMP_C_RIGHT 17
2
0_0603_5%
3
4
PJDLC05C_SOT23-3
2
3
C955 1
RIN+
D39
2
C957
2
1
0.47U_0603_10V7K R830
7
1
1
<30> AMP_RIGHT
2 0.47U_0603_10V7K
1
2
@ R829
100K_0402_5%
2
C958 1
1
JSPK2
SPK_L+
SPK_L-
2 0_0603_5%
2 0_0603_5%
20mil
R827
100K_0402_5%
VDD
PVDD1
PVDD2
U83
R834 1
R833 1
2
SPKL+
SPKL-
10 dB
3
1
NC
12
BYPASS
10
2
SHUTDOWN
2
Keep 10 mil width
2
GND5
GND1
GND2
GND3
GND4
<28> EC_MUTE#
C956
0.47U_0603_10V7K
21
20
13
11
1
1
TPA6017A2_TSSOP20
C779
330P_0402_50V7K
<30> HP_LEFT
R686 1
2 56.2_0603_1%
HPOUT_L_1
<30> HP_RIGHT
R685 1
2 56.2_0603_1%
HPOUT_R_1
1
L94
1
L93
2
1
2
C774
Headphone Out
330P_0402_50V7K
1
JHP1
1
2
HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P
3
4
<30> HP_PLUG#
HP_PLUG#
5
6
SINGA_2SJ-0960-C01
CONN@
3
MIC_PLUG#
3
2
2
1
1 1
2
MIC1_R_R
1
C780
220P_0402_50V7K
JMIC1
1
2
MIC1_L_R
3
2
2
R695 1
4.7K_0402_5%
L89 1
2
FBMA-L11-160808-700LMT_2P
L90 1
2
FBMA-L11-160808-700LMT_2P
3
<30> MIC1_R
MIC1_L_1
2
1K_0603_1%
MIC1_R_1
2
1K_0603_1%
MIC JACK
R693
2
R692
4.7K_0402_5%
R694 1
@
D24
PJDLC05C_SOT23-3
D42
CH751H-40PT_SOD323-2
1 1
D43
CH751H-40PT_SOD323-2
<30> MIC1_L
2
3
HP_PLUG#
MIC1_VREFO MIC1_VREFO
1
2
C781
220P_0402_50V7K
@
D29
<30> MIC_PLUG#
4
MIC_PLUG#
5
PJDLC05C_SOT23-3
6
4
4
1
SINGA_2SJ-A960-C01
CONN@
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Amplifier & Audio Jack
Document Number
Rev
0.2
PEW96 LA-6552P
Sheet
Friday, June 11, 2010
E
31
of
45
ON/OFF switch
FAN1 Conn
D25
1SS355_SOD323-2
2
@ 10K_0603_5%
2
1
R494
R495
8
7
6
5
2
C823
10U_0805_10V4Z
1
2
APL5607KI-TRG_SO8
+3VS
ON/OFF <28>
3
51ON# <34>
1
DAN202UT106_SC70-3
<28> FAN_SPEED1
1
C825
1000P_0402_50V7K
1
2
3
G1
G2
EC_ON
<28,36> EC_ON
S 2N7002_SOT23
Q27
R496
4
5
D
2
G
2
JFAN1
1
2
3
Change to SC600000B00
10K_0402_5%
CONN@
ACES_85204-03001
1
2
+VCC_FAN1
2
1000P_0402_50V7K
1
R568
10K_0402_5%
40mil
C773
ON/OFFBTN# <29>
C824
1000P_0402_50V7K
1
2
1
2
FIDUCIAL_C40M80
FIDUCIAL_C40M80
2010/04/12
Deciphered Date
H23
H_4P2
H13
H_3P0N
1
H17
H_3P0X3P5N
1
H22
H_4P2
1
1
H10
H_3P0
1
1
H21
H_4P2
FD3
FD4
FIDUCIAL_C40M80
FIDUCIAL_C40M80
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
FD2
1
1
FD1
H8
H_3P0
1
1
H18
H_3P4
H20
H_4P2
1
H24
H_3P0
1
H19
H_3P0
1
1
H11
H_3P0
H7
H_3P0
1
H5
H_3P0
1
H4
H_3P0
1
0.01U_0402_25V4Z
ON/OFFBTN#
4
1
C822
@
2
GND
GND
GND
GND
2
1
2
0_0402_5% 1
EN
VIN
VOUT
VSET
D12
6
5
1
2
3
4
SW3
SMT1-05-A_4P
1
3
@ D26 BAS16_SOT23-3
@D26
1
2
1
2
U35
1
100K_0402_5%
Bottom Side
1
1
R567
2
@ 10K_0603_5%
3
2
1
10U_0805_10V4Z
2
@
+VCC_FAN1
<28> EN_DFAN1
1
R493
R566
0_0603_5%
@
+3VALW
TOP Side
+5VS
+5VS
C821
1
Power Button
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
FAN & Screw Hole & PBTN
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
32
of
45
A
B
C
+5VALW TO +5VS
E
+5VALW
+1.1VALW TO +1.1VS
+5VS
+1.1VALW
2
+5VALW
D
+1.1VS
R570
100K_0402_5%
U36
D
+3VS
+3VALW
S
2
2
R576
100K_0402_5%
Q48
@
2N7002_SOT23
1
1
2
3
4
C832
SI4800BDY_SO8
1
R575
D
2
1
R503 47K_0402_5%
2
G
Q34
S
2N7002_SOT23
1
3
VGA_ON#
C848
0.22U_0603_16V4Z2
2
2
470_0603_5%
R583
100K_0402_5%
S
@
D
S
ACIN 2
G
2 VGA_ON#
G
Q32
2N7002_SOT23
VLDT_EN#
<28,39> VLDT_EN
1
2
C835
0.1U_0603_25V7K
1
D
1.5VSG_GATE
2
100K_0402_5%
1
+VSB
2
10U_0805_10V4Z
+5VALW
R572
1
10U_0805_10V4Z
C833
1
2
0.1U_0603_25V7K
1
3
C843
1
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
2
S
S
S
G
2
D
D
D
D
1
2
C831
1
D
S
Q40
2N7002_SOT23
2
G
R584
10K_0402_5%
2
1
8
7
6
5
R596
S
Q35
2N7002_SOT23
1
3
1
S
U37
2 SUSP
G
Q36
2N7002_SOT23
C830
D
D
2
G
R580
10K_0402_5%
+1.5VS
2
3
+1.5V
D
S
SUSP
2
Q38G
2N7002_SOT23
SUSP
<40> SUSP
+1.5V to +1.5VS
R579
470_0603_5%
3VS_GATE
1
200K_0402_5%
1
2
2
R582
1
510K_0402_5%
10U_0805_10V4Z
2
2
10U_0805_10V4Z
+VSB
1
10U_0805_10V4Z
C836
2
2
1U_0402_6.3V4Z
1
2
0.1U_0603_25V7K
2
C842
SI4800BDY_SO8
1
1
C841
1
2
3
4
3
1
S
S
S
G
3
+5VALW
<28> SUSP#
1 1
C840
D
D
D
D
1
C844
U39
8
7
6
5
S
Q30
2N7002_SOT23
R573
100K_0402_5%
2 VLDT_EN#
G
Q37
2N7002_SOT23
D
2
G
1
@
ACIN 2
G
<28,37> ACIN
<28,38> SYSON
1
S
S
1
SYSON#
<27> SYSON#
470_0603_5%
3
VLDT_EN# 2
Q39G
2N7002_SOT23
+3VALW TO +3VS
D
1
0.1U_0603_25V7K
R595
2
Q33G
2N7002_SOT23
1.1VS_GATE
2
47K_0402_5%
510K_0402_5%
2
1
R581
C834
1 2
S
+VSB
R578
D
3
1
SUSP
1
D
2 SUSP
G
Q31
2N7002_SOT23
2
10U_0805_10V4Z
3
1
3
S
1
1
5VS_GATE
2
100K_0402_5%
3
1
R574
1
10U_0805_10V4Z
C839
2
2
1U_0402_6.3V4Z
3
1
C838
SI4800BDY_SO8
1
D
1
2
R577
C837
1K_0402_5%
1
R571
470_0603_5%
1
10U_0805_10V4Z
2
2
10U_0805_10V4Z
1
2
3
4
S
S
S
G
3
1
1
1
C829
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
D
D
D
D
1
2
C827
SI4800BDY_SO8
+VSB
8
7
6
5
1
U38
1
2
3
4
S
S
S
G
2
1
C828
D
D
D
D
1
1
C826
8
7
6
5
Q49
@
2N7002_SOT23
2
+5VALW
R587
100K_0402_5%
+CPU_VDDR
+NB_CORE
+1.8VS
1
1
+0.75VS
S
Q42
2N7002_SOT23
2
G
R586
10K_0402_5%
+1.5V
2
2
S
1
+5VS
1
1
1
1
S
R605
470_0603_5%
D
VGA_ON#
2
G
Q46
2N7002_SOT23
S
3
S
D
2 VLDT_EN#
G
Q69
2N7002_SOT23
3
S
R592
470_0603_5%
D
2 VLDT_EN#
G
Q56
2N7002_SOT23
3
D
2 SUSP
G
2N7002_SOT23
Q45
R610
470_0603_5%
1
1
1
1
R604
470_0603_5%
3
3
D
2 SUSP
G
Q44
2N7002_SOT23
3
D
S
R591
470_0603_5%
1
1
1
R590
470_0603_5%
2
2
2
2
2
+2.5VS
D
3
VGA_ON#
<28,41> VGA_ON
3
1
3
2 SYSON#
G
Q57
2N7002_SOT23
1
C972
1
C973
1
1
C974
C975
1
C976
1
C977
1
C978
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/10/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
DC Interface
Document Number
Rev
0.2
PEW96 LA-6552P
Sheet
Friday, June 11, 2010
E
33
of
45
A
B
C
D
1
1
DC-IN cable: DC301009W00 (Yellow)
VIN
SP02000GC00
ACES_50305-00441-001
2
PC4
100P_0402_50V8J
1
PC5
100P_0402_50V8J
2
1
PC3
1000P_0402_50V7K
2
2
PJP1
1
PL1
SMB3025500YA_2P
1
2
DC_IN_S1
1
2
3
4
5
6
1
1
2
3
4
GND
GND
PC6
1000P_0402_50V7K
2
2
PJ1
1
+3VALWP
1
2
PJ22
2
+3VALW
2
PD2
RLS4148_LL34-2
1
1
3
<32> 51ON#
1
2
2
2
+1.1VALW
PJ11
2
+VSB
1
+0.75VSP
1
2
2
+0.75VS
3
JUMP_43X118
(3A,120mils ,Via NO.=6)
2
2
1
(7A,280mils ,Via NO.=14)
(120mA,40mils ,Via NO.= 2)
PJ8
VS
1
+NB_COREP
1
2
+1.5VP
2
+NB_CORE
1
1
2
+1.5V
2
JUMP_43X118
1
JUMP_43X118
PJ19
PC14
0.1U_0603_25V7K
1
1
2
2
JUMP_43X118
2
2
1
2
PR14
22K_0402_1%
1
2
PC13
0.22U_0603_25V7K
1
+1.1VALWP
PJ6
1
2
PR13
100K_0402_1%
+5VALW
JUMP_43X39
1
2
PJ26
2
(5A,200mils ,Via NO.= 10)
1
1
1
BATT+
PQ1
TP0610K-T1-E3_SOT23-3
N1
PR11
68_1206_5%
+1.8VS
JUMP_43X118
1
+VSBP
2
JUMP_43X118
PJ5
PR10
68_1206_5%
PD3
RLS4148_LL34-2
2
2
(3A,120mils ,Via NO.=6)
PJ3
1
+5VALWP
3
1
JUMP_43X118
(3.9A,160mils ,Via NO.= 8)
VIN
1
+1.8VSP
JUMP_43X118
(7.09A,300mils ,Via NO.=16)
(8.1A,320mils ,Via NO.=17)
PJ9
+2.5VSP
1
1
2
2
+2.5VS
2
+CPU_VDDR
JUMP_43X39
+3VLP
PJ21
+CHGRTC
4
1
+CPU_VDDRP
PR16
0_0603_5%
2
1
2
JUMP_43X39
(1.5A,40mils ,Via NO.= 3)
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
B
C
DCIN & DETECTOR
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
D
34
of
45
A
B
C
D
PH1 under CPU botten side : Not SPEC, reference only!
CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
1
7
3
OT1 TMSNS2
6
OT2 RHYST2
5
2
1
1
2
8
GND RHYST1
4
EC_SMB_CK1 <28>
PC19
0.01U_0402_25V7K
@ PR169
47K_0402_1%
1
2
G718TM1U_SOT23-8
PR261
1K_0402_5%
MAINPW ON <8,36>
PR24
6.49K_0402_1%
2
1
+3VALW P
PH1
1
1
2
PC20
1000P_0402_50V7K
VCC TMSNS1
2
1
1
2
<40,41>
BATT+
1
@ PR21
100K_0402_1%
PR30
9.53K_0402_1%
1
2
100K_0402_1%_NCP15W F104F03RC
100K_0402_1%_NCP15W F104F03RC
2
2
PC22
1U_0402_6.3V6K
PH2 @
2
PR33
1K_0402_1%
2
PL2
SMB3025500YA_2P
1
2
BATT_S1
EC_SMB_DA1 <28>
2
2
PR32
100_0402_1%
1
CONN@
PU3
1
PJP2
SUYIN_200275GR008G13GZR
PR28
21K_0402_1%
PR27
10K_0402_1%
1
<40,41>
VMB
PC21
0.1U_0402_10V7K
1
PR29
100_0402_1%
2
2
EC_SMCA
TH
PI
1
VL
EC_SMDA
1
10
9
8
7
6
5
4
3
2
1
2
GND
GND
8
7
6
5
4
3
2
1
1
1
2
2
BATT_TEMP <28>
PQ3
TP0610K-T1-E3_SOT23-3
2
VL
1
1
2
2
PR34
100K_0402_1%
3
+VSBP
1
PC25
0.1U_0603_25V7K
3
2
1
1
B+
PC24
0.22U_0603_25V7K
3
2
2
PR36
22K_0402_1%
PR39
1K_0402_5%
2
1
1
D
S
PQ4
2N7002W -T/R7_SOT323-3
2
G
1
<36,38> SPOK
3
1
PR38
100K_0402_1%
2
1U_0402_6.3V6K
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Deciphered Date
2010/10/12
Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
D
35
of
45
5
4
3
2
1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
PC344
1U_0603_10V6K
2VREF_8205
RT8205_B+
Typ: 175mA
PR266
20K_0402_1%
1
2
PR267
20K_0402_1%
1
2
20
LX_5V
LGATE2
LGATE1
19
LG_5V
1
2
1
4
2
PQ62
AO4712_SO8
3
2
1
RT8205_B+
1
2VREF_8205
S
PC360
4.7U_0805_10V6K
2
1
VL
Typ: 175mA
PR273
4.7_1206_5%
5
6
7
8
RT8205EGQW _W QFN24_4X4
+5VALWP
1
PC356
220U_6.3V_M
PC358
680P_0402_50V7K
NC
PL35
10UH_MSCDRI-104A-100M-E_4.6A_20%
1
2
18
VIN
VREG5
17
GND
3
2
1
PHASE1
13
5
6
7
8
PC350
2200P_0402_50V7K
2
1
PC349
10U_1206_25V6M
2
1
ENTRIP1
2
UG_5V
PHASE2
2
PC361
0.1U_0603_25V7K
4
1
1
3
PC23
1U_0402_6.3V6K
1
2
S
PC363
2.2U_0603_10V7K
2
1
1
D
2
G
PQ63B
DMN66D0LDW -7_SOT363-6
PQ64
PDTC115EU_SOT323
2
3
PR288
200K_0402_1%
1
2
1
<37> ACPRN
D
5
G
C
+
2
RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)
B
TPS51125A
TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.902A (Freq=305KHz)
Iocp = 7.108A ~ 8.34A
5VALWP Delta I = 3.199A (Freq=245KHz)
Iocp = 8.74A ~ 10.16A
1
PR276
100K_0402_1%
2
PR277
100K_0402_1%
2
1
PR278
40.2K_0402_1%
1
VS
1
FB1
22
21
EN
3
6
2
S
<8,35> MAINPWON
ENTRIP1
REF
3
4
TONSEL
BOOT1
PC359
1U_0603_10V6K
2
1
1
2
PR275
100K_0402_1%
ENTRIP2
PQ60
AO4466_SO8
4
SPOK <35,38>
B+
G
2
23
UGATE1
PR274
499K_0402_1%
1
2
D
PR279
0_0402_5%
1
2
PGOOD
VFB=2.0V
B
VL
VO1
24
UGATE2
BOOT2
4
ENTRIP1
PQ63A
DMN66D0LDW -7_SOT363-6
PR269
154K_0402_1%
1
2
PR271 PC354
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2
16
12
5
6
VREG3
15
8
7
6
5
LG_3V
1
2
3
2
VO2
8
1
2 1
2 BST_3V 9
2.2_0603_5%
UG_3V 10
PC353
0.1U_0603_25V7K
LX_3V
11
PQ61
AO4712_SO8
PC357
680P_0402_50V7K
2
1
+
7
SKIPSEL
PR270
1
2
3
1
PC355
220U_6.3V_M
P PAD
FB2
1
25
1
PR272
4.7_1206_5%
2
1
2
ENTRIP2
PU19
PL34
4.7UH_SIL104R-4R7PF_5.7A_30%
+3VALWP
ENTRIP2
RT8205_B+
PR268
133K_0402_1%
1
2
2
C
PC352
4.7U_0805_10V6K
8
7
6
5
PC348
2200P_0402_50V7K
2
1
PQ59
AO4466_SO8
4
1
PR265
30.9K_0402_1%
1
2
+3VLP
2
PC347
10U_1206_25V6M
2
1
1
PC351
1000P_0402_50V7K
2
1
PC362
0.1U_0402_25V6
2
1
B+
PR264
13K_0402_1%
1
2
14
PL36
FBMA-L11-322513-151LMA50T_1210
D
2
D
+3.3VALWP Ipeak=5.629A ; Imax=3.940A
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(10E-06 * 133K)/10=133mV
Ilimit=133mV/(18m*1.2) ~ 133mV/(15m*1.2)
=6.157A ~ 7.389A
Iocp=Ilimit+Delta I/2
=6.931A ~ 8.162A
Delta I=1.547A (Freq=375KHz)
+5VALWP Ipeak=5.875A ; Imax=4.113A
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(10E-06 * 154K)/10=154mV
Ilimit=154mV/(18m*1.2) ~ 154mV/(15m*1.2)
=7.14A ~ 8.56A
Iocp=Ilimit+Delta I/2
=8.44A ~ 9.86A
Delta I=2.613A (Freq=300KHz)
PQ65
2N7002W -T/R7_SOT323-3
A
<28,32> EC_ON
A
2
PQ66
PDTC115EU_SOT323
2010/04/12
3
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/12
Title
+5VALWP/+3VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
36
of
45
B
1
CSIP
19
PHASE
18
VCOMP
7
ICM
4
2
1
1
2
1
PQ54
2N7002W -T/R7_SOT323-3
2
65W/90W#
G
D
S
16
2
PC59
0.1U_0603_25V7K
BST_CHGA 2
1
VDDP
11
VADJ
LGATE
14
12
GND
PGND
13
PD12
RB751V-40TE17_SOD323-2
6251VDDP
DL_CHG
26251VDD
1
2
ACLIM
15
2
10
1
S
<40,41>
DH_CHG
PR82
0_0603_5%
BST_CHG 1
2
PQ24
2N7002W -T/R7_SOT323-3
PR78
0.02_1206_1%
CHG1
4
2
BATT+
3
PQ57
@
AO4466_SO8
2
BOOT
2 PACIN
G
@ PQ23
2N7002W -T/R7_SOT323-3
D
ACPRN 2
G
PL5
10UH_PCMB104T-100MS_6A_20%
1
2
4
1
CHLIM
17
S
@
4
3
2
1
9
UGATE
1
VREF
1
1
12.1K_0402_1%
3
3
<28>
6251aclim
PR87
20K_0402_1%
2
2
2
8
PR84
6251VREF 1
2
ACOFF
PR83
100K_0402_1%
PR85
2.55K_0402_1%
<28,40> ACOFF
<28> IREF
0.1U_0402_16V7K
2
1
PC60
0.01U_0402_25V7K
2
1
PQ53
PDTC115EU_SOT323
6251VREF
PC58
1
2
PR81
80.6K_0402_1%
2
1
1
PR79
47K_0402_5%
1
2
1
PACIN
<28> ADP_I
D
3
3
PQ55
AO4466_SO8
PC52
0.1U_0603_25V7K
2
1
20
PR283
VIN1 100K_0402_1%
1
2
CSIN
CSOP
1
ICOMP
6
CSON
PC53
0.047U_0603_16V7K
1
2
PR73
20_0402_5%
2
1
PR74
PC129
20_0402_5%
0.1U_0603_25V7K
1
2
PR76
2_0402_5%
LX_CHG
3
CSOP
2
2
CELLS
VIN
PR86
4.7_0603_5%
PC63
10U_1206_25V6M
2
1
PC55
0.01U_0402_25V7K
1 1
2
1 1
PR77
100_0402_1%
1
2
S
5
22
21
@ PR67
200K_0402_1%
1
2
PC68
10U_1206_25V6M
2
1
2
PC54
6800P_0402_25V7K
1
2
PR75
10K_0402_1%
1
2
CSON
5
6
7
8
4
1
EN
4
PR72
20_0402_5%
1
2
1
PQ68B
DMN66D0LDW -7_SOT363-6
1
S
3
ACPRN
PR80
3.3_1206_5%
D
5
G
23
PC57
2200P_0402_50V7K
2
1
2
3
3
6
PQ68A
DMN66D0LDW -7_SOT363-6
2
G
ACSET ACPRN
2
2
D
2
2
6251_EN
24
@ PD17
BAS40CW _SOT323-3
3 ACOFF
2 1
2
5
6
7
8
<28> 3S/4S#
DCIN
3
2
1
3
2
PQ35
PDTC115EU_SOT323
VDD
VIN
PR65
10K_0402_1%
PR282
14.3K_0402_1%
PC127
0.1U_0603_25V7K
DCIN
2
1
1
PR63
47K_0402_1%
1
2
PQ20
PDTC115EU_SOT323
1
PR69
150K_0402_1%
2
1
8
7
6
5
ACSETIN
PC364
1000P_0402_50V7K
2
PR70 47K_0402_5%
2
1
PR281
10_1206_5%
PU5
2
1
PR71
100K_0402_1%
1
1
6251VDD
PR280
191K_0402_1%
PD16
RB751V-40_SOD323-2
ACSETIN
1
1
<28> FSTCHG
PQ21
PDTC115EU_SOT323
PreCHG
PC61
2200P_0402_50V7K
2
1
VIN
PR68
0_0402_5%
2
1
1
2
3
PC48
0.1U_0603_25V7K
2
1
CSIP
47K
PQ16
AO4407A_SO8
2
CSIN
PC49
2.2U_0603_6.3V6K
2
1
PR94
200K_0402_1%
1
PC51
10U_1206_25V6M
2
1
3
PC56
5600P_0402_25V7K
1
2
1
3
2
2
2
CHG_B+
PL37
FBMA-L11-322513-151LMA50T_1210
6251VDD
VIN1
4
PQ19
PDTA144EU_SOT323-3
47K
2
PC62
0.1U_0603_25V7K
2
1
1
PR62
200K_0402_1%
1
PC50
10U_1206_25V6M
2
1
8
7
6
5
4
1
B+
PR61
0.02_2512_1%
P3
PQ15
AO4407A_SO8
1
2
3
B+
1
P2
1
2
3
4
8
7
6
5
CP = 85%*Iada ; CP = 2.91A
CP = 85%*Iada ; CP = 4.07A
ADP_I = 19.9*Iadapter*Rsense
PQ14
AO4407A_SO8
VIN
D
2
Iada=0~3.42A(65W/19V=3.421A)
Iada=0~4.74A(90W/19V=4.736A)
C
PC128
220P_0402_50V7K
A
@
PC64
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
3
3
CP= 85%*Iada; CP=2.91A
<28> CALIBRATE#
6251VDD
PR90
31.6K_0402_1%
1
CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.464V (90W), Iinput=4.03A
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A
PR84=12.1K;PR85=2.55K
PR284
10K_0402_1%
1
2
1
Iada=0~3.42A(65W)
PR88
15.4K_0402_1%
1
2
2
CP= 85%*Iada; CP=4.03A
1
Iada=0~4.74A(90W)
ACIN <28,33>
PR286
10K_0402_1%
2
PR285
47K_0402_1%
1
1
2
PACIN
PR287
14.3K_0402_1%
CC=0.6~4.48A
2
PQ67
PDTC115EU_SOT323
3
IREF=1.016*Icharge
2
<36> ACPRN
IREF=0.43V~3.24V
4
4
BATT Type
Charging Voltage
(0x15)
CV mode
12600mV
12.60V
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Normal 3S LI-ON Cells
2010/04/12
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
-
Date:
A
B
C
CHARGER
Rev
0.1
Friday, June 11, 2010
Sheet
D
37
of
45
A
B
C
D
PR96
255K_0402_1%
1
2
11
VDDP
10
LGATE
DL_1.1VALW
9
1
+ PC76
330U_6.3V_M
4
2
S IC G5603RU1U TQFN 14P PW M
PC80
4.7U_0805_10V6K
2
PC78
680P_0603_50V7K
PR103
4.7K_0402_1%
2
1
2
2
1
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=7.42A, Imax=5.2A, Iocp=8.9A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V
Rcs=Vtrip/9uA=0.065V/9uA=7.2K
choose Rcs=7.32K
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A
Iocp=10A~19A
2
PR104
8.45K_0402_1%
PL32
FBMA-L11-322513-151LMA50T_1210
1
1
B+
PC83
2200P_0402_50V7K
2
1
2
5
6
7
8
2
PQ27
AO4466_SO8
4
VDDP
10
2
PR112
13K_0402_1%
FB
9
DL_1.5V
LGATE
4
S IC G5603RU1U TQFN 14P PW M
2
4
Cout ESR=17 mohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm
Ipeak=13.5A, Imax=9.5A, Iocp=16.2A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
=>1/2Delta I=1.95A
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V
Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A
Iocp=18A~32A
PQ28
AO4456_SO8
1
+ PC86
330U_6.3V_M
PC88
680P_0603_50V7K
2
PC90
4.7U_0805_10V6K
1
PR113
10K_0402_1%
2
1
PR114
10K_0402_1%
2
VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=335KHz
PR110
4.7_1206_5%
+5VALW
1
PGND
8
7
2
PGOOD
GND
6
PC87
4.7U_0603_6.3V6K
1
+1.5VP
1
11
2
BOOT
12
CS
1
5
PHASE
1
VDD
LX_1.5V
2
VOUT
4
DH_1.5V
5
6
7
8
3
13
UGATE
3
PL7
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
3
2
1
PR111
100_0603_1%
1
2
NC
2
+5VALW
TON
PC84
0.1U_0603_25V7K
BST_1.5V-1
1
2
14
1
PU7
2
15
@PC85
@
PC85
0.1U_0402_16V7K
2
@ PR109
30K_0402_5%
EN/DEM
3
1
1
3
2
1
PR108
2.2_0603_5%
BST_1.5V 1
2
PR105 0_0402_5%
1
2
PC82
10U_1206_25V6M
1.5V_B+
PR106
226K_0402_1%
1
2
<28,33> SYSON
1
PQ26
AO4456_SO8
1
PGND
7
VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
8
PGOOD
GND
6
2
PC77
4.7U_0603_6.3V6K
PR100
4.7_1206_5%
+5VALW
2
PR102
7.32K_0402_1%
+1.1VALWP
1
LX_1.1VALW
1
2
NC
FB
12
CS
1
5
PHASE
0.1U_0603_25V7K
1
VDD
DH_1.1VALW
13
2
VOUT
4
UGATE
5
6
7
8
3
BOOT
TON
PL6
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
PC75
BST_1.1VALW -11
2
3
2
1
PR101
100_0603_1%
1
2
2
14
1
EN/DEM
PU6
2
+5VALW
15
1
@ PC74
0.1U_0402_16V7K
2
@ PR99
30K_0402_5%
1
DCR= 7.5 mohm
1
<35,36> SPOK
B+
PQ25
AO4466_SO8
4
PR98
2.2_0603_5%
BST_1.1VALW
1
2
3
2
1
PR97
0_0402_5%
1
2
PL31
FBMA-L11-322513-151LMA50T_1210
2
1
PC72
10U_1206_25V6M
1
2
2
5
6
7
8
1
PC139
2200P_0402_50V7K
1.1VALW _B+
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
1.1VALWP/1.5VP
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
D
38
of
45
A
B
C
D
PL33
FBMA-L11-322513-151LMA50T_1210
2
1
PR115
255K_0402_1%
1
2
VDDP
10
FB
LGATE
PC218
100U_25V_M
1
2
PC97
680P_0603_50V7K
2
PC99
4.7U_0805_10V6K
1
2
HIGH
LOW
D
3
1
2
3
S
1
2
2
PC125
0.1U_0402_25V6
PQ43
2N7002W -T/R7_SOT323-3
2
G
PR157
0_0402_5%
2
1
1.1V
POW ER_SEL <13>
1
1
PR159
10K_0402_5%
2
1
PC126
0.01U_0402_25V7K
3
PJ24
@ JUMP_43X79
2
1
0.95V
2
1
1
2
G
S
1
POWER_SEL
PR131
10K_0402_1%
PR123
8.87K_0402_1%
+5VALW
3
PC115
1U_0402_6.3V6K
1
VIN
9
1
2
PC118
0.01U_0402_25V7K
2
2
GND
PR154
31.6K_0402_1%
APL5915KAI-TRL_SO8
1
1
2
2
1
LOW
D
1.05V
PC114
1U_0402_6.3V6K
3
+2.5VSP
1
0.9V
PQ58
2N7002W -T/R7_SOT323-3
2
G
S
@ PR153
150_1206_5%
4
1
3
<20> VDDR_SW
OUT
GND
2
1
HIGH
IN
PC113
4.7U_0805_6.3V6K
PR152
10K_0402_1%
4
2
+3VS
VDDR_SW
PR156
249K_0402_1%
2
PR161
165K_0402_1%
PU16
APL5508-25DC-TRL_SOT89-3
1
2
+5VALW
+CPU_VDDRP
1
2
2
PR188 @
47K_0402_5%
EN
1
1
1
8
2
3
FB
1
VOUT
PC116
4.7U_0805_6.3V6K
1
4
2
5
1
@ PR155
10K_0402_1%
1
2
VIN
VOUT
PC119
22U_0805_6.3V6M
POK
2
PU12
7
VCNTL
10K_0402_1%
1
2
6
2
2
1
4
S IC G5603RU1U TQFN 14P PW M
PR158
11.8K_0402_1%
+1.5V
PC121
0.1U_0402_16V7K
DL_NB_CORE
+5VALW
D
VLDT_EN
+ PC95
330U_6.3V_M
2
PR122
2.37K_0402_1%
1
2
PQ44
2N7002W -T/R7_SOT323-3
<28,42> VR_ON
1
PQ30
AO4456_SO8
2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m
Ipeak=7.6A, Imax=5.4A, Iocp=9.2A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V
Rcs=Vtrip/9uA=0.067V/9uA=7.44K
choose Rcs=7.5K
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A
Iocp=10.3A~19.36A
PR162
9
2
PR121
7.5K_0402_1%
1
PGND
8
7
2
PGOOD
GND
6
PC96
4.7U_0603_6.3V6K
VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
PR119
4.7_1206_5%
+5VALW
1
+NB_COREP
1
11
2
NC
BOOT
12
CS
1
5
PHASE
LX_NB_CORE
5
6
7
8
VDD
14
1
VOUT
4
DH_NB_CORE 0.1U_0603_25V7K
1
2
DCR= 7.5 mohm
2
FB1_NB_COREP
3
13
+
2
PL8
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
PC93
BST_NB_CORE-1
1
2
UGATE
1
1
3
2
1
PR120
100_0603_1%
1
2
+5VALW
TON
EN/DEM
PU8
2
15
1
PC94
0.1U_0402_16V7K
2
2
@ PR118
30K_0402_5%
B+
PQ29
AO4466_SO8
1
<28,33> VLDT_EN
4
PR117
2.2_0603_5%
BST_NB_CORE
1
2
3
2
1
PR116
100K_0402_5%
1
2
PC91
10U_1206_25V6M
2
5
6
7
8
1
1
PC140
2200P_0402_50V7K
NB_CORE_B+
@ PR160
10K_0402_1%
2010/04/12
Deciphered Date
2010/10/12
Title
NB_CORE/2.5VS/CPU_VDDRP
2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
D
39
of
45
5
4
3
2
1
PreCHG
+1.5V
PR126
1K_1206_5%
1
2
3
VREF VCNTL
6
4
VOUT
NC
5
TP
9
+3VALW
PC101
1U_0603_6.3V6M
PR128
100K_0402_5%
2
2
PR130
1K_0402_1%
D
PR127
1K_1206_5%
1
2
2
7
PR129
100K_0402_5%
2
3
S
2N7002W -T/R7_SOT323-3
1
PR132
100K_0402_5%
1
1
+0.75VSP
PQ33
DTC115EUA_SC70-3
PD18
PC103
22U_0805_6.3V6M
<28,37> ACOFF
+5VALWP
2
1
2
PQ34
DTC115EUA_SC70-3
3
BAS40CW _SOT323-3
2
3
2
PR134
1K_0402_1%
PC102
0.1U_0402_16V7K
2
1
1
D
2
PC104
0.22U_0402_10V4Z
PQ32
2
G
1
PR133
300K_0402_5%
1
2
<33> SUSP
1
UP7711U8 PSOP 8P
1 2
8
NC
B+
1
LL4148_LL34-2
1
NC
GND
3
2
VIN
2
1
1
1
2
PU9
1
PC100
4.7U_0805_6.3V6K
2
PD13
1
1
1
2
PJ17
JUMP_43X79
2
D
PQ31
TP0610K-T1-E3_SOT23-3
PR125
1K_1206_5%
1
2
VIN
2
1
PR124
1K_1206_5%
1
2
3
Change 300K / 0.22u delay
Ipeak=1A, Imax=0.7A
C
C
B
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Issued Date
Deciphered Date
2010/10/12
Title
Precharge/+0.75VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Friday, June 11, 2010
Rev
0.1
PEW96 LA-6552P
Sheet
1
40
of
45
5
4
3
2
1
FB=0.6V
Note:Iload(max)=3.5A
D
D
1
1
2
SY8033BDBC_DFN10_3X3
1
2
PR145
4.99K_0402_1%
2
@
PC155
680P_0603_50V7K
1
2
PC1026
0.1U_0402_10V7K
1
2
PC156
0.22U_0603_25V7K
PC124
22U_0805_6.3VAM
2
NC
FB_1.8V
1
NC
TP
1.8V_EN
PR147
10K_0402_1%
1
6
2
FB
+1.8VSP
PC117
22U_0805_6.3VAM
3
PL9
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2
PC1022
68P_0402_50V8J
2
1
LX
LX_1.8V
1
EN
2
2
SVIN
5
LX
1
8
PG
PVIN
7
PR144
200K_0402_1%
1
2
9
11
VGA_ON
PVIN
PR143
4.7_1206_5%
1
<28,33> VGA_ON
10
2
PC157
22U_0805_6.3VAM
4
PU11
+3VALW
C
C
B
B
A
A
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
+1.8VSP
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
41
of
45
E
F
G
PC189
1000P_0402_50V7K
2
1
1
1 2
2
1
28
26
UGATE1
25
BOOT1
PC202
1U_0603_16V6K
3
2
1
2
PC201
1
2
0.1U_0402_16V7K
LGATE0
CPU_B+
5
PQ51
AON6428L 1N DFN-8
UGATE1
4
+CPU_CORE_0
Design Current: 25A
Max current: 35A
OCP_min:42A
PHASE1
PL18
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
3
2
1
PR243
2.2_0603_5%
BOOT1 1
2 1
1
5
PR247
16.2K_0402_1%
PR248
4.7_1206_5%
PQ49
AON6704L_DFN8-5
4
4
AON6704L_DFN8-5
PC208
680P_0603_50V7K
2
3
2
1
PR251
10_0402_5%
1
3
2
1
VSEN1
DIFF_1
3
+CPU_CORE
1
2
PC207
0.1U_0603_25V7K
2
1 PR235 2
4.02K_0402_1%
ISP0
PHASE1
PC200
680P_0603_50V7K
PC206
2200P_0402_50V7K
2
1
27
PC204
4.7U_0805_25V6-K
2
1
LGATE1
29
@ PQ47
AON6704L_DFN8-5
@ PQ52
+CPU_CORE
PC198
2200P_0402_50V7K
2
1
1
1
4
3
2
1
30
@ PR252 1K_0402_1%
2
1
<8> CPU_VDD1_FB_H
PC197
0.01U_0402_25V7K
2
1
3
2
1
4
+5VALW
RTN1
PR246 10K_0402_1%
2
1
+1.5VS
PR233
4.7_1206_5%
LGATE0
31
+CPU_CORE
PR232
16.2K_0402_1%
PQ48
AON6704L_DFN8-5
PC205
0.01U_0402_25V7K
2
1
32
PC199
0.1U_0603_25V7K
1 2
33
PHASE0
2
UGATE0
5
BOOT0
34
PL17
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
2
5
35
2
PR229
2.2_0603_5%
BOOT0 1
2 1
TP
VW1
ISN1
24
ISP1
23
ISN1
FB1
COMP1
22
21
BOOT_NB
2
10_0402_5%
1
36
1 2
RTN0
4
5
<8> CPU_VDD0_FB_L
BOOT1
ISP1
0_0402_5%
PR240
2
20
14
ISP0
13
1
UGATE0
PC223
4.7U_0805_25V6-K
2
1
5
UGATE1
PR241
2
1
10_0402_5%
PQ46
AON6428L 1N DFN-8
1
COMP0
VDIFF1
PHASE1
VW0
<8>
2
38
37
UGATE_NB
LGATE_NB
PHASE_NB
41
40
39
PGND_NB
OCSET_NB
43
42
RTN_NB
VSEN_NB
PGND1
FB0
VSEN0
VW0
LGATE1
ISL6265IRZ-T_QFN48_6X6~D
ISP0
ISN0
PR245
2
45
PVCC
VSEN1
12
<8> CPU_VDD1_FB_L
44
LGATE0
VDIFF0
11
+CPU_CORE
FSET_NB
46
PGND0
OCSET
10
<8> CPU_VDD0_FB_H
FB_NB
SVC
RBIAS
9
3
COMP_NB
VCC
PHASE0
ENABLE
8
PR239
1
95.3K_0402_1%
SVD
19
<28,39> VR_ON
DIFF_0
CPU_VDDNB_FB_L
49
6
7
2
47
48
VIN
5
BOOT0
UGATE0
RTN1
1
0_0402_5%
BOOT_NB
PWROK
RTN0
2
PR236
4
+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A
PHASE0
PGOOD
VSEN0
<8> CPU_SVC
3
15
PR242 0_0402_5%
16
2
1
0_0402_5%
2 PR244 1
17
0_0402_5%
2 PR250 1
18
1
0_0402_5%
2
ISN0
2
PR234
PR238
2
1
21.5K_0402_1%
1
1
2
<8> CPU_SVD
OFS/VFIXEN
PC192
220U_D2_4VM
CPU_B+
PC196
4.7U_0805_25V6-K
2
1
2
2
2
1
1
PR237 0_0402_5%
1
2
1
2
PR231 0_0402_5% @
<18> H_PWRGD_L
+
LGATE_NB
PR226
10_0402_5%
1
<28> VGATE
2
PHASE_NB
PR224
0_0402_5%
PU15
2
<8>
1
PC193
680P_0603_50V7K
UGATE_NB
PR228
@ 105K_0402_1%
2
2
PR227
105K_0402_1%
4
PHASE_NB
2
PR225
@ 10K_0402_1%
+CPU_CORE_NB
PR217
4.7_1206_5%
3
2
1
CPU_VDDNB_FB_H
PR221
13.7K_0402_1%
2
1
PR220
0_0402_5%
1
PR223
@ 105K_0402_1%
1
1
5
6
7
8
LGATE_NB
2
PR222
0_0402_5%
+CPU_CORE_NB
2
PC194
0.1U_0603_16V7K
PL16
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2
PQ70
AO4712_SO8
PR218
10_0402_5%
1
2
PR219
2_0603_5%
+3VS
1
+5VS
1
+3VS
+
2
B+
2
PC191
0.1U_0603_25V7K
2
CPU_B+
PHASE_NB
4
PR216
22K_0402_1%
2
1
2
PC190
0.1U_0603_16V7K
1
UGATE_NB
PR230
2.2_0603_5%
BOOT_NB 1
2 1
PC195
4.7U_0805_25V6-K
2
1
PR215
2_0603_5%
1
2
1
+5VALW
1
PC184
1200P_0402_50V7K
PC219
2200P_0402_50V7K
2
1
2
PC188
220U_25V_M
1
PR214
44.2K_0402_1%
1
PC203
4.7U_0805_25V6-K
2
1
2
3
2
1
1
PC187
2200P_0402_50V7K
2
1
PQ69
AO4466_SO8
PL15
FBMA-L18-453215-900LMA90T_1812
2
1
PC186
0.01U_0402_25V7K
2
1
5
6
7
8
PC185
10U_1206_25V6M
2
1
CPU_B+
PC183
33P_0402_50V8K
2
1
H
PC222
0.01U_0402_25V7K
2
1
D
PC221
0.01U_0402_25V7K
2
1
C
PC220
2200P_0402_50V7K
2
1
B
ISN0
A
1 PR249 2
4.02K_0402_1%
PC209
1
2
0.1U_0402_16V7K
VW1
1
COMP0
PC211
180P_0402_50V8J
PR255
1K_0402_5%
2
1
PR256
2
1
PC216
2
1
2
1
PC212
1000P_0402_50V7K
PR257
6.81K_0402_1%
2
1
2
1
COMP1
PC214
180P_0402_50V8J
PR258
1K_0402_5%
2
1
PR259
2
PC217
2
1
1
PC215
1000P_0402_50V7K
PR260
6.81K_0402_1%
2
1
1
54.9K_0402_1% 1200P_0402_50V7K
1
54.9K_0402_1% 1200P_0402_50V7K
1
2
ISN1
2
PR254
PC213
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
ISP1
LGATE1
PR253
PC210
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
2
PR263 @
1K_0402_5%
2
PR262 @
1K_0402_5%
4
4
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/12
Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
C
Date:
A
B
C
D
E
F
G
Document Number
Rev
0.1
NAV71
Friday, June 11, 2010
Sheet
42
H
of
45
5
4
3
2
Version change list (P.I.R. List)
Item
Fixed Issue
Page 1 of 2
for PWR
Reason for change
Rev.
PG#
D
1
2
1
Modify Pre-charger
Meet common rule
36
Modify List
Date
Phase
Add PR279,PR288,PC57
Change PR285 100K to 47K
Change PR287 20K to 14.3K
Change PQ67 2N7002 to PDTC115
Change PR62 47K to 200K
Change PR79 22K to47K
Change PR283 0 to 100K
2010
0528
PVT
Change PJ30 to PL36, PJ23 to PL37
Add PC361,PC362
2010
0602
PVT
Change PR265 from 30K to 30.9K
2010
0604
PVT
D
3
HDMI test fail
5V voltage too low at test termial
4
ESD test fail
ESD solution
Add PC22, PC23
2010
0608
PVT
5
EMI test fail
EMI solution
Enable 3V,5V,1.1V,1.5V,NB_CORE,CPU snubber
2010
0608
PVT
C
C
6
7
8
9
10
B
B
11
12
13
14
15
A
A
16
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR (PWR)
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
43
of
45
5
4
3
2
Version change list (P.I.R. List)
Item
Fixed Issue
1
Page 2 of 2
for PWR
Reason for change
Rev.
PG#
Modify List
Date
Phase
D
D
1
2
3
4
5
C
C
6
7
8
9
10
B
B
11
12
13
14
15
A
A
16
2010/04/12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR (PWR)
Rev
0.1
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
44
of
45
5
4
3
2
1
05/10 First release
1. Change Cardreader chip (RTS5137/RTS5138)
2. ODD used to ODD sub/b
3. RTC Battery change (w/o charge)
D
D
06/02 PVT
1. P.28 Reserve R889 For EC_CLK, pop R851, unpop R852 For EC_SMBus leakage
2. P.26 Remove R853
3. P.28 project ID-->1 Board ID -->1, unstuff KSI, KSO Cap.
C
C
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/12
Deciphered Date
2010/10/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
HW PIR
Document Number
Rev
0.2
PEW96 LA-6552P
Friday, June 11, 2010
Sheet
1
45
of
45
www.s-manuals.com
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Title : Compal LA-6552P - Schematics. www.s-manuals.com.
Subject : Compal LA-6552P - Schematics. www.s-manuals.com.
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