Compal LA 6582P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-6582P PEW71, PEW81, PEW91 - Schematics. Free.
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A B C D E 1 1 Compal Confidential 2 2 PEW71_81_91 UMAM/B Schematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M 2010-07-08 REV:1.0 3 3 4 4 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet E 1 of 48 Rev 1.0 A B C D E Compal Confidential Model Name PEW71_81_91 UMA File Name : LA-6582P 1 1 ZZZ1 ZZZ2 46@ M/B PCB HDMI+HDCP LOGO DAZ0FO00400 RO0000003HM Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel Arrandale (UMA) Fan Control page 26 Processor rPGA988A 6.4G/8.5G/10.6G 100M/133M/166M(CFD) USB conn x3 page 4,5,6,7,8,9 (UMA) FDI x8 DMI x4 100MHz 1GB/s x4 USB port 0 (Left Low) USB Port 1 (Left High) USB port 2 (sub board) 100MHz LVDS Conn. LVDS(UMA) page 22 CRT(UMA) CRT Conn. page 23 Level Shift HDMI Conn. page 24 page 24 HDMI(UMA) PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz port 2,4 MINI Card x1 WLAN port 1 GIGA LAN BCM57780 page 26 Intel Ibex Peak-M USBx14 3.3V 48MHz HD Audio 3.3V 24MHz CMOS Camera USB port 11 USB port 8 page 29 Mini card USB port 9 page 22 page 26 page 29 2 HDA Codec ALC272X SPI page 33 port 0 SPI ROM page 27 Card Reader USB port 12 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz PCH page 13,14,15,16,17 18,19,20,21 SATA HDD Conn. page 13 RJ45 Conn. Bluetooth Conn page 29 2.7GT/s 2 page 10,11 BANK 0, 1, 2, 3 1.5V DDRIII 800/1066/1333 port 1 SATA ODD Conn. page 25 Audio AMP TPA6017 page 25 page 34 page 28 LPC BUS 3 3 Int. Speaker 33MHz page 34 RTC CKT. ENE KB926 LS-6581P USB/B page 30 Power ON/Off CKT. LS-6582P PWR/B Touch Pad DC/DC Interface CKT. LS-6583P ODD/B Int.KBD page 31 Clock Generator page 31 BIOS ROM Power Circuit DC/DC CKT. IDT: 9LRS3199AKLFT SILEGO: SLG8SP587 133/120/100/96/14.318MHZ to PCH 48MHZ to CardReader page 31 page 12 4 4 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Block Diagrams Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 2 of 48 Rev 1.0 A B C SIGNAL STATE Voltage Rails D Full ON 1 Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON ON OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF +1.05VS 1.05V switched power rail for PCH ON OFF OFF +1.05VS_VTT 1.05V switched power rail (1.05 for AUB CPU) ON OFF OFF +1.5V 1.5V power rail for DDRIII ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8VS 1.8V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V_LAN 3.3V power rail for LAN ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# E +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF 1 Project ID / Board ID Table for EC-AD channel Vcc Ra/Rc 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb / Rd 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V VAD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Board ID 0.1 0.2 0.3 1.0 Project ID Original NEW70/80/90/50/71/91 PEW71/81/91 Audio Mono/Crystal PEW71/81/91 Audio Mono/SUSCLK NEW71/91 Optumis 2 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BTO Item HDMI External PCI Devices Device IDSEL# REQ#/GNT# EC SM Bus1 address Device Address Smart Battery 0001 011X b EC SM Bus2 address Device Device Address Clock Generator (9LRS3199AKLFT, SLG8SP587) 1101 0010b DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb BOM Structure HDMI@ Interrupts Address Ibex SM Bus address 3 BTO Option Table USB Port Table USB 2.0 USB 1.1 Port UHCI0 0 1 2 4 External USB Port 3 External USB Port Ext1 Left Low USB Ext2 Left High USB Ext3 Right USB Ext1 Left Low USB Ext2 Left High USB Ext3 Right USB Camera Card Reader Camera Card Reader Blue Tooth 1st Min-Card Blue Tooth 1st Min-Card 3 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 4 UHCI6 3 4 5 6 7 8 9 10 11 12 13 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C 4 D Title Notes List Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 3 of 48 Rev 1.0 5 4 3 2 1 JCPU1E JCPU1A DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] <15> H_FDI_FSYNC0 <15> H_FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] <15> H_FDI_INT C17 FDI_INT <15> H_FDI_LSYNC0 <15> H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] C Intel(R) FDI H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 B PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_IRCOMP 1 R1 2 49.9_0402_1% EXP_RBIAS 1 R3 2 750_0402_1% AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 R5 3.01K_0402_1% 1 @ 2 CFG0 R6 3.01K_0402_1% R7 3.01K_0402_1% 1 @ 1 @ 2 2 CFG3 CFG4 R8 3.01K_0402_1% 1 @ 2 CFG7 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 R11 0_0402_5% @ 1 2 @ 1 2 H_RSVD17_R H_RSVD18_R R12 0_0402_5% DMI_PTX_HRX_N[0..3] <15> DMI_PTX_HRX_P[0..3] <15> <15> <15> CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 C1 A3 DMI_HTX_PRX_N[0..3] <15> DMI_HTX_PRX_P[0..3] <15> H_FDI_TXN[0..7] H_FDI_TXP[0..7] AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 (CFD Only) (CFD Only) RESERVED DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS -- GRAPHICS A24 C23 B22 A21 DMI D DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS D C R9 0_0402_5% RSVD64_R 2 @ RSVD65_R 2 @ R10 0_0402_5% 1 1 B AP34 IC,AUB_CFD_rPGA,R1P0 CONN@ A eDP Signals Mapping eDP Singal PEG Singals eDP_TX0 PEG_HTX_C_GRX_P15 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1 PEG_HTX_C_GRX_N14 eDP_TX2 PEG_HTX_C_GRX_P13 eDP_TX#2 PEG_HTX_C_GRX_N13 eDP_TX3 PEG_HTX_C_GRX_P12 eDP_TX#3 PEG_HTX_C_GRX_N12 eDP_AUX PEG_GTX_C_HRX_P13 eDP_AUX# PEG_GTX_C_HRX_N13 eDP_HPD# PEG_GTX_C_HRX_P12 5 Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port CFG3 - PCI-Express Static Lane Reversal *:Default *1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ... A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PROCESSOR (1/6) DMI,FDI,PEG Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 1 4 of 48 Rev 1.0 5 4 3 2 1 JCPU1B COMP3 R19 2 1 20_0402_1% H_COMP2 AT24 COMP2 R20 2 1 49.9_0402_1% H_COMP1 G16 COMP1 R21 2 1 49.9_0402_1% H_COMP0 AT26 COMP0 T24 PAD @ SKTOCC#_R D AH24 R26 1 0_0402_5% <18> H_PECI AK14 H_PECI_R 2 AT15 H_PROCHOT# <45> H_PROCHOT# R36 1 0_0402_5% <18> H_THERMTRIP# AN26 H_THERMTRIP#_R 2 AK15 CATERR# THERMAL H_CATERR# SKTOCC# PECI PROCHOT# THERMTRIP# BCLK BCLK# AR30 AT30 PEG_CLK PEG_CLK# E16 D16 CLK_CPU_DMI <14> CLK_CPU_DMI# <14> DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 CLK_CPU_DP <14> CLK_CPU_DP# <14> SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] AN14 VCCPWRGOOD_1 H_PM_SYNC_R R44 1 0_0402_5% 2 H_CPUPW RGD_1 R50 1 0_0402_5% <15> PM_DRAM_PW RGD PM_SYNC 2 R47 1 0_0402_5% <18> H_CPUPW RGD AL15 R42 1 0_0402_5% H_CPUPW RGD_0 2 AK13 SM_DRAMPWROK 2 H_VTTPW RGD_R 0_0402_5% AM15 VTTPWRGOOD AM26 TAPPWRGOOD AL14 RSTIN# del net for XDP remove R56 1 1.5K_0402_1% PM_EXT_TS#[0] PM_EXT_TS#[1] PLT_RST#_R 2 del net for XDP remove F6 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R 1 R28 2 100K_0402_5% R32 R34 R35 1 1 1 del R27 / R29 / R30 / R31 / R33 for XDP remove +1.05VS_VTT 2 10K_0402_5% 2 10K_0402_5% 2 0_0402_5% PM_EXTTS#0_1 <10,11> XDP_TRST# R37 XDP_TDO AT28 AP27 TCK TMS TRST# AN28 AP28 AT27 H_TCK H_TMS XDP_TRST# @ @ PAD T25 PAD T26 TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 H_TDI XDP_TDO XDP_TDI_M XDP_TDO_M @ PAD T27 20100610 Add DBR# AN25 XDP_DBR#_R R46 BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 1 1 1 D 2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev0.9 SM_DRAMRST# <10> AL1 AM1 AN1 R38 R39 R40 1 R70 2 51_0402_5% 1 2 51_0402_5% +1.05VS_VTT XDP_TDO_M R45 0_0402_5% XDP_TDI_M 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# <15> del R41 / R43 / R48 / R49 XDP remove XDP_DBRESET# 1 R67 2 1K_0402_5% +3VS C del net for XDP remove 1 <17,27,30> PLT_RST# VCCPWRGOOD_0 PM_DRAM_PW RGD_R 2 H_VTTPW RGD 1 @ R52 AN27 JTAG & BPM C RESET_OBS# PWR MANAGEMENT <15> H_PM_SYNC AP26 CLK_CPU_BCLK <18> CLK_CPU_BCLK# <18> BCLK_ITP BCLK_ITP# PRDY# PREQ# H_CPURST# A16 B16 1 AT23 2 H_COMP3 CLOCKS 1 20_0402_1% DDR3 MISC 2 MISC R18 2009/2/4 #414044 DG Update Rev1.11 IC,AUB_CFD_rPGA,R1P0 CONN@ 2 R57 750_0402_1% +1.05VS_VTT R58 R59 R60 1 49.9_0402_1% 1 68_0402_5% @ 1 68_0402_5% 2 2 2 H_CATERR# H_PROCHOT# H_CPURST# B B +3VALW 5 Y MC74VHC1G08DFT2G_SC70-5 R61 2K_0402_1% 1 2 H_VTTPW RGD_R 1 A 4 G 1 P U1 H_VTTPW RGD 2 B R62 3 <43> H_VTTPW RGD 2009/8/14 change back to 2K 1K_0402_1% 2 U1 / U2 change to SA00000OH00 #425302 CP_S3PowerReduction WhitePaper_Rev0.7 +3VALW R69 P 3 R68 @ 1.1K_0402_1% H_VTTPW RGD 1 MC74VHC1G08DFT2G_SC70-5 2 1.5K_0402_1% 2 A A Y 1 1 4 U2 B 2 G 5 Need to check Voltage Level +1.5V_1 A 1 1 PM_DRAM_PW RGD_R 2 5 R72 2009/04/23 Intel CRB 1.55 Update Change R68 to 1.1K_1%, R71 to 3.01K_1% 4 Compal Electronics, Inc. Compal Secret Data Security Classification 750_0402_1% 2 R71 @ 3.01K_0402_1% 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title PROCESSOR (2/6) CLK,JTAG Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 1 5 of 48 Rev 1.0 4 B <10> DDR_A_BS0 <10> DDR_A_BS1 <10> DDR_A_BS2 <10> DDR_A_CAS# <10> DDR_A_RAS# <10> DDR_A_W E# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_W E# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 Y6 Y5 P6 DDR_A_CLK1 <10> DDR_A_CLK1# <10> DDR_A_CKE1 <10> SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# <10> DDR_A_CS1# <10> SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 <10> DDR_A_ODT1 <10> B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 <10> DDR_A_CLK0# <10> DDR_A_CKE0 <10> SA_CK[1] SA_CK#[1] SA_CKE[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 <11> DDR_B_BS0 <11> DDR_B_BS1 <11> DDR_B_BS2 <11> DDR_B_CAS# <11> DDR_B_RAS# <11> DDR_B_W E# 1 JCPU1D <11> DDR_B_D[0..63] <11> DDR_B_DM[0..7] <11> DDR_B_DQS#[0..7] <11> DDR_B_DQS[0..7] <11> DDR_B_MA[0..15] JCPU1C <10> DDR_A_D[0..63] <10> DDR_A_DM[0..7] <10> DDR_A_DQS#[0..7] <10> DDR_A_DQS[0..7] <10> DDR_A_MA[0..15] D 3 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B 5 SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDR_B_CLK0 <11> DDR_B_CLK0# <11> DDR_B_CKE0 <11> SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDR_B_CLK1 <11> DDR_B_CLK1# <11> DDR_B_CKE1 <11> SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_B_CS0# <11> DDR_B_CS1# <11> SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 <11> DDR_B_ODT1 <11> SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@ A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 A 3 2 Title PROCESSOR (3/6) DDRIII Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 1 6 of 48 Rev 1.0 5 4 3 2 1 JCPU1F WW15 MOW +CPU_CORE Peak 21A A 10U_0805_6.3V6M +CPU_CORE 1 1 C66 2 1 C67 2 1 C68 2 C69 2 10U_0805_6.3V6M 1 1 C70 2 C71 2 10U_0805_6.3V6M 1 10U_0805_6.3V6M C72 1 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C73 2 10U_0805_6.3V6M 1 C74 2 10U_0805_6.3V6M 1 C75 2 C76 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C77 2 1 C78 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C79 2 1 C80 2 10U_0805_6.3V6M D C81 2 10U_0805_6.3V6M (Place these capacitors between inductor and socket on Bottom) +CPU_CORE 1 10U_0805_6.3V6M + C83 330U_2.5V_M_R15 1 1 C84 10U_0805_6.3V6M 1 C85 1 C86 10U_0805_6.3V6M 1 C87 1 C88 C89 2 + C82 2 2 2 2 2 2 330U_2.5V_M_R15 Change to OS-CON 20100414 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.05VS_VTT VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VTT_SELECT 1 C91 C92 1 2 2 H_PSI# <45> AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 CPU_VID0 <45> CPU_VID1 <45> CPU_VID2 <45> CPU_VID3 <45> CPU_VID4 <45> CPU_VID5 <45> CPU_VID6 <45> H_DPRSLPVR <45> H_VTTVID1 @ PAD T14 AN35 C +CPU_CORE CPU_VID2 R77 R78 1 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID3 R79 R80 1 @ 1 2 1K_0402_1% 2 1K_0402_1% CPU_VID4 R81 R82 1 @ 1 2 1K_0402_1% 2 1K_0402_1% CPU_VID5 R83 R84 1 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID6 R85 R86 1 @ 1 2 1K_0402_1% 2 1K_0402_1% H_DPRSLPVR R87 R88 1 1 @ 2 1K_0402_1% 2 1K_0402_1% H_PSI# 1 @ 1 2 1K_0402_1% 2 1K_0402_1% R89 R90 2 2 1 1 C97 2 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) +CPU_CORE 22U_0805_6.3V6M C99 1 C100 1 22U_0805_6.3V6M C101 2 1 C102 2 1 22U_0805_6.3V6M C103 2 1 C104 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M B +CPU_CORE 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) 2 100_0402_1% VCCSENSE <45> VSSSENSE <45> 2 100_0402_1% R94 1 +CPU_CORE C105 1 + C272 1 + C273 1 + C275 + Del C106 330U_D2E_2.5VM_R6M 2 2 330U_D2E_2.5VM_R6M 2 2 330U_D2E_2.5VM_R6M 330U_D2E_2.5VM_R6M 2 0_0402_5% TOP side (under inductor) 2009/08/01 Issued Date 4X470uF 4m ohm/4 16X22uF 3m ohm/12 16X10uF 3m ohm/16 Stuffing Option 2X470uF A Compal Electronics, Inc. 2010/08/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 ESR, mohm C,uF Compal Secret Data Security Classification 4 C96 22U_0805_6.3V6M +CPU-CORE Decoupling SPCAP,Polymer IC,AUB_CFD_rPGA,R1P0 CONN@ 1 C95 (Place these capacitors on CPU cavity, Bottom Layer) Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V VTT_SENSE <43> 1 1 2 2 1 R91 VCCSENSE VSSSENSE R95 C94 22U_0805_6.3V6M IMVP_IMON <45> VSS_SENSE_VTT 1 22U_0805_6.3V6M VTT Rail AJ34 AJ35 B15 A15 2 1K_0402_1% 2 1K_0402_1% 22U_0805_6.3V6M 1 VTT_SENSE VSS_SENSE_VTT 2 1K_0402_1% 2 1K_0402_1% 1 1 @ 20090915 Modify H_VTTVID1 = high, 1.05V VCC_SENSE VSS_SENSE 1 1 @ R75 R76 C98 22U_0805_6.3V6M H_VTTVID1 = low, 1.1V ISENSE R73 R74 CPU_VID1 22U_0805_6.3V6M AN33 G15 CPU_VID0 22U_0805_6.3V6M MLCC 0805 X5R 5 1 +1.05VS_VTT 1 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 10U_0805_6.3V6M 2 VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 PSI# POWER B +1.05VS_VTT 10U_0805_6.3V6M AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +1.05VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 1.1V RAIL POWER 48A 2 Title PROCESSOR (4/6) PWR,Bypass Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 7 of 48 Rev 1.0 5 4 3 2 1 +VGFX_CORE JCPU1G C112 1 C113 1 + 2 330U_D2E_2.5VM_R6M 1 2 2 2 2 22U_0805_6.3V6M 10U_0805_6.3V6M J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 15A GRAPHICS C VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 3A 2 2 C123 FDI C122 22U_0805_6.3V6M 1 AR22 AT22 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 VCC_AXG_SENSE <44> VSS_AXG_SENSE <44> D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR_R R97 <44> <44> <44> <44> <44> <44> <44> GFXVR_EN PD 470ohm AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 1U_0402_6.3V6K C114 1 C115 1 C116 1 1U_0402_6.3V6K C117 1 C118 1 C119 1 C120 2 1 2 2 2 2 2 2 2 22U_0805_6.3V6M 1.1V 2 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 1 C121 330U_D2E_2.5VM_R6M J3 2 2 1 1 +1.5VS @ JUMP_43X118 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C 22U_0805_6.3V6M Reserved for +1.5VS to +1.5V_1 11/03 add four 0.1u 0402 Intel suggest +1.05VS_VTT 1 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 1 2 +1.5V 1 C670 1 C671 1 C672 1 C673 C124 10U_0805_6.3V6M 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z C127 22U_0805_6.3V6M B +1.8VS 0.6A 1.8V 2 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 PEG & DMI 22U_0805_6.3V6M B 1 +1.5V_1 22U_0805_6.3V6M C126 2 @ JUMP_43X118 1 + 2 2 1 +1.5V 22U_0805_6.3V6M +1.05VS_VTT 1 +1.5V_1 Reserved for +1.5V to +1.5V_1 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 +1.05VS_VTT C125 2 470_0402_5% 20091105 GFXVR_EN <44> GFXVR_DPRSLPVR <44> GFXVR_IMON <44> 2 0_0402_5% 1 1 R167 J1 +1.05VS_VTT 1 VAXG_SENSE VSSAXG_SENSE - 1.5V RAILS C111 DDR3 D 1 GRAPHICS VIDs C107 C110 POWER 1 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 SENSE LINES 10U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0603_6.3V6K +1.8VS_VCCSFR C128 1U_0402_6.3V6K IC,AUB_CFD_rPGA,R1P0 CONN@ 1 2 R99 0_0805_5% 1 2 C129 1 C130 2 1 C131 2 1U_0402_6.3V6K 1 1 2 2 22U_0805_6.3V6M C132 4.7U_0805_10V4Z A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR (5/6) PWR Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 8 of 48 Rev 1.0 5 4 3 2 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 1 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 @ @ PAD T2 PAD T3 H_NCTF6 H_NCTF7 @ @ PAD T4 PAD T5 B IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR (6/6) VSS Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 9 of 48 Rev 1.0 5 4 3 2 1 +1.5V DIMMA VREFDQ M1 Circuit JDIMM1 <6> DDR_A_DQS#[0..7] +1.5V +DIMM_VREFDQA <6> DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 1 <6> DDR_A_DM[0..7] +DIMM_VREFDQA R101 DDR_A_DM0 <6> DDR_A_DQS[0..7] 1K_0402_1% DDR_A_D2 DDR_A_D3 2 <6> DDR_A_MA[0..15] M1 Circuit 1 DDR_A_D8 DDR_A_D9 +DIMM_VREFDQA R104 D DDR_A_DQS#1 DDR_A_DQS1 2 1K_0402_1% C134 0.1U_0402_16V4Z 1 1 2 2 DDR_A_D10 DDR_A_D11 C133 2.2U_0603_6.3V6K DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DIMMA & DIMMB VREFCA circuit +1.5V 1 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 +DIMM_VREFCA R106 DDR_A_DM3 2 1K_0402_1% +1.5V R102 0_0402_5% 1 @ 2 1K_0402_1% DDR_A_D26 DDR_A_D27 1 1 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 R107 2 2 DDR_A_CKE0 <6> DDR_A_CKE0 D S DIMM_DRAMRST# 1 Q2 BSS138LT1G_SOT23-3 3 G C <18> RST_GATE DIMM_DRAMRST# <11> DDR_A_BS2 <6> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 C617 2 RST_GATE 1 DDR_A_MA8 DDR_A_MA5 2 0.047U_0402_16V7K DDR_A_MA3 DDR_A_MA1 DDR_A_CLK0 DDR_A_CLK0# <6> DDR_A_CLK0 <6> DDR_A_CLK0# DDR_A_MA10 DDR_A_BS0 <6> DDR_A_BS0 DDR_A_WE# DDR_A_CAS# <6> DDR_A_WE# <6> DDR_A_CAS# DDR_A_MA13 DDR_A_CS1# <6> DDR_A_CS1# DDR_A_D32 DDR_A_D33 Layout Note: Place near JDIMM1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_A_D40 DDR_A_D41 B +1.5V DDR_A_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43 1 10U_0805_6.3V6M C138 2 C139 2 10U_0805_6.3V6M 1 C140 2 1 C141 2 10U_0805_6.3V6M 1 C142 2 10U_0805_6.3V6M 1 1 2 2 C143 0.1U_0402_16V4Z 1 2 C144 1 C145 2 1 + C146 DDR_A_D48 DDR_A_D49 @ C147 330U_2.5V_M_R15 2 C137 1 2 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 Layout Note: Place near JDIMM1.203 & JDIMM1.204 R109 1 2 10K_0402_5% C148 2.2U_0603_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1 2 2 C149 1 +3VS +0.75VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 R110 205 0.1U_0402_16V4Z DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 10K_0402_5% CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 C150 2 1 C151 2 1 C152 2 C153 1 1 2 2 DDR_A_MA11 DDR_A_MA7 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# 4 3 2010/08/01 2 +DIMM_VREFCA DDR_A_ODT1 <6> DDR_VREF_CA_DIMMA R108 1 2 0_0402_5% DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 C135 2.2U_0603_6.3V6K DDR_A_D44 DDR_A_D45 1 1 2 2 C136 0.1U_0402_16V4Z B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 <5,11> D_CK_SDATA <11,12> D_CK_SCLK <11,12> +0.75VS 206 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 DDR_A_CS0# <6> DDR_A_ODT0 <6> DDR_A_ODT1 FOX_AS0A626-U8RN-7F Deciphered Date DDR_A_BS1 <6> DDR_A_RAS# <6> DDR_A_CS0# DDR_A_ODT0 Compal Secret Data 2009/08/01 Issued Date DDR_A_CLK1 <6> DDR_A_CLK1# <6> DDR_A_BS1 DDR_A_RAS# 10U_0805_6.3V6M 1U_0402_6.3V6K C DDR_A_MA6 DDR_A_MA4 C154 Security Classification 1U_0402_6.3V6K DDR_A_CKE1 <6> DDR_A_MA15 DDR_A_MA14 2 A 1 D DDR_A_DM1 DIMM_DRAMRST# R103 1K_0402_1% <5> SM_DRAMRST# 1 +1.5V Title DDR3 SO-DIMM A Change to Reverse Type 8mm High Compal Electronics, Inc. A DDRIII-SODIMM SLOT1 Size Document Number Custom PEW71 M/B LA-6582P Date: Rev 1.0 Schematic Thursday, July 08, 2010 Sheet 1 10 of 48 5 4 3 2 1 +1.5V +1.5V JDIMM2 2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details <6> DDR_B_DQS#[0..7] <6> DDR_B_D[0..63] <6> DDR_B_DM[0..7] +DIMM_VREFDQB DDR_B_D0 DDR_B_D1 DDR_B_DM0 <6> DDR_B_DQS[0..7] DDR_B_D2 DDR_B_D3 <6> DDR_B_MA[0..15] DDR_B_D8 DDR_B_D9 D M1 Circuit DDR_B_DQS#1 DDR_B_DQS1 +DIMM_VREFDQB DIMMB VREFDQ M1 Circuit DDR_B_D10 DDR_B_D11 +1.5V 1 C155 +DIMM_VREFDQB R113 2.2U_0603_6.3V6K 1 C156 2 1 DDR_B_D16 DDR_B_D17 2 DDR_B_DQS#2 DDR_B_DQS2 2 1K_0402_1% DDR_B_D18 DDR_B_D19 1 0.1U_0402_16V4Z DDR_B_D24 DDR_B_D25 R114 1K_0402_1% 2 DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_B_CKE0 <6> DDR_B_CKE0 DDR_B_BS2 <6> DDR_B_BS2 C DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_CLK0 DDR_B_CLK0# <6> DDR_B_CLK0 <6> DDR_B_CLK0# DDR_B_MA10 DDR_B_BS0 <6> DDR_B_BS0 DDR_B_WE# DDR_B_CAS# <6> DDR_B_WE# <6> DDR_B_CAS# Layout Note: Place near JDIMM2 DDR_B_MA13 DDR_B_CS1# <6> DDR_B_CS1# Layout Note: Place these 4 Caps near Command and Control signals of DIMMB DDR_B_D32 DDR_B_D33 +1.5V 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_DQS#4 DDR_B_DQS4 0.1U_0402_16V4Z DDR_B_D34 DDR_B_D35 1 10U_0805_6.3V6M C159 1 C160 10U_0805_6.3V6M 2 1 C161 2 1 C162 2 1 C163 2 1 C164 2 1 C165 2 1 2 C166 1 C167 2 1 C168 2 1 2 + C169 330U_2.5V_M_R15 DDR_B_D40 DDR_B_D41 2 B DDR_B_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_D42 DDR_B_D43 0.1U_0402_16V4Z DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 Layout Note: Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 +0.75VS DDR_B_DM7 1U_0402_6.3V6K 1U_0402_6.3V6K DDR_B_D58 DDR_B_D59 1 1 1 1 1 C174 R116 1 +3VS C170 2 C171 2 C172 2 C173 2 2 1 10U_0805_6.3V6M R117 C175 A 2.2U_0603_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 1 2 C176 0.1U_0402_16V4Z 2 10K_0402_5% VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 205 G1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 4 2009/08/01 3 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 D DDR_B_DM1 DIMM_DRAMRST# 2010/08/01 Deciphered Date 2 DIMM_DRAMRST# <10> DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_B_CKE1 DDR_B_CKE1 <6> DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_CLK1 DDR_B_CLK1# DDR_B_CLK1 <6> DDR_B_CLK1# <6> DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 <6> DDR_B_RAS# <6> DDR_B_CS0# DDR_B_ODT0 DDR_B_CS0# <6> DDR_B_ODT0 <6> DDR_B_ODT1 DDR_B_ODT1 <6> DDR_VREF_CA_DIMMB R115 1 +DIMM_VREFCA 2 0_0402_5% DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 C157 2.2U_0603_6.3V6K DDR_B_D44 DDR_B_D45 1 1 2 2 C158 0.1U_0402_16V4Z B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 <5,10> D_CK_SDATA <10,12> D_CK_SCLK <10,12> +0.75VS DDR3 SO-DIMM B Reverse Type 4mm High FOX_AS0A626-U4RN-7F CONN@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 DDR_B_D4 DDR_B_D5 Compal Secret Data Security Classification Issued Date 2 10K_0402_5% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Title A Compal Electronics, Inc. DDRIII-SODIMM SLOT2 Size Document Number Rev 1.0 PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 11 of 48 A B C D E F G H +CLK_3VS +CLK_1.05VS +1.05VS L1 2 1 FBMA-L11-201209-221LMA30T_0805 1 C178 C177 10U_0805_10V4Z 10U_0805_10V4Z 2 2 1 change to +1.05VS 20100429 1 0.1U_0402_16V4Z 1 1 C179 2 C180 1 C181 0.1U_0402_16V4Z C182 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z L2 2 1 FBMA-L11-201209-221LMA30T_0805 +3VS Del 3G solution 1 1 2 2 10U_0805_10V4Z C183 1 C184 2 1 Del 3G solution 0.1U_0402_16V4Z Del L3 +CLK_1.5VS 0.1U_0402_16V4Z L4 2 1 FBMA-L11-201209-221LMA30T_0805 +1.5VS 1 2 C186 C185 10U_0805_10V4Z 10U_0805_10V4Z 1 1 2 2 C187 1 1 C188 2 0.1U_0402_16V4Z C189 2 Del 3G solution 0.1U_0402_16V4Z +CLK_3VS 2 2 +CLK_3VS Clock Generator +CLK_1.5VS U3 <14> CLK_BUF_DREF_96M <14> CLK_BUF_DREF_96M# For Cardreader CLK_BUF_DREF_96M CLK_BUF_DREF_96M# 1 R119 <29> CLK_SD_48M <14> CLK_BUF_PCIE_SATA <14> CLK_BUF_PCIE_SATA# <14> CLK_BUF_CPU_DMI <14> CLK_BUF_CPU_DMI# 1 2 3 4 5 6 7 8 2 33_0402_5% CLK_SD_48M_R CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# +CLK_1.05VS H_STP_CPU# 9 10 11 12 13 14 15 16 33 VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL R118 1 D_CK_SCLK <10,11> D_CK_SDATA <10,11> CLK_BUF_ICH_14M <14> 2 33_0402_5% CLK_XTAL_IN CLK_XTAL_OUT CK505_PW RGD CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK# CLK_BUF_CPU_BCLK <14> CLK_BUF_CPU_BCLK# <14> +CLK_1.05VS +CLK_1.5VS IDT SA00003HR00 TGND SLG8SP587VTR_QFN32_5X5 IDT: 9LRS3199AKLFT, SA000030P00 3 3 SILEGO: SLG8SP587V(WF), SA00002XY10 +3VS Low Power: 2 IDT: 9LVS3199AKLFT, SA00003HR00 R120 10K_0402_5% Realtek: RTM890N-631-GRT, SA00003HQ00 R123 4.7K_0402_5% 1 2 2 2 10K_0402_5% H_STP_CPU# <14,26> PCH_SMBDATA 6 D_CK_SDATA 1 R122 0_0402_5% @ 1 2 CK505_PW RGD VGATE <15,45> D +3VS S 3 R121 1 1 +3VS Silego Have Internal Pull-Up 1 +3VS Q4A 2N7002DW -T/R7_SOT363-6 2 G Q5 2N7002_SOT23 CLK_ENABLE# <45> +3VS R125 4.7K_0402_5% 1 2 +3VS 2 10K_0402_5% REF_0/CPU_SEL <14,26> PCH_SMBCLK 3 4 CLK_XTAL_IN D_CK_SCLK PIN 30 CPU_0 CPU_1 0 (Default) 133MHz 133MHz 1 100MHz Change to 2N7002DW 20100416 Issued Date 100MHz Change to 5x3.2 CLK_XTAL_OUT 2009/08/01 B C D Deciphered Date E Y1 Change to SJ100009R00 20091117 2 C191 1 4 33P_0402_50V8J Compal Electronics, Inc. 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 33P_0402_50V8J Compal Secret Data Security Classification C190 1 Y1 14.31818MHZ 20PF 7A14300003 Q4B 2N7002DW -T/R7_SOT363-6 4 2 1 R124 1 2 5 IDT Have Internal Pull-Down F Title Clock Generator (CK505) Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 G Sheet 12 of H 48 Rev 1.0 5 4 2 C192 18P_0402_50V8J 2 1 PCH_RTCX1 X1 Change to mini type 20091102 OSC 2 NC OSC 1 2 REV1.0 2 C195 2 1 B13 D13 PCH_RTCX2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# C34 LPC_FRAME# LDRQ0# LDRQ1# / GPIO23 A34 F34 SERIRQ AB9 SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_DTX_C_PRX_N0 <25> SATA_DTX_C_PRX_P0 <25> SATA SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25> SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_DTX_C_PRX_N1 <25> SATA_DTX_C_PRX_P1 <25> SATA SATA_PTX_DRX_N1 <25> SATA_PTX_DRX_P1 <25> SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# R134 1 2 330K_0402_1% PCH_INTVRMEN A14 INTVRMEN HDA_BITCLK_PCH A30 HDA_BCLK HDA_SYNC_PCH D29 HDA_SYNC <33> HDA_BITCLK_AUDIO R135 <33> HDA_SYNC_AUDIO R131 1 2 33_0402_5% 2 33_0402_5% 1 <33> PCH_SPKR <33> HDA_RST_AUDIO# R137 1K_0402_5% @ 1 2 R136 1 2 33_0402_5% PCH_SPKR P1 HDA_RST_PCH# <33> HDA_SDIN0 PCH_SPKR SPKR C30 HDA_RST# G30 HDA_SDIN0 F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3 HDA_SDOUT_PCH B29 HDA_SDO PCH_GPIO33# H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 M3 JTAG_TCK Have internal PD C 1 2 R138 10K_0402_5% SERIRQ <33> HDA_SDOUT_AUDIO R139 If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door. 1 PCH_JTAG_TCK PCH_JTAG_TCK K3 JTAG_TMS PCH_JTAG_TDI K1 JTAG_TDI PCH_JTAG_TDO J2 JTAG_TDO J4 TRST# PCH_JTAG_TMS D 2 G Q7 S 2N7002_SOT23 3 1 R140 100K_0402_5% 2 33_0402_5% GPIO33 can not pull down (manufacturing environments) PCH_GPIO33# <30> ME_OVERRIDE 1 LPC R133 1 INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Internal VRs HDA for AUDIO +3VS SRTCRST# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 <30> <30> <30> <30> PCH_SPI_CLK_1 R142 1 PCH_SPI_CS0# R143 1 T6 PAD PCH_SPI_CLK 2 15_0402_5% PCH_SPI_CS0#_R AV3 @ BA2 PCH_SPI_CS1# LPC_FRAME# <30> SERIRQ <30> +RTCBATT for HDD1 @ JBATT1 for ODD 2/10 SATA2, SATA3 not support on HM55 SUYIN_060003HA002G202ZL C 20100416 add GPIO21 0 1 SATAICOMPO AF16 SATAICOMPI AF15 SATA_COMP R141 1 2 37.4_0402_1% dGPU iGPU SG +3VS SPI_CLK R144 1 SPI_CS0# AY3 D Project NEW50/70/80/90 NEW71/91 +1.05VS SATALED# T3 SATA_LED# SATA0GP / GPIO21 Y9 PCH_GPIO21 SATA1GP / GPIO19 V1 PCH_GPIO19 SPI_CS1# 2 10K_0402_5% SATA_LED# <32> GPIO19 GPIO37 PCH_GPIO19 VGA_PRSNT_L# 0 0 1 0 1 X +3VS B PCH_SPI_MOSI AY1 PCH_SPI_MISO_1 R147 1 2 33_0402_5% PCH_SPI_MISO SPI_MOSI AV1 SPI_MISO R146 R148 IBEXPEAK-M_FCBGA107 R149 PCH_SPI_MOSI R157 1 @ @ 1 @ 2 10K_0402_5% 2 10K_0402_5% R150 2 10K_0402_5% 2 10K_0402_5% +3VS 1 1 2 15_0402_5% 1 PCH_SPI_MOSI_1 R145 1 SPI B GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manfacturing/ debug. 2 0_0402_5% 2 1K_0402_5% 20100421 Modify 2 PCH_JTAG_RST# SATA modify to 330K D17 IHDA 1 2 R130 @ 10K_0603_5% C194 1U_0402_6.3V6K 1 2 RTCRST# PCH_SRTCRST# JTAG close to RAM door C14 RTC +RTCVCC RC Delay 18~25mS PCH_RTCRST# 1 3 1 R129 DAN202UT106_SC70-3 D33 B33 C32 A32 RTCX1 RTCX2 18P_0402_50V8J PCH_SRTCRST# 1 2 R132 20K_0402_1% +RTCBATT D1 U4A 10M_0402_5% 32.768KHZ_12.5PF_Q13MC14610002 D +CHGRTC +RTCVCC R128 1 NC 4 + 3 - 1 2 R127 @ 10K_0603_5% C193 1U_0402_6.3V6K 1 2 1 X1 2 RC Delay 18~25mS close to RAM door +RTCVCC 1 PCH_RTCRST# 1 2 R126 20K_0402_1% +RTCVCC 3 2 1K_0402_5% enable iTPM: SPI_MOSI High +1.05VS PCH_JTAG_TCK +3VALW R158 2 4.7K_0402_5% 1 CRB 1.0 Change to 4.7K +3VS PCH_JTAG_TMS R151 1 R478 1 R479 1 @ PCH_JTAG_TDO R152 1 R480 1 R481 1 @ 2 51_0402_5% 2 200_0402_1% 2 100_0402_5% PCH_JTAG_TDI R153 1 R482 1 R483 1 @ 2 51_0402_5% 2 200_0402_1% 2 100_0402_5% PCH_JTAG_RST# R154 1 R484 1 R485 1 @ 2 51_0402_5% 2 20K_0402_5% 2 10K_0402_5% A 2 51_0402_5% 2 200_0402_1% 2 100_0402_5% U18 +3VS R155 1 R156 1 2 3.3K_0402_5% 2 3.3K_0402_5% PCH_SPI_CS0# SPI_W P1# SPI_HOLD1# 1 3 7 4 @ CS# WP# HOLD# GND VCC SCLK SI SO 8 6 5 2 PCH_SPI_CLK_1 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1 For 3G team Close to U5 @ 2 1 10_0402_5% C557 2 10P_0402_50V8J 20090915 MX25L1605DM2I-12G SOP 8P SA000021A00 A SPI ROM Footprint 200mil Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 R340 4 3 2 Title PCH (1/9) SATA,HDA,SPI, LPC Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 13 of 48 Rev 1.0 4 3 2 1 U4B BA32 BB32 BD32 BE32 PERN4 PERP4 PETN4 PETP4 BF33 BH33 BG32 BJ32 PERN5 PERP5 PETN5 PETP5 BA34 AW34 BC34 BD34 PERN6 PERP6 PETN6 PETP6 AT34 AU34 AU36 AV36 PERN7 PERP7 PETN7 PETP7 BG34 BJ34 BG36 BJ36 PERN8 PERP8 PETN8 PETP8 C AK48 AK47 <27> CLK_PCIE_LAN# <27> CLK_PCIE_LAN For PCIE LAN <27> LAN_CLKREQ# R164 1 <26> MINI1_CLKREQ# R165 1 For Wireless LAN 2 0_0402_5% PCH_GPIO73 AM43 AM45 <26> CLK_PCIE_MINI1# <26> CLK_PCIE_MINI1 2 0_0402_5% P9 PCH_GPIO18 U4 AM47 AM48 PCH_GPIO20 N4 AH42 AH41 PCH_GPIO25 A8 AM51 AM53 B PCH_GPIO26 M9 AJ50 AJ52 PCH_GPIO44 H6 AK53 AK51 PCH_GPIO56 +3VS P13 PCH_SMBDATA PCH_SMBDATA <12,26> J14 PCH_GPIO60 SML0CLK C6 SML0DATA G8 D M14 PCH_GPIO74 SML1CLK / GPIO58 E10 PCH_SML1CLK SML1DATA / GPIO75 G12 PCH_SML1DAT CL_CLK1 T13 +3VALW CL_DATA1 T11 CL_RST1# T9 PEG_A_CLKRQ# / GPIO47 H1 Link SML1ALERT# / GPIO74 2 SMBus PCH_SMBCLK <12,26> C8 EC_LID_OUT# <30> R159 10K_0402_5% PEG_CLKREQ# 20090915 Add CLKOUT_PEG_A_N CLKOUT_PEG_A_P AD43 AD45 CLKOUT_DMI_N CLKOUT_DMI_P AN4 AN2 CLK_CPU_DMI# <5> CLK_CPU_DMI <5> CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AT1 AT3 CLK_CPU_DP# <5> CLK_CPU_DP <5> C CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P CLKOUT_PCIE3N CLKOUT_PCIE3P AP3 AP1 CLK_BUF_CPU_BCLK# <12> CLK_BUF_CPU_BCLK <12> CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DREF_96M# <12> CLK_BUF_DREF_96M <12> AH13 AH12 P41 CLKIN_PCILOOPBACK 2 1 10_0402_5% C555 PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P J42 XTAL25_IN XTAL25_OUT AH51 AH53 XCLK_RCOMP AF38 CLKOUTFLEX0 / GPIO64 T45 6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics CLK_BUF_PCIE_SATA# <12> CLK_BUF_PCIE_SATA <12> 1 R338 2 10P_0402_50V8J CLK_BUF_ICH_14M CLKOUT_PCIE4N CLKOUT_PCIE4P PEG_B_CLKRQ# / GPIO56 CLKIN_BCLK_N CLKIN_BCLK_P REFCLK14IN PCIECLKRQ3# / GPIO25 CLKOUT_PEG_B_N CLKOUT_PEG_B_P CLK_BUF_CPU_DMI# <12> CLK_BUF_CPU_DMI <12> CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 PCIECLKRQ5# / GPIO44 AW24 BA24 CLKIN_DMI_N CLKIN_DMI_P <12> CLK_PCI_FB <17> C203 27P_0402_50V8J 1 2 XTAL25_IN XTAL25_OUT XCLK_RCOMP R169 1 2 90.9_0402_1% +3VS Project Port ID CLKOUTFLEX1 / GPIO65 P43 PROJECT_ID1 CLKOUTFLEX2 / GPIO66 T42 PROJECT_ID0 CLKOUTFLEX3 / GPIO67 N50 R170 1M_0402_5% +1.05VS 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% +3VS 0602 GPIO65 no use PULL HIGH:PVT PULL DOWN:DVT +3VALW 6 1 A +3VALW 2009/09/23:Change to +3VALW PCH_GPIO26 R166 1 2 10K_0402_5% PCH_GPIO25 R186 1 2 10K_0402_5% 2009/08/13: Change back to +3VALW 5 2 10K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% PCH_GPIO60 R182 1 2 10K_0402_5% PCH_SML1CLK PCH_SML1DAT R183 1 R184 1 2 2.2K_0402_5% 2 2.2K_0402_5% PCH_GPIO74 R185 1 2 10K_0402_5% PCH_GPIO44 PCH_GPIO56 PCH_GPIO73 R187 1 R188 1 R189 1 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% GPIO66 6L/8L SATA register separe GPIO66 4 0 1 6L * 8L PCH_SML1DAT 2009/08/01 Issued Date Deciphered Date 3 4 EC_SMB_DA2 EC_SMB_DA2 <30> Compal Electronics, Inc. 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 Pull high +3VS at KB926 side 2N7002DW -T/R7_SOT363-6 Q9B Compal Secret Data Security Classification EC_SMB_CK2 <30> 5 R179 1 R180 1 R181 1 EC_SMB_CK2 2N7002DW -T/R7_SOT363-6 Q9A +3VS EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA 2 C204 27P_0402_50V8J PCH_SML1CLK 2 10K_0402_5% 2 10K_0402_5% Change to 5x3.2 1 R171 1 1 @ R172 @ R174 1 1 R175 IBEXPEAK-M_FCBGA107 MINI1_CLKREQ# R177 1 PCH_GPIO20 R178 1 B Y2 25MHZ_20PF_7A25000012 2 2/10 PCIE7, PCIE8 not support on HM55 SML0ALERT# / GPIO60 PCH_SMBCLK 2 PERN3 PERP3 PETN3 PETP3 H14 1. Connect Directly EXPRESS CARD, MINI1, MINI2 2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2 3. Level Shift2, Pull-Up to +3VS LAN 4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP 1 AU30 AT30 AU32 AV32 D SMBDATA EC_LID_OUT# 2 PERN2 PERP2 PETN2 PETP2 SMBCLK B9 1 1 1 SMBALERT# / GPIO11 Controller C199 2 C200 2 PCIE_DTX_C_PRX_N2 AW30 PCIE_DTX_C_PRX_P2 BA30 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PERN1 PERP1 PETN1 PETP1 PEG PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 1 1 PCI-E* <26> <26> <26> <26> C197 2 C198 2 From CLK BUFFER For Wireless LAN PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 BG30 BJ30 BF29 BH29 Clock Flex <27> <27> <27> <27> For PCIE LAN REV1.0 PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 0.1U_0402_16V7K PCIE_PTX_DRX_P1 1 5 2 Title PCH (2/9) PCIE, SMBUS, CLK Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 14 of 48 Rev 1.0 A 5 4 1 PM_CLKRUN# 2 8.2K_0402_5% +3VALW +1.05VS SUS_PW R_ACK 2 10K_0402_5% PCH_GPIO72 2 8.2K_0402_5% EC_SW I# 2 10K_0402_5% PCH_PCIE_W AKE# 2 10K_0402_5% PM_SLP_LAN# 2 10K_0402_5% R192 49.9_0402_1% 1 2 DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP BH25 DMI_COMP DMI_ZCOMP BF25 SYS_PW ROK VGATE R197 2 R198 2 @ 1 0_0402_5% 1 0_0402_5% BH13 H_FDI_FSYNC1 <4> FDI_LSYNC0 BJ12 H_FDI_LSYNC0 <4> FDI_LSYNC1 BG14 H_FDI_LSYNC1 <4> M6 SYS_PWROK B17 PWROK MEPWROK A10 LAN_RST# D9 DRAMPWROK C16 RSMRST# SUS_PW R_ACK M1 PBTN_OUT# P5 PCH_ACIN P7 ACPRESENT / GPIO31 PCH_GPIO72 A6 BATLOW# / GPIO72 J12 PCH_PCIE_W AKE# CLKRUN# / GPIO32 Y1 PM_CLKRUN# SUS_STAT# / GPIO61 P8 PCH_GPIO61 SUSCLK / GPIO62 F3 PCH_SUSCLK <30> SLP_S5# / GPIO63 E4 PM_SLP_S5# <30> SLP_S4# H7 PM_SLP_S4# <30> SLP_S3# P12 SLP_M# K8 PM_SLP_M# @ PAD T9 TP23 N2 PM_SLP_DSW # @ PAD T10 SUS_PWR_DN_ACK / GPIO30 PWRBTN# 1 R199 <30> EC_SW I# FDI_FSYNC1 PCH_PCIE_W AKE# D H_FDI_TXN[0..7] <4> H_FDI_TXP[0..7] <4> <4> <4> C <26,27> PM_CLKRUN# <30> @ PAD T7 32.768KHZ ouput for remove EC crystal 20091103 PM_SLP_S3# <30> B @ 1 0_0402_5% R200 2 Q11 MMBT3906_SOT23-3 PCH_RSMRST# 1 3 EC_SW I# F14 PMSYNCH RI# SLP_LAN# / GPIO29 BJ10 F6 H_PM_SYNC <5> R201 10K_0402_5% PM_SLP_LAN# IBEXPEAK-M_FCBGA107 R203 2 @ 1 R202 6 2 D3B P U6 EC_PW ROK G 5 BAV99DW -7_SOT363 2 A 1 VGATE Y 4 3 EC_PW ROK <30> 5 VGATE <12,45> BAV99DW -7_SOT363 SYS_PW ROK 1 R205 2 10K_0402_5% EC_PW ROK 1 R206 2 10K_0402_5% LAN_RST# 1 R207 2 10K_0402_5% 2 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 A Compal Electronics, Inc. Compal Secret Data Security Classification No used Integrated LAN, connecting LAN_RST# to GND 5 R204 2.2K_0402_5% MC74VHC1G08DFT2G_SC70-5 U6 change to SA00000OH00 A +3VALW 1 1 0_0402_5% B 3 4 2 4.7K_0402_5% D3A +3VS SYS_PW ROK EC_RSMRST# <30> E <30> EC_ACIN H_FDI_FSYNC0 SYS_PW ROK_R PCH_RSMRST# <30> PBTN_OUT# 2 10K_0402_5% 2 D2 CH751H-40PT_SOD323-2 H_FDI_INT BF13 WAKE# <5> PM_DRAM_PW RGD 1 BJ14 SYS_RESET# LAN_RST# +3VALW FDI_INT FDI_FSYNC0 T6 K5 <30> SUS_PW R_ACK H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 XDP_DBRESET# SYS_PW ROK 10/2 R199 Intel suggestion change to 10K BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 DMI_IRCOMP R195 Change to 10K for WW37 20090916 <5> XDP_DBRESET# FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 H_FDI_TXP[0..7] 1 1 R191 1 R193 1 R194 1 R195 1 @ R196 DMI0RXP DMI1RXP DMI2RXP DMI3RXP H_FDI_TXN[0..7] 2 1 R190 BD24 BG22 BA20 BG20 H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 C +3VS DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 2 B DMI_PTX_HRX_P[0..3] <4> DMI_PTX_HRX_P[0..3] System Power Management <4> DMI_PTX_HRX_N[0..3] FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 1 DMI_PTX_HRX_N[0..3] DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI DMI_HTX_PRX_P[0..3] <4> DMI_HTX_PRX_P[0..3] REV1.0 DMI_HTX_PRX_N0 BC24 DMI_HTX_PRX_N1 BJ22 DMI_HTX_PRX_N2 AW20 DMI_HTX_PRX_N3 BJ20 DMI DMI_HTX_PRX_N[0..3] <4> DMI_HTX_PRX_N[0..3] B 2 U4C D C 3 2 Title PCH (3/9) DMI, FDI, PM Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 15 of 48 Rev 1.0 5 4 3 2 1 U4D <22> DPST_PW M R209 100K_0402_5% 2 <22> PCH_LCD_CLK <22> PCH_LCD_DATA L_DDC_CLK L_DDC_DATA LCTLA_CLK LCTLB_DATA AB46 V48 L_CTRL_CLK L_CTRL_DATA LVDS_IBG AP39 AP41 LVD_IBG LVD_VBG R211 1 0_0402_5% 2 LVD_VREF AT43 AT42 LVD_VREFH LVD_VREFL C R216 1 2 10K_0402_5% LCTLB_DATA R217 1 2 2.2K_0402_5% PCH_CRT_CLK R218 1 2 2.2K_0402_5% PCH_CRT_DATA R219 R220 R221 <22> PCH_TXOUT0+ <22> PCH_TXOUT1+ <22> PCH_TXOUT2+ 1 2 1 2 1 2 PCH_CRT_B 150_0402_1% PCH_CRT_G 150_0402_1% PCH_CRT_R 150_0402_1% <23> PCH_CRT_B <23> PCH_CRT_G <23> PCH_CRT_R <23> PCH_CRT_CLK <23> PCH_CRT_DATA SDVO_TVCLKINN SDVO_TVCLKINP LVDSA_CLK# LVDSA_CLK PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2- BB47 BA52 AY48 AV47 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AP48 AP47 LVDSB_CLK# LVDSB_CLK AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED PCH_CRT_CLK PCH_CRT_DATA <23> PCH_CRT_HSYNC <23> PCH_CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA Y53 Y51 CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN SDVO_INTN SDVO_INTP D T51 T53 SDVO_SCLK <24> SDVO_SDATA <24> R212 1 DDPB_AUXN DDPB_AUXP DDPB_HPD BG44 BJ44 AU38 PCH_DPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 2 100K_0402_5% PCH_DPB_HPD C205 C206 C207 C208 C209 C210 C211 C212 2 2 2 2 2 2 2 2 1HDMI@ 1HDMI@ 1HDMI@ 1HDMI@ 1HDMI@ 1HDMI@ 1HDMI@ 1HDMI@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K <24> PCH_TMDS_D2# <24> PCH_TMDS_D2 <24> PCH_TMDS_D1# <24> PCH_TMDS_D1 <24> PCH_TMDS_D0# <24> PCH_TMDS_D0 <24> PCH_TMDS_CK# <24> PCH_TMDS_CK <24> HDMI D2 HDMI D1 HDMI D0 HDMI CLK C DDPD_CTRLCLK DDPD_CTRLDATA V51 V53 CRT_IREF AD48 AB51 B BJ48 BG48 BF45 BH45 SDVO_CTRLDATA strap Pull High at Level Shift Page AV53 AV51 PCH_CRT_B PCH_CRT_G PCH_CRT_R BJ46 BG46 SDVO_STALLN SDVO_STALLP SDVO_CTRLCLK SDVO_CTRLDATA PCH_TXCLKPCH_TXCLK+ +3VS LCTLA_CLK L_BKLTCTL AB48 Y45 2 <22> PCH_TXOUT0<22> PCH_TXOUT1<22> PCH_TXOUT2- 2 10K_0402_5% Y48 PCH_LCD_CLK PCH_LCD_DATA R210 1 2.37K_0402_1% <22> PCH_TXCLK<22> PCH_TXCLK+ R215 1 L_BKLTEN L_VDD_EN Digital Display Interface D T48 T47 LVDS ENBKL 1 <30> ENBKL <22> PCH_ENVDD CRT ENBKL REV1.0 U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 B 1 IBEXPEAK-M_FCBGA107 2 R222 1K_0402_1% 2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect) A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (4/9) LVDS, CRT, DPI Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 16 of 48 Rev 1.0 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% PCI_PLOCK# PCI_PERR# PCI_PIRQE# PCI_STOP# R228 R235 R236 R237 1 1 1 1 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3# R243 R244 R245 R246 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% PCI_IRDY# PCI_PIRQD# DGPU_SELECT# PCI_DEVSEL# PCI_FRAME# PCI_REQ1# PCI_PIRQH# PCI_TRDY# PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3# A16 swap overide Strap/Top-Block Swap Override jumper Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default * T11 PAD PCI_GNT0# PCI_GNT1# @ DGPU_PW MSEL# PCI_GNT3# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# T12 PAD @ TP_PCI_RST# PCI_SERR# PCI_PERR# PCI_IRDY# B <5,27,30> PLT_RST# <30> CLK_PCI_LPC <14> CLK_PCI_FB R252 R253 1 1 2 22_0402_5% 2 22_0402_5% C/BE0# C/BE1# C/BE2# C/BE3# G38 H51 B37 A44 F51 A46 B45 M53 PCI_GNT#0 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 * Boot BIOS Location 0 0 LPC 0 1 Reserved (NAND) 1 0 PCI 1 1 SPI PCI_DEVSEL# PCI_FRAME# PCI_PLOCK# D49 PLOCK# PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 PME# D5 PLTRST# PLT_RST# CLK_PCI_LPC_R CLK_PCI_FB_R N52 P53 P46 P51 P48 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 NV_ALE NV_CLE BD3 AY6 NV_RCOMP AU2 NV_RB# AV7 NV_WR#0_RE# NV_WR#1_RE# AY8 AY5 U7 change to SA00000OH00 PLT_RST# Y A MC74VHC1G08DFT2G_SC70-5 4 PLT_RST_BUF# <26> R226 100K_0402_5% D NV_ALE NV_CLE NV_RCOMP R239 1 @ +1.8VS 2 32.4_0402_1% NV_ALE R247 1 @ 2 1K_0402_5% NV_CLE R248 1 @ 2 1K_0402_5% AV11 BF5 Intel Anti-Theft Techonlogy USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USBRBIAS# B25 USB_BIAS USBRBIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 <29> <29> <29> <29> <29> <29> NV_ALE USB/B (Left Side Low) DMI Termination Voltage USB/B (Right Side) USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N11 USB20_P11 USB20_N12 USB20_P12 <22> <22> <29> <29> <29> <29> <26> <26> Set to Vcc when HIGH NV_CLE Set to Vss when LOW NV_ALE Enable Intel Anti-Theft Technology 8.2K PU to +3VS 2/10 USB6, USB7 not support on HM55 USB20_N8 USB20_P8 USB20_N9 USB20_P9 C USB Port (Left Side High) EHCI 1 USB20_N8 USB20_P8 USB20_N9 USB20_P9 High=Endabled Low=Disable(floating) * ： ： Disable Intel Anti-Theft Technology floating(internal PD) CMOS Camera (LVDS) Card Reader Del SIM Card USB NV_CLE DMI termination voltage. weak internal PU, don't PD EHCI 2 Bluetooth Mini Card(WLAN) Del 3G Card USB B CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 1 2 R249 22.6_0402_1% USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R R250 1 2 0_0402_5% USB_OC#0 <29> (For USB Port0, 2) R251 1 2 0_0402_5% USB_OC#2 <29> (For USB Port1) R254 1 @ 2 1K_0402_5% @ 2 1K_0402_5% @ 2 1K_0402_5% RP1 USB_OC#3_R USB_OC#5_R USB_OC#6_R USB_OC#7_R OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2 R256 1 1 2 3 4 8 7 6 5 +3VALW 10K_1206_8P4R_5% Have internal PU PCI_GNT1# U7 2 B 1 IBEXPEAK-M_FCBGA107 USB_OC#1_R R255 1 2 10K_0402_5% USB_OC#4_R R257 1 2 10K_0402_5% Have internal PU PCI_GNT3# R258 1 A Have internal PU 2009/08/01 Issued Date Low = A16 swap High = Default Compal Electronics, Inc. Compal Secret Data Security Classification Swap Override jumper 5 SERR# PERR# IRDY# PAR DEVSEL# FRAME# A16 swap override Strap/Top-Block PCI_GNT#3 PCIRST# A42 H44 F46 C46 PCI_GNT0# PCI_GNT#1 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 B41 K53 A36 A48 2008/1/6 2009MOW01 change to 22 ohm Boot BIOS Strap PIRQA# PIRQB# PIRQC# PIRQD# GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 K6 AV9 BG8 NV_WE#_CK0 NV_WE#_CK1 F48 K45 F36 H53 E44 E50 NV_DQS0 NV_DQS1 +3VS 1 J50 G42 H47 G34 AY9 BD1 AP15 BD8 2 1 1 1 1 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 5 PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR# R230 R227 R231 R232 R238 R240 R241 R242 A 1 P 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% REV1.0 NVRAM 2 2 2 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 USB 1 1 1 1 H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 PCI R229 R223 R224 R225 C 2 U4E +3VS D 3 G 4 3 5 Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PCH (5/9) PCI, USB, VRAM Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 17 of 48 Rev 1.0 5 4 3 2 1 +3VS 2 10K_0402_5% DGPU_EDIDSEL# 2 10K_0402_5% DGPU_HPD_INT# R261 1 R262 1 2 10K_0402_5% VGA_PRSNT_R# 2 10K_0402_5% VGA_PRSNT_L# CRT_DET R263 1 @ 2 10K_0402_5% DGPU_HOLD_RST# DGPU_EDIDSEL# C38 TACH1 / GPIO1 R264 1 2 10K_0402_5% PCH_GPIO22 DGPU_HPD_INT# D37 TACH2 / GPIO6 R265 1 2 10K_0402_5% PCH_GPIO39 EC_SCI# J32 TACH3 / GPIO7 EC_SMI# F10 U4F GPIO8 R270 1 R271 1 2 10K_0402_5% PCH_GPIO48 2 10K_0402_5% PCH_TEMP_ALERT# DGPU_HOLD_RST# AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# <5> R300 1 2 10K_0402_5% DGPU_PW ROK_1 DGPU_PW ROK_1 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <5> R273 1 R274 1 2 10K_0402_5% PCH_GPIO34 2 10K_0402_5% EC_SCI# PCH_GPIO15 20090915 Add 2 10K_0402_5% PCH_GPIO12 2 10K_0402_5% EC_SMI# 2 1K_0402_5% PCH_GPIO15 (GPIO8 Should not be Pull-Low) T7 GPIO15 EC_GA20 LAN_PHY_PWR_CTRL / GPIO12 PCH_GPIO22 Y7 PCH_GPIO24 H10 GPIO24 PCH_GPIO27 AB12 GPIO27 PCH_GPIO28 V13 GPIO28 PCH_GPIO34 M11 STP_PCI# / GPIO34 SCLOCK / GPIO22 A20GATE PECI RCIN# CPU GPIO24 change PU +3VS to +3VALW 20090916 K9 GPIO PCH_GPIO12 U2 PROCPWRGD BE10 THRMTRIP# BD10 PCH_GPIO35 R268 1 @ 2 10K_0402_5% PCH_GPIO24 DGPU_PW R_EN AB7 SATA2GP / GPIO36 TP1 BA22 R280 R281 R282 R283 2 2 2 2 VGA_PRSNT_L# AB13 SATA3GP / GPIO37 TP2 AW22 VGA_PRSNT_R# V3 SLOAD / GPIO38 TP3 BB22 PCH_GPIO39 P3 SDATAOUT0 / GPIO39 TP4 AY45 PCH_GPIO45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46 RST_GATE F1 PCIECLKRQ7# / GPIO46 TP6 AV43 SDATAOUT1 / GPIO48 TP7 AV45 SATA5GP / GPIO49 TP8 AF13 PCH_GPIO28 PCH_GPIO57 PCH_GPIO45 RST_GATE R286 1 2 10K_0402_5% DGPU_HOLD_RST# R287 1 @ 2 10K_0402_5% DGPU_PW ROK_1 <10> RST_GATE R289 1 2 10K_0402_5% PCH_GPIO35 R290 1 @ 2 10K_0402_5% PCH_GPIO27 <30> PCH_TEMP_ALERT# PCH_GPIO57 GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable GPIO19 PCH_GPIO19 dGPU iGPU SG F8 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 GPIO37 VGA_PRSNT_L# 0 0 1 AB6 PCH_TEMP_ALERT# AA4 0 1 0 GPIO27 On-Die PLL Voltage Regulator This signal has a weak internal pull up ： voltage regulator enable ：On-Die On-Die PLL Voltage Regulator disable GPIO8 2 10K_0402_5% 2 10K_0402_5% EC_KBRST# <30> H_CPUPW RGD THRMTRIP_PCH# 2 R276 <5> H_THERMTRIP# 1 56_0402_5% 2 R278 H_THERMTRIP# <5> 1 56_0402_5% +1.05VS C MAINPW ON <37,38> R288 @ 330_0402_5% 1 2 +1.05VS C 2 B E 3 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R267 1 EC_KBRST# R269 1 H_PECI <5> EC_KBRST# SATACLKREQ# / GPIO35 GPIO57 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 RSVD 1 1 1 1 EC_GA20 <30> WW46 Platform/Design Updates 2008/11/17 54.9 1% ->56 5% 10/7 Not Use PCH_GPIO15 PU 1K to +3V V6 EC_GA20 BG10 T1 TP9 M18 TP10 N18 TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AA23 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 INIT3_3V# REV1.0 TP24 D +3VS 2 10K_0402_5% CRT_DET PCH_GPIO48 H L AF48 AF47 2 10K_0402_5% DGPU_PW R_EN R279 1 * CLKOUT_PCIE7N CLKOUT_PCIE7P R291 1 R275 1 R277 1 B AH45 AH46 R266 1 +3VALW C CLKOUT_PCIE6N CLKOUT_PCIE6P 1 <30> EC_SMI# BMBUSY# / GPIO0 MISC <30> EC_SCI# Y3 NCTF D R259 1 R260 1 @ Q12 2SC2411KT146_SOT23-3 H_THERMTRIP# B INIT3_3V P6 (Have internal PD,Do not pull high) C10 TP24_SST @ This signal has weak internal PU, can't pull low PAD T13 IBEXPEAK-M_FCBGA107 This signal has a weak internal pull up can't Pull low A ： GPIO15 L Intel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality * A ： H Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality Compal Electronics, Inc. Compal Secret Data Security Classification it have weak internal PU 20K 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (6/9) GPIO, CPU, MISC Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 18 of 48 Rev 1.0 5 4 3 2 +1.05VS C213 C214 2 2 Near AB24 Near AB24 Top Side Intel suggest follow CRB 8/21 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 C223 Near AN20 1 C224 2 Top Side 1U_0402_6.3V6K 1 C225 2 1U_0402_6.3V6K 1 1 C226 2 C227 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K Near AN35 +3VS Follow Intel suggestion 8/21 0.1U_0402_16V4Z C229 2 1 B +VCCVRM T21 PAD DG 1.6 (Page 329) Have Internal VRM @ +VCCAPLL_FDI +1.05VS AF53 VSSA_DAC[2] AF51 VCCALVDS AH38 VSSA_LVDS AH39 59mA VCC3_3[2] AB34 VCC3_3[3] AB35 VCC3_3[4] AD35 VCCAPLLEXP AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] AN30 AN31 VCCIO[54] VCCIO[55] AN35 VCC3_3[1] AT22 VCCVRM[1] BJ18 VCCFDIPLL AM23 LVDS 42mA AP43 AP45 AT46 AT45 VCCIO[1] HVCMOS BJ24 VCCIO[24] VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] C222 0.01U_0402_16V7K 1 C215 C216 2 C217 0.1U_0402_16V4Z 2 1 C221 22U_0805_6.3V6M 2 35mA VCCVRM[2] 3208mA 61mA 1 2 L5 MBK1608221YZF_2P 1 22U_0805_6.3V6M 2 VCCDMI[1] VCCDMI[2] AU16 156mA VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] D L5 Change to 220ohm bead 20091116 CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290) 2 0_0805_5% 1 L6 +VCCTX_LVDS C220 C218 1 1 1 0.01U_0402_16V7K 22U_0805_6.3V6M C219 0.01U_0402_16V7K 2 2 2 2 1 0.1UH_MLF1608DR10KT_10%_1608 0.1uH inductor, 200mA +3VS 1 C Near AB34 R296 1 @ 2 0_0805_5% +1.05VS R297 1 @ 2 0_0805_5% +1.5VS R298 1 2 0_0805_5% +1.8VS +1.05VS +VCC_DMI 1 R299 1 C228 1U_0402_6.3V6K 2 AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 60mA 220 ohm bead,350mA +1.8VS AT24 AT16 R293 Near AP43 +VCCVRM 6mA 1 Change to 0_0805_5% 20090923 0.1U_0402_16V4Z 2 DMI +1.05VS VSSA_DAC[1] +VCCADAC +VCCA_LVDS NAND / SPI C AE52 300mA PCI E* DG 1.6 (Page 329) Have Internal VRM AE50 VCCADAC[2] +3VS FDI @ +VCCAPLL_EXP T20 PAD VCCADAC[1] 69mA +1.05VS AK24 10U_0805_10V4Z 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1524mA VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] CRT 1U_0402_6.3V6K 1 VCC CORE 10U_0805_10V4Z 1 D +3VS For CRT Issue 20091105 Near AE50 POWER U4G 1 2 0_0402_5% Change to 0_0402 20090914 Near AT16 +1.8VS C230 1 B 0.1U_0402_16V4Z 2 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 Near AK13 +3VS C232 REV1.0 IBEXPEAK-M_FCBGA107 1 0.1U_0402_16V4Z 2 Near AM8 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (7/9) PWR Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 19 of 48 Rev 1.0 4 3 22U_0805_6.3V6M 1 1 C236 2 2 1U_0402_6.3V6K Near AD38 VCCME[2] AD41 VCCME[3] AF43 VCCME[4] AF41 VCCME[5] AF42 VCCME[6] V39 VCCME[7] V41 VCCME[8] Near V39 V42 VCCME[9] Y39 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails VCCME[10] Y41 VCCME[11] Y42 C249 0.1U_0402_16V4Z +VCCRTCEXT 1 2 Near V9 C AU24 +VCCVRM BB51 BB53 +VCCADPLLA +VCCADPLLB +1.05VS 1 C253 1U_0402_6.3V6K Near AH35 2 1 2 Near AF32 C255 2 +PCH_VCCIO 0_0603_5% 2 1 R337 1U_0402_6.3V6K 1 C254 1U_0402_6.3V6K Near AH23 B +3VALW +VCCSST 1 2 C257 Near 0.1U_0402_16V4Z V12 +VCCSUS 1 2 C260 Near 0.1U_0402_16V4Z Y22 C261 0.1U_0402_16V4Z V9 VCCME[12] DCPRTC VCCVRM[3] 72mA VCCADPLLA[1] VCCADPLLA[2] 73mA BD51 BD53 VCCADPLLB[1] VCCADPLLB[2] AH23 AJ35 AH35 VCCIO[21] VCCIO[22] VCCIO[23] AF34 VCCIO[2] AH34 C265 AF32 VCCIO[4] V12 DCPSST Y22 4.7U_0805_10V4Z C266 1 2 2 V5REF 357mA K49 VCC3_3[8] J38 VCC3_3[9] L38 VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 VCCSUS3_3[32] V15 VCC3_3[5] V16 VCC3_3[6] Y16 VCC3_3[7] AT18 A > 1mA AT18 V_CPU_IO[1] AU18 V_CPU_IO[2] A12 2mA VCCRTC +1.05VS +VCC5REFSUS IBEXPEAK-M_FCBGA107 C269 1U_0402_6.3V6K 2 C270 1 2 C271 +VCC5REF 5 4 1 1 2 + 1 @ C248 1U_0402_6.3V6K 2 +3VS +5VALW R305 2 100_0402_5% C250 1U_0402_6.3V6K 1 D5 CH751H-40PT_SOD323-2 R306 100_0402_5% 1 2 Near F24 Change to 1U for power sequence issue on ICH9 2 1 2/12 Follow EDS1.11 Change to 100 ohm C +5VS C251 1U_0402_6.3V6K Near K49 +3VS N36 VCC3_3[12] P36 C252 VCC3_3[13] U35 0.1U_0402_16V4Z 2 VCC3_3[14] AD13 1 +3VS Near J38 Near AD13 +VCCSATAPLL @ 2 C256 0.1U_0402_16V4Z PAD T23 DG 1.6 (Page 329) Have Internal VRM B VCCIO[9] AH22 VCCVRM[4] AT20 VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 1 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 C262 1U_0402_6.3V6K 2 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 +VCCVRM +1.05VS Near AB19 +1.05VS PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16 R309 R310 R311 R312 1 1 1 1 2 2 2 2 L30 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% +3VALW C268 1 A 2 1U_0402_6.3V6K Near L30 1 Near A12 Compal Electronics, Inc. Compal Secret Data Security Classification 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +VCCADPLLB Near BD51 1 +RTCVCC 1 @ C247 220U_6.3V_M_R17 2/12 Follow EDS1.11 Change to 100 ohm M36 6mA Near U23 D R304 0_0402_5% D4 CH751H-40PT_SOD323-2 VCC3_3[11] VCCSUSHDA 220U_6.3V_M_R17 +3VALW VCC3_3[10] AK3 AK1 0.1U_0402_16V4Z 2 1 @ C245 1U_0402_6.3V6K 2 @ L11 1 2 10UH_LB2012T100MR_20% 2 >1mA DCPSUS VCCSUS3_3[29] 1 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z Near 2 F24 32mA P18 1 C267 V5REF_SUS >1mA VCCSATAPLL[1] VCCSATAPLL[2] U19 1 Near V15 1 VCCIO[56] V23 + C244 10uH inductor, 120mA 1 RTC +1.05VS U23 1 Near A26 VCCIO[3] +3VS 0.1U_0402_16V4Z VCCSUS3_3[28] 0.1U_0402_16V4Z 2 +1.05VS Near P18 C263 163mA C243 2 VCCME[1] AD39 1 @ C238 C239 22U_0805_6.3V6M 1U_0402_6.3V6K 2 2 C237 2 22U_0805_6.3V6M 1 1998mA AD38 1 C242 +VCCADPLLA Near BB51 L10 1 2 10UH_LB2012T100MR_20% 10uH inductor, 120mA 1 Follow Intel suggestion DCPSUSBYP +3VALW Near V24 2 0.1U_0402_16V4Z 2 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 09/09/21 WW37 remove +VCCADPLLA,+VCCADPLLB external 1U +1.05VS C240 1U_0402_6.3V6K 1 2 2 1 VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] +1.05VS 1 C246 Y20 1 2 2 +PCH_VCCD6W Near AF23 +1.05VS C235 VCCLAN[2] HDA C241 1U_0402_6.3V6K 2 @ Near Y20 1 VCCLAN[1] AF24 SATA R302 0_0402_5% D V24 V26 Y24 Y26 344mA AF23 1 VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] 1 +VCCLAN 2 VCCACLK[2] PCI/GPIO/LPC @ 1 R303 1 0_0603_5% AP53 USB +1.05VS VCCACLK[1] Clock and Miscellaneous DG 1.6 (Page 329) Have Internal VRM REV1.0 52mA AP51 PCI/GPIO/LPC +1.1VS_VCCACLK 2 POWER U4J @ T22 PAD CPU 5 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title PCH (8/9) PWR Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 20 of 48 Rev 1.0 5 4 U4I D C B A AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 3 2 1 U4H VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] REV1.0 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 Del PCH XDP C B IBEXPEAK-M_FCBGA107 A REV1.0 Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M_FCBGA107 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 D 4 3 2 Title PCH (9/9) VSS & PCH XDP Port Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 21 of 48 Rev 1.0 5 4 3 1 LCD POWER CIRCUIT +LCDVDD +3VS +3VALW 1 W=60mils 1 R724 4 1 2N7002DW-T/R7_SOT363-6 <16> DPST_PWM 2 A 1 1 5 P Q17 change to SB934130020 2 100K_0402_5% R96 Y 1 +LCDVDD R727 W=60mils 2 C620 4.7U_0805_10V4Z 1 2 2 @ 1 R728 2 0_0402_5% 10K_0402_5% C621 U8 change to SA00000U500 20091216 0.1U_0402_16V4Z 2 R729 100K_0402_5% 1 D INVTPWM 4 2 Q65B 5 <16> PCH_ENVDD U8 74AHCT1G125GW_SOT353-5 OE# 3 C619 1 Add R96 for SA00000U500 part 20091216 +3VS 4.7U_0805_10V4Z Q17 AO3413_SOT23-3 2 0.047U_0402_16V7K C618 3 3 1 2 1 2 2N7002DW-T/R7_SOT363-6 R726 1K_0402_5% 2 1 G Q65A D 6 2 2 G 1 R725 100K_0402_5% S 300_0603_5% D 2 LED PANEL Conn. +3VS JLVDS1 1 C C626 41 42 43 44 45 46 2 0.1U_0402_16V4Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 G1 G2 G3 G4 G5 G6 +INVPWR_B+ L12 2 1 FBMA-L11-201209-221LMA30T_0805 W=40mils B+ L13 2 1 FBMA-L11-201209-221LMA30T_0805 C622 470P_0402_50V7K 1 1 2 INVTPWM DISPOFF# C623 68P_0402_50V8J 2 1 C624 1 C625 2 220P_0402_50V7K 2 220P_0402_50V7K B +3VS 11/21 intel JIM suggest Pull high at LVDS Conn R735 1 2 2.2K_0402_5% PCH_LCD_CLK R736 1 2 2.2K_0402_5% PCH_LCD_DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +INVPWR_B+ C +LCDVDD INVTPWM DISPOFF# PCH_LCD_CLK PCH_LCD_DATA PCH_TXOUT0PCH_TXOUT0+ W=60mils R731 @ 2 +3VS 0_0402_5% 1 BKOFF# <30> BKOFF# INVT_PWM <30> R730 1 R732 1 2 0_0402_5% 2 10K_0402_5% DISPOFF# PCH_LCD_CLK <16> PCH_LCD_DATA <16> DAC_BRIG <30> PCH_TXOUT0- <16> PCH_TXOUT0+ <16> PCH_TXOUT1PCH_TXOUT1+ PCH_TXOUT1- <16> PCH_TXOUT1+ <16> PCH_TXOUT2PCH_TXOUT2+ PCH_TXOUT2- <16> PCH_TXOUT2+ <16> PCH_TXCLKPCH_TXCLK+ 1 @ R15 2 0_0402_5% 1 @ R16 2 0_0402_5% PCH_TXCLK- <16> PCH_TXCLK+ <16> LOCAL_DIM LOCAL_DIM <30> COLOR_ENG_EN COLOR_ENG_EN <30> B For Camera USB20_N8 USB20_P8 +3VS USB20_N8 <17> USB20_P8 <17> STARC_107K40-000001-G2 CONN@ @ +3VS USB20_P8 D10 6 CH3 5 Vp 4 CH4 CH2 3 Vn 2 CH1 1 USB20_N8 CM1293-04SO_SOT23-6 A A 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title LVDS Connector Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 22 of 48 Rev 1.0 C D CRT Connector D7 D7 / D8 / D9 change to SC6BAV99390 D8 E W=40mils D9 +5VS +CRT_VCC +R_CRT_VCC 1 DAN217_SC59 DAN217_SC59 DAN217_SC59 D6 1 B 1 A F2 2 1 1 RB491D_SC59-3 2 1.1A_6VDC_FUSE 3 2 3 2 3 2 D6 change to SCS00002000 CRT_R_1 2 FBMA-L11-160808-800LMT_0603 1 L25 2 FBMA-L11-160808-800LMT_0603 CRT_R_2 PCH_CRT_G 1 L27 CRT_G_1 2 FBMA-L11-160808-800LMT_0603 1 L26 2 FBMA-L11-160808-800LMT_0603 CRT_G_2 PCH_CRT_B 1 L28 CRT_B_1 2 FBMA-L11-160808-800LMT_0603 1 L29 2 FBMA-L11-160808-800LMT_0603 CRT_B_2 1 <16> PCH_CRT_B 1 L24 R473 R475 2 150_0402_1% 2 2 1 C505 R474 150_0402_1% 1 C506 2 2 10P_0402_50V8J 150_0402_1% 1 JCRT1 C507 1 C508 2 10P_0402_50V8J 1 C509 1 C510 1 2 2 2 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 10P_0402_50V8J 1 C511 10P_0402_50V8J 2 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 1 C512 10P_0402_50V8J 2 2 C513 10P_0402_50V8J 1 Change to 12pf for Discrete 2 +CRT_VCC 5 R476 2 P 2 A 1 10K_0402_5% 1 L33 2 MBC1608121YZF_0603 CRT_HSYNC_2 1 L34 2 MBC1608121YZF_0603 CRT_VSYNC_2 U22 Y C516 10P_0402_50V8J CRT_HSYNC_1 4 3 G G 16 17 C514 C-H_13-12201513CP CONN@ 100P_0402_50V8J DSUB_12 1 1 2 2 1 C517 10P_0402_50V8J C518 2 68P_0402_50V8J 1 G PCH_CRT_HSYNC2 1 2 0.1U_0402_16V4Z OE# C515 1 <16> PCH_CRT_HSYNC 2 1 <16> PCH_CRT_G PCH_CRT_R 1 <16> PCH_CRT_R 1 C501 0.1U_0402_16V4Z +3VS 1 74AHCT1G125GW_SOT353-5 2 DSUB_15 2 C519 68P_0402_50V8J +CRT_VCC 5 P PCH_CRT_VSYNC 2 A U23 Y 4 CRT_VSYNC_1 3 G <16> PCH_CRT_VSYNC 1 2 0.1U_0402_16V4Z OE# C520 1 74AHCT1G125GW_SOT353-5 +CRT_VCC 1 +3VS PCH_CRT_DATA 1 5 pull-up 2k on GPU SIDE <16> PCH_CRT_CLK PCH_CRT_CLK 4 6 2 2 <16> PCH_CRT_DATA R743 2.2K_0402_5% 2 R742 2.2K_0402_5% pull-up 2.2k on PCH side 3 1 3 DSUB_12 Q19A 2N7002DW-T/R7_SOT363-6 DSUB_15 3 Q19B 2N7002DW-T/R7_SOT363-6 4 4 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title CRT Connector Size B Date: Document Number PEW71 M/B LA-6582P Schematic Sheet Thursday, July 08, 2010 E 23 of 48 Rev 1.0 5 4 3 2 1 +3VS +3VS 2 C648 HDMI@ 2 C649 HDMI@ 2 1 C650 HDMI@ 2 1 HDMI@ 1 +5VS 2 W=40mils F1 OE# 2 1.1A_6VDC_FUSE 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI@ C651 0.1U_0402_16V4Z D CG2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 450 420 450 460 340 400 400 420 0 0 0 0 0 2db 2db 0 0 -3db -3db (default) -4db 0 0 0 0 OC_S2 HDMI_CG2 1 1 +3VS S @ 2 SCL_SINK 28 HDMI@ D12 CH751H-40PT_SOD323-2 HDMI_SCLK R749 1 HDMI@ 2 2.2K_0402_5% 1 2 +HDMI_5V_OUT SDA_SINK 29 HDMI_SDATA R747 1 HDMI@ 2 2.2K_0402_5% 1 HPD_SINK 30 DDC_EN 32 EQ_0 EQ_1 34 35 HDMI_R_CK- R746 HDMI@ 100K_0402_5% OE# HDMI_HPD R753 R754 R757 R758 EQ_S1 1 1 1 1 HDMI_R_D2+ HPD# SDA SCL 0 0 1 1 0 1 0 1 @ HDMI@ @ HDMI@ 2 2 2 2 HDMI_CLK- 2.2K_0402_5% 0_0402_5% 2.2K_0402_5% 0_0402_5% R752 1 L14 W CM-2012-900T_0805 @ 4 +3VS HDMI_TX0- 12dB 9dB 6dB 3dB (default) R760 R762 1 L15 W CM-2012-900T_0805 @ 4 CG_2 IN_D4+ IN_D4- 48 47 PCH_TMDS_D2 <16> PCH_TMDS_D2# <16> HDMI_TX1+ HDMI_TX1- 16 17 OUT_D3+ OUT_D3- IN_D3+ IN_D3- 45 44 PCH_TMDS_D1 <16> PCH_TMDS_D1# <16> HDMI_CLK+ HDMI_CLK- 19 20 OUT_D2+ OUT_D2- IN_D2+ IN_D2- 42 41 HDMI_TX0+ HDMI_TX0- 22 23 OUT_D1+ OUT_D1- IN_D1+ IN_D1- 39 38 1 5 12 18 24 27 31 36 37 43 GND GND GND GND GND GND GND GND GND GND R765 HDMI_TX1- L16 W CM-2012-900T_0805 @ 4 HDMI_TX1+ PCH_TMDS_D0 <16> PCH_TMDS_D0# <16> HDMI_TX2- 49 1 R777 PCH_TMDS_CK# 1 R778 @ @ R767 1 PCH_TMDS_CK <16> PCH_TMDS_CK# <16> PCH_TMDS_CK GND 20 21 22 23 D SUYIN_100042MR019S153ZL CONN@ 1 HDMI@ 2 1 0_0402_5% 2 4 3 HDMI_R_CK- 2 3 2 0_0402_5% HDMI_R_CK+ 1 HDMI@ 2 0_0402_5% HDMI_R_D0- 1 HDMI@ Equalization OUT_D4+ OUT_D4- <16> HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ HDMI@ HDMI_CLK+ EQ1 HDMI_R_D0+ HDMI_R_D1- HDMI Conn. Change to DC232000900 20090917 CH751H-40PT_SOD323-2 REXT EQ0 HDMI_R_CK+ HDMI_R_D0- HDMI_R_D1+ HDMI_R_D2- 2 R751 1 HDMI@ 2 2.2K_0402_5%+3VS 13 14 2 1 3 2N7002_SOT23 1 R773 20K_0402_5% @ 2 B C652 HDMI@ 0.1U_0402_16V4Z 1 OE# D17 CG_0 CG_1 HDMI_HPD 2 G S 25 HDMI_TX2+ HDMI_TX2- PCH_DPB_HPD Q21 10 VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V HDMI_SDATA HDMI_SCLK HDMI_TX0+ R769 20K_0402_5% @ 2 G 6 LS_HDMI_DET 7 R761 1 HDMI@ 2 2.2K_0402_5% SDVO_SDATA 8 R763 1 HDMI@ 2 2.2K_0402_5% SDVO_SCLK 9 HDMI@ R766 0_0402_5% LS_HDMI_DET 2 2 R764 1 @ 2 2.2K_0402_5% D 2 11 15 21 26 33 40 46 R759 1 HDMI@ 2 4.32K_0402_1% <16> SDVO_SCLK 1 HDMI@ 2 R771 0_0402_5% +3VS HDMI_CG0 3 HDMI_CG1 4 +3VS +3VS +3VS 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D Q20 2N7002_SOT23 HDMI@ U11 R755 1 HDMI@ 2 4.7K_0402_5% R756 1 @ 2 2.2K_0402_5% <16> SDVO_SDATA C 1 Swing Pre-amp Slew-rate 2.2K_0402_5% 1 2 @ R750 0 0 0 0 1 1 1 1 CG1 2.2K_0402_5% 1 2 @ R748 CG0 JHDMI1 HDMI_HPD +HDMI_5V_OUT 1 2 C647 HDMI@ 1 2 2 0.1U_0402_16V4Z C644 HDMI@ 1 2 C646 HDMI@ 1 NAL00 HDMI connector R745 10K_0402_5% HDMI@ 1 1 0.1U_0402_16V4Z 3 C645 HDMI@ 1 0.1U_0402_16V4Z 1 +HDMI_5V_OUT 0.1U_0402_16V4Z 2 2.2K_0402_5% 2 2.2K_0402_5% R768 R770 1 L17 W CM-2012-900T_0805 @ 4 HDMI_TX2+ R772 1 2 4 1 3 HDMI@ 2 1 HDMI@ 2 1 2 4 1 3 HDMI@ 2 1 HDMI@ 2 1 2 4 1 3 HDMI@ 2 C 2 3 0_0402_5% HDMI_R_D0+ 0_0402_5% HDMI_R_D1- 2 3 0_0402_5% HDMI_R_D1+ 0_0402_5% HDMI_R_D2- 2 3 0_0402_5% HDMI_R_D2+ For HDMI SW Issue B ASM1442T_QFN48_7X7 HDMI@ Change to TI 20100608 P/N: SA00003DS00 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/4/15 Issued Date Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HDMI Level Shife & Conn Size Document Number Custom Rev 1.0 PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 24 of 48 A B H1 H_3P0 H2 H_3P0 H4 H_3P0 H6 H_3P0 C H7 H_3P0 H8 H_3P0 H9 H_3P0 D E F G H SATA HDD1 Conn. H12 H_3P0 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 1 1 CL 4.0 mm @ @ JHDD1 <13> SATA_PTX_DRX_P0 <13> SATA_PTX_DRX_N0 1 @ H23 H_4P2 @ H24 H_4P2 @ 1 H22 H_4P2 1 H21 H_4P2 1 1 <13> SATA_DTX_C_PRX_N0 <13> SATA_DTX_C_PRX_P0 C658 1 C659 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 C661 1 C660 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_PRX_N0 SATA_DTX_PRX_P0 1 H41 H_3P0X3P5N H42 H_3P0N 2 1 1 1 @ C653 0.1U_0402_16V4Z 0.1U_0402_16V4Z C654 1 C655 2 2 1000P_0402_50V7K FD7 10U_0805_10V4Z 1 C656 1 C657 @ Stand-off FD8 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS +5VS 1 @ JMINI1 GND A+ AGND BB+ GND 1 @ +3VS H18 H_3P4 1 2 3 4 5 6 7 FD5 2 2 1U_0603_10V6K V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 GND GND 24 23 FD6 FIDUCIAL_C40M80 FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 1 @ 1 1 1 SANTA_192301-1 CONN@ @ @ 20090915 Update to SANTA FIDUCIAL_C40M80 2 2 SATA ODD FFC Conn. JODD1 <13> SATA_PTX_DRX_P1 <13> SATA_PTX_DRX_N1 <13> SATA_DTX_C_PRX_N1 <13> SATA_DTX_C_PRX_P1 C666 1 C667 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C668 1 C669 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 SATA_DTX_PRX_P1 +5VS 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 GND GND 13 14 ACES_85201-1205N CONN@ 3 3 Change to 12P conn. for FFC 20100413 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Title HDD & ODD & Screw Hole Size B Document Number PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 G Sheet 25 H of 48 Rev 1.0 A B C D E For Wireless LAN +3VS C1148 4.7U_0805_10V4Z +1.5VS 47P_0402_50V8J 1 1 C1149 @ C37 1 2 1 1 2 2 0.1U_0402_16V4Z 20090915 Add for 3G team 2 C1150 +3VS 0.1U_0402_16V4Z 1 C1151 4.7U_0805_10V4Z 2 47P_0402_50V8J 1 1 C1152 @ C38 1 2 2 0.1U_0402_16V4Z 20090915 Add for 3G team C1157 0.1U_0402_16V4Z 2 1 JMINI1 @ 2 0_0402_5% <14> MINI1_CLKREQ# <14> CLK_PCIE_MINI1# <14> CLK_PCIE_MINI1 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 <14> PCIE_DTX_C_PRX_N2 <14> PCIE_DTX_C_PRX_P2 <14> PCIE_PTX_C_DRX_N2 <14> PCIE_PTX_C_DRX_P2 +3VS R952 1 <30> E51TXD_P80DATA <30> E51RXD_P80CLK 0_0402_5% 2 1 3 5 7 9 11 13 15 E51TXD_P80DATA_R E51RXD_P80CLK 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VS +1.5VS Del 3G / GPS Module Connect 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 WL_OFF# PLT_RST_BUF# R949 1 R950 1 @ PCH_SMBCLK PCH_SMBDATA 53 54 55 56 2 0_0603_5% 2 0_0603_5% WL_OFF# <30> PLT_RST_BUF# <17> +3VS +3VALW PCH_SMBCLK <12,14> PCH_SMBDATA <12,14> USB20_N12 <17> USB20_P12 <17> 1 R14 2 0_0402_5% Mini1_LED# <30> (9~16mA) R953 100K_0402_5% 2 2 G1 G2 G3 G3 2 2 4 6 8 10 12 14 16 1 PCH_PCIE_WAKE# R947 1 <15,27> PCH_PCIE_WAKE# ACES_88910-5204 CONN@ 5.2 mm Change to PU +3VS +3VS 20091230 高 Mini Card Power Rating Power 3 Primary Power (mA) Auxiliary Power (mA) Peak Normal +3VS 1000 750 Normal +3V 330 250 250 (wake enable) +1.5VS 500 375 5 (Not wake enable) FAN1 Conn 3 +5VS @ C1160 1 10U_0805_10V4Z 2 U60 +VCC_FAN1 <30> EN_DFAN1 1 2 3 4 EN VIN VOUT VSET GND GND GND GND 8 7 6 5 APL5607KI-TRG_SO8 C1166 10U_0805_10V4Z 1 2 +3VS 1 C1167 1000P_0402_50V7K 1 2 R956 10K_0402_5% 2 40mil +VCC_FAN1 <30> FAN_SPEED1 1 4 JFAN1 1 2 3 1 2 3 G1 G2 4 5 4 CONN@ ACES_85204-03001 C1168 1000P_0402_50V7K 2 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title MINI CARD (WLAN & 3G)/FAN Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 26 of 48 Rev 1.0 5 4 3 2 1 +3V_LAN +3VALW R901 1 60mil 2 0_1206_5% 1 U58 C674 1 C675 1000P_0402_50V7K2 1 2 2 0.1U_0402_16V4Z C676 2 2 0.1U_0402_16V4Z +LAN_AVDDL BIASVDDH 6 15 41 VDDC VDDC VDDC XTALVDDH 14 AVDDH 30 AVDDH 27 33 39 1 AVDDL AVDDL AVDDL 2 1000P_0402_50V7K +LAN_GPHYPLLVDDL 1000P_0402_50V7K 24 +LAN_XTALVDDH +LAN_AVDDH TRD3_N 37 LAN_MIDI3- TRD3_P 38 LAN_MIDI3+ TRD2_N 35 LAN_MIDI2- TRD2_P 34 LAN_MIDI2+ TRD1_N 31 LAN_MIDI1- TRD1_P 32 LAN_MIDI1+ TRD0_N 29 LAN_MIDI0- TRD0_P 28 LAN_MIDI0+ LAN_MIDI3- <28> LAN_MIDI3+ <28> LAN_MIDI2- <28> +LAN_PCIEPLLVDD 18 PCIE_PLLVDDL 21 PCIE_PLLVDDL 0.1U_0402_16V7K <14> PCIE_PTX_C_DRX_P1 <14> PCIE_PTX_C_DRX_N1 <15,26> PCH_PCIE_WAKE# <30> EC_PME# +3V_LAN R908 1 R909 1 R910 1 <5,17,30> PLT_RST# R911 1 @ 17 16 22 23 LAN_PME# 4 LAN_RESET# 2 20 2 0_0402_5% 19 2 0_0402_5% 2 4.7K_0402_5% 0 AT24C02 1 1 LAN_MIDI2+ <28> C1118 1 LAN_MIDI1- <28> LAN_MIDI0- <28> LAN_MIDI0+ <28> PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# REST# PCIE_REFCLK_P PCIE_REFCLK_N 48 47 SPD1000LED# TRAFFICLED# 2 1 R904 0_0402_5% LAN_LINK# <28> 2 1 R907 0_0402_5% U59 @ SPROM_CLK SPROM_DOUT +LAN_XTALVDDH 1 C1121 +3VS R912 1 2 1K_0402_5% 40 R913 1 2 10K_0402_5% 1 EECLK SPROM_DOUT 44 SPROM_CLK SR_LX 13 LAN_XTALI 12 XTALO SR_VFB +1.2V_LAN_OUT 1 2 4.7UH_PG031B-4R7MS_1.1A_20% C1125 XTALI 0.1U_0402_16V4Z 1 1 2 2 0.1U_0402_16V4Z 2 C1126 10U_0805_10V4Z 2 LAN_RDAC 26 RDAC SR_VDDP 1.24K_0402_1% SR_VDD <14> LAN_CLKREQ# 3 10 C1129 1 0.1U_0402_16V4Z 2 L103 1 2 BLM18AG601SN1D_2P C1128 +1.2V_LAN 4.7U_0603_6.3V6K L104 +LAN_GPHYPLLVDDL 1 2 BLM18AG601SN1D_2P 1 1 C1131 C1132 0.1U_0402_16V4Z 49 BCM57780A0KMLG_QFN48_7X7 2 1 20mil 7 PAD NC 0.1U_0402_16V4Z C1130 2 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z CLKREQ# 2 +LAN_PCIEPLLVDD 1 C1127 +3V_LAN 1 9 L101 1 2 BLM18AG601SN1D_2P 20mil R914 1 0.1U_0402_16V4Z B +1.2V_LAN 8 +3V_LAN L100 1 2 BLM18AG601SN1D_2P +LAN_AVDDH 1 1 C1123 C1124 L102 LAN_XTALO_R 2 20mil LOW_PWR 11 L99 1 2 BLM18AG601SN1D_2P 0.1U_0402_16V4Z +LAN_BIASVDDH 1 C1122 VMAIN_PRSINT B C 2 20mil 43 1 2 3 4 R906 1K_0402_1% @ 20mil 5 <14> CLK_PCIE_LAN <14> CLK_PCIE_LAN# EEDATA A0 A1 NC GND LAN_ACTIVITY# <28> 2 0_0402_5% MODE VCC WP SCL SDA AT24C02_SO8 R905 1K_0402_1% 46 45 R903 1K_0402_1% 8 7 6 5 2 LINKLED# SPD100LED# 2 0.1U_0402_16V4Z @ R902 1K_0402_1% @ LAN_MIDI1+ <28> 1 PCIE_DTX_PRX_P1 PCIE_DTX_PRX_N1 SPROM_DOUT (EEDATA) 1 +3V_LAN C 0.1U_0402_16V7K 1 2 C1119 1 2 C1120 SPROM_CLK (EECLK) On chip 36 GPHY_PLLVDDL For EMI 20091211 <14> PCIE_DTX_C_PRX_P1 <14> PCIE_DTX_C_PRX_N1 D +LAN_BIASVDDH 2 4.7U_0603_6.3V6K 2 VDDC 25 1 1 42 2 C1114 C1113 2 0.1U_0402_16V4Z 1 1 1 C1115 C1116 C1117 +1.2V_LAN 1 1 +3V_LAN C1112 4.7U_0603_6.3V6K 2 2 0.1U_0402_16V4Z 1 D 2 2 20mil +LAN_AVDDL 1 C1133 LAN_XTALI 0.1U_0402_16V4Z 1 2 2 +1.2V_LAN 4.7U_0603_6.3V6K L105 1 2 BLM18AG601SN1D_2P C1134 +1.2V_LAN 4.7U_0603_6.3V6K LAN_XTALO_R A 1 A 2 R915 200_0402_1% Y6 1 1 2 2 LAN_XTALO 25MHZ_20PF_7A25000012 C1135 33P_0402_50V8J 5 2 2008/08/10 Issued Date C1136 33P_0402_50V8J Compal Electronics, Inc. Compal Secret Data Security Classification 1 2009/08/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title Broadcom BCM57780 Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 27 of 48 Rev 1.0 5 4 3 2 1 LAN Connector D D Change to SP050006B00 20091117 T1 MCT1 MX1+ MX1- 24 23 22 RJ45_MIDI0+ RJ45_MIDI0- TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_MIDI1+ RJ45_MIDI1- 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_MIDI2+ RJ45_MIDI2- <27> LAN_MIDI3+ <27> LAN_MIDI3- LAN_MIDI3+ LAN_MIDI3- 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 RJ45_MIDI3+ RJ45_MIDI3- 2 C1140 1 C1141 1 R917 75_0402_1% C1142 0.1U_0402_16V4Z 2 2 R919 75_0402_1% RJ45_GND Place close to TCT pin C1138 68P_0402_50V8J @ 2 1 LAN_LINK# R920 75_0402_1% 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 R918 75_0402_1% 2 C1139 1 2 1 1 <27> LAN_LINK# 350UH_IH-037-2 C 220P_0402_50V7K C1137 1 <27> LAN_MIDI2+ <27> LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- 1 1K_0402_5% 2 LAN_MIDI1+ LAN_MIDI1- 2 R916 +3V_LAN 1 <27> LAN_MIDI1+ <27> LAN_MIDI1- 4 5 6 TCT1 TD1+ TD1- 1 1 2 3 1 LAN_MIDI0+ LAN_MIDI0- <27> LAN_MIDI0+ <27> LAN_MIDI0- +3V_LAN 2 R921 40mil 1 1K_0402_5% 1 220P_0402_50V7K C1143 Green LED+ 10 Green LED- RJ45_MIDI0+ 1 PR1+ RJ45_MIDI0- 2 PR1- RJ45_MIDI1+ 3 PR2+ RJ45_MIDI2+ 4 PR3+ RJ45_MIDI2- 5 PR3- RJ45_MIDI1- 6 PR2- RJ45_MIDI3+ 7 PR4+ RJ45_MIDI3- 8 PR4- LAN_ACTIVITY# <27> LAN_ACTIVITY# JRJ45 9 2 @ C 11 Yellow LED+ 12 Yellow LED- 68P_0402_50V8J 2 14 13 SHLD1 SHLD2 SANTA_130451-K CONN@ 1 C1144 RJ45_GND 1 LANGND 1 2 C1145 1000P_1206_2KV7K 1 C1146 2 2 40mil C1147 4.7U_0603_6.3V6K 0.1U_0402_16V4Z B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2009/08/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title LAN Magnetic & RJ45 Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 28 of 48 Rev 1.0 A B C D E Card Reader RTS5138 / RTS5137 (only SD+MMC function) +3VS_CR 2 0_0603_5% 1 C740 1 1 C350 4.7U_0805_10V4Z 2 2 30mil C355 1 1 0.1U_0402_16V4Z 2 1 2 R824 10K_0402_5% TPS2061DRG4_SO8 10mil 5IN1_LED# U17 RREF 1 +3VS_CR +CARDPWR VREG 10mil C353 1U_0402_6.3V6K XDDRY_SDWP_MSCLK REFE 17 GPIO0 2 3 DM DP 4 5 6 3V3_IN CARD_3V3 V18 7 CLK_IN 24 XD_D7 23 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 22 21 20 19 18 16 15 14 13 XD_CD# 8 9 10 11 12 SP1 SP2 SP3 SP4 SP5 25 XDCE#_SDD1 XDCLE_SDD0 1 R823 100K_0402_5% 8 7 6 5 OUT OUT OUT FLG @ 1 R744 CLK_SD_48M 4.7U_0805_10V4Z 2 5IN1_LED# <32> 2 1 10_0402_5% @ C716 <35> SYSON# 2 0.1U_0402_16V4Z SYSON# +USB_VCCA XDD5_SDD2_MS_D5 XDD4_SDD3_MSD1 W=100mils Left side USB Port x 1 +USB_VCCA XDD2_SDCMD XDD0_SDCLK_MSD2 XDWE#_SDCD# 220U_6.3V_M_R17 1 + C64 R827 1 Card Reader Connector C743 2 470P_0402_50V7K RTS5138-GR_QFN24_4X4 Change to RTS5137 (SA000043500) 2 0_0402_5% (Port 1) @ L7 USB20_N1 <17> USB20_N1 1 USB20_P1 <17> USB20_P1 4 1 4 JUSB1 2 2 3 3 1 2 3 4 5 6 7 8 USB20_N1_1 USB20_P1_1 WCM2012F2S-900T04_0805 1 2 R828 0_0402_5% +CARDPWR +CARDPWR 1 2 3 4 5 6 1 1 R294 100K_0402_5% 2 C354 0.1U_0402_16V4Z C381 0.1U_0402_16V4Z 1 1 2 2 XDD0_SDCLK_MSD2 C379 0.1U_0402_16V4Z XDCLE_SDD0 XDCE#_SDD1 XDD5_SDD2_MS_D5 XDDRY_SDWP_MSCLK XDWE#_SDCD# Close to connector D3 CMD VSS1 VDD CLK VSS2 7 8 9 10 11 6 5 +USB_VCCA D0 D1 D2 WP CD 12 13 2 SUYIN_020133GB004M51PZR CONN@ D13 USB20_P1_1 4 CH3 CH2 Vp CH4 USB20_N1_1 3 Vn 2 CH1 1 CM1293-04SO_SOT23-6 GND1 GND2 TAITW_PSDBTC09GLBS1N14N0 CONN@ +3VALW +5VALW U15 1 2 3 4 3 C745 1 GND IN IN EN# +USB_VCCB 80mil OUT OUT OUT FLG 8 7 6 5 1 XDD4_SDD3_MSD1 XDD2_SDCMD 2 @ L7 / L22 change to SM070001600 20091230 JCR1 30mil VBUS DD+ GND GND GND GND GND R829 100K_0402_5% 1 2 R830 10K_0402_5% TPS2061DRG4_SO8 4.7U_0805_10V4Z 2 3 2 2 C741 1 Change to SA00002XX00 20090922 2 10P_0402_50V8J CLK_SD_48M <12> USB_OC#2 <17> 1 1 1 100P_0402_50V8J 2 6.2K_0603_1% USB20_N9 <17> USB20_N9 USB20_P9 <17> USB20_P9 EPAD 2 C356 R285 1 GND IN IN EN# 2 R292 80mil U13 1 2 3 4 30mil 2 +3VS +USB_VCCA 1 +3VALW +5VALW Change to SA00002XX00 20090922 USB_OC#0 <17> 1 2 C746 0.1U_0402_16V4Z SYSON# USB/B Conn. Bluetooth Conn. +3VALW (Port 0,2) +3VS JUSB2 1 2 1 Q23 AO3413_SOT23-3 <17> USB20_P11 <17> USB20_N11 W=40mils +BT_VCC C750 1 C751 1 1 0.1U_0402_16V4Z 2 4 JBT1 2 1 2 10K_0402_5% C749 +BT_VCC C748 1U_0402_6.3V6K 1 G 1 R831 D <30> BT_ON# 3 0.1U_0402_16V4Z 2 S C747 Q23 change to SB934130020 8 GND 7 6 5 4 3 2 1 GND 10 13 14 USB20_N0 USB20_P0 USB20_N0 <17> USB20_P0 <17> USB20_N2 USB20_P2 USB20_N2 <17> USB20_P2 <17> ACES_85201-1205N CONN@ 9 ACES_87213-0800G CONN@ R832 300_0603_5% GND GND 1 2 3 4 5 6 7 8 9 10 11 12 4 1 2 4.7U_0805_10V4Z 2 2 0.1U_0402_16V4Z 8 7 6 5 4 3 2 1 +USB_VCCB 1 2 3 4 5 6 7 8 9 10 11 12 Q24 2N7002_SOT23 3 A 2009/5/12 Issued Date S Compal Electronics, Inc. Compal Secret Data Security Classification D 2 G 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C D Title USB & Card reader& BT Connector Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 29 of 48 Rev 1.0 5 4 3 2 1 For EC Tools +3VALW 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 2 C752 C757 C753 C754 C755 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z +3VALW _EC 2 1 1 1000P_0402_50V7K C756 KSI[0..7] +3VALW <31> @JP3 @ JP3 KSO[0..17] <31> 1 1 2 3 4 C758 2 0.1U_0402_16V4Z 1 2 3 4 E51RXD_P80CLK E51TXD_P80DATA ACES_85205-0400 D +3VALW C762 1 47K_0402_5% 2 1 0.1U_0402_16V4Z <5,17,27> PLT_RST# <18> EC_SCI# <15> PM_CLKRUN# +3VALW KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 2 EC_SMB_CK1 2.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5% 1 R839 1 R840 1 R842 2 LID_SW # 100K_0402_5% 1 R843 1 R844 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 10/1 ENE Recommand 1 R846 2 EC_PME# 10K_0402_5% @ +3VS EC suggested 2.2K for SMBus 2 EC_SMB_CK2 2.2K_0402_5% 2 EC_SMB_DA2 2.2K_0402_5% 1 R850 1 R851 1 R852 1 R53 1 R54 1 R51 2 GFX_CORE_PW RGD 10K_0402_5% @ @ 20090915 Add 2 LOCAL_DIM 100K_0402_5% 2 COLOR_ENG_EN 100K_0402_5% E51TXD_P80DATA 2 100K_0402_5% For LVDS Function 20091209 Add EC_CRY1 4 OSC OSC NC 2 1 @ C765 18P_0402_50V8J 2 NC 1 1 2 @ X2 32.768KHZ_12.5PF_Q13MC14610002 5 EC_CRY1 EC_CRY2 122 123 1 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 97 98 99 109 3S/4S# 65W /90W # SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 GPIO SM Bus GPI 2 DAC_BRIG <22> EN_DFAN1 <26> IREF <39> CALIBRATE# <39> EN_DFAN1 IREF CALIBRATE# C761 @ 2 0.1U_0402_16V4Z R838 100K_0402_5% Ra EC_MUTE# <34> GFX_CORE_PW RGD <44> TP_CLK TP_DATA AD_BID0 C R841 8.2K_0402_5% Rb TP_CLK <31> TP_DATA <31> 1 C763 2 0.1U_0402_16V4Z 3S/4S# <39> 65W /90W # <39> LID_SW # +5VS LID_SW # <32> TP_CLK 2 4.7K_0402_5% 2 4.7K_0402_5% TP_DATA EC_SI_SPI_SO <31> EC_SO_SPI_SI <31> EC_SPICLK <31> EC_SPICS#/FSEL# <31> PCH_TEMP_ALERT# FSTCHG 1 R845 1 R847 +3VALW PCH_TEMP_ALERT# <18> FSTCHG <39> BATT_Blue_LED# <32> BATT_Amber_LED# <32> PW R_LED <32> SYSON <35,42> VR_ON <45> ACIN <35,39> PW R_LED SYSON VR_ON ACIN EC_RSMRST# EC_LID_OUT# EC_ON EC_SW I# EC_PW ROK BKOFF# W L_OFF# KB926QFD3_LQFP128_14X14 2 2009/4/15 3 2 R848 1 100K_0402_5% 65W /90W # 2 R849 1 100K_0402_5% BATT_OVP ACIN 2 C767 2 C768 2 C769 1 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J B PM_SLP_S4# <15> ENBKL <16> EAPD <33> SUS_PW R_ACK <15> SUSP# <35,41,43> PBTN_OUT# <15> EC_PME# <27> ENBKL EAPD SUS_PW R_ACK SUSP# PBTN_OUT# EC_PME# 1 3S/4S# BATT_TEMP EC_RSMRST# <15> EC_LID_OUT# <14> EC_ON <32,38> EC_SW I# <15> EC_PW ROK <15> BKOFF# <22> W L_OFF# <26> C766 4.7U_0805_10V4Z 20mil L9 ECAGND 2 1 FBMA-L11-160808-800LMT_0603 A Deciphered Date Compal Electronics, Inc. 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 +3VALW Compal Secret Data Security Classification Issued Date C765 100K_0402_5% EC_MUTE# GFX_CORE_PW RGD XCLK1 XCLK0 1.Use crystal X2,remove R13 and C765 change to 100K for SUSCLK PD. 2.Use PCH_SUSCLK,remove X1. 20091103 For EC SUSCLK PD 100K 83 84 85 86 87 88 R835 200K_0402_5% Rd 10/1 EC Recommand PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A EC_CRY2 3 @ C764 18P_0402_50V8J 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 EC_CRY2 2 0_0402_5% 1 R13 <15> PCH_SUSCLK <15> PM_SLP_S3# <15> PM_SLP_S5# <18> EC_SMI# <15> EC_ACIN <26> Mini1_LED# <22> LOCAL_DIM <22> COLOR_ENG_EN <22> INVT_PW M <26> FAN_SPEED1 <29> BT_ON# <26> E51TXD_P80DATA <26> E51RXD_P80CLK <32> ON/OFF <32> PW R_SUSP_LED <32> W LAN_LED# PM_SLP_S3# PM_SLP_S5# EC_SMI# EC_ACIN Mini1_LED# LOCAL_DIM COLOR_ENG_EN INVT_PW M FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PW R_SUSP_LED W LAN_LED# PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SPI Flash ROM 2 PCH_TEMP_ALERT# 2.2K_0402_5% P80DATA PD 100K for EC common design 20091105 A EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 AD_ProjectID BATT_TEMP <37> BATT_OVP ADP_I <39> SPI Device Interface GND GND GND GND GND 1 R605 B <37> <37> <14> <14> BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 PS2 Interface 11 24 35 94 113 C 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 BATT_TEMP BATT_OVP ADP_I AD_BID0 AD_ProjectID 63 64 65 66 75 76 DA Output KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 BEEP# <33> ME_OVERRIDE <13> ACOFF <39,40> ECAGND 2 1 C759 0.01U_0402_16V7K 1 R837 2 +3VALW AD BEEP# ME_OVERRIDE ACOFF 1 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D PWM Output 21 23 26 27 2 EC_RST# EC_SCI# 12 13 37 20 38 <17> CLK_PCI_LPC INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 1 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC 2 1 2 3 4 5 7 8 10 R834 100K_0402_5% Rc AGND R836 10_0402_5% 2 1 EC_GA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 69 C760 10P_0402_50V8J 2 1 <18> EC_GA20 <18> EC_KBRST# <13> SERIRQ <13> LPC_FRAME# <13> LPC_AD3 <13> LPC_AD2 <13> LPC_AD1 <13> LPC_AD0 AVCC VCC VCC VCC VCC VCC VCC 2 67 9 22 33 96 111 125 D U16 KSI[0..7] KSO[0..17] 1000P_0402_50V7K ECAGND 1 R833 0_0603_5% L8 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA 2 Title EC ENE KB926 Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 1 30 of 48 Rev 1.0 To TP/B Conn. <30> (Right) G2 G1 28 27 C771 100P_0402_50V8J 1 1 2 2 C772 100P_0402_50V8J 3 RIGHT_BTN# 2 D14 PJDLC05C_SOT23-3 D16 PJDLC05C_SOT23-3 7 8 ACES_85201-0605N CONN@ +5VS LEFT_BTN# 3 SW1 SMT1-05-A_4P 1 RIGHT_BTN# 3 SW2 SMT1-05-A_4P 1 4 2 4 2 C773 0.1U_0402_16V4Z ACES_88747-2601 CONN@ KSO15 @ C775 1 2 100P_0402_50V8J KSO14 @ C777 1 2 100P_0402_50V8J KSO13 @ C778 1 2 100P_0402_50V8J KSO12 @ C780 1 2 100P_0402_50V8J KSI0 @ C783 1 2 100P_0402_50V8J 2 100P_0402_50V8J KSO16 @ C774 1 2 100P_0402_50V8J KSO17 @ C776 1 2 100P_0402_50V8J KSO7 @ C779 1 2 100P_0402_50V8J KSO6 @ C781 1 2 100P_0402_50V8J KSO5 @ C782 1 2 100P_0402_50V8J KSO4 @ C784 1 2 100P_0402_50V8J KSO3 @ C787 1 KSI4 +3VALW 1 R853 2 0_0603_5% C770 1 @ C785 1 KSO10 @ C786 1 2 100P_0402_50V8J KSI1 @ C788 1 2 100P_0402_50V8J KSI2 @ C791 1 2 100P_0402_50V8J KSO9 @ C793 1 2 100P_0402_50V8J KSI3 @ C794 1 2 100P_0402_50V8J @ C796 1 2 100P_0402_50V8J 2 0.1U_0402_16V4Z +SPI_VCC U30 KSO11 KSO8 LEFT_BTN# TP_DATA 1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 2 3 4 5 6 GND GND 5 6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 5 6 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 TP_CLK TP_DATA LEFT_BTN# RIGHT_BTN# <30> TP_CLK <30> TP_DATA JKB1 (Left) TP_CLK JTP1 +5VS <30> 3 KSO[0..17] 2 KSI[0..7] KSO[0..17] 1 KSI[0..7] 2 100P_0402_50V8J @ C789 1 2 100P_0402_50V8J KSO2 @ C790 1 2 100P_0402_50V8J KSO1 @ C792 1 2 100P_0402_50V8J KSO0 @ C795 1 2 100P_0402_50V8J KSI5 @ C797 1 2 100P_0402_50V8J KSI6 @ C798 1 2 100P_0402_50V8J KSI7 @ C799 1 2 100P_0402_50V8J <30> EC_SPICS#/FSEL# +3VALW R854 1 R856 1 EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD# 1 3 7 4 @ CE# WP# HOLD# VSS VDD SCK SI SO 8 6 5 2 EC_SPICLK_R R855 1 R857 1 R858 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% EC_SPICLK <30> EC_SO_SPI_SI <30> EC_SI_SPI_SO <30> MX25L8005M2C-15G_SOP8 U31 EC_SPICS#/FSEL# SPI_WP# SPI_HOLD# 1 3 7 4 CS# WP# HOLD# GND VCC SCLK SI SO 8 6 5 2 +SPI_VCC EC_SPICLK_R EC_SO_SPI_SI EC_SI_SPI_SO @ EC_SPICLK_R 1 R339 @ 2 10_0402_5% 1 C556 2 10P_0402_50V8J For EMI Close to U31 MX25L512AMC-12G_SO8 use 128KB EC ROM SA00002C100 ENE suggestion SPI Frequency over 66MHz SST: 50MHz MXIC: 70MHz ST: 40MHz To BTN/B Conn. KSO0 KSO3 KSI1 WL_BTN# Program_BTN# KSI2 T/P lock_BTN# KSI3 Back up_BTN# KSI4 BT_BTN# KSI5 Power save_BTN# Volum up_BTN# Volum down_BTN# Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title BIOS, I/O Port & K/B Connector Size C Date: Document Number Rev 1.0 PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 31 of 48 A B C D E Power Button 2 +3VALW 1 1 R859 LED/B LEFT 1 100K_0402_5% D15 change to SC600000B00 1 R860 D S 2N7002_SOT23 +3VS @ R864 10K_0402_5% +3VS PWR_LED# ON/OFFBTN# U19 2 B <29> 5IN1_LED# SATA_LED# <13> SATA_LED# Pin define modify 20100413 ACES_85201-08051 CONN@ 3 EC_ON 2 <30,38> EC_ON LID_SW# WLAN_LED# MEDIA_LED# 1 5 51ON# <36> +3VALW LID_SW# <30> WLAN_LED# <30> P 51ON# 3 DAN202UT106_SC70-3 1 2 3 4 5 6 7 8 9 10 Y A MC74VHC1G08DFT2G_SC70-5 4 MEDIA_LED# G 1 1 2 3 4 5 6 7 8 GND GND 3 ON/OFF <30> 2 ON/OFFBTN# +3VS JLED1 2 1 D15 Q25 2 G Change to AND gate 20100416 1 10K_0402_5% LED1 +3VS 1 R619 2 2 2.2K_0402_5% 2 B 1 PWR_LED# 2 HT-191NB5_BLUE LED2 +3VALW 1 R620 2 2 3.9K_0402_5% A 1 PWR_SUSP_LED# HT-191UD5_AMBER 6 PWR_LED# Q36A 2N7002DW-T/R7_SOT363-6 LED3 2 2 2.2K_0402_5% B 1 BATT_Blue_LED# 2 <30> PWR_LED BATT_Blue_LED# <30> 1 1 R621 1 +3VALW R865 HT-191NB5_BLUE 10K_0402_5% 2 2 3.9K_0402_5% A 1 BATT_Amber_LED# PWR_SUSP_LED# BATT_Amber_LED# <30> 3 1 R622 2 LED4 Q36B 2N7002DW-T/R7_SOT363-6 HT-191UD5_AMBER 1 4 5 <30> PWR_SUSP_LED R866 3 3 2 10K_0402_5% 4 4 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 32 of 48 Rev 1.0 5 4 3 2 +3VS C301 3 2 D 2 0.1U_0402_16V4Z 1 R641 10K_0402_5% 40mil 5 OUT R638 20K_0402_5% 4.75V +VDDA GND SHDN 4 BYP G9191-475T1U_SOT23-5 @ 2 2 IN 1 2 C291 0.01U_0402_25V7K @ 1 1 C300 1 (output = 300 mA) C679 1 <30> BEEP# 2 1U_0402_6.3V6K C680 1 <13> PCH_SPKR 2 1U_0402_6.3V6K 1 R643 2 2 B R646 D MONO_IN 2 1 R644 Q42 2 2.4K_0402_1% E 560_0402_5% 1 C678 1 1U_0402_6.3V6K C 3 1 L20 1 @ 2 FBMA-L11-201209-221LMA30T_0805 U14 60mil 0.1U_0402_16V4Z 2 L19 1 2 FBMA-L11-201209-221LMA30T_0805 2SC2411KT146_SOT23-3 2 560_0402_5% 1 +5VAMP +5VS +5VAMP 2 0_0805_5% 1 1 R334 1 2 D22 CH751H-40PT_SOD323-2 Q42 change to SB324110080 HD Audio Codec +AVDD_HDA Place near Codec 1 C279 C259/C279/C692/C693 Change to SE107475K80 20091216 Internal MIC REF 272@ MIC2_VREFO MIC1_L <34> MIC1_L 1 C692 MIC1_R <34> MIC1_R 1 C693 MIC1_C_L 2 4.7U_0603_6.3V6K MIC1_C_R 2 4.7U_0603_6.3V6K MONO_IN LINE2_L LOUT1_L 35 AMP_LEFT LINE2_R LOUT_R 36 AMP_RIGHT 16 MIC2_L LOUT2_L 39 17 MIC2_R LOUT2_R 41 23 LINE1_L SPDIFO2 45 LINE1_R DMIC_CLK1/2 LINE1_VREFO NC 20 LINE2_VREFO DMIC_CLK3/4 19 MIC2_VREFO 21 MIC1_L 22 12 BITCLK MIC1_R PCBEEP_IN SDATA_IN MONO_OUT B 11 <13> HDA_RST_AUDIO# 10 <13> HDA_SYNC_AUDIO 5 <13> HDA_SDOUT_AUDIO <34> MIC_PLUG# <34> HP_PLUG# R672 2 R668 2 <30> EAPD 2 3 13 34 SENSE_A SENSE_B 1 20K_0402_1% 1 5.11K_0402_1% 1 R671 2 0_0402_5% 47 48 4 7 CBP RESET# CPVEE SYNC MIC1_VREFO SDATA_OUT EAPD SPDIFO1 DVSS1 DVSS2 AVSS1 AVSS2 GND 2 C231 22P_0402_50V8J 2 1 0_0402_5% 8 For EMI HDA_BITCLK_AUDIO <13> HDA_SDIN0_AUDIO 1 R301 GND 2 33_0402_5% GNDA HDA_SDIN0 <13> Del 0_0805_5% 20100506 B 29 2.2U_0402_6.3VM 31 28 C277 1 10mil MIC1_VREFO HP_RIGHT 27 CODEC_VREF 40 R651 1 33 2 HP_LEFT External MIC REF 272@ HP_RIGHT <34> 1 C274 2 10mil C700 1 C701 1 MIC2_VREFO 2.2U_0402_6.3VM 2 0.1U_0402_16V4Z 2 10U_0805_10V4Z Int. MIC 2 20K_0402_1% Place next pin27 HP_LEFT <34> 26 42 1 2 G1 G2 AGND For EMI 15mil JMIC2 ALC272X-GR_LQFP48_7X7 <BOM Structure> DGND GNDA 37 30 HPOUT_L 1 R336 6 CBN VREF 272@amp AMP_RIGHT <34> 43 44 HPOUT_R JDREF AMP_LEFT <34> 46 32 GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B C 0.1U_0402_16V4Z 15 18 20091116 2 14 24 0603 type 2 +3VS L21 Change to SM010012010 C280 10U_0805_10V4Z 1 2 1 C259 MIC2_C_L 2 4.7U_0603_6.3V6K MIC2_C_R 2 4.7U_0603_6.3V6K C233 R673 2.2K_0402_5% 15mil INT_MIC_L 1 L53 INT_MIC_R 2 FBMA-L11-160808-700LMT_2P 2 INT_MIC 1 2 L21 1 2 MBC1608121YZF_0603 1 1 3 4 2 ACES_88266-02001 CONN@ C702 220P_0402_50V7K 2 External MIC 1K_0402_1% INT_MIC_RR335 2 1 AVDD1 Place near Codec C234 +3VS_DVDD 1 9 U36 1 2 0.1U_0402_16V4Z DVDD 2 DVDD_IO 2 1 38 C 0.1U_0402_16V4Z C278 25 C276 10U_0805_10V4Z 1 AVDD2 +VDDA 10mil 3 40mil 0.1U_0402_16V4Z 1 1 C258 L18 1 2 FBMA-L11-160808-800LMT_0603 @ D23 PJDLC05C_SOT23-3 1 A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A Change to SCA00001100 20090921 2 Title HD Audio Codec ALC271X/272X Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 33 of 48 Rev 1.0 A B Ri 90k 70k 45k 25k D 0.1U_0402_16V4Z 1 10 dB C706 2 +5VAMP 2 16 15 6 R678 100K_0402_5% VDD PVDD1 PVDD2 C707 C709 1 <33> AMP_LEFT 1 C710 2 1 0.47U_0603_10V7K R683 2 0.47U_0603_10V7K 9 AMP_C_LEFT 2 0_0603_5% 5 EC_MUTE# 19 GAIN1 ROUT+ 18 SPKR+ ROUT- 14 SPKR- LOUT+ 4 SPKL+ LOUT- 8 SPKL- RIN- 2 GAIN0 3 @ R681 100K_0402_5% R682 100K_0402_5% LIN+ LIN- NC 12 BYPASS 10 SHUTDOWN Keep 10 mil width 2 GND5 GND1 GND2 GND3 GND4 <30> EC_MUTE# 2 GAIN1 1 AMP_C_RIGHT 17 2 0_0603_5% GAIN0 2 2 1 0.47U_0603_10V7K R680 RIN+ 1 1 7 1 2 <33> AMP_RIGHT 2 0.47U_0603_10V7K @ R679 100K_0402_5% 2 1 1 1 C705 10U_0805_10V4Z U37 C708 1 E +5VAMP 1 GAIN0 GAIN1 AV(inv) 0 0 6dB 0 1 10dB 1 0 15.6dB 1 1 21.6dB C C711 0.47U_0603_10V7K 21 20 13 11 1 1 2 2 TPA6017A2PWPR_TSSOP20 2 C712 330P_0402_50V7K <33> HP_LEFT R686 1 2 56.2_0603_1% HPOUT_L_1 <33> HP_RIGHT R685 1 2 56.2_0603_1% HPOUT_R_1 1 L55 1 L56 1 2 (Use NAL00 PCB Footprint) C713 330P_0402_50V7K 1 Headphone Out JHP1 1 2 2 HPOUT_L_2 FBMA-L11-160808-700LMT_2P 2 HPOUT_R_2 FBMA-L11-160808-700LMT_2P 3 4 HP_PLUG# <33> HP_PLUG# Int. Speaker Conn. 3 3 MIC1_VREFO Left Side 2 3 3 4 1 <33> MIC1_R R695 1 MIC1_L_1 2 1K_0603_1% MIC1_R_1 2 1K_0603_1% 1 2 2 L57 1 2 FBMA-L11-160808-700LMT_2P L58 1 2 FBMA-L11-160808-700LMT_2P 1 C714 220P_0402_50V7K G1 G2 JMIC1 MIC1_L_R MIC1_R_R 3 2 4 1 2 C715 220P_0402_50V7K MIC_PLUG# <33> MIC_PLUG# @ D30 PJDLC05C_SOT23-3 5 6 4 SINGA_2SJ-A960-C01 CONN@ 1 1 ACES_88266-02001 CONN@ @ D25 PJDLC05C_SOT23-3 4 2 3 1 R694 1 1 2 3 <33> MIC1_L MIC JACK 4.7K_0402_5% 2 1 2 @ D24 PJDLC05C_SOT23-3 R693 2 1 JSPK2 SPK_R+ SPK_R- 2 0_0603_5% 2 0_0603_5% Headphone Out D28 CH751H-40PT_SOD323-2 R692 4.7K_0402_5% Right Side @ @ 2 2 D27 CH751H-40PT_SOD323-2 G1 G2 ACES_88266-02001 CONN@ @ D26 PJDLC05C_SOT23-3 SPKR+ R690 1 SPKR- R691 1 SINGA_2SJ-0960-C01 CONN@ HP_PLUG# 1 2 1 3 4 2 3 20mil 1 2 1 SPK_L+ SPK_L- 2 0_0603_5% 2 0_0603_5% 1 R688 1 R689 1 6 MIC_PLUG# JSPK1 SPKL+ SPKL- 5 D25 / D26 Change to SCA00001100 for ESD 20090921 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Amplifier & Audio Jack Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet E 34 of 48 Rev 1.0 A B C D E +5VALW +5VALW SUSP 2 470_0603_5% 2 1 1 1 +1.05VS SYSON# <29> SYSON# 6 @ JUMP_43X118 PJ12 2 2 1 1 Q57A @ JUMP_43X118 SYSON <30,42> SYSON 1 2 2N7002DW-T/R7_SOT363-6 1 1 1 2 PJ13 2 +1.05VS_VTT R933 R934 100K_0402_5% Q56B 2N7002DW-T/R7_SOT363-6 5VS_GATE SUSP 5 6 1 4 2 2 1 R935 200K_0402_5% +VSB 2 1 3 SI4800BDY-T1-GE3_SO8 C842 1U_0603_10V6K 2 3 2 1 1 C845 10U_0805_10V4Z C844 5 6 7 8 10U_0805_10V4Z 2 10U_0805_10V4Z C843 1 1 R932 100K_0402_5% 4 +5VS U25 1 2 +5VALW TO +5VS C846 Q56A 0.1U_0603_25V7K 2 2N7002DW-T/R7_SOT363-6 1 2 +3VALW TO +3VS +3VS C47 1 C48 1 C50 R937 100K_0402_5% <41> SUSP 2 SUSP G Q59 2N7002_SOT23 S 5VS_GATE 1 2 560P_0402_50V7K 2 560P_0402_50V7K 2 2 D 1 C46 1 C49 SUSP For EC B+ 20100507 Q57B 5 <30,41,43> SUSP# 2N7002DW-T/R7_SOT363-6 1 For LAM Common mode noise 200911102330 R938 10K_0402_5% 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 6 SUSP C854 1 2 R939 470_0603_5% Q31B 2N7002DW-T/R7_SOT363-6 1.5VS_GATE 2 1 R940 28K_0402_1% +VSB 3 1 10U_0805_10V4Z 2 2 C851 SI4800BDY-T1-GE3_SO8 1U_0603_10V6K 3 2 1 3 1 C853 5 6 7 8 1 5 SUSP 3 4 C852 4 +1.5VS U24 1 2 +1.5V to +1.5VS +1.5V 2 3 2 R936 1 1 1 2 560P_0402_50V7K 2 560P_0402_50V7K 2 560P_0402_50V7K 2 560P_0402_50V7K 1 4 2 C850 C45 470_0603_5% 2 SI4800BDY-T1-GE3_SO8 +5VALW 1 3 1 1U_0603_10V6K 2 2 C848 B+ +3VS 3 2 1 1 C849 10U_0805_10V4Z 1 10U_0805_10V4Z C847 10U_0805_10V4Z U26 5 6 7 8 4 +3VALW C855 0.1U_0603_25V7K 2 Q31A 2N7002DW-T/R7_SOT363-6 R941 2.2M_0402_1% @ 2N7002_SOT23 Q60 @ S 3 3 S 2 1 1 D 2 SUSP G Q61 2N7002_SOT23 R944 470_0603_5% D 2 SUSP G Q62 2N7002_SOT23 S 3 D +1.5V 2 2 1 1 1 R943 22_0402_5% 1 R942 470_0603_5% 4 +1.8VS R945 470_0603_5% @ 4 1 S 1 D 2 G +0.75VS 2 +1.05VS_VTT 1 <30,39> ACIN 3 1 U24 / U25 / U26 Change to SB548000320 20090922 D 2 SUSP G Q63 2N7002_SOT23 S 3 1 2 2 2 SYSON# G Q64 2N7002_SOT23 @ 2009/5/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC Interface Size B Date: Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet E 35 of 48 Rev 1.0 A B C D VIN PC207 100P_0402_50V8J 1 PC208 100P_0402_50V8J 2 PC206 1000P_0402_50V7K 2 1 2 ACES_50305-00441-001 2DC_IN_S2 1 DC_IN_S1 1 PJP1 1 2 3 4 GND GND 1 PL24 SMB3025500YA_2P 1 2 1 PC209 1000P_0402_50V7K 2 2 PJ6 +3VALWP 2 VIN PJ2 2 1 1 +3VALW +VGFX_COREP 2 PJ5 PR305 68_1206_5% 2 2 1 1 <32> 51ON# +1.5V 1 1 3 +VSB JUMP_43X118 JUMP_43X39 VS 1 1 2 JUMP_43X118 PJ7 2 2 1 1 PJ11 +VSBP 1 PJ9 2 +1.05VS_VTTP PC213 0.1U_0603_25V7K 2 +1.8VSP 2 2 1 1 2 1 1 +1.05VS_VTT JUMP_43X118 PJ10 2 2 1 1 PJ14 2 PC212 0.22U_0603_25V7K 2 PR308 22K_0402_1% 1 2 2 PR307 100K_0402_1% 2 1 1 3 +5VALW 1 N1 1 1 +1.5VP PR304 68_1206_5% 2 PQ42 TP0610K-T1-E3_SOT23-3 2 JUMP_43X118 1 PD3 LL4148_LL34-2 2 1 +VGFX_CORE PJ8 +5VALWP 2 BATT+ 1 1 JUMP_43X118 PD2 LL4148_LL34-2 3 2 JUMP_43X118 PJ4 2 2 1 1 2 JUMP_43X118 2 +1.8VS JUMP_43X118 JUMP_43X118 PJ17 +0.75VSP 2 2 1 1 +0.75VS JUMP_43X79 +3VLP 4 +CHGRTC PR310 0_0603_5% 1 4 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title DCIN Size Document Number Custom Rev 1.0 PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet D 36 of 48 A TH PI PR542 100_0402_1% 2 PR543 100_0402_1% VL +3VALW P PR546 21K_0402_1% 1 VCC TMSNS1 8 2 GND RHYST1 7 3 OT1 TMSNS2 6 OT2 RHYST2 5 PR549 9.53K_0402_1% @ PR551 47K_0402_1% 1 2 4 PH1 100K_0402_1%_NCP15W F104F03RC 1 G718TM1U_SOT23-8 1 2 PR550 1K_0402_1% @ PR547 100K_0402_1% 1 PU30 2 1 2 PR545 10K_0402_1% 2 PC381 0.1U_0402_10V7K PR548 6.49K_0402_1% 2 1 2 PR544 1K_0402_5% 1 PC380 0.01U_0402_25V7K 1 EC_SMB_CK1 <30> 1 2 2 PC379 1000P_0402_50V7K VL EC_SMB_DA1 <30> 1 1 <40,41> BATT+ 2 PL44 SMB3025500YA_2P 1 2 BATT_S1 1 1 <40,41> VMB CONN@ PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C 2 EC_SMCA D 1 PJP2 SUYIN_200275GR008G13GZR EC_SMDA C 1 10 9 8 7 6 5 4 3 2 1 2 1 GND GND 8 7 6 5 4 3 2 1 B 2 BATT_TEMP <30> MAINPW ON <18,38> 2 1 2 2 @ PH2 100K_0402_1%_NCP15W F104F03RC PQ44 TP0610K-T1-E3_SOT23-3 1 2 PC222 0.1U_0603_25V7K 2 @ 3 2 2 PR327 22K_0402_1% 1 2 VL +VSBP 1 2 1 1 PR325 100K_0402_1% 3 PC221 0.22U_0603_25V7K 3 B+ PR330 1K_0402_5% 2 PC224 1U_0402_6.3V6K D S 2N7002W -T/R7_SOT323-3 2 1 PQ45 2 G 1 1 <38> SPOK 3 1 PR329 100K_0402_1% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet D 37 of 48 Rev 1.0 5 4 3 2 1 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO PC1000 1U_0603_10V6K 2VREF_8205 PR565 PC1010 2.2_0603_5% 0.1U_0603_25V7K BST_5V 1 2 1 2 LG_5V 3 2 1 2 RT8205EGQW _W QFN24_4X4 2 D PQ100B DMN66D0LDW -7_SOT363-6 5 G 4 1 2VREF_8205 S Typ: 175mA +5VALWP 1 PC1014 220U_6.3V_M + 2 RT8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) B TPS51125A TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP) (2)SMPS2=305KHZ(+3VALWP) 3.3VALWP Delta I = 1.902A (Freq=305KHz) Iocp = 5.931A ~ 7.100A 5VALWP Delta I = 3.199A (Freq=245KHz) Iocp = 8.759A ~ 10.449A 1 1 PR570 100K_0402_1% 2 3 2 1 1 RT8205_B+ PC1016 4.7U_0805_10V6K 1 2 1 PC1015 1U_0603_10V6K 2 1 VL 2 PC1017 0.1U_0603_25V7K 3 6 G S 1 4 18 17 16 13 1 19 PR567 4.7_1206_5% LGATE1 PL47 4.7UH_SIL104R-4R7PF_5.7A_30% 1 2 PC1013 680P_0402_50V7K LGATE2 NC LX_5V VREG5 UG_5V 20 VIN 21 PHASE1 GND UGATE1 PHASE2 EN UGATE2 5 6 7 8 VFB=2.0V 5 6 7 8 PC1007 0.1U_0603_25V7K 2 1 PC1006 2200P_0402_50V7K 2 1 PC1005 10U_1206_25V6M 2 1 22 AO4712_SO8 PQ99 2 ENTRIP2 D 2 1 2 FB1 23 BOOT1 B VL ENTRIP1 REF 3 4 TONSEL 6 5 FB2 PGOOD BOOT2 C SPOK <37> B+ ENTRIP1 PQ100A DMN66D0LDW -7_SOT363-6 PQ97 AO4466_SO8 4 VREG3 PR568 499K_0402_1% 1 2 1 2 3 2 12 PR563 154K_0402_1% 2 24 4 PR569 100K_0402_1% + LG_3V PQ98 AO4468_SO8 PC1012 680P_0402_50V7K 2 1 PC1011 220U_6.3V_M 8 7 6 5 PR566 4.7_1206_5% 2 1 PL46 4.7UH_SIL104R-4R7PF_5.7A_30% 1 2 1 RT8205_B+ VO1 VO2 15 1 2 3 8 PR564 2 1 2 BST_3V 9 2.2_0603_5% UG_3V 10 PC1009 0.1U_0603_25V7K LX_3V 11 1 1 P PAD SKIPSEL 25 7 +3VALWP ENTRIP2 PU1000 1 PC1008 4.7U_0805_10V6K 8 7 6 5 C PR562 137K_0402_1% 1 2 ENTRIP1 PR561 20K_0402_1% 1 2 2 PC1003 10U_1206_25V6M 2 1 PC1004 2200P_0402_50V7K 2 1 PQ96 AO4466_SO8 4 1 PR560 20K_0402_1% 1 2 ENTRIP2 PR559 30K_0402_1% 1 2 +3VLP 1 PC1002 0.1U_0603_25V7K 2 1 1 2 2 @ PC1028 0.1U_0603_25V7K PC1001 680P_0402_50V7K 2 1 B+ Typ: 175mA PR558 13K_0402_1% 1 2 14 RT8205_B+ PL48 FBMA-L18-453215-900LMA90T_1812 D 2 D <18,37> MAINPWON D S 2 G 2 1 2 3 +3.3VALWP Ipeak=4.72A ; Imax=4.00A Delta I=1.547A=>1/2Delta I=0.773A (F=375K Hz) Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Ilimit_min=(137K*10uA)/(10*22m*1.2)=5.18A Ilimit_max=(133K*10uA)/(10*17.4m*1.2)=6.56A Iocp=5.962A~7.334A +5VALWP Ipeak=7A ; Imax=4.9A Delta I=2.613A=>1/2Delta I=1.306A (F=300K Hz) Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Ilimit_min=(154K*10uA)/(10*18m*1.2)=7.12A Ilimit_max=(154K*10uA)/(10*15m*1.2)=8.555A Iocp=Ilimit+1/2Delta I =8.426A ~ 9.861A 1 1 3 PQ102 2N7002W -T/R7_SOT323-3 PR592 <39> ACPRN200K_0402_1% PQ101 PDTC115EUA_SC70-3 2 1 2 PR571 100K_0402_1% PC1019 2.2U_0603_10V6K VS 2 1 PR572 40.2K_0402_1% 1 A A PQ103 PDTC115EUA_SC70-3 2 Compal Secret Data Security Classification 3 <30,32> EC_ON 2009/02/04 Issued Date 2010/02/04 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. 3VALW/5VALW Size Document Number Custom Rev 1.0 PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 38 of 48 B 2 2 1 PR366 2 10K_0402_1% PR368 100_0402_1% 1 2 4 2 1 1 1 1 5 ICOMP CSIN 20 6 VCOMP CSIP 19 7 ICM PHASE 18 PC254 0.047U_0402_16V7K 1 2 PR364 20_0402_5% 2 1 PR365 PC257 20_0402_5% 0.1U_0603_25V7K 1 2 PR367 2_0402_5% LX_CHG 8 VREF UGATE 17 DH_CHG 9 CHLIM BOOT 16 ACLIM VDDP 15 VADJ LGATE 14 GND PGND 13 CSOP 2 PQ112 2N7002W -T/R7_SOT323-3 ACPRN 2 PQ62 G AO4466_SO8 CV mode 1 S 1 12 2 1 2 <40,41> TCR=50ppm / C PL29 10UH_PCMB104T-100MS_6A_20% 1 2 2 1 CHG @ 4 1 3 2 1 2 RB751V-40_SOD323-2 1 26251VDD PR376 4.7_0603_5% PC265 4.7U_0603_6.3V6K BATT+ 4 PR369 0.02_1206_1% 3 1 2 PQ64 AO4468_SO8 6251VDDP DL_CHG S 4 PC260 0.1U_0603_25V7K 2 BST_CHGA 2 1 PD13 2 11 1 2 BATT Type D @ @P ISL6251AHAZ-T_QSOP24 2N7002W -T/R7_SOT323-3 PR379 15.4K_0402_1% 1 2 2 6251VDD PR589 10K_0402_1% 1 2 1 1 PR381 31.6K_0402_1% 1 PACIN 2 1 2 PR587 47K_0402_1% PR590 14.3K_0402_1% 2 PQ111 PDTC115EU_SOT323 2 ACPRN 3 Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 ACIN <30,35> PR588 10K_0402_1% 1 Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 Charging Voltage (0x15) 10 S @ PQ61 2N7002W -T/R7_SOT323-3 2 PACIN G 3 <30> CALIBRATE# CC=0.6~4.48A IREF=0.7224*Icharge Ki=0.7224 IREF=0.43V~3.24V PQ66 2 G 3 3 CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A 6251aclim 20K_0402_1% PR378 2 12.1K_0402_1% 2 6251VREF 1 <30> 65W/90W# 3 PR373 0_0603_5% BST_CHG 1 D @ D 3 21 PC253 0.1U_0603_25V7K 2 1 CSOP PC1027 2200P_0402_50V7K CELLS CSON 2 CSON 4 PR363 20_0402_5% 1 2 1 EN 22 VIN_1 ACPRN <38> 23 PR375 1 PR374 100K_0402_1% 2 0.1U_0402_16V7K PR377 2.55K_0402_1% ACOFF <30> IREF 6251VREF PC259 1 2 PR372 80.6K_0402_1% 2 1 2 1 PC261 0.01U_0402_25V7K 2 1 PQ65 PDTC115EU_SOT323 <30,40> ACOFF <30> ADP_I PR371 47K_0402_5% 1 2 1 PACIN 1 3 1 2 2 2 ACPRN ACSET ACPRN 5 6 7 8 PC256 0.01U_0402_25V7K 2 2 1 1 6251VDD 6800P_0402_25V7K 2 PR574 14.3K_0402_1% PC252 0.1U_0603_25V7K 2 1 PC264 10U_1206_25V6M 2 1 1 1 1 PC255 1 DCIN DCIN 3 S @ PD19 BAS40CW _SOT323-3 3 2 1 2 @ PR357 200K_0402_1% 1 2 VIN PC263 10U_1206_25V6M 2 1 S 4 1 PQ59B DMN66D0LDW -7_SOT363-6 2 ACOFF PQ57 PDTC115EU_SOT323 1 PQ59A 5 G DMN66D0LDW -7_SOT363-6 2 G 2 D 3 3 6 PDTC115EU_SOT323 D 6251_EN VDD 24 2 PQ60 2 <30> 3S/4S# 1 1 VIN PR356 10K_0402_1% ACSETIN PC1020 1000P_0402_25V8J 1 PR362 2 2 3 PR361 150K_0402_1% PR576 10_1206_5% PR352 47K_0402_1% 1 2 PR591 100K_0402_5% 2 @ PR575 PR573 191K_0402_1% 191K_0402_1% PD18 RB751V-40_SOD323-2 PU17 1 6251VDD 1 PR359 0_0402_5% 2 1 PR360 47K_0402_5% 2 1 1 1 <30> FSTCHG 100K_0402_1% 47K PQ58 PDTC115EU_SOT323 1 PC250 2.2U_0603_6.3V6K 2 1 ACSETIN PR354 200K_0402_1% PreCHG 8 7 6 5 3 PC248 5600P_0402_25V7K 1 2 4 1 3 2 2 VIN_1 CSIP VIN PQ56 PDTA144EU_SOT323-3 47K 2 PC249 0.1U_0603_25V7K 2 1 1 4 1 PR353 200K_0402_1% 1 2 3 CSIN 1 3 PR370 4.7_1206_5% 4 2 2 1 3 2 1 8 7 6 5 PQ53 AO4435L_SO8 PC247 2200P_0402_25V7K 2 1 1 2 3 CHG_B+ PL45 HCB4532KF-800T90_1812 1 2 5 6 7 8 1 2 3 B+ PR351 0.02_2512_1% PC246 0.1U_0603_25V7K 2 1 8 7 6 5 P3 PC245 10U_1206_25V6M 2 1 VIN PQ52 AO4407A_SO8 P2 B+ CP = 85%*Iada ; CP = 4.07A CP = 85%*Iada ; CP = 2.91A ADP_I = 19.9*Iadapter*Rsense PQ51 AO4435L_SO8 D PC244 10U_1206_25V6M 2 1 Iada=0~4.74A(90W/19V=4.736A) Iada=0~3.42A(90W/19V=3.421A) C PC262 C262 680P_0402_50V7K A 4 4 Normal 3S LI-ON Cells 12600mV 12.60V Issued Date A Compal Electronics, Inc. Compal Secret Data Security Classification - 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C Title CHARGER Size Document Number Custom Rev 1.0 PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet D 39 of 48 5 4 3 2 1 D D PreCHG PR386 1K_1206_5% 1 2 PR388 1K_1206_5% 1 2 VIN TP0610K-T1-E3_SOT23-3 PQ67 PD14 LL4148_LL34-2 2 1 3 B+ 1 2 1 PR393 C 1 2 2 100K_0402_5% PR391 1K_1206_5% 1 2 C 100K_0402_5% PR392 1 PR390 1K_1206_5% 1 2 <30,39> ACOFF 2 1 +5VALWP 1 2 1 PR396 100K_0402_5% PQ68 PDTC115EU_SOT323 PD20 2 PQ70 PDTC115EU_SOT323 3 BAS40CW _SOT323-3 3 3 2 B B A A 2007/09/20 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PRECHARGE Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 40 of 48 Rev 1.0 5 4 3 2 1 FB=0.6V Note:Iload(max)=3.5A 1 1 2 1 PR405 4.99K_0402_1% 2 @ SY8033BDBC_DFN10_3X3 PC382 680P_0603_50V7K 1 2 PC1026 0.1U_0402_10V7K 1 2 PC274 0.47U_0603_16V7K 2 2 NC FB_1.8V 1 TP NC 7 11 1.8V_EN PR407 10K_0402_1% PC279 22U_0805_6.3VAM 6 1 FB 2 EN +1.8VSP PC278 22U_0805_6.3VAM SVIN 5 3 D PL30 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% 1 2 PC1022 68P_0402_50V8J 2 1 8 LX LX_1.8V 1 PVIN 2 2 9 LX 1 PVIN PR553 4.7_1206_5% 1 <30,35,43> SUSP# PR401 22K_0402_5% 1 2 10 2 PC282 22U_0805_6.3VAM 4 PU20 +3VALW PG D C C B B PJ20 JUMP_43X79 2 1 1 +1.5VP 8 NC 7 3 VREF VCNTL 6 4 VOUT NC 5 TP 9 +3VALW 1 NC GND 2 2 PR408 1K_0402_1% 1 PC284 4.7U_0603_6.3V6K VIN 2 1 2 2 PU21 1 PC285 1U_0402_6.3V6K 2 1K_0402_1% 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 1 PC288 10U_0805_6.3V6M A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date +0.75VSP 2 PR410 2N7002W -T/R7_SOT323-3 PC286 0.1U_0402_16V7K 2 1 S 1 D 2 PC287 0.033U_0402_16V7K A PQ72 2 G 1 PR409 28K_0402_1% 1 2 1 <35> SUSP 3 UP7711U8 PSOP 8P 2 Title +1.8VSP/+0.75VSP Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 41 of 48 Rev 1.0 A B C D PL31 FBMA-L18-453215-900LMA90T_1812 1 LX 12 LX_1.5V ILIM 11 G5603RU1U_TQFN14_3P5X3P5 2 2 PC296 4.7U_0603_6.3V6K 2 1 2 1 2 + 1 9 PC295 4.7U_0805_10V6K 1 2 2 PGND DL LG_1.5V +1.5VP PC293 330U_6.3V_M PC294 680P_0603_50V7K 3 2 1 7 AGND FB PQ74 AO4712_SO8 4 1 VDD 10 PR415 4.7_1206_5% +5VALW 2 VCC 1 4 DH 0.1U_0603_25V7K PR417 18.2K_0402_1% OUT 2 1 UG_1.5V TON 6 open-drain PGOOD Rds=4.5mΩ(Typ) 5.6mΩ(Max) 2 VFB=0.75V 1 PR418 5.9K_0402_1% 1 2 1 PL32 1.8UH_1164AY-1R8N=P3_9.5A_30% 1 2 PC292 1 5 6 7 8 14 TP 1 15 BST 13 3 1 +5VALW EN_SKIP 2 PR416 100_0603_1% 1 2 PR414 2.2_0603_5% 1 2BST_1.5V-1 2 5 PC383 560P_0402_50V7K 3 2 1 BST_1.5V PU22 8 1 1.5V_EN @ PC291 0.1U_0402_16V7K 2 @ PR413 47K_0402_5% 1 4 1 PR412 0_0402_5% 1 2 <30,35> SYSON PR411 280K_0402_1% 1 2 B+ 2 PC290 4.7U_0805_25V6-K PQ73 AO4466_SO8 2 Because +1.5VSP has 17.74A power budget, it includes DDR3, VGA chip, VRAM, so must use molding choke. 2 5 6 7 8 1 EN_PSV 1. GND=>Disable SMPS 2. FLOAT=>PWM_only mode 3. HIGH=>Auto_skip mode PC289 4.7U_0805_25V6-K 51117_1.5V_B+ VFB=0.75V Vo=VFB*(1+PR418/PR419)=1.52V Freq=282KHz(min) , 300KHz(typ) 2 PR419 5.76K_0402_1% Cesr=15m ohm Iocp=9.94A~13A 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2009/08/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title 1.5VP Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet D 42 of 48 Rev 1.0 5 4 3 1 PL37 FBMA-L18-453215-900LMA90T_1812 1 2 PR470 280K_0402_1% 1 2 PR461 1 1.05V_EN BST_1.05VS_VTT 2 2.2_0603_5% 1 1 1 15 TON DH 13 3 OUT LX 12 4 VCC ILIM 11 VDD 10 DH_1.05VS_VTT LX_1.05VS_VTT +5VALW G5603RU1U_TQFN14_3P5X3P5 PR465 4.7_1206_5% PC329 4.7U_0805_10V6K PQ83 TPCA8028-H_SOP-ADVANCE8-5 4 1 3 2 1 1 1 + PC332 680P_0603_50V7K 2 PR467 8.66K_0402_1% C 1 5 DL_1.05VS_VTT 2 9 1 DL +1.05VS_VTTP PL38 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 2 PGND PGOOD 8 6 AGND FB 7 5 VFB=0.75V VTT_SENSE <7> 3 2 1 TP BST 2 1 2 PC330 4.7U_0603_6.3V6K PR473 10_0402_5% 1 2 4 EN_SKIP PU999 PR463 100_0603_1% 1 2 +5VALW PQ82 TPCA8030-H 1N SOP-ADV 14 1 PC331 0.22U_0603_16V7K 2 2 @ PR468 10K_0402_5% 2 PC328 0.1U_0603_25V7K 1 2 PR466 80.6K_0402_1% 1 2 <30,35,41> SUSP# 5 PC384 560P_0402_50V7K 2 1 D VTTP_B+ 1 PC385 560P_0402_50V7K 2 1 PC326 10U_1206_25V6M 2 1 2 B+ PC327 10U_1206_25V6M D C 2 PC333 390U_2.5V_M 2 PR472 2.4K_0402_1% 1 2 Material Note: 330uF/9 mΩ, number are 3, Power 1, HW 2 Rdson=2.3mΩ/3.2mΩ 2 PR476 5.9K_0402_1% Change from APW7138 to RT8209 at 2010-0428 night. 1 1 2 @ PR462 1K_0402_1% 1 2 VFB=0.75V Vo=VFB*(1+PR308/PR309)=1.05V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=2.74E-07 Freq=282KHz , 300KHz(typ) PR459 2K_0402_1% PGOOD=1V @ H_VTTPWRGD <5> +3VS PR460 2K_0402_1% B +5VS 2 PR458 0_0402_5% 1 2 B Cesr=15m ohm Ipeak=19.6A Imax=13.72A Iocp=23.52A Delta I=((19-1.05)*(1.05/19))/(L*Freq)=1.837A =>1/2 Delta I=0.918A Vtrip=Rtrip*10uA=0.0866V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+1/2 Delta I = 23.471A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+1/2 Delta I =32.295A Iocp=22.4A~30.8A A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/4/15 2010/04/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +1.1VS_VTTP Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 43 of 48 Rev 1.0 5 4 3 2 1 Intel Auburndale CPU(Integrate Graphics) Ipeak=22A Imax=15A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum)=0.617 where Rn=PR277 // (PR274+PH3)=5.875k ohm Rsum=PR269=3.65k ohm LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm Iocp=OCP Threshold*Rdroop/LL=24.89A 2 PC191 0.22U_0402_6.3V6K GFXVR_IMON ISUMBST_GFX 1 1 2 1 3 2 1 PL10 0.45UH_PCMB104T-R45MN_25A_20% 15 DH_GFX PR269 3.65K_0805_1% PQ41 AO4456_SO8 4 2 4 2 +5VALW 1 1 PC198 2.2U_0603_6.3V6K PC199 680P_0603_50V7K Rds=4.5mOHM(typ) Rds=5.6mOHM(max) + PH3 2 1 PC130 330U_X_2VM_R6M 2 2 2.61K_0402_1% 10K +-5% TSM0A103J4302RE 0402 1 PR276 8.06K_0402_1% 1 PR270 0_0402_5% PR274 2 13 1 21 2 1 PR268 4.7_1206_5% PR273 1 2 0_0603_5% 3 +VGFX_COREP 2 PQ40 AO4456_SO8 19 20 1 1 1 17 18 DL_GFX 4 5 6 7 8 5 6 7 8 16 LX_GFX 2 VID2 VID3 C 14 VID1 VID4 PQ39 TPCA8030-H 1N SOP-ADV 4 BOOT 12 VIN IMON 10 9 11 VDD RTN ISUM ISUM+ VID0 CLK_EN# 2 22 1 PR275 17.8K_0402_1% PGOOD 23 1 2 PC200 150P_0402_50V8J VCCP 24 2 PC201 22P_0402_50V8J 1 2 1 RBIAS VID5 147K for CPU 47K for GPU PC196 100P_0402_50V8J LGATE 25 2 VSSP VW VID6 2 1 2 PHASE COMP 28 1 PC197 1000P_0402_50V7K 2 1 3 VR_ON 4 PR294 2 1 47K_0402_1% 1 PC193 0.22U_0603_25V7K DCR=1.1 mOHM UGATE PU12 ISL62881HRZ-T_QFN28_4X4 FB DPRSLPVR 5 PR272 825K_0402_1% VSEN 26 6 27 7 PR271 8.66K_0402_1% 2 1 8 29 PC195 330P_0402_50V7K AGND PR293 2 1 10_0402_1% 2 2 1 2 PR266 2.2_0603_5% PC194 330P_0402_50V7K 3 2 1 <8> VSS_AXG_SENSE <8> VCC_AXG_SENSE <8> 5 ISUM+ PC192 1000P_0402_50V7K 1 2 C +VGFX_COREP 1 2 2 PR265 22.6K_0402_1% 3 2 1 PR292 2 1 10_0402_1% 2 PC189 1U_0402_6.3V6K VSS_AXG_SENSE 1 1 1 PR263 0_0603_5% PR264 2 1 1_0603_5% 2 2 +5VALW PC190 0.22U_0603_25V7K @ PC188 0.1U_0402_25V6 1 1 PC126 10U_1206_25V6M 2 1 PC125 10U_1206_25V6M 2 1 1 2 PC187 2200P_0402_50V7K 1 1 2 PC386 560P_0402_50V7K D PL23 FBMA-L11-322513-201LMA40T_1210 GFX_B+ 1 2 2 B+ PC1029 0.1U_0603_25V7K D Layout Note: Place near Choke 2 PR277 11K_0402_1% 1 Material Note: 330uF/6 mΩ, number are 3, PW 1, HW 1, 1 of HW is backup 2 PC202 0.1U_0402_16V7K @ PR555 0_0402_5% 2 1 GFXVR_VID_0 <8> GFXVR_VID_1 <8> GFXVR_VID_2 <8> GFXVR_VID_3 <8> GFXVR_VID_4 <8> GFXVR_VID_5 <8> GFXVR_VID_6 <8> GFXVR_EN <8> GFXVR_DPRSLPVR B PR283 PR288 1.69K_0402_1% 82.5_0402_1% 1 2 1 2 PC204 0.01U_0402_16V7K <8> 2 2 PC203 0.1U_0402_16V7K @ PR284 100_0402_1% 1 PR280 PR281 PR282 PR285 PR286 PR287 PR289 PR290 PR291 2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 1 <30> GFX_CORE_PWRGD B ISUM+ @ PC205 180P 50V J NPO 0402 ISUM- +1.05VS_VTT 2009-1214 common circiut modify. A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/4/15 Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title GFX_COREP Size C Date: 5 4 3 2 Document Number PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 1 44 of 48 Rev 1.0 7 6 5 4 3 2 CPU_VID2 <7> CPU_VID3 <7> CPU_VID4 <7> CPU_VID5 <7> CPU_VID6 <7> H_PSI# <7> H_DPRSLPVR <7> <7> CPU_VID1 CPU_VID0 <7> HFM_VID H PH0 PH1 HFM_Icc 1 LL Auburndale 45W 1.075 50 1.9m 37 35 Auburndale 35W 0.975 38 1.9m 29 27 Clarksfield SV 0.95 51 1.9m 38 39 Clarksfield XE 0.95 65 TBD 48 TBD 0 1 2 1 1 3 +CPU_B+ 1 PGND TRDET DRVL2 SW2 3212_DRVL2 PR506 100_0402_1% 1 2 3212_CS_PH2 28 PC350 4.7U_0603_6.3V6K 3212_SW2 27 3212_DRVH2 26 25 2 1 PC358 0.1U_0603_25V7K 2 1 2 1 2 PC343 220U_25V_M PC387 560P_0402_50V7K 2 1 1 2 2 3 2 1 1 5 PR523 165K_0402_1% 1 2 2 1 PC359 680P_0603_50V7K CSREF 3 2 1 D PR513 10_0402_5% 3212_CS_PH2 4 2 PR522 73.2K_0402_1% 2 1 PC363 1200P_0402_50V7K 1 2 PC362 330P_0402_50V7K 2 1 1 1K_0402_1% PC360 0.01U_0402_50V7K 2 PH6 100K_0402_1%_NCP15WF104F03RC C 1 1 +CPU_B+ 2 PR520 PC361 1000P_0402_50V7K PR524 2 2 TTSense 3 PR512 4.7_1206_5% 1 2 Place PH1 close to PHASE 1 inductor on the same layer 1 2 PR517 649K_0402_1% Connect to input caps C PR521 0_0402_5% 1 3212_CSCOMP 3212_CSCOMP 2 PR516 1 162K_0402_1% 1 1 2 2 1 PR519 2.05K_0402_1% 2 PR518 7.32K_0402_1% 3 PQ94 2N7002W-T/R7_SOT323-3 +5VALW S PL41 0.36UH +-20% ETQP4LR36WFC 24A 4 1 PQ92 TPCA8028-H_SOP-ADVANCE8-5 3212_DRVL2 3212_VRTT 2 G E 3212_DRVH2 2.05K PR515 69.8K_0402_1% D PQ90 TPCA8030-H_SOP-ADV8-5 PR557 2.2_0603_5% 2 13212_DRVH2_1 4 PR509 2.2_0603_5% TP BST2 +CPU_B+ 30 29 2 1 PR514 80.6K_0402_1% 1 2 +5VALW 3212_DRVL1 3212_SW2 PR510 @ 499_0402_1% PC347 680P_0603_50V7K CSREF 32 31 F 3212_CS_PH1 PR502 1 33 4 3212_SW1 100_0402_1% 3212_CS_PH1 2 34 49 SWFB3 24 PWM3 OD3 ILIM 22 23 21 20 19 CSREF LLINE 18 17 13 CSCOMP DRVH2 GND CSSUM TTSNS RAMP 11 SWFB2 VRTT 16 TTSense VARFREQ RT 10 15 9 3212_VRTT 2 1 Avoid high dV/dt +CPU_CORE PR500 10_0402_5% 2 3212_DRVL1 3212_DRVH1 35 1 COMP IREF 2 2 1 1 1 <5> H_PROCHOT# 2 3 PR499 4.7_1206_5% 2 DRVL1 NCP3218MNR2G_QFN48_6X6 +3VS PR511 0_0402_5% G + 1 1 PVCC FB PR508 0_0402_5% D 3 2 1 5 38 39 37 VCC PH1 PH0 PSI VID6 VID5 VID4 VID3 VID2 FBRTN RPM 8 12 PR507 0_0402_5% PC341 4.7U_0805_25V6-K 1 2 2 5 2 2 40 42 41 43 44 45 46 47 48 SWFB1 14 E B+ 1 PC355 4.7U_0805_25V6-K 7 CLKEN PQ88 TPCA8028-H_SOP-ADVANCE8-5 1 1 6 SW1 2 PC349 1000P_0402_50V7K DRVH1 IMON PC346 0.1U_0603_25V7K 2 1 2 5 2 2 PWRGD PR498 2.2_0603_5% 2 1 36 PC354 4.7U_0805_25V6-K 4 BST1 1 2 CLK_EN# EN 2 DCR=1.1m OHM 2 3 AGND 3 2 1 1 IMVP_IMON PC348 3212_FBRTN 0.068U_0402_16V7K PC351 150P_0402_50V8J 3212_FB 1 2 PC353 PC352 150P_0402_50V8J PR504 12P_0402_50V8J PR503 1.65K_0402_1% 39.2K_0402_1% 1 2 1 21 2 2 1 PR505 5.11K_0402_1% +5VALW 1 1 PL40 0.36UH +-20% ETQP4LR36WFC 24A 1 4 5 2 PR501 5.49K_0402_1% B+ 4 1 1 2 2 <7> IMVP_IMON PR491 0_0603_5% 2 1 2 PR496 0_0402_5% DPRSLP @ PU27 VID1 2 1 F PR556 2.2_0603_5% 3212_DRVH1 2 13212_DRVH1_1 3212_SW1 VID0 1 PQ87 TPCA8030-H_SOP-ADV8-5 PC344 1U_0603_16V6K PGND PR494 +1.05VS_VTT <12,15> VGATE 1 2 CLK_EN# PR497 0_0402_5% 2 PR490 0_0402_5% 1 1 2 PR493 3K_0402_5% 1 1 <12> CLK_ENABLE# PR489 2 +3VS PC339 4.7U_0805_25V6-K 0_0402_5% 2 1 499_0402_1% 1 +3VS PR495 0_0402_5% PL39 FBMA-L18-453215-900LMA90T_1812 2 PR481 10_0603_5% PR492 3K_0402_5% H 1 VR_ON <30> +5VALW G Icc_Dyn Icc_TDC # of PH PC342 4.7U_0805_25V6-K 2 1 8 2 CSREF 1 3212_CS_PH1 3212_CS_PH2 137K_0603_1% 2 2 PR525 137K_0603_1% 1 PC364 1U_0603_16V6K 1 PH7 1 100K_0402_1%_NCP15WF104F03RC B B @ PR526 100_0402_1% 2 1 VCCSENSE VSSSENSE 2 +CPU_CORE VCCSENSE <7> VSSSENSE <7> 1 PR527 100_0402_1% @ A A Compal Secret Data Security Classification 2009/02/04 Issued Date Deciphered Date 2010/02/04 Title CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size C Date: 8 7 6 5 4 3 Compal Electronics, Inc. 2 Document Number Rev 1.0 PEW71 M/B LA-6582P Schematic Thursday, July 08, 2010 Sheet 45 1 of 48 5 4 3 2 Version change list (P.I.R. List) Item 1 Page 1 of 2 for PWR Fixed Issue Reason for change Rev. PG# Modify List Date Phase Change PR353 from SD034470280 to SD034200380. D 2 Change PR587 from SD034100380 to SD034470280. Pre-Charge circiut update. Pre-Charge circiut disable in EVT, now modify and enable it. 0.1 39 5 6 7 C Change PR590 from SD034200280 to SD034143280. Change PR591 from SD028470280 to SD028100380. 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT Add PC1027 SE074222K80(S CER CAP 2200P 0402 50V7K) 3 4 D Change PR371 from SD034220280 to SD034470280. 1 Change PQ111 from SB000006800 to SB301150200 Pre-Charge circiut update. Pre-Charge circiut disable in EVT, now modify and enable it. Pre-Charge circiut update. Pre-Charge circiut disable in EVT, now modify and enable it. 0.1 38 0.1 40 Add PQ102 and PQ103 SB301150200. Add PR592 SD034200380. Change PR386 from SD011000080 to SD011100180. EMI fail, add 3/5V snubber and Boost Resister to silve it. Add PR388, PR390, PR391 SD011100180. Add PD14 SC100001Y80 LL4148_LL34-2 Add PR566 and PR567 SD001470B80 S RES 4.7 1206 EMI request to solve EMI issue. 0.1 38 5% Add PC1012 and PC1013 SE074681K80 S CER CAP 680P 0402 50V7K Change PR564 and PR565 from SD013000080 to SD013220B80 8 EMI fail, add 1.5V snubber. EMI request to solve EMI issue. 0.1 42 Add PR415 SD001470B80 4.7 1206 5%. Add PC294 SE025681K80 S CER CAP 680P 50V K X7R 0603 C Add PR465 SD001470B80 4.7 1206 5%. 9 EMI fail, add 1.05V snubber. and Boost Resister. 0.1 EMI request to solve EMI issue. 43 10 11 12 Add PC332 SE025681K80 S CER CAP 680P 50V K X7R 0603 Change PR461 from SD013000080 to SD013220B80 EMI fail, add GFX_CORE snubber. EMI request to solve EMI issue. 0.1 44 Add PR268 SD001470B80 4.7 1206 5%. Add PC199 SE025681K80 S CER CAP 680P 50V K X7R 0603 Change PR466 from SD034576280 S RES 1/16W 57.6K +-1% 0402 to SD034806280 S RES 80.6K 0402 1%) HW power sequence modify. HW request. 0.1 43 13 Change PC331 from SE076104K80 S CER CAP .1U 16V K X7R to SE00000R700 S CER CAP 0.22U 16V K X7R 0402 14 BOM unique. BOM unique. 0.1 38 Chnage PQ101 from SB301150000 to SB301150200. 2010/06/08 to PVT 15 EMI request. EMI request. 0.1 38 Add PC1028 SE042104K80 S CER CAP .1U 25V K X7R 0603 2010/06/08 to PVT 16 EMI request. EMI request. 0.1 44 Add PC1029 SE042104K80 S CER CAP .1U 25V K X7R 0603 2010/06/08 to PVT Sourcer request to change a common part. Sourcer request. 0.1 38 Change PC1019 from SE00000GC00 S CER CAP 2.2U 10V K X7R 0603 to SE000003H00 S CER CAP 2.2UF 10V K X5R 0603 2010/06/08 to PVT 18 Per sourcer request. Sourcer request to change PC331 from SE00000R700 to SE026224K80 for common part. 0.1 43 2010/06/08 to PVT 19 CPU transient issue. Need modify PC362 to 330P due to transient fail. 0.1 45 2010/06/08 to PVT 20 Per sourcer request. Per sourcer request. 0.1 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT 2010/06/08 to PVT B B 17 21 A 22 23 Cost down. Cost down 3VALWP and Charger Low Side MOS. 0.1 Cost down. Cost down +1.5VP Low side MOS and choke. 0.1 Cost down. re-caculate 1.5VP OCP. 0.1 44 38 39 42 42 Change PC362 from SE074561K80 S CER CAP 560P 50V K X7R 0402 to SE074331K80 S CER CAP 330P 50V K X7R 0402 Chnage PQ39/PQ82 from SB000008L80 to SB00000HL00. Change PQ98 from SB00000AJ00 to SB000009580(AO4468). Change PQ64 from SB00000CG00 to SB000009580(AO4468). Chnage PQ74 from SB000009F80 to SB00000AJ00(AO4712). CHnage PL32 from SH000009U00 to SH000009680. Change PR417 from SD034110280 to SD034182280. 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 43 change PC331 from SE00000R700 to SE026224K80 2 Title PIR (PWR) Size Document Number Custom Date: Thursday, July 08, 2010 Rev 1.0 Sheet 1 46 of 48 5 4 3 2 Version change list (P.I.R. List) Item Page 2 of 2 for PWR Fixed Issue Cost down. D 1 Reason for change Rev. PG# re-caculate +3VALWP OCP. 0.1 38 Modify List Date Change PR562 from SD034107380 to SD034137380. Phase 2010/06/08 to PVT D 24 25 26 27 28 29 30 C 31 C 32 33 34 35 36 37 38 B B 39 40 41 42 43 44 45 A A 46 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PIR (PWR) Size Document Number Custom Date: Thursday, July 08, 2010 Rev 1.0 Sheet 1 47 of 48 5 4 3 2 1 Version change list (P.I.R. List) Item 1 Phase PAGE DATE Modifycatio list EVT 04 / 08 04 / 16 N/A Modify RTC SCH Change LAN to AR8152 Update Power SCH Update AND Gate symbol - U1 / U2 / U6 / U7 / U19 Update Power MOS symbol - U24 / U25 / U26 C196 change to 1U for INTEL disign CLK GEN del C35 / C36 / C30 / C31 / C32 / C33 / C34 / L3 (for 3G@ and @ function) Q4+Q6 change to 2N7002DW Update U8 symbol Add DMIC function Modify USB define. Update Power SCH Add R17 for DMIC power Update Power SCH Change LAN to GIGA&10/100 co-lay Del R307 (LVDS conn.) Change +1.05VS_VTT to +1.05VS (CLK GEN) Change C842 / C850 / C854 / C656 to SE080105K80 1U_0603_10V6K Change R940 to 28K (S3 Power sequence) SW T1 pin define (LAN) Change R907 (0_0603) to 0_1206 5% Remove C40 / C41 / C42 / C43 / C44 Change FAN Conn. Update Power SCH Change LAN to BCM57780 GIGA Del R637 / R639 / R640 / R645 / R647 / R648 (AUDIO) Del DMIC Update Power SCH Update Power SCH Add C49 / C50 (EC B+) Update Power SCH C764 / C765 change to 18P_0402_50V8J (EC) Reserve D13 / D24 / D30 (ESD) U17 change to RTS5137 (SA000043500) Card reader Update Power SCH 04 / 21 D 04 / 26 04 / 27 04 / 29 04 / 29 05 / 03 05 / 03 05 / 06 05 / 07 05 / 10 05 / 11 05 / 12 05 / 13 C 06 / 01 06 / 02 Purpose C Unpop L11 / C247 & Pop R304 for cost down Unpop C764 / X2 & Pop R13 & C765 Change to 100K for EC remove Crystal Pop R834 & R835 change to 200K for Project ID Unpop D24 / D30 Unpop R690 / R691 Pop C49 / C50 For HDMI Unpop R753 / R757 , Add R754 / R758 to 0 ohm. Change R759 to 3.9K. Change R755 to 4.7K ohm , Unpop R748. Unpop R778. 06 / 10 R833 / R292 0_0805 change to 0_0603. C190 / C191 & C1135 / C1136 change to 33P 0402 50V8J for Vender test report Unpop C774~C799 for EMI cost down. Update Power SCH Add T25 / T26 / T27 07 / 07 07 / 08 Update Power SCH Change R759 to 4.32K_1% SD00000J280 06 / 03 06 / 04 D B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/07/01 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PIR (HW) Size Document Number Custom PEW71 M/B LA-6582P Schematic Date: Thursday, July 08, 2010 Sheet 1 48 of 48 Rev 1.0 www.s-manuals.com </pre><hr>Source Exif Data: <br /><pre>File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Format : application/pdf Creator : Title : Compal LA-6582P - Schematics. www.s-manuals.com. Subject : Compal LA-6582P - Schematics. www.s-manuals.com. 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