Compal LA 6832P Schematics. Www.s Manuals.com. R0.2 Schematics
User Manual: Motherboard Compal LA-6832P PHQAA Marseille 10R/10RG - Schematics. Free.
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A B C D E 1 1 PHQAA Marseille 10R/10RG 2 2 LA-6832P REV 0.2 Schematic Intel Processor(Sandy Bridge) / PCH(Cougar Point) 2010-09-03 Rev 0.1 3 3 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size B Date: Document Number Rev 0.2 PHQAA LA-6832P M/B Thursday, October 07, 2010 Sheet E 1 of 45 A B C D E Fan Control APL5607 Intel CPU Sandy Bridge 1 page 5 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 rPGA-989 37.5mm*37.5mm Dual Channel page 5,6,7,8,9,10 FDI X8 page 14 1.5V DDRIII 1066/1333/1600 MT/s DMI X4 2.7GT/s page 11,12 BANK 0, 1, 2, 3 USB/B Right CRT 1 Left USB USB port 0,1 page 25 5GT/s FingerPrinter USB port 2 page 25 Felica USB port 8 page 26 Int. Camera USB port 9 page 26 USB USB port 11 page 13 5V 480MHz LVDS Conn. page 13 2 USB 5V 480MHz EC SMBus HDMI-CEC page 15 1.5V 5GT/s Intel PCH Cougar Point - M page 15 RTL8105E 10/100M RTL8111E 1G PCIe port 1 RJ45 page 28 PCIeMini Card WLAN PCIe port 2 PCIeMini Card JET PCIe port 4 page 27 SATA port 0 PCIe 1x 5V 6GHz(600MB/s) USB port 12 USB port 10 page 27 3G/TV#1 TV#2 page 27 SATA HDD B-CAS page 26 SATA port 1 page 25 1.5V 5GT/s page 28 Express Card USB USB port 4 2 page 27 Express Card PCIe PCIe port 3 page 27 SIM page 27 FCBGA-989 25mm*25mm SATA port 2 5V 3GHz(300MB/s) Cardreader JMB389C PCIeMini Card page 27 PCIe 1x HDMI Conn. PCIeMini Card WiMax USB port 13 SATA ODD SATA port 4 page 25 PCIe 1x 1.5V 5GT/s page 16,17,18,19,20,21,22,23,24 PCIe port5 page 29 PCIe 1x USB3.0 TUSB7320 1.5V 5GT/s 3 3 PCIe port6 page 30 LPC BUS 3.3V 24MHz HD Audio 3.3V 33 MHz TP& Light Pipe/B LS-6061P page 34 Cap Sensor & Light Sensor/B LS-6062P page 34 RTC CKT. HDA Codec MDC 1.5 Conn SPI ROM (4MB) page 16 Debug Port ENE KB930 page 33 ALC269 page 26 page 31 page 32 page 16 DC/DC Interface CKT. LED/B LS-6063P Touch Pad page 34 Int.KBD EC ROM (128KB) page 33 page 33 page 34 page 35 4 Power Circuit DC/DC page 36,37,38,39,40 41,42,43,44 Power On/Off CKT. page 34 A page 32 Int. MIC Conn G-Sensor page 33 SPK Conn JPIO (HP &page MIC) 25 page 31 page 13 EC SMBus Audio & USB/B LS-6064P page 25 Finger Printer/B LS-6065P page 26 Power/B_FPC DA300006JM0 CIR 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. page 34 B C D Title Block Diagram Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet E 2 of 45 5 4 3 2 DESIGN CURRENT 0.1A 1 +3VL +5VL DESIGN CURRENT 0.1A B+ Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW DESIGN CURRENT 2A +1.8VS DESIGN CURRENT 4A +5VS SUSP# SY8033BDBC SUSP D N-CHANNEL D BCPWON SI4800 DESIGN CURRENT 0.5A +5VS_L_BCAS P-CHANNEL AO-3413 KB_LED UP6182CQAG DESIGN CURRENT 400mA +5VS_LED DESIGN CURRENT 300mA +3VS_HDP DESIGN CURRENT 1.6A +5VS_ODD P-CHANNEL AO-3413 +5VS LDO G9191 ODD_EN# P-CHANNEL AO-3413 Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW WOL_EN# P-CHANNEL AO-3413 DESIGN CURRENT 330mA +3V_LAN SYSON DESIGN CURRENT 0.2A C +3V P-CHANNEL AO-3413 SUSP DESIGN CURRENT 4A N-CHANNEL C +3VS LCD_ENVDD SI4800 P-CHANNEL AO-3413 DESIGN CURRENT 1.5A +LCD_VDD DESIGN CURRENT 0.5A +FLICA_VCC FELICA_PWR P-CHANNEL AO-3413 VR_ON ISL95831HRTZ-T DESIGN CURRENT 94A +CPU_CORE DESIGN CURRENT 33A +GFX_CORE DESIGN CURRENT 15A +1.05VS_VCCP SUSP# Ipeak=18A, Imax=12.6A, Iocp min=19.8 G5603RU1U B B VCCPPWRGD Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 6A Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 10A G5603RU1U +VCCSA SYSON +1.5V SUSP G5603RU1U N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU FDS6676AS SUSP N-CHANNEL DESIGN CURRENT 2A +1.5VS DESIGN CURRENT 1A +1.05V FDS6676AS +3V APL5930KAI-TRG SUSP or 0.75VR_EN# A A DESIGN CURRENT 1.5A UP7711U8 +0.75VS Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Power Tree Size 4 3 2 Rev 0.3 PHQAA LA-6832P M/B Date: 5 Document Number Sheet Thursday, October 07, 2010 1 3 of 45 A Voltage Rails B ( O MEANS ON C D E X MEANS OFF ) +5VS +RTCVCC B+ +5VL +5VALW +3VL +3VALW +1.5V +3VS +1.8VS +VSB +1.5VS power plane 1 1 +1.05VS BTO Option Table +0.75VS +CPU_CORE +VGA_CORE HDMI Function CPU +GFX_CORE HDMI description +VTT State +VRAM_1.5VS explain UMA Discrete/ Optimus BTO IHDMI@ DHDMI@ Arrandale COMMON Clarksfield CEC Arrandale Clarksfield Clarksfield with S3 Power Saving CEC@ M1@ M3@ PSM3@ +3VS_DGPU +1.05VS_DGPU MINI PCI-E SLOT Function S0 O O O O O O S1 O O O O O O S3 O O O O O X S5 S4/AC O O O O X X O O O X X X explain O X X X X X BTO BTO 2 S5 S4/ Battery only S5 S4/AC & Battery don't exist 3G 3G@ 3 Device HEX Address +3VS DDR SO-DIMM 0 A0 H 1010 0000 b +3VS DDR SO-DIMM 1 A4 H 1010 0100 b +3VS Clock Generator D2 H 1101 0010 b +3VS New Card +3VS WLAN/WIMAX +3VS Clock Generator +3VS 3G TV@ LAN WIMAX 10/100M WIMAX@ 8105E@ Fingerprint Modem CIR KB Light Fingerprint Modem CIR KB Light Giga Fingerprint Modem CIR KB Light 8111E@ FP@ MDC@ CIR@ KBL@ 2 BLUE TOOTH G-SENSOR description Felica BLUE TOOTH G-SENSOR SKU Felica BLUE TOOTH G-SENSOR Discrete BT@ GSENSOR@ FELICA@ LVDS SKU Felica Function DIS@ OPT@ Discrete 3D@ No Power Saving BTO NOPS@ Function description PS@ Card reader New Card JMB385C/389C New Card explain JMB389C BTO JMB385@ JMB389@ Camera & Mic OPTFH@ NO3D@ N11P & N11E Power Saving JMB385C Camera & Mic Optimus CAM@ GPU S3 Power Saving explain Camera & Mic 3D Panel Optimus S3 Power Saving description Power SLOT1 TV Tuner Function PCH SM Bus Address LAN SLOT2 description explain HDMI@ N11M VRAM N11P N11E N11M-GE1 N11M-GE2 N11M-OP1 8PCS@ N11P@ N11E@ N11MGE1@ N11MGE2@ N11MOP@ 3 New Card NEW@ SIGNAL STATE EC SM Bus1 Address 4 EC SM Bus2 Address SLP_S3# SLP_S4# SLP_S5# Full ON HIGH HIGH HIGH Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH +3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH +3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b LOW LOW HIGH G-Sensor 40 H S4 (Suspend to Disk) +3VS 0100 0000 b +3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW Power +3VL Device Cap. Sensor HEX Address 4 Virtual I2C 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 E 4 of 45 5 4 3 2 1 JCPUB 100 MHz H_SNB_IVB# <20> H_SNB_IVB# C26 MISC PROC_SELECT# PM_DRAM_PWRGD_R 1 C487 SNB_IVB# @ 1000P_0402_50V7K 2 H_PWRGOOD 1 C488 T1 TP_SKTOCC# PAD AN34 SKTOCC# CLOCKS @ 1000P_0402_50V7K 2 D <32> H_PECI +1.05VS_VCCP H_PECI AN33 1 2 2 H_PROCHOT#_R 56_0402_5% AL32 H_THERMTRIP#_R AN32 Stuff R41 and R42 if do not support eDP CLK_CPU_DMI <17> CLK_CPU_DMI# <17> A16 A15 DPLL_REF_SSCLK DPLL_REF_SSCLK# +1.05VS_VCCP CLK_CPU_DPLL CLK_CPU_DPLL# CLK_CPU_DPLL# R42 1 2 1K_0402_5% CLK_CPU_DPLL R41 1 2 1K_0402_5% D CATERR# PECI PROCHOT# H_PROCHOT# 1 62_0402_5% 2 <21> H_THERMTRIP# R51 AL33 R450 <32,37> H_PROCHOT# R47 H_CATERR# CLK_CPU_DMI CLK_CPU_DMI# 120 MHz R8 H_DRAMRST# AK1 A5 A4 SM_RCOMP_0 R1437 2 SM_RCOMP_1 R1438 2 SM_RCOMP_2 R1439 2 PRDY# PREQ# AP29 AP27 XDP_PRDY#_R XDP_PREQ#_R R1 1 R2 1 @ @ 2 0_0402_5% 2 0_0402_5% XDP_PRDY# XDP_PREQ# TCK TMS TRST# AR26 AR27 AP30 XDP_TCK_R XDP_TMS_R XDP_TRST#_R R4 1 R6 1 R7 1 @ @ @ 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% XDP_TCK XDP_TMS XDP_TRST# TDI TDO AR28 AP26 XDP_TDI_R XDP_TDO_R R8 1 R10 1 @ @ 2 0_0402_5% 2 0_0402_5% XDP_TDI XDP_TDO DBR# AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R R12 1 R13 1 R15 1 R18 1 R19 1 R20 1 R21 1 R23 1 @ @ @ @ @ @ @ @ 2 2 2 2 2 2 2 2 SM_DRAMRST# DDR3 MISC PAD THERMAL T2 A28 A27 BCLK BCLK# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] H_DRAMRST# <7> DDR3 Compensation Signals Layout Note:Place these resistors near Processor 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% THERMTRIP# H_PWRGOOD 1 10K_0402_5% H_PWRGOOD <21> H_PWRGOOD PM_SYS_PWRGD_BUF 1 R454 C AM34 AP33 2 PM_DRAM_PWRGD_R 130_0402_5% BUF_CPU_RST# V8 AR33 PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# +3VALW Routed as a single daisy chain R36 1 2 1K_0402_5% XDP_DBRESET# +3VS XDP_DBRESET# <18> C 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 R24 1 R25 1 R26 1 R27 1 @ @ @ @ 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% CFG12 CFG13 CFG14 CFG15 <10> <10> <10> <10> Close to CPU side +1.5V_CPU 1 Sandy Bridge_rPGA_Rev0p61 1 C93 0.1U_0402_16V4Z JTAG & BPM H_PM_SYNC <18> H_PM_SYNC PWR MANAGEMENT Remove R14(o ohm) for HW Review demand @ 2 2 5 1 2 B O A 4 PM_SYS_PWRGD_BUF PU/PD for JTAG signals +1.05VS_VCCP 3 1 <18> DRAMPWROK R339 200_0402_5% P <18,32> PM_PWROK U10 74AHC1G09GW_TSSOP5 G R312 0_0402_5% 1 2 R340 39_0402_5% @ @ 2 0_0402_5% 1 2 R3841 SUSP <9,35,42> SUSP 2 G 3 B D Q5 2N7002_SOT23 @ S JXDP @ XDP Connector XDP_PREQ# XDP_PRDY# XDP_BPM#0 XDP_BPM#1 Buffered Reset to CPU XDP_BPM#2 XDP_BPM#3 +3VS <18,32> PBTN_OUT# <10> CFG0 <18,32,43> VGATE <17> CLK_CPU_ITP <17> CLK_CPU_ITP# +1.05VS_VCCP 1 0.1U_0402_16V4Z C84 +1.05VS_VCCP PLT_RST# <20,27,28,29,30,32,33> H_PWRGOOD PBTN_OUT# CFG0 VGATE PLT_RST# U3 OE# IN A @ XDP_CPU_HOOK6 2 1K_0402_5% XDP_DBRESET# OUT 4 GND BUFO_CPU_RST# C8 0.1U_0402_10V6K @ R155 43_0402_1% 1 2 BUF_CPU_RST# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS 1 2 XDP_TCK 1 51_0402_5% XDP_TDI_R R29 2 1 51_0402_5% XDP_TDO R30 2 1 51_0402_5% XDP_TCK_R R31 2 1 51_0402_5% XDP_TRST#_R R32 2 1 51_0402_5% B 1A 2 C3 10U_0805_10V6K JFAN 2 U1 1 2 3 4 +FAN1 <32> EN_DFAN1 10mil 1 2 EN VIN VOUT VSET +FAN1 1 GND GND GND GND 8 7 6 5 1 1 2 3 C4 1000P_0402_50V7K @ 4 5 1 2 3 GND GND ACES_85204-0300N APL5607KI-TRG_SO8 C1 10U_0805_10V6K R3 10K_0402_5% 1 +3VS 2 FAN_SPEED1 <32> 1 27 28 R209 0_0402_5% @ 74AHC1G125GW_SOT353-5 2 2 C6 0.01U_0402_25V7K @ MOLEX 52435-2671 2 3 R69 75_0402_5% 5 2 VCC 2 1 R40 2 2 2 2 1K_0402_5%XDP_CPU_HOOK0 0_0402_5% XDP_CPU_HOOK1 1K_0402_5%XDP_CPU_HOOK2 0_0402_5% XDP_CPU_HOOK3 CLK_CPU_ITP CLK_CPU_ITP# 1 1 1 1 1 1 @ @ @ @ 1 2 PLT_RST# R35 R152 R37 R451 R28 FAN Control Circuit +5VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 XDP_TMS_R Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_JTAG/XDP/FAN Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 5 of 45 A 5 4 3 2 1 +1.05VS_VCCP B DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 <18> <18> <18> <18> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <18> <18> <18> <18> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <18> <18> <18> <18> <18> <18> <18> <18> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <18> <18> <18> <18> <18> <18> <18> <18> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 B27 B25 A25 B24 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] <18> FDI_FSYNC0 <18> FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 J18 J17 <18> FDI_INT FDI_INT H20 <18> FDI_LSYNC0 <18> FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# +1.05VS_VCCP R9 1 2 24.9_0402_1% +1.05VS_VCCP R33 2 1 10K_0402_5% EDP_COMP Reserve R33 for HW Review demand eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm FDI_INT C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] Sandy Bridge_rPGA_Rev0p61 PCI EXPRESS* - GRAPHICS <18> <18> <18> <18> DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 Intel(R) FDI DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 eDP C <18> <18> <18> <18> DMI D PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_COMP 2 R34 24.9_0402_1% JCPUA 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 m ohm (12 mils) D J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] C M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] B @ A A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_DMI/PEG/FDI Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 1 6 of 45 5 4 3 2 JCPUC <11> DDR_A_D[0..63] 1 JCPUD C B <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_WE# DDR_A_CAS# DDR_A_RAS# DDR_A_WE# <11> DDR_A_CAS# <11> DDR_A_RAS# <11> DDR_A_WE# SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 SA_CLK[2] SA_CLK#[2] SA_CKE[2] AB4 AA4 W9 SA_CLK[3] SA_CLK#[3] SA_CKE[3] AB3 AA3 W10 SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] AK3 AL3 AG1 AH1 DDRA_SCS0# DDRA_SCS1# SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] AH3 AG3 AG2 AH2 DDRA_ODT0 DDRA_ODT1 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] DDRA_CLK0 <11> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRA_CLK1 <11> DDRA_CLK1# <11> DDRA_CKE1 <11> DDRA_SCS0# <11> DDRA_SCS1# <11> DDRA_ODT0 <11> DDRA_ODT1 <11> DDR_A_DQS#[0..7] DDR_A_DQS#0 C4 G6 DDR_A_DQS#1 DDR_A_DQS#2 J3 M6 DDR_A_DQS#3 AL6 DDR_A_DQS#4 AM8 DDR_A_DQS#5 AR12 DDR_A_DQS#6 AM15 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS[0..7] <11> <11> DDR_A_MA[0..15] <11> SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Sandy Bridge_rPGA_Rev0p61 <12> DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12> DDR_B_CAS# <12> DDR_B_RAS# <12> DDR_B_WE# DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AA9 AA7 R6 SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_WE# DDR_B_CAS# DDR_B_RAS# DDR_B_WE# @ SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR SYSTEM MEMORY B D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR SYSTEM MEMORY A <12> DDR_B_D[0..63] SB_CLK[0] SB_CLK#[0] SB_CKE[0] AE2 AD2 R9 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 SB_CLK[2] SB_CLK#[2] SB_CKE[2] AB2 AA2 T9 SB_CLK[3] SB_CLK#[3] SB_CKE[3] AA1 AB1 T10 SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] AD3 AE3 AD6 AE6 DDRB_SCS0# DDRB_SCS1# SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] AE4 AD4 AD5 AE5 DDRB_ODT0 DDRB_ODT1 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] Sandy Bridge_rPGA_Rev0p61 DDRB_CLK0 <12> DDRB_CLK0# <12> DDRB_CKE0 <12> DDRB_CLK1 <12> DDRB_CLK1# <12> DDRB_CKE1 <12> D DDRB_SCS0# <12> DDRB_SCS1# <12> DDRB_ODT0 <12> DDRB_ODT1 <12> D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0..7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0..7] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 <12> C <12> DDR_B_MA[0..15] <12> B @ 1 +1.5V R465 1K_0402_5% 2 R466 0_0402_5% 1 2 @ H_DRAMRST# D Q14 DDR3_DRAMRST#_R 1 S 3 2 <5> H_DRAMRST# R467 1K_0402_5% 2 SM_DRAMRST# <11,12> BSS138_NL_SOT23-3 2 G R464 4.99K_0402_1% 1 A 1 A <17> DRAMRST_CNTRL_PCH 1 R463 2 DRAMRST_CNTRL 0_0402_5% 1 Compal Electronics, Inc. Compal Secret Data Security Classification C140 0.047U_0402_25V6K 2010/09/03 Issued Date Deciphered Date 2012/12/31 Title Sandy Bridge_DDR3 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 7 of 45 5 +CPU_CORE 4 POWER JCPUF 94A (Quad Core 45W) 53A (SV 35W) +1.05VS_VCCP PEG AND DDR VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 22U_0805_6.3V6M 1 C146 C144 1 22U_0805_6.3V6M 1 C143 C141 1 22U_0805_6.3V6M 1 C137 C136 1 22U_0805_6.3V6M 1 C135 C134 1 22U_0805_6.3V6M 1 C133 C142 1 2 2 2 2 2 2 2 2 2 2 C147 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 C145 C163 @ 22U_0805_6.3V6M 1 1 C153 C160 @ @ 22U_0805_6.3V6M 1 1 C152 C139 @ @ 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 C138 C132 @ @ 2 2 2 2 2 22U_0805_6.3V6M 2 22U_0805_6.3V6M 2 22U_0805_6.3V6M +CPU_CORE Decoupling: 4X 470U (4m ohm), 16X 22U, 10X 10U 22U_0805_6.3V6M 2 Bottom Socket Cavity +CPU_CORE 2 22U_0805_6.3V6M 10U_0805_10V6K 1 C101 1 C102 10U_0805_10V6K C103 1 C104 1 10U_0805_10V6K C105 1 C106 1 C107 10U_0805_10V6K 1 C108 1 10U_0805_10V6K 1 C109 C110 1 1 C111 330U_D2_2V_Y ESR 9mohm Bottom Socket Cavity x 5 1 1 1 C10 + C11 + C12 + 330U_D2_2V_Y 2 @ 2 2 2 2 10U_0805_10V6K 2 2 10U_0805_10V6K 2 2 2 10U_0805_10V6K 2 10U_0805_10V6K 2 2 10U_0805_10V6K @ 2 10U_0805_10V6K 330U_D2_2V_Y C +1.05VS_VCCP 1 C876 330U_2.5V_M_R17 @ + Co-lay for Cost Down Plan Top Socket Edge 2 +CPU_CORE J23 22U_0805_6.3V6M 1 C151 2 1 C130 2 +1.05VS_VCCP +1.05VS_VCCP 1 1 R70 130_0402_5% 22U_0805_6.3V6M 1 C129 2 22U_0805_6.3V6M 1 C124 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C123 2 1 22U_0805_6.3V6M C122 2 22U_0805_6.3V6M 1 C121 2 1 C125 @ 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M 9/02 Remove C126, C131 by Power Demand R68 75_0402_5% AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT 2 2 SVID Top Socket Cavity VIDALERT# VIDSCLK VIDSOUT 1 R67 1 R63 1 R66 2 2 43_0402_1% 2 0_0402_5% 0_0402_5% VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43> +CPU_CORE B 22U_0805_6.3V6M Pull high resistor on VR side C158 1 C150 2 1 C128 2 22U_0805_6.3V6M 1 C127 2 22U_0805_6.3V6M 1 C120 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C118 2 22U_0805_6.3V6M 1 22U_0805_6.3V6M C119 2 1 C117 2 1 2 22U_0805_6.3V6M +CPU_CORE Bottom Socket Edge 2 Co-Lay with C2, C5, C7, C9 R64 100_0402_1% +CPU_CORE Close to CPU +CPU_CORE 330U_D2_2V_Y 1 470U_D2_2VM_R4.5M R65 1 R52 1 1 2 0_0402_5% 2 0_0402_5% VCCSENSE <43> VSSSENSE <43> + 1 VCC_SENSE VSS_SENSE AJ35 VCCSENSE_R AJ34 VSSSENSE_R VCCIO_SENSE VCCIO_SENSE 2 3 R62 100_0402_1% <42> 1 C890 + 1 + C891 2 3 470U_D2_2VM_R4.5M @ C2 C894 330U_D2_2V_Y 2 3 470U_D2_2VM_R4.5M 2 C5 @ C7 + 2 1 1 + C9 2 + 2 330U_D2_2V_Y 470U_D2_2V_C 2 A R105 100_0402_1% @ 9/02 Add C898 3Pin Bulk Cap by Power Demand 9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand Close to CPU 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 5 + 1 1 R102 0_0402_5% +1.05VS_VCCP Sandy Bridge_rPGA_Rev0p61 1 2 VSS_SENSE_VCCIO B10 A10 2 VCCIO_SENSE VSSIO_SENSE 1 A VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 D C159 SENSE LINES B 1 TOP Socket Cavity x 7 VCCIO40 CORE SUPPLY C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 2 +1.05VS_VCCP Decoupling: 2X 330U (6m ohm), 12X 22U 8.5A D AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 3 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. @ 4 3 2 Title Sandy Bridge_POWER-1 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 8 of 45 5 4 3 2 1 +GFX_CORE ESR 17mohm +GFX_CORE Decoupling: 2X 470U (4m ohm), 12X 22U +GFX_CORE 1 + +GFX_CORE 2 C873 330U_2.5V_M_R17 POWER 2 Bottom Socket Edge R74 Close 100_0402_1% to CPU JCPUG 22U_0805_6.3V6M 2 1 C342 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M Bottom Socket Edge 22U_0805_6.3V6M C343 1 22U_0805_6.3V6M C344 2 C Top Socket Cavity 1 C345 2 1 C346 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C347 2 1 C348 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M Top Socket Edge 22U_0805_6.3V6M C349 @ 1 22U_0805_6.3V6M C350 @ 2 1 2 C351 @ C391 @ 2 22U_0805_6.3V6M +1.8VS 1 1 2 22U_0805_6.3V6M R76 2 1 0_0805_5% 1.2A +1.8VS_VCCPLL 10U_0805_10V6K 1 C185 @+ C186 2 330U_B2_2.5VM_R15M 1 2 C206 1 1 2 2 1U_0402_6.3V6K B6 A6 A2 1 R486 5A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 C148 @ AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 1 1 VCCPLL1 VCCPLL2 VCCPLL3 C230 1U_0402_6.3V6K Sandy Bridge_rPGA_Rev0p61 +1.5VS 2 @ R122 +V_SM_VREF 3 1 2 2 2 Q2 @ AP2302GN-HF_SOT23-3 2 1 RUN_ON_CPU1.5VS3 2 +1.5V_CPU 1 +V_SM_VREF_CNT 100_0402_1% R252 100_0402_1% 8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU +1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U +1.5V_CPU +1.5V_CPU 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 1 ESR 6mohm C114 1 1 C115 2 C116 2 1 1 C149 2 C154 2 1 C155 2 1 + 2 2 ESR 17mohm 1 C180 @ 330U_D2_2VM_R6M C875 330U_2.5V_M_R17 + 2 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K C Co-lay for Cost Down Plan +VCCSA Decoupling: 1X 330U (6m ohm), 3X 10U VCCSA_VID0 +VCCSA Bottom Socket Cavity VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U B AL1 1 JUMP_43X118 2 C341 SM_VREF PJ32 1 R111 0_0402_5% 2 1 0.1U_0402_16V4Z 2 1 D VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 M27 M26 L26 J26 J25 J24 H26 H25 10U_0805_10V6K VCCSA_VID1 +VCCSA Co-lay for Cost Down Plan 6A +VCCSA 10U_0805_10V6K 0 0 0.90 V 0 1 0.80 V 1 0 0.75 V 1 1 0.65 V For Sandy Bridge ESR 17mohm C100 1 C447 1 C476 1 C477 + 2 2 2 @ 2 2 10U_0805_10V6K 2 VCCSA_SENSE 0_0402_5% 1 1 R253 1 1 + C485 @ 330U_D2_2VM_R6M C877 2 330U_2.5V_M_R17 10U_0805_10V6K Bottom Socket Edge VCCSA_SENSE H23 VCCSA_SENSE FC_C22 VCCSA_VID1 VCCSA_SENSE <41> 1 R95 0_0402_5% @ VCCSA_VID0 C22 VCCSA_VID0 C24 B 2 VCCSAP_VID1 <41> 2 C338 R75 100_0402_1% +V_SM_VREF should have 20 mil trace width 100K_0402_5% 2 1 VCC_AXG_SENSE <43> VSS_AXG_SENSE <43> R114 R119 @ @ 10K_0402_5% 1 10K_0402_5% +1.5V_CPU 1 C271 VCC_AXG_SENSE_R VSS_AXG_SENSE_R AK35 AK34 2 1 33A VAXG_SENSE VSSAXG_SENSE 2 C267 22U_0805_6.3V6M VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 VREF 330U_D2_2VM_R6M 22U_0805_6.3V6M 2 Bottom Socket Cavity 2 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 DDR3 -1.5V RAILS 1 ESR 6mohm SA RAIL C266 @ 2 22U_0805_6.3V6M + MISC @ 1 C113 GRAPHICS C112 + 1.8V RAIL 330U_D2_2VM_R6M 1 D SENSE LINES 1 Co-lay for Cost Down Plan +1.5V PJ30 +1.5V_CPU 2 +1.5V 2 @ 1 1 JUMP_43X118 08/18 Reserve R119 to follow CRB 1.0 Vgs=10V,Id=14.5A,Rds=6mohm Q33 2 0.1U_0402_16V4Z C210 1 2 0.1U_0402_16V4Z R449 470_0805_5% C179 10U_0805_10V4K C472 0.1U_0402_25V6 4 5 2N7002DW-T/R7_SOT363-6 D D D D 8 7 6 5 FDS6676AS_SO8 RUN_ON_CPU1.5VS3 2 Q46B SUSP S S S G 1 3 1 C211 1 1 1 2 R420 820K_0402_5% 1 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 SUSP SUSP <5,35,42> 2N7002DW-T/R7_SOT363-6 A Compal Electronics, Inc. Compal Secret Data 2010/09/03 +VSB Q46A 2 A Security Classification R455 1 2 220K_0402_5% 6 2 0.1U_0402_16V4Z 1 2 3 4 2 C212 1 2 0.1U_0402_16V4Z 2 C213 1 2 Title Sandy Bridge_POWER-2 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 9 of 45 5 4 3 2 1 CFG Straps for Processor B @ <5> <5> <5> <5> CFG12 CFG13 CFG14 CFG15 T26 PAD T27 PAD RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD33 RSVD34 RSVD35 CFG2 1 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 R254 1K_0402_1% @ AT26 AM33 AJ27 2 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 <5> CFG0 T5 PAD T6 PAD T7 PAD T11 PAD T12 PAD T15 PAD T18 PAD T16 PAD T19 PAD T21 PAD T20 PAD D PEG Static Lane Reversal - CFG2 is for the 16x RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 CFG2 * 1: Normal Operation; Lane # socket pin map definition definition matches 0:Lane Reversed B4 D1 RSVD6 RSVD7 SB_DIMM_VREFDQ R115 1K_0402_1% R116 1K_0402_1% F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18 A19 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 VCCIO_SEL J15 R255 1K_0402_1% @ RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 B34 A33 A34 B35 C35 Embedded Display Port Presence Strap * AJ32 AK32 CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port C 0 : Enabled; An external Display Port device is connected to the Embedded Display Port AH27 T28 PAD CFG6 RSVD54 RSVD55 AN35 AM35 CLK_RES_ITP <17> CLK_RES_ITP# <17> CFG5 1 RSVD5 SA_DIMM_VREFDQ CPU_RSVD6 CPU_RSVD7 CFG4 1 AJ26 RSVD1 RSVD2 RSVD3 RSVD4 AR35 AT34 AT33 AP35 AR34 R257 1K_0402_1% @ RSVD56 RSVD57 RSVD58 AT2 AT1 AR1 R256 1K_0402_1% @ 2 AJ31 AH31 AJ33 AH33 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 2 PAD PAD PAD PAD 1 T22 T24 T25 T23 2 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 RESERVED VSS VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 1 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 (CFG[17:0] internal pull high to VCCIO) L7 AG7 AE7 AK2 W8 RSVD27 KEY B1 PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled Sandy Bridge_rPGA_Rev0p61 *10: x8, x8 - Device 1 function 1 enabled ; function 2 @ CFG[6:5] Sandy Bridge_rPGA_Rev0p61 B disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled @ CFG7 1 Sandy Bridge_rPGA_Rev0p61 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 2 C VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 JCPUE 1 D VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPUI AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 2 JCPUH AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 2 R258 1K_0402_1% @ PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_GND/RSVD/CFG Size Document Number Custom Rev 0.2 PHQAA LA-6831P M/B Date: Thursday, October 07, 2010 Sheet 1 10 of 45 4 +1.5V JDDRL Close to JDDRL.1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDRA_CKE0 <7> DDRA_CKE0 C DDR_A_BS2 <7> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDRA_CLK0 DDRA_CLK0# <7> DDRA_CLK0 <7> DDRA_CLK0# DDR_A_MA10 DDR_A_BS0 <7> DDR_A_BS0 DDR_A_WE# DDR_A_CAS# <7> DDR_A_WE# <7> DDR_A_CAS# DDR_A_MA13 DDRA_SCS1# <7> DDRA_SCS1# DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 B DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 C181 2 1 2 5 1 1 C182 +0.75VS R91 10K_0402_5% 2 +3VS 2.2U_0603_6.3V4Z A 0.1U_0402_16V4Z DDR_A_D58 DDR_A_D59 R90 1 2 10K_0402_5% 205 207 GND1 GND2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_D6 DDR_A_D7 <7> <7> <7> DDR_A_D12 DDR_A_D13 SM_DRAMRST# D SM_DRAMRST# <7,12> +1.5V DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 R79 1K_0402_1% +VREF_DQA_DIMMA +VREF_DQA DDR_A_D22 DDR_A_D23 R81 1K_0402_1% DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDRA_CKE1 DDRA_CKE1 <7> DDR_A_MA15 DDR_A_MA14 C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 DDRA_CLK1# DDR_A_BS1 DDR_A_RAS# DDRA_SCS0# DDRA_ODT0 DDRA_ODT1 DDRA_CLK1 <7> DDRA_CLK1# <7> +1.5V DDR_A_BS1 <7> DDR_A_RAS# <7> DDRA_SCS0# <7> DDRA_ODT0 <7> DDRA_ODT1 R80 1K_0402_1% <7> +VREF_CAA +VREF_CAA_DIMMA DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 R82 1K_0402_1% C161 1 2 1 C162 0.1U_0402_16V4Z DDR_A_D40 DDR_A_D41 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD W E# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT <7> DDR_A_DQS#[0..7] 2.2U_0603_6.3V4Z DDR_A_D34 DDR_A_D35 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_A_DQS[0..7] 1 DDR_A_DQS#1 DDR_A_DQS1 DDR3 SO-DIMM A Reverse Type 2 DDR_A_D8 DDR_A_D9 DDR_A_D4 DDR_A_D5 1 DDR_A_D2 DDR_A_D3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 2 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS B 2 Layout Note: Place near JDDRL close to JDDRL.126 +1.5V Layout Note: Place these 4 Caps near Command and Control signals of DIMMA Layout Note: Place near JDDRL1.203 and 204 Change C218 to OSCON at DVT +1.5V DDR_A_D52 DDR_A_D53 C218 1 DDR_A_D54 DDR_A_D55 + 2 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z D C157 DDR_A_D0 DDR_A_D1 1 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 1 C156 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 +VREF_DQA 3 1 +1.5V 2 5 +0.75VS 2 390U_2.5V_M_R10 C165 1 2 10U_0603_6.3V6M C169 2 1 1U_0402_6.3V6K C172 2 1 1U_0402_6.3V6K 2 10U_0603_6.3V6M C175 2 1 1U_0402_6.3V6K C176 1 2 10U_0603_6.3V6M C177 2 1 1U_0402_6.3V6K C178 1 2 10U_0603_6.3V6M C166 1 2 10U_0603_6.3V6M C168 1 2 10U_0603_6.3V6M C171 1 2 10U_0603_6.3V6M C174 1 C164 1 2 0.1U_0402_16V4Z C167 1 2 0.1U_0402_16V4Z C170 1 DDR_A_D60 DDR_A_D61 C173 1 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z A PM_SMBDATA PM_SMBCLK PM_SMBDATA <12,17,27> PM_SMBCLK <12,17,27> +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date FOX_AS0A626-U2SN-7F_204P @ Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title DDRIII-SODIMM0 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 11 of 45 A B +1.5V C D E +1.5V JDDRH DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDRB_CKE0 <7> DDRB_CKE0 2 DDR_B_BS2 <7> DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDRB_CLK0 DDRB_CLK0# <7> DDRB_CLK0 <7> DDRB_CLK0# DDR_B_MA10 DDR_B_BS0 <7> DDR_B_BS0 DDR_B_WE# DDR_B_CAS# <7> DDR_B_WE# <7> DDR_B_CAS# DDR_B_MA13 DDRB_SCS1# <7> DDRB_SCS1# DDR_B_D37 DDR_B_D36 DDR_B_DQS#4 DDR_B_DQS4 3 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 R98 1 2 10K_0402_5% 4 +3VS 2.2U_0603_6.3V4Z 1 C207 @ 2 1 1 R99 2 10K_0402_5% C208 2 @ 0.1U_0402_16V4Z +0.75VS 205 207 GND1 GND2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 SM_DRAMRST# <7> <7> <7> DDR_B_MA[0..15] 1 <7> SM_DRAMRST# <7,11> DDR_B_D14 DDR_B_D15 +1.5V DDR_B_D20 DDR_B_D21 R83 1K_0402_1% DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 +VREF_DQB_DIMMB +VREF_DQB DDR_B_DQS#3 DDR_B_DQS3 R84 1K_0402_1% DDR_B_D30 DDR_B_D31 DDRB_CKE1 DDRB_CKE1 <7> DDR_B_MA15 DDR_B_MA14 2 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 DDRB_CLK1# DDR_B_BS1 DDR_B_RAS# DDRB_SCS0# DDRB_ODT0 DDRB_ODT1 DDRB_CLK1 <7> DDRB_CLK1# <7> +1.5V DDR_B_BS1 <7> DDR_B_RAS# <7> DDRB_SCS0# <7> DDRB_ODT0 <7> R86 1K_0402_1% DDRB_ODT1 <7> +VREF_CAB +VREF_CAB_DIMMB DDR_B_D32 DDR_B_D33 R94 1K_0402_1% C187 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 1 2 C188 1 3 2 Layout Note: Place near JDDRH Layout Note: Place these 4 Caps near Command and Control signals of DIMMB Layout Note: Place near JDDRH.203 and 204 Close to JDDRH.126 +1.5V +1.5V @ DDR_B_D52 DDR_B_D53 C189 1 DDR_B_D50 DDR_B_D51 +0.75VS 2 330U_B2_2.5VM_R15M C191 1 2 10U_0603_6.3V6M C195 2 1 1U_0402_6.3V6K C198 2 1 1U_0402_6.3V6K 2 10U_0603_6.3V6M C201 2 1 1U_0402_6.3V6K C202 1 2 10U_0603_6.3V6M C203 2 1 1U_0402_6.3V6K C204 1 2 10U_0603_6.3V6M C192 1 2 10U_0603_6.3V6M C194 1 2 10U_0603_6.3V6M C197 1 2 10U_0603_6.3V6M C200 1 C190 1 2 0.1U_0402_16V4Z C193 1 2 0.1U_0402_16V4Z C196 1 DDR_B_D60 DDR_B_D61 C199 1 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4 PM_SMBDATA PM_SMBCLK PM_SMBDATA <11,17,27> PM_SMBCLK <11,17,27> +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date FOX_AS0A626-UASN-7F_204P @ A DDR_B_D[0..63] 0.1U_0402_16V4Z DDR_B_D40 DDR_B_D41 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD W E# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DDR_B_D12 DDR_B_D13 2.2U_0603_6.3V4Z DDR_B_D34 DDR_B_D35 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_B_DQS[0..7] 1 Close to JDDRH.1 DDR_B_DQS#[0..7] 2 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D6 DDR_B_D7 1 DDR_B_D8 DDR_B_D9 DDR_B_DQS#0 DDR_B_DQS0 2 DDR_B_D2 DDR_B_D3 2 Reverse Type DDR3 SO-DIMM B DDR_B_D4 DDR_B_D5 + 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 C184 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 1 1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 C183 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 +VREF_DQB Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C D Title DDRIII-SODIMM1 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet E 12 of 45 A B C D E F +LCD_VDD USB20_P11_R 1 R108 100K_0402_5% +3VS 2 4 R107 150_0603_5% 2 <20> USB20_N11 +3VS 6 <20> USB20_P11 1 CAM@ 2 R78 0_0402_5% @ L55 1 1 2 2 H 1 Reserve for EMI request G Q1A 2N7002DW-T/R7_SOT363-6 <32> INVT_PWM C229 0.01U_0402_25V7K LCD_EDID_DATA @ 2 0_0402_5% 2 0_0402_5% 5 LED_PWM 4 1 R357 1 R358 UMA_ENVDD <19> UMA_ENVDD LED_PWM 8/20 Swap USB20_P11 and USB20_N11 for layout request +LCD_VDD W=80mils 2 Q1B 2N7002DW-T/R7_SOT363-6 1 C233 0.1U_0402_16V4Z 2 R112 100K_0402_5% 1 Close to LVDS Connector 1 Q17 AO3413_SOT23 2 <19> LCD_EDID_DATA <19> PCH_PWM 3 LCD_EDID_CLK <19> LCD_EDID_CLK W=80mils 2 1 2 R109 2 LCDPWR_GATE 1 47K_0402_5% 1 1 1 CAM@ 2 R96 0_0402_5% C228 0.1U_0402_16V7K 2 3 USB20_N11_R 1 3 G 3 D 4 WCM-2012-900T_0805 S 1 LCD/PANEL BD. Conn. +3VS 2 <19> LCD_TXOUT0+ <19> LCD_TXOUT0<19> LCD_TXOUT1+ <19> LCD_TXOUT1<19> LCD_TXOUT2+ <19> LCD_TXOUT2<19> LCD_TXCLK+ <19> LCD_TXCLK- CAM@ W=20mils 0.1U_0402_16V4Z 1 CAM@ 2 +3VS_LVDS_CAM 1 2 R388 0_0603_5% C225 JLVDS @ LCD_EDID_CLK 1 1 2 2 USB20_P11_R LCD_EDID_DATA 3 3 4 4 USB20_N11_R INT_MIC_CLK 5 5 6 6 INT_MIC_DATA 7 7 8 8 LED_PWM 9 9 10 10 BKOFF#_R 11 11 2 12 12 R103 13 13 14 14 15 15 16 1 16 R113 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 +LCD_INV 28 28 29 29 30 30 31 32 D84 @ 2 1 3 PACDN042Y3R_SOT23-3 2 INT_MIC_CLK <31> INT_MIC_DATA <31> 1 33_0402_5% 2 10K_0402_5% BKOFF# <32> +3VS 3A +LCD_VDD 1 2 1 C226 0.1U_0402_16V4Z 2 C227 4.7U_0805_10V4Z GND1 GND2 For EMI 1 @ C231 680P_0402_50V7K 2 1 2 C232 0.1U_0402_16V4Z ACES_87242-3001-09 +LCD_INV 1 C234 68P_0402_50V8J 2 3 B+ L2 2 1 FBMA-L11-201209-221LMA30T_0805 1 C235 0.1U_0402_25V6 2 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Title LVDS/eDP Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 G Sheet 13 H of 45 A B C D E D4 @ D5 1 @ 1 1 CRT CONNECTOR D3 @ +3VS If=1A +5VS +CRT_VCC_R +CRT_VCC D6 F1 2 3 2 DAN217_SC59 3 DAN217_SC59 2 3 2 DAN217_SC59 1 1 RB491D_SOT23-3 3 1 <19> UMA_CRT_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L <19> UMA_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L <19> UMA_CRT_B L5 1 2 NBQ100505T-800Y_0402 40 mils 2 1 1.1A_6V_MINISMDC110F-2 C237 0.1U_0402_16V4Z 2 @ CRT_B_L 2 2 C241 2 1 C242 2 1 C243 2 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_R_L 2.2P_0402_50V8C 2 C240 1 2.2P_0402_50V8C C239 1 2.2P_0402_50V8C C238 1 2.2P_0402_50V8C 2.2P_0402_50V8C 2 1 150_0402_1% 2 1 150_0402_1% 2 1 150_0402_1% 1 2.2P_0402_50V8C JCRT R138 R139 R140 1 CRT_DDC_DAT CRT_G_L HSYNC CRT_B_L +CRT_VCC VSYNC CRT_DDC_CLK 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 @ G G 16 17 ALLTO_C10532-11505-L_15P-T 2 2 +CRT_VCC 2 0.1U_0402_16V4Z 2 R141 1 10K_0402_5% 4 D_CRT_HSYNC 1 L6 2 10_0402_5% D_CRT_VSYNC 1 L7 2 10_0402_5% +CRT_VCC HSYNC 5 1 3 2 A 4 Y G <19> UMA_CRT_VSYNC U7 SN74AHCT1G125GW _SOT353-5 3 C245 @ VSYNC 1 2 1 C246 @ 2 10P_0402_50V8J U6 SN74AHCT1G125GW _SOT353-5 10P_0402_50V8J Y G A P OE# 2 <19> UMA_CRT_HSYNC P OE# 5 1 1 C244 3 3 +CRT_VCC 2 2 +3VS 5 Q205B 4 <19> UMA_CRT_DATA 1 C282 33P_0402_50V8K 2 @ 1 1 2 Q205A 1 <19> UMA_CRT_CLK R159 4.7K_0402_5% 1 R153 4.7K_0402_5% CRT_DDC_CLK 6 2N7002DW -T/R7_SOT363-6 CRT_DDC_DAT 3 2N7002DW -T/R7_SOT363-6 C285 33P_0402_50V8K 2 @ C284 470P_0402_50V8J @ 1 1 2 C283 470P_0402_50V8J 2 @ 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title CRT Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet E 14 of 45 4 P1_5/RXD0/CNTR01/INT11# CEC_INT# CEC_TEST 13 CEC_FSHUPD1 CEC@ 2 R170 4.7K_0402_5% 1 1 1 2 2 CEC@ 1CEC_XIN R174 47K_0402_5% XOUT/P4_7 P1_1/KI1#/AN9/CMP0_1 17 8 MODE P1_0/KI0#/AN8/CMP0_0 18 HDMI_DATA 9 P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 19 HDMI_HPD_R P3_4/SCS#/SDA/CMP1_1 20 7 1 3 3 HDMI_CLK R165 100K_0402_5% CEC@ 2 CEC@ 1 R176 4.7K_0402_5% C262 1 0.1U_0402_16V4Z CEC@ HDMI_CECIN HDMI_CECOUT 10 P1_7/CNTR00/INT10# D HDMI_DATA 3 HDMI_SCLK 1 HDMI_SDATA 1 Q48 BSH111_SOT23-3 CEC@ EC_SMB_DA1 <32,37> 2 2 3 S S Q50 2N7002_SOT23-3 CEC@ Q47 BSH111_SOT23-3 CEC@ D VCC/AVCC XIN/P4_6 R164 4.7K_0402_5% CEC@ D 16 6 15 P1_2/KI2#/AN10/CMP0_2 +3VL S P4_2/VREF VSS/AVSS D 2 G 1 R166 4.7K_0402_5% CEC@ +3VL S 1 R163 2 27K_0402_5% CEC@ +3VL CEC_FSHUPD (Pin13) Low= Force to update flash. 14 P1_3/KI3#/AN11/TZOUT CEC@ 1 2 C848 1U_0402_6.3V6K 1 2 C263 0.1U_0402_16V4Z CEC@ HDMI_CLK 5 HDMI_CEC P1_4/TXD0 G 2 G RESET# CEC_INT# <32> +3VL 1 CEC@ 2 R168 4.7K_0402_5% 2 P3_7/CNTR0#/SSO/TXD1 11 12 2 P1_6/CLK0/SSI01 2 1 P3_5/SSCK/SCL/CMP1_2 G D 3 2 CEC@ 1CEC_XOUT 4 R171 47K_0402_5% R581 27K_0402_5% CEC@ D HDMI_CECOUT 2 CEC@ 1CEC_RST# R169 4.7K_0402_5% D9 CH751H-40PT_SOD323-2 CEC@ 2 R162 10K_0402_5% CEC@ Q49 2N7002_SOT23-3 CEC@ 2 1 1 +3VL HDMI_CECIN U16 Address: 0011010X <32,37> EC_SMB_CK1 +3VL 1 1 +3VL 2 2 HDMI CEC Controller 3 2 5 R5F211A4C33SP-W4_LSSOP20 CEC@ +3VS +HDMI_5V_OUT +5VL 2 3 2 Y 4 74AHCT1G125GW_SOT353-5 HDMI@ 2 1 C265 0.1U_0402_16V4Z HDMI@ C 1 G 3 U9 HDMI_SCLK D S G Q18 BSH111_SOT23-3 HDMI@ 1 3 <19> UMA_HDMI_DATA 1 HDMI_HPD_C R186 100K_0402_5% HDMI@ HDMI_HPD_R 2 G <19> UMA_HDMI_CLK A R185 2.2K_0402_5% HDMI@ 2 2 2 R184 2.2K_0402_5% HDMI@ 1 5 P 1 1 1 C 2 OE# C264 0.1U_0402_16V4Z HDMI@ HDMI@ R145 HDMI_HPD_U 1 2 1K_0402_5% HDMI_SDATA D S +3VL Q19 BSH111_SOT23-3 HDMI@ HDMI@ 2 1 R570 100K_0402_5% HDMI@ 2 1 R571 2.2K_0402_5% +3VS D55 HDMI_HPD_R 1 2 HDMI_HPD <19,21> CH751H-40PT_SOD323-2 HDMI@ 4 <19> UMA_HDMI_TXC+ B <19> UMA_HDMI_TXC<19> UMA_HDMI_TX0+ <19> UMA_HDMI_TX0<19> UMA_HDMI_TX1+ <19> UMA_HDMI_TX1<19> UMA_HDMI_TX2+ <19> UMA_HDMI_TX2- CV308 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXC+ CV304 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXC- CV306 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXD0+ CV302 1 2 0.1U_0402_16V7K HDMI@ CV303 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXC+ UMA_DVI_TXD0- 1 2 0.1U_0402_16V7K HDMI@ CV307 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXD0+ 1 R175 L9 UMA_DVI_TXD1+ CV305 1 2 0.1U_0402_16V7K HDMI@ UMA_DVI_TXD1UMA_DVI_TXD2+ 4 UMA_DVI_TXD2- 3 @ 1 2 0_0402_5% HDMI@ 2 2 4 3 UMA_DVI_TXD1- @ 1 R182 L10 1 1 2 0_0402_5% HDMI@ 2 2 4 4 3 UMA_DVI_TXD2+ @ 1 R187 L11 1 A 4 1 4 2 0_0402_5% HDMI@ 2 2 3 HDMI_R_CK+ HDMI_R_D0+ HDMI@ D53 +5VS D54 +5VL 2 1 D S Q24 2N7002_SOT23-3 HDMI@ HDMI Connector JHDMI HDMI_HPD_C 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +HDMI_5V_OUT HDMI_SDATA HDMI_SCLK HDMI_CEC HDMI_R_CKHDMI_R_D1+ HDMI_R_CK+ HDMI_R_D0HDMI_R_D2+ HDMI_R_D0+ HDMI_R_D1HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+ 3 OCE2012120YZF @ 1 2 R188 0_0402_5% B PMEG2010AEH_SOD123 CEC@ 08/18 Change R195, R197, R198, R202, R201, R203, R205, R206 to SD028680080 for UMA request HDMI_R_D1- @ HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 A TYCO_1939864-1_19P HDMI_R_D2- 08/13 Change L8, L9 L10, L11 from SM070001600 to SM070001310 by EMI demand Issued Date Compal Electronics, Inc. Compal Secret Data 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 F2 +HDMI_5V_OUT_F 2 1 +HDMI_5V_OUT 1.1A_6V_MINISMDC110F-21 HDMI@ C259 HDMI@ 0.1U_0402_16V4Z 2 HDMI_R_D0- Security Classification 5 1 PMEG2010AEH_SOD123 2 G +5VS 2 3 OCE2012120YZF @ 1 2 R183 0_0402_5% UMA_DVI_TXD1+ HDMI_R_CK- 3 OCE2012120YZF @ 1 2 R180 0_0402_5% UMA_DVI_TXD0- UMA_DVI_TXD2- 4 HDMI_R_CK+ 3 OCE2012120YZF @ 1 2 R173 0_0402_5% 1 CV301 1 1 HDMI@ 2 R195 680_0402_1% 1 HDMI@ 2 R197 680_0402_1% HDMI_R_D1- 1 HDMI@ 2 R198 680_0402_1% HDMI_R_D1+ 1 HDMI@ 2 R202 680_0402_1% HDMI_R_D0+ 1 HDMI@ 2 R201 680_0402_1% HDMI_R_D0- 1 HDMI@ 2 R203 680_0402_1% HDMI_R_D2- 1 HDMI@ 2 R205 680_0402_1% HDMI_R_D2+ 1 HDMI@ 2 R206 680_0402_1% HDMI_R_CK- 1 1 2 0_0402_5% HDMI@ 2 2 3 @ 1 R157 L8 UMA_DVI_TXC- 3 2 Title HDMI Conn./CEC Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 15 of 45 5 4 3 2 1 U2A NC OSC 4 R286 1 <31> AZ_BITCLK_HD Integrated SUS 1.05V VRM Enable High - Enable Internal VRs PCH_INTVRMEN (must be always pulled high) 2 33_0402_5% <31> PCH_SPKR R142 1 <31> AZ_RST_HD# +RTCVCC 2 33_0402_5% R118 1 D20 PCH_SRTCRST# G22 SM_INTRUDER# K22 PCH_INTVRMEN C17 RTCX1 RTCX2 AZ_BITCLK N34 AZ_SYNC L34 INTRUDER# PCH_SPKR T10 SPKR AZ_RST# K34 HDA_RST# E34 A34 HDA_SDIN3 A36 HDA_SDO 2 R273 @ 1 1K_0402_5% R289 1 <31> AZ_SDOUT_HD 2 33_0402_5% AZ_SDOUT R580 1 <32> PWRME_CTRL# CR_CPPE# 2 10K_0402_5% 2 0_0402_5% C36 CR_CPPE# <29> CR_CPPE# V5 SERIRQ SERIRQ +3VALW 1 R560 FELICA_PWR HDA_SDIN0 HDA_SDIN2 +3VALW LPC_FRAME# E36 K36 HDA_SYNC HDA_SDIN1 PCH_SPK High = Enabled (No Reboot) Low = Disabled (Default) D36 LDRQ0# LDRQ1# / GPIO23 HDA_BCLK C34 PCH_SPKR FWH4 / LFRAME# INTVRMEN PCH_INTVRMEN 2 1K_0402_5% LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SRTCRST# G34 @ C38 A38 B37 C37 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 RTCRST# SM_INTRUDER# +3VS 1 R276 PCH_RTCRST# AZ_SDIN0_HD <31> AZ_SDIN0_HD 2 1M_0402_5% 2 330K_0402_5% C20 1 D R117 1 A20 PCH_RTCX2 HDA_DOCK_EN# / GPIO33 N32 J3 T37 PAD PCH_JTAG_TMS H7 T38 PAD PCH_JTAG_TDI K5 T39 PAD PCH_JTAG_TDO H1 JTAG_TDI AB8 AB10 AF3 AF1 SATAICOMPI JTAG_TDO SATA3RCOMPO HDA_SYNC SATA3COMPI 1 1K_0402_5% PCH_SPIDI PCH_SPICLK PCH_SPICS# PCH_SPIDO +3VS R572 R573 R574 R575 C494 0.1U_0402_16V4Z 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% R569 2@ 1 0_0603_5% DI CLK CS# DO SPI_MOSI 8 VCC U3 3 W 7 HOLD CS# 1 CLK 6 DI 5 SATA3RBIAS SATALED# SATA0GP / GPIO21 SPI_MISO for EMI 4 VSS <26> SERIRQ SERIRQ <32,33> SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_PRX_C_DTX_N0 <25> SATA_PRX_C_DTX_P0 <25> SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25> SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 SATA_PRX_C_DTX_N2 <25> SATA_PRX_C_DTX_P2 <25> SATA_PTX_DRX_N2 <25> SATA_PTX_DRX_P2 <25> 2 R136 1 10K_0402_5% +3VS HDD ODD SATA_LED# R336 2 1 10K_0402_5% CR_WAKE# R334 2 1 10K_0402_5% PCH_GPIO19 R335 1 2 10K_0402_5% +RTCBATT SATA1GP / GPIO19 COUGARPOINT_FCBGA989~D Y7 Y5 AD3 AD1 D13 BAS40-04_SOT23-3 +RTCVCC Y3 Y1 AB3 AB1 C486 +3VL 1 0.1U_0402_16V4Z 2 Y11 Y10 SATAICOMP 1 R279 2 37.4_0402_1% +1.05VS_VCC_SATA SATA3_COMP 1 R280 2 49.9_0402_1% +1.05VS_SATA3 1 R281 2 750_0402_1% AB12 C AB13 AH1 RBIAS_SATA3 P3 SATA_LED# V14 CR_WAKE# P1 PCH_GPIO19 SATA_LED# <34> CR_WAKE# <29> PCH_GPIO19 <20> BOOT BIOS Strap Bit 0 Q65R3@ CLK S C D DO 2 Q 1 C86 10P_0402_50V8J 2 Socket: SP07000F500/SP07000H900 Please close to U2 PCH 8/30 Change U13 from SA000021A00 to SA00003IN00 due to EOL of SA000021A00 +5VALW B +5VALW 8/ 12 Change R572, R573, R574, R575, R569 from @ to mount +3V_SPI 2 GND DI CLK CS# DO R443 SPI@ 100K_0402_5% 7 R442 SPI@ C456 SN74CBTLV3125PWR_TSSOP14 SPI@ SPI@ 0.1U_0402_16V4Z 1 1 2 1 PCH_JTAG_TDI 2 2 PCH_JTAG_TDO 1 PCH_JTAG_TMS R301 100_0402_1% R295 100_0402_1% 1 3 1 100K_0402_5% A 8/12 Add R442, R443 8/30 Change R442, R443 from 10k to 100k Issued Date 3 PCH_JTAG_TCK 2 51_0402_1% 1 R355 Compal Electronics, Inc. Compal Secret Data 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 R278 200_0402_5% R330 200_0402_5% R306 100_0402_1% Security Classification 5 R363 200_0402_5% +5VALW Please close to U2 PCH,and between U2 & U13 8/30 Change U53 PIN 9 from KSI4 to KSI3 +3VALW +3V_SPI C482 SPI@ 0.1U_0402_16V4Z 8/30 Change U56 Pin3 from KSO6 to +5VALW 8/12 Change U51, U53 P/N form SA00000BJ20 to SA00000CA00 +3VALW 1 3 6 8 11 2 +3VALW 2 1 Q37 SPI@ AO3416_SOT23-3 1 4 7 2 1B 2B 3B 4B RB715FGT106_UMD3 R226 SPI@ 100K_0402_5% 2 VCC O SPI@ LM393DG_SO8 S 2 G 2 14 - SPI@ R432 SPI@ 10K_0402_5% U56B + 1 1 1A 2A 3A 4A 1 8 SUSP# 1OE# 2OE# 3OE# 4OE# 2 5 9 12 1 2 2 KSI6 KSI5 KSI3 KSI7 1 P 4 8 5 D 3 +5VALW 7 6 <32,33,34> SPIDI <32,33> SPICLK <32,33> SPICS# <32,33> SPIDO +3VALW C483 SPI@ 0.1U_0402_16V4Z D43 <27,32,35,40,42> 1 4 10 13 2 +5VALW U52 <32,34> EC_ON 1 8/30 Add R227 100k ohm C455 SN74CBTLV3125PWR_TSSOP14 SPI@ SPI@ 0.1U_0402_16V4Z EC_ON 1 SPI@ LM393DG_SO8 U56A 2 GND DI CLK CS# DO O P 2 VCC 3 6 8 11 - G 1 1B 2B 3B 4B + 2 14 +3VS 1A 2A 3A 4A 2 R418 SPI@ 10K_0402_5% 2 1 SPI@ 0.1U_0402_16V4Z 1 2 5 9 12 EC_ON R217 SPI@ 100K_0402_5% B 2 PCH_SPIDI PCH_SPICLK PCH_SPICS# PCH_SPIDO SPI@ 1OE# 2OE# 3OE# 4OE# 3 G +5VALW U51 1 4 10 13 100K_0402_5% 2 1 R227 C249 2 For MP phase 1 D R397 10_0402_5% MX25L3205DM2I-12G SO8 45@ +3V_SPI SPI_CLK U13 2 BSS138_NL_SOT23-3 @ 1 2 R285 0_0402_5% 1@ 1@ 1@ 1@ SPI_CS1# V4 +3VS FELICA_PWR 1 2 2 1M_0402_5% Q21 1 D 1 R125 3 T1 PCH_SPIDO 1 S AZ_SYNC_R 2 33_0402_5% SPI_CS0# PCH_SPIDI 4M Byte G 1 R156 Y14 +3V_SPI AZ_SYNC +5VS <31> AZ_SYNC_HD T3 PCH_SPICS# LPC_FRAME# <32,33> 2 2 R284 +3VALW PCH_SPICLK SPI down L=>On Die PLL is supplied by 1.8V Need to pull high for Huron River platform A SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATAICOMPO C signal has a weak internal pull *This H=>On Die PLL is supplied by 1.5V <32,33> <32,33> <32,33> <32,33> AM10 AM8 AP11 AP10 AD7 AD5 AH5 AH4 SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TCK JTAG_TMS AM3 AM1 AP7 AP5 SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_DOCK_RST# / GPIO13 JTAG ME debug mode, this signal has a weak internal pull down = Disable (default) *Low High = Enable (flash descriptor security overide) PCH_JTAG_TCK SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP 8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS HDA_SDO SATA0RXN SATA0RXP SATA0TXN SATA0TXP LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 1 3 PCH_RTCX1 LPC 1 32.768KHZ_12.5PF_Q13MC14610002 2 1 C205 15P_0402_50V8J @ 2 C248 2 1U_0402_6.3V6K OSC 2 2PCH_SRTCRST# NC 3 R293 1 20K_0402_5% JME 1 1 15P_0402_50V8J 2 SATA 6G iME Setting. 2 C216 Y3 1 SATA JCOMS @ 1 2 C247 2 1U_0402_6.3V6K RTC PCH_RTCRST# 2 IHDA R292 1 20K_0402_5% R291 10M_0402_5% 2 1 CMOS Setting, near DDR Door +RTCVCC 2 Title PCH_HDA/JTAG/SATA/SPI/LPC Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 16 of 45 2 U2B C505 1 C503 1 <29> <29> <29> <29> PCIE_PRX_C_CRTX_N4 PCIE_PRX_C_CRTX_P4 PCIE_PTX_C_CRRX_N4 PCIE_PTX_C_CRRX_P4 C504 1 C868 1 PERN2 PERP2 PETN2 PETP2 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K PCIE_PRX_JETTX_N3 PCIE_PRX_JETTX_P3 PCIE_PTX_JETRX_N3 PCIE_PTX_JETRX_P3 BG36 BJ36 AV34 AU34 PERN3 PERP3 PETN3 PETP3 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K PCIE_PRX_C_CRTX_N4 PCIE_PRX_C_CRTX_P4 PCIE_PTX_CRRX_N4 PCIE_PTX_CRRX_P4 BF36 BE36 AY34 BB34 PERN4 PERP4 PETN4 PETP4 BG37 BH37 AY36 BB36 <30> <30> <30> <30> USB30 PCIE_PRX_C_USBTX_N6 PCIE_PRX_C_USBTX_P6 PCIE_PTX_C_USBRX_N6 PCIE_PTX_C_USBRX_P6 C519 1 C869 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K PCIE_PRX_C_USBTX_N6 PCIE_PRX_C_USBTX_P6 PCIE_PTX_USBRX_N6 PCIE_PTX_USBRX_P6 BJ38 BG38 AU36 AV36 PERN6 PERP6 PETN6 PETP6 BG40 BJ40 AY40 BB40 PERN7 PERP7 PETN7 PETP7 BE38 BC38 AW 38 AY38 PERN8 PERP8 PETN8 PETP8 +3VS R287 1 2 10K_0402_5% CLKREQ_JET# R338 1 2 10K_0402_5% CLKREQ_WLAN# C <28> CLK_LAN# <28> CLK_LAN LAN <28> CLKREQ_LAN# WLAN <27> CLK_WLAN# <27> CLK_WLAN <27> CLKREQ_WLAN# <27> CLK_JET# <27> CLK_JET JET <27> CLKREQ_JET# <29> CLK_CR# <29> CLK_CR Card Reader CLK_LAN# CLK_LAN Y40 Y39 CLKREQ_LAN# J2 CLK_WLAN# CLK_WLAN AB49 AB47 CLKREQ_WLAN# M1 CLK_JET# CLK_JET AA48 AA47 CLKREQ_JET# V10 CLK_CR# CLK_CR Y37 Y36 CLKREQ_CR# A8 Y43 Y45 <30> CLK_USB30# <30> CLK_USB30 USB30 B +3VALW <30> CLKREQ_USB30# R343 1 210K_0402_5% CLKREQ_LAN# R344 1 210K_0402_5% PCH_GPIO26 R345 1 210K_0402_5% CLKREQ_CR# R346 1 210K_0402_5% CLKREQ_USB30# R348 1 210K_0402_5% PCH_GPIO46 R351 1 210K_0402_5% PCH_GPIO56 R352 R353 <5> CLK_CPU_ITP# <5> CLK_CPU_ITP 2 2 2 2 @ @ PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCH_SMLDATA0 SML1ALERT# / PCHHOT# / GPIO74 C13 PCH_GPIO74 SML1CLK / GPIO58 E14 PCH_SMLCLK1 M16 PCH_SMLDATA1 +3VS Q3B PCH_SMBDATA 3 Q3A 6 4.7K_0402_5% 4.7K_0402_5% 4 PM_SMBDATA <11,12,27> 2N7002DW-T/R7_SOT363-6 1 PM_SMBCLK <11,12,27> 2N7002DW-T/R7_SOT363-6 DRAMRST_CNTRL_PCH <7> D +3VALW 2 R364 1 2.2K_0402_5% 2 R385 1 2.2K_0402_5% +3VS PCH_SMLDATA1 3 Q4A PCH_SMLCLK1 CL_CLK1 4 EC_SMB_DA2 <32,33,34> 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2 <32,33,34> M7 CL_DATA1 T11 CL_RST1# P10 Control Link only for support Intel IAMT. +3VALW M10 EC_LID_OUT# R123 1 2 10K_0402_5% DRAMRST_CNTRL_PCH R228 1 2 10K_0402_5% PCH_GPIO74 R234 1 2 10K_0402_5% PCH_SMLCLK0 R238 1 2 10K_0402_5% PCH_SMLDATA0 R239 1 2 10K_0402_5% PCH_GPIO47 R251 1 2 10K_0402_5% PCH_GPIO47 C CLKOUT_PEG_A_N CLKOUT_PEG_A_P AB37 AB38 CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AM12 AM13 CLK_DPLL# CLK_DPLL CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 PCH_CLK_DMI# PCH_CLK_DMI T13 T14 PAD PAD CLKIN_GND1# CLKIN_GND1 G24 E24 CLK_DOT# CLK_DOT CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P AK7 AK5 CLK_SATA# CLK_SATA REFCLK14IN K45 CLK_14M_PCH CLKIN_PCILOOPBACK H45 CLK_PCILOOP XTAL25_IN XTAL25_OUT V47 V49 PCH_X1 PCH_X2 XCLK_RCOMP Y47 XCLK_RCOMP 1 R354 CLKOUTFLEX0 / GPIO64 K43 CLK_FLEX0 T29 PAD CLKOUTFLEX1 / GPIO65 F47 CLKOUTFLEX2 / GPIO66 H47 PCH_48MCLK 1 @ R576 2 22_0402_5% CLK_FLEX2 T31 PAD K49 CLK_FLEX3 CLKOUT_PCIE4N CLKOUT_PCIE4P CLKOUT_PEG_B_N CLKOUT_PEG_B_P CLK_CPU_DMI# <5> CLK_CPU_DMI <5> BJ30 BG30 CLKIN_GND1_N CLKIN_DMI2_N CLKIN_GND1_P CLKIN_DMI2_P CLKIN_DOT_96N CLKIN_DOT_96P 120 MHz for eDP From Clock Gen. PCH_CLK_DMI# PCH_CLK_DMI R242 1 R243 1 2 10K_0402_5% 2 10K_0402_5% CLKIN_GND1# CLKIN_GND1 R244 1 R245 1 2 10K_0402_5% 2 10K_0402_5% CLK_DOT# CLK_DOT R246 1 R247 1 2 10K_0402_5% 2 10K_0402_5% CLK_SATA# CLK_SATA R248 1 R249 1 2 10K_0402_5% 2 10K_0402_5% CLK_14M_PCH R250 1 2 10K_0402_5% B For EMI CLK_PCILOOP <20> CLK_PCILOOP @ 2 R417 @ 2 1 C474 22P_0402_50V8J 1 10_0402_5% PEG_B_CLKRQ# / GPIO56 CLKOUT_PCIE6N CLKOUT_PCIE6P T13 PCIECLKRQ6# / GPIO45 V38 V37 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P COUGARPOINT_FCBGA989~D CLKOUTFLEX3 / GPIO67 2 90.9_0402_1% T33 +1.05VS_VCCDIFFCLKN 48MCLK_USB30 <30> R365 2 1 1M_0402_5% Y2 PCH_X1 PAD Q65R3@ C506 27P_0402_50V8J +3VALW R400 R386 2N7002DW-T/R7_SOT363-6 PCIECLKRQ3# / GPIO25 V40 V42 AK14 AK13 PCH_SMLCLK0 G12 SML1DATA / GPIO75 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ5# / GPIO44 CLK_BCLK_ITP# CLK_BCLK_ITP 1 2.2K_0402_5% EC_LID_OUT# <32> DRAMRST_CNTRL_PCH C8 SML0CLK PCIECLKRQ2# / GPIO20 L14 1 0_0402_5% 1 0_0402_5% A12 SML0DATA CLKOUT_PCIE2N CLKOUT_PCIE2P CLKOUT_PCIE5N CLKOUT_PCIE5P K12 SML0ALERT# / GPIO60 PCIECLKRQ1# / GPIO18 V45 V46 PCH_GPIO46 PCH_SMBDATA PEG_A_CLKRQ# / GPIO47 CLKREQ_USB30# 1 0_0402_5% 1 0_0402_5% C9 CLKOUT_PCIE0N CLKOUT_PCIE0P CLK_USB30# CLK_USB30 LVDS_SEL PCH_SMBCLK 1 2.2K_0402_5% 2 R260 Q4B PCIECLKRQ4# / GPIO26 E6 H14 2 R232 PCH_SMBCLK L12 AB42 AB40 E12 SMBCLK SMBDATA PCH_GPIO26 PCH_GPIO56 R233 R282 <10> CLK_RES_ITP# <10> CLK_RES_ITP PERN5 PERP5 PETN5 PETP5 SMBALERT# / GPIO11 EC_LID_OUT# 5 PCIE_PRX_JETTX_N3 PCIE_PRX_JETTX_P3 PCIE_PTX_C_JETRX_N3 PCIE_PTX_C_JETRX_P3 BE34 BF34 BB32 AY32 Link Card Reader <27> <27> <27> <27> 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 +3VALW SMBUS JET C501 2 C502 2 PERN1 PERP1 PETN1 PETP1 Controller D PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_C_WLANRX_N2 PCIE_PTX_C_WLANRX_P2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K BG34 BJ34 AV32 AU32 FLEX CLOCKS WLAN <27> <27> <27> <27> C498 2 C497 2 PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1 CLOCKS LAN PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 PCI-E* <28> <28> <28> <28> 1 5 3 2 4 2 5 1 1 2 PCH_X2 25MHZ_20PF_7A25000012 2 1 2 C507 27P_0402_50V8J LVDS_SEL A A R347 1 2 10K_0402_5% LVDS_SEL LVDS_SEL @ R564 1 2 10K_0402_5% Channel H L Single (Default) Dual Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_PCI-E/SMBUS/CLK Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 1 17 of 45 5 4 3 2 1 U2C DRAMPWROK PCH_SUSPWRDN_R RI# PCH_LOW_BAT# PCH_RSMRST# 1 10K_0402_5% PM_PWROK 1 10K_0402_5% SYS_PWROK 1 10K_0402_5% 2 R127 2 R128 2 R129 BC24 BE20 BG18 BG20 <6> <6> <6> <6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 <6> <6> <6> <6> DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 AW24 AW20 BB18 AV18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN <6> <6> <6> <6> DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 AY24 AY20 AY18 AU18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP 0_0402_5% 1 @ R259 2 PM_PWROK 2 RBIAS_CPY 2 750_0402_1% BJ24 T34 SUSACK# XDP_DBRESET# <5> XDP_DBRESET# U12 O SYS_PWROK 4 FDI_FSYNC0 SN74AHC1G08DCKR_SC70-5 PM_PWROK 1 R216 PM_PWROK_R 2 0_0402_5% 1 PCH_SUSPWRDN_R 0_0402_5% <32> PCH_RSMRST# Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit 1 R320 <32> PCH_SUSPWRDN <5,32> PBTN_OUT# +3VALW B 1 R469 2 330K_0402_5% D12 1 <32,34,38> ACIN BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 AW16 FDI_INT AV12 FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 BC10 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 FDI_LSYNC1 BB10 FDI_LSYNC1 DSWVRMEN A18 DSWVREN DPWROK E22 PCH_DPWROK C12 K3 SUSACK# SYS_RESET# P12 SYS_PWROK L22 DRAMPWROK B13 PCH_RSMRST# C21 2 PCH_SUSPWRDN_R K16 0_0402_5% PBTN_OUT# E20 PCH_ACIN H20 PCH_LOW_BAT# E10 RI# A10 PWROK APWROK DRAMPWROK RSMRST# WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <6> <6> <6> <6> <6> <6> <6> <6> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <6> <6> <6> <6> <6> <6> <6> <6> D FDI_INT <6> BH21 B9 EC_SWI# N3 PM_GPIO32 G8 SUS_STAT# FDI_FSYNC0 PCH_DPWROK <6> FDI_FSYNC1 <6> FDI_LSYNC0 <6> FDI_LSYNC1 <6> Stuff R222 if do not support DeepSX state +RTCVCC DSWVREN SUSCLK / GPIO62 R224 2 R225 2 1 330K_0402_5% @ C 1 330K_0402_5% EC_SWI# <28,30> DSWVREN must be always pulled high to +RTCVCC T17 PAD * 32.768 KHz SLP_S5# / GPIO63 PCH_RSMRST# 2 0_0402_5% 1 R222 N14 CLK_EC <32> D10 PM_SLP_S5# H4 PM_SLP_S4# F4 PM_SLP_S3# G10 PM_SLP_A# T35 PAD G16 PM_SLP_SUS# T58 PAD AP14 H_PM_SYNC K14 PCH_GPIO29 Κ Κ DSWVREN - Internal Deep Sleep 1.05V regulator H Enable L Disable PM_SLP_S5# <32> +3VS SLP_S4# PM_SLP_S4# <32> PM_GPIO32 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 PMSYNCH R313 1 2 8.2K_0402_5% PM_SLP_S3# <32> 8/18 Change Net name from PM_CLKRUN# to PCH_GPIO32 by HW Review demand +3VALW B 2 CH751H-40PT_SOD323-2 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 BG25 IN2 <5> DRAMPWROK @ 2 R137 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_FSYNC1 L10 SUSACK# DMI_ZCOMP P 5 PAD IN1 3 <5,32> PM_PWROK DMI_COMP 2 49.9_0402_1% G 1 <5,32,43> VGATE DMI0RXP DMI1RXP DMI2RXP DMI3RXP 8/30 Reserve R259 For cost down plan +3VS 0.1U_0402_16V4Z 1 2 C250 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_INT 1 R130 +1.05VS_PCH 1 R160 C DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI 1 200_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 System Power Management 2 R316 2 R218 2 R220 2 R221 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI +3VALW D <6> <6> <6> <6> RI# SLP_LAN# / GPIO29 COUGARPOINT_FCBGA989~D H_PM_SYNC <5> EC_SWI# R319 1 2 10K_0402_5% PCH_GPIO29 R563 1 @ 2 10K_0402_5% Q65R3@ H_PM_SYNC 9/1 C898 1 @ 2 220P_0402_50V7K Reserve C894 for ESD requset D16 PM_PWROK 2 1 PCH_RSMRST# CH751H-40PT_SOD323-2 D14 <37,39> POK 1 2 CH751H-40PT_SOD323-2 A A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_DMI/FDI/PM Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 1 18 of 45 5 4 3 2 1 U2D 1 R219 1 R230 UMA_ENBKL 2 100K_0402_5% C 2 R471 LCTL_CLK 1 2.2K_0402_5% 2 R472 LCTL_DATA 1 2.2K_0402_5% 2 R223 LCD_EDID_CLK 1 2.2K_0402_5% 2 R229 LCD_EDID_DATA 1 2.2K_0402_5% 2 R237 UMA_CRT_CLK 1 2.2K_0402_5% 2 R231 UMA_CRT_DATA 1 2.2K_0402_5% 1 R240 UMA_CRT_B 2 150_0402_1% 1 R241 UMA_CRT_G 2 150_0402_1% 1 R318 UMA_CRT_R 2 150_0402_1% L_DDC_CLK L_DDC_DATA LCTL_CLK LCTL_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA <13> LCD_TXOUT0<13> LCD_TXOUT1<13> LCD_TXOUT2<13> LCD_TXOUT0+ <13> LCD_TXOUT1+ <13> LCD_TXOUT2+ <14> UMA_CRT_B <14> UMA_CRT_G <14> UMA_CRT_R <14> UMA_CRT_CLK <14> UMA_CRT_DATA <14> UMA_CRT_HSYNC <14> UMA_CRT_VSYNC 2 R311 AF37 AF36 LVD_IBG LVD_VBG AE48 AE47 LVD_VREFH LVD_VREFL LCD_TXCLKLCD_TXCLK+ AK39 AK40 LVDSA_CLK# LVDSA_CLK LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2- AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+ AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AF40 AF39 LVDSB_CLK# LVDSB_CLK AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 UMA_CRT_B UMA_CRT_G UMA_CRT_R N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED UMA_CRT_CLK UMA_CRT_DATA T39 M40 CRT_DDC_CLK CRT_DDC_DATA UMA_CRT_HSYNC UMA_CRT_VSYNC M47 M49 CRT_HSYNC CRT_VSYNC CRT_IREF 1 1K_0402_0.5% T43 T42 DAC_IREF CRT_IRTN SDVO_STALLN SDVO_STALLP AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 +3VS R214 2.2K_0402_5% HDMI@ R215 2.2K_0402_5% HDMI@ 2 AP43 AP45 SDVO_CTRLCLK SDVO_CTRLDATA P38 M39 AT49 AT47 AT40 HDMI_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 UMA_HDMI_TX2UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+ HDMI_HPD HDMI_HPD <15,21> UMA_HDMI_TX2UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+ <15> <15> <15> <15> <15> <15> <15> <15> 2 1 100K_0402_5% R1433 HDMI P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA D UMA_HDMI_CLK <15> UMA_HDMI_DATA <15> DDPB_AUXN DDPB_AUXP DDPB_HPD DDPC_CTRLCLK DDPC_CTRLDATA COUGARPOINT_FCBGA989~D 1 T40 K47 SDVO_TVCLKINN SDVO_TVCLKINP 1 L_BKLTCTL LCD_EDID_CLK LCD_EDID_DATA L_BKLTEN L_VDD_EN 2 P45 LVDS_IBG 2 2.37K_0402_1% T40 PAD <13> LCD_TXCLK<13> LCD_TXCLK+ +3VS PCH_PW M Digital Display Interface D J47 M45 LVDS <13> PCH_PW M <13> LCD_EDID_CLK <13> LCD_EDID_DATA UMA_ENBKL UMA_ENVDD CRT <32> UMA_ENBKL <13> UMA_ENVDD R473 2 1 100K_0402_5% C M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 R524 2 1 100K_0402_5% Q65R3@ B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_CRT/LVDS/HDMI Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 19 of 45 5 4 3 2 1 8.2K_0804_8P4R_5% 8/23 PIN swap for layout request 8 7 6 5 PCH_GPIO52 PCH_GPIO53 PCH_GPIO54 RF_OFF# 1 2 3 4 8.2K_0804_8P4R_5% RP3 C 8 7 6 5 PCH_GPIO50 PCI_PIRQB# ODD_DA# W L_OFF# 1 2 3 4 8.2K_0804_8P4R_5% PCH_GPIO5 2 8.2K_0402_5% PCI_PIRQD# 2 8.2K_0402_5% 1 R321 1 R322 <27> RF_OFF# <27> W L_OFF# <25> ODD_DA# B T32 PAD <5,27,28,29,30,32,33> <32> CLK_PCI_EC <17> CLK_PCILOOP <33> CLK_PCI_DDR PLT_RST# 22_0402_5% 1 22_0402_5% 1 22_0402_5% 1 B21 M20 AY16 BG46 TP21 TP22 TP23 TP24 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 RF_OFF# PCH_GPIO53 W L_OFF# D47 E42 F46 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 K10 C6 2 R525 2 R526 2 R527 CLK_EC_R CLK_PCH CLK_SIO H49 H43 J48 K42 H40 AV5 AY1 PIRQA# PIRQB# PIRQC# PIRQD# NV_RB# AT8 AY5 BA2 NV_CLE AT12 BF3 C USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB port6 and port7 are disabled on HM65 USBRBIAS# C33 USBBIAS USBRBIAS B33 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 EHCI 2 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 D AV10 NV_RE#_WRB0 NV_RE#_WRB1 EHCI 1 C46 C44 E40 PLT_RST# NV_ALE NV_WE#_CK0 NV_WE#_CK1 PCH_GPIO50 PCH_GPIO52 PCH_GPIO54 PCI_PME# AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 NV_RCOMP K40 K38 H38 G38 G42 G40 C42 D44 AT10 BC8 DF_TVS NV_CLE PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 NV_DQS0 NV_DQS1 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 PCI RP2 AY7 AV7 AU3 BG4 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 <25> <25> <25> <25> <25> <25> USB-RIGHT1 USB-RIGHT2 USB-Left1 DMI & FDI Termination Voltage Set to VCC when HIGH NV_CLE USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USB20_N8 <26> USB20_P8 <26> USB20_N9 <27> USB20_P9 <27> USB20_N10 <27> USB20_P10 <27> USB20_N11 <13> USB20_P11 <13> USB20_N12 <27> USB20_P12 <27> USB20_N13 <26> USB20_P13 <26> 1 R535 Set to VSS when LOW +1.8VS Finger Printer WiMax 1 PCI_PIRQC# PCH_GPIO4 PCH_GPIO2 PCI_PIRQA# 1 2 3 4 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 R324 2.2K_0402_5% TV Tuner #1 Int. Camera NV_CLE 3G/ TV tuner #2 2 RP1 8 7 6 5 USB +3VS TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD D BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 NVRAM U2E 2 R323 1 1K_0402_5% 8/18 Change R324 From 1K to 2.2K by Intel check list demand 2 22.6_0402_1% H_SNB_IVB# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 COUGARPOINT_FCBGA989~D B Within 500 mils PME# PLTRST# H_SNB_IVB# <5> Felica USB_OC#0 USB_OC#1 USB_OC#2 SLP_CHG_M3 SLP_CHG_M4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#0 <25,32> USB-Right USB_OC#1 <27,30,32> USB-Left & C895 1 @ 2 220P_0402_50V7K eSATA SLP_CHG_M3 <27> SLP_CHG_M4 <27> 9/1 Reserve C895 for ESD requset +3VALW Q65R3@ RP4 SLP_CHG_M4 USB_OC#0 SLP_CHG_M3 USB_OC#6 Boot BIOS Strap RF_OFF# 1K_0402_5% 1K_0402_5% 2 2 @ @ 1 R537 RF_OFF# 1 R538 PCH_GPIO19 A 1K_0402_5% 2 @ 1 R536 W L_OFF# PCH_GPIO19 <16> PCH_GPIO19 0 1 0 1 0 0 1 1 Boot BIOS Loaction 10K_0804_8P4R_5% RP5 USB_OC#1 USB_OC#2 USB_OC#5 USB_OC#7 Reserved PCI * * Low= A16 swap override Enable High= A16 swap override Disable 4 5 6 7 8 A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 1 10K_0804_8P4R_5% A16 Swap Override Strap WL_OFF# 5 6 7 8 8/23 PIN swap for layout request LPC SPI 4 3 2 1 3 2 Title PCH_PCI/USB/NAND Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 1 20 of 45 5 4 3 2 1 +3VS +3VALW U2F ODD_EN# C C40 ODD_EN# TACH1 / GPIO1 TACH5 / GPIO69 B41 PCH_W L_BT_LED PCH_GPIO6 H36 TACH2 / GPIO6 TACH6 / GPIO70 C41 LOGO_LED EC_SCI# E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 MAXIC_SELECT <32> EC_SMI# EC_SMI# C10 GPIO8 PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12 USB30_SMI# G2 GPIO15 PCH_GPIO16 PCH_GPIO17 U2 D40 BT_DET# T5 E8 <27> BT_ON# T74 PAD <25> ODD_DETECT# <27> ISDBT_DET @ SCLOCK / GPIO22 GPIO24 / MEM_LED GPIO27 PCH_GPIO28 P8 GPIO28 BT_ON# K1 STP_PCI# / GPIO34 PCH_GPIO35 K4 GPIO35 ODD_DETECT# V8 SATA2GP / GPIO36 PCH_GPIO37 M5 SATA3GP / GPIO37 OPTIMUS_EN# N2 SLOAD / GPIO38 CIR_EN# M3 SDATAOUT0 / GPIO39 V13 ISDBT_DET PECI P4 <34> W L_BT_LED# PROCPWRGD AY11 H_PW RGOOD THRMTRIP# AY10 RCIN# INIT3_3V# T14 NC_1 AH8 NC_2 AK11 NC_3 AH10 NC_4 AK10 NC_5 P37 KB_RST# <32> Q53B H_PW RGOOD <5> PCH_THRMTRIP# 1 R416 2 390_0402_5% PCH_W L_BT_LED H_THERMTRIP# <5> VSS_NCTF_15 BG2 VSS_NCTF_16 BG48 3D_DET# D6 GPIO57 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 This signal has weak internal pull-up, can't be pulled low 8/18 Remove PCH PECI by HW Review demand +3VS VSS_NCTF_1 VSS_NCTF_19 BJ4 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 VSS_NCTF_21 BJ45 VSS_NCTF_22 BJ46 VSS_NCTF_23 BJ5 IC TYPE A45 VSS_NCTF_3 A46 VSS_NCTF_4 A5 VSS_NCTF_5 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 B3 VSS_NCTF_7 VSS_NCTF_25 C2 B47 VSS_NCTF_8 VSS_NCTF_26 C48 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BF49 VSS_NCTF_14 VSS_NCTF_32 F49 1 14550@ 2 R444 10K_0402_5% 1 2 R124 14566@ 10K_0402_5% C MAXIC_SELECT MAXIC_SELECT A4 5 2N7002DW -T/R7_SOT363-6 MAXIC_SELECT SATA5GP / GPIO49 D GATEA20 <32> KB_RST# SDATAOUT1 / GPIO48 COUGARPOINT_FCBGA989~D GATEA20 P5 V3 2 1K_0402_5% PCH_GPIO28 LOGO_LED <34> AU16 PCH_GPIO49 On-Die PLL Voltage Regulator H: Enable L: Disable 1 TACH0 / GPIO17 E16 GPIO28 R325 A20GATE SATA4GP / GPIO16 PCH_GPIO27 2 1 R437 10K_0402_5% PCH_GPIO37 2 1 R547 100K_0402_5% PCH_GPIO27 2 1 R402 10K_0402_5% CIR_EN# 2 CIR@ 1 R405 10K_0402_5% ISDBT_DET 1 2 R328 47K_0402_5% * ODD_EN# <35> <32> EC_SCI# USB30_SMI# @ B T7 3 3D_DET# BT_ON# 2 10K_0402_5% HDMI_HPD 2 10K_0402_5% PCH_GPIO1 2 10K_0402_5% BT_DET# 2 10K_0402_5% OPTIMUS_EN# 2 10K_0402_5% ODD_DETECT# 2 200K_0402_5% PCH_GPIO6 2 10K_0402_5% PCH_GPIO16 2 10K_0402_5% EC_SCI# 2 10K_0402_5% CIR_EN# 2 100K_0402_5% ISDBT_DET 2 10K_0402_5% PCH_GPIO49 2 10K_0402_5% PCH_GPIO17 2 10K_0402_5% @ TACH4 / GPIO68 A42 CPU/MISC PCH_GPIO28 <30> USB30_SMI# @ BMBUSY# / GPIO0 PCH_GPIO1 PCH_GPIO12 +3VS 1 R567 1 R539 1 R540 1 R542 1 R554 1 R545 1 R546 1 R577 1 R550 1 R551 1 R552 1 R553 1 R555 HDMI_HPD EC_SMI# 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 4 <15,19> HDMI_HPD USB30_SMI# GPIO D 1 1K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% NCTF 2 R390 1 R558 1 R556 1 R557 1 R549 1 R106 GATEA20 1 R548 KB_RST# 1 R559 LOGO_LED 1 R436 PCH_W L_BT_LED 1 R110 H L MAX14550E MAX14566B 8/30 Add MAC IC select function for MAX14550E/14566B co-lay B H_THERMTRIP# C896 1 @ 2 220P_0402_50V7K H_PW RGOOD C897 1 @ 2 220P_0402_50V7K 9/1 Q65R3@ Reserve C896, C897 for ESD requset GPIO8 * Integrated Clock Chip Enable (Removed) H: Disable L: Enable R326 1 @ 2 1K_0402_5% OPTIMUS_EN# OPTIMUS_EN# SKU A H L EC_SMI# Discrete Optimus A Integrated clock enable functionality is achieved by soft-strap The current default is clock enable Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_CPU/GPIO Size B Date: Document Number Rev 0.2 PHQAA LA-6832P M/B Thursday, October 07, 2010 Sheet 1 21 of 45 4 3 +1.05VS_VCCP U2G 1 C275 C289 1 D 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K +1.05VS_PCH This pin can be left as NC if On-Die VR is enabled (Default) AN19 +1.05VS_PCH @ +VCCAPLLEXP VCCAPLLEXP AN16 VCCIO[15] AN17 2 AN26 AN27 C +1.05VS_PCH AP21 1U_0402_6.3V6K 1 C279 1 C510 1 1 C511 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K 2 BH29 2 AP16 +1.05VS_PCH VCCALVDS +VCCA_LVDS AK36 BG6 AK37 VCCTX_LVDS[1] AM37 AM38 +1.8VS +VCCTX_LVDS 1 VCCTX_LVDS[3] AP36 VCCTX_LVDS[4] AP37 L1 1 2 0.1UH_MLF1608DR10KT_10%_1608 0.01U_0402_25V7K C514 0.01U_0402_25V7K C513 B VCC3_3[6] 2 V33 1 VCC3_3[7] V34 C272 0.1U_0402_10V7K 2 VCCVRM[3] VCCIO[23] VCCIO[24] +1.5VS R474 0_0603_5% 1 2 AT16 +VCCAFDI_VRM VCCIO[20] VCCDMI[1] 20mA VCCIO[1] AT20 +VCCP_VCCDMI AB36 +1.05VS_VCC_DMI 1 2 VCCIO[25] R477 0_0805_5% 1 2 AP17 +VCCP_VCCDMI AU20 0.001 5 0.001 D 5 0.001 VCC3_3 3.3 0.266 VCCADAC 3.3 0.001 VCCADPLLA 1.05 0.08 VCCADPLLB 1.05 0.08 VCCCORE 1.05 1.3 VCCDMI 1.05 0.042 VCCIO 1.05 2.925 VCCPNAND[1] VCC3_3[3] VCCVRM[2] VCCFDIPLL +1.05VS_PCH 1 2 C276 1U_0402_6.3V6K VCCIO[27] VCCDMI[2] 1.05 1.01 3.3 0.02 VCCDSW 3.3 0.002 VCCDFTERM 1.8 0.19 VCCRTC 3.3 6 uA 3.3 0.97 VCCSUS3_3 +1.8VS AG16 VCCASW VCCSPI C +1.05VS_VCCP R480 0_0805_5% 1 2 C270 1U_0402_6.3V6K VCCDFTERM VCCIO[26] FDI +1.05VS_PCH 1.05 C256 22U_0805_6.3V6M VCCSusHDA VCCPNAND[2] 1 190mA VCCPNAND[3] AJ16 2 VCCPNAND[4] VCCSPI VCCVRM 1.5 0.16 VCCCLKDMI 1.05 0.02 VCCSSC 1.05 0.095 AJ17 VCCDIFFCLKN 1.05 0.055 VCCALVDS 3.3 0.001 VCCTX_LVDS 1.8 0.06 V1 1 COUGARPOINT_FCBGA989~D 0.01 C278 0.1U_0402_10V7K +3VS 20mA 3.3 / 1.5 AG17 1 C280 1U_0402_6.3V6K 2 @ S0 Iccmax Current (A) 2 0_0603_5% V5REF_SUS VSSALVDS VCCTX_LVDS[2] 1 R541 +VCCP_VCCDMI @ +1.05VS_VCCAPLL_FDI V_PROC_IO 2 +VCCAFDI_VRM C290 0.1U_0402_10V7K +VCCAFDI_VRM Voltage C286 10U_0603_6.3V6M V5REF 1mA VCCIO[19] 2925mA VCCIO[22] AN34 Voltage Rail +3VS 1U_0402_6.3V6K 1 1 0_0603_5% 2 1 VCCIO[18] VCCIO[21] AT24 +3VS R483 2 U47 VCCIO[17] AP24 AN33 This pin can be left as NC if On-Die VR is enabled (Default) C512 0.01U_0402_25V7K PCH Power Rail Table L12 2 1 BLM18PG181SN1D_0603 +3VS VCCIO[16] AP23 AP26 10U_0603_6.3V6M 0.1U_0402_10V7K 1 C288 VCCIO[28] BJ22 AN21 C273 VSSADAC 60mA 1 C509 10U_0603_6.3V6M @ 1 VCCADAC +VCCA_DAC U48 L22 1 2 1UH_LB2012T1R0M_20% C277 1mA HVCMOS 10U_0603_6.3V6M +3VS CRT C269 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] 1 POWER LVDS JUMP_43X118 1 C274 2 1300mA AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 DMI 1 +1.05VS_PCH 1U_0402_6.3V6K 1 NAND / SPI 2 @ VCCIO PJ31 2 VCC CORE 5 Q65R3@ 2 C281 1U_0402_6.3V6K B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_POWER-1 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 22 of 45 5 4 3 2 1 This pin can be left as NC if On-Die VR is enabled (Default) +3VS +1.05VS_PCH POWER U2J 1 D This pin can be left as NC if On-Die VR is enabled (Default) T16 2 @ C305 2 1 "@" Avoid leakage AD49 C324 0.1U_0402_10V7K +1.05VS_PCH VCCACLK VCCIO[29] VCCIO[30] 3mA VCCDSW3_3 VCCIO[31] +PCH_VCCDSW V12 +3VS_VCC_CLKF33 T38 DCPSUSBYP VCCIO[32] 0.1U_0402_10V7K +1.05VS_PCH VCCIO[33] BH23 AL29 +1.05VS_PCH +VCCSUS AA21 AA24 C311 1 AA26 1 C312 AA27 22U_0805_6.3V6M 2 2 22U_0805_6.3V6M AA29 AA31 C C323 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1 C294 C308 2 2 AC26 1 AC27 1U_0402_6.3V6K 2 AC29 +1.05VS_PCH AC31 L21 10UH_LB2012T100MR_20% 1 2 AD29 +1.05VS_VCCADPLLA AD31 L19 1 2 10UH_LB2012T100MR_20% +1.05VS_VCCADPLLB 1 C333 220U_B2_2.5VM_R15 + 2 W21 W23 1 C295 1 C515 1 + C298 1U_0402_6.3V6K W24 1U_0402_6.3V6K 2 2 2 220U_B2_2.5VM_R15 W26 W29 W31 +1.05VS_PCH R522 W33 2 +VCCDIFFCLK 1 0_0603_5% 1 DCPSUS[3] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[6] AA19 VCCASW[1] VCCASW[2] VCCIO[34] 1010mA 1mA VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS +VCCRTCEXT C334 0.1U_0402_10V7K 2 N16 1 VCCSUS3_3[1] 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] Y49 C328 1U_0402_6.3V6K T27 T29 +3VALW T23 1 T24 V23 C321 0.1U_0402_10V7K 2 +3VALW +5VALW +3VALW 1 V24 P24 2 C332 0.1U_0402_10V7K R512 100_0402_5% T26 CH751H-40PT_SOD323-2 VCC3_3[8] VCCASW[16] VCC3_3[4] 1 M26 +PCH_V5REF_SUS AN23 +VCCA_USBSUS 2 C335 1 AN24 P34 +3VALW +3VALW VCCASW[20] +1.05VS_VCCADPLLA BD47 VCCVRM[4] VCCIO[13] +1.05VS_VCCDIFFCLKN 1 1 0_0603_5% C320 1U_0402_6.3V6K +1.05VS_VCCADPLLB BF47 +VCCDIFFCLK AF17 AF33 AF34 AG34 2 +1.05VS_VCCDIFFCLKN +1.05VS_PCH VCCADPLLB 80mA 80mA C318 1U_0402_6.3V6K 1 CH751H-40PT_SOD323-2 C293 1U_0402_6.3V6K 2 VCCVRM[1] VCCIO[7] VCCIO[8] VCCIO[9] 55mA VCCIO[11] P22 +3VS VCCIO[10] VCCIO[4] 95mA 1 2 +VCCSST V16 0.1U_0402_10V7K +1.05VM_VCCSUS C299 T17 V19 +3VS W16 T34 1 C313 0.1U_0402_10V7K 2 +3VS AJ2 +1.05VS_SATA3 1 AF13 2 1 AH13 +1.05VS_SATA3 AH14 +1.05VS_PCH R516 C297 0.1U_0402_10V7K 1 0_0805_5% C329 1U_0402_6.3V6K This pin can be left as NC if On-Die VR is enabled (Default) 2 +V_CPU_IO BJ8 VCCASW[22] 1mA 1 C316 1U_0402_6.3V6K 0_0603_5% C325 4.7U_0603_6.3V6K 1 2 C322 1 2 1 C303 +VCCAFDI_VRM 1 +1.05VS_VCC_SATA +1.05VS_PCH AC16 +1.05VS_VCC_SATA AC17 2 2 1 0_0805_5% 1 AD17 C296 10U_0603_6.3V6M @ C331 1U_0402_6.3V6K VCCASW[23] VCCASW[21] T21 +VCCME_22 R509 2 1 0_0603_5% V21 +VCCME_23 R517 2 1 0_0603_5% T19 +VCCME_21 R520 2 1 0_0603_5% +RTCVCC +3VALW 0.1U_0402_10V7K 2 2 C327 A 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2 C330 1 2 1 2 A22 C336 VCCRTC RTC +1.05VM_VCCSUS 1 V_PROC_IO CPU 0.1U_0402_10V7K @ 0_0603_5% AF11 +1.05VS_PCH DCPSUS[1] DCPSUS[2] R511 R521 2 +VCCSATAPLL +VCCAFDI_VRM 10mA VCCSUSHDA COUGARPOINT_FCBGA989~D P32 1 Q65R3@ 0.1U_0402_10V7K C307 0.1U_0402_16V4Z A 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 B +1.05VS_PCH L17 @ 1 2 10UH_LB2012T100MR_20% AF14 AK1 DCPSST +1.05VS_VCCP 2 C304 1U_0603_10V6K AA16 R491 VCCIO[2] +PCH_V5REF_RUN 1 2 2 1 VCCAPLLSATA VCCIO[3] AG33 +1.05VS_PCH VCCIO[6] MISC 2 VCCADPLLA D7 1 P20 2 DCPRTC SATA +1.05VS_VCCDIFFCLKN R485 +3VS R490 100_0402_5% 1 2 C306 0.1U_0402_10V7K HDA +1.05VS_PCH +5VS C +PCH_V5REF_RUN N22 VCCASW[18] VCC3_3[2] C326 0.1U_0603_25V7K 2 1U_0402_6.3V6K N20 VCCASW[17] VCCASW[19] +PCH_V5REF_SUS +1.05VS_PCH 2 B D8 2 VCC3_3[1] VCCIO[12] +VCCAFDI_VRM 2 @ DCPSUS[4] VCCIO[5] C337 1U_0402_6.3V6K D P28 2 2 +1.05VS_PCH AL24 C300 1U_0402_6.3V6K @ 119mA VCCIO[14] PCI/GPIO/LPC 1 VCCAPLLDMI2 Clock and Miscellaneous 2 VCCSUS3_3[7] USB +VCCAPLL_CPY_PCH 1 C302 10U_0603_6.3V6M @ 1 P26 VCC3_3[5] L20 @ 1 2 10UH_LB2012T100MR_20% N26 2 +3VALW 1 C310 1U_0402_6.3V6K 2 2 1 C301 10U_0603_6.3V6M +VCCACLK 1 0_0603_5% 1 2 @ R498 2 1 1 +3VS_VCC_CLKF33 1 2 L18 1 2 10UH_LB2012T100MR_20% 4 3 2 Title PCH_POWER-2 Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 23 of 45 5 4 3 2 1 U2I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 U2H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 D C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] COUGARPOINT_FCBGA989~D VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 Q65R3@ VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] COUGARPOINT_FCBGA989~D H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B Q65R3@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_GND Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 24 of 45 5 SATA HDD Conn. +5VS 3 2 1 SATA ODD Conn Place closely JHDD SATA CONN. C356 10U_0805_10V4Z 2 1 2 C357 0.1U_0402_16V4Z 1 C358 0.1U_0402_16V4Z 2 1 JODD 2 D 15 14 Close to JODD @ C359 0.1U_0402_16V4Z GND GND GND A+ AGND BB+ GND 1 2 3 4 5 6 7 DP +5V +5V MD GND GND 8 9 10 11 12 13 ODD_DA#_R SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 C378 1 C377 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 <16> SATA_PTX_DRX_N2 <16> SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C376 1 C375 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N2 <16> SATA_PRX_C_DTX_P2 <16> ODD_DETECT#_R 1 +5VS_ODD R561 ODD_DA#_R 1 R562 2 0_0402_5% ODD_DETECT# <21> 2 0_0402_5% ODD_DA# <20> 1 2 3 4 5 6 7 GND A+ AGND BB+ GND GND GND 2 4 Place components closely ODD CONN. 1.1A 1 2 1 C352 10U_0805_10V4Z 2 1 C353 10U_0805_10V4Z 2 1 @ C354 1U_0402_6.3V6K 2 1 C355 0.1U_0402_16V4Z 2 C360 0.1U_0402_16V4Z Close to JHDD JHDD 24 23 SW5 SMT1-05-A_4P 3 D +5VS_ODD SANTA_206401-1_RV C 1 6 5 1.2A 1 4 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 C369 1 C367 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P0 <16> SATA_PTX_DRX_N0 <16> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C368 1 C370 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N0 <16> SATA_PRX_C_DTX_P0 <16> R73 1 USB Board@ Right Side +3VS +USB_VCCA U14 USB_EN# 1 2 3 4 GND VOUT VIN VOUT VIN VOUT EN FLG <20> USB20_P0 4 <20> USB20_N0 1 W=60mils 2.5A +5VALW +5VS 8 7 6 5 2 C361 0_0402_5% 2 4 1 L53 1 R87 For EMI R77 1 1 1000P_0402_50V7K W=60mils +USB_VCCA 3 3 USB20_P0_R 2 2 USB20_N0_R @ 1 2 R148 0_0402_5% +5VALW @ @ USB20_N0_R USB20_P0_R 0_0402_5% 2 <20> USB20_P1 4 4 3 3 USB20_P1_R C362 4.7U_0805_10V4Z 2 @ <20> USB20_N1 1 1 L54 2 2 USB20_N1_R 1 R88 @ +5V_IO USB20_N1_R USB20_P1_R 2 0_0402_5% 1 SANTA_191201-1 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 R149 0_0402_5% +5VL WCM-2012-900T_0805 USB_OC#0 <20,32> RT9715BGS_SO8 @ WCM-2012-900T_0805 2 0_0402_5% <31> HP_R <31> HP_L <31> MIC1_L <31> MIC1_R <31> NBA_PLUG <31> BACK_SENSE JPIO @ 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C ACES_85201-2005N 10/04 Swap USB20_P0, USB20_N0, USB20_P1, USB20_N1 for layout request USB Board@ Left Side S D Q8 1 +USB_VCCC 3 +USB_VCCB AO3413_SOT23 <32> USB_EN# B 1 R568 2 100K_0402_5% 2 G +5VALW USB_EN# B 8/30 Change C426 to Aluminum Solid Cap 220u for cost down +USB_VCCC C426 1 2 220U_6.3V_M_R15 + W=60mils @ 2 R190 1 0_0402_5% C428 1 2 1000P_0402_50V7K C389 1 2 0.1U_0402_16V4Z L15 JUSB <20> USB20_N2 3 3 4 4 <20> USB20_P2 2 2 1 1 USB20_N2_R USB20_P2_R WCM-2012-900T_0805 2 R189 @ VCC DD+ GND @ GND GND GND GND 5 6 7 8 ALLTOP C107L8-10405-L 1 0_0402_5% D23 A 1 2 3 4 USB20_N2_R 2 USB20_P2_R 3 @ 1 A PJDLC05C_SOT23-3 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title SATA-HDD/ODD/USB Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 25 of 45 5 4 3 2 1 Screw cap for ESD request B+ C490 C489 2 @1 2 0.1U_0402_25V6 2 @1 0.1U_0402_25V6 2 @1 C268 C236 @1 0.1U_0402_25V6 D 0.1U_0402_25V6 D For EMI Felica 2 2 2 TV@ RB8 2.2K_0402_5% B CB3 TV@ 4.7U_0603_6.3V6K 2 G Q34 <16> FELICA_PW R USB20_N13 USB20_P13 FELICA_GND <20> USB20_N13 <20> USB20_P13 2 1 C758 0.1U_0402_16V4Z FELICA@ 2 1 R132 0_0603_5% FELICA@ 1 2 3 4 5 6 7 8 @ 1 2 3 4 5 6 G1 G2 ACES_87151-06051 2 R419 FELICA@ 100K_0402_5% C479 FELICA@ 0.1U_0402_16V7K 1 FELICA@ 1 2 2 R403 47K_0402_5% 2 C403 D 0.01U_0402_25V7K FELICA@ 1 2N7002_SOT23-3 S FELICA@ 3 1 2 1 R445 100K_0402_5% @ 1 FELICA@ C414 0.1U_0402_16V4Z 1 1 TV@ RB7 10K_0402_5% 1 CB4 TV@ 0.1U_0402_16V4Z 2 +5VS_L_BCAS 1 4 1 5 +5VS_L_BCAS LB1 TV@ 1 2 1 FBMA-L11-201209-221LMA30T_0805 CB5 TV@ 1U_0402_6.3V6K 2 1 +5VS_BCAS QB2B TV@ +FLICA_VCC R147 0_0603_5% FELICA@ 2 3 1 47K_0402_5% 1 TV@ TV@ CB2 2 0.01U_0402_25V7K 2 3 2 1 1 2 3 G 1 D 2 +3VS +5VS QB1 AO3413_SOT23 TV@ JFEL R154 0_0603_5% @ G 2 RB5 current = 0A D 100K_0402_5% BCPW ON +5VS S Inrush 1 TV@ CB1 0.1U_0402_16V7K TV@RB2 TV@ RB2 <27> BCPW ON +3VS C +5VS +5VALW 2N7002DW -T/R7_SOT363-6 Reserve +3VS Felica by Customer demand. 2010/09/27 2 B-CAS Circuit S C Q20 AO3413_SOT23 FELICA@ +FLICA_VCC B 5 +5VS_L_BCAS IN2 UB1 TV@ Finger printer P IN1 O 4 G <27> BCRSTM 1 BCRSTM 2 B_R_BCRST 1 TV@ RB9 B_BCRST 2 100_0402_5% B_BCRST <27> IN2 +3VS O 4 B_R_XBCCLK1 TV@ RB11 B_XBCCLK 2 100_0402_5% B_XBCCLK <27> 3 SN74AHC1G08DCKR_SC70-5 1 R134 2 0_0603_5% 1 FP@ C480 0.1U_0402_16V4Z FP@ 2 +3VS_FP USB20_N8 USB20_P8 FP_GND <20> USB20_N8 <20> USB20_P8 1 2 3 4 5 6 1 2 JFP UB2 TV@ P IN1 G XBCLKM <27> XBCLKM 1 D82 +5VS_L_BCAS R133 0_0603_5% FP@ FP@ 4 VIN IO1 2 3 IO2 GND 1 @ 1 2 3 4 GND GND P-TW O_161011-04021 2 5 3 SN74AHC1G08DCKR_SC70-5 CM1293A-02SR SOT143-4 <27> CPLGP1 CPLGP1 5 2 B BCIO A BCIO <27> C 1 2 RB14 TV@ 1.5K_0402_5% QB2A TV@ 2 2N7002DW -T/R7_SOT363-6 2 1 RB13 TV@ 10K_0402_5% For ESD 1 2 RB12 TV@ 10K_0402_5% QB4 TV@ 2SB1197K_SOT23-3 1 10K_0402_5% 6 +5VS_L_BCAS E TV@ 2 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 RB1 1 3 A 4 3 2 Title IR/FP/B-CAS/Felica Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 26 of 45 +3VS 2 1 1 BT on module Enable Disable H L PCIE--JET BT_CRTL PJ26@ JUMP_43X79 BT_ON# <26> XBCLKM L H <17> CLK_JET# <17> CLK_JET **If +3V_WLAN is +3VS, please remove D24 <26> BCRSTM <26> BCPWON D24 CM2 2 0.01U_0402_25V7K CM3 C253 CM7 CM8 47P_0402_50V8J 2 2 2 @ 4.7U_0805_10V4Z 0.01U_0402_25V7K 1 Q36 3 1 1 1 1 <17> PCIE_PTX_C_JETRX_N3 <17> PCIE_PTX_C_JETRX_P3 D 2 G <21> BT_ON# 0.1U_0402_16V4Z 1 2 CM1 BT_CTRL 2 For SED <17> PCIE_PRX_JETTX_N3 <17> PCIE_PRX_JETTX_P3 S 2N7002_SOT23-3 CM9 C254 47P_0402_50V8J 2 2 @ 4.7U_0805_10V4Z +3VS 2 0.1U_0402_16V4Z 1 1 SUSP# CH751H-40PT_SOD323-2 +1.5VS For SED 1 <16,32,35,40,42> 40 mils 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 BCCDET <17> CLKREQ_JET# Short PJ27 for Wimax Short PJ26 for WLAN +3V_WLAN B-CAS +3V_WLAN PJ27@ JUMP_43X79 2 1 2 1 <32> TMPTU2_SXP 53 +1.5VS <17> CLK_WLAN# <17> CLK_WLAN <17> PCIE_PRX_WLANTX_N2 <17> PCIE_PRX_WLANTX_P2 <17> PCIE_PTX_C_WLANRX_N2 <17> PCIE_PTX_C_WLANRX_P2 WLAN/ WiFi +3V_WLAN <32> E51_TXD <32> E51_RXD R16 10_0402_5%2 1 2 0_0402_5% R17 E51_RXD_R 53 Debug card using 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 GND2 2.75A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +UIM_PWR UIM_DATA UIM_CLK UIM_RESET COMMON ISDBT_DET ISDBT_DET <21> RF_OFF# RF_OFF# <20> PLT_RST# USB20_P10_TV 1 R126 2 TV@ 0_0402_5% USB20_N10_TV 1 2 TV@ 0_0402_5% R135 R72 1 3G@ PM_SMBCLK 2 0_0402_5% R85 1 3G@ PM_SMBDATA 2 0_0402_5% USB20_N12 <20> USB20_P12 <20> C255 47P_0402_50V8J @ RM3 1 3G@ 0_0402_5% UIM_VPP 2 1 TV@ RM7 BCIO 2 0_0402_5% 2 2 4.7U_0805_10V4Z COMMON USB--TV#2 Close to J3G 1 TV@ RM4 1 3G@ RM1 +5VS_BCAS USB--3G/TV#1 +UIM_PWR LED_WIMAX# CPLGP1 CPLGP1 <26> TMPTU1_SXP <32> UIM_RESET B-CAS B_BCRST <26> B_BCRST 1 R327 2 1K_0402_5% E51_RXD_R Add BCCDET pull down 1 TV@ R307 BCCDET For isolate Intel Rainbow Peak and Compal Debug Card. B_XBCCLK <26> B_XBCCLK 2 470_0402_5% +UIM_PWR UIM_DATA BCIO WL_OFF# <20> PLT_RST# <5,20,28,29,30,32,33> PLT_RST# USB20_N9 <20> USB20_P9 <20> LED_WIMAX# 1 RM6 1 2 3 CM13 0.1U_0402_16V4Z 3G@ WiMax 7 1 2 DM1 RLZ20A_LL34 3G@ LED_WIMAX# <34> 1 CM15 10P_0402_50V8J 3G@ 2 +VCC_SIM 1 3G@ RM5 1 TV@ RM8 SIM_RESET 2 0_0402_5% 2 0_0402_5% 1 3G@ RM9 1 TV@ RM10 2 0_0402_5% 2 0_0402_5% 1 3G@ RM11 1 TV@ RM12 SIM_DATA 2 0_0402_5% 2 0_0402_5% VCC RST CLK GND VPP I/O 4 5 6 1 NC NC SIM_CLK RM2 4.7K_0402_5% @ @ J3GSIM +VCC_SIM SIM_RESET SIM_CLK PM_SMBCLK <11,12,17> PM_SMBDATA <11,12,17> 2 0_0603_5% 2 0_0603_5% 54 UIM_CLK BT_CTRL 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 BCIO <26> USB20_P10 <20> USB20_N10 <20> FOX_AS0B226-S40N-7F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 For SED 1 <17> CLKREQ_WLAN# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 0.01U_0402_25V7K 2 UIM_VPP SIM_DATA 1 1 R1443 0_0402_5% @ 2BT_CTRL_R BT_CTRL 1 +3VS @ +3V_WLAN @ 2 JWLAN CM4 +1.5VS J3G 120 mils 0.1U_0402_16V4Z 1 1 CM5 CM6 2 2 +3VALW BT on module 1 1 Slot 1 Half PCIe Mini Card-WLAN/ WiMax +3VS Slot 2 Full PCIe Mini Card- 3G/ TV Tuner Half PCIe Mini Card- JET 2 WLAN&BT Combo module circuits 8 MOLEX_47273-0001~D 2 CM16 10P_0402_50V8J 2 3G@ CM14 22P_0402_50V8J @ 2 +3VS 100K_0402_5% WIMAX@ 54 GND2 8/30 Reserve R1443 for WLAN Mini PCIE Card Pin5 FOX_AS0B226-S40N-7F USB Sleep & Charge Auto-Mode Mode3/Mode4 MAX14566B CB0 SLP_CHG# <30,32> USB_CHG_EN# GND VOUT VIN VOUT VIN VOUT EN FLG RT9715BGS_SO8 2 STATUS AUTO MODE 0 0 AUTO MODE 0 1 Force Dedicated charger mode (MODE3) 1 Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM 0 1 MODE3 X Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM 1 0 MODE4 1 1 Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM 14566@ R1444 10_0402_5%2 1 C383 4.7U_0805_10V4Z @ CB1 SLP_CHG_M4 0 USB_OC#1 <20,30,32> 1 CB0 SLP_CHG_M4 AUTO MODE W=60mils 8 7 6 5 STATUS 0 +USB_VCCB U15 1 2 3 4 CB: SLP_CHG# STATUS 0 1 2.5A +5VALW MAX14550E MAX14566E CB1 (CEN#) SLP_CHG_M3 <20> SLP_CHG_M3 SLP_CHG_M3 <30> USB20_DN1_R <30> USB20_DP1_R 14566@ R1441 0_0402_5% 1 2 USB20_DN1_R USB20_DP1_R U5 1 2 3 4 9 CEN DM DP GND GND CB TDM TDP VCC 8 7 6 5 2 0_0402_5% R1445 @ U2D_DN1 U2D_DP1 1 MAX14566EETA+_TDFN-EP8_2X2~D 14566@ 2 SLP_CHG_M4 SLP_CHG# <32> U57 <20> SLP_CHG_M4 U2D_DN1 <30> U2D_DP1 <30> +5VALW C892 0.1U_0402_16V7K 14566@ CB0 DP DM GND RDP GND CB1 TDP TDM VCC RDM 10 9 8 7 6 2010/09/03 SLP_CHG_M3 U2D_DP1 U2D_DN1 +5VALW 1 2 C893 0.1U_0402_16V7K 14550@ 8/30 Add MAX14550E Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 1 2 3 4 5 11 MAX14550EETB-T_TDFN10 14550@ 9/2 Change U5 Pin8 control pin from SLP_CHG# to SLP_CHG_M4 9/2 Add 14566@ & 14550@ SLP_CHG_M4 USB20_DP1_R USB20_DN1_R Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCIe-WLAN/JET/3G/TV/NewCard Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 27 of 45 A B C D E UL1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 CLKREQ_LAN# <17> CLKREQ_LAN# <5,20,27,29,30,32,33> PLT_RST# <17> CLK_LAN <17> CLK_LAN# CLKREQ_LAN# 1 10K_0402_5% EC_SWI# +3VS Pin15 NC LAN_X1 43 LAN_X2 44 EC_SWI# <18,30> EC_SWI# NC 28 ISOLATE# Pin38 1 2 NC 19 20 26 10K ohm PD 1K ohm Pull-high RL21 2 8111E@ 1 10K_0402_5% RL22 1 2 1K_0402_5% +3V_LAN 1K_0402_5% RL6 @ ISOLATE# ENSWREG 1 RL433 CLKREQB PERSTB REFCLK_P REFCLK_N WOL_EN 2 0_0402_5% CKXTAL2 RL7 15K_0402_5% Sx Enable Sx Disable Wake up Wake up WOL_EN LOW 1 RL5 S0 ISOLATEB MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3 1 2 4 5 7 8 10 11 DVDD10 DVDD10 DVDD10 13 29 41 RL2 2 RL1 2 1 10K_0402_5% 1 10K_0402_5% LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- Layout Note: LL1 must be within 200mil to Pin36, CL13,CL9 must be within 200mil to LL1 1 CL9 0.1U_0402_16V4Z 2 8111E@ CL13 4.7U_0603_6.3V6K 8105ESWR@ CL9 0.1U_0402_16V4Z 8105ESWR@ +LAN_VDD10 33 ENSWREG +LAN_VDD10 VDDREG VDDREG RSET GND PGND +3V_LAN AVDD33 AVDD33 AVDD33 AVDD33 12 42 47 48 +3V_LAN EVDD10 21 +LAN_EVDD10 AVDD10 AVDD10 AVDD10 AVDD10 3 6 9 45 +LAN_VDD10 36 REGOUT 1 1 2 2 CL17 0.1U_0402_16V4Z Close to Pin 21 +3V_LAN 8111E@ 8111E@ +LAN_VDDREG 8111E@ 1 8111E@ LL3 2 0_0603_5% 1 8111E@ 1 CL28 4.7U_0603_6.3V6K 8105ESWR@ CL29 0.1U_0402_16V4Z 8105ESWR@ +3V_LAN ENSWREG 2 LAN_X2 2 1 CL684 10U_0805_10V6K @ 1 CL26 27P_0402_50V8J 2 RL23 0_0402_5% 8105ELDO@ CL27 27P_0402_50V8J 1 LAN Conn. UL3 8105ELDO@ CL682 1U_0402_6.3V6K LAN_MDI0+ LAN_MDI0- 2 LAN_MDI1+ LAN_MDI1- 1 2 3 4 5 6 7 8 TD+ TDCT NC NC CT RD+ RD- TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 RJ45_MIDI0+ RJ45_MIDI0- JLAN 3 RJ45_MIDI1+ RJ45_MIDI1- RJ45_MIDI3- 8 RJ45_MIDI3+ 7 RJ45_MIDI1- 6 RJ45_MIDI2- 5 RJ45_MIDI2+ 4 RJ45_MIDI1+ 3 1 2 3 LAN_MDI2LAN_MDI2+ 4 5 6 LAN_MDI1LAN_MDI1+ 7 8 9 LAN_MDI0LAN_MDI0+ 10 11 12 UL1 UL3 TCT1 TD1+ TD1- MCT1 MX1+ MX1- TCT2 TD2+ TD2- MCT2 MX2+ MX2- TCT3 TD3+ TD3- MCT3 MX3+ MX3- TCT4 TD4+ TD4- MCT4 MX4+ MX4- 24 23 22 CL40 1000P_0402_50V7K 2 1 1 8111E@ 2 8111E@ RL12 75_0402_1% 21 20 19 CL41 1000P_0402_50V7K 2 1 1 2 RL13 75_0402_1% 18 17 16 CL42 1000P_0402_50V7K 2 1 1 2 RL15 75_0402_1% 15 14 13 RJ45_MIDI3RJ45_MIDI3+ RJ45_MIDI0- 2 RJ45_MIDI0+ 1 1 2 CL34 0.1U_0402_25V4K PR3+ PR2+ DL1 AZ5125-02S.R7G_SOT23-3 PR1- @ PR1+ SHLD2 RJ45_MIDI1RJ45_MIDI1+ SANTA_130451-D @ 9 10 DL2 AZ5125-02S.R7G_SOT23-3 @ 8/30 Reserve DL1 and DL2 for ESD request RJ45_MIDI0RJ45_MIDI0+ 1 CL36 2 1000P_1808_3KV7K LANGND 1 CL37 1 CL38 4 2 Compal Secret Data 2010/09/03 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B PR3- RJ45_MIDI2RJ45_MIDI2+ SUPERWORLD_SWG150401 8111E@ Security Classification A PR2- SHLD1 RJ45_GND Place CL34, CL35 colse 1 @ to LAN chip CL35 0.1U_0402_25V4K 2 PR4+ 3 LAN_MDI3LAN_MDI3+ CL39 1000P_0402_50V7K 2 1 1 8111E@ 2 8111E@ RL11 75_0402_1% PR4- 1 UL4 10/100M transformer 8105ESWR@ RL4 0_0402_5% 8105ESWR@ 2 X'FORM_ NS681680 4 0 ohm (Pull Down) RL23 8/30 Add UL3 at DVT +3V_LAN rising time (10%~90%) need > 1ms and <100ms. 8105E-VC 10/100M 8105ESWR@ NC 2 FOR EMI ISN TEST DEMAND. 3 8105E-VC 10/100M 8105ELDO@ RTL8105E-VC RTL8105E-VC RTL8111E-VB PWM Mode LDO Mode RL4 0 ohm NC (Pull High) 2 CL681 4.7U_0805_10V4Z @ UL1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 2 PJ29 JUMP_43X79 @ +3V_LAN 1 For P/N and footprint Please place them to ISPD page 1 CL19 1 CL20 1 CL21 1 CL22 1 CL23 1 CL24 1 CL25 1 @ CL482 0.01U_0402_25V7K 1 3 2 1 AO3413_SOT23 1 G 2 D 2 1 0.1U_0402_16V4Z 2 1 @ QL51 2 S @ RL432 47K_0402_5% 1 CL683 + 220U_6.3V_M_R16 @ 2 Vgs=-4.5V,Id=3A,Rds<97mohm 1 25MHZ_20PF_7A25000012 1 1 0.1U_0402_16V4Z 2 1 +3VALW +3VALW <32> WOL_EN 0.1U_0402_16V4Z 2 RL4 0_0402_5% 8111E@ YL1 CL483 @ 0.1U_0402_16V7K 0.1U_0402_16V4Z 2 +3V_LAN LL3 0_0603_5% 8105ESWR@ LAN_X1 1 0.1U_0402_16V4Z 2 CL29 0.1U_0402_16V4Z 2 8111E@ CL28 4.7U_0603_6.3V6K 8111E@ 2 +LAN_REGOUT 60 mils +3VALW TO +3V_LAN 2 0.1U_0402_16V4Z 2 CL19, CL20,CL21 close to pin 13,29,45, respectively CL22 close to pin 3, respectively CL23,CL24,CL25 close to pin 6,9,41, respectively 2 0_0603_5% CL18 1U_0402_6.3V6K RTL8111E-GR_QFN48_6X6 8111E@ 2 2 +LAN_EVDD10 1 LL2 HIGH HIGH RL147 100K_0402_5% @ 1 CL3 1 CL4 1 CL5 1 CL6 1 8111E@ CL7 1 8111E@ CL8 1 CL13 4.7U_0603_6.3V6K 8111E@ 2 LL1 2.2UH +-5% NLC252018T-2R2J-N 8105ESWR@ +LAN_VDD10 27 39 DVDD33 DVDD33 NC/SMBCLK NC/SMBDATA GPO/SMBALERT 2 46 2.49K_0402_1% 24 49 30 32 8111E@ +LAN_REGOUT 1 2 2.2UH +-5% NLC252018T-2R2J-N LANWAKEB 14 15 38 34 35 +LAN_VDDREG EECS/SCL EEDI/SDA CL3 to CL6 close to Pin 27,39,47,48 CL7 to CL8 close to Pin 12,42 +LAN_VDD10 LL1 CKXTAL1 RTL8111E RTL8105E Pin14 CLK_LAN CLK_LAN# HSIP HSIN 31 37 40 2 1 10K_0402_5% RL25 2 @ 1 16 0_0402_5% 25 HSON LED3/EEDO LED1/EESK LED0 1 RL24 2 @ 2 RL19 PLT_RST# +3V_LAN HSOP 3 +3V_LAN 23 PCIE_PTX_C_LANRX_P1 17 PCIE_PTX_C_LANRX_N1 18 <17> PCIE_PTX_C_LANRX_P1 <17> PCIE_PTX_C_LANRX_N1 1 22 2 <17> PCIE_PRX_C_LANTX_N1 CL2 1 1 CL1 2 <17> PCIE_PRX_C_LANTX_P1 C D Title 0.1U_0402_16V4Z 2 4.7U_0603_6.3V6K Compal Electronics, Inc. PCIe-LAN-RTL8105E/8111E Size Document Number Custom Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet E 28 of 45 5 4 3 2 1 +1.8VS_OUT CC3 close to pin 5 JMB389C D 2 1 CC3 2 1 CC4 2 0.1U_0402_16V4Z CC16 close to pin43 For internal LDO in SD3.0 1 CC2 1000P_0402_50V7K 2 10U_0805_10V4Z 1 CC1 0.22U_0402_6.3V4K CC2 close to CC3 CC1 is near CC3 20mil D3E mode CC4 close to pin 10 +3VS <16> CR_CPPE# RC31 1 0_0402_5% CPPE# 2 <16> CR_W AKE# RC6 1 0_0402_5% SD_CD# 2 D +3VS UC1 place near pin 19,20 and 44 CLK_CR# CLK_CR <17> CLK_CR# <17> CLK_CR PCIE_PTX_C_CRRX_N4 PCIE_PTX_C_CRRX_P4 <17> PCIE_PTX_C_CRRX_N4 <17> PCIE_PTX_C_CRRX_P4 <17> PCIE_PRX_C_CRTX_N4 <17> PCIE_PRX_C_CRTX_P4 CC8 CC9 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 3 4 PCIE_PRX_CRTX_N4 PCIE_PRX_CRTX_P4 APREXT 1 12K_0402_1% 12mil 2 RC3 2 CC16 9 8 +SDV33_18 1 2.2U_0603_6.3V6K 11 12 7 43 39 APCLKN APCLKP 1 2 PLT_RST# CPPE# XD_CD# C 13 14 MS_CD# SD_CD# CR_LED 2 XDW P#_SDW P# 1 10K_0402_5% 2 1K_0402_5% RC7 1 RC9 19 20 44 18 37 MDIO0 MDIO1 MDIO2 MDIO3 MDIO6/4 MDIO5 G/MDIO6 MDIO7 MDIO8 MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 48 47 46 45 41 42 24 40 29 28 27 26 25 23 22 APREXT SDDV/MDIO4 TXIN/NC XRSTN XTEST CPPE_N CR1_CD2N 15 16 CR1_CD1N CR1_CD0N 17 CR1_PCTLN 21 DV33 DV33 DV33 DV18 DV18 APTXN APTXP 40 mils +VCC_OUT +VCC_OUT 5 10 36 APRXN APRXP JMB389 <5,20,27,28,30,32,33> APVDD APV18 NC/TAV33 1 40mil CC5 1 CC6 NC/SPI_SCK NC/SPI_CSN NC/SPI_SO NC/SPI_SI 30 33 34 35 APGND NC/GND NC/GND NC/GND 6 31 32 38 1 CC7 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 +1.8VS_OUT 20mil CC12 0.1U_0402_16V4Z 1 CC12 close to pin 36 Power On Strapping setting XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SDCMD_MSBS_XDW E# SDCLK_MSCLK_XDCE# XDW P#_SDW P# XD_CLE XD_SD_D4 XD_SD_D5 XD_SD_D6 XD_SD_D7 XD_RE# XD_RB# XD_ALE CC10 2 CC11 1 1 2 0.22U_0402_6.3V4K 10U_0805_10V4Z Description Pin name CC11 close to pin18 For intenal LDO's usage MDIO7 CC10 close to pin37 MDIO14 High Ϫ on-board add-in card Ϫ CR_LED high active CR_LED low active +3VS XD_CLE MDIO7 XD_ALE CR1_LEDN low MDIO14 1 RC28 @ 2 1 RC26 @ 1 RC25 @ C 10K_0402_5% 2 1K_0402_5% 2 200K_0402_5% XD_RB# Vendor review to set @ JMB389-LGAZ0A_LQFP48_7X7 Add RC24 and RC17 close to UC1 for xD issue SDCMD_MSBS_XDW E# XDW E# 2 RC24 1 22_0402_5% 2 RC17 SDCMD_MSBS 1 22_0402_5% 5 in 1 Card Reader B SD_CD# XD_CD# JREAD +VCC_OUT @ 40 mils CC22 0.1U_0402_16V4Z @ 1 1 2 2 CC23 0.1U_0402_16V4Z @ CC17 10U_0805_10V4Z CR_LEDCON# 2 RC8 1 2 CR_LEDCON# 1 2 CC18 0.1U_0402_16V4Z XD_CD# XD_RB# XD_RE# XD_CE# XD_CLE XD_ALE XDW E# XDW P#_SDW P# 33 34 1 2 3 4 5 6 7 XD-VCC XD-CD-SW XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_SD_D4 XD_SD_D5 XD_SD_D6 XD_SD_D7 8 9 26 27 28 30 31 32 XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 14 15 17 21 19 20 18 16 MS_CLK MS_CD# SDCMD_MSBS XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SD-VCC SD-CLK SD-CMD SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-WP-SW SD-CD-SW 23 24 12 25 29 10 11 35 36 SD_CLK SDCMD_MSBS XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XDW P#_SDW P# SD_CD# 4in1-GND 4in1-GND 4in1-GND 4in1-GND 13 22 37 38 <34> 1 0_0402_5% B MS-VCC MS-SCLK MS-INS MS-BS MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 +VCC_OUT SDCLK_MSCLK_XDCE# SD_CLK RC12 1 2 22_0402_5% MS_CLK RC13 1 2 22_0402_5% XD_CE# Reserved for EMI,close to UC1.42 @ RC14 SD_CLK 1 2 @ CC19 1 2 MS_CLK 100_0402_5% @ RC15 1 2 XD_CE# 100_0402_5% 100P_0402_50V8J @ @ RC16 CC21 1 2 1 2 100P_0402_50V8J @ CC20 1 2 TAITW _R015-211-LM-A_NR 1 100_0402_5% 100P_0402_50V8J A CR_LED 2 2 G S 3 Reserved for EMI,close to JREAD Confirm sinking 16mA RC10 4.7K_0402_5% @ Compal Secret Data Security Classification 1 QC1 2N7002_SOT23-3 @ 2 0_0402_5% +VCC_OUT D A RC11 1 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCIe-CardReader JMB389 Size Document Number Custom Date: Rev 0.2 PHQAA LA-6832P M/B Sheet Thursday, October 07, 2010 1 29 of 45 5 4 +1.5V to +1.05V Transfer 1 2 +5VALW 1 RT1 4.7K_0402_5% +5VALW USB30_POK Close to U102.D7 +1.05V UT2 USB30_POK 5 9 6 7 +3V 8 3 4 VIN VOUT VIN VOUT VCNTL POK FB EN 1 Close to U102.P13 +3VA +3VA 2 2 1 GND 2 1A APL5930KAI-TRG_SO8 D 2 +1.5V 1 RT2 10K_0402_1% 1 RT3 32.4K_0402_1% 2 Vout=0.8(1+10K/32.4K) 1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025 1 0.1U_0402_16V7K CT4 CT3 10U_0603_6.3V6M CT2 10U_0603_6.3V6M 2 CT1 1U_0603_10V6K 1 +1.5V 1 +5VALW 3 2 1 8P_0402_50V8D CT6 1 @ 2 CT5 2 0.01U_0402_25V7K 1 0.1U_0402_16V7K CT7 2 1 8P_0402_50V8D CT9 1 @ U3RXDP1_R 2 CT8 2 0.01U_0402_25V7K 1 2 4 3 U3TXDP1 1 2 3 4 1 2 RT5 0_0402_5% WCM-2012-121T_0805 3 4 3 2 1 U3TXDP1_L D 1 +3VALW to +3V Transfer U3RXDP1_R_L 2 RT4 0_0402_5% LT1 @ 4 WCM-2012-121T_0805 1 2 RT6 0_0402_5% U3RXDN1_R +3VALW +3VALW U3RXDN1_R_L 1 LT2 @ U3TXDN1 1 2 2 2 RT7 0_0402_5% U3TXDN1_L 2 Follow Vendor recommend. <27> USB20_DN1_R <27> USB20_DP1_R F2 F1 U2DP2 U3RXDP2 2 U3RXDN2 CT25 RT12 10_0402_5% 2 RT15 RT16 RT17 +3V USB30_SMI#_IC +1.05V 2 10K_0402_5% 1 D 1 2 3 2 1 G S 2N7002_SOT23-3 1 @ 2 USB30_SMI_R RT21 0_0402_5% PPON2 PPON1 PONRSTB SPI_CLK_USB SPI_CS_USB# SPI_SI_USB SPI_SO_USB M2 N2 N1 M1 K13 K14 J13 SPISCK SPISCB SPISI SPISO U3TXDN1 U2DM1 U2DP1 U3RXDP1 GND GND GND U3RXDN1 @ 2 USB30_SMI#_R RT40 0_0402_5% C14 RREF U2AVSS GND U2PVSS +3V 2 RT26 100_0402_5% 2 0_0402_5% 2 @ RT31 @ 1 1 2 CT38 12P_0402_50V8J 2 @ CT37 12P_0402_50V8J RT30 0_0402_5% 1 RT291 2 0_0402_5% 2 24MHZ_12PF_X5H024000DC1H RT281 2 0_0402_5% YT1 1 P6 CSEL 2 1 1 2 0.01U_0402_25V7K 0.1U_0402_16V7K 1 1 CT15 0.01U_0402_25V7K 1 2 CT14 0.01U_0402_25V7K 1 2 CT13 0.01U_0402_25V7K 0.01U_0402_25V7K 1 2 CT12 2 CT11 CT10 B U3AVSS XT1 XT2 +3V <17> 48MCLK_USB30 Place as close as possibile to UU102.N14 and UU102.M14 A1 A2 A3 A4 A5 A7 A9 A11 A13 A14 B3 B4 B5 B7 B9 B11 B13 B14 C1 C2 C3 C10 C11 CT26 P8 B8 OCI2# OCL1# 1 RT13 H14 J14 USB30PWRON 2 10K_0402_5% CT28 2 C 1000P_0402_50V7K JUSB30 U3TXDP1_L +USB_VCCB B10 U3TX_C_DP1 CT32 A10 N10 U3TX_C_DN1 U2D_DN1 CT33 U2D_DP1 U3RXDP1_R 1 2 0.1U_0402_16V7K U3TXDP1 1 2 0.1U_0402_16V7K U3TXDN1 U2D_DN1 <27> U2D_DP1 <27> 9 1 8 3 7 2 6 4 5 U3TXDN1_L USB20_DP1_L USB20_DN1_L U3RXDP1_R_L U3RXDN1_R_L SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX- GND GND GND GND 10 11 12 13 W=80mils USB_GND SANTA_371394-3 0_0603_5% A12 0_0603_5% RT42 U3RXDN1_R RT41 P12 N12 RT22 1 2 1 2 1.6K_0402_1% N11 D6 @ 2USB_CHG_EN# USB_CHG_EN# <27,32> GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND P14 P11 P9 P7 P2 P1 N13 N9 N7 N3 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 L12 L11 L7 L6 +USB_VCCB DT2 U3TXDN1_L U3TXDP1_L U3RXDN1_R_L U3RXDP1_R_L 1 2 3 4 RR+ TT+ VCC GND DD+ 8 7 6 5 USB20_DN1_L USB20_DP1_L LXES4XBAA6-027_MSOP8 @ +3V +3V 10K_0402_5% 2 RT43 1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND USB30_SMI#_IC QT3B 4 3 C12 C13 D3 D4 D11 D12 D13 D14 E1 E2 E13 E14 F4 F6 F7 F8 F9 F11 F12 G1 G2 G6 G7 G8 G9 G11 G12 G13 H6 H7 H8 H9 H12 J3 J4 J6 J7 J8 J9 J11 J12 K3 K4 L1 L2 L3 L4 2N7002DW-T/R7_SOT363-6 OCL1# USB30_SMI# 1 10K_0402_5% 2 RT44 1 <21> QT3A 6 USB_OC#1 <20,27,32> 2N7002DW-T/R7_SOT363-6 A UPD720200AF1-DAP-SSA-A 1 2 1 CT27 2 +3V A RT33 10K_0402_5% SPI_CLK_USB UT4 1 2 3 4 CS# SO WP# GND 35mA VCC HOLD# SCLK SI 1 RT34 2 0_0402_5% @ 2 1 1 220U_6.3V_M_R15 G14 H13 P10 B12 CT31 2 A8 +3V SPI_CS_USB# SPI_SO_USB + 2 +3V RT32 47K_0402_5% 0.1U_0402_16V4Z 1 1 B CSEL=0 CSEL=1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 9/2 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80 (10uF_0603) by sourcer demand A6 N8 USB30PWRON RT11 1 0_0402_5% ΚΚ24MHz XTAL 48MHz Clock 1 CLK_48M_USB N14 M14 4.7U_0805_10V4Z .1U_0402_16V7K Q57 @ P5 OCI2B OCI1B AUXDET PSEL SMI SMIB U3TXDP1 1SS355TE-17_SOD323-2 1 2 1 2 DT3 For UPD720200: SMI high active J2 J1 H1 P4 PERSTB PEWAKEB PECREQB +USB_VCCB W=80mils B6 CT45 USB30_SMI#_IC RT391 +3V 1 2 1 RT18 CT44 1U_0603_10V6K 1 0.01U_0402_25V7K 0.01U_0402_25V7K 1 2 CT24 2 CT23 2 0.01U_0402_25V7K 0.1U_0402_16V7K 1 1 CT22 0.01U_0402_25V7K 1 2 CT21 2 CT20 2 0.01U_0402_25V7K 0.1U_0402_16V7K 0.01U_0402_25V7K 0.1U_0402_16V7K 1 1 CT19 2 CT18 CT17 CT16 2 UPD720200A: SMIB Low active 0_0402_5% H2 K1 K2 USB30_WAKE# 1 2 10K_0402_5% @ @1 2 100_0402_1% 1 2 10K_0402_5% USB30_SMI_R USB30_SMI#_R 2 USB20_DP1_L 2 <5,20,27,28,29,32,33> PLT_RST# <18,28> EC_SWI# <17> CLKREQ_USB30# +3V 1 D7 U3TXDN2 U2DM2 PERXP PERXN USB20_DN1_L 3 @ WCM-2012-900T_0805 1 2 RT10 0_0402_5% P13 U3TXDP2 +1.05V:800mA 3 2 U2AVDD10 H11 K11 K12 L8 VDD10 VDD10 VDD10 VDD10 E11 E12 E3 E4 H3 H4 L5 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 C8 C9 D8 D9 VDD10 VDD10 VDD10 VDD10 C4 C5 C6 C7 D5 VDD10 VDD10 VDD10 VDD10 VDD10 N4 N5 N6 P3 VDD33 VDD33 VDD33 VDD33 L13 L14 VDD33 VDD33 L9 L10 VDD33 VDD33 F3 G3 G4 VDD33 VDD33 VDD33 D10 F13 F14 PETXP PETXN 4 2 1 D2 D1 +3V:200mA 1 1 PCIE_PRX_USBTX_P6 PCIE_PRX_USBTX_N6 <17> PCIE_PTX_C_USBRX_P6 <17> PCIE_PTX_C_USBRX_N6 10U_0603_6.3V6M 1 4 2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K CT29 2 CT30 2 PECLKP PECLKN U3AVDO33 B2 B1 <17> CLK_USB30 <17> CLK_USB30# <17> PCIE_PRX_C_USBTX_P6 <17> PCIE_PRX_C_USBTX_N6 C VDD33 VDD33 VDD33 +3V & +1.05V has power sequence timing: 0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms LT3 1 2 BLM18AG601SN1D_2P 1 USB20_DP1_R +3V S 2N7002_SOT23-3 +3VA USB20_DN1_R 2 3 2 0_0402_5% 2 LT4 UT1 +3V RT9 1 1 3 +3VA QT1 AO3413_SOT23 2 1 1 1 G <32,40> SYSON D +1.05V D 2 G QT2 1 2 RT38 47K_0402_5% CT43 0.01U_0402_25V7K +3V CT42 0.1U_0402_16V4Z S CT41 0.1U_0402_16V7K 1 5 2 RT37 100K_0402_5% 8 7 6 5 CT39 1 2 0.1U_0402_16V7K 2010/09/17 Add Level shift to avoid +3V leakage from +3VALW_PCH 2 Close to UU37.6 1 1 RT35 210K_0402_5% SPI_CLK_USB_R CT40 0.1U_0402_16V7K @ Issued Date MX25L5121EMC-20G SOP 8P SPI_CLK_USB_R 1 RT36 2 0_0402_5% Compal Secret Data Security Classification SPI_SI_USB 200910/9 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SPI_CLK_USB Title Size Document Number Custom Date: 5 4 3 2 Compal Electronics, Inc. PCIe-USB3.0 UPD720200A Rev 0.2 PHQAA LA-6832P M/B Thursday, October 07, 2010 1 Sheet 30 of 58 4 3 +PVDD1 2 CA57 1 1 2 1 CA1 1 CA8 1 MIC1_LINE1_R_R 0_0402_5% 1 2 CA10 1U_0402_6.3V6K RA37 4.7U_0805_10V4Z CA21 2 1 0_0402_5% MIC1_LINE1_R_L @ MIC1_LINE1_R_R 2 1 4.7U_0805_10V4Z C <13> INT_MIC_DATA <32> EC_MUTE# For EMI CA11 0.01U_0402_25V7K @ 1 CA12 CA48 1 2 0.1U_0603_50V7K CA49 1 2 0.1U_0603_50V7K CA50 1 2 0.1U_0603_50V7K 1 10_0603_5% 38 AVDD2 25 LINE2_L LINE2_R SPK_OUT_R+ SPK_OUT_R- 45 44 SPKR+ SPKR- 21 22 MIC1_L MIC1_R HP_OUT_L HP_OUT_R 32 33 MIC2_L MIC2_R EC_MUTE# 4 PD# 11 RESET# 12 PCBEEP 13 SENSE A 18 SENSE B 75_0402_1% 75_0402_1% SYNC 10 AZ_SYNC_HD BCLK 6 AZ_BITCLK_HD SDATA_OUT 5 SDATA_IN 8 EAPD AZ_SDOUT_HD AZ_SDIN0_HD_R SPDIFO 48 20 1 33_0402_5% 29 30 28 <16> AZ_SDIN0_HD CA23 10U_0805_10V4Z 1 2 +MIC1_VREFO_R 35 CBN VREF 27 AC_VREF 31 MIC1_VREFO_L JDREF 19 AC_JDREF2 RA9 CPVEE 34 AVSS1 AVSS2 26 37 9/1 2 2.2U_0603_6.3V4Z CA17 2 2 0.1U_0402_16V4Z Function PORT-B (PIN 21, 22) Ext. MIC CA16 2.2U_0603_6.3V6K @ MIC1_LINE1_R_L 10K PORT-C (PIN 23, 24) 20K PORT-F (PIN 16, 17) 2 1 1K_0402_5% RA32 CA18 100P_0402_50V8J 1 +MIC1_VREFO_R MIC1_R <25> B MIC1_L <25> RA29 1 2 2.2K_0402_5% +MIC1_VREFO_L MIC_SENSE AGND 1 4.7K_0402_5% +3VL place close to chip +3VALW MIC_SENSE PORT-E (PIN 14, 15) 2 RA28 RA22 2 20K 39.2K C QA1A Headphone out (PIN 48) MONO_IN 0.1U_0402_16V4Z 2N7002DW -T/R7_SOT363-6 PORT-I (PIN 32, 33) 5.1K CA13 1 2 RA33 2 RA31 1 1K_0402_5% 2.2K_0402_5% 2 1 MIC1_LINE1_R_R 1 RA42 100K_0402_5% @ Codec Signals SPK_R2 Ext.MIC/LINE IN JACK place close to chip DGND PESD5V0U2BT_SOT23-3 Change RA12 from 10k to 4.7kohm and CA18 from 0.1uF to 100pF for Beep by A51 demand. 1 20K_0402_1% 1 CPVEE 1 CA14 CA27 1U_0402_6.3V6K Change to AGND for high frequency noise issue CA29 1 1 2 @ RA17 10P_0402_50V8J AZ_BITCLK_HD 2 10_0402_5% CBP 3 2 RA12 4.7K_0402_5% <16> For EMI @ MIC2_VREFO AZ_BITCLK_HD ACES_85204-0400N @ 2 RA8 1 2 47K_0402_5% AZ_SDOUT_HD <16> 2 RA6 47 MONO_OUT <16> @ RA7 1 2 47K_0402_5% PCI Beep HP_R <25> AZ_SYNC_HD DA6 1 2 3 4 1 1 ALC269Q-VB5-GR _QFN48_7X7 39.2K 2 RA10 1 20K_0402_1% 100K_0402_5% 2 RA43 RA34 100K_0402_5% @ 100K_0402_5% <32> SM_SENSE# SENSE_A QA1B 5 BACK_SENSE <25> 2N7002DW -T/R7_SOT363-6 <25> NBA_PLUG RA21 39.2K_0402_1% 2010/09/03 PORT-H (PIN 20) Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 10K HP_L <25> 1 2 3 4 Beep sound EC Beep RA5 36 PVSS2 PVSS1 DVSS2 DVSS1 close to chip <32> EC_BEEP# RA4 MIC1_VREFO_R LDO_CAP 43 42 49 7 CA26 RA16 @ 10U_0805_10V4Z 2 2 1 0_0603_5% SPKR- <16> PCH_SPKR GPIO1/DMIC_CLK +5VALW AVDD1 46 39 PVDD2 14 15 GPIO0/DMIC_DATA 1 2 INT_MIC_CLK_R CA15 FBMA-10-100505-301T 2.2U_0603_6.3V4Z CAM@ 1 +MIC1_VREFO_L CA28 27P_0402_50V8J @ 2 EC_MUTE# Impedance SPKL+ SPKL- 16 17 CA6 SPK_L1 SPK_L2 SPK_R1 SPK_R2 SPK_R1 CA25 @ 10U_0805_10V4Z 2 @ 1 1 D JSPK SPK_L2 6 2 0.1U_0603_50V7K 5 SPKR+ 3 PESD5V0U2BT_SOT23-3 1 <13> INT_MIC_CLK CA5 40 41 3 RA41 CA4 1 2 2 2 2 place 10U_0805_10V4Z 0.1U_0402_16V4Z SPK_OUT_L+ SPK_OUT_L- 2 For EMI CA3 1 LINE1_L LINE1_R INT_MIC_CLK_R MONO_IN 2 100P_0402_50V8J UA1 1 23 24 INT_MIC_DATA SENSE_A SENSE B 2 10U_0805_10V4Z RA3 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VALW 0_0603_5% SPKL- 2 CA24 1U_0402_6.3V6K 3 RA44 100K_0402_5% @ CA22 AZ_RST_HD# <16> AZ_RST_HD# A 2 2 CA20 RA14 @ 10U_0805_10V4Z 2 2 1 0_0603_5% RA15 2 1 0_0603_5% 1 @ 1 4 0_0402_5% SENSE A 0.1U_0402_16V4Z +5VALW 1 1 CA59 CA58 @ @ DA7 1 2 1U_0402_6.3V6K CA9 1 2 RA38 PVDD1 RA30 0_0402_5% @ 9 1 0_0402_5% RA39 Sense Pin 2 1 0_0603_5% @ CA60 @ 2 10U_0805_10V4Z 68 mA DVDD 0_0402_5% 2 RA18 1 SPK_L1 1 CA19 @ 10U_0805_10V4Z 2 @ 1 RA35 Ext. Mic/LINE IN B 2 CA7 10U_0805_10V4Z 2 2 MIC1_LINE1_R_L CA47 1 RA13 2 1 0_0603_5% 2 10U_0805_10V4Z place close to chip +PVDD2 1 0.1U_0402_16V4Z CA61 +AVDD 2 DVDD_IO RA36 2 SPKL+ RA11 35 mA 2 1 FBMH1608HM601-T 2 10U_0805_10V4Z +3VS_DVDD 0.1U_0402_16V4Z RA1 +3VS 1 10U_0805_10V4Z 2 2 place close to chip 2 placement near Audio Codec +5VALW CA43 1 CA2 D 0.1U_0402_16V4Z +DVDD_IO 2 1 FBMH1608HM601-T +3VS JA1 JUMP_43X39 @ 0.1U_0402_16V4Z 1 1 CA44 CA56 1 RA20 RA2 2 1 0_0603_5% 600 mA0.1U_0402_16V4Z 1 Speaker Connector 1 5 2 Title HDA-ALC269/HP/MIC Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 31 of 45 2 1 R737 0_0402_5% 2 1 2 2 1 C438 2 C439 2 2 0.1U_0402_16V4Z C441 1000P_0402_50V7K 1 1 1000P_0402_50V7K U19 1 <20> CLK_PCI_EC <5,20,27,28,29,30,33> PLT_RST# +3VL R378 47K_0402_5% 2 1 2 C444 <21> EC_SCI# <33> HDPLOCK ECRST# 1 2 3 4 5 7 8 10 CLK_PCI_EC PLT_RST# ECRST# EC_SCI# HDPLOCK 12 13 37 20 38 1 0.1U_0402_16V4Z 1 @ R380 1 @ R382 2 47K_0402_5% 2 47K_0402_5% EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 KSO2 to avoid EC entry ENE test mode C KSI[0..7] <16,33,34> KSI[0..7] KSO[0..17] <33,34> KSO[0..17] RP7 +3VL +3VS 1 2 3 4 8 7 6 5 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <15,37> <15,37> <17,33,34> <17,33,34> 2.2K_0804_8P4R_5% EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 CLK_PCI_EC/PCICLK PCIRST#/GPIO05 EC_RST#/ECRST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 <27,30> USB_CHG_EN# <34> ESB_CK <34> ESB_DAT <18> PCH_SUSPWRDN <13> INVT_PWM <5> FAN_SPEED1 <37,38> CPSETIN <27> E51_TXD <27> E51_RXD <34> ON/OFFBTN# <34> PWR_SUSP_LED# <33> NUM_LED# @ PLT_RST# 2 1U_0402_6.3V6K 1 C819 @ 1 C820 6 14 15 16 17 18 19 25 28 29 E51_TXD 30 E51_RXD 31 ON/OFFBTN# 32 PWR_SUSP_LED# 34 NUM_LED# 36 <21> EC_SMI# SUSP# 2 180P_0402_50V8J 0_0402_5% 0_0402_5% 0_0402_5% CRY1_EC CRY2_EC 122 123 1 <18> CLK_EC 1 2 R266 100K_0402_5% +3VALW 21 23 26 27 KB_LED EC_BEEP# SM_SENSE# ACOFF 63 64 65 66 75 76 BATT_TEMPA TMPTU1_SXP ADP_I ADP_V TMPTU2_SXP HDPACT 68 70 71 72 EN_DFAN1 IREF CHGVADJ 83 84 85 86 87 88 EC_MUTE# USB_EN# CAP_INT# H_PROCHOT#_EC TP_CLK TP_DATA 97 98 99 109 VGATE WOL_EN PWRME_CTRL# LID_SW# KB_LED <33> EC_BEEP# <31> SM_SENSE# <31> ACOFF <38> BATT_TEMPA <37> TMPTU1_SXP <27> ADP_I <37,38> ADP_V <38> TMPTU2_SXP <27> HDPACT <33> O D +3VS EN_DFAN1 <5> IREF <38> CHGVADJ <38> TMPTU1_SXP R754 1 10K_0402_5% 2 TMPTU2_SXP R757 1 10K_0402_5% 2 H_PROCHOT#_EC R758 1 SPI Device I/F SPI Flash ROM GPIO SPIDI/MISO SPIDO/MOSI SPICLK/GPIO58 SPICS# GPIO40 H_PECI/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 PWR_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI SPI_CLK SPI_CS# 73 74 89 90 91 92 93 95 121 127 CIR_IN EC_PECI R461 1 FSTCHG BATT_FULL_LED# CAPS_LED# BATT_CHG_LOW_LED# PWR_ON_LED# SYSON VR_ON ACIN_D 100 101 102 103 104 105 106 107 108 PCH_RSMRST# EC_LID_OUT# EC_ON TP_LED PM_PWROK BKOFF# HDPINT CAP_RST# SA_PGOOD 110 112 114 115 116 117 118 CEC_INT# UMA_ENBKL USB_OC#1 SLP_CHG# SUSP# PBTN_OUT# USB_OC#0 124 EC_MUTE# <31> USB_EN# <25> CAP_INT# <34> 10K_0402_5% 2 +3VL TP_CLK <34> TP_DATA <34> VGATE <5,18,43> WOL_EN <28> PWRME_CTRL# <16> LID_SW# <33> CEC_INT# 2 R53 1 100K_0402_5% CAP_INT# 1 R172 2 4.7K_0402_5% +5VS TP_CLK 1 R379 TP_DATA 1 R381 EC_SI_SPI_SO <33> EC_SO_SPI_SI <33> SPI_CLK <33> SPI_CS# <33> 2 4.7K_0402_5% 2 4.7K_0402_5% C +3VALW LID_SW# 2 47K_0402_5% 2 43_0402_1% H_PECI <5> FSTCHG <38> BATT_FULL_LED# <34> CAPS_LED# <33> BATT_CHG_LOW_LED# <34> PWR_ON_LED# <34> SYSON <30,40> VR_ON <43> SYSON PCH_RSMRST# <18> EC_LID_OUT# <17> EC_ON <16,34> TP_LED <34> PM_PWROK <5,18> BKOFF# <13> HDPINT <33> CAP_RST# <34> SA_PGOOD <41> 1 R5 1 R383 2 4.7K_0402_5% R341 330K_0402_5% 1 2 +3VL D21 ACIN_D 2 1 ACIN <18,34,38> CH751H-40PT_SOD323-2 CEC_INT# <15> UMA_ENBKL <19> USB_OC#1 <20,27,30> SLP_CHG# <27> SUSP# <16,27,35,40,42> PBTN_OUT# <5,18> USB_OC#0 <20,25> +3VALW SLP_CHG# R1428 2 1 10K_0402_5% B +EC_V18R C448 4.7U_0805_10V4Z KB930QF-A1_LQFP128_14X14 Cost Down Plan and cut in PVT 2010/09/22 SLP_CHG# R439 2 SUSP# R423 2 @ 1 10K_0402_5% 1 10K_0402_5% VR_ON R462 2 1 10K_0402_5% CIR +5VL 0.1U_0402_16V4Z 4 SLP_S5# R748 10K_0402_5% IN2 SN74AHC1G08DCKR_SC70-5 R389 CRY1 1 2 CRY2 Y4 2 2 C783 4.7U_0805_10V4Z CIR@ 4 Vout VCC GND A GND IRM-V538/TR1 CIR@ 8/12 Change C449, C450, Y4 from @ to mount Compal Electronics, Inc. Compal Secret Data Security Classification @ 32.768KHZ_12.5PF_Q13MC14610002 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 +5VL_CIR 1 CIR@ 2 R750 100_0805_5% 3 @ C450 18P_0402_50V8J OSC 4 OSC NC 2 NC 1 1 3 E51_TXD 2 100K_0402_5% 1 2 A 18P_0402_50V8J @ C449 U45 CIR_IN +5VL 5 2 100P_0402_50V8J 2 100P_0402_50V8J TV tuner temperature 10M_0402_5% @ 1 R342 1 C445 1 C446 ACIN_D 2 2 IN1 <5,37> C518 47P_0402_50V8J 1 <18> PM_SLP_S4# C1206 20P_0402_50V8J Q41 G 1 3 <18> PM_SLP_S5# U44 2 S 2N7002_SOT23 2 G P 5 C818 2 1 SDICS#/GPXIOA00 WOL_EN/SDICLK/GPXIOA01 ME_EN/SDIMOSI/GPXIOA02 LID_SW#/GPXIOD00 GND GND GND GND GND Close to EC EC_MUTE#/PSCLK1/GPIO4A USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_SMI#/GPIO08 EC_ON/GPXIOA05 GPIO0A EC_SWI#/GPXIOA06 GPIO0B ICH_PWROK/GPXIOA07 GPIO GPIO0C BKOFF#/GPXIOA08 GPO RF_OFF#/GPXIOA09 SUS_PWR_DN_ACK/GPIO0D INVT_PWM/PWM2/GPIO11 GPXIOA10 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 ON_OFF/GPIO18 ENBKL/GPXIOD02 SUSP_LED#/GPIO19 EAPD/GPXIOD03 GPI EC_THERM#/GPXIOD04 NUM_LED#/GPIO1A SUSP#/GPXIOD05 PBTN_OUT#/GPXIOD06 EC_PME#/GPXIOD07 XCLK1 XCLK0 V18R B CRY1 @ R991 CRY2 @ R992 R990 DAC_BRIG/DA0/GPO3C EN_DFAN1/DA1/GPO3D IREF/DA2/GPO3E DA3/GPO3F PS2 Interface SM Bus PM_SLP_S3# SLP_S5# EC_SMI# USB_CHG_EN#_R ESB_CK ESB_DAT PCH_SUSPWRDN INVT_PWM FAN_SPEED1 <18> PM_SLP_S3# H_PROCHOT# D @ EC_SMB_CK1/SCL0/GPIO44 EC_SMB_DA1/SDA0/GPIO45 EC_SMB_CK2/SCL1/GPIO46 EC_SMB_DA2/SDA1/GPIO47 9/2 Add CPSETIN function in EC_GPIO15 by Power demand R1442 0_0402_5% 1 2USB_CHG_EN#_R BATT_TEMP/AD0/GPI38 BATT_OVP/AD1/GPI39 ADP_I/AD2/GPI3A AD3/GPI3B AD Input AD4/GPI42 AD5/GPI43 DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSO1 PWM0/GPIO0F BEEP#/PWM1/GPIO10 FANPWM0/GPIO12 ACOFF/FANPWM1/GPIO13 PWM Output LPC & MISC KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 +3VL GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ# LPC_FRAME#/LFRAME# LPC_AD3/LAD3 LPC_AD2/LAD2 LPC_AD1/LAD1 LPC_AD0/LAD0 AGND 2 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 69 1 11 24 35 94 113 C443 22P_0402_50V8J @ H_PROCHOT#_EC BATT_TEMPA <21> GATEA20 <21> KB_RST# <16,33> SERIRQ <16,33> LPC_FRAME# <16,33> LPC_AD3 <16,33> LPC_AD2 <16,33> LPC_AD1 <16,33> LPC_AD0 2 D 0.1U_0402_16V4Z VCC VCC VCC VCC VCC VCC CLK_PCI_EC R377 10_0402_5% @ <43> VR_HOT# C442 1 2 2 C440 67 0.1U_0402_16V4Z For EMI 0.1U_0402_16V4Z 1 C437 AVCC 1 9 22 33 96 111 125 0.1U_0402_16V4Z 1 C436 1 +3VL 2 3 +3VL 1 4 3 5 3 2 Title LPC-EC-KB930 Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 32 of 45 SPI Flash (256KB) Place the PAD under DDR DIMM. LPC Debug Port Lid SW +3VS H7 +3VL 5 7 4 PLT_RST# <5,20,27,28,29,30,32> 8 3 LPC_AD2 <16,32> 9 2 LPC_AD0 <16,32> 10 1 CLK_PCI_DDR 20mils 1 U22 3 W 7 HOLD <32> SPI_CS# SPI_CS# 1 S SPI_CLK 6 <32> SPI_CLK <32> EC_SO_SPI_SI C EC_SO_SPI_SI 5 D VSS +3VALW 2 1 EC_SI_SPI_SO 2 VDD EC_SI_SPI_SO <32> W 25X10BVSNIG_SO8 LID_SW # <32> C453 0.1U_0402_16V4Z <16,32> LPC_FRAME# 1 C452 10P_0402_50V8J <20> DEBUG_PAD 2 R393 22_0402_5% @ 1 2 <16,32> LPC_AD1 3 VOUT 2 0_0402_5% <16,32> LPC_AD3 U21 APX9132ATI-TRL_SOT23-3 Q 1 R392 <16,32> SERIRQ 4 2 VCC GND 8 2 1 C451 0.1U_0402_16V4Z @ 6 SPI_CLK 1 R394 2 10_0402_5% 2 1 C454 2 10P_0402_50V8J C457 22P_0402_50V8J 1 @ For EMI 8/30 Change U22 From SA00003GK00 to SA00003GM10 due to EOL of SA00003GK00 For EMI 9/03 Change U22 change to SA00003FL10 1 2 3 4 GND GND Q38 KBL@ AO3413_SOT23-3 D S 3 1 +5VS_LED 1 1 RG2 @ 1 3 S 2 G <32> KB_LED KSO16 KSO17 KSO2 KSO1 KSO0 KSO4 KEYBOARD CONN. KSO3 KSO5 KSI[0..7] KSO[0..17] KSI[0..7] <16,32,34> KSO14 KSO[0..17] <32,34> KSO6 KSO7 JKB 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ACES_88170-3400 @ JKB34 KSO16 1 2 R372 300_0402_5% +3VS KSO13 KSO8 KSO17 KSO9 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4 2 1 CAPS_LED# R376 300_0402_5% NUM_LED# KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 +3VS CAPS_LED# <32> NUM_LED# <32> +5VS DG1 1 Close to JKB Q52 2N7002_SOT23-3 KBL@ CAPS_LED# NUM_LED# 1 C401 1 C402 1 C404 1 C405 1 C406 1 C407 1 C408 1 C409 1 C410 1 C411 1 C412 1 C413 1 C415 1 C416 1 C417 1 C418 1 C419 1 C420 1 C421 1 C422 1 C423 1 C424 1 C425 1 C427 1 C429 1 C431 1 C433 1 C435 SELF_TEST 1 +3VS_HDP 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J CG12 1U_0402_6.3V6K GSENSOR@ 1 UG3 2 +3VS_HDP GSENSOR@ +3VS_HDP CH751H-40PT_SOD323-2 2 1 GSENSOR@ CG13 1U_0402_6.3V6K GSENSOR@ VOUT 5 2 1 VIN 2 GND 3 SHDN# BP 4 G9191-330T1U_SOT23-5 CG14 2 1 Vdd1 Vdd2 4 6 8 ST PD FS 9 Rev 0_0603_5% For EMI D 2 +3VS ACES_85201-0405N @ C836 0.1U_0402_16V4Z 2 KBL@ 2 12 +5VS_LED 2 2 G R587 10K_0402_5% KBL@ 1 2 3 4 5 6 +3VS_HDP GSENSOR@ Voutx Vouty Voutz 3 5 7 NC1 NC2 NC3 NC4 NC5 10 11 14 15 16 GND1 GND2 1 13 VOUTXCG1 VOUTYCG2 VOUTZCG3 GSENSOR@ 0.033U_0402_16V7K 1 2 0.033U_0402_16V7K 1 2 0.033U_0402_16V7K 1 2GSENSOR@ GSENSOR@ Reserve for 2nd Source +3VS_HDP CG9 0.1U_0402_16V4Z UG4 @ 2 1VOUTX2 CG10 0.1U_0402_16V4Z XOUT @ 2 1VOUTY3 CG11 0.1U_0402_16V4ZYOUT @ 2 1VOUTZ4 ZOUT TSH352TR LGA 16P Place UG1 and UG4 on TOP Layer 9 +3VS_HDP @ 0.22U_0402_10V4Z SELF_TEST 7 10 13 @ VDD 0G-DET SLEEP# G-SELECT ST 6 NC NC NC NC NC 1 8 11 12 14 VSS 5 MMA7360LR2_LGA14 UG5 1 <17,32,34> EC_SMB_CK2 P1_6/CLK0/SSI01 11 P1_5/RXD0/CNTR01/INT11# 12 P1_4/TXD0 13 P1_3/KI3#/AN11/TZOUT 14 P3_5/SSCK/SCL/CMP1_2 HDPACT <32> 2 +5VS UG1 G-Sensor JBLG SELF_TEST +3VS_HDP HDPINT 1 4.7K_0402_5% 3 RESET# RG4 2 GSENSOR@ 1GXOUT 4.7K_0402_5% 4 XOUT/P4_7 1GXIN 4.7K_0402_5% RG6 2 1 4.7K_0402_5% GSENSOR@ RG7 2 1 1K_0402_5% GSENSOR@ 1 CG7 0.1U_0402_16V4Z GSENSOR@ 2 5 VSS/AVSS 6 XIN/P4_6 P4_2/VREF 16 VOUTX VOUTY VCC/AVCC P1_1/KI1#/AN9/CMP0_1 17 8 MODE P1_0/KI0#/AN8/CMP0_0 18 9 P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 19 P3_4/SCS#/SDA/CMP1_1 20 1 P1_7/CNTR00/INT10# CG8 GSENSOR@ R5F211B4D34SP 0.1U_0402_16V4Z 2 2010/09/03 Deciphered Date HDPLOCK <32> VOUTZ 15 7 10 RG9 47K_0402_5% GSENSOR@ P1_2/KI2#/AN10/CMP0_2 RG10 47K_0402_5% 2 1 GSENSOR@ +3VS_HDP 1 2 CG6 0.1U_0402_16V4Z GSENSOR@ EC_SMB_DA2 <17,32,34> GSENSOR@ Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date P3_7/CNTR0#/SSO/TXD1 RG3 2 GSENSOR@ RG5 2 GSENSOR@ <32> HDPINT 2 1 Keyboard LED 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SPI ROM/LID/Debug/KB/G-Sen Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 33 of 45 5 4 3 +3VL Caps Sensor/Light Sensor Conn. 1 Touchpad & Light Pipe Connector 2 Power Button 2 JCS C458 0.1U_0402_25V6 @ 3 2 4 <17,32,33> EC_SMB_CK2 <17,32,33> EC_SMB_DA2 1 SW3 1 2 <16,32> EC_ON 2 2 <32> ESB_DAT <32> ESB_CK <32> CAP_INT# <32> CAP_RST# Q7A 2N7002DW-T/R7_SOT363-6 ESB_DAZ ESB_CKZ CAP_INT# CAP_RST# R396 10K_0402_5% 1 2 3 4 5 6 7 8 9 10 11 12 D For EMI request SW_L JTPL +5VS <32> TP_CLK <32> TP_DATA 2 390_0402_5% +5VALW ESB_DAZ @ 1 100_0402_5% 100P_0402_50V8J ESB_CKZ @ 1 1 D83 ACES_85201-0405N @ ON/OFFBTN# 2 R428 <16,32,33> KSI6 <32,33> KSO0 2 1 R427 2 C260 @ 2 3 1 R22 4 @ D 1 2 3 4 5 6 7 8 9 10 GND GND Q7B SW4 SW_R 1 3 2 4 SMT1-05_4P P-TWO_161021-10021 5 <32> TP_LED C261 @ 2 3 SMT1-05_4P 2N7002DW-T/R7_SOT363-6 4 ON/OFFBTN# TP_LED# KSI6 KSO0 For EMI PWR_ON_LED# 1 2 3 4 5 6 7 8 9 10 11 12 SW_L SW_R 6 5 SMT1-05-A_4P JPOWER 1 1 2 2 3 3 4 4 5 G1 6 G2 1 2 P-TWO_161021-10021 1 BTM side SW1 1 2 3 4 5 6 7 8 9 10 GND GND 6 5 ON/OFFBTN# <32> TOP side 1 +5VALW +3VL FBMA-11-100505-301T_0402 +3VS L13 1 2 L14 1 2 FBMA-11-100505-301T_0402 51_ON# <36> ON/OFFBTN# 6 1 100K_0402_5% @ 6 5 R395 For debug 1 PWR_ON_LED# 3 100_0402_5% 100P_0402_50V8J PJSOT05C_SOT23-3 8/30 Change SW1, SW4 to SN100002Y00 Screw Hole 2N7002_SOT23-3 C WIMAX_LED_GND# H13 H_3P0 @ H14 H_3P0 @ H_3P0 @ 1 1 H12 H_3P0 @ 1 H11 H_3P0 @ 1 H10 H_3P0 @ 1 1 1 H9 H_3P0 @ 1 H8 H_3P0 @ @ 6 3 1 H1 4 H26 H_2P7x3P2N @ Q156A 2N7002DW-T/R7_SOT363-6 WIMAX@ H_2P7N @ C 1 R819 2 1 10K_0402_5% WIMAX@ +5VS H6 H_3P0 @ LED_WIMAX# <27> 1 3 5 2 G 1 S Q32 D DC_IN R506 WIMAX_LED_GND# 1 2 0_0402_5% 2 WiMAX LED ACIN <18,32,38> 1 H5 DC-IN LED Q156B 2N7002DW-T/R7_SOT363-6 WIMAX@ +5VS 4 Q9B 3 4 H22 H_4P2x4P7 @ H16 H_3P3 @ H23 H_4P2x4P7 @ H_4P7 @ H17 H_3P3 @ H_3P3 @ 1 H21 H_4P2 @ 1 LOGO_LED# 1 H20 1 D22 HT-SV116BP_WHITE 1 2 2 R774 120_0402_5% 1 3 1 Q9A 2N7002DW-T/R7_SOT363-6 1 6 H15 CPU LOGO_LED <21> 1 2 Logo LED 1 HDD_LED# 2 R404 1 10K_0402_5% 5 +5VS MINI CARD -- 3G SATA_LED# <16> 5 HDD LED 2N7002DW-T/R7_SOT363-6 Q6B 2N7002DW-T/R7_SOT363-6 @ 1 2 R50 0_0402_5% 1 2 2 R776 120_0402_5% HT-SV116BP_WHITE 1 MINI CARD -- WLAN D20 H18 H19 H_3P3 @ 1 1 H_3P3 @ PCB Fedical Mark PAD <21> WL_BT_LED# <32> PWR_ON_LED# <32> PWR_SUSP_LED# <29> CR_LEDCON# <32> BATT_FULL_LED# <32> BATT_CHG_LOW_LED# WIMAX_LED_GND# WL_BT_LED# DC_IN PWR_ON_LED# PWR_SUSP_LED# HDD_LED# CR_LEDCON# BATT_FULL_LED# BATT_CHG_LOW_LED# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 DC_IN @ 1 2 3 1 6 2 5 3 4 6 WL_BT_LED# 5 @ B FD4 @ ISPD D85 JLED +5VALW +5VS @ FD3 1 @ LED/B Connector FD2 1 FD1 1 B +5VALW U2 ZZZ Q65R1@ 4 IP4223CZ6_SO-6-6 PCH PCB LA-6832P D86 GND GND 13 14 ACES_85201-1205N WIMAX_LED_GND# 1 2 PWR_ON_LED# 3 1 6 2 5 3 4 6 PWR_SUSP_LED# U2 5 4 Q67R1@ PJP1 45@ +5VALW HDD_LED# IP4223CZ6_SO-6-6 PCH U2 A PJP1 Q67R3@ A For ESD Demand 2010/10/01 PCH Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR/Cap./TP/LED/LP/LS/Screw Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Thursday, October 07, 2010 Sheet 1 34 of 45 A B C +3VALW TO +3VS +3VALW +3VS D +5VALW TO +5VS +1.5V to +1.5VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW Vgs=10V,Id=9A,Rds=18.5mohm E +1.8VS +1.5V +5VS +1.5VS C469 2 2 1 1 2 SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R414 820K_0402_5% D Q12A S Q12B 1 Q190 SUSP 2 G 2N7002_SOT23-3 3 1 3 1 1 4 @ 1 1 R408 1 R411 2 +VSB 220K_0402_5% FDS6676AS_SO8 470_0805_5% 2 6 2 1 C821 R470 470_0805_5% 1 C464 C463 1U_0402_6.3V6K 2 Q11B SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 @ 2 1 2 3 4 S S S G C470 2 470_0805_5% Q11A 1 C822 D D D D 0.1U_0402_25V6 R413 200K_0402_5% @ +VSB 2 8 7 6 5 4.7U_0805_10V4Z C468 2 R407 0.1U_0402_16V4Z C467 2 1 2 1 R410 2 47K_0402_5% 3 1 1 6 SI4800BDY_SO8 1 Q31 For EMI 0.1U_0402_16V4Z Q10B SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 C461 1U_0402_6.3V6K Vgs=10V,Id=14.5A,Rds=6mohm 4 Q10A 1 2 3 4 1 +VSB S S S G 1 R406 D D D D 2 R412 330K_0402_5% 2 2 1 R409 2 47K_0402_5% 1 Q30 8 7 6 5 0.01U_0402_25V7K 6 1 C466 1 C465 2 1 2 1 0.022U_0402_25V7K 4.7U_0805_10V4Z SI4800BDY_SO8 1 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 C460 C459 1U_0402_6.3V6K 2 1 2 3 4 470_0805_5% S S S G 3 1 1 D D D D 4 1 Q29 8 7 6 5 2 4.7U_0805_10V4Z +5VS 4.7U_0805_10V4Z 1 C462 +3VALW +5VALW +0.75VS +1.05VS_VCCP 2 2 2 2 For S3 CPU Power Saving R425 100K_0402_5% 1 R422 100K_0402_5% <42> R421 22_0805_5% R468 470_0805_5% 1 1 S D S 2 G 2 Q60 2N7002_SOT23-3 1 2N7002DW-T/R7_SOT363-6 1 Q189 SUSP 2 G 2N7002_SOT23-3 2 SUSP# 3 1 D Q6A <16,27,32,40,42> 3 Q44A 2N7002DW-T/R7_SOT363-6 SUSP <5,9,42> SUSP Q44B 2N7002DW-T/R7_SOT363-6 5 6 0.75VR_EN 2 100K_0402_5% 4 1 R158 6 <41,42> VCCPPWRGD 2 1 3 0.75VR_EN# SUSP 1 2 +5VS_ODD 2 +5VS TO +5VS_ODD 6 1 R457 470_0805_5% Q53A 2 3 +5VS +5VS D 2 47K_0402_5% 2N7002_SOT23-3 Q51 2 Q45 2 2 1 AO3413_SOT23 C217 0.01U_0402_25V7K 1 S 1 PJ28 JUMP_43X79 @ +5VS_ODD 1 1 2 R440 1 3 Vgs=-4.5V,Id=3A,Rds<97mohm 3 2 G <21> ODD_EN# C471 0.1U_0402_16V7K 1 1 2 2 R441 10K_0402_5% G +3VS D 1 ODD_EN# 2N7002DW-T/R7_SOT363-6 S 3 1 1 C679 4.7U_0805_10V4Z @ 2 C680 1U_0402_6.3V6K 2 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC-DC INTERFACE Size Document Number Rev 0.2 PHQAA LA-6832P M/B Date: Sheet Thursday, October 07, 2010 E 35 of 45 A B C D 1 2 PR1 1K_1206_5% VIN DC_IN_S1 1 @ PJP1 DC_IN_S2 2 PD1 PL1 SMB3025500YA_2P 1 2 PF1 DC301001M80 2 VIN N3 1 1 2 B+ PR2 1K_1206_5% RLS4148_LL34-2 2 PR3 1K_1206_5% 1 1 PR38 511K_0402_1% @ 2 2 3 - 2 O G 2 2 + LM393DG_SO8 +5VALW P PQ2 DTC115EUA_SC70-3 3 P PU2A 1 22K_0402_1% +3VALW P 1 1 PC5 0.1U_0603_25V7K 2 2 2 PC6 0.22U_0603_25V7K 2 1 2 N1 PR11 <34> 51_ON# 2 3 VS 1 PR10 100K_0402_1% <38> 2 1 2 1 1 3 PACIN <38> S 1 N1 1 2 G 8 2 RLS4148_LL34-2 PQ1 SSM3K7002FU_SC70-3 4 BATT+ 2 D PR9 68_1206_5% 2 BSS84_SOT23-3 PD4 PR39 47K_0402_1% 2 1 1 PR8 68_1206_5% PQ4 PC14 1000P_0402_50V7K 1 1 1 PC15 1000P_0402_50V7K @ PR7 66.5K_0402_1% PR35 255K_0402_1% PR36 150K_0402_1% 2 RLS4148_LL34-2 1 PR6 34K_0402_1% 1 PC13 1000P_0402_50V7K PD3 2 1 6 2 LM393DG_SO8 2 5 - 6251VREF + O 1 7 1 2 3 P 2 <38> ACON G <39> EN0 4 VIN PU2B 8 N1 PD2 RB715F_SOT323-3 1 VL PR5 2.2M_0402_5% 2 1 2 PR4 100K_0402_1% 1 2 2 1 1 1 PC4 100P_0402_50V8J 2 2 SINGA_2DW -0005-B03 2 - 4 PC3 1000P_0402_50V7K 3 1 - 1 PC2 100P_0402_50V8J 2 2 + 1 1 PC1 1000P_0402_50V7K 10A_125V_451010MRL + @ PJ76 PJ332 1 1 +3VALW +0.75VSP 2 2 1 1 +0.75VS JUMP_43X79 JUMP_43X118 (5A,200mils ,Via NO.= 10) OCP=8.6A (1A,40mils ,Via NO.= 2) +1.5VP 2 @ PJ152 1 1 2 +1.5V JUMP_43X118 +5VALW P 2 @ PJ352 2 1 1 +5VALW +VCCSAP JUMP_43X118 3 2 @ PJ452 2 1 1 (16A,640mils ,Via NO.= 32) +VCCSA JUMP_43X118 (6A,240mils ,Via NO.= 12) (5A,200mils ,Via NO.= 10) OCP=7.9A @ PJ402 3 2 2 1 1 JUMP_43X118 @ PJ182 +1.8VSP 2 2 1 1 @ PJ333 +1.8VS +3VLP 2 2 1 @ PJ403 1 +3VL JUMP_43X118 JUMP_43X39 (1.65A,70mils ,Via NO.= 4) OCP=4.2A (100mA,40mils ,Via NO.= 2) @ PJ2 +VSBP 2 2 1 +1.05VS_VCCPP 2 +VSB VL 2 2 1 1 1 1 +1.05VS_VCCP JUMP_43X118 2 +5VL JUMP_43X39 JUMP_43X39 (120mA,40mils ,Via NO.= 1) (100mA,40mils ,Via NO.= 2) RTC Battery (17A,680mils ,Via NO.=34) @ PJ353 1 2 - @ PJ502 2 1 1 @ 2 + PBJ1 1 +GFX_COREP 2 @ PJ503 1 1 2 PR13 PR12 1 2 560_0603_5% JUMP_43X118 1 2 +RTCBATT 560_0603_5% MAXEL_ML1220T10 +GFX_CORE JUMP_43X118 SP093MX0000 (33A,1320mils ,Via NO.=66) OCP=40A ACIN Precharge detector Min. typ. Max. H-->L 14.42V 14.74V 15.23V L-->H 15.39V 15.88V 16.39V 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/13 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title DCIN/VIN DECTOR Size Document Number Rev 0.1 NHQAA LA-6831P M/B Date: Thursday, October 07, 2010 D Sheet 36 of 58 4 A B C VMB 1 @ PJP2 1 2 PH1 under CPU botten side : CPU thermal protection at 95 degree C Recovery at 56 degree C BATT+ 15A_65V_451015MRL 1 BATT_P4 BATT_P5 EC_SMDA EC_SMCA PC8 0.01U_0402_25V7K 1 PC7 1000P_0402_50V7K 2 PR14 1K_0402_1% VL 1 1 2 SUYIN_200045MR009G171ZR 2 GND GND GND GND BATT_S1 1 2 3 4 5 6 7 8 9 1 10 11 12 13 1 PL2 SMB3025500YA_2P 1 2 PF2 1 2 3 4 5 6 7 8 9 D PR15 19.6K_0402_1% 2 2 1 PR18 8.66K_0402_1% PH1 +3VLP 100K_0402_1%_NCP15W F104F03RC 1 PR19 1K_0402_1% 2 <39> VS_ON 1 1 8 GND RHYST1 7 3 OT1 TMSNS2 6 4 OT2 RHYST2 5 2 2 PR22 19.6K_0402_1% 1 D @ PQ7 SSM3K7002FU_SC70-3 2 G 1 3 2 PR28 8.66K_0402_1% G718TM1U_SOT23-8 S D PR27 8.66K_0402_1% 2 G S 3 EC_SMB_DA1 <15,32> VCC TMSNS1 2 2 BATT_TEMPA <32> 1 2 PR29 100K_0402_1% <5,32> H_PROCHOT# PR21 100_0402_1% 1 PR20 100_0402_1% PU1 +3VS 2 2 2 2 1 1 ADP_I <32,38> 1 3 PR16 6.49K_0402_1% 2 1 1 2 1 PD5 2 PJSOT24C_SOT23-3 3 2 PC9 0.1U_0603_25V7K PD6 PJSOT24C_SOT23-3 1 PQ219 2N7002W -T/R7_SOT323-3 2 EC_SMB_CK1 <15,32> 1 PR30 4.99K_0402_1% PQ5 BSS84_SOT23-3 3 B+ 1 +VSBP VL 1 2 2 PR24 1 PR25 100K_0402_1% 1 1 D CPSETIN <32,38> S 3 PC11 @ 0.1U_0603_25V7K 2 G 2 @ PC16 .1U_0402_16V7K 1 2 @ PR31 8.66K_0402_1% 2 1 2 VL PC10 0.22U_0603_25V7K 3 2 1 PR23 100K_0402_1% 3 PQ220 2N7002W -T/R7_SOT323-3 2 1 D 3 1 22K_0402_1% S PR26 1 <18,39> POK 2 PQ6 SSM3K7002FU_SC70-3 2 G @ PC12 .1U_0402_16V7K 2 1 0_0402_5% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/13 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number Rev 0.1 NHQAA LA-6831P M/B Date: Thursday, October 07, 2010 D Sheet 37 of 58 CSIN 1 2 DCIN 2 ACSET ACPRN 23 3 EN CSON 22 4 CELLS CSOP 21 5 ICOMP CSIN 20 PR2312 3 1 <32,37> CPSETIN D 3 PQ218 2N7002W -T/R7_SOT323-3 17 DH_CHG 6251aclim 2 10 CHLIM BOOT 16 2 3 2 BST_CHG 1 2 0_0603_5% S 2 G 11 VDDP 15 6251VDDP VADJ LGATE 14 DL_CHG GND PGND 13 ACLIM 12 1 5 6 7 8 3 2 PL202 10UH_MSCDRI-104A-100M-E_4.6A_20% CHG 1 2 2 0.1U_0603_25V7K PD202 RB751V-40_SOD323-2 1 2 6251VDD PR233 PC221 4.7U_0603_6.3V6M BATT+ 4 2 PQ202 AO4466L_SO8 PC205 BST_CHGA 2 1 PR235 1 @ PR206 4.7_1206_5% 3 0.02_1206_1% 4 @ PC206 680P_0603_50V7K PC204 10U_1206_25V6M 2 1 UGATE S 1 VREF 2 2_0402_5% 24K_0402_1% PR223 20K_0402_1% 2 1 1 1 PC216 2 2 1 6251VREF 1 PR222 3 <32> ACOFF PR221 120K_0402_1% PHASE LX_CHG PR205 9 <36> ACON PQ213 DTC115EUA_SC70-3 ACOFF 2 8 ICM 18 <36> 6251VREF .1U_0402_16V7K PR234 12.4K_0402_1% 2 1 <32> IREF PR220 154K_0402_1% 2 1 19 D 2 G PQ216 2N7002W -T/R7_SOT323-3 2 PC215 1 2 0.01U_0402_25V7K PACIN PR211 22K_0402_5% 1 2 PC220 0.1U_0603_25V7K 1 PR232 CSIP VCOMP PQ201 AO4466L_SO8 1 <32,37> ADP_I 7 PACIN 2 PR219 1 2 47K_0402_1% PC222 0.1U_0402_25V6 4 3 2 1 6 2 10K_0402_1% 2 CSOP 5 6 7 8 1 0.01U_0402_25V7K 1 CSON 1 20_0402_5% 2 S 6800P_0402_25V7K PR218 2 1SS355_SOD323-2 PR229 20_0402_5% 1 2 PC219 0.047U_0402_16V7K 1 2 PR230 20_0402_5% 1 4 PC214 1 2 VIN PD10 PQ215 DTC115EUA_SC70-3 1 1 PC213 1 2 2 D 5 G 1 3 PQ212A DMN66D0LDW -7_SOT363-6 PR238 200K_0402_1% 1 2 0.1U_0603_25V7K ACPRN 3 1 S 2 PQ212B DMN66D0LDW -7_SOT363-6 VIN ACOFF 2 1SS355_SOD323-2 1 2 VDD 24 1 PD9 1 1 PC217 1000P_0402_25V8J 2 1 1 1 6251_EN D 2 G PR228 14.3K_0402_1% PC218 DCIN 2 1 1 2 2 100K_0402_1% ACSETIN 2 47K_0402_1% PR237 10K_0402_1% 1 1 2 6251VDD 1 1 1 1 1 PU200 PR217 PR213 150K_0402_1% PQ211 DTC115EUA_SC70-3 PR227 10_1206_5% 2 PR216 10K_0402_1% 2 1 <32> FSTCHG 2 6 PC212 2.2U_0603_6.3V6K 2 PD201 RB751V-40_SOD323-2 2 1 ACSETIN 1 PC203 10U_1206_25V6M 2 1 2 1 2 3 PC210 0.1U_0603_25V7K 2 1 2 PQ210 DTA144EUA_SC70-3 PR226 191K_0402_1% PR236 4 4 CSIP VIN PR212 200K_0402_1% AO4435_SO8 8 7 6 5 1 2 3 2 3 PC211 5600P_0402_25V7K 1 PR210 47K_0402_1% @ PQ207 CHG_B+ PL201 HCB2012KF-121T50_0805 1 2 3 2 1 2 AO4435_SO8 8 7 6 5 PC202 10U_1206_25V6M 2 1 B+ PR215 0.02_1206_1% 4 1 PC233 4.7U_0805_25V6-K 2 1 8 7 6 5 PQ208 1 2 3 PC232 4.7U_0805_25V6-K 2 1 1 2 3 4 1 P3 PQ204 AO4407A_SO8 1 2 3 @ PC231 4.7U_0805_25V6-K 2 1 P2 PQ203 AO4435_SO8 8 7 6 5 VIN @ D 4 @ PC209 10U_1206_25V6M 2 1 C PC208 10U_1206_25V6M 2 1 B PC207 10U_1206_25V6M 2 1 A @ 4.7_0603_5% ISL6251AHAZ-T_QSOP24 PR224 1 2 15.4K_0402_1% 3 2 <32> CHGVADJ PR225 31.6K_0402_1% 6251VDD PR240 47K_0402_1% ACIN <18,32,34> PR246 309K_0402_1% PR247 10K_0402_1% 1 2 2 PR241 10K_0402_1% 1 2 2 2 PR242 10K_0402_1% 1 1 1 1 VIN 1 PACIN <36> 1 1 PR248 PR243 14.3K_0402_1% PC223 .1U_0402_16V7K 47K_0402_1% 2 2 2 2 ACPRN ADP_V <32> 1 PQ214 DTC115EUA_SC70-3 CP mode Iada=0~3.42A(65W) 4 CP= 92%*Iada; CP=3.147A Vaclim=1.08V(65W) PR222=75k PR223=20k PR45=0.02 Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A Vaclim=0.736V(75W) PR222=24k PR223=20k PR45=0.02 Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A Vaclim=0.736V(90W) PR222=53.6k PR223=20k PR45=0.015 Iada=0~6.316A(120W) CP= 92%*Iada; CP=5.81A Vaclim=0.736V(120W) PR222=8.25k PR223=26.7k PR45=0.015 A 3 CC=0.25A~3A Vin Detector IREF=1.016*Icharge IREF=0.254V~3.048V VCHLIM need over 95mV High 18.089V Low 17.44V - 4 CHGVADJ=(Vcell-4)*9.445 Vcell 4V CHGVADJ 0V Issued Date 4.2V 1.882V 4.35V 3.2935V B Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/25 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C Title CHARGER Size Document Number Custom Date: Rev 0.1 NHQAA LA-6831P M/B Thursday, October 07, 2010 D Sheet 38 of 58 5 4 3 2 1 2VREF_8205 D 2 PC363 1U_0603_10V6K 1 D +3VLP 1 PR365 19.1K_0402_1% 1 2 PR337 150K_0402_1% 1 2 RT8205_B+ PR357 150K_0402_1% 1 2 1 2 PR363 20K_0402_1% 1 2 ENTRIP1 B+ PR364 30K_0402_1% 1 2 ENTRIP2 RT8205_B+ PL331 HCB2012KF-121T50_0805 PR362 13K_0402_1% 1 2 UG_3V 10 UGATE2 UGATE1 21 PR355 BST_5V 1 2 0_0603_5% UG_5V LX_3V 11 PHASE2 PHASE1 20 LX_5V LG_3V 12 LGATE2 LGATE1 19 LG_5V PC355 2 0.1U_0603_25V7K AO4466L_SO8 PL352 4.7UH_SIL1045R-4R7PF_6.3A_30% 1 2 2 D S 5 G 1 PR361 2 2VREF_8205 2 1 S RT8205_B+ PQ360B DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 2 VL PC364 4.7U_0805_10V6K B Ipeak=3.98A Imax=2.8A F=300KHz Total Capacitor ??uF, ESR ??mohm 1 2 + PC356 @ 680P_0603_50V7K 2 1 G 100K_0402_5% 1 D PQ360A 3 ENTRIP2 4 ENTRIP1 1 2 1 PQ352 TPS51125ARGER_QFN24_4X4 PC352 330U_6.3V_M 1 NC 4 AO4712L_SO8 2 PC362 1U_0402_6.3V6K 6 B Ipeak=6.97A Imax=4.88A F=375KHz Total Capacitor ??uF, ESR ??mohm +5VALWP PR356 @ 4.7_1206_5% 18 17 16 EN 1 5 6 7 8 22 VREG5 23 BOOT1 VIN PGOOD BOOT2 GND VREG3 9 3 2 1 FB1 REF FB2 TONSEL 2 1 3 2 4 5 6 ENTRIP2 ENTRIP1 POK <18,37> 2 B+ 24 3 2 1 AO4712L_SO8 4 VO1 8 13 @ PC336 680P_0603_50V7K 2 PQ351 C BST_3V PR360 499K_0402_1% 1 2 1 330U_6.3V_M 1 2 3 + VO2 <36> EN0 4 2 1 PC332 PQ332 @ PR336 4.7_1206_5% 7 SKIPSEL 1 +3VALWP 8 7 6 5 PL332 4.7UH_SIL1045R-4R7PF_6.3A_30% 1 2 PR335 1 2 0_0603_5% 2 P PAD 15 1 2 3 PC335 0.1U_0603_25V7K 1 25 14 4 4.7U_0805_10V6K PC361 2 1 8 7 6 5 2 PQ331 AO4466L_SO8 C PU330 5 6 7 8 PC366 10U_1206_25V6M 1 PC360 10U_1206_25V6M PC365 0.1U_0603_25V7K PR370 VL 2 1 1 100K_0402_1% <37> VS_ON PR371 3 0.01U_0402_16V7K A @ PC370 2 1 2 PR372 1 2 42.2K_0402_1% 1 2 100K_0402_1% VS PQ361 DTC115EUA_SC70-3 A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/13 Issued Date Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 3VALWP/5VALWP Size Document Number Rev NHQAA LA-6831P M/B Date: Thursday, October 07, 2010 Sheet 1 39 of 0.1 58 A B C D PL151 HCB2012KF-121T50_0805 4 PR160 1 2 VCC FB 6 PGOOD 14 BST TP 1 5 LX 12 LX_1.5V ILIM 11 VFB=0.75V VDD DL 9 1 @ PC228 10U_1206_25V6M 2 1 @ PC225 10U_1206_25V6M 2 1 2 1 +1.5VP PR157 1 2 10K_0402_1% PQ152 AO4712L_SO8 +5VALW @ PR156 4.7_1206_5% 1 DL_1.5V + PC152 330U_6.3V_M 4 2 Ipeak=19.6A Imax=13.72A F=294KHz Total Capacitor ??uF, ESR ??mohm 2 PGND 8 AGND 7 2 PC161 4.7U_0603_6.3V6K 2 0.1U_0603_25V7K 10 1 100_0603_5% DH_1.5V 1 OUT 4 13 DH 1 PL152 1.8U_D104C-919AS-1R8N_9.5A_30% PC155 1 2 BST_1.5V-1 2 3 PR161 +5VALW 2 G5603RU1U_TQFN14_3P5X3P5 1 TON PR155 0_0603_5% PC162 4.7U_0805_10V6K 3 2 1 2 EN_SKIP PU150 15 1 2 PC160 @ .1U_0402_16V7K 1 B+ 3 2 1 BST_1.5V 5 6 7 8 2 0_0402_5% 1 1 <30,32> SYSON 1 PC164 4.7U_0805_25V6-K 2 1 PR164 255K_0402_1% 1 2 PQ151 AO4466L_SO8 5 6 7 8 PC163 4.7U_0805_25V6-K 2 1 2 @ PC165 680P_0402_50V7K 1.5_B+ 1 @ PC156 680P_0603_50V7K 2 2 2 PR162 1 2 1 10K_0402_1% 2 PR163 10K_0402_1% PU180 SY8033BDBC_DFN10_3X3 @ PR182 499K_0402_1% PC186 0.1U_0402_10V7K FB_1.8V PR184 10K_0402_1% 1 3 2 2 PC185@ 2 1 1 0_0402_5% PR183 20K_0402_1% 2 PR186 2 NC NC 1 2 EN_1.8V 1 PR181 7 TP 1 11 <16,27,32,35,42> SUSP# FB=0.6Volt PC183 22U_0805_6.3VAM 6 1 FB 2 EN LX PC182 22U_0805_6.3VAM 5 2 PC184 22U_0805_6.3VAM Ipeak=1.308A ILIM = 4A F=1MHz Total Capacitor ??uF, ESR ??mohm +1.8VSP PC187 68P_0402_50V8J 2 1 SVIN 3 LX_1.8V 1 PVIN 8 2 1 9 LX 1 JUMP_43X39 PVIN 2 10 1 1 2 1 4.7_1206_5% 2 680P_0603_50V7K 2 PG +5VALW PL182 1UH_FMJ-0630T-1R0 HF_11A_20% 1 2 4 @ PJ181 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/25 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title +1.5VP/+1.8VSP Size Document Number Custom Date: Rev 0.1 NHQAA LA-6831P M/B Thursday, October 07, 2010 D Sheet 40 of 58 5 4 3 2 1 PL451 HCB2012KF-121T50_0805 D PR460 0_0402_5% 1 2 10K_0402_1% 6 PGOOD 8 7 <32> SA_PGOOD 2 C DL PR457 1 2 10K_0402_1% +5VALW 1 PC466 0.1U_0402_25V6 2 1 1 1 4.7_1206_5% + PC452 390U_2.5V_M 2 PC462 4.7U_0805_10V6K 9 @ PR456 2 @ PC456 4 DL_VCCSAP G5603RU1U_TQFN14_3P5X3P5 1 11 10 +VCCSAP 0.1U_0603_25V7K 1 LX_VCCSAP 2 VDD DH_VCCSAP 1 ILIM FB 13 12 5 6 7 8 15 14 BST 1 TP LX VCC 2 +3VS DH OUT PL452 1.8U_D104C-919AS-1R8N_9.5A_30% 1 2 PC455 1 2 680P_0603_50V7K PR463 0_0402_5% PQ452 AO4712L_SO8 C 2 1 PR471 5 BST_VCCSAP-1 2 4 FB TON PGND 3 AGND 1 VOUT EN_SKIP PU450 2 PR461 100_0402_1% 1 2 PC461 4.7U_0805_10V6K 2 0_0603_5% @ PC460 .1U_0402_16V7K 2 +5VALW PQ451 AO4466L_SO8 PR455 1 Ipeak=6A Imax=4.2A F=276K Toatal Capacitor ??u ESR=??mohm 3 2 1 BST_VCCSAP 2 D B+ 1 4 3 2 1 1 <35,42> VCCPPWRGD 2 2 255K_0402_1% PC465 2200P_0402_50V7K 2 1 PR462 1 2 PC464 4.7U_0805_25V6-K 2 5 6 7 8 1 PC463 4.7U_0805_25V6-K VCCSAP_B+ @ PR472 10K_0402_1% VCCSA_SENSE <9> 1 1 PR464 10_0402_5% 2 1 2 PR465 680_0402_1% 1 2 2 1 MMST3904-7-F_SOT323-3 2 PR473 0_0402_5% 1 2 VCCSAP_VID1 <9> 3 @ PR470 100K_0402_1% 2 1 3 B PQ454 2 2 G S PQ453 SSM3K7002FU_SC70-3 PR468 10K_0402_1% 1 D PC470 .1U_0402_16V7K PR469 10K_0402_1% 1 2 1 2 PR467 5.1K_0402_1% 1 1 +3VS PR466 9.09K_0402_1% B VID1 +VCCSAP 1 0.8V 0 0.9V A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/25 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title +VCCSAP/+1.0VSDGPUP Size C Date: 5 4 3 2 Document Number Rev 0.1 NHQAA LA-6831P M/B Sheet Thursday, October 07, 2010 1 41 of 58 5 4 3 2 1 @ PJ75 JUMP_43X79 2 2 1 1 +1.5V PU75 1 4 6 GND NC 5 VREF NC 7 VOUT NC 8 TP 9 D +3VALW PC264 2 PR280 1K_0402_1% 1 3 VCNTL VIN 2 <5,9,35> SUSP @ PR282 0_0402_5% 1 2 2 1 2 PC261 4.7U_0805_6.3V6K 1 D 1U_0603_10V6K PR281 1 +0.75VSP 2 PC263 .1U_0402_16V7K 2 1 1 PC262 10U_0805_6.3V6M For shortage changed PR410 0_0402_5% 1 2 2 1 PC415 4.7U_0805_25V6-K PC414 4.7U_0805_25V6-K 2 1 PC413 4.7U_0805_25V6-K 2 1 3 2 1 9 DL_1.05VS_VCCP G5603RU1U_TQFN14_3P5X3P5 PR415 1 <35,41> VCCPPW RGD 2 +3VALW 2 10K_0402_1% 3 2 1 PC412 4.7U_0805_10V6K 2 4 2 8 7 B 1 DL 2 PQ402 PGOOD 1 TPCA8028-H_SOP-ADVANCE8-5 6 FB 13.7K_0402_1% 1 + PR420 0_0402_5% VDD 10 VFB=0.75V @ PR406 4.7_1206_5% +5VALW 2 LX_1.05VS_VCCP PR407 1 2 VCC +1.05VS_VCCPP 1 1 12 11 OUT 4 @ PC406 680P_0603_50V7K LX ILIM 3 2 1 DH_1.05VS_VCCP DH PL402 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 13 TON PC405 0.1U_0603_25V7K 1 2 5 BST TP 14 15 1 PR405 0_0603_5% BST_1.05VS_VCCP 1 2 2 PGND PR411 100_0603_1% 1 2 EN_SKIP PU400 AGND 2 PC410 @ .1U_0402_16V7K 5 PC411 4.7U_0603_6.3V6K C B+ 4 1 <16,27,32,35,40> SUSP# +5VALW PQ401 PR414 255K_0402_1% 1 2 PL401 HCB4532KF-800T90_1812 1 2 1.05VS_B+ 5 C TPCA8030-H_SOP-ADV8-5 2 PC260 .1U_0402_16V7K 2 S 2 G 1K_0402_1% D PQ260 SSM3K7002FU_SC70-3 1 PR279 0_0402_5% 1 2 1 <35> 0.75VR_EN# 3 G2992F1U_SO8 PC402 390U_2.5V_M 2 B 1 @ PR416 10K_0402_1% PR421 10_0402_5% 2 1 VCCIO_SENSE <8> 1 PR412 4.02K_0402_1% 1 2 2 PR413 10K_0402_1% A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/25 Issued Date Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +1.05VS_VCCP/+0.75VSP Size Document Number Custom Date: Rev 0.1 NHQAA LA-6831P M/B Thursday, October 07, 2010 Sheet 1 42 of 58 4 LGATE3 PGND LGATE3 1 3 2 1 2.61K_0402_1% 5 2 2 + 2 ISEN1 2 PC591 470P_0402_50V7K 2 1 GFX@ PC502 390U_2.5V_M 1 GFX@ PR571 1_0402_5% 2 GFX@ PR570 10K_0402_1% 1 2 PC590 470P_0402_50V7K 2 1 PC227 10U_1206_25V6M 2 1 PC226 10U_1206_25V6M 2 1 GFX@ PC565 4.7U_0805_25V6-K 2 1 GFX@ PC564 4.7U_0805_25V6-K 2 1 GFX@ PC563 4.7U_0805_25V6-K 2 1 ISNG QC@ PC586 4.7U_0805_25V6-K 2 1 470P_0402_50V7K PC589 2 1 470P_0402_50V7K PC579 2 1 2 4 +CPU_CORE QC@ PR594 2 1 ISEN3 1 2 1 PR506 4.7_1206_5% 1 2 10K_0402_1% 10K_0402_1% PL503 0.36UH_PCMC104T-R36MN1R17_30A_20% 3 3 2 1 680P_0603_50V7K 4.7_1206_5% 1 PR526 2 @ @ PC526 2 1 PQ506 TPCA8028-H_SOP-ADVANCE8-5 5 4 3 B 4 LGATE2 PR591 1 ISEN2 1 PC515 0.22U_0603_10V7K BOOT2 2 1 2 1 PR515 0_0603_5% 5 + 1 @ PC574 68U_25V_M_R0.36 + 1 PC569 100U_25V_M 1 PL504 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1 3 2 1 PQ504 TPCA8028-H_SOP-ADVANCE8-5 5 PC525 0.22U_0603_10V7K BOOT1 2 1 2 1 PR525 0_0603_5% LGATE1 4 PC566 68U_25V_M_R0.36 2 PC568 68U_25V_M_R0.36 PC585 4.7U_0805_25V6-K 2 1 PC584 4.7U_0805_25V6-K 2 1 + PHASE1 3 2 1 A 1 ISEN1 10K_0402_1% PHASE2 PQ508 TPCA8028-H_SOP-ADVANCE8-5 3 2 1 4 PC583 4.7U_0805_25V6-K 2 1 UGATE1 PQ503 TPCA8030-H_SOP-ADV8-5 5 CPU_B+ PC578 2 1 4 PC577 2 1 5 UGATE2 0.1U_0402_25V6 1 2 PR557 11K_0402_1% 0.047U_0402_16V7K PR556 1 2 @PC552 @ PC552 @ PR555 330P_0402_50V7K 100_0402_1% 2 1 2 1 QC@ PR589 2 1 3.65K_0402_1% QC@ PR584 2 VSUM- PC582 4.7U_0805_25V6-K 2 1 1000P_0402_50V7K 2 1 QC@ PR585 VSUM+ 2 1 10K_0402_1% For EMI sollution @ 4 680P_0603_50V7K 4.7_1206_5% PC546 QC@ PR587 2 1 10K_0402_1% CPU_B+ VSUM- 3 2 1 <8> VSSSENSE QC@ PR586 ISEN3 2 +CPU_CORE 1_0402_5% PQ505 TPCA8030-H_SOP-ADV8-5 330P_0402_50V7K 2 1 @ 4 PH503 10K_0402_1%_ERTJ0EG103FA .1U_0402_16V7K PC545 <8> VCCSENSE PR554 1.24K_0402_1% 2 1 2 PC544 0.22U_0402_6.3V6K PC553 2 1 470P_0402_50V7K PR551 2 1 3.65K_0402_1% PC551 2 1 @ PR550 @PR550 316K_0402_1% 2 1 PC562 0.22U_0402_6.3V6K 2 1 PC576 2 1 1 VSUM+ 0.1U_0402_10V7K @ PC575 @PC575 150P_0402_50V8J 2 1 499_0402_1% 1 4 PC549 0.22U_0603_10V7K 0.22U_0402_10V6K PR549 316K_0402_1% 2 1 2 2 QC@ +5VALW 1_0603_5% PC550 2 1 PC543 150P_0402_50V8J 2 1 1 330P_0402_50V7K 2 PC547 1 1 3 680P_0603_50V7K 4.7_1206_5% PR560 0_0402_5% 4 QC@ PC535 0.22U_0603_10V7K BOOT3 2 1 2 1 PR535 0_0603_5% QC@ PQ512 TPCA8028-H_SOP-ADVANCE8-5 1 1 QC@ PC567 0.22U_0402_6.3V6K VSUM2 1 PC542 5 3 2 1 CPU_B+ QC@ PL505 0.36UH_PCMC104T-R36MN1R17_30A_20% PHASE3 5 1 2 2 2 22P_0402_50V8J 1U_0603_10V6K PC548 2 1 ISEN1 ISEN2 DC@ PC540 2 1 PR548 4 QC@ PC587 4.7U_0805_25V6-K 2 1 UGATE3 QC@ PQ514 TPCA8028-H_SOP-ADVANCE8-5 @ PC536 PR536 2 1 2 1 BOOT1 C PC581 4.7U_0805_25V6-K 2 1 UGATE1 25 +5VALW CPU_B+ PQ510 TPCA8028-H_SOP-ADVANCE8-5 @ PC516 PR516 2 1 2 1 PHASE1 1 2 DISEN@ PR576 0_0402_5% PR562 0_0603_5% QC@ PC588 4.7U_0805_25V6-K 2 1 27 D Connect to +5V can disable GFX portion 5 28 26 2 @ PC573 0.01U_0402_16V7K +5VALW 3 2 1 LGATE1 Connect to +5V can disable PWM3 5 30 29 1 2 @ PR561 0_0402_5% 1 2 PC554 2.2U_0603_10V6K 2 1 31 VDDP+ 9 ISPG 1 LGATE2 2 GFX@ PH504 10K_0402_1%_ERTJ0EG103FA 1 2 1 2 1 2 GFX@ PR572 7.5K_0402_1% GFX@ PC570 .1U_0402_16V7K 1 2 GFX@ PR573 11K_0402_1% 1 2 1 2 @ PR574 100_0402_1% GFX@ PC571 .1U_0402_16V7K ISL6208ACRZ-T_QFN8_3X3 33 32 + @ PC572 470P_0402_50V7K LGATE 1 1 PHASE3 GND 2 B+ +GFX_COREP 2 7 PL501 HCB4532KF-800T90_1812 2 1 GFX@ PR575 590_0402_1% 3 2 1 PHASE @ PC580 4.7U_0805_25V6-K 2 1 PHASE2 3 2 1 PWM 5 34 PR558 1 499K_0402_1% 2 UGATE3 2 2 GFX@ PL502 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1 3 2 1 UGATE2 0_0603_5% For Turbo mode , PH502 must be changed 470K (b value = 4700) PC541 33P_0402_50V8J 2 BOOT3 8 QC@ PQ507 TPCA8030-H_SOP-ADV8-5 35 PR559 2 1 1 UGATE 3 QC@ PR569 0_0603_5% 1 2 BOOT2 1 ISEN3 1 PC539 2 1000P_0402_50V7K 2 PR546 1 1 PR545 27.4K_0402_1% @ PR547 BOOT FCCM PU500 2 8.06K_0402_1% 1 QC@ PR568 0_0603_5% 1 2 QC@ PR577 0_0603_5% 1 2 LGATEG UGATEG PHASEG LGG PROG1 BOOT1 VIN VDD ISUMP 3.83K_0402_1% 2 B VCC 6 37 38 39 40 BOOTG PROG2 PHG BOOTG NTCG 1 41 ISNG 42 45 46 43 ISNG NTCG ISPG RTNG 47 FBG VSENG UGG 2 470KB_0402_5%_ERTJ0EV474J 2 1 22 PH502 2 COMPG GND 470P_0402_50V7K PR544 1 PH1 UG1 21 1 VW 13 2 VR_HOT# 36 4 QC@ PU501 2 2 1 43P_0402_50V8J 1 2 @ PR543 499_0402_1% PC538 VSSP1 NTC LGATEG 5 1 3 GFX@ PR505 0_0603_5% VDD+ +1.05VS_VCCPP PC537 <32> VR_HOT# IMON ISUMN 12 LG1 RTN 11 PWM3 PGOOD 20 10 <5,18,32> VGATE VR_ON 19 9 44 ISPG 2 1.91K_0402_1% VDDP ISL95831CRZ-T_TQFN48_6X6 VSEN 8 SCLK 18 7 LG2 ISEN1 2 VSSP2 ALERT# 17 PR540 0_0402_5% SDA ISEN2 1 6 PH2 ISEN3/ FB2 5 BOOT2 UG2 16 PC561 0.033U_0603_16V7 2 1 PR542 19.1K_0402_1% 2 1 <32> VR_ON @ @ PR567 16.5K_0402_1% PGOODG 15 4 48 49 SVID_SDA SVID_ALERT# SVID_SCLK PR541 BOOTG 2 IMONG FB 3 COMP 2 14 2 1 @ PC560 .1U_0402_16V7K 2 1 PR537 130_0402_1% <8> VR_SVID_CLK VWG GFX@ PC505 0.22U_0603_10V7K 1 2 1 VSS_AXG_SENSE <9> GFX@ PC558 1000P_0402_50V7K +1.05VS_VCCPP 1 1 1 +5VALW <8> VR_SVID_ALRT# +3VS 2 GFX@ PR534 2.55K_0402_1% <8> VR_SVID_DAT C PHASEG 24 GFX@ PR533 475K_0402_1% GFX@ PC534 0.047U_0603_16V7K 2 1 GFX@ PR539 18.2K_0402_1% 2 1 GFX@ PC533 150P_0402_50V8J 1 VCC_AXG_SENSE <9> 23 2 GFX@ PC532 680P_0402_50V7K 1 1 PR538 54.9_0402_1% 1 1 2 GFX@ PR532 422_0402_1% 2 D 2 1 2 2 2 2 4 2 1 @ PC506 680P_0603_50V7K UGATEG GFX@ PC556 330P_0402_50V7K 1 2 GFX@ PQ501 TPCA8030-H_SOP-ADV8-5 GFX@ PR564 27.4K_0402_1% 1 2 GFX@ PQ502 TPCA8028-H_SOP-ADVANCE8-5 3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J 1 GFX@ PC557 330P_0402_50V7K 2 1 GFX@ PC531 39P_0402_50V7K 2 1 1 CPU_B+ 5 GFX@ PH501 1 2 @ PR531 499K_0402_1% 2 QC@ PC559 1U_0603_10V6K 1 2 1 GFX@ PC530 1000P_0402_50V7K GFX@ PR563 2 1 2 3 @PC555 PC555 470P_0402_50V7K NTCG 1 @ 2 0.1U_0402_25V6 4 GFX@ PR530 8.06K_0402_1% 5 +CPU_CORE PR580 ISEN2 2 PR581 1 2 10K_0402_1% VSUM+ 1 3.65K_0402_1% VSUM- ISEN1 QC@ PR588 2 1 ISEN3 PR582 2 1 10K_0402_1% A 10K_0402_1% PR583 2 1 1_0402_5% VSUM+ PR590 PR592 2 1 2 PR593 VSUM- 2 1_0402_5% 4 1 ISEN2 10K_0402_1% 3.65K_0402_1% 1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/25 2009/04/28 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title CPU_CORE/GFX Size Document Number Custom Date: Rev 0.1 NHQAA LA-6831P M/B Thursday, October 07, 2010 Sheet 1 43 of 58 OP!!!!!!!EBUF!!!!!!!!!!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF ........................................................................................................................................ 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 12. 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 2010/09/07 P37-PWR_BATTERY CONN / OTP P40-PWR-+1.5VP/+1.8VSP P41-PWR_+VCCSAP P40-PWR-+1.5VP/+1.8VSP P53-PWR_+VCCSAP P50-PWR-CHARGER P50-PWR-CHARGER P50-PWR-CHARGER P55-PWR-CPU_CORE/GFX P50-PWR-CHARGER P55-PWR-CPU_CORE/GFX P55-PWR-CPU_CORE/GFX P55-PWR-CPU_CORE/GFX Remove PQ7 SSM3K7002FU Change PQ152 to AO4712L Change PQ452 to AO4712L Change PQ151 to AO446L Change PQ451 to AO446L Change PQ201,PQ202 to AO4466L Change PQ203 to AO4435L and remove PQ207 Add PR234 12.4k Add PR560 0 Ohm Add PR222 24k and PR223 20k Add PR544 3.83k,PR545 27.4k,PH502 470k Change PR551 from 3.83k to 3.65k Change PC550 0.33u to 0.22u and add PC551 0.1u Adapter protect circuit not ready Use same part number Use same part number Use same part number Use same part number Use same part number For UMA SKU For DC and QC CP setting Set CPU VBOOT to 0V For CP setting Add CPU NTC NET For CPU_CORE load line For shortage issue Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/13 Deciphered Date 2009/04/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Power PIR Size Document Number Rev 0.1 NHQAA LA-6831P M/B Date: Thursday, October 07, 2010 Sheet 44 of 58 5 4 3 2 1 HW PIR (Product Improve Record) NWQAA LA-6832P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 GERBER-OUT DATE: 2010/09/03 NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------- D C B Item Date Page Component Solution Request ----------------------------------------------------------------------------------------------------------------------------------1) 07/21 Delete 3D@,DHDMI@,DIS@,EDP@,NO3D@,OPT@,UMA@ For low cost Huron River 2) 08/11 Update room 3) 08/11 09 Change R119 change to @ 4) 08/12 16 Add R442, R443 For SPI debug circuit 5) 08/12 16 Change R572, R573, R574, R575, R569 from @ to mount For SPI debug circuit 6) 08/12 20 Remove USB20_P3/N3 from PCH Don't need USB20/30 BTO 7) 08/12 30 Remove DT1, JUSB20, RT14, RT20, RT23, RT24 Don't need USB20/30 BTO 8) 08/12 32 Change C449, C450, Y4 from @ to mount 9) 08/13 15 Change L8, L9 L10, L11 from SM070001600 to SM070001310 For EMI demand 10) 08/13 30 Change RT11 to @ 11) 08/13 30 Change RT19 to USB30@ 12) 08/13 30 Change CT3 from SE000005TN0 to SE000005T80 13) 08/13 30 Remove RT25, RT27 Don't need USB20/30 BTO 14) 08/17 5 Remove R14 For HW Review demand 15) 08/18 6 Reserve R33 For HW Review demand 16) 08/18 9 Reserve R119 To follow CRB 1.0 17) 08/18 11 Remove R92, R89 For HW Review demand 18) 08/18 12 Remove R93, R97 For HW Review demand 19) 08/18 26 Reserve C236, C268, C490 For HW Review demand 20) 08/18 15 Remove R435, R438, R453(0 ohm) 21) 08/18 15 Change R195, R197, R198, R202, R201, R203, R205, R206 to SD028680080 22) 08/18 15 Remove R207 For HW Review demand 23) 08/18 18 Change Net name from PM_CLKRUN# to PCH_GPIO32 For HW Review demand 24) 08/18 20 Change R324 From 1K to 2.2K For Intel check list demand 25) 08/18 21 Remove PCH PECI signal By HW Review demand 26) 08/18 25 Remove C363, C364, C365, C366 By HW Review demand 27) 08/18 30 Change UT4 to SA00004600 For CIC demand 28) 08/18 30 Change USB30@ to always mount Due to no BTO USB20/30. 29) 08/18 27 Remove all new card function 30) 08/20 9 Add PJ32 For Cost down +1.5V to +1.5V_CPU 31) 08/20 13 Swap USB20_P11 and USB20_N11 For layout request 32) 08/20 25 Swap USB20_P0, USB20_N0, USB20_P1, USB20_N1 For layout request 33) 08/23 Update Power schematic 34) 08/23 20 Swap PCI_PIRQC#, PCH_GPIO4, PCH_GPIO2, PCI_PIRQA# For layout request 35) 08/23 20 Swap SLP_CHG_M3, SLP_CHG_M4, USB_OC#0 For layout request 36) 08/30 18 Reserve R259 For cost down plan 37) 08/30 Change USB3.0 Connector For ME demand 38) 08/30 21 Add USB Sleep & Charge MAXIC_Select pin in GPIO71(Remove T73) For MAX14550E/14566B co-lay 39) 08/30 25 Change C426 to Aluminum Solid Cap 220u For cost down 40) 08/30 27 Add USB Sleep & Charge IC: MAX14550E 41) 08/30 28 Add 16pin X’form for cost down, and P/N is SP050006E00 For cost down 42) 08/30 28 Change PWRME_CTRL# from PCH_GPIO33 to HDA_SDO By Intel spec 43) 08/30 16 Change U53 PIN 9 from KSI4 to KSI3 44) 08/30 16 Change R442, R443 from 10k to 100k 45) 08/30 16 Change U56 Pin3 from KSO6 to +5VALW 46) 08/30 16 Add R227 100k ohm 47) 08/30 28 Reserve D85 and D86 For ESD request 48) 08/30 30 Swap U3RXDN1_R, U3RXDN1_R_L, U3RXDP1_R, U3RXDP1_R_L For layout request 49) 08/30 16 Change U13 from SA000021A00 to SA00003IN00 Due to EOL of SA000021A00 50) 08/30 27 Reserve R1443 for WLAN Mini PCIE Card Pin5 51) 08/30 33 Change U22 From SA00003GK00 to SA00003GM10 Due to EOL of SA00003GK00 52) 08/30 34 Change SW1, SW4 to SN100002Y00 53) 09/01 28 Add LL5 for ISN test For EMI demand 54) 09/01 31 Change RA12 from 10k to 4.7kohm and CA18 from 0.1uF to 100pF For Beep by A51 demand. 55) 09/01 32 Add CPSETIN to power For 65W/75W select 56) 09/01 18,20,21 Reserve C894, C895, C896, C897 For ESD request 57) 09/02 08 Remove, add C126, C131 and add C898 3Pin Bulk Cap By Power Demand 58) 09/02 27 Add 14566@ & 14550@ 59) 09/02 27 Change U5 Pin8 control pin from SLP_CHG# to SLP_CHG_M4 60) 09/02 33 Change EC ROM size from 256KB(SA00003GM10) to 128KB(SA00003FL10) 61) 09/02 11 Change C165,C166,C168,C171,C174,C176,C178 from SE093106M80 to SE000005T80 For sourcer demand 62) 09/02 12 Change C191,C192,C194,C197,C200,C202,C204 from SE093106M80 to SE000005T80 For sourcer demand 63) 09/02 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80 (10uF_0603) For sourcer demand 64) 09/03 08 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 For Power demand 65) 09/06 33 Change U22 change to SA00003FL10 66) 09/06 28 Delete UL4 8105ELDO@ and 8105ESWR@ D C B A A Compal Electronics, Inc. Compal Secret Data Security Classification 200910/9 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW-PIR Size Document Number Custom Rev 0.1 NHQAA LA-6831P M/B Date: Thursday, October 07, 2010 Sheet 1 57 of 57 www.s-manuals.com
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