Compal LA 7221P Schematics. Www.s Manuals.com. R1.0 Schematics

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A

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C

D

E

Compal Confidential
Model Name : P5LJ0 & P5LS0
File Name : LA-7221P
1

1

Compal Confidential

2

2

JM50-HR M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P-GS/GV
3

3

2010-02-16
REV:0.5
MB PCB
Part Number
DA80000MA00

Description
PCB 0IN LA-7221P REV0 M/B

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Cover Page
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Friday, February 18, 2011

Sheet
E

1

of

59

A

B

C

Fan Control
page

D

E

45

1

1

PEG(DIS)

100MHz

PCI-E 2.0x16

5GT/s PER LANE

Nvidia N12P-GS/GV
973pin BGA

Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel

Intel
Sandy Bridge

133MHz

page 11,12

BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333

Processor

page22~30

EDP

rPGA989

(reserved)
page 32

HDMI(Optimus1.1)

page 4~10

DMI x4 USB 2.0 conn x3

FDI x8
HDMI Conn.

CRT Conn. LVDS Conn.
page 32

page 33

page 31

2

HDMI(Optimus1.0)

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

port 4

port 3

USB uPD720200A
USB 3.0 conn x1

port 2

port 1

MINI Card x1

LAN(GbE)

USB port 8

AR8151/8152

WLAN

page 44.45

page 37

1GB/s x4

page 36

USB port 0,1,2 on USB/B
page 37

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

CMOS Camera

Mini Card
(WWAN,SIM)

USB port 13
page 37

USB port 10

USB port 9,12 on 3G/B
page 37

page 31

2

HDA Codec
CX20584

989pin BGA

SATA x 6
100MHz
(GEN1 1.5GT/S ,GEN2 3GT/S)

page 42

SPI

page 13~21

page 35

RJ45

page 38

3

100MHz

2.7GT/s

LVDS(UMA/Optimus)
Intel
CRT(UMA/Optimus)
HDMI(UMA/Optimus) Cougar Point-M
PCH
100MHz

SPI ROM x1
port 0

Card Reader
RTS5209

100MHz

Bluetooth
Conn

SATA HDD
Conn.

page 34

(SJM)

page 13

port 2

SATA CDROM
Conn.

Audio AMP

LPC BUS

page 34

(JM)
3

TI TPS6017
page 43

33MHz

ENE KB930

Sub-board

page 39

RTC CKT.
page 13

LS-7221P

LS-7225P

USB/B 3 port
USB Port0,1,2 page 37

USB/B/DW 3 port
USB Port0,1,2 page 37

LS-7222P(JM)

LS-7226P(SJM)

3G/B
USB Port 9,12 page 37

3G/B
USB Port 9,12 page 37

LS-7223P(JM)

LS-7227P(SJM)

Power/B

Power/B

Int. Speaker
Touch Pad
page 40

Power On/Off CKT.
page 40

page 46

4

page 47~55

CPU XDP

page 39

page 5
4

LS-7224P(JM)

LED/B

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

page 41

2009/08/01

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

page 43

page 41

page 41

Power Circuit DC/DC

SPDIF Jack

page 43

page 43

page 40

BIOS ROM
DC/DC Interface CKT.

MIC Jack

Int.KBD

B

C

D

Title

Block Diagrams
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

2

of

59

A

B

C

D

Voltage Rails
Power Plane

1

2

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+V

+VS

Clock

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VCCP

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VCCP to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.5VSDGPU

+1.5VS to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

Board ID

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF

0
1
2
3
4
5
6
7

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW always to KBC

ON

ON

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

EC SM Bus1 address
Device

Address

Smart Battery

0001 011X b

PCH SM Bus address
Device

1101 0010b

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

Address

UHCI0
UHCI1
EHCI1

3G SKU: 3G@
BT SKU: BT@

UHCI2
UHCI3

BOM Config

4

BT@/3G@/UMA@/UMAO@/JM@/8151@

4319BOBOL01/L21
4319BOBOL02/L22
4319BOBOL03/L23
4319BOBOL04/L24
4319BOBOL05/L25
4319BOBOL06/L26
4319BOBOL07/L27
4319BOBOL08/L28
A

UHCI4

BT@/3G@/UMA@/OPT@/JM@/8151@/GV@/GS@
BT@/3G@/UMA@/UMAO@/SJM@/8151@

EHCI2

UHCI5

BT@/3G@/UMA@/OPT@/SJM@/8151@/GV@/GS@

BOM P/N(JM/SJM)
UMA W3G HDMI
UMA N3G HDMI
N12PGS 1GW3G HDMI
N12PGS 1GN3G HDM
N12PGS 2GW3G HDMI
N12PGS 2GN3G HDMI
N12PGV 512W3G HDMI
N12PGV 512N3G HDMI

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

UHCI6

VRAM BOM Config
X76289BOL01
X76289BOL02
X76289BOL03
X76289BOL04
X76289BOL05
X76289BOL06

512M SAM 64M16
512M HYN 64M16
1G SAM 64M16
1G HYN 64M16
2G SAM 128M16
2G HYN 128M16

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB/B (Right Side)
USB/B (Right Side)
USB/B (Right Side)

2009/08/01

C

2

BOM Structure
UMAO@
UMA@
OPT@
OPT11@
GS@
GV@
X76@
CONN@
3G@
BT@
EDP@
8151@
8152@
JM@
SJM@
@
VGA@

3

Mini Card(WLAN)
Mini Card(WWAN)
Camera
SIM Card
Blue Tooth

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Item
UMA Only
UMA with OPTIMUS
OPTIMUS1.0
OPTIMUS1.1
N12P-GS@
N12P-GV@
VRAM
Connector
3G
Blue Tooth
EDP
LAN Chip AR8151
LAN Chip AR8152
JM Board
SJM Board
Unpop
Power GPU

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1

BTO Option Table
PCB Revision
0.1
0.2
0.3
1.0

Board ID
0
1
2
3
4
5
6
7

USB 2.0 USB 1.1 Port

3G & BT Config

JM UMA Only:
JM OPTIMUS:
SJM UMA Only:
SJM OPTIMUS:

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

USB Port Table

Address

Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

BOARD ID Table

EC SM Bus2 address
Device

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Board ID / SKU ID Table for AD channel

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

3

+VALW

HIGH

Full ON

+1.0VSDGPU

+3VALW_EC

SIGNAL

STATE

E

D

Title

Notes List
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

3

of

59

5

4

3

2

D

1

+1.05VS_VCCP

R1
24.9_0402_1%

15
15
15
15

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

15
15
15
15

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

15
15
15
15

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

15
15
15
15
15
15
15
15

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

15 FDI_FSYNC0
15 FDI_FSYNC1

J18
J17

15 FDI_INT

H20

R2
24.9_0402_1%

15 FDI_LSYNC0
15 FDI_LSYNC1

J19
H17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

PCI EXPRESS* - GRAPHICS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

2

B

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

B27
B25
A25
B24

1

+1.05VS_VCCP

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

C

15
15
15
15

DMI

A18
A17
B16
C15
D15

31 EDP_AUXP
31 EDP_AUXN
31 EDP_TXP0
31 EDP_TXP1
PAD
T1 @
PAD
T2 @
31 EDP_TXN0
31 EDP_TXN1
PAD
T3 @
PAD
T4 @

EDP_TXP2
EDP_TXP3

C17
F16
C16
G15

EDP_TXN2
EDP_TXN3

C18
E16
D16
F15

eDP_COMPIO
eDP_ICOMPO
eDP_HPD
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

eDP

EDP_COMP
31 EDP_HPD#

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PEG_COMP

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

D

PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

2

JCPU1A

1

PEG_GTX_C_HRX_N[0..15] 22
PEG_GTX_C_HRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

C

B

SUYIN_100361HK988_SANDY BRIDGE

CONN@

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

4

of

59

5

4

3

2

1

D

D

Modify R05
Delete XDP

For eDP
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

R25
R26

1 EDP@ 2 0_0402_5%
1 EDP@ 2 0_0402_5%

CLK_CPU_DPLL 14
CLK_CPU_DPLL# 14

JCPU1B

1 62_0402_5% H_PROCHOT#

2

T5

18,39 H_PECI
R34

2

1 10K_0402_5% H_CPUPWRGD_R

PAD
R32
0_0402_5%
1
2

H_CATERR#

AL33

H_PECI_ISO

AN33

39,50 H_PROCHOT#

R36
56_0402_5%
1
2

H_PROCHOT#_R

AL32

18 H_THRMTRIP#

R38
0_0402_5%
1
2

H_THEMTRIP#_R

AN32

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

BCLK
BCLK#

A28
A27

CLK_CPU_DMI_R
CLK_CPU_DMII#_R

R27
R29

DPLL_REF_CLK
DPLL_REF_CLK#

A16
A15

CLK_CPU_DPLL_R R30
CLK_CPU_DPLL#_R R31

1 LVDS@ 2 1K_0402_5%
1 LVDS@ 2 1K_0402_5%

R8

H_DRAMRST#

SM_DRAMRST#

DDR3
MISC

R28

AN34

Processor Pullups

THERMAL

+1.05VS_VCCP

PROC_SELECT#

CLOCKS

C

C26

17 H_SNB_IVB#

MISC

C

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

2
BUFO_CPU_RST#

R49
43_0402_1%
1
2 BUF_CPU_RST#

SN74LVC1G07DCKR_SC70-5

H_PM_SYNC_R

AM34

H_CPUPWRGD_R

R51
130_0402_5%
PM_SYS_PWRGD_BUF 1
2 PM_DRAM_PWRGD_R

AP33

V8

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

@
R52
0_0402_5%
2

BUF_CPU_RST#

AR33

RESET#

JTAG & BPM

18 H_CPUPWRGD

R48
0_0402_5%
1
2

1

5
P

A

G

Y

4

3

,39,44 PLT_RST#

PLT_RST# 2

R42
0_0402_5%
1
2

R44
75_0402_5%

U1

NC

15 H_PM_SYNC

PWR MANAGEMENT

+1.05VS_VCCP
C35
0.1U_0402_16V4Z

2

B

1

1

PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO

DBR#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

DDR3 compensation

Signals

SM_RCOMP0 R33

2

1 140_0402_1%

SM_RCOMP1 R35

2

1 25.5_0402_1%

SM_RCOMP2 R37

2

1 200_0402_1%

Modify R05
Delete XDP

AP29
AP27
AR26
AR27
AP30

XDP_TCK
XDP_TMS
XDP_TRST#

PAD
PAD
PAD

T94
T95
T96

AR28
AP26

XDP_TDI_R
XDP_TDO_R

PAD
PAD

T97
T98

AL35

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

+1.05VS_VCCP

H_DRAMRST# 6

Buffered reset to CPU

+3VS

1

AK1
A5
A4

2 0_0402_5%
2 0_0402_5%

1
1

DBRESET#_R

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

1 R50

2 0_0402_5%

B

Modify R05
Delete XDP

XDP_DBRESET#

XDP_DBRESET# 15

Modify R05
Delete XDP

+3VS
XDP_DBRESET#

R17

1 1K_0402_5%

2

+3VALW

1
2

5
1

B

2

A

O

4

A

PM_SYS_PWRGD_BUF

3

1

15 PM_DRAM_PWRGD

R61
200_0402_5%

U2
74AHC1G09GW_TSSOP5

P

A

CONN@

G

R62
10K_0402_5%
1
2

SUYIN_100361HK988_SANDY BRIDGE

+1.5V_CPU_VDDQ

1

C36
0.1U_0402_16V4Z

2

+3VS

1 2

@
R63
39_0402_5%

SUSP

SUSP

5

Compal Secret Data

Security Classification
D

2
G
3

46,53

@
Q2
2N7002H_SOT23-3

Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

5

of

59

5

4

3

2

JCPU1C

JCPU1D

C

AE10
AF10
V6

11 DDR_A_BS0
11 DDR_A_BS1
11 DDR_A_BS2

B

AE8
AD9
AF9

11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

DDR SYSTEM MEMORY A

D

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

M_CLK_DDR0 11
M_CLK_DDR#0 11
DDR_CKE0_DIMMA 11

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

M_CLK_DDR1 11
M_CLK_DDR#1 11
DDR_CKE1_DIMMA 11

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

AB4
AA4
W9

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA# 11
DDR_CS1_DIMMA# 11

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

AH3
AG3
AG2
AH2

M_ODT0 11
M_ODT1 11

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SUYIN_100361HK988_SANDY BRIDGE

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

12 DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

11

11

DDR_A_MA[0..15] 11

12 DDR_B_BS0
12 DDR_B_BS1
12 DDR_B_BS2

12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7
R6

AA10
AB8
AB9

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

DDR SYSTEM MEMORY B

11 DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

1

AE2
AD2
R9

M_CLK_DDR2 12
M_CLK_DDR#2 12
DDR_CKE2_DIMMB 12

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

M_CLK_DDR3 12
M_CLK_DDR#3 12
DDR_CKE3_DIMMB 12

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

AB2
AA2
T9

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

AD3
AE3
AD6
AE6

DDR_CS2_DIMMB# 12
DDR_CS3_DIMMB# 12

SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

AE4
AD4
AD5
AE5

M_ODT2 12
M_ODT3 12

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SUYIN_100361HK988_SANDY BRIDGE

CONN@

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

D

12

C

12

DDR_B_MA[0..15] 12

B

CONN@

R65
1K_0402_5%
R66
1K_0402_5%
2

2

@ R64
0_0402_5%
1
2

1

+1.5V

D

S

H_DRAMRST#

DDR3_DRAMRST#_R
1
Q3
BSS138_NL_SOT23-3

3
2

5 H_DRAMRST#

R68
0_0402_5%
1
2

2

A

DRAMRST_CNTRL

2

Compal Secret Data

Security Classification

1

11,12,14 DRAMRST_CNTRL_PCH

1

A

DDR3_DRAMRST# 11,12

G

R67
4.99K_0402_1%

1

C37
0.047U_0402_16V4Z

Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

6

of

59

5

4

3

2

1

CFG Straps for Processor

1

CFG2

2

R69
1K_0402_1%
D

PEG Static Lane Reversal - CFG2 is for the 16x

JCPU1E

to
to
to
to

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

T6
T7
T8
T9

PAD
PAD
PAD
PAD

AJ31
AH31
AJ33
AH33

RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

1

+3VS

B

R75
10K_0402_5%
VCCIO_SEL

1 2

@

B4
D1

VCCIO_SEL

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
A19

R76
10K_0402_5%

@

1
2

EDP@
R70
1K_0402_1%

Modify R02

C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

*

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

RSVD5

RSVD6
RSVD7

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

CFG6

B34
A33
A34
B35
C35

CFG5
@ R73
1K_0402_1%

@ R74
1K_0402_1%

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD24
RSVD25
VCCIO_SEL

AJ32
AK32

PAD

AH27

T10

PCIE Port Bifurcation Straps
RSVD54
RSVD55

AN35
AM35

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]
RSVD56
RSVD57
RSVD58

*10: x8, x8 - Device 1 function 1 enabled ; function 2

B

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2
AT1
AR1

RSVD27

2

J15

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AR35
AT34
AT33
AP35
AR34

0:Lane Reversed
CFG4

Display Port Presence Strap

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

1
R72
1K_0402_1%
2

R71
1K_0402_1%
2

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC

1

11 SA_DIMM_VREFDQ
12 SB_DIMM_VREFDQ

AJ26

T8
J16
H16
G16

definition matches

1

change
change
change
change

RSVD37
RSVD38
RSVD39
RSVD40

*

1

AJ31
AH31
AJ33
AH33

RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

1: Normal Operation; Lane #
socket pin map definition

CFG2

2

C

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

L7
AG7
AE7
AK2
W8

2

CFG4
CFG5
CFG6
CFG7

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RESERVED

CFG2

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

D

KEY

B1

CFG7

*

VCCIO_SEL

@ R77
1K_0402_1%

1/NC : (Default) +1.05VS_VTT
0: +1.0VS_VTT

SUYIN_100361HK988_SANDY BRIDGE

2

A19

1

VCCIO_SEL

CONN@

For 2012 CPU support

RSVD26 had changed the name to VCCIO_SEL
Need PH +3VS 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

A

Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

7

of

59

5

4

3

JCPU1F

SV type CPU

2

1

POWER

+CPU_CORE

1

1
2

2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1

1
2

1
2

1
2

1

1

1

2
R80
43_0402_1%
1
2
1
2 0_0402_5%
1
2 0_0402_5%

R81
R82

VR_SVID_ALRT# 54
VR_SVID_CLK 54
VR_SVID_DAT 54

B

Place the PU
resistors
close to CPU

1
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R

R84
R85

1
1

2
2

0_0402_5%
0_0402_5%

VCCSENSE 54
VSSSENSE 54
1

VCC_SENSE
VSS_SENSE

2

R83
100_0402_1%

VCCIO_SENSE
VSSIO_SENSE

B10
A10

R86
100_0402_1%

VCCIO_SENSE 53
VSSIO_SENSE 53

VSSIO_SENSE

2

1
2
1
2

1
2
1
2

2

2

1
2

1
2

PEG AND DDR
SVID

1
1

1
2
1
2

1
2
1
2

1
2
1
2

C64
330U_D2_2V_Y

R79
75_0402_5%

+CPU_CORE

SENSE LINES

2

2

2

1

1

1
2
1
2
1
2
1
2

1
2

CORE SUPPLY

2

2

2

1

1

1
2

1
2
1
2

1
2
1
2

1
2
1

C63
330U_D2_2V_Y

C61
22U_0805_6.3V6M

2

C62
330U_D2_2V_Y

C60
22U_0805_6.3V6M

C50
22U_0805_6.3V6M

C49
22U_0805_6.3V6M

C59
22U_0805_6.3V6M

3

C48
22U_0805_6.3V6M

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

A

CONN@

Compal Secret Data
2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+

@

Place the PU
resistors
close to VR

SUYIN_100361HK988_SANDY BRIDGE

5

C58
22U_0805_6.3V6M

AJ29
AJ30
AJ28

+

@

+1.05VS_VCCP

R78
130_0402_5%

VIDALERT#
VIDSCLK
VIDSOUT

D

C

+1.05VS_VCCP

Security Classification
Issued Date

J23

C47
22U_0805_6.3V6M

A

VCCIO40

+

@

BoT side.
C53
22U_0805_6.3V6M

B

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

C46
22U_0805_6.3V6M

Modify R02

+

C85
330U_D2_2V_Y

+

C84
330U_D2_2V_Y

+

C82
330U_D2_2V_Y

C81
330U_D2_2V_Y

+

Socket Cavity

C80
22U_0805_6.3V6M

Socket Edge

C72
22U_0805_6.3V6M

+CPU_CORE

C79
22U_0805_6.3V6M

C78
22U_0805_6.3V6M

C77
22U_0805_6.3V6M

C76
22U_0805_6.3V6M

C75
22U_0805_6.3V6M

C74
22U_0805_6.3V6M

C73
22U_0805_6.3V6M

Socket Cavity

C71
22U_0805_6.3V6M

C70
22U_0805_6.3V6M

C69
22U_0805_6.3V6M

C68
22U_0805_6.3V6M

C67
22U_0805_6.3V6M

C66
22U_0805_6.3V6M

C65
22U_0805_6.3V6M

C

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

+1.05VS_VCCP

C52
22U_0805_6.3V6M

Socket Edge

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

C51
22U_0805_6.3V6M

C57
10U_0805_6.3V6M

C56
10U_0805_6.3V6M

C55
10U_0805_6.3V6M

C39
10U_0805_6.3V6M

C54
10U_0805_6.3V6M

+CPU_CORE

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

C45
22U_0805_6.3V6M

10x 10 µF Bottom Socket Cavity

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

Top side.
C44
22U_0805_6.3V6M

C43
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

Top Socket Cavity
Top Socket Edge

C41
10U_0805_6.3V6M

8x 22 µF
8x 22 µF

C40
10U_0805_6.3V6M

4x 470 µF Bottom Socket Edge
D

+1.05VS_VCCP

8.5A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

2

QC 94A
DC 53A

Socket Cavity

2

Title

Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

8

of

59

5

4

3

2

1

Delete
+1.5V_CPU_VDDQ Source
D

D

1
2
1

1

SENSE
LINES

2

2

VREF

2

1

PAD-OPEN 4x4m
+

C114
330U_D2_2V_Y

2

1
2

1
2

1
2

1
2

1
2

2

1

1

Modify R03
B

+VCCSA

6A

R96

2 0_0402_5%

1

VCCSA_SENSE

1

@

+
2

1
2

1
2

2

1

+VCCSA

M27
M26
L26
J26
J25
J24
H26
H25

1

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

2

DDR3 -1.5V RAILS
SA RAIL

@ JP2

5A

C119
330U_D2_2V_Y
R97

2 0_0402_5%

1

VSSSA_SENSE 52

VCCSA_SENSE

VCCSA_SENSE 52

C22 H_FC_C22
C24

VCCSA_VID1 52
1

2

FC_C22
VCCSA_VID1

H23

R99
10K_0402_5%

SUYIN_100361HK988_SANDY BRIDGE

CONN@

A

@ R100
0_0402_5%

2

1

1
2

1
2

1
2

1
2

VCCPLL1
VCCPLL2
VCCPLL3

+1.5VS
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

Modify R04

MISC

1
2

1
2

1
2
1
2

1
2

1

2

1
2

9/30 DG1.5

C118
10U_0603_6.3V6M

C123
1U_0402_6.3V6K

Modify R05

C122
1U_0402_6.3V6K

A

C121
10U_0603_6.3V6M

C120
330U_D2_2V_Y

+

B6
A6
A2

R95
1K_0402_1%

C117
10U_0603_6.3V6M

+1.8VS_VCCPLL

C101
0.1U_0402_16V4Z

C116
10U_0603_6.3V6M

1.5A

R98
0_0805_5%
1
2

+V_SM_VREF

AL1

C115
10U_0603_6.3V6M

+1.8VS

SM_VREF

C

R94
1K_0402_1%

+1.5V_CPU_VDDQ

GRAPHICS

1
2

1
2

1
2

1
2

1
2

1
2
2
1
2

1
2

‧

+V_SM_VREF should
have 20 mil trace width

C113
10U_0603_6.3V6M

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

+1.5V_CPU_VDDQ

C112
10U_0603_6.3V6M

‧ Can connect to GND if motherboard only

VCC_AXG_SENSE 54
VSS_AXG_SENSE 54

C111
10U_0603_6.3V6M

Vaxg
B

AK35
AK34

C110
10U_0603_6.3V6M

@

VAXG_SENSE
VSSAXG_SENSE

C109
10U_0603_6.3V6M

@

C105
22U_0805_6.3V6M

C104
22U_0805_6.3V6M

+

C103
330U_D2_2V_Y

C102
330U_D2_2V_Y

+

@

C100
22U_0805_6.3V6M

Bottom Socket Edge

C99
22U_0805_6.3V6M

4x 22 µF

C94
22U_0805_6.3V6M

Bottom Socket Cavity

C98
22U_0805_6.3V6M

2x 470 µF

C97
22U_0805_6.3V6M

Top Socket Cavity
Top Socket Edge

C93
22U_0805_6.3V6M

2x 22 µF
4x 22 µF

1

Bottom Socket Edge

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

C108
10U_0603_6.3V6M

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

C92
22U_0805_6.3V6M

C91
22U_0805_6.3V6M

C96
22U_0805_6.3V6M

C90
22U_0805_6.3V6M

C89
22U_0805_6.3V6M

2x 470 µF

C95
22U_0805_6.3V6M

C

POWER

JCPU1G

1.8V RAIL

QC 33A
DC 26A

+VGFX_CORE

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(6/7) PWR

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

9

of

59

5

4

3

2

JCPU1H
D

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

C

B

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

1

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

D

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

C

B

SUYIN_100361HK988_SANDY BRIDGE

SUYIN_100361HK988_SANDY BRIDGE

CONN@

CONN@

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(7/7) VSS

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

10

of

59

5

4

3

2

1

1

+1.5V

R101
1K_0402_1%

+1.5V

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

+3VS

2
1

1
2

1

1
2

R115
10K_0402_5%

R114
10K_0402_5%

C145
2.2U_0603_6.3V6K

DIMM_A Reserve H:4mm

C144
0.1U_0402_16V4Z



+0.75VS

2

A

205

G1

FOX_AS0A626-U4SN-7F
CONN@

4

DDR_A_DQS#5
DDR_A_DQS5

1

1

1
2

2
1
2

DDR_A_D44
DDR_A_D45

1
2

1
2

1
2

1
2

1
2

1

B

1

DDR_A_D38
DDR_A_D39

+0.75VS
R105
1K_0402_1%

2

DDR_A_D36
DDR_A_D37

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 12,14
D_CK_SCLK 12,14

A

+0.75VS

10/04 Check footprint ok
Compal Secret Data
2009/12/01

3

2

Layout Note:
Place near JDIMM1.203,204

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2

1
R104
1K_0402_1%

M_ODT1 6
+VREF_CA

Security Classification
Issued Date

2
1

G2

206

DDR_CS0_DIMMA# 6
M_ODT0 6

C143
1U_0402_6.3V6K

DDR_A_D48
DDR_A_D49

M_ODT1

C142
1U_0402_6.3V6K

DDR_A_D42
DDR_A_D43

DDR_CS0_DIMMA#
M_ODT0

C141
1U_0402_6.3V6K

DDR_A_D40
DDR_A_D41

2

C

+1.5V

C140
1U_0402_6.3V6K

DDR_A_D34
DDR_A_D35

DDR_A_BS1 6
DDR_A_RAS# 6

1

B

M_CLK_DDR1 6
M_CLK_DDR#1 6

DDR_A_BS1
DDR_A_RAS#

C139
0.1U_0402_16V4Z

DDR_A_DQS#4
DDR_A_DQS4

M_CLK_DDR1
M_CLK_DDR#1

C138
2.2U_0603_6.3V6K

DDR_A_D32
DDR_A_D33

2

1

DDR_A_MA2
DDR_A_MA0

2

6 DDR_CS1_DIMMA#

2

1

C866
0.1U_0402_16V4Z

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_MA6
DDR_A_MA4

+

C865
0.1U_0402_16V4Z

DDR_A_WE#
DDR_A_CAS#

6 DDR_A_WE#
6 DDR_A_CAS#

DDR_A_MA11
DDR_A_MA7

1

C137
330U_D2_2V_Y

6 DDR_A_BS0

DDR_CKE1_DIMMA 6

DDR_A_MA15
DDR_A_MA14

C136
0.1U_0402_16V4Z

DDR_A_MA10
DDR_A_BS0

DDR_CKE1_DIMMA

C135
10U_0603_6.3V6M

M_CLK_DDR0
M_CLK_DDR#0

6 M_CLK_DDR0
6 M_CLK_DDR#0

+1.5V

C134
10U_0603_6.3V6M

DDR_A_MA3
DDR_A_MA1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D30
DDR_A_D31

C133
10U_0603_6.3V6M

DDR_A_MA8
DDR_A_MA5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_DQS#3
DDR_A_DQS3

C132
10U_0603_6.3V6M

DDR_A_MA12
DDR_A_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D28
DDR_A_D29

C131
10U_0603_6.3V6M

6 DDR_A_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_D22
DDR_A_D23

C130
10U_0603_6.3V6M

DDR_A_BS2

+1.5V

C129
1U_0402_6.3V6K

DDR_CKE0_DIMMA

6 DDR_CKE0_DIMMA

C

Layout Note:
Place near JDIMM1

DDR_A_D20
DDR_A_D21

C128
1U_0402_6.3V6K

DDR_A_D26
DDR_A_D27

DDR3_DRAMRST# 6,12

DDR_A_D14
DDR_A_D15

C127
1U_0402_6.3V6K

DDR_A_D24
DDR_A_D25

DDR3_DRAMRST#

C126
1U_0402_6.3V6K

DDR_A_D18
DDR_A_D19

6

D

2

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D[0..63]

6

DDR_A_D12
DDR_A_D13

1

DDR_A_D16
DDR_A_D17

6

DDR_A_MA[0..15] 6

DDR_A_D6
DDR_A_D7

2

All VREF traces should
have 10 mil trace width

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_DQS[0..7]

1

DDR_A_D10
DDR_A_D11

DDR_A_DQS#[0..7]

DDR_A_D4
DDR_A_D5

2

DDR_A_DQS#1
DDR_A_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

DDR_A_D8
DDR_A_D9

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_A_D2
DDR_A_D3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

1

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

2

D

2

1
2

2

G

R103
1K_0402_1%

1

BSS138_NL_SOT23-3
6,12,14 DRAMRST_CNTRL_PCH

C125
0.1U_0402_16V4Z

1
Q8
@

C124
2.2U_0603_6.3V6K

D

S

3

+1.5V
JDIMM1

+DIMM0_VREF

1

@R102
@
R102
0_0402_5%
1
2
2

7 SA_DIMM_VREFDQ

2

M3 support

2

Title

Compal Electronics, Inc.
DDRIII DIMMA

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

11

of

59

5

4

3

2

1

@ R116
0_0402_5%
1
2

R117
1K_0402_1%

+1.5V

+1.5V
JDIMM2

1

G1

2

205

DDR_B_D28
DDR_B_D29

C868
0.1U_0402_16V4Z

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_D22
DDR_B_D23

C867
0.1U_0402_16V4Z

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

+1.5V

DDR_B_D20
DDR_B_D21
C151
1U_0402_6.3V6K

DDR_B_D26
DDR_B_D27

D

DDR3_DRAMRST# 6,11

DDR_B_D14
DDR_B_D15

C150
1U_0402_6.3V6K

DDR_B_D24
DDR_B_D25

DDR3_DRAMRST#

C149
1U_0402_6.3V6K

DDR_B_D18
DDR_B_D19

DDR_B_MA[0..15] 6

C148
1U_0402_6.3V6K

DDR_B_DQS#2
DDR_B_DQS2

6

DDR_B_D12
DDR_B_D13

1

DDR_B_D16
DDR_B_D17

6

DDR_B_D[0..63]

2

DDR_B_D10
DDR_B_D11

6

DDR_B_DQS[0..7]

DDR_B_D6
DDR_B_D7

1

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_DQS#[0..7]

DDR_B_DQS#0
DDR_B_DQS0

2

All VREF traces should
have 10 mil trace width

DDR_B_D4
DDR_B_D5

1

1

DDR_B_D8
DDR_B_D9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2

DDR_B_D2
DDR_B_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

D

DDR_B_D0
DDR_B_D1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

2

6,11,14 DRAMRST_CNTRL_PCH

2

2

G

R118
1K_0402_1%

2

1

1

1
Q9

C147
0.1U_0402_16V4Z

@

C146
2.2U_0603_6.3V6K

D

S

3
BSS138_NL_SOT23-3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

+DIMM1_VREF

2

7 SB_DIMM_VREFDQ

2

M3 support

1

+1.5V

DDR_B_DQS#3
DDR_B_DQS3

modify R03

DDR_B_D30
DDR_B_D31

Layout Note:
Place near JDIMM2
+1.5V

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
+3VS

+3VS

1
2

1
2
2

C167
2.2U_0603_6.3V6K

1

DDR_B_D56
DDR_B_D57
C166
0.1U_0402_16V4Z

R129
10K_0402_5%

DDR_B_D50
DDR_B_D51

DDR_B_D58
DDR_B_D59

+0.75VS
1

A

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2
1

1
2

1
2

2

2

1

DDR_B_D44
DDR_B_D45

R120
1K_0402_1%

1

2
DDR_B_D38
DDR_B_D39

1

DDR_B_D36
DDR_B_D37

2

206

+VREF_CB

1

G2

+0.75VS

B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 11,14
D_CK_SCLK 11,14

+0.75VS

A

10/04 Check footprint ok

TYCO_2-2013287-1
CONN@

2

R130
10K_0402_5%

R119
1K_0402_1%

M_ODT3 6
C163
1U_0402_6.3V6K

DDR_B_D42
DDR_B_D43

Layout Note:
Place near JDIMM2.203,204

C162
1U_0402_6.3V6K

DDR_B_D40
DDR_B_D41

M_ODT3

DDR_CS2_DIMMB# 6
M_ODT2 6

C161
1U_0402_6.3V6K

DDR_B_D34
DDR_B_D35

DDR_CS2_DIMMB#
M_ODT2

+1.5V

C160
1U_0402_6.3V6K

B

DDR_B_BS1 6
DDR_B_RAS# 6

C165
0.1U_0402_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_B_BS1
DDR_B_RAS#

C164
2.2U_0603_6.3V6K

DDR_B_D32
DDR_B_D33

M_CLK_DDR3
M_CLK_DDR#3

2

DDR_B_MA13
DDR_CS3_DIMMB#

6 DDR_CS3_DIMMB#

C

@

+

DDR_B_MA2
DDR_B_MA0

1

DDR_B_WE#
DDR_B_CAS#

6 DDR_B_WE#
6 DDR_B_CAS#

C159
330U_D2_2V_Y

6 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

C158
0.1U_0402_16V4Z

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA6
DDR_B_MA4

C157
10U_0603_6.3V6M

6 M_CLK_DDR2
6 M_CLK_DDR#2

DDR_B_MA11
DDR_B_MA7

C156
10U_0603_6.3V6M

DDR_B_MA3
DDR_B_MA1

DDR_B_MA15
DDR_B_MA14

C155
10U_0603_6.3V6M

DDR_B_MA8
DDR_B_MA5

DDR_CKE3_DIMMB 6
C154
10U_0603_6.3V6M

DDR_B_MA12
DDR_B_MA9

DDR_CKE3_DIMMB

C153
10U_0603_6.3V6M

DDR_B_BS2

6 DDR_B_BS2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

C152
10U_0603_6.3V6M

C

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2

DDR_CKE2_DIMMB

6 DDR_CKE2_DIMMB



DIMM_B Reverse type H:4mm
5

Compal Secret Data

Security Classification

4

Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
DDRIII DIMMB

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

12

of

59

5

4

3

2

1

PCH_RTCX1

Modify 03
Link CIS symbol D44

+RTCCONN

RTCX2

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

L34

HDA_SPKR

42 HDA_SPKR

42 HDA_SDIN0

HDA_RST#

K34

HDA_RST#

HDA_SDIN0

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
HDA_SDOUT

+3VALW_PCH
R143

2

1 1K_0402_5% HDA_SYNC

N32
R153
51_0402_5%
2
1

On Die PLL VR Select is supplied by
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

PAD
PAD

42 HDA_BITCLK_AUDIO
42 HDA_SYNC_AUDIO
B

42 HDA_RST_AUDIO#
42 HDA_SDOUT_AUDIO

A36
C36

This signal has a weak internal pull-down

*

R147
33_0402_5%
1
2 HDA_BIT_CLK
R148
33_0402_5%
1
2 HDA_SYNC_R
R151
33_0402_5%
1
2 HDA_RST#
R155
33_0402_5%
1
2 HDA_SDOUT_R

PAD

T84 @
T85 @
T86 @

PCH_JTAG_TCK

J3

PCH_JTAG_TMS

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

D36

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

E36
K36

HDA_SDO
HDA_DOCK_EN# / GPIO33

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AM3
AM1
AP7
AP5

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI

SATAICOMPI

JTAG_TDO
SATA3COMPI

PCH_SPI_CS#

T3
Y14
T1

PCH_SPI_SI

V4

PCH_SPI_SO

U3

39
39
39
39

2

SPI_CLK

SATA3RBIAS

SPI_MOSI

1
CONN@

20101011 add

+3VS
SERIRQ

SERIRQ 39
SATA_PRX_DTX_N0 34
SATA_PRX_DTX_P0 34
SATA_PTX_DRX_N0 34
SATA_PTX_DRX_P0 34

HDD

SERIRQ

R134

2

1 10K_0402_5%

PCH_SATALED#

R136

2

1 10K_0402_5%

PCH_GPIO21

R139

2

1 10K_0402_5%

PCH_GPIO19

R783

2

1 4.7K_0402_5%

Debug Port DG 1.2 PH 4.7K +3VS

SATA_PRX_DTX_N2 34
SATA_PRX_DTX_P2 34
SATA_PTX_DRX_N2 34
SATA_PTX_DRX_P2 34

C

ODD

SPI ROM FOR ME ( 4MByte )
+3VS
PCH_SPI_WP#

If use SPI programmer,
R146 should be open
(Normal is pop)

Y3
Y1
AB3
AB1

+3VS

R146
0_0402_5%
1
2

R142 1

2

3.3K_0402_5%

PCH_SPI_HOLD# R144 1

2

3.3K_0402_5%

Please short PJP35

R156
37.4_0402_1%
1
2

SATA_COMP

+1.05VS_PCH

AB12

AH1

SATA3_COMP
RBIAS_SATA3

R157
49.9_0402_1%
1
2
1

R162

R145
0_0402_5%
1
2PCH_SPI_SO

+3V_DSW_SPI
PCH_SPI_SO_R

C172

Y11

AB13

SUYIN_060003HA002G202ZL

0.1U_0402_16V4Z


1

2
U4

0.1U_0402_16V4Z
+1.05VS_PCH

8
3

PCH_SPI_HOLD# 7
PCH_SPI_CS# 1
R149
PCH_SPI_CLK 1
R150
PCH_SPI_SI 1
R154

2
750_0402_1%

SPI_CS0#
SPI_CS1#

C859

LPC_FRAME# 39

Y7
Y5
AD3
AD1

Y10

20mil

PCH_SPI_WP#
SATA3RCOMPO

PCH_SPI_CLK

V5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

+

D44
BAV70W_SOT323-3
1

FWH4 / LFRAME#

LPC

HDA_SYNC
SPKR

HDA_SDO

*

HDA_BCLK

T10

HDA_SDOUT

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SATA 6G

N34

HDA_SYNC

C38
A38
B37
C37

SERIRQ

SATA

HDA_BIT_CLK

1

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

RTCX1

D

20mil

2

C20

RTC

1

PCH_RTCX2

IHDA

39 HDA_SDO

A20

JTAG

C

2

ME

+3VALW_PCH

@ R140
1K_0402_5%
2
1
R141
0_0402_5%
2
1

2

HDA_SPKR

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

PCH_RTCX1

PCH_SPI_CS#_R
2
0_0402_5%
PCH_SPI_CLK_R
2
0_0402_5%
PCH_SPI_SI_R
2
0_0402_5%

1
6
5

VCC

VSS

4

W
HOLD
S
C
D

Q

2

B

PCH_SPI_SO_R

MX25L3205DM2I-12G SOP 8P

SPI

*

2 1K_0402_5%

1

C171
1U_0603_10V4Z

1

(INTVRMEN should always be pull high.)
+3VS

1

INTVRMEN

U3A

JME1
SHORT PADS

C170
1U_0603_10V4Z
1
2
R137 20K_0402_5%
1
2
R138 20K_0402_5%

Integrated VRM enable
* LH：：Integrated
VRM disable

@

+RTCVCC

2

PCH_INTVRMEN

2

SM_INTRUDER#

2 330K_0402_5%

JBATT1

+RTCCONN_R

+RTCVCC

JCMOS1
SHORT PADS

2 1M_0402_5%

R133 1

R135 1

2
2

CMOS

+RTCVCC
R132 1

+RTCCONN

R795
1K_0402_5%

C169
18P_0402_50V8J
3 1

1

+CHGRTC

2

1

4
OSC
NC

OSC
2

NC

1
2

D

C168

32.768KHZ_12.5PF_Q13MC14610002

18P_0402_50V8J

Y1

PCH_RTCX2

2
10M_0402_5%

3

1
R131

SATALED#
SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

PCH_GPIO19

P/N:SA00003K800

PCH_SATALED# 41

@ C173
@ R158
22P_0402_50V8J
33_0402_5%
2
1
1
2 PCH_SPI_CLK_R

COUGARPOINT_FCBGA989~D

Reserve for EMI please close to UH1

Prevent back drive issue.

Prevent back drive issue.

3

HDA_SDOUT_R

3

2

1

2
A

@ R768
0_0402_5%

1

@ R152
0_0402_5%

Q65
BSS138_NL_SOT23-3
1 HDA_SDOUT
D

S

D

S
1
A

G

G

HDA_SYNC_R

+3VS

Q10
BSS138_NL_SOT23-3
1 HDA_SYNC

2

+3VS
2

No PCH XDP
Delete JTAG_TMS,PCH_JTAG_TDI,JTAG_TD0

R747
1M_0402_5%

Compal Secret Data

2

Security Classification
Issued Date

9/29 DG1.5

5

4

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

13

of

59

5

4

3

2

1

+3VALW_PCH

U3B

BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34

C179
C180

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

C181
C182

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

+3VS
R175

2

1 10K_0402_5%

PCH_GPIO18

R176

2

1 10K_0402_5%

PCH_GPIO20

2

1 10K_0402_5%

PCH_GPIO73

+3VALW_PCH
R178
R180

2

1 10K_0402_5%

PCH_GPIO25

R181

2

1 10K_0402_5%

PCH_GPIO26

R182

2

1 10K_0402_5%

PCH_GPIO44

R183

2

1 10K_0402_5%

PCH_GPIO45

R184

2

1 10K_0402_5%

PCH_GPIO46

BE34
BF34
BB32
AY32

PERN2
PERP2
PETN2
PETP2

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

Y40
Y39

C

PCH_GPIO73

37 CLK_PCIE_MINI1#
37 CLK_PCIE_MINI1

Mini Card

37 MINI1_CLKREQ#

R187

44 USB30_CLKREQ#

2
2

1 0_0402_5%
1 0_0402_5%

CLK_MINI1#
CLK_MINI1

2

1 0_0402_5%

PCH_GPIO18

J2
AB49
AB47
M1

2
2

1 0_0402_5%
1 0_0402_5%

CLK_USB30#
CLK_USB30

R190

2

1 0_0402_5%

PCH_GPIO20

V10

R191
R192

1
1

2 0_0402_5%
2 0_0402_5%

CLK_LAN#
CLK_LAN

Y37
Y36

R193

1

2 0_0402_5%

PCH_GPIO25

A8

R194
R195

1
1

2 0_0402_5%
2 0_0402_5%

CLK_CARD#
CLK_CARD

Y43
Y45

R198

1

2 0_0402_5%

PCH_GPIO26

L12

R188
R189

44 CLK_PCIE_USB30#
44 CLK_PCIE_USB30

USB3.0

R185
R186

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

AA48
AA47

C9

PCH_SMBDATA

SMBDATA

PERN3
PERP3
PETN3
PETP3

BG37
BH37
AY36
BB36

PCH_SMBCLK

SML0ALERT# / GPIO60
SML0CLK

DRAMRST_CNTRL_PCH

R167

1

2

1K_0402_5%

PCH_SMBDATA 37

PCH_SMBCLK

R168

1

2

2.2K_0402_5%

PCH_SMBDATA

R169

1

2

DRAMRST_CNTRL_PCH 6,11,12

2.2K_0402_5%

PCH_GPIO74

R170

1

2

10K_0402_5%

PCH_SML1CLK

R171

1

2

2.2K_0402_5%

PCH_SML1DATA

R172

1

2

2.2K_0402_5%

PCH_GPIO47

R174

1

2

10K_0402_5%

D

SML1ALERT# / PCHHOT# / GPIO74

C13

PCH_GPIO74

SML1CLK / GPIO58

E14

PCH_SML1CLK

M16

PCH_SML1DATA

For DDR
+3VS

CL_CLK1
CL_DATA1
CL_RST1#

M7

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

R177
4.7K_0402_5%
1
2
+3VS

PCH_SMBDATA 6

T11
P10

3

C

+3VS
CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

PCIECLKRQ1# / GPIO18

AM12
AM13

CLK_CPU_DPLL#
CLK_CPU_DPLL

BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

Pull up at EC side.

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20

CLK_CPU_DPLL# 5
CLK_CPU_DPLL 5

120MHz for eDP.

PCH_SML1DATA 6

38 CARD_CLKREQ#

V45
V46
PCH_GPIO44

L14

CLKIN_DMI2_N
CLKIN_DMI2_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

CLK_VGA#
CLK_VGA

AB42
AB40

PEG_CLKREQ#_R

E6
V40
V42

PCH_GPIO45

T13
V38
V37

PCH_GPIO46
CLK_CPU_ITP# R212 2
CLK_CPU_ITP R213 2

CLK_CPU_ITP#
CLK_CPU_ITP

@
@

1 0_0402_5%
1 0_0402_5%

K12

CLK_BCLK_ITP# AK14
CLK_BCLK_ITP AK13

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

CLK_PCI_LPBACK 17

Y47

XCLK_RCOMP

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

K43
F47

CLK_FLEX0
CLK_27M_TCLK_R

@

T12

2
2

10K_0402_5%
10K_0402_5%

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R201
R202

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

R203
R204

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_ICH_14M

R207

1

2

10K_0402_5%

R748 1

1
R209

PAD
@

2 22_0402_5%

2

CLK_27M_TCLK 22

H47
K49

DGPU_PRSNT#

C183
12P_0402_50V8J

+3VS

1
R216

GPIO67

1

S

1

D

2

Pull high @ VGA side

R220
1
2
0_0402_5%
OPT@
R222
@
2.2K_0402_5%

0
1

2

CLK_PCI_LPBACK

@ C185
22P_0402_50V8J
1
2

@ R219
33_0402_5%
2
1

@ C186
22P_0402_50V8J
1
2

A

Reserve for EMI please close to U3

PEG_CLKREQ# 22

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK

2

R221
@
2.2K_0402_5%

for safe

OPTIMUS
UMA

@ R215
33_0402_5%
2
1

1

2
G

2

OPT@
Q13
2N7002H_SOT23-3

CLK_BUF_ICH_14M
R218
10K_0402_5%
OPT@

DGPU_PRSNT#

10K_0402_5%

3

C184
12P_0402_50V8J

2

DGPU_PRSNT#

VGA_ON 17,25,46,55

1

Modify R02

1

25MHZ_12PF_X5H025000DC1H-H

1
R214
10K_0402_5%
UMAO@

PEG_CLKREQ#_R

B

2
1M_0402_5%
Y2

+3VALW_PCH

5

1
1

R199
R200

XTAL25_OUT
CLKOUTFLEX0 / GPIO64

COUGARPOINT_FCBGA989~D

A

R196
R197

CLKIN_DMI2#
CLKIN_DMI2

XTAL25_IN

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P

EC_SMB_CK2 22,39

+1.05VS_PCH

R208
90.9_0402_1%
1
2

PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP

EC_SMB_CK2

4

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

1

2 0_0402_5%
2 0_0402_5%

1
1

FLEX CLOCKS

R205
R206

3

Q12B
DMN66D0LDW-7_SOT363-6

B

22 CLK_PEG_VGA#
22 CLK_PEG_VGA

EC_SMB_DA2 22,39

1

Card Reader

CLKOUT_PCIE3N
CLKOUT_PCIE3P

EC_SMB_DA2

1

Q12A
DMN66D0LDW-7_SOT363-6

2

38 CLK_PCIE_CARD#
38 CLK_PCIE_CARD

D_CK_SCLK 11,12

AB37
AB38

2

35 LAN_CLKREQ#

D_CK_SCLK

4

PCH_SML1CLK
35 CLK_PCIE_LAN#
35 CLK_PCIE_LAN

PCIE LAN

D_CK_SDATA 11,12

R179
4.7K_0402_5%
1
2 +3VS

Q11B
DMN66D0LDW-7_SOT363-6

PCH_GPIO47

M10

D_CK_SDATA

1

Q11A
DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

CLKOUT_PCIE0N
CLKOUT_PCIE0P

CLKOUT_PCIE1N
CLKOUT_PCIE1P

10K_0402_5%

C8
G12

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

2

PCH_SMBCLK 37

DRAMRST_CNTRL_PCH

A12

SML0DATA

SML1DATA / GPIO75

LID_SW_OUT# 39

1

5

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

H14

R173

2

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

SMBCLK

LID_SW_OUT#

5

1
1

SMBALERT# / GPIO11

LID_SW_OUT#

2

44 PCIE_PRX_DTX_N4
44 PCIE_PRX_DTX_P4
44 PCIE_PTX_C_DRX_N4
44 PCIE_PTX_C_DRX_P4

USB3.0

C177
C178

SMBUS

38 PCIE_PRX_DTX_N3
38 PCIE_PRX_DTX_P3
38 PCIE_PTX_C_DRX_N3
38 PCIE_PTX_C_DRX_P3

Card Reader

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

E12

Link

D

1
1

PERN1
PERP1
PETN1
PETP1

Controller

37 PCIE_PRX_DTX_N2
37 PCIE_PRX_DTX_P2
37 PCIE_PTX_C_DRX_N2
37 PCIE_PTX_C_DRX_P2

Mini Card

C175
C176

BG34
BJ34
AV32
AU32

CLOCKS

PCIE LAN

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCI-E*

35 PCIE_PRX_DTX_N1
35 PCIE_PRX_DTX_P1
35 PCIE_PTX_C_DRX_N1
35 PCIE_PTX_C_DRX_P1

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

14

of

59

5

4

3

2

1

D

D

U3C

VGATE

IN1

2

IN2

3

54

GND

39 PCH_PWROK

1

VCC

5
C

R228

2

OUT

4 SYS_PWROK

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

4
4
4
4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

4
4
4
4

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

+1.05VS_PCH

SYS_PWROK

DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

1
R226
1
R227

U5 @
MC74VHC1G08DFT2G_SC70-5

1 10K_0402_5%

BC24
BE20
BG18
BG20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

PAD

2 XDP_DBRESET#_R
0_0402_5%

1

5 XDP_DBRESET#

SUSACK#_R

T90

R229

SYS_PWROK
PCH_PWROK
1
R233

Modify R02
Delete R231 between SUSACK#_R and SUSWARN#_R

2

PCH_PWROK_R
0_0402_5%

1

39 PCH_RSMRST#

R237

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

AW16

FDI_INT

DMI_ZCOMP

FDI_FSYNC0

AV12

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

BC10

FDI_FSYNC1

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

C12
K3
P12
L22

PM_DRAM_PWRGD B13
PCH_RSMRST#_R
2
0_0402_5%

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BJ24

L10

5 PM_DRAM_PWRGD

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BG25

4mil width and place
within 500mil of the
PCH

SYS_PWROK

FDI

+3VS

4
4
4
4

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

2 0_0402_5%

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

C21

SUSWARN#_R

K16

PBTN_OUT#_R
2
0_0402_5%

E20

System Power Management

R223

4
4
4
4

SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

DSWVRMEN
DPWROK
WAKE#

A18

DSWODVREN

E22
B9

PCH_RSMRST#_R
R230
0_0402_5%
WAKE#
1
2

N3

PCH_GPIO32

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

4
4
4
4
4
4
4
4

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

4
4
4
4
4
4
4
4

+RTCVCC

FDI_INT 4

DSWODVREN

FDI_FSYNC0

4

FDI_FSYNC1

4

FDI_LSYNC0

4

FDI_LSYNC1

4

*

R224

2

R225

2

1 330K_0402_5%
@

1 330K_0402_5%

：
：

DSWODVREN - On Die DSW VR Enable
H Enable
L Disable

C

not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
PCH_PCIE_WAKE# 35,37,44
+3VALW_PCH

CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

G8
N14
D10

SUS_STAT#
SUSCLK

T15

PAD

R235
0_0402_5%
2
1

WAKE#

R232

1

2 10K_0402_5%

PCH_GPIO29

R234

1

2 10K_0402_5%
+3VS

R750 1

SUSCLK_R 39
T16

PAD

T17

PAD

T18

PAD

PM_SLP_S5#

PCH_GPIO32

PM_SLP_S5# 39

R236

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

PM_SLP_A#

T91

PAD

Can be left NC when IAMT is not
support on the platfrom

G16

PM_SLP_SUS#

T19

PAD

T20

PAD

not support Deep S4,S5 can NC
PCH EDS1.2 P.74

AP14

H_PM_SYNC

K14

PCH_GPIO29

2 8.2K_0402_5%
1

@

2 10K_0402_5%

EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)

PM_SLP_S4# 39
PM_SLP_S3# 39

+3VS
B

R239

2

1 200_0402_5%

1
R238

39 PBTN_OUT#

PM_DRAM_PWRGD

PWRBTN#

SLP_A#

D2
1

39,46,48 ACIN
+3VALW_PCH

2

PCH_ACIN

RB751V-40_SOD323-2
PCH_GPIO72

R240

2

1 10K_0402_5%

SUSWARN#_R

R241

2

1 200K_0402_5%

PCH_ACIN

R242

2

1 10K_0402_5%

PCH_GPIO72

R243

2

1 10K_0402_5%

RI#

R244

2

1 10K_0402_5%

PCH_RSMRST#_R

RI#

H20
E10
A10

ACPRESENT / GPIO31
BATLOW# / GPIO72

SLP_SUS#
PMSYNCH

RI#

SLP_LAN# / GPIO29

B

H_PM_SYNC 5

COUGARPOINT_FCBGA989~D

Modify R02

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM,

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

15

of

59

5

ENBKL

ENBKL R245

2

3

2

1

IGPU_BKLT_EN

1 0_0402_5%
2

39

4

D

D

1

R246
100K_0402_5%

U3D
J47
M45

31 DPST_PWM

P45

L_BKLTCTL

31 PCH_LCD_CLK
31 PCH_LCD_DATA

T40
K47

L_DDC_CLK
L_DDC_DATA

T45
P39

L_CTRL_CLK
L_CTRL_DATA

2.37K_0402_1%
2
1

LVDS_IBG

AF37
AF36

LVD_IBG
LVD_VBG

LVD_VREF

AE48
AE47

LVD_VREFH
LVD_VREFL

PCH_TXCLKPCH_TXCLK+

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

+3VS
R248

1

2 2.2K_0402_5%

CTRL_CLK

R250

1

2 2.2K_0402_5%

CTRL_DATA

R249

0_0402_5%
2
1

31 PCH_TXCLK31 PCH_TXCLK+
31 PCH_TXOUT031 PCH_TXOUT131 PCH_TXOUT2-

C

31 PCH_TXOUT0+
31 PCH_TXOUT1+
31 PCH_TXOUT2+

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AF40
AF39

+3VS
R251

1

2 2.2K_0402_5%

PCH_CRT_CLK

R252

1

2 2.2K_0402_5%

PCH_CRT_DATA

R253

1

2 150_0402_1%

PCH_CRT_B

R254

1

2 150_0402_1%

PCH_CRT_G

R255

1

2 150_0402_1%

PCH_CRT_R

AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43

32 PCH_CRT_B
32 PCH_CRT_G
32 PCH_CRT_R
32 PCH_CRT_CLK
32 PCH_CRT_DATA

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

N48
P49
T49

PCH_CRT_CLK
PCH_CRT_DATA

T39
M40

PCH_CRT_HSYNC
PCH_CRT_VSYNC

M47
M49

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSB_CLK#
LVDSB_CLK

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD

B

32 PCH_CRT_HSYNC
32 PCH_CRT_VSYNC
+3VS

2 2.2K_0402_5%

PCH_LCD_DATA

T43
T42

DAC_IREF
CRT_IRTN

SDVO_SCLK
SDVO_SDATA

P38
M39

AT49
AT47
AT40 PCH_DPB_HPD
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

SDVO_SCLK 33
SDVO_SDATA 33

PCH_DPB_HPD 33
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

33
33
33
33
33
33
33
33

HDMI D2
HDMI D1

C

HDMI D0
HDMI CLK

P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
B

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

COUGARPOINT_FCBGA989~D
R256
1K_0402_0.5%
2

@ C485
10P_0402_50V8J

2

2

@ C484
10P_0402_50V8J

1

PCH_LCD_CLK

1

R471 1

2 2.2K_0402_5%

1

CRT_IREF

R470 1

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC

AP43
AP45

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK
SDVO_CTRLDATA

Digital Display Interface

R247

SDVO_TVCLKINN
SDVO_TVCLKINP

LVDS

CTRL_CLK
CTRL_DATA

L_BKLTEN
L_VDD_EN

CRT

IGPU_BKLT_EN
31 PCH_ENVDD

+3VS

R529 1 UMA@ 2 2.2K_0402_1%

SDVO_SCLK

R530 1 UMA@ 2 2.2K_0402_1%

SDVO_SDATA

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

16

of

59

5

4

3

1

8.2K_0804_8P4R_5%
RP3

Modify R02

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

8.2K_0804_8P4R_5%

1

2 8.2K_0402_5%

R259 1

2 100K_0402_5%

DGPU_HOLD_RST#
PLT_RST#

C

14,25,46,55 VGA_ON

Boot BIOS Strap bit1 BBS1
Bit11 Bit10
GNT1#/
GPIO51

0

1

Boot BIOS
Destination
Reserved

1

0

PCI

1

1

SPI

0

0

34 ODD_DA#

LPC

PAD

CLK_PCI_LPBACK
CLK_PCI_LPC
1

2

DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON

C46
C44
E40

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44
K10

PLT_RST#

1 22_0402_5%
2 22_0402_5%
T22 @
T23 @
T24 @

2
1
PAD
PAD
PAD

@ C861
10P_0402_50V8J

2

@ C860
10P_0402_50V8J

R263
R264
1

K40
K38
H38
G38

T21 @

5,35,38,39,44 PLT_RST#
14 CLK_PCI_LPBACK
39 CLK_PCI_LPC

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

C6
H49
H43
J48
K42
H40

NV_ALE
NV_CLE
NV_RCOMP

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1

DF_TVS

DMI Termination Voltage

AV10

NV_RB#

AT8

NV_RE#_WRB0
NV_RE#_WRB1

AY5
BA2

NV_WE#_CK0
NV_WE#_CK1

D

+1.8VS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

USBRBIAS#
USBRBIAS

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

Some PCH config not support USB port 6 & 7.
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

USB20_N8 37
USB20_P8 37
USB20_N9 37
USB20_P9 37
USB20_N10 31
USB20_P10 31

USB20_N12
USB20_P12
USB20_N13
USB20_P13

USB20_N12
USB20_P12
USB20_N13
USB20_P13

37
37
37
37

Mini Card (WLAN)
+3VALW_PCH

Mini Card (3G)
RP4

CMOS Camera (LVDS)

USB_OC0#
USB_OC2#
USB_OC7#
USB_OC5#

Mini Card (SIM card)

4
3
2
1

5
6
7
8

10K_1206_8P4R_5%

Bluetooth

Within 500 mils

USBRBIAS

1
R262

2
22.6_0402_1%

RP5
USB_OC1#
USB_OC4#
USB_OC3#
USB_OC6#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0# 37
USB_OC1# 37

4
3
2
1

5
6
7
8

B

10K_1206_8P4R_5%

5
1

U6

OUT

OPT@ R266
100_0402_5%
1
2

4

2
PLTRST_VGA# 22

IN1
IN2

MC74VHC1G08DFT2G_SC70-5

U7

OUT

4

PLT_RST_BUF# 37
R269
100K_0402_5%
2

IN2

PLT_RST#

VCC

IN1

MC74VHC1G08DFT2G_SC70-5
OPT@

A

H_SNB_IVB# 5

1

2

1
1K_0402_5%

CLOSE TO THE BRANCHING POINT

B33
A14
K20
B17
C16
L16
A16
D14
C14

2
R261

+3VS

5
1

USB/B (Right side)

PME#
PLTRST#

C

R260
2.2K_0402_5%

USB/B (Right side)

@ R265
0_0402_5%
2
1

GND

R267
2 OPT@
0_0402_5%

USB/B (Right side)

COUGARPOINT_FCBGA989~D

OPT@ R268
100K_0402_5%

3

DGPU_HOLD_RST#

37
37
37
37
37
37

DF_TVS

+3VS

1

Set to Vss when LOW

DG1.2 CRB1.0 PH 2.2K series 1K

AT12
BF3

For RF request

PLT_RST#

Set to Vcc when HIGH

DF_TVS

1

R258

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

VCC

PCH_GPIO2
PCH_GPIO53
PCH_GPIO4
ODD_DA#

1
2
3
4

AT10
BC8

GND

8
7
6
5

NV_DQS0
NV_DQS1

1

PCH_GPIO51
PCH_GPIO55
PCH_GPIO5
PCH_GPIO52

1
2
3
4

AY7
AV7
AU3
BG4

2

RP2
8
7
6
5

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

3

D

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

USB

8.2K_0804_8P4R_5%

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

RSVD

PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#

1
2
3
4

PCI

RP1
8
7
6
5

NVRAM

U3E

+3VS

B

2

A

2

Modify R02

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (5/9) PCI, USB, NVRAM

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

17

of

59

5

4

3

2

1

+3VS
+3VS
R279
R643

OPTIMUS_EN#

2 UMAO@ 1 10K_0402_5%
1 OPT@

2 10K_0402_5%

ODD_EN#

R275

1

2 10K_0402_5%

EC_KBRST#

R276

1

2 10K_0402_5%

GPIO38
Board ID

OPTIMUS_EN#

D

*

OPTIMUS
Non-OPTIMUS

0
1

D

PCH_GPIO69

R851

1

2 0_0402_5%

PCH_GPIO70

R852

1

2 0_0402_5%

GPIO28
On-Die PLL Voltage Regulator

：：

This signal has a weak internal pull up

H On-Die PLL voltage regulator enable
L On-Die PLL Voltage Regulator disable

33 DGPU_HPD_INT#
39 EC_SCI#

Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70
C

R277

39 EC_SMI#

44 SMIB

2

1 10K_0402_5%

PCH_GPIO0

1

2 10K_0402_5%

PCH_GPIO1

37 BT_ON#
R280
R281

1

2 10K_0402_5%

PCH_GPIO16

R284

1

2 10K_0402_5%

PCH_GPIO22

R285

1

2 100K_0402_5% WWAN_OFF#

1

2 200K_0402_5% ODD_DETECT#

R287

1

2 10K_0402_5%

PCH_GPIO39

R288

1

2 10K_0402_5%

BT_ON#

R289

1

2 10K_0402_5%

PCH_GPIO48

R290

2 10K_0402_5%

1

ODD_EN#

TACH5 / GPIO69

B41

PCH_GPIO69

DGPU_HPD_INT#

H36

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

EC_SCI#

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

PCH_GPIO71

EC_SMI#

C10

GPIO8

34 ODD_DETECT#
37 WWAN_OFF#

37 WL_OFF#

CRB1.0 PH200K to +3VS

C4

LAN_PHY_PWR_CTRL / GPIO12

SMIB

G2

GPIO15

PCH_GPIO16

U2

SATA4GP / GPIO16

D40
T5

SCLOCK / GPIO22

PCH_GPIO24

E8

GPIO24 / MEM_LED

PCH_GPIO27

E16

PCH_GPIO28

P8

BT_ON#

K1

ODD_DETECT#

V8

WWAN_OFF#

M5

OPTIMUS_EN#

N2

PCH_GPIO39

M3

PCH_GPIO48

V13

WL_OFF#

V3

PCH_GPIO57

D6

PAD

T32 @

A4

PAD

T34 @

A44

PAD

T36 @

A45

PAD

T38 @

A46

WL_OFF#

1

2 10K_0402_5%

PCH_GPIO12

PAD

T40 @

A5

R292

1

2 1K_0402_5%

SMIB

PAD

T42 @

A6

R293

1

2 10K_0402_5%

PCH_GPIO57

PAD

T44 @

B3

R294

1

2 10K_0402_5%

PCH_GPIO24

PAD

T46 @

B47

PAD

T47 @

BD1

PAD

T49 @

BD49

PAD

T51 @

BE1

PAD

T53 @

BE49

PAD

T54 @

BF1

PAD

T56 @

BF49

CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.

+3VS
1

1

2
1

2
1

3
4

5

OPT@
DMN66D0LDW-7_SOT363-6

C871
1U_0402_6.3V6K

2

OPT@

OPT@

DGPU_PWROK
Q78A

2

Q78B
DMN66D0LDW-7_SOT363-6

1

OPT@
R850
100K_0402_5%

A

OPT@
R841
10K_0402_5%

+3VSDGPU

R283
10K_0402_5%

6

2

+3VS

1

TACH0 / GPIO17

PCH_GPIO22

R291

Modify R10

A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#

+3VS
@ T25

PAD

P4

GATEA20 39

AU16

PCH_PECI_R

P5

EC_KBRST#

@
1
2
0_0402_5% R274

AY10

GPIO28
NC_1
STP_PCI# / GPIO34
NC_2
GPIO35
NC_3
SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5

H_PECI 5,39
EC_KBRST# 39

AY11

H_THRMTRIP#
2
390_0402_5%

T14

H_THRMTRIP# 5

INIT3_3V

This signal has weak internal
PU, can't pull low

AH8
AK11
AH10

Intel schematic reviwe recommand.

AK10
P37

SLOAD / GPIO38
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2

@ T28

PAD

BG48

@ T29

PAD

BH3

@ T30

PAD

BH47

@ T31

PAD

BJ4

@ T33

PAD

BJ44

@ T35

PAD

BJ45

@ T37

PAD

BJ46

@ T39

PAD

BJ5

@ T41

PAD

BJ6

@ T43

PAD

C2

@ T45

PAD

C48

@ T87

PAD

D1

@ T48

PAD

D49

@ T50

PAD

E1

@ T52

PAD

E49

@ T88

PAD

F1

@ T55

PAD

F49

@ T89

PAD

B

COUGARPOINT_FCBGA989~D
C872
0.1U_0402_16V4Z

2

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C

H_CPUPWRGD 5
PCH_THRMTRIP#_R 1
R278

GPIO27

VSS_NCTF_18

+3VALW_PCH

ODD_EN# 34

R273
10K_0402_5%

PCH_GPIO12

K4

DGPU_HPD_INT#

R282

R286

B

2 10K_0402_5%

1

C40

TACH1 / GPIO1

DGPU_PWROK

+3VS

R270

TACH4 / GPIO68

A42

PCH_GPIO27

2 10K_0402_5%

1

BMBUSY# / GPIO0

PCH_GPIO1

PCH_GPIO28

2

2 4.7K_0402_5%

@
1
R272
1K_0402_5%

1

@

T7

CPU/MISC

2

U3F
PCH_GPIO0

GPIO

+3VALW_PCH
R485 1

NCTF

*

4

3

2

Title

Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

18

of

59

5

4

3

2

1

Modify R04
L1 -->SHI00003Y00
U3G

Modify R03

1300mA

AP37

2
AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24
AN33
AN34

+3VS

PAD

VCCIO[24]

+VCCAFDI_VRM

AP16

+1.05VS_VCCAPLL_FDI

T77 @

BG6

1

1

1
VCCVRM[3]

AT16

C197
0.1U_0402_10V7K

VCCDMI[1]

AT20

20mA

VCCIO[1]

AB36

C203
1U_0402_6.3V6K

VCCIO[25]
VCCIO[26]

VCCPNAND[1]

190mA VCCPNAND[2]

VCC3_3[3]

VCCVRM[2]
VCCFDIPLL

AG16

0.001

5

0.001

Vcc3_3

3.3

0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.3

VccDMI

1.05

0.042

VccIO

1.05

2.925

VccASW

1.05

1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119

+VCCAFDI_VRM
+1.05VS_PCH

C205
0.1U_0402_10V7K

2

1

BH29

2925mA

5

V5REF_Sus

0.1uH inductor, 200mA

1

VCCIO[18]

V34

2

VCCIO[17]

AN26

VCC3_3[7]

2

VCCIO[16]

AN21

HVCMOS

AN17

VCC3_3[6]

VccSusHDA

3.3 / 1.5

VccVRM

1.8 / 1.5

VCCPNAND[4]

0.01
0.16

AG17

VccCLKDMI
VCCPNAND[3]

C

+1.8VS

AJ16
AJ17

1

1
2

1
2

1
2

1
2

2

C202
1U_0402_6.3V6K

C201
1U_0402_6.3V6K

C200
1U_0402_6.3V6K

C199
1U_0402_6.3V6K

Modify R03

C198
10U_0603_6.3V6M

1

C

VCCIO[15]

V33

V5REF

C206
0.1U_0402_10V7K

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

2

+1.05VS_PCH

AN16

C195
0.01U_0402_16V7K

+3VS

DMI

This pin can be left as no connect in
On-Die VR enabled mode (default).

VCCAPLLEXP

NAND / SPI

BJ22

VCCIO

+VCCAPLLEXP

T57 @

C194
0.01U_0402_16V7K

1

VCCTX_LVDS[4]

C196
22U_0805_6.3V6M

PAD

+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1

+VCCTX_LVDS

VCCIO[28]

0.001

D

AM38
AP36

1.05

+3VS

AM37

60mA VCCTX_LVDS[3]

S0 Iccmax
Current
(A)

V_PROC_IO

C193
10U_0603_6.3V6M

1

VCCTX_LVDS[2]

2

VCCTX_LVDS[1]

Voltage

Voltage Rail

AK37

1

VSSALVDS

AK36

2

2

U47

2

1

CRT

1
2

1
2

1
2

1
2

VSSADAC

1mA VCCALVDS

+1.05VS_PCH
AN19

VCCADAC

+VCCADAC

U48

C192
0.1U_0402_10V7K

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

1mA

C191
0.01U_0402_16V7K

C187
1U_0402_6.3V6K

Modify R03

C190
1U_0402_6.3V6K

D

C189
1U_0402_6.3V6K

C188
10U_0603_6.3V6M

PAD-OPEN 4x4m

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

LVDS

+1.05VS_PCH

1

VCC CORE

@ JP3
2

PCH Power Rail Table

+3VS
L1
4.7UH_LQM18FN4R7M00D_20%
2
1

2

+1.05VS_VCCP

POWER

2

B

C795
1U_0402_6.3V6K

VCCIO[27]
VCCDMI[2]

20mA VCCSPI

V1

+3VS

COUGARPOINT_FCBGA989~D

2

1

AU20

1

AP17

FDI

+1.05VS_PCH

C208
1U_0402_6.3V6K

B

+VCCAFDI_VRM
+1.5VS
R307

2

1

0_0603_5%

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (7/9) PWR

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

19

of

59

4

3

2

1

Have internal VRM

VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
+5VALW

VCCASW[9]
VCCASW[10]

AC31

VCCASW[11]

W33

VCCASW[15]

N16

+VCCAFDI_VRM

Y49

2
1
1

+PCH_V5REF_SUS

2
+3VALW_PCH
+5VS

1mA V5REF

P34

VCCSUS3_3[2]

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

+PCH_V5REF_RUN
+3VALW_PCH

VCC3_3[8]

VCCASW[16]

VCC3_3[4]

C226
1U_0402_6.3V6K

VCC3_3[2]

+PCH_V5REF_RUN
C227
1U_0603_10V6K

AA16
W16
T34

VCCASW[18]

VCCASW[20]

C

D4
RB751V-40_SOD323-2

P22

VCCASW[17]

VCCASW[19]

+3VS

R323
100_0402_5%

+3VS
VCC3_3[1]

C219
0.1U_0603_25V7K

PAD T81 @

AJ2

Place C228 near
Place C233 near
Place C234 near

AA16.W16 pin
T34 pin
AJ2 pin

+1.05VS_PCH

AF13
1

+VCCRTCEXT

1

S

AN24

VCCIO[5]
DCPRTC
VCCIO[12]

AH13
2

VCCVRM[4]

VCCIO[13]

C235
1U_0402_6.3V6K

AH14

2

C236
0.1U_0402_10V7K

1

VCCSUS3_3[1]

1

1
2

1
2

1
2

W31

VCCASW[14]

+VCCA_USBSUS

C228
0.1U_0402_10V7K

W29

VCCASW[13]

DCPSUS[4]

AN23

1mA V5REF_SUS

C233
0.1U_0402_10V7K

W26

VCCASW[12]

M26

+PCH_V5REF_SUS

C234
0.1U_0402_10V7K

W23

C232
1U_0402_6.3V6K

C231
220U_B2_2.5VM_R35

C230
1U_0402_6.3V6K

C229
220U_B2_2.5VM_R35

1

2

AC29

W24

2

1010mA

2

VCCASW[8]

AC27

D3
RB751V-40_SOD323-2

1

AC26

R319
100_0402_5%

+1.05VS_PCH

D

+3VALW_PCH

2

VCCASW[7]

T26

+5VALW_PCH

1

AA31

VCCIO[34]

T23 pin
P24 pin

2

VCCASW[6]

P24

1

VCCASW[5]

AA29

2

2

AA27

V24

VCCSUS3_3[6]

1

VCCASW[4]

VCCSUS3_3[10]

Place C217 near
Place C218 near

2

VCCASW[3]

AA26

V23

1

AA24

T24

VCCSUS3_3[9]

2

1
2

1
2

C225
1U_0402_6.3V6K

C224
1U_0402_6.3V6K

1

VCCASW[2]

35,46 PCH_PWR_EN#

+3VALW_PCH

1

1
2

1
2

C221
22U_0805_6.3V6M

C220
22U_0805_6.3V6M

C223
1U_0402_6.3V6K

2

VCCASW[1]

W21

+1.05VS_VCCA_B_DPL

DCPSUS[3]

AA21

AD29

+1.05VS_VCCA_A_DPL

VCCSUS3_3[8]
VCCIO[14]

AA19

AD31

+

1

T23

2

AL24

VCCAPLLDMI2

T29

2

+VCCSUS1

119mA VCCSUS3_3[7]

USB

AL29

VCCIO[33]

C218
0.1U_0402_10V7K

BH23

+1.05VS_PCH

+

C213
1U_0402_6.3V6K

1

VCC3_3[5]

C

1
2
L6
10UH_LB2012T100MR_20%

VCCIO[32]

T27

+5VALW_PCH

1

2
T38

+1.05VS_PCH

L5
10UH_LB2012T100MR_20%
1
2

P28

1

DCPSUSBYP

+3VS_VCC_CLKF33

T80 PAD

VCCIO[31]

3

2

V12

+1.05VS_PCH
@

P26

1

+PCH_VCCDSW

+VCCAPLL_CPY_PCH

T79 PAD

3mA

VCCDSW3_3

Q64
AO3413L_SOT23-3

N26

C217
0.1U_0402_10V7K

@

T16

VCCIO[30]

PCI/GPIO/LPC

T78 PAD

VCCIO[29]

2

1
@

+1.05VS_PCH

VCCACLK

R752
20K_0402_5%

2

1
2

AD49
C211
0.1U_0402_10V7K

@ R751
0_0603_5%
2
1

C816
0.1U_0402_10V7K

C210
1U_0402_6.3V6K

D

C209
10U_0603_6.3V6M

Modify R03

POWER

U3J

G

+3VALW_PCH

+3VS_VCC_CLKF33

Clock and Miscellaneous

L3
10UH_LB2012T100MR_20%
1
2

2

+VCCACLK

1

+1.05VS_PCH @ R310
0_0603_5%
2
1

@ R309
0_0805_5%
2

1

1

2

+3VS

D

5

B

+1.05VS_VCCA_B_DPL

BF47

VCCVRM[1]
VCCIO[7]
VCCIO[8] 55mA
VCCIO[9]
VCCIO[11]

AK1

+VCCSATAPLL
+VCCAFDI_VRM

AF11

+VCCAFDI_VRM

PAD T82 @

+1.05VS_PCH
VCCIO[2]

95mA

VCCIO[4]

AC16
AC17
AD17

C241
1U_0402_6.3V6K

2

VCCIO[10]

B

AF14

MISC

V_PROC_IO 1mA

VCCASW[22]
VCCASW[23]
VCCASW[21]

T21

+VCCME_22

R335

2

1 0_0603_5%

V21

+VCCME_23

R336

2

1 0_0603_5%

T19

+VCCME_21

R338

2

1 0_0603_5%

P32

+VCCSUSHDA

R339

2

1 0_0603_5%

10mA VCCSUSHDA

1

HDA

COUGARPOINT_FCBGA989~D

C250
0.1U_0402_16V4Z

A

2

1
2

1
2

C249
0.1U_0402_10V7K

C248
0.1U_0402_10V7K

2

VCCRTC

RTC

+3VALW_PCH
A22

C247
1U_0402_6.3V6K

Modify R03

DCPSUS[1]
DCPSUS[2]

CPU

T17
V19

+1.05VS_PCH

DCPSST

+RTCVCC

1

1

2

+1.05VM_VCCSUS

BJ8

2

1

1

1

V16

T83 PAD

C246
0.1U_0402_10V7K

2

@

C245
0.1U_0402_10V7K

C244
4.7U_0603_6.3V6K

2

1

+VCCSST
C242
0.1U_0402_10V7K

2

1

80mA

VCCAPLLSATA

VCCIO[3]
AG33

+1.05VS_PCH

A

VCCADPLLB

80mA

+1.05VS_PCH
C240
1U_0402_6.3V6K

2

2

AF17
AF33
AF34
AG34

+1.05VS_PCH
C238
1U_0402_6.3V6K

C237
1U_0402_6.3V6K

1

+1.05VS_PCH

VCCIO[6]
VCCADPLLA

1

BD47

SATA

+1.05VS_VCCA_A_DPL

Compal Secret Data

Security Classification
2009/12/01

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (8/9) PWR

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

20

of

59

5

4

3

2

1

U3I

D

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

U3H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

C

B

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

COUGARPOINT_FCBGA989~D

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

D

C

B

A

A

COUGARPOINT_FCBGA989~D

Compal Secret Data

Security Classification
2009/12/01

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (9/9) VSS

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

21

of

59

A

B

C

D

E

GS@ U8A

AR16
AR17
AR13

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

14 PEG_CLKREQ#
2
R360
3

AM16
AG21
2
1
R365 OPT@ 2.49K_0402_1%

MIOB_HSYNC_NC
MIOB_VSYNC_NC

150mA

AE9
AF9
AD9

XTALIN
XTALOUT

B1
B2

XTAL_OUTBUFFD1
XTAL_SSIN
D2

under GPU

MIOB_CLKIN_NC
MIOB_CLKOUT_NC

VID_PLLVDD
XTAL_IN
XTAL_OUT

XTALOUT

XTALIN

1

E3
E4

I2CB_SCL
I2CB_SDA

G3
G2

I2CA_SCL
I2CA_SDA

G1
G4

I2CH_SCL
I2CH_SDA

1

Y3 OPT@
27MHZ_16PF_X5H027000FG1H

2

OPT@ C297
18P_0402_50V8J
2

I2CC_SCL
I2CC_SDA

1M_0402_5%

2
1

1 0_0402_5%

@
R370

4

@

E2
E1

OPT@ C298
18P_0402_50V8J

F6
G6

I2CS_SCL
I2CS_SDA
I2CC_SCL
I2CC_SDA
I2CB_SCL
I2CB_SDA
I2CA_SCL
I2CA_SDA
I2CH_SCL
I2CH_SDA

GPU_VID2

IN

OVERT

GPIO9

IN

ALERT

GPIO12

IN

AC/DC detection

GPIO18

IN

Reserve for VPS

2

NV_PERFORMANCE 39

2
I2CS_SCL

1

6

EC_SMB_CK2 14,39

Q16A OPT@
DMN66D0LDW-7_SOT363-6
+3VSDGPU

I2CS_SDA

4

3

EC_SMB_DA2 14,39
2

Q16B OPT@
DMN66D0LDW-7_SOT363-6

+3VSDGPU

N3
L3

I2CS_SCL
I2CS_SDA
I2CH_SCL
I2CH_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA

R343
R344
R345
R346
R347
R348
R349
R350

W1
W2

I2CA_SCL
I2CA_SDA

R351 1 OPT@
R352 1 OPT@

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

2 2.2K_0402_5%
2 2.2K_0402_5%

External Spread Spectrum

N4
R4

R359 1 OPT@

2 10K_0402_5%

AE1
V4

R362 1 OPT@

2 10K_0402_5%

OSC_OUT

1

OSC_OUT

REFOUT
XOUT

VSS
MODOUT

R356 1

@

XTAL_OUTBUFF

22_0402_5%

2

R357
10K_0402_5%
OPT@

6
5

OSC_SPREAD

3

XIN/CLKIN

VDD

4

+3VSDGPU

@ ASM3P2872AF-06OR_TSOT-23-6

3

@
C283
0.1U_0402_16V4Z

OSC_SPREAD R361 1

@

XTAL_SSIN

2 22_0402_5%

R364
10K_0402_5%
OPT@

If External Spread Spectrum not stuff then stuff resistor

DACA_RED
DACA_GREEN
DACA_BLUE

AM13
AL13
AJ12
AK12
AK13

Option Component
R367 1 OPT@ 2 10K_0402_5%
@ C814
0.1U_0402_16V4Z
1
2
@ R744 1
2 124_0402_1%

U8

AK4
AL4
AJ4

DACB_RED
DACB_GREEN
DACB_BLUE

N12P-GV-OP-B-A1_BGA973
GV@

AM1
AM2

DACB_HSYNC
DACB_VSYNC

AG7
AK6
AH7

DACB_VDD
DACB_VREF
DACB_RSET

SA00004JO10

OPT@
R368 2
1 10K_0402_5%
@ C296
0.1U_0402_16V4Z
1
2
@ R369 1
2 124_0402_1%

4

N12P-GS-A1_BGA973

Compal Secret Data

Security Classification
Issued Date

2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

OUT

GPIO8

AM15
AM14
AL14

DACA_VDD
DACA_VREF
DACA_RSET

I2C
DACs

R753 2

I2CS_SCL
I2CS_SDA

GPIO7

AA7
AA6

MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC

XTAL_OUTBUFF
XTAL_SSIN

GPU_VID1

U5
T5

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

SP_PLLVDD

OUT

+3VSDGPU

T4
W4

DACA_HSYNC
DACA_VSYNC

14 CLK_27M_TCLK

1

Q68 OPT@
2N7002H_SOT23-3

2

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

PLLVDD

GPU_VID0

GPIO6

U9

MIOA_CLKIN_NC
MIOA_CLKOUT_NC

PEX_RST_N
PEX_TERMP

3

Modify R02, changed location of the pull-up
resistor (R342) from U8.H6 to net
NV_PERFORMANCE_R.

Y5
W3
AF1

MIOB_DE_NC
MIOB_CTL3_NC
MIOB_VREF_NC

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

HPD_C

OUT

1

1 OPT@ 2
R342
10K_0402_5%
NV_PERFORMANCE_R

IN

GPIO5

N2
P5
N5

MIOA_DE_NC
MIOA_CTL3_NC
MIOA_VREF_NC

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

@
1
R763
0_0402_5%

2

GPIO1

5

GPIO
PCI EXPRESS
DVO

MIOA_HSYNC_NC
MIOA_VSYNC_NC

2 OPT@ 1
R762
0_0402_5%

FUNCTION

2

OPT@ C290
0.1U_0402_16V4Z

OPT@ C289
0.1U_0402_16V4Z
2
1

OPT@ C288
0.1U_0402_16V4Z
2
1

+GPU_PLLVDD

OPT@ C287
0.1U_0402_16V4Z
2
1

@ C286
4700P_0402_25V7K
2
1

2

1

OPT@ L8
2
1
BLM18PG300SN1D_2P

OPT@ C285
10U_0603_6.3V6M
2
1

1
2

OPT@ C284
22U_0805_6.3V6M

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

+3VSDGPU

2

17 PLTRST_VGA#

+1.05VSDGPU

AJ17
AJ18
1
OPT@ 200_0402_1%

MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

39,55
39,55
55
+3VSDGPU

I/O

1

2
10K_0402_5%

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

R340 2 OPT@
R341 2 OPT@

GPU_VID0
GPU_VID1
GPU_VID2
1 10K_0402_5%
1 10K_0402_5%

GPIO

2

R358

PEG_GTX_HRX_P0 AL17
PEG_GTX_HRX_N0 AM17
PEG_GTX_HRX_P1 AM18
PEG_GTX_HRX_N1 AM19
PEG_GTX_HRX_P2 AL19
PEG_GTX_HRX_N2 AK19
PEG_GTX_HRX_P3 AL20
PEG_GTX_HRX_N3 AM20
PEG_GTX_HRX_P4 AM21
PEG_GTX_HRX_N4 AM22
PEG_GTX_HRX_P5 AL22
PEG_GTX_HRX_N5 AK22
PEG_GTX_HRX_P6 AL23
PEG_GTX_HRX_N6 AM23
PEG_GTX_HRX_P7 AM24
PEG_GTX_HRX_N7 AM25
PEG_GTX_HRX_P8 AL25
PEG_GTX_HRX_N8 AK25
PEG_GTX_HRX_P9 AL26
PEG_GTX_HRX_N9 AM26
PEG_GTX_HRX_P10AM27
PEG_GTX_HRX_N10AM28
PEG_GTX_HRX_P11 AL28
PEG_GTX_HRX_N11 AK28
PEG_GTX_HRX_P12 AK29
PEG_GTX_HRX_N12 AL29
PEG_GTX_HRX_P13AM29
PEG_GTX_HRX_N13AM30
PEG_GTX_HRX_P14AM31
PEG_GTX_HRX_N14AM32
PEG_GTX_HRX_P15 AN32
PEG_GTX_HRX_N15 AP32

OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

VGA_HDMI_DET 33

1

1 OPT@

+3VSDGPU

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC
MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

R514 1 OPT11@2 100K_0402_5%

1

4 PEG_GTX_C_HRX_P[0..15]

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
M7

D

4 PEG_GTX_C_HRX_N[0..15]

C251
C252
C253
C254
C255
C256
C257
C258
C259
C260
C261
C262
C263
C264
C265
C266
C267
C268
C269
C270
C271
C272
C273
C274
C275
C276
C277
C278
C279
C280
C281
C282

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

S

2

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_N15

Part 1 of 7

G

4
4
4
4
4
4
4
4
4
4
4
4

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

CLK

1

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

4 PEG_HTX_C_GRX_P0
4 PEG_HTX_C_GRX_N0
4 PEG_HTX_C_GRX_P1
4 PEG_HTX_C_GRX_N1
4 PEG_HTX_C_GRX_P2
4 PEG_HTX_C_GRX_N2
4 PEG_HTX_C_GRX_P3
4 PEG_HTX_C_GRX_N3
4 PEG_HTX_C_GRX_P4
4 PEG_HTX_C_GRX_N4
4 PEG_HTX_C_GRX_P5
4 PEG_HTX_C_GRX_N5
4 PEG_HTX_C_GRX_P6
4 PEG_HTX_C_GRX_N6
4 PEG_HTX_C_GRX_P7
4 PEG_HTX_C_GRX_N7
4 PEG_HTX_C_GRX_P8
4 PEG_HTX_C_GRX_N8
4 PEG_HTX_C_GRX_P9
4 PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

B

C

D

Title

Compal Electronics, Inc.
N12P PEG 1/9

Size Document Number
Custom LA-7221P
Date:

Rev
0.2
Sheet

Wednesday, February 16, 2011
E

22

of

59

A

VRAM Interface

MDA[15..0]

27 MDA[15..0]
27 MDA[31..16]
28 MDA[47..32]
28 MDA[63..48]

MDA[31..16]

29 MDC[15..0]

MDA[47..32]

29 MDC[31..16]

MDA[63..48]

30 MDC[47..32]

MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]

30 MDC[63..48]

GS@ U8B

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N

FB_DLLAVDD_0
FB_PLLAVDD_0
FB_DLLAVDD_1
FB_PLLAVDD_1

FBA_CLK0
FBA_CLK0_N

FB_VREF_NC
FBA_DEBUG0
FBA_DEBUG1

FBA_CLK1
FBA_CLK1_N

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

DQMA[3..0] 27

DQMA[7..4] 28

DQSA#[3..0] 27

DQSA#[7..4] 28

DQSA[3..0] 27

DQSA[7..4] 28

P29
R29
L29
M29
AG29
AH29
AD29
AE29
T32
T31
AC31
AC30

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

MEMORY INTERFACE C

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

OPT@1
2
40.2_0402_1%
R371
OPT@1
2
40.2_0402_1%
R372
OPT@1
2
60.4_0402_1%
R373
FBB_DEBUG0
FBB_DEBUG1

CLKA0 27
CLKA0# 27
CLKA1 28
CLKA1# 28

K27
L27
M27
G19
G16

N12P-GS-A1_BGA973

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

A16
D10
F11
D15
D27
D34
A34
D28

DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7

B14
B10
D9
E14
F26
D31
A31
A26

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

+1.5VSDGPU
FBCAL_PD_VDDQ
FBCAL_PU_GND

FBC_CLK0
FBC_CLK0_N

FBCAL_TERM_GND
FBC_DEBUG0
FBB_DEBUG1

FBC_CLK1
FBC_CLK1_N

DQMC[3..0] 29

DQMC[7..4] 30

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

C14
A10
E10
D14
E26
D32
A32
B26

29

DQSC#[7..4]

30

DQSC[3..0]

29

DQSC[7..4]

30

1

G14
G15
G11
G12
G27
G28
G24
G25
E17
D17

CLKC0 29
CLKC0# 29

D23
E23

CLKC1 30
CLKC1# 30

OPT@

1
2

OPT@ C308
10U_0603_6.3V6M

1
2

1
2

1
2

1
2

1

100mA

OPT@ C307
1U_0603_10V4Z

FBA_DEBUG1
R376
FBB_DEBUG1
R377

+FB_PLLAVDD_1
OPT@ C306
0.1U_0402_16V4Z

OPT@1

1
+1.05VSDGPU
L11
BLM18PG330SN1_2P

OPT@ C305
0.1U_0402_16V4Z
2
1

OPT@1

2

OPT@ C303
10U_0603_6.3V6M

2
10K_0402_5%

OPT@

2

2

100mA

OPT@ C302
1U_0603_10V4Z

2
60.4_0402_1%

FBA_DEBUG0
R374
FBB_DEBUG0
OPT@1
R375
OPT@1

OPT@ C301
0.1U_0402_16V4Z

+FB_PLLAVDD_0
2
60.4_0402_1%

OPT@ C304
0.1U_0402_16V4Z

+1.5VSDGPU

10K_0402_5%

DQSC#[3..0]

N12P-GS-A1_BGA973

1

J27
FBA_DEBUG0 T30
FBA_DEBUG1 T29

P32
H34
J30
P30
AF32
AL32
AL34
AF35

2

J19
J18

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

CMDC[30..0] 29,30
Part 3 of 7

OPT@ C300
0.1U_0402_16V4Z
2
1

+FB_PLLAVDD_1

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

1

AG27
AF27

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

2

+FB_PLLAVDD_0

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE
A

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

OPT@ C299
0.1U_0402_16V4Z

1

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

GS@ U8C

CMDA[30..0] 27,28
Part 2 of 7

2

1
+1.05VSDGPU
L10
BLM18PG330SN1_2P

Modify R03
Modify R03

Compal Secret Data

Security Classification
Issued Date

2009/11/23

Deciphered Date

2010/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.
N12P VRAM 2/9

Size Document Number
Custom LA-7221P
Date:

Wednesday, February 16, 2011

Rev
0.2
Sheet

23

of

59

2

1

C

1

1

+3VSDGPU

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AL2
AL3
AJ3
AJ2
AJ1
AH1
R395
AH2
4.7K_0402_5% AH3
OPT@

AP2
AN3

33 VGA_HDMI_SCLK
33 VGA_HDMI_SDATA

AP4
AN4

B

AE4
AD4

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

D35
P7
AD20

R760
5.1K_0402_1%

R390 1 OPT@
R391 1 OPT@
R392 1 OPT@

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

GS@
R383
15K_0402_1%

2
1
GV@
R382
10K_0402_1%

2

1

@
R381
15K_0402_1%

1
@ R389
15K_0402_1%
2

1

X76@ R387
20K_0402_5%

2

2
1
GS@ R388
10K_0402_1%

2
1
@
R380
45.3K_0402_1%

@ R379
34.8K_0402_1%

strap0

ROM_SO

ROM_SCLK

H
45K

L
35K

L 25k(GS@)
L 5k (GV@)

L
20K

H (GV@)
L (GS@)

H 15K(GS@)
H 5K(GV@)

64MX16
Hynix
SA000041S40

H
45K

L
35K

L 25k(GS@)
L 5k (GV@)

L
15K

H (GV@)
L (GS@)

H 15K(GS@)
H 5K(GV@)

128MX16
Samsung
SA00003MQ60

H
45K

L
35K

L 25k(GS@)

L
45K

H (GV@)
L (GS@)

H 15K(GS@)

128MX16
Hynix
SA00003VS10

H
45K

L
35K

L 25k(GS@)

L
35K

VGAVCC_SENSE 55

Power delete the circuit of
VGAVSS_SENSE, due to the
connection isn't
differental.

AD19
E35
R7

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AP35
AP14
AN14
AN16
AR14
AP16

R398 1

OPT@

2 10K_0402_5%
JTAG_TCK
JTAG_TDI
PAD @ T59
JTAG_TDO
PAD @ T60
JTAG_TMS
PAD @ T61
JTAG_TRST
PAD @ T62

PAD @ T58
2 @ R796
10K_0402_5%

1

strap1

strap2

ROM_SI

H (GV@)
L (GS@)

Pull-up to +3VS

H 15K(GS@)

C

Pull-down to Gnd

5K

1000

0000

10K

1001

0001

15K

1010

0010

20K

1011

0011

25K

1100

0100

30K

1101

0101

35K

1110

0110

45K

1111

0111

DeviceID

ROM_SCLK

STRAP2

N12P-GS

0x0DF4

Pull up 15K

Pull down 25K

N12P-GE

0x0DF5

Pull up 15K

Pull down 30K

N12P-GV

0x1050

Pull up 5K

Pull down 5K

Hynix (900MHZ)
64MX16 H5TQ1G63DFR-11C
SA000041S40

SERIAL

NC/SPDIF_NC
MULTI_STRAP_REF0_GND
CEC
MULTI_STRAP_REF1_GND
THERMDP
THERMDN

C3
D3
C4
D4

ROM_CS#
R400 1 OPT@
ROM_SI
ROM_SO
ROM_SCLK

A5

R401

2 OPT@

2 10K_0402_5%

1 36K_0402_1%

N9

R402 2 OPT@

1 40.2K_0402_1%

M9

R404 2 OPT@

1 40.2K_0402_1%

+3VSDGPU

Hynix 2G
128MX16 H5TQ2G63BFR-12C
SA00003VS10

if unuse this pin , pull down 36k

B5
B4

Samsung (900MHZ)
64MX16 K4W1G1646G-BC11
SA00004GS10
Samsung 2G
128M16 K4W2G1646C-HC12
SA00003MQ60

A

Issued Date

2009/11/23

0010

PD 15K

(SD034150280)

1GB

0010

PD 15K

(SD034150280)

2GB

0110

PD 34.8k(SD034348280)

512MB

0011

PD 20K

(SD028200280)

1GB

0011

PD 20K

(SD028200280)

2GB

0111

PD 45.3K(SD034453280)

A

Compal Electronics, Inc.
2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

512MB

Compal Secret Data

Security Classification

4

B

1 10K_0402_5%

N12P-GS-A1_BGA_973P

5

1

2
1

N11P-GS
64MX16
Samsung
SA00004GS10

STRAP3

GPU

BUFRST_N

STRAP0
STRAP1
STRAP2

D

+3VSDGPU

R759
10K_0402_5%
@

R399 2 OPT@

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

ROM_SI
ROM_SO
ROM_SCLK

TEST

GENERAL
OPT@2
AB5
1
R403
10K_0402_5%
STRAP0 W5
STRAP1 W7
STRAP2
V7

GV@ R383
5.1K_0402_1%

+3VSDGPU

2
1
GS@ R386
24.9K_0402_1%

GV@ R386
5.1K_0402_1%

2

2 R758
1
GV@
40.2K_0402_1%

STRAP0
STRAP1
STRAP2

OPT@ R385
34.8K_0402_1%

STRAP_REF2

R756
10K_0402_5%
GV@

+3VSDGPU

Resistor Values

ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

A4

1

2 R757
1
GV@
10K_0402_5%

Straps MULTI LEVEL STRAPS

1

PGOOD

GV@

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

+3VSDGPU

2

STRAP4
STRAP3

N12P-GS-A1_BGA973
AF3
AF2

R755
10K_0402_5%
@

STRAP4

2

A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

2

2

R394
4.7K_0402_5%
OPT@

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

1

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

33 VGA_HDMI_TXD2+
33 VGA_HDMI_TXD233 VGA_HDMI_TXD1+
33 VGA_HDMI_TXD133 VGA_HDMI_TXD0+
33 VGA_HDMI_TXD033 VGA_HDMI_TXC+
33 VGA_HDMI_TXC-

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

NC

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

LVDS/TMDS

D

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

2

Part 4 of 7
AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

DevID: 0x1050, detail
strap setting, please refer
to N12P-GV DG and PUN-05515-001_v03
1. ROM_SCLK: pull up 5K ohm.
2. STRAP2: pull down 5K ohm.
3. ROM_SO: pull up 10K ohm.
4. STRAP3: pull down 5K ohm.
5. STRAP4: pull down 10K ohm.
6. STRAP_REF2, need to stuff with 40K
ohm 1%.
7. PGOOD (pin E7) stuff 10K ohm.

+3VSDGPU

Modify R02

GS@ U8D

1

11/8, For GB2-128(GS) & GB2b-128(GV) colayout.
QS
the circuit isfor GB2b-128(GV-B) package. N12P-GV
additional

2

3

OPT@ R378
45.3K_0402_1%

4

2
1
@
R384
45.3K_0402_1%

5

2

Title

N12P LVDS 3/9
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

24

of

59

5

4

3

2

1

+3VS
Modify R03
1

@
R405
0_0805_5%
1
2

2

OPT@
C309
10U_0603_6.3V6M

OPT@ Q17
AO3413L_SOT23-3
D

6 1

2

OPT@
R407
470_0603_5%

Q18A
DMN66D0LDW-7_SOT363-6
OPT@
OPT@
C311
0.1U_0603_25V7K

2 3VSdelay_gate

2

1

Q18B
DMN66D0LDW-7_SOT363-6
OPT@

5
4
2

OPT@
C312
0.1U_0603_25V7K

1

G
2
3

2
R408
1K_0402_5%

1

14,17,46,55 VGA_ON

D

Modify R03
OPT@
C310
10U_0603_6.3V6M

2

1
2

3VSdelay_gate

OPT@
1

OPT@
R409
1K_0402_5%
1
2

100mil(1.5A)

1

S

3

OPT@
R406
100K_0402_5%

1

+3VALW
D

+3VSDGPU

GS@ U8E
+1.5VSDGPU

A

+IFPC_IOVDD AK8

@ C359
0.1U_0402_10V7K

+IFPC_IOVDD
@ C358
0.1U_0402_10V7K
2
1

2

1

570 mA
@ C357
4.7U_0603_6.3V6M
2
1

1
2

@ C356
1U_0402_6.3V6K

@
L14
2
1
BLM18BB221SN1D_2P

@

10K_0402_5%2 OPT@
1K_0402_1% 2
@

1 R417
1 R418

AJ6
AL1

10K_0402_5% OPT@
10K_0402_5%1

2 R419

AE7
AD7

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

AA9
AB9
W9
Y9

OPT@
R791
10K_0402_5%

Issued Date

1
2

OPT@ C325
0.1U_0402_16V4Z

1
2

OPT@ C324
0.1U_0402_16V4Z

2

1

OPT@ C323
1U_0402_6.3V6K

2

1

OPT@ C322
1U_0402_6.3V6K

1
2

1
2

1
2

OPT@ C331
0.1U_0402_16V4Z

1
2

2

1

OPT@ C329
1U_0402_6.3V6K

OPT@ C330
1U_0402_6.3V6K

OPT@ C341
1U_0402_6.3V6K

1
2

OPT@ C340
4.7U_0603_6.3V6M

2

1

OPT@ C328
4.7U_0603_6.3V6M

OPT@ C332
0.1U_0402_16V4Z
1

R414
0_0603_5%

OPT@ C344
1U_0402_6.3V6K

1
2

1
2

OPT@ C343
4.7U_0603_6.3V6M

OPT@ C342
0.1U_0402_16V4Z

Under GPU

A

Compal Secret Data
2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+3VSDGPU
2 OPT@

OPT@
R792
10K_0402_5%

IFPE_IOVDD
IFPF_IOVDD

Security Classification

5

OPT@ C339
0.1U_0402_10V7K

1
2

OPT@ C327
10U_0603_6.3V6M
2

1

P9
R9
T9
U9

IFPD_IOVDD
IFPEF_PLLVDD
IFPEF_RSET

OPT@ C321
4.7U_0603_6.3V6M

1
2

OPT@ C320
10U_0603_6.3V6M

1
2
1

OPT@C326
22U_0805_6.3V6M

1
MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

N12P-GS-A1_BGA973

Under GPU

2

IFPC_IOVDD
IFPD_PLLVDD
IFPD_RSET

B

Under GPU
OPT@ C354
4.7U_0603_6.3V6M

1K_0402_1% 2

+1.05VSDGPU

1 @ R793
0_0603_5%

2 OPT@ 1
R410
0_0603_5%

1

1 R416

+IFPC_PLLVDD AC6
AB6

AJ8

+1.05VSDGPU

2

+IFPC_IOVDD

For debug used.

120mA

+VDD33

OPT@ C353
1U_0402_6.3V6K

1 R847

Under GPU

IFPC_PLLVDD
IFPC_RSET

J10
J11
J12
J13
J9

1

10K_0402_5% 2 OPT@

AJ9
AK7

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

+PEX_SVDD_3V3 120mA

2

+IFPC_PLLVDD

IFPA_IOVDD
IFPB_IOVDD

AG19
F7

1

1 R846
1 R415

PEX_SVDD_3V3
PEX_SVDD_3V3_NC

2

10K_0402_5% 2 OPT@
1K_0402_1% 2
@

IFPAB_PLLVDD
IFPAB_RSET

OPT@ C352
0.1U_0402_16V4Z

AG9
AG10

120mA

2

1 R413

+PEX_PLLVDD

1

10K_0402_5%2 OPT@

AG14

2

AK9
AJ11

+1.05VSDGPU

+3VSDGPU
PEX_PLLVDD

OPT@ C351
0.1U_0402_16V4Z

1 R411
1 R412

2

Under GPU

1

10K_0402_5% 2 OPT@
1K_0402_1% 2
@

1

Under GPU

OPT@ L12
2
1
BLM18PG121SN1D_0603

2

2

@ C349
0.1U_0402_10V7K

2

@ C348
0.1U_0402_10V7K
2
1

1

+IFPC_PLLVDD
@ C347
0.1U_0402_10V7K
2
1

2

440 mA
@ C346
4.7U_0603_6.3V6M
2
1

1

@ C345
1U_0402_6.3V6K

@
L13
2
1
BLM18PG331SN1D_2P

2200 mA

AK16
AK17
AK21
AK24
AK27

OPT@ C350
0.1U_0402_16V4Z

+3VSDGPU

Under GPU
+1.05VSDGPU

1

B

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

C

2

Modify R03
not support optimus 1.1

+1.05VSDGPU

2200mA

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

1

under GPU

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

2

OPT@ C338
0.1U_0402_16V4Z

OPT@ C337
0.1U_0402_16V4Z
2
1

OPT@ C336
0.1U_0402_16V4Z
2
1

OPT@ C335
0.1U_0402_16V4Z
2
1

1
2

OPT@ C334
1U_0402_6.3V6K
2
1

1
2

OPT@ C333
4.7U_0603_6.3V6M

under GPU

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

POWER

OPT@ C316
0.1U_0402_16V4Z

OPT@ C318
0.1U_0402_16V4Z
2
1

OPT@ C315
0.1U_0402_16V4Z
2
1

OPT@ C314
0.1U_0402_16V4Z
2
1

1
2

OPT@ C313
1U_0402_6.3V6K
2
1

1
2

OPT@ C317
4.7U_0603_6.3V6M

C

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

OPT@ C319
22U_0805_6.3V6M

Part 5 of 7

7900mA

3

2

Title

Compal Electronics, Inc.
N12P POWER & GND 4/9

Size Document Number
Custom LA-7221P
Date:

Rev
0.2

Wednesday, February 16, 2011

Sheet
1

25

of

59

5

4

D

3

2

1

D

GS@ U8F

B

A

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

+VGA_CORE
+VGA_CORE

Under GPU

GS@ U8G

OPT@ C364
0.01U_0402_16V7K
2
1

OPT@ C374
0.01U_0402_16V7K
2
1

OPT@ C365
0.01U_0402_16V7K
2
1

OPT@ C366
0.01U_0402_16V7K
2
1

OPT@ C367
0.01U_0402_16V7K

OPT@ C370
0.047U_0402_16V7K
2
1

OPT@ C371
0.047U_0402_16V7K
2
1

OPT@ C376
0.047U_0402_16V7K
2
1

OPT@ C372
0.1U_0402_16V4Z
2
1

OPT@ C373
0.1U_0402_16V4Z

Put Under GPU

1
2

OPT@ C386
47U_0805_4V6

1
2

OPT@ C385
22U_0805_6.3V6M

1
2

OPT@ C384
4.7U_0603_6.3V6K

1
2

OPT@ C383
10U_0603_6.3V6M

1
2

Modify R02

+

OPT@ C382
10U_0603_6.3V6M

+

OPT@ C381
470U_D2_2VM_R4.5M

1

+VGA_CORE

Modify R03

Change values from
330u*1 to 470u*2.

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

Part 7 of 7

POWER

OPT@ C363
0.01U_0402_16V7K
2
1
OPT@ C375
0.022U_0402_16V7K
2
1

1
2

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

OPT@ C380
1U_0603_10V4Z

2

1

OPT@ C362
0.01U_0402_16V7K
2
1
OPT@C369
0.022U_0402_16V7K
2
1

OPT@ C379
0.22U_0603_16V7K
2
1

OPT@ C378
0.22U_0603_16V7K
2
1

1
2
2

1

OPT@ C377
0.22U_0603_16V7K
2
1

OPT@C368
0.022U_0402_16V7K

2

1

OPT@ C361
0.01U_0402_16V7K

41.02A

2

GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

OPT@ C857
470U_D2_2VM_R4.5M
2
1

C

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

Part 6 of 7

GND

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

C

B

N12P-GS-A1_BGA973

A

N12P-GS-A1_BGA973

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N12P POWER & GND 5/9

Size Document Number
Custom LA-7221P
Date:

Rev
0.2

Wednesday, February 16, 2011

Sheet
1

26

of

59

5

4

3

2

1

VRAM DDR3 chips (GS=1GB, GV=512M)
128Mx16 DDR3*8==>2GB (GS)
64Mx16 DDR3*8==>1GB (GS)
64Mx8 DDR3*4==>512M
(The 512M DDR3*4 are used at MEMORY INTERFACE A for GV)
DQSA[7..0]

23,28 DQSA[7..0]

U10
+MEM_VREF0

M8
H1

VREFCA
VREFDQ

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA13
CMDA27

M2
N8
M3

BA0
BA1
BA2

CLKA0
CLKA0#
CMDA3

J7
K7
K9

CK
CK
CKE/CKE0

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

DQMA[7..0]

DQSA2
DQSA1

F3
C7

DQMA2
DQMA1

E7
D3

DQSA#2
DQSA#1

G3
B7

CMDA20

T2

ZQ0

L8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

DQSL
DQSU

RESET

OPT@
R425
243_0402_1%
2

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

1

2

R433
OPT@
80.6_0402_1%

BA0
BA1
BA2

CLKA0
CLKA0#
CMDA3

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

DQSA0
DQSA3

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA0
DQMA3

E7
D3

+1.5VSDGPU

DQSA#0
DQSA#3

@
C389
0.01U_0402_16V7K

CMDA20

T2

ZQ1

L8

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

OPT@
R426
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

D7
C3
C8
C2
A7
A2
B8
A3

MDA31
MDA26
MDA30
MDA25
MDA27
MDA28
MDA29
MDA24
+1.5VSDGPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CKE_L

CMD8

CMD1

A8

32..63
D

A8

CMD2

CMD2

CMD21
CMD24

CMD3

A7

A6

CMD4

A2

A1

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11

CMD18

CMD11

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

CMD12
CMD28

CS0_L#

CS0_H#

BA1
CS1_H#
ODT_H

A4

A5

CMD18

A13

A14

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD30
CMD31

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CMDA3
CMDA0
CMDA16
CMDA20
CMDA19

B1
B9
D1
D8
E2
E8
F9
G1
G9

R427
R428
R430
R431
R432

C

RAS*
A7
CKE_H

Not Available

OPT@ C399
0.1U_0402_16V4Z

OPT@ C398
0.1U_0402_16V4Z
2
1

OPT@ C397
0.1U_0402_16V4Z
2
1

OPT@ C396
0.1U_0402_16V4Z
2
1

OPT@ C395
0.1U_0402_16V4Z
2
1

OPT@ C394
0.1U_0402_16V4Z
2
1

OPT@ C393
0.1U_0402_16V4Z
2
1

OPT@ C392
0.1U_0402_16V4Z
2
1

1
1
1
1
1

OPT@
OPT@
OPT@
OPT@
OPT@

2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

B

Command Bit Default Pull-down
ODTx

10k
10k

CKEx

DDR3

RST
CS*

+1.5VSDGPU

OPT@ C391
0.1U_0402_16V4Z
2
1

1
2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

ODT/ODT0
CS/CS0
RAS
CAS
WE

10k
No Termination

Samsung :
SA00004GS10 (S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO! )
SA000047Q20 (S IC D3 128M16 K4W2G1646C-HC11 FBGA 96P ABO!)
Hynix :
SA000041S40 (S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO! )
SA00003YO20 (S IC D3 128M16 H5TQ2G63BFR-11C FBGA ABO!)
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

CMD0

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

OPT@ C390
1000P_0402_50V7K
2
1

G3
B7

MDA0
MDA7
MDA1
MDA4
MDA3
MDA6
MDA2
MDA5

OPT@ C408
4.7U_0603_6.3V6M

1
2
R424
OPT@
@
80.6_0402_1%
R429
160_0402_1%
1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

0..31

CMD3

1

ZQ/ZQ0

2

1

ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

M2
N8
M3

B2
D9
G7
K2
K8
N1
N9
R1
R9

1

B

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

OPT@ C401
4.7U_0603_6.3V6M
2
1

1
2

OPT@
R423
240_0402_1%

C388 OPT@
0.1U_0402_10V6K

+MEM_VREF1

CMDA29
CMDA13
CMDA27

+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

OPT@ C407
4.7U_0603_6.3V6M
2
1

OPT@
R422
240_0402_1%

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

OPT@ C406
4.7U_0603_6.3V6M
2
1

+1.5VSDGPU

MDA14
MDA10
MDA15
MDA8
MDA12
MDA9
MDA13
MDA11

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

2

2

OPT@
R421
240_0402_1%

D7
C3
C8
C2
A7
A2
B8
A3

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

1

1

C

C387 OPT@
0.1U_0402_10V6K

+MEM_VREF0

A

X76@

VREFCA
VREFDQ

OPT@ C405
4.7U_0603_6.3V6M
2
1

OPT@
R420
240_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

+MEM_VREF1 M8
H1

OPT@ C404
4.7U_0603_6.3V6M
2
1

+1.5VSDGPU

MDA17
MDA18
MDA16
MDA23
MDA22
MDA20
MDA19
MDA21

OPT@ C403
4.7U_0603_6.3V6M
2
1

CMDA[30..0]

E3
F7
F2
F8
H3
H8
G2
H7

OPT@ C402
4.7U_0603_6.3V6M
2
1

MDA[63..0]

23,28 MDA[63..0]
23,28 CMDA[30..0]

23 CLKA0#

U11
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

23,28 DQMA[7..0]

23 CLKA0

X76@

DQSA#[7..0]

23,28 DQSA#[7..0]

OPT@ C400
4.7U_0603_6.3V6M
2
1

D

Mode C
Address

**Mode E
Address

4

3

2

Title

N21P DDR3 6/9
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

27

of

59

5

4

3

2

1

VRAM DDR3 chips (GS=1GB, GV=512M)
128Mx16 DDR3*8==>2GB (GS)
64Mx16 DDR3*8==>1GB (GS)
64Mx8 DDR3*4==>512M
(The 512M DDR3*4 are used at MEMORY INTERFACE A for GV)
U12
+MEM_VREF2
DQMA[7..0]

23,27 DQMA[7..0]

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

CMDA[30..0]

23,27 CMDA[30..0]

DQSA#[7..0]

23,27 DQSA#[7..0]

DQSA[7..0]

23,27 DQSA[7..0]

MDA[63..0]

23,27 MDA[63..0]

+1.5VSDGPU
OPT@
R434
240_0402_1%

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

X76@

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

1
2

C409 OPT@
0.1U_0402_10V6K

C

M2
N8
M3

BA0
BA1
BA2

CLKA1
CLKA1#
CMDA16

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

E7
D3

DQSA#7
DQSA#4

G3
B7

CMDA20

T2

ZQ2

L8

OPT@
R438
243_0402_1%

J1
L1
J9
L9

2

B

CLKA1

D7
C3
C8
C2
A7
A2
B8
A3

MDA35
MDA38
MDA34
MDA36
MDA33
MDA37
MDA32
MDA39

+MEM_VREF3
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M2
N8
M3

BA0
BA1
BA2

CLKA1
CLKA1#
CMDA16

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25
DQSA5
DQSA6

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA5
DQMA6

E7
D3

DQSA#5
DQSA#6

G3
B7

CMDA20

T2

ZQ3

L8

K1
L2
J3
K3
L3

E3
F7
F2
F8
H3
H8
G2
H7

MDA41
MDA45
MDA43
MDA44
MDA42
MDA47
MDA40
MDA46

D7
C3
C8
C2
A7
A2
B8
A3

MDA51
MDA52
MDA48
MDA54
MDA49
MDA55
MDA50
MDA53
+1.5VSDGPU

CMDA29
CMDA6
CMDA30

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

1
2
R440
OPT@
@
80.6_0402_1%
R441
160_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

OPT@
R439
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0..31

CMD0

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

A7

CMD4

A2

A1

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

CMD18

CMD11

32..63

A8

A8
D

CS0_L#
A6

A11
CS0_H#

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD30
CMD31

BA1
CS1_H#
ODT_H
A5
C

RAS*
A7
CKE_H

Not Available

B1
B9
D1
D8
E2
E8
F9
G1
G9

B

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

2

1

23

MDA63
MDA57
MDA62
MDA61
MDA59
MDA56
MDA60
MDA58

1

1
2

OPT@
R437
240_0402_1%

C410 OPT@
0.1U_0402_10V6K

+MEM_VREF3

DQMA7
DQMA4

DQSL
DQSU

E3
F7
F2
F8
H3
H8
G2
H7

X76@

1

OPT@
R436
240_0402_1%

F3
C7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSDGPU
DQSA7
DQSA4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

CMDA29
CMDA6
CMDA30

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

U13

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

+MEM_VREF2
OPT@
R435
240_0402_1%

Mode E
Address

2

D

Mode C
Address

CMD3

1
2

OPT@ C430
4.7U_0603_6.3V6M

1
2

OPT@ C429
4.7U_0603_6.3V6M

1
2

OPT@ C428
4.7U_0603_6.3V6M

1
2

OPT@ C427
4.7U_0603_6.3V6M

1
2

OPT@ C426
4.7U_0603_6.3V6M

1
2

OPT@ C425
4.7U_0603_6.3V6M

1
2

OPT@ C424
4.7U_0603_6.3V6M

1
2

OPT@ C423
4.7U_0603_6.3V6M

1
2

OPT@ C422
4.7U_0603_6.3V6M

OPT@
C421
.1U_0402_16V7K

OPT@
C420
.1U_0402_16V7K
2
1

OPT@
C419
.1U_0402_16V7K
2
1

OPT@
C418
.1U_0402_16V7K
2
1

OPT@
C417
.1U_0402_16V7K
2
1

OPT@
C416
.1U_0402_16V7K
2
1

OPT@
C415
1U_0402_6.3V6K
2
1

OPT@
C414
1U_0402_6.3V6K
2
1

+1.5VSDGPU

OPT@
C413
1U_0402_6.3V6K
2
1

2

1

2

+1.5VSDGPU
@
C411
0.01U_0402_16V7K

OPT@
C412
1U_0402_6.3V6K
2
1

2
R442
OPT@
80.6_0402_1%

1

1

23 CLKA1#

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

N12P DDR3 7/9
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

28

of

59

5

4

3

2

1

VRAM DDR3 chips (GS=1GB, GV=512M)
128Mx16 DDR3*8==>2GB (GS)
64Mx16 DDR3*8==>1GB (GS)
D

DQSC[7..0]

23,30 DQSC[7..0]

DQSC#[7..0]

23,30 DQSC#[7..0]

DQMC[7..0]

23,30 DQMC[7..0]

U14
+MEM_VREF4

MDC[63..0]

23,30 MDC[63..0]

CMDC7
CMDC10
CMDC24
CMDC6
CMDC22
CMDC26
CMDC5
CMDC21
CMDC8
CMDC4
CMDC25
CMDC23
CMDC9
CMDC12
CMDC14
CMDC30

CMDC[30..0]

23,30 CMDC[30..0]

+1.5VSDGPU

GS@
R443
240_0402_1%

1
2

GS@
R444
240_0402_1%

C431
GS@
0.1U_0402_10V6K

+MEM_VREF4

C

CMDC29
CMDC13
CMDC27

CLKC0
CLKC0#
CMDC3

+1.5VSDGPU

GS@
R445
240_0402_1%

1
2

C432
GS@
0.1U_0402_10V6K

M8
H1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

DQSC2
DQSC1

F3
C7

DQMC2
DQMC1

E7
D3

DQSC#2
DQSC#1

G3
B7

CMDC20

T2

ZQ4

L8

U15
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDC21
MDC19
MDC16
MDC17
MDC18
MDC20
MDC23
MDC22

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC13
MDC8
MDC14
MDC9
MDC12
MDC11
MDC15
MDC10

+MEM_VREF5 M8
H1
CMDC7
CMDC10
CMDC24
CMDC6
CMDC22
CMDC26
CMDC5
CMDC21
CMDC8
CMDC4
CMDC25
CMDC23
CMDC9
CMDC12
CMDC14
CMDC30

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

CMDC29
CMDC13
CMDC27

CMD0

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

A7

A6

CMD4

A2

A1

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CMDC0
CMDC2
CMDC11
CMDC15
CMDC28

K1
L2
J3
K3
L3

DQSC0
DQSC3

F3
C7

DQMC0
DQMC3

E7
D3

DQSC#0
DQSC#3

G3
B7

CMDC20

T2

ZQ5

L8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDC2
MDC7
MDC0
MDC5
MDC3
MDC6
MDC1
MDC4

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC31
MDC24
MDC30
MDC25
MDC28
MDC26
MDC29
MDC27

CMD18

CMD11

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

+1.5VSDGPU

CMD17

CMD15

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

+1.5VSDGPU

A2

CMD25

CMD21

A10

WE*

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD30
CMD31

32..63

A8

A8

D

CS0_L#

CS0_H#

BA1
CS1_H#
ODT_H
C

RAS*
A7
CKE_H

Not Available

2

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

1
2
R454
GS@
@
80.6_0402_1%
R455
160_0402_1%

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

GS@
R448
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B

B1
B9
D1
D8
E2
E8
F9
G1
G9

CMDC3
CMDC0
CMDC16
CMDC20
CMDC19

R449
R450
R451
R452
R453

1
1
1
1
1

GS@
GS@
GS@
GS@
GS@

2
2
2
2
2

Command Bit Default Pull-down

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

ODTx
DDR3

CKEx
RST
CS*

10k
10k
10k
No Termination

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

2

1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CLKC0
CLKC0#
CMDC3

+1.5VSDGPU

X76@

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

2

GS@
R447
243_0402_1%

23 CLKC0

0..31

CMD3

1

ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

1

B

X76@

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDC0
CMDC2
CMDC11
CMDC15
CMDC28

+MEM_VREF5
GS@
R446
240_0402_1%

Mode C
Address

Mode E
Address

1

GS@ C452
4.7U_0603_6.3V6M

GS@ C451
4.7U_0603_6.3V6M
2
1

GS@ C450
4.7U_0603_6.3V6M
2
1

GS@ C449
4.7U_0603_6.3V6M
2
1

GS@ C448
4.7U_0603_6.3V6M
2
1

GS@ C447
4.7U_0603_6.3V6M
2
1

GS@ C446
4.7U_0603_6.3V6M
2
1

GS@ C445
4.7U_0603_6.3V6M
2
1

GS@ C444
4.7U_0603_6.3V6M
2
1

1
2

GS@ C443
0.1U_0402_16V4Z

GS@ C442
0.1U_0402_16V4Z
2
1

GS@ C441
0.1U_0402_16V4Z
2
1

GS@ C440
0.1U_0402_16V4Z
2
1

GS@ C439
0.1U_0402_16V4Z
2
1

GS@ C438
0.1U_0402_16V4Z
2
1

GS@ C437
0.1U_0402_16V4Z
2
1

GS@ C436
0.1U_0402_16V4Z
2
1

1
2

GS@ C434
1000P_0402_50V7K
2
1

2

+1.5VSDGPU
@
C433
0.01U_0402_16V7K

GS@ C435
0.1U_0402_16V4Z
2
1

+1.5VSDGPU
1

2
R456
GS@
80.6_0402_1%

23 CLKC0#

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

N12P DDR3 8/9
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

29

of

59

5

4

3

2

1

VRAM DDR3 chips (GS=1GB, GV=512M)
128Mx16 DDR3*8==>2GB (GS)
64Mx16 DDR3*8==>1GB (GS)
D

DQMC[7..0]

23,29 DQMC[7..0]

CMDC[30..0]

23,29 CMDC[30..0]

DQSC#[7..0]

23,29 DQSC#[7..0]

U16

DQSC[7..0]

23,29 DQSC[7..0]

+MEM_VREF6

MDC[63..0]

23,29 MDC[63..0]

CMDC9
CMDC24
CMDC10
CMDC13
CMDC26
CMDC22
CMDC21
CMDC5
CMDC8
CMDC23
CMDC28
CMDC4
CMDC7
CMDC14
CMDC12
CMDC27

+1.5VSDGPU
GS@
R457
240_0402_1%

2

1

GS@
R458
240_0402_1%

C453
GS@
0.1U_0402_10V6K

+MEM_VREF6

C

CMDC29
CMDC6
CMDC30

CLKC1
CLKC1#
CMDC16

+1.5VSDGPU
GS@
R459
240_0402_1%

M8
H1

X76@

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

CMDC19
CMDC18
CMDC11
CMDC15
CMDC25

K1
L2
J3
K3
L3

DQSC7
DQSC4

F3
C7

U17
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDC63
MDC56
MDC62
MDC58
MDC61
MDC59
MDC60
MDC57

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC34
MDC36
MDC35
MDC38
MDC33
MDC37
MDC32
MDC39

+MEM_VREF7
CMDC9
CMDC24
CMDC10
CMDC13
CMDC26
CMDC22
CMDC21
CMDC5
CMDC8
CMDC23
CMDC28
CMDC4
CMDC7
CMDC14
CMDC12
CMDC27

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

CMDC29
CMDC6
CMDC30

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKC1
CLKC1#
CMDC16

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

X76@

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

CMDC19
CMDC18
CMDC11
CMDC15
CMDC25

K1
L2
J3
K3
L3

DQSC5
DQSC6

F3
C7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDC42
MDC43
MDC41
MDC47
MDC40
MDC46
MDC44
MDC45

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC48
MDC53
MDC50
MDC54
MDC49
MDC52
MDC51
MDC55
+1.5VSDGPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

1
2

C454
GS@
0.1U_0402_10V6K

+MEM_VREF7
GS@
R460
240_0402_1%

Mode C
Address

0..31

CMD3

CMD0

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

A7

A6

CMD4

A2

A1

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11

CMD18

CMD11

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

Mode E
Address

DQMC7
DQMC4

E7
D3

DQSC#7
DQSC#4

G3
B7

CMDC20

T2

ZQ6

L8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMC5
DQMC6

E7
D3

DQSC#5
DQSC#6

G3
B7

CMDC20
ZQ7

T2
L8

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CMD30
CMD31

A8

A8

D

CS0_L#

CS0_H#

BA1
CS1_H#
ODT_H
C

RAS*
A7
CKE_H

Not Available

B

GS@
R461
243_0402_1%

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

1
2

C474 GS@
4.7U_0603_6.3V6M

1
2

C473 GS@
4.7U_0603_6.3V6M

1
2

C472 GS@
4.7U_0603_6.3V6M

1
2

C471 GS@
4.7U_0603_6.3V6M

1
2

C470 GS@
4.7U_0603_6.3V6M

1
2

C469 GS@
4.7U_0603_6.3V6M

1
2

C467 GS@
4.7U_0603_6.3V6M

1
2

1
2

C466 GS@
4.7U_0603_6.3V6M

C465
GS@
.1U_0402_16V7K

C464
GS@
.1U_0402_16V7K
2
1

C463
GS@
.1U_0402_16V7K
2
1

C462
GS@
.1U_0402_16V7K
2
1

C461
GS@
.1U_0402_16V7K
2
1

C459
GS@
1U_0402_6.3V6K
2
1

C458
GS@
1U_0402_6.3V6K
2
1

2

C457
GS@
1U_0402_6.3V6K
2
1

+1.5VSDGPU

1

@
C455
0.01U_0402_16V7K

C456
GS@
1U_0402_6.3V6K
2
1

2

1

2
R465
GS@
80.6_0402_1%

GS@
R462
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

1

23 CLKC1#

C460
GS@
.1U_0402_16V7K
2
1

1
2

@
R464
160_0402_1%

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C468 GS@
4.7U_0603_6.3V6M

2
R463
GS@
80.6_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

1

23 CLKC1

J1
L1
J9
L9

2

1

1

B

DML
DMU

32..63

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/11/23

2010/11/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

N12P DDR3 9/9
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

30

of

59

5

4

W=60mils

1

0.1U_0402_16V4Z

10U_0603_6.3V6M

C478

1

C480
68P_0402_50V8J

2

1
2

C477

1

C476

2

D

1

1

G

D

SM010014520 3000ma
220ohm@100mhz DCR
0.04

0.1U_0402_16V4Z

+LCDVDD

W=60mils
1

Q21
2N7002H_SOT23-3
3

1

C479
680P_0402_50V7K

Q20
AO3413L_SOT23-3

2

D

2
G

Place closed to JLVDS1

+INVPWR_B+
L15
FBMA-L11-201209-221LMA30T_0805
2
1
L16
FBMA-L11-201209-221LMA30T_0805
2
1

2

1

3

PCH_ENVDD

C481
0.47U_0402_6.3V6K

+LCDVDD
+3VS

2

2

S

Modify R03
C475
4.7U_0603_6.3V6K

2
3

S

1

2
G

Modify R02

R468
100K_0402_5%
2
1

2

D

1

1

2

2

R467
10K_0402_5%

2

R466
300_0603_5%

1

1

1

W=60mils

Q19
2N7002H_SOT23-3

1

B+

+3VS

+3VALW

16 PCH_ENVDD

2

LCD POWER CIRCUIT

+LCDVDD

D

3

S
C482
4.7U_0603_6.3V6K

2

R469
100K_0402_5%

Modify R03
C483
0.1U_0402_16V4Z

LCD/LED PANEL Conn.
W=60mils
+INVPWR_B+

W=60mils

C

VCC
2
3

BKOFF#

IN
OUT

2 10K_0402_5%

4

GND

INVTPWM

C486 2

1 220P_0402_50V7K DAC_BRIG

C487 2

1 220P_0402_50V7K INVTPWM

C488 2

1 220P_0402_50V7K DISPOFF#

EDP_AUX_R
EDP_AUX#_R
EDP_TX1_R
EDP_TX1#_R

R829
10K_0402_5%

EDP_TX0_R
EDP_TX0#_R

For RF request

2

74AHC1G125GW_SOT353-5

DAC_BRIG
DISPOFF#
INVTPWM

39 DAC_BRIG

5

16 PCH_TXCLK+
16 PCH_TXCLK16 PCH_TXOUT2+
16 PCH_TXOUT2-

Modify R02
PCH_LCD_CLK & PCH_LCD_DATA
Pull high at PCH side.
+LCDVDD

16 PCH_TXOUT1+
16 PCH_TXOUT1-

+3VS

16 PCH_TXOUT0+
16 PCH_TXOUT016 PCH_LCD_DATA
16 PCH_LCD_CLK

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

1
1
1
1

2
2
2
2

R818
R819
R820
R821

PCH_TXCLK+_R
PCH_TXCLK-_R
PCH_TXOUT2+_R
PCH_TXOUT2-_R

0_0402_5%
0_0402_5%

1
1

2 R822
2 R823

PCH_TXOUT1+_R
PCH_TXOUT1-_R

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

1
1
1
1

2
2
2
2

R824
R825
R826
R827

PCH_TXOUT0+_R
PCH_TXOUT0-_R
PCH_LCD_DATA_R
PCH_LCD_CLK_R

B

EDP_HPD

C492
22P_0402_50V8J
@

eDP
EDP@ R477
+1.05VS_VCCP 1K_0402_5%
1
2

1

USB20_CMOS_P10
USB20_CMOS_N10

1

4 EDP_HPD#
D

EDP_HPD

4 EDP_TXN1
4 EDP_TXP1

1

2
G
3

S

.1U_0402_16V7K EDP@
2
.1U_0402_16V7K EDP@
2

1
1

C489
C490

EDP_TX0#_R
EDP_TX0_R

EDP_TXN1
EDP_TXP1

.1U_0402_16V7K EDP@
2
.1U_0402_16V7K EDP@
2

1
1

C491
C494

EDP_TX1#_R
EDP_TX1_R

C495
C496

EDP_AUX#_R
EDP_AUX_R

.1U_0402_16V7K EDP@
2
.1U_0402_16V7K EDP@
2

1
1

G1
G2
G3
G4
G5

41
42
43
44
45

D5
USB20_CMOS_N10
+3VS

4
5
6

I/O3

I/O2

REF2 REF1
I/O4

I/O1

3

USB20_CMOS_P10

2
1

@ PJUSB208H_SOT23-6

2

EDP@
R480
100K_0402_5%

4 EDP_AUXN
4 EDP_AUXP

B

10/01 Check footprint OK

EDP_TXN0
EDP_TXP0

EDP_AUXN
EDP_AUXP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

ACES_50398-04071-001
CONN@

C493
22P_0402_50V8J
@

Near JLVDS1
4 EDP_TXN0
4 EDP_TXP0

Q22
2N7002H_SOT23-3
EDP@

2

1

17 USB20_P10
17 USB20_N10

Modify R03
R845 2
1 0_0603_5%
R478 1
2 0_0402_5%
R479 1
2 0_0402_5%

2

+3VS

C

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

DISPOFF#

2 0_0402_5%

R475 1

OE#

1


16 DPST_PWM

1

39

+3VS

U45
1 R828
2
100K_0402_5%

R474 1

SC300000D00--> EOL
Change to SC300000B10

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

A

2009/08/01

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LVDS Connector
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Sheet

Wednesday, February 16, 2011
1

31

of

59

A

B

C

D

E

Modify 03
Link CIS symbol D6.D7
Modify R02

ESD team Suggestion

1

1

W=40mils

2

3

2

3

+5VS

+R_CRT_VCC

+CRT_VCC
F1
1.1A_6V_SMD1812P110TFW=40mils
1
2

D8
2
1

2
1
2

SM010012010 300ma 120ohm@100mhz DCR 0.4

A

U18
Y

2
MBC1608121YZF_0603

CRT_VSYNC_2

C509
10P_0402_50V8J
CRT_HSYNC_1

4

100P_0402_50V8J

10/01 Check footprint OK

1

1

1
C510
10P_0402_50V8J

DSUB_15

C511
68P_0402_50V8J

74AHCT1G125GW_SOT353-5

2

3

2

1

2

1
L24

16
17

DSUB_12

2

P

PCH_CRT_HSYNC

1 10K_0402_5%

CRT_HSYNC_2

G
G

SUYIN_070546FR015S297ZR
CONN@

G

16 PCH_CRT_HSYNC

1

R484 2
5

2 0.1U_0402_16V4Z

OE#

C508 1

2
MBC1608121YZF_0603

2

+CRT_VCC

1
L23

DSUB_5

T93
PAD

C507

2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

2

1

CRT_B_2
C506
10P_0402_50V8J

2

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

DSUB_11

T92
PAD

CRT_G_2

C505
10P_0402_50V8J

2

CRT_R_2

C504
10P_0402_50V8J

C503
22P_0402_50V8J

2

CRT_B_1
C502
22P_0402_50V8J

2

CRT_G_1

C497
0.1U_0402_16V4Z

CRT Connector

L18
BLM18BA470SN1D_2P
1
2
L20
BLM18BA470SN1D_2P
1
2
L22
BLM18BA470SN1D_2P
1
2

CRT_R_1

C501
22P_0402_50V8J

C500
10P_0402_50V8J

2

C499
10P_0402_50V8J

R483
150_0402_1%

C498
10P_0402_50V8J

R481
R482
150_0402_1% 150_0402_1%

1

PCH_CRT_B
1

16 PCH_CRT_B

1

16 PCH_CRT_G

PCH_CRT_G

1

16 PCH_CRT_R

L17
BLM18BA470SN1D_2P
1
2
L19
BLM18BA470SN1D_2P
1
2
L21
BLM18BA470SN1D_2P
1
2

PCH_CRT_R

RB491D-YS_SOT23-3

1

1

D7
PJDLC05C_SOT23-3

1

3
D6
PJDLC05C_SOT23-3

C512
68P_0402_50V8J

+CRT_VCC

5
P
PCH_CRT_VSYNC

2

A

U19
Y

4

CRT_VSYNC_1

3

G

16 PCH_CRT_VSYNC

1

2 0.1U_0402_16V4Z

OE#

C513 1

74AHCT1G125GW_SOT353-5
+CRT_VCC
3

1

+3VS

1

3

PCH_CRT_DATA

3
2

PCH_CRT_CLK

3

D
Q23
2N7002H_SOT23-3

G

Q24
1 2N7002H_SOT23-3

DSUB_15

D

S

16 PCH_CRT_CLK

DSUB_12

1

S

16 PCH_CRT_DATA

R487
4.7K_0402_5%
2

G

2

2

R486
4.7K_0402_5%

PCH DDC PU 2.2K on Page 17

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

CRT Connector
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Sheet

Wednesday, February 16, 2011
E

32

of

59

5

4

3

2

1

Modify 03
Link CIS symbol L25.L26.L27.L28
R502
0_0603_5%
1
2

HDMI_CLK+

+HDMI_5V_OUT

@ L25
WCM2012F2S-900T04_0805
4

2
C514
0.1U_0402_16V4Z

1
HDMI_HPD

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX0HDMI_TX0+

16 PCH_DPB_N3
16 PCH_DPB_P3

C522 UMA@ 2
C523 UMA@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_CLKHDMI_CLK+

C

1

D

1

UMA@
R506
1M_0402_5%

2
3

PCH_DPB_HPD 16

Q25 UMA@
UMA@
2N7002H_SOT23-3
R509
100K_0402_5%

24 VGA_HDMI_TXD124 VGA_HDMI_TXD1+

HDMI_TX2HDMI_TX2+

2
2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX1HDMI_TX1+

C528 OPT11@
C529 OPT11@

2
2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX0HDMI_TX0+

C530 OPT11@
C531 OPT11@

2
2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_CLKHDMI_CLK+

R505 1

2

4

22 VGA_HDMI_DET

A

Y

NC7SZ08P5X_NL_SC70-5

2
1

3

2

4

3

R507 1

2

HDMI_TX1+

R508 1

2

HDMI_TX1-

R510

HDMI_TX2+

R511

HDMI_TX2-

2 OPT11@1 R794
1K_0402_5%
HDMI_HPD

1

HDMI_TX0-

1
@ L28
WCM2012F2S-900T04_0805
4

+3VSDGPU

0.1U_0402_16V4Z
B

D

HDMI_R_CK+

2
3
0_0402_5%

HDMI_R_CK-

0_0402_5%

HDMI_R_D0+

1

2

4

3

1

2

1

2

1

2

4

3

R513 1

2

2
3
0_0402_5%

HDMI_R_D0-

0_0402_5%

HDMI_R_D1+

2
3
0_0402_5%

HDMI_R_D1-

0_0402_5%

HDMI_R_D2+

1

DGPU_HPD_INT# 18

Q26 OPT11@
2N7002H_SOT23-3

C

2
3
0_0402_5%

HDMI_TX2- R515 1 UMA@ 2 680_0402_5%
HDMI_TX2+ R516 1 UMA@ 2 680_0402_5%
D

C526 OPT11@
C527 OPT11@

OPT11@ U44

S

24 VGA_HDMI_TXC24 VGA_HDMI_TXC+

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX0+

@ L27
WCM2012F2S-900T04_0805
4

G

24 VGA_HDMI_TXD024 VGA_HDMI_TXD0+

2
2

5

Optimus 1.1
C524 OPT11@
C525 OPT11@

3
2

1

+3VSDGPU
OPT11@ C858
1
2

NVIDA Recommand 10/08
OPT1.1
24 VGA_HDMI_TXD224 VGA_HDMI_TXD2+

2

4

R504 1

@ L26
WCM2012F2S-900T04_0805
4

2

C519 UMA@ 2
C520 UMA@ 2

2

16 PCH_DPB_N2
16 PCH_DPB_P2

1

HDMI_CLK-

1

S

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX1HDMI_TX1+

1

C517 UMA@ 2
C518 UMA@ 2

HDMI_TX2HDMI_TX2+
UMA@ C521
220P_0402_25V8J

16 PCH_DPB_N1
16 PCH_DPB_P1

1 .1U_0402_16V7K
1 .1U_0402_16V7K

2
G

UMA & Optimus 1.0
C515 UMA@ 2
C516 UMA@ 2

0_0402_5%

2

+3VS

UMA/OPT1.0

Modify R02

2

2

RB491D-YS_SOT23-3

P

1

1.1A_6V_SMD1812P110TF

G

1 +HDMI_5V

1

3

16 PCH_DPB_N0
16 PCH_DPB_P0

R503 1

F2

3

@ D9
2

+5VS

SM070001310 400ma 90ohm@100mhz DCR 0.3

W=40mils

1

D

HDMI_R_D2-

HDMI_GND

HDMI_TX1- R517 1 UMA@ 2 680_0402_5%
HDMI_TX1+ R518 1 UMA@ 2 680_0402_5%
HDMI_TX0- R519 1 UMA@ 2 680_0402_5%
HDMI_TX0+ R520 1 UMA@ 2 680_0402_5%

2

2

D

S

2
G

+3VS

HDMI connector

1

Optimus 1.0--> 680_0402_5%
Optimus 1.1--> 499_0402_1%

+HDMI_5V_OUT

3

HDMI_CLK- R521 1 UMA@ 2 680_0402_5%
HDMI_CLK+ R522 1 UMA@ 2 680_0402_5%

Q27
2N7002H_SOT23-3

JHDMI1

Pull high at VGA side
3

1

2

HDMI_SDATA

Q29
2N7002H_SOT23-3

Place closed to JHDMI1

2

1

1

3

D

HDMI_SDATA_R

HDMI_R_D0+
HDMI_R_D1-

HDMI_SCLK

Q28
2N7002H_SOT23-3

S

1 UMA@ 2 0_0402_5%
1 OPT11@2 0_0402_5%

1109 RF request

HDMI_R_CK+
HDMI_R_D0-

D

S

G

R527
R528

16 SDVO_SDATA
24 VGA_HDMI_SDATA

HDMI_R_CK-

1

1
HDMI_SCLK_R

1

2

1 UMA@ 2 0_0402_5%
1 OPT11@2 0_0402_5%

HDMI_SDATA
HDMI_SCLK




G

R525
R526

16 SDVO_SCLK
24 VGA_HDMI_SCLK

+HDMI_5V_OUT

2 1
R524
2.2K_0402_5%

+3VS

HDMI_HPD

D12
RB751V-40_SOD323-2
2 1
R523
2.2K_0402_5%

D11
RB751V-40_SOD323-2

2

B

C532
47P_0402_50V8J
@

HDMI_R_D1+
HDMI_R_D2-

C533
47P_0402_50V8J
@

HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

B

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

Optimus 1.1 Option Component
20
21
22
23

R515 2 OPT11@
1 499_0402_1%
R516 2 OPT11@
1 499_0402_1%
R517 2 OPT11@
1 499_0402_1%
R518 2 OPT11@
1 499_0402_1%
R519 2 OPT11@
1 499_0402_1%
R520 2 OPT11@
1 499_0402_1%
R521 2 OPT11@
1 499_0402_1%
R522 2 OPT11@
1 499_0402_1%

SUYIN_100042GR019M23DZL
CONN@

10/13 Link CIS symbol OK!

A

A

Modify R02
SDVO_CTRL.DATA strap pull high at PCH side

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HDMI Conn
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Sheet

Wednesday, February 16, 2011
1

33

of

59

5

4

3

2

1

D

D

SATA HDD1 Conn.
CL 4.0 mm

JHDD1

+5VS

R531
0_0805_5%
1
2

+5VS_HDD1

C

C538
0.1U_0402_16V4Z

+5VS_HDD1
C

100mils

C550
0.1U_0402_16V4Z

C551
1000P_0402_50V7K

C542
1000P_0402_50V7K

C541
0.1U_0402_16V4Z

C540
1U_0402_6.3V6K

C539
10U_0603_6.3V6M

ACES_50406-02071-001
CONN@

1

+3VS

+3VS

2

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2

C536 1
C537 1

10/4 Check footprint ok

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

2

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2

C534 1
C535 1

1

13 SATA_PRX_DTX_N0
13 SATA_PRX_DTX_P0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

2

13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0

Modify R03

SATA ODD Conn.

1

0_0402_5%

ODD_DETECT#_R
+5VS_ODD

R535

1

2

0_0402_5%

ODD_DA#_R

8
9
10
11
12
13

80mils

DP
+5V
+5V
MD
GND
GND

GND
GND

15
14

SANTA_202801-1
CONN@

1

2

2

1

1

R534

+5VS_ODD

2

18 ODD_DETECT#
+5VS_ODD

GND
A+
AGND
BB+
GND

1

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

2

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1

13 SATA_PRX_DTX_N2
13 SATA_PRX_DTX_P2

C545 1
C546 1

1
2
3
4
5
6
7

2

S
2
1

2

2

G
3

1

2
1
1
3

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

17 ODD_DA#

Q31
2N7002H_SOT23-3

2
G

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

C549
1U_0402_6.3V6K

S

Q30
SI3456DDV-T1-GE3_TSOP6

C543 1
C544 1

C552
0.1U_0402_25V6

D

4

R536
1.5M_0402_5%

18 ODD_EN#

6
5
2
1

13 SATA_PTX_DRX_P2
13 SATA_PTX_DRX_N2

C548
10U_0603_6.3V6M

ODD_EN

C547
1U_0402_6.3V6K

R533
470K_0402_5%

D

@ R532
0_0805_5%
1
2

+VSB

B

JODD1

+5VS_ODD

+5VS

B

Modify R03
Modify R02

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HDD & ODD Connector
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

34

of

59

5

4

3

2

1

Power On strapping
+3V_LAN

Check PU/PD on MB side
@

1
R539

LAN_WAKE#
2
4.7K_0402_5%

1
R541
D

H

L:Over Clock Disable *

Modify R02

@1

R538 1

1

LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+

AR8152, Pin23 is CLKREQ

Close to lan chip.

R537 1

LAN_MIDI0-

LAN_MIDI1-

AR8151-BL1A
applies
switch mode
regulator.

AR8151 Pin39
*
H: switch regulator applied.
L: switch regulator isn't applied.

LED1

LAN_MIDI0+

LAN_MIDI1+

H:SWR Switch mode regulator Select

LAN_CLKREQ#
2
4.7K_0402_5%

1
R544

Chip Default

H:Over Clock Enable

LED0

PLT_RST#
2
4.7K_0402_5%

Place Close to LAN chip

Description

Pin

LAN_MIDI3-

2
49.9_0402_1%
2
49.9_0402_1%
R540 1
2
49.9_0402_1%
R542 1
2
49.9_0402_1%
R543 1
2
8151@ 49.9_0402_1%
R545 1
2
8151@ 49.9_0402_1%
R546 1
2
8151@ 49.9_0402_1%
R547 1
2
8151@ 49.9_0402_1%

@1
1

2 C553 1000P_0402_50V7K
2 C554 0.1U_0402_16V4Z
2 C555 1000P_0402_50V7K
2 C556 0.1U_0402_16V4Z

@1

2 C557 1000P_0402_50V7K

1

2 C558 0.1U_0402_16V4Z
8151@
2 C559 1000P_0402_50V7K

@1
1

D

2 C560 0.1U_0402_16V4Z
8151@

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+
resister and cap
no overclocking
PD 5.1K

R553 1

LAN_WAKE#

2 0_0402_5%
2 0_0402_5%

PERST#

3

WAKE#

25
26
28
27
7
8

LX
VDDCT

2

13
19
31
34
6

C574

41

1

2

0.1U_0402_16V4Z

C573

C572

2

1

+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
1U_0402_6.3V6K

2

1

0.1U_0402_16V4Z

C571

1

0.1U_0402_16V4Z

C570

2

0.1U_0402_16V4Z

8151@

2

1

8151@

1

0.1U_0402_16V4Z

C569

20mils

CLKREQ#
DVDDL
DVDDL_REG
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

AVDDH
AVDDH
AVDDH_REG

+3V_LAN

1
2
R554 2.37K_0402_1%

+1.7_LX

1

+1.7_LX

40mils

5

+1.7_VDDCT

24
37

+1.1_DVDDL
+1.1_DVDDL

16
22
9

+2.7_AVDDH_R
+2.7_AVDDH
+2.7_AVDDH

2 C564
0.1U_0402_16V4Z

1

+1.7_VDDCT

2

20mils

20mils
1 8151@

1

GND
S IC AR8151-BL1A-RL QFN 40P E-LAN CTRL
8151@

2

1

2

2 +2.7_AVDDH
R738 0_0402_5%

1

2

+3VALW

1

2

1

2

C

@ R555
0_1206_5%
2
1

Modify R03

40mils

C575

4

2
0_0402_5%

40

Close Pin 10

LAN_RBIAS

1

@

2

1

Modify R02

3
Q76
AO3413L_SOT23-3

G

1
R556

VDD33

1

XTLO
XTLI

8151@
LAN_CLKREQ#

14 LAN_CLKREQ#

10

S

LAN_XTALO
LAN_XTALI

TEST_RST
TESTMODE

RBIAS

D

8152@
1
2
C563
0.1U_0402_16V4Z

SMCLK
SMDATA

2

@

36
36
36
36
36
36
36
36

C568

EC_PME#

39 EC_PME#

C

R552 1

LAN_MIDI0LAN_MIDI0+
LAN_MIDI1LAN_MIDI1+
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3LAN_MIDI3+

10U_0603_6.3V6M

PCH_PCIE_WAKE#

15,37,44 PCH_PCIE_WAKE#

2

12
11
15
14
18
17
21
20

C567

LAN_RST#

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

LAN_ACT 36
LAN_LINK# 36

10U_0603_6.3V6M

REFCLK_N
REFCLK_P

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

1 0_0402_5%
1 0_0402_5%

LAN_CLKREQ#
2
0_0402_5%

C566

14 CLK_PCIE_LAN#
14 CLK_PCIE_LAN

R551 2
R549 2

1
R550

1U_0402_6.3V6K

RX_P

32
33

CLK_PCIE_LAN#
CLK_PCIE_LAN

8152@

C565

RX_N

35

38
39
23

0.1U_0402_16V4Z

36

PCIE_PTX_C_DRX_P1

LED_0
LED_1
LED_2

PCH_PWR_EN#

PCH_PWR_EN# 20,46

C15 & C16 Close pin1 < 200mil
C13 & C14 Close pin < 400mil
1

2

1

2

1

2

C581

PCIE_PTX_C_DRX_N1

8151-AL1A

0.1U_0402_16V4Z

14 PCIE_PTX_C_DRX_P1

Atheros

C580

TX_P

1U_0402_6.3V6K

30

0.1U_0402_16V4Z

PCIE_PRX_C_DTX_P1

C578

2 0.1U_0402_16V7K

0.1U_0402_16V4Z
C579

PCIE_PRX_DTX_P1 C562 1

Note 2 : C553, C555, C557, C559 reserved for EMI.

8151@

14 PCIE_PRX_DTX_P1

C577

TX_N

0.1U_0402_16V4Z

29

C576

PCIE_PRX_C_DTX_N1

1U_0402_6.3V6K

2 0.1U_0402_16V7K

2
5.1K_0402_5%

0.1U_0402_16V4Z

PCIE_PRX_DTX_N1 C561 1

14 PCIE_PTX_C_DRX_N1

LED0,1,2 intel Pull UP

U20

Place Close to Chip
14 PCIE_PRX_DTX_N1

1
R548

2

1

LAN_XTALI
LAN_XTALO
Y4

B

1

Near
Pin13

Near
Pin19

Near
Pin31

Near
Pin34

Near
Pin6

Near
Pin9

Near
Pin22

Near Near
Pin16 Pin37

Near
Pin24
B

2

Modify R02

C583

2

1

2

15P_0402_50V8J

C582

18P_0402_50V8J

25MHZ_12PF_X5H025000DC1H-H

1

Note: Place Close to LAN chip
L2 DCR< 0.15 ohm
Rate current > 1A
Modify R02

+1.7_VDDCT

+1.7_LX

1

4

Pin4

R556

Configure
Pin23

C563

2
C587

Configure

LAN_RST#

2

1

10U_0603_6.3V6M

Y
A

C585

B

P

U21
2

@
2

G

@
PLT_RST#

5,17,38,39,44 PLT_RST#

5

C584
1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

@

C586

+3V_LAN

1000P_0402_50V7K

L30
1
2
4.7UH_SIA4012-4R7M_20%

40mils
Modify 03
Link CIS symbol C587.C567.C568

Modify R03

R550

3

NC7SZ08P5X_NL_SC70-5

A

Pull low 100K at PCH side(P17)

1
R558

2
0_0402_5%

AR8152

VDDCT_REG

AR8151

CLKREQn

CLKREQn

*

*

Close to
Pin40

LED[2]

*

A

Reserve for 8151A/B PERST# leakage issue

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN Board AR8151 RevB
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

35

of

59

5

4

3

2

1

D

D

Modify R02
Change T63 from SP050003T10 to SP050003T20
T63

12
11
10

TD4TD4+
TCT4

MX4MX4+
MCT4

13
14
15

RJ45_MIDI0+
RJ45_MIDI0-

LAN_MIDI1+
LAN_MIDI1-

9
8
7

TD3TD3+
TCT3

MX3MX3+
MCT3

16
17
18

RJ45_MIDI1+
RJ45_MIDI1-

6
5
4

TD2TD2+
TCT2

MX2MX2+
MCT2

19
20
21

RJ45_MIDI2+
RJ45_MIDI2-

22
23
24

RJ45_MIDI3+
RJ45_MIDI3-

35 LAN_MIDI2+
35 LAN_MIDI2-

LAN_MIDI2+
LAN_MIDI2-

35 LAN_MIDI3+
35 LAN_MIDI3-

LAN_MIDI3+
LAN_MIDI3-

3
2
1

TD1TD1+
TCT1

MX1MX1+
MCT1

JRJ45
LAN_ACT_R
2
300_0402_5%
RJ45_MIDI3-

1
R559

35 LAN_ACT
@
C588
470P_0402_50V7K

1

2

C

Yellow LED-

11

Yellow LED+

8

PR4-

RJ45_MIDI3+

7

PR4+

RJ45_MIDI1-

6

PR2-

RJ45_MIDI2-

5

PR3-

RJ45_MIDI2+

4

PR3+

RJ45_MIDI1+

3

PR2+

RJ45_MIDI0-

2

PR1-

RJ45_MIDI0+

1

PR1+

350UH_GSL5009-1-LF

+1.7_VDDCT

2

2
R564
75_0402_1%
2
1
R565
75_0402_1%

C594

C593

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

C592

1

0.1U_0402_16V4Z

C591

2

35 LAN_LINK#
@
C589
470P_0402_50V7K

1
R563

1

LAN_LINK#_R
2
300_0402_5%

10
9

+3V_LAN

10/01 Check footprint OK
C

Guide Pin
SHLD2
SHLD1

13
14

Green LEDGreen LED+
SANTA_130451-K
CONN@

2

2

C599

C598
@

@

2

1

2

@
C862
4.7U_0603_6.3V6K

RJ45_GND

C595
1000P_1206_2KV7K
1
2

Reserve for EMI

For EMI

LANGND

40mil
LAN_ACT_R
LAN_LINK#_R

D47
PJDLC05C_SOT23-3

L31
100UH_SSC0301101MCF_0.18A_20%

Close CT1
Close CT3
Close CT2
Close CT4

Modify R02

2

3

2

2

1

40mil

2

@

1

1000P_0402_50V7K

2

1

1000P_0402_50V7K

@

C597

1

1000P_0402_50V7K

RJ45_GND

Modify R02

C596

2

1000P_0402_50V7K

C590

1

1

0.1U_0402_16V4Z

+1.7_VDDCT_R

2

R560
0_0603_5%

2
1
R561
75_0402_1%
2
1
R562
75_0402_1%
1

25mil

1U_0402_6.3V6K

1

12

1

35 LAN_MIDI1+
35 LAN_MIDI1-

LAN_MIDI0+
LAN_MIDI0-

3

35 LAN_MIDI0+
35 LAN_MIDI0-

B

1

D13
PJDLC05C_SOT23-3
@

B

1

LANGND

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN Magnetic & RJ45
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

36

of

59

A

B

1

C606
0.1U_0402_16V4Z

C607
0.1U_0402_16V4Z

+3VS

1

+3VS_WLAN
JMINI1

14 MINI1_CLKREQ#
14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

14 PCIE_PRX_DTX_N2
14 PCIE_PRX_DTX_P2

14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2

R574
0_0402_5%
1
2 E51TXD_P80DATA1_R
1
2 E51RXD_P80CLK_R
R816
0_0402_5%

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Primary Power (mA)

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

WL_OFF#
PLT_RST_BUF#
R569 1

2 0_0603_5%

MINI1_SMBCLK R570 1
MINI1_SMBDATA R571 1

@
@

2 0_0402_5%
2 0_0402_5%

Normal

53
54
55
56

+VSB

WL_OFF# 18
PLT_RST_BUF# 17
+3VS

1
3
5
7
9
11
13
15
17
19

1
3
5
7
9
11
13
15
17
19

22

G2

G1

21

USB20_N9
USB20_P9

USB20_N9 17
USB20_P9 17

USB20_N12
USB20_P12

USB20_N12 17
USB20_P12 17

UIM_DET_EC

UIM_DET_EC 39
EC_SIM_DETECT# 39
WWAN_DET#_EC 39

PCH_SMBCLK 14
PCH_SMBDATA 14

R573 1

2 0_0402_5%
MINI1_LED# 39

(9~16mA)
Modify R02
Change 3G Power to 3G board
Change L49 . L50.R764.R765.R766.R767 to 3G Board.(RF suggestion )

R575
100K_0402_5%

ACES_88910-5204
CONN@

2

+3VS_WLAN

10/04 Check footprint ok
Footprint: BELLW_80003-1021_52P
WLAN&BT Combo module circuits

1

D

Q70

3

D45
RB751V-40_SOD323-2
1
2 BT_CTRL
@
BT_ON#

2
4
6
8
10
12
14
16
18
20

ACES_88242-2001
CONN@

2

R576
100K_0402_5%
2
1

1
R817
1K_0402_5%

WWAN_OFF#
WWAN_LED#

18 WWAN_OFF#
39 WWAN_LED#

2
4
6
8
10
12
14
16
18
20

USB20_N8 17
USB20_P8 17

4 mm High

2



39,46,52,53 SUSP#

Power

J3G1

G1
G2
G3
G3

39 E51TXD_P80DATA
39 E51RXD_P80CLK

1
3
5
7
9
11
13
15

1

(WLAN_BT_DATA)
(WLAN_BT_CLK)

1

Mini Card Power Rating

+1.5VS +3VS_WLAN

@ R568
0_0402_5%
1
2

15,35,44 PCH_PCIE_WAKE#

S

2N7002H_SOT23-3


2
G

BT
on module

BT
on module

Enable

Disable

H

L

L

H

BT_CTRL
BT_ON#

+5VALW

+USB_VCCB

3

3

VOUT
VOUT
VOUT
FLG

8
7
6
5

R578
0_0402_5%
1
2

USB_OC0# 17
+3VALW

BT_ON# 1 BT@
2
R579 10K_0402_5%

1
1

+USB_VCCA
+USB_VCCB

AP2301MPG-13_MSOP8

SYSON#

Follow HW3 Standard Part
(AP2301MPG-13_MSOP8)

4

17 USB20_N0
17 USB20_P0

USB20_N0
USB20_P0

17 USB20_N1
17 USB20_P1

USB20_N1
USB20_P1
USB20_N2
USB20_P2

17 USB20_N2
17 USB20_P2
39,40,50 BI

R838 1

40 BI_RESET

R839 1

Modify R02 -->D-Door

A

JUSB1

W=100mils
USB_OC1# 17

@

41

B

2

0_0402_5% BI_R

2

0_0402_5%
BI_R

C615
BT@
0.1U_0402_16V4Z

22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

G2
G1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2005N
CONN@

(Port 13)
+BT_VCC
JBT1

W=40mils
BT@

BT@

R580
300_0603_5%
BT@

S

BT@
Q33
2N7002H_SOT23-3

2008/08/10

USB20_P13 17
USB20_N13 17

4

Compal Electronics, Inc.
2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

6
5
4
3
2
1

10/01 Check footprint OK

Compal Secret Data

Security Classification

G2 6
G1 5
4
3
2
1

ACES_87213-0600G
CONN@
D

2
G

Issued Date

8
7

+BT_VCC
1

R746
0_0402_5%
1
2

2

(Port 0,1,2)

1

8
7
6
5

2

9

EPAD

1
2

SYSON#

VOUT
VOUT
VOUT
FLG

C617
0.1U_0402_16V4Z

46

GND
VIN
VIN
EN

BT Conn.

Q32
BT@
AO3413L_SOT23-3

C616
4.7U_0603_6.3V6K

C815
4.7U_0603_6.3V6K

G
D

U40
1
2
3
4

3
2

1

BT_ON#

2

18

C614
BT@
1U_0603_10V4Z

1

USB/B Conn.

+USB_VCCA

S

3

+5VALW

2

@
C613
0.1U_0402_16V4Z

SYSON#

SYSON#

+3VS

AP2301MPG-13_MSOP8

1

46

9

1
2

C612
4.7U_0603_6.3V6K

GND
VIN
VIN
EN

EPAD

U22
1
2
3
4

Modify R03

2

2

E

2

1

C605
0.1U_0402_16V4Z

2

1

C604
4.7U_0603_6.3V6K

2

1

2

C603
0.1U_0402_16V4Z

+3VS_WLAN

2

C602
4.7U_0603_6.3V6K

2

60mil

+1.5VS

1

1

+3VS_WLAN

+3VS_WLAN

R566
0_0805_5%
2
1

D

For 3G / GPS
To 3G Module Connect

Modify R03

For Wireless LAN
+3VS

C

D

Title

MINI CARD (WLAN & TV-Tuner)/USB/BT
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

37

of

59

A

B

C

D

+3VS

+3VS_CARD
1
R833

Card Reader

E

Modify R02, Add 0R between
+3VS and +3VS_CARD

2
0_0805_5%

40 mils

40 mils
Modify R02
U23

1

HSIP

RREF

48

PCIE_PTX_C_DRX_N3

2

HSIN

3V3_IN

47

14 CLK_PCIE_CARD

CLK_PCIE_CARD

3

REFCLKP

CLK_REQ#

46

CARD_CLKREQ#

14 CLK_PCIE_CARD#

CLK_PCIE_CARD#

4

REFCLKN

PERST#

45

PLT_RST#

5

AV12

EEDO

44

14 PCIE_PTX_C_DRX_N3

Modify 03
Link CIS symbol C618

1
C618
PCIE_PRX_DTX_P3 1
C619
PCIE_PRX_DTX_N3 1
C621

14 PCIE_PRX_DTX_P3

2

4.7U_0603_6.3V6M
2 PCIE_PRX_C_DTX_P3
0.1U_0402_10V7K
2 PCIE_PRX_C_DTX_N3
0.1U_0402_10V7K

1
2
C622 0.1U_0402_10V7K

+3VS_CARD

1

2

6

20 mils DV12
40 mils
40 mils

2

C631
0.1U_0402_10V7K

2

@ C630
4.7U_0603_6.3V6K

Close to connector
2

@
1
2
C633 5P_0402_50V8C

CARD_CLKREQ# 14
PLT_RST# 5,17,35,39,44

EECS

HSON

EESK

42

8

GND

GPIO/EEDI

41

9

DV12

MS_INS#

40

5IN1_LED#

5IN1_LED# 41

MS_INS#
SD_CD#

Card1_3V3

SD_CD#

39

3V3_IN

SP15

38

SP15_SDWP_XDD7

12

Card2_3V3

SP14

37

SP14_MSCLK_XDD6

13

XD_CD#

SP13

36

SP13_MSD7_XDD5

14

DV33_18

SP12

35

SP12_MSD3_XDD4

15

GND

SP11

34

SP11_MSD6_XDD3

SP1_SDD7_XDRDY 16

SP1

SP10

33

SP10_MSD2_XDD2

SP2_SDD6_XDRE# 17

SP2

SP9

32

SP9_MSD0_XDD1

SP3_SDD5_XDCE# 18

SP3

SP8

31

SP8_MSD4_XDD0

DV33_18

SD_D1
2
0_0402_5%
SD_D0
2
0_0402_5%
SD_CLK
2
33_0402_5%
SD_CMD
2
0_0402_5%
SD_D3
2
0_0402_5%

20
21
22
23
24

SP4

SP7

30

SD_D1

SP6

29

SP6_MSD5_XDALE

SD_D0

SP5

28

SP5_MSBS_XDCLE

DV12_S

SD_CMD

GND

SD_D3

SD_D2

2 SP14_MSCLK_XDD6_R
0_0402_5%
2
@

1
R583

1

2

SP7_MSD1_XDWP#

SD_CLK

1

2
1
C620 0.1U_0402_10V7K

43

HSOP

7

SP4_SDD4_XDWE# 19
SD_D1_R
1
R584
SD_D0_R
1
R585
SD_CLK_R 1
R586
SD_CMD_R 1
R587
SD_D3_R
1
R588

40 mils

11

20 mils
1

1 6.2K_0603_1%

10

XD_CD#

1

RREF R581 2

C629
5P_0402_50V8C

2

1

C628
0.1U_0402_10V7K

2

+ODR_PWR

C627
10U_0603_6.3V6M

2

1

Modify R02

C626
0.1U_0402_10V7K

2

1

C625
0.1U_0402_10V7K

2

1

C624
10U_0603_6.3V6M

1

C623
0.1U_0402_10V7K

2

14 PCIE_PRX_DTX_N3

@

R582
100K_0402_5%

1

+ODR_PWR

20 mils AV12

+3VS_CARD

10 mils

PCIE_PTX_C_DRX_p3

14 PCIE_PTX_C_DRX_P3

1

1
2
C632 4.7U_0603_6.3V6K

20 mils

27

1
2
C634 0.1U_0402_10V7K

26
SD_D2
1
R589

25

SD_D2_R
2
0_0402_5%

RTS5209-GR_LQFP48_7X7

+ODR_PWR

Reserve for EMI please close to JREAD1

+ODR_PWR
JREAD1
39

3

SP8_MSD4_XDD0
SP9_MSD0_XDD1
SP10_MSD2_XDD2
SP11_MSD6_XDD3
SP12_MSD3_XDD4
SP13_MSD7_XDD5
SP14_MSCLK_XDD6
SP15_SDWP_XDD7

31
32
33
34
35
36
37
38

SP4_SDD4_XDWE#
SP7_MSD1_XDWP#
SP6_MSD5_XDALE
XD_CD#
SP1_SDD7_XDRDY
SP2_SDD6_XDRE#
SP3_SDD5_XDCE#
SP5_MSBS_XDCLE

28
29
27
22
23
24
25
26
30
40

41
42

XD-VCC

SD4-VDD
MS9-VCC

XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7

SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP

XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE

SD6-VSS
SD3-VSS

MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS

XD GND
XD GND

SD CD/WP GND
SD CD/WP GND

11
18
8
4
3
21
19
16
1
2

SD_CLK_R
SD_D0_R
SD_D1_R
SD_D2_R
SD_D3_R
SD_CMD_R
SD_CD#
SP15_SDWP_XDD7

2

2

R590
22_0402_5%

1

C635
10P_0402_50V8J
3

Reserve for EMI
please close to JREAD1

6
13

17
10
9
12
15
14
7
5
20

1

SP14_MSCLK_XDD6_R
SP9_MSD0_XDD1
SP7_MSD1_XDWP#
SP10_MSD2_XDD2
SP12_MSD3_XDD4
MS_INS#
SP5_MSBS_XDCLE

1

2

R591
22_0402_5%

1

2

C636
10P_0402_50V8J

PLAST_CM5S-212-H-D_NR
CONN@

10/5 Update symbol

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Card Reader RTS5209
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

38

of

59

5

4

3

2

1

+3VALW_EC

+3VLP

R623
0_0805_5%
@
1
2

LID_SW#

R592

2

1 100K_0402_5%

+3VALW_EC
+5VS

1
ECAGND2
9
22
33
96
111
125

EC_SMI#

R605

1

2 2.2K_0402_5%

EC_SMB_DA1

R606

1

2 2.2K_0402_5%

EC_SMB_CK1

18 EC_SCI#
41 PWR_SUSP_LED

@ R608
33_0402_5%
1
2

1
2
3
4
5
7
8
10

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
PWR_SUSP_LED

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

KSI[0..7]

40,41 KSI[0..7]

Reserve for EMI please close to U24

KSO[0..17]

40,41 KSO[0..17]

+3VS
R610

1

2 2.2K_0402_5% EC_SMB_CK2

R611

1

2 2.2K_0402_5% EC_SMB_DA2

R615

1

2 10K_0402_5% EC_SCI#

PLT_RST#

C863
0.1U_0402_16V4Z

48,50
48,50
14,22
14,22

Modify R02
Add C863 for ESD suggestion
B

1
4

2

15P_0402_50V8J

NC

OSC

C652

3

2

NC

2

OSC

1

1

EC_XCLK0

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
WWAN_DET#_EC
MINI1_LED#
USB_CHARGE_2A#
GPU_VID0
USB_CHARGE_100mA
FAN_SPEED1
PCH_PWR_EN
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF

15 PM_SLP_S3#
15 PM_SLP_S5#
18 EC_SMI#
37 WWAN_DET#_EC
37 MINI1_LED#
45 USB_CHARGE_2A#
22,55 GPU_VID0
45 USB_CHARGE_100mA
45 FAN_SPEED1
46 PCH_PWR_EN
37 E51TXD_P80DATA
37 E51RXD_P80CLK
40 ON/OFF
Modify R1.0
Delete TP_PWM
41 NUM_LED#

NUM_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PWM Output
MISC
AD

1

@

2
100K_0402_5%

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

DAC_BRIG
EC_SIM_DETECT#

DA Output

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

XCLK1
XCLK0

V18R

2

2

2

Rb

1 100P_0402_50V8J ECAGND
BATT_TEMP 50
BI
37,40,50
ADP_I 48,50

2 510K_0402_5%

ACIN 15,46,48

GFX_CORE_PWRGD

1
C870

2
0.1U_0402_16V4Z

modify R03
@

T69

PAD

DAC_BRIG 31
EC_SIM_DETECT# 37
@ T67
PAD
@ T68
PAD

U25
H_PROCHOT#_EC

83
84
85
86
87
88

EC_MUTE#
GFX_CORE_PWRGD
WWAN_LED#
H_PROCHOT#_EC
TP_CLK
TP_DATA

97
98
99
109

GPU_VID1
65W/90W#
HDA_SDO
LID_SW#

119
120
126
128

FRD#_R
FWR#_R
SPI_CLK_R
FSEL#_R

73
74
89
90
91
92
93
95
121
127

EC_MUTE# 42,43
GFX_CORE_PWRGD 54
WWAN_LED# 37
TP_CLK 40
TP_DATA 40
GPU_VID1 22,55
65W/90W#
HDA_SDO 13
LID_SW# 41
1
1
1
1

UIM_DET_EC
EC_PECI
R617 1
USB_CHARGE_CB
BATT_AMB_LED#
CAPS_LED#
BATT_BLUE_LED#
PWR_LED
SYSON
VR_ON
EC_ACIN

2
2
2
2

VR_HOT#

0_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

PCH_RSMRST#
LID_SW_OUT#
EC_ON
EC_PME#
PCH_PWROK
BKOFF#
PWR_SAVE_LED#
WLAN_LED#
BATT_RED_LED#

110
112
114
115
116
117
118

PM_SLP_S4#
ENBKL
EAPD
SA_PGOOD
SUSP#
PBTN_OUT#
NV_PERFORMANCE

124

+V18R

1
C648
Y

2
0.1U_0402_16V4Z

4
C

SN74LVC1G06DCKR_SC70-5

R609
0_0402_5%
2
1

H_PROCHOT# 5,50

DG1.5 suggest change UE4 to 74LVC1G06.
FRD#
FWR#
SPI_CLK
FSEL#

2 43_0402_1%

UIM_DET_EC 37
H_PECI 5,18

USB_CHARGE_CB 45
BATT_AMB_LED# 41
CAPS_LED# 41
BATT_BLUE_LED# 41
PWR_LED 41
SYSON 44,46,51
VR_ON 54

SPI ROM

+3VALW_EC

128KB

U26
20mils
C650
0.1U_0402_16V4Z

100
101
102
103
104
105
106
107
108

A

R607
100K_0402_5%

54 VR_HOT#

R612
R613
R614
R616

2

PCH_RSMRST# 15
LID_SW_OUT# 14
EC_ON 40
EC_PME# 35
PCH_PWROK 15
BKOFF# 31
PWR_SAVE_LED# 41
WLAN_LED# 41
BATT_RED_LED# 41

8
3
7

FSEL#

1

SPI_CLK

6

FWR#

5

VCC

VSS

4

W
HOLD

B

S
C
D

Q

FRD#

2

MX25L2005M2C-12G SOP 8P

KB930QF A1 LQFP 128P

C654

PM_SLP_S4# 15
ENBKL 16
EAPD 42
SA_PGOOD 52
SUSP# 37,46,52,53
PBTN_OUT# 15
NV_PERFORMANCE 22

SPI_CLK

@ R618
22_0402_5%
2
1

@ C653
100P_0402_50V8J
1
2

Reserve for EMI please close to U26

Modify R03

4.7U_0603_6.3V6K

20mil

L33
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

Modify R05
Delete U27

C843
0.1U_0402_16V4Z

SJM
R770 2 SJM@ 1 100K_0402_5%

Modify R1.0
5

C645

A

AD_PID0
1

JM

2

1
1

1

1
1

C655
0.1U_0402_16V4Z

EC_ACIN

1
RB751V-40_SOD323-2
2
1 100P_0402_50V8J

R769
100K_0402_5%

Ra

AD_BID0
R621
33K_0402_5%

2

2

2

+3VALW_EC

R620
100K_0402_5%

1 200K_0402_5%

2

SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P 3.3V)

Project ID

Analog Board ID definition,
Please see page 3.

JM@ R770
18K_0402_5%

Board ID

2 10K_0402_5%

1

+3VS

11
24
35
94
113

R799

122
123

C647 2

BATT_TEMP
R848 1
ADP_I
AD_BID0
AD_PID0

1

2

1 10K_0402_5%

D14

3G_LED# 41
BEEP# 42
FAN_PWM 45
ACOFF 47

63
64
65
66
75
76

AGND

@

3G_LED#
BEEP#
FAN_PWM
ACOFF

21
23
26
27

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

69

EC_XCLK1
EC_XCLK0
0_0402_5%

1
R619

@

+3VALW_EC

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

GND
GND
GND
GND
GND

15 SUSCLK_R

Rb

R601

D

R602

X1
32.768KHZ_12.5PF_Q13MC14610002

Ra

BKOFF#

+3VS
2

5

KSO2

2 10K_0402_5%

17 CLK_PCI_LPC
5,17,35,38,44 PLT_RST#

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

C

A

R596

P

2 47K_0402_5%

1

+3VALW_EC

EC_MUTE#

NC

1

R600

15P_0402_50V8J

4.7K_0402_5%

G

R599

C651

2

1

KSO1

EC_XCLK1

1

1

2 47K_0402_5%

1

R595

2

1

2

TP_DATA

1

10/1 ENE Recommand

@ C649
22P_0402_50V8J
2
1

4.7K_0402_5%

2

18 GATEA20
18 EC_KBRST#
13 SERIRQ
13 LPC_FRAME#
13 LPC_AD3
13 LPC_AD2
13 LPC_AD1
13 LPC_AD0

+3VALW_EC

R598

2

EC_RST#

0.1U_0402_16V4Z

1

1

C643
0.1U_0402_16V4Z

2

1 47K_0402_5%

C646 2

R594

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
R603 2

+3VALW_EC

TP_CLK

3

2

2
1

1
2

1
2

1
2

1
2

1
U24

C642
1000P_0402_50V7K

C641
1000P_0402_50V7K

C640
0.1U_0402_16V4Z

CLK_PCI_LPC

C639
0.1U_0402_16V4Z

@ R597
33_0402_5%
2
1

C638
0.1U_0402_16V4Z

@ C644
22P_0402_50V8J
2
1

C637
0.1U_0402_16V4Z

D

L32
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW_EC

67

R593
+3VALW 0_0805_5%
1
2

4

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
EC ENE-KB930

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

39

of

59

1

2

INT_KBD Conn.

3

4

5

6

7

8

Modify R02
KB connector use JKB2,JKB1 reserved.
SJM

KSI[0..7]

KSI[0..7] 39,41

KSO[0..17]

(Left)

KSO[0..17] 39,41

A

KSO7

C659 1

2

100P_0402_50V8J

KSO6

C663 1

2

100P_0402_50V8J

KSO5

C665 1

2

100P_0402_50V8J

KSO4

C667 1

2

100P_0402_50V8J

C669 1

2

100P_0402_50V8J

KSI4

C671 1

2

100P_0402_50V8J

KSO2

C673 1

2

100P_0402_50V8J

KSO1

C675 1
C677 1

2

100P_0402_50V8J

KSI5

C679 1

2

100P_0402_50V8J

KSI7

100P_0402_50V8J

2

100P_0402_50V8J

KSO15

C662 1

2

100P_0402_50V8J

C664 1

100P_0402_50V8J

2

KSO13

C666 1

2

100P_0402_50V8J

KSO12

C668 1

2

100P_0402_50V8J

C670 1

100P_0402_50V8J

2

KSO11

C672 1

2

100P_0402_50V8J

KSO10

C674 1

2

100P_0402_50V8J

KSI1

C676 1

2

100P_0402_50V8J

KSI2

C678 1

2

100P_0402_50V8J

KSO9

C680 1

2

100P_0402_50V8J

KSI3

C682 1

2

100P_0402_50V8J

KSO8

C684 1

2

100P_0402_50V8J

100P_0402_50V8J

2

C683 1

2

C658 1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

100P_0402_50V8J

2

C681 1

C657 1

KSO17

KSI0

KSO0

KSI6

KSO16

KSO14

KSO3

100P_0402_50V8J

2

JM
JKB2

(Right)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

JKB1

(Left)

KSO7

C819 1

2 @

100P_0402_50V8J

KSO6

C821 1

2 @

100P_0402_50V8J

KSO5
KSO4
KSO3
KSI4

27
28

2 @

C825 1

2 @

C827 1

2 @

C829 1

2 @

C817 1

2 @

100P_0402_50V8J

KSO17

C818 1

2 @

100P_0402_50V8J

KSO15

C820 1

2 @

100P_0402_50V8J

KSO14

C822 1

2 @

100P_0402_50V8J

KSO13

C824 1

2 @

100P_0402_50V8J

KSO12

C826 1

2 @

100P_0402_50V8J

KSI0

C828 1

2 @

100P_0402_50V8J

KSO11

C830 1

2 @

100P_0402_50V8J

KSO10

C832 1

2 @

100P_0402_50V8J

KSI1

C834 1

2 @

100P_0402_50V8J

KSI2

C836 1

2 @

100P_0402_50V8J

KSO9

C838 1

2 @

100P_0402_50V8J

KSI3

C840 1

2 @

100P_0402_50V8J

KSO8

C842 1

2 @

100P_0402_50V8J

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO2

C831 1

2 @

100P_0402_50V8J

KSO1

C833 1

2 @

100P_0402_50V8J

KSO0

G1
G2

C823 1

KSO16

C835 1

2 @

100P_0402_50V8J

KSI5

C837 1

2 @

100P_0402_50V8J

KSI6

C839 1

2 @

100P_0402_50V8J

KSI7

C841 1

2 @

100P_0402_50V8J

ACES_85201-26051
CONN@

(Right)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

A

G1
G2

27
28

ACES_85201-26051
CONN@

10/04 Check footprint ok

B

B

Modify R02
+3VALW_EC

To TP/B Conn.

10/04 Check footprint ok

ON/OFF switch

Power Button

2

41 ON/OFFBTN#

R622
100K_0402_5%

TOP Side
LEFT_BTN#

TP_DATA

RIGHT_BTN#

2

D17

1

TP_CLK

SW4
SMT1-05-A_4P
1
3

2

ON/OFFBTN#

TP_CLK
TP_DATA
1

+RTCVCC
R836
1K_0402_5%
1
2

Reset Button
TP_CLK

BI

Modify R02

@
C864
0.1U_0402_16V4Z

49,50 MAINPWON

D19
PJDLC05C_SOT23-3
SJM@

49 3V5V EN

R844
@
1K_0402_5%
1
2

3
1

S

1

2

BI_GATE 2

2

37,39,50

Q72
AO3413L_SOT23-3

G

D

S

1

SKPMAME010_2P

1

BAV70W_SOT323-3
BI_GATE

BI

D

@

Q77
2N7002H_SOT23-3

2
G

R837
10K_0402_5%

D

BI_RESET 37

2

1

SW7

3

D18

1

TP_DATA
3

2

1
1

@

2

1
2

ACES_85201-0605N
CONN@

TP_DATA
TP_CLK
C706
100P_0402_50V8J

6
5
4
3
2
1

C703
100P_0402_50V8J

D

+5VS

+3VS

2

JTP2
GND
GND
6
5
4
3
2
1

2

6
5

Change D17 from SC1N202U010 to SC600000B00

Test Only

Modify R05

8
7

C

4

@

Place D15.D16.C660.C661 near JTP1

SJM

Q34
2N7002H_SOT23-3

10K_0402_5%

3

Modify R03
SW2.SW3-->100g

@

2

1

TP_CLK 39
TP_DATA 39

2

2

S

1

1

1
4
5
6

SW3 JM@
SMT1-05-A_4P
1

5
6

2

3

C661
100P_0402_50V8J

4

RIGHT_BTN#

C660
100P_0402_50V8J

SW2 JM@
SMT1-05-A_4P
1

D

2
G

R624

SW5
SMT1-05-A_4P
1
3
2

3

EC_ON

Bottom Side

C

LEFT_BTN#

EC_ON

1

JM@
D16
PJDLC05C_SOT23-3

39

ACES_85201-0605N
CONN@

51ON# 47

BAV70W_SOT323-3

2

3

2
JM@
D15
PJDLC05C_SOT23-3

JM@
C656
0.1U_0402_16V4Z

51ON#

3
4
6
5

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

3

+5VS

+5VS
6
5
4
3
2
1

1

GND
GND
6
5
4
3
2
1

2

8
7

ON/OFF 39

1

JTP1

3

JM

Modify R02
JTP1 Pin define inverse

Place D19.C706.C703 near JTP2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

5

6

Title

I/O Port & K/B Connector/PWR OK
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011
7

Sheet

40
8

of

59

B

C

Battery LED(JM)

D

Modify R02
LED_HT-210UD5-NB5
A-->AMB
B-->BLUE

Battery LED(SJM)
Modify R05

Modify R02
LED_HT-210UD5-NB5
A-->AMB
B-->BLUE

Side View LED with Blue/Amber/Red Color
Modify R05

+3VALW

3

3

B

BATT_AMB_LED#

BATT_BLUE_LED# 39

LED7 SJM@

A

1

LED2 JM@

2

BATT_AMB_LED#

BATT_AMB_LED# 39

BATT_BLUE_LED#

B

BATT_RED_LED#

BATT_BLUE_LED# 39

KSO0

SW6
MPTCFG-T-Q-T-R_2P
JM@
KSI2
2

1

KSI2 39,40

BATT_RED_LED# 39
HT-210UD5-NB5_AMBER-BLUE
LED8 SJM@

HT-110USD5_RED

3

R802 SJM@
510_0402_1%
1
2
R803 SJM@
100_0402_1%
1
2

3
1

R

Battery Indicator BTN (JM only)

HT-210UD5-NB5_AMBER-BLUE
BATT_BLUE_LED#

HT-210UD5-NB5_AMBER-BLUE

2

1

BATT_BLUE_LED# 39

BATT_AMB_LED# 39

B

R739 JM@
390_0402_5%
1
2

BATT_AMB_LED# 39

BATT_BLUE_LED#

3

2

A

1

R625 JM@
750_0402_1%
1
2
R626 JM@
200_0402_5%
1
2

BATT_AMB_LED#

A

1

R804 SJM@
510_0402_1%
1
2
R805 SJM@
100_0402_1%
1
2

2
3

Modify R05
BATT_AMB_LED#

BATT_AMB_LED# 39

BATT_BLUE_LED#

B

Power LED(JM)

6

LED1 JM@

A

1

R800 SJM@
510_0402_1%
1
2
R801 SJM@
100_0402_1%
1
2

2

5

1

+3VALW
LED6 SJM@

E

4

A

BATT_BLUE_LED# 39

PWR/B

HT-210UD5-NB5_AMBER-BLUE
+3VALW

2

R627 JM@
1.6K_0402_1%
1
2
R629 JM@
3.9K_0402_5%
1
2

LED3 JM@
2
4

LED9 SJM@
PWR_LED#

1

B

A

1
PWR_SUSP_LED#

3

A

JM

R806 SJM@
510_0402_1%
1
2
R807 SJM@
100_0402_1%
1
2

2
3

+3VALW
BATT_AMB_LED#
BATT_BLUE_LED#

B

HT-297UD5-CB5_AMBER-BLUE

HT-210UD5-NB5_AMBER-BLUE

7
8

+3VS

@
R632
10K_0402_5%

2

B

1

MEDIA_LED#4

3

HT-191NB5_BLUE

A

+3VALW

1

U39
2

5IN1_LED# 38

B

Y
G

JM@
2
750_0402_1%

P

LED4 JM@
1

R740

5

+3VS

1

PCH_SATALED# 13

MC74VHC1G08DFT2G_SC70-5

R808 SJM@
150_0402_1%
1
2
R809 SJM@
750_0402_1%
1
2

B

3

R741 JM@
1.47K_0402_1%
1
2
R742 JM@
3.9K_0402_5%
1
2

PWR_LED#

3

PWR_SUSP_LED#

+3VALW
JPWR2

4

A

1
2
3
4
5
6
GND
GND

HDD LED(SJM)

1
2
3
4
5
6

LID_SW#
PWR_LED#
ON/OFFBTN#
BI_R

LID_SW# 39
BI_R

37

Modify R02
SJM D-door

ACES_85201-0605N
CONN@

LED5 JM@
2

B

1

3G_LED#

4

A

3

WLAN_LED#

3G_LED# 39

+3VS

LED11

1 SJM@ 2
R811
100_0402_1%

WLAN_LED# 39

2

3

SJM@

B

1

MEDIA_LED#

LED Board (JM only)

HT-191NB5_BLUE

HT-297UD5-CB5_AMBER-BLUE

JLED1
1
2
3
4
5
6
7
8
9
10
GND
GND

3G/Wireless LED(SJM)

PWR_SUSP_LED#

2
2

39 PWR_SUSP_LED

6

+3VS
Q36A

R812 SJM@
150_0402_1%
1
2
R813 SJM@
680_0402_5%
1
2

D

G
DMN66D0LDW-7_SOT363-6
1

R628
100K_0402_5%

S

1

LED Status

1

3G_LED#

4

A

3

WLAN_LED#

3G_LED# 39
WLAN_LED# 39

+3VS
PWR_SAVE_LED# 39
NUM_LED# 39
CAPS_LED# 39
KSO0 39,40
KSI1 39,40

Modify R02
LID_SW# -->Power board

ACES_85201-1005N
CONN@

Power/SUS
ON

SUS

Battery
Full Charge

3G/WLAN
3G

BlueTooth

KSO0

ACIN

WLAN

D

Blue Amber

5
G

Blue Amber

Blue Amber

KSI0

Battery

KSI1

PWR SAVE BTN#

BTN#
4

DMN66D0LDW-7_SOT363-6
4

2

B

PWR_SAVE_LED#
NUM_LED#
CAPS_LED#
KSO0
KSI1

S

1

R630
100K_0402_5%

3

Q36B
39 PWR_LED

LED12 SJM@
2

1
2
3
4
5
6
7
8
9
10
11
12

HT-297UD5-CB5_AMBER-BLUE

PWR_LED#

4

2

ON/OFFBTN# 40

SJM

1

7
8

3G/Wireless LED(JM)

LID_SW# 39

LED10 SJM@
2

HT-297UD5-CB5_AMBER-BLUE

+3VS

LID_SW#
PWR_LED#
ON/OFFBTN#

ACES_85201-0605N
CONN@

Power LED(SJM)

2

HDD LED(JM)

1
2
3
4
5
6

1
2
3
4
5
6
GND
GND

BATT_BLUE_LED# 39

+3VS

Modify R03

Modify R02

JPWR1

BATT_AMB_LED# 39

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

LED/PWR/B
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

41

of

59

5

4

3

2

1

Modify 03
Link CIS symbol C688.C692.C698.C699.C700.C709
2
0_0805_5%

4.75V

+3VS_CODEC

2

D

+VDDA

2
+3VS_CODEC

2

1
RB751V-40_SOD323-2
1

13 HDA_SPKR

2

1

D35
1

34

C801
2

MONO_IN

41
42

0.1U_0402_16V4Z
R731
10K_0402_5%

22

20

18

31

15

9

SPK_OUT_L+
PORTD_R
SPK_OUT_LPORTE_L
SPK_OUT_R+
PORTE_R
SPK_OUT_RPORTF_L
PORTB_L
PORTF_R
PORTB_R
FLY_P
B_BIAS

2

RB751V-40_SOD323-2

PORTD_L

Modify R02
MIC1_L

43 MIC1_L

MIC1_R

43 MIC1_R

Modify R02
CX2058-21Z Option Component

23
2
1U_0603_10V4Z

1
C702

MIC_L
35
2
2.2U_0603_6.3V6K
MIC_R
36
2
2.2U_0603_6.3V6K
37

1
C704
1
C705

MIC1_VREFO

FLY_N

SDATA_IN
SDATA_OUT

PORTC_L
SYNC
PORTC_R
RESET#
C_BIAS
BIT_CLK

14
16
19
17

SPKL+ JM@ L41 1
2
FBMA-L11-201209-221LMA30T_0805
SPKL- JM@ L42 1
2
FBMA-L11-201209-221LMA30T_0805
SPKR+ JM@ L43 1
2
FBMA-L11-201209-221LMA30T_0805
SPKR- JM@ L44 1
2
FBMA-L11-201209-221LMA30T_0805

39

30mils
1
1
1
1

MONO_IN

13
1 EXT_MUTE# 12
0_0402_5%

8

HDA_SDIN0_AUDIO

6
10

1
@ C800

2 33_0402_5%

HDA_RST_AUDIO#
2 22P_0402_50V8J
HDA_BITCLK_AUDIO_R
2 22P_0402_50V8J

11
7

1 R730

PCBEEP
DMIC_CLK0
EXT_MUTE#
DMIC_1/2

CX20584-21Z QFN 48P
21Z@

1
@ C802
1
@ C803

HDA_SDOUT_AUDIO 13
HDA_SYNC_AUDIO

R814 1
2
0_0402_5%

Modify R02

R784
R649
R650
R815

+3VS
43 MIC_PLUG#
43 HP_PLUG#
+3VS

10/14, Add pull up
resistor for vendor
suggestion.

39

2 5.1K_0402_5%
1 10K_0402_1%
1 39.2K_0402_1%
2 5.1K_0402_5%

1
2
2
1

0_0402_5%

EAPD

1

2 R651

0.1U_0402_16V4Z
C808
1
2

0.1U_0402_16V4Z
C809
1
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

49

SENSE A
SENSE B

GPIO1/SPK_MUTE#
GPIO2/SPDIF2

46
45

AVEE
EP_GND

DMIC_CLK 43
DMIC_DATA

SPK_MUTE# 1

DMIC_DATA 43

FILT_1.8V

FILT_1.65V

2EC_MUTE#

0_0402_5%
R652

FILT_1.8
FILT_1.65
AVDD_3.3

5

FILT_1.8V

32

FILT_1.65V

30

LDO_OUT_3.3V

1

2

1

2

Modify R02

CX20584-11Z_QFN48_7X7
11Z@

LDO_OUT_3.3V

AVDD_3.3 pin is output of
internal LDO. Do NOT connect
to external supply.

Modify R02
Delete J2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2
R647

GPIO0/EAPD#
SPDIFO

B

2

C805
2

C714
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
C807
1
2

47

24

2

1
2

A

C804
2

C713
10U_0603_6.3V6M

1

0.1U_0402_16V4Z
C806
1
2

44
43

48

43 SPDIF_OUT
AVEE

EAPD active low
0=power down ex AMP
1=power up ex AMP

1
90.9_0402_1%

3

R733
SENSE_A
SENSE_B

HDA_BITCLK_AUDIO 13

10/14, add the resistor for
reserve ESD purpose.

1
2

13

HDA_RST_AUDIO# 13

1

SA000034020

SPKR-_L 43

HDA_SDIN0 13

HDA_SDOUT_AUDIO
2 22P_0402_50V8J
HDA_SYNC_AUDIO

2

@
2
R732

39,43 EC_MUTE#

SPKR+_L 43

38

U29
DMIC_3/4

SPKL-_L 43

Internal SPEAKER

40

B

21Z@ R635
0_1206_5%

SPKL+_L 43

2 C796
1000P_0402_50V7K
2 C797
1000P_0402_50V7K
2 C798
1000P_0402_50V7K
2 C799
1000P_0402_50V7K

4

3

0.1U_0402_16V4Z

BEEP#

C

10/14, change values of cap to
meet vendor ref circuit.

C712
2

39

33

2

1

D34

2

1

1U_0402_6.3V6K

28

1

C716
1

43 AMP_RIGHT

Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)

2

27

2

For version of 21Z, changing R635 from
0.1R to 0R.

10U_0603_6.3V6M

PORTA_R

43 AMP_LEFT

RPWR5.0

PORTA_L

26

2

1

2

CLASSDREF

25

HP_RIGHT

LPWR5.0

43 HP_RIGHT

VDD_IO

43 HP_LEFT

VAUX_3.3

U29

4

C

HP_LEFT

1

1

Please bypass caps very close to device.

AVDD_5V

2

2

29

2

Modify R02
Delete R638.Q39.Q38
Add R835 between EC_MUTE# and PD#.

1

AVDD_HP

1

21

C700

Modify R02
Delete R639 and R640

2

1
1

40mils

DVDD_3.3

2
0_0805_5%

0.1U_0402_16V4Z

2

+3VS_CODEC

0.1U_0402_16V4Z

1
R834

1

10U_0603_6.3V6M
C701

40mils

1U_0603_10V4Z
C694

C693

1

2
+3VS

R635
0.1_1206_1%
11Z@

+3VS_CODEC

Modify R02
Delete R634 and R636

C695
0.1U_0402_16V4Z

Modify R02
Add R834 between +3VS and +3VS_Codec.
change power from +3VS to +3VS_CODEC.

1

C711
2
1

(output = 300 mA)

2

1

0.1U_0402_16V4Z

2

1

C715
1

1

0.1U_0402_16V4Z

4

10U_0603_6.3V6M
C710

BYP

10K_0402_5%
C709

1
2
C687
G9191-475T1U_SOT23-5 0.01U_0402_16V7K
@
@
SHDN

C699
10U_0603_6.3V6M

+VDDA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

C698
10U_0603_6.3V6M

D

2

2

3

40mil
OUT

C697
0.1U_0402_16V4Z

GND

C692

2
C686

10U_0603_6.3V6M
C691

IN

C696
0.1U_0402_16V4Z

1

1

C685

U28
1

0.1U_0402_16V4Z

60mil

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C690

+5VAMP
L34 1
2
FBMA-L11-201209-221LMA30T_0805
@
L35 1
2
FBMA-L11-201209-221LMA30T_0805

+5VS

C688

1
R633

10U_0603_6.3V6M
C689

SM010014520 3000ma 220ohm@100mhz DCR 0.04

2

Title

HD Audio Codec CX20584
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

42

of

59

A

2

2

GAIN0

GAIN0
GAIN1

2

GAIN0

NC

12

SHUTDOWN

19

EC_MUTE#

8

AMP_SPKL-

14

AMP_SPKR-

LOUT+

4

AMP_SPKL+

ROUT+

18

AMP_SPKR+

LOUT-

3

GAIN1
ROUT-

1

GAIN1
1

1

42 AMP_LEFT
@ R773
100K_0402_5%

@
R774
100K_0402_5%

42 AMP_RIGHT

AMP_C_LEFT
1
0.47U_0603_10V7K @
AMP_C_RIGHT
1
0.47U_0603_10V7K @

2
C847
2
C848

@
@

2

2

@
@

AMP_R_LEFT
0_0603_5%
AMP_R_RIGHT
0_0603_5%

R779
R780
2
C849
2
C850

1

5

LIN-

17

RIN-

9

LIN+

0.47U_0603_10V7K
7

1

GND
GND
GND
GND
GND

RIN+

0.47U_0603_10V7K

BYPASS
TPA6017A2PWPR_TSSOP20

EC_MUTE# 39,42

30mils

30mils

AMP_SPKL+
AMP_SPKLAMP_SPKR+
AMP_SPKR-

@
@
@
@

R775
R777
R776
R778

1
1
1
1

2
2
2
2

JSPK2

SPK_L+
SPK_LSPK_R+
SPK_R-

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

SJM@ D38
PJDLC05C_SOT23-3

1
2
3
4

SJM@ D37
PJDLC05C_SOT23-3

1
11
13
20
21
10

SJM

3

1

VDD
PVDD
PVDD

2

1

16
6
15

1
2
3
4

5
6

G1
G2

1

ACES_88266-04001
CONN@

Place D37.D38 near

JSPK2

10/04 Check footprint ok
AMP_BYPASS 2

Keep 10
mil width

Modify 05 SJM don't use Audio AMP

1

1

2

2

@ R772
100K_0402_5%

Int. Speaker Conn.

U42 @

2

1

1

+5VAMP
R771
100K_0402_5%

E

1

10 dB
@

D

+5VAMP

Modify 03
Link CIS symbol C844

Ri
90k
70k
45k
25k

@ C844
10U_0603_6.3V6M

GAIN0 GAIN1 AV(inv)
0
0
6dB
0
1
10dB
1
0
15.6dB
1
1
21.6dB

Audio AMP

C

3

B

@ C845
0.1U_0402_16V4Z

A

@
C846
0.47U_0603_10V7K

JM

Int. Speaker Conn.
30mils

JHP1
42 HP_RIGHT

R735 1

42 HP_LEFT

R734 1

HPOUT_R_1

2 39_0402_5%

HPOUT_L_1

2 39_0402_5%

HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P

1
L45
1
L46

R665
R667
R669
R670

1
1
1
1

JM@ D25
PJDLC05C_SOT23-3

1

JSPK1

SPK_L+
SPK_LSPK_R+
SPK_R-

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

2
2
2
2

2

2

6
4

SPKL+_L
SPKL-_L
SPKR+_L
SPKR-_L

SPKL+_L
SPKL-_L
SPKR+_L
SPKR-_L

1
2
3
4

3

42
42
42
42

2

Headphone Out/SPDIF

3

Modify R02
Exchange HP right and left channel.

JM@ D26
PJDLC05C_SOT23-3

1
2
3
4

5
6

G1
G2

2

ACES_88266-04001
CONN@

5

C810
330P_0402_50V7K

2

2

3

2

HPOUT_R_2
1

D20
PJDLC05C_SOT23-3

C811
330P_0402_50V7K

1

Modify R02
Exchange SPDIF_OUT
and +5VSPDIF, Pin8 is
signal pin and Pin3 is
power pin.

Place D25.D26 near

JSPK1

2
SINGA_2SJ1558-011111
CONN@

Modify R02

10/04 Update CIS symbol.
1

42 DMIC_CLK
MIC_PLUG#
42 DMIC_DATA

Digital MIC CONN

L50
FBMA-L10-160808-301LMT_2P
DMIC_CLK 1
2 DMIC_CLK_R
L51
FBMA-L10-160808-301LMT_2P
DMIC_DATA 1
2 DMIC_DATA_R

+3VS

3

2

2

SPDIF_PLUG#

MIC1_VREFO

Close to IC

1

7
3
8

42 SPDIF_OUT

HPOUT_R_2

1

SPDIF_PLUG#

HPOUT_L_2

@
D39
PJDLC05C_SOT23-3

L36
MBK1608121YZF_0603
+3VS_DMIC
1
2
JDMIC1

3

+5VSPDIF
HPOUT_L_2

+3VS_DMIC
DMIC_CLK_R
DMIC_DATA_R

@ D24
PJDLC05C_SOT23-3

Modify 03
Link CIS symbol D24

1
2
3
4

1
2
3
4

G1
G2

5
6

ACES_88266-04001
CONN@



100P_0402_50V8J 1

1
R737
3K_0402_5%

@
2 C720

DMIC_CLK_R

2

MIC1_L

R663 1

2 100_0402_1%

MIC1_L_R

42

MIC1_R

R664 1

2 100_0402_1%

MIC1_R_R

MIC1_L_L
L47 1
2
FBMA-L11-160808-700LMT_2P
MIC1_R_L
L48 1
2
FBMA-L11-160808-700LMT_2P

+5VAMP

3
+5VAMP

5

R789
100K_0402_5%

2

2

4

6 1

1

3

S

10/04 Check footprint ok
Footprint:SINGA_2SJ-0960-D06_6P

C813

G

2

SPDIF_PLUG#

D36
PJDLC05C_SOT23-3

Q66A
DMN66D0LDW-7_SOT363-6

2

D

220P_0402_50V7K

5

4

1

1

Q67
AO3413L_SOT23-3

HP_PLUG# 42

Q66B
DMN66D0LDW-7_SOT363-6

+5VSPDIF

1

220P_0402_50V7K

1

SINGA_2SJ-A960-C01
CONN@

1

C812

R790
100K_0402_5%

6

3

2
4

HP_PLUG#

2

MIC_PLUG#

2

42 MIC_PLUG#

MIC1_R_L

DMIC_CLK

1
2

4

MIC1_L_L

R671
@
1
10K_0402_5%


JMIC1

42

MIC1_R_L

2

1000P_0402_50V7K

12/7 Add C1107=@100pF(Avoid noise)

MIC JACK

C719 @
2
1



3

1
2

R736
3K_0402_5%

MIC1_L_L

10/04 Check footprint ok

1

D22
RB751V-40_SOD323-2
1

D21
RB751V-40_SOD323-2

1

1

2

3

2

3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

2010/08/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Amplifier & Audio Jack
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

43

of

59

1

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

1
2

1
2

1

Exchange port2 and port1 for vendor's suggestion,
port2 may affect test issue.
Modify 03

+3V_USB3

A8

2

+3V_USB3
R711 1
R712 1

C

R840
10K_0402_5%

2 10K_0402_5%
2 10K_0402_5%

1

G14
H13 OCI1B

2

P8
B8

PONRSTB

PPON2
PPON1

PCI Express/ExpressCard select signal
1:others
0:Express Card or Mini card

SPISCK
SPISCB
SPISI
SPISO

U3TXDN1
U2DM1
U2DP1
U3RXDP1

GND
GND
GND

N14
M14

OCI1B 45

H14
J14

B10

U3TX_C_DP11

P10
B12

U2DP1_L
U3RXDP1_L

A12

U3RXDN1_L

P12
N12

2

SMI#

3

1

SMIB 18

2N7002H_SOT23-3
Q73

C786.1U_0402_16V7K
2 U3TXDP1_L

A10 U3TX_C_DN11
N10 U2DN1_L

2

2

2

U2AVDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10
VDD10

VDD33
VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

U3AVDO33

U2DP2
U3RXDP2

OCI2B
OCI1B

1

P13

D7

H11
K11
K12
L8

H3
H4
L5

E11
E12

E3
E4

C8
C9
D8
D9

C4
C5
C6
C7
D5

N4
N5
N6
P3

L13
L14

L9
L10

F3
G3
G4

D10
F13
F14

2

1
2

1

1
2

2

2

1

1

1

GND

1
2

1
2

2
G
D

S

A6
N8

U3TXDP1_L 45

2 U3TXDN1_L
C785 .1U_0402_16V7K

U3TXDN1_L 45
U2DN1_L 45
U2DP1_L 45

U3RXDP1_L 45
U3RXDN1_L 45

R718

As short as possible

RREF
GND

GND
GND

USB3_XT1
USB3_XT2

0.01U_0402_16V7K

C14

Modify R02

0.01U_0402_16V7K

Q63
2N7002H_SOT23-3

C772

AUXDET
PSEL
SMI
SMIB

D

S

14 USB30_CLKREQ#

M2
N2
N1
M1

K13
K14
J13

CLKREQ_USB3

1

.1U_0402_16V7K

B6

Can be attach to EC, either.

Modify R03

Modify R02
solve 3vs leakage

U3TXDP2

U3RXDN1

G
3

C783
10U_0603_6.3V6M

U3TXDN2
U2DM2

U3TXDP1
C788
1U_0603_10V6K

R717
10K_0402_5%

P5
SPI_CLK_USB
SPI_CS_USB#
USB_SO_SPI_SI
USB_SI_SPI_SO

C771

J2
J1
H1
SMIB_R P4

2 10K_0402_5%

1
2
D32 1 2
1SS355TE-17_SOD323-2
+3V_USB3

0.01U_0402_16V7K

R715 1

+3V_USB3

2 0_0402_5%

C777

R798 1

C770

+3V_USB3 L40
+3VA_USB3
BLM18AG601SN1D_2P
1
2

D

SMI#

0.01U_0402_16V7K

+3VA_USB3

S

+3V_USB3

.1U_0402_16V7K

PERSTB
PEWAKEB
PECREQB

C769

H2
K1
K2

D

G

R713 1
@ R709 1
R714 1

+3V_USB3

+3VS

2 0_0402_5%
2 0_0402_5%
CLKREQ_USB3
2 10K_0402_1%
2 100_0402_1%
2 10K_0402_5%

C768

R708 1
R710 1

0.01U_0402_16V7K

USB3_PEWAKEB

0.01U_0402_16V7K

5,17,35,38,39 PLT_RST#

C767

+1.05VR

U3RXDN2
C

.1U_0402_16V7K

PERXP
PERXN

C762

F2
F1

C766

PETXP
PETXN

.1U_0402_16V7K

D2
D1

0.01U_0402_16V7K

14 PCIE_PTX_C_DRX_P4
14 PCIE_PTX_C_DRX_N4

PECLKP
PECLKN

C765

2 .1U_0402_16V7K PCIE_PRX_C_DTX_P4
2 .1U_0402_16V7K PCIE_PRX_C_DTX_N4

C787 1
C784 1

14 PCIE_PRX_DTX_P4
14 PCIE_PRX_DTX_N4

B2
B1

0.01U_0402_16V7K

14 CLK_PCIE_USB30
14 CLK_PCIE_USB30#

@

7K for customer request, can use other kind
of capacitor, like Y5V.

R707
0_0805_5%
1
2

U35
USB3_PEWAKEB
3
Q71
2N7002H_SOT23-3

1

+1.05V_USB3

C764

+3V_USB3

@

0.01U_0402_16V7K

Modify R02 add MOS to gate leakage from
PCH_PCIE_WAKE# at S4/S5. +3V_USB3

15,35,37 PCH_PCIE_WAKE#

GND
RT9701-PB_SOT23-5

0.01U_0402_16V7K

R706
32.4K_0402_1%

+3VA_USB3

0.01U_0402_16V7K

APL5930KAI-TRG_SO8
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025

+3VA_USB3
1
5

+1.05VR
C776

2
1 R705
2
10K_0402_1%

VIN
VOUT
VIN/CE VOUT

C763
8P_0402_50V8D

2

3
4

C761
0.01U_0402_16V7K

FB

SYSON

39,46,51 SYSON

C779
.1U_0402_16V7K

EN
POK

3
4

C778
8P_0402_50V8D

SYSON
8
2
1
7
R704 5.1K_0402_1%

VOUT
VOUT

C760
0.01U_0402_16V7K

+5VALW

VCNTL
VIN
VIN

Close to U35.P13

C774
.1U_0402_16V7K

6
5
9

Close to U35.D7
+3V_USB3

U34

C773

U33

+1.5V

+3VALW

C759

+1.05V_USB3

C775

+5VALW

C782
10U_0603_6.3V6M

C758
10U_0603_6.3V6M

C757
1U_0603_10V6K

D

+1.5V

1

+3V_USB3

+3VALW to +3V Transfer

+1.5V to +1.05V Transfer
+5VALW

2

2

3

2

4

2

5

GND

N11

1
1.6K_0402_1%

D6

XT1
XT2

B

B

P6

1

1

2

2

24MHZ_12PF_X5H024000DC1H
C792
15P_0402_50V8J

Place as close as
possibile to
U3.N14 and U3.M14

+3V_USB3

C793
15P_0402_50V8J

U38

8
7
SPI_CLK_USB
6
USB_SO_SPI_SI 5

VCC
NC
SCLK
SI

2

Pop R720 for EON issue

R719
10K_0402_5%
1

1

C790
.1U_0402_16V7K

2

2

2

+3V_USB3

CS#
SO
WP#
GND

1
2
3
4

R720
47K_0402_5%
1

+3V_USB3

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

SPI_CS_USB#
USB_SI_SPI_SO

MX25L5121EMC-20G_SO8

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Modify R02

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1

2
1

2
1

1
2
2

+3V_USB3
A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

R721
10K_0402_5%

Y5
1

0_0402_5%

0_0402_5%

R727
100_0402_5%

R725

R723

@
USB3_XT1
USB3_XT2

CSEL

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

A

Pin compare table for support USB remote wakeup or not

Support USB
remote
wakeup
Not support USB
remote wakeup

AUXDET(Pin J2)

CSEL(Pin P6)

CLK

pull high
10k to VDD33

Tied to GND

Must use 24MHz crystal: mount
Y1,R19,C40,C41

Tied to GND
5

pull high
to VDD33

P/N: SA000048H00

UPD720200AF1-DAP-A_FBGA176

Compal Secret Data

Security Classification
Issued Date

A

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Can use either 48MHz or 24MHz When
use 48MHz clock: mount R22,R25
4

3

2

Title

USB3.0 PD720200A
Size Document Number
Custom LA-7221P
Date:

Rev
0.2

Wednesday, February 16, 2011

Sheet
1

44

of

59

U2DN1_L
U2DP1_L
R842 1
R843 1

VL

@

2

2

2 0_0402_5%
C789
0.1U_0402_16V4Z

8
7
6
5

1

CB
TDM
TDP
VCC

1
2
3
4
9

CEN
DM
DP
GND
GND

SW_U2DN1_L
SW_U2DP1_L

Oper Drain, Low Active, need PU

Auto detection charger identification active

CB=1

Connect DP/DM to TDP/TDM

4

U2DP1

2

1

1

U2DN1

+
2

WCM2012F2S-900T04_0805
D31
U2DN1

MAX14566EETA+_TDFN-EP8_2X2

6
5

+USB3_VCCA

2

4

CB=0

4

I/O4

I/O1

REF2 REF1
I/O3

I/O2

Modify R03

Modify R02

U2DP1

1

2

SW_U2DN1_L

3

1

3

U36

2 0_0402_5%

Modify R02

L39
SW_U2DP1_L

C781
10U_0603_6.3V6M

39 USB_CHARGE_CB
44 U2DN1_L
44 U2DP1_L
+USB3_VCCA

R726
10K_0402_5%
1

C780
150U_B2_6.3VM_R35M

USB Host Charger

1

+USB3_VCCA

USB3.0 Connector

2
3

PJUSB208H_SOT23-6

+USB3_VCCA

L37
44 U3TXDP1_L
+USB3_VCCA

44 U3TXDN1_L

+5VALW

U3TXDP1_L 2

1 U3TXDP1

U3TXDN1_L 3

JUSB2

4 U3TXDN1

U3RXDN1
U3RXDP1

OCE2012120YZF_4P

R722 1
10K_0402_5%

1
2
3
4

2

GND
VIN
VIN
EN

9

39 USB_CHARGE_2A#

W=60mils

U37

EPAD

C791
.1U_0402_16V7K
1
2

Modify R02
Delete D46.R831

VOUT
VOUT
VOUT
FLG

8
7
6
5

R724
10K_0402_5%
1
2 OCI1B

L38
44 U3RXDP1_L

U3RXDP1_L 2

44 U3RXDN1_L

U3RXDN1_L 3

OCI1B 44

R754 1
@
10K_0402_5%

39 USB_CHARGE_100mA

5
2

4

VOUT

1

GND

2

OC

3

VIN
ON

U3TXDN1
U3TXDP1

4 U3RXDN1

For customer request
GND
GND
GND
GND

GND_Frame 1
2
R728 0_0603_5%
1
2
R729 0_0603_5%
1
2
C794
.1U_0402_16V7K

10
11
12
13

OCTEK_USB-09EAEB
CONN@

OCE2012120YZF_4P

@ U41

VL

@ C204
1U_0603_10V4Z
2
1

1 U3RXDP1

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

AP2301MPG-13_MSOP8

+USB3_VCCA

Modify R02

1
2
3
4
5
6
7
8
9

U2DN1
U2DP1

10/05 Update symbol .

U3RXDN1

D30
1 1

10 9

U3RXDN1

U3RXDP1

2 2

9 8

U3RXDP1

U3TXDN1

4 4

7 7

U3TXDN1

U3TXDP1

5 5

6 6

U3TXDP1

3 3
8

Oper Drain, Low Active

TPS22945DCKR_SC70-5

YSCLAMP0524P_SLP2510P8-10-9

100mA MAX
10/13 Link CIS symbol OK!

Modify R02

FAN1 Conn

H2
H_3P0

H3
H_4P0

H4
H_3P3

H5
H_3P0

H6
H_3P0

H7
H_3P0

H8
H_3P0x5P0

H9
H_3P0

H10
H_3P0

H11
H_3P0

H13
H_3P0
@

1

@

1

@

1

@

1

@

1

@

1

@

1

@

1

@

1

@

1

1

1

+5VS
@

H18
H_4P0

1

C724
1000P_0402_50V7K
1
2

+3VS
1

JM

1

1

@

@

@

H19
H_4P0
@

@

JFAN1
GND2
GND1

H20
H_3P0

4
3
2
1

H21
H_3P5x4p5N
@

H22
H_3P5N

@

1

39 FAN_PWM
C725
1000P_0402_50V7K

4
3
2
1

@

+VCC_FAN1
FAN_SPEED1
FAN_PWM

GND2
GND1

4
3
2
1

4
3
2
1

SJM

ACES_88231-04001
CONN@

1012 footprint check Ok

FD1

FD2
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD4
@

FIDUCIAL_C40M80

2008/08/10

Deciphered Date

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD3
@

1

JFAN2
6
5

1

2

ACES_88231-04001
CONN@

1

39 FAN_SPEED1

+VCC_FAN1
FAN_SPEED1
FAN_PWM

1

6
5

40mil

1

R673
10K_0402_5%
2

@

H23
H_4P0

H17
H_4P2

Modify R02
Delete H25

1

Modify R03

1

@

H16
H_4P2

C723
10U_0603_6.3V6M
1
2

C721
10U_0603_6.3V6M

1

1

1

H15
H_4P2

1

+VCC_FAN1
1
0_0603_5%

2

2
R672

H14
H_4P2

@ D28
BAS16_SOT23-3
2

1

+5VS

1

2

@ D27
1SS355_SOD323-2

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

FAN & Screw Hole
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet

45

of

59

A

B

C

2
1

Q44A
DMN66D0LDW-7_SOT363-6

R681
100K_0402_5%

C736
0.1U_0603_25V7K
SUSP

SUSP

3

4

5,53

1

2

5

Q44B
DMN66D0LDW-7_SOT363-6

1
6

1

3
PCH_PWR_EN#

+5VALW

PCH_PWR_EN#

2

4

Q43B
DMN66D0LDW-7_SOT363-6

R678
100K_0402_5%

2

10mil
1 200K_0402_5% 3V_GATE

R680 2

DMN66D0LDW-7_SOT363-6

2

2

2

+VSB

1

2

1

2
1

4

1
2

20mil

5

R677
470_0603_5%

1

1

Q43A
DMN66D0LDW-7_SOT363-6

SYSON

39,44,51 SYSON

6 1

2
1
6

1

1
2
1

1

1
2

4
3

C735
0.1U_0603_25V7K

Q45A

1
2
3

C734
1U_0603_10V4Z

C732
SUSP

2

Modify R02
SUSP

8
7
6
5

SYSON#

37 SYSON#

40mil

C733
10U_0603_6.3V6M

C731
1U_0603_10V4Z

2

JUMP_43X79
Q42
SI4178DY-T1-GE3_SO8

R676
470_0603_5%

5VS_GATE

+3VALW_PCH

2

2

10U_0603_6.3V6M

10mil

2
1
R679
100K_0402_5%

+VSB

C730
10U_0603_6.3V6M

20mil

C729
10U_0603_6.3V6M

C728
10U_0603_6.3V6M

1

R675
100K_0402_5%

@

1

1

J1
1

2

+3VALW

+5VS

1
2
3

+5VALW

Short J5 for PCH VCCSUS3.3

2

Q41
SI4178DY-T1-GE3_SO8
8
7
6
5

E

+3VALW TO +3VALW(PCH AUX Power)

+5VALW TO +5VS
+5VALW

D

2
2

2
1
2
+3VS
14,17,25,55 VGA_ON

1 1

1 1
2 SUSP
G
Q61
2N7002H_SOT23-3

S

2 SYSON#
G
Q62 @
2N7002H_SOT23-3

1
S

OPT@
Q58
2N7002H_SOT23-3
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge
A

R703
OPT@
100K_0402_5%

D

3

S

3

2 SUSP
G
Q60
2N7002H_SOT23-3

D

2
G

2

1 1

S

3

2 SUSP
G
Q59
2N7002H_SOT23-3

Modify R04

1

@
Q57
2N7002H_SOT23-3

1

S

2
G

@ R702
470_0603_5%

D

1
1
2

2
1

VGA_ON#
OPT@ R849
10K_0402_5%
2
1

OPT@
R698
100K_0402_5%

3

2

1

1

1

C756
OPT@
0.1U_0603_25V7K

2 VGA_ON#
Q55A
OPT@
DMN66D0LDW-7_SOT363-6

2
1

4

D

3

2

2

1

+5VALW

5

OPT@ Q55B
DMN66D0LDW-7_SOT363-6
ACIN

R693
470_0603_5%
OPT@

1.5VSDGPU_GATE

@

+1.5V

OPT@

6

4

10mil
2
1
R696
510K_0402_5%
OPT@

3

+VSB

OPT@

2

1

1
2
3

2

1

OPT@
C755
10U_0603_6.3V6M

8
7
6
5

2

1

SUSP

1

2

3

2
1
3

S

D

3

1

1
1
2

2
1
3

4

2
1
6

1
2

1
2
1

2

VGA_ON#

D

Q50
2N7002H_SOT23-3

+1.5VSDGPU

20mil

R701
470_0603_5%

S

U32 OPT@
AO4430L_SO8

@
Q56
2N7002H_SOT23-3

R700
470_0603_5%

D

2
G

R689
100K_0402_5%

+1.5V

2

C753
0.1U_0603_25V7K

+1.8VS

39 PCH_PWR_EN

@
Q51
2N7002H_SOT23-3

2
1

S

2
G

+1.05VS_VCCP

4

S

PCH_PWR_EN#

+1.5V to +1.5VSDGPU for GPU

+0.75VS

R699
22_0603_5%

D

2
G

R697
510K_0402_5%

D

3

4

1
2

1
2

1
2

2

4
1
3
5

ACIN

15,39,48 ACIN

R694
510K_0402_5%

SUSP

Q53B
DMN66D0LDW-7_SOT363-6

@

20,35 PCH_PWR_EN#

C745
OPT@
0.1U_0603_25V7K

C752
1U_0603_10V4Z

Modify R02

VGA_ON#

OPT@ Q49A
DMN66D0LDW-7_SOT363-6

R690
470_0603_5%

Q53A
DMN66D0LDW-7_SOT363-6

1.5VS_GATE

1

3

4

10mil

@

R686
100K_0402_5%

2

C754
10U_0603_6.3V6M

2
1
R692
750K_0402_5%

C747
1U_0603_10V4Z

+VSB

1
2
3

ACIN

C746
10U_0603_6.3V6M

20mil

+1.5VS

Q52
SI4178DY-T1-GE3_SO8
8
7
6
5

C751
0.1U_0402_16V4Z

C750
0.1U_0402_16V4Z

C749
10U_0603_6.3V6M

C748
10U_0603_6.3V6M

1

+1.5V

5

OPT@ Q49B
DMN66D0LDW-7_SOT363-6

+1.5V to +1.5VS

1211 EMI ADD 0.1U close PJ5

3

10mil
1.05VSDGPU_GATE
R688
510K_0402_5%

VGA_ON#

4

1

20mil
+VSB

+5VALW

R684
470_0603_5%
OPT@
6 1

2
4

OPT@ R687
510K_0402_5%
2
1

OPT@

2

1
2

2

1

1

SUSP

5

Q48B
DMN66D0LDW-7_SOT363-6

2

OPT@

Q48A
DMN66D0LDW-7_SOT363-6

2

3

2
C744
0.1U_0603_25V7K

R682
10K_0402_5%

4A

1
2
3

1

2
6 1

1

1
2

4

1
2

SUSP

Q45B
DMN66D0LDW-7_SOT363-6

5

37,39,52,53 SUSP#

+1.05VSDGPU

C743
1U_0603_10V4Z

10mil

8
7
6
5

OPT@
C741
10U_0603_6.3V6M

3VS_GATE

Modify R02

+1.05VS_VCCP
Q47 OPT@
SI4178DY-T1-GE3_SO8

R683
470_0603_5%

C742
10U_0603_6.3V6M

+VSB

+1.05VS_VCCP to +1.05VSDGPU for GPU
C740
1U_0603_10V4Z

R685
200K_0402_5%
2
1

20mil

+3VS

1
2
3

C739
10U_0603_6.3V6M

2

Q46
SI4178DY-T1-GE3_SO8

8
7
6
5

C738
10U_0603_6.3V6M

2

C737
10U_0603_6.3V6M

1

+3VALW

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

DC Interface
Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
E

46

of

59

5

4

PL1
SMB3025500YA_2P
1

ACES_50305-00441-001
1
2
3
4
5
6

2

VIN

1

PJ1 @

2

2

+3VALWP

2

PJ2
1

1

+3VALW

+0.75VSP

3

1

1

+0.75VS

JUMP_43X118

PJ3
2

+5VALWP
2

2

@

PC4
1000P_0402_50V7K

D

PJ4

2

@

PJ25
@ JUMP_43X39
1 1
2 2

1

1

+5VALW

+VCCSAP

JUMP_43X118

2

2

@

+VCCSA

1

1

D

JUMP_43X118

1

PD9 @
PJSOT24CH_SOT23-3

2

1

PC3
100P_0402_50V8J

2

1
PC2
100P_0402_50V8J

2

PC1
1000P_0402_50V7K

2

2

PJP1

1

JUMP_43X118
1

1
2
3
4
GND
GND

3

VIN

PJ5

2

+1.8VSP

2

PJ26
@ JUMP_43X39
1 1
2 2

51ON#

1
2

2

PC6 @
0.1U_0603_25V7K

+1.5V

2

1

1

+VSBP

+1.05VS_VCCPP

2

1

C

1
PJ12@

JUMP_43X118
PJ13
2 2
1 1

2
+1.05VS_VCCP

+GFX_COREP

JUMP_43X118

2

Reserved for usb charge (1/7)

2

1

1

JUMP_43X118
PJ14@
2
1 1

+VGFX_CORE

JUMP_43X118

B

1

PR8
1

PR10
1K_1206_5%
1
2

PR9

PR7
1K_1206_5%
1
2

2

2

LL4148_LL34-2
PD3
1
100K_0402_5%

PR6
1K_1206_5%
1
2

100K_0402_5%

Pre_chg
VIN

PQ2
TP0610K-T1-E3_SOT23-3
3

B

1

PR13
1K_1206_5%
1
2

12

PR14
100K_0402_5%
1

2

0_0402_5%
PR15
1

B+

1

2

+3VLP

2

PR5
0_0402_5%
1
2

ACOFF

+VSB

JUMP_43X118

@

@

39

PJ10
@ JUMP_43X39
1 1
2 2

PJ11
2

2

@

+CHGRTC

JUMP_43X118

1

1

JUMP_43X118

2
@

2

1
40

@ PR4
22K_0402_5%
1
2

+VGA_CORE

1

2

@ PR3
100K_0402_5%

C

3

1

PC5
0.22U_0603_25V7K
2
1

N1

+1.5VP

1

1

JUMP_43X118
PJ7
2 2
1 1

PJ9

VS

2

@

@

2

@
PR2
@ 68_1206_5%

2

+VGA_COREP

PJ8

@ PR1
68_1206_5%
@ PQ1
TP0610K-T1-E3_SOT23-3

PJ6
+1.8VS

1

1

JUMP_43X118

2
1

PD2
LL4148_LL34-2
2
1

BATT+

@

1

@ PD1
LL4148_LL34-2

2

PQ4
PDTC115EU_SOT323-3

PD20
2
1

+5VALW

2

2

3
PQ3
PDTC115EU_SOT323-3

3

3

BAS40CW_SOT323-3

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR DCIN / Pre-charge

Size Document Number
Custom

Rev
0.1

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

47

of

59

A

B

C

D

S

SI1304BDL-T1-E3_SC70-3

EMI request for ISN issue (1/7)

DH_CHG 1

2
2.2_0603_5%

ACDRV

5

ACOK

12

SRN 1

BATDRV

11

1

1

PC26
0.01U_0402_50V7K

2

1

PC24
2200P_0402_50V7K

2

1
2

PC22
10U_0805_25V6K

PC21
10U_0805_25V6K

PC25
0.1U_0402_25V6
2
1

CSON1

1

1
2

2

CSOP1

PC23
0.1U_0402_25V6

1
2
1

ILIM

SCL

1

PC29
0.01U_0402_25V7K

2

2

1

2

2

316K_0402_1%

Close to EC pin (PC121, PR70)
1

EC_SMB_CK1 39,50

PR70

EC_SMB_DA1 39,50
PC31

2

1

1

1

@
PC121
100P_0402_50V8J

2

ILIM and external DPM
3.97A

2

Max.
PC30
0.1U_0402_25V6

Typ
17.23V
17.63V

2

Min.
H-->L
L--> H

PR36
66.5K_0402_1%

1

Vin Dectector

PR35
154K_0402_1%

2

PR34
100K_0402_1%

PR33

255K_0402_1%

0.01U to avoid IC be latch

PR32
PD7
RB751V-40_SOD323-2

VIN

1

@

3

1

10K_0402_1%

3

+3VALW

10

2

9

SDA

IOUT

8

PR31

1

15,39,46 ACIN

6

Pre_chg

7

2

10K_0402_1%

3

ACDET

PR30

1

2CSON1
PR67
6.8_0603_5%
BQ24725_BATDRV
Change

PR29
4.7_1206_5%

5

SRP
SRN

PR66
10_0603_5%
2CSOP1

2

4

SRP 1

2

@

PC27
680P_0402_50V7K

CMSRC

BQ24725_ACDRV

13

PQ10
SIS412DN-T1-GE3_POWERPAK8-5

3

PC28
0.1U_0603_16V7K
3
2
1

14

4

1

GND

DL_CHG

2

15

BATT+

PR28
0.01_1206_1%
1
4

10U_LF919AS-100M-P3_4.5A_20%
PL2
BQ24725_LX
1
2 CHG

3
2
1

2
16
LODRV

2

EMI request for ISN issue (1/17)

PC19
1
2

BQ24725RGRR_VQFN20_3P5X3P5
BQ24725_CMSRC

PR20
0_0402_5%

PQ9
SIS412DN-T1-GE3_POW ERPAK8-5

4

PD6
RB751V-40_SOD323-2

REGN

18

19

17
BTST

ACP

HIDRV

2

PHASE

ACN

VCC

PAD

1

2

5

PR25
10_0603_5%

1
DH_CHG

BQ24725_LX

PR197

BQ24725_BST 2

1
20

2
1
2

21

2

EMI request for ISN issue (1/7)

1U_0603_25V6K
PU1

@

PR21
4.12K_0603_1%

2

PR24
10_1206_1%

1

1

2

1U_0603_25V6K

PR27
@ 3.3_1210_5%

+3VALW

1
2
BQ24725_BATDRV 1

PC16

PC18
1
2

PC20
@ 2.2U_0805_25V6K

4

2

1
2

BQ24725_ACP

1

1 2

2

PR26
@ 3.3_1210_5%

PC17
0.1U_0603_25V7K

1

PR23
4.12K_0603_1%

2

1

PR22
4.12K_0603_1%

2

2

@

0.047U_0402_25V7K

PD5
BAS40CW_SOT323-3
BQ24725_ACN

1

VIN

1
2
3
PC14
0.01U_0402_50V7K

2
2

3

1

AO4466L_SO8
PQ8

8
7
6
5

PC13
2200P_0402_50V7K

1

1

JUMP_43X118

CHG_B+

PC12
0.1U_0402_25V6
2
1

2

3

PC10
10U_0805_25V6K
2
1

2
@

2

PC9
0.1U_0402_25V6

VIN

1

PJ15

B+

0.02_2512_1%
PR18
4

1

8
7
6
5

1UH_FDV0630-1R0M-P3_10.3A_20%
PL16
1
2

4

1
2

1
2
3

PC7
0.1U_0402_25V6

1
4

PR19
0_0402_5%

@

2

1
2

1
2
3

PC8
2200P_0402_50V7K

8
7
6
5

AO4466L_SO8
PQ7

1

PC11
10U_0805_25V6K
2
1

P2

AO4466L_SO8
PQ6

PC51
10U_0805_25V6K
2
1

P1

2

1

VIN

PC119
10U_0805_25V6K

1

PC109
10U_0805_25V6K

3M_0402_5%

PC15
0.1U_0402_25V6

1M_0402_5%

2

2

1

1

2

PC80
10U_0805_25V6K

PR17

1
1

D

2

PR16

1

PQ5
2
G

3

for reverse input protection

2

4

1

1

100P_0402_50V8J

Compal Secret Data
2010/01/25

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

4

ADP_I 39,50

Add reserved resistor0_0402_5%
for charger control (1/24)

Security Classification
Issued Date

2

C

Title

Compal Electronics, Inc.
PWR DCIN / Pre-charge

Size Document Number
Custom

Rev
0.1

LA-7221P

Date:

Sheet

W ednesday, February 16, 2011
D

48

of

59

5

4

3

2

1

PC32
1U_0603_10V6K

2VREF_8205

LX_5V

LGATE2

LGATE1

19

LG_5V

1

1
2
3
2
1

PC48
1U_0603_10V6K
2
1

1

PQ15B
DMN66D0LDW -7_SOT363-6

2VREF_8205

Change to 150K to avoid battery
shutdown when low voltage (1/7)

PC49
4.7U_0805_10V6K

1
2

2

1

S

5
G

RT8205_B+

2
PC50
0.1U_0603_25V7K

3
4

2

D

VL

Typ: 175mA

+5VALWP

PR46
4.7_1206_5%

5
4

1
+

PC46

1

NC

RT8205EGQW _W QFN24_4X4

18

VIN

VREG5
17

16

FDSD0630-H-4R7M=P3 5.5A_20%
PL5
1
2

PQ14
SI7716ADN-T1-GE3_POW ERPAK8-5

1

PR50
0_0402_5%
2
1

150U_D2E_6.3VM_R18

2

B

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

PQ16
PDTC115EU_SOT323-3

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=8.44~11.57A (8.44>8.4 -> OK)

A

3

1
2

PC114
4.7U_0603_6.3V6K

2

+3.3VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A
f=375KHz, L=4.7UH
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A
Vlimit=10*10^-6*110Kohm/10=0.11V
Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A
Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT-

Compal Secret Data

Security Classification
2010/07/13

Issued Date

Deciphered Date

2011/07/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

5

PC40
0.1U_0603_25V7K
2
1

PC39
2200P_0402_50V7K
2
1

PC38
4.7U_0805_25V6-K
2
1

PC37
4.7U_0805_25V6-K
2
1

ENTRIP1

1

3

4

2
FB1

REF

FB2

UG_5V

20

PR51
100K_0402_1%
2
1

VL

2
1
PR54
402K_0402_1%

VS

21

PHASE1

2

2

ENTRIP2

6

G

PD4
1M_0402_1%
LL4148_LL34-2
PR53 2
2
1 1
PR52
316K_0402_1%
2
1

UGATE1

PHASE2

PR48
499K_0402_1%
1
2

RLZ5.1B_LL34

S

VIN

UGATE2

PC47
680P_0402_50V7K

1

ENTRIP1

A

PR44
PC43
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

VFB=2.0V

C

SPOK 50

B+

D

40,50 MAINPWON

22

13

PD8

B

PQ15A
DMN66D0LDW -7_SOT363-6

12

23

BOOT1

PR47 @
0_0402_5%
2
1

3V5V EN

PR49
150K_0402_1%

2

LG_3V

PGOOD

BOOT2

4

+

1
2
3

330U_D2E_6.3VM_R25M

40

PC45
680P_0402_50V7K
2
1

PC44

SI7716ADN-T1-GE3_POW ERPAK8-5
PQ13

VREG3

EN

1
2
3
1

5

PR45
4.7_1206_5%
2
1

+3VALWP

24

GND

8
PR43
2 1
2 BST_3V 9
2.2_0603_5%
PC42
UG_3V
10
0.1U_0603_25V7K
LX_3V
11

SIS412DN-T1-GE3_POW ERPAK8-5
1

PQ12
SIS412DN-T1-GE3_POW ERPAK8-5

4
VO1

VO2

SKIPSEL

7

PR42
154K_0402_1%
2

3
2
1

4

RT8205_B+

ENTRIP1

P PAD

15

25

TONSEL

6
ENTRIP2

PU2

1

5

+3VLP
PR41
110K_0402_1%
1
2

FDSD0630-H-4R7M=P3 5.5A_20%
PL4
1
2

1

PR40
20K_0402_1%
1
2

ENTRIP2

PR39
20K_0402_1%
1
2

1

PQ11

PR38
30K_0402_1%
1
2

2

PC41
4.7U_0805_10V6K

5

PC36
2200P_0402_50V7K
2
1

PC35
4.7U_0805_25V6-K
2
1

Typ: 175mA
PC34
4.7U_0805_25V6-K
2
1

C

PC33
0.1U_0603_25V7K
2
1

B+

PL3
HCB4532KF-800T90_1812
1
2

PR37
13K_0402_1%
1
2

14

RT8205_B+

D

2

D

4

3

2

Title

Compal Electronics, Inc.
3VALWP/5VALWP

Size
Document Number
Custom

Rev
0.1

LA-7221P

Date:

W ednesday, February 16, 2011

Sheet
1

49

of

59

5

@ ACES_50299-01001-001
10 10
9 9
8 8
7 7
6 6
5 5
4
4
3 3
2 2
1 1

3

2

1

D

Combine protection circuit(1/7)

2

EC_SMDA
EC_SMCA
TH
BI+

PJP2

EC_SMB_DA1 39,48

+3VLP

1

1

<40,41>
VMB

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C

1

PR56
100_0402_1%

Reference only

PR55
100_0402_1%

2

D

4

PC52
0.1U_0603_25V7K

PR59
21K_0402_1%

1

40,49 MAINPWON
D

PQ22
2N7002W-T/R7_SOT323-3

C

2
G

8

GND RHYST1

7

3

~OT1TMSNS2

6

4

~OT2 RHYST2

5

PR63 1
2
9.53K_0402_1%

1

G718TM1U_SOT23-8

3

S

1

37,39,40

PH1
100K_0402_1%_NCP15WF104F03RC

+VSBP

PR78
10K_0402_1%

2

1

For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W

PC56
0.1U_0603_25V7K

B

2

@ PC57
0.1U_0603_25V7K

1

1

PQ20
2N7002W-T/R7_SOT323-3

2

@ PR58
10K_0402_1%

@ PR80
100K_0402_1%

PU4
1

VCC TMSNS1
GND RHYST1

8
7

2

1

2

40,49 MAINPWON

2

@ PR73
10K_0402_1%

VL

3
4

OT1 TMSNS2
OT2 RHYST2

1

@ PR64
47K_0402_1%

6

1

3

S

1

1

D

2
G

2

2

1

PR71
1K_0402_5%
2

PC58
1U_0402_6.3V6K

1

SPOK

C

+3VLP

1
49

65W@ PR77
28.7K_0402_1%

Reference only

1

PR69
100K_0402_1%

B

2

2

1
2

3

2

VL

PC55
0.22U_0603_25V7K

PR68
22K_0402_1%
1
2

2

B+

1
PR65
100K_0402_1%

PQ19
TP0610K-T1-E3_SOT23-3

90W@ PR74
8.87K_0402_1%

90W@ PR77
16.2K_0402_1%

BATT_TEMP 39

BI

2

VCC TMSNS1

2

2

2

Reserved for TI demand (1/17)

1

1

2

1

5,39 H_PROCHOT#

PU3

@ PR61
100K_0402_1%

2

PR76
100K_0402_1%

2

1

+3VALW

PR62
1K_0402_1%

65W@ PR74
5.62K_0402_1%
1

1
1

1

+3VLP

2

2

PR60
6.49K_0402_1%
2
1

PC54
0.01U_0402_25V7K

2

2

1

1
PD11
SX34H_SMA2 PC53
1000P_0402_50V7K

@

ADP_I 39,48

+3VLP

1

EC_SMB_CK1 39,48
PR57
1K_0402_5%

2

<40,41>
BATT+
2

PL6
SMB3025500YA_2P
1
2

@ PH2
100K_0402_1%_NCP15WF104F03RC

5
2

@ G718TM1U_SOT23-8

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR-BATTERY CONN/OTP

Size Document Number
Custom

Rev
0.1

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

50

of

59

A

B

C

D

1.5_8209_B+

LGATE

9

5
6
7
8

PC62
4.7U_0805_25V6-K
2
1

PC61
4.7U_0805_25V6-K
2
1

1

+

2

VDDP

10
DL_1.5V

PC65
330U_2.5V_M

2

4

RT8209MGQW _W QFN14_3P5X3P5
2

PC66
4.7U_0805_10V6K

AO4456_SO8

PC67
680P_0402_50V7K

2

PC68
4.7U_0603_6.3V6K

+1.5VP

1

PR85
4.7_1206_5%

PQ24

+5VALW

1

11

1

2

CS

3
2
1

15
NC

14

LX_1.5V

VFB=0.75V

B+

PL7
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

1

PGOOD

DH_1.5V

12

2

FB

6

13

PHASE

1

5

UGATE

2
PL17
FBMA-L11-322513-151LMA50T_1210

AO4406AL_SO8

PR83
PC63
2.2_0603_5%
0.1U_0603_25V7K
1
2BST_1.5V-1 1
2

PR87
15K_0402_1%

VDD

BST_1.5V

BOOT

4

PGND

VOUT

8

TON

3

7

PR86
100_0603_5%
1
2

2

1

PU5

EN/DEM

@
PC64
.1U_0402_16V7K

GND

2

1

2

3
2
1

4

1

+5VALW

1

39,44,46 SYSON

@ PR84
47K_0402_5%

1

PR81
267K_0402_1%
1
2

PR82
0_0402_5%
1
2

PC60
0.1U_0603_25V7K
2
1

PC59
2200P_0402_50V7K
2
1

5
6
7
8

1

PQ23

 VFB=0.75V
V=0.75*(1+10K/10K)=1.5V
Fsw=298KHz
1

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=19.53A, Imax=23.44A, Iocp=13.67A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A
=>1/2Delta I=2.315A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A
Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A
Iocp=23.06A~35.65A

2
10K_0402_1%

Change footprint to TPS51117

PR89
10K_0402_1%

2

2

2

PR88
1

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2010/07/13

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc.
PWR-+1.5VP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

LA-7221P

Date:

A

B

C

W ednesday, February 16, 2011
D

Sheet

51

of

59

5

4

3

2

1

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V

PC70
68P_0402_50V8J
2
1

1
1

2

PR93
10K_0402_1%

1

2

SY8033BDBC_DFN10_3X3
2

@ PR94
1M_0402_5%

2

2

FB=0.6Volt

PC74
680P_0603_50V7K

1

2

PR92 510K_0402_5%

PC72
22U_0805_6.3VAM

D

1

1

1
2

NC

PR91
20K_0402_1%

1

2

FB_1.8V

+1.8VSP

PC71
22U_0805_6.3VAM

11

EN

2

6

FB

5

PC73
0.1U_0402_10V7K

1

37,39,46,53 SUSP#

3

LX

SVIN

NC

EN_1.8V

LX_1.8V

1

2

D

PVIN

8

2

LX

PR90
4.7_1206_5%

9
PC69
22U_0805_6.3VAM

TP

JUMP_43X118

PVIN

PG

10

7

1

1

1

@

2

PL8
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

4

PU6
PJ17
2

+5VALW

1
2
PR103
10K_0402_5%

+3VS

1
2

PC84
22U_0805_6.3VAM

PC83

1

22U_0805_6.3VAM

@

+VCCSAP

@

PR102
1
2
0_0402_5%

C

VSSSA_SENSE

9

VCCSA_SENSE

9

PR100
PR107

1
1

2

SY8033BDBC_DFN10_3X3
2

PR104
1M_0402_5%

2

1
2
PR101
0_0402_5%

FB=0.6Volt

PC77
680P_0603_50V7K

2

PR99 100K_0402_5%

2

FB_VCCSAP

PC82
22U_0805_6.3VAM
2
1

6

PC78
22U_0805_6.3VAM

FB
EN

1

1

PG

SVIN

11

2

1

1

53 VCCPPWRGOOD

EN_VCCSAP
5

3

PL9
2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
1
2
PC75
68P_0402_50V8J
2
1

2

8

LX

LX_VCCSAP

2

PC76
22U_0805_6.3VAM

PVIN

2

NC

9

LX

NC

JUMP_43X118

PVIN

39

1

10

TP

1

7

1

1

@

2

PC79
0.1U_0402_10V7K

2

+5VALW

SA_PGOOD

4

PU7
PJ18
C

0_0402_5%
PR105
1

PR97
4.7_1206_5%

2

2

1
3.4K_0402_1%

1

2
10_0402_5%

1

1

+3VS

PR108
20K_0402_1%

PR109
10K_0402_5%

2

D

PR112 @
100K_0402_5%

1

@ PC85
4700P_0402_25V7K

3

2
PR113

1

100K_0402_5%

VCCSA_VID1

9

@ PR114
10K_0402_5%

B

2

B

PQ28
PMBT2222A_SOT23-3
2

2

2

3

PQ27
2N7002W-T/R7_SOT323-3

1

1

2
G
S

1

1

PR111
10K_0402_5%
2
1

2

2

1
PR95
10K_0402_1%

VID[0]
0
0
1
1

VID[1]
0
1
1
1

VCCSA Vout
0.9 V
0.8 V
0.75V
0.65V

Require on 2011/ 2012 Required
Yes/Yes
Yes/Yes
No/Yes
No/Yes

A

A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]
(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Compal Secret Data

Security Classification
Issued Date

2010/07/13

Deciphered Date

2011/07/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR +VCCSAP
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
0.1

LA-7221P
Wednesday, February 16, 2011
1

Sheet

52

of

59

5

4

3

2

PU8

1

2

4

6

GND

NC

5

VREF

NC

7

VOUT

NC

8

TP

9

2

D

3

VCNTL

VIN

+3VALW
PC87
1U_0603_10V6K

2

PR115
1K_0402_1%

1

PC86
4.7U_0805_6.3V6K

2

1

1

+1.5V

1

D

+0.75VSP
1

S

PR117
1K_0402_1%

PC90
10U_0603_6.3V6M

2

1
D

2

SUSP 2
G
PQ29
2N7002W -T/R7_SOT323-3

1

PQ30
2N7002W -T/R7_SOT323-3

3

S

2

PC89
1U_0402_6.3V6K

D

2
G
3

1

5,46 SUSP

1

PR116
100K_0402_1%
1
2

PC88
.1U_0402_16V7K
2
1

G2992F1U_SO8

PJ19
1.05VS_51117_B+

10

LGATE

9

2

PC99
4.7U_0805_10V6K

1
+

@ PC98
680P_0402_50V7K

2

PR123
0_0402_5%

1

NC
8

7

4
PQ32
AO4456_SO8

@ PR122
4.7_1206_5%

1 2

DL_1.05VS_VCCP

2

PC100
4.7U_0603_6.3V6K
B

3
2
1

+5VALW

RT8209MGQW _W QFN14_3P5X3P5

+1.05VS_VCCPP

1

2

PGOOD

C

2

VDDP

VFB=0.75V

2

B+

1

LX_1.05VS_VCCP

11

1

1

PL10
1UH_FDUE1040D-1R0M-P3_21.3A_20%

5
6
7
8

12

CS

1

6

PHASE

2

JUMP_43X118

PC97
330U_2.5V_M
PR145
0_0402_5%
2

VSSIO_SENSE 8

1

3
2
1

FB

DH_1.05VS_VCCP

1

5

13

2

VDD

UGATE

PR125
15K_0402_1%

VOUT

4

BOOT

3

PR121
PC96
0_0603_5% 0.1U_0603_25V7K
BST_1.05VS_VCCP 1
2
1
2

14

1
EN/DEM

TON

PGND

PR124
100_0603_5%
1
2

2

GND

2
S

15

PU9
PC95
0.1U_0603_25V7K

1

+5VALW

@ PR120
47K_0402_5%

2
G
3

SUSP

D

2

PQ45
2N7002W -T/R7_SOT323-3

1

1

4

PC94
4.7U_0805_25V6-K
2
1

PQ31
AO4406AL_SO8

PC93
4.7U_0805_25V6-K
2
1

PR119
680K_0402_5%
1
2

1

37,39,46,52 SUSP#

PR118
267K_0402_1%
1
2

PC92
0.1U_0603_25V7K
2
1

PC91
2200P_0402_50V7K
2
1

5
6
7
8

C

2
@

B

Change footprint to TPS51117 (1/23)
PR126
4.02K_0402_1%
1
2
PR128
10_0402_5%
2
1

1

52

VCCPPW RGOOD

PR127
10K_0402_1%

PR129

1

2

VCCIO_SENSE

8

+3VALW

2

2

10K_0402_1%

PR130 @
10K_0402_1%

A

1

 VFB=0.75V
V=0.75*(1+4.02K/10K)=1.052V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=12.866A, Imax=9A, Iocp=15.439A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A
=>1/2Delta I=1.665A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A
Iocp=23.02A~37.62A

A

Compal Secret Data

Security Classification
2010/07/13

Issued Date

Deciphered Date

2011/07/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR +1.05VS_VCCPP/+0.75VSP

Size
Document Number
Custom

Rev
0.1

LA-7221P

Date:

W ednesday, February 16, 2011

Sheet
1

53

of

59

24

LGATE1

PHASE1

23

PHASE1

UGATE1

22

UGATE1

BOOT1

21

BOOT1

1

1

1

2

2

+5VS

1

@ PR152

1

ISNG

0_0402_5%

Connect to +5V can disable
GFX portion

1

VDD

VIN

GFX_B+

2

2

2

20

19

PR162
2.2_0603_5%

1
3
2
1

1
2
1

1

3
2
1

2-ph: PR178=1.47K for ~70A OCP

Issued Date

1
2

PC151
PR183
680P_0603_50V7K 4.7_1206_5%

3
2
1

4

1

PC150
0.22U_0603_10V7K
LGATE1

PQ38
TPCA8057-H_PPAK56-8-5

8

1

1

1

ISEN1

10K_0402_1%

+CPU_CORE

2

PR185
3.65K_0402_1%
VSUM+ 1
2
ISEN1

A

10K_0402_1%
1 PR184 2

PR187
10K_0402_1%
2
1ISEN2

1_0402_5%
VSUM- 1 PR186 2

Compal Electronics, Inc.
2009/04/28

Deciphered Date

Title

CPU_CORE/GFX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

3

Compal Secret Data
2010/01/25

2

PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PHASE1
PR182
2.2_0603_5%
BOOT1 2
1 2

PR171

PC149
4.7U_0805_25V6-K
2
1

4

PC127
68U_25V_M_R0.44

1
2

10K_0402_1%
1 PR168 2
PR170

ISEN2

PC148
4.7U_0805_25V6-K
2
1

PR227
0_0603_5%
1
2

PC81
10U_0805_25V6K

B

1_0402_5%
PC147
4.7U_0805_25V6-K
2
1

5

PC146
.1U_0402_16V7K

+CPU_CORE

2

PR169
3.65K_0402_1%
VSUM+ 1
2

CPU_B+
VSUM-

+

2

2
B+
PL11
FBMA-L11-322513-151LMA50T_1210

3

VSUM-

PQ37
CSD17308Q3_SON8-5

1

PC140
PR166
680P_0603_50V7K 4.7_1206_5%

3
2
1

4

2

PC132
0.22U_0603_10V7K
LGATE2
PR167
2.61K_0402_1%

PQ36
TPCA8057-H_PPAK56-8-5

1

1
1

PL13
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PH6
10K_0402_1%_ERTJ0EG103FA

2

@

PC138
0.22U_0402_10V6K
2
1

1

VSUM+

PR165
2.2_0603_5%
BOOT2 2
1 2

2
2

PC125
4.7U_0805_25V6-K
2
1

4

PC124
4.7U_0805_25V6-K
2
1

1
2

PR226
0_0603_5%
1
2

UGATE2

PQ35
CSD17308Q3_SON8-5

1

5

CPU_B+

PJ21
JUMP_43X39
@

1

EMI request for ISN issue (1/7)
PC126
4.7U_0805_25V6-K
2
1

2

0.22U_0603_25V7K
PC123

Security Classification

4

GFX@ PR151
953_0402_1%

C

Date:

5

GFX@ PC120
10U_0805_25V6K

1
2

2

2
1
1

ISPG

PC118
GFX@ 0.068U_0402_16V7K

PR160
0_0402_5%

PR181
10_0402_1%

VSSSENSE

8

GFX@ PQ33
CSD17308Q3_SON8-5

3
2
1
5
3
2
1

1
25

UGATE1

@

VCCSENSE

PC164
1U_0603_10V6K

2

PWM3
LGATE1

PC111
330U_X_2VM_R6M

GFX@ PR144
GFX@ PH4
7.5K_0402_1% 10K_0402_1%_ERTJ0EG103FA
1
2 1
2
GFX@ PC115
.1U_0402_16V7K
1
2
1
2
GFX@ PR147
11K_0402_1%
1
2

2
2

1

VCCP

GFX@

2

2

LGATEG

2
1
2
PC143
0.01U_0402_50V7K

1
2

330P_0402_50V7K
PC142
2
1

10_0402_1%
1
2

PR179

+GFX_CORE
Iocp=40A, IccMAX=24A
Load line=3.9mohm
DCR=1.1mohm

2

PHASEG

31
LGATEG

LGATE2

26

@

+CPU_CORE
Iocp=70A, IccMAX=53A
Load line=1.9mohm
DCR=1.1mohm

2

UGATEG

32
ISUMP
18

ISUMN
17

RTN

ISEN1

3.32K_0402_1%

+CPU_CORE

1

BOOTG

33

PHASEG

27

D

+
GFX@ PR142
1_0402_5%

GFX@ PC117
.1U_0402_16V7K
1
2

1

2
PR176

A

2

NTCG

34
BOOTG

UGATEG

LGATE2

PR178
1.47K_0402_1%
2
1

1

PC113
PR138
680P_0603_50V7K 4.7_1206_5%

ISNG

35

ISUMNG

NTCG
16

12

2

1

PC141
470P_0402_50V8J

PHASE2

2

PHASE2

330P_0402_50V7K

1

3
GFX@ PR141
3.65K_0402_1%

CPU_B+

PR180 PC145
100_0402_1%
2
1

2

UGATE2

28

PR164
1_0603_5%

FB

1

29

PHASE2

+5VS

VSUM-

2K_0402_1%
@ PR177
2

GFX@ PQ34
TPCA8057-H_PPAK56-8-5

ISPG

37

36

38

11

FB

1
2

PC130 10P_0402_50V8J
2
1comp

COMP

VW

ISEN2

NTC

15

VR_HOT#

9

ISEN1

8

PC135
PR173
1000P_0402_50V7K 887_0402_1%

2 1

UGATE2

PGOOD

2
1
PC134
47P_0402_50V8J

PC137
680P_0402_50V7K

1

RTNG

FBG

ISL95835HRTZ-T_TQFN40_5X5

PC129
1000P_0402_50V7K

1
2
PR172
20.5K_0402_1%
1
2

comp

267K_0402_1%
PR175
2
1 2

1
PR131
GFX@ 3.83K_0402_1%

4

+GFX_COREP
1

1

VR_ON

BOOT2

2

SCLK

6

30

PR174
11K_0402_1%
1
2

5

EMI request for ISN issue (1/7)

PR218
0_0603_5%

BOOT2

PC131
1U_0603_10V6K

ALERT#

GFX@ 27.4K_0402_1%
PR133

2

2

PR163
8.06K_0402_1%

1

LGATEG

+5VS

PC139
0.022U_0402_16V7K
2
1

SDA

4

10

2-ph: PR172=20.5K Vboot=0V, Iccmax=54A
2-ph: PR172=169K Vboot=1.1V, Iccmax=54A

ISUMPG

40

3

7

NTC

GFX@ 470KB_0402_5%_ERTJ0EV474J
PH3
2
1
2
1

PAD
PGOODG

ISEN3/ FB2

1

VWG

2

14

2

1

13

PR155

0_0402_5%

PC122

BOOTG 2

ISEN3

1

VR_ON

VGATE

47P_0402_50V8J

GFX@ PC108
0.22U_0603_10V7K
1 2
1

GFX_B+

GFX@ PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PHASEG

1

39

PR161

2
1
27.4K_0402_1%

0_0603_5%

1

0.22U_0402_6.3V6K2
PC133
0.22U_0402_6.3V6K2
PC136

SVID_ALERT#

SVID_SCLK

PR158
3.83K_0402_1%

470KB_0402_5%_ERTJ0EV474J
PH5
2
1
2

1

2

1

GFX_CORE_PWRGD

8 VR_SVID_ALRT#
8 VR_SVID_CLK

39

41
39

8 VR_SVID_DAT

COMPG

2
2
2
1

1

2
1
1.91K_0402_1%
PR156
1
2

2
1

PR148
130_0402_1%

PR149
54.9_0402_1%

PU10

PR217
GFX@ 1.91K_0402_1%

39 VR_HOT#

B

4

+3VS

+1.05VS_VCCP

FB

GFX@ 8.06K_0402_1%
PR132

NTCG

2

GFX@ PR137
2.2_0603_5%

GFX@ PC106
1000P_0402_50V7K
2
1

@ PC144
.1U_0402_16V7K

1

VSS_AXG_SENSE 9

1

ISEN2

2

+3VS

C

1

GFX@ PC110
0.01U_0402_50V7K

0.1U_0402_16V4Z

15

UGATEG

PR221

2

GFX@ PR139
GFX@ 330P_0402_50V7K
475K_0402_1%
PC104

Add 1.0u for sequence control (1/17)

PR159
@ 499_0402_1%

+GFX_COREP

VCC_AXG_SENSE 9

2

PR135
GFX@ 422_0402_1%
1
2
1

2

1

GFX@ PR134
10_0402_1%

5

PR136
294K_0402_1%
2
1

1

2

@
PC107
330P_0402_50V7K
1
2

GFX@ PR143
10_0402_1%

GFX_CORE_PWRGD

2

2

GFX@ PC112
150P_0402_50V8J

PC165

1

1

PR140
GFX@ 2.55K_0402_1%
2
1

5

@ 1K_0402_1%

1
PR153

2

2
PC116
1
2

@ 330P_0402_50V7K

D

PC105
GFX@ 39P_0402_50V7K
2
1

GFX@ PC103
4.7U_0805_25V6-K
2
1

1

1

2

GFX@ PC102
4.7U_0805_25V6-K

3

GFX@ PC101
4.7U_0805_25V6-K

4

5

5

2

Rev
0.1

JM/SJM30
Sheet

Wednesday, February 16, 2011
1

54

of

59

5

4

FBMA-L11-322513-151LMA50T_1210
PL18
1
2

B+

3

2

1

B+_CORE

1

1

5

@ PR188
10K_0402_5%

2

VGA@ PC153
10U_1206_25V6M

2

1

+3VS
VGA@ PC152
10U_1206_25V6M

4

10

BST_VCORE

DRVH

9

DH_VCORE

3

EN

SW

8

SW_VCORE

4

VFB

V5IN

7

5

RF

DRVL

6

1

1

1

VGA@ PR195
0_0402_5%

2

1 2
VGA@ PC158
680P_0603_50V7K
GS@
PR198
2.26K_0402_1%

VGA@ PC157
330U_D2E_2.5VM

+

2

VGA@ PR196
10_0402_5%
2
1

C

2

4

VGA@ PR193
4.7_1206_5%

2

VGA@ PC159
.1U_0402_16V7K

4

ESR=10mohm

VGA@ PQ41
TPCA8057-H_PPAK56-8-5

Switch freq. (RF pin setting)
47K ==>450KHz
100K ==>390KHz
200K ==>350KHz (Currently setting)
470K ==>300KHz

5

VGA@
PC155
1U_0603_6.3V6M

3
2
1

2

C

1

VFB=0.6V

1

VGA@ PR194
10K_0402_1%
1
2

+VGA_COREP

1

DL_VCORE

11

TP

3
2
1

VGA@ PR191
200K_0402_1%

1

VGA_ON

4

+5VALW

RT8237_SON10_3X3

25,46 VGA_ON

VGA@ 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PL15
3
2

VGA@ PQ40
TPCA8057-H_PPAK56-8-5

2

VBST

TRIP

DL_VCORE

2

1
@ PR192
10K_0402_5%

PGOOD

2

5

+3VS

1

VGA@ PC154
0.1U_0603_25V7K
1
2

2

VGA@ PR190
75K_0402_1%
1
2

VGA@ PR189
2.2_0603_5%
1
2

VGA@

3
2
1

PU11

VGA@ PQ39
CSD17308Q3_SON8-5

D

2

D

GCORE_SEN

VGAVCC_SENSE 24

GV@ PR198
2.15K_0402_1%

1

TPCA8057-H Rds=2.6m/3.2m ohm

+3VSDGPU

2

VGA@ PR202
10K_0402_5%

6

1

2

2

S

1

GV@ PR205
10K_0402_1%

+3VSDGPU

1

+3VSDGPU

2

1
VGA@ PC162
4700P_0402_25V7K

VGA@ PR210
10K_0402_5%

3

2

D

GPU_VID2 22

3

4

VGA@ PR224
10K_0402_5%

2

D

GPU_VID1

GPU_VID0

NVIDIA/N12P-GS

NVIDIA/N12P-GV1

VGA@

PQ43B

VGA@ PR214
10K_0402_5%
5 2
1
G

@ PR213
10K_0402_5%

1

0

1

1.0V

P0(Hot)

1

1

0

0.975V(default)

1.0V

P8/P12

1

1

1

0.860V

0.85V(default)

0

1

1

0.900V

----

Compal Secret Data

Security Classification
Issued Date

2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JM/SJM30
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

A

2

1.025V

GPU_VID0 22,39
VGA@ PR215
10K_0402_5%

S

4

DMN66D0LDW-7_SOT363-6
A

P0(Cold)

4

2

S

11

DMN66D0LDW-7_SOT363-6

GPU_VID2

GPU_VID1 22,39
@ PR212
10K_0402_5%

S

2

G

PQ44B

VGA@ PR211
10K_0402_5%
2
1

1

VGA@

G
VGA@ PQ42B
DMN66D0LDW-7_SOT363-6
+3VSDGPU

1

3

VGA@ PR223
VGA@PR223
10K_0402_5%
VGA@ PR225
10K_0402_5%
5
2
1

5

1

@ PR209
10K_0402_5%

1

6

1

1

S
+3VSDGPU

B

2

@ PR220
10K_0402_5%

2

2

2

1

S

G

VGA@ PC163
4700P_0402_25V7K

1

2

VGA@ PR208
10K_0402_5%
1
2

D

1

G

VGA@ PQ44A
DMN66D0LDW-7_SOT363-6

VGA@ PR207
10K_0402_5%
VGA@ PQ43A
DMN66D0LDW-7_SOT363-6

2

6

VGA@ PR222
10K_0402_5%
1
2

D

D

5

@ PR206
10K_0402_5%

2

2

2

2

VGA@ PR216
10K_0402_5%

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm.
Ipeak=41.02A, Imax=28.714A, Iocp=43A
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A
=>1/2Delta I=3.4A
choose Rcs=75K
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A
Iocp=48.42A~75.52A

SJM only ==> VPS

VGA@ PC161
4700P_0402_25V7K

1

2

+3VSDGPU

1

B

GS@PR219
GS@PR219
37.4K_0402_1%

VFB=0.7V
V=0.7*(1+Rtop/Rbottom)
Fsw=350KHz

DMN66D0LDW-7_SOT363-6
VGA@ PQ42A

1

1

G

Vtrip range ==> 0.2V ~ 3V

VGA@ PR203
10K_0402_5%
1
2

D

1

2

1

VGA@ PR200
10K_0402_1%

2

VGA@ PC160
2200P_0402_25V7K
GS@
PR205
13.3K_0402_1%

GV@PR201
GV@PR201
8.66K_0402_1%

2

1

1

GS@PR201
GS@PR201
10.7K_0402_1%

3

2

+VGA_COREP
Rev
0.1

Wednesday, February 16, 2011

Sheet
1

55

of

59

5

4

3

2

Version change list (P.I.R. List)
Item

D

Fixed Issue

1

Page 1 of 2
for PWR
Reason for change

Rev.

PG#

1

HW/Edward request

Meet Turn off sequence

53

2

HW/Edward request

Meet Turn on sequence

53

3

HW/Edward request

Meet new VGA table

55

4

Battery Turn on time too long

Change enable 3/5V path

5

HW/Edward request

For USB 3.0 charger function

47

6

HW/Edward request

Don't need VGA_PW_OK net

55

Modify List

Date

2010
11/24

DVT

2010
11/27

DVT

2010
12/03

DVT

2010
12/04

DVT

Add PJ26

2010
12/04

DVT

Delete net

2010
12/04

DVT

2010
12/10

DVT

2010
12/10

DVT

Add PQ45
Change PR119 to 680KΩ, PC95 to 0.1uF

Change PR201, PR205, PR219

C

7

NVedia request.

8

HW request.

9

NVedia request.

0.2

55

to adjust power sequence to modify.

0.2

52
53

Sourcer request.

Change to a normal part.

0.2

54

10

EMI request

For ISN issue, add solution on charger and
CORE power

0.3

48,54

11

EMI request

0.3

48

For ISN issue, add solution on charger

change PR201 to SD034107280.
change PR198 to SD034226180
chnage PR205 to SD034133280.
Change PR219 to SD034374280
Change PR92 to SD034510380, remove PR94 SD028100480
Change PR116 from SD034249280 to SD034100380.

2010
12/10

Change PC138 from SE00000R700to SE095224K00

13

TI concern charger IC will be lauch

RT8209 footprint issue

DVT

2010
01/17

PVT

Change PL2 to SH162100M10 (4.7U to 10U)

2010
01/17

PVT
PVT
PVT

Negative current reaches 110mV on low side Rdson
Charger IC will be lauch

0.3

48

Change PC38 to SE026104K80 (2.2U to 0.1U)

2010
01/23

The footprint pad is too short, It will happen
SMT problem

0.3

51
53

Change PU5, PU9 footprint to
TPS51117RGYR_QFN14_3P5X3P5

2010
01/23

D

C

Add PL16 PC19 PC109 PC80 PC51 PC120 PC81

B

12

Phase

B

14

15
16
A

A

17

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PIR (PWR)
Rev
0.1

P5LJ0

W ednesday, February 16, 2011

Sheet
1

56

of

59

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

41

Memo

2010/11/25

Compal

2

27~30

Memo

2010/11/25

Compal

3

42

Memo

2010/11/25

Compal

4

41

LED

2010/11/25

5

07

EDP

6

24

7

05

8

9

1

Page 1

Issue Description

Solution Description

Bom structure error.

Rev.

Correct LED1,LED2,LED5 bom structure to JM@

Rev02

Change X76289BOL05(VRAM P/N) from SA00003MQ60 to SA000047Q20
Change X76289BOL06(VRAM P/N) from SA00003VS10 to SA00003YO20

Rev02

New Audio Codec IC

Change U29 from SA000034010 to SA000034020
Change R635 from 0.1ohm to 0 ohm

Rev02

Compal

Battery LED Color mistake

SWAP LED1,LED6,LED7,LED8,LED9 Pin 2 and Pin3
(Pin2-->BATT_AMB_LED#,Pin3-->BATT_BLUE_LED#)

Rev02

2010/12/08

Compal

Bom structure error.

Correct R70 bom structure to EDP@

Rev02

2010/12/08

Compal

N12P-GV Strap sets up the mistake

XDP

2010/12/08

Compal

07

EDP

2010/12/08

Compal

15

PCH

2010/12/08

Compal

D

D

Rework instruction

a. Pop R382, Depop R388 (ROM_SO: pull up 10K ohm)
b. Pop R380, Change R380 from 15k to 45k. Depop R386.(STRAP2: pull up 45K ohm.)
c. Pop R760, Change R760 from 10k to 5k.( STRAP3: pull down 5K ohm.)
d. Pop R756. (STRAP4: pull down 10K ohm.)
e. Pop R578. (STRAP_REF2, need to stuff with 40K ohm 1%.)
f. Pop R757. (PGOOD (pin E7) stuff 10K ohm.)

Rev02

Depop XDP component

Rev02

C

C

10

17

PCH

2010/12/08

Bom structure error.

Correct R70 bom structure to EDP@

Rev02

Change R244.1 net name from PCH_RSMRST# to PCH_RSMRST#_R
Pop R223,Depop U5
Delete R231(0 ohm) between SUSACK#_R and SUSWARN#_R
Add T90 test point for SUSACK#

Rev02

Delete VGA_ON for PD only.
Change PR3.2 to PCH_GPIO53
Delete R257
Change U6.U7 to SA00000OH00

Compal

11

18

PCH

2010/12/08

Compal

12

22

GPU

2010/12/08

Compal

13

26

GPU

2010/12/08

Compal

Bom structure error.

Correct C381 & C857 bom structure to OPT@

14

31

LVDS

2010/12/08

Compal

For LCDVDD rise time sequence issue

Change R468 from 1k to 100k
Change C481 from 0.047u to 0.47u
PCH_LCD_CLK & PCH_LCD_DATA,Pull high at PCH side.
Add R832 between +3VS and JLVDS1.31.

15

32,33

CRT.HDMI

2010/12/08

Compal

D8, D9 change material to SCS00003600

HDMI

2010/12/08

Compal

Pop R502.Depop D9
SDVO_CTRL.DATA strap pull high at PCH side

Rev02

ODD.USB3.0

2010/12/08

Compal

Change Q31.Q63.Q71 to SB000008J10

Rev02

Change R541.2 net name from PCH_PCIE_WAKE# to LAN_WAKE#.
Pop R541

Rev02

B

16

33

17

34.44

18

35

LAN

2010/12/08

Compal

19

35

LAN

2010/12/08

Compal

Power sequence for DGPU_PWROK after 1.5VSDGPU

Rev02

Auto power on issue

36

Transformer

2010/12/08

Rev02

Change R342.1 from R762.2 to R762.1(NV_PERFORMANCE_R)

Rev02

Compal

B

Rev02

Rev02

Rev02
A

Change T63 from SP050003T10 to SP050003T20

Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

Rev02

Compal Secret Data

Security Classification

5

Rev02

Change C583 from 27 to 15P
Change C582 from 27to 18P
Change Y4 from CL(20P)to CL(12P)
Add Q76 and Depop R555

A

20

Add Q75,Q74,R841

2

Title

Compal Electronics, Inc.
EE P.I.R (1)

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

57

of

59

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

Page 2

Issue Description

Solution Description

Rev.

21

36

LAN

2010/12/08

Compal

22

37

3G

2010/12/08

Compal

23

37

D_Door switch

2010/12/08

Compal

Add R838,R839
Depop R838
Pop R839

Rev02

24

38

Card Reader

2010/12/08

Compal

Change R590,R591 to 22ohm
Change C635,C636 to 10P
Add R833 between +3VS and +3VS_CARD

Rev02

25

39

EC

2010/12/08

Compal

Change R621 from 0ohm to 8.2k(Board ID)
Add C863

Rev02

26

40

TP

2010/12/08

Compal

27

40

Power Button

2010/12/08

Compal

28

40

Reset Button

2010/12/08

Compal

29

41

Power board

2010/12/08

Compal

30

42

HD Audio Codec

2010/12/08

Compal

31

42

HD Audio Codec

2010/12/08

Compal

L31 update CIS Symbol and PCB footprint

Rev02

Delete L49.L50.R764.R765.R766.R767.U43.C852.C853.CR781.Q69.C856.C854.
C855.C851.R572.R782
Change J3G1 Pin 2.4.6.8.10 to +3VS
Change R572.3 to +3VS
Change J3G1.30 to +VSB
Change J3G1.17 to EC_SIM_DETECT#

Rev02

D

C

D

3G Power noise

Change JTP1 Pin define
(Pin-->GND,Pin2-->RIGHT_BTN#,Pin3-->LEFT_BTN#,Pin4-->TP_DATA,
Pin5-->TP_CLK,Pin6-->+5VS)
Change JTP2 Pin define
(Pin-->NC,Pin2-->GND,Pin3-->TP_CLK,Pin4-->TP_DATA,Pin5-->PWM,Pin6-->+5VS)
Add C864

TP Pin define issue

Reset system by mainpower and BI

Fix HP/MIC Detect issue

B

Rev02

Change R622.2 from +3VALW to +3VALW_EC

Rev02

Add R844,R836.R837.Q72.Q77
Change R836 to 1K
Change R837 to 10K

Rev02

Change JPWR2.5 from NC pin to BI_R (SJM D_door)
Change LID_SW# from LED board(JLED1.8) to Power board(JPWR1.2)

Rev02

Change R649 from 39.2k to 10k
Change R650 from 10k to 39.2k

Rev02

Change C704.C705 to SE107225K80
Delete R637.R638.Q39.Q38.R634. R636.R639.R640.J2
Change power from +3VS to +3VS_CODEC.
Add R834

Rev02

Change R735.1 to HP_RIGHT
Change R734.1 to HP_LEFT
SWAP JHP1.3 and JHP1.8
(Pin8-->SPDIF_OUT and Pin3-->+5VSPDIF)

Rev02

Delete R666.R668
Add L50,L51 300ohm bead(SM010017710)

Rev02

Delete R797,R830
Add R840,Q73.Q71

Rev02

B

32

43

Headphone Out/SPDIF

2010/12/08

Compal

33

43

Digital MIC

2010/12/08

Compal

34

44

USB3.0

2010/12/08

Compal

35

44

USB3.0

2010/12/08

Compal

Change c792.c793 from 12P to 15P

Rev02

36

45

USB3.0

2010/12/08

Compal

Delete D46
Change C780 from SGA19151410(D size) to SGA00002N80(B2 size)
Depop U41,C204,R754
Add R842,R843

Rev02

HP right and left channel inverse issue

Modify SMI circuit for leakage issue

A

37

45

Screw Hole

2010/12/08

Issued Date

Rev02

Compal Secret Data

Security Classification
2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

A

Change H4 from H_3P0 to H_3P3
Change H8 from H_3P0 to H_3P0x5P0
Delete H25

Compal

4

3

2

C

Title

Compal Electronics, Inc.
EE P.I.R (2)

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Wednesday, February 16, 2011

Sheet
1

58

of

59

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#
38

46

Title

Date

DC Interface

2010/12/08

Request
Owner

1

Page 3

Issue Description

Solution Description

Compal

Rev.
Rev02

a.+5VS (Change R679 from 20K to 100K)
b.+3VS (Change R685 from 47K to 200K)
c. +1.5VS (Change R692 from 200K to 750K)

D

D

PCH

2010/12/08

Compal

Change U3 from SA00004EE10 to SA00004EE40

Rev02

Caed Reader

2010/12/08

Compal

Change R587 from SD028330A00 to SD028330A80

Rev02

Capacitor

2010/12/08

Compal

C226, C540, C549, C566, C573, C576, C580, C590, C712 change material to SE000000K80

Rev02

24

GPU

2010/12/10

Compal

Update N12P-GV QS DevID: 0x1050

1. ROM_SCLK: pull up 5K ohm.
2. STRAP2: pull down 5K ohm.
3. ROM_SO: pull up 10K ohm.

Rev02

43

44

USB3.0

2010/12/20

Compal

USB driver can't install issue

Change Q73.2 from +3V_USB3.0 to +3V_USB3
Pop R840

Rev03

44

31

CMOS Camera

2010/12/29

Compal

Add R845,Delete R832

Rev03

45

39

BI

2011/01/03

Compal

Add R848

Rev03

46

40

TP

2011/01/03

Compal

Change SW2.SW3 from SN111002700 to SN100000K00

Rev03

47

41

LED

2011/01/12

Compal

Change R625 from 3.9K to 680 ohm
Change R626 from 2.2K to 390 ohm
Change R739 from 3.9K to 390 ohm
Change R740 from 100 to 3.3K ohm

Rev03

48

46

VGA_ON

2011/01/13

Compal

Restart dGPU loss issue.

Change R703 from 22K to 100K
Add R849 (10K)

49

19

CRT

2011/01/22

Compal

water ripple issue

Change L1 from SM01000AX00 to SHI00003Y00

50

39

EC

2011/01/25

Compal

Delete U27

Rev0.5

51

41

BTN

2011/01/25

Compal

Change SW6 from SN100001C00 to SN100001D10

Rev0.5

52

39

Board ID

2011/01/27

Compal

Change R621 to 33K

Rev0.5

53

5

CPU XDP

2011/01/27

Compal

Delete C34.C35.Q1.R21.R24.JXDP1.R3~R16.R18~R22.R39~R41.R43.R45~R47.R53~R60
Add T94~T98

Rev0.5

54

40

TP

2011/01/27

Compal

Delete net name TP_PWM

Rev0.5

39

13~21

40

38

41

20.34.
35.36.42

42

C

B

C

55

18

DGPU_PWROK

2011/01/27

Compal

56

44

USB3.0

2011/01/27

Compal

TI charger short protection prevent

Board ID version

For EEPROM (EON).

Rev04

Rev04

Pop C872

Rev0.5

Pop R720

Rev0.5

B

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
EE P.I.R (3)

Size Document Number
Custom

Rev
0.2

LA-7221P

Date:

Friday, February 18, 2011

Sheet
1

59

of

59

www.s-manuals.com



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Title                           : Compal LA-7221P - Schematics. www.s-manuals.com.
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