Compal LA 7221P Schematics. Www.s Manuals.com. R1.0 Schematics

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Page Count: 60

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Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
1
Compal Electronics, Inc.
Cover Page
0.2
LA-7221P
59
2010/08/012009/08/01
Custom
Friday, February 18, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
1
Compal Electronics, Inc.
Cover Page
0.2
LA-7221P
59
2010/08/012009/08/01
Custom
Friday, February 18, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
1
Compal Electronics, Inc.
Cover Page
0.2
LA-7221P
59
2010/08/012009/08/01
Custom
Friday, February 18, 2011
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
JM50-HR M/B Schematics Document
REV:0.5
Compal Confidential
2010-02-16
Nvidia N12P-GS/GV
Model Name : P5LJ0 & P5LS0
File Name : LA-7221P
Compal Confidential
Part Number Description
DA80000MA00 PCB 0IN LA-7221P REV0 M/B
MB PCB
Part Number Description
DA80000MA00 PCB 0IN LA-7221P REV0 M/B
MB PCB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
2009/08/01 2010/08/01
592
LA-7221P
0.2
Block Diagrams
Compal Electronics, Inc.
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
2009/08/01 2010/08/01
592
LA-7221P
0.2
Block Diagrams
Compal Electronics, Inc.
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
2009/08/01 2010/08/01
592
LA-7221P
0.2
Block Diagrams
Compal Electronics, Inc.
Custom
Wednesday, February 16, 2011
USB port 10USB port 13
USB port 8
page 5
CPU XDP
100MHz
33MHz
100MHz
LS-7223P(JM)
100MHz
1GB/s x4
DMI x4
100MHz
FDI x8
port 2 port 1
Sub-board
page 41
page 37
page 13
SPI
SATA x 6
(GEN1 1.5GT/S ,GEN2 3GT/S)
RTC CKT.
page 13
3.3V 24MHz
LAN(GbE)
AR8151/8152
page 35
MINI Card x1
CMOS Camera
WLAN
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
Dual Channel
2.7GT/s
Power On/Off CKT.
Touch Pad
LPC BUS
page 42
Processor
Int.KBD
page 39
BANK 0, 1, 2, 3
USB 2.0 conn x3
CX20584
DC/DC Interface CKT.
Sandy Bridge
3.3V 48MHz
RJ45
page 39
Fan Control
Power Circuit DC/DC
page 40
204pin DDRIII-SO-DIMM X2
page 46
Intel
BIOS ROM
1.5V DDRIII 1066/1333
page 40
HDA Codec
Memory BUS(DDRIII)
PCH
HD Audio
page 45
page 4~10
Cougar Point-M
page 11,12
page 40
ENE KB930
page 36
page 37
page 37page 37 page 31
rPGA989
Intel
Bluetooth
Conn
port 2
SATA CDROM
Conn. page 34
SPI ROM x1
page 47~55
USBx14
page 13~21
port 0
page 34
SATA HDD
Conn.
Power/B
USB/B 3 port
USB Port0,1,2
USB port 0,1,2 on USB/B
LS-7224P(JM)
3G/B
USB Port 9,12
page 41
989pin BGA
PCI-E 2.0x16 5GT/s PER LANE100MHz
133MHz
LVDS Conn.
page 31
CRT Conn.
page 32
HDMI(Optimus1.0)
HDMI(Optimus1.1)
Nvidia N12P-GS/GV
973pin BGA
page22~30
PEG(DIS)
page 33
HDMI Conn.
CRT(UMA/Optimus)
LVDS(UMA/Optimus)
HDMI(UMA/Optimus)
EDP
page 32
USB uPD720200A
USB 3.0 conn x1
page 44.45
port 3
Card Reader
RTS5209
page 38
port 4
page 43
page 43
Audio AMP
MIC Jack
page 43
SPDIF Jack
USB port 9,12 on 3G/B
Mini Card
(WWAN,SIM)
page 37
(reserved)
LS-7221P
LS-7222P(JM)
page 37
LED/B
page 37
USB/B/DW 3 port
USB Port0,1,2
LS-7225P
3G/B
USB Port 9,12
LS-7226P(SJM)
page 37
LS-7227P(SJM)
page 41
Power/B
page 43
Int. Speaker
TI TPS6017
(SJM) (JM)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Compal Electronics, Inc.
Notes List
0.2
LA-7221P
3 59
2010/08/012009/08/01
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Compal Electronics, Inc.
Notes List
0.2
LA-7221P
3 59
2010/08/012009/08/01
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Compal Electronics, Inc.
Notes List
0.2
LA-7221P
3 59
2010/08/012009/08/01
Custom
Wednesday, February 16, 2011
USB 2.0 USB 1.1 Port 3 External
USB Port
Camera
USB/B (Right Side)
Blue Tooth
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
1101 0010b
ON OFF OFF
Board ID / SKU ID Table for AD channel
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VS
+5VALW
+3VALW +3VALW always on power rail
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
ONON
ON
ON BOARD ID Table
EC SM Bus1 address
Device
OFF
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
+1.5V to +1.5VS switched power rail
+CPU_CORE
STATE SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID V typ
AD_BID VAD_BID max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
PCH SM Bus address
Device
Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)
Address
Address Address
Voltage Rails
VIN
B+
+1.05VS_VCCP
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
ON
ON ON*
OFF
OFF
0.2
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
ON ON*
ON OFF OFF
+3VALW_PCH
+3V_LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
+3VALW to +3V_LAN power rail for LAN
ON ON
ON ON
S1
+5VALW_PCH
S3 S5
ON
ON
ON ON
OFF
N/A N/A N/A
N/AN/AN/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
+1.5VP to +1.5V power rail for DDRIII ON ON OFF
0.3
1.0
0001 011X b
ON*
OFF
BOM Config
JM OPTIMUS:
JM UMA Only: Mini Card(WWAN)
Mini Card(WLAN)
+1.5V
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
ON OFF OFF
BT@/3G@/UMA@/OPT@/JM@/8151@/GV@/GS@
BT@/3G@/UMA@/UMAO@/JM@/8151@
+VGA_CORE
ON OFF OFF
Core voltage for GPU
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+3VALW_EC +3VALW always to KBC ON ON ON*
ON*
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
+5VS +5VALW to +5VS switched power rail OFFON OFF
ON*
SIM Card
3G & BT Config
3G SKU: 3G@
BT SKU: BT@
USB/B (Right Side)
VRAM BOM Config
X76289BOL01 512M SAM 64M16
X76289BOL02 512M HYN 64M16
X76289BOL03 1G SAM 64M16
X76289BOL04 1G HYN 64M16
X76289BOL05 2G SAM 128M16
X76289BOL06 2G HYN 128M16
USB/B (Right Side)
SJM OPTIMUS:
SJM UMA Only:
BT@/3G@/UMA@/OPT@/SJM@/8151@/GV@/GS@
BT@/3G@/UMA@/UMAO@/SJM@/8151@
UMA@UMA with OPTIMUS
OPTIMUS1.0 OPT@
OPTIMUS1.1 OPT11@
N12P-GS@
N12P-GV@
GS@
GV@
VRAM X76@
Connector
3G
Blue Tooth BT@
CONN@
3G@
BTO Option Table
BTO Item BOM Structure
LAN Chip AR8151
LAN Chip AR8152
8151@
8152@
JM Board
SJM Board
JM@
SJM@
EDP EDP@
Unpop
Power GPU
@
VGA@
UMAO@UMA Only
4319BOBOL01/L21 UMA W3G HDMI
4319BOBOL02/L22 UMA N3G HDMI
4319BOBOL03/L23 N12PGS 1GW3G HDMI
4319BOBOL04/L24 N12PGS 1GN3G HDM
4319BOBOL05/L25 N12PGS 2GW3G HDMI
4319BOBOL06/L26 N12PGS 2GN3G HDMI
4319BOBOL07/L27 N12PGV 512W3G HDMI
4319BOBOL08/L28 N12PGV 512N3G HDMI
BOM P/N(JM/SJM)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDP_COMP
EDP_TXN2
EDP_TXN3
EDP_TXP2
EDP_TXP3
PEG_COMP
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P9
PEG_HTX_GRX_N0
PEG_HTX_GRX_N1
PEG_HTX_GRX_N10
PEG_HTX_GRX_N11
PEG_HTX_GRX_N12
PEG_HTX_GRX_N13
PEG_HTX_GRX_N14
PEG_HTX_GRX_N15
PEG_HTX_GRX_N2
PEG_HTX_GRX_N3
PEG_HTX_GRX_N4
PEG_HTX_GRX_N5
PEG_HTX_GRX_N6
PEG_HTX_GRX_N7
PEG_HTX_GRX_N8
PEG_HTX_GRX_N9
PEG_HTX_GRX_P0
PEG_HTX_GRX_P1
PEG_HTX_GRX_P10
PEG_HTX_GRX_P11
PEG_HTX_GRX_P12
PEG_HTX_GRX_P13
PEG_HTX_GRX_P14
PEG_HTX_GRX_P15
PEG_HTX_GRX_P2
PEG_HTX_GRX_P3
PEG_HTX_GRX_P4
PEG_HTX_GRX_P5
PEG_HTX_GRX_P6
PEG_HTX_GRX_P7
PEG_HTX_GRX_P8
PEG_HTX_GRX_P9
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N9
DMI_CTX_PRX_P015
DMI_CRX_PTX_P015
DMI_CTX_PRX_N115
DMI_CRX_PTX_N115
DMI_CTX_PRX_P315
DMI_CRX_PTX_P315
DMI_CTX_PRX_P215
DMI_CTX_PRX_N015
DMI_CRX_PTX_N315
DMI_CRX_PTX_P215
DMI_CTX_PRX_N315
DMI_CTX_PRX_P115
DMI_CRX_PTX_N015
DMI_CRX_PTX_N215
DMI_CRX_PTX_P115
DMI_CTX_PRX_N215
FDI_CTX_PRX_N015
FDI_CTX_PRX_N115
FDI_CTX_PRX_N215
FDI_CTX_PRX_N315
FDI_CTX_PRX_N415
FDI_CTX_PRX_N515
FDI_CTX_PRX_N615
FDI_CTX_PRX_N715
FDI_CTX_PRX_P015
FDI_CTX_PRX_P115
FDI_CTX_PRX_P215
FDI_CTX_PRX_P315
FDI_CTX_PRX_P415
FDI_CTX_PRX_P515
FDI_CTX_PRX_P615
FDI_CTX_PRX_P715
FDI_FSYNC015
FDI_FSYNC115
FDI_INT15
FDI_LSYNC015
FDI_LSYNC115
EDP_HPD#31
EDP_AUXP31
EDP_AUXN31
PEG_GTX_C_HRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_GTX_C_HRX_P[0..15] 22
EDP_TXP031
EDP_TXP131
EDP_TXN031
EDP_TXN131
+1.05VS_VCCP
+1.05VS_VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
2009/12/01
59
2010/12/31
4
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
2009/12/01
59
2010/12/31
4
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
2009/12/01
59
2010/12/31
4
Custom
Wednesday, February 16, 2011
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
Compal Electronics, Inc.
C28 0.1U_0402_10V7K
OPT@
C28 0.1U_0402_10V7K
OPT@
1 2
C3 0.1U_0402_10V7K
OPT@
C3 0.1U_0402_10V7K
OPT@
1 2
C14 0.1U_0402_10V7K
OPT@
C14 0.1U_0402_10V7K
OPT@
1 2
C7 0.1U_0402_10V7K
OPT@
C7 0.1U_0402_10V7K
OPT@
1 2
T1 @PAD T1 @PAD
C8 0.1U_0402_10V7K
OPT@
C8 0.1U_0402_10V7K
OPT@
1 2
C32 0.1U_0402_10V7K
OPT@
C32 0.1U_0402_10V7K
OPT@
1 2
C6 0.1U_0402_10V7K
OPT@
C6 0.1U_0402_10V7K
OPT@
1 2
C12 0.1U_0402_10V7K
OPT@
C12 0.1U_0402_10V7K
OPT@
1 2
C17 0.1U_0402_10V7K
OPT@
C17 0.1U_0402_10V7K
OPT@
1 2
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
SUYIN_100361HK988_SANDY BRIDGE
CONN@
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
SUYIN_100361HK988_SANDY BRIDGE
CONN@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21 DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI J22
PEG_ICOMPO J21
PEG_RCOMPO H22
PEG_RX#[0] K33
PEG_RX#[1] M35
PEG_RX#[2] L34
PEG_RX#[3] J35
PEG_RX#[4] J32
PEG_RX#[5] H34
PEG_RX#[6] H31
PEG_RX#[7] G33
PEG_RX#[8] G30
PEG_RX#[9] F35
PEG_RX#[10] E34
PEG_RX#[11] E32
PEG_RX#[12] D33
PEG_RX#[13] D31
PEG_RX#[14] B33
PEG_RX#[15] C32
PEG_RX[0] J33
PEG_RX[1] L35
PEG_RX[2] K34
PEG_RX[3] H35
PEG_RX[4] H32
PEG_RX[5] G34
PEG_RX[6] G31
PEG_RX[7] F33
PEG_RX[8] F30
PEG_RX[9] E35
PEG_RX[10] E33
PEG_RX[11] F32
PEG_RX[12] D34
PEG_RX[13] E31
PEG_RX[14] C33
PEG_RX[15] B32
PEG_TX#[0] M29
PEG_TX#[1] M32
PEG_TX#[2] M31
PEG_TX#[3] L32
PEG_TX#[4] L29
PEG_TX#[5] K31
PEG_TX#[6] K28
PEG_TX#[7] J30
PEG_TX#[8] J28
PEG_TX#[9] H29
PEG_TX#[10] G27
PEG_TX#[11] E29
PEG_TX#[12] F27
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25
PEG_TX[0] M28
PEG_TX[1] M33
PEG_TX[2] M30
PEG_TX[3] L31
PEG_TX[4] L28
PEG_TX[5] K30
PEG_TX[6] K27
PEG_TX[7] J29
PEG_TX[8] J27
PEG_TX[9] H28
PEG_TX[10] G28
PEG_TX[11] E28
PEG_TX[12] F28
PEG_TX[13] D27
PEG_TX[14] E26
PEG_TX[15] D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD
B16 eDP_ICOMPO
A17
T4 @PAD T4 @PAD
C15 0.1U_0402_10V7K
OPT@
C15 0.1U_0402_10V7K
OPT@
1 2
C4 0.1U_0402_10V7K
OPT@
C4 0.1U_0402_10V7K
OPT@
1 2
C29 0.1U_0402_10V7K
OPT@
C29 0.1U_0402_10V7K
OPT@
1 2
C19 0.1U_0402_10V7K
OPT@
C19 0.1U_0402_10V7K
OPT@
1 2
C11 0.1U_0402_10V7K
OPT@
C11 0.1U_0402_10V7K
OPT@
1 2
C30 0.1U_0402_10V7K
OPT@
C30 0.1U_0402_10V7K
OPT@
1 2
C5 0.1U_0402_10V7K
OPT@
C5 0.1U_0402_10V7K
OPT@
1 2
C21 0.1U_0402_10V7K
OPT@
C21 0.1U_0402_10V7K
OPT@
1 2
C25 0.1U_0402_10V7K
OPT@
C25 0.1U_0402_10V7K
OPT@
1 2
C9 0.1U_0402_10V7K
OPT@
C9 0.1U_0402_10V7K
OPT@
1 2
C1 0.1U_0402_10V7K
OPT@
C1 0.1U_0402_10V7K
OPT@
1 2
C13 0.1U_0402_10V7K
OPT@
C13 0.1U_0402_10V7K
OPT@
1 2
C27 0.1U_0402_10V7K
OPT@
C27 0.1U_0402_10V7K
OPT@
1 2
C20 0.1U_0402_10V7K
OPT@
C20 0.1U_0402_10V7K
OPT@
1 2
C23 0.1U_0402_10V7K
OPT@
C23 0.1U_0402_10V7K
OPT@
1 2
C18 0.1U_0402_10V7K
OPT@
C18 0.1U_0402_10V7K
OPT@
1 2
R1
24.9_0402_1%
R1
24.9_0402_1%
12
T3 @PAD T3 @PAD
T2 @PAD T2 @PAD
C31 0.1U_0402_10V7K
OPT@
C31 0.1U_0402_10V7K
OPT@
1 2
C22 0.1U_0402_10V7K
OPT@
C22 0.1U_0402_10V7K
OPT@
1 2
C10 0.1U_0402_10V7K
OPT@
C10 0.1U_0402_10V7K
OPT@
1 2
C26 0.1U_0402_10V7K
OPT@
C26 0.1U_0402_10V7K
OPT@
1 2
C2 0.1U_0402_10V7K
OPT@
C2 0.1U_0402_10V7K
OPT@
1 2
C24 0.1U_0402_10V7K
OPT@
C24 0.1U_0402_10V7K
OPT@
1 2
C16 0.1U_0402_10V7K
OPT@
C16 0.1U_0402_10V7K
OPT@
1 2
R2
24.9_0402_1%
R2
24.9_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BUFO_CPU_RST#
BUF_CPU_RST#
BUF_CPU_RST#
CLK_CPU_DMII#_R
CLK_CPU_DMI_R
DBRESET#_R
H_CATERR#
H_CPUPWRGD_R
H_CPUPWRGD_R
H_DRAMRST#H_PECI_ISO
H_PM_SYNC_R
H_PROCHOT#
H_PROCHOT#_R
H_THEMTRIP#_R
PLT_RST# PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF
PM_SYS_PWRGD_BUF
SM_RCOMP0
SM_RCOMP0
SM_RCOMP1
SM_RCOMP1
SM_RCOMP2
SM_RCOMP2
SUSP
XDP_DBRESET#
XDP_DBRESET#
CLK_CPU_DPLL#_R
CLK_CPU_DPLL_R
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
PM_DRAM_PWRGD15
SUSP46,53
H_PECI18,39
H_SNB_IVB#17
H_PM_SYNC15
H_THRMTRIP#18
H_CPUPWRGD18
H_PROCHOT#39,50
H_DRAMRST# 6
CLK_CPU_DMI# 14
CLK_CPU_DMI 14
XDP_DBRESET# 15
CLK_CPU_DPLL# 14
CLK_CPU_DPLL 14
PLT_RST#
17,35,38,39,44
+1.05VS_VCCP
+3VS
+1.5V_CPU_VDDQ
+3VALW
+1.05VS_VCCP
+3VS
+3VS
+1.05VS_VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5
2010/12/31
59
2009/12/01
PROCESSOR(2/7) PM,XDP,CLK
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5
2010/12/31
59
2009/12/01
PROCESSOR(2/7) PM,XDP,CLK
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5
2010/12/31
59
2009/12/01
PROCESSOR(2/7) PM,XDP,CLK
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
For eDP
Processor Pullups
Compal Electronics, Inc.
Buffered reset to CPU
DDR3 compensation Signals
Modify R05
Delete XDP
Modify R05
Delete XDP
Modify R05
Delete XDP
Modify R05
Delete XDP
R62
10K_0402_5%
R62
10K_0402_5%
1 2
R51
130_0402_5%
R51
130_0402_5%
1 2
G
D
S
Q2
2N7002H_SOT23-3
@
G
D
S
Q2
2N7002H_SOT23-3
@
2
13
R28 62_0402_5%R28 62_0402_5%
12
R38
0_0402_5%
R38
0_0402_5%
1 2
R27 0_0402_5%R27 0_0402_5%
1 2
C36
0.1U_0402_16V4Z
C36
0.1U_0402_16V4Z
12
T5 PADT5 PAD
R63
@
39_0402_5%
R63
@
39_0402_5%
12
R35 25.5_0402_1%R35 25.5_0402_1%
12
U1
SN74LVC1G07DCKR_SC70-5
U1
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y4
P5
R42
0_0402_5%
R42
0_0402_5%
1 2
T95PAD T95PAD
T96PAD T96PAD
R17 1K_0402_5%R17 1K_0402_5%
12
T97PAD T97PAD
R49
43_0402_1%
R49
43_0402_1%
1 2
U2
74AHC1G09GW_TSSOP5
U2
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O4
P5
T98PAD T98PAD
R50 0_0402_5%R50 0_0402_5%
1 2
R33 140_0402_1%R33 140_0402_1%
12
R52
@
0_0402_5%
R52
@
0_0402_5%
12
R36
56_0402_5%
R36
56_0402_5%
1 2
R48
0_0402_5%
R48
0_0402_5%
1 2
T94PAD T94PAD
R25 0_0402_5%
EDP@
R25 0_0402_5%
EDP@
1 2
R31 1K_0402_5%LVDS@R31 1K_0402_5%LVDS@
1 2
R34 10K_0402_5%R34 10K_0402_5%
12
R30 1K_0402_5%LVDS@R30 1K_0402_5%LVDS@
1 2
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
SUYIN_100361HK988_SANDY BRIDGE
CONN@
SM_RCOMP[1] A5
SM_RCOMP[2] A4
SM_DRAMRST# R8
SM_RCOMP[0] AK1
BCLK# A27
BCLK A28
DPLL_REF_CLK# A15
DPLL_REF_CLK A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY# AP29
PREQ# AP27
TCK AR26
TMS AR27
TRST# AP30
TDI AR28
TDO AP26
DBR# AL35
BPM#[0] AT28
BPM#[1] AR29
BPM#[2] AR30
BPM#[3] AT30
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R26 0_0402_5%
EDP@
R26 0_0402_5%
EDP@
1 2
R32
0_0402_5%
R32
0_0402_5%
1 2
R29 0_0402_5%R29 0_0402_5%
1 2
R44
75_0402_5%
R44
75_0402_5%
12
C35
0.1U_0402_16V4Z
C35
0.1U_0402_16V4Z
12
R61
200_0402_5%
R61
200_0402_5%
12
R37 200_0402_1%R37 200_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3_DRAMRST#_R
DDR_A_D0
DDR_A_D1
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D2
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D3
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D4
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D5
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D6
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_B_D0
DDR_B_D1
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D2
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D3
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D4
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D5
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D6
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DRAMRST_CNTRL
H_DRAMRST#
DDR_A_D[0..63]11
DDR_A_BS011
DDR_A_BS111
DDR_A_BS211
DDR_A_WE#11
DDR_A_RAS#11
DDR_A_CAS#11
M_CLK_DDR0 11
M_CLK_DDR#0 11
DDR_CKE0_DIMMA 11
M_CLK_DDR1 11
M_CLK_DDR#1 11
DDR_CKE1_DIMMA 11
DDR_CS0_DIMMA# 11
DDR_CS1_DIMMA# 11
M_ODT0 11
M_ODT1 11
DDR_A_DQS#[0..7] 11
DDR_A_DQS[0..7] 11
DDR_B_BS012
DDR_B_BS112
DDR_B_BS212
DDR_B_D[0..63]12
DDR_B_WE#12
DDR_B_RAS#12
DDR_B_CAS#12
DDR_CS3_DIMMB# 12
DDR_B_DQS[0..7] 12
DDR_B_DQS#[0..7] 12
M_CLK_DDR2 12
M_CLK_DDR#2 12
DDR_CKE2_DIMMB 12
M_CLK_DDR3 12
DDR_CS2_DIMMB# 12
M_ODT3 12
M_ODT2 12
DDR_CKE3_DIMMB 12
M_CLK_DDR#3 12
DDR3_DRAMRST# 11,12
H_DRAMRST#5
DRAMRST_CNTRL_PCH11,12,14
DDR_A_MA[0..15] 11 DDR_B_MA[0..15] 12
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(3/7) DDRIII
2009/12/01
59
2010/12/31
6
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(3/7) DDRIII
2009/12/01
59
2010/12/31
6
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(3/7) DDRIII
2009/12/01
59
2010/12/31
6
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
R68
0_0402_5%
R68
0_0402_5%
1 2
DDR SYSTEM MEMORY A
JCPU1C
SUYIN_100361HK988_SANDY BRIDGE
CONN@
DDR SYSTEM MEMORY A
JCPU1C
SUYIN_100361HK988_SANDY BRIDGE
CONN@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK[0] AB6
SA_CLK[1] AA5
SA_CLK#[0] AA6
SA_CLK#[1] AB5
SA_CKE[0] V9
SA_CKE[1] V10
SA_CS#[0] AK3
SA_CS#[1] AL3
SA_ODT[0] AH3
SA_ODT[1] AG3
SA_DQS[0] D4
SA_DQS#[0] C4
SA_DQS[1] F6
SA_DQS#[1] G6
SA_DQS[2] K3
SA_DQS#[2] J3
SA_DQS[3] N6
SA_DQS#[3] M6
SA_DQS[4] AL5
SA_DQS#[4] AL6
SA_DQS[5] AM9
SA_DQS#[5] AM8
SA_DQS[6] AR11
SA_DQS#[6] AR12
SA_DQS[7] AM14
SA_DQS#[7] AM15
SA_MA[0] AD10
SA_MA[1] W1
SA_MA[2] W2
SA_MA[3] W7
SA_MA[4] V3
SA_MA[5] V2
SA_MA[6] W3
SA_MA[7] W6
SA_MA[8] V1
SA_MA[9] W5
SA_MA[10] AD8
SA_MA[11] V4
SA_MA[12] W4
SA_MA[13] AF8
SA_MA[14] V5
SA_MA[15] V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J1
SA_DQ[20]
J5
SA_DQ[21]
J4
SA_DQ[22]
J2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ5
SA_DQ[39]
AJ6
SA_DQ[40]
AJ8
SA_DQ[41]
AK8
SA_DQ[42]
AJ9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ15
SA_DQ[63]
AH15
RSVD_TP[1] AB4
RSVD_TP[2] AA4
RSVD_TP[4] AB3
RSVD_TP[5] AA3
RSVD_TP[3] W9
RSVD_TP[6] W10
RSVD_TP[7] AG1
RSVD_TP[8] AH1
RSVD_TP[9] AG2
RSVD_TP[10] AH2
G
D
S
Q3
BSS138_NL_SOT23-3
G
D
S
Q3
BSS138_NL_SOT23-3
1
2
3
R65
1K_0402_5%
R65
1K_0402_5%
12
R64@
0_0402_5%
R64@
0_0402_5%
1 2
R67
4.99K_0402_1%
R67
4.99K_0402_1%
1 2
R66
1K_0402_5%
R66
1K_0402_5%
1 2
C37
0.047U_0402_16V4Z
C37
0.047U_0402_16V4Z
12
DDR SYSTEM MEMORY B
JCPU1D
SUYIN_100361HK988_SANDY BRIDGE
CONN@
DDR SYSTEM MEMORY B
JCPU1D
SUYIN_100361HK988_SANDY BRIDGE
CONN@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK[0] AE2
SB_CLK[1] AE1
SB_CLK#[0] AD2
SB_CLK#[1] AD1
SB_CKE[0] R9
SB_CKE[1] R10
SB_ODT[0] AE4
SB_ODT[1] AD4
SB_DQS[4] AN6
SB_DQS#[4] AN5
SB_DQS[5] AP8
SB_DQS#[5] AP9
SB_DQS[6] AK11
SB_DQS#[6] AK12
SB_DQS[7] AP14
SB_DQS#[7] AP15
SB_DQS[0] C7
SB_DQS#[0] D7
SB_DQS[1] G3
SB_DQS#[1] F3
SB_DQS[2] J6
SB_DQS#[2] K6
SB_DQS[3] M3
SB_DQS#[3] N3
SB_MA[0] AA8
SB_MA[1] T7
SB_MA[2] R7
SB_MA[3] T6
SB_MA[4] T2
SB_MA[5] T4
SB_MA[6] T3
SB_MA[7] R2
SB_MA[8] T5
SB_MA[9] R3
SB_MA[10] AB7
SB_MA[11] R1
SB_MA[12] T1
SB_MA[13] AB10
SB_MA[14] R5
SB_MA[15] R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J7
SB_DQ[17]
J8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J9
SB_DQ[21]
J10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
RSVD_TP[11] AB2
RSVD_TP[12] AA2
RSVD_TP[13] T9
RSVD_TP[14] AA1
RSVD_TP[15] AB1
RSVD_TP[16] T10
SB_CS#[0] AD3
SB_CS#[1] AE3
RSVD_TP[17] AD6
RSVD_TP[18] AE6
RSVD_TP[19] AD5
RSVD_TP[20] AE5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG2
CFG4
CFG5
CFG6
CFG7
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VCCIO_SEL
VCCIO_SEL
CFG2
CFG4
CFG5
CFG6
CFG7
SA_DIMM_VREFDQ11
SB_DIMM_VREFDQ12
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(4/7) RSVD,CFG
2009/12/01
59
2010/12/31
7
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(4/7) RSVD,CFG
2009/12/01
59
2010/12/31
7
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(4/7) RSVD,CFG
2009/12/01
59
2010/12/31
7
Custom
Wednesday, February 16, 2011
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following xxRESETB
de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
Compal Electronics, Inc.
*
*
*
AJ31 change to VAXG_VAL_SENSE
AH31 change to VSSAXG_VAL_SENSE
AJ33 change to VCC_VAL_SENSE
AH33 change to VSS_VAL_SENSE
RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VS 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
*
A19
VCCIO_SEL For 2012 CPU support
0: +1.0VS_VTT
1/NC : (Default) +1.05VS_VTT
VCCIO_SEL
Modify R02
T7 PADT7 PAD
T6 PADT6 PAD
T8 PADT8 PAD
T10PAD T10PAD
R75
10K_0402_5%@
R75
10K_0402_5%@
12
RESERVED
JCPU1E
SUYIN_100361HK988_SANDY BRIDGE
CONN@
RESERVED
JCPU1E
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34 AM33
RSVD35 AJ27
RSVD38 J16
RSVD42 AT34
RSVD39 H16
RSVD40 G16
RSVD41 AR35
RSVD43 AT33
RSVD45 AR34
RSVD56 AT2
RSVD57 AT1
RSVD58 AR1
RSVD46 B34
RSVD47 A33
RSVD48 A34
RSVD49 B35
RSVD50 C35
RSVD51 AJ32
RSVD52 AK32
RSVD30 AE7
RSVD31 AK2
RSVD28 L7
RSVD29 AG7
RSVD27
J15
RSVD16
C30 RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30 RSVD19
B29
RSVD22
A30 RSVD21
B31
RSVD23
C29
RSVD24
J20
RSVD37 T8
RSVD6
B4
RSVD7
D1
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32 W8
RSVD33 AT26
RSVD25
B18
RSVD44 AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY B1
VCC_DIE_SENSE AH27
VCCIO_SEL
A19
RSVD54 AN35
RSVD55 AM35
T9 PADT9 PAD
R70
1K_0402_1%
EDP@
R70
1K_0402_1%
EDP@
12
R76
10K_0402_5%@
R76
10K_0402_5%@
12
R74@
1K_0402_1%
R74@
1K_0402_1%
12
R71
1K_0402_1%
R71
1K_0402_1%
12
R69
1K_0402_1%
R69
1K_0402_1%
12
R73@
1K_0402_1%
R73@
1K_0402_1%
12
R72
1K_0402_1%
R72
1K_0402_1%
12
R77@
1K_0402_1%
R77@
1K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS_VCCP
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCSENSE_R
VSSIO_SENSE
VSSSENSE_R
VCCIO_SENSE 53
VCCSENSE 54
VSSSENSE 54
VR_SVID_ALRT# 54
VR_SVID_CLK 54
VR_SVID_DAT 54
VSSIO_SENSE 53
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.05VS_VCCP
+1.05VS_VCCP+1.05VS_VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(5/7) PWR,BYPASS
2009/12/01
59
2010/12/31
8
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(5/7) PWR,BYPASS
2009/12/01
59
2010/12/31
8
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PROCESSOR(5/7) PWR,BYPASS
2009/12/01
59
2010/12/31
8
Custom
Wednesday, February 16, 2011
8.5A
Place the PU
resistors
close to CPU
Compal Electronics, Inc.
Place the PU
resistors
close to VR
QC 94A
DC 53A
SV type CPU
Top side.
BoT side.
Socket Cavity
Socket Cavity
Socket Edge
Socket Edge Socket Cavity
4x 470 µFBottom Socket Edge
8x 22 µF Top Socket Cavity
8x 22 µF Top Socket Edge
10x 10 µF Bottom Socket Cavity
Modify R02
C70
22U_0805_6.3V6M
C70
22U_0805_6.3V6M
12
C46
22U_0805_6.3V6M
C46
22U_0805_6.3V6M
12
C73
22U_0805_6.3V6M
C73
22U_0805_6.3V6M
12
C67
22U_0805_6.3V6M
C67
22U_0805_6.3V6M
12
C61
@
22U_0805_6.3V6M
C61
@
22U_0805_6.3V6M
12
C60
@
22U_0805_6.3V6M
C60
@
22U_0805_6.3V6M
12
C40
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
12
C77
22U_0805_6.3V6M
C77
22U_0805_6.3V6M
12
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
SUYIN_100361HK988_SANDY BRIDGE
CONN@
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
SUYIN_100361HK988_SANDY BRIDGE
CONN@
VCC_SENSE AJ35
VSS_SENSE AJ34
VIDALERT# AJ29
VIDSCLK AJ30
VIDSOUT AJ28
VSSIO_SENSE A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1 AH13
VCCIO12 J11
VCCIO18 G12
VCCIO19 F14
VCCIO20 F13
VCCIO21 F12
VCCIO22 F11
VCCIO23 E14
VCCIO24 E12
VCCIO2 AH10
VCCIO3 AG10
VCCIO4 AC10
VCCIO5 Y10
VCCIO6 U10
VCCIO7 P10
VCCIO8 L10
VCCIO9 J14
VCCIO10 J13
VCCIO11 J12
VCCIO13 H14
VCCIO14 H12
VCCIO15 H11
VCCIO16 G14
VCCIO17 G13
VCCIO25 E11
VCCIO32 C12
VCCIO33 C11
VCCIO34 B14
VCCIO35 B12
VCCIO36 A14
VCCIO37 A13
VCCIO38 A12
VCCIO39 A11
VCCIO26 D14
VCCIO27 D13
VCCIO28 D12
VCCIO29 D11
VCCIO30 C14
VCCIO31 C13
VCCIO_SENSE B10
VCCIO40 J23
C53
22U_0805_6.3V6M
C53
22U_0805_6.3V6M
12
R86
100_0402_1%
R86
100_0402_1%
12
R82 0_0402_5%R82 0_0402_5%
1 2
C65
22U_0805_6.3V6M
C65
22U_0805_6.3V6M
12
C72
22U_0805_6.3V6M
C72
22U_0805_6.3V6M
12
C59
22U_0805_6.3V6M
C59
22U_0805_6.3V6M
12
C56
10U_0805_6.3V6M
C56
10U_0805_6.3V6M
12
C54
10U_0805_6.3V6M
C54
10U_0805_6.3V6M
12
C42
10U_0805_6.3V6M
C42
10U_0805_6.3V6M
12
C58
22U_0805_6.3V6M
C58
22U_0805_6.3V6M
12
+
C81
330U_D2_2V_Y
+
C81
330U_D2_2V_Y
12
+
C85
330U_D2_2V_Y
+
C85
330U_D2_2V_Y
12
C44
22U_0805_6.3V6M
C44
22U_0805_6.3V6M
12
C74
22U_0805_6.3V6M
C74
22U_0805_6.3V6M
12
C75
22U_0805_6.3V6M
C75
22U_0805_6.3V6M
12
C80
22U_0805_6.3V6M
C80
22U_0805_6.3V6M
12
C69
22U_0805_6.3V6M
C69
22U_0805_6.3V6M
12
C79
22U_0805_6.3V6M
C79
22U_0805_6.3V6M
12
C66
22U_0805_6.3V6M
C66
22U_0805_6.3V6M
12
R81 0_0402_5%R81 0_0402_5%
1 2
C71
22U_0805_6.3V6M
C71
22U_0805_6.3V6M
12
C55
10U_0805_6.3V6M
C55
10U_0805_6.3V6M
12
C50
22U_0805_6.3V6M
C50
22U_0805_6.3V6M
12
C43
10U_0805_6.3V6M
C43
10U_0805_6.3V6M
12
+
C63
330U_D2_2V_Y
@
+
C63
330U_D2_2V_Y
@
12
R78
130_0402_5%
R78
130_0402_5%
12
R83
100_0402_1%
R83
100_0402_1%
12
C38
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
12
R84 0_0402_5%R84 0_0402_5%
1 2
C48
22U_0805_6.3V6M
C48
22U_0805_6.3V6M
12
C47
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
12
R80
43_0402_1%
R80
43_0402_1%
1 2
C52
22U_0805_6.3V6M
C52
22U_0805_6.3V6M
12
+
C84
330U_D2_2V_Y
+
C84
330U_D2_2V_Y
12
R79
75_0402_5%
R79
75_0402_5%
12
+
C82
330U_D2_2V_Y
+
C82
330U_D2_2V_Y
12
C41
10U_0805_6.3V6M
C41
10U_0805_6.3V6M
12
C51
22U_0805_6.3V6M
C51
22U_0805_6.3V6M
12
R85 0_0402_5%R85 0_0402_5%
1 2
C68
22U_0805_6.3V6M
C68
22U_0805_6.3V6M
12
+C64
330U_D2_2V_Y
+C64
330U_D2_2V_Y
12
C45
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
12
C49
22U_0805_6.3V6M
C49
22U_0805_6.3V6M
12
C57
10U_0805_6.3V6M
C57
10U_0805_6.3V6M
12
C76
22U_0805_6.3V6M
C76
22U_0805_6.3V6M
12
+
C62
330U_D2_2V_Y
+
C62
330U_D2_2V_Y
12
C39
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
12
C78
22U_0805_6.3V6M
C78
22U_0805_6.3V6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.8VS_VCCPLL
+VCCSA
+V_SM_VREF
H_FC_C22
VCCSA_SENSE
VCCSA_SENSE 52
VCCSA_VID1 52
VCC_AXG_SENSE 54
VSS_AXG_SENSE 54
VSSSA_SENSE 52
+VCCSA
+1.5V_CPU_VDDQ
+1.8VS
+VGFX_CORE
+1.5V_CPU_VDDQ
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
9
2010/12/31
59
2009/12/01
PROCESSOR(6/7) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
9
2010/12/31
59
2009/12/01
PROCESSOR(6/7) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
9
2010/12/31
59
2009/12/01
PROCESSOR(6/7) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
+1.5V_CPU_VDDQ Source
5A
+V_SM_VREF should
have 20 mil trace width
QC 33A
DC 26A
Compal Electronics, Inc.
6A
Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
Vaxg
1.5A
Delete
9/30 DG1.5
2x 470 µF Bottom Socket Edge
2x 22 µF Top Socket Cavity
4x 22 µF Top Socket Edge
2x 470 µF Bottom Socket Cavity
4x 22 µF Bottom Socket Edge
Modify R03
Modify R04
Modify R05
+C114
330U_D2_2V_Y
+C114
330U_D2_2V_Y
12
C91
22U_0805_6.3V6M
C91
22U_0805_6.3V6M
12
+
C103
330U_D2_2V_Y
+
C103
330U_D2_2V_Y
12
C101
0.1U_0402_16V4Z
C101
0.1U_0402_16V4Z
12
+C119
330U_D2_2V_Y
+C119
330U_D2_2V_Y
12
C97
22U_0805_6.3V6M
C97
22U_0805_6.3V6M
12
C109
10U_0603_6.3V6M
C109
10U_0603_6.3V6M
12
C89
22U_0805_6.3V6M
C89
22U_0805_6.3V6M
12
R95
1K_0402_1%
R95
1K_0402_1%
12
C118
@
10U_0603_6.3V6M
C118
@
10U_0603_6.3V6M
12
C123
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
12
R97 0_0402_5%R97 0_0402_5%
1 2
C105
@
22U_0805_6.3V6M
C105
@
22U_0805_6.3V6M
12
C96
22U_0805_6.3V6M
C96
22U_0805_6.3V6M
12
R94
1K_0402_1%
R94
1K_0402_1%
12
C98
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
12
C122
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
12
R98
0_0805_5%
R98
0_0805_5%
1 2
C121
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
12
R96 0_0402_5%R96 0_0402_5%
1 2
R100@
0_0402_5%
R100@
0_0402_5%
12
C99
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
12
C93
22U_0805_6.3V6M
C93
22U_0805_6.3V6M
12
POWER
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
SUYIN_100361HK988_SANDY BRIDGE
CONN@
POWER
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
SUYIN_100361HK988_SANDY BRIDGE
CONN@
SM_VREF AL1
VSSAXG_SENSE AK34
VAXG_SENSE AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11 U4
VDDQ12 U1
VDDQ13 P7
VDDQ14 P4
VDDQ15 P1
VDDQ1 AF7
VDDQ2 AF4
VDDQ3 AF1
VDDQ4 AC7
VDDQ5 AC4
VDDQ6 AC1
VDDQ7 Y7
VDDQ8 Y4
VDDQ9 Y1
VDDQ10 U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1 M27
VCCSA2 M26
VCCSA3 L26
VCCSA4 J26
VCCSA5 J25
VCCSA6 J24
VCCSA7 H26
VCCSA8 H25
VCCSA_SENSE H23
VCCSA_VID1 C24
VCCPLL3
A2
FC_C22 C22
R99
10K_0402_5%
R99
10K_0402_5%
1 2
C117
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
12
C112
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
12
JP2@
PAD-OPEN 4x4m
JP2@
PAD-OPEN 4x4m
1 2
C108
10U_0603_6.3V6M
C108
10U_0603_6.3V6M
12
+
C120
330U_D2_2V_Y
+
C120
330U_D2_2V_Y
12
C115
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
12
C113
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
12
C92
22U_0805_6.3V6M
C92
22U_0805_6.3V6M
12
+
C102
330U_D2_2V_Y
@
+
C102
330U_D2_2V_Y
@
12
C116
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
12
C94
22U_0805_6.3V6M
C94
22U_0805_6.3V6M
12
C111
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
12
C104
@
22U_0805_6.3V6M
C104
@
22U_0805_6.3V6M
12
C100
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
12
C90
22U_0805_6.3V6M
C90
22U_0805_6.3V6M
12
C95
22U_0805_6.3V6M
C95
22U_0805_6.3V6M
12
C110
10U_0603_6.3V6M
C110
10U_0603_6.3V6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
10
2010/12/31
59
2009/12/01
PROCESSOR(7/7) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
10
2010/12/31
59
2009/12/01
PROCESSOR(7/7) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
10
2010/12/31
59
2009/12/01
PROCESSOR(7/7) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
VSS
JCPU1I
SUYIN_100361HK988_SANDY BRIDGE
CONN@
VSS
JCPU1I
SUYIN_100361HK988_SANDY BRIDGE
CONN@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234 F22
VSS235 F19
VSS236 E30
VSS237 E27
VSS238 E24
VSS239 E21
VSS240 E18
VSS241 E15
VSS242 E13
VSS243 E10
VSS244 E9
VSS245 E8
VSS246 E7
VSS247 E6
VSS248 E5
VSS249 E4
VSS250 E3
VSS251 E2
VSS252 E1
VSS253 D35
VSS254 D32
VSS255 D29
VSS256 D26
VSS257 D20
VSS258 D17
VSS259 C34
VSS260 C31
VSS261 C28
VSS262 C27
VSS263 C25
VSS264 C23
VSS265 C10
VSS266 C1
VSS267 B22
VSS268 B19
VSS269 B17
VSS270 B15
VSS271 B13
VSS272 B11
VSS273 B9
VSS274 B8
VSS275 B7
VSS276 B5
VSS277 B3
VSS278 B2
VSS279 A35
VSS280 A32
VSS281 A29
VSS282 A26
VSS283 A23
VSS284 A20
VSS285 A3
VSS
JCPU1H
SUYIN_100361HK988_SANDY BRIDGE
CONN@
VSS
JCPU1H
SUYIN_100361HK988_SANDY BRIDGE
CONN@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81 AJ22
VSS82 AJ19
VSS83 AJ16
VSS84 AJ13
VSS85 AJ10
VSS86 AJ7
VSS87 AJ4
VSS88 AJ3
VSS89 AJ2
VSS90 AJ1
VSS91 AH35
VSS92 AH34
VSS93 AH32
VSS94 AH30
VSS95 AH29
VSS96 AH28
VSS97 AH26
VSS98 AH25
VSS99 AH22
VSS100 AH19
VSS101 AH16
VSS102 AH7
VSS103 AH4
VSS104 AG9
VSS105 AG8
VSS106 AG4
VSS107 AF6
VSS108 AF5
VSS109 AF3
VSS110 AF2
VSS111 AE35
VSS112 AE34
VSS113 AE33
VSS114 AE32
VSS115 AE31
VSS116 AE30
VSS117 AE29
VSS118 AE28
VSS119 AE27
VSS120 AE26
VSS121 AE9
VSS122 AD7
VSS123 AC9
VSS124 AC8
VSS125 AC6
VSS126 AC5
VSS127 AC3
VSS128 AC2
VSS129 AB35
VSS130 AB34
VSS131 AB33
VSS132 AB32
VSS133 AB31
VSS134 AB30
VSS135 AB29
VSS136 AB28
VSS137 AB27
VSS138 AB26
VSS139 Y9
VSS140 Y8
VSS141 Y6
VSS142 Y5
VSS143 Y3
VSS144 Y2
VSS145 W35
VSS146 W34
VSS147 W33
VSS148 W32
VSS149 W31
VSS150 W30
VSS151 W29
VSS152 W28
VSS153 W27
VSS154 W26
VSS155 U9
VSS156 U8
VSS157 U6
VSS158 U5
VSS159 U3
VSS160 U2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+DIMM0_VREF
+VREF_CA
DDR3_DRAMRST#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_D0
DDR_A_D1
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D2
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D3
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D4
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D5
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D6
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0DDR_A_MA1
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14DDR_A_MA14
DDR_A_MA15
DDR_A_MA2DDR_A_MA3
DDR_A_MA4DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_RAS#
DDR_A_WE#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
D_CK_SCLK
D_CK_SDATA
M_CLK_DDR#0 M_CLK_DDR#1
M_CLK_DDR0 M_CLK_DDR1
M_ODT0
M_ODT1
DDR_A_D[0..63] 6
DDR_A_DQS[0..7] 6
DDR_A_DQS#[0..7] 6
DDR_A_MA[0..15] 6
DDR_CS1_DIMMA#6
DDR_A_CAS#6
DDR_A_WE#6
DDR_A_BS06
M_CLK_DDR#06
M_CLK_DDR06
DDR_A_BS26
DDR_CKE0_DIMMA6 DDR_CKE1_DIMMA 6
M_CLK_DDR1 6
M_CLK_DDR#1 6
DDR_A_BS1 6
DDR_A_RAS# 6
DDR_CS0_DIMMA# 6
M_ODT0 6
M_ODT1 6
D_CK_SDATA 12,14
D_CK_SCLK 12,14
DDR3_DRAMRST# 6,12
SA_DIMM_VREFDQ7
DRAMRST_CNTRL_PCH6,12,14
+1.5V
+0.75VS
+1.5V
+1.5V
+3VS
+0.75VS +0.75VS
+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
11
2010/12/31
59
2009/12/01
DDRIII DIMMA
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
11
2010/12/31
59
2009/12/01
DDRIII DIMMA
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
11
2010/12/31
59
2009/12/01
DDRIII DIMMA
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
All VREF traces should
have 10 mil trace width
Compal Electronics, Inc.
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1.203,204
<Address: 00>
DIMM_A Reserve H:4mm
M3 support
10/04 Check footprint ok
R105
1K_0402_1%
R105
1K_0402_1%
12
C144
0.1U_0402_16V4Z
C144
0.1U_0402_16V4Z
12
C142
1U_0402_6.3V6K
C142
1U_0402_6.3V6K
12
G
D
S
Q8
BSS138_NL_SOT23-3 @
G
D
S
Q8
BSS138_NL_SOT23-3 @
2
13
C141
1U_0402_6.3V6K
C141
1U_0402_6.3V6K
12
C138
2.2U_0603_6.3V6K
C138
2.2U_0603_6.3V6K
12
C129
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
12
C127
1U_0402_6.3V6K
C127
1U_0402_6.3V6K
12
C136
0.1U_0402_16V4Z
C136
0.1U_0402_16V4Z
1
2
JDIMM1
FOX_AS0A626-U4SN-7F
CONN@
JDIMM1
FOX_AS0A626-U4SN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
R114
10K_0402_5%
R114
10K_0402_5%
12
R115
10K_0402_5%
R115
10K_0402_5%
1 2
+
C137
330U_D2_2V_Y
+
C137
330U_D2_2V_Y
12
C125
0.1U_0402_16V4Z
C125
0.1U_0402_16V4Z
12
C128
1U_0402_6.3V6K
C128
1U_0402_6.3V6K
12
C139
0.1U_0402_16V4Z
C139
0.1U_0402_16V4Z
12
C135
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
12
C143
1U_0402_6.3V6K
C143
1U_0402_6.3V6K
12
C866
0.1U_0402_16V4Z
C866
0.1U_0402_16V4Z
1
2
C131
10U_0603_6.3V6M
C131
10U_0603_6.3V6M
12
C865
0.1U_0402_16V4Z
C865
0.1U_0402_16V4Z
1
2
R104
1K_0402_1%
R104
1K_0402_1%
12
C140
1U_0402_6.3V6K
C140
1U_0402_6.3V6K
12
R103
1K_0402_1%
R103
1K_0402_1%
12
C132
10U_0603_6.3V6M
C132
10U_0603_6.3V6M
12
C124
2.2U_0603_6.3V6K
C124
2.2U_0603_6.3V6K
12
C126
1U_0402_6.3V6K
C126
1U_0402_6.3V6K
12
R102
0_0402_5%
@R102
0_0402_5%
@
1 2
C145
2.2U_0603_6.3V6K
C145
2.2U_0603_6.3V6K
12
R101
1K_0402_1%
R101
1K_0402_1%
12
C130
10U_0603_6.3V6M
C130
10U_0603_6.3V6M
12
C133
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
12
C134
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+DIMM1_VREF
+VREF_CB
DDR3_DRAMRST#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_D0
DDR_B_D1
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D2
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D3
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D4
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D5
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D6
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0DDR_B_MA1
DDR_B_MA10
DDR_B_MA11DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA2DDR_B_MA3
DDR_B_MA4DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_RAS#
DDR_B_WE#
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
D_CK_SCLK
D_CK_SDATA
M_CLK_DDR#2 M_CLK_DDR#3
M_CLK_DDR2 M_CLK_DDR3
M_ODT2
M_ODT3
DDR_B_D[0..63] 6
DDR_B_DQS[0..7] 6
DDR_B_DQS#[0..7] 6
DDR_B_MA[0..15] 6
DDR_CS3_DIMMB#6
DDR_B_CAS#6
DDR_B_WE#6
DDR_B_BS06
M_CLK_DDR#26
M_CLK_DDR26
DDR_CKE2_DIMMB6
DDR_B_BS26
DDR3_DRAMRST# 6,11
D_CK_SDATA 11,14
D_CK_SCLK 11,14
M_CLK_DDR#3 6
DDR_B_BS1 6
DDR_B_RAS# 6
DDR_CS2_DIMMB# 6
M_ODT2 6
M_ODT3 6
M_CLK_DDR3 6
DDR_CKE3_DIMMB 6
SB_DIMM_VREFDQ7
DRAMRST_CNTRL_PCH6,11,14
+1.5V
+1.5V
+1.5V
+0.75VS
+3VS
+0.75VS
+3VS
+1.5V
+0.75VS
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
DDRIII DIMMB
2009/12/01
59
2010/12/31
12
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
DDRIII DIMMB
2009/12/01
59
2010/12/31
12
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
DDRIII DIMMB
2009/12/01
59
2010/12/31
12
Custom
Wednesday, February 16, 2011
All VREF traces should
have 10 mil trace width
Compal Electronics, Inc.
Layout Note:
Place near JDIMM2.203,204
Layout Note:
Place near JDIMM2
<Address: 01>
DIMM_B Reverse type H:4mm
M3 support
10/04 Check footprint ok
modify R03
R119
1K_0402_1%
R119
1K_0402_1%
12
C164
2.2U_0603_6.3V6K
C164
2.2U_0603_6.3V6K
12
C147
0.1U_0402_16V4Z
C147
0.1U_0402_16V4Z
12
C161
1U_0402_6.3V6K
C161
1U_0402_6.3V6K
12
C153
10U_0603_6.3V6M
C153
10U_0603_6.3V6M
12
C166
0.1U_0402_16V4Z
C166
0.1U_0402_16V4Z
12
C156
10U_0603_6.3V6M
C156
10U_0603_6.3V6M
12
R116
0_0402_5%
@R116
0_0402_5%
@
1 2
C146
2.2U_0603_6.3V6K
C146
2.2U_0603_6.3V6K
12
C154
10U_0603_6.3V6M
C154
10U_0603_6.3V6M
12
JDIMM2
TYCO_2-2013287-1
CONN@
JDIMM2
TYCO_2-2013287-1
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C160
1U_0402_6.3V6K
C160
1U_0402_6.3V6K
12
+
C159
@
330U_D2_2V_Y
+
C159
@
330U_D2_2V_Y
12
R117
1K_0402_1%
R117
1K_0402_1%
12
C148
1U_0402_6.3V6K
C148
1U_0402_6.3V6K
12
C157
10U_0603_6.3V6M
C157
10U_0603_6.3V6M
12
R120
1K_0402_1%
R120
1K_0402_1%
12
C155
10U_0603_6.3V6M
C155
10U_0603_6.3V6M
12
R129
10K_0402_5%
R129
10K_0402_5%
12
C149
1U_0402_6.3V6K
C149
1U_0402_6.3V6K
12
C152
10U_0603_6.3V6M
C152
10U_0603_6.3V6M
12
C165
0.1U_0402_16V4Z
C165
0.1U_0402_16V4Z
12
C162
1U_0402_6.3V6K
C162
1U_0402_6.3V6K
12
C151
1U_0402_6.3V6K
C151
1U_0402_6.3V6K
12
C167
2.2U_0603_6.3V6K
C167
2.2U_0603_6.3V6K
12
C158
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
12
R118
1K_0402_1%
R118
1K_0402_1%
12
C868
0.1U_0402_16V4Z
C868
0.1U_0402_16V4Z
12
R130
10K_0402_5%
R130
10K_0402_5%
12
G
D
S
Q9
BSS138_NL_SOT23-3 @
G
D
S
Q9
BSS138_NL_SOT23-3 @
2
13
C150
1U_0402_6.3V6K
C150
1U_0402_6.3V6K
12
C867
0.1U_0402_16V4Z
C867
0.1U_0402_16V4Z
12
C163
1U_0402_6.3V6K
C163
1U_0402_6.3V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3V_DSW_SPI
HDA_BIT_CLK
HDA_BIT_CLK
HDA_RST#
HDA_RST#
HDA_SDIN0
HDA_SDOUT
HDA_SDOUT_R
HDA_SDOUT
HDA_SPKR
HDA_SPKR
HDA_SYNC
HDA_SYNC
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PCH_GPIO19
PCH_GPIO21
PCH_INTVRMEN
PCH_INTVRMEN
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_RTCRST#
PCH_RTCX1
PCH_RTCX1
PCH_RTCX2
PCH_RTCX2
PCH_SATALED#
PCH_SATALED#
PCH_SPI_CLK PCH_SPI_CLK PCH_SPI_CLK_R
PCH_SPI_CLK_R
PCH_SPI_CS#
PCH_SPI_CS# PCH_SPI_CS#_R
PCH_SPI_HOLD#
PCH_SPI_HOLD#
PCH_SPI_SI
PCH_SPI_SI PCH_SPI_SI_R
PCH_SPI_SO
PCH_SPI_SO
PCH_SPI_SO_R
PCH_SPI_SO_R
PCH_SPI_WP#
PCH_SPI_WP#
PCH_SRTCRST#
RBIAS_SATA3
SATA3_COMP
SATA_COMP
SERIRQ
SERIRQ
SM_INTRUDER#
SM_INTRUDER#
PCH_GPIO21
HDA_SDOUT_R HDA_SDOUTHDA_SYNCHDA_SYNC_R
HDA_SYNC_R
PCH_GPIO19
+RTCCONN_R
HDA_SPKR42
HDA_SDIN042
SERIRQ 39
SATA_PRX_DTX_P0 34
SATA_PTX_DRX_N0 34
SATA_PTX_DRX_P0 34
SATA_PRX_DTX_N0 34
LPC_AD0 39
LPC_AD1 39
LPC_AD2 39
LPC_AD3 39
LPC_FRAME# 39
HDA_SYNC_AUDIO42
HDA_SDOUT_AUDIO42
HDA_RST_AUDIO#42
HDA_BITCLK_AUDIO42
PCH_SATALED# 41
HDA_SDO39 SATA_PRX_DTX_P2 34
SATA_PTX_DRX_N2 34
SATA_PTX_DRX_P2 34
SATA_PRX_DTX_N2 34
+RTCVCC
+RTCVCC
+1.05VS_PCH
+1.05VS_PCH
+3VS
+3VS
+3VS
+3VALW_PCH
+3VALW_PCH
+3VS
+3VS+3VS
+RTCCONN
+CHGRTC
+RTCVCC
+RTCCONN
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
13
2010/12/31
59
2009/12/01
PCH (1/9) SATA,HDA,SPI, LPC, XDP
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
13
2010/12/31
59
2009/12/01
PCH (1/9) SATA,HDA,SPI, LPC, XDP
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
13
2010/12/31
59
2009/12/01
PCH (1/9) SATA,HDA,SPI, LPC, XDP
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
SPI ROM FOR ME ( 4MByte )
ME
CMOS
HDD
Compal Electronics, Inc.
Please short PJP35
If use SPI programmer,
R146 should be open
(Normal is pop)
H Integrated VRM enable
L Integrated VRM disable
INTVRMEN
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
*Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
Reserve for EMI please close to UH1
*
P/N:SA00003K800
(INTVRMEN should always be pull high.)
Prevent back drive issue.
ME debug mode,this signal has a weak internal PD
HDA_SDO
No PCH XDP
Delete JTAG_TMS,PCH_JTAG_TDI,JTAG_TD0
Prevent back drive issue.
9/29 DG1.5
Debug Port DG 1.2 PH 4.7K +3VS
20mil
20mil
20101011 add
Modify 03
Link CIS symbol D44
ODD
BAV70W_SOT323-3
D44
BAV70W_SOT323-3
D44
2
3
1
T84 @
PAD T84 @
PAD
T85 @
PAD T85 @
PAD
JBATT1
SUYIN_060003HA002G202ZL
CONN@
JBATT1
SUYIN_060003HA002G202ZL
CONN@
+1
-
2
R747
1M_0402_5%
R747
1M_0402_5%
12
C172
0.1U_0402_16V4Z
C172
0.1U_0402_16V4Z
1 2
R131 10M_0402_5%R131 10M_0402_5%
1 2
R783 4.7K_0402_5%R783 4.7K_0402_5%
12
G
D
S
Q10
BSS138_NL_SOT23-3
G
D
S
Q10
BSS138_NL_SOT23-3
1
2
3
R147
33_0402_5%
R147
33_0402_5%
1 2
R139 10K_0402_5%R139 10K_0402_5%
12
R153
51_0402_5%
R153
51_0402_5%
12
R132 1M_0402_5%R132 1M_0402_5%
1 2
C168
18P_0402_50V8J
C168
18P_0402_50V8J
12
R149 0_0402_5%R149 0_0402_5%
1 2
R145
0_0402_5%
R145
0_0402_5%
1 2
Y1
32.768KHZ_12.5PF_Q13MC14610002
Y1
32.768KHZ_12.5PF_Q13MC14610002
OSC 1
NC
2
NC
3OSC 4
G
D
S
Q65
BSS138_NL_SOT23-3
G
D
S
Q65
BSS138_NL_SOT23-3
1
2
3
R795
1K_0402_5%
R795
1K_0402_5%
1 2
C171
1U_0603_10V4Z
C171
1U_0603_10V4Z
12
R148
33_0402_5%
R148
33_0402_5%
1 2
R141
0_0402_5%
R141
0_0402_5%
12
C173@
22P_0402_50V8J
C173@
22P_0402_50V8J
12
JCMOS1
SHORT PADS
JCMOS1
SHORT PADS
12
T86 @
PAD T86 @
PAD
R144 3.3K_0402_5%R144 3.3K_0402_5%
1 2
R143 1K_0402_5%R143 1K_0402_5%
12
R142 3.3K_0402_5%R142 3.3K_0402_5%
1 2
R158@
33_0402_5%
R158@
33_0402_5%
1 2
C859
0.1U_0402_16V4Z
<BOM Structure>
C859
0.1U_0402_16V4Z
<BOM Structure>
1
2
R146
0_0402_5%
R146
0_0402_5%
1 2
R133 330K_0402_5%R133 330K_0402_5%
1 2
R134 10K_0402_5%R134 10K_0402_5%
12
R140@
1K_0402_5%
R140@
1K_0402_5%
12
R137 20K_0402_5%R137 20K_0402_5%
1 2
R162 750_0402_1%R162 750_0402_1%
1 2
R136 10K_0402_5%R136 10K_0402_5%
12
R157
49.9_0402_1%
R157
49.9_0402_1%
1 2
JME1
SHORT PADS
JME1
SHORT PADS
12
R135 @1K_0402_5%R135 @1K_0402_5%
1 2
R151
33_0402_5%
R151
33_0402_5%
1 2
R155
33_0402_5%
R155
33_0402_5%
1 2
R152@
0_0402_5%
R152@
0_0402_5%
1 2
R150 0_0402_5%R150 0_0402_5%
1 2
R138 20K_0402_5%R138 20K_0402_5%
1 2
R154 0_0402_5%R154 0_0402_5%
1 2
C169
18P_0402_50V8J
C169
18P_0402_50V8J
12
C170
1U_0603_10V4Z
C170
1U_0603_10V4Z
12
R156
37.4_0402_1%
R156
37.4_0402_1%
1 2
R768@
0_0402_5%
R768@
0_0402_5%
1 2
RTCIHDA
SATA LPC
SPI JTAG
SATA 6G
U3A
COUGARPOINT_FCBGA989~D
RTCIHDA
SATA LPC
SPI JTAG
SATA 6G
U3A
COUGARPOINT_FCBGA989~D
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED# P3
FWH0 / LAD0 C38
FWH1 / LAD1 A38
FWH2 / LAD2 B37
FWH3 / LAD3 C37
LDRQ1# / GPIO23 K36
FWH4 / LFRAME# D36
LDRQ0# E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN# / GPIO33
C36
HDA_DOCK_RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN AM3
SATA0RXP AM1
SATA0TXN AP7
SATA0TXP AP5
SATA1RXN AM10
SATA1RXP AM8
SATA1TXN AP11
SATA1TXP AP10
SATA2RXN AD7
SATA2RXP AD5
SATA2TXN AH5
SATA2TXP AH4
SATA3RXN AB8
SATA3RXP AB10
SATA3TXN AF3
SATA3TXP AF1
SATA4RXN Y7
SATA4RXP Y5
SATA4TXN AD3
SATA4TXP AD1
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
SATA5TXP AB1
SATAICOMPI Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21 V14
SATA1GP / GPIO19 P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ V5
SPKR
T10
SATAICOMPO Y11
SATA3COMPI AB13
SATA3RCOMPO AB12
SATA3RBIAS AH1
U4
MX25L3205DM2I-12G SOP 8P
U4
MX25L3205DM2I-12G SOP 8P
S
1
Q2
W
3
VSS 4
D
5
C
6
HOLD
7
VCC
8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLKIN_DMI2
CLKIN_DMI2
CLKIN_DMI2#
CLKIN_DMI2#
CLK_BCLK_ITP
CLK_BCLK_ITP#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI#
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M#
CLK_BUF_ICH_14M
CLK_BUF_ICH_14M
CLK_BUF_ICH_14M
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA#
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_CPU_DPLL
CLK_CPU_DPLL#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_FLEX0
CLK_27M_TCLK_R
CLK_LAN
CLK_LAN#
CLK_MINI1
CLK_MINI1#
CLK_CARD
CLK_CARD#
CLK_PCI_LPBACK
CLK_PCI_LPBACK
CLK_USB30
CLK_USB30#
CLK_VGA
CLK_VGA#
DRAMRST_CNTRL_PCH
DRAMRST_CNTRL_PCH
D_CK_SCLK
D_CK_SDATA
EC_SMB_CK2
EC_SMB_DA2
LID_SW_OUT#
LID_SW_OUT#
PCH_GPIO18
PCH_GPIO18
PCH_GPIO20
PCH_GPIO20
PCH_GPIO25
PCH_GPIO25
PCH_GPIO26
PCH_GPIO26
PCH_GPIO44
PCH_GPIO45
PCH_GPIO45
PCH_GPIO46
PCH_GPIO46
PEG_CLKREQ#_R
PCH_GPIO47
PCH_GPIO73
PCH_GPIO73
PCH_GPIO74
PCH_GPIO74
PCH_SMBCLK
PCH_SMBCLK
PCH_SMBCLK
PCH_SMBDATA
PCH_SMBDATA
PCH_SMBDATA
PCH_SML1CLK
PCH_SML1CLK
PCH_SML1CLK
PCH_SML1DATA
PCH_SML1DATA
PCH_SML1DATA
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_P3
PCIE_PTX_DRX_P4
PCH_GPIO47
XCLK_RCOMP
XTAL25_IN
XTAL25_IN
XTAL25_OUT
XTAL25_OUT
DGPU_PRSNT#
DGPU_PRSNT#
PEG_CLKREQ#_R
PCH_GPIO44
CLK_CPU_DMI# 5
CLK_CPU_DMI 5
CLK_CPU_DPLL# 5
CLK_CPU_DPLL 5
PCIE_PRX_DTX_N135
PCIE_PTX_C_DRX_N135
PCIE_PRX_DTX_P135
PCIE_PTX_C_DRX_P135
PCIE_PRX_DTX_N237
PCIE_PRX_DTX_P237
PCIE_PTX_C_DRX_N237
PCIE_PTX_C_DRX_P237
CLK_CPU_ITP#
CLK_CPU_ITP
CLK_PCIE_MINI1#37
CLK_PCIE_MINI137
MINI1_CLKREQ#37
LID_SW_OUT# 39
CLK_PCI_LPBACK 17
PCH_SMBCLK 37
PCH_SMBDATA 37
DRAMRST_CNTRL_PCH 6,11,12
EC_SMB_CK2 22,39
EC_SMB_DA2 22,39
CLK_PCIE_LAN#35
CLK_PCIE_LAN35
LAN_CLKREQ#35
CLK_PEG_VGA#22
CLK_PEG_VGA22
CLK_PCIE_USB30#44
CLK_PCIE_USB3044
USB30_CLKREQ#44
PCIE_PRX_DTX_N444
PCIE_PRX_DTX_P444
PCIE_PTX_C_DRX_N444
PCIE_PTX_C_DRX_P444
PCIE_PRX_DTX_N338
PCIE_PRX_DTX_P338
PCIE_PTX_C_DRX_N338
PCIE_PTX_C_DRX_P338
CLK_PCIE_CARD#38
CLK_PCIE_CARD38
CARD_CLKREQ#38
D_CK_SDATA 11,12
D_CK_SCLK 11,12
PEG_CLKREQ# 22
VGA_ON 17,25,46,55
CLK_27M_TCLK 22
+1.05VS_PCH
+3VALW_PCH
+3VS
+3VS
+3VALW_PCH
+3VS
+3VS
+3VS
+3VS
+3VALW_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (2/9) PCIE, SMBUS, CLK
2009/12/01
59
2010/12/31
14
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (2/9) PCIE, SMBUS, CLK
2009/12/01
59
2010/12/31
14
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (2/9) PCIE, SMBUS, CLK
2009/12/01
59
2010/12/31
14
Custom
Wednesday, February 16, 2011
PCIE LAN
Mini Card
Compal Electronics, Inc.
Reserve for EMI please close to U3
120MHz for eDP.
Mini Card
USB3.0
PCIE LAN
USB3.0
Card Reader
Card Reader
Pull up at EC side.
GPIO67
0
1
OPTIMUS
DGPU_PRSNT#
UMA
Pull high @ VGA side
for safe
For DDR
Modify R02
C181 0.1U_0402_10V7KC181 0.1U_0402_10V7K
1 2
R206 0_0402_5%R206 0_0402_5%
1 2
R187 0_0402_5%R187 0_0402_5%
12
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U3B
COUGARPOINT_FCBGA989~D
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U3B
COUGARPOINT_FCBGA989~D
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_DMI2_N BJ30
CLKIN_DMI2_P BG30
CLKIN_DMI_N BF18
CLKIN_DMI_P BE18
CLKIN_DOT_96N G24
CLKIN_DOT_96P E24
CLKIN_SATA_N / CKSSCD_N AK7
CLKIN_SATA_P / CKSSCD_P AK5
XTAL25_IN V47
XTAL25_OUT V49
REFCLK14IN K45
CLKIN_PCILOOPBACK H45
CLKOUT_PEG_A_N AB37
CLKOUT_PEG_A_P AB38
PEG_A_CLKRQ# / GPIO47 M10
PCIECLKRQ0# / GPIO73
J2
PCIECLKRQ1# / GPIO18
M1
PCIECLKRQ2# / GPIO20
V10
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
L12
PCIECLKRQ5# / GPIO44
L14
CLKOUTFLEX0 / GPIO64 K43
CLKOUTFLEX1 / GPIO65 F47
CLKOUTFLEX2 / GPIO66 H47
CLKOUTFLEX3 / GPIO67 K49
CLKOUT_DMI_N AV22
CLKOUT_DMI_P AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40 CLKOUT_PEG_B_N
AB42
XCLK_RCOMP Y47
CLKOUT_DP_P / CLKOUT_BCLK1_P AM13
CLKOUT_DP_N / CLKOUT_BCLK1_N AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7# / GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK14
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AK13
SMBALERT# / GPIO11 E12
SMBCLK H14
SMBDATA C9
SML0ALERT# / GPIO60 A12
SML0CLK C8
SML0DATA G12
SML1ALERT# / PCHHOT# / GPIO74 C13
SML1CLK / GPIO58 E14
SML1DATA / GPIO75 M16
CL_CLK1 M7
CL_DATA1 T11
CL_RST1# P10
PCIECLKRQ6# / GPIO45
T13
R190 0_0402_5%R190 0_0402_5%
12
R207 10K_0402_5%R207 10K_0402_5%
1 2
R216
10K_0402_5%
R216
10K_0402_5%
12
R185 0_0402_5%R185 0_0402_5%
12
R221
2.2K_0402_5%
@
R221
2.2K_0402_5%
@
12
R204 10K_0402_5%R204 10K_0402_5%
1 2
R209 1M_0402_5%R209 1M_0402_5%
1 2
G
D
S
Q13
2N7002H_SOT23-3
OPT@
G
D
S
Q13
2N7002H_SOT23-3
OPT@
2
1 3
R215@
33_0402_5%
R215@
33_0402_5%
12
R181 10K_0402_5%R181 10K_0402_5%
12
R179
4.7K_0402_5%
R179
4.7K_0402_5%
1 2
R192 0_0402_5%R192 0_0402_5%
1 2
R199 10K_0402_5%R199 10K_0402_5%
1 2
R214
10K_0402_5%
UMAO@
R214
10K_0402_5%
UMAO@
12
R186 0_0402_5%R186 0_0402_5%
12
R219@
33_0402_5%
R219@
33_0402_5%
12
R212 0_0402_5%
@
R212 0_0402_5%
@12
C186@
22P_0402_50V8J
C186@
22P_0402_50V8J
1 2
R168 2.2K_0402_5%R168 2.2K_0402_5%
1 2
Q12A
DMN66D0LDW-7_SOT363-6
Q12A
DMN66D0LDW-7_SOT363-6
6 1
2
R178 10K_0402_5%R178 10K_0402_5%
12
R184 10K_0402_5%R184 10K_0402_5%
12
R167 1K_0402_5%R167 1K_0402_5%
1 2
C179 0.1U_0402_10V7KC179 0.1U_0402_10V7K
1 2
R188 0_0402_5%R188 0_0402_5%
12
Q12B
DMN66D0LDW-7_SOT363-6
Q12B
DMN66D0LDW-7_SOT363-6
3 4
5
R197 10K_0402_5%R197 10K_0402_5%
1 2
R201 10K_0402_5%R201 10K_0402_5%
1 2
C180 0.1U_0402_10V7KC180 0.1U_0402_10V7K
1 2
R203 10K_0402_5%R203 10K_0402_5%
1 2
Y2
25MHZ_12PF_X5H025000DC1H-H
Y2
25MHZ_12PF_X5H025000DC1H-H
12
C183
12P_0402_50V8J
C183
12P_0402_50V8J
12
R170 10K_0402_5%R170 10K_0402_5%
1 2
R222
2.2K_0402_5%
@
R222
2.2K_0402_5%
@
12
C176 0.1U_0402_10V7KC176 0.1U_0402_10V7K
1 2
R189 0_0402_5%R189 0_0402_5%
12
R193 0_0402_5%R193 0_0402_5%
1 2
R169 2.2K_0402_5%R169 2.2K_0402_5%
1 2
C175 0.1U_0402_10V7KC175 0.1U_0402_10V7K
1 2
R196 10K_0402_5%R196 10K_0402_5%
1 2
C177 0.1U_0402_10V7KC177 0.1U_0402_10V7K
1 2
C184
12P_0402_50V8J
C184
12P_0402_50V8J
12
R173 10K_0402_5%R173 10K_0402_5%
1 2
R174 10K_0402_5%R174 10K_0402_5%
1 2
C182 0.1U_0402_10V7KC182 0.1U_0402_10V7K
1 2
T12
@PAD
T12
@PAD
R182 10K_0402_5%R182 10K_0402_5%
12
R208
90.9_0402_1%
R208
90.9_0402_1%
1 2
R177
4.7K_0402_5%
R177
4.7K_0402_5%
1 2
R191 0_0402_5%R191 0_0402_5%
1 2
R175 10K_0402_5%R175 10K_0402_5%
12
R220
0_0402_5%
OPT@
R220
0_0402_5%
OPT@
1 2
R171 2.2K_0402_5%R171 2.2K_0402_5%
1 2
R194 0_0402_5%R194 0_0402_5%
1 2
C185@
22P_0402_50V8J
C185@
22P_0402_50V8J
1 2
R200 10K_0402_5%R200 10K_0402_5%
1 2
R218
10K_0402_5%
OPT@
R218
10K_0402_5%
OPT@
1 2
R205 0_0402_5%R205 0_0402_5%
1 2
Q11A
DMN66D0LDW-7_SOT363-6
Q11A
DMN66D0LDW-7_SOT363-6
6 1
2
R172 2.2K_0402_5%R172 2.2K_0402_5%
1 2
R195 0_0402_5%R195 0_0402_5%
1 2
R198 0_0402_5%R198 0_0402_5%
1 2
R213 0_0402_5%
@
R213 0_0402_5%
@12
R176 10K_0402_5%R176 10K_0402_5%
12
R180 10K_0402_5%R180 10K_0402_5%
12
R183 10K_0402_5%R183 10K_0402_5%
12
R202 10K_0402_5%R202 10K_0402_5%
1 2
R748 22_0402_5%@R748 22_0402_5%@
1 2
C178 0.1U_0402_10V7KC178 0.1U_0402_10V7K
1 2
Q11B
DMN66D0LDW-7_SOT363-6
Q11B
DMN66D0LDW-7_SOT363-6
3 4
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_IRCOMP
DSWODVREN
DSWODVREN
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
H_PM_SYNC
PBTN_OUT#_R
PCH_ACIN
PCH_ACIN PCH_GPIO29
PCH_GPIO32
PCH_GPIO72
PCH_GPIO72
PCH_PWROK
PCH_RSMRST#_R
PCH_RSMRST#_R
PCH_RSMRST#_R
PM_DRAM_PWRGD
PM_DRAM_PWRGD
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
RBIAS_CPY
RI#
RI#
SUSACK#_R
SUSCLK
SUSWARN#_R
SUS_STAT#
SYS_PWROK
SYS_PWROK
SYS_PWROKSYS_PWROK
WAKE#XDP_DBRESET#_R
PCH_PWROK_R PCH_GPIO29
WAKE#
SUSWARN#_R
PCH_GPIO32
PM_SLP_A#
DMI_CTX_PRX_N04
DMI_CRX_PTX_N24
DMI_CTX_PRX_N14
DMI_CTX_PRX_N34
DMI_CTX_PRX_N24
DMI_CTX_PRX_P04
DMI_CTX_PRX_P14
DMI_CTX_PRX_P34
DMI_CTX_PRX_P24
DMI_CRX_PTX_N34
DMI_CRX_PTX_N14
DMI_CRX_PTX_N04
DMI_CRX_PTX_P24
DMI_CRX_PTX_P34
DMI_CRX_PTX_P14
DMI_CRX_PTX_P04
FDI_CTX_PRX_N0 4
FDI_CTX_PRX_N1 4
FDI_CTX_PRX_N2 4
FDI_CTX_PRX_N3 4
FDI_CTX_PRX_N4 4
FDI_CTX_PRX_N5 4
FDI_CTX_PRX_N6 4
FDI_CTX_PRX_N7 4
FDI_CTX_PRX_P0 4
FDI_CTX_PRX_P1 4
FDI_CTX_PRX_P2 4
FDI_CTX_PRX_P3 4
FDI_CTX_PRX_P4 4
FDI_CTX_PRX_P5 4
FDI_CTX_PRX_P6 4
FDI_CTX_PRX_P7 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_FSYNC0 4
FDI_INT 4
FDI_LSYNC1 4
XDP_DBRESET#5
PM_DRAM_PWRGD5
PCH_RSMRST#39
PBTN_OUT#39
ACIN39,46,48
PCH_PCIE_WAKE# 35,37,44
H_PM_SYNC 5
PM_SLP_S3# 39
PM_SLP_S4# 39
PM_SLP_S5# 39
SUSCLK_R 39
PCH_PWROK39
VGATE54
SYS_PWROK +1.05VS_PCH
+RTCVCC
+3VALW_PCH
+3VS
+3VS
+3VALW_PCH
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
15
2010/12/31
59
2009/12/01
PCH (3/9) DMI,FDI,PM,
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
15
2010/12/31
59
2009/12/01
PCH (3/9) DMI,FDI,PM,
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
15
2010/12/31
59
2009/12/01
PCH (3/9) DMI,FDI,PM,
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
4mil width and place
within 500mil of the
PCH
Can be left NC when IAMT is not
support on the platfrom
DSWODVREN - On Die DSW VR Enable
H Enable
L Disable
*
Compal Electronics, Inc.
not support Deep S4,S5 can NC
PCH EDS1.2 P.74
not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)
Modify R02
Modify R02
Delete R231 between SUSACK#_R and SUSWARN#_R
T91 PADT91 PAD
R230
0_0402_5%
R230
0_0402_5%
1 2
R236 10K_0402_5%
@
R236 10K_0402_5%
@
1 2
R232 10K_0402_5%R232 10K_0402_5%
1 2
D2
RB751V-40_SOD323-2
D2
RB751V-40_SOD323-2
1 2
T17 PADT17 PAD
T90PAD T90PAD
R234 10K_0402_5%R234 10K_0402_5%
1 2
R750 8.2K_0402_5%R750 8.2K_0402_5%
1 2
T19 PADT19 PAD
R227 750_0402_1%R227 750_0402_1%
1 2
T15 PADT15 PAD
U5
MC74VHC1G08DFT2G_SC70-5
@
U5
MC74VHC1G08DFT2G_SC70-5
@
IN1
1
IN2
2
GND
3
OUT 4
VCC 5
R244 10K_0402_5%R244 10K_0402_5%
12
R242 10K_0402_5%R242 10K_0402_5%
12
R226 49.9_0402_1%R226 49.9_0402_1%
1 2
R225 @330K_0402_5%R225 @330K_0402_5%
12
R239 200_0402_5%R239 200_0402_5%
12
R235
0_0402_5%
R235
0_0402_5%
12
R223 0_0402_5%R223 0_0402_5%
1 2
R224 330K_0402_5%R224 330K_0402_5%
12
R240 10K_0402_5%R240 10K_0402_5%
12
R233 0_0402_5%R233 0_0402_5%
1 2
T18 PADT18 PAD
T16 PADT16 PAD
DMI
FDI
System Power Management
U3C
COUGARPOINT_FCBGA989~D
DMI
FDI
System Power Management
U3C
COUGARPOINT_FCBGA989~D
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0 BJ14
FDI_RXN1 AY14
FDI_RXN2 BE14
FDI_RXN3 BH13
FDI_RXN4 BC12
FDI_RXN5 BJ12
FDI_RXN6 BG10
FDI_RXN7 BG9
FDI_RXP0 BG14
FDI_RXP1 BB14
FDI_RXP2 BF14
FDI_RXP3 BG13
FDI_RXP4 BE12
FDI_RXP5 BG12
FDI_RXP6 BJ10
FDI_RXP7 BH9
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
FDI_INT AW16
PMSYNCH AP14
SLP_SUS# G16
SLP_S3# F4
SLP_S4# H4
SLP_S5# / GPIO63 D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE# B9
SUS_STAT# / GPIO61 G8
SUSCLK / GPIO62 N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32 N3
SUSWARN# / SUS_PWR_DN_ACK / GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29 K14
APWROK
L10
DPWROK E22
DMI2RBIAS
BH21
SLP_A# G10
DSWVRMEN A18
SUSACK#
C12
R228 10K_0402_5%R228 10K_0402_5%
12
R238 0_0402_5%R238 0_0402_5%
1 2
R243 10K_0402_5%R243 10K_0402_5%
12
R237 0_0402_5%R237 0_0402_5%
1 2
R229 0_0402_5%R229 0_0402_5%
1 2
R241 200K_0402_5%R241 200K_0402_5%
12
T20 PADT20 PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_IREF
CTRL_CLK
CTRL_CLK
CTRL_DATA
CTRL_DATA
ENBKL
IGPU_BKLT_EN
IGPU_BKLT_EN
LVDS_IBG
LVD_VREF
PCH_CRT_B
PCH_CRT_B
PCH_CRT_CLK
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_DATA
PCH_CRT_G
PCH_CRT_G
PCH_CRT_HSYNC
PCH_CRT_R
PCH_CRT_R
PCH_CRT_VSYNC
PCH_DPB_HPD
PCH_DPB_N0
PCH_DPB_N1
PCH_DPB_N2
PCH_DPB_N3
PCH_DPB_P0
PCH_DPB_P1
PCH_DPB_P2
PCH_DPB_P3
PCH_TXCLK+
PCH_TXCLK-
PCH_TXOUT0+
PCH_TXOUT0-
PCH_TXOUT1+
PCH_TXOUT1-
PCH_TXOUT2+
PCH_TXOUT2-
SDVO_SCLK
SDVO_SDATA
PCH_LCD_CLK
PCH_LCD_DATA
SDVO_SCLK
SDVO_SDATA
SDVO_SCLK 33
SDVO_SDATA 33
PCH_DPB_HPD 33
PCH_TXCLK-31
PCH_TXCLK+31
PCH_TXOUT0-31
PCH_TXOUT1-31
PCH_TXOUT2-31
PCH_TXOUT0+31
PCH_TXOUT1+31
PCH_TXOUT2+31
PCH_CRT_DATA32
PCH_CRT_R32
PCH_CRT_G32
PCH_CRT_B32
PCH_ENVDD31
DPST_PWM31
PCH_LCD_DATA31
PCH_LCD_CLK31
PCH_CRT_HSYNC32
PCH_CRT_VSYNC32
PCH_CRT_CLK32
PCH_DPB_N1 33
PCH_DPB_N3 33
PCH_DPB_P1 33
PCH_DPB_P3 33
PCH_DPB_N0 33
PCH_DPB_P0 33
PCH_DPB_N2 33
PCH_DPB_P2 33
ENBKL39
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (4/9) LVDS,CRT,DP,HDMI
2009/12/01
59
2010/12/31
16
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (4/9) LVDS,CRT,DP,HDMI
2009/12/01
59
2010/12/31
16
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (4/9) LVDS,CRT,DP,HDMI
2009/12/01
59
2010/12/31
16
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
R470 2.2K_0402_5%R470 2.2K_0402_5%
1 2
R246
100K_0402_5%
R246
100K_0402_5%
1 2
C484@
10P_0402_50V8J
C484@
10P_0402_50V8J
12
R249
0_0402_5%
R249
0_0402_5%
12
C485@
10P_0402_50V8J
C485@
10P_0402_50V8J
12
R256
1K_0402_0.5%
R256
1K_0402_0.5%
12
R252 2.2K_0402_5%R252 2.2K_0402_5%
1 2
R248 2.2K_0402_5%R248 2.2K_0402_5%
1 2
R245 0_0402_5%R245 0_0402_5%
12
R530 UMA@ 2.2K_0402_1%R530 UMA@ 2.2K_0402_1%
1 2
R254 150_0402_1%R254 150_0402_1%
1 2
R529 UMA@ 2.2K_0402_1%R529 UMA@ 2.2K_0402_1%
1 2
R247
2.37K_0402_1%
R247
2.37K_0402_1%
12
LVDS
Digital Display Interface
CRT
U3D
COUGARPOINT_FCBGA989~D
LVDS
Digital Display Interface
CRT
U3D
COUGARPOINT_FCBGA989~D
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N AV42
DDPB_1N AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N BF42
DDPD_3N BJ42
DDPB_2N AU48
DDPB_3N AV47
DDPC_0N AY47
DDPC_1N AY43
DDPC_2N BA47
DDPC_3N BB47
DDPD_0N BB43
DDPD_1N BF44
DDPB_0P AV40
DDPB_1P AV46
DDPD_2P BE42
DDPD_3P BG42
DDPB_2P AU47
DDPB_3P AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P AY45
DDPC_0P AY49
DDPC_2P BA48
DDPC_3P BB49
DDPD_0P BB45
DDPD_1P BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK P38
SDVO_CTRLDATA M39
DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
DDPD_CTRLCLK M43
DDPD_CTRLDATA M36
DDPB_AUXN AT49
DDPC_AUXN AP47
DDPD_AUXN AT45
DDPB_AUXP AT47
DDPC_AUXP AP49
DDPD_AUXP AT43
DDPB_HPD AT40
DDPC_HPD AT38
DDPD_HPD BH41
SDVO_TVCLKINP AP45
SDVO_TVCLKINN AP43
SDVO_STALLP AM40
SDVO_STALLN AM42
SDVO_INTP AP40
SDVO_INTN AP39
R251 2.2K_0402_5%R251 2.2K_0402_5%
1 2
R253 150_0402_1%R253 150_0402_1%
1 2
R250 2.2K_0402_5%R250 2.2K_0402_5%
1 2
R471 2.2K_0402_5%R471 2.2K_0402_5%
1 2
R255 150_0402_1%R255 150_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
DGPU_HOLD_RST#
DGPU_HOLD_RST#
DGPU_HOLD_RST#
VGA_ON
PCH_GPIO53
DF_TVS
DF_TVS
ODD_DA#
ODD_DA#
PCH_GPIO2
PCH_GPIO2
PCH_GPIO4
PCH_GPIO4
PCH_GPIO5
PCH_GPIO5
PCH_GPIO52
PCH_GPIO53
PCH_GPIO51
PCH_GPIO55
PCI_PIRQA#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQD#
PLT_RST#
PLT_RST#
PLT_RST#
USB20_N0
USB20_N1
USB20_N10
USB20_N12
USB20_N13
USB20_N8
USB20_N9
USB20_P0
USB20_P1
USB20_P10
USB20_P12
USB20_P13
USB20_P8
USB20_P9
USBRBIAS
USB_OC0#
USB_OC0#
USB_OC1#
USB_OC1#
USB_OC2#
USB_OC2#
USB_OC3#
USB_OC3#
USB_OC4#
USB_OC4#
USB_OC5#
USB_OC5#
USB_OC6#
USB_OC6#
USB_OC7#
USB_OC7#
PCH_GPIO51
PCH_GPIO55
PCH_GPIO52
USB20_N2
USB20_P2
PLT_RST#
CLK_PCI_LPBACK
CLK_PCI_LPC
PLT_RST_BUF# 37
USB20_N0 37
USB20_P0 37
USB_OC0# 37
H_SNB_IVB# 5
PLTRST_VGA# 22
CLK_PCI_LPBACK14
CLK_PCI_LPC39
USB20_N8 37
USB20_P8 37
USB20_N9 37
USB20_P9 37
USB20_N10 31
USB20_P10 31
USB20_N12 37
USB20_P12 37
USB20_N13 37
USB20_P13 37
PLT_RST#5,35,38,39,44
ODD_DA#34
USB20_N1 37
USB20_P1 37
VGA_ON14,25,46,55
USB20_N2 37
USB20_P2 37
USB_OC1# 37
+3VS
+3VS
+1.8VS
+3VALW_PCH
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (5/9) PCI, USB, NVRAM
2009/12/01
59
2010/12/31
17
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (5/9) PCI, USB, NVRAM
2009/12/01
59
2010/12/31
17
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (5/9) PCI, USB, NVRAM
2009/12/01
59
2010/12/31
17
Custom
Wednesday, February 16, 2011
Set to Vcc when HIGH
DMI Termination Voltage
DF_TVS Set to Vss when LOW
USB/B (Right side)
Within 500 mils
CLOSE TO THE BRANCHING POINT
Compal Electronics, Inc.
CMOS Camera (LVDS)
Mini Card (SIM card)
Bluetooth
Mini Card (WLAN)
Mini Card (3G)
Bit11
GNT1#/
GPIO51
Boot BIOS Strap bit1 BBS1
Bit10
0
0
1
1
0
0
1
1
Boot BIOS
Destination
Reserved
PCI
SPI
LPC
USB/B (Right side)
Some PCH config not support USB port 6 & 7.
DG1.2 CRB1.0 PH 2.2K series 1K
USB/B (Right side)
For RF request
Modify R02
Modify R02
T24 @PAD T24 @PAD
RP3
8.2K_0804_8P4R_5%
RP3
8.2K_0804_8P4R_5%
1
2
3
45
6
7
8
R264 22_0402_5%R264 22_0402_5%
1 2
R266OPT@
100_0402_5%
R266OPT@
100_0402_5%
1 2
R265@
0_0402_5%
R265@
0_0402_5%
12
T23 @PAD T23 @PAD
R258 8.2K_0402_5%R258 8.2K_0402_5%
1 2
R267 OPT@
0_0402_5%
R267 OPT@
0_0402_5%
12
RSVD
NVRAM
PCI
USB
U3E
COUGARPOINT_FCBGA989~D
RSVD
NVRAM
PCI
USB
U3E
COUGARPOINT_FCBGA989~D
NV_ALE AV5
NV_CE#0 AY7
NV_CE#1 AV7
NV_CE#2 AU3
NV_CE#3 BG4
NV_CLE AY1
NV_DQS0 AT10
NV_DQS1 BC8
NV_DQ0 / NV_IO0 AU2
NV_DQ1 / NV_IO1 AT4
NV_DQ10 / NV_IO10 BB5
NV_DQ11 / NV_IO11 BB3
NV_DQ12 / NV_IO12 BB7
NV_DQ13 / NV_IO13 BE8
NV_DQ14 / NV_IO14 BD4
NV_DQ15 / NV_IO15 BF6
NV_DQ2 / NV_IO2 AT3
NV_DQ3 / NV_IO3 AT1
NV_DQ4 / NV_IO4 AY3
NV_DQ5 / NV_IO5 AT5
NV_DQ6 / NV_IO6 AV3
NV_DQ7 / NV_IO7 AV1
NV_DQ8 / NV_IO8 BB1
NV_DQ9 / NV_IO9 BA3
NV_RB# AT8
NV_RCOMP AV10
NV_RE#_WRB0 AY5
NV_RE#_WRB1 BA2
NV_WE#_CK0 AT12
NV_WE#_CK1 BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1# / GPIO50
C46
REQ2# / GPIO52
C44
REQ3# / GPIO54
E40
GNT1# / GPIO51
D47
GNT2# / GPIO53
E42
GNT3# / GPIO55
F46
PIRQE# / GPIO2
G42
PIRQF# / GPIO3
G40
PIRQG# / GPIO4
C42
PIRQH# / GPIO5
D44
USBP0N C24
USBP0P A24
USBP1N C25
USBP1P B25
USBP2N C26
USBP2P A26
USBP3N K28
USBP3P H28
USBP4N E28
USBP4P D28
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
USBP7N N28
USBP7P M28
USBP8N L30
USBP8P K30
USBP9N G30
USBP9P E30
USBP10N C30
USBP10P A30
USBP11N L32
USBP11P K32
USBP12N G32
USBP12P E32
USBP13N C32
USBP13P A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J48
USBRBIAS# C33
USBRBIAS B33
OC0# / GPIO59 A14
OC1# / GPIO40 K20
OC2# / GPIO41 B17
OC3# / GPIO42 C16
OC4# / GPIO43 L16
OC5# / GPIO9 A16
OC6# / GPIO10 D14
OC7# / GPIO14 C14
CLKOUT_PCI4
H40 CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
TP25
BE28
TP26
BC30
TP27
BE32
TP28
BJ32
TP29
BC28
TP30
BE30
TP31
BF32
TP32
BG32
TP33
AV26
TP34
BB26
TP35
AU28
TP36
AY30
TP37
AU26
TP38
AY26
TP39
AV28
TP40
AW30
TP4
BJ16
TP5
BG16
TP15
AM5 TP14
AM4 TP13
AH12 TP12
H3 TP11
N30 TP10
C18
TP24
BG46
U7
MC74VHC1G08DFT2G_SC70-5
U7
MC74VHC1G08DFT2G_SC70-5
IN1
1
IN2
2OUT 4
VCC 5
GND
3
R263 22_0402_5%R263 22_0402_5%
12
T22 @PAD T22 @PAD
U6
MC74VHC1G08DFT2G_SC70-5
OPT@
U6
MC74VHC1G08DFT2G_SC70-5
OPT@
IN1
1
IN2
2OUT 4
VCC 5
GND
3
C861
10P_0402_50V8J
@C861
10P_0402_50V8J
@
1
2
RP4
10K_1206_8P4R_5%
RP4
10K_1206_8P4R_5%
1
2
3
4 5
6
7
8
RP5
10K_1206_8P4R_5%
RP5
10K_1206_8P4R_5%
1
2
3
4 5
6
7
8
R261 1K_0402_5%R261 1K_0402_5%
12
R259 100K_0402_5%R259 100K_0402_5%
1 2
C860
10P_0402_50V8J
@C860
10P_0402_50V8J
@
1
2
R262 22.6_0402_1%R262 22.6_0402_1%
1 2
R260
2.2K_0402_5%
R260
2.2K_0402_5%
12
R268OPT@
100K_0402_5%
R268OPT@
100K_0402_5%
12
RP2
8.2K_0804_8P4R_5%
RP2
8.2K_0804_8P4R_5%
1
2
3
45
6
7
8
T21 @PAD T21 @PAD
R269
100K_0402_5%
R269
100K_0402_5%
12
RP1
8.2K_0804_8P4R_5%
RP1
8.2K_0804_8P4R_5%
1
2
3
45
6
7
8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BT_ON#
BT_ON#
PCH_GPIO0
DGPU_HPD_INT#
DGPU_HPD_INT#
DGPU_PWROK
PCH_GPIO12
PCH_GPIO12
EC_KBRST#
EC_KBRST#
EC_SCI#
EC_SMI#
H_THRMTRIP#
PCH_GPIO39
ODD_DETECT#
ODD_EN#
PCH_GPIO1
PCH_GPIO1
PCH_GPIO16
PCH_GPIO16
PCH_GPIO22
PCH_GPIO22
PCH_GPIO27
PCH_GPIO27
PCH_GPIO28
OPTIMUS_EN#
WWAN_OFF#
PCH_GPIO39
ODD_DETECT#
PCH_GPIO48
PCH_GPIO48
WL_OFF#
PCH_GPIO57
PCH_GPIO57
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
PCH_PECI_R
PCH_THRMTRIP#_R
SMIB
SMIB
PCH_GPIO24
PCH_GPIO24
PCH_GPIO28
ODD_EN#
PCH_GPIO0
WWAN_OFF#
WL_OFF#
OPTIMUS_EN#
DGPU_PWROK
PCH_GPIO69
PCH_GPIO70
GATEA20 39
EC_SCI#39
H_PECI 5,39
H_CPUPWRGD 5
EC_KBRST# 39
H_THRMTRIP# 5
ODD_DETECT#34
EC_SMI#39
SMIB44
DGPU_HPD_INT#33
BT_ON#37
ODD_EN# 34
WWAN_OFF#37
WL_OFF#37
+3VS
+3VS
+3VS
+3VALW_PCH
+3VS
+3VALW_PCH
+3VSDGPU
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (6/9) GPIO, CPU, MISC
2009/12/01
59
2010/12/31
18
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (6/9) GPIO, CPU, MISC
2009/12/01
59
2010/12/31
18
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (6/9) GPIO, CPU, MISC
2009/12/01
59
2010/12/31
18
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
INIT3_3V
This signal has weak internal
PU, can't pull low
Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70
Intel schematic reviwe recommand.
CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
*
This signal has a weak internal pull up
On-Die PLL Voltage Regulator
L On-Die PLL Voltage Regulator disable
GPIO28
H On-Die PLL voltage regulator enable
CRB1.0 PH200K to +3VS
GPIO38
0
1
*OPTIMUS
Non-OPTIMUS
OPTIMUS_EN#
Modify R10
Board ID
R292 1K_0402_5%R292 1K_0402_5%
1 2
R272
1K_0402_5%
@
R272
1K_0402_5%
@12
T39@PADT39@PAD
T87@PADT87@PAD
T31@PADT31@PAD
T38 @PAD T38 @PAD
T34 @PAD T34 @PAD
R286 200K_0402_5%R286 200K_0402_5%
1 2
T35@PADT35@PAD
T48@PADT48@PAD
R852 0_0402_5%R852 0_0402_5%
1 2
T55@PADT55@PAD
T37@PADT37@PAD
Q78A
DMN66D0LDW-7_SOT363-6
OPT@
Q78A
DMN66D0LDW-7_SOT363-6
OPT@
61
2
R283
10K_0402_5%
R283
10K_0402_5%
12
T29@PADT29@PAD
R276 10K_0402_5%R276 10K_0402_5%
1 2
R850
100K_0402_5%
OPT@
R850
100K_0402_5%
OPT@
1 2
R278 390_0402_5%R278 390_0402_5%
1 2
R275 10K_0402_5%R275 10K_0402_5%
1 2
R289 10K_0402_5%R289 10K_0402_5%
1 2
T42 @PAD T42 @PAD
R274
@
0_0402_5% R274
@
0_0402_5%
1 2
R281 10K_0402_5%R281 10K_0402_5%
1 2
T43@PADT43@PAD
R273
10K_0402_5%
R273
10K_0402_5%
1 2
R851 0_0402_5%R851 0_0402_5%
1 2
T50@PADT50@PAD
Q78B
DMN66D0LDW-7_SOT363-6
OPT@
Q78B
DMN66D0LDW-7_SOT363-6
OPT@
34
5
T30@PADT30@PAD
T88@PADT88@PAD
T45@PADT45@PAD
R280 10K_0402_5%R280 10K_0402_5%
1 2
T40 @PAD T40 @PAD
T28@PADT28@PAD
T51 @PAD T51 @PAD
R282 10K_0402_5%R282 10K_0402_5%
1 2
T41@PADT41@PAD
T56 @PAD T56 @PAD T89@PADT89@PAD
T52@PADT52@PAD
R284 10K_0402_5%R284 10K_0402_5%
1 2
R643 10K_0402_5%OPT@R643 10K_0402_5%OPT@
1 2
T47 @PAD T47 @PAD
R287 10K_0402_5%R287 10K_0402_5%
1 2
C871
1U_0402_6.3V6K
OPT@
C871
1U_0402_6.3V6K
OPT@
1
2
R288 10K_0402_5%R288 10K_0402_5%
1 2
R279 10K_0402_5%
UMAO@
R279 10K_0402_5%
UMAO@12
R270 10K_0402_5%R270 10K_0402_5%
12
T49 @PAD T49 @PAD
C872
0.1U_0402_16V4Z
C872
0.1U_0402_16V4Z
1
2
T33@PADT33@PAD
R277 10K_0402_5%R277 10K_0402_5%
1 2
R294 10K_0402_5%R294 10K_0402_5%
1 2
T44 @PAD T44 @PAD
T32 @PAD T32 @PAD
T53 @PAD T53 @PAD
T54 @PAD T54 @PAD
R291 10K_0402_5%R291 10K_0402_5%
1 2
T25@PADT25@PAD
R485 4.7K_0402_5%@R485 4.7K_0402_5%@
1 2
T46 @PAD T46 @PAD
R293 10K_0402_5%R293 10K_0402_5%
1 2
CPU/MISC
NCTF
GPIO
U3F
COUGARPOINT_FCBGA989~D
CPU/MISC
NCTF
GPIO
U3F
COUGARPOINT_FCBGA989~D
GPIO27
E16
GPIO28
P8
GPIO24 / MEM_LED
E8
GPIO57
D6
LAN_PHY_PWR_CTRL / GPIO12
C4
VSS_NCTF_1
A4
VSS_NCTF_2
A44
VSS_NCTF_3
A45
VSS_NCTF_4
A46
VSS_NCTF_5
A5
VSS_NCTF_6
A6
VSS_NCTF_7
B3
VSS_NCTF_8
B47
VSS_NCTF_9
BD1
VSS_NCTF_10
BD49
VSS_NCTF_11
BE1
VSS_NCTF_12
BE49
TACH2 / GPIO6
H36
TACH0 / GPIO17
D40
TACH3 / GPIO7
E38
SATA3GP / GPIO37
M5
SATA5GP / GPIO49
V3
SCLOCK / GPIO22
T5
SLOAD / GPIO38
N2
SDATAOUT0 / GPIO39
M3
SDATAOUT1 / GPIO48
V13
PROCPWRGD AY11
RCIN# P5
PECI AU16
THRMTRIP# AY10
GPIO8
C10
BMBUSY# / GPIO0
T7
GPIO15
G2
TACH1 / GPIO1
A42
SATA2GP / GPIO36
V8
INIT3_3V# T14
STP_PCI# / GPIO34
K1
GPIO35
K4
SATA4GP / GPIO16
U2
VSS_NCTF_32 F49
A20GATE P4
TACH4 / GPIO68 C40
TACH6 / GPIO70 C41
TACH7 / GPIO71 A40
TACH5 / GPIO69 B41
VSS_NCTF_17 BH3
VSS_NCTF_18 BH47
VSS_NCTF_19 BJ4
VSS_NCTF_20 BJ44
VSS_NCTF_21 BJ45
VSS_NCTF_22 BJ46
VSS_NCTF_23 BJ5
VSS_NCTF_24 BJ6
VSS_NCTF_25 C2
VSS_NCTF_26 C48
VSS_NCTF_27 D1
VSS_NCTF_28 D49
VSS_NCTF_29 E1
VSS_NCTF_30 E49
VSS_NCTF_31 F1
NC_4 AK10
NC_3 AH10
NC_2 AK11
NC_1 AH8
NC_5 P37
VSS_NCTF_13
BF1
VSS_NCTF_14
BF49
VSS_NCTF_15 BG2
VSS_NCTF_16 BG48
T36 @PAD T36 @PAD
R285 100K_0402_5%R285 100K_0402_5%
1 2
R290 10K_0402_5%R290 10K_0402_5%
1 2
R841
10K_0402_5%
OPT@
R841
10K_0402_5%
OPT@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS_PCH
+1.05VS_VCCAPLL_FDI
+VCCADAC
+VCCAFDI_VRM
+VCCAFDI_VRM
+VCCAFDI_VRM
+VCCAPLLEXP
+VCCTX_LVDS
+1.5VS
+VCCAFDI_VRM
+1.05VS_VCCP
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+3VS
+1.8VS
+3VS
+3VS
+3VS
+3VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (7/9) PWR
2009/12/01
59
2010/12/31
19
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (7/9) PWR
2009/12/01
59
2010/12/31
19
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-7221P
0.2
PCH (7/9) PWR
2009/12/01
59
2010/12/31
19
Custom
Wednesday, February 16, 2011
3.3
1.05
1.05
1.05
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
Voltage Rail
VccCore
VccDMI
1.05
5
3.3
0.001
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
5
Voltage
S0 Iccmax
Current
(A)
1.05
1.05VccIO 2.925
1.05VccASW 1.01
3.3VccSPI 0.02
3.3VccDSW 0.003
1.8 0.19VccpNAND
3.3VccRTC 6 uA
3.3VccSus3_3
3.3 / 1.5VccSusHDA
0.119
0.01
VccVRM 1.8 / 1.5 0.16
1.05VccCLKDMI
VccALVDS 3.3
1.8VccTX_LVDS 0.06
0.001
0.02
PCH Power Rail Table
Compal Electronics, Inc.
1mA
1300mA
2925mA
20mA
190mA
VCCVRM = 160mA detal waiting for newest spec
20mA
1mA
60mA
VccSSC 1.05 0.095
VccDIFFCLKN 1.05 0.055
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
This pin can be left as no connect in
On-Die VR enabled mode (default).
0.1uH inductor, 200mA
Modify R03
Modify R03
Modify R03
Modify R04
L1 -->SHI00003Y00
T77 @PAD T77 @PAD
C201
1U_0402_6.3V6K
C201
1U_0402_6.3V6K
12
C198
10U_0603_6.3V6M
C198
10U_0603_6.3V6M
12
R307 0_0603_5%R307 0_0603_5%
12
C190
1U_0402_6.3V6K
C190
1U_0402_6.3V6K
12
C196
22U_0805_6.3V6M
C196
22U_0805_6.3V6M
12
C192
0.1U_0402_10V7K
C192
0.1U_0402_10V7K
12
C202
1U_0402_6.3V6K
C202
1U_0402_6.3V6K
12
C199
1U_0402_6.3V6K
C199
1U_0402_6.3V6K
12
L1
4.7UH_LQM18FN4R7M00D_20%
L1
4.7UH_LQM18FN4R7M00D_20%
12
C197
0.1U_0402_10V7K
C197
0.1U_0402_10V7K
12
C191
0.01U_0402_16V7K
C191
0.01U_0402_16V7K
12
C795
1U_0402_6.3V6K
C795
1U_0402_6.3V6K
12
C195
0.01U_0402_16V7K
C195
0.01U_0402_16V7K
12
C203
1U_0402_6.3V6K
C203
1U_0402_6.3V6K
12
C188
10U_0603_6.3V6M
C188
10U_0603_6.3V6M
12
C193
10U_0603_6.3V6M
C193
10U_0603_6.3V6M
12
C189
1U_0402_6.3V6K
C189
1U_0402_6.3V6K
12
C205
0.1U_0402_10V7K
C205
0.1U_0402_10V7K
12
JP3@
PAD-OPEN 4x4m
JP3@
PAD-OPEN 4x4m
12
C206
0.1U_0402_10V7K
C206
0.1U_0402_10V7K
12
C200
1U_0402_6.3V6K
C200
1U_0402_6.3V6K
12
C208
1U_0402_6.3V6K
C208
1U_0402_6.3V6K
12
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
NAND / SPI HVCMOS
U3G
COUGARPOINT_FCBGA989~D
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
NAND / SPI HVCMOS
U3G
COUGARPOINT_FCBGA989~D
VCCCORE[1]
AA23
VCCCORE[2]
AC23
VCCCORE[3]
AD21
VCCCORE[4]
AD23
VCCCORE[5]
AF21
VCCCORE[6]
AF23
VCCCORE[7]
AG21
VCCCORE[8]
AG23
VCCCORE[9]
AG24
VCCCORE[10]
AG26
VCCCORE[11]
AG27
VCCCORE[12]
AG29
VCCCORE[13]
AJ23
VCCCORE[14]
AJ26
VCCCORE[15]
AJ27
VCCPNAND[4] AJ17
VCCPNAND[3] AJ16
VCCIO[17]
AN21
VCCIO[18]
AN26
VCCIO[19]
AN27
VCCIO[20]
AP21
VCCIO[23]
AP26
VCCIO[24]
AT24
VCCIO[15]
AN16
VCCIO[16]
AN17
VCCIO[21]
AP23
VCCIO[22]
AP24
VCCADAC U48
VCCTX_LVDS[1] AM37
VCCTX_LVDS[2] AM38
VCCALVDS AK36
VCCVRM[3] AT16
VCCVRM[2]
AP16
VCCAPLLEXP
BJ22
VCCFDIPLL
BG6
VCCIO[28]
AN19 VCCTX_LVDS[4] AP37
VCCTX_LVDS[3] AP36
VSSADAC U47
VSSALVDS AK37
VCCIO[27]
AP17
VCC3_3[6] V33
VCC3_3[7] V34
VCC3_3[3]
BH29 VCCPNAND[2] AG17
VCCPNAND[1] AG16
VCCDMI[1] AT20
VCCIO[25]
AN33
VCCIO[26]
AN34
VCCCORE[16]
AJ29
VCCCORE[17]
AJ31
VCCSPI V1
VCCIO[1] AB36
VCCDMI[2]
AU20
T57 @PAD T57 @PAD
L2
0.1UH_MLF1608DR10KT_10%_1608
L2
0.1UH_MLF1608DR10KT_10%_1608
12
C194
0.01U_0402_16V7K
C194
0.01U_0402_16V7K
12
C187
1U_0402_6.3V6K
C187
1U_0402_6.3V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VM_VCCSUS
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+1.05VS_VCCA_B_DPL
+3VS_VCC_CLKF33
+3VS_VCC_CLKF33
+PCH_V5REF_RUN
+PCH_V5REF_RUN
+PCH_V5REF_SUS
+PCH_V5REF_SUS
+PCH_VCCDSW
+VCCACLK
+VCCAFDI_VRM
+VCCAFDI_VRM
+VCCAPLL_CPY_PCH
+VCCA_USBSUS
+VCCME_21
+VCCME_22
+VCCME_23
+VCCRTCEXT
+VCCSATAPLL
+VCCSST
+VCCSUS1
+VCCSUSHDA
PCH_PWR_EN#35,46
+3VS+5VS
+3VALW_PCH+5VALW_PCH
+1.05VS_PCH
+3VALW_PCH
+1.05VS_PCH
+1.05VS_PCH
+3VALW_PCH
+1.05VS_PCH
+1.05VS_PCH
+3VALW_PCH
+3VALW_PCH
+3VS
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+RTCVCC
+VCCAFDI_VRM
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+1.05VS_PCH
+3VS
+5VALW
+5VALW_PCH
+3VALW_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
20
2010/12/31
59
2009/12/01
PCH (8/9) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
20
2010/12/31
59
2009/12/01
PCH (8/9) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
20
2010/12/31
59
2009/12/01
PCH (8/9) PWR
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
1mA
1mA
1mA
119mA
80mA
80mA
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
1010mA
3mA
10mA
95mA
55mA
Have internal VRM
Place C228 near AA16.W16 pin
Place C233 near T34 pin
Place C234 near AJ2 pin
Place C217 near T23 pin
Place C218 near P24 pin
Modify R03
Modify R03
C240
1U_0402_6.3V6K
C240
1U_0402_6.3V6K
12
C248
0.1U_0402_10V7K
C248
0.1U_0402_10V7K
12
C224
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
12
C236
0.1U_0402_10V7K
C236
0.1U_0402_10V7K
12
C230
1U_0402_6.3V6K
C230
1U_0402_6.3V6K
12
T82 @PAD T82 @PAD
C249
0.1U_0402_10V7K
C249
0.1U_0402_10V7K
12
C235
1U_0402_6.3V6K
C235
1U_0402_6.3V6K
12
+
C231
220U_B2_2.5VM_R35
+
C231
220U_B2_2.5VM_R35
12
C234
0.1U_0402_10V7K
C234
0.1U_0402_10V7K
12
D
G
S
Q64
AO3413L_SOT23-3
D
G
S
Q64
AO3413L_SOT23-3
1
2
3
L3
10UH_LB2012T100MR_20%
L3
10UH_LB2012T100MR_20%
1 2
C245
0.1U_0402_10V7K
C245
0.1U_0402_10V7K
12
C210
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
12
C244
4.7U_0603_6.3V6K
C244
4.7U_0603_6.3V6K
12
R339 0_0603_5%R339 0_0603_5%
12
T78@PADT78@PAD
R751
0_0603_5%
@R751
0_0603_5%
@
12
R309@
0_0805_5%
R309@
0_0805_5%
1 2
R310@
0_0603_5%
R310@
0_0603_5%
12
C218
0.1U_0402_10V7K
C218
0.1U_0402_10V7K
12
C237
1U_0402_6.3V6K
C237
1U_0402_6.3V6K
12
C217
0.1U_0402_10V7K
C217
0.1U_0402_10V7K
12
R752
20K_0402_5%
R752
20K_0402_5%
12
D4
RB751V-40_SOD323-2
D4
RB751V-40_SOD323-2
1 2
C242
0.1U_0402_10V7K
C242
0.1U_0402_10V7K
12
C233
0.1U_0402_10V7K
C233
0.1U_0402_10V7K
12
L6
10UH_LB2012T100MR_20%
L6
10UH_LB2012T100MR_20%
1 2
C816
0.1U_0402_10V7K
C816
0.1U_0402_10V7K
1
2
T81 @PAD T81 @PAD
C232
1U_0402_6.3V6K
C232
1U_0402_6.3V6K
12
C209
10U_0603_6.3V6M
C209
10U_0603_6.3V6M
12
C250
0.1U_0402_16V4Z
C250
0.1U_0402_16V4Z
12
D3
RB751V-40_SOD323-2
D3
RB751V-40_SOD323-2
1 2
C247
1U_0402_6.3V6K
C247
1U_0402_6.3V6K
12
R338 0_0603_5%R338 0_0603_5%
12
C211
0.1U_0402_10V7K
C211
0.1U_0402_10V7K
12
T79@PADT79@PAD
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
U3J
COUGARPOINT_FCBGA989~D
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
U3J
COUGARPOINT_FCBGA989~D
DCPSUSBYP
V12
VCCASW[1]
AA19
VCCASW[2]
AA21
VCCASW[3]
AA24
VCCASW[5]
AA27
VCCASW[6]
AA29
VCCSUSHDA P32
VCCSUS3_3[6] P24
VCCIO[34] T26
VCCIO[4] AD17
VCCASW[7]
AA31
VCCASW[8]
AC26
VCCASW[9]
AC27
VCCASW[10]
AC29
VCCASW[11]
AC31
VCCASW[12]
AD29
V5REF P34
VCC3_3[4] T34
VCCRTC
A22
VCCSUS3_3[10] V24
VCCSUS3_3[9] V23
VCCSUS3_3[8] T24
VCCSUS3_3[7] T23
VCCIO[2] AC16
VCCADPLLB
BF47
VCCIO[8]
AF33
V5REF_SUS M26
VCCIO[3] AC17
DCPSUS[1]
T17
VCCIO[10]
AG33
VCCADPLLA
BD47
VCCVRM[4]
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW[4]
AA26
VCCIO[9]
AF34
VCCIO[7]
AF17
DCPSST
V16
VCCIO[5] AF13
VCCASW[22] T21
VCCASW[23] V21
VCCASW[21] T19
VCC3_3[1] AA16
VCC3_3[8] W16
VCCSUS3_3[2] N20
VCCSUS3_3[3] N22
VCCSUS3_3[4] P20
VCCSUS3_3[5] P22
VCCIO[29] N26
VCCIO[30] P26
VCCIO[31] P28
VCCIO[32] T27
V_PROC_IO
BJ8
VCCIO[33] T29
VCCIO[11]
AG34
VCCASW[13]
AD31
VCCASW[14]
W21
VCCASW[15]
W23
VCCASW[16]
W24
VCCASW[17]
W26
VCCASW[18]
W29
VCCASW[19]
W31
VCCASW[20]
W33
VCCIO[6] AF14
VCCVRM[1] AF11
VCCIO[12] AH13
VCCIO[13] AH14
VCC3_3[2] AJ2
VCCAPLLSATA AK1
DCPSUS[3]
AL24
VCCIO[14]
AL29
DCPSUS[4] AN23
VCCSUS3_3[1] AN24
VCCAPLLDMI2
BH23
DCPSUS[2]
V19
VCCDSW3_3
T16
VCC3_3[5]
T38
T80@PADT80@PAD
C213
1U_0402_6.3V6K
C213
1U_0402_6.3V6K
12
C226
1U_0402_6.3V6K
C226
1U_0402_6.3V6K
12
C241
1U_0402_6.3V6K
C241
1U_0402_6.3V6K
12
T83@PADT83@PAD
R336 0_0603_5%R336 0_0603_5%
12
C238
1U_0402_6.3V6K
C238
1U_0402_6.3V6K
12
C220
22U_0805_6.3V6M
C220
22U_0805_6.3V6M
12
L5
10UH_LB2012T100MR_20%
L5
10UH_LB2012T100MR_20%
1 2
C223
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
12
C219
0.1U_0603_25V7K
C219
0.1U_0603_25V7K
12
C228
0.1U_0402_10V7K
C228
0.1U_0402_10V7K
12
+
C229
220U_B2_2.5VM_R35
+
C229
220U_B2_2.5VM_R35
12
C221
22U_0805_6.3V6M
C221
22U_0805_6.3V6M
12
R319
100_0402_5%
R319
100_0402_5%
12
C225
1U_0402_6.3V6K
C225
1U_0402_6.3V6K
12
R335 0_0603_5%R335 0_0603_5%
12
C246
0.1U_0402_10V7K
C246
0.1U_0402_10V7K
12
C227
1U_0603_10V6K
C227
1U_0603_10V6K
12
R323
100_0402_5%
R323
100_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
21
2010/12/31
59
2009/12/01
PCH (9/9) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
21
2010/12/31
59
2009/12/01
PCH (9/9) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
21
2010/12/31
59
2009/12/01
PCH (9/9) VSS
0.2
LA-7221P
Custom
Wednesday, February 16, 2011
Compal Electronics, Inc.
U3H
COUGARPOINT_FCBGA989~D
U3H
COUGARPOINT_FCBGA989~D
VSS[1]
AA17
VSS[2]
AA2
VSS[3]
AA3
VSS[5]
AA34
VSS[6]
AB11
VSS[7]
AB14
VSS[8]
AB39
VSS[9]
AB4
VSS[10]
AB43
VSS[11]
AB5
VSS[12]
AB7
VSS[13]
AC19
VSS[14]
AC2
VSS[15]
AC21
VSS[16]
AC24
VSS[17]
AC33
VSS[18]
AC34
VSS[19]
AC48
VSS[20]
AD10
VSS[21]
AD11
VSS[22]
AD12
VSS[23]
AD13
VSS[24]
AD19
VSS[25]
AD24
VSS[26]
AD26
VSS[27]
AD27
VSS[28]
AD33
VSS[29]
AD34
VSS[30]
AD36
VSS[31]
AD37
VSS[33]
AD39
VSS[34]
AD4
VSS[35]
AD40
VSS[36]
AD42
VSS[37]
AD43
VSS[38]
AD45
VSS[39]
AD46
VSS[43]
AF10
VSS[44]
AF12
VSS[46]
AD16
VSS[47]
AF16
VSS[48]
AF19
VSS[49]
AF24
VSS[50]
AF26
VSS[51]
AF27
VSS[52]
AF29
VSS[53]
AF31
VSS[54]
AF38
VSS[55]
AF4
VSS[56]
AF42
VSS[57]
AF46
VSS[59]
AF7
VSS[60]
AF8
VSS[61]
AG19
VSS[62]
AG2
VSS[63]
AG31
VSS[64]
AG48
VSS[65]
AH11
VSS[66]
AH3
VSS[67]
AH36
VSS[68]
AH39
VSS[69]
AH40
VSS[70]
AH42
VSS[71]
AH46
VSS[72]
AH7
VSS[73]
AJ19
VSS[76]
AJ33
VSS[77]
AJ34
VSS[78]
AK12
VSS[79]
AK3
VSS[80] AK38
VSS[81] AK4
VSS[82] AK42
VSS[83] AK46
VSS[84] AK8
VSS[85] AL16
VSS[86] AL17
VSS[87] AL19
VSS[88] AL2
VSS[89] AL21
VSS[90] AL23
VSS[91] AL26
VSS[92] AL27
VSS[93] AL31
VSS[96] AL48
VSS[97] AM11
VSS[98] AM14
VSS[99] AM36
VSS[100] AM39
VSS[102] AM45
VSS[103] AM46
VSS[104] AM7
VSS[105] AN2
VSS[106] AN29
VSS[107] AN3
VSS[108] AN31
VSS[109] AP12
VSS[110] AP19
VSS[111] AP28
VSS[112] AP30
VSS[113] AP32
VSS[114] AP38
VSS[116] AP42
VSS[117] AP46
VSS[118] AP8
VSS[119] AR2
VSS[120] AR48
VSS[121] AT11
VSS[122] AT13
VSS[123] AT18
VSS[124] AT22
VSS[125] AT26
VSS[126] AT28
VSS[127] AT30
VSS[128] AT32
VSS[131] AT42
VSS[132] AT46
VSS[133] AT7
VSS[134] AU24
VSS[135] AU30
VSS[136] AV16
VSS[137] AV20
VSS[138] AV24
VSS[139] AV30
VSS[140] AV38
VSS[141] AV4
VSS[142] AV43
VSS[143] AV8
VSS[144] AW14
VSS[145] AW18
VSS[146] AW2
VSS[147] AW22
VSS[148] AW26
VSS[149] AW28
VSS[150] AW32
VSS[151] AW34
VSS[152] AW36
VSS[153] AW40
VSS[154] AW48
VSS[155] AV11
VSS[156] AY12
VSS[157] AY22
VSS[158] AY28
VSS[40]
AD8
VSS[42]
AE3
VSS[45]
AD14
VSS[115] AP4
VSS[0]
H5
VSS[58]
AF5
VSS[32]
AD38
VSS[4]
AA33
VSS[74]
AJ21
VSS[75]
AJ24
VSS[41]
AE2
VSS[129] AT34
VSS[130] AT39
VSS[101] AM43
VSS[95] AL34
VSS[94] AL33
U3I
COUGARPOINT_FCBGA989~D
U3I
COUGARPOINT_FCBGA989~D
VSS[159]
AY4
VSS[160]
AY42
VSS[161]
AY46
VSS[162]
AY8
VSS[163]
B11
VSS[164]
B15
VSS[165]
B19
VSS[166]
B23
VSS[167]
B27
VSS[168]
B31
VSS[169]
B35
VSS[170]
B39
VSS[171]
B7
VSS[173]
BB12
VSS[174]
BB16
VSS[175]
BB20
VSS[176]
BB22
VSS[177]
BB24
VSS[178]
BB28
VSS[179]
BB30
VSS[180]
BB38
VSS[181]
BB4
VSS[182]
BB46
VSS[183]
BC14
VSS[184]
BC18
VSS[185]
BC2
VSS[186]
BC22
VSS[187]
BC26
VSS[188]
BC32
VSS[189]
BC34
VSS[190]
BC36
VSS[191]
BC40
VSS[192]
BC42
VSS[193]
BC48
VSS[194]
BD46
VSS[195]
BD5
VSS[196]
BE22
VSS[197]
BE26
VSS[198]
BE40
VSS[199]
BF10
VSS[200]
BF12
VSS[201]
BF16
VSS[202]
BF20
VSS[203]
BF22
VSS[204]
BF24
VSS[205]
BF26
VSS[206]
BF28
VSS[207]
BD3
VSS[208]
BF30
VSS[209]
BF38
VSS[210]
BF40
VSS[211]
BF8
VSS[212]
BG17
VSS[213]
BG21
VSS[214]
BG33
VSS[215]
BG44
VSS[216]
BG8
VSS[217]
BH11
VSS[218]
BH15
VSS[219]
BH17
VSS[220]
BH19
VSS[222]
BH27
VSS[223]
BH31
VSS[224]
BH33
VSS[225]
BH35
VSS[226]
BH39
VSS[227]
BH43
VSS[228]
BH7
VSS[229]
D3
VSS[230]
D12
VSS[231]
D16
VSS[232]
D18
VSS[233]
D22
VSS[234]
D24
VSS[235]
D26
VSS[236]
D30
VSS[237]
D32
VSS[264] K7
VSS[265] L18
VSS[266] L2
VSS[267] L20
VSS[268] L26
VSS[269] L28
VSS[270] L36
VSS[271] L48
VSS[272] M12
VSS[273] P16
VSS[274] M18
VSS[275] M22
VSS[276] M24
VSS[277] M30
VSS[278] M32
VSS[279] M34
VSS[280] M38
VSS[281] M4
VSS[282] M42
VSS[283] M46
VSS[284] M8
VSS[285] N18
VSS[286] P30
VSS[288] P11
VSS[289] P18
VSS[290] T33
VSS[291] P40
VSS[292] P43
VSS[293] P47
VSS[294] P7
VSS[295] R2
VSS[296] R48
VSS[297] T12
VSS[298] T31
VSS[299] T37
VSS[300] T4
VSS[301] W34
VSS[302] T46
VSS[303] T47
VSS[304] T8
VSS[305] V11
VSS[306] V17
VSS[307] V26
VSS[308] V27
VSS[309] V29
VSS[310] V31
VSS[311] V36
VSS[312] V39
VSS[313] V43
VSS[314] V7
VSS[315] W17
VSS[316] W19
VSS[238]
D34
VSS[239]
D38
VSS[240]
D42
VSS[241]
D8
VSS[242]
E18
VSS[243]
E26
VSS[244]
G18
VSS[245]
G20
VSS[246]
G26
VSS[247]
G28
VSS[248]
G36
VSS[249]
G48
VSS[250]
H12
VSS[251]
H18
VSS[317] W2
VSS[318] W27
VSS[319] W48
VSS[320] Y12
VSS[321] Y38
VSS[322] Y4
VSS[323] Y42
VSS[324] Y46
VSS[325] Y8
VSS[328] BG29
VSS[329] N24
VSS[330] AJ3
VSS[287] N47
VSS[252]
H22
VSS[253]
H24
VSS[254]
H26
VSS[255]
H30
VSS[256]
H32
VSS[257]
H34
VSS[258]
F3
VSS[262] K39
VSS[263] K46
VSS[259] H46
VSS[260] K18
VSS[261] K26
VSS[331] AD47
VSS[333] B43
VSS[334] BE10
VSS[335] BG41
VSS[337] G14
VSS[338] H16
VSS[340] T36
VSS[342] BG22
VSS[343] BG24
VSS[344] C22
VSS[345] AP13
VSS[172]
F45
VSS[221]
H10
VSS[346] M14
VSS[347] AP3
VSS[348] AP1
VSS[349] BE16
VSS[350] BC16
VSS[351] BG28
VSS[352] BJ28
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+GPU_PLLVDD
I2CB_SCL
I2CB_SCL
I2CB_SDA
I2CB_SDA
I2CC_SCL
I2CC_SCL
I2CC_SDA
I2CC_SDA
I2CH_SCL
I2CH_SCL
I2CH_SDA
I2CH_SDA
I2CS_SCL
I2CS_SCL
I2CS_SCL
I2CS_SDA
I2CS_SDA
I2CS_SDA
OSC_OUT
OSC_OUT
OSC_SPREAD
OSC_SPREAD
I2CA_SCL
I2CA_SCL
I2CA_SDA
I2CA_SDA
XTALIN
XTALIN
XTALOUT
XTALOUT
XTAL_OUTBUFF
XTAL_OUTBUFF
XTAL_SSIN
XTAL_SSIN
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_P3
PEG_GTX_HRX_N7
PEG_GTX_HRX_P7
PEG_GTX_HRX_N2
PEG_GTX_HRX_P2
PEG_GTX_HRX_N1
PEG_GTX_HRX_P1
PEG_GTX_HRX_N0
PEG_GTX_HRX_P0
PEG_GTX_HRX_N6
PEG_GTX_HRX_P6
PEG_GTX_HRX_N5
PEG_GTX_HRX_P5
PEG_GTX_HRX_N4
PEG_GTX_HRX_P4
PEG_GTX_HRX_N3
PEG_GTX_HRX_P3
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_P11
PEG_GTX_HRX_N15
PEG_GTX_HRX_P15
PEG_GTX_HRX_N10
PEG_GTX_HRX_P10
PEG_GTX_HRX_N9
PEG_GTX_HRX_P9
PEG_GTX_HRX_N8
PEG_GTX_HRX_P8
PEG_GTX_HRX_N14
PEG_GTX_HRX_P14
PEG_GTX_HRX_N13
PEG_GTX_HRX_P13
PEG_GTX_HRX_N12
PEG_GTX_HRX_P12
PEG_GTX_HRX_N11
PEG_GTX_HRX_P11
NV_PERFORMANCE_R
CLK_PEG_VGA14
CLK_PEG_VGA#14
PEG_HTX_C_GRX_P24
PEG_HTX_C_GRX_N04
PEG_HTX_C_GRX_P04
PEG_HTX_C_GRX_N94
PEG_HTX_C_GRX_P94
PEG_HTX_C_GRX_N114
PEG_HTX_C_GRX_P114
PEG_HTX_C_GRX_N84
PEG_HTX_C_GRX_P84
PEG_HTX_C_GRX_N104
PEG_HTX_C_GRX_P104
PEG_HTX_C_GRX_N124
PEG_HTX_C_GRX_P124
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N44
PEG_HTX_C_GRX_P44
PEG_HTX_C_GRX_N34
PEG_HTX_C_GRX_P34
PEG_HTX_C_GRX_N64
PEG_HTX_C_GRX_P64
PEG_HTX_C_GRX_N54
PEG_HTX_C_GRX_P54
PEG_HTX_C_GRX_N74
PEG_HTX_C_GRX_P74
PEG_HTX_C_GRX_N154
PEG_HTX_C_GRX_P154
PEG_HTX_C_GRX_N144
PEG_HTX_C_GRX_P144
PEG_HTX_C_GRX_N134
PEG_HTX_C_GRX_P134
PEG_HTX_C_GRX_N24
PLTRST_VGA#17
EC_SMB_DA2 14,39
EC_SMB_CK2 14,39
PEG_CLKREQ#14
VGA_HDMI_DET 33
GPU_VID0 39,55
GPU_VID1 39,55
PEG_GTX_C_HRX_P[0..15]4
PEG_GTX_C_HRX_N[0..15]4
CLK_27M_TCLK14
GPU_VID2 55
NV_PERFORMANCE 39
+3VSDGPU
+1.05VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5922
2010/11/232009/11/23
LA-7221P
Compal Electronics, Inc.
N12P PEG 1/9
0.2Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5922
2010/11/232009/11/23
LA-7221P
Compal Electronics, Inc.
N12P PEG 1/9
0.2Custom
Wednesday, February 16, 2011
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
5922
2010/11/232009/11/23
LA-7221P
Compal Electronics, Inc.
N12P PEG 1/9
0.2Custom
Wednesday, February 16, 2011
150mA
under GPU
External Spread Spectrum
If External Spread Spectrum not stuff then stuff resistor
Option Component
Modify R02, changed location of the pull-up
resistor (R342) from U8.H6 to net
NV_PERFORMANCE_R.
AC/DC detection
Reserve for VPSIN
OVERT
GPIO5
GPIO1
GPIO6
GPIO7
GPIO8
GPIO9
GPIO18
GPIO12
IN
OUT
OUT
OUT
IN
IN
GPIO I/O FUNCTION
GPU_VID2
ALERT
HPD_C
GPU_VID0
GPU_VID1
IN
C281 0.1U_0402_10V7KOPT@C281 0.1U_0402_10V7KOPT@
1 2
R369@124_0402_1%R369@124_0402_1%
1 2
C262 0.1U_0402_10V7KOPT@C262 0.1U_0402_10V7KOPT@
1 2
C264 0.1U_0402_10V7KOPT@C264 0.1U_0402_10V7KOPT@
1 2
C277 0.1U_0402_10V7KOPT@C277 0.1U_0402_10V7KOPT@
1 2
C274 0.1U_0402_10V7KOPT@C274 0.1U_0402_10V7KOPT@
1 2
R357
OPT@
10K_0402_5%
R357
OPT@
10K_0402_5%
12
C298OPT@
18P_0402_50V8J
C298OPT@
18P_0402_50V8J
12
C268 0.1U_0402_10V7KOPT@C268 0.1U_0402_10V7KOPT@
1 2
C257 0.1U_0402_10V7KOPT@C257 0.1U_0402_10V7KOPT@
1 2
R365 OPT@ 2.49K_0402_1%R365 OPT@ 2.49K_0402_1%
12
R341 OPT@ 10K_0402_5%R341 OPT@ 10K_0402_5%
12
C283
@
0.1U_0402_16V4Z
C283
@
0.1U_0402_16V4Z
12
C272 0.1U_0402_10V7KOPT@C272 0.1U_0402_10V7KOPT@
1 2
C261 0.1U_0402_10V7KOPT@C261 0.1U_0402_10V7KOPT@
1 2
C251 0.1U_0402_10V7KOPT@C251 0.1U_0402_10V7KOPT@
1 2
C260 0.1U_0402_10V7KOPT@C260 0.1U_0402_10V7KOPT@
1 2
R356 @22_0402_5%R356 @22_0402_5%
1 2
Q16A
DMN66D0LDW-7_SOT363-6
OPT@Q16A
DMN66D0LDW-7_SOT363-6
OPT@
61
2
R343 OPT@ 2.2K_0402_5%R343 OPT@ 2.2K_0402_5%
1 2
L8
BLM18PG300SN1D_2P
OPT@ L8
BLM18PG300SN1D_2P
OPT@
12
C253 0.1U_0402_10V7KOPT@C253 0.1U_0402_10V7KOPT@
1 2
R744@124_0402_1%R744@124_0402_1%
1 2
DVO
PCI EXPRESS
CLK
Part 1 of 7
DACs
I2C
GPIO
U8A
N12P-GS-A1_BGA973
GS@
DVO
PCI EXPRESS
CLK
Part 1 of 7
DACs
I2C
GPIO
U8A
N12P-GS-A1_BGA973
GS@
PEX_RX0
AP17
PEX_RX0_N
AN17
PEX_RX1
AN19
PEX_RX1_N
AP19
PEX_RX2
AR19
PEX_RX2_N
AR20
PEX_RX3
AP20
PEX_RX3_N
AN20
PEX_RX4
AN22
PEX_RX4_N
AP22
PEX_RX5
AR22
PEX_RX5_N
AR23
PEX_RX6
AP23
PEX_RX6_N
AN23
PEX_RX7
AN25
PEX_RX7_N
AP25
PEX_RX8
AR25
PEX_RX8_N
AR26
PEX_RX9
AP26
PEX_RX9_N
AN26
PEX_RX10
AN28
PEX_RX10_N
AP28
PEX_RX11
AR28
PEX_RX11_N
AR29
PEX_RX12
AP29
PEX_RX12_N
AN29
PEX_RX13
AN31
PEX_RX13_N
AP31
PEX_RX14
AR31
PEX_RX14_N
AR32
PEX_RX15
AR34
PEX_RX15_N
AP34
PEX_TX0
AL17
PEX_TX0_N
AM17
PEX_TX1
AM18
PEX_TX1_N
AM19
PEX_TX2
AL19
PEX_TX2_N
AK19
PEX_TX3
AL20
PEX_TX3_N
AM20
PEX_TX4
AM21
PEX_TX4_N
AM22
PEX_TX5
AL22
PEX_TX5_N
AK22
PEX_TX6
AL23
PEX_TX6_N
AM23
PEX_TX7
AM24
PEX_TX7_N
AM25
PEX_TX8
AL25
PEX_TX8_N
AK25
PEX_TX9
AL26
PEX_TX9_N
AM26
PEX_TX10
AM27
PEX_TX10_N
AM28
PEX_TX11
AL28
PEX_TX11_N
AK28
PEX_TX12
AK29
PEX_TX12_N
AL29
PEX_TX13
AM29
PEX_TX13_N
AM30
PEX_TX14
AM31
PEX_TX14_N
AM32
PEX_TX15
AN32
PEX_TX15_N
AP32
PEX_REFCLK
AR16
PEX_REFCLK_N
AR17
PEX_RST_N
AM16
XTAL_IN
B1
XTAL_OUT
B2
XTAL_OUTBUFF
D1
XTAL_SSIN
D2
GPIO0 K1
GPIO1 K2
GPIO2 K3
GPIO3 H3
GPIO4 H2
GPIO5 H1
GPIO6 H4
GPIO7 H5
GPIO8 H6
GPIO9 J7
GPIO10 K4
GPIO11 K5
GPIO12 H7
MIOA_D0_NC N1
MIOA_D1_NC P4
MIOA_D2_NC P1
MIOA_D3_NC P2
MIOA_D4_NC P3
MIOA_D5_NC T3
MIOA_D6_NC T2
MIOA_D7_NC T1
MIOA_D8_NC U4
MIOA_D9_NC U1
MIOA_D10_NC U2
MIOA_D11_NC U3
MIOA_HSYNC_NC N3
MIOA_VSYNC_NC L3
MIOA_CLKOUT_NC R4
MIOA_CLKOUT_NC_N T4
MIOB_HSYNC_NC W1
MIOB_VSYNC_NC W2
MIOB_DE_NC Y5
MIOB_CTL3_NC W3
MIOB_CLKIN_NC AE1
MIOB_CLKOUT_NC V4
MIOB_CLKOUT_NC_N W4
MIOB_VREF_NC AF1
DACA_HSYNC AM13
DACA_VSYNC AL13
DACA_RED AM15
DACA_BLUE AL14
DACA_GREEN AM14
DACA_RSET AK13
DACA_VREF AK12
PEX_TSTCLK_OUT
AJ17
PEX_TSTCLK_OUT_N
AJ18
I2CS_SDA
E1
I2CA_SCL
G1
I2CA_SDA
G4
I2CB_SCL
G3
I2CB_SDA
G2
I2CC_SCL
E3
I2CC_SDA
E4
GPIO13 J4
GPIO14 J6
I2CS_SCL
E2
GPIO15 L1
GPIO16 L2
GPIO17 L4
GPIO18 M4
GPIO19 L7
GPIO20 L5
GPIO21 K6
GPIO22 L6
GPIO23 M6
MIOA_D12_NC R6
MIOA_D13_NC T6
MIOA_D14_NC N6
MIOA_CLKIN_NC N4
MIOB_D14_NC Y6
PEX_TERMP
AG21
I2CH_SCL
F6
I2CH_SDA
G6
DACB_RED AK4
DACB_GREEN AL4
DACB_BLUE AJ4
DACB_VREF AK6
DACB_RSET AH7
PEX_CLKREQ_N
AR13
DACB_HSYNC AM1
DACB_VSYNC AM2
MIOB_D0_NC Y1
MIOB_D1_NC Y2
MIOB_D2_NC Y3
MIOB_D3_NC AB3
MIOB_D4_NC AB2
MIOB_D5_NC AB1
MIOB_D6_NC AC4
MIOB_D7_NC AC1
MIOB_D8_NC AC2
MIOB_D9_NC AC3
MIOBD_10_NC AE3
MIOB_D11_NC AE2
MIOB_D12_NC U6
MIOB_D13_NC W6
MIOACAL_PD_VDDQ_NC U5
MIOBCAL_PD_VDDQ_NC AA7
MIOACAL_PU_GND_NC T5
MIOBCAL_PU_GND_NC AA6
MIOA_DE_NC N2
MIOA_CTL3_NC P5
MIOA_VREF_NC N5
PLLVDD
AE9
SP_PLLVDD
AF9
VID_PLLVDD
AD9
DACA_VDD AJ12
DACB_VDD AG7
GPIO24 M7
Y3 OPT@
27MHZ_16PF_X5H027000FG1H
Y3 OPT@
27MHZ_16PF_X5H027000FG1H
12
C278 0.1U_0402_10V7KOPT@C278 0.1U_0402_10V7KOPT@
1 2
C273 0.1U_0402_10V7KOPT@C273 0.1U_0402_10V7KOPT@
1 2
C287OPT@
0.1U_0402_16V4Z
C287OPT@
0.1U_0402_16V4Z
12
Q16B
DMN66D0LDW-7_SOT363-6
OPT@Q16B
DMN66D0LDW-7_SOT363-6
OPT@
34
5
R345 OPT@ 2.2K_0402_5%R345 OPT@ 2.2K_0402_5%
1 2
R763
0_0402_5%
@
R763
0_0402_5%
@12
R358
OPT@
10K_0402_5%R358
OPT@
10K_0402_5%
1 2
R368 OPT@ 10K_0402_5%R368 OPT@ 10K_0402_5%
12
C289OPT@
0.1U_0402_16V4Z
C289OPT@
0.1U_0402_16V4Z
12
C284OPT@
22U_0805_6.3V6M
C284OPT@
22U_0805_6.3V6M
12
R352 OPT@ 2.2K_0402_5%
R352 OPT@ 2.2K_0402_5%
1 2
C266 0.1U_0402_10V7KOPT@C266 0.1U_0402_10V7KOPT@
1 2
G
D
S
Q68
2N7002H_SOT23-3
OPT@
G
D
S
Q68
2N7002H_SOT23-3
OPT@
2
13
C263 0.1U_0402_10V7KOPT@C263 0.1U_0402_10V7K