Compal LA 7741P Schematics. Www.s Manuals.com. R0.1 Schematics
User Manual: Motherboard Compal LA-7741P QAL70, Dalmore 13 UMA - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 57
| Download | |
| Open PDF In Browser | View PDF |
A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : QAL70
LA-7741P(DAB00000800)
PCB NO :
BOM P/N : 4619EO31L01 TPM ;4519EO31L02 TPM/TAA
GPIO MAP:
1
Rev0.9
Dalmore 13 UMA
2
@
2
Ivy Bridge + Panther POINT
2011-06-23
REV : 0.1 (X00)
@ : Nopop Component
CONN@ : Connector Component
3
3
MB Type
BOM P/N
TPM EN/ TCM DIS
1@
3@
TPM DIS/ TCM EN
2@
4@
TPM DIS/ TCM DIS
2@
3@
TAA
@TAA
SPI ON BOARD
@SPI
4
4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number
DA80000I700
Description
Compal Electronics, Inc.
PCB 0FH LA-6562P REV0 M/B UMA
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Cover Sheet
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
E
1
of
56
A
B
C
D
E
Block Diagram
DDRIII-DIMM X2
Memory BUS (DDR3)
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1333/1600 MHz
1
1
Ivy Bridge
On IO board
BGA 2C 1023P
VGA
CRT CONN
For MB/DOCK
Video Switch
PI3V713-AZLEX
VGA
BT 4.0
HDMI CONN
DOCKING PORT
DMI2
Lane x 8
Lane x 4
VGA
DPB
INTEL
DPC
DPD
Panther POINT-M
Camera
USB
SATA Repeater
PS8511B
SATA
E-SATA
USB 2.0 Port
BGA 989P
LVDS CONN
USB3.0/2.0
LVDS
SATA5
DOCK LAN
USB3.0 [4]
SDXC/MMC
Card Reader
PI5USB1457A USB
Power Share
PCIE x1
OZ600FJ0LN
PCIE5
1/2 Mini Card
PP
USB10
PCIE2
1/2 Mini Card Full Mini Card
WLAN/WiFi
WWAN
USB6
USB4
SPI
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
DOCK LAN
China TCM1.2
SSX44B
LPC BUS
SATA
33MHz
W25Q64BVSSIG
HDA Codec
92HD90B3
SATA Repeater
Combo Jack
RFID
Fingerprint
CONN
FP_USB
FFS LNG3DM
Dig.
MIC
PCIE4
LED
E-Module
Trough LVDS Cable
BC BUS
BC BUS
PWM FAN
To Docking side
USB7
WiFi ON/OFF
DC/DC Interface
3
on IO board
USH Module
SMSC SIO
ECE5048
RJ45
HDD
16M 4K sector
DAI
PCH XDP Port
4
INT.Speaker
W25Q32BVSSIG
USH
BCM5882
CPU XDP Port
LAN SWITCH
PI3L720
Parade PS8520B
64M 4K sector
USB5
TDA8034HN
USB3.0/2.0+PS
Intel Lewisville
82579LM
3
Smart Card
USB3.0
HD Audio I/F
Option
PCIE1
PS8710B USB3.0
Repeater
PCI Express BUS 100MHz
PCI Express BUS 100MHz
PCIE3
2
USB3.0
USB2.0 [3,8]
EXPRESS
Card
Trough Cable
USB3.0
DAI
2
FDI
SMSC
SMSC KBC
MEC5055
4021
4
Discrete TPM
AT97SC3204
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
TP CONN
UMA Block Diagram
KB CONN
Size
B
Rev
0.1
LA-7741
Date:
A
Document Number
C
D
Thursday, June 23, 2011
2
Sheet
E
of
56
5
4
3
2
POWER STATES
SUS
PLANE
RUN
PLANE
ON
ON
ON
ON
HIGH
ON
ON
ON
HIGH
HIGH
ON
ON
LOW
LOW
HIGH
ON
HIGH
HIGH
LOW
ON
SLP
S4#
SLP
S5#
SLP
A#
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
S4 (Suspend to DISK) / M3
LOW
LOW
S5 (SOFT OFF) / M3
LOW
S3 (Suspend to RAM) / M-OFF
LOW
State
D
M
PLANE
SLP
S3#
Signal
ALWAYS
PLANE
USB PORT#
CLOCKS
JUSB1 (Right side )
ON
1
JUSB2 (Rear Left side)
OFF
OFF
2
NA
OFF
OFF
OFF
3
MLK DOCK
ON
OFF
OFF
OFF
4
WLAN
OFF
ON
OFF
OFF
5
WWAN
6
JMINI3(PP)
7
USH->BIO
8
DOCKING
9
JESATA1 ( right side)
10
Express card
11
Bluetooth
12
Camera
13
NA
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
PCH
PM TABLE
power
plane
+15V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+5V_ALW
+1.5V_MEM
+3.3V_RUN
+1.05V_M +1.05V_M
+3.3V_ALW_PCH
+1.8V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
+3.3V_M
(M-OFF)
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
State
B
DESTINATION
0
S4 (Suspend to DISK) / M-OFF
C
1
SATA
DESTINATION
SATA 0
HDD
SATA 1
ODD/ E3 Module Bay
SATA 2
NA
SATA 3
NA
ESATA
S0
ON
ON
ON
ON
ON
SATA 4
S3
ON
ON
OFF
ON
OFF
SATA 5
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
D
USH
Dock
0
BIO
1
NA
PCI EXPRESS
DESTINATION
B
Lane 1
MINI CARD-1 WWAN
Lane 2
MINI CARD-2 WLAN
Lane 3
Express card
Lane 4
E3 Module Bay (USB3)
Connetion
Lane 5
1/2vMINI CARD-3 PCIE
Port B
MB HDMI Conn
Lane 6
MMI
Port C
Dock DP port 2
Lane 7
10/100/1G LOM
Port D
Dock DP port 1
Lane 8
None
need to update Power Status and PM
Table
UMA DP/HDMI Port
A
C
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Index and Config.
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
3
of
56
EN_INVPWR
3
FDC654P
Q21
2
1
MODC_EN
4
HDDC_EN
5
+BL_PWR_SRC
D
D
ADAPTER
+PWR_SRC
BATTERY
1.05V_VTTPWRGD
+VCC_SA
TPS51461RGER
(PU13)
SI3456BDV
(Q27)
SI3456BDV
(Q30)
+5V_HDD
+5V_MOD
ALWON
+15V_ALW
C
RT8205LZQW
(PU2)
CHARGER
+5V_ALW
C
RUN_ON
TPS22966DPUR
(U78)
+VCC_CORE
+1.5V_MEM
CPU1.5V_S3_GATE
A
AO4728
(QC3)
+0.75V_DDR_VTT
+1.8V_RUN +1.05V_RUN_VTT
RUN_ON
NTGS4141N
(Q59)
SI3456
(Q49)
S13456
(Q54)
SI3456
(Q34)
+3.3V_WLAN
+3.3V_ALW_PCH
+3.3V_SUS
+3.3V_LAN
M_ON
AUX_ON
SI3456
(Q38)
(PU17)
RUN_ON
SUS_ON
(PU7)
TPS51212DSCR
+5V_RUN
TPS22966DPUR
(U78)
SI3456
(Q58)
B
SIO_SLP_A#
0.75V_DDR_VTT_ON
DDR_ON
1.05V_0.8V_PWROK
B
SN1003055
SY8033BDBC
(PU15)
+3.3V_RUN
+3.3V_M
+1.05V_M
RUN_ON
RT8207MZQW
(PU16)
CPU_VTT_ON
RT8207MZQW
(PU16)
RUN_ON
MAX17511
(PU9)
PCH_ALW_ON
AUX_EN_WOWL
+3.3V_ALW
Pop option
Pop option
+1.0V_LAN
+3.3V_M
SI4164
(Q63)
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
+1.5V_CPU_VDDQ
+1.05V_RUN
+1.5V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Power Rail
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
4
of
56
5
4
3
2
1
@ 2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
@ 2.2K
H14
MEM_SMBCLK
C9
MEM_SMBDATA
202
2N7002
200
DIMMA
SMBUS Address [A0]
DIMMB
SMBUS Address [A4]
2N7002
2.2K
PCH
D
202
+3.3V_LAN
2.2K
M16
C8
LAN_SMBCLK
28
G12
LAN_SMBDATA
31
53
SML1_SMBCLK
A5
D
SMBUS Address [C8]
LOM
E14
SML1_SMBDATA
3A
200
2.2K
53
3A
2.2K
B4
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
+3.3V_ALW
SMBUS Address
127
129
DOCKING
2.2K
C
2.2K
1B
XDP2
51
2.2K
1A
SMBUS Address [TBD]
+3.3V_ALW_PCH
B6
1A
XDP1
51
2.2K
SMBUS Address [TBD]
2.2K
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
2.2K
+3.3V_RUN
14
13
G Sensor
SMBUS Address [3B]
+3.3V_ALW
C
B5
LCD_SMBCLK
30
A4
LCD_SMBDAT
32
WWAN
1B
SMBUS Address [TBD]
2.2K
KBC
2.2K
1C
1C
A56
B59
PBAT_SMBCLK
PBAT_SMBDAT
+3.3V_ALW
100 ohm
7
100 ohm
6
BATTERY
CONN
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
2.2K
2.2K
A50
1E
B53
1E
+3.3V_ALW
M9
USH_SMBCLK
L9
USH_SMBDAT
B
B
2.2K
2.2K
MEC 5065
2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
+3.3V_SUS
7
8
Express card
SMBUS Address [TBD]
2.2K
2.2K
B50
1G
A47
1G
+3.3V_ALW
10
CHARGER_SMBCLK
9
CHARGER_SMBDAT
Charger
SMBUS Address [0x12]
2.2K
2.2K
2D
A
2D
B7
A7
+3.3V_ALW
29
BAY_SMBDAT
30
BAY_SMBCLK
E3 Module Bay
SMBUS Address [0xd2]
A
Compal Electronics, Inc.
Title
SMBUS TOPOLOGY
Size
Document Number
Rev
0.1
LA-7741
Date:
5
4
3
2
Thursday, June 23, 2011
Sheet
1
5
of
56
4
3
2
1
(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
U1I
1
+1.05V_RUN_VTT
RC2
24.9_0402_1%~D
D
M2
P6
P1
P10
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
N3
P7
P3
P11
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
K1
M8
N4
R2
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
K3
M7
P4
T3
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
U7
W11
W1
AA6
W6
V4
Y2
AC9
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
U6
W10
W3
AA7
W7
T4
AA3
AC8
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
<16>
<16>
<16>
<16>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
AA11
AC12
FDI_INT
<16> FDI_INT
FDI_LSYNC0
FDI_LSYNC1
<16> FDI_LSYNC0
<16> FDI_LSYNC1
U11
AA10
AG8
FDI0_FSYNC
FDI1_FSYNC
Intel(R) FDI
FDI_FSYNC0
FDI_FSYNC1
<16> FDI_FSYNC0
<16> FDI_FSYNC1
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
EDP_COMP
AF3
AD2
AG11
AG4
AF4
B
AC1
AA4
AE10
AE6
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP
AC3
AC4
AE11
AE7
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
PCI EXPRESS -- GRAPHICS
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI
C
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<16>
<16>
<16>
<16>
G3
G1
G4
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
2
U1A
PEG_COMP
PEG Compensation
PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS
NCTF
5
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48 TP_G48
D
C
T23 @
PAD~D
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
B
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
eDP Compensation
1
+1.05V_RUN_VTT
RC1
24.9_0402_1%~D
A
2
A
EDP_COMP
DELL CONFIDENTIAL/PROPRIETARY
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Sandy Bridge (1/6)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
6
of
56
5
4
3
2
1
+1.05V_RUN_VTT
2
2
200_0402_1%~D
3
<16> PM_DRAM_PWRGD
2
RUNPWROK_AND
4
1
1
@ RC124
1K_0402_1%~D
2 PM_DRAM_PWRGD_CPU
130_0402_1%~D
1
RC28
2
2
5
P
O
A
2
1
RC18
G
<39,40> RUNPWROK
+3.3V_ALW_PCH
RC12
200_0402_1%~D
SYS_PWROK_XDP
RC64 @
39_0402_5%~D
74AHC1G09GW_TSSOP5~D
CC65
0.1U_0402_25V6K~D
UC2
1 B
0.1U_0402_25V6K~D
2
+1.05V_RUN_VTT
+3.3V_ALW_PCH
1
+1.5V_CPU_VDDQ
+3.3V_ALW_PCH
CC156
1
JXDP1 @
XDP_PREQ#
XDP_PRDY#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Place near JXDP1
1 1
D
H_CPUPWRGD
<14,16> SIO_PWRBTN#_R
<9> CFG0
<16,39> SYS_PWROK
D
QC1 @
SSM3K7002FU_SC70-3~D
2
G
3
<11,42> RUN_ON_CPU1.5VS3#
1
RC51
RC61
RC71
@RC9
@
RC9
H_CPUPWRGD_XDP
2
2 1K_0402_1%~D CFD_PWRBTN#_XDP
2 0_0402_5%~D XDP_HOOK2
2 1K_0402_1%~D SYS_PWROK_XDP
0_0402_5%~D CLK_XDP
CLK_XDP#
RC8
2 1K_0402_5%~D XDP_RST#_R
XDP_DBRESET#
S
<17> PLTRST_XDP#
1
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
INTEL suggest RC64 and QC1 NO stuff by default
+1.05V_RUN_VTT
XDP_TCLK
H_THERMTRIP#
2
56_0402_5%~D
H_CATERR#
2
49.9_0402_1%~D
H_PROCHOT#
2
62_0402_5%~D
F49
PROC_SELECT#
<39> CPU_DETECT#
C57
PROC_DETECT#
<22> H_THERMTRIP#
2 H_THERMTRIP#_R
0_0402_5%~D
1
RC129
D45
PROCHOT#
BCLK_ITP
BCLK_ITP#
N59
N58
D44
CLK_XDP_ITP
CLK_XDP_ITP#
C
+1.05V_RUN_VTT
AT30
DDR3_DRAMRST#_CPU
1
@ RC48
@RC48
CLK_XDP
2
0_0402_5%~D
BF44
BE43
BG43
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
3
1
Max 500mils
TCK
TMS
TRST#
TDI
TDO
XDP_PRDY#
XDP_PREQ#
L56
L55
J58
XDP_TCLK
XDP_TMS
XDP_TRST#
M60
L59
XDP_TDI_R
XDP_TDO_R
1
RH107
1
RH106
2
0_0402_5%~D
2
0_0402_5%~D
CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>
DDR3_DRAMRST# <12>
QC2
BSS138W-7-F_SOT323-3~D
CLK_XDP_ITP
CLK_XDP_ITP#
RC50
4.99K_0402_1%~D
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
N53
N55
2
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
THERMTRIP#
PWR MANAGEMENT
B46
PM_DRAM_PWRGD_CPUBE45
PCH_PLTRST#_R
2
2 1K_0402_5%~D
1K_0402_5%~D
PRDY#
PREQ#
C48
2 VCCPWRGOOD_0_R
0_0402_5%~D
1
RC25
1
RC16 1
RC17
SM_DRAMRST#
250mils~2530 mils
H_PM_SYNC
<16> H_PM_SYNC
<18> H_CPUPWRGD
C45
CPU_DPLL
CPU_DPLL#
1
PECI
300mils ~1530mils
place RC129 near CPU
B
H_PROCHOT#_R
56_0402_5%~D
AG3
AG1
G
2
DPLL_REF_CLK
DPLL_REF_CLK#
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
D
1
RC57
place RC57 near CPU
2
2 0_0402_5%~D
0_0402_5%~D
CLK_XDP#
VR1 TOPOLOGY
<40,51,53> H_PROCHOT#
1
RC13 1
RC15
S
PECI_EC
CPU_DMI
CPU_DMI#
CATERR#
THERMAL
A48
J3
H2
BCLK
BCLK#
DDR_HVREF_RST
1
@ RH109
1
@ RH108
2
0_0402_5%~D
2
0_0402_5%~D
1
2
C49
DDR3
MISC
H_CATERR#
CLOCKS
MISC
<18> H_SNB_IVB#
<40>
2
CC177
0.047U_0402_16V4Z~D
1
<15> DDR_HVREF_RST_PCH
2
0_0402_5%~D
2
0_0402_5%~D
RC46
1
@RC47
@
RC47
<40> DDR_HVREF_RST_GATE
DDR_HVREF_RST <12>
M3 control
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
K58
G58
E55
E59
G55
G59
H60
J59
J61
XDP_DBRESET#_R
BPM#6
BPM#7
@
@
@
@
@
@
@
@
2
RC26
T128
T131
T129
T130
T125
T126
T107
T127
XDP_DBRESET#
1
0_0402_5%~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
B
XDP_DBRESET# <14,16>
@ T133 PAD~D
XDP_TDI_R
1
RC23
XDP_TDI
2
0_0402_5%~D
XDP_TDO_R
1
RC24
XDP_TDO
2
0_0402_5%~D
PU/PD for JTAG signals
@ T134 PAD~D
+3.3V_RUN
XDP_DBRESET#RC19 2
1 1K_0402_1%~D
XDP_TMS
RC27 2
1 51_0402_1%~D
XDP_TDI
+1.05V_RUN_VTT
T133 place near T107;T134 pleace near T127
IVY-BRIDGE_BGA1023~D
VCCPWRGOOD_0_R
4
PCH_PLTRST#_BUF
2 PCH_PLTRST#_R
43_0402_5%~D
SN74LVC1G07DCKR_SC70-5~D
RC45
200_0402_1%~D
2
1
2
1
2
1
RC10
RC43
25.5_0402_1%~D
2
1
5
RC42
140_0402_1%~D
2
1
NC VCC
A
GND
Y
RC130
10K_0402_5%~D
RC4
1
2
3
75_0402_1%~D
UC1
CC140
0.1U_0402_25V6K~D
2
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
1
+1.05V_RUN_VTT
1
<14,17> PCH_PLTRST#
For ESD concern, please put near CPU
+3.3V_RUN
Buffered reset to CPU
A
27
28
U1B
Follow check list 0.5
C
D
MOLEX_52435-2671
JTAG & BPM
1
@ RC126
1
@ RC128
1
RC44
OBSFN_A0
OBSFN_A1
GND
OBSDATA_A[0]
OBSDATA_A[1]
GND
OBSDATA_A[2]
OBSDATA_A[3]
GND
HOOK0
HOOK1
HOOK2
HOOK3
HOOK4
HOOK5
VCCOBS_AB
HOOK6
HOOK7
GND
TDO
TRSTn
TDI
TMS
TCK1
GND
GND
GND
TCK0
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
RC29 2
1 51_0402_1%~D
XDP_PREQ# @ RC32 2
1 51_0402_1%~D
XDP_TDO
RC35 2
1 51_0402_1%~D
XDP_TCLK
RC40 2
1
XDP_TRST#
RC41 2
1
51_0402_1%~D
51_0402_1%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Open drain buffer
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Sandy Bridge (2/6)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
7
of
56
5
4
3
2
1
U1D
U1C
<13> DDR_B_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2
<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
BD37
BF36
BA28
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
BE39
BD39
AT41
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
AU36
AV36
AY26
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
AT40
AU40
BB26
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
SA_CS#[0]
SA_CS#[1]
BB40
BC41
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
SA_ODT[0]
SA_ODT[1]
AY40
BA41
M_ODT0
M_ODT1
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0
M_ODT1
<12>
<12>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
<12>
<12>
DDR_A_MA[0..15] <12>
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2
<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#
D
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
BG39
BD42
AT22
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AV43
BF40
BD45
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
BA34
AY34
AR22
M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
BA36
BB36
BF27
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
SB_CS#[0]
SB_CS#[1]
BE41
BE47
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SB_ODT[0]
SB_ODT[1]
AT43
BG47
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS#[0..7]
<13>
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS[0..7]
<13>
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
DDR SYSTEM MEMORY B
<12> DDR_A_D[0..63]
DDR SYSTEM MEMORY A
D
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
M_ODT2
M_ODT3
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2
M_ODT3
<13>
<13>
C
DDR_B_MA[0..15] <13>
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
B
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Sandy Bridge (3/6)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
8
of
56
5
4
3
2
1
CFG Straps for Processor
1
CFG2
2
@ RC51
1K_0402_1%~D
D
D
U1E
+VCC_GFXCORE
+VCC_CORE
2 VCC_VAL_SNESE
49.9_0402_1%~D
1
1
@ RC120
C
VCC_VAL_SNESE
VSS_VAL_SNESE
H43
K43
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
H45
K45
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
EDS 1.0 RSVD_12 -> VCC_DIE_SENSE
TP_VCC_DIESENSE
PAD~D T22 @
2
@ RC71
100_0402_1%~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
1
@ RC121
2 VSS_VAL_SNESE
49.9_0402_1%~D
F48
VCC_DIE_SENSE
H48
K48
RSVD6
RSVD7
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24
B
1
@ RC96
1
@ RC97
2 +DIMM0_1_VREF_CPU
1K_0402_1%~D
2 +DIMM0_1_CA_CPU
1K_0402_1%~D
RSVD28
RSVD29
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BE7 +DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
BG7
RSVD30
RSVD31
RSVD32
RSVD33
N42
L42
L45
L47
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
M13
M14
U14
W14
P13
RSVD39
RSVD40
AT49
K24
RSVD41
RSVD42
RSVD43
RSVD44
AH2
AG13
AM14
AM15
RSVD45
N50
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG4
1
@ T17
@ T18
@ T15
@ T16
@ T9
@ T10
@ T12
@ T14
@ T20
@ T19
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
@ RC52
1K_0402_1%~D
2
2 VSSAXG_VAL_SENSE
49.9_0402_1%~D
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
Display Port Presence Strap
CFG4
TP_DC_TEST_A4
@ T121 PAD~D
DC_TEST_C4_D3
TP_DC_TEST_D1
TP_DC_TEST_A58
@ T118 PAD~D
@ T119 PAD~D
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
DC_TEST_A59_C59
DC_TEST_A61_C61
TP_DC_TEST_D61
TP_DC_TEST_BD61
CFG5
@ T120 PAD~D
@ T122 PAD~D
@ RC54
1K_0402_1%~D
DC_TEST_BE59_BE61
DC_TEST_BG59_BG61
TP_DC_TEST_BG58
TP_DC_TEST_BG4
C
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
1
1
@ RC123
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
1
@ T13 PAD~D
2
@ RC69
100_0402_1%~D
@ T11 PAD~D
@ RC53
1K_0402_1%~D
2
CFG0
2
<7>
RESERVED
2 VAXG_VAL_SENSE
49.9_0402_1%~D
1
1
@ RC122
@ T132 PAD~D
@ T123 PAD~D
DC_TEST_BE3_BG3
DC_TEST_BE1_BG1
TP_DC_TEST_BD1
@ T124 PAD~D
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
IVY-BRIDGE_BGA1023~D
B
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1
CFG7
2
@ RC56
1K_0402_1%~D
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately
following xxRESETB de assertion
0: PEG Wait for BIOS for training
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Sandy Bridge (4/6)
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
9
of
56
5
4
3
POWER
U1F
2
1
+1.05V_RUN_VTT
+VCC_CORE
8.5A
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
D
+1.05V_RUN_VTT
C
1
+1.05V_RUN_VTT
Note: Place the PU resistors close to CPU
RC61 close to CPU 300 - 1500mils
2
H_CPU_SVIDALRT#
1
RC61
2
43_0402_5%~D
VIDALERT_N
<51>
+3.3V_RUN
2
W16
W17
CAD Note: Place the PU
resistors close to CPU
RC63 close to CPU 300 - 1500mils
@
RC141
10K_0402_5%~D
Iccmax current changed for PDDG Rev0.7
1
VCCIO50
VCCIO51
VCCIO_SEL
BC22
1
RC140
2
0_0402_5%~D
H_CPU_SVIDALRT# must be routed between the
VIDSOUT and VIDSCLK lines to reduce cross
talk. 18 mils spacing to others.
AM25
AN22
1
A44
B43
C44
RC63
130_0402_1%~D
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
S0 Iccmax
Current (A)
VIDSCLK
<51>
VIDSOUT
1.05/1
8.5
0.0-1.1
33
VCCPLL
1.8
1.2
VDDQ
1.5
5
<51>
VCCSA
1
@ RC75
100_0402_1%~D
1
2
2
2 0_0402_5%~D
0_0402_5%~D
2
RC98
VCCSENSE
VSSSENSE
1
+1.05V_RUN_VTT
10_0402_1%~D
AN16
AN17
VTT_SENSE
VTT_GND
6
1.5
12-16
*
RC66
100_0402_1%~D
2
1
RC67 1
RC68
0.65-0.9
+1.5V_MEM
*
<51>
<51>
Description
5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT
RC70
100_0402_1%~D
<50>
<50>
1
RC133
2
10_0402_1%~D
A
DELL CONFIDENTIAL/PROPRIETARY
IVY-BRIDGE_BGA1023~D
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Sandy Bridge (5/6)
Size
4
3
2
Document Number
Rev
0.1
LA-7741
Date:
5
B
53
2
SENSE LINES
VCCIO_SENSE
VSS_SENSE_VCCIO
VCCSENSE_R
VSSSENSE_R
0.65-1.3
VAXG
Place RC66, RC70 ,RC133near CPU
F43
G43
VCC
VCCIO
+VCC_CORE
VCC_SENSE
VSS_SENSE
Voltage
+1.05V_RUN_VTT
1
SVID
VIDALERT#
VIDSCLK
VIDSOUT
Voltage Rail
1
VCCPQE[1]
VCCPQE[2]
CPU Power Rail Table
VCCP_PWRCTRL <50>
+1.05V_RUN_VTT
2
A
RC60
75_0402_1%~D
2
B
PEG IO AND DDR IO
C
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
QUIET
RAILS
D
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
CC573
1U_0402_6.3V6K~D
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
CORE SUPPLY
53A
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
Thursday, June 23, 2011
Sheet
1
10
of
56
4
+V_SM_VREF_CNT
POWER
VREF
1
2
1
2
1
2
1U_0402_6.3V6K~D
CC259
2
1
+
2
1U_0402_6.3V6K~D
CC258
2
1
2
1
CC167
2
1
2
1
1U_0402_6.3V6K~D
CC257
1
2
1
1U_0402_6.3V6K~D
CC256
2
2
1
1U_0402_6.3V6K~D
CC255
1
1
+1.5V_MEM
330U_D2_2VM_R6M~D
- 1.5V RAILS
1 0.1U_0402_10V7K~D
CC166
10U_0603_6.3V6M~D
DDR3
2
CC165
10U_0603_6.3V6M~D
SENSE
LINES
QUIET RAILS
2
VAXG_SENSE
VSSAXG_SENSE
SENSE LINES
VCCSA VID
lines
VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]
SA RAIL
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
VCCPLL[1]
VCCPLL[2]
VCCPLL[3]
1.8V RAIL
1
2
CC150
1U_0402_6.3V6K~D
CC254
2
1 0.1U_0402_10V7K~D
CC164
10U_0603_6.3V6M~D
2
1
2
1U_0402_6.3V6K~D
CC253
1
2
1 0.1U_0402_10V7K~D
CC149
CC163
10U_0603_6.3V6M~D
2
2
1
1U_0402_6.3V6K~D
CC252
2
1
6A
1U_0402_6.3V6K~D
CC260
2
1
BB3
BC1
BC4
CC175
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
CC261
2
2
1U_0402_6.3V6K~D
CC262
2
1
CC176
2
1
1U_0402_6.3V6K~D
CC263
2
1
1U_0402_6.3V6K~D
CC264
2
1
10U_0603_6.3V6M~D
CC183
2
1
10U_0603_6.3V6M~D
CC168
2
1
10U_0603_6.3V6M~D
CC169
2
1
10U_0603_6.3V6M~D
CC170
1
+
10U_0603_6.3V6M~D
CC171
330U_D2_2VM_R6M~D
CC172
A
2
CC174
1U_0402_6.3V6K~D
330U_D2_2.5VM_R6M~D
+VCC_SA
2
1
1 0.1U_0402_10V7K~D
2
CC162
10U_0603_6.3V6M~D
2
1.2A
1
2
1
2
CC179
AM28
AN26
VCCDQ[1]
VCCDQ[2]
1
2
CC574
1U_0402_6.3V6K~D
+1.8V_RUN
100_0402_1%~D
1
1
CC178
+1.5V_CPU_VDDQ
F45
G45
+
+1.5V_CPU_VDDQ
1
@RC76
@
RC76
100_0402_1%~D
1
2
<51> VCC_AXG_SENSE
<51> VSS_AXG_SENSE
1
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
1U_0402_6.3V6K~D
CC251
1
5A
+1.5V_CPU_VDDQ
CC161
10U_0603_6.3V6M~D
RC99
100_0402_1%~D
+V_SM_VREF should
have 20 mil trace width
CC180
10U_0603_6.3V6M~D
+VCC_GFXCORE
SM_VREF
1U_0402_6.3V6K~D
CC250
B
VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]
AY43
CC181
10U_0603_6.3V6M~D
AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61
C
RC100
+V_SM_VREF_CNT
+VCC_GFXCORE
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34
2
1
2
33A
+1.5V_CPU_VDDQ
1K_0402_1%~D
RC78
U1G
RUN_ON_CPU1.5VS3# <7,42>
GRAPHICS
1
<40> CPU1.5V_S3_GATE
2
U1H
1
2
2
4
2
0_0402_5%~D
6
1
@ RC79
5
@
1K_0402_1%~D
RC84
QC4A
DMN66D0LDW-7_SOT363-6~D
3
2
CC136
0.1U_0603_50V7K~D
2
0_0402_5%~D
RC143
330K_0402_1%~D
1
RC82
<16,27,35,39,42,48> SIO_SLP_S3#
QC4B
DMN66D0LDW-7_SOT363-6~D
D
1
1
2
1
2
RUN_ON_CPU1.5VS3
1
RC73
20K_0402_5%~D
RC72
100K_0402_5%~D
2
+1.5V_CPU_VDDQ
1
2
3
CC135
10U_0603_6.3V6M~D
RC74
100K_0402_5%~D
+1.5V_CPU_VDDQ Source
QC3
AO4728L_SO8~D
8
7
6
5
1
+1.5V_MEM
2
+PWR_SRC_S
1
+3.3V_ALW2
3
4
5
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS
AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13
B
IVY-BRIDGE_BGA1023~D
A
VCCSA_SENSE
U10
VCCSA_VID[0]
VCCSA_VID[1]
D48
D49
+VCCSA_SENSE <54>
RC139
1
1
RC138
0_0402_5%~D
2
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
VCCSA_VID_0 <54>
VCCSA_VID_1 <54>
Title
Sandy Bridge (6/6)
Size
Date:
IVY-BRIDGE_BGA1023~D
4
C
BC43
BA43
VDDQ_SENSE
VSS_SENSE_VDDQ
Document Number
Rev
0.1
LA-7741
5
D
3
2
Thursday, June 23, 2011
Sheet
1
11
of
56
4
2
0_0402_5%~D
1
2
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D26
DDR_A_D27
<8> DDR_A_D[0..63]
<8> DDR_A_DQS[0..7]
<8> DDR_A_MA[0..15]
<8> DDR_CKE0_DIMMA
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
2
1
2
CD6
1U_0402_6.3V6K~D
2
1
CD5
1U_0402_6.3V6K~D
1
CD4
1U_0402_6.3V6K~D
2
CD3
1U_0402_6.3V6K~D
1
<8> M_CLK_DDR0
<8> M_CLK_DDR#0
<8> DDR_A_BS0
<8> DDR_A_WE#
<8> DDR_A_CAS#
<8> DDR_CS1_DIMMA#
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
2
1
+
2
CD14
330U_SX_2VY~D
2
1
@ CD13
2
1
10U_0603_6.3V6M~D
CD51
2
1
10U_0603_6.3V6M~D
CD11
2
1
10U_0603_6.3V6M~D
CD10
2
1
10U_0603_6.3V6M~D
CD9
1
10U_0603_6.3V6M~D
CD8
2
10U_0603_6.3V6M~D
CD7
10U_0603_6.3V6M~D
1
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
Layout Note:
Place near JDIMM1.203,204
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
RD21
+0.75V_DDR_VTT
1
A
2
1
2
CD20
1U_0402_6.3V6K~D
2
1
CD19
1U_0402_6.3V6K~D
1
CD18
1U_0402_6.3V6K~D
2
CD17
1U_0402_6.3V6K~D
1
2
1
2
CD22
2.2U_0603_6.3V6K~D
2 10K_0402_5%~D
+3.3V_RUN
2
10K_0402_5%~D
CD21
0.1U_0402_25V6K~D
1
RD3
+0.75V_DDR_VTT
205
GND1
GND1
206
RD27
1K_0402_1%~D
DDR_A_D12
DDR_A_D13
<13> DDR3_DRAMRST#_R
DDR3_DRAMRST#_R
DDR3_DRAMRST#_R 1
RD28
2
1K_0402_1%~D
DDR3_DRAMRST# <7>
DDR_A_D20
DDR_A_D21
@ RD29 1
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
<7> DDR_HVREF_RST
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
@ RD30 1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
QD2
1 BSS138_NL_SOT23-3
C
+V_DDR_REFB_M3
DDR_HVREF_RST
DDR_A_MA2
DDR_A_MA0
M_ODT1
2 0_0402_5%~D
3
+DIMM0_1_CA_CPU
DDR_A_MA6
DDR_A_MA4
DDR_CS0_DIMMA#
M_ODT0
+V_DDR_REFA_M3
DDR_HVREF_RST
DDR_A_MA11
DDR_A_MA7
DDR_A_BS1
DDR_A_RAS#
QD1
1 BSS138_NL_SOT23-3
DDR_CKE1_DIMMA <8>
DDR_A_MA15
DDR_A_MA14
M_CLK_DDR1
M_CLK_DDR#1
2 0_0402_5%~D
3
+DIMM0_1_VREF_CPU
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
M_ODT0
<8>
+DIMM1_VREF_CA
M_ODT1
<8>
1
2
1
2
2
RD11
1
0_0402_5%~D
+V_DDR_REF
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
DDR_XDP_WAN_SMBDAT <13,15,27,34>
DDR_XDP_WAN_SMBCLK <13,15,27,34>
+0.75V_DDR_VTT
A
TYCO_2-2013022-2~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDRIII-SODIMM SLOT1
Size
4
3
2
Document Number
Rev
0.1
LA-7741
Date:
5
D
DDR_A_D14
DDR_A_D15
CD16
0.1U_0402_25V6K~D
DDR_A_D34
DDR_A_D35
B
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D6
DDR_A_D7
CD15
DDR_A_DQS#4
DDR_A_DQS4
+1.5V_MEM
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
+1.5V_MEM
DDR_A_DQS#0
DDR_A_DQS0
2.2U_0603_6.3V6K~D
DDR_A_D32
DDR_A_D33
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_A_D4
DDR_A_D5
G
DDR_A_MA12
DDR_A_MA9
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
+1.5V_MEM
2-3A to 1 DIMMs/channel
D
DDR_A_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
S
<8> DDR_A_BS2
DDR_CKE0_DIMMA
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
G
<8> DDR_A_DQS#[0..7]
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
D
DDR_A_D24
DDR_A_D25
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
S
All VREF traces should
have 10 mil trace width
Layout Note:
Place near JDIMM1
+1.5V_MEM
JDIMM1
DDR_A_DQS#1
DDR_A_DQS1
C
JDIMM1 H=4
+1.5V_MEM
CD2
0.1U_0402_25V6K~D
2
D
CD1
2.2U_0603_6.3V6K~D
1
+DIMM1_VREF_DQ
1
2
0_0402_5%~D
1
RD1
1
2
+V_DDR_REF
1
RD7
2
2
+V_DDR_REFA_M3
3
2
5
Thursday, June 23, 2011
Sheet
1
12
of
56
5
4
3
2
1
2-3A to 1 DIMMs/channel
+DIMM2_VREF_DQ
+1.5V_MEM
+1.5V_MEM
JDIMM2
2
0_0402_5%~D
+V_DDR_REF
1
RD4
2
0_0402_5%~D
1
2
D
1
2
CD24
0.1U_0402_25V6K~D
1
RD8
CD23
2.2U_0603_6.3V6K~D
+V_DDR_REFB_M3
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
<8> DDR_B_DQS#[0..7]
All VREF traces should
have 10 mil trace width
<8> DDR_B_D[0..63]
<8> DDR_B_DQS[0..7]
DDR_CKE2_DIMMB
<8> DDR_CKE2_DIMMB
<8> DDR_B_MA[0..15]
DDR_B_BS2
<8> DDR_B_BS2
C
DDR_B_MA12
DDR_B_MA9
Layout Note:
Place near JDIMM2
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
<8> M_CLK_DDR2
<8> M_CLK_DDR#2
+1.5V_MEM
DDR_B_MA10
DDR_B_BS0
<8> DDR_B_BS0
2
1
2
DDR_B_WE#
DDR_B_CAS#
<8> DDR_B_WE#
<8> DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
<8> DDR_CS3_DIMMB#
DDR_B_DQS#4
DDR_B_DQS4
+1.5V_MEM
DDR_B_D34
DDR_B_D35
2
1
+
2
CD36
330U_SX_2VY~D
2
1
@ CD35
10U_0603_6.3V6M~D
2
1
CD34
10U_0603_6.3V6M~D
2
1
CD33
10U_0603_6.3V6M~D
2
1
CD32
10U_0603_6.3V6M~D
2
1
CD31
10U_0603_6.3V6M~D
2
1
CD30
10U_0603_6.3V6M~D
1
CD29
10U_0603_6.3V6M~D
B
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
Layout Note:
Place near JDIMM2.203,204
DDR_B_D58
DDR_B_D59
2
1
2
2
CD42
1U_0402_6.3V6K~D
2
1
CD41
1U_0402_6.3V6K~D
1
CD40
1U_0402_6.3V6K~D
2
CD39
1U_0402_6.3V6K~D
1
1
2
1
2
CD44
2.2U_0603_6.3V6K~D
A
+0.75V_DDR_VTT
CD43
0.1U_0402_25V6K~D
+3.3V_RUN
1
10K_0402_5%~D
RD6
10K_0402_5%~D
2
RD5
+0.75V_DDR_VTT
1
+3.3V_RUN
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
GND1
CONN@
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D4
DDR_B_D5
JDIMMB H=8
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
D
DDR3_DRAMRST#_R <12>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <8>
DDR_B_MA15
DDR_B_MA14
C
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2
<8>
+DIMM2_VREF_CA
M_ODT3
<8>
DDR_B_D36
DDR_B_D37
1
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
2
1
2
3
1
0_0402_5%~D
+V_DDR_REF
B
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DDR_XDP_WAN_SMBDAT <12,15,27,34>
DDR_XDP_WAN_SMBCLK <12,15,27,34>
+0.75V_DDR_VTT
206
A
TYCO_2-2013297-2~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
2
RD15
DDR_B_DQS#5
DDR_B_DQS5
Title
DDRIII-SODIMM SLOT2
Size
2
Document Number
Rev
0.1
LA-7741
Date:
5
CD38
0.1U_0402_25V6K~D
DDR_B_D32
DDR_B_D33
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CD37
2.2U_0603_6.3V6K~D
CD28
1U_0402_6.3V6K~D
2
1
CD27
1U_0402_6.3V6K~D
1
CD26
1U_0402_6.3V6K~D
2
CD25
1U_0402_6.3V6K~D
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Thursday, June 23, 2011
Sheet
1
13
of
56
5
4
Keep CMOS
+3.3V_ALW_PCH
1
Keep ME RTC Registers
1
RH31
+RTC_CELL
3
2
1M_0402_5%~D
PCH_AZ_SYNC
1
QH7
SSM3K7002FU_SC70-3~D
+3.3V_ALW_PCH
1
2
JXDP2 @
+1.05V_RUN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
PXDP@
RH284 0_0402_5%~D
1
2
2
RSMRST#_XDP
@ RH283 1K_0402_5%~D
1
2 1.05V_0.8V_PWROK_R
1
2 PCH_PWRBTN#_XDP
RH21
0_0402_5%~D
PXDP@
<40,51> 1.05V_0.8V_PWROK
<7,16> SIO_PWRBTN#_R
INTEL HDA_SYNC
isolation circuit
+3.3V_ALW_PCH
1
1
PCH_AZ_SYNC
1
CH1 clsoe to JXDP2
CH6 clsoe to JXDP2
+5V_RUN
2
Open
PCH_AZ_SYNC_Q
RH66
1K_0402_1%~D
G
Clear ME RTC Registers
D
Shunt
S
ME_CLR1 TPM setting
2
Clear CMOS
Open
2
+1.05V_RUN
CH1
0.1U_0402_16V4Z~D
PXDP@
Shunt
3
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
CMOS setting
CH6
0.1U_0402_16V4Z~D
PXDP@
CMOS_CLR1
D
SIO_PWRBTN#_R
2
PXDP@ RH41
RH282 @
100K_0402_5%~D
RH38
330K_0402_1%~D
+3.3V_ALW_PCH
1
10K_0402_5%~D
RSMRST#_XDP
XDP_DBRESET#
<7,16> XDP_DBRESET#
PCH_INTVRMEN
PCH_RSMRST#_Q
1
PXDP@ RH24
<16,41> PCH_RSMRST#_Q
1
2
2
PCH_JTAG_TDO
@ RH39
@RH39
330K_0402_1%~D
2
PCH_JTAG_TDI
PCH_JTAG_TMS
RSMRST#_XDP
1K_0402_1%~D
PCH_JTAG_TCK
CH2
15P_0402_50V8J~D
2
1
PCH_RTCX1
D
27
28
MOLEX_52435-2671
@
CMOS1 SHORT PADS~D
1
2
1U_0402_6.3V6K~D
CH4
SHORT PADS~D
2
1U_0402_6.3V6K~D
RTCRST#
<29>
G22
SRTCRST#
INTRUDER#
K22
INTRUDER#
PCH_INTVRMEN
C17
INTVRMEN
PCH_AZ_BITCLK
N34
HDA_BCLK
PCH_AZ_SYNC
L34
HDA_SYNC
T10
SPKR
PCH_AZ_RST#
K34
HDA_RST#
PCH_AZ_CODEC_SDIN0
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
PCH_AZ_SDOUT
A36
HDA_SDO
PCH_GPIO33
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
SPKR
CMOS place near DIMM
C
<29> PCH_AZ_CODEC_SDIN0
<29> PCH_AZ_CODEC_SDOUT
<29> PCH_AZ_CODEC_SYNC
<29> PCH_AZ_CODEC_RST#
<29> PCH_AZ_CODEC_BITCLK
1
2 PCH_AZ_SDOUT
33_0402_5%~D
2 PCH_AZ_SYNC_Q
33_0402_5%~D
2 PCH_AZ_RST#
33_0402_5%~D
2 PCH_AZ_BITCLK
33_0402_5%~D
+3.3V_ALW_PCH
1
2
1K_0402_1%~D
@ RH287
<39>
1
RH50
ME_FWP
2
1K_0402_1%~D
+3.3V_ALW_PCH
2
1
@CH101
@
CH101
27P_0402_50V8J~D
1
RH29
1
RH26
1
RH27
1
RH25
<28> USB30_SMI#
USB30_SMI#
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
C38
A38
B37
C37
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
FWH4 / LFRAME#
D36
LPC_LFRAME#
LDRQ0#
LDRQ1# / GPIO23
E36
K36
LPC_LDRQ0#
LPC_LDRQ1#
V5
IRQ_SERIRQ
LPC
D20
SRTCRST#
2
2
PCH_RTCRST#
2
2
20K_0402_5%~D
2
20K_0402_5%~D
2
1M_0402_5%~D
1
RTCX2
SERIRQ
SATA_ODD_PRX_DTX_N1_C
SATA_ODD_PRX_DTX_P1_C
SATA_ODD_PTX_DRX_N1_C
SATA_ODD_PTX_DRX_P1_C
ODD/ E Module Bay
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
ESATA_PRX_DTX_N4_C
ESATA_PRX_DTX_P4_C
ESATA_PTX_DRX_N4_C
ESATA_PTX_DRX_P4_C
SATA_PRX_DKTX_N5_C <38>
SATA_PRX_DKTX_P5_C <38>
SATA_PTX_DKRX_N5_C <38>
SATA_PTX_DKRX_P5_C <38>
+1.05V_RUN
Y3
Y1
AB3
AB1
RH44 2
1 200_0402_1%~D
PCH_JTAG_TMS
H7
JTAG_TMS
SATAICOMPO
Y11
RH45 2
1 200_0402_1%~D
PCH_JTAG_TDI
K5
JTAG_TDI
RH43 2
1 200_0402_1%~D
PCH_JTAG_TDO
H1
JTAG_TDO
SPI_CS0#
PCH_SPI_CS1#
T1
SPI_CS1#
PCH_SPI_DO
V4
SPI_MOSI
PCH_SPI_DIN
U3
SPI_MISO
JTAG
SPKR
Y10
Low = Default
SATA_COMP
1
RH40
2
37.4_0402_1%~D
2
AB13
SATA3_COMP
1
RH42
2
49.9_0402_1%~D
SATA3RBIAS
AH1
RBIAS_SATA3
1
RH46
2
750_0402_1%~D
P3
SATA_ACT#
SATA0GP / GPIO21
V14
HDD_DET#_R
SATA1GP / GPIO19
P1
BBS_BIT0_R
3
4
SATALED#
/HOLD
7
/WP
CLK
6
GND
DIO
5
SPI_HOLD#
SPI_CLK64 1
@SPI R899
SPI_DO64
1
@SPI R901
2 PCH_SPI_CLK
33_0402_5%~D
2 PCH_SPI_DO
33_0402_5%~D
2 PCH_SPI_CS1_R#
0_0402_5%~D
2 SPI_DIN32
33_0402_5%~D
SPI_DO32
SPI_CLK32
PCH_SPI_CS0#
PCH_SPI_CLK
1
+3.3V_M
C1204
12P_0402_50V8J~D
A
2
1
RH290
3
<43>
1
QH1
2
0_0402_5%~D
HDD_DET#
<27>
B
PCH_SATA_MOD_EN#
<40>
BSS138W-7-F_SOT323-3~D
<7,17> PCH_PLTRST#
C745
0.1U_0402_25V6K~D
1
2
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DI
8
7
6
5
SPI_HOLD#
SPI_CLK32
SPI_DO32
1
R897
PCH_SPI_CLK
2
33_0402_5%~D
1
R900
2 PCH_SPI_DO
33_0402_5%~D
SPI_WP#_SEL_R
1
3
5
7
9
11
13
15
17
@
1
2
3
4
W25Q32BVSSIG_SO8~D
W25Q64CVSSIG_SO8~D
RF team request
SATA_ACT#
32Mb Flash ROM
PCH_SPI_CS1# 1
R936
PCH_SPI_DIN 1
R895
2
8
DO
+3.3V_RUN
U53 @SPI
VCC
/CS
DOCK
200 MIL SO8
U52 @SPI
1
High = No Reboot
E-SATA
+1.05V_RUN
SATA3COMPI
+3.3V_M
R891 @SPI
3.3K_0402_5%~D
64Mb Flash ROM
2
2 PCH_SPI_CS0_R#
0_0402_5%~D
2 SPI_DIN64
33_0402_5%~D
2 SPI_WP#_SEL_R
0_0402_5%~D
1
10K_0402_5%~D
SPKR
<37>
<37>
<37>
<37>
SATA3RCOMPO
C746 @SPI
0.1U_0402_25V6K~D
1
2
1
1
<39> SPI_WP#_SEL
PCH_SPI_CS0# 1
@SPI R935
PCH_SPI_DIN
1
@SPI R894
SPI_WP#_SEL
1
@R898
@
R898
200 MIL SO8
2
@ RH35
No Reboot Strap
AB12
BBS_BIT0 - BIOS BOOT STRAP BIT 0
@SPI R890
3.3K_0402_5%~D
C
+3.3V_RUN
BD82PPSM-QNHN-A0_BGA989~D
+3.3V_M
<28>
<28>
<28>
<28>
BBS_BIT0_R
1
2
RH52
4.7K_0402_5%~D
INTEL feedback 0302
RH30
10K_0402_5%~D
SPI
2
1
RH48
100_0402_1%~D
2
1
RH49
100_0402_1%~D
2
1
RH47
100_0402_1%~D
B
SATAICOMPI
SPI_CLK
1
8.2K_0402_5%~D
AM10
AM8
AP11
AP10
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
T3
IRQ_SERIRQ 2
RH28
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
JTAG_TCK
Y14
<32,39,40>
HDD
J3
PCH_SPI_CS0#
<39>
<39>
IRQ_SERIRQ
1
100K_0402_5%~D
PSATA_PRX_DTX_N0_C <27>
PSATA_PRX_DTX_P0_C <27>
PSATA_PTX_DRX_N0_C <27>
PSATA_PTX_DRX_P0_C <27>
PCH_JTAG_TCK
PCH_SPI_CLK
LPC_LDRQ0#
LPC_LDRQ1#
PCH_GPIO33 2
RH355
AM3
AM1
AP7
AP5
1 51_0402_1%~D
2
+3.3V_ALW_PCH_JTAG
+3.3V_RUN
LPC_LFRAME# <32,34,39,40>
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
RH59 2
RH288
0_0603_5%~D
LPC_LAD0 <32,34,39,40>
LPC_LAD1 <32,34,39,40>
LPC_LAD2 <32,34,39,40>
LPC_LAD3 <32,34,39,40>
1
1
CH5
1
C20
2
@
ME1
2
PCH_RTCX2
S
2
2
0_0402_5%~D
D
1
PCH_RTCX2_R 1
RH286
2
G
1
RTCX1
SATA 6G
1
RH22
1
RH23
1
RH11
+RTC_CELL
UH4A
A20
SATA
Low - Enable External VRs
2
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
CH3
15P_0402_50V8J~D
2
1
* High - Enable Internal VRs
RTC
INTVRMEN- Integrated SUS
1.1V VRM Enable
RH2
10M_0402_5%~D
IHDA
1
1
2
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
OBSFN_A0
OBSFN_A1
GND
OBSDATA_A[0]
OBSDATA_A[1]
GND
OBSDATA_A[2]
OBSDATA_A[3]
GND
HOOK0
HOOK1
HOOK2
HOOK3
HOOK4
HOOK5
VCCOBS_AB
HOOK6
HOOK7
GND
TDO
TRSTn
TDI
TMS
TCK1
GND
GND
GND
TCK0
JTAA1 CONN@
1
2 2
3
4 4
SPI_DIN32
5
6 6
7
8 8
PCH_SPI_CS1_R#
9
10 10
11 12 12
G1 G2
G3 G4
G5 G6
TAA config R895,R897,R900 need change to 0 ohm SD02800008L
A
14
16
18
TYCO_5-1775013-4~D
DELL CONFIDENTIAL/PROPRIETARY
Link Done
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
PCH (1/8)
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
14
of
56
5
4
3
2
1
+3.3V_RUN
2
QH5A
DMN66D0LDW-7_SOT363-6~D
MEM_SMBCLK
1
DDR_XDP_WAN_SMBCLK <12,13,27,34>
5
6
MEM_SMBDATA
10/100/1G LAN --->
MiniWWAN (Mini Card 1)--->
10/100/1G LAN --->
<33>
<33>
<33>
<33>
<31>
<31>
<31>
<31>
PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
<34> CLK_PCIE_MINI1#
<34> CLK_PCIE_MINI1
+3.3V_ALW_PCH
<34> MINI1CLK_REQ#
PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
Y40
Y39
2
RH81
1
10K_0402_5%~D
B
MiniWPAN (Mini Card 3)--->
Express card--->
MiniWLAN (Mini Card 2)--->
<33> CLK_PCIE_MMI#
<33> CLK_PCIE_MMI
+3.3V_RUN
<33> MMICLK_REQ#
<34> CLK_PCIE_MINI3#
<34> CLK_PCIE_MINI3
+3.3V_ALW_PCH
<34> MINI3CLK_REQ#
<35> CLK_PCIE_EXP#
<35> CLK_PCIE_EXP
+3.3V_ALW_PCH
<35> EXPCLK_REQ#
<34> CLK_PCIE_MINI2#
<34> CLK_PCIE_MINI2
+3.3V_ALW_PCH
<34> MINI2CLK_REQ#
J2
AB49
AB47
<31> CLK_PCIE_LAN#
<31> CLK_PCIE_LAN
LANCLK_REQ#
<31> LANCLK_REQ#
MMI Card--->
MINI1CLK_REQ#
M1
AA48
AA47
1
2
RH87
10K_0402_5%~D
MMICLK_REQ#
10K_0402_5%~D
MINI3CLK_REQ#
V10
Y37
Y36
2
RH152
1
A8
Y43
Y45
2
1
RH94
10K_0402_5%~D
EXPCLK_REQ#
10K_0402_5%~D
MINI2CLK_REQ#
L12
V45
V46
2
1
RH97
L14
AB42
AB40
+3.3V_ALW_PCH
1
RH98
2
10K_0402_5%~D
PEG_B_CLKRQ#
E6
V40
V42
T13
eModule Bay--->
A
<28> CLK_PCIE_EMB#
<28> CLK_PCIE_EMB
+3.3V_ALW_PCH
<28> EMBCLK_REQ#
V38
V37
2
RH104
1
10K_0402_5%~D
EMBCLK_REQ#
K12
AK14
AK13
<7> CLK_CPU_ITP#
<7> CLK_CPU_ITP
MEM_SMBCLK
C9
MEM_SMBDATA
+3.3V_ALW_PCH
SML1_SMBCLK
SML1_SMBDATA
A12
DDR_HVREF_RST_PCH
C8
LAN_SMBCLK
SML0DATA
G12
LAN_SMBDATA
SML1ALERT# / PCHHOT# / GPIO74
C13
PCH_GPIO74
SML1CLK / GPIO58
E14
SML1_SMBCLK
SML1DATA / GPIO75
M16
SML1_SMBDATA
M7
PCH_CL_CLK1
T11
PCH_CL_DATA1
SML0ALERT# / GPIO60
SML0CLK
CL_CLK1
DDR_HVREF_RST_PCH <7>
LAN_SMBDATA <31>
SML1_SMBCLK <40>
SML1_SMBDATA <40>
5
DDR_HVREF_RST_PCH 2
RH300
PCH_GPIO74
2
RH301
MEM_SMBCLK
2
RH302
MEM_SMBDATA
2
RH303
PCH_SMB_ALERT#
2
RH304
PEG_A_CLKRQ#
2
RH80
1
1K_0402_1%~D
1
10K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
10K_0402_5%~D
1
10K_0402_5%~D
LAN_SMBCLK
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
+3.3V_LAN
PCH_CL_CLK1 <34>
PCH_CL_DATA1 <34>
CL_RST1#
P10
PCH_CL_RST1#
2
RH305
2
RH306
M10
PEG_A_CLKRQ#
PCH_CL_RST1# <34>
CLK_BUF_DMI#
CLK_BUF_DMI
1
RH74 1
RH75
CLK_BUF_BCLK
2
2 10K_0402_5%~D
10K_0402_5%~D
1
2
RH91
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
PCIECLKRQ5# / GPIO44
CLKIN_PCILOOPBACK
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
AB37
AB38
AV22
AU22
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
AM12
AM13
BF18
BE18
CLK_BUF_DMI#
CLK_BUF_DMI
BJ30
BG30
CLK_BUF_BCLK
CLK_BUF_BCLK
G24
E24
CLK_BUF_DOT96#
CLK_BUF_DOT96
AK7
AK5
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
K45
CLK_PCH_14M
H45
CLK_PCI_LOOPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
10K_0402_5%~D
1
RH76 1
RH77
2
2 10K_0402_5%~D
10K_0402_5%~D
CLK_BUF_CKSSCD#
1
CLK_BUF_CKSSCD
RH78 1
RH79
2
2 10K_0402_5%~D
10K_0402_5%~D
CLK_PCH_14M
2
1
RH183
10K_0402_5%~D
CLOCK TERMINATION for FCIM and need close to PCH
B
CLK_PCI_TPM_TCM
CLK_SIO_14M
PCLK_80H
1
2
1
2
1
RF request
2
CLK_PCI_LOOPBACK <17>
2
RH309
1
0_0402_5%~D
RH99
1M_0402_5%~D
PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP
Y47
+XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
1
RH100
2
+1.05V_RUN
90.9_0402_1%~D
YH2
3
PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
PCI_TPM_TCM
2
RH311
2
1 22_0402_5%~D
F47
SIO_14M
RH313
2
1 22_0402_5%~D
CLK_SIO_14M <39>
CLKOUTFLEX2 / GPIO66
H47
CLK_80H
RH314
2
1 22_0402_5%~D
PCLK_80H
CLKOUTFLEX3 / GPIO67
K49
JETWAY_14M @ RH315
2
1 22_0402_5%~D
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
K43
BD82PPSM-QNHN-A0_BGA989~D
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
+3.3V_ALW_PCH
LAN_SMBCLK <31>
LAN_SMBDATA
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
C
CL_DATA1
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
1
RH298
1
RH299
CLK_PCI_TPM_TCM <32>
1
<34>
4
OUT
IN
GND
GND
1
2
CH19
12P_0402_50V8J~D
C
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
PERN3
PERP3
PETN3
PETP3
PCH_SMB_ALERT#
H14
27P_0402_50V8J~D
CH112 @
MMI --->
<34>
<34>
<34>
<34>
BG36
BJ36
AV34
AU34
SMBDATA
E12
27P_0402_50V8J~D
CH111 @
1/2vMINI CARD-3 PCIE
(Mini Card 3)--->
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
SMBCLK
CH18
12P_0402_50V8J~D
PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4
PERN2
PERP2
PETN2
PETP2
SMBALERT# / GPIO11
D
27P_0402_50V8J~D
CH113 @
E3 Module Bay--->
<28>
<28>
<28>
<28>
BE34
BF34
BB32
AY32
DDR_XDP_WAN_SMBDAT <12,13,27,34>
1
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PERN1
PERP1
PETN1
PETP1
Link
EXPRESS Card--->
<35>
<35>
<35>
<35>
BG34
BJ34
AV32
AU32
SMBUS
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
Controller
<34>
<34>
<34>
<34>
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
FLEX CLOCKS
MiniWLAN (Mini Card 2)--->
UH4B
<34>
<34>
<34>
<34>
4
QH5B
DMN66D0LDW-7_SOT363-6~D
CLOCKS
MiniWWAN (Mini Card 1)--->
3
2
Follow DG0.9 Device
down & Express/Mini
card topology
PCI-E*
D
2
25MHZ_10PF_Q22FA2380049900~D
1
JETWAY_CLK14M <32>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
PCH (2/8)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
15
of
56
A
3
1
RH142
PCH_PCIE_WAKE#
2
10K_0402_5%~D
D
PCH_DPWROK
1
RH113
2 PCH_RSMRST#_R
0_0402_5%~D
PCH_CRT_DDC_CLK
RESET_OUT#
Enabled (DEFAULT)
2 SYS_PWROK
0_0402_5%~D
1
@ RH321
PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT
<24>
D
<24>
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
PCH_RI#
2
10K_0402_5%~D
1
RH140
PCH_CRT_DDC_CLK
DSWODVREN - On Die DSW VR Enable
SIO_SLP_LAN#
2
10K_0402_5%~D
1
@ RH319
1
RH134
RH317
ME_SUS_PWR_ACK
2
10K_0402_5%~D
RH316
1
RH144
2.2K_0402_5%~D
RH133
SUS_STAT#/LPCPD#
2
10K_0402_5%~D
1
+3.3V_RUN
2.2K_0402_5%~D
1
1
1
RH132
1
@ RH318
2 PCH_CRT_BLU
150_0402_1%~D
2 PCH_CRT_GRN
150_0402_1%~D
2 PCH_CRT_RED
150_0402_1%~D
2 ENVDD_PCH
100K_0402_5%~D
1
RH131
1
+3.3V_ALW_PCH
2
2
4
2
5
ME_SUS_PWR_ACK_R 1
RH323
Disabled
2 SUSACK#_R
0_0402_5%~D
LOW: RH129 STUFFED,
RH127 UNSTUFFED
+3.3V_RUN
+3.3V_RUN
PCH_RSMRST#_Q
RH137
CLKRUN#
2
8.2K_0402_5%~D
1
@
1
RH322
2
10K_0402_5%~D
PCH_SDVO_CTRLCLK
2
RH351
PCH_SDVO_CTRLDATA
2
RH352
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
UH4C
UH4D
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
+1.05V_RUN
BJ24
1
RH111
1
RH112
DMI_COMP_R
2
49.9_0402_1%~D
RBIAS_CPY
2
750_0402_1%~D
BG25
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
FDI_LSYNC1
<39>
SUSACK#_R
2
0_0402_5%~D
1
@ RH114
SUSACK#
C12
XDP_DBRESET#
K3
1
RH116
SYS_PWROK_R
2
0_0402_5%~D
P12
<40> RESET_OUT#
1
RH117
PCH_PWROK
2
0_0402_5%~D
L22
<40> PM_APWROK
1
RH118
PM_APWROK_R
2
0_0402_5%~D
L10
<7,14> XDP_DBRESET#
SUSACK#
SYS_RESET#
B
<7,39> SYS_PWROK
<7> PM_DRAM_PWRGD
1
RH320
2
0_0402_5%~D
PM_DRAM_PWRGD_R
B13
<14,41> PCH_RSMRST#_Q
1
RH120
PCH_RSMRST#_R
2
0_0402_5%~D
C21
<40> ME_SUS_PWR_ACK
1
RH121
ME_SUS_PWR_ACK_R
2
0_0402_5%~D
K16
1
RH122
SIO_PWRBTN#_R
2
0_0402_5%~D
E20
<7,14> SIO_PWRBTN#_R
<40> SIO_PWRBTN#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
System Power Management
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
FDI_LSYNC0
BB10
FDI_LSYNC1
DSWODVREN
SLP_S3#
SLP_A#
N3
CLKRUN#
AC_PRESENT
PCH_BATLOW#
2
8.2K_0402_5%~D
1
RH139
H20
ACPRESENT / GPIO31
SLP_SUS#
BATLOW# / GPIO72
PMSYNCH
A10
RI#
SLP_LAN# / GPIO29
<6>
FDI_LSYNC1
<6>
+RTC_CELL
T56
PAD~D
T57
PAD~D
T58
PAD~D
D10
SIO_SLP_S5#
SIO_SLP_SUS#
AP14
H_PM_SYNC
K14
SIO_SLP_LAN#
<23> LCD_ACLK-_PCH
<23> LCD_ACLK+_PCH
FDI_LSYNC0
SUSCLK
G16
AF37
AF36
<23> LCD_A0-_PCH
<23> LCD_A1-_PCH
<23> LCD_A2-_PCH
<23> LCD_A0+_PCH
<23> LCD_A1+_PCH
<23> LCD_A2+_PCH
LCD_ACLK-_PCH
LCD_ACLK+_PCH
AK39
AK40
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
AN48
AM47
AK47
AJ48
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
AN47
AM49
AK49
AJ47
<40>
<32,39,40>
AH43
AH49
AF47
AF43
<24> PCH_CRT_BLU
<24> PCH_CRT_GRN
<24> PCH_CRT_RED
SIO_SLP_S5# <40>
PAD~D
SIO_SLP_S4# <39>
PAD~D
SIO_SLP_S3# <11,27,35,39,42,48>
PAD~D
SIO_SLP_A#
<24> PCH_CRT_HSYNC
<24> PCH_CRT_VSYNC
<39,42,49>
RH123
1
1
RH124
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
N48
P49
T49
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
T39
M40
20_0402_1%~D
2 HSYNC
2 VSYNC
20_0402_1%~D
M47
M49
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
CRT_IREF
<39>
PAD~D
H_PM_SYNC
SIO_SLP_LAN#
<7>
T43
T42
C
AP39
AP40
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
PAD~D
SIO_SLP_SUS#
AP43
AP45
AM42
AM40
DAC_IREF
CRT_IRTN
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
PCH_SDVO_CTRLCLK <25>
PCH_SDVO_CTRLDATA <25>
HDMIB_PCH_HPD
<25>
TMDSB_PCH_N2 <25>
TMDSB_PCH_P2 <25>
TMDSB_PCH_N1 <25>
TMDSB_PCH_P1 <25>
TMDSB_PCH_N0 <25>
TMDSB_PCH_P0 <25>
TMDSB_PCH_CLK# <25>
TMDSB_PCH_CLK <25>
PCH_DDPC_CTRLCLK <26>
PCH_DDPC_CTRLDATA <26>
AP47
AP49
AT38
DPC_PCH_DOCK_AUX# <26>
DPC_PCH_DOCK_AUX <26>
DPC_PCH_DOCK_HPD
<38>
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DPC_PCH_LANE_N0
DPC_PCH_LANE_P0
DPC_PCH_LANE_N1
DPC_PCH_LANE_P1
DPC_PCH_LANE_N2
DPC_PCH_LANE_P2
DPC_PCH_LANE_N3
DPC_PCH_LANE_P3
M43
M36
<38>
<38>
<38>
<38>
<38>
<38>
<38>
<38>
B
PCH_DDPD_CTRLCLK <26>
PCH_DDPD_CTRLDATA <26>
AT45
AT43
BH41
DPD_PCH_DOCK_AUX# <26>
DPD_PCH_DOCK_AUX <26>
DPD_PCH_DOCK_HPD
<38>
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
DPD_PCH_LANE_N0
DPD_PCH_LANE_P0
DPD_PCH_LANE_N1
DPD_PCH_LANE_P1
DPD_PCH_LANE_N2
DPD_PCH_LANE_P2
DPD_PCH_LANE_N3
DPD_PCH_LANE_P3
<38>
<38>
<38>
<38>
<38>
<38>
<38>
<38>
BD82PPSM-QNHN-A0_BGA989~D
RH126
1K_0402_0.5%~D
<31,39>
2
PCH_RI#
E10
<6>
<6>
SUS_STAT#/LPCPD#
T63
+3.3V_ALW_PCH
2 LVD_IBG
2.37K_0402_1%~D
1
AE48
AE47
FDI_FSYNC1
CLKRUN#
T62
<40> AC_PRESENT
RH344
Minimum speacing of 20mils for LVD_IBG
<6>
G8
SIO_SLP_A#
T45
P39
FDI_FSYNC0
N14
G10
T40
K47
PCH_PCIE_WAKE#
PCH_PCIE_WAKE#
SIO_SLP_S3#
LDDC_CLK_PCH
LDDC_DATA_PCH
AH45
AH47
AF49
AF45
PCH_DPWROK
SIO_SLP_S4#
P45
AF40
AF39
E22
F4
BIA_PWM_PCH
2 330K_0402_1%~D
PCH_DPWROK <39>
B9
H4
<23> LDDC_CLK_PCH
<23> LDDC_DATA_PCH
J47
M45
2 330K_0402_1%~D
T61
PWRBTN#
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<23> BIA_PWM_PCH
PANEL_BKEN_PCH
ENVDD_PCH
RH127 1
T60
SUSWARN#/SUSPWRDNACK/GPIO30
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<23> PANEL_BKEN_PCH
<23,39> ENVDD_PCH
@ RH129 1
T59
SLP_S4#
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
FDI_INT
AV14
A18
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
Digital Display Interface
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
LVDS
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
BE24
BC20
BJ18
BJ20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
CRT
<6>
<6>
<6>
<6>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BC24
BE20
BG18
BG20
1
<6>
<6>
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
<6>
<6>
<6>
<6>
C
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
<6>
<6>
<6>
<6>
BD82PPSM-QNHN-A0_BGA989~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PCH (3/8)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
16
of
56
5
4
3
2
1
+3.3V_RUN
1
RH324
PCI_PIRQA#
2
8.2K_0402_5%~D
1
RH325
PCI_PIRQB#
2
8.2K_0402_5%~D
UH4E
1
RH326
PCI_PIRQC#
2
8.2K_0402_5%~D
1
RH329
PCI_PIRQD#
2
8.2K_0402_5%~D
1
RH327
PCI_REQ1#
2
10K_0402_5%~D
1
RH330
LCD_CBL_DET#
2
10K_0402_5%~D
1
RH331
CAM_MIC_CBL_DET#
2
10K_0402_5%~D
1
RH328
BT_DET#
2
10K_0402_5%~D
PCH_GPIO3
2
10K_0402_5%~D
1
@ RH332
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD
1
PCI_GNT3#
Swap Override jumper
PCI_GNT#3
Low = A16 swap
High = Default
USB3RN1
USB3RN2
<38>
<36>
<36>
USB3RN4
USB3RP1
USB3RP2
<38>
<36>
<36>
USB3RP4
USB3TN1
USB3TN2
<38>
<36>
<36>
USB3TN4
USB3TP1
USB3TP2
<38>
USB3TP4
2
1
2
27P_0402_50V8J~D
CH110 @
2
1
27P_0402_50V8J~D
CH109 @
1
27P_0402_50V8J~D
CH108 @
B
27P_0402_50V8J~D
CH107 @
CLK_PCI_5048
CLK_PCI_MEC
CLK_PCI_DOCK
CLK_PCI_LOOPBACK
1
RF request
<34> PCIE_MCARD2_DET#
<41> BT_DET#
2
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PCI_REQ1#
C46
C44
E40
BT_DET#
BBS_BIT1
<23> LCD_CBL_DET#
<23> CAM_MIC_CBL_DET#
1
2
RH334
0_0402_5%~D
<27> HDD_FALL_INT
<32>
<33>
<7>
<31>
<28>
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
1
RH3351
RH3361
RH3371
RH3381
RH340
PLTRST_USH#
PLTRST_MMI#
PLTRST_XDP#
PLTRST_LAN#
PLTRST_EMB#
2
2
2
2
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
<39> CLK_PCI_5048
<40> CLK_PCI_MEC
<38> CLK_PCI_DOCK
<15> CLK_PCI_LOOPBACK
RH160
RH102
RH103
PAD~D
LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
FFS_PCH_INT
G42
G40
C42
D44
T104 @
K10
PCH_PLTRST#
2
2
1
2
RH105
PCI_GNT3#
D47
E42
F46
C6
PCI_5048
1
PCI_MEC
1 22_0402_5%~D
PCI_DOCK
2 22_0402_5%~D
22_0402_5%~D
PCI_LOOPBACKOUT
1
22_0402_5%~D
H49
H43
J48
K42
H40
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3TP1
USB3Tp2
USB3Tp3
USB3Tp4
USB30
A16 swap override Strap/Top-Block
<36>
<36>
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD23
RSVD24
AV5
AV10
RSVD25
AT8
RSVD26
RSVD27
AY5
BA2
RSVD28
RSVD29
AT12
BF3
USBRBIAS#
USBRBIAS
D
AY7
AV7
AU3
BG4
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
PCI
C
2
@ RH333
1K_0402_1%~D
USB
D
C
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBP0USBP0+
USBP1USBP1+
C33
USBRBIAS
USBP0USBP0+
USBP1USBP1+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
<36>
<36>
<36>
<36>
USBP3- <38>
USBP3+ <38>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <32>
USBP7+ <32>
USBP8- <38>
USBP8+ <38>
USBP9- <37>
USBP9+ <37>
USBP10- <35>
USBP10+ <35>
USBP11- <41>
USBP11+ <41>
USBP12- <23>
USBP12+ <23>
----->Right Side
----->Rear Left side
----->MLK DOCK
----->WLAN/WIMAX
----->WWAN/UWB
----->PP
----->USH
----->DOCK
----->Right side E-SATA
----->Express Card
----->Blue Tooth
----->Camera
+3.3V_ALW_PCH
INTEL feedback 0307
USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R
Within 500 mils
1
2
RH151
22.6_0402_1%~D
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#
B33
PME#
PLTRST#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
1
RH339
2
1
RH356
2
0_0402_5%~D
USB_OC4#
0_0402_5%~D
SIO_EXT_SMI#
USB_OC0#
<36>
USB_OC4#
<36>
RPH1
4
3
2
1
5
6
7
8
B
10K_1206_8P4R_5%~D
RPH2
4
5
3
6
2
7
1
8
10K_1206_8P4R_5%~D
SIO_EXT_SMI# <40>
BD82PPSM-QNHN-A0_BGA989~D
+3.3V_RUN
CH102
0.1U_0402_25V6K~D
1
2
O
A
4
PCH_PLTRST#_EC
BBS_BIT1
SATA_SLPD
(BBS_BIT0)
A
Boot BIOS Location
PCH_PLTRST#_EC <32,34,35,39,40>
0
0
LPC
0
1
Reserved (NAND)
1
0
PCI
1
1
SPI
TC7SH08FU_SSOP5~D
BBS_BIT1
1
2
B
@ RH342
1K_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
2
1
G
PCH_PLTRST#
3
<7,14> PCH_PLTRST#
UH3
P
5
Boot BIOS Strap
A
PCH (4/8)
Size
*
4
3
Rev
0.1
LA-7741
Date:
5
Document Number
2
Thursday, June 23, 2011
Sheet
1
17
of
56
5
4
3
2
1
+3.3V_ALW_PCH
2
+3.3V_RUN
CONTACTLESS_DET# 2
RH256
UH4F
SIO_EXT_SCI#
1
RH259
<32> USH_DET#
BMBUSY# / GPIO0
TACH4 / GPIO68
C40
CONTACTLESS_DET#
A42
TACH1 / GPIO1
TACH5 / GPIO69
B41
PCH_GPIO69
IO_LOOP#
H36
TACH2 / GPIO6
TACH6 / GPIO70
C41
PCIE_MCARD3_DET#
PCH_GPIO7
E38
TACH3 / GPIO7
TACH7 / GPIO71
C10
<39> SIO_EXT_WAKE#
SLP_ME_CSW_DEV#
<31> PM_LANPHY_ENABLE
C4
LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15
G2
GPIO15
PCH_GPIO16
U2
PCH_GPIO17
D40
PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
MEDIA_DET#
<30> MEDIA_DET#
EXPRCRD_DET#
<35> EXPRCRD_DET#
+3.3V_ALW_PCH
SLP_ME_CSW_DEV#
<39> SLP_ME_CSW_DEV#
2
RH177
1
RH354
SIO_EXT_WAKE#
1
10K_0402_5%~D
PCH_GPIO15
2
1K_0402_1%~D
A20GATE
PECI
SATA4GP / GPIO16
USB_MCARD1_DET#
<34> USB_MCARD1_DET#
<27>
FFS_INT2
<39> TEMP_ALERT#
<41> KB_DET#
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
V8
SATA2GP / GPIO36
PCH_GPIO37
M5
SATA3GP / GPIO37
TPM_ID0
N2
TPM_ID1
M3
FFS_INT2
V13
V3
KB_DET#
D6
PCH_GPIO36
1
10K_0402_5%~D
PCH_GPIO37
1
10K_0402_5%~D
2
@ RH273
PCH_GPIO17
1
1K_0402_1%~D
A44
VSS_NCTF_3
A45
VSS_NCTF_4
A46
VSS_NCTF_5
A5
VSS_NCTF_6
A6
VSS_NCTF_7
B3
VSS_NCTF_8
B47
B
2
@ RH265
PCH_GPIO16
1
10K_0402_5%~D
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
VSS_NCTF_9
BD1
VSS_NCTF_10
BD49
VSS_NCTF_11
BE1
VSS_NCTF_12
BE49
VSS_NCTF_13
BF1
VSS_NCTF_14
BF49
H_CPUPWRGD
THRMTRIP#
AY10
KB_DET#
1
10K_0402_5%~D
2
1.5K_0402_1%~D
SIO_A20GATE <40>
SIO_RCIN#
<40>
+3.3V_RUN
+1.05V_RUN_VTT
H_CPUPWRGD <7>
PCH_THRMTRIP#_R
INIT3_3V#
T14
INIT3_3V#
DF_TVS
AY1
DF_TVS
2
RH262
PAD~D
@
T106
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
NC_1
SIO_A20GATE
1
56_0402_5%~D
SIO_RCIN#
1
2
SLOAD / GPIO38
CH97
0.1U_0402_25V6K~D
SIO_EXT_SCI#
USH_DET#
2
RH158
2
RH203
1
10K_0402_5%~D
1
10K_0402_5%~D
1
RH263
1
RH164
2
10K_0402_5%~D
2
100K_0402_5%~D
C
AK10
P37
NC_1
PAD~D T108 @
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
VSS_NCTF_15
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
GPIO57
VSS_NCTF_17
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
+3.3V_ALW_PCH
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
BG2
VSS_NCTF_15
BG48
VSS_NCTF_16
BH3
VSS_NCTF_17
BH47
VSS_NCTF_18
BJ4
VSS_NCTF_19
BJ44
VSS_NCTF_20
BJ45
VSS_NCTF_21
BJ46
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ6
VSS_NCTF_24
C2
VSS_NCTF_25
C48
VSS_NCTF_26
D1
VSS_NCTF_27
D49
VSS_NCTF_28
E1
VSS_NCTF_29
E49
VSS_NCTF_30
F1
VSS_NCTF_31
F49
VSS_NCTF_32
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
B
PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
+VCCDFTERM
RH149 need to close to CPU
RH149
2.2K_0402_5%~D
BD82PPSM-QNHN-A0_BGA989~D
2
2
RH170
SIO_A20GATE
SIO_RCIN#
TS_VSS4
NCTF
2
RH174
2
RH172
A4
VSS_NCTF_2
1
RH260
AU16
AY11
VSS_NCTF_18
VSS_NCTF_1
P4
P5
GPIO35
PCH_GPIO36
TEMP_ALERT#
PCH_GPIO69
PCIE_MCARD3_DET# <34>
USB_MCARD2_DET# <34>
PROCPWRGD
RCIN#
<34> PCIE_MCARD1_DET#
A40
CONTACTLESS_DET# <32>
GPIO8
PM_LANPHY_ENABLE
CPU/MISC
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
T7
GPIO
2
<30> IO_LOOP#
SIO_EXT_SCI#_R
2
0_0402_5%~D
USH_DET#
1
<40> SIO_EXT_SCI#
RH353
1K_0402_1%~D
@
C
1
10K_0402_5%~D
D
SLP_ME_CSW_DEV#
1
D
1
RH53
4.7K_0402_5%~D
<7> H_SNB_IVB#
1
RH150
2
0_0402_5%~D
DF_TVS_R 1
RH358
DF_TVS
2
1K_0402_1%~D
+3.3V_RUN
+3.3V_RUN
1
PCH_GPIO36
1
10K_0402_5%~D
PCH_GPIO37
1
1K_0402_1%~D
PCH_GPIO16
2
10K_0402_5%~D
TEMP_ALERT#
1
10K_0402_5%~D
MEDIA_DET#
1
10K_0402_5%~D
PCH_GPIO7
2
10K_0402_5%~D
DMI & FDI Termination Voltage
IO_LOOP#
2
10K_0402_5%~D
TPM_ID1
TPM_ID1
0
0
0
1
China TPM
No TPM, No China TPM
1
2@ RH270
10K_0402_5%~D
TPM_ID0
4@ RH271
2.2K_0402_5%~D
USH1.0 (For SSI)
1
0
USH2.0
1
1
DF_TVS
Set to Vss when LOW
A
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
2
1
RH163
PCH_GPIO17
2
8.2K_0402_5%~D
2
TPM_ID0
1
RH269
3@ RH268
20K_0402_5%~D
2
1
1@ RH267
10K_0402_5%~D
1
A
2
@ RH171
2
@ RH173
1
RH272
2
RH266
2
RH181
1
RH178
2
+3.3V_RUN
PCH (5/8)
Size
Document Number
Rev
0.1
LA-7741
Date:
5
4
3
2
Thursday, June 23, 2011
Sheet
1
18
of
56
5
4
3
2
1
+3.3V_RUN
AN17
2
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
AN33
AN34
+3.3V_RUN
BH29
BG6
+1.05V_RUN
AP17
+1.05V_RUN_VTT
AU20
B
CRT
LVDS
AP37
VCCIO[24]
2
2
LH8
100NH_HK1608R10J-T_5%_0603~D
2
1
VCC3_3[7]
CH43
0.1U_0402_10V7K~D
V34
2
5
0.001
V5REF_Sus
5
0.001
Vcc3_3
3.3
0.228
VccADAC3
3.3
0.063
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.7
VccDMI
1.1
0.047
VccIO
1.05
3.711
VccASW
1.05
0.903
VccSPI
3.3
0.01
VccDSW3_3
3.3
0.001
VCCDFTERM
1.8
0.002
0.1uH inductor, 200mA
CPN: SHI0110BJ0L
+3.3V_RUN
VCCDMI[1]
AT16
AT20
+1.05V_RUN_VTT
1
VCCCLKDMI
AB36
+1.05V_RUN_VCCCLKDMI
1
2
CH50
1U_0402_6.3V6K~D
2 CH49
1U_0402_6.3V6K~D
2
1
@ RH205
0_0603_5%~D
1
2
VCCIO[25]
VCCIO[26]
VCCDFTERM[1]
VCC3_3[3]
VCCDFTERM[2]
VCCVRM[2]
VccAFDIPLL
AG16
+VCCDFTERM
AG17
+1.05V_RUN
VCCDFTERM[3]
PJP66
1
VCCDFTERM[4]
VCCSPI
AJ16
3.3
2 (mA)
3.3
0.095
VccSusHDA
3.3
0.01
VccVRM
1.5
2
0.167
VccClkDMI
1.05
0.07
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
+1.8V_RUN
1
AJ17
2
CH52
0.1U_0402_10V7K~D
+VCCSPI
V1
2
2
RH202
2
@ RH204
1
BD82PPSM-QNHN-A0_BGA989~D
+1.5V_RUN
VccRTC
VccSus3_3
C
INTEL feedback 0302
PAD-OPEN1x1m
VCCIO[27]
VCCDMI[2]
1
V33
V5REF
D
1
VCCVRM[3]
+1.05V_+1.5V_1.8V_RUN
AP16
VCCTX_LVDS[4]
2
0.001
+1.05V_+1.5V_1.8V_RUN
FDI
2
CH51
0.1U_0402_10V7K~D
1
AP36
1
S0 Iccmax
Current (A)
+3.3V_RUN
+1.8V_RUN_LVDS
1
AM38
Voltage
1.05
V_PROC_IO
+1.8V_RUN
CH106
10U_0603_6.3V6M~D
2
1
CH48
1U_0402_6.3V6K~D
2
1
CH47
1U_0402_6.3V6K~D
2
1
CH46
1U_0402_6.3V6K~D
1
CH45
1U_0402_6.3V6K~D
2
CH44
10U_0603_6.3V6M~D
1
VCCIO[16]
AN21
+1.05V_RUN
C
VCCIO[15]
2
AM37
VCCTX_LVDS[3]
VCC3_3[6]
HVCMOS
AN16
VCCTX_LVDS[2]
2
Voltage Rail
AK37
VCCAPLLEXP
DMI
2
@
VCCTX_LVDS[1]
AK36
VCCIO[28]
DFT / SPI
1
BJ22
VSSALVDS
2
1
CH105
22U_0805_6.3V6M~D
1UH_LB2012T1R0M_20%~D
VCCALVDS
U47
1
CH104
0.01U_0402_16V7K~D
+VCCAPLLEXP
2
CH40
10U_0603_6.3V6M~D
1
@ RH247
VSSADAC
1
CH36
10U_0603_6.3V6M~D
AN19
+1.05V_RUN
VCCADAC
U48
CH103
0.01U_0402_16V7K~D
+1.05V_RUN
PCH Power Rail Table
2
1
BLM18PG181SN1_0603~D
CH35
0.1U_0402_10V7K~D
2
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
+VCCADAC
CH34
0.01U_0402_16V7K~D
2
1
CH31
1U_0402_6.3V6K~D
2
1
CH33
1U_0402_6.3V6K~D
1
CH32
1U_0402_6.3V6K~D
2
D
CH30
10U_0603_6.3V6M~D
1
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
VCC CORE
UH4G
VCCIO
+1.05V_RUN
LH1
POWER
CH54
1U_0402_6.3V6K~D
1
0_0603_5%~D
1
0_0603_5%~D
+3.3V_M
+3.3V_RUN
B
INTEL feedback 0307
+1.05V_+1.5V_1.8V_RUN
2
RH197
1
0_0603_5%~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PCH (6/8)
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
19
of
56
4
3
2
1
+5V_ALW
POWER
AL24
+1.05V_M
C
2
1
2
CH69
1U_0402_6.3V6K~D
1
CH68
1U_0402_6.3V6K~D
2
2
CH67
1U_0402_6.3V6K~D
1
1
CH65
22U_0805_6.3V6M~D
2
CH64
22U_0805_6.3V6M~D
1
VCCASW[1]
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD31
W23
@
2
Note: If EMI concern, pop
with SHI00008S0L, 10UH +-20%
2
W24
CH74
1U_0402_6.3V6K~D
CH73
10U_0603_6.3V6M~D
+3.3V_RUN_VCC_CLKF33
1
1
2
0.022_0805_1%
W26
W29
W31
W33
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
Note: Place VCCDIFFCLKN with a trace
specially for XCLK_RCOMP (RH100.2)
1
2
N16
Y49
CH79
1U_0402_6.3V6K~D
BF47
V16
1
2
1
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
DCPSUS[4]
AN24
V5REF
P34
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCC3_3[2]
+
2
1
2
2
A22
1
2
1
+PCH_V5REF_RUN
VCCVRM[4]
VCCIO[13]
VCCIO[6]
VCCADPLLA
VCCADPLLB
VCCAPLLSATA
VCCVRM[1]
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCIO[2]
VCCIO[4]
1
CH63
0.1U_0402_10V7K~D
+5V_RUN +3.3V_RUN
C
RH213
10_0402_1%~D
DH3
RB751S40T1_SOD523-2~D
1
2
CH70
1U_0603_10V7K~D
+3.3V_RUN
+PCH_V5REF_RUN
1
P22
CH71
1U_0603_10V7K~D
1
AA16
2
W16
2
CH72
0.1U_0402_10V7K~D
+3.3V_RUN
T34
1
CH75
0.1U_0402_10V7K~D
AJ2
1
CH76
0.1U_0402_10V7K~D
AF13
+1.05V_RUN
1
AH13
2
AH14
CH77
1U_0402_6.3V6K~D
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN
AK1
B
LH5
@
10UH_LBR2012T100M_20%~D
1
2
AF14
1
AF11
+1.05V_RUN
@ CH80
10U_0603_6.3V6M~D
AC16
+1.05V_RUN
1
AC17
AD17
2
CH82
1U_0402_6.3V6K~D
+1.05V_M
DCPSUS[1]
DCPSUS[2]
VCCASW[22]
CPU
VCCASW[23]
VCCASW[21]
VCCSUSHDA
T21
V21
T19
P32
+3.3V_ALW_PCH
1
BD82PPSM-QNHN-A0_BGA989~D
CH90
1U_0402_6.3V6K~D
2
CRB 0.7 RH208,RH213 trace width 20mil.
DCPSST
VCCRTC
+PCH_V5REF_SUS
2
VCCSSC
V_PROC_IO
2
G
+3.3V_ALW_PCH
+3.3V_ALW_PCH
2
DCPRTC
DH2
RB751S40T1_SOD523-2~D
+1.05V_RUN
2
VCCASW[20]
+3.3V_ALW_PCH
+PCH_V5REF_SUS
+3.3V_RUN
VCCASW[19]
+5V_ALW_PCH
RH208
10_0402_1%~D
2
A
CH91
0.1U_0402_10V7K~D
DELL CONFIDENTIAL/PROPRIETARY
CH93
1U_0402_6.3V6K~D
2
1
CH95
220U_B2_2.5VM_R35M~D
1
CH92
1U_0402_6.3V6K~D
2
CH94
220U_B2_2.5VM_R35M~D
+
2
1
2
+3.3V_ALW_PCH
VCCASW[18]
+RTC_CELL
CH89
0.1U_0402_10V7K~D
LH6
10UH_LBR2012T100M_20%~D
1
2
1
BJ8
CH88
0.1U_0402_10V7K~D
1
CH85
4.7U_0603_6.3V6K~D
2
2
T17
V19
M26
VCCSUS3_3[1]
VCC3_3[4]
2
CH87
0.1U_0402_10V7K~D
1
CH86
0.1U_0402_10V7K~D
CH84
0.1U_0402_10V7K~D
1
VCCASW[17]
MISC
+VCCSST
2
1
AN23
VCC3_3[8]
HDA
AG33
CH96
1U_0402_6.3V6K~D
1
T26
VCCIO[3]
1
5
BD47
AF17
AF33
AF34
AG34
2 CH81
1U_0402_6.3V6K~D
1
1
2
LH7
10UH_LBR2012T100M_20%~D
VCCIO[34]
VCC3_3[1]
VCCASW[16]
RTC
2
+1.05V_RUN
P24
VCCSUS3_3[5]
SATA
+1.05V_RUN_VCCA_B_DPL
1
+1.05V_RUN_VTT
V24
VCCSUS3_3[6]
+3.3V_ALW_PCH
1
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCA_A_DPL
2
VCCSUS3_3[10]
V5REF_SUS
+1.05V_RUN
B
T24
V23
VCCIO[12]
CH78
0.1U_0402_10V7K~D
T23
VCCSUS3_3[9]
VCCIO[5]
+VCCRTCEXT
A
DCPSUS[3]
AA21
W21
1
RH215
VCCSUS3_3[8]
VCCIO[14]
AA19
AD29
+3.3V_RUN
VCCSUS3_3[7]
D
2
AL29
T29
VCC3_3[5]
VCCAPLLDMI2
2
1
2
2
T27
1
<42> ALW_ENABLE
1
BH23
VCCIO[33]
CH56
1U_0402_6.3V6K~D
2
+VCCAPLL_CPY_PCH
VCCIO[32]
1
P28
1
+1.05V_RUN
@
DCPSUSBYP
P26
2
+3.3V_RUN_VCC_CLKF33 T38
USB
1
CH58
10U_0603_6.3V6M~D
@ LH3
10UH_LBR2012T100M_20%~D
1
2
PCI/GPIO/LPC
V12
Clock and Miscellaneous
+1.05V_RUN
3
2
VCCIO[31]
QH4
SSM3K7002FU_SC70-3~D
1
VCCIO[30]
VCCDSW3_3
+1.05V_RUN
CH66
0.1U_0402_10V7K~D
T16
N26
CH60
0.1U_0402_10V7K~D
+VCCDSW3_3
VCCIO[29]
CH59
2
D
CH55
0.1U_0402_10V7K~D
VCCACLK
0.1U_0402_10V7K~D
AD49
1
S
1
D
2
0_0402_5%~D
2
0_0402_5%~D
RH278
20K_0402_5%~D
UH4J
1
RH201
1
@ RH253
CH98
0.1U_0402_10V7K~D
+3.3V_ALW_PCH
+3.3V_ALW2
+5V_ALW_PCH
2
5
Compal Electronics, Inc.
Title
PCH (7/8)
Size
Document Number
Rev
0.1
LA-7741
Date:
4
3
2
Thursday, June 23, 2011
Sheet
1
20
of
56
5
4
3
2
1
UH4I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
D
UH4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
C
B
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
BD82PPSM-QNHN-A0_BGA989~D
A
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
D
C
B
A
BD82PPSM-QNHN-A0_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
PCH (8/8)
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
21
of
56
5
4
3
2
+FAN1_VOUT
1
1
C
3
2
1
2
B
E Q12
MMBT3904WT1G_SC70-3~D
2
@
C266
100P_0402_50V8J~D
REM_DIODE1_N_4022
1
2
C219
22U_0805_6.3V6M~D
REM_DIODE1_P_4022
D
JFAN1 CONN@
FAN1_DET#
+FAN1_VOUT
FAN1_TACH_FB
D2
RB751S40T1_SOD523-2~D
Place under CPU
Place C266 close to the Q12 as possible
1
1
2
3
4
1
2
3
4
5
6
GND
GND
+3.3V_M
TYCO_2-1775293-4~D
Link Done
+5V_RUN
1
2
1
2
C738
0.1U_0402_25V6K~D
1
2
3
6
13
+3.3V_M
2 VDD_PWRGD
10K_0402_5%~D
1
R389
3
1
1
3
2
C
Q14
MMBT3904WT1G_SC70-3~D
@
2
B
E
THERMATRIP2#
18
THERMATRIP3#
23
24
DN1/THERM
DP1/VREF_T
SYS_SHDN#
19
2
C271
1
2200P_0402_50V7K~D
REM_DIODE2_N_4022
REM_DIODE2_P_4022
26
27
DN2/DP4
DP2/DN4
POWER_SW#
20
POWER_SW#
30
29
DP3/DN5
DN3/DP5
ACAVAIL_CLR
ATF_INT#/BC_IRQ#
21
9
BC_INT#_EMC4022
31
25
VCP
VIN
<53> MAX8731_IINP
2
VCP2
1
4.7K_0402_5%~D
R387
VSET_4022
28
FAN1_TACH_FB
+3.3V_M
10
1
11
1
17
THERMTRIP3#
REM_DIODE1_N_4022
REM_DIODE1_P_4022
2
Q13
MMBT3904WT1G_SC70-3~D
REM_DIODE2_N_4022
R395
8.2K_0402_5%~D
THERMTRIP2#
2
2200P_0402_50V7K~D
E
C
VDDH
VDDH
VDDL
VDD_PWRGD
1
C270
B
2
C277
@C272
@
C272
100P_0402_50V8J~D
100P_0402_50V8J~D
C
1
2
R426
1
10K_0402_5%~D
FAN1_DET#
2
R402
1
10K_0402_5%~D
U6
REM_DIODE2_P_4022
1
1
10K_0402_5%~D
Change to EMC4021 for cost saving
2
(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14
(2) DP5/DN5 for Skin on Q13, place Q13 close to Vcore VR choke.
2
R385
FAN1_TACH_FB
+3.3V_RUN
C305
10U_0603_6.3V6M~D
C275
0.1U_0402_25V6K~D
2
C276
10U_0805_10V6K~D
1
BC_INT#_EMC4022
FAN1_DET#
15
R404
10K_0402_5%~D
FAN_OUT
FAN_OUT
VSET
TACH/GPIO1
SMCLK/BC_CLK
SMDATA/BC_DATA
THERM_STP#
5
4
1
@R390
@
R390
2
47K_0402_1%~D
C
ACAV_IN
<40,53,55>
BC_INT#_EMC4022 <40>
+FAN1_VOUT
8
7
BC_CLK_EMC4022 <40>
BC_DAT_EMC4022 <40>
GPIO2
GPIO3/PWM/THERMTRIP_SIO
+3.3V_M
1
R388
22_0402_5%~D
3V_PWROK#
1
2
C274
1U_0402_6.3V6K~D
B
RTC_PWR3V
2
R393
+VCC_4022
14
22
33
1
16
+RTC_CELL
TEST1
TEST2
VSS
+VCC_4022
+ADDR_XEN
1
4.7K_0402_5%~D
2
VDD
ADDR_MODE/XEN
1
32
EMC4022-1-EZK-TR_QFN32_5X5~D
R403
10K_0402_5%~D
SMSC request
1
2
1
2
B
2
3
12
1U_0402_6.3V6K~D
C1179
2
2 3V_PWROK#
1K_0402_1%~D
1
R391
<40> PCH_PWRGD#
0.1U_0402_25V6K~D
C273
<7> H_THERMTRIP#
1
2
2
1
THERMATRIP2#
C278
0.1U_0402_25V6K~D
R399
C
2.2K_0402_5%~D
2
2
B
E
Q16
PMST3904_SOT323-3~D
1
<46>
+RTC_CELL
SMSC request
+1.05V_RUN_VTT
D
+RTC_CELL
+3.3V_M
THERMATRIP3#
1
P
5
1
C281
B
G
1
U10
TC7SH08FU_SSOP5~D
POWER_SW#
4
A
O
2
0.1U_0402_25V6K~D
1
DOCK_PWR_SW# <40>
2
POWER_SW_IN# <40>
3
2
2
R406
1.4K_0402_1%~D
2
1
R405
8.2K_0402_5%~D
C282
0.1U_0402_25V6K~D
1
VSET_4022
Rest=1400 Tp=94degree
C280
0.1U_0402_25V6K~D
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
FAN & Thermal Sensor
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
22
of
56
5
4
3
2
1
LCD Power
Q18
SI3456DDV-T1-GE3_TSOP6~D
+3.3V_ALW
6
4
5
2
R412
1
100K_0402_5%~D
1
D
+PWR_SRC_S +LCDVDD
S
LCD_A1+_PCH <16>
LCD_A1-_PCH <16>
+5V_ALW
PANEL_BKEN_PCH <16>
1
1
2
R1138
100K_0402_5%~D
BIA_PWM_EC <40>
C
1
3
2
1
2
4
3
PWR_SRC_ON
1
R423
Close to JLVDS1.6
D69
RB751V-40GTE-17_SOD323-2~D
1
2
C296
0.1U_0603_50V7K~D
Q22
SSM3K7002FU_SC70-3~D
2
1
47K_0402_5%~D
3
EN_INVPWR
<40> EN_INVPWR
PANEL_BKEN_EC <39>
FDC654P: P CHANNAL
Panel backlight power control by EC
2
D68
RB751V-40GTE-17_SOD323-2~D
1
2
2
R1137
10K_0402_5%~D
2
2
G
DISP_ON
BIA_PWM_PCH <16>
D67
RB751V-40GTE-17_SOD323-2~D
1
2
1
R422
100K_0402_5%~D
C302
0.1U_0402_25V6K~D
1
+BL_PWR_SRC
S
CONN@
BIA_PWM_LVDS
1
1
1
Close to JLVD1.9
40mil
6
5
2
1
D
2
4
G
Close to JLVDS1.7,8
40mil
C246
0.1U_0603_50V7K~D
S
2
Q21
FDC654P-G_SSOT-6~D
+PWR_SRC
1
D
1
+BL_PWR_SRC
C297
1000P_0402_50V7K~D
2
+3.3V_RUN
2
D66
RB751V-40GTE-17_SOD323-2~D
1
2
2
1
6 2
BAT54CW_SOT323-3~D
C243
0.1U_0402_25V6K~D
1
AMPHE_G47D4022101EU~D
Q20
PDTC124EU_SC70-3~D
LDDC_CLK_PCH
2
2.2K_0402_5%~D
LDDC_DATA_PCH
2
2.2K_0402_5%~D
+LCDVDD
+5V_ALW
PANEL_HDD_LED <43>
BREATH_WHITE_LED <43>
BATT_YELLOW_LED <43>
BATT_WHITE_LED <43>
EN_LCDPWR 2
1
Place near to JLVDS1
LCD_A0+_PCH <16>
LCD_A0-_PCH <16>
LDDC_DATA_PCH <16>
LDDC_CLK_PCH <16>
LCD_TST
<39>
+3.3V_RUN
+LCDVDD
BREATH_WHITE_LED
BATT_YELLOW_LED
BATT_WHITE_LED
3
1
LCD_A0+_PCH
LCD_A0-_PCH
LDDC_DATA_PCH
LDDC_CLK_PCH
<16,39> ENVDD_PCH
2
LCD_A1+_PCH
LCD_A1-_PCH
1
R159
1
R160
2
2
D
3
1
LCD_A2+_PCH <16>
LCD_A2-_PCH <16>
<39> LCD_VCC_TEST_EN
1
2
3
LCD_A2+_PCH
LCD_A2-_PCH
+3.3V_RUN
1
C292
0.1U_0402_25V6K~D
LCD_ACLK+_PCH <16>
LCD_ACLK-_PCH <16>
5
2
C293
0.1U_0402_25V6K~D
LCD_ACLK+_PCH
LCD_ACLK-_PCH
D6
G
1
2BIA_PWM_LVDS
LE92 BLM18BB221SN1D_2P~D
LCD_CBL_DET# <17>
2
R1632
1M_0402_5%~D
CAM_MIC_CBL_DET# <17>
+BL_PWR_SRC
Q19B
DMN66D0LDW-7_SOT363-6~D
USBP12_DUSBP12_D+
CAM_MIC_CBL_DET#
DISP_ON
BIA_PWM_LVDS_L
<29>
DMIC_CLK
<29>
+CAMERA_VDD
R414
10K_0402_5%~D
DMIC0
DMIC_CLK
C298
0.1U_0402_25V6K~D
C
DMIC0
+3.3V_ALW
R413
130_0402_1%~D
D
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D8
PESD5V0U2BT_SOT23-3~D
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Q19A
DMN66D0LDW-7_SOT363-6~D
G5
G4
G3
G2
G1
3
+LCDVDD
JLVDS1
45
44
43
42
41
RF TEAM request
B
LCD_ACLK+_PCH
LCD_ACLK-_PCH
For Webcam
Q23
+CAMERA_VDD
PMV65XP_SOT23-3~D
@
1
2
1
2
<39>
1
2
CCD_OFF
USBP12+
USBP12+
4
USBP12-
1
+3.3V_RUN
C301
0.1U_0402_25V6K~D
1
<17>
3
S
2
D
@
1
C1203
2
C300
10U_0805_10V6K~D
@
1
C1202
12P_0402_50V8J~D
2
C1201
12P_0402_50V8J~D
1
C299
0.1U_0402_25V6K~D
12P_0402_50V8J~D
LDDC_CLK_PCH
2
G
B
<17>
USBP12-
@ L10 DLW21SN121SQ2L_4P~D
3
4
3
1
2
USBP12_D+
USBP12_D-
2
1
R427
2
0_0402_5%~D
1
R428
2
0_0402_5%~D
CCD_OFF
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
LVDS
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
23
of
56
2
1
SW for MB/DOCK
B
B
+5V_RUN
+3.3V_RUN
U18
PCH_CRT_RED
PCH_CRT_GRN
PCH_CRT_BLU
PCH_CRT_HSYNC
PCH_CRT_VSYNC
PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
1
2
5
6
7
9
10
R
G
B
H_SOURCE
V_HOURCE
SDA_SOURCE
SCL_SOURCE
CRT_SWITCH
30
SEL
29
TEST
1
+3.3V_RUN
<16> PCH_CRT_RED
<16> PCH_CRT_GRN
<16> PCH_CRT_BLU
<16> PCH_CRT_HSYNC
<16> PCH_CRT_VSYNC
<16> PCH_CRT_DDC_DAT
<16> PCH_CRT_DDC_CLK
<39> CRT_SWITCH
16
VDD
VDD
VDD
4
23
32
R1
G1
B1
H1_OUT
V1_OUT
SDA1
SCL1
27
25
22
20
18
12
14
RED_CRT
GREEN_CRT
BLUE_CRT
HSYNC_BUF
VSYNC_BUF
DAT_DDC2_CRT
CLK_DDC2_CRT
R2
G2
B2
H2_OUT
V2_OUT
SDA2
SCL2
26
24
21
19
17
13
15
RED_DOCK
GREEN_DOCK
BLUE_DOCK
HSYNC_DOCK
VSYNC_DOCK
DAT_DDC2_DOCK
CLK_DDC2_DOCK
2
R556
4.7K_0402_5%~D
5V VDD
8
3
11
28
31
33
Reserved
GND
GND
GND
GND
GPAD
RED_CRT
<30>
GREEN_CRT <30>
BLUE_CRT
<30>
HSYNC_BUF <30>
VSYNC_BUF <30>
DAT_DDC2_CRT <30>
CLK_DDC2_CRT <30>
RED_DOCK
<38>
GREEN_DOCK <38>
BLUE_DOCK <38>
HSYNC_DOCK <38>
VSYNC_DOCK <38>
DAT_DDC2_DOCK <38>
CLK_DDC2_DOCK <38>
PI3V713-AZLEX_TQFN32_6X3~D
+3.3V_RUN
1
2
@
1
2
@
1
2
1
2
1
2
1
2
C339
0.1U_0402_25V6K~D
APR/SPR
C336
0.1U_0402_25V6K~D
A=B2
C335
0.1U_0402_25V6K~D
MB
1
C334
0.1U_0402_25V6K~D
Source
A=B1
C333
0.01U_0402_16V7K~D
Chanel
0
C332
0.01U_0402_16V7K~D
SEL1/SEL2
+5V_RUN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
CRT/Video switch
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
2
1
Sheet
24
of
56
2
1
+5V_RUN
NC
2 +5V_RUN_HDMI 1
1
2
1
F2
1
2
C338
10U_0805_10V6K~D
0.5A_15V_SMD1812P050TF
+VDISPLAY_VCC
C337
0.1U_0402_10V7K~D
B
D4
BAT1000-7-F_SOT23-3~D
2
3
fuse P/N ok only, symbol not ready
PCH_SDVO_CTRLDATA_R
PCH_SDVO_CTRLCLK_R
HDMI_CEC
TMDSB_CON_CLK#
TMDSB_CON_CLK
+3.3V_RUN
TMDSB_CON_N0
TMDSB_CON_P0
HDMI_CEC
2
TMDSB_CON_N1
TMDSB_CON_P1
1
10K_0402_5%~D
R1165
B
JHDMI1 CONN@
HDMI_HPD_SINK
TMDSB_CON_N2
TMDSB_CON_P2
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
Reserved
SDA
SCL
CEC
DDC/CEC_GND
CKCK+
CK_shield
D0D0+
D0_shield
D1D1+
D1_shield GND1
D2GND2
D2+
GND3
D2_shield GND4
20
21
22
23
BELLW_80079-1021
2
2
2
2
2
2
2
2
R458
HDMI_OB
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
680_0402_5%~D
1
+3.3V_RUN
1
1
1
1
1
1
1
1
D
3
TMDSB_PCH_P2_C
R452
TMDSB_PCH_N2_C R450
TMDSB_PCH_P1_C
R448
TMDSB_PCH_N1_C R449
TMDSB_PCH_P0_C
R454
TMDSB_PCH_N0_C R453
TMDSB_PCH_CLK_C R456
TMDSB_PCH_CLK#_C R455
S
<16> TMDSB_PCH_CLK
2
C353
TMDSB_PCH_CLK_C
1
0.1U_0402_10V7K~D
<16> TMDSB_PCH_CLK#
2
C352
1
2 10K_0402_5%~D
1
2
G
Q26
SSM3K7002FU_SC70-3~D
TMDSB_PCH_CLK#_C
0.1U_0402_10V7K~D
1
@ R451
L19
1
1
4
4
<16> TMDSB_PCH_P0
<16> TMDSB_PCH_N0
2
C351
1
TMDSB_PCH_P0_C
0.1U_0402_10V7K~D
1
2
C350
TMDSB_PCH_N0_C
1
0.1U_0402_10V7K~D
4
1
R1153
+5V_HDMI_DDC_CLK
2
2.2K_0402_5%~D
PCH_SDVO_CTRLDATA_R
1
R1152
+5V_HDMI_DDC_DAT
2
2.2K_0402_5%~D
5
PCH_SDVO_CTRLCLK_R
4
<16> PCH_SDVO_CTRLDATA
3
Q120B
DMN66D0LDW-7_SOT363-6~D
1
R1164
0_0402_5%~D
<16> TMDSB_PCH_P1
2
C347
1
TMDSB_PCH_P1_C
0.1U_0402_10V7K~D
<16> TMDSB_PCH_N1
2
C346
1
TMDSB_PCH_N1_C
0.1U_0402_10V7K~D
2
4
3
4
1
@ R470
L22
<16> TMDSB_PCH_P2
TMDSB_PCH_P2_C
0.1U_0402_10V7K~D
1
<16> TMDSB_PCH_N2
2
C348
1
TMDSB_PCH_N2_C
0.1U_0402_10V7K~D
4
TMDSB_CON_CLK#
2
TMDSB_CON_P0
3
TMDSB_CON_N0
2
0_0402_5%~D
2
3
2
TMDSB_CON_P1
3
TMDSB_CON_N1
A
2
0_0402_5%~D
1
2
4
3
2
TMDSB_CON_P2
3
TMDSB_CON_N2
DLW21SN900HQ2L_0805_4P~D
1
2
@ R471
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2
2
4
1
G
1
R1168
1M_0402_5%~D
3
3
2
0_0402_5%~D
1
1
@ R468
L21
1
1
2
C349
+3.3V_RUN
1
HDMI_HPD_SINK
1
R1128
D
S
<16> HDMIB_PCH_HPD
TMDSB_CON_CLK
DLW21SN900HQ2L_0805_4P~D
1
2
@ R469
0_0402_5%~D
2
@ D70
RB751V-40GTE-17_SOD323-2~D
1
2
A
R1163
Q120A
DMN66D0LDW-7_SOT363-6~D
1
2
@D65
@
D65
RB751V-40GTE-17_SOD323-2~D
0_0402_5%~D
2
1
2
+5V_RUN
+3.3V_RUN
6
3
2
DLW21SN900HQ2L_0805_4P~D
1
2
@ R466
0_0402_5%~D
+5V_RUN
1
2
DLW21SN900HQ2L_0805_4P~D
1
2
@ R459
0_0402_5%~D
1
@ R462
L20
<16> PCH_SDVO_CTRLCLK
2
0_0402_5%~D
Q121
SSM3K7002FU_SC70-3~D
2
Compal Electronics, Inc.
2
20K_0402_5%~D
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
HDMI port
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
1
Sheet
25
of
56
5
4
3
2
1
+3.3V_RUN
AUX/DDC SW for DPC to E-DOCK
1
2
C356
0.1U_0402_25V6K~D
D
<16> DPC_PCH_DOCK_AUX
C357
0.1U_0402_10V7K~D
DPC_AUX_C
2
1
1
2
BE0
A0
DPC_DOCK_AUX
3
B0
<38> DPC_DOCK_AUX
<16> DPC_PCH_DOCK_AUX#
2
C360
<38> DPC_DOCK_AUX#
U20
4
5
DPC_AUX#_C
1
0.1U_0402_10V7K~D
DPC_DOCK_AUX#
VCC
BE3
14
13
A3
12
BE1
A1
6
7
A2
GND
B2
PCH_DDPC_CTRLCLK <16>
11
10
B3
BE2
B1
D
9
PCH_DDPC_CTRLDATA <16>
8
PI3C3125LEX_TSSOP14~D
+5V_RUN
1
P
2
U21
NC
DPC_CA_DET
A
DPC_CA_DET#
4
Y
G
<38> DPC_CA_DET
5
C365
0.1U_0402_25V6K~D
1
2
3
NC7SZ04P5X-G_SC70-5~D
C
C
There is a new die for PI3C3125. Sample availabe on May.
+3.3V_RUN
AUX/DDC SW for DPD to E-DOCK
1
2
C366
0.1U_0402_25V6K~D
<16> DPD_PCH_DOCK_AUX
C367
0.1U_0402_10V7K~D
DPD_AUX_C
2
1
<38> DPD_DOCK_AUX
<16> DPD_PCH_DOCK_AUX#
2
C368
<38> DPD_DOCK_AUX#
U23
1
2
DPD_DOCK_AUX
3
4
5
DPD_AUX#_C
1
0.1U_0402_10V7K~D
DPD_DOCK_AUX#
6
7
BE0
A0
VCC
BE3
B0
A3
BE1
A1
B3
BE2
B1
A2
GND
B2
14
13
12
PCH_DDPD_CTRLCLK <16>
11
10
9
PCH_DDPD_CTRLDATA <16>
8
PI3C3125LEX_TSSOP14~D
B
B
+5V_RUN
P
2
A
U24
Y
4
DPD_CA_DET#
3
G
<38> DPD_CA_DET
5
C369
0.1U_0402_25V6K~D
DPD_CA_DET
1
1
NC
2
NC7SZ04P5X-G_SC70-5~D
+3.3V_RUN
A
PCH_DDPC_CTRLCLK
2
2.2K_0402_5%~D
PCH_DDPC_CTRLDATA
2
2.2K_0402_5%~D
PCH_DDPD_CTRLCLK
2
2.2K_0402_5%~D
PCH_DDPD_CTRLDATA
2
2.2K_0402_5%~D
1
R487
1
R488
1
R489
1
R490
1
R491
1
R492
5
Intel WW18 Strapping option
A
Intel WW18 Strapping option
DELL CONFIDENTIAL/PROPRIETARY
DPD_CA_DET
2
1M_0402_5%~D
DPC_CA_DET
2
1M_0402_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
DP125
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
26
of
56
5
4
3
2
1
+5V_HDD
1
2
C396
0.1U_0402_25V6K~D
2
D
C395
1000P_0402_50V7K~D
1
For HDD Temp.
JSATA1 CONN@
<14> PSATA_PTX_DRX_P0_C
<14> PSATA_PTX_DRX_N0_C
<14> PSATA_PRX_DTX_N0_C
<14> PSATA_PRX_DTX_P0_C
C389 2
C390 2
1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0
1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0
2
C391 2
C392
SATA_PRX_DTX_N0
1
1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0
0.01U_0402_16V7K~D
PJP64
Pleace near HDD CONN
1
+3.3V_RUN
2
1
2
C388
0.1U_0402_25V6K~D
C
C387
10U_0603_6.3V6M~D
1
2
HDD_DET#
+5V_HDD
C399
0.1U_0402_25V6K~D
Free Fall Sensor
+3.3V_RUN
C402
0.1U_0402_25V6K~D
2
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3.3V_RUN_HDD
PAD-OPEN1x1m
<14> HDD_DET#
+3.3V_RUN_HDD
1
2
1
2
3
4
5
6
7
FFS_INT2_Q
GND
RX+
RXGND
TXTX+
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
D
23
24
GND1
GND2
TYCO_1775770-3~D
Main SATA +5V Default
Pleace near HDD CONN
U88
LNG3DM
HDD_FALL_INT
FFS_INT2
<17> HDD_FALL_INT
10
13
15
16
GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC
5
12
VDD_IO
VDD
11
9
INT 1
INT 2
7
6
4
<12,13,15,34> DDR_XDP_WAN_SMBDAT
<12,13,15,34> DDR_XDP_WAN_SMBCLK
RES
RES
RES
RES
1
14
8
C
2
3
LNG3DMTR_LGA16_3X3~D
+3.3V_RUN
HDD PWR
+PWR_SRC_S
1
+3.3V_ALW2
R499
100K_0402_5%~D
2
2
A
4
R505
100K_0402_5%~D
2
1
1
1
R1624
FFS_INT2_Q
2
4
S
1
2
1
2
+5V_HDD
+5V_RUN
PJP3
1
1
4
3
2
6
1
2
FFS_INT2
1
<18> FFS_INT2
Q29A
DMN66D0LDW-7_SOT363-6~D
6
5
2
0_0402_5%~D
2
0_0402_5%~D
Q29B
DMN66D0LDW-7_SOT363-6~D
3
2
1
<11,16,35,39,42,48> SIO_SLP_S3#
R508
100K_0402_5%~D
1
@R1621
@
R1621
SI3456DDV-T1-GE3_TSOP6~D
3
C394
10U_0805_10V6K~D
<35,39,42,48> RUN_ON
B
G
C393
0.1U_0603_50V7K~D
@R506
@
R506
100K_0402_5%~D
Q28A
DMN66D0LDW-7_SOT363-6~D
+3.3V_RUN
Q28B
DMN66D0LDW-7_SOT363-6~D
5
+5V_HDD
@
Q27
D
R500
100K_0402_5%~D HDD_EN_5V
1
2
2
JUMP_43X79
SHORT DEFAULT
R504
100K_0402_5%~D
2
B
+5V_ALW
1
2
5
6
2 DDR_XDP_WAN_SMBDAT
10K_0402_5%~D
2 DDR_XDP_WAN_SMBCLK
10K_0402_5%~D
2 HDD_FALL_INT
100K_0402_5%~D
1
1
R501
1
R502
1
R503
+5V_HDD Source
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
HDD CONNECTOR
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
27
of
56
5
4
3
2
1
+3.3V_ALW
1
R510
2 ZODD_WAKE#
10K_0402_5%~D
1
R513
2 MOD_MD
10K_0402_5%~D
1
R514
2 USB30_SMI#
100K_0402_5%~D
For ODD
+3.3V_ALW_PCH
D
D
+5VMOD Source
<15> PCIE_PRX_EMBTX_P4
<15> PCIE_PRX_EMBTX_N4
<15> PCIE_PTX_EMBRX_P4
<15> PCIE_PTX_EMBRX_N4
Pleace near ODD CONN
<15> EMBCLK_REQ#
<34,35,40> PCIE_WAKE#
<17> PLTRST_EMB#
<40,45> BAY_SMBDAT
<40,45> BAY_SMBCLK
<39> MOD_SATA_PCIE#_DET
0.1U_0402_10V7K~D 2
0.1U_0402_10V7K~D 2
EMBCLK_REQ#
PCIE_WAKE#
PLTRST_EMB#
BAY_SMBDAT
BAY_SMBCLK
+3.3V_ALW
1
R1183
1 C409 PCIE_PTX_EMBRX_P4_C
1 C408 PCIE_PTX_EMBRX_N4_C
+5V_MOD
1
2
R512
100K_0402_5%~D
GND1
GND2
2
3
4
+5V_MOD
1
2
1
+5V
CLKREQ#
WAKE#
PERST#
SMB_DATA
SMB_CLK
HPD
2
<39> MODC_EN
1
S
R511
100K_0402_5%~D
2
25
26
27
28
29
30
31
1
2
5
6
GND
REFCLK+
REFCLKGND
PETX+
PETXGND
GND
PERX+
PERXGND
1
14
15
16
17
18
19
20
21
22
23
24
MODC_EN# 5
SI3456DDV-T1-GE3_TSOP6~D
3
C401
10U_0805_10V6K~D
<15> CLK_PCIE_EMB
<15> CLK_PCIE_EMB#
D Q30
G
MOD_EN
2
Q31A
DMN66D0LDW-7_SOT363-6~D
2
C398
0.1U_0402_25V6K~D
C
C397
1000P_0402_50V7K~D
2
1
R507
100K_0402_5%~D
R509
100K_0402_5%~D
C400
0.1U_0603_50V7K~D
MOD_MD
1
DP
+5V
+5V
MD
GND
GND
+5V_ALW
Q31B
DMN66D0LDW-7_SOT363-6~D
+5V_MOD
8
9
10
11
12
13
+PWR_SRC_S
+3.3V_ALW2
2
<40> DEVICE_DET#
+5V_MOD
GND
A+
AGND
BB+
GND
6
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
1
2
3
4
5
6
7
1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
1
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
SATA_ODD_PRX_DTX_N1_RP
SATA_ODD_PRX_DTX_P1_RP
2
C407 2
C406
2
C405 2
C404
4
JSATA2 CONN@
SATA_ODD_PTX_DRX_P1_RP
SATA_ODD_PTX_DRX_N1_RP
C
32
33
TYCO_2-2129116-1
2
10K_0402_5%~D
+3.3V_RUN
2
SATA_ODD_PRX_DTX_P1
1
0.01U_0402_16V7K~D
+ODD_EQ1
+3.3V_ALW
1
+ODD_EQ2
+ODD_EQ1
4
5
3
13
17
21
HAP
HAM
HBM
HBP
GND
GND
GND
EP
PA
PB
DAP
DAM
DBP
DBM
2
1
2
1
1
2
1
2
9
8
+ODD_PE1
+ODD_PE2
15
14
SATA_ODD_PTX_DRX_P1_RP
SATA_ODD_PTX_DRX_N1_RP
11
12
SATA_ODD_PRX_DTX_P1_RP
SATA_ODD_PRX_DTX_N1_RP
R495
0_0402_5%~D
0.01U_0402_16V7K~D
R496
0_0402_5%~D
C385
1
2
@ R1178
10K_0402_5%~D
<14> SATA_ODD_PRX_DTX_P1_C
SATA_ODD_PRX_DTX_N1
1
@ R1172
10K_0402_5%~D
C386
SATA_ODD_PTX_DRX_N1
0.01U_0402_16V7K~D
2
<14> SATA_ODD_PRX_DTX_N1_C
SATA_ODD_PTX_DRX_P1
0.01U_0402_16V7K~D
1
1
2
1
2
C384
1
5
USB30_EN
2
C383
B
+ODD_DEW1
2
<14> SATA_ODD_PTX_DRX_P1_C
<14> SATA_ODD_PTX_DRX_N1_C
+ODD_DEW2
6
10
16
20
VCC
VCC
VCC
VCC
1
USB30_SMI# <14>
EN
DD
OL
2
DMN66D0LDW-7_SOT363-6~D
USB30_SMI#
4
3
7
18
19
2
+ODD_EQ2
1
2
Q123B
@ R494
0_0402_5%~D
G
U25
B
2
@ R493
0_0402_5%~D
2
MODC_EN#
R1177
0_0402_5%~D
ZODD_WAKE# <39>
+3.3V_RUN
R1181
0_0402_5%~D
1
1
C382
0.1U_0402_25V6K~D
D
S
3
1
ZODD_WAKE#
C381
0.01U_0402_16V7K~D
Q76
SSM3K7002FU_SC70-3~D
MOD_MD
MAX4951CCTPLFT_TQFN20_4X4~D
R515
100K_0402_5%~D
1
2
1
2
1
1
2
6
1
R1176
0_0402_5%~D
R1174
0_0402_5%~D
A
@ R1175
10K_0402_5%~D
Q123A
DMN66D0LDW-7_SOT363-6~D
2
@ R1173
10K_0402_5%~D
MOD_SATA_PCIE#_DET
2
2
+3.3V_RUN
USB30_EN
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
ODD CONNECTOR
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
28
of
56
2
1
+VDDA_AVDD
INT_SPKR_R-
5
6
2
GND
GND
2
TYCO_2-1775765-4~D
2
3
<14> PCH_AZ_CODEC_SYNC
3
9
<14> PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
6
PCH_AZ_CODEC_SDOUT
5
10
Place R1096 close to codec
PCH_AZ_SDIN0_R
2
33_0402_5%~D
PCH_AZ_CODEC_RST#
1
<14> PCH_AZ_CODEC_SDIN0
1
2
3
1
@ DE1
PESD5V0U2BT_SOT23-3~D
2
R1096
DVDD_CORE
AVDD1
AVDD2
DVDD_IO
PVDD
PVDD
DVDD
SENSE_A
SENSE_B
8
11
RE9
I2S_BCLK
I2S_MCLK_R
2
0_0402_5%~D
I2S_BCLK_R
2
0_0402_5%~D
2
33_0402_5%~D
1
I2S_DO
1
RE10
1
R1097
I2S_LRCLK
Place R1097 close to codec
15
16
17
18
I2S_DI#
24
Close to U72 pin6
Close to U72 pin5
PORTA_L
PORTA_R
VrefOut_A
BITCLK
SDATA_OUT
PORTB_L
PORTB_R
SYNC
SDATA_IN
PORTD_+L
PORTD_-L
RESET#
PORTD_+R
PORTD_-R
I2S_MCLK
I2S_MCLK
MONO_OUT
I2S_SCLK
PC_BEEP
I2S_DOUT
DMIC_CLK/GPIO 1
DMIC_0/GPIO 2
DMIC1/GPIO0/SPDIFOUT1
SPDIFOUT0//GPIO3/Aux_Out
I2S_LRCLK
I2S_DIN
CAP+
PCH_AZ_CODEC_BITCLK
1
42
2
10K_0402_5%~D
2
49
AUD_SENSE_A
AUD_SENSE_B
28
29
23
MIC_IN_L
MIC_IN_R
+VREFOUT
31
32
AUD_HP_OUT_L
AUD_HP_OUT_R
40
41
INT_SPK_L+
INT_SPK_L-
44
43
INT_SPK_R+
INT_SPK_R-
25
AUD_PC_BEEP
2
4
46
48
No Connect
EAPD
VREFFILT
CAP2
VVreg
DVSS
PVSS
AVSS1
AVSS
AVSS
GND
2
2.2U_0603_6.3V6K~D
+VREFOUT
1
R1143
1
2
+VDDA_AVDD
place at AGND and DGND plane
R1083
2.49K_0402_1%~D
2
1
1
1
2
1
1
26
30
33
2
2
2
3
4
1
2
<30,39>
1
R162, R163, R164, R165,R166 CO-lay with U73
DAI_BCLK#
DAI_LRCK#
DAI_DO#
A
Place closely to Pin 14
DAI_12MHZ#
SENSE_B
2
PORT A
1
@ R162
1
@ R163
1
@ R164
1
@ R165
PORT E
20K
PORT B
PORT F
10K
NA
DMIC0
5.11K
R1082
100K_0402_5%~D
2.49K
SPKR
<14>
BEEP
<40>
<23>
<23>
1
@ R1141
1
@ R1142
2
10K_0402_5%~D
2
10K_0402_5%~D
1
2
1
2
1
2
2
4
6
10
SPDIFOUT0
SPDIFOUT1 (DMIC1)
14
<39> EN_I2S_NB_CODEC#
EN_I2S_NB_CODEC#
1
15
2
1
R1540
1K_0402_1%~D
VCC
1A
1Y#
2A
2Y#
3A
3Y#
4A
4Y#
5A
5Y#
6A
6Y#
OE1#
OE2#
GND
3
DAI_BCLK#
5
DAI_LRCK#
7
DAI_DO#
9
DAI_12MHZ#
DAI_BCLK#
<38>
DAI_LRCK#
<38>
DAI_DO#
<38>
A
DAI_12MHZ# <38>
11
I2S_DI# 1
@ R166
13
DAI_DI
2
0_0402_5%~D
8
CD74HC366M96_SO16~D
DAI_DI
DAI_DI
<38>
Pull-up to AVDD
2
3
2
+3.3V_RUN
1
1
1
6
2
2
R1081
100K_0402_5%~D
R1080
20K_0402_1%~D
C979
1000P_0402_50V7K~D
R1079
39.2K_0402_1%~D
39.2K
2
100K_0402_5%~D
2
100K_0402_5%~D
U73
16
12
R1078
2.49K_0402_1%~D
2
1
1
+3.3V_RUN
1
SENSE_A
2 I2S_BCLK
22_0402_5%~D
2 I2S_LRCLK
0_0402_5%~D
2 I2S_DO
0_0402_5%~D
2 I2S_MCLK
22_0402_5%~D
+VDDA_AVDD
AUD_SENSE_B
1
R1119
1
R1120
+3.3V_RUN
Q107B
DMN66D0LDW-7_SOT363-6~D
Resistor
AUD_HP_OUT_L <30>
AUD_HP_OUT_R <30>
PAD-OPEN1x1m
C983
100P_0402_50V8J~D
AUD_HP_NB_SENSE
2
Place C963~C966 close to Codec
C1103
0.1U_0402_10V7K~D
5
<30>
Place C962 close to Codec
2
Q107A
DMN66D0LDW-7_SOT363-6~D
@
+VREFOUT
place at Codec bottom side
PJP62
1
2
2
C982
100P_0402_50V8J~D
R1087
100K_0402_5%~D
2
C962
4.7U_0603_6.3V6K~D
21
22
34
37
@
6
2
1
+3.3V_RUN
2
2.2K_0402_5%~D
2
0_0402_5%~D
PAD~D
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
2
C981
100P_0402_50V8J~D
@
1
C980
0.1U_0402_10V7K~D
R1086
20K_0402_1%~D
1
@
AUD_SENSE_A
2
1
B
92HD90B2X5NLGXYAX8_QFN48_7X7~D
Place closely to Pin 13.
MIC_IN_R
Place LE3 close to codec
1
@ R169
@ T90
36
35
1
2
1
C1105
0.1U_0402_25V6K~D
2
1
C1106
0.1U_0402_25V6K~D
2
DMIC_CLK
BLM18BB221SN1D_2P~D
DMIC0
DMIC_CLK_L 1
LE3
2
1
1
C1163
12
1
C966
10U_0805_10V6K~D
2
R1099
13
14
C965
1U_0603_10V7K~D
7
@ C977
10P_0402_50V8J~D
+VDDA_PVDD
No Connect
+3.3V_RUN
1
@C978
@C978
0.1U_0402_10V7K~D
2
45
39
C964
4.7U_0603_6.3V6K~D
2
47
<39> AUD_NB_MUTE#
1
27
38
C963
4.7U_0603_6.3V6K~D
1
20
CAP-
@ R1076
10_0402_1%~D
2
@ R1077
47_0402_5%~D
19
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output
1
1
PCH_AZ_CODEC_SDOUT
2
C1180
1U_0603_10V7K~D
1
<14> PCH_AZ_CODEC_SDOUT
@ DE2
PESD5V0U2BT_SOT23-3~D
2
<14> PCH_AZ_CODEC_BITCLK
2
U72
1
0.1U_0402_25V6K~D
680P_0402_50V7K~D
1
680P_0402_50V7K~D
2
C994
2
1
@ C976
680P_0402_50V7K~D
1
@ C975
680P_0402_50V7K~D
2
@ C974
@ C973
1
B
2
2
Place C994, C952~C957 close to Codec
1
INT_SPKR_R+
2 BLM18BD121SN1D_2P~D
1
C961
0.1U_0402_25V6K~D
2 BLM18BD121SN1D_2P~D
L94 1
1
R1095
0_0805_5%~D
L93 1
INT_SPK_R-
1
1
2
3
4
C960
10U_0805_10V6K~D
INT_SPK_R+
1
2
3
4
C959
0.1U_0402_25V6K~D
INT_SPKL_L-
1
C958
10U_0805_10V6K~D
INT_SPKL_L+
2 BLM18BD121SN1D_2P~D
C954
10U_0805_10V6K~D
2 BLM18BD121SN1D_2P~D
L92 1
C953
0.1U_0402_25V6K~D
L91 1
INT_SPK_L-
C952
1U_0603_10V7K~D
INT_SPK_L+
1
C955
10U_0805_10V6K~D
CONN@
JSPK1
C956
1U_0603_10V7K~D
1
DVDD_IO should match
with HDA Bus level
C957
0.1U_0402_25V6K~D
+3.3V_RUN
15 mils trace
+5V_RUN
place close to pin38
L77
BLM21PG600SN1D_0805~D
1
2
+5V_RUN
2
place close to pin27
Internal Speakers Header
5
4
2
Q106A
DMN66D0LDW-7_SOT363-6~D
1
<39> DOCK_HP_DET
DOCK_MIC_DET
Q106B
DMN66D0LDW-7_SOT363-6~D
2
PORT A
External MIC
PORT B
HeadPhone Out
PORT C
Dock Audio
PORT D
Internal SPK
DELL CONFIDENTIAL/PROPRIETARY
<39>
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
Azalia (HD) Codec
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
29
of
56
5
4
3
2
SW1
<40,41> POWER_SW#_MB
POWER_SW#_MB
3
1
4
2
1
I/O board CONN.
@ D23
3
1
Link Done
2
JIO1
NTC033-XJ1J-X260CM_4P
PESD24VS2UT_SOT23-3~D
D
RED_CRT
GREEN_CRT
BLUE_CRT
<24> RED_CRT
<24> GREEN_CRT
<24> BLUE_CRT
DAT_DDC2_CRT
CLK_DDC2_CRT
<24> DAT_DDC2_CRT
<24> CLK_DDC2_CRT
Defult on,
WIRELESS_ON/OFF#:
LOW: ON
HIGH: OFF
DETECT_GND
24
26
28
Media Board
LS-6613P
2
4
6
8
10
12
14
16
18
20
22
G2
G4
G6
CONN@
1 1
3 3
5 5
7 7
9 9
11
11
13 13
15 15
17 17
19 19
21 21
G1
G3
G5
IO_LOOP#
<18>
+5V_RUN
D
+5V_RUN
1
AUD_HP_OUT_R <29>
AUD_HP_OUT_L <29>
MIC_IN_R
<29>
AUD_HP_NB_SENSE <29,39>
23
25
27
2
C1000
0.1U_0402_16V4Z~D
POWER & INSTANT ON SWITCH
2
4
6
8
10
12
14
16
18
20
22
VSYNC_BUF
HSYNC_BUF
<24> VSYNC_BUF
<24> HSYNC_BUF
Place close
to JIO1.3,5
TYCO_2041300-1~D
JMEDIA1 CONN@
<18> MEDIA_DET#
<39> WIRELESS_ON#/OFF
<40> VOL_MUTE
<40> VOL_DOWN
<40> VOL_UP
MEDIA_DET#
WIRELESS_ON#/OFF
VOL_MUTE
VOL_DOWN
VOL_UP
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6 G1
7 G2
8
9
10
LED Board with Lid
11
12
LS-6612P
+5V_ALW
TYCO_1-2041070-0~D
JLED1 CONN@
LinK Done
C
1
0.1U_0402_25V6K~D
2
<43> SATA_LED
<43> BATT_WHITE
<43> BATT_YELLOW
C1002
<43> WLAN_LED
<39,43> LID_CL#
+3.3V_ALW
SATA_LED
BATT_WHITE
BATT_YELLOW
WLAN_LED
LID_CL#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
C
G1
G2
9
10
TYCO_2041322-8~D
C457
0.1U_0402_10V7K~D
1
Link Done
2
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
PWR SW/Sub-board Connector
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
30
of
56
5
4
3
2
1
+3.3V_LAN
+3.3V_RUN
1
TP_LAN_JTAG_TMS
2
10K_0402_5%~D
TP_LAN_JTAG_TCK
2
10K_0402_5%~D
R547
10K_0402_5%~D
2
<15> PCIE_PTX_GLANRX_P7
1
2
<18> PM_LANPHY_ENABLE
1
R555
41
42
MDI_PLUS1
MDI_MINUS1
PETp
PETn
PERp
PERn
MDI_PLUS3
MDI_MINUS3
LAN_DISABLE#_R
3
SMB_CLK
SMB_DATA
RSVD_NC
1
2
5
VDD3P3_OUT
4
LAN_DISABLE_N
26
27
25
LED0
LED1
LED2
1
2
1
2
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
XTALO
XTALI
9
10
XTAL_OUT
XTAL_IN
LAN_TEST_EN
30
TEST_EN
RES_BIAS
12
RBIAS
JTAG
32
34
33
35
VDD3P3_15
VDD3P3_19
VDD3P3_29
15
19
29
VDD1P0_47
VDD1P0_46
VDD1P0_37
47
46
37
VDD1P0_43
43
VDD1P0_11
11
VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8
40
22
16
8
7
CTRL_1P0
+RSVD_VCC3P3_1
+RSVD_VCC3P3_2
2
R5532
R554
1
14.7K_0402_5%~D
4.7K_0402_5%~D
1
+3.3V_LAN
2
+3.3V_LAN_OUT
1
2
Place C462, C463 and L29 close to U31
1
+1.0V_LAN
C464
1U_0603_10V7K~D
+1.0V_LAN
1
2
1
2
1
2
1
2
+3.3V_LAN
1
2
1
2
REGCTL_PNP10
C
Place C1178 close to pin5
49
VSS_EPAD
R562
3.01K_0402_1%~D
R561
1K_0402_1%~D
1
2
Idc max=330mA
2
2
2
1
C1178
22U_0805_6.3V6M~D
4
REGCTL_PNP10
C1177
22U_0805_6.3V6M~D
GND
+1.0V_LAN
L29
C469
0.1U_0402_10V7K~D
GND
C471
33P_0402_50V8J~D
1
C470
33P_0402_50V8J~D
2
2
LAN_TX3+
LAN_TX3-
C468
0.1U_0402_10V7K~D
25MHZ_18PF_X3G025000DI1H-H~D
Y3
1 IN
OUT 3
23
24
C467
0.1U_0402_10V7K~D
C
LAN_TX2+
LAN_TX2-
D
C466
0.1U_0402_10V7K~D
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
R1144
0_0402_5%~D
1
2
20
21
RSVD_VCC3P3_1
RSVD_VCC3P3_2
VDD3P3_IN
LED
1
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
T142 PAD~D
T143 PAD~D
LAN_TX1+
LAN_TX1-
6
<39> LAN_DISABLE#_R
@ R557
10K_0402_5%~D
17
18
4.7UH_CBC2012T4R7M_20%~D
28
31
SMBus Device Address 0xC8
2
0_0402_5%~D
MDI_PLUS2
MDI_MINUS2
LAN_TX0+
LAN_TX0-
C463
0.1U_0402_10V7K~D
<15> LAN_SMBCLK
<15> LAN_SMBDATA
38
39
PE_CLKP
PE_CLKN
13
14
C462
10U_0603_6.3V6M~D
<15> PCIE_PTX_GLANRX_N7
R549
10K_0402_5%~D
44
45
MDI_PLUS0
MDI_MINUS0
Note:
+1.0V_LAN will work at 0.95V to 1.15V
82579_QFN48_6X6~D
Q34
+3.3V_ALW
LAN_TX2+ 1
2
L34
12NH_0603CS-120EJTS_5%~D
LAN_TX21
2
L35
12NH_0603CS-120EJTS_5%~D
LAN_TX2+R
9
LAN_TX2-R
10
LAN_TX3+ 1
2
L36
12NH_0603CS-120EJTS_5%~D
LAN_TX31
2
L37
12NH_0603CS-120EJTS_5%~D
LAN_TX3+R
11
LAN_TX3-R
12
13
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
Layout Notice : Place bead as
close PI3L500 as possible
15
16
42
5
43
FROM NIC
DOCKED
17
18
41
LAN_ACTLED_YEL#
LED_100_ORG#
LED_10_GRN#
36
35
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
32
31
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
27
26
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
C3+
C3-
23
22
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
LEDC0
LEDC1
LEDC2
19
20
40
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
A1-
B3+
B3-
A2+
A2-
LEDB0
LEDB1
LEDB2
A3+
C0+
C0-
A3-
C1+
C1-
SEL
C2+
C2-
LEDA0
LEDA1
LEDA2
SW_LAN_TX3+ <44>
SW_LAN_TX3- <44>
LAN_ACTLED_YEL# <44>
LED_100_ORG# <44>
LED_10_GRN# <44>
DOCK_LOM_TRD1+ <38>
DOCK_LOM_TRD1- <38>
DOCK_LOM_TRD2+ <38>
DOCK_LOM_TRD2- <38>
LOM_SPD100LED_ORG#
1
LOM_SPD10LED_GRN#
2
DOCK_LOM_TRD3+ <38>
DOCK_LOM_TRD3- <38>
DOCK_LOM_ACTLED_YEL# <38>
DOCK_LOM_SPD100LED_ORG# <38>
DOCK_LOM_SPD10LED_GRN# <38>
B
A
O
4
D
1
3
G
WLAN_LAN_DISB# <39>
TC7SH08FU_SSOP5~D
U15
A
DELL CONFIDENTIAL/PROPRIETARY
PAD_GND
Compal Electronics, Inc.
TO
DOCK
PI3L720ZHEX_TQFN42_9X3P5~D
2
Title
Intel 82579 (Hanksville) / LAN SW
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
5
4
3
B
+3.3V_LAN
C478
0.1U_0402_10V7K~D
1
2
DOCK_LOM_TRD0+ <38>
DOCK_LOM_TRD0- <38>
1: TO DOCK
0: TO RJ45
3
SW_LAN_TX2+ <44>
SW_LAN_TX2- <44>
2
SW_LAN_TX3+
SW_LAN_TX3-
4
SW_LAN_TX2+
SW_LAN_TX2-
25
24
B2+
B2-
6
29
28
A1+
PD
2
1
7
2
<16,39> SIO_SLP_LAN#
1
LAN_TX1-R
A0-
SW_LAN_TX1+ <44>
SW_LAN_TX1- <44>
1
2
5
6
SW_LAN_TX1+
SW_LAN_TX1-
B1+
B1-
P
LAN_TX1+R
34
33
A0+
G
3
LAN_TX1+ 1
2
L33
12NH_0603CS-120EJTS_5%~D
LAN_TX11
2
L32
12NH_0603CS-120EJTS_5%~D
2
SW_LAN_TX0+ <44>
SW_LAN_TX0- <44>
3
LAN_TX0-R
2
39
30
21
14
8
4
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
LAN_TX0+R
SW_LAN_TX0+
SW_LAN_TX0-
2
ENAB_3VLAN
1
C476
0.1U_0402_10V7K~D
A
DOCKED
1
C475
10U_0603_6.3V6M~D
5
38
37
B0+
B0-
Q35A
DMN66D0LDW-7_SOT363-6~D
<39>
4
C477
2200P_0402_50V7K~D
U32
LAN_TX0+ 1
2
L30
12NH_0603CS-120EJTS_5%~D
LAN_TX01
2
L31
12NH_0603CS-120EJTS_5%~D
DOCKED
R565
100K_0402_5%~D
LAN ANALOG
SWITCH
R1638
470K_0402_5%~D
2
Q35B
DMN66D0LDW-7_SOT363-6~D
2
1
R564
100K_0402_5%~D
C474
0.1U_0402_25V6K~D
1
C473
0.1U_0402_25V6K~D
2
B
C472
0.1U_0402_25V6K~D
1
6
5
2
1
1
+3.3V_ALW2
+3.3V_LAN
+3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S
S
<15> PCIE_PRX_GLANTX_N7
+3.3V_LAN
CLK_PCIE_LAN
CLK_PCIE_LAN#
2
1 PCIE_PRX_GLANTX_P7_C
C458
0.1U_0402_10V7K~D
2
1 PCIE_PRX_GLANTX_N7_C
C459
0.1U_0402_10V7K~D
1
2 PCIE_PTX_GLANRX_P7_C
C460
0.1U_0402_10V7K~D
1
2 PCIE_PTX_GLANRX_N7_C
C461
0.1U_0402_10V7K~D
R551
0_0402_5%~D
1
2 LAN_SMBCLK_R
1
2 LAN_SMBDATA_R
R552
0_0402_5%~D
CLK_REQ_N
PE_RST_N
MDI
<15> CLK_PCIE_LAN
<15> CLK_PCIE_LAN#
<15> PCIE_PRX_GLANTX_P7
48
36
PCIE
D
U31
LANCLK_REQ#_R
2
0_0402_5%~D
1
R1187
<15> LANCLK_REQ#
<17> PLTRST_LAN#
SMBUS
1
@ R545
1
@ R546
2
Sheet
1
31
of
56
5
4
3
2
1
USH board conn
+3.3V_SUS
+3.3V_RUN
+3.3V_SB3V
1
1@ R873
2
0_0402_5%~D
USH_SMBCLK
2
2.2K_0402_5%~D
USH_SMBDAT
2
2.2K_0402_5%~D
1
R589
1
R585
+3.3V_SB3V
+3.3V_RUN
SB3V
26
23
20
17
LAD0
LAD1
LAD2
LAD3
V_BAT
NBO_13
NBO_14
12
13
14
<15> CLK_PCI_TPM_TCM
<14,34,39,40> LPC_LFRAME#
<17,34,35,39,40> PCH_PLTRST#_EC
<14,39,40> IRQ_SERIRQ
<16,39,40> CLKRUN#
21
22
16
27
15
1
CLK_PCI_TPM_TCM
@
1
2
3
TCM_BA1
RE5
33_0402_5%~D
C
2
1
2
1
2
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
TESTBI
TESTI
9
8
NC_7
7
ATEST_1
ATEST_2
ATEST_3
GND_4
GND_11
GND_18
GND_25
<41> BT_COEX_STATUS2
<41> BT_PRI_STATUS
<17> PLTRST_USH#
<39> USH_PWR_STATE#
<18> CONTACTLESS_DET#
+3.3V_RUN
JETWAY_CLK14M
JETWAY_CLK14M <15>
NC_P
1
2
C554
1U_0402_6.3V6K~D
+5V_RUN
1
6
GPIO6
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
2
1
TCM_BA0
2
+3.3V_RUN
PP
1
@ R656
2
4.7K_0402_5%~D
1
2
<18> USH_DET#
C52
0.1U_0402_25V6K~D
LPCPD#
2
1
C51
0.1U_0402_25V6K~D
28
10
19
24
USBP7USBP7+
<40> USH_SMBCLK
<40> USH_SMBDAT
<39> BCM5882_ALERT#
C53
0.1U_0402_25V6K~D
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
VCC_0
VCC_1
VCC_2
C553
0.1U_0402_25V6K~D
5
SP_TPM_LPC_EN
<39> SP_TPM_LPC_EN
<14,34,39,40>
<14,34,39,40>
<14,34,39,40>
<14,34,39,40>
U39 1@
C552
2200P_0402_50V7K~D
2
C551
2200P_0402_50V7K~D
2
+3.3V_SUS
ATMEL TPM for E4
1@
C550
2200P_0402_50V7K~D
1@
1
C45
4700P_0402_25V7K~D
1
C44
0.1U_0402_25V6K~D
D
JUSH1 CONN@
<17>
<17>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND1
GND2
D
TYCO_2-2041070-0
4
11
18
25
C
2
AT97SC3204-X2A14-AB_TSSOP28
@
1
2
CE3
27P_0402_50V8J~D
Co-lay U37 and U39
LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay
+3.3V_RUN
LOW:Power Down Mode
High:Working Mode
4@ U37
VDD_0
VDD_1
VDD_2
+3.3V_RUN
SP_TPM_LPC_EN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
28
26
23
20
17
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
PP
TCM_BA1
TCM_BA0
21
22
16
27
15
7
3
9
LPCPD#
LAD0
LAD1
LAD2
LAD3
GND_11
GND_18
GND_25
GND_4
11
18
25
4
B
+3.3V_SB3V
1
1
TCM_BA0
TCM_BA1
R660
10K_0402_5%~D
NC_1
NC_2
NC_6
NC_8
NC_P
JETWAY_CLK14M
JETWAY_CLK14M
1
NC_5
NC_12
NC_13
@
RE6
33_0402_5%~D
1
2
6
8
14
NC_P
1
2
2
2
R659
10K_0402_5%~D
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
BA_1
BA_0
5
12
13
2
2
@ R658
10K_0402_5%~D
2
@ R657
10K_0402_5%~D
1
1
B
10
19
24
@
CE4
27P_0402_50V8J~D
SSX44-B-D-T1_TSSOP28~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
TPM/TCM
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
32
of
56
5
4
3
2
1
D
D
+3.3V_RUN
+PE_VDDH
1
2
C574
0.01U_0402_16V7K~D
2
C578
0.1U_0402_25V6K~D
1
<15> CLK_PCIE_MMI
<15> CLK_PCIE_MMI#
1
2
C579
4.7U_0603_6.3V6K~D
<15>
<15>
<15>
<15>
C569
C573
C567
C568
PCIE_PRX_MMITX_P6
PCIE_PRX_MMITX_N6
PCIE_PTX_MMIRX_P6
PCIE_PTX_MMIRX_N6
1
1
1
1
2
2
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
R677
PCIE_PRX_MMITX_P6_C
PCIE_PRX_MMITX_N6_C
PCIE_PTX_MMIRX_P6_C
PCIE_PTX_MMIRX_N6_C
2
191_0402_1%~D
C
place close to pin U38.32
2
1
PE_REFCLKP
PE_REFCLKM
6
7
5
4
3
PE_TXP
PE_TXM
PE_RXP
PE_RXM
PE_REXT
33
GPAD
13
PE_RST#
<17> PLTRST_MMI#
14
31
<15> MMICLK_REQ#
MULTI-IO1
MULTI-IO2
1
1
2
1
2
C560
4.7U_0603_6.3V6K~D
3.3VDDH
VDDH
PE_VDDH
2
C559
0.1U_0402_25V6K~D
16
9
32
1
C564
4.7U_0603_6.3V6K~D
+3.3VDDH
+VDDH_SD
+PE_VDDH
2
BLM18BD601SN1D_0603~D
2
C563
0.1U_0402_25V6K~D
U38
C566
4.7U_0603_6.3V6K~D
L44
2
1
1
C565
0.1U_0402_25V6K~D
1
2
1
C575
0.1U_0402_25V6K~D
2
2
1
C576
0.1U_0402_25V6K~D
2
1
C562
0.1U_0402_25V6K~D
1
C561
4.7U_0603_6.3V6K~D
L47
1
2
BLM18BD601SN1D_0603~D
C577
4.7U_0603_6.3V6K~D
L45
BLM18PG471SN1D_2P~D
1
2
1
+1.5V_RUN
DVDD
AVDD
10
8
+OZ_DVDD
+OZ_AVDD
SKT_VCC
MMI_VCC_OUT
17
15
+SKT_VCC
SD_D1
SD_D2
MMI_D0
MS_D1
MS_D2
MMI_D3
MMI_D4
MMI_D5
MMI_D6
MMI_D7
28
26
29
27
25
24
23
22
21
20
SD/MMCDAT1_R
SD/MMCDAT2_R
SD/MMCDAT0_R
R663 1
R664 1
R665 1
2 33_0402_5%~D SD/MMCDAT1
2 33_0402_5%~D SD/MMCDAT2
2 33_0402_5%~D SD/MMCDAT0
SD/MMCDAT3_R
SD/MMCDAT4_R
SD/MMCDAT5_R
SD/MMCDAT6_R
SD/MMCDAT7_R
R668
R669
R670
R672
R673
2
2
2
2
2
MS_CD#
SD_CMD/MS_BS
MMI_CLK
SD_CD#
SD_WPI
11
19
18
12
30
SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCCD#
SDWP
R674 1
1
R676
2
1
1
1
1
1
2
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
+3.3V_RUN_CARD
SD/MMCDAT3
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7
C
2 33_0402_5%~D SD/MMCCMD
SD/MMCCLK
2
33_0402_5%~D
OZ600FJ0LN_QFN32_5X5~D
EMI request
2
SD/MMCCLK
@ RE678
33_0402_5%~D
@ CE757
+3.3V_RUN_CARD
SD/MMCDAT0
SD/MMCDAT1
SD/MMCDAT2
14
12
10
9
8
6
4
3
15
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7
13
11
7
5
SD/MMCCLK
10P_0402_50V8J~D
2
R826
10K_0402_5%~D
1
C571
0.1U_0402_25V6K~D
2
C572
4.7U_0603_6.3V6K~D
1
1
2
2
1
B
JSD1 CONN@
SD/MMCDAT3
SD/MMCCMD
1
B
19
20
SD/MMCCD#
SDWP
SD/MMCCD#
SDWP
17
18
2
1
16
DAT3/SD1
CMD/SD2
VSS1/SD3
VCC/SD4
CLK/SD5
GND/VSSS2/SD6
DAT0/SD7
DAT1/SD8
DAT2/SD9
DAT4/MMC10
DAT5/MMC11
DAT6/MMC12
DAT7/MMC13
CD_WP_SW/GND
CD_WP_SW/GND
CD_SW/SD
WP_SW/SD
CD_SW_TAISOL/SD
WP/SW_TAISOL/SD
GND_SW
T-SOL_156-4000000901_NR~D
Link Done
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Card Reader
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
33
of
56
5
4
3
2
1
+3.3V_PCIE_WWAN
1
@ R693
2
2
100K_0402_5%~D
2
R1157
2
R1158
<12,13,15,27> DDR_XDP_WAN_SMBCLK
<12,13,15,27> DDR_XDP_WAN_SMBDAT
1
0_0402_5%~D
1
0_0402_5%~D
<39> WLAN_RADIO_DIS#
+3.3V_ALW_PCH
2
0_0402_5%~D
1
PCIE_MCARD1_DET# 1
R692
WLAN_RADIO_DIS#_R
2
D31
RB751S40T1_SOD523-2~D
USB_MCARD1_DET#
1
@ R698
WWAN_SMBDAT
+3.3V_WLAN
D
<41> COEX2_WLAN_ACTIVE
<41> COEX1_BT_ACTIVE
<15> MINI2CLK_REQ#
+3.3V_PCIE_WWAN
JMINI1 CONN@
+1.5V_RUN
+1.5V_RUN
C
<39> HW_GPS_DISABLE2#
GND2
1
USBP5<17>
USBP5+
<17>
USB_MCARD2_DET# <18>
@ C600
33P_0402_50V8J~D
USB_MCARD2_DET# 1
@ R697
2 PCIE_MCARD2_DET#
0_0402_5%~D
+1.5V_RUN
2
2
R719
1
1
2
1
1
2
C608
4.7U_0603_6.3V6K~D
2
C616
1U_0402_6.3V6K~D
2
2
C607
0.1U_0402_25V6K~D
1
5
6
7
8
9
10
2
1
C606
0.1U_0402_25V6K~D
3
1
54
MSDATA
2
0_0402_5%~D
1
@R706
@
R706
WIMAX_LED#
MSDATA
<40>
WIMAX_LED# STUDY FOR DEBUG
+3.3V_WLAN
C
WLAN_LED#
DMN66D0LDW-7_SOT363-6~D
4
WIRELESS_LED#
3
Q124B
DMN66D0LDW-7_SOT363-6~D
1
6
WIRELESS_LED# <39,43>
+3.3V_PCIE_FLASH
PWR
Rail
Voltage
Tolerance
+3.3V
Primary Power
Peak
Normal
+-9%
1000
750
+3.3Vaux
+-9%
330
250
+1.5V
+-5%
500
375
JMINI3 CONN@
PCIE_WAKE#
COEX2_WLAN_ACTIVE
1
2
R709
0_0402_5%~D
MINI3CLK_REQ#
<15> MINI3CLK_REQ#
Normal
<15> CLK_PCIE_MINI3#
<15> CLK_PCIE_MINI3
250 (Wake enable)
5 (Not wake enable)
<15>
NA
PCLK_80H
<15> PCIE_PRX_WPANTX_N5
<15> PCIE_PRX_WPANTX_P5
UIM_VPP
UIM_DATA
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
PCH_PLTRST#_EC
PCLK_80H
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
C617
1
1
C618
0.1U_0402_10V7K~D
PCIE_PTX_WPANRX_N5_C
2
PCIE_PTX_WPANRX_P5_C
2
0.1U_0402_10V7K~D
PCIE_MCARD3_DET#
<18> PCIE_MCARD3_DET#
<15> PCIE_PTX_WPANRX_N5
<15> PCIE_PTX_WPANRX_P5
1
R711
+3.3V_RUN
SUYIN_254070FB008S205ZL
+1.5V_RUN
2
100K_0402_5%~D
+3.3V_PCIE_FLASH
1
1
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
R710
2 PCIE_MCARD3_DET#
0_0402_5%~D
1
@R708
@
R708
B
+1.5V_RUN
LPC_LFRAME# <14,32,39,40>
LPC_LAD3 <14,32,39,40>
LPC_LAD2 <14,32,39,40>
LPC_LAD1 <14,32,39,40>
LPC_LAD0 <14,32,39,40>
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
1 PCH_PLTRST#_EC
0_0402_5%~D
USBP6USBP6+
USB_MCARD3_DET#
USBP6- <17>
USBP6+ <17>
2
@ R712
just reserve
1
100K_0402_5%~D
+3.3V_ALW_PCH
WPAN Noise
USB_MCARD3_DET#
54
1
LOTES_AAA-PCI-073-P02-A
C626
4.7U_0603_6.3V6K~D
1
2
C625
0.1U_0402_25V6K~D
2
2
C624
0.1U_0402_25V6K~D
2
1
C623
0.047U_0402_16V4Z~D
2
1
53
C622
0.047U_0402_16V4Z~D
2
1
@ C621
0.1U_0402_25V6K~D
1
C620
0.047U_0402_16V4Z~D
2
C619
0.047U_0402_16V4Z~D
1
A
+3.3V_PCIE_FLASH
USB_MCARD3_DET#
Aux Power
JSIM1 CONN@
GND
VPP
I/O
NC
GND
GND
GND2
USBP4- <17>
USBP4+ <17>
USB_MCARD1_DET# <18>
1/2 Minicard Flash Card H=4
+SIM_PWR
VCC
RST
CLK
NC
GND1
USBP4USBP4+
USB_MCARD1_DET#
WIMAX_LED#
WLAN_LED#
Q77
SSM3K7002FU_SC70-3~D
SIM Card Push-Push
1
2
3
4
2
1
C605
0.047U_0402_16V4Z~D
2
1
C604
0.047U_0402_16V4Z~D
1
@ C603
0.1U_0402_25V6K~D
LED_WWAN_OUT#
B
UIM_RESET
UIM_CLK
53
+3.3V_WLAN
C602
0.047U_0402_16V4Z~D
2
2
HOST_DEBUG_TX <40>
Q124A
D
+
2
S
2
1
2
0_0402_5%~D
2
WLAN_RADIO_DIS#_R
2
1 PCH_PLTRST#_EC
R703
0_0402_5%~D
MOLEX_48338-1088~D
G
+
@ C1176
330U_D2E_6.3VM_R25~D
2
1
C615
330U_D2E_6.3VM_R25~D
1
C614
33P_0402_50V8J~D
2
C613
22U_0805_6.3V6M~D
2
1
<15> PCH_CL_CLK1
<15> PCH_CL_DATA1
1
<15> PCH_CL_RST1#
R707
check
1
1
0.1U_0402_10V7K~D
2 PCIE_PTX_WLANRX_N2_C
2 PCIE_PTX_WLANRX_P2_C
0.1U_0402_10V7K~D
PCIE_MCARD1_DET#
COEX2_WLAN_ACTIVE
USBP5USBP5+
USB_MCARD2_DET#
LED_WWAN_OUT#
+3.3V_PCIE_WWAN
C612
33P_0402_50V8J~D
2
C611
0.047U_0402_16V4Z~D
C610
0.047U_0402_16V4Z~D
2
1
C596
1
1
C598
<15> PCIE_PTX_WLANRX_N2
<15> PCIE_PTX_WLANRX_P2
<18> PCIE_MCARD1_DET#
WWAN_SMBCLK
WWAN_SMBDAT
MOLEX_48338-1088~D
+3.3V_PCIE_WWAN
1
WWAN_RADIO_DIS# <39>
PCH_PLTRST#_EC <17,32,35,39,40>
C601
0.047U_0402_16V4Z~D
2
GND1
54
R704
2
0_0402_5%~D
1
100K_0402_5%~D
1
C594
0.047U_0402_16V4Z~D
2
C593
33P_0402_50V8J~D
1
53
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
<15> PCIE_PRX_WLANTX_N2
<15> PCIE_PRX_WLANTX_P2
D
2
100K_0402_5%~D
2
100K_0402_5%~D
C595 4700P_0402_25V7K~D
5
0.1U_0402_10V7K~D
2 PCIE_PTX_WANRX_N1_C
2 PCIE_PTX_WANRX_P1_C
0.1U_0402_10V7K~D
2 PCIE_MCARD2_DET#_R
0_0402_5%~D
<40> HOST_DEBUG_RX
<40> MSCLK
1
2
C597
1
<15> PCIE_PTX_WANRX_N1
1
<15> PCIE_PTX_WANRX_P1
C599
<17> PCIE_MCARD2_DET# R7251
+1.5V_RUN
+SIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
PCIE_MCARD1_DET# 1
@ R699
USB_MCARD1_DET#
1
R701
MSDATA
2
<15> PCIE_PRX_WANTX_N1
<15> PCIE_PRX_WANTX_P1
<15> CLK_PCIE_MINI2#
<15> CLK_PCIE_MINI2
R705
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<15> CLK_PCIE_MINI1#
<15> CLK_PCIE_MINI1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
MINI1CLK_REQ#
<15> MINI1CLK_REQ#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
R718
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
PCIE_WAKE#
<28,35,40> PCIE_WAKE#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
100K_0402_5%~D
+3.3V_PCIE_WWAN
PCIE_WAKE#
1
2
R7001
0_0402_5%~D
2
R702
0_0402_5%~D
<28,35,40> PCIE_WAKE#
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
+3.3V_RUN
2 PCIE_MCARD1_DET#
0_0402_5%~D
+3.3V_WLAN
JMINI2 CONN@
Mini WWAN/GPS/LTE/UWB H=5.2
2
100K_0402_5%~D
Mini WLAN/WIMAX H=6.7
WWAN_SMBCLK
100K_0402_5%~D
PCIE_MCARD2_DET#_R 1
R695
2
1
+3.3V_PCIE_WWAN
@ R1160
2.2K_0402_5%~D
@ R1159
2.2K_0402_5%~D
1
100K_0402_5%~D
1
+3.3V_RUN
USB_MCARD2_DET# 2
R694
2
@ C627
4700P_0402_25V7K~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Mini Card
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
34
of
56
5
4
3
2
Power Control for Mini card2
+PWR_SRC_S
+3.3V_ALW
+3.3V_ALW
1
Express Card PWR S/W
Q38
+3.3V_WLAN
SI3456DDV-T1-GE3_TSOP6~D
+1.5V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_CARDAUX
+1.5V_CARD
+3.3V_CARD
4
S
1
G
3
1
2
2
2
3
1
2
6
1
1
EXPRCRD_STBY_R#
+3.3V_RUN
+3.3V_CARD
+1.5V_CARD
+1.5V_RUN
2
R716
100K_0402_5%~D
17
2
12
AUXIN
3.3VIN
1.5VIN
AUXOUT
3.3VOUT
1.5VOUT
15
3
11
20
1
6
19
SHDN#
STBY#
SYSRST#
OC#
PERST#
CPPE#
CPUSB#
8
10
9
4
5
13
14
16
NC
NC
NC
NC
NC
RCLKEN
18
GND
PAD
7
21
2
1
2
1
2
1
2
1
2
C638
10U_0603_6.3V6M~D
U41
1
C637
0.1U_0402_25V6K~D
2
C641
10U_0603_6.3V6M~D
1
C640
0.1U_0402_25V6K~D
2
0_0402_5%~D
2
0_0402_5%~D
2
C643
10U_0603_6.3V6M~D
<27,39,42,48> RUN_ON
<17,32,34,39,40> PCH_PLTRST#_EC
1
C642
0.1U_0402_25V6K~D
1
R734
1
@ R717
<11,16,27,39,42,48> SIO_SLP_S3#
2
C633
0.1U_0402_25V6K~D
2
1
C634
0.1U_0402_25V6K~D
1
2
C635
0.1U_0402_25V6K~D
<39> AUX_EN_WOWL
1
R715
20K_0402_5%~D
C632
4700P_0402_25V7K~D
2
4
R1620
1M_0402_5%~D
Q39A
DMN66D0LDW-7_SOT363-6~D
R714
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
Q39B
R713
100K_0402_5%~D
5
6
5
2
1
D
D
1
D
CARD_RESET#
EXPRCRD_CPPE#
CPUSB#
TPS2231MRGPR-2_QFN20_4X4~D
Power Control for Mini card1
+PWR_SRC_S
+3.3V_ALW
D
S
1
G
2
3
1
@R727
@
R727
1
1
2
0_0402_5%~D
2
2
2
2
0_0402_5%~D
<17> USBP10-
4
<17> USBP10+
4
D
1
S
6
5
2
1
1
4
G
2
R730
20K_0402_5%~D
3
1
2
1
1
CARD_SMBCLK
CARD_SMBDAT
CARD_RESET#
2
1
2
2
1
2
3
1
2
6
DLW21SN900SQ2L_0805_4P~D
C649
0.1U_0402_25V6K~D
1
JEXP1 CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
<28,34,40> PCIE_WAKE#
+3.3V_CARDAUX
C646
0.1U_0402_25V6K~D
1
2
+3.3V_CARD
C650
4700P_0402_25V7K~D
2
<39> MCARD_MISC_PWREN
3
1
USBP10_DUSBP10_D+
CPUSB#
3
<40> CARD_SMBCLK
<40> CARD_SMBDAT
Q42
+3.3V_PCIE_FLASH
SI3456DDV-T1-GE3_TSOP6~D
R1628
1M_0402_5%~D
Q43A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
R729
Q43B
100K_0402_5%~D
R728
100K_0402_5%~D
5
4
L49
Power Control for Mini card3
+3.3V_ALW
+PWR_SRC_S
1
<18> EXPRCRD_DET#
1
@R724
@
R724
2
MCARD_WWAN_PWREN#
B
+3.3V_ALW
+1.5V_CARD
1
2
G
S
3
4
1
2
3
1
2
6
1
2
2
+3.3V_SUS
D
C645
0.1U_0402_25V6K~D
1
1
Express Card Conn.
R723
1K_0402_1%~D
R732
2.2K_0402_5%~D
R726
100K_0402_5%~D
4
R731
2.2K_0402_5%~D
<39> MCARD_WWAN_PWREN
6
5
2
1
SSM3K7002FU_SC70-3~D
Q73
2
Q40
SI3456DDV-T1-GE3_TSOP6~D
C644
4700P_0402_25V7K~D
Q41A
DMN66D0LDW-7_SOT363-6~D
C
Note: Add connection on pin4, pin5, pin 13
and pin14 to support GMT 2nd source part
+3.3V_PCIE_WWAN
R1625
1M_0402_5%~D
MCARD_WWAN_PWREN# 5
R722
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
Q41B
R721
100K_0402_5%~D
1
+3.3V_ALW
2
C
<15> EXPCLK_REQ#
EXPRCRD_CPPE#
<15> CLK_PCIE_EXP#
<15> CLK_PCIE_EXP
<15> PCIE_PRX_EXPTX_N3
<15> PCIE_PRX_EXPTX_P3
<15> PCIE_PTX_EXPRX_N3
<15> PCIE_PTX_EXPRX_P3
C647
1
1
C648
0.1U_0402_10V7K~D
2 PCIE_PTX_EXPRX_N3_C
2 PCIE_PTX_EXPRX_P3_C
0.1U_0402_10V7K~D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
GND
B
TYCO_2-2041070-6~D
R733
100K_0402_5%~D
A
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PCIE-SATA SW / PCIE PWR
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
35
of
56
5
4
3
2
1
+5V_USB_PWR
D79
USB3RP2
1
4
1
3
3
USB3RN2_D-
2
2
USB3RP2_D+
1
10
USB3RN2_D-
USB3RP2_D+
2
9
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
1
USB3TP2_D+
5
6
USB3TP2_D+
+
JUSB2
3
D
U49
2
10
9
8
7
6
11
USB_OC0#
1
@R1609
@
R1609
<17>
2
0_0402_5%~D
8
1
IP4292CZ10-TB_XSON10U10~D
1
<39> USB_SIDE_EN#
GND FAULT1#
IN
OUT1
IN
OUT2
EN1#
ILIM
EN2# FAULT#2
T-PAD
2
R750
24.9K_0402_1%~D
TPS2560DRCR-PG1.1_SON10_3X3~D
USB3RN2_DUSB3RP2_D+
USB3TN2_DUSB3TP2_D+
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
10
11
12
13
GND
GND
GND
GND
D
SANTA_373130-1
new conn
L52
2
1
C677
0.1U_0402_25V6K~D
2
C678
10U_0805_10V6K~D
1
1
2
3
4
5
2
1
1
2
3
4
5
6
7
8
9
USBP1_DUSBP1_D+
D73
PESD5V0U2BT_SOT23-3~D
DLW21SN900HQ2L_0805_4P~D
1
2
@R1608
@
R1608
0_0402_5%~D
+5V_USB_PWR
+5V_ALW
USB3RN2_D-
2
4
C655
0.1U_0402_25V6K~D
USB3RP2
USB3RN2
C652
150U_B2_6.3V-M~D
<17>
USB3RN2
3
L97
<17>
L98
<17>
USB3TN2
2
C410
<17>
USB3TP2
2
C411
USB3TN2_C
1
0.01U_0402_16V7K~D
4
4
USB3TP2_C
1
0.01U_0402_16V7K~D
1
1
3
3
USB3TN2_D-
2
2
USB3TP2_D+
<17>
USBP1+
4
<17>
USBP1-
1
3
1
2
3
USBP1_D+
2
USBP1_D-
DLW21SN900SQ2L_0805_4P~D
1
2
@ R737
0_0402_5%~D
DLW21SN900HQ2L_0805_4P~D
1
2
@ R1612
0_0402_5%~D
1
@ R1607
4
1
@ R739
2
0_0402_5%~D
2
0_0402_5%~D
+SATA_SIDE_PWR
+5V_ALW
+5V_USB_CHG_PWR
U2
8
7
6
5
USBP0USBP0+
+5V_ALW
SB
YY+
VDD
INT
DD+
SEL
GND
1
2
3
4
9
1
PWRSHARE_EN#
USB_OC4#
<17>
USB_OC0#
<17>
C
R748
24.9K_0402_1%~D
TPS2560DRCR-PG1.1_SON10_3X3~D
D
S
Q48
SSM3K7002FU_SC70-3~D
1
2
G
2
2
2
<39> ESATA_USB_PWR_EN#
10
9
8
7
6
11
PWRSHARE_EN#
R1614
10K_0402_5%~D
C715
0.1U_0402_25V6K~D
PI5USB1457AZAEX_TDFN8_2X2~D
2
1
<17>
<17>
1
2
R816
100K_0402_5%~D
PWRSHARE_EN
USBP0_DUSBP0_D+
SEL
+5V_ALW
3
<39> USB_PWR_SHR_EN#
SB#
10_0402_5%~D
2
R1626
1
GND FAULT1#
IN
OUT1
IN
OUT2
EN1#
ILIM
EN2# FAULT#2
T-PAD
2
1
2
2
0_0402_5%~D
C675
0.1U_0402_25V6K~D
1
R784
<39> USB_PWR_SHR_VBUS_EN
C676
10U_0805_10V6K~D
+5V_ALW
C
1
2
3
4
5
1
U48
@ R1613
10K_0402_5%~D
+5V_USB_CHG_PWR
1
+3.3V_RUN
JUSB1
USB3TN1
<17>
USB3RP1
<17>
USB3RN1
2
C414
2
C415
2
C416
2
C417
USB3TP1_C
1
0.01U_0402_16V7K~D
USB3TN1_C
1
0.01U_0402_16V7K~D
USB3RP1_C
1
0.01U_0402_16V7K~D
USB3RN1_C
1
0.01U_0402_16V7K~D
19
20
22
23
3
4
16
15
VDD
VDD
PD#
A_DE1
B_DE1
A_EQ0
B_EQ0
A_INp A_OUTp
A_INn A_OUTn
B_INp
B_OUTp B_INn
B_OUTn REXT
TEST
I2C_R0 12C_EN
I2C_R1
GND
SCL_CTL GND
SDA_CTL EPAD
18
6
17
2
12
11
9
8
7
14
24
21
10
25
A
1
@ R783
1
@ R781
1
@ R779
1
@ R773
1
4
3
1
2
3
USB3RN1_D-
2
USB3RP1_D+
DLW21SN900HQ2L_0805_4P~D
1
2
@ R1605
0_0402_5%~D
1
@ R1604
2
1
USB3RP1_RP
2
0_0402_5%~D
USB3RN1_DUSB3RP1_D+
USB3TN1_DUSB3TP1_D+
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
B
SANTA_373280-1
new conn
D78
USB3RN1_D-
1
10
USB3RN1_D-
USB3RP1_D+
2
9
USB3RP1_D+
USB3TN1_D-
4
7
USB3TN1_D-
USB3TP1_D+
5
6
USB3TP1_D+
L96
USB3TN1_RP
2
C412
1 USB3TN1_RP_C
0.01U_0402_16V7K~D
4
USB3TP1_RP
2
C413
1 USB3TP1_RP_C
0.01U_0402_16V7K~D
1
4
3
1
2
3
USB3TN1_D-
2
USB3TP1_D+
3
8
R751
3.3K_0402_1%~D
2
+B_DE0
2
4.7K_0402_5%~D
+B_EQ1
2
4.7K_0402_5%~D
+A_DE0
2
4.7K_0402_5%~D
+A_EQ1
2
4.7K_0402_5%~D
4
@
+A_DE1
+B_DE1
+A_EQ0
+B_EQ0
USB3TP1_RP
USB3TN1_RP
USB3RP1_RP
USB3RN1_RP
PS8710BTQFN24GTR-A0_TQFN24_4X4
+3.3V_RUN
@
R771
4.7K_0402_5%~D
2
1
@
R754
4.7K_0402_5%~D
2
1
R753
4.7K_0402_5%~D
2
1
R752
4.7K_0402_5%~D
2
1
@
U90
1
USB3TP1
<17>
1
13
5
L95
USB3RN1_RP
2
D72
PESD5V0U2BT_SOT23-3~D
<17>
2
+
2
1
C654
0.1U_0402_25V6K~D
2
1
C670
0.1U_0402_25V6K~D
B
C669
0.01U_0402_16V7K~D
1
C651
150U_B2_6.3V-M~D
1
1
2
3
4
5
6
7
8
9
USBP0_R_DUSBP0_R_D+
3
+3.3V_RUN
IP4292CZ10-TB_XSON10U10~D
DLW21SN900HQ2L_0805_4P~D
1
2
@ R1606
0_0402_5%~D
USBP0_D+
4
1
@ R1603
USBP0_D-
1
L51
2
0_0402_5%~D
4
3
1
2
3
USBP0_R_D+
2
USBP0_R_D-
DLW21SN900SQ2L_0805_4P~D
1
2
@ R736
0_0402_5%~D
1
@ R740
A
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
USB 3.0 x2
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
36
of
56
3
2
ESATA Repeater
2
1
2
1
2
2
R743
0_0402_5%~D
<14> ESATA_PRX_DTX_P4_C
2
@ R742
0_0402_5%~D
<14> ESATA_PRX_DTX_N4_C
2
ESATA_PTX_DRX_P4
0.01U_0402_16V7K~D
1 ESATA_PTX_DRX_N4
0.01U_0402_16V7K~D
1 ESATA_PRX_DTX_N4
0.01U_0402_16V7K~D
1 ESATA_PRX_DTX_P4
0.01U_0402_16V7K~D
R1594
0_0402_5%~D
<14> ESATA_PTX_DRX_N4_C
2
2
R1595
0_0402_5%~D
ESATA_PTX_DRX_P4_C
C663
ESATA_PTX_DRX_N4_C
C664
ESATA_PRX_DTX_N4_C
C665
ESATA_PRX_DTX_P4_C
C666
<14> ESATA_PTX_DRX_P4_C
2
0_0402_5%~D
C662
0.1U_0402_25V6K~D
1
R741
C661
0.01U_0402_16V7K~D
2
+3.3V_RUN
1
1
+3.3V_RUN
1
D
1
1
4
2
5
D
U44
7
17
19
18
1
1
2
4
5
3
13
21
EN
VCC
NC_GND_VDD
VCC
NC_GND_VDD
PREXT/NC/VDD
NC_GND_VDDNC/GND/VDD
A_INp
A_INn
B_OUTn
B_OUTp
GND
GND
GND
A_PRE
B_PRE
6
16
20
10
REXT
ESATA_PE1
ESATA_PE2
9
8
A_OUTp
A_OUTn
15
14
ESATA_PTX_DRX_P4_RP
ESATA_PTX_DRX_N4_RP
B_INp
B_INn
11
12
ESATA_PRX_DTX_P4_RP
ESATA_PRX_DTX_N4_RP
PS8513BTQFN20GTR-A0_TQFN20_4X4
C
C
+SATA_SIDE_PWR
2
1
2
C668
0.1U_0402_25V6K~D
+
C667
150U_B2_6.3V-M~D
1
JESA1 CONN@
USBP9_DUSBP9_D+
1
2
3
4
VBUS
DD+
GND
USB
B
B
ESATA_PTX_DRX_P4_RP
1
C671
ESATA_PTX_DRX_N4_RP
1
C672
ESATA_PRX_DTX_N4_RP
1
C673
ESATA_PRX_DTX_P4_RP
1
C674
L90
1
USBP9-
4
1
4
2
3
2
USBP9_D+
3
USBP9_D-
DLW21SN900SQ2L_0805_4P~D
1
2
@ R1150
0_0402_5%~D
1
@ R1151
5
6
7
8
9
10
11
12
13
14
15
2
<17>
USBP9+
3
<17>
2 SATA_PTX_DRX_P4
0.01U_0402_16V7K~D
2 SATA_PTX_DRX_N4
0.01U_0402_16V7K~D
2 SATA_PRX_DTX_N4
0.01U_0402_16V7K~D
2 SATA_PRX_DTX_P4
0.01U_0402_16V7K~D
2
0_0402_5%~D
GND
A+
ESATA
AGND
BB+
GND
GND
GND
GND
GND
D74
TYCO_2129160-2~D
1
PESD5V0U2BT_SOT23-3~D
Place D74 close to JESATA1
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB/ESATA/IO/MDC
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
37
of
56
5
4
3
2
1
JDOCK1 CONN@
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1
C692
C685
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2
C687
C689
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
DPD_DOCK_AUX
DPD_DOCK_AUX#
<26> DPD_DOCK_AUX
<26> DPD_DOCK_AUX#
DPD_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD
Close to DOCK
Its for Enhance ESD on dock issue.
BLUE_DOCK
<24> BLUE_DOCK
RED_DOCK
<24> RED_DOCK
GREEN_DOCK
<24> GREEN_DOCK
<24> HSYNC_DOCK
<24> VSYNC_DOCK
DPD_PCH_DOCK_HPD
<40> CLK_MSE
<40> DAT_MSE
C
1
<29> DAI_BCLK#
<29> DAI_LRCK#
R757
100K_0402_5%~D
2
<29> DAI_DI
<29> DAI_DO#
<29> DAI_12MHZ#
<39>
<39>
D_LAD0
D_LAD1
<39>
<39>
D_LAD2
D_LAD3
<39> D_LFRAME#
<39> D_CLKRUN#
<39> D_SERIRQ
<39> D_DLDRQ1#
<17> CLK_PCI_DOCK
<40> DOCK_SMB_CLK
<40> DOCK_SMB_DAT
<39,55> DOCK_SMB_ALERT#
<45> DOCK_PSID
B
<40> DOCK_PWR_BTN#
SLICE_BAT_PRES#
<39,55> SLICE_BAT_PRES#
2
3
@
153
154
155
156
157
158
GND1
PWR1
PWR1
PWR1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
DOCK_AC_OFF <39,55>
DOCK_LOM_SPD100LED_ORG# <31>
DPC_CA_DET <26>
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
C691 2
C680 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
C682 2
C684 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
C693 2
C686 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
C688 2
C694 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPC_DOCK_AUX
DPC_DOCK_AUX#
DPC_PCH_LANE_P0 <16>
DPC_PCH_LANE_N0 <16>
D
DPC_PCH_LANE_P1 <16>
DPC_PCH_LANE_N1 <16>
DPC_PCH_LANE_P2 <16>
DPC_PCH_LANE_N2 <16>
DPC_PCH_LANE_P3 <16>
DPC_PCH_LANE_N3 <16>
DPC_DOCK_AUX <26>
DPC_DOCK_AUX# <26>
DPC_PCH_DOCK_HPD
DPC_PCH_DOCK_HPD <16>
ACAV_DOCK_SRC# <55>
1
DAT_DDC2_DOCK <24>
CLK_DDC2_DOCK <24>
2
SATA_PRX_DKTX_P5
SATA_PRX_DKTX_N5
SATA_PTX_DKRX_P5
SATA_PTX_DKRX_N5
2
C697 2
C698
1
C699 1
C700
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
2 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
SATA_PRX_DKTX_P5_C <14>
SATA_PRX_DKTX_N5_C <14>
SATA_PTX_DKRX_P5_C <14>
SATA_PTX_DKRX_N5_C <14>
USBP8+ <17>
USBP8- <17>
Close to DOCK
Its for Enhance ESD on dock issue.
DPC_PCH_DOCK_HPD
USBP3+ <17>
USBP3- <17>
C
CLK_KBD <40>
DAT_KBD <40>
R758
100K_0402_5%~D
USB3RN4 <17>
USB3RP4 <17>
USB3TN4 <17>
USB3TP4 <17>
BREATH_LED# <39,43>
DOCK_LOM_ACTLED_YEL# <31>
DOCK_LOM_TRD0+ <31>
DOCK_LOM_TRD0- <31>
+3.3V_ALW
DOCK_LOM_TRD1+ <31>
DOCK_LOM_TRD1- <31>
+LOM_VCT
1
+LOM_VCT
DOCK_LOM_TRD2+ <31>
DOCK_LOM_TRD2- <31>
2
DOCK_DET#
@
C701
1U_0402_6.3V6K~D
1
R755
2
100K_0402_5%~D
DOCK_LOM_TRD3+ <31>
DOCK_LOM_TRD3- <31>
DOCK_DCIN_IS+ <53>
DOCK_DCIN_IS- <53>
D32
RB751S40T1_SOD523-2~D
1
2
DOCK_POR_RST# <40>
DOCK_DET_R#
149
150
151
152
B
DOCK_DET#
<39>
+DOCK_PWR_BAR
1
159
160
161
162
163
164
2
DAI_12MHZ#
DAI_BCLK#
1
SM24.TCT_SOT23-3~D
2
D33
1
1
@
C702
0.1U_0603_50V7K~D
2
CE6
4.7U_0805_25V6K~D
1
145
146
147
148
DPC_CA_DET
C703
0.1U_0603_50V7K~D
+DOCK_PWR_BAR
DOCK_AC_OFF
C696
0.033U_0402_16V7K~D
2
+NBDOCK_DC_IN_SS
C695
0.033U_0402_16V7K~D
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
<16> DPD_PCH_LANE_P3
<16> DPD_PCH_LANE_N3
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
2
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
<16> DPD_PCH_LANE_P2
<16> DPD_PCH_LANE_N2
2
2
C681
C683
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
JAE_WD2F144WB3R300~D
R756
33_0402_5%~D
2
@ RE12
10_0402_1%~D
2
@ RE11
10_0402_1%~D
1
2
CLK_PCI_DOCK
1
<16> DPD_PCH_LANE_P1
<16> DPD_PCH_LANE_N1
C690
C679
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
2
<16> DPD_PCH_LANE_P0
<16> DPD_PCH_LANE_N0
D
DPD_CA_DET
1
DOCK_DET_1
<31> DOCK_LOM_SPD10LED_GRN#
<26> DPD_CA_DET
1
@CE8
@CE8
4.7P_0402_50V8C~D
2
1
@CE9
@CE9
4.7P_0402_50V8C~D
2
C704
12P_0402_50V8J~D
A
A
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DOCKING CONN
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
38
of
56
5
4
3
2
1
+3.3V_ALW
WWAN_RADIO_DIS#
2
100K_0402_5%~D
1
R776
USB_PWR_SHR_EN#
2
100K_0402_5%~D
1
R768
USB_SIDE_EN#
2
10K_0402_5%~D
C
<24> CRT_SWITCH
<35> MCARD_MISC_PWREN
<53> PROCHOT_GATE
USB_PWR_SHR_VBUS_EN
2
100K_0402_5%~D
1
R785
DOCK_SMB_ALERT#
2
10K_0402_5%~D
SYS_LED_MASK#
2
10K_0402_5%~D
1
R775
<36> USB_SIDE_EN#
<29> EN_I2S_NB_CODEC#
<32> USH_PWR_STATE#
<55> EN_DOCK_PWR_BAR
<23> PANEL_BKEN_EC
<16,23> ENVDD_PCH
<23> LCD_TST
<45> PSID_DISABLE#
<45,55> PBAT_PRES#
<31>
DOCKED
<38> DOCK_DET#
<29> AUD_NB_MUTE#
<35> MCARD_WWAN_PWREN
<23> LCD_VCC_TEST_EN
<23> CCD_OFF
<29,30> AUD_HP_NB_SENSE
<36> ESATA_USB_PWR_EN#
<55> MODULE_ON
<55> SLICE_BAT_ON
<38,55> SLICE_BAT_PRES#
<45,55> MODULE_BATT_PRES#
<55> CHARGE_MODULE_BATT
<55> CHARGE_PBATT
<55> DEFAULT_OVRDE
<36> USB_PWR_SHR_EN#
CHARGE_EN
2
100K_0402_5%~D
1
R3
CRT_SWITCH
B52
A49
B53
A50
B54
A51
B55
A52
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WWAN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
CHARGE_MODULE_BATT
CHARGE_PBATT
DEFAULT_OVRDE
B32
A31
B33
B15
A15
B16
A16
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
<38,55> DOCK_SMB_ALERT#
1
R778
MCARD_PCIE_SATA#
2
100K_0402_5%~D
WIRELESS_ON#/OFF
2
100K_0402_5%~D
SP_TPM_LPC_EN
2
10K_0402_5%~D
LCD_TST
2
100K_0402_5%~D
<7> CPU_DETECT#
<28> MOD_SATA_PCIE#_DET
<28> ZODD_WAKE#
<32> BCM5882_ALERT#
<16> SUSACK#
USB_PWR_SHR_EN#
MCARD_PCIE_SATA#
CPU_DETECT#
MOD_SATA_PCIE#_DET
ZODD_WAKE#
BCM5882_ALERT#
VGA_ID
<18> SLP_ME_CSW_DEV#
<31> LAN_DISABLE#_R
B
<43> SYS_LED_MASK#
<18> SIO_EXT_WAKE#
<34,43> WIRELESS_LED#
<36> USB_PWR_SHR_VBUS_EN
<34> WLAN_RADIO_DIS#
+3.3V_ALW
VGA_ID
2
100K_0402_5%~D
1
R800
VGA_ID
1
@R803
@
R803
2
100K_0402_5%~D
<30> WIRELESS_ON#/OFF
<41> BT_RADIO_DIS#
<34> WWAN_RADIO_DIS#
<7,16> SYS_PWROK
<50> CPU_VTT_ON
<16> PCH_DPWROK
SLP_ME_CSW_DEV#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
DYN_TURB_PWR_ALRT#
R797 1
2 0_0402_5%~D
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
2
0_0402_5%~D
CPU_VTT_ON
1
@R802
@
R802
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
B63
A60
A61
B65
A62
B66
A63
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
B67
A64
A5
B6
A6
B7
A7
B8
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
A8
B9
B10
A10
B11
A11
B12
A12
ME_FWP
MASK_SATA_LED#
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
B60
A57
B64
B68
A9
B1
A18
A44
SUS_ON
B34
B39
B51
HW_GPS_DISABLE2#
BREATH_LED#
A27
A26
B26
B25
A21
B22
A28
B20
A23
A22
B21
A32
B35
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
CLK_PCI_5048
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
B29
B28
A25
A24
B23
A19
B24
A20
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
A29
B31
A30
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
PWRGD
OUT65
TEST_PIN
VSS
EP
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
UMA
1
2
C710
0.1U_0402_25V6K~D
1
R765
2
0_0402_5%~D
SIO_SLP_LAN#
SIO_SLP_SUS#
MODC_EN
DOCK_HP_DET
DOCK_MIC_DET
LED_SATA_DIAG_OUT#
TEMP_ALERT#_R
RUN_ON
AUX_EN_WOWL <35>
WLAN_LAN_DISB# <31>
SIO_SLP_LAN# <16,31>
SIO_SLP_SUS# <16>
GPIO_PSID_SELECT <45>
MODC_EN
<28>
DOCK_HP_DET <29>
DOCK_MIC_DET <29>
RUN_ON
2
<27,35,42,48>
A
1
O 4D34 2@
RB751S40T1_SOD523-2~D
U47 @
TC7SH08FU_SSOP5~D
2TEMP_ALERT#
0_0402_5%~D
1
R738
TEMP_ALERT# <18>
+3.3V_RUN
D_CLKRUN#
<42>
D_SERIRQ
BAT1_LED#
<43> trace width 20 mils
D_DLDRQ1#
BAT2_LED#
<43> trace width 20 mils
USH_PWR_ON
2
R777
2
R780
2
R782
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
RUN_ON
2
R786
1
100K_0402_5%~D
CPU_VTT_ON
2
R789
1
100K_0402_5%~D
0.75V_DDR_VTT_ON 2
R790
SLICE_BAT_ON
2
R791
SUS_ON
2
R878
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
HW_GPS_DISABLE2# <34>
BREATH_LED# <38,43>
LPC_LAD0 <14,32,34,40>
LPC_LAD1 <14,32,34,40>
LPC_LAD2 <14,32,34,40>
LPC_LAD3 <14,32,34,40>
LPC_LFRAME# <14,32,34,40>
PCH_PLTRST#_EC <17,32,34,35,40>
CLK_PCI_5048 <17>
CLKRUN# <16,32,40>
LPC_LDRQ0# <14>
LPC_LDRQ1# <14>
IRQ_SERIRQ <14,32,40>
CLK_SIO_14M <15>
EC_32KHZ_ECE5048 <40>
D_LAD0
<38>
D_LAD1
<38>
D_LAD2
<38>
D_LAD3
<38>
D_LFRAME# <38>
D_CLKRUN# <38>
D_DLDRQ1# <38>
D_SERIRQ <38>
RUNPWROK
SP_TPM_LPC_EN
B19
1
R804
+CAP_LDO
B
BC_INT#_ECE5048 <40>
BC_DAT_ECE5048 <40>
BC_CLK_ECE5048 <40>
RUNPWROK
<7,40>
SP_TPM_LPC_EN <32>
2
1K_0402_1%~D
+3.3V_ALW
+CAP_LDO trace width 20 mils
CLK_SIO_14M
1
C714
4.7U_0603_6.3V6K~D
CLK_PCI_5048
@R794
@
R794
10_0402_1%~D
R805
100K_0402_5%~D
@ R795
10_0402_1%~D
1
2
LID_CL_SIO#
2
R807
1
LID_CL#
10_0402_1%~D
<30,43>
1
1
@ C713
4.7P_0402_50V8C~D
2
C716
0.047U_0402_16V4Z~D
A
2
DELL CONFIDENTIAL/PROPRIETARY
1
ME_FWP
Compal Electronics, Inc.
@ R793
1K_0402_1%~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
C
PAD~D T117 @
ME_FWP PCH has internal 20K PD.
(suspend power rail)
5
DOCK_AC_OFF <38,55>
R770 @
33K_0402_5%~D
SUS_ON
@ C712
4.7P_0402_50V8C~D
A
B
SPI_WP#_SEL <14>
BAT2_LED#
2
0.1U_0402_25V6K~D
2
DOCK_AC_OFF_EC <55>
ME_FWP
<14>
MASK_SATA_LED# <43>
1.8V_RUN_PWRGD <48>
LED_SATA_DIAG_OUT# <43>
BAT1_LED#
A4
B27
C1
1
DOCK_AC_OFF_EC
B56
B46
+3.3V_ALW
@ C711
1
<40,53,55>
SIO_SLP_A#
<16,42,49>
0.75V_DDR_VTT_ON <47>
SIO_SLP_S4# <16>
SIO_SLP_S3# <11,16,27,35,42,48>
IMVP_PWRGD <51>
IMVP_VR_ON <51>
2
VGA_ID0
0
2
ACAV_IN_NB
SIO_SLP_A#
0.75V_DDR_VTT_ON
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
CAP_LDO
Discrete
2
1
C709
0.1U_0402_25V6K~D
B5
A17
B30
A43
A54
U46
ESATA_USB_PWR_EN#
2
100K_0402_5%~D
1
R457
1
R766
1
@ R772
1
R767
1
C708
0.1U_0402_10V7K~D
D
1
R769
+3.3V_RUN
2
1
C707
0.1U_0402_25V6K~D
1
1
R774
2
1
C706
0.1U_0402_25V6K~D
2
SLICE_BAT_PRES#
2
100K_0402_5%~D
2
VCC1
VCC1
VCC1
VCC1
VCC1
D
1
C705
10U_0603_6.3V6M~D
1
1
R760
1
2
CPU_DETECT#
2
100K_0402_5%~D
5
1
R763
+3.3V_ALW
P
PROCHOT_GATE
2
100K_0402_5%~D
G
1
R761
3
HW_GPS_DISABLE2#
2
100K_0402_5%~D
1
1
R798
2
DYN_TURB_PWR_ALRT#
2
10K_0402_5%~D
1
1
R796
2
Title
ECE5048
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
39
of
56
5
4
3
2
1
+3.3V_ALW
+RTC_CELL
1
VCCSAPWROK
2
B
A
O
3
Modify name net
@ C721
1U_0402_6.3V6K~D
1
2
R810
100K_0402_5%~D
U50
2
5
1.05V_VTTPWRGD
P
<54> VCCSAPWROK
G
<50,54> 1.05V_VTTPWRGD
1
C720
0.1U_0402_25V6K~D
2
1
1.05V_0.8V_PWROK
4
1.05V_0.8V_PWROK
<14,51>
POWER_SW_IN#
<22> POWER_SW_IN#
1
R811
1
TC7SH08FU_SSOP5~D
2
10K_0402_5%~D
POWER_SW#_MB <30,41>
C722
1U_0402_6.3V6K~D
2
+3.3V_ALW
2
22P_0402_50V8J~D
2
MEC_XTAL2
1
Y6
32.768KHZ_12.5PF_Q13FC1350000~D
<39> EC_32KHZ_ECE5048
MEC_XTAL2 2
R1068
1
R867
A11
A22
B35
A41
A58
A52
B3
A26
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
PECI
XTAL1
XTAL2
GPIO160/32KHZ_OUT
DB Version 0.12
NC1
NC2
NC3
PECI_VREF
PECI
I2S
B66
15mil
VR_CAP
B34
A64
B68
1
2
1
2
R870
100K_0402_5%~D
DDR_HVREF_RST_GATE <7>
DYN_TUR_CURRNT_SET#
<53>
CPU1.5V_S3_GATE <11>
MSDATA
<34>
MSCLK
<34>
SIO_A20GATE <18>
PS_ID
<45>
LAT_ON_SW#
FWP#
PROCHOT#_EC
2 1K_0402_1%~D
R886 1
R887 2
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
PM_APWROK
1.05V_A_PWRGD
ALW_PWRGD_3V_5V
DEVICE_DET#
RESET_OUT#
2 1K_0402_1%~D
1 1K_0402_1%~D
ME_SUS_PWR_ACK <16>
1.5V_SUS_PWRGD <47>
PM_APWROK <16>
1.05V_A_PWRGD <49>
ALW_PWRGD_3V_5V <46>
DEVICE_DET# <28>
RESET_OUT# <16>
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
VOL_MUTE
<30>
VOL_UP
VOL_DOWN
<30>
<30>
1
@ R1179
1
@ R812
1
1
1
2
2
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
USH_SMBDAT
USH_SMBCLK
1
RUNPWROK
CHARGER_SMBDAT <53>
CHARGER_SMBCLK <53>
CARD_SMBDAT <35>
CARD_SMBCLK <35>
USH_SMBDAT <32>
USH_SMBCLK <32>
<42> RUN_ON_ENABLE#
I2S_DAT
I2S_CLK
I2S_WS
AC_PRESENT
A59
B63
A60
A63
B67
B1
A1
LAT_ON_SW#
ALWON
VCI_IN1#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#
B51
A48
+PECI_VREF
PECI_EC_R
ALWON
R863
1
2
PECI_EC
43_0402_5%~D
<7>
B17
B27
B28
+1.05V_RUN_VTT
R863 close to
U51& least 250mils
1
2
R862
0_0402_5%~D
1
BAY_SMBCLK
DYN_TUR_CURRNT_SET#
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
2
R854
2
R856
2
R1171
2
R1125
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
DAT_KBD
VCI_IN1#
2
R1156
1
100K_0402_5%~D
2
MSDATA
1
10K_0402_5%~D
1
DDR_ON
2
100K_0402_5%~D
CLK_MSE
2
R845
2
R846
2
R851
2
R852
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
+3.3V_RUN
2
R872
10K_0402_5%~D
1
1
BOARD_ID
1
2
4
1
R883
@ R879
10K_0402_5%~D
Q50
SSM3K7002FU_SC70-3~D
3
SYSTEM_ID
C744
4700P_0402_25V7K~D
D
2
G
1
RESET_OUT#
S
1
2
R871
1K_0402_1%~D
R875
240K_0402_5%~D
R882
<22>
2
PCH_PWRGD#
R880
R881
FWP#
2
+3.3V_ALW
REV
@ R843
R889
R892
1
2
B
+5V_RUN
CLK_KBD
C740
4.7U_0603_6.3V6K~D
PCH_ALW_ON
2
100K_0402_5%~D
DOCK_POR_RST#
2
100K_0402_5%~D
EN_INVPWR
2
100K_0402_5%~D
2 1.05V_0.8V_PWROK
10K_0402_5%~D
1
1
1
1
VOL_MUTE
2
R1169
VOL_DOWN
2
R1197
VOL_UP
2
R1118
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2 RESET_OUT#
8.2K_0402_5%~D
2 CPU1.5V_S3_GATE
100K_0402_5%~D
2 PCH_RSMRST#
10K_0402_5%~D
1
1
1
A
DELL CONFIDENTIAL/PROPRIETARY
CHIPSET_ID for BID
function
BOARD_ID rise time is measured from 5%~68%.
5
DEVICE_DET#
2
R418
2
R420
2
R838
2
R841
+3.3V_ALW
C744
+3.3V_ALW_PCH
2
10K_0402_5%~D
+RTC_CELL
2
1
2
2
DOCK_SMB_DAT
BAY_SMBDAT
GPIO024/THSEL_STRAP note
i.THSEL_STRAP =1 (selects thermistor on diode channel 1)
ii.THSEL_STRAP = 0 (selects remote diode on diode channel 1)
+3.3V_M
C742
4700P_0402_25V7K~D
1
@ C747
4.7P_0402_50V8C~D
LCD_SMBDAT
DOCK_SMB_CLK
C737
0.1U_0402_25V6K~D
2
LCD_SMBCLK
MEC5055-LZY_DQFN132_11X11~D
HOST_DEBUG_TX
HOST_DEBUG_RX
130K 4700p X01
62K 4700p X02
33K 4700p A00
8.2K 4700p
4.3K 4700p
2K 4700p
1K 4700p
@ R885
10_0402_1%~D
S
1
R835
+3.3V_ALW
<22,53,55>
DAT_MSE
* 240K 4700p X00
CLK_PCI_MEC
D
2
G
<46>
ACAV_IN
+3.3V_ALW
Place closely pin A29
2
0_0402_5%~D
R799
10K_0402_5%~D
R869
R875
A
1
R1180
BAY_SMBDAT <28,45>
BAY_SMBCLK <28,45>
R893
100K_0402_5%~D
G1
G2
G3
G4
ACES_87153-10411
S
DOCK_SMB_DAT <38>
DOCK_SMB_CLK <38>
1
1
1
1
1
2
1
2
2
2
2
1
2
2
2
2 0_0402_5%~D
0_0402_5%~D
2
100K_0402_5%~D
20mA drive pins
R876
1
R853 1
R855
@ Q47
SSM3K7002FU_SC70-3~D
2
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
@ R850
100K_0402_5%~D
R848
10K_0402_5%~D
R849
10K_0402_5%~D
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEB_TX
HOST_DEB_RX
2
C740 close to U51.B12
R847
10K_0402_5%~D
10
11
12
13
14
R861
10K_0402_5%~D
8
R860
10K_0402_5%~D
6
1
2
3
4
5
6
7
8
9
10
R859
10K_0402_5%~D
4
1
2
3
4
5
6
7
8
9
10
R858
10K_0402_5%~D
2
R864
49.9_0402_1%~D
CONN@
JDEG2
D
2
G
Bat2 = Amber LED
Bat1 = Blue LED
1
+3.3V_ALW
<7,51,53>
C
PROCHOT#_EC
PCH_RSMRST# <41>
AC_PRESENT <16>
SIO_PWRBTN# <16>
least
15mil
+3.3V_ALW
H_PROCHOT#
2
10K_0402_5%~D
1
R884 1
DELL PWR SW INF
2
22P_0402_50V8J~D
DDR_HVREF_RST_GATE
DYN_TUR_CURRNT_SET#
CPU1.5V_S3_GATE
MSDATA
MSCLK
SIO_A20GATE
PS_ID
<38>
+RTC_CELL
3
B64
GPIO011/nSMI
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/nEC_SCI
MASTER CLOCK
A61
A62
B62
DDR_ON
<47>
HOST_DEBUG_TX <34>
HOST_DEBUG_RX <34>
RUNPWROK
<7,39>
EN_INVPWR <23>
PCH_SATA_MOD_EN# <14>
DOCK_PWR_BTN#
+3.3V_RUN
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
HOST INTERFACE
MEC_XTAL1
MEC_XTAL2_R
1
20_0402_5%~D
0_0402_5%~D
B2
A2
B8
B18
A8
B9
A9
A14
B15
A17
B39
A44
B47
A54
B58
SMBUS INTERFACE
+VR_CAP B12
C743
1
GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO022/BCM_B_CLK
GPIO023/BCM_B_DAT
GPIO024/BCM_B_INT#
GPIO044/BCM_C_CLK
GPIO043/BCM_C_DAT
GPIO042/BCM_C_INT#
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT
GPIO045/LSBCM_D_INT#
GPIO032/GPTP-IN3/BCM_E_CLK
GPIO31/GPTP-OUT2/BCM_E_DAT
GPIO30/GPTP-IN2/BCM_E_INT#
VSS[1]
VSS[4]
MEC_XTAL1
B
GPIO001/ECSPI_CS1
GPIO002/ECSPI_CS2
GPIO014/GPTP-IN7/HSPI_CS1
GPIO040/GPTP-OUT3/HSPI_CS2
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO026/GPTP-IN1
GPIO027/GPTP-OUT1
GPIO041
GPIO107/nRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
B11
B60
C741
1
<14,32,39> IRQ_SERIRQ
<17,32,34,35,39> PCH_PLTRST#_EC
<17> CLK_PCI_MEC
<14,32,34,39> LPC_LFRAME#
<14,32,34,39> LPC_LAD0
<14,32,34,39> LPC_LAD1
<14,32,34,39> LPC_LAD2
<14,32,34,39> LPC_LAD3
<16,32,39> CLKRUN#
<18> SIO_EXT_SCI#
A6
A27
B29
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
SYSTEM_ID
BOARD_ID
DDR_ON
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR
2
10K_0402_5%~D
C734
1U_0402_6.3V6K~D
1
32 KHz Clock
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
1
1 R825
3
2
<17> SIO_EXT_SMI#
<18> SIO_RCIN#
PCH_PCIE_WAKE#
PCIE_WAKE#
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
BEEP
SIO_SLP_S5#
ACAV_IN_NB
DOCK_PWR_SW#
Q45
SSM3K7002FU_SC70-3~D
<16> PCH_PCIE_WAKE#
<28,34,35> PCIE_WAKE#
<41> BC_CLK_ECE1117
<41> BC_DAT_ECE1117
<41> BC_INT#_ECE1117
<29> BEEP
<16> SIO_SLP_S5#
<39,53,55> ACAV_IN_NB
GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3
VSS_RO
1
2
1
2
2
A43
B45
A42
A12
B13
A13
B20
A18
B19
A20
B21
A19
A16
B16
A15
A10
B10
B14
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
A55
A57
B61
B65
A46
GENERAL PURPOSE I/O
BC-LINK
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
BC_CLK_EMC4022
BC_DAT_EMC4022
BC_INT#_EMC4022
<39> BC_CLK_ECE5048
<39> BC_DAT_ECE5048
<39> BC_INT#_ECE5048
<22> BC_CLK_EMC4022
<22> BC_DAT_EMC4022
<22> BC_INT#_EMC4022
JTAG1 CONN@
@SHORT PADS~D
2
1
C735
0.1U_0402_25V6K~D
R836
100_0402_1%~D
@
PCH_ALW_ON
BIA_PWM_EC
<22> DOCK_PWR_SW#
EP
B22
A21
B23
B24
A23
B25
A24
2
@ C733
R819
1U_0402_6.3V6K~D
100K_0402_5%~D
1
2
+1.05V_RUN_VTT
FAN PWM & TACH
<42> PCH_ALW_ON
<23> BIA_PWM_EC
1
1
R824
10K_0402_5%~D
JTAG_RST#
JTAG_RST# citcuit
close to U51.B57
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
C1
1 0.1U_0402_25V6K~D
DOCK_POR_RST#
<38> DOCK_POR_RST#
C
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
GPIO124/GPTP-OUT5/UART_RX
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/HSPI_SCLK
GPIO104/HSPI_MISO
GPIO106/HSPI_MOSI
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
PROCHOT#/PWM4
B54
C736 2
A51
B55
B56
A53
B57
2
1
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
+3.3V_ALW
MISC INTERFACE
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
2
1
C730
10U_0603_6.3V6M~D
EC firmware can configure those un-used SMBUS pins as GPO (Output),
then it's OK to leave these un-used pins No-Connect.
2
1
C732
0.1U_0402_25V6K~D
GPU_SMBDAT
2
2.2K_0402_5%~D
GPU_SMBCLK
2
2.2K_0402_5%~D
A5
B6
A37
B40
A38
B41
A39
B42
B59
A56
2
1
2
PS/2 INTERFACE
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
2
1
C739
0.1U_0402_25V6K~D
1
<15> SML1_SMBDATA
<15> SML1_SMBCLK
<41> CLK_TP_SIO
<41> DAT_TP_SIO
<38> CLK_KBD
<38> DAT_KBD
<38> CLK_MSE
<38> DAT_MSE
<45> PBAT_SMBDAT
<45> PBAT_SMBCLK
2
1
C728
0.1U_0402_25V6K~D
CHARGER_SMBCLK
2
2.2K_0402_5%~D
2
1
C726
0.1U_0402_25V6K~D
1
1
2
1
C731
0.1U_0402_25V6K~D
1
CHARGER_SMBDAT
2
2.2K_0402_5%~D
D
1
C729
0.1U_0402_25V6K~D
R822
2
U51
+RTC_CELL
C727
0.1U_0402_25V6K~D
R829
1
+3.3V_ALW
C725
0.1U_0402_25V6K~D
R828
R815
0_0402_5%~D
1
2 +RTC_CELL_VBAT
C723
0.1U_0402_25V6K~D
R827
+RTC_CELL
AGND
D
PCIE_WAKE#
2
10K_0402_5%~D
BC_DAT_ECE5048
2
100K_0402_5%~D
BC_DAT_ECE1117
1
100K_0402_5%~D
BC_DAT_EMC4022
1
100K_0402_5%~D
PBAT_SMBDAT
2
2.2K_0402_5%~D
PBAT_SMBCLK
2
2.2K_0402_5%~D
LPC_LDRQ#_MEC
1
100K_0402_5%~D
1
R759
1
R814
2
R817
2
R821
1
R818
1
R820
2
@ R823
3
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
MEC5055
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
1
Sheet
40
of
55
5
4
3
2
1
+3.3V_TP
2
2
1
2
3
1
L54 2
1 BLM18AG601SN1D_0603~D
<40> CLK_TP_SIO
L55 2
1 BLM18AG601SN1D_0603~D
2
2
TP_DATA
TP_CLK
1
2
1
1
2
3
4
5
6
7
8
9
10
11
12
<17> BT_DET#
<34> COEX1_BT_ACTIVE
<32> BT_COEX_STATUS2
<32> BT_PRI_STATUS
<43> BT_ACTIVE
<39> BT_RADIO_DIS#
<34> COEX2_WLAN_ACTIVE
2
<17>
<17>
USBP11USBP11+
C758
0.1U_0402_25V6K~D
G1
G2
+3.3V_RUN
R1133
1K_0402_5%~D
1
2 BT_COEX_STATUS2
1
R1134
1K_0402_5%~D
1
2 BT_PRI_STATUS
2
TYCO_2041070-8~D
1
9
10
2
TP_DATA
TP_CLK
R904
10K_0402_5%~D
2
+3.3V_TP
@R1162
@
R1162
0_0603_5%~D
1
2
1
C756
0.1U_0402_25V6K~D
+3.3V_TP
R1161
0_0603_5%~D
1
2
C753
33P_0402_50V8J~D
1
2
+3.3V_RUN
1
2
@ C754
100P_0402_50V8J~D
+3.3V_ALW
+5V_RUN
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
GND
ACES_50228-0127N-001
JTP1 CONN@
1
2
3
4
5
6
7
8
PS2_CLK_TS
PS2_DAT_TS
+3.3V_ALW
D
JBT1 CONN@
10P_0402_50V8J~D
C749
2
1
10P_0402_50V8J~D
C750
1
+3.3V_RUN
C748
0.1U_0402_16V4Z~D
C751
10P_0402_50V8J~D
Place close to JTP1
BlueTooth
Touch Pad
<40> DAT_TP_SIO
C752
10P_0402_50V8J~D
1
D
D37
PESD5V0U2BT_SOT23-3~D
2
C755
0.1U_0402_25V6K~D
R902
4.7K_0402_5%~D
1
R903
4.7K_0402_5%~D
TP_CLK
TP_DATA
1
+3.3V_TP
Link Done
Link Done
C
C
Place close to JKB1
Power Switch for debug
KB Conn. Pitch=1.0mm
JKB1 CONN@
<18>
KB_DET#
PS2_CLK_TS
PS2_DAT_TS
KB_DET#
+3.3V_ALW
+5V_RUN
<40> BC_INT#_ECE1117
<40> BC_DAT_ECE1117
<40> BC_CLK_ECE1117
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
1
<30,40> POWER_SW#_MB
1
2
2
1
@ C759
100P_0402_50V8J~D
2
@ PWRSW1
@SHORT PADS~D
Place on Bottom
GND
GND
TYCO_1-2041084-0~D
Link Done
B
B
+3.3V_ALW
R1622
10K_0402_5%~D
1
2
+3.3V_ALW
2
VCC
RESET#
3
RSMRST#
PCH_RSMRST#
5
1
2
B
A
2
2
0.1U_0402_25V6K~D
U7
O
GND
3
C289
0.01U_0402_16V7K~D
A
1
EC SIDE
<40> PCH_RSMRST#
PCH_RSMRST#_Q
2
0_0402_5%~D
P
U9
1
1
C288
1
@ R1623
G
+5V_ALW
4
PCH_RSMRST#_Q <14,16>
TC7SH08FU_SSOP5~D
A
RT9818A-46GU3_SC70-3~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Touch PAD/Int KB/BT
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
41
of
56
3
2
1
+1.5V_RUN Source
1
4
1
3
2
1
2
@ R919
20K_0402_5%~D
2
1
C770
4700P_0402_25V7K~D
A_ON_3.3V#
D
3
2
G
S
5
2
0_0402_5%~D
6
7
+3.3V_ALW
C1198
1U_0603_10V7K~D
1
VBIAS
1
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
12
11
10
9
8
G
@ C1196
1
2
2
270P_0402_50V7K~D
C1197
1
2
1
R910
20K_0402_5%~D
2
ON1
1
14
13
270P_0402_50V7K~D
+3.3V_RUN Source
+3.3V_RUN
15
TPS22966DPUR_SON14_2X3~D
2
1
2
1
1
S
3
1
@ R747
<27,35,39,48> RUN_ON
1
2
4
VOUT1
VOUT1
C764
0.1U_0402_25V6K~D
1
<11,16,27,35,39,48> SIO_SLP_S3#
3
2
0_0402_5%~D
R916
39_0603_5%~D
Q60
SSM3K7002FU_SC70-3~D
2
2
R1617
1M_0402_5%~D
4
1
1
1
D
1
3
2
G
1
1
R749
VIN1
VIN1
R913
20K_0402_5%~D
B
2
4
1
2
3
2
6
1
1
+5V_RUN Source
U78
1
2
+3.3V_M
+3.3V_M_CHG
2
R931
20K_0402_5%~D
C
+5V_ALW
+3.3V_M
C768
10U_0603_6.3V6M~D
4
A_ENABLE
Q57B
DMN66D0LDW-7_SOT363-6~D
6
2
C761
0.1U_0402_25V6K~D
6
5
2
1
R917
100K_0402_5%~D
1
1
C773
2200P_0402_50V7K~D
Q58
SI3456DDV-T1-GE3_TSOP6~D
+3.3V_ALW2
B
1
2
R1611
470K_0402_5%~D
+3.3V_ALW
+PWR_SRC_S
A_ON_3.3V# 5
+1.05V_RUN
+5V_RUN
C1199
1U_0603_10V7K~D
2
1
Q57A
DMN66D0LDW-7_SOT363-6~D
2
<16,39,49> SIO_SLP_A#
S
C767
4700P_0402_25V7K~D
+3.3V_M Source
R918
100K_0402_5%~D
D
2
G
1
2
1.05V_RUN_ENABLE
Q64
Q53A
DMN66D0LDW-7_SOT363-6~D
2
<39> SUS_ON
R1618
1M_0402_5%~D
5
Q53B
DMN66D0LDW-7_SOT363-6~D
SUS_ON_3.3V#
C
2
R914
20K_0402_5%~D
2
SUS_ENABLE
R915
100K_0402_5%~D
+1.05V_RUN Source
+1.05V_M Q63
SI4164DY-T1-GE3_SO8~D
8
1
7
2
R930
6
3
100K_0402_5%~D
5
S
3
1
G
2
1
C765
10U_0603_6.3V6M~D
4
C771
4700P_0402_25V7K~D
C772
10U_0603_6.3V6M~D
6
5
2
1
2
+PWR_SRC_S
D
1
Q54
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS
D
2
1
2
R921
20K_0402_5%~D
1
4
2
0_0402_5%~D
1
2
0_0402_5%~D
1
@ R744
2
1
R735
5
2
RUN_ON_ENABLE#
<40> RUN_ON_ENABLE#
+PWR_SRC_S
+3.3V_ALW2
2
3
2
C762
3300P_0402_50V7K~D
<27,35,39,48> RUN_ON
R911
100K_0402_5%~D
2
1.5V_RUN_ENABLE
<11,16,27,35,39,48> SIO_SLP_S3#
+3.3V_ALW
1
3
1
1
R909
100K_0402_5%~D
6
G
1
2
4
3
2
3
2
6
+3.3V_SUS Source
4
R1610
470K_0402_5%~D
1
R908
20K_0402_5%~D
Q52B
DMN66D0LDW-7_SOT363-6~D
1
2
6
5
2
1
R920
100K_0402_5%~D
Q52A
DMN66D0LDW-7_SOT363-6~D
Q51A
DMN66D0LDW-7_SOT363-6~D
2
<40> PCH_ALW_ON
2
R1619
1M_0402_5%~D
5
Q51B
DMN66D0LDW-7_SOT363-6~D
ALW_ON_3.3V#
1
ALW_ENABLE
<20> ALW_ENABLE
D
S
1
1
R905
100K_0402_5%~D
+3.3V_ALW2
4
Q59
NTGS4141NT1G_TSOP6~D
+1.5V_RUN
C769
10U_0603_6.3V6M~D
6
5
2
1
C760
10U_0603_6.3V6M~D
R907
100K_0402_5%~D
+PWR_SRC_S
D
+3.3V_ALW2
+1.5V_MEM
1
Q49
+3.3V_ALW_PCH
SI3456DDV-T1-GE3_TSOP6~D
SSM3K7002FU_SC70-3~D
+3.3V_ALW
2
+PWR_SRC_S
2
DC/DC Interface
+3.3V_ALW_PCH Source
D
4
S
5
Discharg Circuit
1
2
1
S
2
G
D
3
1
S
D
3
1
3
1
3
2
2
2
2
1
3
1
1
1
1
1
2
1
3
1
2
G
<7,11> RUN_ON_CPU1.5VS3#
S
2
G
Q72
SSM3K7002FU_SC70-3~D
3
R927
22_0603_5%~D
+DDR_CHG
D
Q71
SSM3K7002FU_SC70-3~D
1
+0.75V_DDR_VTT
R926
220_0402_5%~D
+1.5V_CPU_VDDQ_CHG
S
@
@ Q70
SSM3K7002FU_SC70-3~D
S
2
G
+1.05V_RUN_CHG
2
G
D
Q69
SSM3K7002FU_SC70-3~D
S
D
+1.5V_CPU_VDDQ
@ R925
39_0402_5%~D
+3.3V_RUN_CHG
2
G
+1.05V_RUN
@ R929
39_0603_5%~D
@ R924
1K_0402_1%~D
@ Q68
SSM3K7002FU_SC70-3~D
3
+3.3V_RUN
+1.5V_RUN_CHG
RUN_ON_ENABLE#
D
@ Q67
SSM3K7002FU_SC70-3~D
S
+5V_RUN_CHG
D
ALW_ON_3.3V# 2
G
@ Q66
SSM3K7002FU_SC70-3~D
S
@ Q65
SSM3K7002FU_SC70-3~D
D
2
G
+1.5V_RUN
@ R923
1K_0402_1%~D
+3.3V_ALWPCH_CHG
+3.3V_SUS_CHG
A
@ R928
@R928
1K_0402_1%~D
2
2
@ R922
1K_0402_1%~D
SUS_ON_3.3V#
+5V_RUN
1
+3.3V_ALW_PCH
1
+3.3V_SUS
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
POWER CONTROL
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
42
of
56
5
4
3
2
1
HDD LED solution for White LED
Battery LED
+3.3V_ALW
Q83B
1
+5V_ALW
<39> BAT2_LED#
3
2
Q74B
DMN66D0LDW-7_SOT363-6~D
4
3
1
BAT2_LED#_Q
R949
4.7K_0402_5%~D
1
2
BATT_WHITE
BATT_YELLOW
MASK_BASE_LEDS#
<30>
<30>
Q74A
DMN66D0LDW-7_SOT363-6~D
1
6 2
D59
<14> SATA_ACT#
5
R932
10K_0402_5%~D
D
DMN66D0LDW-7_SOT363-6~D
4
3
2
Q75
PDTA114EU_SC70-3~D
2
5
RB751S40T1_SOD523-2~D
R958
4.7K_0402_5%~D
2
D
BATT_WHITE_LED
<23>
1
<39> MASK_SATA_LED#
1
D62
1
<39> LED_SATA_DIAG_OUT#
1
R934
MASK_BASE_LEDS#
2
2
4.7K_0402_5%~D
BATT_YELLOW_LED
SATA_LED
RB751S40T1_SOD523-2~D
Q83A
DMN66D0LDW-7_SOT363-6~D
1
6
<39> BAT1_LED#
<23>
3
2
PANEL_HDD_LED
BAT1_LED#_Q
1
R951
330_0402_5%~D
2
1
R959
330_0402_5%~D
2
MASK_BASE_LEDS#
Q80A
DMN66D0LDW-7_SOT363-6~D
1
6 2
Q81
PDTA114EU_SC70-3~D
1
2
<23>
<30>
1
R938
SYS_LED_MASK#
2
4.7K_0402_5%~D
Breath LED
+5V_ALW
WLAN LED solution for White LED
+3.3V_ALW
1
Q84A
DMN66D0LDW-7_SOT363-6~D
1
6
<38,39> BREATH_LED#
+5V_ALW
LED1
BREATH_LED#_Q
2
2
BREATH_WHITE_LED_SNIFF
1
R957
2
1K_0402_1%~D
C
3
2
R937
100K_0402_5%~D
Place LED1 close to SW1
MASK_BASE_LEDS#
Q78A
DMN66D0LDW-7_SOT363-6~D
1
6
2
Q79
PDTA114EU_SC70-3~D
2
<34,39> WIRELESS_LED#
1
LTW-193ZDS5_WHITE~D
C
R955
4.7K_0402_5%~D
2
BREATH_WHITE_LED
<23>
3
1
MASK_BASE_LEDS#
1
Q78B
DMN66D0LDW-7_SOT363-6~D
5
4
<41> BT_ACTIVE
1
1
R939
2
4.7K_0402_5%~D
WLAN_LED
<30>
2
R950
100K_0402_5%~D
B
B
LED Circuit Control Table
SYS_LED_MASK#
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
LID_CL#
0
1
1
X
0
1
+3.3V_ALW
<39> SYS_LED_MASK#
@ FD1
1
<30,39> LID_CL#
2
B
O
A
GND
4
TC7SH08FU_SSOP5~D
@ H13
H_2P6
A
@ FD3
1
FIDUCIAL MARK~D
@ H15
H_2P8
@ H16
H_3P4
@ H17
H_2P3
@ H18
H_3P4
@ H19
H_2P3
@ H20
H_2P8
@ H21
H_2P8
@ H22
H_2P0X2P5
@ H24
H_2P8
@ H25
H_2P8
@ H26
H_2P8
DELL CONFIDENTIAL/PROPRIETARY
@ H27
H_2P8
Compal Electronics, Inc.
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
1
1
1
1
1
1
1
1
1
1
1
@ FD4
1
FIDUCIAL MARK~D
1
MASK_BASE_LEDS#
1
@ H12
H_2P6
1
@ H11
H_2P8
1
@ H10
H_2P8
1
@ H9
H_2P8
1
@ H7
CLIP_C5
1
@ H6
CLIP_C5
1
@ H5
H_2P8
1
1
FIDUCIAL MARK~D
@ H4
H_2P0
1
@ H3
H_2P8
@ FD2
1
1
LID_CL#
3
LVDS standoff
FIDUCIAL MARK~D
A
SYS_LED_MASK#
CLIP1
EMI_CLIP
U58
G
Fiducial Mark
EMI CLIP
0.1U_0402_25V6K~D
2
P
5
C778
1
3
2
Title
PAD and Standoff
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
43
of
56
5
4
3
2
1
TR1
D
D
1:1
3
TDCT1
TX1+
TXCT2
21
T1/B
TX2+
20
TX2-
19
NB_LAN_TX1-
TD2-
<31> LAN_ACTLED_YEL#
T1/A
7
1:1
T1/B
TD3+
18
TDCT3
T1/A
TXCT3
16
1
2
TDCT4
TD4+
1:1
TXCT4
15
TX4+
14
T1/B
Z2808
NB_LAN_TX3+
TD4-
13
TX4-
NB_LAN_TX3-
T1/A
350UH_H5120DNL~D
1 75_0402_1%~D
<31> LED_10_GRN#
12
R1089 1
2 150_0402_5%~D
9
Yellow LED+
LAN_ACTLED_YEL#_R 10
Yellow LED-
NB_LAN_TX3-
8
PR4-
NB_LAN_TX3+
7
PR4+
NB_LAN_TX1-
6
PR2-
NB_LAN_TX2-
5
PR3-
NB_LAN_TX2+
4
PR3+
NB_LAN_TX1+
3
PR2+
NB_LAN_TX0-
2
PR1-
NB_LAN_TX0+
1
PR1+
Z2806
1 75_0402_1%~D
<31> SW _LAN_TX3-
17
2
2
10
11
TX3-
R1111
1
C39
0.47U_0603_10V7K~D
2
C38
0.47U_0603_10V7K~D
<31> SW _LAN_TX3+
1
2
NB_LAN_TX2-
1 75_0402_1%~D
+TRM_CT4
9
TD3-
2
+TRM_CT3
8
NB_LAN_TX2+
R1112
<31> SW _LAN_TX2-
1
JLOM1 CONN@
6
TX3+
C
2
Z2807
NB_LAN_TX1+
1 75_0402_1%~D
<31> SW _LAN_TX2+
1:1
TDCT2
TD2+
1
Z2805
2
<31> SW _LAN_TX1-
2
4
5
23
22
2
2
1
C37
0.47U_0603_10V7K~D
1
C36
0.47U_0603_10V7K~D
<31> SW _LAN_TX1+
NB_LAN_TX0-
TX1TXCT1
R1113
+TRM_CT2
T1/A
NB_LAN_TX0+
R1114
+TRM_CT1
24
470P_0402_50V7K~D
C1167
TD1-
+3.3V_LAN
T1/B
0.1U_0402_10V7K~D
C1168
<31> SW _LAN_TX0-
2
TD1+
1U_0603_10V4Z~D
C1169
<31> SW _LAN_TX0+
1
<31> LED_100_ORG#
R1091
R1090
150_0402_5%~D
1
2
1
2 150_0402_5%~D
C
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
GND
14
GND
15
TYCO_2041341-1~D
Link Done
B
B
GND
CHASSIS
C1104
1
2 GND_CHASSIS
1000P_1808_3KV7K~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
RJ45
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.3
LA-7741
Sheet
1
44
of
56
5
4
3
2
1
+COINCELL
@ PD3
PESD24VS2UT_SOT23-3~D
GND
GND
BAY_SMBCLK
BAY_SMBDAT
2
2
2
1
MODULE_BATT_PRES#
1
2
1 G
2 G
3
4
D
TYCO_2-1775293-2~D
+RTC_CELL
<39,55>
PD1
7
8
RB715FGT106_UMD3
ESD Diodes
3
2
PJP43
1
2
PBATT+
PR2
PAD-OPEN 4x4m
1
100K_0402_5%~D
2
PC2
0.1U_0603_25V7K~D
PR3
100_0402_5%~D
1
2
+3.3V_ALW
2
PR4
100_0402_5%~D
1
2
Move to power schematic
PL1
FBMJ4516HS720NT_2P~D
1
2
PBATT+_C
Z4304
Z4305
Z4306
PC1
1U_0603_10V4Z~D
2
1
1
3
2
@ PD7
PESD24VS2UT_SOT23-3~D
PBATT1
9
8
7
6
5
4
3
2
1
1
PL20
FBMJ4516HS720NT_2P~D
1
2
@ PD6
PESD24VS2UT_SOT23-3~D
GND
PC3
2200P_0402_50V7K~D
2
1
JRTC1
+COINCELL
<28,40>
<28,40>
SUYIN_150010GR006M500ZR
GND
GND
7
6
5
4
3
2
1
PR108
100K_0402_5%~D
PAD-OPEN 2x2m~D
3
PR105
100_0402_5%~D
1
2
Link Done
1
Z5304
Z5305
Z5306
PR77
100_0402_5%~D
1
2
MPBATT+
2
1
2
3
4
5
6
PC136
0.1U_0603_25V7K~D
PR106
100_0402_5%~D
1
2
1
1
PC141
2200P_0402_50V7K~D
2
1
1
2
3
4
5
6
2
1
MBATT+_C
PBATT2
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
PJP51
COIN RTC Battery
Z4012
2nd Battery Connector
D
+3.3V_ALW
3
2
3
2
PL19
FBMJ4516HS720NT_2P~D
1
2
1
1
1
ESD Diodes
@ PD2
PESD24VS2UT_SOT23-3~D
PR5
100_0402_5%~D
1
2
PBAT_SMBCLK
PBAT_SMBDAT
<40>
<40>
PBAT_PRES#
<39,55>
SUYIN_200277MR009F515ZR~D
C
C
GND
+3.3V_ALW
PU1
2
@ PR7
1
Primary Battery Connector
2
PR8
2.2K_0402_5%~D
0_0402_5%~D
1
<38> DOCK_PSID
PQ2
FDV301N_NL_SOT23-3~D
1
1
IN
GND
V+
6
GPIO_PSID_SELECT
5
+5V_ALW
4
PS_ID
1
NB_PSID_TS5A63157
3
PQ3
MMST3904-7-F_SOT323~D
E
2
3
NC
COM
<39>
<40>
TS5A63157DCKR_SC70-6~D
+5V_ALW
C
2
B
PR12
15K_0402_1%~D
1
2
B
3
2
G
PR10
100K_0402_1%~D
1
2
1
NO
PR11
10K_0402_1%~D
D
PL2
2
1
BLM18BD102SN1D_0603~D
S
2
PR9
33_0402_5%~D
1
2
PR13
1
@
2
PSID_DISABLE#
<39>
10K_0402_5%~D
B
DC_IN+ Source
+DC_IN
+PWR_SRC_S
+PWR_SRC
1
2
2
PC13
0.1U_0603_25V7K~D
A
1VSB_N_003
PR901
0_0402_5%
1
2VSB_N_002
1
+3.3V_ALW
D
3
S
1
2
2
1
1
PQ902
TP0610K-T1-E3_SOT23-3
PC903
0.1U_0603_25V7K
PR902
22K_0402_1%
1
2
2
1
2
PC11
10U_1206_25V6M~D
PR16
100K_0402_5%~D
2
1
PC9
0.1U_0603_25V7K~D
2
1
2
PR18
10K_0402_5%~D
PC8
0.1U_0603_25V7K~D
2
1
SOFT_START_GC
PC7
0.1U_0603_25V7K~D
2
1
PR15
2
1M_0402_5%~D
1
PC901
0.1U_0402_16V7K
@
PL4
FBMJ4516HS720NT_2P~D
1
2
MOLEX_87438-0743~D
PC6
0.022U_0805_50V7K~D
1
2
PD10
2
<55>
PR19
1M_0402_5%~D
2
1
-DCIN_JACK
4.7K_0805_5%~D
+DCIN_JACK
@
@ PR17
2
1
NB_PSID
PC12
0.1U_0603_25V7K~D
2
1
1
2
3
4
5
6
7
1
2
3
4
5
6
7
PC10
0.1U_0603_25V7K~D
2
1
1
PJPDC1
VZ0603M260APT_0603
Link Done
PC902
0.22U_0603_25V7K
3
1
+DC_IN
PR903
2
1
100K_0402_1%
PL3
FBMJ4516HS720NT_2P~D
1
2
+DC_IN_SS
PQ4
FDS6679AZ_SO8~D
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
D
VSB_N_001
PQ901
SSM3K7002FU_SC70-3
2
G
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+DCIN
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
45
of
56
A
B
C
D
E
+5V_ALWP/ +3.3V_ALWP
3.3VALWP +/- 5%
TDC=5.45A
Peak Current=7.786A
OCP min=10.122A
L/S RDS(on) 14.2m ohm(typ),17.5m ohm(max)
FSW=375KHz
Delta_Iin=1.246A
Delta_Io=3.3231A
Charlie_note :
5VALWP +/- 5%
TDC=8.41A
Peak Current=12.012A
OCP min=15.62A
L/S RDS(on) 14.2m ohm(typ),17.5m ohm(max)
FSW=300KHz
Delta_Iin=1.64A
Delta_Io=3.756A
SKIPSEL Connect to REF : DEM Mode
@DEM VFBx=2.0V
2VREF_6182
1
TONSEL
Frequency Selectable Input for VOUT1(+5v)/VOUT2(+3.3v)
respectively.
300kHz/375kHz : Connect to REF
1
2
PC36
1U_0603_16V6K
1
+PWR_SRC
PJP5
1
PR37
13.7K_0402_1%
1
2
2
1
PR36
30.9K_0402_1%
2
PAD-OPEN 4x4m
+DC1_PWR_SRC
PR43
20K_0402_1%
1
2
+3.3V_RTC_LDO
FB_3V
FB_5V 1
PR42
20K_0402_1%
2
+DC1_PWR_SRC
@ PL24
2
3
LGATE2
LGATE1
19
LG_5V
3
D
S
1
PJP6
1
2
100K_0402_1%
+5V_ALWP
+5V_ALW2
2
+5V_ALW(5A,180mils ,Via NO.= 9)
PAD-OPEN 4x4m
PQ105
4
Compal Secret Data
Security Classification
@
2007/08/02
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
1
PDTC115EU_SOT323-3
PC119
1U_0603_10V6K
2
1
<22> THERM_STP#
2
PAD-OPEN 4x4m
PJP74
2
3
4
PR151
0_0402_5%
1
2
PR40
2
PC33
1
+DC1_PWR_SRC
PR150
PR147
2K_0402_1%~D
1
2
2
3
ALW_PWRGD_3V_5V <40>
PQ70A
2N7002DW-T/R7_SOT363-6~D
2
1
ALWON
+
2
PR20
100K_0402_1%
PC27
0.1U_0603_25V7K
1
<40>
SNUB_5V
S
1
2
ENTRIP1
@
1
Max: 100uA
6
3
10U_0805_25V6K
+3.3V_ALW
PC26
4.7U_0805_10V6K
2VREF_6182
4
10U_0805_25V6K
PC20
2
1
PQ7
FDMS7692 1N POWER56-8
1
2
PC19
1
PAD-OPEN 4x4m
ENTRIP2
G
Typ: 175mA
MMSZ5229BS_SOD323-2
+5V_ALWP
2
2
1
499K_0402_1%~D
1U_0603_10V6K
2
@
2
1
1
PR46
PR47
+PWR_SRC
5
@
2
RT8205LZQW(2) WQFN 24P PWM
+5V_ALW2
+3.3V_ALW
(4A,120mils ,Via NO.= 6)
PQ70B
PC18
2
1
NC
18
VIN
VREG5
17
16
14
13
PL7
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
1
2
PC35
220U_D_6.3VM_R25M
LX_5V
1
20
4.7_1206_5%
PHASE1
680P_0603_50V7K
PHASE2
2
2.2_0603_5%
2
1
UG_5V
G
3
22
21
PQ5
FDS8878_G 1N SO8
D
BOOT1
UGATE1
PR38
PC37
0.22U_0603_25V7K~D
BST1_5V 1
2
IRF8707GTRPBF_SO8
PD37
2N7002DW-T/R7_SOT363-6~D
2200P_0402_50V7K
1
2
1
3
4
5
2
FB1
REF
ENTRIP1
2
UGATE2
BOOT2
GND
12
23
BST_5V 1
EN
LG_3V
24
@
1
1
11
VO1
PGOOD
1
+3.3V_ALWP
9
LX_3V
2
2
PAD-OPEN 4x4m
PJP10
VREG3
UG_3V 10
300K_0402_1%
@
PJP9
VO2
8
PQ8
680P_0603_50V7K
2
BST_3V
7
4
1
2
3
1
PR39
PC34
1 SNUB_3V
2
@
4.7_1206_5%
+
2
PC40
220U_D_6.3VM_R25M
1
8
7
6
5
PL8
2.2UH_ETQP3W2R2WFN_8.5A_20%
1
2
+3.3V_ALWP
1
PC38
0.22U_0603_25V7K~D
BST1_3V 1 PR41 2
1
2
2.2_0603_5%
15
Typ: 175mA
1
2
3
2
TONSEL
P PAD
FB2
1
25
2
4
6
PU2
PC28
10U_0805_6.3V6M
ENTRIP2
PQ6
AON7408L_DFN8-5
PR34
232K_0402_1%~D
ENTRIP1
1
2
2 ENTRIP2
PC17
PR33
140K_0402_1%
1
SKIPSEL
5
10U_0805_25V6K
10U_0805_25V6K
PC24
2
1
PC23
2
1
1
PC21
2
2200P_0402_50V7K
PC22
0.1U_0402_25V6
2
1
@
PR27
0_0402_5%
1
2
0.1U_0402_25V6
PC16
2
1
+3.3V_ALW2
1
2
HCB2012KF-121T50_0805
B
C
D
Title
Compal Electronics, Inc.
+5V/+3.3V
Size Document Number
Custom
Date:
Rev
0.1
LA-7741
Thursday, June 23, 2011
Sheet
E
46
of
56
5
4
3
1.5Volt +/- 5%
TDC=7.18A
Peak Current=10.25A
OCP min=13.33A
L/S RDS(on) 3.8m ohm(typ),4.8m ohm(max)
FSW=253KHz for RTON=1M ohm, spec. On-Time =303.947ns
Delta_Iin=1.458A
Delta_Io=5.4728A
+PWR_SRC
0.75Volt +/- 5%
TDC=0.525A
Peak Current=0.75A
OCP min=0.975A
D
PJP404
PJP204
1.5V_B+
VLDOIN_1.5V
PR482
1
2
2.2_0603_5%~D
BOOT_1.5V
+5V_ALW
GND
3
VTTREF
4
VDDQ
5
PC418
2
1
+V_DDR_REF
VDDQ_1.5V
C
+1.5V_MEN_P
FB
PC425
0.033U_0402_16V7~D
6
S3
PC417
2
1
2
10U_0805_6.3V6M~D
VTT
19
20
17
18
BOOT
VLDOIN
VDD
20110602 modify item
1. delete PU16.4 another net name VTTREF_1.5V
, only left +V_DDR_REF
PR485
100K_0402_1%~D
1.5V_SUS_PW RGD
+1.5V_MEN_P_FB
@ PR904
2
1
PR905
0_0402_5%~D
<39> 0.75V_DDR_VTT_ON
0.1U_0603_25V7K
1
S3_1.5V
Note: S3 - sleep ; S5 - power off
@ PC904
1
@ PC426
0.1U_0402_16V7K~D
+1.5V_MEN_P
0_0402_5%~D
1
2
1M_0402_1%~D
2
S5_1.5V
2
1
2
0_0402_5%~D
PR486
2
2
B
11
VTTSNS
1
<40> DDR_ON
VDDP
21
1
RT8207MZQW _W QFN20_3X3
7
SIR466DP-T1-GE3_POW ERPAK8-5
PR487
+V_DDR_REF
off
on
on
12
1U_0603_10V6K~D
1.5V_B+
+0.75V_P
off
off
on
CS
PC424
<40> 1.5V_SUS_PW RGD
Level
L
L
H
13
S5
2
+3.3V_ALW
PQ68
1
2
3
1
PGND
8
4
1SNUB_1.5V2
@ PC231
0.1U_0603_25V7K~D
+5V_ALW
VDD_1.5V
1
@ PR220
4.7_1206_5%
2
1U_0603_10V6K~D
PR484
5.1_0603_5%~D
1
1
+
2
PC419
14
PAD
VTTGND
2
1
+
PC423
330U_SX_2VY~R9M
@ PC422
330U_SX_2VY~R9M
C
5
1
2
1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D
LGATE
PGOOD
1
2
3
PR483
5.1K_0402_1%~D
1
2 CS_1.5V
15
10
4
UGATE
PU16
TON
DL_1.5V
10U_0805_6.3V6M~D
+0.75V_P
SW _1.5V
PL27
+1.5V_MEN_P
+1.5V_MEN_P
1
DH_1.5V
PQ67
SIR472DP-T1-GE3_POW ERPAK8-5~D
2
PAD-OPEN1x1m
0.22U_0603_16V7K~D
PC416
1
2
5
PC415
2
1
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
PC414
2
1
4.7U_0805_25V6K~D
PC413
2
1
PC412
2
1
4.7U_0805_25V6K~D
PAD-OPEN 4x4m
9
2
16
1
Mode
S5
S3
S0
1
+1.5V_MEN_P/ +0.75V_P
PHASE
D
2
PR489
0_0402_5%~D
1
2
B
PJP405
2
2
1
1
JUMP_43X118
PJP406
+1.5V_MEN_P
2
2
1
1
+1.5V_MEM
PJP407
+0.75V_P
JUMP_43X118
1
2
+0.75V_DDR_VTT
PAD-OPEN 3x3m
(2A,80mils ,Via NO.= 4)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.5V_MEN/+0.75V_DDR_VTT
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
47
of
56
A
B
C
D
+1.8V_RUNP
1.8Volt +/-5%
TDC=0.81A
Peak Current=1.157A
OCP min=1.5A
1
FSW=1MHz
Delta_Iin=0.407A
Delta_Io=0.8182A
+3.3V_RUN
1.8V_RUN_PW RGD
@
1
2
1
2
1
1
PC407
2
2
PC306
47P_0402_50V8J~D
SYN470DBC_DFN10_3X3
@ PC410
0.1U_0402_10V7K
PC411
2
1
0_0402_5%
@ PR479
47K_0402_5%
1
2
2
SIO_SLP_S3#
PR481
2
<11,16,27,35,39,42>
1
PR480
10K_0402_1%
PC409
22U_0805_6.3VAM
1
0_0402_5%
PR477
20K_0402_1%
22P_0402_50V8J
@
1
1
PR476
1.8VSP_FB
PC408
22U_0805_6.3VAM
EN_1.8VSP
6
1
2
FB
+1.8V_RUNP
2
2
1
NC
TP
<27,35,39,42> RUN_ON
11
2
7
EN
3
2
SVIN
LX
4.7_1206_5%
8
5
@ PR478
PL26
1UH_PH041H-1R0MS_3.8A_20%
1
2
1.8VSP_LX
SNUB_1.8VSP
PVIN
2
680P_0603_50V7K
9
LX
NC
PC406
22U_0805_6.3VAM
PVIN
2
1
HCB1608KF-121T30_0603
10
1
1.8VSP_VIN
2
4
PU15
PL25
1
PG
+3.3V_ALW
<39>
2
PR475
2
1
10K_0402_5%~D
1
VFB=0.6V
Vo=VFB*(1+PR477/PR480)=0.6*(1+20K/10K)=1.8V
PJP403
+1.8V_RUNP
1
2
+1.8V_RUN
PAD-OPEN 3x3m
3
3
4
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
+1.8V_RUN
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
D
48
of
56
5
4
3
2
1
+1.05V_MP
PJP400
+V1.05SP_B+
2
2
1
1
+PWR_SRC
PR401
2.2_0603_5%
1
2
2
TRIP
EN_+V1.05SP
3
EN
FB_+V1.05SP
4
VFB
RF_+V1.05SP
5
RF
DRVH
UG_+V1.05SP
SW
8
SW _+V1.05SP
V5IN
7
V5IN_+V1.05SP
DRVL
6
LG_+V1.05SP
11
+5V_ALW
PC403
2
1
PC400
2
1
+1.05V_MP
PQ401
AO4710_SO8
PC405
1U_0603_6.3V6M
@ PR404
4.7_1206_5%
4
2
TPS51212DSCR_SON10_3X3
PL400
3.3UH_PCMB064T-3R3MS_7A_20%
1
2
5
6
7
8
BST_+V1.05SP
9
2
@ PC431
0.1U_0402_16V7K
10
TP
1
S0 mode be high level
VBST
1
1
2
0_0402_5%
<16,39,42> SIO_SLP_A#
PGOOD
2
PR403
PU17
PC430
220U_D2_4VM
1
1
<40> 1.05V_A_PW RGD
PR402
66.5K_0402_1%~D
TRIP_+V1.05SP
1
2
PC404
0.1U_0603_25V7K
1
2
4
3
2
1
2
100K_0402_1%~D
1
+
2
C
PR405
470K_0402_1%
1
3
2
1
1
C
4.7U_0805_25V6K
1
AO4466_SO8
PR400
D
4.7U_0805_25V6K
PQ400
PC402
2
1
PC401
2
1
5
6
7
8
+3.3V_ALW
0.1U_0402_25V6
D
2200P_0402_50V7K
JUMP_43X118
@ PC432
2
2
1000P_0603_50V7K
2
PR406
1
@
PC433
0.1U_0603_25V7K
+1.05Volt +/- 5%
TDC=2.38A
Peak Current=3.396A
OCP min=4.42A
PJP401
PR407
10K_0402_1%
2
2
1
1
JUMP_43X118
1
2
1
2
4.99K_0402_1%
+1.05V_MP
PJP402
2
2
1
1
+1.05V_M
L/S RDS(on) 11.7m ohm(typ),14.12m ohm(max)
FSW=290KHz
Delta_Iin=0.234A
Delta_Io=1.038A
JUMP_43X118
B
A
B
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.05V_M
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
49
of
56
5
4
3
2
1
+1.05VTTP
PJP23
PC108
+1.05VTT_PWR_SRC
VOUT
IMON
11 +1.05VTT_MODE
10
1
PGND
9
SW
2
PC113
0.1U_0603_25V7K~D
2
1
PC112
0.1U_0603_25V7K~D
2
1
PC301
10U_0805_25V6K
2
1
PC300
10U_0805_25V6K
2
1
CPU_VTT_ON <39>
GNDA_1.05VTT
SN1003055RUWR_QFN17_3P5X3P5~D
+1.05VTTP
GNDA_1.05VTT
PL10
+1.05VTT_VX
2
1
PC131
6800P_0402_25V7K~D
2
1
PC127
22U_0805_6.3V6M
2
1
PC128
0.1U_0603_25V7K~D
2
1
2
C
1
PC126
22U_0805_6.3V6M
2
1
@ PR511
7.68K_0805_1%~D
PC125
22U_0805_6.3V6M
2
1
1
PR100
2
GNDA_1.05VTT
PR128
PC124
47U_0805_4V6M~D
2
1
PC513
0.1U_0603_25V7K~D
SNUB_1.05VTT
PC123
22U_0805_6.3V6M
2
1
+3.3V_RUN
@
PC130
22U_0805_6.3V6M
2
1
1
0.42UH_ETQP4LR42AFM_17A_20%~D
2
GNDA_1.05VTT
D
0_0402_5%~D
PC122
22U_0805_6.3V6M
2
1
8
7
PGND
1
PC118
0.01U_0402_25V7K~D
PC111
10U_0805_25V6K
2
1
1
MODE
SS
@ PR91
1
@ PR92
2
1
22.1K_0402_1%~D
PC121
47U_0805_4V6M~D
2
1
6
13 +1.05VTT_EN
12 +1.05VTT_FSET
PC129
22U_0805_6.3V6M
2
1
5
+1.05VTT_SS
EN
VFB VFB=0.6V FSET
1.05Volt +/-5%
TDC=4.49A
Peak Current=6.411A
OCP min=8.334A
FSW=1MHz
Delta_Iin=0.804A
Delta_Io=1.975A
+5V_ALW
PR89
1
2
3.3_0603_1%~D
PC120
22U_0805_6.3V6M
2
1
+1.05VTT_SENSE
COMP
14 +1.05VTT_PWRGD
2
4
15 +1.05VTT_BST
2
1
PR130
20K_0402_0.5%~D
2
3
+1.05VTT_VFB
PGOOD
+1.05VTT_VX
PR96
2
1
3.01K_0402_1%
2
+1.05VTT_SENSE
PR93 2K_0402_0.5%~D
2
1
PC117
PR94
2
1
1
2
0_0402_5%~D
1800P_0402_50V7K~D
+1.05VTT_COMP
VBST
GND
PR95
680P_0402_50V7K~D
VCCA
10_0402_5%~D
2
PC116
2
1
0_0402_5%~D
1
C
2
16
1
100P_0402_50V8J~D
PR90
2
1
5.6K_0402_5%~D
2
PAD-OPEN 4x4m
PC114
0.1U_0603_25V7K
VIN
VIN
PU7
17
+1.05VTT_VX
+3.3V_ALW
GNDA_1.05VTT
PC110
10U_0805_25V6K
2
1
1U_0402_6.3V6K~D
PC115
2
1
1
PC109
10U_0805_25V6K
2
1
2
D
1
1
10K_0402_5%
D
PQ17
PR119
2
1
0_0402_5%~D
2
G
S
VCCP_PWRCTRL
<10>
From GPIO
+1.05VTT_SENSE
2
VCCP_PWRCTRL = "High" ,
VCCP_PWRCTRL = "Low" ,
@ PR116
1
Vo = 1.05V (SNB)
Vo = 1V (IVB)
PR102
2
VTT_SENSE
<10>
VTT_GND
<10>
0_0402_5%~D
100K_0402_5%
1
@
2
PC183
1
Vth =1~x~2.5v
0.01U_0402_16V7K~D
3
SSM3K7002FU_SC70-3
GNDA_1.05VTT
PR118
1
2
0_0402_5%~D
GNDA_1.05VTT
PR101
2
1
+5V_RUN
9.31K_0402_1%~D
B
+1.05VTT_PWRGD
1
@ PR103
B
2
1.05V_VTTPWRGD
<40,54>
0_0402_5%~D
2
PR104
1
13.3K_0402_1%~D
PJP25
PJP24
1
2
2
PAD-OPEN 43X118
1
PAD-OPEN1x1m
PJP26
+1.05VTTP
1
2
+1.05V_RUN_VTT
GNDA_1.05VTT
PAD-OPEN 43X118
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
ISL95870A +1.05V_RUN_VTT
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
50
of
56
4
3
2
1
+VCC_CORE
PR330
2
2
1
3.09K_0402_1%~D
10K_0402_1%_ERTJ0EG103FA~D
3
9
P3_SW
GND
DL
P3_SW
7
PQ10
SIR818DP-T1-GE3_POWERPAK8-5
4
EP
LGATE3
PR127
165K_0402_1%
1
2
PR135
105K_0402_1%~D
1
2
1
2
PC135
4.7U_0805_25VAK
2
1
PC134
4.7U_0805_25VAK
1
3
2
1
BOST1
PR161
2
1
2.2_0603_5%~D
BT1_1
4
PR170
1_0402_5%~D
PR169
2K_0402_0.5%~D
2
1_1206_5%
PR176
2
1
3.24K_0402_1%~D
2
PC176
2200P_0402_50V7K~D
2
1
0_0402_5%~D
PJP28
1
2
Main
X7629631L88
AON6414AL
AON6704L
2nd
X7629631L89
MDU2657RH
MDU2653RH
1000P_0402_50V7K~D
GNDA_VCC
@ PC178
1
2
PC179
2
1
A
1000P_0402_50V7K~D
0.22U_0402_16V7K~D
+Vcore_CSNA
PAD-OPEN1x1m
GNDA_VCC
@ PC177
1
2
+Vcore_CSPA1
+VCC_CORE
TDC=37.1A
Peak Current=53A
OCP min=69A
Fsw=270KHZ
+VCC_CORE
P1_SW
@ PC175
1500P_0603_50V7K~D
PQ14
SIR818DP-T1-GE3_POWERPAK8-5
@ PR173
PQ9,PQ11,PQ13 PQ10,PQ14,PQ15
2
PL13
0.42UH_ETQP4LR42AFM_17A_20%~D
1
2
+Vcore_POKA
A
1
1
2
2
4
PC174
1
2
0.22U_0603_10V7K~D
2
0_0402_5%~D
2
0_0402_5%~D
2
0_0402_5%~D
PC172
4.7U_0805_25VAK
2
1
PQ13
SIR472DP-T1-GE3_POWERPAK8-5~D
P1_SW
1
PR164
1
PR167
1
PR168
PC155
100U_25V_M_R0.7~D
PC153
4.7U_0805_25VAK
2
1
2
1
PC152
4.7U_0805_25VAK
PC151
2200P_0402_50V7K~D
2
1
PC148
0.1U_0603_25V7K~D
2
1
PC192
4.7U_0805_25VAK
2
1
PC214
4.7U_0805_25VAK
2
1
5
PC154
100U_25V_M_R0.7~D
PR126
107K_0402_1%~D
1
2
B
PC169
0.1U_0603_25V7K~D
2
1
CLK
18
ALERT#
VDIO
VDDB
15
DLB
14
13
POKA
+VCC_PWR_SRC
1
VIDSCLK
+Vcore_CSNA
LGATE1
@ PR171
2
1
<39> IMVP_PWRGD
0.22U_0402_16V7K~D
2
<10>
1
1
<10> VIDALERT_N
PC166
2
1
1000P_0402_50V7K~D
1
@ PR166
0_0402_5%~D
VIDSOUT
@ PC164
1
2
GNDA_VCC
UGATE1
1
130_0402_1%~D
1
130_0402_1%~D
1
54.9_0402_1%~D
1000P_0402_50V7K~D
1
<10>
@ PC162
1
2
2
2
2
+GFX_POKB
2
PR159
2
@ PR160
2
PR162
0.1U_0402_25V6K~D
2
+VCC_CORE
+Vcore_CSPA2
20
1
+1.05V_RUN_VTT
C
PR152
2
1
3.24K_0402_1%~D
21
5
GNDA_VCC
+3.3V_RUN
+
2
PR145
1_0402_5%~D
@ PR148
1_1206_5%
PC161
2200P_0402_50V7K~D
PC276
4.7U_0805_25VAK
2
1
PC173
PC160
2.2U_0603_10V7K~D
23
22
+Vcore_POKA 19
+GFX_DLB
+Vcore_CLK
+GFX_DHB
<52>
+Vcore_VDIO 16
<52>
1
PR165
10K_0402_1%~D
12
BSTB
1+VGFX_FBB
8.45K_0402_1%~D
PC167
1000P_0402_50V7K~D
+GFX_LXB
+Vcore_ALERT# 17
PR157
<52>
2
1
PR144
3
2
1
2
+VCC_GFXCORE
+Vcore_VDD
1
2
2
1
1
2
10_0402_5%~D
PR158
1
2
10_0402_5%~D
11
<52> +GFX_BSTB
GNDA_VCC
PR156
DHB
BSTA1
LXB
POKB
+
2K_0402_0.5%~D
1
DHA1
PC163
1000P_0402_50V7K~D
2
1000P_0402_50V7K~D
<11> VCC_AXG_SENSE
+Vcore_VDD
1
P2_SW
@ PC159
1500P_0603_50V7K~D
PC226
4.7U_0805_25VAK
2
1
CSNB
+VGFX_GNDSB
1
@ PC165
B
24
PQ15
SIR818DP-T1-GE3_POWERPAK8-5
3
2
1
DLA1
PC205
1
2
PR153
1
2
10_0402_5%~D
LGAT2
2
2
CSPB1
1000P_0402_50V7K~D
<11> VSS_AXG_SENSE
25
+
PL12
0.42UH_ETQP4LR42AFM_17A_20%~D
1
2
4
LXA1
10
GNDA_VCC
UGATE2
1
9
<52> +GFX_CSNB
<52> +GFX_CSPB1
26
PR141
PC157
2.2_0603_5%~D
0.22U_0603_10V7K~D
2
1 BT2_1
1
2
MAX17511GTL+T_TQFN40_5X5~D
GNDSB
VDDA
8
43P_0402_50V8J
PR149
1
2
10_0402_5%~D
27
P2_SW
4
1
PC171
4.7U_0805_25VAK
2
1
DLA2
BOST2
PQ11
SIR472DP-T1-GE3_POWERPAK8-5~D
GNDA_VCC
+PWR_SRC
2
PAD-OPEN 4x4m
PC170
2200P_0402_50V7K~D
2
1
FBB
+Vcore_IMAXA
28
PJP27
1
2
LXA2
29
+VCC_PWR_SRC
5
6
+VGFX_GNDSB 7
PC146
0.22U_0402_16V7K~D
2
1
3
2
1
+VGFX_FBB
1000P_0402_50V7K~D
PC145
2
+Vcore_CSNA
5
VRHOT#
DHA2
GNDA_VCC
PR125
1K_0402_5%~D
1
2
2
BSTA2
@
PR134
154K_0402_1%~D
1
2
+Vcore_PWMA
IMAXA
FBA
+GFX_IMAXB
PR133
10K_0402_1%~D
1
2
+Vcore_SR
31
GNDSA
30
PH3
100K_0402_1%_TSM0B104F4251RZ~D
1
2
+Vcore_THERMA
32
PH2
100K_0402_1%_TSM0B104F4251RZ~D
1
2
+VGFX_THERMB
33
DRVPWMA
+Vcore_CSPAAVE
34
SR
+Vcore_CSPA1
35
THERMA
+Vcore_CSNA
36
THERMB
+Vcore_CSPA2
37
CSPAAVE
+Vcore_CSPA3
38
CSPA1
+Vcore_VCC
IMAXB
@ PR146
0_0402_5%~D
PC269
1
2
GNDA_VCC
TON
1000P_0402_50V7K~D
2
GNDA_VCC
1
1
H_PROCHOT#
3
PR140
2
1 +Vcore_FBA 4
9.76K_0402_1%~D
+Vcore_VRHOT# 5
PC158
@ PC144
1
2
@
1
1000P_0402_50V7K~D
2
+1.05V_RUN_VTT
<7,40,53>
1
@ PR143
75_0402_5%~D
1
2
2
1
2
10_0402_5%~D
+VCC_CORE
2
GNDA_VCC
2
@
PR139
1
2
10_0402_5%~D
PC149
1000P_0402_50V7K~D
CSNA
1
2
1
PC150
1000P_0402_50V7K~D
CSPA2
+Vcore_GNDSA
1
2
10_0402_5%~D
@ PR142
TPAD
PU9
PR138
EN
@ PR137
1
2
10_0402_5%~D
<10> VCCSENSE
PR120
2
1
3.24K_0402_1%~D
+Vcore_CSPA3
+GFX_IMAXB
39
+VGFX_TONB
CSPA3
PR132
1
2
100K_0402_5%~D
<10> VSSSENSE
PR114
1_0402_5%~D
@ PR117
1_1206_5%
PC140
2200P_0402_50V7K~D
+Vcore_IMAXA
+Vcore_EN
<39> IMVP_VR_ON
0_0402_5%~D
@ PR131
2
0_0402_5%~D
1
1
40
2.2U_0603_10V7K~D
<14,40> 1.05V_0.8V_PWROK
PR124
5.62K_0402_1%~D
1
2
@ PR129
1
2
VCC
GNDA_VCC
+VCC_PWR_SRC
C
PR123
5.62K_0402_1%~D
1
2
PC143
1
2
41
1
PC142
2
1
2
10_0402_5%~D
2.2U_0603_10V7K~D
PC277
1U_0603_10V6K~D
2
1
@
1
+Vcore_VCC
PR122
D
+VCC_CORE
P3_SW
@ PC139
1500P_0603_50V7K~D
PR113
2K_0402_0.5%~D
4
MAX17491GTA+T_TQFN8_3X3~D
12.7K_0402_1%~D
@ PR121
0_0402_5%~D
1
2 +Vcore_VDD
0.42UH_ETQP4LR42AFM_17A_20%~D
1
2
8
1
LX
PL11
0.22U_0603_10V7K~D
3
2
1
PWM
1
1
P2_SW
DH
1
2
BST
SKIP
2
1
PR111
VDD
2
PH1
6
P1_SW
2
1
12.7K_0402_1%~D
PR112
2
1
12.7K_0402_1%~D
2 PR115 1
6.49K_0402_1%~D
Layout Note:
PC142 close to PIN15
5
1U_0603_10V6K~D
4
PC137
1
2
BT3_1
2
PR110
1
2.2_0603_5%~D
1
1
PU8
2
PR109
PR107
BOST3 2
PC138
2
1
5
0.1U_0402_16V7K~D
2
2
0_0402_5%~D
3
2
1
1
PC133
2200P_0402_50V7K~D
2
1
+5V_ALW
PC278
1
2
D
PC132
0.1U_0603_25V7K~D
2
1
UGATE3
PC147
4.7U_0805_25VAK
2
1
2
0.01U_0402_25V7K~D
20110509 Maxim FAE-Allen reply:There are total 3 pcs
2.2uF capacitor for VCC(PC143), VDDA(PC160)
and VDDB(PC142) pin.
+5V_ALW
5
PQ9
SIR472DP-T1-GE3_POWERPAK8-5~D
PC281
1
Charlie_note :
PC168
4.7U_0805_25VAK
2
1
+VCC_PWR_SRC
PC156
100U_25V_M_R0.7~D
5
GNDA_VCC
Choke DCR=1.55± 7% mΩ
@ PC180
1
2
1000P_0402_50V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Vcore
Size
4
3
2
Rev
0.1
LA-7741
Date:
5
Document Number
Thursday, June 23, 2011
Sheet
1
51
of
56
5
4
3
2
1
+VCC_GFXCORE
D
D
+VGFX_PWR_SRC
C
C
PJP29
1
2
+PWR_SRC
PC197
2
PC204
10U_1206_25VAK~D
2
1
1
2
PC196
10U_1206_25VAK~D
2
1
PQ21
SIR472DP-T1-GE3_POWERPAK8-5~D
0.22U_0603_10V7K~D
1
+
2
PC199
2200P_0402_50V7K~D
2
1
1
PQ26
SIR818DP-T1-GE3_POWERPAK8-5
+
2
PC202
470U_D2_2VM_R4.5M~D
2
+VCC_GFXCORE
1
2
3
2
1
3
2
1
@ PR193
2.2_1206_1%~D
PC203
4700P_0402_25V7K~D
2
1
4
3GP1_Vo
470P_0603_50V8J~D
1
4
<51> +GFX_DLB
GP1_SW 2
@ PC198
PQ25
SIR818DP-T1-GE3_POWERPAK8-5
PC201
5
1
PL15
0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
1
4
<51> +GFX_LXB
470U_D2_2VM_R4.5M~D
GBT1_1 1
PC200
0.1U_0402_10V7K~D
2
1
1
3
2
1
PR189
2.2_0603_5%~D
5
2
<51> +GFX_BSTB
4
3
2
1
4
PC195
10U_1206_25VAK~D
SIR472DP-T1-GE3_POWERPAK8-5~D
<51> +GFX_DHB
PC194
2200P_0402_50V7K~D
2
1
PC193
0.1U_0603_25V7K~D
2
1
5
5
PAD-OPEN 4x4m
PQ24
PR190
1.37K_0402_1%~D
B
1
2
B
PR191
0_0402_5%~D
<51> +GFX_CSPB1
2
PC282
1
2
0.068U_0402_16V7K~D
PC208
1
2
PR192
2
PQ21,PQ24
X7629631L88
AON6414AL
AON6704L
1
PR203
2
2
10K_0402_1%_ERTJ0EG103FA~D
2nd
X7629631L89
MDU2657RH
+VCC_GFXCORE
TDC=23.1A
Peak Current=33A
OCP min=43A
Fsw=330KHZ
@ PR201
2
1
40.2K_0402_1%~D
PQ25,PQ26
PH4
Main
1
0_0402_5%~D
0.33U_0402_10V6K
1
2.21K_0402_1%~D
MDU2653RH
<51> +GFX_CSNB
Choke DCR=0.82± 5% mΩ
GNDA_VCC
PC207
1
2
1000P_0402_50V7K~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
ISL95870A +1.05V_RUN_VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
5
4
3
2
Sheet
1
52
of
56
4
3
@ PD14
2
2
1
@ PL800
1UH_PCMB053T-1R0MS_7A_20%
2
1
ES2AA-13-F
PQ27
SI4835DDY-T1-E3_SO8~D
8
1
7
2
6
3
5
CHAGER_SRC
PJP800
4
1
1
2
3
2
PAD-OPEN 4x4m
4
Adapter Protection Event
+SDC_IN
+PWR_SRC
PR801
0.01_1206_1%~D
PC801
47P_0402_50V8J~D
2
1
+DC_IN_SS
PR510
PR521
PR522
SW
0 Ohm
@
100k
HW
@
0 Ohm
@
2
<55> DC_BLOCK_GC
1
@ PR206
D
1
PC802
0.1U_0603_25V7K~D
2
1
5
@
D
1
0_0402_5%~D
D
2
0_0402_5%~D
PQ801
NTR4502PT1G_SOT23-3~D
2
G
D
3
1
CSS_GC
1
S
PQ803A
NTGD4161PT1G_TSOP6~D
2
G
+DOCK_PWR_BAR
3
5
CSSN_1
1
2
1
100K_0402_1%~D
3
PR812
1
2
DK_CSS_GC
27
C
PC807
2
9
14
1
MAX8731_IINP
8
0.1U_0603_25V7K~D
SCL
SDA
VDDP
NC
UGATE
VICM
PHASE
1
PQ804
2
PC811 1U_0603_10V6K~D
CHG_UGATE
24
23
5
GNDA_CHG
21 MAX8731A_LDO
2
FBO
PR819
4
+VCHGR_B
1
0_0603_5%~D
AON7408L_DFN8-5
2
6
PC809
VDDSMB
3
2
1
10
1
11
PC810
10U_1206_25V6M~D
2
1
1U_0603_10V6K~D
1
ACOK
PC814
10U_1206_25V6M~D
2
1
PR817
PR816
4.7_0603_5%~D
2.2_0603_1%~D
BOOT_D
2
BOOT
25
1
PC813
0.1U_0603_25V7K~D
2
1
BOOT
PC812
2200P_0402_50V7K~D
2
1
ACIN
26
1
ICOUT
2
ICOUT
CSSN
28
CSSP
DCIN
2
1
13
GNDA_CHG
VFB
GND
NC
1
1
12
29
PC825
1
PR826
100_0402_5%~D
16
+VCHGR
TP
2
2
0.01U_0402_25V7K~D
4
0.01U_0402_25V7K~D
ISL88731CHRTZ-T T_QFN28P__5X5
3
2
1
PJP801
2
B
PAD-OPEN1x1m
GNDA_CHG
3
1
2
2
PC823
15 VFB
GNDA_CHG
PC821
1000P_0603_50V7K~D
PR829
4.7_1206_5%~D
2
@ PC832
0.1U_0603_25V7K~D
1
2
GNDA_CHG
PC831
10U_1206_25V6M~D
2
1
@ PR825
8.45K_0402_1%~D
PQ805
17
PC830
10U_1206_25V6M~D
2
1
CSON
19
18
PC829
10U_1206_25V6M~D
2
1
CE
1
7
PC828
0.1U_0603_25V7K~D
2
1
PGND
CSOP
2
3
SI7716ADN-T1-GE3_POWERPAK8-5
MAX8731_REF
2.2K_0402_1%~D
<22> MAX8731_IINP
PR828
0_0402_5%~D
2
1
VREF
PL801
PR823
0.01_1206_1%~D
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
2
1+VCHGR_L 4
1
5
<40> CHARGER_SMBDAT
+VCHGR
CHG_LGATE
20
PR827
10_0402_1%~D
2
1
LGATE
1
EAO
2
4
PR822
2
GNDA_CHG
<40> CHARGER_SMBCLK
EAI
1
5
1
<55>
GNDA_CHG
2
PR818
1
2
0_0402_5%~D
PR814
+5V_ALW
<38>
PR808
1
2
PR807
1
1
2
PU801
+DCIN 22
1
GNDA_CHG
ICREF
2
PC806
0.1U_0805_50V7M~D
2
1
15.8K_0402_1%~D
PC815
0.1U_0402_10V7K~D
2
1
PR810
10K_0402_1%~D
2
1
10K_0402_5%~D
ACAV_IN
0.01U_0402_25V7K~D
GNDA_CHG
DOCK_DCIN_IS-
0_0402_5%~D
2
<22,40,55>
PC805
2
@ PR811
2
1
49.9K_0402_1%~D
PC808
2
1
1
0.1U_0603_25V7K~D
PR815
C
PC804
0.047U_0603_25V7M~D
1
2
1_0805_5%~D
1
2
PC803
0.1U_0603_25V7K~D
1
2
2
4
D
@ PR809
1
<55> +CHGR_DC_IN
2
G
PR813
226K_0402_1%~D
MAX8731_REF
PR850
<38>
PQ803B
NTGD4161PT1G_TSOP6~D
S
PR833
10_0402_5%~D
+SDC_IN
PR804
10K_0402_5%~D
2
1
10_0402_5%~D
CSSP_1
3
PD801
BAT54CW_SOT323~D
DOCK_DCIN_IS+
G
+DC_IN_SS
MAX8731A_LDO
6
2
1
PR813
TI bq24745 = 316K
Intersil ISL88731 = 226K
Maxim = 383K
D
E2 AC_OK=17.7 Volt
S
S
PQ802
NTR4502PT1G_SOT23-3~D
100K_0402_1%~D
<55>
0.1U_0603_25V7K~D
1
2
@ PC800
PR803
@ PC834
1
2
PC833
1
2
0.22U_0603_25V7K~D
B
0.1U_0603_25V7K~D
GNDA_CHG
MAX8731_REF
+DC_IN
PQ38
RHU002N06_SOT323-3~D
2N7002DW-T/R7_SOT363-6~D
220P_0402_50V8J~D
PC841
1
2
1
2
4
O
1
2
@ PR240
0_0402_5%~D
1
PR243
41.2K_0402_1%~D
2
1
P
-
G
8
+
PC243
100P_0402_50V8J~D
2
1
PR852
100K_0402_5%~D
+3.3V_ALW
2
PR242
42.2K_0402_1%~D
2
1
5
PQ806A
PR241
22.6K_0402_1%~D
2
1
3
1
PU12B
LM393DR_SO8~D
PR237
47K_0402_1%~D
2
1
2
1
PQ806B
2N7002DW-T/R7_SOT363-6~D
4
-
2
7
1
O
10K_0402_1%~D
PU12A
LM393DR_SO8~D
ACAV_IN_NB
<39,40,55>
@
2
1
PC842
+
PR239
+5V_ALW
A
0.1U_0402_25V4Z~D
B
A
O
3
TC7SH08FU_SSOP5~D
S
Adapter Protection Circuit fot Turbo Mode
1
2
1
P
4
G
PUH800
D
PROCHOT_GATE
2
G
<39>
To preset system to throtlle
switching from AC to DC
S
3
5
2
PC279
100P_0402_50V8J~D
2
1
D
2
G
3
0> DYN_TUR_CURRNT_SET#
PR260
66.5K_0402_1%~D
2
1
PR261
1
150K_0402_1%~D
2
1
6
A
+3.3V_ALW
P
5
MAX8731_REF
PR236
1M_0402_1%~D
1
2
3
8
PR847
20K_0402_1%~D
1
2
<7,40,51>
@ PR336
0_0402_5%~D
6
1
1
2
1.8M_0402_1%
G
MAX8731_IINP
PR846
4
Low
2
90W
PR474
2
1
2
PR259
150K_0402_1%~D
H_PROCHOT#
221K_0402_1%~D
High
@ PC245
0.01U_0402_25V7K~D
1
65W
@ PC244
100P_0402_50V8J~D
2
DYN_TUR_CURRENT_SET#
1
+5V_ALW
PC242
100P_0402_50V8J~D
2
1
+5V_ALW
+3.3V_ALW2
PR235
232K_0402_1%~D
2
1
Maximum charging current is 7.2A
ACAV_IN
<22,40,55>
PQ808
RHU002N06_SOT323-3~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Charger
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741P
Sheet
1
53
of
56
5
4
3
2
+VCCSA_P
1
VCCSA_VID_0
VCCSA_VID_1
VCCSA Vout
0
0
0.9V
0
1
0.8V
1
0
0.725V
1
1
0.675V
output voltage adjustable network
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
D
D
@ PR264
1
2
VCCSA_VID_1
<11>
2
0_0402_5%~D
PR266
1K_0402_5%~D
2
PC252
PR303
1
2
+5V_ALW
1
10_0402_1%~D
PC250
1
2
1U_0603_10V6K~D
0_0402_5%~D
1
VCCSA_VID_0
VCCSA
TDC=3.15A
Peak Current=4.5A
OCP min=5.85A
FSW=1MHz
<11>
2
0_0402_5%~D
PR300
1K_0402_5%~D
1
1
+VCCSA_PWRGD
<40> VCCSAPWROK
@ PR258
@ PR265
2
+VCCSA_VID0
2
PR244
100K_0402_5%~D
2
1
1
+3.3V_RUN
@
PR255
0_0402_5%~D
1
2
1.05V_VTTPWRGD
<40,50>
+VCCSA_EN
2.2U_0603_10V7K~D
1
7
PC260
22U_0805_6.3V6M
2
1
PC257
22U_0805_6.3V6M
2
1
PC256
2200P_0402_50V7K~D
2
1
@
2
SW
@
@ PR248
2.2_1206_1%~D
VIN
VIN
1000P_0603_50V7K~D
PC259
22U_0805_6.3V6M
2
1
SW
8
PC255
22U_0805_6.3V6M
2
1
PC181
22U_0805_6.3V6M
1
2
1
9
1 2
SW
VIN
PC258
0.1U_0402_10V7K~D
2
1
+VCCSA_P
PC182
22U_0805_6.3V6M
1
2
14
15
13
10
@ PC254
TP
25
6
VREF
GND
2
1
MODE
Vo=2v
PAD-OPEN 43X118
VOUT
24
PL18
2
PGND
SLEW
+VCCSA_PWR_SRC
+VCCSA_PHASE
EN
VID0
VID1
16
PGOOD
SW
5
23
11
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
TPS51461RGER_QFN24_4X4~D
22
12
PC253
0.1U_0603_25V7K
PR245
+VCCSA_BT 1
2+VCCSA_BT_1 1
2
2.2_0603_1%~D
PGND
4
PC246
10U_0805_25V6K
PC247
PC248
2
1
1
BST
SW
COMP
1 +VCCSA_PWR_SRC
1
2
PGND
3
2
2
10U_0805_25V6K
PJP35
+3.3V_ALW
2
21
0.1U_0603_25V7K~D
PC249
1
2200P_0402_50V7K~D
20
V5FILT
19
V5DRV
PU13
17
C
18
C
@ PR335
2
1
33K_0402_5%~D
2
PR267
1
100_0402_1%~D
GNDA_VCCSA
PC251
2
1
0.22U_0402_10V6K~D
B
PC383
2
1
2
PR247
PR253
2
1
0_0402_5%~D
1
5.1K_0402_1%~D
B
+VCCSA_SENSE
<11>
1
2
3300P_0402_50V7K~D
PC262
0.01U_0402_25V7K~D
PJP37
PJP38
+VCCSA_P
1
+VCC_SA
2
2
PAD-OPEN 4x4m
1
PAD-OPEN1x1m
GNDA_VCCSA
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
ISL95870A 0.8V_VCC_SA
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
54
of
56
5
4
PR307
2
47_0805_5%~D
1
2
3
4
+PWR_SRC
1
PD23
<39>
2
DEFAULT_OVRDE
1
RB751V-40_SOD323~D
2
PR292
2
1
499K_0402_1%~D
1
PC270
2
0.01U_0603_25V7K~D
PD21
2
RB751V-40_SOD323~D
1
PR923
10K_0402_5%~D
<39>
C
2
@
PQ911
2N7002W-7-F_SOT323-3~D
D
2
G
ACAV_IN
<22,40,53>
S
3
@ PR473
1
2
100K_0402_5%~D
2
MODULE_BATT_PRES#
<39,45>
PBATT+
@ PR301
0_0402_5%~D
@ PR312
1
<38> ACAV_DOCK_SRC#
1
2ACAVDK_SRC
0_0402_5%~D
+SDC_IN
@ PR314
1
2
0_0402_5%~D
CD3301_SDC_IN
<53> DC_BLOCK_GC
@ PR318
1
2
0_0402_5%~D
37
1
2
0_0402_5%~D
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
TP
27
26
25
24
23
22
21
20
19
P50ALW
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
GND
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
5
4
ERC2
@
+5V_ALW
DK_AC_OFF
SLICE_BAT_ON
DOCK_AC_OFF
@ PR316
1
2
0_0402_5%~D
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
<39>
<38,39>
3301_ACAV_IN_NB
@ PR317
1
2
0_0402_5%~D
SLICE_BAT_PRES#
ACAV_IN_NB
PR315
1
2
1M_0402_5%~D
<39,40,53>
DOCK_AC_OFF_EC
<39>
<38,39>
+NBDOCK_DC_IN_SS
CD3301ARHHR_QFN36_6X6~D
A
P33ALW
1
EN_DK_PWRBAR
PC275
0.1U_0402_25V4Z~D
2
1
PC272
1500P_0402_7K~D
0.047U_0603_25V7K~D
PC273
2
1
1
0_0402_5%~D
<38,39>
ERC3
PC274
2
1
2
2
DOCK_SMB_ALERT#
0.1U_0603_25V7K~D
3
3
1
@ PR321
1
2
<53>
CSS_GC
<53> DK_CSS_GC
2
0_0402_5%~D
@ PR311
2
0_0402_5%~D
@ PR313
1
2
0_0402_5%~D
1
@ PR320
1
2
0_0402_5%~D
@ PR322
1
2
0_0402_5%~D
PQ57
FDN338P_NL_SOT23-3~D
1
CD_PBATT_OFF
10
11
12
13
14
15
16
17
18
+3.3V_ALW2
1
1
PD28
2
ACAV_IN
@ PR319
2
38,39> SLICE_BAT_PRES#
RB751V-40_SOD323~D
1
PD29
2
A
RB751V-40_SOD323~D
<22,40,53>
1
2
ERC1
3
4
5
6
7
ACAVIN
8
P33ALW2 9
P50ALW
36
35
34
33
32
31
30
29
28
PU14
NC
CHARGERVR_DCIN
DC_IN_SS
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
+3.3V_ALW2
B
@ PR306
0_0402_5%~D
@ PR309
<45> SOFT_START_GC
PR310
1
2
100K_0402_5%~D
PC268
0.1U_0603_25V7K~D
2
1
S
S
S
G
PC267
2200P_0402_50V7K~D
2
1
D
D
D
D
PR289
2
1
499K_0402_1%~D
MODULE_ON
CSS_GC
DK_CSS_GC
ERC3
ERC2
GND
PWR_SRC
SS_DCBLK_GC
EN_DK_PWRBAR
P33ALW
PC271
0.1U_0603_50V4Z~D
1
PQ46
2
2
1
CD3301_DCIN
2
1
PDS5100H-13_POWERDI5-3~D
CHGVR_DCIN
DC_IN_SS
DK_PWRBAR
1
+DC_IN
2
2
1
1
PR275
PC265
2
1
2
1
3
PBATT_IN_SS
1
PR471
2
1
510K_0402_5%~D
2
FDS6679AZ_SO8~D
PR284
2N7002DW-T/R7_SOT363-6~D
1
6
PQ50A
RB751V-40_SOD323~D
499K_0402_1%~D
3
PR282
2
1
620K_0402_5%~D
6
1
2
@ PR305
0_0402_5%~D
<53> +CHGR_DC_IN
@ PR269
0_0402_5%~D
PD20
2
330K_0402_5%~D
PC263
0.47U_0805_25V7K~D
D
PR268
330K_0402_5%~D
1
+DC_IN_SS
1
2
3
4
0_0402_5%~D
PR299
1
2
@ PR302 0_0402_5%~D
1
2
0_0402_5%~D
+DOCK_PWR_BAR
S
S
S
G
@ PR472
1
@
PBAT_PRES#
D
D
D
D
820_0603_1%~D
MPBATT+
5
8
7
6
5
+DOCK_PWR_BAR
2
SLICE_BAT_PRES#
PQ49A
1
PR291
2
1
390K_0402_5%~D
PQ48B
2N7002DW-T/R7_SOT363-6~D
2
4
3
PD27
1
PQ50B
2N7002DW-T/R7_SOT363-6~D
4
3
1
0_0402_5%~D
2
3
2 4
1
<39,45>
@ PR296
<38,39>
@ PR298
0_0402_5%~D
@ PR287
5 1
2
0_0402_5%~D
PR278
1
1
PQ37
2
@
B
2N7002DW-T/R7_SOT363-6~D
PR288
1
2
1
499K_0402_1%~D
2
0_0402_5%~D
PQ51A
@ PR294
1
2
<39> DEFAULT_OVRDE
2N7002DW-T/R7_SOT363-6~D
PQ51B
5
6
<39> SLICE_BAT_ON
PD22
RB751V-40_SOD323~D
1
2
1
2
PD24
RB751V-40_SOD323~D
PR290
2
1
200K_0402_1%~D
PBATT+
PD26
RB751V-40_SOD323~D
1
2
2
6
PQ48A
2
2
@ PR285
0_0402_5%~D
1
2N7002W-7-F_SOT323-3~D
2N7002DW-T/R7_SOT363-6~D
1
2
PR280
20K_0402_1%~D
PD25
RB751V-40_SOD323~D
1
2
1
4
S
5
4
1
3
5
D PQ910
2
G
9,45> PBAT_PRES#
PR281
2
1
390K_0402_5%~D
2
PQ49B
2N7002DW-T/R7_SOT363-6~D
PQ47A
2N7002DW-T/R7_SOT363-6~D
1
6
3
1
C
PQ47B
3
PR286
2
1
10K_0402_5%~D
2
3
PR257
1K_0402_5%~D
2
2
FDS6679AZ_SO8~D
PD19
RB751V-40_SOD323~D
2
1
8
7
6
5
1
G
A
PR297
20K_0402_1%~D
1
2
3
4
S
S
S
G
PD18
RB751V-40_SOD323~D
2
1
PQ45
FDS6679AZ_SO8~D
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
D
2N7002DW-T/R7_SOT363-6~D
O
2
CHARGE_PBATT
@
4
1
B
PQ42B
4
1
PR276
2
1
P
5
PUH5
TC7SH08FU_SSOP5~D
1
ACAV_IN
2N7002DW-T/R7_SOT363-6~D
0.1U_0402_10V7K~D
>
0.1U_0603_25V7K~D
PC233
1
2
PC266
2
1
PR279
1
2
100K_0402_5%~D
+3.3V_ALW2
4
+VCHGR
PQ44
SI4835DDY-T1-E3_SO8~D
1
8
2
7
3
6
5
D
D
D
D
FDS6679AZ_SO8~D
PBATT+
2N7002W-7-F_SOT323-3~D
PQ41
8
7
6
5
PR274
1
2
820_0603_1%~D
PQ909
PD16
ES2AA-13-F_SMA2~D
PDS5100H-13_POWERDI5-3~D
0.01U_0603_25V7K~D
4
6
PR304
2
1
1K_0402_5%~D
1
3
S
1
3
PR283
1
2
330K_0402_5%~D
STSTART_DCBLOCK_GC
D
5
PQ42A
2N7002DW-T/R7_SOT363-6~D
2
39,45> MODULE_BATT_PRES#
2
G
1
2
MPBATT_IN_SS
2N7002DW-T/R7_SOT363-6~D
3
D
PR272
2
1
620K_0402_5%~D
@
390K_0402_5%~D
4
O
A
PC264
2
1
5
B
TC7SH08FU_SSOP5~D
PR270
1
2
100K_0402_5%~D
2
PQ40
FDS6679AZ_SO8~D
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
D
MPBATT+
PR273
2
1
10K_0402_5%~D
1
ACAV_IN
G
<22,40,53>
9> CHARGE_MODULE_BATT
PUH3
P
0.1U_0402_10V7K~D
0.1U_0603_25V7K~D
+VCHGR
2
PD17
PR271
2
1
390K_0402_5%~D
+3.3V_ALW2
PC232
1
2
3
PQ39
SI4835DDY-T1-E3_SO8~D
1
8
2
7
3
6
5
@ PR324
2
0_0402_5%~D
1
@ PR325
2
0_0402_5%~D
STSTART_DCBLOCK_GC
3301_PWRSRC
@ PR327
1
2
0_0402_5%~D
+3.3V_ALW
EN_DOCK_PWR_BAR
<39>
DELL CONFIDENTIAL/PROPRIETARY
@ PR326
1
2
1M_0402_5%~D
Compal Electronics, Inc.
Title
+PWR_SRC
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Selector
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
55
of
56
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_GFXCORE
Charlie note:
iGfx_Cout1
1.22uF*6 (SE000000I10)
2.10uF*6 (SE000005T8L)
3.1uF*11 (SE000000K8L)
iGfx_Cout2
1.470uF 4.5m *2 (SGA00004200)
Socket Bottom
5 x 22 µF (0805)
5 x (0805) no-stuff
sites
Socket Top
7 x 22 µF (0805)
2 x (0805) no-stuff
sites
PC1216
22U_0805_6.3V6M
PC1229
1U_0402_6.3V6K~D
2
1
PC1230
1U_0402_6.3V6K~D
2
1
PC1231
1U_0402_6.3V6K~D
2
1
PC1232
1U_0402_6.3V6K~D
2
1
PC1233
1U_0402_6.3V6K~D
2
1
PC1234
1U_0402_6.3V6K~D
PC1250
1U_0402_6.3V6K~D
2
1
PC1251
1U_0402_6.3V6K~D
2
1
PC1252
1U_0402_6.3V6K~D
2
1
PC1253
1U_0402_6.3V6K~D
2
1
PC1254
1U_0402_6.3V6K~D
2
1
PC1255
1U_0402_6.3V6K~D
PC1321
10U_0603_6.3V6M~D
2
1
PC1322
10U_0603_6.3V6M~D
2
1
2
PC1219
22U_0805_6.3VAM
2
1
PC1220
22U_0805_6.3VAM
2
1
PC1221
22U_0805_6.3VAM
2
1
PC1222
22U_0805_6.3VAM
2
2
PC1223
22U_0805_6.3VAM
+
2
1
Charlie note:
+1.05V_RUN_VTT_1
3.1uF*26 (SE000000K8L)
4.10uF*10 (SE000005T8L)
B
1
2
1
PC1243
22U_0805_6.3VAM
1
2
2
1
PC1244
22U_0805_6.3VAM
1
PC1260
22U_0805_6.3VAM
2
2
1
PC1245
22U_0805_6.3VAM
1
PC1261
22U_0805_6.3VAM
2
2
1
PC1246
22U_0805_6.3VAM
2
1
PC1262
22U_0805_6.3VAM
2
2
PC1264
22U_0805_6.3VAM
+VCC_CORE
+
2
1
PC1268
22U_0805_6.3VAM
2
1
PC1269
22U_0805_6.3VAM
2
1
PC1270
22U_0805_6.3VAM
2
1
PC1271
22U_0805_6.3VAM
2
PC1298
22U_0805_6.3VAM
+
2
B
+VCC_CORE
1
1
2
1
+1.05V_RUN_VTT_2
5.330uF 6m *2 (SGA00001Q80)
PC1247
22U_0805_6.3VAM
1
PC1263
22U_0805_6.3VAM
+
PC1323
10U_0603_6.3V6M~D
1
PC1265
1
1
330U_X_2VM_R6M
2
+
C
PC1316
1U_0402_6.3V6K~D
PC1228
1U_0402_6.3V6K~D
2
1
PC1249
1U_0402_6.3V6K~D
2
1
PC1325
10U_0603_6.3V6M~D
2
1
1
PC1256
470U_D2_2VM_R4.5M
+VCC_CORE
PC1257
470U_D2_2VM_R4.5M
2
PC1297
2.2U_0402_6.3V6M~D
PC1314
1U_0402_6.3V6K~D
2
1
PC1227
1U_0402_6.3V6K~D
2
1
PC1248
1U_0402_6.3V6K~D
2
1
PC1318
10U_0603_6.3V6M~D
2
1
1
2
1
PC1295
2.2U_0402_6.3V6M~D
2
PC1292
2.2U_0402_6.3V6M~D
2
PC1296
2.2U_0402_6.3V6M~D
2
1
PC1293
2.2U_0402_6.3V6M~D
2
1
2
1
2
PC1294
2.2U_0402_6.3V6M~D
PC1326
10U_0603_6.3V6M~D
2
1
PC1226
1U_0402_6.3V6K~D
2
1
PC1311
1U_0402_6.3V6K~D
2
1
PC1317
10U_0603_6.3V6M~D
2
1
1
PC1225
1U_0402_6.3V6K~D
2
1
PC1267
1U_0402_6.3V6K~D
2
1
1
PC1218
10U_0603_6.3V6M~D
PC1306
1U_0402_6.3V6K~D
PC1291
2.2U_0402_6.3V6M~D
PC1319
10U_0603_6.3V6M~D
2
1
PC1217
10U_0603_6.3V6M~D
2
1
PC1304
1U_0402_6.3V6K~D
2
1
PC1309
1U_0402_6.3V6K~D
2
PC1238
10U_0603_6.3V6M~D
2
1
PC1242
1U_0402_6.3V6K~D
2
1
PC1310
1U_0402_6.3V6K~D
2
1
1
PC1237
10U_0603_6.3V6M~D
2
1
PC1241
1U_0402_6.3V6K~D
2
1
PC1308
1U_0402_6.3V6K~D
2
1
1
2
1
PC1289
2.2U_0402_6.3V6M~D
2
2
1
2
PC1287
2.2U_0402_6.3V6M~D
1
2
PC1288
2.2U_0402_6.3V6M~D
2
C
+1.05V_RUN_VTT
PC1224
1U_0402_6.3V6K~D
2
1
1
+1.05V_RUN_VTT
2
PC1236
10U_0603_6.3V6M~D
2
1
PC1240
1U_0402_6.3V6K~D
2
1
PC1307
1U_0402_6.3V6K~D
2
1
1
1
PC1285
2.2U_0402_6.3V6M~D
D
PC1312
1U_0402_6.3V6K~D
2
1
PC1215
22U_0805_6.3V6M
2
PC1278
2.2U_0402_6.3V6M~D
2
2
1
2
1
PC1235
10U_0603_6.3V6M~D
2
1
2
1
2
1
PC1239
1U_0402_6.3V6K~D
2
1
2
1
2
PC1290
PC1286
2.2U_0402_6.3V6M~D 2.2U_0402_6.3V6M~D
PC1283
2.2U_0402_6.3V6M~D
2
2
PC1280
2.2U_0402_6.3V6M~D
1
PC1284
2.2U_0402_6.3V6M~D
2
PC1281
2.2U_0402_6.3V6M~D
1
PC1282
2.2U_0402_6.3V6M~D
2
1
PC1305
1U_0402_6.3V6K~D
2
1
PC1276
2.2U_0402_6.3V6M~D
2
1
PC1214
22U_0805_6.3V6M
1
2
1
PC1259
2.2U_0402_6.3V6M~D
2
1
2
1
PC1277
2.2U_0402_6.3V6M~D
1
1
2
1
1
2
1
1
2
PC1279
PC1258
2.2U_0402_6.3V6M~D 2.2U_0402_6.3V6M~D
1
2
1
PC1213
22U_0805_6.3V6M
1
PC1212
22U_0805_6.3V6M
PC1210
2.2U_0402_6.3V6M~D
PC1211
22U_0805_6.3V6M
1
2
1
PC1208
PC1209
2.2U_0402_6.3V6M~D 2.2U_0402_6.3V6M~D
2
1
2
1
PC1207
2.2U_0402_6.3V6M~D
2
1
PC1205
PC1206
2.2U_0402_6.3V6M~D 2.2U_0402_6.3V6M~D
2
1
2
D
330U_X_2VM_R6M
PC1266
+VCC_GFXCORE
PC1204
2.2U_0402_6.3V6M~D
1
PC1313
1U_0402_6.3V6K~D
2
1
PC1203
2.2U_0402_6.3V6M~D
2
2
PC1202
2.2U_0402_6.3V6M~D
+VCC_CORE
1
1
1
2
1
PC1201
2.2U_0402_6.3V6M~D
2
1
2
PC1200
2.2U_0402_6.3V6M~D
2
PC1320
10U_0603_6.3V6M~D
2
1
+VCC_CORE
3
PC1315
1U_0402_6.3V6K~D
2
1
4
Charlie note: Vcore_Cout1
1.2.2uF*35 (SE00000888L)
2.22uF*25 (SE000008L80)
Vcore_Cout2
1.470uF 4.5m *4 (SGA00004X80)
PC1324
10U_0603_6.3V6M~D
2
1
5
1
+
PC1272
1
PC1273
+
1
PC1274
+
PC1275
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
2 3
2 3
2 3
2 3
A
A
1
2
1
PC1302
22U_0805_6.3VAM
2
1
PC1301
22U_0805_6.3VAM
2
1
PC1300
22U_0805_6.3VAM
2
DELL CONFIDENTIAL/PROPRIETARY
1
PC1299
22U_0805_6.3VAM
2
PC1303
22U_0805_6.3VAM
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR DECOUPLING
Size
Document Number
Date:
Thursday, June 23, 2011
Rev
0.1
LA-7741
Sheet
1
56
of
56
www.s-manuals.com
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Format : application/pdf Creator : Title : Compal LA-7741P - Schematics. www.s-manuals.com. Subject : Compal LA-7741P - Schematics. www.s-manuals.com. Create Date : 2011:06:23 14:42:12 Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2015:11:16 21:26:01+02:00 Metadata Date : 2015:11:16 21:26:01+02:00 Producer : GPL Ghostscript 8.15 Document ID : uuid:7bd6b1f5-b189-4aca-89fc-e77f9771cf5c Instance ID : uuid:8b767e1c-ba1c-4241-b705-670562a1ee2e Has XFA : No Page Count : 57 Keywords : Compal, LA-7741P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools