Compal LA 8131P, 8132P Schematics. Www.s Manuals.com. R0.6 Schematics

User Manual: Motherboard Compal LA-8131P QILE1 - Schematics. Free.

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Compal Confidential

A

Model Name : QILE1 & QILE2
File Name : LA-8131P, LA-8132P
BOM P/N:
QILE1:
4319GG39L01 : SMT MB A8131 QILE1 DIS-N13P
4319GG39L02 : SMT MB A8131 QILE1 DIS GPU-N13M
4319GG39L03 : SMT MB A8131 QILE1 UMA

A

QILE2:
4319GJ39L01 : SMT MB A8133 QILE2 DIS-N13P
4319GJ39L02 : SMT MB A8133 QILE2 DIS GPU-N13M
4319GJ39L03 : SMT MB A8133 QILE2 UMA

Compal Confidential
B

B

M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
GPU nVIDIA N13M-GE1 / N13P-GL

2011-12-20

C

C

REV:0.6

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
Cover
Sheet
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
1
58
of
Date:
Sheet
Title

5

Rev
0.6

A

B

C

D

E

ZZZ

LA8131P
DA_PCB

nVIDIA N13M-GE1
DDR3*4
VRAM 256M*16/
128M*16/64M*16
nVIDIA N13P-GL
DDR3*8
VRAM 256M*16/
128M*16/64M*16 Page 24~32

DA80000QL00

1

Intel
Ivy Bridge

PCI-E X16

1.5V DDR3 1600MHz

rPGA 989 Socket
37.5mm * 37.5mm

1

DDR3-SO-DIMM X2
Page 11~12

Page 4~10

HDMI Connector
HDMI

Page 34

FDI x8
(UMA)

DMI x4

2Channel Speaker
Page 35

100MHz
5GB/s

100MHz
2.7GT/s

CRT Connector
Page 33

2

Memory Bus
Dual Channel

RGB
HD Audio

Intel
Panther Point

LVDS

LVDS Connector
Page 32

PCI-E
cable

Realtek RTS5229

SPI ROM
BIOS 8M+4M

Page 36

RTL8111F(Giga)

Page 35

USB 2.0

CMOS Camera

2

Page 32

USB 3.0

Page 13~21

SATA

USB PORT 2.0 x 1(charger)
Page 39

cable

Sub-Board

Page 40

LPC BUS

Finger Printer

UPEK TCS5DA6C0

3

Audio combo Jack
Page 35
Sub-Board

SPI

Page 13

Realtek

CX20671-21Z CODEC

FCBGA 989
25mm*25mm
HM76

Card Reader

Digital MIC
Page 35

Audio Codec

TPM

EC

RJ45 CONN
Page 40

Page 40

ENE KBC9012

Page 40

USB PORT 3.0 x 3

Page 41

3

Page 37

Sub-Board

Track Point
Page 39

PCI Express
Mini card
Slot 1
Page 38

USB(BT)

PCI Express
Mini card
Slot 2
Page 38

USB

G-Sensor
Page 36

Click Pad

Int.KBD

Page 39

Page 39

Thermal Sensor

Fintek F75303M

Page 36

SATA ODD CONN

Page 36

m-SATA CONN

Page 38

Page 39

PCI-E(WLAN)

WLAN/WiMAX/BT

4

SATA3.0 HDD CONN

SATA
4

WWAN/mSATA

SIM Card

A

Compal Secret Data

Security Classification
Issued Date

Page 38

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Compal Electronics, Inc.
Block
Diagram
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
2
58
of
Date:
Sheet
Title

E

Rev
0.6

1

2

3

4

5

Voltage Rails
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#

STATE
+5VS

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON

+3VS
power
plane

+1.5VS
+VCCP

A

+1.5V

+B

A

+CPU_CORE

+5VALW

+VGA_CORE
+3VM

+3VALW

+VCC_GFXCORE_AXG
+1.05VM

+1.8VS
+0.75VS

State

BOARD ID Table

+1.05VS

B

O

S0

O

O

O

O

M3 Supported

S3

O

O

O

X

M3 Supported

S5 S4/AC

O

O

X

X

M3 Supported

S5 S4/ Battery only

X

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

O
O

Board ID
0
1
2
3
4
5
6
7

PCB Revision
0.1
0.2
0.3
0.4
0.5
0.6

B

USB Port Table

BOM Structure Table
3 External
USB Port

USB 2.0 Port

EC SM Bus1 address

EC SM Bus2 address

UHCI0

Device

Address

Device

Smart Battery

0001 011X b

Thermal Sensor Fintek F75303M 1001_101xb

Address

UHCI1
EHCI1
USB3.0

PCH SM Bus address
Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

UHCI2
UHCI3
UHCI4

EHCI2

UHCI5

C

UHCI6

0
1
2
3
4
5
6
7
8
9
10
11
12
13

USB 3.0 Port (Left Side)
USB 3.0 Port (Left Side)
USB 3.0 Port (Left Side)
Camera

USB Port (Right Side)
Mini Card(WLAN/BT)
FPR
Mini Card(WWAN)
Blue Tooth

BTO Item
Connector
45 LEVEL
Unpop
nVidia
INTEL DD3 M3
SIM Card Slot
Intel UMA
VRAM Option
Intel SBA
Intel AOAC
TPM
GPU N13M
GPU N13P

BOM Structure
CONN@
45@
@
DIS@
M3@
3G@
UMA@
X76@
SBA@
AOAC@
TPM@
N13M@
N13MP
C

60%86&RQWURO7DEOH
6285&(
60%B(&B&.
60%B(&B'$
60%B(&B&.
60%B(&B'$
60%&/.
60%'$7$
60/&/.
60/'$7$
60/&/.
60/'$7$

.%
9$/:
.%
9$/:
3&+
9$/:
3&+
9$/:
3&+
9$/:

9*$

%$77

.(

62',00

:/$1
::$1

7KHUPDO
6HQVRU

3&+

9

;

;

;

;

;

;

;

;

;

;

96

;

;

;

96

9

96

9

;

;

;

;

;

;

;

;

;

9

;

96

9

;

;

96

9

;

;
;

96

9$/:

9

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
Notes
List
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
3
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

A

B27
B25
A25
B24

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

(15)
(15)
(15)
(15)

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

(15)
(15)
(15)
(15)

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

(15)
(15)
(15)
(15)

B

(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

(15) FDI_FSYNC0
(15) FDI_FSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

(15) FDI_INT

H20

FDI_INT

(15) FDI_LSYNC0
(15) FDI_LSYNC1

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

C15
D15

eDP_AUX
eDP_AUX#

C17
F16
C16
G15

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

C18
E16
D16
F15

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

R2

1

R3

1

2 24.9_0402_1%
@

EDP_COMP

2 10K_0402_5%

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

C

eDP

+1.05VS

PCI EXPRESS* - GRAPHICS

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

(15)
(15)
(15)
(15)

CONN@

DMI

JCPU1A

4

5

A

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_COMP

R1

2 24.9_0402_1%

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N15

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P15

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N15

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P15

C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

1

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms

+1.05VS

PCIE_CRX_GTX_N[0..15]

(22)

PEG Static Lane Reversal - CFG2 is for the 16x

*

CFG2
PCIE_CRX_GTX_P[0..15]

1: Normal Operation; Lane #
socket pin map definition

definition matches

0:Lane Reversed

(22)

B

PCIE_CTX_GRX_N[0..15]

(22)

PCIE_CTX_GRX_P[0..15]

(22)

C

TYCO_2013620-2_IVY BRIDGE

Nvidia support PCIE Gen2

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PROCESSOR(1/7)
DMI,FDI,PEGRev
Size Document Number
Custom
0.6
LA-8131P
Friday, January 06, 2012
4
58
of
Date:
Sheet
Title

5

1

2

3

4

5

JCPU1B
A

2 10K_0402_5%

+1.05VS
(18,41) H_PECI

Processor Pullups
R5 1

2 62_0402_5%

H_PROCHOT#

H_PROCHOT#

(41) H_PROCHOT#

R12

1

AN34

AL33

CATERR#

H_PECI

AN33

PECI

AL32

PROCHOT#

H_THRMTRIP#

(15) H_PM_SYNC

AN32

PM_SYS_PWRGD_BUF

R23
R6
C33

@
1
2 0_0402_5%
1
2 10K_0402_5%
@1
2 220P_0402_50V7K

R25

1

2 130_0402_5%

THERMTRIP#

H_PM_SYNC

AM34

PM_SYNC

H_CPUPWRGD_R

AP33

UNCOREPWRGOOD

B

(18) H_CPUPWRGD

SKTOCC#

H_CATERR#

2 56_0402_5% H_PROCHOT#_R

(18) H_THRMTRIP#

PROC_SELECT#

PM_DRAM_PWRGD_R

BUF_CPU_RST#

V8

AR33

CLOCKS

@

SM_DRAMPWROK

RESET#

A28
A27

DPLL_REF_CLK
DPLL_REF_CLK#

A16
A15

SM_DRAMRST#

R8

DDR3
MISC

1

BCLK
BCLK#

JTAG & BPM

R8

THERMAL

(18) H_SNB_IVB#

PWR MANAGEMENT

C26

MISC

A

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AK1
A5
A4

CLK_CPU_DMI_R
CLK_CPU_DMI#_R

R4
R7

1
1

2 0_0402_5%
2 0_0402_5%

CLK_CPU_DMI (14)
CLK_CPU_DMI# (14)

R9
R10

1
1

2 1K_0402_5%
2 1K_0402_5%

+1.05VS

H_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

R13
R14
R15

1
1
1

(6)

2 140_0402_1%
2 25.5_.402_1%
2 200_0402_1%

DDR3 Compensation Signals

P+
P+

PRDY#
PREQ#

AP29
AP27

XDP_PRDY#
XDP_PREQ#

P+
P+
P+

TCK
TMS
TRST#

AR26
AR27
AP30

XDP_TCK
XDP_TMS
XDP_TRST#

R21
R17
R22

1
1
1

2 51_0402_5%
2 51_0402_5%
2 51_0402_5%

P+

TDI
TDO

AR28
AP26

XDP_TDI
XDP_TDO

R18
R19

1
1

2 51_0402_5%
2 51_0402_5%

AL35

XDP_DBRESET#

R24

1

2 1K_0402_5%

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

PU/PD for JTAG signals
+1.05VS

B

+3VS

P+

XDP_DBRESET#

(15)

TYCO_2013620-2_IVY BRIDGE
CONN@

C

C

P

5
(17) PCH_PLTRST#

2

NC
A

G

O

1
PM_SYS_PWRGD_BUF

4

P

1
3

R34
75_0402_5%

Y

4 BUFO_CPU_RST#

R36
43_0402_1%
1
2

U2
SN74LVC1G07DCKR_SC70-5

R37
39_0402_5%
@

BUF_CPU_RST#
R38
0_0402_5%
@

For 26 Pin XDP Conn.

1 2

2

A

U1 @
74AHC1G09GW_TSSOP5

C35
0.1U_0402_16V4Z

2

3

2

(15) PM_DRAM_PWRGD

1

Buffered reset to CPU
R33
200_0402_5%

2

B

5

R35 @
10K_0402_5%
1
2 1

+1.05VS

1

C34 @
0.1U_0402_16V4Z

2

G

1

+3VS

1

+1.5V_CPU_VDDQ

2

+3VALW

1

+3VS

Q1
2N7002K_SOT23-3
@

D
(9) RUN_ON_CPU1.5VS3#

2

(18)
(15,41)
(7)
(15)
(14)
(14)
(14,17,22,36,38,40,41)

G
3

S
D

PM_DRAM_PWRGD

R214 1

2 0_0402_5%

PLT_RST#

R26
R27
R28
R29
R30
R31
R32

1
1
1
1
1
1
1

@
@
@
@
@
@
@

2
2
2
2
2
2
2

1K_0402_1%
0_0402_5%
1K_0402_1%
0_0402_5%
0_0402_5%
0_0402_5%
1K_0402_1%
D

PM_SYS_PWRGD_BUF

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

H_CPUPWRGD
PBTN_OUT#
XDP_CFG0
SYS_PWROK
CLK_XDP_CLK
CLK_XDP_CLK#
PLT_RST#

2

3

4

Compal Electronics, Inc.
PROCESSOR(2/7)
PM,XDP,CLKRev
Size Document Number
Custom
0.6
LA-8131P
Friday, January 06, 2012
5
58
of
Date:
Sheet
Title

5

2

JCPU1C

(11) DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

B

C

(11) DDR_A_BS0
(11) DDR_A_BS1
(11) DDR_A_BS2

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AE10
AF10
V6

SA_BS[0]
SA_BS[1]
SA_BS[2]

AE8
AD9
AF9

SA_CAS#
SA_RAS#
SA_WE#

(11) DDR_A_CAS#
(11) DDR_A_RAS#
(11) DDR_A_WE#

4

CONN@

DDR SYSTEM MEMORY A

A

3

5

JCPU1D

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

M_CLK_DDR0 (11)
M_CLK_DDR#0 (11)
DDR_CKE0_DIMMA (11)

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

M_CLK_DDR1 (11)
M_CLK_DDR#1 (11)
DDR_CKE1_DIMMA (11)

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

AB4
AA4
W9

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

AH3
AG3
AG2
AH2

M_ODT0 (11)
M_ODT1 (11)

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#[0..7]

(12) DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

(11)
(11)

(11)

DDR_A_DQS[0..7]

(11)

DDR_A_MA[0..15]

(11)

CONN@

(12) DDR_B_BS0
(12) DDR_B_BS1
(12) DDR_B_BS2

(12) DDR_B_CAS#
(12) DDR_B_RAS#
(12) DDR_B_WE#

TYCO_2013620-2_IVY BRIDGE

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9
AA7
R6

SB_BS[0]
SB_BS[1]
SB_BS[2]

AA10
AB8
AB9

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

1

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

AE2
AD2
R9

M_CLK_DDR2 (12)
M_CLK_DDR#2 (12)
DDR_CKE2_DIMMB (12)

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

M_CLK_DDR3 (12)
M_CLK_DDR#3 (12)
DDR_CKE3_DIMMB (12)

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

AB2
AA2
T9

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

AD3
AE3
AD6
AE6

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

AE4
AD4
AD5
AE5

M_ODT2 (12)
M_ODT3 (12)

A

(12)
(12)

B

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

(12)

(12)

(12)

C

TYCO_2013620-2_IVY BRIDGE

+1.5V
@

1

2 0_0402_5%

1

R39

1

D

D

S

1

2

G

R41
1K_0402_5%
1
2

DDR3_DRAMRST#

(11,12)
D

Q2
BSS138_NL_SOT23-3

2

R42
4.99K_0402_1%

DDR3_DRAMRST#_R

2

R40
1K_0402_5%
3

(5) H_DRAMRST#

(14) DRAMRST_CNTRL_PCH

R43

1

2 0_0402_5%

DRAMRST_CNTRL
1

DRAMRST_CNTRL

(9)

Issued Date

2

1

Compal Secret Data

Security Classification

C36
0.047U_0402_16V4Z

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3

4

Compal Electronics, Inc.
PROCESSOR(3/7)
DDRIII
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
6
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

CFG Straps for Processor
1

CFG2

2

A

JCPU1E

R45
1K_0402_1%
@

A

CONN@

PEG Static Lane Reversal - CFG2 is for the 16x

B

R176
R179

1

@

1

@

2 100_0402_1%
2 100_0402_1%

VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

R47

1

2 49.9_0402_1%

VSS_AXG_VAL_SENSE

R49

1

2 49.9_0402_1%

VSS_VAL_SENSE

AJ26

RSVD5

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

J20
B18

RSVD24
RSVD25

J15

RSVD27

L7
AG7
AE7
AK2

RSVD32

W8

RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

RSVD37
RSVD38
RSVD39
RSVD40

T8
J16
H16
G16

2 0_0402_5%

CFG2

*

1: Normal Operation; Lane #
socket pin map definition

definition matches

0:Lane Reversed

CFG4
1

RSVD28
RSVD29
RSVD30
RSVD31

@

2

@ R50
1K_0402_1%

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

Display Port Presence Strap
B

CFG4

*

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

AR35
AT34
AT33
AP35
AR34

CFG6
CFG5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10

@ R51
1K_0402_1%

B34
A33
A34
B35
C35

RSVD51
RSVD52

AJ32
AK32

BCLK_ITP
BCLK_ITP#

AN35
AM35

*10: x8, x8 - Device 1 function 1 enabled ; function 2

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2
AT1
AR1

B1

C

CFG7
1

KEY

@ R52
1K_0402_1%

PCIE Port Bifurcation Straps

C

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

1

1

AJ31
AH31
AJ33
AH33

2

R46
49.9_0402_1%
2

R48
49.9_0402_1%

P+

R173 1

1

+VCC_GFXCORE_AXG

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

T2

2

+CPU_CORE

1

CFG4
CFG5
CFG6
CFG7

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AH27
AH26

2

CFG2

RESERVED

XDP_CFG0

CFG

(5)

VCC_DIE_SENSE
VSS_DIE_SENSE

@ R53
1K_0402_1%
2

TYCO_2013620-2_IVY BRIDGE

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PROCESSOR(4/7)
RSVD,CFG
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
7
58
of
Date:
Sheet
Title

5

Rev
0.6

2

3

+CPU_CORE
JCPU1F

4

CONN@

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

VCCIO40

J23

A

B

SVID

2

VIDALERT#
VIDSCLK
VIDSOUT

AJ29
AJ30
AJ28

1

1

1

R54
130_0402_5%

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

1

R55
75_0402_5%

R56
R57
R58

1
1
1

@
@

C38
0.1U_0402_16V4Z

2

2

C37
0.1U_0402_16V4Z

+1.05VS

Place the PU
resistors close to VR

2 43_0402_1%
2 0_0402_5%
2 0_0402_5%

VR_SVID_ALRT# (52)
VR_SVID_CLK (52)
VR_SVID_DAT (52)

C

VSSSENSE_R

R174

2 100_0402_1% VCCSENSE_R

@1

1

+CPU_CORE

R59
100_0402_1%

VCCSENSE_R
VSSSENSE_R

R60
R61

1
1

@
@

2 0_0402_5%
2 0_0402_5%

VCCSENSE (52)
VSSSENSE (52)

R64 1
2 10_0402_1%
VCCIO_SENSE
B10
VSSIO_SENSE
A10

1

+1.05VS
VCCIO_SENSE

1

VCCIO_SENSE
VSS_SENSE_VCCIO

AJ35
AJ34

R62
100_0402_1%

(50)
2

VCC_SENSE
VSS_SENSE

Place the PU
resistors close to CPU

2

Trace Impedance = 27 ~ 33 ohm
Trace Length Match < 25 mils

R63
10_0402_1%
2

C

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

+1.05VS

SENSE LINES

B

8.5A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

CORE SUPPLY

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

PEG AND DDR

97A
A

5

+1.05VS

POWER

2

1

D

D

TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PROCESSOR(5/7)
PWR,BYPASS
Size Document Number
Rev
Custom
0.6
LA-8131P
Friday, January 06, 2012
8
58
of
Date:
Sheet
Title

5

1

2

3

4

5

Dϯ^ƵƉƉŽƌƚ

R67

@

1

2 0_0402_5%
+VREF_DQ_DIMMA

Q3
BSS138_NL_SOT23-3
+V_DDR_REFA_R

1

2

1

S

3

D

+VCC_GFXCORE_AXG

2
DRAMRST_CNTRL

1

2

R65
10_0402_1%

G

R79
1K_0402_1%
@

2

2
1

+1.5V

2

1
2

2

2

PAD-OPEN 4x4m

C47

1

2 0.1U_0402_10V7K

C53

1

2 0.1U_0402_10V7K

C54

1

2 0.1U_0402_10V7K

C55

1

2 0.1U_0402_10V7K
B

2

1

@

2

1
+

@

2

+VCCSA_SENSE
1

@

+1.5V_CPU_VDDQ Source

(49)

2 0_0402_5%

C

H_VCCSA_VID0
H_VCCSA_VID1

+3VALW

(49)
(49)

+VSB

+1.5V

1

@

2 0_0402_5%

R78

1

1

2

PAD-OPEN 4x4m
Q5
AP4800BGM-HF_SO-8

2 10K_0402_5%
1

8
7
6
5

2

R81
82K_0402_1%

1
2
3

R82

R80
100K_0402_5%
@

1

R77

1

4

2

H_VCCP_SEL

+1.5V_CPU_VDDQ

@ J2

1

2

1

1

R86

1

@

2 0_0402_5%

2

0_0402_5%

D

Vaxg

(5) RUN_ON_CPU1.5VS3#

Ʉ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
Ʉ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

D

S

2011/07/12

2

D
2
G
S

RUN_ON_CPU1.5VS3#

Q7
2N7002K_SOT23-3

D

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

C60
0.1U_0402_10V6K
@

RUN_ON_CPU1.5VS3#

Compal Secret Data

Security Classification
Issued Date

Q12
2
G
@

C61

2

@

1

@
S
3

1

2

0.047U_0603_25V7K

R84

R85

330K_0402_5%

SUSP#

2
G

2N7002K_SOT23-3

(24,41,42,46,48,50,51)

2 0_0402_5%

1

2N7002K_SOT23-3

(41) CPU1.5V_S3_GATE

R83

1

SUSP

3

(24,42,50,51)

1

15K_0402_5%

1

D

2

220_0402_5%

RUN_ON_CPU1.5VS3
Q11

R201

2

2

1

1

1

3

SA RAIL
MISC

1
1

2

SENSE
LINES
VREF
DDR3 -1.5V RAILS

GRAPHICS

+

@ JP1

(6)

330U_D2_2V_Y

1.8V RAIL

1

IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0

2

D

+1.5V_CPU_VDDQ

@ R74
100_0402_5%

RUN_ON_CPU1.5VS3

Sandy Bridge is NC for A19
VCCP_PWRCTRL:1

1

DRAMRST_CNTRL

from 1PCS 2N7002 dual channel change to BSS138 2pCS

+3VS

TYCO_2013620-2_IVY BRIDGE

1

G

2

330U_D2_2V_Y

C46

2

10U_0603_6.3V6M

1

C52

A19

C45

VCCIO_SEL

2

10U_0603_6.3V6M

C22
C24

+VREF_DQ_DIMMB

+VCCSA

R75
VCCSA_VID[0]
VCCSA_VID[1]

1

10U_0603_6.3V6M

H23

2

C51

VCCSA_SENSE

1

10U_0603_6.3V6M

M27
M26
L26
J26
J25
J24
H26
H25

2

C50

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

2

1

C44

2

1

10U_0603_6.3V6M

1

10U_0603_6.3V6M

6A

2

0.1U_0402_16V4Z

@

@ R69
100_0402_5%

2 0_0402_5%
+V_SM_VREF
1
Q4
AP2302GN-HF_SOT23-3
@

1
C43

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

3

R108
1K_0402_1%
@

+1.5V

10U_0603_6.3V6M

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

@

1

+1.5V_CPU_VDDQ

10A

A

2 0_0402_5%

Q6
BSS138_NL_SOT23-3

3
1

R72
1K_0402_5%

+V_DDR_REFA_R
+V_DDR_REFB_R

B4
D1

@

1

+V_DDR_REFB_R

R70

C39

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

C49

2

+V_SM_VREF_CNT

C42

+
@

VCCPLL1
VCCPLL2
VCCPLL3

AL1

10U_0603_6.3V6M

1

330U_D2_2V_Y

2

C59

1

1U_0402_6.3V6K

2

C58

1

1U_0402_6.3V6K

C57

2

10U_0603_6.3V6M

C56

1

B6
A6
A2

SM_VREF

10U_0603_6.3V6M

2 0_0805_5%

R71

+1.5V

R68
1K_0402_5%

C48

1.5A
1

(52)

+1.5V_CPU_VDDQ

C41

R76

(52)

VSS_AXG_SENSE

+V_SM_VREF should
have 10 mil trace width

R66
10_0402_1%

AK35
AK34

10U_0603_6.3V6M

+1.8VS_VCCPLL

+1.8VS
C

VAXG_SENSE
VSSAXG_SENSE

C40

B

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCC_AXG_SENSE

S

33A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

2 100_0402_1%

2

CONN@

@

1

2

JCPU1G

R73

POWER

1

+VCC_GFXCORE_AXG

1

A

4

Compal Electronics, Inc.
PROCESSOR(6/7)
PWR
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
9
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

A

A

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

B

C

JCPU1H

CONN@

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

VSS

JCPU1I
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

TYCO_2013620-2_IVY BRIDGE

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

CONN@

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

B

C

TYCO_2013620-2_IVY BRIDGE

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PROCESSOR(7/7)
VSS
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
10
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
+1.5V

DDR_A_D[0..63]

(6)
(6)

1

DDR_A_MA[0..15]

(6)
(6)

R2001
1K_0402_1%

DDR_A_D2
DDR_A_D3

1

DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 (6)
M_CLK_DDR#1 (6)

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 (6)
DDR_A_RAS# (6)

DDR_CS0_DIMMA#
M_ODT0

DDR_CS0_DIMMA#
M_ODT0 (6)

M_ODT1

M_ODT1 (6)

+0.75VS

+1.5V

(6)

1

R2004
1K_0402_1%

2

1
2

1
2

1
2

Layout Note:
Place near
JDIMM1.203,204

+VREF_CA
DDR_A_D36
DDR_A_D37

1
2

DDR_A_D38
DDR_A_D39

1
2

C

R2005
1K_0402_1%

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3

SMB_DATA_S3 (12,14,38,39)
SMB_CLK_S3 (12,14,38,39)
+0.75VS

D

TYCO_2-2013310-1
CONN@

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

2

DDR_A_MA6
DDR_A_MA4

@

1

+
@

DDR_A_MA11
DDR_A_MA7

2

1
2

206

1

330U_D2_2V_Y

G2

G1

2

C2014

205

1

@

10U_0603_6.3V6M

10K_0402_5%

R2007

10K_0402_5%

2

R2006

1

2.2U_0603_6.3V6K

2

C2022

1

0.1U_0402_16V4Z

2

C2046

1

0.1U_0402_16V4Z

DIMM_A Reserve H:4.0mm

C2021



C2013

+0.75VS

2

10U_0603_6.3V6M

+3VS

D

1

(6)

1U_0402_6.3V6K

DDR_A_D58
DDR_A_D59

2

C2012

DDR_A_D56
DDR_A_D57

1

C2020

DDR_A_D50
DDR_A_D51

2

10U_0603_6.3V6M

DDR_A_DQS#6
DDR_A_DQS6

1

C2011

DDR_A_D48
DDR_A_D49

2

1U_0402_6.3V6K

DDR_A_D42
DDR_A_D43

DDR_CKE1_DIMMA

0.1U_0402_16V4Z

DDR_A_D40
DDR_A_D41

1

DDR_A_MA15
DDR_A_MA14

C2016

DDR_A_D34
DDR_A_D35

DDR_CKE1_DIMMA

2.2U_0603_6.3V6K

DDR_A_DQS#4
DDR_A_DQS4

2

B

C2015

DDR_A_D32
DDR_A_D33

C

DDR_A_D30
DDR_A_D31

1

10U_0603_6.3V6M

(6) DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

2

C2019

DDR_A_WE#
DDR_A_CAS#

1

DDR_A_DQS#3
DDR_A_DQS3

1U_0402_6.3V6K

(6) DDR_A_WE#
(6) DDR_A_CAS#

DDR_A_D28
DDR_A_D29

C2018

(6) DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

+1.5V
DDR_A_D22
DDR_A_D23

1U_0402_6.3V6K

M_CLK_DDR0
M_CLK_DDR#0

2

DDR_A_D20
DDR_A_D21

C2017

(6) M_CLK_DDR0
(6) M_CLK_DDR#0

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1

0.1U_0402_10V6K

DDR_A_MA3
DDR_A_MA1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

C2010

DDR_A_MA8
DDR_A_MA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

C2006

DDR_A_MA12
DDR_A_MA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2

10U_0603_6.3V6M

DDR_A_BS2

2

1

0.1U_0402_10V6K

DDR_CKE0_DIMMA

(6) DDR_A_BS2

2

DDR_A_D14
DDR_A_D15

1

C2009

(6) DDR_CKE0_DIMMA

(6,12)

C2008

DDR_A_D26
DDR_A_D27

B

DDR3_DRAMRST#

10U_0603_6.3V6M

DDR_A_D24
DDR_A_D25

1

DDR3_DRAMRST#

C2007

DDR_A_D18
DDR_A_D19

DDR_A_D12
DDR_A_D13

10U_0603_6.3V6M

DDR_A_DQS#2
DDR_A_DQS2

+1.5V

DDR_A_D6
DDR_A_D7
C2005

DDR_A_D16
DDR_A_D17

DDR_A_DQS#0
DDR_A_DQS0

0.1U_0402_10V6K

DDR_A_D10
DDR_A_D11

A

Layout Note:
Place near
JDIMM1

DDR_A_D4
DDR_A_D5

C2004

All VREF traces should
have 10 mil trace width

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

0.1U_0402_10V6K

DDR_A_DQS#1
DDR_A_DQS1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C2003

DDR_A_D8
DDR_A_D9

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

2

JDIMM1

2

1
2

1

0.1U_0402_16V4Z

2

C2002

1

2.2U_0603_6.3V6K

C2001

R2003
1K_0402_1%

DDR_A_D0
DDR_A_D1

+1.5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

+VREF_DQ_DIMMA

+VREF_DQ_DIMMA

2

+1.5V

2

A

3

4

Compal Electronics, Inc.
DDRIII
DIMMA
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
11
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

DDR_B_DQS#[0..7]

+1.5V

(6)
(6)

1

DDR_B_DQS[0..7]
DDR_B_D[0..63]

R2008
1K_0402_1%

2

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9

1
2

1

1
+

@

2

330U_D2_2V_Y

206

2

C2036

G2

1

@

10U_0603_6.3V6M

G1

2

C2035

B

M_CLK_DDR3 (6)
M_CLK_DDR#3 (6)

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 (6)
DDR_B_RAS# (6)

DDR_CS2_DIMMB#
M_ODT2

DDR_CS2_DIMMB#
M_ODT2 (6)

M_ODT3

M_ODT3 (6)

+1.5V

+0.75VS

R2011
1K_0402_1%

(6)

1

+VREF_CB
DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

2

1

1
2

2

1
2

1
2

1
2

1
2

@

C

R2012
1K_0402_1%

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3

SMB_DATA_S3 (11,14,38,39)
SMB_CLK_S3 (11,14,38,39)
+0.75VS

D

FOX_AS0A626-U2SN-7F
CONN@

2

R2014
10K_0402_5%

205

1

10U_0603_6.3V6M

+0.75VS

M_CLK_DDR3
M_CLK_DDR#3

1U_0402_6.3V6K

DDR_B_D58
DDR_B_D59

C2034

DDR_B_D56
DDR_B_D57

C2045

2

DDR_B_D50
DDR_B_D51

2

10U_0603_6.3V6M

1

2.2U_0603_6.3V6K

2

C2044

1

0.1U_0402_16V4Z

D

C2043

R2013
10K_0402_5%

+3VS

1U_0402_6.3V6K

+3VS

DDR_B_DQS#6
DDR_B_DQS6

C2033

DDR_B_D48
DDR_B_D49

1

Layout Note:
Place near
JDIMM2.203,204

DDR_B_MA2
DDR_B_MA0

C2042

DDR_B_D42
DDR_B_D43

10U_0603_6.3V6M

DDR_B_D40
DDR_B_D41

2

(6)

0.1U_0402_16V4Z

DDR_B_D34
DDR_B_D35

1

DDR_B_MA6
DDR_B_MA4

C2038

DDR_B_DQS#4
DDR_B_DQS4

2

DDR_B_MA11
DDR_B_MA7

2.2U_0603_6.3V6K

C

1

DDR_B_MA15
DDR_B_MA14

C2037

DDR_B_D32
DDR_B_D33

DDR_CKE3_DIMMB

2

1U_0402_6.3V6K

(6) DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_CKE3_DIMMB

1

C2041

DDR_B_WE#
DDR_B_CAS#

2

1U_0402_6.3V6K

(6) DDR_B_WE#
(6) DDR_B_CAS#

1

DDR_B_D30
DDR_B_D31

C2040

(6) DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

DDR_B_DQS#3
DDR_B_DQS3

1U_0402_6.3V6K

M_CLK_DDR2
M_CLK_DDR#2

2

+1.5V

DDR_B_D28
DDR_B_D29

C2039

(6) M_CLK_DDR2
(6) M_CLK_DDR#2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1

0.1U_0402_10V6K

DDR_B_MA3
DDR_B_MA1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2

C2032

DDR_B_MA8
DDR_B_MA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_D22
DDR_B_D23

2

1

C2028

DDR_B_MA12
DDR_B_MA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2

DDR_B_D20
DDR_B_D21

1

10U_0603_6.3V6M

DDR_B_BS2

1

(6,11)

0.1U_0402_10V6K

DDR_CKE2_DIMMB

(6) DDR_B_BS2

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

C2031

(6) DDR_CKE2_DIMMB

DDR3_DRAMRST#

C2027

B

+1.5V

DDR_B_D12
DDR_B_D13

10U_0603_6.3V6M

DDR_B_D26
DDR_B_D27

Layout Note:
Place near
JDIMM2

DDR_B_D6
DDR_B_D7

C2029

DDR_B_D24
DDR_B_D25

DDR_B_DQS#0
DDR_B_DQS0

0.1U_0402_10V6K

DDR_B_D18
DDR_B_D19

A

DDR_B_D4
DDR_B_D5

C2030

DDR_B_DQS#2
DDR_B_DQS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C2026

DDR_B_D16
DDR_B_D17

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

10U_0603_6.3V6M

All VREF traces should
have 10 mil trace width

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

0.1U_0402_10V6K

DDR_B_D10
DDR_B_D11

JDIMM2

C2025

DDR_B_DQS#1
DDR_B_DQS1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

1
2

1

0.1U_0402_16V4Z

C2023

2

2.2U_0603_6.3V6K

C2024

1

R2010
1K_0402_1%

DDR_B_D0
DDR_B_D1

2

+VREF_DQ_DIMMB

+VREF_DQ_DIMMB

(6)

+1.5V

1

+1.5V

2

2
A

(6)

DDR_B_MA[0..15]

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
DDRIII
DIMMB
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
12
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

PCH_RTCX1
2 10M_0402_5%

1

W=20mils

PCH_RTCX2

W=20mils

+RTCVCC

+RTCBATT

Y1
2

18P_0402_50V8J

32.768KHZ_12.5PF_CM31532768DZFT
1
C64
18P_0402_50V8J
C63
11/14

2

1

2

1

1
1

R106
1K_0402_5%
1
2
C179
1U_0402_6.3V6K

CLRP1
SHORT PADS

2

R87

2

CMOS
A

PCH_RTCRST#

D20

RTCRST#

2 20K_0402_5%

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

2

(INTVRMEN should always be pull high.)

@

ME

+3VS

*

@

1

2 1K_0402_5%

(35) HDA_SPKR

HDA_SPKR

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

(35) HDA_SDIN0

HDA_BIT_CLK

N34

HDA_SYNC

L34

HDA_SYNC

P-

HDA_SPKR

T10

SPKR

P-

HDA_RST#

K34

HDA_RST#

HDA_SDIN0

E34

HDA_SDIN0

P-

G34

HDA_SDIN1

P-

C34

HDA_SDIN2

P-

+3V_PCH

+3VS
R95

@

1

2 1K_0402_5%

(41) ME_FLASH

HDA_SDOUT
2 10K_0402_5% WLBT_OFF_5#

R202 1

A34

HDA_SDIN3

P-

A36

HDA_SDO

P-

WLBT_OFF_5#

C36

HDA_DOCK_EN# / GPIO33

2 10K_0402_5%

PCH_GPIO13

N32

HDA_DOCK_RST# / GPIO13

2 51_0402_5%

PCH_JTAG_TCK

J3

JTAG_TCK

P-

PCH_JTAG_TMS

H7

JTAG_TMS

P+

2 0_0402_5%

1

(38) WLBT_OFF_5#

9/27

HDA_SDO

*

R94

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R209 1

R96

1

@

PCH_JTAG_TDI

K5

JTAG_TDI

PCH_JTAG_TDO

H1

JTAG_TDO

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4 / LFRAME#

D36

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

E36
K36

SERIRQ

HDA_BCLK

HDA_SDOUT

B

P+
P+

C38
A38
B37
C37

P+ FWH0 / LAD0
P+ FWH1 / LAD1
P+ FWH2 / LAD2
P+ FWH3 / LAD3

P+

2 1K_0402_5%

1

SPI_CLK_PCH_R

This signal has a weak internal pull-down

*

On Die PLL VR Select is supplied by
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

Prevent back drive issue.

T3
Y14

SPI_CS0#

SPI_SB_CS1#

T1

SPI_CS1#

HDA_BIT_CLK

(35) HDA_SYNC_AUDIO

1

R241
33_0402_5%
2

HDA_SYNC_R

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

Y3
Y1
AB3
AB1

SATAICOMPO

Y11

C69
C70

SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_P2

C71
C72

SATA_DTX_C_PRX_N0 (36)
SATA_DTX_C_PRX_P0 (36)
SATA_PTX_DRX_N0 (36)
SATA_PTX_DRX_P0 (36)

HDD

1
1

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
2 0.01U_0402_16V7K SATA_PTX_DRX_N1
2 0.01U_0402_16V7K SATA_PTX_DRX_P1

SATA_DTX_C_PRX_N1 (36)
SATA_DTX_C_PRX_P1 (36)
SATA_PTX_DRX_N1 (36)
SATA_PTX_DRX_P1 (36)

ODD

1
1

SATA_DTX_C_PRX_N2
SATA_DTX_C_PRX_P2
2 0.01U_0402_16V7K SATA_PTX_DRX_N2
2 0.01U_0402_16V7K SATA_PTX_DRX_P2

SATA_DTX_C_PRX_N2 (38)
SATA_DTX_C_PRX_P2 (38)
SATA_PTX_DRX_N2 (38)
SATA_PTX_DRX_P2 (38)

m-SATA

B

+1.05VS_PCH

Y10

SATA_COMP

R97

1

2 37.4_0402_1%

AB12
SATA3_COMP

R98

1

2 49.9_0402_1%

SATA3RBIAS

AH1

RBIAS_SATA3

R100 1

2 750_0402_1%

P3

PCH_SATALED#

R101 1

2 10K_0402_5%

V4

SPI_MOSI

P-

SPI_SO_R

U3

SPI_MISO

P+

SATA0GP / GPIO21

V14

PCH_GPIO21

R102 1

2 10K_0402_5%

SATA1GP / GPIO19

P1

ODD_DET#

R103 1

2 10K_0402_5%

SATALED#

P+

0%0%63,520)2500( 6%$
1RQVKDUH520

G

HDA_SYNC

ODD_DET#

R110 1

1

9/22
@

R112 1 SBA@

R303
1M_0402_5%

SPI_SB_CS1#
SPI_SO_R

R336 1
R343 1

2 0_0402_5%
2 33_0402_5%

HDA_SDOUT

CS1#
SPI_SO1
SPI_WP#1

1
2
3
4

+3VS

1

2 22P_0402_50V8J

HDA_BITCLK_AUDIO

C77 @1

2 22P_0402_50V8J

HDA_SDOUT_AUDIO

U6 4M

U6

+3VS_SPI
8
7
6
5

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

SPI_HOLD#1
SPI_CLK1 R339 1
SPI_SI1
R338 1

C191 1
SPI_SB_CS0#
SPI_SO_R

+3V_PCH

2 33_0402_5%
2 33_0402_5%

SPI_CLK_PCH_R
SPI_SI

R340 1
R337 1

2 0_0402_5%
2 33_0402_5%

+3V_PCH

CS#
SPI_SO_L
SPI_WP#

1
2
3
4

U5

2 0.1U_0402_16V4Z

U5 8M

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DI

8
7
6
5

SPI_HOLD#
SPI_CLK_PCH
SPI_SI_R

W25Q32BVSSIG_SO8

1
1

R342
R341

33_0402_5%
2
2
33_0402_5%

SPI_CLK_PCH_R
SPI_SI

2

PCH_JTAG_TDI

2

3.3K_0402_5%

SPI_HOLD#1

R105

1

2

3.3K_0402_5%

SPI_WP#

R334

1

2

3.3K_0402_5%

SPI_HOLD#

R335

1

2

3.3K_0402_5%

SPI_CLK_PCH_R

R119

1

@

2 33_0402_5%

C78 @1

2 22P_0402_50V8J

SPI_CLK_PCH_R

C84

1

2 22P_0402_50V8J

C85

1

2 22P_0402_50V8J

Compal Secret Data

Security Classification

R125 @
100_0402_1%

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

D

S IC FL 64M EN25Q64-104HIP SOP 8P
S IC FL 32M EN25Q32B-104HIP SOP 8P

2
1

1

Reserve for RF please close to U5, U6

1

2
1

EON
8M:SA000046400
4M:SA00004LI00

R122 @
200_0402_5%

R124 @
100_0402_1%
2

R123 @
100_0402_1%
2

PCH_JTAG_TMS

R104

9/28 RF modify

1

1

1
2
1

PCH_JTAG_TDO

R121 @
200_0402_5%

SPI_WP#1

Reserve for EMI please close to U3

D

R120 @
200_0402_5%

C

if not supply SBA function R110 mount , R112 @
if supply SBA function R110 @,R112 mount

2 0_0402_5%

+3VS_SPI

+3V_PCH

(36)

+3VM

2 0_0402_5%

W25Q16BVSSIG_SO8
C76

+1.05VS_VCC_SATA

+1.05VS_SATA3

+3VS_SPI

Q8
BSS138_NL_SOT23-3

2

HDA_RST#

1

D

3

S

(35) HDA_SDOUT_AUDIO

R111
33_0402_5%
1
2

+5VS
2

(35) HDA_BITCLK_AUDIO

(35) HDA_RST#_AUDIO

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

1
1

PANTHER-POINT_FCBGA989

R107
33_0402_5%
1
2

R109
33_0402_5%
1
2

AD7
AD5
AH5
AH4

C67
C68

(40,41)

+3VS

SPI_SI

C

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0

AB13

SPI_CLK

SPI_SB_CS0#

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SERIRQ

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
2 0.01U_0402_16V7K SATA_PTX_DRX_N0
2 0.01U_0402_16V7K SATA_PTX_DRX_P0

SATA3COMPI

HDA_SYNC

SPI

R99

(38,40,41)

2 10K_0402_5%

1

SATA3RCOMPO

+3V_PCH

(38,40,41)
(38,40,41)
(38,40,41)
(38,40,41)

LPC_FRAME#

R92

SERIRQ

V5

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATAICOMPI

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
+3VS

AM3
AM1
AP7
AP5

SATA 6G

C66
1U_0402_6.3V6K

1

LPC

2 20K_0402_5%

1

JME1
SHORT PADS

1

R89

H烉
烉Integrated VRM enable
L烉
烉Integrated VRM disable

R93

RTCX2

R88

INTVRMEN

*

RTCX1

C20

SATA

PCH_INTVRMEN

A20

PCH_RTCX2

RTC

SM_INTRUDER#

2 330K_0402_5%

PCH_RTCX1

IHDA

2 1M_0402_5%

1

1

1

R91

2

R90

@

U3A

JTAG

2

+RTCVCC

2

1

JCMOS1
SHORT PADS

C62
1U_0402_6.3V6K

+RTCVCC

1

A

3

4

Compal Electronics, Inc.
PCH
(1/9)
SATA,HDA,SPI, LPC
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
13
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

+3V_PCH

U3B

PERN3
PERP3
PETN3
PETP3

BF36
BE36
AY34
BB34

PERN4
PERP4
PETN4
PETP4

BG37
BH37
AY36
BB36

PERN5
PERP5
PETN5
PETP5

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

@
@

2 0_0402_5%
2 0_0402_5%

(38) CLK_PCIE_WLAN1#
(38) CLK_PCIE_WLAN1

Y40
Y39

CARD_CLKREQ#

(36) CARD_CLKREQ#

Wireless LAN

CLK_CARD#
CLK_CARD

R141 1
R142 1

@
@

2 0_0402_5%
2 0_0402_5%

J2

CLK_MINI1#
CLK_MINI1

AB49
AB47

WLAN_CLKREQ1#

(38) WLAN_CLKREQ1#

M1
AA48
AA47

PCIE LAN

(40) CLK_PCIE_LAN#
(40) CLK_PCIE_LAN

R145 1
R146 1

@
@

2 0_0402_5%
2 0_0402_5%

R170 1

2 10K_0402_5%

WLAN_CLKREQ1#

R162 1

2 10K_0402_5%

PCH_GPIO20

+3V_PCH

C

2 10K_0402_5%

CARD_CLKREQ#

R175 1

2 10K_0402_5%

LAN_CLKREQ#

R181 1

2 10K_0402_5%

PCH_GPIO26

R182 1

2 10K_0402_5%

PCH_GPIO44

R159 1

2 10K_0402_5%

PCH_GPIO56

R183 1

2 10K_0402_5%

PCH_GPIO45

2 10K_0402_5%

ON_ODD_DET

R184 1

@

PCH_GPIO56

PCH_GPIO45

ON_ODD_DET

(36) ON_ODD_DET
(5) CLK_XDP_CLK#
(5) CLK_XDP_CLK

R164 1
R165 1

@
@

2 0_0402_5%
2 0_0402_5%

CLK_BCLK_ITP#
CLK_BCLK_ITP

PCH_SML0DATA

SML1ALERT# / PCHHOT# / GPIO74

C13

PCH_HOT#

SML1CLK / GPIO58

E14

PCH_SML1CLK

SML1DATA / GPIO75

M16

PCH_SML1DATA

SMBUS

CLKOUT_PCIE4N
CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45
V46

CLKOUT_PCIE5N
CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

DRAMRST_CNTRL_PCH

T13

PCIECLKRQ6# / GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

2.2K_0402_5%

2

2.2K_0402_5%

PCH_SML0DATA

R131

1

2

2.2K_0402_5%

PCH_SML1CLK

R126

1

2

2.2K_0402_5%

PCH_SML1DATA

R132

1

2

2.2K_0402_5%

PCH_HOT#

R133

1

2

10K_0402_5%

PCH_GPIO11

R135

1

2

10K_0402_5%

DRAMRST_CNTRL_PCH

R127

1

2

1K_0402_5%

PCH_GPIO47

R138

1

2

10K_0402_5%

CL_CLK1
CL_DATA1

T11

CL_RST1#

P10

PEG_A_CLKRQ# / GPIO47

M10

R136
1

6

2.2K_0402_5%
2

+3VS

SMB_DATA_S3

1

Q9A

P+/P-

A

+3VS

SMB_DATA_S3 (11,12,38,39)

2N7002KDWH_SOT363-6

PCH_SMBCLK

R137
1

3
Q9B

P+

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

AB37
AB38

CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

PCH_GPIO47

R139
R140

1 DIS@
@
1

2 0_0402_5%
2 10K_0402_5%

GPU_CLKREQA

R144
R151

1 DIS@
1 DIS@

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA# (22)
CLK_PCIE_VGA (22)

2.2K_0402_5%
2

DDR, WALN, WWAN
+3VS

SMB_CLK_S3

4

SMB_CLK_S3

(11,12,38,39)

2N7002KDWH_SOT363-6

Pull up at EC side.

(22)

B

PCH_SML1DATA

6

CLK_CPU_DMI# (5)
CLK_CPU_DMI (5)
PCH_SML1CLK

EC_SMB_DA2

(22,39,41)

CLKOUT_DP_N
CLKOUT_DP_P

AM12
AM13

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

R148
R150

1
1

2
2

10K_0402_5%
10K_0402_5%

CLKIN_GND1_N
CLKIN_GND1_P

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

R152
R153

1
1

2
2

10K_0402_5%
10K_0402_5%

CLKIN_DOT_96N
CLKIN_DOT_96P

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R154
R155

1
1

2
2

10K_0402_5%
10K_0402_5%

CLKIN_SATA_N
CLKIN_SATA_P

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

R156
R157

1
1

2
2

10K_0402_5%
10K_0402_5%

REFCLK14IN

K45

CLK_BUF_ICH_14M

R158

1

2

10K_0402_5%

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

Y47

XCLK_RCOMP

EC, VGA, Theraml
4EC_SMB_CK2

3

EC_SMB_CK2

(22,39,41)

Q10B 2N7002KDWH_SOT363-6

CLK_BUF_ICH_14M

R168
1

33_0402_5%
@
2

C89
22P_0402_50V8J
@ 1
2

CLK_PCI_LPBACK

R169
1

33_0402_5%
@
2

C90
22P_0402_50V8J
@ 1
2

Reserve for EMI please close to U60

CLK_PCI_LPBACK

XTAL25_IN

(17)

XTAL25_OUT

R161 1

R160 1

1

2 90.9_0402_1%

1
C87
18P_0402_50V8J

P-

CLKOUTFLEX0 / GPIO64

K43

PCH_GPIO64

P-

CLKOUTFLEX1 / GPIO65

F47

PCH_GPIO65

P-

CLKOUTFLEX2 / GPIO66

H47

LAN_25M

P-

CLKOUTFLEX3 / GPIO67

K49

PCH_GPIO67

R163 1

@

2 22_0402_5%

2 1M_0402_5%

C

Y2
25MHZ_20PF_ X3G025000DK1H

+1.05VS_PCH
+1.05VS_VCCDIFFCLKN

P+

EC_SMB_DA2

1

Q10A 2N7002KDWH_SOT363-6

CLK_CPU_DMI#
CLK_CPU_DMI

PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P

(6)

2

1

M7

P+/P-

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

V40
V42

AK14
AK13

G12

SML0CLK

PCIECLKRQ3# / GPIO25

Y43
Y45

E6

SML0DATA

CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

AB42
AB40

PCH_SML0CLK

PCIECLKRQ1# / GPIO18

Y37
Y36

PCH_GPIO44

R177 1

C8

SML0ALERT# / GPIO60

1

R130

+3VS

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLK_LAN#
CLK_LAN

PCH_GPIO26

DRAMRST_CNTRL_PCH

R129

PCH_SML0CLK

PCH_SMBDATA

PCIECLKRQ0# / GPIO73

PCIECLKRQ2# / GPIO20

+3VS

A12

CLKOUT_PCIE0N
CLKOUT_PCIE0P

V10

A8

PCH_SMBDATA

SMBDATA

PCH_GPIO20

LAN_CLKREQ#

(40) LAN_CLKREQ#

C9

PCH_SMBDATA

5

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCH_SMBCLK

2.2K_0402_5%

2

BG36
BJ36
AV34
AU34

SMBCLK

H14

2

5

R147 1
R149 1

PERN2
PERP2
PETN2
PETP2

PCH_GPIO11

Link

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

BE34
BF34
BB32
AY32

E12

1

2

(36) CLK_PCIE_CARD#
(36) CLK_PCIE_CARD

C80
C81

1
1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

SMBALERT# / GPIO11

R128

PCH_LAN_25M
PCH_GPIO67

1

GND

GND

2

4

2

3

3
1
2

11/14

C88
18P_0402_50V8J

(40)
+3VS

(18)

+3VS

1

Card Reader

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

C82
C83

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PERN1
PERP1
PETN1
PETP1

Controller

(40)
(40)
(40)
(40)

PCIE LAN

B

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

1
1

BG34
BJ34
AV32
AU32

FLEX CLOCKS

A

(38)
(38)
(38)
(38)

C86
C79

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

CLOCKS

Wireless LAN

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

PCI-E*

Card Reader

(36)
(36)
(36)
(36)

PCH_SMBCLK

PANTHER-POINT_FCBGA989

2

R172
10K_0402_5%
@

(5,17,22,36,38,40,41)

PLT_RST#

PLT_RST#

1
2
3
4

U8
NC
NC
PROT#
GND

VCC
WP
SCL
SDA

8
7
6
5

PCA24S08D_SO8
EEPROM SA00004MK00
EEPROM SA00004ML00

ROM_WP

SMB_CLK_S3
SMB_DATA_S3

1

C91
0.1U_0402_16V4Z

2

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(2/8)
PCIE, SMBUS, CLK
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
14
58
of
Sheet
Date:
Title

5

Rev
0.6

1

2

3

4

5

U3C
BC24
BE20
BG18
BG20

A

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

(4)
(4)
(4)
(4)

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

(4)
(4)
(4)
(4)

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

(4)
(4)
(4)
(4)

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BJ24

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

BC10

FDI_FSYNC1

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DSWODVREN

DPWROK

E22

PCH_DPWROK_R

R189 1

@

2 0_0402_5%

B9

WAKE#

R194 1

@

2 0_0402_5%

+1.05VS_PCH

+1.05VS_VCC_EXP

R186 1

2 49.9_0402_1% DMI_IRCOMP

BG25

R188 1

2 750_0402_1% RBIAS_CPY

BH21

FDI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

(4)
(4)
(4)
(4)

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

AW16

FDI_INT

AV12

FDI_FSYNC0

FDI_INT

DMI2RBIAS

4mil width and place
within 500mil of the PCH

FDI_INT

A

(4)

FDI_FSYNC0

(4)

FDI_FSYNC1

(4)

FDI_LSYNC0

(4)

FDI_LSYNC1

(4)

SUSACK#_R

T8
B

R193 1

(5) XDP_DBRESET#

(41) PCH_PWROK
(41) PCH_APWROK

PCH_PWROK

R197 1
R198 1

@

@

R200 1

2 0_0402_5%

R203 1

@

D3

1

SYS_RESET#

P12

PCH_POK_R

L22

PWROK

2 0_0402_5%

APWROK

L10

APWROK

PM_DRAM_PWRGD

B13

DRAMPWROK

PCH_RSMRST#_R

C21

RSMRST#

2 0_0402_5%

SUSWARN#

ACIN

P+

SYS_PWROK

SYS_PWROK

WAKE#
CLKRUN# / GPIO32

N3

SUS_STAT# / GPIO61

G8

PM_CLKRUN#

(40)

SLP_S5# / GPIO63

PM_SLP_S5#

T11
PM_SLP_S5# (41)

H4

PM_SLP_S4#

T12
PM_SLP_S4# (41)
T13
PM_SLP_S3# (41)

SLP_S4#

H20

ACPRESENT / GPIO31

PCH_GPIO72

E10

BATLOW# / GPIO72 P+

RI#

A10

RI#

SUSCLK

F4

PM_SLP_S3#

G10

PCH_SLPA#

SLP_SUS#

G16

PM_SLP_SUS#

T14
PM_SLP_SUS#

PMSYNCH

AP14

H_PM_SYNC

T15
H_PM_SYNC

K14

PCH_GPIO29

SLP_LAN# / GPIO29

1

R187

1

2 330K_0402_5%
@

2 330K_0402_5%

PCH_SLPA#

B

DSWODVREN - On Die DSW VR Enable
H烉Enable
L烉Disable

(41)

SLP_A#

SLP_S3#

*

R185

+3V_PCH

SUSCLK

PWRBTN#

P-

(40)

D10

SUSWARN#/SUSPWRDNACK/GPIO30

AC_PRESENT_R
2
RB751V-40_SOD323-2

PM_CLKRUN#

PCIE_WAKE#

N14

E20

P+

DSWODVREN

PCH_RSMRST#_R

SUSCLK / GPIO62

K16

(5,41) PBTN_OUT#
(40,41,44)

K3

SUSACK#

2 0_0402_5%
2 0_0402_5%

(5) PM_DRAM_PWRGD
(41) EC_RSMRST#

XDP_DBRESET#_R

C12

System Power Management

+RTCVCC

WAKE#

R192

1

2 10K_0402_5%

PCH_GPIO29

R195

1

PM_CLKRUN#

R196

1

2 8.2K_0402_5%

R199

1 @

2 10K_0402_5%

@

2 10K_0402_5%
+3VS

(41)

EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)
Use CLKRUN# Requires a 8.2- k weak
pull-up resistor to Vcc3_3S

(41)

(5)

Can be left NC when
IAMT is not support on
the platfrom

PANTHER-POINT_FCBGA989
C

C

+3VS

PM_DRAM_PWRGD

PCH_PWROK
(52) VGATE

1

IN1

2

IN2

4

SYS_PWROK

SYS_PWROK

(5)

2 200_0402_5%

PM_DRAM_PWRGD

R205 1

@

2 10K_0402_5%

SUSWARN#

R206 1

2 200K_0402_5%

AC_PRESENT_R

R207 1

2 10K_0402_5%

PCH_GPIO72

R208 1

2 10K_0402_5%

RI#

R210 1

2 10K_0402_5%

PCH_RSMRST#_R

MC74VHC1G08DFT2G_SC70-5

R211
100K_0402_5%
D

2

R305 1
D

OUT

1

+3V_PCH

VCC

2 200_0402_5%

GND

@

3

R204 1

5

U9

+3VS

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(3/8)
DMI,FDI,PM,
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
15
58
of
Sheet
Date:
Title

5

Rev
0.6

1

2

3

4

5

A

A

2 R252

+3VS
R218

1

2 2.2K_0402_5%

CRT_DDC_CLK

R219

1

2 2.2K_0402_5%

CRT_DDC_DATA

1

2 150_0402_1%

DAC_BLU

R221

1

2 150_0402_1%

DAC_GRN

R222

1

2 150_0402_1%

DAC_RED

U3D

J47
M45

L_BKLTEN
L_VDD_EN

PP-

SDVO_TVCLKINN
SDVO_TVCLKINP

AP43
AP45

(32) PCH_PWM

P45

L_BKLTCTL
L_DDC_CLK
L_DDC_DATA

SDVO_STALLN
SDVO_STALLP

AM42
AM40

(32) EDID_CLK
(32) EDID_DATA

T40
K47

PP-

T45
P39

PP-

SDVO_INTN
SDVO_INTP

AP39
AP40

L_CTRL_CLK
L_CTRL_DATA

2.2K_0402_5%
2.2K_0402_5%

1

P-

1
1

2 R212
2 R213

CTRL_CLK
CTRL_DATA

2.37K_0402_1% 1

2 R215

LVDS_IBG

AF37
AF36

LVD_IBG
LVD_VBG

LVD_VREF

AE48
AE47

LVD_VREFH
LVD_VREFL

(32) LVDS_ACLK#
(32) LVDS_ACLK

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

(32) LVDS_A0#
(32) LVDS_A1#
(32) LVDS_A2#

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

(32) LVDS_A0
(32) LVDS_A1
(32) LVDS_A2

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

(32) LVDS_BCLK#
(32) LVDS_BCLK

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

(32) LVDS_B0#
(32) LVDS_B1#
(32) LVDS_B2#

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

(32) LVDS_B0
(32) LVDS_B1
(32) LVDS_B2

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

2 R217

1

(33) DAC_BLU
(33) DAC_GRN
(33) DAC_RED
(33) CRT_DDC_CLK
(33) CRT_DDC_DATA

R220

PCH_ENBKL

(32) PCH_ENVDD

0_0402_5%

B

C

2 R253

0_0402_5%

(33) CRT_HSYNC
(33) CRT_VSYNC
1K_0402_0.5%

1

2 R223

DAC_BLU
DAC_GRN
DAC_RED

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

M47
M49

CRT_HSYNC
CRT_VSYNC

CRT_IREF

T43
T42

DAC_IREF
CRT_IRTN

P38
M39

HDMICLK_NB
HDMIDAT_NB

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

AT49
AT47
AT40

PCH_DPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

SDVO_CTRLCLK
P- SDVO_CTRLDATA

Digital Display Interface

+3VS

100K_0402_5% 1

LVDS

ENBKL

DDPC_CTRLCLK
P- DDPC_CTRLDATA

(34)
(34)
B

(34)
(34)
(34)
(34)
(34)
(34)
(34)
(34)
(34)

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

P46
P42

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DDPD_CTRLCLK
P- DDPD_CTRLDATA

CRT

(41)

M43
M36

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

C

PANTHER-POINT_FCBGA989

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(4/9)
LVDS,CRT,DP,HDMI
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
16
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

+3VS

8.2K_8P4R_5%

A

1
2
3
4

R228

PCH_GPIO52
PCH_GPIO5
PCH_GPIO51
PCH_GPIO53

8
7
6
5

8.2K_8P4R_5%
1
2
3
4

R227

ODD_DA#
PCH_GPIO4
PCH_GPIO2

8
7
6
5

8.2K_8P4R_5%
R230 1

2 8.2K_0402_5%

PCH_GPIO55

R231 1

2 8.2K_0402_5%

PCH_GPIO50

R246 1

2 8.2K_0402_5%

PCH_GPIO54

@

2 8.2K_0402_5%

PCH_GPIO54

R232 1

@

2 8.2K_0402_5%

PCH_GPIO50

R234 1

@

2 100K_0402_5%

PCH_PLTRST#

(37) USB3_RX1_P
(37) USB3_RX2_P
(37) USB3_RX3_P
(37) USB3_TX1_N
(37) USB3_TX2_N
(37) USB3_TX3_N
(37) USB3_TX1_P
(37) USB3_TX2_P
(37) USB3_TX3_P

B

R243 1

@

2 1K_0402_5%

PCH_GPIO51

Boot BIOS Strap bit1 BBS1
GPIO51 GPIO19
Bit11 Bit10
0

1

1

0

1

1

0

0

Boot BIOS
Destination

*

SPI (Default)

R254 1 DIS@
R348 1 DIS@
R264 1 DIS@

(22) DGPU_HOLD_RST#
(51) NVDD_PWR_EN
(22,24) DGPU_PWR_EN

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

R332 1

(38) BT_DET#
(36) ODD_DA#

@

2 0_0402_5%

C

2 1K_0402_5%

A16 swap overide Strap/Top-Block
Swap Override jumper

(14)
(41)
(38,40)
(40)

CLK_PCI_LPBACK
CLK_PCI_EC
CLK_PCI_DB
CLK_PCI_TPM

CLK_PCI_EC

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *

R248
R249
R250
R350

1
1
1
1

TPM@

2
2
2
2

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K10

PME#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3

H49
H43
J48
K42
H40

AY7
AV7
AU3
BG4

RSVD5
RSVD6

AT10
BC8

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

RSVD25

AT8

RSVD26
RSVD27

AY5
BA2

RSVD28
RSVD29

AT12
BF3

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USBRBIAS#

C33

P-

C46
C44
E40

C6

RSVD1
RSVD2
RSVD3
RSVD4

5

A

PCH HM65 config not support USB port 6 & 7.

PCH_GPIO50
PCH_GPIO52
PCH_GPIO54

PCH_PLTRST#

PCH_GPIO55

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4

PIRQA#
PIRQB#
PIRQC#
PIRQD#

LPC
(5) PCH_PLTRST#

@

TP21
TP22
TP23
TP24

K40
K38
H38
G38

(41) PCI_PME#

R245 1

B21
M20
AY16
BG46

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

Reserved
PCI

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

(37) USB3_RX1_N
(37) USB3_RX2_N
(37) USB3_RX3_N
R244 1

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

USB

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQA#

8
7
6
5

RSVD

U3E

R225

PCI

1
2
3
4

4

P+
P+
P+

USBRBIAS

B33

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

P+

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

PPPPP-

USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N1 (37)
USB20_P1 (37)
USB20_N2 (37)
USB20_P2 (37)
USB20_N3 (37)
USB20_P3 (37)

USB 3.0
USB 3.0
USB 3.0
B

USB20_N5
USB20_P5

USB20_N5 (32)
USB20_P5 (32)

USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
USBRBIAS

USB20_N9 (39)
USB20_P9 (39)
USB20_N10 (38)
USB20_P10 (38)
USB20_N11 (40)
USB20_P11 (40)
USB20_N12 (38)
USB20_P12 (38)
USB20_N13 (38)
USB20_P13 (38)

CMOS Camera (LVDS)

USB 2.0
Mini Card(WLAN/BT)
FingerPrint
Mini Card(WWAN)
Bluetooth Module

OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2

Within 500 mils22.6_0402_1%

R247 1

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

+3V_PCH

2

USB_OC0#
USB_OC1#

(37)
(37)

USB_OC4#

(39)

(To USB S/B)

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

1
2
3
4

USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

1
2
3
4

R233

8
7
6
5

10K_8P4R_5%
R235
8
7
6
5

C

10K_8P4R_5%

PANTHER-POINT_FCBGA989

RF Boris Tsai suggests

10P_0402_50V8J

1

2 C119

CLK_PCI_TPM

1

2 C92

CLK_PCI_LPBACK

1

2 C93

CLK_PCI_EC

R251 1

2 0_0402_5%
+3VS

1

B

P

2

A

Y

4

PLT_RST# (5,14,22,36,38,40,41)
R255
100K_0402_5%
2

@
TC7SH08FUF_SSOP5

U11

3

PCH_PLTRST#

G

5

10P_0402_50V8J

@

1

10P_0402_50V8J

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(5/9)
PCI, USB, NVRAM
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
17
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

*

H烉On-Die voltage regulator enable
L烉On-Die PLL Voltage Regulator disable
R265 1

@

2 1K_0402_5%

PCH_GPIO28

+3VS

U3F

@

2 1K_0402_5%

(41) EC_SCI#

EC_SMI#

(41) EC_SMI#
+3VS

EC_WAKE#

R280
R282

1
1

@

2 10K_0402_5%
2 10K_0402_5%

R178 1

@

2 0_0402_5%

WLBT_OFF_51#

R288 1
R290 1

2 10K_0402_5%
2 10K_0402_5%

@

R167 1

(41) EC_WAKE#

2 0_0402_5%

+3VS
R285 1
R284 1

@

2 10K_0402_5%
2 10K_0402_5%

(38) BT_ON#

PCH_GPIO37

(38) 3G_DET#
(38) WLBT_OFF_51#

+3VS

B

R269 1

2 10K_0402_5%

PCH_GPIO0

R270 1

2 10K_0402_5%

PCH_GPIO1

2 10K_0402_5%

PCH_GPIO6

2 10K_0402_5%

EC_SCI#

R275 1

2 10K_0402_5%

PCH_GPIO16

R268 1

2 10K_0402_5%

DGPU_PWROK

R277 1

2 10K_0402_5%

PCH_GPIO22

R346 1

2 10K_0402_5%

BT_ON#

R283 1

2 10K_0402_5%

R287 1

2 10K_0402_5%

R289 1
R291 1

R266 1
R344 1

@

(38) 3G_OFF#

(38) mSATA_PCH

R293 1

(41) mSATA_DETEC#

R294 1

A42

TACH1 / GPIO1

P+

P+

TACH5 / GPIO69

B41

PCH_GPIO69

H36

TACH2 / GPIO6

P+

P+

TACH6 / GPIO70

C41

PCH_GPIO70

EC_SCI#

E38

TACH3 / GPIO7

P+

P+

TACH7 / GPIO71

A40

PCH_GPIO71

EC_SMI#

C10

GPIO8

2 0_0402_5%
2 10K_0402_5%

C4

LAN_PHY_PWR_CTRL / GPIO12

PCH_GPIO15

G2

GPIO15

PCH_GPIO16

U2

SATA4GP / GPIO16

PECI
RCIN#

PCH_GPIO24

E8

GPIO24

PCH_GPIO27

E16

GPIO27

P+

PCH_GPIO28

P8

GPIO28

P+

BT_ON#

K1

STP_PCI# / GPIO34

3G_DET#

K4

GPIO35

WLBT_OFF_51#

V8

SATA2GP / GPIO36

P-

PCH_GPIO37

M5

SATA3GP / GPIO37

P-

PCH_GPIO38

N2

SLOAD / GPIO38

3G_OFF#

M3

SDATAOUT0 / GPIO39

PCH_GPIO48

V13

PCH_GPIO49

V3
D6

AU16

PCH_PECI_R

P5

KB_RST#

PROCPWRGD

AY11

H_CPUPWRGD

THRMTRIP#

AY10

R278 1

P+

INIT3_3V#

T14

P-

DF_TVS

AY1

TS_VSS1

AH8

TS_VSS2

AK11

TS_VSS3

AH10

TS_VSS4

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

T18

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

BG48

T19

GPIO57

VSS_NCTF_17

BH3

T20

VSS_NCTF_18

BH47

T21

VSS_NCTF_19

BJ4

T23
T25

VSS_NCTF_2

VSS_NCTF_20

A45

VSS_NCTF_3

VSS_NCTF_21

BJ45

T27

A46

VSS_NCTF_4

VSS_NCTF_22

BJ46

T29

2 10K_0402_5%

PCH_GPIO48

T30

A5

VSS_NCTF_5

VSS_NCTF_23

BJ5

T31

2 10K_0402_5%

PCH_GPIO49

T32

A6

VSS_NCTF_6

VSS_NCTF_24

BJ6

T33

T34

B3

VSS_NCTF_7

VSS_NCTF_25

C2

B47

VSS_NCTF_8

VSS_NCTF_26

C48

T38

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

T40

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

T42

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

T44

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

T46

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

T48

BF49

VSS_NCTF_32

F49

2 1K_0402_5%

PCH_GPIO15

R347 1

2 10K_0402_5%

PCH_GPIO28

2 10K_0402_5%

PCH_GPIO57

1 10K_0402_5%
@

2 10K_0402_5%

2 0_0402_5%

H_PECI

+3VS

(5,41)
PCH_GPIO71

H_CPUPWRGD
2 390_0402_5% H_THRMTRIP#

R257 2

1 10K_0402_5%

R263 1

(5)

@

2 10K_0402_5%

H_THRMTRIP# (5)
VGA_THRMTRIP# (22)

+3VS

INIT3_3V

GATEA20

R272 1

2 10K_0402_5%

KB_RST#

R276 1

2 10K_0402_5%

R226
2.2K_0402_5%

T28

R273 1

R258 2

Intel schematic reviwe recommand.

P37

T26

PCH_GPIO12

@

KB_RST# (41)

AK10

NC_1

3G_OFF#

EC_SMI#

A

+1.8VS

3G_DET#

2 10K_0402_5%

R267 1

This signal has weak internal
PU, can't pull low

BJ44

2 10K_0402_5%

2 8.2K_0402_5%

+3VS

DF_TVS

A44

R271 1

@

GATEA20 (41)

T24

GPIO34

2 8.2K_0402_5%

R260 1

P4

A4

R345 1

@

P-

SCLOCK / GPIO22

T36

R292 1

A20GATE

TACH0 / GPIO17

R256 1

R262 1

P-

T5

PCH_GPIO57

ODD_EN#

(36)

PCH_GPIO70

PCH_GPIO12

D40

ODD_EN#

P+

T22

+3V_PCH

C

@

ODD_EN#

PCH_GPIO6

PCH_GPIO22
PCH_GPIO24

C40

PCH_GPIO1

DGPU_PWROK

(24,51) DGPU_PWROK

+3V_PCH

TACH4 / GPIO68

1

R274 1

P+

B

2

H烉On-Die voltage regulator enable
L烉On-Die PLL Voltage Regulator disable

BMBUSY# / GPIO0

CPU/MISC

*

T7

VSS_NCTF_1

NCTF

A

PCH_GPIO0

GPIO

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

VSS_NCTF_14

DF_TVS R229 1

2 1K_0402_5%

H_SNB_IVB#

(5)

DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
CLOSE TO THE BRANCHING POINT

T35

T37
T39

T41
T43

T45
C

T47

T49

PANTHER-POINT_FCBGA989

For Edge code setting
PCH_GPIO69

PCH_GPIO38

PCH_GPIO67

0

0

0

Optimus

0

0

1

Reserved

0

1

0

DIS

0

1

1

UMA

Function

R311
10K_0402_5%
UMA@

(14)

(MB_ID_2)
(MB_ID_1)
(MB_ID_0)

R286
10K_0402_5%
DIS@

Compal Secret Data

Security Classification
Issued Date

2

R329
10K_0402_5%
DIS@
2

2

PCH_GPIO67

1

1

1

PCH_GPIO69
PCH_GPIO38
PCH_GPIO67
R261
10K_0402_5%

D

2

2

R330
10K_0402_5%
UMA@
2

R259
10K_0402_5%
@

D

1

1

1

+3VS

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(6/9)
GPIO, CPU, MISC
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
18
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

+VCCADAC

+3VS

+VCCADAC

MBK1608221YZF_2P

1

C112
0.1U_0402_10V7K

VCCIO[15]

AN17

VCCIO[16]
VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

+VCCAFDI_VRM

1
@ C114
1U_0402_6.3V6K

C

+1.05VS_PCH

2

CRT
LVDS

AM37

VCCTX_LVDS[2]

AM38

40mAVCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

3709mA

VCC3_3[6]

V33

VCC3_3[7]

V34

VCCVRM[3]

AT16

VCCDMI[1]

AT20

VCCIO[26]

VCCDFTERM[1]

AG16

BH29

VCC3_3[3]

2mA VCCDFTERM[2]

AG17

VCCDFTERM[3]

AJ16

VCCDFTERM[4]

AJ17

DMI

VCCIO[25]

AN34

VccAFDIPLL

B

+VCCAFDI_VRM

+VCCAFDI_VRM

75mA VCCCLKDMI

1

AB36

1

C111
1U_0402_6.3V6K

C110
1U_0402_6.3V6K

2

+1.8VS

+VCCPNAND
+VCCPNAND

0_0805_5%
1

2 R300

+3VM
+3V_VCCPSPI R166

10mA VCCSPI

1

C113
1U_0402_6.3V6K

2

+3V_VCCPSPI

V1

R302
1

PANTHER-POINT_FCBGA989

+1.5VS

C104
0.1U_0402_10V7K

2

VCCVRM[2]

VCCDMI[2]

2

2 L2

1

0.1uH inductor, 200mA

+VCCP_VCCDMI

AN33

VCCIO[27]

2

1

+1.05VS

VCCIO[24]

AP17

2

1

+1.05VS_PCH

VCCIO[23]

AU20

0.1UH_MLF1608DR10KT_10%_1608
1

2

AT24

BG6

+VCCTX_LVDS

1

VCCIO[22]

+1.05VS_VCCDPLL_FDI
+VCCP_VCCDMI

1 SBA@
1

@

C115
1U_0402_6.3V6K

+3VS

2 0_0402_5%
2 0_0402_5%

C

11/16

2

+VCCAFDI_VRM

R304

D

VCCTX_LVDS[1]

AP26

AP16

+1.05VS_VCCAPLL_FDI

AK37

AP24

2

Place C167 Near BG6 pin

VSSALVDS

HVCMOS

AN21

DFT / SPI

+3VS

AN16

AK36

+3VS

VCCIO

2

VCCAPLLEXP

FDI

1

1U_0402_6.3V6K

2

C109

1

1U_0402_6.3V6K

2

C108

1

1U_0402_6.3V6K

C107

2

1U_0402_6.3V6K

C106

10U_0603_6.3V6M

C105

2

1

BJ22

1mAVCCALVDS

22U_0805_6.3V6M

+1.05VS_VCC_EXP

1

A

+3VS

C103

+1.05VS_PCH

B

VCCIO[28]

U47

0.01U_0402_16V7K

This pin can be left as no connect in
On-Die VR enabled mode (default).

AN19

U48

VSSADAC

C102

+1.05VS_PCH
T50

@

2

+1.8VS

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

1mA VCCADAC

0.01U_0402_16V7K

+1.05VS_PCH

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

C101

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

VCC CORE

2

10U_0603_6.3V6M

1

1U_0402_6.3V6K

2

C98

1

1U_0402_6.3V6K

2

C97

1

1U_0402_6.3V6K

C96

2

10U_0603_6.3V6M

C95

1

1

1300mA

+1.05VS_PCH

2

2

C160

1

PAD-OPEN 4x4m

POWER

U3G

1

10U_0603_6.3V6M

+1.05VS_PCH
JP2

2

C100

+1.05VS

1

0.1U_0402_10V7K

A

C99

2

0.01U_0402_16V7K

C94

1

2 L1

1

1

2 0_0603_5% +VCCAFDI_VRM

D

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(7/9)
PWR
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
19
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
+1.05VS

+VCCACLK
+5VALW
+VCCPDSW

POWER

1

+PCH_VCCDSW

2

+1.05VS_PCH

C123

@

2

T16

VCCDSW3_3 3mA

V12

DCPSUSBYP

T38

VCC3_3[5]

+VCCAPLL_CPY_PCH

1

BH23

10U_0603_6.3V6M

AL29
C124

@

1

+VCCSUS1

2

AL24

DCPSUS[3]

1U_0402_6.3V6K
AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

+1.05VM_VCCASW

AA27

VCCASW[5]

22U_0805_6.3V6M

AA29

VCCASW[6]

R316 1

@

2 0_0805_5%

2

1
2

22U_0805_6.3V6M

1

C131

2

C130

+1.05VS_PCH

2

1

1U_0402_6.3V6K

2

C129

2 0_0805_5%

1

1U_0402_6.3V6K

SBA@

if not supply SBA R316 mount , R349 @
if supply SBA R316 @,R349 mount

C128

R349 1

B

1

1U_0402_6.3V6K

C127

+1.05VM

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31
L4

1
2
10UH_LB2012T100MR_20%

+1.05VS_VCCA_A_DPL
C136

220U_B2_2.5VM_R35

1
+
2

L5
1
2
10UH_LB2012T100MR_20%

C137
1

1U_0402_6.3V6K

2

+1.05VS_VCCA_B_DPL
C138

220U_B2_2.5VM_R35

1
+
2

C139
1

1U_0402_6.3V6K

C143 1

2

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

+VCCAFDI_VRM

N16

DCPRTC

Y49

VCCVRM[4]

T27

T24

VCCSUS3_3[9]

V23

VCCSUS3_3[10]

V24

VCCSUS3_3[6]

P24

VCCIO[34]

T26

+1.05VS_PCH

V5REF_SUS

M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

+3V_PCH

V5REF

P34

+PCH_V5REF_RUN

VCCSUS3_3[2]

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

DCPSUS[4]
VCCSUS3_3[1]

1mA

+1.05VS_VCCA_A_DPL

BD47

VCCADPLLA

75mA

+1.05VS_VCCA_B_DPL

BF47

VCCADPLLB

75mA

AA16

VCC3_3[8]

W16

VCC3_3[4]

T34

VCC3_3[2]

AJ2

VCCIO[5]

AF13

VCCIO[12]

AH13

VCCIO[13]

AH14

+1.05VS_PCH

AF17
AF33
AF34
AG34

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

AG33

VCCSSC 95mA

2

+1.05VS
R328 1

C146
1U_0402_6.3V6K

2 0_0603_5%

Ensure independent power
routing for SSC and DIFFCLKN

+1.05VS_SSCVCC
1

C149
1U_0402_6.3V6K

+VCCSST
+1.05VM_VCCSUS

2
C150
0.1U_0402_10V7K

2

1

1

2

C151
1U_0402_6.3V6K
@

1
2

+3V_PCH

C125
0.1U_0402_10V7K

+1.05VS_PCH

2

1
2

+PCH_V5REF_SUS

C132
@
1U_0402_6.3V6K

+3V_PCH

C126
0.1U_0402_10V7K

2

C133
0.1U_0402_10V7K

11/16
B

+3V_PCH
1

VCCIO[2]

AC16

VCCIO[3]

AC17

VCCIO[4]

AD17

C134
1U_0402_6.3V6K

2

D5
RB751V-40_SOD323-2

+3VS

+PCH_V5REF_RUN

C141
0.1U_0402_10V7K

1

1

2

2

1

C135
1U_0402_6.3V6K

C140
0.1U_0402_10V7K

+1.05VS_PCH

C145
1U_0402_6.3V6K

+VCCSATAPLL

2

1

C142
0.1U_0402_10V7K

Place C199 Near AK1 pin
1

R318
10_0402_5%

2

2

AK1
AF11

+5VS

C147
10U_0603_6.3V6M
@

1

+1.05VS_SATA3

2
C

+VCCAFDI_VRM

+VCCAFDI_VRM

+1.05VS_PCH

+1.05VS_VCC_SATA
1

C148
1U_0402_6.3V6K

T17
V19

DCPSUS[1]
DCPSUS[2]

BJ8

1mA
V_PROC_IO

VCCRTC

VCCASW[22]

T21

VCCASW[23]

V21

VCCASW[21]

T19

VCCSUSHDA

P32

+1.05VM_VCCASW

PANTHER-POINT_FCBGA989

10mA

C158
0.1U_0402_16V4Z

2

D

11/16

1
2

0.1U_0402_10V7K

2

C157

1

0.1U_0402_10V7K

C156

1U_0402_6.3V6K

2

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

1
2

+RTCVCC

1

1

R315
10_0402_5%

1

AF14

VCCVRM[1]

+5VALW_PCH

D4
RB751V-40_SOD323-2

+1.05VS_VCCAUPLL

1

C155

0.1U_0402_10V7K

C154

2

0.1U_0402_10V7K

C153

2

4.7U_0603_6.3V6K

C152

D

1

11/16

+3V_PCH

+1.05VS_PCH
1

DCPSST

A22

+1.05VS_PCH
+V_CPU_IO

C122
0.1U_0402_10V7K

2

1

+1.05VS_VCCUSBCORE

2

V16

CPU

+1.05VS_PCH
1

VCCAPLLSATA

55mA

RTC

2

VCCIO[6]

SATA

C144
1U_0402_6.3V6K

MISC

1

HDA

C

1

C120
1U_0402_6.3V6K

+3VS

VCC3_3[1]

+VCCAFDI_VRM

2

+3V_PCH

VCCSUS3_3[8]

+VCCRTCEXT

2

0.1U_0402_10V7K

P28

VCCIO[32]

A

1

T23

1mA

VCCASW[11]

VCCIO[31]

+1.05VS_PCH

T29

903mA

Clock and Miscellaneous

+1.05VS

P26

VCCIO[33]

VCCIO[14]

+VCCDPLL_CPY

N26

VCCIO[30]

VCCSUS3_3[7]

119mA

VCCAPLLDMI2

VCCIO[29]

2 0_0603_5%

2

2

@

0.1U_0402_10V7K

1U_0402_6.3V6K

C117

10U_0603_6.3V6M

C116

1

C121

VCCACLK

1

1

+3VS

2

AD49

2

+3VS

1

C118
0.1U_0402_10V7K

USB

1

+5VALW_PCH
R309

2

U3J

If platform does not support
Deep S4/S5 then tie to VccSus3_3.

A

+1.05VS_PCH

1

2 0_0603_5%

PCI/GPIO/LPC

R308 1

1

2 0_0603_5%

2

@

1

R307 1

2

+3VALW

Have internal VRM

3

4

Compal Electronics, Inc.
PCH
(8/9)
PWR
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
20
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

A

B

C

3

4

U3H

5

U3I

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

PANTHER-POINT_FCBGA989

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

A

B

C

PANTHER-POINT_FCBGA989

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH
(9/9)
VSS
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
21
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

+3VS_VGA

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

B

C1401
C1402
C1403
C1404
C1405
C1406
C1407
C1409
C1410
C1411
C1412
C1413
C1414
C1415
C1416
C1417
C1418
C1419
C1420
C1421
C1422
C1423
C1424
C1425
C1426
C1427
C1428
C1429
C1430
C1431
C1432
C1433

C

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

(14) CLK_PCIE_VGA
(14) CLK_PCIE_VGA#
1
R1432

Differential signal

@

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

AJ12
AP29

PEX_RST_N
PEX_TERMP

PLT_RST_VGA#
PEX_TERMP
1
2
R1434 DIS@ 2.49K_0402_1%

1 DIS@

2 10K_0402_5%

VGA_ENVDD

R1411

1 DIS@

2 10K_0402_5%

VGA_ENBKL

R1412

1

VGA_GPIO15

R1414

1 DIS@

@

2 10K_0402_5%

At LVDS site

2 100K_0402_5%

A

(51)

(51)
(51)

+3VS_VGA

GPU_VID0
VGA_GPIO12
GPU_VID5
VGA_GPIO15
VGA_GPIO16

D2414

2

1

RB751V-40_SOD323-2
R1430 1

@

GPU_VID0 (51)
VGA_AC_DET (41,51)
GPU_VID5 (51)

VGA_AC_DET

VGA_THRMTRIP#

DIS@

2 0_0402_5%

DPRSLPVR_VGA

(18)

3

AJ26
AK26

PEX_TSTCLK_OUT
2
200_0402_1% PEX_TSTCLK_OUT#

R1413

R1423
10K_0402_5%
DIS@

Q1401B
2N7002KDWH_SOT363-6
DIS@

5

(51)

4

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

GPU_VID1
GPU_VID2

2 10K_0402_5%

VGA_BL_PWM

1

PEX_WAKE_N

AL13
AK13
AK12

DPRSLPVR_VGA

1 DIS@

2

AJ11
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#

2 0_0402_5%

R1409

OVERT#
THERM#_VGA

OVERT#
2
DIS@
Q1401A
2N7002KDWH_SOT363-6

DACA_RED
DACA_GREEN
DACA_BLUE

AK9
AL10
AL9

DACA_HSYNC
DACA_VSYNC

AM9
AN9

DACA_VDD
DACA_VREF
DACA_RSET

@

2 10K_0402_5%

VGA_GPIO12

6

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

R1429 1

(51)
(51)

2 10K_0402_5%

1 DIS@

1

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

GPU_VID4
GPU_VID3

1 DIS@

R1410

+3VS_VGA

B

R1448 1 DIS@

AG10
AP9
AP8

2 10K_0402_5%

5

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15

DIS@

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

GPU_VID4
GPU_VID3
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
GPU_VID1
GPU_VID2

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

R1408

THERM#_VGA

I2CS_SCL

Q1402B
3

4

DIS@
EC_SMB_CK2

(14,39,41)

EC_SMB_DA2

(14,39,41)

2N7002KDWH_SOT363-6
+3VS_VGA
R4
R5

I2CA_SCL
I2CA_SDA

R1452 1 DIS@
R1460 1 DIS@

2 2.2K_0402_5%
2 2.2K_0402_5%

I2CB_SCL
I2CB_SDA

R7
R6

I2CB_SCL
I2CB_SDA

R1406 1 DIS@
R1407 1 DIS@

2 2.2K_0402_5%
2 2.2K_0402_5%

I2CC_SCL
I2CC_SDA

R2
R3

I2CC_SCL
I2CC_SDA

R1402 1 DIS@
R1403 1 DIS@

2 2.2K_0402_5%
2 2.2K_0402_5%

I2CS_SCL
I2CS_SDA

T4
T3

I2CS_SCL
I2CS_SDA

R1404 1 DIS@
R1405 1 DIS@

2 2.2K_0402_5%
2 2.2K_0402_5%

I2CA_SCL
I2CA_SDA

R1442 1

@

2 0_0402_5%

2

PCIE_CRX_GTX_P[0..15]

(4) PCIE_CRX_GTX_P[0..15]

Part 1 of 7

GPIO

(4) PCIE_CRX_GTX_N[0..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

DACs

PCIE_CRX_GTX_N[0..15]

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

I2C

(4) PCIE_CTX_GRX_P[0..15]

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

I2CS_SDA

Q1402A
6

1

DIS@

2N7002KDWH_SOT363-6
R1443

1

@

2 0_0402_5%

PU AT EC SIDE, +3VS AND 4.7K

R1436 1 DIS@

PLLVDD

AD8

+PLLVDD

SP_PLLVDD

AE8

45mA

VID_PLLVDD

AD7

45mA

XTAL_IN
XTAL_OUT

H3
H2

XTALIN
XTAL_OUT

XTAL_OUTBUFF
XTAL_SSIN

J4
H1

XTALOUT
XTALSSIN

R1428 1

@

2 0_0402_5%

XTALIN
XTAL_OUT
1 1
3 3
GND
GND
C1441
2
4
18P_0402_50V8J
DIS@
2
27MHZ 16PF X3G027000FG1H-HX
1

+SP_PLLVDD

R1433 1 DIS@
R1435 1 DIS@

2 10M_0402_5%

DIS@
Y1401

60mA

CLK

PCIE_CTX_GRX_P[0..15]

PCI EXPRESS

(4) PCIE_CTX_GRX_N[0..15]
A

U1401A

PCIE_CTX_GRX_N[0..15]

OVERT#

1
2

C

C1442
18P_0402_50V8J
DIS@

2 10K_0402_5%
2 10K_0402_5%

Internal Thermal Sensor
Under GPU(below 150mils)

N13P-PES-A1_FCBGA908
DIS@

1

1

2
R1447

2

2

L1403 DIS@
1
2
BLM18PG181SN1D_2P

+1.05VS_VGA

30 ohms @100MHz (ESR=0.05)
D

Near GPU

@

1

S

D
1

2

+1.05VS_VGA

180ohms (ESR=0.2) Bead

CLK_REQ_GPU#

3

Q2414
DIS@
2N7002K_SOT23-3

R1446
10K_0402_5%
@

2
0_0402_5%

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1
2

2

Under GPU

L1402 DIS@
1
2
BLM18PG330SN1_2P

2

G

2

5
P
G

3

R1445
10K_0402_5%
DIS@

DIS@

2

1

22U_0805_6.3V6M

R1441
10K_0402_5%
DIS@

1

2

C1449

C2108
0.1U_0402_16V4Z

DIS@

1

1

1

(14) GPU_CLKREQA

1

0.1U_0402_10V7K

PLT_RST_VGA#

4

C1446

Y

DIS@

A

TC7SH08FUF_SSOP5
DIS@

U1402

2

0.1U_0402_10V7K

B

2

C1445

1

DGPU_HOLD_RST#

11/17

1

DIS@

(17) DGPU_HOLD_RST#

PLT_RST#

R1438
10K_0402_5%
@

1

+PLLVDD
+3VS_VGA

0.1U_0402_10V7K

PLT_RST#

C2154
0.1U_0402_16V4Z
DIS@

10K_0402_5%
DIS@

2

C1448

(5,14,17,36,38,40,41)

2

DIS@

R1437 1
2
@ 0_0402_5%

D

1

(17,24) DGPU_PWR_EN

2

1

4.7U_0402_6.3V6M

R1444
+3VS_VGA

DIS@

SA000051A40
S IC N13P-GL-A1 FCBGA 908P GPU A39

C1444

1

22U_0805_6.3V6M

C1443

SA000056B30
S IC N13M-GE1-B-A1 FCBGA 908P GPU A39

+3VS_VGA

150mA

+SP_PLLVDD

3

4

Compal Electronics, Inc.
N13X-PCIE/DAC/GPIO
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
22
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

U1401D

B

C

AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

A

VDD_SENSE

L4

VCCSENSE_VGA

GND_SENSE

L5

VSSSENSE_VGA

VCCSENSE_VGA

(51)

VSSSENSE_VGA

(51)

trace width: 16mils
differential voltage sensing.
differential signal routing.

TEST

LVDS/TMDS

A

Part 4 of 7

AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6

AG3
AG2

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

AK3
AK2

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

AB3
AB4

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

AF3
AF2

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

TESTMODE

AK11

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AM10
AM11
AP12
AP11
AN11

TESTMODE
T1401
T1402
T1403
T1404

R1449 1 DIS@

2 10K_0402_5%

R1450 1 DIS@

2 10K_0402_5%

B

SERIAL

DIS@

H6
H4
H5
H7

ROM_CS R1453
ROM_SCLK
ROM_SI
ROM_SO

BUFRST_N

L2

R1530 1 DIS@

2 10K_0402_5%

CEC

L3

R1531 1 DIS@

2 10K_0402_5%

MULTI_STRAP_REF0_GND

J1

R1532 1 DIS@

2 40.2K_0402_1%

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

J2
J7
J6
J5
J3

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

THERMDP
THERMDN

K3
K4

ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO

1

2 10K_0402_5%
ROM_SCLK (31)
ROM_SI (31)
ROM_SO (31)

+3VS_VGA

GENERAL

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

+3VS_VGA

(31)
(31)
(31)
(31)
(31)

C

N13P-PES-A1_FCBGA908
DIS@

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-LVDS/HDMI/DP/THM
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
23
58
of
Sheet
Date:
Title

5

Rev
0.6

1

2

3

5

1

DIS@

2

22U_0805_6.3V6M

C1478

2

22U_0805_6.3V6M

1

DIS@

2

C1477

22U_0805_6.3V6M

1

DIS@

DIS@

2

C1476

1

22U_0805_6.3V6M

DIS@

2

C1475

1

10U_0603_6.3V6M

C1474

DIS@

2

10U_0603_6.3V6M

C1473

DIS@

2

1

4.7U_0603_6.3V6K

1

DIS@

DIS@

2

C1495

1

4.7U_0603_6.3V6K

C1494

DIS@

2

DIS@

1

4.7U_0805_10V4Z

2

C1502

+PEX_PLLVDD

L1404
DIS@
1
2
BLM18PG121SN1D_0603

120mA
1

2

0.1U_0402_10V7K

C1493

1

2

+3VS_VGA

Under GPU(below 150mils)

+1.05VS_VGA

1

2

120ohms @100MHz (ESR=0.18)
L1405

@

Place near balls

0_0603_5%

Place near balls

+3VS_VGA

Place near GPU

+VDD33

R1461 1 DIS@

AB8
AD6

+IFPEF_PLLVDD

R1474 1 DIS@

2 10K_0402_5%

IFPE_IOVDD
IFPF_IOVDD

AC7
AC8

+IFPE_IOVDD

R1466 1 DIS@

2 10K_0402_5%

B

+5VALW

1

IFPEF_PLVDD
IFPEF_RSET

2

R1545
100K_0402_5%
DIS@
DGPU_PWROK#

DGPU_PWROK#

(51)

1

2 10K_0402_5%

DIS@

R1472 1 DIS@

1

4.7U_0603_6.3V6K

IFPD_IOVDD

+IFPD_IOVDD

2

C1499

2 10K_0402_5%

AG6

DIS@

R1469 1 DIS@

1

1U_0402_6.3V6K

IFPD_PLLVDD
IFPD_RSET

+IFPD_PLLVDD

2

C1498

2 10K_0402_5%

AG7
AN2

1

DIS@

IFPC_IOVDD

2

0.1U_0402_10V7K

2 10K_0402_5%

R1467 1 DIS@

1

C1497

R1465 1 DIS@

+IFPC_IOVDD

2

DIS@

+IFPC_PLLVDD

AF6

1

0.1U_0402_10V7K

AF7
AF8

2

C1496

IFPC_PLLVDD
IFPC_RSET

1

DIS@

2 10K_0402_5%

0.1U_0402_10V7K

R1471 1 DIS@

C1506

2 10K_0402_5%

+IFPAB_IOVDD

DIS@

+IFPAB_PLLVDD R1462 1 DIS@

AG8
AG9

0.1U_0402_10V7K

AH8
AJ8

IFPA_IOVDD
IFPB_IOVDD

C1507

IFPAB_PLLVDD
IFPAB_RSET

2 0_0603_5%

2

VDD33_0
VDD33_1
VDD33_2
VDD33_3

1

2 0_0402_5%

+PEX_PLLVDD

J8
K8
L8
M8

10U_0603_6.3V6M

DIS@

2

C1472

1

10U_0603_6.3V6M

C1471

DIS@

2

4.7U_0603_6.3V6K

C1470

@

DIS@

Place near balls

R1459 1

1U_0603_10V6K

FB_CAL_TERM_GND

+PEX_PLLHVDD

C1501

H25

DIS@

51.1Ohm

2 51.1_0402_1%

FB_CAL_PU_GND

4.7U_0603_6.3V6K

FB_CAL_xTERM_GND

R1473 1 DIS@

H27

C1469

42.2Ohm

2 42.2_0402_1%

2

1

A

DIS@

FB_CAL_x_PU_GND

R1470 1 DIS@

FB_CAL_PD_VDDQ

1

GPU

For N13P-GT/N13E-GE

0.1U_0402_10V7K

40.2Ohm

J27

2

C1500

FB_CAL_x_PD_VDDQ

2 40.2_0402_1%

DIS@

DDR3

FB_GND_SENSE

1

1U_0402_6.3V6K

R1468 1 DIS@

CALIBRATION PIN

F2

AG26

2

C1468

2 R1464 FB_VSS_SENSE

FB_VDDQ_SENSE

PEX_PLLVDD

DIS@

@

1

+1.5VS_VGA

F1

PEX_SVDD_3V3

AG12

1

1U_0402_6.3V6K

2 R1463 FB_VDDQ_SENSE

AH12

2

C1467

10_0402_5%

@

1

PEX_PLL_HVDD

2

DIS@

10_0402_5%

+1.5VS_VGA

B

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

1

1U_0402_6.3V6K

rise 1.5v system source voltage to 1.55-1.57V

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

1

GPU(below 150mils) Near
C1466

A

AG19
AG21
AG22
AG24
AH21
AH25

DIS@

DIS@

2

2000mAUnder
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

1U_0402_6.3V6K

1

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

C1465

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

10U_0805_6.3V6M

DIS@

2

C1461

1

+1.05VS_VGA

Part 5 of 7

3.5A
10U_0805_6.3V6M

DIS@

2

C1460

1

10U_0805_6.3V6M

DIS@

2

C1459

1

10U_0805_6.3V6M

DIS@

2

C1458

1

4.7U_0603_6.3V6K

DIS@

2

C1457

1

4.7U_0603_6.3V6K

DIS@

2

C1456

1

1U_0603_10V6K

DIS@

2

C1480

1

1U_0603_10V6K

DIS@

2

C1479

1

0.1U_0402_10V7K

DIS@

2

C1490

1

0.1U_0402_10V7K

DIS@

2

C1489

1

0.1U_0402_10V7K

DIS@

2

C1488

1

0.1U_0402_10V7K

DIS@

2

C1487

1

0.1U_0402_10V7K

DIS@

2

C1486

1

0.1U_0402_10V7K

C1485

DIS@

2

0.1U_0402_10V7K

C1484

DIS@

0.1U_0402_10V7K

C1483

2

1

Near GPU

POWER

Under GPU(below 150mils)

1

4

U1401E

+1.5VS_VGA

D
R1544

(18,51) DGPU_PWROK

1 DIS@

2 10K_0402_5% 2

G
S

DIS@

Q1411
2N7002K_SOT23-3
DIS@

3

1

N13P-PES-A1_FCBGA908

2

R1546
100K_0402_5%
@

C

C

+3VS to +3VS_VGA
+1.5V to +1.5VS_VGA
+1.5V
2

1

2 0_0402_5%

G
S

1

DGPU_PWROK#
R1480 DIS@
100K_0402_5%

SUSP

2

1 2

D
2

Q1406
2N7002K_SOT23-3
DIS@

1
2

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

R1479 @
1
2
10K_0402_5%

D
Q1407
2N7002K_SOT23-3 S
@

3

R1478 1 DIS@

R1476
1 DIS@
2
10K_0402_5%

G

2
1

@

2

1

1 2

R1543 @
1
2
0_0402_5%

1

1
2

4

3

G

SUSP#

(17,22) DGPU_PWR_EN

2 0_0402_5%

2

2

2

R1540 @
1
2
0_0402_5%

@

DIS@
2

10U_0603_6.3V6M
R1533
470_0603_5%
@

2

DGPU_PWR_EN#

0.1U_0402_10V7K

DIS@

3

(9,41,42,46,48,50,51)

D
Q1408
S
2N7002K_SOT23-3
@

C1511
1

1

C1521

1

DGPU_PWR_EN#
R1477 1

DIS@

S

1

3

G

G

Q1410
2N7002K_SOT23-3
DIS@

0.1U_0603_25V7K

R1537
100K_0402_5%
@

D

D
2

C1516

2 0_0402_5%

2

D

2 0_0402_5%

S

R1539
470_0603_5%
@

2 0_0402_5%

2

Q1405
DIS@
AO3413_SOT23-3

R1475
100K_0402_5%
DIS@

0.1U_0402_10V7K

@

DGPU_PWROK# R1541 1 DIS@

2

1

JUMP_43X79

C1515

R1542 1

SUSP

DIS@

(9,42,50,51)

(51) DGPU_PWROK#

1 DIS@

2

1

0.1U_0402_10V7K

R1538

2

C1627

@

1
2
3

DIS@

8
7
6
5

1

10U_0603_6.3V6M

R1536
100K_0402_5%
DIS@

C1512

1

Q1404
DIS@
AO4430L_SO8

10U_0603_6.3V6M

C1513

JUMP_43X79

J1401 @

1

2

+3VS_VGA
1

1

1

+3VS

2

1

J1402 @

3

+VSB

+5VALW

+1.5VS_VGA

Compal Electronics, Inc.
N13X-POWER
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
24
58
of
Date:
Sheet

D

Title

5

Rev
0.6

1

U1401F

Part 7 of 7

XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8

U1
U2
U3
U4
U5
U6
U7
U8

XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16

V1
V2
V3
V4
V5
V6
V7
V8

XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22

W2
W3
W4
W5
W7
W8

XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

1

DIS@

V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

2

47U_0805_4V6

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71

VDD33
tIFPx_IOVDD
IFPx_IOVDD
tNVVDD
NVVDD
tFBVDDQ
FBVDDQ

N13P-PES-A1_FCBGA908
C

5

Place near balls
C1636

B

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15

4

tPEX_VDD

DIS@

PEX_VDD
tIFPy_IOVDD
IFPy_IOVDD

NV Recommended Power On Sequencing Order
X=A and B
Y=C,D,E and F

D

Part 6 of 7
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

GND

A

3

+VGA_CORE

U1401G

POWER

+VGA_CORE

2

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32

A

B

C

D

N13P-PES-A1_FCBGA908
DIS@

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-VGA
CORE, GND
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
25
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

FBA_D[0..63]

(27,28) FBA_D[0..63]

(29,30) FBC_D[0..63]

FBA_MA[15..0]

(27,28) FBA_DQS#[7..0]

FBA_BA[2..0]

U1401B

C

(27,28)
(27,28)

(29,30) FBC_DQS[7..0]

FBC_MA[15..0]

(29,30) FBC_DQS#[7..0]

FBC_BA[2..0]

PU for X16 mode

U1401C

Part 2 of 7

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

FB_CLAMP

FBA_ODT_H
FBA_CKE_H

FBA_RAS#

@
@

(28)
(28)

(27,28)

2 60.4_0402_1%
2 60.4_0402_1%

+1.5VS_VGA

FBA_CLK0 (27)
FBA_CLK0# (27)
FBA_CLK1 (28)
FBA_CLK1# (28)

T1405
E1

R1513 1 DIS@

2

10K_0402_5%
+FB_PLLAVDD

FB_DLL_AVDD

K27

C1622 1

2 DIS@ 0.1U_0402_10V7K

Place close to ball
FBA_PLL_AVDD

FB_VREF

U27

H26

+FB_PLLAVDD
1
2

1
2

Place close to ball

1
2

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

E11
E3
A3
C9
F23
F27
C30
A24

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBC_DQS0
FBC_DQS1
FBC_DQS2
FBC_DQS3
FBC_DQS4
FBC_DQS5
FBC_DQS6
FBC_DQS7

D10
D5
C3
B9
E23
E28
B30
A23

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBC_DQS#0
FBC_DQS#1
FBC_DQS#2
FBC_DQS#3
FBC_DQS#4
FBC_DQS#5
FBC_DQS#6
FBC_DQS#7

D9
E4
B2
A9
D22
D28
A30
B23

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

Place close to BGA

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

FBB_CMD_RFU0
FBB_CMD_RFU1

C12
C20

FBB_DEBUG0
FBB_DEBUG1

G14
G20

R1510 1
R1512 1

FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N

D12
E12
E20
F20

FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#

FBC_CS0#_L

FBC_ODT_L
FBC_CKE_L
FBC_MA14
FBC_RST#
FBC_MA9
FBC_MA7
FBC_MA2
FBC_MA0
FBC_MA4
FBC_MA1
FBC_BA0
FBC_WE#
FBC_MA15
FBC_CAS#
FBC_CS0#_H

FBC_ODT_L
FBC_CKE_L

FBx_CMD0

(29)
(29)

FBC_RST#

FBC_WE#

Address

(29)

FBx_CMD2

(29,30)

FBC_ODT_H
FBC_CKE_H

FBC_RAS#

(30)
(30)

(29,30)

ODT_L

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

F8
E8
A5
A6
D24
D25
B27
C27

FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

D6
D7
C6
B6
F26
E26
A26
A27

FBB_PLL_AVDD

H17

CAS#
CS0#_H

FBx_CMD16

B

FBx_CMD17
ODT_H

FBx_CMD18

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

A

32..63

CS0#_L

FBx_CMD1

(29,30)

FBC_CAS# (29,30)
FBC_CS0#_H (30)

FBC_ODT_H
FBC_CKE_H
FBC_MA13
FBC_MA8
FBC_MA6
FBC_MA11
FBC_MA5
FBC_MA3
FBC_BA2
FBC_BA1
FBC_MA12
FBC_MA10
FBC_RAS#

0..31

@
@

2 60.4_0402_1%
2 60.4_0402_1%

CKE_H

FBx_CMD19

+1.5VS_VGA

FBC_CLK0 (29)
FBC_CLK0# (29)
FBC_CLK1 (30)
FBC_CLK1# (30)

FBx_CMD20

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

A13

C

+FB_PLLAVDD
1
2

Place close to ball

N13P-PES-A1_FCBGA908

DIS@

D

DATA Bus
FBC_CS0#_L

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

DIS@

N13P-PES-A1_FCBGA908

FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#

FBA_ODT_H
FBA_CKE_H
FBA_MA13
FBA_MA8
FBA_MA6
FBA_MA11
FBA_MA5
FBA_MA3
FBA_BA2
FBA_BA1
FBA_MA12
FBA_MA10
FBA_RAS#

Mode D - Mirror Mode Mapping

Part 3 of 7

0.1U_0402_10V7K

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N

R30
R31
AB31
AC31

(27,28)

(29,30)
(29,30)

PU for X16 mode

C1623

M30
H30
E34
M34
AF30
AK31
AM34
AF32

R1509 1
R1511 1

(27,28)

FBA_CAS# (27,28)
FBA_CS0#_H (28)

DIS@

FBA_DQS#0
FBA_DQS#1
FBA_DQS#2
FBA_DQS#3
FBA_DQS#4
FBA_DQS#5
FBA_DQS#6
FBA_DQS#7

R28
AC28

(27)
(27)

FBA_RST#

FBA_WE#

(27)

22U_0805_6.3V6M

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DEBUG0
FBA_DEBUG1

FBA_ODT_L
FBA_CKE_L

C1626

M31
G31
E33
M33
AE31
AK30
AN33
AF33

R32
AC32

FBA_ODT_L
FBA_CKE_L
FBA_MA14
FBA_RST#
FBA_MA9
FBA_MA7
FBA_MA2
FBA_MA0
FBA_MA4
FBA_MA1
FBA_BA0
FBA_WE#
FBA_MA15
FBA_CAS#
FBA_CS0#_H

DIS@

FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7

FBA_CMD_RFU0
FBA_CMD_RFU1

FBA_CS0#_L

1U_0402_6.3V6K

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

C1625

P30
F31
F34
M32
AD31
AL29
AM32
AF34

FBA_CS0#_L

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

DIS@

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

0.1U_0402_10V7K

L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

C1624

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE
A

B

5

(29,30) FBC_DQM[7..0]

(27,28) FBA_DQS[7..0]

MEMORY INTERFACE B

(27,28) FBA_DQM[7..0]

A

4

FBC_D[0..63]

DIS@

30ohms (ESR=0.01) Bead
P/N;SM010007W00
+1.05VS_VGA

D

+FB_PLLAVDD

600mA

L1414 DIS@
+FB_PLLAVDD
1
2
FBMA-L11-160808300LMA25T_2P

Place close to BGA

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-MEM
Interface
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
26
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Memory Partition A - Lower 32 bits
FBA_MA[15..0]

A

(26,28)

FBA_BA[2..0]

(26,28)

FBA_D[0..63]

(26,28)

FBA_DQM[7..0]

(26,28)

FBA_DQS[7..0]

(26,28)

FBA_DQS#[7..0]

1

(26) FBA_CLK0
(26) FBA_CLK0#
(26) FBA_CKE_L

R1483
160_0402_1%
DIS@
2

(26)
(26)
(26,28)
(26,28)
(26,28)

FBA_CLK0#

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

FBA_BA0
FBA_BA1
FBA_BA2

M2
N8
M3

BA0
BA1
BA2

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

J7
K7
K9

CK
CK
CKE/CKE0

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBA_DQS0
FBA_DQS3

F3
C7

DML
DMU

FBA_DQS#0
FBA_DQS#3

G3
B7

DQSL
DQSU

FBA_RST#

T2

RESET

L8

ZQ/ZQ0

R1487
243_0402_1%
DIS@

2

C

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

R1486
10K_0402_5%
DIS@

1

E7
D3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D29
FBA_D25
FBA_D28
FBA_D26
FBA_D31
FBA_D24
FBA_D30
FBA_D27

Group0 (IN3)

Group3 (BOT)

+1.5VS_VGA

DQSL
DQSU

FBA_DQM0
FBA_DQM3

1

(26,28) FBA_RST#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

FBA_D4
FBA_D1
FBA_D7
FBA_D0
FBA_D6
FBA_D3
FBA_D5
FBA_D2

+FBA_VREF0

M8
H1

VREFCA
VREFDQ

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBA_BA0
FBA_BA1
FBA_BA2

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBA_DQS2
FBA_DQS1

F3
C7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_DQM2
FBA_DQM1

E7
D3

DML
DMU

FBA_DQS#2
FBA_DQS#1

G3
B7

DQSL
DQSU

FBA_RST#

T2

RESET

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

R1488
243_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
DIS@

DQSL
DQSU

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

Group2 (IN1)

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D10
FBA_D15
FBA_D8
FBA_D13
FBA_D9
FBA_D12
FBA_D11
FBA_D14

Group1 (TOP)

Mode D - Mirror Mode Mapping
DATA Bus
Address

FBx_CMD0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

0..31

32..63

CS0#_L

FBx_CMD1

FBA_ODT_L
FBA_CKE_L

R1484
10K_0402_5%
DIS@

R1485
10K_0402_5%
DIS@

FBx_CMD2

ODT_L

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

B

CAS#

FBx_CMD16

CS0#_H

FBx_CMD17
FBx_CMD18

ODT_H

FBx_CMD19

CKE_H

FBx_CMD20

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

A13

C

+1.5VS_VGA

U1406 SIDE

1

DIS@

2

1U_0402_6.3V6K

DIS@

2

C1546

1

1U_0402_6.3V6K

2

C1545

1

@

1U_0402_6.3V6K

DIS@

2

C1540

1

1U_0402_6.3V6K

DIS@

2

C1539

1

1U_0402_6.3V6K

2

C1538

1

@

0.1U_0402_10V7K

DIS@

2

C1536

1

0.1U_0402_10V7K

DIS@

2

C1535

1

0.1U_0402_10V7K

DIS@

2

C1525

1

0.1U_0402_10V7K

DIS@

2

C1524

1

0.1U_0402_10V7K

DIS@

2

C1530

1

1U_0402_6.3V6K

DIS@

2

C1534

1

1U_0402_6.3V6K

DIS@

2

C1533

1

1U_0402_6.3V6K

DIS@

2

C1532

1

1U_0402_6.3V6K

DIS@

2

U1407 SIDE
C1531

1

1U_0402_6.3V6K

DIS@

2

C1537

1

0.1U_0402_10V7K

DIS@

2

C1529

1

0.1U_0402_10V7K

DIS@

2

C1528

1

0.1U_0402_10V7K

DIS@

2

C1527

1

0.1U_0402_10V7K

C1526

DIS@

0.1U_0402_10V7K

C1541

2

FBA_D19
FBA_D20
FBA_D17
FBA_D21
FBA_D16
FBA_D23
FBA_D18
FBA_D22

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
DIS@

+1.5VS_VGA

1

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VS_VGA

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

FBA_CLK0

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

E3
F7
F2
F8
H3
H8
G2
H7

2

2
B

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

1

DIS@

2

0.01U_0402_16V7K

C1522

1

R1482
1.1K_0402_1%
DIS@

VREFCA
VREFDQ

1

+FBA_VREF0

M8
H1

2

1
2

R1481
1.1K_0402_1%
DIS@

U1407

+FBA_VREF0

2

U1406
+1.5VS_VGA

A

(26,28)

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-VRAM
A Lower
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
27
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Memory Partition A - Upper 32 bits

A

A

U1409
+FBA_VREF1

VREFCA
VREFDQ

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

FBA_BA0
FBA_BA1
FBA_BA2

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

1
2

DIS@

B

1
2

0.01U_0402_16V7K

R1490
1.1K_0402_1%
DIS@

+FBA_VREF1
C1547

1

2

R1489
1.1K_0402_1%
DIS@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D36
FBA_D34
FBA_D37
FBA_D35
FBA_D39
FBA_D32
FBA_D38
FBA_D33

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D45
FBA_D42
FBA_D46
FBA_D41
FBA_D47
FBA_D43
FBA_D44
FBA_D40

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

R1491
160_0402_1%
DIS@

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

VREFCA
VREFDQ

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBA_BA0
FBA_BA1
FBA_BA2

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBA_DQS7
FBA_DQS6

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_DQM7
FBA_DQM6

E7
D3

DML
DMU

FBA_DQS#7
FBA_DQS#6

G3
B7

DQSL
DQSU

FBA_RST#

T2

RESET

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

Group4 (IN1)

Group5 (TOP)

+1.5VS_VGA

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D63
FBA_D58
FBA_D60
FBA_D59
FBA_D61
FBA_D56
FBA_D62
FBA_D57

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D55
FBA_D51
FBA_D54
FBA_D49
FBA_D52
FBA_D50
FBA_D53
FBA_D48

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

FBA_D[0..63]
FBA_MA[15..0]
FBA_BA[2..0]

Group7 (IN3)

(26)
(26)
(26,27)
(26,27)
(26,27)

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

FBA_DQS4
FBA_DQS5

F3
C7

DQSL
DQSU

FBA_DQM4
FBA_DQM5

E7
D3

DML
DMU

FBA_DQS#4
FBA_DQS#5

G3
B7

DQSL
DQSU

FBA_RST#

T2

RESET

L8

ZQ/ZQ0

FBA_CKE_H
(26,27) FBA_RST#

1

1

J1
L1
J9
L9

R1494
243_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

R1493
10K_0402_5%
DIS@
2

R1492
10K_0402_5%
DIS@
2

C

1

FBA_ODT_H

J1
L1
J9
L9

R1495
243_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

FBA_CLK1#

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
DIS@

+1.5VS_VGA

FBx_CMD0

(26,27)

FBx_CMD2

32..63

B

CS0#_L
ODT_L

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

FBx_CMD16

CAS#
CS0#_H

C

FBx_CMD17
FBx_CMD18

ODT_H

FBx_CMD19

@

2

1

@

2

1U_0402_6.3V6K

2

C1571

@

1

1U_0402_6.3V6K

2

C1570

@

1

1U_0402_6.3V6K

1

C1569

2

0..31

FBx_CMD1

1U_0402_6.3V6K

@

(26,27)

DATA Bus
Address

C1568

2

1

1U_0402_6.3V6K

@

C1565

2

1

0.1U_0402_10V7K

@

C1566

1

0.1U_0402_10V7K

DIS@

2

C1567

1

0.1U_0402_10V7K

C1562

DIS@

2

0.1U_0402_10V7K

DIS@

2

1

(26,27)

FBA_DQS[7..0]

Mode D - Mirror Mode Mapping

U1408 SIDE
C1561

1

0.1U_0402_10V7K

DIS@

2

C1560

1

1U_0402_6.3V6K

DIS@

2

C1559

1

1U_0402_6.3V6K

DIS@

2

C1558

1

1U_0402_6.3V6K

DIS@

2

C1557

1

1U_0402_6.3V6K

DIS@

2

C1556

1

1U_0402_6.3V6K

DIS@

2

C1553

1

0.1U_0402_10V7K

DIS@

2

C1554

1

0.1U_0402_10V7K

DIS@

2

C1552

1

0.1U_0402_10V7K

C1551

DIS@

2

0.1U_0402_10V7K

C1555

DIS@

0.1U_0402_10V7K

C1549

2

1

FBA_DQM[7..0]

+1.5VS_VGA

U1409 SIDE
1

(26,27)
(26,27)

Group6 (BOT)

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
DIS@

+1.5VS_VGA

(26,27)

FBA_DQS#[7..0]

2

(26) FBA_CLK1
(26) FBA_CLK1#
(26) FBA_CKE_H

+FBA_VREF1

M8
H1

1

FBA_CLK1

U1408

M8
H1

1

+1.5VS_VGA

CKE_H

FBx_CMD20

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

A13

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-VRAM
A Upper
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
28
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Memory Partition C - Lower 32 bits
FBC_D[0..63]

(26,30)

FBC_MA[15..0]

(26,30)

FBC_BA[2..0]

A

(26,30)

FBC_DQM[7..0]

(26,30)

FBC_DQS[7..0]

(26,30)

FBC_DQS#[7..0]

A

(26,30)

+1.5VS_VGA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

FBC_BA0
FBC_BA1
FBC_BA2

B

FBC_CLK0
1

(26) FBC_CLK0
(26) FBC_CLK0#
(26) FBC_CKE_L

R1498
160_0402_1%
N13P@
2

(26)
(26)
(26,30)
(26,30)
(26,30)

FBC_CLK0#

FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#

FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQSL
DQSU

E7
D3

DML
DMU

FBC_DQS#0
FBC_DQS#3

G3
B7

DQSL
DQSU

FBC_RST#

T2

C

R1534
243_0402_1%
N13P@

FBC_D28
FBC_D27
FBC_D31
FBC_D25
FBC_D29
FBC_D24
FBC_D30
FBC_D26

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

Group3 (BOT)

M8
H1

VREFCA
VREFDQ

FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBC_BA0
FBC_BA1
FBC_BA2

FBC_CLK0
FBC_CLK0#
FBC_CKE_L

J7
K7
K9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBC_DQM2
FBC_DQM1

E7
D3

DML
DMU

FBC_DQS#2
FBC_DQS#1

G3
B7

DQSL
DQSU

FBC_RST#

T2

RESET

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

RESET

L8

Group0 (IN3)

+FBB_VREF0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

2

R1535
10K_0402_5%
N13P@

1

1

(26,30) FBC_RST#

D7
C3
C8
C2
A7
A2
B8
A3

310mA

J7
K7
K9

FBC_DQM0
FBC_DQM3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

+1.5VS_VGA

FBC_CLK0
FBC_CLK0#
FBC_CKE_L

FBC_DQS0
FBC_DQS3

FBC_D4
FBC_D3
FBC_D7
FBC_D0
FBC_D5
FBC_D1
FBC_D6
FBC_D2

FBC_DQS2
FBC_DQS1

R1499
243_0402_1%
N13P@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
N13P@

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBC_D8
FBC_D15
FBC_D11
FBC_D12
FBC_D9
FBC_D13
FBC_D10
FBC_D14

Group2 (IN1)

Mode D - Mirror Mode Mapping
DATA Bus
Address

FBx_CMD0
Group1 (TOP)

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CK
CK
CKE/CKE0

FBx_CMD2

ODT_L

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

FBx_CMD13

WE#

BA0
WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

FBx_CMD16

B

CAS#
CS0#_H

FBx_CMD17
FBx_CMD18

ODT_H

FBx_CMD19

FBC_ODT_L
FBC_CKE_L

R1500
10K_0402_5%
N13P@

R1501
10K_0402_5%
N13P@

CKE_H

FBx_CMD20

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

A13
C

1

N13P@

2

1U_0402_6.3V6K

N13P@

2

C1596

1

1U_0402_6.3V6K

N13P@

2

C1595

1

1U_0402_6.3V6K

N13P@

2

C1594

1

1U_0402_6.3V6K

N13P@

2

C1593

1

1U_0402_6.3V6K

N13P@

2

C1588

1

0.1U_0402_10V7K

N13P@

2

C1591

1

0.1U_0402_10V7K

N13P@

2

C1586

1

0.1U_0402_10V7K

N13P@

2

C1585

1

0.1U_0402_10V7K

N13P@

2

C1592

1

0.1U_0402_10V7K

2

C1587

1

@

1U_0402_6.3V6K

2

C1583

1

@

1U_0402_6.3V6K

2

C1582

1

@

1U_0402_6.3V6K

N13P@

2

C1581

1

1U_0402_6.3V6K

N13P@

2

C1577

1

1U_0402_6.3V6K

N13P@

2

32..63

CS0#_L

U1411 SIDE
C1576

1

0.1U_0402_10V7K

N13P@

2

C1575

1

0.1U_0402_10V7K

2

C1580

1

@

0.1U_0402_10V7K

C1579

2

0.1U_0402_10V7K

1

@

0..31

FBx_CMD1

+1.5VS_VGA

C1574

0.1U_0402_10V7K

C1573

2

FBC_D16
FBC_D21
FBC_D18
FBC_D17
FBC_D20
FBC_D23
FBC_D19
FBC_D22

+1.5VS_VGA

U1410 SIDE
1

E3
F7
F2
F8
H3
H8
G2
H7

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
N13P@

+1.5VS_VGA

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

E3
F7
F2
F8
H3
H8
G2
H7

2

FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

VREFCA
VREFDQ

2

2

M8
H1

1

2

N13P@

2

1

0.01U_0402_16V7K

R1497
1.1K_0402_1%
N13P@

C1572

1

+FBB_VREF0

U1411

+FBB_VREF0

2

1

U1410
R1496
1.1K_0402_1%
N13P@

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-VRAM
C Lower
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
29
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Memory Partition C - Upper 32 bits
FBC_D[0..63]

(26,29)

FBC_MA[15..0]

(26,29)

FBC_BA[2..0]

A

(26,29)

FBC_DQM[7..0]

(26,29)

FBC_DQS[7..0]

(26,29)

FBC_DQS#[7..0]

U1413

1

+1.5VS_VGA

2

R1502
1.1K_0402_1%
N13P@
+FBB_VREF1

1

N13P@

R1503
1.1K_0402_1%
N13P@
2

2

0.01U_0402_16V7K

C1597

1

U1412

+FBB_VREF1

M8
H1

VREFCA
VREFDQ

FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

FBC_BA0
FBC_BA1
FBC_BA2

M2
N8
M3

BA0
BA1
BA2

FBC_CLK1
FBC_CLK1#
FBC_CKE_H

J7
K7
K9

CK
CK
CKE/CKE0

FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBC_DQS4
FBC_DQS5

F3
C7

DQSL
DQSU

FBC_DQM4
FBC_DQM5

E7
D3

DML
DMU

FBC_DQS#4
FBC_DQS#5

G3
B7

DQSL
DQSU

E3
F7
F2
F8
H3
H8
G2
H7

FBC_D39
FBC_D33
FBC_D38
FBC_D32
FBC_D36
FBC_D35
FBC_D37
FBC_D34

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBC_D47
FBC_D43
FBC_D46
FBC_D42
FBC_D40
FBC_D45
FBC_D44
FBC_D41

Group4 (IN1)

Group5 (TOP)

+FBB_VREF1

M8
H1

VREFCA
VREFDQ

FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

FBC_D60
FBC_D57
FBC_D63
FBC_D58
FBC_D61
FBC_D56
FBC_D62
FBC_D59

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

FBC_D54
FBC_D51
FBC_D55
FBC_D49
FBC_D52
FBC_D50
FBC_D53
FBC_D48

Group7 (IN3)

Group6 (BOT)

Mode D - Mirror Mode Mapping
DATA Bus

+1.5VS_VGA

Address

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBC_BA0
FBC_BA1
FBC_BA2

M2
N8
M3

BA0
BA1
BA2

FBC_CLK1
FBC_CLK1#
FBC_CKE_H

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBC_DQS7
FBC_DQS6

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBC_DQM7
FBC_DQM6

E7
D3

DML
DMU

FBC_DQS#7
FBC_DQS#6

G3
B7

DQSL
DQSU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

FBx_CMD0

R1504
160_0402_1%
N13P@
2

(26)
(26)
(26,29)
(26,29)
(26,29)

FBC_CLK1#

FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#

FBC_ODT_H
T2

RESET

L8

ZQ/ZQ0

FBC_RST#

T2

RESET

L8

ZQ/ZQ0

R1507
243_0402_1%
N13P@
2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

1

J1
L1
J9
L9

R1508
243_0402_1%
N13P@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

1

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
N13P@

1

N13P@

2

1U_0402_6.3V6K

N13P@

2

C1621

1

1U_0402_6.3V6K

N13P@

2

C1620

1

1U_0402_6.3V6K

2

C1619

N13P@

2

1

1U_0402_6.3V6K

@

C1618

1

1U_0402_6.3V6K

N13P@

2

C1613

1

0.1U_0402_10V7K

N13P@

2

C1617

1

0.1U_0402_10V7K

N13P@

2

C1616

1

0.1U_0402_10V7K

2

C1612

N13P@

2

1

0.1U_0402_10V7K

@

C1611

1

0.1U_0402_10V7K

N13P@

2

C1610

1

1U_0402_6.3V6K

N13P@

2

C1609

1

1U_0402_6.3V6K

N13P@

2

C1608

1

1U_0402_6.3V6K

C1607

N13P@

2

1U_0402_6.3V6K

N13P@

2

1

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

CAS#
CS0#_H
ODT_H

FBx_CMD19

U1412 SIDE

C1606

1

1U_0402_6.3V6K

N13P@

2

C1603

1

0.1U_0402_10V7K

N13P@

2

C1605

1

0.1U_0402_10V7K

N13P@

2

C1604

1

0.1U_0402_10V7K

N13P@

2

C1599

1

0.1U_0402_10V7K

C1598

N13P@

2

0.1U_0402_10V7K

C1602

1

ODT_L

FBx_CMD3

FBx_CMD18

+1.5VS_VGA

U1413 SIDE

B

FBx_CMD2

FBx_CMD17

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
N13P@

+1.5VS_VGA

32..63

CS0#_L

FBx_CMD16

1

1
2

R1506
10K_0402_5%
N13P@
2

R1505
10K_0402_5%
N13P@
C

FBC_RST#

(26,29) FBC_RST#

FBC_CKE_H

0..31

FBx_CMD1

1

FBC_CLK1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VS_VGA

B

(26) FBC_CLK1
(26) FBC_CLK1#
(26) FBC_CKE_H

A

(26,29)

C

CKE_H

FBx_CMD20

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

A13

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-VRAM
C Upper
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
30
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

1

1

R1518
20K_0402_1%
@
2

2

2

R1517
20K_0402_1%
@

4.99K_0402_1%

N13M@
SD034499180

1

1

R1523
10K_0402_5%
N13M@
2

R1522
4.99K_0402_1%
N13M@
2

R1521
4.99K_0402_1%
@
2

R1520
34.8K_0402_1%
N13M@
2

2

1

R1520

R1519
4.99K_0402_1%
@

Logical
Strapping Bit0

PCI_DEVID[4]

Logical
Strapping Bit2
SUB_VENDOR

Logical
Strapping Bit1

+3VS_VGA

SLOT_CLK_CFG

PEX_PLL_EN_TERM

ROM_SI

+3VS_VGA

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VS_VGA

FB[1]

FB[0]

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VS_VGA

USER[3]

USER[2]

USER[1]

USER[0]

STRAP1

+3VS_VGA

STRAP2

+3VS_VGA

PCI_DEVID[3]

PCI_DEVID[2]

PCI_DEVID[1]

PCI_DEVID[0]

STRAP3

+3VS_VGA

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

STRAP4

+3VS_VGA

PCIE_SPEED_
CHANGE_GEN3

PCIE_MAX_SPEED

DP_PLL_VDD33V

Physical
Strapping pin
ROM_SCLK

R1516

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

1

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

R1516
10K_0402_5%
N13P@

1

(23)
(23)
(23)
(23)
(23)

A

R1515
34.8K_0402_1%
@
2

2

R1514
45.3K_0402_1%
DIS@

1

1

1

+3VS_VGA

Pull-down to Gnd

10K

1001

0001

15K

1010

0010

20K

1011

0011

25K

1100

0100

30K

1101

0101

35K

1110

0110

45K

1111

0111

5K

R1526
4.99K_0402_1%
N13M@
2

2

R1525
4.99K_0402_1%
@

N13M @
N13P @

ZZZ2

ZZZ3

1

2

R1529
15K_0402_1%
N13P@

Samsung

S2G@
X7635439L02

0000

Hynix

Samsung

H1G@
X7635439L03

S1G@
X7635439L04

1

3GIO_PADCFG

No VBIOS ROM

XCLK_417

3GIO_PADCFG[3:0]

BIOS ROM is present (Default)

0110

FB_0_BAR_SIZE

Notebook Default

0

277MHz (Default)

1

Reserved

B

SLOT_CLK_CFG

2

1
2

R1528
29.4K_0402_1%
DIS@

N13M Mount
N13P Mount

FB Memory gDDR3

Hynix

H2G@
X7635439L01

3GIO_PAD_CFG_ADR[0]

ZZZ4

SUB_VENDOR

R1527
15K_0402_1%
X76@

Samsung
900MHz

ZZZ1

0

B

GPU

N13M Mount
N13P @

ROM_SI
ROM_SO
ROM_SCLK

1

(23) ROM_SI
(23) ROM_SO
(23) ROM_SCLK

1

1

1
2

R1524
15K_0402_1%
@

RESERVED

Pull-up to
+3VS_VGA
1000

Resistor Values

+3VS_VGA

3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]

A

45.3K_0402_1%

N13P@
SD034453280

Logical
Strapping Bit3

Power Rail

ROM_SO

N13M @
N13P Mount

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3

PD 20K

PD 15K

PU 45K

PD 45K

PU 10K

0

GPU and MCH don't share a common reference clock

1

Reserved

1

GPU and MCH share a common reference clock (Default)

2

256MB (Default)

SMBUS_ALT_ADDR

3

Reserved

0

0x9E (Default)

0

3D Device (Class Code 302h)

1

0x9C (Multi-GPU usage)

1

VGA Device (Default)

NC

NC

USER Straps

PU 45K(ES)

64Mx16

Reserved

STRAP4

K4W1G1646G-BC11
PD 10K

0

VGA_DEVICE

User[3:0]
Hynix
900MHz

H5TQ1G63DFR-11C
PD 10K

PD 15K

PD 15K

PU 45K

PD 45K

N13P-GL

Samsung
900MHz

Hynix
900MHz

PCIE_MAX_SPEED

NC

NC

1000-1100

Customer defined

K4W2G1646C-HC11
PD 10K

PD 15K

PD 45K

PU 45K

PD 45K

PU 10K

NC

NC

NC

NC

PEX_PLL_EN_TERM

0

Limit to PCIE Gen1

0

Disable (Default)

1

PCIE Gen 2/3 Capable

1

Enable

PU 45K(ES)

128Mx16
C

PU 10K
PU 45K(ES)

64Mx16

C

H5TQ2G63BFR-11C
PD 10K

PD 15K

PD 35K

PU 45K

PD 45K

PU 10K
PU 45K(ES)

128Mx16
X76

GPU

FB Memory gDDR3
Samsung
900MHz

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

PD 30K

PU 5K

PD 20K

PU 45K

PD 35K

PU 5K

PD 5K

PD 10K

PD 30K

PU 5K

PD 15K

PU 45K

PD 35K

PU 5K

PD 5K

PD 10K

PD 30K

PU 5K

PD 45K

PU 45K

PD 35K

PU 5K

PD 5K

PD 10K

PD 30K

PU 5K

PD 35K

PU 45K

PD 35K

PU 5K

PD 5K

PD 10K

K4W1G1646G-BC11
64Mx16

Hynix
900MHz

H5TQ1G63DFR-11C
64Mx16

N13M-GE1
Samsung
900MHz

K4W2G1646C-HC11
128Mx16

Hynix
900MHz

D

H5TQ2G63BFR-11C

D

128Mx16
9/27
from 15K to 5K

X76

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
N13X-MISC
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
31
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

LCD POWER CIRCUIT

W=60mils

1

1
2
FBMA-L11-201209-221LMA30T_0805
L2102

+3VS

1

3

AP2301GN-HF_SOT23-3

2 220K_0402_5%
C2107
0.1U_0402_16V4Z

6

4

2
R2103 1
5
Q2415B
2N7002KDWH_SOT363-6

Place closed to JLVDS1

1
2

4.7U_0805_10V4Z

2

2

3

C2101
4.7U_0805_10V4Z

PN:SP01000XE00

+LCDVDD_CONN

C2124

2

1

W=60mils

0.1U_0402_16V4Z

R2102
100K_0402_5%

+LCDVDD

C2109

R2101
150_0603_1%

2

A

Q2102

+3VS

+5VALW
1

1

+LCDVDD

LCD/LED PANEL Conn.

1

+LEDVDD

B+

C2103
0.1U_0402_16V4Z

2

C2113
4.7U_0805_25V6-K

10/06
1

PCH_ENVDD

Q2415A
2N7002KDWH_SOT363-6
1

1

2

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

9/19 Del R1010
DISPOFF#
INVPWM

11/14

@ R2106
100K_0402_5%
2

+3VS_CMOS

A LOGO RED LIGHT
CMOS

(35) DMIC_CLK
(35) DMIC_1_2
+3VS
(36,41) LOGO_LED#
+3VALW
(17) USB20_N5
(17) USB20_P5
(16) LVDS_ACLK
(16) LVDS_ACLK#

B

1

+3VS

D2101
1

2

@
2

R2113
4.7K_0402_5%
@

R1209 1

(16)
(16)
(16)
(16)
(16)
(16)

LVDS_A2
LVDS_A2#
LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#

(16)
(16)
(16)
(16)
(16)
(16)
(16)
(16)
(16)
(16)

LVDS_BCLK
LVDS_BCLK#
LVDS_B2
LVDS_B2#
LVDS_B1
LVDS_B1#
LVDS_B0
LVDS_B0#
EDID_DATA
EDID_CLK
+3VS
+LCDVDD_CONN

2 4.99K_0402_1%

LOGO_LED#
+3VALW_LOGO
USB20_N5
USB20_P5

EDID_DATA
EDID_CLK

RB751V-40_SOD323-2
2 0_0402_5%

1

1

2

R2116
10K_0402_5%
@

2

R2115
10K_0402_5%

1

2

2

C2112
680P_0402_50V7K
@

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

B

G6
G5
G4
G3
G2
G1

46
45
44
43
42
41

STARC_107K40-000001-G2

+3VS

DISPOFF#

1

R2114

(41) BKOFF#

1

JLCD1

(20 MIL)
2

(16) PCH_ENVDD

A

R2108
1
2
0_0805_5%

CONN@

R2118

1

2 10K_0402_5%

INVPWM

C2116

1

2 220P_0402_50V7K

INVPWM

C2125 @

1

2 1000P_0402_50V7K

INVPWM

C2117

1

2 220P_0402_50V7K

DISPOFF#

C

C

+3VS

1

+3VS

D2102
1

2

@
2

R2154
4.7K_0402_5%
@

R2104 1

2 2.2K_0402_5%

R2105 1

2 2.2K_0402_5%
C2110
10P_0402_50V8J
@

EDID_CLK
1

EDID_DATA
1

2

2

CMOS Camera Conn
C2111
10P_0402_50V8J
@

+3VS

RB751V-40_SOD323-2
R2107

2 0_0402_5%

1 R2150

3

1

1

R2137
10K_0402_5%
@

2

2

1
2

R2153
10K_0402_5%
@

CMOS SUSPEND 2.4mA
2 0_0603_5%

1

+3VALW

INVPWM

2

(16) PCH_PWM

1

+3VS_CMOS

(20 MIL)

Q2105
AP2301GN-HF_SOT23-3

(20 MIL)

(41) CMOS_ON#

C2114
0.1U_0402_16V4Z

C2123
0.1U_0402_16V4Z
@

R2119 1
2
150K_0402_5%

1

1

2

2

@ C2115
10U_0603_6.3V6M

4.7V
1

C2118
0.1U_0402_16V4Z

2

D

Compal Secret Data

Security Classification
Issued Date

D

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
LVDS
Connector
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
32
58
of
Date:
Sheet
Title

5

Rev
0.6

3

4

5

W=40mils

+5VS
2

+R_CRT_VCC
F2101
1.1A_6V_SMD1812P110TF
1
1
2

D2105

+CRT_VCC

W=40mils

3
RB491D_SOT23-3

A

A

CRT Connector

1

C2119
0.1U_0402_16V4Z

PN:DC060002L10

2

(16) DAC_GRN

DAC_RED

L2104

1

2 FCM1608CF-121T03_2P

RED

DAC_GRN

L2105

1

2 FCM1608CF-121T03_2P

GREEN

L2106

1

2 FCM1608CF-121T03_2P

1

1

2

2

2

1
2

10P_0402_50V8J

2

C2128

1

10P_0402_50V8J

2

C2127

1

10P_0402_50V8J

2

BLUE
C2126

1

10P_0402_50V8J

2

C2122

2

1

10P_0402_50V8J

R2122
150_0402_1%

C2121

R2120
R2121
150_0402_1% 150_0402_1%

1

10P_0402_50V8J

C2120

1

DAC_BLU

(16) DAC_BLU

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T16

16
17

R314
0_0603_5%

R319
0_0603_5%
2

CONN@
TE_2041480-1

+CRT_VCC
R2123

P

JVGA_HS

2 FCM1608CF-121T03_2P

JVGA_VS

CRT_HSYNC_1

4

C2130
10P_0402_50V8J
@

3

G

Y

+CRT_VCC

U2102
74AHCT1G125GW_SOT353-5

P

2

A

1

2

2

C2131
10P_0402_50V8J
@

1
2

1

@

2

CRT_DDC_CLK_CONN
1
2

C2134
68P_0402_50V8J
@

2 1K_0402_5%

Y

CRT_VSYNC_1

4

G

CRT_VSYNC

1

1

D2110

BLUE

C

3

I/O2

I/O4

6

2

GND

VDD

5

1

I/O1

I/O3

D2103

JVGA_VS

RED

@

2 0_0402_5%

R116 1

@

2 0_0402_5%

R117 1

@

2 0_0402_5%

R118 1

@

2 0_0402_5%

GREEN

4

2

GND

VDD

5

I/O3

4

+R_CRT_VCC

I/O1

CRT_DDC_DAT_CONN

1

1
CRT_DDC_DATA
5

R2125
4.7K_0402_5%
2

2

1

CRT_DDC_DAT_CONN

6

2N7002KDWH_SOT363-6

Q2107A

Chip
(16) CRT_DDC_CLK

JVGA_HS

+R_CRT_VCC

2
2

100P_0402_50V8J

C2153

100P_0402_50V8J

C2152

2

6

1

R2124
4.7K_0402_5%

(16) CRT_DDC_DATA

I/O4

AZC099-04S.R7G_SOT23-6

+3VS

1

I/O2

C

CRT_DDC_CLK_CONN

+3VS

1

3

+R_CRT_VCC

AZC099-04S.R7G_SOT23-6

D

R115 1

3

(16) CRT_VSYNC

B

1

R2127
5

2 0.1U_0402_16V4Z

OE#

C2135 1

CRT_DDC_DAT_CONN

68P_0402_50V8J

U2101
74AHCT1G125GW_SOT353-5

A

2 FCM1608CF-121T03_2P

1

C2133

2

1

L2110

100P_0402_50V8J

CRT_HSYNC

L2109

C2132

(16) CRT_HSYNC

2 1K_0402_5%

1

1

2 0.1U_0402_16V4Z
5

C2129 1

OE#

B

1

(16) DAC_RED

1

2

2

1

Conn
CRT_DDC_CLK

4

CRT_DDC_CLK_CONN

3

2N7002KDWH_SOT363-6

D

Q2107B

9/27 ESD
Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
CRT
Connector
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
33
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

A

A

1

+3VS

2

R2126
1M_0402_5%
2

G

Q2109
2N7002K_SOT23-3
1
1

D

S

3

(16) PCH_DPB_HPD

(16) PCH_DPB_P3

.1U_0402_16V7K

1

2 C2145

HDMI_CLK+

R2128
1
L2111
4

(16) PCH_DPB_N3

.1U_0402_16V7K

1

2 C2144

HDMI_CLK-

R2130

1

@

0_0402_5%

2
2

4

WCM-2012HS-900T
3 3

1

@

0_0402_5%

2

2

2

C2137
220P_0402_50V7K
@

HDMI Connector
PN:DC232001K10

+HDMI_5V

HDMI_R_CK+

2

1

1

R2129
20K_0402_5%

ESD request
Common mode choke 90ohm on these singals
Compal PN: SM070000K00
Vendor PN: WCM-2012-900T

2

+5VS

W=40mils

D2106
+HDMI_5V

1
3
RB491D-YS_SOT23-3

+HDMI_5V_OUT

1

F2102

HDMI_HPD

W=40mils

2

HDMI_SDATA
HDMI_SCLK

1.1A_6V_SMD1812P110TF
1

HDMI_R_CK-

B

C2136
0.1U_0402_16V4Z

HDMI_R_CK-

2
0_0402_5%

HDMI_R_D0+

2

4

WCM-2012HS-900T
3 3

(16) PCH_DPB_N2

.1U_0402_16V7K

1

2 C2142

HDMI_TX0-

R2132

1

@

2

0_0402_5%

HDMI_R_D0-

(16) PCH_DPB_P1

.1U_0402_16V7K

1

2 C2141

HDMI_TX1+

R2133

1

@

2

0_0402_5%

HDMI_R_D1+

4

3

.1U_0402_16V7K

1

2 C2140

HDMI_TX1-

R2134

(16) PCH_DPB_P0

.1U_0402_16V7K

1

2 C2139

HDMI_TX2+

R2135

1

@

2

1

1

@

2

L2114
4
(16) PCH_DPB_N0

.1U_0402_16V7K

1

2 C2138

HDMI_TX2-

R2136

1

2

4

3

1

@

2

+HDMI_5V

HDMI_R_D2+

WCM-2012HS-900T
3
0_0402_5%

HDMI_R_D1-

0_0402_5%

HDMI_R_D2+

R2148
2.2K_0402_1%

R2143
2.2K_0402_1%

R2145
2.2K_0402_5%

footprint check

R2146
2.2K_0402_5%

Chip

WCM-2012HS-900T
3

HDMI_SCLK

1
6
Q2111A
2N7002KDWH_SOT363-6

(16) HDMICLK_NB

2

0_0402_5%

B

SUYIN_100042GR019M23DZL
CONN@

2

2

(16) PCH_DPB_N1

HDMI_R_D1+
HDMI_R_D2+3VS

20
21
22
23

Conn
HDMI_SDATA

4
3
Q2111B
2N7002KDWH_SOT363-6

(16) HDMIDAT_NB
HDMI_R_D2-

C2146 @
47P_0402_50V8J

Place closed to JHDMI1

1

L2113
4

HDMI_R_D0+
HDMI_R_D1-

1

2

2 0_0805_5%

2

1

@

1

1

R2149 1

2

1

HDMI_R_CK+
HDMI_R_D0-

2

2

1

@

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

2

1
L2112
4

1

1

R2131

2

HDMI_TX0+

JHDMI1

2

2 C2143

5

1

1

.1U_0402_16V7K

2

(16) PCH_DPB_P2

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C2147
@
47P_0402_50V8J

C

C

2 680_0402_5%
2 680_0402_5%

HDMI_TX1- R2139 1
HDMI_TX1+ R2140 1

2 680_0402_5%
2 680_0402_5%

HDMI_TX0- R2141 1
HDMI_TX0+ R2142 1

2 680_0402_5%
2 680_0402_5%

HDMI_CLK- R2151 1
HDMI_CLK+ R2147 1

2 680_0402_5%
2 680_0402_5%

HDMI_GND

D2113

1

HDMI_TX2- R2144 1
HDMI_TX2+ R2152 1

UMA 680_0402_5%

D
+3VS

2

Q2110
2N7002K_SOT23-3

G
3

S

D2112

D2108

HDMI_HPD

1 

 9

HDMI_HPD

HDMI_R_CK-

1 

 9

HDMI_R_CK-

HDMI_R_D2-

1 

 9

HDMI_R_D2-

HDMI_SDATA

2 

 8

HDMI_SDATA

HDMI_R_CK+

2 

 8

HDMI_R_CK+

HDMI_R_D2+

2 

 8

HDMI_R_D2+

HDMI_SCLK

4 

 7

HDMI_SCLK

HDMI_R_D1-

4 

 7

HDMI_R_D1-

HDMI_R_D0-

4 

 7

HDMI_R_D0-

+HDMI_5V_OUT

5 

 6

+HDMI_5V_OUT

HDMI_R_D1+

5 

 6

HDMI_R_D1+

HDMI_R_D0+

5 

 6

HDMI_R_D0+

3 

3 

8

3 

8

YSCLAMP0524P_SLP2510P8-10-9

9/27 ESD

8

YSCLAMP0524P_SLP2510P8-10-9

YSCLAMP0524P_SLP2510P8-10-9

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
HDMI
Connector
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
34
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
D2417

+3VS

FILT_1.65_R

C1121
0.1U_0402_16V4Z

1

1

To support Wake-on-Jack or Wake-on-Ring, the CODEC
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed.
*DSH page42 has more detail.

RB751V-40_SOD323-2
1

C1119
4.7U_0603_6.3V6K
@

5

C1135

1

2 1U_0402_6.3V6K

C1136

1

2 0.1U_0402_16V4Z

+LDO_OUT_3.3V_R C1133

1

2 4.7U_0603_6.3V6K

C1134

1

2 0.1U_0402_16V4Z

Layout Note:Path from +5VS to Pin12,
Pin15 must be very low
resistance (<0.01 ohms)

2

2

4

2

A

3

Near Pin 29

A

Near Pin 27

Near Pin 2

AVDD_3.3 pinis output of internal LDO. NOT connect
to external supply.

1

1

1

2

Near Pin 28

1

+3VS

1
2

2

C1132
0.1U_0402_16V4Z

C1130
4.7U_0603_6.3V6K

Near Pin 3

C1129
0.1U_0402_16V4Z

2

R1121
10K_0402_5%

@
C1112
4.7U_0603_6.3V6K

FILT_1.8_R

10 mils
1

2

RB751V-40_SOD323-2

C1113
0.1U_0402_16V4Z

Near Pin 7

2

0.1U_0402_16V4Z
D2416

+5VS
C1114
1U_0402_6.3V6K
@

1

C1116
0.1U_0402_16V4Z

1

PC Beep

2 @

1

2 0.1U_0402_16V4ZPC_BEEP

2

C1142

(13) HDA_SPKR

PC_BEEP_C C1111 1

2

0.1U_0402_16V4Z

ICH Beep

2 33_0402_5%

1

PC_BEEP_C_R R1120 1

1

2 @

1

2

C1141

(41) BEEP#

2

EC Beep

C1124
4.7U_0603_6.3V6K

1
D

3

S

Q1103
LBSS138LT1G_SOT-23-3
R1130 1
2
G
1
C1146
1U_0402_6.3V6K

R1112 1

+3VS
(13) HDA_RST#_AUDIO
2 33K_0402_5%

EXT_MIC

(13)
(13)
(13)
(13)

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_SDIN0
HDA_SDOUT_AUDIO

@

2 4.7K_0402_5%

R1115 1

2 33_0402_5%

HDA_RST#_AUDIO

9

RESET#

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO

5
8
6
4

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

HDA_SDOUT_AUDIO

2

PLUG_IN

CX_GPIO0
1
2

R1129 1

@

EAPD active low
0=power down ex AMP
1=power up ex AMP

2 33K_0402_5%

C1147
1U_0402_6.3V6K
@

R1111
R1131

(41) EAPD
(41) EC_MUTE#

Internal DMIC

PC_BEEP

2 0_0402_5%
2 0_0402_5%

1
1

CX_GPIO0

R1125
1
2
FBMA-10-100505-301T_2P

(32) DMIC_CLK
(32) DMIC_1_2

10

SENSE_A

36

SENSE_A

PORTB_R
PORTB_L
B_BIAS

35
34
33

PORTB

C_BIAS
PORTC_R
PORTC_L

32
31
30

PORTA_R
PORTA_L

23
22

DMIC_CLK
DMIC_1/2

SPK_L2+
SPK_L1-

11
13

LEFT+
LEFT-

NC
NC
NC

24
25
39

SPK_R2+
SPK_R1-

16
14

RIGHT+
RIGHT-

AVEE
FLY_P
FLY_N

21
19
20

C1107 1

C

41

Decoupling CAP

R1113 1
R1114 1
R1116 1

C1108

+CLASSD_5V

1

@

2

0_0805_5%

+5VS
B

2 5.11K_0402_1%
MIC_JD
2 20K_0402_1%
2 39.2K_0402_1% PLUG_IN
2 2.2U_0402_6.3V6M

1

R1122

2 0.1U_0402_16V4Z

PLUG_IN

Port B
Port A

(39)

2 100_0402_1% EXT_MIC

R1133 1

1109

+3VS

EXT_MIC (39)

External MIC

+MICBIASB

29

+MICBIASB

GPIO0/EAPD#
GPIO1/SPK_MUTE#

40
1

Sense resistors must be
connected same power
that is used for
VAUX_3.3

27
28
26

12
15
17

PC_BEEP

DMIC_CLK_R

Near Pin 17

LPWR_5.0
RPWR_5.0
CLASS-D_REF

EXT_MIC R1132 1

HP_OUTR_R R1117
HP_OUTL_R R1118

2 2K_0402_5%

1
1

R1128

HP_OUTR
HP_OUTL

39_0402_5%
39_0402_5%

2
2

2 4.7K_0402_5%

1

Headphone

HP_OUTR (39)
HP_OUTL (39)

Changed from 5.1ohm to 15ohm
for "zi zi"noise.
AVEE
FLY_P
FLY_N

C1110

1

2

C1122

1

2 0.1U_0402_16V4Z

C1125

1

2 4.7U_0603_6.3V6K

Near Pin 21

1U_0402_6.3V6K

GND

Internal SPEAKER

38
37

FILT_1.65

B

AVDD_3.3
AVDD_5V
AVDD_HP

MIC_JD

U1101

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

Combo Jack detect (normal open)

10K only needed if supply to VAUX_3.3
is removed during system re-start.

3
7
2
18

Near Pin 26

CX20671-21Z_QFN40_6X6
C

+CLASSD_5V
C1115

1

2 0.1U_0402_16V4Z

C1117

1

2 10U_0603_6.3V6M

C1118

1

2 0.1U_0402_16V4Z

C1120 @1

2 10U_0603_6.3V6M

Near Pin 12
Near Pin 15

Internal Speaker

EMC request
Bead 120ohm on these singals
Compal PN: SM010016720
Vendor PN: FBMA-L11-160808-121LMT

SP02000N010
SP02000SM10

Rdc < 0.05 ohms
Rated Current > 2A
SPK_R1SPK_R2+
SPK_L1SPK_L2+

L1102
L1103
L1104
L1105

1
1
1
1

2
2
2
2

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

EMI

1

2 0.1U_0402_16V4Z

C1123 @1

2 22P_0402_50V8J

HDA_SYNC_AUDIO

C1126 @1

2 22P_0402_50V8J

R1102 1

@

2 0_0402_5%

HDA_SDOUT_AUDIO

C1128 @1

2 22P_0402_50V8J

R1104 1

@

2 0_0402_5%

C1131

2 22P_0402_50V8J

R1105 1

@

2 0_0402_5%

HDA_BITCLK_AUDIO R1123

1

2 33_0402_5%

HDA_BITCLK_AUDIO_R

1

GND
1

2

GND

Compal Secret Data

Security Classification
Issued Date

9/28 RF modify

2

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GNDA
3

4

@

2

@

2

1

@

2

1

SPK_R2+_CONN

2

2

SPK_L1-_CONN

3

3

SPK_L2+_CONN

4

4

5

GND

6

GND

1000P_0402_50V7K

C1104

@

C1140

2 0.1U_0402_16V4Z

1

1000P_0402_50V7K

1

C1139

C1103

EMI

1

1000P_0402_50V7K

HDA_RST#_AUDIO

2 0.1U_0402_16V4Z

C1138

EMI

1

1

1000P_0402_50V7K

D

C1102

C1137

Width 20 mil

JSPK1

SPK_R1-_CONN

1

ACES_87302-0401-003
CONN@

Compal Electronics, Inc.
HD
Audio
Codec CX20671
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
35
58
of
Date:
Sheet

D

Title

5

Rev
0.6

1

2

3

4

5

SATA HDD CONN.

Card Reader CONN.
PN:DC010004C00
JHDD1

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

(13) SATA_PTX_DRX_P0
(13) SATA_PTX_DRX_N0
A

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0

(13) SATA_DTX_C_PRX_N0
(13) SATA_DTX_C_PRX_P0

C2401 1
C2402 1

SATA_DTX_PRX_N0
SATA_DTX_PRX_P0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+3VS

@ J2401
1

1

2

5VS_HDD

2

JUMP_43X79

+5VS

2

1
2

14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

(14) PCIE_PRX_DTX_P1
(14) PCIE_PRX_DTX_N1
(14) CLK_PCIE_CARD
(14) CLK_PCIE_CARD#
(14)
(14)
(14)
(5,14,17,22,38,40,41)

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
CARD_CLKREQ#
PLT_RST#
+3VALW
(32,41) LOGO_LED#

GND
GND

11/15 del R2414
㨇㥳⸚㴱

23
24

JCARD1

A

14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_87213-1400G
CONN@

10/06
change PN to SP02000H810
footprint: ACES_87213-1400G_14P

SANTA_198202-1
CONN@

10U_0603_6.3V6M

@

C2406

1

1U_0402_6.3V6K

2

C2405

@

1000P_0402_50V7K

C2403

1

PN:SP01001BF00

GND
A+
AGND
BB+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

(41) HDD_DETECT#
+5VS

1
2
3
4
5
6
7

Pin 18 to GND for Gen 3

B

B

SATA ODD CONN.

APS G-Sensor

PN:SP01000TU10
1

for Edge 14''
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1

(13) SATA_DTX_C_PRX_N1
(13) SATA_DTX_C_PRX_P1

C2408 1
C2409 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

S

D

Vs
Vs

2

3
5
6
7

NC
NC
NC
NC
NC
NC

1
4
9
11
13
16

COM
COM
COM
COM

1
2

1
2

GS_VOUTX (41)
GS_VOUTY (41)

1
2

1
2

.1U_0402_16V7K

2

SANTA_204901-1
CONN@

ODD_DETECT#_R

14
15

2 56K_0402_5%
2 56K_0402_5%

1
1

C2415

3

15
14

1

R2403
R2404

.1U_0402_16V7K

1

(13) ODD_DET#

GND
GND

11/17
BOM modify

1

VOUTX
VOUTY

C2412

Q2406
2N7002K_SOT23-3

2 0_0603_5%

12
10
8

.1U_0402_16V7K

ODD_DA#_R

@

Xout
Yout
Zout

C2414

ODD_DA#_R

R2405 1

ST

+3VS_GS

.1U_0402_16V7K

(17) ODD_DA#

C

2 0_0402_5%

DP
+5V
+5V
MD
GND
GND

2

C2411

R2406 1

8
9
10
11
12
13

U2401

.1U_0402_16V7K

ODD_DETECT#_R
+5VS_ODD

(41) GS_SELFTEST
+3VS

C2410

+5VS_ODD

+5VS_ODD

R2402
100K_0402_5%

10U_0603_6.3V6M

SATA_DTX_PRX_N1
SATA_DTX_PRX_P1

GND
A+
AGND
BB+
GND

C2413

SATA_DTX_PRX_N1
SATA_DTX_PRX_P1

1
2
3
4
5
6
7

2

JODD1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

(13) SATA_PTX_DRX_P1
(13) SATA_PTX_DRX_N1

C

APS_GND

LIS34ALTR_LGA16_4X4
APS_GND

@

@

2

G

1

J2402

2

2MM

(14) ON_ODD_DET

APS_GND

+5VS_ODD

D

S
G

2

3

2

SI3456DDV-T1-GE3_TSOP6

@

2

1
2

C2155

1

3

11/17
@
R2138
150K_0402_5%

ODD_EN

(41)

GS_ON#

GS_ON#

1

1
D

D
2

Q2403
2N7002K_SOT23-3

1
R2411
1.5M_0402_5%

G
S
2

ODD_EN#

3

(18)

+3VS_GS
Q2402
AP2301GN-HF_SOT23-3

2 220P_0402_50V7K

10U_0603_6.3V6M

Q2401

1

C2407

1

4

0.1U_0402_16V4Z

C2416
1U_0402_6.3V6K

6
5
2
1

C2425

R2408
470K_0402_5%

+3VS
ODD_DA#

2 0_0805_5%

1

1
1

1
C2426
0.01U_0402_16V7K
2 @

2

2
0_0603_5%

C2417
0.1U_0402_16V4Z

1
2

C2420
10U_0603_6.3V6M
@

R2410
1
2
150K_0402_5%
D

1

C2419
0.1U_0603_25V7K

2

2

Issued Date

C2418
0.01U_0402_16V7K

Compal Secret Data

Security Classification

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

R2409

2

@

1

R2407 1

1

+5VS

2

+VSB

2

3

4

Compal Electronics, Inc.
HDD/ODD/Card
reader/G-Sensor
Size Document Number
Rev
Custom
0.6
LA-8131P
Friday, January 06, 2012
36
58
of
Date:
Sheet
Title

5

1

2

3

4

5

USB 3.0 Conn.
+USB_VCCA

U2405
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

2

G547I2P81U_MSOP8

1
2

USB20_P1

3

L2403
2
3

1

1

USB20_N1_C

USB3TXDP1 3

4

4

USB20_P1_C

USB3TXDN1 2

WCM-2012-900T_4P

USB_OC0#

2

(17) USB3_TX1_P
1

I/O1

I/O3

4

GND

VDD

5

I/O2

I/O4

6

(17) USB3_TX1_N
(17) USB20_P1

USB20_P1_C
+USB_VCCA

2

USB3_TX1_C_P

USB3_RX1_P

1

1

USB3_TX1_C_N

USB3_RX1_N 2

3

L2405
3
2

4

4

USB3_RX1_C_P

1

1

USB3_RX1_C_N

1
+
2

WCM-2012HS-900T

C2443 1

2 0.1U_0402_10V6K

USB3TXDP1 0_0402_5%

1

@

2 R2423

USB3_TX1_C_P

C2442 1

2 0.1U_0402_10V6K

USB3TXDN1 0_0402_5%
0_0402_5%

1
1

@
@

2 R2424
2 R2420

USB3_TX1_C_N
USB20_P1_C

0_0402_5%
0_0402_5%

1
1

@
@

2 R2419
2 R2463

USB20_N1_C
USB3_RX1_C_P

0_0402_5%

1

@

2 R2464

USB3_RX1_C_N

(17) USB20_N1
(17) USB3_RX1_P
(17) USB3_RX1_N

9/27 ESD
3

4

PN: SM070001S00 x 2

(17)
D2405

4

WCM-2012HS-900T

PN: SM070000K00 x 1

C2448
1000P_0402_50V7K
@

L2404
3

9
1
8
3
7
2
6
4
5

470P_0402_50V7K

USB_ON#

1
2
3
4

2

C2435

C2447
0.1U_0402_16V4Z
1
2

C2215

A

1

1000P_0402_50V7K

Low Active

USB20_N1

150U_B2_6.3VM_R35M

+USB_VCCA

C2434

W=80mils
+5VALW

1
2

D2410

USB3_TX1_C_P

1 

 9

USB3_TX1_C_P

USB3_TX1_C_N

2 

 8

USB3_TX1_C_N

USB3_RX1_C_P

4 

 7

USB3_RX1_C_P

USB3_RX1_C_N

5 

 6

USB3_RX1_C_N

JUSB1

A

3 

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

8
YSCLAMP0524P_SLP2510P8-10-9
GND
GND
GND
GND

10
11
12
13

ACON_TARA4-9K1311
CONN@

USB20_N1_C

AZC099-04S.R7G_SOT23-6

PN:DC23300AS20

PN: SC300001G00

D2411

USB20_N2

2

B

W=80mils
+5VALW

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

2

8
7
6
5

G547I2P81U_MSOP8

2

3

4

USB20_N2_C

1

USB20_P2_C

4

USB3TXDP2 3

C2424
1000P_0402_50V7K
@

3

USB3TXDN2 2

2

4
1

WCM-2012HS-900T

(17) USB3_TX2_P
(17) USB3_TX2_N
(17) USB20_P2
USB_OC1#

1

1

L2406

PN: SM070000K00 x 1

C2216

USB_ON#

U2409

1

1000P_0402_50V7K

USB_ON#

1
2
3
4

3

2

WCM-2012-900T_4P

+USB_VCCB

Low Active
C2421
0.1U_0402_16V4Z
1
2
(41)

USB20_P2

L2402

4
1

USB3_TX2_C_P

USB3_RX2_P3

USB3_TX2_C_N

USB3_RX2_N2

PN: SM070001S00 x 2

USB20_P2_C

1

I/O1

I/O3

4

GND

VDD

5

I/O4

6

4

2

1

4
1

USB3_RX2_C_P
USB3_RX2_C_N

+USB_VCCB

1 

 9

USB3_TX2_C_P

USB3_TX2_C_N

2 

 8

USB3_TX2_C_N

USB3_RX2_C_P

4 

 7

USB3_RX2_C_P

USB3_RX2_C_N

5 

 6

USB3_RX2_C_N

WCM-2012HS-900T

B

3 
8

1

2 C2511 USB3TXDP2 0_0402_5%

1

@

2 R2425

USB3_TX2_C_P

0.1U_0402_10V6K

1

2 C2446 USB3TXDN2 0_0402_5%
0_0402_5%

1
1

@
@

2 R2426
2 R2421

USB3_TX2_C_N
USB20_P2_C

0_0402_5%
0_0402_5%

1
1

@
@

2 R2422
2 R2465

USB20_N2_C
USB3_RX2_C_P

1

@

2 R2466

USB3_RX2_C_N

0_0402_5%

(17) USB3_RX2_N
D2403

3

0.1U_0402_10V6K

(17) USB20_N2
(17) USB3_RX2_P

(17)

L2407

USB3_TX2_C_P

9
1
8
3
7
2
6
4
5

YSCLAMP0524P_SLP2510P8-10-9

JUSB2
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

ACON_TARA4-9K1311
CONN@
+USB_VCCB

2

3

I/O2

PN:DC23300AS20

9/27 ESD
USB20_N2_C

AZC099-04S.R7G_SOT23-6

PN: SC300001G00

C

C

+USB_VCCB

3

4

1
4

USB20_P3_C

L2408

USB3TXDP3 3

USB20_N3_C

3

USB3TXDN3 2

WCM-2012-900T_4P

2

4
1

4
1

USB3_TX3_C_P
USB3_TX3_C_N

USB3_RX3_P3
USB3_RX3_N2

WCM-2012HS-900T

PN: SM070000K00 x 1

L2409
3

4

2

1

1

4
1

USB3_RX3_C_P

+
2

USB3_RX3_C_N

WCM-2012HS-900T

1
2

470P_0402_50V7K

3

1

C2423

2

150U_B2_6.3VM_R35M

USB20_N3

L2401

2

C2422

USB20_P3

1 

 9

USB3_TX3_C_P

USB3_TX3_C_N

2 

 8

USB3_TX3_C_N

USB3_RX3_C_P

4 

 7

USB3_RX3_C_P

USB3_RX3_C_N

5 

 6

USB3_RX3_C_N

3 
8

PN: SM070001S00 x 2
(17) USB3_TX3_P
(17) USB3_TX3_N
(17) USB20_P3

YSCLAMP0524P_SLP2510P8-10-9

0.1U_0402_10V6K

1

2 C2445 USB3TXDP3 0_0402_5%

1

@

2 R2461

USB3_TX3_C_P

0.1U_0402_10V6K
USB20_P3

1

2 C2444 USB3TXDN3 0_0402_5%
0_0402_5%

1
1

@
@

2 R2462
2 R2413

USB3_TX3_C_N
USB20_P3_C

0_0402_5%
0_0402_5%

1
1

@
@

2 R2412
2 R2467

USB20_N3_C
USB3_RX3_C_P

0_0402_5%

1

@

2 R2468

USB3_RX3_C_N

USB20_N3

(17) USB20_N3
(17) USB3_RX3_P
(17) USB3_RX3_N

D2415

USB3_TX3_C_P

9
1
8
3
7
2
6
4
5

JUSB3
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

ACON_TARA4-9K1311
CONN@
D

USB20_P3_C

1

D

D2401
I/O1

I/O3

4

2

GND

VDD

5

3

I/O2

I/O4

6

PN:DC23300AS20

+USB_VCCB

9/27 ESD

Issued Date

AZC099-04S.R7G_SOT23-6

2

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PN: SC300001G00
1

Compal Secret Data

Security Classification

USB20_N3_C

3

4

Compal Electronics, Inc.
USB
3.0
Connector
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
37
58
of
Date:
Sheet
Title

5

Rev
0.6

2

3

Mini-Express Card for WLAN/WiMAX(Half)

9/19

(40,41) EC_TX_P80_DATA
(40,41) EC_RX_P80_CLK

2 R2470
1K_0402_5%

1

R2432
R2433

2 100_0402_1%
2 100_0402_1%

1
2

2

1
2

500

375

5 (Not wake enable)

SMB_CLK_S3
SMB_DATA_S3

USB20_N10
USB20_P10

(17)
(17)

+3VALW

+VSB

For AOAC assessment

C2509
1U_0402_6.3V6K
AOAC@

2

@

2
R2483

1

1
3

S

+3VS_WWAN

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB_R

RX_1P
RX_1N

SATA_DTX_PRX_P2
SATA_DTX_PRX_N2

5
4

TX_2P
TX_2N

PE1
PE2

3
13
17
18
19
21

GND
GND
GND
GND
GND
PAD

@

Q2412
2N7002K_SOT23-3

R2436
@
1
2
10K_0402_5%

D2406

R2449 1
R2455 1
R2456 1
R2457 1
R2458 1
R2459 1
R2428 1

2
2
2
2
2
2
2

LPC_FRAME# (13,40,41)
LPC_AD3 (13,40,41)
LPC_AD2 (13,40,41)
LPC_AD1 (13,40,41)
LPC_AD0 (13,40,41)
CLK_PCI_DB

(17,40)

+UIM_PWR
@

I/O2

I/O4

6

2

GND

VDD

5

1

I/O1

I/O3

4

+3VS

+3VS

AZC099-04S.R7G_SOT23-6

JSIM1

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
CLK_PCI_DB

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

GND
VPP
I/O
DET

2 10K_0402_5%

VCC
RST
CLK

1
2
3

GND
GND

8
9

40mil

+UIM_PWR
UIM_RST
UIM_CLK

3G@ C2457
4.7U_0603_6.3V6K

@

D2407

1

3

C

2

DAN217T146_SC59-3
1

1

2

2

3G@ C2458
0.1U_0402_16V4Z

TAITW_PMPAT6-06GLBS7N14H0
CONN@

PS8520B
pin 17 B_PRE1 4.7K pull up NC
Pin 19 A_PRE1 4.7Kpull up NC
Pin 18 test pin
L:Normal operation
H:Test mode

6
10
16
20
9
8

2

PEXTN

1
2

PS8520B
pin8 B_PRE0 4.7K NC
pin9 A_PRE0 4.7K NC

1

1

1

+3VS

R2441
4.7K_0402_5%
@

A_PRE1

R2460
R2438

2
2

B_PRE1

R2471
R2472

2
2

TEST

R2475
R2476

2
2

R352
R353

2
2

R2442
4.7K_0402_5%
@
PEXTN
PS8131B
pin 20 PEXTN 4.99K pull low to GND

TX_1P
TX_1N

15
14

SATA_ITX_DRX_P2_C
SATA_ITX_DRX_N2_C

C2463
C2464

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_ITX_DRX_P2_R
SATA_ITX_DRX_N2_R

RX_2N
RX_2P

12
11

SATA_DTX_IRX_N2_C
SATA_DTX_IRX_P2_C

C2466
C2465

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N2_R
SATA_DTX_IRX_P2_R

@

@

@

+3VS
1 4.7K_0402_5%
1 0_0402_5%
1 4.7K_0402_5%
1 0_0402_5%
1 4.7K_0402_5%
1 0_0402_5%
D

Issued Date

@

1 0_0402_5%
1 4.99K_0402_1%

Compal Secret Data

Security Classification

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SN75LVCP412ARTJR_QFN20_4X4
1

1 3G@

(17)
(17)

2

1
2

B_PRE1
TEST
A_PRE1

1
2
2

SATA_PTX_DRX_P2
SATA_PTX_DRX_N2

VCC
VCC
VCC
VCC

0.01U_0402_16V7K

EN

R2439

C2513

PN:SP07000LM00

0.01U_0402_16V7K

0.01U_0402_16V7K
C2462 1
2
C2461 1
2

7

4
5
6
7

(18)

+3VS

C2460

(13) SATA_DTX_C_PRX_P2
(13) SATA_DTX_C_PRX_N2

2 4.7K_0402_5%

3G_OFF#

USB20_N12
USB20_P12

0.1U_0402_16V4Z

(13) SATA_PTX_DRX_P2
(13) SATA_PTX_DRX_N2

1

U2406

3

SMB_CLK_S3
SMB_DATA_S3

C2459

PS8520B
internal pull up 150K
R2440

54

2

BT@

B

C2501
.1U_0603_25V7K
2
AOAC@

UIM_VPP
UIM_DATA

PLT_RST#

BELLW_80003-7021
CONN@

+3VS

D

GND2

@

S
1

2

Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.

UIM_DATA

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

2

GND1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

1

G

BT@

Q2400
SI3456DDV-T1-GE3_TSOP6
AOAC@

47P_0402_50V8J

53

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

C2456

(18) mSATA_PCH

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

@

1

0.1U_0402_16V4Z

+3VS_WWAN

(18) 3G_DET#

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2

1

2

2

BT@

1

R2481
1.5M_0402_5%
AOAC@

2

C2506 C2507
1
1

4

+1.5VS

C2454

11/15

1

2
4
6
8
10
12
14
16

R2477
470_0402_5%
@

BT@
2 0.1U_0402_16V4Z

1

+1.5VS

1

2 0_0805_5%

11/15

+3VS_WWAN

47P_0402_50V8J

P23 B+
SATA_DTX_IRX_P2_R
SATA_DTX_IRX_N2_R
P25 BP32 ASATA_ITX_DRX_N2_R
SATA_ITX_DRX_P2_R

2
4
6
8
10
12
14
16

1

100K_0402_5%

1
2
0_0402_5%
AOAC@

2

2
G
Q2404
2N7002K_SOT23-3
AOAC@

6
5
2
1

1

WLAN_EN

BT_ON# R2109

BT_ON#

+3VS_AOAC
R2485 1

R2482
470K_0402_5%
AOAC@

C2453

C

1
3
5
7
9
11
13
15

+3VAUX_BT

D
(18)

9/19

11/15

JMINI1
1
3
5
7
9
11
13
15

(17)
(17)

BT_DET# (17)

SMB_CLK_S3 (11,12,14,39)
SMB_DATA_S3 (11,12,14,39)

10U_0603_6.3V6M

2 0_0402_5%

USB20_P13
USB20_N13

RF_OFF# (41)
PLT_RST# (5,14,17,22,36,40,41)

C2451

@

1

2 0_0402_5%
2 0_0402_5%

3

RF_OFF#
PLT_RST#

D

WLAN_WAKE# R2437

R2473 1
R2474 1

Q2411
BT@
AP2301GN-HF_SOT23-3

(41) AOAC_WLAN

@ J2404
JUMP_43X79

USB20_P13_R
USB20_N13_R

+3VS

from EC

PN:SP07000JP00

70mA

A

if AOAC enable +3VS_AOAC always ON
if AOAC disable +3VS_AOAC same +3VS

+3VS

1
2
3
4
5
6

ACES_50224-00601-001
CONN@

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

BELLW_80003-7021
CONN@

Mini-Express Card for WWAN/mSATA(Full)

7
8

1
2
3
4
G1 5
G2 6

1

54

+1.5VS

JBT1

1 2

GND2

250 (wake enable)

2

GND1

For EC to detect
R2435
debug card
100K_0402_5%
insert.

B

2

53

1

(18) WLBT_OFF_51#

1
1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

250

D

EC_TX_P80_DATA
EC_RX_P80_CLK

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

330

10U_0603_6.3V6M

+3VS_AOAC

9/19

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

+3V

0.1U_0402_16V4Z

(14) PCIE_PTX_C_DRX_N2
(14) PCIE_PTX_C_DRX_P2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

750

S

PCI_RST#_R
CLK_PCI_DB_R

Normal

1000

G

2 1K_0402_5%

1

2
4
6
8
10
12
14
16

Normal

Peak

2

R2427

(14) PCIE_PRX_DTX_N2
(14) PCIE_PRX_DTX_P2

1
3
5
7
9
11
13
15

2

BT Connector
+3VAUX_BT

Auxiliary Power (mA)

3

(14) CLK_PCIE_WLAN1#
(14) CLK_PCIE_WLAN1

(17) BT_DET#

5

+3VS

1

2 0_0402_5% BT_OFF#_R

2

1

0.1U_0402_16V4Z

WLBT_OFF_5# R2434 1
WLAN_CLKREQ1#

(13) WLBT_OFF_5#
(14) WLAN_CLKREQ1#

2
4
6
8
10
12
14
16

1

C2455

(41) WLAN_WAKE#

JMINI2

1
3
5
7
9
11
13
15

J2406
JUMP_43X79
@

+1.5VS

10U_0603_6.3V6M

11/21
WLAN_WAKE#

+3VS_AOAC

C2452

J2403
JUMP_43X79
@

+3VS_AOAC +1.5VS

1

+3VALW

1

+3VS

Primary Power (mA)

Power

9/19

Mini-Express Card(WLAN/WiMAX)
PN:SP07000JP00

A

4

Mini Card Power Rating

3

1

2

3

4

Compal Electronics, Inc.
WLAN
and WWAN/mSATA
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
38
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Click pad

INT_KBD Conn.

Track point

PN:SP01001AL00

PN:SP01001CH00
+5VS

PN:SP01000YH00

1

2 @100P_0402_50V8J

C2469 1

2 @100P_0402_50V8J

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

(41)

2 @100P_0402_50V8J

KSO1

C2471

2 @100P_0402_50V8J

1

KSO15

C2472

1

2 @100P_0402_50V8J

KSO7

C2473

1

2 @100P_0402_50V8J

KSO6

C2476

1

2 @100P_0402_50V8J

KSI2

C2477

1

2 @100P_0402_50V8J

KSO8

C2478

1

2 @100P_0402_50V8J

KSO5

C2479

1

2 @100P_0402_50V8J

KSO13

C2480

1

2 @100P_0402_50V8J

KSI3

C2481

1

2 @100P_0402_50V8J

KSO12

C2482

1

2 @100P_0402_50V8J

KSO14

C2483

1

2 @100P_0402_50V8J

KSO11

C2484

1

2 @100P_0402_50V8J

KSI7

C2485

1

2 @100P_0402_50V8J

KSO10

C2486

1

2 @100P_0402_50V8J

KSI6

C2487

1

2 @ 100P_0402_50V8J

KSO3

C2488

1

2 @100P_0402_50V8J

KSI5

C2489

1

2 @100P_0402_50V8J

KSO4

C2490

1

2 @100P_0402_50V8J

KSI4

C2491

1

2 @100P_0402_50V8J

KSI0

C2492

1

2 @100P_0402_50V8J

KSO9

C2493

1

2 @100P_0402_50V8J

KSO0

C2494

1

2 @100P_0402_50V8J

KSI1

C2495

1

2 @100P_0402_50V8J

KSO16

C2496

1

2 @100P_0402_50V8J

KSO17

C2497

1

2 @100P_0402_50V8J

M1(Left BUTTON)
M2(Center BUTTON)
M3(Right BUTTON)

LEFT
MIDDLE
RIGHT
KSO16
KSO17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

B

(11,12,14,38)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31
32

SMB_DATA_S3

R2479

1

CP_RESET#
TP_CLK
TP_DATA

(41) CP_RESET#
(41) TP_CLK
(41) TP_DATA

C2474
100P_0402_50V8J
@

1

1

2

C2475
100P_0402_50V8J
2 @

1
C2508
0.1U_0402_16V4Z

GND
GND

11
12

(41) TP_RESET

ACES_51522-01001-001
CONN@

2

TP_DATA2
TP_RESET
MIDDLE
RIGHT
LEFT
TP_CLK2

JTP1

1
2
3
4
5
6
7
8
9
10
11
12

A

1
2
3
4
5
6
7
8
9
10
GND
GND

ACES_50524-0100N-001
CONN@

+5VS

GND1
GND2

R2443

1

@

2 4.7K_0402_5%

TP_CLK2

JAE_FL4S030HA3R3000A-DT

R2444

1

@

2 4.7K_0402_5%

TP_DATA2

CONN@

R2445

1

@

2 4.7K_0402_5%

TP_RESET

R2446

1

2 0_0402_5%

TP_DETECT

R2447

1

2 100K_0402_1%

CP_RESET#

Reserve for ESD.

CONN PIN define need double check

2 0_0402_5%
TP_DETECT
TP_DATA2
TP_CLK2
2 0_0402_5%

1

TP_CLK

TP_DATA2

TP_DATA

TP_CLK2

D2408
PJDLC05_SOT23-3
@

2

C2470

C2468 1

RIGHT

R2469

3

KSO2

KSO[0..17]

MIDDLE

SMB_CLK_S3

D2409
PJDLC05_SOT23-3
@
B

1

KSO[0..17]

(41)

(11,12,14,38)
+5VS

JKB1

2

KSI[0..7]

2 @100P_0402_50V8J

1
2
3
4
5
6
7
8
9
10

3

KSI[0..7]

C2467 1

JCP1

1

A

LEFT

1
2
3
4
5
6
7
8
9
10

PN: SCA00000U10 X 2

Fintek thermal sensor
placed near by TOP DDR3
+3VS

PN:SP011108040

1

+3VS

Audio Board

R2448
10K_0402_5%
@

C

C2498
0.1U_0402_16V4Z

1
2

2

U2407
1

VDD

SMCLK

10

EC_SMB_CK2

REMOTE1+

2

DP1

SMDATA

9

EC_SMB_DA2

REMOTE1-

3

DN1

ALERT#

8

REMOTE2+

4

DP2/DN3

THERM#

7

REMOTE2-

5

DN2/DP3

GND

6

R2450 1
@
2
0_0402_5%

EC_SMB_CK2

(14,22,41)

EC_SMB_DA2

(14,22,41)

MAINPWON

JAUD1

FAN CONN.

(41,44,45,47)

(35) HP_OUTL
(35) HP_OUTR
+5VS

(35) EXT_MIC
(35) PLUG_IN

F75303M_MSOP10

(17) USB20_N9
(17) USB20_P9

1

Address 1001_101xb

R2478
0_0603_5%

(17) USB_OC4#
(41) AOU_EN

2

2nd source
SA000029210-->EMC1403-2-AIZL-TR

AOU_CTL1
C2499 @

REMOTE1-

C
Q2407
MMST3904-7-F_SOT323-3

2
B

(41) EC_TACH
(41) EC_FAN_PWM

E

REMOTE1-

1
2

REMOTE2+
1

@
C2505
2200P_0402_25V7K
REMOTE2-

CONN@

CONN@

D

C
Q2408
MMST3904-7-F_SOT323-3

2
B

PN:SP02000U900

E

Compal Secret Data

Security Classification

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
1

1
2
3
4
G5
G6

ACES_50273-00401-001

3

REMOTE2-

C

ACES_88194-2041

JFAN1
1
2
3
4
5
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND1
GND2

1

1
2

C2503
1000P_0402_50V7K
@

TOP CPU_CORE

REMOTE2+

2

C2504
2200P_0402_25V7K

40mil

+VCC_FAN1

3

@
C2500
2200P_0402_25V7K

1

1

1

D

(41) AOU_CTL2
(41) AOU_CTL3

AOU_ILIM

REMOTE1+

2

REMOTE1+

2

2 1U_0402_6.3V6K

1

BOTTOM DDR3

Close U2407
C2502
2200P_0402_25V7K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VALW

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3

4

Compal Electronics, Inc.
KB/TP/Thermal
Sensor/Audio
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
39
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

4

5

Power Button CONN.

Power Button

Finger Print Board

PN:SP01000R400

SHORT PADS

51_ON#

2

(41)

(41) LID_SW#

51_ON# (44)

1
2
3
4

R2469
G1
G2

5
6

ACES_50504-0040N-001

D2412
BAV70W_SOT323-3

@
D2413
AZC199-02SPR7G_SOT23-3

1

CONN@

EC_ON

EC_ON

1

D
(41,47)

Q2409
2N7002K_SOT23-3

2
G

1
2
3
4

(17) USB20_N11
(17) USB20_P11
2

1

ON/OFF

JPWR1

3

3

1
2
3
4

2

ON/OFFBTN#

ON/OFFBTN#

3

J2405
1
2

PN:SP01000R400

+3VS

11/21

2

2

R113
0_0402_5%
@
2

R114
0_0402_5%
@

R2453
100K_0402_5%

A

1

A

JFPB1
1
2
3
4

G1
G2

5
6

ACES_50504-0040N-001

C2512
0.1U_0402_10V6K

CONN@

1

1

1

+3VALW
1

+3VLP

+3VLP

2

1

3

S

2

R2454
100K_0402_5%

B

B

RJ45 Board
PN:SP01001CB00

TPM
+3VS
+3VS
U10

C

1
2
3
7

SDA
SCL
VNC
PP

6
9

DataAvailable
AcceptCmd

4
11
18

GND1
GND2
GND3

5
8
12
13
14

NC
NC
NC
NC
NC

VPS
VPS

24
10

VPS1
VPS1
VPS1
VPS1
VPS1
VPS1
VPS1

28
27
26
23
22
20
17

NC
NC
NC
NC

25
21
19
15

LRESET#

16

C589 1
C645 1
SERIRQ
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD2
LPC_AD3

PM_CLKRUN#
PLT_RST#

CLK_PCI_TPM

(17)

PM_CLKRUN#

(13,38,41)
(13,38,41)
(13,38,41)
(13,38,41)
(13,38,41)

(15)

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

PLT_RST#

(17,38) CLK_PCI_DB
(38,41) EC_TX_P80_DATA
(38,41) EC_RX_P80_CLK
CLK_PCI_DB

Debug Conn.

TPM@

2

10_0402_5%
TPM@

C159 1

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

(14)
(14)
(14)
(5,14,17,22,36,38,41)
(41)
(15)
(14)
(15,41,44)
GND
GND

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
PLT_RST#
LAN_WAKE#
PCIE_WAKE#
PCH_LAN_25M
ACIN
+3VS

13
14

+3VALW
+RTCBATT

ACES_85201-1205N

JRJ45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND

C

ACES_50506-01841-P01

ME@

PLT_RST# (5,14,17,22,36,38,41)

R317 1

(14) PCIE_PTX_C_DRX_N4
(14) PCIE_PTX_C_DRX_P4

JDB3

SERIRQ (13,41)
LPC_AD0 (13,38,41)
LPC_AD1 (13,38,41)
LPC_FRAME# (13,38,41)
LPC_AD2 (13,38,41)
LPC_AD3 (13,38,41)

CLK_PCI_TPM

CLK_PCI_TPM

+3VALW

TPM@
2 10U_0603_6.3V6M
2 0.1U_0402_16V4Z
TPM@

ST33ZP24AR28PVSC TSSOP 28P

D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

(14) PCIE_PRX_DTX_N4
(14) PCIE_PRX_DTX_P4

CONN@

C5109
12P_0402_50V8J
@

2

22P_0402_50V8J
TPM@
D

RF 11/17

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PWR
Button/Power OK/RJ45
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
40
58
of
Date:
Sheet
Title

5

Rev
0.6

2

3

R310 1

@ 2 0_0603_5%

R313 1

2 0_0603_5%
BRDID

KSI[0..7]

(39) KSI[0..7]

(45,46)
(45,46)
(14,22,39)
(14,22,39)

ODD_DA#
EC_INVT_PWM

(38,40)
(38,40)
(15)
(39)
(36)

2

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

+VSB_EN
EC_TACH
EC_PME#
EC_TX_P80_DATA
EC_RX_P80_CLK
PCH_PWROK
EC_FAN_PWM

2 0_0402_5%

EC_RTCX1
SUSCLK_R

2

KSO2

R2228

1

2 2.2K_0402_5%

EC_SMB_CK1

R2230

1

2 2.2K_0402_5%

EC_SMB_DA1

2 10K_0402_5%

EC_FAN_PWM

@

R2451

1

2 10K_0402_5%

EC_TACH

R2236

1

2 2.2K_0402_5%

EC_SMB_CK2

R2237

1

2 2.2K_0402_5%

EC_SMB_DA2

C2220 @

1

2 100P_0402_50V8J

EC_SMB_CK2

C2221 @

1

2 100P_0402_50V8J

EC_SMB_DA2

1

2 10K_0402_5%

67
EC_VDD/AVCC

1

(32,36)

G
3

S

IMVP_IMON

(52)
+3VALW_EC

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

83
84
85
86
87
88

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

97
98
99
109

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

119
120
126
128

SPI Device Interface
SPI Flash ROM

GPIO

M_PWR_ON (42,55)
PCH_SLPA# (15)
BATT_LEN# (45)
BM#
(46,47)

BATT_LEN#
BM#

100
101
102
103
104
105
106
107
108

H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

110
112
114
115
116
117
118

ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
PM_SLP_SUS#_R
EC_PECI

V18R

124

R2203 1

Muxless_STAT

SPK_RT_DET#

2 100K_0402_5%

AOU_CTL1

ENBKL (16)
ADP_ID (44)
FSTCHG (46)
AOU_EN (39)
mSATA_DETEC# (18)
HDD_DETECT# (36)
CP_RESET# (39)
SYSON (42,48)
VR_ON (52)
PM_SLP_S4# (15)

SYSON

EC_RSMRST# (15)
EC_WAKE# (18)
Turbo_V (45)

EC_WAKE#

2 10K_0402_5%
B

Turbo_V

R2217 1

EC_MUTE#

R2202 1

@

2 47K_0402_5%

NTC_V

R2206 1

HDD_DETECT#

R2204 1

ADP_PROTECT

R2207 1

@

2 100K_0402_1%

BM#

R2208 1

@

2 100K_0402_1%

USB_ON#

R2209 1

2 10K_0402_5%

TP_CLK

R2211 1

2 4.7K_0402_5%

TP_DATA

R2212 1

BATT_TEMP

C2211

1

2 100P_0402_50V8J

ACIN

C2212

1

2 100P_0402_50V8J

SA_PGOOD

C2510

1

2 0.1U_0402_10V6K

2 10K_0402_5%
@

2 10K_0402_5%
2 100K_0402_5%

+5VALW

+5VS

Pull Up (40k)
R2243 1
R2215 1

@
@

2 0_0402_5%
2 0_0402_5%

PROCHOT (45)
MAINPWON (39,44,45,47)

BKOFF# (32)
PBTN_OUT# (5,15)
PCH_APWROK (15)
SA_PGOOD (49)

SA_PGOOD

R2216 1

+3VALW

CPU1.5V_S3_GATE (9)
VGA_AC_DET (22,51)
ME_FLASH (13)
NTC_V (45)

NTC_V

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

AOU_ILIM

EC_MUTE# (35)
USB_ON# (37)
AOAC_WLAN (38)
EAPD
(35)
TP_CLK (39)
TP_DATA (39)

TP_CLK
TP_DATA

73
74
89
90
91
92
93
95
121
127

LID_SW#

+3VS

EC_MUTE#
USB_ON#

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

GPIO
Bus

AOU_CTL2 (39)
PCH_PWR_EN# (42)
AOU_CTL3 (39)
SPK_RT_DET#

2 4.7K_0402_5%

C

ACIN
(15,40,44)
EC_ON (40,47)
ON/OFF (40)
LID_SW# (40)
SUSP# (9,24,42,46,48,50,51)

VR_HOT#

(45,52) VR_HOT#

R2214 1

2 0_0402_5%

D
R2244 1
R2245 1

@

2 0_0402_5%
2 43_0402_1%

H_PROCHOT#_EC

PM_SLP_SUS# (15)
H_PECI (5,18)

2

H_PROCHOT#

(5)

Q2202
2N7002K_SOT23-3

G
S

+V18R
1

C2214
4.7U_0805_10V4Z

2
+3VALW

R2220
10K_0402_5%

@
@
1

SUSCLK_R

2 10M_0402_5%

EC_PME#

1
Q2203
2N7002K_SOT23-3
@

Y2202
2

11/14

32.768KHZ_12.5PF_CM31532768DZFT

C2218
18P_0402_50V8J
@

1

1

2

2

C2219
18P_0402_50V8J
@

Compal Secret Data

Security Classification
Issued Date

PCH_PWROK

2

2 0_0402_5%

R2224 1

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

R2222 1

R2229 1
1

68
70
71
72

BRDID

LOGO_LED

EC_RTCX1

+3VS
R2452

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

LOGO_LED#

Q2104
2N7002K_SOT23-3

D

BATT_TEMP (45)
GS_VOUTX (36)
ADP_I
(45,46)
GS_VOUTY (36)

3

4

@
S

KSO1

2 47K_0402_5%

BATT_TEMP

LOGO_LED#

ODD_DETECT#

D

2 47K_0402_5%

1

C2213
20P_0402_50V8
KB9012QF A3 LQFP 128P_14X14

63
64
65
66
75
76

ACOFF

(EC_PME#)
LAN_WAKE#

(40)

2 0_0402_5%
3

PCI_PME# (17)
D

G

1

R2227

R2239

1

XCLKI/GPIO5D
XCLKO/GPIO5E

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

BEEP# (35)
WLAN_WAKE# (38)
ACOFF (44,46)

2

+3VALW

D

122
123

2

R2223
100K_0402_5%

R2225

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

77
78
79
80

EC_SMI#

EC_TX_P80_DATA
EC_RX_P80_CLK
PCH_PWROK
EC_FAN_PWM
GS_SELFTEST

R2221 1

SUSCLK

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

1

(15)

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#
TP_RESET
GS_ON#
RF_OFF#
+VSB_EN
EC_TACH

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

LOGO_LED
BEEP#

2

C

(15)
(15)
(18)
(32)
(39)
(36)
(38)
(45)
(39)

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

AD Input

DA Output

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

SD028470180 S RES 1/16W 4.7K +-5% 0402
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

1

KSO[0..17]

(39) KSO[0..17]

V
V
V
V

max Phase
SVT
SIT2
V
SIT1
V
FVT
V
V
SDV

3

RF
B

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

AGND/AGND

2

CLK_PCI_EC

12
13
37
20
38

VAD_BID
0 V
0.155
0.289
0.538
0.875

SD028820180 S RES 1/16W 8.2K +-5% 0402

69

R2201 1
2
10_0402_5%

EC_RST#
EC_SCI#
ADP_PROTECT

(18) EC_SCI#
(45) ADP_PROTECT

1

C2209 1
2
22P_0402_50V8J

CLK_PCI_EC

(17) CLK_PCI_EC
(5,14,17,22,36,38,40)
PLT_RST#

2 47K_0402_5%

C2210
0.1U_0402_10V6K

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

V
V
V
V

typ

SD028180280 S RES 1/16W 18K +-5% 0402

U2201

ECAGND

R2205 1

1
2
3
4
5
7
8
10

KB_RST#

V AD_BID
0 V
0.148
0.250
0.503
0.819

A

GND/GND
GND/GND
GND/GND
GND/GND
GND0

11/21

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

min

SD028330280 S RES 1/16W 33K +-5% 0402

11
24
35
94
113

(18)
(18)
(13,40)
(13,38,40)
(13,38,40)
(13,38,40)
(13,38,40)
(13,38,40)

VAD_BID
0 V
0.141
0.216
0.436
0.712

1

2

9
22
33
96
111
125

2

1

R2213
4.7K_0402_5%

1000P_0402_50V7K

2

C2207

2

1

1000P_0402_50V7K

2

C2208

2

1

0.1U_0402_16V4Z

2
ECAGND

1

C2206

2 0_0603_5%

1

0.1U_0402_16V4Z

2
L2202 1

1

C2202
1000P_0402_50V7K

C2205

1

0.1U_0402_16V4Z

1

C2204

+EC_AVCC

0.1U_0402_16V4Z

C2201
0.1U_0402_16V4Z
A

1

+3VALW_EC

2 0_0603_5%

C2203

L2201 1

5

3.3V +/- 5%
Vcc
R2210 100K +/- 1%
Board ID
R2213
0K +/- 5%
0
4.7K +/- 5%
1
8.2K +/- 5%
2
18K +/- 5%
3
33K +/- 5%
4

R2210
100K_0402_1%

11/21

+3VALW_EC

+3VALW_EC

4

+3VALW

+3VALW_EC
+EC_AVCC
+3VALW_EC

1

+3VLP +3VALW

2

1

+3VALW

Compal Electronics, Inc.
EC
ENE-KB9012
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
41
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

2

1

R2318
20K_0402_5%

1
2

2

1
Q2302
2N7002K_SOT23-3

G

A

S
3

H

1

SUSP#

R2306
10K_0402_5%
2

1
1

@

2

2

3

1

2

G

3

1

1

JUMP_43X79
@
Q1409
+3V_PCH@
AO3413_SOT23-3

+3V_PCH@

2

Q2303
2N7002K_SOT23-3
@

D
(9,24,41,46,48,50,51)

1U_0402_6.3V6K

G
S

2

D

C2309
0.01U_0603_25V7K

SUSP

2

S

+3V_PCH@

2

D

1

R2303
100K_0402_5%

L

40mil
C2308

R2313
1
2 5VS_GATE
82K_0402_5%

10U_0603_6.3V6M

C2306

2
G
Q2301
2N7002K_SOT23-3

1
1

D
SUSP

J2301

40mil

1

4

R2304
470_0603_5%
@

SUSP

SUSP

+3V_PCH

2

2

+3VALW

2

2

10U_0603_6.3V6M

@

1

10mil
2 150K_0402_5%

1
(9,24,50,51)

1

C2304

20mil
R2301 1

+VSB

1
2
3

@
R2308
100K_0402_5%

Short J2301 for PCH VCCSUS3.3

10U_0805_10V4Z

2

8
7
6
5

C2303

1

10U_0603_6.3V6M

C2302

2

A

10U_0603_6.3V6M

C2301

1

+5VALW

11/14

+3VALW TO +3VALW(PCH AUX Power)

+5VS

U2301
AP4800BGM-HF_SO-8

5

VL

+5VALW TO +5VS
+5VALW

4

3

S
R171

+3V_PCH@
2 0_0402_5%

1

2

1

(41) PCH_PWR_EN#

C2322
0.1U_0603_25V7K
@

+3VALW TO +3VS

4

2

3VS_GATE

1
R2309
470_0603_5%
@
B

FOR SBA Function POWER(always mount)
Q2108
SBA@
AP2301GN-HF_SOT23-3

3
1
2

C2325
0.1U_0603_25V7K
SBA@

H

11/14

2

SUSP

G

S

Q2311
2N7002K_SOT23-3
@

2

SUSP

SYSON#
2
Q2310A
2N7002KDWH_SOT363-6
@

2
3

D

SYSON
5
Q2310B
2N7002KDWH_SOT363-6
@

SYSON (41,48)
R2307
10K_0402_5%
@

Compal Secret Data

Security Classification

2

Q2309
2N7002K_SOT23-3
@

SYSON#

1

G

1

1
2
6

SUSP
S

R2305
100K_0402_5%
@

4

2

Q2308
2N7002K_SOT23-3
@

+5VALW

R2317
470_0603_5%
@

1

G
S

3

SUSP

3

3

2

M_PWR_ON
2
Q2416A
2N7002KDWH_SOT363-6
SBA@

M_PWR_ON#
5
Q2416B
2N7002KDWH_SOT363-6
SBA@

1

1
1 2
D

Q2307
2N7002K_SOT23-3

L

D

3

1
1

1

1 2

R2316
470_0603_5%
@

1 2

R2315
470_0603_5%
@

D
G

(41,55) M_PWR_ON

from EC

+1.8VS

D

S

R2324
1
2 +3VM_GATE
10K_0402_5%
SBA@

S

+1.05VS

R2314
22_0603_5%
D

M_PWR_ON#

4

6
1
R2311
470_0603_5%
@

+1.5V
+0.75VS

2 47K_0402_5%

3

Q2306
2N7002K_SOT23-3

2 47K_0402_5%

1

2

1
2

2

G

0.1U_0603_25V7K

C2321

2

@

C

1
21.5VS_GATE
0_0402_5%

D
SUSP#

SUSP#

2

SBA@

10mil

R2322

1

(9,24,41,46,48,50,51)

1

1U_0402_6.3V6K

20mil

2

C2320

+3VALW

2 100K_0402_5%

1

1

10U_0603_6.3V6M

C

R2312

1
C2319

0.1U_0402_16V4Z
C2317

2

10U_0603_6.3V6M

C2315

1

R2319 1

2

3

R2320 1

+1.5VS

U2303
AP2301GN-HF_SOT23-3

R351
SBA@
390_0402_5%

SBA@

2

2

1

+1.5V to +1.5VS
+1.5V

1

10U_0603_6.3V6M

SBA@

2

VL

C2329

10U_0603_6.3V6M

1

+3VALW

+3VM

1

1

3

2

C2314
0.01U_0603_25V7K

C2327

2
Q2304A
2N7002KDWH_SOT363-6

+3VALW

SUSP
5
Q2304B
2N7002KDWH_SOT363-6

2

SUSP

4

1

6

R2321
1
2
0_0402_5%

1

3

2 470K_0402_5%

1

2

10U_0603_6.3V6M

10mil
R2310

+VSB

1

@

C2313

B

20mil

11/21
10U_0603_6.3V6M

2

+3VS
1
2
3

C2312

1

10U_0603_6.3V6M

C2311

2

10U_0603_6.3V6M

C2310

1

U2302
AP4800BGM-HF_SO-8
8
7
6
5

2

+3VALW

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
DC
Interface
Size Document Number
Custom
LA-8131P
Tuesday, January 10, 2012
42
58
of
Date:
Sheet
Title

5

Rev
0.6

1

2

3

G3

4

S5

5

S0

RTC
RTCRST
EC_111 pin
EC_ON
FD1

FD2

FD3

FD4

MAINPWON
FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

1

@

1

@

1

1

A

FIDUCIAL_C40M80

A

@

+5VALW

FIDUCIAL_C40M80

+3VALW/VCCDSW
ON/OFF#
H18
H_4P0N

1

1

@

H22
H_3P3

@

H20
H_2P1N

@

CPU Screw

SYSON

PCH_SLPA#
@

M_PWR_ON

H24
H_3P5X4P5N

B

+3VM

@

1

@

1

H5
H_4P0

@

1

+1.05VM
H3
H_4P0

1

1

H7
H_2P3

H9
H_2P3

@

SYSON
H8
H_2P3

1
@

SLP_S5#
SLP_S4#

@

@

H10
H_2P3

B

@

1

1
H2
H_4P0

1

H4
H_4P0

@

H23
H_5P2X5P7N

1

H19
H_5P2X5P7N

1

PBTN_OUT#

@

GPU Screw
H11
H_4P0N

EC_RSMRST#

H12
H_2P3

1

@

1

1

H21
H_4P0N

@

PCH_APWROK

@

SLP_S3#
SUSP#

H15
H_2P3

1

+1.5V_CPU_VDDQ
@

+1.8VS
+5VS

H17
H13
H_3P5X4P5N H_2P3

+3VS

H6
H_2P3
@

1

1

1

+1.5VS
@

@

+0.75VS
+V1.05VS(VCCP)

C

C

+VCCSA
SA_PGOOD
99ms

VR_ON
PCH_POK
PCH_CLKOUT
DRAMPWROK
H_CPUPWRGD
CPU_VID
CPU_CORE
VGATE
SYS_PWROK
D

D

ME and BIOS
activity will continue

BUF_PLT_RST#
SPI
DMI

Tralning
Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
Screw
Hole
Size Document Number
Custom
LA-8131P
Friday, January 06, 2012
43
58
of
Date:
Sheet
Title

5

Rev
0.6

1

3

1

(46)

B+

1

2

2
A

2011_0805
del PD107,PR134,JRTC1
䦣⇘HW⮷㜧
2011_0728 del PR130 and +3VLP
add PR? 1K_0603_5%
change place for R132,R133, +CHGRTC,PD107

3

VOUT

VIN

2

PC117
1U_0805_25V6K

2

1

1

PC113
0.01U_0402_25V7K

2
1
PR118
499K_0402_1%
PR121
511K_0402_1%
2
1

1

1

PACIN (46)

2

+5VALW

3

3

S

2011_1005 PQ106 form
SB301150000
(S TR DTC115EUA NPN (UMT3))
change to SB00000RM00
(S TR LTC015EUBFS8TL NPN UMT3F)

2011_0808 PU102 change
form SA00001PE00(APL5156-33DI-TRL)
to SA00002E280(BIT3021A-ST9)

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2
G

B

BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V

Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V

CHGRTCIN

GND
PC116
10U_0603_6.3V6M

ACIN

PRG++ 2

1
PR120
205K_0402_1%

0.01U_0402_25V7K

PC110
2
1

1

8

1
PR131
200_0603_5%

PR127
47K_0402_5%
2
1

D

PQ106
LTC015EUBFS8TL_UMT3F

1
2

PQ105
2N7002KW_SOT323-3

1
2

PC115
0.1U_0603_25V7K

51ON-3

PU102
BIT3021A-ST9_SOT89-3

RTC Battery
5

6

2011_1005 PQ105 change
form SB000006800(2N7002W T/R7 1N SOT-323)
to SB000009Q80( 2N7002KW 1N SOT323-3)

1

RB751V-40_SOD323-2

5

-

RTCVREF

1

+RTCBATT

3.3V

+

O

PR126
10K_0402_5%
2
1

VS

2

PD106

PR124
68_1206_5%

1

RTCVREF
PR133
560_0603_5%
1
2

PR122
200K_0402_1%
2
1

7

2

1
1
2
3

(46) PRECHG

PU101B
LM393DG_SO8

2

PC114
0.22U_0603_25V7K

2

PR129
22K_0402_1%
1
2

2

PR128
100K_0402_1%

1

1

51ON-2

+CHGRTC
PR132
560_0603_5%
1
2

ACON

51ON-1

PR125
200_0603_5%
CHGRTCP 1
2

(40) 51_ON#

(46)

PD103
RB715FGT106_UMD3
2
1
3

P

2

(39,41,45,47) MAINPWON

PR123
68_1206_5%
PQ101
TP0610K-T1-GE3_SOT23-3

VS

PC112
1000P_0402_50V7K

VL

PD104
LL4148_LL34-2
PD105
LL4148_LL34-2
2
1

PR115
4.99M_0402_1%
2
1

2011_1005 PD103 change
form SCSB715F000(S SCH DIO RB715F UMD3)
to SCSB715F010( S SCH DIO RB715FGT106 UMD3)

VIN

B

1 2
3

3
PACIN

Vin Detector
Min.
typ.
Max.
L-->H 17.430V 17.901V 18.384V
H-->L 16.976V 17.262V 17.728V

3.3V

BATT+

PQ104
DDTC115EUA-7-F_SOT323-3
2

C

G

RTCVREF

(15,40,41)

4

PD101
LLZ4V3B_LL34-2

ACIN

PR119
100K_0402_1%
2
1

PR117
10K_0402_5%
2
1

2

ACOFF

PC111
0.1U_0603_25V7K
2
1

1
PR111
10K_0805_5%

PACIN

1
1
PR116
10K_0402_5%

O

PU101A
LM393DG_SO8

2

P

-

G

8
+

2

1

1
2

3

4

VINDE-3

PR112
10K_0402_1%
1
2

2

2

1

VINDE-1

PC109
0.1U_0402_16V7K

2

PR113
22K_0402_1%
1
2
PR114
20K_0402_1%

PC108
0.068U_0603_16V7K
2
1

2

PR110
84.5K_0402_1%

C

2

1

1

VIN

(41,46)

VIN

VS
PC107
0.01U_0402_25V7K

VINDE-2

DDTC115EUA-7-F_SOT323-3

PQ103

1

1

2

PR105
1K_1206_5%
1
2

2011_0818 change JDCIN1

PR109
1M_0402_1%
1
2

D

LL4148_LL34-2

2

1

1
2

PL101
SMB3025500YA_2P

2

PR104
1K_1206_5%
1
2

PQ102
TP0610K-T1-GE3_SOT23-3
PD102

PR108
100K_0402_1%

VS

2

2

1
2

@

2011_0727
del PreCHG
PR102
1K_1206_5%
1
2

PC106
1000P_0402_50V7K

1

PF101
7A_24VDC_429007.WRML

ACES_50312-00541-001

Precharge detector
15.97V/14.84V FOR
ADAPTOR

VIN

APDIN1

2

1

PR107
100K_0402_1%
2
1

A/D

PC105
100P_0402_50V8J

1

2

PR106
100K_0402_1%
2
1

1

1
APDIN

1

1
2
3
4
5

2

1
2
3
4
5

ADP_ID

PC104
100P_0402_50V8J

JDCIN1

3

ADP_ID
AC Adapter 90W 65W
(41)
R(K ohm) open 10
ADP_ID(V) 3.3 1.65
Detection voltage >2.64 1.32~1.98

PR103
270_0402_1%
1
2

PC103
1000P_0402_50V7K

D

2

2011_0929 PR103
for 0ohm change to 270ohm

2

PR101
10K_0402_1%
1
2

+3VALW

PC102
680P_0603_50VK

4

PC101
0.1U_0402_16V7K

5

3

2

Title

A

Compal Electronics, Inc.
PWR DCIN / Vin Detector /Pre-charge

Size Document Number
Custom
Date:

LA-8133P
Friday, January 06, 2012
Sheet
1

Rev
0.6

44

of

58

5

4

VMB2
1
2
3
4
5
6
7
8
9

PL201
SMB3025500YA_2P
1
2

2

1

BATT+

@

2

1
PC201
1000P_0402_50V7K

2

1

EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%

D

1
2
3
4
5
6
7
GND
GND

VMB

PF201
12A_65V_451012MRL
1
2

2
1
PR202
100_0402_1%

JBATT1

3

D

PC202
0.01U_0402_25V7K

2011_1128
Add OTP
PR212 and PR206 unmount

SUYIN_200082GR007M211ZR

2011_0823
change 9P JBATT1

EC_SMB_DA1 (41,46)

1

MAINPWON (39,41,44,47)

2

2
1
PR207
21.5K_0402_1%

2
1
PR206
12.7K_0402_1%

1

1

1

2

2

PQ202
TP0610K-T1-GE3_SOT23-3

3

S

(47)

SPOK

(41)

+VSB_EN

(41) BATT_LEN#

PR234
1K_0402_5%
2

2
A

1

1
2

PQ203
2N7002KW_SOT323-3

+VSBP

S

3

+VSB

A

Compal Secret Data

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PJ201
@ JUMP_43X39
1 1
2 2

2011_1005 PQ105 change
form SB000006800(2N7002W T/R7 1N SOT-323)
to SB000009Q80( 2N7002KW 1N SOT323-3)

Security Classification
Issued Date

PC205
0.1U_0603_25V7K

D

2
G
1

1

PC204
0.22U_0603_25V7K

2
1
PR214
100K_0402_1%

@
PR217
1K_0402_5%
1
2

+VSBP

1

@

PR215
22K_0402_1%
1
2

1

3

@

@

PC206
1U_0402_6.3V6K

RTCVREF

PR216
100K_0402_1%

S

1

PR226
100K_0402_1%

2

1

PQ205
D 2N7002KW_SOT323-3

3

B+

VL
@
2
G

2

2VREF_8205

PR225
10K_0402_1%
@

5

2011_1005
PH201 form SL200000V00
100K +-1% NCP15WF104F03RC 0402
change to SL200000U00
100K +-1% TSM0B104F4251RZ 0402

B

2

2
G

+3VLP
1

@ PR231
47K_0402_1%

1

PR232
47K_0402_1%

2

1

PU202A
LM393DG_SO8

PR223
10K_0402_1%
2@
1

2

BATT_OUT (46)
1

O

1

2011_0808
PR227,PQ206
change place

PQ204
D 2N7002KW_SOT323-3

3

-

0_0402_5%

+3VLP

PH201
100K_0402_1%_TSM0B104F4251RZ

2

2

2

(41)

PR229

+3VALW

0_0402_5%

NTC_V

1

@PR228
@
PR228
0_0402_5%

27.4K_0402_1%

1
PR208
10K_0402_1%

PR220
100K_0402_1%
@

1

1

2

5

C

2
@ PR230

1

1

PR222
100K_0402_1%
@

@

@

OT2 RHYST2

Turbo_V_1
PR210
ADP_OCP_2 1
2

2

2
+

4

2

6

+3VALW

8
3

P

PR221
221K_0402_1%@

@
PR218
10M_0402_5%
1

G

1
2

PR219
10K_0402_1%
1
2

OT1 TMSNS2

2011_1119
Change PQ201,PR209,PR212 to mount from unmount
+3VLP

PC207
0.01U_0402_25V7K

2
2

1

B

PR224 @
768K_0402_1%

3

PR213 0_0402_5%

P2

@

OTP_N_002

1

2011_0731 add circuit for battery learning function
2011_1119 change circuit to unmount from mount

VMB2

7

OTP_N_003

@ PR212
0_0402_5%
2

PROCHOT

8

GND RHYST1

G718TM1U_SOT23-8

3
(41)

NTC_V_1

VCC TMSNS1

2

4

2 ADP_OCP_1
G
S 2N7002KW_SOT323-3

2
ADP_PROTECT (41) @
G
S TR 2N7002KW 1N SOT323-3

(41)

PQ201

1
D

PU201

S

2

2
PR209
1

(41,52) VR_HOT#

100K_0402_1%

1

C

+3VLP

D

PQ206

PR211
10K_0402_1%
1
2

+3VS
2

PC203
0.1U_0603_16V7K

2011_0801 add PR227, PQ206,
place port name"ADP_PROTECT"

3

90W : 6.67K
65W : 1.65K

1

A/D
1

BATT_TEMP (41)

1
2
PR227
2.1K_0402_1%

Turbo_V

1
2
PR204
10K_0402_5%


ADP_I

1

(41,46)

2

VL

+3VALW

PR205
4.42K_0402_1%

1
2
PR203
6.49K_0402_1%


For KB930 --> Keep PU201 circuit
(Vth = 1.25V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205, PR211,PQ201,PR208,PR212

PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

EC_SMB_CK1 (41,46)

2

Title

Compal Electronics, Inc.
PWR-BATTERY CONN/OTP

Size Document Number
Custom
Date:

LA-8133P
Tuesday, January 10, 2012
Sheet
1

45

Rev
0.6
of

58

CHGVADJ

4V

0V

4.2V

1.882V

4.35V

3.2935V

IREF=0.254V~3.048V
VCHLIM need over 95mV

19

HIDRV

18

DH_CHG

REGN

BM#

2011_1210
PR330,PR333 @

(41,47)
@
PR330
10K_0402_5%

for lid wake up from S4

2

1

4
2

2

1

PC315
0.047U_0603_25V7M

4

2011_1129

RB751V-40_SOD323-2 Change 2.2
1
2

3

LTA044EUBFS8TL_UMT3F

2

1SS355_SOD323-2

1

1

1

2ACOFF-1

PD302
1

PC318
1U_0603_25V6

2

2011_0829
change part

DL_CHG

PC320
0.1U_0603_25V7K
2
1

PC321
0.1U_0603_25V7K

+3VS

3
1

PACIN

2011_1005 PQ309
form SB301150000
change to
SB00000RM00

3

PC311
0.1U_0603_25V7K
2
1

2
G
S

2

CHG

2011_1207
PR303 change to 499k from 100k
PR304 change to 10k from 49.9k
PR320
0.01_1206_1%
1

4

2

3

SRP

SRN

BA+

2011_0830
change PL302
for height
2011_1127
Change from SH00000LI00 4.7u to SH000009R00
10UH +-20% MMD-10DZ-100M-X1 6A
B

@
PC322
0.1U_0603_25V7K

2011_0831 PQ314
change form AO4466L
to TPC8A03-H

PQ315 TP0610K-T1-GE3_SOT23-3
BQ24727VCC

1

2

PR329

2011_1005 PD103 change
form SCSB715F000(S SCH DIO RB715F UMD3)
to SCSB715F010( S SCH DIO RB715FGT106 UMD3)

1

PQ316
LTC015EUBFS8TL_UMT3F

2

3

2011_1005 PQ316
form SB301150000
change to
SB00000RM00

1

2

FSTCHG

3

SUSP#

FSTCHG (41)
SUSP# (9,24,41,42,48,50,51)
A

PD304
RB715FGT106_UMD3

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Compal Electronics, Inc.

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PR304
49.9K_0402_1%
1

4
3

3
2
1

1

1

PD301

15

14

1
13

PR327
10_0603_5%

2

PR324
2.2_0603_5%
1
2

D

PL302
10UH +-20% MMD-10DZ-100M-X1 6A

1U_0603_25V6

BST_CHG

2

1

6.8_0603_5%
1 12
PR326

11

2011_1122
Add PR333

PR333
0_0402_5%

2

(44)

C

2

17
16

1

PRECHG
PQ309
LTC015EUBFS8TL_UMT3F

PQ311
2N7002KW _SOT323-3

24727_SN

BTST

2

@

2011_0728 add charger
turbo boost function

4

PC314

2

PC317
10U_0805_25V6K
2
1

PR317
10_1206_5%
1
2

PHASE

LX_CHG

2011_0829
change part

PQ314
TPC8A03-H_SO8

BM

PR325
100K_0402_1%

SRP

PR323
1
2
316K_0402_1%

BQ24727VCC-1

D

PQ306

2

2011_1005 PQ308
form SB301150000
change to
SB00000RM00

5
6
7
8

ILIM

+3VALW

1

PQ308
LTC015EUBFS8TL_UMT3F

5
6
7
8
1
ACN

10

2011_0818
add PC323
with unmount

20

LODRV

SA000051W00

GND

SCL

VCC

2
PR303
499K_0402_1%

2

2011_1005 PQ311 change
form SB000006800
(2N7002W T/R7 1N SOT-323)
to SB000009Q80
( 2N7002KW 1N SOT323-3)

PR322
4.7_1206_5%

0.1U_0603_25V7K

2
ACP

3

CMPIN

CMPOUT

9

SRN

(41,45) EC_SMB_CK1

100K_0402_1%

A

5

2
1
432K_0603_1%

PU301
BQ24737RGRR_VQFN20_3P5X3P5

3
PR328
100K_0402_1%
2
1

IREF=1.016*Icharge

SDA

2011_1005 PQ313
form SB301150000
change to
SB00000RM00

P2

CC=0.25A~3A

(41,45) EC_SMB_DA1

100P_0603_50V8
8

21

1

PR308
200K_0402_1%

BQ24727VCC

TP

1

Vcell

IOUT

1

2

CHGVADJ=(Vcell-4)/0.10627

7

2

2011_0801 add PR332, PQ318
for battery learning
B
2011_1119 change PR332,PQ318 to unmount from mount

ACDET

1

3

S

PC313
1
2

@

2

0.1U_0603_25V7K

6

2

BATT+

2011_1005 PQ305, PQ306
form SB00000RL00
change to SB00000RL00

PD303
1SS355_SOD323-2

2011_1005 PQ312
change form TPC8037-H
to TPC8065-H_1N_SOP-8

0.1U_0603_25V7K

1
2
3

1

2
G

(45) BATT_OUT

ADP_I

2

D

1
PC323

@

1

2
PQ318

1

@

2N7002KW_SOT323-3

3

@ PR332
0_0402_5%

(41,45)

PR319
64.9K_0603_1%
1
2

2

1

2

PR321
1
2ACOFF-12
10K_0402_5%
1

ACOFF

1

PQ313
LTC015EUBFS8TL_UMT3F

PR314

PQ310B

5

2

ACON

3

P2-2
(44)

PR318
47K_0402_1%
1
2

PACIN

4

PACIN

2N7002KDW-2N_SOT363-6
2011_0731 PR319 form
SD00000Z480_66.5K_0603_0.1%
change to SD014649280_64.9K_0603_1%

(44)

2011_0915 del
PR310,PR311
PR312,PR313
H_PROCHOT#,+3VALW
4

VIN

@
C

@

PC310
2

PC312

ACOK

S

2

0.1U_0603_25V7K

1

1 2

PQ317
2N7002KW _SOT323-3
2
BATT_OUT (45)
G

D

@

PC309
1

2011_0728 numount
PR315,PR316, HW䪗㚱PU

PR315
10K_0402_5%
1
2
PR316
10K_0402_5%
1
2

1

2

PQ310A
2N7002KDW -2N_SOT363-6

3

1

PR331
20K_0402_1%
PR309
150K_0402_1%

6

3

2011_1005 PQ307
form SB301150000
change to
SB00000RM00

1

2011_1005 PQ301,PQ302,PQ303
form SB00000DL00_AO4407A_SO8
change to SB00000DL10(S TR AO4407AL 1P SO8 )

2011_0805 change net name
form ACOFF to ACOFF-1

PR307
10K_0402_1%
1DISCHG_G-1
1
2

ACN
ACP

+3VALW

1

PQ307

8
7
6
5

VIN

2011_0801 add PR331, PQ317
for battery learning

LTC015EUBFS8TL_UMT3F

8
7
6
5

PQ303
AO4407AL_SO8

PR305
47K_0402_1%
1
2

3
2
1

3

1

P2-1

2

1
2
3

PC308
2200P_0402_50V7K

2

PC307
4.7U_0805_25V6-K
1
2

2
1

4

2011_0731 PC302 form
SE074222K80_2200P 50V K X7R 0402
change to SE075562K80_5600P_0402_25V7K

1

PQ302
AO4407AL_SO8

B+

1

PC304
@ 10U_0805_25V6K

2
1

PC303
@ 10U_0805_25V6K

4
1

2

PC302
5600P_0402_25V7K

1

2

2

2

1

PC306
4.7U_0805_25V6-K
1
2

SH00000AA00
PL301
1UH_PCMB061H-1R0MS_7A_20%

1

PC301
0.1U_0603_25V7K
2
1
PR306
200K_0402_1%

2

3

2

1
PR301
47K_0402_5%

LTA044EUBFS8TL_UMT3F

PR302
0.01_1206_1%

1

8
7
6
5

PC305
4.7U_0805_25V6-K
1
2

1
2
3

4

1
2
3

PQ305

2

(41,44)

Need EC write ChargeOption() bit[8]=1

PQ304
AO4423L 1P SO8

8
7
6
5

2011_0731 PR301 form
SD028200380_200K +-5% 0402
change to SD028470280_47K_0402_5%

D

2

PC319
680P_0603_50V7K

PQ301
AO4407AL_SO8

VIN

3

B+

PC316
10U_0805_25V6K
2
1

4

PQ304 form SB00000DL00_AO4407A_SO8
SB00000I600_SI4459ADY-T1-GE3_SO8
P3
PQ304 from SB00000I600_SI4459ADY-T1-GE3_SO8
P2
SB00000N100 AO4423L
1P SO8

PQ312
TPC8065-H_1N_SOP-8

5

2011_0731
change to
2011_1127
change to

4

3

2

Title
Size
Date:

CHARGER

Document Number

LA-8133P
Friday, January 06, 2012
Sheet
1

Rev
0.6
46

of

58

5

4

3

2

1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205
2

+3VALW P

PJ402

2

1

1

+3VALW

D

1

2

+5VALW P

@

19

LG_5V

1
2
1
2
PC420
0.1U_0603_25V7K

4

2VREF_8205

5
6
7
8
PQ402

3
2
1

1
2

PR410
4.7_1206_5%

5
6
7
8
1
2
3
2
1

NC

PQ404
TPC8A03-H_SO8

PC418
1U_0603_10V6K
2
1

2

3

RT8205_B+

+5VALWP

1
+

4

18

VIN

VREG5
17

16

GND

SKIPSEL

2011_1129
Change 2.2

RT8205EGQW _W QFN24_4X4

VL

PQ405B
2N7002KDW -2N_SOT363-6

2011_0829 change part

PL402
4.7UH_20%_VMPI1004AR-4R7M-Z01_10A
1
2

1

15

EN

(45)

TPC8065-H_1N_SOP-8

LGATE1

14

PC425
68P_0402_50V8J
2
1

PC410
0.1U_0603_25V7K
2
1

PC409
2200P_0402_50V7K
2
1

PC408
4.7U_0805_25V6-K
2
1

PC407
4.7U_0805_25V6-K
2
1

ENTRIP1

1

2

3

12
2011_1005 for S5 LGATE2
add PR417

PR412
100K_0402_1%

1
2
3

ENTRIP1

FB1

REF

4

LX_5V

SPOK

C

Typ: 175mA

PC415
150U_B2_6.3VM_R45M

2

B

2011_0826
mount for EMI

+3.3VALWP OCP(min)=5.81A
+5VALWP OCP(min)=8.44A

PR413
100K_0402_1%
2
1

1

2011_1005 PQ406
form SB301150000
change to
SB00000RM00

D

2
G

PQ406
LTC015EUBFS8TL_UMT3F

3

S

A

3

1

2
PC421
4.7U_0603_10V6K

1

@

2
1
PR416
40.2K_0402_1%

PQ407
2N7002KW _SOT323-3

2

2

PR415
100K_0402_1%

2

1

PC426
0.1U_0603_25V7K

5

20

VFB=2.0V

+5VALW

VS

1

PR419
0_0402_5%
2
1

UG_5V

PHASE1

@

ENTRIP2

5

1

2

PR414
0_0402_5%
2
1

PR420
100K_0402_1%
2
1

A

21

PHASE2

11

PR417
499K_0402_1%
1
2

B+

6
PQ405A
2N7002KDW -2N_SOT363-6

VL

2011_1122
Add PR419,PR420,PC426,PQ407

UGATE1

PR411
499K_0402_1%
1
2

ENTRIP1

PR418
1
2
20.5K_0402_1%

BOOT1

PR409 PC413
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

UGATE2

1

2011_1005 PQ402
change form TPC8037-H
to TPC8065-H_1N_SOP-8

4

22

13

4

2011_0826
mount for EMI

EC_ON

(39,41,44,45) MAINPWON

VS

2011_0829
PR407 adj
5V OCP
23

LG_3V

PQ403
AO4712L_SO8

PR407
71.5K_0402_1%
2

PGOOD

BOOT2

1

2011_0826 add
for EMI

24

VREG3

2

JUMP_43X118

RT8205_B+

VO1

VO2

PC419
4.7U_0805_10V6K

1
2
3

B

2011_1215
Change PR418 to 20.5k SD034205280
from 2.2k SD028220180

8
7
6
5

PR401
4.7_1206_5%
2
1

2

2011_1005 PQ403
form SB00000AJ00(S TR AO4712 1N SO8)
change to SB00000AJ10(S TR AO4712L 1N SO8)

P PAD

1

FB2

1

7
0.1U_0603_25V7K
8
PC412
PR408
1
2 1
2 BST_3V 9
2.2_0603_5%
UG_3V 10
LX_3V

PC414
150U_B2_6.3VM_R45M

PC416
680P_0603_50V7K
2
1

+

BM#

25

PL401
4.7UH +-20% PCMB063T-4R7MS 5.5A
1
2

1

6)

PU401

2011_1129
Change 2.2

2011_1127
Change PL401 from SH000006J80 to SH00000PG00
4.7UH +-20% PCMB063T-4R7MS 5.5A

2011_0826 add
for EMI

+3VLP

4

PR406
137K_0402_1%
1
2

2

PQ401
AO4466L_SO8

+3VALWP

(40,41)

PC411
4.7U_0805_10V6K

8
7
6
5

PC403
0.1U_0603_25V7K
2
1

2011_0826 add
for EMI

TONSEL

+3VLP

PC424
68P_0402_50V8J
2
1

PC422
2200P_0402_50V7K
2
1

PC401
0.1U_0603_25V7K
2
1

C

PR405
20K_0402_1%
1
2

ENTRIP2

1

1

PC406
2200P_0402_50V7K
2
1
PC423
68P_0402_50V8J
2
1

2

@ JUMP_43X118

PC405
4.7U_0805_25V6-K
2
1

2

PC404
4.7U_0805_25V6-K
2
1

B+

Typ: 175mA

PR404
20K_0402_1%
1
2

6

PJ401

PR403
30K_0402_1%
1
2

5

RT8205_B+

PR402
13K_0402_1%
1
2

ENTRIP2

2011_0829
PR406 adj
3.3V OCP

PJ403

PC417
680P_0603_50V7K

D

2

PC402
1U_0603_10V6K

@ JUMP_43X118

Compal Secret Data

Security Classification
Issued Date

@

2011_1116
PR415,PR416=>@
Add PR418

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
3VALWP/5VALWP

Size
Document Number
Custom
Date:

LA-8133P
Sheet

Friday, January 06, 2012

1

Rev
0.6
47

of

58

A

B

C

D

3
2
1
BST_1.5V

2

TRIP

DRVH

9

DH_1.5V

3

EN

SW

8

LX_1.5V

4

VFB

V5IN

7

5

RF

DRVL

470K_0402_1%

TP

PR502
PC506
2.2_0603_5%
0.22U_0603_16V7K
1
2BST_1.5V-1 1
2

1

+5VALW

PQ502

11

PC507
1U_0603_10V6K

4
1

TPS51212DSCR_SON10_3X3

3
2
1

2011_1129
PR507 change from 11.5K to 11.8K SD034118280

2

VFB=0.7V
TPC8A03-H_SO8

PR507
1

PC519
68P_0402_50V8J
2
1

PC505
2
1

2200P_0402_50V7K

B+

1

2011_0826 add
for EMI

1

+1.5VP

1

220U_6.3V_M_F45_R18M_PXK

+

PC508

+1.5VP OCP(min)=15.6A
2
2
@
+1.5VP

2

2011_0829
mount for EMI

@

PJ502
2

1

1

JUMP_43X118
PJ503
2

1

+1.5V

1

JUMP_43X118

2
11.8K_0402_1%

1

1

2011_0829
change part

DL_1.5V

6

2

JUMP_43X118

PL501
1UH_+-20%_MMD-10DZ-1R0M-X1A_18A
1
2

PR504
4.7_1206_5%

1

10

2

PR5062

VBST

PC509
1000P_0603_50V7K

1
2

1

PC501 @
.1U_0402_16V7K

2
1

PR505
@
47K_0402_5%

(41,42) SYSON

2

PGOOD

2
@

PJ501

TPC8065-H_1N_SOP-8

5
6
7
8

PR501
0_0402_5%
1
2

PU501

1

1

PR503

2

100K_0402_1%

PC504
2
1

PQ501

2011_1129
Change 2.2
1

0.1U_0402_25V6

4

PC503
10U_0805_25V6K
2
1

5
6
7
8

2011_1005 PQ501
change form TPC8037-H
to TPC8065-H_1N_SOP-8

PC502
10U_0805_25V6K
2
1

1.5V_B+

2011_1007 PL501
form SH000004S00(S COIL 1.0UH +-20% PCMC104T1R0MN 20A) change to SH00000CN00(S COIL 1UH +20% MMD-10DZ-1R0M-X1A 18A)

2

PR508
10K_0402_1%
2

2

3

3

2011_0801 JP504 form
43x118 change to 43x79

1



2

PR512
1M_0402_5%

SY8033BDBC_DFN10_3X3

2011_0826
mount for EMI

PC517
2
1

0.1U_0402_25V6

PC518
68P_0402_50V8J
2
1

PC516
2
1

1 2

2200P_0402_50V7K

2

0_0402_5%

FB=0.6Volt

+1.8VSP

PJ505

2

2

1

+1.8VS

1

@ JUMP_43X79

1.8VSP max current=4A

1.8VSP_FB
1

EN_1.8VSP

6

2

TP

2

FB

1

EN

2011_0801 JP505 form
43x118 change to 43x79
2011_0826 add
for EMI

2

5

PR510
20K_0402_1%

PC514
22U_0805_6.3VAM

SVIN

1

8

+1.8VSP

2

3

PC513
22U_0805_6.3VAM

LX

PC511
68P_0402_50V8J
2
1

PVIN

1

9

11

PR511

1

1

PC515 @
0.1U_0402_10V7K

(9,24,41,42,46,50,51) SUSP#

PL502
1UH_PH041H-1R0MS_3.8A_20%
1
2

1.8VSP_LX

2

2

1

LX

PC512
PR509
680P_0603_50V7K 4.7_1206_5%

PVIN

NC

PC510
22U_0805_6.3VAM

2

1

@ JUMP_43X79

10

1

1.8VSP_VIN

1

PG

1

NC

2

4

PU502

PJ504

7

2

+5VALW

PR513
10K_0402_1%

4

4

2

2011_0829
change and mount

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
PWR-+1.5VP/+1.8VSP

Size Document Number
Custom
Date:

LA-8133P
Sheet

Friday, January 06, 2012

D

Rev
0.6
48

of

58

4

3

+3VS
PR603
100K_0402_5%
1

VCCSA Vout
0.9V
0.8V
0.725V
0.675V

24

PJ602
2

1

+VCCSA

1

JUMP_43X118

(9)

+VCCSA_VID0

PR605
0_0402_5%
1
2

1.05VS_VCCP_PWRGOOD

D

(50)

11

+VCCSA_PHASE

TP

7

PC616
1000P_0603_50V7K

25

@

2

PR608

2011_0826
mount for EMI

2011_0929
del PC606
(22U_0805_6.3V6M)

2
PC618
3300P_0402_50V7K

1

2
PR610
10K_0402_5%

1

PC620
68P_0402_50V8J
2
1

PC612
22U_0805_6.3V6M
1
2

PC611
22U_0805_6.3V6M
1
2

2011_1012
PC607 PC610 mount for RF

C

PR609
100_0402_5%
2
1

PC619
0.01U_0402_25V7K
1
2

0.22U_0402_10V6K

@

1

33K_0402_5%

PC617
2
1

PC610
2200P_0402_50V7K
2
1

2
8

PC609
22U_0805_6.3V6M
1
2

PR607
4.7_1206_5%

9

+VCCSAP
PC608
22U_0805_6.3V6M
1
2

10

PC607
0.1U_0402_10V7K
2
1

1

PC605
22U_0805_6.3V6M
1
2

PL601
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

1
MODE
6

1

VOUT

VIN

JUMP_43X118

2011_0826 add
for EMI

13

12

PR606
PC604
0_0603_5%
0.22U_0603_16V7K
+VCCSA_BT 1
2 +VCCSA_BT_1 1
2

EN

15

14
VID0

VID1

16

SW
SLEW

10U_0805_6.3V6M
PC615

10U_0805_6.3V6M
PC614

SW

VIN

5

+VCCSA_PWR_SRC

SW

VIN

23

4

+VCCSA_PWR_SRC

TPS51461RGER_QFN24_4X4

VREF

1

SW

PGND

22

3

1

21

1

BST

PGND

GND

@

2

@

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

+VCCSA_EN

SW

2

C

2

0.1U_0603_25V7K
PC613
1
2

2200P_0402_50V7K
PC601

+3VALW

PJ601

1

V5FILT

PGND

20

2

17

18
V5DRV

19

2

H_VCCSA_VID0

2

+VCCSAP

2011_0818 change VCCSA of enable name
PU601

2

1

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

(9)

PR604
1K_0402_5%
2
1

+VCCSA_VID1

PR601
10_0402_1%
2
1

PC603
2.2U_0603_10V7K
1
2

1

2

PC602
1U_0603_10V6K

+5VALW

PGOOD

output voltage adjustable network
D

1

H_VCCSA_VID1

2
(41) SA_PGOOD

COMP

VID[1]
0
1
0
1

+VCCSA_PWRGD

VID [0]
0
0
1
1

2

PR602
1K_0402_5%
2
1

2

5

PR611
0_0402_5%
2
1

+VCCSA_SENSE (9)

2011_0801 del +V1.05S_VCCPP circuit
B

B

A

A

Compal Secret Data

Security Classification

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title
Size
C
Date:

Compal Electronics, Inc.
PWR +VCCSAP/1.0

Document Number

LA-8133P
Sheet

Friday, January 06, 2012

1

Rev
0.6
49

of

58

5

4

3

2

1

2011_0801 JP701 size form
43x118 change to 43x39

D

PU701

1

8

NC

7

3

VREF VCNTL

6

4

VOUT

NC

5

TP

9

+3VALW

@

PC702

1

2

1

1

+0.75VS

JUMP_43X118

2

PJ703

2

1

1

@

JUMP_43X118
PJ704
2 2
1 1

+1.05VS_VCCPP

PC704
10U_0603_6.3V6M

2

2

3

PJ702

1U_0603_10V6K

+0.75VSP

PC703
10U_0603_6.3V6M
2
1

PC705
.1U_0402_16V7K
2
1

1
PR703

S

1K_0402_1%

1
2
G

@

+1.05VS

JUMP_43X118

2011_0801 del PJ705 and "+V1.05S_VCCP"

2011_1005 PQ701 change
form SB000006800
(2N7002W T/R7 1N SOT-323)
to SB000009Q80
( 2N7002KW 1N SOT323-3)

C

2

+0.75VSP

APL5336KAI-TRL_SOP8P8

D

PC706
0.1U_0402_10V7K
2
1

(9,24,42,51) SUSP

1

PR701
1K_0402_1%

PQ701
2N7002KW _SOT323-3
PR702
49.9K_0402_1%
1
2

NC

GND

2

1

2011_1119
Change PR702 to 49.9K (SD034499280)
from 0 (SD028000080)

VIN

2

2

PC701
4.7U_0805_6.3V6K

2011_1127 PU701
Change from SA00002XR00 to SA00002XR10

1

PJ701
JUMP_43X39
@

2

2

D

2

1

1

+1.5V

C

Ivy Bridge CPU ES2 Using
2011_1127
Change PC711 from Sanyo SF000000S80
to panasonic SF000000I80

DRVL

6

PR713
470K_0402_1%
1
2

RF

TP

DL_1.05VS_VCCP

11

4

TPS51212DSCR_SON10_3X3

VFB=0.7V

2

2011_1202
PR708 change from 0 to 60.4K
PC713 mount

1

1
+

2011_0826 add
for EMI

2011_0929
PC1166 non-mount

2

+1.05VS_VCCPP

2 3

1
+

2 3

+

2 3

2011_1005 PC1167,PC1168
change to 330U_2V_R9M
VCCIO_SENSE

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

B

@

1

A

(8)

2

PR715
10K_0402_1%

B+

B+

2011_0815 PC1166, PC1167
PC1168 change place
form"+1.05VS"
to"+1.05VS_VCCPP"

PR716 @
10_0402_5%
2
1

2011_1007 PL701
form SH000004S00(S COIL 1.0UH +-20% PCMC104T1R0MN 20A) change to SH00000CN00(S COIL 1UH +20% MMD-10DZ-1R0M-X1A 18A)

1

PC711
100U_25V_M

PC710
4.7U_0805_25V6-K
2
1

PC709
4.7U_0805_25V6-K
2
1

PC717
68P_0402_50V8J
2
1
+

2

PR714
4.99K_0402_1%

A

PC715
1U_0603_10V6K

1

2011_1005 PQ805 change
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
to SB00000Q400(TPCA8057-H_PPAK56-8-5)

2011_1007 PR712
form 88.7K change to 75K
1

PQ703

+5VALW

PR711
0_0402_5%
2
1

7

1

1

V5IN

2

SW

VFB

1

LX_1.05VS_VCCP

EN

4

2

DH_1.05VS_VCCP

8

1

PC716
PR710
1000P_0603_50V7K 4.7_1206_5%

9

3
2
1

DRVH

5

TRIP

3

PL701
1UH_+-20%_MMD-10DZ-1R0M-X1A_18A

2

3
2
1

2

5
PR712
75K_0402_1%
2
1

1
2

PGOOD

2

JUMP_43X118

PC1166
330U_D2_2VM_R6M

PC713
.1U_0402_16V7K

PR707
PC712
2.2_0603_5% 0.22U_0603_16V7K
BST_1.05VS_VCCP
1
2
1
2

@

PJ706

PC1168
330U_D2_2VM_R9M

1

TRIP_1.05VS_VCCP

VBST

10

PU702

1

2

PC1167
330U_D2_2VM_R9M

PR709

2

PR708
60.4K_0402_1%
1
2
@ 10K_0402_1%

(9,24,41,42,46,48,51) SUSP#

4

1

(49) 1.05VS_VCCP_PWRGOOD

B

2011_1129
Change 2.2

1

PR706
0_0402_5%
1
2

2011_0829 PU702
PN error,change

TPCA8057-H_PPAK56-8-5

PR704
100K_0402_5%

TPCA8065-H_PPAK56-8-5

PQ702

2

2011_0801 mount
PR704, PR706

5

+3VS

PC707
0.1U_0402_25V6
2
1

1.05VS_B+

PC708
2200P_0402_50V7K
2
1

+1.05VS_VCCPP OCP(min)=20.75A
2011_0926
change part
to TPC8065
del PR705

Title

Compal Electronics, Inc.
PWR +1.05VS_VCCPP/+0.75VSP

Size
Document Number
Custom
Date:

LA-8133P
Sheet

Friday, January 06, 2012

1

50

of

Rev
0.6
58

B

1
2

PC873
68P_0402_50V8J
2
1

5
3
2
1

PC812
330U_D2_2.5VY_R9M

2

2011_1007
PC811, PC812
form SGA20331E10
(330U_D2_2V_Y)
change to SGA00002680
(330U_D2_2.5VY_R9M)

Near VGA Core

TPCA8065-H_PPAK56-8-5

PC825
4.7U_0805_6.3V6K
2
1

PC826
22U_0805_6.3V6M
2
1

PC827
4.7U_0805_6.3V6K

PC839
4.7U_0805_6.3V6K
2
1

PC840
4.7U_0805_6.3V6K

2

PC853
@0.1U_0402_10V7K

1
2

PC861
10U_0805_25V6K
2
1

PC860
10U_0805_25V6K

PC859
2200P_0402_50V7K
2
1

PC858
0.1U_0402_25V6
2
1

5
PC862
0.22U_0603_10V7K
1
2

3

2011_0826 add
for EMI

2011_0728 PL801 and PL802
(SH00000HK00/0.36uH_10X10X4)
change to (SH00000NX00/0.36uH_7X7X4)
del net name (V1N_VGA and LF1_VGA)

3
2
1

4

BOOT1_1_VGA

PC838
4.7U_0805_6.3V6K
2
1

PC822
4.7U_0603_6.3V6M
2
1
PC836
4.7U_0603_6.3V6M
PC845
@0.1U_0402_10V7K
2
1

+VGA_B+

PC874
68P_0402_50V8J
2
1

PC821
4.7U_0603_6.3V6M
2
1
PC835
4.7U_0603_6.3V6M
2
1
PC849
@0.1U_0402_10V7K
2
1

UGATE1_VGA

PC824
22U_0805_6.3V6M
2
1

PC820
4.7U_0603_6.3V6M
2
1
PC834
4.7U_0603_6.3V6M
2
1
PC852
@0.1U_0402_10V7K
2
1

1

PC819
4.7U_0603_6.3V6M
2
1
PC833
4.7U_0603_6.3V6M
2
1
PC848
0.1U_0402_10V7K
2
1

2011_0818 mount for
PC832, PC833, PC834,
PC835, PC836.

PC837
4.7U_0805_6.3V6K
2
1

PC818
4.7U_0603_6.3V6M
2
1
PC832
4.7U_0603_6.3V6M
2
1
PC847
0.1U_0402_10V7K
2
1

PC823
4.7U_0603_6.3V6M

PC817
4.7U_0603_6.3V6M
2
1
PC831
4.7U_0603_6.3V6M
2
1
PC844
0.1U_0402_10V7K
2
1

1
2
1

PC816
4.7U_0603_6.3V6M
2
1

1
2

PR858
2.61K_0402_1%
NTC_VGA
2
1

PL801
0.36UH 20% PDME064T-R36MS1R405 24A
1
2

+VGA_CORE

2
VSUM-_VGA

Layout Note:
Place near Phase1 Choke

VSUM+_VGA

2011_0815 PQ808 change
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
to SB00000Q400(TPCA8057-H_PPAK56-8-5)

ISEN1_VGA

1
+
2

1
+
2

PC867
330U_D2_2.5VY_R9M

1

1
2

PR862
10K_0402_1%

PQ808
TPCA8057-H_PPAK56-8-5

2011_0829
change part
PC864 form 0.22U to 0.1U
PC865 form 0.033U to 0.1U

PR870
10K_0402_1%
1
2

PH801
10K_0402_1%_TSM0A103F34D1RZ

PR863
1_0402_5%

3
2
1

1

4

PR861
3.65K_0805_1%
2
1

5

2011_0728
del PQ809
LGATE1_VGA

2

PR864
11K_0402_1%
2
1

PC865
0.1U_0603_25V7K
2
1

1

2

PHASE1_VGA

VSUM-_VGA

PC872
0.1U_0402_16V7K

1

PQ807

2011_1129
Change 2.2

PR857
2.2_0603_5%
2
1

@

2

PC830
4.7U_0603_6.3V6M
2
1

1
2

GPU_IMON

2011_0824
change form
VSSSENSEVGA to GND

PR856
@82.5_0402_5%

2
1
2

1

@

+
2

Under VGA Core

PC846
0.1U_0402_10V7K
2
1

@ PR848
0_0402_5%
2
+5VS

PC811
330U_D2_2.5VY_R9M

PR869
10K_0402_1%
1
2

1

PR829
10K_0402_1%

1
2

PR826
3.65K_0805_1%
2
1

5
3
2
1

ISEN1_VGA

2011_0826 add
for feedback
balance

1

PC866
330U_D2_2.5VY_R9M

1
1
PC857
0.22U_0603_25V7K

+5VS

1

0.047U_0402_16V7-K
1
2
PR851
11K_0402_1%

0_0402_5%
2
+VGA_B+

PR816->120K(SD034120380)
PR820->1.69K(SD00000JB80)
PR822->22K(SD034220280)
PR837->866(SD034866080)
PC858->0.1uF(SE026104M80)
PC859->0.068uF(SE026683K80)
PR850->22.1K(SD034221280)

ISEN2_VGA
4

2011_0826 add
for feedback
balance

2011_0830
change 1%
for feedback
balance

Compal Secret Data

Security Classification

2012/07/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Issued Date

A

PC808
10U_0805_25V6K
2
1

1
1
3

(22)

(22)

PR837
0_0402_5%
1
2

PR836
0_0402_5%
1
2

2

PC829
1U_0603_10V6K

PR867
806_0402_1%
1
2

2011_0830
N13M-GE1
OCP: 28.7A
form 1K to 806

POP:PR815,PC803

+5VS

+

2011_1007
PC866, PC867
form SGA20331E10
(330U_D2_2V_Y)
change to SGA00002680
(330U_D2_2.5VY_R9M)

2

For N13M-GE(15W without turbo)
@:PR806,PR812,PC823,PC848,PC849,PR832,
PC801,PC802,PQ801,PQ802,PQ803,PR804,
PC805,PC803,PR808,PR809,PR810,PC807,
PC804

PC807
10U_0805_25V6K

2

2

4
1
2

(22)
GPU_VID0

(22)
GPU_VID1

(22)
GPU_VID2

(22)
GPU_VID3

PR835
0_0402_5%
1
2

PR834
0_0402_5%
1
2

PR850
1

PC870
@0.01U_0402_25V7K

PR866
10_0402_5%
1
2

2

1

PR865
0_0402_5%
1
2

PC869
@330P_0402_50V7K
2
1

PC868
1000P_0402_50V7K

(23) VSSSENSE_VGA

ISEN2_VGA

2011_0830
change 1%
for feedback
balance

10uF

PR843
VCCP_VGA1
2
0_0402_5%

1

2

2
VDD_VGA
2

1

PC855
0.22U_0402_10V6K

1
2

PC863
330P_0402_50V7K

+VGA_CORE

VSUM-_VGA
VSUM+_VGA

PC815
1U_0603_10V6K

VSUM+_VGA

2
PR859
0_0402_5%

1

PR830
1_0402_5%

TPCA8057-H_PPAK56-8-5

VSUM-_VGA

2

1

30
29
28
27
26
25
24
23
22
21

PR853
1_0402_5%
1
2

PR855
10_0402_5%

(23) VCCSENSE_VGA

PC806
2200P_0402_50V7K
2
1

2
1

1

1
2

2
1
1

GPU_VID4

40
39
38
37
36
35
34
33
32
31
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

11
12
13
14
15
16
17
18
19
20
RTN_VGA
ISUM-_VGA

VIN_VGA

VSUM_VGA_N001

2011_0929
PR855.1 net change form
+VGA_CORE to +VGA_COREP

2

PC854
0.22U_0402_10V6K

1
1

2011_0728
del PQ806

4

2011_0815 PQ805 change
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
to SB00000Q400(TPCA8057-H_PPAK56-8-5)

ISL62883CHRTZ-T_TQFN40_5X5

ISEN1_VGA

PR854
68.1K_0402_1%

B+

PL802
0.36UH 20% PDME064T-R36MS1R405 24A
1
2

PHASE2_VGA

IMON_VGA

VSEN_VGA

For 15W one phase

ISEN2_VGA

+VGA_CORE

4

AGND

1

1

TPCA8065-H_PPAK56-8-5

UGATE2_VGA

BOOT1_VGA

2011_0829
change part
PR852 form 267K to 33K
PC842 form 680P to 390P

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PC864
0.1U_0603_25V7K
2
1

2

PR852
33K_0402_1%

41

@ PR847
0_0402_5%
2
+5VS

1

2FB2_VGA1

PC809
0.22U_0603_10V7K
1
2

BOOT2_2_VGA

2

JUMP_43X118

2011_0728 PL801 and PL802
(SH00000HK00/0.36uH_10X10X4)
change to (SH00000NX00/0.36uH_7X7X4)
del net name (V2N_VGA and LF2_VGA)

4
PR821
2.2_0603_5%
2
1

BOOT2_VGA

PJ802

2011_0826 add
for EMI

Confirm with HW

PQ805

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

390P_0402_50V7K

2

1

PC850
150P_0402_50V8J

1
2
3
4
5
6
7
8
9
10

PR846
499_0402_1%
PC842
2FB1_VGA1
2
PR849
1.15K_0402_1%
1
2
1

PR817 @
0_0402_5%

PQ804

PC851
2
1

PC828
22P_0402_50V8J

PC843
100P_0402_50V8J
1
2

3

COMP_VGA
FB_VGA
2ISEN3_VGA

1

PC841
1000P_0402_50V7K

1
2

PR844
@249K_0402_1%
1
2

PR845
8.06K_0402_1%
2
1

2011_0727
mount PR842,PH802

1

PQ801
2N7002KW_SOT323-3

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

VW_VGA

PH802

SUSP

+VGA_CORE

470K_0402_5%_TSM0B474J4702RE
2
1
2

PR842

2

2
@

DGPU_PWROK# (24)
SUSP (9,24,42,50)

LGATE2_VGA

PU801

2

1

4.02K_0402_1%

1

+VGA_CORE

2

PR841 @
0_0402_5%

2011_0727
del PC814

S

PR825
0_0402_5%

2011_0929 PR827
change to @

RBIAS_VGA
PSI#_VGA

1

+VGA_B+

2011_1129
Change 2.2

2
+3VS

+1.05VS_VGA

PR815
0_0402_5%
1
2

2
G

PR839
147K_0402_1%
1
2

PR840
@ 100K_0402_5%
1
2

1

1

2011_0830
change P/N

@

PR838
100K_0402_5%
1
2

+3VS

2

CLK_ENABLE#_VGA

PR831
@1.91K_0402_1%

2011_0929 PR839
for 47Kohm change to 147Kohm

(22,41) VGA_AC_DET

2
G
3

PR819 @
0_0402_5%

(18,24) DGPU_PWROK

2

PC803

PJ801

@ JUMP_43X118

1

PR827
1.91K_0402_1%
1
2

HW䪗㚱PU

PC802

@
PR813
470_0603_5%

2

2011_0727 modfiy net

@

1

+3VS

2

2

(22) DPRSLPVR_VGA

+1.05VS

1
2
3

D

D

PC856
1U_0603_10V6K
2
1

SUSP#

1

GPU_VID6

2011_0727 add PR868 and
place port DPRSLPVR_VGA
2011_0819 unmount PR868

PR818
0_0402_5%
2

2

PR820
147K_0402_1%
VRON_VGA
1
2
PD802
1
2
RB751V-40_SOD323-2
@
1 PR822 2
@2 PR823 1
@0_0402_5%
47K_0402_5%
1
2
PR868
0_0402_5%
1
2
@
PC810
.1U_0402_16V7K
10K_0402_1%
PR824 1
DPRSLPVR_VGA+
2

(17) NVDD_PWR_EN

+1.05VS_VGA
8
7
6
5

10U_0805_10V6K 1U_0603_10V6K
TPC8A03-H_SO8 PQ802

PR814

20K_0402_1%
PR816
D
100K_0402_5%
1
2
PC804
PQ803
0.1U_0603_25V7K
2011_0727 PR816
S
2N7002KW_SOT323-3
modfiy 10K to 100K.

PR833
0_0402_5%
1
2

1

SUSP

1

GPU_VID5

10K_0402_1%
2

10K_0402_1%
2

10K_0402_1%
2

10K_0402_1%
2

10K_0402_1%
2
PR812
GPU_VID0
1

PR811
GPU_VID1
1

PR810
GPU_VID2
1
@

(24) DGPU_PWROK#
(9,24,42,50) SUSP
PD801

RB751V-40_SOD323-2

(9,24,41,42,46,48,50)

@

C

+1.05VS

PC801
10U_0805_10V6K

PR832
0_0402_5%
1
2

2011_1202
Change PR820 from 0 to 147K
PC810 mount

PR809
GPU_VID3
1

10K_0402_1%
2
@

PR808
GPU_VID4
1

PR807
1

@

GPU_VID5

10K_0402_1%
2

10K_0402_1%
2
PR806
GPU_VID0
1

10K_0402_1%
2

10K_0402_1%
2

PR805
GPU_VID1
1

PR804
1

@

GPU_VID2

10K_0402_1%
2

10K_0402_1%
2

PR803
GPU_VID3
1

PR802
GPU_VID4
1

PR801
1
GPU_VID5
1

@

2011_1007
N13M-GE1
VID: 0110100
0.85V
+5VALW

PC805
0.1U_0402_25V6
2
1

A

+3VS_VGA

B

2011/07/12

C

Deciphered Date

Date:

Compal Electronics, Inc.
PWR - VGA_COREP

Document Number

LA-8131P
Sheet

Friday, January 06, 2012
D

51

Rev
0.6
of

58

4

3

2

1

2011_1007 for function test
1. modify PR903 form 1.21K to 8.2K,
2. PC905 form 4700p to 33n,
3. PC901 form 680p to 33n,
4. PR904 form 10.7K to 806,
5. PC907 form 330p to 560p
6. PC909 form 3300p to 1500p
7. PC904 form 330p to 820p
8. PR911 form 63.4K to 66.5K
9. PR942 form 4.32K to 6.04K
10. PC927 form 3300p to 2200p
11. PC934 330p to 820p

2011_0830
PC901,PC905,PR901,PR903,PR904 mount

1

2

1K_0402_1%

DROOP

PC935
1
2

CSREF

1000P_0402_50V7K


3P:
2P: 1K

A

1
2

PC904
1
2

PR905
1
2
75K_0402_1%

PUT COLSE
TO VCORE
Phase 1
Inductor

2
1

1

8.25K_0402_1%

2
1

PR915
2
LG2

6132P_VCCP

LG1
HG1

BST1

(53)
PR9242 BST2_1 1
1
2.2_0603_5%
(53)

PC918
2
0.22U_0603_25V7K

PC919
(53)
1
2
2.2U_0603_10V7K
1 PR928 2
(53)
+5VS
0_0402_5%
PC921
(53)
PR9312 BST1_1 1
1
2
2.2_0603_5%
0.22U_0603_25V7K

+5VS
SW1A

(53)

SW2

(53)

SW1

(53)

Option for
1 phase GFX
CSP2A

2011_0809
PR928 change place

PR9342
41.2K_0402_1%

2Phase: @
1Phase: install

1

HG2

PR920
PC917
1
2 BSTA1_11
2
2.2_0603_5%
0.22U_0603_25V7K
(53)

PR929
0_0402_5%

+5VS

3P: 73.2K
2P: 41.2K

Option for
2 phase CPU

CSP2

PR935
0_0402_5%

3P: 1500p
2P: 1200p

2 PC934
820P_0402_25V7

PR940
1
2
6.98K_0402_1%

SWN2

(53)

2

B

TSENSE

PR944
1
2
6.98K_0402_1%
PR955
20K_0402_1%
@

PC930
0.047U_0402_16V7K
CSREF

SWN1

(53)

2

CSP1

(53)

CSSUM
PC932
2
1200P_0402_50V7K

1

PR954
20K_0402_1%
@

CSREF

CSREF

3Phase: @
2Phase: install

20k_0402_1%

PR945 1

PC925
0.047U_0402_16V7K

PC929
1000P_0402_50V7K

CSP3

2011_0930
add PR954

PC923
2
.1U_0402_16V7K

C

2

LG1A

BST2

PUT COLSE
TO V_GT
HOT SPOT

2011_0829
PR920,PR924,PR931
form 4.7 to 2.2

1

HG1A

2
1

CSCOMP
PC933
1
2

24.9K_0402_1%

.1U_0402_16V7K

CSCOMP

BSTA1

3P: 21K
2P: 12.4K

1

3P: 23.7K
2P: 24.9K
PR953

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

CSP1
CSP2
CSP3

3P: 3.65K
2P: 9.53K

2P: 36K
1P: 26.1K
6132_PWMA

1

3P: 2200p
2P: 3300p

100K_0402_1%_TSM0B104F4251RZ

PH903
100K_0402_1%_TSM0B104F4251RZ

1

9.53K_0402_1%

2

3P: 348
2P: 1.21K

2

PR949
1

1
PC931

2

1.21K_0402_1%

1

PH902

6132_PWM

10P_0402_50V8J

3P: 6.04K
2P: 4.32K

PR947
4700P_0402_25V7K

PR943
PC928
1
2FB_CPU3 1
2
10_0402_1%
680P_0402_50V7K
PR946
FB_CPU2
1
2

TRBST#

PR918
1
2
26.1K_0402_1%

1

PR941
PC926
PR942
PC927
1
2FB_CPU1 1
2
2
1COMP_CPU1 2
1
49.9_0402_1%
6.04K_0402_1%
1000P_0402_50V7K
2200P_0402_50V7K

(53)

.1U_0402_16V7K

1

PC924
2
1

SWN1A

2

1 PR939 2
1K_0402_1%

3P: 330p
2P: 1000p

2011_1119
Change PC936 to 47P (SE071470J80)
form 43P (SE00000D180)

6.98K_0402_1%
2

2

2011_1005
for Intel add PC836 SE00000D180 (43P_0402_50V8J)

TSENSEA

1

PC922
1000P_0402_50V7K
VSP

3P: 22p
2P: 10p

CSREFA

1000P_0402_50V7K

2

VSN

PC906
1
2

DROOPA

CSREFA (53)

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2

PR937
1
2
0_0402_5%

(8) VCCSENSE
B

1

PR936
1
2
0_0402_5%

PR912
1

1

VGATE

CSP1A

PC910
0.047U_0402_16V7K

2

1
2

1
2

(15)

(8) VSSSENSE

PR906
2

PC913
1
2

PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
NCP6132AMNR2G_QFN60_7X7
LG2
PVCC
PGND
LG1
SW1
HG1
BST1

TRBST#
FB_CPU
COMP_CPU
IMVP_IMON
IMON
ILIM_CPU
1
2
PR938 12.4K_0402_1%
DROOP

1
2

PR933
10K_0402_5%

VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF

2
(41,45) VR_HOT#

PC903
1
2

DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
6132_VCC

1

1K_0402_1%


PC911
1000P_0402_50V7K

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA

.1U_0402_16V7K

1
1

PR932
75_0402_1%

2

PC936
47P_0402_50V8J

SWN1A

PU901

0.01U_0402_25V7K

+1.05VS

CSREFA

2

TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM

2

2011_0819
change to

PR9192
1
2_0603_5%
PC914
1
2

1
2.2U_0603_10V7K
2
PR923
VR_RDYA
3
VR_ON_CPU
4
1
2
(41)
VR_ON
PC916
VR_SVID_DAT1 5
0_0402_5%
VR_SVID_ALRT# 6
PR927
PR925
VR_SVID_CLK
7
95.3K_0402_1%
0_0402_5%
8
1
2 VBOOT
10K_0402_1%
ROSC_CPU
9
1 PR926 2VR_SVID_DAT1
1
2
VRMP
10
CPU_B+ 1
2
VR_HOT#
11
PR930 1K_0402_1%
VGATE
+V1.05VS_VCCP
12
13
+1.05VS
PC920
14
+3VS
DIFF_CPU
15

PR922
1
2
54.9_0402_1%

PR921 2

1

130_0402_1%

1
2

.1U_0402_16V7K

+5VS

VR_RDYA

(8) VR_SVID_DAT
(8) VR_SVID_ALRT#
(8) VR_SVID_CLK

PC912
1000P_0402_50V7K

PR911

1

64.9K_0603_1%

2P: 21.5K
1P: 15.8K

PR917
10K_0402_1%

2011_0819 +V1.05VS_VCCP
change to +1.05VS

PC915

1500P_0402_50V7K

1

+1.05VS

C

PR916
1
2
0_0402_5%

CSCOMPA

220K_0402_5%_ERTJ0EV224J


1

PR913
1
2
0_0402_5%

NTC_PH203

2P: 1.65K
1P: 1K

PR910 10P_0402_50V8J PC909
2 COMPA1 1
2

5.11K_0402_1%

1K_0402_1%

+3VS

1

PR9071
2
165K_0402_1%

2

560P_0402_50V7K

PR9092

(9) VCC_AXG_SENSE

PC908
1
2

CSSUMA

FBA2

1
2
10_0402_1%
1

PC907
1
2

D

PUT COLSE
TO GT
Inductor

PH901

2

PR908

(9) VSS_AXG_SENSE

24.9K_0402_1%

2P: 24K
1P: 24.9K

806_0402_1%

PC905

0.033U_0402_16V7

.1U_0402_16V7K
1 PR902 2

2

2

PR903
8.2K_0402_1%

PR904

1

1

1

TSENSE

FBA1

2

2

1

PC902
2

1PR914
2
15.8K_0402_1%
CSCOMPA

10_0402_1%
TRBSTA#

1

820P_0402_25V7

2011_0829
PC909
change part

CSP2A
CSP1A
TSENSEA

PC901
0.033U_0402_16V7
FBA3
1
2

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

D

2

1

PR901

1

1200P_0402_50V7K

2011_1119
Change PC901,PC905 to 0.033u (SE076333K80)
from 0.033u (SE076333KN0)

8.25K_0402_1%

5

1

PR9482
130K_0603_1%

SWN1

1

PR9502
130K_0603_1%

SWN2

2011_0930
add PR955

20k_0402_1%

PUT COLSE
TO VCORE
HOT SPOT

1 PR951 2NTC_PH201 1 PR952 2
75K_0402_1%
165K_0402_1%
PH904
2

1
220K_0402_5%_ERTJ0EV224J


A

(41) IMVP_IMON

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR-CPU_CORE1

Size Document Number
Custom
Date:

LA-8133P
Sheet

Friday, January 06, 2012

1

Rev
0.6
52

of

58

2

3

2011_1005 PC1009 change
form SF000000S80
(100U 25V M 6.3X7.7 CE-LX )
to SF000000W00
( 68U 25V M 6.3X5.8 ESR0.36 FK)

2
1SNUB_CPU1

V1N_CPU2

1

CSREF (52)

PQ1004

SWN1

(52)

4

LG2

2011_1005 PQ1003 change
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
to SB00000Q400(TPCA8057-H_PPAK56-8-5)

2011_1127
Change PL1001,PL1003,PL1004
from SH00000HK00 to SH00000N900
PCMB104T-R36MH1R105 30A GLUE

(52)

TPCA8057-H_PPAK56-8-5

2011_1127
Change PL1002 from SM010018210 to SM01000JR00
HCB4532VF-800T90 1812 for EOL
2011_1005 PQ1004 change
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
to SB00000Q400(TPCA8057-H_PPAK56-8-5)

1

680P_0603_50V7K

PC1004
0.1U_0402_25V6
2
1

PC1007
10U_0805_25V6K
2
1

PC1008
2200P_0402_25V7K
2
1

D

2

3

PR1004
4.7_1206_5%

10_0402_1%

PC1010

PC1006
10U_0805_25V6K
2
1

PC1018
68P_0402_50V8J
2
1

5
3
2
1

SW2

2

2

TPCA8057-H_PPAK56-8-5

PR1005

(52)

+CPU_CORE

PL1003
PCMB104T-R36MH1R105_30A_GLUE
1
4
1

4

4

HG2

2011_0727
chang net name

2

1

(52)

2011_0815 change PC1009 of place
form"CPU_B+" change to "B+"

CPU_B+

V2N_CPU 2 PR1006 1
10_0402_1%

SNUB_CPU2

5
4

3
2
1

+
2

PR1003
4.7_1206_5%

PQ1003

LG1

1

+CPU_CORE

PQ1002
CPU_B+

5

PC1003
0.1U_0402_25V6
2
1

PC1002
10U_0805_25V6K
2
1

SW1

(52)

PL1002
HCB4532VF-800T90_1812
1
2

PL1001
PCMB104T-R36MH1R105_30A_GLUE

1

(52)

2011_0826 add
for EMI

B+

2011_0727
chang net name

1

2011_0926
change part
to TPC8065
del PR1002

3
2
1

3
2
1

D

PC1001
10U_0805_25V6K
2
1

4

HG1

PC1017
68P_0402_50V8J
2
1

(52)

TPCA8065-H_PPAK56-8-5

PQ1001

2

2011_0801 PC1009 form SF22004M210_220U 25V M
8X10.2 CE-AX change to SF000000S80_100U 25V M
6.3X7.7 CE-LX and place

CPU_B+

PC1009
68U_25V_M_R0.36

2011_0826 add
for EMI

5

2011_0926
change part
to TPC8065
del PR1001

3

TPCA8065-H_PPAK56-8-5

4

PC1005
2200P_0402_25V7K
2
1

5

CSREF

SWN2

(52)

PC1011
680P_0603_50V7K

C

C

QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A

2011_0826 add
for EMI

3
2
1

PC1014
0.1U_0402_25V6
2
1

PC1013
10U_0805_25V6K
2
1

PC1012
10U_0805_25V6K
2
1

PL1004

1

TPCA8057-H_PPAK56-8-5

PR1008
4.7_1206_5%
2

PQ1006

1

4

2

3

2

1

SNUB_GFX1

4

LG1A

3
2
1

(52)

+VCC_GFXCORE_AXG

PCMB104T-R36MH1R105_30A_GLUE

SW1A
5

(52)

B

V1N_GFX

4

HG1A

PC1015
2200P_0402_25V7K
2
1

PQ1005

(52)

CPU_B+

TPCA8065-H_PPAK56-8-5

5

B

PC1019
68P_0402_50V8J
2
1

2011_0926
change part
to TPC8065
del PR1007

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

2

PR10091

CSREFA (52)

10_0402_1%
PC1016
SWN1A (52)

680P_0603_50V7K

A

A

QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
5

4

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A

Compal Secret Data

Security Classification

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title
Size
C
Date:

Compal Electronics, Inc.
PWR-CPU_CORE2

Document Number

LA-8133P
Sheet

Friday, January 06, 2012

1

Rev
0.6
53

of

58

+CPU_CORE
1
2

4

2011_0727
chang net name

1

PC1101
10U_0805_6.3VAM

2

2011_0727
chang net name

1
PC1102
10U_0805_6.3VAM

3

2

1
PC1103
10U_0805_6.3VAM

2

2

+CPU_CORE

1

Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_GFXCORE_AXG

1
PC1104
10U_0805_6.3VAM

2

PC1105
10U_0805_6.3VAM

Socket Bottom

5 x 22 ȝF (0805)
5 x (0805) no-stuff
sites

Socket Top

7 x 22 ȝF (0805)
2 x (0805) no-stuff
sites

+VCC_GFXCORE_AXG

D

+CPU_CORE 2011_0727

2

@
PC1171
22U_0805_6.3V6M

2

B

1
PC1173

+

330U_D2_2VM_R9M
2 3

1
PC1174

330U_D2_2VM_R9M
2 3

+

330U_D2_2VM_R9M
2 3

+

2

+

2011_0815 PC1160
change form unmount
to mount
2011_0815 PC714 change place
form "+1.05VS_VCCPP" to "+1.05VS"
2011_1005 PC714 change to
330uF_2V_R9M

2011_1007
PC714
form SGA00001Q802
(S POLY C 330U 2V M X LESR6M SX H1.9)
change to SGA00002680
(330U_D2_2.5VY_R9M)

1
PC1175

2

@

2

chang net name

+

2

1

C

+CPU_CORE 2011_0727
1

2

1

@

2

1

2011_07929
PC1158 non-mount

@
PC1172
22U_0805_6.3V6M

2

1

2

PC1156
22U_0805_6.3V6M

@
PC1170
22U_0805_6.3V6M

2

1

2

@

PC1135
22U_0805_6.3V6M

2

1

2

1
@

2

1

PC1155
22U_0805_6.3V6M

PC1169
22U_0805_6.3V6M

1

2 3

2

1
@

2

PC1134
22U_0805_6.3V6M

2

1

+

1

@

2

1

PC1154
22U_0805_6.3V6M

2011_0815 del PC1157

1

1

2

+1.05VS
PC1133
22U_0805_6.3V6M

2 3

1

2

1

PC1153
22U_0805_6.3V6M

PC1165
22U_0805_6.3V6M

+

2

PC1132
22U_0805_6.3V6M

2

2

1

PC1152
22U_0805_6.3V6M

2

2

2

1

PC1131
22U_0805_6.3V6M

2

1
PC1164
22U_0805_6.3V6M

2

1

1

PC1151
22U_0805_6.3V6M

2

1
PC1163
22U_0805_6.3V6M

2

1

PC1160
330U_D2_2VM_R9M

2

1
PC1162
22U_0805_6.3V6M

1

PC1159
330U_D2_2VM_R9M

@

PC1158
330U_D2_2VM_R9M

1

2 3
1

2

1

1

PC1130
22U_0805_6.3V6M

PC1148
22U_0805_6.3V6M

C

PC1161
22U_0805_6.3V6M

2

1

2011_0901 mount PC1140,PC1141
PC1142,PC1143

+

1

2

1

1

PC1150
22U_0805_6.3V6M

2

2

1

1

+1.05VS
1
1

PC1129
22U_0805_6.3V6M

2

PC1147
22U_0805_6.3V6M

@

PC1149
22U_0805_6.3V6M

2

PC1146
22U_0805_6.3V6M

1

1

2011_0808 place power name
change form +V1.05S_VCCP
to +1.05VS
PC1128
22U_0805_6.3V6M

2

PC1145
22U_0805_6.3V6M

1

@

2

PC1127
22U_0805_6.3V6M

PC1144
22U_0805_6.3V6M

1

2

1

PC1143
22U_0805_6.3V6M

2

1

1

PC1142
22U_0805_6.3V6M

1
2

1

2

PC1141
22U_0805_6.3V6M

2

PC1124
22U_0805_6.3V6M

PC1140
22U_0805_6.3V6M

2

PC1123
22U_0805_6.3V6M

PC1139
22U_0805_6.3V6M

2

PC1122
22U_0805_6.3V6M

@

2

1

2011_0901 unmount PC1114,PC1115
PC1118,PC1119

1

PC1138
22U_0805_6.3V6M

2

PC1121
22U_0805_6.3V6M

1

PC1137
22U_0805_6.3V6M

PC1120
22U_0805_6.3V6M

1

PC1136
22U_0805_6.3V6M

2

1

@

2

1

PC1126
22U_0805_6.3V6M

1

2

1

PC1125
22U_0805_6.3V6M

chang net name

2

1

PC1119
22U_0805_6.3V6M

2

1

PC1118
22U_0805_6.3V6M

2

1

@
PC1111
10U_0805_6.3VAM

PC1117
22U_0805_6.3V6M

2

1
PC1110
10U_0805_6.3VAM

PC1116
22U_0805_6.3V6M

2

1
PC1109
10U_0805_6.3VAM

PC1115
22U_0805_6.3V6M

2

1
PC1108
10U_0805_6.3VAM

PC1114
22U_0805_6.3V6M

2

1
PC1107
10U_0805_6.3VAM

PC1113
22U_0805_6.3V6M

2

1
PC1106
10U_0805_6.3VAM

PC1112
22U_0805_6.3V6M

1

D

PC714
330U_D2_2.5VY_R9M

5

PC1176

330U_D2_2VM_R9M
2 3

B

2011_1007
PC1173 mount
1 @
+

2011_1005
chang to 330uF_2V_R9M

1
PC1177

+

470U_D2_2VM_R4.5M
2 3

PC1178

330U_D2_2VM_R9M
2 3

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title
Size
Date:

Compal Electronics, Inc.
PWR - PROCESSOR DECOUPLING
Document Number

LA-8131P
Sheet

Friday, January 06, 2012

1

54

of

58

Rev
0.6

A

B

C

D

2011_0923 JUMP form 43X79 change to 43X79

1

2

PR1204
1M_0402_5%

1
2

1
2

PC1205
22U_0805_6.3VAM

SY8033BDBC_DFN10_3X3

+1.05VMP

2

PJ1202
2

1

1

+1.05VM

@ JUMP_43X79

1.05VMP max current=1A
1.05VMP_FB
1

2

0_0402_5%

FB=0.6Volt

2

EN_1.05VMP

1

TP

11

2

1

(41,42) M_PWR_ON

PR1203

PC1206 @
0.1U_0402_10V7K

1

PR1202
7.5K_0402_1%

PC1204
22U_0805_6.3VAM

FB

6

EN

+1.05VMP
PC1202
68P_0402_50V8J
2
1

SVIN

5

1

8

1

3

1

PL1201
1UH_PH041H-1R0MS_3.8A_20%
1
2

1 2

LX

NC

LX

PVIN

PG

PVIN

9

1.05VMP_LX

2

4

1
2

PC1201
22U_0805_6.3VAM

2

NC

1

JUMP_43X39
@
PC1207
22U_0805_6.3VAM

10

7

2

PU1201
1.05VMP_VIN

1
1

PJ1201

2

+5VALW

2

PC1203
PR1201
680P_0603_50V7K 4.7_1206_5%

1

2

PR1205
10K_0402_1%

2

2

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
PWR-+1.05VMP

Size Document Number
Custom
Date:

LA-8133P
Sheet

Friday, January 06, 2012

D

Rev
0.6
55

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title
Size
Date:

Compal Electronics, Inc.
PWR-Thermal Protect
Document Number

LA-8131P
Friday, January 06, 2012
Sheet
1

Rev
0.6
56

of

58

5

4

9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP

5HDVRQIRUFKDQJH

3*

3

2

0RGLI\/LVW

1

'DWH

3KDVH



D



D










C



C







B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

Compal Electronics, Inc.
2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title
Size Document Number
Custom
Date:

PIR (PWR)

LA-8133P
Sheet
Friday, January 06, 2012
1

Rev
0.6
57

of

58

1

2

3

4

5

9HUVLRQ&KDQJH/LVW 3,5/LVW
Phase

A

Date

No.

2011/09/13

No1

V

C

Sch

Layout
V

Description

function

Add C2325,C2326,C2327,C2328,C2329,R2319,R2324,Q2312

Add SBA function (+3VM) power

2011/09/15

No2

V

Del Q2305

Del SYSYON#

2011/09/15

No3

V

Add EC pin 119(M_PWR_ON) for SBA function

Add SBA function

2011/09/15

No4

V

Add EC pin 120(PCH_SLPA#) from PCH to EC for SBA function

Add SBA function

2011/09/15

No5

V

Add EC pin72 (Muxless_STAT) for GPU STAT

Add Muxless_STAT function

2011/09/15

No6

V

Del PR310, PR311, PR312, PR313, net name:"H_PROCHOT#", +3VALW.

PWR-CHARGER-BQ24727

2011/09/15

No7

2011/09/15

No8

V

V

Add R2482,Q2404,C2509,R2481,R2485,Q2400,R2483,C2501

AOAC Function

2011/09/15

No9

V

V

change net name BT_OFF# to BT_ON# and change PCH EN GPIO from GPIO34 to GPIO36
R280 from @ to mount,R282 from mount to @

BT Function

V

change net name(Mini-Express) from BT_OFF# to WLBT_OFF#
PCH EN GPIO change to GPIO34

BT Function
AOAC Function

2011/09/15

B

BOM

No10

A

mount PC832

V

V

2011/09/19

No11

V

V

change +3VS_WLAN net name to +3VS_AOAC
change +3VS_WWAN net name to +3VS_AOAC

2011/09/19

No12

V

V

Del R1010 for LVDS CONN plug high voltage

LVDS CONN

2011/09/19

No13

V

V

R1102,R1104,R1105 from @ to mount fix MIC(ECR97236)issue

MIC function

2011/09/19

No14

V

V

Add R2470 for 80 port function

80 port function

2011/09/19

No15

V

V

Del R2476 Add Q2405

BT Function

Add power schematic 9/15 again modify RF PC423, PC425, PC519, PC620, PC717,
PC873, PC874, PC424, PC518 PC1017, PC1018, PC1019, PC422, PC516, PC517
modify POWER⛐VGA䘬PWM IC ≈䘬暞ẞPR869, PR870

2011/09/20

No16

V

V

2011/09/22

No17

V

V

Add U10,C589,C645

2011/09/22

No18

V

V

Add R110,R112 for SPI POWER choose(SBA function)

2011/09/23

No19

V

V

modify power page 44~57(PJ1201 JUMP form 43X79 change to 43X79)

2011/09/26

No20

V

V

change
change
change
change

2011/09/26

No21

V

V

change PCH_GPIO24(R288) pull up to +3V_PCH

2011/09/26

No22

V

2011/09/26

No23

V

2011/09/26

No24

V

V

PQ702 change to TPC8065,Del PR705
PQ1001,PQ1002,PQ1005 change to TOC8065,Del PR1001,PR1002,PR1007

2011/09/26

No25

V

V

p43 change Q2304 dual channel 2n7002 to single channel Q2304,Q2305(Q2305 @)
p43 change Q2306 dual channel 2n7002 to single channel Q2306,Q2311(Q2311 @)

2011/09/27

No27

2011/09/27

No28

V

V

net name CX_GPIO0 connect to U1101 pin 38

2011/09/27

No29

V

V

Add C2152,C2153,D2113 for ESD

2011/09/27

No30

V

V

change NVIDIA N13M ROM_SCLK from 15K PU to 5K PU

2011/09/27

No31

V

V

change ESD part D2401,D2403,D2405 power from +5VALW to +USB VCCA

2011/09/27

No32

V

V

Add C2108 for GPU_CLKREQA

2011/09/27

No33

Add Q2406 , modify R2401,Change PCH_GPIO19 to ODD_DET#,for zero power ODD

2011/09/27

No34

change WLBT_OFF# to PCH_GPIO34

2011/09/27

No35

change PCH_GPIO34 to WLBT_OFF#(mini card pin5)

2011/09/27

No36

change BT_ON# connect to WLBT_OFF#(mini card pin51)

2011/09/28

No37

C76 , R1123 , c1131 , R2201,C2209 C84,C85 from @ to mount for RF team

2011/09/29

No38

R1529 change to 15K

2011/09/29

No39

Add CONN JDB3 fo debug

2011/09/29

No40

Add R2460,R2438,R2471,R2472,R2475,R2476 for PS8520B

2011/09/29

No41

change D2403 ,D2401 power to +USB_VCCB,and del D2403 ,D2401,D2405 Pin3

2011/09/29

No42

2011/09/29

No43

change power schematic
del PC606 (22U_0805_6.3V6M)
PR855.1 net change form +VGA_CORE to +VGA_COREP
PR827 mount change to @(non-mount)
PR839 for 47Kohm change to 147Kohm
PR103 for 0ohm change to 270ohm
PC1166 non-mount,PC1173 non-mount,PC1158 non-mount

2011/09/29

No44

Add Q2313,C2305,C2306,C2307,C2308,R2318,R2320,R2320,C2322 for +3V_PCH

2011/09/29

No45

change CRT CONN to DC061109231(footprint pin modify)
Add PR954,PR955
Add H16,H27
change Q2304.Q2305 to Q2304
modify PTH H11,H18 ,H21
Del T10 for SUS_STAT(SLP_S3# 崘ᶵ↢Ἦ)

2011/10/04

No46

reserve R352,R353 for SATA re-drive PS-8131B
change net name fron WLBT_OFF to WLBT_OFF_5#
modify PCH_GPIO34 connect to BT_ON# for BT module
modify PCH_GPIO36 from BT_ON# connect to WLBT_OFF_51# for mini card BT combo module
changr Q2301 to 2N7002

2011/10/05

No47

Del R2469,T49,T45,T41,T37,T36,T28,T26 for ME 旸檀0
changer power net +3VS_FP to +3VS
update power schematics P44~P57

2011/10/06

No48

D

for TPM function

TPM function

CPU footprint from TYCO_2013620-2_989P-T to TYCO_2013620-2_989P-T-A39
PCH footprint from PANTHER-POINT_FCBGA_989P-T to PANTHER-POINT_FCBGA_989P-T-A39
GPU footprint N13P-PES-A1_FCBGA_908P to N13P-PES-A1_FCBGA_908P-A39
VRAM footprint K4W1G1646E-HC12_FBGA_96P to K4W1G1646E-HC12_FBGA_96P-A39

B

change P18 (R311,R330,R286,R329) for UMA and Optimus memon
change net name PCH_THRMTRIP#_R to VGA_THRMTRIP#

modify EC Board ID R2213 to 18K

V

C

net

D

change Q1202 part to SB000007H10.
change JCARD1 PN to SP02000H810 footprint: ACES_87213-1400G_14P
change some CONN part NO. for ME CONN list
Add D2416

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

Compal Electronics, Inc.
2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

PIR (EE)
Size Document Number
Custom
Date:

Rev
0.6

LA-8133P

Friday, January 06, 2012

5

Sheet

58

of

58

www.s-manuals.com



---

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Producer                        : Acrobat Distiller 10.0.0 (Windows)
Modify Date                     : 2014:04:28 21:57:39+03:00
Create Date                     : 2012:02:14 00:40:32+07:00
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Format                          : application/pdf
Title                           : Compal LA-8131P, LA-8132P - Schematics. www.s-manuals.com.
Creator                         : 
Description                     : 
Description (x-repair)          : 
Subject                         : Compal LA-8131P, LA-8132P - Schematics. www.s-manuals.com.
Has XFA                         : No
Page Count                      : 59
Keywords                        : Compal LA-8131P, LA-8132P - Schematics. www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

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