Compal LA 8241P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-8241P QCL00/QCL20 - Schematics. Free.

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MODEL NAME : QCL00_QCL20
PCB NO : LA-8241P
BOM P/N : 4619GP31L21 Inspiron DIS
4619GQ31L21 Inspiron UMA
4619GP31L01 Vostro DIS
4619GQ31L01 Vostro UMA

1

Dell / Compal Confidential
Schematic Document
2

Inspron A5 & Vostro 3560 (Intel Chief River)
Ivy Bridge(rPGA) + Panther Point(mainstream)

2

Discrete AMD Thames-XT
3

4

2012-02-01
46@ : for 46 level
@ : Nopop Component
Rev: 1.0
CONN@ : Connector Component
KB930@ : ENE KB930 Implemented
MB Type
KB9012@ : ENE KB9012 Implemented
EXP@ : Express Card Implemented
FFS@ : Only for Free Fall Sensor
VOS@ : Only for Vostro
INS@ : Only for Inspiron
UMA@ : Only for UMA
GCLK@ : Green CLK implemented
AMP@ : External Amplifier implemented
KBBL@ : Keyboard Back Light implemented

BOM P/N

Config

Compal Electronics, Inc.

Compal Secret Data
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

3

4

Security Classification
Issued Date

X76@ : VRAM Group
CH@ : Chelsea M2
SE@ : Seymour M2
TH@ : Thames-XT
DIS@ : Only for Discrete

D

Cover Page
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
E

1

of

56

A

B

C

D

Compal Confidential

E

CPU XDP
Conn. P.6

Fan Control
P.25

Project Code : QCL00 / QCL20
File Name : LA-8241P

64M*16

VRAM * 4
P.40
DDR3
64bit

1

64M*16

VRAM * 4
P.41
DDR3

64bit

AMD
Thames-XT /
Chelsea Pro
24-26 W P.34~39

PEG 3.0 x16

Intel
Ivy Bridge
Processor
35W QC rPGA 988
35W DC rPGA 988

Memory Bus (DDR3)
Dual Channel

DDRIII-DIMM X2

1

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

1.5V DDR3 1333 MHz

page 11,12

8GB Max

P.5~10

FDI x8

DMI x4

100MHz
2.7GT/s

100MHz
5GB/s

Port 0

SATA3.0
CRT

CRT Conn.

P.22

( Full )

Port 2

Intel
Panther Point
PCH HM77

P.22

HDMI

HDMI Conn.

P.23

USB 3.0

USB2.0

Port 1,2
Port 0,1
Port 3,4
Port 2,3

USB2.0

BGA 989 Balls

PCI-E x1

Port 2

Mini Card-1
WLAN / BT4.0
Half
P.32

Express Card
P.28

3

Port 1

Ethernet
RTL8105E (10/100)
RTL8111F (10/100/1000)

Daughter board

Daughter board

Port 4

P.32

Daughter board

Port 8

USB 3.0 Conn. 1 P.33
USB 3.0 Conn. 2 -( USB Charger )
USB 3.0 Conn. 3
USB 3.0 Conn. 4

P.32

Digital Camera

P.22

Daughter board

( Half )

P.32

Card Reader
RTS5139

P.32

Finger Print

Daughter board
3 in 1 Socket
Daughter board

3

P.32

HD Audio

Daughter board

P.29

Mini Card-1 (WLAN)

Port 10

RJ45

34mm Slot

P.32

SATA ODD Conn.

Port 12
Port 3

P.29

2

LVDS Conn.

Port 11

FFS

P.29

Mini Card-2 (mSATA)

Port 5

LVDS

2

SATA HDD Conn.

Port 1

P13~20

RTC CKT.

SPI ROM
P.13

4MB

Power On/Off CKT.

P.13

2MB

LPC Bus

P.13

ENE KBC
KB9012 /
KB930 page

DC/DC Interface CKT.
P.27

Headphone Jack

Audio Codec
CX20672

33MHz

SPI

SPI ROM

P.25

Digital Mic.

SPI

P.30

Mic. Jack

SPI

Amplifier
TPA3113D2

24

P.31

Int. Speaker R/L
only for Vostro 3560

PS/2
4

4

Int.KBD
page 25

Touch Pad
page 25

Dashboard
Button page
x3 32

SPI ROM
128K

page 26

reserved for KB930

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Block Diagram
Size

A

B

C

D

Document Number

Rev
1.0

LA-8241P
Date:

Wednesday, February 01, 2012
E

Sheet

2

of

56

A

B

C

D

E

Compal Confidential
Project Code : QCL00 / QCL20
File Name : LA-8241P
1

1

Led1

8 pin-Hot Bar LS-8241P

(Ins) LED/B
LS-8251P (Vos)

Led2
4 pin-Hot Bar

LS-8245P (Ins)
LS-8255P (Vos) SW1

Led1
SW1

LED/B

FFC

FFC

4 pin

8 pin

4 pin

LA-8241P M/B

Lid (Inspiron)

SW2

Led3
SW3

Lid (Vostro)

JFC
8 pin

JLVDS
40 pin

JPWR
2

Led2

80 pin
JBTB1

FFC

LS-8242P (Ins)
LS-8252P (Vos)

4 pin

IO/B

Touch Pad
L

JFP
6 pin
JTP

JCR2
4 pin

4 pin

Camera

TP Led (Ins)

LCD Panel

FFC

40 pin

4 pin
JLED
JEXP
26 pin

10 pin

R

(Vostro)
TP Led (Vos)

3

2

4 pin-Hot Bar

JCR1
4 pin

3

Card Reader/B
26

LS-8243P (Ins)
LS-8253P (Vos)

1

(Vostro)

Wire

(Inspiron)

FFC
10 pin

LS-8244P (Ins)
LS-8254P (Vos) LED/B
Express Card
10 pin-Hot Bar
Led1

Led2

Led3

4 pin-Hot Bar
Led4

Finger Print/B
LS-8256P (Vos)

Top Side
Bottom Side

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

4

2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Block Diagram
Document Number

Rev
1.0

Wednesday, February 01, 2012

Sheet
E

3

of

56

A

Board ID Table for AD channel
Vcc
Ra
Board ID

0
1
2
3
4
5
6
7

3.3V +/100K +/Rb
0
8.2K +/18K +/33K +/56K +/100K +/200K +/NC

5%
5%

5%
5%
5%
5%
5%
5%

USB PORT#

BOARD ID Table
V AD_BID min
0 V
0.168 V
0.375 V
0.634 V
0.958 V
1.372 V
1.851 V
2.433 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0.155 V
0.362 V
0.621 V
0.945 V
1.359 V
1.838 V
2.420 V
3.300 V

Board ID
0
1
2
3
4
5
6
7

EC AD3
0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

PCB Revision
0.1
0.1
0.2
0.2
0.3
0.2
0.3
0.3
1.0
1.0
1.0
QCL00

QCL20

PCH

QCL01

SMBUS Control Table
SOURCE
EC_SMB_CK1
EC_SMB_DA1

KB9012

EC_SMB_CK2
EC_SMB_DA2

KB9012

PCH_SML0CLK
PCH_SML0DATA

PCH

PCH_SML1CLK
PCH_SML1DATA

PCH

MEM_SMBCLK
MEM_SMBDATA

PCH

CLKOUT

MINI1

MINI2

BATT

SODIMM

Express
Card

Thermal
Sensor

FFS

VGA Thermal
VGA
Sensor

XDP

V

Charger

V
V

V
Link

V

V

V

V

V

V

DESTINATION

DESTINATION

0

USB conn.1

1

USB conn.2 - Power Share

2

USB conn.3

3

USB conn.4

4

MINI CARD-1 (WLAN)

5

NC

6

NC

7

NC

8

Finger Print

9

NC

10

Card Reader

11

Express Card

12

Camera

13

NC

1

1

PCI0

PCH_LOOPBACK

PCI1

EC LPC

PCI2

None

PCI3

None

PCI4

None

DIFFERENTIAL

CLK

DESTINATION

FLEX CLOCKS

SATA

DESTINATION

PCI EXPRESS

DESTINATION

SATA0

HDD

Lane 1

10/100/1G LAN

SATA1

SSD

Lane 2

MINI CARD-1 (WLAN)

SATA2

ODD

Lane 3

Express Card

SATA3

None

Lane 4

None

SATA4

None

Lane 5

None

SATA5

None

Lane 6

None

Lane 7

None

Lane 8

None

DESTINATION

CLKOUT_PCIE0

10/100/1G LAN

CLKOUTFLEX0

None

CLKOUT_PCIE1

MINI CARD-1 WLAN

CLKOUTFLEX1

None

CLKOUT_PCIE2

Express Card

CLKOUTFLEX2

None

CLKOUT_PCIE3

None

CLKOUTFLEX3

None

CLKOUT_PCIE4

None

CLKOUT_PCIE5

None

CLKOUT_PCIE6

None

CLKOUT_PCIE7

None

Symbol Note :
: means Digital Ground

: means Analog Ground

CLKOUT_PEG_B

None

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Notes List
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet

4

of

56

5

4

3

2

1

1

+VCCP

JCPU1A
D

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

B27
B25
A25
B24

<15>
<15>
<15>
<15>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

<15>
<15>
<15>
<15>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

<15>
<15>
<15>
<15>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<15> FDI_FSYNC0
<15> FDI_FSYNC1
<15> FDI_INT
<15> FDI_LSYNC0
<15> FDI_LSYNC1

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI_FSYNC0
FDI_FSYNC1

J18
J17

FDI_INT

H20

FDI_LSYNC0
FDI_LSYNC1

J19
H17

FDI0_FSYNC
FDI1_FSYNC

DMI

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

FDI_INT
FDI0_LSYNC
FDI1_LSYNC

+VCCP
+EDP_COM
2
24.9_0402_1%
1
10K_0402_5%

@

A18
A17
B16
C15
D15

B

C17
F16
C16
G15
C18
E16
D16
F15

eDP_COMPIO
eDP_ICOMPO
eDP_HPD
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP

1
RC36
2
RC158

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

Intel(R) FDI

C

<15>
<15>
<15>
<15>

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms

JCPU1I

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

2

RC2
24.9_0402_1%

PEG_COMP

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

CC9
CC10
CC11
CC12
CC13
CC14
CC15
CC16

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K

PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

CC25
CC26
CC27
CC28
CC29
CC30
CC31
CC32

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

D

C

B

Sandy Bridge_rPGA_Rev1p0
CONN@

Sandy Bridge_rPGA_Rev1p0
CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-8241P
Sheet

Wednesday, February 01, 2012
1

5

of

56

5

4

3

2

<15,24> PCH_PWROK

JXDP1

1
1

@
@

2 RC22 H_CPUPWRGD_XDP
2 RC23 CFD_PWRBTN#_XDP

1K_0402_5%
0_0402_1%

1
1

@
@

2 RC24 XDP_HOOK2
2 RC26 SYS_PWROK_XDP

<11,12,14,28,29,32> PCH_SMBDATA
<11,12,14,28,29,32> PCH_SMBCLK
1
<13> PCH_JTAG_TCK
0_0402_5%

@

2

1
2

1

RC8
CRB 1.1K
CHECK LIST 0.7 --> 4.75K
RC19
INTEL recommand 1.1K
39_0402_1%
PDG 0.71 rev -->200

2
200_0402_1%
@

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>

XDP_RST#_R
XDP_DBRESET#

@
1
RC25

XDP_TDO
RC28 1
XDP_TRST#_R
XDP_TDI
RC31 1
XDP_TMS_R RC29 1

SAMTE_BSH-030-01-L-D-A
CONN@

PLT_RST#

2
1K_0402_5%

@
@
@

PCH_JTAG_TDO <13>

2 0_0402_5%
2 0_0402_5%

D

S

RUN_ON_CPU1.5VS3# 2
G

<10,27> RUN_ON_CPU1.5VS3#

2 0_0402_5%

@

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

QC1
SSM3K7002F_SC59-3

+3VALW
+VCCP

2

2

1

2

1

CC36
0.1U_0402_16V7K

1

@
RC27
1K_0402_5%

CC35
0.1U_0402_16V7K

1

+3VALW

C

D

VDDPWRGOOD

74AHC1G09GW TSSOP 5P

2

CC34
0.1U_0402_16V7K

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

2 RC30 XDP_TCK1
XDP_TCK_R

5
4

+VCCP

UC2

SYS_PWROK_XDP

1
2
3

<16,24,28,32> PLT_RST#

Place near JXDP1

RC32
75_0402_5%

NC VCC
A
GND
Y

C

5
4

RC33
1
2 BUF_CPU_RST#
43_0402_1%

BUFO_CPU_RST#

1
JCPU1B

SKTOCC#

+VCCP

T1

@

H_CATERR#

AL33

CATERR#

AN33

PECI

DPLL_REF_CLK
DPLL_REF_CLK#

A28
A27

CLK_CPU_DMI_R
CLK_CPU_DMI#_R

RC37 1
RC38 1

A16
A15

CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

RC39 1
RC40 1

@
@

2 0_0402_1%
2 0_0402_1%

@
RC34
0_0402_5%

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

2 1K_0402_1%
2 1K_0402_1%

PU/PD for JTAG signals

+VCCP

+VCCP

Remove DPLL Ref clock (for eDP only)

RC41
1
2 H_PROCHOT#_R
56_0402_1%

<24,44> H_PROCHOT#

AL32

PROCHOT#

B

H_THERMTRIP#

<17> H_THERMTRIP#

AN32

SM_DRAMRST#

DDR3
MISC

<17,24> H_PECI

1

RC43
62_0402_5%

THERMAL

2

PAD~D

BCLK
BCLK#

CLOCKS

AN34

PROC_SELECT#

MISC

C26

<17> H_SNB_IVB#

2

CC63
0.1U_0402_16V7K

SN74LVC1G07DCKR_SC70-5~D

1

<8>
CFG0
<15,50> VGATE

1K_0402_5%
0_0402_5%

B
VCC
A
GND
Y

RC8
200_0402_1%

2

H_CPUPWRGD
<15,24> PBTN_OUT#

1

+3V_PCH

2
UC1

+1.5V_CPU_VDDQ

2

XDP_BPM#6
XDP_BPM#7

RC4

1

1

XDP_BPM#4
XDP_BPM#5

1
@
2D_PWG 2
0_0402_1%
3

1
RC11

<15> PM_DRAM_PWRGD

@
RC6
10K_0402_5%

2

1 RC13 CFG10_R
1 RC15 CFG11_R

@

2

@
@

2
2

RC127
0_0402_1%
@

1

0_0402_5%
0_0402_5%

CFG10
CFG11

+3V_PCH
+3VS
RC128

<15> SYS_PWROK

1

<8>
<8>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

XDP_BPM#2
XDP_BPM#3

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

0_0402_5%
1
2

XDP_BPM#0
XDP_BPM#1

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

CC33
0.1U_0402_16V7K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

XDP_PREQ#_R
XDP_PRDY#_R

D

1

+VCCP

3

+VCCP

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AM34

<17> H_CPUPWRGD

1

@
RC53 2 H_CPUPWRGD_R
0_0402_1%

AP33

RC57
VDDPWRGOOD 1
2 VDDPWRGOOD_R
130_0402_1%~D

BUF_CPU_RST#

V8

AR33

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

TCK
TMS
TRST#
TDI
TDO

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

CC64
A

1
@

2

H_CPUPWRGD_R
Sandy Bridge_rPGA_Rev1p0
CONN@

10P_0402_50V8J

H_DRAMRST#

H_DRAMRST# <7>

SM_RCOMP0 140_0402_1%1
SM_RCOMP1 25.5_0402_1%1
SM_RCOMP2 200_0402_1%1

2 RC55
2 RC58
2 RC60

DDR3 Compensation Signals

JTAG & BPM

@
H_PM_SYNC_R
RC49 2
0_0402_1%

PWR MANAGEMENT

1

AK1
A5
A4

THERMTRIP#

PRDY#
PREQ#

<15> H_PM_SYNC

R8

XDP_PRDY# RC1211
XDP_PREQ# RC1221

@
@

2 0_0402_5%
2 0_0402_5%

XDP_PRDY#_R
XDP_PREQ#_R

AR26
AR27
AP30

XDP_TCK
RC1231
XDP_TMS
RC1241
XDP_TRST# RC1251

@
@
@

2 0_0402_1%
2 0_0402_1%
2 0_0402_1%

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

AR28
AP26

XDP_TDI_R
XDP_TDO_R

AL35 XDP_DBRESET#_R
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

1

XDP_DBRESET#
@
2 0_0402_1%
RC56

RC59
RC61
RC62
RC63
RC64
RC65
RC66
RC67

1
1
1
1
1
1
1
1

@
@
@
@
@
@
@
@

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

RC68
RC69
RC70
RC71

1
1
1
1

@
@
@
@

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

CFG12
CFG13
CFG14
CFG15

3

XDP_TDO

51_0402_5% 1

2 RC48

2 RC46
@

2 RC47

51_0402_5% 1

2 RC52

XDP_TRST#_R 51_0402_5% 1

2 RC54

XDP_DBRESET# 1K_0402_5% 1

2 RC42

H_CPUPWRGD_R 10K_0402_5%1

2 RC44

B

<8>
<8>
<8>
<8>

A

Compal Electronics, Inc.
2013/01/16

Deciphered Date

Title

Date:

4

51_0402_5% 1

XDP_DBRESET# <15>

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

XDP_PREQ#

2 RC45

+3VS

Compal Secret Data
2012/01/17

51_0402_5% 1

2 0_0402_1% XDP_TDI
2 0_0402_1% XDP_TDO

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

Security Classification
Issued Date

@
@

51_0402_5% 1

XDP_TDI_R

XDP_TCK_R

AP29
AP27

RC50 1
RC51 1

XDP_TMS_R

2

PROCESSOR(2/6) PM,XDP,CLK
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

6

of

56

5

4

3

2

1

JCPU1C
JCPU1D

C

B

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10
V6

<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2

AE8
AD9
AF9

<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

DDR SYSTEM MEMORY A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AA5
AB5
V10

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

AB4
AA4
W9

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

AH3
AG3
AG2
AH2

M_ODT0
M_ODT1

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

M_CLK_DDR0 <11>
M_CLK_DDR#0 <11>
DDR_CKE0_DIMMA <11>

<12> DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

<11>
<11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

<11>

<11>

<11>

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7
R6

<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2

AA10
AB8
AB9

<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_WE#

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

DDR SYSTEM MEMORY B

<11> DDR_A_D[0..63]
D

AB6
AA6
V9

AE2
AD2
R9

M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB

AE1
AD1
R10

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

AB2
AA2
T9

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

AD3
AE3
AD6
AE6

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

AE4
AD4
AD5
AE5

M_ODT2
M_ODT3

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M_CLK_DDR2 <12>
M_CLK_DDR#2 <12>
DDR_CKE2_DIMMB <12>

D

M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

<12>
<12>

M_ODT2 <12>
M_ODT3 <12>
C

DDR_B_DQS#[0..7]

<12>

DDR_B_DQS[0..7]

<12>

DDR_B_MA[0..15]

<12>

B

Sandy Bridge_rPGA_Rev1p0
CONN@
Sandy Bridge_rPGA_Rev1p0
CONN@

1

+1.5V

@
1
2
RC74
0_0402_5%
QC2

D

S

H_DRAMRST#

<6> H_DRAMRST#

3

1

RC75
1K_0402_5%

2

BSS138_SOT23
DDR3_DRAMRST#_R

1
RC76

2
1K_0402_5%

DDR3_DRAMRST#

<11,12>

2

1

G

RC77
4.99K_0402_1%

1
RC72

A

2

@
2
0_0402_1%

DRAMRST_CNTRL_PCH

<14>
A

DRAMRST_CNTRL

DRAMRST_CNTRL

<11>

1

2

CC37
.047U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PROCESSOR(3/6) DDRIII
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

7

of

56

5

4

3

2

1

CFG Straps for Processor
D

D

1

CFG2

2

@

PAD~D
PAD~D

T87
T88

@
@

<6>
<6>
<6>
<6>
<6>
<6>
PAD~D
PAD~D

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
T89
@
T90
@

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

@ T7
@ T8
@ T9

PAD~D
PAD~D
PAD~D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

RSVD37
RSVD38
RSVD39
RSVD40

T8
J16
H16
G16

@ T10
@ T11
@ T12
@ T13

PAD~D
PAD~D
PAD~D
PAD~D

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AR35
AT34
AT33
AP35
AR34

@ T14
@ T15
@ T16
@ T17
@ T18

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

1:(Default) Normal Operation; Lane #
definition matches socket pin map definition

*0:Lane Reversed
CFG4
@ RC81
1K_0402_1%

VSS_VAL_SENSE

C

PAD~D

+SA_DIMM_VREFDQ

T19 @

AJ31
AH31
AJ33
AH33

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

AJ26

RSVD5

B4
D1

RSVD6
RSVD7

+SB_DIMM_VREFDQ

@
RC84
1K_0402_1%

1

1

+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ

@

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

2

2

RC85
1K_0402_1%

RC159
+3VS

2

1
10K_0402_5%

B

T25
T26
T27
T28
T30
T32
T33
T34
T35
T37
T38
T39
T40
T41
T42
T43

@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

PAD~D T44 @
PAD~D T45 @
H_VCCP_SEL

J20
B18
A19

PAD~D

J15

T49 @

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
VCCIO_SEL

2

C

Display Port Presence Strap
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

B34
A33
A34
B35
C35

@ T20
@ T21
@ T22
@ T23
@ T24

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

AJ32
AK32

@ T29
@ T31

PAD~D
PAD~D

AH27

@ T36

PAD~D

CFG4

* 1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6
CFG5

VCC_DIE_SENSE

1

VSS_AXG_VAL_SENSE
VCC_VAL_SENSE

RC87
1K_0402_1%

RSVD54
RSVD55

AN35
AM35

RSVD56
RSVD57
RSVD58

AT2
AT1
AR1

@ T46
@ T47
@ T48

PAD~D
PAD~D
PAD~D

B1

@ T50

PAD~D

CLK_RES_ITP <14>
CLK_RES_ITP# <14>

@ RC86
1K_0402_1%

2

1

VCC_AXG_VAL_SENSE

RESERVED

1

@
RC80
50_0402_1%

T86

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

1

@
RC79
50_0402_1%

PAD~D

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

1

2

+VCC_CORE

CFG0
T85
@

@ T2
@ T3
@ T4
@ T5
@ T6

2

+VCC_GFXCORE_AXG

<6>
PAD~D

RC78
1K_0402_1%

L7
AG7
AE7
AK2
W8

2

JCPU1E

PCIE Port Bifurcation Straps
B

RSVD27

11: (Default) x16 - Device 1 functions 1 and 2 disabled
KEY

CFG[6:5]

*10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Sandy Bridge_rPGA_Rev1p0
CONN@

1

CFG7

2

@ RC89
1K_0402_1%

VSS_AXG_VAL_SENSE

A

2

PEG DEFER TRAINING

@
RC91
50_0402_1%

CFG7

*1: (Default) PEG Train immediately
following xxRESETB de assertion

0: PEG Wait for BIOS for training

1

1

@
RC90
50_0402_1%

2

VSS_VAL_SENSE

INTEL 12/28 recommand
to add RC120, RC121, RC122, RC123
Please place as close as JCPU1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

A

2

PROCESSOR(4/6) RSVD,CFG
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

8

of

56

4

3

PEG AND DDR

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

VCCIO40

J23

D

C

1

1

+VCCP

RC95

RC93
75_0402_5%

2
VIDALERT#
VIDSCLK
VIDSOUT

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

Place the PU
resistors close to CPU

2

RC95 close to CPU

130_0402_1%~D

RC94 1
RC92 1
RC96 1

@
@

2 43_0402_1%
2 0_0402_1%
2 0_0402_1%

VR_SVID_ALRT# <50>
VR_SVID_CLK <50>
VR_SVID_DAT <50>

B

1

+VCC_CORE

AJ35 VCCSENSE_R
AJ34 VSSSENSE_R

RC98 1
RC99 1

@
@

2 0_0402_1%
2 0_0402_1%

VCCSENSE <50>
VSSSENSE <50>

1

VCC_SENSE
VSS_SENSE

2

RC97
100_0402_1%

VCCIO_SENSE
VSSIO_SENSE

+VCCP

B10
A10

RC100
100_0402_1%

1

RC108

2
1
10_0402_1%

RC111
10_0402_1%

VCCIO_SENSE

<47>

2

B

8.5A

SVID

C

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

+VCCP

SENSE LINES

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

1

POWER

QC=94A
DC=53A

+VCC_CORE

D

2

2

JCPU1F

CORE SUPPLY

5

A

A

Sandy Bridge_rPGA_Rev1p0
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PROCESSOR(5/6) PWR,BYPASS
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

9

of

56

5

4

3

2

1

+1.5V_CPU_VDDQ Source
QC3
AO4728L_SO8~D

RC105
330K_0402_1%

QC5B
RUN_ON_CPU1.5VS3#

D

5

6

2

4

2N7002DW-7-F_SOT363-6

QC5A
2N7002DW-7-F_SOT363-6

@ RC104
1
2
0_0402_5%
RC107
1
2
0_0402_5%

1
2

JCPU1H

2
+VCC_GFXCORE_AXG
RUN_ON_CPU1.5VS3#

RC113

@
CC40
0.1U_0402_10V7K~D

1

2
10_0402_1%

VCC_AXG_SENSE

1K_0402_5%
RC112
2

AL1

+V_SM_VREF_CNT

3

+V_SM_VREF

1
@

1

SENSE
LINES
VREF

SM_VREF

QC4
2 NTR4503NT1G_SOT23-3~D
RUN_ON_CPU1.5VS3

2

1K_0402_5%
RC116

@

5A
+1.5V_CPU_VDDQ
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

@
JP10
1

1

2

1

2

1

2

1

2

1

2

1

2

CC46
10U_0805_4VAM~D

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

2

+1.5V

PAD-OPEN 4x4m

J8 OPEN

1
+

CC47
330U_D2_2VM_R6M~D

2

+VCCSA

VCCSA_SENSE

FC_C22
VCCSA_VID1

M27
M26
L26
J26
J25
J24
H26
H25

6A

2

1

2

1

2

1

2

@

1
+

CC48
330U_D2_2VM_R6M~D

2

H23

C22
C24

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

VSS

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

D

C

B

Sandy Bridge_rPGA_Rev1p0
CONN@

VCCSA_SENSE <49>

+1.5V_CPU_VDDQ

VCCSA_VID0 <49>
VCCSA_VID1 <49>
1

MISC

1.8V RAIL

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

1

CC52
10U_0603_6.3V6M

@ RC110
0_0402_5%

Sandy Bridge_rPGA_Rev1p0
CONN@
2

2

@

2
0_0402_5%

CC45
10U_0805_4VAM~D

+

1
@ RC106

+V_SM_VREF should
have 10 mil trace width

CC51
10U_0805_4VAM~D

1

VCCPLL1
VCCPLL2
VCCPLL3

2
1K_0402_5%

CC44
10U_0805_4VAM~D

2

B6
A6
A2

@

+1.5V
1
RC129

CC50
10U_0805_4VAM~D

1

CC57
330U_D2_2.5VM_R6M~D

2

@

CC62
10U_0805_4VAM~D

2

1

CC61
10U_0805_4VAM~D

2

1

CC56
1U_0402_6.3V6K

1

CC55
1U_0402_6.3V6K

2

CC54
10U_0805_4VAM~D

1

+1.5V_CPU_VDDQ
2

10_0402_1%

CC43
10U_0805_4VAM~D

+1.8VS_VCCPLL

2 0_0805_1%

1

CC49
10U_0805_4VAM~D

@

VSS_AXG_SENSE <50>

RC114

AK35
AK34

CC42
10U_0805_4VAM~D

1.2A
1

VSS_AXG_SENSE

VAXG_SENSE
VSSAXG_SENSE

1K_0402_5%

B

+1.8VS

@

RC126

DDR3 -1.5V RAILS

C

VCC_AXG_SENSE <50>
2 100_0402_1%

1

CC41
10U_0805_4VAM~D

AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

POWER

SA RAIL

33A AT24

GRAPHICS

+VCC_GFXCORE_AXG JCPU1G

RC157

1

2

<6,27>

1

1

RC109

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

2

<24> CPU1.5V_S3_GATE

2

1

1

<24,27,28,46,47,48> SUSP#

1

CC39
0.1U_0603_50V_X7R

1

RUN_ON_CPU1.5VS3

3

2

2

4

RC101
100K_0402_5%

RC102
100K_0402_5%

+1.5V_CPU_VDDQ
1
2
3

CC38
10U_0805_10V6K

1

1

8
7
6
5

2

B+_BIAS

RC103
20K_0402_5%

+1.5V
+3VALW

+1.5V

CC53

2

1 0.1U_0402_10V7K~D

CC58

2

1 0.1U_0402_10V7K~D

CC59

2

1 0.1U_0402_10V7K~D

CC60

2

1 0.1U_0402_10V7K~D

add CC181 , CC182, 4 caps are all pop.
follow checklist 1.0 5/24

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

PROCESSOR(6/6) PWR,VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-8241P

Date:

5

4

3

2

Wednesday, February 01, 2012
1

Sheet

10

of

56

5

4

3

2

+1.5V

1

+1.5V
JDIMM1

D

DDR_A_DQS#1
DDR_A_DQS1

2

RD3
1K_0402_1%

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

+1.5V
DDR_A_D26
DDR_A_D27

1

CD6

2

1U_0402_6.3V6K

2

1

CD5

1U_0402_6.3V6K

1

CD4

CD3

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

DDR_CKE0_DIMMA

<7> DDR_CKE0_DIMMA

2
<7> DDR_A_BS2

C

+1.5V

1

2

1
+
2

CD14
330U_SX_2VY~D

2

@
CD13

2

1

10U_0603_6.3V6M
CD12

2

1

10U_0603_6.3V6M
CD11

2

1

10U_0603_6.3V6M
CD10

2

1

10U_0603_6.3V6M
CD9

1

10U_0603_6.3V6M
CD8

2

10U_0603_6.3V6M
CD7

10U_0603_6.3V6M

1

<7> M_CLK_DDR0
<7> M_CLK_DDR#0
<7> DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
<7> DDR_CS1_DIMMA#

DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <7>

DDR_A_MA15
DDR_A_MA14
C

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

+1.5V

DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_ODT1

RD4
1K_0402_1%

<7>
+VREF_CA

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

1

2

RD5
1K_0402_1%

1

2

DDR_A_D44
DDR_A_D45

B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
@ RD8

M3

DDR_A_D54
DDR_A_D55

2 0_0402_5%

1

QD1
1 BSS138_NL_SOT23-3

3

+SA_DIMM_VREFDQ

DDR_A_D60
DDR_A_D61

+V_DDR_REFA

DDR_A_DQS#7
DDR_A_DQS7

<7> DRAMRST_CNTRL

DRAMRST_CNTRL

DDR_A_D62
DDR_A_D63
@ RD9
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <6,12,14,28,29,32>
PCH_SMBCLK <6,12,14,28,29,32>

2 0_0402_5%

1

+0.75VS

QD2
1 BSS138_NL_SOT23-3

D

3

+SB_DIMM_VREFDQ

+V_DDR_REFB

G

G2

G1

DDR_A_D28
DDR_A_D29

D

2

206

DDR_A_D22
DDR_A_D23

S

1

DDR_A_D20
DDR_A_D21

G

2

CD21

A

1

CD22
2.2U_0603_6.3V6K

0.1U_0402_16V7K

+3VS

DDR_A_D14
DDR_A_D15

S

2

DDR3_DRAMRST# <7,12>

CD16

2

1

CD20
1U_0402_6.3V6K

2

1

CD19
1U_0402_6.3V6K

1

CD18
1U_0402_6.3V6K

2

CD17
1U_0402_6.3V6K

1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

D

DDR3_DRAMRST#

CD15

+0.75VS

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_D12
DDR_A_D13

0.1U_0402_16V7K

B

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D6
DDR_A_D7

2.2U_0603_6.3V6K

Layout Note:
Place near JDIMM1.203,204

73
75
77
DDR_A_BS2
79
81
DDR_A_MA12
83
DDR_A_MA9
85
87
DDR_A_MA8
89
DDR_A_MA5
91
93
DDR_A_MA3
95
DDR_A_MA1
97
99
M_CLK_DDR0
101
M_CLK_DDR#0
103
105
DDR_A_MA10
107
DDR_A_BS0
109
111
DDR_A_WE#
113
DDR_A_CAS#
115
117
DDR_A_MA13
119
DDR_CS1_DIMMA#
121
123
125
127
DDR_A_D32
129
DDR_A_D33
131
133
DDR_A_DQS#4
135
DDR_A_DQS4
137
139
DDR_A_D34
141
DDR_A_D35
143
145
DDR_A_D40
147
DDR_A_D41
149
151
153
155
DDR_A_D42
157
DDR_A_D43
159
161
DDR_A_D48
163
DDR_A_D49
165
167
DDR_A_DQS#6
169
DDR_A_DQS6
171
173
DDR_A_D50
175
DDR_A_D51
177
179
DDR_A_D56
181
DDR_A_D57
183
185
187
189
DDR_A_D58
191
DDR_A_D59
193
195
1
2
197
RD6 10K_0402_5% 199
1
2
201
RD7 10K_0402_5% 203
+0.75VS
205

DDR_A_DQS#0
DDR_A_DQS0

2

1

DDR_A_D8
DDR_A_D9

DDR_A_D4
DDR_A_D5

2

2

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

2

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

1
2

+V_DDR_REFA

DDR_A_D0
DDR_A_D1
CD2

<7> DDR_A_MA[0..15]

CD1

RD1
1K_0402_1%

<7> DDR_A_D[0..63]

0.1U_0402_16V7K

2.2U_0603_6.3V6K

<7> DDR_A_DQS[0..7]

+V_DDR_REFA

+V_DDR_REFA

+1.5V

2

<7> DDR_A_DQS#[0..7]

BELLW_80001-5021
CONN@

A

DRAMRST_CNTRL

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

DDRIII DIMMA
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

11

of

56

4

3

2

+1.5V

1
<7> DDR_B_DQS#[0..7]
1

<7> DDR_B_D[0..63]

DDR_B_DQS#1
DDR_B_DQS1

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

RD16
1K_0402_1%
2

<7> DDR_B_MA[0..15]

DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19

All VREF traces should
have 10 mil trace width

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

Layout Note:
Place near JDIMMB

DDR_CKE2_DIMMB

<7> DDR_CKE2_DIMMB

DDR_B_BS2

<7> DDR_B_BS2
+1.5V

DDR_B_MA12
DDR_B_MA9

C

1

CD31

2

1U_0402_6.3V6K

2

1

CD30

CD29

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CD28

1U_0402_6.3V6K

1

DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

2

M_CLK_DDR2
M_CLK_DDR#2

<7> M_CLK_DDR2
<7> M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

<7> DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

<7> DDR_B_WE#
<7> DDR_B_CAS#

+1.5V

DDR_B_MA13
DDR_CS3_DIMMB#

<7> DDR_CS3_DIMMB#

DDR_B_D40
DDR_B_D41

B

DDR_B_D42
DDR_B_D43

Layout Note:
Place near JDIMMB.203,204

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

+0.75VS

2

1

+0.75VS
1

CD47

2

CD46

1

2.2U_0603_6.3V6K

0.1U_0402_16V7K

A

+3VS

RD20
10K_0402_5%

RD19
10K_0402_5%

1

2

+3VS

2

2

1

CD45
1U_0402_6.3V6K

2

1

CD44
1U_0402_6.3V6K

1

CD43
1U_0402_6.3V6K

2

CD42
1U_0402_6.3V6K

1

DDR_B_D58
DDR_B_D59

205
207

2

GND2
BOSS2

DDR_B_D12
DDR_B_D13
D

DDR3_DRAMRST#

DDR3_DRAMRST# <7,11>

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7

C

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB#
M_ODT2
M_ODT3

2012/01/17

M_ODT3

+VREF_CB
DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

1

2

3

RD18
1K_0402_1%

1

2

DDR_B_D44
DDR_B_D45
B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <6,11,14,28,29,32>
PCH_SMBCLK <6,11,14,28,29,32>

+0.75VS

206
208
A

BELLW_80001-1021
CONN@

Compal Electronics, Inc.
2013/01/16

Deciphered Date

Title

Date:

4

RD17
1K_0402_1%

<7>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+1.5V

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

Compal Secret Data

Security Classification
Issued Date

GND1
BOSS1

DDR_B_D6
DDR_B_D7

CD41

DDR_B_D34
DDR_B_D35

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_DQS#0
DDR_B_DQS0

CD40

DDR_B_DQS#4
DDR_B_DQS4

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_B_D4
DDR_B_D5

0.1U_0402_16V7K

+
2

DDR_B_D32
DDR_B_D33

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2.2U_0603_6.3V6K

2

1

CD39
330U_SX_2VY~D

2

@
1

CD38

2

1

10U_0603_6.3V6M
CD37

2

1

10U_0603_6.3V6M
CD36

2

1

10U_0603_6.3V6M
CD35

2

1

10U_0603_6.3V6M
CD34

1

10U_0603_6.3V6M
CD33

2

10U_0603_6.3V6M
CD32

10U_0603_6.3V6M

1

@

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

1

2

DDR_B_D2
DDR_B_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

2

1
CD26

2

CD27

2

1

0.1U_0402_16V7K

2.2U_0603_6.3V6K

RD15
1K_0402_1%
+V_DDR_REFB

DDR_B_D0
DDR_B_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

+V_DDR_REFB

+V_DDR_REFB

DDR_B_D8
DDR_B_D9

<7> DDR_B_DQS[0..7]

+1.5V
JDIMM2

+1.5V

D

1

2

5

2

DDRIII DIMMB
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

12

of

56

5

4

3

2

1

+3VS

PCH_RTCX1

1
1

PCH_RTCX2

2
10M_0402_5%
YH1
2

32.768KHZ_12.5PF_9H03200019
18P_0402_50V8J

D

<31> PCH_RTCX1_R

RH30

1

CH3

2

2

CH1

PCH_RTCX1
2
0_0402_5%

1

1

HDA_SDOUT
10P_0402_50V8J
PCH_INTVRMEN RH13

2

PCH_INTVRMEN RH16

2

@

2

CH2

GCLK@

1

+RTCVCC

@

close to YH1

1

HDA_BIT_CLK
10P_0402_50V8J

UH1

@

* LH：
：Integrated
Integrated

330K_0402_5%
1
@

SERIRQ

RH10

2

1 10K_0402_5%

HDD_DET#

RH12

2

1 10K_0402_5%

PCH_SATALED#RH14

2

1 10K_0402_5%

HDA_SPKR RH17

2

1
+3VS

330K_0402_5%

INTVRMEN

CH4
18P_0402_50V8J

+RTCVCC

2

Reserve for RF please close to UH1
RH2

1

SM_INTRUDER#

2
1M_0402_5%

VRM enable
VRM disable

HDA_SPKR

T10

HDA_RST#

K34

HDA_SDIN0

E34

HDA_SYNC

QH1 BSS138_SOT23
@
1
2
RH9
0_0402_5%

G34
C34

C

<24>

ME_EN

RH11

1

HDA_SDOUT
2
1K_0402_1%

1

HDA_SDOUT
2
33_0402_5%

A34
HDA_SDOUT

<30> HDA_SDOUT_AUDIO

RH15

A36
C36
N32

+3V_PCH

@ RH19
200_0402_5%

@ RH20
200_0402_5%

<6> PCH_JTAG_TDI

2

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

LPC

HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TCK
JTAG_TMS
JTAG_TDI

SATAICOMPO
SATAICOMPI

JTAG_TDO
SATA3RCOMPO

PCH_JTAG_TDI

SATA3COMPI
RH26
100_0402_1%

2

RH25
100_0402_1%

2

2

RH24
100_0402_1%

J3

PCH_JTAG_TMS

HDA_BCLK

1

2

PCH_JTAG_TMS

1

1

2

<6> PCH_JTAG_TDO
PCH_JTAG_TDO

PCH_JTAG_TCK

SERIRQ

PCH_SPI_CLK

T3

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#

T1

PCH_SPI_SI

V4

PCH_SPI_SO

U3

SPI_CLK

SATA3RBIAS

LPC_FRAME#

LPC_FRAME#

+3V_PCH

ME debug mode , this signal has a weak internal PD

<24>
<24>
<24>
<24>

HDA_SDOUT RH23

L=>security measures defined in the Flash
Descriptor will be in effect (default)

<24>

2

SATALED#

SPI_MOSI

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

1 1K_0402_5%

= Disabled
*Low
High = Enabled

H=>Flash Descriptor Security will be overridden

SERIRQ

V5

SERIRQ

AM3
AM1
AP7 SATA_PTX_DRX_N0 CH7
AP5 SATA_PTX_DRX_P0 CH8

<24>

HDA_SYNC

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_DTX_N0 <29>
SATA_PRX_DTX_P0 <29>
SATA_PTX_DRX_N0_C <29>
SATA_PTX_DRX_P0_C <29>

HDD

AM10
AM8
AP11 SATA_PTX_DRX_N1 CH18 1
AP10 SATA_PTX_DRX_P1 CH17 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_DTX_N1 <32>
SATA_PRX_DTX_P1 <32>
SATA_PTX_DRX_N1_C <32>
SATA_PTX_DRX_P1_C <32>

mSATA

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_DTX_N2 <29>
SATA_PRX_DTX_P2 <29>
SATA_PTX_DRX_N2_C <29>
SATA_PTX_DRX_P2_C <29>

ODD

AD7
AD5
AH5 SATA_PTX_DRX_N2 CH9 1
AH4 SATA_PTX_DRX_P2 CH10 1

This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
+3V_PCH

HDA_SYNC

RH32

1 1K_0402_5%

2

AB8
AB10
AF3
AF1

C

RTC Battery

Y7
Y5
AD3
AD1

+RTCBATT

Y3
Y1
AB3
AB1

SATA_COMP

1
RH21

2
37.4_0402_1%

W=20mils

+1.05VS_SATA3

AB12
AB13

SATA3_COMP
1
RH22

AH1

RBIAS_SATA3
1
RH28

P3

PCH_SATALED#

V14

HDD_DET#_R

P1

BBS_BIT0_R

2

+CHGRTC

2

1

1

+3VLP

JUMP_43X39

2
750_0402_1%~D

+RTCVCC

PCH_SATALED# <32>
HDD_DET#

2 0_0402_5%
1 10K_0402_5%

2
RH29

W=20mils
DH1
BAT54CW_SOT323-3

JP12

2
49.9_0402_1%

RH268 1

RH34
1K_0402_5%

+CHGRTC

+1.05VS_VCC_SATA

Y11
Y10

W=20mils 1

SPI_CS1#

@

E36
K36

SPI_CS0#

SPI

@ RH18
200_0402_5%

<6> PCH_JTAG_TCK
<6> PCH_JTAG_TMS

1

1

+3V_PCH

1

+3V_PCH

LDRQ0#
LDRQ1# / GPIO23

INTVRMEN

D36

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

2

L34

INTRUDER#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1

N34

HDA_SYNC

FWH4 / LFRAME#
SRTCRST#

SATA 6G

2
1

HDA_BIT_CLK

RTCRST#

RTC

K22
C17

RTCX2

C38
A38
B37
C37

3

RH8

G22

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

1

2
1M_0402_5%

D20

PCH_SRTCRST#

1

<30> HDA_SPKR

3

<30> HDA_SDIN0

1

PCH_RTCRST#

HDA_SDO

RTCX1

SATA

RH7

HDA_SYNC_R
2
33_0402_5%

C20

IHDA

1

HDA_RST#
2
33_0402_5%

D

<30> HDA_SYNC_AUDIO

RH6

+5VS

S

1

PCH_RTCX2

SM_INTRUDER#
CLRP2
PCH_INTVRMEN
SHORT PADS
ME CMOS
CLP1 & CLP2 place near DIMM

2

G

<30> HDA_RST_AUDIO#

HDA_BIT_CLK
2
33_0402_5%

RH5

1

2

1

<30> HDA_BITCLK_AUDIO

2

A20

JTAG

CH6
1U_0603_10V6K

CMOS
CLRP1
SHORT PADS

PCH_RTCX1

2

CH5
1U_0603_10V6K
1
2
RH3 20K_0402_5%
1
2
RH4 20K_0402_5%

1

1

D

*HIGH=No

SA00005AG1L

UH1A
+RTCVCC

1 1K_0402_5%

LOW=Default
Reboot

BD82HM77 QPRG C1 BGA 989P PCH
SA00005AG1L

keep away hot spot

@

2

RH1

CH12
1U_0603_10V6K

2

HDD_DET# <29>

+3VS

BD82HM77 QPRG C1 BGA 989P PCH

B

B

+3V_PCH
+3V_PCH
+3V_PCH

2
51_0402_5%

SPI ROM FOR WIN8( 2MByte )

@
RH263
3.3K_0402_5%

@
PCH_SPI_CS0#
PCH_SPI_SO

UH2
PCH_SPI_CS1#
PCH_SPI_SO

1
RH38

2 PCH_SPI_WP#
3.3K_0402_5%

1
RH40

2 PCH_SPI_HOLD#
3.3K_0402_5%

1 RH36
2 RH37

2 0_0402_5%
1 33_0402_5%

SPI ROM FOR ME
( 4MByte )

CH98

UH6

1

1
RH35

2

2

2

2
+3V_PCH

1

PCH_JTAG_TCK

1

PCH_SPI_CS1#_R
PCH_SPI_SO_R
PCH_SPI_WP#

1
2
3
4

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

PCH_SPI_HOLD#
PCH_SPI_CLK_R
PCH_SPI_SI_R

2 RH27
2 RH39

133_0402_5%
133_0402_5%

1 RH264
2
RH265

2 0_0402_5%
1
33_0402_5%

PCH_SPI_CLK
PCH_SPI_SI

PCH_SPI_CS0#_R 1
PCH_SPI_SO_L 2
PCH_SPI_WP#
3
4

CS#
SO/SIO1
WP#
GND

VCC
HOLD#
SCLK
SI/SIO0

8
7
6
5

PCH_SPI_HOLD#
PCH_SPI_CLK_L
PCH_SPI_SI_L

1

2

0.1U_0402_16V7K

CH11
@
RH33
3.3K_0402_5%

RH262
3.3K_0402_5%

+3V_PCH

0.1U_0402_16V7K

+3V_PCH

1

NEC flash issue.

2 RH266
2
RH267

133_0402_5% PCH_SPI_CLK
PCH_SPI_SI
1
33_0402_5%

EN25Q32B-104HIP_SO8

EN25QH16-104HIP_SO8

EON EN25Q32B-104HIP_SO8

1
@

EON EN25QH16-104HIP_SO8

2

CH99
10P_0402_50V8J

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PCH (1/8) SATA,HDA,SPI, LPC
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

13

of

56

5

4

3

2

1

SMBCLK
UH1B

RH75 2
RH76 2
RH77 2

1 0_0402_5%
1 0_0402_5%
1 10K_0402_5%

PCIE_WLAN#
PCIE_WLAN

RH79
RH80
RH81

<28> CLK_PCIE_EXP#
<28> CLK_PCIE_EXP
+3VS
<28> EXPCLK_REQ#

1 0_0402_5%
1 0_0402_5%
1 10K_0402_5%

2
2
2

LAN_CLKREQ#

WLAN_CLKREQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#

PERN4
PERP4
PETN4
PETP4

BG37
BH37
AY36
BB36

PERN5
PERP5
PETN5
PETP5

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

Y40
Y39
J2
AB49
AB47
M1
AA48
AA47

SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

SML0CLK

G12

SML0DATA

SML1ALERT# / PCHHOT# / GPIO74

C13

PCH_HOT#

SML1CLK / GPIO58

E14

SML1CLK

SML1DATA / GPIO75

M16

SML1DATA

SMBDATA

SML0DATA
SML1CLK

MEMORY

SML1DATA
SMBALERT#

SML0ALERT# / GPIO60
SML0CLK
SML0DATA

DRAMRST_CNTRL_PCH

PCH_HOT#

CL_DATA1
CL_RST1#

P10

<24>

If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH

+3V_PCH

M10

PEG_A_CLKRQ#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

AB37
AB38

CLK_PEG_VGA#
CLK_PEG_VGA

CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

CLKOUT_DP_N
CLKOUT_DP_P

AM12
AM13

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

CLKIN_DMI#
CLKIN_DMI

CLKIN_GND1_N
CLKIN_GND1_P

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

CLKIN_DOT_96N
CLKIN_DOT_96P

G24
E24

CLKIN_DOT96#
CLKIN_DOT96

CLKIN_SATA_N
CLKIN_SATA_P

AK7
AK5

CLKIN_SATA#
CLKIN_SATA

REFCLK14IN

K45

CLK_PCH_14M

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

Y47

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

K43

CLK_FLEX0

CLKOUTFLEX1 / GPIO65

F47

CLK_14M_R

CLKOUTFLEX2 / GPIO66

H47

CLKOUTFLEX3 / GPIO67

K49

PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37
Y36

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PEG_A_CLKRQ#

<35>

+3VS

GPIO26

+3V_PCH

RH83 1

2 10K_0402_5%

GPIO44

+3V_PCH

RH84 1

2 10K_0402_5%

GPIO56

CLKOUT_PCIE4N
CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45
V46

B

L14

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

RH71
2.2K_0402_5%

AB42
AB40

RH88 1

+3V_PCH

2 10K_0402_5%

GPIO45

XTAL25_IN
2
1M_0402_5%

XTAL25_OUT

1
RH89

A

2
2

RH93
RH94

2
2

1 0_0402_5%
1 0_0402_5%

GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

YH2

OSC

@
@

CLKOUT_PCIE6N
CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

close to YH2
<31>

CLK_PCI_LPBACK

4

PCH_SMBDATA

PCH_X1

RH41

1

<6,11,12,28,29,32>

<16>

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

1
RH85

2
90.9_0402_1%

@

+1.05VS_VCCDIFFCLKN

PAD~D
PAD~D

+3V_PCH

SML1CLK
CLK_LAN_25M

<32>

1

6

@
RH63
2
33_0402_5%

1

PCH_SMLCLK

<24>

DMN66D0LDW-7_SOT363-6
QH3A

RH261
10K_0402_5%

SML1DATA

4

3

PCH_SMLDATA

<24>

DMN66D0LDW-7_SOT363-6
QH3B

close to RH270

@
CH25
1
2
22P_0402_50V8J~D

A

<31>

LAN_X1

RH31

CLK_LAN_25M
2
0_0402_5%

1

XTAL25_IN
2
0_0402_5%

GCLK@

GCLK@

@
RH65
CLK_PCI_LPBACK 2
33_0402_5%

@
CH26
1
1
2
22P_0402_50V8J~D

Issued Date

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Reserve for EMI please close to
UH1

5

3

QH2B
RH82
1 @
2
0_0402_5%

T53

DIS@

CLK_PCH_14M

<6,11,12,28,29,32>

DMN66D0LDW-7_SOT363-6

@ T54
1 RH125 2
22_0402_5%
CLK_LAN_25M_R
@ 1
2
RH270
22_0402_5%
DGPU_PRSNT#
2
1
+3VS
RH269
10K_0402_5%
UMA@

BD82HM77 QPRG C1 BGA 989P PCH

1 0_0402_5%
1 0_0402_5%

PCH_SMBCLK

1

2

<8> CLK_RES_ITP#
<8> CLK_RES_ITP

1

PEG_B_CLKRQ# / GPIO56

V40
V42

AK14
AK13

RH72
2.2K_0402_5%

B

PCIECLKRQ5# / GPIO44

3

CLK_CPU_ITP# RH91
CLK_CPU_ITP RH92

2 10K_0402_5%

4

GND

1
CH28

27P_0402_50V8J

2

27P_0402_50V8J

1

25MHZ_20PF_FSX3M-25.M20FDO
2
GND OSC

1

<6> CLK_CPU_ITP#
<6> CLK_CPU_ITP

CH27

RH90 1

+3V_PCH

E6

6

DMN66D0LDW-7_SOT363-6
QH2A
RH78
1 @
2
0_0402_5%
SMBDATA

CLKOUT_PCIE5N
CLKOUT_PCIE5P

+3VS

5

RH66 1

PCIECLKRQ3# / GPIO25

Y43
Y45

C

CLK_PEG_VGA# <34>
CLK_PEG_VGA <34>

2

+3V_PCH

A8

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2
2
2
2
2
2
2
2
2

2

2 10K_0402_5%

GPIO25

1
1
1
1
1
1
1
1
1

RH64
10K_0402_5%

FLEX CLOCKS

+3V_PCH

*PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2

1 10K_0402_5%

RH54
RH55
RH56
RH57
RH58
RH59
RH60
RH61
RH62

D

No support iAMT

SMBCLK

RH74 2

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

20090512
add double mosfet prevent
ATI M92 electric leakage

M7
T11

PCH_HOT#
DRAMRST_CNTRL_PCH

Total device

CL_CLK1

<7>

2

PCIE_LAN#
PCIE_LAN

BF36
BE36
AY34
BB34

C9

2

2 0_0402_5%
2 0_0402_5%
1 10K_0402_5%

PERN3
PERP3
PETN3
PETP3

SMBCLK

1

Express Card --->

<32> CLK_PCIE_WLAN#
<32> CLK_PCIE_WLAN
+3VS
<32> WLAN_CLKREQ#

RH67 1
RH68 1
RH69
2

BG36
BJ36
AV34
AU34

SMBALERT#

H14

1

WLAN (Mini Card 1)--->

<32> CLK_PCIE_LAN#
<32> CLK_PCIE_LAN
+3V_PCH
<32> LAN_CLKREQ#

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3_C
PCIE_PTX_EXPRX_P3_C

PERN2
PERP2
PETN2
PETP2

E12

SMBCLK

5

10/100/1G LAN --->

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

2

C

CH15 1
CH16 1

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C

SML0CLK

PERN1
PERP1
PETN1
PETP1

+3V_PCH

2

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

BG34
BJ34
AV32
AU32

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
1K_0402_5%

1

<28>
<28>
<28>
<28>

CH21 1
CH22 1

PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1_C
PCIE_PTX_LANRX_P1_C

SMBUS

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

Link

Express Card --->

<32>
<32>
<32>
<32>

CH19 1
CH20 1

Controller

D

PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1

CLOCKS

WLAN (Mini Card 1)--->

<32>
<32>
<32>
<32>

PCI-E*

10/100/1G LAN --->

1
RH45
1
RH46
1
RH47
1
RH49
1
RH50
1
RH51
1
RH52
1
RH86
1
RH53

SMBDATA

2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

PCH (2/8) PCIE, SMBUS, CLK
Size

Document Number

Rev
1.0

LA-8241P
Date:

Wednesday, February 01, 2012
1

Sheet

14

of

56

5

4

3

2

1

UH1C

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

<5>
<5>
<5>
<5>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

+1.05VS

BJ24
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%~D

1
RH99
RH100

1

BG25
BH21

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place
within 500mil of the PCH

FDI_LSYNC1

PAD~D T57

C12
XDP_DBRESET#

<6> XDP_DBRESET#

SYS_PWROK
1
RH104

2

1

2

C

RH105
<6,24> PCH_PWROK

RH106

1

2

K3

SYS_PWROK_R P12
0_0402_5%

L22

0_0402_5%

L10

0_0402_5%

PM_DRAM_PWRGD

<6> PM_DRAM_PWRGD
<24> EC_RSMRST#

RH108

B13

2PCH_RSMRST#_R C21
0_0402_5%

1

SUSWARN#

<6,24> PBTN_OUT#

RH110

1

K16

2
0_0402_5%

E20

System Power Management

DSWVRMEN
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

DPWROK

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

AW16

FDI_INT

AV12

FDI_FSYNC0

FDI_INT

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

SLP_S3#
SLP_A#

B9
N3
G8
N14

WAKE#

1

2

<5>

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

LVDS_IBG
PAD~D

SUSCLK

2
RH107

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

<22> LVDS_ACLK<22> LVDS_ACLK+
<22> LVDS_A0<22> LVDS_A1<22> LVDS_A2-

PCIE_WAKE#

<22> LVDS_BCLK<24,28,32> <22> LVDS_BCLK+
<22> LVDS_B0<22> LVDS_B1<22> LVDS_B2-

2 AC_PRESENT_R H20
RB751V-40_SOD323-2

1
0_0402_5%

SUSCLK_R

<22> LVDS_B0+
<22> LVDS_B1+
<22> LVDS_B2+

<24>

GPIO72

E10

RI#

A10

ACPRESENT / GPIO31

SLP_SUS#

<21> CRT_B
<21> CRT_G
<21> CRT_R

PM_SLP_S4# <24>
PM_SLP_S3# <24,28>

G10

BATLOW# / GPIO72

PMSYNCH

RI#

SLP_LAN# / GPIO29

PM_SLP_SUS#

AP14

H_PM_SYNC

K14

BD82HM77 QPRG C1 BGA 989P PCH

T59

RH230
1
1
RH202

<21> CRT_HSYNC
<21> CRT_VSYNC

PAD~D

H_PM_SYNC

2 10K_0402_5%

If not using integrated
LAN,signal may be left as NC.

RI#

RH117 1

2 10K_0402_5%

PCIE_WAKE#

RH118 1

AC_PRESENT_R

RH121 1

2 200K_0402_5%

DSWODVREN

RH119

2

SUSWARN#

RH124 1

2 10K_0402_5%

DSWODVREN

RH122

2

RH126 1

2 10K_0402_5%

RH127 1

2 10K_0402_5%

WAKE#
EC_RSMRST#

@

AH45
AH47
AF49
AF45

LVDS_B0+
LVDS_B1+
LVDS_B2+

AH43
AH49
AF47
AF43

CRT_B
CRT_G
CRT_R

N48
P49
T49

CRT_DDC_CLK
CRT_DDC_DATA

T39
M40

33_0402_5%
2 HSYNC
2 VSYNC
33_0402_5%

M47
M49
T43
T42

*

D

LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

HDMI

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD

mDP

CRT_BLUE
CRT_GREEN
CRT_RED

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

DMC

DAC_IREF
CRT_IRTN

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

P38
M39

PCH_SDVO_CTRLCLK <23>
PCH_SDVO_CTRLDATA <23>

AT49
AT47
AT40

HDMI_DET

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

HDMI_DET <23>
HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

C

M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

BD82HM77 QPRG C1 BGA 989P PCH

B

10P_0402_50V8J

1 330K_0402_5%
@

Reserve for RF please close to UH1
RH120

1 330K_0402_5%

RH123
+3VS

：：

RH132
RH134

1
RH133
1
RH135
1
RH136 @
1
RH137
1
RH138
1
RH233
1
RH234
@
1
RH238
@
1
RH239

1

IN1

3

IN2

UH3

VCC

5

CH30
0.1U_0402_16V7K

2

OUT

4

SYS_PWROK

SYS_PWROK

<6>

2
2.2K_0402_5%
2
2.2K_0402_5%
2
8.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

CTRL_CLK
RH235
CTRL_DATA
RH236
PM_CLKRUN#
RH237

1

2
10K_0402_5%
2
2.37K_0402_1%
2
100K_0402_5%
2
100K_0402_5%
2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

1
1
1
1
1
1

PM_CLKRUN#
LVDS_IBG
PCH_ENVDD
ENBKL
CRT_B
CRT_G
CRT_R

LVDS_DDC_CLK
LVDS_DDC_DATA
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
CRT_DDC_CLK
CRT_DDC_DATA

A

MC74VHC1G08DFT2G_SC70-5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

AP39
AP40

L_CTRL_CLK
L_CTRL_DATA

DSWODVREN - On Die DSW VR Enable
H Enable
L Disable

GND

PCH_PWROK

A

AF40
AF39

LVDS_B0LVDS_B1LVDS_B2-

SDVO_INTN
SDVO_INTP

AM42
AM40

2 10K_0402_5%

2

VGATE

LVDS_BCLKLVDS_BCLK+

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

CH29
2
1

1

<6,50>

AN47
AM49
AK49
AJ47

L_BKLTCTL

AP43
AP45

2
@

+RTCVCC

+3VS

<6,24> PCH_PWROK

LVDS_A0+
LVDS_A1+
LVDS_A2+

SDVO_TVCLKINN
SDVO_TVCLKINP

RH115
1K_0402_0.5%

SUSCLK
B

AN48
AM47
AK47
AJ48

CRT_IREF

Can be left NC when IAMT is
not support on the platfrom

+3V_PCH
RH116 1

LVDS_A0LVDS_A1LVDS_A2-

<6>

Check EC for S3 S4 LED

GPIO72

AK39
AK40

L_BKLTEN
L_VDD_EN

PM_SLP_S5# <24>

<21> CRT_DDC_CLK
<21> CRT_DDC_DATA

G16

LVDS_ACLKLVDS_ACLK+

PAD~D

DH4

1

<24,35,43,44> ACIN

AF37
AF36

T56

PCH_RSMRST#_R

0_0402_5%

T58

T45
P39

<5>

FDI_FSYNC0

2 0_0402_5%

T40
K47

CTRL_CLK
CTRL_DATA

PM_CLKRUN#
SUS_STAT#

LVDS_DDC_CLK
LVDS_DDC_DATA

<22> LVDS_A0+
<22> LVDS_A1+
<22> LVDS_A2+

1 RH128

RH103

P45

<22> VGA_PWM
<22> LVDS_DDC_CLK
<22> LVDS_DDC_DATA

DSWODVREN

E22 PCH_DPWROK

J47
M45

AE48
AE47

@

WAKE#

UH1D
ENBKL
PCH_ENVDD

<24>
ENBKL
<22> PCH_ENVDD

Digital Display Interface

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

LVDS

<5>
<5>
<5>
<5>

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

CRT

BC24
BE20
BG18
BG20

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

D

<5>
<5>
<5>
<5>

4

3

2

PCH (3/8) DMI,FDI,PM,GFX,DP
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet

15

of

56

1

Compal Electronics, Inc

5

4

3

2

1

8
7
6
5

D

1
2
3
4

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#

1
2
3
4

GPIO51
GPIO52
PXS_PWREN
FFS_INT1

8.2K_0804_8P4R_5%
RPH2
8
7
6
5

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

8.2K_0804_8P4R_5%
RPH3
8
7
6
5

1
2
3
4

GPIO5
PCI_PIRQA#
GPIO4
ODD_DA#

8.2K_0804_8P4R_5%
10K_0402_5%

2 RH140 1

<33>
<33>
<32>
<32>
<33>
<33>
<32>
<32>
<33>
<33>
<32>
<32>
<33>
<33>
<32>
<32>

DGPU_HOLD_RST#

C

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

<36,52> PXS_PWREN

GPIO51

CH31
2
1

CLK_PCI1

WL_OFF#

<29> FFS_INT1
<29> ODD_DA#

@
10P_0402_50V8J

K40
K38
H38
G38

DGPU_HOLD_RST#
C46
GPIO52
C44
PXS_PWREN
E40

<34> DGPU_HOLD_RST#

<32>

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

WL_OFF#

D47
E42
F46

FFS_INT1
ODD_DA#
GPIO4
GPIO5

G42
G40
C42
D44

Reserve for RF please close to PCH
PAD~D

T60 @

<34> PCH_PLTRST#

K10
PCH_PLTRST#

C6

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

H49
H43
J48
K42
H40

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

CLK_PCI_LPBACK
CLK_PCI_LPC

RH144
RH145

1 22_0402_5%
2 22_0402_5%
PAD~D T61 @
PAD~D T62 @
PAD~D T63 @

2
1

RSVD5
RSVD6

AT10
BC8

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

RSVD25

AT8

RSVD26
RSVD27

AY5
BA2

RSVD28
RSVD29

AT12
BF3

D

Intel Anti-Theft Techonlogy

NV_ALE

High=Endabled
Low=Disable(floating)

*

+1.8VS
NV_ALE

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USBRBIAS#

C33

USBRBIAS

USBRBIAS

B33

USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

@ RH1391

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

2 1K_0402_5%

<33>
<33>
<33>
<33>
<32>
<32>
<32>
<32>
<32>
<32>
<32>
<32>

USB20_N8 <32>
USB20_P8 <32>
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

<32>
<32>
<28>
<28>
<22>
<22>

USB Conn 1
USB Conn 2 (with PWR Share)
USB Conn 3

C

USB Conn 4
Mini Card-1 (WLAN)
Mini Card-2 (mSATA)

Finger Print
Card Reader
Express Card
Camera

Within 500 mils
1
RH143

2
22.6_0402_1%

+3V_PCH
RPH4

PME#
PLTRST#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

B

<14> CLK_PCI_LPBACK
<24> CLK_PCI_LPC

AY7
AV7
AU3
BG4

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

RSVD1
RSVD2
RSVD3
RSVD4

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USB

RPH1

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI

+3VS

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

RSVD

UH1E

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

<33>
<33>
<32>
<32>

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

BD82HM77 QPRG C1 BGA 989P PCH

+3VS
2

@
1
RH149

4
3
2
1

5
6
7
8

B

10K_1206_8P4R_5%
RPH5
4
5
3
6
2
7
1
8
10K_1206_8P4R_5%

2
0_0402_5%

+3VS

@
RH150
10K_0402_5%

5

1

CH101
2
0.1U_0402_25V6K

IN1

1

IN2

2

P

1

UH5
4

O

PCH_PLTRST#

SN74AHC1G08DCKR_SC70-5
2

3

1

G

<6,24,28,32> PLT_RST#

RH155
100K_0402_5%

RH157
10K_0402_5%

@

2

A

1

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PCH (4/8) PCI, USB, NVRAM
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

16

of

56

5

4

3

2

1

UH1F

GPIO6

H36

TACH2 / GPIO6

TACH6 / GPIO70

EC_SCI#

E38

TACH3 / GPIO7

TACH7 / GPIO71

<24> EC_SMI#

EC_SMI#

C10

GPIO8

+3VS
2
RH160
10K_0402_5%

1

1

High: CRT Plugged

CRT_DET

<36,52> VGA_PWRGD

D

2
QH4 G
SSM3K7002F_SC59-3 S

<26> KB_DET#

+3VS

<32>

BT_ON#

<29> ODD_DETECT#
10K_0402_5%

2 RH164 1

2 PCH_LID_SW_IN#
RH73
GPIO16

3

<21> CRT_DET#

EC_LID_OUT# 1
0_0402_5%

<24> EC_LID_OUT#

GPIO1

VGA_PWRGD

<29> FFS_INT2

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

*

H
L

：
voltage regulator enable
：On-Die
On-Die PLL Voltage Regulator disable
1

2

@ RH165

<32> HDD_DETECT#

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

E8

GPIO24 / MEM_LED

PCH_GPIO27

E16

GPIO27

PCH_GPIO28

P8

GPIO28

BT_ON#

K1

STP_PCI# / GPIO34

GPIO35

K4

GPIO35

ODD_DETECT#

V8

PCH_GPIO37

M5

SATA3GP / GPIO37

PCH_GPIO38

N2

SLOAD / GPIO38

PCH_GPIO39

M3

SDATAOUT0 / GPIO39

PCH_GPIO28

V13

1

PCH_GPIO37

2

KB_RST# <24>
H_CPUPWRGD <6>

H_THERMTRIP#_C 1
390_0402_5%
INIT3_3V#

2
RH162

H_THERMTRIP#

H_THERMTRIP# <6>

INIT3_3V#

T14

DF_TVS

AY1

TS_VSS1

AH8

TS_VSS2

AK11

TS_VSS3

AH10

INIT3_3V

TS_VSS4

AK10

This signal has weak internal
PU, can't pull low

NV_CLE
@
RH163
10K_0402_5%

SATA2GP / GPIO36

NC_1

P37

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

C

BG48

VSS_NCTF_17

BH3

DMI Termination Voltage

BH47

Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_22
VSS_NCTF_23

BJ4
BJ44
BJ45

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

F1

VSS_NCTF_14

VSS_NCTF_32

F49

BF49

RH166
2.2K_0402_5%

BJ6

VSS_NCTF_24

BF1

Weak internal
PU,Do not pull low

BJ5

VSS_NCTF_7

10K_0402_5%

+1.8VS

BJ46

VSS_NCTF_6

BE49
RH169

AY10

<6,24>

VSS_NCTF_16

B47

B

KB_RST#

AY11

H_PECI

GPIO57

BD1

PCH_GPIO37

P5

@
1
2
0_0402_5% RH161

SATA5GP / GPIO49

B3

+3VS

PCH_PECI_R

V3

A6

LOW - Tx, Rx terminated
to same voltage
(DC Coupling Mode)

GATEA20 <24>

AU16

D6

A4

FDI TERMINATION VOLTAGE OVERRIDE

1 1K_0402_5%

THRMTRIP#

P4

HDD_DETECT#

A44

PCH_GPIO37

@

RCIN#
PROCPWRGD

VSS_NCTF_18

1K_0402_5%

D

GPIO49

A5

2

TACH0 / GPIO17

KB_DET#

A46

RH168

PECI

SCLOCK / GPIO22

A45

*

A20GATE

T5

FFS_INT2

+3VS

A40

RH159
10K_0402_5%

PCH_GPIO22

C

C41

1

RH241

PAD~D

C2
2

<24> EC_SCI#

ODD_EN# <29>
@ T64

1

PCH_GPIO28

ODD_EN#
GPIO69

1

PCH_LID_SW_IN#

B41

2

1

C40

TACH5 / GPIO69

A42

CPU/MISC

1

TACH4 / GPIO68

TACH1 / GPIO1

GPIO1
RH240
10K_0402_5% 2

D

BMBUSY# / GPIO0

NCTF

1K_0402_5% 2

T7

2

CRT_DET

GPIO

+3V_PCH

NV_CLE
2
1K_0402_5%

C48

1
RH167

H_SNB_IVB# <6>

D1

CLOSE TO THE BRANCHING POINT

RH161 and RH162
Follow CRB FAB2 setting

E49

B

BD82HM77 QPRG C1 BGA 989P PCH
+3VS

2 PCH_GPIO27
10K_0402_5%

1
@ RH173

+3V_PCH

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

ODD_EN#

1

HDD_DETECT#

1

CRT_DET#

1

ODD_DETECT#

1

GPIO16

1

BT_ON#

1

KB_RST#

1

VGA_PWRGD

1

PCH_GPIO22

1

GPIO35

1

GPIO49

1

PCH_GPIO38

1

PCH_GPIO39

1

2 10K_0402_5%

10K_0402_5%
200K_0402_5%
10K_0402_5%
8.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 10K_0402_5%
RH177

RH178
2 10K_0402_5%
RH179

A

@
2
RH170
2
RH171
2
RH172
2
RH174
2
RH175
2
RH242
2
RH176

2 10K_0402_5%
RH180

Please refer to Huron River Debug Board DG 0.5

2 10K_0402_5%

A

RH181
2 10K_0402_5%
RH182
EC_SMI#

2 10K_0402_5%

1

GPIO6

RH183

2 10K_0402_5%

1
RH184

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PCH (5/8) GPIO, CPU, MISC
Document Number

Rev
1.0

LA-8241P
Sheet

Wednesday, February 01, 2012
1

17

of

56

5

4

3

2

1

D

D

+1.05VS

POWER

UH1G

+3VS

Voltage Rail

@

+1.05VS

+1.05VS

RH186

+1.05VS_VCCDPLLEXP AN19

1 0_0603_5%

2

VCCADAC
VSSADAC

U48

1
U47
2

1mA VCCALVDS

AK36

VSSALVDS

AK37

VCCTX_LVDS[1]

AM37

VCCTX_LVDS[2]

AM38

60mA VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

+VCCA_LVDS

1

2

CH33
0.1U_0402_10V7K~D

CRT

1mA

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

+VCCADAC

CH32
0.01U_0402_16V7K

2

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

LVDS

2

1

2
1
4.7UH_LQM18FN4R7M00D_20%

1

V_PROC_IO

CH34
10U_0805_4VAM~D

2

V5REF

AN17

2 @
+1.05VS

AN21

1

AN26

RH189
0_0805_5%

AN27

2

AP21

2

RH192
0_0805_5%

2

AP23
1

2

CH49
1U_0402_6.3V6K

2

1

CH48
1U_0402_6.3V6K

2

1

CH47
1U_0402_6.3V6K

1

2

1

CH46
1U_0402_6.3V6K

1

+3VS

CH45
10U_0805_4VAM~D

+1.05VS_VCC_EXP

AP24
AP26
AT24
AN33

+3VS_VCCA3GBG

1

VCCIO[15]
VCCIO[16]

Near AP43

LH2
2
1
0.1UH_MLF1608DR10KT_10%_1608

+VCCTX_LVDS
CH41
CH39 1
1
1
0.01U_0402_16V7K
22U_0805_6.3V6M
CH40
0.01U_0402_16V7K
2
2
2

VCCIO[19]

@

1
0_0603_5%
1

CH53
1U_0402_6.3V6K

2
RH194

2 @

+1.05VS

+1.05VS_VCCAPLL_FDI

2

VCCVRM[3]

AT16

VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCDMI[1]

20mA VCCCLKDMI

AT20

AB36

1

+1.05VS_VCC_DMI_CCI
1

2

RH191
1
2
0_0805_5%

0.001
0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.3

VccDMI

1.05

0.042

VccIO

1.05

2.925

VccASW

1.05

1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

3.3

0.119

VCC3_3[3]

190mAVCCDFTERM[2]

AG17

VCCVRM[2]
VccAFDIPLL

VCCDFTERM[3]
VCCDFTERM[4]

0_0805_5%
CH44

+1.05VS

2 1U_0402_6.3V6K

VccSus3_3

CH50
1U_0402_6.3V6K

VCCDMI[2]

20mA VCCSPI

1
RH193

AJ16

1

AJ17

V1

VccSusHDA

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

+VCCPNAND

2

2
+1.8VS
0_0805_5%

RH196

VCCIO[27]

+3V_VCCPSPI

1
2
0_0805_5%

VccCLKDMI

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

+1.5VS

+3V_PCH

1

1
0_0603_5%
@

+3VS

CH54
1U_0402_6.3V6K

+VCCAFDI_VRM

2

RH197
1
0_0603_5%

+VCCAFDI_VRM
1

2

A

CH100
1U_0402_6.3V6K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

B

RH243
2

BD82HM77 QPRG C1 BGA 989P PCH

2

5

C

2

VCCIO[25]

BH29

A

+VCCP

RH190

+VCCP_VCCDMI
1

AG16

AU20

+VCCAFDI_VRM
+VCCP_VCCDMI

VCCDFTERM[1]

BG6

CH43
0.1U_0402_10V7K~D

V34

VCCIO[26]

RH195
1
2 +1.05VS_VCCDPLL_FDI AP17
0_0805_5%
+VCCP_VCCDMI

VCC3_3[7]

2925mA

0.1U_0402_10V7K~D

Place CH53 Near BG6 pin

+3VS

1

AN34

AP16

RH188
1
2
0_0805_5%

+3VS_VCC3_3_6

V33

VCCIO[18]

CH51
+VCCAFDI_VRM

VCC3_3[6]

FDI

2

5
3.3

0.1uH inductor, 200mA

VCCIO[17]

+1.05VS
B

0.001

2 0_0805_5%

1

CH52
0.1U_0402_10V7K~D

AN16

HVCMOS

Place CH40 Near BJ22 pin

0.001

5

Vcc3_3

V5REF_Sus
RH185

+1.8VS

VCCAPLLEXP

DMI

C

BJ22

DFT / SPI

+VCCAPLLEXP
1

1.05

VCCIO[28]

VCCIO

1 +VCCAPLLEXP_R1
2
0_0603_5%
1UH_LB2012T1R0M_20%~D

CH42
10U_0805_4VAM~D

@

S0 Iccmax
Current (A)

+3VS

@ LH3
2
RH187

Voltage

LH1

VCC CORE

2

1

CH38
1U_0402_6.3V6K

2

1

CH36
1U_0402_6.3V6K

1
PAD-OPEN 4x4m 1

CH35
10U_0805_4VAM~D

2

1300mA

+1.05VS_VCCCORE
CH37
1U_0402_6.3V6K

JP1

PCH Power Rail Table

3

2

PCH (6/8) PWR
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

18

of

56

5

4

3

2

1

VCC3_3 = 266mA detal waiting for newest spec

+1.05VS

1

2

C

2
0_0805_5%

1

+3VS

2

1

2

1

2

CH70
1U_0402_6.3V6K

1
RH211

CH66
22U_0805_6.3V6M

+1.05VS

2

CH69
1U_0402_6.3V6K

2

1

CH68
1U_0402_6.3V6K

1

CH65
22U_0805_6.3V6M

+1.05VM_VCCASW

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]
VCCASW[10]

AC31

VCCASW[11]

2
RH215

AD31
W21
W23

CH75
1U_0402_6.3V6K

2

CH74
10U_0805_10V6K

LH5
10UH_LBR2012T100M_20%
+3VS_VCC_CLKF33
1
2
1
1
@
2

W24
W26
W29
W31
W33

VCCASW[13]
VCCASW[14]
VCCASW[15]

+VCCRTCEXT
2
RH219

@

1

+1.05VM_VCCSUS

1
0_0603_5%

N16

V24

VCCIO[34]

T26

+1.05VS_VCCAUPLL

M26

+PCH_V5REF_SUS

DCPSUS[4]

AN23

+VCCA_USBSUS

VCCSUS3_3[1]

AN24

+3V_VCCPSUS_1

1mA V5REF

P34

VCCSUS3_3[2]

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

VCC3_3[1]
VCC3_3[8]

VCCASW[16]

VCC3_3[4]

+VCCAFDI_VRM

CH79
0.1U_0402_10V7K~D

2

Y49

BD47

+VCCDIFFCLK

1
0_0603_5%

+1.05VS_VCCA_B_DPL

VCCASW[20]
DCPRTC
VCCVRM[4]

+1.05VS_VCCDIFFCLKN

1
0_0603_5% 1

2

+1.05VS

BF47

VCCADPLLB

AF17
AF33
AF34
AG34

VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

+1.05VS_SSCVCC

CH82
1U_0402_6.3V6K

AG33

CH84
1U_0402_6.3V6K

CH85
0.1U_0402_10V7K~D

1

2

1

LH7
10UH_LBR2012T100M_20%
1
2
2

1
2
LH8
10UH_LBR2012T100M_20%

1
+

1

2

2

+1.05VS_VCCA_B_DPL

1

2

1
+
2

1

2

2

RH213
0_0603_5%
1

2

VCCIO[6]

80mA

VCCAPLLSATA
VCCVRM[1]

2
RH214

VCCSSC

VCCIO[4]

95mA

+3VS_VCCPPCI

+VCC3_3_2

2

2
1

V_PROC_IO 1mA

2

2
RH216

VCCASW[22]
VCCASW[23]
VCCASW[21]

0_0603_5%
CH77
0.1U_0402_10V7K~D

1

RH203
20K_0402_5%

RH218
2
1

1

2

@ LH6
10UH_LBR2012T100M_20%
1
2 +VCCSATAPLL_R

+VCCSATAPLL
+VCCAFDI_VRM
1

+VCCAFDI_VRM
+1.05VS_VCC_SATA
+1.05VS_VCC_SATA

AC17

2
1

AD17

+1.05VS

0_0805_5%
CH78
1U_0402_6.3V6K

1

+1.05VS

B

@
RH221
2

1

+1.05VS

0_0805_5%
@ CH81
10U_0805_10V6K

2

0_0805_5%

+1.05VS

T21
V21
T19

1

2

1

2

A22

VCCRTC

10mA VCCSUSHDA

+VCCSUSHDA

P32
1

BD82HM77 QPRG C1 BGA 989P PCH
0.1U_0402_10V7K~D

CH93
2

1
0_0603_5%

+3V_PCH

If it support 3.3V audio signals
POP:RH244
Depop RH245 / RH246
A

If it support 1.5V audio signals
POP:RH245 / RH246
Depop R244

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

@

2
RH229

2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

2

1
0_0603_5%

CH76
0.1U_0402_10V7K~D

+1.05VS_SATA3

AC16

CH72
1U_0603_10V6K

+3VS

AF14
AK1

+PCH_V5REF_RUN

1

+1.05VS_SATA3

DCPSST
DCPSUS[1]
DCPSUS[2]

C

DH3
RB751S40T1_SOD523-2~D

1
0_0805_5%

RH222
VCCIO[2]

CH64
0.1U_0603_25V7K

+3VS

RH212
100_0402_1%

+3V_PCH

CH73
0.1U_0402_10V7K~D

2

AF13

AF11

2

+3VS

+3VS_VCCPCORE
1

1

AH14

+3V_PCH

CH71
1U_0402_6.3V6K

1

VCCIO[13]

+PCH_V5REF_SUS

1

1

T34

AH13

CH57
0.1U_0402_10V7K~D

2

1
0_0603_5%

DH2
RB751S40T1_SOD523-2~D

+5VS

W16

AJ2

2

RH208
100_0402_1%

+RTCVCC

+1.05VS_VCCA_A_DPL

+VCCA_DPLL_L

0_0805_5%

2

T17
V19

@
CH86
1U_0402_6.3V6K

BJ8

CH97
1U_0402_6.3V6K

1
RH232

1

CH95
220U_B2_2.5VM_R35M~D

+1.05VS

CH94
220U_B2_2.5VM_R35M~D

A

2

CH96
1U_0402_6.3V6K

2

1
CH87
4.7U_0603_6.3V6K

CH89
0.1U_0402_10V7K~D

+V_CPU_IO

CH88
0.1U_0402_10V7K~D

2
2
0_0603_5%

2

+1.05VM_VCCSUS

CH92
1U_0402_6.3V6K

2

1

CH91
0.1U_0402_10V7K~D

1

+VCCP

2
RH210

2

CH90
0.1U_0402_10V7K~D

1
0_0603_5%

V16

+1.05VS

+3V_PCH

1

AA16

VCCIO[12]

VCCIO[3]

+VCCSST

1
RH227

80mA

MISC

2
RH223

2
RH224

VCCADPLLA

HDA

2

+1.05VS_VCCDIFFCLKN

1
0_0603_5%

+3V_VCCPSUS

2

CH80
1U_0402_6.3V6K

+PCH_V5REF_RUN

1

+3VS
VCC3_3[2]

CPU

+1.05VS

2
RH209

+5V_PCH

+VCCA_USBSUS

RH217

VCCASW[19]

RTC

1

2

VCCASW[18]

SATA

+1.05VS_VCCA_A_DPL
2
RH220

1

VCCASW[17]

+1.05VS

B

2

P24

VCCIO[5]
+1.05VS

1

V23

VCCSUS3_3[6]

1mA V5REF_SUS

VCCASW[12]

T24

VCCSUS3_3[10]

1010mA

AC29

AD29
1
0_0805_5%

DCPSUS[3]

VCCSUS3_3[9]

2

1
+3V_PCH
0_0603_5%
2
1
+3V_PCH
RH206
0_0603_5%

2

AL24

@
CH62
1U_0402_6.3V6K

VCCSUS3_3[8]
VCCIO[14]

2
RH205
+3V_VCCAUBG

1

+VCCSUS1

VCCAPLLDMI2

<27> PCH_PWR_EN#
+3V_VCCPUSB

T23

D

2

AL29

T29

1

BH23

+VCCDPLL_CPY

1

1

+VCCAPLL_CPY_PCH

2

1

2

2
0_0603_5%

119mA VCCSUS3_3[7]

3

CH56
1U_0402_6.3V6K

1

1
RH207

VCCIO[33]

2

+1.05VS

2

VCCIO[32]

1

2

VCC3_3[5]

QH5
AO3419L_SOT23-3 +5V_PCH

RH201
0_0603_5%
2
1

@CH63
1U_0402_6.3V6K

T38

T27

+5VALW

+1.05VS

CH67

1

DCPSUSBYP

+3VS_VCC_CLKF33

1
@ CH58
0.1U_0402_10V7K~D

P28

CH83
1U_0402_6.3V6K

@

V12

P26

VCCIO[31]

1
0_0603_5%

RH231
150_0402_1%
2
1

CH59
10U_0805_10V6K

0_0805_5%

+PCH_VCCDSW

VCCIO[30]

3mA

VCCDSW3_3

2
RH200

CH61
0.1U_0402_10V7K~D

@ LH4
10UH_LBR2012T100M_20%
+VCCAPLL_CPY 1
2

@ RH204
1
2

T16

+1.05VS_VCCUSBCORE

N26

G

+1.05VS

+VCCPDSW

VCCIO[29]

D

2

D

VCCACLK

S

CH55
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

AD49

1

CH60
0.1U_0402_10V7K~D

2
0_0603_5%

USB

1
RH199

VCCDMI = 42mA detal waiting for newest spec

POWER

UH1J

PCI/GPIO/LPC

+3V_PCH

+VCCACLK
1
0_0603_5%

@

Clock and Miscellaneous

2
RH198

4

3

2

PCH (7/8) PWR
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

19

of

56

5

4

3

2

1

UH1I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

UH1H

D

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

C

B

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

BD82HM77 QPRG C1 BGA 989P PCH

A

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

D

C

B

A

BD82HM77 QPRG C1 BGA 989P PCH

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PCH (8/8) VSS
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

20

of

56

5

4

3

2

1

C R T
for debug CRT
VGA_CRT_R RV223 1
VGA_CRT_G RV224 1
VGA_CRT_B RV225 1
VGA_CRT_HSYNCRV226 1
VGA_CRT_VSYNCRV227 1
VGA_CRT_CLK RV228 1
VGA_CRT_DATARV229 1

<35> VGA_CRT_R
<35> VGA_CRT_G
<35> VGA_CRT_B
<35> VGA_CRT_HSYNC
<35> VGA_CRT_VSYNC
<35> VGA_CRT_CLK
<35> VGA_CRT_DATA

@
@
@
@
@
@
@

D

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
CRT_DDC_CLK
CRT_DDC_DATA

20_0402_5%
20_0402_5%
20_0402_5%
20_0402_5%
20_0402_5%
20_0402_5%
20_0402_5%

+5VS

+R_CRT_VCC
DV4

W=40mils

+CRT_VCC
FV2

2
3 NC

1

1

2

W=40mils
1

From VGA
D

1.1A_6VDC_FUSE

BAT1000-7-F_SOT23-3~D

1

RV1
2

0_1206_5%
1
@

100K_0402_5%

CV1
0.1U_0402_16V7K

2

2

RV2
<17> CRT_DET#
LV1

0_0603
2

1

<15> CRT_R

LV2
CRT_R_C

1

LQW18AN47NG00D _0603
2 CRT_R_L

DV1

@

2

1
2

1
2

1
2

1
2

2

1

1

2

1

1

1
2

1

For EMI

HSYNC_L
CRT_B_L

2
1

VSYNC_L

3
PESD5V0U2BT_SOT23-3

CRT_DDC_CLK_C
CV12
100P_0402_50V8J

2

@

CRT_DDC_DATA_C
CRT_G_L

PESD5V0U2BT_SOT23-3
DV2
@
CV11
10P_0402_50V8J

1

1

LQW18AN47NG00D _0603
2 CRT_B_L

1
3

CV10
10P_0402_50V8J

2

LQW18AN47NG00D _0603
2 CRT_G_L

CV9
10P_0402_50V8J

@

RV5
150_0402_1%

RV4
150_0402_1%

RV3
150_0402_1%

CV8
150_0402_1%

CV7
150_0402_1%

CV6
150_0402_1%

For EMI

@

1

CRT_B_C

C

2

<15> CRT_B

1
LV6
CV5
22P_0402_50V8J

1

0_0603
2

LV5

LV4
CRT_G_C

CV4
22P_0402_50V8J

0_0603
2

CV3
22P_0402_50V8J

1

2

LV3
<15> CRT_G

JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

PAD~D T65 @
CRT_R_L

2

1

C

G
G

16
17

SUYIN_070546HR015M22BZR
CONN@

2

B

B

D_CRT_HSYNC

1

UV26
74AHCT1G125GW_SOT353-5

2 0_0603_5%

HSYNC_L

2 0_0603_5%

VSYNC_L
1

RV12
10K_0402_5%
1
2

5
1
2

P
OE#

CRT_VSYNC

4

A

Y

UV27
74AHCT1G125GW_SOT353-5

3

<15> CRT_VSYNC

1

RV11
D_CRT_VSYNC 1

2

4

2

3

RV10
Y

G

2

5
1
A

CV15
10P_0402_50V8J

CRT_DDC_CLK_C

D

S

QV2
2N7002BKW_SOT323-3

P
OE#

2

+CRT_VCC
CV16
0.1U_0402_16V7K
1
2

CRT_DDC_DATA_C

QV1
2N7002BKW_SOT323-3
1

CRT_HSYNC

G

<15> CRT_HSYNC

CV14
10P_0402_50V8J

2

1

2
1
2

2

RV9
2.2K_0402_5%

3

1
D

G

<15> CRT_DDC_CLK

3
S

<15> CRT_DDC_DATA

+CRT_VCC
CV13
0.1U_0402_16V7K
1
2

+CRT_VCC +CRT_VCC

RV8
2.2K_0402_5%

1

+3VS

G

RV6
2.2K_0402_5%

1

+3VS
RV7
2.2K_0402_5%

2

+3VS

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

VGA / LVDS /camera conn.
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

21

of

56

5

4

3

2

1

+3VS

@

RV13
4.7K_0402_5%

@
DV5

+5VALW

BKOFF#

BKOFF#

1

2

JLVDS
<15> LVDS_A0<15> LVDS_A0+

LVDS_A0LVDS_A0+

<15> LVDS_A1<15> LVDS_A1+

LVDS_A1LVDS_A1+

<15> LVDS_A2<15> LVDS_A2+

LVDS_A2LVDS_A2+

<15> LVDS_ACLK<15> LVDS_ACLK+

LVDS_ACLKLVDS_ACLK+

<15> LVDS_B0<15> LVDS_B0+

LVDS_B0LVDS_B0+

USB20_P12_R

<15> LVDS_B1<15> LVDS_B1+

LVDS_B1LVDS_B1+

USB20_N12_R

<15> LVDS_B2<15> LVDS_B2+

LVDS_B2LVDS_B2+

DISPOFF#

2

2

1

<24>

2

+LCDVDD

LVDS Conn.

1

LCD PWR CTRL

1

3

1 1

2

3

S

1

2

EC_ENVDD

3

3

<24> EC_ENVDD

QV5
BSS138_SOT23~D

2
G

1

1

D
2

S

4.14
1

+LCDVDD

+LCDVDD

W=60mils

1

2

RV18
10K_0402_5%

1
CV20
4.7U_0805_10V4Z

CV21
0.1U_0402_16V7K

<16> USB20_P12

1

<16> USB20_N12

4

2

2

BAT54C-7-F_SOT23-3

5P_0402_50V8C @
1

D

PCH_ENVDD

CV19
0.1U_0402_16V7K

1

DV7
<15> PCH_ENVDD

2

AO3419L_SOT23-3
QV4

G

2
G

5P_0402_50V8C
CV17
@
1
2

CH751H-40PT_SOD323-2~D

S

QV3
SSM3K7002FU_SC70-3~D

2

10K_0402_5%
RV16

W=60mils
RV17
56K_0402_5%
2
1

D

D

+3VS

RV15
47K_0402_5%

RV14
100_0402_1%

CH751H-40PT_SOD323-2~D
DV6
1

DLW21SN900HQ2L_0805_4P~D
2
1
2
3
@

3

4
LV24
1
RV210

2
0_0402_5%

1
RV208

2
0_0402_5%

<15> LVDS_DDC_CLK
<15> LVDS_DDC_DATA

CV18
2

INV_PWM
DISPOFF#
USB20_P12_R
USB20_N12_R

<15> LVDS_BCLK<15> LVDS_BCLK+
<24> LCD_TEST
@
2
1
@ RV19 20_0402_1% 1
RV20 0_0402_1%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

LVDS_BCLKLVDS_BCLK+
LCD_TEST
EDID_CLK_LCD
EDID_DATA_LCD

+3VS_CAM
MIC_CLK_R
MIC_DATA

<30> MIC_DATA

W=60mils

CV22
0.1U_0402_16V7K

LCD backlight PWR CTRL

1

2

1

2

10U_0805_10V6K
CV24

+INV_PWR_SRC

0.1U_0402_16V7K
CV23

W=60mils

+LCDVDD
+3VS

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

D

STARC_107K40-000001-G2
CONN@

2

C

C

60mil

QV6
SI3457CDV-T1-E3_TSOP6~D
+INV_PWR_SRC_R
6
4
5
2
1
1

60mil
RV24 1

2 0_0805_5%

+INV_PWR_SRC

S

D

B+

2

* Reserved for EMI/ESD/RF
need to close to JLVDS

G

3

1

RV25
100K_0402_5%

2

5P_0402_50V8C
1

CV26
0.1U_0603_50V_X7R

5P_0402_50V8C
1

PWR_SRC_ON

CV27
@2

LVDS_BCLK-

CV28

DV8
LVDS_BCLK+

@2

MIC_CLK_R

6

V I/O

V I/O

USB20_P12_R

1

1

2

CV25
1000P_0402_50V7K

1

+5VS

RV26
100K_0402_5%

MIC_DATA

RV28
0_0402_5%
1

+LCDVDD_R

1

2
D

S

RV27 1

2 0_0805_5%

V I/O

V I/O

2
USB20_N12_R

3

IP4223CZ6_SO6-6

+INV_PWR_SRC

QV7
SSM3K7002FU_SC70-3~D

2
G

RV31
0_0402_5%
2
1

V BUS Ground

<15>

VGA_PWM

RV29
0_0402_5%
2
1

INV_PWM

MIC_CLK

<30> MIC_CLK

RV30
0_0402_5%
2
1

MIC_CLK_R
1

1

+LCDVDD

2

4

@
B+

3

<24> EN_INVPWR

5

1

RV230
100K_0402_5%

@

@
2

B

2

2

CV30
680P_0402_50V7K~D

@ CV29
470P_0402_50V7K~D
B

Wedcam PWR CTRL
+INV_PWR_SRC

* Reserved for LCD
sequence tuning

1
3 2

1

@
RV32
820_0805_1%
2N7002DW-7-F_SOT363-6

+5VALW

@
QV9B

0_0603_5%
@
QV9A
+LCDVDD_R

2

1

5
4

2
RV231

1
6

@

2

1

@

1

2

1
2

@2

RV209
2

3

+3VS

G

@

1

1000P_0402_50V7K

A

<24> CMOS_ON#

CV319

D

S

RV34
100K_0402_5%

+3VS_CAM

QV8
SI2301CDS-T1-GE3_SOT23-3

2N7002DW-7-F_SOT363-6

+3VS

RV33
100K_0402_5%
@

A

47K_0402_5%
CV31
0.1U_0402_16V7K

2
@
1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LVDS /camera conn.
Size

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Date:

Wednesday, February 01, 2012
1

Sheet

22

of

56

5

4

3

2

1

W=40mils

Place close to JHDMI1
RV36 0_1206_5%
2
1
@ 2 0_0402_5%

+VDISPLAY_VCC

1 0.1U_0402_10V7K~D TMDS_TXCN
1 0.1U_0402_10V7K~D TMDS_TXCP

1

TMDS_TXCP

4

<15> HDMI_A0N_VGA
<15> HDMI_A0P_VGA

CV36 2
CV37 2

1 0.1U_0402_10V7K~D TMDS_TX0N
1 0.1U_0402_10V7K~D TMDS_TX0P

<15> HDMI_A1N_VGA
<15> HDMI_A1P_VGA

CV38 2
CV39 2

1 0.1U_0402_10V7K~D TMDS_TX1N
1 0.1U_0402_10V7K~D TMDS_TX1P

<15> HDMI_A2N_VGA
<15> HDMI_A2P_VGA

CV40 2
CV41 2

1 0.1U_0402_10V7K~D TMDS_TX2N
1 0.1U_0402_10V7K~D TMDS_TX2P

1
4

2

2

TMDS_L_TXCN

3

3

TMDS_L_TXCP

2
1
3 NC
@
BAT1000-7-F_SOT23-3~D

2

+5VS

1

1.5A_6V_1206L150PR~D

WCM-2012HS-900T_4P

+3VS

RV37 1

@

2 0_0402_5%

RV38 1

@

2 0_0402_5%

1

1

2

2

TMDS_L_TX0N

TMDS_TX0P

4

4

3

3

TMDS_L_TX0P

1

@

DDC_DAT_HDMI
DDC_CLK_HDMI
TMDS_L_TXCN

2 0_0402_5%

2

2

TMDS_L_TX1N

TMDS_L_TXCP
TMDS_L_TX0N

3

3

TMDS_L_TX1P

TMDS_L_TX0P
TMDS_L_TX1N

LV9
1

1

TMDS_TX1P

4

4

2

1

1
2

2

1

1
2

1

1

1

2

2

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

2

RV49

RV48

RV47

RV46

RV45

RV44

RV43

RV42
2

HDMI_HPLUG

WCM-2012HS-900T_4P
@
RV40 1
2 0_0402_5%
RV41 1

TMDS_L_TX1P
TMDS_L_TX2N

WCM-2012HS-900T_4P
1

C

@
RV53
100K_0402_5%

@

RV52 1

2

2 0_0402_5%

TMDS_L_TX2P

JHDMI
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

QV11
S

CV35

@

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

20
21
22
23

C

ACON_HMR2U-AK120C
CONN@

2 0_0402_5%

2N7002_SOT23
LV10
TMDS_TX2N

1

TMDS_TX2P

4

1

2

4

3

2

TMDS_L_TX2N

3

TMDS_L_TX2P

2

RV51

RV50 1

D

2
G
3

+3VS

1

0_0402_1%
1
2

2

D

1

RV39
10K_0402_5%

LV8
TMDS_TX0N

TMDS_TX1N

1

1

CV32 2
CV33 2

2

<15> HDMI_A3N_VGA
<15> HDMI_A3P_VGA

FV1
CV34

TMDS_TXCN
D

DV9

10U_0603_6.3V6M

LV7

0.1U_0402_10V7K~D

RV35 1

46@

RV54 1

@

RO0000002HM

2 0_0402_5%

TMDS_TXCN

@ CV358

1

2 100P_0402_50V8J

TMDS_L_TXCN

CV349

1

2 3.3P_0402_50V8C~D

TMDS_TXCP

@ CV360

1

2 100P_0402_50V8J

TMDS_L_TXCP

CV350

1

2 3.3P_0402_50V8C~D

TMDS_TX0N

@ CV362

1

2 100P_0402_50V8J

TMDS_L_TX0N

CV351

1

2 3.3P_0402_50V8C~D

TMDS_TX0P

@ CV363

1

2 100P_0402_50V8J

TMDS_L_TX0P

CV352

1

2 3.3P_0402_50V8C~D

TMDS_TX1N

@ CV359

1

2 100P_0402_50V8J

TMDS_L_TX1N

CV353

1

2 3.3P_0402_50V8C~D

TMDS_TX1P

@ CV357

1

2 100P_0402_50V8J

TMDS_L_TX1P

CV354

1

2 3.3P_0402_50V8C~D

TMDS_TX2N

@ CV361

1

2 100P_0402_50V8J

TMDS_L_TX2N

CV355

1

2 3.3P_0402_50V8C~D

TMDS_TX2P

@ CV364

1

2 100P_0402_50V8J

TMDS_L_TX2P

CV356

1

2 3.3P_0402_50V8C~D

B

20111024 EMI ADD

ROYALTY HDMI W/LOGO

Part Number

WCM-2012HS-900T_4P

Description
HDMI W/Logo:RO0000002HM

B

20110805 EMI ADD

1

+3VS

6

1

2

2

CV42
220P_0402_50V8J

DV11
BAV99-7-F_SOT23-3
@

+5V_HDMI_DDC
2
2.2K_0402_5%

A

5

1
RV58

3

2

DDC_CLK_HDMI

RV55
100K_0402_5%

2

1

2
1

<15> PCH_SDVO_CTRLCLK
A

HDMI_HPLUG
1

@
RV59
200K_0402_5%

1

1

2

<15> HDMI_DET
@
0_0402_1%
RV56

@ DV10
RB751V-40GTE-17_SOD323-2~D
QV12A
DMN66D0LDW-7_SOT363-6

RV57
1
2
150K_0402_5%

2
B
E

2

3

+3VS

1

C
QV13
MMBT3904_NL_SOT23-3

+5VS

<15> PCH_SDVO_CTRLDATA

4

3

DDC_DAT_HDMI

+3VS
1
RV60

2
2.2K_0402_5%

QV12B
DMN66D0LDW-7_SOT363-6

Compal Secret Data

Security Classification
Issued Date

2012/01/17

2013/01/16

Deciphered Date

Title

Compal Electronics, Inc.
HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-8241P

Date:

5

4

3

2

Wednesday, February 01, 2012

Sheet
1

23

of

56

4

3

+3VALW

2

1
2
3
4
5
7
8
10

<16> CLK_PCI_LPC
RE8

+3VALW

1 47K_0402_5%

2

CE11

<6,16,28,32> PLT_RST#

2

EC_RST#
EC_SCI#

<17>
EC_SCI#
<32> AOAC_ON

0.1U_0402_16V7K

1

+3VALW

C

1
RE11
1
RE13
1
RE62
1
RE63
1
RE71
1
RE70
1
RE77
1
RE78
1
RE16
1
RE21
1
RE24
1
RE25

2 EC_SMB_CK1_R
2.2K_0402_5%
2 EC_SMB_DA1_R
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%

@
@

USB_DET#_DELAY
2
10K_0402_5%
WLAN_WAKE#
2
10K_0402_5%
DASH_SW3
2
100K_0402_5%
DASH_SW1
2
100K_0402_5%
2 EC_SMI#
1K_0402_1%
2 EC_PME#
10K_0402_5%
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%

@

@

<25>

KSI[0..7]

<25>

KSO[0..16]

KSI[0..7]
KSO[0..16]

EC_SMB_CK2 <35>
EC_SMB_DA2 <35>

<33> PWRSHARE_EN_EC#
EC_SMB_CK1 1 RE26
EC_SMB_DA1 1 RE27

<43,44> EC_SMB_CK1
<43,44> EC_SMB_DA1

<14> PCH_SMLCLK
<14> PCH_SMLDATA

+3VS

@

<15,28> PM_SLP_S3#
<15> PM_SLP_S5#

EC_SCI#
10K_0402_5%
2 PCH_HOT#
10K_0402_5%

1

2

RE32
1 @
RE35

2 RE38
KB930@

2

1

10K_0402_5%

1 0_0402_5% PCH_PWROK

PCH_PWROK
RE18

1 RE28
1 RE29

EC_SMB_CK1_R
2 0_0402_5%
EC_SMB_DA1_R
2 0_0402_5%
EC_SMB_CK2
EC_SMB_DA2
2 0_0402_5%
2 0_0402_5%

1 RE31
1 RE33

2 0_0402_5%
2 0_0402_5%

<17> EC_SMI#
<43>
PS_ID
<25> TOUCH_LED#
<22> CMOS_ON#
<43> 130W/90W#
<32> DASH_LED_PWM
<25> FAN_SPEED1

B

VCOUT0

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

PM_SLP_S3#_R
PM_SLP_S5#_R
EC_SMI#
TOUCH_LED#

<32>
EC_TX
<32>
EC_RX
PCH_PWROK
2
KB9012@ RE40

<6,15> PCH_PWROK
<32> DASH_SW1

DASH_LED_PWM
FAN_SPEED1
EC_PME#
EC_TX
EC_RX
1 0_0402_5%

<32> DASH_SW3

EC_PME#
2
0_0402_5%

1
RE61

<15,28,32> PCIE_WAKE#

EC_CRY1
EC_CRY2

<15> SUSCLK_R
2 RE45

USB_DET#_DELAY
1
RE72

<28> USB_DET#_DELAY

CMOS_ON#
2
0_0402_5%

1
CE17

2

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

12
13
37
20
38

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

1 100K_0402_5%
2
KB9012@

20P_0402_50V8

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

21
23
26
27

2

KB930@

PS2 Interface

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

68
70
71
72

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

83
84
85
86
87
88

EC_MUTE_R
USB_EN#

97
98
99
109

CPU1.5V_S3_GATE
WOL_EN#
ME_EN
RE15 2
1
0_0402_5% KB9012@

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

4

1

VCIN0_PH_R

2

PCH_HOT#_R

2 RE76
1
0_0402_5%

1
0_0402_5%

<43,44>

PCH_HOT#
0_0402_5%

PCH_HOT# <14>
IMVP_IMON <50>

VCIN0_PH2 <25>
3S_ON

<25>

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

SPI Flash ROM

GPIO
Bus

GPIO

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EN_INVPWR <22>
EN_DFAN1 <25>
EC_ENVDD <22>
LCD_TEST <22>

73
74
89
90
91
92
93
95
121
127

2
4.7K_0402_5%
2
4.7K_0402_5%

EC_MUTE# <30>

C

CPU1.5V_S3_GATE <10>
WOL_EN# <32>
ME_EN
<13>
VCIN0_PH <43>

FRD#
FWR#
SPI_CLK
FSEL#

FRD#
FWR#
SPI_CLK
FSEL#

FRD#

<26>
<26>
<26>
<26>

ENBKL
<15>
H_PECI
<6,17>
PX_MODE <36,52,53>
BATT_CHG_LED# <32> +3VLP
CAPS_LED <25>
reserve for
PWR_PWM_LED# <32>
BATT_LOW_LED# <32>
SYSON
<27,28,48>
VR_ON
<50>
RE30
@
47K_0402_5%

BATT_CHG_LED#
CAPS_LED
PWR_PWM_LED#
BATT_LOW_LED#
SYSON
VR_ON
PM_SLP_S4#_R

EC_RSMRST#
100
EC_RSMRST# <15>
EC_LID_OUT#
101
EC_LID_OUT# <17>
102 0_0402_5%2 RE34
1 KB9012@
VCOUT1_PH
103
104 VCOUT0 KB9012@
2 RE37
10_0402_5%
BKOFF#
105
BKOFF# <22>
PBTN_OUT#
106
PBTN_OUT# <6,15>
HDD_S3.5
107
HDD_S3.5 <29>
SA_PGOOD
108
SA_PGOOD <49>

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

110
112
114
115
116
117
118

ACIN_D
EC_ON_R
ON/OFF_R
LID_SW#
SUSP#

RE14 2
RE41 1
RE42 1

PECI_KB9012

RE43 1
KB9012@

V18R

124

+V18R

KB9012QF-A3_LQFP128_14X14

2

DASH_LED1#
2
0_0402_5%
DASH_LED2#
2
0_0402_5%
DASH_LED3#
2
0_0402_5%
WL_BT_LED#
2
0_0402_5%

1
RE64
1
RE65
SPI_CLK 1
RE66
FSEL#
1
RE67
FWR#

ENBKL
RE22
0_0402_5%
1
2
PECI_KB930 RE23 1 KB930@ 2 43_0402_1%

1

1
RE9
1
RE10

USB_EN# <32,33>
PWRSHARE_OE# <33>
EAPD
<30,31>
TP_CLK <25>
TP_DATA <25>

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

20mil

TP_DATA

1 0_0402_5% EC_MUTE#

RE12 2

TP_CLK
TP_DATA

119
120
126
128

TP_CLK

PECI_KB930 1
RE69

DASH_LED1# <32>
DASH_LED2# <32>
DASH_LED3# <32>
WL_BT_LED# <32>

2
0_0402_5%

WLAN_WAKE# <32>

KB9012 Rev.A2

PM_SLP_S4#_R 1
RE39

PM_SLP_S4#
2
0_0402_5%

PM_SLP_S4# <15>

VCIN1_PH <43>
VCOUT0_PH <45>
B

HDD_S3.5

1
RE80

2
0_0402_5%

ACIN_65W <35>

1 0_0402_5%
2 0_0402_5%
2 0_0402_5%

ACIN
<15,35,43,44>
EC_ON
<25,28>
ON/OFF <25>
LID_SW# <26,32>
SUSP#
<10,27,28,46,47,48>
SA_PGOOD
65W/90W# <43>
H_PECI
2
43_0402_1%

Co-lay KB930/KB9012 PECI

CE16

KB930

2
RE46

10K_0402_5%

R4930

LE2

KB9012

2 0.1U_0402_16V7K

EC_MUTE# 1

Stuff

4.7U_0805_10V4Z

CE14
1

R4944

ACIN

CE18
2

100P_0402_50V8J
1

EC_CRY2

OSC

OSC

1

RE19

BATT_TEMP <43,44>

VCIN0_PH
ADP_I

@

2

EN_DFAN1

SPI Device Interface

1 @
CE13
2

22P_0402_50V8J

VCOUT1_PH

@
YE1
32.768KHZ_12.5PF_Q13MC14610002

RE47
100K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2

2
RE7

1

Analog Board ID definition,
Please see page 4.

PCH_PWR_EN <27>

ECAGND
1
100P_0402_50V8J

NC

NC
2

P
G

NC

A

RE17 2
0_0402_5% @

2
0.1U_0402_16V7K

A

5

SN74LVC1G06DCKR_SC70-5
1
CE19
47P_0402_50V8J

Y

2

<44>
2
CE9

D

CE8

2

3

4

1

H_PROCHOT#

22P_0402_50V8J

1

BATT_TEMP
VCIN0_PH_R
ADP_I
AD_BID0
PCH_HOT#_R

63
64
65
66
75
76

KB_LED_PWM <26>
BEEP#
<30>
PCH_PWR_EN

1

3

1
2

UE2
<6,44> H_PROCHOT#

@
1
CE12
1

CE15

RE44 0_0402_5%

A

0.1U_0402_16V7K

+3VS

2

VR_HOT#

2
1

100K_0402_5%
KB_LED_PWM
BEEP#
43_0402_1% 2 RE36
1
ACOFF
ACOFF

2012/01/17

2013/01/16

Deciphered Date

Title

Compal Electronics, Inc.
EC ENE-KB930/Co-lay 9012

1

<50>

EC_CRY1

AD_BID0
RE5
56K_0402_5%
INS@

Rb

ECAGND 2
1
FBMA-L11-160808-800LMT_0603
VR_HOT#

VOS@

+5VS

DA Output

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

RE5

Reserved for KB9012

PWM Output
AD Input

RE3
100K_0402_5%

Ra

1

<17> GATEA20
<17> KB_RST#
<13>
SERIRQ
<13> LPC_FRAME#
<13>
LPC_AD3
<13>
LPC_AD2
1 @ 33_0402_5% <13>
LPC_AD1
<13>
LPC_AD0

+3VALW
1

AGND/AGND

CE10
@ 22P_0402_50V8J
RE6
2
1

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

Board ID

2

UE1

1

0.1U_0402_16V7K
CE7
ECAGND
2
KB9012@
RE4 2
+3VLP
1
0_0402_5%

EC_VDD/AVCC

D

RE2
0_0402_5%
1

1000P_0402_50V7K

67

1
1
1000P_0402_50V7K

69

2
2
0.1U_0402_16V7K

CE6

9
22
33
96
111
125

2
2
0.1U_0402_16V7K

2

2

LE1
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW_EC

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1
1
2
CE1
CE2
CE3
CE4
CE5

2

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1
RE1
0_0805_5%

11
24
35
94
113

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-8241P

Date:

5

4

3

2

Sheet

Wednesday, February 01, 2012
1

24

of

56

3

2

1

+FAN_POWER

ON/OFF

<24>

3

51_ON#

<43>

BAV70W_SOT323-3

1
2
3
4

EN_DFAN1

VEN
VIN
VO
VSET

GND
GND
GND
GND

8
7
6
5

+3VALW

2

VOS@
RE50
10K_0402_5%

40mil

6
5

2

JFAN
1
2
3
4
5

<24> FAN_SPEED1

DE2
1

3

3S_ON

<24>
2

BAV70W_SOT323-3

To
RE73

GND
GND

C

INT_KBD Conn.

POWER/B

390_0402_5% JPWR
2
1 1
2 2
3 3 G1
4 4 G2

<24>

KSI[0..7]

<24>

KSO[0..16]

KSI[0..7]
KSO[0..16]

JKB

5
6

ACES_50504-0040N-001
CONN@

2

3

<32> PWR_LED#

HE1
100K_0402_1%_TSM0B104F4251RZ

CE24
0.01U_0402_16V7K

+5VALW

1
PWR_LED#
ON/OFFBTN#

1
2
3

ACES_85204-0300N
CONN@

1

1

<32> DASH_SW2

Pop only for
SSI debug

DE5
PESD24VS2UT_SOT23-3~D

1

B

Touch pad

Touch Pad LED

+3VS
+5VS
1
2
3
4

TP_CLK
TP_DATA

KB_CAPS_PWR-

B

GND
GND

31
32

1
<24> CAPS_LED

D

3

ACES_51510-03041-001
CONN@

PESD5V0U2BT_SOT23-3
D1
C191KSKT-5A
INS@

2

240_0402_1%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

S

QE3
SSM3K7002FU_SC70-3~D

2
G

A

1

A

A

C191KSKT-5A

1

5
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

D2
VOS@

RE60
1
G1
G2

DE3
2

2

+TPLED

1
2
3
4

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KB_CAPS_PWR

ACES_50504-0040N-001
CONN@

2

3

TP_CLK
TP_DATA

2

1
390_0402_5%
R6

A

+5VS

JTP
<24>
<24>

1

1

1

+FAN_POWER

4

2

RE74
13.7K_0402_1%

@

<24> VCIN0_PH2

+3VS

+3VALW

RE75
100K_0402_5%

+3VLP

1

QE1
KB930@
S SSM3K7002F_SC59-3

Compal Secret Data

Security Classification
<24> TOUCH_LED#

Issued Date

2012/01/17

2013/01/16

Deciphered Date

Title

Compal Electronics, Inc.
SW/TP/SCREW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-8241P

Date:

5

D

1

1

1
EC_ON
RE51
KB930@
10K_0402_5%

RE20
0_0402_5%
VOS@

@

C

CE25
2.2U_0603_6.3V6K
2

HE1 place around FAN area.

2

2

1

RE79
13.7K_0402_1%

D

2
G

2

<24,28>

SW2
SMT1-05-A_4P
1
3

+5VS

APE8873M SOP 8P

@

Bottom Side

CE23
2

UE3

<24> EN_DFAN1

CE20
0.1U_0402_25V6K

3

2

2
1

1

2

1

2

ON/OFFBTN#

4

CE22

1

DE1

6
5

2

1

SW1
SMT1-05-A_4P
1
3

1

1000P_0402_50V7K

RE49
100K_0402_5%
KB9012@

TOP Side

D

2.2U_0603_6.3V6K

+3VLP

2

2

+3VALW

RE48
100K_0402_5%
KB930@

ON/OFF switch

FAN Control circuit

40mil

Power ON Circuit

2

4

2

5

4

3

2

Wednesday, February 01, 2012

Sheet
1

25

of

56

5

4

3

2

1

Keyboard back light

D

D

SPI ROM 128KB
+3VS

+3VALW

20mils

VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_CLK_R0_0402_5%2 KB930@ 1RE54
SPI_FWR#
2
1
0_0402_5% KB930@ RE55

SPI_CLK
FWR#

<24>
<24>

MX25L1005AMC-12G_SO8
KB930@
SA00002C100

20mil

1

S

2

RE59
0_0805_5%

1
KBBL@

KBBL@

JKBL

1
KBBL@

2

2

QE4
SSM3K7002FU_SC70-3~D
KBBL@

KB_BL_PWM
RE58
100K_0402_5%
KBBL@

G
3

<24> KB_LED_PWM

GND
GND

5
6

ACES_50519-00401-001
CONN@
QE2
SI3456BDV-T1-E3 1N TSOP6 W/D
KBBL@

4

S

@
RE56

@
CE53
2
1
1
2
22P_0402_50V8J
33_0402_5%

SPI_CLK_R

1
2
3
4

20mil
D

Reserve for EMI please close to U15

C

1
2
3
4

2
G

1
2
5
6

CS#
SO
WP#
GND

CE56
1U_0603_10V6K

1
2
3
4

+5VS_KBL
@
FE1
0.75A_24V_1812L075-24DR~OK
2
1

1

SPI_FSEL#
SPI_SO

+5VS_KBL

D

CE57
10U_0603_6.3V6M

RE52 1 KB930@ 2 0_0402_5%
FRD#
2
1
RE53
KB930@
0_0402_5%

2

2

+5VS
FSEL#
FRD#

RE68
10K_0402_5%

UE4
<24>
<24>

@
1

KB_DET#

1

2

<17>

CE52
0.1U_0402_16V7K
KB930@

3

1

C

Screw Hole
H1
B

Lid Switch

1

H_3P3X4P3N
@

B

ZZZ1

H2
H_3P3N
@
1

+3VALW

PCB-MB

RE57
10K_0402_5%

2

2

OUTPUT

2

UE5

LID_SW#

3

LID_SW# <24,32>

H23
H_2P8
@

H24
H_2P8
@

H_2P8
@

INS@
S-5712ACDL1-M3T1U_SOT23-3

1

1

H22
H_2P8
@

1

H21
H_2P8
@

1

H20
H_2P8
@

1

H19
H_2P8
@

GND

1

H17
H_2P8
@

H_3P7
@

1

H16
H_2P8
@

H14
H_3P7
@

1

1

1
H15
H_2P8
@

H10
H_3P7
@

1

1

1

H13
H_2P8
@

H9
H_3P7
@

1

H12
H_2P8
@

1

H11

H8
H_3P7
@

1

1

1

H7
H_3P7
@

1

H6
H_3P7
@

1

VDD

1

1
H5

INS@

CE54
0.1U_0402_16V7K

H_3P5
@

1

DA80000R900

H4
H_3P5
@

1

1

H3

2

CE55
0.1U_0402_16V7K
INS@

A

A

FD4
@ FIDUCIAL

1

1

FD2
FD3
@ FIDUCIAL @ FIDUCAL

1

1

FD1
@ FIDUCAL

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

CONN & LID
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

26

of

56

A

B

C

+5VALW to +5VS

2
1

2

CZ6
10U_0805_10V6K

1
1
3
2

1

@
RZ17
100K_0402_5%

1

2

@

1

3

2

RZ19
100K_0402_5%
SYSON#

RZ21

1
+VCCP

+3V_PCH

+3VS

RZ22
100K_0402_5%
2

RZ26

1

S

QZ12
SSM3K7002F_SC59-3

2

@

RZ27

470_0402_5%

470_0402_5%

D
QZ15
S SSM3K7002FU_SC70-3

2
G

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1
SYSON#

3

3
5
4

SUSP

2N7002DW-7-F_SOT363-6

6
1

PCH_PWR_EN# 2

2N7002DW-7-F_SOT363-6

3
4

6
1

2N7002DW-7-F_SOT363-6

5

QZ14B

+1.5V_D

4

SUSP

QZ14A

+3VS_D

2

QZ13B

+3V_D

SUSP

+VCCP_D

+1.5VS_D
QZ13A

2N7002DW-7-F_SOT363-6

2

2

470_0402_5%

2

2

1

RZ25

470_0402_5%

1

RZ24

470_0402_5%

2

RZ23

1

1

+1.5V

D

2
G

<24,28,48> SYSON

+1.5VS

1

2

1

2M_0402_5%~D

2

1

3

4
1

1

2

1

CZ21
0.1U_0603_50V_X7R

3

1

2

1
2

QZ10
SSM3K7002F_SC59-3

+5VALW
0.1U_0402_16V7K

0_0402_5%

CZ20
0.1U_0603_50V_X7R

QZ11
S SSM3K7002FU_SC70-3

CZ18

RZ20
D

2
G

S

+1.5VS
SI4634DY-T1-E3_SO8~D
8
1
7
2
6
3
5

CZ19
10U_0805_10V6K

RZ18
100K_0402_5%

SUSP

D

2
G

<24> PCH_PWR_EN

UZ1
+1.5V

3

1

<19> PCH_PWR_EN#

@

3

PCH_PWR_EN#

2

2

2

RZ12
100K_0402_5%
1

1
1

RZ16
100K_0402_5%

RZ11
10K_0402_5%

QZ8
SSM3K7002F_SC59-3

+1.5V To +1.5VS
B+_BIAS

2

1

2
S

CZ17
0.1U_0603_50V_X7R

1

2

QZ9
SSM3K7002F_SC59-3
2
RZ15

1.5M_0402_5%~D

1
3

S

2
G

D

2
G

CZ16
0.1U_0603_50V_X7R

CZ15
0.1U_0603_50V_X7R

SUSP

D

+5VALW

RZ10
100K_0402_5%

<10,24,28,46,47,48> SUSP#

39.2K_0402_1%
1

2

+3VALW

CZ14
1U_0603_10V6K
SUSP

1
2
RZ13
470K_0402_5%

S

2

2

RZ14
B+_BIAS

S

D

2
G

1

1
CZ13
10U_0805_10V6K

1

1

2

RZ9
1

S

D

2
G

<6,10> RUN_ON_CPU1.5VS3#

+5VALW

3

1
2
3

1

QZ4
SSM3K7002F_SC59-3
2

1.5M_0402_5%~D

0_0402_5%

D

2
G
3

+3VS

4

2

QZ7
SI4128DY-T1-GE3_SO8

CZ12
10U_0805_10V6K

CZ8
1U_0603_10V6K

QZ6
SSM3K7002FU_SC70-3~D

2

1
CZ11
10U_0805_10V6K

2

RZ8
1
2
RZ7
470K_0402_5%

B+_BIAS

RZ2
22_0603_5%~D

1
CZ7
10U_0805_10V6K

QZ5
SSM3K7002FU_SC70-3~D

1
2

1

2

1

RZ3
220_0402_5%

DMN66D0LDW-7_SOT363-6

+3VALW to +3VS

8
7
6
5

40mil

1
2
3

2

1
CZ5
10U_0805_10V6K

2

SUSP

8
7
6
5

PCH_PWR_EN#

+3VALW

+0.75VS

+3V_PCH

1

6
2
1

RZ6

+1.5V_CPU_VDDQ

CZ10
0.1U_0603_50V_X7R

4

QZ2A

1.5M_0402_5%~D

2

5

2

+DDR_CHG

3

1

2

2

+1.5V_CPU_VDDQ_CHG

QZ2B
SUSP

DMN66D0LDW-7_SOT363-6

1

CZ9
0.1U_0603_50V_X7R

0_0402_5%

@

1

QZ3
SI4128DY-T1-GE3_SO8

+5VS_D

RZ5
1
2
RZ4
470K_0402_5%

B+_BIAS

JP2

JUMP_43X79

3

1

2

1
RZ1
470_0603_5%

1

2

1

CZ4

2

1

4

CZ3

CZ2
10U_0805_10V6K

4

2

+3VALW

1
2
3

1

1
CZ1
10U_0805_10V6K

+3VALW to +3V_PCH

1U_0603_10V6K

2

8
7
6
5

E

+5VS

10U_0805_10V6K

1

QZ1
SI4128DY-T1-GE3_SO8

1

+5VALW

D

2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DC/DC Interface
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
E

27

of

56

5

4

3

2

1

USB Detected for PWR Share
+RTCVCC

+RTCVCC

+RTCVCC

+RTCVCC

+RTCVCC

Express Card

+CHGRTC

5
1
2

NC
A

<24,25>
Y

2

EC_ON

1

4

PCIE_WAKE#

<15,24,32> PCIE_WAKE#

EC_ON_35V <45>

3

+3.3V_CARDAUX

CARD_RESET#

G

1

PCH_SMBCLK
PCH_SMBDATA

<6,11,12,14,29,32> PCH_SMBCLK
<6,11,12,14,29,32> PCH_SMBDATA
+1.5V_CARD

D5

2.2U_0603_6.3V6K

+3.3V_CARD

BAV70W-7-F_SOT323-3
1

3

U1

<14> CLK_PCIE_EXP#
<14> CLK_PCIE_EXP
CX12EXP@
1
CX13EXP@
1

<14> PCIE_PRX_EXPTX_N3
<14> PCIE_PRX_EXPTX_P3
USB_DETECT#

2

1

C

USB_DETECT# <33>

1

EXPCLK_REQ#
EXPRCRD_CPPE#
CLK_PCIE_EXP#
CLK_PCIE_EXP

<14> EXPCLK_REQ#

R780
1M_0402_5%
2

TC7SZ14FU_SSOP5~D

1
R781

USB_DET#_DELAY
2
0_0402_5%

D4
SDMK0340L-7-F

1

C13
0.1U_0402_16V7K

2

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

<14> PCIE_PTX_EXPRX_N3
<14> PCIE_PTX_EXPRX_P3

USB_DET#_DELAY <24>

C14
0.1U_0402_16V7K

LX1

2

1

1
RX6 @
1
RX7

<10,24,27,46,47,48> SUSP#
<15,24> PM_SLP_S3#

2
0_0402_5%
2
0_0402_5%

SHDN#
STBY#
SYSRST#
OC#

PERST#
CPPE#
CPUSB#

8
10
9

SYSON_R

NC
NC
NC
NC
NC

RCLKEN

18

GND
PAD

7
21

4

3

3

EXP_USBP11_D+

2

B

+3.3V_CARD

+1.5V_CARD

500mA
CARD_RESET#
EXPRCRD_CPPE#
CPUSB#

EXP@ 1

2

+3.3V_CARDAUX

1

2

EXP@

1

+3VS

EXP@
2

EXP@
1

+3VS

EXP@

EXP@

2
PCH_SMBCLK
PCH_SMBDATA

TPS2231MRGPR-2_QFN20_4X4~D
EXP@

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

STBY#_R

2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

2
0_0402_5%

RX5
2.2K_0402_5%

RX8

20
1
6
19

4

RX4
2.2K_0402_5%

<24,27,48> SYSON

15
3
11

USB20_P11

USB20_P11

0.1U_0402_25V6K
CX1

A

2
0_0402_5%

AUXOUT
3.3VOUT
1.5VOUT

4
5
13
14
16

+3VS
+3.3V_CARD
+1.5V_CARD
+1.5VS
1

AUXIN
3.3VIN
1.5VIN

<16>

EXP@

CX11
10U_0603_6.3V6M

SYSON_R
STBY#_R
PLT_RST#

17
2
12

EXP_USBP11_D-

1
RX3 @

CX10
0.1U_0402_25V6K

<6,16,24,32> PLT_RST#

EXP@

2

0.1U_0402_25V6K
CX2

EXP@

2

2

2

EXP@ EXP@ 1

UX1
EXP@

1

DLW21SN900SQ2_0805~D
1
2
RX2 @
0_0402_5%

CX9
10U_0603_6.3V6M

2

1

CX8
0.1U_0402_25V6K

2

EXP@ 1

EXP@

1

1A
CX7
10U_0603_6.3V6M

1

C

USB20_N11

+3.3V_CARD

275mA
CX6
0.1U_0402_25V6K

2

+3.3V_CARDAUX

275mA
CX5
0.1U_0402_25V6K

2

1

CX4
0.1U_0402_25V6K

1

CX3
0.1U_0402_25V6K

B

+3VALW

1A

D

<16> USB20_N11

1

+3VS

500mA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
GND
TYCO_2-2041070-6~D
CONN@

2

Express Card PWR S/W
+1.5VS

PCIE_PRX_EXPTX_N3_C
PCIE_PRX_EXPTX_P3_C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

2

C4

@

2 CLOSE TO U1

P

2

D3

C3
0.1U_0402_16V7K

EXP_USBP11_DEXP_USBP11_D+
CPUSB#

2
0_0402_5%

1

1

1
2

2

R779

2

1

SDMK0340L-7-F

R778
100K_0402_5%

220K_0402_5%

D

1

JEXP
1
R787

4

3

2

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

28

of

56

A

B

C

D

E

F

G

H

+3VS
JP6

SATA HDD Conn.

+3.3V_RUN_FFS

JHDD
UN1

11
9

INT 1
INT 2

7
6
4

<6,11,12,14,28,32> PCH_SMBDATA
<6,11,12,14,28,32> PCH_SMBCLK

8

RES
RES
RES
RES

GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC

<13> SATA_PTX_DRX_P0_C
<13> SATA_PTX_DRX_N0_C

10
13
15
16
5
12

1

1

1
2

2
3
4

6

@

1

2

@

1

2

+5V_HDD

+5VS
@ JP13
1 1

@

1

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

2

SUYIN_127043FB022G208ZR_RV
CONN@

2

JUMP_43X79

SHORT DEFAULT

+3VS

2

1
CN9
2

1
CN5
2

1
CN6
2

1
CN7
2

10U_0805_10V6K

1
CN8

+5V_HDD
0.1U_0402_25V6K

RN11
100K_0402_5%

1000P_0402_50V7K

1

S

0.1U_0402_25V6K

2

SI3456DDV-T1-GE3_TSOP6~D

3

0.1U_0402_25V6K

@ RN12
100K_0402_5%

QN4

CN18
10U_0805_10V6K

2

<24> HDD_S3.5

@

HDD_EN_5V

CN17
0.1U_0603_50V_X7R

1

D

5
@

FFS_INT2_Q

@

G
QN5B
DMN66D0LDW-7_SOT363-6

2

1 FFS@ 2 PCH_SMBDATA
RN3
10K_0402_5%
1 FFS@ 2 PCH_SMBCLK
RN4
10K_0402_5%
1 FFS@ 2 FFS_INT1
RN5
100K_0402_5%

RN9
100K_0402_5%

@
RN10
100K_0402_5%

@

HDD_DET#

<13> HDD_DET#
+5V_HDD

QN5A
DMN66D0LDW-7_SOT363-6

QN1A
DMN66D0LDW-7_SOT363-6

FFS@

2

+3VS

FFS@

5

FFS_INT2

FFS_INT2_Q

+5VALW

B+_BIAS

GND
A+
AGND
BB+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+3VALW

QN1B
DMN66D0LDW-7_SOT363-6

FFS@
RN2
100K_0402_5%

SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+5V_HDD Source

@ RN1
100K_0402_5%

2

1

+3VS

1
1

2
3

LNG3DMTR_LGA16_3X3~D
FFS@

+5V_HDD

CN3
CN4

<13> SATA_PRX_DTX_N0
<13> SATA_PRX_DTX_P0

1

VDD_IO
VDD

1
2
3
4
5
6
7

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C

2

<16> FFS_INT1
<17> FFS_INT2

1
14

1
2
5
6

LNG3DM

1

4

2

2

1

3

2

FFS@
CN2

4

1

0.1U_0402_25V6K

FFS@
CN1

10U_0603_6.3V6M

@

6

2
PAD-OPEN1x1m

1

1

2

SATA ODD Conn.
ODD Power Control

+5VS_ODD

Pleace near ODD CONN

2

1

2

JUMP_43X79

2

+5VS

2

1

D

RN6
470K_0402_5%

2
CN14 2
CN15

1
1 0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PRX_DTX_N2_C
SATA_PRX_DTX_P2_C

8
9
10
11
12
13

<17> ODD_DETECT#
ODD_DA#_R
2
0_0402_1%

1
RN8

<16> ODD_DA#

ODD_EN

RN7

4

1
CN16
2

GND
RX+
RXGND
TXTX+
GND
DP
+5V
+5V
MD
GND
GND

Issued Date

Compal Electronics, Inc.

Compal Secret Data
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

C

14
15

4

Security Classification

A

GND1
GND2

TYCO_2-1759838-8~D
CONN@

0.1U_0402_25V6K

QN3
SSM3K7002FU_SC70-3

1.5M_0402_5%~D

2

S

2
G

1

ODD_EN#

1
<17>

3

@
D

2

3

S

<13> SATA_PRX_DTX_N2
<13> SATA_PRX_DTX_P2

1
2
3
4
5
6
7

SATA_PTX_DRX_P2_C
SATA_PTX_DRX_N2_C

<13> SATA_PTX_DRX_P2_C
<13> SATA_PTX_DRX_N2_C

SI3456BDV-T1-E3 1N TSOP6

2

B+_BIAS

2

1

JODD

4

G

CN13

6
5
2
1

+5VS_ODD

3

1

1U_0402_6.3V6K

QN2

1

CN12
10U_0805_10V6K

JP7

1

CN11
0.1U_0402_25V6K

@
1

CN10
1000P_0402_50V7K

3

D

E

F

HDD/ODD/FAN

Wednesday, February 01, 2012

G

Rev
1.0

LA-8241P
Sheet

29
H

of

56

4

3

LEFT+
LEFT-

2

2 20K_0402_1% MIC1_PLUG
2 39.2K_0402_1% HP_PLUG

GNDA

+3VS

+MICBIASB

1
2
CA21 1000P_0402_50V7K

C_BIAS
PORTC_R
PORTC_L

32
31
30

2

3
1

GNDA
SINGA_2SJ3013-010311F
CONN@

GNDA

HeadPhone JACK

AMP_RIGHT
AMP_LEFT

PORTA_R
PORTA_L

23
22

RA12 1
RA13 1

NC
NC

24
25

AVEE
FLY_P
FLY_N

21
19
20

AMP_RIGHT <31>
AMP_LEFT <31>

2 39.2_0402_1%
2 39.2_0402_1%

OUTPUT 1Vrms

HPL
HPR

RIGHT+
RIGHT-

2
1U_0603_10V6K
CA27
@

CX20672-21Z_QFN40_6X6

1

1

2

Close to UA1
Pin11,13,14,16
SPK_R1SPK_R2+
SPK_L1SPK_L2+

LA3
LA4
LA5
LA6

1
1
1
1

2
2
2
2

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

CA22
@

GNDA

1

2

CA23

GNDA

GNDA
SINGA_2SJ3013-010311F
CONN@

GNDA

JSPK

1000P_0402_50V7K

2

ACES_87213-0400G
CONN@

@

+5VS

HDA_SYNC_AUDIO

0.1U_0402_16V7K

1

HDA_BITCLK_AUDIO
@

2

RA19
10K_0402_5%

2

CA34
10P_0402_50V8J

HDA_SDOUT_AUDIO

1

2

RA18
10_0402_1%
@

RA17
4.7K_0402_5%

@

HDA_RST_AUDIO#

1
2
CA39
1
2 @

1

A

1
CA36
10P_0402_50V8J
@

@

2

@
CA38
10P_0402_50V8J

CA37
0.1U_0402_16V7K

2
A

0.1U_0402_16V7K
CA40
1
2 @

for EMI

0.1U_0402_16V7K

GNDA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GND

2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

B

SPK_R1-_CONN

<31> SPK_R1-_CONN

BAT54C-7-F_SOT23-3

PC Beep

@

1

1000P_0402_50V7K
CA32

1000P_0402_50V7K
CA31

CA29

1000P_0402_50V7K
CA30

2

1

5
6

1

3

2

1

1
2
3 GND
4 GND

2

HDA_SPKR

1

ICH Beep<13>

PC_BEEP

1

DA6
PESD5V0U2BT_SOT23-3

1

DA5
PESD5V0U2BT_SOT23-3

CA41
1
2

1

C

SPK_R2+_CONN

<31> SPK_R2+_CONN

2

9

1
2
3
4

SPK_L1-_CONN

<31> SPK_L1-_CONN

G

close to Codec

2

DA7

8

6

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

SPK_L2+_CONN

<31> SPK_L2+_CONN

7

G

5

3

2

1
CA28

G

2

4

HP_R
HP_L

2

1
CA26

1

3

HP_PLUG

wide 30MIL

BEEP#

9

5

GNDA

LA1
1
2
FBMA-L10-160808-800LMT_2P
LA2
1
2
FBMA-L10-160808-800LMT_2P

HP_L
HP_R

@

B

EC Beep <24>

G

D

JHP
MIC1_R
MIC1_L

2 4.7U_0603_6.3V6K
2 4.7U_0603_6.3V6K

@

41

2

3

CA14

10U_0603_6.3V6M

CA5

2 5.11K_0402_1%

RA8
RA9

2

1

AVDD_5V

CA20 1
CA19 1

RA6

1
1

6

2

11
13

0.1U_0402_16V7K

0.1U_0402_16V7K

CA12

DMIC_CLK
DMIC_1/2

16
14

35
34
33

GND

2

SPK_R2+
SPK_R1-

PORTB_R
PORTB_L
B_BIAS

1

8

3

SPK_L2+
SPK_L1-

40
1

Internal SPEAKER

SENSE_A

7

G

1

1

36

1
CA17 @ CA18

10P_0402_50V8J

2

@ CA25 15P_0402_50V8J

@ CA24 15P_0402_50V8J

1

GPIO0/EAPD#
GPIO1/SPK_MUTE#

1

10P_0402_50V8J

RA15 2 33_0402_5%
RA14 2 0_0402_5%

Reserve for EMI

38
37

0_0402_5%

SENSE_A

PC_BEEP
SPDIF

@

2

0_0402_5%

12
15
17

G

2

4

2

LPW R_5.0
RPW R_5.0
CLASS-D_REF

1

3

28

29
27

3
7
2
18
26

Vendor

39

MIC1_R_R

DA3
PESD5V0U2BT_SOT23-3

@
RA10 2
1
RA11

10

1 RA4
2
100_0402_1%

2

1
2

<24,31>
EAPD
<24> EC_MUTE#

1
1

recommend
BIT_CLK
SYNC
VDD_IO is
SDATA_IN the same
SDATA_OUT

MIC1_R

3

PC_BEEP

MIC_CLK
MIC_DATA

RESET#

5
8
6
4

with HDA

C

<22>
<22>

9

MIC1_L_R

1

2 0_0402_5%
HDA_SYNC_AUDIO
RA5 2 33_0402_5%
HDA_SDOUT_AUDIO

1 RA3
2
100_0402_1%

MIC1_PLUG

4.7U_0603_6.3V6K

1

RA7

2

JMIC

MIC1_L

Please bypass caps very close to device.

0.1U_0402_16V7K

1

<13> HDA_BITCLK_AUDIO
<13> HDA_SYNC_AUDIO
<13> HDA_SDIN0
<13> HDA_SDOUT_AUDIO

FILT_1.65
AVDD_3.3

HDA_RST_AUDIO#

<13> HDA_RST_AUDIO#

UA1

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3
AVDD_HP

0.1U_0402_16V7K

CA16

2

2

1

220P_0402_50V8J

2

1

2

2

1

220P_0402_50V8J

CA15

1

2

2
1

1

MIC JACK

DA2
PESD5V0U2BT_SOT23-3

2

4.7U_0603_6.3V6K

1

+FILT_1.8V

1

1

RA2

DA1
PESD5V0U2BT_SOT23-3

CA13

2

+VDD_IO
0.1U_0402_16V7K

1

0.1U_0402_16V7K

2

+5VS

CA11

2

1

0.1U_0402_16V7K

CA9

1

4.7U_0603_6.3V6K
CA10

+3VS

10U_0603_6.3V6M
CA8

D

1

1
RA1
+5VS
0.1U_0402_16V7K
CA7

2

AVDD_3.3 pinis output of
internal LDO. NOT connect
to external supply.

0.1U_0402_16V7K
CA6

CA3

2

1

0.1U_0402_16V7K

2

1

4.7U_0603_6.3V6K
CA4

2

1

CA2

RA23 2 0_0402_5%

0.1U_0402_16V7K

1

1

CA1

@
RA22 2 0_0402_5%

+MICBIASB

+LDO_OUT_3.3V

3.3K_0402_5%

1

1

3.3K_0402_5%

+3V_PCH

1U_0603_10V6K

+FILT_1.65V

2

2

5

4

3

2

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

30

of

56

5

4

UA2

2
2

240K_0402_1%

Need final turn R/C
10/24

2

AMP@

@

GIN0

@
RA35
100K_0402_1%

AMP@

0

20dB

60Kohm

GIN1

0

1

26dB

30Kohm

RA36
100K_0402_1%

1

0

32dB

15Kohm

1

1

36dB

9Kohm

1

1

RA34
100K_0402_1%

0

GAIN0

OUTPR

17

BSPR

1

2

CA54
0.22U_0603_25V7K
CA55
0.22U_0603_25V7K

AMP@

OUTNR

20

BSNR

21

OUTNR

OUTNL
+GVDD

BSNR

1

CA56
0.22U_0603_25V7K
5

GAIN0

PBTL

14

GIN1

6

GAIN1

PLIMIT

10

PLIMIT

EAPD_R

1

SD#

GVDD

9

+GVDD

PGND
PGND
AGND

24
19
8

RA26
100K_0402_5%
AMP@

FAULT#

13
29

NC
GND

SPK_L1-_CONN

SPK_L1-_CONN <30>

5A/120ohm/100MHz
AMP@

RA27
28.7K_0402_1%
AMP@

AMP@

GIN0

LA8
HCB2012KF-121T50_0805
1
2

2

AMP@

2

Close to LA5

OUTPR

18

RINP

2

2

@
RA33
100K_0402_1%

2 1

2
2 1

C

AV(inv)

INPUT
IMPEDANCE

2

+GVDD
CA57
1U_0603_25V6K

+5VS

1

CA52

AMP@

GAIN1

BSPR

2
11
0.027U_0402_16V6K RINN

RA25
0_0402_5%
1
2

EAPD

BSNL

D

AMP@

OUTNL

CA58
1U_0603_25V6K

<24,30>

1

RA24
100K_0402_5%
@
1
2

+3VALW

TPA3113 for Speaker

2
4
0.027U_0402_16V6K LINN

CA51
1
2 0.027U_0402_16V6K AMP_RIGHT_C 12
RA40
10K_0402_5%
AMP@

22

SPK_L2+_CONN <30>

1

1

BSNL

SPK_L2+_CONN

5A/120ohm/100MHz

2

AMP_RIGHT

23

AMP@

AMP@

1

RA39

1

OUTNL

OUTPL

LA7
HCB2012KF-121T50_0805
1
2

OUTPL

AMP@

LINP

CA50

@

25

1

RA38
10K_0402_5%
AMP@

AMP@

3

OUTPL

BSPL

2

240K_0402_1%

<30> AMP_RIGHT

CA49
1
2 0.027U_0402_16V6K AMP_LEFT_C

26

1

1

BSPL
PVCCR
PVCCR
PVCCL
PVCCL

2

AMP_LEFT

<30> AMP_LEFT

AMP@ AMP@
RA37
2

1

AMP@

1

AMP@

AVCC

TPA3113D2PWPR_HTSSOP28

Close to LA4

1

7
15
16
27
28

CA53
0.22U_0603_25V7K
1
2

RA28
10K_0402_1%
OUTPR

LA10
HCB2012KF-121T50_0805
1
2

SPK_R2+_CONN

SPK_R2+_CONN <30>

5A/120ohm/100MHz

2

+PVDD

Close to UA2
Pin7,15,16,27,28
AMP@

1

Close to LA6

1U_0603_25V6K
CA46

1U_0603_25V6K
CA45
2
1

1

Close to LA9

D

2

40mil

+PVDD
1U_0603_25V6K
CA48
2
1

2

CA43
0.1U_0402_16V7K
2 AMP@

AMP@

1U_0603_25V6K
CA47
2
1

1

2

CA42
10U_1206_25V6M
AMP@

1

1U_0603_25V6K
CA44
2
1

LA9
FBMA-L11-160808-121LMA30T_0805
1
2

B+

3

AMP@

AMP@
C

AMP@

AMP@

AMP@

Close to LA3
OUTNR

LA11
HCB2012KF-121T50_0805
1
2

SPK_R1-_CONN

SPK_R1-_CONN <30>

5A/120ohm/100MHz

AMP@
AMP@

+1.8VGS

+VCCP

+3VALW

+3VLP

2

C7
2

1
0.1U_0402_16V7K

C6

1 GCLK@
0.1U_0402_16V7K

1
0.1U_0402_16V7K

0.1U_0402_16V7K

Depop if GCLK
with UMA

1 GCLK@

C8
2

+RTCVCC

2

GCLK@
GCLK@
22U_0805_6.3V6M

C9
2

10
15

+3VLP

1

U2

2

VBAT

VDD_RTC_OUT

14

2

+V3.3A
VDD
32kHz

2.2U_0603_6.3V6K
C10

GCLK@

+RTCBATT

C5
1

B

9

B

GCLK@

PCH_RTCX1_R <13>
GCLK@

2

3
GND

C11
33P_0402_50V8K 2
GCLK@

3

+VCCP

3

CLK_X2

GND

1

4
GCLK@

2

CLK_X1
CLK_X2
C12
33P_0402_50V8K
GCLK@

1
16

VDDIO_27M

27MHz

VDDIO_25M_A

25MHz_A

VDDIO_25M_B

25MHz_B

XTAL_IN
XTAL_OUT

SLG3NB274VTR_TQFN16_2X3

6
5

VGA_X1_R1

2 R785
33_0402_5%
LAN_X1_R 1 GCLK@ 2 R782
33_0402_5%
PCH_X1_R1
2 R783
0_0402_5%

VGA_X1 <35>
LAN_X1 <14>
PCH_X1 <14>

GCLK@
GND4

1

8

12

17

1

1

+3VALW

GND1
GND2
GND3

CLK_X1

11

4
7
13

Y1
25MHZ_20PF_7V25000016

+1.8VGS

GCLK@
LAN_X1_R

1

R784
0_0402_5%
2
@

UMA only

A

reserved for swing level adjustment
(close to U2)

U2

SLG3NB244VTR_TQFN16_2X3
@

Compal Secret Data

Security Classification
Issued Date

A

2012/01/17

2013/01/16

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

AMP
Rev
1.0

LA-8241P

Wednesday, February 01, 2012

Sheet
1

31

of

56

5

4

0_0402_1%
1 R771
2
1 R772
2
@ 0_0402_1%

<16>
<16>

USB3TP3
USB3TN3

@
1
1
@

<16> USB3RP4
<16> USB3RN4
<16>
<16>

D

USB3RP3_R
USB3RN3_R

0_0402_1%
R775
2 USB3RP4_R
R776
2 USB3RN4_R
0_0402_1%

USB3TP4
USB3TN4

<16> USB20_P2
<16> USB20_N2
<16> USB20_P3
<16> USB20_N3
<16> USB20_P4
<16> USB20_N4
<16> USB20_P5
<16> USB20_N5
+3VS
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

<13> SATA_PRX_DTX_P1
<13> SATA_PRX_DTX_N1

SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C

<13> SATA_PTX_DRX_P1_C
<13> SATA_PTX_DRX_N1_C

2

1

JBTB1

@
<16> USB3RP3
<16> USB3RN3

3

+1.5VS
<24> WLAN_WAKE#
+3VS

+5VALW
C

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79

81

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

GND

82

USB_OC2# <16>
USB_OC3# <16>
BT_ON# <17>
WL_OFF# <16>
USB_EN# <24,33>
PCIE_WAKE# <15,24,28>
WLAN_CLKREQ# <14>
PLT_RST# <6,16,24,28>
LAN_CLKREQ# <14>
WOL_EN# <24>
AOAC_ON <24>
EC_TX <24>
EC_RX <24>
PCH_SMBCLK <6,11,12,14,28,29>
PCH_SMBDATA <6,11,12,14,28,29>
HDD_DETECT# <17>
B+_BIAS
+3VALW

D

PCIE_PRX_WLANTX_P2 <14>
PCIE_PRX_WLANTX_N2 <14>
PCIE_PTX_WLANRX_P2 <14>
PCIE_PTX_WLANRX_N2 <14>

To CardReader/B

<---WLAN (Mini Card 1)

* Inspiron only

CLK_PCIE_WLAN <14>
CLK_PCIE_WLAN# <14>

+3VS

PCIE_PTX_LANRX_P1 <14>
PCIE_PTX_LANRX_N1 <14>

JCR1

PCIE_PRX_LANTX_P1 <14>
PCIE_PRX_LANTX_N1 <14>

1
2
3
4

USB20_N10_R
USB20_P10_R

<---10/100/1G LAN

CLK_PCIE_LAN <14>
CLK_PCIE_LAN# <14>
LID_SW# <24,26>
CLK_LAN_25M <14>

1
2
3
4

G1
G2

5
6

ACES_50504-0040N-001
CONN@
C

DLW21SN900SQ2_0805~D
<16> USB20_N10
ACES_88079-0800A1
CONN@

<16>

TO Function/B

USB20_P10

USB20_N10

1

USB20_P10

4

JFC
<24> DASH_SW1
<25> DASH_SW2
<24> DASH_SW3

To Finger Print

1
2
3
4
5
6
7
8

+DAS_PWR

<24> DASH_LED1#
<24> DASH_LED2#
<24> DASH_LED3#

+3VS
2
C1
0.1U_0402_25V6K

3
7
8

To LED/B
10mils, All pins

1
3

1

1
2
3
4
5
6
7
8

+5VS
PCH_SATALED#
BATT_CHG_LED#
BATT_LOW_LED#
WL_BT_LED#

2
0_0402_5%

USB10P

B

2
G
S

2

1
2
3
4
5
6
7
8

G1
G2

9
10

1
2
3
4

USB10N_R
USB10P_R

DASH_LED_PWM <24>
Q3
SSM3K7002FU_SC70-3~D

1
2
3
4
5
6
7
8

G1
G2

G1
G2

5
6

ACES_50504-0040N-001
CONN@

L2

1
2
3
4
5
6
7
8

1
2
3
4

USB10N

1

USB10P

4

VOS@

1

2

4

3

2

USB10N_R

3

USB10P_R

DLW21SN900SQ2_0805~D
1
2
R8 @
0_0402_5%

9
10

1
R7 @

2
0_0402_5%

ACES_51524-0080N-001
CONN@

A

ACES_51524-0080N-001
CONN@

Q1
S

1
R10 VOS@

JCR2
D

1

+5VS
PWR_LED#
PCH_SATALED#
BATT_CHG_LED#
BATT_LOW_LED#
WL_BT_LED#

JLED

D

2
G

USB10N

+3VS

+5VALW

+5VALW

<24> PWR_PWM_LED#

2
0_0402_5%

* Vostro only

JLED2

A

2
0_0402_5%

1
R9 VOS@

1

C2
0.1U_0402_16V7K

<13>
<24>
<24>
<24>

1
R2 @

To CardReader/B

1

1

2
10K_0402_5%

PWR_LED#

USB20_P10_R

R777

ACES_51524-0060N-001
CONN@

<25> PWR_LED#

2

3 3
INS@
2
0_0402_5%

2

2
1

@

D6
PESD5V0U2BT_SOT23-3

3

B

1
2
3
4
5 G1
6 G2

Q2
AP2301GN-HF_SOT23-3

+5VS

JFP
1
2
3
4
5
6

USB20_P8
USB20_N8

9
10

G1
G2

2

4
L1
1
R1 @

ACES_51524-0080N-001
CONN@

3

1

<16>
<16>

1
2
3
4
5
6
7
8

1

USB20_N10_R

2N7002_SOT23

R786
100K_0402_5%
2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

32

of

56

5

4

3

2

1

+5VALW

LI1
1

1

2

2

USB3RN1_R

USB3RP1

4

4

3

3

USB3RP1_R

CI12
4.7U_0805_10V4Z

1

1

2

2

CI14

1
2
3
4

USB_EN#

<24,32> USB_EN#

1

USB3TN1

<16>

USB3TP1

USB3TP1
2
CI4

1

1 USB3TP1_C
0.01U_0402_16V7K

4

1

2

4

3

2

USB3TN1_R

3

USB3TP1_R

2

DLW21SN900HQ2L_0805_4P~D
1
2
0_0402_5%

CI13

VOUT
VOUT
VOUT
FLG

<16>

USB20_N0

USB20_P0

1

USB20_N0

4

1

2

2

4

3

3

1

220U_6.3V_M

USB3RP1_R

1

10

USB3RP1_R

USB3RN1_R

2

9

USB3RN1_R

USB3TP1_R

4

7

USB3TP1_R

USB3TN1_R

5

6

USB3TN1_R

USB20_P0_R

1

+

CI1

2

2

USB20_N0_R

9
1
8
3
7
2
6
4
5

USB3TN1_R
USB20_P0_R

3
8

DLW21SN900SQ2L_0805_4P~D
1
2
@ RI3
0_0402_5%
C

JUSB1

DI1

1

+5V_USB_PWR1

0.1U_0402_16V7K

USB3TP1_R

2
0_0402_5%

D

CI15

AP2301MPG-13_MSOP8

1

USB20_P0

1

2

LI2
<16>

USB conn.1

USB_OC0# <16>

@

USB20_N0_R
USB3RP1_R
DI2
PESD5V0U2BT_SOT23-3

1

0_0402_1%
1
2
RI19

@ RI4
@ RI6

80mil

CI2
0.1U_0402_25V6K

<16>

1 USB3TN1_C
0.01U_0402_16V7K

0.1U_0402_16V7K

LI3
USB3TN1
2
CI3

GND
VIN
VIN
EN

8
7
6
5

2

2
0_0402_5%

@ RI2

+5V_USB_PWR1

UI3

9

1

D

2.0A

0.1U_0402_16V7K

DLW21SN900HQ2L_0805_4P~D
1
2
@ RI1
0_0402_5%

3

<16> USB3RP1

USB3RN1

EPAD

<16> USB3RN1

USB3RN1_R

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

TAITW_PUBAU1-09FNLSCNN4H0
CONN@

IP4292CZ10-TB_XSON10U10~D

2
0_0402_5%

@ RI5

C

+5VALW

+5VALW

2

+5VALW

10K_0402_5%

1

PWRSHARE_EN

2
D

S

2
G
2

2

CI7

2.0A

0.1U_0402_16V7K

1
2
3
4

PWRSHARE_EN#

DI3
B

2

1

SDMK0340L-7-F_SOD323-2~D

QI1
SSM3K7002FU_SC70-3~D

CI5
0.1U_0402_25V6K

1

+5V_USB_PWR2

UI2

RI8
10K_0402_5%

RI12
10K_0402_5%

1

1

GND
VIN
VIN
EN

EPAD

1

@

SLG55584AVTR_TDFN8_2X2

2

RI10

CI6
4.7U_0805_10V4Z

9

USB20_N1_SW
USB20_P1_SW
SEL

+3VALW

1

CEN
DM
DP
SELCDP
Thermal Pad

PWRSHARE_EN

3

+5VALW

CB
TDM
TDP
VDD

1
2
3
4
9

1

USB20_N1
USB20_P1

SB# 8
7
6
5

2

<16>
<16>

2 0_0402_5%

2

<24> PWRSHARE_OE#

RI7

1

RI11
100K_0402_5%

UI1
1

VOUT
VOUT
VOUT
FLG

80mil

8
7
6
5

0_0402_1%
1
2
RI20

@

USB_OC1# <16>
1

CI17

AP2301MPG-13_MSOP8
2

0.1U_0402_16V7K

B

<24> PWRSHARE_EN_EC#

LI4
1

1

2

2

USB3RN2_R

USB3RP2

4

4

3

3

USB3RP2_R

DLW21SN900HQ2L_0805_4P~D
1
2
@ RI13
0_0402_5%

1

10

USB3RN2_R

USB3RP2_R

2

9

USB3RP2_R

USB3TN2_R

4

7

USB3TN2_R

USB3TP2_R

5

6

USB3TP2_R

<28> USB_DETECT#
+5V_USB_PWR2
JUSB2

2
0_0402_5%

USB3TP2_R

3
1

8

+

CI8

1

IP4292CZ10-TB_XSON10U10~D
LI5
USB20_P1_SW

4

USB20_N1_SW

1

LI6

<16>
A

USB3TN2
USB3TP2

USB3TN2
USB3TP2

2
CI10
2
CI11

1 USB3TN2_C
0.01U_0402_16V7K
1 USB3TP2_C
0.01U_0402_16V7K

1
4

1
4

2
3

2
3

3

3

USB20_P1_R

2

USB20_N1_R

USB3TN2_R
USB3TP2_R

DLW21SN900HQ2L_0805_4P~D
1
2
@ RI17
0_0402_5%
1
@ RI18

4

2

1

2

@

DLW21SN900SQ2L_0805_4P~D
1
2
@ RI15
0_0402_5%
1
@ RI16

1

<16>

2

2
0_0402_5%

USB20_N1_R
USB3RP2_R
USB3RN2_R

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

D1-DP

GND
GND
GND
GND

10

11
12
13
14

TAITW_USB011-107BRL-TW
CONN@

A

2
0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

9
1
8
3
7
2
6
4
5

USB3TN2_R
USB20_P1_R

DI5
PESD5V0U2BT_SOT23-3

220U_6.3V_M

CI9
0.1U_0402_25V6K

1
@ RI14

USB conn.2

DI4
USB3RN2_R

2

<16> USB3RP2

USB3RN2

3

<16> USB3RN2

4

3

2

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

33

of

56

5

4

3

2

1

GFX PCIE LANE REVERSAL
PEG_GTX_C_HRX_P[7..0] <5>
PEG_GTX_C_HRX_N[7..0]

<5>

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

Y33 PCIE_CRX_C_GTX_P0
Y32 PCIE_CRX_C_GTX_N0

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV43 DIS@
1 CV44 DIS@

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33 PCIE_CRX_C_GTX_P1
W32 PCIE_CRX_C_GTX_N1

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV45 DIS@
1 CV46 DIS@

PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33 PCIE_CRX_C_GTX_P2
U32 PCIE_CRX_C_GTX_N2

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV47 DIS@
1 CV48 DIS@

PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30 PCIE_CRX_C_GTX_P3
U29 PCIE_CRX_C_GTX_N3

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV49 DIS@
1 CV50 DIS@

PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33 PCIE_CRX_C_GTX_P4
T32 PCIE_CRX_C_GTX_N4

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV51 DIS@
1 CV52 DIS@

PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30 PCIE_CRX_C_GTX_P5
T29 PCIE_CRX_C_GTX_N5

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV53 DIS@
1 CV54 DIS@

PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

P33 PCIE_CRX_C_GTX_P6
P32 PCIE_CRX_C_GTX_N6

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV55 DIS@
1 CV56 DIS@

PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

P35
N36

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

P30 PCIE_CRX_C_GTX_P7
P29 PCIE_CRX_C_GTX_N7

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV57 DIS@
1 CV58 DIS@

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7

N38
M37

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

N33
N32

M35
L36

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

N30
N29

L38
K37

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

L33
L32

K35
J36

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

L30
L29

J38
H37

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

K33
K32

H35
G36

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

J33
J32

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

B

GPU_RST#

AH16

AK27
AJ27

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK35
AL36

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

TXOUT_L3P
TXOUT_L3N

AN36
AP37

C

THAMES XT M2 @

RV61 2

Chelsea Only

@

1 0_0402_5%

+3VGS

1
2
+1.0VGS
RV198 CH@1.69K_0402_1%~D

PCIE_REFCLKP
PCIE_REFCLKN

PWRGOOD

VARY_BL
DIGON

12/8 Remove CV59~CV74 TX8~15

Thames/seymour Only

PCIE_CALRP

Y30

1.27K_0402_1% 1 DIS@

PCIE_CALRN

Y29

2K_0402_1% 1 DIS@
1K_0402_1% 1 CH@

2 RV65
2 RV203

1

<16> DGPU_HOLD_RST#

2

+1.0VGS
CV326
0.1U_0402_25V6K
DIS@

Install 2K for Thames/Seymour

PERSTB

2

<16> PCH_PLTRST#

2 RV63

1

AA30

LVDS CONTROL

LVTMDP

CALIBRATION

1RV64 DIS@
2
1K_0402_5%

UV1G

B

CLOCK
CLK_PEG_VGA
AB35
CLK_PEG_VGA# AA36

<14> CLK_PEG_VGA
<14> CLK_PEG_VGA#

D

LVDS Interface

5

12/8 Remove RX8~15

PCI EXPRESS INTERFACE

C

PEG_GTX_C_HRX_N[7..0]

B

UV13

P

D

PEG_GTX_C_HRX_P[7..0]

UV1A

PEG_HTX_C_GRX_N[7..0]

<5> PEG_HTX_C_GRX_N[7..0]

Y
A

GPU_RST#

4

G

<5> PEG_HTX_C_GRX_P[7..0]

3

PEG_HTX_C_GRX_P[7..0]

DIS@
MC74VHC1G08DFT2G SC70 5P

1

DIS@
THAMES XT M2 TH@
RV66
100K_0402_5%

2

A

UV1

A

CH@

Issued Date

Chelsea Pro

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

ATI_SeymourXT_M2_PCIE/LVDS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

LA-8241P

Wednesday, February 01, 2012

Sheet
1

34

of

56

4

3

2

1

CONFIGURATION STRAPS

UV1B

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
TXCAP_DPA3P
TXCAM_DPA3N

RSVD

GPIO2

Advertises PCIE speed
when compliance test

0: 2.5GT/s
1: 5GT/s

0

TX3P_DPB2P
TX3M_DPB2N

AV31
AU30

RSVD

GPIO8

RESERVED

0

TX4P_DPB1P
TX4M_DPB1N

AR32
AT31

BIF_VGA DIS

GPIO9

VGA ENABLED

0

AT15
AR14

TX1P_DPC1P
TX1M_DPC1N

AU16
AV15<15,24,43,44>

TX2P_DPC0P
TX2M_DPC0N

AT17
AR16

TXCDP_DPD3P
TXCDM_DPD3N

AU20
AT19

TX3P_DPD2P
TX3M_DPD2N

AT21
AR20

TX4P_DPD1P
TX4M_DPD1N

AU22
AV21

TX5P_DPD0P
TX5M_DPD0N

AT23
AR22

R
RB

AD39
AD37

VGA_CRT_R

G
GB

AE36
AD35

VGA_CRT_G

<21>

B
BB

AF37
AE38

VGA_CRT_B

<21>

HSYNC
VSYNC

AC36
AC38

VGA_CRT_HSYNC
VGA_CRT_VSYNC

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

@

1
1

@
@

1 DIS@
@
1
@
1

RV78 AC_BATT

2
2

RV79 GPU_GPIO8
RV80 GPU_GPIO9

2
2
2

<52>
<52>

GPU_VID0
GPU_VID2
RV89 1 @

<52> GPU_VID1

RV81 GPU_GPIO11
RV82 GPU_GPIO12
RV83 GPU_GPIO13

T78

T79

+3VGS
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

1
1
1

@
@
@

2 RV85
2 RV86
2 RV87

GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS

1

@

2 RV88

GPIO26_TCK

AK24

0.60 V level, Please
VREFG Divider ans
cap close to ASIC

+1.8VGS
DIS@
2 RV93
DIS@
2 RV95

+1.8VGS

(Thames 75mA)

LV14DIS@
2
1
BLM15BD121SN1D_0402

1U_0402_6.3V6K
DIS@
CV83

1

+1.0VGS

2

2

0.935V@Chelsea

XTALIN
Voltage Swing: 1.8 V

RV235
10K_0402_5%
@

1

2

TS_FDO

1

2

RV236
10K_0402_5%
CH@

2

DIS@
LV16

(1.8V@20mA TSVDD)

DIS@
CV94
18P_0402_50V8J

3

1
GND

GND

4
2
27MHZ_16PF_7V27000011

DIS@
CV95
18P_0402_50V8J

2

1

AF29
AG29

AD34
AE34
AC33
AC34

+VDD1DI

R2/NC
R2B/NC

AC30
AC31
AD30
AD31

B2/NC
B2B/NC

AF30
AF31

C/NC
Y/NC
COMP/NC

AC32
AD32
AF32

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

AD29
AC29

VDD2DI/NC
VSS2DI/NC

AG31
AG32

A2VDD/NC

AG33

A2VDDQ/NC

AD33

A2VSSQ/TSVSSQ

AF33

R2SET/NC

AA29

DDC1CLK
DDC1DATA

AM26
AN26

HSYNC

AUD[0]

VSYNC

AUX1P
AUX1N

AM27
AL27

DDC2CLK
DDC2DATA

AM19
AL19

AUX2P
AUX2N

AN20
AM20

DDCCLK_AUX3P
DDCDATA_AUX3N

AL30
AM30

2

TS_FDO

AL31

TS_A/NC

AJ33

1

DPLUS
DMINUS

THERMAL

DDCCLK_AUX4P
DDCDATA_AUX4N

AL29
AM29

DDCCLK_AUX5P
DDCDATA_AUX5N

AN21
AM21

DDC6CLK
DDC6DATA

AJ30
AJ31

TSVDD
TSVSS

DDCCLK_AUX7P
DDCDATA_AUX7N

AK30
AK29

11

H2SYNC

GPIO21

GENERICC

<21>
<21>

+1.8VGS

+1.8VGS
C

(1.8V@65mA AVDD)

2

PS_1

2

GPIO8

+1.8VGS

65mA
1

100mA
10mil
(1.8V@100mA VDD1DI) 1
1

GPIO2

Reserved test pad of CRT Signals for debug

2
+1.8VGS
LV13DIS@
BLM15BD121SN1D_0402

1

1

2

1

2

RV237
8.45K_0402_1%
@

2
LV12DIS@
BLM15BD121SN1D_0402
PS_1

1

2
CV329

2

@

RV239
10K_0402_5%
@
PS_2

RV238
4.75K_0402_1%
CH@

1

2

CV331
CH@

RV246
1
@
1
@

2 +DPLL_PVDD
0_0402_5%
RV247
2 DPLL_PVSS
0_0402_5%

Add 12/8

T80
T81

GENLK_CLK
GENLK_VSYNC

RV241
10K_0402_5%
@
PS_3

RV240
4.75K_0402_1%
CV333
CH@

1

2

@

RV242
4.75K_0402_1%
CH@

1

2

Add 12/6 for MLPS
TX_PWRS_ENB

Transmitter Power Saving Enable
GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable
GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

PS_2

Internal VGA Thermal Sensor

+3VGS

PS_3
RV207
1
2
DIS@ 0_0402_5%

DIS@
RV90
10K_0402_5%

NC_TSVSSQ should be tied to GND on Thames/Seymour

+3VGS
DIS@
RV91
10K_0402_5%

1

6

EC_SMB_CK2

QV15A TH@
DMN66D0LDW-7_SOT363-6
4

VGA_SMB_DA2

3

<24>

EC_SMB_DA2

B

<24>

QV15B TH@
DMN66D0LDW-7_SOT363-6
@1 RV92

2 0_0402_5%

@1 RV94

2 0_0402_5%

CRT

VGA Thermal Sensor ADM1032ARMZ
Closed to GPU

2

for debug CRT

@

1

<31>

VGA_X1

RV232

1

VGA_CRT_VSYNC
VGA_CRT_HSYNC
VGA_CRT_CLK
VGA_CRT_DATA

RV216 1
RV217 1
RV218 1
RV219 1

@
@
@
@

210K_0402_5%
210K_0402_5%
210K_0402_5%
210K_0402_5%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

RV220 1
RV221 1
RV222 1

@
@
@

2150_0402_1%
2150_0402_1%
2150_0402_1%

+3VGS

+3VGS

2

GPU_THERMAL_D+
1

GPU_THERMAL_D-

CV89
2

CH@
2200P_0402_50V7K

XTALIN
2
0_0402_5%

1
RV98
VGA_CLKREQ#_R

2
4.7K_0402_5%

CH@

1

VDD

2

D+

3

D-

4

THERM#

SCLK

8

VGA_SMB_CK2

SDATA

7

VGA_SMB_DA2

ALERT#

6

GND

5

THM_ALERT#
1

ADM1032ARMZ-2REEL_MSOP8
CH@

+3VGS

GCLK@

RV96
4.7K_0402_5%

CH@

1
UV14

S

3

D

1

+3VGS

0.1U_0402_16V7K

2

2
G

RV199
2.2K_0402_5%
@

VGA_CRT_CLK <21>
VGA_CRT_DATA <21>

CH@
CV85

close to YV1
+3VGS

Reserved test pad of CRT Signals for debug
VGA_CRT_CLK
VGA_CRT_DATA

THAMES XT M2

+3VGS

<14> PEG_A_CLKRQ#

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

VGA_SMB_CK2

DIS@

A

AUD[1]

0

DAC2

XTALIN
XTALOUT

AK32

10mil
AJ32

DIS@ CV93
0.1U_0402_16V7K

1

1

DIS@ CV92
1U_0402_6.3V6K

+TSVDD
DIS@ CV91
10U_0603_6.3V6M

1
2
BLM15BD121SN1D_0402

+1.8VGS

YV1

GENERICC

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

<21>

2 499_0402_1%

10mil

AVDD
AVSSQ

G2/NC
G2B/NC

PLL/CLOCK
DPLL_VDDC

XO_IN2

(Thames 5mA)

RV97

1M_0402_5%

RSVD

DPLL_PVDD
DPLL_PVSS

XO_IN

Add 12/6 for MLPS

XTALIN

3

RV84 1 DIS@

VDD1DI
VSS1DI

VREFG

AW35

TS_FDO
DIS@
XTALOUT

AB34

1

DDC/AUX

AV33
AU34

RV251
1
2
DIS@ 0_0402_5%

H2SYNC

AMD RESERVED CONFIGURATION STRAPS

+AVDD

HPD1

AW34

GPU_THERMAL_D+
GPU_THERMAL_D-

2

2

XTALIN
XTALOUT

0

RSVD

1

0.1U_0402_16V7K
DIS@
CV88

1U_0402_6.3V6K
DIS@
CV87

10U_0603_6.3V6M
DIS@
CV86

1

AH13

+DPLL_VDDC AN31

+3VGS

+DPLL_VDDC

2
1
BLM15BD121SN1D_0402

RSET

1 249_0402_1%

20mil

(Thames 125mA)

LV15DIS@

+VREFG_GPU

IGNORE VIP DEVICE STRAPS

VIP_DEVICE_STRAP_ENA

QV14A
2N7002DW-7-F_SOT363-6

+1.8VGS

20mil

1

1

2

DAC1

20mil

2
1
CV81 0.1U_0402_16V7K
+DPLL_PVDD AM32
DIS@
10_0402_5% 2 DPLL_PVSS AN32
TH@
RV248

0.1U_0402_16V7K
DIS@
CV84

10U_0603_6.3V6M
DIS@
CV82

+DPLL_PVDD

1

B

1 499_0402_1%

XXX

V2SYNC

X

1

2

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

2

1

GPIO[13:11]

1

VDDCI_VID

ROMIDCFG(2:0)

2

10K_0402_5%

RV75 GPU_GPIO0
RV76 GPU_GPIO1
RV77 GPU_GPIO2

QV14B
2N7002DW-7-F_SOT363-6

Not share via for other GND

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

0
0: disable
1: enable

1

<53>

2
2
2

ENABLE EXTERNAL BIOS ROM

2

1 DIS@
1 DIS@
@
1

RESERVED

GPIO_22_ROMCSB

1

10K_0402_5%
10K_0402_5%
10K_0402_5%

GPIO21

BIOS_ROM_EN

2

STRAPS

+3VGS
C

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
GPU_GPIO11
AK16
GPU_GPIO12
AL16
GPU_GPIO13
AM16
AM14
GPU_VID0
AM13
GPU_VID2
AK14
THM_ALERT#
AG30
AN14
2 10K_0402_5%
AM17
GPU_VID1
AL13
GPIO21_BBEN AJ14
AK13
VGA_CLKREQ#_R
AN13
GPIO24_TRSTB AM23
GPIO25_TDI
AN23
GPIO26_TCK
AK23
GPIO27_TMS
AL24
GPIO28_TDO
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

DIS@
2
2
0_0402_5%

RSVD

RV250
1
@

ACIN

<24> ACIN_65W

SCL
SDA
GENERAL PURPOSE I/O

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2
VGA_SMB_CK2
AC_BATT
VDDCI_VID
R02
GPU_GPIO8
GPU_GPIO9

5

1

DPD

PACIN#

AC_BATT

DIS@

2

DPC

I2C
AK26
AJ26

1

TX0P_DPC2P
TX0M_DPC2N

RV74
4.7K_0402_5%

DIS@

3

SWAPLOCKA
SWAPLOCKB

1

AJ21
AK21

PT

1

AU14
AV13

0.68U_0402_10V

RV71

1

AT33
AU32

D

5

RV69

1

TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N

RV73
10K_0402_5%

2

1

DIS@

1

1

+3VGS

2

1

RV71

DPB

+3VGS

1

RV67

AR30
AT29

2

0

MT41J64M16JT-107G

PN:SA00004Y20L

X

TXCBP_DPB3P
TXCBM_DPB3N

0.68U_0402_10V

RV71

RV69

0

64MX16 (1G) *Micron 1GB

0: disable
1: enable

1

PT

0

RV70

1

RV68

Samsung 2GB
PN:SA000047Q1L

PCIE TRANSMITTER DE-EMPHASIS

1

RV72

1

K4W2G1646C-HC11

128M16 (2G)

GPIO1

2

RV67

Hynix 2GB
PN:SA00003YO1L

TX_DEEMPH_EN

2

RV69

0

H5TQ2G63BFR-11C

128M16 (2G)

AT27
AR26

10U_0603_6.3V6M
DIS@
CV77

RV68

X

TX2P_DPA0P
TX2M_DPA0N

4

PT

0

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

1U_0402_6.3V6K
DIS@
CV76

RV72

0

K4W1G1646G-BC11

1GB
PN:SA00004GS1L

0: 50% swing
1: Full swing

0.1U_0402_16V7K
DIS@
CV75

RV70

1

64MX16 (1G) *Samsung

PCIE FULL TX OUTPUT SWING

2

H5TQ1G63DFR-11C

RV67

DESCRIPTION OF DEFAULT SETTINGS

GPIO0

6

VRAM_ID0 VRAM_ID1 VRAM_ID2

1GB
PN:SA000041S3L

PIN

TX_PWRS_ENB

1

VRAM_ID0
VRAM_ID1
VRAM_ID2

64MX16 (1G) *Hynix

STRAPS

AU26
AV25

VRAM_ID2

D

Vendor

AT25
AR24

TX1P_DPA1P
TX1M_DPA1N

DPA
VRAM_ID1

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

RECOMMENDED
SETTINGS

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

VRAM_ID0

1U_0402_6.3V6K
DIS@
CV79

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2
2
2
2
2
2

10U_0603_6.3V6M
DIS@
CV80

X76@
X76@
X76@
X76@
X76@
X76@

1
1
1
1
1
1

0.1U_0402_16V7K
DIS@
CV78

RV67
RV68
RV69
RV70
RV71
RV72

2

+1.8VGS

AU24
AV23

0.68U_0402_10V

5

2

A

CV90
10P_0402_50V8J
@

Address:100_1101

12/8 Add external thermal sensor BOM

@
2N7002_SOT23-3
QV28
2 RV200 1
0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@

2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_Main_MSIC
Size
Document Number
Custom
Date:

Rev
1.0

LA-8241P

Wednesday, February 01, 2012
1

Sheet

35

of

56

4

3

+3VGS

+5VS

1

D

2
6
1

4

5
1

3

2

22U_0805_6.3V6M

1

P

PX_MODE

PX_MODE <24,52,53>

@
MC74VHC1G08DFT2G SC70 5P

PX_MODE=1 for Normal Operation
PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

RV102

2

@

1
2
DV12
RB751V_SOD323
1
2
1
RV233 0_0402_5%
CV100
DIS@
1U_0603_10V6K
2
@

4

G

A

DIS@

D

for PX5.0

CV97

2

3

2

DIS@
RV105
20K_0402_5%

60mil

1 RV234 2
TH@ 0_0603_5%
1

VDDC_ON#
Y

3

1

1 RV103 2
CH@ 0_0805_5%

G

+3VGS

B

1

+VGA_CORE

60mil

D

3

S

2

+BIF_VDDC

1

QV20
@
AO3416_SOT23-3

G

1

+VGA_CORE

UV16

RV104
5.11K_0402_1%
DIS@

PXS_PWREN

CV98
0.1U_0402_16V7K
@

D

S

2

+3VGS CV99
@
0.1U_0402_16V7K
1
2

QV21
2N7002K_SOT23-3
DIS@

QV19
@
AO3416_SOT23-3
S

2
G

1.0V_ON#

2

1

for PX4.0

3

60mil
@
QV18A
DMN66D0LDW-7_SOT363-6

2

60mil

1

2

1
3

5
3

P

1

G

@
QV18B
DMN66D0LDW-7_SOT363-6

5

MC74VHC1G08DFT2G SC70 5P

3

G

1

+1.0VGS

1.0V_ON#

QV17
CH@
AO3416_SOT23-3
D

UV15
@
4
Y

55mA@1.0V, in BACO mode

QV16
CH@
AO3416_SOT23-3

S

A

2

1 RV249 2
@
0_0805_5%
VDDC_ON#

G

1

D

B

RV100
10K_0402_5%
CH@

D

2

1

S

RV101
10K_0402_5%
DIS@

RV99
10K_0402_5%
@

2

0.1U_0402_16V7K
@ CV96

2

<17,52> VGA_PWRGD

PX_EN

1

Switch circuits in BACO desingns for Thanes/Seymour only

+5VS

Circuits to support BACO

+3VGS

<37>

2

2

5

RUNPWROK

1

DIS@ 2

PX_MODE

0_0402_5%

for PX5.0

+1.8VS TO +1.8VGS

+3VALW

+1.8VS

@

2

2MM

DIS@
QV25
2N7002_SOT23

S

DIS@

C

4

1

J9
UV35

DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

D

PXS_PWREN 2
G
3

1

PXS_PWREN#

C

<16,52> PXS_PWREN

+1.8VGS

2

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON

1

CV320
10U_0805_10V6K
2 DIS@

CV321
1U_0603_10V6K
2 DIS@
1 2

Note:

1

2N7002H_SOT23-3
QV29
@

1
2

330K_0402_5%
RV128
DIS@
1 RV211 2
DIS@ 470K_0402_5%

+1.5V

1

S

PXS_PWREN# 2
G

2N7002H_SOT23-3
DIS@

2

1

QV10

+1.5VGS

1

RV212
0_0402_5%
@

2
G
S

PXS_PWREN# 1 RV214 2
@
0_0402_5%

2

Power Seguence of Thames and Chelsea

3

+1.5VS TO +1.5VGS

D

RV213
470_0603_5%
@

D

B+_BIAS

PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

1

DIS@
RV109
100K_0402_5%

3

1

for PX4.0 and PX5.0

CV2
0.1U_0603_25V7K
DIS@

JP9 @
2

1
2MM

CV104
DIS@

+VGA_CORE

8
7
6
5

1

10U_0603_6.3V6M

1
2
3

1

CV105
DIS@

2

4

2

1

CV106 DIS@
1U_0603_10V6K

2

RV112 DIS@
20K_0402_5%

2
G
QV26 @
2N7002K_SOT23-3

+3.3VS TO +3.3VGS

RV113
+3VS

2

10U_0603_6.3V6M

1U_0603_10V6K

2 0_0402_5%

CV107 DIS@
0.1U_0603_25V7K

1

PX_MODE#

1
2MM

1

3

+5VALW
DIS@
RV107

DIS@
RV108

20K_0402_5%

2

1

1

CV102
DIS@

RV106
470_0603_5%
@

2

D

QV22 DIS@
AP2301GN-HF_SOT23-3

S

1K_0402_5%
D
DIS@
QV24

2
G
3

PXS_PWREN

CV101
DIS@

2

@

1

2

1

2
RV115
0_0402_5%
1

1

+3VGS
JP8 @

@
1 RV116

1

4

1
2

DIS@
RV117
100K_0402_5%

DIS@
QV27B

5

DMN66D0LDW-7_SOT363-6

PX_MODE

DIS@
QV27A

PX_MODE# 2

DMN66D0LDW-7_SOT363-6

3 2

<20ms

1 DIS@
2
300K_0402_5%

6

DIS@
RV114
100K_0402_5%

3

1

+1.0VGS
+1.8VGS

S

3

+3VALW

B

D

B+_BIAS

+1.5VGS

RV111 @
470_0603_5%

1 2

+VDDCI

2

B

UV17 DIS@
AO4304L_SO8

10U_0603_6.3V6M

1

+3VGS

1 DIS@
CV103
0.1U_0603_25V7K

2
G
QV23
2N7002K_SOT23-3
@

RV110
PXS_PWREN#

1
@

2
0_0402_5%

2
S
2N7002H_SOT23-3

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_SeymourXT_M2_BACO POWER
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

36

of

56

5

4

3

2

1

UV1F

(Thames 330mA)
+DPAB_VDD18

1

2

@ CV119
0.1U_0402_16V7K

2

@ CV118
1U_0402_6.3V6K

C

1

AP22
AP23

AP14
AP15

1

2

1

2

@ CV125
0.1U_0402_16V7K

@ CV123
10U_0603_6.3V6M

DIS@

@ CV124
1U_0402_6.3V6K

+DPEF_VDD10

0_0402_5%
B

2

1 RV122 AW18

1

2

20mil

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

AN27
AP27
AP28
AW24
AW26

+DPAB_VDD10

CV109
1U_0402_6.3V6K

1

@

1

@

2

+1.0VGS

1 RV120

2

0_0402_5%
1

DIS@

@

2

2

20mil
DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AP25 130mA
AP26

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

20mil

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

AN33 110mA
AP33

AN29
AP29
AP30
AW30
AW32

AW28 RV123 1 DIS@

20mil

2

2 150_0402_1%

+DPAB_VDD18
AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

20mA

10mil

AU28
AV27

+DPEF_VDD10

1

+DPAB_VDD18

20mA
AL33
AM33

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

10mil

AV29
AR28

+DPCD_VDD18

20mA
AN34
AP39
AR39
AU37

+DPEF_VDD10

1.0V@240mA DPEF_VDD10)
0.935V@Chelsea
2

1

@ CV121
1U_0402_6.3V6K

@ CV120
10U_0603_6.3V6M

DIS@

@ CV122
0.1U_0402_16V7K

+DPEF_VDD18

0_0402_5%

1 RV126

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

+DPEF_VDD18

2

(Thames 330mA)

+DPAB_VDD10

20mil

1 RV124

2

+DPAB_VDD10

+DPCD_VDD10

2

1.8V@300mA DPEF_VDD18)

2 @

+DPAB_VDD18

20mil

1

2 @

0.935V@Chelsea

AP31
AP32

+DPCD_VDD18

150_0402_1% 2 DIS@

+1.0VGS

AN24
AP24

2

0_0402_5%
DIS@

10U_0603_6.3V6M
CV116

+DPCD_VDD10

(Thames 330mA)

(Thames 220mA)

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

+1.8VGS

1 RV118

1

20mil (1.0V@220mA DPAB_VDD10)

AN19
AP18
AP19
AW20
AW22

+1.8VGS

@

20mil

DP A/B POWER

110mA
AP13
AT13

AN17
AP16
AP17
AW14
AW16

+DPCD_VDD10

@ CV117
10U_0603_6.3V6M

1 RV121 2
0_0402_5%
DIS@

20mil

2

1.0V@220mA DPCD_VDD10)
0.935V@Chelsea

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

+DPCD_VDD10

1

@
2

AP20
AP21

1U_0402_6.3V6K
CV115

(Thames 220mA)

1

@
2

CV113
0.1U_0402_16V7K

1

@

CV112
1U_0402_6.3V6K

CV111
10U_0603_6.3V6M

DIS@

DP C/D POWER

130mA

+DPCD_VDD18

2

0_0402_5%

+1.0VGS

20mil

+DPCD_VDD18

1.8V@300mA DPCD_VDD18)
1 RV119

CV114
0.1U_0402_16V7K

+1.8VGS

CV108
0.1U_0402_16V7K

UV1H

(Thames 330mA)

CV110
10U_0603_6.3V6M

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18
1
1

20mil
1

AF34
AG34

20mil

20mA
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

AK33
AK34

AF39
AH39
AK39
AL34
AM34

AM37
AN38

10mil

+DPEF_VDD18

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

20mA
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

PS_0

10mil

AV19
AR18

+DPEF_VDD18

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

+DPEF_VDD10
2

+DPCD_VDD18

20mA
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

+DPEF_VDD18

10mil

AU18
AV17

AL38
AM35

10mil

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

+1.8VGS

1

1

AM39

RV127
150_0402_1%
DIS@

2

2

RV243
8.45K_0402_1%
CH@

DPEF_CALR
THAMES XT M2
@

PS_0

MLPS Bit

2K_0402_1%

RV201
0_0402_5%
TH@
2

CH@

CV335
@

0.68U_0402_10V

1

RV201
1

2

Thames/Seymour Only

AMD recommended setting
strap

R_PU

R_PD

C

PS0:

11001

RV243=8.45K

RV201=2K

CV335=NC

PS1:

11000

RV237=NC

RV238=4.75K

CV329=NC

PS2:

00000

RV239=NC

RV240=4.75K

CV331=0.68u

PS3:

11000

RV241=NC

RV242=4.75K

CV333=NC

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

D

C

PX_EN

<36>

1

D

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

RV125
4.7K_0402_5%
DIS@
2

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

B

A39 MECH#1
AW1 MECH#2
AW39MECH#3

T82 PAD
T83 PAD
T84 PAD

THAMES XT M2
@

Do not install for Heathrow/Chelsea

A

A

PS_0 Should be tied to GND on Thames/Seymour

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_SetmourXT_M2_PWR_GND
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

37

of

56

3

2

(Thames 440mA)

10mil
20mil

(120mA SPV10)

2

+VDDCI

0.1U_0402_16V7K
DIS@
CV217

H7
H8

+SPV18 AM10
+SPV10

+VGA_CORE

AN9
AN10

RV215
10_0402_1%
DIS@

2

<52> VCCSENSE_VGA

RV202
10_0402_1%
DIS@

SPVSS

VOLTAGE
SENESE
AF28

FB_VDDC

10mil

VSSSENSE_VGA

AG28
AH29

FB_VDDCI
FB_GND

1

<52> VSSSENSE_VGA

SPV10

2

RV204
DIS@ 10_0402_1%

1U_0402_6.3V6K
DIS@
CV130

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

1U_0402_6.3V6K
DIS@
CV133

10U_0603_6.3V6M
DIS@
CV134

0.1U_0402_16V7K
DIS@
CV132
1U_0402_6.3V6K
DIS@
CV150

10U_0603_6.3V6M
DIS@
CV151

1U_0402_6.3V6K
DIS@
CV149

1U_0402_6.3V6K
DIS@
CV148

1U_0402_6.3V6K
DIS@
CV147

1U_0402_6.3V6K
DIS@
CV146

(Chelsea)

2

(0.935V@2.5A PCIE_VDDC)

2

2

1

2

1

1

2

+

DIS@

1

1U_0402_6.3V6K
DIS@
CV169

2

1

1U_0402_6.3V6K
DIS@
CV168

2

1

1U_0402_6.3V6K
DIS@
CV167

2

1

1U_0402_6.3V6K
DIS@
CV166

2

1

1U_0402_6.3V6K
DIS@
CV165

2

1

1U_0402_6.3V6K
DIS@
CV164

2

1

1U_0402_6.3V6K
DIS@
CV163

2

1

1U_0402_6.3V6K
DIS@
CV162

2

1

1U_0402_6.3V6K
DIS@
CV161

1

1U_0402_6.3V6K
DIS@
CV160

1

2

2

2

1

2

1

2

2

1

2

1

2

1

1U_0402_6.3V6K
DIS@
CV186

2

1

1U_0402_6.3V6K
DIS@
CV185

2

1

1U_0402_6.3V6K
DIS@
CV184

2

1

1U_0402_6.3V6K
DIS@
CV183

1

1U_0402_6.3V6K
DIS@
CV182

1

1U_0402_6.3V6K
DIS@
CV181

+VGA_CORE

1

2

C

1

2

2

+VGA_CORE

1

2

1

2

+BIF_VDDC

55mA
1

2

For non-BACO designs, connect BIF_VDDC to VDDC.
For BACO designs - see BACO reference schematics

1

2

B

(GDDR3/DDR3 1.12V@4A VDDCI)

+VDDCI

(GDDR5 1.12V@16A VDDCI)

SPV18

10mil

VGA_CORE_SEN
VDDCI_SEN

<53> VDDCI_SEN

MPV18#1
MPV18#2

1

1
1

1U_0402_6.3V6K
DIS@
CV216

2

PLL

20mil
+MPV18

2

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

1

2

1

2

1

2

1

2

+VGA_CORE
LV25 @
1
2
BLM15BD121SN1D_0402
LV26 @
1
2
BLM15BD121SN1D_0402

4A
1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

10U_0603_6.3V6M
DIS@
CV323

DIS@
1
2
MCK1608471YZF 0603

10U_0603_6.3V6M
DIS@
CV215

LV23

1

2

2

(Thames
100mA)
0.935V@Chelsea

1

2

NC_VDDRHB
NC_VSSRHB

2

(1.0V@1920mA PCIE_VDDC)

22U_0603_6.3V6M
DIS@
CV214

2

2

NC_VDDRHA
NC_VSSRHA

D

2

10U_0603_6.3V6M
DIS@
CV322

1

V12
U12

1

2

2

1

1

0.1U_0402_16V7K
DIS@
CV199

1

0.1U_0402_16V7K
DIS@
CV202

1

2

+1.0VGS

M20
M21
1U_0402_6.3V6K
DIS@
CV198

(1.8V@75mA SPV18)
10U_0603_6.3V6M
DIS@
CV200

B

(Thames 150mA)

10U_0603_6.3V6M
DIS@
CV197

LV22 DIS@
1
2
BLM15BD121SN1D_0402

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

(M97, Broadway and Madison: 1.8V@150mA MPV18)

LV21 DIS@
1
2
MCK1608471YZF 0603

(Thames 50mA)
1U_0402_6.3V6K
DIS@
CV201

+1.8VGS

2

1

10U_0603_6.3V6M
DIS@
CV324

+1.8VGS

AD12
AF11
AF12
AG11

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

2

1U_0402_6.3V6K
DIS@
CV325

2

1

1

(Thames 1.1A)

1

1U_0402_6.3V6K
DIS@
CV211

0.1U_0402_16V7K
DIS@
CV194

1U_0402_6.3V6K
DIS@
CV193

1

+VDDR4 AF13
AF15
AG13
AG15

1

1U_0402_6.3V6K
DIS@
CV210

20mil

DIS@ LV20
1
2
BLM15BD121SN1D_0402

2

1U_0402_6.3V6K
DIS@
CV209

+1.8VGS

I/O
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

2

22U_0603_6.3V6M
DIS@
CV192

AF23
AF24
AG23
AG24

2

1U_0402_6.3V6K
DIS@
CV208

10mil

2

1

1

1U_0402_6.3V6K
DIS@
CV180

1

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

1

10U_0603_6.3V6M
DIS@
CV191

AF26
AF27
AG26
AG27

2

LEVEL
TRANSLATION

1

1U_0402_6.3V6K
DIS@
CV207

2

20mil

2

1U_0402_6.3V6K
DIS@
CV179

1

1

1U_0402_6.3V6K
DIS@
CV206

2

1

+1.8VGS

2
1
MBK1608121YZF_0603

+VGA_CORE

1U_0402_6.3V6K
DIS@
CV178

1

0.1U_0402_16V7K
DIS@
CV174

1U_0402_6.3V6K
DIS@
CV173

2

1U_0402_6.3V6K
DIS@
CV172

1U_0402_6.3V6K
DIS@
CV171

10U_0603_6.3V6M
DIS@
CV170

2

1

40mA
(1.8V@40mA PCIE_PVDD) DIS@ LV18

(Thames 20.5A)

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

1U_0402_6.3V6K
DIS@
CV159

+VDDC_CT

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

1U_0402_6.3V6K
DIS@
CV158

0.1U_0402_16V7K
DIS@
CV156

0.1U_0402_16V7K
DIS@
CV155

0.1U_0402_16V7K
DIS@
CV154

0.1U_0402_16V7K
DIS@
CV153

2

1U_0402_6.3V6K
DIS@
CV205

2

2

2

+1.0VGS

1U_0402_6.3V6K
DIS@
CV177

1

1U_0402_6.3V6K
DIS@
CV190

2

1U_0402_6.3V6K
DIS@
CV189

1U_0402_6.3V6K
DIS@
CV188

10U_0603_6.3V6M
DIS@
CV187

1

2

1

POWER

(Thames 60mA)

2

2

1

(1.8V@110mA VDD_CT)

1

+3VGS

1

1

(Thames 250mA)

DIS@ LV19
1
2
BLM15BD121SN1D_0402

C

2

1

2

+PCIE_PVDD

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

1U_0402_6.3V6K
DIS@
CV196

+1.8VGS

1

2

1

CV327
330U_D2_2VM_R6M~D

0.1U_0402_16V7K
DIS@
CV152

+1.5VGS

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

1

RV244
1
2 +PCIE_VDDR
TH@ 0_0402_5%
RV245
1
2
+BIF_VDDC
@
0_0402_5%

1U_0402_6.3V6K
DIS@
CV204

2

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

1U_0402_6.3V6K
DIS@
CV157

2

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

1U_0402_6.3V6K
DIS@
CV176

2

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

1U_0402_6.3V6K
DIS@
CV175

2

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

1

1U_0402_6.3V6K
DIS@
CV195

2

1

2

1

Add 12/8

1U_0402_6.3V6K
DIS@
CV203

2

1

1U_0402_6.3V6K
DIS@
CV145

2

1

1U_0402_6.3V6K
DIS@
CV144

2

1

1U_0402_6.3V6K
DIS@
CV143

2

1

1U_0402_6.3V6K
DIS@
CV142

2

1

2

40mil

PCIE

1U_0402_6.3V6K
DIS@
CV141

2

1

10U_0603_6.3V6M
DIS@
CV140

+

@

1

10U_0603_6.3V6M
DIS@
CV139

1

10U_0603_6.3V6M
DIS@
CV138

1

10U_0603_6.3V6M
DIS@
CV137

10U_0603_6.3V6M
DIS@
CV136

220U_B2_2.5VM_R35
CV135

D

MEM I/O

1

10U_0603_6.3V6M
DIS@
CV131

2

UV1E

For DDR3 MVDDQ = 1.5V

(Thames 1.7)A

1U_0402_6.3V6K
DIS@
CV129

1

1U_0402_6.3V6K
DIS@
CV128

0.1U_0402_16V7K
DIS@
CV127

0.1U_0402_16V7K
DIS@
CV126

1

+1.5VGS

DIS@ LV17
2
1
MBK1608121YZF_0603

(1.8V@504mA PCIE_VDDR)

+PCIE_VDDR

1

+1.8VGS

10U_0603_6.3V6M
DIS@
CV213

4

1U_0402_6.3V6K
DIS@
CV212

5

1

2

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

THAMES XT M2
@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_SeymourXT_M2_Power
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

38

of

56

4

UV1C
DDR2
GDDR3/GDDR5
DDR3

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

+1.5VGS

L18
L20

RV129 1 DIS@
RV130 1 SE@
RV131 1 DIS@

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

L27
N12
AG12

RV132 1
RV134 1
RV135 1
RV206 1
RV205 1

2
2
2
2
2

240_0402_1%
240_0402_1%
240_0402_1%
120_0402_5%
120_0402_5%

M12
M27
AH12

SE@
DIS@
DIS@
CH@
CH@

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

WEA0B
WEA1B

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA0_8
MAA1_8

MDA[0..63]

MAA[12..0]
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

A32
C32
D23
E22
C14
A14
E10
D9

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

C34
D29
D25
E20
E16
E12
J10
D7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

A34
E30
E26
C20
C16
C12
J11
F8

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

J21
G19

ODTA0
ODTA1

H27
G27

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19

MAA13
MAA14

A_BA[2..0]

MAA[12..0] <40>

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

A_BA[2..0] <40>

DQMA#[7..0] <40>

QSA[7..0] <40>

QSA#[7..0] <40>

ODTA0
ODTA1

<40>
<40>

CLKA0
CLKA0#

<40>
<40>

CLKA1
CLKA1#

<40>
<40>

RASA0#
RASA1#

<40>
<40>

CASA0#
CASA1#

<40>
<40>

CSA0#_0

<40>

CSA1#_0

<40>

CKEA0
CKEA1

<40>
<40>

WEA0#
WEA1#

<40>
<40>

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

MAB[12..0]
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

MAB[12..0] <41>

B_BA[2..0]

B_BA[2..0] <41>

D

DQMB#[7..0] <41>

QSB[7..0] <41>

QSB#[7..0] <41>

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

ODTB0
ODTB1

<41>
<41>

CLKB0
CLKB0#

<41>
<41>

CLKB1
CLKB1#

<41>
<41>

RASB0#
RASB1#

<41>
<41>

CASB0#
CASB1#

<41>
<41>

CSB0#_0

<41>

CSB1#_0

<41>

CKEB0
CKEB1

<41>
<41>

WEB0#
WEB1#

<41>
<41>

C

RV133 1

<40>
<40>

TESTEN
2
5.11K_0402_1%

AD28
AK10
AL10

TESTEN
CLKTESTA
CLKTESTB

MAB0_8
MAB1_8

DRAM_RST

T8
W8
AH11

MAB13
MAB14

MAB13
MAB14

<41>
<41>

DRAM_RST#_R

THAMES XT M2
@

@

@

@

POP

@

RV134

POP

@

@

RV135

POP

@

@

RV206

@

@

POP

RV205

@

@

POP

1

POP

RV132

1

RV131

2

@

2

@

POP

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

@
CV219
0.1U_0402_16V7K

1

@

@

1

POP

RV130

@
RV136
51.1_0402_1%
2

RV129

@
CV218
0.1U_0402_16V7K

@
RV137
51.1_0402_1%

B

route 50ohms single-ended/100ohms diff
and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

2

Chelsea M2

+1.5VGS
1

B

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MDB[0..63]

MDB[0..63]

DIS@
MAA13
MAA14

@

Seymour M2

<41>

DDR2
GDDR5/GDDR3
DDR3

WEB0B
WEB1B

Co-lay Thames/Seymour/Chelsea
THAMES XT M2
Thames M2

1

UV1D
DDR2
GDDR3/GDDR5
DDR3

GDDR5

C

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

2

GDDR5

D

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

<40>

DDR2
GDDR5/GDDR3
DDR3

MEMORY INTERFACE A

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

3

MDA[0..63]

MEMORY INTERFACE B

5

1
DRAM_RST#_R

RV141
40.2_0402_1%
DIS@

RV142
40.2_0402_1%
DIS@

1

1

+VDD_MEM15_REFSB

RV149
100_0402_1%
DIS@

CV224
0.1U_0402_16V7K
DIS@

2

DIS@

2

1

RV148
100_0402_1%

CV223
0.1U_0402_16V7K
DIS@

1

+VDD_MEM15_REFDB
DIS@
RV145
4.99K_0402_1%

2

1

DIS@
CV222
120P_0402_50V9

2

2

1

1
RV147
100_0402_1%
DIS@

CV221
0.1U_0402_16V7K
DIS@

2

2

2

1

1
RV146
100_0402_1%
DIS@

CV220
0.1U_0402_16V7K
DIS@

2

+VDD_MEM15_REFSA

1 RV144 2
10_0402_1%
DIS@
2

+VDD_MEM15_REFDA

1 RV143 2
51.1_0402_1%
DIS@

2

<40,41> DRAM_RST#

+1.5VGS
1

+1.5VGS

2

2

RV140
40.2_0402_1%
DIS@
2

RV139
40.2_0402_1%
DIS@

2

1

RV138
4.7K_0402_5%
@

1

+1.5VGS

1

+1.5VGS

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_SeymourXT_M2_MEM IF
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

39

of

56

5

4

3

2

1

CHANNEL A: 256MB/512MB DDR3

<39>

MAA[14..0]

MDA[0..63]

MAA[14..0]

<39> DQMA#[7..0]

<39>

<39>

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

QSA[7..0]

DQMA#[7..0]

<39>
<39>
<39>

A_BA0
A_BA1
A_BA2

M2
N8
M3

QSA[7..0]

<39>
<39>
<39>

CLKA0
CLKA0#
CKEA0

J7
K7
K9

<39>
<39>
<39>
<39>
<39>

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA#[7..0]

QSA#[7..0]

C

QSA3
QSA0

F3
C7

DQMA#3
DQMA#0

E7
D3

QSA#3
QSA#0

G3
B7

T2

<39,41> DRAM_RST#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA29
MDA27
MDA30
MDA26
MDA28
MDA24
MDA31
MDA25

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA5
MDA1
MDA6
MDA3
MDA4
MDA2
MDA7

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA2
QSA1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#2
DQMA#1

E7
D3

QSA#2
QSA#1

G3
B7

+1.5VGS

DRAM_RST# T2
L8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA17
MDA23
MDA16
MDA19
MDA18
MDA21
MDA20
MDA22

D7
C3
C8
C2
A7
A2
B8
A3

MDA15
MDA10
MDA14
MDA11
MDA13
MDA9
MDA12
MDA8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

RV151
240_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11

DIS@

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

RESET
ZQ/ZQ0

M2
N8
M3

<39>
<39>
<39>

CLKA1
CLKA1#
CKEA1

J7
K7
K9

<39>
<39>
<39>
<39>
<39>

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

A_BA0
A_BA1
A_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

QSA4
QSA5

F3
C7

DQMA#4
DQMA#5

E7
D3

QSA#4
QSA#5

G3
B7

DRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

J1
L1
J9
L9

RV152
240_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@

2
56_0402_1%

VREFC_A3
VREFD_Q3

+1.5VGS

BA0
BA1
BA2

1

ZQ/ZQ0

A_BA0
A_BA1
A_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

UV20

VREFCA
VREFDQ

2

J1
L1
J9
L9

RV150
240_0402_1%
DIS@

CLKA0 1
RV154

VREFC_A2
VREFD_Q2

+1.5VGS

BA0
BA1
BA2

1

L8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

UV21

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA38
MDA36
MDA39
MDA34
MDA35
MDA33
MDA37
MDA32

D7
C3
C8
C2
A7
A2
B8
A3

MDA42
MDA44
MDA40
MDA46
MDA43
MDA45
MDA41
MDA47

VREFC_A4
VREFD_Q4

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#
CKEA1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

DRAM_RST# T2
L8

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA55
MDA51
MDA48
MDA52
MDA50
MDA53
MDA49
MDA54

D7
C3
C8
C2
A7
A2
B8
A3

MDA60
MDA57
MDA63
MDA56
MDA61
MDA59
MDA62
MDA58

D

+1.5VGS

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

RV153
240_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

MDA[0..63]

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

VREFCA
VREFDQ

1

<39>

M8
H1

2

D

VREFC_A1
VREFD_Q1

UV19

1

UV18

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@

X76@

DIS@
2
56_0402_1%

1

CV233
2
1

1

VREFD_Q4

RV173
4.99K_0402_1%
DIS@

DIS@

2

DIS@

2

CV232
1

1

VREFC_A4
RV172
4.99K_0402_1%
DIS@
2

2

2

2

2
1

CV231
1
DIS@

2

2

CV230
1

1
2

2

1

1

1
2

2

2

2

1

CV229
1

CV228
1

1
2

2

CV227
1

1
2

CV226
1

2

1
2

DIS@

VREFD_Q3

RV171
4.99K_0402_1%
DIS@

B

15mil
0.1U_0402_16V7K

DIS@

RV163
4.99K_0402_1%
DIS@

15mil
0.1U_0402_16V7K

DIS@

+1.5VGS

RV162
4.99K_0402_1%
DIS@

15mil

VREFC_A3
RV170
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

DIS@

+1.5VGS

RV161
4.99K_0402_1%
DIS@

15mil

VREFD_Q2

RV169
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

DIS@

+1.5VGS

RV160
4.99K_0402_1%
DIS@

15mil

VREFC_A2
RV168
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

CV234
0.01U_0402_16V7K
DIS@

RV159
4.99K_0402_1%
DIS@

15mil

VREFC_A1
RV167
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

RV166
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

2
56_0402_1%

+1.5VGS

0.1U_0402_16V7K

1

VREFD_Q1

DIS@
CLKA1# 1
RV165

RV158
4.99K_0402_1%
DIS@

15mil

2

2
56_0402_1%

15mil

2

CLKA1 1
RV164

RV157
4.99K_0402_1%
DIS@

2

DIS@

+1.5VGS

1

RV156
4.99K_0402_1%
DIS@

B

+1.5VGS
1

+1.5VGS
1

+1.5VGS

2

CV225
0.01U_0402_16V7K
DIS@

1

2

1

CLKA0# 1
RV155

+1.5VGS
+1.5VGS

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1U_0402_6.3V6K
DIS@
CV271

2

1U_0402_6.3V6K
DIS@
CV270

1

1U_0402_6.3V6K
DIS@
CV269

2

1U_0402_6.3V6K
DIS@
CV268

1

1U_0402_6.3V6K
DIS@
CV267

2

1U_0402_6.3V6K
DIS@
CV266

1

1U_0402_6.3V6K
DIS@
CV265

2

1U_0402_6.3V6K
DIS@
CV264

1

1U_0402_6.3V6K
DIS@
CV263

2

1U_0402_6.3V6K
DIS@
CV262

1

2

1U_0402_6.3V6K
DIS@
CV261

1

1U_0402_6.3V6K
DIS@
CV260

2

1U_0402_6.3V6K
DIS@
CV259

1

1U_0402_6.3V6K
DIS@
CV258

2

1U_0402_6.3V6K
DIS@
CV257

1

1U_0402_6.3V6K
DIS@
CV256

2

1U_0402_6.3V6K
DIS@
CV255

1

1U_0402_6.3V6K
DIS@
CV254

2

+1.5VGS

1U_0402_6.3V6K
DIS@
CV253

1

1U_0402_6.3V6K
DIS@
CV252

2

10U_0603_6.3V6M
DIS@
CV251

1

10U_0603_6.3V6M
DIS@
CV250

2

10U_0603_6.3V6M
DIS@
CV249

1

10U_0603_6.3V6M
DIS@
CV248

2

0.1U_0402_16V7K
DIS@
CV247

1

0.1U_0402_16V7K
DIS@
CV246

2

0.1U_0402_16V7K
DIS@
CV245

1

0.1U_0402_16V7K
DIS@
CV244

2

0.1U_0402_16V7K
DIS@
CV243

1

0.1U_0402_16V7K
DIS@
CV242

2

0.1U_0402_16V7K
DIS@
CV241

1

0.1U_0402_16V7K
DIS@
CV240

2

0.1U_0402_16V7K
DIS@
CV239

1

0.1U_0402_16V7K
DIS@
CV238

2

0.1U_0402_16V7K
DIS@
CV237

1

0.1U_0402_16V7K
DIS@
CV236

0.1U_0402_16V7K
DIS@
CV235

+1.5VGS

1

2

A

A

Compal Secret Data

Security Classification
Issued Date

2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
ATI_SeymourXT_M2_VRAM_A
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

40

of

56

5

4

3

2

1

CHANNEL B: 256MB/512MB DDR3

<39>

MAB[14..0]

MDB[0..63]

MAB[14..0]

<39> DQMB#[7..0]

<39>

QSB[7..0]

QSB#[7..0]

B_BA0
B_BA1
B_BA2

DQMB#[7..0]

QSB[7..0]

<39>
<39>
<39>

CLKB0
CLKB0#
CKEB0

J7
K7
K9

QSB#[7..0]

<39>
<39>
<39>
<39>
<39>

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

DIS@

C

CLKB0 1
RV174

QSB3
QSB0

F3
C7

DQMB#3
DQMB#0

E7
D3

QSB#3
QSB#0

G3
B7

2
56_0402_1%
DIS@

T2

<39,40> DRAM_RST#

2
56_0402_1%

L8

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

RV176
240_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2
56_0402_1%

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB2
QSB1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#2
DQMB#1

E7
D3

QSB#2
QSB#1

G3
B7

UV24

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

DRAM_RST# T2

RESET

L8

1

E3
F7
F2
F8
H3
H8
G2
H7

MDB16
MDB19
MDB20
MDB22
MDB17
MDB21
MDB18
MDB23

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8

VREFC_A3_B
VREFD_Q3_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VGS

BA0
BA1
BA2

ZQ/ZQ0

J1
L1
J9
L9

RV177
240_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

M2
N8
M3

<39>
<39>
<39>

CLKB1
CLKB1#
CKEB1

J7
K7
K9

<39>
<39>
<39>
<39>
<39>

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

DRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

RV178
240_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@

2

2
56_0402_1%

CLKB0
CLKB0#
CKEB0

+1.5VGS

96-BALL
SDRAM DDR3
K4W1G1646G-BC11

DIS@
CLKB1# 1
RV181

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DIS@
CLKB1 1
RV180

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

CV272
0.01U_0402_16V7K
DIS@

MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5

M8
H1

+1.5VGS

BA0
BA1
BA2

2

2

1

CLKB0# 1
RV175

D7
C3
C8
C2
A7
A2
B8
A3

VREFC_A2_B
VREFD_Q2_B

1

<39>

M2
N8
M3

<39>
<39>
<39>

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB29
MDB26
MDB30
MDB27
MDB31
MDB25
MDB28
MDB24

UV25

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB42

VREFC_A4_B
VREFD_Q4_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB6
QSB7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

DRAM_RST# T2
L8

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

D

+1.5VGS

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

RV179
240_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C

96-BALL
SDRAM DDR3
K4W1G1646G-BC11

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

MDB[0..63]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

2

<39>

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

D

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

UV23

VREFCA
VREFDQ

1

VREFC_A1_B M8
VREFD_Q1_B H1

1

UV22

96-BALL
SDRAM DDR3
K4W1G1646G-BC11

X76@

X76@

X76@

CV273
0.01U_0402_16V7K
DIS@

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS
1

VREFD_Q4_B
1

0.1U_0402_16V7K
DIS@
CV281

1

1

RV197
4.99K_0402_1%
DIS@

2

2

2

RV196
4.99K_0402_1%
DIS@

2

2

2
1

0.1U_0402_16V7K
DIS@
CV280

2

1

15mil

VREFC_A4_B

2

1
RV195
4.99K_0402_1%
DIS@
2

2

2

2
1

1

RV194
4.99K_0402_1%
DIS@

RV189
4.99K_0402_1%
DIS@

15mil

VREFD_Q3_B
0.1U_0402_16V7K
DIS@
CV279

2

1

RV188
4.99K_0402_1%
DIS@

15mil

VREFC_A3_B
0.1U_0402_16V7K
DIS@
CV278

RV193
4.99K_0402_1%
DIS@

1

1

1

1
1

1

VREFD_Q2_B

1

RV192
4.99K_0402_1%
DIS@

RV187
4.99K_0402_1%
DIS@

15mil

2

2

VREFC_A2_B

2

2

1

RV186
4.99K_0402_1%
DIS@

15mil
0.1U_0402_16V7K
DIS@
CV277

RV191
4.99K_0402_1%
DIS@

2

2

2
1

1

15mil

2

2

RV190
4.99K_0402_1%
DIS@

RV185
4.99K_0402_1%
DIS@

VREFC_A1_B

2

1

0.1U_0402_16V7K
DIS@
CV274

VREFD_Q1_B

RV184
4.99K_0402_1%
DIS@

15mil

0.1U_0402_16V7K
DIS@
CV276

RV183
4.99K_0402_1%
DIS@

15mil

0.1U_0402_16V7K
DIS@
CV275

2

RV182
4.99K_0402_1%
DIS@

1

1

B

1

B

+1.5VGS
+1.5VGS

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

Compal Secret Data

Security Classification
Issued Date

1

2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

2

1

2

1

2

1

2

1

2

1

2

A

Compal Electronics, Inc.
ATI_SeymourXT_M2_VRAM_B

Size
C
Date:

5

1

1U_0402_6.3V6K
DIS@
CV318

2

1U_0402_6.3V6K
DIS@
CV317

1

1U_0402_6.3V6K
DIS@
CV316

2

1U_0402_6.3V6K
DIS@
CV315

1

2

1U_0402_6.3V6K
DIS@
CV314

1

1U_0402_6.3V6K
DIS@
CV313

2

1U_0402_6.3V6K
DIS@
CV312

1

1U_0402_6.3V6K
DIS@
CV311

2

1U_0402_6.3V6K
DIS@
CV310

1

1U_0402_6.3V6K
DIS@
CV309

2

1U_0402_6.3V6K
DIS@
CV308

1

1U_0402_6.3V6K
DIS@
CV307

2

1U_0402_6.3V6K
DIS@
CV306

1

2

1U_0402_6.3V6K
DIS@
CV305

1

1U_0402_6.3V6K
DIS@
CV304

2

1U_0402_6.3V6K
DIS@
CV303

1

1U_0402_6.3V6K
DIS@
CV302

2

1U_0402_6.3V6K
DIS@
CV301

1

+1.5VGS

1U_0402_6.3V6K
DIS@
CV300

2

1U_0402_6.3V6K
DIS@
CV299

1

10U_0603_6.3V6M
DIS@
CV298

2

10U_0603_6.3V6M
DIS@
CV297

1

10U_0603_6.3V6M
DIS@
CV296

2

10U_0603_6.3V6M
DIS@
CV295

1

0.1U_0402_16V7K
DIS@
CV294

2

0.1U_0402_16V7K
DIS@
CV293

1

0.1U_0402_16V7K
DIS@
CV292

2

0.1U_0402_16V7K
DIS@
CV291

1

0.1U_0402_16V7K
DIS@
CV290

2

0.1U_0402_16V7K
DIS@
CV289

1

0.1U_0402_16V7K
DIS@
CV288

2

0.1U_0402_16V7K
DIS@
CV287

1

2

0.1U_0402_16V7K
DIS@
CV286

A

1

0.1U_0402_16V7K
DIS@
CV285

2

0.1U_0402_16V7K
DIS@
CV284

1

0.1U_0402_16V7K
DIS@
CV283

0.1U_0402_16V7K
DIS@
CV282

+1.5VGS

Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012
1

Sheet

41

of

56

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

Page 1

Issue Description

Rev.

Solution Description

1

08,11,12

DIMM

11/07/28

COMPAL

The M3 traces are routed to the Sandy Bridge Processor reserved pins for DDR3
VREF

Intel CHKLST Rev1.5 required

0.1

2

18,19

PCH

11/07/28

COMPAL

VCCDMI, V_PROC_IO change to +VCCP from +1.05VS

Intel CHKLST Rev1.5 required

0.1

3

09,10

CPU

11/07/28

COMPAL

remove decoupling cap for +VCC_CORE, +VCCP, +VCC_GFXCORE_AXG, owner change to
PWR

Intel CHKLST Rev1.5 required

0.1

4

10

CPU

11/07/28

COMPAL

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent
(SA) VR controller.

Intel CHKLST Rev1.5 required

0.1

D

D

5
6
7
8
9
10
11
12
13
C

14

C

15
16
17
18

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HW-PIR
Size
Date:

5

4

3

2

Document Number

Rev
1.0

Wednesday, February 01, 2012
1

Sheet

42

of

56

B

PC907
100P_0402_50V8J

PR904
100K_0402_1%
1
2

PR902
2.2K_0402_5%
2
1

2

PD900
DA204U_SOT323~D

PR905
10K_0402_1%

@

1

@
PD902
SM24_SOT23

PR906
1

PSID-5

2

10K_0402_1%

SUYIN_060003FA002G202NL

+3VLP

1VSB_N_003

1

EC_SMB_DA1 <24,44>

D

3

2
PR912
0_0402_5%
2VSB_N_002 2
G

2

2
PR919

1

POK

EC_SMB_CK1 <24,44>

PR913
100_0402_5%
1
2

0_0402_5%

1

PBATT1 battery connector (Follow E3)

+3VALW
<45>

PR914
100_0402_5%
1
2

ALLTO_C144FE-109A7-L

PR909
100K_0402_1%

PC910
.1U_0402_16V7K

PR911
10K_0402_1%
1
2

PR910
100_0402_5%
1
2

1

CLK_SMB
DAT_SMB
BATT_PRS
SYS_PRES

PR908
22K_0402_1%
1
2

S

B+_BIAS
1

1

2

@
PD905
RB751V-40_SOD323-2
1
2

3

B+

2

3

PD903

2

+RTCBATT

PQ902
TP0610K-T1-E3_SOT23-3

PC909
0.1U_0402_25V6

1

1

+

2

-

@
2

3

PD904 @
PESD24VS2UT_SOT23-3

PC908
0.22U_0603_25V7K

1

1

2

BATT_TEMP <24,44>

SMART
Battery:
01.BATT1+
02.BATT2+
03.CLK_SMB
04.DAT_SMB
05.BATT_PRS
06.SYS_PRES
07.BAT_ALERT
08.GND1
09.GND2

2
1
2

E

+5VALW

VSB_N_001

PQ903
2N7002KW _SOT323-3

VIN
2

3

2

PR927
13K_0402_1%
130W /90W #

<24>

<24>

PR916 @
13K_0402_1%

VCIN0_PH

1
2

2

1

2
G

+3VLP
2

2

D

<24>
S

1

S

65W /90W #

1 1

1 1
2
G

+3VALW

<24> VCIN1_PH

VS_N_002

1
2
@930 PR923
22K_0402_1%

@

D

PR926 @
6.81K_0402_1%

PR917

65W/90W#

90W

High

Low

130W

PH900
100K_0402_1%_TSM0B104F4251RZ

.1U_0402_16V7K

1

1

499K_0402_1%

65W
PC915 @

130W/90W#

Low

2

51_ON#

2

<25>

PC912 @930
0.1U_0402_25V6

2N7002KW_SOT323-3
PQ906

2

VS
1

1
PC911 @930
0.22U_0603_25V7K

2

2

@930 PR922
100K_0402_1%

PR918
90.9K_0402_1%

3

1

2N7002KW_SOT323-3
PQ904

3

PR915
332K_0402_1%
1

N1

2

PR921 @930
68_1206_5%
2

@930 PR920
68_1206_5%
2

@930
PQ905
TP0610K-T1-E3_SOT23-3

1

1

LL4148_LL34-2

2

<24,44>

VS_N_001
1

@930 PD907
2

1

BATT+

PH901 under CPU botten side :
CPU thermal protection at 90 degree C

3

ADP_I

PD906 @930
LL4148_LL34-2

1

3

1

PQ900
MMST3904-7-F_SOT323~D

2
B

PESD24VS2UT_SOT23-3

PBATT9 @
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
GND 10
GND 11

3

PD901
BAV99W-7-F_SOT-323-3~D

S
1

PSID-1

3

32
4

2
1

6
1

1M_0402_1%

PSID-2
C

JRTC9
@

2

2

PC900
1000P_0402_50V7K
2
1

1

BATT++

PR930

1

+5VALW

2
1
PR907
100K_0402_1%

PL900
SMB3025500YA_2P
1
2
PC906
0.01U_0402_25V7K

1
2

1
2
2

PC905
100P_0402_50V8J

BATT+

PC916
0.1U_0402_25V6

2

BATT++

1

2

PQ907A
SSM6N7002FU-2N_SOT363-6

2

200K_0402_1%

BATT+

PQ907B

1

1
PR928

5

PS_ID <24>

+5VALW

PR900
15K_0402_1%
1
2

PR929

1M_0402_1%

3

<15,24,35,44>

2

1
ACIN

1

PSID

2

PL902
BLM18BD102SN1D_0603~D
2
1

+3VALW

2
G

1

ACES_50299-00501-003

2

PR903
33_0402_5%
3 PSID-3 1
2
PQ901
FDV301N_NL_SOT23-3~D

D

Erp lot6 Circuit VIN

SSM6N7002FU-2N_SOT363-6

1
2

PR901
@ 0_0402_5%
1

PC904
100P_0402_50V8J

1
2

1

PC903
1000P_0402_50V7K

6
7

PC902
100P_0402_50V8J

GND
GND

2

1
2
3
4
5

2

1
2
3
4
5

D

+5VALW

PR931
1.2K_1206_5%~D

1

1

@ PJPDC9

PC901
1000P_0402_50V7K

ADPIN

C

VIN

PL901
SMB3025500YA_2P
1
2

3

A

High

4

4

@930

PU900
G920AT24U_SOT89-3

@930
A

OUT

IN

@930

GND
1

PR925

1

2
1U_0603_25V6K

4.7U_0603_6.3V6K~D

+3VLP

@930 PR924
0_0603_5%
1
2

PC913
2
1

3

PC914
2
1

+CHGRTC

2
200_0805_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@930

Date:

B

C

PWR-DCIN / BATT CONN / OTP
Document Number

Rev
1.0

LA-8241P
W ednesday, February 01, 2012
D

Sheet

43

of

56

A

B

Iada=0~4.62A(90W)

P3

CC = 3.52A (Normal)

ADP_I = 19.9*Iadapter*Rsense

8
7
6
5

CV = 13.3V
B+

PR102
0.01_1206_1%

PQ102
AO4407AL_SO8
1
2
3

1
PR136
1.2K_1206_5%~D

747@

PC131

309K/0402

747@

0.1U/0402

4
2

PC105
2200P_0402_25V7K~D
2
1

1
1

PC106
0.1U_0603_25V7K
2
1

PC104
4.7U_0805_25V6-K
2
1

PC103
4.7U_0805_25V6-K
2
1

24

DH_CHG

PHASE

23

LX_CHG

BATT_TEMP

PQ106A
SSM6N7002FU-2N_SOT363-6

6
2
<24,43>

EAI

4

EAO

LGATE

20

3

VREF

PGND
CSOP

19
18

7

CE

CSON

17

PC128
0.1U_0402_10V7K
2
1

747@ PC125

29

VFB
GND
NC

16

1 PR130

747@

2

3
4

3
1 2

BATT+

2

6

BATT+

3

@

3

731@ PC126
1
2

TP
747@ PC129
0.1U_0603_25V7K
1
2

ISL88731CHRTZ-T_QFN28_5X5~D

0.22U_0603_25V7K
@ PC130
1

2

0.1U_0603_25V7K

PR127

0/0402

PR107

PC112

ISL88731C BQ24747

ISL88731C BQ24747

ISL88731C BQ24747

PU100 ISL88731C BQ24747

PR122

@

200k

PC134

0.01u

@

PC108

0.1u

@

PR133

@

100k

PR123

@

7.5k

PC129

@

0.1u

PR106

10

0

PR112

100k

@

PR129

@

10k

PC126

0.22u

0.1u

PR107

10

0

PR117

158k

@

PC117

@

2200p

PR127

10

0

PC112

0.047u

0.1u

PR113

210k

309k

PC124

@

56p

PR111

4.7

@

PC131

0.1u

220p

PC123

@

120p

PC110

1u

@

747@

731@ for ISL88731C

747@

PC132
0/0402

@

@

100_0402_5%

@

0.1U/0603
747@

2

4

ISL88731C BQ24747

PC126

AO4712L_SO8~D

DL_CHG

3
2
1

15 VFB

PQ113B
SSM6N7002FU-2N_SOT363-6

PQ107
DDTC115EUA-7-F_SOT323

PR121
PL100
0.01_1206_1%
10UH_PCMB063T-100MS_4A_20%
1
2 CHG
1
4

5
6
7
8

5

PQ110

747@
2

PQ113A
SSM6N7002FU-2N_SOT363-6

PC120
10U_0805_25V5K~D
2
1

UGATE

2

1

2

2

ACOFF

AO4466L_SO8~D

VDDP_LDO

<24>

5
6
7
8
1

3
2
1

21

2

PC115

4
VDDP

1

10K_0402_5%

PC119
10U_0805_25V5K~D
2
1

FBO

25 BST

5
PR132
VDDP_LDO

PC118
10U_0805_25V5K~D
2
1

6

PD101 747@
BAT54HT1G_SOD323-2~D
1
2

2

PC122
10U_0805_25V5K~D
2
1

VICM

0.1U_0603_25V7K
1
2

2BST_CHGA

1U_0603_10V6K

NC

8

26

PC135

PQ108

1

27
CSSN

SDA

28

1

SCL

9

CSSP

VDDSMB

10

BOOT

V1

2

2
1

2

731@ PC108
0.1U_0603_25V7K

731@
2

PR107
1

10_0402_5%

10_0402_5%

PR106
1
PC107 731@
2

0.1U_0603_25V7K
1
2

ACOK

11

12

V1

1

PQ112B

13

PR114
0_0603_5%
1
ICOUT

PR115
1

1
747@ PR113

BQ24747

A

PR111 731@
4.7_0603_5%
1

2

1
2

PR113
210K_0402_1%

731@
1

@

2

S

SSM6N7002FU-2N_SOT363-6

1
2
3
4

5

ACIN

10K_0402_5%

1U_0603_10V6K
2
1

@

56P_0402_50V8~D

PC124
2

MAX8731_REF

747@ PR129
1

VIN

<24>

DCIN

2

VIN

100K_0402_1%

PR110
47K_0402_1%

PC110 731@
1U_0603_10V6K

7.5K_0402_5%

MAX8731_REF

731@ PC134
0.01U_0402_25V7K
2
1

PQ111 @
SSM3K7002FU_SC70-3

PR123
1

2200P_0402_50V7K

@ PC133
0.01U_0402_25V7K
2
1

1

D

731@ PC132
0.01U_0402_25V7K
2
1

PC131
.1U_0402_16V7K

2

1
1

2

731@

PU100

ACOFF

22

14

For DT Mode

4

DCIN
ACSETIN

PR108
200K_0402_1%
1
2

PR128
0_0402_5%
1

PC102
5600P_0402_25V7K~D
1
2
3

747@ PC117
2
1

120P_0402_50VNPO~D

<6,24> H_PROCHOT#

3

4

2

747@ PR122
200K_0402_5%

747@
1

<24,43> ADP_I

2
G

PQ106B
SSM6N7002FU-2N_SOT363-6

PC109

0.1U_0402_10V7K
2
1

<24,43> EC_SMB_DA1

747@ PC123
1
2

3

<24,43> BATT_TEMP

731@
PU100

ICREF

PR101
200K_0402_1%
747@

PR133
100K_0402_1%
2
1MAX8731_REF

2

3

PR125
100_0402_1%

@ PC127
1U_0603_25V6K

731@
PC112
0.047U_0603_25V7M
1
2

2

PR120
0_0402_5%
1
2

0_0402_5% 0_0402_5%
PR135
PR134
2 1
2

1

BATT_TEMP

VIN

PR119
0_0402_5%
1
2

1

2

PC111
1U_0603_25V6K

<24,43> EC_SMB_CK1

1

1

6

PQ112A
SSM6N7002FU-2N_SOT363-6

10K_0402_5%

PC116
0.1U_0402_10V7K
2
1

2

PR126
4.7K_0402_5%
2
1

<24>
PR131
2

@

+5VALW

731@
PR117
158K_0402_1%
2
1

ACIN

PR109
10_1206_1%
1
2

PR116
2
49.9K_0402_1%

1

1

CHG_B+

PL101
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

PC113
1000P_0402_50V7K
1
2

<15,24,35,43>

PQ109
DDTC115EUA-7-F_SOT323

1

2

1
2

PR118
47K_0402_5%
1
2

@

8
7
6
5

CSIP

1
2
3
4

ACIN

1
ACOFF

PC101
0.1U_0603_25V7K

3

PQ105B
SSM6N7002FU-2N_SOT363-6

2

ACIN

5

<24,43> BATT_TEMP
5

3

CSIN

VIN
PR105
150K_0402_1%

731@
PR112
100K_0402_1%
2
1VDDP_LDO

6
1

2

PQ105A
SSM6N7002FU-2N_SOT363-6

3

2

4

2

1

PQ104
DDTC115EUA-7-F_SOT323

V1

2

1

2

PC100
2.2U_0805_25V6K
PR104
1
2 2
1
3.3_1210_5%

PR103
200K_0402_1%

1

1
3.3_1210_5%
2

1

PR100

1
PQ103
PDTA144EU PNP_SOT323

2

4

1
2
3

4

1
2
3

D

PR127
731@ 10_0402_5%
2
1

P2

8
7
6
5

C

PR124
4.7_1206_5%

PQ100
AO4407AL_SO8

PQ101
AO4409L_SO8

PC121
680P_0402_50V7K

VIN

0.01u

@

PC125

@

1u

PD101

@

747@ for BQ24747

4

BAT54HT1G

0.1U/0603

PR106

747@

@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0/0402

Date:

B

C

PWR-Charger
Document Number

Rev
1.0

LA-8241P
W ednesday, February 01, 2012
D

Sheet

44

of

56

A

B

C

D

E

2VREF_6182
PC201

1

2

1

1

1U_0603_16V6K

0.1U_0402_25V6

0.1U_0402_25V6
@
PC202

1

5

1
2

PC209
4.7U_0805_25V6-K

PC208
2200P_0402_50V7K
2
1

2

3
2
1

RT8205LZQW(2) WQFN 24P PWM
PQ205
AON7702A_DFN8-5

+

PC213
330U_6.3V_M

1

2

2

1
2

1

1

B++

@

2

1
2

PC217
1U_0603_10V6K
2
1

ENTRIP2
3

PC216
4.7U_0805_10V6K

+5VALWP

@

PC215
680P_0603_50V7K

18

4

PR210
4.7_1206_5%
2
1

LG_5V

SNUB_5V

19

PL201
3.3UH_PCMC063T-3R3MS_6A_20%
1
2

NC

LX_5V

1

5

ENTRIP1
2

1
ENTRIP1

3
VIN

VREG5
17

16

13

20

BST1_5V 2

3
2
1

1
2
3

BST_5V 1
2
2.2_0603_5%
UG_5V

@
PR212
200K_0402_1%

1

4
PC211

0.22U_0603_10V7K
PR208POK <43>

VL

@

PC218
0.1U_0402_25V6

3

2VREF_6182

N_3_5V_001

5
4

1

SSM6N7002FU-2N_SOT363-6

1

PR215
1

0_0402_5%
2

PR214
100K_0402_5%

1

2.2K_0402_5%
2

2

VL

PJP202
1

+5VALWP

PJP203
2

+5VALW

+3VALWP

3/5V_EN-2 2

1

1

2

1

2

+3VALW

5VALWP
TDC 5.6A
Peak Current 8A
OCP current 9.6A
TYP
H/S Rds(on) :27mohm ,
L/S Rds(on) :11mohm ,

MAX
34mohm
14mohm

PAD-OPEN 4x4m

3

PC219
4.7U_0603_10V6K

2
PAD-OPEN 4x4m
PJP200

PAD-OPEN 4x4m

2

1

PAD-OPEN 4x4m
PJP204

PQ201
DTC115EUA_SC70-3
2
1
PR217
40.2K_0402_1%

FB1

LGATE1

AON7702A_DFN8-5

PR213
1

@930

REF

LGATE2

PQ203
AON7408L_DFN8-5

PQ200B
2

@930

4

PHASE1

EN

2

TONSEL

PHASE2

<24>
VCOUT0_PH
PQ204

PQ200A

VS

ENTRIP2

22
21

BZV55-B5V1_SOD80C2
PR211
@ 0_0402_5%
1
2

SSM6N7002FU-2N_SOT363-6

1
2
PR216
150K_0402_1%

5

BOOT1

GND

1
2
3
2

1

24
23

UGATE1

15

12

VO1

UGATE2

PR200
499K_0402_1%
1
2

B++

PR206
110K_0402_1%
2

PGOOD

BOOT2

@

PD200

PR204
20K_0402_1%
2

1

6

1
2

9

11

5

1

VREG3

UG_3V 10

LG_3V

B++

6 ENTRIP1

MAX
34mohm
14mohm

VO2

8

4

2

@

BST_3V

LX_3V

@

SNUB_3V

PC212
330U_6.3V_M

2

<24> VCOUT0_PH

P PAD

7

@

PC214
680P_0603_50V7K

+

PR209
4.7_1206_5%

1

<28> EC_ON_35V

25

PC210
0.22U_0603_10V7K
BST1_3V 1 PR207 2
2
1
2.2_0603_5%

PL200
3.3UH_PCMC063T-3R3MS_6A_20%
1
2

+3VALWP

3.3VALWP
TDC 5.4A
Peak Current 7.7A
OCP current 9.2A
TYP
H/S Rds(on) :27mohm ,
L/S Rds(on) :11mohm ,

PU200

PC206
10U_0805_6.3V6M

4

2

FB2

PQ202
AON7408L_DFN8-5

2

3

PR205
110K_0402_1%
1

5

1
2

PC205
4.7U_0805_25V6-K

PC204
2200P_0402_50V7K
2
1

PC203
0.1U_0402_25V6
2
1

+3VLP

FB_5V 1

14

1UH_PCMB061H-1R0MS_7A_20%
1
2

FB_3V

ENTRIP2

B++

2

PR203
20K_0402_1%
1
2

PL202

2

PR202
30.9K_0402_1%
1
2

PC207
0.1U_0402_25V6
2
1

PR201
13.7K_0402_1%
1

B+

@ PC200

2

SKIPSEL

1

4

4

2012/01/17

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

PWR-3VALWP/5VALWP
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
E

45

of

56

A

B

C

D

1

1

 VFB=0.6V
Vo=VFB*(1+PR401/PR404)=0.6*(1+20K/10K)=1.8V

1
2

+1.8VSP
TDC 2.6A
Peak Current 3.8A
OCP current 4.5A

PC404
22U_0805_6.3V6M

1
2

PR400
10K_0402_1%

PC400
22U_0805_6.3V6M

22P_0402_50V8J

2

PC402
1

1
2

NC

SY8033BDBC_DFN10_3X3

2

2

@ PR401
47K_0402_5%

PR403
20K_0402_1%

1

EN_1.8VSP

1

2

2

1

PR402 100K_0402_5%

PC405
0.22U_0402_16V7K

SUSP#

FB

1.8VSP_FB

1

<10,24,27,28,47,48>

11

TP

EN

7

5

6

+1.8VSP

2

SVIN

3

PL400
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
1

8

LX

1.8VSP_LX

PR404
4.7_1206_5%

PVIN

2

1SNUB_1.8VSP 2

9

LX

PC401
680P_0603_50V7K

PC403
22U_0805_6.3VAM

PVIN

2

1

PAD-OPEN 3x3m

10

NC

1.8VSP_VIN

1

@
2

PG

PJP400
1

4

PU400

+3VALW

2

2

PJP401

+1.8VSP

1

@
2

+1.8VS

PAD-OPEN 3x3m

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

PWR-1.8VSP
Document Number

Rev
1.0

LA-8241P
W ednesday, February 01, 2012
D

Sheet

46

of

56

5

4

3

2

1

@ PJP500
2 2
1 1

+V1.05S_VCCPP_B+

B+

SW _+V1.05S_VCCPP

FB_+V1.05S_VCCPP

4

VFB

V5IN

7

+V1.05S_VCCPP_5V

RF_+V1.05S_VCCPP

5

TST

DRVL

6

LG_+V1.05S_VCCPP

TP
1

2

PC506
0.22U_0402_16V7K

+5VALW
1

11

2 PC500
1U_0603_10V6K

TPS51212DSCR_SON10_3X3
PR504
470K_0402_1%

3
2
1

2

4

C

2

1

PC509
PR507 @ 1000P_0402_50V7K

2

1

PC504
4.7U_0805_25V6-K

2

1

PC503
4.7U_0805_25V6-K
2
1

PC501
2200P_0402_50V7K
2
1

PC502
0.1U_0402_25V6
2
1

PL500
1UH_PCMC063T-1R0MN_11A_20%
1
2

+VCCP

PR505
@ 4.7_1206_5%

@

PC508

@ 1000P_0402_50V7K

PC507

UG_+V1.05S_VCCPP

8

0.1U_0402_10V7K

9

SW

2

DRVH

EN

1

TRIP

3

D

1

2

PR500
1
2
2.2_0603_5%

2

1
2 TRIP_+V1.05S_VCCPP
47.5K_0402_1%
EN_+V1.05S_VCCPP

1

<10,24,27,28,46,48> SUSP#

10

3
2
1

VBST

PQ501

PR503
150K_0402_5%
1
2

BST_+V1.05S_VCCPP

PGOOD

5

PU500

1
PR502

PC505
.1U_0603_25V7K
2
1

1

4

<49> +V1.05S_VCCP_PWRGOOD

2

1

PQ500

PR501
100K_0402_5%

SIR818DP-T1-GE3_POWERPAK8-5~D

D

5

2

+3VS

SIR472DP-T1-GE3_POWERPAK8-5~D

JUMP_43X118

C

+VCCP

PR506
@ 1.2K_0402_1%

PR508
0_0402_5%
2
1

VCCIO_SENSE

<9>

2

4.99K_0402_1%
2
1

1

PR509
10K_0402_1%

@ PJP501

B

+VCCP

1

2

PAD-OPEN 4x4m

B

+1.05VS
+V1.05S_VCCP
TDC 11A
Peak Current 16A
OCP current 19A
TYP
H/S Rds(on) 10mohm ,
L/S Rds(on) :3mohm ,

MAX
14.5mohm
3.6mohm

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Issued Date

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PWR-V1.05S_VCCPP
Size

Document Number

Rev
1.0

LA-8241P
Date:

W ednesday, February 01, 2012

Sheet
1

47

of

56

4

3

2

1

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.2A

PJP301
VLDOIN_1.5V

PR301
1
2
2.2_0603_5%

1.5V_B+
SIR472DP-T1-GE3_POWERPAK8-5~D
PQ300

B

GND

3

VTTREF

4

VTTREF_1.5V

VDDQ

5

+1.5V

PR300
1M_0402_1%
1
2

1U_0402_6.3VX5R

1
2

PR308
0_0402_5%
1
2

C

PR305
10K_0402_1%
2
1

PR307
10K_0402_1%

S5_1.5V
PC300

1

PC314 220P_0402_50V8J~D
1
2

1.5V_FB

1.5V_B+

PC310
0.033U_0402_16V7~D

FB

S3
7

S5
8

VDD

TON

VDDP

9

1

11

PC311
1U_0603_10V6K

PR306
200K_0402_5%
1
2

PC307
10U_0805_6.3V6M

1
2

20

19

17

18
BOOT

VTT

2

RT8207MZQW _W QFN20_3X3

PGOOD

2 PC309
12
1U_0603_10V6K
VDD_1.5V

2

VTTSNS

6

5

1

VLDOIN

CS

UGATE

16
PHASE

13

1

CS_1.5V

+5VALW

<10,24,27,28,46,47> SUSP#
1.5VP
TDC 14A
Peak Current 20A
OCP current 24A
TYP
H/S Rds(on) :10mohm ,
L/S Rds(on) :3mohm ,

PGND

21

PC306
10U_0805_6.3V6M

2
1
5

1
2

PC305
2200P_0402_50V7K

1
2
3

1

4

2

<24,27,28> SYSON

14

PAD

VTTGND

2

@

LGATE

PU300

PC313
@ .1U_0402_16V7K

1

C

15

10

2

4

PR304
5.1_0603_5%

+5VALW

2

PC308
330U_2.5V_M

DL_1.5V

PR302
7.15K_0402_1%
1
2

D

+0.75VSP

SW _1.5V

4

1

+

SIR818DP-T1-GE3_POWERPAK8-5~D
PQ302

1

PC304
0.22U_0603_10V7K

1
2
3

@

@

BOOT_1.5V

DH_1.5V

5

680P_0603_50V7K
4.7_1206_5%
PC312
PR303
2
1 SNUB_1.5V 2
1

PL300
0.68UH_PCMC063T-R68MN_15.5A_20%
1
2

1
2
3

1
2

PC303
0.1U_0402_25V6

1
2

PC302
4.7U_0805_25V6-K

1
2

PC301
4.7U_0805_25V6-K

JUMP_43X118
D

+1.5V

+1.5V

1
PAD-OPEN1x1m

@ PJP302
2 2
1 1

SIR818DP-T1-GE3_POWERPAK8-5~D
PQ301

B+

2

2

5

S3_1.5V

+1.5V

MAX
14.5mohm
3.6mohm

B

@

+0.75VSP

1

PJP300

+0.75VS

2
PAD-OPEN 3x3m

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Issued Date

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PWR-1.5V/0.75VSP
Size

Document Number

Rev
1.0

LA-8241P
Date:

W ednesday, February 01, 2012

Sheet
1

48

of

56

5

4

3

VID [0]
0
0
1
1

D

VID[1]
0
1
0
1

2

1

VCCSA Vout
0.9V
0.8V
0.725V
0.675V

D

2

output voltage adjustable network

1

PC600
680P_0402_50V7K

2

SNUB_+1.5VP

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

PR600
4.7_1206_5%

PL601

1K_0402_5%
PR603
1
2

PG

VOUT
VID1

EN
VID0

1
PR605
100K_0402_5%
2
1

3
4
5

+VCCSA_EN

6

+3VS

1

2

0_0402_5%
PR601
<47>
+V1.05S_VCCP_PWRGOOD

C

+VCCSAP
PC609
22U_0805_6.3VAM
1
2

7

LX

FB

PC607
22U_0805_6.3VAM
1
2

8

SVIN

SA_PGOOD <24>

PC606
22U_0805_6.3VAM
1
2

9

2

PC604
22U_0805_6.3VAM
1
2

10
1

LX

PL600
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

+VCCSA_PHASE

@ PC601
0.1U_0402_10V7K
2
1

PC610
68P_0402_50V8J
+VCCSAP_FB 2

PVIN

1

1K_0402_5%
PR604
1
2

11

GND

1

PC612
10U_0805_6.3V6M

1

2

2

PC611
10U_0805_6.3V6M
2
1

+VCCSA_PWR_SRC

13

HCB1608KF-121T30_0603
1
2

2200P_0402_50V7K
PC605

+3VALW

0.1U_0603_25V7K
PC603
2
1

C

PU600
SY8037BDCC_DFN12_3X3
12
PVIN
LX

PR606
100_0402_5%
2
1

PR602
0_0402_5%
2
1

VCCSA_VID0 <10>

VCCSA_SENSE <10>

VCCSA_VID1 <10>

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

B

B

@
PJP601

+VCCSAP

1

2

+VCCSA

PAD-OPEN 4x4m

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR-VCC_SAP
Size

5

4

3

2

Document Number

Rev
1.0

LA-8241P
Date:

Wednesday, February 01, 2012
1

Sheet

49

of

56

24.9K_0402_1%
10P_0402_50V8J
FBA2

1
2
10_0402_1%

PC707
1
2

560P_0402_50V7K
PR708 2

1

2

1K_0402_1%

COMPA1

2

5.11K_0402_1%

1

PC708
2

2

SWN1A

2

1K_0402_1%

2

PR714
2

1

1
LG2

BST1

<51>

PC719

1

SW2

<51>

SW1

<51>

1 2.2U_0603_10V7K

2

PR728 2
0_0402_5%

LG1

<51>

HG1

<51>
PR730 2 BST1_1 2
1
1
2.2_0603_5%
PC721
0.22U_0603_10V7K

CSP2A

+5VS

DROOP

TSENSE

<24>

IMVP_IMON

PC734
1
2

24.9K_0402_1%

2
PR749
1

PUT COLSE
TO VCORE
Phase 1
Inductor

SWN2

<51>

2

CSP3

B

TSENSE

CSSUM
PC733
2
1500P_0402_50V7K

1

<51>

PR745 1

2

@

PH702
100K_0402_1%_TSM0B104F4251RZ

CSREF

2 PC735
560P_0402_50V7K

1

PR748 2
130K_0603_1%

SWN1

1

PR750 2
130K_0603_1%

SWN2

PUT COLSE
TO VCORE
HOT SPOT

1 PR751 2NTC_PH201 1 PR752 2
75K_0402_1%
165K_0402_1%
PH703
2

1
220K_0402_5%_ERTJ0EV224J
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

2

SWN1

1

PR744
2
6.98K_0402_1%

2

<51>

PC730
1000P_0402_50V7K

1

8.25K_0402_1%

2

CSREF

PC731
0.047U_0402_16V7K
2
1

CSP1

1

CSREF

1000P_0402_50V7K

2
6.98K_0402_1%

CSREF

2

PC736
1
2

1

<51>

1

PR766
13.3K_0402_1%

DRVEN
PC723
2
.1U_0402_16V7K

806_0402_1%

@ PR736
0_0402_5%

Option for
2 phase CPU

PR740

CSP1
CSP2
CSP3

1

2

A

5

C

Option for
1 phase GFX

+5VS

PR733 2
43.2K_0402_1%
CSP2

1

CSCOMP

1

1
PR754

1

HG2
6132P_VCCP

PC718
PR723 2 BST2_1 2
1
1
2.2_0603_5%
<51>
0.22U_0603_10V7K

PR742
PC728
2
1COMP_CPU1 2
1
6.34K_0402_1%
1800P_0402_50V7K

PR747
0.033U_0603_16V7

PC732
2
1

PC729
1
2FB_CPU3 1
2
10_0402_1%
0.033U_0603_16V7
PR746
FB_CPU2
1
2

CSCOMP

100K_0402_1%_TSM0B104F4251RZ

+5VS
BST2

1

10P_0402_50V8J
PR741
PC727
1
2FB_CPU1 1
2
49.9_0402_1%
560P_0402_50V7K

8.06K_0402_1%

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

PR767
13.3K_0402_1%

PC725
2
1

1 PR739 2
1K_0402_1%

TRBST#

PH701

PUT COLSE
TO V_GT
HOT SPOT

6132_PWMA <51>

PC726
0.047U_0402_16V7K
2
1

B

PR743

CSP2A
CSP1A
TSENSEA

DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA

PC722
1000P_0402_50V7K
VSP

ILIM_CPU
DROOP

2

PR737
1
2
0_0402_5%

VSN

1
2
PR738 12.7K_0402_1%

1

PR735
1
2
0_0402_5%

<9> VCCSENSE

PR717
1
2
28K_0402_1%

1

.1U_0402_16V7K

VGATE

TRBST#
FB_CPU
COMP_CPU

2
<6,15>

<9> VSSSENSE

<51>

.1U_0402_16V7K

VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT NCP6132BMNR2G_QFN60_7X7
SW2
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1

2
<24> VR_HOT#

SWN1A

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

PR732
10K_0402_5%

6.98K_0402_1%
2

PC713
1
2

TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM

PC720
2
1

1

PR731
75_0402_1%

0.01U_0402_25V7K

1
2

1

+VCCP

PR712
1

TSENSEA

PC710
1000P_0402_50V7K

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

2
.1U_0402_16V7K

PR722
1
2
54.9_0402_1%

PR721 2

1
<9> VR_SVID_DAT
<9> VR_SVID_ALRT#
<9> VR_SVID_CLK

CSP1A

PC709
0.047U_0402_16V7K

PU700

1
2.2U_0603_10V7K
6132_VDDBP
2
PR720
VR_RDYA
3
VR_ON_CPU
1
2
4
<24>
VR_ON
PC717
0_0402_5%
VR_SVID_DAT1 5
VR_SVID_ALRT# 6
PR726
PR724
VR_SVID_CLK
7
95.3K_0402_1%
0_0402_5%
8
1
2 VBOOT
10K_0402_1%
ROSC_CPU
1 PR725 2VR_SVID_DAT1
1
2
9
VRMP
CPU_B+
1
2
10
VR_HOT#
11
PR727 1K_0402_1%
VGATE
12
13
14
+3VS
DIFF_CPU
15

130_0402_1%

1
2

.1U_0402_16V7K

PC716

6132_VDDBP

2.2U_0603_10V7K
PR718 2
1
2_0603_5%
PC714
6132_VCC
1
2

+5VS

VR_RDYA

+VCCP

PC753
1
2

CSREFA

1000P_0402_50V7K

CSREFA <51>

CSSUMA

2

1

+5VS
PR716 @
10K_0402_1%

C

1

PC711
1000P_0402_50V7K

PR765
1
2
0_0402_5%

+3VS

1PR713
2
15.8K_0402_1%
CSCOMPA

69.8K_0603_1%

<10> VSS_AXG_SENSE

PC705
1
2

DROOPA

2

CSREFA

1500P_0402_50V7K
PR711

PR753
1
2
0_0402_5%

1

1K_0402_1%


165K_0402_1%

1

<10> VCC_AXG_SENSE

CSCOMPA

PR706

PR709

1

PR705

220K_0402_5%_ERTJ0EV224J

NTC_PH203

1

2

PC706
1
2

1

PR707

D

8.25K_0402_1%

806_0402_1%

PUT COLSE
TO GT
Inductor

PH700

2

8.06K_0402_1%

2

1

1

1

PR703
FBA1

2

PC704
0.033U_0603_16V7
2
1

1

PC702
1
2

PR702
TRBSTA#

.1U_0402_16V7K
1 PR701 2

1

2

PC701
2

1

D

PR704
1
2
75K_0402_1%

PC700
0.033U_0603_16V7
FBA3
1
2

2

PC703
1
2

PR700
10_0402_1%
1
2

3

680P_0402_50V7K

4

1200P_0402_50V7K

5

3

2

CPU Core
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

50

of

56

5

4

3

2

1

VCC_core
TDC 32A
Peak Current 53A
OCP current 65
Load line -1.9mV/A
FSW=300kHz
DCR 1.1mohm +/-5%
TYP
H/S Rds(on) :10mohm ,
L/S Rds(on) :3mohm ,

B+
PJP700
1

1

CPU_B+

JUMP_43X118
PC712

1
+
2

1
PC724

2

+
2

4

HG2

3
2
1

PL701
0.36UH_FDU1040J-H-R36M=P3_33A_20%
SW2

<50>

1

4

LG2

CSREF <50>
3
2
1

10_0402_1%
SWN1

<50>

PC745 @
680P_0402_50V7K

1

GFX_HG

PC750
0.22U_0603_10V7K
4

PU701
BST

FLAG

PWM

DRVH

9
3
2
1

1
2

4

EN

GND
DRVL

6
5

GFX_LG

4

PC749
4.7U_0805_25V6-K
2
1

PC748
4.7U_0805_25V6-K
2
1

4

3
2
1

2

1

NCP5911MNTBG_DFN8_2X2
PC751
2.2U_0603_10V7K

A

@ 4.7_1206_5%

PR761
0_0402_5%

SW

1

3

2

2
@ 680P_0402_50V7K

VCC

1VCC_GFX

PQ706
SIR818DP-T1-GE3_POWERPAK8-5~D
PC752
PR762
2
1 SNUB_GFX1
2

2

1

4

PC744
4.7U_0805_25V6-K
2
1

B

MAX
14.5mohm
3.6mohm

+VCC_GFXCORE_AXG

Issued Date

PR764 1

CSREFA <50>

10_0402_1%

SWN1A <50>

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR-VCC_SAP
Size

4

3

2

Document Number

Rev
1.0

LA-8241P
Date:

5

<50>

680P_0402_50V7K

+VCC_GFXCORE_AXG
TDC 21.5A
Peak Current 33A
OCP current 40A
Load line -3.9mV/A
FSW=300kHz
DCR 1.1mohm +/-5%
TYP
H/S Rds(on) :10mohm ,
L/S Rds(on) :3mohm ,

PL704
0.36UH_FDU1040J-H-R36M=P3_33A_20%

GFX_SW
5

4

+5VS

1

CSREF

SWN2

PJP701
2

PR758
10_0402_1%
2
1

PC746 @

JUMP_43X118

8
7

PC743
4.7U_0805_25V6-K
2
1

2

V2N_CPU

1

3

3
2
1

DRVEN

1EN_GFX

PQ705
SIR818DP-T1-GE3_POWERPAK8-5~D

<50>

PR760
DRVEN 2
2K_0402_1%

5

<50> 6132_PWMA

PC747
4.7U_0805_25V6-K
2
1

GFX_BST_1
2

2

5

PR759

PQ704
SIR472DP-T1-GE3_POWERPAK8-5~D

B

2.2_0603_5%

C

PR756 @
4.7_1206_5%

B+

1

2

SNUB_CPU2

2

@

1

V1N_CPU

@
2

GFX_BST

1

3

2

2
1SNUB_CPU1

PR757

2

3
2
1

4

PR755 @
4.7_1206_5%

PQ708
SIR818DP-T1-GE3_POWERPAK8-5~D

5

PQ707
SIR818DP-T1-GE3_POWERPAK8-5~D

QC-SV 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=32A
R_LL=1.9m ohm
OCP~65A

PQ702
SIR818DP-T1-GE3_POWERPAK8-5~D

5
4

LG1

3
2
1

<50>

@

4
1

<50>

5

2

3
2
1

1

3

+VCC_CORE
PL702
0.36UH_FDU1040J-H-R36M=P3_33A_20%

5

4
1

SW1

PC742
4.7U_0805_25V6-K
2
1

5

PC741
4.7U_0805_25V6-K
2
1

PC740
4.7U_0805_25V6-K
2
1

PC739
4.7U_0805_25V6-K
2
1

<50>

+VCC_CORE

PQ701
SIR472DP-T1-GE3_POWERPAK8-5~D

3
2
1
C

<50>

D

CPU_B+

PQ703
SIR818DP-T1-GE3_POWERPAK8-5~D

4

HG1

PQ700
SIR472DP-T1-GE3_POWERPAK8-5~D

5

CPU_B+

<50>

MAX
14.5mohm
3.6mohm

100U_25V_M~D

@
2

100U_25V_M~D

D

Wednesday, February 01, 2012
1

Sheet

51

of

56

4

3

2

1

VCCSENSE_VGA

@ PJP800
2 2
1 1

VGA@

BST

1

2

EN

PC805 VGA@
0.1U_0603_25V7K

PC804 VGA@
4.7U_0805_25V6-K

2

1

PC803 VGA@
4.7U_0805_25V6-K
2
1

PC802 VGA@
2200P_0402_50V7K
2
1

PC801 VGA@
0.1U_0402_25V6
2
1

1
2

1
2

+
2 3

1

1
2

5

1
PR802 VGA@
2.2_0603_5%

2 3

1

1000P_0603_50V7K

C

10

VID1
9

11 BST_VGA_CORE 2

+

PC812 VGA@
10U_0805_6.3V6M

V0

5

PC813 @

1

PC811 VGA@
10U_0805_6.3V6M

SW _VGA_CORE

4

PR808 @
4.7_1206_5%

PC810 VGA@
10U_0805_6.3V6M

12

+VGA_CORE

PC800 VGA@
470U_D2_2VM_R4.5M

SW

4

VGA@ PQ802
SIR818DP-T1-GE3_POWERPAK8-5~D

V1

4

VGA@ PL800
0.36UH_FDU1040J-H-R36M=P3_33A_20%
1
2

3
2
1

UG_VGA_CORE

TPS51518RUKR_QFN20_3X3

+5VALW

VGA@ PQ801
SIR818DP-T1-GE3_POWERPAK8-5~D

VGA_CORE_5V
LG_VGA_CORE

3
2
1

DRVL

14

D

5

1
15

13

V2

1U_0603_10V6K
PC807 VGA@

VGA@ PQ800
SIR472DP-T1-GE3_POWERPAK8-5~D

3
2
1
2

16
MODE

TRIP

17

18

20

SLEW

GND

V5IN

DRVH

3

PR834 VGA@
2.49K_0402_1%
1
2

PC814
1

4700P_0402_25V7K
19 1
2

VSNS

V3

VREF

C

4

PR807
43K_0402_1%

GSNS

VID0

2
PR833 VGA@
105K_0402_1%
2
1

1

2

8

G

2

1

PGOOD

1

PU801

7

PR811 VGA@
5.11K_0402_1%
1
2
1

D

S

3

VGA@
21

PQ803

2N7002KW _SOT323-3

PAD

VGA@

PR815 VGA@
76.8K_0402_1%

6

PR814 VGA@
2.49K_0402_1%

1

2

2

PR813 VGA@
5.11K_0402_1%

1

PR810 VGA@
5.11K_0402_1%

2

VGA@
2

D

1

1

5

2

2

10P_0402_50V8J

B+

JUMP_43X118
0_0402_5%

1

PR830

VGA@ PC829

2

10P_0402_50V8J

VGA@ PR835
0_0402_5%
1
2

<38> VSSSENSE_VGA

PC828 VGA@
1
2

VGA_CORE_B+

2

<38>

PC809 VGA@
470U_D2_2VM_R4.5M

5

3
VGA@ PC830
0.1U_0402_10V7K
2
1

2

+VGA_CORE
TDC 22A
Peak Current 30A
OCP current 36A
FSW=350kHz
DCR 1.1mohm +/-5%
TYP
H/S Rds(on) :10mohm ,
L/S Rds(on) :3mohm ,

@

VGA@

0.9V

0

1

1

0.875V

1

0

0

0.85V

1

0

1

0.825V

1

VGA@
2

VGA@ PR827
10K_0402_1%

PC825
1

2

22P_0402_50V8J

PJP804
A

1
1

1

0

1

1

0.8V

+VGA_PCIEP

2

2

1

@
1

Thames XT

+1.0VGS

1
2

VGA@ PC818
22U_0805_6.3VAM

1
2

1

B

Chelsea Pro

VGA_PCIE

1.0V

0.95V

PR825

6.81K

5.9K

A

JUMP_43X79

0.775V

2012/01/17

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

2

1
2

2

1
2
PR825 VGA@
5.9K_0402_1%
2
1

+VGA_PCIEP

VGA@ PC824
22U_0805_6.3VAM

VGA@

FB_PCIE

VGA@ PC821
22U_0805_6.3VAM

@ PR828
47K_0402_5%

1

200K_0402_5%

SS

TP

2EN_PCIE

1

6

SY8036LDBC_DFN10_3x3

VGA@ PR829
4.7_1206_5%

2
PXS_PWREN

FB

SNUB_PCIE

0.925V

0

EN

3

1

1

1

SVIN

5

LX

LX_PCIE

2

0

0

<16,36>

VGA@ PR826

2

0

8

2

PC822

0.95V

PVIN

LX

7

0

9

11

0

1

0

1K_0402_5%
VGA@ PR837
<35>

Core Voltage Level

<35>

GPU_VID2

GPU_VID0

GPU_VID0

GPU_VID1

GPU_VID1

VGA@ PR836
1K_0402_5%
1
2

VGA@

PVIN

VGA@ PC826
680P_0603_50V7K

1

VGA@
PC819
22U_0805_6.3VAM

10

+VGA_PCIEP

JUMP_43X79

.1U_0402_16V7K

Chelsea Pro

VGA@ PL801
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

4

PU800
PCIE_B+

1

0.1U_0402_10V7K

1

LX

PC806

2

VGA@

2

1

EN_VGA_CORE

2

2

1

1

2

B

@

PG

PJP805
+3VALW

1

<24,36,53> PX_MODE

+VGA_PCIE
TDC 3.6A
Peak Current 5.2A
OCP current 6A

PC823
0.1U_0402_10V7K

PR800
0_0402_5%
1
2

VGA@
PR804
2.2K_0402_5%
1
2

MAX
14.5mohm
3.6mohm

2

VGA@

10K_0402_1%

1

<17,36> VGA_PW RGD

PR801 VGA@

+3VS

VGA@ PC820
22U_0805_6.3VAM

2
G
PR803 VGA@
10K_0402_1%
1
2

<35> GPU_VID2

@

1

D

1

VGA@

0_0402_5%~D
PR839

S

PR838
0_0402_5%~D
1
2

PQ804
SI2301CDS-T1-GE3_SOT23-3

4

3

2

VGA_COREP
Document Number

Rev
1.0

LA-8241P
W ednesday, February 01, 2012

Sheet
1

52

of

56

A

B

C

D

+VDDCI
TDC 2.8A
Peak Current 4A
OCP current 6A

1

2
1

2

1

1

PR1006 VGA@
10_0402_5%

2

1

VGA@ PR1003

VGA@ PC1005
22U_0805_6.3V6M

FB=0.6Volt

+VDDCIP

VGA@ PC1003
22U_0805_6.3V6M
2
1

SY8036LDBC_DFN10_3x3

VGA@ PC1000
22P_0402_50V8J
2
1

1
2

PR1001 VGA@
4.7_1206_5%

FB_VDDCIP

2

VGA@

6

LX_VDDCIP

4.99K_0402_1%

VGA@ PC1002
680P_0603_50V7K

1

PR1005
1M_0402_5%
@
1

VGA@

2

PR1002 10K_0402_5%

PC1004
0.1U_0402_10V7K

2
2

1

11

TP

EN

FB
LX

SVIN

3

PG

8
EN_VDDCIP
5

LX

SS

PVIN

2

1

9

LX

VGA@ PC827
0.1U_0402_10V7K

PVIN

7

10

1

PC1001 VGA@
22U_0805_6.3V6M

2

1

JUMP_43X79

<24,36,52> PX_MODE

PL1000 VGA@
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

4

PU1000 VGA@
2

2

PJ1000
@
1 1
2

+3VALW

1

PR1004
2

1

VDDCI_SEN

<38>

0_0402_5%
+3VGS

1

VGA@
VGA@
PR1007
29.4K_0402_1%

1

PR1008 VGA@
10K_0402_5%
PR1009 VGA@
10K_0402_5%
2
1

1

PR1000
10K_0402_1%
2

D

@ PC1006
4700P_0402_25V7K

<35>

PR1010 @
100K_0402_5%
2

2

PQ1000 VGA@
2N7002W -T/R7_SOT323-3

1

S

3

VDDCI_VID

1

2
G

2

2

VGA@

2

1

2

VDDCI_VID
High

1V

Low

0.9V

@

3

3

PJ1001

+VDDCIP

1

2

+VDDCI

PAD-OPEN 4x4m

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Deciphered Date

2013/01/16

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

+VDDCIP
Document Number

Rev
1.0

LA-8241P
W ednesday, February 01, 2012
D

Sheet

53

of

56

5

4

+VCC_CORE

2

+VCC_CORE

1

2

3

1
PC1201
10U_0805_6.3VAM

2

1
PC1202
10U_0805_6.3VAM

2

1
PC1203
10U_0805_6.3VAM

2

1

Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_GFXCORE_AXG

1
PC1204
10U_0805_6.3VAM

2

PC1205
10U_0805_6.3VAM

Socket Bottom

5 x 22 µF (0805)
5 x (0805) no-stuff
sites

Socket Top

7 x 22 µF (0805)
2 x (0805) no-stuff
sites

+VCC_GFXCORE_AXG

D

2

1

2

1

2

1

2

1

2

1

2

PC1218
22U_0805_6.3V6M

2

1

PC1217
22U_0805_6.3V6M

2

+VCC_CORE

1

PC1216
22U_0805_6.3V6M

2

1
PC1210
10U_0805_6.3VAM

PC1215
22U_0805_6.3V6M

2

1
PC1209
10U_0805_6.3VAM

PC1214
22U_0805_6.3V6M

2

1
PC1208
10U_0805_6.3VAM

PC1213
22U_0805_6.3V6M

2

1
PC1207
10U_0805_6.3VAM

PC1212
22U_0805_6.3V6M

2

1
PC1206
10U_0805_6.3VAM

PC1211
22U_0805_6.3V6M

1

+VCCP

2
1

+

+

2

2

330U_D2_2V_Y

2

1

2

1
PC1250
22U_0805_6.3V6M

2

1
PC1251
22U_0805_6.3V6M

2

PC1247
330U_D2_2V_Y

2

1

2

C

1

1
PC1252
22U_0805_6.3V6M

1

2

2

+
PC1253
22U_0805_6.3V6M

2

+

2

+

2

PC1255
330U_D2_2VM_R9M

1

2

PC1245
22U_0805_6.3V6M

PC1242
22U_0805_6.3V6M

1

2

1

PC1233
22U_0805_6.3V6M

2

1

PC1254
330U_D2_2VM_R9M

PC1241
22U_0805_6.3V6M

C

PC1249
22U_0805_6.3V6M

1

1

PC1246

1

2

PC1244
22U_0805_6.3V6M

2

2

1

PC1232
22U_0805_6.3V6M

PC1240
22U_0805_6.3V6M

2

PC1231
22U_0805_6.3V6M

2

2

PC1200
330U_D2_2VM_R9M

PC1239
22U_0805_6.3V6M

2

1

PC1243
22U_0805_6.3V6M

2

1

2

1

PC1230
22U_0805_6.3V6M

PC1238
22U_0805_6.3V6M

1

2

2

PC1229
22U_0805_6.3V6M

2

1

2

1

+VCCP
1
1
PC1228
22U_0805_6.3V6M

1

2

1

1

PC1227
22U_0805_6.3V6M

2

1

1

PC1226
22U_0805_6.3V6M

1

1

PC1225
22U_0805_6.3V6M

2

PC1223
22U_0805_6.3V6M

PC1237
22U_0805_6.3V6M

2

1
PC1222
22U_0805_6.3V6M

PC1236
22U_0805_6.3V6M

2

1
PC1221
22U_0805_6.3V6M

PC1235
22U_0805_6.3V6M

2

1
PC1220
22U_0805_6.3V6M

PC1234
22U_0805_6.3V6M

2

1
PC1219
22U_0805_6.3V6M

PC1224
22U_0805_6.3V6M

1
1

D

1

2

PC1256
22U_0805_6.3V6M

+VCC_CORE
1
+

B

1
+

PC1257

330U_D2_2VM_R9M
2 3

2

1

1

+

+

PC1261 @
330U_D2_2V_Y

2

1
PC1258
330U_D2_2V_Y

+

1
PC1259

330U_D2_2VM_R9M
2 3

+

PC1260
330U_D2_2V_Y

2

B

PC1262 @
330U_D2_2V_Y

2

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/01/17

Issued Date

Deciphered Date

2013/01/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PROCESSOR DECOUPLING
Size

Document Number

Rev
1.0

LA-8241P
Date:

W ednesday, February 01, 2012

Sheet
1

54

of

56

5

4

3

2

1

Power block
CPU OTP

Page 43

Turn Off

D

Input
Switch Page 44

DC IN

D

B+
+3VALWP: TDC:5.4A
+5VALWP: TDC:5.6A
RT8205LZQW(2) WQFN

CHARGER
CC:0A~3.52A
CV:13.3V(6cell)
ISL88731CHRTZ-T

+1.8VSP: TDC:2.6A
SY8033BDBC

Always
Page 45

SUSP#
Page 46

Page 44
C

Battery

C

SUSP#

+VCCP: TDC:11A
TPS51212DSCR

Page 47

+1.5V/+0.75VSP: TDC:14A/0.7A
RT8207MZQW

SYSON

Page 48

+VCCSAP: TDC:4.2A
SY8037DCC
+VGA_CORE
TDC:23.4A
TPS51518RUKR

PX_MODE
B

+VCC_CORE
TDC: 32A
NCP6132BMNR2G

VR_ON

+VCC_GFXCORE_AXG
TDC: 21.5A
NCP6132BMNR2G

VR_ON
A

+V1.05S_VCCP_PWRGOOD
Page 49

B

Page 52

PXS_PWREN

+VGA_PCIEP: TDC:3.5A
SY8036LDBC

Page 52

+VDDCIP: TDC:2.8A
SY8036LDBC

Page 53

PX_MODE

Page 50/51

A

Page 50/51

2012/1/17

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/1/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PROCESSOR DECOUPLING
Document Number

Rev
0.2

LA-8241P
Wednesday, February 01, 2012

Sheet
1

55

of

56

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

Page 1

Issue Description

1

44

Charger.

11/12/08

Frank

Change PR113 for

2

45

3.3VALWP/5VALWP

11/12/08

Frank

3

53

+VDDCIP

11/12/08

Frank

1

Solution Description

temperature and voltage test.

Rev.

Change PR113 from 316k to 309k for Charger IC BQ24747RHDR.
Remove PR132.

X00

Design change.

Change PC219 from 1uF to 4.7uF.

X00

Fine tune time sequence.

Change PR1002 from 100k to 0ohm.
Remove PR1005 and PC1004.

X00

D

D

C

C

B

B

A

A

2012/01/17

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/01/16

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PWR-PIR
Document Number

Rev
1.0

LA-8241P
Wednesday, February 01, 2012

Sheet
1

56

of

56

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Format                          : application/pdf
Creator                         : 
Title                           : Compal LA-8241P - Schematics. www.s-manuals.com.
Subject                         : Compal LA-8241P - Schematics. www.s-manuals.com.
Create Date                     : 2012:02:01 13:36:34Z
Creator Tool                    : PScript5.dll Version 5.2
Modify Date                     : 2014:04:25 23:05:54+03:00
Metadata Date                   : 2014:04:25 23:05:54+03:00
Producer                        : GPL Ghostscript 8.15
Document ID                     : uuid:3402254b-b3fe-4f68-b806-a972ede2ed51
Instance ID                     : uuid:6ff56448-6736-4b5a-9787-9cdf1069b18b
Page Count                      : 57
Keywords                        : Compal, LA-8241P, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

EXIF Metadata provided by EXIF.tools