Compal LA 8241P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-8241P QCL00/QCL20 - Schematics. Free.

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Page Count: 57

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Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

1 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

Cover Page

Schematic Document

QCL00_QCL20

PCB NO :

BOM P/N :

MODEL NAME :

LA-8241P

4619GP31L21

Inspron A5 & Vostro 3560 (Intel Chief River)

Rev: 1.0

Discrete AMD Thames-XT

Ivy Bridge(rPGA) + Panther Point(mainstream)

2012-02-01

@ : Nopop Component

CONN@ : Connector Component

KB930@ : ENE KB930 Implemented

KB9012@ : ENE KB9012 Implemented

EXP@ : Express Card Implemented

ConfigBOM P/NMB Type

VOS@ : Only for Vostro

INS@ : Only for Inspiron

UMA@ : Only for UMA

SE@ : Seymour M2

4619GP31L01

46@ : for 46 level CH@ : Chelsea M2

FFS@ : Only for Free Fall Sensor

X76@ : VRAM Group

4619GQ31L01

4619GQ31L21

Inspiron DIS

Inspiron UMA

Vostro DIS

Dell / Compal Confidential

Vostro UMA

GCLK@ : Green CLK implemented

AMP@ : External Amplifier implemented

KBBL@ : Keyboard Back Light implemented

DIS@ : Only for Discrete

TH@ : Thames-XT

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Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

2 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

Block Diagram

Project Code : QCL00 / QCL20

File Name : LA-8241P

Compal Confidential

Daughter board

35W QC

AMD

DDR3

DDR3

VRAM * 4

64M*16

RTL8105E (10/100)

Port 2

Express Card

34mm Slot

P.28

Card Reader

RTS5139

Daughter board

3 in 1 Socket

Finger Print

Port 10

Port 8

USB 3.0 Conn. 2 -( USB Charger )

Daughter board

Digital Mic.

4MB

Dashboard

Button x3

page 32

LVDS

CRT

CRT Conn.

SPI

PS/2

35W DC

rPGA 988

8GB Max

Thames-XT /

P.34~39

PEG 3.0 x16

VRAM * 4

64M*16

64bit

64bit

page 11,12

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

DDRIII-DIMM X2

1.5V DDR3 1333 MHz

Half

P.32

( Full )

Mini Card-2 (mSATA)

P.32

USB 3.0 Conn. 1

( Half )

Digital Camera

Mini Card-1 (WLAN)

Port 12

Port 4

Port 3,4

P.22

P.32

rPGA 988

LPC Bus

page 24

page 25

ENE KBC

KB9012 /

KB930

Int.KBD

page 25

Touch Pad

page 26

SPI ROM

Daughter board

USB2.0 Port 0,1

FFS

P.25

Fan Control

P.13

P.25

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

P.27

Port 0

24-26 W

LVDS Conn.

HDMI Conn.

Port 2 SATA ODD Conn. P.29

Audio Codec

CX20672

Mic. Jack

Headphone Jack

Amplifier

HD Audio

Port 1,2

USB 3.0 Conn. 3

P.33

USB 3.0

Port 2,3

PCI-E x1

Mini Card-1

WLAN / BT4.0

100MHz 100MHz

5GB/s

DMI x4FDI x8

P.32 P.32

Port 3 Port 1

SPI

Ethernet

RTL8111F (10/100/1000)

RJ45

2.7GT/s

Processor

Ivy Bridge

Intel

PCH HM77

P.5~10

Panther Point

Intel

P.29

SPI ROM

P.13

P.41

P.40

HDMI

P.22

P.23

P13~20

P.22

P.30

Dual Channel

Memory Bus (DDR3)

SATA HDD Conn. P.29

CPU XDP

Conn. P.6

33MHz

SATA3.0

BGA 989 Balls

only for Vostro 3560

USB2.0

Port 11 USB 3.0 Conn. 4

SPI

P.13

SPI ROM

2MB

128K

reserved for KB930

Port 1

Port 5

Daughter board

Daughter board

P.32

P.32

Daughter board

Chelsea Pro

Int. Speaker R/L

TPA3113D2 P.31

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Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

3 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

Block Diagram

LA-8241P M/B

LED/B

Project Code : QCL00 / QCL20

File Name : LA-8241P

Compal Confidential

LS-8244P (Ins)

80 pin

10 pin

JBTB1

FFC

Lid (Vostro)

Led1

Touch Pad

LCD Panel

Wire

Camera

4 pin

4 pin

JCR2

4 pin

JPWR

10 pin

JCR1JLED

8 pin

JFC

26 pin

JEXP

10 pin-Hot Bar

LS-8242P (Ins) IO/B

SW1

Led2 Led3 Led4

Led1

4 pin-Hot Bar

8 pin-Hot Bar

SW1 SW2 SW3

Led1 Led2 Led3

8 pin

FFC

4 pin

FFC

LS-8245P (Ins)

LED/B

LS-8241P (Ins) LED/B

JTP

4 pin

JLVDS

40 pin

TP Led (Vos)

Lid (Inspiron)

Bottom Side

Top Side

Card Reader/B

Express Card

LS-8243P (Ins)

Finger Print/B

LS-8252P (Vos)

LS-8251P (Vos)

LS-8253P (Vos)

LS-8254P (Vos)

6 pin

JFP

LS-8255P (Vos)

L R

40 pin

(Inspiron)

(Vostro)

Led2

TP Led (Ins)

4 pin

FFC

4 pin

FFC

(Vostro)

1

26

LS-8256P (Vos)

4 pin-Hot Bar

4 pin-Hot Bar

A

A

1 1

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

4 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

Notes List

Symbol Note :

: means Digital Ground

: means Analog Ground

MINI2

EC_SMB_CK2

SOURCE

KB9012

MINI1 BATT SODIMM

SMBUS Control Table

PCH_SML1CLK

PCH_SML1DATA PCH

EC_SMB_DA2

EC_SMB_CK1

EC_SMB_DA1

KB9012

MEM_SMBCLK

V

MEM_SMBDATA

V

USB conn.4

MINI CARD-1 (WLAN)

NC

8

9

NC

10

USB conn.3

11

2

3

1

4

USB PORT#

0

DESTINATION

6

5

7

12

13

PCH

USB conn.2 - Power Share

ODD

HDD

SATA5

SATA4

SATA3

SATA2

SATA1

DESTINATION

SATA0

SATA

Express Card

Lane 7

Lane 8 None

None

Lane 5

Lane 6

MINI CARD-1 (WLAN)

PCI EXPRESS

Lane 1

DESTINATION

Lane 2

Lane 3

Lane 4

10/100/1G LAN

None

None

NC

Express Card

Camera

NC

None

None

CLKOUT_PCIE7 None

None

CLKOUT_PCIE6

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE0

DESTINATIONDIFFERENTIAL

CLK

CLKOUT_PEG_B

FLEX CLOCKS DESTINATION

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

CLKOUTFLEX0

None

MINI CARD-1 WLAN

Express Card

10/100/1G LAN

None

None

Card Reader

PCH_LOOPBACK

EC LPC

PCI0

CLKOUT

None

PCI1

PCI2

PCI3

DESTINATION

None

None

PCI4

None

NC

Finger Print

USB conn.1

SSD

None

None

None

None

0.3

0.1

1.0

0.2

BOARD ID Table

Board ID

0

1

2

3

4

5

6

7

PCB Revision

0.1

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Board ID

Rb V min

0

1

2

3

0 0 V

0.168 V

0.375 V 0.503 V

0.819 V

0.362 V

0.621 V

AD_BID

V typ

AD_BID

V

AD_BID

max

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

200K +/- 5%

3.300 V

0 V 0.155 V

4

5

6

7NC

0.634 V

0.958 V

1.650 V

1.359 V

1.372 V

1.851 V 2.200 V

3.300 V

1.838 V

1.185 V

0.945 V

Board ID Table for AD channel

0x00-0x0C

EC AD3

0x0D-0x1C

0x1D-0x30

0x31-0x49

0x4A-0x69

0x6A-0x8E

0x8F-0xBB

0xBC-0xFF

8.2K +/- 5%

2.433 V

2.420 V

0.250 V

None

None

Express

Card

Thermal

Sensor FFS VGA

V

V

XDP

PCH

V

Charger

PCH_SML0DATA

PCH_SML0CLK PCH

V V

Link

VGA Thermal

Sensor

V

0.2

0.3

1.0

QCL00 QCL20

V

V

0.2

0.3

1.0

QCL01

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FDI_CTX_PRX_N1

FDI_CTX_PRX_N4

FDI_CTX_PRX_N6

FDI_CTX_PRX_P1

FDI_CTX_PRX_P6

FDI_FSYNC0

FDI_CTX_PRX_N0

FDI_CTX_PRX_N2

FDI_CTX_PRX_N3

FDI_CTX_PRX_N5

FDI_CTX_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

FDI_CTX_PRX_P7

FDI_LSYNC0

FDI_LSYNC1

FDI_FSYNC1

FDI_INT

PEG_COMP

+EDP_COM

PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P0

PEG_GTX_C_HRX_P1

PEG_GTX_C_HRX_P2

PEG_GTX_C_HRX_P3

PEG_GTX_C_HRX_P4

PEG_GTX_C_HRX_P5

PEG_GTX_C_HRX_P6

PEG_GTX_C_HRX_P7

PEG_HTX_GRX_N0

PEG_HTX_GRX_N2

PEG_HTX_GRX_N4

PEG_HTX_GRX_N3

PEG_HTX_GRX_N1

PEG_HTX_GRX_N5

PEG_HTX_GRX_N6

PEG_HTX_GRX_N7

PEG_HTX_GRX_P0

PEG_HTX_GRX_P2

PEG_HTX_GRX_P4

PEG_HTX_GRX_P1

PEG_HTX_GRX_P3

PEG_HTX_GRX_P6

PEG_HTX_GRX_P5

PEG_HTX_GRX_P7

PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_N1

DMI_CTX_PRX_P0<15>

DMI_CRX_PTX_P0<15>

DMI_CTX_PRX_N1<15>

DMI_CRX_PTX_N1<15>

DMI_CTX_PRX_P3<15>

DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_P2<15>

DMI_CTX_PRX_N0<15>

DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P2<15>

DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P1<15>

DMI_CRX_PTX_N0<15>

DMI_CRX_PTX_N2<15>

DMI_CRX_PTX_P1<15>

DMI_CTX_PRX_N2<15>

FDI_CTX_PRX_N0<15>

FDI_CTX_PRX_N1<15>

FDI_CTX_PRX_N2<15>

FDI_CTX_PRX_N3<15>

FDI_CTX_PRX_N4<15>

FDI_CTX_PRX_N5<15>

FDI_CTX_PRX_N6<15>

FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>

FDI_CTX_PRX_P1<15>

FDI_CTX_PRX_P2<15>

FDI_CTX_PRX_P3<15>

FDI_CTX_PRX_P4<15>

FDI_CTX_PRX_P5<15>

FDI_CTX_PRX_P6<15>

FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>

FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>

FDI_LSYNC1<15>

PEG_HTX_C_GRX_P0 <34>

PEG_HTX_C_GRX_P1 <34>

PEG_HTX_C_GRX_P2 <34>

PEG_HTX_C_GRX_P3 <34>

PEG_HTX_C_GRX_P4 <34>

PEG_HTX_C_GRX_P5 <34>

PEG_HTX_C_GRX_P7 <34>

PEG_HTX_C_GRX_P6 <34>

PEG_HTX_C_GRX_N0 <34>

PEG_HTX_C_GRX_N1 <34>

PEG_HTX_C_GRX_N3 <34>

PEG_HTX_C_GRX_N2 <34>

PEG_HTX_C_GRX_N6 <34>

PEG_HTX_C_GRX_N7 <34>

PEG_HTX_C_GRX_N5 <34>

PEG_HTX_C_GRX_N4 <34>

PEG_GTX_C_HRX_N0 <34>

PEG_GTX_C_HRX_N1 <34>

PEG_GTX_C_HRX_N2 <34>

PEG_GTX_C_HRX_N3 <34>

PEG_GTX_C_HRX_N4 <34>

PEG_GTX_C_HRX_N5 <34>

PEG_GTX_C_HRX_N6 <34>

PEG_GTX_C_HRX_N7 <34>

PEG_GTX_C_HRX_P2 <34>

PEG_GTX_C_HRX_P1 <34>

PEG_GTX_C_HRX_P0 <34>

PEG_GTX_C_HRX_P5 <34>

PEG_GTX_C_HRX_P4 <34>

PEG_GTX_C_HRX_P3 <34>

PEG_GTX_C_HRX_P7 <34>

PEG_GTX_C_HRX_P6 <34>

+VCCP

+VCCP

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

5 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PEG_ICOMPI and RCOMPO signals should be shorted and routed

with - max length = 500 mils - typical impedance = 43 mohms

PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

CC10 220nF_0402_16V7KDIS@

1 2

PCI EXPRESS* - GRAPHICS

DMI

Intel(R) FDI

eDP

JCPU1A

Sandy Bridge_rPGA_Rev1p0

CONN@

DMI_RX#[0]

B27

DMI_RX#[1]

B25

DMI_RX#[2]

A25

DMI_RX#[3]

B24

DMI_RX[0]

B28

DMI_RX[1]

B26

DMI_RX[2]

A24

DMI_RX[3]

B23

DMI_TX#[0]

G21

DMI_TX#[1]

E22

DMI_TX#[2]

F21

DMI_TX#[3]

D21

DMI_TX[0]

G22

DMI_TX[1]

D22

DMI_TX[3]

C21 DMI_TX[2]

F20

FDI0_TX#[0]

A21

FDI0_TX#[1]

H19

FDI0_TX#[2]

E19

FDI0_TX#[3]

F18

FDI1_TX#[0]

B21

FDI1_TX#[1]

C20

FDI1_TX#[2]

D18

FDI1_TX#[3]

E17

FDI0_TX[0]

A22

FDI0_TX[1]

G19

FDI0_TX[2]

E20

FDI0_TX[3]

G18

FDI1_TX[0]

B20

FDI1_TX[1]

C19

FDI1_TX[2]

D19

FDI1_TX[3]

F17

FDI0_FSYNC

J18

FDI1_FSYNC

J17

FDI_INT

H20

FDI0_LSYNC

J19

FDI1_LSYNC

H17

PEG_ICOMPI J22

PEG_ICOMPO J21

PEG_RCOMPO H22

PEG_RX#[0] K33

PEG_RX#[1] M35

PEG_RX#[2] L34

PEG_RX#[3] J35

PEG_RX#[4] J32

PEG_RX#[5] H34

PEG_RX#[6] H31

PEG_RX#[7] G33

PEG_RX#[8] G30

PEG_RX#[9] F35

PEG_RX#[10] E34

PEG_RX#[11] E32

PEG_RX#[12] D33

PEG_RX#[13] D31

PEG_RX#[14] B33

PEG_RX#[15] C32

PEG_RX[0] J33

PEG_RX[1] L35

PEG_RX[2] K34

PEG_RX[3] H35

PEG_RX[4] H32

PEG_RX[5] G34

PEG_RX[6] G31

PEG_RX[7] F33

PEG_RX[8] F30

PEG_RX[9] E35

PEG_RX[10] E33

PEG_RX[11] F32

PEG_RX[12] D34

PEG_RX[13] E31

PEG_RX[14] C33

PEG_RX[15] B32

PEG_TX#[0] M29

PEG_TX#[1] M32

PEG_TX#[2] M31

PEG_TX#[3] L32

PEG_TX#[4] L29

PEG_TX#[5] K31

PEG_TX#[6] K28

PEG_TX#[7] J30

PEG_TX#[8] J28

PEG_TX#[9] H29

PEG_TX#[10] G27

PEG_TX#[11] E29

PEG_TX#[12] F27

PEG_TX#[13] D28

PEG_TX#[14] F26

PEG_TX#[15] E25

PEG_TX[0] M28

PEG_TX[1] M33

PEG_TX[2] M30

PEG_TX[3] L31

PEG_TX[4] L28

PEG_TX[5] K30

PEG_TX[6] K27

PEG_TX[7] J29

PEG_TX[8] J27

PEG_TX[9] H28

PEG_TX[10] G28

PEG_TX[11] E28

PEG_TX[12] F28

PEG_TX[13] D27

PEG_TX[14] E26

PEG_TX[15] D25

eDP_AUX

C15

eDP_AUX#

D15

eDP_TX[0]

C17

eDP_TX[1]

F16

eDP_TX[2]

C16

eDP_TX[3]

G15

eDP_TX#[0]

C18

eDP_TX#[1]

E16

eDP_TX#[2]

D16

eDP_TX#[3]

F15

eDP_COMPIO

A18

eDP_HPD

B16 eDP_ICOMPO

A17

CC25 220nF_0402_16V7KDIS@

1 2

CC28 220nF_0402_16V7KDIS@

1 2

CC27 220nF_0402_16V7KDIS@

1 2

RC2

24.9_0402_1%

12

CC16 220nF_0402_16V7KDIS@

1 2

RC36 24.9_0402_1%

1 2

CC11 220nF_0402_16V7KDIS@

1 2

CC31 220nF_0402_16V7KDIS@

1 2

CC15 220nF_0402_16V7KDIS@

1 2

CC13 220nF_0402_16V7KDIS@

1 2

CC30 220nF_0402_16V7KDIS@

1 2

CC14 220nF_0402_16V7KDIS@

1 2

VSS

JCPU1I

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS161

T35

VSS162

T34

VSS163

T33

VSS164

T32

VSS165

T31

VSS166

T30

VSS167

T29

VSS168

T28

VSS169

T27

VSS170

T26

VSS171

P9

VSS172

P8

VSS173

P6

VSS174

P5

VSS175

P3

VSS176

P2

VSS177

N35

VSS178

N34

VSS179

N33

VSS180

N32

VSS181

N31

VSS182

N30

VSS183

N29

VSS184

N28

VSS185

N27

VSS186

N26

VSS187

M34

VSS188

L33

VSS189

L30

VSS190

L27

VSS191

L9

VSS192

L8

VSS193

L6

VSS194

L5

VSS195

L4

VSS196

L3

VSS197

L2

VSS198

L1

VSS199

K35

VSS200

K32

VSS201

K29

VSS202

K26

VSS203

J34

VSS204

J31

VSS205

H33

VSS206

H30

VSS207

H27

VSS208

H24

VSS209

H21

VSS210

H18

VSS211

H15

VSS212

H13

VSS213

H10

VSS214

H9

VSS215

H8

VSS216

H7

VSS217

H6

VSS218

H5

VSS219

H4

VSS220

H3

VSS221

H2

VSS222

H1

VSS223

G35

VSS224

G32

VSS225

G29

VSS226

G26

VSS227

G23

VSS228

G20

VSS229

G17

VSS230

G11

VSS231

F34

VSS232

F31

VSS233

F29

VSS234 F22

VSS235 F19

VSS236 E30

VSS237 E27

VSS238 E24

VSS239 E21

VSS240 E18

VSS241 E15

VSS242 E13

VSS243 E10

VSS244 E9

VSS245 E8

VSS246 E7

VSS247 E6

VSS248 E5

VSS249 E4

VSS250 E3

VSS251 E2

VSS252 E1

VSS253 D35

VSS254 D32

VSS255 D29

VSS256 D26

VSS257 D20

VSS258 D17

VSS259 C34

VSS260 C31

VSS261 C28

VSS262 C27

VSS263 C25

VSS264 C23

VSS265 C10

VSS266 C1

VSS267 B22

VSS268 B19

VSS269 B17

VSS270 B15

VSS271 B13

VSS272 B11

VSS273 B9

VSS274 B8

VSS275 B7

VSS276 B5

VSS277 B3

VSS278 B2

VSS279 A35

VSS280 A32

VSS281 A29

VSS282 A26

VSS283 A23

VSS284 A20

VSS285 A3

CC32 220nF_0402_16V7KDIS@

1 2

RC158 10K_0402_5%

@

12

CC9 220nF_0402_16V7KDIS@

1 2

CC12 220nF_0402_16V7KDIS@

1 2

CC26 220nF_0402_16V7KDIS@

1 2

CC29 220nF_0402_16V7KDIS@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_BPM#3

XDP_BPM#4

XDP_BPM#0

XDP_BPM#2

XDP_BPM#5

XDP_BPM#6

XDP_BPM#7

XDP_BPM#1

XDP_DBRESET#

XDP_TDI

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

BUFO_CPU_RST#

XDP_TDO

XDP_DBRESET#

XDP_RST#_R

XDP_PRDY#_R

CLK_CPU_ITP#

XDP_HOOK2

XDP_TRST#_R

XDP_PREQ#_R

XDP_DBRESET#

XDP_TCK_R

CLK_CPU_ITP

XDP_TDO

XDP_TDI

XDP_TMS_R

H_CPUPWRGD_XDP

SYS_PWROK_XDP

H_CPUPWRGD

CFD_PWRBTN#_XDP

XDP_BPM#3

XDP_BPM#4

XDP_BPM#0

XDP_BPM#2

XDP_BPM#5

XDP_BPM#6

XDP_BPM#7

XDP_BPM#1

H_CPUPWRGD_R

VDDPWRGOOD

RUN_ON_CPU1.5VS3#

PLT_RST#

XDP_TCK1

CFG10_R

CFG11_R

XDP_BPM#4

XDP_BPM#5

XDP_BPM#6

XDP_BPM#7

VDDPWRGOOD

XDP_BPM#7_R

XDP_TDI_R

XDP_TRST#

BUF_CPU_RST#

SM_RCOMP1

CLK_CPU_DMI#_R

SM_RCOMP0

XDP_TMS

VDDPWRGOOD_R

SM_RCOMP2

H_THERMTRIP#

BUF_CPU_RST#

XDP_PREQ#

XDP_BPM#5_R

XDP_TCK

XDP_BPM#2_R

XDP_DBRESET#_R

CLK_CPU_DMI_R

H_PM_SYNC_R

H_CPUPWRGD_R

XDP_PRDY#

XDP_BPM#4_R

XDP_BPM#1_R

XDP_TDO_R

H_DRAMRST#

XDP_BPM#0_R

H_CATERR#

XDP_BPM#6_R

XDP_BPM#3_R

H_PROCHOT#_R

SYS_PWROK_XDP

XDP_PRDY#_R

XDP_PREQ#_R

XDP_TCK_R

XDP_TMS_R

XDP_TRST#_R

CLK_CPU_DPLL_R

CLK_CPU_DPLL#_R

D_PWG

H_CPUPWRGD_R

H_SNB_IVB#<17>

H_THERMTRIP#<17>

H_CPUPWRGD<17>

H_PROCHOT#<24,44>

H_DRAMRST# <7>

CLK_CPU_DMI# <14>

CLK_CPU_DMI <14>

PCH_SMBCLK<11,12,14,28,29,32>

PCH_SMBDATA<11,12,14,28,29,32>

CLK_CPU_ITP# <14>PBTN_OUT#<15,24>

CLK_CPU_ITP <14>

VGATE<15,50>

XDP_DBRESET# <15>

PM_DRAM_PWRGD<15>

PLT_RST#<16,24,28,32>

PCH_JTAG_TCK<13>

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>

PCH_JTAG_TMS <13>

H_PECI<17,24>

CFG11<8>

CFG10<8>

CFG0<8>

CFG14 <8>

CFG15 <8>

CFG13 <8>

CFG12 <8>

RUN_ON_CPU1.5VS3#<10,27>

H_PM_SYNC<15>

SYS_PWROK<15>

PCH_PWROK<15,24>

+VCCP

+VCCP

+VCCP

+3VS

+VCCP +VCCP

+1.5V_CPU_VDDQ

+3VALW

+3V_PCH

+3VS

+3V_PCH

+VCCP

+3VALW

+VCCP

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

6 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

The resistor

for HOOK2 should be

placed such that the

stub is very small

on CFG0 net

PU/PD for JTAG signals

DDR3 Compensation Signals

RC8

CRB 1.1K

CHECK LIST 0.7 --> 4.75K

INTEL recommand 1.1K

PDG 0.71 rev -->200

Place near JXDP1

Remove DPLL Ref clock (for eDP only)

RC67 0_0402_5%@

1 2

CC63

0.1U_0402_16V7K

1

2

RC30

0_0402_5% @

1 2

RC66 0_0402_5%@

1 2

RC11 0_0402_1%

@

1 2

RC33

43_0402_1%

1 2

RC56

0_0402_1%@

1 2

RC230_0402_5% @

1 2

RC49

0_0402_1%

@

1 2

RC32

75_0402_5%

12

RC4410K_0402_5%

1 2

RC121 0_0402_5%@

1 2

RC68 0_0402_5%@

1 2

RC4651_0402_5% 1 2

RC53

0_0402_1%

@

1 2

RC34

0_0402_5%

@

12

RC4

200_0402_1%

1 2

RC39 1K_0402_1%

1 2

RC125 0_0402_1%@

1 2

CC64

10P_0402_50V8J

@

1 2

T1PAD~D @

RC38 0_0402_1%@

1 2

CC34

0.1U_0402_16V7K

1

2

JXDP1

SAMTE_BSH-030-01-L-D-A

CONN@

GND0

1

OBSFN_A0

3

OBSFN_A1

5

GND2

7

OBSDATA_A0

9

OBSDATA_A1

11

GND4

13

OBSDATA_A2

15

OBSDATA_A3

17

GND6

19

OBSFN_B0

21

OBSFN_B1

23

GND8

25

OBSDATA_B0

27

OBSDATA_B1

29

GND10

31

OBSDATA_B2

33

OBSDATA_B3

35

GND12

37

PWRGOOD/HOOK0

39

HOOK1

41

VCC_OBS_AB

43

HOOK2

45

HOOK3

47

GND14

49

SDA

51

SCL

53

TCK1

55

TCK0

57

GND16

59

GND1 2

OBSFN_C0 4

OBSFN_C1 6

GND3 8

OBSDATA_C0 10

OBSDATA_C1 12

GND5 14

OBSDATA_C2 16

OBSDATA_C3 18

GND7 20

OBSFN_D0 22

OBSFN_D1 24

GND9 26

OBSDATA_D0 28

OBSDATA_D1 30

GND11 32

OBSDATA_D2 34

OBSDATA_D3 36

GND13 38

ITPCLK/HOOK4 40

ITPCLK#/HOOK5 42

VCC_OBS_CD 44

RESET#/HOOK6 46

DBR#/HOOK7 48

GND15 50

TD0 52

TRST# 54

TDI 56

TMS 58

GND17 60

RC61 0_0402_5%@

1 2

RC19

39_0402_1%

@

1 2

RC40 1K_0402_1%

1 2

RC70 0_0402_5%@

1 2

CC36

0.1U_0402_16V7K

1

2

RC51 0_0402_1%@

1 2

RC28 0_0402_5%@

1 2

RC122 0_0402_5%@

1 2

CC35

0.1U_0402_16V7K

1

2

RC150_0402_5% @12

RC8

200_0402_1%

12

RC260_0402_1% @

1 2

RC5825.5_0402_1%

1 2

RC5451_0402_5% 1 2

RC57

130_0402_1%~D

1 2

RC31 0_0402_5%@

1 2

RC60200_0402_1%1 2

RC71 0_0402_5%@

1 2

RC123 0_0402_1%@

1 2

G

D

S

QC1

SSM3K7002F_SC59-3

@

2

13

UC1

74AHC1G09GW TSSOP 5P

B

1

A

2

GND

3Y4

VCC 5

RC59 0_0402_5%@

1 2

RC130_0402_5% @12

RC421K_0402_5%

1 2

RC241K_0402_5% @

1 2

RC69 0_0402_5%@

1 2

RC4551_0402_5% 1 2

RC29 0_0402_5%@

1 2

RC65 0_0402_5%@

1 2

CC33

0.1U_0402_16V7K

1

2

RC62 0_0402_5%@

1 2

RC63 0_0402_5%@

1 2

RC5251_0402_5% 1 2

RC27

1K_0402_5%

@

12

RC37 0_0402_1%@

1 2

RC128

0_0402_5%

@

1 2

RC6

10K_0402_5%

@

12

RC41

56_0402_1%

1 2

RC43

62_0402_5%

1 2

RC64 0_0402_5%@

1 2

RC25 1K_0402_5%

@

1 2

RC127

0_0402_1%

@

1 2

RC124 0_0402_1%@

1 2

RC50 0_0402_1%@

1 2

UC2

SN74LVC1G07DCKR_SC70-5~D

NC

1

A

2

GND

3Y4

VCC 5

RC4751_0402_5% @

1 2

RC221K_0402_5% @

1 2

CLOCKS

MISCTHERMALPWR MANAGEMENT

DDR3

MISC

JTAG & BPM

JCPU1B

Sandy Bridge_rPGA_Rev1p0

CONN@

SM_RCOMP[1] A5

SM_RCOMP[2] A4

SM_DRAMRST# R8

SM_RCOMP[0] AK1

BCLK# A27

BCLK A28

DPLL_REF_CLK# A15

DPLL_REF_CLK A16

CATERR#

AL33

PECI

AN33

PROCHOT#

AL32

THERMTRIP#

AN32

SM_DRAMPWROK

V8

RESET#

AR33

PRDY# AP29

PREQ# AP27

TCK AR26

TMS AR27

TRST# AP30

TDI AR28

TDO AP26

DBR# AL35

BPM#[0] AT28

BPM#[1] AR29

BPM#[2] AR30

BPM#[3] AT30

BPM#[4] AP32

BPM#[5] AR31

BPM#[6] AT31

BPM#[7] AR32

PM_SYNC

AM34

SKTOCC#

AN34

PROC_SELECT#

C26

UNCOREPWRGOOD

AP33

RC4851_0402_5%

1 2

RC55140_0402_1%1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D63

DDR_A_D62

DDR_A_D8

DDR_A_D3

DDR_A_D4

DDR_A_D7

DDR_A_D5

DDR_A_D6

DDR_A_D59

DDR_A_D58

DDR_A_D57

DDR_A_D56

DDR_A_D47

DDR_A_D46

DDR_A_D42

DDR_A_D43

DDR_A_D34

DDR_A_D39

DDR_A_D44

DDR_A_D45

DDR_A_D35

DDR_A_D41

DDR_A_D40

DDR_A_D38

DDR_A_D36

DDR_A_D37

DDR_A_D32

DDR_A_D33

DDR_A_D61

DDR_A_D60

DDR_A_D2

DDR_A_D1

DDR_A_D0

DDR_A_D55

DDR_A_D54

DDR_A_D51

DDR_A_D48

DDR_A_D50

DDR_A_D49

DDR_A_D52

DDR_A_D53

DDR_A_D31

DDR_A_D14

DDR_A_D15

DDR_A_D25

DDR_A_D24

DDR_A_D26

DDR_A_D27

DDR_A_D30

DDR_A_D9

DDR_A_D13

DDR_A_D12

DDR_A_D10

DDR_A_D11

DDR_A_D29

DDR_A_D28

DDR_A_D19

DDR_A_D20

DDR_A_D16

DDR_A_D21

DDR_A_D17

DDR_A_D22

DDR_A_D18

DDR_A_D23

M_CLK_DDR0

M_CLK_DDR#0

DDR_CKE0_DIMMA

M_CLK_DDR1

M_CLK_DDR#1

DDR_CKE1_DIMMA

DDR_A_MA15

DDR_A_DQS0

DDR_A_DQS2

DDR_A_DQS1

DDR_A_DQS6

DDR_A_DQS5

DDR_A_DQS4

DDR_A_DQS3

DDR_A_DQS7

DDR_A_DQS#7

DDR_A_DQS#0

DDR_A_DQS#2

DDR_A_DQS#5

DDR_A_DQS#3

DDR_A_DQS#1

DDR_A_DQS#4

DDR_A_DQS#6

DDR_A_MA0

DDR_A_MA14

DDR_A_MA5

DDR_A_MA4

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA9

DDR_A_MA7

DDR_A_MA6

DDR_A_MA12

DDR_A_MA13

DDR_A_MA8

DDR_A_MA11

DDR_A_MA10

DDR_CS0_DIMMA#

DDR_CS1_DIMMA#

M_ODT0

M_ODT1

DDR_B_D33

DDR_B_D14

DDR_B_D42

DDR_B_D59

DDR_B_D63

DDR_B_D43

DDR_B_D55

DDR_B_D53

DDR_B_D29

DDR_B_D24

DDR_B_D34

DDR_B_D4

DDR_B_D26

DDR_B_D13

DDR_B_D10

DDR_B_D21

DDR_B_D11

DDR_B_D57

DDR_B_D44

DDR_B_D0

DDR_B_D7

DDR_B_D46

DDR_B_D3

DDR_B_D15

DDR_B_D27

DDR_B_D30

DDR_B_D35

DDR_B_D40

DDR_B_D49

DDR_B_D23

DDR_B_D25

DDR_B_D19

DDR_B_D37

DDR_B_D48

DDR_B_D36

DDR_B_D18

DDR_B_D8

DDR_B_D47

DDR_B_D9

DDR_B_D60

DDR_B_D50

DDR_B_D62

DDR_B_D52

DDR_B_D2

DDR_B_D51

DDR_B_D56

DDR_B_D39

DDR_B_D22

DDR_B_D28

DDR_B_D6

DDR_B_D45

DDR_B_D17

DDR_B_D58

DDR_B_D61

DDR_B_D31

DDR_B_D54

DDR_B_D1

DDR_B_D41

DDR_B_D5

DDR_B_D12

DDR_B_D20

DDR_B_D38

DDR_B_D32

DDR_B_D16

M_CLK_DDR2

DDR_CKE2_DIMMB

M_CLK_DDR3

M_CLK_DDR#3

DDR_CKE3_DIMMB

DDR_B_MA15

DDR_B_DQS#7

DDR_B_DQS#5

DDR_B_DQS#6

DDR_B_DQS7

DDR_B_DQS5

DDR_B_DQS6

DDR_B_MA13

DDR_B_MA14

M_CLK_DDR#2

DDR_CS2_DIMMB#

DDR_CS3_DIMMB#

M_ODT2

M_ODT3

DDR3_DRAMRST#_R

DRAMRST_CNTRL

H_DRAMRST#

DDR_B_MA11

DDR_B_MA5

DDR_B_DQS#4

DDR_B_DQS2

DDR_B_MA10

DDR_B_MA6

DDR_B_MA4

DDR_B_DQS#1

DDR_B_MA2

DDR_B_DQS#3

DDR_B_MA9

DDR_B_MA3

DDR_B_DQS1

DDR_B_MA1

DDR_B_DQS3

DDR_B_MA8

DDR_B_DQS0

DDR_B_MA12

DDR_B_MA0

DDR_B_DQS4

DDR_B_DQS#2

DDR_B_DQS#0

DDR_B_MA7

DDR_A_D[0..63]<11>

DDR_A_BS0<11>

DDR_A_BS1<11>

DDR_A_BS2<11>

DDR_A_WE#<11>

DDR_A_RAS#<11>

DDR_A_CAS#<11>

M_CLK_DDR0 <11>

M_CLK_DDR#0 <11>

DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11>

M_CLK_DDR#1 <11>

DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>

DDR_CS1_DIMMA# <11>

M_ODT0 <11>

M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12>

DDR_B_BS1<12>

DDR_B_BS2<12>

DDR_B_D[0..63]<12>

DDR_B_WE#<12>

DDR_B_RAS#<12>

DDR_B_CAS#<12>

DDR_CS3_DIMMB# <12>

DDR_B_DQS[0..7] <12>

DDR_B_DQS#[0..7] <12>

M_CLK_DDR2 <12>

M_CLK_DDR#2 <12>

DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12>

DDR_CS2_DIMMB# <12>

M_ODT3 <12>

M_ODT2 <12>

DDR_CKE3_DIMMB <12>

M_CLK_DDR#3 <12>

DDR_B_MA[0..15] <12>

DDR3_DRAMRST# <11,12>

H_DRAMRST#<6>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL <11>

+1.5V

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

7 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

DDR SYSTEM MEMORY B

JCPU1D

Sandy Bridge_rPGA_Rev1p0

CONN@

SB_BS[0]

AA9

SB_BS[1]

AA7

SB_BS[2]

R6

SB_CAS#

AA10

SB_RAS#

AB8

SB_WE#

AB9

SB_CLK[0] AE2

SB_CLK[1] AE1

SB_CLK#[0] AD2

SB_CLK#[1] AD1

SB_CKE[0] R9

SB_CKE[1] R10

SB_ODT[0] AE4

SB_ODT[1] AD4

SB_DQS[4] AN6

SB_DQS#[4] AN5

SB_DQS[5] AP8

SB_DQS#[5] AP9

SB_DQS[6] AK11

SB_DQS#[6] AK12

SB_DQS[7] AP14

SB_DQS#[7] AP15

SB_DQS[0] C7

SB_DQS#[0] D7

SB_DQS[1] G3

SB_DQS#[1] F3

SB_DQS[2] J6

SB_DQS#[2] K6

SB_DQS[3] M3

SB_DQS#[3] N3

SB_MA[0] AA8

SB_MA[1] T7

SB_MA[2] R7

SB_MA[3] T6

SB_MA[4] T2

SB_MA[5] T4

SB_MA[6] T3

SB_MA[7] R2

SB_MA[8] T5

SB_MA[9] R3

SB_MA[10] AB7

SB_MA[11] R1

SB_MA[12] T1

SB_MA[13] AB10

SB_MA[14] R5

SB_MA[15] R4

SB_DQ[0]

C9

SB_DQ[1]

A7

SB_DQ[2]

D10

SB_DQ[3]

C8

SB_DQ[4]

A9

SB_DQ[5]

A8

SB_DQ[6]

D9

SB_DQ[7]

D8

SB_DQ[8]

G4

SB_DQ[9]

F4

SB_DQ[10]

F1

SB_DQ[11]

G1

SB_DQ[12]

G5

SB_DQ[13]

F5

SB_DQ[14]

F2

SB_DQ[15]

G2

SB_DQ[16]

J7

SB_DQ[17]

J8

SB_DQ[18]

K10

SB_DQ[19]

K9

SB_DQ[20]

J9

SB_DQ[21]

J10

SB_DQ[22]

K8

SB_DQ[23]

K7

SB_DQ[24]

M5

SB_DQ[25]

N4

SB_DQ[26]

N2

SB_DQ[27]

N1

SB_DQ[28]

M4

SB_DQ[29]

N5

SB_DQ[30]

M2

SB_DQ[31]

M1

SB_DQ[32]

AM5

SB_DQ[33]

AM6

SB_DQ[34]

AR3

SB_DQ[35]

AP3

SB_DQ[36]

AN3

SB_DQ[37]

AN2

SB_DQ[38]

AN1

SB_DQ[39]

AP2

SB_DQ[40]

AP5

SB_DQ[41]

AN9

SB_DQ[42]

AT5

SB_DQ[43]

AT6

SB_DQ[44]

AP6

SB_DQ[45]

AN8

SB_DQ[46]

AR6

SB_DQ[47]

AR5

SB_DQ[48]

AR9

SB_DQ[49]

AJ11

SB_DQ[50]

AT8

SB_DQ[51]

AT9

SB_DQ[52]

AH11

SB_DQ[53]

AR8

SB_DQ[54]

AJ12

SB_DQ[55]

AH12

SB_DQ[56]

AT11

SB_DQ[57]

AN14

SB_DQ[58]

AR14

SB_DQ[59]

AT14

SB_DQ[60]

AT12

SB_DQ[61]

AN15

SB_DQ[62]

AR15

SB_DQ[63]

AT15

RSVD_TP[11] AB2

RSVD_TP[12] AA2

RSVD_TP[13] T9

RSVD_TP[14] AA1

RSVD_TP[15] AB1

RSVD_TP[16] T10

SB_CS#[0] AD3

SB_CS#[1] AE3

RSVD_TP[17] AD6

RSVD_TP[18] AE6

RSVD_TP[19] AD5

RSVD_TP[20] AE5

RC74 0_0402_5%

@

1 2

G

D

S

QC2

BSS138_SOT23

2

13

RC75

1K_0402_5%

12

RC77

4.99K_0402_1%

12

RC76 1K_0402_5%

1 2

CC37

.047U_0402_16V7K

1

2

RC72 0_0402_1%

@

1 2

DDR SYSTEM MEMORY A

JCPU1C

Sandy Bridge_rPGA_Rev1p0

CONN@

SA_BS[0]

AE10

SA_BS[1]

AF10

SA_BS[2]

V6

SA_CAS#

AE8

SA_RAS#

AD9

SA_WE#

AF9

SA_CLK[0] AB6

SA_CLK[1] AA5

SA_CLK#[0] AA6

SA_CLK#[1] AB5

SA_CKE[0] V9

SA_CKE[1] V10

SA_CS#[0] AK3

SA_CS#[1] AL3

SA_ODT[0] AH3

SA_ODT[1] AG3

SA_DQS[0] D4

SA_DQS#[0] C4

SA_DQS[1] F6

SA_DQS#[1] G6

SA_DQS[2] K3

SA_DQS#[2] J3

SA_DQS[3] N6

SA_DQS#[3] M6

SA_DQS[4] AL5

SA_DQS#[4] AL6

SA_DQS[5] AM9

SA_DQS#[5] AM8

SA_DQS[6] AR11

SA_DQS#[6] AR12

SA_DQS[7] AM14

SA_DQS#[7] AM15

SA_MA[0] AD10

SA_MA[1] W1

SA_MA[2] W2

SA_MA[3] W7

SA_MA[4] V3

SA_MA[5] V2

SA_MA[6] W3

SA_MA[7] W6

SA_MA[8] V1

SA_MA[9] W5

SA_MA[10] AD8

SA_MA[11] V4

SA_MA[12] W4

SA_MA[13] AF8

SA_MA[14] V5

SA_MA[15] V7

SA_DQ[0]

C5

SA_DQ[1]

D5

SA_DQ[2]

D3

SA_DQ[3]

D2

SA_DQ[4]

D6

SA_DQ[5]

C6

SA_DQ[6]

C2

SA_DQ[7]

C3

SA_DQ[8]

F10

SA_DQ[9]

F8

SA_DQ[10]

G10

SA_DQ[11]

G9

SA_DQ[12]

F9

SA_DQ[13]

F7

SA_DQ[14]

G8

SA_DQ[15]

G7

SA_DQ[16]

K4

SA_DQ[17]

K5

SA_DQ[18]

K1

SA_DQ[19]

J1

SA_DQ[20]

J5

SA_DQ[21]

J4

SA_DQ[22]

J2

SA_DQ[23]

K2

SA_DQ[24]

M8

SA_DQ[25]

N10

SA_DQ[26]

N8

SA_DQ[27]

N7

SA_DQ[28]

M10

SA_DQ[29]

M9

SA_DQ[30]

N9

SA_DQ[31]

M7

SA_DQ[32]

AG6

SA_DQ[33]

AG5

SA_DQ[34]

AK6

SA_DQ[35]

AK5

SA_DQ[36]

AH5

SA_DQ[37]

AH6

SA_DQ[38]

AJ5

SA_DQ[39]

AJ6

SA_DQ[40]

AJ8

SA_DQ[41]

AK8

SA_DQ[42]

AJ9

SA_DQ[43]

AK9

SA_DQ[44]

AH8

SA_DQ[45]

AH9

SA_DQ[46]

AL9

SA_DQ[47]

AL8

SA_DQ[48]

AP11

SA_DQ[49]

AN11

SA_DQ[50]

AL12

SA_DQ[51]

AM12

SA_DQ[52]

AM11

SA_DQ[53]

AL11

SA_DQ[54]

AP12

SA_DQ[55]

AN12

SA_DQ[56]

AJ14

SA_DQ[57]

AH14

SA_DQ[58]

AL15

SA_DQ[59]

AK15

SA_DQ[60]

AL14

SA_DQ[61]

AK14

SA_DQ[62]

AJ15

SA_DQ[63]

AH15

RSVD_TP[1] AB4

RSVD_TP[2] AA4

RSVD_TP[4] AB3

RSVD_TP[5] AA3

RSVD_TP[3] W9

RSVD_TP[6] W10

RSVD_TP[7] AG1

RSVD_TP[8] AH1

RSVD_TP[9] AG2

RSVD_TP[10] AH2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG4

CFG6

CFG5

CFG2

CFG7

VCC_VAL_SENSE

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

CFG10

CFG11

CFG13

CFG14

CFG15

CFG16

CFG17

CFG12

CFG1

CFG2

CFG0

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

+SA_DIMM_VREFDQ

+SB_DIMM_VREFDQ

VSS_VAL_SENSE

VSS_VAL_SENSE

VSS_AXG_VAL_SENSE

H_VCCP_SEL

CFG0<6>

CFG10<6>

CFG11<6>

CLK_RES_ITP <14>

CLK_RES_ITP# <14>

CFG12<6>

CFG13<6>

CFG14<6>

CFG15<6>

+SA_DIMM_VREFDQ

+SB_DIMM_VREFDQ

+VCC_CORE

+VCC_GFXCORE_AXG

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

8 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled

PCIE Port Bifurcation Straps

CFG[6:5]

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG7

PEG DEFER TRAINING

0: PEG Wait for BIOS for training

1: (Default) PEG Train immediately

following xxRESETB de assertion

CFG4

Display Port Presence Strap

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

1 : Disabled; No Physical Display Port

attached to Embedded Display Port

CFG Straps for Processor

01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

0:Lane Reversed

1:(Default) Normal Operation; Lane #

definition matches socket pin map definition

INTEL 12/28 recommand

to add RC120, RC121, RC122, RC123

Please place as close as JCPU1

*

*

*

*

T49PAD~D @

T50 PAD~D@

T7 PAD~D@

T43PAD~D @

T23 PAD~D@

RC81

1K_0402_1%

@

12

T26PAD~D @

T48 PAD~D@

T2 PAD~D@

T40PAD~D @

T20 PAD~D@

T6 PAD~D@

RC85

1K_0402_1%

@

12

T47 PAD~D@

T87PAD~D @

T89PAD~D @

T34PAD~D @

T25PAD~D @

T11 PAD~D@

RC90

50_0402_1%

@

1 2

T29 PAD~D@

RC79

50_0402_1%

@

1 2

T90PAD~D @

T32PAD~D @

T10 PAD~D@

T37PAD~D @

T88PAD~D @

T18 PAD~D@

T35PAD~D @T36 PAD~D@

T21 PAD~D@

T16 PAD~D@

T86PAD~D @

T13 PAD~D@

T12 PAD~D@

T4 PAD~D@

T45PAD~D @

RC86

1K_0402_1%

@

12

RC80

50_0402_1%

@

1 2

T8 PAD~D@

T42PAD~D @

T39PAD~D @

RESERVED

JCPU1E

Sandy Bridge_rPGA_Rev1p0

CONN@

CFG[0]

AK28

CFG[1]

AK29

CFG[2]

AL26

CFG[3]

AL27

CFG[4]

AK26

CFG[5]

AL29

CFG[6]

AL30

CFG[7]

AM31

CFG[8]

AM32

CFG[9]

AM30

CFG[10]

AM28

CFG[11]

AM26

CFG[12]

AN28

CFG[13]

AN31

CFG[14]

AN26

CFG[15]

AM27

CFG[16]

AK31

CFG[17]

AN29

RSVD34 AM33

RSVD35 AJ27

RSVD38 J16

RSVD42 AT34

RSVD39 H16

RSVD40 G16

RSVD41 AR35

RSVD43 AT33

RSVD45 AR34

RSVD56 AT2

RSVD57 AT1

RSVD58 AR1

RSVD46 B34

RSVD47 A33

RSVD48 A34

RSVD49 B35

RSVD50 C35

RSVD51 AJ32

RSVD52 AK32

RSVD30 AE7

RSVD31 AK2

RSVD28 L7

RSVD29 AG7

RSVD27

J15

RSVD16

C30 RSVD15

D23

RSVD17

A31

RSVD18

B30

RSVD20

D30 RSVD19

B29

RSVD22

A30 RSVD21

B31

RSVD23

C29

RSVD24

J20

RSVD37 T8

RSVD6

B4

RSVD7

D1

RSVD8

F25

RSVD9

F24

RSVD11

D24

RSVD12

G25

RSVD13

G24

RSVD14

E23

RSVD32 W8

RSVD33 AT26

RSVD25

B18

RSVD44 AP35

RSVD10

F23

RSVD5

AJ26

VAXG_VAL_SENSE

AJ31

VSSAXG_VAL_SENSE

AH31

VCC_VAL_SENSE

AJ33

VSS_VAL_SENSE

AH33

KEY B1

VCC_DIE_SENSE AH27

VCCIO_SEL

A19

RSVD54 AN35

RSVD55 AM35

T5 PAD~D@

RC87

1K_0402_1%

12

T33PAD~D @

T17 PAD~D@

RC78

1K_0402_1%

12

RC159

10K_0402_5%

12

T19PAD~D @

T3 PAD~D@

T38PAD~D @

T15 PAD~D@

T85PAD~D @

T28PAD~D @

T30PAD~D @

T27PAD~D @

T14 PAD~D@

RC91

50_0402_1%

@

1 2

RC84

1K_0402_1%

@

12

T46 PAD~D@

T22 PAD~D@

T41PAD~D @

RC89

1K_0402_1%

@

12

T9 PAD~D@

T24 PAD~D@

T31 PAD~D@

T44PAD~D @

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSSENSE_R

VCCSENSE_R

H_CPU_SVIDALRT#

H_CPU_SVIDDAT

H_CPU_SVIDCLK

VCCIO_SENSE <47>

VCCSENSE <50>

VSSSENSE <50>

VR_SVID_DAT <50>

VR_SVID_CLK <50>

VR_SVID_ALRT# <50>

+VCC_CORE

+VCC_CORE

+VCCP

+VCCP

+VCCP

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

9 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

8.5A

QC=94A

DC=53A

Place the PU

resistors close to CPU

RC95 close to CPU

RC99 0_0402_1%@

1 2

RC100

100_0402_1%

12

RC97

100_0402_1%

12

RC94 43_0402_1%

1 2

RC96 0_0402_1%@

1 2

RC93

75_0402_5%

12

RC92 0_0402_1%@

1 2

RC98 0_0402_1%@

1 2

RC111

10_0402_1%

12

RC108

10_0402_1%

12

POWER

CORE SUPPLY

PEG AND DDR

SENSE LINES SVID

JCPU1F

Sandy Bridge_rPGA_Rev1p0

CONN@

VCC_SENSE AJ35

VSS_SENSE AJ34

VIDALERT# AJ29

VIDSCLK AJ30

VIDSOUT AJ28

VSSIO_SENSE A10

VCC1

AG35

VCC2

AG34

VCC3

AG33

VCC4

AG32

VCC5

AG31

VCC6

AG30

VCC7

AG29

VCC8

AG28

VCC9

AG27

VCC10

AG26

VCC11

AF35

VCC12

AF34

VCC13

AF33

VCC14

AF32

VCC15

AF31

VCC16

AF30

VCC17

AF29

VCC18

AF28

VCC19

AF27

VCC20

AF26

VCC21

AD35

VCC22

AD34

VCC23

AD33

VCC24

AD32

VCC25

AD31

VCC26

AD30

VCC27

AD29

VCC28

AD28

VCC29

AD27

VCC30

AD26

VCC31

AC35

VCC32

AC34

VCC33

AC33

VCC34

AC32

VCC35

AC31

VCC36

AC30

VCC37

AC29

VCC38

AC28

VCC39

AC27

VCC40

AC26

VCC41

AA35

VCC42

AA34

VCC43

AA33

VCC44

AA32

VCC45

AA31

VCC46

AA30

VCC47

AA29

VCC48

AA28

VCC49

AA27

VCC50

AA26

VCC51

Y35

VCC52

Y34

VCC53

Y33

VCC54

Y32

VCC55

Y31

VCC56

Y30

VCC57

Y29

VCC58

Y28

VCC59

Y27

VCC60

Y26

VCC61

V35

VCC62

V34

VCC63

V33

VCC64

V32

VCC65

V31

VCC66

V30

VCC67

V29

VCC68

V28

VCC69

V27

VCC70

V26

VCC71

U35

VCC72

U34

VCC73

U33

VCC74

U32

VCC75

U31

VCC76

U30

VCC77

U29

VCC78

U28

VCC79

U27

VCC80

U26

VCC81

R35

VCC82

R34

VCC83

R33

VCC84

R32

VCC85

R31

VCC86

R30

VCC87

R29

VCC88

R28

VCC89

R27

VCC90

R26

VCC91

P35

VCC92

P34

VCC93

P33

VCC94

P32

VCC95

P31

VCC96

P30

VCC97

P29

VCC98

P28

VCC99

P27

VCC100

P26

VCCIO1 AH13

VCCIO12 J11

VCCIO18 G12

VCCIO19 F14

VCCIO20 F13

VCCIO21 F12

VCCIO22 F11

VCCIO23 E14

VCCIO24 E12

VCCIO2 AH10

VCCIO3 AG10

VCCIO4 AC10

VCCIO5 Y10

VCCIO6 U10

VCCIO7 P10

VCCIO8 L10

VCCIO9 J14

VCCIO10 J13

VCCIO11 J12

VCCIO13 H14

VCCIO14 H12

VCCIO15 H11

VCCIO16 G14

VCCIO17 G13

VCCIO25 E11

VCCIO32 C12

VCCIO33 C11

VCCIO34 B14

VCCIO35 B12

VCCIO36 A14

VCCIO37 A13

VCCIO38 A12

VCCIO39 A11

VCCIO26 D14

VCCIO27 D13

VCCIO28 D12

VCCIO29 D11

VCCIO30 C14

VCCIO31 C13

VCCIO_SENSE B10

VCCIO40 J23

RC95

130_0402_1%~D

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RUN_ON_CPU1.5VS3#

+1.8VS_VCCPLL

RUN_ON_CPU1.5VS3

RUN_ON_CPU1.5VS3

+V_SM_VREF_CNT +V_SM_VREF

VCC_AXG_SENSE

VSS_AXG_SENSE

SUSP#<24,27,28,46,47,48>

VCCSA_SENSE <49>

VCCSA_VID1 <49>

VCC_AXG_SENSE <50>

VSS_AXG_SENSE <50>

RUN_ON_CPU1.5VS3# <6,27>

CPU1.5V_S3_GATE<24>

VCCSA_VID0 <49>

+VCCSA

+1.5V +1.5V_CPU_VDDQ

B+_BIAS+3VALW

+1.5V_CPU_VDDQ

+1.5V

+1.8VS

+VCC_GFXCORE_AXG

+1.5V

+1.5V_CPU_VDDQ +1.5V

+VCC_GFXCORE_AXG

+1.5V_CPU_VDDQ

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

10 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

+1.5V_CPU_VDDQ Source

5A

+V_SM_VREF should

have 10 mil trace width

33A

J8 OPEN

6A

1.2A

add CC181 , CC182, 4 caps are all pop.

follow checklist 1.0 5/24

RC113

10_0402_1%

1 2

RC110

0_0402_5%

@

12

CC51

10U_0805_4VAM~D

1

2

QC4

NTR4503NT1G_SOT23-3~D

@

1

2

3

RC102

100K_0402_5%

12

RC112

1K_0402_5%

@

12

CC56

1U_0402_6.3V6K

1

2

CC55

1U_0402_6.3V6K

1

2

CC40

0.1U_0402_10V7K~D

@

1

2

RC114

10_0402_1%

1 2

CC52

10U_0603_6.3V6M

@

1

2

CC54

10U_0805_4VAM~D

1

2

+

CC48

330U_D2_2VM_R6M~D

1

2

+

CC47

330U_D2_2VM_R6M~D

1

2

CC62

10U_0805_4VAM~D

@

1

2

RC106 0_0402_5%@

1 2

CC38

10U_0805_10V6K

1

2

VSS

JCPU1H

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS1

AT35

VSS2

AT32

VSS3

AT29

VSS4

AT27

VSS5

AT25

VSS6

AT22

VSS7

AT19

VSS8

AT16

VSS9

AT13

VSS10

AT10

VSS11

AT7

VSS12

AT4

VSS13

AT3

VSS14

AR25

VSS15

AR22

VSS16

AR19

VSS17

AR16

VSS18

AR13

VSS19

AR10

VSS20

AR7

VSS21

AR4

VSS22

AR2

VSS23

AP34

VSS24

AP31

VSS25

AP28

VSS26

AP25

VSS27

AP22

VSS28

AP19

VSS29

AP16

VSS30

AP13

VSS31

AP10

VSS32

AP7

VSS33

AP4

VSS34

AP1

VSS35

AN30

VSS36

AN27

VSS37

AN25

VSS38

AN22

VSS39

AN19

VSS40

AN16

VSS41

AN13

VSS42

AN10

VSS43

AN7

VSS44

AN4

VSS45

AM29

VSS46

AM25

VSS47

AM22

VSS48

AM19

VSS49

AM16

VSS50

AM13

VSS51

AM10

VSS52

AM7

VSS53

AM4

VSS54

AM3

VSS55

AM2

VSS56

AM1

VSS57

AL34

VSS58

AL31

VSS59

AL28

VSS60

AL25

VSS61

AL22

VSS62

AL19

VSS63

AL16

VSS64

AL13

VSS65

AL10

VSS66

AL7

VSS67

AL4

VSS68

AL2

VSS69

AK33

VSS70

AK30

VSS71

AK27

VSS72

AK25

VSS73

AK22

VSS74

AK19

VSS75

AK16

VSS76

AK13

VSS77

AK10

VSS78

AK7

VSS79

AK4

VSS80

AJ25

VSS81 AJ22

VSS82 AJ19

VSS83 AJ16

VSS84 AJ13

VSS85 AJ10

VSS86 AJ7

VSS87 AJ4

VSS88 AJ3

VSS89 AJ2

VSS90 AJ1

VSS91 AH35

VSS92 AH34

VSS93 AH32

VSS94 AH30

VSS95 AH29

VSS96 AH28

VSS97 AH26

VSS98 AH25

VSS99 AH22

VSS100 AH19

VSS101 AH16

VSS102 AH7

VSS103 AH4

VSS104 AG9

VSS105 AG8

VSS106 AG4

VSS107 AF6

VSS108 AF5

VSS109 AF3

VSS110 AF2

VSS111 AE35

VSS112 AE34

VSS113 AE33

VSS114 AE32

VSS115 AE31

VSS116 AE30

VSS117 AE29

VSS118 AE28

VSS119 AE27

VSS120 AE26

VSS121 AE9

VSS122 AD7

VSS123 AC9

VSS124 AC8

VSS125 AC6

VSS126 AC5

VSS127 AC3

VSS128 AC2

VSS129 AB35

VSS130 AB34

VSS131 AB33

VSS132 AB32

VSS133 AB31

VSS134 AB30

VSS135 AB29

VSS136 AB28

VSS137 AB27

VSS138 AB26

VSS139 Y9

VSS140 Y8

VSS141 Y6

VSS142 Y5

VSS143 Y3

VSS144 Y2

VSS145 W35

VSS146 W34

VSS147 W33

VSS148 W32

VSS149 W31

VSS150 W30

VSS151 W29

VSS152 W28

VSS153 W27

VSS154 W26

VSS155 U9

VSS156 U8

VSS157 U6

VSS158 U5

VSS159 U3

VSS160 U2

CC41

10U_0805_4VAM~D

1

2

CC50

10U_0805_4VAM~D

1

2

RC107

0_0402_5%

1 2

RC157 100_0402_1%

@

1 2

RC104

0_0402_5%

@

1 2

CC61

10U_0805_4VAM~D

@

1

2

POWER

GRAPHICS

DDR3 -1.5V RAILS SENSE

LINES

1.8V RAIL

SA RAIL

VREFMISC

JCPU1G

Sandy Bridge_rPGA_Rev1p0

CONN@

SM_VREF AL1

VSSAXG_SENSE AK34

VAXG_SENSE AK35

VAXG1

AT24

VAXG2

AT23

VAXG3

AT21

VAXG4

AT20

VAXG5

AT18

VAXG6

AT17

VAXG7

AR24

VAXG8

AR23

VAXG9

AR21

VAXG10

AR20

VAXG11

AR18

VAXG12

AR17

VAXG13

AP24

VAXG14

AP23

VAXG15

AP21

VAXG16

AP20

VAXG17

AP18

VAXG18

AP17

VAXG19

AN24

VAXG20

AN23

VAXG21

AN21

VAXG22

AN20

VAXG23

AN18

VAXG24

AN17

VAXG25

AM24

VAXG26

AM23

VAXG27

AM21

VAXG28

AM20

VAXG29

AM18

VAXG30

AM17

VAXG31

AL24

VAXG32

AL23

VAXG33

AL21

VAXG34

AL20

VAXG35

AL18

VAXG36

AL17

VAXG37

AK24

VAXG38

AK23

VAXG39

AK21

VAXG40

AK20

VAXG41

AK18

VAXG42

AK17

VAXG43

AJ24

VAXG44

AJ23

VAXG45

AJ21

VAXG46

AJ20

VAXG47

AJ18

VAXG48

AJ17

VAXG49

AH24

VAXG50

AH23

VAXG51

AH21

VAXG52

AH20

VAXG53

AH18

VAXG54

AH17

VDDQ11 U4

VDDQ12 U1

VDDQ13 P7

VDDQ14 P4

VDDQ15 P1

VDDQ1 AF7

VDDQ2 AF4

VDDQ3 AF1

VDDQ4 AC7

VDDQ5 AC4

VDDQ6 AC1

VDDQ7 Y7

VDDQ8 Y4

VDDQ9 Y1

VDDQ10 U7

VCCPLL1

B6

VCCPLL2

A6

VCCSA1 M27

VCCSA2 M26

VCCSA3 L26

VCCSA4 J26

VCCSA5 J25

VCCSA6 J24

VCCSA7 H26

VCCSA8 H25

VCCSA_SENSE H23

VCCSA_VID1 C24

VCCPLL3

A2

FC_C22 C22

RC126

1K_0402_5%

12

CC59 0.1U_0402_10V7K~D

12

+

CC57

330U_D2_2.5VM_R6M~D

1

2

CC43

10U_0805_4VAM~D

1

2

QC3

AO4728L_SO8~D

4

7

8

6

5

1

2

3

QC5B

2N7002DW-7-F_SOT363-6

3

5

4

CC44

10U_0805_4VAM~D

1

2

CC49

10U_0805_4VAM~D

1

2

CC45

10U_0805_4VAM~D

1

2

RC129 1K_0402_5%

1 2

CC60 0.1U_0402_10V7K~D

12

RC105

330K_0402_1%

12

RC116

1K_0402_5%

@

12

RC101

100K_0402_5%

12

CC58 0.1U_0402_10V7K~D

12

QC5A

2N7002DW-7-F_SOT363-6

61

2

RC109 0_0805_1%@

1 2

JP10

PAD-OPEN 4x4m

@

1 2

RC103

20K_0402_5%

12

CC42

10U_0805_4VAM~D

1

2

CC39

0.1U_0603_50V_X7R

1

2

CC53 0.1U_0402_10V7K~D

12

CC46

10U_0805_4VAM~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V_DDR_REFA

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D10

DDR_A_D11

DDR_A_D18

DDR_A_D19

DDR_A_D26

DDR_A_D27

DDR_A_D32

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_MA1

DDR_A_MA3

DDR_A_MA5

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA12

DDR_A_MA13

DDR_A_DQS1

DDR_A_DQS2

DDR_A_DQS4

DDR_A_DQS6

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS#4

DDR_A_DQS#6

DDR_A_BS0

DDR_A_BS2

DDR_CS1_DIMMA#

M_CLK_DDR0

M_CLK_DDR#0

DDR_CKE0_DIMMA

DDR_A_CAS#

DDR_A_WE#

DDR_A_D17

DDR_A_D9

DDR_A_D16

DDR_A_D25

DDR_A_D24

DDR_A_D33

DDR_A_D48

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D21

DDR_A_D28

DDR_A_D29

DDR_A_D36

DDR_A_D37

DDR_A_D45

DDR_A_D46

DDR_A_D52

DDR_A_D53

DDR_A_D55

DDR_A_D60

DDR_A_D61

DDR_A_D62

DDR_A_MA2

DDR_A_MA0

DDR_A_MA4

DDR_A_MA6

DDR_A_MA7

DDR_A_MA11

DDR_A_MA14

DDR_A_DQS0

DDR_A_DQS3

DDR_A_DQS5

DDR_A_DQS7

DDR_A_DQS#0

DDR_A_DQS#3

DDR_A_DQS#5

DDR_A_DQS#7

DDR_A_BS1

DDR_CS0_DIMMA#

M_CLK_DDR1

M_CLK_DDR#1

DDR_CKE1_DIMMA

DDR_A_RAS#

PCH_SMBDATA

PCH_SMBCLK

M_ODT0

M_ODT1

DDR3_DRAMRST#

DDR_A_D63

DDR_A_MA15

+VREF_CA

DDR_A_D23

DDR_A_D31

DDR_A_D13

DDR_A_D20

DDR_A_D30

DDR_A_D14

DDR_A_D15

DDR_A_D12

DDR_A_D22

DDR_A_D39

DDR_A_D54

DDR_A_D38

DDR_A_D47

DDR_A_D44

DRAMRST_CNTRL

DRAMRST_CNTRL

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

DDR_CS1_DIMMA#<7>

DDR_A_CAS#<7>

DDR_A_WE#<7>

DDR_A_BS0<7>

M_CLK_DDR#0<7>

M_CLK_DDR0<7>

DDR_A_BS2<7>

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>

M_CLK_DDR#1 <7>

DDR_A_BS1 <7>

DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_ODT1 <7>

PCH_SMBDATA <6,12,14,28,29,32>

PCH_SMBCLK <6,12,14,28,29,32>

DDR3_DRAMRST# <7,12>

DRAMRST_CNTRL<7>

+0.75VS

+1.5V

+1.5V

+1.5V

+V_DDR_REFA

+1.5V

+3VS

+0.75VS

+V_DDR_REFA

+1.5V

+0.75VS

+1.5V

+SB_DIMM_VREFDQ

+SA_DIMM_VREFDQ

+V_DDR_REFB

+V_DDR_REFA

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

11 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

DDRIII DIMMA

Layout Note:

Place near JDIMM1

Layout Note:

Place near JDIMM1.203,204

All VREF traces should

have 10 mil trace width

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

M3

CD22

2.2U_0603_6.3V6K

1

2

G

D

S

QD2

BSS138_NL_SOT23-3

2

13

CD16

0.1U_0402_16V7K

1

2

CD10

10U_0603_6.3V6M

1

2

CD12

10U_0603_6.3V6M

1

2

RD3

1K_0402_1%

12

RD1

1K_0402_1%

12

CD4

1U_0402_6.3V6K

1

2

G

D

S

QD1

BSS138_NL_SOT23-3

2

13

CD2

0.1U_0402_16V7K

1

2

CD5

1U_0402_6.3V6K

1

2

RD5

1K_0402_1%

12

CD1

2.2U_0603_6.3V6K

1

2

RD6 10K_0402_5%

1 2

CD19

1U_0402_6.3V6K

1

2

CD18

1U_0402_6.3V6K

1

2

CD6

1U_0402_6.3V6K

1

2

CD7

10U_0603_6.3V6M

1

2

CD21

0.1U_0402_16V7K

1

2

JDIMM1

BELLW_80001-5021

CONN@

VREF_DQ

1VSS1 2

VSS2

3DQ4 4

DQ0

5DQ5 6

DQ1

7VSS3 8

VSS4

9DQS#0 10

DM0

11 DQS0 12

VSS5

13 VSS6 14

DQ2

15 DQ6 16

DQ3

17 DQ7 18

VSS7

19 VSS8 20

DQ8

21 DQ12 22

DQ9

23 DQ13 24

VSS9

25 VSS10 26

DQS#1

27 DM1 28

DQS1

29 RESET# 30

VSS11

31 VSS12 32

DQ10

33 DQ14 34

DQ11

35 DQ15 36

VSS13

37 VSS14 38

DQ16

39 DQ20 40

DQ17

41 DQ21 42

VSS15

43 VSS16 44

DQS#2

45 DM2 46

DQS2

47 VSS17 48

VSS18

49 DQ22 50

DQ18

51 DQ23 52

DQ19

53 VSS19 54

VSS20

55 DQ28 56

DQ24

57 DQ29 58

DQ25

59 VSS21 60

VSS22

61 DQS#3 62

DM3

63 DQS3 64

VSS23

65 VSS24 66

DQ26

67 DQ30 68

DQ27

69 DQ31 70

VSS25

71 VSS26 72

A12/BC#

83 A11 84

A9

85 A7 86

VDD5

87 VDD6 88

A8

89 A6 90

CKE0

73 CKE1 74

VDD1

75 VDD2 76

NC1

77 A15 78

BA2

79 A14 80

VDD3

81 VDD4 82

A5

91 A4 92

VDD7

93 VDD8 94

A3

95 A2 96

A1

97 A0 98

VDD9

99 VDD10 100

CK0

101 CK1 102

CK0#

103 CK1# 104

VDD11

105 VDD12 106

A10/AP

107 BA1 108

BA0

109 RAS# 110

VDD13

111 VDD14 112

WE#

113 S0# 114

CAS#

115 ODT0 116

VDD15

117 VDD16 118

A13

119 ODT1 120

S1#

121 NC2 122

VDD17

123 VDD18 124

NCTEST

125 VREF_CA 126

VSS27

127 VSS28 128

DQ32

129 DQ36 130

DQ33

131 DQ37 132

VSS29

133 VSS30 134

DQS#4

135 DM4 136

DQS4

137 VSS31 138

VSS32

139 DQ38 140

DQ34

141 DQ39 142

DQ35

143 VSS33 144

VSS34

145 DQ44 146

DQ40

147 DQ45 148

DQ41

149 VSS35 150

VSS36

151 DQS#5 152

DM5

153 DQS5 154

VSS37

155 VSS38 156

DQ42

157 DQ46 158

DQ43

159 DQ47 160

VSS39

161 VSS40 162

DQ48

163 DQ52 164

DQ49

165 DQ53 166

VSS41

167 VSS42 168

DQS#6

169 DM6 170

DQS6

171 VSS43 172

VSS44

173 DQ54 174

DQ50

175 DQ55 176

DQ51

177 VSS45 178

VSS46

179 DQ60 180

DQ56

181 DQ61 182

DQ57

183 VSS47 184

VSS48

185 DQS#7 186

DM7

187 DQS7 188

VSS49

189 VSS50 190

DQ58

191 DQ62 192

DQ59

193 DQ63 194

VSS51

195 VSS52 196

SA0

197 EVENT# 198

VDDSPD

199 SDA 200

SA1

201 SCL 202

VTT1

203 VTT2 204

G1

205 G2 206

CD13

10U_0603_6.3V6M

@

1

2

CD8

10U_0603_6.3V6M

1

2

CD9

10U_0603_6.3V6M

1

2

RD7 10K_0402_5%

1 2

CD20

1U_0402_6.3V6K

1

2

RD4

1K_0402_1%

12

CD15

2.2U_0603_6.3V6K

1

2

CD3

1U_0402_6.3V6K

1

2

RD8 0_0402_5%@1 2

+

CD14

330U_SX_2VY~D

1

2

RD9 0_0402_5%@1 2

CD17

1U_0402_6.3V6K

1

2

CD11

10U_0603_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_B_D57

DDR_CKE2_DIMMB

DDR_B_D58

DDR_B_D59

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D8

+V_DDR_REFB

DDR_B_D9

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D10

DDR_B_D11

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18

DDR_B_D19

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_MA15

DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

PCH_SMBDATA

PCH_SMBCLK

DDR_B_D62

DDR_B_D63

+VREF_CB

DDR_B_MA7

DDR_B_D52

M_ODT2

DDR_B_MA14

DDR_B_D37

DDR_B_D36

DDR_B_MA6

DDR_B_D44

DDR_B_D54

DDR_B_D53

DDR_B_D46

DDR_CKE3_DIMMB

DDR_B_MA4

DDR_B_D45

DDR_B_D38

DDR_B_BS1

DDR_B_D55

DDR_B_D47

M_ODT3

M_CLK_DDR3

DDR_B_RAS#

M_CLK_DDR#3

DDR_B_MA2

DDR_B_DQS#5

DDR_B_MA11

DDR_B_D60

DDR_B_D39

DDR_B_MA0

DDR_B_DQS5

DDR_CS2_DIMMB#

DDR_B_D4

DDR_B_D5

DDR_B_DQS#0

DDR_B_DQS0

DDR_B_D22

DDR_B_D20

DDR3_DRAMRST#

DDR_B_D23

DDR_B_D21

DDR_B_DQS#3

DDR_B_D14

DDR_B_DQS3

DDR_B_D7

DDR_B_D6

DDR_B_D15

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D12

DDR_B_D13

DDR_B_BS2

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA5

DDR_B_MA3

DDR_B_MA1

M_CLK_DDR2

M_CLK_DDR#2

DDR_B_MA10

DDR_B_BS0

DDR_B_WE#

DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32

DDR_B_D33

DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D31DDR_B_D27

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

DDR_CS3_DIMMB#<7>

DDR_B_CAS#<7>

DDR_B_WE#<7>

DDR_B_BS0<7>

M_CLK_DDR#2<7>

M_CLK_DDR2<7>

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

PCH_SMBDATA <6,11,14,28,29,32>

PCH_SMBCLK <6,11,14,28,29,32>

M_CLK_DDR#3 <7>

DDR_B_BS1 <7>

DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_ODT3 <7>

M_CLK_DDR3 <7>

DDR_CKE3_DIMMB <7>

DDR3_DRAMRST# <7,11>

+1.5V

+1.5V

+0.75VS

+1.5V

+V_DDR_REFB

+3VS

+3VS

+1.5V

+V_DDR_REFB

+0.75VS

+1.5V

+1.5V

+0.75VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

12 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

DDRIII DIMMB

Layout Note:

Place near JDIMMB.203,204

Layout Note:

Place near JDIMMB

All VREF traces should

have 10 mil trace width

Note:

Check voltage tolerance of

VREF_DQ at the DIMM socket

CD27

2.2U_0603_6.3V6K

1

2

RD17

1K_0402_1%

12

CD29

1U_0402_6.3V6K

1

2

RD20

10K_0402_5%

12

CD32

10U_0603_6.3V6M

1

2

CD31

1U_0402_6.3V6K

1

2

CD45

1U_0402_6.3V6K

1

2

CD30

1U_0402_6.3V6K

1

2

CD37

10U_0603_6.3V6M

1

2

+

CD39

330U_SX_2VY~D

@

1

2

RD16

1K_0402_1%

12

CD44

1U_0402_6.3V6K

1

2

CD26

0.1U_0402_16V7K

1

2

CD28

1U_0402_6.3V6K

1

2

RD19

10K_0402_5%

12

CD41

0.1U_0402_16V7K

1

2

RD15

1K_0402_1%

12

CD40

2.2U_0603_6.3V6K

1

2

CD43

1U_0402_6.3V6K

1

2

RD18

1K_0402_1%

12

CD36

10U_0603_6.3V6M

1

2

CD34

10U_0603_6.3V6M

1

2

CD42

1U_0402_6.3V6K

1

2

CD47

2.2U_0603_6.3V6K

1

2

JDIMM2

BELLW_80001-1021

CONN@

VREF_DQ

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DM0

11

VSS

13

DQ2

15

DQ3

17

VSS

19

DQ8

21

DQ9

23

VSS

25

DQS1#

27

DQS1

29

VSS

31

DQ10

33

DQ11

35

VSS

37

DQ16

39

VSS 2

DQ4 4

DQ5 6

VSS 8

DQS0# 10

DQS0 12

VSS 14

DQ6 16

DQ7 18

VSS 20

DQ12 22

DQ13 24

VSS 26

DM1 28

RESET# 30

VSS 32

DQ14 34

DQ15 36

VSS 38

DQ20 40

DQ17

41

VSS

43

DQS2#

45

DQS2

47

VSS

49

DQ18

51

DQ19

53

VSS

55

DQ24

57

DQ25

59

VSS

61

DM3

63

VSS

65

DQ26

67

DQ27

69

VSS

71

CKE0

73

VDD

75

NC

77

BA2

79

VDD

81

A12/BC#

83

A9

85

VDD

87

A8

89

A5

91

VDD

93

A3

95

A1

97

VDD

99

CK0

101

CK0#

103

VDD

105

A10/AP

107

BA0

109

VDD

111

WE#

113

CAS#

115

VDD

117

A13

119

S1#

121

VDD

123

TEST

125

VSS

127

DQ32

129

DQ33

131

VSS

133

DQS4#

135

DQS4

137

VSS

139

DQ34

141

DQ35

143

VSS

145

DQ40

147

DQ41

149

VSS

151

DM5

153

VSS

155

DQ42

157

DQ43

159

VSS

161

DQ48

163

DQ49

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SA0

197

VDDSPD

199

DQ21 42

VSS 44

DM2 46

VSS 48

DQ22 50

DQ23 52

VSS 54

DQ28 56

DQ29 58

VSS 60

DQS3# 62

DQS3 64

VSS 66

DQ30 68

DQ31 70

VSS 72

CKE1 74

VDD 76

A15 78

A14 80

VDD 82

A11 84

A7 86

VDD 88

A6 90

A4 92

VDD 94

A2 96

A0 98

VDD 100

CK1 102

CK1# 104

VDD 106

BA1 108

RAS# 110

VDD 112

S0# 114

ODT0 116

VDD 118

ODT1 120

NC 122

VDD 124

VREF_CA 126

VSS 128

DQ36 130

DQ37 132

VSS 134

DM4 136

VSS 138

DQ38 140

DQ39 142

VSS 144

DQ44 146

DQ45 148

VSS 150

DQS5# 152

DQS5 154

VSS 156

DQ46 158

DQ47 160

VSS 162

DQ52 164

DQ53 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

EVENT# 198

SDA 200

SA1

201

VTT

203

GND1

205

SCL 202

VTT 204

GND2 206

BOSS1

207 BOSS2 208

CD46

0.1U_0402_16V7K

1

2

CD33

10U_0603_6.3V6M

1

2

CD38

10U_0603_6.3V6M

@

1

2

CD35

10U_0603_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCH_RTCX1

PCH_RTCX2

PCH_RTCX1

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

SM_INTRUDER#

HDA_SPKR

PCH_JTAG_TCK

PCH_SATALED#

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

HDA_SYNC

HDA_RST#

HDA_SDIN0

HDA_SDOUT

HDD_DET#_R

PCH_RTCX2

HDA_BIT_CLK

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

PCH_JTAG_TCK

PCH_SPI_WP#

PCH_SPI_HOLD#

SATA_PTX_DRX_P0

SATA_PTX_DRX_N0

LPC_AD2

LPC_FRAME#

LPC_AD0

LPC_AD3

LPC_AD1

SERIRQ

SATA_PTX_DRX_N2

SATA_PTX_DRX_P2

BBS_BIT0_R

SATA_COMP

RBIAS_SATA3

SATA3_COMP

HDA_BIT_CLK

HDA_RST#

HDA_SDOUT

HDA_SDOUT

PCH_SPI_CLK

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CS0#

HDA_SYNC

SERIRQ

HDA_SPKR

PCH_INTVRMEN

HDD_DET#

HDA_SDOUT

HDA_SYNC

PCH_SATALED#PCH_INTVRMEN

HDA_BIT_CLK

HDA_SDOUT

HDA_SYNC_R SATA_PTX_DRX_P1

SATA_PTX_DRX_N1

PCH_SPI_CS0#_R

PCH_SPI_SO_LPCH_SPI_SO

PCH_SPI_CS0#

PCH_SPI_SI_L PCH_SPI_SI

PCH_SPI_CLKPCH_SPI_WP#

PCH_SPI_HOLD#

PCH_SPI_CLK_L

PCH_SPI_SO

PCH_SPI_CLK

PCH_SPI_SI_R

PCH_SPI_CS1#_RPCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_WP#

PCH_SPI_HOLD#PCH_SPI_SO_R

PCH_SPI_CLK_R

PCH_SPI_CS1#

HDD_DET#

PCH_RTCX1

HDA_SPKR<30>

HDA_SDIN0<30>

SERIRQ <24>

SATA_PRX_DTX_P0 <29>

SATA_PTX_DRX_N0_C <29>

SATA_PTX_DRX_P0_C <29>

SATA_PRX_DTX_N0 <29>

LPC_AD0 <24>

LPC_AD1 <24>

LPC_AD2 <24>

LPC_AD3 <24>

LPC_FRAME# <24>

SATA_PRX_DTX_P2 <29>

SATA_PTX_DRX_N2_C <29>

SATA_PTX_DRX_P2_C <29>

SATA_PRX_DTX_N2 <29>

HDA_SDOUT_AUDIO<30>

HDA_RST_AUDIO#<30>

HDA_BITCLK_AUDIO<30>

PCH_SATALED# <32>

ME_EN<24>

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

HDA_SYNC_AUDIO<30>

SATA_PRX_DTX_N1 <32>

SATA_PTX_DRX_P1_C <32>

SATA_PTX_DRX_N1_C <32>

SATA_PRX_DTX_P1 <32>

HDD_DET# <29>

PCH_RTCX1_R<31>

+RTCVCC

+RTCVCC

+3V_PCH +3V_PCH+3V_PCH

+1.05VS_VCC_SATA

+1.05VS_SATA3

+3V_PCH

+5VS

+3VS

+RTCVCC

+3VS

+3V_PCH

+3V_PCH

+CHGRTC +3VLP

+3VS

+CHGRTC

+RTCBATT

+RTCVCC

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

13 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

ME CMOS

CMOS

CLP1 & CLP2 place near DIMM

HDD

ODD

keep away hot spot

SPI ROM FOR ME

( 4MByte )

LOW=Default

HIGH=No Reboot

*

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash

Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

H Integrated VRM enable

L Integrated VRM disable

INTVRMEN

*

HDA_SYNC

This signal has a weak internal pull-down

On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low

Needs to be pulled High for Huron River platfrom

*

Low = Disabled

High = Enabled

W=20mils

W=20mils

W=20mils

RTC Battery

Reserve for RF please close to UH1

SA00005AG1L

SA00005AG1L

mSATA

SPI ROM FOR WIN8( 2MByte )

NEC flash issue.

close to YH1

EON EN25Q32B-104HIP_SO8

EON EN25QH16-104HIP_SO8

RH24

100_0402_1%

12

RH40 3.3K_0402_5%

1 2

RH7 33_0402_5%

1 2

RH38 3.3K_0402_5%

1 2

CH3

18P_0402_50V8J

1

2

CH98

0.1U_0402_16V7K

1

2

RH37 33_0402_5%

12

RH17 1K_0402_5%@

12

RH39 33_0402_5%

12

RH22 49.9_0402_1%

1 2

CLRP1

SHORT PADS

12

RH5 33_0402_5%

1 2

DH1

BAT54CW_SOT323-3

2

3

1

RH28 750_0402_1%~D

1 2

RH10 10K_0402_5%

12

RH265 33_0402_5%

12

CH6

1U_0603_10V6K

1

2

RH13

330K_0402_5%

12

CH4

18P_0402_50V8J

1

2

UH6

EN25Q32B-104HIP_SO8

CS#

1

SO/SIO1

2

WP#

3

GND

4

VCC 8

HOLD# 7

SCLK 6

SI/SIO0 5

CH10 0.01U_0402_16V7K

1 2

RH18

200_0402_5%

@

12

UH1

BD82HM77 QPRG C1 BGA 989P PCH

@

RH8 1M_0402_5%

1 2

RH30 0_0402_5%

GCLK@

1 2

CH7 0.01U_0402_16V7K

1 2

RH14 10K_0402_5%

12

RH33

3.3K_0402_5%

@

1 2

CH11

0.1U_0402_16V7K

1

2

RH23 1K_0402_5%@

12

G

D

S

QH1 BSS138_SOT23

2

13

RH27 33_0402_5%

12

CH12

1U_0603_10V6K

1

2

CH17 0.01U_0402_16V7K

1 2

CH99

10P_0402_50V8J

@

1

2

RH35 51_0402_5%

1 2

RH1 10M_0402_5%

1 2

JP12

JUMP_43X39

11

2

2

RH16

330K_0402_5%

@

12

CH1 10P_0402_50V8J

@

12

RH26

100_0402_1%

12

RH266 33_0402_5%

12

CH5

1U_0603_10V6K

1

2

RH264 0_0402_5%

1 2

RH19

200_0402_5%

@

12

RH268 0_0402_5%

1 2

YH1

32.768KHZ_12.5PF_9H03200019

1 2

RH263

3.3K_0402_5%

@

1 2

RH11 1K_0402_1%

1 2

RH21 37.4_0402_1%

1 2

RH6 33_0402_5%

1 2

CH9 0.01U_0402_16V7K

1 2

RH267 33_0402_5%

12

RH34

1K_0402_5%

1 2

RH15 33_0402_5%

1 2

RH4 20K_0402_5%

1 2

CH8 0.01U_0402_16V7K

1 2

RH25

100_0402_1%

12

CLRP2

SHORT PADS

12

CH18 0.01U_0402_16V7K

1 2

RH262

3.3K_0402_5%

@

1 2

RH29

10K_0402_5%

12

UH2

EN25QH16-104HIP_SO8

CS#

1

SO

2

WP#

3

GND

4

VCC 8

HOLD# 7

SCLK 6

SI 5

RH36 0_0402_5%

1 2

RH3 20K_0402_5%

1 2

CH2 10P_0402_50V8J

@

12

RH32 1K_0402_5%

12

RH2

1M_0402_5%

1 2

RH12 10K_0402_5%

12

RH9 0_0402_5%

@

1 2

RTCIHDA

SATA

LPC

SPI JTAG

SATA 6G

UH1A

BD82HM77 QPRG C1 BGA 989P PCH

RTCX1

A20

RTCX2

C20

INTVRMEN

C17

INTRUDER#

K22

HDA_BCLK

N34

HDA_SYNC

L34

HDA_RST#

K34

HDA_SDIN0

E34

HDA_SDIN1

G34

HDA_SDIN2

C34

HDA_SDO

A36

SATALED# P3

FWH0 / LAD0 C38

FWH1 / LAD1 A38

FWH2 / LAD2 B37

FWH3 / LAD3 C37

LDRQ1# / GPIO23 K36

FWH4 / LFRAME# D36

LDRQ0# E36

RTCRST#

D20

HDA_SDIN3

A34

HDA_DOCK_EN# / GPIO33

C36

HDA_DOCK_RST# / GPIO13

N32

SRTCRST#

G22

SATA0RXN AM3

SATA0RXP AM1

SATA0TXN AP7

SATA0TXP AP5

SATA1RXN AM10

SATA1RXP AM8

SATA1TXN AP11

SATA1TXP AP10

SATA2RXN AD7

SATA2RXP AD5

SATA2TXN AH5

SATA2TXP AH4

SATA3RXN AB8

SATA3RXP AB10

SATA3TXN AF3

SATA3TXP AF1

SATA4RXN Y7

SATA4RXP Y5

SATA4TXN AD3

SATA4TXP AD1

SATA5RXN Y3

SATA5RXP Y1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI Y10

SPI_CLK

T3

SPI_CS0#

Y14

SPI_CS1#

T1

SPI_MOSI

V4

SPI_MISO

U3

SATA0GP / GPIO21 V14

SATA1GP / GPIO19 P1

JTAG_TCK

J3

JTAG_TMS

H7

JTAG_TDI

K5

JTAG_TDO

H1

SERIRQ V5

SPKR

T10

SATAICOMPO Y11

SATA3COMPI AB13

SATA3RCOMPO AB12

SATA3RBIAS AH1

RH20

200_0402_5%

@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMBCLK

SMBDATA

XTAL25_OUT

XTAL25_IN

XTAL25_IN

XTAL25_OUT

SMBCLK

SMBDATA

SML1CLK

SML1DATA

SML0CLK

SML0DATA

DRAMRST_CNTRL_PCH

SML1CLK

SML1DATA

SML0CLK

SML0DATA

XCLK_RCOMP

CLK_PCI_LPBACK

CLK_CPU_DMI

CLK_CPU_DMI#

CLK_CPU_ITP#

GPIO46

CLK_BCLK_ITP

CLK_BCLK_ITP#

CLK_CPU_ITP

GPIO56

DRAMRST_CNTRL_PCH

CLK_BCLK_ITP

CLK_PCH_14M

CLKIN_DOT96

CLKIN_DOT96#

CLKIN_DMI

CLKIN_DMI#

CLKIN_SATA

CLKIN_SATA#

CLKIN_DMI#

CLKIN_DMI

CLKIN_DMI2#

CLKIN_DMI2

CLKIN_DOT96

CLKIN_DOT96#

CLKIN_SATA

CLKIN_SATA#

CLK_PCH_14M

SMBCLK

SMBDATA

SML1CLK

SML1DATA

PCIE_PRX_WLANTX_P2

PCIE_PRX_WLANTX_N2

PCIE_PTX_WLANRX_P2_C

PCIE_PTX_WLANRX_N2_C

PCIE_PTX_LANRX_P1_C

PCIE_PTX_LANRX_N1_C

PCIE_PRX_LANTX_P1

PCIE_PRX_LANTX_N1

PCIE_PRX_EXPTX_P3

PCIE_PRX_EXPTX_N3

PCIE_PTX_EXPRX_P3_C

PCIE_PTX_EXPRX_N3_C

GPIO26

PCIE_EXP

EXPCLK_REQ#

PCIE_EXP#

GPIO44

PCIE_WLAN

PCIE_WLAN#

WLAN_CLKREQ#

GPIO25

PCIE_LAN

PCIE_LAN#

LAN_CLKREQ#

CLKIN_DMI2

CLKIN_DMI2#

PEG_A_CLKRQ#

CLK_PEG_VGA

CLK_PEG_VGA#

SMBALERT#

GPIO45

CLK_PCH_14M

CLK_PCI_LPBACK

CLK_14M_R

CLK_FLEX0

DGPU_PRSNT#

PCH_HOT#

PCH_HOT#

SMBALERT#

CLK_LAN_25M_R

CLK_LAN_25M

XTAL25_IN

PCH_SMLCLK <24>

PCH_SMLDATA <24>

CLK_CPU_DMI# <6>

CLK_CPU_DMI <6>

CLK_CPU_ITP#<6>

CLK_CPU_ITP<6>

DRAMRST_CNTRL_PCH <7>

CLK_RES_ITP#<8>

CLK_RES_ITP<8>

CLK_PCI_LPBACK <16>

PCIE_PRX_WLANTX_N2<32>

PCIE_PTX_WLANRX_N2<32>

PCIE_PRX_WLANTX_P2<32>

PCIE_PTX_WLANRX_P2<32>

PCIE_PRX_LANTX_N1<32>

PCIE_PTX_LANRX_N1<32>

PCIE_PRX_LANTX_P1<32>

PCIE_PTX_LANRX_P1<32>

PCIE_PTX_EXPRX_N3<28>

PCIE_PRX_EXPTX_N3<28>

PCIE_PTX_EXPRX_P3<28>

PCIE_PRX_EXPTX_P3<28>

CLK_PCIE_EXP<28>

CLK_PCIE_EXP#<28>

EXPCLK_REQ#<28>

CLK_PCIE_WLAN#<32>

CLK_PCIE_WLAN<32>

WLAN_CLKREQ#<32>

CLK_PCIE_LAN#<32>

CLK_PCIE_LAN<32>

LAN_CLKREQ#<32>

PCH_SMBCLK <6,11,12,28,29,32>

PCH_SMBDATA <6,11,12,28,29,32>

CLK_PEG_VGA <34>

CLK_PEG_VGA# <34>

PEG_A_CLKRQ# <35>

PCH_HOT# <24>

CLK_LAN_25M <32>

LAN_X1<31>

PCH_X1<31>

+3V_PCH

+1.05VS_VCCDIFFCLKN

+3V_PCH

+3V_PCH

+3VS

+3V_PCH

+3V_PCH

+3VS

+3V_PCH

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3VS

+3V_PCH

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

14 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

Total device

MEMORY

20090512

add double mosfet prevent

ATI M92 electric leakage

If use extenal CLK gen, please place close to CLK gen

else, please place close to PCH

Express Card --->

WLAN (Mini Card 1)--->

10/100/1G LAN --->

10/100/1G LAN --->

Express Card --->

WLAN (Mini Card 1)--->

No support iAMT

Reserve for EMI please close to

UH1

*PCIE REQ power rail:

suspend: 0 3 4 5 6 7

core: 1 2

close to RH270

close to YH2

QH3A

DMN66D0LDW-7_SOT363-6

61

2

RH270 22_0402_5%

@

12

RH94 0_0402_5%@

12

RH50 2.2K_0402_5%

1 2

CH21 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~D

1 2

RH92 0_0402_5%

12

CH16 0.1U_0402_10V7K~D

1 2

RH46 2.2K_0402_5%

1 2

RH71

2.2K_0402_5%

1 2

RH76 0_0402_5%

12

CH19 0.1U_0402_10V7K~D

1 2

RH59 10K_0402_5%

1 2

QH2B

DMN66D0LDW-7_SOT363-6

3

5

4

RH54 10K_0402_5%

1 2

CH15 0.1U_0402_10V7K~D

1 2

RH64

10K_0402_5%

1 2

RH65

33_0402_5%

@

12

RH891M_0402_5%

12

RH31 0_0402_5%

GCLK@

1 2

YH2

25MHZ_20PF_FSX3M-25.M20FDO

OSC 1

OSC 3

GND

2

GND

4

RH60 10K_0402_5%

1 2

PCI-E*

CLOCKS

FLEX CLOCKS

SMBUSController

Link

UH1B

BD82HM77 QPRG C1 BGA 989P PCH

PERN1

BG34

PERP1

BJ34

PERN2

BE34

PERP2

BF34

PERN3

BG36

PERP3

BJ36

PERN4

BF36

PERP4

BE36

PERN5

BG37

PERP5

BH37

PERN6

BJ38

PERP6

BG38

PERN7

BG40

PERP7

BJ40

PERN8

BE38

PERP8

BC38

PETN1

AV32

PETP1

AU32

PETN2

BB32

PETP2

AY32

PETN3

AV34

PETP3

AU34

PETN4

AY34

PETP4

BB34

PETN5

AY36

PETP5

BB36

PETN6

AU36

PETP6

AV36

PETN7

AY40

PETP7

BB40

PETN8

AW38

PETP8

AY38

CLKOUT_PCIE0N

Y40

CLKOUT_PCIE0P

Y39

CLKOUT_PCIE1N

AB49

CLKOUT_PCIE1P

AB47

CLKOUT_PCIE2N

AA48

CLKOUT_PCIE2P

AA47

CLKOUT_PCIE3N

Y37

CLKOUT_PCIE3P

Y36

CLKOUT_PCIE4N

Y43

CLKOUT_PCIE4P

Y45

CLKOUT_PCIE5N

V45

CLKOUT_PCIE5P

V46

CLKIN_GND1_N BJ30

CLKIN_GND1_P BG30

CLKIN_DMI_N BF18

CLKIN_DMI_P BE18

CLKIN_DOT_96N G24

CLKIN_DOT_96P E24

CLKIN_SATA_N AK7

CLKIN_SATA_P AK5

XTAL25_IN V47

XTAL25_OUT V49

REFCLK14IN K45

CLKIN_PCILOOPBACK H45

CLKOUT_PEG_A_N AB37

CLKOUT_PEG_A_P AB38

PEG_A_CLKRQ# / GPIO47 M10

PCIECLKRQ0# / GPIO73

J2

PCIECLKRQ1# / GPIO18

M1

PCIECLKRQ2# / GPIO20

V10

PCIECLKRQ3# / GPIO25

A8

PCIECLKRQ4# / GPIO26

L12

PCIECLKRQ5# / GPIO44

L14

CLKOUTFLEX0 / GPIO64 K43

CLKOUTFLEX1 / GPIO65 F47

CLKOUTFLEX2 / GPIO66 H47

CLKOUTFLEX3 / GPIO67 K49

CLKOUT_DMI_N AV22

CLKOUT_DMI_P AU22

PEG_B_CLKRQ# / GPIO56

E6

CLKOUT_PEG_B_P

AB40 CLKOUT_PEG_B_N

AB42

XCLK_RCOMP Y47

CLKOUT_DP_P AM13

CLKOUT_DP_N AM12

CLKOUT_PCIE6N

V40

CLKOUT_PCIE6P

V42

PCIECLKRQ7# / GPIO46

K12

CLKOUT_PCIE7N

V38

CLKOUT_PCIE7P

V37

CLKOUT_ITPXDP_N

AK14

CLKOUT_ITPXDP_P

AK13

SMBALERT# / GPIO11 E12

SMBCLK H14

SMBDATA C9

SML0ALERT# / GPIO60 A12

SML0CLK C8

SML0DATA G12

SML1ALERT# / PCHHOT# / GPIO74 C13

SML1CLK / GPIO58 E14

SML1DATA / GPIO75 M16

CL_CLK1 M7

CL_DATA1 T11

CL_RST1# P10

PCIECLKRQ6# / GPIO45

T13

RH261

10K_0402_5%DIS@

1 2

RH63

33_0402_5%

@

12

RH125

22_0402_5%

1 2

RH61 10K_0402_5%

1 2

RH72

2.2K_0402_5%

1 2

RH269 10K_0402_5%

UMA@

12

RH78

0_0402_5%

@

1 2

RH66 10K_0402_5%

1 2

RH83 10K_0402_5%

1 2

RH41 0_0402_5%

GCLK@

1 2

CH28

27P_0402_50V8J

1

2

RH52 10K_0402_5%

1 2

CH25

22P_0402_50V8J~D

@

1 2

RH75 0_0402_5%

12

RH90 10K_0402_5%

1 2

RH69 10K_0402_5%

12

RH88 10K_0402_5%

1 2

RH82

0_0402_5%

@

1 2

RH91 0_0402_5%

12

CH22 0.1U_0402_10V7K~D

1 2

RH62 10K_0402_5%

1 2

RH67 0_0402_5%

1 2

QH3B

DMN66D0LDW-7_SOT363-6

3

5

4

RH68 0_0402_5%

1 2

T53 PAD~D@

RH85 90.9_0402_1%

1 2

RH81 10K_0402_5%

12

RH55 10K_0402_5%

1 2

RH84 10K_0402_5%

1 2

RH53 1K_0402_5%

1 2

QH2A

DMN66D0LDW-7_SOT363-6

6 1

2

RH77 10K_0402_5%

12

RH56 10K_0402_5%

1 2

CH27

27P_0402_50V8J

1

2

RH57 10K_0402_5%

1 2

RH47 2.2K_0402_5%

1 2

T54 PAD~D@

RH58 10K_0402_5%

1 2

RH49 2.2K_0402_5%

1 2

CH26

22P_0402_50V8J~D

@

1 2

RH86 10K_0402_5%

1 2

RH80 0_0402_5%

12

RH79 0_0402_5%

12

RH93 0_0402_5%@

12

RH45 2.2K_0402_5%

1 2

RH74 10K_0402_5%

12

RH51 2.2K_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DMI_IRCOMP

EC_RSMRST#

GPIO72

AC_PRESENT_R

DMI_CRX_PTX_N1

DMI_CRX_PTX_P0

DMI_CRX_PTX_P3

DMI_CTX_PRX_P0

DMI_CRX_PTX_N2

DMI_CRX_PTX_P1

DMI_CTX_PRX_P2

DMI_CTX_PRX_N2

DMI_CTX_PRX_N3

DMI_CTX_PRX_P3

DMI_CRX_PTX_P2

DMI_CTX_PRX_N1

DMI_CRX_PTX_N0

DMI_CTX_PRX_N0

DMI_CTX_PRX_P1

DMI_CRX_PTX_N3

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC1

FDI_LSYNC0

FDI_CTX_PRX_N0

FDI_CTX_PRX_N1

FDI_CTX_PRX_N2

FDI_CTX_PRX_N3

FDI_CTX_PRX_N4

FDI_CTX_PRX_N5

FDI_CTX_PRX_N6

FDI_CTX_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

FDI_CTX_PRX_P5

RI#

XDP_DBRESET#

RBIAS_CPY

SYS_PWROK_R

SUSWARN#

PM_DRAM_PWRGD

PCH_RSMRST#_R

DSWODVREN

WAKE#

PM_CLKRUN#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

SUSCLK

SUSWARN#

CRT_IREF

PCH_ENVDD

DSWODVREN

RI#

PCIE_WAKE#

CTRL_CLK

CTRL_DATA

DSWODVREN

SUS_STAT#

LVDS_IBG

LVDS_DDC_CLK

LVDS_DDC_DATA

PM_CLKRUN#

GPIO72

PM_CLKRUN#

CTRL_CLK

CTRL_DATA

LVDS_IBG

PCH_ENVDD

ENBKL

LVDS_DDC_CLK

LVDS_DDC_DATA

ENBKL

LVDS_B0+

LVDS_B1-

LVDS_B2-

LVDS_B1+

LVDS_B2+

LVDS_B0-

LVDS_A1-

LVDS_A2-

LVDS_A0+

LVDS_A2+

LVDS_A0-

LVDS_A1+

LVDS_ACLK-

LVDS_ACLK+

LVDS_BCLK-

LVDS_BCLK+

SYS_PWROK

PCH_PWROK

SYS_PWROK

SUSCLK

HDMI_A2N_VGA

HDMI_A2P_VGA

HDMI_A1N_VGA

HDMI_A1P_VGA

HDMI_A0N_VGA

HDMI_A0P_VGA

HDMI_A3N_VGA

HDMI_A3P_VGA

HDMI_DET

PCH_SDVO_CTRLDATA

PCH_SDVO_CTRLCLK

CRT_DDC_DATA

CRT_DDC_CLK

HSYNC

VSYNC

CRT_B

CRT_G

CRT_R

CRT_B

CRT_G

CRT_R

CRT_DDC_CLK

CRT_DDC_DATA

PCH_RSMRST#_RPCH_DPWROK

AC_PRESENT_R

WAKE#

DMI_CTX_PRX_N0<5>

DMI_CRX_PTX_N2<5>

DMI_CTX_PRX_N1<5>

DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_N2<5>

DMI_CTX_PRX_P0<5>

DMI_CTX_PRX_P1<5>

DMI_CTX_PRX_P3<5>

DMI_CTX_PRX_P2<5>

DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_N1<5>

DMI_CRX_PTX_N0<5>

DMI_CRX_PTX_P2<5>

DMI_CRX_PTX_P3<5>

DMI_CRX_PTX_P1<5>

DMI_CRX_PTX_P0<5>

FDI_CTX_PRX_N0 <5>

FDI_CTX_PRX_N1 <5>

FDI_CTX_PRX_N2 <5>

FDI_CTX_PRX_N3 <5>

FDI_CTX_PRX_N4 <5>

FDI_CTX_PRX_N5 <5>

FDI_CTX_PRX_N6 <5>

FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>

FDI_CTX_PRX_P1 <5>

FDI_CTX_PRX_P2 <5>

FDI_CTX_PRX_P3 <5>

FDI_CTX_PRX_P4 <5>

FDI_CTX_PRX_P5 <5>

FDI_CTX_PRX_P6 <5>

FDI_CTX_PRX_P7 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_FSYNC0 <5>

FDI_INT <5>

FDI_LSYNC1 <5>

XDP_DBRESET#<6>

PM_DRAM_PWRGD<6>

EC_RSMRST#<24>

PBTN_OUT#<6,24>

PCIE_WAKE# <24,28,32>

H_PM_SYNC <6>

PM_SLP_S3# <24,28>

PM_SLP_S4# <24>

PM_SLP_S5# <24>

PCH_PWROK<6,24> SUSCLK_R <24>

ENBKL<24>

PCH_ENVDD<22>

VGA_PWM<22>

LVDS_DDC_DATA<22>

LVDS_DDC_CLK<22>

LVDS_B1-<22>

LVDS_B1+<22>

LVDS_B2-<22>

LVDS_B2+<22>

LVDS_B0+<22>

LVDS_B0-<22>

LVDS_A1-<22>

LVDS_A1+<22>

LVDS_A2-<22>

LVDS_A2+<22>

LVDS_A0-<22>

LVDS_A0+<22>

LVDS_ACLK+<22>

LVDS_ACLK-<22>

LVDS_BCLK+<22>

LVDS_BCLK-<22>

VGATE<6,50>

PCH_PWROK<6,24>

SYS_PWROK <6>

HDMI_A3N_VGA <23>

HDMI_A3P_VGA <23>

HDMI_A2N_VGA <23>

HDMI_A2P_VGA <23>

HDMI_A1P_VGA <23>

HDMI_A1N_VGA <23>

HDMI_A0P_VGA <23>

HDMI_A0N_VGA <23>

HDMI_DET <23>

PCH_SDVO_CTRLDATA <23>

PCH_SDVO_CTRLCLK <23>

CRT_R<21>

CRT_G<21>

CRT_B<21>

CRT_VSYNC<21>

CRT_HSYNC<21>

CRT_DDC_DATA<21>

CRT_DDC_CLK<21>

ACIN<24,35,43,44>

+1.05VS

+3V_PCH

+3VS

+RTCVCC

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

15 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

4mil width and place

within 500mil of the PCH

If not using integrated

LAN,signal may be left as NC.

Can be left NC when IAMT is

not support on the platfrom

H Enable

L Disable

DSWODVREN - On Die DSW VR Enable

*

Compal Electronics, Inc.

Check EC for S3 S4 LED

mDP

HDMI

DMC

Reserve for RF please close to UH1

RH235 150_0402_1%

1 2

RH236 150_0402_1%

1 2

RH202 33_0402_5%

1 2

DMI

FDI

System Power Management

UH1C

BD82HM77 QPRG C1 BGA 989P PCH

DMI0RXN

BC24

DMI1RXN

BE20

DMI2RXN

BG18

DMI3RXN

BG20

DMI0RXP

BE24

DMI1RXP

BC20

DMI2RXP

BJ18

DMI3RXP

BJ20

DMI0TXN

AW24

DMI1TXN

AW20

DMI2TXN

BB18

DMI3TXN

AV18

DMI0TXP

AY24

DMI1TXP

AY20

DMI2TXP

AY18

DMI3TXP

AU18

DMI_ZCOMP

BJ24

DMI_IRCOMP

BG25

FDI_RXN0 BJ14

FDI_RXN1 AY14

FDI_RXN2 BE14

FDI_RXN3 BH13

FDI_RXN4 BC12

FDI_RXN5 BJ12

FDI_RXN6 BG10

FDI_RXN7 BG9

FDI_RXP0 BG14

FDI_RXP1 BB14

FDI_RXP2 BF14

FDI_RXP3 BG13

FDI_RXP4 BE12

FDI_RXP5 BG12

FDI_RXP6 BJ10

FDI_RXP7 BH9

FDI_FSYNC0 AV12

FDI_FSYNC1 BC10

FDI_LSYNC0 AV14

FDI_LSYNC1 BB10

FDI_INT AW16

PMSYNCH AP14

SLP_SUS# G16

SLP_S3# F4

SLP_S4# H4

SLP_S5# / GPIO63 D10

SYS_RESET#

K3

SYS_PWROK

P12

PWRBTN#

E20

RI#

A10

WAKE# B9

SUS_STAT# / GPIO61 G8

SUSCLK / GPIO62 N14

ACPRESENT / GPIO31

H20

BATLOW# / GPIO72

E10

PWROK

L22

CLKRUN# / GPIO32 N3

SUSWARN#/SUSPWRDNACK/GPIO30

K16

RSMRST#

C21

DRAMPWROK

B13

SLP_LAN# / GPIO29 K14

APWROK

L10

DPWROK E22

DMI2RBIAS

BH21

SLP_A# G10

DSWVRMEN A18

SUSACK#

C12

RH99 49.9_0402_1%

1 2

RH100 750_0402_1%~D

1 2

RH118 10K_0402_5%@

1 2

CH30

0.1U_0402_16V7K

1

2

RH239 2.2K_0402_5%

@

1 2

RH106 0_0402_5%

1 2

RH137 2.2K_0402_5%

1 2

RH107 0_0402_5%

12

T57PAD~D

RH238 2.2K_0402_5%

@

1 2

UH3

MC74VHC1G08DFT2G_SC70-5

IN1

1

IN2

2OUT 4

VCC 5

GND

3

RH116 10K_0402_5%

1 2

LVDS

Digital Display Interface

CRT

UH1D

BD82HM77 QPRG C1 BGA 989P PCH

L_BKLTCTL

P45

L_BKLTEN

J47

L_CTRL_CLK

T45

L_CTRL_DATA

P39

L_DDC_CLK

T40

L_DDC_DATA

K47

L_VDD_EN

M45

LVDSA_CLK#

AK39

LVDSA_CLK

AK40

LVDSA_DATA#0

AN48

LVDSA_DATA#1

AM47

LVDSA_DATA#2

AK47

LVDSA_DATA#3

AJ48

LVDSA_DATA0

AN47

LVDSA_DATA1

AM49

LVDSA_DATA2

AK49

LVDSA_DATA3

AJ47

LVDSB_CLK#

AF40

LVDSB_CLK

AF39

LVDSB_DATA#0

AH45

LVDSB_DATA#1

AH47

LVDSB_DATA#2

AF49

LVDSB_DATA#3

AF45

LVDSB_DATA0

AH43

DDPB_0N AV42

DDPB_1N AV45

LVD_VREFH

AE48

LVD_VREFL

AE47

DDPD_2N BF42

DDPD_3N BJ42

DDPB_2N AU48

DDPB_3N AV47

DDPC_0N AY47

DDPC_1N AY43

DDPC_2N BA47

DDPC_3N BB47

DDPD_0N BB43

DDPD_1N BF44

DDPB_0P AV40

DDPB_1P AV46

DDPD_2P BE42

DDPD_3P BG42

DDPB_2P AU47

DDPB_3P AV49

LVDSB_DATA1

AH49

LVDSB_DATA2

AF47

LVDSB_DATA3

AF43

LVD_IBG

AF37

LVD_VBG

AF36

DDPC_1P AY45

DDPC_0P AY49

DDPC_2P BA48

DDPC_3P BB49

DDPD_0P BB45

DDPD_1P BE44

CRT_BLUE

N48

CRT_DDC_CLK

T39

CRT_DDC_DATA

M40

CRT_GREEN

P49

CRT_HSYNC

M47

CRT_IRTN

T42

CRT_RED

T49

CRT_VSYNC

M49

DAC_IREF

T43

SDVO_CTRLCLK P38

SDVO_CTRLDATA M39

DDPC_CTRLCLK P46

DDPC_CTRLDATA P42

DDPD_CTRLCLK M43

DDPD_CTRLDATA M36

DDPB_AUXN AT49

DDPC_AUXN AP47

DDPD_AUXN AT45

DDPB_AUXP AT47

DDPC_AUXP AP49

DDPD_AUXP AT43

DDPB_HPD AT40

DDPC_HPD AT38

DDPD_HPD BH41

SDVO_TVCLKINP AP45

SDVO_TVCLKINN AP43

SDVO_STALLP AM40

SDVO_STALLN AM42

SDVO_INTP AP40

SDVO_INTN AP39

RH108 0_0402_5%

1 2

RH104 0_0402_5%

1 2

RH135 2.2K_0402_5%

1 2

RH117 10K_0402_5%

1 2

RH237 150_0402_1%

1 2

RH230 33_0402_5%

1 2

RH138 2.2K_0402_5%

1 2

RH123 2.37K_0402_1%

1 2

RH134 100K_0402_5%

1 2

RH103 0_0402_5%

@

1 2

RH234 2.2K_0402_5%

1 2

RH233 2.2K_0402_5%

1 2

RH122 330K_0402_5%@

12

RH133 2.2K_0402_5%

1 2

DH4

RB751V-40_SOD323-2

1 2

RH132 100K_0402_5%

1 2

RH126 10K_0402_5%

1 2

RH105 0_0402_5%

1 2

RH110 0_0402_5%

1 2

RH121 200K_0402_5%

1 2

RH136 8.2K_0402_5%@

1 2

RH128 0_0402_5%

1 2

RH124 10K_0402_5%

1 2

RH115

1K_0402_0.5%

12

T59 PAD~D

T58 PAD~D

RH119 330K_0402_5%

12

CH29

10P_0402_50V8J

@

12

RH127 10K_0402_5%

1 2

RH120 10K_0402_5%

1 2

T56PAD~D

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBRBIAS

PCH_PLTRST#

PCH_PLTRST#

NV_ALE

PCI_PIRQA#

PCI_PIRQD#

PCI_PIRQC#

PCI_PIRQB#

CLK_PCI0

CLK_PCI1

USB20_N4

USB20_P4

USB20_P2

USB20_N2

CLK_PCI_LPBACK

CLK_PCI_LPC

FFS_INT1

GPIO51

ODD_DA#

DGPU_HOLD_RST#

USB20_N12

USB20_P12

CLK_PCI2

CLK_PCI3

USB_OC2#

USB_OC0#

USB_OC5#

USB_OC3#

USB_OC1#

USB_OC4#

USB_OC4#

USB_OC0#

USB_OC7#

USB_OC3#

USB_OC2#

USB_OC1#

USB20_N1

USB20_P1

PXS_PWREN

GPIO52

CLK_PCI4

WL_OFF#

GPIO5

USB_OC5#

USB_OC6#

CLK_PCI1

USB_OC7#

USB_OC6#

PCI_PIRQD#

DGPU_HOLD_RST#

GPIO52

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQA#

ODD_DA#

GPIO51

WL_OFF#

FFS_INT1

PXS_PWREN

USB20_N0

USB20_P0

USB3RN1

USB3RN2

USB3TN1

USB3TN2

USB3RN3

USB3TN3

USB3RP1

USB3RP2

USB3RP3

USB3TP2

USB3TP1

USB3TP3

USB3RN4

USB3RP4

USB3TN4

USB3TP4

USB20_P3

USB20_N3

USB20_N11

USB20_P11

USB20_N10

USB20_P10

USB20_N8

USB20_P8

GPIO5

GPIO4

GPIO4

USB20_N5

USB20_P5

PLT_RST#<6,24,28,32>

USB20_N4 <32>

USB20_P4 <32>

USB20_N2 <32>

USB20_P2 <32>

CLK_PCI_LPBACK<14>

CLK_PCI_LPC<24>

FFS_INT1<29>

ODD_DA#<29>

USB20_N12 <22>

USB20_P12 <22>

USB_OC0# <33>

USB_OC2# <32>

USB_OC3# <32>

USB20_N1 <33>

USB20_P1 <33>

PXS_PWREN<36,52>

WL_OFF#<32>

USB20_N0 <33>

USB20_P0 <33>

USB3RN1<33>

USB3RN2<33>

USB3TN1<33>

USB3TN2<33>

USB3RN3<32>

USB3TN3<32>

USB3RP1<33>

USB3RP2<33>

USB3RP3<32>

USB3TP3<32>

USB3TP2<33>

USB3TP1<33>

USB3RN4<32>

USB3RP4<32>

USB3TN4<32>

USB3TP4<32>

USB20_P3 <32>

USB20_N3 <32>

USB20_N11 <28>

USB20_P11 <28>

USB20_N10 <32>

USB20_P10 <32>

USB20_N8 <32>

USB20_P8 <32>

USB_OC1# <33>

PCH_PLTRST#<34>

DGPU_HOLD_RST#<34>

USB20_N5 <32>

USB20_P5 <32>

+3VS

+1.8VS

+3VS

+3V_PCH

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

16 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

Intel Anti-Theft Techonlogy

*

NV_ALE High=Endabled

Low=Disable(floating)

Mini Card-1 (WLAN)

Within 500 mils

Camera

USB Conn 1

Reserve for RF please close to PCH

USB Conn 2 (with PWR Share)

USB Conn 3

USB Conn 4

Express Card

Card Reader

Finger Print

Mini Card-2 (mSATA)

RH143 22.6_0402_1%

1 2

T60PAD~D @

CH101

0.1U_0402_25V6K

1 2

RPH2

8.2K_0804_8P4R_5%

18

27

36

45

T63PAD~D @

RH144 22_0402_5%

12

RPH1

8.2K_0804_8P4R_5%

18

27

36

45

T62PAD~D @

RSVD

PCI

USB

UH1E

BD82HM77 QPRG C1 BGA 989P PCH

RSVD23 AV5

RSVD1 AY7

RSVD2 AV7

RSVD3 AU3

RSVD4 BG4

RSVD5 AT10

RSVD6 BC8

RSVD7 AU2

RSVD8 AT4

RSVD17 BB5

RSVD18 BB3

RSVD19 BB7

RSVD20 BE8

RSVD21 BD4

RSVD22 BF6

RSVD9 AT3

RSVD10 AT1

RSVD11 AY3

RSVD12 AT5

RSVD13 AV3

RSVD14 AV1

RSVD15 BB1

RSVD16 BA3

RSVD25 AT8

RSVD24 AV10

RSVD26 AY5

RSVD27 BA2

RSVD28 AT12

RSVD29 BF3

PIRQA#

K40

PIRQB#

K38

PIRQC#

H38

PIRQD#

G38

REQ1# / GPIO50

C46

REQ2# / GPIO52

C44

REQ3# / GPIO54

E40

GNT1# / GPIO51

D47

GNT2# / GPIO53

E42

GNT3# / GPIO55

F46

PIRQE# / GPIO2

G42

PIRQF# / GPIO3

G40

PIRQG# / GPIO4

C42

PIRQH# / GPIO5

D44

USBP0N C24

USBP0P A24

USBP1N C25

USBP1P B25

USBP2N C26

USBP2P A26

USBP3N K28

USBP3P H28

USBP4N E28

USBP4P D28

USBP5N C28

USBP5P A28

USBP6N C29

USBP6P B29

USBP7N N28

USBP7P M28

USBP8N L30

USBP8P K30

USBP9N G30

USBP9P E30

USBP10N C30

USBP10P A30

USBP11N L32

USBP11P K32

USBP12N G32

USBP12P E32

USBP13N C32

USBP13P A32

PME#

K10

CLKOUT_PCI0

H49

CLKOUT_PCI1

H43

CLKOUT_PCI2

J48

USBRBIAS# C33

USBRBIAS B33

OC0# / GPIO59 A14

OC1# / GPIO40 K20

OC2# / GPIO41 B17

OC3# / GPIO42 C16

OC4# / GPIO43 L16

OC5# / GPIO9 A16

OC6# / GPIO10 D14

OC7# / GPIO14 C14

CLKOUT_PCI4

H40 CLKOUT_PCI3

K42

PLTRST#

C6

TP1

BG26

TP2

BJ26

TP3

BH25

TP6

AH38

TP7

AH37

TP8

AK43

TP9

AK45

TP16

Y13

TP17

K24

TP18

L24

TP19

AB46

TP20

AB45

TP21

B21

TP22

M20

TP23

AY16

TP25

BE28

TP26

BC30

TP27

BE32

TP28

BJ32

TP29

BC28

TP30

BE30

TP31

BF32

TP32

BG32

TP33

AV26

TP34

BB26

TP35

AU28

TP36

AY30

TP37

AU26

TP38

AY26

TP39

AV28

TP40

AW30

TP4

BJ16

TP5

BG16

TP15

AM5 TP14

AM4 TP13

AH12 TP12

H3 TP11

N30 TP10

C18

TP24

BG46

RPH5

10K_1206_8P4R_5%

1 8

2 7

3 6

4 5

RH149 0_0402_5%

@

1 2

RPH4

10K_1206_8P4R_5%

1 8

2 7

3 6

4 5

T61PAD~D @

RH145 22_0402_5%

1 2

UH5

SN74AHC1G08DCKR_SC70-5

IN1 1

IN2 2

G

3

O

4

P5

CH31

10P_0402_50V8J

@

12

RPH3

8.2K_0804_8P4R_5%

18

27

36

45

RH150

10K_0402_5%

@

1 2

RH139 1K_0402_5%@1 2

RH155

100K_0402_5%

12

RH14010K_0402_5% 12

RH157

10K_0402_5%

@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_THERMTRIP#_C

CRT_DET#

BT_ON#

PCH_GPIO28

PCH_PECI_R

KB_RST#

INIT3_3V#

VGA_PWRGD

PCH_GPIO37

PCH_GPIO37

GPIO1 PCH_GPIO37

CRT_DET

CRT_DET

PCH_GPIO28

PCH_GPIO27

PCH_GPIO27

GPIO35

HDD_DETECT#

KB_RST#

ODD_DETECT#

ODD_EN#

PCH_GPIO22

PCH_GPIO22

EC_SMI#

EC_SMI#

H_THERMTRIP#

NV_CLE

EC_SCI#

ODD_DETECT#

GPIO69

FFS_INT2

NV_CLE

HDD_DETECT#

GPIO35

GPIO49

GPIO49

GPIO1

PCH_GPIO38

PCH_GPIO39

PCH_GPIO38

PCH_GPIO39

ODD_EN#

BT_ON#

GPIO6

GPIO6

GPIO16

GPIO16

PCH_LID_SW_IN#EC_LID_OUT#

PCH_LID_SW_IN#

PCH_GPIO28

VGA_PWRGD

KB_DET#

GATEA20 <24>

H_PECI <6,24>

H_CPUPWRGD <6>

KB_RST# <24>

H_THERMTRIP# <6>

CRT_DET#<21>

EC_SMI#<24>

EC_SCI#<24>

ODD_DETECT#<29>

FFS_INT2<29>

H_SNB_IVB# <6>

HDD_DETECT#<32>

ODD_EN# <29>

BT_ON#<32>

VGA_PWRGD<36,52>

EC_LID_OUT#<24>

KB_DET#<26>

+3V_PCH

+3VS

+3VS

+3VS

+3VS

+3VS

+1.8VS

+3V_PCH

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

17 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

*

This signal has a weak internal pull up

On-Die PLL Voltage Regulator

L On-Die PLL Voltage Regulator disable

GPIO28

H On-Die voltage regulator enable

LOW - Tx, Rx terminated

to same voltage

(DC Coupling Mode)

FDI TERMINATION VOLTAGE OVERRIDE

PCH_GPIO37

*

High: CRT Plugged

PCH_GPIO28 needs to be connected to XDP_FN8

PCH_GPIO35 needs to be connected to XDP_FN9

PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

INIT3_3V

This signal has weak internal

PU, can't pull low

Weak internal

PU,Do not pull low

Set to Vcc when HIGH

DMI Termination Voltage

NV_CLE

Set to Vss when LOW

CLOSE TO THE BRANCHING POINT

RH161 and RH162

Follow CRB FAB2 setting

RH159

10K_0402_5%

1 2

RH1610_0402_5%

@

1 2

RH173 10K_0402_5%@

1 2

RH166

2.2K_0402_5%

12

RH241

10K_0402_5% 12

RH162390_0402_5%

1 2

RH181

10K_0402_5%

1 2

RH170

10K_0402_5%@

1 2

RH168 1K_0402_5%@12

RH172

10K_0402_5%

1 2

RH178

10K_0402_5%

1 2

CPU/MISC

NCTF

GPIO

UH1F

BD82HM77 QPRG C1 BGA 989P PCH

GPIO27

E16

GPIO28

P8

GPIO24 / MEM_LED

E8

GPIO57

D6

LAN_PHY_PWR_CTRL / GPIO12

C4

VSS_NCTF_1

A4

VSS_NCTF_2

A44

VSS_NCTF_3

A45

VSS_NCTF_4

A46

VSS_NCTF_5

A5

VSS_NCTF_6

A6

VSS_NCTF_7

B3

VSS_NCTF_8

B47

VSS_NCTF_9

BD1

VSS_NCTF_10

BD49

VSS_NCTF_11

BE1

VSS_NCTF_12

BE49

TACH2 / GPIO6

H36

TACH0 / GPIO17

D40

TACH3 / GPIO7

E38

SATA3GP / GPIO37

M5

SATA5GP / GPIO49

V3

SCLOCK / GPIO22

T5

SLOAD / GPIO38

N2

SDATAOUT0 / GPIO39

M3

SDATAOUT1 / GPIO48

V13

PROCPWRGD AY11

RCIN# P5

PECI AU16

THRMTRIP# AY10

GPIO8

C10

BMBUSY# / GPIO0

T7

GPIO15

G2

TACH1 / GPIO1

A42

SATA2GP / GPIO36

V8

INIT3_3V# T14

STP_PCI# / GPIO34

K1

GPIO35

K4

SATA4GP / GPIO16

U2

VSS_NCTF_32 F49

A20GATE P4

TACH4 / GPIO68 C40

TACH6 / GPIO70 C41

TACH7 / GPIO71 A40

TACH5 / GPIO69 B41

VSS_NCTF_17 BH3

VSS_NCTF_18 BH47

VSS_NCTF_19 BJ4

VSS_NCTF_20 BJ44

VSS_NCTF_21 BJ45

VSS_NCTF_22 BJ46

VSS_NCTF_23 BJ5

VSS_NCTF_24 BJ6

VSS_NCTF_25 C2

VSS_NCTF_26 C48

VSS_NCTF_27 D1

VSS_NCTF_28 D49

VSS_NCTF_29 E1

VSS_NCTF_30 E49

VSS_NCTF_31 F1

TS_VSS4 AK10

TS_VSS3 AH10

TS_VSS2 AK11

TS_VSS1 AH8

NC_1 P37

VSS_NCTF_13

BF1

VSS_NCTF_14

BF49

VSS_NCTF_15 BG2

VSS_NCTF_16 BG48

DF_TVS AY1

RH179

10K_0402_5%

1 2

RH169

10K_0402_5%

1 2

RH163

10K_0402_5%

@

12

RH16410K_0402_5% 12

RH183

10K_0402_5%

1 2

RH160

10K_0402_5%

1 2

RH176

10K_0402_5%

1 2

RH242

10K_0402_5%

1 2

RH175

10K_0402_5%

1 2

RH177

10K_0402_5%

1 2

RH240

1K_0402_5% 12

RH184

10K_0402_5%

1 2

G

D

S

QH4

SSM3K7002F_SC59-3

2

13

RH174

8.2K_0402_5%

1 2

RH171

200K_0402_5%

1 2

RH182

10K_0402_5%

1 2

RH730_0402_5%

1 2

RH180

10K_0402_5%

1 2

RH165 1K_0402_5%@

1 2

RH1671K_0402_5%

12

T64 PAD~D@

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.05VS_VCCCORE

+VCCAPLLEXP

+1.05VS_VCC_EXP

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+VCCADAC

+VCCAFDI_VRM

+VCCA_LVDS

+3V_VCCPSPI

+1.05VS_VCCDPLLEXP

+3VS_VCCA3GBG

+1.05VS_VCCDPLL_FDI

+1.05VS_VCC_DMI_CCI

+VCCTX_LVDS

+VCCP_VCCDMI

+VCCAPLLEXP_R

+3VS_VCC3_3_6

+VCCAFDI_VRM

+1.5VS +VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS

+1.05VS

+3VS

+1.05VS

+1.05VS

+1.05VS

+3VS

+VCCP

+1.8VS

+VCCPNAND

+3VS

+1.8VS

+3VS

+3V_PCH

+VCCP_VCCDMI

+1.05VS

+1.05VS

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

18 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (6/8) PWR

3.3

1.05

1.05

1.05

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

Voltage Rail

VccCore

VccDMI

1.05

5

3.3

0.001

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

5

Voltage

S0 Iccmax

Current (A)

1.05

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

VccALVDS 3.3

1.8VccTX_LVDS 0.06

0.001

0.02

PCH Power Rail Table

Place CH53 Near BG6 pin

Place CH40 Near BJ22 pin

Near AP43

0.1uH inductor, 200mA

1mA

1300mA

2925mA

20mA

190mA

20mA

1mA

60mA

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

RH187 0_0603_5%

@12

RH243

0_0603_5%

@

12

CH36

1U_0402_6.3V6K

1

2

CH44

1U_0402_6.3V6K

1

2

CH38

1U_0402_6.3V6K

1

2

JP1

PAD-OPEN 4x4m

@

12

CH39

0.01U_0402_16V7K

1

2

CH49

1U_0402_6.3V6K

1

2

RH193 0_0805_5%

1 2

CH33

0.1U_0402_10V7K~D

1

2

RH185 0_0805_5%

1 2

CH35

10U_0805_4VAM~D

1

2

RH194 0_0603_5%

@12

RH197

0_0603_5%

12

CH45

10U_0805_4VAM~D

1

2

LH2

0.1UH_MLF1608DR10KT_10%_1608

12

CH52

0.1U_0402_10V7K~D

1

2

RH195

0_0805_5%

1 2

RH189

0_0805_5%

12

CH34

10U_0805_4VAM~D

1

2

CH48

1U_0402_6.3V6K

1

2

CH47

1U_0402_6.3V6K

1

2

CH42

10U_0805_4VAM~D

@

1

2

CH100

1U_0402_6.3V6K

1

2

CH43

0.1U_0402_10V7K~D

1

2

RH191

0_0805_5%

1 2

CH50

1U_0402_6.3V6K

1

2

CH37

1U_0402_6.3V6K

1

2

CH46

1U_0402_6.3V6K

1

2

LH3

1UH_LB2012T1R0M_20%~D

@

1 2

POWER

VCC CORE

DMI

VCCIO

CRTLVDS

FDI

DFT / SPI HVCMOS

UH1G

BD82HM77 QPRG C1 BGA 989P PCH

VCCCORE[1]

AA23

VCCCORE[2]

AC23

VCCCORE[3]

AD21

VCCCORE[4]

AD23

VCCCORE[5]

AF21

VCCCORE[6]

AF23

VCCCORE[7]

AG21

VCCCORE[8]

AG23

VCCCORE[9]

AG24

VCCCORE[10]

AG26

VCCCORE[11]

AG27

VCCCORE[12]

AG29

VCCCORE[13]

AJ23

VCCCORE[14]

AJ26

VCCCORE[15]

AJ27

VCCDFTERM[4] AJ17

VCCDFTERM[3] AJ16

VCCIO[17]

AN21

VCCIO[18]

AN26

VCCIO[19]

AN27

VCCIO[20]

AP21

VCCIO[23]

AP26

VCCIO[24]

AT24

VCCIO[15]

AN16

VCCIO[16]

AN17

VCCIO[21]

AP23

VCCIO[22]

AP24

VCCADAC U48

VCCTX_LVDS[1] AM37

VCCTX_LVDS[2] AM38

VCCALVDS AK36

VCCVRM[3] AT16

VCCVRM[2]

AP16

VCCAPLLEXP

BJ22

VccAFDIPLL

BG6

VCCIO[28]

AN19 VCCTX_LVDS[4] AP37

VCCTX_LVDS[3] AP36

VSSADAC U47

VSSALVDS AK37

VCCIO[27]

AP17

VCC3_3[6] V33

VCC3_3[7] V34

VCC3_3[3]

BH29 VCCDFTERM[2] AG17

VCCDFTERM[1] AG16

VCCDMI[1] AT20

VCCIO[25]

AN33

VCCIO[26]

AN34

VCCCORE[16]

AJ29

VCCCORE[17]

AJ31

VCCSPI V1

VCCCLKDMI AB36

VCCDMI[2]

AU20

CH53

1U_0402_6.3V6K

@

1

2

RH188

0_0805_5%

1 2

LH1

4.7UH_LQM18FN4R7M00D_20%

12

RH190

0_0805_5%

1 2

CH54

1U_0402_6.3V6K

1

2

CH32

0.01U_0402_16V7K

1

2

RH186 0_0603_5%

12

CH40

0.01U_0402_16V7K

1

2

RH192

0_0805_5%

12

RH196

0_0805_5%

1 2

CH41

22U_0805_6.3V6M

1

2

CH51

0.1U_0402_10V7K~D

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+PCH_V5REF_RUN

+PCH_V5REF_SUS

+VCCA_DPLL_L

+1.05VS_VCCA_A_DPL

+1.05VS_VCCUSBCORE

+PCH_V5REF_RUN

+1.05VS_VCC_SATA

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS

+VCCA_USBSUS

+3VS_VCCPPCI

+3V_VCCPUSB

+3V_VCCAUBG

+VCCSATAPLL_R

+3V_VCCPSUS_1

+VCCAFDI_VRM

+3VS_VCCPCORE

+1.05VS_SATA3

+1.05VM_VCCASW

+VCCPDSW

+PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCDPLL_CPY

+VCCAPLL_CPY +3VS_VCC_CLKF33

+VCCSUS1

+VCCACLK

+VCCAPLL_CPY_PCH

+VCCRTCEXT

+VCCSST

+1.05VM_VCCSUS

+V_CPU_IO

+VCCAFDI_VRM

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

+VCCDIFFCLK

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+1.05VS_VCCAUPLL

+VCCSUSHDA

+VCC3_3_2

+1.05VM_VCCSUS

+VCCSATAPLL

+1.05VS_VCCA_B_DPL

PCH_PWR_EN#<27>

+3VS+5VS

+3V_PCH+5V_PCH

+1.05VS

+1.05VS

+3V_PCH

+3V_PCH

+1.05VS

+3VS

+3VS

+1.05VS

+3V_PCH

+1.05VS

+1.05VS

+3V_PCH

+3VS

+3V_PCH

+1.05VS

+1.05VS

+3V_PCH

+3VS

+1.05VS

+1.05VS

+1.05VS

+VCCP

+RTCVCC

+1.05VS

+VCCAFDI_VRM

+5V_PCH+5VALW

+1.05VS

+1.05VS

+1.05VS

+1.05VS_SATA3

+1.05VS_VCC_SATA

+1.05VS_VCCDIFFCLKN

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

19 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (7/8) PWR

If it support 3.3V audio signals

POP:RH244

Depop RH245 / RH246

If it support 1.5V audio signals

POP:RH245 / RH246

Depop R244

1mA

1mA

1mA

119mA

80mA

80mA

VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec

1010mA

3mA

10mA

95mA

55mA

RH223 0_0603_5%

12

RH227 0_0603_5%

1 2

LH4

10UH_LBR2012T100M_20%

@

1 2

CH67

0.1U_0402_10V7K~D

1

2

CH80

1U_0402_6.3V6K

1

2

CH76

0.1U_0402_10V7K~D

1

2

RH229 0_0603_5%

12

CH90

0.1U_0402_10V7K~D

1

2

CH59

10U_0805_10V6K

@1

2

CH87

4.7U_0603_6.3V6K

1

2

CH65

22U_0805_6.3V6M

1

2

CH73

0.1U_0402_10V7K~D

1

2

RH201

0_0603_5%

12

CH82

1U_0402_6.3V6K

1

2

RH208

100_0402_1%

12

CH64

0.1U_0603_25V7K

1

2

CH75

1U_0402_6.3V6K

1

2

RH204

0_0805_5%

@

1 2

CH83

1U_0402_6.3V6K

1

2

RH213

0_0603_5%

12

CH57

0.1U_0402_10V7K~D

1

2

CH63

1U_0402_6.3V6K

@

1

2

RH212

100_0402_1%

12

CH55

0.1U_0402_10V7K~D

1

2

RH206 0_0603_5%

12

CH56

1U_0402_6.3V6K

1

2

+

CH94

220U_B2_2.5VM_R35M~D

1

2

DH3

RB751S40T1_SOD523-2~D

21

CH81

10U_0805_10V6K

@

1

2

RH214 0_0805_5%

12

RH199 0_0603_5%

1 2

RH232

0_0805_5%

1 2

LH6

10UH_LBR2012T100M_20%

@

1 2

G

D

S

QH5

AO3419L_SOT23-3

2

13

CH84

1U_0402_6.3V6K

1

2

CH97

1U_0402_6.3V6K

1

2

CH61

0.1U_0402_10V7K~D

1

2

RH207 0_0603_5%

1 2

LH5

10UH_LBR2012T100M_20%

@

1 2

RH217

0_0603_5%

12

RH203

20K_0402_5%

12

CH88

0.1U_0402_10V7K~D

1

2

LH8

10UH_LBR2012T100M_20%

1 2

RH220 0_0603_5%

12

RH211 0_0805_5%

1 2

CH70

1U_0402_6.3V6K

1

2

CH71

1U_0402_6.3V6K

1

2

CH62

1U_0402_6.3V6K

@

1

2

POWER

SATA USB

Clock and Miscellaneous

HDA

CPURTC

PCI/GPIO/LPCMISC

UH1J

BD82HM77 QPRG C1 BGA 989P PCH

DCPSUSBYP

V12

VCCASW[1]

AA19

VCCASW[2]

AA21

VCCASW[3]

AA24

VCCASW[5]

AA27

VCCASW[6]

AA29

VCCSUSHDA P32

VCCSUS3_3[6] P24

VCCIO[34] T26

VCCIO[4] AD17

VCCASW[7]

AA31

VCCASW[8]

AC26

VCCASW[9]

AC27

VCCASW[10]

AC29

VCCASW[11]

AC31

VCCASW[12]

AD29

V5REF P34

VCC3_3[4] T34

VCCRTC

A22

VCCSUS3_3[10] V24

VCCSUS3_3[9] V23

VCCSUS3_3[8] T24

VCCSUS3_3[7] T23

VCCIO[2] AC16

VCCADPLLB

BF47

VCCDIFFCLKN[1]

AF33

V5REF_SUS M26

VCCIO[3] AC17

DCPSUS[1]

T17

VCCSSC

AG33

VCCADPLLA

BD47

VCCVRM[4]

Y49

VCCACLK

AD49

DCPRTC

N16

VCCASW[4]

AA26

VCCDIFFCLKN[2]

AF34

VCCIO[7]

AF17

DCPSST

V16

VCCIO[5] AF13

VCCASW[22] T21

VCCASW[23] V21

VCCASW[21] T19

VCC3_3[1] AA16

VCC3_3[8] W16

VCCSUS3_3[2] N20

VCCSUS3_3[3] N22

VCCSUS3_3[4] P20

VCCSUS3_3[5] P22

VCCIO[29] N26

VCCIO[30] P26

VCCIO[31] P28

VCCIO[32] T27

V_PROC_IO

BJ8

VCCIO[33] T29

VCCDIFFCLKN[3]

AG34

VCCASW[13]

AD31

VCCASW[14]

W21

VCCASW[15]

W23

VCCASW[16]

W24

VCCASW[17]

W26

VCCASW[18]

W29

VCCASW[19]

W31

VCCASW[20]

W33

VCCIO[6] AF14

VCCVRM[1] AF11

VCCIO[12] AH13

VCCIO[13] AH14

VCC3_3[2] AJ2

VCCAPLLSATA AK1

DCPSUS[3]

AL24

VCCIO[14]

AL29

DCPSUS[4] AN23

VCCSUS3_3[1] AN24

VCCAPLLDMI2

BH23

DCPSUS[2]

V19

VCCDSW3_3

T16

VCC3_3[5]

T38

RH218

0_0805_5%

12

CH58

0.1U_0402_10V7K~D

@

1

2

CH66

22U_0805_6.3V6M

1

2

CH77

0.1U_0402_10V7K~D

1

2

RH205 0_0603_5%

12

CH96

1U_0402_6.3V6K

1

2

CH68

1U_0402_6.3V6K

1

2

CH89

0.1U_0402_10V7K~D

1

2

CH91

0.1U_0402_10V7K~D

1

2

RH231

150_0402_1%

@

12

RH216 0_0603_5%

12

CH79

0.1U_0402_10V7K~D

1

2

CH69

1U_0402_6.3V6K

1

2

RH200 0_0603_5%

12

CH74

10U_0805_10V6K

1

2

RH221

0_0805_5%

@

12

LH7

10UH_LBR2012T100M_20%

1 2

+

CH95

220U_B2_2.5VM_R35M~D

1

2

RH210 0_0603_5%

12

RH224 0_0603_5%

12

RH198 0_0603_5%

@12

RH219 0_0603_5%

@12

CH85

0.1U_0402_10V7K~D

1

2

CH72

1U_0603_10V6K

1

2

RH2150_0805_5%

1 2

CH930.1U_0402_10V7K~D

1

2

CH86

1U_0402_6.3V6K

@

1

2

CH92

1U_0402_6.3V6K

1

2

CH78

1U_0402_6.3V6K

1

2

RH222

0_0805_5%

12

DH2

RB751S40T1_SOD523-2~D

21

CH60

0.1U_0402_10V7K~D

1

2

RH209 0_0603_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

20 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PCH (8/8) VSS

UH1H

BD82HM77 QPRG C1 BGA 989P PCH

VSS[1]

AA17

VSS[2]

AA2

VSS[3]

AA3

VSS[5]

AA34

VSS[6]

AB11

VSS[7]

AB14

VSS[8]

AB39

VSS[9]

AB4

VSS[10]

AB43

VSS[11]

AB5

VSS[12]

AB7

VSS[13]

AC19

VSS[14]

AC2

VSS[15]

AC21

VSS[16]

AC24

VSS[17]

AC33

VSS[18]

AC34

VSS[19]

AC48

VSS[20]

AD10

VSS[21]

AD11

VSS[22]

AD12

VSS[23]

AD13

VSS[24]

AD19

VSS[25]

AD24

VSS[26]

AD26

VSS[27]

AD27

VSS[28]

AD33

VSS[29]

AD34

VSS[30]

AD36

VSS[31]

AD37

VSS[33]

AD39

VSS[34]

AD4

VSS[35]

AD40

VSS[36]

AD42

VSS[37]

AD43

VSS[38]

AD45

VSS[39]

AD46

VSS[43]

AF10

VSS[44]

AF12

VSS[46]

AD16

VSS[47]

AF16

VSS[48]

AF19

VSS[49]

AF24

VSS[50]

AF26

VSS[51]

AF27

VSS[52]

AF29

VSS[53]

AF31

VSS[54]

AF38

VSS[55]

AF4

VSS[56]

AF42

VSS[57]

AF46

VSS[59]

AF7

VSS[60]

AF8

VSS[61]

AG19

VSS[62]

AG2

VSS[63]

AG31

VSS[64]

AG48

VSS[65]

AH11

VSS[66]

AH3

VSS[67]

AH36

VSS[68]

AH39

VSS[69]

AH40

VSS[70]

AH42

VSS[71]

AH46

VSS[72]

AH7

VSS[73]

AJ19

VSS[76]

AJ33

VSS[77]

AJ34

VSS[78]

AK12

VSS[79]

AK3

VSS[80] AK38

VSS[81] AK4

VSS[82] AK42

VSS[83] AK46

VSS[84] AK8

VSS[85] AL16

VSS[86] AL17

VSS[87] AL19

VSS[88] AL2

VSS[89] AL21

VSS[90] AL23

VSS[91] AL26

VSS[92] AL27

VSS[93] AL31

VSS[96] AL48

VSS[97] AM11

VSS[98] AM14

VSS[99] AM36

VSS[100] AM39

VSS[102] AM45

VSS[103] AM46

VSS[104] AM7

VSS[105] AN2

VSS[106] AN29

VSS[107] AN3

VSS[108] AN31

VSS[109] AP12

VSS[110] AP19

VSS[111] AP28

VSS[112] AP30

VSS[113] AP32

VSS[114] AP38

VSS[116] AP42

VSS[117] AP46

VSS[118] AP8

VSS[119] AR2

VSS[120] AR48

VSS[121] AT11

VSS[122] AT13

VSS[123] AT18

VSS[124] AT22

VSS[125] AT26

VSS[126] AT28

VSS[127] AT30

VSS[128] AT32

VSS[131] AT42

VSS[132] AT46

VSS[133] AT7

VSS[134] AU24

VSS[135] AU30

VSS[136] AV16

VSS[137] AV20

VSS[138] AV24

VSS[139] AV30

VSS[140] AV38

VSS[141] AV4

VSS[142] AV43

VSS[143] AV8

VSS[144] AW14

VSS[145] AW18

VSS[146] AW2

VSS[147] AW22

VSS[148] AW26

VSS[149] AW28

VSS[150] AW32

VSS[151] AW34

VSS[152] AW36

VSS[153] AW40

VSS[154] AW48

VSS[155] AV11

VSS[156] AY12

VSS[157] AY22

VSS[158] AY28

VSS[40]

AD8

VSS[42]

AE3

VSS[45]

AD14

VSS[115] AP4

VSS[0]

H5

VSS[58]

AF5

VSS[32]

AD38

VSS[4]

AA33

VSS[74]

AJ21

VSS[75]

AJ24

VSS[41]

AE2

VSS[129] AT34

VSS[130] AT39

VSS[101] AM43

VSS[95] AL34

VSS[94] AL33

UH1I

BD82HM77 QPRG C1 BGA 989P PCH

VSS[159]

AY4

VSS[160]

AY42

VSS[161]

AY46

VSS[162]

AY8

VSS[163]

B11

VSS[164]

B15

VSS[165]

B19

VSS[166]

B23

VSS[167]

B27

VSS[168]

B31

VSS[169]

B35

VSS[170]

B39

VSS[171]

B7

VSS[173]

BB12

VSS[174]

BB16

VSS[175]

BB20

VSS[176]

BB22

VSS[177]

BB24

VSS[178]

BB28

VSS[179]

BB30

VSS[180]

BB38

VSS[181]

BB4

VSS[182]

BB46

VSS[183]

BC14

VSS[184]

BC18

VSS[185]

BC2

VSS[186]

BC22

VSS[187]

BC26

VSS[188]

BC32

VSS[189]

BC34

VSS[190]

BC36

VSS[191]

BC40

VSS[192]

BC42

VSS[193]

BC48

VSS[194]

BD46

VSS[195]

BD5

VSS[196]

BE22

VSS[197]

BE26

VSS[198]

BE40

VSS[199]

BF10

VSS[200]

BF12

VSS[201]

BF16

VSS[202]

BF20

VSS[203]

BF22

VSS[204]

BF24

VSS[205]

BF26

VSS[206]

BF28

VSS[207]

BD3

VSS[208]

BF30

VSS[209]

BF38

VSS[210]

BF40

VSS[211]

BF8

VSS[212]

BG17

VSS[213]

BG21

VSS[214]

BG33

VSS[215]

BG44

VSS[216]

BG8

VSS[217]

BH11

VSS[218]

BH15

VSS[219]

BH17

VSS[220]

BH19

VSS[222]

BH27

VSS[223]

BH31

VSS[224]

BH33

VSS[225]

BH35

VSS[226]

BH39

VSS[227]

BH43

VSS[228]

BH7

VSS[229]

D3

VSS[230]

D12

VSS[231]

D16

VSS[232]

D18

VSS[233]

D22

VSS[234]

D24

VSS[235]

D26

VSS[236]

D30

VSS[237]

D32

VSS[264] K7

VSS[265] L18

VSS[266] L2

VSS[267] L20

VSS[268] L26

VSS[269] L28

VSS[270] L36

VSS[271] L48

VSS[272] M12

VSS[273] P16

VSS[274] M18

VSS[275] M22

VSS[276] M24

VSS[277] M30

VSS[278] M32

VSS[279] M34

VSS[280] M38

VSS[281] M4

VSS[282] M42

VSS[283] M46

VSS[284] M8

VSS[285] N18

VSS[286] P30

VSS[288] P11

VSS[289] P18

VSS[290] T33

VSS[291] P40

VSS[292] P43

VSS[293] P47

VSS[294] P7

VSS[295] R2

VSS[296] R48

VSS[297] T12

VSS[298] T31

VSS[299] T37

VSS[300] T4

VSS[301] W34

VSS[302] T46

VSS[303] T47

VSS[304] T8

VSS[305] V11

VSS[306] V17

VSS[307] V26

VSS[308] V27

VSS[309] V29

VSS[310] V31

VSS[311] V36

VSS[312] V39

VSS[313] V43

VSS[314] V7

VSS[315] W17

VSS[316] W19

VSS[238]

D34

VSS[239]

D38

VSS[240]

D42

VSS[241]

D8

VSS[242]

E18

VSS[243]

E26

VSS[244]

G18

VSS[245]

G20

VSS[246]

G26

VSS[247]

G28

VSS[248]

G36

VSS[249]

G48

VSS[250]

H12

VSS[251]

H18

VSS[317] W2

VSS[318] W27

VSS[319] W48

VSS[320] Y12

VSS[321] Y38

VSS[322] Y4

VSS[323] Y42

VSS[324] Y46

VSS[325] Y8

VSS[328] BG29

VSS[329] N24

VSS[330] AJ3

VSS[287] N47

VSS[252]

H22

VSS[253]

H24

VSS[254]

H26

VSS[255]

H30

VSS[256]

H32

VSS[257]

H34

VSS[258]

F3

VSS[262] K39

VSS[263] K46

VSS[259] H46

VSS[260] K18

VSS[261] K26

VSS[331] AD47

VSS[333] B43

VSS[334] BE10

VSS[335] BG41

VSS[337] G14

VSS[338] H16

VSS[340] T36

VSS[342] BG22

VSS[343] BG24

VSS[344] C22

VSS[345] AP13

VSS[172]

F45

VSS[221]

H10

VSS[346] M14

VSS[347] AP3

VSS[348] AP1

VSS[349] BE16

VSS[350] BC16

VSS[351] BG28

VSS[352] BJ28

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

D_CRT_HSYNC HSYNC_LCRT_HSYNC

CRT_VSYNC

CRT_R_L

D_CRT_VSYNC

CRT_R_C

CRT_G_C

CRT_B_L

CRT_R_L

HSYNC_L

CRT_DDC_DATA_C

CRT_DDC_CLK_C

CRT_G_L

CRT_G_L

VSYNC_L

CRT_B_L

CRT_DDC_CLK_C

CRT_DDC_DATA_C

VSYNC_L

CRT_B_C

CRT_HSYNCVGA_CRT_HSYNC

CRT_R

CRT_VSYNC

VGA_CRT_R

VGA_CRT_VSYNC

CRT_G

CRT_DDC_CLK

VGA_CRT_G

VGA_CRT_CLK

CRT_B

CRT_DDC_DATA

VGA_CRT_B

VGA_CRT_DATA

CRT_R<15>

CRT_G<15>

CRT_B<15>

CRT_DDC_DATA<15>

CRT_DDC_CLK<15>

CRT_HSYNC<15>

CRT_VSYNC<15>

CRT_DET#<17>

VGA_CRT_G<35>

VGA_CRT_R<35>

VGA_CRT_CLK<35>

VGA_CRT_DATA<35>

VGA_CRT_VSYNC<35>

VGA_CRT_HSYNC<35>

VGA_CRT_B<35>

+3VS +CRT_VCC+3VS +CRT_VCC+3VS

+CRT_VCC

+CRT_VCC

+5VS +CRT_VCC+R_CRT_VCC

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

21 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

VGA / LVDS /camera conn.

C R T

For EMI

W=40mils

W=40mils

From VGA

for debug CRT

For EMI

CV11

10P_0402_50V8J

12

RV4

150_0402_1%

@

12

DV1

PESD5V0U2BT_SOT23-3

@

2

3

1

RV225 0_0402_5%@

1 2

RV228 0_0402_5%@

1 2

CV6

150_0402_1%

12

RV5

150_0402_1%

@

12

G

D

S

QV2

2N7002BKW_SOT323-3

2

13

CV1

0.1U_0402_16V7K

1

2

RV8

2.2K_0402_5%

1 2

RV226 0_0402_5%@

1 2

CV16

0.1U_0402_16V7K

1 2

RV11

0_0603_5%

1 2

RV10

0_0603_5%

1 2

CV12

100P_0402_50V8J

1

2

CV3

22P_0402_50V8J

12

LV5 0_0603

1 2

RV1

100K_0402_5%

12

UV27

74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

RV229 0_0402_5%@

1 2

G

D

S

QV1

2N7002BKW_SOT323-3

2

13

CV10

10P_0402_50V8J

12

LV1 0_0603

1 2

CV15

10P_0402_50V8J

12

LV6 LQW18AN47NG00D _0603

1 2

FV2

1.1A_6VDC_FUSE

21

LV4 LQW18AN47NG00D _0603

1 2

NC

DV4

BAT1000-7-F_SOT23-3~D

2 1

3

RV9

2.2K_0402_5%

1 2

CV13

0.1U_0402_16V7K

1 2

CV7

150_0402_1%

12

T65PAD~D @

G

G

JCRT

SUYIN_070546HR015M22BZR

CONN@

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

16

17

RV7

2.2K_0402_5%

1 2

UV26

74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

RV223 0_0402_5%@

1 2

RV2

0_1206_5%

@

12

DV2

PESD5V0U2BT_SOT23-3

@

2

3

1

LV2 LQW18AN47NG00D _0603

1 2

LV3 0_0603

1 2

RV227 0_0402_5%@

1 2

CV8

150_0402_1%

12

RV3

150_0402_1%

@

12

RV6

2.2K_0402_5%

1 2

CV9

10P_0402_50V8J

12

RV12

10K_0402_5%

1 2

RV224 0_0402_5%@

1 2

CV4

22P_0402_50V8J

12

CV14

10P_0402_50V8J

12

CV5

22P_0402_50V8J

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+LCDVDD_R

PCH_ENVDD

EC_ENVDD

PWR_SRC_ON

+INV_PWR_SRC_R

MIC_CLK

USB20_P12_RMIC_CLK_R

USB20_N12_RMIC_DATA

BKOFF#

LVDS_BCLK-

LVDS_BCLK+

+LCDVDD_R

MIC_DATA

LVDS_B1+

LVDS_A1-

LVDS_B1-

USB20_N12_R

LVDS_A2+

EDID_CLK_LCD

LVDS_ACLK-

LVDS_B0-

DISPOFF#

USB20_P12_R

LVDS_A0-

MIC_CLK_R

LVDS_A1+

INV_PWM

MIC_CLK_R

+LCDVDD

LVDS_BCLK-

LVDS_B2-

LVDS_A0+

DISPOFF#

LCD_TEST

INV_PWM

LVDS_BCLK+

LVDS_B2+

LVDS_A2-

LVDS_ACLK+

LVDS_B0+

USB20_N12_R

USB20_P12_R

EDID_DATA_LCD

BKOFF#<24>

VGA_PWM<15>

PCH_ENVDD<15>

EC_ENVDD<24>

LVDS_B0+<15>

LVDS_B0-<15>

LVDS_A2+<15>

LVDS_A0+<15>

LVDS_A2-<15>

LVDS_ACLK+<15>

LVDS_DDC_CLK<15>

LVDS_A0-<15>

LVDS_A1+<15>

LVDS_A1-<15>

LVDS_DDC_DATA<15>

LVDS_ACLK-<15>

LVDS_BCLK+<15>

LVDS_BCLK-<15>

LVDS_B2+<15>

LVDS_B2-<15>

LVDS_B1+<15>

LVDS_B1-<15>

USB20_N12<16>

USB20_P12<16>

MIC_DATA<30>

MIC_CLK<30>

LCD_TEST<24>

EN_INVPWR<24>

CMOS_ON#<24>

+5VALW

+INV_PWR_SRC

+3VS

+LCDVDD

B+

+INV_PWR_SRC

B+ +INV_PWR_SRC

+LCDVDD

+LCDVDD +5VALW

+3VS

+INV_PWR_SRC

+3VS_CAM

+3VS

+LCDVDD

+5VS

+3VS_CAM+3VS +3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

22 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LVDS /camera conn.

LVDS Conn.

Wedcam PWR CTRL

W=60mils

W=60mils

60mil

60mil

* Reserved for EMI/ESD/RF

need to close to JLVDS

W=60mils

W=60mils

* Reserved for LCD

sequence tuning

LCD backlight PWR CTRL

LCD PWR CTRL

RV210 0_0402_5%

1 2

CV25

1000P_0402_50V7K

1

2

G

D

S

QV5

BSS138_SOT23~D

2

13

RV25

100K_0402_5%

12

RV26

100K_0402_5%

12

G

D

S

QV3

SSM3K7002FU_SC70-3~D

2

13

RV34

100K_0402_5% @

12

G

D

S

QV8

SI2301CDS-T1-GE3_SOT23-3

@

2

13

RV14

100_0402_1%

1 2

CV28

5P_0402_50V8C

@

1 2

CV319

1000P_0402_50V7K

@

1

2

RV28

0_0402_5%

12

RV230

100K_0402_5%

12

JLVDS

STARC_107K40-000001-G2

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

G1 41

G2 42

G3 43

G4 44

G5 45

G6 46

RV16

10K_0402_5%

12

QV9A

2N7002DW-7-F_SOT363-6

@

61

2

CV21

0.1U_0402_16V7K

1

2

RV31

0_0402_5%

@

12

CV29

470P_0402_50V7K~D

@

1

2

RV32

820_0805_1%

@

12

RV18

10K_0402_5%

12

QV9B

2N7002DW-7-F_SOT363-6

@

3

5

4

DV6

CH751H-40PT_SOD323-2~D

2 1

RV30

0_0402_5%

12

CV31

0.1U_0402_16V7K @

1

2

RV13

4.7K_0402_5%

@

12

RV20 0_0402_1%

@

12

RV15

47K_0402_5%

1 2

RV33

100K_0402_5%

@

12

DV7

BAT54C-7-F_SOT23-3

2

3

1

S

G

D

QV6

SI3457CDV-T1-E3_TSOP6~D

3

6

2

4 5

1

CV30

680P_0402_50V7K~D

@

1

2

CV26

0.1U_0603_50V_X7R

1

2

DV8

IP4223CZ6_SO6-6

V I/O 1

V I/O 3

V I/O

6

V I/O

4

Ground 2

V BUS

5

CV22

0.1U_0402_16V7K

1

2

RV231 0_0603_5%

12

CV19

0.1U_0402_16V7K

1

2

CV18

5P_0402_50V8C @

1 2

G

D

S

QV7

SSM3K7002FU_SC70-3~D

2

13

G

D

S

QV4

AO3419L_SOT23-3

4.14

2

1 3

DV5

CH751H-40PT_SOD323-2~D

@

21

CV23

0.1U_0402_16V7K

1

2

RV29

0_0402_5%

12

RV27 0_0805_5%

@

1 2

CV20

4.7U_0805_10V4Z

1

2

RV208 0_0402_5%

1 2

CV27

5P_0402_50V8C

@

1 2

RV19 0_0402_1%

@

12

LV24

DLW21SN900HQ2L_0805_4P~D

@

1

122

33

4

4

RV17

56K_0402_5%

12

RV24 0_0805_5%

1 2

CV24

10U_0805_10V6K

1

2

RV209

47K_0402_5%

@

12

CV17

5P_0402_50V8C

@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TMDS_TXCP

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TXCP

TMDS_L_TXCN

TMDS_L_TX2N

TMDS_L_TX2P

TMDS_TXCN

TMDS_TX1P

TMDS_TX1N

TMDS_TX0P

TMDS_TX0N TMDS_L_TX0N

TMDS_TX2P

TMDS_TX2N

DDC_DAT_HDMI

DDC_CLK_HDMI

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX0P

TMDS_L_TX2N

TMDS_L_TX2P

TMDS_L_TX0N

TMDS_L_TXCN

TMDS_L_TXCP

HDMI_HPLUG

DDC_DAT_HDMI

DDC_CLK_HDMI +5V_HDMI_DDC

TMDS_TX1N

TMDS_TX2P

TMDS_TX2N

TMDS_TX0P

TMDS_TX1P

TMDS_TXCP

TMDS_TX0N

TMDS_TXCN

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX0P

TMDS_L_TX2N

TMDS_L_TX2P

TMDS_L_TX0N

TMDS_L_TXCN

TMDS_L_TXCP

HDMI_HPLUG

TMDS_TX2P

TMDS_TX2N

TMDS_TX0P

TMDS_TX1P

TMDS_TX1N

TMDS_TXCP

TMDS_TXCN

TMDS_TX0N

HDMI_A3N_VGA<15>

HDMI_A3P_VGA<15>

HDMI_A2N_VGA<15>

HDMI_A2P_VGA<15>

HDMI_A1P_VGA<15>

HDMI_A1N_VGA<15>

HDMI_A0P_VGA<15>

HDMI_A0N_VGA<15>

PCH_SDVO_CTRLCLK<15>

PCH_SDVO_CTRLDATA<15>

HDMI_DET<15>

+VDISPLAY_VCC

+3VS

+3VS

+5VS

+3VS

+3VS

+3VS

+5VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

HDMI

Custom

23 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

W=40mils

Place close to JHDMI1

20110805 EMI ADD20111024 EMI ADD

CV41 0.1U_0402_10V7K~D

12

RV36 0_1206_5%

12

CV42

220P_0402_50V8J

1

2

Part Number Description

RO0000002HM HDMI W/Logo:RO0000002HM

ROYALTY HDMI W/LOGO46@

CV358 100P_0402_50V8J@1 2

RV54 0_0402_5%@

1 2

RV46 680_0402_1%

12

CV33 0.1U_0402_10V7K~D

12

CV354 3.3P_0402_50V8C~D

1 2

CV363 100P_0402_50V8J@1 2

LV7

WCM-2012HS-900T_4P

1

122

33

4

4

RV59

200K_0402_5%

@

1 2

RV51

0_0402_1%

@

1 2

CV350 3.3P_0402_50V8C~D

1 2

NC

DV9

BAT1000-7-F_SOT23-3~D

@

2 1

3

RV43 680_0402_1%

12

RV38 0_0402_5%@

1 2

G

D

S

QV11

2N7002_SOT23

2

13

CV359 100P_0402_50V8J@1 2

RV60 2.2K_0402_5%

1 2

QV12B

DMN66D0LDW-7_SOT363-6

3

5

4

RV44 680_0402_1%

12

CV37 0.1U_0402_10V7K~D

12

CV364 100P_0402_50V8J@1 2

CV355 3.3P_0402_50V8C~D

1 2

RV40 0_0402_5%

@

1 2

CV32 0.1U_0402_10V7K~D

12

RV45 680_0402_1%

12

CV349 3.3P_0402_50V8C~D

1 2

CV351 3.3P_0402_50V8C~D

1 2

RV42 680_0402_1%

12

RV47 680_0402_1%

12

RV49 680_0402_1%

12

CV39 0.1U_0402_10V7K~D

12

JHDMI

ACON_HMR2U-AK120C

CONN@

D2+

1D2_shield

2D2-

3D1+

4D1_shield

5D1-

6D0+

7D0_shield

8D0-

9CK+

10 CK_shield

11 CK-

12 CEC

13 Reserved

14 SCL

15 SDA

16 DDC/CEC_GND

17 +5V

18 HP_DET

19

GND 20

GND 21

GND 22

GND 23

RV53

100K_0402_5%

12

CV360 100P_0402_50V8J@1 2

LV10

WCM-2012HS-900T_4P

1

122

33

4

4

E

B

C

QV13

MMBT3904_NL_SOT23-3

2

3 1

LV8

WCM-2012HS-900T_4P

1

122

33

4

4

CV356 3.3P_0402_50V8C~D

1 2

RV39

10K_0402_5%

12

CV35

10U_0603_6.3V6M

1

2

CV352 3.3P_0402_50V8C~D

1 2

FV1

1.5A_6V_1206L150PR~D

12

RV48 680_0402_1%

12

CV36 0.1U_0402_10V7K~D

12

CV361 100P_0402_50V8J@1 2

RV56

0_0402_1%

@

12

CV34

0.1U_0402_10V7K~D

1

2

RV37 0_0402_5%@

1 2

DV11

BAV99-7-F_SOT23-3

@

2

3

1

RV52 0_0402_5%@

1 2

CV40 0.1U_0402_10V7K~D

12

DV10

RB751V-40GTE-17_SOD323-2~D

@

21

RV55

100K_0402_5%

12

RV35 0_0402_5%@

1 2

CV357 100P_0402_50V8J@1 2

CV353 3.3P_0402_50V8C~D

1 2

RV57

150K_0402_5%

1 2

CV362 100P_0402_50V8J@1 2

RV50 0_0402_5%@

1 2

CV38 0.1U_0402_10V7K~D

12

RV41 0_0402_5%@

1 2

RV58 2.2K_0402_5%

1 2

QV12A

DMN66D0LDW-7_SOT363-6

61

2

LV9

WCM-2012HS-900T_4P

1

122

33

4

4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

KSO[0..16]

KSI[0..7]

ECAGND

ACIN

EC_SMB_DA1_R

EC_SMB_CK1_R

TP_DATA

TP_CLK

EC_CRY1

EC_MUTE#

SYSON

KSI1

KSO9

BKOFF#

KSI7

FAN_SPEED1

LPC_AD1

AD_BID0

KSI3

KSO4

+3VALW_EC

+V18R

EC_RSMRST#

KSO8

KSO2

EC_SMI#

FWR#

VR_ON

SUSP#

KSO16

EN_DFAN1

BATT_TEMP

KSI0

KSO1

SERIRQ

EC_RST#

LPC_AD2

ECAGND

KSO14

KB_RST#

ADP_I

KSI4

EC_SCI#

LPC_AD3

VCOUT0

KSO15

KSO10

KSO0

ACOFF

LPC_AD0

LPC_FRAME#

SPI_CLK

KSO13

EC_CRY2

EC_CRY1

KSI2

KSO11

KSO3

FSEL#

KSI6

BEEP#

+EC_VCCA

EC_MUTE_R

KSO12

PM_SLP_S5#_R

TP_CLK

KSI5

KSO7

EC_TX

BATT_CHG_LED#

TP_DATA

KSO6

KSO5

PM_SLP_S3#_R

EC_RX

FRD#

PECI_KB930

EC_SMI#

EC_SMB_CK2

EC_SMB_DA2

PWR_PWM_LED#

CAPS_LED

BATT_LOW_LED#

LID_SW#

PECI_KB9012

EC_SCI#

SA_PGOOD

EC_CRY2

CPU1.5V_S3_GATE

USB_EN#

EC_MUTE#

EC_LID_OUT#

EC_SMB_DA2

EC_SMB_CK2

PM_SLP_S4#PM_SLP_S4#_R

PCH_HOT#_R PCH_HOT#

PCH_HOT#

VR_HOT#

VCOUT1_PHH_PROCHOT#

PM_SLP_S4#_R

ACIN_D

EC_ON_R

ON/OFF_R

ENBKL

H_PECI

PBTN_OUT#

ECAGND

PCH_PWROK

VCOUT1_PH

EC_SMB_DA1_REC_SMB_DA1

EC_SMB_CK1 EC_SMB_CK1_R

SA_PGOOD

DASH_LED_PWM

EC_PME#

WL_BT_LED#

GATEA20

PCH_PWROK

VCOUT0 PCH_PWROK

ME_EN

PCH_PWR_EN

EC_PME#

AD_BID0

EC_PME#

KB_LED_PWM

DASH_LED2#

TOUCH_LED#

DASH_LED3#

DASH_LED1#

HDD_S3.5

KSO1

KSO2

FRD#

FWR#

SPI_CLK

FSEL#

VCIN0_PHVCIN0_PH_R

WOL_EN#

PECI_KB930

WLAN_WAKE#

USB_DET#_DELAY

USB_DET#_DELAY

CMOS_ON#

VCIN0_PH_R

PCH_HOT#_R

DASH_SW3

DASH_SW1

HDD_S3.5

KSI[0..7]<25>

KSO[0..16]<25>

LPC_FRAME#<13>

LPC_AD2<13>

LPC_AD0<13>

LPC_AD3<13>

LPC_AD1<13>

SERIRQ<13>

TP_CLK <25>

BEEP# <30>

EC_SMI#<17>

KB_RST#<17>

BATT_TEMP <43,44>

FAN_SPEED1<25>

ADP_I <43,44>

TP_DATA <25>

EC_RSMRST# <15>

SYSON <27,28,48>

VR_ON <50>

CLK_PCI_LPC<16>

PCH_SMLDATA<14>

SPI_CLK <26>

FSEL# <26>

FWR# <26>

EN_DFAN1 <25>

BATT_CHG_LED# <32>

FRD# <26>

SUSP# <10,27,28,46,47,48>

EC_SCI#<17>

PLT_RST#<6,16,28,32>

H_PECI <6,17>

CAPS_LED <25>

BATT_LOW_LED# <32>

H_PROCHOT#<6,44>

SUSCLK_R<15>

PM_SLP_S3#<15,28>

PM_SLP_S5#<15> EC_LID_OUT# <17>

PM_SLP_S4# <15>

BKOFF# <22>

PCH_HOT# <14>

VR_HOT#<50>

EC_ON <25,28>

ON/OFF <25>

PCH_SMLCLK<14>

EC_TX<32>

EC_RX<32>

SA_PGOOD <49>

USB_EN# <32,33>

LID_SW# <26,32>

ACIN <15,35,43,44>

PBTN_OUT# <6,15>

VCIN0_PH <43>

VCIN1_PH <43>

EC_MUTE# <30>

EC_SMB_DA1<43,44>

EC_SMB_CK1<43,44>

VCOUT0_PH <45>

ACOFF <44>

ENBKL <15>

DASH_LED_PWM<32>

EC_ENVDD <22>

WL_BT_LED# <32>

PCH_PWROK<6,15>

PWR_PWM_LED# <32>

CPU1.5V_S3_GATE <10>

GATEA20<17>

ME_EN <13>

AOAC_ON<32>

PCH_PWR_EN <27>

PS_ID<43>

65W/90W# <43>

IMVP_IMON <50>

EN_INVPWR <22>

LCD_TEST <22>

EAPD <30,31>

PX_MODE <36,52,53>

PCIE_WAKE#<15,28,32>

PWRSHARE_OE# <33>

KB_LED_PWM <26>

CMOS_ON#<22>

EC_SMB_DA2 <35>

EC_SMB_CK2 <35>

TOUCH_LED#<25>

DASH_LED1# <32>

DASH_LED3# <32>

HDD_S3.5 <29>

PWRSHARE_EN_EC#<33>

DASH_LED2# <32>

DASH_SW3<32>

WOL_EN# <32>

WLAN_WAKE# <32>

USB_DET#_DELAY<28>

VCIN0_PH2 <25>

3S_ON <25>

DASH_SW1<32>

130W/90W#<43>

ACIN_65W <35>

+3VALW

+3VALW

+3VALW

+3VS

+5VS

+3VS

+3VLP

+3VLP

+3VALW

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

EC ENE-KB930/Co-lay 9012

Custom

24 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

20mil

Compal Electronics, Inc.

KB930

KB9012

R4944

R4930

Stuff

Co-lay KB930/KB9012 PECI

Reserved for KB9012

Analog Board ID definition,

Please see page 4.

Ra

Rb

Board ID

reserve for KB9012 Rev.A2

RE29 0_0402_5%

1 2

CE15

0.1U_0402_16V7K

1

2

CE19

47P_0402_50V8J

1

2

RE27 0_0402_5%

1 2

RE22 0_0402_5%

1 2

RE5

100K_0402_5%

VOS@

LPC & MISC

Int. K/B

Matrix

SM Bus

GPIO

GPIO

AD Input

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPO

GPI

UE1

KB9012QF-A3_LQFP128_14X14KB9012@

GATEA20/GPIO00

1

KBRST#/GPIO01

2

SERIRQ

3

LPC_FRAME#

4

LPC_AD3

5

PM_SLP_S3#/GPIO04

6

LPC_AD2

7

LPC_AD1

8

EC_VDD/VCC 9

LPC_AD0

10

GND/GND

11

CLK_PCI_EC

12

PCIRST#/GPIO05

13

PM_SLP_S5#/GPIO07

14

EC_SMI#/GPIO08

15

GPIO0A

16

GPIO0B

17

GPIO0C

18

GPIO0D

19

EC_SCII#/GPIO0E

20

GPIO0F 21

EC_VDD/VCC 22

BEEP#/GPIO10 23

GND/GND

24

EC_INVT_PWM/GPIO11

25

GPIO12 26

ACOFF/GPIO13 27

FAN_SPEED1/GPIO14

28

EC_PME#/GPIO15

29

EC_TX/GPIO16

30

EC_RX/GPIO17

31

PCH_PWROK/GPIO18

32

EC_VDD/VCC 33

SUSP_LED#/GPIO19

34

GND/GND

35

NUM_LED#/GPIO1A

36

EC_RST#

37

GPIO1D

38

KSO0/GPIO20

39

KSO1/GPIO21

40

KSO2/GPIO22

41

KSO3/GPIO23

42

KSO4/GPIO24

43

KSO5/GPIO25

44

KSO6/GPIO26

45

KSO7/GPIO27

46

KSO8/GPIO28

47

KSO9/GPIO29

48

KSO10/GPIO2A

49

KSO11/GPIO2B

50

KSO12/GPIO2C

51

KSO13/GPIO2D

52

KSO14/GPIO2E

53

KSO15/GPIO2F

54

KSI0/GPIO30

55

KSI1/GPIO31

56

KSI2/GPIO32

57

KSI3/GPIO33

58

KSI4/GPIO34

59

KSI5/GPIO35

60

KSI6/GPIO36

61

KSI7/GPIO37

62

BATT_TEMP/GPIO38 63

GPIO39 64

ADP_I/GPIO3A 65

GPIO3B 66

EC_VDD/AVCC 67

DAC_BRIG/GPIO3C 68

AGND/AGND

69

EN_DFAN1/GPIO3D 70

IREF/GPIO3E 71

CHGVADJ/GPIO3F 72

ENBKL/GPIO40 73

PECI_KB930/GPIO41 74

GPIO42 75

IMON/GPIO43 76

EC_SMB_CK1/GPIO44

77

EC_SMB_DA1/GPIO45

78

EC_SMB_CK2/GPIO46

79

EC_SMB_DA2/GPIO47

80

KSO16/GPIO48

81

KSO17/GPIO49

82

EC_MUTE#/GPIO4A 83

USB_EN#/GPIO4B 84

CAP_INT#/GPIO4C 85

EAPD/GPIO4D 86

TP_CLK/GPIO4E 87

TP_DATA/GPIO4F 88

FSTCHG/GPIO50 89

BATT_CHG_LED#/GPIO52 90

CAPS_LED#/GPIO53 91

PWR_LED#/GPIO54 92

BATT_LOW_LED#/GPIO55 93

GND/GND

94

SYSON/GPIO56 95

EC_VDD/VCC 96

CPU1.5V_S3_GATE/GPXIOA00 97

WOL_EN/GPXIOA01 98

ME_EN/GPXIOA02 99

EC_RSMRST#/GPXIOA03 100

EC_LID_OUT#/GPXIOA04 101

PROCHOT_IN/GPXIOA05 102

H_PROCHOT#_EC/GPXIOA06 103

VCOUT0_PH/GPXIOA07 104

BKOFF#/GPXIOA08 105

PBTN_OUT#/GPXIOA09 106

PCH_APWROK/GPXIOA10 107

SA_PGOOD/GPXIOA11 108

VCIN0_PH/GPXIOD00 109

AC_IN/GPXIOD01 110

EC_VDD0 111

EC_ON/GPXIOD02 112

GND0

113

ON/OFF/GPXIOD03 114

LID_SW#/GPXIOD04 115

SUSP#/GPXIOD05 116

GPXIOD06 117

PECI_KB9012/GPXIOD07 118

SPIDI/GPIO5B 119

SPIDO/GPIO5C 120

VR_ON/GPIO57 121

XCLKI/GPIO5D

122

XCLKO/GPIO5E

123 V18R 124

EC_VDD/VCC 125

SPICLK/GPIO58 126

PM_SLP_S4#/GPIO59 127

SPICS#/GPIO5A 128

CE12

22P_0402_50V8J

@1

2

RE16 1K_0402_1%

@

1 2

RE17

0_0402_5% @

12

RE62 47K_0402_5%@

1 2

RE15

0_0402_5% KB9012@

12

RE8 47K_0402_5%

12

RE31 0_0402_5%

1 2

RE1810K_0402_5%

12

RE77 100K_0402_5%

1 2

CE11 0.1U_0402_16V7K

12

LE2

FBMA-L11-160808-800LMT_0603

12

CE4

0.1U_0402_16V7K

1

2

RE94.7K_0402_5%

12

RE80 0_0402_5%

1 2

RE3643_0402_1% 12

CE9 100P_0402_50V8J

12

RE40

0_0402_5%

KB9012@

12

RE70 10K_0402_5%

1 2

CE18 100P_0402_50V8J

12

RE13 2.2K_0402_5%

1 2

CE17 20P_0402_50V8

1 2

CE14

0.1U_0402_16V7K

1 2

RE7 0_0402_5%

@12

RE37 0_0402_5%KB9012@ 12

CE1

0.1U_0402_16V7K

1

2

RE32 10K_0402_5%

@

1 2

RE1

0_0805_5%

1 2

RE12 0_0402_5%

12

RE6 33_0402_5%@

12

RE71 10K_0402_5%@

1 2

RE4

0_0402_5%

KB9012@

12

RE19

0_0402_5%

12

RE33 0_0402_5%

1 2

RE14 0_0402_5%

12

RE78 100K_0402_5%

1 2

RE39 0_0402_5%

1 2

RE25 2.2K_0402_5%

1 2

RE340_0402_5% KB9012@

12

RE72 0_0402_5%

1 2

RE42 0_0402_5%

1 2

CE13

22P_0402_50V8J

@

1

2

CE6

1000P_0402_50V7K

1

2

RE30

47K_0402_5%@

12

RE11 2.2K_0402_5%

1 2

RE65 0_0402_5%

1 2

RE23 43_0402_1%KB930@

1 2

RE45 100K_0402_5%

12

RE2

0_0402_5%

KB930@

1 2

CE16

4.7U_0805_10V4Z

1

2

LE1

FBMA-L11-160808-800LMT_0603

1 2

YE1

32.768KHZ_12.5PF_Q13MC14610002

@

OSC 4

OSC 1

NC

3

NC

2

RE26 0_0402_5%

1 2

CE10

22P_0402_50V8J@

12

RE63 47K_0402_5%@

1 2

RE46 10K_0402_5%

1 2

RE24 2.2K_0402_5%

1 2

CE5

1000P_0402_50V7K

1

2

RE35 10K_0402_5%

@

1 2

RE38 0_0402_5%

KB930@

12

CE2

0.1U_0402_16V7K

1

2

RE43

43_0402_1%KB9012@

1 2

CE8

0.1U_0402_16V7K

1

2

RE67 0_0402_5%

1 2

RE61 0_0402_5%

1 2

RE76

0_0402_5%

12

RE5

56K_0402_5%

INS@

1 2

RE3

100K_0402_5%

1 2

RE44 0_0402_5%

12

RE21 10K_0402_5%

1 2

RE64 0_0402_5%

1 2

CE3

0.1U_0402_16V7K

1

2

RE41 0_0402_5%

1 2

UE2

SN74LVC1G06DCKR_SC70-5

Y

4A2

P5

G

3

NC

1

CE7

0.1U_0402_16V7K

1

2

RE28 0_0402_5%

1 2

RE104.7K_0402_5%

12

RE47

100K_0402_5%

1 2

RE66 0_0402_5%

1 2

RE69 0_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TP_CLK

TP_DATA

KSO[0..16]

KSI[0..7]

EN_DFAN1

ON/OFFBTN#

PWR_LED#

KB_CAPS_PWR

KB_CAPS_PWR-

KSI0

KSI1

KSI4

KSI2

KSI3

KSI5

KSI6

KSI7

KSO16

KSO2

KSO4

KSO3

KSO1

KSO0

KSO8

KSO7

KSO6

KSO5

KSO9

KSO10

KSO13

KSO12

KSO11

KSO14

KSO15

+TPLED

ON/OFFBTN#

TP_CLK<24>

TP_DATA<24>

EC_ON<24,28>

ON/OFF <24>

51_ON# <43>

KSO[0..16]<24>

KSI[0..7]<24>

FAN_SPEED1<24>

EN_DFAN1<24>

PWR_LED#<32>

CAPS_LED<24>

TOUCH_LED#<24>

VCIN0_PH2<24>

3S_ON <24>

DASH_SW2<32>

+3VS

+3VALW

+FAN_POWER

+3VS

+5VS

+FAN_POWER

+3VLP

+5VALW

+5VS+5VS

+3VLP

+3VALW

+3VALW

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

SW/TP/SCREW

Custom

25 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

Touch pad

Power ON Circuit

ON/OFF switch

Pop only for

SSI debug

TOP Side

Bottom Side

INT_KBD Conn.

40mil

40mil FAN Control circuit

To POWER/B

Touch Pad LED

HE1 place around FAN area.

JFAN

ACES_85204-0300N

CONN@

1

1

2

2

3

3

GND

4

GND

5

CE23

1000P_0402_50V7K

1

2

RE60

240_0402_1%

1 2

RE73 390_0402_5%

1 2

A

D2

C191KSKT-5A

VOS@

21

CE20

0.1U_0402_25V6K

1

2

DE5

PESD24VS2UT_SOT23-3~D

2

3

1

RE51

10K_0402_5%

KB930@

1 2

RE20

0_0402_5%

VOS@

12

RE48

100K_0402_5%

KB930@

1 2

SW1

SMT1-05-A_4P

@

3

2

1

4

5

6

RE79

13.7K_0402_1%

1 2

CE25

2.2U_0603_6.3V6K

1 2

UE3

APE8873M SOP 8P

VEN

1

VIN

2

GND 5

GND 6

GND 8

VO

3

VSET

4

GND 7

RE75

100K_0402_5%

1 2

SW2

SMT1-05-A_4P

@

3

2

1

4

5

6

RE50

10K_0402_5%

12

G

D

S

QE1

SSM3K7002F_SC59-3

KB930@

2

13

RE74

13.7K_0402_1%@

1 2

CE22

2.2U_0603_6.3V6K

1

2

R6

390_0402_5%

12

G

D

S

QE3

SSM3K7002FU_SC70-3~D

2

13

HE1

100K_0402_1%_TSM0B104F4251RZ

VOS@

12

DE1

BAV70W_SOT323-3

2

3

1

A

D1

C191KSKT-5A

INS@

21

JPWR

ACES_50504-0040N-001

CONN@

1

1

2

2

G1 5

G2 6

3

3

4

4

JTP

ACES_50504-0040N-001

CONN@

1

1

2

2

G1 5

G2 6

3

3

4

4

RE49

100K_0402_5%

KB9012@

1 2

DE2

BAV70W_SOT323-3

2

3

1

JKB

ACES_51510-03041-001

CONN@

1

1

4

4

2

2

5

5

3

3

8

87

76

6

10

10 9

9

11

11

12

12

13

13

14

14

17

17 16

16

19

19

20

20

15

15

22

22 21

21

18

18

23

23

25

25 24

24

26

26

27

27

28

28

29

29

30

30 GND 31

GND 32

CE24

0.01U_0402_16V7K

1

2

DE3

PESD5V0U2BT_SOT23-3

2

3

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SPI_CLK_R

SPI_CLK_R

FRD# SPI_SO

SPI_FWR#

SPI_FSEL#

KB_BL_PWM

LID_SW#

SPI_CLK <24>

FRD#<24>

FWR# <24>

FSEL#<24>

KB_LED_PWM<24>

LID_SW# <24,32>

KB_DET#<17>

+3VALW

+5VS +5VS_KBL

+5VS_KBL

+3VALW

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

26 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

CONN & LID

Screw Hole

Reserve for EMI please close to U15

SPI ROM 128KB

20mils

20mil

Keyboard back light

20mil

Lid Switch

DA80000R900

JKBL

ACES_50519-00401-001

CONN@

1

1

2

2

GND 5

GND 6

3

3

4

4

H12

H_2P8

@

1

S

G

D

QE2

SI3456BDV-T1-E3 1N TSOP6 W/D

KBBL@

3

6

2

4 5

1

RE68

10K_0402_5%

@

1 2

H23

H_2P8

@

1

H10

H_3P7

@

1

CE53

22P_0402_50V8J

@

1 2

RE56

33_0402_5%

@

12

RE58

100K_0402_5%

KBBL@

12

RE53 0_0402_5%KB930@

12

FD1

FIDUCAL@

1

H8

H_3P7

@

1

RE52 0_0402_5%KB930@

1 2

H1

H_3P3X4P3N

@

1

H4

H_3P5

@

1

RE540_0402_5% KB930@12

CE54

0.1U_0402_16V7K

INS@ 1

2

H21

H_2P8

@

1

H13

H_2P8

@

1

H3

H_3P5

@

1

CE55

0.1U_0402_16V7K

INS@

1

2

H19

H_2P8

@

1

FE1

0.75A_24V_1812L075-24DR~OK

@

12

H11

H_2P8

@

1

CE52

0.1U_0402_16V7K

KB930@

1

2

H24

H_2P8

@

1

FD2

FIDUCIAL@

1

G

D

S

QE4

SSM3K7002FU_SC70-3~D

KBBL@

2

13

H2

H_3P3N

@

1

RE550_0402_5% KB930@

12

RE59

0_0805_5%

KBBL@

1 2

H6

H_3P7

@

1

UE5

S-5712ACDL1-M3T1U_SOT23-3

INS@

GND

1

OUTPUT 3

VDD 2

H7

H_3P7

@

1

ZZZ1

PCB-MB

H9

H_3P7

@

1

RE57

10K_0402_5%

12

H17

H_2P8

@

1

FD3

FIDUCAL@

1

H15

H_2P8

@

1

H20

H_2P8

@

1

H22

H_2P8

@

1

H5

H_3P7

@

1

H14

H_3P7

@

1

CE57

10U_0603_6.3V6M

KBBL@

1

2

FD4

FIDUCIAL@

1

UE4

MX25L1005AMC-12G_SO8

SA00002C100

KB930@

CS#

1

SO

2

WP#

3

GND

4

VCC 8

HOLD# 7

SCLK 6

SI 5

CE56

1U_0603_10V6K

KBBL@

1

2

H16

H_2P8

@

1

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SUSP SUSP

+3V_D

PCH_PWR_EN#

+1.5VS_D

SUSP

+VCCP_D

+3VS_D

SUSP

SUSP

SUSP

+5VS_D

SUSP

PCH_PWR_EN#

SUSP

+DDR_CHG

+1.5V_CPU_VDDQ_CHG

SYSON#

PCH_PWR_EN#

SYSON#

+1.5V_D

SUSP#<10,24,28,46,47,48>

SYSON<24,28,48>

RUN_ON_CPU1.5VS3#<6,10>

PCH_PWR_EN<24>

PCH_PWR_EN#<19>

+3V_PCH

+1.5VS +3VS+VCCP

+5VALW

B+_BIAS

+5VS

+3VALW

B+_BIAS

+3VS

B+_BIAS

+1.5V +1.5VS

+3VALW

B+_BIAS

+3V_PCH

+5VALW

+5VALW

+0.75VS+1.5V_CPU_VDDQ

+5VALW+3VALW

+1.5V

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

27 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

DC/DC Interface

+5VALW to +5VS

+3VALW to +3VS

+1.5V To +1.5VS

+3VALW to +3V_PCH

40mil

QZ1

SI4128DY-T1-GE3_SO8

3

5

2

4

1

6

7

8

RZ8

0_0402_5%

CZ1

10U_0805_10V6K

1

2

RZ4

470K_0402_5%

1 2

CZ15

0.1U_0603_50V_X7R

1

2

QZ13A

2N7002DW-7-F_SOT363-6

61

2

CZ17

0.1U_0603_50V_X7R

@

1

2

CZ21

0.1U_0603_50V_X7R

@

1

2

RZ16

100K_0402_5%

12

QZ13B

2N7002DW-7-F_SOT363-6

3

5

4

QZ2A

DMN66D0LDW-7_SOT363-6

61

2

QZ14B

2N7002DW-7-F_SOT363-6

3

5

4

RZ20

0_0402_5%

CZ5

10U_0805_10V6K

1

2

G

D

S

QZ9

SSM3K7002F_SC59-3

2

13

G

D

S

QZ15

SSM3K7002FU_SC70-3

2

13

CZ18

10U_0805_10V6K

1

2

CZ10

0.1U_0603_50V_X7R

1

2

CZ6

10U_0805_10V6K

1

2

G

D

S

QZ10

SSM3K7002F_SC59-3

2

13

CZ16

0.1U_0603_50V_X7R

@

1

2

RZ5

0_0402_5%

CZ11

10U_0805_10V6K

1

2

CZ2

10U_0805_10V6K

1

2

QZ14A

2N7002DW-7-F_SOT363-6

61

2

RZ13

470K_0402_5%

1 2

RZ19

100K_0402_5%

12

CZ19

0.1U_0402_16V7K

1

2

RZ22

100K_0402_5%

12

RZ24

470_0402_5%

12

RZ3

220_0402_5%

12

RZ12

100K_0402_5%

12

RZ9

1.5M_0402_5%~D

1 2

RZ18

100K_0402_5%

12

G

D

S

QZ11

SSM3K7002FU_SC70-3

2

13

QZ2B

DMN66D0LDW-7_SOT363-6

3

5

4

RZ14

39.2K_0402_1%

QZ7

SI4128DY-T1-GE3_SO8

3

5

2

4

1

6

7

8

RZ10

100K_0402_5%

12

G

D

S

QZ6

SSM3K7002FU_SC70-3~D

2

13

CZ8

1U_0603_10V6K

1

2

CZ7

10U_0805_10V6K

1

2

RZ23

470_0402_5%

12

G

D

S

QZ12

SSM3K7002F_SC59-3

2

13

CZ9

0.1U_0603_50V_X7R

1

2

RZ21

2M_0402_5%~D

12

G

D

S

QZ4

SSM3K7002F_SC59-3

2

13

JP2

JUMP_43X79

@

1

122

CZ4

1U_0603_10V6K

1

2

RZ25

470_0402_5%

12

UZ1

SI4634DY-T1-E3_SO8~D

4

7

8

6

5

1

2

3

RZ15

1.5M_0402_5%~D

1 2

CZ13

10U_0805_10V6K

1

2

CZ3

10U_0805_10V6K

1

2

G

D

S

QZ5

SSM3K7002FU_SC70-3~D

2

13

RZ2

22_0603_5%~D

12

RZ26

470_0402_5%

12

RZ11

10K_0402_5%

1 2

QZ3

SI4128DY-T1-GE3_SO8

3

5

2

4

1

6

7

8

CZ14

1U_0603_10V6K

1

2

CZ12

10U_0805_10V6K

1

2

RZ17

100K_0402_5%

@

12

RZ27

470_0402_5%

12

RZ7

470K_0402_5%

1 2

G

D

S

QZ8

SSM3K7002F_SC59-3

2

13

RZ1

470_0603_5%

1 2

CZ20

0.1U_0603_50V_X7R

1

2

RZ6

1.5M_0402_5%~D

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EXPRCRD_CPPE#

CARD_RESET#

CPUSB#

USB20_P11

USB20_N11

EXP_USBP11_D+

EXP_USBP11_D-

PCH_SMBDATA

PCH_SMBCLK

CPUSB#

CARD_RESET#

EXPCLK_REQ#

EXP_USBP11_D-

EXP_USBP11_D+

CLK_PCIE_EXP#

EXPRCRD_CPPE#

PCIE_WAKE#

CLK_PCIE_EXP

PCIE_PTX_EXPRX_N3

PCIE_PTX_EXPRX_P3

PCIE_PRX_EXPTX_N3_C

PCIE_PRX_EXPTX_P3_C

PLT_RST#

STBY#_R

PCH_SMBDATA

PCH_SMBCLK

STBY#_R

SYSON_R

SYSON_R

USB_DETECT# USB_DET#_DELAY

USB20_N11<16>

USB20_P11<16>

PCIE_WAKE#<15,24,32>

EXPCLK_REQ#<14>

CLK_PCIE_EXP#<14>

CLK_PCIE_EXP<14>

PCIE_PRX_EXPTX_P3<14>

PCIE_PRX_EXPTX_N3<14>

PCIE_PTX_EXPRX_P3<14>

PCIE_PTX_EXPRX_N3<14>

PLT_RST#<6,16,24,32>

PCH_SMBCLK<6,11,12,14,29,32>

PCH_SMBDATA<6,11,12,14,29,32>

PM_SLP_S3#<15,24>

SUSP#<10,24,27,46,47,48>

USB_DET#_DELAY <24>

USB_DETECT# <33>

EC_ON<24,25>

EC_ON_35V <45>

SYSON<24,27,48>

+1.5VS

+1.5V_CARD

+3VALW

+3VS +3.3V_CARD

+3.3V_CARDAUX

+3VS

+1.5VS

+1.5V_CARD

+3.3V_CARD

+3VS +3VS

+3.3V_CARDAUX

+3.3V_CARD

+1.5V_CARD

+3.3V_CARD +3.3V_CARDAUX

+RTCVCC +RTCVCC +RTCVCC +RTCVCC +RTCVCC +CHGRTC

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

28 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

Express Card PWR S/W

1A 1A

500mA

500mA

275mA275mA

Express Card

CLOSE TO U1

USB Detected for PWR Share

RX6 0_0402_5%@

1 2

CX3

0.1U_0402_25V6K

EXP@

1

2

R778

100K_0402_5%

12

CX5

0.1U_0402_25V6K

EXP@

1

2

C13

0.1U_0402_16V7K

1

2

R787 0_0402_5%

@

1 2

BAV70W-7-F_SOT323-3

D5

2

3

1

CX8

0.1U_0402_25V6K

EXP@ 1

2

RX3 0_0402_5%@

1 2

RX2 0_0402_5%@

1 2

RX7 0_0402_5%

1 2

C14

0.1U_0402_16V7K

1

2

UX1

TPS2231MRGPR-2_QFN20_4X4~D

EXP@

STBY#

1

3.3VIN

23.3VOUT 3

NC

4

NC

5

SYSRST#

6

GND 7

PERST# 8

CPUSB# 9

CPPE# 10

1.5VOUT 11

1.5VIN

12

NC

13

NC

14

AUXOUT 15

NC

16

AUXIN

17

RCLKEN 18

OC#

19

SHDN#

20

PAD 21

CX6

0.1U_0402_25V6K

EXP@ 1

2

CX11

10U_0603_6.3V6M

EXP@

1

2

CX10

0.1U_0402_25V6K

EXP@ 1

2

CX12 0.1U_0402_10V7K~DEXP@

1 2

D4

SDMK0340L-7-F

2 1

JEXP

TYCO_2-2041070-6~D

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

GND

27

GND

28

U1

TC7SZ14FU_SSOP5~D

Y4

P5

G

3

A

2NC

1

C4

2.2U_0603_6.3V6K

12

CX13 0.1U_0402_10V7K~DEXP@

1 2

C3

0.1U_0402_16V7K

1

2

R781 0_0402_5%

1 2

D3

SDMK0340L-7-F

2 1

R780

1M_0402_5%

12

CX1

0.1U_0402_25V6K

EXP@

1

2

CX7

10U_0603_6.3V6M

EXP@

1

2

R779

220K_0402_5%

12

CX4

0.1U_0402_25V6K

EXP@

1

2

RX5

2.2K_0402_5%

EXP@

1 2

CX9

10U_0603_6.3V6M

EXP@

1

2

RX8 0_0402_5%

1 2

CX2

0.1U_0402_25V6K

EXP@

1

2

RX4

2.2K_0402_5%

EXP@

1 2

LX1

DLW21SN900SQ2_0805~D

EXP@

1

1

4

433

22

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

1 1

2 2

3 3

4 4

SATA_PRX_DTX_N2_C

SATA_PTX_DRX_N2_C

SATA_PTX_DRX_P2_C

SATA_PRX_DTX_P2_C

FFS_INT2_Q

HDD_DET#

SATA_PRX_DTX_P0_C

SATA_PTX_DRX_N0_C

SATA_PRX_DTX_N0_C

SATA_PTX_DRX_P0_C

ODD_EN

+3.3V_RUN_FFS

FFS_INT2_Q

FFS_INT2

PCH_SMBDATA

PCH_SMBCLK

FFS_INT1

ODD_DA#_R

HDD_EN_5V

HDD_DET#<13>

ODD_EN#<17>

SATA_PRX_DTX_P0<13>

SATA_PRX_DTX_N0<13>

FFS_INT1<16>

FFS_INT2<17>

ODD_DETECT#<17>

SATA_PTX_DRX_P0_C<13>

SATA_PTX_DRX_N0_C<13>

SATA_PRX_DTX_P2<13>

SATA_PRX_DTX_N2<13>

SATA_PTX_DRX_P2_C<13>

SATA_PTX_DRX_N2_C<13>

PCH_SMBDATA<6,11,12,14,28,32>

PCH_SMBCLK<6,11,12,14,28,32>

ODD_DA#<16>

HDD_S3.5<24>

+5V_HDD

+5VS_ODD

+3VS

+5VS

B+_BIAS

+5VS_ODD

+3VS

+5V_HDD

+3VS

+3VS

+5V_HDD+3VS

+5V_HDD

+5VALW

+5VS

+3VALW

B+_BIAS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

HDD/ODD/FAN

Custom

29 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

SATA HDD Conn.

Pleace near ODD CONN

SATA ODD Conn.

ODD Power Control

SHORT DEFAULT

+5V_HDD Source

JP6

PAD-OPEN1x1m

@

1 2

CN14 0.01U_0402_16V7K

12

CN1

10U_0603_6.3V6M

FFS@ 1

2

CN3 0.01U_0402_16V7K

1 2

RN10

100K_0402_5%@

12

CN8

0.1U_0402_25V6K

1

2

CN13

1U_0402_6.3V6K

1

2

QN5A

DMN66D0LDW-7_SOT363-6

@

61

2

10U_0805_10V6K

CN18

@1

2

10U_0805_10V6K

CN12

1

2

LNG3DM

UN1

LNG3DMTR_LGA16_3X3~D

FFS@

VDD_IO

1

NC 2

NC 3

SCL/SPC

4

GND 5

VDD

14

CS

8

INT 1

11

INT 2

9

RES 10

GND 12

SDO/SA0

7

SDA / SDI / SDO

6

RES 13

RES 16

RES 15

RN8 0_0402_1%

@

1 2

CN2

0.1U_0402_25V6K

FFS@ 1

2

RN5 100K_0402_5%

FFS@

1 2

CN15 0.01U_0402_16V7K

12

CN9

0.1U_0402_25V6K

1

2

JHDD

SUYIN_127043FB022G208ZR_RV

CONN@

GND

1

A+

2

A-

3

GND

4

B-

5

B+

6

GND

7

VCC3.3

8

VCC3.3

9

VCC3.3

10

GND

11

GND

12

GND

13

VCC5

14

VCC5

15

VCC5

16

GND

17

RESERVED

18

GND

19

VCC12

20

VCC12

21

VCC12

22

RN12

100K_0402_5%

@

12

QN1A

DMN66D0LDW-7_SOT363-6

FFS@

61

2

RN2

100K_0402_5%

FFS@

12

RN11

100K_0402_5%

@

12

CN17

0.1U_0603_50V_X7R

@1

2

RN7

1.5M_0402_5%~D

1 2

QN1B

DMN66D0LDW-7_SOT363-6

FFS@

3

5

4

CN6

0.1U_0402_25V6K

1

2

JP13

JUMP_43X79

@

1

122

RN1

100K_0402_5%

@

12

CN10

1000P_0402_50V7K

1

2

QN5B

DMN66D0LDW-7_SOT363-6

@

3

5

4

RN9

100K_0402_5%@

12

RN4 10K_0402_5%

FFS@

1 2

CN7

10U_0805_10V6K

1

2

CN11

0.1U_0402_25V6K

1

2

S

G

D

QN4

SI3456DDV-T1-GE3_TSOP6~D

@

3

6

2

4 5

1

G

D

S

QN3

SSM3K7002FU_SC70-3

2

13

CN5

1000P_0402_50V7K

1

2

S

G

D

QN2

SI3456BDV-T1-E3 1N TSOP6

3

6

2

45

1

RN6

470K_0402_5%

1 2

CN16

0.1U_0402_25V6K

1

2

RN3 10K_0402_5%

FFS@

1 2

CN4 0.01U_0402_16V7K

1 2

JP7

JUMP_43X79

@

1

122

JODD

TYCO_2-1759838-8~D

CONN@

GND1 14

GND2 15

GND

1

RX+

2

RX-

3

GND

4

TX-

5

TX+

6

GND

7

DP

8

+5V

9

+5V

10

MD

11

GND

12

GND

13

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+FILT_1.65V

+FILT_1.8V

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

+VDD_IO

PC_BEEP

SPK_L2+

SPK_R1-

SPK_L1-

SPK_R2+

SENSE_A MIC1_PLUG

HP_PLUG

PC_BEEP

SPK_L2+_CONN

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

SPK_L2+

SPK_R1-

SPK_R2+

SPK_L1-

HP_R

HP_L

HDA_SDOUT_AUDIO HDA_RST_AUDIO#

HDA_SYNC_AUDIO

HDA_BITCLK_AUDIO

MIC1_L

MIC1_R

MIC1_PLUG

MIC1_L

MIC1_R_RMIC1_R

MIC1_L_R

HP_R

HP_L HPL

HPR

HP_PLUG

SPK_L2+_CONN

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

AMP_LEFT

AMP_RIGHT

HDA_RST_AUDIO#<13>

HDA_SDIN0<13>

HDA_SYNC_AUDIO<13>

HDA_SDOUT_AUDIO<13>

HDA_BITCLK_AUDIO<13>

EAPD<24,31>

EC_MUTE#<24>

MIC_CLK<22>

MIC_DATA<22>

BEEP#<24>

HDA_SPKR<13>

SPK_L2+_CONN<31>

SPK_L1-_CONN<31>

SPK_R2+_CONN<31>

SPK_R1-_CONN<31>

AMP_LEFT <31>

AMP_RIGHT <31>

+LDO_OUT_3.3V

+5VS

+5VS

+3VS

+3VS

+5VS

+MICBIASB

GNDA

GNDA

GNDAGNDA

GNDA GNDA

+MICBIASB

+3V_PCH

GNDA

GNDA

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

30 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

AVDD_3.3 pinis output of

internal LDO. NOT connect

to external supply.

Please bypass caps very close to device.

Internal SPEAKER

Reserve for EMI

PC Beep

ICH Beep

EC Beep

close to Codec

wide 30MIL

for EMI

GND GNDA

Vendor

recommend

VDD_IO is

the same

with HDA

MIC JACK

HeadPhone JACK

Close to UA1

Pin11,13,14,16

OUTPUT 1Vrms

CA37

0.1U_0402_16V7K@

1

2

RA8 20K_0402_1%

1 2

CA36

10P_0402_50V8J

@

1

2

CA18

220P_0402_50V8J

@

1

2

RA6 5.11K_0402_1%

1 2

CA30

1000P_0402_50V7K

1

2

CA31

1000P_0402_50V7K

1

2

CA25 15P_0402_50V8J@

1

2

CA12

0.1U_0402_16V7K

1

2

RA14 0_0402_5%

1 2

CA3

4.7U_0603_6.3V6K

1

2

RA22 0_0402_5%

@

1 2

LA2

FBMA-L10-160808-800LMT_2P

1 2

RA11 0_0402_5%

12

RA10 0_0402_5%

@

1 2

CA2

0.1U_0402_16V7K

1

2

CA32

1000P_0402_50V7K

1

2

CA11

0.1U_0402_16V7K

1

2

CA8

10U_0603_6.3V6M

1

2

RA19

10K_0402_5%

12

RA18

10_0402_1%

@

1 2

G

G

G

JMIC

SINGA_2SJ3013-010311F

CONN@

1

2

3

4

5

6

8

9

7

CA26 1U_0603_10V6K

1 2

CA20 4.7U_0603_6.3V6K

1 2

DA1

PESD5V0U2BT_SOT23-3

2

3

1

RA1

3.3K_0402_5%

12

UA1

CX20672-21Z_QFN40_6X6

VDD_IO 7

VAUX_3.3 2

SDATA_OUT

4

BIT_CLK

5

SDATA_IN

6

DVDD_3.3 18

SYNC

8

RESET#

9

PORTA_L 22

PORTA_R 23

AVDD_3.3 27

PORTC_L 30

RPW R_5.0 15

LPW R_5.0 12

FLY_P 19

FLY_N 20

RIGHT-

14 RIGHT+

16

PORTB_L 34

B_BIAS 33

PORTB_R 35

DMIC_CLK

40

AVEE 21

C_BIAS 32

PORTC_R 31

FILT_1.65 29

LEFT-

13

GPIO1/SPK_MUTE#

37

DMIC_1/2

1

AVDD_5V 28

GPIO0/EAPD#

38

LEFT+

11

SENSE_A 36

CLASS-D_REF 17

AVDD_HP 26

FILT_1.8 3

PC_BEEP

10

GND

41

NC 24

NC 25

SPDIF

39

CA17

220P_0402_50V8J

@

1

2

RA23 0_0402_5%

1 2

CA7

10U_0603_6.3V6M

1

2

DA2

PESD5V0U2BT_SOT23-3

2

3

1

DA7

BAT54C-7-F_SOT23-3

2

3

1

DA5

PESD5V0U2BT_SOT23-3

@

2

3

1

RA12 39.2_0402_1%

1 2

CA14

0.1U_0402_16V7K

1

2

CA5

0.1U_0402_16V7K

1

2

CA22

10P_0402_50V8J

@

1

2

LA6 0_0603_5%

1 2

RA9 39.2K_0402_1%

1 2

G

G

G

JHP

SINGA_2SJ3013-010311F

CONN@

1

2

3

4

5

6

8

9

7

CA21 1000P_0402_50V7K

@

1 2

CA19 4.7U_0603_6.3V6K

1 2

CA40

0.1U_0402_16V7K

@

1 2

DA3

PESD5V0U2BT_SOT23-3

2

3

1

RA3

100_0402_1%

1 2

CA23

10P_0402_50V8J

@

1

2

RA13 39.2_0402_1%

1 2

RA5 33_0402_5%

1 2

CA1

1U_0603_10V6K

1

2

CA9

4.7U_0603_6.3V6K

1

2

CA29

1000P_0402_50V7K

1

2

CA34

10P_0402_50V8J

@

1

2

CA39

0.1U_0402_16V7K

@

1 2

LA5 0_0603_5%

1 2

RA4

100_0402_1%

1 2

DA6

PESD5V0U2BT_SOT23-3

@

2

3

1

LA1

FBMA-L10-160808-800LMT_2P

1 2

JSPK

ACES_87213-0400G

CONN@

1

1

2

2

3

3

4

4GND 5

GND 6

RA17

4.7K_0402_5%@

12

LA3 0_0603_5%

1 2

CA4

0.1U_0402_16V7K

1

2

RA2

3.3K_0402_5%

12

CA27

0.1U_0402_16V7K

@

1

2

CA6

0.1U_0402_16V7K

1

2

CA10

0.1U_0402_16V7K

1

2

CA28

4.7U_0603_6.3V6K

1

2

RA15 33_0402_5%

1 2

RA7 0_0402_5%

1 2

CA13

0.1U_0402_16V7K

1

2

CA38

10P_0402_50V8J

@

1

2

CA16

0.1U_0402_16V7K

1

2

LA4 0_0603_5%

1 2

CA24 15P_0402_50V8J@

1

2

CA41

0.1U_0402_16V7K

1 2

CA15

4.7U_0603_6.3V6K

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BSPR

EAPD_R

GIN0

AMP_LEFT_C

PLIMIT

OUTPR

GIN1

BSPL

OUTNR

GIN1GIN0

OUTPL

OUTNL

BSNR

BSNL

OUTNL

OUTNR

OUTPR

OUTPL

AMP_RIGHT_C

+GVDD

AMP_LEFT

AMP_RIGHT

+PVDD

+PVDD SPK_L2+_CONN

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

CLK_X1 CLK_X2

CLK_X2

CLK_X1

LAN_X1_R

LAN_X1_R

PCH_X1_R

VGA_X1_R

EAPD<24,30>

SPK_L2+_CONN <30>

SPK_L1-_CONN <30>

SPK_R2+_CONN <30>

SPK_R1-_CONN <30>

AMP_LEFT<30>

AMP_RIGHT<30>

PCH_RTCX1_R <13>

LAN_X1 <14>

PCH_X1 <14>

VGA_X1 <35>

+GVDD

+GVDD

B+

+3VALW

+5VS

+RTCBATT +RTCVCC

+3VLP

+3VLP

+3VALW

+VCCP

+3VALW+VCCP

+1.8VGS

+1.8VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

AMP

Custom

56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

31

Close to UA2

Pin7,15,16,27,28

5A/120ohm/100MHz

5A/120ohm/100MHz

5A/120ohm/100MHz

5A/120ohm/100MHz

0

0

GAIN1 GAIN0

1

1 0

0

1 1

20dB

26dB

32dB

60Kohm

36dB

30Kohm

15Kohm

AV(inv) INPUT

IMPEDANCE

9Kohm

TPA3113 for Speaker

Close to LA9

40mil

Close to LA3

Close to LA4

Close to LA5

Close to LA6

reserved for swing level adjustment

(close to U2)

Need final turn R/C

10/24

Depop if GCLK

with UMA

UMA only

CA42

10U_1206_25V6M

AMP@

1

2

C5

22U_0805_6.3V6M

GCLK@

1 2

CA46

1U_0603_25V6K

AMP@

12

CA58

1U_0603_25V6K

AMP@

12

RA35

100K_0402_1%

@

1 2

CA52

0.027U_0402_16V6K

AMP@

1 2

UA2

TPA3113D2PWPR_HTSSOP28

AMP@

SD#

1

FAULT#

2

LINP

3

LINN

4

GAIN0

5

GAIN1

6

AVCC

7

AGND 8

GVDD 9

PLIMIT 10

RINN

11

RINP

12

NC

13

PBTL 14

PVCCR

15

PVCCR

16

BSPR 17

OUTPR 18

PGND 19

OUTNR 20

BSNR 21

BSNL 22

OUTNL 23

PGND 24

OUTPL 25

BSPL 26

PVCCL

27

PVCCL

28

GND

29

RA27

28.7K_0402_1%

AMP@

12

CA51

0.027U_0402_16V6K

AMP@

1 2

C8

0.1U_0402_16V7K

GCLK@

1

2

RA33

100K_0402_1%

@

1 2

U2

SLG3NB274VTR_TQFN16_2X3

GCLK@

XTAL_IN

1

VDD

2

VDDIO_25M_B

3

GND1

4

25MHz_B 5

25MHz_A 6

GND2

7

VDDIO_25M_A

8

32kHz 9

VBAT

10

VDDIO_27M

11 27MHz 12

GND3

13

VDD_RTC_OUT 14

+V3.3A

15

XTAL_OUT

16

GND4

17

RA34

100K_0402_1%

AMP@

1 2

R785

33_0402_5%

GCLK@

1 2

RA38

10K_0402_5%

@

12

CA47

1U_0603_25V6K

AMP@

12

CA56

0.22U_0603_25V7K

AMP@

1 2

CA45

1U_0603_25V6K

AMP@

12

CA53

0.22U_0603_25V7K

AMP@

1 2

C10

2.2U_0603_6.3V6K

GCLK@

1

2

U2

SLG3NB244VTR_TQFN16_2X3

@

CA57

1U_0603_25V6K

AMP@

12

RA39

240K_0402_1%

AMP@

1 2

RA26

100K_0402_5%

AMP@

12

C9

0.1U_0402_16V7K

GCLK@

1

2

R783

0_0402_5%

GCLK@

1 2

LA7

HCB2012KF-121T50_0805

AMP@

1 2

C7

0.1U_0402_16V7K

GCLK@

1

2

Y1

25MHZ_20PF_7V25000016

GCLK@

GND

2

33

1

1

GND

4

CA55

0.22U_0603_25V7K

AMP@

1 2

RA37

240K_0402_1%

AMP@

1 2

RA24

100K_0402_5%

@

1 2

C6

0.1U_0402_16V7K

GCLK@ 1

2

LA11

HCB2012KF-121T50_0805

AMP@

1 2

CA54

0.22U_0603_25V7K

AMP@

1 2

CA44

1U_0603_25V6K

AMP@

12

C12

33P_0402_50V8K

GCLK@

1

2

RA25

0_0402_5%

AMP@

1 2

C11

33P_0402_50V8K

GCLK@

1

2

RA36

100K_0402_1%

AMP@

1 2

LA9

FBMA-L11-160808-121LMA30T_0805

AMP@

1 2

R784

0_0402_5%

@

1 2

RA40

10K_0402_5%

@

12

CA49

0.027U_0402_16V6K

AMP@

1 2

RA28

10K_0402_1%

AMP@

12

LA8

HCB2012KF-121T50_0805

AMP@

1 2

CA48

1U_0603_25V6K

AMP@

12

CA43

0.1U_0402_16V7K

AMP@

1

2

R782

33_0402_5%

GCLK@

1 2

CA50

0.027U_0402_16V6K

AMP@

1 2

LA10

HCB2012KF-121T50_0805

AMP@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB20_N10_R

USB20_P10

USB20_N10

USB20_P10_R

USB20_N10_R

USB20_P10_R

SATA_PRX_DTX_P1

SATA_PRX_DTX_N1

SATA_PTX_DRX_P1_C

SATA_PTX_DRX_N1_C

PWR_LED#

USB10N_R

USB10N_R

USB10P_R

USB10N

USB10P

USB10P_R

USB10N

USB10P

USB3RP3_R

USB3RN3_R

USB3RP4_R

USB3RN4_R

+DAS_PWR

PCH_SATALED#

BATT_LOW_LED#

BATT_CHG_LED#

PWR_LED#

WL_BT_LED#

USB20_N2<16>

USB20_P2<16>

USB3TN3<16>

USB3TP3<16>

USB3RN3<16>

USB3RP3<16>

USB20_P3<16>

USB20_N3<16>

USB3RP4<16>

USB3RN4<16>

USB3TP4<16>

USB3TN4<16>

USB20_N10<16>

USB20_P10<16>

SATA_PRX_DTX_P1<13>

SATA_PRX_DTX_N1<13>

SATA_PTX_DRX_P1_C<13>

SATA_PTX_DRX_N1_C<13>

PWR_PWM_LED#<24>

BATT_CHG_LED#<24>

BATT_LOW_LED#<24>

PCH_SATALED#<13>

WL_BT_LED#<24>

DASH_SW1<24>

DASH_SW2<25>

DASH_SW3<24>

WOL_EN# <24>

PLT_RST# <6,16,24,28>

WLAN_CLKREQ# <14>

USB_OC3# <16>

USB_OC2# <16>

LAN_CLKREQ# <14>

USB_EN# <24,33>

PCIE_WAKE# <15,24,28>

BT_ON# <17>

WL_OFF# <16>

CLK_PCIE_WLAN <14>

CLK_PCIE_WLAN# <14>

PCIE_PRX_WLANTX_N2 <14>

PCIE_PRX_WLANTX_P2 <14>

PCIE_PTX_WLANRX_P2 <14>

PCIE_PTX_WLANRX_N2 <14>

PCIE_PRX_LANTX_P1 <14>

PCIE_PRX_LANTX_N1 <14>

CLK_PCIE_LAN <14>

CLK_PCIE_LAN# <14>

PCIE_PTX_LANRX_N1 <14>

PCIE_PTX_LANRX_P1 <14>

USB20_N4<16>

USB20_P4<16>

DASH_LED1#<24>

DASH_LED2#<24>

DASH_LED3#<24>

AOAC_ON <24>

EC_TX <24>

EC_RX <24>

USB20_P8<16>

USB20_N8<16>

USB20_N5<16>

USB20_P5<16>

PCH_SMBDATA <6,11,12,14,28,29>

PCH_SMBCLK <6,11,12,14,28,29>

HDD_DETECT# <17>

CLK_LAN_25M <14>

LID_SW# <24,26>

DASH_LED_PWM <24>

WLAN_WAKE#<24>

PWR_LED#<25>

+3VS

+5VS

+5VALW

+3VS

+5VALW

+3VS

+3VS

+1.5VS

B+_BIAS

+3VALW

+5VS

+5VS

+5VALW

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

32 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

To CardReader/B

To Finger Print

10mils, All pins

To LED/B

TO Function/B

To CardReader/B

* Inspiron only

* Vostro only

<---WLAN (Mini Card 1)

<---10/100/1G LAN

R9 0_0402_5%VOS@

1 2

JFP

ACES_51524-0060N-001

CONN@

1

1

2

2

3

3

4

4

5

5

6

6G1 7

G2 8R777

10K_0402_5%

12

R786

100K_0402_5%

12

JCR1

ACES_50504-0040N-001

CONN@

1

1

2

2

G1 5

G2 6

3

3

4

4

R7 0_0402_5%@

1 2

L2

DLW21SN900SQ2_0805~D

VOS@

1

1

4

433

22

R8 0_0402_5%@

1 2

R1 0_0402_5%@

1 2

Q2

AP2301GN-HF_SOT23-3

2

3 1

G

D

S

Q1

2N7002_SOT23

2

13

R776

0_0402_1%@

1 2

D6

PESD5V0U2BT_SOT23-3

@

2

3

1

C1

0.1U_0402_25V6K

1

2

JLED2

ACES_51524-0080N-001

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

G1 9

G2 10

JCR2

ACES_50504-0040N-001

CONN@

1

1

2

2

G1 5

G2 6

3

3

4

4

R771

0_0402_1%@

1 2

R2 0_0402_5%@

1 2

JLED

ACES_51524-0080N-001

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

G1 9

G2 10

R10 0_0402_5%VOS@

1 2

JBTB1

ACES_88079-0800A1

CONN@

1

122

3

344

5

566

7

788

9

910 10

11

11 12 12

13

13 14 14

15

15 16 16

17

17 18 18

19

19 20 20

21

21 22 22

23

23 24 24

25

25 26 26

27

27 28 28

29

29 30 30

31

31 32 32

33

33 34 34

35

35 36 36

37

37 38 38

39

39 40 40

41

41 42 42

43

43 44 44

45

45 46 46

47

47 48 48

49

49 50 50

51

51 52 52

53

53 54 54

55

55 56 56

57

57 58 58

59

59 60 60

61

61 62 62

63

63 64 64

65

65 66 66

67

67

69

69

71

71

73

73

75

75

77

77

79

79

68 68

70 70

72 72

74 74

76 76

78 78

GND

81

80 80

GND 82

C2

0.1U_0402_16V7K

1

2

G

D

S

Q3

SSM3K7002FU_SC70-3~D

2

13

R775

0_0402_1%@

1 2

JFC

ACES_51524-0080N-001

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

G1 9

G2 10

L1

DLW21SN900SQ2_0805~D

INS@

1

1

4

433

22

R772

0_0402_1%@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB20_N0_R

USB20_P0_R

USB3RP1_R

USB3TN1_R

USB3TP1_R

USB3RN1_R

USB3TP2_R

USB3RP2_R

USB3TP2_R

USB3RN2_R

USB3TN2_R

USB3RP2_R

USB3TN2_R

USB3RN2_R

USB20_P1_R

USB20_N1_R

USB20_N1_R

USB20_P1_R

USB3RP2_R

USB3TN2_R

USB3TP2_R

USB3RN2_R

USB20_P1_SW

USB20_N1_SW

USB3RP1_R

USB3TP1_C USB3TP1_R

USB3TN1_RUSB3TN1_C

USB3TP1_R

USB3RP1_R

USB3TP1_R

USB3RN1_R

USB3TN1_R

USB3RP1_R

USB3TN1_R

USB3RN1_R

USB3RN1_R

USB20_N0

USB20_P0

USB20_N0_R

USB20_P0_R

USB3TN2

USB3TP2

USB3RP2_R

USB3TP2_C USB3TP2_R

USB3TN2_RUSB3TN2_C

USB3RN2_R

USB3TN1

USB3TP1

USB3RN1

USB3RP1

USB3RN2

USB3RP2

SB#

USB20_P1_SW

USB20_N1_SW

PWRSHARE_EN

SEL

USB_EN#

PWRSHARE_EN

PWRSHARE_EN#

USB3TN2<16>

USB3TP2<16>

USB3RN2<16>

USB3RP2<16>

USB3TN1<16>

USB3TP1<16>

USB3RN1<16>

USB3RP1<16>

USB20_N0<16>

USB20_P0<16>

USB20_P1<16>

USB20_N1<16>

PWRSHARE_OE#<24>

USB_EN#<24,32> USB_OC0# <16>

USB_OC1# <16>

PWRSHARE_EN_EC#<24>

USB_DETECT#<28>

+5V_USB_PWR1

+5V_USB_PWR2

+5VALW +5VALW

+5V_USB_PWR1

+5VALW

+5V_USB_PWR2

+5VALW

+5VALW

+3VALW

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

33 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

2.0A

USB conn.1

USB conn.2

80mil

80mil

2.0A

UI3

AP2301MPG-13_MSOP8

FLG 5

VIN

3VOUT 6

GND

1

EN

4

VOUT 7

VIN

2VOUT 8

EPAD

9

LI2

DLW21SN900SQ2L_0805_4P~D

1

122

33

4

4

JUSB1

TAITW_PUBAU1-09FNLSCNN4H0

CONN@

VBUS

1

SSTX-

8

D+

3

GND 11

D-

2GND 10

GND 13

GND

4

SSTX+

9

SSRX-

5

GND

7

SSRX+

6

GND 12

8

DI4

IP4292CZ10-TB_XSON10U10~D

4

5

1

6

2

7

3

10

9

LI1

DLW21SN900HQ2L_0805_4P~D

1

122

33

4

4

RI14 0_0402_5%@

1 2

CI13

0.1U_0402_16V7K

1

2

CI6

4.7U_0805_10V4Z

1

2

LI5

DLW21SN900SQ2L_0805_4P~D

1

122

33

4

4

LI4

DLW21SN900HQ2L_0805_4P~D

1

122

33

4

4

CI3 0.01U_0402_16V7K

12

RI20

0_0402_1%

@

1 2

CI10 0.01U_0402_16V7K

12

RI16 0_0402_5%@

1 2

UI1

SLG55584AVTR_TDFN8_2X2

CEN 1

DP 3

SELCDP 4

DM 2

VDD

5TDP

6

CB

8

TDM

7

Thermal Pad 9

DI5

PESD5V0U2BT_SOT23-3

@

2

3

1

8

DI1

IP4292CZ10-TB_XSON10U10~D

4

5

1

6

2

7

3

10

9

RI6 0_0402_5%@

1 2

RI5 0_0402_5%@

1 2

RI10

10K_0402_5%

1 2

RI17 0_0402_5%@

1 2

RI4 0_0402_5%@

1 2

G

D

S

QI1

SSM3K7002FU_SC70-3~D

2

13

LI3

DLW21SN900HQ2L_0805_4P~D

1

122

33

4

4

RI1 0_0402_5%@

1 2

CI11 0.01U_0402_16V7K

12

RI13 0_0402_5%@

1 2

CI2

0.1U_0402_25V6K

1

2

DI2

PESD5V0U2BT_SOT23-3

2

3

1

+

CI1

220U_6.3V_M

1

2

RI15 0_0402_5%@

1 2

CI4 0.01U_0402_16V7K

12

RI8

10K_0402_5%

12

+

CI8

220U_6.3V_M

1

2

RI12

10K_0402_5%

@

1 2

DI3

SDMK0340L-7-F_SOD323-2~D

1 2

RI18 0_0402_5%@

1 2

RI7 0_0402_5%

1 2

LI6

DLW21SN900HQ2L_0805_4P~D

1

122

33

4

4

RI19

0_0402_1%

@

1 2

CI14

0.1U_0402_16V7K

1

2

CI7

0.1U_0402_16V7K

1

2

RI3 0_0402_5%@

1 2

CI17

0.1U_0402_16V7K

1

2

UI2

AP2301MPG-13_MSOP8

FLG 5

VIN

3VOUT 6

GND

1

EN

4

VOUT 7

VIN

2VOUT 8

EPAD

9

JUSB2

TAITW_USB011-107BRL-TW

CONN@

VBUS

1

SSTX-

8

D+

3

GND

4

D-

2

D1-DP 10

GND 12

SSTX+

9

SSRX-

5

GND 11

SSRX+

6

GND

7

GND 13

GND 14

CI12

4.7U_0805_10V4Z

1

2

CI5

0.1U_0402_25V6K

1

2

CI9

0.1U_0402_25V6K

1

2

CI15

0.1U_0402_16V7K

1

2

RI2 0_0402_5%@

1 2

RI11

100K_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PEG_VGA

CLK_PEG_VGA#

PCIE_CRX_C_GTX_P4

PCIE_CRX_C_GTX_N4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P4

PCIE_CRX_C_GTX_P6

PCIE_CRX_C_GTX_N6

PEG_GTX_C_HRX_P6

PEG_GTX_C_HRX_N6

PCIE_CRX_C_GTX_P7

PCIE_CRX_C_GTX_N7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P7

PCIE_CRX_C_GTX_P1

PCIE_CRX_C_GTX_N1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P1

PCIE_CRX_C_GTX_P0

PCIE_CRX_C_GTX_N0

PEG_GTX_C_HRX_P0

PEG_GTX_C_HRX_N0

PCIE_CRX_C_GTX_P5

PCIE_CRX_C_GTX_N5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P5

PCIE_CRX_C_GTX_P3

PCIE_CRX_C_GTX_N3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P3

PCIE_CRX_C_GTX_P2

PCIE_CRX_C_GTX_N2

PEG_GTX_C_HRX_P2

PEG_GTX_C_HRX_N2

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_P[7..0]

PEG_HTX_C_GRX_N[7..0]

PEG_GTX_C_HRX_P[7..0]

PEG_GTX_C_HRX_N[7..0]

GPU_RST#

GPU_RST#

CLK_PEG_VGA<14>

CLK_PEG_VGA#<14>

PEG_HTX_C_GRX_P[7..0]<5>

PEG_HTX_C_GRX_N[7..0]<5>

PEG_GTX_C_HRX_P[7..0] <5>

PEG_GTX_C_HRX_N[7..0] <5>

DGPU_HOLD_RST#<16>

PCH_PLTRST#<16>

+1.0VGS

+3VGS

+1.0VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

1.0

ATI_SeymourXT_M2_PCIE/LVDS

Custom

34 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

LVDS Interface

GFX PCIE LANE REVERSAL

Chelsea Only

Thames/seymour Only

Install 2K for Thames/Seymour

12/8 Remove CV59~CV74 TX8~15

12/8 Remove RX8~15

PCI EXPRESS INTERFACE

CLOCK

CALIBRATION

UV1A

THAMES XT M2 TH@

PWRGOOD

AH16 PCIE_CALRN Y29

PCIE_CALRP Y30

PCIE_REFCLKN

AA36 PCIE_REFCLKP

AB35

PCIE_RX0N

Y37 PCIE_RX0P

AA38

PCIE_RX10N

K37 PCIE_RX10P

L38

PCIE_RX11N

J36 PCIE_RX11P

K35

PCIE_RX12N

H37 PCIE_RX12P

J38

PCIE_RX13N

G36 PCIE_RX13P

H35

PCIE_RX14N

F37 PCIE_RX14P

G38

PCIE_RX15N

E37 PCIE_RX15P

F35

PCIE_RX1N

W36 PCIE_RX1P

Y35

PCIE_RX2N

V37 PCIE_RX2P

W38

PCIE_RX3N

U36 PCIE_RX3P

V35

PCIE_RX4N

T37 PCIE_RX4P

U38

PCIE_RX5N

R36 PCIE_RX5P

T35

PCIE_RX6N

P37 PCIE_RX6P

R38

PCIE_RX7N

N36 PCIE_RX7P

P35

PCIE_RX8N

M37 PCIE_RX8P

N38

PCIE_RX9N

L36 PCIE_RX9P

M35

PERSTB

AA30

PCIE_TX0N Y32

PCIE_TX0P Y33

PCIE_TX10N L32

PCIE_TX10P L33

PCIE_TX11N L29

PCIE_TX11P L30

PCIE_TX12N K32

PCIE_TX12P K33

PCIE_TX13N J32

PCIE_TX13P J33

PCIE_TX14N K29

PCIE_TX14P K30

PCIE_TX15N H32

PCIE_TX15P H33

PCIE_TX1N W32

PCIE_TX1P W33

PCIE_TX2N U32

PCIE_TX2P U33

PCIE_TX3N U29

PCIE_TX3P U30

PCIE_TX4N T32

PCIE_TX4P T33

PCIE_TX5N T29

PCIE_TX5P T30

PCIE_TX6N P32

PCIE_TX6P P33

PCIE_TX7N P29

PCIE_TX7P P30

PCIE_TX8N N32

PCIE_TX8P N33

PCIE_TX9N N29

PCIE_TX9P N30

CV326

0.1U_0402_25V6K

DIS@

1

2

CV57220nF_0402_16V7K DIS@

12

UV1

Chelsea Pro

CH@

CV52220nF_0402_16V7K DIS@

12

RV64

1K_0402_5%

DIS@

1 2

RV631.27K_0402_1% DIS@

1 2

RV2031K_0402_1% CH@

1 2

RV198 1.69K_0402_1%~DCH@

1 2

CV47220nF_0402_16V7K DIS@

12

CV56220nF_0402_16V7K DIS@

12

LVTMDP

LVDS CONTROL

UV1G

THAMES XT M2 @

DIGON AJ27

TXCLK_LN_DPE3N AR34

TXCLK_LP_DPE3P AP34

TXCLK_UN_DPF3N AL36

TXCLK_UP_DPF3P AK35

TXOUT_L0N_DPE2N AU35

TXOUT_L0P_DPE2P AW37

TXOUT_L1N_DPE1N AU39

TXOUT_L1P_DPE1P AR37

TXOUT_L2N_DPE0N AR35

TXOUT_L2P_DPE0P AP35

TXOUT_L3N AP37

TXOUT_L3P AN36

TXOUT_U0N_DPF2N AK37

TXOUT_U0P_DPF2P AJ38

TXOUT_U1N_DPF1N AJ36

TXOUT_U1P_DPF1P AH35

TXOUT_U2N_DPF0N AH37

TXOUT_U2P_DPF0P AG38

TXOUT_U3N AG36

TXOUT_U3P AF35

VARY_BL AK27

RV66

100K_0402_5%

DIS@

12

CV44220nF_0402_16V7K DIS@

12

CV51220nF_0402_16V7K DIS@

12

CV43220nF_0402_16V7K DIS@

12

CV55220nF_0402_16V7K DIS@

12

CV50220nF_0402_16V7K DIS@

12

CV49220nF_0402_16V7K DIS@

12

CV54220nF_0402_16V7K DIS@

12

CV53220nF_0402_16V7K DIS@

12

UV13

MC74VHC1G08DFT2G SC70 5P

DIS@

B

2

A

1Y4

P5

G

3

CV46220nF_0402_16V7K DIS@

12

CV45220nF_0402_16V7K DIS@

12

RV61 0_0402_5%@

12

CV58220nF_0402_16V7K DIS@

12

CV48220nF_0402_16V7K DIS@

12

RV652K_0402_1% DIS@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPU_GPIO0

GPU_GPIO1

GPU_GPIO2

GPU_GPIO9

GPU_GPIO12

GPU_GPIO13

GPU_GPIO11

GPU_VID0

GPIO25_TDI

GPIO24_TRSTB

GPIO26_TCK

GPIO27_TMS

GPIO28_TDO

XTALIN

AC_BATT

XTALOUT

+DPLL_VDDC

+DPLL_PVDD

DPLL_PVSS

VRAM_ID0

VRAM_ID1

VRAM_ID2

+AVDD

+VDD1DI

+TSVDD

XTALINXTALOUT

+VREFG_GPU

GPU_VID1

GPIO24_TRSTB

GPIO25_TDI

GPIO26_TCK

GPIO27_TMS

+VREFG_GPU

VGA_CLKREQ#_R

VGA_SMB_DA2

VGA_SMB_CK2

+DPLL_PVDD

+DPLL_VDDC

GPU_GPIO8

GENLK_CLK

GENLK_VSYNC

GPIO21_BBEN

GPU_VID2

VDDCI_VID

VGA_SMB_CK2

VGA_SMB_DA2

GPU_GPIO0

GPU_GPIO2

GPU_GPIO1

AC_BATT

GPU_GPIO9

GPU_GPIO13

GPU_GPIO12

GPU_GPIO11

GPU_GPIO8

VRAM_ID1

VRAM_ID0

VRAM_ID2

VGA_SMB_CK2

GPU_THERMAL_D-

GPU_THERMAL_D+ VGA_SMB_DA2

THM_ALERT#

GPU_THERMAL_D+

GPU_THERMAL_D-

THM_ALERT#

PACIN#

AC_BATT

VGA_CLKREQ#_R

VGA_CRT_CLK

VGA_CRT_DATA

VGA_CRT_VSYNC

VGA_CRT_HSYNC

VGA_CRT_CLK

VGA_CRT_DATA

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

XTALIN

PS_1

PS_2

PS_3

TS_FDO

TS_FDO

PS_1 PS_2 PS_3

DPLL_PVSS

+DPLL_PVDD

GPU_VID0<52>

GPU_VID1<52>

EC_SMB_DA2 <24>

EC_SMB_CK2 <24>

ACIN<15,24,43,44>

PEG_A_CLKRQ#<14>

VDDCI_VID<53>

VGA_CRT_R <21>

VGA_CRT_G <21>

VGA_CRT_B <21>

VGA_CRT_HSYNC <21>

VGA_CRT_VSYNC <21>

VGA_CRT_CLK <21>

VGA_CRT_DATA <21>

VGA_X1<31>

GPU_VID2<52>

ACIN_65W<24>

+1.8VGS

+1.8VGS

+1.8VGS

+3VGS

+1.8VGS +3VGS

+3VGS

+1.8VGS

+1.0VGS

+3VGS

+1.8VGS

+3VGS

+3VGS

+3VGS

+3VGS

+3VGS

+3VGS

+3VGS

+3VGS

+1.8VGS

+3VGS

+1.8VGS +1.8VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

1.0

ATI_SeymourXT_M2_Main_MSIC

Custom

35 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

AUD[1] AUD[0]

0 0 No audio function

0 1 Audio for DisplayPort and HDMI if dongle is detected

1 0 Audio for DisplayPort only

1 1 Audio for both DisplayPort and HDMI

HSYNCAUD[1]

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

ENABLE EXTERNAL BIOS ROM

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB

GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS

GPIO9 VGA ENABLEDBIF_VGA DIS

VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS

GPIO_22_ROMCSB

GPIO2

STRAPS

Advertises PCIE speed

when compliance test

DESCRIPTION OF DEFAULT SETTINGSPIN

GPIO[13:11]ROMIDCFG(2:0)

RECOMMENDED

SETTINGS

RSVD

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

CONFIGURATION STRAPS

BIOS_ROM_EN

VSYNCAUD[0]

H2SYNC

GPIO8

GPIO21

GENERICC

X

X

0

0

0

0

11

X

XXX

0

0

0

H2SYNC GENERICC

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL

RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND

NOT CONFLICT DURING RESET

RECOMMENDED SETTINGS

0= DO NOT INSTALL RESISTOR

1 = INSTALL 10K RESISTOR

X = DESIGN DEPENDANT

NA = NOT APPLICABLE

0.60 V level, Please

VREFG Divider ans

cap close to ASIC

XTALIN

Voltage Swing: 1.8 V

GPIO21 GPIO2

GPIO8

RSVD

RESERVED

RSVD

RESERVED

RSVD

RSVD

(1.8V@100mA VDD1DI)

(1.8V@65mA AVDD)

(1.8V@20mA TSVDD)

STRAPS

TX_PWRS_ENB GPIO0 Transmitter Power Saving Enable

0: 50% Tx output swing for mobile mode

1: full Tx output swing (Default setting for Desktop)

GPIO1TX_DEEMPH_EN PCI Express Transmitter De-emphasis Enable

0: Tx de-emphasis diabled for mobile mode

1: Tx de-emphasis enabled (Defailt setting for desktop)

R02

Internal VGA Thermal Sensor

0: 50% swing

1: Full swing

0: disable

1: enable

0: disable

1: enable

0: 2.5GT/s

1: 5GT/s

Address:100_1101

VGA Thermal Sensor ADM1032ARMZ

Closed to GPU

20mil

20mil

20mil

10mil

10mil

10mil

0

0 0

0

0

1

1 1

1 1

64MX16 (1G)

128M16 (2G)

64MX16 (1G)

Hynix 2GB

PN:SA00003YO1L

Samsung 2GB

PN:SA000047Q1L

RV67

RV68

RV70

RV69

RV71

RV71

RV67

RV69

RV70

RV68

RV72

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

Hynix 1GB

PN:SA000041S3L

Samsung 1GB

PN:SA00004GS1L

RV72

128M16 (2G)

H5TQ1G63DFR-11C

K4W1G1646G-BC11

H5TQ2G63BFR-11C

K4W2G1646C-HC11

1 0

*

(Thames 75mA)

(Thames 125mA)

(Thames 5mA)

65mA

100mA

NC_TSVSSQ should be tied to GND on Thames/Seymour

Not share via for other GND

CRT

Reserved test pad of CRT Signals for debug

Reserved test pad of CRT Signals for debug

for debug CRT

close to YV1

RV67 RV69 RV71

MT41J64M16JT-107G

PT

PT

PT

Micron 1GB

PN:SA00004Y20L

64MX16 (1G)

*

*

111

Add 12/6 for MLPS

Add 12/6 for MLPS

Add 12/8

12/8 Add external thermal sensor BOM

0.935V@Chelsea

CV89

2200P_0402_50V7K

CH@

1 2

CV88

0.1U_0402_16V7K

DIS@

1

2

RV73

10K_0402_5%

DIS@

12

RV250

0_0402_5%@

1 2

RV8810K_0402_5% @

1 2

RV239

10K_0402_5%

@

12

CV87

1U_0402_6.3V6K

DIS@

1

2

RV67 10K_0402_5%X76@

1 2

CV329

0.68U_0402_10V

@

1

2

CV77

10U_0603_6.3V6M

DIS@

1

2

RV69 10K_0402_5%X76@

1 2

RV219 10K_0402_5%@

1 2

G

D

S

QV28

2N7002_SOT23-3

@

2

1 3

CV79

1U_0402_6.3V6K

DIS@

1

2

RV95 249_0402_1%

DIS@

12

CV84

0.1U_0402_16V7K

DIS@

1

2

CV94

18P_0402_50V8J

DIS@

RV89 10K_0402_5%@

1 2

RV8010K_0402_5% @

1 2

RV90

10K_0402_5%

DIS@

12

RV7710K_0402_5% @

1 2

RV70 10K_0402_5%X76@

1 2

CV82

10U_0603_6.3V6M

DIS@

1

2

RV7510K_0402_5% DIS@

1 2

RV92 0_0402_5%@

1 2

QV14A

2N7002DW-7-F_SOT363-6

DIS@

61

2

LV16

BLM15BD121SN1D_0402

DIS@

1 2

T78

RV246

0_0402_5%@

1 2

T80

CV78

0.1U_0402_16V7K

DIS@

1

2

RV97

1M_0402_5%

DIS@

RV248

0_0402_5%

TH@

1 2

CV85

0.1U_0402_16V7K

CH@

1

2

CV95

18P_0402_50V8J

DIS@

QV15B

DMN66D0LDW-7_SOT363-6

TH@

3

5

4

RV251

0_0402_5%DIS@

1 2

QV15A

DMN66D0LDW-7_SOT363-6

TH@

61

2

RV221 150_0402_1%@

1 2

RV96

4.7K_0402_5%

CH@

1 2

CV81 0.1U_0402_16V7K

DIS@

12

DPA

DPB

DPC

DPD

MUTI GFX

I2C

GENERAL PURPOSE I/O

DAC1

DAC2

DDC/AUX

THERMAL

PLL/CLOCK

UV1B

THAMES XT M2

@

DMINUS

AG29

DPLL_PVDD

AM32

DPLL_PVSS

AN32

DPLL_VDDC

AN31

DPLUS

AF29

DVPCLK

AR1

DVPCNTL_0

AP8

DVPCNTL_1

AW8

DVPCNTL_2

AR3

DVPCNTL_MVP_0

AR8

DVPCNTL_MVP_1

AU8

DVPDATA_0

AU1

DVPDATA_1

AU3

DVPDATA_10

AV7

DVPDATA_11

AN7

DVPDATA_12

AV9

DVPDATA_13

AT9

DVPDATA_14

AR10

DVPDATA_15

AW10

DVPDATA_16

AU10

DVPDATA_17

AP10

DVPDATA_18

AV11

DVPDATA_19

AT11

DVPDATA_2

AW3

DVPDATA_20

AR12

DVPDATA_21

AW12

DVPDATA_22

AU12

DVPDATA_23

AP12

DVPDATA_3

AP6

DVPDATA_4

AW5

DVPDATA_5

AU5

DVPDATA_6

AR6

DVPDATA_7

AW6

DVPDATA_8

AU6

DVPDATA_9

AT7

GENERICA

AJ19

GENERICB

AK19

GENERICC

AJ20

GENERICD

AK20

GENERICE_HPD4

AJ24

GENERICF_HPD5

AH26

GENERICG_HPD6

AH24

GPIO_0

AH20

GPIO_1

AH18

GPIO_10_ROMSCK

AJ16

GPIO_11

AK16

GPIO_12

AL16

GPIO_13

AM16

GPIO_14_HPD2

AM14

GPIO_15_PWRCNTL_0

AM13

GPIO_16

AK14

GPIO_17_THERMAL_INT

AG30

GPIO_18_HPD3

AN14

GPIO_19_CTF

AM17

GPIO_2

AN16

GPIO_20_PWRCNTL_1

AL13

GPIO_21_BB_EN

AJ14

GPIO_22_ROMCSB

AK13

GPIO_23_CLKREQB

AN13

GPIO_3_SMBDATA

AH23

GPIO_4_SMBCLK

AJ23

GPIO_5_AC_BATT

AH17

GPIO_6

AJ17

GPIO_7_BLON

AK17

GPIO_8_ROMSO

AJ13

GPIO_9_ROMSI

AH15

H2SYNC/GENLK_CLK AD29

HPD1

AK24

HSYNC AC36

JTAG_TCK

AK23 JTAG_TDI

AN23

JTAG_TDO

AM24 JTAG_TMS

AL24

JTAG_TRSTB

AM23

DDCDATA_AUX7N AK29

DDCCLK_AUX7P AK30

TS_FDO

AK32

TSVDD

AJ32

TSVSS

AJ33

VREFG

AH13

VSS1DI AC34

VSS2DI/NC AG32

XTALIN

AV33

XTALOUT

AU34

A2VDD/NC AG33

A2VDDQ/NC AD33

A2VSSQ/TSVSSQ AF33

AUX1N AL27

AUX1P AM27

AUX2N AM20

AUX2P AN20

AVDD AD34

AVSSQ AE34

BAF37

B2/NC AF30

B2B/NC AF31

BB AE38

C/NC AC32

COMP/NC AF32

DDC1CLK AM26

DDC1DATA AN26

DDC2CLK AM19

DDC2DATA AL19

DDC6CLK AJ30

DDC6DATA AJ31

DDCDATA_AUX3N AM30

DDCCLK_AUX3P AL30

DDCDATA_AUX4N AM29

DDCCLK_AUX4P AL29

DDCDATA_AUX5N AM21

DDCCLK_AUX5P AN21

GAE36

G2/NC AD30

G2B/NC AD31

GB AD35

RAD39

R2/NC AC30

R2B/NC AC31

R2SET/NC AA29

RB AD37

RSET AB34

SCL

AK26

SDA

AJ26

TX0M_DPA2N AR24

TX0M_DPC2N AR14

TX0P_DPA2P AT25

TX0P_DPC2P AT15

TX1M_DPA1N AV25

TX1M_DPC1N AV15

TX1P_DPA1P AU26

TX1P_DPC1P AU16

TX2M_DPA0N AR26

TX2M_DPC0N AR16

TX2P_DPA0P AT27

TX2P_DPC0P AT17

TX3M_DPB2N AU30

TX3M_DPD2N AR20

TX3P_DPB2P AV31

TX3P_DPD2P AT21

TX4M_DPB1N AT31

TX4M_DPD1N AV21

TX4P_DPB1P AR32

TX4P_DPD1P AU22

TX5M_DPB0N AU32

TX5M_DPD0N AR22

TX5P_DPB0P AT33

TX5P_DPD0P AT23

TXCAM_DPA3N AV23

TXCAP_DPA3P AU24

TXCBM_DPB3N AT29

TXCBP_DPB3P AR30

TXCCM_DPC3N AV13

TXCCP_DPC3P AU14

TXCDM_DPD3N AT19

TXCDP_DPD3P AU20

V2SYNC/GENLK_VSYNC AC29

VDD1DI AC33

VDD2DI/NC AG31

VSYNC AC38

Y/NC AD32

TS_A/NC

AL31

XO_IN

AW34

XO_IN2

AW35

SWAPLOCKA

AJ21

SWAPLOCKB

AK21

RV218 10K_0402_5%@

1 2

RV7910K_0402_5% @

1 2

LV13

BLM15BD121SN1D_0402

DIS@

1 2

RV93 499_0402_1%

DIS@

12

CV333

0.68U_0402_10V

@

1

2

RV199

2.2K_0402_5%

@

12

RV200

0_0402_5%

@

12

CV91

10U_0603_6.3V6M

DIS@

1

2

RV232 0_0402_5%

GCLK@

1 2

CV80

10U_0603_6.3V6M

DIS@

1

2

T79

CV93

0.1U_0402_16V7K

DIS@

1

2

T81

RV220 150_0402_1%@

1 2

QV14B

2N7002DW-7-F_SOT363-6

DIS@

3

5

4

YV1

27MHZ_16PF_7V27000011

DIS@

GND

2

3

311

GND

4

RV7810K_0402_5% @

1 2

RV94 0_0402_5%@

1 2

RV247

0_0402_5%@

1 2

RV222 150_0402_1%@

1 2

RV216 10K_0402_5%@

1 2

RV238

4.75K_0402_1%

CH@

12

CV90

10P_0402_50V8J

@

1

2

CV83

1U_0402_6.3V6K

DIS@

1

2

CV76

1U_0402_6.3V6K

DIS@

1

2

RV8510K_0402_5% @

1 2

RV8110K_0402_5% DIS@

1 2

RV91

10K_0402_5%

DIS@

12

LV15

BLM15BD121SN1D_0402

DIS@

12

LV12

BLM15BD121SN1D_0402

DIS@

1 2

RV8210K_0402_5% @

1 2

RV74

4.7K_0402_5%DIS@

12

RV240

4.75K_0402_1%

CH@

12

RV71 10K_0402_5%X76@

1 2

RV242

4.75K_0402_1%

CH@

12

RV72 10K_0402_5%X76@

1 2

UV14

ADM1032ARMZ-2REEL_MSOP8

CH@

VDD

1

ALERT# 6

THERM#

4GND 5

D+

2

D-

3

SCLK 8

SDATA 7

RV98 4.7K_0402_5%

CH@

1 2

CV86

10U_0603_6.3V6M

DIS@

1

2

LV14

BLM15BD121SN1D_0402

DIS@

12

RV235

10K_0402_5%

@

12

RV8710K_0402_5% @

1 2

CV75

0.1U_0402_16V7K

DIS@

1

2

RV237

8.45K_0402_1%

@

12

CV92

1U_0402_6.3V6K

DIS@

1

2

RV241

10K_0402_5%

@

12

RV207

0_0402_5%DIS@

1 2

RV217 10K_0402_5%@

1 2

RV8310K_0402_5% @

1 2

RV236

10K_0402_5%

CH@

12

RV84 499_0402_1%DIS@

1 2

RV7610K_0402_5% DIS@

1 2

CV331

0.68U_0402_10V

CH@

1

2

RV68 10K_0402_5%X76@

1 2

RV8610K_0402_5% @

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.0V_ON#

1.0V_ON#

VDDC_ON#

RUNPWROK

PX_MODE

VDDC_ON#

PX_MODE#

PX_MODE#

PXS_PWREN#

PXS_PWREN

PXS_PWREN

PXS_PWREN#

PXS_PWREN#

PXS_PWREN#

PX_MODE

PX_MODEPXS_PWREN

VGA_PWRGD<17,52>

PX_MODE <24,52,53>

PXS_PWREN<16,52>

PX_EN<37>

+3VGS

+1.0VGS

+VGA_CORE

+BIF_VDDC

+5VS+5VS

+3VGS

+3VGS

+1.5V +1.5VGS

B+_BIAS

+3VS +3VGS

+5VALW

+3VALW

+3VALW

+3VGS

+1.8VS +1.8VGS

B+_BIAS

+VGA_CORE

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

ATI_SeymourXT_M2_BACO POWER

C

36 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

+1.5VS TO +1.5VGS

+3.3VS TO +3.3VGS

55mA@1.0V, in BACO mode

60mil

60mil

60mil

Circuits to support BACO

PX_MODE=1 for Normal Operation

PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

Switch circuits in BACO desingns for Thanes/Seymour only

+1.8VS TO +1.8VGS

for PX4.0

for PX4.0 and PX5.0

Power Seguence of Thames and Chelsea

+3VGS

+VGA_CORE

+VDDCI

+1.5VGS

+1.0VGS

+1.8VGS <20ms

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON

PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF

Note:

PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

for PX5.0

for PX5.0

60mil

RV105

20K_0402_5%

DIS@

12

RV233 0_0402_5%

DIS@

1 2

CV98

0.1U_0402_16V7K

@

1

2

CV2

0.1U_0603_25V7K

DIS@

1

2

CV97

22U_0805_6.3V6MDIS@

1

2

RV104

5.11K_0402_1%

DIS@

12

RV112

20K_0402_5%

DIS@

RV212

0_0402_5%

@

1 2

DV12

RB751V_SOD323

@

21

JP9

2MM

@

2 1

RV100

10K_0402_5%

CH@

12

RV111

470_0603_5%

@

12

UV35

DMN3030LSS-13_SOP8L-8

DIS@

36

5

7

8

2

4

1

G

D

S

QV10

2N7002H_SOT23-3

DIS@

2

13

G

D

S

QV29

2N7002H_SOT23-3

@

2

13

RV113

300K_0402_5%

DIS@

1 2

UV17

AO4304L_SO8

DIS@

6

2

4

1

3

5

7

8

RV108

1K_0402_5%

DIS@

CV106

1U_0603_10V6K

DIS@

1

2

G

D

S

QV21

2N7002K_SOT23-3

DIS@

2

13

CV102

1U_0603_10V6K

DIS@

1

2

RV114

100K_0402_5%

DIS@

12

RV117

100K_0402_5%

DIS@

12

CV100

1U_0603_10V6K

@

1

2

RV116 0_0402_5%

@

1 2

CV101

10U_0603_6.3V6M

DIS@

1

2

CV103

0.1U_0603_25V7K

DIS@

1

2

QV27B

DMN66D0LDW-7_SOT363-6

DIS@

34

5

G

D

S

QV24

2N7002H_SOT23-3

DIS@

2

13

RV109

100K_0402_5%

DIS@

12

G

D

S

QV16

AO3416_SOT23-3

CH@

2

13

RV234

0_0603_5%TH@

1 2

UV15

MC74VHC1G08DFT2G SC70 5P

@

B

2

A

1Y4

P5

G

3

G

D

S

QV26

2N7002K_SOT23-3

@

2

13

G

D

S

QV20

AO3416_SOT23-3

@

2

13

RV214

0_0402_5%@

1 2

QV18A

DMN66D0LDW-7_SOT363-6

@

1

2

6

UV16

MC74VHC1G08DFT2G SC70 5P

@

B

2

A

1Y4

P5

G

3

RV106

470_0603_5%

@

12

G

D

S

QV23

2N7002K_SOT23-3

@

2

13

G

D

S

QV19

AO3416_SOT23-3

@

2

13

JP8

2MM

@

2 1

RV128

330K_0402_5%

DIS@

12

QV18B

DMN66D0LDW-7_SOT363-6

@

34

5

G

D

S

QV25

2N7002_SOT23

DIS@

2

13

CV99

0.1U_0402_16V7K

@

1 2

RV249

0_0805_5%@

1 2

J92MM

@

2 1

RV213

470_0603_5%

@

12

RV211

470K_0402_5%DIS@

1 2

CV96

0.1U_0402_16V7K

@

1

2

RV99

10K_0402_5%

@

12

QV27A

DMN66D0LDW-7_SOT363-6

DIS@

1

2

6

G

D

S

QV17

AO3416_SOT23-3

CH@

2

13

CV105

10U_0603_6.3V6M

DIS@

1

2

RV115

0_0402_5%

@

1 2

CV104

10U_0603_6.3V6M

DIS@

1

2

RV101

10K_0402_5%

DIS@

1 2

QV22

AP2301GN-HF_SOT23-3

DIS@

2

3 1

RV103

0_0805_5%CH@

1 2

CV321

1U_0603_10V6K

DIS@

1

2

RV107

20K_0402_5%

DIS@

CV107

0.1U_0603_25V7K

DIS@

1

2

CV320

10U_0805_10V6K

DIS@

1

2

RV102

0_0402_5%

DIS@

1 2

RV110

0_0402_5%@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+DPCD_VDD18

+DPEF_VDD10

MECH#1

MECH#2

MECH#3

+DPAB_VDD18

+DPAB_VDD10

+DPEF_VDD18

+DPCD_VDD10

PS_0

PS_0

PX_EN <36>

+1.8VGS

+1.0VGS

+DPEF_VDD10

+1.0VGS

+1.8VGS

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

+DPAB_VDD18

+DPCD_VDD18

+DPCD_VDD18

+DPEF_VDD18

+DPEF_VDD18

+DPCD_VDD10

+DPCD_VDD18

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD10

+DPEF_VDD18

+DPEF_VDD10

+1.8VGS

+DPEF_VDD18

+1.0VGS +DPCD_VDD10

+DPAB_VDD18

+DPAB_VDD10

+1.8VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

ATI_SetmourXT_M2_PWR_GND

C

37 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

130mA

130mA

110mA

110mA

20mA

20mA

1.8V@300mA DPAB_VDD18)

(1.0V@220mA DPAB_VDD10)

1.8V@300mA DPCD_VDD18)

1.0V@220mA DPCD_VDD10)

1.8V@300mA DPEF_VDD18)

1.0V@240mA DPEF_VDD10)

(Thames 330mA)

(Thames 220mA)

(Thames 330mA)

Thames/Seymour Only

Do not install for Heathrow/Chelsea

PS_0 Should be tied to GND on Thames/Seymour

(Thames 220mA)

(Thames 330mA)

(Thames 330mA)

20mil

20mil

20mil

20mil

20mil

20mil

20mil

20mil

20mA

20mA

20mA

20mA

10mil

10mil

10mil

10mil

10mil

10mil

20mil

20mil

20mil

20mil

0.935V@Chelsea

0.935V@Chelsea

0.935V@Chelsea

PS0:

PS1:

PS2:

PS3:

11001

11000

00000

11000

MLPS Bit AMD recommended setting

RV243=8.45K

RV237=NC

RV239=NC

RV241=NC

RV201=2K CV335=NC

RV238=4.75K CV329=NC

RV240=4.75K CV331=0.68u

RV242=4.75K CV333=NC

R_PU R_PD Cstrap

CV109

1U_0402_6.3V6K

@

1

2

CV121

1U_0402_6.3V6K

@

1

2

CV112

1U_0402_6.3V6K

@

1

2

CV117

10U_0603_6.3V6M

@

1

2

RV121

0_0402_5%

DIS@

1 2

RV125

4.7K_0402_5%

DIS@

12

CV124

1U_0402_6.3V6K

@

1

2

CV108

0.1U_0402_16V7K

@

1

2

RV124

0_0402_5%

DIS@

1 2

CV116

10U_0603_6.3V6M

@

1

2

CV113

0.1U_0402_16V7K

@

1

2

CV118

1U_0402_6.3V6K

@

1

2

RV127

150_0402_1%

DIS@

12

RV201

2K_0402_1%

CH@

CV119

0.1U_0402_16V7K

@

1

2

CV120

10U_0603_6.3V6M

@

1

2

T83 PAD

CV123

10U_0603_6.3V6M

@

1

2

RV120

0_0402_5%

DIS@

1 2

RV126

0_0402_5%

DIS@

1 2

CV110

10U_0603_6.3V6M

@

1

2

RV201

0_0402_5%

TH@

12

DP PLL POWER

DP A/B POWER

DP C/D POWER

DP E/F POWER

UV1H

THAMES XT M2

@

DPAB_VDD18/DPA_PVDD AU28

DP_VSSR/DPA_PVSS AV27

DPAB/DPA_VDD10#1 AP31

DPAB/DPA_VDD10#2 AP32

DPAB/DPA_VDD18#1 AN24

DPAB/DPA_VDD18#2 AP24

DP/DPA_VSSR#1 AN27

DP/DPA_VSSR#2 AP27

DP/DPA_VSSR#3 AP28

DP/DPA_VSSR#4 AW24

DP/DPA_VSSR#5 AW26

DPAB_CALR AW28

DPAB_VDD18/DPB_PVDD AV29

DP_VSSR/DPB_PVSS AR28

DPAB/DPB_VDD10#1 AN33

DPAB/DPB_VDD10#2 AP33

DPAB/DPB_VDD18#1 AP25

DPAB/DPB_VDD18#2 AP26

DP/DPB_VSSR#1 AN29

DP/DPB_VSSR#2 AP29

DP/DPB_VSSR#3 AP30

DP/DPB_VSSR#4 AW30

DP/DPB_VSSR#5 AW32

DPCD_VDD18/DPC_PVDD AU18

DP_VSSR/DPC_PVSS AV17

DPCD/DPC_VDD10#1

AP13

DPCD/DPC_VDD10#2

AT13

DPCD/DPC_VDD18#1

AP20

DPCD/DPC_VDD18#2

AP21

DP/DPC_VSSR#1

AN17

DP/DPC_VSSR#2

AP16

DP/DPC_VSSR#3

AP17

DP/DPC_VSSR#4

AW14

DP/DPC_VSSR#5

AW16

DPCD_CALR

AW18

DPCD_VDD18/DPD_PVDD AV19

DP_VSSR/DPD_PVSS AR18

DPCD/DPD_VDD10#1

AP14

DPCD/DPD_VDD10#2

AP15

DPCD/DPD_VDD18#1

AP22

DPCD/DPD_VDD18#2

AP23

DP/DPD_VSSR#1

AN19

DP/DPD_VSSR#2

AP18

DP/DPD_VSSR#3

AP19

DP/DPD_VSSR#4

AW20

DP/DPD_VSSR#5

AW22

DPEF_VDD18/DPE_PVDD AM37

DP_VSSR/DPE_PVSS AN38

DPEF/DPE_VDD10#1

AL33

DPEF/DPE_VDD10#2

AM33

DPEF/DPE_VDD18#1

AH34

DPEF/DPE_VDD18#2

AJ34

DP/DPE_VSSR#1

AN34

DP/DPE_VSSR#2

AP39

DP/DPE_VSSR#3

AR39

DP/DPE_VSSR#4

AU37

DPEF_CALR

AM39

DPEF_VDD18/DPF_PVDD AL38

DP_VSSR/DPF_PVSS AM35

DPEF/DPF_VDD10#1

AK33

DPEF/DPF_VDD10#2

AK34

DPEF/DPF_VDD18#1

AF34

DPEF/DPF_VDD18#2

AG34

DP/DPF_VSSR#1

AF39

DP/DPF_VSSR#2

AH39

DP/DPF_VSSR#3

AK39

DP/DPF_VSSR#4

AL34

DP/DPF_VSSR#5

AM34

T82 PAD

CV335

0.68U_0402_10V

@

1

2

RV123 150_0402_1%DIS@

1 2

RV243

8.45K_0402_1%

CH@

12

RV122150_0402_1% DIS@

12

RV119

0_0402_5%

DIS@

1 2

GND

UV1F

THAMES XT M2

@

PCIE_VSS#1

AB39

PCIE_VSS#10

J31

PCIE_VSS#11

J34

PCIE_VSS#12

K31

PCIE_VSS#13

K34

PCIE_VSS#14

K39

PCIE_VSS#15

L31

PCIE_VSS#16

L34

PCIE_VSS#17

M34

PCIE_VSS#18

M39

PCIE_VSS#19

N31

PCIE_VSS#2

E39

PCIE_VSS#20

N34

PCIE_VSS#21

P31

PCIE_VSS#22

P34

PCIE_VSS#23

P39

PCIE_VSS#24

R34

PCIE_VSS#25

T31

PCIE_VSS#26

T34

PCIE_VSS#27

T39

PCIE_VSS#28

U31

PCIE_VSS#29

U34

PCIE_VSS#3

F34

PCIE_VSS#30

V34

PCIE_VSS#31

V39

PCIE_VSS#32

W31

PCIE_VSS#33

W34

PCIE_VSS#34

Y34

PCIE_VSS#35

Y39

PCIE_VSS#4

F39

PCIE_VSS#5

G33

PCIE_VSS#6

G34

PCIE_VSS#7

H31

PCIE_VSS#8

H34

PCIE_VSS#9

H39

VSS_MECH#1 A39

VSS_MECH#2 AW1

VSS_MECH#3 AW39

GND#1 A3

GND#10 AA6

GND#98 F13

GND#100

F15

GND#101

F17

GND#102

F19

GND#103

F21

GND#104

F23

GND#105

F25

GND#106

F27

GND#107

F29

GND#108

F31

GND#11 AB12

GND#109

F33

GND#110

F7

GND#111

F9

GND#112

G2

GND#113

G6

GND#114

H9

GND#115

J2

GND#116

J27

GND#117

J6

GND#118

J8

GND#12 AB15

GND#119

K14

GND#120

K7

GND#121

L11

GND#122

L17

GND#123

L2

GND#124

L22

GND#125

L24

GND#126

L6

GND#127

M17

GND#128

M22

GND#13 AB17

GND#129

M24

GND#130

N16

GND#131

N18

GND#132

N2

GND#133

N21

GND#134

N23

GND#135

N26

GND#136

N6

GND#137

R15

GND#138

R17

GND#14 AB20

GND#139

R2

GND#140

R20

GND#141

R22

GND#142

R24

GND#143

R27

GND#144

R6

GND#145

T11

GND#146

T13

GND#147

T16

GND#148

T18

GND#15 AB22

GND#149

T21

GND#150

T23

GND#151

T26

GND#153

U15

GND#154

U17

GND#155

U2

GND#156

U20

GND#157

U22

GND#158

U24

GND#159

U27

GND#16 AB24

GND#160

U6

GND#161

V11

GND#163

V16

GND#164

V18

GND#165

V21

GND#166

V23

GND#167

V26

GND#168

W2

GND#169

W6

GND#170

Y15

GND#17 AB27

GND#171

Y17

GND#172

Y20

GND#173

Y22

GND#174

Y24

GND#175

Y27

GND#18 AC11

GND#19 AC13

GND#2 A37

GND#20 AC16

GND#21 AC18

GND#22 AC2

GND#23 AC21

GND#24 AC23

GND#25 AC26

GND#26 AC28

GND#27 AC6

GND#28 AD15

GND#29 AD17

GND#3 AA16

GND#30 AD20

GND#31 AD22

GND#32 AD24

GND#33 AD27

GND#34 AD9

GND#35 AE2

GND#36 AE6

GND#37 AF10

GND#38 AF16

GND#39 AF18

GND#4 AA18

GND#40 AF21

GND#41 AG17

GND#42 AG2

GND#43 AG20

GND#44 AG22

GND#45 AG6

GND#46 AG9

GND#47 AH21

GND#48 AJ10

GND#5 AA2

GND#49 AJ11

GND#50 AJ2

GND#51 AJ28

GND#52 AJ6

GND#53 AK11

GND#54 AK31

GND#55 AK7

GND#56 AL11

GND#57 AL14

GND#58 AL17

GND#6 AA21

GND#59 AL2

GND#60 AL20

GND/PX_EN#61 AL21

GND#62 AL23

GND#63 AL26

GND#64 AL32

GND#65 AL6

GND#66 AL8

GND#67 AM11

GND#68 AM31

GND#7 AA23

GND#69 AM9

GND#70 AN11

GND#71 AN2

GND#72 AN30

GND#73 AN6

GND#74 AN8

GND#75 AP11

GND#76 AP7

GND#77 AP9

GND#78 AR5

GND#8 AA26

GND#79 B11

GND#80 B13

GND#81 B15

GND#82 B17

GND#83 B19

GND#84 B21

GND#85 B23

GND#86 B25

GND#87 B27

GND#9 AA28

GND#88 B29

GND#89 B31

GND#90 B33

GND#91 B7

GND#92 B9

GND#93 C1

GND#94 C39

GND#95 E35

GND#96 E5

GND#97 F11

GND#152

U13

GND#162

V13

RV118

0_0402_5%

DIS@

1 2

CV122

0.1U_0402_16V7K

@

1

2

T84 PAD

CV114

0.1U_0402_16V7K

@

1

2

CV115

1U_0402_6.3V6K

@

1

2

CV111

10U_0603_6.3V6M

@

1

2

CV125

0.1U_0402_16V7K

@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+PCIE_PVDD

+VDDR4

+PCIE_VDDR

+MPV18

+SPV18

+SPV10

VGA_CORE_SEN

VDDCI_SEN

VSSSENSE_VGA

+PCIE_VDDR

VCCSENSE_VGA<52>

VDDCI_SEN<53>

VSSSENSE_VGA<52>

+1.8VGS

+VDDCI

+1.8VGS +VDDC_CT

+1.0VGS

+1.0VGS

+1.5VGS

+1.8VGS

+3VGS

+1.8VGS

+1.8VGS

+VGA_CORE

+BIF_VDDC

+VGA_CORE

+VGA_CORE

+1.5VGS

+1.8VGS

+VGA_CORE

+VGA_CORE

+VDDCI

+BIF_VDDC

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

ATI_SeymourXT_M2_Power

C

38 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

For DDR3 MVDDQ = 1.5V

(M97, Broadway and Madison: 1.8V@150mA MPV18)

(1.8V@75mA SPV18)

(120mA SPV10)

(1.8V@110mA VDD_CT)

(1.8V@504mA PCIE_VDDR)

(1.0V@1920mA PCIE_VDDC)

For non-BACO designs, connect BIF_VDDC to VDDC.

For BACO designs - see BACO reference schematics

(GDDR3/DDR3 1.12V@4A VDDCI)

For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

(GDDR5 1.12V@16A VDDCI)

VDDCI and VDDC should have seperate regulators with a merge option on PCB

4A

(1.8V@40mA PCIE_PVDD)

55mA

(Thames 1.7)A

(Thames 250mA)

(Thames 60mA)

(Thames 150mA)

(Thames 50mA)

(Thames 100mA)

(Thames 20.5A)

(Thames 1.1A)

40mA

(Thames 440mA)

10mil

10mil

20mil

20mil

10mil

20mil

10mil

20mil

40mil Add 12/8

(0.935V@2.5A PCIE_VDDC)

(Chelsea)

0.935V@Chelsea

CV157

1U_0402_6.3V6K

DIS@

1

2

CV175

1U_0402_6.3V6K

DIS@

1

2

CV138

10U_0603_6.3V6M

DIS@

1

2

CV167

1U_0402_6.3V6K

DIS@

1

2

LV23

MCK1608471YZF 0603

DIS@

1 2

+

CV135

220U_B2_2.5VM_R35

@

1

2

CV186

1U_0402_6.3V6K

DIS@

1

2

LV22

BLM15BD121SN1D_0402

DIS@

1 2

CV133

1U_0402_6.3V6K

DIS@

1

2

CV209

1U_0402_6.3V6K

DIS@

1

2

CV180

1U_0402_6.3V6K

DIS@

1

2

CV143

1U_0402_6.3V6K

DIS@

1

2

CV214

22U_0603_6.3V6M

DIS@

1

2

CV177

1U_0402_6.3V6K

DIS@

1

2

CV170

10U_0603_6.3V6M

DIS@

1

2

CV161

1U_0402_6.3V6K

DIS@

1

2

RV202

10_0402_1%

DIS@

12

CV158

1U_0402_6.3V6K

DIS@

1

2

LV19

BLM15BD121SN1D_0402

DIS@

1 2

CV200

10U_0603_6.3V6M

DIS@

1

2

CV141

1U_0402_6.3V6K

DIS@

1

2

CV140

10U_0603_6.3V6M

DIS@

1

2

LV20

BLM15BD121SN1D_0402

DIS@

1 2

CV198

1U_0402_6.3V6K

DIS@

1

2

CV176

1U_0402_6.3V6K

DIS@

1

2

CV147

1U_0402_6.3V6K

DIS@

1

2

CV182

1U_0402_6.3V6K

DIS@

1

2

+

CV327

330U_D2_2VM_R6M~D

DIS@

1

2

LV25

BLM15BD121SN1D_0402

@

1 2

CV183

1U_0402_6.3V6K

DIS@

1

2

CV212

1U_0402_6.3V6K

DIS@

1

2

CV181

1U_0402_6.3V6K

DIS@

1

2

CV136

10U_0603_6.3V6M

DIS@

1

2

CV139

10U_0603_6.3V6M

DIS@

1

2

CV126

0.1U_0402_16V7K

DIS@

1

2

CV156

0.1U_0402_16V7K

DIS@

1

2

CV189

1U_0402_6.3V6K

DIS@

1

2

RV245

0_0402_5%@

1 2

CV190

1U_0402_6.3V6K

DIS@

1

2

CV204

1U_0402_6.3V6K

DIS@

1

2

CV211

1U_0402_6.3V6K

DIS@

1

2

LV26

BLM15BD121SN1D_0402

@

1 2

CV145

1U_0402_6.3V6K

DIS@

1

2

CV178

1U_0402_6.3V6K

DIS@

1

2

CV130

1U_0402_6.3V6K

DIS@

1

2

CV206

1U_0402_6.3V6K

DIS@

1

2

LV21

MCK1608471YZF 0603

DIS@

1 2

CV168

1U_0402_6.3V6K

DIS@

1

2

CV193

1U_0402_6.3V6K

DIS@

1

2

CV129

1U_0402_6.3V6K

DIS@

1

2

CV213

10U_0603_6.3V6M

DIS@

1

2

CV187

10U_0603_6.3V6M

DIS@

1

2

CV192

22U_0603_6.3V6M

DIS@

1

2

CV132

0.1U_0402_16V7K

DIS@

1

2

CV131

10U_0603_6.3V6M

DIS@

1

2

CV208

1U_0402_6.3V6K

DIS@

1

2

CV144

1U_0402_6.3V6K

DIS@

1

2

CV172

1U_0402_6.3V6K

DIS@

1

2

CV199

0.1U_0402_16V7K

DIS@

1

2

CV150

1U_0402_6.3V6K

DIS@

1

2

CV203

1U_0402_6.3V6K

DIS@

1

2

CV179

1U_0402_6.3V6K

DIS@

1

2

RV204

10_0402_1%DIS@

12

CV151

10U_0603_6.3V6M

DIS@

1

2

CV128

1U_0402_6.3V6K

DIS@

1

2

CV194

0.1U_0402_16V7K

DIS@

1

2

CV207

1U_0402_6.3V6K

DIS@

1

2

CV142

1U_0402_6.3V6K

DIS@

1

2

CV205

1U_0402_6.3V6K

DIS@

1

2

CV146

1U_0402_6.3V6K

DIS@

1

2

CV164

1U_0402_6.3V6K

DIS@

1

2

CV184

1U_0402_6.3V6K

DIS@

1

2

CV191

10U_0603_6.3V6M

DIS@

1

2

CV160

1U_0402_6.3V6K

DIS@

1

2

CV323

10U_0603_6.3V6M

DIS@

1

2

CV155

0.1U_0402_16V7K

DIS@

1

2

CV216

1U_0402_6.3V6K

DIS@

1

2

LV17

MBK1608121YZF_0603

DIS@

12

LV18

MBK1608121YZF_0603

DIS@

12

CV137

10U_0603_6.3V6M

DIS@

1

2

CV202

0.1U_0402_16V7K

DIS@

1

2

CV127

0.1U_0402_16V7K

DIS@

1

2

CV196

1U_0402_6.3V6K

DIS@

1

2

CV217

0.1U_0402_16V7K

DIS@

1

2

CV134

10U_0603_6.3V6M

DIS@

1

2

CV163

1U_0402_6.3V6K

DIS@

1

2

CV210

1U_0402_6.3V6K

DIS@

1

2

CV169

1U_0402_6.3V6K

DIS@

1

2

CV154

0.1U_0402_16V7K

DIS@

1

2

CV148

1U_0402_6.3V6K

DIS@

1

2

CV325

1U_0402_6.3V6K

DIS@

1

2

CV195

1U_0402_6.3V6K

DIS@

1

2

CV171

1U_0402_6.3V6K

DIS@

1

2

CV173

1U_0402_6.3V6K

DIS@

1

2

RV215

10_0402_1%

DIS@

12

CV201

1U_0402_6.3V6K

DIS@

1

2

CV152

0.1U_0402_16V7K

DIS@

1

2

CV166

1U_0402_6.3V6K

DIS@

1

2

RV244

0_0402_5%TH@

1 2

CV159

1U_0402_6.3V6K

DIS@

1

2

POWER

PLL

PCIE

CORE

MEM I/O

I/O

LEVEL

TRANSLATION

ISOLATED

CORE I/O

VOLTAGE

SENESE

UV1E

THAMES XT M2

@

PCIE_VDDR/PCIE_PVDD AB37

MPV18#1

H7

MPV18#2

H8

SPV18

AM10

PCIE_VDDC#1 G30

PCIE_VDDC#10 R28

PCIE_VDDC#11 T28

PCIE_VDDC#12 U28

PCIE_VDDC#2 G31

PCIE_VDDC#3 H29

PCIE_VDDC#4 H30

PCIE_VDDC#5 J29

PCIE_VDDC#6 J30

PCIE_VDDC#7 L28

PCIE_VDDC#8 M28

PCIE_VDDC#9 N28

PCIE_VDDR#1 AA31

PCIE_VDDR#2 AA32

PCIE_VDDR#3 AA33

PCIE_VDDR#4 AA34

PCIE_VDDR#5 V28

PCIE_VDDR#6 W29

PCIE_VDDR#7 W30

PCIE_VDDR#8 Y31

SPV10

AN9

SPVSS

AN10

VDDR1#1

AC7

VDDR1#10

G17

VDDR1#11

G20

VDDR1#12

G23

VDDR1#13

G26

VDDR1#14

G29

VDDR1#15

H10

VDDR1#16

J7

VDDR1#17

J9

VDDR1#18

K11

VDDR1#19

K13

VDDR1#2

AD11

VDDR1#20

K8

VDDR1#21

L12

VDDR1#22

L16

VDDR1#23

L21

VDDR1#24

L23

VDDR1#25

L26

VDDR1#26

L7

VDDR1#27

M11

VDDR1#28

N11

VDDR1#29

P7

VDDR1#3

AF7

VDDR1#30

R11

VDDR1#31

U11

VDDR1#32

U7

VDDR1#33

Y11

VDDR1#34

Y7

VDDR1#4

AG10

VDDR1#5

AJ7

VDDR1#6

AK8

VDDR1#7

AL9

VDDR1#8

G11

VDDR1#9

G14

VDDR3#1

AF23

VDDR3#2

AF24

VDDR3#3

AG23

VDDR3#4

AG24

VDDR4#4

AF13

VDDR4#5

AF15

VDDR4#7

AG13

VDDR4#8

AG15

VDDR4#1

AD12

VDDR4#2

AF11

VDDR4#3

AF12

VDDR4#6

AG11

NC_VDDRHA

M20

NC_VDDRHB

V12

NC_VSSRHA

M21

NC_VSSRHB

U12

VDD_CT#1

AF26

VDD_CT#2

AF27

VDD_CT#3

AG26

VDD_CT#4

AG27

VDDC#1 AA15

VDDC#9 AB21

VDDC#10 AB23

VDDC#11 AB26

VDDC#12 AB28

VDDCI#3 AC12

VDDCI#4 AC15

VDDC#13 AC17

VDDC#14 AC20

VDDC#15 AC22

VDDC#16 AC24

VDDC#2 AA17

VDDC#17 AC27

VDDCI#5 AD13

VDDCI#6 AD16

VDDC#18 AD18

VDDC#19 AD21

VDDC#20 AD23

VDDC#21 AD26

VDDC#22 AF17

VDDC#23 AF20

VDDC#24 AF22

VDDC#3 AA20

VDDC#25 AG16

VDDC#26 AG18

VDDC#27 AG21

VDDC#28 AH22

VDDCI#8 M16

VDDCI#9 M18

VDDCI#10 M23

VDDC#31 M26

VDDCI#12 N15

VDDCI#13 N17

VDDC#4 AA22

VDDCI#14 N20

VDDCI#15 N22

VDDC#32 N24

VDDC/BIF_VDDC#33 N27

VDDCI#17 R13

VDDCI#18 R16

VDDC#34 R18

VDDC#35 R21

VDDC#36 R23

VDDC#37 R26

VDDC#5 AA24

VDDCI#20 T15

VDDC#38 T17

VDDC#39 T20

VDDC#40 T22

VDDC#41 T24

VDDC/BIF_VDDC#42 T27

VDDC#43 U16

VDDC#44 U18

VDDC#45 U21

VDDC#46 U23

VDDC#6 AA27

VDDC#47 U26

VDDCI#21 V15

VDDC#48 V17

VDDC#49 V20

VDDC#50 V22

VDDC#51 V24

VDDC#52 V27

VDDC#53 Y16

VDDC#54 Y18

VDDC#55 Y21

VDDCI#2 AB13

VDDC#56 Y23

VDDC#57 Y26

VDDC#58 Y28

VDDC#7 AB16

VDDC#8 AB18

VDDCI#7 M15

VDDCI#11 N13

VDDCI#16 R12

VDDCI#19 T12

VDDCI#1 AA13

VDDCI#22 Y13

VDDC#29 AH27

VDDC#30 AH28

FB_VDDC

AF28

FB_VDDCI

AG28

FB_GND

AH29

CV322

10U_0603_6.3V6M

DIS@

1

2

CV324

10U_0603_6.3V6M

DIS@

1

2

CV185

1U_0402_6.3V6K

DIS@

1

2

CV162

1U_0402_6.3V6K

DIS@

1

2

CV174

0.1U_0402_16V7K

DIS@

1

2

CV165

1U_0402_6.3V6K

DIS@

1

2

CV149

1U_0402_6.3V6K

DIS@

1

2

CV197

10U_0603_6.3V6M

DIS@

1

2

CV153

0.1U_0402_16V7K

DIS@

1

2

CV188

1U_0402_6.3V6K

DIS@

1

2

CV215

10U_0603_6.3V6M

DIS@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MDA[0..63] MDB[0..63]

MAA[12..0] MAB[12..0]

A_BA[2..0] B_BA[2..0]

+VDD_MEM15_REFSA

+VDD_MEM15_REFSA

+VDD_MEM15_REFSB

+VDD_MEM15_REFSB

+VDD_MEM15_REFDA

+VDD_MEM15_REFDA

+VDD_MEM15_REFDB

+VDD_MEM15_REFDB

A_BA0

A_BA1

A_BA2

B_BA0

B_BA1

B_BA2

CASA0#

CASA1#

CASB0#

CASB1#

CKEA0

CKEA1

CKEB0

CKEB1

CLKA0

CLKA0#

CLKA1

CLKA1#

CLKB0

CLKB0#

CLKB1

CLKB1#

CSA0#_0

CSA1#_0

CSB0#_0

CSB1#_0

DQMA#0

DQMA#1

DQMA#2

DQMA#3

DQMA#4

DQMA#5

DQMA#6

DQMA#7

DQMB#0

DQMB#1

DQMB#2

DQMB#3

DQMB#4

DQMB#5

DQMB#6

DQMB#7

DRAM_RST#_R

DRAM_RST#_R

MAA0

MAA1

MAA10

MAA11

MAA12

MAA13

MAA14

MAA2

MAA3

MAA4

MAA5

MAA6

MAA7

MAA8

MAA9

MAB0

MAB1

MAB10

MAB11

MAB12

MAB13

MAB14

MAB2

MAB3

MAB4

MAB5

MAB6

MAB7

MAB8

MAB9

MDA0

MDA1

MDA10

MDA11

MDA12

MDA13

MDA14

MDA15

MDA16

MDA17

MDA18

MDA19

MDA2

MDA20

MDA21

MDA22

MDA23

MDA24

MDA25

MDA26

MDA27

MDA28

MDA29

MDA3

MDA30

MDA31

MDA32

MDA33

MDA34

MDA35

MDA36

MDA37

MDA38

MDA39

MDA4

MDA40

MDA41

MDA42

MDA43

MDA44

MDA45

MDA46

MDA47

MDA48

MDA49

MDA5

MDA50

MDA51

MDA52

MDA53

MDA54

MDA55

MDA56

MDA57

MDA58

MDA59

MDA6

MDA60

MDA61

MDA62

MDA63

MDA7

MDA8

MDA9

MDB0

MDB1

MDB10

MDB11

MDB12

MDB13

MDB14

MDB15

MDB16

MDB17

MDB18

MDB19

MDB2

MDB20

MDB21

MDB22

MDB23

MDB24

MDB25

MDB26

MDB27

MDB28

MDB29

MDB3

MDB30

MDB31

MDB32

MDB33

MDB34

MDB35

MDB36

MDB37

MDB38

MDB39

MDB4

MDB40

MDB41

MDB42

MDB43

MDB44

MDB45

MDB46

MDB47

MDB48

MDB49

MDB5

MDB50

MDB51

MDB52

MDB53

MDB54

MDB55

MDB56

MDB57

MDB58

MDB59

MDB6

MDB60

MDB61

MDB62

MDB63

MDB7

MDB8

MDB9

ODTA0

ODTA1

ODTB0

ODTB1

QSA#0

QSA#1

QSA#2

QSA#3

QSA#4

QSA#5

QSA#6

QSA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7

QSB#0

QSB#1

QSB#2

QSB#3

QSB#4

QSB#5

QSB#6

QSB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7

RASA0#

RASA1#

RASB0#

RASB1#

TESTEN

WEA0#

WEA1#

WEB0#

WEB1#

B_BA[2..0] <41>

QSB#[7..0] <41>

QSB[7..0] <41>

CLKB1 <41>

CLKB0 <41>

MAB[12..0] <41>

DQMB#[7..0] <41>

RASB0# <41>

CKEB0 <41>

CLKB1# <41>

CLKB0# <41>

CSB0#_0 <41>

WEB0# <41>

CASB0# <41>

CKEB1 <41>

CSB1#_0 <41>

RASB1# <41>

ODTB1 <41>

ODTB0 <41>

WEB1# <41>

CASB1# <41>

DRAM_RST#<40,41>

MAB13 <41>

A_BA[2..0] <40>

QSA#[7..0] <40>

QSA[7..0] <40>

CLKA1 <40>

CLKA0 <40>

MAA[12..0] <40>

DQMA#[7..0] <40>

RASA0# <40>

CLKA1# <40>

CLKA0# <40>

CSA0#_0 <40>

WEA0# <40>

CASA0# <40>

CSA1#_0 <40>

RASA1# <40>

ODTA1 <40>

ODTA0 <40>

WEA1# <40>

CASA1# <40>

MAA13 <40>

MAA14 <40> MAB14 <41>

CKEA0 <40>

CKEA1 <40>

MDA[0..63]<40> MDB[0..63]<41>

+1.5VGS

+1.5VGS +1.5VGS

+1.5VGS

+1.5VGS +1.5VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

ATI_SeymourXT_M2_MEM IF

C

39 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

LA-8241P

route 50ohms single-ended/100ohms diff

and keep short

Debug only, for clock observation, if not needed, DNI

5mil 5mil

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These

Capacitors and Resistor values are an example only. The Series R and

|| Cap values will depend on the DRAM load and will have to be

calculated for different Memory ,DRAM Load and board to pass Reset

Signal Spec.

Place all these components very close to GPU (Within

25mm) and keep all component close to each Other (within

5mm) except Rser2

Co-lay Thames/Seymour/Chelsea

@

POP

POP

RV130

POP

RV131

RV132

@

POP

RV134

@

POP

RV135

@

Thames M2

@

Seymour M2

@

Chelsea M2

RV129

POP

@

RV206

@

@

POPRV205

@

@

@

@

@

@

@

POP

CV223

0.1U_0402_16V7K

DIS@

12

RV133

5.11K_0402_1%

DIS@

1 2

RV206 120_0402_5%CH@

1 2

CV222

120P_0402_50V9

DIS@

12

CV219

@

0.1U_0402_16V7K

12

CV220

0.1U_0402_16V7K

DIS@

12

CV224

0.1U_0402_16V7K

DIS@

12

RV146

100_0402_1%

DIS@

12

RV135 240_0402_1%DIS@

1 2

MEMORY INTERFACE B

DDR2

GDDR5/GDDR3

DDR3

DDR2

GDDR3/GDDR5

DDR3

GDDR5

GDDR5/DDR2/GDDR3

UV1D

THAMES XT M2

@

DQB0_0/DQB_0

C5

DQB0_1/DQB_1

C3

DQB0_10/DQB_10

J4

DQB0_11/DQB_11

K6

DQB0_12/DQB_12

K5

DQB0_13/DQB_13

L4

DQB0_14/DQB_14

M6

DQB0_15/DQB_15

M1

DQB0_16/DQB_16

M3

DQB0_17/DQB_17

M5

DQB0_18/DQB_18

N4

DQB0_19/DQB_19

P6

DQB0_2/DQB_2

E3

DQB0_20/DQB_20

P5

DQB0_21/DQB_21

R4

DQB0_22/DQB_22

T6

DQB0_23/DQB_23

T1

DQB0_24/DQB_24

U4

DQB0_25/DQB_25

V6

DQB0_26/DQB_26

V1

DQB0_27/DQB_27

V3

DQB0_28/DQB_28

Y6

DQB0_29/DQB_29

Y1

DQB0_3/DQB_3

E1

DQB0_30/DQB_30

Y3

DQB0_31/DQB_31

Y5

DQB1_0/DQB_32

AA4

DQB1_1/DQB_33

AB6

DQB1_2/DQB_34

AB1

DQB1_3/DQB_35

AB3

DQB1_4/DQB_36

AD6

DQB1_5/DQB_37

AD1

DQB1_6/DQB_38

AD3

DQB1_7/DQB_39

AD5

DQB0_4/DQB_4

F1

DQB1_8/DQB_40

AF1

DQB1_9/DQB_41

AF3

DQB1_10/DQB_42

AF6

DQB1_11/DQB_43

AG4

DQB1_12/DQB_44

AH5

DQB1_13/DQB_45

AH6

DQB1_14/DQB_46

AJ4

DQB1_15/DQB_47

AK3

DQB1_16/DQB_48

AF8

DQB1_17/DQB_49

AF9

DQB0_5/DQB_5

F3

DQB1_18/DQB_50

AG8

DQB1_19/DQB_51

AG7

DQB1_20/DQB_52

AK9

DQB1_21/DQB_53

AL7

DQB1_22/DQB_54

AM8

DQB1_23/DQB_55

AM7

DQB1_24/DQB_56

AK1

DQB1_25/DQB_57

AL4

DQB1_26/DQB_58

AM6

DQB1_27/DQB_59

AM1

DQB0_6/DQB_6

F5

DQB1_28/DQB_60

AN4

DQB1_29/DQB_61

AP3

DQB1_30/DQB_62

AP1

DQB1_31/DQB_63

AP5

DQB0_7/DQB_7

G4

DQB0_8/DQB_8

H5

DQB0_9/DQB_9

H6

MVREFDB

Y12

MVREFSB

AA12

TESTEN

AD28

CASB0B W10

CASB1B AA10

CKEB0 U10

CKEB1 AA11

CLKB0 L9

CLKB0B L8

CLKB1 AD8

CLKB1B AD7

CLKTESTA

AK10

CLKTESTB

AL10

CSB0B_0 P10

CSB0B_1 L10

CSB1B_0 AD10

CSB1B_1 AC10

WCKB0_0/DQMB_0 H3

WCKB0B_0/DQMB_1 H1

WCKB0_1/DQMB_2 T3

WCKB0B_1/DQMB_3 T5

WCKB1_0/DQMB_4 AE4

WCKB1B_0/DQMB_5 AF5

WCKB1_1/DQMB_6 AK6

WCKB1B_1/DQMB_7 AK5

DRAM_RST AH11

MAB0_0/MAB_0 P8

MAB0_1/MAB_1 T9

MAB1_2/MAB_10 AC8

MAB1_3/MAB_11 AC9

MAB1_4/MAB_12 AA7

MAB1_5/BA2 AA8

MAB1_6/BA0 Y8

MAB1_7/BA1 AA9

MAB0_2/MAB_2 P9

MAB0_3/MAB_3 N7

MAB0_4/MAB_4 N8

MAB0_5/MAB_5 N9

MAB0_6/MAB_6 U9

MAB0_7/MAB_7 U8

MAB1_0/MAB_8 Y9

MAB1_1/MAB_9 W9

ADBIB0/ODTB0 T7

ADBIB1/ODTB1 W 7

RASB0B T10

RASB1B Y10

EDCB0_0/QSB_0/RDQSB_0 F6

EDCB0_1/QSB_1/RDQSB_1 K3

EDCB0_2/QSB_2/RDQSB_2 P3

EDCB0_3/QSB_3/RDQSB_3 V5

EDCB1_0/QSB_4/RDQSB_4 AB5

EDCB1_1/QSB_5/RDQSB_5 AH1

EDCB1_2/QSB_6/RDQSB_6 AJ9

EDCB1_3/QSB_7/RDQSB_7 AM5

DDBIB0_0/QSB_0B/WDQSB_0 G7

DDBIB0_1/QSB_1B/WDQSB_1 K1

DDBIB0_2/QSB_2B/WDQSB_2 P1

DDBIB0_3/QSB_3B/WDQSB_3 W4

DDBIB1_0/QSB_4B/WDQSB_4 AC4

DDBIB1_1/QSB_5B/WDQSB_5 AH3

DDBIB1_2/QSB_6B/WDQSB_6 AJ8

DDBIB1_3/QSB_7B/WDQSB_7 AM3

WEB0B N10

WEB1B AB11

MAB0_8 T8

MAB1_8 W8

RV140

40.2_0402_1%

DIS@

12

RV132 240_0402_1%SE@

1 2

RV130 240_0402_1%SE@

1 2

RV147

100_0402_1%

DIS@

12

MEMORY INTERFACE A

DDR2

GDDR3/GDDR5

DDR3

GDDR5/DDR2/GDDR3

DDR2

GDDR5/GDDR3

DDR3

GDDR5

UV1C

THAMES XT M2

@

DQA0_0/DQA_0

C37

DQA0_1/DQA_1

C35

DQA0_10/DQA_10

C30

DQA0_11/DQA_11

A30

DQA0_12/DQA_12

F28

DQA0_13/DQA_13

C28

DQA0_14/DQA_14

A28

DQA0_15/DQA_15

E28

DQA0_16/DQA_16

D27

DQA0_17/DQA_17

F26

DQA0_18/DQA_18

C26

DQA0_19/DQA_19

A26

DQA0_2/DQA_2

A35

DQA0_20/DQA_20

F24

DQA0_21/DQA_21

C24

DQA0_22/DQA_22

A24

DQA0_23/DQA_23

E24

DQA0_24/DQA_24

C22

DQA0_25/DQA_25

A22

DQA0_26/DQA_26

F22

DQA0_27/DQA_27

D21

DQA0_28/DQA_28

A20

DQA0_29/DQA_29

F20

DQA0_3/DQA_3

E34

DQA0_30/DQA_30

D19

DQA0_31/DQA_31

E18

DQA1_0/DQA_32

C18

DQA1_1/DQA_33

A18

DQA1_2/DQA_34

F18

DQA1_3/DQA_35

D17

DQA1_4/DQA_36

A16

DQA1_5/DQA_37

F16

DQA1_6/DQA_38

D15

DQA1_7/DQA_39

E14

DQA0_4/DQA_4

G32

DQA1_8/DQA_40

F14

DQA1_9/DQA_41

D13

DQA1_10/DQA_42

F12

DQA1_11/DQA_43

A12

DQA1_12/DQA_44

D11

DQA1_13/DQA_45

F10

DQA1_14/DQA_46

A10

DQA1_15/DQA_47

C10

DQA1_16/DQA_48

G13

DQA1_17/DQA_49

H13

DQA0_5/DQA_5

D33

DQA1_18/DQA_50

J13

DQA1_19/DQA_51

H11

DQA1_20/DQA_52

G10

DQA1_21/DQA_53

G8

DQA1_22/DQA_54

K9

DQA1_23/DQA_55

K10

DQA1_24/DQA_56

G9

DQA1_25/DQA_57

A8

DQA1_26/DQA_58

C8

DQA1_27/DQA_59

E8

DQA0_6/DQA_6

F32

DQA1_28/DQA_60

A6

DQA1_29/DQA_61

C6

DQA1_30/DQA_62

E6

DQA1_31/DQA_63

A5

DQA0_7/DQA_7

E32

DQA0_8/DQA_8

D31

DQA0_9/DQA_9

F30

MEM_CALRP1

M12

MVREFDA

L18

MVREFSA

L20

MEM_CALRN0

L27

MEM_CALRN1

N12

MEM_CALRN2

AG12

MEM_CALRP0

M27

MEM_CALRP2

AH12

CASA0B K20

CASA1B K17

CKEA0 K21

CKEA1 J20

CLKA0 H27

CLKA0B G27

CLKA1 J14

CLKA1B H14

CSA0B_0 K24

CSA0B_1 K27

CSA1B_0 M13

CSA1B_1 K16

WCKA0_0/DQMA_0 A32

WCKA0B_0/DQMA_1 C32

WCKA0_1/DQMA_2 D23

WCKA0B_1/DQMA_3 E22

WCKA1_0/DQMA_4 C14

WCKA1B_0/DQMA_5 A14

WCKA1_1/DQMA_6 E10

WCKA1B_1/DQMA_7 D9

MAA0_0/MAA_0 G24

MAA0_1/MAA_1 J23

MAA1_2/MAA_10 L13

MAA1_3/MAA_11 G16

MAA1_4/MAA_12 J16

MAA1_5/MAA_13_BA2 H16

MAA1_6/MAA_14_BA0 J17

MAA1_7/MAA_A15_BA1 H17

MAA0_2/MAA_2 H24

MAA0_3/MAA_3 J24

MAA0_4/MAA_4 H26

MAA0_5/MAA_5 J26

MAA0_6/MAA_6 H21

MAA0_7/MAA_7 G21

MAA1_0/MAA_8 H19

MAA1_1/MAA_9 H20

ADBIA0/ODTA0 J21

ADBIA1/ODTA1 G19

RASA0B K23

RASA1B K19

EDCA0_0/QSA_0/RDQSA_0 C34

EDCA0_1/QSA_1/RDQSA_1 D29

EDCA0_2/QSA_2/RDQSA_2 D25

EDCA0_3/QSA_3/RDQSA_3 E20

EDCA1_0/QSA_4/RDQSA_4 E16

EDCA1_1/QSA_5/RDQSA_5 E12

EDCA1_2/QSA_6/RDQSA_6 J10

EDCA1_3/QSA_7/RDQSA_7 D7

MAA0_8 H23

MAA1_8 J19

DDBIA0_0/QSA_0B/WDQSA_0 A34

DDBIA0_1/QSA_1B/WDQSA_1 E30

DDBIA0_2/QSA_2B/WDQSA_2 E26

DDBIA0_3/QSA_3B/WDQSA_3 C20

DDBIA1_0/QSA_4B/WDQSA_4 C16

DDBIA1_1/QSA_5B/WDQSA_5 C12

DDBIA1_2/QSA_6B/WDQSA_6 J11

DDBIA1_3/QSA_7B/WDQSA_7 F8

WEA0B K26

WEA1B L15

RV148

100_0402_1%

DIS@

12

RV205 120_0402_5%CH@

1 2

RV145

4.99K_0402_1%

DIS@

1 2

CV221

0.1U_0402_16V7K

DIS@

12

CV218

@

0.1U_0402_16V7K

12

RV138

@

4.7K_0402_5%

12

RV131 240_0402_1%DIS@

1 2

RV144

10_0402_1%

DIS@

1 2

RV137

@

51.1_0402_1%

12

RV134 240_0402_1%DIS@

1 2

RV139

40.2_0402_1%

DIS@

12

RV143

51.1_0402_1%

DIS@

1 2

RV136

@

51.1_0402_1%

12

RV142

40.2_0402_1%

DIS@

12

RV141

40.2_0402_1%

DIS@

12

RV149

100_0402_1%

DIS@

12

RV129 240_0402_1%DIS@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MDA[0..63]

MAA[14..0]

DQMA#[7..0]

QSA#[7..0]

QSA[7..0]

A_BA0 A_BA0 A_BA0

A_BA1 A_BA1 A_BA1

A_BA2 A_BA2 A_BA2

CASA0# CASA1#

CKEA0 CKEA1

CLKA0

CLKA0

CLKA0#

CLKA0#

CLKA1

CLKA1

CLKA1#

CLKA1#

CSA0#_0 CSA1#_0

DQMA#1

DQMA#2 DQMA#4

DQMA#5

DQMA#6

DQMA#7

DRAM_RST# DRAM_RST# DRAM_RST#

MAA0 MAA0 MAA0

MAA1 MAA1 MAA1

MAA10 MAA10 MAA10

MAA11 MAA11 MAA11

MAA12 MAA12 MAA12

MAA13 MAA13 MAA13

MAA14 MAA14 MAA14

MAA2 MAA2 MAA2

MAA3 MAA3 MAA3

MAA4 MAA4 MAA4

MAA5 MAA5 MAA5

MAA6 MAA6 MAA6

MAA7 MAA7 MAA7

MAA8 MAA8 MAA8

MAA9 MAA9 MAA9

MDA10

MDA11

MDA12

MDA13

MDA14

MDA15

MDA32

MDA33

MDA34

MDA35

MDA36

MDA37

MDA38

MDA39

MDA40

MDA41

MDA42

MDA43

MDA44

MDA45

MDA46

MDA47

MDA48

MDA49

MDA50

MDA51

MDA52

MDA53

MDA54

MDA55

MDA56

MDA57

MDA58

MDA59

MDA60

MDA61

MDA62

MDA63

ODTA0 ODTA1

QSA#1

QSA#2 QSA#4

QSA#5

QSA#6

QSA#7

QSA1

QSA2 QSA4

QSA5

QSA6

QSA7

RASA0# RASA1#

VREFC_A1 VREFC_A2

VREFC_A2

VREFC_A3

VREFC_A3

VREFC_A4

VREFC_A4

VREFD_Q1 VREFD_Q2

VREFD_Q2

VREFD_Q3

VREFD_Q3

VREFD_Q4

VREFD_Q4

WEA0# WEA1#

DQMA#0

DQMA#3

MAA0

MAA1

MAA10

MAA11

MAA12

MAA13

MAA14

MAA2

MAA3

MAA4

MAA5

MAA6

MAA7

MAA8

MAA9

MDA0

MDA1

MDA2

MDA3

MDA4

MDA5

MDA6

MDA7

QSA#0

QSA#3

QSA0

QSA3

VREFC_A1

VREFD_Q1

MDA8

MDA9

MDA19

MDA21

MDA22

MDA16

MDA18

MDA20

MDA23

MDA17

MDA26

MDA31

MDA24

MDA30

MDA29

MDA27

MDA28

MDA25

QSA#[7..0]<39>

QSA[7..0]<39>

DQMA#[7..0]<39>

MAA[14..0]<39>

CKEA1<39>

RASA1#<39>

CLKA1#<39>

CLKA1<39>

WEA1#<39>

CSA1#_0<39>

ODTA1<39>

CASA1#<39>

CLKA0<39>

CASA0#<39>

A_BA2<39>

ODTA0<39>

RASA0#<39>

CKEA0<39>

CSA0#_0<39>

A_BA1<39>

DRAM_RST#<39,41>

CLKA0#<39>

WEA0#<39>

A_BA0<39>

MDA[0..63]<39>

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS +1.5VGS+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS +1.5VGS

+1.5VGS

+1.5VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

C 1.0

ATI_SeymourXT_M2_VRAM_A

Compal Electronics, Inc.

LA-8241P

2012/01/17 2013/01/16

40 56Wednesday, February 01, 2012

CHANNEL A: 256MB/512MB DDR3

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

CV234

0.01U_0402_16V7K

DIS@

12

RV160

4.99K_0402_1%

DIS@

12

CV259

1U_0402_6.3V6K

DIS@

1

2

RV170

4.99K_0402_1%

DIS@

12

CV254

1U_0402_6.3V6K

DIS@

1

2

96-BALL

SDRAM DDR3

UV20

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV252

1U_0402_6.3V6K

DIS@

1

2

CV253

1U_0402_6.3V6K

DIS@

1

2

CV244

0.1U_0402_16V7K

DIS@

1

2

CV230

0.1U_0402_16V7K

DIS@

12

RV173

4.99K_0402_1%

DIS@

12

RV164 56_0402_1%

DIS@

1 2

CV271

1U_0402_6.3V6K

DIS@

1

2

CV243

0.1U_0402_16V7K

DIS@

1

2

RV171

4.99K_0402_1%

DIS@

12

CV248

10U_0603_6.3V6M

DIS@

1

2

CV266

1U_0402_6.3V6K

DIS@

1

2

CV235

0.1U_0402_16V7K

DIS@

1

2

CV226

0.1U_0402_16V7K

DIS@

12

RV152

240_0402_1%

DIS@

12

CV249

10U_0603_6.3V6M

DIS@

1

2

CV240

0.1U_0402_16V7K

DIS@

1

2

CV255

1U_0402_6.3V6K

DIS@

1

2

CV265

1U_0402_6.3V6K

DIS@

1

2

CV231

0.1U_0402_16V7K

DIS@

12

RV157

4.99K_0402_1%

DIS@

12

CV262

1U_0402_6.3V6K

DIS@

1

2

CV270

1U_0402_6.3V6K

DIS@

1

2

CV264

1U_0402_6.3V6K

DIS@

1

2

RV150

240_0402_1%

DIS@

12

RV159

4.99K_0402_1%

DIS@

12

96-BALL

SDRAM DDR3

UV21

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

RV154 56_0402_1%

DIS@

1 2

CV258

1U_0402_6.3V6K

DIS@

1

2

RV165 56_0402_1%

DIS@

1 2

CV251

10U_0603_6.3V6M

DIS@

1

2

CV238

0.1U_0402_16V7K

DIS@

1

2

96-BALL

SDRAM DDR3

UV19

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV239

0.1U_0402_16V7K

DIS@

1

2

CV229

0.1U_0402_16V7K

DIS@

12

RV161

4.99K_0402_1%

DIS@

12

CV257

1U_0402_6.3V6K

DIS@

1

2

CV227

0.1U_0402_16V7K

DIS@

12

96-BALL

SDRAM DDR3

UV18

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV263

1U_0402_6.3V6K

DIS@

1

2

RV151

240_0402_1%

DIS@

12

RV163

4.99K_0402_1%

DIS@

12

CV242

0.1U_0402_16V7K

DIS@

1

2

CV260

1U_0402_6.3V6K

DIS@

1

2

CV233

0.1U_0402_16V7K

DIS@

12

RV156

4.99K_0402_1%

DIS@

12

CV250

10U_0603_6.3V6M

DIS@

1

2

CV241

0.1U_0402_16V7K

DIS@

1

2

CV247

0.1U_0402_16V7K

DIS@

1

2

CV228

0.1U_0402_16V7K

DIS@

12

RV153

240_0402_1%

DIS@

12

CV267

1U_0402_6.3V6K

DIS@

1

2

RV162

4.99K_0402_1%

DIS@

12

CV268

1U_0402_6.3V6K

DIS@

1

2

RV158

4.99K_0402_1%

DIS@

12

CV245

0.1U_0402_16V7K

DIS@

1

2

RV168

4.99K_0402_1%

DIS@

12

CV237

0.1U_0402_16V7K

DIS@

1

2

CV232

0.1U_0402_16V7K

DIS@

12

CV256

1U_0402_6.3V6K

DIS@

1

2

RV155 56_0402_1%

DIS@

1 2

RV172

4.99K_0402_1%

DIS@

12

CV246

0.1U_0402_16V7K

DIS@

1

2

CV269

1U_0402_6.3V6K

DIS@

1

2

RV167

4.99K_0402_1%

DIS@

12

CV225

0.01U_0402_16V7K

DIS@

12

CV261

1U_0402_6.3V6K

DIS@

1

2

RV166

4.99K_0402_1%

DIS@

12

CV236

0.1U_0402_16V7K

DIS@

1

2

RV169

4.99K_0402_1%

DIS@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MDB[0..63]

MAB[14..0]

DQMB#[7..0]

QSB#[7..0]

QSB[7..0]

B_BA0 B_BA0 B_BA0

B_BA1 B_BA1 B_BA1

B_BA2 B_BA2 B_BA2

CASB0# CASB1#

CKEB0 CKEB1

CLKB0

CLKB0

CLKB0#

CLKB0#

CLKB1

CLKB1

CLKB1#

CLKB1#

CSB0#_0 CSB1#_0

DQMB#0 DQMB#1

DQMB#3 DQMB#2 DQMB#4

DQMB#5

DQMB#6

DQMB#7

DRAM_RST# DRAM_RST# DRAM_RST#

MAB0 MAB0 MAB0 MAB0

MAB1 MAB1 MAB1 MAB1

MAB10 MAB10 MAB10 MAB10

MAB11 MAB11 MAB11 MAB11

MAB12 MAB12 MAB12 MAB12

MAB13 MAB13 MAB13 MAB13

MAB14 MAB14 MAB14 MAB14

MAB2 MAB2 MAB2 MAB2

MAB3 MAB3 MAB3 MAB3

MAB4 MAB4 MAB4 MAB4

MAB5 MAB5 MAB5 MAB5

MAB6 MAB6 MAB6 MAB6

MAB7 MAB7 MAB7 MAB7

MAB8 MAB8 MAB8 MAB8

MAB9 MAB9 MAB9 MAB9

MDB0

MDB1

MDB10

MDB11

MDB12

MDB13

MDB14

MDB15

MDB2

MDB3

MDB32

MDB33

MDB34

MDB35

MDB36

MDB37

MDB38

MDB39

MDB4

MDB40

MDB41

MDB42

MDB43

MDB44

MDB45

MDB46

MDB47

MDB5

MDB6

MDB7

MDB8

MDB9

ODTB0 ODTB1

QSB#0 QSB#1

QSB#3 QSB#2 QSB#4

QSB#5

QSB#6

QSB#7

QSB0 QSB1

QSB3 QSB2 QSB4

QSB5

QSB6

QSB7

RASB0# RASB1#

VREFC_A1_B

VREFC_A1_B

VREFC_A2_B

VREFC_A3_B

VREFC_A3_B

VREFC_A4_B

VREFC_A4_B

VREFD_Q1_B

VREFD_Q1_B VREFD_Q2_B

VREFD_Q2_B

VREFD_Q3_B

VREFD_Q3_B

VREFD_Q4_B

VREFD_Q4_B

WEB0# WEB1#

MDB63

MDB58

MDB48

MDB49

MDB50

MDB51

MDB52

MDB53

MDB54

MDB55

MDB57

MDB56

MDB60

MDB59

MDB61

MDB62

VREFC_A2_B

MDB23

MDB21

MDB22

MDB18

MDB17

MDB20

MDB19

MDB16

MDB28

MDB29

MDB24

MDB25

MDB30

MDB31

MDB26

MDB27

QSB#[7..0]<39>

QSB[7..0]<39>

DQMB#[7..0]<39>

MAB[14..0]<39>

CLKB0<39>

CASB0#<39>

CKEB1<39>

RASB1#<39>

B_BA2<39>

ODTB0<39>

RASB0#<39>

CLKB1#<39>

CKEB0<39>

CSB0#_0<39>

CLKB1<39>

WEB1#<39>

B_BA1<39>

CSB1#_0<39>

DRAM_RST#<39,40>

CLKB0#<39>

WEB0#<39>

ODTB1<39>

CASB1#<39>

B_BA0<39>

MDB[0..63]<39>

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS +1.5VGS

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

C 1.0

ATI_SeymourXT_M2_VRAM_B

Compal Electronics, Inc.

LA-8241P

2012/01/17 2013/01/16

41 56Wednesday, February 01, 2012

CHANNEL B: 256MB/512MB DDR3

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

CV284

0.1U_0402_16V7K

DIS@

1

2

RV187

4.99K_0402_1%

DIS@

12

RV174 56_0402_1%

DIS@

1 2

CV286

0.1U_0402_16V7K

DIS@

1

2

CV279

0.1U_0402_16V7K

DIS@

1

2

CV303

1U_0402_6.3V6K

DIS@

1

2

CV296

10U_0603_6.3V6M

DIS@

1

2

CV273

0.01U_0402_16V7K

DIS@

12

RV183

4.99K_0402_1%

DIS@

12

RV188

4.99K_0402_1%

DIS@

12

RV181 56_0402_1%

DIS@

1 2

CV300

1U_0402_6.3V6K

DIS@

1

2

RV192

4.99K_0402_1%

DIS@

12

CV280

0.1U_0402_16V7K

DIS@

1

2

RV180 56_0402_1%

DIS@

1 2

RV178

240_0402_1%

DIS@

12

RV190

4.99K_0402_1%

DIS@

12

CV307

1U_0402_6.3V6K

DIS@

1

2

CV282

0.1U_0402_16V7K

DIS@

1

2

CV301

1U_0402_6.3V6K

DIS@

1

2

RV195

4.99K_0402_1%

DIS@

12

CV314

1U_0402_6.3V6K

DIS@

1

2

CV293

0.1U_0402_16V7K

DIS@

1

2

CV304

1U_0402_6.3V6K

DIS@

1

2

CV302

1U_0402_6.3V6K

DIS@

1

2

CV315

1U_0402_6.3V6K

DIS@

1

2

RV177

240_0402_1%

DIS@

12

RV185

4.99K_0402_1%

DIS@

12

CV305

1U_0402_6.3V6K

DIS@

1

2

CV317

1U_0402_6.3V6K

DIS@

1

2

CV281

0.1U_0402_16V7K

DIS@

1

2

RV196

4.99K_0402_1%

DIS@

12

CV287

0.1U_0402_16V7K

DIS@

1

2

CV312

1U_0402_6.3V6K

DIS@

1

2

RV176

240_0402_1%

DIS@

12

CV274

0.1U_0402_16V7K

DIS@

1

2

RV191

4.99K_0402_1%

DIS@

12

CV309

1U_0402_6.3V6K

DIS@

1

2

96-BALL

SDRAM DDR3

UV24

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV283

0.1U_0402_16V7K

DIS@

1

2

CV295

10U_0603_6.3V6M

DIS@

1

2

CV290

0.1U_0402_16V7K

DIS@

1

2

CV311

1U_0402_6.3V6K

DIS@

1

2

RV197

4.99K_0402_1%

DIS@

12

CV298

10U_0603_6.3V6M

DIS@

1

2

CV308

1U_0402_6.3V6K

DIS@

1

2

CV313

1U_0402_6.3V6K

DIS@

1

2

CV272

0.01U_0402_16V7K

DIS@

12

RV179

240_0402_1%

DIS@

12

96-BALL

SDRAM DDR3

UV25

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV278

0.1U_0402_16V7K

DIS@

1

2

RV194

4.99K_0402_1%

DIS@

12

RV193

4.99K_0402_1%

DIS@

12

CV276

0.1U_0402_16V7K

DIS@

1

2

CV292

0.1U_0402_16V7K

DIS@

1

2

CV310

1U_0402_6.3V6K

DIS@

1

2

96-BALL

SDRAM DDR3

UV23

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV299

1U_0402_6.3V6K

DIS@

1

2

RV182

4.99K_0402_1%

DIS@

12

RV175 56_0402_1%

DIS@

1 2

RV186

4.99K_0402_1%

DIS@

12

CV306

1U_0402_6.3V6K

DIS@

1

2

CV291

0.1U_0402_16V7K

DIS@

1

2

RV184

4.99K_0402_1%

DIS@

12

CV288

0.1U_0402_16V7K

DIS@

1

2

CV318

1U_0402_6.3V6K

DIS@

1

2

RV189

4.99K_0402_1%

DIS@

12

CV289

0.1U_0402_16V7K

DIS@

1

2

CV285

0.1U_0402_16V7K

DIS@

1

2

CV294

0.1U_0402_16V7K

DIS@

1

2

CV316

1U_0402_6.3V6K

DIS@

1

2

CV275

0.1U_0402_16V7K

DIS@

1

2

CV277

0.1U_0402_16V7K

DIS@

1

2

96-BALL

SDRAM DDR3

UV22

K4W1G1646G-BC11

X76@

WE

L3

RAS

J3

CAS

K3

CS/CS0

L2

CKE/CKE0

K9

CK

J7

CK

K7

DQSU

B7

BA0

M2

BA1

N8

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

DQL0 E3

DQL1 F7

DQL2 F2

DQL3 F8

DQL4 H3

DQL5 H8

DQL6 G2

DQL7 H7

VSSQ D1

VSS A9

VSS E1

VSS B3

NC/ODT1

J1

VDD B2

VDD D9

VDDQ A1

VDDQ A8

VDDQ C1

VDDQ C9

NC/CS1

L1

NC/CE1

J9

VDDQ E9

ZQ/ZQ0

L8

RESET

T2

DQSL

F3

DMU

D3 DML

E7

VSSQ B1

VSSQ B9

VSSQ D8

VSSQ E2

DQSU

C7

VSSQ E8

DQSL

G3

VDDQ F1

VSSQ F9

VSSQ G1

VDDQ H2

VDDQ H9

VSSQ G9

VREFCA

M8

VSS G8

VDD G7

ODT/ODT0

K1

A0

N3

A1

P7

VDD K2

A12

N7

VSS J2

VDD K8

DQU1 C3

DQU2 C8

DQU3 C2

DQU4 A7

DQU5 A2

DQU6 B8

DQU7 A3

DQU0 D7

A13

T3

A14

T7

A15/BA3

M7

BA2

M3

VREFDQ

H1

NCZQ1

L9

VDD N1

VDD N9

VDD R1

VDD R9

VSS J8

VSS M1

VSS M9

VSS P1

VSS P9

VSS T1

VSS T9

VDDQ D2

CV297

10U_0603_6.3V6M

DIS@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

1.0

HW-PIR

42 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

17

10

16

COMPAL

14

4

COMPAL

COMPAL

COMPAL

0.1

Page 1

Page 1Page 1

Page 1

Solution Description

Solution DescriptionSolution Description

Solution Description Rev.

Rev.Rev.

Rev.Page#

Page#Page#

Page# Title

TitleTitle

Title

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Item

ItemItem

Item Issue Description

Issue DescriptionIssue Description

Issue DescriptionDate

DateDate

Date Request

RequestRequest

Request

Owner

OwnerOwner

Owner

1

2

3

18,19 PCH VCCDMI, V_PROC_IO change to +VCCP from +1.05VS

09,10 CPU

remove decoupling cap for +VCC_CORE, +VCCP, +VCC_GFXCORE_AXG, owner change to

PWR

15

12

10 CPU

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent

(SA) VR controller.

13

5

11/07/28

6

7

8

9

08,11,12 DIMM

The M3 traces are routed to the Sandy Bridge Processor reserved pins for DDR3

VREF Intel CHKLST Rev1.5 required

11

18

11/07/28

11/07/28

11/07/28

0.1

0.1

0.1

Intel CHKLST Rev1.5 required

Intel CHKLST Rev1.5 required

Intel CHKLST Rev1.5 required

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

ADPIN

VSB_N_002

VSB_N_003

VSB_N_001

PSID

PSID-1

PSID-5

PSID-2

PSID-3

BATT+

BATT++

BATT_PRS

SYS_PRES

VS_N_001

VS_N_002

N1

CLK_SMB

DAT_SMB

POK<45>

BATT_TEMP <24,44>

EC_SMB_DA1 <24,44>

EC_SMB_CK1 <24,44>

VCIN0_PH<24>

VCIN1_PH<24>

PS_ID <24>

65W /90W# <24>

51_ON#<25>

ADP_I <24,44>

130W/90W# <24>

ACIN <15,24,35,44>

VIN

B+

+5VALW

B+_BIAS

+5VALW

+5VALW

+3VALW+5VALW

+RTCBATT

+3VLP

+3VALW

BATT++BATT+

+3VLP

VIN

VS

BATT+

+3VLP

+CHGRTC

+3VALW

VIN

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

43 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

SMART

SMARTSMART

SMART

Battery:

Battery:Battery:

Battery:

01.BATT1+

01.BATT1+01.BATT1+

01.BATT1+

02.BATT2+

02.BATT2+02.BATT2+

02.BATT2+

03.CLK_SMB

03.CLK_SMB03.CLK_SMB

03.CLK_SMB

04.DAT_SMB

04.DAT_SMB04.DAT_SMB

04.DAT_SMB

05.BATT_PRS

05.BATT_PRS05.BATT_PRS

05.BATT_PRS

06.SYS_PRES

06.SYS_PRES06.SYS_PRES

06.SYS_PRES

07.BAT_ALERT

07.BAT_ALERT07.BAT_ALERT

07.BAT_ALERT

08.GND1

08.GND108.GND1

08.GND1

09.GND2

09.GND209.GND2

09.GND2

PBATT1 battery connector (Follow E3)

PH901 under CPU botten side :

CPU thermal protection at 90 degree C

65W/90W#

130W/90W#

65W 90W 130W

High

High

Low

Low

Erp lot6 Circuit

PR903

33_0402_5%

1 2

PD904

PESD24VS2UT_SOT23-3

@

2

3

1

PR904

100K_0402_1%

1 2

JRTC9

SUYIN_060003FA002G202NL

@

+1

-

2

PC907

100P_0402_50V8J

12

PH900

100K_0402_1%_TSM0B104F4251RZ

12

PR917

499K_0402_1%

1 2

PC915

.1U_0402_16V7K

@

1 2

PR913

100_0402_5%

1 2

PJPDC9

ACES_50299-00501-003

@

11

22

33

44

55

GND 6

GND 7

PD907

LL4148_LL34-2

@930

12

PC916

0.1U_0402_25V6

12

PR925

200_0805_5%

@930

1 2

G

D

S

PQ904

2N7002KW_SOT323-3

2

13

PU900

G920AT24U_SOT89-3

@930

IN 2

GND

1

OUT

3

PC913

4.7U_0603_6.3V6K~D

@930

12

PR930

1M_0402_1%

1 2

PC911

0.22U_0603_25V7K

@930

12

PC900

1000P_0402_50V7K

12

PD905

RB751V-40_SOD323-2

@

1 2

PR911

10K_0402_1%

1 2

G

D

S

PQ903

2N7002KW _SOT323-3

2

13

PR931

1.2K_1206_5%~D

12

PR922

100K_0402_1%

@930

12

PR915

332K_0402_1%

1 2

PC912

0.1U_0402_25V6

@930

12

PL900

SMB3025500YA_2P

1 2

PR914

100_0402_5%

1 2

PQ907B

SSM6N7002FU-2N_SOT363-6

3

5

4

PC914

1U_0603_25V6K

@930

12

PR918

90.9K_0402_1%

1 2

G

D

S

PQ901

FDV301N_NL_SOT23-3~D

2

1 3

PR901

0_0402_5%@

1 2

PR924

0_0603_5%

@930

1 2

PR910

100_0402_5%

1 2

PD906

LL4148_LL34-2

@930

1 2

PL901

SMB3025500YA_2P

1 2

PD900

DA204U_SOT323~D

@

2

3

1

PC903

1000P_0402_50V7K

12

PR927

13K_0402_1%

1 2

PR923

22K_0402_1%

@930

1 2

PR905

10K_0402_1%

12

PC905

100P_0402_50V8J

12

PR929

1M_0402_1%

1 2

PQ902

TP0610K-T1-E3_SOT23-3

2

13

PC902

100P_0402_50V8J

12

PR900

15K_0402_1%

1 2

G

D

S

PQ906

2N7002KW_SOT323-3

@

2

13

E

B

C

PQ900

MMST3904-7-F_SOT323~D

2

3 1

PR902

2.2K_0402_5%

1 2

PR916

13K_0402_1%

@

1 2

PR906

10K_0402_1%

1 2

PD902

SM24_SOT23

@

2

3

1

PR920

68_1206_5%

@930

12

PR912

0_0402_5%

1 2

PR908

22K_0402_1%

1 2

PR909

100K_0402_1%

1 2

PD903

PESD24VS2UT_SOT23-3

@

2

3

1

PQ907A

SSM6N7002FU-2N_SOT363-6

61

2

PC908

0.22U_0603_25V7K

12

PC901

1000P_0402_50V7K

12

PL902

BLM18BD102SN1D_0603~D

12

PR921

68_1206_5%

@930

12

PBATT9

ALLTO_C144FE-109A7-L

@

11

33

44

55

66

88

99

22

77

GND 10

GND 11

PC910

.1U_0402_16V7K

12

PC909

0.1U_0402_25V6

12

PC904

100P_0402_50V8J

12

PR926

6.81K_0402_1%

@

1 2

PC906

0.01U_0402_25V7K

12

PD901

BAV99W-7-F_SOT-323-3~D

2

3

1

PR907

100K_0402_1%

12

PQ905

TP0610K-T1-E3_SOT23-3

@930

2

13

PR919

0_0402_5%

1 2

PR928

200K_0402_1%

12

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

DL_CHG

ACSETIN

CSIP

DH_CHG

CHG

VDDP_LDO

CSIN

BST

BST_CHGA

VFB

MAX8731_REF

DCIN

VDDP_LDO

V1

ACIN

ACIN

V1

LX_CHG

MAX8731_REF

MAX8731_REF

V1

VDDP_LDO

ACOFF <24>

EC_SMB_DA1<24,43>

EC_SMB_CK1<24,43>

ACIN <15,24,35,43>

BATT_TEMP

<24,43>

H_PROCHOT#<6,24>

ADP_I<24,43>

BATT_TEMP<24,43>

BATT_TEMP<24,43>

BATT_TEMP

ACOFF<24>

ACOFF <24>

VIN

VIN

BATT+

P2 P3

B+

CHG_B+

VIN

BATT+

+5VALW

VIN

VIN

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

44 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-Charger

Iada=0~4.62A(90W)

CC = 3.52A (Normal)

CV = 13.3V

ADP_I = 19.9*Iadapter*Rsense

731@ for ISL88731C

747@ for BQ24747

PU100

PR133

PR112

PR117

PR113

PC131

PC132

PR122

PR123

PR129

PC117

PC124

PC123

PC125

ISL88731C BQ24747

@ 100k

100k @

158k @

210k 309k

0.1u 220p

0.01u @

@ 200k

@

@

@

@

@

@

7.5k

10k

2200p

56p

120p

1u

PC134

PC129

PC126

PR127

PR111

PC110

@0.01u

@ 0.1u

0.1u0.22u

10 0

4.7 @

@1u

PC108

PR106

PR107

PC112

PD101

10 0

010

0.1u @

0.047u 0.1u

@BAT54HT1G

ISL88731C BQ24747 BQ24747ISL88731C BQ24747ISL88731C BQ24747ISL88731C

For DT Mode

PR130

100_0402_5%

1 2

PQ106B

SSM6N7002FU-2N_SOT363-6

@

3

5

4

PR129

10K_0402_5%

747@

1 2

PR110

47K_0402_1%

1 2

PQ103

PDTA144EU PNP_SOT323

2

1 3

PQ107

DDTC115EUA-7-F_SOT323

2

13

PC132

0.01U_0402_25V7K

731@

12

PC107

0.1U_0603_25V7K

1 2

PR123

7.5K_0402_5%

747@

1 2

PR135

0_0402_5%

@

1 2

PR100

3.3_1210_5%

12

PR116

49.9K_0402_1%

1 2

PR122

200K_0402_5%

747@

1 2

PQ105A

SSM6N7002FU-2N_SOT363-6

61

2

PR127

0/0402

747@

PQ105B

SSM6N7002FU-2N_SOT363-6

3

5

4

PC126

0.1U/0603

747@

PC103

4.7U_0805_25V6-K

12

PC130

0.1U_0603_25V7K

@

1 2

PC116

0.1U_0402_10V7K

12

PU100

ISL88731CHRTZ-T_QFN28_5X5~D

731@

UGATE 24

CSOP 18

PHASE 23

VFB 15

SDA

9

VICM

8

ICREF 1

DCIN

22

ACIN

2

VDDSMB

11

SCL

10

ACOK

13

NC

14

BOOT 25

NC 16

EAO

4

VDDP 21

ICOUT 26

CSSP 28

CSON 17

PGND 19

LGATE 20

FBO

6

EAI

5

CSSN 27

VREF

3

CE

7

GND

12

TP

29

PR111

4.7_0603_5%

731@

12

PC131

0.1U/0402

747@

PQ100

AO4407AL_SO8

36

5

7

8

2

4

1

PQ101

AO4409L_SO8

3 6

5

7

8

2

4

1

PR103

200K_0402_1%

12

PR128

0_0402_5%

12

PR113

309K/0402

747@

PR107

10_0402_5%

731@

12

PC117

2200P_0402_50V7K

747@

12

PR114

0_0603_5%

1 2

PC134

0.01U_0402_25V7K

731@

12

PC119

10U_0805_25V5K~D

12

PQ112B

SSM6N7002FU-2N_SOT363-6

3

5

4

PR126

4.7K_0402_5%

12

PC121

680P_0402_50V7K

@

12

PR105

150K_0402_1%

12

G

D

S

PQ111

SSM3K7002FU_SC70-3

@

2

13

PC127

1U_0603_25V6K

@

12

PC128

0.1U_0402_10V7K

@

12

PC131

.1U_0402_16V7K

731@

1 2

PC113

1000P_0402_50V7K

1 2

PR109

10_1206_1%

1 2

PC101

0.1U_0603_25V7K

12

PD101

BAT54HT1G_SOD323-2~D

747@

1 2

PQ112A

SSM6N7002FU-2N_SOT363-6

61

2

PR104

3.3_1210_5%

12

PR136

1.2K_1206_5%~D

12

PC122

10U_0805_25V5K~D

12

PR127

10_0402_5%731@

12

PR134

0_0402_5%

@

1 2

PR131

10K_0402_5%

1 2

PR102

0.01_1206_1%

1

3

4

2

PC105

2200P_0402_25V7K~D

12

PR133

100K_0402_1%

747@

12

PC100

2.2U_0805_25V6K

1 2

PR125

100_0402_1%

1 2

PQ109

DDTC115EUA-7-F_SOT323

2

13

PR108

200K_0402_1%

1 2

PC120

10U_0805_25V5K~D

@

12

PC104

4.7U_0805_25V6-K

12

PR112

100K_0402_1%

731@

12

PR117

158K_0402_1%

731@

12

PR106

0/0402

747@

PC124

56P_0402_50V8~D

747@

1 2

PC118

10U_0805_25V5K~D

12

PQ102

AO4407AL_SO8

3 6

5

7

8

2

4

1

PR132

10K_0402_5%

1 2

PQ104

DDTC115EUA-7-F_SOT323

2

13

PC129

0.1U_0603_25V7K

747@

1 2

PR119

0_0402_5%

1 2

PR120

0_0402_5%

1 2

PR107

0/0402

747@

PU100

BQ24747

747@

PR115

100K_0402_1%

1 2

PC125

1U_0603_10V6K

747@

12

PR121

0.01_1206_1%

1

3

4

2

PR106

10_0402_5%

731@

12

PL100

10UH_PCMB063T-100MS_4A_20%

1 2

PR118

47K_0402_5%

1 2

PC112

0.1U/0603

747@

PC110

1U_0603_10V6K

731@

1 2

PQ108

AO4466L_SO8~D

4

7

8

6

5

1

2

3

PC115

1U_0603_10V6K

1 2

PC102

5600P_0402_25V7K~D

1 2

PR124

4.7_1206_5%

@

12

PQ106A

SSM6N7002FU-2N_SOT363-6

@

61

2

PC111

1U_0603_25V6K

12

PC109

0.1U_0402_10V7K

@

12

PR113

210K_0402_1%

731@

1 2

PC135

0.1U_0603_25V7K

1 2

PC106

0.1U_0603_25V7K

12

PC108

0.1U_0603_25V7K

731@

1 2

PC112

0.047U_0603_25V7M

731@

1 2

PQ113A

SSM6N7002FU-2N_SOT363-6

61

2

PC123

120P_0402_50VNPO~D

747@

1 2

PQ113B

SSM6N7002FU-2N_SOT363-6

3

5

4

PL101

1UH_NRS4018T1R0NDGJ_3.2A_30%

1 2

PC133

0.01U_0402_25V7K

@

12

PR101

200K_0402_1%

12

PC126

0.22U_0603_25V7K

731@

1 2

PQ110

AO4712L_SO8~D

4

7

8

6

5

1

2

3

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

BST_5V

LX_5V

BST1_5VBST1_3V

UG_5V

BST_3V

ENTRIP2

ENTRIP1

FB_3V

LG_5V

SNUB_3V

SNUB_5V

ENTRIP1ENTRIP1

ENTRIP2

LG_3V

UG_3V

LX_3V

FB_5V

N_3_5V_001

3/5V_EN-2

POK <43>

VCOUT0_PH<24>

VCOUT0_PH<24>

EC_ON_35V<28>

B++

+5VALWP

VL

+3VALWP

B++

B++

2VREF_6182

B+

+3VLP

2VREF_6182

+5VALWP +3VALW

+5VALW +3VALWP

B++

VL

VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

45 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-3VALWP/5VALWP

3.3VALWP

TDC 5.4A

Peak Current 7.7A

OCP current 9.2A

TYP MAX

H/S Rds(on) :27mohm , 34mohm

L/S Rds(on) :11mohm , 14mohm

5VALWP

TDC 5.6A

Peak Current 8A

OCP current 9.6A

TYP MAX

H/S Rds(on) :27mohm , 34mohm

L/S Rds(on) :11mohm , 14mohm

PC202

0.1U_0402_25V6

@

1 2

PR202

30.9K_0402_1%

1 2

PC210

0.22U_0603_10V7K

12

PC211

0.22U_0603_10V7K

12

PC205

4.7U_0805_25V6-K

12

PJP200

PAD-OPEN 4x4m

1 2

PL201

3.3UH_PCMC063T-3R3MS_6A_20%

1 2

PR216

150K_0402_1%

@930

1 2

PC217

1U_0603_10V6K

@

12

PR209

4.7_1206_5%

@

12

PR214

100K_0402_5%

1 2

PC207

0.1U_0402_25V6

12

PJP204

PAD-OPEN 4x4m

1 2

PC206

10U_0805_6.3V6M

12

PC209

4.7U_0805_25V6-K

12

PC201

1U_0603_16V6K

12

PR210

4.7_1206_5%

@

12

PQ204

AON7702A_DFN8-5

4

5

1

2

3

PR206

110K_0402_1%

1 2

BZV55-B5V1_SOD80C2

PD200@

21

+

PC213

330U_6.3V_M

1

2

PC214

680P_0603_50V7K

@

12

PR213 2.2K_0402_5%

1 2

PR212

200K_0402_1%

@

12

PU200

RT8205LZQW(2) WQFN 24P PWM

FB1 2

REF 3

VO1 24

ENTRIP1 1

TONSEL 4

FB2 5

SKIPSEL

14

NC

18

VREG5

17

VO2

7

VREG3

8

VIN

16

GND

15

UGATE1 21

BOOT1 22

ENTRIP2 6

PGOOD 23

PHASE1 20

LGATE1 19

EN

13

BOOT2

9

UGATE2

10

PHASE2

11

LGATE2

12

P PAD

25

PR207

2.2_0603_5%

1 2

PQ200A

SSM6N7002FU-2N_SOT363-6

61

2

PJP202

PAD-OPEN 4x4m

1 2

PR205

110K_0402_1%

1 2

PQ202

AON7408L_DFN8-5

3 5

2

4

1

PL200

3.3UH_PCMC063T-3R3MS_6A_20%

1 2

PJP203

PAD-OPEN 4x4m

1 2

PQ203

AON7408L_DFN8-5

3 5

2

4

1

PC203

0.1U_0402_25V6

12

PR217

40.2K_0402_1%

@930

12

PC215

680P_0603_50V7K

@

12

PR208

2.2_0603_5%

1 2

PC208

2200P_0402_50V7K

12

PC219

4.7U_0603_10V6K

12

PC200

0.1U_0402_25V6

@

1 2

PC216

4.7U_0805_10V6K

12

+

PC212

330U_6.3V_M

1

2

PR201

13.7K_0402_1%

1 2

PQ205

AON7702A_DFN8-5

4

5

1

2

3

PQ200B

SSM6N7002FU-2N_SOT363-6

34

5

PR203

20K_0402_1%

1 2

PR204

20K_0402_1%

1 2

PC218

0.1U_0402_25V6

12

PC204

2200P_0402_50V7K

12

PQ201

DTC115EUA_SC70-3

2

13

PL202

1UH_PCMB061H-1R0MS_7A_20%

1 2

PR215 0_0402_5%

1 2

PR200

499K_0402_1%

@

1 2

PR211

0_0402_5%@

1 2

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

1.8VSP_FB

1.8VSP_VIN

1.8VSP_LX

SNUB_1.8VSP

EN_1.8VSP

SUSP#<10,24,27,28,47,48>

+1.8VSP

+3VALW

+1.8VSP +1.8VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

46 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-1.8VSP

<Vo=1.8V> VFB=0.6V

Vo=VFB*(1+PR401/PR404)=0.6*(1+20K/10K)=1.8V

+1.8VSP

TDC 2.6A

Peak Current 3.8A

OCP current 4.5A

PJP401

PAD-OPEN 3x3m

@

1 2

PU400

SY8033BDBC_DFN10_3X3

EN

5

PG 4

LX 3

FB 6

SVIN

8

TP

11

LX 2

PVIN

10

NC

7

PVIN

9

NC

1

PC404

22U_0805_6.3V6M

12

PC403

22U_0805_6.3VAM

12

PC400

22U_0805_6.3V6M

12

PR401

47K_0402_5%

@

12

PC402

22P_0402_50V8J

12

PR404

4.7_1206_5%

12

PR402 100K_0402_5%

1 2

PC401

680P_0603_50V7K

12

PR400

10K_0402_1%

12

PL400

1UH_NRS4018T1R0NDGJ_3.2A_30%

1 2

PJP400

PAD-OPEN 3x3m

@

1 2

PR403

20K_0402_1%

12

PC405

0.22U_0402_16V7K

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BST_+V1.05S_VCCPP

SW_+V1.05S_VCCPP

UG_+V1.05S_VCCPP

LG_+V1.05S_VCCPP

+V1.05S_VCCPP_5V

TRIP_+V1.05S_VCCPP

EN_+V1.05S_VCCPP

FB_+V1.05S_VCCPP

RF_+V1.05S_VCCPP

+V1.05S_VCCPP_B+

+V1.05S_VCCP_PW RGOOD<49>

SUSP#<10,24,27,28,46,48>

VCCIO_SENSE <9>

B+

+5VALW

+VCCP

+3VS

+VCCP +1.05VS

+VCCP

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

47 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-V1.05S_VCCPP

+V1.05S_VCCP

TDC 11A

Peak Current 16A

OCP current 19A

TYP MAX

H/S Rds(on) 10mohm , 14.5mohm

L/S Rds(on) :3mohm , 3.6mohm

PR501

100K_0402_5%

1 2

PU500

TPS51212DSCR_SON10_3X3

EN

3

TRIP

2

V5IN 7

DRVH 9

SW 8

DRVL 6

VBST 10

TST

5

VFB

4

PGOOD

1

TP 11

PC509

1000P_0402_50V7K@

12

PR500

2.2_0603_5%

1 2

PC503

4.7U_0805_25V6-K

12

PQ500

SIR472DP-T1-GE3_POWERPAK8-5~D

4

5

1

2

3

PR504

470K_0402_1%

12

PR509

10K_0402_1%

1 2

PR505

4.7_1206_5%@

12

PJP500

JUMP_43X118

@

11

2

2

PC502

0.1U_0402_25V6

12

PC504

4.7U_0805_25V6-K

12

PC505

.1U_0603_25V7K

12

PR506

1.2K_0402_1%@

12

PC500

1U_0603_10V6K

1 2

PL500

1UH_PCMC063T-1R0MN_11A_20%

1 2

PC501

2200P_0402_50V7K

12

PR508

0_0402_5%

12

PQ501

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PC507

0.1U_0402_10V7K

@

1 2

PR502

47.5K_0402_1%

1 2

PC506

0.22U_0402_16V7K

12

PR503

150K_0402_5%

1 2

PR507

4.99K_0402_1%

12

PC508

1000P_0402_50V7K

@

12

PJP501

PAD-OPEN 4x4m

@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DH_1.5V

VLDOIN_1.5V

S3_1.5V

SW_1.5V

CS_1.5V

DL_1.5V

1.5V_B+

VDD_1.5V

S5_1.5V

VTTREF_1.5V

SNUB_1.5V

BOOT_1.5V

1.5V_B+

1.5V_FB

+1.5V

SYSON<24,27,28>

SUSP#<10,24,27,28,46,47>

+0.75VS

+0.75VSP

B+

+1.5V

+5VALW

+5VALW

+1.5V

+0.75VSP

+1.5V

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

48 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-1.5V/0.75VSP

0.75Volt +/- 5%

TDC 0.7A

Peak Current 1A

OCP Current 1.2A

1.5VP

TDC 14A

Peak Current 20A

OCP current 24A

TYP MAX

H/S Rds(on) :10mohm , 14.5mohm

L/S Rds(on) :3mohm , 3.6mohm

PC314 220P_0402_50V8J~D

1 2

PQ302

SIR818DP-T1-GE3_POWERPAK8-5~D

@

5

4

2

1

3

PR301

2.2_0603_5%

1 2

PR306

200K_0402_5%

1 2

PC305

2200P_0402_50V7K

12

PC311

1U_0603_10V6K

12

PU300

RT8207MZQW_WQFN20_3X3

VTTSNS 2

FB

6

S5

8

PGOOD

10

VDDP

12

PHASE 16

BOOT 18

VTTREF 4

PGND

14

VTTGND 1

GND 3

VDDQ 5

S3

7

TON

9

VDD

11

CS

13

LGATE

15

UGATE 17

VTT 20

VLDOIN 19

PAD 21

PR307

10K_0402_1%

1 2

PC309

1U_0603_10V6K

1 2

+

PC308

330U_2.5V_M

1

2

PC304

0.22U_0603_10V7K

1 2

PR308

0_0402_5%

1 2

PJP300

PAD-OPEN 3x3m

@

1 2

PJP302

JUMP_43X118

@

11

2

2

PR304

5.1_0603_5%

1 2

PR303

4.7_1206_5%

@

12

PC303

0.1U_0402_25V6

12

PQ300

SIR472DP-T1-GE3_POWERPAK8-5~D

4

5

1

2

3

PR300

1M_0402_1%

1 2

PJP301

PAD-OPEN1x1m

12

PQ301

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PC301

4.7U_0805_25V6-K

12

PC307

10U_0805_6.3V6M

12

PC312

680P_0603_50V7K

@

12

PR302

7.15K_0402_1%

1 2

PC310

0.033U_0402_16V7~D

PL300

0.68UH_PCMC063T-R68MN_15.5A_20%

1 2

PC300

1U_0402_6.3VX5R

12

PC302

4.7U_0805_25V6-K

12

PR305

10K_0402_1%

12

PC306

10U_0805_6.3V6M

12

PC313

.1U_0402_16V7K

@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SNUB_+1.5VP

+VCCSA_EN

+VCCSA_PWR_SRC +VCCSA_PHASE

+VCCSAP_FB

+V1.05S_VCCP_PWRGOOD<47>

VCCSA_SENSE <10>

VCCSA_VID1 <10>

VCCSA_VID0 <10>

SA_PGOOD <24>

+VCCSAP +VCCSA

+3VALW +VCCSAP

+3VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

49 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-VCC_SAP

output voltage adjustable network

VID [0] VID[1] VCCSA Vout

0 0 0.9V

0 1 0.8V

1 0 0.725V

1 1 0.675V

The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that

VCCSA VID is 00 prior to VCCIO stability.

+VCC_SAP

TDC 4.2A

Peak Current 6A

OCP current 7.2A

PJP601

PAD-OPEN 4x4m

@

1 2

PU600

SY8037BDCC_DFN12_3X3

LX 3

LX 2

FB

9

PVIN

11

SVIN

10

VOUT

8

PVIN

12

EN 5

PG 4

LX 1

VID1

7

GND

13

VID0 6

PR605

100K_0402_5%

12

PR602

0_0402_5%

12

PR603

1K_0402_5%

1 2

PC601

0.1U_0402_10V7K

@

12

PC605

2200P_0402_50V7K

1

2

PC612

10U_0805_6.3V6M

12

PC607

22U_0805_6.3VAM

1 2

PL600

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

PC603

0.1U_0603_25V7K

12

PC610

68P_0402_50V8J

12

PR606

100_0402_5%

12

PC600

680P_0402_50V7K

1 2

PR604

1K_0402_5%

1 2

PR600

4.7_1206_5%

1 2

PC604

22U_0805_6.3VAM

1 2

PC609

22U_0805_6.3VAM

1 2

PC611

10U_0805_6.3V6M

12

PL601

HCB1608KF-121T30_0603

1 2

PR601

0_0402_5%

1 2

PC606

22U_0805_6.3VAM

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TRBSTA#

COMP_CPU1

CSP1A

VSP

FBA3

VR_HOT#

SWN2

CSREF

BST1

CSSUM

BST2_1

CSREF

VR_SVID_DAT1

SWN1

CSSUMA

CSP2A

VR_SVID_DAT1

NTC_PH201

VSN

VRMP

IMONAIMONA

FBA

FB_CPU1

DIFF_CPU

DROOPA

TRBST#

CSP1A

ROSC_CPU

VR_RDYA

TSENSE

NTC_PH203

BST2

CSP3

CSP3

CSP1

CSCOMPA

COMP_CPU

VGATE

TSENSETSENSE CSP2A

ILIMA

DIFFA

ILIM_CPU

TSENSEA

VR_SVID_ALRT#

VR_SVID_CLK

FBA2

SWN1A

CSREFA

VR_ON_CPU

6132P_VCCP

CSP2

TSENSEA

VBOOT

FB_CPU

CSREFCSCOMP

COMPA

6132_VDDBP

FBA1

COMPA1

BST1_1

6132_VCC

TRBSTA#

DROOP

CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP

DROOP

FB_CPU2

FB_CPU3

CSREFACSCOMPA DROOPA

TRBST#

6132_VDDBP

CSP2

CSP1

LG1 <51>

HG1 <51>

VCCSENSE<9>

VSSSENSE<9>

VSS_AXG_SENSE<10>

VCC_AXG_SENSE<10>

VR_RDYA

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

6132_PWMA <51>

VR_SVID_CLK<9>

SWN1A <51>

SWN2 <51>

SW2 <51>

SW1 <51>

HG2 <51>

LG2 <51>

VR_HOT#<24>

SWN1 <51>

CSREFA <51>

VR_ON<24>

VGATE<6,15>

DRVEN <51>

CSREF <51>

IMVP_IMON<24>

+5VS

+3VS

+5VS

+5VS

+VCCP

+5VS

+VCCP

+3VS

CPU_B+

+5VS

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

LA-8241P

1.0

50 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

CPU Core

Option for

1 phase GFX

PUT COLSE

TO V_GT

HOT SPOT

PUT COLSE

TO VCORE

Phase 1

Inductor

PUT COLSE

TO VCORE

HOT SPOT

PUT COLSE

TO GT

Inductor

Option for

2 phase CPU

PR747

806_0402_1%

1 2

PR733

43.2K_0402_1%

1 2

PR735

0_0402_5%

1 2

PC713

.1U_0402_16V7K

1 2

PR753

0_0402_5%

1 2

PR705

1K_0402_1%

<BOM Structure>

1 2

PC707

10P_0402_50V8J

1 2

PC730

1000P_0402_50V7K

1 2

PR743

10_0402_1%

1 2

PR742

6.34K_0402_1%

12

PR704

75K_0402_1%

1 2

PR726

95.3K_0402_1%

1 2

PR707

10_0402_1%

1 2

PC710

1000P_0402_50V7K

1 2

PR724

10K_0402_1%

1 2

PR739

1K_0402_1%

1 2

PR745

8.25K_0402_1%

12

PC722

1000P_0402_50V7K

12

PR714

8.25K_0402_1%

12

PR746

8.06K_0402_1%

1 2

PH701

100K_0402_1%_TSM0B104F4251RZ

1 2

PR700

10_0402_1%

1 2

PC703

680P_0402_50V7K

1 2

PR736

0_0402_5%

@

1 2

PC705

1000P_0402_50V7K

1 2

PR713

15.8K_0402_1%

1 2

PC718

0.22U_0603_10V7K

12

PR740

6.98K_0402_1%

1 2

PC714

2.2U_0603_10V7K

1 2

PC734

.1U_0402_16V7K

1 2

PR708

1K_0402_1%

1 2

PR741

49.9_0402_1%

1 2

PR730

2.2_0603_5%

1 2

PC729

0.033U_0603_16V7

1 2

PC728

1800P_0402_50V7K

12

PH702

100K_0402_1%_TSM0B104F4251RZ

1 2

PR748

130K_0603_1%

1 2

NCP6132BMNR2G_QFN60_7X7

PU700

TSNSA 46

IOUTA 54

EN

4

VRHOT#

11

SDIO

5

ALERT#

6

ROSC

9

SCLK

7

VRDYA

3

CSCOMP

22

CSP3

25 CSREF

24 CSSUM

23

LGA 41

TRBSTA# 57

PVCC 36

BST2 40

HG2 39

SW2 38

LG2 37

PGND 35

COMP

18

VSP

14

DROOP

21

FB

17

DIFF

15

CSP1

27

SWA 42

HGA 43

VSPA 59

DIFFA 58

DROOPA 52

FBA 56

COMPA 55

CSREFA 49

CSSUMA 50

CSP2A 48

VRMP

10

VRDY

12

DRVEN

29

VSN

13 LG1 34

SW1 33

VSNA 60

ILIMA 53

VCC

1

IOUT

19

HG1 32

CSP2

26 CSCOMPA 51

TSNS

28

ILIM

20

TRBST#

16

PWM

30

BST1 31

BSTA 44

CSP1A 47

PWMA 45

VDDBP

2

VBOOT

8

PAD 61

PC704

0.033U_0603_16V7

12

PH700

220K_0402_5%_ERTJ0EV224J

12

PC717

.1U_0402_16V7K

12

PR720

0_0402_5%

1 2

PC700

0.033U_0603_16V7

1 2

PR728

0_0402_5%

1 2

PR706

165K_0402_1%

12

PC721

0.22U_0603_10V7K

12

PR750

130K_0603_1%

1 2

PR709

5.11K_0402_1%

1 2

PR717

28K_0402_1%

1 2

PR752

165K_0402_1%

1 2

PR767

13.3K_0402_1%

@

1 2

PC708

1500P_0402_50V7K

1 2

PR754

1K_0402_1%

1 2

PR718

2_0603_5%

1 2

PC701

.1U_0402_16V7K

1 2

PR722

54.9_0402_1%

1 2

PC720

0.01U_0402_25V7K

12

PH703

220K_0402_5%_ERTJ0EV224J

12

PC732

0.033U_0603_16V7

12

PR751

75K_0402_1%

1 2

PC702

1200P_0402_50V7K

1 2

PC709

0.047U_0402_16V7K

1 2

PR731

75_0402_1%

12

PC723

.1U_0402_16V7K

1 2

PR702

8.06K_0402_1%

1 2

PC735

560P_0402_50V7K

1 2

PC736

1000P_0402_50V7K

1 2

PR744

6.98K_0402_1%

1 2

PR737

0_0402_5%

1 2

PR712 6.98K_0402_1%

1 2

PR701

24.9K_0402_1%

1 2

PC706

560P_0402_50V7K

1 2

PC727

560P_0402_50V7K

1 2

PC719 2.2U_0603_10V7K

12

PR721

130_0402_1%

1 2

PR711

69.8K_0603_1%

1 2

PR716

10K_0402_1%

@

12

PC733

1500P_0402_50V7K

1 2

PR738 12.7K_0402_1%

1 2

PC725

10P_0402_50V8J

12

PC726

0.047U_0402_16V7K

12

PC716

.1U_0402_16V7K

12

PR725

0_0402_5%

1 2

PR727 1K_0402_1%

1 2

PR703

806_0402_1%

1 2

PC753

2.2U_0603_10V7K

1 2

PR732

10K_0402_5%

12

PC711

1000P_0402_50V7K

1 2

PR766

13.3K_0402_1%

1 2

PC731

0.047U_0402_16V7K

12

PR723

2.2_0603_5%

1 2

PR749

24.9K_0402_1%

1 2

PR765

0_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V1N_CPU

SNUB_GFX1

GFX_BST_1

EN_GFX

CSREF

DRVEN

V2N_CPU

GFX_BST

GFX_HG

GFX_SW

SNUB_CPU2

GFX_LG

SNUB_CPU1

VCC_GFX

CSREFA <50>

SWN1A <50>

HG1<50>

SWN2 <50>

SW1<50>

LG1<50>

HG2<50>

SW2<50>

LG2<50>

6132_PWMA<50>

CSREF <50>

SWN1 <50>

DRVEN<50>

+VCC_CORE +VCC_CORE

+5VS

CPU_B+ CPU_B+

B+

+VCC_GFXCORE_AXG

CPU_B+

B+

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

51 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-VCC_SAP

QC-SV 35W CPU

VID1=1.05V

IccMax=53A

Icc_Dyn=43A

Icc_TDC=32A

R_LL=1.9m ohm

OCP~65A

VCC_core

TDC 32A

Peak Current 53A

OCP current 65

Load line -1.9mV/A

FSW=300kHz

DCR 1.1mohm +/-5%

TYP MAX

H/S Rds(on) :10mohm , 14.5mohm

L/S Rds(on) :3mohm , 3.6mohm

+VCC_GFXCORE_AXG

TDC 21.5A

Peak Current 33A

OCP current 40A

Load line -3.9mV/A

FSW=300kHz

DCR 1.1mohm +/-5%

TYP MAX

H/S Rds(on) :10mohm , 14.5mohm

L/S Rds(on) :3mohm , 3.6mohm

PQ705

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PC742

4.7U_0805_25V6-K

12

PC741

4.7U_0805_25V6-K

12

PC743

4.7U_0805_25V6-K

12

PC745

680P_0402_50V7K

@

12

PR760

2K_0402_1%

12

PC752

680P_0402_50V7K@

12

PJP701

JUMP_43X118

@

11

2

2

PR755

4.7_1206_5%

@

12

PR756

4.7_1206_5%

@

12

PC751

2.2U_0603_10V7K

12

PR764

10_0402_1%

12

PJP700

JUMP_43X118

@

11

2

2

PQ704

SIR472DP-T1-GE3_POWERPAK8-5~D

4

5

1

2

3

PQ703

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PR757

10_0402_1%

12

PQ708

SIR818DP-T1-GE3_POWERPAK8-5~D

@

5

4

2

1

3

PC746

680P_0402_50V7K

@

12

PC749

4.7U_0805_25V6-K

12

PQ701

SIR472DP-T1-GE3_POWERPAK8-5~D

4

5

1

2

3

PC744

4.7U_0805_25V6-K

12

PC747

4.7U_0805_25V6-K

12

PR759

2.2_0603_5%

1 2

PQ702

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PQ707

SIR818DP-T1-GE3_POWERPAK8-5~D

@

5

4

2

1

3

+

PC724

100U_25V_M~D

1

2

+

PC712

100U_25V_M~D

1

2

PL704

0.36UH_FDU1040J-H-R36M=P3_33A_20%

1

3

4

2

PU701

NCP5911MNTBG_DFN8_2X2

DRVL 5

EN

3

VCC

4

PWM

2

BST

1

GND 6

SW 7

DRVH 8

FLAG 9

PL701

0.36UH_FDU1040J-H-R36M=P3_33A_20%

1

3

4

2

PL702

0.36UH_FDU1040J-H-R36M=P3_33A_20%

1

3

4

2

PC750

0.22U_0603_10V7K

1 2

PR758

10_0402_1%

12

PR761

0_0402_5%

12

PC740

4.7U_0805_25V6-K

12

PC739

4.7U_0805_25V6-K

12

PQ700

SIR472DP-T1-GE3_POWERPAK8-5~D

4

5

1

2

3

PR762

4.7_1206_5%@

12

PQ706

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

2

1

3

PC748

4.7U_0805_25V6-K

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LX_PCIE

+VGA_PCIEP

EN_PCIE

FB_PCIE

PCIE_B+

SNUB_PCIE

VGA_CORE_B+

EN_VGA_CORE

BST_VGA_CORE

SW _VGA_CORE

LG_VGA_CORE

VGA_CORE_5V

UG_VGA_CORE

PXS_PWREN<16,36>

GPU_VID1

<35>

VCCSENSE_VGA<38>

VSSSENSE_VGA<38>

GPU_VID0

<35>

VGA_PW RGD<17,36>

PX_MODE<24,36,53>

GPU_VID2<35>

+VGA_CORE

+VGA_PCIEP +1.0VGS

B+

+VGA_PCIEP

+3VALW

+3VS

+5VALW

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

52 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

VGA_COREP

0.95V

PR825 6.81K

1.0VVGA_PCIE

5.9K

+VGA_CORE

TDC 22A

Peak Current 30A

OCP current 36A

FSW=350kHz

DCR 1.1mohm +/-5%

TYP MAX

H/S Rds(on) :10mohm , 14.5mohm

L/S Rds(on) :3mohm , 3.6mohm

Thames XT Chelsea Pro

+VGA_PCIE

TDC 3.6A

Peak Current 5.2A

OCP current 6A

Core Voltage Level

0

1

GPU_VID0GPU_VID1

11

Chelsea Pro

GPU_VID2

0.775V

0.8V

0.825V

0.85V

0.875V

0.9V

0.925V

0.95V

11

1 10

100

011

0 01

001

000

G

D

S

PQ804

SI2301CDS-T1-GE3_SOT23-3

VGA@

2

1 3

PC830

0.1U_0402_10V7K

VGA@

12

PC806

.1U_0402_16V7K

VGA@

1 2

PR836

1K_0402_5%

VGA@

1 2

PJP804

JUMP_43X79

@

11

2

2

PC822

0.1U_0402_10V7K

VGA@

12

PR827

10K_0402_1%

VGA@

12

PR825

5.9K_0402_1%

VGA@

12

PC812

10U_0805_6.3V6M

VGA@

12

PR801

10K_0402_1%

VGA@

12

PC819

22U_0805_6.3VAM

VGA@

12

PR804

2.2K_0402_5%

VGA@

1 2

PR829

4.7_1206_5%

VGA@

12

PU801

TPS51518RUKR_QFN20_3X3

VGA@

V0

5

GSNS

1

VID0

8

PGOOD

7

SLEW 19

V5IN 15

SW 12

BST 11

MODE 16

VREF

6

V3

2

V2

3

V1

4

DRVL 14

DRVH 13

GND 17

TRIP 18

VSNS 20

PAD 21

VID1

9

EN

10

PQ802

SIR818DP-T1-GE3_POWERPAK8-5~D

VGA@

5

4

2

1

3

PR800

0_0402_5%

VGA@

1 2

PC826

680P_0603_50V7K

VGA@

12

PC804

4.7U_0805_25V6-K

VGA@

12

PC821

22U_0805_6.3VAM

VGA@

12

PC829

10P_0402_50V8J

VGA@

12

PR815

76.8K_0402_1%

VGA@

12

PC810

10U_0805_6.3V6M

VGA@

12

PJP800

JUMP_43X118

@

11

2

2

PL800

0.36UH_FDU1040J-H-R36M=P3_33A_20%

VGA@

1 2

PR811

5.11K_0402_1%

VGA@

1 2

PJP805

JUMP_43X79

@

11

2

2

PR833

105K_0402_1%

VGA@

12

PC824

22U_0805_6.3VAM

VGA@

12

PQ800

SIR472DP-T1-GE3_POWERPAK8-5~D

VGA@

4

5

1

2

3

PR830

0_0402_5%

VGA@

12

PC828

10P_0402_50V8J

VGA@

1 2

PR802

2.2_0603_5%

VGA@

12

PR807

43K_0402_1%

1 2

PC805

0.1U_0603_25V7K

VGA@

1 2

PC825

22P_0402_50V8J

VGA@

12

PU800

SY8036LDBC_DFN10_3x3

VGA@

EN

5

PG 4

LX 3

FB 6

SVIN

8

TP

11

LX 2

PVIN

10

SS

7

PVIN

9

LX

1

PC823

0.1U_0402_10V7K

VGA@

12

PC813

1000P_0603_50V7K

@

12

PQ801

SIR818DP-T1-GE3_POWERPAK8-5~D

VGA@

5

4

2

1

3

PR839

0_0402_5%~D

@

1 2

+

PC800

470U_D2_2VM_R4.5M

VGA@

1

2 3

PR810

5.11K_0402_1%

VGA@

1 2

PC807

1U_0603_10V6K

VGA@

1 2

PC814

4700P_0402_25V7K

VGA@

1 2

PR808

4.7_1206_5%

@

12

PR838

0_0402_5%~D

@

1 2

PR803

10K_0402_1%

VGA@

1 2

PR826

200K_0402_5%

VGA@

1 2

PL801

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

VGA@

1 2

PR813

5.11K_0402_1%

VGA@

1 2

PR828

47K_0402_5%

@

12

PC801

0.1U_0402_25V6

VGA@

12

PC802

2200P_0402_50V7K

VGA@

12

PR834

2.49K_0402_1%

VGA@

1 2

PC803

4.7U_0805_25V6-K

VGA@

12

PR814

2.49K_0402_1%

VGA@

12

G

D

S

PQ803

2N7002KW _SOT323-3

VGA@

2

13

PR835

0_0402_5%

VGA@

1 2

+

PC809

470U_D2_2VM_R4.5M

VGA@

1

2 3

PC811

10U_0805_6.3V6M

VGA@

12

PR837

1K_0402_5%

VGA@

1 2

PC818

22U_0805_6.3VAM

VGA@

12

PC820

22U_0805_6.3VAM

VGA@

12

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

FB_VDDCIP

LX_VDDCIP

EN_VDDCIP

VDDCI_VID <35>

PX_MODE<24,36,52>

VDDCI_SEN <38>

+VDDCIP

+3VALW

+3VGS

+VDDCIP +VDDCI

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

53 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

+VDDCIP

FB=0.6Volt

Low 0.9V

1VHigh

VDDCI_VID

+VDDCI

TDC 2.8A

Peak Current 4A

OCP current 6A

PR1006

10_0402_5%

VGA@

1 2

PJ1000

JUMP_43X79

@

1

122

PR1001

4.7_1206_5%

VGA@

12

PC1000

22P_0402_50V8J

VGA@

12

PR1003

4.99K_0402_1%

VGA@

1 2

PL1000

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

VGA@

1 2

PC827

0.1U_0402_10V7K

VGA@

12

PR1007

29.4K_0402_1%

VGA@

12

PR1004

0_0402_5%

VGA@

12

PR1008

10K_0402_5%

VGA@

12

G

D

S

PQ1000

2N7002W -T/R7_SOT323-3

VGA@

2

13

PC1004

0.1U_0402_10V7K

VGA@

12

PR1009

10K_0402_5%

VGA@

12

PC1001

22U_0805_6.3V6M

VGA@

12

PR1000

10K_0402_1%

VGA@

12

PC1003

22U_0805_6.3V6M

VGA@

12

PR1010

100K_0402_5%

@

12

PC1005

22U_0805_6.3V6M

VGA@

12

PC1002

680P_0603_50V7K

VGA@

12

PU1000

SY8036LDBC_DFN10_3x3

VGA@

EN

5

PG 4

LX 3

FB 6

SVIN

8

TP

11

LX 2

PVIN

10

SS

7

PVIN

9

LX

1

PR1002 10K_0402_5%

VGA@

1 2

PR1005

1M_0402_5%

@

1 2

PJ1001

PAD-OPEN 4x4m

@

1 2

PC1006

4700P_0402_25V7K

@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCCP

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_GFXCORE_AXG

+VCCP

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

54 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PROCESSOR DECOUPLING

+VCC_CORE +VCC_GFXCORE_AXG

Socket Bottom

Socket Top

5 x 22 µF (0805)

5 x (0805) no-stuff

sites

7 x 22 µF (0805)

2 x (0805) no-stuff

sites

Below is 458544_CRV_PDDG_0.5 Table 5-8.

PC1212

22U_0805_6.3V6M

1

2

PC1218

22U_0805_6.3V6M

1

2

PC1215

22U_0805_6.3V6M

1

2

+

PC1257

330U_D2_2VM_R9M

1

2 3

PC1239

22U_0805_6.3V6M

1

2

+

PC1261

330U_D2_2V_Y

@

1

2

+

PC1246

330U_D2_2V_Y

1

2

PC1231

22U_0805_6.3V6M

1

2

PC1235

22U_0805_6.3V6M

1

2

PC1228

22U_0805_6.3V6M

1

2

PC1229

22U_0805_6.3V6M

1

2

PC1205

10U_0805_6.3VAM

1

2

PC1216

22U_0805_6.3V6M

1

2

+

PC1200

330U_D2_2VM_R9M

1

2

PC1207

10U_0805_6.3VAM

1

2

PC1249

22U_0805_6.3V6M

1

2

PC1202

10U_0805_6.3VAM

1

2

PC1210

10U_0805_6.3VAM

1

2

PC1204

10U_0805_6.3VAM

1

2

PC1203

10U_0805_6.3VAM

1

2

PC1208

10U_0805_6.3VAM

1

2

PC1214

22U_0805_6.3V6M

1

2

+

PC1254

330U_D2_2VM_R9M

1

2

+

PC1260

330U_D2_2V_Y

1

2

PC1233

22U_0805_6.3V6M

1

2

PC1256

22U_0805_6.3V6M

1

2

PC1226

22U_0805_6.3V6M

1

2

PC1251

22U_0805_6.3V6M

1

2

PC1221

22U_0805_6.3V6M

1

2

+

PC1255

330U_D2_2VM_R9M

1

2

PC1217

22U_0805_6.3V6M

1

2

PC1245

22U_0805_6.3V6M

1

2

PC1232

22U_0805_6.3V6M

1

2

PC1213

22U_0805_6.3V6M

1

2

PC1206

10U_0805_6.3VAM

1

2

PC1241

22U_0805_6.3V6M

1

2

PC1225

22U_0805_6.3V6M

1

2

PC1238

22U_0805_6.3V6M

1

2

PC1236

22U_0805_6.3V6M

1

2

PC1244

22U_0805_6.3V6M

1

2

+

PC1259

330U_D2_2VM_R9M

1

2 3

PC1250

22U_0805_6.3V6M

1

2

PC1234

22U_0805_6.3V6M

1

2

PC1252

22U_0805_6.3V6M

1

2

PC1230

22U_0805_6.3V6M

1

2

PC1237

22U_0805_6.3V6M

1

2

PC1219

22U_0805_6.3V6M

1

2

+

PC1262

330U_D2_2V_Y

@

1

2

+

PC1258

330U_D2_2V_Y

1

2

PC1240

22U_0805_6.3V6M

1

2

+

PC1247

330U_D2_2V_Y

1

2

PC1209

10U_0805_6.3VAM

1

2

PC1224

22U_0805_6.3V6M

1

2

PC1243

22U_0805_6.3V6M

1

2

PC1223

22U_0805_6.3V6M

1

2

PC1211

22U_0805_6.3V6M

1

2

PC1201

10U_0805_6.3VAM

1

2

PC1220

22U_0805_6.3V6M

1

2

PC1242

22U_0805_6.3V6M

1

2

PC1227

22U_0805_6.3V6M

1

2

PC1253

22U_0805_6.3V6M

1

2

PC1222

22U_0805_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

0.2

55 56Wednesday, February 01, 2012

2012/1/17 2013/1/16

Compal Electronics, Inc.

PROCESSOR DECOUPLING

Page 48

+1.5V/+0.75VSP: TDC:14A/0.7A

RT8207MZQW

B+

Always

DC IN +3VALWP: TDC:5.4A

+5VALWP: TDC:5.6A

RT8205LZQW(2) WQFN

Power block

CHARGER

CC:0A~3.52A

CV:13.3V(6cell)

ISL88731CHRTZ-T

SYSON

VR_ON +VCC_CORE

TDC: 32A

NCP6132BMNR2G

Page 45

Page 44

Input

Switch

Page 50/51

CPU OTP

Turn Off

Page 43

Page 44

Battery

+1.8VSP: TDC:2.6A

SY8033BDBC

SUSP#

Page 46

+VGA_CORE

TDC:23.4A

TPS51518RUKR Page 52

+VCCP: TDC:11A

TPS51212DSCR Page 47

SUSP#

+VCC_GFXCORE_AXG

TDC: 21.5A

NCP6132BMNR2G Page 50/51

+VCCSAP: TDC:4.2A

SY8037DCC

Page 49

VR_ON

+V1.05S_VCCP_PWRGOOD

+VGA_PCIEP: TDC:3.5A

SY8036LDBC Page 52

PXS_PWREN

PX_MODE

+VDDCIP: TDC:2.8A

SY8036LDBC Page 53

PX_MODE

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-8241P

1.0

56 56Wednesday, February 01, 2012

2012/01/17 2013/01/16

Compal Electronics, Inc.

PWR-PIR

Page 1

Page 1Page 1

Page 1

Solution Description

Solution DescriptionSolution Description

Solution Description Rev.

Rev.Rev.

Rev.Page#

Page#Page#

Page# Title

TitleTitle

Title

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Item

ItemItem

Item Issue Description

Issue DescriptionIssue Description

Issue DescriptionDate

DateDate

Date Request

RequestRequest

Request

Owner

OwnerOwner

Owner

1 Frank44 Charger. 11/12/08 Change PR113 from 316k to 309k for Charger IC BQ24747RHDR.

Remove PR132.

2 45 3.3VALWP/5VALWP 11/12/08 Frank

Change PR113 for temperature and voltage test.

Change PC219 from 1uF to 4.7uF.

+VDDCIP533 11/12/08 Frank Change PR1002 from 100k to 0ohm.

Remove PR1005 and PC1004.

Fine tune time sequence.

Design change.

X00

X00

X00

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