Compal LA 8371P Schematics. Www.s Manuals.com. R0.2 Schematics

User Manual: Motherboard Compal LA-8371P QML70 - Schematics. Free.

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Compal Confidential
2

2

QML70 Schematics Document
AMD Comal
APU Trinity / Hudson M3 / Thames XT M2
UMA Only / PX Muxless with BACO
3

3

2011-10-17
LA-8371P REV: 0.2

4

4

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Title

Cover Page
Size
B
Date:

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet
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Compal Confidential
Model Name : QML70
ZZZ1
1

VRAM 2G/1G
128M x16 x 8 /
64M x 16 x 8

Comal

page 24, 25

PCB 0OG LA-8371P REV0 MB

1

DA80000RG00

DDR3
Thermal Sensor

ATI Thames XT M2
uFCBGA-962

ADM1032

page 19

GFX x 16

Gen2

AMD FS1r2 APU
Trinity

DP x4 (DP0 TXP/N0 ~ 3)

+1.0VSG, +1.5VSG, +1.8VSG,
+3VSG, +VGA_CORE, +VDDCI

Page 18~25

APU HDMI
(UMA / Muxless)
DP x2 (DP2 TXP/N0 ~ 1)

Memory BUS(DDR3)

204pin DDRIII-SO-DIMM X2

Dual Channel

Page 11,12

BANK 0, 1, 2, 3

1.5V DDRIII 800~1333MHz

uPGA-722 Package

HDMI Conn.
page 29

2

+APU_CORE, +APU_CORE_NB,
+1.5V, +1.2VS, +2.5VS

LVDS Conn.

LVDS

page 28

LVDS Translator
RTD2136S-VE-CG

P_GPP x 2
GEN1

Page 6~10
2

DP x4 (DP1 TXP/N0 ~ 3)

UMI
USB 2.0 + 3.0

page 27

USB 2.0 + 3.0

page 35

FCH CRT (VGA DAC)

CRT Conn.
page 28

GPP1

GPP2

LAN(GbE)
RTL8111F-CGT

MINI Card 1
WLAN w/ BT

page 30

USB

FCH
Hudson-M3

page 35

USB3.0 Port 0
USB2.0 Port 10

USB2.0

USB2.0

page 30

page 30

USB3.0 Port 1
USB2.0 Port 11

USB2.0 Port 0

CMOS
Camera

Mini Card
(with BT)

page 28

USB2.0 Port 1

page 33

USB2.0 Port 2

USB2.0 Port 3

3.3V 48MHz

HD Audio

uFCBGA-656

USB2.0 Port 4

3.3V 24.576MHz/48Mhz

Card Reader
RTS5137-GR

SATA Gen2

page 33

page 32

port 0

port 1

port 2

3

3

RJ45

page 30

Page 13~17

+3V_PCH, +1.1VALW, +1.1VS

SATA HDD1
Conn.

page 34

SATA HDD2
Conn.

page 34

ODD
Conn.
page

34

HDA Codec
ALC269Q-VB5-GR
page 31

LPC BUS
SPI ROM
4MB
page 15

LED

SPI ROM
128KB
(Reserve)

ENE KB9012
page 39

page 37

page 37

RTC CKT.
4

Touch Pad

page 13

Int.KBD

page 38

DC/DC
Interface CKT.page

39

VGA DC/DC
Interface CKT.page

26

Power Circuit

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 40~50
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

4

page 38

B

C

D

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet
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1

DISPLAY DISTRIBUTION

CLOCK DISTRIBUTION

: LVDS PATH
: APU HDMI PATH
LVDS CONN

A_SODIMM

B_SODIMM

D

D

TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA

AMD

R

ATI VGA
1066~1600MHz

MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N

1066~1600MHz

MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N

Thames XT M2

CLK_PEG_VGA / CLK_PEG_VGA#
100MHz

APU_DISP_CLKP/N
C

AMD

100MHz

CPU FS1r2 SOCKET

APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA

APU_CLKP/N
100MHz

AMD

C

LVDS_OUT

RTD2136S-VE-CG

FCH
Hudson-M3
Internal CLK GEN

DP2_AUX

DP_IN

GPP_CLK
100MHz

32.768KHz 25MHz

LVDS Transtator

C

DP0_TXP/N[0:1]
DP0_AUXP/N
B

GPP2

GPP1

WLAN
Mini PCI Socket

B

DP0

APU

GbE LAN

DP1

PCIE_GFX[0:7]

C

PCIE_GFX[12:15]

C

VGA

PCIE_GFX[0:15]

25MHz

FCH
LS
R
A

A

CRT CONN
Compal Secret Data

Security Classification
2011/07/29

Issued Date

HDMI CONN

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

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2

Title

CLOCK / DISPLAY DISTRIBUTION
Size
Document Number
Custom QML70 LA-8371P
Date:

Rev
0.2
Sheet

W ednesday, October 19, 2011
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Voltage Rails
Power Plane

1

2

Description

S4/S5 Deep S3

S1

S3

VIN

Adapter power supply (19V)

N/A

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

N/A

+APU_CORE

Core voltage for CPU

ON

OFF

OFF

OFF

+APU_CORE_NB

Voltage for On-die VGA of APU

ON

OFF

OFF

OFF

+VGA_CORE

0.95-1.2V switched power rail

ON

OFF

OFF

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

ON

OFF

ON

+1.0VSG

1.0V switched power rail for VGA

ON

OFF

OFF

OFF

+1.1VALW

1.1V switched power rail for FCH

ON

ON

ON*

OFF

+3V_PCH

3.3V switched power rail for FCH

ON

ON

ON*

OFF

+1.1VS

1.1V switched power rail for FCH

ON

OFF

OFF

OFF

+1.2VS

1.2V switched power rail for APU

ON

OFF

OFF

OFF

+3VSG

1.8V switched power rail

ON

OFF

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDR

ON

ON

OFF

ON

+1.5VS

1.5V switched power rail

ON

OFF

OFF

OFF

+1.8VSG

1.8V switched power rail

ON

OFF

OFF

OFF

+2.5VS

2.5V for CPU_VDDA

ON

OFF

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

ON

+LAN_IO

3.3V power rail for LAN

ON

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

ON

+5VS

5V switched power rail

ON

OFF

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

ON

+RTCVCC

RTC power

ON

ON

ON

ON

4

HIGH

HIGH

ON

ON

ON

ON

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

2

BTO Option Table

EC SM Bus2 address

BOM Structure

BTO Item

PX@

Use VGA (Mux)

X76@

VRAM ID Table

AI

Use AI Charger

nonAI@

Do not use AI Charger

CARD@

Use Card Reader IC

nonCARD@

do not use Card Reader IC

X76L01@

Use Hynix GDDR3 1GB VRAM

X76L02@

Use Hynix GDDR3 2GB VRAM

X76L03@

Use Samsung GDDR3 1GB VRAM

X76L04@

Use Samsung GDDR3 2GB VRAM

930@

Use EC KB930

9012@

Use EC KB9012

3

Board ID Table for AD channel

Address

HEX

Device

Address

HEX

Smart Battery

0001 011X b

16H

ADI ADM1032

1001 101X b

9AH

AMD Thames XT M2

1000 001X b

82H

AMD FS1r2 (APU)

1001 1000 b

98H

RTD2132S (TL)

1010 1000 b

A8H

Vcc
Ra / Rc
Board ID

0
1

3.3V +/- 5%
100K +/- 5%
Rb / Rd
0 +/- 5%
8.2K +/- 5%

V AD_BID min
0 V
0.168 V

V AD_BID typ
0 V
0.250 V

V AD_BID max
0.155 V
0.362 V

FCH
SM Bus 1 address

Device

Address

HEX

DDR DIMM1

1101 000X b

D0

DDR DIMM2

1101 001X b

D2

Device

4

Address

HEX

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Clock

HIGH

Interrupts

Device

FCH
SM Bus 0 address

+VS

HIGH

3

EC SM Bus1 address

+V

HIGH

External PCI Devices
REQ#/GNT#

+VALW

S1(Power On Suspend)

x = 1 is read cmd, x= 0 is writee cmd.

IDSEL#

SLP_S3# SLP_S4# SLP_S5#

Full ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Device

SIGNAL

STATE

B

C

D

Title

Notes List
Size
B
Date:

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet
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AMD APU FS1
BATTERY
12.6V

PU101
CHARGER

BATT+

PU201
ISL6277HRTZ-T

+APU_CORE

+CPU_CORE

+APU_CORE_NB

+CPU_CORE_NB

+2.5VS

+1.5V
D

AC ADAPTOR
19V 90W

PU501
RT8207MZQW

VIN

1.025~1.475VVDD CORE 54A
0.7~1.475V

VDDNB 27.5A

+2.5VS

+2.5VS

VDDA 500mA

+1.5V

+1.5V

VDDIO 4.6A

+1.2VS

+1.2VS

VDDR 6.7A

PU702
APL5508-25DC

D

RAM DDRIII SODIMMX2
PU701
TPS51212DSCR

B+

+1.2VS

+1.5V

VDD_MEM 4A

+0.75VS

VTT_MEM 0.5A

+0.75VS +0.75VS
PU501
RT8207MZQW

PU901
TPS51212DSCR

+VGA_CORE
+VDDCI

+VDDCI

PU701
SY8036DBC

+1.1VALW

PU301
RT8205LZQW

+3VALW

VGA ATI
Whistler/Seymour/Granville

+VGA_CORE

PU902
APL5912

+1.0VSG

U19
AO4430L

+1.5VSG

0.85~1.1V

VDDC 47A

0.9~1.0V

VDDCI 4.6A

+1.0VSG

DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA

+1.5VSG

VDDR1: 3400 mA

+1.0VSG

C

+INVPWR_B+

PU401
SY8033BDBC

U71
SI4178

+5VALW

+1.8VSG

+1.8VSG

+1.8VSG

Q7
AO3404AL

U69
SI4178

+3VSG

+3VSG

+3VSG

U39
AO4430L

+1.1VS

+1.1VS

+3.3 350mA

FAN Control
APL5607

C

VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

+1.1VALW

VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA

+5VS

+5VALW
U27,U29,U30,U31
+USB_VCCA
AP2301MPG

+USB_VCCB

+3VS
+3VS

+3VS

+1.5VS

USB X4
+5V
Dual+1
2.5A

+3VALW
+3VALW

+3VALW

SATA
HDD*2
ODD*1
+5V 3A

A2VDD: 130 mA
VDDR3: 60 mA

+1.1VS

+1.1VALW

+5VS 500mA

Audio Codec
ALC269-GR

EC
ENE KB9012

+5V 45mA

+3.3VALW 30mA
+3.3VS 3mA

+3.3VS 25mA

LAN
RTL8111F

Mini Card

+3.3VALW 201mA

+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA

RTC
Bettary

A

Issued Date

VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA

VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA

GND

VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S

RTC BAT

VDDBT_RTC_G

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

A

Title

POWER DELIVERY CHART
Size
Document Number
Custom QML70 LA-8371P
Date:

4

B

Compal Secret Data

Security Classification

5

2.4 A

FCH AMD Hudson M2/M3

B+ 300mA

+3.3V

+1.5VSG

PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA

+3VS

LCD panel
17.3"

B

VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8

+1.5VSG

2

Rev
0.2

Wednesday, October 19, 2011
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18 PCIE_CRX_GTX_P[0..15]

PCIE_CTX_GRX_P[0..15] 18

18 PCIE_CRX_GTX_N[0..15]

PCIE_CTX_GRX_N[0..15] 18

E

JCPU1A

WLAN

30
30
33
33

PCIE_DTX_C_CRX_P1
PCIE_DTX_C_CRX_N1
PCIE_DTX_C_CRX_P2
PCIE_DTX_C_CRX_N2

AE5
AE6
AD8
AD7
AC9
AC8
AC5
AC6

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

13
13
13
13
13
13
13
13

UMI_MTX_C_CRX_P0
UMI_MTX_C_CRX_N0
UMI_MTX_C_CRX_P1
UMI_MTX_C_CRX_N1
UMI_MTX_C_CRX_P2
UMI_MTX_C_CRX_N2
UMI_MTX_C_CRX_P3
UMI_MTX_C_CRX_N3

AG8
AG9
AG6
AG5
AF7
AF8
AE8
AE9

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

+1.2VS

1
R1

2 P_ZVDDP
196_0402_1%

AG11

P_ZVDDP
CONN@

GPP

LAN
2

P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15

UMI

1

AB8
AB7
AA9
AA8
AA5
AA6
Y8
Y7
W9
W8
W5
W6
V8
V7
U9
U8
U5
U6
T8
T7
R9
R8
R5
R6
P8
P7
N9
N8
N5
N6
M8
M7

GRAPHICS

PCI EXPRESS

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15

AB2
AB1
AA3
AA2
Y5
Y4
Y2
Y1
W3
W2
V5
V4
V2
V1
U3
U2
T5
T4
T2
T1
R3
R2
P5
P4
P2
P1
N3
N2
M5
M4
M2
M1

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15

P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

AD5
AD4
AD2
AD1
AC3
AC2
AB5
AB4

P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AG2
AG3
AF4
AF5
AF1
AF2
AE2
AE3

P_ZVSS

PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_CTX_DRX_P1
PCIE_CTX_DRX_N1
PCIE_CTX_DRX_P2
PCIE_CTX_DRX_N2

C35
C36
C71
C72

1
1
1
1

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

UMI_CTX_MRX_P0
UMI_CTX_MRX_N0
UMI_CTX_MRX_P1
UMI_CTX_MRX_N1
UMI_CTX_MRX_P2
UMI_CTX_MRX_N2
UMI_CTX_MRX_P3
UMI_CTX_MRX_N3

C37
C38
C39
C40
C41
C42
C43
C44

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

AH11 P_ZVSS

1
R2

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

1

PCIE_CTX_C_DRX_P1
PCIE_CTX_C_DRX_N1
PCIE_CTX_C_DRX_P2
PCIE_CTX_C_DRX_N2

30
30
33
33

UMI_CTX_C_MRX_P0
UMI_CTX_C_MRX_N0
UMI_CTX_C_MRX_P1
UMI_CTX_C_MRX_N1
UMI_CTX_C_MRX_P2
UMI_CTX_C_MRX_N2
UMI_CTX_C_MRX_P3
UMI_CTX_C_MRX_N3

LAN
2

WLAN

13
13
13
13
13
13
13
13

2
196_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2

3

3

Power Sequence of APU
+1.5V
+2.5VS

Group A

+1.5VS
+CPU_CORE
Group B

+CPU_CORE_NB

4

4

+1.2VS

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

FS1r2 PCIE/UMI
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

6

of

53

A

B

C

D

E

1

1

JCPU1B

11
11
11
11

DDRA_SMA0
U20
DDRA_SMA1
R20
DDRA_SMA2
R21
DDRA_SMA3
P22
DDRA_SMA4
P21
DDRA_SMA5
N24
DDRA_SMA6
N23
DDRA_SMA7
N20
DDRA_SMA8
N21
DDRA_SMA9
M21
DDRA_SMA10
U23
DDRA_SMA11 M22
DDRA_SMA12
L24
DDRA_SMA13 AA25
DDRA_SMA14
L21
DDRA_SMA15
L20
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM[7..0]

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

2

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

11
11
11
11

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

11 DDRA_ODT0
11 DDRA_ODT1
11 DDRA_SCS0#
11 DDRA_SCS1#
11 DDRA_SRAS#
11 DDRA_SCAS#
11 DDRA_SWE#

E14
J17
E21
F25
AD27
AC23
AD19
AC15

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

T21
T22
R23
R24

DDRA_CKE0
DDRA_CKE1

H28
H27

DDRA_ODT0
DDRA_ODT1

Y25
AA27

DDRA_SCS0#
DDRA_SCS1#

V22
AA26

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

V21
W24
W23

MEM_MA_RST# H25
MEM_MA_EVENT# T24

11 MEM_MA_RST#
11 MEM_MA_EVENT#
+MEM_VREF
+1.5V

15mil

U24
U21
L23

DDRA_SDQS0 G14
DDRA_SDQS0# H14
DDRA_SDQS1 G18
DDRA_SDQS1# H18
DDRA_SDQS2
J21
DDRA_SDQS2# H21
DDRA_SDQS3 E27
DDRA_SDQS3# E26
DDRA_SDQS4 AE26
DDRA_SDQS4# AD26
DDRA_SDQS5 AB22
DDRA_SDQS5# AA22
DDRA_SDQS6 AB18
DDRA_SDQS6# AA18
DDRA_SDQS7 AA14
DDRA_SDQS7# AA15

11 DDRA_CKE0
11 DDRA_CKE1

3

JCPU1C

MEMORY CHANNEL A

11 DDRA_SMA[15..0]

1
R3

2 M_ZVDDIO
39.2_0402_1%

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MA_CS_L0
MA_CS_L1
MA_RAS_L
MA_CAS_L
MA_WE_L

M_ZVDDIO

H17
F17
E19
J19
G16
H16
H19
F19

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

H20
F21
J23
H23
G20
E20
G22
H22

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

G24
E25
G27
G26
F23
H24
E28
F27

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_RESET_L
MA_EVENT_L
M_VREF

MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_ODT0
MA_ODT1

W21

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_CKE0
MA_CKE1

W20

E13
J13
H15
J15
H13
F13
F15
E15

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1

DDRA_SDQ[63..0]

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

11

MEMORY CHANNEL B

12 DDRB_SMA[15..0]

12
12
12
12

AB28 DDRA_SDQ32
AC27 DDRA_SDQ33
AD25 DDRA_SDQ34
AA24 DDRA_SDQ35
AE28 DDRA_SDQ36
AD28 DDRA_SDQ37
AB26 DDRA_SDQ38
AC25 DDRA_SDQ39
Y23 DDRA_SDQ40
AA23 DDRA_SDQ41
Y21 DDRA_SDQ42
AA20 DDRA_SDQ43
AB24 DDRA_SDQ44
AD24 DDRA_SDQ45
AA21 DDRA_SDQ46
AC21 DDRA_SDQ47

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM[7..0]

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

12
12
12
12

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

12 DDRB_ODT0
12 DDRB_ODT1
12 DDRB_SCS0#
12 DDRB_SCS1#
12 DDRB_SRAS#
12 DDRB_SCAS#
12 DDRB_SWE#

AA16 DDRA_SDQ56
Y15 DDRA_SDQ57
AA13 DDRA_SDQ58
AC13 DDRA_SDQ59
Y17 DDRA_SDQ60
AB16 DDRA_SDQ61
AB14 DDRA_SDQ62
Y13 DDRA_SDQ63

T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

U27
T28
K28

MB_BANK0
MB_BANK1
MB_BANK2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

D14
A18
A22
C25
AF25
AG22
AH18
AD14

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

12 DDRB_CKE0
12 DDRB_CKE1

AA19 DDRA_SDQ48
AC19 DDRA_SDQ49
AC17 DDRA_SDQ50
AA17 DDRA_SDQ51
AB20 DDRA_SDQ52
Y19 DDRA_SDQ53
AD18 DDRA_SDQ54
AD17 DDRA_SDQ55

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

12 MEM_MB_RST#
12 MEM_MB_EVENT#

R26
R27
P27
P28

DDRB_CKE0
DDRB_CKE1

J26
J27

DDRB_ODT0
DDRB_ODT1

W27
Y28

DDRB_SCS0#
DDRB_SCS1#

V25
Y27

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

V24
V27
V28

MEM_MB_RST#
J25
MEM_MB_EVENT# T25

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

A14
B14
D16
E16
B13
C13
B16
A16

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

C17
B18
B20
A20
E17
B17
B19
C19

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

C21
B22
C23
A24
D20
B21
E23
B23

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

E24
B25
B27
D28
B24
D24
D26
C27

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDRB_SDQ[63..0]

12

2

AG26 DDRB_SDQ32
AH26 DDRB_SDQ33
AF23 DDRB_SDQ34
AG23 DDRB_SDQ35
AG27 DDRB_SDQ36
AF27 DDRB_SDQ37
AH24 DDRB_SDQ38
AE24 DDRB_SDQ39
AE22 DDRB_SDQ40
AH22 DDRB_SDQ41
AE20 DDRB_SDQ42
AH20 DDRB_SDQ43
AD23 DDRB_SDQ44
AD22 DDRB_SDQ45
AD21 DDRB_SDQ46
AD20 DDRB_SDQ47
AF19 DDRB_SDQ48
AE18 DDRB_SDQ49
AE16 DDRB_SDQ50
AH16 DDRB_SDQ51
AG20 DDRB_SDQ52
AG19 DDRB_SDQ53
AF17 DDRB_SDQ54
AD16 DDRB_SDQ55

3

AG15 DDRB_SDQ56
AD15 DDRB_SDQ57
AG13 DDRB_SDQ58
AD13 DDRB_SDQ59
AG16 DDRB_SDQ60
AF15 DDRB_SDQ61
AE14 DDRB_SDQ62
AF13 DDRB_SDQ63

Place them close to APU within 1"
CONN@
CONN@

EVENT# pull high

LOTES_ACA-ZIF-109-P12-A_FS1R2

LOTES_ACA-ZIF-109-P12-A_FS1R2

0.75V reference voltage

+1.5V
2

+1.5V
4

4

R4
1K_0402_1%
2 1K_0402_5%

MEM_MA_EVENT#

R6

1

2 1K_0402_5%

MEM_MB_EVENT#

15mil
1

1

+MEM_VREF

2

R5

1

R7
1K_0402_1%
1

2

2
C45
1000P_0402_50V7K

1

C46
0.1U_0402_16V7K

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

FS1r2 DDRIII Memory I/F
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

7

of

53

A

B

C

D

E

JCPU1D
ANALOG/DISPLAY/MISC

DP2_TXP1
DP2_TXN1

K8
K7
J6
J5

13
13

100P_0402_50V8J

C597

47

APU_SVT

14
14

APU_SIC
APU_SID

APU_SIC
APU_SID

13 APU_RST#
13 APU_PWRGD

EMI request for ESD protection
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

As close as U2

47 APU_VDD_RUN_FB_L

Route as differential
with VSS_SENSE

DISP_CLKIN_H
DISP_CLKIN_L

B3
A3

SVC
SVD

C3

SVT

AG12
AH12

SIC
SID

AF10
AB12

RESET_L
PWROK

AC10
APU_THERMTRIP# AE12
ALERT_L
AF12

13 APU_PROCHOT#

CLKIN_H
CLKIN_L

R541
R542
R543
R544
R545
R546
R547

1
1
1
1
1
1
1

2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

H10
J10
F10
G10
F9
G9
H9

R28

1

2 0_0402_5%

B4
C5
A4
A5
C4
B5

47 APU_VDDNB_SEN
47 APU_VDD_SEN

PROCHOT_L
THERMTRIP_L
ALERT_L

C1 DP_AUX_ZVSS

TEST6
TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35

AD12
M18
N18
F11
G11
H11
J11
F12 APU_TEST18
G12 APU_TEST19
J12 APU_TEST20
H12 APU_TEST24
AE10 TEST25_H
AD10 TEST25_L
L10
M10
P19
R19
K22 APU_TEST31
T19
N19
AA12 APU_TEST35

TEST4
TEST5

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE

C6 DP_ENBKL
B6
A6 DP_INT_PWM

DP_AUX_ZVSS

FS1R2
DMAACTIVE_L

RSVD1
RSVD2
RSVD3
RSVD4

+1.5V

+3VS

R615
R10
1K_0402_5% 1K_0402_5%
@

DP_ENBKL 10

R11
10K_0402_5%

DP_INT_PWM 10
R13

2 150_0402_1%

1

T1
T2
T3
T4
T5
T6

T7
T8

Q101
1

APU_PROCHOT#

3

H_PROCHOT#_EC 37,47

MMBT3904_NL_SOT23-3

+1.5VS
R14
R15
R16
R17
R20
R21

1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
510_0402_1%
510_0402_1%

1
1
1
1
1
1

2
2
2
2
2
2

R22

1

2 39.2_0402_1%

R23
R24
R25

1
1 @
1

2 300_0402_5%
2 300_0402_5%
2 10K_0402_5%

+1.5V

Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately

THERMTRIP shutdown
temperature: 125 degree
R614
1K_0402_5%
@

+1.2VS

R18
1K_0402_5%

R19
10K_0402_5%
@

APU_THERMTRIP#

2

Q2
1

3

H_THERMTRIP# 14

MMBT3904_NL_SOT23-3 @

W10 FS1R2
AC12

+1.5V
+3VALW

for issue, HDMI no display @ DOS Mode
R560 1

ALLOW_STOP 13

P18
R18

R12
10K_0402_5%

C

2

APU_SVC
APU_SVD

DP2_TXP3
DP2_TXN3

Asserted as an input to force the
processor into the HTC-active state +1.5VS

HDMI_DET 10
ML_VGA_HPD 10
LVDS_HPD_R 10

E

@

1

47
47

DP2_TXP2
DP2_TXN2

D3
E3
D7
E7
F7
G7

B

2

@

100P_0402_50V8J
C598

APU_PWRGD

1

AB11
AA11

13 APU_DISP_CLKP
13 APU_DISP_CLKN

APU_RST#

2

AE11
AD11

APU_CLKP
APU_CLKN

LVDS

1

1

2 0.1U_0402_16V7K DP2_TXP1 L5
2 0.1U_0402_16V7K DP2_TXN1 L6

1 1.8K_0402_5%

2

1
1

Place near APU

1 1.8K_0402_5%

2

1

C51
C52

DP_BLON
DP_DIGON
DP_VARY_BL

2

R30

2 2
B

DP2_TXP0
DP2_TXN0

DP1_TXP3
DP1_TXN3

DP5_AUXP
DP5_AUXN

G5
G6

R40

DP2_AUXN

E

2 0.1U_0402_16V7K DP2_TXP0 L9
2 0.1U_0402_16V7K DP2_TXN0 L8

F5
F6

DP2_AUXP

C

2 0.1U_0402_16V7K DP1_TXP3 F2
2 0.1U_0402_16V7K DP1_TXN3 F1

1
1

DP4_AUXP
DP4_AUXN

DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

To LVDS
Translater

2

1
1

C47
C48

To FCH

DP1_TXP2
DP1_TXN2

DP2_AUXP_C 27
DP2_AUXN_C 27

1 1.8K_0402_5%

1

C61
C62

DP1_TXP1
DP1_TXN1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

1 1.8K_0402_5%

2

1

2 0.1U_0402_16V7K DP1_TXP2 G3
2 0.1U_0402_16V7K DP1_TXN2 G2

1
1

E5
E6

2

ML_VGA_AUXN R9

2 2

1
1

To FCH for RGB

ML_VGA_AUXP R8

2

C59
C60

ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15

2

2 0.1U_0402_16V7K DP1_TXP1 H2
2 0.1U_0402_16V7K DP1_TXN1 H1

C49
C50

1
1

1

1
1

D5 DP2_AUXP
D6 DP2_AUXN

To HDMI

1

27 DP2_TXP1_C
27 DP2_TXN1_C

C57
C58

DP1_TXP0
DP1_TXN0

DP2_AUXP
DP2_AUXN

HDMI_CLK 29
HDMI_DATA 29
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

2

27 DP2_TXP0_C
27 DP2_TXN0_C

2 0.1U_0402_16V7K DP1_TXP0 H5
2 0.1U_0402_16V7K DP1_TXN0 H4

RSVD

15 ML_VGA_TXP3
15 ML_VGA_TXN3

1
1

CLK

15 ML_VGA_TXP2
15 ML_VGA_TXN2

C55
C56

DP1_AUXP
DP1_AUXN

E1 ML_VGA_AUXP C53
E2 ML_VGA_AUXN C54

DP3_AUXP
DP3_AUXN

SER.

15 ML_VGA_TXP1
15 ML_VGA_TXN1

DP0_TXP3
DP0_TXN3

D1
D2

JTAG

15 ML_VGA_TXP0
15 ML_VGA_TXN0

DP0_TXP2
DP0_TXN2

DP0_AUXP
DP0_AUXN

1

HDMI_CLKP
HDMI_CLKN

HDMI_CLKP J3
HDMI_CLKN J2

DISPLAY PORT MISC.

HDMI_TX0P K2
HDMI_TX0N K1

TEST

HDMI_TX0P
HDMI_TX0N

HDMI

DISPLAY PORT 0

29
29

DP0_TXP1
DP0_TXN1

DISPLAY PORT 1

HDMI_TX1P
HDMI_TX1N

DP0_TXP0
DP0_TXN0

DISPLAY PORT 2

29
29

HDMI_TX1P K5
HDMI_TX1N K4

29
29
1

L3
L2

CTRL

HDMI_TX2P
HDMI_TX2N

HDMI_TX2P
HDMI_TX2N

2 0_0402_5%

EC_THERMTRIP# 37

T9
T10

Y10
AA10
Y12
K21

SENSE

29
29

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

3

3

CPU TSI interface level shift

R37

1
1
1

R48

1

@
@
@

2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%

APU_SVT
APU_SVC

+3VS

31.6K_0402_1%
1 R33
2
@
31.6K_0402_1%

ALERT_L

2 1K_0402_5%

ALLOW_STOP

2 1K_0402_5%

APU_SIC

3

Q4
1

EC_SMB_DA

1
R43

D

@

2
0_0402_5%

EC_SMB_DA2 19,27,37

To EC

BSH111 1N_SOT23-3
@

2 1K_0402_5%

R41 1

1

@

2 300_0402_5%

APU_RST#

R68

1

@

2 300_0402_5%

APU_PWRGD

G

R89

1

APU_SIC

3

R49

2
0_0402_5%

9

1

2 10K_0402_5%

11

R47

1

2 10K_0402_5%

13

R50

1

2 10K_0402_5%

15

Q5
1

17
EC_SMB_CK

1
R54

D

S

+1.5VS

@

2 0_0402_5%

R44

APU_SID
2

R608 1

3

7
APU_TRST#

APU_SID

4

2
0_0402_5%

+1.5V

JHDT1
1
R36
1K_0402_5%

APU_SVD

2 1K_0402_5%

HDT Debug conn
+1.5V

5

S

R607 1

2 0.1U_0402_16V4Z

1 R34
2
@
30K_0402_1%

G

R45

@

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

2

APU_TCK

R31

1

2 1K_0402_5%

4

APU_TMS

R38

1

2 1K_0402_5%

6

APU_TDI

R39

1

2 1K_0402_5%

8

APU_TDO

10

APU_PWRGD

12

APU_RST#

14

APU_DBRDY
APU_DBREQ# R51

1

2 300_0402_5%

1

R35

1

2

R32

2 C63

2

1 R59

+1.5VS

+1.5V

BSH111, the Vgs is:
min = 0.4V
Max = 1.3V

@

+1.5V

EC_SMB_CK2 19,27,37

To EC

19

16
18

R52

1

2 0_0402_5% APU_TEST19

20

R55

1

2 0_0402_5% APU_TEST18
4

BSH111 1N_SOT23-3
R53

1

2 300_0402_5%

APU_RST#

R56

1
R58

1

2 300_0402_5%

APU_PWRGD

R57

1

2 1K_0402_5%

APU_SIC

R46

1

2 1K_0402_5%

APU_SID

R613 1

2 1K_0402_5%

ALERT_L

2 1K_0402_5%

ALLOW_STOP

R582 1

@

A

@

SAMTE_ASP-136446-07-B
CONN@

2
0_0402_5%

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

FS1r2 Display/MISC/HDT
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

8

of

53

A

Power Name
VDD
+CPU_CORE

60A

VDDNB
+CPU_CORE_NB

29A

VDDIO
+1.5V

C

D

E

JCPU1F

VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23

+APU_CORE_NB

K13
K12

+APU_CORE_NB_CAP

T23
T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28

+1.5V

1
2

1
2

1

C64
22U_0603_6.3V6K
2
1
4.7U_0402_6.3V6M

A

2

3

Demo Board Capacitor

+VDDA_APU

1

2

C69

10U_0603_6.3V6K
C68

10U_0603_6.3V6K
C65

2

10U_0603_6.3V6K

2

1

0.22U_0402_6.3V6K

C67
10U_0603_6.3V6K
2
1

2

1

VDDR decoupling

C358

2

1

0.22U_0402_6.3V6K

2

1

C111

2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

1

1000P_0402_50V7K

1

VDDA

C109

C66
10U_0603_6.3V6K
2
1

+1.2VS

180P_0402_50V8J

C70
10U_0603_6.3V6K
2
1

1

40mil

C114

2

0.22U_0402_6.3V6K

C113

3300P_0402_50V7K

C112

1

2

22U_0603_6.3V6M

C108

2

22U_0603_6.3V6M

C107

1

4

L1
FBMA-L11-201209-221LMA30T_0805
2
1

1

180P_0402_50V8J

2

C94

1

0.22U_0402_6.3V6K

2

C93

1

0.22U_0402_6.3V6K

2

C92

1

0.22U_0402_6.3V6K

2

C91

1

0.22U_0402_6.3V6K

2

C90

1

0.22U_0402_6.3V6K

2

C89

2

1

0.22U_0402_6.3V6K

1

2

+APU_CORE_NB_CAP

180P_0402_50V8J

2

C99

1

180P_0402_50V8J

2

C98

1

1

C88

2

C87

1

4.7U_0603_6.3V6K

2

C86

1

4.7U_0603_6.3V6K

C85

2

4.7U_0603_6.3V6K

1

4.7U_0603_6.3V6K

2

C84

1

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

C82

22U_0603_6.3V6M

C81

AG10
AH8
AH9
AH10
C105

AB10

VDDR_1
VDDR_2
VDDR_3
VDDR_4

2

A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12

VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143

CONN@

180P_0402_50V8J

2

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

1

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

C104

1

1000P_0402_50V7K

2

C359

1

0.22U_0402_6.3V6K

2

C103

1

0.22U_0402_6.3V6K

2

C102

C101

1

180P_0402_50V8J

C100

2

180P_0402_50V8J

1

AH6
AH5
AH4
AH3
AH7

2

2

across VDDIO and VSS
split

+1.5V

1

1

0.22U_0402_6.3V6K

VDDP decoupling

2

22U_0603_6.3V6M

+1.2VS

VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36

1

C97

3

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18

C80

H26
K20
J28
K23
K26
L22
L25
L28
M20
M23
M26
N22
N25
N28
P20
P23
P26
AA28

+1.5V

2

0.22U_0402_6.3V6K

VDDNB_CAP_1
VDDNB_CAP_2

1

@

22U_0603_6.3V6M

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12

C11
C12
D9
D8
D12
D11
B11
A12
B10
E12
B9

+1.5V

C96

C8
D10
B8
B12
C9
A9
A10
A8
A11
E10
E11
C10

+APU_CORE_NB

R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11

C79

2

+APU_CORE

VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62

2

0.5A

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31

1

JCPU1E
F8
H6
J1
J14
P6
P10
J16
J18
J9
K19
K3
K17
M3
K6
V10
V18
V3
F3
L18
V6
W1
T18
Y14
AA1
AB6
AC1
R1
P3
K10
H3
M19

2

+APU_CORE

5A / 3.5A

VDDA
+2.5VS

+2.5VS

J20
L4
R7
W18
A15
AB17
AC22
AE21
AF24
AH23
AH25
B7
C14
C16
C2
C20
C22
C24
C26
C28
D13
D15
D17
D19
D23
D25
D27
E4
E9
F14
F16
F18
F20
F22
F26
F28
G13
G15
G17
G19
G21
G23
G25
G4
J22
J24
J4
J7
K11
K14
K9
AC11
L19
L7
M11
AF11
V19
V9
W16
W4
W7
Y11
Y20
Y22
Y9
A17
A13
K16
F24
G8
H7
J8

3.2A

VDDP / VDDR
+1.2VS
1

B

Consumption

CORE_NB
22uF x 2
10uF x 1
0.22uF x 2
180pF x 3

CORE_NB_CAP
22uF x 2

VDDP
22uF x 1
10uF x 3
0.22uF x 2
180pF x 2
1nF x 1

VDDR
10uF x 3
0.22uF x 2
1nF x 1
180pF x 2

VDDA
4.7uF x 1
0.22uF x 1
3.3nF x 1

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

APU_CORE
22uF x 7
0.22uF x 2
0.01uF x 3
180pF x 2

D

Title

FS1r2 PWR/GND
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

9

of

53

5

4

3

2

Panel PWM

1

+3VS

1

1

HPD
D

R61
47K_0402_5%

From FCH

2 0_0402_5%

ML_VGA_HPD 8

Q8
2
2
2.2K_0402_5% B

1
R65

8 DP_INT_PWM

C

1

3

E

2

R66
4.7K_0402_5%

1
R626 1

1

FCH_CRT_HPD

D

3

APU_INVT_PWM 27,28

MMBT3904_NL_SOT23-3

15 FCH_CRT_HPD

D

R62
4.7K_0402_5%
2

2

CRT HPD

S

2
G

Q6
2N7002K_SOT23-3

Translator HPD

From Translator

C

27

LVDS_HPD

LVDS_HPD

R627 1

2 0_0402_5%

+1.5VS

C

Panel ENBKL

LVDS_HPD_R 8

DP_ENBKL

DP_ENBKL

R624 1

2 0_0402_5%

ENBKL

ENBKL 37

1

8

@
R630
4.7K_0402_5%

HDMI HPD
2

From HDMI Conn
APU_HDMI_HPD

29 APU_HDMI_HPD

2
R659

@

R711 1

2 0_0402_5%

HDMI_DET 8

1
100K_0402_5%

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

FS1r2 Signal Level Shifter
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
1

10

of

53

A

B

3.56A

+1.5V

DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

7
2

7

DDRA_CKE0
DDRA_SBS2#

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

7
7

DDRA_CLK0
DDRA_CLK0#

DDRA_SCS1#

DDRA_SMA13
DDRA_SCS1#

7 DDRA_SDQS4#
7 DDRA_SDQS4

DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35

3

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
7 DDRA_SDQS6#
7 DDRA_SDQS6

DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R73
10K_0402_5%
1
2

+3VS

1

+3VS

4

C136

1

C137

R74

1

2.2U_0603_6.3V4Z

2

0.1U_0402_16V4Z
2

G1

+1.5V

DDRA_SDQ20
DDRA_SDQ21

2

0.1U_0402_16V4Z
2

DDRA_SDM2

C115
1
0.1U_0402_16V4Z

DDRA_SDQ22
DDRA_SDQ23

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

C117

2

C118

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2
C119

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C120

C121

C122

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C123

C124

1
0.1U_0402_16V4Z

1

DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3

DDRA_SDQS3# 7
DDRA_SDQS3 7

+0.75VS

+1.5V
@

DDRA_SDQ30
DDRA_SDQ31

DDRA_CKE1

0.1U_0402_16V4Z
2

2

C127

1
0.1U_0402_16V4Z

DDRA_CKE1 7

1

1

C125

1
C128

2
4.7U_0603_6.3V6K

2
0.1U_0402_16V4Z
Add C1106
20101101

DDRA_SMA15
DDRA_SMA14

2

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
+VREF_CA

DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

+VREF_DQ

15mil

DDRA_SCS0# 7
DDRA_ODT0 7
DDRA_ODT1 7

1

C135

1

2

@

DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39

2

R70
1K_0402_1%

R69
1K_0402_1%

DDRA_SBS1# 7
DDRA_SRAS# 7

+VREF_CA
DDRA_SDQ36
DDRA_SDQ37

+1.5V

+1.5V

DDRA_CLK1 7
DDRA_CLK1# 7

15mil

15mil
+VREF_DQ

1

2

C130

1

C131

R71
1K_0402_1%

2

1

2

@

+VREF_CA

1

2

C133

1

C134

R72
1K_0402_1%

2

1000P_0402_50V7K
3

DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# 7
DDRA_SDQS5 7

DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# 7
DDRA_SDQS7 7

DDRA_SDQ62
DDRA_SDQ63
MEM_MA_EVENT#

MEM_MA_EVENT# 7
FCH_SDATA0 12,14,33
FCH_SCLK0 12,14,33

+0.75VS
4

TYCO_2-2013310-1

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_A STD H:9.2mm

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


A

1

C126

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

0.1U_0402_16V4Z
2

2

C116

2

10K_0402_5%

205

Place near DIMM1

MEM_MA_RST# 7

DDRA_SDQ14
DDRA_SDQ15

C129

DDRA_SDQ32
DDRA_SDQ33

DDRA_SDM1
MEM_MA_RST#

C132

7

DDRA_SWE#
DDRA_SCAS#

1

4.7U_0603_6.3V6K

DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#

DDRA_SMA10
DDRA_SBS0#

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDRA_SMA[0..15] 7

DDRA_SDQ12
DDRA_SDQ13

4.7U_0603_6.3V6K

7
7
7

DDRA_CLK0
DDRA_CLK0#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRA_SMA[0..15]

DDRA_SDQ6
DDRA_SDQ7

2

7 DDRA_SDQS2#
7 DDRA_SDQS2

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQS0# 7
DDRA_SDQS0 7

7

DDRA_SDM[0..7] 7

1

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS0#
DDRA_SDQS0

2

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

1

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ[0..63]

DDRA_SDQ4
DDRA_SDQ5

1000P_0402_50V7K

7 DDRA_SDQS1#
7 DDRA_SDQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

0.1U_0402_16V4Z

DDRA_SDQ8
DDRA_SDQ9

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

DDRA_SDQ2
DDRA_SDQ3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

DDRA_SDM0

+1.5V

1

DDRA_SDQ0
DDRA_SDQ1

E

JDIMM1

1000P_0402_50V7K

15mil

D

0.1U_0402_16V4Z

+VREF_DQ

C

B

C

D

Title

DDRIII SO-DIMM 1
Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

11

of

53

A

B

3.56A

+1.5V

15mil
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
1

DDRB_SDQ8
DDRB_SDQ9
7 DDRB_SDQS1#
7 DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17

7 DDRB_SDQS2#
7 DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27

D

E

+1.5V

JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDRB_SDQ[0..63]

DDRB_SDQ4
DDRB_SDQ5

DDRB_SDQ[0..63]

DDRB_SDM[0..7]
DDRB_SDQS0#
DDRB_SDQS0

DDRB_SDQS0# 7
DDRB_SDQS0 7

7

DDRB_SDM[0..7] 7

DDRB_SMA[0..15]

DDRB_SMA[0..15] 7

DDRB_SDQ6
DDRB_SDQ7
1

DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
MEM_MB_RST#

MEM_MB_RST# 7

DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21

Place near DIMM2

DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23

+1.5V

DDRB_SDQ28
DDRB_SDQ29

2

0.1U_0402_16V4Z
2
C138

DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# 7
DDRB_SDQS3 7

0.1U_0402_16V4Z
2

2

C139

1
0.1U_0402_16V4Z

1

C140

1
0.1U_0402_16V4Z

1

C142

7

DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

7
7
7
7
7
7

DDRB_CLK0
DDRB_CLK0#
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#

DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#

DDRB_SDQ32
DDRB_SDQ33

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
7 DDRB_SDQS6#
7 DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R75
10K_0402_5%
1
2

1

+3VS

4

R76

206

1

0.1U_0402_16V4Z
2

2

C146

1
0.1U_0402_16V4Z

C147
1

+1.5V

C149
1
0.1U_0402_16V4Z

C150
1

C148

1

2
0.1U_0402_16V4Z
Add C1107
20101101

C151

2
4.7U_0603_6.3V6K

1
+
@

2

C152
330U_X_2VM_R6M

2

DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7

+VREF_DQ

15mil
DDRB_SDQ36
DDRB_SDQ37

1

DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39

C154
1000P_0402_50V7K

2

DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

+VREF_CA

15mil

+VREF_CA

1

2

@

1

2

15mil

+VREF_DQ

C155

1

C156

2

1

2

@

1

+VREF_CA

C158

2

1

C159

2

3

DDRB_SDQS5# 7
DDRB_SDQS5 7

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7

DDRB_SDQS7# 7
DDRB_SDQS7 7

DDRB_SDQ62
DDRB_SDQ63
MEM_MB_EVENT#

MEM_MB_EVENT# 7
FCH_SDATA0 11,14,33
FCH_SCLK0 11,14,33

+0.75VS
4

TYCO_2-2013289-1

2

10K_0402_5%

G2

2

DDRB_SMA11
DDRB_SMA7

C157

DDRB_SDM5

DDRB_SMA15
DDRB_SMA14

1

0.1U_0402_16V4Z

DDRB_SDQ40
DDRB_SDQ41

+1.5V
0.1U_0402_16V4Z
2

4.7U_0603_6.3V6K

3

1
0.1U_0402_16V4Z

C145

@

DDRB_CKE1 7

C153

DDRB_SDQ34
DDRB_SDQ35

DDRB_CKE1

0.1U_0402_16V4Z

DDRB_SDQS4#
DDRB_SDQS4

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

4.7U_0603_6.3V6K

7 DDRB_SDQS4#
7 DDRB_SDQS4

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1

0.1U_0402_16V4Z
2
C144

DDRB_SDQ30
DDRB_SDQ31

1000P_0402_50V7K

2

DDRB_CKE0

2

C143

1
0.1U_0402_16V4Z

+0.75VS
7

0.1U_0402_16V4Z
2

2

C141

1000P_0402_50V7K

+VREF_DQ

C

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


A

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_B STD H:5.2mm
B

C

D

Title

DDRIII SO-DIMM 2
Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

12

of

53

A

B

C160

C

D

E

150P_0402_50V8J
2

U2A

1

HUDSON-2

APU_CLKP
APU_CLKN

8 APU_CLKP
8 APU_CLKN

T24
T23

CLK_PEG_VGA R220 1
CLK_PEG_VGA# R221 1

18 CLK_PEG_VGA
18 CLK_PEG_VGA#

CLK_PEG_VGA_R
0_0402_5%
2
CLK_PEG_VGA#_R
0_0402_5%
2

J30
K29
H27
H28

SS

GLAN

30 CLK_PCIE_LAN
30 CLK_PCIE_LAN#

WLAN

33 CLK_PCIE_MINI1
33 CLK_PCIE_MINI1#

CLK_PCIE_LAN R90
CLK_PCIE_LAN# R91

1
1

CLK_PCIE_LAN_R
0_0402_5%
2
CLK_PCIE_LAN#_R
0_0402_5%
2

CLK_PCIE_MINI1 R93
CLK_PCIE_MINI1#R94

1
1

CLK_PCIE_MINI1_R F33
0_0402_5%
2
CLK_PCIE_MINI1#_R F31
0_0402_5%
2

J27
K26

E33
E31
M23
M24

3

M27
M26
N25
N26
R23
R24
N27
R27
R99 1

32 CLK_SD_48M

C172 1

EMI2

22_0402_5% CLK_SD_48M_R J26

2 33P_0402_50V8K

GND

2

OSC

GND

OSC

SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N

GPP_CLK6P
GPP_CLK6N
GPP_CLK7P
GPP_CLK7N

25M_X1

25M_X2

C33

25M_X2

3
R103
1M_0402_5%

1

25MHZ_20PF_X3G025000DK1H-X
C173 1
2 33P_0402_50V8K
1
R101

LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#

14M_25M_48M_OSC

C31

2
0_0402_5%

1

10P_0402_50V8J
R105
20M_0402_5%

1

NC

3

OSC

NC

2

32K_X2

2

A

B

5
P
G
5
A

P

1

4

G

Y

1
R83

@

1
R84

2
@ 100K_0402_5%

VGA_PWRGD_R

2
0_0402_5%

3

1
R85

2
0_0402_5%

+3VS
2

R87
10K_0402_5%
@

APU_PWRGD

3

R88
4.7K_0402_5%
@

1
Q10
@ MMBT3904_NL_SOT23-3

T11
1
2
R575 1
2 0_0402_5%
0_0402_5%
T12 R576
PM_CLKRUN# 1 R437
2
@
0_0402_5%

1
R579

PE_GPIO0 14,18
PE_GPIO1 14,20,37

APU_PWRGD_L 47

2
0_0402_5%

PM_CLKRUNEC# 37

AF18
AE18
AC16
AD18

PE_GPIO1 1
R92

2
10K_0402_5%
APU_PWRGD

@

S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19

G25
E28
E26
G26
F26
H7
F1
F3
E6

LPC_CLK0_EC_R R95 1 22_0402_5%
LPC_CLK0_EC
2
R96 1 22_0402_5%
2
LPC_CLK1_R
R97 1 22_0402_5%
2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0_EC 16,37
CLK_PCI_DB 33
LPC_CLK1 16
LPC_AD0 33,37
LPC_AD1 33,37
LPC_AD2 33,37
LPC_AD3 33,37
LPC_FRAME# 33,37
SERIRQ 37

R98
APU_PWRGD

1

@

APU_RST#

R100 1

32K_X1

G2

32K_X1

32K_X2

G4

32K_X2

S5_CORE_EN 37
RTC_CLK 16,37

2 22_0402_5%

C174 1

2

2
1K_0402_5%

D1

W=20mils

CLRP1
C176
SHORT PADS

for Clear CMOS

C

2

R67

3

1K_0402_5%

1

2

1

1

2
@

+RTCBATT
+CHGRTC

DAN202UT106_SC70-3
4

Compal Electronics, Inc.

Compal Secret Data
2011/07/29

Issued Date

2

1 C175

1
R104

3

APU_PG/APU_RST#/LDT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC

+RTCVCC
RTCVCC_R

2

DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.

APU_RST# 8

S5_CORE_EN

@

1

EMI request for ESD protection

ALLOW_STOP 8
APU_PROCHOT# 8
APU_PWRGD 8

2 0_0402_5%

1

2

@

As close as U2

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Close to HUDSON-M2

10P_0402_50V8J

0.1U_0402_16V4Z

+1.5VS

Security Classification

32.768KHZ 7PF Q13MC1461000100

2

C178

OSC

1

B

PCI_AD23 16
PCI_AD24 16
PCI_AD25 16
PCI_AD26 16
PCI_AD27 16
VGA_PWRGD_R 14

VGA_PWRGD_R
2
0_0402_5%

1
R102

Y1
4

@U4
@
U4
2

NC7SZ08P5X_NL_SC70-5

32K_X1

2

VGA_PWRGD

20,49 VGA_PWRGD

C177
1

2
0_0402_5%
@ C171
1
2

HUDSON-M3_FCBGA656
4

3

2

1
R80
+3V_FCH

APU_RST#
LPCCLK0

GPP_CLK5P
GPP_CLK5N

GPP_CLK8P
GPP_CLK8N

R79
8.2K_0402_5%

1

PLT_RST# 18,30,33

U3
NC7SZ08P5X_NL_SC70-5

1

PCI CLKS

APU_CLKP
APU_CLKN

25M_X1

X1
4

DISP2_CLKP
DISP2_CLKN

@
1

@
4

C

H33
H31

DISP_CLKP
DISP_CLKN

C170
150P_0402_50V8J

Y

100P_0402_50V8J

PCIE_RCLKP
PCIE_RCLKN

A

100P_0402_50V8J
C600

G30
G28

B

1

C599

CLK_CALRN

2

2

F27

2
2 33_0402_5%

1

E

APU

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

R26
T26

APU DISP

VGA

AA27
AA26
W27
V27
V26
W26
W24
W23

R78

1

8 APU_DISP_CLKP
8 APU_DISP_CLKN

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

APU_PCIE_RST#_C

B

APU_DISP_CLKP
APU_DISP_CLKN

V33
V31
W30
W32
AB26
AB27
AA24
AA23

@ C166
1
2
0.1U_0402_16V4Z

1

2 2K_0402_1% CLK_CALRN

1

PCIE_CALRP
PCIE_CALRN

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

+3V_FCH

For PCIE device reset on FS1
(GLAN, WLAN, Card Reader)

2 2

AF29
AF31

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

PCI_CLK3 16
PCI_CLK4 16

0.1U_0402_16V4Z

2 590_0402_1% PCIE_CALRP
2 2K_0402_1% PCIE_CALRN

1
1

For "EXT" CLK mode, input to PCIE,

SS
NSS

AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29

PCIRST#

AB5

PCI_CLK1 16

1

R86

+1.1VS_CKVDD

UMI_CTX_C_MRX_P0
UMI_CTX_C_MRX_N0
UMI_CTX_C_MRX_P1
UMI_CTX_C_MRX_N1
UMI_CTX_C_MRX_P2
UMI_CTX_C_MRX_N2
UMI_CTX_C_MRX_P3
UMI_CTX_C_MRX_N3

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

2

2

AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32

AF3
AF1
AF5
AG2
AF6

1U_0402_6.3V4Z

+PCIE_VDDR_FCH

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

0.1U_0402_16V4Z

R81
R82

2
2
2
2
2
2
2
2

PCI INTERFACE

UMI_CTX_C_MRX_P0
UMI_CTX_C_MRX_N0
UMI_CTX_C_MRX_P1
UMI_CTX_C_MRX_N1
UMI_CTX_C_MRX_P2
UMI_CTX_C_MRX_N2
UMI_CTX_C_MRX_P3
UMI_CTX_C_MRX_N3

1
1
1
1
1
1
1
1

LPC

6
6
6
6
6
6
6
6

C161
C162
C163
C164
C165
C167
C168
C169

APU

UMI_MTX_C_CRX_P0
UMI_MTX_C_CRX_N0
UMI_MTX_C_CRX_P1
UMI_MTX_C_CRX_N1
UMI_MTX_C_CRX_P2
UMI_MTX_C_CRX_N2
UMI_MTX_C_CRX_P3
UMI_MTX_C_CRX_N3

UMI_MTX_CRX_P0
UMI_MTX_CRX_N0
UMI_MTX_CRX_P1
UMI_MTX_CRX_N1
UMI_MTX_CRX_P2
UMI_MTX_CRX_N2
UMI_MTX_CRX_P3
UMI_MTX_CRX_N3

PCIE_RST#
A_RST#

S5 PLUS

6
6
6
6
6
6
6
6

APU_PCIE_RST#_CAE2
A_RST#_R
AD5

2 33_0402_5%

1

PCI EXPRESS INTERFACES

1

R77

A_RST#

CLOCK GENERATOR

PCI Host Bus Reset (To EC)

37

D

Title

Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

13

of

53

A

B

C

D

E

PCIE_RST2 : Reset PCIE device on Hudson2
U2D

AG19
R9
C26
T5
U4
K1
V7
R10
AF19

+3V_FCH
FCH_PCIE_WAKE#

8 H_THERMTRIP#

@
1
2 SYS_RESET#
R106 10K_0402_5%

1
2
R107 10K_0402_5%

+3VS

U2

37 EC_RSMRST#

Modify 2010212-AMD request
1
2
FCH_SCLK0
R110
10K_0402_5%
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
MINI1_CLKREQ#
R109 1
2 0_0402_5% LAN_CLKREQ#_1

11,12,33 FCH_SCLK0
11,12,33 FCH_SDATA0

SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off +3VS

33 MINI1_CLKREQ#
30 LAN_CLKREQ#

R577 2
@
VGA_PD

13 VGA_PWRGD_R
16
VGA_PD

2

2

1 0_0402_5%

R360
10K_0402_5%
@

R111 2

1

19 PEG_CLKREQ#

PEG_CLKREQ#_R

USB_OC0#: for USB3.0 w/ AI Charger (JUSB1)
USB_OC1#: for USB2.0 port (JUSB3, 4)
USB_OC2#: for USB3.0 port (JUSB2)

M7
R8
T1
P6
F5
P5
J7
T8

FCH_ODD_DA#

34 FCH_ODD_DA#

2
1
R571
10K_0402_5%

1 0_0402_5% PEG_CLKREQ#_R

@

ODD_DETECT#
AC_PRESENT_OK
USB_OC2#
USB_OC1#
USB_OC0#

34 ODD_DETECT#
37 AC_PRESENT_OK
35 USB_OC2#
35 USB_OC1#
35 USB_OC0#

AG24
AE24
AE26
AF22
AH17
AG18
AF24
AD26
AD25
T7
R7
AG25
AG22
J2
AG26
V8
W8
Y6
V10
AA8
AF25

GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD

USB 1.1

H1
H3

USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

USB_OC0#

H9
G9

USB_HSD5P
USB_HSD5N

A8
C8

USB_HSD4P
USB_HSD4N

F8
E8

USB20_P4
USB20_N4

USB_HSD3P
USB_HSD3N

C6
A6

USB20_P3
USB20_N3

USB_HSD2P
USB_HSD2N

C5
A5

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

C1
C3

USB20_P1
USB20_N1

E1
E3

USB20_P0
USB20_N0

C16
A16

USBSS_CALRP
USBSS_CALRN

FCH_SDATA1
EC_LID_OUT#
FCH_PCIE_WAKE#

+3VALW

USB 3.0

USB_SS_TX1P
USB_SS_TX1N

PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166

USB_SS_TX0P
USB_SS_TX0N

MINI1_CLKREQ#

FCH_GPIO189
FCH_GPIO190

Project SKU ID

1

1

LAN_CLKREQ#_1

EC_RSMRST#

Add Project ID Table
201011301600
+3VALW

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EMBEDDED CTRL

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

USB2.0 + 3.0, JUSB2

USB20_P10 35
USB20_N10 35

USB2.0 + 3.0, JUSB1
Hudson-M2/M3
EHCI CTL
DEV 19, Fn 2

USB20_P4 32
USB20_N4 32

Card Reader

USB20_P3 33
USB20_N3 33

Mini Card (WLAN w/ BT)

USB20_P2 28
USB20_N2 28

Camera

USB20_P1 31
USB20_N1 31

USB2.0 Conn. JUSB4

USB20_P0 31
USB20_N0 31

USB2.0 Conn. JUSB3

R112 1
R113 1

2 1K_0402_1%
2 1K_0402_1%

Hudson-M2/M3
EHCI CTL
DEV 18, Fn 2
2

+FCH_VDD_11_SSUSB_S

A14
C14

Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

C12
A12
D15
B15
E14
F14
F15
G15

USB3_TX1_P
USB3_TX1_N

H13
G13

USB3_RX1_P
USB3_RX1_N

J16
H16

USB3_TX0_P
USB3_TX0_N

J15
K15

USB3_RX0_P
USB3_RX0_N

H19
G19
G22
G21
E22
H22
J22
H21

R123 1
R125 1
APU_SIC
APU_SID

USB3_TX1_P 35
USB3_TX1_N 35
USB3_RX1_P 35
USB3_RX1_N 35
USB3_TX0_P 35
USB3_TX0_N 35

3

On board
USB Conn

USB3_RX0_P 35
USB3_RX0_N 35
2 10K_0402_5%
2 10K_0402_5%
APU_SIC 8
APU_SID 8

EC_PWM2

EC_PWM2 16

K21
K22
F22
F24
E24
B23
C24
F18

R750 2

@

1 0_0402_5%

R751 2

1 0_0402_5%

+3VS @
C838 0.1U_0402_16V7K
1
2

FCH_PWRGD

4
2

B
A

Y

2

FCH_POK 37

1

VGATE 37,47

@
MC74VHC1G08DFT2G SC70 5P
C839
U75 @
0.1U_0402_16V7K
3

FCH_SDATA0

1

2
FCH_SCLK0

2

AC_PRESENT_OK

1

ODD_DETECT#

D21
C20
D23
C22

F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17

FCH_ODD_DA#

ODD_DETECT#

HUDSON-M3_FCBGA656

1

4

For FCH internal debug use

HDA_BITCLK

1

@

2

1

@

2

1

@

2

R141
HDA_SDIN0
R145

TEST0
2.2K_0402_5%

R143
HDA_SDIN1

A

FCH_GPIO189
FCH_GPIO190
R573 2
@
1
R574 2
@
1
0_0402_5%
0_0402_5%

13,18 PE_GPIO0
13,20,37 PE_GPIO1

2

2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

USB_SS_RX2P
USB_SS_RX2N

USB20_P11 35
USB20_N11 35

Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

5

FCH_SCLK1

2

1
R139
@
1
R140
@
1
R142
@
1
R144

USB_SS_TX2P
USB_SS_TX2N

H_THERMTRIP#

@
R134
8.2K_0402_5%

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

K19
J19
J21

USB20_P10
USB20_N10

USB_HSD6P
USB_HSD6N

USB_SS_RX0P
USB_SS_RX0N

@
R133
8.2K_0402_5%

4

T34
T15

USB_OC1#

+3VS

@
1
R445
1
R131
1
R136
@
1
R137
1
R138

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#

USB_OC2#

@
R127
8.2K_0402_5%

2
100K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%

AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4

K12
K13

C10
A10

USB_SS_RX1P
USB_SS_RX1N

@
R130
8.2K_0402_5%

1
R118
1
R119
1
R120
1
R121
1
R122
1
R124
1
R126
@
1
R128
@
1
R135
1
R555 @
1
R410

3

R116 1
R117 1

31 HDA_SYNC_AUDIO
31 HDA_RST_AUDIO#

+3V_FCH

HDA_BITCLK
2 33_0402_5%
HDA_SDOUT
2 33_0402_5%
HDA_SDIN0
HDA_SDIN1
T13
T14
HDA_SYNC
33_0402_5%
2
HDA_RST#
2 33_0402_5%

HD AUDIO

R114 1
R115 1

G12
F12

USB20_P11
USB20_N11

USB_HSD7P
USB_HSD7N

USB_SS_TX3P
USB_SS_TX3N

Hudson-M2
EHCI CTL
DEV 22, Fn 2


K10
J12

E10
F10

USB_SS_RX3P
USB_SS_RX3N
31 HDA_BITCLK_AUDIO
31 HDA_SDOUT_AUDIO
31 HDA_SDIN0

1

USB_HSD8P
USB_HSD8N

USBSS_CALRP
USBSS_CALRN

2 11.8K_0402_1%

H10
G10

B11
D11

USB_HSD0P
USB_HSD0N

R108 1

H6
H5

USB_HSD9P
USB_HSD9N

RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

USB_RCOMP

P

KB_RST#
EC_SCI#
EC_SMI#

B9

USB_FSD1P/GPIO186
USB_FSD1N

G

GATE20

37
37
37

TEST0
TEST1/TMS
TEST2

G8

USB_RCOMP

USB 2.0

37

AE22

30,33,37 FCH_PCIE_WAKE#

THERMTRIP:
Need level shift from +3VALW to +1.5V

T9
T10
V9

ACPI / WAKE UP EVENTS

1

USBCLK/14M_25M_48M_OSC

GPIO

FCH_PWRGD
TEST0
TEST1
TEST2

PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD

USB OC

37 PM_SLP_S3#
37 PM_SLP_S5#
37 PBTN_OUT#

AB6
R2
W7
T3
W2
J4
N7

USB MISC

HUDSON-2
EC_LID_OUT#

37 EC_LID_OUT#

TEST1
2.2K_0402_5%
TEST2
2.2K_0402_5%

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

Hudson-M2/M3-ACPI/USB/EC
Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

14

of

53

A

B

C

D

E

U2B
HUDSON-2

SATA_TX1P
SATA_TX1N

34 SATA_FRX_DTX_N1
34 SATA_FRX_DTX_P1

AH20
AJ20

34 SATA_FTX_DRX_P2
34 SATA_FTX_DRX_N2

AJ22
AH22

34 SATA_FRX_DTX_N2
34 SATA_FRX_DTX_P2

AM23
AK23
AH24
AJ24

2

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N

AN24
AL24

SATA_RX3N
SATA_RX3P

AL26
AN26

SATA_TX4P
SATA_TX4N

AJ26
AH26

SATA_RX4N
SATA_RX4P

AN29
AL28

SATA_TX5P
SATA_TX5N

AK27
AM27

SATA_RX5N
SATA_RX5P

AL29
AN31

NC6
NC7

AL31
AL33

NC8
NC9

AH33
AH31

NC10
NC11

AJ33
AJ31

NC12
NC13

1K_0402_1% 2

1 R156

SATA_CALRP

AF28

SATA_CALRP

931_0402_1%2

1 R157

SATA_CALRN

AF27

SATA_CALRN

SATA_LED#

SATA_LED#

AG21

SATA_X1

SATA_X2

VGA_GREEN

L32

VGA_BLUE

M29

VGA_HSYNC/GPO68
VGA_VSYNC/GPO69

M28
N30

AUX_VGA_CH_P
AUX_VGA_CH_N
AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229

3

T16
33

BT_ON_FCH

BT_ON_FCH

+3VS
WL_OFF#_FCH

33 WL_OFF#_FCH

AH16
AM15
AJ16
AK15
AN16
AL16

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

VIN0/GPIO175
HW MONITOR

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN1/GPIO176
VIN2/SDATI_1/GPIO177

ODD_EN#

2

ODD_EN#

34 ODD_EN#

K6

1
R169
1
R172
1
R173

2

K5
10K_0402_5%

2

K3
10K_0402_5%

2

M6
10K_0402_5%

TEMPIN1/GPIO172

+3V_FCH
FCH_SPI_CLK_R1
4

R151 1
0_0402_5%

37,38
37,38
37,38
37,38

+3VALW
KSI4
KSI5
KSI6
KSI7

FCH_SPI_CS1#_R
2 FCH_SPI_CLK_R
FCH_SPI_MOSI_R
FCH_SPI_MISO_R
KSI4
KSI5
KSI6
KSI7

24
22
18
17
14
23
21
16
15
13

A0
B0
C0
D0
E0
A1
B1
C1
D1
E1

SEL
YA
YB
YC
YD
YE
GND
GND
GND
GND

12

FLASH_EN

2
5
6

FCH_SPI_CS1#_RR R548 1
FCH_SPI_CLK_RR R549 1

8
11

FLASH_EN 37

FCH_SPI_MOSI_RR R550 1

+3V_SPI

2

@

2

1

+3V_FCH
GBE_MDIO

C29
N2

L2

VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

P3
M1
M5

TEMPIN2/GPIO173
NC1
NC2
NC3
NC4
NC5

TEMPIN3/TALERT#/GPIO174

GBE_PHY_INTR
GBE_COL
GBE_PHY_INTR

GBE_CRS
FCH_SPI_MISO_R
FCH_SPI_MOSI_R
FCH_SPI_CLK_R1
FCH_SPI_CS1#_R
FCH_SPI_WP#

2

R152 1

2 150_0402_1%

1
R147
1
R148
1
R149
1
R150

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

R154 1

2 150_0402_1%

R155 1

2 150_0402_1%

FCH_SPI_WP# 37
@ R153

FCH_CRT_R 28

FCH_SPI_CLK

1

FCH_CRT_G 28

FCH_CRT_HSYNC
FCH_CRT_VSYNC

@ C179
2
1
2
10_0402_5%
10P_0402_50V8J
2

R646
C620
FCH_SPI_MOSI_R1
2
2
1
33_0402_5% @
@
22P_0402_50V8J

FCH_CRT_B 28
28
28

FCH_CRT_DDC_SDA 28
FCH_CRT_DDC_SCL 28
R158 1

2 715_0402_1%

ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
2
100_0402_1%

+VDDAN_11_ML

ML_VGA_TXP0
ML_VGA_TXN0
ML_VGA_TXP1
ML_VGA_TXN1
ML_VGA_TXP2
ML_VGA_TXN2
ML_VGA_TXP3
ML_VGA_TXN3

FCH_CRT_HPD

8
8
8
8
8
8
8
8

+FCH_VDDAN_33_DAC_R
FCH_CRT_HPD

FCH_CRT_HPD 10

2
10K_0402_5%

1
R161
@

2

3

10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
GL-02/10/2011: Please enabled integrated pull-up/pull-down and left unconnected.

10K_0402_5%
2
@

10K_0402_5%
2
10K_0402_5%

AG16
AH10
A28
G27
L4
0.1U_0402_16V4Z
2

SYS BIOS ROM 4MB

HUDSON-M3_FCBGA656

2
10K_0402_5%

Change to PD 20101112

1
R162
1
R163
1
R164
1
R165
1
R166
1
R168
1
R170
1
R171

M3

1
R146

25mA

+3V_SPI

C180
1

+3V_SPI
2 33_0402_5%FCH_SPI_CS1#
2 47_0402_5%FCH_SPI_CLK

R617
10K_0402_5%
@

U6
@

1
R174 1
R175 1
R176

2 75_0402_5%FCH_SPI_MOSI
FCH_SPI_MISO

2
2 1K_0402_5%
2 10K_0402_5%
10K_0402_5%

FCH_SPI_CS1#
FCH_SPI_WP#
FCH_SPI_HOLD#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

FCH_SPI_CLK
FCH_SPI_MOSI
FCH_SPI_MISO

4

W25Q32BVSSIG_SO8
SA00003K800

3
7
10
20

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PI3V512QE_QSOP24

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1

C625

FCH_SDCLK 32
FCH_SDCMD 32
FCH_SDCD# 32
FCH_SDWP 32
FCH_SDDATA0 32
FCH_SDDATA1 32
FCH_SDDATA2 32
FCH_SDDATA3 32

2

VDD
VDD
VDD
VDD

FCH_SDCLK
FCH_SDCMD
FCH_SDCD#
FCH_SDWP
FCH_SDDATA0
FCH_SDDATA1
FCH_SDDATA2
FCH_SDDATA3

GBE_RXERR

U28 AUXCAL 1
R160
T31
T33
T29
T28
R32
R30
P29
P28

P1

U5
1
4
9
19

K31

VIN4/SLOAD_1/GPIO179
TEMPIN0/GPIO171

+3V_FCH

0.8mA

@

V28
V29

VIN3/SDATO_1/GPIO178

VIN5/SCLK_1/GPIO180
10K_0402_5%

1
C624

M33
N32

N4

R167
1
@

V6
V5
V3
T6
V1
L30

SATA_ACT#/GPIO67

2 10K_0402_5%
AF21

60.4_0402_1%
60.4_0402_1%
0_0402_5%
0_0402_5%
60.4_0402_1%
60.4_0402_1%
60.4_0402_1%
60.4_0402_1%

GBE_MDIO

R551 1
0_0402_5%

VGA_RED

VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71

VGA MAINLINK

R159 1

+3VS

AD22

GBE_COL
GBE_CRS

nonCARD@
2
nonCARD@
2
nonCARD@
2
nonCARD@
2
nonCARD@
2
nonCARD@
2
nonCARD@
2
nonCARD@
2

GBE_RXERR
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161

VGA_DAC_RSET
38

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9

1
1
1
1
1
1
1
1

1

+AVDD_SATA

SATA_RX1N
SATA_RX1P

FCH_SDCLK_R R752
FCH_SDCMD_R R753
FCH_SDCD#_R R754
FCH_SDWP_R
R755
FCH_SDDATA0_R R756
FCH_SDDATA1_R R757
FCH_SDDATA2_R R758
FCH_SDDATA3_R R759

5P_0402_50V_C

AN22
AL22

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

5P_0402_50V_C

34 SATA_FTX_DRX_P1
34 SATA_FTX_DRX_N1

SD CARD

SATA_RX0N
SATA_RX0P

GBE LAN

ODD

AL20
AN20

SPI ROM

1

34 SATA_FRX_DTX_N0
34 SATA_FRX_DTX_P0

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

VGA DAC

HDD2

SATA_TX0P
SATA_TX0N

SERIAL ATA

HDD1

34 SATA_FTX_DRX_P0
34 SATA_FTX_DRX_N0

AK19
AM19

B

C

D

Title

Hudson-M2/M3-SATA/GBE/HWM
Size Document Number
Custom

Rev
0.11

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

15

of

53

A

B

C

D

E

STRAP PINS
1

PULL
HIGH

PCI_CLK1

PCI_CLK3

PCI_CLK4

LPC_CLK0

LPC_CLK1

EC_PWM2

ALLOW
PCIE GEN2

USE
DEBUG
STRAPS

NON_FUSION
CLOCK MODE

EC
ENABLED

CLKGEN
ENABLED

LPC ROM
DEFAULT

DEFAULT

PULL
LOW

DEFAULT

FORCE
PCIE GEN1

IGNORE
DEBUG
STRAP

FUSION
CLOCK
MODE

EC
DISABLED

DEFAULT

DEFAULT

DEFAULT

RTC_CLK
S5 PLUS
MODE
DISABLED

1

If support ML DAC power down when no VGA plug

DEFAULT

SPI ROM

CLKGEN
DISABLE

L2
1
2
FBMA-L11-201209-221LMA30T_0805

S5 PLUS
MODE
ENABLED

30mil

220 ohm
+3VS

+FCH_VDDAN_33_DAC

+FCH_VDDAN_33_DAC_R

220 ohm

1
2

1
2

1
2

1
2

1
2

1
2

1

R183 10K_0402_5%

@

+3V_FCH

R182 10K_0402_5%

2

+3V_FCH

R181 10K_0402_5%

@

+3V_FCH

R180 10K_0402_5%

@

+3V_FCH

R179 10K_0402_5%

10K_0402_5%

@

+3VS
R178 10K_0402_5%

R177

13 PCI_CLK1
2

+3VS

2

1

+3VS

VGA_PD#

2

AO3413 Vgs(max)=1V

R184 1

C182

C181

1
2
FBMA-L11-201209-221LMA30T_0805

1

2

0.1U_0402_16V4Z

1

2.2U_0603_6.3V4Z

@ L3
@ Q12 3
@Q12
AP2301GN-HF_SOT23-3

2 0_0402_5%

+1.1VS

+FCH_VDDAN_11_MLDAC

@ Q13 3
AP2301GN-HF_SOT23-3

@
1
R185

1

2
0_0402_5%

30mil

13 PCI_CLK3

2

2

13 PCI_CLK4
13,37 LPC_CLK0_EC

VGA_PD#
+3VS

13 LPC_CLK1

PCI_AD24

DEFAULT

DEFAULT

BYPASS
PCI PLL

ENABLE
ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

1
2

@

R202 2.2K_0402_5%

@

R201 2.2K_0402_5%

@

R200 2.2K_0402_5%

@

R199 2.2K_0402_5%

@

R198 2.2K_0402_5%

4

1

DEFAULT

2

PCI_AD23

DEFAULT

1

PCI_AD24

13

DEFAULT

2

PCI_AD25

13

DISABLE PCI
MEM BOOT

1

PCI_AD26

13

USE DEFAULT
PCIE STRAPS

2

PCI_AD27

13

USE FC
PLL

1

13

DISABLE
ILA
AUTORUN

6
1
@

3

@

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

2

@

Issued Date

A

2

1
2

PCI_AD23

USE PCI
PLL

2

PULL
LOW

4

2

2
1U_0402_6.3V4Z

1

PCI_AD25

@

PULL
HIGH

3

2
1

2
1

1
2

1
2

1
2

1
2

1

1
2

1
2

2

PCI_AD26

1

Q14A
DMN66D0LDW-7_SOT363-6

1

R197
C184
2.2K_0402_5%

@

C183
1U_0402_6.3V4Z

5

VGA_PD

3

PCI_AD27

2
Q14B
DMN66D0LDW-7_SOT363-6

14

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

VGA_PD#

@

@

Check VGA_PD states

DEBUG STRAPS

R187
100K_0402_5%

@

R196
0_0402_5%

@

R195
1K_0402_5%

VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off

R186
100K_0402_5%

@

R194 2.2K_0402_5%

R193 2.2K_0402_5%

@

R192 10K_0402_5%

R191 10K_0402_5%

R190 10K_0402_5%

R189 10K_0402_5%

R188 10K_0402_5%

@

1

14 EC_PWM2
13,37 RTC_CLK

C

D

Title

Hudson-M2/M3-STRAP
Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

16

of

53

B

C

D

E

+VCC_FCH_R
U2C

PCI/GPIO I/O

CORE S0
CLKGEN I/O

2

+1.1VS
R209

1

2

2

1

2

C219

MAIN LINK

C209

2

1

C218

SERIAL ATA

0_0603_5%

2

1
0_0805_5%

1

2

R212
2

22U_0805_6.3V6M

PCI EXPRESS

1

1

1337mA+AVDD_SATA

1
0_0805_5%

+3V_FCH

2

1

2

C225

2

1

1

2

2.2U_0603_6.3V4Z

1

R213
1

59mA

+VDDIO_33_S
C224

N18
L19
M18
V12
V13
Y12
Y13
W11

1U_0402_6.3V6K

GBE LAN

HUDSON-2
A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18

+1.1VS

22U_0805_6.3V6M

2

.1U_0402_16V7K

2

1

C217

3.3V_S5 I/O

10U_0603_6.3V6M

C360

U2E

R208
C199

C208

2

1

.1U_0402_16V7K

1

C223

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

0_0805_5%

+1.1VS

1U_0402_6.3V6K

VDDIO_GBE_S_1
VDDIO_GBE_S_2

2

1088mA
.1U_0402_16V7K

C207

2

1

+AVDD_SATA

10mils

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

1

2

22U_0805_6.3V6M

2

.1U_0402_16V7K

2

1

C216

VDDIO_33_GBE_S

2

C187
10U_0603_6.3V6M

C193

C198

1

.1U_0402_16V7K

C197

2

.1U_0402_16V7K

1

60mils

VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4

10U_0603_6.3V6M

C186

.1U_0402_16V7K

C192

.1U_0402_16V7K

1

1U_0402_6.3V6K

2

0_0402_5%

+3V_FCH

10mils

G24

5mA

+VDDXL_3.3V

2

1

2

L11
1
2
MBK1608221YZF_2P

220ohm / 550mA

USB

+1.1VALW

10mils

R215

187mA

+VDDCR_1.1V

2

C238

1

1

2

2

1U_0402_6.3V6K

C237

VDDCR_11_S_1
VDDCR_11_S_2

N20
M20

1U_0402_6.3V6K

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

C234

C233

1

2.2U_0603_6.3V4Z

VDDXL_33_S

.1U_0402_16V7K

2

2

C206

1

VDDPL_11_DAC

10mils

U12
U13

1

1U_0402_6.3V6K

2

.1U_0402_16V7K

C364

C236

2

.1U_0402_16V7K

2

1

LDO_CAP

C222

C230

2

1

.1U_0402_16V7K

C229

2

1

10U_0603_6.3V6M

1

+VDDAN_11_USB_S

1

VDDPL_33_SATA

30mils

G7
H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11

2

1

1

+PCIE_VDDR_FCH

1U_0402_6.3V6K

AA9
AA10

C196

AB10

1

340mA

+PCIE_VDDR_FCH

C215

Y22
V23
V24
V25

2

1U_0402_6.3V6K

2

.1U_0402_16V7K

1

10U_0603_6.3V6M

2

C228

C227

C235

C240

2

1

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

2

50mils

VDDPL_33_PCIE

20mils

2
0_0402_5%

140mA

220ohm / 550mA
.1U_0402_16V7K

C239

2.2U_0603_6.3V4Z

2

1

2

2.2U_0603_6.3V4Z

+3VS

1

1

1U_0402_6.3V6K

2

1
2
MBK1608221YZF_2P

220ohm / 550mA

V21

+1.1VALW
L12

L13
+VDDPL_33_SATA
1
2
MBK1608221YZF_2P

2

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

VDDPL_33_USB_S

+VDDAN_11_ML

+VDDAN_33_USB
1U_0402_6.3V6K

2

1

C226
22U_0805_6.3V6M

C363

C232

2

.1U_0402_16V7K

2

1

658mA

C362
2.2U_0603_6.3V4Z

1

1

C213
4.7U_0603_6.3V6K

C212

C221

C231

1

2.2U_0603_6.3V4Z

220ohm / 550mA

3

1

M31

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

2

1

VDDPL_33_SSUSB_S

10mils

+VDDPL_11_DAC

C214
.1U_0402_16V7K

1

+3V_FCH

L10
+VDDPL_33_PCIE
1
2
MBK1608221YZF_2P

2
2.2U_0603_6.3V4Z

1
R214

220ohm / 3A

VDDAN_33_DAC

1

1U_0402_6.3V6K

1
C204
2
0_0402_5%

AB11
AA11

L9
1
2
FBMA-L11-201209-221LMA30T_0805

+3VS

VDDPL_33_ML

C205

AG28

VDDPL_33_DAC

2

1

+1.1VS_CKVDD

1U_0402_6.3V6K

10mils

H26
J25
K24
L22
M22
N21
N22
P22

1

2

+1.1VS_CKVDD

20mils

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

VDDPL_33_SYS

@

R211
0_0603_5%

.1U_0402_16V7K

2

D7

AH29

2

C191

10mils

93mA

1

1U_0402_6.3V6K

43mA

+VDDPL_33_PCIE

T14
T17
T20
U16
U18
V14
V17
V20
Y17

C203

10mils

50mils

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

1U_0402_6.3V6K

C211

C220

2.2U_0603_6.3V4Z

2

1

T22

17mA

+FCH_VDDPL_33_USB_S

.1U_0402_16V7K

C210

2.2U_0603_6.3V4Z

1

U22

10mils
10mils

+FCH_VDDPL_33_USB_S

Change to 0ohm-AMD request
20110212

V22

10mils

+FCH_VDDPL_33_SSUSB_S L18

2

L8
2
0_0603_5%

10mils

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10

C185

20mA

+VDDAN_33_USB
1

C361

VDDPL_33_SSUSB_S
For Hudson3 USB3.0 only
For Hudson2, connect to GND

+FCH_VDDAN_11_MLDAC
L6
L7
1
2 +FCH_VDDPL_33_SSUSB_S
7mA
MBK1608221YZF_2P
1
2 +VDDPL_11_DAC_L 1
MBK1608221YZF_2P
R210
220ohm / 550mA
220ohm / 550mA
226mA
1
1
2
2

.1U_0402_16V7K

2 +VDDPL_33_DAC
0_0402_5%
+VDDPL_33_ML
1
2
0_0402_5%
200mA R206
+FCH_VDDAN_33_DAC_R
1

20mA R204

LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA
supply for the RGB outputs

2

2

10mils

+3V_FCH

2

.1U_0402_16V7K

2

C202

2

C201

220 ohm

1

.1U_0402_16V7K

1

C200

C190

0_0603_5%

2

1

20mA

+FCH_VDDPL_33_MLDAC

@ L5 1
2
MBK1608221YZF_2P

2

1

HUDSON-2

AB17
AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16
H24

1+FCH_VDDPL_33_MLDAC
2.2U_0603_6.3V4Z

+3VS

2

1

47mA
+VDDPL_3.3V

+FCH_VDDAN_33_DAC_R
R205 2

1

.1U_0402_16V7K

2

2

.1U_0402_16V7K

1

.1U_0402_16V7K

2

C189

C195

1

2.2U_0603_6.3V4Z

220ohm / 550mA

1

1

C188

+VDDPL_3.3V

1
2
MBK1608221YZF_2P

+VDDIO_33_PCIGP
C194

L4

22U_0805_6.3V6M

R203
2
1
0_0603_5%

+3VS

+3VS

+1.1VS
R207

1007mA

10mils

1U_0402_6.3V6K

131mA

1
0_0603_5%

N8
K25
H25

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GROUND

A

VSSAN_HWM
VSSXL

VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC

VSSPL_SYS
EFUSE

+1.1VALW
L38

197mA

10mils

VDDPL_11_SYS_S

J24

2

3

T21
L28
K33
N28
R6

L39

70mA

+VDDPL_1.1V

2

C245

1

1

2

.1U_0402_16V7K

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

C244

2

T12
T13

2.2U_0603_6.3V4Z

1

.1U_0402_16V7K

2

C243

C242

2

1

.1U_0402_16V7K

C241

1

10U_0603_6.3V6M

1
2
MBK1608221YZF_2P

220ohm / 550mA

1

+1.1VALW

10mils

+VDDCR_1.1V_USB

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

HUDSON-M3_FCBGA656

1
2
MBK1608221YZF_2P

Connected to VSS through a dedicated via.

220ohm / 550mA

+3V_FCH
+FCH_VDD_11_SSUSB_S

20mils

+VDDCR_11_SSUSB

2

C256

1

1

2

.1U_0402_16V7K

2

C255

USB SS

+FCH_VDD_11_SSUSB_S

B

1

.1U_0402_16V7K

2

C254

1

1U_0402_6.3V6K

C253

2
0_0603_5%

1
C250

2

VDDCR_11_SSUSB_S_1
VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3
VDDCR_11_SSUSB_S_4

12mA R217

+VDDAN_33_HWM

1

30mils

N16
N17
P17
M17

M8

1

2

.1U_0402_16V7K

VDDAN_33_HWM_S

C249

2

.1U_0402_16V7K

C248

.1U_0402_16V7K

1

10mils

VDDAN_11_SSUSB_S_1
VDDAN_11_SSUSB_S_2
VDDAN_11_SSUSB_S_3
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S_5

2

AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

0_0402_5%

+3VS

10mils

VDDIO_AZ_S

AA4

1
C251
1
C252

HUDSON-M3_FCBGA656

R218
1

2011/07/29

4

VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported

0_0402_5%
2
2.2U_0603_6.3V4Z
2
.1U_0402_16V7K

Compal Electronics, Inc.
2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

2

Compal Secret Data

Security Classification
Issued Date

26mA

+VDDIO_AZ

POWER

424mA

220ohm / 3A

A

1

2

10U_0603_6.3V6M

2 L40
1
1
R219
FBMA-L11-201209-221LMA30T_0805

2

C247

+1.1VALW

C246

4

1

1U_0402_6.3V6K

40mils

P16
M14
N14
P13
P14

+VDDAN_SSUSB

2
0_0603_5%

2.2U_0603_6.3V4Z

282mA
1
R216

D

Title

Hudson-M2/M3-POWER/GND
Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Sheet

Wednesday, October 19, 2011
E

17

of

53

5

4

PCIE_CTX_GRX_P[15..0]

6 PCIE_CTX_GRX_P[15..0]

3

PCIE_CRX_GTX_P[15..0]

U7A

PCIE_CTX_GRX_N[15..0]

6 PCIE_CTX_GRX_N[15..0]

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

AA38
Y37

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

Y35
W36

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

W38
V37

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

2

PCIE_CRX_GTX_P[15..0] 6

PCIE_CRX_GTX_N[15..0]

LVDS Interface

PCIE_CRX_GTX_N[15..0] 6

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_CRX_C_GTX_P0 0.1U_0402_16V7K
PCIE_CRX_C_GTX_N0 0.1U_0402_16V7K

2
2

1 C257 PX@
1 C258 PX@

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_TX1P
PCIE_TX1N

W33 PCIE_CRX_C_GTX_P1 0.1U_0402_16V7K
W32 PCIE_CRX_C_GTX_N1 0.1U_0402_16V7K

2
2

1 C264 PX@
1 C259 PX@

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33 PCIE_CRX_C_GTX_P2 0.1U_0402_16V7K
U32 PCIE_CRX_C_GTX_N2 0.1U_0402_16V7K

2
2

1 C260 PX@
1 C261 PX@

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30 PCIE_CRX_C_GTX_P3 0.1U_0402_16V7K
U29 PCIE_CRX_C_GTX_N3 0.1U_0402_16V7K

2
2

1 C262 PX@
1 C263 PX@

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33
T32

PCIE_CRX_C_GTX_P4 0.1U_0402_16V7K
PCIE_CRX_C_GTX_N4 0.1U_0402_16V7K

2
2

1 C265 PX@
1 C266 PX@

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30
T29

PCIE_CRX_C_GTX_P5 0.1U_0402_16V7K
PCIE_CRX_C_GTX_N5 0.1U_0402_16V7K

2
2

1 C267 PX@
1 C268 PX@

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

P33
P32

PCIE_CRX_C_GTX_P6 0.1U_0402_16V7K
PCIE_CRX_C_GTX_N6 0.1U_0402_16V7K

2
2

1 C269 PX@
1 C270 PX@

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

P35
N36

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

P30
P29

PCIE_CRX_C_GTX_P7 0.1U_0402_16V7K
PCIE_CRX_C_GTX_N7 0.1U_0402_16V7K

2
2

1 C271 PX@
1 C272 PX@

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8

N38
M37

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

N33 PCIE_CRX_C_GTX_P8 0.1U_0402_16V7K
N32 PCIE_CRX_C_GTX_N8 0.1U_0402_16V7K

2
2

1 C273 PX@
1 C274 PX@

PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8

N30 PCIE_CRX_C_GTX_P9 0.1U_0402_16V7K
N29 PCIE_CRX_C_GTX_N9 0.1U_0402_16V7K

2
2

1 C275 PX@
1 C276 PX@

PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9

PCIE_RX0P
PCIE_RX0N

1

U7G

D

PCIE_RX1P
PCIE_RX1N

PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9

M35
L36

PCIE_RX9P
PCIE_RX9N

PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10

L38
K37

PCIE_RX10P
PCIE_RX10N

PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11

K35
J36

PCIE_RX11P
PCIE_RX11N

PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12

J38
H37

PCIE_RX12P
PCIE_RX12N

PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13

H35
G36

PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCI EXPRESS INTERFACE

C

LVDS CONTROL

VARY_BL
DIGON

AK27
AJ27

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK35
AL36

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36
C

PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N

L33
L32

PCIE_CRX_C_GTX_P100.1U_0402_16V7K
PCIE_CRX_C_GTX_N100.1U_0402_16V7K

2
2

1 C277 PX@
1 C278 PX@

PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10

PCIE_TX11P
PCIE_TX11N

L30
L29

PCIE_CRX_C_GTX_P110.1U_0402_16V7K
PCIE_CRX_C_GTX_N110.1U_0402_16V7K

2
2

1 C279 PX@
1 C280 PX@

PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11

PCIE_TX12P
PCIE_TX12N

K33
K32

PCIE_CRX_C_GTX_P120.1U_0402_16V7K
PCIE_CRX_C_GTX_N120.1U_0402_16V7K

2
2

1 C281 PX@
1 C282 PX@

PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

J33
J32

PCIE_CRX_C_GTX_P130.1U_0402_16V7K
PCIE_CRX_C_GTX_N130.1U_0402_16V7K

2
2

1 C283 PX@
1 C284 PX@

PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

PCIE_CRX_C_GTX_P140.1U_0402_16V7K
PCIE_CRX_C_GTX_N140.1U_0402_16V7K

2
2

1 C285 PX@
1 C286 PX@

PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33 PCIE_CRX_C_GTX_P150.1U_0402_16V7K
H32 PCIE_CRX_C_GTX_N150.1U_0402_16V7K

2
2

1 C287 PX@
1 C288 PX@

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

B

D

LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

TXOUT_L3P
TXOUT_L3N

AN36
AP37

THAMES XT M2 FCBGA 962P
B

PX@

2

2

+3VSG +3VS

CLOCK
AB35
AA36

13,14 PE_GPIO0

PCIE_REFCLKP
PCIE_REFCLKN

R556 2

PX@ 1 0_0402_5%

13,30,33 PLT_RST#

R223 2 PX@
1
10K_0402_5%
GPU_RST#

AH16

PWRGOOD
PERSTB

5

Y30 1.27K_0402_1% 1 PX@

2 R222

PCIE_CALRN

Y29

2K_0402_1% 1 PX@

2 R224

Issued Date

THAMES XT M2 FCBGA 962P

4

A

Y

GPU_RST#

4

PX@
MC74VHC1G08DFT2G SC70 5P
A

Compal Electronics, Inc.

Compal Secret Data
2011/07/29

Deciphered Date

2012/07/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PX@

1

U8

+1.0VSG

Security Classification

1

AA30
PX@
R225
100K_0402_5%
2

A

PCIE_CALRP

B

3

CALIBRATION

2

G

CLK_PEG_VGA
CLK_PEG_VGA#

13 CLK_PEG_VGA
13 CLK_PEG_VGA#

P

5

1

R536
0_0402_5%

1

R562
0_0402_5%
@

3

2

ATI_Thames XT_M2_PCIE/LVDS
Size
B
Date:

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet
1

18

of

53

5

4

3

2

1

CONFIGURATION STRAPS

U7B

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX
DPA

TX1P_DPA1P
TX1M_DPA1N

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC

TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N

DPD

TX4P_DPD1P
TX4M_DPD1N

I2C

R
RB

GENERAL PURPOSE I/O

10K_0402_5%

2

R229 GPU_GPIO5

1

@

10K_0402_5%
10K_0402_5%

1
1

@
@

2
2

R230 GPU_GPIO8
R231 GPU_GPIO9

10K_0402_5%
10K_0402_5%
10K_0402_5%

1
1
1

PX@ 2
@
2
@
2

R232 GPU_GPIO11
R234 GPU_GPIO12
R235 GPU_GPIO13

37,41

RB751V_SOD323
D2 @ 1

ACIN

49

49

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
GPU_GPIO5

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
GPU_GPIO8
AJ13
GPU_GPIO9
AH15
AJ16
GPU_GPIO11
AK16
GPU_GPIO12
AL16
GPU_GPIO13
AM16
AM14
GPU_VID0
AM13
AK14
THM_ALERT#
AG30
AN14
GPU_CTF
AM17
GPU_VID1
AL13
GPIO21_BBEN AJ14
AK13
PEG_CLKREQ#
AN13
GPIO24_TRSTB AM23
GPIO25_TDI
AN23
GPIO26_TCK
AK23
GPIO27_TMS
AL24
GPIO28_TDO
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

2

GPU_VID0

GPU_VID1

+3VSG

T19
10K_0402_5%
10K_0402_5%
10K_0402_5%

1
1
1

@
@
@

2 R237
2 R238
2 R239

GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS

10K_0402_5%

1

@

2 R242

GPIO26_TCK

T20
GPU_CTF

GPU_CTF
2

37

14 PEG_CLKREQ#

R236
10K_0402_5%

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

1

B

+1.8VSG

AK24

75mA
1

2

1

2

PX@
2 R244
PX@
2 R246

2

+VREFG_GPU

1 499_0402_1%

125mA

AH13

+DPLL_PVDD AM32
AN32

G2/NC
G2B/NC
B2/NC
B2B/NC
C/NC
Y/NC
COMP/NC

XTALIN
XTALOUT

AV33
AU34
AW34

XTALIN
Voltage Swing: 1.8 V

AW35

XTALIN

PX@

200_0402_5%

GPU_THERM_D+
GPU_THERM_D-

A2VDDQ/NC
VREFG

AF29
AG29
AK32

PX@
C305
22P_0402_50V8J

27MHZ_16PF_X3G027000FG1H-HX

1

3
GND

GND

2

4

AL31
PX@
L45

3
+1.8VSG
C306 PX@
22P_0402_50V8J

1
2
BLM15BD121SN1D_0402

(1.8V@20mA TSVDD)
+TSVDD
1

2

1

2

AJ32
AJ33

PX@
C304
0.1U_0402_16V4Z

1

PX@

PX@
C303
1U_0402_6.3V6K

Y2

GPIO_22_ROMCSB

ENABLE EXTERNAL BIOS ROM

AT15
AR14

ROMIDCFG(2:0)

GPIO[13:11]

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

XXX

V2SYNC

IGNORE VIP DEVICE STRAPS

0

AU16
AV15

VIP_DEVICE_STRAP_ENA

R2SET/NC

1

AT17
AR16

RSVD

H2SYNC

AU20
AT19

RSVD

GENERICC

AT21
AR20

AUD[1]

HSYNC

AU22
AV21

AUD[0]

VSYNC

AT23
AR22

AMD RESERVED CONFIGURATION STRAPS

GPIO21

AE36
AD35

0
0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort only
1 0 Audio for DisplayPort and HDMI, if dongle is detected.
1 1 Audio for both DisplayPort and HDMI

H2SYNC

GENERICC

GPIO2

AB34

R233 1 PX@

AD34
AE34

+AVDD

AC33
AC34

+VDD1DI

2 499_0402_1%

(1.8V@65mA AVDD)
(1.8V@100mA VDD1DI) 1

2

1

2

2
+1.8VSG
L42 PX@
BLM15BD121SN1D_0402

1

1

1

2

1

2

Transmitter Power Saving Enable
GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable
GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

2
L41 PX@
BLM15BD121SN1D_0402

1

2

2

Internal VGA Thermal Sensor

+3VSG

AF30
AF31
AC32
AD32
AF32
AD29
AC29

PX@
R240
10K_0402_5%

+3VS
PX@
R241
10K_0402_5%

GENLK_CLK
GENLK_VSYNC

PX@ 1 0_0402_5%

SM_CK2

PX@ 1 0_0402_5%

Q15A PX@
DMN66D0LDW-7_SOT363-6
SM_DA2
4

T21
T22

1

6

AG31
AG32

8,27,37

EC_SMB_DA2

8,27,37

B

3

Q15B PX@
DMN66D0LDW-7_SOT363-6

AD33
@

1 R243

2 0_0402_5%

AF33
1 R245

2 0_0402_5%

AA29

PLL/CLOCK
DPLL_VDDC

DDC1CLK
DDC1DATA
AUX1P
AUX1N

XTALIN
XTALOUT

DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N

XO_IN2

DPLUS
DMINUS

THERMAL

DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
TS_A/NC
TSVDD
TSVSS

DDC6CLK
DDC6DATA
DDCCLK_AUX7P
DDCDATA_AUX7N

AM26
AN26

GPU_GPIO4

R553 1 PX@

2 0_0402_5%

SM_CK2

AM27
AL27

GPU_GPIO3

R558 1 PX@

2 0_0402_5%

SM_DA2

AM19
AL19
AN20
AM20

External VGA Thermal Sensor

+3VSG

U34

AL30
AM30

1
1

AL29
AM29

PX@
2

AN21
AM21
AJ30
AJ31

GPU_THERM_D+
2200P_0402_50V7K
1
2
C356
PX@
GPU_THERM_D-

2
3
4

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

8

VGA_SMB_CK2

7

VGA_SMB_DA2

6

THM_ALERT#

5

1
R554 PX@

2
4.7K_0402_5%

A

+3VSG

ADM1032ARMZ-2REEL_MSOP8
PX@

AK30
AK29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PX@

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

EC_SMB_CK2

AG33

Title

ATI_Thames XT_M2_Main_MSIC
Size
C
Date:

5

C

TX_PWRS_ENB
AC36
AC38

AD30
AD31

11

GPIO8

AF37
AE38

AC30
AC31

X

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

AD39
AD37

THAMES XT M2 FCBGA 962P

2

0
0: disable
1: enable

DPLL_PVDD
DPLL_PVSS

1M_0402_5%

PX@
C302
10U_0603_6.3V6M

A

BIOS_ROM_EN

VGA_SMB_CK2 R564 2

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

A2VDD/NC

2

R247

PX@

AU14
AV13

C357
0.1U_0402_16V4Z

XTALOUT

RESERVED

DAC2

DDCCLK_AUX3P
DDCDATA_AUX3N
R561

GPIO21

1

R2/NC
R2B/NC

DDC/AUX

1

2

0

RSVD

AT33
AU32

@

0.1U_0402_16V7K
PX@
C301

1U_0402_6.3V6K
PX@
C300

10U_0603_6.3V6M
PX@
C299

AVDD
AVSSQ
VDD1DI
VSS1DI

A2VSSQ/TSVSSQ

+DPLL_VDDC AN31

2

0

VGA ENABLED

VGA_SMB_DA2 R565 2

+DPLL_VDDC

1

RESERVED

GPIO9

+1.8VSG
RSET

HPD1

1 249_0402_1%

2
1
C295 0.1U_0402_16V7K
PX@

1

HSYNC
VSYNC

0.60 V level, Please
VREFG Divider ans
cap close to ASIC

+1.8VSG

+1.0VSG
L44 PX@
2
1
BLM15BD121SN1D_0402

B
BB

DAC1

VDD2DI/NC
VSS2DI/NC

0.1U_0402_16V7K
PX@
C298

1

G
GB

+DPLL_PVDD

1U_0402_6.3V6K
PX@
C297

10U_0603_6.3V6M
PX@
C296

L43 PX@
2
1
BLM15BD121SN1D_0402

GPIO8

D

2

R226 GPU_GPIO0
R227 GPU_GPIO1
R228 GPU_GPIO2

RSVD
BIF_VGA DIS

AR32
AT31

1

2
2
2

0

AV31
AU30

1

1 PX@
1 PX@
@
1

0: 2.5GT/s
1: 5GT/s

SCL
SDA

C

10K_0402_5%
10K_0402_5%
10K_0402_5%

Advertises PCIE speed
when compliance test

RSVD

2

+3VSG

TX5P_DPD0P
TX5M_DPD0N

X

GPIO2

AR30
AT29

10U_0603_6.3V6M
PX@
C291

AK26
AJ26

STRAPS

0: disable
1: enable

GPIO1

2

SWAPLOCKA
SWAPLOCKB

DPB

X

PCIE TRANSMITTER DE-EMPHASIS

GPIO0

TX_DEEMPH_EN

1U_0402_6.3V6K
PX@
C290

AJ21
AK21

TX3P_DPB2P
TX3M_DPB2N

PCIE FULL TX OUTPUT SWING

TX_PWRS_ENB

AT27
AR26

0.1U_0402_16V7K
PX@
C289

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

TXCBP_DPB3P
TXCBM_DPB3N

RECOMMENDED
SETTINGS

DESCRIPTION OF DEFAULT SETTINGS
0: 50% swing
1: Full swing

10U_0603_6.3V6M
PX@
C294

23
23
23
23

TX2P_DPA0P
TX2M_DPA0N

PIN

STRAPS

AU26
AV25

1U_0402_6.3V6K
PX@
C293

D

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AT25
AR24

0.1U_0402_16V7K
PX@
C292

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AU24
AV23

5

TXCAP_DPA3P
TXCAM_DPA3N

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

19

of

53

5

4

3

Power Sequence of Whistler and Seymour
SUSP#
+3VSG
(JUMP form +3VS)
D

10ms

VGA_ON
VGA_PWR_ON
1.5_VDDC_PWREN
+VGA_CORE
+1.5VSG

2

VGA Muxless with BACO Status Mapping table
Normal mode
BACO mode
PX_EN
0
1
1.5_VDDC_PWREN
1
0
VDDC_EN
1
0
1.0_EN
0
1
+3.3VSG
ON
ON
+1.8VSG
ON
ON
+1.0VSG
ON
ON
+VGA_CORE
ON
OFF
+1.5VSG
ON
OFF
+BIF_VDDC
+VGA_CORE
+1.0VSG

1

VGA Power Enable Signal Mapping table
Whislter
VGA_PWR_ON source signal
VGA_ON
SUSP#
+3.3VSG
+1.8VSG
VGA_PWR_ON
+1.0VSG
VGA_PWR_ON
+VDDCI
Combine with +VGA_CORE
+VGA_CORE
1.5_VDDC_PWREN
+1.5VSG
1.5_VDDC_PWREN

D

+1.0VSG
+1.8VSG

20ms

For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON
@
R248 1
+3VS

PE_GPIO1
VGA_PWR_ON

>2ms

PX@
U9

R249 1

+3VS

2
2 10K_0402_5%

B

Y

1

A

1.5_VDD_PWREN

1.5_VDD_PWREN

26,49

NC7SZ08P5X_NL_SC70-5

1

3

PX@

C

4

G

VGA_PWR_ON

P

5

C

2 0_0402_5%

C307 PX@
0.1U_0402_16V4Z
1
2

D
1 PX@
R250

PX_EN
1

21,37

2
2
0_0402_5%
G
S

VGA_PWR_ON

26,43,49

2

2

VGA_PWR_ON

PX@
R253
1K_0402_5%

2
10K_0402_1%

PX@
R254
1K_0402_5%

1.0_EN

5
B

P

2
2
0_0402_5%
1

A

G

1 PX@
R256

Y

4

5

NC7SZ08P5X_NL_SC70-5

3

From +VGA_CORE regulator
B

2

+BIF_VDDC
Q18

PX@

D

S

20mil

3

1

AO3416_SOT23-3

1

30mil

3

AO3416_SOT23-3

+VGA_CORE
@
1
R257

2
0_0805_5%

1
2
G

G

2

B

Q19
S

PX@

D

+1.0VSG

Q17A
PX@
DMN66D0LDW-7_SOT363-6

PX@
U10

Q17B
PX@
DMN66D0LDW-7_SOT363-6

1.5_VDD_PWREN

VDDC_EN

+3VS

PX@
C308
0.1U_0402_16V4Z
2
1

13,49 VGA_PWRGD

1

2
0_0402_5%

6

@

1

1
R255

+5VS

1

PE_GPIO1

1 PX@
R252

3

13,14,37

VGA_ON

+5VS

4

37

For VGA Power on control

2

Delay SUSP# 10ms

2N7002K_SOT23-3

3

PX@
R251
5.11K_0402_1%

Q16
PX@

PX@
C309
2 22U_0805_6.3V6M

1.0_EN

2
G
D

S

+VGA_CORE

30mil

1
PX@
Q89
AO3416_SOT23-3

1
D

3

3
PX@
Q90
AO3416_SOT23-3
S

G

2

VDDC_EN

AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_Thames XT_M2_BACO POWER
Size
C
Date:

5

4

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

20

of

53

5

4

3

2

1

U7F

+DPAB_VDD18

1.8V@300mA DPAB_VDD18)

+DPCD_VDD18
DP A/B POWER

130mA

1

2

1

2

PX@ C315
0.1U_0402_16V7K

PX@

PX@ C314
1U_0402_6.3V6K

PX@ C313
10U_0603_6.3V6M

0_0402_5%

AP20
AP21

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

AN24
AP24

+DPCD_VDD10

1

110mA
AP13
AT13

2

AN17
AP16
AP17
AW14
AW16

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2
DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

1

2

0_0402_5%
PX@

2

+DPAB_VDD10

+1.0VSG

(1.0V@220mA DPAB_VDD10)

AN27
AP27
AP28
AW24
AW26

1

2

1 R260

1

2

2

0_0402_5%
1

PX@

2

+DPAB_VDD18

GND

+DPCD_VDD10

1 R261

AP22
AP23

+DPCD_VDD10

2

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AP25 130mA
AP26

PX@

1

2

1

2

PX@ C321
0.1U_0402_16V7K

PX@ C319
10U_0603_6.3V6M

0_0402_5%

PX@ C320
1U_0402_6.3V6K

+DPCD_VDD10
C

2

+DPAB_VDD10

AP31
AP32

+DPCD_VDD18

+1.0VSG

1

10U_0603_6.3V6M
PX@ C318

+DPCD_VDD18

2

PX@ C316
0.1U_0402_16V7K

1 R259

2

1U_0402_6.3V6K
PX@ C317

DP C/D POWER

PX@ C312
10U_0603_6.3V6M

U7H
+1.8VSG

+1.8VSG

1 R258
PX@ C311
1U_0402_6.3V6K

PX@ C310
0.1U_0402_16V7K

+DPAB_VDD18
1

+DPAB_VDD10
AP14
AP15

1

AN33 110mA
AP33

2
AN19
AP18
AP19
AW20
AW22

150_0402_1% 2 PX@

+1.8VSG

1 R262 AW18

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

AN29
AP29
AP30
AW30
AW32

AW28 R263 1 PX@

+DPEF_VDD18

150mA
PX@ C322
10U_0603_6.3V6M

0_0402_5%
PX@

1

2

+DPEF_VDD18

1

2

PX@ C324
0.1U_0402_16V7K

2

PX@ C323
1U_0402_6.3V6K

1 R264

AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

2

+DPAB_VDD18
DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

AF34
AG34

+DPEF_VDD10

DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

20mA
PX@ C326
1U_0402_6.3V6K

PX@ C325
10U_0603_6.3V6M

2

2

PX@ C327
0.1U_0402_16V7K

+DPEF_VDD10

1

AK33
AK34

DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS
AF39
AH39
AK39
AL34
AM34

2

150_0402_1%

2

PX@ 1 R267

AM39

AV19
AR18

AM37
AN38
+DPEF_VDD18

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

1

AU18
AV17

+DPEF_VDD18

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

+DPEF_VDD10

1

AV29
AR28

+DPCD_VDD18
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

20mA
+1.0VSG

2

AU28
AV27

+DPCD_VDD18

B

PX@

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

20mA
AL33
AM33

+DPEF_VDD18

0_0402_5%

2 150_0402_1%

+DPAB_VDD18

20mA

+DPEF_VDD10

1

AN34
AP39
AR39
AU37

1 R266

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

AL38
AM35

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR
THAMES XT M2 FCBGA 962P
PX@

NC @ Thames Pro M2

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

D

C

PX_EN

20,37

1

D

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

R265
4.7K_0402_5%
PX@
2

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

B

A39 MECH#1
AW1 MECH#2
AW39MECH#3

T23 PAD
T24 PAD
T25 PAD

THAMES XT M2 FCBGA 962P
A

A

PX@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_Thames XT_M2_PWR_GND
Size
C
Date:

5

4

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

21

of

53

5

4

+1.5VSG

3

2

+1.8VSG
PX@ L46
2
1
MBK1608121YZF_0603

(1.8V@504mA PCIE_VDDR)

U7E

For DDR3/GDDR5, MVDDQ = 1.5V

+PCIE_VDDR

1

2

2

1

2

1

1

2

1

+1.8VSG

+VDDR4
1U_0402_6.3V6K
PX@
C395

1
2
BLM15BD121SN1D_0402
1

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

(M97, Broadway and Madison: 1.8V@150mA MPV18)

1

B

2

1

2

1

2

1

2

1U_0402_6.3V6K
PX@
C657

1

1U_0402_6.3V6K
PX@
C652

L50 PX@
1
2
BLM15BD121SN1D_0402

10U_0603_6.3V6M
PX@
C403

Design
1
1
1

AD12
AF11
AF12
AG11

2

L49
PX@
1
2
MCK1608471YZF 0603

0.1U_0402_16V7K
PX@
C656

CRB
1
1
1

1

AF13
AF15
AG13
AG15

+1.8VSG

1U_0402_6.3V6K
PX@
C655

SPV10
0.1u
1u
10u

+1.8VSG

10U_0603_6.3V6M
PX@
C654

Design
1
1
1

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

L48

2

CRB
1
1
1

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
I/O

AF23
AF24
AG23
AG24

2

Design
2
2
1

SPV18
0.1u
1u
10u

LEVEL
TRANSLATION
AF26
AF27
AG26
AG27

2

1

2

1

2

+MPV18

M20
M21

1

V12
U12

NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB

2
PLL

2
H7
H8

MPV18#1
MPV18#2

PX@
1
2
MCK1608471YZF 0603

(1.8V@75mA SPV18)

+SPV18 AM10

(120mA SPV10)

+SPV10

AN9

2

1

2

0.1U_0402_16V7K
PX@
C674

1

1U_0402_6.3V6K
PX@
C673

10U_0603_6.3V6M
PX@
C672

AN10

+VGA_CORE

VOLTAGE
SENESE

2
49 GCORE_SEN

GCORE_SEN
T17

AF28
AG28
AH29

1

SPVSS

1

FB_VDDC
FB_VDDCI
FB_GND

1

2

1U_0402_6.3V6K
PX@
C330

2

1

2

10U_0603_6.3V6M
PX@
C331

1

1U_0402_6.3V6K
PX@
C329

1U_0402_6.3V6K
PX@
C328

0.1U_0402_16V7K
PX@
C340

2

PCIE_VDDR
0.1u
1u
10u

1

2

CRB
2
3
1

Design
2
3
1

D

+1.0VSG

2

1

2

1

2

1

2

10U_0603_6.3V6M
PX@
C355

1

1U_0402_6.3V6K
@
C354

2

1U_0402_6.3V6K
PX@
C353

1

1U_0402_6.3V6K
PX@
C352

(1.0V@1920mA PCIE_VDDC)

1

2

PCIE_VDDC
1u
10u

CRB
7
1

VDDC
1u
10u
22u

CRB
30
10
0

Design
5 (1@)
1

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

Design
30
3
1

+VGA_CORE

C

+VGA_CORE

+BIF_VDDC

1

2

1

For non-BACO designs, connect BIF_VDDC to VDDC.
For BACO designs - see BACO reference schematics

VDDCI
1u
10u
22u

2

CRB
10
3
0

Design
10
4(3@)
1
B

(GDDR3/DDR3 1.12V@4A VDDCI)

+VDDCI

(GDDR5 1.12V@16A VDDCI)
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

2

R774
100_0402_5%
@

1

+VGA_CORE
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

SPV18
SPV10

2

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

+1.0VSG
L51

1

1U_0402_6.3V6K
PX@
C351

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

1U_0402_6.3V6K
PX@
C350

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

1U_0402_6.3V6K
PX@
C402

1

2

2

2

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

1U_0402_6.3V6K
PX@
C401

1

1

2

0.1U_0402_16V7K
PX@
C376

2

1

(1.8V@110mA VDD_CT)

+3VSG

2

0.1U_0402_16V7K
PX@
C349

0.1U_0402_16V7K
PX@
C348

0.1U_0402_16V7K
PX@
C347

2

1

+VDDC_CT

PX@ L47
1
2
BLM15BD121SN1D_0402

PX@

CRB
2
2
1

2

1

+1.8VSG

1

MPV18
0.1u
1u
10u

0.1U_0402_16V7K
PX@
C346

0.1U_0402_16V7K
PX@
C338

1U_0402_6.3V6K
PX@
C369

1U_0402_6.3V6K
PX@
C366

1U_0402_6.3V6K
PX@
C367

1U_0402_6.3V6K
PX@
C370

1U_0402_6.3V6K
PX@
C368

1U_0402_6.3V6K
PX@
C337

2

1

0.1U_0402_16V7K
PX@
C653

Design
1
1

2

1

0.1U_0402_16V7K
PX@
C658

CRB
1
1

2

1

0.1U_0402_16V7K
PX@
C396

VDDR4
0.1u
1u

2

1

0.1U_0402_16V7K
PX@
C375

Design
3
1

1

1U_0402_6.3V6K
PX@
C374

CRB
3
1

2

1

1U_0402_6.3V6K
PX@
C373

VDDR3
1u
10u

2

1

1U_0402_6.3V6K
PX@
C372

Design
1
3
1

2

1

10U_0603_6.3V6M
PX@
C371

CRB
1
3
1

2

1

1U_0402_6.3V6K
PX@
C394

Design
6
10
6

2

1

1U_0402_6.3V6K
PX@
C393

CRB
6
10
6

2

1

1U_0402_6.3V6K
PX@
C345

2

1

1U_0402_6.3V6K
PX@
C336

1

1U_0402_6.3V6K
PX@
C344

2

1U_0402_6.3V6K
PX@
C335

10U_0603_6.3V6M
PX@
C365

10U_0603_6.3V6M
PX@
C343

2

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

POWER

C

2

1

1U_0402_6.3V6K
PX@
C392

VDD_CT
0.1u
1u
10u

2

1

10U_0603_6.3V6M
PX@
C391

VDDR1
0.1u
1u
10u

2

1

10U_0603_6.3V6M
PX@
C342

2

1

10U_0603_6.3V6M
PX@
C334

2

1

10U_0603_6.3V6M
PX@
C333

+

@

10U_0603_6.3V6M
PX@
C332

220U_B2_2.5VM_R35
C339

PCIE

1

0.1U_0402_16V7K
PX@
C341

MEM I/O

D

1

GCORE_SEN
1

THAMES XT M2 FCBGA 962P
PX@

R775
100_0402_5%
@

A

2

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_Thames XT_M2_Power
Size
C
Date:

5

4

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

22

of

53

4

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA0_8
MAA1_8

VRAM_ID3

19

VRAM_ID1

19

VRAM_ID2

19

VRAM_ID3

19

QSA[7..0] 24

Vendor

VRAM_ID0 VRAM_ID1 VRAM_ID2 VRAM_ID3

H5TQ1G63DFR-11C

64MX16 (1G)
QSA#[7..0] 24

64MX16 (1G)

128M16 (2G)

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19

MAA13
1
R611
@

ODTA0
ODTA1

24
24

CLKA0
CLKA0#

24
24

CLKA1
CLKA1#

24
24

RASA0#
RASA1#

24
24

CASA0#
CASA1#

24
24

CSA0#_0

24

CSA1#_0

24

CKEA0
CKEA1

24
24

WEA0#
WEA1#

24
24

128M16 (2G)

Hynix 1GB
PN:SA000041S60
K4W1G1646G-BC11
Samsung 1GB
PN:SA00004GS30
H5TQ2G63BFR-11C
Hynix 2GB
PN:SA00003YO30
K4W2G1646C-HC11
Samsung 2GB
PN:SA000047QA0

+1.5VSG

2 MAA14
0_0402_5%

MAA13

24
MAA14

24

R269

0

1

R268

R271
0

1

R270

R269

0

1

R273
0

R273
0

R272
1

R272
1

R433
0

R433
0

R433
0

R433
0

+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12

MAB14

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

MDB[0..63]

MDB[0..63]

MAB[12..0]

WEB0B
WEB1B

@
R27
10K_0402_5%

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

MAB[12..0] 25

B_BA[2..0]

B_BA[2..0] 25

D

DQMB#[7..0] 25

QSB[7..0] 25

QSB#[7..0] 25

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8

MAB13

ODTB0
ODTB1

25
25

CLKB0
CLKB0#

25
25

CLKB1
CLKB1#

25
25

RASB0#
RASB1#

25
25

CASB0#
CASB1#

25
25

CSB0#_0

25

CSB1#_0

25

CKEB0
CKEB1

25
25

WEB0#
WEB1#

25
25

C

PX@
R278 1

TESTEN

2
5.11K_0402_1%

AD28
AK10
AL10

TESTEN
CLKTESTA
CLKTESTB

MAB0_8
MAB1_8

DRAM_RST

AH11

MAB13
MAB14
1
2
R612
@ 0_0402_5%
DRAM_RST#_R

25
MAB14

25

R64
0_0402_5%

@

THAMES XT M2 FCBGA 962P

@

1

1

0

R270

R63
0_0402_5%
THAMES XT M2 FCBGA 962P

R271

1

+1.5VSG

@
R26
10K_0402_5%
MAA14

R268

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MEMORY INTERFACE B

H27
G27

VRAM_ID2

VRAM_ID0

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

25

DDR2
GDDR5/GDDR3
DDR3

GDDR5

WEA0B
WEA1B

ODTA0
ODTA1

VRAM_ID1

PX@

Close to U7.J19

@
C675
0.1U_0402_16V7K

Close to U7.W8

B

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

J21
G19

VRAM_ID0

1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%

2
2
2
2
2
2
2
2

1

CKEA0
CKEA1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

X76@
X76@
X76@
X76@
X76@
X76@
X76@
X76@

2

MVREFDA
MVREFSA

A34
E30
E26
C20
C16
C12
J11
F8

DQMA#[7..0] 24

1
1
1
1
1
1
1
1

2

M12
M27
AH12

CSA1B_0
CSA1B_1

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

R268
R270
R269
R271
R272
R273
R434
R433

1

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

CASA0B
CASA1B
CSA0B_0
CSA0B_1

C34
D29
D25
E20
E16
E12
J10
D7

+1.8VSG

1

R277 1 PX@
R279 1 PX@
R280 1 PX@

CLKA1
CLKA1B
RASA0B
RASA1B

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

A_BA[2..0] 24

@
R281
51.1_0402_1%

PX@
@
C676
0.1U_0402_16V7K

@
R282
51.1_0402_1%
2

L27
N12
AG12

CLKA0
CLKA0B

A32
C32
D23
E22
C14
A14
E10
D9

MAA[12..0] 24

A_BA[2..0]

1

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

ADBIA0/ODTA0
ADBIA1/ODTA1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

2

R274 1 PX@
R275 1 PX@
R276 1 PX@

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

1

2

+1.5VSG

L18
L20

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

MAA[12..0]

1

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

2

U7D
DDR2
GDDR3/GDDR5
DDR3

2

C

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MDA[0..63]

GDDR5

D

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

24

DDR2
GDDR5/GDDR3
DDR3

MEMORY INTERFACE A

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

3

MDA[0..63]

2

U7C
DDR2
GDDR3/GDDR5
DDR3

B

route 50ohms single-ended/100ohms diff
and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

2

5

1

+1.5VSG

1
R286
40.2_0402_1%
PX@

DRAM_RST#_R

R287
40.2_0402_1%
PX@
2

PX@

2

1

1

1

R293
100_0402_1%

C680
0.1U_0402_16V7K
PX@

+VDD_MEM15_REFSB

R294
100_0402_1%
PX@

1

+VDD_MEM15_REFDB
PX@
R292
4.99K_0402_1%

2

1

PX@
C679
120P_0402_50V9

2

2

1

1
R291
100_0402_1%
PX@

C678
0.1U_0402_16V7K
PX@

2

2

2

1

1
R290
100_0402_1%
PX@

C677
0.1U_0402_16V7K
PX@

2

+VDD_MEM15_REFSA

1 R289
2
10_0402_5%
PX@
2

+VDD_MEM15_REFDA

1 R288
2
51.1_0402_1%
PX@

1

24,25 DRAM_RST#

+1.5VSG
1

+1.5VSG

2

2

R285
40.2_0402_1%
PX@
2

R284
40.2_0402_1%
PX@

2

1

R283
4.7K_0402_5%
@

C681
0.1U_0402_16V7K
PX@

2

+1.5VSG

1

+1.5VSG

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_Thames XT_M2_MEM IF
Size
C
Date:

5

4

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

23

of

53

5

4

3

U11

2

U12

1

U13

U14
ZZZ2

23

23

MDA[0..63]

MDA[0..63]

MAA[14..0]

MAA[14..0]

DQMA#[7..0]

QSA[7..0]

DQMA#[7..0]

23
23
23

A_BA0
A_BA1
A_BA2

M2
N8
M3

QSA[7..0]

23
23
23

CLKA0
CLKA0#
CKEA0

J7
K7
K9

23
23
23
23
23

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA#[7..0]

QSA#[7..0]

C

QSA1
QSA3

F3
C7

DQMA#1
DQMA#3

E7
D3

QSA#1
QSA#3

G3
B7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

D7
C3
C8
C2
A7
A2
B8
A3

MDA31
MDA27
MDA30
MDA26
MDA28
MDA24
MDA29
MDA25

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA2
QSA0

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#2
DQMA#0

E7
D3

QSA#2
QSA#0

G3
B7

+1.5VSG

DRAM_RST# T2

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA22
MDA19
MDA20
MDA18
MDA21
MDA16
MDA23
MDA17

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA7
MDA1
MDA4
MDA3
MDA6
MDA2
MDA5

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R296
240_0402_1%
PX@

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

PX@
CLKA_0
2
40.2_0402_1%

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

RESET
ZQ/ZQ0

VREFCA
VREFDQ

CLKA1
CLKA1#
CKEA1

J7
K7
K9

23
23
23
23
23

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA4
QSA7

F3
C7

DQMA#4
DQMA#7

E7
D3

QSA#4
QSA#7

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

23
23
23

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

A_BA0
A_BA1
A_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

L8

E3
F7
F2
F8
H3
H8
G2
H7

MDA33
MDA35
MDA34
MDA39
MDA32
MDA37
MDA36
MDA38

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA57
MDA62
MDA56
MDA60
MDA59
MDA61
MDA58

VREFC_A4
VREFD_Q4

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

BA0
BA1
BA2

DRAM_RST# T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VREFC_A3
VREFD_Q3

+1.5VSG

BA0
BA1
BA2

1

L8

1

ZQ/ZQ0

J1
L1
J9
L9

R295
240_0402_1%
PX@

CLKA0 1
R299

VREFC_A2
VREFD_Q2

A_BA0
A_BA1
A_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

L8

MDA11
MDA13
MDA8
MDA14
MDA10
MDA15
MDA9
MDA12

+1.5VSG

BA0
BA1
BA2

T2

23,25 DRAM_RST#

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

ZQ/ZQ0

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#
CKEA1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA5

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#5

E7
D3

QSA#6
QSA#5

G3
B7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSG

DRAM_RST# T2
L8

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA51
MDA49
MDA52
MDA48
MDA53
MDA50
MDA54
MDA55

D7
C3
C8
C2
A7
A2
B8
A3

MDA41
MDA44
MDA40
MDA45
MDA43
MDA46
MDA42
MDA47

1GVRAM-HYNIX 2GVRAM-HYNIX

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

RESET
ZQ/ZQ0

ZZZ4

ZZZ5

1GVRAM-SAM

2GVRAM-SAM

X76L03@

X76L04@

+1.5VSG

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

X76L02@

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

X76L01@

D

+1.5VSG

BA0
BA1
BA2

ZZZ3

C

1

23

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

J1
L1
J9
L9

R297
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R298
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

23

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

VREFCA
VREFDQ

1

23

M8
H1

2

D

VREFC_A1
VREFD_Q1

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

PX@
2
40.2_0402_1%
+1.5VSG

1

1

2

2

1

C689
2
1

PX@

2

C688
1
2

2

1
2

1

C687
1

2

C686
1

1
2

2

2

2

2

2
1
2

C684
1

1

1

1

1

1
2
2

C683
1

1
2

2

2

1
2

PX@

VREFD_Q4

R313
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

B

VREFC_A4
R318
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

R308
4.99K_0402_1%
PX@

VREFD_Q3

R312
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

+1.5VSG

R307
4.99K_0402_1%
PX@

VREFC_A3
R317
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

+1.5VSG

R306
4.99K_0402_1%
PX@

VREFD_Q2

R316
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

+1.5VSG

R305
4.99K_0402_1%
PX@

VREFC_A2
R315
4.99K_0402_1%
PX@

0.1U_0402_16V7K

PX@

+1.5VSG

R304
4.99K_0402_1%
PX@

VREFC_A1
R314
4.99K_0402_1%
PX@

0.1U_0402_16V7K

C690
0.01U_0402_16V7K
PX@

0.1U_0402_16V7K

R311
4.99K_0402_1%
PX@

2
40.2_0402_1%

C691
1

VREFD_Q1

PX@
CLKA1# 1
R310

R303
4.99K_0402_1%
PX@

2

CLKA_1
2
40.2_0402_1%

1

CLKA1 1
R309

R302
4.99K_0402_1%
PX@
2

PX@

2

R301
4.99K_0402_1%
PX@

B

+1.5VSG

1

+1.5VSG

2

+1.5VSG

C685
1

C682
0.01U_0402_16V7K
PX@

1

2

1

CLKA0# 1
R300

+1.5VSG
+1.5VSG

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1U_0402_6.3V6K
PX@
C728

2

1U_0402_6.3V6K
PX@
C727

1

1U_0402_6.3V6K
PX@
C726

2

1U_0402_6.3V6K
PX@
C725

1

1U_0402_6.3V6K
PX@
C724

2

1U_0402_6.3V6K
PX@
C723

1

1U_0402_6.3V6K
PX@
C722

2

1U_0402_6.3V6K
PX@
C721

1

1U_0402_6.3V6K
PX@
C720

2

1U_0402_6.3V6K
PX@
C719

1

2

1U_0402_6.3V6K
PX@
C718

1

1U_0402_6.3V6K
PX@
C717

2

1U_0402_6.3V6K
PX@
C716

1

1U_0402_6.3V6K
PX@
C715

2

1U_0402_6.3V6K
PX@
C714

1

1U_0402_6.3V6K
PX@
C713

2

1U_0402_6.3V6K
PX@
C712

1

1U_0402_6.3V6K
PX@
C711

2

+1.5VSG

1U_0402_6.3V6K
PX@
C710

1

1U_0402_6.3V6K
PX@
C709

2

10U_0603_6.3V6M
PX@
C708

1

10U_0603_6.3V6M
PX@
C707

2

10U_0603_6.3V6M
PX@
C706

1

10U_0603_6.3V6M
PX@
C705

2

0.1U_0402_16V7K
PX@
C704

1

0.1U_0402_16V7K
PX@
C703

2

0.1U_0402_16V7K
PX@
C702

1

0.1U_0402_16V7K
PX@
C701

2

0.1U_0402_16V7K
PX@
C700

1

0.1U_0402_16V7K
PX@
C699

2

0.1U_0402_16V7K
PX@
C698

1

0.1U_0402_16V7K
PX@
C697

2

0.1U_0402_16V7K
PX@
C696

1

0.1U_0402_16V7K
PX@
C695

2

0.1U_0402_16V7K
PX@
C694

1

0.1U_0402_16V7K
PX@
C693

0.1U_0402_16V7K
PX@
C692

+1.5VSG

1

2

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
ATI_Thames XT_M2_VRAM_A
Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

24

of

53

4

3

23

23

DQMB#[7..0]

QSB[7..0]

QSB#[7..0]

B_BA0
B_BA1
B_BA2

DQMB#[7..0]

QSB[7..0]

23
23
23

CLKB0
CLKB0#
CKEB0

J7
K7
K9

QSB#[7..0]

23
23
23
23
23

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

PX@

C

CLKB0 1
R319

M2
N8
M3

23
23
23

QSB1
QSB3

F3
C7

DQMB#1
DQMB#3

E7
D3

QSB#1
QSB#3

G3
B7

CLKB_0
2
40.2_0402_1%
PX@

L8

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

R321
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

CLKB_1
2
40.2_0402_1%

1

2
40.2_0402_1%

2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB2
QSB0

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

+1.5VSG

U17

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

L8

E3
F7
F2
F8
H3
H8
G2
H7

MDB21
MDB20
MDB23
MDB18
MDB19
MDB17
MDB22
MDB16

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB4
MDB3
MDB5
MDB0
MDB7
MDB2
MDB6

VREFC_A3_B
VREFD_Q3_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

BA0
BA1
BA2

DRAM_RST# T2

ZQ/ZQ0

J1
L1
J9
L9

R322
240_0402_1%
PX@

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

PX@
CLKB1# 1
R326

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

PX@
CLKB1 1
R325

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

C729
0.01U_0402_16V7K
PX@

MDB30
MDB26
MDB29
MDB24
MDB28
MDB25
MDB31
MDB27

M8
H1

+1.5VSG

BA0
BA1
BA2

2

2

T2

23,24 DRAM_RST#

2
40.2_0402_1%
1

CLKB0# 1
R320

D7
C3
C8
C2
A7
A2
B8
A3

VREFC_A2_B
VREFD_Q2_B

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

M2
N8
M3

23
23
23

CLKB1
CLKB1#
CKEB1

J7
K7
K9

23
23
23
23
23

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB6
QSB5

F3
C7

DQMB#6
DQMB#5

E7
D3

QSB#6
QSB#5

G3
B7

DRAM_RST# T2
L8

U18

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48

D7
C3
C8
C2
A7
A2
B8
A3

MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB44
MDB42

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFC_A4_B
VREFD_Q4_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB4
QSB7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#4
DQMB#7

E7
D3

QSB#4
QSB#7

G3
B7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSG

DRAM_RST# T2
L8

1

23

MAB[14..0]

MAB[14..0]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB10
MDB12
MDB8
MDB13
MDB11
MDB14
MDB9
MDB15

J1
L1
J9
L9

R323
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

23

MDB[0..63]

MDB[0..63]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

23

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

D

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

U16

VREFCA
VREFDQ

1

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB33
MDB39
MDB34
MDB36
MDB32
MDB38

D7
C3
C8
C2
A7
A2
B8
A3

MDB63
MDB59
MDB61
MDB56
MDB60
MDB57
MDB62
MDB58

D

+1.5VSG

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C

1

U15
VREFC_A1_B M8
VREFD_Q1_B H1

2

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R324
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

5

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
X76@

C730
0.01U_0402_16V7K
PX@

+1.5VSG

+1.5VSG

+1.5VSG

+1.5VSG

+1.5VSG

+1.5VSG

+1.5VSG

+1.5VSG

2

2

2

2

VREFD_Q4_B
1

1

1

R342
4.99K_0402_1%
PX@

2

2

2

1
R341
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C738

VREFC_A4_B
0.1U_0402_16V7K
PX@
C737

2

1

2

1

0.1U_0402_16V7K
PX@
C736

0.1U_0402_16V7K
PX@
C735

R334
4.99K_0402_1%
PX@

VREFD_Q3_B

R340
4.99K_0402_1%
PX@

2

1

1

1

1

1
2

2

1

R339
4.99K_0402_1%
PX@

2

R333
4.99K_0402_1%
PX@

VREFC_A3_B
1

1

1

2

1

2

2

2

2

R332
4.99K_0402_1%
PX@

VREFD_Q2_B

R338
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C734

2

1

R331
4.99K_0402_1%
PX@

VREFC_A2_B
1

R337
4.99K_0402_1%
PX@
2

1

1

R336
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C732

2

VREFC_A1_B
0.1U_0402_16V7K
PX@
C731

1

0.1U_0402_16V7K
PX@
C733

VREFD_Q1_B

R335
4.99K_0402_1%
PX@

R330
4.99K_0402_1%
PX@
2

R329
4.99K_0402_1%
PX@
2

R328
4.99K_0402_1%
PX@
2

R327
4.99K_0402_1%
PX@

1

1

B

1

B

+1.5VSG
+1.5VSG

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

Compal Secret Data

Security Classification
Issued Date

1

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

2

1

2

1

2

1

2

1

2

1

2

A

Compal Electronics, Inc.
ATI_Thames XT_M2_VRAM_B

Size
C
Date:

5

1

1U_0402_6.3V6K
PX@
C775

2

1U_0402_6.3V6K
PX@
C774

1

1U_0402_6.3V6K
PX@
C773

2

1U_0402_6.3V6K
PX@
C772

1

2

1U_0402_6.3V6K
PX@
C771

1

1U_0402_6.3V6K
PX@
C770

2

1U_0402_6.3V6K
PX@
C769

1

1U_0402_6.3V6K
PX@
C768

2

1U_0402_6.3V6K
PX@
C767

1

1U_0402_6.3V6K
PX@
C766

2

1U_0402_6.3V6K
PX@
C765

1

1U_0402_6.3V6K
PX@
C764

2

1U_0402_6.3V6K
PX@
C763

1

2

1U_0402_6.3V6K
PX@
C762

1

1U_0402_6.3V6K
PX@
C761

2

1U_0402_6.3V6K
PX@
C760

1

1U_0402_6.3V6K
PX@
C759

2

1U_0402_6.3V6K
PX@
C758

1

+1.5VSG

1U_0402_6.3V6K
PX@
C757

2

1U_0402_6.3V6K
PX@
C756

1

10U_0603_6.3V6M
PX@
C755

2

10U_0603_6.3V6M
PX@
C754

1

10U_0603_6.3V6M
PX@
C753

2

10U_0603_6.3V6M
PX@
C752

1

0.1U_0402_16V7K
PX@
C751

2

0.1U_0402_16V7K
PX@
C750

1

0.1U_0402_16V7K
PX@
C749

2

0.1U_0402_16V7K
PX@
C748

1

0.1U_0402_16V7K
PX@
C747

2

0.1U_0402_16V7K
PX@
C746

1

0.1U_0402_16V7K
PX@
C745

2

0.1U_0402_16V7K
PX@
C744

1

2

0.1U_0402_16V7K
PX@
C743

A

1

0.1U_0402_16V7K
PX@
C742

2

0.1U_0402_16V7K
PX@
C741

1

0.1U_0402_16V7K
PX@
C740

0.1U_0402_16V7K
PX@
C739

+1.5VSG

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

25

of

53

5

4

3

VGA Power

2

+3VS to +3VSG (60mA)

+1.5V to +1.5VSG (5.2A)

Q7

+3VS
+1.5VSG

D

2

3

C537
PX@
0.1U_0603_25V7K

VGA_PWR_ON#

29,33,39

SUSP

2
R344
33_0603_5%
1

2

C535
1U_0402_6.3V4Z
2 PX@

1

2
G

1
PX@

SUSP

D

Q92

D

1

S PX@
SSM3K7002FU_SC70-3

2

Q93
2
G

VGA_PWRON#

VGA_PWRON#

S

3

1
R345

3VSG_GATE

1

@
2 R347
1
0_0402_5%
PX@
2 R420
1
0_0402_5%

PX@ 2
100K_0402_5%

D

PX@

2
G
+VSBP

3

S PX@
SSM3K7002FU_SC70-3

1

1

2 PX@

1

SSM3K7002FU_SC70-3
PX@

C536
PX@
0.1U_0603_25V7K

3

4

2
1 1

2 1.5VSG_PWREN#
G
PX@
S
SSM3K7002FU_SC70-3

2

PX@
1

C534

Q91

1

3
10U_0603_6.3V6M

D

PX@

C533

2

PX@
R343
10_0603_5%

0.1U_0402_16V7K
C532

C538
0.1U_0402_16V7K

PX@
C531
1U_0402_6.3V4Z
2

10U_0603_6.3V6M

1

1

1.5VSG_GATE

D

Q94
2
G

2

C530

2 PX@

1

PX@

1
2
3

10U_0603_6.3V6M

1.5VSG_PWREN#
1
47K_0402_5%

1

8
7
6
5

C777

0.1U_0402_16V7K
PX@ C776

10U_0603_6.3V6M

2

1

1 PX@
2
R346
100K_0402_5%

+VSBP

1.5_VDDC_PWREN#
2
PX@ R348

1

+3VSG

AO3404AL_SOT23

U19
PX@
AO4430L_SO8

S

+1.5V

D

1

1

C539
0.1U_0402_16V7K

2

@

@

PX4.0: control by SUSP
PX5.0: control by VGA_PWR_ON#

+5VALW

C

+5VALW

2
G
S

PX@
SSM3K7002FU_SC70-3

2
1
2
G

S

1

1

VGA_PWR_ON#

D

Q98
1.5_VDDC_PWREN#

PX@
SSM3K7002FU_SC70-3

3

1

S SSM3K7002FU_SC70-3
PX@

D

Q97

3

PX@
R355
10K_0402_5%

PX@

D
D

3

1

Q96
2
G

1

1
3

20,49 1.5_VDD_PWREN
S SSM3K7002FU_SC70-3
PX@

2

PX@
R354
100K_0402_5%

D

R353
33_0603_5%

1

R352
470_0603_5%
PX@

S

Q99

2 VGA_PWR_ON#
G
PX@
SSM3K7002FU_SC70-3

2

VGA_PWR_ON
1

20,43,49

Q95
2
G

+1.8VSG

2

2
R351
470_0603_5%
PX@
1

1.5_VDDC_PWREN#

1

R350
100K_0402_5%
PX@

1

R349
100K_0402_5%
PX@
VGA_PWR_ON#

+VGA_CORE

2

2

+1.0VSG

3

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK

Size Document Number
Custom
QML70
Date:

Rev
0.2

LA-8371P

Wednesday, October 19, 2011
1

Sheet

26

of

53

5

4

Pin5 (DPV33) < 20mA
Pin 11 (DPV12) < 100mA
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)
Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)
Pin 22 (PVCC) < 50 mA
Pin 43 (VCCK) < 50mA

1

2

RTD2136S
+DVCC33

+3VS_RT

22

+SWR_V12

Close to 5 pin

+DVCC33
L28 2
40 mils
1
FBMA-L11-201209-221LMA30T_0805
+AVCC33
L29 2
1
FBMA-L11-201209-221LMA30T_0805
+SW_LX
L30 1
60 mils
2
4.7UH_PG031B-4R7MS_1.1A_20%
60 mils

2

DP_V33

17

SWR_LX

15

2

DP2_TXP0_C
DP2_TXN0_C

8 DP2_TXP0_C
8 DP2_TXN0_C

DP2_TXP1_C
DP2_TXN1_C

8 DP2_TXP1_C
8 DP2_TXN1_C

DP2_AUXP_C
DP2_AUXN_C

8 DP2_AUXP_C
8 DP2_AUXN_C

Close to 22 pin

10

LVDS_HPD
2
R616

C

2 1K_0402_5%

11

DP_V12

7
8

LANE0P
LANE0N

9
10

LANE1P
LANE1N
AUX-CH_P
AUX-CH_N

PWMIN
TESTMODE
DP_REXT

CSCL
CSDA

Close to 11 pin

1 R362
1 R363

2 0_0402_5%
2 0_0402_5%

CIICSCL
CIICSDA

MIICSCL0
MIICSDA0

13
14

CIICSCL1
CIICSDA1

1

2

C551

Close to L30

2

0.1U_0402_16V4Z

2

1
C550

0.1U_0402_16V4Z

1
C549

2

0.1U_0402_16V4Z
C548

22U_0805_6.3V6M

1

APU_TXOUT2APU_TXOUT2+

TXO3+
TXO3-

33
34

TXEC+
TXEC-

25
26

APU_TZOUT_CLKAPU_TZOUT_CLK+

TXE0+
TXE0-

31
32

APU_TZOUT0APU_TZOUT0+

APU_TZOUT0- 28
APU_TZOUT0+ 28

TXE1+
TXE1-

29
30

APU_TZOUT1APU_TZOUT1+

APU_TZOUT1- 28
APU_TZOUT1+ 28

TXE2+
TXE2-

27
28

APU_TZOUT2APU_TZOUT2+

TXE3+
TXE3-

23
24

MIICSCL1
MIICSDA1

46
45

APU_LVDS_CLK
APU_LVDS_DAT

APU_LVDS_CLK 28
APU_LVDS_DAT 28

PANEL_VCC
PWMOUT
BL_EN

20
19
44

TL_ENVDD
TL_INVT_PWM
TL_BKOFF#

TL_ENVDD 28
TL_INVT_PWM 28
TL_BKOFF# 28,37

APU_TXOUT_CLK- 28
APU_TXOUT_CLK+ 28

8
7
6
5

MIIC_SCL
MIIC_SDA

APU_TXOUT0- 28
APU_TXOUT0+ 28

VCC
WP
SCL
SDA

A0
A1
A2
GND

D

1
2
3
4

CAT24C64WI-GT3_SO8

Addr: A8 (1010 100X)

APU_TXOUT1- 28
APU_TXOUT1+ 28
APU_TXOUT2- 28
APU_TXOUT2+ 28

+DVCC33

APU_TZOUT_CLK- 28
APU_TZOUT_CLK+ 28

R776
4.7K_0402_5%
MIIC_SCL

EEPROM

APU_TZOUT2- 28
APU_TZOUT2+ 28

R777
4.7K_0402_5%
@

ROMLESS

+DVCC33

OTHERS

21
2
12

TP2
2
12K_0402_1%

+1.2VS

1
R357

37
38

DP_HPD

MIIC_SCL 48
MIIC_SDA 47

+SWR_V12
2
0_0805_5%

TXO2+
TXO2-

1
100K_0402_5%

1
R361

@

APU_TXOUT1APU_TXOUT1+

VCCK

1

10,28 APU_INVT_PWM

60 mils

39
40

TXO1+
TXO1-

SWR_VCCK

4
3

R358 1

APU_TXOUT0APU_TXOUT0+

TXO0+
TXO0-

DP

Close to 18 pin

1
C547

0.1U_0402_16V4Z

2

1
C546

Close to L28

1

0.1U_0402_16V4Z
C545

22U_0805_6.3V6M

2

C544

0.1U_0402_16V4Z
C543

10U_0603_6.3V6M

2

1

41
42

SWR_VDD

5

+DVCC33

APU_TXOUT_CLKAPU_TXOUT_CLK+

PVCC

18

43

1

EEROM
U44

35
36

TXOC+
TXOC-

PWR

Close to L29

1
C542

2

C541

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
C540

10U_0603_6.3V6M

D

+DVCC33
U21

2

+AVCC33

1

2
0_0805_5%

2

1
R356

1

1

30mil

LVDS

+3VS_RT

30mil

2

DP_GND

GND

+3VS

3

Power Consumption:

6

GND

16

PAD

49

1
R359

2
0_0402_5%

APU_LVDS_DAT

R364 1

2 4.7K_0402_5%

APU_LVDS_CLK

R366 1

2 4.7K_0402_5%

MIIC_SDA

R778 1

2 4.7K_0402_5%

CSCL

R779 1

2 4.7K_0402_5%

CSDA

R780 1

2 4.7K_0402_5%

TL_INVT_PWM R568 1

2 100K_0402_5%

C

RTD2136S-VE-CG_QFN48_6X6
LVDS_HPD

R569 1

2 100K_0402_5%

TL_BKOFF#

R570 1

2 100K_0402_5%

Close to 43 pin

+3VS_RT
B

1

B

2

R365
100K_0402_5%
@

1

DP2_AUXN_C
DP2_AUXP_C

2

R367
100K_0402_5%
@

+3VS_RT

2

AUX termination

1

EC_SMB_DA2

6

Q3A
DMN66D0LDW-7_SOT363-6~D
CSCL
A

EC_SMB_DA2 8,19,37

5

CSDA

4

3

EC_SMB_CK2

EC_SMB_CK2 8,19,37

A

Q3B
DMN66D0LDW-7_SOT363-6~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LVDS Translator - RTD2132S
Size Document Number
Custom
Date:

Rev
0.11

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
1

27

of

53

5

4

3

2

1

D6
BLUE

+5VALW

CRT

GREEN

6

5

4

I/O4

I/O2

VDD

GND

I/O3

I/O1

RED

3

2

1

W=40mils

+5VS

AZC099-04S.R7G_SOT23-6

2

+5VS_CRTVCC

1

D9
D

HSYNC_L

L15
RED
1
2
CHILISIN NBQ160808T-800Y-N 0603

FCH_CRT_R

15 FCH_CRT_R

L16
FCH_CRT_G

GREEN
1
2
CHILISIN NBQ160808T-800Y-N 0603

I/O2

VDD

GND

I/O3

VSYNC_L

3

D8
RB491D_SOT23-3

D

2

VGA_DDC_DATA_C

1

I/O1

AZC099-04S.R7G_SOT23-6

1

C408

2

2

C409

1

2

1

C410

1

C411

2

10P_0402_50V8J

1

10P_0402_50V8J

C407

2

10P_0402_50V8J

1

10P_0402_50V8J

C406

10P_0402_50V8J

R440

4

I/O4

D7

2
1
150_0402_1%

R439

2
1
150_0402_1%

2
1
150_0402_1%

R438

VGA_DDC_CLK_C

L17
BLUE
1
2
CHILISIN NBQ160808T-800Y-N 0603

FCH_CRT_B

15 FCH_CRT_B

5

+5VALW

10P_0402_50V8J

15 FCH_CRT_G

6

2

2

2

1

1

3

+5VS_CRTVCC

3
AZC199-02SPR7G_SOT23-3

ESD

JCRT1
T36

CRTTEST

RED
+5VS
+5VS_CRTVCC

HSYNC_L
BLUE

G

1
@ C419
33P_0402_50V8K

2

C414

1

1

1

1

VGA_DDC_DATA_C
2

BSS138_SOT23

3

Q21

VGA_DDC_CLK_C

BSS138_SOT23

1

2

2

2
2

2

2

FCH_CRT_DDC_SCL

15 FCH_CRT_DDC_SCL

10P_0402_50V8J

10P_0402_50V8J

P
OE#

5
1
3

@ C416

2

1

VGA_DDC_CLK_C

G
G

16
17

SUYIN_070546FR015S251ZR
CONN@
C

D

@ C415

1

S

1

3

R444
4.7K_0402_5%

U24
SN74AHCT1G125GW_SOT353-5

FCH_CRT_DDC_SDA

15 FCH_CRT_DDC_SDA

VSYNC_L

2
10_0402_5%

4.7K_0402_5%

D_CRT_VSYNC 1
R446

4

D

Y

S

A

G

2

VSYNC_L

R443

G

FCH_CRT_VSYNC

R132
2.2K_0402_5%

3

R129
2.2K_0402_5%

+5VS

15 FCH_CRT_VSYNC

HSYNC_L

2
10_0402_5%

2

1
R442

2

D_CRT_HSYNC

4

U23
SN74AHCT1G125GW_SOT353-5

1

Y

G

A

1

2

1
2
C413
0.1U_0402_16V4Z

C

VGA_DDC_DATA_C
GREEN

+3VS

5
1
P
OE#

FCH_CRT_HSYNC

15 FCH_CRT_HSYNC

+3VS

10K_0402_5%
1

100P_0402_50V8J

R441
2

1
2
C412
0.1U_0402_16V4Z

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

Q22

@ C420
33P_0402_50V8K

1

@ C417
470P_0402_50V8J

1

2

2

@ C418
470P_0402_50V8J

@
FCH_CRT_DDC_SDA

2
0_0402_5%

FCH_CRT_DDC_SCL

2
0_0402_5%

1
R534

VGA_DDC_DATA_C

1
R535

VGA_DDC_CLK_C

2

6 2

1

2
G

C422
4.7U_0805_10V4Z

2

C423
2

0.1U_0402_16V4Z

R449
2
1
220K_0402_1%

2

B

1

2N7002DW-7-F_SOT363-6
Q1A

1
R450

2
0_0402_5%

+3VS
@
C426

C427

1

2

Q1B
2N7002DW-7-F_SOT363-6

5

W=80mils
+3VS

0.047U_0402_16V7K

APU_TXOUT0+
APU_TXOUT0-

27 APU_TXOUT0+
27 APU_TXOUT0-

APU_TXOUT1+
APU_TXOUT1-

27 APU_TXOUT1+
27 APU_TXOUT1-

APU_TXOUT2+
APU_TXOUT2-

27 APU_TXOUT2+
27 APU_TXOUT2-

APU_TXOUT_CLKAPU_TXOUT_CLK+

1

27 APU_TXOUT_CLK27 APU_TXOUT_CLK+

R451

Imax: 920mA
Inrush: 1.5A
JLVDS1

L18
B+_L
1
2
FBMA-L11-201209-221LMA30T_0805

B+

4

27 TL_ENVDD

4.7U_0805_10V4Z

D

2

C425

W=60mils

0.1U_0402_16V4Z

2

1

3

0.1U_0402_16V4Z

1

1

Imax: 409mA
Inrush: 1.5A

3

S

1
R448
47K_0402_5%

R447
100_0805_5%
C424

@

1

1

+LCDVDD

+3VS
Q23
SI2301BDS-T1-E3_SOT23-3

2

+LCDVDD
+5VALW

1

LCD POWER CIRCUIT
+LCDVDD

C421
680P_0402_50V7K

@

INVTPWM
DISPOFF#

2

100K_0402_5%

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

GMD
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

W=80mils

42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+LCDVDD

APU_TZOUT1APU_TZOUT1+

APU_TZOUT1- 27
APU_TZOUT1+ 27

APU_TZOUT2+
APU_TZOUT2-

APU_TZOUT2+ 27
APU_TZOUT2- 27

APU_TZOUT0APU_TZOUT0+

APU_TZOUT0- 27
APU_TZOUT0+ 27

APU_TZOUT_CLKAPU_TZOUT_CLK+

APU_TZOUT_CLKAPU_TZOUT_CLK+

APU_LVDS_CLK
APU_LVDS_DAT

B

27
27

APU_LVDS_CLK 27
APU_LVDS_DAT 27

ACES_87242-4001-09
CONN@

+3VS

Camera
JCM1

Panel PWM Control
R454
4.7K_0402_5%
@

B+_L

2

2
10,27 APU_INVT_PWM

2

C812
0.1U_0603_50V_X7R

27 TL_INVT_PWM

@

USB20_P2

DMIC_CLK

USB20_N2

DMIC_DATA

1
C428
22P_0402_50V8J

1

1

@

2

C429
22P_0402_50V8J
@

2

3

2

3
DISPOFF#

2

3
1

1

2
33_0402_5%
2

@

D25
@

1

BKOFF#

2

3
BKOFF#

D24

1

37

2

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3

1

1

Q40
SSM3K7002FU_SC70-3~D
S

R456
10K_0402_5%

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

Title

Compal Electronics, Inc.
P10-LVDS/CRT CONN

2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
C
Date:

5

7
8

ACES_87213-0600G
CONN@

A

R539
@
R455

D

2
G
3

0_0402_5%
TL_BKOFF#
1

R453
33_0402_5%
@

Colse to JCM1

1
2

27,37 TL_BKOFF#

R764
0_0402_5%
1
@

INVTPWM

2
1
R538
1
R458

Panel Backlight Control

R29
100K_0402_5%

2

R457

@
2
0_0402_5% @
2
0_0402_5%

PWR_SRC_ON

A

+LCDVDD

0_0402_5%
1

1

G

37 EC_INVT_PWM

3

1

R763
100K_0402_5%~D

2

C613
1000P_0402_50V7K~D

1

R452
33_0402_5%

1
2
3
4
5 G1
6 G2

1

D

2 0_0805_5%

S

@

2

Q54
SI3457CDV-T1-E3_TSOP6~D
+B+_Q
R765 1
6
4
5
2
1
1

60mil

B+

1
2
3
4
5
6

+3VS

USB20_N2
USB20_P2
DMIC_CLK
DMIC_DATA

USB20_N2
USB20_P2
DMIC_CLK
DMIC_DATA

2

1

60mil

14
14
31
31

4

3

2

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

28

of

53

5

4

3

2

1

10 9

HDMI_R_D1-

HDMI_R_D0+

D4
1 1

10 9

HDMI_R_D0+

HDMI_R_D1+

2 2

9 8

HDMI_R_D1+

HDMI_R_D0-

2 2

9 8

HDMI_R_D0-

HDMI_R_D2-

4 4

7 7

HDMI_R_D2-

HDMI_R_CK+

4 4

7 7

HDMI_R_CK+

HDMI_R_D2+

5 5

6 6

HDMI_R_D2+

HDMI_R_CK-

5 5

6 6

HDMI_R_CK-

8

8

AZ1045-04F DFN2510P10E

D

D

HDMI_DETECT

2
G

AZ1045-04F DFN2510P10E

S
APU_HDMI_HPD

10 APU_HDMI_HPD

1

3 3

1

3 3

3

D

R368
2.2K_0402_5%
1

D3
1 1

2

+3VS

HDMI_R_D1-

Q37
SSM3K7002FU_SC70-3

R369
100K_0402_5%
2

For ESD request.

D5
HDMI_DETECT

6

I/O4

I/O2

VDD

GND

3

HDMI_SDATA
U22

2
GND

I/O3

I/O1

1

1

HDMI_SCLK
1

C787

AZC099-04S.R7G_SOT23-6

For ESD request.
2

0.1U_0402_16V7K

4

+HDMI_5V_OUT

2

IN
OUT

3
1

C788

AP2330W-7_SC59-3

2
+5VS

Q100

55mA
D

HDMI_R_D1-

26,33,39

SUSP

HDMI_R_D1+

1

HDMI_R_D2+

D

3

2

HDMI_R_D2-

S

2
G

1

C

EN_HDMI
R374
Q33
SSM3K7002FU_SC70-3
@
@

HDMI_R_D0-

1

C798
@

HDMI_R_D0+

2

0.1U_0402_16V7K

@
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2
604_0402_1%
2

C794
@

1

R370
R371
TMDS_GND
1
R372
1
R373
1
R375
1
R376
1
R377
1
R378
1
R380
1

2

2

2

HDMI_D2+
HDMI_D2-

@
1U_0603_10V4Z

+VSBP

F1
1

+HDMI_5V

W=40mils0.5A 15VDC_FUSE

@
SI3456BDV-T1-E3 1N TSOP6

1.5M_0402_5%

HDMI_D1+
HDMI_D1-

+HDMI_5V_OUT

3

2

1U_0603_10V6K

HDMI_TX2P
HDMI_TX2N

8 HDMI_TX2P
8 HDMI_TX2N

1

C792
@

1

HDMI_TX1P
HDMI_TX1N

8 HDMI_TX1P
8 HDMI_TX1N

6
5
2
1

4

HDMI_D0+
HDMI_D0-

470K_0402_5%

HDMI_TX0P
HDMI_TX0N

8 HDMI_TX0P
8 HDMI_TX0N

HDMI_CK+
HDMI_CK-

1
1 C564
C789
1
1 C790
C791
1
1 C793
C795
1
1 C796
C797

G

C

2
0.1U_0402_16V7K 2
0.1U_0402_16V7K
2
0.1U_0402_16V7K 2
0.1U_0402_16V7K
2
0.1U_0402_16V7K 2
0.1U_0402_16V7K
2
0.1U_0402_16V7K 2
0.1U_0402_16V7K

S

HDMI_CLKP
HDMI_CLKN

8 HDMI_CLKP
8 HDMI_CLKN

0.1U_0402_16V7K

5

+5VS

HDMI_R_CKHDMI_CKHDMI_R_CK+

1
R379
L32
1

@

HDMI_R_CK-

2
0_0402_5%

1

2

4

3

2

1

+HDMI_5V_OUT

D

2
G Q34

R381
1
2
10K_0402_5%

4
+5VS

3

(pin 19) plug in 5V

WCM-2012HS-900T_4P
JHDMI1

3

S

HDMI_DETECT

SSM3K7002FU_SC70-3
HDMI_CK+

1
R382

@

2
0_0402_5%

HDMI_R_CK+
HDMI_SDATA
HDMI_SCLK

B

HDMI_D0+

1
R383

@

2
0_0402_5%

HDMI_R_D0+
HDMI_R_CK-

L33
4
1

4

3

1

2

3

HDMI_R_CK+
HDMI_R_D0-

2

HDMI_R_D0+
HDMI_R_D1-

WCM-2012HS-900T_4P

HDMI
HDMI_D0-

1
R384

2
0_0402_5%

HDMI_R_D0-

@

1
R385

2
0_0402_5%

HDMI_R_D1+

@

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

+3VS

+3VS

HDMI_D1+

+HDMI_5V_OUT

L35

1

1
2

1
2

2

1
2

2

1

HDMI_D1-

R390

G

R389

2K_0402_5%

2K_0402_5%

R388

R387

10K_0402_5%

10K_0402_5%

1

2

4
R386
0_0402_5%

HDMI_D2+
3

1
D

HDMI_SCLK

3

Q35
12N7002K-C_SOT23-3

3

1

2

@

1
R392

@

4
1

Q36
2N7002K-C_SOT23-3

HDMI_D2-

SUYIN_100042GR019M26DZL
CONN@

3
2

2
0_0402_5%

HDMI_R_D1-

2
0_0402_5%

HDMI_R_D2+

WCM-2012HS-900T_4P

4

3

1

2

3

Issued Date

1
R393

@

2

2
0_0402_5%

A

HDMI_R_D2-

Compal Secret Data

Security Classification

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Compal Electronics, Inc.
HDMI Connector

Size
C
Date:

5

B

20
21
22
23

HDMI_SDATA

D

HDMI_DATA

S

8

4

L34

G

A

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

WCM-2012HS-900T_4P

1
R391

2

HDMI_CLK

S

8

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011
1

Sheet

29

of

53

2

+LAN_IO

2

2

D

S

2 EN_WOL#
G
SSM3K7002FU_SC70-3
Q27

1

C451

2

1

C452

2

1

C453

2

1

C454

2

1

C455

2

2

0.1U_0402_16V7K

1

2

+LAN_IO_DISC

1

C450

1

1
C462

3

2

1
C461

1
C449

W=20mils

0.1U_0402_16V7K

2

1
C460

0.1U_0402_16V7K

2

2

1
C459

0.1U_0402_16V7K

2

D

1
C458

0.1U_0402_16V7K

C457

0.1U_0402_16V7K

2

G

+5VALW

1

AO3419L 1P SOT23-3

2

0.1U_0402_16V7K

D

S

C456
1U_0402_6.3V6K

R465
470_0603_5%

0.1U_0402_16V7K

+LAN_IO
1

0.1U_0402_16V7K

2

+3VALW
Q26
3

+LAN_VDD
0.1U_0402_16V7K

W=60mils
Rising time: 1mS ~ 100mS (10%~90%)

1

1

0.1U_0402_16V7K

W=60mils

3

0.1U_0402_16V7K

4

0.1U_0402_16V7K

5

D

These caps close to Pin 3,6,9,13,29,41,45

R467
1
2 EN_WOL#
220K_0402_5%~N

2

R470
10K_0402_5%

C464

D

U25
PCIE_DTX_CRX_P1

22

HSOP

6 PCIE_DTX_C_CRX_N1

C470 1

20.1U_0402_16V7K

PCIE_DTX_CRX_N1

23

HSON

LED3/EEDO
LED1/EESK
LED0

HSIP
HSIN

EECS/SCL
EEDI/SDA

R472

31
37
40

1
2
C469
3
18P_0402_50V8J

30 R473 1
32 R474 1

2 10K_0402_5%
2 10K_0402_5%
+LAN_SROUT1.05

14 LAN_CLKREQ#

16

13,18,33 PLT_RST#

25

PERSTB

13 CLK_PCIE_LAN
13 CLK_PCIE_LAN#

19
20

REFCLK_P
REFCLK_N

ISOLATEB

2

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

2

R476 1
R478 1

1

+LAN_IO

1
2
+LAN_IO
R479
0_0402_5%
3.3V : Enable switching regulator
0V
: Disable switching regulator

R480 1

2 10K_0402_5%
2 1K_0402_5%

CKXTAL2

DVDD10
DVDD10
DVDD10

28

LANWAKEB

26

ISOLATEB

DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

14
15
38
33

+LAN_VDDREG

2 2.49K_0402_1%

B

34
35
46
24
49

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

2

W=60mils

2.2UH +-5% NLC252018T-2R2J-N

1
C471
2

1
C472
2

ENSWREG
EVDD10
VDDREG
VDDREG

AVDD10
AVDD10
AVDD10
AVDD10

RSET
GND
PGND

REGOUT

13
29
41

12
42
47
48

2

0.01U_0402_16V7K

JLAN1
21

+LAN_EVDD10

3
6
9
45
36

+LAN_VDD

+LAN_SROUT1.05

+V_DAC
LAN_MDIP2
LAN_MDIN2

7
8
9

+V_DAC
LAN_MDIP3
LAN_MDIN3

10
11
12

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

24
23
22

RJ45_TX0+
RJ45_TX0-

21
20
19

RJ45_RX1+
RJ45_RX1-

18
17
16

RJ45_TX2+
RJ45_TX2-

15
14
13

RJ45_TX3+
RJ45_TX3-

2

R485

2

1
0_0603_5%

6

RJ45_TX2-

5

RJ45_TX2+

4

RJ45_RX1+

3

RJ45_TX0-

2

PR1-

RJ45_TX0+

1

PR1+

PR4+
PR2B

PR3PR3+
PR2+

SHLD2

10

D16

D18

@
1

LSE-200NX3216TRLF_1206-2
2

D19

@
1

LSE-200NX3216TRLF_1206-2
2

D20

@
1

LSE-200NX3216TRLF_1206-2
2

D21

@
1

LSE-200NX3216TRLF_1206-2
2

D15
@

AZC199-02SPR7G_SOT23-3

LAN_MDIP1

+LAN_IO

LAN_MDIN1

6

5

4

I/O4

I/O2

VDD

GND

I/O3

I/O1

LAN_MDIP0

3

ESD

2

D17
LAN_MDIP3

+LAN_IO

LAN_MDIN0

1

LAN_MDIN3

AZC099-04S.R7G_SOT23-6

6

5

4

I/O4

I/O2

VDD

GND

I/O3

I/O1

LAN_MDIP2

3

2

LAN_MDIN2

1

A

AZC099-04S.R7G_SOT23-6

LANGND

ESD

@

Compal Secret Data

Security Classification
Issued Date

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

RJ45_RX1-

9

PR4-

C475
100P_1206_2KV7K
04/19

@

R486

7

1

LANGND
1
0_0603_5%

2

2
2
2
2

8

RJ45_TX3+

SANTA_130452-07
CONN@

TAIMAG_IH-160

A

1
1
1
1

75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%

SHLD1

RJ45_TX3-

3

4
5
6

MCT1
MX1+
MX1-

XTLO

1
2
C473
22P_0402_50V8J

3

+V_DAC
LAN_MDIP1
LAN_MDIN1

TCT1
TD1+
TD1-

25MHZ_12PF_X3G025000DC1H

1

1

C474 1

1
2
3

2

+LAN_IO

RTL8111F-CGT QFN 48P

R481
R482
R483
R484

GND

C

3.3V: 70mA
1.0V: 300mA

27
39

TS1
+V_DAC
LAN_MDIP0
LAN_MDIN0

4

1

These components close to Pin 36
( Should be place within 200 mils )

+LAN_VDD

GND
Y4

CKXTAL1

1K_0402_5%
R477
15K_0402_5%

1
2
4
5
7
8
10
11

1

XTLI

1

560_0402_5%

1

1

44

LAN_WAKE#

R475
+3VS

43

CLKREQB

W=60mils

2

3

+LAN_VDD

L19

C

XTLI

2

LAN_WAKE#

2

20.1U_0402_16V7K

XTLO

2

1
C467

2

C468 1

17
18

1
C466

SSM3K7002FU_SC70-3
Q29

6 PCIE_DTX_C_CRX_P1

6 PCIE_CTX_C_DRX_P1
6 PCIE_CTX_C_DRX_N1

2

4.7U_0603_6.3V6K

close to U25

3

C465

+LAN_EVDD10

S

1

14,33,37 FCH_PCIE_WAKE#

2

1

2
G

1

R471
10K_0402_5%

1

R469
1
2
0_0603_5%

1U_0402_6.3V6K

1

2

W=20mils

+LAN_VDD

+LAN_VDDREG

0.1U_0402_16V7K

S

W=40mils

R468
1
2
0_0603_5%

0.1U_0402_16V7K

+LAN_IO
+LAN_IO

C463
0.1U_0603_25V7K

0.1U_0402_16V7K

3

These caps close to Pin 12,27,39,42,47,48
1

Q28
SSM3K7002FU_SC70-3

2
G

EN_WOL
2

37

D

4.7U_0603_6.3V6K

1

1

R466
100K_0402_5%

4

3

2

Title

Compal Electronics, Inc.
P24-LAN RTL8111E

Size Document Number
Custom QML70 LA-8371P
Date:

Rev
0.11

Wednesday, October 19, 2011

Sheet
1

30

of

53

D

E

1K_0402_5%
MIC1_R 1
1 R495
2

MIC1
MIC2

MIC2_R 1
1 R496
2
1K_0402_5% AMIC1_L1
AMIC1_R1

28

DMIC_DATA

28

DMIC_CLK

37

DMIC_DATA
DMIC_CLK

1

2

L21
EC_MUTE#

EC_MUTE#

R500 1

DMIC_CLK_CODEC
FBMA-L10-160808-301LMT_2P
PD#

2 0_0402_5%

2

SPKOUT_R1

R490 1

2 0_0603_5%

SPK_R1

1
1 C482

SPK_R2

2 0_0603_5%

2
0.22U_0603_16V7K
@

2

1
C486

LINE2_L
LINE2_R

SPK_OUT_R+
SPK_OUT_R-

45
44

SPKOUT_R1
SPKOUT_R2

HP_OUT_L
HP_OUT_R

32
33

HP_OUTL
HP_OUTR

GPIO0/DMIC_DATA

3
2
C498

3

GPIO1/DMIC_CLK

10

HDA_SYNC_AUDIO

BCLK

6

HDA_BITCLK_AUDIO

5

HDA_SDOUT_AUDIO

8

HDA_SDIN_AUDIO1 R501
2
33_0402_5%

SDATA_OUT
SDATA_IN

ESD

HDA_SYNC_AUDIO

1

1
C496
@

2

R497 1
R498 1

14

2.2K_0402_1%
2
2.2K_0402_1%
2

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC_JD
MIC2

HDA_SDIN0 14

1 R503
2
20K_0402_1%
2 R504
1
39.2K_0402_1%

HP_JD

EAPD

47

1 R502

SPDIFO

48

0_0402_5%

PCBEEP
MONO_OUT

SENSE_A

Close to Codec pin13

13
18
36

1
C499
+MIC1_VREFO_L

2
35
2.2U_0603_16V6K
31
43
42
49
7

3

+1.5VS

SENSE A
MIC2_VREFO
SENSE B
MIC1_VREFO_R
LDO_CAP

CBP
CBN

VREF

MIC1_VREFO_L

JDREF

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE
AVSS1
AVSS2

2

EAPD

HP_JD
HP_OUTR
HP_OUTL

37

20
29

+MIC2_VREFO

30
28

+MIC1_VREFO_R

27

AC97_VREF

19

AC_JDREF

34
26
37

1 R505
2
20K_0402_1%
1
2
C501
2.2U_0603_16V6K

JUSB4

1
C502

1

C503

2

2

1
C500
2

14
14

USB20_N1
USB20_P1
+USB_VCCC

10U_0805_10V6K

MIC_JD

RESET#

0.1U_0402_16V7K

12

+USB_VCCD
1

2 @

1

2 @

1

2 @

1

0.1U_0402_16V7K
2 @

C504

0.1U_0402_16V7K

JUSB3

14
14

USB20_P0
USB20_N0

USB20_P0
USB20_N0

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ALC269Q-VB5-GR_QFN48_7X7
1

C505

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

3

ACES_88514-02401-071
CONN@

0.1U_0402_16V7K

2

C506

HDA_RST_AUDIO#

2

GND2
GND1

R505, C500 ~ C503 Close to Codec
4.7K_0402_5%
R506 @

1

1

JAU1
26
25

HDA_SDOUT_AUDIO 14

10U_0805_10V6K

11

YSDA0502C 3P C/A SOT-23

@

2

HDA_BITCLK_AUDIO 14

@

HDA_RST_AUDIO#

5
6

D23

@

MIC1
14 HDA_RST_AUDIO#

1

G1
G2

ACES_88266-04001
CONN@

2
0.22U_0603_16V7K
@

1

HDA_SYNC_AUDIO

SYNC

R494
@

1
2
3
4

EMI

SPK Out: 40mil

@

2

1

38

25

14
15

MIC2_L
MIC2_R

1

@
SPKOUT_L1
SPKOUT_L2

1
2
3
4

YSDA0502C 3P C/A SOT-23
HDA_BITCLK_AUDIO
0_0402_5%

C494

40
41

JSPK1
SPK_R1
SPK_R2
SPK_L1
SPK_L2

2
0.22U_0603_16V7K
@
1U_0603_10V6K

D22

HDA_SDOUT_AUDIO
2

SPK_OUT_L+
SPK_OUT_L-

PD#

2

AVDD2

46

39

2

LINE1_L
LINE1_R

4

R492 1

1
C478

+5VS

U26

40mA

MIC1_L
MIC1_R

1

C490

23
24

2 C495 4.7U_0603_6.3V6K MIC1_C 21
MIC2_C 22
2 C497 4.7U_0603_6.3V6K
AMIC1_L_C 16
2 C601 4.7U_0603_6.3V6K
AMIC1_R_C17
2 C602 4.7U_0603_6.3V6K
2 0_0402_5% DMIC_DATA_CODEC

R499 1

600mA

AVDD1

22.8mA

PVDD2

Close to pin1
C493
22P_0402_50V8J
@

2

SPK_L2

2

2

2

PVDD1

1

C492

9

2

1

C489

2

1

C491

L20
2
1
MBK1608800YZF 0603

40mil

C488

DVDD

EMI
DMIC_CLK

1

2 0_0603_5%

+5VS_PVDD +VDDA

60mil

20mil

DVDD_IO

1

R489 1

@ C483

1

0.1U_0402_16V7K

+3VS

2
0.22U_0603_16V7K
@
1U_0603_10V6K

SPKOUT_L2

SPKOUT_R2

+3VS_DVDD
10U_0603_6.3V6M

2

2

1
1 C476

22P_0402_50V8J

1
R493
2
1
0_0603_5%

2

SPK_L1

2 0_0603_5%

@ C477

10P_0402_50V8J

2

1
C485

10U_0805_10V6K

1

C487
22P_0402_50V8J
@

1
C481

R487 1

+3VS_DVDD_R

C484
DMIC_DATA

2

0.1U_0402_16V7K

2
1
0_0603_5%

+3VS_DVDD

0.1U_0402_16V7K

20mil

10U_0603_6.3V6M

R491

0.1U_0402_16V7K

1

1
C480

H

close to JSPK1

SPKOUT_L1

0.1U_0402_16V7K

2

0.1U_0402_16V7K

1
C479

10U_0805_10V6K

R488
2
1
0_0805_5%

+5VS

G

2

EMI
+5VS_PVDD

F

3

C

2

B

10P_0402_50V8J

A

@
0.1U_0402_16V7K
C508

Close to Codec pin11

R507 1

2 0_0402_5%

R508 1

2 0_0402_5%

R509 1

2 0_0402_5%

R510 1

2 0_0402_5%

C507

0.1U_0402_16V7K

For EMI (on MIC and Headphone AGND to connected with
DGND)

2

+MIC2_VREFO

R563
4.7K_0402_5%
AMIC1_L
R42
AMIC1_R

1

4

1

4

R566

2 AMIC1 1
1K_0402_5%
15mil
2

1

2 0_0402_5%

C603
100P_0402_50V8J

Issued Date

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R566 close to JCM1
For Mono Analog Microphone

E

F

Title

P25-HD CODEC ALC259
Size Document Number
Custom QML70 LA-8371P
Date:

Wednesday, October 19, 2011
G

Rev
0.2
Sheet

31
H

of

53

5

4

3

2

1

Card Reader RTS5137
(only SD/MMC/MS function)

+CARDPWR

12mil
SDWP
SDD1
SDD0

GPIO0
CLK_IN

4
5
6

3V3_IN
CARD_3V3
V18

7

NC

8
9
10
11
12

SP1
SP2
SP3
SP4
SP5

NC
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

EPAD
CARD@

@
1
R636
CLK_SD_48M

17
24

2
1
10_0402_5% @
@C614
C614

2
10P_0402_50V8J

CLK_SD_48M 13

23
22
21
20
19
18
16
15
14
13

SDD2
SDD3
SDCMD
SDCLK_R

SDCLK
1
2
0_0402_5% CARD@ R634
EMI
SDCD#

RTS5137-GR_QFN24_4X4

Card Reader Connector

+3VS

@

2

250mA

6 1

R773
100K_0402_5%

R768
100K_0402_5%

@
R781
100K_0402_5%
2

1

2

JCR1

C

+CARDPWR

SDCD#

R772
100K_0402_5%
SDWP

30mil

1

R635
100K_0402_5%

C617
0.1U_0402_16V4Z
2 CARD@

CARD@
C618
0.1U_0402_16V4Z

1

1

2

2

SDWP#

2

2N7002DW-7-F_SOT363-6
Q63A

CARD@
C622
0.1U_0402_16V4Z

SDCMD
SDCLK

SDD0
SDD1
SDD2
SDD3

5
3
6
4
7

VDD
CMD
CLK
VSS
VSS

8
9
1
2

DAT0
DAT1
DAT2
CD/DAT3

5

2N7002DW-7-F_SOT363-6
Q63B

4

1

1

2

SDCD
@

+CARDPWR

+3VS

2

30mil

+VREG
C623
1
C619
CARD@
C616
4.7U_0805_10V4Z
1U_0402_6.3V6K
1
CARD@ 2
CARD@
2
0.1U_0402_16V4Z
2

D

25

+3VS_CR

1

35mA (Latch up: 400mA)

3 1

+3VS_CR

R633 CARD@
30mil
2
1
0_0603_5%
@
2
1
12mil
C615
100P_0402_50V8J
U40
+RREF
R723 1
1 REFE
2
CARD@
6.2K_0603_1%
USB20_N4
2 DM
14
USB20_N4
USB20_P4
3 DP
14
USB20_P4

1

+3VS
D

SDWP#
SDCD

10
11

C

GND SW
GND SW

WP SW
CD SW

12
13

T-SOL_156-2000302604

Close to connector
CONN@

SDCLK
1
1
1
1
1
1
1
1

nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%
nonCARD@
2 0_0402_5%

SDCLK
SDCMD
SDCD#
SDWP
SDD0
SDD1
SDD2
SDD3

C612
R632
2
1
1
2 SDCLK
@
33_0402_5% @
22P_0402_50V8J

EMI
close U40
1

close U40

C621
@

+3VS

2

EMI

5P_0402_50V_C

B

R637
R639
R640
R641
R642
R643
R644
R645

15 FCH_SDCLK
15 FCH_SDCMD
15 FCH_SDCD#
15 FCH_SDWP
15 FCH_SDDATA0
15 FCH_SDDATA1
15 FCH_SDDATA2
15 FCH_SDDATA3

close JCR1
B

+CARDPWR
R638 nonCARD@
2
1
0_0603_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

P26-RTS5137 Media Card Controller
Size Document Number
Custom
QML70
Date:

Rev
0.11

LA-8371P

Wednesday, October 19, 2011

Sheet
1

32

of

53

A

B

C

D

E

+3VS
+1.5VS

WLAN/BT combo

@ 1 0_1206_5%

1

R583 2

2

2

0.1U_0402_16V4Z

@

2 0_0402_5%

BT_ON_FCH
R587 1
@
MINI1_CLKREQ# 0_0402_5%~D

14 MINI1_CLKREQ#

2

13 CLK_PCIE_MINI1#
13 CLK_PCIE_MINI1
PCI_RST#_R
CLK_PCI_DB_R
6 PCIE_DTX_C_CRX_N2
6 PCIE_DTX_C_CRX_P2

6 PCIE_CTX_C_DRX_N2
6 PCIE_CTX_C_DRX_P2
+3VS_WLAN

2

37
37

EC_TX
EC_RX

EC_TX
EC_RX

R594 1
R595 1
2 R596

@

2 0_0402_5%~D EC_TX_R
2 0_0402_5%~D EC_RX_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

WAKE#
RESERVED
RESERVED
CLKREQ#
GND
REFCLKREFCLK+
GND
RESERVED
RESERVED
GND
PERn0
PERp0
GND
GND
PETn0
PETp0
GND
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

C590

3.3V: 900mA
1.5V: 500mA

JMINI1
R586 1

C589
0.1U_0402_16V4Z

2

3.3V
GND
1.5V
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GND
RESERVED
PERST#
+3.3Vaux
GND
+1.5V
SMB_CLK
SMB_DATA
GND
USB_DUSB_D+
GND
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
GND
+3.3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND

54

1
R724

+VSBP

1

2

@

1

2

3VSWLAN_GATE
2
47K_0402_5%
1

+3VS_WLAN
+1.5VS_WLAN

0_0402_5%1
0_0402_5%1
PLT_RST#
R590 1
R591 1

26,29,39

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
2 R588
2@ R589 WL_OFF#_EC

2 0_0603_5%
@
2 0_0603_5%
0_0402_5%
FCH_SMCLK0_R R592 1
@
2
@
FCH_SMDAT0_R
1
2
R593 0_0402_5%

SUSP

SUSP

Q60
2
G

SSM3K7002FU_SC70-3

D
2

C592
0.1U_0603_25V7K

1

R585
100_0603_5%
3VS_WLAN_CHG

PCIE_WAKE#

14,30,37 FCH_PCIE_WAKE#

1

C588

1

1

0.1U_0402_16V4Z

2

4.7U_0805_10V4Z

C591
22U_0805_6.3V6

2

1

0.1U_0402_16V4Z

80mil

D

S
S


SUSP
2
G
Q32
SSM3K7002FU_SC70-3

3

2

+1.5VS_WLAN
1
C587

1
2
3

4

4.7U_0805_10V4Z

C586

1

2

1

C585

8
7
6
5

3

1

1

C584

+3VS_WLAN
U37
AO4478L 1N SO8

+3VS_WLAN
10U_0603_6.3V6M

2

+3VS_WLAN

1

+3VS

R584
0_1206_5%

WL_OFF#_FCH 15
WL_OFF#_EC 37
PLT_RST# 13,18,30

+3VS_WLAN
+3VALW
FCH_SCLK0 11,12,14
FCH_SDATA0 11,12,14

USB20_N3 14
USB20_P3 14
2

1

100K_0402_5%
15 BT_ON_FCH
37 BT_ON

BT_ON_FCH
BT_ON

R597 1
R598 1

2 1K_0402_0.5%
2@ 1K_0402_0.5%

53

GND
ACES_88915-5204
CONN@

5.2 mm High
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB_R

3

R599
R600
R601
R602
R603
R604
R605

1
1
1
1
1
1
1

2
2
2
2
2
2
2

0_0402_5% LPC_FRAME#
0_0402_5% LPC_AD3
0_0402_5% LPC_AD2
0_0402_5% LPC_AD1
0_0402_5% LPC_AD0
0_0402_5% PLT_RST#
CLK_PCI_DB
0_0402_5%

LPC_FRAME# 13,37
LPC_AD3 13,37
LPC_AD2 13,37
LPC_AD1 13,37
LPC_AD0 13,37

3

CLK_PCI_DB 13

C593
R606
2
1
1
2CLK_PCI_DB_R
@
33_0402_5% @
22P_0402_50V8J

Reserve for EMI please close to JMINI1

4

4

Compal Secret Data

Security Classification
Issued Date

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
WLAN/ WWAN/ m-SATA

Size Document Number
Custom

Rev
0.2

QML70 LA-8371P

Date:

Wednesday, October 19, 2011

Sheet
E

33

of

53

B

C

D

+3VS

HDD-SATA Redriver
15 SATA_FTX_DRX_P0
15 SATA_FTX_DRX_N0

@

2 4.7K_0402_5%

1
1

2 C432
2 C431

SATA_FRX_DTX_P0_R
SATA_FRX_DTX_N0_R

+3VS

SATA0_B_PRE1
SATA0_A_PRE1

PIN7 & PIN18 have internal PD
2
R667
0_0402_5%

1
15 SATA_FTX_DRX_P1
15 SATA_FTX_DRX_N1

B_OUTp
B_OUTn
B_PRE1
A_PRE1

NC
REXT

10
20

A_PRE0
B_PRE0
A_OUTp
A_OUTn

TEST
GND
GND
EPAD

B_INp
B_INn

@

2 4.7K_0402_5%

7

EN

VDD
VDD

SATA_FTX_DRX_P10.01U_0402_16V7K
SATA_FTX_DRX_N10.01U_0402_16V7K

1
1

2 C434
2 C437

SATA_FTX_DRX_P1_R
SATA_FTX_DRX_N1_R

1
2

A_INp
A_INn

SATA_FRX_DTX_P10.01U_0402_16V7K
SATA_FRX_DTX_N10.01U_0402_16V7K

1
1

2 C436
2 C435

SATA_FRX_DTX_P1_R
SATA_FRX_DTX_N1_R

5
4

B_OUTp
B_OUTn

+3VS

SATA1_B_PRE1
SATA1_A_PRE1

PIN7 & PIN18 have internal PD
R738 1
@
4.7K_0402_5%

2

2

9
8
15
14

SATA_FTX_C_DRX_P0_R
SATA_FTX_C_DRX_N0_R

11
12

SATA_FRX_C_DTX_P0_R
SATA_FRX_C_DTX_N0_R

R670
0_0402_5%

1

2

Place caps.
near U42

1

2

1

2

1

2

1

2

1

+3VS

NC
REXT

17
19

B_PRE1
A_PRE1

18
3
13
21

TEST
GND
GND
EPAD

SATA HDD BTB Conn.

6
16
@ R671
1
2
4.99K_0402_1%
SATA1_A_PRE0
SATA1_B_PRE0

10
20

A_PRE0
B_PRE0

9
8

A_OUTp
A_OUTn

15
14

SATA_FTX_C_DRX_P1_R
SATA_FTX_C_DRX_N1_R

B_INp
B_INn

11
12

SATA_FRX_C_DTX_P1_R
SATA_FRX_C_DTX_N1_R

JHDD1
SATA_FTX_DRX_P00_0402_5%
SATA_FTX_DRX_N00_0402_5%

1 @
1 @

2 R699
2 R700

SATA_FTX_C_DRX_P0_R
SATA_FTX_C_DRX_N0_R

SATA_FRX_DTX_N00_0402_5%
SATA_FRX_DTX_P0 0_0402_5%

1 @
1 @

2 R701
2 R702

SATA_FRX_C_DTX_N0_R
SATA_FRX_C_DTX_P0_R

SATA_FTX_DRX_P10_0402_5%
SATA_FTX_DRX_N10_0402_5%

1 @
1 @

2 R703
2 R704

SATA_FTX_C_DRX_P1_R
SATA_FTX_C_DRX_N1_R

SATA_FRX_DTX_N10_0402_5%
SATA_FRX_DTX_P1 0_0402_5%

1 @
1 @

2 R705
2 R706

SATA_FRX_C_DTX_N1_R
SATA_FRX_C_DTX_P1_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

PS8520BTQFN20GTR2_TQFN20_4X4

1

@

Place caps.
near U41

+3VS
@ R668
1
2
4.99K_0402_1%
SATA0_A_PRE0
SATA0_B_PRE0

81mA

U42
R669 1

15 SATA_FRX_DTX_P1
15 SATA_FRX_DTX_N1

5
4
17
19

6
16

PS8520BTQFN20GTR2_TQFN20_4X4


+3VS

HDD-SATA Redriver

A_INp
A_INn

18
3
13
21

2

@

H

C641
0.01U_0402_16V7K

SATA_FRX_DTX_P00.01U_0402_16V7K
SATA_FRX_DTX_N00.01U_0402_16V7K

1
2

VDD
VDD

C642
0.1U_0402_16V7K

SATA_FTX_DRX_P0_R
SATA_FTX_DRX_N0_R

EN

C643
1U_0603_10V6K

2 C430
2 C433

7

C638
0.01U_0402_16V7K

1
1

R736 1
@
4.7K_0402_5%

G

81mA

U41
R459 1

SATA_FTX_DRX_P00.01U_0402_16V7K
SATA_FTX_DRX_N00.01U_0402_16V7K

1

F

C639
0.1U_0402_16V7K

15 SATA_FRX_DTX_P0
15 SATA_FRX_DTX_N0

E

+3VS

Co-lay with redriver
Add EQ pin for PS8520BTQFN20GTR2 FOR SATA1

SATA0_B_PRE0 1@ R681

2 4.7K_0402_5%

SATA1_B_PRE1 1@ R688

2 4.7K_0402_5%

SATA1_A_PRE1 1@ R685

2 4.7K_0402_5%

SATA1_A_PRE0 1@ R683

2 4.7K_0402_5%

SATA1_B_PRE0 1@ R689

2 4.7K_0402_5%

SI3456DDV-T1-GE3_TSOP6

C439
1U_0402_6.3V6K

15 SATA_FRX_DTX_P2
15 SATA_FRX_DTX_N2

SATA_FRX_DTX_P20.01U_0402_16V7K
SATA_FRX_DTX_N20.01U_0402_16V7K

1
1

2 C438
2 C637

SATA_FTX_DRX_P2_R
SATA_FTX_DRX_N2_R

1
2

1
1

2 C636
2 C635

SATA_FRX_DTX_P2_R
SATA_FRX_DTX_N2_R

5
4

+3VS

SATA2_B_PRE1
SATA2_A_PRE1

PIN7 & PIN18 have internal PD
2

R673
0_0402_5%

EN

VDD
VDD

A_INp
A_INn

NC
REXT

B_OUTp
B_OUTn

A_PRE0
B_PRE0

B_PRE1
A_PRE1

A_OUTp
A_OUTn

TEST
GND
GND
EPAD

B_INp
B_INn

6
16
10
20

15
@R674
@
R674

9
8

1
2
4.99K_0402_1%
SATA2_A_PRE0
SATA2_B_PRE0

15
14

SATA_FTX_C_DRX_P2_R
SATA_FTX_C_DRX_N2_R

11
12

SATA_FRX_C_DTX_P2_R
SATA_FRX_C_DTX_N2_R

+5VS_ODD

2

Placea caps. near ODD CONN.

1

ODD_EN
D
Q25
SSM3K7002FU_SC70-3

2
G

ODD_EN#

0_1206_5%

0.1U_0402_16V4Z
C445

R462

S

1
C444
2

1000P_0402_50V7K

1

2

1

C447

2

C448

2

1U_0402_6.3V4Z
3

SATA ODD Conn.

PS8520BTQFN20GTR2_TQFN20_4X4

10U_0805_10V4Z
1

C446

JODD1

1

@

17
19
18
3
13
21

2

R740 1
@
4.7K_0402_5%

7

1600mA

2

1

15 SATA_FTX_DRX_P2
15 SATA_FTX_DRX_N2

SATA_FTX_DRX_P20.01U_0402_16V7K
SATA_FTX_DRX_N20.01U_0402_16V7K

2 4.7K_0402_5%

3

3

@

1

1

2

+3VS

81mA
U43

R672 1

+5VS_ODD_R

+5VS_ODD

2

+3VS

R460
4

R461
330K_0402_5%

1

2

0.1U_0402_25V6

1
C552

6
5
2
1

1

2

+VSBP

ODD-SATA Redriver

Q24

+5VS

0.1U_0402_25V6

2 4.7K_0402_5%

SATA1_B_PRE11@ R684
2
0_0402_5%
SATA1_A_PRE11@ R687
2
0_0402_5%
SATA1_A_PRE01@ R690
2
0_0402_5%
SATA1_B_PRE01@ R686
2
0_0402_5%

1.5M_0402_5%

SATA0_A_PRE0 1@ R675

2

+3VS

D

2 4.7K_0402_5%

+3VS

S

2 4.7K_0402_5%

SATA0_A_PRE1 1@ R677

+5VS

G

SATA0_B_PRE1 1@ R680

2000mA

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

ACES_88018-304G
CONN@

+3VS

SATA0_B_PRE11@ R676
2
0_0402_5%
SATA0_A_PRE11@ R679
2
0_0402_5%
SATA0_A_PRE01@ R682
2
0_0402_5%
SATA0_B_PRE01@ R678
2
0_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

31
32
33
34
35
36

Add EQ pin for PS8520BTQFN20GTR2 FOR SATA0

3

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

GND
GND
GND
GND
GND
GND

A

SATA_FTX_DRX_P2
SATA_FTX_DRX_N2

0_0402_5%
0_0402_5%

1 @
1 @

2 R707
2 R708

SATA_FTX_C_DRX_P2_R
SATA_FTX_C_DRX_N2_R

2 R709
2 R710

SATA_FRX_C_DTX_P2_R
SATA_FRX_C_DTX_N2_R

SATA_FTX_C_DRX_P2_R
SATA_FTX_C_DRX_N2_R

C440 1
C441 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FTX_DRX_P2_C
SATA_FTX_DRX_N2_C

SATA_FRX_C_DTX_N2_R
SATA_FRX_C_DTX_P2_R

C442 1
C443 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FRX_DTX_N2_C
SATA_FRX_DTX_P2_C

14 ODD_DETECT#

1
R463
+5VS_ODD
ODD_DA#
1
R464

2 4.7K_0402_5%

SATA2_B_PRE0 1@ R697

2 4.7K_0402_5%

B

1

2

C

1

2

1

2

R557

1

2

ODD_DETECT#_R
0_0402_5%
ODD_DA#_R
0_0402_5%

FCH_ODD_DA# 14

E

DP
V5
V5
MD
GND
GND

4

Compal Electronics, Inc.

Compal Secret Data
2011/07/29

6
5
4
3
2
1

GND
A+
AGND
BB+
GND

SUYIN_127382FR013G109ZR_RV
CONN@

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

2

80mils

2N7002K-C_SOT23-3
2
@
0_0402_5%

Security Classification
Issued Date

FCH_ODD_DA#

D

2 4.7K_0402_5%

SATA2_A_PRE0 1@ R691

37 ODD_DA#
3
Q31
1

C644
0.01U_0402_16V7K

2 4.7K_0402_5%

SATA2_A_PRE1 1@ R693

ODD_DA#

C645
0.1U_0402_16V7K

A

SATA2_B_PRE1 1@ R696

C646
1U_0603_10V6K

SATA2_B_PRE11@ R692
2
0_0402_5%
SATA2_A_PRE11@ R695
2
0_0402_5%
SATA2_A_PRE01@ R698
2
0_0402_5%
SATA2_B_PRE01@ R694
2
0_0402_5%

Place caps.
near U43

S

+3VS

Add EQ pin for PS8520BTQFN20GTR2 FOR SATA2

G

+3VS
4

R60
10K_0402_5%

2

1 @
1 @

Co-lay with redriver

2

0_0402_5%
0_0402_5%

1

+3VS
SATA_FRX_DTX_P2
SATA_FRX_DTX_N2

13
12
11
10
9
8
7

F

Title

P28-HDD & ODD CONN
Size
B

Document Number

Rev
0.11

QML70 LA-8371P

Date:

Wednesday, October 19, 2011
G

Sheet

34
H

of

53

1

2

3

@ 1
R511
+5VALW

1

C510

2A

+USB_VCCA

14 USB3_RX0_N

2.2U_0603_6.3V4Z

2

1
2
3
4

2
10.1U_0402_16V4Z
USBAI_PEN#
37 USBAI_PEN#

GND
IN
IN
EN#

2

1

USB3_RX0_P_R

USB3_RX0_N

3

4

USB3_RX0_N_R

AI CHARGER
U28

DLP11TB800UL2L_4P

8
7
6
5

OUT
OUT
OUT
OC#

USB3_RX0_P

1
0_0402_5%

2
R515

@ 1
R514
@ 1
R517

USB_OC0# 14

37

2
0_0402_5%
2
0_0402_5%

2

L23
C512
@ 1000P_0402_50V7K

2

14

USB3_TX0_P

USB3_TX0_P

14

USB3_TX0_N

USB3_TX0_N

C648
C649

2

USB3_TX0_P_C
1
0.1U_0402_10V7K

2

2

USB3_TX0_N_C
1
0.1U_0402_10V7K

3

8
7
6
5

1

USB3_TX0_P_R

4

USB3_TX0_N_R

R516
100K_0402_5%
AI@
C511
0.1U_0402_16V7K
AI@

140uA

2

CB
CEN
TDM
DM
TDP
DP
VDD
SELCDP
Thermal Pad

@

SLG55584AVTR_TDFN8_2X2
AI@

1

CEN# R537 1
USB20_N10_CON

1
2
3
4
9

R581
4.7K_0402_5%
AI@

2
0_0402_5%

2

@ 1
R519

SELCDP

14

USB20_N10

USB20_N10

R540 2 nonAI@ 1 0_0402_5%

USB20_N10_CON

14

USB20_P10

USB20_P10

R552 2 nonAI@ 1 0_0402_5%

USB20_P10_CON

CB

R580
4.7K_0402_5%

2

@

L24
14 USB3_RX1_P

+5VALW

U29
C515

@

1

C516

14 USB3_RX1_N

2A

USB3_RX1_P
USB3_RX1_N

2
3

+USB_VCCB

37

A

1

2
0_0402_5%

AI_CEN#

+5VALW

DLP11TB800UL2L_4P
@ 1
R518

2 0_0402_5%

USB20_P10_CON
SELCDP

1

1

Low Active

2 0_0402_5%
USB20_N10
USB20_P10

+5VALW

AP2301MPG-13 MSOP 8P

A

R512 1 AI@

USBAI_EN

1

@

5

L22
14 USB3_RX0_P
U27

C509

4

2
0_0402_5%

1

USB3_RX1_P_R

4

USB3_RX1_N_R

SELCDP

Function

0

X

DCP autodetect charger mode

1

0

S0 charging with SDP only

1

1

S0 charging with SDP or CDP

charger port: left side & near user

DLP11TB800UL2L_4P

2.2U_0603_6.3V4Z

2

1
2
3
4

2
10.1U_0402_16V4Z
USBSW_EN#
37 USBSW_EN#

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
OC#

1
0_0402_5%

2
R523

1

Low Active

C517
@ 1000P_0402_50V7K

2
0_0402_5%

@ 1
R522

2
0_0402_5%

+USB_VCCA

2 R521
1 0_0402_5%
@
L27
USB20_N10_CON

1

1

2

2

4

3

3

USB20_N10_C

USB3_TX1_P

USB3_TX1_P
C650

2

USB3_TX1_P_C
1
0.1U_0402_10V7K

2

1

USB3_TX1_P_R

USB20_P10_CON

4

USB20_P10_C

1
C513
470P_0402_50V7K

L25
14

2

2

2

USB3_TX1_N

USB3_TX1_N
C651

2

USB3_TX1_N_C
1
0.1U_0402_10V7K

3

4

C514
47U_0805_6.3V

USB3_RX0_N_R
USB3_RX0_P_R
USB3_TX0_N_R
USB3_TX0_P_R

USB3_TX1_N_R

2 R525
1 0_0402_5%
@

DLP11TB800UL2L_4P
@ 1
R524

1
2
3
4
5
6
7
8
9

USB20_N10_C
USB20_P10_C

1

WCM-2012HS-900T_4P
14

JUSB1

W=80mils

USB_OC2# 14

AP2301MPG-13 MSOP 8P

B

@ 1
R520

10
11
12
13

2
0_0402_5%

VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND
STDA_SSTXSTDA_SSTX+

B

GND
GND
GND
GND
SANTA_373280-1
CONN@

2 R526
1 0_0402_5%
@
+5VALW

U30
C518

@

1

C519

+USB_VCCC

2.2U_0603_6.3V4Z

2

10.1U_0402_16V4Z

2

2A

1
2
3
4

USBSW_EN#

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
OC#

0_0402_5%
1
2
R527

USB3_RX0_N_R

D27
1 1

10 9

USB3_RX0_N_R

USB3_RX0_P_R

2 2

9 8

USB3_RX0_P_R

USB3_TX0_N_R

4 4

7 7

USB3_TX0_N_R

USB3_TX0_P_R

5 5

6 6

USB3_TX0_P_R

WCM-2012HS-900T_4P
14

USB20_N11

USB20_N11

4

4

3

3

USB20_N11_C

14

USB20_P11

USB20_P11

1

1
L26

2

2

USB20_P11_C

2 R528
1 0_0402_5%
@

3 3

USB_OC1# 14

+USB_VCCB

C520
470P_0402_50V7K

8

1

2

2

USB20_N11_C
USB20_P11_C
C521
47U_0805_6.3V

AP2301MPG-13 MSOP 8P

1

Low Active

JUSB2

W=80mils
1

USB3_RX1_N_R
USB3_RX1_P_R
USB3_TX1_N_R
USB3_TX1_P_R

AZ1045-04F DFN2510P10E
C522
@ 1000P_0402_50V7K

2
C

U31

2A

USB3_TX1_P_R

+USB_VCCA

USB20_N10_C

USB20_N11_C

USB20_P10_C

USB20_P11_C

10
11
12
13

GND
GND
GND
GND
SANTA_373280-1
CONN@

C

+USB_VCCB

D26

3 3

+USB_VCCD

VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND
STDA_SSTXSTDA_SSTX+

2

USB3_TX1_N_R

6 6

3

7 7

5 5

2

4 4

USB3_TX1_P_R

D32

1

USB_OC1#

1

1

AP2301MPG-13 MSOP 8P

Low Active

D28
AZC199-02SPR7G_SOT23-3

C525
@ 1000P_0402_50V7K

PJSOT24CH 3P C/A SOT-23

@

1

@

1

2

0_0402_5%
2
R529

3

AZ1045-04F DFN2510P10E

2

8
7
6
5

3

OUT
OUT
OUT
OC#

PJSOT24CH 3P C/A SOT-23

D39
AZC199-02SPR7G_SOT23-3

1

USBSW_EN#

GND
IN
IN
EN#

1

10.1U_0402_16V4Z

1
2
3
4

2

8

2.2U_0603_6.3V4Z

2

2

2

USB3_RX1_P_R

USB3_TX1_N_R

1

C524

1

USB3_RX1_N_R

9 8

3

@

10 9

2 2

3

C523

D29
1 1

USB3_RX1_P_R

3

+5VALW

USB3_RX1_N_R

1
2
3
4
5
6
7
8
9

2

D

D

Compal Secret Data

Security Classification

Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal
Electronics, Inc.
Title
USB2/USB3/AUDIO
Size
Document Number
Custom

Rev
0.11

QML70 LA-8371P

Date:

Wednesday, October 19, 2011
5

Sheet

35

of

53

2

H16

2

2

1

H17

1

H_3P0

H_3P0

@

@

@

@

+5VALW

4P3

H13
H_3P0

H_3P0

@

@

H15
H_3P0

H_3P1

1

H_3P0

1

1

1

1

@

H14

@

H19
H_4P3

@

1

H_3P1

@

H24
H_3P0

H_3P0

@

@

H20

H21

@

@

H_4P3

H_4P3

H_4P3

@

@

H23

3

2

1

H12

H_3P0

ON/OFFBTN#

2

@

@

H11

H_3P0

300_0402_5%

PW R_ON_LED#
Q30
2N7002_SOT23-3
930@

H_3P0

1

1

@

H_3P0

1

PW R_ON_LED#

H_3P0

1

H10

1

1

S

2
G

R532
10K_0402_5%
930@

3

EC_ON

EC_ON

H8

1

@

H9

H_3P0

H18

37,42

H25

R722

19-213A-T1D-CP2Q2HY-3T_W HITE
D

H6

1

@

1

5

LED7

H_3P0

1

40

DAN202UT106_SC70-3
930@

37,38 PW R_ON_LED#

H5

1

51_ON#

H3

1

51_ON#

3

H2

3P0

37

1

3

H1
ON/OFF

1

1

4

2

ON/OFFBTN#

Screw Hole

R531
9012@
100K_0402_5%

1

D30

1

E

1

NTC010-BB1G-C100C
SW 1

2

R530
930@
100K_0402_5%

2 0_0402_5%

1

1

R513 1
9012@

+3VLP

1

ON/OFF switch

+3VALW

D

1

Power Button

C

2

B

2

A

2

1

3P3
PJSOT24CH_SOT23-3
D31

H_3P3

1

@

@

H22

1

2P9
H_2P9

@

FD1

Fan Control Circuit

FD2

FD3

FD4

FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

FIDUCIAL_C40M80

@

1

@

1

@

1

3

1

3

FIDUCIAL_C40M80

+5VS
C526
1
2.2U_0603_6.3V4Z

1

2

+3VS

U32

1

R533
10K_0402_5%

37

FAN_SPEED

FAN_SPEED

2

8
7
6
5

GND
GND
GND
GND

EN
VIN
VOUT
VSET

1
2
3
4

2

JFAN1
+5VS_FAN

1

2

2
37

FAN_SPEED

1

APL5607KI-TRG_SO8
C529
1000P_0402_50V7K

C527
1000P_0402_50V7K~D

C528
10U_0603_6.3V6M

1
2
3
4
5

1
2
3
GND
GND
ACES_85204-0300N
CONN@

FAN_SET

place as close as EC
4

4

Compal Secret Data

Security Classification
2011/07/29

Issued Date

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
PWRBTN/ FAN / Screws

Size
Document Number
Custom

Rev
0.11

QML70 LA-8371P

Date:

W ednesday, October 19, 2011

Sheet
E

36

of

53

4

3

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C799
C800
C801
C802

2
2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

L36
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW_EC
2

C803

2

1
1
1000P_0402_50V7K

C580

2

R399 2

GATE20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

EC_RST#
EC_SCI#

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

13,16 LPC_CLK0_EC
+3VALW

R400 2
C807

13

1 47K_0402_5%
2

A_RST#

14
EC_SCI#
13 PM_CLKRUNEC#

0.1U_0402_16V4Z

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

+3VALW
1
R403
1
R406
1
R408
1
R559
1
R609
1
R610

C

@
@
@
@

2 EC_SMB_CK1_R
2.2K_0402_5%
2 EC_SMB_DA1_R
2.2K_0402_5%
2 FLASH_EN
10K_0402_5%
2 S5_CORE_EN
10K_0402_5%
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%

+3VS

1
R411
1
R413
1
R417

EC_SCI#
10K_0402_5%
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%
2

40,41
40,41
8,19,27
8,19,27

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1 1 R421
EC_SMB_DA1 1 R422
1 R423
2 0_0402_5%
1 R424
2 0_0402_5%

EC_SMB_CK1_R
2 0_0402_5%
EC_SMB_DA1_R
2 0_0402_5%
EC_SMB_CK2_R
EC_SMB_DA2_R

+3VALW

38

0.1U_0402_16V4Z
C581
ECAGND

2
21
23
26
27

USBSW_EN#
FCH_SPI_WP# 15
2
C805

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BATT_TEMPA

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

USBAI_PEN#
FAN_SET
ODD_DA#
AC_PRESENT_OK

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE_R
USBAI_EN
BT_ON
EAPD
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

GPU_CTF
EN_WOL
VLDT_EN
R567 2
1
0_0402_5% 9012@

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

AD Input

USBSW_EN#
1
10K_0402_5%
USBAI_PEN#
1
10K_0402_5%

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

35

2
2

R770
R771

ECAGND
1
100P_0402_50V8J
BATT_TEMPA 40

EC_THERMTRIP#
ADP_I
40,41

ADP_I
AD_BID0
ENBKL
AI_CEN#

ENBKL

8

10
AI_CEN#

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

USBAI_PEN# 35
FAN_SET 36
ODD_DA# 34
AC_PRESENT_OK

35

TP_CLK
4.7K_0402_5%

14

TP_DATA
4.7K_0402_5%

PS2 Interface

SPI Device Interface
SPI Flash ROM

GPIO
SM Bus

EC_PME#

FCH_PWROK

9012@
1 R432
0_0402_5%

33
EC_TX
33
EC_RX
2
36,38 PWR_ON_LED#
38 NUM_LED#

PWR_ON_LED#
NUM_LED#

EC_CRY1
EC_CRY2

13,16 RTC_CLK
2 R435
1
C815

122
123

R414
R416
R418

R404 2

1 0_0402_5%
USBAI_EN
BT_ON
EAPD
TP_CLK
TP_DATA

EC_MUTE#

35
33
31
38
38

2
2
2

R419 2
PX_EN
SPOK
BATT_CHG_LED#
CAPS_LED#
PE_GPIO1
BATT_CHG_LOW_LED#
SYSON
VR_ON
VGATE

1 0_0402_5%

2

FCH_1.1PWR_EN
1
R749
EC_MUTE#
1
R405

R428
2
1
0_0402_5%
9012@

TL_BKOFF#

2

20P_0402_50V8

A

EC_RSMRST#
100
EC_LID_OUT#
101
102 0_0402_5% 2 R572
103
104
BKOFF#
105
PBTN_OUT#
106
WL_BT_LED#
107
VGA_ON
108
110
112
114
115
116
117
118

ACIN_D
EC_ON
ON/OFF
LID_SW_IN#
SUSP#
WL_OFF#_EC
FCH_1.1PWR_EN

V18R

124

+V18R
1

2

KB9012QF A3 LQFP 128P

20mil

1 9012@

ACIN

Y3

@

5

2

27,28

14

@
D42
RB751V_SOD323
2
1

FCH_POK
+3VS

2

R761
10K_0402_5%
@

1

2

R762
0_0402_5%

BKOFF# 28
PBTN_OUT# 14
WL_BT_LED# 38
VGA_ON 20

EC_ON
36,42
ON/OFF 36
LID_SW_IN# 38
SUSP#
39,44
WL_OFF#_EC 33
FCH_1.1PWR_EN
45

9012@ 2 R429
R430

10_0402_5%

1 930@
0_0402_5%

2

2

1

FCH_PWROK

R760
0_0402_5%

1

B

MAINPWON

42

FCH_POK_EC

C811
2
1
@
22P_0402_50V8J

SPI ROM 128KB

R415

+3VALW
20mils

1
2SPI_CLK
33_0402_5% @

1

Reserve for EMI please close to U74

930@

15mA

C814
4.7U_0805_10V4Z

C813
0.1U_0402_16V4Z

2

U74
FRD#
2 930@
0_0402_5%

1
R436

FSEL#
SPI_SO

1
2
3
4

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_CLK
FWR#

A

MX25L1005AMC-12G_SO8
SA00002C100
930@

@
2EC_CRY2

C595
15P_0402_50V8J

4

9012@
FCH_POK_EC

EC_RSMRST#
EC_LID_OUT#

L37

2

Compal Secret Data

Security Classification

32.768KHZ_12.5P_1TJF125DP1A000D
1
@

100P_0402_50V8J
1

19,41

ECAGND 2
1
FBMA-L11-160808-800LMT_0603
EC_CRY1 1
1

C

10K_0402_5%

38

14
14
Turbo_V
40
H_PROCHOT#_EC 8,47

2
100K_0402_5%
2
10K_0402_5%

C810
2

ACIN

FCH_PWROK
1
R412

@

+3VLP

2

ACIN_D

TL_BKOFF#

PX_EN
20,21
SPOK
40,42
BATT_CHG_LED# 38
CAPS_LED# 38
PE_GPIO1 13,14,20
BATT_CHG_LOW_LED#
SYSON
39,44
VR_ON
47
VGATE
14,47

1
R401
1
R402

1 @
2
R407 100K_0402_5%

R409 1 930@
200K_0402_5%

FRD#
FWR#
SPI_CLK
FSEL#

33_0402_5%
33_0402_5%
33_0402_5%

2

EC_MUTE# 31

+3VALW_EC

GPU_CTF 19
EN_WOL 30
VLDT_EN 39,46
NTC_V
40

1 930@
1 930@
1 930@

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0

1 100K_0402_5%
2

GPI

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

AGND

1 @
2
R4310_0402_5%

GPO

69

FCH_PCIE_WAKE#

S5_CORE_EN
EC_INVT_PWM
FAN_SPEED
EC_PME#
EC_TX
EC_RX

0.1U_0402_16V4Z

+5VS

DA Output

GND
GND
GND
GND
GND

14,30,33

13 S5_CORE_EN
28 EC_INVT_PWM
36 FAN_SPEED

C804

1

PWM Output

11
24
35
94
113

1
2

R427
10K_0402_5%
@

PM_SLP_S3#_R
PM_SLP_S5#_R
EC_SMI#
FCH_3.3PWR_EN
FLASH_EN

D

1

2
USBSW_EN#
FCH_SPI_WP#

+3VALW
1 R425
2 0_0402_5%
1 R426
2 0_0402_5%
14
EC_SMI#
39 FCH_3.3PWR_EN
15
FLASH_EN

AD_BID0
R398
8.2K_0402_5%

Rb

+3VALW

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

B

14 PM_SLP_S3#
14 PM_SLP_S5#

R396
100K_0402_5%

Ra
+3VLP

1
9012@

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
C806
@ 22P_0402_50V8J
2
1

Board ID

15,38

KSO[0..17]

67

20mA
U72

9
22
33
96
111
125

R397 2
0_0402_5%

14
GATE20
14 KB_RST#
13
SERIRQ
13,33 LPC_FRAME#
13,33
LPC_AD3
13,33
LPC_AD2
1 @ 33_0402_5% 13,33
LPC_AD1
13,33
LPC_AD0

KSI[0..7]

KSO[0..17]
1

R395
0_0402_5%
930@

1000P_0402_50V7K

D

KSI[0..7]

2

2

1

1
R394
0_0805_5%

1

2

+3VALW

2

1

5

Issued Date

C596
15P_0402_50V8J

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
EC ENE-KB930/Co-lay 9012

Size Document Number
Custom

Rev
0.11

QML70 LA-8371P

Date:

Wednesday, October 19, 2011
1

Sheet

37

of

53

KSI2
KSI3
KSI4
KSI0
KSI5
KSI6

KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9

+5VS

C594
1

JTP1
KSI[0..7]

KSI[0..7]

KSO[0..17]

GND
GND

15,37

KSO[0..17] 37

6
5
4
3
2
1

JKB1

KSO15
KSO14
KSO12
KSO10
KSO11
KSO6
KSO8
KSO4
KSO2
KSO5
KSO13
KSI0
KSI3
KSO1
KSI2
KSI4
KSO3
KSI5
KSI6
KSO9
KSI7
KSI1
KSO0
KSO7

26
25

GND2
GND1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

8
7
6
5
4
3
2
1

2

TP_CLK

0.1U_0402_16V4Z

LEFT_BTN#

TP_DATA

LEFT_BTN#
RIGHT_BTN#

RIGHT_BTN#

1

2

ACES_88514-00601-071
CONN@

1

@

2

D33
PJDLC05C_SOT23-3

TP_CLK 37
TP_DATA 37

D34
PJDLC05C_SOT23-3

@

C571
100P_0402_50V8J

KSI1

INT_KBD Conn.

2

KSI7

Touch/B Connector

3

KSO15

1

KSO12

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

C570
100P_0402_50V8J

1
C553
1
C554
@
1
C555
@
1
C556
@
1
C557
@
1
C558
@
1
C559
@
1
C560
@
1
C561
@
1
C562
@
1
C563
@
1
C565
@
1
C566
@
1
C567
@
1
C568
@
1
C569
@
1
C572
@
1
C573
@
1
C574
@
1
C575
@
1
C576
@
1
C577
@
1
C578
@
1
C579

2

@

3

@

KSO11

1

KSO10

DTSM-61N-S-V-T-R(756)_4P
LEFT_BTN#

DTSM-61N-S-V-T-R(756)_4P

1

3

2

4

RIGHT_BTN#

1

3

2

SW3

4
SW4

Lid Switch
(Hall Effect Switch)
+3VALW

1

ACES_88514-02401-071
CONN@
2
U36

LED1
3
1

OUTPUT
2
200_0402_5%

1
R714

+3VALW
D35

HT-121UYG_YELLOW-GREEN

Green
37 BATT_CHG_LED#

2
100_0402_5%

1 2
R716

Amber

2
300_0402_5%

BATT_LOW_LED#

1 3
R715

G

YG

2

3
1

2
200_0402_5%

APX9131AAI-TRG SOT-23

2

C583
10P_0402_50V8J
@

1
3

+3VALW
YSDA0502C 3P C/A SOT-23

HT-210UD/UYG_AMB/GRN

D36

LED3

Green
37 WL_BT_LED#

@

LID_SW_IN# 37
1

2

PWR_ON_LED#
1

37 BATT_CHG_LOW_LED#

SATA_LED#

LED2

BATT_CHG_LED#

3

GND

36,37 PWR_ON_LED#

1

YG

2

2

1

Green

R578
47K_0402_5%

2

C582
0.1U_0402_16V4Z

2
10K_0402_5%

G

LED

1
R713

VDD

+5VALW

1
R717

BATT_CHG_LOW_LED#

2

BATT_CHG_LED#

3

@
1

YSDA0502C 3P C/A SOT-23
D37
@

+3VS

HT-121UYG_YELLOW-GREEN

WL_BT_LED#

2

CAPS_LED#

3

1

LED4
2

YG

SATA_LED#

G

Green
15

3
1

YSDA0502C 3P C/A SOT-23
2
200_0402_5%

1
R719

+3VS

D38
NUM_LED#

@

2
1

HT-121UYG_YELLOW-GREEN

3

LED5
2

YG

NUM_LED#

G

Green
37

3
1

YSDA0502C 3P C/A SOT-23
2
200_0402_5%

1
R720

+3VS

1
R721

+3VS

ESD

HT-121UYG_YELLOW-GREEN
LED6
2

YG

CAPS_LED#

G

Green
37

3
1

2
200_0402_5%

HT-121UYG_YELLOW-GREEN

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
KB/EC ROM/TP/FUN/LED

Size
B
Date:

Document Number

Rev
0.2

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet

38

of

53

D

1

2

S

2

SSM3K7002FU_SC70-3

1

R732
100K_0402_5%

1

D

S

+5VALW
2
R733
100K_0402_5%

SUSP#
1

S
Q61
SSM3K7002FU_SC70-3

1

Q75
2
G

D

S

2

2

R734
10K_0402_5%

Q76
2
G

SUSP

3

S

SSM3K7002FU_SC70-3

1

Q77
SUSP

37,44

SUSP

1

1
D

SUSP

3

1
2
2

26,29,33

D

2
G

R748
100K_0402_5%

R735
470_0603_5%
1 1

4

2

1

C829

1U_0402_6.3V4Z

1
C828

C827

2

10U_0603_6.3V6M

1

37 FCH_3.3PWR_EN

1
2
3

3VS_GATE
1
47K_0402_5%

2
R767

+VSBP

C826

2

0.1U_0402_16V7K

10U_0603_6.3V6M

2

1

8
7
6
5

+3VS

2

FCH_3.3PWR_EN#

+3VALW U71
SI4178DY-T1-GE3_SO8

1

+5VALW
C825
0.1U_0603_25V7K
R718
100K_0402_5%

+3VALW TO +3VS (3A)

SSM3K7002FU_SC70-3

3

SSM3K7002FU_SC70-3

Q72
2
G

SYSON

3

R729
10K_0402_5%

37,44

1

SSM3K7002FU_SC70-3

1

VLDT_EN#

SSM3K7002FU_SC70-3

3

S

Q74
2
G

1

Q71
2
G

SYSON#

3

VLDT_EN#

S

37,46 VLDT_EN
1

D

1.1VS_GATE

2
47K_0402_5%

D

R725
100K_0402_5%

2

C824
0.1U_0603_25V7K

1
R731

1

+VSBP

Q69
2
G

3

2
1 1

2

3

2
3

4

1

2
1

4
1

Q73
2
G

2

S

SSM3K7002FU_SC70-3

D

VLDT_EN#
R728
470_0603_5%

S
1

SUSP

2

2

1

C823

SUSP

1

C822

Q70
2
G

1

1
2
3

1U_0402_6.3V4Z

R727
1K_0402_5%

R766
100K_0402_5%

8
7
6
5

10U_0603_6.3V6M

D

5VS_GATE
2
47K_0402_5%

1
R730

+1.1VS

C821

R726
470_0603_5%

2

10U_0603_6.3V6M

2

1

C818

1U_0402_6.3V4Z

2

1

1

+VSBP

+5VALW
2

+1.1VALW

+5VALW

U70
AO4430L_SO8

1
2
3

C817

C820

2

1

8
7
6
5

E

+1.1VALW TO +1.1VS (4A)

+5VS

10U_0805_10V4Z

0.1U_0402_16V7K

C819

10U_0805_10V4Z

1

U69
SI4178DY-T1-GE3_SO8

1

+5VALW

D

1

+5VALW TO +5VS (5.35A)

C

SSM3K7002FU_SC70-3

B

2

A

D

3

2
G
S

2

SSM3K7002FU_SC70-3

2

Instant On

+3VALW TO +3V_FCH (1A)

1

+3VALW

C830
0.1U_0603_25V7K

+3V_FCH

R737
@
2
1
0_0805_5%
Q79
AO3404AL_SOT23

2
1
D

10mil
R743 2

1
D

S SSM3K7002FU_SC70-3

2

3

3

1

Q84
FCH_3.3PWR_EN# 2
G

SSM3K7002FU_SC70-3

FCH_3.3PWR_EN#

S

SUSP

S

Q82
2
G

1 200K_0402_5% 3V_GATE
3

+VSBP

3

D

Q81
2
G

1

S
2
G

1
2

D

R741
470_0603_5%

1

2

20mil

1

2
1

R769
470_0603_5%

1

2
1

2

C834
1U_0603_10V4Z

C833

10U_0805_10V4Z

S
SSM3K7002FU_SC70-3

C836
0.22U_0603_16V4Z

3

Q83
2
G

1

2

1

PX@

C832
10U_0805_10V4Z

R744
2
1
47K_0402_5%

1

C831

10U_0603_6.3V6M

R739
100K_0402_5%

SUSP#

+1.5VS

AP2301GN-HF_SOT23-3
Q78
3
1

40mil

3

D

1

+1.5V

2

+1.5V TO +1.5VS (0.5A)

SSM3K7002FU_SC70-3

C837
0.1U_0603_25V7K
3

2

2

+1.2VS

1

1

R745
470_0603_5%

D

Q85
2
G

VLDT_EN#

3

S

SSM3K7002FU_SC70-3

1

+0.75VS

+2.5VS

SYSON#

2
G

2
SUSP

3

S

3

S

SUSP

Q87

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

A

B

1
2
G

D

3

1
1

1

D

Q86

S

2
G

Q51
SSM3K7002FU_SC70-3~D

1

R747
470_0603_5%

+DDR_CHG

R746
470_0603_5%

D

R623
22_0603_5%~D

2

2

+1.5V
4

4

2011/07/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D

Title

DC Interface
Size
B
Date:

Document Number

Rev
0.11

QML70 LA-8371P
Wednesday, October 19, 2011

Sheet
E

39

of

53

A

B

PL1
HCB2012KF-121T50_0805
1
2

D

PH901 under CPU botten side :
CPU thermal protection at 90 degree C
Recovery at 50 degree C

VIN

ADP_I

2

2

1

@ PR2
5.62K_0402_1%
1

1

37

Turbo_V

2

NTC_V
1

37

@ PR3

@ PC13
.1U_0402_16V7K

1

PH1
100K_0402_1%_TSM0B104F4251RZ

2

13.7K_0402_1%

1

1

PC5
100P_0402_50V8J

2

1

PC3
1000P_0402_50V7K

PR1
13.7K_0402_1%

PJPDC1

Change DC040007T0L to DC040004L00
( Use DC040001V00 symbol )

37,41

+3VLP

2

1
2

2

1

CONN@
ACES_88299-0610
GND 8
GND 7
6 6
5 5
4 4
3 3
2 2
1 1

PC1
1000P_0402_50V7K

ADPIN

PC2
100P_0402_50V8J

PL2
HCB2012KF-121T50_0805
1
2

2

DCIN jack P/N:SP02000N000,
need doble confirm P/N with ME

1

C

PL3
HCB2012KF-121T50_0805
1
2
VMB
PL4
HCB2012KF-121T50_0805
1
2

PR14
22K_0402_1%
1
2

3

2
100_0402_1%

EC_SMB_CK1 37,41

1
PR31

2
100_0402_1%

EC_SMB_DA1 37,41

1
PR29

2
100K_0402_5%

1
PR30

2
1K_0402_1%

2

1
PR28

1VSB_N_003

PR18
0_0402_5%
1
2VSB_N_002 2
G
1

SPOK

D

3

1
37,42

S

1
2
2

1
2

PQ3
TP0610K-T1-E3_SOT23-3

2

VSB_N_001

PQ4
SSM3K7002FU_SC70-3

PC10
.1U_0402_16V7K

3

2

2
PR16
100K_0402_1%
@ PD2
PJSOT24CW _SOT323-3
2
1
3

PC8
0.22U_0603_25V7K

VL

@

+VSBP

1
PC9
0.1U_0603_25V7K

3

B+
2
1
PR13
100K_0402_1%

1
2

PC6
1000P_0402_50V7K

PC7
0.01U_0402_25V7K

PC128
10U_0805_25V6K
2
1

PR27
1K_0402_1%

BATT+

1

SUYIN_200275MR009G186ZL

2

2

EC_SMCA
EC_SMDA
TS_A

PD1
PJSOT24CW_SOT323-3

GND
GND

1
2
3
4
5
6
7
8
9

1

2

10
11

1
2
3
4
5
6
7
8
9

1

@ PJP2

+3VALW

BATT_TEMPA 37
3

PJ3
2

+CHGRTC

2

1

1

+3VLP

JUMP_43X39

2

VIN
@ PD3
RLS4148_LL34-2

3

+

PR20
68_1206_5%

2

1

1

1
PC11
0.22U_0603_25V7K

51_ON#

2

2
36

2
22K_0402_1%

1

Must close PBJ1
4

SP07000H700

VS_N_002

Compal Secret Data

Security Classification
Issued Date

For KB9012 --> Remove all 51_ON# circuit

A

+RTCBATT

Change RTC For Cost Down

4

1
@ PR24

+

LOTES_AAA-BAT-054-K01
CONN@

PC12
0.1U_0603_25V7K

2

2

PR23
100K_0402_1%

-

VS

1

N1

PR19
68_1206_5%
2

PQ5
TP0610K-T1-E3_SOT23-3

PBJ1

1

1

1

2

2

BATT+

RTC Battery

VS_N_001
1

@ PD4
LL4148_LL34-2

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

Title
Size

Compal Electronics, Inc.
PWR-DCIN / BATT CONN / OTP
Document Number

Rev
0.2

QML70 LA-8371P
Date:

W ednesday, October 19, 2011
D

Sheet

40

of

53

A

B

C

D

1

for reverse input protection

SI1304BDL-T1-E3_SC70-3

3

PQ106 D
2
G
S
PR103
2

1

2

1

3M_0402_5%

P2
0.01_2512_1% B+
PL102
1UH_FDSD0630-H-1R0M-P3_11A_20%
PR101
8
1
2
1
4
7
6
2
3
5

1
DH_CHG

PR125

0_0402_5%
3
2
1

1
2

PC109
0.01U_0402_50V7K

1
2

PC108
2200P_0402_50V7K

1
2

PC107
10U_0805_25V6K

CSON1
1

CSOP1
1

1
1
2

@

@

PC124
0.1U_0603_16V7K

ILIM

Remember to change PC124 from SE000006S80
to SE025104K80 (2011-02-22)
+3VALW

10

SCL
9

8

SDA

IOUT

ACDET

7

PR126

3
PC106
10U_0805_25V6K

11

BQ24725_BATDRV

2
10K_0402_1%

2

PC120
10U_0805_25V6K

12

1

PR102
0.02_1206_1%
4

2

SRN
BATDRV

1

PC122
0.1U_0402_25V6
2
1

ACDRV

1

13

2

SRP

3
2
1

CMSRC

4

1

3

@

2

1

4

BQ24725_ACDRV

ACOK

CHG

PC121
0.1U_0402_25V6

DL_CHG

2
GND

14

2

PC123
PR114
680P_0402_50V7K 4.7_1206_5%

15

1

5
6
7
8

16
REGN

17
BTST

18

PL101
2.2UH_ETQP3W2R2WFN_8.5A_20%
BQ24725_LX

BQ24725_CMSRC

1

PR106
0_0402_5%

BATT+

PQ105
AO4468L_SO8

LODRV

ACP

6

+3VL

3

@ PR117

2

2DH_CHG1
4

PC119
1
2

BQ24725RGRR_VQFN20_3P5X3P5

+3VALW

1
2

5

1

PQ104
SIS412DN-T1-GE3_POW ERPAK8-5

PR115
10_0603_1%
SRP1
2 CSOP1
PR116
6.8_0603_5%
SRN1
2 CSON1

2 BQ24725_ACOK 5
10K_0402_1%

@

2

BQ24725_REGN2

PR111
0_0603_5%
BQ24725_BST 2
1

PD102
RB751V-40_SOD323-2

2

2

PC114
0.01U_0402_50V7K

4

1
2

PC101
0.1U_0402_25V6

1
2

PC102
0.1U_0402_25V6

1
2

PC103
10U_0805_25V6K

1

PC104
10U_0805_25V6K

2

1

PC105
10U_0805_25V6K

2

1
2

20

19

HIDRV

ACN

PHASE

PAD

1

VCC

PU101

2BQ24725_BATDRV_1

1

2

1U_0603_25V6K

21

1
2
3

PR107
4.12K_0603_1%

PC116

DH_CHG

1U_0603_25V6K

BQ24725_BATDRV

0.047U_0402_25V7K

1

BQ24725_LX

BQ24725_VCC
2

BQ24725_ACP

1
2

1
2

PR109
4.12K_0603_1%

1
2

PC118
1
2
BQ24725_ACN

PR108
4.12K_0603_1%

PC117
0.1U_0603_25V7K

PC113
0.1U_0402_25V6

2

PC111
10U_0805_25V6K

2

3
1 1

2

@

8
7
6
5

PD101
BAS40CW_SOT323-3

PR110
10_1206_1%

2

1

BQ24725_ACDRV_1

1

PQ103
MDS2659URH_SO8

VIN

PC115
0.1U_0402_25V6

4

1
2

PC110
0.1U_0402_25V6

1

@ PR105
0_0402_5%

4

2

1
2

1
2
3

PC112
2200P_0402_50V7K

8
7
6
5

PQ102
MDS2659URH_SO8
1
2
3

PC130
10U_0805_25V6K
2
1

P1
PQ101
MDS2659URH_SO8

2

VIN

1

1M_0402_5%

PC129
10U_0805_25V6K

1

1

PR104

3

PR119

ILIM and external DPM
3.97A

PC125
0.01U_0402_25V7K

1
2

PR121
100K_0402_1%

2

1

2

210K_0402_1%

EC_SMB_CK1 37,40

PC127
2
1

100_0402_5%

1
2
1
2

Max.

1

Typ
17.23V
17.63V

2

H-->L
L--> H

PC126
0.1U_0402_25V6

Vin Dectector
Min.

2

2

PR120
255K_0402_1%

1

1

BQ24725_ACDET

2
10K_0402_1%

PR124

VIN

1

PR122
154K_0402_1%

PR118

PR123
66.5K_0402_1%

19,37 ACIN

1

BQ24725_ILIM

EC_SMB_DA1 37,40
ADP_I

37,40

100P_0402_50V8J

Please locate the RC
Near EC chip
2011-02-22

4

4

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
PWR-CHARGER

Size

Document Number

Rev
0.2

QML70 LA-8371P
Date:

W ednesday, October 19, 2011
D

Sheet

41

of

53

A

B

C

D

E

1

2VREF_51125

1

2

PC308
1U_0603_16V6K

5
3
2
1

2

PC318
4.7U_0805_10V6K

+

@

2

@

1

2

+5VALWP

150U_V_6.3VM_R18

1
1
2

PC320
1U_0603_10V6K

1

2

PR315
95.3K_0402_1%

@

1

1

VL

1
PC305

RT8205LZQW(2)_WQFN24_4X4
3
2
1

PQ304
AO4468L_SO8

PR313
4.7_1206_5%

4

SNUB_5V 2

37,40

PC317
680P_0402_50V7K

18

17

SPOK

FDMC7692S_MLP8-5

LG_5V

5

LX_5V

PR323
0_0402_5%

20
19

2

PL305
2.2UH_ETQP3W2R2WFN_8.5A_20%
1
2


PQ306

PR314
499K_0402_1%
2

21

UG_5V

NC

LGATE1

PC306
10U_0805_25V6K

2
ENTRIP1

FB1

REF

LGATE2
VREG5

PHASE1

VIN

UGATE1

PHASE2

4
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2

1

ENTRIP1
2

1

4
TONSEL

FB2

UGATE2

PQ305
SIS412DN-T1-GE3_POWERPAK8-5

EN0
1
2
3

2

22

13

@

1

BOOT1

16

B++

BOOT2

15

4

12

2

1

+

LG_3V

24
23

EN

PC316
PR312
680P_0402_50V7K
4.7_1206_5%
2
1 SNUB_3V 2
1

PC303
150U_V_6.3VM_R18

8
7
6
5

11

VO1
PGOOD

GND

LX_3V

B++

PR307
174K_0402_1%
1
2

VREG3

VO2

14

PL303
4.7UH_ETQP3W4R7WFN_5.5A_20%
2
1

PC314
8
0.1U_0402_10V7K
PR308
BST1_3V 1
1
2
2 BST_3V 9
2.2_0402_5%
UG_3V 10

ENTRIP2

1

2

7
PR318

0_0402_5%

1

1
2
3
2

+3VALWP

P PAD

2

PQ303
SIS412DN-T1-GE3_POWERPAK8-5

25

3

ENTRIP2

PU301
PC313
10U_0805_6.3V6M

4

5

6

PR303
133K_0402_1%
1
2

5

PC304
4.7U_0805_25V6-K
2
1

PC310
2200P_0402_50V7K
2
1

@

+3VLP

2
PC309
0.1U_0402_25V6
2
1

PC322
680P_0603_50V7K
2
1

1

PR306
20K_0402_1%
FB_5V 1
2

FB_3V

SKIPSEL

PL301
HCB2012KF-121T50_0805

1

PR302
20K_0402_1%
1
2

B++

B+

PR305
30.9K_0402_1%
1
2

PC312
2200P_0402_50V7K
2
1

PR301
13.7K_0402_1%
1
2

PC311
0.1U_0402_25V6
2
1

1

ENTRIP2

D
PQ307A
SSM6N7002FU_US6

G

2 N_3_5V_001

5

3

6

3

D

4

ENTRIP1

2

B++

S

1

3

PQ307B
SSM6N7002FU_US6

G

S

PC319
0.1U_0603_25V7K

2VREF_51125

+3VLP

+3VL
PJP302
2

1
PAD-OPEN 2x2m

PR322
100K_0402_1%
1
2
PR321
0_0402_5%
1
2

PJP305
PQ308
DRC5115E0L_SOD323-3

1

+5VALWP

1

+3VALWP

+5VALW

(5A,200mils ,Via NO.= 10)

2

+3VALW

(4A,120mils ,Via NO.= 8)

PAD-OPEN 4x4m

3

1

PC321
4.7U_0805_25V6-K

@

2

@ PR319
100K_0402_1%

2
PAD-OPEN 4x4m
PJP303

N_3_5V_002 2

2

2
1
PR320
42.2K_0402_1%

VS

1

VL

1

36,37 EC_ON
37 MAINPWON

PR317
100K_0402_5%
1
2

4

4

For KB930 --> Keep PR319, Remove PR322
For KB9012 (Red square) --> Remove PR319
Keep PR322

Compal Secret Data

Security Classification
2011/07/29

Issued Date

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
PWR-3.3VALWP/5VALWP

Size Document Number
Custom
Date:

Rev
0.01

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

42

of

51

5

4

3

2

1

D

1
2

1

PC402
22U_0805_6.3V6M

2
SY8033BDBC_DFN10_3X3

2

FB=0.6Volt

PR401
20K_0402_1%

PC401
22U_0805_6.3V6M

6

+1.8VSP
PC404
22P_0402_50V8J
2
1

TP

NC
7

FB

1

EN

2

SVIN

5

3

PL401
1UH_FMJ-0630T-1R0 HF_11A_20%
1
2
1

8

11
1

@ PD401

C

FB_1.8V

1

ISS355_SOD323-2
1
2

2

20,26,49 VGA_PWR_ON

200K_0402_1%
1
2 EN_1.8V
PC405
0.1U_0402_10V7K

PR404

PR405
1M_0402_5%
1
2

C

LX

LX_1.8V

1 2

PVIN

2

PC406
PR403
680P_0603_50V7K 4.7_1206_5%

9

LX

NC

PVIN

2

PC403
22U_0805_6.3V6M

10

1

PU401

1

+5VALW

PG

PL402
HCB1608KF-121T30_0603
1
2

4

D

2

PR402
10K_0402_1%

B

B

PJP401
+1.8VSP

2
@

2

1

1

+1.8VSG

JUMP_43X118

A

A

Compal Secret Data

Security Classification
2011/07/29

Issued Date

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
+1.8VP

Size

Document Number

Rev
0.01

QML70 LA-8371P
Date:

Wednesday, October 19, 2011

Sheet
1

43

of

51

5

2

BOOT_1.5V

DH_1.5V_1

PR511
1
2
0_0402_5%

DH_1.5V

VDD

VTTGND

1

VTTSNS

2

GND

3

VTTREF

4

VDDQ

5

37,39

SYSON

1

PC517
10U_0805_6.3V6K

2

1

+1.5VP

PR508
0_0402_5%
1
2

1.5V_B+

PC511
0.033U_0402_16V7K

6

7

8

2

FB

1

C

PR501
10.2K_0402_1%
2
1

FB_1.5V

+1.5VP

PR503
887K_0402_1%
1
2

PR502
10K_0402_1%

PC513
.1U_0402_16V7K

2

VTTREF_1.5V
off
on
on

2

VTTREF_1.5V

2

+0.75VSP
off
off
on

@

EN_1.5V

1

Level
L
L
H

@ PC512
680P_0402_50V7K

TON_1.5V

2

Mode
S5
S3
S0

PC508
10U_0805_6.3V6K

2

20
VTT

19

18
BOOT

21

1

+5VALW

2

PC510
1U_0603_10V6K

PAD

RT8207MZQW _W QFN20_3X3

1

+5VALW

PQ502
FDMC7692S_MLP8-5

17

1
11

4

VLDOIN

VDDP

UGATE

CS

12

S3

VDD_1.5V

13

9

1
@ PR506
4.7_1206_5%

PGND

PU501

1

2

PR507
5.1_0603_5%
1
2

1
2
3

PC501

+

SNUB_+1.5VP
2

C

330U_D2_2.5VY_R15M

1

14

S5

PC509
1U_0603_10V6K
1
2

LGATE

TON

PR505
20K_0402_1%
1
2CS_1.5V

15

PGOOD

PQ501
SIS412DN-T1-GE3_POW ERPAK8-5

PHASE

16

DL_1.5V

PC507
10U_0805_6.3V6K

+0.75VSP

SW _1.5V

5

1
2
3

PL501
1UH_VMPI0703AR-1R0M-Z01_11A_20%
2
1

+1.5V

10

2

PR504
1
2
2.2_0402_5%

PC506
0.22U_0402_10V6K

5

@

1

1
2

PC503
4.7U_0805_25V6-K

1
2

PC502
10U_0805_25V6K

1
2

PC505
2200P_0402_50V7K

1
2

D

BST_1.5V

4

+1.5VP

1

1.5V_B+

PC504
0.1U_0402_25V6

@

3

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A

PL502
HCB1608KF-121T30_0603
1
2

B+

PC516
680P_0603_50V7K
2
1

D

4

@ PC514
0.1U_0402_10V7K

2

B

EN_0.75VSP

1

Note: S3 - sleep ; S5 - power off

PJP501

1

37,39 SUSP#

2

B

PR510
0_0402_5%
2
1

1

PAD-OPEN 4x4m
PJP502

2

+1.5V (9A,360mils

,Via NO.= 18)

+0.75VS (2A,80mils

,Via NO.= 4)

2

1

+1.5VP

PAD-OPEN 4x4m

@ PC515
0.1U_0402_10V7K

PJP503
+0.75VSP

1

2
PAD-OPEN 3x3m

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR-1.5VP / +0.75VSP

Size
Document Number
Custom
Date:

Rev
0.01

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
1

44

of

51

5

4

3

2

1

D

D

1
2

1
2

1

PC806
22U_0805_6.3V6M

SNUB_+1.1V

1

+1.1VALWP

PC805
22U_0805_6.3V6M

2

LX

SS

PR804
2

2

FB_+1.1V

PC804
22U_0805_6.3V6M

6

1

FB

PC803
22U_0805_6.3V6M

3

C

1

8.45K_0402_1%

PR805
10K_0402_1%

2

1

PC808
2

1
22P_0402_50V8J

2
PJP801
+1.1VALWP

1

2
PAD-OPEN 4x4m

+1.1VALW

PC809
680P_0603_50V7K

@

+1.1VALWP

1

LX

PL802
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

LX_+1.1V

1

EN

2

2

SVIN

5

PG

4

@

2

@ PD801

PR803
2

ISS355_SOD323-2
1
2

8

LX

PC807
0.1U_0402_10V7K

1

2 EN_1.1V

0_0402_5%

C

47K_0402_5%

1

PVIN

11

PR801
37 FCH_1.1PWR_EN

SY8036DBC_DFN10_3X3

1

1
2

PC802
22U_0805_6.3V6M

9

TP

1
2

@ PC801
22U_0805_6.3V6M

PU801
10 PVIN

1.1V_B+

7

HCB1608KF-121T30_0603
1
2

PR802
4.7_1206_5%

PL801
+5VALW

+1.1VALWP
Iocp=4.94A
(6A,240mils ,Via NO.= 12)

B

B

A

A

Compal Secret Data

Security Classification
2011/07/29

Issued Date

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
+1.1VALWP

Size

Document Number

Rev
0.01

QML70 LA-8371P
Date:

Wednesday, October 19, 2011

Sheet
1

45

of

51

5

4

3

2

1

PL701
HCB1608KF-121T30_0603
2
1

PR702
2.2_0603_5%
1
2

RF

7

+1.2VSP_5V

6

LG_+1.2VSP

DRVL

3
2
1

V5IN

TP
1

11

TPS51212DSCR_SON10_3X3

PQ702

PC707
1U_0603_6.3V6M

PR705
470K_0402_1%

3
2
1

2

4

@

C

PR707

@

PC710

2

1

2

1000P_0402_50V7K

1
2

PL702
1UH_ETQP3W 1R0W FN_11.8A_20%
1
2

+1.2VSP

+5VALW

2

1
@ PC701
2

SW _+1.2VSP

1
PC708
330U_D2_2.5VY_R15M

5

8

1

RF_+1.2VSP

SW

SIS412DN-T1-GE3_POW ERPAK8-5

@ PR704
4.7_1206_5%

2

VFB

DRVH

UG_+1.2VSP

1

4

10
9

@ PC709
1000P_0603_50V7K

2

FB_+1.2VSP

BST_+1.2VSP

VBST

FDMC7692S_MLP8-5

EN

0.1U_0402_16V7K

@

TRIP

3

2

PR701
0_0402_5%
1
2

1

VLDT_EN

PR710
47K_0402_1%

37,39

PGOOD

2

4

1

1
PR703
1
2 TRIP_+1.2VSP
27.4K_0402_1%
EN_+1.2VSP

D

2

0.1U_0603_25V7K
PR711
0_0402_5%
1
2

5

PU701

PC706

1

B+

PC704
10U_0805_25V6K

PQ701

D

PC703
2200P_0402_50V7K
2
1

5

PC702
0.1U_0402_25V6
2
1

+1.2VSP_B+

+

2

C

PR706

1
PJP701

1.2K_0402_1%

+1.2VSP

2

7.15K_0402_1%
2
1

@

2

+1.2VS

1

1

JUMP_43X118

2

+1.2VSP
Iocp=13A

1

PR708
10K_0402_1%

B

B

PU702
APL5508-25DC-TRL_SOT89-3

1
2

PC711
1U_0603_10V6K

+2.5VSP

+2.5VSP

2

2

1

+2.5VS

1

@ JUMP_43X39
@ PR709
10K_1206_5%

(0.38A,20mils ,Via NO.=1)

2

1

GND

PJP702

3
1

OUT

1

IN

2

2

PC712
4.7U_0805_6.3V6K

+3VS

A

A

Compal Secret Data

Security Classification
2011/07/29

Issued Date

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
+1.2VSP/+2.5VSP

Size

Document Number

Rev
0.01

QML70 LA-8371P
Date:

W ednesday, October 19, 2011

Sheet
1

46

of

51

6

LGATE

5

PC234

PR249
1

1

1

2

PR257
2

10_0402_5%

PR256
0_0402_5%

0.1U_0603_25V7K

1
2

PC201
100U_25V_M

PC209
100U_25V_M

PC218
4.7U_0805_25V6-K
2
1

PR230
1_0402_1%
2

PJP201
1

PC230
10U_0805_25V6K
2
1

PC228
4.7U_0805_25V6-K
2
1

5
PQ209

PAD-OPEN 4x4m

CPU_B+
2

VSUM-1

3

0.36UH_ETQP4LR36WHC_24A_20%
PL204 1
4
+APU_CORE_NB
2

3

PR244
3.65K_0402_1%
VSUM+_NB
1
2
PR248
1_0402_1%
VSUM-_NB
1
2

@ PC246
680P_0402_50V7K

4

1

2

+APU_CORE

10_0402_5%

APU_VDD_SEN 8

Compal Secret Data
2011/07/29

Issued Date

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

PR229
3.65K_0402_1%
VSUM+
1
2

@PR253
@
PR253
32.4K_0402_1%

Security Classification
8 APU_VDD_RUN_FB_L

PR225
10K_0402_1%
1
2 ISEN1

PR258

2

PR255
0_0402_5%

PC242
1
2

2 1

1

0.01U_0402_50V7K

1

2

820P_0402_50V7K

2

2

3

137K_0402_1% 390P_0402_50V7K
@ PR252
2K_0402_1%

PC245

2
1

100_0402_1%

@ PC244
2
1

1

@ PR254
1

3
2
1

PR250
2

2.74K_0402_1%

2
PR224
10K_0402_1%
ISEN21
2

2

@

1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J

2

PC241
2
1

PR251
590_0402_1%
1
2

PC217
4.7U_0805_25V6-K
2
1
1
1 2
2

4

PC240
1
2

2

PC208
4.7U_0805_25V6-K
2
1

5

0.22U_0603_25V7K

1U_0603_16V6K

FCCM_NB

PC235
1
2

PR247

0.36UH_ETQP4LR36WHC_24A_20%
PL203 1
4
+APU_CORE

MDV1525URH_PDFN33-8-5

VCC

GND

4

1 2
1
PR242
4.7_1206_5% 3
PC238
680P_0603_50V7K
2
1

PWM

3

2

+5VS

4

MDU1512RH 1N POWERDFN56-8

7

BOOT

3
2
1

FCCM

2

PR241
2.2_0603_5% PC231
1
2 1
2

MDV1525URH_PDFN33-8-5

5
PQ205

8

5

PWM_Y
14,37

UGATE PHASE

1

1

2

1

49

4

PU202

10P_0402_50V8J

4

A

4

PR223
PC223
4.7_1206_5%
680P_0603_50V7K

3
2
1
PR262
0_0603_5%
1
2

+3VS

1

1

PR214
10K_0402_1%
1
2 ISEN2

NB_B+

PR259
100K_0402_1%

2

+APU_CORE

3

PC227
1U_0603_16V6K

ISL6208BCRZ-T_QFN8_2X2

PC237
1

@

PR216
1_0402_1%
2

5
3
2
1

2
2

1

UGATE1

2

2

PHASE1

VGATE

330P_0402_50V8J

PC239
2
1

0.022U_0402_16V7K

PC236
2
1

0.22U_0402_10V6K

11K_0402_1%

1
2

PC243
0.1U_0402_25V6

1

26
25

1

LGATE1

PC226
1U_0603_16V6K

PWM_Y

1

VSUM-

2

PH204
10K_0402_5%_ERTJ0ER103J

PR246
2

1 2

2.61K_0402_1%
PR245

4

TP

BOOT1
24

PGOOD

COMP

23

22

FB
21

20

RTN

28
27

1

VSUM+

29

2

1

VSUM-

LGATE2

PR201
1_0603_5%
1
2

2

PC232
1
2

PR264
@ 10K_0402_1%
1
2

PC224
0.22U_0603_50V7K

+5VS

30

BOOT1

ISEN2

FB2

UGATE1

VSEN

PHASE1

NTC

2

PQ204

37
UGATEX

39

38

LGATEX

PHASEX

40

42

43

41

45

IMON

+5VS
0_0402_5%
@1 PR240 2

44

LGATE1

1
470K_0402_5%_TSM0B474J4702RE

3

47

PWROK

PH203
2

46

VDD

19

12

LGATE2

PWM_Y

18

11
2
27.4K_0402_1%

PHASE2

ENABLE

13

PR238
9.76K_0402_1%

10

SVT

ISUMN

2PR237
1
107K_0402_1%
1
2
1 PR239

9

32
31

VDDP

ISUMP

13 APU_PWRGD_L

8

ISL6277HRTZ-T_TQFN48_6X6

VDDIO

17

VR_ON

UGATE2

LGATE2

16

APU_SVT

37

BOOT2

33

PHASE2

PC233
0.22U_0402_16V7K

8

7

35
34

SVD

ISEN1

100K_0402_1%
PC225
1000P_0402_50V7K
1
2

+1.5VS

VIN

VSUM-1

MDV1525URH_PDFN33-8-5

4

PC221
0.22U_0603_25V7K

PR226
0_0603_5% CPU_B+
1
2

36

BOOT2

VR_HOT_L

ISEN1 15

2

6

2

1

5

1

APU_SVD

BOOTX

UGATE2

ISEN3

PR260

PR220
2.2_0603_5%
BOOT2 1
2 1

SVC

ISEN2

8

1 PR228 2
0_0402_5%
1 PR231 2
0_0402_5%
PR232
1
2
0_0402_5%
1 PR233 2
0_0402_5%
1 PR234 2
0_0402_5%
1 PR235 2
0_0402_5%
1 PR236 2
0_0402_5%

14

APU_SVC

PWM2_NB

4

8

FCCM_NB

2PR227
1
107K_0402_1%

COMP_NB

IMON_NB

PGOOD_NB

NTC_NB

3

FB_NB

2

VSEN_NB

ISEN2_NB

ISUMN_NB

48

1
9.76K_0402_1% PH201
PC222
2
1
1000P_0402_50V7K
470K_0402_5%_TSM0B474J4702RE
1
2

8,37 H_PROCHOT#_EC

+3VS

ISEN1_NB

+5VS

0.22U_0402_16V7K

PR222
27.4K_0402_1%
1
2

ISUMP_NB

PU201
PR221
2

1

+

PR215
3.65K_0402_1%
VSUM+
1
2

3
2
1

PR261
0_0603_5%
1
2

PHASE2

2

PC207
4.7U_0805_25V6-K
2
1

PC206
4.7U_0805_25V6-K
2
1
2
1 2
1
PR212
4.7_1206_5%
PC214
680P_0603_50V7K

MDV1525URH_PDFN33-8-5

5
3
2
1

5
UGATE2

1

B+

CPU_B+

PQ203

FCCM_NB

PR263
10K_0402_1%
1
2

+

2
PR213
10K_0402_1%
ISEN11
2

PQ208

PR219
41.2K_0402_1%

2

220P_0402_50V7K

1

0.36UH_ETQP4LR36WHC_24A_20%
PL202 1
4

PQ206

@ PC216
2
1

1

2

@ PR218
1
100_0402_1%

MDV1525URH_PDFN33-8-5

3
2
1

4

2

1

VSUM-_NB

MDV1525URH_PDFN33-8-5
PQ207

5
PQ202

PC213
2
1

0.1U_0402_25V6

0.047U_0402_16V7K

LGATE1

PR217
649_0402_1%
1
2

2

PC212
2
1

11K_0402_1%

1

1

PC211
0.22U_0603_25V7K

PR211
2

1 2

2

MDU1512RH 1N POWERDFN56-8

VSUM+_NB

PC215
0.1U_0402_25V6

4

MDU1512RH 1N POWERDFN56-8

1

PR209
2.2_0603_5%
BOOT1 1
2 1

330P_0402_50V7K

PH202
10K_0402_5%_ERTJ0ER103J

4

PHASE1

100P_0402_50V8J

1

2.61K_0402_1%
PR210

PQ201

5
UGATE1

@ PR208
32.4K_0402_1%

PR243
0_0603_5%
1
2

3
2
1

PC205
1
2

PL201
HCB2012KF-121T50_0805
1
2
PL205
HCB2012KF-121T50_0805
1
2

CPU_B+

2

PR204
3.57K_0402_1%
+APU_CORE_NB
1
2
1
PR206
PC204
10_0402_1% 0_0402_5% 1000P_0402_50V7K
1
2
1
2
1
2
PR207
APU_VDDNB_SEN
@ PC210
301_0402_1%
1
2

E

PC299

D

@PR202
@
PR202
@ PC202
2K_0402_1%
330P_0402_50V7K
2
1 1
2
PR205
PC203
137K_0402_1% 390P_0402_50V7K
2 1
2 1
2

PR203

8

C

PC219
4.7U_0805_25V6-K
2
1

B

PC229
4.7U_0805_25V6-K
2
1

A

C

D

Compal Electronics, Inc.
+CPU_CORE/VDDNBP

Size Document Number
Custom
Date:

Rev
0.01

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
E

47

of

51

5
4

Security Classification

Issued Date

2011/07/29

3

PC933
10U_0603_6.3V6M
2
1

PC943
1U_0402_6.3V6K
2
1

PJP902
JUMP_43X79
@

Compal Secret Data

Deciphered Date
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size
A3
Date:
W ednesday, October 19, 2011
Sheet

1

48

PC973
1U_0402_6.3V6K
2
1

+VGA_CORE

PC972
1U_0402_6.3V6K
2
1

2

PC967
1U_0402_6.3V6K
2
1

+VDDC

PC936
1U_0402_6.3V6K
2
1

2

PC267
330U_D2_2V_Y

+

PC956
1U_0402_6.3V6K
2
1

PC266
330U_D2_2V_Y

1

PC968
1U_0402_6.3V6K
2
1

1

@

PC260
22U_0805_6.3V6M
2
1

3

PC954
1U_0402_6.3V6K
2
1

1

PC929
10U_0603_6.3V6M
2
1

PC942
1U_0402_6.3V6K
2
1

2

PC927
10U_0603_6.3V6M
2
1

PC941
1U_0402_6.3V6K
2
1

PC284
180P_0402_50V8J
2
1

PC256
10U_0805_6.3V6K
2
1

2

2

PC928
10U_0603_6.3V6M
2
1

PC940
1U_0402_6.3V6K
2
1

PC283
180P_0402_50V8J
2
1

+

PC935
1U_0402_6.3V6K
2
1

PC953
1U_0402_6.3V6K
2
1

PC963
1U_0402_6.3V6K
2
1

PC926
10U_0603_6.3V6M
2
1

PC969
1U_0402_6.3V6K
2
1

PC255
22U_0805_6.3V6M
2
1

1

PC930
10U_0603_6.3V6M
2
1

PC952
1U_0402_6.3V6K
2
1

PC962
1U_0402_6.3V6K
2
1

PC925
10U_0603_6.3V6M
2
1

PC938
1U_0402_6.3V6K
2
1

+VGA_CORE

PC254
22U_0805_6.3V6M
2
1

PC253
22U_0805_6.3V6M
2
1

@

PC282
180P_0402_50V8J
2
1

PC276
0.22U_0402_16V7K
2
1

PC252
22U_0805_6.3V6M
2
1

PC251
22U_0805_6.3V6M
2
1

PC250
22U_0805_6.3V6M
2
1

PC249
22U_0805_6.3V6M
2
1

+APU_CORE_NB

PC939
1U_0402_6.3V6K
2
1

PC951
1U_0402_6.3V6K
2
1

PC961
1U_0402_6.3V6K
2
1

PC924
10U_0603_6.3V6M
2
1

PC937
1U_0402_6.3V6K
2
1

@

PC275
0.22U_0402_16V7K
2
1

PC259
22U_0805_6.3V6M
2
1

PC262
22U_0805_6.3V6M
2
1

PC261
22U_0805_6.3V6M
2
1

+APU_CORE

PC922
10U_0603_6.3V6M
2
1

PC950
1U_0402_6.3V6K
2
1

PC960
1U_0402_6.3V6K
2
1

PC923
10U_0603_6.3V6M
2
1

PC964
1U_0402_6.3V6K
2
1

PC265
22U_0805_6.3V6M
2
1

PC264
22U_0805_6.3VAM
2
1

PC263
22U_0805_6.3V6M
2
1

PC248
22U_0805_6.3V6M
2
1

+APU_CORE

PC934
1U_0402_6.3V6K
2
1

PC949
1U_0402_6.3V6K
2
1

PC959
1U_0402_6.3V6K
2
1

PC931
10U_0603_6.3V6M
2
1

PC966
1U_0402_6.3V6K
2
1

PC281
180P_0402_50V8J
2
1

PC280
180P_0402_50V8J
2
1

PC279
0.01U_0402_50V7K
2
1

PC278
0.01U_0402_50V7K
2
1

PC258
22U_0805_6.3V6M
2
1

PC247
22U_0805_6.3V6M
2
1

4

PC921
10U_0603_6.3V6M
2
1

PC948
1U_0402_6.3V6K
2
1

PC932
10U_0603_6.3V6M
2
1

PC965
1U_0402_6.3V6K
2
1

B

PC958
1U_0402_6.3V6K
2
1

2

PC947
1U_0402_6.3V6K
2
1

+

PC957
1U_0402_6.3V6K
2
1

2
1

PC946
1U_0402_6.3V6K
2
1

+

PC971
1U_0402_6.3V6K
2
1

2
1

PC945
1U_0402_6.3V6K
2
1

+

PC271
330U_D2_2V_Y

Local

PC955
1U_0402_6.3V6K
2
1

2
1
@

PC944
1U_0402_6.3V6K
2
1

+
PC277
0.01U_0402_50V7K
2
1

@

PC970
1U_0402_6.3V6K
2
1

1

PC270
330U_D2_2V_Y

+APU_CORE

PC269
330U_D2_2V_Y

PC274
0.22U_0402_16V7K
2
1

PC257
22U_0805_6.3V6M
2
1

D

PC268
330U_D2_2V_Y

PC273
0.22U_0402_16V7K
2
1

5
1

+APU_CORE_NB
+APU_CORE_NB

Local
D

capacitors under processor on bottom side of board

C
C

+VGA_CORE
+VDDCI
+VDDCI

+VDDCI

of

B

A
A

Compal Electronics, Inc.

Document Number

PROCESSOR DECOUPLING
QML70 LA-8371P
51
Rev
0.01

A

B

PL901
HCB2012KF-121T50_0805
1
2

3
2
1

PC909
2.2U_0603_6.3V6K

1

5

1
4

PR908
470K_0402_1%

PR907
4.7_1206_5%

4

2

1
+

2

1
+

2

PR919

1

SSM3K7002FU_SC70-3

2

@

2

1

GCORE_SEN 22

PR917
5.1K_0402_1%
2

19

GPU_VID0

2
@ PR918
10K_0402_5%

1

S

GPU_VID0_1 1
PC913
0.1U_0402_16V7K

2
G
PQ906

2

PR914
10K_0402_1%
2

D

@ PR916
10K_0402_5%

2

100_0402_1%

1

GPU_VID1

+

+3VSG

1

2

+VGA_CORE1

2
5.1K_0402_1%

3

1
2

@

PC912
0.1U_0402_16V7K

S

1

1

1
2GPU_VID1_1
G
3

SSM3K7002FU_SC70-3
PQ905

FB0_VGA 1

2
@ PR915
5.1K_0402_1%
19

D

1

@ PR913
10K_0402_1%

2

@

Rtrip = 73.2K, OCP = 34.42A

35.7K_0402_1%

2

PR910
23.7K_0402_1%
FB1_VGA1
2

17.8K_0402_1%
1
2

PR912

2

1

PR909

1

+3VSG

+

PC911
680P_0402_50V7K

2

PR911

1

PC984
330U_D2_2V_Y

TPS51212DSCR SON 10P

PQ904

1SNUB_VGA

PQ903

2

11

5

+5VALW

MDU1512RH 1N POWERDFN56-8

TP

1
2
0_0603_5%

3
2
1

RF

V5IN_VGA
DL_VGA

PC920
330U_D2_2V_Y

DRVL

6

PC919
330U_D2_2V_Y

7

+VGA_CORE

PC910
330U_D2_2V_Y

V5IN

PR901

1

VFB

PL902
0.36UH_PDME104T-R36MS0R825_37A_20%
1
2

2

SW

LX_VGA

1

PC974
0.1U_0402_10V7K

EN

8

MDV1525URH_PDFN33-8-5

9

TRIP

PR904
PC906
1
2BST1_VGA 1
2
2.2_0603_5%
0.1U_0603_25V7K
2
1
PR905 0_0603_5%

4

MDU1512RH 1N POWERDFN56-8

5

DRVH

DH_VGA

2

4

BST_VGA

VBST

2

@

FB_VGA

10

PGOOD

1

PC907
0.1U_0402_16V7K

2

0_0402_5%

RF_VGA

2
1

20,26 1.5_VDD_PW REN

PR9032TRIP_VGA 2
1
73.2K_0402_1%
EN_VGA 3

3
2
1

PU901

1

13,20 VGA_PW RGD

5

1

4

PQ902

3
2
1

PQ901

PR902
10K_0402_1%

1 PR906

MDV1525URH_PDFN33-8-5

5

1
2

2

1

PC903
4.7U_0805_25V6-K
2
1

10U_0805_25V6K
PC902
2
1

2

PC905
2200P_0402_50V7K

PC904
0.1U_0402_25V6

+3VS

1

D

VGA_B+

10U_0805_25V6K
PC901
2
1

B+

C

Rrf = 470K, FSW = 290KHz
+5VALW
3

3

VGA_PCIE

+1.5V

PC914
1U_0402_6.3V6K

2

1

+5VALW

GPU_VID0

PR922
1.15K_0402_1%

APL5912-KAC-TRL_SO8

PR924
4.53K_0402_1%

2

0

1.0V

PJP901

+VGA_PCIEP

2

2

1

1

4

+1.0VSG

JUMP_43X79
@

Compal Secret Data

Security Classification
Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

PC916
0.01U_0402_25V7K

22U_0805_6.3V6M

2
9

PC917
2
1

FB
VIN

Core Voltage Level

0.9V

3K

+VGA_PCIEP

1

3

2

4

VOUT

1

5

2

VIN
VOUT

4

1

4.53K

2
GND

EN

PR923
47K_0402_5%

1

1

8

POK

1

Thames

7

1.1 V

PC915
4.7U_0805_6.3V6K

2

1
2

PR925
1K_0402_5%

PC918
0.1U_0603_25V7K
2
1

VGA_PW R_ON

20,26,43 VGA_PW R_ON

PR921
40.2K_0402_1%
1
2

2

RB751V-40_SOD323-2
1
2

VCNTL

PU902

For Whistler (Thames)
1/2Delta I=4.05A
Vtrip=36.5K*10uA=0.365V
Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A
=32.56A

6

1

1

PR924

PR920
0_0402_5%

@ PD901

1.0V

B

C

Title

Compal Electronics, Inc.
VGA_CORE

Size

Document Number

Rev
0.01

QML70 LA-8371P
Date:

W ednesday, October 19, 2011
D

Sheet

49

of

51

V ersion Change L ist ( P. I. R . L ist ) for Pow er Circuit
P age#

T itle

D ate

R equest
O w ner

Issue D escription

Solution D escription

Compal Secret Data

Security Classification

Issued Date

2011/07/29

Deciphered Date

2012/07/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
Power PIR

Size
Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet

50

of

53

5

4

3

2

Version change list (P.I.R. List)
Item

Fixed Issue

D

Rev.

PG#

0.02

22

2

0.02

3

Base on GPU Reference schematic

4

These components are for VGA

Date

Phase

Reserve pull-up / pull-down resistor 100ohm on GCORE_SEN

08/30

SR

15

Modify Netname of SPI signal of U5

08/30

SR

0.02

26

Change Q91.2 from 1.5_VDDC_PWREN# to 1.5VSG_PWREN#

08/30

SR

0.02

26

Change BOM Structure of R349, R350, R354, R355, Q95, Q96 to PX@

08/30

SR

08/30

SR

5

Base on AMD Comal CRB

0.02

8

6

For EMI request

0.02

15

Reserve R559, R561, C624, C625 @ FCH_SDCLK / FCH_SDWP

08/30

SR

7

0.02

36

Remove USB3.0 Host contorller circuit

09/01

SR

8

0.02

17

Remove componets of HUDSON_M2

09/01

SR

0.02

19

Modify GPU Straps: GPU_GPIO0 pull-high

09/01

SR

0.02

23

Reserve pull-high and pull-down resistor of MAA14/MBB14

09/01

SR

0.02

21

Modify U7.U13, U7.14 to NC

09/01

SR

19

Add THM_ALERT# to from U7.AG30 (GPU_THERMAL INT) to U34.6 (ADM1032)
Add GPU_CTF from U7.AM17 (GPU_CTF) to U72.97 (EC)

09/02

SR

Set PCIE FULL TX OUTPUT SWING to High (Full Swing)

10
Base on Thames M2 datasheet

11

B

12

0.02

13

0.02

31

Reserve Analog mircophone circuit

09/02

SR

14

0.02

9,
39,45

Change contorl singal of 1.1VALWP from SPOK to FCH_1.1PWR_EN
Change +1.1V_FCH to +1.1VALW

09/02

SR

15

0.02

15,37

Connect U72.92 (EC) to U2.V1 (FCH)for SYS ROM Write Protect

09/02

SR

16

0.02

35

Co-lay AI Charger

09/02

SR

17

0.03

31

Modify Analog Microhpone circut base on Vendor suggestion

09/05

SR

18

0.03

22

Add decoupling cap. base on GPU check list

09/06

SR

19

0.03

17

Change decoupling cap. base on FCH check list

09/06

SR

20

0.03

27

Change LVDS translator to RTD2136

09/06

SR

21

0.03

28

Add pull-up resistor R129, R132 (2.2K) of FCH_CRT_DDC_SDA / SCL

09/06

SR

13

Change R99 to 22ohm (CLK_SD_48M)

09/07

SR

0.03

22

A

Modify List

Change pull-up voltage of APU_RST#, APU_PWRGD, APU_SVT, APU_SVC, APU_SVD,
ALERT_L, ALLOW_STOP from +1.5V to +1.5VS

9
C

Page 1 of 2 for HW
Reason for change

1

1

23

0.03

14

Pull-down PEG_CLKREQ#

09/08

SR

24

0.03

37

Change Board ID, R398: 0ohm

09/08

SR

25

0.03

34

Change Power source of ODD from +5VS to +5VALW

09/09

SR

26

0.03

33

Change Power source of WLAN from +3VALW to +3VS

09/09

SR

27

0.03

32

Add power source for none Card Reader IC solution

09/09

SR

Compal Secret Data

Security Classification
Issued Date

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

D

C

B

A

Compal Electronics, Inc.
HW-PIR1

Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
1

51

of

53

5

4

3

2

Version change list (P.I.R. List)
Item

D

C

Page 2 of 2 for HW
Rev.

PG#

Date

Phase

1

0.2

15

Change U5 power from +3V_PCH to +3V_FCH

10/11

SR2

2

0.2

15

Change GBE_MDIO pull-up voltage from +3VALW to +3V_FCH

10/11

SR2

0.2

25

SWAP QSB7 and QSB#7

10/11

SR2

4

0.2

32

Delete Net SDCD, SDWP# that connect to EC
Add MOSFET inverter of SDWP#

10/11

SR2

5

0.2

8

Un-mount pull-high resistor of APU_SVT, APU_SVC, APU_SVD

10/11

SR2

6

0.2

28

Follow QCL70 pin define

10/11

SR2

7

0.2

38

Modify Touch Pad pin define

10/11

SR2

8

Change pull-high voltage of APU_PROCHOT#, APU_THERMTRIP#, APU_SVT, APU_SVC,
APU_SVD, ALERT_L, ALLOW_STOP, APU_RST#, APU_PWRGD, APU_SIC, APU_SID

10/11

SR2

Change R299, R300, R309, R310, R319, R320, R325, R326 from 56ohm to 40.2ohm

10/11

SR2

3

Fixed Issue

1

Reason for change

Blue Screen after install VGA Driver

8

For voltage leakage

0.2

9

Base on AMD recommend

0.2

Modify List

24, 25

10

0.2

37

Change Board ID to "1" for SR2

10/13

SR2

11

0.2

22

Seperate VDDC and VDDCI of VGA

10/14

SR2

12

0.2

23

Reserve R611, R612 for MAA14, MAB14

10/14

SR2

D

C

13
14
15
16
17
B

B

18
19
20
21
22
23
24
25

A

A

26
27
Compal Secret Data

Security Classification
Issued Date

2011/07/29

2012/07/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
HW-PIR2

Size Document Number
Custom
Date:

Rev
0.2

QML70 LA-8371P

Wednesday, October 19, 2011

Sheet
1

52

of

53

www.s-manuals.com



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Title                           : Compal LA-8371P - Schematics. www.s-manuals.com.
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