Compal LA 8581P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-8581P QAQ10, QAQ11 - Schematics. Free.

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5

1

2

3

4

D

D

Compal Confidential
QAQ10/11

C

C

Schematic

LA-8581P REV1.0

B

B

Intel Ivy Bridge/Pather Point
UMA&OPT
2012-04-23 Rev 1.0

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

1

of

60

Compal Confidential
Model Name : QAQ10/11
File Name : LA-8581P

1

2

3

4

5

Fan Control

page 6

PEG(DIS)

PCI-E 2.0x16

100MHz

Mobile Ivy Bridge

5GT/s PER LANE
133MHz

CPU Dual Core

Memory BUS(DDRIII)

D

Socket-rPGA988B/989

VGA (DDR3)

D

204pin DDRIII-SO-DIMM X2

Dual Channel
1.5V DDRIII 1333/1600

37.5mm*37.5mm page 5,6,7,8,9,10

page 11,12

BANK 0, 1, 2, 3

NVIDIA N13P-GLP, 128bit with 1GB/2GB
DMI X4

page 13,14,15,16,17,18,19,20,21

FDI
USB3.0
USB port 0

USB/B Right USB Left Port

USB port 3,4

CRT
OPT & UMA

page 23

LCD Conn.
C

port 4

port 2

port 6

port 3

port 5

USB port 2

SATA port 0

port 1

5V 1.5GHz(150MB/s)

HM76

SATA port 2
5V 1.5GHz(150MB/s)

PCIeMini Card
WLAN &BT
USB Port 13

PCIe port 1

SATA port 4

PCIe Port 5

PCIe Port 2

page 36

page 36

5V 1.5GHz(150MB/s)

page 35,42

USB Port 12

page 40

Finger Print
USB port 11

USB port 10

page 25 ~ 32

page 40

C

page 34

SATA ODD

page 34

E-SATA
USB port 3

HD Audio

25mm*25mm

page 23

SATA HDD0

RTL8111E&Intel 82579

PCIe Mini Card WWAN
&SIM

page 43

Int. Camera

page 39

989pin FCBGA

100MHz

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

Smart Card

Intel
Panther Point-M

HDMI Conn.
page 24

page 44

USB

OPT & UMA

page 22

USB port 1,9

page 43

3.3V 24.576MHz/48Mhz

BIOS ROM

RJ45
JMB385/388 Card Reader
&1394
PCIe Port 6

Express Card
PCIe Port 3

LPC BUS

ALC259
page 38

page 39

USB&Function/B

B

33MHz

ENE KB9012

SIO

page 43

Power/B

HDA Codec

USB port 8

page 37

B

page 33

page 39

Page 47

TPM 1.2

page 41

Int. MIC

page 34

page 38

MIC CONN
page 38

SPK CONN
page 38

HP CONN
page 38

page 43

Touch Pad
Touch Pad/B

Int.KBD

page 43

page 40

page 43

RTC CKT.
page 25,47

A

DC/DC Interface

A

page 45

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Power Circuit DC/DC

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 46,47,48,49,50,51,52,53,54,55,56,57,58

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

2

of

60

Ipeak=5A, Imax=3.5A, Iocp min=7.9

DESIGN CURRENT 5A

+5VALW

DESIGN CURRENT 4A

+5VS

DESIGN CURRENT 2A

+1.8VS

1

2

3

4

5

B+

SUSP

N-CHANNEL
SI4800
SUSP#

SY8033BDBC

D

D

RT8205
DESIGN CURRENT 5A

Ipeak=5A, Imax=3.5A, Iocp min=7.7

+3VALW

WOL_EN#
DESIGN CURRENT 330mA

P-CHANNEL
AO-3413

+3V_LAN

SUSP
DESIGN CURRENT 4A

N-CHANNEL
SI4800

+3VS

VGA_ENVDD

P-CHANNEL
AO-3413
BT_PWR#

DESIGN CURRENT 1.5A

+LCD_VDD

DESIGN CURRENT 180mA

+BT_VCC

DESIGN CURRENT 100mA

+3VS_DELAY

P-CHANNEL
AO-3413
PCIE_OK
C

P-CHANNEL
AO-3413

C

VR_ON
DESIGN CURRENT 52A

+CPU_CORE

DESIGN CURRENT 30A

+GFX_CORE

DESIGN CURRENT 26A

+VGA_CORE

DESIGN CURRENT 18A

+1.05VS_VCCP

ISL95831CRZ

DGPU_PWR_EN / SUSP#

APW7138
SUSP#

Ipeak=18A, Imax=12.6A, Iocp min=19.8

G5603RU1U

B

B

SYSON

Ipeak=15A, Imax=10.5A, Iocp min=16.5

DESIGN CURRENT 15A

+1.5V

+1.5V_CPU

G5603RU1U
CPU1.5V_S3_GATE / SUSP

DESIGN CURRENT 2A

+0.75VS

DESIGN CURRENT 12A

+1.5VS

DESIGN CURRENT 6A

+VCCSA

APL5336
SUSP

SI4856
SUSP#
A

G5603RU1U

A

2011/09/23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/12/30

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

3

of

60

Power Plane

D

BOM configu table
S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

Description

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+VCC_CORE

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VSDGPU

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VCCP

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VCCP to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

+1.5VSDGPU

+1.5VS to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_EC

+3VALW always to KBC

ON

ON

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

OFF

ON

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

C

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

SKU

SIGNAL

B

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON

EC SM Bus1 address

EC SM Bus2 address

Power

Device

Address

Power

Device

Address

+3VL

charger

0x12

+3VS

VGA(N13P-GLP)

0X9E

+3VL

Smart Battery

0x16

+3VS

PCH

0x96

Description

Bom config

1

QAQ10 UMA GIGA W/HDMI

DA8@/8111E@/UMA@/TF@/10@/WIN8@/388@/COM@

4619IE30L01

2

QAQ11 DIS N13PGLP1G W/HDMI

DA8@/8111E@/OPT@/TF@/11@/WIN8@/388@/COM@

4619IE30L11

3

QAQ13 DIS GLP2G W/HDMI/TPM

DA8@/8111E@/OPT@/030@/13@/WIN8@/388@/COM@
/TPM@/IN_TPM@

4619IE30L21

5
6
7
8
DA8@/8111E@/PCH@/UMA@/OPT@/385@/388@/389@/IN_TPM@/TPM@/WB_TPM@/SM@/COM@/030@/TF@
/WIN8@/10@/11@/12@/13@/Rev02@/Rev03@/Rev04@/Rev10@/VPRO@
388@: with 1394;
389@: without 1394.

IN_TPM@: TPM chip from vendor "INFINEON";
WB_TPM@: TPM chip from vendor "Nuvoton"
With TPM SKUs: mount "TPM@ and IN_TPM@ " or "TPM@ and WB_TPM@".

If has Vpro@, no 8111E@, Rev02@,Rev03@, Rev04@ and Rev10@.

SKU
1
2
3
4
5

Description
4619IE30L11

ZZZ
SAM1G@
SAM 1G

Config
HY1G@
ZZZ
Hynix 1G

QAQ11 DIS N13P-GLP

4619IE30L21

ZZZ
SAM2G@
SAM 2G

HY2G@
ZZZ
Hynix 2G

QAQ13 DIS N13P-GLP

Board ID Rb
Table

Ra

VCC

Vtyp

Vmax

PCB Revision

0

0

100K +/- 5%

3.3V +/- 5% 0V

0V

0V

0.1

1

8.2K +/- 5%

100K +/- 5%

3.3V +/- 5% 0.216 V

0.250 V

0.289 V

0.2

2

18K +/- 5%

100K +/- 5%

3.3V +/- 5% 0.436 V

0.503 V

0.538 V

0.3

3

33K +/- 5%

100K +/- 5%

3.3V +/- 5% 0.712 V

0.819 V

0.875 V

0.4

4

56K +/- 5%

100K +/- 5%

3.3V +/- 5% 1.036 V

1.185 V

1.264 V

1.0

5

100K +/- 5%

100K +/- 5%

3.3V +/- 5% 1.453 V

1.650 V

1.759 V

VPRO

6

200K +/- 5%

100K +/- 5%

3.3V +/- 5% 1.935 V

2.200 V

2.341 V

7

NC

100K +/- 5%

3.3V +/- 5% 2.500 V

3.300 V

3.300 V

Board ID

V min

UPCH1
BD82HM76 SLJ8E C1 BGA 989P PCH 030!
8111E@

UPCH1
BD82QM77 QPRE C1 BGA 989P PCH
VPRO@

A

+3VALW

PCH

ZZZ

Address

+3VS

Clock Generator

1101 001x b

+3VS

DDR DIMMA

1001 000x b

+3VS

DDR DIMMB

1001 010x b

+3VS

Slot#1--WLAN

DA8@

ZZZ

DAZ@

PCB
PCB LA-8581P REV1 M/B

Issued Date

PCB QAQ10

Compal Secret Data

Security Classification

2011/09/23

2011/12/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

A

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Rev
B

4019IE

Date:
5

B

PCH And PCBA table

PCH SM Bus address
Device

C

X76 AND VGA configu table

PCH

Power

D

4

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

1

2

3

4

5

Voltage Rails

Friday, August 24, 2012

Sheet
1

4

of

60

1

2

3

4

5

+1.05VS_VCCP

1

JCPU1I

2

RC2
24.9_0402_1%

JCPU1A

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

<27>
<27>
<27>
<27>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

<27>
<27>
<27>
<27>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<27>
<27>

FDI_FSYNC0
FDI_FSYNC1

<27>

FDI_INT

<27>
<27>

FDI_LSYNC0
FDI_LSYNC1

RC4

1

G21
E22
F21
D21

G22
D22
F20
C21

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1

FDI_INT

24.9_0402_1%
2

EDP_COMP

2

+1.05VS_VCCP

A21
H19
E19
F18
B21
C20
D18
E17

A22
G19
E20
G18
B20
C19
D19
F17

J18
J17

H20

J19
H17

FDI_LSYNC0
FDI_LSYNC1

+1.05VS_VCCP

B

B28
B26
A24
B23

A18
A17
B16
C15
D15

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

eDP_AUX
eDP_AUX#

1

10K_0402_5%
@ R88

EDP_HPD#

C17
F16
C16
G15

C18
E16
D16
F15

DMI

<27>
<27>
<27>
<27>

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

C

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>

<27>
<27>
<27>
<27>

eDP

B27
B25
A25
B24

D

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms

PEG_COMP

PCIE_GTX_C_CRX_N[0..15]
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

<13>

PEG signals swapped at VGA side.

PCIE_GTX_C_CRX_P[0..15]

2
2

OPT@
C222 1
OPT@
C136 1
C60 1
OPT@

2

OPT@ C67
C75 1 1
OPT@

22

OPT@
C220 1
C118 1
OPT@

2

C62 1 1
OPT@ C59
OPT@
OPT@
C115 1
OPT@
OPT@

C70 1
C197 1

2

22

2

2

OPT@
C61 1
C223 1
OPT@

2

C88 1 1
OPT@ C68
OPT@

22

OPT@

2

C209 1

OPT@
C66 1
C224 1
OPT@

2

2

C89 1 1
OPT@ C69
OPT@
C221 1
OPT@
C135 1
OPT@
OPT@
C71 1

22

C74 1 1
OPT@ C72
OPT@

22

C214 1 1
OPT@ C117
OPT@

22

OPT@
C78 1
OPT@ C79
C87 1 1
OPT@

2
22

OPT@

C111 1

2

2

2

2

2

2

<13>

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N3
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N7
0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N14
0.1U_0402_16V7K PCIE_CTX_C_GRX_N15
0.1U_0402_16V7K PCIE_CTX_C_GRX_P0
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P1
0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P8
0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P10
0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[0..15]

<13>

PCIE_CTX_C_GRX_P[0..15]

<13>

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

D

C

B

TYCO_2013620-2_IVY BRIDGE
CONN@

TYCO_2013620-2_IVY BRIDGE
CONN@

A

A

Compal Secret Data

Security Classification

Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

5

of

60

1

2

3

4

5

<27>

SYSTEM_PWROK

C85
0.1U_0402_16V4Z

+3VALW

+3VS

1

+3VALW

@ RC13
10K_0402_5%

R104

R289
200_0402_1%

B

O

2

0_0402_5%
RC21
D_PWG
short@

A

4
VDDPWRGOOD
D

3

PM_DRAM_PWRGD

R81
200_0402_1%

G

<27>

D

P

1

+1.5V_CPU_VDDQ

U5
74AHC1G08DCKR_SC70-5

5

2

0_0402_5%
short@

0_0402_5%
@ 2
RC16 1
SUSP

5

Y

1
2
R72
C

4
BUFO_CPU_RST#
SN74LVC1G07DCKR_SC70-5

43_0402_1%
BUF_CPU_RST#

+1.05VS_VCCP
<29>

2
R47
62_0402_5%

1
H_PROCHOT#

PROC_SELECT#

H_SNB_IVB#

AN34

SKTOCC#

CC62

@

220P_0402_25V8J

AL33

T0501
H_CATERR#

CATERR#

CLOCKS

Processor Pullups

C26

MISC

JCPU1B

PROC_SELECT#:
Sandy Bridge---output high;
Ivy Bridge---output low.

@
R73
0_0402_5%

2

3

A

R64
75_0402_5%

U3

P

NC

G

2
PLT_RST#

@
Q5
2N7002_SOT23-3

+1.05VS_VCCP

C84
0.1U_0402_16V4Z

1
<28,34,35,36,37,39,41,42,44>

S

0_0402_5%

+3VS

C

D

2
G

1

<11,40,43,45>

1

RUN_ON_CPU1.5VS3#

<10,45>

3

@

@ 2

RC17 1

R110
39_0402_1%

BCLK
BCLK#

A28
A27

short@
CLK_CPU_DMI_R
CLK_CPU_DMI#_R

R138 1
R139 1

2 0_0402_5%
2 0_0402_5%
short@

CLK_CPU_DMI
CLK_CPU_DMI#

<26>
<26>

+1.05VS_VCCP

PU/PD for JTAG signals
DPLL_REF_CLK
DPLL_REF_CLK#

A16
A15

CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

2 1K_0402_5%
2 1K_0402_5%

R126 1
R115 1

+1.05VS_VCCP

XDP_TMS_R

51_0402_5%
51_0402_5%

XDP_TDI_R

RC46
RC47

51_0402_5%

RC48

@

H_PECI

H_PROCHOT#

H_PROCHOT#

B

AN33

2
H_PECI_R

R58
2
1
56_0402_5% H_PROCHOT#_R

AL32

Place R58 close to CPU.
<29>

AN32

2
H_THERMTRIP#_R
0_0402_5%

1
R14

H_THERMTRIP#

PECI

PROCHOT#

THERMTRIP#

SM_DRAMRST#

R8
H_DRAMRST#

DDR3
MISC

<29,41>

<41,47>

RC441
43_0402_1%

THERMAL

XDP_PREQ#_R

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AK1
A5
A4

H_DRAMRST#

<7>

DDR3 Compensation
Signals
2
140_0402_1% 1

RC49

51_0402_5%

RC57

RC42

SM_RCOMP0

25.5_0402_1%1

2 RC43

200_0402_1% 1

2 RC45

SM_RCOMP1
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

51_0402_5%
XDP_TDO_R

XDP_TCK_R

SM_RCOMP2

51_0402_5%

RC55

XDP_TRST#_R
B

short@

<27>

<29>

AM34

2
1
H_PM_SYNC_R
0_0402_5% short@

H_PM_SYNC

R16
2
1
H_CPUPWRGD_R
0_0402_5% short@

H_CPUPWRGD

AP33

PM_SYNC

UNCOREPWRGOOD

R79
VDDPWRGOOD

V8

2
1
130_0402_1% VDDPWRGOOD_R

AR33
BUF_CPU_RST#

10K_0402_5%

SM_DRAMPWROK

RESET#

R50

H_CPUPWRGD_R

JTAG & BPM

R15

PWR MANAGEMENT

PRDY#
PREQ#

TCK
TMS
TRST#

TDI
TDO

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AP29
AP27

XDP_PRDY#_R
XDP_PREQ#_R
AR26
AR27
XDP_TCK_R
AP30
XDP_TMS_R
XDP_TRST#_R
AR28
AP26
XDP_TDI_R
XDP_TDO_R

+5VS1A

FAN Control Circuit
2
C863
10U_0805_10V4Z

1

JFAN

U58

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

1
2
3
4

+FAN1

<41>

EN_DFAN1

1

10mil
2

EN
VIN
VOUT
VSET

GND
GND
GND
GND

8
7
6
5

1

1
2
3

GND
GND
ACES_85205-03001
CONN@

G996P11U SOP 8P
C1
10U_0805_10V4Z

R3

2

10K_0402_5%
1
+3VS

TYCO_2013620-2_IVY BRIDGE
CONN@

2

Compal Secret Data

Security Classification
Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

3

2

A

C865@
0.01U_0402_25V7K

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Rev
B

4019IE

Date:
4

<41>

FAN_SPEED

1

220P_0402_25V8J

5

4
5

@ C864
1000P_0402_50V7K

@ C379
A

1
2
3

+FAN1

2

AL35
XDP_DBRESET#

Friday, August 24, 2012

Sheet
1

6

of

60

1

2

3

4

5

JCPU1C

JCPU1D

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C

<11>
<11>
<11>

B

<11>
<11>
<11>

AE10
AF10
V6

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AE8
AD9
AF9

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

SA_CAS#
SA_RAS#
SA_WE#

DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0

AA5
AB5
V10

<11>
<11>
<11>

DDR_B_D[0..63]

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20

<11>
<11>

DDRA_SCS0#
DDRA_SCS1#

DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28

<11>
<11>

DDRA_ODT0
DDRA_ODT1

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12

<11>
<11>
<11>

DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1

AB4
AA4
W9

<12>

DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

AB6
AA6
V9

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

<11>

DDR_A_DQS#[0..7]
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS[0..7]

DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54

<11>

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA[0..15]

DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58

<11>

DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

<12>
<12>
<12>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<12>
<12>
<12>

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AA9
AA7
R6

AA10
AB8
AB9

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AE2
AD2
R9

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

AE1
AD1
R10

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

DDR SYSTEM MEMORY B

DDR_A_D[0..63]

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

DDR SYSTEM MEMORY A

<11>

D

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

<12>
<12>
<12>

DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1

<12>
<12>
<12>

DDRB_SCS0#
DDRB_SCS1#

<12>
<12>

D

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
SB_ODT[0] AD4
AD5
SB_ODT[1]
RSVD_TP[19]
AE5
RSVD_TP[20]

DDRB_ODT0
DDRB_ODT1

<12>
<12>

C

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

<12>

DDR_B_DQS#[0..7]
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS[0..7]

<12>

DDR_B_MA[0..15]

<12>

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

B

TYCO_2013620-2_IVY BRIDGE
CONN@

TYCO_2013620-2_IVY BRIDGE
CONN@

+1.5V

@
R124

0_0402_5%
QC3

R123
1K_0402_5%

BSS138_SOT23

3
<6>

D

S

1

H_DRAMRST#

H_DRAMRST#

DDR3_DRAMRST#_R

R129

1K_0402_5%

SM_DRAMRST#

<11,12>
A

2

G

A

R119
4.99K_0402_1%

DRAMRST_CNTRL

short@
R118

0_0402_5%

DRAMRST_CNTRL_PCH

<10,26>

Compal Secret Data

Security Classification

C86
0.047U_0402_16V4Z

Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.

SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

7

of

60

1

2

3

4

5

CFG Straps for Processor
D

D

CFG2

RC51
1K_0402_1%

JCPU1E

CFG[3]:

reserved configuration lane.

reserved

CFG[17:7]:

reserved configuration lanes.

CFG[17:0]:
Processor internal pull up 5~15Kohm to VCCIO

T266

VCC_DIE_SENSE
VSS_DIE_SENSE

PAD
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

T251
PAD
T252 PAD
T253 PAD
T254 PAD
T255 PAD
T256 PAD
T257 PAD
T258 PAD
T259 PAD
T260 PAD
T261 PAD
T267 PAD
T268 PAD
T269 PAD
T270 PAD
T262 PAD
T263 PAD

T245
T246
T247
T248

PAD
PAD
PAD
PAD

AJ31
AH31
AJ33
AH33

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

CFG

CFG[1:0]:

RSVD33
RSVD34
RSVD35

AH27
AH26

L7
AG7
AE7
AK2

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed

W8

CFG2
AT26
AM33
AJ27

CFG4

RSVD37
RSVD38
RSVD39
RSVD40

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

@ RC52
1K_0402_1%

T8
J16
H16
G16

C

C

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

J20
B18

J15

RSVD5

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RESERVED

AJ26

RSVD24
RSVD25

RSVD27

B

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10

AR35
AT34
AT33
AP35
AR34

Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

B34
A33
A34
B35
C35

CFG6

CFG5

RSVD51
RSVD52

BCLK_ITP
BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

@ RC54
1K_0402_1%

AJ32
AK32

AN35
AM35

CLK_RES_ITP
CLK_RES_ITP#

@ RC53
1K_0402_1%

<26>
<26>

AT2
AT1
AR1

PCIE Port Bifurcation Straps
B

11: (Default) x16 - Device 1 functions 1 and 2 disabled
KEY

CFG[6:5]

B1

TYCO_2013620-2_IVY BRIDGE

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CONN@
CFG7

@ RC56
1K_0402_1%

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately
following RESETB de assertion
0: PEG Wait for BIOS for training
A

A

Compal Secret Data

Security Classification

Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

8

of

60

JCPU1F

JCPU1H

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

POWER
+1.05VS_VCCP

AH13

8.5A
AH10

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

D

AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

Package Sensing Recommendations--PDDG P30

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

Sense

Trace Impedance

VCC_SENSE /
VSS_SENSE

25.5-34.5ohm

Trace Length Match

VCCAXG_SENSE /
VSSAXG_SENSE

<25 mils

VCCIO_SENSE /
VSS_SENSE_VCCIO

55ohm
C

VCCSA

J23

+1.05VS_VCCP

short@
RC59

0_0402_5%
VR_SVID_CLK

<54>

1

H_CPU_SVIDCLK

Place the PU resistors
RC60, RC137 close to CPU.

2

RC60
75_0402_5%

VIDALERT#
VIDSCLK
VIDSOUT

AJ29
AJ30
AJ28 H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

RC61

VR_SVID_ALRT#

43_0402_1%

<54>

+1.05VS_VCCP

RC137
130_0402_1%

B

RC65

H_CPU_SVIDDAT

0_0402_5%
VR_SVID_DAT

short@

<54>

1

+VCC_CORE

R53
100_0402_1%

VCCIO_SENSE
VSS_SENSE_VCCIO

AJ35
AJ34
VCCSENSE_R
VSSSENSE_R

short@

R52
R51

short@

B10
A10

VCCSENSE
VSSSENSE

0_0402_5%
0_0402_5%

R168
1

<54>
<54>

1

VCC_SENSE
VSS_SENSE

2

Place the PU resistors
R53, R54 close to CPU

2

R54
100_0402_1%

+1.05VS_VCCP

2

10_0402_1%

VCCIO_SENSE

<51>

1

CONN@

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

CC50
0.1U_0402_16V4Z

TYCO_2013620-2_IVY BRIDGE

AG35
AG34 VCC1
AG33 VCC2
AG32 VCC3
AG31 VCC4
AG30 VCC5
AG29 VCC6
AG28 VCC7
AG27 VCC8
AG26 VCC9
AF35 VCC10
AF34 VCC11
AF33 VCC12
AF32 VCC13
AF31 VCC14
AF30 VCC15
AF29 VCC16
AF28 VCC17
AF27 VCC18
AF26 VCC19
AD35 VCC20
AD34 VCC21
AD33 VCC22
AD32 VCC23
AD31 VCC24
AD30 VCC25
AD29 VCC26
AD28 VCC27
AD27 VCC28
AD26 VCC29
AC35 VCC30
AC34 VCC31
AC33 VCC32
AC32 VCC33
AC31 VCC34
AC30 VCC35
AC29 VCC36
AC28 VCC37
AC27 VCC38
AC26 VCC39
AA35 VCC40
AA34 VCC41
AA33 VCC42
AA32 VCC43
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
Y34 VCC51
Y33 VCC52
Y32 VCC53
Y31 VCC54
Y30 VCC55
Y29 VCC56
Y28 VCC57
Y27 VCC58
Y26 VCC59
V35 VCC60
V34 VCC61
V33 VCC62
V32 VCC63
V31 VCC64
V30 VCC65
V29 VCC66
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78
U26 VCC79
R35 VCC80
R34 VCC81
R33 VCC82
R32 VCC83
R31 VCC84
R30 VCC85
R29 VCC86
R28 VCC87
R27 VCC88
R26 VCC89
P35 VCC90
P34 VCC91
P33 VCC92
P32 VCC93
P31 VCC94
P30 VCC95
P29 VCC96
P28 VCC97
P27 VCC98
P26 VCC99
VCC100

SVID

97A

PEG AND DDR

+VCC_CORE

CC49
0.1U_0402_16V4Z

B

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

SENSE LINES

C

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

CORE SUPPLY

D

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

1

2

3

4

5

R158
10_0402_1%
A

2

A

TYCO_2013620-2_IVY BRIDGE
CONN@

Compal Secret Data

Security Classification

Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

9

of

60

1

2

3

4

5

+1.5V_CPU_VDDQ

+1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ

+1.5V

Q7
AO4728L_SO8

R1361

4

0_0402_5%

<41>

SUSP#

1

1

D

+1.5V_CPU_VDDQ

+1.5V

+1.5V_CPU_VDDQ

Q208A
2N7002DW-T/R7_SOT363-6

2

R133
0_0402_5%

<6,45>

RUN_ON_CPU1.5VS3#

0.1U_0603_50V7K

1

<39,41,45,50,51,52,57>

2

6

@ R132

2
G
Q8 RUN_ON_CPU1.5VS3#
2N7002E-T1-GE3_SOT23-3

S

C196

330K_0402_1%

Q208B
2N7002DW-T/R7_SOT363-6

5

D

3

CC38
3

2

RUN_ON_CPU1.5VS3#

RUN_ON_CPU1.5VS3

@

C107
2

2

4

1

@

R134
100K_0402_5%

D

0.1U_0402_10V6K

R135
100K_0402_5%

10U_0805_10V4Z

+VSB

R131
220_0402_5%

1
2
3

8
7
6
5

1

+3VALW

C199

0.1U_0402_10V7K

C201

0.1U_0402_10V7K

J3
1
2
1
J2
@ JUMP_43X118
2
1
2
1

2

CPU1.5V_S3_GATE

CC47

0.1U_0402_10V7K

CC48

+1.5VS

@ JUMP_43X118

+1.5V

0.1U_0402_10V7K

R89 CPU
Close to
+GFX_CORE
100_0402_1%

RC118
1K_0402_1%

2

3

VREFDQ_DIMMA_CPU

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

AL1

2

+V_SM_VREF_CNT

CC178

B4
D1

VREFDQ_DIMMA_CPU
VREFDQ_DIMMB_CPU

1

2

3

+V_SM_VREF

@
QC5
1 AP2302GN-HF_SOT23-3

@

QC6
1 AP2302GN-HF_SOT23-3

RC121
1K_0402_1%

R120
0_0402_5%
short@

DRAMRST_CNT

DRAMRST_CNTRL_PCH

<7,26>

0_0402_5%

RC78
@

1

2

VREFDQ_DIMMB_CPU

@

CC57
330U_X_2VM_R6M

3

@ RC84

0_0402_5% short@
0_0402_5%

+

2

+VREF_CB

+V_DDR_REFB

RC80

10A
CC56
10U_0805_6.3V6M

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

CC54
10U_0805_6.3V6M

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

0_0402_5%

0_0402_5% short@

RC119
1K_0402_1%

C

RC79

RUN_ON_CPU1.5VS3

CC55
10U_0805_6.3V6M

DDR3 -1.5V RAILS

+VREF_CA

+V_DDR_REFA

@ RC83

RC122
1K_0402_1%
QC7
1 AP2302GN-HF_SOT23-3

DRAMRST_CNT

check

Confirm QC6, QC7 is low Rdson or not--Joyce 0929

B

M27
M26
L26
J26
J25
J24
H26
H25

6A

+VCCSA

CC43
10U_0603_6.3V6M

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

CC41
10U_0805_6.3V6M

SA RAIL

0_0402_5%

RC77
@

+1.5V_CPU_VDDQ

0_0402_5%

RC76

0.1U_0402_16V4Z

SENSE
LINES
VREF

<54>
<54>

CC42
10U_0805_6.3V6M

VCCSA: 0.675V (Min) ~ 0.9V (Max)

@ 1
+

CC44
330U_X_2VM_R6M

SA: System Agent
(Memory controller, DMI, PCIE controllers, and display engine)

2

@ R92

VCCPLL1
VCCPLL2
VCCPLL3

VCCSA_SENSE

H23
+VCCSA_SENSE

<53>

+VCCSA_SENSE

2

1

+VCCSA

100_0402_1%
VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

C22
C24

@ RC111
0_0402_5%

<53>
<53>

H_VCCSA_VID0
H_VCCSA_VID1

VCCSA_VID Configuration --CPU EDS Page99.

A19

VCCSA_VID[0] output default logic state is low for Sandy Bridge processors

TYCO_2013620-2_IVY BRIDGE

+3VS

2

B6
A6
A2

1.8V RAIL

+

2

Intel future processor compatibility design. --DG1.5 P113

+V_SM_VREF should
have 20 mil trace width

VCC_AXG_SENSE
VSS_AXG_SENSE

CC53
10U_0805_6.3V6M

2

1

CC61
330U_X_2VM_R6M

1

CC60
1U_0402_6.3V6K

2

CC59
1U_0402_6.3V6K

CC58
10U_0805_6.3V6M

1

VCC_AXG_SENSE
VSS_AXG_SENSE

CC40
10U_0805_6.3V6M

1.5A

100_0402_1%

CC52
10U_0805_6.3V6M

RC120
0_0805_5%

AK35
AK34

2

+1.5V_CPU_VDDQ

+1.8VS_VCCPLL

+1.8VS

VAXG_SENSE
VSSAXG_SENSE

R86
1

CC51
10U_0805_6.3V6M

B

VSS_AXG_SENSE

SM_VREF

MISC

C

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

GRAPHICS

33A

+GFX_CORE

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

2

1

POWER

JCPU1G

VCC_AXG_SENSE

CONN@

RC112
10K_0402_5%

@

@

1

RC113
0_0402_5%

A

A

Compal Secret Data

Security Classification
Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

10

of

60

+1.5V

DDR_A_DQS#4
DDR_A_DQS4

B

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5

DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

R68
1
2
10K_0402_5%

2

R67
1
2
10K_0402_5%

1

0.1U_0402_10V6K

2

C161

1

+3VS

C160

A

2.2U_0603_6.3V4Z

DDR_A_D58
DDR_A_D59

205

G2

G1

206

LCN_DAN06-K4526-0101

DDR_A_MA15
DDR_A_MA14

2

1

2

DDR_A_MA11

1

2

C

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDRA_CLK1
DDRA_CLK1#

DDRA_CLK1 <7>
DDRA_CLK1# <7>

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDRA_SCS0#
DDRA_ODT0

DDRA_SCS0# <7>
DDRA_ODT0 <7>

DDRA_ODT1

DDRA_ODT1

1
DDR_A_D36
DDR_A_D37
DDR_A_DM4

DDR_A_D38

2

+1.5V

Layout Note:
Place near JDDRL.203,204

R56
1K_0402_1%

+0.75VS

<7>

1

2

1

+VREF_CA

2
R60
1K_0402_1%

1

2

1

2

1

2

1

2

B

+3VALW

DDR_A_D39

DDR_A_D44
DDR_A_D45

R5536
100K_0402_5%

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

0.75VR_EN#
DDR_A_D52
DDR_A_D53

<52>

DDR_A_DM6

Q5520B

0.75VR_EN

5
DDR_A_D54
DDR_A_D55

<51,53>

R5535 0.75VR_EN
100K_0402_5%

+1.05VSP_PWRGOOD

DDR_A_D60
DDR_A_D61

Q5520A
2N7002DW-T/R7_SOT363-6

DDR_A_DQS#7
DDR_A_DQS7

PM_SMBDATA

+0.75VS

refer to QAL51, need confirm. --Joyce 0929/2011

2
<6,40,43,45>

DDR_A_D62
DDR_A_D63

PM_SMBCLK

2N7002DW-T/R7_SOT363-6

SUSP

SUSP

PM_SMBDATA <12,26,36,39>
PM_SMBCLK <12,26,36,39>

A

0.65A@0.75V

Compal Secret Data
2011/09/23

2012/12/31

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
4

1

DDR_A_MA7

Issued Date

5

1

2

2

Security Classification

CONN@

C140
330U 2V Y D2 LESR9M

<7>

3

DDR_A_D33

DDRA_CKE1

C369
22U_0805_6.3V6M

DDR_A_D32

1
DDRA_CKE1

4

DDR_A_MA13
DDRA_SCS1#

+1.5V

6

DDRA_SCS1#

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRL

DDR_A_D30
DDR_A_D31

1

<7>

+VREF_CB

1

DDR_A_WE#
DDR_A_CAS#

2

2

DDR_A_WE#
DDR_A_CAS#

+VREF_CA

DDR_A_DQS#3
DDR_A_DQS3

1

<7>
<7>

1

C359
1U_0402_6.3V6K

DDR_A_MA10
DDR_A_BS0

@

C152
0.1U_0402_10V6K

DDR_A_BS0

CD15

<7>

DDR_A_D28
DDR_A_D29

C362
1U_0402_6.3V6K

DDRA_CLK0
DDRA_CLK0#

2

C360
1U_0402_6.3V6K

DDRA_CLK0
DDRA_CLK0#

1

DDR_A_DM2
DDR_A_D22
DDR_A_D23

C361
1U_0402_6.3V6K

<7>
<7>

2

10U_0603_6.3V6M

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

0_0402_5%

1

47P_0402_50V8J
C153

DDR_A_MA12
DDR_A_MA9

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

RC82
@

2

2

10U_0603_6.3V6M

DDR_A_BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

0_0402_5%

2

1

C151
0.1U_0402_10V6K

DDR_A_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

RC81
@

2

1

C148

DDRA_CKE0

DDR_A_D20
DDR_A_D21

+V_DDR_REFB

1

C150
0.1U_0402_10V6K

<7>

DDRA_CKE0

+V_DDR_REFA

2

C149
0.1U_0402_10V6K

<7>

DDR_A_D15

1

10U_0603_6.3V6M

DDR_A_D26
DDR_A_D27

+

C147

DDR_A_D24
DDR_A_D25
DDR_A_DM3

1

<7,12>

C146

DDR_A_D18

+1.5V
SM_DRAMRST#

10U_0603_6.3V6M

DDR_A_DQS2
DDR_A_D19

DDR_A_D12
DDR_A_D13

DDR_A_DM1
SM_DRAMRST#
DDR_A_D14

C145

DDR_A_DQS#2

D

Layout Note:
Place near JDDRL
10U_0603_6.3V6M

DDR_A_D16
DDR_A_D17

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7

C144

DDR_A_D10
DDR_A_D11

DDR_A_MA[0..15]

10U_0603_6.3V6M

DDR_A_DQS#1
DDR_A_DQS1

<7>
DDR_A_D4
DDR_A_D5

C143

DDR_A_D9

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]

10U_0603_6.3V6M

DDR_A_D8

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

<7>
<7>

2

DDR_A_D3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C139

DDR_A_DM0
DDR_A_D2

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D[0..63]

2.2U_0603_6.3V4Z

DDR_A_D0
DDR_A_D1

C138

2

0.1U_0402_10V6K

C134

2

1

2.2U_0603_6.3V4Z

1
CD1

2

0.1U_0402_10V6K

C133

1

JDDRLSO-DIMM A
DDR3
1
2

D

C

<7>

3A@1.5V
0.1U_0402_10V6K

1

2
R57
1
2
1K_0402_1%

+V_DDR_REFA

+1.5V

1

2

3

4

5

1K_0402_1%

+1.5V

R55

3

2

SCHEMATICS, MB A8581
Rev
B

4019IE

Friday, August 24, 2012

Sheet
1

11

of

60

DDR_B_WE#
DDR_B_CAS#

<7>

DDRB_SCS1#

DDRB_SCS1#

DDR_B_MA13

DDR_B_D32

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

C186

2

0.1U_0402_10V6K

C185

2.2U_0603_6.3V4Z

2

1

DDR_B_D58
2
1DDR_B_D59
R76
10K_0402_5%

1
R77

2
10K_0402_5%

205

G1

G2

206

C141
330U 2V Y D2 LESR9M

2

DDR_B_D28
DDR_B_D29

2

1

2

1

2

DDR_B_DQS#3
DDR_B_DQS3

C

DDRB_CKE1

DDRB_CKE1

Layout Note:
Place near JDDRH.203 and 204

<7>

+0.75VS

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

1

DDR_B_MA6
DDR_B_MA4

2

DDR_B_MA2

1

2

1

2

1

2

DDR_B_MA0

DDRB_CLK1
DDRB_CLK1#

DDRB_CLK1 <7>
DDRB_CLK1# <7>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDRB_SCS0#
DDRB_ODT0

DDRB_SCS0# <7>
DDRB_ODT0 <7>

DDRB_ODT1

DDRB_ODT1

1

2

+1.5V

RD12
1K_0402_1%

+VREF_CB

1
DDR_B_D36
DDR_B_D37

DDR_B_DM4

2

<7>

1

2

+VREF_CB

RD13
1K_0402_1%
B

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53
DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63
A

PM_SMBDATA <11,26,36,39>
PM_SMBCLK <11,26,36,39>
+0.75VS

PM_SMBDATA
PM_SMBCLK

0.65A@0.75V
LCN_DAN06-K4926-0101
CONN@

Compal Secret Data

Security Classification

2011/09/23

Issued Date

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

1

DDR_B_D30
DDR_B_D31

C168

B

1
DDR_B_DM2
DDR_B_D22
DDR_B_D23

C167

DDR_B_D33

+1.5V

1

DDR_B_WE#
DDR_B_CAS#

2

2

<7>
<7>

1

C370
22U_0805_6.3V6M

DDR_B_MA10
DDR_B_BS0

@

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRH

DDR_B_D20
DDR_B_D21

C184
1U_0603_10V4Z

DDR_B_BS0

2

<7,11>

C183
1U_0603_10V4Z

<7>

SM_DRAMRST#

DDR_B_D14
DDR_B_D15

2.2U_0603_6.3V4Z

DDRB_CLK0
DDRB_CLK0#

DDR_B_DM1
SM_DRAMRST#

0.1U_0402_10V6K

DDRB_CLK0
DDRB_CLK0#

1

DDR_B_D12
DDR_B_D13

C182
1U_0603_10V4Z

DDR_B_MA3
DDR_B_MA1

<7>
<7>

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

@

D

C181
1U_0603_10V4Z

DDR_B_MA8
DDR_B_MA5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2

DDR_B_D6
DDR_B_D7

1

CD28

CD27

0.1U_0402_10V6K

0.1U_0402_10V6K

CD51

RD11
1
2
1K_0402_1%

2.2U_0603_6.3V4Z

DDR_B_BS2
DDR_B_MA12
DDR_B_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

1

2

1

2

1K_0402_1%
DDR_B_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2

CD49

DDRB_CKE0

1

10U_0603_6.3V6M

DDRB_CKE0

2

CD48

C

1

10U_0603_6.3V6M

DDR_B_DM3

2

2

C180
0.1U_0402_10V6K

DDR_B_D25

DDR_B_D26
DDR_B_D27

2

1

C176

DDR_B_D24

2

1

10U_0603_6.3V6M

DDR_B_D19

DDR_B_DQS#0
DDR_B_DQS0

1

C175

DDR_B_D18

DDR_B_D4
DDR_B_D5

+

C179
0.1U_0402_10V6K

DDR_B_DQS2

1

DDR_B_MA[0..15]

C178
0.1U_0402_10V6K

DDR_B_DQS#2

+3VS

DDR_B_DQS#[0..7]

<7>

C177
0.1U_0402_10V6K

DDR_B_D16
DDR_B_D17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C174

DDR_B_D10
DDR_B_D11

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

10U_0603_6.3V6M

DDR_B_D8

DDR_B_DQS#1
DDR_B_DQS1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

10U_0603_6.3V6M

DDR_B_DM0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

C173

DDR_B_D0
DDR_B_D1

DDR_B_D9

<7>

<7>

JDDRH

DDR_B_D2
DDR_B_D3

<7>

DDR_B_DQS[0..7]

C172

2

DDR_B_D[0..63]

10U_0603_6.3V6M

2

1

<7>

<7>

C171

2

1

Layout Note:
Place near JDDRH

+1.5V

3A@1.5V

10U_0603_6.3V6M

1

D

A

+1.5V

+1.5V

+V_DDR_REFB

10U_0603_6.3V6M

RD10

1

2

3

4

5

+1.5V

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

12

of

60

B
UV1A

OPT@ C30
OPT@
C32

11

22

OPT@ C31

1

2

OPT@ C33
OPT@ C35
OPT@ C34
OPT@ C37
OPT@ C36

1
1
1
1
1

2
2
2
2
2

OPT@ C38
C39
OPT@
OPT@ C40
OPT@ C45

11
1
1

22
2
2

OPT@ C46 1
OPT@ C116 1
OPT@ C48 1

2
2
2

OPT@ C213 1

2

OPT@ C226 1
OPT@ C47 1

2
2

2
10K_0402_5%

1 OPT@
RV48

+3VS_DGPU

AJ11
AL13
AK13
AK12

<26> CLK_PCIE_VGA
<26> CLK_PCIE_VGA#
<26>

3

PEG_CLKREQ#

RV36

@

AJ26
AK26

200_0402_1%
PEX_TSTCLK_OUT+
PEX_TSTCLK_OUT-

termination
RV36 default unmount
<28>

AJ12
AP29

@

DACA_RED
DACA_GREEN
DACA_BLUE

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

DACA_HSYNC
DACA_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

AK9
AL10
AL9

1

PWR_GPS_DOWN#
ACIN

1
0_0402_5%

RH172
2

OPT@
1

I2CB_SCL
I2CB_SDA

I2CA_SCL
I2CA_SDA

I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA

VGA_LCD_CLK
VGA_LCD_DATA

R4
R5

I2CB_SCL
I2CB_SDA

T4
T3

猁ㄩ30ohm,

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

AE8
AD7

VID_PLLVDD

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

60mA

4

CV38,CV40 under
GPU
close to ball :
AE8,AD7

2

LV18

OPT@
CV40
0.1U_0402_16V4Z

GND

27MHZ_10PF_7V27000050
OPT@

XTAL_OUTBUFF
XTAL_SSIN

RV52 1

1

EC_SMB_CK2

O

LCD_BLEN

GPIO5

O

GPU Core VID1

GPIO6

O

GPU Core VID2

GPIO7

O

3D Vision

GPIO8

I/O

OVERT

GPIO9

I/O

ALERT

GPIO10

O

MEM_VREF_CTL

GPIO11

O

GPU Core VID0

GPIO12

I

PWR_LEVEL

GPIO13

O

GPU Core VID5

GPIO14

I

HPD_AB

GPIO15

I

HPD_C

GPIO16

O

MEM_VDD_CTL or PSI

GPIO17

I

HPD_D

GPIO18

I

HPD_E

GPIO19

I

HPD_F

1

@ RV35

OPT@
4
QV6B

2

GPIO20

Reserved

GPIO21

Reserved

3

OPT@
2

BLM18PG181SN1D_2P
+1.05VS_DGPU

CV311,
CV310,
LV18
Near GPU

PFH: Pixel-Clock Frequency Hopping Interface.
PFH can be implemented in system software with
NVAPI to reduce interference between graphic
and wireless networking modems.
Refer to SP-04941-001
4

<26,41>

0_0402_5%
I2CS_SCL

+3VS_DGPU

B

LCD_VCC or PSI

GPIO4

2 10K_0402_5%
OPT@
2 10K_0402_5%
OPT@

OPT@
6

I2CS_SCL
DMN66D0LDW-7_SOT363-6
QV6A

1

Issued Date

0_0402_5%
I2CS_SDA
3
EC_SMB_DA2

<26,41>

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@ RV40

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
Document Number
Custom
Date:

A

O

CV47

+3VS_DGPU

I2CS_SDA

LCD_BL_PWM

GPIO3

10P_0402_50V8J

RV45 1

<57>
<57>
<57>
<57>
<57>
<57>

GPU Core VID3

O

拸CV42ㄛCV44

+GPU_PLLVDD

OPT@
CV38
0.1U_0402_16V4Z

IN

XTALIN

3
OPT@

OPT@

10P_0402_50V8J
GPU_VID0
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
GPU_VID5

CV46 1

1M_0402_5%

OUT

CV42, CV43,
CV44
LV10
Near GPU

ESR=0.2

2

22 0_0402_5%
OPT@
OPT@
0_0402_5%
2 0_0402_5%
OPT@
2 0_0402_5%
OPT@
2
OPT@
2 0_0402_5%
OPT@
0_0402_5%

O

GPIO2

DG

猁ㄩ180ohm,

+GPU_PLLVDD

GND

+1.05VS_DGPU

2
1
BLM18PG330SN1D_0603

XTALIN
XTALOUT

N13P-GLP-A1 FCBGA 908P GPU
OPT@

@
RV55
YV1
Crystal

OPT@ LV10
30R@100MHz(ESR=0.5)

CV41 under GPU
close to ball : AD8

XTAL_OUTBUFF
XTAL_SSIN

4

OPT@ 2.2K_0402_5%
OPT@ 2.2K_0402_5%

ESR=0.05

+GPU_PLLVDD

J4
H1

XTAL_OUTBUFF
XTAL_SSIN

PEX_RST_N
PEX_TERMP

+PLLVDD

+PLLVDD

H3
H2

XTAL_IN
XTAL_OUT

RV46
RV47

SM010018510--SM01000FE00-SM010007W00--

+PLLVDD

AD8

PLLVDD

SP_PLLVDD

OPT@ 2.2K_0402_5%
OPT@ 2.2K_0402_5%
OPT@ 2.2K_0402_5%
OPT@ 2.2K_0402_5%

VGA_LCD_CLK
VGA_LCD_DATA

LV10

PEX_WAKE_N

RV41
RV42
RV44
RV43

I2CA/B/C: Master
I2CS: Slaver (for Internal Thermal Sensor)

I2CS_SCL
I2CS_SDA

5

1
1
1
1
1

GPIO1

OPT@ 2.2K_0402_5%

I2CS_SCL
I2CS_SDA

R7
VGA_CRT_CLK
R6
VGA_CRT_DATA
R2
R3

OPT@ 2.2K_0402_5%

RV38
VGA_CRT_CLK
VGA_CRT_DATA

10K_0402_5%

I2CB_SCL
I2CB_SDA

XTALOUT

+3VS_DGPU

<41>

EC_GPS_DOWN#

90mA

2
@ 1
RV159
10K_0402_5%
2
@ 1
RV160
10K_0402_5%
2
@ 1
RV161
10K_0402_5%
2
@ 1
RV162
10K_0402_5%
2 OPT@ 1
RV163
10K_0402_5%
2 OPT@ 1
10K_0402_5%
RV164

RV165
RV166
RV167
RV168
RV169
RV170

<27,41,48>

RV39

AG10
AP9
AP8

+3VS_DGPU

2 OPT@ 1
RV171
10K_0402_5%
2 OPT@ 1
RV172
10K_0402_5%
2 OPT@ 1
10K_0402_5%
RV173
2 OPT@ 1
10K_0402_5%
RV174
2
@ 1
10K_0402_5%
RV175
2
@ 1
10K_0402_5%
RV176

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5

USAGE
GPU Core VID4

@ R270

2
1
R268 OPT@ 0_0402_5%

LV18

VID Default setup is
for boot voltage 0.9V

O

<41,57>

2

TC7SH08FU(TE85L,F)
@ DV6
1
2

2

AM9
AN9

OPT@ 2.49K_0402_1%
PEX_TREMP

PEX_TERMP: used for internal calibration.

I/O

GPIO0

CH751H-40PT_SOD323-2

PLTRST_VGA#

RV37

IN2

OPT@
CV44
22U_0805_6.3V6M

2
2
22
2
22
2
2

IN1

O

PSI: Phase shedding

OPT@
CV310
22U_0805_6.3V6M

1
1
11
1
11
1
1

UV2

4

GPS_DOWN#

@
1
0_0402_5% 2 R266
+3VS_DGPU
0_0402_5% 2 R267
1
@

@
CV42
4.7U_0402_6.3V6M
OPT@
CV43
22U_0805_6.3V6M

OPT@ C21
OPT@ C22
OPT@ C23
C24
OPT@ C25
OPT@
C28
OPT@ C26
OPT@ C29
OPT@ C27

0.1U_0402_16V7K
PCIE_GTX_CRX_P15
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_N15
0.1U_0402_16V7K PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
0.1U_0402_16V7K PCIE_GTX_CRX_P13
0.1U_0402_16V7K PCIE_GTX_CRX_N13
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_P12
0.1U_0402_16V7K PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P11
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_N11
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_CRX_N9
0.1U_0402_16V7K PCIE_GTX_CRX_P8
0.1U_0402_16V7K PCIE_GTX_CRX_N8
0.1U_0402_16V7K PCIE_GTX_CRX_P7
0.1U_0402_16V7K PCIE_GTX_CRX_N7
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
0.1U_0402_16V7K PCIE_GTX_CRX_P5
0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_N5
0.1U_0402_16V7K PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
0.1U_0402_16V7K PCIE_GTX_CRX_P3
0.1U_0402_16V7K PCIE_GTX_CRX_N3
0.1U_0402_16V7K
PCIE_GTX_CRX_P2
0.1U_0402_16V7K PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
0.1U_0402_16V7K
PCIE_GTX_CRX_N1
0.1U_0402_16V7K PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0

GPIO

+3VS_DGPU

OPT@
CV41
0.1U_0402_16V4Z

PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0

2
22
2
2

1
11
1
1

OPT@ C16
OPT@
C20
OPT@ C17
OPT@ C18
OPT@ C19

OPT@ 330K_0402_5%

CV311
4.7U_0402_6.3V6M

2

PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

RH168

+3VS_DGPU

OPT@

PCIE:80ohm+_10%
45~50ohm+_10%

OPT@10K_0402_5%
10K_0402_5%
OPT@

5

PCIE_CTX_C_GRX_N[0..15]

1

RV30
RV29

P

PCIE_CTX_C_GRX_P[0..15]

G

PCIE_CTX_C_GRX_N[0..15]

P6
M3
L6
P5
P7 VID_4
L7 VID_3
M7
N8
M1
M2 VID_1
L1 VID_2
M5
N3
M4
N4
P2 VID_0
R8 GPS_DOWN#
M6 VID_5
R1
P3
P4
P1

3

PCIE_CTX_C_GRX_P[0..15]

<5>

PCIE_GTX_C_CRX_N[0..15]

GPIO

<5>

PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_GTX_C_CRX_P[0..15]

DACs

PCIE_GTX_C_CRX_N[0..15]

I2C

PCIE_GTX_C_CRX_P[0..15]

<5>

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

E

D

C

Part 1 of 7

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PCI EXPRESS

<5>

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

CLK

A

C

D

SCHEMATICS, MB A8581
Rev
B

4019IE

Friday, August 24, 2012

Sheet
E

13

of

60

A

<20>

MDC[15..0]

MDA[31..16]

MDA[15..0]

<20>

MDC[31..16]

<19>

MDA[47..32]

MDA[31..16]

<21>

MDC[47..32]

MDC[47..32]

<19>

MDA[63..48]

MDA[47..32]

<21>

MDC[63..48]

MDC[63..48]

<18>

DQMA[3..0]

<19>

DQMA[7..4]

<18>

DQSA[3..0]

<19>

<18>

<19>

DQSA[7..4]

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

DQSA#[3..0]

DQSA#[7..4]

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

M31
G31
E33
M33
AE31
AK30
AN33
AF33
M30
H30
E34
M34
AF30
AK31
AM34
AF32

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

N13P-GLP-A1 FCBGA 908P GPU
OPT@

FB_CLAMP

FB_DLL_AVDD

CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

R32
AC32

RV57, RV58, RV59, RV60 change BS from
"OPT@"
"@".--Design Guide. Joyce 1018
2
RV57
@ to 160.4_0402_1%
+1.5VSDGPU

R28
AC28
FBA_DEBUG0
FBA_DEBUG1

2
RV59

R30
R31
AB31
AC31

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

1
60.4_0402_1%

CLKA0 <18>
CLKA0# <18>
CLKA1 <19>
CLKA1# <19>

FB_CLAMP:
Leave as NC for N13P-PES/-GL/-GLP/-NS1
and N13M-GE1/NS1;
Pull down with a 10K on N13P-GV, N13M-GS,
N13E-GE,N13P-GT/-GS/-LP and N14-Q1/-Q3.

@

E1

@

<20>

DQMC[3..0]

<21>

DQMC[7..4]

<20>

RV152
10K_0402_5%

<21>

K27

DQSC[3..0]

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

DQSC[7..4]

+FB_PLLAVDD

35mA

FBA_PLL_AVDD

U27

+FB_PLLAVDD

66mA
FB_VREF

H26

CV49
0.1U_0402_16V4Z

CV49 Under GPU
close to ball : U27

<20>

DQSC#[3..0]

<21>

DQSC#[7..4]

MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

E11
E3
A3
C9
F23
F27
C30
A24

D10
D5
C3
B9
E23
E28
B30
A23

D9
E4
B2
A9
D22
D28
A30
B23

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_CMD_RFU0
FBB_CMD_RFU1

FBB_DEBUG0
FBB_DEBUG1

FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

C12
C20

2RV58

G14
G20
FBB_DEBUG0
FBB_DEBUG1
D12
E12
E20
F20

2
RV60

@ 1 60.4_0402_1%
+1.5VSDGPU
1

@

60.4_0402_1%

CLKC0 <20>
<20>
CLKC0#
CLKC1 <21>
<21>
CLKC1#

F8
E8
A5
A6
D24
D25
B27
C27

1

+FB_PLLAVDD

300mA

+FB_PLLAVDD

FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

D6
D7
C6
B6
F26
E26
A26
A27

1

2

LV11 OPT@ +1.05VS_DGPU
2
1
MPZ1608S300AT 0603

30ohm@100M // ESR=0.01
SM01000EQ00-SM010031100--

FBB_PLL_AVDD

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

H17
+FB_PLLAVDD

66mA

+FB_PLLAVDD

CV48 Under GPU
close to ball : H17

N13P-GLP-A1 FCBGA 908P GPU
OPT@

CV50 Under GPU
close to ball : K27

<20,21>

CMDC[30..0]
CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30

OPT@

FBA_DEBUG0
FBA_DEBUG1

CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

FBB_PLL_AVDD Design Guide:
100nF

X7R 0402

1pcs per pin

22uF X5R 0805 1pcs per pin

under GPU

Near GPU

bead--30ohm@100MHz (ESR=0.01ohm) 0603 1pcs

Issued Date

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
Document Number
Custom
Date:

A

Near GPU

Compal Electronics, Inc.

Compal Secret Data

Security Classification

4019IE

SCHEMATICS, MB A8581

Friday, August 24, 2012

Sheet

14

of

60

Rev
B

CV53
1U_0402_6.3V6K

FBA_CMD_RFU0
FBA_CMD_RFU1

AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55

OPT@ CV52

MEMORY INTERFACE
A

FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

<18,19>

22U_0805_6.3V6M

P30
F31
F34
M32
AD31
AL29
AM32
AF34

FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20

Y32
AA31
AA29
AA28
AC34
AC33

CMDA[30..0]

OPT@ CV51

MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

FBA_CMD15
FBA_CMD16

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33

OPT@
CV50
0.1U_0402_16V4Z

1

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14

OPT@

Part 2 of 7

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE B

Part 3 of 7

UV1B

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55

MDC[31..16]

UV1C

MDA[63..48]

L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

MDC[15..0]

<18>

1U_0402_6.3V6K

VRAM Interface

MDA[15..0]

OPT@
CV48
0.1U_0402_16V4Z

<18>

1

2

3

4

5

UV1D

MULTI LEVEL STRAPS

Part 4 of 7

AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

C

AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

GND_SENSE

AK3
AK2
AB3
AB4

L4

L5

RV177

1

2 0_0402_5%
OPT@

RV178

1

2 0_0402_5%
OPT@

RV88

VCCSENSE_VGA

<57>

VSSSENSE_VGA

<57>

1
1

1
@

@
2

@

4.99K_0402_1%

4.99K_0402_1%

2

2

1

1

1

D

RV77

RV78

RV79

10K_0402_1%

15K_0402_1%

@
45.3K_0402_1%

2

2

4.99K_0402_1%

ROM_SI
ROM_SO
ROM_SCLK

STRAP3
STRAP4

RV71

RV70

2

10K_0402_1%

4.99K_0402_1%

30K_0402_1%

1
2
@ RV76
20K_0402_1%

RV74

1
2
@ RV75
4.99K_0402_1%

2

1

4.99K_0402_1%

@

2

2

45.3K_0402_1%

@

2

@

2

1

RV73

1

1
2
RV67
34.8K_0402_1%

1

1
1

2

4.99K_0402_1%

RV69

X76-

10K_0402_5%
+3VS_DGPU

TESTMODE

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

DG:

AK11

AM10
AM11
AP12
AP11
AN11

啎啎RV88 for XOR tree testing. --Joyce 1026
RV82
RV83

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

OPT@ 10K_0402_5%
OPT@ 10K_0402_5%
PAD TV1
PAD TV2
PAD TV3
PAD TV4

Physical
strapping pin

Logical
Strapping Bit3

Logical
Strapping Bit2

Logical
Strapping Bit1

Logical
Strapping Bit0

@
@

ROM_SCLK

PCI_DEVID[4]

SUB_VENDOR

SLOT_CLK_CFG

PEX_PLL_EN_TERM

@
@

ROM_SI

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

OPT@
10K_0402_5%
RV84

SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO

H6
H4
H5
H7

RV85 10K_0402_5%
OPT@

ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO

FB [1]

STRAP0

USER [3]

STRAP1

3GIO_PAD_CFG_ADR[3]

STRAP2

+3VS_DGPU

FB [0]

SMB_ALT_ADDR

USER [2]

PCI-DEVID [3]

Pull down
to GND

1000

0000

10K

1001

0001

15K

1010

0010

20K

1011

0011

25K

1100

0100

30K

1101

0101

35K

1110

0110

45K

1111

0111

USER [0]

3GIO_PAD_CFG_ADR[1]

PCI-DEVID [2]

Pull up
to 3V

5K

VGA_DEVICE

USER [1]

3GIO_PAD_CFG_ADR[2]

Resistor
Values

C

3GIO_PAD_CFG_ADR[0]

PCI-DEVID [1]

PCI-DEVID [0]

STRAP3

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

STRAP4

RESERVED

PCIE_SPEED_
CHANGE_GEN3

PCIE_MAX_SPEED

DP_PLL_VDD33V

ROM support: 512Kbit or greater, up to 50MHz.
CEC: Place a 10K pull up resistor to 3.3V on
N13P-PES/-GL/-GLP/-NS1 and N13M-NS1

GENERAL
BUFRST_N
CEC

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

@

L2

10K_0402_5%

PEX_PLL_EN_TERM:
PLL termination setting

0

No VBIOS ROM

1

BIOS ROM is present (Default)

0
1

PCIE_MAX_SPEED

Disable (Default)
Enable

0

Limited to PCIE GEN 1

1

PCIE GEN 2/3 capable

+3VS_DGPU

J1
MULTI_STRAP_REF0_GND

J2
J7
J6
J5
J3

SUB_VENDOR

RV153 10K_0402_5%

OPT@ RV86

L3

2
1
OPT@ RV87 40.2K_0402_1%

FB [1:0]: N13x FB Aperture Size

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

0

RESERVED

1

RESERVED

2

256 MB (Default)

3

RESERVED

USER Straps

THERMDP
THERMDN

B

AF3
AF2

STRAP0
STRAP1
STRAP2

@

MULTI_STRAP_REF0_GND
AG3
AG2

Straps

45.3K_0402_1%

RV68

@

RV66

RV65
RV64

@

VDD_SENSE

TEST

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

@

TV5

RV72

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

PAD

1

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

+3VS_DGPU

+3VS_DGPU

P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

2

AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

D

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

LVDS/TMDS

AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6

K3
K4

1111

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

EDID is used

B

others: DG-05587 Page195
3GIO_PAD_CFG

N13P-GLP-A1 FCBGA 908P GPU
OPT@

0000--0101

RESERVED

0110

Notebook (default)

0111--1111

RESERVED

For N13P-GLP strap table
For N13P-PES :
Strap 0 : PU45
Strap 1 : PD35
Strap 2 : PU35
ROM_SCLK : PU15
ROM_SI : PD35
ROM_SO : PD10

A

GPU

Frenq.

Memory Config

strap0

strap1

strap2

strap3

strap4

ROM_SI

ROM_SO

64M* 16* 8
1GB

Hynix
SA000041S20

RV64
PU 45K

RV73
PD 45K

RV74
PU 5K

NC

NC

RV77
PD 15K

RV70
PD 30K

RV71
PD 15K

900 MHz

64M* 16* 8
1GB

Samsung
SA00004GS00

RV64
PU 45K

RV73
PD 45K

RV74
PU 5K

NC

NC

RV77
PD 20K

RV70
PD 30K

RV71
PD 15K

900 MHz

128M* 16* 8
2GB

Hynix
SA00003YO00

RV64
PU 45K

RV73
PD 45K

RV74
PU 5K

NC

NC

RV77
PD 35K

RV70
PD 30K

RV71
PD 15K

900 MHz

128M* 16* 8
2GB

Samsung
SA000047Q00

RV64
PU 45K

RV73
PD 45K

RV74
PU 5K

NC

NC

RV77
PD 45K

RV70
PD 30K

RV71
PD 15K

2012/12/31

Deciphered Date

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

4

3

A

Compal Electronics, Inc.

Compal Secret Data
2011/09/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

ROM_SCLK

N13P-GLP

Security Classification
Issued Date

Memory Size

900 MHz

2

4019IE

Friday, August 24, 2012

Sheet
1

15

Rev
B
of

60

+1.5VSDGPU

DDR3

GDDR5

FB_CAL_PD_VDDQ

40.2ohm

40.2ohm

FB_CAL_PU_GND

42.2ohm

40.2ohm

FB_CAL_TERM_GND

51.1ohm

60.4ohm

H27
H25

IFPC_IOVDD

IFPD_PLLVDD
IFPD_RSET
IFPD_IOVDD

IFPE_IOVDD
IFPF_IOVDD

@

RV94

OPT@

CV60
22U_0805_6.3V6M

OPT@

CV59
22U_0805_6.3V6M

OPT@

OPT@

CV68
22U_0805_6.3V6M

OPT@

CV78
22U_0805_6.3V6M

OPT@

CV77
10U_0603_6.3V6M

OPT@

CV67
10U_0603_6.3V6M

CV76
4.7U_0603_6.3V6K
OPT@

CV82
4.7U_0603_6.3V6K

CV81
4.7U_0603_6.3V6K
OPT@

OPT@

CV88
1U_0402_6.3V6K

CV89
4.7U_0603_6.3V6K

OPT@

OPT@

1K_0402_5%

CV97
4.7U_0603_6.3V6K

RV89

+3VS_DGPU

0_0603_5%

AF6
+IFPC_IOVDD

AG7
AN2

+IFPD_PLLVDD

AG6
+IFPD_IOVDD

FB_CAL_TERM_GND
IFPEF_PLVDD
IFPEF_RSET

1OPT@ RV922 10K_0402_5%

OPT@

+IFPC_PLLVDD

C

LV12 stuff a 0ohm resistor instead for
N13E-GE, N13P-GT/-GS/-LP/-GV, N13M-GS,
N14P-Q1/-Q3

Under GPU

2 10K_0402_5%
1OPT@ RV104

AF7
AF8

+1.05VS_DGPU

猁:120ohm@100MHz, ESR=0.18ohm 0603
OPT@

2 10K_0402_5%
1OPT@ RV102
@ RV90 1K_0402_5%
+IFPAB_PLLVDD
+IFPAB_IOVDD

420mA

LV12

Design guide no define

AG8
AG9

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

CV58
10U_0603_6.3V6M

CV57
10U_0603_6.3V6M
OPT@
OPT@

120mA

LV12
2
1
BLM18PG121SN1D_0603
OPT@

CV96
1U_0402_6.3V6K

+VDD33

Near GPU

OPT@

IFPC_PLLVDD
IFPC_RSET

FB_GND_SENSE

J27

2 OPT@ 1
51.1_0402_1%
RV101
FB_CAL_TERM_GND

Under GPU

150mA

FB_VDDQ_SENSE

F2

2 OPT@ 1
FB_CAL_PD_VDDQ
40.2_0402_1%
RV96
2 OPT@ 1
RV98
42.2_0402_1%
FB_CAL_PU_GND

210mA
OPT@
0.1U_0402_16V4Z

+PEX_PLLVDD

OPT@

F1

CV80,CV198 Under GPU
close to ball
@
210mA
0.1U_0402_16V4Z

CV80

AG26

AH8
AJ8

D

+3VS_DGPU

CV95
1U_0402_6.3V6K

2 OPT@
RV93

IFPA_IOVDD
IFPB_IOVDD

2

Near GPU

AG12

J8
K8
L8
M8

1

CV92
0.1U_0402_16V4Z
OPT@

VDD33_0
VDD33_1
VDD33_2
VDD33_3

2

CV91
0.1U_0402_16V4Z

+1.5VSDGPU

1
10_0402_5%
FB_VDDQ_SENSE
1
10_0402_5%
FB_GND_SENSE

AH12

1

PEX_PLL_HVDD:
N13P-GLP/PES :NC
N13P-LP : power.

CV198
PEX_PLLVDD

IFPAB_PLLVDD
IFPAB_RSET

2 OPT@
RV91

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

Near GPU

OPT@

PEX_SVDD_3V3

+1.05VS_DGPU

Under GPU

3300 mA

OPT@

PEX_PLL_HVDD

2

CV75
1U_0402_6.3V6K

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

AG19
AG21
AG22
AG24
AH21
AH25

OPT@

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

CV87
0.1U_0402_16V4Z

2

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

1

OPT@

1

CV86
10U_0603_6.3V6M

2

CV85
10U_0603_6.3V6M
OPT@

2

1

C

Calibration Pin

2

CV90
0.1U_0402_16V4Z

CV73
0.1U_0402_16V4Z

OPT@

OPT@

OPT@
CV72
0.1U_0402_16V4Z

CV71
0.1U_0402_16V4Z

CV79
0.1U_0402_16V4Z

OPT@

CV70
1U_0402_6.3V6K

OPT@

OPT@
CV69
4.7U_0603_6.3V6K
1

CV84
10U_0603_6.3V6M
OPT@

OPT@

CV83
10U_0603_6.3V6M
OPT@

Near GPU

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

CV74
1U_0402_6.3V6K

7200mA

POWER

OPT@
CV66
0.1U_0402_16V4Z

OPT@
CV65
0.1U_0402_16V4Z

OPT@
CV64
0.1U_0402_16V4Z

OPT@
CV63
0.1U_0402_16V4Z

OPT@
CV61
4.7U_0603_6.3V6K

OPT@
CV62
1U_0402_6.3V6K

Under GPU

Under GPU

2

1

Part 5 of 7

+1.5VSDGPU

1

OPT@
CV56
4.7U_0603_6.3V6K

UV1E

+1.05VS_DGPU

Near GPU

OPT@
CV54
1U_0402_6.3V6K

Design guide no define

D

OPT@
CV55
1U_0402_6.3V6K

Under GPU

FBVDDQ Decouping Design Guide:
0.1uF X7R 0402 8pcs under GPU
1uF
X7R 0603 2pcs under GPU
4.7uF X6S 0603 2pcs under GPU
10uF X5R 0805 4pcs Near GPU

1

2

3

4

5

AB8
AD6

1OPT@ RV952 10K_0402_5%

1OPT@ RV972 10K_0402_5%
@ RV99 1K_0402_5%
2 10K_0402_5%
1OPT@ RV100

2 10K_0402_5%
1OPT@ RV114
+IFPEF_PLLVDD

AC7
AC8
+IFPEF_IOVDD

@
RV103 1K_0402_5%
2 10K_0402_5%
1OPT@ RV126
B

B

PEX_IOVVD/Q
N13P-GLP-A1 FCBGA 908P GPU
OPT@

Near GPU
+3VS_DGPU LV7
2
1
BLM18PG181SN1D_0603
@

Under GPU
0.1U_0402_16V4Z

1U_0402_6.3V4Z

+IFPC_PLLVDD

1

300ohm 100MHz,

ESR=0.25ohm
2

CV203
@

2

CV199
@

4.7U_0603_6.3V6K

LV13
+1.05VS_DGPU
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
@

A

220ohm 100MHz,

1

ESR=0.05ohm
2

2

1

1

1

1

CV200
@

2

CV202
@

2

110mA

CV215
0.1U_0402_16V4Z
@

+IFPC_IOVDD

1

2

CV201
@

2

CV204
@

1

2

0402

4

Under GPU

X6S

0603

2

Near GPU

10uF

X5R

0805

4

Midway between GPU and Power Supply

22uF

X5R

0805

4

Midway between GPU and Power Supply

Capacitor Type Footprint

Population Location

100nF

X6S

0402

1

Under GPU

1.0uF

X5R

0603

1

Near GPU

4.7uF

X5R

0805

1

Near GPU

PEX_SVDD/PLL_HVDD

50mA

0.1U_0402_16V4Z
1

CV205
@

Population Location

X6S

4.7uF

PEX_PLLVDD

0.1U_0402_16V4Z

Under GPU(below 150mils)

Capacitor Type Footprint
1.0uF

CV206
0.1U_0402_16V4Z
@

Capacitor Type Footprint

Population Location

0.1uF

X5R

0402

1

Near GPU

4.7uF

X5R

0603

2

Near GPU

A

1U_0402_6.3V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

5

4

3

2

4019IE

Friday, August 24, 2012

Sheet
1

16

Rev
B
of

60

4

5

1

2

3

UV1F
+VGA_CORE

C

B

A

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32

Part 7 of 7
AA12
AA14 VDD_0
AA16 VDD_1
AA19 VDD_2
AA21 VDD_3
AA23 VDD_4
AB13 VDD_5
AB15 VDD_6
AB17 VDD_7
AB18 VDD_8
AB20 VDD_9
AB22 VDD_10
AC12 VDD_11
AC14 VDD_12
AC16 VDD_13
AC19 VDD_14
AC21 VDD_15
AC23 VDD_16
M12 VDD_17
M14 VDD_18
M16 VDD_19
M19 VDD_20
M21 VDD_21
M23 VDD_22
N13 VDD_23
N15 VDD_24
N17 VDD_25
N18 VDD_26
N20 VDD_27
N22 VDD_28
P12 VDD_29
P14 VDD_30
P16 VDD_31
P19 VDD_32
P21 VDD_33
P23 VDD_34
R13 VDD_35
R15 VDD_36
R17 VDD_37
R18 VDD_38
R20 VDD_39
R22 VDD_40
T12 VDD_41
T14 VDD_42
T16 VDD_43
T19 VDD_44
T21 VDD_45
T23 VDD_46
U13 VDD_47
U15 VDD_48
U17 VDD_49
U18 VDD_50
U20 VDD_51
U22 VDD_52
V13 VDD_53
V15 VDD_54
VDD_55

XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16

XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22

XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30

XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

D

U1
U2
U3
U4
U5
U6
U7
U8

V1
V2
V3
V4
V5
V6
V7
V8

C

W2
W3
W4
W5
W7
W8

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data
2011/09/23

2012/12/31

Deciphered Date

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

4

XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8

V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71

N13P-GLP-A1 FCBGA 908P GPU
OPT@

Security Classification

N13P-GLP-A1 FCBGA 908P GPU
OPT@

+VGA_CORE

UV1G

60A

POWER

D

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

GND

Part 6 of 7

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

3

2

4019IE

Friday, August 24, 2012

Sheet
1

17

Rev
B

of

60

1

2

3

4

5

VRAM DDR3 chips (1GB)

Mode D
Address

0..31

M8
H1

DQSA#[7..0]

DQMA[7..0]

+MEM_VREF0

N3
P7

DQMA[7..0]

MDA[63..0]

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

MDA[63..0]

CMDA[30..0]

CMDA[30..0]

+1.5VSDGPU

OPT@

RV105
1.33K_0402_1%

OPT@

C

OPT@

RV106
1.33K_0402_1%

2

CV109
0.1U_0402_16V4Z

+MEM_VREF0
1

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

J7
K7
K9

CLKA0
CLKA0#
CMDA3

K1
L2
J3
K3
L3

OPT@

CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

RV107
1.33K_0402_1%

F3
C7

DQSA1
DQSA2

OPT@

RV108
1.33K_0402_1%

2

CV110
0.1U_0402_16V4Z

OPT@

+MEM_VREF1
1

E7
D3

DQMA1
DQMA2

G3
DQSA#1
DQSA#2

B7

T2
CMDA5

CLKA0

1
RV110
243_0402_1%

RV15
160_0402_1%

L8

ZQ0

J1
L1
J9
L9

2

OPT@ 1

CLKA0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

310mA

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

CLKA0#

CLKA0#

2
RV118
@
80.6_0402_1%

1

2

D7
C3
C8
C2
A7
A2
B8
A3

MDA12
MDA14
MDA8
MDA15
MDA9
MDA13
MDA10
MDA11

swap 0329

MDA17
MDA21
MDA18
MDA23
MDA19
MDA22
MDA16
MDA20

+MEM_VREF1

N3
P7

X76@

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

Group1

Group2

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKA0
CLKA0#
CMDA3

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ

J7
K7
K9

K1
L2
J3
K3
L3

CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

E9
F1
H2
H9

@
CV111
0.01U_0402_16V7K

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

ODT/ODT0

DQSL
DQSU

E7
D3

DQMA0
DQMA3

G3
B7

DQSA#0
DQSA#3

T2
L8

CMDA5

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV111
243_0402_1%

Group3

+1.5VSDGPU

+1.5VSDGPU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ODT_L

CMD3

CKE

CMD4

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

CMD15

CAS*

A14

A15
CAS*
CS0_H#
C

CMD17

E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ

CMD2

CMD16

A1
A8
C1
C9
D2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

Group0

MDA27
MDA29
MDA25
MDA30
MDA24
MDA28
MDA26
MDA31

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

MDA3
MDA4
MDA2
MDA7
MDA0
MDA5
MDA1
MDA6

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

310mA

DQSA0
DQSA3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

A0
A1

CS/CS0
RAS
CAS
WE

F3
C7

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

M2
BA0
N8
M3 BA1
BA2

CMDA12
CMDA27
CMDA26

A1
A8
C1
C9
D2

VREFCA
VREFDQ

CMD18

ODT_H

CMD19

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

B

ZQ1

1
<14>

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

<14>

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M8
H1

E3
F7
F2
F8
H3
H8
G2
H7

1

2
RV109
@
80.6_0402_1%

1

OPT@

B

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

M2
N8
M3

CMDA12
CMDA27
CMDA26

+1.5VSDGPU

X76@

VREFCA
VREFDQ

J1
L1
J9
L9

OPT@

<14,19>

<14,19>

UV3

DQSA[7..0]

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

<14,19>

DQSA[7..0]

DQSA#[7..0]

D

CMD1

UV4
<14,19>

<14,19>

32..63

CS0_L#

CMD0

64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB

D

2 10K_0402_5%

RV112 1 OPT@

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

RV115 1 OPT@ 2 10K_0402_5%
1 OPT@
RV113
2 10K_0402_5%
1 OPT@2 10K_0402_5%
RV116

CMDA2
CMDA3
CMDA5
CMDA18
CMDA19

RV117 1 OPT@

Command Bit

2 10K_0402_5%

Default Pull-down

ODTx

10k
10k

CKEx

DDR3

RST
CS*

10k
No Termination

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

NV recommand 0720

+1.5VSDGPU

OPT@
CV138
1U_0402_6.3V6K

OPT@
CV137
1U_0402_6.3V6K

OPT@
CV136
1U_0402_6.3V6K

2

OPT@
CV135
1U_0402_6.3V6K

1

OPT@ CV134
0.1U_0402_16V4Z

2

OPT@ CV130
0.1U_0402_16V4Z

1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

OPT@
CV129
1U_0402_6.3V6K

2

OPT@
CV128
1U_0402_6.3V6K

1

OPT@
CV127
1U_0402_6.3V6K

2

close to UV4
OPT@ CV125
0.1U_0402_16V4Z
OPT@
CV126
1U_0402_6.3V6K

OPT@
CV123
1U_0402_6.3V6K

OPT@
CV121
1U_0402_6.3V6K
OPT@
CV122
1U_0402_6.3V6K

2

1

OPT@
CV120
1U_0402_6.3V6K

1

OPT@ CV119
0.1U_0402_16V4Z

2

OPT@ CV118
0.1U_0402_16V4Z

1
OPT@
CV117
1U_0402_6.3V6K

OPT@
CV116
1U_0402_6.3V6K

OPT@
CV115
1U_0402_6.3V6K

2

OPT@
CV114
1U_0402_6.3V6K

A

1

OPT@ CV113
0.1U_0402_16V4Z

2

OPT@ CV112
0.1U_0402_16V4Z

close to UV3
1

OPT@ CV124
0.1U_0402_16V4Z

+1.5VSDGPU

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

5

4

3

2

4019IE

Friday, August 24, 2012

Sheet
1

18

Rev
B
of

60

1

2

3

4

5

VRAM DDR3 chips (1GB)

Mode D
Address

64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB
DQMA[7..0]

<14,18>

CMDA[30..0]

<14,18>

<14,18>
<14,18>

DQMA[7..0]

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

CMDA[30..0]

DQSA#[7..0]

DQSA#[7..0]

DQSA[7..0]

DQSA[7..0]

MDA[63..0]

MDA[63..0]

OPT@

+1.5VSDGPU

RV119
1.33K_0402_1%

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

CMDA12
CMDA27
CMDA26

OPT@

RV120
1.33K_0402_1%
C

CV131
0.1U_0402_16V4Z

OPT@

+MEM_VREF2
1

2

CLKA1
CLKA1#
CMDA19

CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

+1.5VSDGPU

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

DQSA4
DQSA7

OPT@

E7
D3

RV121
1.33K_0402_1%

DQMA4
DQMA7

G3

2

DQSA#4
DQSA#7

T2
L8

CMDA5

1

OPT@

RV122
1.33K_0402_1%

CV132
0.1U_0402_16V4Z

OPT@

1
+MEM_VREF3

<14>

OPT@ 1

CLKA1

2
1
RV125
@
80.6_0402_1%
RV16
160_0402_1%

2
RV127
@
80.6_0402_1%

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
DQSL
310mA VDDQ
VDDQ
DQSU

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2

UV6

M8
H1

MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34

+MEM_VREF3

MDA61
MDA59
MDA60
MDA57
MDA63
MDA56
MDA62
MDA58

N3
P7

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

Group4

Group7

+1.5VSDGPU

1

2

MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44
MDA42

Group5

MDA53
MDA49
MDA55
MDA50
MDA52
MDA48
MDA54
MDA51

Group6

+1.5VSDGPU

J7
K7
K9

310mA

F3
C7

DQSA5
DQSA6

DQSL
DQSU

E7
D3

DQMA5
DQMA6

G3
DQSA#5
DQSA#6

DQSL

B7

DQSU

T2
CMDA5

RESET

L8

ZQ/ZQ0

ZQ3

B1
B9
D1
D8
E2
E8
F9
G1
G9

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

A14

CAS*
CS0_H#
C

ODT_H
CKE_H

CMD19

A9
VSS B3
VSS E1
VSS
G8
VSS J2
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VSS

DML
DMU

CKE

CMD4

CMD18

E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ

ODT_L

CMD3

CMD17

A1
A8
C1
C9
D2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CS/CS0
RAS
CAS
WE

D

CMD2

CMD16
+1.5VSDGPU

ODT/ODT0

L2
J3
K3
L3

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

K1
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M2
BA0
N8
M3 BA1
BA2

CLKA1
CLKA1#
CMDA19

E9
F1
H2
H9

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1

P3
N2 A2
P8 A3
P2 A4
R8 A5
R2 A6
T8 A7
R3 A8
L7 A9
R7 A10/AP
N7 A11
T3 A12
T7 A13
M7 A14
A15/BA3

CMDA12
CMDA27
CMDA26

+1.5VSDGPU

X76@

VREFCA
VREFDQ

RV124
243_0402_1%

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

1
CLKA1#

CLKA1#

J1
L1
J9
L9

VREFCA
VREFDQ

CLKA1

2
<14>

2
OPT@

ZQ2
RV123
243_0402_1%

B

B7

32..63

CS0_L#

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

1

<14,18>

N3
P7

OPT@

M8
H1
+MEM_VREF2

0..31

CMD1

2

D

CMD0
X76@

UV5

Not Available

B

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

@
CV133
0.01U_0402_16V7K

NV recommand 0720

+1.5VSDGPU

OPT@
CV158
1U_0402_6.3V6K

OPT@
CV157
1U_0402_6.3V6K

OPT@
CV156
1U_0402_6.3V6K

2

OPT@
CV152
1U_0402_6.3V6K

1

OPT@ CV151
0.1U_0402_16V4Z

2

OPT@ CV165
0.1U_0402_16V4Z

1

OPT@
CV164
1U_0402_6.3V6K

2

OPT@
CV163
1U_0402_6.3V6K

1

OPT@
CV162
1U_0402_6.3V6K

close to UV6
OPT@ CV160
0.1U_0402_16V4Z
OPT@
CV161
1U_0402_6.3V6K

2

OPT@ CV159
0.1U_0402_16V4Z

OPT@
CV143
1U_0402_6.3V6K

2

1
OPT@
CV142
1U_0402_6.3V6K

2

1

OPT@
CV140
1U_0402_6.3V6K
OPT@
CV141
1U_0402_6.3V6K

1

OPT@ CV150
0.1U_0402_16V4Z

OPT@
CV149
1U_0402_6.3V6K

OPT@
CV148
1U_0402_6.3V6K

OPT@
CV147
1U_0402_6.3V6K

2

OPT@
CV146
1U_0402_6.3V6K

2

1

OPT@ CV145
0.1U_0402_16V4Z

1

OPT@ CV144
0.1U_0402_16V4Z

close to UV5

OPT@ CV139
0.1U_0402_16V4Z

+1.5VSDGPU

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

5

4

3

2

4019IE

Friday, August 24, 2012

Sheet
1

19

Rev
B
of

60

1

2

3

4

5

Mode D
Address

VRAM DDR3 chips (1GB)

0..31

CMD0

32..63

CS0_L#

CMD1

64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB
DQSC[7..0]

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7
E7
D3

B7

T2
L8

2
OPT@

RV151
243_0402_1%

B

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

2
RV139
@
80.6_0402_1%

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2
RV141
@
80.6_0402_1%
@
CV155
0.01U_0402_16V7K

1

G3
B7

DQSC#0
DQSC#3

T2
L8

CMDC5

ZQ5

RV133
243_0402_1%

J1
L1
J9
L9

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

A7

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

CMD15

CAS*

A15
CAS*
CS0_H#
ODT_H

CMD19

+1.5VSDGPU

C

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A9

A7

CMD8

CMD18

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9

CMD7

CMD17

E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ

CMD6

CMD16

+1.5VSDGPU

2 10K_0402_5%
2 10K_0402_5%

RV134 1 OPT@
RV135 1 OPT@
CMDC2
CMDC3
CMDC5
CMDC18
CMDC19

RV136 1 OPT@

B

Command Bit

2 10K_0402_5%

Default Pull-down
10k

ODTx

RV137
OPT@ 2 2 10K_0402_5%
10K_0402_5%
RV1381 1OPT@
DDR3

10k

CKEx
RST

10k

CS*

No Termination

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

close to UV7
1

2

OPT@
CV174
1U_0402_6.3V6K

2
NV recommand 0720

DQMC0
DQMC3

B1
B9
D1
D8
E2
E8
F9
G1
G9

DQSL
DQSU

A1
A8
C1
C9
D2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5VSDGPU

1

OPT@ CV172
0.1U_0402_16V4Z

CLKC0#

CLKC0#

E7
D3

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

OPT@
CV173
1U_0402_6.3V6K

1

CLKC0

RV17
160_0402_1%
1

OPT@ CV171
0.1U_0402_16V4Z

<14>

CLKC0

2OPT@

1
<14>

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

F3
C7

ODT/ODT0
CS/CS0
RAS
CAS
WE

310mA

DQSC0
DQSC3

1

ZQ4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E9
F1
H2
H9

K1
L2
J3
K3
L3

RST

close to UV8
1

2

1

2

1

2

1

2

1

2

1

2

OPT@
CV185
1U_0402_6.3V6K

CMDC5

DML
DMU

VDDQ
VDDQ
VDDQ
VDDQ

CMDC2
CMDC0
CMDC30
CMDC15
CMDC13

A14

RST

OPT@
CV184
1U_0402_6.3V6K

DQSC#1
DQSC#2

1

2

G3

CV154
0.1U_0402_16V4Z

OPT@

+MEM_VREF5
1

OPT@

RV131
1.33K_0402_1%

DQSL
DQSU

310mA

A1
A8
C1
C9
D2

A14

CMD5

OPT@
CV183
1U_0402_6.3V6K

DQMC1
DQMC2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

Group3

D

CKE

CMD4

OPT@
CV182
1U_0402_6.3V6K

DQSC1
DQSC2

+1.5VSDGPU

ODT/ODT0
CS/CS0
RAS
CAS
WE

CK
CK
CKE/CKE0

MDC26
MDC31
MDC25
MDC30
MDC27
MDC28
MDC24
MDC29

ODT_L

CMD3

OPT@ CV181
0.1U_0402_16V4Z

OPT@

RV130
1.33K_0402_1%

CLKC0
CLKC0#
CMDC3

J7
K7
K9

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

Group0

OPT@ CV192
0.1U_0402_16V4Z

+1.5VSDGPU

CMDC12
CMDC27
CMDC26

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDC3
MDC7
MDC1
MDC4
MDC2
MDC6
MDC0
MDC5

OPT@
CV190
1U_0402_6.3V6K
OPT@
CV191
1U_0402_6.3V6K

CMDC2
CMDC0
CMDC30
CMDC15
CMDC13

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

OPT@
CV189
1U_0402_6.3V6K

CLKC0
CLKC0#
CMDC3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

M2
N8
M3

A0
A1

OPT@
CV188
1U_0402_6.3V6K

CMDC12
CMDC27
CMDC26

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VREFCA
VREFDQ

OPT@
CV170
1U_0402_6.3V6K

2

Group2

N3
P7

OPT@
CV169
1U_0402_6.3V6K

OPT@

OPT@

RV129
1.33K_0402_1%

MDC18
MDC20
MDC17
MDC22
MDC16
MDC23
MDC19
MDC21

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

Group1

+1.5VSDGPU

+MEM_VREF4

C

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

+MEM_VREF5

OPT@
CV168
1U_0402_6.3V6K

1

CV153
0.1U_0402_16V4Z

RV128
1.33K_0402_1%

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

swap 0329

OPT@ CV187
0.1U_0402_16V4Z

OPT@

+1.5VSDGPU

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MDC8
MDC12
MDC11
MDC13
MDC9
MDC14
MDC10
MDC15

OPT@ CV186
0.1U_0402_16V4Z

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

CMDC[30..0]

A0
A1

E3
F7
F2
F8
H3
H8
G2
H7

2
OPT@

MDC[63..0]

CMDC[30..0]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

OPT@
CV167
1U_0402_6.3V6K

<14,21>

N3
P7

VREFCA
VREFDQ

OPT@ CV166
0.1U_0402_16V4Z

MDC[63..0]

<14,21>

+MEM_VREF4

DQMC[7..0]

M8
H1

X76@

UV7

M8
H1

DQSC#[7..0]

DQMC[7..0]

OPT@ CV180
0.1U_0402_16V4Z

DQSC#[7..0]

<14,21>

OPT@
CV179
1U_0402_6.3V6K

<14,21>

X76@

UV8

DQSC[7..0]

<14,21>

CMD2

OPT@
CV178
1U_0402_6.3V6K

D

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

5

4

3

2

4019IE

Friday, August 24, 2012

Sheet
1

20

Rev
B
of

60

1

2

3

4

5

VRAM DDR3 chips (1GB)
64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB

D

<14,20>

DQMC[7..0]

<14,20>

CMDC[30..0]

<14,20>

DQSC#[7..0]

<14,20>

DQSC[7..0]

<14,20>

D

DQMC[7..0]

UV10
CMDC[30..0]

M8
H1

DQSC#[7..0]
DQSC[7..0]

MDC[63..0]

+MEM_VREF6

MDC[63..0]

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

+1.5VSDGPU

OPT@

RV142
1.33K_0402_1%

OPT@

C

2

CV175
0.1U_0402_16V4Z

OPT@

1
+MEM_VREF6
RV143
1.33K_0402_1%

CMDC18
CMDC16
CMDC30
CMDC15
CMDC13

OPT@

+1.5VSDGPU

RV144
1.33K_0402_1%

DQSC4
DQSC5

OPT@

CV176
0.1U_0402_16V4Z

OPT@

+MEM_VREF7
1

2

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

CMDC12
CMDC27
CMDC26

CLKC1
CLKC1#
CMDC19

RV145
1.33K_0402_1%

N3
P7

DQMC4
DQMC5

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

DQSC#4
DQSC#5

T2
L8

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DQSL
DQSU

RESET
ZQ/ZQ0

Group5

J7
K7
K9

<14>

2
RV148
@
80.6_0402_1%

CLKC1#

1

CLKC1

2OPT@

CLKC1

RV18
160_0402_1%

1
CLKC1#

1

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

ZQ7

B1
B9
D1
D8
E2
E8
F9
G1
G9

CMD0

J1
L1
J9
L9

RV147
243_0402_1%

VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

0..31

32..63

CS0_L#

CMD1
Group7

MDC54
MDC48
MDC52
MDC50
MDC53
MDC51
MDC55
MDC49

Group6

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2

CMD2

ODT_L

CMD3

CKE

CMD4

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

A14

C

CAS*
CS0_H#

CMD16
CMD17
CMD18

E9
F1
H2
H9

ODT_H

CMD19

A9
VSS B3
VSS E1
VSS
G8
VSS J2
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VSS

DML
DMU

G3
DQSC#7
DQSC#6

CMDC5

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

310mA

DQSL
DQSU

E7
D3

DQMC7
DQMC6

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CS/CS0
RAS
CAS
WE

F3
C7

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

2

RV150
@
80.6_0402_1%

J1
L1
J9
L9

D7
C3
C8
C2
A7
A2
B8
A3

MDC63
MDC58
MDC62
MDC59
MDC60
MDC61
MDC57
MDC56

+1.5VSDGPU

ODT/ODT0

L2
J3
K3
L3

DQSC7
DQSC6

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

K1
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M2
BA0
N8
M3 BA1
BA2

2
OPT@

1
RV146
243_0402_1%

1
<14>

ZQ6

2
OPT@

B

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VSDGPU

CLKC1
CLKC1#
CMDC19

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDC12
CMDC27
CMDC26

E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

N3
P7

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

+1.5VSDGPU

A1
A8
C1
C9
D2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
DQSL
DQSU310mA VDDQ

DML
DMU

MDC44
MDC43
MDC47
MDC40
MDC45
MDC42
MDC46
MDC41

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

+MEM_VREF7

Group4

Mode D
Address

X76@

UV9

M8
H1

MDC39
MDC33
MDC38
MDC32
MDC36
MDC34
MDC37
MDC35

1

CMDC5

X76@

B1
B9
D1
D8
E2
E8
F9
G1
G9

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

B

Not Available

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

@
CV177
0.01U_0402_16V7K

NV recommand 0720

+1.5VSDGPU

+1.5VSDGPU

2011/09/23

3

OPT@
CV220
1U_0402_6.3V6K

Title

SCHEMATICS, MB A8581

Size
Document Number
Custom
Date:

4

A

Compal Electronics, Inc.
2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

OPT@
CV219
1U_0402_6.3V6K

2

OPT@
CV218
1U_0402_6.3V6K

1

OPT@
CV217
1U_0402_6.3V6K

2

OPT@ CV216
0.1U_0402_16V4Z

1

OPT@ CV227
0.1U_0402_16V4Z

OPT@
CV226
1U_0402_6.3V6K

OPT@
CV225
1U_0402_6.3V6K

OPT@
CV224
1U_0402_6.3V6K

2

Compal Secret Data

Security Classification
Issued Date

1

OPT@
CV223
1U_0402_6.3V6K

2

OPT@ CV222
0.1U_0402_16V4Z

1

OPT@ CV221
0.1U_0402_16V4Z

OPT@
CV207
1U_0402_6.3V6K

OPT@
CV196
1U_0402_6.3V6K

OPT@
CV195
1U_0402_6.3V6K

2

OPT@
CV194
1U_0402_6.3V6K

2

1

OPT@ CV193
0.1U_0402_16V4Z

1

OPT@ CV214
0.1U_0402_16V4Z

OPT@
CV213
1U_0402_6.3V6K

close to UV9
OPT@
CV212
1U_0402_6.3V6K

OPT@
CV211
1U_0402_6.3V6K

2

OPT@
CV210
1U_0402_6.3V6K

A

1

OPT@ CV209
0.1U_0402_16V4Z

2

OPT@ CV208
0.1U_0402_16V4Z

close to UV10
1

2

4019IE

Friday, August 24, 2012

Sheet
1

21

Rev
B
of

60

1

2

3

+5VS

1

1

4

5

@
D29

D58

@

2

D30

3

3

2

40mil
1

1.1A_6V_MINISMDC110F-2
C679
0.1U_0402_16V4Z

2

3

2

+CRT_VCC

+CRT_VCC_R
F3
1
1
RB491D_SOT23-3

PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

2

If=1A

D

CRT_G_L

R670

2

1

C681

2

1
C682

2

C683

1

2

D

CRT CONNECTOR
JCRT

1
C684

1

C685

2

2

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_B_L

2.2P_0402_50V8C

R671

1
2
150_0402_1%

1
2
150_0402_1%

1
2
150_0402_1%

R672

C680

2.2P_0402_50V8C

PCH_CRT_B
1

PCH_CRT_B

L20
2
1
NBQ100505T-800Y_0402

2.2P_0402_50V8C

PCH_CRT_G

2.2P_0402_50V8C

<27>

CRT_R_L

L19
2
1
NBQ100505T-800Y_0402

2.2P_0402_50V8C

PCH_CRT_G

<27>

PCH_CRT_R

2.2P_0402_50V8C

PCH_CRT_R

<27>

L18
2
1
NBQ100505T-800Y_0402

PAD

T264

CRT11
CRT_R_L
CRT_DDC_DAT
CRT_G_L

HSYNC
CRT_B_L

40mil
+CRT_VCC
T265 PAD

VSYNC
CRT12
CRT_DDC_CK

+3VS

16
17

+CRT_VCC

GND
GND

C

SUYIN_070546FR015S293ZR

2

2

C

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

2
PCH_CRT_DATA

<27>

4

PCH_CRT_CLK

PCH_CRT_CLK

1
@ C850
33P_0402_50V8K

2

1

2

1

1

CRT_DDC_DAT

2N7002DW-T/R7_SOT363-6

5

PCH_CRT_DATA

4.7K_0402_5%

Q157A
6

1
<27>

CONN@

R678

4.7K_0402_5%

R677

3 Q157B

CRT_DDC_CK

1

2N7002DW-T/R7_SOT363-6
@ C689
470P_0402_50V8J

@ C849
33P_0402_50V8K

1

2

2

@ C690
470P_0402_50V8J

B

B

+CRT_VCC

A

4 D_CRT_VSYNC 1
Y
L22
U39
SN74AHCT1G125GW_SOT353-5

2
10_0402_5%

HSYNC

5
1
A

VSYNC

1
@ C687

1

@ C688

2

2

10P_0402_50V8J

2

G

PCH_CRT_VSYNC

2
10_0402_5%

D_CRT_HSYNC

+CRT_VCC

PCH_CRT_VSYNC

3

<27>

1
L21

4

Y

U38
SN74AHCT1G125GW_SOT353-5

P
OE#

2
1
C851
0.1U_0402_16V4Z

10K_0402_5%
1

10P_0402_50V8J

2

P
OE#

PCH_CRT_HSYNC

G

PCH_CRT_HSYNC

3

<27>

R1436
2

5
1

2
1
C686
0.1U_0402_16V4Z

A

A

Compal Secret Data

Security Classification
Issued Date

2011/09/23

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

22

of

60

1

2

3

4

5

+LCD_VDD

+3VS

1

+3VS

1

R1440
0_0402_5%
2

R621
300_0603_5%
LCD_BL_PWM

PCH_BL_PWM

1

62
1

3
BKOFF#

BKOFF#_R

BKOFF#

<27>

short@
2
1
R1379
0_0402_5%

PCH_ENVDD

Q17B

2

+LCD_VDD

2N7002DW-T/R7_SOT363-6

1

1
W=60mils
@ C672
4.7U_0805_10V4Z

R1421
10K_0402_5%

D

AO3413_SOT23

2

C671
0.01U_0402_25V7K

5

3

2
C908
0.1U_0402_16V7K
2
1
1
47K_0402_5%
R623

1

<41>

R103
33_0402_5%
2

4

1

Vds=-20V
Id=-3A
Rds=130m ohm
Vgs=-4.5
Q18
Vth=-1

R627
100K_0402_5%

2

1

Q17A
2N7002DW-T/R7_SOT363-6

C958
180P_0402_50V8J

1

2

2

@

D

G

INVT_PWM

2
R1441

D

<41>

1
0_0402_5%

S

<27>

2

2

1
L24 2
0_0805_5%

1

2

1

C673
0.1U_0402_16V4Z

2

+LCDVDD_R
1
C678

C693

4.7U_0805_10V4Z

2

0.1U_0402_16V4Z

Close to JLVDS1

C

LCD/PANEL BD. Conn.
1

W=30mils
R1428 0_0603_5%

3

1

2
B

2

3
1

2
1

G

1

1
1
C327 @ @

Q20
AO3413_SOT23
TF@

Q61
TF@
2N7002_SOT23-3

220P_0402_25V8J

2

2

2

C328
220P_0402_25V8J

+LVDS_CAM

S

W=30mils
R1427 0_0603_5%
1
@ 2
+3VS
USB20_P10_R
USB20_N10_R

Add on 7/27 for fn+f5 turn off camera.

3

@
3

WCM-2012-900T_0805
1
R7

USB20_P10_R

USB20_N10_R

USB20_P10_R
USB20_N10_R

2
0_0402_5%

3

4

DMIC_DATA_R
+LCD_INV
+LCD_INV
+LCD_INV

2

@ D14

31
32

@ C400
680P_0402_50V7K

1
DMIC_CLK
0_0402_5%

DMIC_CLK

2 @
R1402

1
0_0402_5%
DMIC_DATA

DMIC_DATA

<38>

<38>

DMIC_DATA_R

+LVDS_CAM

JP4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

DMIC_CLK_R

B

PCH_TXCLK+
PCH_TXCLK-

PCH_EDID_CLK
PCH_EDID_DATA
1

CE_EN_R
LCD_BL_PWM
BKOFF#_R

PCH_TXCLK+
PCH_TXCLK-

PCH_EDID_CLK <27>
2PCH_EDID_DATA <27>
R183
1K_0402_5%
CE_EN
CE_EN <29>

CE_EN: reserve for special panel,
controlled by PCH--Joyce 0921-2011

+LCDVDD_R

1
DMIC_CLK_R

1

GND1
GND2
2

ACES_88242-3001
CONN@

<27>
<27>

@

2

100K_0402_5%
R1191

4

2

2

2 @
R1401

0.1U_0402_16V4Z
C691

USB20_N10

0_0402_5%
2

1

PCH_TXOUT0+
PCH_TXOUT0PCH_TXOUT1+
PCH_TXOUT1PCH_TXOUT2+
PCH_TXOUT2-

PCH_TXOUT0+
PCH_TXOUT0PCH_TXOUT1+
PCH_TXOUT1PCH_TXOUT2+
PCH_TXOUT2-

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2

2

C319
0.1U_0402_25V4K

Rated Current MAX:3000mA

0.1U_0402_16V4Z
C399

USB20_P10

<27>
<27>
<27>
<27>
<27>
<27>

2

R6
1
L4

1

<28>

2

C692
68P_0402_50V8J

1

1

1

@

C911
47P_0402_50V8J
2
1

@

<28>

1
@

W=30mils

0.1U_0402_16V4Z
C699

R1422
10K_0402_5%
TF@

D

1

DMIC_DATA

D

CAMPWR_EN

030@

S

CAMPWR_EN

1
0_0402_5% 2
G

1.5A

PCH_EDID_CLK
PCH_EDID_DATA

DMIC_CLK

C758
100P_0402_50V8J

<41>

2
R1403 TF@

1

C760
100P_0402_50V8J

2

TF@
2
C909
R628
0.1U_0402_16V7K
100K_0402_5%
TF@
1
TF@
2
2CAMPWR_EN#
1
R624 47K_0402_5%

1

Must close JLVDS pin 28、30

+5VS
+5VS

B+
L23
2
1
FBMA-L11-201209-221LMA30T_0805

+LCD_INV

2

C

+3VS

PJDLC05_SOT23-3

A

1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

SCHEMATICS, MB A8581
Rev
B

4019IE

Friday, August 24, 2012

Sheet
1

23

of

60

1

DISO and OPT Channel

D

1
L91

2

2 R166
0_0402_5%

@

HDMI_CK-

VGA Video Chanel

HDMI_D0+

1

2
2N7002_SOT23-3
Q16
1

HDMI_R_CK-

HDMI_HPD

2

R573
100K_0402_5%

HDMI_R_D0+

0.1U_0402_16V7K
<27>

PCH_HDMI_TXC-

<27>

PCH_HDMI_TX0+

<27>

PCH_HDMI_TX0-

<27>

PCH_HDMI_TX1+

<27>

PCH_HDMI_TX1-

<27>

PCH_HDMI_TX2+

<27>

PCH_HDMI_TX2-

2
0.1U_0402_16V7K 2
0.1U_0402_16V7K
2
0.1U_0402_16V7K

1
1C458

2
0.1U_0402_16V7K 2
0.1U_0402_16V7K
2
0.1U_0402_16V7K

1
1C435
C457
1
C436

HDMI_CK+

HDMI_D0+

2

2 R173
@
0_0402_5%
WCM-2012-121T_0805

HDMI_R_D0-

BAV99_SOT23-3
D34

1

HDMI_D0-

Internal Graphic Video Chanel

HDMI_D1+

UMAO Channel

HDMI_D1+

4

D

1

2

2 R172
0_0402_5%

@

HDMI_D0-

HDMI_CK-

C392
1
C402

1
L10
1

3

1
C433
1
C401

2

PCH_HDMI_TXC+

<27>

C729

4

3

1
L11

2

2

1

2
0.1U_0402_16V7K
<27>

2
0_0402_5%

0.1U_0402_16V4Z
2
1
C730
@
0.1U_0402_16V4Z
1

1

WCM-2012-121T_0805
4
3
4
3

short@

1
R438

3

PCH_HDMI_HPD

2 R167
0_0402_5%

@

+3VS
R1568
1M_0402_5%

2

1

HDMI_R_CK+

2
G

WCM-2012-121T_0805
3
4
3

S

4

HOT PLUG1

D

HDMI_CK+

2 R164
0_0402_5%

@

2

1

1

2

3

4

5

HDMI Source Select

HDMI_R_D1+

3
+HDMI_5V_OUT

HDMI_D1-

1

HDMI_D2+
HDMI_D2-

1

2

2 R176
0_0402_5%

@

HDMI_D1-

HDMI_R_D1-

@

2 R177
0_0402_5%

1
HDMI_D2+

C

4
1

HDMI_R_D2+

C

WCM-2012-121T_0805
3
4
3

1
L12
1

2

2

2 R178
0_0402_5%

@

HDMI_D2-

HDMI_R_D2-

EVT mount chock, DVT mount resistor

EDID SELECT

HDMI_R_D1-

2

0.1U_0402_16V4Z
HDMI_R_D0-

HDMI_SDATA
HDMI_SCLK
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0-

A

HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
GND
CKCK_shield GND
GND
CK+
GND
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

HDMI_R_D2+
HDMI_R_D2-

1
1

R693

1
R694 1
R695
1
R696
1
R697

2

2
680
2 +-5% 0402
680 +-5% 0402
2
680 +-5% 0402
2
680 +-5% 0402

1
R698

1

3

HDMI_SCLK

HDMI_R_DATA

D

2
100K_0402_5%

S

Q2
2N7002_SOT23-3

Q182
BSH111_SOT23-3

1

3

2
G

+5VS

20
21
22
23

HDMI_R_CLK
BSH111_SOT23-3
Q183

HDMI_SDATA

D

HDMI_HPD
+HDMI_5V_OUT

JHDMI

R692

S

HDMI_R_D0+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R691

D

HDMI_R_D1+

2
2

HDMI_R_CK-

+HDMI_5V_OUT

short@
2
1
R433
0_0402_5%
2
1
R436 short@ 0_0402_5%

HDMI_R_CLK

HDMI_R_DATA

PCH_HDMI_CLK

PCH_HDMI_DATA

<27>

<27>

1
C266
2 0.1U_0402_16V4Z

A

2011/09/23

Issued Date

CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LOTES_ABA-HDM-029-P01

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

B

R1328
2.2K_0402_5%

R1329
2.2K_0402_5%

SG

C250

2
680 +-5% 0402
2
680 +-5% 0402
2
680 +-5% 0402
2
680 +-5% 0402

2

1

1

1

1

1
R690

3

RB161M-20_SOD123-2 D53
2
+5VS

HDMI_R_CK+

2
1
R434 short@ 0_0402_5%

G

40mil

1.1A_6V_MINISMDC110F-2
F2
1
2

+HDMI_5V_OUT

+3VS

if use VGA_HDMI,
R690~R697 should be 499ohm+/-1%.

+5VS_HDMI

1
1

HDMI Connector
B

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

24

of

60

2

3
4
NC
OSC
2
32.768KHZ_12.5PF_Q13MC14610002C205
@

Y2

1
15P_0402_50V8J

R95
R96

1
1

2
1M_0402_5%
2
SM_INTRUDER#
330K_0402_5%
PCH_INTVRMEN

far away hot spot

+RTCBATT

D2
BAS40-04_SOT23-3

+RTCVCC

+RTCVCC

PCH_RTCX2

2
1K_0402_5%

W=20mils
Place near PCH

High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)

3

OSC

R94
10M_0402_5%
1
2

NC

32.768KHZ_12.5PF

1

1

Integrated SUS 1.05V VRM Enable
PCH_RTCX1

1
Y6

2

1

1
R1300

2

1
18P_0402_50V8J

2

3

4

5

2
C204

1

W=20mils

RH37INTVRMEN:
@
330K_0402_5%
check list

C363
0.1U_0402_16V4Z

Rev1.5 P63, P64 error

+CHGRTC

2

PCH_INTVRMEN
D

MP BOM: Y2-SJ100001K00, C204-18pF, C205-15pF.

JCMOS & JME1 place near DIMM
2

+RTCVCC

C206
1

SHORT PADS

20K_0402_5%
2

@
JME1
SHORT PADS

1

C207
1U_0603_10V4Z

A20

@

CMOS
JCOMS

1U_0603_10V4Z
2
1
20K_0402_5%
R97
R98

UPCH1A

PCH_RTCX1

C20

PCH_RTCX2

D20

PCH_RTCRST#

G22

PCH_SRTCRST#

K22

SM_INTRUDER#

C17

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

RTCX1

LPC

another solution: Y2-SJ100004Z00, C204-15pF, C205-15pF.
this is tested OK by DQA, but not add into BOM.

RTCX2

RTCRST#

FWH4 / LFRAME#

SRTCRST#
LDRQ0#
LDRQ1# / GPIO23

RTC

D

INTRUDER#
INTVRMEN

SERIRQ

C38
A38
B37
C37

D36

E36
K36

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_FRAME#

2

V5

1
10K_0402_5%

R99

0_0402_5%
R180
ME_EN from EC.
Please place close to RH29 aviod the branch.
<41> HDA_SDO
HDA_SDOUT

R106

1

2
33_0402_5%
HDA_RST#
2
33_0402_5%
HDA_SDOUT

PCH_SPKR

HDA_SYNC

T10

PCH_SPKR

K34

1
<38>

AZ_SDOUT_HD

R108

AZ_SDIN0_HD

<38>

AZ_SDIN0_HD

G34

C34

A34
C

+3VS

R1299

@

SPKR
HDA_RST#

A36

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN0
HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

HDA_SDO

HDA_SDOUT

1K_0402_5%

C36

PCH_SPKR

N32

LOW=Default
Reboot

*HIGH=No

T1512 PAD

HDA_SDO

J3

T1513 PAD

PCH_JTAG_TCK

H7

T1514 PAD

PCH_JTAG_TMS

K5

PCH_JTAG_TDI

H1

T1515 PAD

ME debug mode , this signal has a weak internal PD

HDA_DOCK_EN# / GPIO33

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI

JTAG_TDO

SATAICOMPI

L=>security measures defined in the Flash
Descriptor will be in effect (default)
H=>Flash Descriptor Security will be overridden

SATA3COMPI

<33>

PCH_SPI_CLK

PCH_SPI_CLK

Y14

<33>

PCH_SPI_CS#

PCH_SPI_CS#

T1

PCH_SPI_CS1#

PCH_SPI_CS1#

+3VALW_PCH

@

1K_0402_5%

HDA_SDOUT

<33>

V4

= Disabled
*Low
High = Enabled

<33>

PCH_SPI_MOSI

PCH_SPI_MOSI

<33>

PCH_SPI_MISO

PCH_SPI_MISO

U3

SATA3RBIAS

SPI_CLK

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
AM10 SATA_PTX_DRX_P0
AM8
AP11
AP10

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
AB8 SATA_PTX_DRX_P2
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

<34,41,44>

SATA_PRX_C_DTX_N0
<34>
<34>
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
<34>
<34>
SATA_PTX_DRX_P0

AD7
AD5
AH5
AH4

SATA_PRX_C_DTX_N2
<34>
<34>
SATA_PRX_C_DTX_P2
<34>
SATA_PTX_DRX_N2
<34>
SATA_PTX_DRX_P2

+5VS

ODD
C

SATA_PRX_C_DTX_N4
SATA_PRX_C_DTX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

<43>
SATA_PRX_C_DTX_N4
<43>
SATA_PRX_C_DTX_P4
SATA_PTX_DRX_N4
<43>
SATA_PTX_DRX_P4
<43>

E-Sata

Y11
+1.05VS_VCC_SATA

R1202

37.4_0402_1%

1
SATA3_COMP RH42

2
49.9_0402_1%

AB12
+1.05VS_SATA3

AB13
AH1

RH46

750_0402_1%

RBIAS_SATA3

+3VS

SPI_CS1#

SPI_MOSI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

SPI_MISO

P3
SATA_LED#

P1

PCH_GPIO21

SATA_LED#

<43>

SATA_LED#

R208

2 @

R205

10K_0402_5%

PCH_GPIO21

2

SATA1GP/GPIO19: Integrated 20K pull up.

@

1

B

2

2

R207
10K_0402_5%

R190
0_0402_5%

1

PCH_JTAG_TDI
RH47
XDP@
100_0402_1%

GPIO19 => BBS_BIT0
GPIO51 => BBS_BIT1
Boot BIOS Strap
Bit 11
(BBS1)
0

2

PCH_JTAG_TMS
RH45
XDP@
100_0402_1%

SATA1GP/GPIO19: Boot BIOS Strap bit 0 (BBS0)
GNT1#/GPIO51: Boot BIOS Strap bit 1 (BBS1)

＆＊
＆＊

RH40
XDP@
200_0402_5%

2
PCH_JTAG_TDO
RH44
XDP@
100_0402_1%

2

2

R418
1M_0402_5%

2

Intel recommend

RH50 2

HDA_SYNC
A

RH39
XDP@
200_0402_5%

1

1

RH38
XDP@
200_0402_5%

SATA0GP / GPIO21: Serial ATA 0 General Purpose.
This is an input pin which can be configured as an
interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication,
0
this signal should be drive to
to indicate
that
1
the switch is closed and to
to indicate that
the switch is open.
If interlock switches are not required,
this pin can be configured as
GPIO21.

+3VALW

2

2
R188

1 2

1

1 @
0_0402_5%

+3VALW

+3VALW

1

Q10
BSS138_NL_SOT23-3
1
HDA_SYNC

D

AZ_SYNC_HD

3
S

<38>

2
33_0402_5%
AZ_SYNC_HD_R

1
R145

1

G

2

1

1

R189
0_0402_5%
@

1 4.7K_0402_5%

BBS_BIT0_R

BBS_BIT0_R

+3VS

10K_0402_5%

R113

V14

PANTHER-POINT_FCBGA989
@
B

HDD

Y10

SPI_CS0#

SPI

T3

AM3
AM1
AP7
AP5

SATA_COMP

SATA3RCOMPO

PCH_JTAG_TDO

R182

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

HDA_RST#

E34
<38>

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

IHDA

R101

AZ_RST_HD#

<38>

HDA_SYNC

SATA

AZ_BITCLK_HD

2
33_0402_5%
HDA_BIT_CLK

HDA_BCLK

JTAG

<38>

1

L34

SATA 6G

N34
HDA_BIT_CLK

<34,41,44>

+3VS
SERIRQ

PCH_INTVRMEN

ME CMOS

<34,41,44>
<34,41,44>
<34,41,44>
<34,41,44>

XDP@ 1
51_0402_5%

Bit 10
(BBS0)
1

Boot BIOS
Destination
Reserved

1

0

1

1

SPI

0

0

LPC

PCI

*

PCH_JTAG_TCK

Intel DPDG Rev1.2 requirement.

PCH EDS Rev1.5 P99, P98

This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom

A

+3VALW_PCH

HDA_SYNC

R181

1K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

25

of

60

2 10K_0402_5%
+3VALW_PCH
2
1K_0402_5%

1
1
R1207

2

3

4

5

1
R1319

2 10K_0402_5%

R1320 1
PCH_GPIO11
DRAMRST_CNTRL_PCH

R1322 2

1 2.2K_0402_5%

PCH_HOT#

UPCH1B

PCIE_PTX_LANRX_N6
PCIE_PTX_LANRX_P6

BG40
BJ40
AY40
BB40

BE38
BC38
AW38
AY38

C

+3VALW_PCH

1 @
R1523
1
R1521
1
R1527

1
1
R1531
R1530

2
CLKREQ_LAN#
2
10K_0402_5%
10K_0402_5% PEG_CLKREQ#_R

1
R1522

CLKREQ_R_WWAN#
2
10K_0402_5%
PCH_GPIO44
2
PCH_GPIO45
10K_0402_5%
1
10K_0402_5%
PCH_GPIO56

1
R1529
2
R1217

short@

2
10K_0402_5%
2
10K_0402_5%
2
CLK_REQ_CARD#
10K_0402_5%
PCH_GPIO46

<35,42>
<35,42>

LAN

<35,42>

CLKREQ_LAN#

<36>
<36>

WLAN

<36>

CLK_LAN#
CLK_LAN

CLK_WLAN#
CLK_WLAN

CLKREQ_WLAN#

2 0_0402_5%

R1212 1
short@
short@

CLKREQ_LAN#

CLK_R_WLAN#
CLK_R_WLAN

2 0_0402_5% CLKREQ_WLAN#
2 0_0402_5%

R1227 1
R1228 1

short@
<39>

CLK_PCIE_EXPCARD

<39>

CLKREQ_EXPCARD#

Card Reader
+3VS

1
R1532

2 0_0402_5%

R140 1

CLK_R_CARD#
CLK_R_CARD

R260
R264

1
R1520

CLK_R_LAN#
CLK_R_LAN

short@
short@

CLK_PCIE_EXPCARD#
<39> Card
Express

<37> CLK_PCIE_READER#
<37> CLK_PCIE_READER

B

Y40
Y39

2 0_0402_5%
2 0_0402_5%

R1213 1
R1214 1

WWAN

2
10K_0402_5%CLKREQ_WLAN#

<36>
<36>

<36>

CLK_WWAN#
CLK_WWAN

CLKREQ_WWAN#

1

1
short@
short@

2 0_0402_5% CLKREQ_EXPCARD#
2 0_0402_5%

2
1
2 0_0402_5%
1 short@10K_0402_5%
R144
R255

2 0_0402_5%
R1220 1
R1226 1 short@ 2 0_0402_5%
short@

CLK_CARD#
CLK_CARD
CLK_REQ_CARD#

CLK_R_WWAN#
CLK_R_WWAN

CLKREQ_R_WWAN#

2
10K_0402_5%

J2

AB49
AB47

M1

AA48
AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

CLKREQ_EXPCARD#

PCH_GPIO44

AB42
AB40
E6

PCH_GPIO56

V40
V42

RN192
RN19311 OPT@
@

DGPU_PWR_EN

VGA_PWROK

2
G

V38
V37

PCH_GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP

<28,45,57>

AK14
AK13

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

T11
CL_CLK_DMC

CL_RST1#

P10
CL_DATA_DMC

1

10K_0402_5%

2.2K_0402_5%

R222

1

R223

1

2

CL_CLK_DMC
2.2K_0402_5%

2

10K_0402_5%
CL_DATA_DMC

<36>

CL_RST#_DMC

<36>

R253
AB37PEG_CLKREQ#_R
AB38

CLKIN_GND1_N
CLKIN_GND1_P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26

REFCLK14IN

CLKOUT_PCIE5N
CLKOUT_PCIE5P

R254

short@
1
1
short@

<13>
<13>

CLKIN_PCILOOPBACK

R130

2

@
@

CLK_DP#
BF18CLK_DP
BE18

CLK_CPU_DMI#
CLK_CPU_DMI
T13
PAD

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

R1206
2

XTAL25_IN
XTAL25_OUT

+3VS

1

EC_SMB_DA2

Q3A
2N7002DW T/R7_SOT-363-6
1
PM_SMBCLK

<11,12,36,39>

2
4.7K_0402_5%

+3VS

PM_SMBCLK
1
R1208

2
4.7K_0402_5%

CLK_SATA#
K45 CLK_SATA

PCH_X1
PCH_X2

CLK_PCILOOP

B

4

1

3

short@

2N7002DW T/R7_SOT-363-6
Q3B
PM_SMBDATA

2
0_0402_5%

PCH_SMBDATA

<28>
PCH_X1

2

1
R1221

K43
F47

CLKOUTFLEX2 / GPIO66

H47
CLK_FLEX1

CLKOUTFLEX3 / GPIO67

K49
CLK_FLEX2

R1216

1M_0402_5%
Y3

90.9_0402_1%
+1.05VS_VCCDIFFCLKN

1

1

PCIECLKRQ6# / GPIO45

@
R2571

2 0_0402_5%

R2581

2 0_0402_5%

@

T15

PAD

C869

R1533
10K_0402_5%

UMA@

short@

1

2
CLK_SIO_48M

PCH_X2

3
GND

GND

2

4

3

C225

1

25MHZ_10PF_7V25000014

2

<44>

DGPU_PRSNT#

R1534
10K_0402_5%

OPT@

5/12

short@

PCH_SMBCLK

+3VS

CLKOUTFLEX1 / GPIO65

R1225

6

+3VS

1
R1209

Y47
XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

<13,41>

2
0_0402_5%

CLK_14M_PCH

H45

V47 CLK_PCILOOP
V49

CLKOUT_PCIE6N
CLKOUT_PCIE6P

EC_SMB_DA2

1

R1223
PM_SMBDATA

<13,41>

2N7002DW T/R7_SOT-363-6
Q4B

PCH_SMLDATA1

CLK_DOT#
AK7 CLK_DOT
AK5

EC_SMB_CK2

4

3

2.2K_0402_5%

CLKIN_DMI2#
G24 CLKIN_DMI2
E24

XCLK_RCOMP

EC_SMB_CK2

PCH_SMLCLK1
2.2K_0402_5%

<6>
<6>

PAD

T14

1

PCH_CLK_DMI#
BJ30PCH_CLK_DMI
BG30

PEG_B_CLKRQ# / GPIO56

C

Q4A
2N7002DW T/R7_SOT-363-6
1
6

+3VALW_PCH

<11,12,36,39>

PCIECLKRQ5# / GPIO44

@ C367
22P_0402_50V8J
2
1

@ R269
33_0402_5%
2
1

Reserve for EMI please close to UPCH1

VGA

CLK_PCIE_VGA#
CLK_PCIE_VGA

CLK_CPU_DMI#
AM12
CLK_CPU_DMI
AM13

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

2
2

0_0402_5%
0_0402_5%

CLK_VGA#
AV22CLK_VGA
AU22

PCIECLKRQ1# / GPIO18

@ C368
22P_0402_50V8J
2
1

1

CLK_PCILOOP

M10

CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ2# / GPIO20

@ R265
33_0402_5%
2
CLK_14M_PCH

CL_RST#_DMC

CLKOUT_PCIE2N
CLKOUT_PCIE2P

<36>

@

@

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

If use extenal CLK gen, please place close to
CLK gen, else, please place close to PCH

2
@

PANTHER-POINT_FCBGA989
@

<29,45,57>

10K_0402_5%
10K_0402_5%

2

+5VALW_PCH

R219

CL_DATA1

PEG_A_CLKRQ# / GPIO47

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

22

1

CLK_SATA#
CLK_SATA

M7

CL_CLK1

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ7# / GPIO46

11

RH183

10K_0402_5%
2210K_0402_5%
10K_0402_5%
10K_0402_5%

CLK_14M_PCH

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE7N
CLKOUT_PCIE7P

RH79
RH78

CLK_DOT#
CLK_DOT

To EC SM BUS 2

PCH_SMLDATA1

10K_0402_5%

2
2

11

CLKIN_DMI2#
CLKIN_DMI2

add port to EC--Joyce

PCH_SMLCLK1

PERN7
PERP7
PETN7
PETP7

CLKOUT_PCIE1N
CLKOUT_PCIE1P

<41>

PCH_HOT#

M16PCH_HOT#

SML1DATA / GPIO75

10K_0402_5%

2

1

1
RH91
RH76
RH89
RH771

E14

SML1CLK / GPIO58

PCIECLKRQ0# / GPIO73

<42>

PCH_SMLDATA0

C13PCH_SMLDATA0

SML1ALERT# / PCHHOT# / GPIO74

A

FROM CLK GEN FOR: 133/100/96/14.318 MHZ

S

T15, T16 reserve 27M_CLK and 27M_SSC for VGA.
we have crystal at VGA side.

Pull PEG_CLKREQ#
high @ VGA <13>
side

1

1
RN188 @
RN72
@
2.2K_0402_5%

2
0_0402_5%

Compal Secret Data

Security Classification
Issued Date

RN73
@
2.2K_0402_5%

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

D

for safe

2

PEG_CLKREQ#_R

QN4
OPT@
Add RN192,RN193
SSM3K7002F_SC59-3
2
1
3
RN71 OPT@ 0_0402_5%

PCH_GPIO45

K12

CLK_RES_ITP#
CLK_RES_ITP

22 0_0402_5%
0_0402_5%

A

1

0_0402_5%
0_0402_5%

PERN4
PERP4
PETN4
PETP4

2

1

RH92
RH90

PCH_CLK_DMI#
PCH_CLK_DMI

<42>

PCH_SMLCLK0

PCH_SMLCLK0

10P_0402_50V8J

<8>
<8>

@
@

PCH_SMLDATA0

<7,10>

DRAMRST_CNTRL_PCH

G12
DRAMRST_CNTRL_PCH

10P_0402_50V8J

T13

RH108
RH109

PCH_SMLCLK0

C8

SML0CLK
SML0DATA

2

2 0.1U_0402_16V7K

BJ38
BG38
AU36
AV36

A12 PCH_SMBDATA

SML0ALERT# / GPIO60

1 2.2K_0402_5%

5

C218 1

PCIE_PTX_CARDRX_N5
PCIE_PTX_CARDRX_P5

PERN3
PERP3
PETN3
PETP3

1 2.2K_0402_5%

R1229 2

2

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

D

R1224 2

5

PCIE_PRX_C_LANTX_N6
PCIE_PRX_C_LANTX_P6
PCIE_PTX_C_LANRX_N6
PCIE_PTX_C_LANRX_P6

C404 1
C403 1
C217 1

BG37
BH37
AY36
BB36

+3VALW_PCH

PCH_SMBCLK

2

PCIE_PRX_C_CARDTX_N5
PCIE_PRX_C_CARDTX_P5
PCIE_PTX_C_CARDRX_N5
PCIE_PTX_C_CARDRX_P5

BF36
BE36
AY34
BB34

PCH_SMBDATA

C9 PCH_GPIO11

1

PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

BG36
BJ36
AV34
AU34

PCH_SMBCLK

H14

2

<35,42>
<35,42>
<35,42>
<35,42>

LAN

PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

E12

1 2.2K_0402_5%

1

<37>
<37>
<37>
<37>

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C215 1
C216 1
C391 1
C386 1

PERN2
PERP2
PETN2
PETP2

SMBUS

PCIE_PRX_C_EXPTX_N3
PCIE_PRX_C_EXPTX_P3
PCIE_PTX_C_EXPRX_N3
PCIE_PTX_C_EXPRX_P3

SMBCLK

SMBDATA

Link

Card Reader

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2

<39>
<39>
<39>
<39>

SMBALERT# / GPIO11

Controller

Express Card

<36>
<36>
<36>
<36>

BE34
BF34
BB32
AY32

PERN1
PERP1
PETN1
PETP1

FLEX CLOCKS

WLAN

BG34
BJ34
AV32
AU32
PCIE_PTX_WWANRX_N1
PCIE_PTX_WWANRX_P1

PCI-E*

WWAN

PCIE_PRX_C_WWANTX_N1
PCIE_PRX_C_WWANTX_P1
PCIE_PTX_C_WWANRX_N1
PCIE_PTX_C_WWANRX_P1

CLOCKS

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C385 1
C384 1
<36>
<36>
<36>
<36>

D

R1222 2

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.

SCHEMATICS, MB A8581
Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

26

of

60

1

2

UPCH1C

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AY24
AY20
AY18
AU18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

+1.05VS_PCH

BJ24
BG25

R1236

49.9_0402_1%

RH112

750_0402_1%
DMI_IRCOMP

BH21

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0

DMI_ZCOMP
DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0
FDI_LSYNC1

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

DSWVRMEN

C12

BC10
AV14
BB10

10K_0402_5%

R35

K3

SUSACK#

SYS_RST#

P12

L22

8111E@SYSTEM_PWROK
0_0402_5%
RH120

C

VPRO@

1
RH118

PCH_APWROK

<41>

<6>
<41>

B13

short@
R2
PM_DRAM_PWRGD
0_0402_5%

PM_DRAM_PWRGD
PCH_RSMRST#

1
R291

K16

2
short@

0_0402_5%
SUSWARN#_R

E20

short@
RH137
0_0402_5%
D12
PBTN_OUT#_R
1
2

PBTN_OUT#

<13,41,48>

C21

PCH_RSMRST#_R

PCH_RSMRST#

SUSWARN#

<41>

<41>

L10

PM_PWROK

2
0_0402_5%

ACIN

CH751H-40PT_SOD323-2
AC_PRESENT_R

E10
A10

PCH_GPIO72

2
RH135

<5>
<5>

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK
DRAMPWROK
RSMRST#

DPWROK

E22

CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30

SLP_S3#

SLP_A#

PWRBTN#

B9

<5>

DSWODVREN

N3

EC_SWI#

G8

PM_CLKRUN#

N14

SUS_STAT#

D10

SUSCLK

PM_CLKRUN#

T19

H4

PM_SLP_S5#
PM_SLP_S4#

G10

PM_SLP_S3#

G16

SLP_R_A#

T20

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

SLP_LAN# / GPIO29

RI#

1 VPRO@ 2
0_0402_5%

K14

<23>
<23>
<23>

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

<23>
<23>
<23>

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AN48
AM47
AK47
AJ48

PCH_TXCLKPCH_TXCLK+
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN47
AM49
AK49
AJ47

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AF40
AF39

+RTCVCC
330K_0402_5%

@

AH45
AH47
AF49
AF45

330K_0402_5%

AH43
AH49
AF47
AF43

<34,44>

*：
：

DSWODVREN - On Die DSW VR Enable
H Enable
L Disable

<34>

PM_SLP_S5#

<41>

PM_SLP_S4#

<41>

H_PM_SYNC

1 VPRO@ 2
RH117
0_0402_5%

<22>
<22>
<22>
<22>
<22>

<41>

PM_SLP_S3#

N48
P49
T49

<41>

SUSCLK_R

SLP_A#

<22>
<22>

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

T39
M40

PCH_CRT_CLK
PCH_CRT_DATA

M47
M49

PCH_CRT_HSYNC
PCH_CRT_VSYNC

<41>

Can be left NC when IAMT is
not support on the platfrom

PAD T22

H_PM_SYNC

AF37
AF36
AE48
AE47

DSWODVREN

PAD T21

AP14

T45
P39

PCH_EDID_CLK
PCH_EDID_DATA

<35,36,39>

SUS_STAT#
short@
2
1
RH119
0_0402_5%
T18

F4

PCH_BL_PWM

PCH_TXCLKPCH_TXCLK+

RH129

PCH_RSMRST#_R

EC_SWI#

T40
K47

PCH_EDID_CLK
PCH_EDID_DATA

<23>
<23>

RH127

PCH_DPWROK

PCH_ENVDD

AK39
AK40

non Deep S4/S5:
tied "DPWROK"to
RSMRST#.
0_0402_5%
RH113

WAKE#

P45
PCH_ENBKL

CTRL_CLK
2
1
CTRL_DATA
2.37K_0402_1%
RH244 short@
LVDS_IBG
2
1
RH290
0_0402_5%

<5>

FDI_FSYNC1
FDI_LSYNC0

FDI_LSYNC1

FDI_LSYNC1

<23>

<23>
<23>

<5>

FDI_FSYNC0

FDI_FSYNC0
FDI_FSYNC1

SLP_R_LAN#

RI#

@
SUSACK#

FDI_INT

RH116

H20

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_INT

FDI_LSYNC0

A18

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<23>

DSWVRMEN: must be always pulled-up to VCCRTC. --PCH EDS

System Power Management

4mil width and place
within 500mil of the PCH

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

AV12

RBIAS_CPY

+3VS

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

T43
T42

CRT_IREF

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

P38
M39

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

D

PCH_HDMI_CLK
PCH_HDMI_DATA
2
@ 1RH142
100K_0402_5%

AT49
AT47
AT40

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

R1335
2.2K_0402_5%

R1334
AP39
AP40 2.2K_0402_5%

L_CTRL_CLK
L_CTRL_DATA

LVDSA_CLK#
LVDSA_CLK

+3VS

AM42
AM40

SDVO_STALLN
SDVO_STALLP

AV42
AV40
PCH_HDMI_HPD
AV45
AV46
AU48 PCH_HDMI_TX2AU47 PCH_HDMI_TX2+
AV47 PCH_HDMI_TX1AV49 PCH_HDMI_TX1+
PCH_HDMI_TX0PCH_HDMI_TX0+
P46 PCH_HDMI_TXCDDPC_CTRLCLK P42 PCH_HDMI_TXC+
DDPC_CTRLDATA
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

R1235
1

100K_0402_5%
2
@

C

M43
M36

DDPD_CTRLCLK
DDPD_CTRLDATA

DAC_IREF
CRT_IRTN

PCH_HDMI_HPD
PCH_HDMI_TX2PCH_HDMI_TX2+
PCH_HDMI_TX1PCH_HDMI_TX1+
PCH_HDMI_TX0PCH_HDMI_TX0+
PCH_HDMI_TXCPCH_HDMI_TXC+

AP47
AP49
AT38

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

CRT_HSYNC
CRT_VSYNC

<24>
<24>

AT45
AT43
BH41

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

R1475

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

100K_0402_5%
2
1
@

PANTHER-POINT_FCBGA989
@

R1250
1K_0402_0.5%

<6>

AP43
AP45

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTEN
L_VDD_EN
L_BKLTCTL

2
2

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

J47
M45

Pull high at LVDS conn side.
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

LVDS

<5>
<5>
<5>
<5>

BE24
BC20
BJ18
BJ20

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

Digital Display Interface

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

CRT

<5>
<5>
<5>
<5>

BC24
BE20
BG18
BG20

FDI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

D

<5>
<5>
<5>
<5>

UPCH1D

1
1

3

4

5

<41>

SLP_LAN#

PANTHER-POINT_FCBGA989
@

1
0_0402_5%
SUSWARN#

Check EC for S3 S4 LED

+3VS

2
PM_PWROK

IN1

O

4

IN2

SYSTEM_PWROK

SYSTEM_PWROK

2 8.2K_0402_5%

1
@

2 10K_0402_5%

R301
R302

R304

R283

<6>

1

TC7SH08FU(TE85L,F)

R1255
10K_0402_5%

RH291

1

2 2.2K_0402_5%

RH292

1

2 2.2K_0402_5%

2 2.2K_0402_5%
2 2.2K_0402_5% CTRL_CLK

1

2 2.2K_0402_5%

1

R305

1

2 2.2K_0402_5%

R1438

1

2 4.7K_0402_5%

R1620

1

2 100K_0402_5%

B

PCH_CRT_CLK
PCH_CRT_DATA

CTRL_DATA
PCH_EDID_CLK
PCH_EDID_DATA

1

PM_PWROK

G

VGATE

<41>

PM_CLKRUN#

U12

1

3

<54>

1

P

5

R284

short@
R1314
0_0402_5%

+3VS

+3VS

+3VS
B

PCH_BL_PWM

RH131

1

2 150_0402_1%

RH132

1

2 150_0402_1%

RH133

1

2 150_0402_1%

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

2

PCH_ENVDD

1
@ 180P_0402_50V8J
VGATE
<41>

PCH_GPIO72

RI#

A

R1251

10K_0402_5%

R1252

10K_0402_5%

R279

10K_0402_5%

EC_SWI#

R1244

330K_0402_5%

AC_PRESENT_R

R1243

SUSWARN#_R

R282

PCH_ENBKL

PCH_ENBKL

R300
100K_0402_5%

祥"SUSWARN#'
support deep S4/S5:
妗妗妗妗妗"SUSPWRDNACK"

1

+3VALW_PCH

2

2
C953

SUSWARN# /SUSPWRDNACK/ GPIO30 (Mobile Only):
Used by Intel@ME as either SUSWARN#
in Deep S4/S5 state supported platforms
or as SUSPWRDNACK in non Deep S4/S5
state supported platforms.

10K_0402_5%
A

10K_0402_5%
@

SLP_R_LAN#

PCH_RSMRST#_R
PM_PWROK

R1257

10K_0402_5%

R1256

10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.

SCHEMATICS, MB A8581
Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

27

of

60

4

BG26
BJ26
BH25
BJ16
BG16

1
R321 1
R322 1
R323

2
PCH_GPIO55
2 8.2K_0402_5% PCH_GPIO51
2 8.2K_0402_5% PCH_GPIO52
8.2K_0402_5% PCI_PIRQA#

1
R324 1
R327

2
2 8.2K_0402_5%
8.2K_0402_5%

AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

1
R329 1
R330
1 @
R319

PCH_GPIO2
PCH_GPIO4
2
2 8.2K_0402_5% PCH_GPIO53
8.2K_0402_5% PCI_PIRQC#
2
8.2K_0402_5%

B21
M20
AY16
BG46

+3VS

2

1

8.2K_0402_5%

R320

D

RSVD1
RSVD2
RSVD3
RSVD4

TP1
TP2
TP3
TP4
TP5

RSVD5
RSVD6

TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD

5

TP21
TP22
TP23
TP24

RSVD23
RSVD24

RSVD25

DGPU_HOLD_RST#_R

2

1
R3161
R317
1
R318
1
R310
1
R311

PCI_PIRQB#
2 8.2K_0402_5%
8.2K_0402_5%
ODD_DA#

2
2

2

<40>

8.2K_0402_5% DGPU_PWR_EN_R

USB3.0 Port0

8.2K_0402_5% PCH_GPIO5

<40>

8.2K_0402_5% PCI_PIRQD#

2 @

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

USB3_RX0_N

USB3_RX0_P

<40>

USB3_TX0_N

<40>

USB3_TX0_P

1

DEL
RP5, ADD R316,R317,R318
FOR REMOVE
10K_0402_5%
R1277
GPIO53 PU---0609
DGPU_PWR_EN

RSVD26
RSVD27

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4

RSVD28
RSVD29

<26,45,57>

DGPU_HOLD_RST#_R
PCH_GPIO52
DGPU_PWR_EN_R

DGPU_PWR_EN

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

<34>

D47
E42
F46

G42
G40
C42
D44

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

ODD_DA#

K10

C6

<41>
<26>
<44>
<34>

PLT_RST#

PLT_RST#

<6,34,35,36,37,39,41,42,44>

B

2 @
R259

1
0_0402_5% BUF_PLT_RST#

22_0402_5%
22_0402_5% 22 R280
R285
22_0402_5% 2 R281

CLK_PCI_EC
CLK_PCILOOP
CLK_PCI_SIO
CLK_PCI_TPM

22_0402_5%

2 R286

11
1

H49
H43
J48
K42
H40

CLK_PCI_EC_R
CLK_PCI
CLK_SIO
CLK_TPM

1

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI

C46
C44
E40

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

USB

DGPU_HOLD_RST#

K40
K38
H38
G38

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

GNT1#/GPIO51: Boot BIOS Strap bit 1 (BBS1)

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

GPIO19 => BBS_BIT0
GPIO51 => BBS_BIT1
Boot BIOS Strap
Bit 11
(BBS1)
0
1

AV5
AV10

Bit 10
(BBS0)
1
0

Boot BIOS
Destination
Reserved

D

PCI

1

1

SPI

0

0

LPC

*

NV_ALE

PCH EDS Rev1.5 P99, P98

Intel Anti-Theft Techonlogy

AY5
BA2

High=Endabled
NV_ALE
Low=Disable(floating)

AT12
BF3

@ RH164

C

2 OPT@ 1
0_0402_5%
R262
1 OPT@ 2
R161
0_0402_5%

SATA1GP/GPIO19: Boot BIOS Strap bit 0 (BBS0)

AT10
BC8

AT8

1

2

3

AY7
AV7
AU3
BG4

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

USB20_P1

USB20_N0
USB20_P0
USB20_N1
USB20_P1

<40>
<40>
<43>
<43>

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

<44>
<44>
<44>
<44>
<39>
<39>

USB20_N0
USB20_P0
USB20_N1

L-CONN
C

R-CONN
R-CONN
Smart Card

USB port 6,7 are disabled on HM76 and HM75.
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
USBRBIAS

USB20_N8
<39>
<39>
USB20_P8
New Card
USB20_N9
<43>
<43>
USB20_P9
USB port with
<23>
USB20_N10
USB20_P10
<23>
<40> Int. Camera
USB20_N11
<40>
USB20_P11
<36>Finger Printer
USB20_N12
USB20_P12
<36>
USB20_N13
<36> WWAN
<36>
USB20_P13
BT
22.6_0402_1%
RH165

Esata

Within 500 mils

PME#

PLTRST#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
PCH_GPIO9
PCH_GPIO10
CP_PE#

USB_OC0#
USB_OC1#

<40>
<44>

USB_OC4#

<40,43>

CP_PE#

For USB3.0, Left USB.
For Right power USB port
B

+3VALW_PCH

For USB port with eSATA.

<39>
USB_OC3#

PANTHER-POINT_FCBGA989
@

5
2

P

U8

IN1

USB_OC0#

4

O
IN2

G

1

USB_OC1#

PLT_RST#

2

2

3

CP_PE#

PCH_GPIO9

R151

R157
100K_0402_5%

2
1
2
1 10K_0402_5%
R1270
R1271 10K_0402_5%

USB_OC4#

USB_OC2#

TC7SH08FU(TE85L,F)

+1.8VS

USB30

+3VS

BUF_PLT_RST#

*

1K_0402_5%

NV_ALE

2
1
R1268 10K_0402_5%
2
1
R1267 10K_0402_5%
2
1
R1269 10K_0402_5%
2
1 @
R1306 10K_0402_5%
2
1
R1307 10K_0402_5%
2
1
R1308 10K_0402_5%

PCH_GPIO10

+3VS_DGPU

100K_0402_5%
1

+3VS_DGPU

O

G

A

DGPU_HOLD_RST#

1

C477
0.1U_0402_16V4Z
OPT@

RV49
10K_0402_5%
@

2
1
4
R261 OPT@ 0_0402_5%

2

5
P

1

A

PLTRST_VGA#

2

R165
100K_0402_5%
OPT@

Compal Secret Data

Security Classification
Issued Date

1

R413
1K_0402_5%
OPT@

<13>

2

3

TC7SH08FU(TE85L,F)

1

1

2

U20
OPT@
1
IN1
2
IN2

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

PLT_RST#

28

of

60

1

2

3

4

5

+3VALW_PCH

1
1
R61
R1284

KEEP LOW XXMS ACTIVE,
NOT TAKE ACTIVE ON
RISE/FALL EDGE

EC_SMI#

PM_LANPHY_ENABLE
D

2
R337
2
R338

1
10K_0402_5%
1
10K_0402_5%

PCH_GPIO28

PCH_GPIO57

<42>

EC_SCI#

<41>

EC_SMI#

PM_LANPHY_ENABLE

LID_SW_OUT#

<41>

1
R1325

22
10K_0402_5%
10K_0402_5%

11
R1323
R1274

2
10K_0402_5%
1
10K_0402_5%
12
10K_0402_5%
10K_0402_5%
1
R34
2
10K_0402_5%
1
R36

KB_RST#
1
R1278
VGA_PWROK_R
2
R339
PCH_GPIO22
21
CR_WAKE#
R352
R1280
2
CR_PE#
200K_0402_5%
1
ODD_DETECT#
R1286
2
PCH_GPIO6
200K_0402_5%

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

1
R1324
1
R1296
1
R1326

PCH_GPIO0

<26,45,57>

2
R147

CR_PE#

2
0_0402_5%

1
RH171
GPIO27_WAKE#

<37>

EC_SCI#

C10

WWAN_OFF#

CR_WAKE#

ODD_DETECT#
1
RH167 @

<23>

<36,41>

G2

T5

PCH_GPIO22

E8

PCH_GPIO24

E16

GPIO27_WAKE#_R

P8

PCH_GPIO28

K1

CR_WAKE#

K4

CE_EN

V8
M5

N2
M3

PCH_GPIO39
2
0_0402_5% PCH_GPIO48

WL_OFF#

WL_R_OFF#

V13
V3
D6

PCH_GPIO57

PCH_GPIO39

A4

A44

T1911

@

A45
A46

PAD

2
R365
1

WWAN_R_OFF#

R1275

PCH_GPIO35

T1913

@

A5
A6

B3
B47

BD1
BD49

PAD

B

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable

T1927

@

PAD

T1929

@

PAD

T1931

@

BE1

BE49

BF1

*

PAD

Can be configured as wake input to allow wakes from
Deep Sleep.
If not used then use 8.2-kΩ to 10-kΩ pull-down to
GND.
R328

TACH5 / GPIO69

TACH2 / GPIO6

TACH6 / GPIO70

TACH3 / GPIO7

TACH7 / GPIO71

T1933

@

BF49

1
R1287

+3VS

C40

B41

ODD_EN#

ODD_EN#

C41

PROJECT_ID0

A40

PROJECT_ID1

<34>

DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE

Set to Vss when LOW

PROJECT_ID2

GPIO8

+1.8VS
Weak internal
PU,Do not pull low

1 R1259 2
10K_0402_5%

LAN_PHY_PWR_CTRL / GPIO12

A20GATE

GPIO15

PECI

SATA4GP / GPIO16

TACH0 / GPIO17

SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS
TS_VSS1

STP_PCI# / GPIO34

TS_VSS2

GPIO35

TS_VSS3

SATA2GP / GPIO36

TS_VSS4

P4
AU16 GATEA20
P5

PCH_PECI_R

1
0_0402_5%

AY11

KB_RST#

+3VS

D

2
@ RH159

RH187
2.2K_0402_5%
GATEA20
H_PECI

<41>
<6,41>

2

1
RH189

1K_0402_5%
NV_CLE

<41>

H_SNB_IVB#

<6>

AY10

<6>
H_CPUPWRGD
2
1
T14
390_0402_5% H_THERMTRIP#
PCH_THRMTRIP# R1261
AY1

AH8

H_THERMTRIP#

CLOSE TO THE BRANCHING POINT

<6>

NV_CLE

INIT3_3V

AK11

PROJECT_ID2

1
R1279

2
10K_0402_5%

This signal has weak internal
PU, can't pull low

AH10
AK10

+3VS

SATA3GP / GPIO37

NC_1

SLOAD / GPIO38

VSS_NCTF_15

SDATAOUT1 / GPIO48

VSS_NCTF_16

PROJECT_ID2

VSS_NCTF_17

GPIO57

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2

PROJECT_ID0

BG48
BH3

@ 10K_0402_5%
1 OPT@ 2
R333
10K_0402_5%

T1908

PAD

PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
@

BJ45

T1912

PAD

0

0

QAQ11 (Optimus)

0

0

QAQ12 (UMA)

0

1

0

QAQ13 (Optimus)

0

1

1

QAT10 (UMA)

1

0

QAQ10 (UMA)
@

T1914

PAD

@

T1916

PAD

BJ5
BJ6
C2

C48
D1

@

D49

T1926

PAD

E1
E49

C

2
R408

1 TF@
10K_0402_5%

@

BJ44

BJ46

1 UMA@ 2
10K_0402_5%
R370
2
1 030@
10K_0402_5%
R409

PROJECT_ID1

BH47

BJ4

2

1
R1276

P37

SDATAOUT0 / GPIO39

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_18

PCH_GPIO48
WL_R_OFF#

PAD

1 @
10K_0402_5%
2 @
10K_0402_5%

TACH4 / GPIO68

TACH1 / GPIO1

RCIN#
D40

ODD_DETECT#
2
0_0402_5% WWAN_R_OFF#

CE_EN

1
RH166 @

EC_SCI#

C4

BMBUSY# / GPIO0

LID_SW#_R

PCH_GPIO35

<34>

<36,41>

CE_EN

2
R356
2
R355

E38

2
1
RH170 short@ 0_0402_5%VGA_PWROK_R

VGA_PWROK

WWAN_R_OFF#

1
10K_0402_5%
1
10K_0402_5%

PCH_GPIO6

CR_PE#

PCH_GPIO1

<35,41>

PCH_GPIO1

H36

U2
<37>

2
10K_0402_5%

A42

EC_SMI#
1
PM_LANPHY_ENABLE
0_0402_5%

short@

+3VS

C

<41>

PCH_GPIO0

GPIO

LID_SW#_R

1

T7

PCH_GPIO24

CPU/MISC

2
2
10K_0402_5%
10K_0402_5%

2
10K_0402_5%

UPCH1F

QAL50/51, PBL22: GPIO24 NC

NCTF

1
R1332
1
R1330

2

@

2
10K_0402_5%
2
10K_0402_5%

@

T1930

PAD

0
1

0

QAT11 (Optimus)

1

0

1

QAQ12 (vPro)

1

1

0

QAQ13 (vPro)

1

1

1

For TongFang: QAQ10 (UMA) / QAQ11 (Optimus)
For 030:
QAQ12 (UMA) / QAQ13 (Optimus)

F1

B

F49

PANTHER-POINT_FCBGA989
@

2 10K_0402_5%

1

GPIO27_WAKE#_R

@
R331

2 10K_0402_5%

1
@

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

+3VALW

Please refer to Huron River Debug Board DG 1.2

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

*

：：On-Die
voltage regulator enable
On-Die PLL Voltage Regulator disable

H
L

R325

1

2 1K_0402_5%

@

PCH_GPIO28

A

A

Compal Secret Data

Security Classification
Issued Date

2011/09/23

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

29

of

60

3

+1.05VS_PCH

1300mA

VSSADAC

1mA

VCCTX_LVDS[1]
VCCTX_LVDS[2]

BJ22

CH41

@

1

2

+VCCAPLLEXP

AN16
AN17
AN21

+1.05VS_PCH

AN26
AN27

PJPH1

AP21

@

2

C

1

2

1

2

C264
1U_0402_6.3V6K

2

1

C267
1U_0402_6.3V6K

2

1

C258
1U_0402_6.3V6K

1

C269
1U_0402_6.3V6K

2

C256
10U_0603_6.3V6M

1

PAD-OPEN 3x3m

AP23

+1.05VS_VCC_EXP

AP26

AT24

AN33
AN34

R369
0_0805_5%
2
1

+3VS

AP24

1

BH29

C270 +3VS_VCCA3GBG
0.1U_0402_10V7K

VCCIO[15]
VCCIO[16]
VCCIO[17]

+VCCAFDI_VRM

1

AP16

Place C265 Near BG6 pin
1

@ C265
1U_0402_6.3V6K

+1.05VS_PCH

BG6
+1.05VS_VCCAPLL_FDI
R364
2
1
AP17
0_0805_5% +1.05VS_VCCDPLL_FDI

2

AU20
+VCCP_VCCDMI

+VCCALVDS

C249

AM37

1

2

PCH Power Rail Table
Refer to PCH EDS R1.5
Voltage Rail
V_PROC_IO

1

1
+VCCTX_LVDS
2

AP36

VCC3_3[6]

VCC3_3[7]

VCCIO[19]

C310
0.01U_0402_16V7K

2

1

C366
0.01U_0402_16V7K
2

+3VS_VCC3_3_6

VCCIO[22]

V34

2

C254
0.1U_0402_10V7K

AT16

VCCIO[23]

VCCIO[24]

R366
0_0603_5%
2

+VCCAFDI_VRM

75mA

0.001

V5REF_Sus

5

0.001

Vcc3_3

3.3

0.178

VccADAC

3.3

0.063

VccADPLLA

1.05

0.075

VccADPLLB

1.05

0.075

VccCore

1.05

1.73

VccDMI

1.1

0.047

VccIO

1.05

3.799

VccASW

1.05

0.803

VccSPI

3.3

0.01

VccDSW

3.3

0.001

VccDFTERM

1.8

0.002

+1.5VS
+VCCP_VCCDMI

VCCCLKDMI

5

C311
0.1uH inductor, 200mA
22U_0805_6.3V6M

+3VS

0_0805_5%

1

VCCIO[20]

VCCDMI[1]

0.002

V5REF

2

1

V33

1

VCCIO[21]

S0 Iccmax
Current (A)

AP37

+VCCAFDI_VRM

VCCVRM[3]

3709mA

1.05/1.0

D

2
0_0805_5%

1
R423

L6
+1.8VS
0.1UH_MLF1608DR10KT_10%_1608
2
1

AM38

Voltage

+3VS

AK37

AT20
+VCCP_VCCDMI

AB36
+1.05VS_VCC_DMI_CCI

1

R359
0_0805_5%
2
1

1

2

+1.05VS_PCH

2

R361
+1.05VS_PCH
0_0805_5%
2
1

C255
1U_0402_6.3V6K

C

VccRTC

3.3

N/A

VccSus3_3

3.3

0.065

VccSusHDA

3.3

0.01

VccVRM

1.5

0.147

VccCLKDMI

1.05

0.075

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.050

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

C262
1U_0402_6.3V6K

VCCIO[25]
VCCIO[26]

VCCDFTERM[1]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

2mA

VCCDFTERM[2]

VCCDFTERM[3]
VCCDFTERM[4]

VCCIO[27]

VCCDMI[2]

10mA

VCCSPI

AG16
+VCCPNAND

AG17

1

AJ16

R360
0_0805_5%
2
1

+1.8VS

C263
0.1U_0402_10V7K

2

AJ17

R362
0_0805_5%
2
1
VPRO@

V1
+3V_VCCPSPI

1

C268
1U_0402_6.3V6K

2

PANTHER-POINT_FCBGA989
@

B

2

VCCIO[18]

FDI

@ R367
0_0603_5%
2

AK36

2

1

R363

2
+1.05VS_PCH

2

U47

C308

VCCAPLLEXP

HVCMOS

2
1
1UH_LB2012T1R0M_20%

VCCTX_LVDS[4]

DMI

0_0603_5%
+VCCAPLLEXP_R

VCCTX_LVDS[3]

U48

1

C309

+3VS

VCCIO[28]

VCCIO

@

RH210

AN19
+1.05VS_VCCDPLLEXP

LH3

10U_0805_6.3V6M

+1.05VS_PCH

1 0_0603_5%

@

DFT / SPI

2

VCCALVDS

VSSALVDS

40mA
R357

VCCADAC

1mA

CRT

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCC CORE

2

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

LVDS

2

1

C247
1U_0402_6.3V6K

2

1

C244
1U_0402_6.3V6K

D

1

C246
1U_0402_6.3V6K

2

C245
10U_0603_6.3V6M

1

1

C271

1

2

10U_0603_6.3V6M

POWER

UPCH1G

0.01U_0402_16V7K

+VCCADAC

+1.05VS_PCH

10U_0603_6.3V6M

L5
MBK1608221YZF_2P
2
1
0.1U_0402_10V7K

4

5

1 8111E@ 2
R414
0_0805_5%

+3V_M
+3VS
B

Intel recommand
VCCVRM==>1.5V FOR MOBILE

A

A

Compal Secret Data

Security Classification

Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

30

of

60

1

AA19

AA21

R379
0_0805_5%
2
1

AA24

AA26

+1.05VM_PCH

AA27

@

2

+1.05VS_PCH

2

PAD-OPEN 2x2m

C

2
+1.05VS_VCCA_A_DPL

1

2

2

1

2

AA31
AC26

AC27
AC29

1

2

AC31
AD29

AD31
W21

C289
1U_0402_6.3V6K

2

C312
220U_B2_2.5VM_R35

+

C286
220U_B2_2.5VM_R35

1

1
+1.05VS_VCCA_B_DPL
+
C288
1U_0402_6.3V6K

2
L14
10UH_LB2012T100MR_20%
1

2

AA29

C282
1U_0402_6.3V6K

+1.05VS_PCH

C292
1U_0402_6.3V6K

1

L16
10UH_LB2012T100MR_20%
2
1

C281
1U_0402_6.3V6K

1

2

C280
22U_0805_6.3V6M

1

C279
22U_0805_6.3V6M

1
1 +1.05VM_VCCASW

Short J6J6When No VPRO

VCCSUS3_3[10]
VCCSUS3_3[6]

+VCCSUS1
@ C276
1U_0402_6.3V6K

W23
W24

W26
W29
W31

W33

VCCASW[1]

VCCIO[34]

V5REF_SUS

VCCASW[3]

903mA

VCCASW[4]
VCCASW[5]

VCCASW[6]

VCCASW[7]
VCCASW[8]

VCCASW[9]
VCCASW[10]

VCCASW[11]
VCCASW[12]

VCCASW[13]
VCCASW[14]

VCCASW[15]

DCPSUS[4]

1mA

VCCSUS3_3[1]

1mA VCCSUS3_3[2]

VCCASW[16]

VCCSUS3_3[3]
VCCSUS3_3[4]

VCCSUS3_3[5]

R417
0_0603_5%
2
1

BF47

+1.05VS_VCCA_A_DPL

VCC3_3[8]

VCC3_3[2]

VCCASW[19]

VCCASW[20]

+1.05VS_VCCA_B_DPL

+1.05VS_VCCDIFFCLKN
C318
1U_0402_6.3V6K

AF17
AF33
AF34
AG34

+VCCDIFFCLK

+1.05VM_VCCSUS

+1.05VS_PCH

1

VCCADPLLA
VCCADPLLB

VCCIO[7] 75mA
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCAPLLSATA
VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCSSC

VCCIO[4]

2
R378

M26

1
0_0603_5%

A22

2

C305
0.1U_0402_10V7K

1

1

2

C313
0.1U_0402_10V7K

1

2

2

2

+PCH_V5REF_SUS
C294
0.1U_0603_25V7K

2
1U_0402_6.3V6K
0.1U_0402_10V7K

+5VS

R380
0_0603_5%+3VALW_PCH
2
1

N20 +PCH_V5REF_RUN

+3VS

N22
+3V_VCCPSUS

1

P20

P22

C283
1U_0402_6.3V4Z

R390
0_0805_5%
2
1

2

T34

R385
0_0603_5%
2
1
+3VS

AJ2

2

AH13

R384
0_0603_5%
2
1
C290
0.1U_0402_10V7K

+1.05VS_SATA3

R387
0_0805_5%
2
1
+1.05VS_PCH

C291
0.1U_0402_10V7K
1

AH14

C297
1U_0402_6.3V6K

+1.05VS_SATA3

AF14

AK1
AF11

AC16

+3VS

2

1

+VCC3_3_2

C284
+PCH_V5REF_RUN
1U_0603_10V6K
2

2

+3VS_VCCPCORE

AF13

C

1

+3VS

C285
0.1U_0402_10V7K

AA16

W16

D4
CH751H-40PT_SOD323-2

R381
100_0402_5%

+VCCAFDI_VRM
+VCCAFDI_VRM

+VCCSATAPLL

+1.05VS_VCC_SATA

+1.05VS_PCH

2
R391

AC17 +1.05VS_VCC_SATA
1

AD17

@ L13
10UH_LB2012T100MR_20%
2
1
+VCCSATAPLL_R
1
@ C296
10U_0603_6.3V6M

2

@ R389
0_0805_5%
+1.05VS_PCH
1

B

2

1
0_0805_5%

Place C296 Near AK1 pin

C300
1U_0402_6.3V6K

2

VCCASW[22]

V_PROC_IO

VCCASW[23]
VCCASW[21]

T21

V21
T19

R393

2

1 0_0603_5%

R394

2

1 0_0603_5%

R396

2

1 0_0603_5%

+VCCME_22

+VCCME_23

VCCRTC

PANTHER-POINT_FCBGA989
@

10mA

VCCSUSHDA

+3VALW_PCH

P32

R397

2

1 0_0603_5%

+VCCSUSHDA

1

C307
0.1U_0402_16V4Z
A

2

Issued Date

Compal Secret Data
2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Rev
B

4019IE

Date:
4

1

1

@
1
C314
CH66

P34

Security Classification

5

D5
CH751H-40PT_SOD323-2

+1.05VS_PCH

+1.05VS_VCCAUPLL

AN23
+PCH_V5REF_SUS
AN24

95mA
DCPSST
DCPSUS[1]
DCPSUS[2]

2mA

+RTCVCC

C304
1U_0402_6.3V6K

2

2

R377
100_0402_5%

2

T26

+3VALW_PCH

+5VALW_PCH

+3VALW_PCH

+VCCME_21

C303
0.1U_0402_10V7K

A

2

C302
0.1U_0402_10V7K

2

VCCIO[6]

2

BJ8

1

VCCIO[13]

+1.05VM_VCCSUS

+V_CPU_IO

1

P24

+1.05VM_PCH

T17
V19

R395
0_0603_5%
2
1

C301
4.7U_0603_6.3V6K

2

C316
1U_0402_6.3V6K

V16

+VCCSST

1

1

VCCIO[12]

55mA
AG33

+1.05VS_SSCVCC

+1.05VS_SSCVCC

C317
1U_0402_6.3V6K
C299
0.1U_0402_10V7K

@ R398
0_0603_5%
2
1

DCPRTC
VCCVRM[4]

75mA

+1.05VS_VCCDIFFCLKN

2
+1.05VM_PCH

BD47

R416
0_0603_5%
2
1

1

1
0_0603_5%

+3V_VCCAUBG
1
C298
0.1U_0402_10V7K

VCCASW[18]

+VCCAFDI_VRM

+1.05VS_VCCDIFFCLKN

2
+1.05VS_PCH

R376

2

0.1U_0402_10V7K

2

2
C315
1U_0402_6.3V6K

2

1

+3VALW_PCH

+3V_VCCPUSB
C287

1

SATA

+1.05VS_PCH

Y49

2

+3VS_VCCPPCI

MISC

B

+VCCRTCEXT

1

V23
V24

D

1
0_0603_5%

1

VCC3_3[1]

VCC3_3[4]

CPU

1

1

C306
0.1U_0402_10V7K

+VCCDIFFCLK

T24

VCCASW[17]

RTC

R399
0_0603_5%
2
1

2
R383

@

+3V_VCCPSUS

V5REF

HDA

+1.05VS_PCH

T23

+VCCA_USBSUS

VCCIO[5]
N16

2

C677
0.1U_0402_16V4Z
2@

T29

VCCASW[2]

Clock and Miscellaneous

2

DcpSus and DcpSusByp do not require Decoupling.
Stuffing Decoupling Caps may cause voltage
oscillations, when Internal 1.05 Voltage
Regulator is used. By CPET

DCPSUS[3]

1

2

+VCCDPLL_CPY

2

VCCSUS3_3[8]
VCCSUS3_3[9]

PCH_PWR_EN#

<45>

T27

1

+1.05VS_PCH

VCCAPLLDMI2
VCCIO[14]

119mA
AL24

1
@

2

AL29

@ C274
10U_0603_6.3V6M

3

2
1
R1382
0_0402_5%
1
@

1

+3VS_VCC_CLKF33

2
1
0_0603_5%
R375 +VCCAPLL_CPY_PCH

1

+VCCAPLL_CPY

VCCSUS3_3[7]

P28

+5VALW_PCH

+1.05VS_PCH

1

2

1
2

0_0805_5%

VCCIO[33]

VCC3_3[5]

P26

2

BH23

VCCIO[32]

DCPSUSBYP
3mA

R371
0_0603_5%
1
2
1
C295
1U_0402_6.3V6K
+1.05VS_VCCUSBCORE
2

N26

1

T38

@ R372

1

V12

+PCH_VCCDSW

Stuff C277
will make
@ L8
voltage 10UH_LB2012T100MR_20%
leakage

+1.05VS_PCH

VCCIO[31]

USB

2

+3VALW_PCH

VCCIO[30]

R388
20K_0402_5%

2
1
@ R415
0_0603_5%

VCCIO[29]

VCCDSW3_3

C272
0.1U_0402_10V7K

D

2

+VCCPDSW
C293
C277
0.1U_0402_10V7K
2
1
@
0.1U_0402_10V7K

G

2

T16

1

VCCACLK

D

+3VS_VCC_CLKF33

C278
1U_0402_6.3V6K

C273
10U_0603_6.3V6M

1

POWER

UPCH1J

AD49

S

+3VALW

1

+VCCACLK

R382
0_0603_5%
2
1

2

@ R374
0_0603_5%
2
1

+1.05VS_PCH

L7
10UH_LB2012T100MR_20%
2
1

+1.05VM_PCH

R392
0_0603_5%
R3732
1
0_0603_5%
2
1
Q14
@
AO3413_SOT23-3

+5VALW

PCI/GPIO/LPC

+3VS

1

2

3

4

5

@ R386
0_0805_5%
2
1

Friday, August 24, 2012

Sheet
1

31

of

60

UPCH1I

H5

AA17
AA2
AA33
AA3

D

AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD38
AD37

AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3

C

AF10
AF12
AD14

AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5

AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21

B

AJ24
AJ33
AJ34
AK12
AK3

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
F45
B7

UPCH1H
VSS[0]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]

VSS[1]
VSS[2]
VSS[4]
VSS[3]

VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[32]
VSS[31]

VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]

VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]

VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]

VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

VSS[43]
VSS[44]
VSS[45]

VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]

VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]

VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34

BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10

AL48
AM11
AM14
AM36
AM39
AM43

AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4

AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

PANTHER-POINT_FCBGA989
@

1

2

3

4

5

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[172]
VSS[171]

VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]

VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]

VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47

D

P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

C

B

A

A

PANTHER-POINT_FCBGA989
@

Compal Secret Data

Security Classification
Issued Date

2011/09/23

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Rev
B

4019IE

Date:
5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Friday, August 24, 2012

Sheet
1

32

of

60

1

2

3

4

5

SBIOS SPI Flash
<25>

PCH_SPI_MOSI

<25>

PCH_SPI_CLK

2
PCH_SPI_MOSI R401
2
PCH_SPI_CLK R402

D

<25>

2 R4927
1
4.7K_0402_5%
2 R4928
1
4.7K_0402_5%

R405
0_0603_5%
2
1
8111E@
2
1

+3V_M

5
6
1

PCH_SPI_CS#

PCH_SPI_CS#

+3VS

1
SBIOS_SI
33_0402_5%
1
SBIOS_CLK
33_0402_5%

7

3
8

U59

SI

2
PCH_SPI_MISO_R R403

2

SO

1
PCH_SPI_MISO
33_0402_5%

PCH_SPI_MISO

<25>

SCLK
D

CS

HOLD

WP
4

GND

VCC

32M W25Q32BVSSIG
8111E@

0_0603_5%
R411
VPRO@

C405
0.1U_0402_16V4Z
U59
64M W25Q64FVSSIG SOIC 8P SPI ROM
VPRO@

For EMI resuest.
C409 @
6P_0402_25V

2

@

1
R419
10_0402_5%

U59:
Vpro--SA000039A20
non-Vpro--SA00003K800

SBIOS_CLK

C413
12P_0402_50V8J

8MB
4MB
C

C

BIOS SPI Flash (2MByte*1) For Win8
PCH_SPI_MOSI
PCH_SPI_CLK

<25>

PCH_SPI_CS1#

+3VS
+3V_M

0_0603_5%
R422
VPRO@

5

6
1

PCH_SPI_CS1#

R421
0_0603_5%
2
1
8111E@
2
1

B

2 WIN8@ 1R404
SBIOS_SI1
33_0402_5%
2 WIN8@ 1R406 SBIOS_CLK1
33_0402_5%
R4932 1 WIN8@ 2
4.7K_0402_5%
R4933 1 WIN8@ 2
4.7K_0402_5%

7

3
8

U60 WIN8@

SI

SO

2

SBIOS_SO1

2 WIN8@ 1
PCH_SPI_MISO
R407
33_0402_5%

SCLK
CS

HOLD
B

WP
VCC

GND

4

16M MX25L1606EM2I-12G SOP 8P ROM
C406
0.1U_0402_16V4Z
WIN8@

P/N: SA000041N00

For EMI resuest.
@ C420

@ R420

2
6P_0402_25V

@
C421

1

SBIOS_CLK1

10_0402_5%

12P_0402_50V8J

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

33

of

60

1

2

3

4

5

SATA HDD Conn.

TPM 1.2

1WB_TPM@2
4.7K_0402_5%

R664
PM_CLKRUN#_R

+3VS_TPM

@
+5VS

1

1.2A

Place closely JP25 SATA CONN.
1

C387
10U_0805_10V4Z

2

C388
0.1U_0402_16V4Z

2

1

1

C389
0.1U_0402_16V4Z

C390
0.1U_0402_16V4Z

+3VS

+3VS_TPM

TPM@

2
0_0603_5%

1

2

R30

2

1
10_0402_5%

2
C768

1
15P_0402_50V8J

EMI
1

C764
0.1U_0402_16V4Z

D

2 @
R669
CLK_PCI_TPM

2

C765
TPM@
1U_0402_6.3V4Z

1

C419
TPM@
10U_0805_10V4Z

2

1
TPM@

1 IN_TPM@2
4.7K_0402_5%
R659 1 @
2
R663
4.7K_0402_5%

BADD

2

+3VS_TPM

D

BADD: IN_TPM PD, WB_TPM NC

Base I/O Address:
IN_TPM:
0 = 02Eh * 1 = 04Eh
WB_TPM:
Default:7EH-7FH
4.7K PD:EEH-EFH

JHDD

TPM@

1
R49

<25>
<25>

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

2
0_0603_5% C778

1
TPM@

0.1U_0402_16V4Z

C777

TPM@

2 1U_0402_6.3V4Z 2

+3VS_TPM

10U_0805_10V4Z

2

C415

1

1

10U_0805_10V4Z

C416
@
1U_0402_6.3V4Z
2

2

C417
0.1U_0402_16V4Z

2

C418
0.1U_0402_16V4Z

IN_TPM:
if support physically access
the platform, connect the pin
to 3.3V.
If this feature is not used,
the pin can be left open (it
has an internal pull-down).

JODD

GND
A+
AGND
BB+
GND

B

13
12
11
10
9
8
7

Place component's closely ODD CONN.
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2

C518 1
C519 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

C424 1
C425 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PTX_DRX_P2
SATA_PTX_DRX_N2

DP
V5
V5
MD
GND
GND

ODD_DETECT#_R
+5VS_ODD

0_0402_5%

2

0_0402_5%

2+5VS_ODD1
short@

1

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

R762
ODD_DETECT#

ODD_DA#_R

R763
ODD_DA#

SUYIN_127382FR013G109ZR_RV
+5VS

1

S

5
VSB

IN_TPM@
C766
18P_0402_50V8J

2
6
TPM_XTALI

1
3
12

SLB 9635 TT 1.2 TSSOP28P FW REV3.19
IN_TPM@

TPM_XTALO

18P_0402_50V8J
B

<29>

WB_TPM:
<25> SERIRQ PU At Page29

<25>

GPIO_IF, GPX and PP are optional.
Leave them open if not used.
U37

<28>

S IC WPCT200AA0WG TSSOP 28P TPM
WB_TPM@

G

Q59
SSM3K7002FU_SC70-3
@

@

1

For NON_TPM SKU Reserve

1

2

@

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

32.768KHZ_12.5PF_Q13FC1350000400
X3
IN_TPM@
C767 IN_TPM@

S

D

ODD_EN

@

<27>

Q55
SI3456BDV-T1-E3 1N TSOP6
@

C818
0.1U_0402_16V4Z

D

2
G

ODD_EN#

@

R772
0_0402_5%

SUS_STAT#

BOM
IN_TPM:IN_TPM@&TPM@
WB_TPM:WB_TPM@&TPM@
4

R764
1.5M_0402_5%

<29>

3

1

2

CS27
1U_0402_6.3V6K

R760
470K_0402_5%
@
A

6
5
2
1

3

2

+VSB

1

+5VS_ODD

R107
0_0805_5%
2
1

2

CONN@

TPM
SLB 9635 TT 1.1
LCLK
GPIO2
LFRAME#
GPIO
LRESET#
SERIRQ
CLKRUN#
NC
PP
NC
NC

TPM_XTALO_R
TPM_XTALI_R

IN_TPM@
22
11
R728
0_0402_5%TPM_XTALO
R729 IN_TPM@ 0_0402_5%
TPM_XTALI

<25>
<25>

short@

6
5
4
3
2
1

21
22
16
27
15
7

R726
SUS_STAT#_R
BADD
TPM_TEST1

1

C414

CLK_PCI_TPM
<28> CLK_PCI_TPM
LPC_FRAME#
<25,41,44> LPC_FRAME#
PLT_RST#
PLT_RST#
<6,28,35,36,37,39,41,42,44>
<25,41,44> SERIRQ 1
2
1SERIRQ
@
2
PM_CLKRUN#_R
<27,44> PM_CLKRUN#
0_0402_5%
R773 4.7K_0402_5%
R665
PP
+3VS_TPM
IN_TPM@

1

14
13

XTALO
XTALI

2

2

1

2
0_0402_5%

1@
28
9
8

LPCPD#
TESTB1/BADD
TEST1

LAD0
LAD1
LAD2
LAD3

2

26
23
20
17

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

+3VS_TPM

IN_TPM@
R668
10M_0402_5%
1
2

<25,41,44>
<25,41,44>
<25,41,44>
<25,41,44>

2
4.7K_0402_5%

1
R727

1

@

+3VALW_TPM

C

U37

+5VS_ODD

2

Default: Normal Mode, IN_TPM PD,
WB_TPM NC
4.7K PU: Test Mode

+5VS

SATA ODD Conn
1

+3VS_TPM

TPM_TEST1

TEST:

CONN@

10U_0805_10V4Z
1
C952

2
1 @
2
1 IN_TPM@
4.7K_0402_5%
R660
R661
0_0402_5%

1

24
19
10

GND
GND

<25>
<25>

VDD
VDD
VDD

23
24

+3VALW_TPM

+3VALW
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

2 0.01U_0402_25V7K

C412 1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

C513 1
C512 1
C410 1

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

GND
GND
GND
GND

C

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

1
2
3
4
5
6
7

4
11
18
25

GND
RX+
RXGND
TXTX+
GND

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

34

of

60

A

+3V_LAN

@

2
10K_0402_5%

PCIE_PRX_C_LANTX_P6

<26,42>

PCIE_PRX_C_LANTX_N6

<26,42>
<26,42>

PCIE_PTX_C_LANRX_P6
PCIE_PTX_C_LANRX_N6

RL20
RL24

<26,42>

8111E@0_0402_5%
0_0402_5%
8111E@

PCIE_PRX_RTLANTX_N6

16

CLKREQ_LAN#

2
10K_0402_5%

19
20

PLT_RST#

PLT_RST#

<6,28,34,36,37,39,41,42,44>

CLK_LAN
CLK_LAN#

CLK_LAN
CLK_LAN#

43
44

@

RL10

0_0402_5%

LAN_X1

@

RL9

0_0402_5%

LAN_X2

8111E@ RL8

0_0402_5%

LAN_WAKE#

GPIO27_WAKE#

<29,41>

<36,39,41,42>

RTL8105E

RTL8111E

NC

NC

Pin14

17
18

PCIE_PTX_C_C_RTLANRX_P6
PCIE_PTX_C_C_RTLANRX_N6

CLKREQ_LAN#

<26,42>
<26,42>

@
1
RL3

+3V_LAN

23
PCIE_PRX_RTLANTX_P6

25

1
RL25
CLKREQ_LAN#

1

22

B

8111E@
2 0.1U_0402_16V7K
1
CL1 8111E@
2 0.1U_0402_16V7K
CL2 1

IC function Part <26,42>

Pin15

NC

Pin38

1K ohm Pull-high

2
1 RL6
<27,36,39>
EC_SWI#
1K_0402_1%
+3VS
8111E@

10K ohm PD

28

EC_PME#

RL7
15K_0402_5%
8111E@

26
LAN_WAKE#
ISOLATEB

1K_0402_5%
RL22 21 8111E@ 12 10K_0402_5%
RL21
8111E@

33

+3V_LAN

+3V_LAN

34
35

ENSWREG

RL4
0_0402_5%

HSON
HSIP
HSIN

EECS/SCL
EEDI/SDA

CLKREQB

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

PERSTB

REFCLK_P
REFCLK_N

DVDD10
DVDD10
DVDD10

CKXTAL2

46

8111E@

1
RL5

LanWake O/D PU at Page31. Used
to reactivate PCIE slot's main
PWR rail and REF CLK

2
2.49K_0402_1%

ISOLATEB used to isolate 8111E
from PCIE

RL23
0_0402_5%
@

24
49

30
32

PWR

Vgs=-4.5V,Id=3A,Rds<97mohm
2
1

+LAN_VDD10

2

+LAN_REGOUT

+3V_LAN

JUMP_43X79
1
@

2

CL13
4.7U_0603_6.3V6K
8111E@

Layout Note: LL1 must be
within 200mil to Pin36,
CL13,CL9 must be within
200mil to LL1

1

+3VALW

1

2
1

1

C840
4.7U_0805_10V4Z
@

CL9 8111E@
0.1U_0402_16V4Z

2
2

C841
1U_0402_6.3V4Z
8111E@
1

+LAN_VDD10

27
39

DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

+LAN_VDD10

12
42
47
48

ENSWREG

2 8111E@ 1
LL2
0_0603_5%

+3V_LAN

+LAN_EVDD10

CL18
1U_0402_6.3V4Z
8111E@

+3V_LAN

+3V_LAN

Close to Pin 27,39,12,47,48

1

2

2

CL17
0.1U_0402_16V4Z
1 8111E@

AVDD10
AVDD10
AVDD10
AVDD10

REGOUT

8111E@
1 2 2 8111E@
CL10
CL12

1
0.1U_0402_16V4Z
0.1U_0402_16V4Z

1

2
CL6 8111E@

1

Close to Pin 21

3
6
9
45

2
CL4
2 8111E@
CL5 8111E@

1
0.1U_0402_16V4Z
0.1U_0402_16V4Z

21

EVDD10

GND
PGND

J35

LL1
8111E@
LL1,CL13
will be 2changed to
1
2.2UH_1008HC-472EJFS-A_5%_1008
2.2uH&4.7uF after EVT test

41

ISOLATEB

RSET

+3VALW TO +3V_LAN

10/100_LINK_LED
1 10K_0402_5%
RL1 2
2 8111E@ 1 10K_0402_5%
RL2 LAN_ACTIVITY#
8111E@

LANWAKEB

VDDREG
VDDREG

E

D

C

1
2
4
5
7 LAN_MDI0+
8 LAN_MDI010 LAN_MDI1+
11 LAN_MDI1LAN_MDI2+
LAN_MDI213 LAN_MDI3+
29 LAN_MDI3-

CKXTAL1

+LAN_VDDREG

ENSWREG
2

14
15
38

31
37
40

LED3/EEDO
LED1/EESK
LED0

HSOP

0.1U_0402_16V4Z

+LAN_EVDD10

2
CL7 8111E@

1

+LAN_VDD10

0.1U_0402_16V4Z

36
+3V_LAN
+LAN_REGOUT

RTL8111E-VL-CGT QFN 48P

2
0_0603_5%

CL28
4.7U_0603_6.3V6K
8111E@

CLKREQ O/D PU at PCH side
SMBDATA and GPO using EFuse
only without ASF function.

2

1

8111E@

60 mils

CL7 close to pin12

+LAN_VDDREG

1
LL3

2

CL29
0.1U_0402_16V4Z
1 8111E@

2

Close to Pin 3,6,9,13,29,41,45
+LAN_VDD10
1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
1
1

YL1

1

1

1

3

8111E@

4

2

CL26
12P_0402_50V8J
8111E@ 2

10/100_LINK_LED

3

GND

GND

LAN_X1

LAN_X2

0.1U_0402_16V4Z

2 8111E@ 1
LAN_ACTIVITY# R1709
LAN_R_ACTIVITY#
510_0402_5%
2
1
C2002 220P_0402_50V7K

2 8111E@ 1
R1713
510_0402_5%
LAN_LINK#

1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z

1

DL2

1

2

+3V_LAN

CL27
12P_0402_50V8J
8111E@ 2

CL11 close to pin42

1

<42>
<42>

LAN_1000_LED#
LAN_10/100_ LED#

CL11
0.1U_0402_16V4Z
2 8111E@

1
VPRO@

3

S DIO BAW56W SOT-323

LAN_ACT_LED#

12
11

+3V_LAN

8

VPRO@
RL36
0_0402_5%
<42>

JLAN1

2 VPRO@ 1
510_0402_5%
R1711

+3V_M

RJ45_MIDI3-

LAN_R_ACTIVITY#

7

RJ45_MIDI3+

6

RJ45_MIDI1RJ45_MIDI2-

LAN_MDI3LAN_MDI3+

4
5
6

LAN_MDI2LAN_MDI2+

7
8
9

LAN_MDI1LAN_MDI1+

10
11
12

LAN_MDI0LAN_MDI0+

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

24
23
22
21
20
19

18
17
16

15
14
13

1000P_0402_50V7K
1
2
1
75_0402_1%
RL11

CL41
2

1000P_0402_50V7K
RJ45_MIDI22
1 1
RJ45_MIDI2+
RL13
75_0402_1%

CL42
2

RJ45_MIDI11000P_0402_50V7K
2
RJ45_MIDI1+
1 1
75_0402_1%
RL15

Place CL34 colse
to LAN chip

RJ45_GND

RJ45_MIDI0RJ45_MIDI0+

CL34

1U_0402_6.3V4Z
VPRO@

LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1LAN_TX2+
LAN_TX2LAN_TX3+
LAN_TX3-

LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1LAN_TX2+
LAN_TX2LAN_TX3+
LAN_TX3-

RL28VPRO@0_0402_5%
RL29VPRO@0_0402_5%
RL30VPRO@0_0402_5%
RL31VPRO@0_0402_5%
RL32VPRO@0_0402_5%
RL33VPRO@0_0402_5%
RL35VPRO@0_0402_5%
RL34VPRO@0_0402_5%

Intel check:Better to put 4x 0.1uF bypass cap
near 4 central tap pin of Transformer.
A

1
CL36

9

SHLD1

14
13

Green LEDGreen LED+

2 1000P_1808_3KV7K

RL38
0_0402_5%

RJ45_GND

<42>
<42>
<42>
<42>
<42>
<42>
<42>
<42>

SHLD2
PR1+

2 VPRO@ 1
R1712
510_0402_5%

+3V_LAN

1

4

3

LIYO_101002-00803-3
+3V_M

NS892407 1G
CL34
0.1U_0402_25V4K
2 8111E@

PR4+

PR1-

1

10

LAN_LINK#
2
1
C2003 220P_0402_50V7K

RJ45_MIDI32
1
1000P_0402_50V7K
RJ45_MIDI3+
75_0402_1%
1 RL12

CL40
2

CL23,CL24,CL25 close to pin6,9,41, respectively

Yellow LED+
PR4-

PR2+

2

RJ45_MIDI0RJ45_MIDI0+

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

1
RL37
0_0402_5%

2

CL31

2

1

4

Compal Secret Data

Security Classification
Issued Date

LAN_GND

CL30

4.7U_0603_6.3V6K

CL39
2

UL5
1
2
3

8111E@

PR3+

3

RJ45_MIDI1+

Transformer

2
CL25

Yellow LED-

PR3-

4

RJ45_MIDI2+

8111E@

PR2-

5

3

0.1U_0402_16V4Z

CONN@

2
CL21

2
CL22 8111E@
2
CL23
8111E@
2
CL24 8111E@

0.1U_0402_16V4Z

Crystal

0.1U_0402_16V4Z

LAN Conn.

25MHZ_10PF_7V25000014

2
8111E@
CL19
2
CL20 8111E@

2011/09/23

2011/12/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Date:
B

C

D

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size
Document Number
Custom

Rev
B

4019IE

Friday, August 24, 2012

Sheet
E

35

of

60

2
0_0402_5%
WLAN_WAKE
WLAN_WAKE

EC_SWI#

BT_PWRON_R

<26>

CLKREQ_WLAN#

<26>
<26>

D

CLK_WLAN#
CLK_WLAN

<26>
<26>

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2

<26>
<26>

PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2

+3VS_WLAN 1
0_0402_5% VPRO@ 2R1434
<26>
<26>
<26>

0_0402_5% 1 VPRO@ 2R1431
0_0402_5% 1 VPRO@ 2R1430

CL_CLK_DMC
CL_DATA_DMC
CL_RST#_DMC

2

BT_PWRON

1

JMINI1
1 WLAN/ WiFi2
3 1
4
5 3
6
7 5
8
9 7
10
9
11
12
13 11
14
15 13
16
17 15
18
19 17
20
21 19
22
23 21
24
25 23
26
27 25
28
29 27
30
29
31
32
31
33
34
33
35
36
35
37
38
39 37
40
41 39
42
43 41
44
45 43
46
47 45
48
49 47
50
51 49
52
51
53
GND1 GND2

1 VPRO@ 2
R83
0_0603_5%
CM17

+1.5VS +3VS_WLAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BT_PWRON_R

1
C675
0.1U_0402_16V4Z
2@

2
4.7U_0805_10V4Z

D

+1.5VS
WL_OFF# <29,41>
PLT_RST# <6,28,34,35,37,39,41,42,44>

PLT_RST#

0.1U_0402_16V4Z
1

CM20

54

2

2

47P_0402_50V8J

PM_SMBCLK <11,12,26,39>
PM_SMBDATA <11,12,26,39>
R1435
0_0402_5% USB20_N13 <28>Bluetooth 3.0
2 USB20_P13 <28>
1 @
2
1
R44 @
10K_0402_5%
LED_WLAN# <43>
2
1
10K_0402_5%
R42 @

1
CM22

CM21

4.7U_0805_10V4Z

+3VS_WLAN

0.1U_0402_16V4Z

0.1U_0402_16V4Z

EMI

0.1U_0402_16V4Z

1

1

1
C374

2

@

C373
@

2

1

1

1

1

+3VS

C371

2

2

C372

C380

2

@

C381

C382
2 0.1U_0402_16V4Z
@

@

@

@
0.1U_0402_16V4Z

CONN@

C

BT_PWRON

CM19

2

47P_0402_50V8J

ACES_88910-5204

R1437

<41>

1

CM18

2
1K_0402_5%

short@
2
1
R1380
0_0402_5%

0.1U_0402_16V4Z
1

1

0_0402_5%

2

@

1
RH121

1 8111E@ 2
0_0603_5%
R87

1

<27,35,39>

EC_PME#

+3VS_WLAN

+3VS

2

<35,39,41,42>

+3V_M

1

2

3

4

5

Slot 1 Half PCIe Mini Card-WLAN
& BT3.0
RH122

0.1U_0402_16V4Z
0.1U_0402_16V4Z
C

Vpro SKU: please delete E51_TXD_R /RXD connection on JMINI1.

Slot 2 Half PCIe Mini Card-G/GPS (FULL Card)

+1.5VS

+3VS_FULL

C634

1
C667

+
150U_B2_6.3VM_R35M

0.1U_0402_16V4Z

2

1

+3VS_FULL

1

C637

C666

2

2

0.1U_0402_16V4Z
1
C615
1

2
2
4.7U_0805_10V4Z

1

0.1U_0402_16V4Z

2

C612
0.1U_0402_16V4Z

+3VS

Peak: 2.75A
2
Normal:
1.1A10_1206_5%
R662
1050mA

1

UIM_DATA

60mil+3VS_FULL

D19 @
CM1293-04SO_SOT23-6
4
CH1
CH4

2

3

UIM_CLK

Vn

Vp

CH2

CH3

UIM_VPP

5

+UIM_PWR

6

UIM_RST

JSIM

<26>
<26>

PCIE_PRX_C_WWANTX_N1
PCIE_PRX_C_WWANTX_P1

<26>
<26>

PCIE_PTX_C_WWANRX_N1
PCIE_PTX_C_WWANRX_P1

+3VS_FULL
A

short@

1

2 0_0402_5%
2 0_0402_5% E51_TXD_R
E51_RXD_R
short@
R683
100K_0402_5%

2

<41> E51_TXD
<41> E51_RXD

R682 1
R1333 1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

WWAN_OFF#
2
1
PLT_RST#
R1375 short@ 0_0402_5%

2
C429

1
22P_0402_50V8J

1

2

C664

@

2

1

2

C426

C1325
@

2

C665

C428
@

2

1
@

2

<29,41>

+3VS_FULL

<28>
<28>

USB20_N12
USB20_P12

2
10K_0402_5%

Up to 150MA, Default 8-10MA

+3VS

A

Compal Electronics, Inc.

Compal Secret Data
2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

Date:
4

1

1

short@
22
11
R1433
short@ 0_0402_5%
0_0402_5% PM_SMBCLK
R1432
PM_SMBDATA

MINI_SMBCLK
MINI_SMBDATA

USB20_N12
USB20_P12
1
R45
@

WWAN_OFF#

@

2

1

56P_0402_50V8

UIM_DATA

1

B

+UIM_PWR

UIM_CLK

@

CONN@
+1.5VS
+UIM_PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C1324

+3VS_FULL
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

Security Classification
ACES_88910-5204
CONN@

40mil
UIM_RST

7

0.1U_0402_16V4Z

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16

GND

1U_0402_6.3V4Z

<26> CLK_WWAN#
<26> CLK_WWAN

2
4
6
8
10
12
14
16

GND

1
2
3

56P_0402_50V8

CLKREQ_WWAN#

1
3
5
7
9
11
13
15

JMINI2
1
3
5
7
9
11
13
15

8

VCC
RST
CLK

22P_0402_50V8J

2
1
R638 short@ 0_0402_5%

UIM_VPP
UIM_DATA

GND
VPP
I/O

56P_0402_50V8

<26>

0_0402_5%
2
0_0402_5%

G1
G2
G3
G3

EC_SWI#

@
1
R701

53
54
55
56

EC_PME#

4
5
6

C427

R702

22P_0402_50V8J

B

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

36

of

60

2

C41,C43,C97 close U4 Pin5.
Pin5 -> 1000pF -> 0.1uF -> 10uF.
C42 close U4 Pin10.
C77 close U4 Pin37.
D

IC Function Part

R11
+3VS_READER
2
1
0.1U_0402_16V4Z
0_0805_5%
0.1U_0402_16V4Z

1
1
40mil C83
C44
1
C50
2
2

+3VS

C73

<6,28,34,35,36,39,41,42,44>

0.1U_0402_16V4Z

1

C52

<26>
<26>

1
C43

1
C42

2

2
10U_0805_10V4Z

2

10U_0805_10V4Z

1

2

2

1000P_0402_50V7K

<26>

1
C80
1
C51

PCIE_PRX_C_CARDTX_N5

<26>

2
0.1U_0402_16V7K
2
PCIE_PRX_CARDTX_N5
0.1U_0402_16V7K

PCIE_PRX_C_CARDTX_P5

<29>

CR_PE#

CR_WAKE#

PCIE_PRX_CARDTX_P5

11
12

2
1M_0402_5%

APTXN
APTXP

13

CPPE_N

OUT

IN

2

GND GND

3

4

24.576MHZ_12PF_X3G024576FC1H
388@

1

C54
15P_0402_50V8J
1
388@

C82
15P_0402_50V8J
388@

CR1_CD1N/WAKEN
CR1_CD0N

MSCD#
SDCD#

2

17
21

<43>

CR1_PCTLN
CR1_LEDN

MC_PWREN#

5IN1_LED#

SDCMD_MSBS_XDWE#

+3VS_READER

8
7
6
5

XD_RE

SLE3

0_0402_5%

C101 should be close to ChipSet for power
source for SDA3.0 3.3/1.8v signaling
2
1
20_0402_5%
R74 1 385@ SDCMD_MSBS_XDWE#
R75
0_0402_5%
XDWP_SDWP

TPBIAS
2
12K_0402_1%

SEL2

385@

2

1
R37

22_0402_5%

SEL1

2
R82

C

2

1

R78

XDCE_SDCLK_MSCLK

1

SDCMD_MSBS_XDWE#
2
2.2U_0603_6.3V4Z

1
C101

2
2 0_0402_5%
2
0_0402_5%
0_0402_5%

XDCE_SDCLK_MSCLK
SDCMD_MSBS_XDWE#
SDCD#
XDWP_SDWP
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7

1

2

2

1
3

R28
56_0402_5%
388@

2
CloseR411to@ Chip
0_0402_5%
2WCM-2012-900T_4P
2
1

2

R27
4.99K_0402_1%
388@

2
1

3

@ D20

2

1

10mil
C95
220P_0402_50V7K
388@

Q116 @
2N7002_SOT23

TPB-

L2
3

3

4
1 @

2 388@
10mil
R32 2 388@

+3V_MCVCC

R38

C1961 1

10U_0805_10V4Z
2

2 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

PJDLC05C_SOT23-3

1
388@
4

JP6

1
2
3
4

TPB+

S

C1960 1

TPBIAS

1
TPA1
56_0402_5%
56_0402_5%
TPA+

1

2

13
22
43

+3V_MCVCC

D

2
G

0_0805_5%
C1959 1

C1962

200K_0402_5%

2

1 385@
R71

7 IN 1 Conn

R29
56_0402_5%
388@

1

2

4.7U_0805_10V4Z

200K_0402_5%

2

1 385@
R23

APWR

1
R43

2

@

XD_ALE

Colay With JMB385; W/1394, mount JMB388;WO/1394, mount JMB385.
CR_PE# and CR_WAKE reserve for D3 mode

R48

1
R1677

2

1

0_0402_5%

2
1 385@ XDWP_SDWP
R80
0_0402_5%

2 388@ 1
R410 0_0603_5%

2

1
MC_PWREN#

1
1K_0402_5%

R31
R21

MSCD#

TAV33

40mil

TPS2061DRG4_SO8
@
R1676
300_0603_5%

MC_PWREN#

2 385@

SDCD#

Note:

1

MC_PWREN#

D

1
C76

2 389@ 1
R412
0_0603_5% 2 385@
R19 1
APREXT
R39

2
+3VS_READER
0.1U_0402_16V4Z

1
2
9.1K_0402_5%
12K_0402_1%

JREAD

1

B

1
1K_0402_5%+3VS_READER

2 385@
1
R20
2 385@ 1K_0402_5%
1
R18
1K_0402_5%

XD_CLE

0_0402_5%

+3V_MCVCC

OUT
OUT
OUT
FLG

1K_0402_5%

2 385@
XD_CD#

XDCE_SDCLK_MSCLK_R

@

GND
IN
IN
EN#

2

1

R40

389@

1394 Conn

+3VS

U49

1K_0402_5%

R17

XD_RB

+1.8VS_APVDD

24.576MHz--main: SJ10000EV00

Memory Card Power
1
2
3
4

10K_0402_5%

2

1

R22
XDWP_SDWP

XIN
XOUT
XD_CD#_R

JMB389-QGAZ0C QFN 48P

0_0402_5%
389@

2

2

15
16

40 mil

C82

7mil

1

C

1
@
R24
D1
CH751H-40PT_SOD323-2
1
2
@

XOUT

X1

JMB389 C

R12
+1.8VS_APVDD

48
47
46
45
43
XD_SD_MS_D0
42
XD_SD_MS_D1
41
XD_SD_MS_D2
40
XD_SD_MS_D3
SLE3
29
28XDCE_SDCLK_MSCLK_R
SEL2
27
26XD_CLE
25XD_D4
23XD_D5
22XD_D6
6 XD_D7
24XD_RE
49XD_RB
30XD_ALE
31SEL1
32
33TAV33
389@ R66 1
34TPB389@ R65 11
35TPB+
385@ R63
36TPA38
39TPA+
1 388@
14
R25
APWR

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
APGND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

2
0_0402_5%
CR_PE#_R

1
@
R26
0_0402_5%

XIN

R13

1
388@

7mil

APRXN
APRXP

0.1U_0402_16V4Z

External Crystal

0_0402_5%
389@

9
8

15mil

C97

<29>

C54

APREXT

APREXT

+3V_MCVCC

2

1

19
20
44
18
37

DV33
DV33
DV33
DV18
DV18

APCLKN
APCLKP

PCIE_PTX_C_CARDRX_N5
PCIE_PTX_C_CARDRX_P5

1
C53

C77

3
4

XRSTN#

Strap Pin Definition

5
10

APVDD
APV18

XRSTN
XTEST

7

APREXT: PCIE reference resistor
8.2Kused in JMB385C;
12Kused in JMB388A

0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS_APVDD 0.1U_0402_16V4Z

40mil

2
1
R141 100_0402_1%

PLT_RST#

1
2

<26> CLK_PCIE_READER#
<26> CLK_PCIE_READER

C52close U4 Pin18.

C41

2
0.1U_0402_16V4Z

1

1

2

3
QFN 48P CARD READER
JMB388-QGAZ0A
U4388@

4

5

IC PWR

C100
0.33U_0603_10V7K
388@

2

@

2
0_0402_5%
0_0402_5%
1

GND1
GND2

XD_CD#
XD_RB
XD_RE
XDCE_SDCLK_MSCLK
XD_CLE
XD_ALE
SDCMD_MSBS_XDWE#
XDWP_SDWP

7
15
6
24
34
44
45
46

SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS

B

TAITW_R013-P12-HM_NR
CONN@

2

CONN@

@ D21

0_0402_5%

12
11
14
18
20
16
9

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7

26
27
28
29
30
31
32
33

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP

D7@

388@
3
4
3
4
WCM-2012-900T_4P

2

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3
MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7

FOX_UV31413-WR50D-7F~N

1

L1

1 @
R46

1
2
3
4

5
6

2

2

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCE_SDCLK_MSCLK
MSCD#
SDCMD_MSBS_XDWE#

10
19
1
2
4
3
25
23
21
17
8
5

35
36
37
38
39
40
41
42

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

SD_VCC
MS_VCC
XD_VCC

2
1
3

2

SDCD#

C49
22P_0402_50V8J
1 @

MSCD#

C99
0.1U_0402_16V4Z

PJDLC05C_SOT23-3

Card Detect
1
1

3
2

2

1

1

1

C98
0.1U_0402_16V4Z

2
0_0402_5%
XD_CD#_R

R33
XD_CD# 2

DAN202UT106_SC70-3

C96
0.1U_0402_16V4Z

A

A

Note:
if use external PWR and change
+3V_MCPWR as control signal, Need BIOS
to change the Setting.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

37

of

60

2

3

4

RA1
2

CA57
RA32 0_0603_5%
2
1
+DVDD_IO
1
CA2
10U_0805_10V4Z

CA1
0.1U_0402_16V4Z

2

JA1
JUMP_43X39

+3VS

2

@

2

0.1U_0402_16V4Z
1
RA2
1
2
1
1BLM18PG181SN1D_0603CA44
1 +5VS
CA56
2
2
CA43
2
2
10U_0805_10V4Z
10U_0805_10V4Z

1

1

@

RA34
0_0402_5%

1

135 mA

1
CA7
CA8
10U_0805_10V4Z 0.1U_0402_16V4Z
2

2

+3VS_DVDD
+3VS

600 mA

+PVDD1

2

0_0603_5%
1

1

5

place close to chip
1
CA9

Ext. Mic/LINE IN
D

MIC1_LINE1_R_R
MIC1_LINE1_R_L

2
4.7U_0603_6.3V6K
MIC1_LINE1_R

place close to chip

2
1
CA10
4.7U_0603_6.3V6K
MIC1_LINE1_L
CA26
1U_0402_6.3V4Z
2
1

@

RA25 RA39

1K_0402_5%
0_0402_5%
2
1

2
1
MIC2_R
2 MIC2R_R
MIC2R_L
MIC2_L
CA28
RA26
1U_0402_6.3V4Z +MIC1_VREFO_L
1K_0402_5%
+MIC1_VREFO_R
+MIC2_VREFO

MIC

1

10U_0805_10V4Z

U143

22
21
17
16

31
30
29
15
14

AZ_SYNC_HD

AZ_SYNC_HD

<25>

AZ_RST_HD#

20K_0402_1%
C

CA18

1

2
0.1U_0402_16V4Z

<23> DMIC_DATA
1
<23> DMIC_CLK
RA18
1
MIC_SENSE
RA16
NBA_PLUG

place close to chip

2

11

LINE2_R
LINE2_L

SPK_OUT_R+
SPK_OUT_R-

MONO_OUT

SPK_OUT_L+
SPK_OUT_L-

47
4

EAPD
PD#

HP_R
HP_L

1
33_0402_5%

MIC
2

3
4

3
PESD5V0U2BT_SOT23-3

SPKR-

10P_0402_50V8J

2

2

HP_L

1
2

CA47 1

2 0.1U_0603_50V7K

CA48 1

2 0.1U_0603_50V7K

CA49 1
CA50 1

2 0.1U_0603_50V7K
2 0.1U_0603_50V7K

1
RA43

HP_R

1

CA11
100P_0402_50V8J
2
@

HP_L_L
1
HP_R_R
CA13
100P_0402_50V8J
2@

Function

<41>

Headphone out

PORT-B (PIN 21, 22)

Ext. MIC

1 RA8

SINGA_2SJ-S351-013
CONN@
B

3

2
0_0603_5%

1

2

EC_BEEP#

PCI Beep
<25>

PCH_SPKR

1 RA9

2

CA15
2
1

47K_0402_5%

MIC1_R
MONO_IN

0.1U_0402_16V4Z

1

PORT-F (PIN 16, 17)

5

D9

47K_0402_5%

2 RA48
1
4.7K_0402_5%
+MIC1_VREFO_R

Ex.MIC JACK

MIC1_R
2
1
MIC1_L
1K_0402_5%
2
RA46 1
RA45
+MIC1_VREFO_L
LA2
4.7K_0402_5%
FBMA-L11-160808-121LMT_0603
2
1
MIC1_L_L

2
1
1
LA8
FBMA-L11-160808-121LMT_0603
CA21
100P_0402_50V8J
2
@

JEMIC
AGND

1MIC1_R_R

5

A

2

SINGA_2SJ-S351-012
CONN@

D10

CA20
0.1U_0402_16V4Z

1
2
6
3

4

MIC_SENSE

CA22
100P_0402_50V8J
2@

1
RA11
10K_0402_5%

2

20K

4

MIC1_LINE1_R_R
MIC1_LINE1_R_L

PORT-C (PIN 23, 24)

PORT-E (PIN 14, 15)

AGND

NBA_PLUG

PACDN042Y3R_SOT23-3

PORT-A (PIN 39, 41)

39.2K

1
2
6
3

@

20K

PORT-D (PIN 35, 36)

PESD5V0U2BT_SOT23-3

2

39.2K

5.1K

CONN@

3

SPK_R+

GND
GND

Codec Signals

C
ACES_85204-0400N

2

1

JHP

MIC1_L

10K

10U_0805_10V4Z

1
2
3
4

Head Phone JACK

DGND

Beep sound
EC Beep

SENSE A

@

1

JSPK

1
2
3
4

SPK_RSPK_R+
SPK_LSPK_L+
DA9

SPK_R10U_0805_10V4Z

2
1

LA3
FBMA-L11-160808-121LMT_0603
LA4
2
1
FBMA-L11-160808-121LMT_0603
2
1

ACES_88231-02001

Impedance

3
PESD5V0U2BT_SOT23-3

1

CA39
@
2
1
0_0603_1%
short@
RA44

RA47
1K_0402_5%
2
1

Sense Pin

2

49

THERMAL_PAD

CONN@
JMIC

1

<25>
<25>

DA8

1

Close to Audio Chip

RA51
4.7K_0402_5%
2
1

1
2

RA7

1

@

SPK_L+

RA15
2
1
0_0603_1%
CA51
short@
@

SPKR+

MIC+MIC2_VREFO
CONN

DA10

2

<25>
AZ_BITCLK_HD
@
CA23

AGND

ALC259-VB5-GR_QFN48_7X7

B

10U_0805_10V4Z

SPKL+

AZ_SDOUT_HD
AZ_SDIN0_HD

Speaker Connector

SPK_L-

1

RA14
CA46
10U_0805_10V4Z 2
2
1
@
0_0603_1% short@
2

10_0402_5%

26
37
42
43
7

AVSS1
AVSS2
PVSS1
PVSS2
DVSS

2
1
0_0603_1%
short@
CA19
@

1

24
23
48

NC
NC
NC

SENSE_A
SENSE_B

EAPD
EC_MUTE#

AZ_SDOUT_HD
AZ_SDIN0_HD_R

2
RA6

D

2
10U_0805_10V4Z

placement
RA13near Audio Codec

SPKL+
75_0402_1%
SPKL-

75_0402_1%

2

2

30MIL/30MIL
RA4

2
10U_0805_10V4Z

2

1

place close to chip

@

GPIO0/DMIC_DATA
GPIO1/DMIC_CLK

13
18

6

CA6

SPKL-

5
8

BITCLK

1

SPKR+
SPKR-

RA5

JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP

2
3

+PVDD1
+PVDD2

40
41

SDATA_OUT
SDATA_IN

CA5

2
2
10U_0805_10V4Z 0.1U_0402_16V4Z

45
44

33
32

1

CA4

2

39
46

HPOUT_R
HPOUT_L

1

CA3

25
38

RESET#

19
110U_0805_10V4Z 28
27
AC_JDREF
34
35
AC_VREF
1CA14
CPVEE
36

DMIC_DATA
2 DMIC_CLK
20K_0402_1%
2
39.2K_0402_1% SENSE_A

<41> EAPD
<41> EC_MUTE#

PVDD1
PVDD2

SYNC

2
2
1
CA16
2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

2

MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO

1
9

PCBEEP_IN

10

+5VS

CA45
1U_0603_10V6K

CA17
2.2U_0603_6.3V4Z

MIC2_R
MIC2_L

AVDD1
AVDD2

RA10 2

1

CA35

12

DVDD
DVDD_IO

RA12
DVT NOT POP
RA12, USE0.1U_0402_16V4Z
JA1
2
1
1 +5VS
1BLM18PG181SN1D_0603
1
CA58
CA60
CA59
@
@
@

0.1U_0402_16V4Z

CA61

68 mA

MIC1_R
MIC1_L

1

+PVDD2

CA42
1U_0603_10V6K

<25>

2
100P_0402_50V8J
MONO_IN

RA3
1
0.1U_0402_16V4Z 2
0_0603_1%

+AVDD

20
1
CA12

place close to chip

3
1

A

2
@
PACDN042Y3R_SOT23-3

SENSE B

10K
5.1K

2011/09/23

Issued Date

PORT-H (PIN 37)

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PORT-I (PIN 32, 33)

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

38

of

60

U52

SUSP#

10

9

GND

CPUSB# Thermal_Pad

0.1U_0402_16V4Z

10U_0805_10V4Z

1

C2035

R102
1

EC_SWI#

<27,35,36>

1

+3VS
+3VS

RCLKEN

R1727
10K_0402_5%

R1726
10K_0402_5%

CLKREQ1#

D

2
G

3

RCLKEN1

USB20_R_N8
USB20_R_P8
CP_USB#

R100
1
@

+3VS

21

JEXP1

C2033

<11,12,26,36> PM_SMBCLK
2
PM_SMBDATA
<11,12,26,36>
0_0402_5%
+1.5VS_CARD

2
0_0402_5%

+3VALW_CARD
PERST1#

+3VS_CARD

EC_PME#

<35,36,41,42>

2
2
1

B
A

NC7SZ32P5X_NL_SC70-5
Q118
2N7002_SOT23

0.1U_0402_16V4Z

<28> CP_PE#
CLK_PCIE_EXPCARD#
CLK_PCIE_EXPCARD

<26>
<26>

PCIE_PRX_C_EXPTX_N3
PCIE_PRX_C_EXPTX_P3

<26>
0_0402_5%
<26>

PCIE_PTX_C_EXPRX_N3
PCIE_PTX_C_EXPRX_P3

4
CLKREQ_EXPCARD#

CLKREQ1#
CP_PE#

<26>
<26>

U53

Y

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1

10U_0805_10V4Z10U_0805_10V4Z
2
2

10U_0805_10V4Z
2

PERST1#

7

G577NSR91U_TQFN20_4x4

New Card Socket (Left/TOP)

+1.5VS

C2036

16

1 2

CP_PE#
(Internal Pull High to AUXIN) 18
CP_USB#
(Internal Pull High to AUXIN)
RCLKEN1

CPPE#

2

C2034

1

8

5

SYSON

SUSP#

NC

+3VALW_CARD

2

C2032

G Vcc

SYSON

PERST#

STBY#

40mil

2

2

1

<26>

3

<41,45,52>

<10,41,45,50,51,52,57>

SHDN#

+3VS_CARD

2

1

+3VALW_PCH

+3VS

Imax = 0.75A
C2031

1

1

19

2

60mils

1

1
Imax
=C2030
1.35A

2

PLT_RST#

PLT_RST#

OC#

SYSRST#

20
D

AUX_OUT

AUX_IN

6

+3VALW_PCH

15

+3VS_CARD

1
Imax = 0.275A
1
C2029
C2028

0.1U_0402_16V4Z

17

C2027

1

+3VS

3.3Vout
3.3Vout

3.3Vin
3.3Vin

+1.5VS_CARD

3
5

+1.5VS_CARD

10U_0805_10V4Z

2
4

+3VALW_CARD

40mil

+1.5VS

0.1U_0402_16V4Z

1.5Vout

1.5Vin

11
13

10U_0805_10V4Z

PWR Switch
1.5Vout
1.5Vin

12
14

<6,28,34,35,36,37,41,42,44>

1

2

3

4

5

Express Card

R59
1

2

27
28
29
30

S

WCM-2012-900T_0805
4
3
4
3

1
<28>
<28>

USB20_N8
USB20_P8

2

USB20_R_N8
USB20_R_P8

1
@
L26

2

1
R84

2
0_0402_5%

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

D

GND
GND
GND
GND
CONN@

C

C

This pin1 define need check

USB20_P5

2

1

1

USB20_N5_R
USB20_P5_R

SM@

SM@

2

2

SM@

1

2

+SC_PWR

CS31
1U_0402_6.3V4K

2

LS2
WCM2012F2S-900T04_0805

2

+5VS

1

SM@

SM@

2

+1.8V_SC

SM@

1
1

2
2

+3V_SC

SM@

CS28
0.1U_0402_10V6K

USB20_P5

4

2

1

1

Layout note: Close to PIN10

<28>

3

SM@

2

1

Layout note:
Close to PIN15
0.1U_0402_10V6K
CS22

USB20_N5

1

+5VS

1U_0402_6.3V4K
CS17

USB20_N5

+3V_SC

Layout note: Close to PIN11

<28>

4

1

SM@

ACES_88514-104N
CONN@

@

1

Layout note: Close to PIN4

SM@

3

+3V_SC

CS25
0.1U_0402_10V6K

2

CS21
0.1U_0402_10V6K

2
0_0402_5%

1
RS20

0.1U_0402_10V6K
CS18to PIN18
Layout note: Close

SM@

1
2
3
4
5
6
7
8
9
10
GND
GND

0.1U_0402_10V6K
CS24
Layout note: Close to PIN14

SM@

2
0_0402_5%

1
RS14

SC_RST
SCard0C6
SC_CLK
SC_DATA
SCard0Fcb
SCard0C8
ICCInsertN

1U_0402_6.3V4K
CS30

CS32
0.1U_0402_10V6K

Smart Card

1

CS26
Layout note:
Close to PIN13
1U_0402_6.3V4K

JSMART

1
2
3
4
5
6
7
8
9
10
11
12

+SC_PWR

SM@

2

B

B

1

+3V_SC

+5VS
+3V_SC

AU9540B55-GBS-GR
SM@

+3V_SC

2

2
SM@

US3

1
2
3
4

A0
A1
A2
GND

VCC
WP
SCL
SDA

@ SM@

@

1
2 RS17
47K_0402_5%

SC_SDA
SC_SCL
EEPWP
ICCInsertN
+3V_SC
+1.8V_SC

1

1
2 RS19
47K_0402_5%
1
2 RS11
47K_0402_5%

1

0.1U_0402_10V6K
CS20

2
1
RS21 @
10K_0402_5%

RS16
100K_0402_5%
SM@

2

SC_XTAL_Out
SC_XTAL_In

SC_XTAL_In

1
SM@ 2
RS15
1M_0402_5%
YS2
12MHZ_16PF_X5H012000FG1H-X

SC_XTAL_Out

2

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1

@

8
7
6
5

EEPWP
SC_SCL
SC_SDA
@ AT24C02BN-SH-T_SO8

2

1

SM@

1 CS16
SM@
2

2

18P_0402_50V8J

SM@

XO
XI
PWRSV_SEL
LEDCRD
LEDPWR
RESET
EEPDATA
EEPCLK
P1(6)
ICCInsertN
VDDH
VDDP
VDD
V18OUT

18P_0402_50V8J

+SC_PWR

+5VS
RS18 1 0_0402_5%
SC_RST 2
SC_CLK 2
RS13 1470_0402_5%
SM@
SC_DATA
USB20_N5_R
RS12
SM@
USB20_P5_R
2
1
+3V_SC
SC_DATA_R
+SC_PWR
4.7K_0402_5%

SCard0C8
SCard0C6
SCard0Fcb
SMIO_5VPWR
SCard0Rst
SCard0Clk
SCard0Data
DM
DP
AV33
SCPWR0
5VGND
5VInput
V33OUT

CS29
1U_0402_6.3V4K

SCard0C8
SCard0C6
SCard0Fcb

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1

RS22
10K_0402_5%
SM@

US4

1 CS23
SM@

2

PWRSV_SEL: (Default high)
High: Normal mode,
Low: Power Saving Mode
A

A

MP: to solve issue of "Smart Card also show in Device Manager
after plug out it", change US4 from SA000042I00 to SA000042I10.

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

39

of

60

100P_0402_50V8J

1 @ 2
2
100P_0402_50V8J
C8141
2
C8151 @ 100P_0402_50V8J
C816 @ 100P_0402_50V8J

1 @ 2
C793
100P_0402_50V8J
1 @ 2
100P_0402_50V8J
C7901
2
C791 @ 100P_0402_50V8J
@
2
1
100P_0402_50V8J
C7921
2
C795 @ 100P_0402_50V8J
1 @ 2
100P_0402_50V8J
C796
2
1
C797 @ 100P_0402_50V8J

KSO4

KSO3
KSO5
KSO14

KSO6

KSO7
KSO13

KSO8

1
+

U3TXDN0_L
USB20_P0_L

USB20_N0_L
U3RXDP0_L

U3RXDN0_L

RU9
KSI[0..7]

KSI[0..7]

KSO[0..15]

KSO[0..15]

<28>

<41,43>

@

3
2

4
1

CU2

CU3

CU4

1000P_0402_50V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z

2

1

4
1

2 2

U3RXDN0_L
98

U3RXDP0_L

4 4

U3RXDP0_L
77

USB20_P0_L

3

USB20_N0_L

YSDA0502C 3P C/A SOT-23

U3TXDN0_L

5 5

U3TXDN0_L
66

U3TXDP0_L

3 3

U3TXDP0_L

8

USB20_P0_L

Screw Hole
H2

+3VS_FP

H3

3
LID_SW#

<41>

0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

+3VS

2

1

2
0_0603_5%
2
0_0603_5%

+3VS_FP

@
H_3P0 @
H_3P0

+3VALW

1

1

2

H6

H4

H1

H18

H16

H8

H7

1

C122

1
R62
1
R69 @

1

1

C128

1

1

U34
APX9132ATI-TRL_SOT23-3

C

L15ESDL5V0NA-4 SLP2510P8

USB20_P0

USB20_P0

Finger Print

GND

DU2

109

U3RXDN0_L

0_0402_5%
USB20_N0_L

3

+3VL

2

U3TXDN0_L

LU3 WCM-2012-900T_0805
RU8 @ 0_0402_5%

C645
0.1U_0402_16V4Z

0_0402_5%

RU2
0_0603_5%

USB20_N0

USB20_N0

<41,43>

2

Lid SW

B

@

0.1U_0402_16V7K
USB3_TX0_N_C

USB3_TX0_N

<28>

2

2

1
RU4

USB30_GND
USB30_GND

DU1
1 1

@ 100P_0402_50V8J
@ 2
100P_0402_50V8J
@ 2
100P_0402_50V8J

VOUT

LU1 WCM-2012-121T_0805
3
4
3

1

CU12
2
1

10
11

0_0402_5%
U3TXDP0_L

4

GND
GND

@

RU5

0.1U_0402_16V7K
USB3_TX0_P_C

USB3_TX0_P

CONN@

<28>

VDD

CU1

<28>

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

SANTA_371394-1

ACES_85208-24071

@

2

C3606

CU6

2

GND1
GND2

D

CU11
2
1
CONN@

JUSB31

9
1
8
3
7
2
6
4
5

U3TXDP0_L

1 @ 2
C802
100P_0402_50V8J

KSO9

<28,43>

U3RXDN0_L

USB3_RX0_N

+USB_VCCB

@ 2
100P_0402_50V8J
2

1
C7981
C799
1
C800
1
C801

C

25
26

USB_OC4#

0_0402_5%

H9

@

@

@

@

@

H_3P0

H_3P0

H_3P0

H_3P0

H_3P0

H33

1

KSO1
KSO0

2
0_0402_5%

<28>

1

KSO2

<28>
USB_OC0#

U3RXDP0_L

2

2
@

RU6

USB_OC0#

1
R91 @

0_0402_5%

1

1

KSI1

1

1

KSI6

SYSON#

@

@

LU2 WCM-2012-121T_0805
4
3
4
3

1

KSI5

<43,45>

C13

0_0402_5%

RU7

USB3_RX0_P

1

C813

KSI0

2

@

<28>

1

KSI4

R90

SUSP

@

1

W=100mils

1

KSI3

<6,11,43,45>

@ RU27
2
1
0_0402_5%
2
1

1000P_0402_50V7K

1 @ 2
C8111
100P_0402_50V8J
2
C812 @ 100P_0402_50V8J
1 @ 2

0.1U_0402_16V4Z

KSI2

G547E2P11U

0.1U_0402_16V4Z

KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

CU5

KSO15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

150U_B2_6.3VM_R35M

KSO12

D

JKB

11 @ 22
C805
100P_0402_50V8J
100P_0402_50V8J
C804
@
@
2
1
100P_0402_50V8J
C807
1 @ 2
2
C8081
100P_0402_50V8J
C810 @ 100P_0402_50V8J

8 +USB_VCCB
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

2.5A

KEYBOARD CONN.

2
1For EMC
100P_0402_50V8J
C803
KSO11

1
2
3
4

4.7U_0805_10V4Z

UU1

+5VALW

KSO10

1

2

3

4

5

@
H_3P0 @
H_3P0

@
H_3P0

@
H_3P0X5P0N
B

C647
0.1U_0402_16V4Z
+3VS_FP

1
L56 @
1
R159

2

2

2

2
0_0402_5%

H11

H21

H12

@

H_2P3

H_3P0N

1
H_4P5

D15

1

1

3
3

@

@

@

PJDLC05_SOT23-3

H24

H23

H22

1

1

1

FD2

FD1

H25

1

USB20_R_P11

FD3

FD4

@

@
@
@
H_3P3 H_3P3 H_3P3
H_3P3

@

1

<41>

3

KILL_SW#

2

1

1

PCB Fiducial Mark PAD

USB20_R_N11

A

2

@

@
H_4P5 H_4P5

@

2

Diode added on Finger Print small board

100K_0402_5%
KILL_SW#

1

@

@
@
@
H_4P5 H_4P5 H_4P5 H_4P5

H_2P3

R580

DAN217_SC59

2

1

1
@

@

E&T_6905-F04N-00R
CONN@

H13

H10

+3VALW

D24
@

1

VGA H26

H32

1

USB20_R_N11
USB20_R_P11

H19
H30

1

3

1

JWLAN

CPU
1

USB20_P11

H31

1
2
3
4

1

USB20_N11

<28>

1
2
3
4

1

<28>

+3VALW

Break hole
JFP

WCM-2012-900T_0805
3
4
3

1

4

1

Kill Switch

0_0402_5%
2

1

R160
1

A

@

1

Compal Electronics, Inc.

Compal Secret Data

Security Classification
SW5
1BS003-1211L_3P

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

40

of

60

D

R738
@ 10_0402_5%

<29> GATEA20
<29> KB_RST#
<25,34,44> SERIRQ
<25,34,44> LPC_FRAME#
<25,34,44> LPC_AD3
<25,34,44> LPC_AD2
<25,34,44> LPC_AD1
<25,34,44> LPC_AD0

2

CLK_PCI_EC

1
C787
@ 22P_0402_50V8J

R739
2
+3VALW_EC
2
C789

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<28> CLK_PCI_EC
<6,28,34,35,36,37,39,42,44>
PLT_RST#
@ R761
2 <29> EC_SCI#
1
<35,36,39,42> EC_PME#
10K_0402_5%

47K_0402_5%
1

@ R768

+3VALW

1
0.1U_0402_16V4Z

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
EC_PME#

2
EC_PME#
10K_0402_5%

1

+3VL

ECRST#

2
0_0402_5%
GPIO27_WAKE#

<29,35>

<40,43>

<40,43>

KSI[0..7]

KSI[0..7]

KSO[0..15]

@

KSO[0..15]

C

1
R767
EC_PME#

When use EC_PME#, should pull
up to +3VL: if pull up to +3VALW,
the system will auto resume when
plug in AC at DC mode.

2
1
R755 2.2K_0402_5%
2
1
R756
2.2K_0402_5%
2
1
EC_SMB_CK1
R758 2.2K_0402_5%

+3VL

EC_SMB_DA1

+3VS

2 EC_SMB_CK2
1
R759 2.2K_0402_5%
EC_SMB_DA2

+3VALW

<45>

PCH_PWR_EN

1

+3VALW

R326
@

<27>

SLP_A#

<47,48> EC_SMB_CK1
<47,48> EC_SMB_DA1
To battery
& charger<13,26> EC_SMB_CK2
@
<13,26> EC_SMB_DA2
2
1
To
PCH & VGA
R819
100K_0402_5%
2
1
R817
100K_0402_5%
<27> PM_SLP_S3#
2
1
<27> PM_SLP_S5#
0_0402_5%
R754
<29> EC_SMI#

2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<43> WL_BT_LED#
<27> SLP_LAN#
SUSWARN#
<23> INVT_PWM
<6> FAN_SPEED
<42,50> PM_SLP_LAN#
<36> E51_TXD
<36> E51_RXD
<27> PM_PWROK
<48> GREEN_PWR
<44> NUM_LED#

<27>

1K_0402_5%
EC_SMI#
B

new added pin--Joyce 0928-2011

<27>

SUSCLK_R

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
WL_OFF_EC#
SLP_A#

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
PCH_PWR_EN_R
WL_BT_LED#
SLP_LAN#
SUSWARN#
INVT_PWM
FAN_SPEED
PM_SLP_LAN#
E51_TXD
E51_RXD
PM_PWROK
GREEN_PWR
NUM_LED#

1 short@ 2
0_0402_5%
R753
CRY1
CRY2
R757
100K_0402_5%

1
C783

2
20P_0402_50V8

1
2
3
4
5
7
8
10

12
13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
EC_SMB_CK2/GPIO46
SM
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

VR_HOT#

2
G
Q38
H_PROCHOT#_EC
2N7002_SOT23

H_PROCHOT#_EC

R731

1

2 10K_0402_5%

R725

1

2 10K_0402_5%

H_PROCHOT#

VR_HOT#

<47>

W L_OFF_EC#

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

21
23
26
27

63
64
65
66
75
76

SPI Device Interface
SPI Flash ROM

GPIO

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
BKOFF#/GPXIOA08
GPO PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPI

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

V18R

EC_BEEP# <38>
PM_SLP_A# <42>

EC_BEEP#
PM_SLP_A#
PWR_GPS_DOWN_R#

PWR_GPS_DOWN#

@

PCH_HOT#_R

<13,57>

BKOFF#

--Add net "PWR_GPS_DOWN#" for EC pin27
power
circuit modified --Joyce 0224/2012
0_0402_5%

BATT_TEMPA <47>
R4934 as
ADP_I <47,48>

BATT_TEMPA
Project_ID

ADP_I
Board_ID
PCH_HOT#_R
GREEN_PWR4

new added pin --Joyce 0922-2011
PCH_HOT#

HDA_SDO <25>
VCIN0_PH <47>
2
0_0402_5%

HDA_SDO
119 VCIN0_PH
120
126
128

1
R818

73
74
89 PCH_ENBKL
90
KILL_SW#
91
PWR_USB_EN#
92
93 BATT_FULL_LED#
95CAPS_LED#
PWR_ON_LED
121
BATT_CHG/LOW_LED#
127
SYSON

VR_ON
100PM_SLP_S4#
101
102
103 PCH_RSMRST#
104 LID_SW_OUT#
VCIN1_PH
105 H_PROCHOT#_EC
106 VCOUT0_PH
107
108 BKOFF#
PBTN_OUT#
PCH_APWROK
SA_PGOOD
110
112
114
115 EC_ACIN
EC_ON
116
ON/OFFBTN#
117
LID_SW#
118
SUSP#
CAMPWR_EN
124H_PECI

+EC_V18R

@

TP_DATA

+3VL

circuit modified R1210
--Joyce
0302/2012
2 10K_0402_5%
1

pin68

LID_SW#

Rb

PCH_ENBKL <27>
KILL_SW# <40>
PWR_USB_EN# <44>

100K_0402_5%

Project_ID
Rd
0
100K_0402_5%
13RM@
1

PCH_RSMRST# <27>
LID_SW_OUT# <29>
VCIN1_PH <47>

VCOUT0_PH <47,49>
BKOFF# <23>
PBTN_OUT# <27>
PCH_APWROK <27>
SA_PGOOD <53>

(QAQ10)

Rd

Vmin

0

0V

0.362V

0.375V 0.503V

0.621V

3 (QAQ13) 33K+/-5%

0.634V 0.819V

0.945V

4 (12-RM) 56K+/-5%

0.958V 1.185V

1.359V

5 (13-RM) 100K+/-5% 1.372V 1.650V

1.838V
B

1
C776

EC_ON <43,49>
ON/OFFBTN#
<43>
LID_SW# <40>
SUSP# <10,39,45,50,51,52,57>
CAMPWR_EN <23>
H_PECI <6,29>

2
100P_0402_50V8J

2
C820
KB_RST#

BATT_TEMPA

1
C788

EC_ACIN

C782
4.7U_0805_10V4Z

2
100P_0402_50V8J

2
C794

1
330P_0402_16V4Z

PLT_RST#
EMI request
close U43

KB9012QF A3 LQFP 128P

+3VL

+3VALW

@

2
R742

1
330K_0402_5%

1
330K_0402_5%

EC_ACIN

2

15P_0402_50V8J

1

1
0.1U_0402_16V4Z
@

D64

4

OSC

OSC

Vmax

0.155V

(QAQ11) 8.2K+/-5% 0.168V 0.250V

2
R747

1

2011/09/23

Issued Date

2011/12/30

Deciphered Date

Date:
3

A

<29,36>

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

<29,36>

W WAN_OFF#

Compal Electronics, Inc.

Compal Secret Data

Security Classification

<13,27,48>

WL_OFF#

WWAN_OFF_EC#

Y5 @
32.768KHZ_12.5PF_Q13MC14610002

5

ACIN

CH751H-40PT_SOD323-2
2
1
0_0402_5%
R748
2
1
R752
0_0402_5%

WL_OFF_EC#

3

NC

Vtype

0V

2 (QAQ12) 18K+/-5%

@

NC

Rd
33K_0402_5%
13@

Rd
18K_0402_5%
12@

Rd
56K_0402_5%
12RM@

SYSON <39,45,52>
VR_ON <54>
PM_SLP_S4# <27>

2

2

C

+3VL

100K_0402_5%

Rd
8.2K_0402_5%
11@

2

15P_0402_50V8J

2

1 @

Rd

Rd
0_0402_5%
10@

Rb
56K_0402_5%
Rev10@

Rb
33K_0402_5%
Rev04@

Rb
18K_0402_5%
Rev03@

Rb
8.2K_0402_5%
Rev02@

Project_ID

1
C785

2

1
VPRO@

Board_ID

Rc

2
100K_0402_5%
VSB_EN_R

BATT_FULL_LED# <43>
CAPS_LED# <44>
PWR_ON_LED <43>
BATT_CHG/LOW_LED# <43>

2
100K_0402_5%
2
100K_0402_5%

1
Ra

由 Board_ID去去去去去去去 VPRO的的的；
由 Project_ID去去去 Tongfang與1030, UMA2與 Op0mus。

1
R766
PCH_PWR_EN_R

VSB_EN

+5VS

R740 4.7K_0402_5%
2 2
1 1
R741
4.7K_0402_5%

TP_CLK

<26>

CRY1 @ 20M_0603_5%
CRY2

A

D

2 10K_0402_5%

1

R724

reserve forR749
ENE_CS board

1

2 10K_0402_5%
2 10K_0402_5%

0_0402_5%

R734

LE2
2
1
FBMA-L11-160808-800LMT_0603
ECAGND

@ C784

@

1

EC_GPS_DOWN#
WWAN_OFF_EC#

20mil

1

@

R732 1
R730

+3VS

2
100K_0402_5%

1
R733

PCH_HOT#
GREEN_PWR4 <48>
68
DAC_BRIG/GPIO3C 70
EN_DFAN1/GPIO3D 71
EC_GPS_DOWN# <13>
EC_GPS_DOWN#
IREF/GPIO3E--Delete
net "PWRMOS_TEMP", add net "GREEN_PWR4"for EC pin 76 as power
72
EN_DFAN1 <6>
CHGVADJ/GPIO3F
--Add net "EC_GPS_DOWN#" to EC
BT_PWRON <36>
EN_DFAN1
BT_PWRON
--Joyce 0224/2012
TP_ON/OFF# <43>
TP_ON/OFF#
2
1
83
EC_MUTE#/GPIO4A 84
R1211
10K_0402_5%
EC_MUTE#
USB_EN#/GPIO4B 85
CAP_INT#/GPIO4C 86
EC_MUTE# <38>
USB_EN# <44>
EAPD/GPIO4D 87 EC_MUTE#
Interface
TP_LED# <43>
TP_LED#
TP_CLK/GPIO4E 88 USB_EN#
EAPD <38>
EAPD
TP_DATA/GPIO4F
TP_CLK <43>
TP_CLK
TP_DATA <43>
97
2
1
CPU1.5V_S3_GATE/GPXIOA00 98 TP_DATA
R765 0_0402_5%
WOL_EN/GPXIOA01 99
@
CPU1.5V_S3_GATE <10>
HDA_SDO/GPXIOA02 109CPU1.5V_S3_GATE
VSB_EN <47>
VSB_EN
VSB_EN_R
VCIN0_PH/GPXIOD00

GPIO

S

<6,47>

PWR_GPS_DOWN_R#

DA Output

Bus

D

WWAN_OFF_EC#

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

AD Input

PS2

1

<54>

ECAGND

67

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

XCLKI/GPIO5D
XCLKO/GPIO5E

0.1U_0402_16V4Z

<47>

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

1

2

+EC_VCCA

ECAGND

EC_VDD/AVCC

1

UE1

3

LE1

AGND/AGND

2
2
0.1U_0402_16V4Z

+3VALW_EC

2
1
FBMA-L11-160808-800LMT_0603

C775
1000P_0402_50V7K

3

2

0.1U_0402_16V4Z
C772
1
2
1
2
C774
0.1U_0402_16V4Z C773
1000P_0402_50V7K
2
1

+3VALW

+3VL

+3VALW_EC

0.1U_0402_16V4Z
1
C770
1 C771

9
EC_VDD/VCC 22
EC_VDD/VCC 33
EC_VDD/VCC
96
EC_VDD/VCC
111
EC_VDD0
125
EC_VDD/VCC

1

@

11
24 GND/GND
35 GND/GND
GND/GND
94
113 GND/GND
GND0

R745
R746
0_0805_5%
0_0805_5%

69

4

5

+3VL

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

41

of

60

1

2

3

4

5

+3V_M

2 10K_0402_5%

1 @

R1232
U31

PCIE_PTX_C_LANRX_N6

@
<35,36,39,41>

R559

0_0402_5%

SMBus Device Address 0xC8

EC_PME#

VPRO@

VPRO@

1

VPRO@

VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8

XTAL_OUT
XTAL_IN

TEST_EN
RBIAS

CTRL_1P0

RES_BIAS

2

2

1

1
LAN_X2

VPRO@

2

4

VDD1P0_11

VSS_EPAD

LAN_TX1+
LAN_TX1-

<35>
<35>

23
24

LAN_TX2+
LAN_TX2-

LAN_TX2+
LAN_TX2-

<35>
<35>

LAN_TX3+
LAN_TX3-

LAN_TX3+
LAN_TX3-

<35>
<35>

6
1
2
5

+RSVD_VCC3P3_1
+RSVD_VCC3P3_2

4

+3.3V_M_OUT

47
46
37

+1.0V_LAN

D

+1.0V_LAN

R548
0_0805_5%~D
2
1

L29 @

2

1
REGCTL_PNP10

1

4.7UH_CBC2012T4R7M_20%~D

VPRO@

2 VPRO@ 1
4.7K_0402_1%~D
R554 2 VPRO@ 1
4.7K_0402_1%~D
R553

15
19
29

1 2.2K_0402_5%

Idc max=330mA

2

+3V_M

1

2

+1.05V_M

VPRO@
VPRO@

1

2

C490
1U_0603_10V6K~D
VPRO@

Place R548, C462, C463 and L29 close to U31
VPRO@ VPRO@ VPRO@
+3V_M

+1.0V_LAN

VPRO@

VPRO@

43

1

11

40
22
16
8

2

VPRO@

VPRO@
1

2

1

2

2
VPRO@

1

2

1

2

1

2

1

2

1

VPRO@

1

2

C1178
22U_0805_6.3V6M~D

GND

2

R562
3.01K_0402_1%

C485
33P_0402_50V8J

1

3

3
GND

C493
33P_0402_50V8J

1

R561
1K_0402_5%

1

12

VDD1P0_43

LAN_TX1+
LAN_TX1-

1 2.2K_0402_5%

R1231 2 @

C483
0.1U_0402_16V4Z~D

LAN_TEST_EN

VDD1P0_47
VDD1P0_46
VDD1P0_37

20
21

R1230 2 @

C1177
22U_0805_6.3V6M~D

30

25MHZ_20PF_7V25000016

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK

VDD3P3_15
VDD3P3_19
VDD3P3_29

PCH_SMLDATA0

C486
0.1U_0402_10V7K~D

XTALO
XTALI

LED0
LED1
LED2

PCH_SMLCLK0

C471
0.1U_0402_10V7K~D

32
34
33
35

9
10

2
VPRO@ 0_0402_5%

Y4

2

LAN_DISABLE_N
VDD3P3_OUT

26
27
25

<35>
<35>

C472
0.1U_0402_10V7K~D

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

22
10K_0402_5%
10K_0402_5%

C

LAN_X1

RSVD_VCC3P3_1
RSVD_VCC3P3_2
VDD3P3_IN

LAN_TX0+
LAN_TX0-

C488
0.1U_0402_10V7K~D

PAD
PAD

T142
T143

1

3

RSVD_NC

LAN_TX0+
LAN_TX0-

17
18

C487
0.1U_0402_16V4Z~D

+3V_M

R1144

SMB_CLK
SMB_DATA

CLKREQ_LAN#

13
14

C494
0.1U_0402_16V4Z~D

LAN_ACT_LED#
LAN_1000_LED#
LAN_10/100_ LED#

<35> LAN_ACT_LED#
<35> LAN_1000_LED#
<35> LAN_10/100_ LED#

11
@R545
R546
@

MDI_PLUS3
MDI_MINUS3

2 10K_0402_5% LAN_DISABLE#_R

1 R557
@

PM_LANPHY_ENABLE

28
31

MDI_PLUS2
MDI_MINUS2

PERp
PERn

PCH_SMLCLK0
PCH_SMLDATA0

<26> PCH_SMLCLK0
22 <26> PCH_SMLDATA0
11 @
R549 VPRO@10K_0402_5%
R555
0_0402_5%

+3V_M
<29>

41
42

PETp
PETn

MDI

PCIE_PTX_C_LANRX_P6

<26,35>

1
PCIE_PRX_VLANTX_P6
0.1U_0402_10V7K
VPRO@
PCIE_PRX_VLANTX_N6
2
0_0402_5%
VPRO@
PCIE_PTX_C_C_VLANRX_P6
2
0_0402_5%
VPRO@
PCIE_PTX_C_C_VLANRX_N6

PCIE

<26,35>

2
1C482
R556
1
R558

MDI_PLUS1
MDI_MINUS1

LED

PCIE_PRX_C_LANTX_N6

38
39

MDI_PLUS0
MDI_MINUS0

PE_CLKP
PE_CLKN

JTAG

<26,35>

CLK_LAN_R
CLK_LAN#_R

CLK_REQ_N
PE_RST_N

C468
0.1U_0402_10V7K~D

<26,35> CLK_LAN
<26,35> CLK_LAN#
PCIE_PRX_C_LANTX_P6

44
45

C470
22U_0805_6.3V6M~D

<26,35>

D

48
36

VPRO@

CLKREQ_LAN#_R
PLT_RST#
2
0_0402_5%
VPRO@
1 2
0_0402_5%
VPRO@
0.1U_0402_10V7K
VPRO@

1
1R563
2
R560
C469

SMBUS

2
0_0402_5%

1
R564
<26,35> CLKREQ_LAN#
<6,28,34,35,36,37,39,41,44>
PLT_RST#

C

7

Place C1178 close to pin5

49

REGCTL_PNP10

82579_QFN48_6X6~D
VPRO@

Note:
+1.0V_LAN will work at 0.95V to 1.15V

VPRO@

+1.0V_LAN POWER OPTIONS
Shared with PCH
1.05V SVR
STUFF: R548
NO STUFF: L29

R1200 Resistor Value:
3.01 kohm for Hanksville-M LOM
2.37 kohm for Hanksville-D LOM

* Internal SRV
STUFF: L29
NO STUFF: R548

Need to verify A3 silicon drive
power before removing C427
KDS crystal vender verify
driving level in A3

B

B

+3VALW
+1.05V_M

+1.05VM_PCH

PM_SLP_A#

PM_SLP_LAN

PM_SLP_LAN

Q56

3

2

Q57
2

D

2
G

VPRO@
AO3416_SOT23-3

S

2
+1.05VM_PCH

@

C496
VPRO@
1

1

C694
4.7U_0805_10V4Z
@

C497
0.1U_0402_16V7K
VPRO@

C695
1U_0402_6.3V4Z
2 VPRO@

+3V_M

1
1

C696
4.7U_0805_10V4Z
@

1

2

1

AO3413_SOT23
VPRO@
C498
0.01U_0402_25V7K

1

1

1

3

2

C495
0.1U_0402_16V7K
@

PM_SLP_A#

0.01U_0402_25V7K

2
S

PM_SLP_A

4

Q44A

<41>

<45>

31

2
1

S

VPRO@
2N7002_SOT23-3

2

1

2N7002DW-T/R7_SOT363-6

D

Q44B

5

2N7002DW-T/R7_SOT363-6

1

3

Q60

2
R461
470_0603_5%
VPRO@

R442
47K_0402_5%
VPRO@

D

2
PM_SLP_LAN G

1

PM_SLP_LAN#

3

<41,50>

Q50
2N7002E-T1-GE3_SOT23-3
VPRO@
2
G

6

1

11

2

R814
100K_0402_5%
VPRO@

G

2

+5VALW

R462
470_0603_5%
VPRO@

D

+3V_M

S

+5VALW

C698
1U_0402_6.3V4Z
2 VPRO@

2

A

A

Compal Secret Data

Security Classification
Issued Date

2011/09/23

2011/12/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Document Number

Rev
B

4019IE
Date:

5

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Size

Friday, August 24, 2012

Sheet
1

42

of

60

1
10K_0603_5%
1

+3VL

2

+3VALW

2

R154
100K_0402_5%
D8
2

100K_0402_5%
8
7

ON/OFFBTN#

1

3

<44,47>

1
LEFT_BTN#
RIGHT_BTN#

ACES_85201-0605N
CONN@

2

2

EC_ON

51_ON#

6
5
4
3
2
1

1

R155
10K_0402_5%
@

3

4

D

SW7
SW LTL-613NQR1
1

4

RIGHT_BTN#

2

5
6
+5VALW

<36>

1

LED_WLAN#
2N7002DW-T/R7_SOT363-6
2
1
1
R1442
WL_BT_LED#
0_0402_5%

TP_ON/OFF#

TP_ON/OFF#

SW6
SMT1-05-A_4P
1

4

2

5
6

<41>

3

C

<41>

5

Q229A

+3VS

PJDLC05C_SOT23-3

2
6

2 R210
1
10K_0402_5%

+3VS

3

LEFT_BTN#
RIGHT_BTN#
D16

D18

WL&BT LED

2 R214
1
10K_0402_5%

TP_CLK
TP_DATA

2

KSO0 <40,41>
KSI0 <40,41>
KSI2 <40,41>
KSI6 <40,41>

1

PWR_ON_LED#
ON/OFFBTN#_R
KSO0
KSI0
KSI2
KSI6

3

ACES_51524-0080N-001
CONN@

C

3

2

2

G1
G2

2

TP_CLK <41>
TP_DATA <41>

@

LEFT_BTN#

PJDLC05C_SOT23-3

9
10

1
2
3
4
5
6
7
8

1

5
6

JP7
1
2
3
4
5
6
7
8

SW8
SW LTL-613NQR1
1

@

C759
100P_0402_50V8J

<41,49>

Q19
2N7002_SOT23-3
@

S

<41>

C757
100P_0402_50V8J

2
G

D

0.1U_0402_16V4Z

GND
GND
6
5
4
3
2
1

3
CHN202UPT SC-70D

ON/OFFBTN#_R

2

JTP

1

Bottom Side

C755

+5VS

R156

1

@

1

@

Touch/B Connector

1

2
R152
2

R153 Side
@ 10K_0603_5%
TOP

1

2

3

4

5

Power Button/ PWR/B

4

3

+USB_VCCE

Left USB

Q229B 2N7002DW-T/R7_SOT363-6

R1
1

2
+5VS

C3
+5VALW
1
0.1U_0402_16V4Z

<6,11,40,45>

<40,45>

SYSON#

@

2

+5VALW

2
220_0402_5%

1
R204
YELLOW GREEN

2
220_0402_5%

RED

4

A

3

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

HT-297USD/UYG 0603 RED/YELLOW GREE

<41>
<37>

SATA_LED#

6

C12
0.1U_0402_16V4Z

MEDIA_LED#

1
R85

@
2
220_0402_5%

1

1

D

A

PWR_ON_LED#
Q6
2N7002_SOT23-3
2
G

2
R4
0_0402_5%

B

USB_OC4#

<28,40>

C14

2

0.1U_0402_16V4Z

3

1
C4

1

2

PJDLC05_SOT23-3
@
R163
1

Q230A
2N7002DW-T/R7_SOT363-6

2
0_0402_5%

<28>

USB20_N9

<28>

USB20_P9

4

1

1

1

+ C9
220U_6.3V_M

2

2

C10
0.1U_0402_16V4Z

+USB_VCCE

2

<25>
<25>

2

2

1

4

3

@
3

WCM-2012-900T_0805

C11
1000P_0402_50V7K

<25>
<25>

PWR_ON_LED

0_0402_5%
2

L57

1
R162
C2055 2
C2054 2

SATA_PTX_DRX_P4
SATA_PTX_DRX_N4

C2052 2
C2053 2

SATA_PRX_C_DTX_N4
SATA_PRX_C_DTX_P4

2
0_0402_5%
1
1
1
1

USB20_N9_R

JESATA

1
2
3
4

USB20_P9_R

5
6
7
8
9
10
11

0.01U_0402_25V7K
0.01U_0402_25V7K
SATA_PTX_C_DRX_P4
SATA_PTX_C_DRX_N4
0.01U_0402_25V7K
0.01U_0402_25V7K SATA_PRX_DTX_N4
SATA_PRX_DTX_P4

2

100K_0402_5%

1

TP_LED#
LED 19-213A/T1D-CP2Q2HY/3T 0603 WHITE

1

+5VS

2
220_0402_5%

ESATA

SHIELD
SHIELD
SHIELD
SHIELD

12
13
14
15

A

CONN@

TP_LED#

Issued Date

<41>

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/09/23

2011/12/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATICS, MB A8581
Size

4

3

2

Document Number

Rev
B

4019IE
Date:

5

GND
A+
AGND
BB+
GND

FOX_3Q318111-R33C3-7F

<41>

R169

LED8
1
R215

USB

VBUS
DD+
GND

2

3

S

1

2
0_0402_5%

1
R93

5
6
7
8

GND
GND
GND
GND

W=80mils

W=40mils

@

1

VCC
DD+
GND

SANTA_360117-1
CONN@

PJDLC05_SOT23-3

2
0_0402_5%

1
1
@

@ D11

USB20_P1_R

WCM-2012-900T_0805

ESATA

5IN1_LED#

2

<25>

PWR ON LED
LED6
2

3

D13

+3VS

R202
+5VALW
HT-191UYG5 0603 YELLOW GREEN

USB20_P1

4

+3VS
2N7002DW-T/R7_SOT363-6
3Q230B
+USB_VCCB

@
4

<41>

BATT_CHG/LOW_LED#
BATT_FULL_LED#

8
7
6
5

G547E2P11U SOP 8P

Vf=2.1V(typ),2.4V(max) for amber
Vf=2.2V(typ),2.4V(max) for green
If=25mA(max)

1
R203

5

1

4

+USB_VCCE

2
0_0402_5%
2
0_0402_5%
1

1
R9 1
R10

SUSP

1
2
3
4

USB20_N1_R

@
3

U6

1
2
3
4

@

B

2

1

USB20_N1

2

1

5

2

Q210B 2N7002DW-T/R7_SOT363-6

2

<28>

1
R5

4

3

BATT CHARGE/FULL
LED
LED5

C8
1000P_0402_50V7K

<28>

1

B

2

1

Q210A

+3VS

LED4
2
2
220_0402_5%
HT-191USD 0603 RED

2

2

C7
0.1U_0402_16V4Z

L3

2N7002DW-T/R7_SOT363-6
MEDIA_LED#
1

6

2 R199
1
10K_0402_5%

1

1

+ C2
220U_6.3V_M

1
R200

+USB_VCCB

JUSB1

1

HDD LED

0_0402_5%
2

W=40mils

3

1

HT-191UYG5 0603 YELLOW GREEN

2

LED2
2
2
220_0402_5%

1
R211

4.7U_0805_10V4Z

+5VS

Friday, August 24, 2012

Sheet
1

43

of

60

1

2

3

4

5

+3VS

EMI And ESD
Reserve R199,C207,R226,C208  0601

2

CLK_SIO_48M

CLK_PCI_SIO

CR7
10_0402_5%

2

Place closely pin 1

Place closely pin 18
D

CU13

<25,34,41>
<25,34,41>
<25,34,41>
<25,34,41>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

3
4
5
6

LPC_AD0
LPC_AD1
LPC_AD2

1

1

1
CC1
4.7P_0402_50V8C

CC2 @
4.7P_0402_50V8C

2
1
18
9

LPC_FRAME#
CLK_PCI_SIO
CLK_SIO_48M
PM_CLKRUN#

LPC_FRAME#
CLK_PCI_SIO
CLK_SIO_48M
PM_CLKRUN#

<25,34,41>
<28>
<26>
<27,34>

GPIO00
CTS0/GPIO01
RTS0/GPIO02
DSR0/GPIO03
DTR0/GPIO04
DCD0/GPIO05
RI0/GPIO06
SIN1/GPIO07
SOUT1/GPIO08

LAD0
LAD1
LAD2
LAD3

LPC_AD3

CR8 @
10_0402_5%

1

COM@

LFRAME#
LCLK
CLKIN
CLKRUN#

22

2

2

SOUT0
SIN0
SIRQ#
LRST#

DFT_EN

24

VSS

VCC

23

SIO_GPIO00
CTS1#
RTS1#
DSR1#
DTR1#
DCD1#
RI1#

@

1

@

CR5

CR6

1

0.1U_0402_16V4Z

@
@

LPC_AD1
2 4.7K_0402_5%
2 4.7K_0402_5%LPC_AD2

2 4.7K_0402_5%

1
COM@

1

2 4.7K_0402_5%
LPC_AD0
2 4.7K_0402_5%

@

2 4.7K_0402_5%

LPC_AD3
D

LPC_FRAME#
SERIRQ

TXD1
RXD1
2
SERIRQ1
PLT_RST#
PLT_RST#_R CR9
0_0402_5% COM@

CC3
KC3820_QFN24

Add CR7,CC1 for EMI test fail issue--0929-2011

1

CR2

CR3 1
CR4 1

21
12
13
14
15
16
17
19
20
11
10
8
7

CR1

SERIRQ <25,34,41>
PLT_RST# <6,28,34,35,36,37,39,41,42>

+3VS
COM@

Base Address Selection
mount : 4E
unmount : 2E

2

SIO_GPIO00

2

Reserve C292 for SIO_RST#  0608

@ CR10
470_0402_5%

CC4
0.1U_0402_16V7K

1

1

PLT_RST#

2

@
C

C

+5VALW
1
0.1U_0402_16V4Z

C5

PWR USB

2

+USB_VCCA

Max 2.5A
W=80mils

U7

R149
1

<41>

0_0402_5%
2

USB_EN#

2
1
R1381
0_0402_5%

2
<28>

USB20_N3

2

1

1

@
4
4
3
WCM-2012-900T_0805
2
1
0_0402_5%
R148
0_0402_5%
R137
2
1

1

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
G547E2P11U

USB20_N3_R

8
7
6
5

1

+USB_VCCA

JP1

2

1

C6
4.7U_0805_10V4Z

C676
0.1U_0402_16V4Z
2@

L54

B

1
2
3
4

USB_OC1#

<28>

R8
0_0402_5%

2

USB20_N4_R
USB20_P4_R

3

USB20_N3_R
USB20_P3_R

TXD1
RXD1
CTS1#
RTS1#

3
<28>

3

USB20_P4

1

4

+3VL

1
USB20_N4_R

@
4

1
R127

R581

R582
10K_0402_5%

USB20_P4_R

WCM-2012-900T_0805

D26

2
0_0402_5%

2

@

PWR_USB_EN#

3
51_ON#

BAV70W_SOT323-3

<41>
<41>

10K_0402_5%

1
PWR_USB_ON#

change from +3VALW to +3VL
since EC power source changed.
--Joyce 1110

+3VALW

1

2

USB20_N4

1

L53

2
<28>

2

USB20_P3

USB20_P3_R

2

<28>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

W=60mils

PWR_USB_EN#

NUM_LED#
CAPS_LED#
+3VS

DSR1#
DTR1#
DCD1#
RI1#
NUM_LED#
CAPS_LED#

PWR_USB_ON#

<41>

<43,47>

51_ON#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2

B

E&T_6916-Q26N-00R

A

A

Compal Secret Data

Security Classification

2011/09/23

Issued Date

Deciphered Date

2011/12/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

44

of

60

0.1U_0402_16V7K

to +3VS_DGPU

<26,29,57>

OPT@

VGA_PWROK

S

2

2

2

1

6

200K_0402_5%
3V_GATE

OPT@
100K_0402_5%

2

R435

Q46A
2N7002KDW 2N SOT-363-6

2

@

D

+3VS_DGPU

1

1

6

3

1

2
SUSP#

<10,39,41,50,51,52,57>

1

4

3

DGPU_PWR_EN

Q225B
2N7002KDW 2N SOT-363-6
OPT@

2

1
R440

4.7K_0402_5%

1

4

1

DGPU_PWR_EN#
Q225A
2N7002KDW 2N SOT-363-6
OPT@

SUSP
SUSP <6,11,40,43>
Q201A
2N7002KDW 2N SOT-363-6

2

3

1

6

<26,28,57>

2
1

SYSON#
DGPU_PWR_EN#
<40,43> SYSON#
OPT@
Q201B
Q191
2N7002KDW 2N SOT-363-6
D
2N7002_SOT23-3
2
5
G
<39,41,52> SYSON
2
S
R70 1
R441
10K_0402_5%
4.7K_0402_5%
@

R463
SUSP

0_0402_5%

3

2
@

5
4

R460

+0.75VS_R

RUN_ON_CPU1.5VS3#

Q198B
2N7002KDW 2N SOT-363-6

1

R796
100K_0402_5%

R1453
100K_0402_5%

A

2011/09/23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/12/30

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

2

2

2
R797
100K_0402_5%
OPT@

1

1

S

R459
470_0603_5%
OPT@

5
R826
22_0603_5%

0_0402_5%

6

+1.5V_R
SYSON#

2N7002KDW 2N SOT-363-6
Q198A

5

1

+5VALW +5VALW

+5VALW

+VGA_CORE

R458
470_0603_5%
OPT@

+0.75VS

1
3 +VCCP_R
SUSP

2

2

1

2
PCH_PWR_EN

R1446
470_0805_5%

<6,10>

C836
0.1U_0402_16V7K

PCH_PWR_EN#
Q46B
2N7002KDW 2N SOT-363-6

1
PCH_PWR_EN#
Q49
2N7002E-T1-GE3_SOT23-3

PCH_PWR_EN#

2
1

PM_SLP_LAN

2N7002KDW 2N SOT-363-6

2
<42>

Q197B

4

6 +1.05V_M_R
Q197A

2N7002KDW 2N SOT-363-6

A

3 1

5

10mil

PCH_PWR_EN#

Q188
2N7002_SOT23-3
OPT@

C

R804
470_0402_5%

4

R807

+VSB

820K_0402_5%
1
2

+5VALW

2

2

2

2

C838
1U_0402_6.3V4K

1
1

Q13B
2N7002KDW 2N SOT-363-6
OPT@

5

1
R1445
470_0805_5%

40mil

1

3

C837

B

Q227B
DGPU_PWR_EN#
2N7002KDW 2N SOT-363-6
<31>
OPT@

+1.5V

2

2

1

R1447
470_0805_5%
VPRO@

4

1

OPT@

+5VALW

2
G

+1.05VS_VCCP

+3VALW_PCH

4

2

470_0805_5%

1

2

1

R813
100K_0402_5%

<41>

+1.05V_M

470_0805_5%

6
1

2
1

D

@

J1

2

@

D

Q37B

5
2N7002KDW 2N SOT-363-6
2N7002KDW 2N SOT-363-6
SUSP

JUMP_43X79
SI7326DN-T1-E3_PAK1212-8
U25
1
2
5
3

20mil

3

R805
470_0603_5%
OPT@

5

C848
0.1U_0603_25V7K
2 OPT@

2

10U_0603_6.3V6M

Q13A

2
2N7002KDW 2N SOT-363-6
VGA_PWROK#
OPT@

2
OPT@ 2

1

1

1

2
DGPU_PWR_EN# Q227A
2N7002KDW 2N SOT-363-6
OPT@

+VSB

2
G

1
R432

OPT@
R430
820K_0402_5%
OPT@

2

6

200K_0402_5%

2

2
1 R431
220K_0402_5%

1

1

820K_0402_5%
1
2

R808

R429

1U_0402_6.3V4Z

FDS6676AS_SO8
1
OPT@
1
C473
OPT@
2
OPT@

2

3

2 OPT@

+VSB

2

R146

C853
1U_0603_10V4Z

2

10U_0603_6.3V6M
2
OPT@

B

470_0805_5%

6
1
2
3
4

S
S
S
G

3

1

SI4800BDY_SO8
OPT@

1

C854
10U_0603_6.3V6M

C852

2

R789
820K_0402_5%

1
C475OPT@
4.7U_0805_10V4Z

1

4

8
7
6
5

C835

Vgs=10V,Id=14.5A,Rds=6mohm

+1.05VS_DGPU

2

2

2
1 R786
220K_0402_5%
Q37A
+VSB

1

@

FDS6676AS

3

D
D
D
D

+1.05VS_PCH

2
1
Q40 JUMP_43X79
1
D
S 2
D
S 3
D
S 4
D
G

C834

4

+1.05VS_DGPU
J4

R783

1

1

OPT@

C481

4.7U_0805_10V4Z

G

1
C697
1U_0402_6.3V4Z
2 OPT@

1

1

C829
4.7U_0805_10V4Z

Short J1 for PCH VCCSUS3.3

8
7
6
5

C492
0.01U_0402_25V7K
1@

2

+3VALW TO +3VALW(PCH AUX Power)

6

3
1

D

2
Q54
AO3413_SOT23
OPT@

2

1
C828
1U_0402_6.3V4Z

C839
10U_0603_6.3V6M

R426
47K_0402_5%
OPT@

2

+3VALW

1

Q43

S

1

2

1
DGPU_PWR_EN#

2N7002KDW 2N SOT-363-6
5
2N7002KDW 2N
SOT-363-6
SUSP

1
2
3
4

+1.5VSDGPU

C478

C

Q36B

S
S
S
G

SI4856ADY_SO8

+1.5V to +1.5VSDGPU
+1.5V

C491
0.1U_0402_16V7K
OPT@

0.1U_0402_16V7K
0.1U_0402_16V7K

2

R788
330K_0402_5%

2

1

D
D
D
D

+3VS_DGPU

+3VS

2

+VSB

1

+3VS

2
1 R785
47K_0402_5%
Q36A

Q34

8
7
6
5

2

1

2

RUN_ON

+1.5VS

C845

0.1U_0603_25V7K

C846

1

1

4.7U_0805_10V4Z

5
2N7002KDW
SOT-363-6
2N7002KDW
2N2N
SOT-363-6
SUSP

C832

+1.5V

2

4

Q35B

2

1 SI4800BDY_SO8

1

R787
330K_0402_5%

2

2

Vgs=10V,Id=14.5A,Rds=6mohm
C842

1

R782

2

1

+VSB

Q35A

2

1
2
3
4

S
S
S
G

2
C827
4.7U_0805_10V4Z

1

6
C831

1

1

D
D
D
D

0.1U_0402_25V6

2

3 1

2
1 R784
47K_0402_5%

Q33

8
7
6
5

1

2

1U_0402_6.3V4Z

1

1

1

C826
1U_0402_6.3V4Z

2

R781

1

C830

2

2

2

1

470_0805_5%

2

0.022U_0402_25V7K

0.1U_0402_16V7K

1
2
3
4

+5VS

C844

0.01U_0402_25V7K

1

S
S
S
G

SI4800BDY_SO8

C847
4.7U_0805_10V4Z

2
D

D
D
D
D

+5VALW

2

4

8
7
6
5

C843

C833

2

1
4.7U_0805_10V4Z

C825

Q32

4.7U_0805_10V4Z

+3VS
1
C824

+3VALW

1

Vgs=-0V,Id=9A,Rds=18.5mohm

+1.5V to +1.5VS

+5VALW TO +5VS

3

0.1U_0402_16V7K
0.1U_0402_16V7K

1

2

3

4

5

+3VALW TO +3VS

4

3

2

SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

45

of

60

1

2

3

4

5

Power block
CPU OTP

Page 47

Turn Off

D

Input
Switch

DC IN

D

B+
+3VALWP: TDC:6A
+5VALWP: TDC:4A
RT8205LZQW(2) WQFN

Page 48

CHARGER
CC:0A~3.64A
CV:12.6V(6cell)
BQ24725RGRR

Always
Page 49

+1.8VP: TDC:3A
SY8033BDBC

SUSP#
Page 50

Page 48
C

Battery

DGPU_PWR_EN
B

+VGA_CORE
TDC:23A
ADP3211AMNR2G

C

SUSP#

+1.05VSP: TDC:12A
TPS51212DSCR

Page 51

+1.5VP: TDC:13A
0.75VS: TDC :2A
RT8207MZQW

Page 52

SYSON
SUSP#

B

Page 57

+VCCSAP: TDC:5A
TPS51461RGER

+VCC_CORE
TDC: 36A
NCP6132A

VR_ON

+1.05VSP_PWRGOOD
Page 53

Page 54

+GFX_CORE
TDC: 21.5A
NCP6132A

VR_ON
A

A

Page 54

Compal Secret Data

Security Classification

2011/10/31

Issued Date

2012/12/31

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019IE

Date:
5

4

3

2

Friday, August 24, 2012

Sheet

46

of

60

1

Compal

@ PR8

KB930@ PR10 0_0402_5%

VCOUT0_PH

2

3

2

1

+3VL

1

6.49K_0402_1%

41

PR22
0_0402_5%
2

VSB_EN

1

2

1
PR3

2
1

PH1

2

2

2

D

S

2
G

PQ3
2N7002KW 1N SOT323-3

2

2

2

PR17
1K_0402_1%

PQ2
TP0610K-T1-E3_SOT23-3

+VSB

VSB_N_001

VSB_N_003
1

PR16
1

1

SPOK

2

48

PR23
1K_0402_1%
2
1
PC10
.1U_0402_16V7K

1
3
PJSOT24CW_SOT323-3

PJSOT24CW_SOT323-3

2

1

2

2

PD1

@ PR15
0_0402_5%
2
1

3

1

@ PR14
100K_0402_1%

BATT_B/I
PR12
1K_0402_1%

PD2
TH

1

EC_SMCA

@ SINGA_2BA1514-000111F

1

PR13
22K_0402_1%
2
1

PC8
0.1U_0603_25V7K

VL

1

2

PC7
0.01U_0402_25V7K

2

2

1
2
PR11
100K_0402_1%

B+

1

1
2

PC6
1000P_0402_50V7K

PC9
0.22U_0603_25V7K

BATT+

9
8
7
6
5
4
3
2
1

EC_SMDA

2

3

41ECAGND

38VCIN0_PH

38VCIN1_PH

PL4
HCB2012KF-121T50_0805
2
1

9
8
7
6
5
4
3
2
1

PR501
KB9012@
PR20
0_0402_5%
@
100K_0402_1%
2
1

+3VL

38,48

VMB

PJP1
11
10 GND
GND

1

UMA@ PR1
OPT@ 309K_0402_1%

0_0402_5% MAINPOWN 48
1

PR500
PR21
KB9012@
@
0_0402_5%
100K_0402_1%
2
1

1

1

2

7.87K_0402_1%

2
1
KB930@ UMA@
ADP_OCP_2
51.1K_0402_1%

2

5

100K_0402_1%_NCP15WF104F03RC

PL3 38 H_PROCHOT#_EC
HCB2012KF-121T50_0805
2
1

2
0_0402_5%
KB9012@

1
PR5
10K_0402_1%
KB930@

PR6

PR6

2

2

OTP_N_002

6

G718TM1U_SOT23-8

OTP_N_003

3

PR9

OT2 RHYST2

1

7

100K_0402_1%

4

2
G
ADP_OCP_1
1N SOT323-3
S 2N7002KW

1

GND RHYST1
OT1 TMSNS2

PR1
OPT@ 47.5K_0402_1%

PR7

2
3

8

1

PQ1

VCC TMSNS1

2

D

PU1 KB930@

1

1

1

5,38 H_PROCHOT#

1

PR4

2

+3VS
100K_0402_1%

@ PC5
0.1U_0603_16V7K

2

ADP_I

PR2
1
2
KB9012@
13.7K_0402_1%

38,47

1

1
2

PC4
100P_0402_50V8J

1
2

+EC_VCCA

PC3
1000P_0402_50V7K

1
2

2

SANTA_322121-1

PC2
100P_0402_50V8J

1

1

1
2
3
4
5

PC1
1000P_0402_50V7K

ADPIN

PJPDC1

V+
GND
GND
GND
GND

PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
VL

VIN

PL2
HCB2012KF-121T50_0805
2
1

2

DCIN jack P/N:DC301008L00,
need doble confirm P/N with ME

For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU1 circuit, but keep
PH1, PR1, PR2,PR4,PR7,PR9,PQ1

KB930@

PL1
HCB2012KF-121T50_0805
2
1

D

C

B

A

PR18
100_0402_1%

PR19
100_0402_1%

1

BATT_TEMPA 38

2

1

VIN
3

3

EC_SMB_DA1 38,47

PD20 @
RLS4148_LL34-2

PQ100
TP0610K-T1-E3_SOT23-3 @

3

PR300
@ 68_1206_5%

1

@
PR301
68_1206_5%

2

RTC Battery

1

1

PD21
@ LL4148_LL34-2

2

2

BATT+

VS_N_001
1
1

EC_SMB_CK1 38,47

N1

1

1

+RTCBATT

MAXEL_ML1220T10

VS

PC500
@0.22U_0603_25V7K

PC501
0.1U_0603_25V7K @

2

2

1

PR302
@ 100K_0402_1%

2

2

PR24
PR25
560_0603_5%
560_0603_5%
2
1
2
1
+RTCBATT2
+RTCBATT1

1

+

PBJ1

2

-

2
PR303
22K_0402_1%

1
47,48,50 51_ON#

Must close PBJ1

@

VS_N_002

SP093MX0000
4

Change RTC For Cost Down

4

For KB9012 --> Remove all 51_ON# circuit
Compal Secret Data

Security Classification

Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
A

B

C

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE

Friday, August 24, 2012

Sheet
D

47

of

60

D

C

B

A

1

input
protection
for reverse PQ5
D
2
G

3

2N7002KW 1N SOT323-3
S

BQ24725_PROT
PR27

2

PQ6
MDS2659URH

2
3M_0402_5%

1
2

1

4
2

1

PC22
@820P_0402_25V7

2

1

PC21
0.1U_0402_25V6

PC20
2200P_0402_25V7K

2

1

PC19
@10U_0805_25V6K
1
2

2

PC18
1

@10U_0805_25V6K

3

PR37
1
2
0_0603_5%

1
2
10_1206_1%

5

1

PD5
RB751V-40_SOD323-2

PQ10
MDV1528URH 1N PDFN33-8

2

2

1

133K_0402_1%

3

+3VL

@

PC42
1

2

PU4

1

4

2

GREEN_PWR2
74LVC1G02_04_SOT353

0_0402_5%
2

GREEN_LATCH1

PR57 @
0_0402_5%

2
G

1
@ PR178
1

3

S

0_0402_5%

Compal Secret Data
Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
C

2

GREEN_LATCH#

GREEN_PWR5

1
1
D

2011/10/31

74LVC1G02_04_SOT353

2

1
2

@ PQ109
SSM3K7002FU_SC70-3

Issued Date

@

4

O
INA

PR58 @
100K_0402_5%

0_0402_5%

Security Classification

PU6 @

INB

2

@ PR56
1

41 GREEN_PWR

GREEN_LATCH#
4

5

O
INA

3

3

@

PU5 @

INB

GREEN_PWR#

+3VL
@
PR179
10K_0402_5%

@ PR180
1

2

P

1

4

GREEN_PWR1

G

5
OUT

3

IN2

P

IN1

G

2

2

0.1U_0402_10V7K

PC45
1

@

Please locate the RC
Near EC chip

1

GREEN_PWR4

GND

1

38,46

1

ADP_I

2

.1U_0402_16V7K

47K_0402_1%

EC_SMB_DA1 38,46

1

1

PR54 @
10K_0402_5%
2
1

GREEN_PWR3
PR55

2

EC_SMB_CK1 38,46

VCC

5

2

MC74VHC1G08DFT2G_SC70-5

0.1U_0402_10V6K

41 GREEN_PWR4

2
PC44

B

PC34
10U_0805_25V6K
1
2

2

1

VIN

PR53
100_0402_5%

2

A

PC36
1
2
2200P_0402_50V7K
PC37
0.01U_0402_50V7K

2

1

PC33
10U_0805_25V6K

@820P_0402_25V7
1
2

PC38
0.1U_0402_25V6
PC32
1
2

1

CSON1

2

CSOP1

2

2

1

3

+3VALW

PR47
PC41
0.01U_0402_25V7K

2

PC35
0.1U_0402_25V6

1

PR41
@4.7_1206_5%

REGN
ILIM

2

CSON1

BQ24725_BATDRV

PR40
0.02_1206_1%
4

PC40
@680P_0402_50V7K

2

2

SRN

11

1

BQ24725_SNUB

3
2
1

PR42
10_0603_1%
PR43
2
6.8_0603_1%
CSOP1

12

2

1
2

BQ24725_IOUT

BQ24725_ACDET

1

PC39
0.1U_0603_16V7K

1
SRP

PR51 @
309K_0402_1%

2

1

1
2

PC43
0.1U_0402_25V6

2

1

BQ24725_PRECHG
255K_0402_1%

PR50
154K_0402_1%

2

VIN 1

3
2
1

5
DL_CHG

13

BQ24725_ILIM

10K_0402_1%
PR48

2
CHG_OUT

14

10

SCL

SDA

9

1M_0402_1%
PR46
2

8

7

IOUT

ACDET

BATDRV

PR49
100K_0402_1%

14,20,38 ACIN

SRN

6

2

1

PR52
66.5K_0402_1%

For KB930 --> Keep PR44
For KB9012 (Red square) --> Remove PR44
Keep PR45

ACOK

PR45

1

SRP

ACDRV

5

1

4

15

BATT+

1

4.7UH_ETQP3W4R7WFN_5.5A_20%
BQ24725_LX

1

BQ24725_BST

BQ24725_REGN

BTST

HIDRV

GND

2

@10K_0402_1%
BQ24725_ACOK

+3VL

PL6

0_0402_5%

AON7406L 1N DFN

LODRV

CMSRC

4

PR44
BQ24725_ACDRV

4

2
DH_CHG1

PQ12

ACP

BQ24725_CMSRC

+3VALW

ILIM and external DPM
3.97A

2

1

ACN

3

1

PR38

1U_0603_25V6K

BQ24725ARGRR_VQFN20_3P5X3P5

Max.

1

DH_CHG
PC31

16

DH_CHG

18

17

BQ24725_LX

20

19

VCC

PAD

2

3

2

BQ24725_BST1

PU3

21
1

H-->L
L--> H

2
1

1

2

1U_0603_25V6K

Vin Dectector
Typ
17.23V
17.63V

PC29

1

PHASE

S

Min.

PR31
4.12K_0603_1%
BQ24725_BATDRV_1

BAS40CW_SOT323-3

BQ24725_VCC

PC30
2
1

BQ24725_ACP

PQ11
SSM3K7002FU_SC70-3 @

3

BQ24725_VCC2
PR36

PR34

1

D

2
G

BQ24725_ACN

GREEN_LATCH#

2

1

BQ24725_BATDRV

0.047U_0402_25V7K

PR35
4.12K_0603_1%

BQ24725_VCC_EN1
1

2

2

2

BQ24725_VCC_EN

4.12K_0603_1%
1
2

2

1

PC28
0.22U_0603_25V7K

PR39
1
2
0_0402_5%

2

22K_0402_1%

PC27

1

0.1U_0402_25V6

1

@ PR33
1

PD4

PC26
0.1U_0402_25V6

BQ24725_VCC2

1
2
3

BQ24725_VCC1

1

2

2

1

2

BQ24725_VCC1

PR32
100K_0402_1%

B+

VIN

PC25
0.1U_0603_25V7K

PQ9
TP0610K-T1-E3_SOT23-3

3

3

PC15
10U_0805_25V6K
1
2

10U_0805_25V6K

PC14
1
2

2

PC17
10U_0805_25V6K
1
2

2

1

PC16

1

8
7
6
5

1
2
3

4

1

1

2

PR30
@0_0402_5%

4

P1

PR28
0.02_2512_1%
4
10U_0805_25V6K
1
2

PQ8
MDS2659URH

PR29
@0_0402_5%

P3
PL5
1UH_VMPI0703AR-1R0M-Z01_11A_20%

2

1

2

PC24
2200P_0402_50V7K

VIN

1

8
7
6
5

P2

PC13
0.1U_0402_25V6

1M_0402_5%
PQ7
TPCA8057-H_PPAK56-8
1
2
3
5

2

1
1

PC23
0.01U_0402_50V7K

1

PR26

4

Compal Electronics, Inc.
Document Number

SCHEMATICS, MB A8581

Rev
B

4019IE
Friday, August 24, 2012
D

Sheet

48

of

60

E

D

C

B

A

1

2VREF_51125

2

PC46
1U_0603_16V6K

1

1

5

1

3
2
1

UG_5V_1

PQ16

2

4

SNUB_5V

46

VL

AON7702L_DFN8-5

1

2
1

1

2

2

2

PC59
1U_0603_10V6K

3 ENTRIP2

6 ENTRIP1

+

PC61
4.7U_0805_10V6K

PC62
0.1U_0603_25V7K

2VREF_51125
PJP2

2

1
D

5

2
G N_3_5V_001

1
PC57
220U_6.3V_M

2

1

RT8205LZQW(2)_WQFN24_4X4

1

PR70
@4.7_1206_5%

1

5

LG_5V

SPOK

2

+5VALWP

PC60
@680P_0402_50V7K

VREG5

2

1

4

2
FB1

ENTRIP1

REF

PC52
10U_0805_25V6K

ENTRIP1

13

PL9
4.7UH_ETQP3W4R7WFN_5.5A_20%
2
1

LX_5V

19

AON7406L_DFN8-5

PR72
95.3K_0402_1%

D

PQ17A
SSM6N7002FU_US6

UG_5V

20

LGATE1

51125_PWR

3

BST_5V

21

3
2
1

1
2
3

PC58
@680P_0402_50V7K
1 SNUB_3V
2

TONSEL

LGATE2

LG_3V
PR71
499K_0402_1%
2

51125_PWR

2

3

ENTRIP2

ENTRIP2

PHASE1

PC55
PR66
0.1U_0402_10V7K
2.2_0402_5%
2
1
2 PR68
1
2
1
BST1_5V
0_0402_5%

NC

1

UGATE1

PHASE2

4

23
22

BOOT1

UGATE2

17

PQ15

BOOT2

PQ14
MDV1528URH 1N PDFN33-8

24

VO1

18

12

B++

PR64
137K_0402_1%
2

PGOOD

VREG3

GND

11

LX_3V

4

10

1

VO2

VIN

UG_3V

9

16

1

0_0402_5%

8

2

+

PR65
2
1
2.2_0402_5%
BST_3V
2

EN

1
PC56
220U_6.3V_M

2

PR69
@4.7_1206_5%

+3VALWP

5

PL8
4.7UH_ETQP3W4R7WFN_5.5A_20%
2
1

PC54
0.1U_0402_10V7K
2 PR67
1
BST1_3V
1

15

UG_3V_1

1
2
3

7

2

P PAD

2

25

SKIPSEL

PC53
10U_0805_6.3V6M

1

4

PQ13
MDV1528URH 1N PDFN33-8

5

6

2

PU8

FB2

PR63
154K_0402_1%
1

5

1

2

PC49
4.7U_0805_25V6-K

+3VLP

14

2

PR62
20K_0402_1%
2

1

FB_5V

PC51
2200P_0402_50V7K
1
2

FB_3V

PC47
0.1U_0402_25V6
1
2

1

2

PR61
20K_0402_1%
2
1

B++

PL7
HCB2012KF-121T50_0805

PC48
2200P_0402_50V7K
1
2

B+

PR60
30.9K_0402_1%
2
1

PC50
0.1U_0402_25V6
1
2

PR59
13.7K_0402_1%
1

+5VALWP

PQ17B
SSM6N7002FU_US6

G

3

+5VALW

(6A,200mils ,Via NO.= 12)

+3VALW

(4A,120mils ,Via NO.= 8)

PAD-OPEN 4x4m

4

PJP3

1

S

S

1
PD8
GLZ27D_LL34-2

+3VLP

1SS355_SOD323-2

BATT+

PD9

2

1

PAD-OPEN 4x4m

51125_PWR1

PD6
1SS355_SOD323-2

1

2

1
+3VALWP

51125_PWR

+3VL

PJP4
1

2

PR77
100_0805_5%
2
1

PAD-OPEN 2x2m

+3VLP

1SS355_SOD323-2

+CHGRTC

PJP5

1

1

2
PC64
0.1U_0603_25V7K

PAD-OPEN 2x2m
2

1

1

2

1

PD7

2

2

PR319 @
100K_0402_1%

@

Vin
VL

51125_PWR2

2

PQ18
DRC5115E0L_SOD323-3

3

2
1
0_0402_5%
1

PR75
2
1
100K_0402_5%

PC63
4.7U_0603_10V6K

VS

@

2

46 MAINPOWN

PR181

1
2
PR320
42.2K_0402_1%

38,46 VCOUT0_PH

PR76
2
1
0_0402_5%
KB9012@

2

N_3_5V_002

38,39,41 EC_ON

PR73
0_0603_5%
2
1

B+

PR74
2.2K_0402_1%
2
1

4

4

For KB930 --> Keep PR319, Remove PR74
For KB9012 (Red square) --> Remove PR319
Keep PR74

Compal Secret Data

Security Classification

2011/10/31

Issued Date

2012/12/31

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
A

B

C

D

Rev
B

4019IE

Friday, August 24, 2012

Sheet
E

49

of

60

D

C

B

A

1

1

SNUB_1.8VSP

1

2

2

1
2

2

PR82
10K_0402_1%

2

SY8033BDBC_DFN10_3X3

2

1

PC69
@0.1U_0402_10V7K

2

PR81
@47K_0402_5%

1

1

1
PR80 0_0402_5%

PC70
680P_0402_50V7K

2 EN_1.8VSP

1

7

11

FB_1.8VSP

9,32,38,44,50,51,56 SUSP#

PC68
22U_0805_6.3VAM

1

PR79
20K_0402_1%

PC67
22U_0805_6.3VAM

2

+1.8VSP

PC66
68P_0402_50V8J
1
2

NC

6

1

3

2

LX

FB
EN

TP

5

PL11
0.47UH_PCMB042T-R47MN_6A_20%
2
1

LX_1.8VSP
1

PVIN

2

SVIN

2

8

LX

PR78
4.7_1206_5%

1

9
PC65
22U_0805_6.3VAM

PVIN

PG

10

VIN_1.8VSP

4

PU9

HCB1608KF-121T30_0603
2
1

NC

PL10
+5VALW

2

PJP7

2

1

(3A,120mils ,Via NO.= 6)

+1.8VS

+1.8VSP

PAD-OPEN 3x3m

VPRO@

2

VPRO@ PR86
10K_0402_1%

1

2

VPRO@ PC74
22U_0805_6.3VAM

1

2

1

3

VPRO@ PC73
22U_0805_6.3VAM

2

PR84
7.5K_0402_1%

VPRO@
PC72
68P_0402_50V
1
2

1
VPRO@

2

SY8033BDBC_DFN10_3X3

@

PR83 VPRO@
4.7_1206_5%

2

+1.05V_MP_FB

SNUB_+1.05V_MP

EN

6

 VFB=0.6V
Vo=VFB(1+PR401/PR402)=0.6*(1+7.5K/10K)=1.05V

+1.05V_MP

VPRO@
PC76
680P_0603_50V7K

3

1

PG

FB

11

1

2

PR87 @
300K_0402_5%

LX

1

100K_0402_1%

EN_+1.05V_MP

1

PR85 VPRO@
2

PC75
0.1U_0402_10V7K

1

2

45,46 PM_SLP_LAN#

VPRO@
PL13
0.47UH_PCMB042T-R47MN_6A_20%
2
1

+1.05V_MP_LX

SVIN

TP

5

PVIN

2

NC

8

PC71 VPRO@
22U_0805_6.3VAM

2

3

LX

NC

1

9

PVIN

7

10

+1.05V_MP_VIN

4

VPRO@ PU10

HCB1608KF_0603
2
1

1

PL12
+5VALW

PJP8
+1.05V_MP

2

1

+1.05V_M

(1.3A, 52mils, Via NO.= 3)

PAD-OPEN 3x3m

4

4

Compal Secret Data

Security Classification

Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
A

B

C

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
D

50

of

60

1

2

3

4

5

PL14
HCB1608KF-121T30_0603
2
1
+1.05VSP_B+

1

1

RF_+1.05VSP

V5IN

TST

DRVL

TP

1

SUSP#

VFB

3
2
1
PR91

2

2.2_0402_5%

+5VALW

6
LG_+1.05VSP

11

PQ20

3
2
1

AO4456_SO8

+

1

2

C

PR95
0_0402_5%
PC85
680P_0402_50V7K

2

2

2

PR93
4.7_1206_5%

4

2

PR96

1

+1.05VSP
1

PC82
1U_0603_10V6K

C

PC86
@1000P_0402_50V7K
2
1
+1.05VSP1

PC79
10U_0805_25V6K
1
2

PL15
0.47UH_PCMB063T-R47MS_18A_20%
2
1

SW_+1.05VSP

PR94
470K_0402_1%

2

MDV1525URH_PDFN33-8-5

UG_+1.05VSP1

7

TPS51212DSCR_SON10_3X3

PC84
@0.1U_0402_16V7K

1

UG_+1.05VSP

8

PC83

5

1

9,32,38,44,49,51,56

FB_+1.05VSP

SW

EN

9

220U_6.3VM_R15

PR92
0_0402_5%
2
1

DRVH

BST_+1.05VSP

1

4

TRIP

BST1_+1.05VSP

10

2

EN_+1.05VSP

VBST

1

3

PGOOD

4

1 SNUB_+1.05VSP 2

TRIP_+1.05VSP

4.7_0402_5%

PU11

PC81
0.22U_0402_10V6K
2
1

D

5
6
7
8

2

2
1
84.5K_0402_1%

2

1

1

PR89

2

44,52 +1.05VSP_PWRGOOD

PR90

PC80
4.7U_0805_25V6-K

PQ19

PR88
10K_0402_5%

PC78
2200P_0402_50V7K
1
2

2

5

+3VS

PC77
0.1U_0402_25V6
1
2

D

B+

+1.05VSP

@1.2K_0402_1%

PR98
100_0402_1%
2
1

4.99K_0402_1%
2
1

VCCIO_SENSE1

VCCIO_SENSE

8

2

PR97

1

PR99
10K_0402_1%

PJP9

2

1

+1.05VS_PCH

PAD-OPEN 4x4m
PJP10

1

+1.05VSP

B

2

+1.05VS_VCCP

(12A,480mils ,Via NO.= 24)

B

PAD-OPEN 4x4m

A

A

Compal Secret Data

Security Classification

Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.
SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Friday, August 24, 2012
Date:
5

4

3

2

Rev
B

4019IE
Sheet
1

51

of

60

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A

PR101 2
DH_1.5V

VDD

19

20
VTT

BOOT

2
2

3
4

VTTREF_1.5V

5

+1.5VP
1

C

6

10

PC97
0.033U_0402_16V7K

+5VALW
PC98

1.5V_B+

PR106
10K_0402_1%

2

PR107
887K_0402_1%
2
1

PC99
.1U_0402_16V7K

EN_1.5V

32,38,39,44 SYSON

1

Note: S3 - sleep ; S5 - power off
PR109

2

2
B

1

2

TON_1.5V

PR108
0_0402_5%
2
1

+1.5VP

1

VTTREF_1.5V
off
on
on

PR105
10.2K_0402_1%
2
1

FB_1.5V

PC100
@0.1U_0402_10V7K

1

44 0.75VR_EN

EN_0.75VSP

+0.75VSP
off
off
on

VDDQ

1

2

2

PC96
1U_0603_10V6K

2

Level
L
L
H

VLDOIN

VTTREF

VDDP

@680P_0402_50V7K

Mode
S5
S3
S0

GND

21

+0.75VSP

FB

1

1
2
3

2

+5VALW
AON7702L_DFN8-5

11

VDD_1.5V

S3

2

1

4

12

VTTSNS

RT8207MZQW_WQFN20_3X3

S5

1
PR103
@4.7_1206_5%

1 SNUB_+1.5VP

PC95

2

220U_6.3VM_R15

1
+

PR104
5.1_0603_5%

CS

PAD

VTTGND

PGND

7

PQ22

13

PC94
1U_0603_10V6K
2
1

5

+1.5VP

C

14
CS_1.5V

8

1

18

16

PR102
18.7K_0402_1%
2
1

1
2
3

2

PU12

LGATE

PGOOD

15

4

UGATE

DL_1.5V

MDV1528URH 1N PDFN33-8

PL17
1UH_VMPI0703AR-1R0M-Z01_11A_20%

17

1

SW_1.5V

1

0_0402_5%

2

DH_1.5V_1

+1.5VP

BOOT_1.5V

PHASE

0.22U_0402_10V6K

1

5

PC91

2

PC90
@4.7U_0805_25V6-K

1

2

PC89
10U_0805_25V6K
1
2

PC88
2200P_0402_50V7K
1
2

PC87
0.1U_0402_25V6
1
2

1

PQ21

D

PR100 2

2.2_0402_5%

PC93
10U_0805_6.3V6M

1

BST_1.5V

PC92
10U_0805_6.3V6M

1.5V_B+

TON

PL16
HCB1608KF-121T30_0603
2
1

B+

9

D

1

2

3

4

5

@0_0402_5%

B

PR110

2

9,32,38,44,49,50,56 SUSP#

1

1

0_0402_5%

PJP11

2
2

1

PAD-OPEN 4x4m

PC101
@0.1U_0402_10V7K

PJP12

2

1

+1.5V

+1.5VP

(13A,520mils ,Via NO.= 26)

PAD-OPEN 4x4m

PJP13

1

2
+0.75VS

+0.75VSP

(2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m

A

A

Compal Secret Data

Security Classification

Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.
SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Friday, August 24, 2012
Date:

Rev
B

4019IE

5

4

3

2

Sheet
1

52

of

60

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

9

PC104
@0.1U_0402_10V7K
1
2

+1.05VSP_PWRGOOD

C

PR116
PC105
2.2_0603_5%
0.22U_0603_10V7K
2
1
2
1
+VCCSA_BT_1

+VCCSA_BT

11
1

10

PR117
4.7_1206_5%

2

9

8

1 SNUB_VCCSA

SW

VIN

SW

7

VIN

TP

+VCCSAP

25

PC114
1000P_0402_25V8J

6

5

4

3

2

1

2

GND

HCB1608KF-121T30_0603

PL18
0.47UH_PCMB042T-R47MN_6A_20%
2
1

+VCCSA_PHASE

PC109
22U_0805_6.3V6M
1
2

SW

44,50

PC106
22U_0805_6.3V6M
1
2

14

13

TPS51461RGER_QFN24_4X4

VIN

D

PR115
0_0402_5%
2
1

EN

VID1

PGOOD

VID0

15

PC102
1
2

1U_0603_10V6K

17 +VCCSA_V5FILT

SW

VCCSA Vout
0.9V
0.8V
0.725V
0.675V

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

PGND

MODE

+VCCSA_PWR_SRC

SW

SLEW

PC113
1
2

10U_0805_10V6M

PC112
1
2

10U_0805_10V6M

0.1U_0402_25V6
PC111
2

1

2200P_0402_50V7K
PC110

24

BST

VOUT

1

22
23

PGND

COMP

+5VALW

21

2

H_VCCSA_VID0

12

PGND

VREF

19
20

V5DRV

PU13

18

C

2

9

+VCCSA_EN

16

PR114
10_0402_1%
2
1
PC103
2.2U_0603_10V7K
2
1

V5FILT

+5VALW

PL19

H_VCCSA_VID1

PR113
1K_0402_5%
2
1

38 SA_PGOOD

VID[1]
0
1
0
1

output voltage adjustable network

2

PR112
100K_0402_5%
1

PR111
1K_0402_5%
2
1

PC108
22U_0805_6.3V6M
1
2

+3VS

1

VID [0]
0
0
1
1

PC107
22U_0805_6.3V6M
1
2

D

1

2

3

4

5

PR118

+VCCSA_VREF

0.22U_0402_10V6K
B

1
2
+VCCSA_COMP1

2

1

@33K_0402_5%

PR119
100_0402_5%
2
1

+VCCSA_VOUT

B

PR120
0_0402_5%
2
1

1

PR121
10K_0402_5%

PC117
0.01U_0402_25V7K
1
2

2
PC116
3300P_0402_50V7K

+VCCSA_SLEW

+VCCSA_COMP

+VCCSA_MODE

PC115
2
1

+VCCSA_SENSE

9

PJP14

1

2
+VCCSA

+VCCSAP

(6A,240mils ,Via NO.= 12)

PAD-OPEN 4x4m

A

A

Compal Secret Data

Security Classification

Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
Document Number

SCHEMATICS, MB A8581
4019IE
Sheet

Friday, August 24, 2012
1

53

of

60

Rev
B

2
@0_0402_5%

1
PR122

+5VS

CSP1A

DIS only:
All AXG components are @.
Except
PR272 and PR273 are 0ohm.
PC223, PC226, PR202 are 0ohm.
PC220, PC215, PR206 are 0ohm.

1K_0402_1%

3300P_0402_25V7K
PR132 10P_0402_50V8J
2
COMPA1
5.11K_0402_1%

2P: 1.65K
1P: 1K

1

1

PC129
1000P_0402_50V7K

PR1332
SW1A
63.4K_0603_1%
PC128
1000P_0402_50V7K

1

+5VS

9 VSS_AXG_SENSE

2
1

1

+3VS
PR151
10K_0402_5%

DIFF_CPU

8

VCCSENSE

PC141
2
1

PR162

1

1

3P: 6.04K
2P: 4.32K

3P: 23.7K
2P: 24.9K
PR168

1

2
DROOP

CSCOMP

1K_0402_1%

PC152
2
1
CSREF
1000P_0402_50V7K

3P: 806
2P: 1K

A

2

1

43

43

SW1

43

TSENSE

B

+5VS
CSP2

3P: 21K
2P: 12.4K
CSREF

43

3P: 1500p
2P: 1200p
1

PC149
2
CSSUM
1200P_0402_50V7K

1

CSP1

TSENSE

1
PR159 2
PC147
SW1
6.98K_0402_1%
0.047U_0402_16V7K

1 PR167

2

PR1632
169K_0603_1%
SW1
PR1652
169K_0603_1%

1

PUT COLSE
TO VCORE
HOT SPOT

SW2

PH5

PUT COLSE
TO VCORE
Phase 1
Inductor

2

1
220K_0402_5%_ERTJ0EV224J
A

Issued Date

Compal Secret Data
2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

100K_0402_1%_TSM0B104F4251RZ

165K_0402_1%

Security Classification

5

PH4

CSREF

1

2 PC151
330P_0402_50V7K

1 PR166 2
75K_0402_1%NTC_PH201

1
PR1552
PC1426.98K_0402_1%
0.047U_0402_16V7K
SW2

CSREF

PC146
1000P_0402_50V7K

3P: 2200p
2P: 3300p
3P: 3.65K
2P: 9.53K

SW1A

SW2

PR1522
41.2K_0402_1%

2

2

3P: 348
2P: 1.21K

2

9.53K_0402_1%

PC144
1

2
0.22U_0402_10V6K

PC136
2
1
43
2.2U_0603_10V7K
PR148
2
1
PR1492
0_0402_5% PC138
+5VS
43 1
2.2_0603_5%
2
1
43
0.22U_0402_10V6K
BST1_1

PC140
2
1
.1U_0402_16V7K

CSP1
CSP2

3300P_0402_50V7K

PC150
1

1

4700P_0402_25V7K

1.21K_0402_1%

FB_CPU2
PC148

2

COMP_CPU1

LG2

LG1

HG1

2

680P_0402_50V7K

2

PR157
2
1
4.32K_0402_1%

2

FB_CPU3

PR161

1

TRBST#

10P_0402_50V8J

PR156
2
1
1000P_0402_50V7K
49.9_0402_1%FB_CPU1

PR164
1

PC145
2
1

24.9K_0402_1%

3P: 330p
2P: 1000p
PR158
2
1
10_0402_1%

CSCOMP

1 PR154 2
1K_0402_1%
PC143
2
1

1
PR153 12.4K_0402_1%

B

3P: 22p
2P: 10p

PC139
1000P_0402_50V7K

.1U_0402_16V7K

2

VSSSENSE

1

1

VGATE

HG2

PC131
2
0.22U_0402_10V6K
PC135

1

3P: 73.2K
2P: 41.2K

TRBST#
FB_CPU
COMP_CPU
IMON
ILIM_CPU
2
DROOP

VR_HOT#

LG1A

BST1

2

2

PR150
75_0402_1%

NCP6132AMNR2G_QFN60_7X7
ROSC

VRMP
VRHOT#
VRDY
VSN
VSP
DIFF

1

BSTA1_1
PR1432
43 1
2.2_0603_5%
43
BST2_1
43

1

CPU_B+

9
10
11
12
13
14
15

PR139
2
2.2_0603_5%

1

HG1A

PR160

2

45
44
43
42
BSTA1
41
40
39
38
BST2
37
36
35
34 6132P_VCCP
33
32
31

2

PR145
95.3K_0402_1%
1
2

1

PR146
VR_ON_CPU
2
1
VR_SVID_DAT1
10K_0402_1%
VR_SVID_ALRT#
VR_SVID_CLK
VBOOT
ROSC_CPU
VRMP
VR_HOT#
VGATE

PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1

1

0_0402_5%
2
VR_SVID_DAT1

VR_ON

VCC
VDDBP

VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT

PUT COLSE
TO V_GT
HOT SPOT

2

3
4
5
6
7
8

2

29

PC137
PR147 1K_0402_1%

+1.05VS_VCCP

1
2

6132_VCC

C

2P: 36K
1P: 26.1K

16
TRBST#
17
18 FB
19 COMP
20 IOUT
ILIM
21
22 DROOP
23 CSCOMP
24 CSSUM
25 CSREF
26 CSP3
CSP2
27
28 CSP1
29 TSNS
30 DRVEN
PWM

8 VR_SVID_DAT
8 VR_SVID_ALRT#
8 VR_SVID_CLK

2

1

1 PR144

PC134
2PR142

1

0.01U_0402_25V7K

1

2

PC133

.1U_0402_16V7K

PR141
1
2
54.9_0402_1%

2

130_0402_1%

PR140

1

2

1

.1U_0402_16V7K

1

2.2U_0603_10V7K
0_0402_5%

PH3
100K_0402_1%_TSM0B104F4251RZ

PR137
2
1
26.1K_0402_1%

1

+5VS

+1.05VS_VCCP

8

SW1A

PC130 CSREFA 43
2

61
60
59 DIFFA
58 TRBSTA#
57 FBA
56 COMPA
55IMONA
54 ILIMA
53DROOPA
52 CSCOMPA
51CSSUMA
50 CSREFA
49
CSP1A
48
TSENSEA
47
46

PU14

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA

1
PR1382
2_0603_5%

14,29

TSENSEA

2

1

CSP1A

.1U_0402_16V7K

C

29

PC127
0.047U_0402_16V7K
PR134 6.98K_0402_1%

PR136
2

2

9 VCC_AXG_SENSE

1

1PR135
2
15.8K_0402_1%

2

1

2P: 21.5K
1P: 15.8K

2

CSREFA

1

1K_0402_1%

PC132

DROOPA

2
PR1301
165K_0402_1% NTC_PH203

PC126
2

1000P_0402_50V7K
CSREFA

2

1

1

PR128

1
CSCOMPA

2

2

1

330P_0402_50V7K

FBA2

PR1312

1

PC123
2
1

PUT COLSE
TO GT

PH2

220K_0402_5%_ERTJ0EV224J
Inductor

1

2P: 24K
PC125
1P: 24.9K

PC124
2
1

8.25K_0402_1%

2

@4700P_0402_25V7K

1

2

24.9K_0402_1%

PR129
2
1
10_0402_1%

8.25K_0402_1%

FBA1

2

PC122

@1.21K_0402_1%

D

PR127
1
2
75K_0402_1%

TRBSTA#

2

@10.7K_0402_1%

1

PR1252

1

.1U_0402_16V7K
1 PR124 2

PR126

1

@10_0402_1% FBA3

PC120
1

@680P_0402_50V7K

PR1232

1

PC119
2

1

2 PC118

1

330P_0402_50V7K

LGA, SWA, HGA, BSTA, DIFFA, TRBSTA#, ILIMA, PWMA are float.
VSPA, VSNA to GND (HW side). FBA and COMPA are short.
CSREFA, TSNSA, IOUTA to GND. CSCOMPA, CSSUMA, DROOPA are short.

1200P_0402_50V7K
PC121
1
2

CSP1A, CSP2A to +5VS.

D

1

2

3

4

5

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581

Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet

54

1

of

60

1

2

3

4

5

D

D

PL20
HCB2012KF-121T50_0805
2
1

HG2

HG2_1

+VCC_CORE
PL23
0.36UH 20% FDUM0640J-H-R36M

2

SW2

5

1

42

2

PQ26

PR172
@4.7_1206_5%

1

PR174
2
1
10_0402_1% CSREF

4
42

CSREF 42

LG2

S TR MDU1512RH 1N POWERDFN56-8

3
2
1

10_0402_1%

SW1

PC165



2

PR173

SNUB_CPU1
1

3
2
1

S TR MDU1516URH 1N POWERDFN56-8

1

2

S TR MDU1512RH 1N POWERDFN56-8

PC158
10U_0805_25V6K
1
2

4

PC161
10U_0805_25V6K
1
2

2

PC164
2200P_0402_25V7K
1
2

42

PR170
1
0_0603_5%

2

4
LG1

PC157
@820P_0402_25V7
1
2

PQ24
CPU_B+

PC163
@100U_25V_M
2


PR171
@4.7_1206_5%

PQ25

42

2

PL21
HCB2012KF-121T50_0805
2
1

1

5

SW1

+

PC159
0.1U_0402_25V6
1
2

+VCC_CORE

1

+

PL22
0.36UH 20% FDUM0640J-H-R36M

S TR MDU1516URH 1N POWERDFN56-8

1
42

5
PC162
100U_25V_M

1

SNUB_CPU2

3
2
1

HG1_1

CPU_B+

3
2
1

4

B+

PC160
2200P_0402_25V7K
1
2

HG1

42

2

PC156
0.1U_0402_25V6
1
2

1
0_0603_5%

PC154
10U_0805_25V6K
1
2

PC153
@820P_0402_25V7
1
2

5

PQ23

PR169

PC155
10U_0805_25V6K
1
2

CPU_B+

SW2

2

1

@680P_0402_50V7K
PC166
@680P_0402_50V7K

C

HG1A

42

SW1A

PR175
1
0_0603_5%

2
HG1A_1

4

PC171
@820P_0402_25V7
1
2

PC169
0.1U_0402_25V6
1
2

B+

S TR MDU1516URH 1N POWERDFN56-8

+GFX_CORE

PL24
0.36UH 20% FDUM0640J-H-R36M

2

5

1

1

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A

PQ27

3
2
1

42

PL30
HCB2012KF-121T50_0805
2
1

PC170
2200P_0402_25V7K
1
2

5

GFX_B+

PC168
10U_0805_25V6K
1
2

PC167
10U_0805_25V6K
1
2

2

C



2

PR176
@4.7_1206_5%
PQ28

B

B

4

1 SNUB_GFX1

S TR MDU1512RH 1N POWERDFN56-8

LG1A

3
2
1

42

2

PR1771
10_0402_1%

CSREFA 42

PC172
@680P_0402_50V7K

2

SW1A

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A

Compal Secret Data

Security Classification
Issued Date
A

2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATICS, MB A8581

Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet

55

1

Compal Electronics, Inc.
PBL22 LA-7391P M/B

of

60

A

+VCC_CORE

+VCC_CORE

1

2

3

4

5

Below is 458544_CRV_PDDG_0.5 Table 5-8.

1

PC176
10U_0805_6.3V6M

PC175
10U_0805_6.3V6M

PC177
10U_0805_6.3V6M

2

2

2

PC174
10U_0805_6.3V6M

2

2

1

PC173
10U_0805_6.3V6M

Socket Bottom

5 x 22 µF (0805)
5 x (0805) no-stuff
sites

Socket Top

7 x 22 µF (0805)
2 x (0805) no-stuff
sites

1

1

1

+GFX_CORE
+GFX_CORE

1

2

1
+

PC218

+

2

2

PC206
22U_0805_6.3V6M

1

1

PC205
22U_0805_6.3V6M

1

1

1

1

2

2

PC226
22U_0805_6.3V6M

+

2

PC216

2

2

2

2

2

1
PC225
22U_0805_6.3V6M

1

1

330U_D2_2V_Y

2

+

330U_D2_2V_Y

1
PC224
22U_0805_6.3V6M

1

2

PC217
22U_0805_6.3V6M

1

2

PC204
22U_0805_6.3V6M

2

1

PC203
22U_0805_6.3V6M

2

PC202
22U_0805_6.3V6M

2

PC201
22U_0805_6.3V6M

2

2

2

2

1

2

C

PC220

2

PC223
22U_0805_6.3V6M

2

PC219

2

1
PC222
22U_0805_6.3V6M

2

1

1
1
+1.05VS_VCCP

PC215
22U_0805_6.3V6M

330U_D2_2V_Y

2

1

1
PC221
22U_0805_6.3V6M

2

1

1

PC200
22U_0805_6.3V6M

2

PC214
22U_0805_6.3V6M

330U_D2_2V_Y

1

1

1

2

1

PC199
22U_0805_6.3V6M

1

2

1

PC198
22U_0805_6.3V6M

2

C

+1.05VS_VCCP
1

PC197
22U_0805_6.3V6M

2

1
PC213
22U_0805_6.3V6M

2

PC196
22U_0805_6.3V6M

2

PC212
22U_0805_6.3V6M

2

1

PC190
22U_0805_6.3V6M

2

PC211
22U_0805_6.3V6M

1

2

1

PC189
22U_0805_6.3V6M

PC195
22U_0805_6.3V6M

2
1

1

2

1

PC210
22U_0805_6.3V6M

2

2

1

1
PC194
22U_0805_6.3V6M

PC209
22U_0805_6.3V6M

2

PC193
22U_0805_6.3V6M

PC208
22U_0805_6.3V6M

2

PC192
22U_0805_6.3V6M

PC207
22U_0805_6.3V6M

2

1

1

1

PC191
22U_0805_6.3V6M

2

1

PC188
22U_0805_6.3V6M

1

2

1

PC187
22U_0805_6.3V6M

2

+VCC_CORE

1

PC186
22U_0805_6.3V6M

1
PC182
10U_0805_6.3V6M

PC181
10U_0805_6.3V6M

PC185
22U_0805_6.3V6M

PC180
10U_0805_6.3V6M

PC179
10U_0805_6.3V6M

PC183
22U_0805_6.3V6M

PC178
10U_0805_6.3V6M

D

PC184
22U_0805_6.3V6M

1

D

2

+VCC_CORE
1
+

2

1
PC227

+

470U_D2_2VM_R4.5M

2

1
PC228
330U_D2_2V_Y

+

2

1
PC229
330U_D2_2V_Y

+

PC230
330U_D2_2V_Y

2

B

B

A

A

Compal Secret Data

Security Classification

2011/10/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

56

of

60

2

5

5

4

CPU_BOOST-1

1

2

OPT@ PC238
0.1U_0402_25V6

1

1

OPT@ PC237
2200P_0402_50V7K

2

2

OPT@ PL32
0.22UH_PCMB104T-R22MS_35A_20%
2

3
2
1

22
3211_DRVH

+5VS

4
17

33

4

1

+VGA_CORE
1
PR195
4.7_1206_5%

+

2

PC247
680P_0603_50V7K

OPT@ PC245
470U_D2_2VM_R4.5M

1

OPT@ PC243
2.2U_0603_10V6K

2
1

3211_DRVL

18

2

2

19

5

5

3211_SW

20

3
2
1

21

1

3
2
1

CPU_BOOST

OPT@ PC236
4.7U_0805_25V6M

1
2

OPT@ PC235
4.7U_0805_25V6M

4

23

3
2
1

AGND

MDU1516URH 1N POWERDFN56-8

OPT@ PQ35
MDU1511RH 1N POWERDFN56-8

AGND

OPT@ PQ32

D

B+

OPT@ PQ33

OPT@ PC240
0.22U_0603_25V7K
2
1

OPT@ PR194
0_0603_5%
2
1

OPT@ PQ34
MDU1511RH 1N POWERDFN56-8

CSCOMP

IREF
9

1

2
1

VID6

3211_VCC

2

VID6

25

VID5

27
VID4

28
VID3

29

PGND

GPU

ILIM

OPT@ PC234
4700P_0402_25V7K

1

<21>

<21>
VID5

26

<21>

<21>

<21>

<21>

1
2
0_0402_5%
1 OPT@ PR188
2
OPT@ PR189
0_0402_5%

GPU_VID5

GPU_VID4

0_0402_5%
OPT@ PR187

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

2
0_0402_5%
2
VID1

30

VID2

VID0

31

COMP

2
C

DRVL

CSFB

8

PVCC

OPT@ PU15

24

MDU1516URH 1N POWERDFN56-8

PC239 OPT@
1U_0805_25V6K

2

1

16

3211_VCC

3211_ILIM

SW
ADP3211AMNR2G_QFN32_5X5

FB

15

7

OPT@ PR197
2 OPT@ PC246
20K_0402_1%
470P_0402_50V8J
3211_COMP-1

1

OPT@ PR196
1K_0402_1%

FBRTN

CSREF

1

6
3211_COMP

CLKEN#

14

2

5
3211_FB

2

1

OPT@ PC244
47P_0402_50V8J
2
1

LLINE

4

2

1

OPT@ PC242
220P_0402_50V7K

DRVH

13

1000P_0402_50V7K

PR190 OPT@
10_0603_1%

BST

IMON

RT

3

OPT@ PL31
HCB2012KF-121T50_0805
+VGA_B+

+5VS

VCC
PWRGD

RPM

2

10

2

1

1

PR193 @
68K_0402_1%

11

PC241

0_0402_5%
1 OPT@ PR184
2
OPT@ PR185
0_0402_5%
VID3
1
2
OPT@ PR186
0_0402_5%
VID4
1
2

1
OPT@ PR183
1
EN

2

1
OPT@

VID1

3211_PWRGD

VID0

32 3211_EN

OPT@ PR192
0_0402_5%
2
1
VGA_PWROK

<14,17,45>

2

OPT@

PR191

+3VS

RAMP

10K_0402_1%

1

D

12

0_0402_5%

OPT@ 0_0402_5%

VID2

100P_0402_50V8J

1
1

OPT@ PC233
2

<14,16,38>

DGPU_PWR_EN

@ PR808
2

PR809
SUSP#
45,53
2
1

1

2

3

4

5

C

2

2

2

PR205 OPT@
124K_0402_1%

OPT@ PC249
OPT@
820P_0402_50V7K
PC248
1200P_0402_50V7K

1

PR206
150K_0603_1%
3211_RAMP-1

OPT@

PC251 OPT@
1000P_0402_50V7K

+VGA_CORE

OPT@ PC289
470U_D2_2VM_R4.5M

B

PR741 OPT@
14.7K_0402_1%
2
1

OT1 TMSNS2

OT2 RHYST2

2
1

2
1
@ PR743
10.5K_0402_1%

Protection at 105 degree C

1

Recoveyr at 85 degree C

Requlator temperature protection:

Protection at 105 degree C
Recoveyr at 85 degree C

Compal Secret Data

Security Classification
Issued Date

2011/10/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

1

6
5

G718TM1U_SOT23-8

GPU Skin temperature protection:

PR744
+3VL OPT@
14.7K_0402_1%

OPT@

2

4

8
7

PH703

3

<41> PWR_GPS_DOWN#

VCC TMSNS1
GND RHYST1

PR742
10.5K_0402_1%

2

1

PU701 OPT@

1
2

4

3

2

@

100K_0402_1%_NCP15WF104F03RC

2

1

OPT@
PC716
0.1U_0603_25V7K

2

1

PH702 OPT@
100K_0402_1%_NCP15WF104F03RC

+3VL

2

2

+

2

OPT@ PC264
22U_0805_6.3V6M

2

@ PC288
470U_D2_2VM_R4.5M

OPT@ PC254
470U_D2_2VM_R4.5M

1
1

OPT@ PC263
22U_0805_6.3V6M

2

1

OPT@ PC272
4.7U_0603_6.3V6M

1

2

OPT@ PC261
22U_0805_6.3V6M

1
1

+

2

OPT@ PC271
4.7U_0603_6.3V6M

2

+

2

OPT@ PC287
0.1U_0402_10V7K

1

OPT@ PC279
4.7U_0603_6.3V6M

OPT@ PC278
4.7U_0603_6.3V6M

2
1

2

OPT@ PC286
0.1U_0402_10V7K
1
2

OPT@ PC285
0.1U_0402_10V7K

OPT@ PC277
4.7U_0603_6.3V6M
1
2
OPT@ PC284
0.1U_0402_10V7K
1
2

OPT@ PC276
4.7U_0603_6.3V6M
1
2
OPT@ PC283
0.1U_0402_10V7K
1
2

2

1

OPT@ PC275
4.7U_0603_6.3V6M
1
2
OPT@ PC282
0.1U_0402_10V7K
1
2

OPT@ PC274
4.7U_0603_6.3V6M

OPT@ PC281
0.1U_0402_10V7K
1
2

1

1
2

2

1
2

OPT@ PC280
0.1U_0402_10V7K
1
2

A

OPT@ PC273
4.7U_0603_6.3V6M

1

OPT@ PC502
47U_0805_6.3V6M

3211_CSCOMP

OPT@ PC267
4.7U_0603_6.3V6M

1
2

OPT@ PC266
4.7U_0603_6.3V6M
1
2

OPT@ PC265
4.7U_0603_6.3V6M

1
2

OPT@ PC259
4.7U_0603_6.3V6M
1
2

OPT@ PC258
4.7U_0603_6.3V6M

OPT@ PC257
4.7U_0603_6.3V6M
1
2

1

OPT@ PC256
4.7U_0603_6.3V6M
1
2

2

1
2

OPT@ PC255
4.7U_0603_6.3V6M

2

2

1

OPT@ PC260
22U_0805_6.3V6M

OPT@
PR209
0_0402_5%

1

1

OPT@ PC268
4.7U_0603_6.3V6M
1
2

1

Under VGA Chip
2

+VGA_CORE

2

OPT@ PC270
4.7U_0603_6.3V6M
1
2

+

@ PR208
0_0402_5%
2
1

OPT@ PC262
22U_0805_6.3V6M

1

Shortest the
net trace

B

OPT@ PC252
470U_D2_2VM_R4.5M

Near VGA Core

OPT@ PC269
1
2
4.7U_0603_6.3V6M

OPT@ PC250
1000P_0402_50V7K

2

1

Connect to input caps

2

<23>

<23>

VCCSENSE_VGA

VSSSENSE_VGA

1

+VGA_B+

1

1

1

OPT@ PR204
499K_0402_1%

OPT@ PR207
1K_0402_1%
2
1

OPT@
OPT@

2

OPT@ PR201
274K_0402_1%
3211_RT
1
2
3211_RAMP
1

2

OPT@ PR200
200K_0402_1%
1
23211_RPM

OPT@ PR199
80.6K_0402_1%
1
2 3211_IREF

3211_CSCOMP

2
2

1
1

3211_CSCOMP

Avoid high dV/dt
PR203
0_0402_5%

PR202
0_0402_5%

3211_CSFB

1

OPT@ PR198
4.53K_0402_1%

A

Compal Electronics, Inc.
Document Number

SCHEMATICS, MB A8581
4019IE
Sheet

Friday, August 24, 2012
1

57

of

60

Rev
B

Version Change List ( P. I. R. List )
Item Page#
1

Title

Page 47

Date

Request
Owner

2012/02/24

1

2

3

4

5

Page 1

Issue Description

Solution Description

Rev.

For DVT can't power on and need to disable EC VCIN0_PH
VCIN1_PH pin detect

Reserve

3D mark06&3D mark Vantage score don't meet SPEC need to
support GPS function

Add PC288 PC289 470U_D2_2VM_R4.5M
PC248 1200P_0402_50V7K
PR209 0_0402_5%
Change PC242 to 220P_0402_50V7K
PC246 to 470P_0402_50V8J
PC244 to 47P_0402_50V8J
PR197 to 20K_0402_1%
PR198 to 4.53K_0402_1%
PC249 to 820P_0402_50V7K
PR205 to 124K_0402_1%
PR206 to 150K_0603_1%
Delete PR208 0_0402_5%

PVT

Change PC56,PC57 footprint from D2 to C_6SVPE220MX

PVT

PR20 PR21 for DVT can't power on issue

PVT

D

2

3

Page 57

2012/02/24

2012/02/24

Page 49

For DVT SMT PC56, PC57 footprint did not match issue

D

C

C

4

Page 57

2012/02/24

5

Page 47

2012/02/24

6

Page 48

2012/02/27

Page 48

7

3D mark06&3D mark Vantage score don't meet SPEC need to
support GPS function

Change PH1 protect action to EC

PVT

Update Green power Circuit

Delete PU7 74LVC1G17GW TSSOP and change to PQ109 SSM3K7002FU_SC70-3
Add PR10 0_0402_5% to connect GREEN_LATCH#
Reserve PR178 0_0402_5%

PVT

2012/03/02

Update Green power Circuit

Connect the Green_PWR4 net to EC GPIO for AC decete for Green power
circuit ACOK will drop once time issue

PVT

Add one control signal in order to disable B+ to VSB
circuit in AC S5 for LOT6 system little than 0.5W issue

Reserve PR22 to add VSB_EN

8

Page 47

2012/03/06

9

Page 47
49

2012/03/06

10

Page 47

2012/04/23

Page 47
48,50,51
52,53,54
57

PVT

Change PH1 pull high vcc from +3VL to +EC_VACC
Change PH1 GND from normal GND to EC_AGND

B

11

Reserve GPU Skin and Requlator temperature protection circuit
for if temperature over spec issue
Add PC716 SE042104K80 0.1U_0603_25V7K
PR741,PR744 SD034147280 14.7K_0402_1%
PR742 SD034105280 10.5K_0402_1%
PH702 SL200000U00 100K_0402_1%_NCP15WF104F03RC

For System can power on immediately after HW shutdown

For EU Erp lot6 fail, need to cut off +VSB when system
at S5

2012/04/23

Change PU1.3 output name from EN0 to MAINPOWN
Dis-connect EN0 to PU8.13
Connect MAINPOWN to PQ18.2

Pre_MP

Add PR22, delete PR14,PR15

Pre_MP

ChangePR56,PR80,PR92,PR95,PR108,PR110,PR115,PR120,PR142,PR144,PR183,
PR184,PR185,PR186,PR187,PR188,PR189,PR192,PR809 footprint
from R_0402 to R0402_0ohm

Change to new footprint

B

PVT

A

A

Compal Secret Data

Security Classification

2011/10/31

Issued Date

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
5

4

3

2

Compal Electronics, Inc.
SCHEMATICS, MB A8581
Document Number

Rev
B

4019IE
Friday, August 24, 2012

Sheet
1

58

of

60

Rev.Item Date
0.2

D

C

1

Modify Description

37

Sourcer require to change crystal to small size.
EVT can't power on issue.

Change X1 from "SJ100009A00" to "SJ10000EV00"

2

12/21 Circuit, Layout

41

3

12/21 Circuit, Layout

26,35,42,36

4

12/21

Circuit, BOM

43

SW7, SW8 part number error.

change SW7,SW8 part number to "SN100005G00"

5

12/21

BOM

27

just reserve pull up resistor for SLP_LAN#.

Add @ to R282.

6

12/26

BOM

34

TPM IC FW update from FW3.16 to FW3.19.

Change U37 from "SA00000GG40" to "SA00000GG70".

7

12/26

Circuit, BOM

33

Add Vpro & non-Vpro WIN8 BIOS ROM power source selection.

Add R421, R422.

8

01/05

BOM

40, 43

issue: redetect USB HDD when resume from S3.

Add @ to RU27, delete @ to R90; add @ to R9, delete @ to R10.

9

01/05

BOM

41

Board ID issue

Add "Rev02@", "Rev03@","Rev04@","Rev10@" serial Rb to distinguish the boards.

10

01/09

Circuit, layout

40

LID_SW# will cause system can't power on at DC mode if use +3VALW, not +3VL.

Change U34 Pin2 VDD from +3VALW to +3VL if EC use +3VL.

11

01/09

Circuit, layout,BOM

43

PWR ON LED will flash when doing Crisis.

Add a pull down resistor R169 100K to PWR_ON_LED; Reserve a 0ohm resistor R93.

Change R739 pull up power source from "+3VALW" to "+3VALW_EC".

Vpro require PCIE port1 can't connect to LAN.

Swap PCH PCIE port1 and port5.
D

12

01/09

Circuit, layout,BOM

36

DVT will build Vpro SKU, delete EC port80 debug signals to WLAN connector.

Delete R684, R1336 and the EC port80 debug signals to WLAN connector.

13

01/09

Circuit, layout,BOM

13,15
24

No need reserve VGA HDMI connection.

Change PCH net "DGPU_HPD_INT#" to PCH_GPIO6;

14

01/10

Circuit, layout

15

01/10

BOM

16

01/11

17

01/11

37,35,26,42

Delete U13,CV197,RV140,RV149,C430,C378,C455,C377,C376,C434,C456,C432,R432,R435,R443,Q65,R439,R437RV132,L88.
C

BIOS prefer LAN connect to PCIE port6 for Vpro.

Swap PCIE port5 and port6 connection.

33,

Distinguish with Vpro SKU.

Change UPCH1 and U59 BOM Structure to "8111E@" for non-Vpro SKUs.

Circuit, layout

43

+USB_VCCE no bulk capacitor.

Change C2,C7,C8 power source from +USB_VCCB to +USB_VCCE.

Circuit, layout

41

power CPU OTP issue, and power modified schematic.

Delete net EC pin27 "PWR_GPS_DOWN#" and EC pin 76 "PWRMOS_TEMP", delete R732.

QAQ1x HW PIR from DVT to PVT LA-8581P REV:0.2 -> 0.3
Rev.Item Date
0.3

<2011.12.05~2012.01.02. >

Page Change Cause

Impact

12/05 Circuit, Layout, BOM

1

2

3

4

5

QAQ1x HW PIR from EVT to DVT LA-8581P REV:0.1 -> 0.2

Impact

<2012.02.24~2012.03.07. >

Page Change Cause

Modify Description

1

02/24 Circuit, BOM

35

LL1 and CL13 change after EVT, DVT schematic missed and used MEMO for change.

Change LL1 from 4.7uH "SHI00004T00" to 2.2uH "SHI0000AA00". CL13 from 22uF "SE000000I10" to 4.7uF "SE107475K80".

2

02/24

BOM

37

DVT board card reader JMB389 can't detect 4IN1 card.

Delete R39 BOM structure "388@".

3

02/24

BOM

27

HDMI HPD signal level is too low for HDMI detection.

Add "@" to RH142.

4

02/24

Circuit, layout,BOM

41,13

PVT add GPU GPS feature.

Add R266 "@", R267 "@", R268 at Page13, add "@" to DV6.

6

02/24

Circuit, layout,BOM

28

requirement from Sourcer and buyer.

Change RP1, RP3 from row resistor "SD309820180" to single ones "SD028820180"-R320,R321,R322,R323,R324,R327,R329,R330.

7

02/24

BOM

35

UL5 BOM structure error with vPro SKU.

Delete UL5 BOM structure "8111E@".

8

03/01

Circuit, layout,BOM

35

LAN vendor Realtek suggest:Reserve CLKREQ_LAN# pull up 10Kohm to +3V_LAN.

Reserve CLKREQ_LAN# pull up 10Kohm to +3V_LAN: add RL25 and unmount it.

9

03/01

BOM

35

LAN vendor Realtek suggest:Reserve UL1 pin28 "EC_SWI#"pull up 10Kohm to +3V_LAN.

Modify reserved resistor RL3 from 100Kohm to 10Kohm.

10

03/01

Circuit, layout,BOM

35

LAN vendor Realtek suggest: 6pcs decoupling capacitor for UL1 Pin 12, 27, 39, 42, 47, 48.

Add one more piece capacitor CL12 close to UL1.

11

03/01

Circuit, layout,BOM

41

Reserve and add pull up for added net of EC pin27,68.

12

03/01

Circuit, layout,BOM

13

Reserve a 0ohm resistor for "GPS_DOWN#" to "PWR_GPS_DOWN#".

Reserve a 0ohm resistor R270 for "GPS_DOWN#" to "PWR_GPS_DOWN#".

13

03/02

Circuit, layout

41

power circuit removed net "PWR_MOS_TEMP", added net "GREEN_PWR4".

Remove net "PWR_MOS_TEMP", add net "GREEN_PWR4" to EC pin 76.

14

03/05

BOM

26

Adjust crystal loading capacitors' value according to matching test result.

B

A

Reserve R732 10Kohm and add R733 100Kohm pull up to +3VS for EC pin27,68, add R734 0ohm for PWR_GPS_DOWN# connect to EC.

Change Y3 from SJ10000DJ00 to SJ10000E800, C869 from SE071150J80 to SE071100J80, C225 from SE071120J80 to SE071100J80.

35

Change YL1 from SJ10000DJ00 to SJ10000E800, CL26 and CL27 from SE071270J80 to SE071120J80.

37,34

Change C54 and C82 from SE071120J80 to SE071150J80; C766,C767 from SE071150J80 to SE071180J80.

13
15

B

Change net ACIN_BUF to GPS_DOWN#, add net PWR_GPS_DOWN#, EC_GPS_DOWN#, PWRMOS_TEMP.

5

03/05

Circuit, layout,BOM

39

A

Change YV1 from SJ10000DK00 to SJ100009700, CV46 and CV47 from SE071180J80 to SE071100J80.
Refer to QAL50/51 design for smart card to add pull high to US4 pin26.

Add RS22 10Kohm pull up to +3V_SC for US4 Pin26. and change reserved pull down resistor RS21 from 0ohm to 10Kohm.

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/12/31

Deciphered Date

Title

SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019IE

Date:
5

4

3

2

Friday, August 24, 2012

Sheet
1

59

of

60

Rev.Item Date
0.3

16

Impact

03/05 Circuit, BOM

<2012.02.24~2012.03.07. >

Page Change Cause
28,39

Modify Description

smart card device lost at USB 3.0 port.

Change smart card reader from USB port 2 to port 5.

17

03/06 BOM

31

PCH VCCDSW3_3 change power connection from +3VALW_PCH to +3VALW.

Add "@" to R415, delete "@" to R382.

18

03/06 Circuit, layout, BOM

35,36,
39,29
41,45

ErP lot 6 fail, reserve a EC pin VSB_EN to control VSB;
reserve LAN WAKE to EC and PCH GPIO27.

Delete reserved net AOAC_ON (EC pin 38) and DRAMRST_GATE (EC pin 98) and their test point T23,T24.
Use these two pins for new added net VSB_EN_R and EC_PME#
Reserve net GPIO27_WAKE#, EC_PME# for LAN WAKE, reserve net EC_PME# to WLAN, WWAN and PCIE Express card wake.
thus, add R702@, RH122@, RH171, R331@, RL8(8111E@),RL9@, RL10@, R100@, R102, R761@, R767@,R768@.
Reserve net VSB_EN, thus add R765@, R766, R817, R818@, R819@; delete R816@, add @ to R754.

D

19

03/06 Circuit, layout, BOM

25

Reserve big size crystal Y6 for 32.768KHz.

20

03/08 BOM

40,43

UU1 SA000047500 was forbidden, change material requirement from buyer.

Change UU1 from SA000047500 to SA000033H00; Correct U6 description and value.

21

03/08 BOM

43,44

Change C4,C6 from SE053475Z05 to normal part SE053475Z80.

Change C4,C6 from SE053475Z05 to normal part SE053475Z80.

C

Impact

D

Reserve big size crystal Y6 for 32.768KHz.

QAQ1x HW PIR from PVT to Pre-MP LA-8581P REV:0.3 -> 1.0
Rev.Item Date
1.0

1

2

3

4

5

QAQ1x HW PIR from DVT to PVT LA-8581P REV:0.2 -> 0.3

<2012.04.18~2012.04.25. >

Page Change Cause

Modify Description

1

04/19 Circuit, BOM,layout

25

Reserve +5VS for MOS Q10 gate of audio sync signal to PCH HDA sync signal.

2

04/19 BOM

25,34

Change 32.768KHz crystal P/N, and RTC capacitor C204 from 15pF to 18pF.

Change Y2, X3 from SJ10000BM00 to SJ100001K00. change C204 from SE071150J80 to SE071180J80.

3

04/19 BOM

39

to solve issue of "Smart Card also show in Device Manager after plug out it".

Change US4 from SA000042I00 to SA000042I10.

4

04/19 Circuit,layout

45

Reserve 820Kohm resistor to GND for +3VALW_PCH and +1.05VS_DGPU DC/DC MOS GATE.

5

04/19 BOM

45,41

For ErP lot6, add +3VALW to +3VALW_PCH DC/DC circuit.

Delete @ for U25, Q46, Q49, R813, C837, C839, C838, R804, C836, R807, R754.

cost down: change some 0ohm resistors to short pad.

cost down: change some 0ohm resistors to short pad.

Add 0ohm 0402 resistor R189@ and R190.

C

Add 820Kohm R432@ and R435@.

6

04/20 BOM,layout

7

04/23 BOM

42

vPro: Intel suggest to change R1232 from 2.2K to 10K.

vPro: change R1232@ from 2.2K to 10K.

8

04/23 BOM

42

vPro: Intel suggest to change C470 from 10uF to 22uF.

vPro: change C470 from 10uF to 22uF.

9

04/23 BOM

35

vPro: Intel suggest to change CL34 from 0.1uF to 1uF.

vPro: change CL34 from 0.1uF to 1uF. keep CL34 0.1uF for 8111E LAN.

04/23 Circuit, BOM,layout

42

vPro: Reserve LAN WAKE to EC.

vPro reserve R559@ 0ohm for LAN WAKE connect to EC.

04/25 Circuit,layout

35

There is not enough space for LAN GND ESD diodes.
EMI test OK without the two ESD diodes.

Remove DL3@, DL4@.

B

B

A

A

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/12/31

Deciphered Date

Title

SCHEMATICS, MB A8581

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019IE

Date:
5

4

3

2

Friday, August 24, 2012

Sheet
1

60

of

60

www.s-manuals.com



---

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