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A

B

C

D

E

Compal Confidential
Model Name : VITU5
File Name : LA-8971P
1

1

Compal Confidential
2

2

VITU5 M/B Schematics Document
Intel Ivy Bridge ULV Processor + Panther Point PCH(HM77)
Nvidia chip:N13M-GS(23x23)

2012-02-16

3

3

REV:0.1

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

2012/07/12

Deciphered Date

Title

Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Thursday, February 16, 2012

Sheet
E

1

of

58

A

B

C

Compal confidential

E

Chief River

File Name :LA-8971P

NV N13M-GS
23mm *23mm

1

D

Intel
IVY Bridge ULV
(Sandy Bridge)
Processor

PCI-E X16
Gen 2

VRAM 128*16
DDR3*4

DDR3-1333/1600

DDR3-SO-DIMM X2

Dual Channel

SATA3.0 HDD CONN

BGA1023

FDI *8
100MHz
2.7GT/s

Std HDMI
Connector

1

PCI Express (Full)
Mini card Slot 2

DMI2 *4
100MHz
5GT/s

SSD(SATA3.0)

6*SATA

ODD (SATA2.0)

(port0,1 Support SATA3)
2

2

Intel
Panther Point

LVDS
Connector
6*PCI-E x1
Mini VGA
Connector

4*USB3.0
14*USB2.0

USB PORT 3.0 x1 (Left)

HM77

USB PORT 2.0 x2 (Right)

FCBGA 989 Balls
25mm*25mm

IO Board

HD Audio

Card Reader RTS 5178 (2in1)
IO Board

PCI Express (Half)
Mini card Slot 1
WLAN/WiMAX
3

CMOS Camera
BlueTooth CONN

LPC BUS

SPI ROM
BIOS

PCI-E(WLAN)

3

4MB*1
2MB*1

EC
ENE KB9012

LAN(10/100/Giga)

2Channel Speaker

Realtek
8105E-VD (10/100)
8111F-CGT (Giga)

Single Digital MIC

Audio Codec
RealTek
ALC259-VC2-CG

Touch Pad

Sub-borad

Audio Combo Jack
(APPLE type)

RJ45 CONN

ODD Board
4

Int.KBD

HeadPhone Output
Microphone Input

Thermal Sensor

4

POWER BOARD
LED BOARD
Compal Secret Data

Security Classification
2011/07/21

Issued Date

IO Board

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.2

LA-8971P

USB2.0*2,card reader

Date:

A

Compal Electronics, Inc.
MB Block Diagram

B

C

D

Wednesday, February 15, 2012

Sheet
E

2

of

58

A

B

C

D

Voltage Rails

E

SIGNAL

STATE

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON
+5VS
+3VS

power
plane

+1.5VS
+V1.05S_VCCP

1

+5VALW

+1.5V

+VCC_CORE

+B

+VGA_CORE
+3VALW

+VCC_GFXCORE_AXG
+1.8VS

State

+0.75VS

Board ID
0
1
2
3
4
5
6
7

+1.05VS

S0

O

S3

O

O

O

O

O

O

X

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

BOARD ID Table

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re

PCB Revision
0.1

Board ID

0
1
2
3
4
5
6
7

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

Porject

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

G-series
G-series
G-series
G-series
Y-series
Y-series
Y-series
Y-series

Phase

MP
PVT
DVT
EVT
EVT
DVT
PVT
MP

2

2

S5 S4/AC

USB Port Table
USB 3.0
xHCI1
xHCI2
xHCI3
xHCI4

Address

EC SM Bus1 address

EC SM Bus2 address

Device

Device

Smart Battery

USB 2.0

Port
UHCI0
UHCI1

EHCI1
UHCI2

Address

Thermal Sensor F75303M

0001 011X b

BOM Structure Table

1001_101xb

UHCI3

PCH SM Bus address

3

UHCI4

Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

EHCI2

UHCI5
UHCI6

AMD-GPU SM Bus address
Device

Address

Internal thermal sensor

1001 111Xb (0x9E)

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB 3.0 Port (Left Side)
USB/B (Right Side USB-BD)
USB/B (Right Side USB-BD)
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )

Camera
Blue Tooth
Mini Card(WLAN)
USB Port (Right Side CR-BD)
X (USB PORT disabled on HM70 )

HM70 Disable xHCI3,xHCI4

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
4

SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB9012
+3VALW
KB9012
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW

VGA

X
X

BATT

V

+3VALW

X

KB9012 SODIMM

X
X

X

X

X

X

X

V

X

+3VS

3

X (USB PORT disabled on HM70 )

SATA Port Table

SOURCE

BTO Item
BOM Structure
INTEL UMA only
UMA@
GPU:Seymour XTX
XTX@
HDMI
HDMI@
HDD1 (HM77 SATA 3.0)
HDD1@
HDD2 (HM70 SATA 2.0)
HDD2@
Interna-Intel-USB3.0
IU3@
Interna-Intel-USB2.0
IU2@
Blue Tooth
BT@
10/100 LAN
8105E@
GIGA LAN
8111F@
Connector
ME@
45 LEVEL
45@
Unpop
@

X
X

X
X

Thermal
Sensor

X
X

PCH

X
V
+3VS

+3VS

+3VS

V

X

X

X

X

X

X

X

V

X

X

V

X

+3VS

V

WLAN
WWAN

+3VS

SATA
SATA
SATA
SATA
SATA
SATA

PCIe Port Table

HM70
HM77
P0 GEN3/2/1 GEN3/2/1 SSD
P1 GEN3/2/1 Disable HDD (HM77)
P2 GEN2/1 GEN2/1 HDD (HM70)
P3 GEN2/1 Disable
P4 GEN2/1 GEN2/1
P5 GEN2/1 GEN2/1

HM70 Disable P1,P3

PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe

HM70

Enable

Enable

LAN

Enable

Enable

WLAN

Enable

Enable

Enable

Enable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

4

2011/06/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/11

Deciphered Date

Title

Date:

B

HM77

HM70 Disable P5,P6,P7,P8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

P1
P2
P3
P4
P5
P6
P7
P8

C

D

Notes List
Document Number

Rev
0.2

LA-7981P
Wednesday, February 15, 2012

Sheet
E

3

of

58

5

4

3

2

1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails

D

ACTIVE

(N13x GPIO)

Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
GPU
(4)

Mem
(1,5)

NVCLK
/MCLK

Products

(W)

(W)

(MHz)

(V)

(A)

(W)

(A)

N13P-GL
64bit
1GB
GDDR3

TBD

TBD

TBD

TBD

TBD

TBD

TBD

GPIO

I/O

GPIO0

OUT

-

GPU VID4

GPIO1

OUT

-

GPU VID3

GPIO2

OUT

H

Panel Back-Light brightness(PWM capable)

GPIO3

OUT

H

Panel Power Enable

GPIO4

OUT

H

Panel Back-Light On/Off (PWM)

Physical
Strapping pin
ROM_SCLK

GPIO5

OUT

-

GPU VID1

GPIO6

OUT

-

GPIO7

OUT

N/A

Function Description

GPU VID2

GPIO8

I/O

-

Thermal Catastrophic Over Temperature

GPIO9

OUT

-

Thermal Alert

GPIO10

OUT

-

Memory VREF Control

GPIO11

OUT

-

GPU VID0

IN

GPIO13

OUT

-

GPIO14

OUT

N/A

GPIO15

IN

GPIO16

OUT

GPIO17

IN

GPIO18

IN

GPIO19

AC Power Detect Input

I/O and
PLLVDD
(1.05V)

Other

(W)

(A)

(W)

(mA)

(W)

(mA)

(W)

(mA)

(W)

(mA)

(W)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

(3.3V)

D

Logical
Strapping Bit0

PCI_DEVID[4]

Logical
Strapping Bit2
SUB_VENDOR

Logical
Strapping Bit1

+3VS_VGA

SLOT_CLK_CFG

PEX_PLL_EN_TERM

ROM_SI

+3VS_VGA

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VS_VGA

FB[1]

FB[0]

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VS_VGA

USER[3]

USER[2]

USER[1]

USER[0]

STRAP1

+3VS_VGA

STRAP2

+3VS_VGA

PCI_DEVID[3]

PCI_DEVID[2]

PCI_DEVID[1]

STRAP3

+3VS_VGA

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

STRAP4

+3VS_VGA

PCIE_SPEED_
CHANGE_GEN3

PCIE_MAX_SPEED

DP_PLL_VDD33V

Power Rail

(10K pull low)

Logical
Strapping Bit3

3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]

RESERVED

3GIO_PAD_CFG_ADR[0]
PCI_DEVID[0]

GPU VID5

C

N13P-GL
(28nm)

???

N13M-GE
(28nm)

???

Hot plug detect for IFP link C
FB Memory (GDDR3)

GPU

N/A
N/A

Samsung
2500MHz

K4G10325FG-HC04

Hynix
2500MHz

H5GQ1H24BFR-T2C

Samsung
2500MHz

K4G20325FG-HC04

32Mx32

Hot Plug Detect for IFPE

IN

N/A
N13P-GL
N13M-GE

B

PCI Express I/O and
(1.05V)
PLLVDD
(6)
(1.8V)

Device ID

C

GPIO12

FBVDDQ
(GPU+Mem)
(1.35V)

FBVDD
(1.35V)

NVVDD

32Mx32

64Mx32

+3VS_VGA

ROM_SO

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

PD 10K

PD 15K

PD 20K

PU 20K

PD 35K

PU 45K

PD 10K

PD 15K

PD 15K

PU 20K

PD 35K

PU 45K

PD 10K

PD 15K

PD 20K

PU 20K

PD 35K

PU 45K
B

Hynix
2500MHz

+VGA_CORE

H5GQ2H24MFR-T2C
64Mx32

PD 10K

PD 15K

PD 20K

PU 20K

PD 35K

PU 45K

tNVVDD >0

+1.5VS_VGA

X76

tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A

A

Tpower-off <10ms

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/15

Issued Date

1.all GPU power rails should be turned off within 10ms

Deciphered Date

2012/07/11

Title

VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.2

LA-7981P

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

4

of

58

A

B

C

D

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

1

+1.05VS_VTT

R249
24.9_0402_1%
UCPU1A

M2
P6
P1
P10

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

<16>
<16>
<16>
<16>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

N3
P7
P3
P11

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

<16>
<16>
<16>
<16>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

K1
M8
N4
R2

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

<16>
<16>
<16>
<16>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

K3
M7
P4
T3

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

U7
W11
W1
AA6
W6
V4
Y2
AC9

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

U6
W10
W3
AA7
W7
T4
AA3
AC8

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

<16>
<16>

FDI_FSYNC0
FDI_FSYNC1

FDI_FSYNC0
FDI_FSYNC1

<16>

FDI_INT

FDI_INT

<16>
<16>

FDI_LSYNC0
FDI_LSYNC1

FDI_LSYNC0
FDI_LSYNC1

AA11
AC12
U11

FDI0_FSYNC
FDI1_FSYNC
FDI_INT

AA10
AG8

FDI0_LSYNC
FDI1_LSYNC

AF3
AD2
AG11

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

2

R247
24.9_0402_1%
EDP_COMP

W=12mil L=500mil S=15mil

3

AG4
AF4

eDP_AUX#
eDP_AUX

AC3
AC4
AE11
AE7

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

AC1
AA4
AE10
AE6

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP

eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...

PCI EXPRESS -- GRAPHICS

1

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

+1.05VS_VTT

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

2

<16>
<16>
<16>
<16>

2

W=12mil L=500mil S=15mil

1

PEG_COMP

G3
G1
G4

E

1

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N15

C259
C276
C257
C274
C254
C272
C252
C270

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_GTX_HRX_N8
PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N12
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P15

C258
C277
C256
C275
C255
C273
C253
C271

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_P10
PEG_GTX_HRX_P11
PEG_GTX_HRX_P12
PEG_GTX_HRX_P13
PEG_GTX_HRX_P14
PEG_GTX_HRX_P15

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_HTX_GRX_N8
PEG_HTX_GRX_N9
PEG_HTX_GRX_N10
PEG_HTX_GRX_N11
PEG_HTX_GRX_N12
PEG_HTX_GRX_N13
PEG_HTX_GRX_N14
PEG_HTX_GRX_N15

C562
C582
C564
C584
C566
C587
C568
C589

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_GTX_HRX_N[8..15]
PEG_GTX_HRX_P[8..15]
PEG_HTX_C_GRX_N[8..15]
PEG_HTX_C_GRX_P[8..15]

<23>
<23>
<23>
<23>

2

3

PEG_HTX_GRX_P8
PEG_HTX_GRX_P9
PEG_HTX_GRX_P10
PEG_HTX_GRX_P11
PEG_HTX_GRX_P12
PEG_HTX_GRX_P13
PEG_HTX_GRX_P14
PEG_HTX_GRX_P15

C561
C583
C563
C585
C565
C586
C567
C588

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15

IVY-BRIDGE_BGA1023

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Issued Date

Deciphered Date

2012/07/12

Title

PROCESSOR(1/7) DMI,FDI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P
Sheet

Wednesday, February 15, 2012
E

5

of

58

A

B

C

1

D

E

1

UCPU1B

PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS

@
T33
PAD

XBOX 三三三三
<19,42>

1 R534
2
62_0402_5%
H_PROCHOT#

+1.05VS_VTT
<42,49>

H_PROCHOT#

H_PECI

1 R533
2
56_0402_5%

Follow DG 1.5& Tacoma_Fall2 1.0
<19>

reserve

H_THERMTRIP#

PROC_SELECT#
PROC_DETECT#

H_CATERR#

C49

H_PECI

A48

H_PROCHOT#_R

H_THERMTRIP#

C45

D45

DPLL_REF_CLK
DPLL_REF_CLK#

PECI

PROCHOT#

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

<19>

H_CPUPWRGD

H_CPUPWRGD

1 R305
2
0_0402_5%

H_PM_SYNC

C48

PM_SYNC

H_CPUPWRGD_R

B46

UNCOREPWRGOOD

1 R237
2 VDDPWRGOOD_R
130_0402_1%

BUF_CPU_RST#

BE45

D44

PWR MANAGEMENT

UNCOREPWRGOOD:非
非CORE外
外外外OK

H_PM_SYNC

2 1K_0402_5%
1 1K_0402_5%

+1.05VS_VTT

AT30

H_DRAMRST#

BF44
BE43
BG43

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

H_DRAMRST#
R272 1
R273 1
R267 1

2 140_0402_1%
2 25.5_0402_1%
2 200_0402_1%

@
C82
100P_0402_50V8J

<7>

1

2

ESD
C Reserve

THERMTRIP#

2 R292
1
10K_0402_5%
<16>

R516 1
R517 2

DDR3 Compensation Signals

PRDY#
PREQ#

N53
N55

TCK
TMS
TRST#

L56
L55
J58

TDI
TDO

M60
L59

XDP_TDI
XDP_TDO

DBR#

K58

XDP_DBRESET#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

G58
E55
E59
G55
G59
H60
J59
J61

H_CPUPWRGD_R

2

CLK_CPU_DPLL
CLK_CPU_DPLL#

<15>
<15>

SM_RCOMP2
W=15mil L=500mil S=13mil

SM_DRAMPWROK

RESET#

JTAG & BPM

1 0.1U_0402_16V4Z

AG3
AG1

CLK_CPU_DMI
CLK_CPU_DMI#

SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil

@
C614 2

CLK_CPU_DMI
CLK_CPU_DMI#

J3
H2

CATERR#

THERMAL

PCH->CPU
UNCOREPWRGOOD:非
非CORE外
外外外OK
SM_DRAMPWROK:DRAM power ok
RESET#:都
都ok後
後後CPU做
做reset

F49
C57

CLOCKS

R35 2
@
1
10K_0402_5%

DDR3
MISC

H_SNB_IVB#

MISC

<18>

BCLK
BCLK#

XDP_TCK
XDP_TMS
XDP_TRST#

+1.05VS_VTT
XDP_TMS
XDP_TDI
XDP_TDO

R20
R39
R37

2
2
2

1 51_0402_5%
1 51_0402_5%
1 51_0402_5%

XDP_TCK
R40
XDP_TRST# R28

2
2

1 51_0402_5%
1 51_0402_5%

2

PU/PD for JTAG signals
+3VS
XDP_DBRESET#

R312 2

@

1 1K_0402_5%

Tacoma_Fall2 1.0 PH 1K +3VS
Check list 1.5 PH 1K +3VS
Debug port DG1.1-1.3 50~5K ohm

IVY-BRIDGE_BGA1023

+3VALW

Buffered reset to CPU
+3VS

SUSP

R13 1
@
2
0_0402_5%

2
G
S

R14 1
@
2
0_0402_5%

5
P

2
1 R544
2
43_0402_5%

BUFO_CPU_RST#

4

NC

Y
A

U45
SN74LVC1G07DCKR_SC70-5
1

2PCH_PLTRST#

PCH_PLTRST#

<18>

3

@
C43
0.1U_0402_16V4Z

1
<10,47,52>

RUN_ON_CPU1.5VS3#

BUF_CPU_RST#

@
Q4
2N7002K_SOT23-3

R9 2
@
1
0_0402_5%

3

RUN_ON_CPU1.5VS3#

1

1
R546
75_0402_5%
@
R38
39_0402_5%

2

U22
74AHC1G09GW_TSSOP5

1

A

C617
0.1U_0402_16V4Z

PM_SYS_PWRGD_BUF

4

G

O

D
<10>

+1.05VS_VTT

R238
200_0402_5%

2
2

B

2

PM_DRAM_PWRGD

1

P

2 10K_0402_5%

1

PM_DRAM_PWRGD

@

3

<16>

R60 1

G

SYS_PWROK

SYS_PWROK

2

2 10K_0402_5%
5

R31 1

<16>

3

2

+3VS

1

C228
0.1U_0402_16V4Z

3

1

+1.5V_CPU_VDDQ

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Deciphered Date

2012/07/12

Title

PROCESSOR(2/7) DDRIII

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012
E

Sheet

6

of

58

A

B

C

D

UCPU1C

UCPU1D
<13>

1

2

<12>
<12>
<12>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

BD37
BF36
BA28

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

BE39
BD39
AT41

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

3

<12>
<12>
<12>

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

SA_CAS#
SA_RAS#
SA_WE#

AU36
AV36
AY26

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

AT40
AU40
BB26

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

BB40
BC41

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

AY40
BA41

M_ODT0
M_ODT1

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_B_D[0..63]

M_CLK_DDR0
<12>
M_CLK_DDR#0
<12>
DDR_CKE0_DIMMA
<12>

M_CLK_DDR1
<12>
M_CLK_DDR#1
<12>
DDR_CKE1_DIMMA
<12>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

<12>
<12>

<12>
<12>

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

<12>

<12>

<12>

<13>
<13>
<13>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<13>
<13>
<13>

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

BG39
BD42
AT22

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AV43
BF40
BD45

IVY-BRIDGE_BGA1023

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

BA34
AY34
AR22

M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB

BA36
BB36
BF27

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

BE41
BE47

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AT43
BG47

M_ODT2
M_ODT3

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2
<13>
M_CLK_DDR#2
<13>
DDR_CKE2_DIMMB
<13>
1

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

DDR SYSTEM MEMORY B

DDR_A_D[0..63]

DDR SYSTEM MEMORY A

<12>

E

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

M_CLK_DDR3
<13>
M_CLK_DDR#3
<13>
DDR_CKE3_DIMMB
<13>

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

<13>
<13>

<13>
<13>

DDR_B_DQS#[0..7]

<13>

2

DDR_B_DQS[0..7]

<13>

DDR_B_MA[0..15]

<13>

3

IVY-BRIDGE_BGA1023

R216 1
@
2
0_0402_5%

R212
1K_0402_5%

2

CPU通通DIMM做reset

1

+1.5V

H_DRAMRST#

SM_DRAMRST#_R
1
Q16
BSS138_NL_SOT23-3

3

1

H_DRAMRST#

D

S

<6>

2

2

G

R217
4.99K_0402_1%
4

<10,15>

DRAMRST_CNTRL_PCH

DRAMRST_CNTRL_PCH

1

2

C190
0.047U_0402_16V7K

1 R219
2
1K_0402_5%

SM_DRAMRST#

S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset

<12,13>

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Classification
2011/06/24

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

PROCESSOR(3/7) DDRIII

C

D

Rev
0.1

LA-8971P
Sheet

Wednesday, February 15, 2012
E

7

of

58

A

B

C

D

E

CFG Straps for Processor
CFG2

2

@
R91
100_0402_1%
VCC_VAL_SENSE
VSS_VAL_SENSE

H43
K43

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

H45
K45

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48
K48

RSVD6
RSVD7

1

VSS_VAL_SENSE

R306
49.9_0402_1%

2

@
T18
PAD

2

1

+VGFX_CORE

VAXG_VAL_SENSE

1

2

R310
49.9_0402_1%

2

@
R95
100_0402_1%

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

VSSAXG_VAL_SENSE

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

M13
M14
U14
W14
P13

RSVD39
RSVD40

AT49
K24

RSVD41
RSVD42
RSVD43
RSVD44

AH2
AG13
AM14
AM15

RSVD45

N50

2

N42
L42
L45
L47

1

PEG Static Lane Reversal - CFG2 is for the 16x

*

0:Lane Reversed

UMA,Optimus eDP啟
啟啟
DISO eDP關
關關

CFG4
@
R293
1K_0402_1%

eDP enable

*

CFG4
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

1:Disable
0:Enable

2

CFG5
CFG6
@
R543
1K_0402_1%

These pins are for solder joint
reliability and non-critical to
function. For BGA only.

R541
1K_0402_1%

PCIE Port Bifurcation Straps

1

CFG[6:5]
R311
49.9_0402_1%

(Default) 1x16 PCI Express
*11:
10: 2x8 PCI Express
01: Reserved

IVY-BRIDGE_BGA1023

00: 1x8,2x4 PCI Express

2

3

1: Normal Operation; Lane # definition matches
socket pin map definition

CFG2

1

1

VCC_VAL_SENSE

RSVD30
RSVD31
RSVD32
RSVD33

R296
1K_0402_1%

2

2

R302
49.9_0402_1%

N59
N58

1

1

CFG4
CFG5
CFG6
CFG7

BCLK_ITP
BCLK_ITP#

2

+CPU_CORE

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

1

CFG2
1

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

2

CFG0

RESERVED

@
T32
PAD

1

UCPU1E

3

1

CFG7

2

@
R297
1K_0402_1%

Tacoma_Fall2 1.0 P.12

PEG DEFER TRAINING
CFG7

1: (Default) PEG Train immediately following
xxRESETB de assertion
0: PEG Wait for BIOS for training

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Issued Date

Deciphered Date

2012/07/12

Title

PROCESSOR(4/7) RSVD,CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P
Sheet

Wednesday, February 15, 2012
E

8

of

58

C

POWER

8.5A

INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
CAP at Power side

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

For PEG

2

+3VS

R521
10K_0402_5%
+1.05VS_VTT

VCCIO50
VCCIO51

VCCIO_SEL

W16
W17

VCCIO_SEL after Ivy bridge ES2 Voltage support

@
R522
10K_0402_5%

BC22
2

VCCIO_SEL

BC22

*

1/NC : (Default) +1.05VS_VTT
0: +1.0VS_VTT

VCCIO_SEL

+1.05VS_VTT

C553
1U_0402_6.3V6K

+1.05VS_VTT

R529
75_0402_5%

VIDALERT#
VIDSCLK
VIDSOUT

A44
B43
C44

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R528 1
R527 1
R530 1

VCC_SENSE
VSS_SENSE

F43 VCCSENSE_R
G43 VSSSENSE_R

R282 1
R289 1

2 R513

0_0402_5%
0_0402_5%

1 10_0402_5%

VCCIO_SENSE
VSSIO_SENSE_L

1 R79 @ 2
100_0402_1%

R281
100_0402_1%
VCCSENSE
VSSSENSE

+1.05VS_VTT
R288
100_0402_1%

VCCIO_SENSE
<54>
VSSIO_SENSE_L
<54>

1

Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.

R512
10_0402_5%

IVY-BRIDGE_BGA1023

2

Check list 1.5

2011/06/24

Deciphered Date

2012/07/12

Title

PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

A

<56>
<56>

2

AN16
AN17

2
2

1

+CPU_CORE

VCCIO_SENSE
VSS_SENSE_VCCIO

Issued Date

VR_SVID_ALRT#
<56>
VR_SVID_CLK
<56>
VR_SVID_DAT
<56>

1

SENSE LINES

2 43_0402_1%
2 0_0402_5%
2 0_0402_5%

2

SVID

2

R531
130_0402_5%

3

Place the PU
resistors close to CPU

2

AM25
AN22

1

+1.05VS_VTT

VCCPQE[1]
VCCPQE[2]

Place the PU
resistors close to VR

4

1

1

PEG IO AND DDR IO

For DDR

2

3

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

QUIET
RAILS

2

CORE SUPPLY

INTEL Recommend VCC
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at Power side

1

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

+1.05VS_VTT

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

2

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

+CPU_CORE

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

E

1

UCPU1F

ULV type
DC 33A

D

1

B

1

A

D

Rev
0.1

LA-8971P
Sheet

Wednesday, February 15, 2012
E

9

of

58

B

C

+1.5V_CPU_VDDQ
@

R86
2
1

U11
AO4430L_SO8

2
1

1
1

2
R85
82K_0402_5%

C157

2

1 0.1U_0402_10V7K

DRAMRST_CNTRL_PCH

R148 1
@
2
0_0402_5%

3

Q8
2N7002K_SOT23-3

1

Q10
BSS138_NL_SOT23-3
C115
0.047U_0603_25V7K

DRAMRST_CNTRL_PCH

1

1

2

2
1

2
1
2

2

2
1

1
2

2

1
2

1

1
2

2

1
2

1

1
2

2

1
2

1

1
2

2

1
2

1

1
2

2

1
2

1

1
2

2

1
2

1
2

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

AM28
AN26
1

VCCDQ[1]
VCCDQ[2]

C317
1U_0402_6.3V6K

2

QUIET RAILS

1.8V RAIL

SENSE
LINES

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

SENSE LINES

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

SA RAIL

6A

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

VCCSA VID
lines

1

1
2

2

1
2

1

VREF
- 1.5V RAILS
DDR3

GRAPHICS

2
1

VAXG_SENSE
VSSAXG_SENSE

2
1
2

1
2

1

+ C286
330U_2.5V_M
SF000002Z00

2

C298

C339

10U_0603_6.3V6M

C299

10U_0603_6.3V6M

C295

10U_0603_6.3V6M

C296

10U_0603_6.3V6M

C338

10U_0603_6.3V6M

C337

10U_0603_6.3V6M

1

1

C316

C349

1U_0402_6.3V6K

C320

1U_0402_6.3V6K

1U_0402_6.3V6K

C318

C312

1U_0402_6.3V6K

1U_0402_6.3V6K

C328

C348

1U_0402_6.3V6K

2

G

2

INTEL Recommend VDDQ
1*330uF,8*10uF(0603) ,10*1uF(0402)
PD0.8

Place BOT OUT BGA

C340

2

D

+1.5V_CPU_VDDQ

Place TOP IN BGA

10U_0603_6.3V6M

C308

C301

1U_0402_6.3V6K

1U_0402_6.3V6K

C300

C302

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C309

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

1U_0402_6.3V6K

+ C242
330U_D2_2V_Y

@
R116
1K_0402_1%~D

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18 M1 default M3 no stuff

1U_0402_6.3V6K

+VCCSA
1

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

10U_0603_6.3V6M

Place TOP IN BGA

+V_SM_VREF

RUN_ON_CPU1.5VS3

R124
1K_0402_1%~D

5A
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

C351

+VCCSA

1
@
Q11
AO3414_SOT23-3

@
R518
1K_0402_1%

C329

2

3

C117
0.1U_0402_16V4Z

1U_0402_6.3V6K

1

1U_0402_6.3V6K

2

C280

1

1U_0402_6.3V6K

C281

C153

10U_0603_6.3V6M

C633

22U_0805_6.3V6M

2

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

@
R519
1K_0402_1%

1.2A
BB3
BC1
BC4

+

@
R76
1K_0402_1%~D

3

Place BOT OUT Conn
1

1 0_0402_5%

+1.5V_CPU_VDDQ

F45
G45

R309
100_0402_5%

@
C287
330U_2.5V_M
SF000002Z00

+V_SM_VREF_CNT

BE7
BG7

@
1 R87
2
100_0402_5%

R308
100_0402_5%

<56> VCC_AXG_SENSE
<56> VSS_AXG_SENSE

+1.8VS

AY43

C321

+VGFX_CORE

SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

1U_0402_6.3V6K

CR CheckList Rev1.5

@

S

2

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

+1.5V

R117 2
R113
1K_0402_1%~D

1U_0402_6.3V6K

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

INTEL Recommend VAXG
2*470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8

INTEL Recommend VCCPLL
1*330uF,2*1uF(0402)
PD0.8

POWER

DC 29A

1

UCPU1G
+VGFX_CORE

+V_SM_VREF_CNT should
have 20 mil trace width

2

<6>

1

+1.5V_CPU_VDDQ
RUN_ON_CPU1.5VS3#

3

+V_DDR_REFB

1

3

S

3

2

G

<7,15>

2

@
R77
330K_0402_5%

D
2

DRAMRST_CNTRL_PCH

1

1 R175
2
15K_0402_1%

1
1

1
D

S

2 0_0402_5%

1 0.1U_0402_10V7K

2

2
@

2

SB_DIMM_VREFDQ
RUN_ON_CPU1.5VS3

3

R82 1

SUSP#

C152
RUN_ON_CPU1.5VS3#

G

<42,47,52,54>

@
Q6
2N7002K_SOT23-3
2
G

1 0.1U_0402_10V7K

+V_DDR_REFA

1

D

CPU1.5V_S3_GATE

2 0_0402_5%

2

3

S

<42,47>

@

C151

Q7
2N7002K_SOT23-3

S

RUN_ON_CPU1.5VS3#

R81 1

1 0.1U_0402_10V7K
Q9
BSS138_NL_SOT23-3

G

@
R78
100K_0402_5%

1

2

D

4

+VSB

+3VALW

R80
220_0402_5%

1
2
3

C150

@
1
2
0_0402_5%

G

8
7
6
5

SA_DIMM_VREFDQ

@
C116
0.1U_0402_10V6K

D

SUSP

2 0_0402_5%

+1.5V

S

<6,47,52>

R65

1

+1.5V_CPU_VDDQ

PAD-OPEN 4x4m

2

J1
1

1

E

M3 Support

2

+1.5V

D

2

A

BC43
BA43

VDDQ_SENSE
VSS_SENSE_VDDQ

R248 1
@
2
0_0402_5%

VCCSA

U10

VCCSA_SENSE

VCCSA_SENSE

CPU EDS1.3 P.93
VCCSA_VID0 Must PD
D48
D49

VCCSA_VID[0]
VCCSA_VID[1]

H_VCCSA_VID0
H_VCCSA_VID1

H_VCCSA_VID0
H_VCCSA_VID1

<53>

<53>
<53>

VID0 VID1 Vout

HR

CR

0

0

0.9V

V

V

0

1

0.85V

V

V

1

0

0.725V

X

V

1

1

0.675V

X

V

B phase Cost down proposal
4

4

IVY-BRIDGE_BGA1023

1

1
2

2

1
2

1
2

2

C559

C579

10U_0603_6.3V6M

C555

10U_0603_6.3V6M

C560

10U_0603_6.3V6M

C577

10U_0603_6.3V6M

10U_0603_6.3V6M

INTEL Recommend VCCSA
1*330uF,5*10uF(0603) ,5*1uF(0402)
PD0.8

1

Place BOT OUT BGA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security
Security Classification
Classification
2011/06/24

Deciphered Date

2012/07/12

Title

PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012
E

Sheet

10

of

58

A

B

C

D

E

UCPU1H
UCPU1I

2

3

4

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS

NCTF

1

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

1

2

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

3

IVY-BRIDGE_BGA1023

4

Issued Date
IVY-BRIDGE_BGA1023

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Deciphered Date

2012/07/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

PROCESSOR(7/7) VSS

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

11

of

58

A

B

C

D

E

+1.5V

DDR3 SO-DIMM A

DDR_A_DM3
DDR_A_D26
DDR_A_D27

<7,13>

Layout Note:
Place near JDIMM1
+1.5V

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

2

1

2

1

2

1

2

1

2

1

2

1

2

@

1

2

@
CD14

+

1

2

10U_0603_6.3V6M

1

DDR_A_D22
DDR_A_D23

CD13

DDR_A_DM2

10U_0603_6.3V6M

DDR_A_D20
DDR_A_D21

CD12

DDR_A_D24
DDR_A_D25

SM_DRAMRST#

DDR_A_D14
DDR_A_D15

10U_0603_6.3V6M

DDR_A_D18
DDR_A_D19

DDR_A_DM1
SM_DRAMRST#

CD11

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D12
DDR_A_D13

10U_0603_6.3V6M

DDR_A_D16
DDR_A_D17

DDR_A_D6
DDR_A_D7

CD10

DDR_A_D10
DDR_A_D11

1

DDR_A_DQS#0
DDR_A_DQS0

10U_0603_6.3V6M

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_MA[0..15]

DDR_A_D4
DDR_A_D5

CD9

DDR_A_D8
DDR_A_D9

DDR_A_DQS#[0..7]

<7>

10U_0603_6.3V6M

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CD8

DDR_A_DM0

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

DDR_A_DQS[0..7]

<7>

10U_0603_6.3V6M

2

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

DDR_A_D[0..63]

<7>

CD7

CD3

2

1

2.2U_0603_6.3V4Z

CD1

1

0.1U_0402_10V6K

CD2

2

2

0.1U_0402_10V6K

1

1

1

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

<7>

CD4

2

JDIMM1

+V_DDR_REFA

RD2
1K_0402_1%

+1.5V

10U_0603_6.3V6M

3A@1.5V

330U_B2_2.5VM_R15M

1

+1.5V
RD1
1K_0402_1%

DDR_A_D30
DDR_A_D31

2

2

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7

2 RD8
1
10K_0402_5%

2

2 RD7
1
10K_0402_5%

CD23

2

1
CD24

1

0.1U_0402_10V6K

+3VS
4

2.2U_0603_6.3V4Z

DDR_A_D58
DDR_A_D59

205
207

GND1
BOSS1

GND2
BOSS2

206
208

DDR_A_D36
DDR_A_D37

1

DDR_A_DM4
DDR_A_D38
DDR_A_D39

2

1

2

CD22

0.1U_0402_10V6K

<7>

CD21

M_ODT1

RD5
1K_0402_1%

<7>

+VREF_CA

RD6
1K_0402_1%

3

DDR_A_D44
DDR_A_D45

Layout Note:
Place near JDDRL.203,204

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

+0.75VS
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55

1

DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7

2

1

2

1

2

1

2

1U_0402_6.3V6K

DDR_A_D34
DDR_A_D35

M_ODT1

DDR_CS0_DIMMA#
M_ODT0 <7>

CD18

DDR_A_DQS#4
DDR_A_DQS4

3

DDR_A_BS1
<7>
DDR_A_RAS#
<7>

DDR_CS0_DIMMA#
M_ODT0

1U_0402_6.3V6K

DDR_A_D32
DDR_A_D33

+1.5V
0.1U_0402_10V6K

DDR_A_MA13
DDR_CS1_DIMMA#

+1.5V

<7>
<7>

CD17

DDR_CS1_DIMMA#

M_CLK_DDR1
M_CLK_DDR#1

1U_0402_6.3V6K

<7>

DDR_A_BS1
DDR_A_RAS#

CD20

DDR_A_WE#
DDR_A_CAS#

M_CLK_DDR1
M_CLK_DDR#1

0.1U_0402_10V6K

DDR_A_WE#
DDR_A_CAS#

Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM1

DDR_A_MA2
DDR_A_MA0

CD16

DDR_A_BS0

<7>
<7>

DDR_A_MA6
DDR_A_MA4

1U_0402_6.3V6K

<7>

DDR_A_MA10
DDR_A_BS0

DDR_A_MA11
DDR_A_MA7

CD19

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA15
DDR_A_MA14

0.1U_0402_10V6K

M_CLK_DDR0
M_CLK_DDR#0

<7>
<7>

<7>

CD15

DDR_A_MA3
DDR_A_MA1

DDR_CKE1_DIMMA

1

DDR_A_MA8
DDR_A_MA5

DDR_CKE1_DIMMA

2

DDR_A_MA12
DDR_A_MA9

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1

DDR_A_BS2

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

2

DDR_A_BS2

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

CD6

<7>

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2.2U_0603_6.3V4Z

DDR_CKE0_DIMMA

CD5

DDR_CKE0_DIMMA

0.1U_0402_10V6K

<7>

DDR_A_D62
DDR_A_D63
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA
<13,15,40,43>
PCH_SMBCLK
<13,15,40,43>
4

+0.75VS

0.65A@0.75V

TYCO_2-2013022-1
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Deciphered Date

2012/07/12

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

LA-8971P

Date:

A

B

C

D

Sheet

Wednesday, February 15, 2012
E

12

of

58

5

4

3

2

1

+1.5V
+1.5V

1

+1.5V

3A@1.5V
+V_DDR_REFB

DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

<7>

DDR_B_D32
DDR_B_D33
B

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7

2

1

2

0.1U_0402_10V6K

1

CD48

+3VS

CD47

A

2.2U_0603_6.3V4Z

DDR_B_D58
DDR_B_D59
1 RD13
2
10K_0402_5%

1 RD14
2
10K_0402_5%

205

G1

G2

206

1
CD26

2

2

10U_0603_6.3V6M

1
CD34

2

10U_0603_6.3V6M

1
CD33

2

10U_0603_6.3V6M

1
CD32

2

10U_0603_6.3V6M

1
CD31

2

10U_0603_6.3V6M

CD30

1

10U_0603_6.3V6M

CD25

10U_0603_6.3V6M

CD29

10U_0603_6.3V6M

2

DDR_B_D30
DDR_B_D31
C

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

<7>

DDR_B_MA15
DDR_B_MA14

Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM2

DDR_B_MA11
DDR_B_MA7

+1.5V

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

<7>
<7>
+1.5V

DDR_B_BS1
<7>
DDR_B_RAS#
<7>

DDR_CS2_DIMMB#
M_ODT2
M_ODT3

0.1U_0402_10V6K

DDR_B_WE#
DDR_B_CAS#

1

DDR_CS2_DIMMB#
M_ODT2 <7>
M_ODT3

<7>

RD11
1K_0402_1%

<7>

+VREF_CB
DDR_B_D36
DDR_B_D37

1

DDR_B_DM4
DDR_B_D38
DDR_B_D39

2

1

2

+VREF_CB

Layout Note:
Place near JDIMM2.203 and 204

RD12
1K_0402_1%

B

+0.75VS

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5

1

DDR_B_D46
DDR_B_D47

2

DDR_B_D52
DDR_B_D53

1

2

1

2

1

2

1U_0402_6.3V6K

DDR_B_WE#
DDR_B_CAS#

@

CD40

<7>
<7>

2

0.1U_0402_10V6K

DDR_B_BS0

1

CD44

<7>

DDR_B_MA10
DDR_B_BS0

@

1U_0402_6.3V6K

M_CLK_DDR2
M_CLK_DDR#2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_DQS#3
DDR_B_DQS3

2

CD39

DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2

<7>
<7>

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_B_D28
DDR_B_D29

0.1U_0402_10V6K

DDR_B_MA8
DDR_B_MA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

@ +

CD43

DDR_B_MA12
DDR_B_MA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

1

DDR_B_D22
DDR_B_D23

CD42

DDR_B_BS2

+1.5V

DDR_B_DM2

1U_0402_6.3V6K

DDR_CKE2_DIMMB

DDR_B_BS2

Layout Note:
Place near JDIMM2

DDR_B_D20
DDR_B_D21

CD38

DDR_CKE2_DIMMB

<7>

<7,12>

0.1U_0402_10V6K

<7>

SM_DRAMRST#

DDR_B_D14
DDR_B_D15

CD41

DDR_B_D26
DDR_B_D27
C

DDR_B_DM1
SM_DRAMRST#

1U_0402_6.3V6K

DDR_B_DM3

DDR_B_D12
DDR_B_D13

CD28

DDR_B_D24
DDR_B_D25

DDR_B_D6
DDR_B_D7

330U_B2_2.5VM_R15M

DDR_B_D18
DDR_B_D19

D

CD37

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_MA[0..15]

1

DDR_B_D16
DDR_B_D17

DDR_B_DQS#[0..7]

<7>

2

DDR_B_D10
DDR_B_D11

DDR_B_DQS[0..7]

<7>

1

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D[0..63]

<7>

DDR_B_DQS#0
DDR_B_DQS0

CD46

DDR_B_D8
DDR_B_D9

DDR_B_D4
DDR_B_D5

2.2U_0603_6.3V4Z

DDR_B_D2
DDR_B_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

CD45

2

DDR_B_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

0.1U_0402_10V6K

CD36

2

1

DDR_B_D0
DDR_B_D1

2.2U_0603_6.3V4Z

2

1
CD27

2

RD10
1K_0402_1%

CD35

1

0.1U_0402_10V6K

1

D

0.1U_0402_10V6K

2

JDIMM2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

<7>

2

RD9
1K_0402_1%

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK

A

PCH_SMBDATA <12,15,40,43>
PCH_SMBCLK <12,15,40,43>
+0.75VS

0.65A@0.75V

TYCO_2-2013287-1
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Deciphered Date

2012/07/12

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

LA-8971P

Date:

5

4

3

2

Sheet

Wednesday, February 15, 2012
1

13

of

58

A

B

W=20mils

C441
1U_0603_10V4Z

U13A

2

A20

PCH_RTCX2

C20

PCH_RTCRST#

R356 1
2
20K_0402_5%
R357 1
2
20K_0402_5%

PCH_SRTCRST#
1

1

CLRP2
SHORT PADS

Prevent back drive issue.

2

C440
1U_0603_10V6K

1

PCH_RTCX1

2

PCH_RTCRST#

D20

PCH_SRTCRST#

G22

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

G

2

+5VS

+RTCVCC

HDA_SYNC_PCH_R

3

2 1M_0402_5%

SM_INTRUDER#

R363 1

2 330K_0402_5%

PCH_INTVRMEN

H：
：Integrated VRM enable
L：
：Integrated VRM disable

N34

HDA_SYNC_PCH

L34

PCH_SPKR

PCH_SPKR

T10

1 R48 @ 2
0_0402_5%

HDA_RST_PCH#

K34

<31>

R29
1M_0402_5%

HDA_SDIN0

HDA_SDIN0

E34
G34

RTCX2

FWH4 / LFRAME#
SRTCRST#
INTRUDER#

LDRQ0#
LDRQ1# / GPIO23

INTVRMEN

SERIRQ

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0

A34

+3VS
R109 1

@

2 1K_0402_5%

PCH_SPKR

HDA_SDOUT_PCH

A36

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

*

LOW= Disable (Default internal PD)

C36
N32

+3V_PCH

HDA_SDIN2
HDA_SDIN3
HDA_SDO

HDA_DOCK_EN# / GPIO33

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

HDA_SDOUT_PCH
J3

PCH_JTAG_TMS

H7

HDA_SDO

PCH_JTAG_TDI

K5

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

PCH_JTAG_TDO

H1

*

1 R73
2
0_0402_5%

ME_FLASH

1 1K_0402_5%

2

On Die PLL VR Select is supplied by
1.5V when sampled high

*

PCH_SPI_CLK_2

R433 2 WIN8@ 1 33_0402_5%

PCH_SPI_CLK_1

R432 2

1 33_0402_5%

PCH_SPI_CLK

T3

PCH_SPI_CS0#_1

R127 2

1 33_0402_5%

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#_2

R446 2 WIN8@ 1 33_0402_5%

PCH_SPI_CS1#

T1

PCH_SPI_MOSI_2

R123 2 WIN8@ 1 33_0402_5%
PCH_SPI_MOSI

V4

PCH_SPI_MOSI_1

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

SATAICOMPI

JTAG_TDO
SATA3COMPI

HDA_SYNC_PCH

This signal has a weak internal pull-down

JTAG_TDI

SATAICOMPO

SATA3RCOMPO

+3V_PCH
R47

JTAG_TMS

R122 2

1 33_0402_5%
U3

PCH_SPI_MISO_1

R437 2

PCH_SPI_MISO_2

R438 2 WIN8@ 1 33_0402_5%

1 33_0402_5%

SPI_CLK

SATA3RBIAS

C38
A38
B37
C37

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

D36

LPC_FRAME#

E36
K36

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

V5

2 R118
1
10K_0402_5%
SERIRQ

AM3
AM1
AP7
AP5

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0

AM10
AM8
AP11
AP10

SATA_PRX_C_DTX_N1_R
SATA_PRX_C_DTX_P1_R
SATA_PTX_DRX_N1_R
SATA_PTX_DRX_P1_R

AD7
AD5
AH5
AH4

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1

<40,42>
<40,42>
<40,42>
<40,42>
<40,42>

1

+3VS
SERIRQ

<42>

C127 2
C131 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_C_DTX_N1_R
<38>
SATA_PRX_C_DTX_P1_R
<38>
SATA_PTX_DRX_N1_R
<38>
SATA_PTX_DRX_P1_R
<38>
SATA_PRX_C_DTX_N2
<38>
SATA_PRX_C_DTX_P2
<38>
SATA_PTX_DRX_N2 <38>
SATA_PTX_DRX_P2 <38>

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

3

HDA_BITCLK_AUDIO

R75 2
1
33_0402_5%

HDA_BITCLK_PCH

<31>

HDA_SYNC_AUDIO

R30 2
1
33_0402_5%

HDA_SYNC_PCH_R

<31>

HDA_RST_AUDIO#

R74 2
1
33_0402_5%

HDA_RST_PCH#

<31>

HDA_SDOUT_AUDIO

R72 2
1
33_0402_5%

HDA_SDOUT_PCH

HDD for HM70

Disable w/ HM70
SATA_PRX_C_DTX_N4
SATA_PRX_C_DTX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

SATA_PRX_C_DTX_N4
<39>
SATA_PRX_C_DTX_P4
<39>
SATA_PTX_DRX_N4 <39>
SATA_PTX_DRX_P4 <39>

ODD

Y3
Y1
AB3
AB1

2

Y11

L=500mil S=15mil

Y10

SATA_COMP

+1.05VS_VTT

1 R121
2
37.4_0402_1%
+1.05VS_VTT

AB12

L=500mil S=15mil

AB13

SATA3_COMP

1 R126
2
49.9_0402_1%

AH1

RBIAS_SATA3

1 R440
2
750_0402_1%

SPI_CS1#

SATALED#

SPI_MOSI

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

P3

PCH_SATALED#

2 R429

1 10K_0402_5%

V14

PCH_GPIO21

2 R136

1 10K_0402_5%

P1

BBS_BIT0_R

2 R466

1 10K_0402_5%

+3VS

PCH_SPI_MISO

R22
R89

1
3
7
4

1
PCH_JTAG_TDI

R142
100_0402_1%

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1

LPC
Reserved
SPI

GPIO51
0
0
1
1

GPIO19
0
1
0
1

3

Reserve for EMI
@

MX25L3206EM2I-12G_SO8
SA000041P00

1

+3VS

2
C459
10P_0402_50V8J

2

@
1 PCH_SPI_CLK
R434
33_0402_5%

U46 WIN8@
R21
R88

+3VS

1 WIN8@ 2 3.3K_0402_5%
1 WIN8@ 2 3.3K_0402_5%

SPI ROM FOR ME (2MB)
Footprint 200mil

PCH_SPI_CS1#_2
SPI_WP2#
SPI_HOLD2#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2

MX25L1606EM2I-12G_SO8
SA000041N00

2

R140
100_0402_1%
2

2

R141
100_0402_1%

2 3.3K_0402_5%
2 3.3K_0402_5%

R137
200_0402_5%
2

PCH_JTAG_TMS

1
1

PCH_SPI_CS0#_1
SPI_WP1#
SPI_HOLD1#

SPI ROM FOR ME (4MB)
Footprint 200mil

1

2

R143
200_0402_5%

1

PCH_JTAG_TDO

1

2

R134
200_0402_5%

*

+3VS
U44

+3V_PCH

1

1

+3V_PCH

Boot BIOS Strap
Boot BIOS

+3VS
+3V_PCH

mSATA

HDD for HM77

COUGARPOINT_FCBGA989

<31>

<40>
<40>
<40>
<40>

SPI_CS0#

SPI

<42>

JTAG_TCK

JTAG

PCH_JTAG_TCK

2 R100
1
51_0402_5%

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

2

1 R46 @ 2
1K_0402_5%

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA

C34

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1

IHDA

(INTVRMEN should always be pull high.)

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

RTCRST#

2

*

<31>

1

INTVRMEN

HDA_BITCLK_PCH

D

S

R358 1

Q3
BSS138_NL_SOT23-3
1

RTCX1

LPC

2

1

E

R59 1
2
1K_0402_5%

SATA 6G

1

1

C439
1U_0603_10V6K

+RTCVCC

CLRP1
SHORT PADS

D

+RTCBATT

W=20mils
2

C

+RTCVCC

RTC

CLRP1/2 close RAM door JDIMM1/2

PCH_RTCX1
PCH_RTCX2

1 R406
2
10M_0402_5%
4

4

Y2
1

2

32.768KHZ_12.5PF_9H03200019

1

1

C452
18P_0402_50V8J

2

C451
18P_0402_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

2011/06/24

2012/07/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number
Custom
Date:

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

14

of

58

A

B

C

D

E

+3V_PCH

U13B

BE38
BC38
AW38
AY38
Y40
Y39
2

WLAN

<40>
<40>

CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1
<40>

1 R287
1 R291

WLAN_CLKREQ#
+3VS

+3VS

PCIE LAN

<33>
<33>

CLK_PCIE_LAN#
CLK_PCIE_LAN

<33>

LAN_CLKREQ#
+3V_PCH

+3V_PCH

+3V_PCH

3

R213 2
1
10K_0402_5%

PCH_GPIO73

2 0_0402_5% CLK_PCIE_WLAN1#_R
2 0_0402_5% CLK_PCIE_WLAN1_R
WLAN_CLKREQ#

1 R215

J2
AB49
AB47
M1

PERN8
PERP8
PETN8
PETP8

1 R110
2
10K_0402_5%

PCH_GPIO20

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
R214 2
1
10K_0402_5%
R53 2
1
10K_0402_5%

R50 2
1
10K_0402_5%

PCH_GPIO26

PCH_GPIO44

PCH_HOT#

E14

PCH_SML1CLK

SML1DATA / GPIO75

M16

PCH_SML1DATA

CL_CLK1

T11

CL_RST1#

P10

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKOUT_PCIE4N
CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45
V46

CLKOUT_PCIE5N
CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

CLK_PCIE_VGA#
CLK_PCIE_VGA

AM12
AM13

PCH_GPIO56

R32 2
1
10K_0402_5%

PCH_GPIO45

+3V_PCH

R51 2
1
10K_0402_5%

PCH_GPIO46

T13

PCIECLKRQ6# / GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P

+3VS
PCH_SMBDATA

2 R371
1
4.7K_0402_5%

3

4

<12,13,40,43>

+3VS
PCH_SMBCLK

<12,13,40,43>

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1

Q33A
DMN66D0LDW-7_SOT363-6
PCH_SML1CLK

R152 1
R147 1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_DMI2_N
CLKIN_DMI2_P

BJ30
BG30

CLKIN_GND1#
CLKIN_GND1

R453 1
R452 1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_DOT_96N
CLKIN_DOT_96P

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R99
R93

1
1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

R139 1
R138 1

2 10K_0402_5%
2 10K_0402_5%

REFCLK14IN

K45

CLK_BUF_ICH_14M

R101 1

2 10K_0402_5%

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

Y47

W=12mil S=15mil
XCLK_RCOMP

EC_SMB_DA2

EC_SMB_DA2

<23,42,44>

3

4

EC_SMB_CK2

EC_SMB_CK2

<23,42,44>

Q33B
DMN66D0LDW-7_SOT363-6

2 OPT@ 1 R8
10K_0402_5%

+3V_PCH

1

R27
10K_0402_5%
PEG_CLKREQ#_R

CLK_PCI_LPBACK

1 R96
2
33_0402_5%

Pull up at EC side.
For VGA,EC,Thermal sensor
2

PCH_SML1DATA 6

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P

1

CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>

BF18
BE18

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

V40
V42

2 R404
1
4.7K_0402_5%

1

OPT@
Q2
2N7002K_SOT23-3
3

@
R23
2.2K_0402_5%

<18>

@1
2
C29
22P_0402_50V8J

DGPU_PWR_EN

<18,30,55>

2 C123 OPT@
0.1U_0402_16V4Z

PEG_CLKREQ#

<23>

Pull high @ VGA side

@
R12
2.2K_0402_5%

3

Reserve for EMI please close to PCH

2 R120
1
90.9_0402_1%

+1.05VS_VTT
+3VS

1

+3V_PCH

E6

For DDR

K12
AK14
AK13

PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX0 / GPIO64

K43

CLKOUTFLEX1 / GPIO65

F47

CLKOUTFLEX2 / GPIO66

H47

CLK_FLEX2

K49

DGPU_PRSNT#

CLKOUTFLEX3 / GPIO67

UMA@
R421
10K_0402_5%
@

T26 PAD
DGPU_PRSNT#

XTAL25_IN
XTAL25_OUT

1 R443
2
1M_0402_5%

1

R54 2
1
10K_0402_5%

1

<42>

CLKIN_DMI_N
CLKIN_DMI_P

FLEX CLOCKS

+3V_PCH

2.2K_0402_5%

+3VS

@

AB42
AB40

2.2K_0402_5%

2

Q34A
DMN66D0LDW-7_SOT363-6

AB37
AB38

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

PCIECLKRQ3# / GPIO25

Y43
Y45

2

R369 1

PCH_SMBDATA_R 6

PEG_CLKREQ#_R

AV22
AU22

CLKOUT_PCIE2N
CLKOUT_PCIE2P

Y37
Y36

R403 1

PCH_SML1DATA

+3VS

M10

CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18

PCIECLKRQ2# / GPIO20

PCH_SML1CLK

PCH_SMBCLK_R

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

PCH_HOT#

M7

CL_DATA1

CLKOUT_PCIE0N
CLKOUT_PCIE0P

V10

A8

C13

SML1CLK / GPIO58

+3V_PCH

Q34B
DMN66D0LDW-7_SOT363-6

2 10K_0402_5%
AA48
AA47

SML1ALERT# / PCHHOT# / GPIO74

10K_0402_5%

<7,10>

2

+3V_PCH

1 R373

2

5

PERN7
PERP7
PETN7
PETP7

1 R408

2.2K_0402_5% 2

R392 1

5

BG40
BJ40
AY40
BB40

2.2K_0402_5% 2

PCH_SML0DATA

1K_0402_5%

PCH_HOT#

1

PERN6
PERP6
PETN6
PETP6

PCH_SML0CLK

G12

2.2K_0402_5%

2

2

BJ38
BG38
AU36
AV36

C8

SML0CLK
SML0DATA

DRAMRST_CNTRL_PCH

2

DRAMRST_CNTRL_PCH R391 1

2

PERN5
PERP5
PETN5
PETP5

DRAMRST_CNTRL_PCH

R370 1

2

HM70 not support
PCIE port 4-7

BG37
BH37
AY36
BB36

A12

SML0ALERT# / GPIO60

PCH_SMBDATA_R

2
G

PERN4
PERP4
PETN4
PETP4

PCH_SMBDATA_R

2

2.2K_0402_5%

S

BF36
BE36
AY34
BB34

1

C9

SMBDATA

+3V_PCH

R405 1

D

PERN3
PERP3
PETN3
PETP3

PCH_SMBCLK_R

PCH_SMBCLK_R

1

BG36
BJ36
AV34
AU34

H14

1 10K_0402_5%

2

PERN2
PERP2
PETN2
PETP2

E12

SMBCLK

2 R33

1

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

PCH_GPIO11

2

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

Link

C482 1
C481 1

PERN1
PERP1
PETN1
PETP1

SMBUS

<40> PCIE_PRX_DTX_N2
<40> PCIE_PRX_DTX_P2
<40> PCIE_PTX_C_DRX_N2
<40> PCIE_PTX_C_DRX_P2

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

BG34
BJ34
AV32
AU32

Controller

C480 1
C478 1

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

CLOCKS

WLAN

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

PCI-E*

PCIE LAN

<33>
<33>
<33>
<33>

Y6
25MHZ_10PF_7V25000014

OPT@
R420
10K_0402_5%
C457
10P_0402_50V8J

2

COUGARPOINT_FCBGA989

1

2

3

3

1
GND

GND

4

2

1

1

C468
10P_0402_50V8J

2

GPIO67
DGPU_PRSNT#
4

4

DIS,Optimus
UMA

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

0
1

2011/06/24

2012/07/12

Deciphered Date

Title

PCH (2/9) PCIE, SMBUS, CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

15

of

58

A

B

C

D

E

U13C

R34

1

2 10K_0402_5%

SUSWARN#_R

R49

1

2 10K_0402_5%

PCH_GPIO72

R390 1

2 10K_0402_5%

RI#

R393 1

2 300_0402_5%

PM_DRAM_PWRGD

Follow G

R394 2

<5>
<5>
<5>
<5>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

<5>
<5>
<5>
<5>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

+1.05VS_VTT

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BE20
BG18
BG20

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI

+3V_PCH

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

1

<5>
<5>
<5>
<5>

AV12

FDI_FSYNC0

FDI_FSYNC1

BC10

FDI_FSYNC1

750_0402_1%

2

DMI2RBIAS

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DPWROK

E22

PCH_DPWROK

B9

PCH_PCIE_WAKE#

1 R155

C12

System Power Management

SUSACK#_R
1 DSP3@ 2
R270
0_0402_5%
1 R415
2
10K_0402_5%

SYS_RST#

K3

PCH_PWROK 1 R107
2
0_0402_5%

P12

PCH_PWROK_R

L22

<6>

PCH_ACIN

R26 2
1
200K_0402_5%
<42>

R263 1
@
2
0_0402_5%

AC_PRESENT

3

<23,42,50>

PM_DRAM_PWRGD
EC_RSMRST#
SUSWARN#

1 R125
2
0_0402_5%

B13

PCH_RSMRST#

C21

SUSWARN#_R
1 DSP3@ 2
R271
0_0402_5%

K16

PBTN_OUT#_R

E20

PBTN_OUT#

1 R129
2
0_0402_5%

ACIN

ACIN

PM_DRAM_PWRGD

PCH_ACIN
2
RB751V-40_SOD323-2

1
D3

H20

No use ,PH 10K +3VALW

PCH_GPIO72

E10

Ring Indicator CRB1.0 PH 10K +3VALW

RI#

A10

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_INT

FDI_FSYNC0

L10

+3V_PCH

FDI_INT

DMI_IRCOMP

SYS_PWROK

PBTN_OUT#

AW16

DMI_ZCOMP

not support AMT APWROK can mux
with PWROK (check list1.5 P.47)

<42>

FDI_INT
BJ24

+3VS

SUSWARN#

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

BG25

SUSACK#

EC_RSMRST#

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

DMI_IRCOMP

SUSACK#

<42>

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

2

L=500mil S=15mil

SUSACK#

2

<42>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

49.9_0402_1% 1 R156

4mil width and place
within 500mil of the PCH

<42>

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

1

+RTCVCC

PCH_RSMRST#

1 10K_0402_5%

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

FDI_FSYNC0

<5>

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

@
1 R153

DSWODVREN

R359 2
R368 1

*

1 330K_0402_5%
@

2 330K_0402_5%

DSWODVREN - On Die DSW VR Enable
H：
： Enable internal DSW +1.05VS
L：
： Disable
Must always PH at +RTCVCC

2 100K_0402_5%

1 R133
2
0_0402_5%

PCH_RSMRST#
2

WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
PWRBTN#

SLP_A#

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

RI#

DSWODVREN

<5>

SLP_LAN# / GPIO29

N3

CLKRUN#

G8

SUS_STAT#

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

SLP_A#

G16

SLP_SUS#

AP14

H_PM_SYNC

K14

PCH_GPIO29

PCH_PCIE_WAKE#

2 R423
1
8.2K_0402_5%
@
T1
PAD
SUSCLK

+3V_PCH

<33,40>
PCH_PCIE_WAKE#

2
1
10K_0402_5%

R374

PCH_GPIO29

@
2
1
10K_0402_5%

R36

+3VS

<42>

PM_SLP_S5#

<42>

PM_SLP_S4#

<42>

PM_SLP_S3#

<42>

@
T4
PAD

Can be left NC when IAMT is not
support on the platfrom
SLP_SUS#

<42>

H_PM_SYNC

<6>

No use ,PH 10K +3VALW

3

COUGARPOINT_FCBGA989

tell PCH all power ok
but cpu core

2
1

B

Y

SYS_PWROK

4

SYS_PWROK

<6>

3

1

A

G

PCH_PWROK

PCH_PWROK
1

<42>

ALL power OK
U36
MC74VHC1G08DFT2G_SC70-5

P

5

+3VS

R104
10K_0402_5%
2

2

R119
100K_0402_5%

4

<56>

1

2

@
C52
0.047U_0402_16V7K

VGATE

VGATE

4

2011/06/24

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/12

Deciphered Date

Title

PCH (3/9) DMI,FDI,PM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

16

of

58

C

D

E

U13D

EDID_DATA

R195 1

2 2.2K_0402_5%

CTRL_CLK

<35>

PCH_PWM

<35>
<35>

EDID_CLK
EDID_DATA

1

2 2.2K_0402_5%

CTRL_DATA

<35>
<35>

LVDS_ACLK#
LVDS_ACLK

<35>
<35>
<35>

LVDS_A0#
LVDS_A1#
LVDS_A2#

<35>
<35>
<35>

LVDS_A0
LVDS_A1
LVDS_A2

<35>
<35>

2

2 R192
1
150_0402_1%
2 R193
1
150_0402_1%
2 R194
1
150_0402_1%

LVDS_BCLK#
LVDS_BCLK

<35>
<35>
<35>

LVDS_B0#
LVDS_B1#
LVDS_B2#

<35>
<35>
<35>

LVDS_B0
LVDS_B1
LVDS_B2

<36>
<36>
<36>

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

L_BKLTEN
L_VDD_EN

PCH_PWM

P45

L_BKLTCTL

EDID_CLK
EDID_DATA

T40
K47

L_DDC_CLK
L_DDC_DATA

CTRL_CLK
CTRL_DATA

T45
P39

L_CTRL_CLK
L_CTRL_DATA

LVDS_IBG

AF37
AF36

LVD_IBG
LVD_VBG

AE48
AE47

LVD_VREFH
LVD_VREFL

LVDS_ACLK#
LVDS_ACLK

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDS_A0
LVDS_A1
LVDS_A2

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDS_BCLK#
LVDS_BCLK

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

LVDS_B0#
LVDS_B1#
LVDS_B2#

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDS_B0
LVDS_B1
LVDS_B2

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

PCH_CRT_R

<36> PCH_CRT_CLK
<36> PCH_CRT_DATA

+3VS

R190

1

2 2.2K_0402_5%

PCH_CRT_CLK

R191

1

2 2.2K_0402_5%

PCH_CRT_DATA

<36>
<36>

PCH_CRT_HSYNC
PCH_CRT_VSYNC

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

PCH_CRT_CLK
PCH_CRT_DATA

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

M47
M49

CRT_HSYNC
CRT_VSYNC

T43
T42

DAC_IREF
CRT_IRTN

3

1

CRT_IREF

SDVO_STALLN
SDVO_STALLP

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

+3VS

HDMI@
R144
2.2K_0402_5%

HDMI@
R131
2.2K_0402_5%

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

AT49
AT47
AT40

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

DDPC_CTRLCLK
DDPC_CTRLDATA

TMDS_B_HPD#
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH

HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

C406
C352
C539
C538
C535
C534
C537
C536

1
1
1
1
1
1
1
1

PCH_HDMICLK
PCH_HDMIDAT

<37>
<37>

TMDS_B_HPD#

<37>

2
2
2
2
2
2
2
2

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K

HDMI_TX2-_CK <37>
HDMI_TX2+_CK <37>
HDMI_TX1-_CK <37>
HDMI_TX1+_CK <37>
HDMI_TX0-_CK <37>
HDMI_TX0+_CK <37>
HDMI_CLK-_CK
<37>
HDMI_CLK+_CK <37>

HDMI D2
HDMI

HDMI D1
HDMI D0
HDMI CLK

Place close to Connector side(0210)

P46
P42

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

DDPD_CTRLCLK
DDPD_CTRLDATA

PCH_HDMICLK
PCH_HDMIDAT

P38
M39

2

M43
M36

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

3

COUGARPOINT_FCBGA989

2

R114
1K_0402_0.5%

AP43
AP45

1

PCH_CRT_B
PCH_CRT_G

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK
SDVO_CTRLDATA

CRT

R196 1

2 R132
1
2.37K_0402_1%

J47
M45

1

EDID_CLK

2 2.2K_0402_5%

PCH_ENBKL
PCH_ENVDD

2

2 2.2K_0402_5%

R105 1

PCH_ENBKL
PCH_ENVDD

Digital Display Interface

R108 1

<35>
<35>

LVDS

+3VS

1

B

2

A

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Classification
2011/06/24

Issued Date

Deciphered Date

2012/07/12

Title

PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

LA-8971P

Wednesday, February 15, 2012

Rev
0.1
Sheet

E

17

of

58

A

B

C

D

E

+3VS
R90
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#

R409

8.2K_1206_8P4R_5%
R395
8
7
6
5

PCH_GPIO51
PCH_GPIO2
PCH_ODD_DA#

1
2
3
4

8.2K_1206_8P4R_5%
1 R401
2
8.2K_0402_5%

DGPU_PWR_EN2

1 R410
2
8.2K_0402_5%

DGPU_PWR_EN1

+3VS
1 R66
2
8.2K_0402_5%

USB3.0

<45>

USB3_RX1_N

<45>

USB3_RX1_P

<45>

USB3_TX1_N

<45>

USB3_TX1_P

USB3_RX1_N

DGPU_HOLD_RST#

@
2
1 R41
8.2K_0402_5%

USB3_RX1_P

USB3_TX1_N

2

Boot BIOS Strap

GNT1#/
GPIO51

GPIO19 GPIO51 Boot BIOS
Bit10 Destination

USB3_TX1_P

Bit11

Internal
PH

0

1

TP21
TP22
TP23
TP24

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

0

PCI

1

1

SPI

0

0

LPC

*
<55>
<15,30,55>

DGPU_PWR_EN2

R56 2 OPT@
R57 2 OPT@

NVDD_PWR_EN
DGPU_PWR_EN

@
R25 1 PCH_WL_OFF#
2
1K_0402_5%

1 0_0402_5%
1 0_0402_5%

<40>

PCH_WL_OFF#

<39>

PCH_ODD_DA#

<42>

3

<6>
CLK_PCI_LPBACK
CLK_PCI_EC
CLK_PCI_DB

CLK_PCI_LPBACK
<42> CLK_PCI_EC
<40> CLK_PCI_DB

PCI_PME#

PCH_PLTRST#

R417 1
R84 1
R162 1

@

1

<15>

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI Interrupt Requests

@
R307
10K_0402_5%

DGPU_HOLD_RST#
DGPU_PWR_EN1
DGPU_PWR_EN2

C46
C44
E40

PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#

D47
E42
F46

PCH_GPIO2
PCH_ODD_DA#
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44

PCI_PME#
PCH_PLTRST#

2 22_0402_5%
2 22_0402_5%
2 22_0402_5%

CLK_PCI0
CLK_PCI1
CLK_PCI2

K10
C6
H49
H43
J48
K42
H40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AT10
BC8

NV_RCOMP

AV5
AY1

NV_RB#

AT8
AY5
BA2

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

DF_TVS

HR CPU NC
CR CPU PD

1

CR Check list P.89 PH 2.2K series 1K
+1.8VS

R145
2.2K_0402_5%

USBRBIAS#
USBRBIAS

DF_TVS

DF_TVS

2 R146
1
1K_0402_5%

H_SNB_IVB#

<6>

CLOSE TO THE BRANCHING POINT

AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_N0
USB20_P0
USB20_N1
USB20_P1

C33

USBRBIAS

USB20_N3
USB20_P3

USB20_N0
USB20_P0
USB20_N1
USB20_P1

<45>
<45>
<46>
<46>

USB20_N3
USB20_P3

<46>
<46>

USB3 (Left side)
2

USB2 (Right side)
USB2 (Right side)

EHCI 1

HM70 not support USB port 4,5,6,7,12,13
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

1 R399
2
22.6_0402_1%

<35>
<35>
<43>
<43>
<40>
<40>
<46>
<46>

CMOS Camera (LVDS)
Bluetooth
Mini Card (WLAN)
Card Reader

EHCI 2

L=500mil S=15mil

B33

PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

3

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#

<45,46>
<46>
+3V_PCH

USB_OC0#

2 R24
1
10K_0402_5%

USB_OC7#

2 R367
1
10K_0402_5%

USB_OC5#

2 R378
1
10K_0402_5%

USB_OC6#

2 R377
1
10K_0402_5%

COUGARPOINT_FCBGA989
1

2

R10 1
2
0_0402_5%

Set to Vcc when HIGH
Set to Vss when LOW

AV10

NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

DMI,FDI Termination Voltage

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

2

@
C149
0.1U_0402_16V4Z

K40
K38
H38
G38

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

Reserved

1

@
NVDD_PWR_EN 2 R218
1
0_0402_5%

B21
M20
AY16
BG46

AY7
AV7
AU3
BG4

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

USB

1

PCH_WL_OFF#
PCH_GPIO53
PCH_GPIO4
PCH_GPIO5

1
2
3
4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

1

8.2K_1206_8P4R_5%

8
7
6
5

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

2

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

NVRAM

U13E

RSVD

1
2
3
4

PCI

8
7
6
5

+3VS
+3V_PCH
5

RP3

B

Y

4

PLT_RST#

+3VS

R11
100K_0402_5%

5
6
7
8
10K_1206_8P4R_5%

4

2

B

1

A

R6
1
2 OPT@
100_0402_5%

DGPU_RST#

<23>

OPT@
R3
100K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

G

4

2011/06/24

2012/07/12

Deciphered Date

Title

Date:

A

PCH (5/9) PCI, USB, NVRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

OPT@
U29
MC74VHC1G08DFT2G_SC70-5

Y
3

DGPU_HOLD_RST#

P

5

4

<33,40,42>

1
U25 @
MC74VHC1G08DFT2G_SC70-5

4
3
2
1

2

A

3

1

USB_OC1#
USB_OC4#
USB_OC3#
USB_OC2#

P

2

G

PCH_PLTRST#

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

18

of

58

D

GPIO70
1

PCH_GPIO28

@
R68
10K_0402_5%

1

PCH_GPIO71

1

PCH_GPIO70

R42
10K_0402_5%

@
R44
10K_0402_5%

R43
10K_0402_5%

1

2 10K_0402_5%

PCH_GPIO0

T7

1 R402

2 10K_0402_5%

PCH_GPIO1

A42

1 R70

<42>

BT ON/OFF

<40,43>

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

PCH_GPIO71

<42>

EC_SMI#

EC_SMI#

C10

GPIO8

2 10K_0402_5%

PCH_GPIO12

C4

LAN_PHY_PWR_CTRL / GPIO12

PCH_GPIO15

G2

GPIO15

mSATA_DET#

DGPU_PWROK
BT_DISABLE
2 10K_0402_5%

EC_LID_OUT#

PCH_BT_ON#
R97 1
2
10K_0402_5%

+3VS
+3VS

ODD_DETECT#

1

<39>
1 R439
2 ODD_DETECT#
200K_0402_5%

@
R55
10K_0402_5%

R94
10K_0402_5%

DGPU_PWROK

U2
D40
T5

SCLOCK / GPIO22

PCH_GPIO24

E8

GPIO24 / MEM_LED

EC_LID_OUT#

E16

GPIO27

PCH_GPIO28

P8

GPIO28

K1

STP_PCI# / GPIO34

PCH_GPIO35

K4

GPIO35

ODD_DETECT#

V8

PCH_GPIO37

M5

PCH_GPIO38

N2

R221 2 10K_0402_5%

PCH_GPIO39

M3

1

R128 2 10K_0402_5%

PCH_GPIO48

V13

1

R111 2 10K_0402_5%

PCH_GPIO49

V3

+3V_PCH

1

R52

PCH_GPIO57

D6

P4

GATEA20

GATEA20

AU16

PCH_PECI_R

P5

KBRST#

PROCPWRGD

AY11

H_CPUPWRGD

THRMTRIP#

AY10

PCH_THRMTRIP#_R

PECI
RCIN#

INIT3_3V#

T14

NC_1

AH8

NC_2

AK11

NC_3

AH10

+3VS

@
1
2 R158
0_0402_5%

SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5

H_PECI

KBRST#

R159 1
2
390_0402_5%

ODD_EN#

2 R103

1 10K_0402_5%

KBRST#

2 R400

1 10K_0402_5%

<42>
H_PECI

<6,42>

CTRL+ALT+DEL

<42>

H_CPUPWRGD

INIT3_3V

PCH_BT_ON#

+3VS

non CPU power ok

<6>

H_THERMTRIP#

H_THERMTRIP#

<6>

130c shut down

Checklist1.5 P.69

2

This signal has weak internal
PU, can't pull low,leave NC

AK10
P37

SLOAD / GPIO38
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17
VSS_NCTF_18

A4
A44
A45
A46
A5

3

A6

+3VS

B3
R115 1

2 10K_0402_5%

mSATA_DET#

B47

R71

1

2 10K_0402_5%

DGPU_PWROK

BD1

R416 1

2 10K_0402_5%

PCH_BT_ON#

R220 1

2 10K_0402_5%

BT_DISABLE

BD49
BE1
BE49
BF1

+3V_PCH

BF49
2 1K_0402_5%

TACH0 / GPIO17

BT_DISABLE

1

2 10K_0402_5%

SATA4GP / GPIO16

PCH_GPIO15

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

NCTF

SATA2GP/GPIO36 & SATA3GP/GPIO37
Sampled at Rising edge of PWROK.
Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled

PCH_GPIO37

mSATA_DET#

+3VS

2 R106
1
10K_0402_5%
A20GATE

<39>

BG2
BG48
BH3

2

EC_SMI#

R261 1
@
2
1K_0402_5%

1

2

+3V_PCH

ODD_EN#

H36

EC_LID_OUT#

@
2
1
10K_0402_5%

PCH_GPIO69

EC_SCI#

1 R92

2

ODD_EN#

B41

PCH_GPIO6

<40>
+3V_PCH

C40

EC_SCI#

<40>
<30,55>

TACH5 / GPIO69

2 10K_0402_5%

1 R376

+3V_PCH

TACH4 / GPIO68

TACH1 / GPIO1

<42>

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal

BMBUSY# / GPIO0

CPU/MISC

2

1 R112

GPIO

1

U13F
+3VS

@
R413
1K_0402_5%

R412 1

R69
10K_0402_5%

2

1
2

R411
4.7K_0402_5%

R83

@
R67
10K_0402_5%
PCH_GPIO69

+3V_PCH
1

1

H：
： On-Die PLL voltage regulator enable
L：
： On-Die PLL Voltage Regulator disable

1

*

2

This signal has a weak internal pull up

+3VS

2

On-Die PLL Voltage Regulator

+3VS
1

+3VS

2

Project ID
* U510

GPIO28

E

2

C

1

B

2

A

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BH47
BJ4
BJ44
BJ45
BJ46
BJ5

3

BJ6
C2
C48
D1
D49
E1
E49
F1
F49

COUGARPOINT_FCBGA989

+3VS

R427 1 UMA@ 2 10K_0402_5%
R426 2 OPT@

4

PCH_GPIO38

1 10K_0402_5%

4

PCH_GPIO38

*

OPT
UMA

0
1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

2012/07/12

Deciphered Date

Title

PCH (6/9) GPIO, CPU, MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

19

of

58

A

B

C

D

E

Thermal Senser share with VCCADAC power rail
so can't remove this power

+1.05VS_VTT

1
C75

2

1U_0402_6.3V6K

1
C67

2

1U_0402_6.3V6K

2

C64

C106

1

1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

2

Place Near AA23

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

POWER
CRT

1300mA

VCCADAC
VSSADAC

U47

1

C53
0.01U_0402_16V7K

2

1

C54
0.1U_0402_16V7K

2

2

VCCALVDS
VSSALVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]

AK36 +VCCA_LVDS

R442 1
2
0_0805_5%

+3VS

AK37
AM37
AM38

60mA VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

Place Near AM37
1

VCCIO[28]

1

C91
0.01U_0402_16V7K

2

VCCIO[15]

H：
： On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

AN17

VCCIO[16]

C86

2

1

2

1U_0402_6.3V6K

C90

2

1

1U_0402_6.3V6K

C88

C87

2

1

1U_0402_6.3V6K

1

1U_0402_6.3V6K

C80

2

10U_0603_6.3V6M

1

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24
AN33

Place Near AN16,AN21,AN33

AN34

+3VS

BH29

Place Near
BH29

1

C107
0.1U_0402_16V7K

AP16
@
T17

+1.05VS_VCCAPLL_FDI

BG6

AU20
1

2

C108
22U_0805_6.3V6M

VCC3_3[7]

V34

1

C61
0.1U_0402_16V7K

2

I/O Buffer Voltage

Place Near V33
PCH Power Rail Table

AT16

Internal PLL and VRM(+1.5VS)

+1.05VS_VTT
VCCDMI[1]

20mA

VCCIO[1]

AT20
1
AB36

DMI buffer logic

C96
1U_0402_6.3V6K

place
near AT20

2

Core Well I/O Buffer

190mA

VCCIO[25]
VCCIO[26]

VCCPNAND[1]

VCC3_3[3]

VCCVRM[2]
VCCFDIPLL
VCCIO[27]
VCCDMI[2]

0.1uH inductor, 200mA

2

VCCPNAND[2]
VCCPNAND[3]

AG16

+1.8VS

AG17
1
AJ16
2

VCCPNAND[4]

VccDFTERM should PH +1.8VS or +3VS

AJ17

C81
0.1U_0402_16V7K

place
near AG16

+3VS

On-Die PLL Voltage Regulator
H：
： On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

V33

+1.05VS_VTT
AP17

3

2

1

+1.5VS

+1.5VS

2

PAD

VCCIO[24]

VCC3_3[6]

VCCVRM[3]

DMI

2

2925mA

AN21

NAND / SPI

+1.05VS_VTT

HVCMOS

AN16

C92
0.01U_0402_16V7K

+1.8VS
L27
+VCCTX_LVDS
2
1
0.1UH_MLF1608DR10KT_10%_1608

+3VS

266mA

VCCAPLLEXP

On-Die PLL Voltage Regulator

VCCIO

+VCCAPLLEXP BJ22

T31 @

FDI

PAD

L16
2
1
MBK1608221YZF_2P
1
C40
10U_0603_6.3V6M

Place Near U48

+VCCADAC

1mA

1mA

+1.05VS_VTT
AN19

+3VS
U48

1

LVDS

U13G

VCC CORE

+1.05VS_VTT

20mA

C98
COUGARPOINT_FCBGA989
1U_0402_6.3V6K

VCCSPI

For SPI control logi

V1
1

C60
1U_0402_6.3V6K

Voltage Rail

Voltage

S0 Iccmax
Current(A)

V_PROC_IO

1.05

0.001

Processor I/F

V5REF

5

0.001

PCH Core Well Reference Voltage

V5REF_Sus

5

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.266

I/O Buffer Voltage

VccADAC

3.3

0.001

Display DAC Analog Power. This power is
supplied by the core well.

VccADPLLA

1.05

0.08

Display PLL A power

VccADPLLB

1.05

0.08

Display PLL B power

VccCore

1.05

1.3

Internal Logic Voltage

2

VccDMI

1.05

0.042

DMI Buffer Voltage

VccIO

1.05

2.925

Core Well I/O buffers

VccASW

1.05

1.01

1.05 V Supply for Intel R Management
Engine and Integrated LAN

VccSPI

3.3

0.02

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

VccSus3_3

3.3

0.266

Suspend Well I/O Buffer Voltage

2

3

Near
AU20

Trace 20mil

4

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

High Definition Audio Controller Suspend
Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)

VccCLKDMI

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile
Only)
Analog power supply for LVDS (Mobile
Only)

2011/06/24

2012/07/12

Deciphered Date

Title

PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VccSusHDA

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

20

of

58

A

B

C

D

E

+5VALW

1
1

2

1
C66

2

2

C104
1U_0402_6.3V6K

C73

+ C112
220U_6.3V_M
SF000002Y00

2

C56

1

1

2

2

1U_0402_6.3V6K

+1.05VS_VCCA_B_DPL

1
2
10UH_LB2012T100MR_20%

1U_0402_6.3V6K

1

L26

1U_0402_6.3V6K

2

1

2

Near BD47

1
C110

C113

2

C103
1U_0402_6.3V6K

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS_VCCA_A_DPL

1
2
10UH_LB2012T100MR_20%

Near AA19

Near BF47

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]
VCCASW[10]
VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

VCCASW[18]

W31

VCCASW[19]

+1.05VS_VCCA_B_DPL

+1.05VS_VTT

VCCVRM[4]

Place
near AG33

2

C72
1U_0402_6.3V6K

Place
near AF33,
AF34,AG34

+1.05VS_VTT

1

Place
near AG33

C74
1U_0402_6.3V6K

Near V16
PAD

C57 2

+VCCSST

1

0.1U_0402_16V7K
+1.05VM_VCCSUS
T13 @

55mA

VCCIO[10]

V16

DCPSST

T17
V19

DCPSUS[1]
DCPSUS[2]

1

2

1
C453

C450

2

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

suppied by internal
1.05V VR Must NC

+3V_PCH

+3VS

+5VS

D29
RB751V-40_SOD323-2

+PCH_V5REF_RUN
C42
1U_0603_10V6K

+3V_PCH

1

2

1

Near P34

Near N20
+3VALW

+3VS

VCC3_3[1]

AA16

VCC3_3[8]

W16

VCC3_3[4]

T34

2

+3V_PCH
J20 @

1

2

AJ2

C471
0.1U_0402_16V7K

Place near
AJ2

1

2

C65
0.1U_0402_16V7K

Place near
AA16,W16

1

2

2
C49
0.1U_0402_16V7K

AF13

VCCIO[12]

AH13

95mA

VCCIO[6]
VCCAPLLSATA

2MM

Place near
T34

3

Near AH13,AH14,AF13
1

C76
1U_0402_6.3V6K

AH14

DSP3@
C434

AF14
+VCCSATAPLL

AK1

1 DSP3@ 2 R711
0_0402_5%

DSP3@
C5242

1

2

GPIO28
@ T29

VCCVRM[1]

AF11

+1.5VS

VCCIO[2]

AC16

+1.05VS_VTT

VCCIO[3]

AC17

VCCIO[4]

AD17

3

On-Die PLL Voltage Regulator

PAD

H：
：On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
+5VALW

1

C68
1U_0402_6.3V6K

2
+1.05VS_VTT

DSP3@
R279
100K_0402_1%

Near AC16

1mA

V_PROC_IO

VCCASW[22]

T21

VCCASW[23]

V21

VCCASW[21]

T19

10mAVCCSUSHDA

P32

PCH_PWR_EN#

<42>

A22

VCCRTC

COUGARPOINT_FCBGA989

1

PCH_PWR_EN

PCH_PWR_EN

D

S

2
G

DSP3@
Q13
2N7002_SOT23

C41
0.1U_0402_16V4Z
4

2

Near P32

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

Deciphered Date

2012/07/12

Title

PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

1

DSP3@
C5104
0.1U_0402_10V7K

2

Near A22

A

1

+1.05VS_VTT

VCCIO[5]

1

R130
100_0402_5%

2

C38
1U_0402_6.3V6K

2

1

R364
100_0402_5%

1
2
C37
0.1U_0402_16V7K

@
T16
PAD

2

2

D23
RB751V-40_SOD323-2

+3V_PCH

0.1U_0402_16V7K

1
C445

Place
near BJ8

VCCSUS3_3[2]

+RTCVCC

0.1U_0402_16V7K

2

BJ8

1U_0402_6.3V6K

C111

C109

2

1

0.1U_0402_16V7K

1

0.1U_0402_16V7K

C114

2

4.7U_0603_6.3V6K

isolation between SSC (AG33)
and DIFFCLKN(AF33,AF34,AG34)
18mil width(DIFFCLKN)
10mil (SSC)

VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]

80mA
80mA

+1.05VS_VTT

1

4

VCCADPLLB

AF17
AF33
AF34
AG34
AG33

2

suppied by internal
1.05V VR Must NC

BF47

+5V_PCH

2

2

1

P34

VCCIO[13]

VCCADPLLA

+3V_PCH

+1.05VS_VTT

Near M26

V5REF

DCPRTC

HDA

Place
near AF17

C79
1U_0402_6.3V6K

AN24

VCCASW[20]

CPU

2

1

C77
1U_0402_6.3V6K

VCCSUS3_3[1]

Near T24

PCH_PWR_EN#

RTC

1

+VCCA_USBSUS

VCC3_3[2]

SATA

BD47

AN23

C45
0.1U_0402_16V7K

2

Q29
AO3413_SOT23-3

MISC

+1.05VS_VCCA_A_DPL

DCPSUS[4]

2

1U_0402_6.3V6K

VCCASW[17]

W29

3

+1.05VS_VTT

+PCH_V5REF_SUS

Near T23

10U_0603_6.3V6M

W26

Y49

V5REF_SUS

M26

1mA

0.1U_0402_16V7K
+1.5VS

T26

1mA

AC31

N16

VCCIO[34]

1

C46
0.1U_0402_16V7K

G

+VCCRTCEXT

1

VCCSUS3_3[6]

P24

1

D

2

VCCSUS3_3[10]

V24

1010mA

AC29

Near M6
C39

DCPSUS[3]

AA19

W33

V23

S

SGA20331E10
330U 2V H1.9
9mohm POLY

T24

VCCSUS3_3[9]

1

L25

VCCSUS3_3[8]

119mA

1

2

+3V_PCH

1

VCCIO[14]

DSP3@
C5245

2

VCCAPLLDMI2

AL29

+1.05VS_VTT

T23

3

+1.05VS_VTT

VCCSUS3_3[7]

1

1

BH23

AL24

T29

DSP3@
C435

2

+VCCAPLL_CPY_PCH

+VCCSUS1

VCCIO[33]

2

VCC3_3[5]

Near N26

1 DSP3@ 2 R710
0_0402_5%
DSP3@
C5103
0.1U_0402_10V7K

1

T38

@
T15
PAD

T27

PCH_PWR_EN#

1

+3VS_VCC_CLKF33

+1.05VS_VTT

VCCIO[32]

3mA

C51
1U_0402_6.3V6K

2

2

H：
：On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

P28

2

T30 @

P26

VCCIO[31]

1

PAD

1

1

DCPSUSBYP

USB

V12

GPIO28
On-Die PLL Voltage Regulator

3

2

+PCH_VCCDSW
T14
PAD @

VCCIO[30]
VCCDSW3_3

1

2

T16

N26

1

2

Clock and Miscellaneous

C47
0.1U_0402_16V7K

suppied by internal
1.05V VR must NC

+1.05VS_VTT

VCCIO[29]

VCCACLK

1U_0402_6.3V6K

AD49
2

POWER

U13J

1

10U_0603_6.3V6M

Near T38

1

G

2
1

+VCCDSW3_3

1 R407
2
0_0402_5%

+3VALW
C55
1U_0402_6.3V6K

2

+3VS_VCC_CLKF33

1

1

2MM
Q39
AO3413_SOT23-3

+VCCACLK

D

C71
10U_0603_6.3V6M

R450 1
@
2
0_0402_5%

S

L23
1
2
10UH_LB2012T100MR_20%

2

+1.05VS_VTT

PCI/GPIO/LPC

+3VS

+5V_PCH
J21 @

+1.05V analog
internal clock PLL
Can NC

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012
E

Sheet

21

of

58

A

B

C

D

E

U13I

1

U13H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

2

3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

COUGARPOINT_FCBGA989


AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

1

2

3

4

4

COUGARPOINT_FCBGA989


Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/24

2012/07/12

Deciphered Date

Title

PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

22

of

58

A

B

C

D

E

N13M-GS VID Default setup is 0.875V
U48A
Part 1 of 5

CLK_PCIE_VGA
CLK_PCIE_VGA#

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
R225

@

200_0402_1%
R226 OPT@
2.49K_0402_1%

3

<18>
<15>

PEG_CLKREQ#

DGPU_RST#

PEG_CLKREQ#

OPT@ R227
0_0402_5%

+3VSDGPU

AE8
AD8

PEX_TSTCLK_OUT+
PEX_TSTCLK_OUT-

AF22
AE22

PEX_TREMP

AF25

DGPU_RST#

AC7

PEG_CLKREQ#_C

AC6

OPT@
R228
10K_0402_5%

AE3
AE4

DACA_RED
DACA_BLUE
DACA_GREEN

AG3
AF3
AF4

DACA_VREF
DACA_RSET

AE2
AF2

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AE5
AE6
AF6
AD6
AG4

TESTMODE

AD9

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA

XTAL_SSIN
XTAL_OUTBUFF

PEX_REFCLK
PEX_REFCLK_N

XTAL_OUT
XTAL_IN

@

10K_0402_5%

10K_0402_5%
OPT@
R243
10K_0402_5%
OPT@
R244
10K_0402_5%

R241

R253

R252

@

<55>
<55>
<55>
<55>
<55>
<55>

@

2 10K_0402_5%
@ T19
@ T10
@ T12
@ T5

R235 1 OPT@
R234 1 OPT@

I2CA_SCL
I2CA_SDA

R236 1

R242

10K_0402_5%
OPT@
10K_0402_5%

GPU_VID0
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
GPU_VID5

@

DACA_HSYNC
DACA_VSYNC

R240

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

10K_0402_5%

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

10K_0402_5%

R45
R98
R135
R222
R223
R224

@

R246
OPT@
10K_0402_5%
R250
OPT@
10K_0402_5%
R251

10K_0402_5%
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5

@

10K_0402_5%

OPT@
R284

@

OPT@
R245

VID_0
ACIN_BUF
VID_5

1 2.2K_0402_5%
1 2.2K_0402_5%

R239

+3VSDGPU

R280 2 OPT@
R283 2 OPT@

10K_0402_5%

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

VID_1
VID_2

PAD
PAD
PAD
PAD

2 10K_0402_5%

B7
A7
C9
C8
A9
B9

VGA_LCD_CLK
VGA_LCD_DATA

D9
D8

I2CS_SCL
I2CS_SDA

A10

OPT@
D8
<42>

I/O

USAGE

GPIO0

O

GPIO1

O

GPU Core VID3

GPIO2

O

LCD_BL_PWM

GPIO3

O

LCD_VCC

GPIO4

O

LCD_BLEN

GPIO5

O

GPU Core VID1

GPIO6

O

GPU Core VID2

GPU Core VID4

GPIO7

O

3D Vision

GPIO8

I/O

OVERT

GPIO9

I/O

ALERT

1

GPIO10 O

MEM_VREF_CTL

GPIO11 O

GPU Core VID0

GPIO12 I

PWR_LEVEL

GPIO13 O

GPU Core VID5

GPIO14 I

HPD_AB

GPIO15 I

HPD_C

GPIO16 O

MEM_VDD_CTL

GPIO17 I

HPD_D

GPIO18 I

HPD_E

GPIO19 I

HPD_F

GPIO20

Reserved

GPIO21

Reserved

2

2 10K_0402_5%

ACIN_BUF

ACIN_BUF

2

ACIN

1

ACIN

<16,42,50>

CH751H-40PT_SOD323-2

XTAL_SSIN

C10 XTAL_OUTBUFF
B10

XTALOUT

C11

XTALIN

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_TERMP

PEX_WAKE_N

PEX_RST_N

PGOOD

PEX_CLKREQ_N

CEC

AB6
3

D10
R232

E9

@
10K_0402_5%

+3VSDGPU

+3VSDGPU
OPT@
R233
10K_0402_1%

N13P-GV-S_FCBGA595~D
2

2

AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25

VID_4
VID_3

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

GPIO

1

PEG_GTX_HRX_P15
PEG_GTX_HRX_N15
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_HRX_P12
PEG_GTX_HRX_N12
PEG_GTX_HRX_P11
PEG_GTX_HRX_N11
PEG_GTX_HRX_P10
PEG_GTX_HRX_N10
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
PEG_GTX_HRX_P8
PEG_GTX_HRX_N8

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

GPIO

PEG_HTX_C_GRX_N[8..15]

DACA

PEG_HTX_C_GRX_N[8..15]

PEG_HTX_C_GRX_P[8..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

TEST

<5>

PEG_HTX_C_GRX_P[8..15]

PEG_GTX_HRX_N[8..15]

AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22

I2C

<5>
1

PEG_GTX_HRX_N[8..15]

PEG_GTX_HRX_P[8..15]

+3VSDGPU

CLK

<5>

PEG_GTX_HRX_P[8..15]

PCI EXPRESS

<5>

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8

XTALOUT

VGA_LCD_CLK R258 1 OPT@
VGA_LCD_DATA R259 1 OPT@

2 2.2K_0402_5%
2 2.2K_0402_5%

I2CS_SCL
I2CS_SDA

2 2.2K_0402_5%
2 2.2K_0402_5%

R260 1 OPT@
R262 1 OPT@

XTALIN

@
R229
1M_0402_5%
Y1000 OPT@
27MHZ 10PF 7V27000050

OPT@
C124
18P_0402_50V8J

3

1
GND

GND

4

2

+3VSDGPU

1
1

2

2

2

3
1

OPT@
C125
18P_0402_50V8J

I2CS_SCL

OPT@
QV6A

1

6

EC_SMB_CK2

<15,42,44>

EC_SMB_DA2

<15,42,44>

DMN66D0LDW-7_SOT363-6

+3VSDGPU
5

OPT@
R231
10K_0402_5%

I2CS_SDA

4

Issued Date

2011/05/23

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

4

3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

A

OPT@
QV6B

2

2

OPT@
R230
10K_0402_5%

1

XTAL_OUTBUFF
1

XTAL_SSIN
4

C

D

N13M-GS 1/7
Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
E

23

of

58

A

U48B

CMDA[30..0]

MDA[15..0]

<28>

MDA[31..16]

<29>

MDA[47..32]

<29>

MDA[63..48]

MDA[15..0]
MDA[31..16]
MDA[47..32]
MDA[63..48]

1

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
@ PAD

<28> CLKA0
<28> CLKA0#
<29> CLKA1
<29> CLKA1#

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
T11

D23

CLKA0
CLKA0#

D24
D25

CLKA1
CLKA1#

N22
M22

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE

Part 2 of 5
<28>

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FB_VREF_PROBE
FBA_WCK45
FBA_WCK45_N
FBA_CLK0
FBA_WCK67
FBA_CLK0_N
FBA_WCK67_N
FBA_CLK1
FBA_CLK1_N

FBA_DEBUG0
FBA_DEBUG1

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

<28,29>

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

D19
D14
C17
C22
P24
W24
AA25
U25
F19
C14
A16
A22
P25
W22
AB27
T27

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

E19
C15
B16
B22
R25
W23
AB26
T26

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

DQMA[3..0]

<28>

DQMA[7..4]

<29>

DQSA#[3..0]

<28>

DQSA#[7..4]

<29>

DQSA[3..0]

<28>

DQSA[7..4]

<29>

1

D18
C18
D17
D16
T24
U24
V24
V25
+1.5VSDGPU
F22
J22

FBA_DEBUG0 RV57
FBA_DEBUG1 RV59

@
@

60.4_0402_1%
60.4_0402_1%

N13P-GV-S_FCBGA595~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

Deciphered Date

2012/12/31

Title

N13M-GS 2/7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet

24

of

58

5

4

3

2

1

U48C
Part 3 of 5

B

H3
H4
M4
M5
L3
L4
K4
K5
J4
J5

D11

THERMDN
THERMDP

E12
F12

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

@
1 R1080 2
10K_0402_5%

+3VSDGPU
1 OPT@ 2 R1064
10K_0402_5%

C12 ROM_SCLK

ROM_SI

B12

ROM_SI

ROM_SO

A12

ROM_SO

IFPAB_RSET

AA6

R1081 1

@

2 1K_0402_1%

IFPC_RSET

T6

R1082 1

@

2 1K_0402_1%

IFPD_RSET

U6

R1084 1

@

2 1K_0402_1%

K6

R1083 1

@

2 1K_0402_1%

NC_W1
NC_W2
NC_W3
NC_W4

VMON_IN0
VMON_IN1

STRAP0
STRAP1
STRAP2

G1
G2
G3
G4
G5
G6
G7

@

@

2 R1113 1
10K_0402_1%

@

2 R1119 1
10K_0402_1%

@

2 R1114 1
10K_0402_1%

@

2 R1075 1
10K_0402_1%

AD10
AD7
B19

2 R1079 1
10K_0402_1%

C

ROM_SI
STRAP3
STRAP4

ROM_SO

2 R1118 1
10K_0402_1%

@

2 R1132 1
10K_0402_1%

V1
V2
V5
V6

2 R1116 1
10K_0402_1%

ROM_SCLK
2 R1077 1
10K_0402_1%

NC_V1
NC_V2
NC_V5
NC_V6

+3VSDGPU

2 R1076 1
10K_0402_1%

NC_G1
NC_G2
NC_G3
NC_G4
NC_G5
NC_G6
NC_G7

+3VSDGPU

2 R1072 1
10K_0402_1%

NC
NC
NC

Straps

X76@
2 R1071 1
10K_0402_1%

ROM_SCLK

D12 ROM_CS#

X76@
2 R1070 1
10K_0402_1%

STRAP

ROM_CS_N

2 R1074 1
10K_0402_1%

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

D

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

X76@
R1073 1

J2
J3
N1
M1
M2
M3
K2
K3
K1
J1

BUFRST_N

IFPEF_RSET
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

D1
D2
E4
E3
D3
C1

10K_0402_1%
X76@
2 R1078 1
10K_0402_1%

P3
P4
V3
V4
U3
U4
T4
T5
R4
R5

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

2

C

N4
N5
T2
T3
T1
R1
R2
R3
N2
N3

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

GENERAL

AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

SERIAL

AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5

LVDS / TMDS

D

W1
W2
W3
W4

B

E10
F10

For N13M-GS strap table

N13P-GV-S_FCBGA595~D
GPU

Memory Size

Memory Config

strap0

strap1

strap2

strap3

strap4

ROM_SI

ROM_SO

ROM_SCLK

900 MHz

128M* 16* 4
1GB

Hynix
SA00003YO00

R1073
PD 10K

R1071
PU 10K

R1072
PU 10K

R1076
PD 10K

R1077
PD 10K

R1132
PD 10K

R1116
PD 10K

R1118
PD 10K

900 MHz

128M* 16* 4
1GB

Samsung
SA000047Q00

R1070
PU 10K

R1078
PD 10K

R1072
PU 10K

R1076
PD 10K

R1077
PD 10K

R1132
PD 10K

R1116
PD 10K

R1118
PD 10K

Frenq.

N13P-GS
900 MHz
900 MHz

SA000047Q00:S IC D3 128M16 K4W2G1646C-HC11 FBGA 96P
SA00003YO00:S IC D3 128MX16 H5TQ2G63BFR-11C FBGA 96P
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

N13M-GS 3/7
Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

25

of

58

5

4

3

2

1

+1.5VSDGPU
U48D
OPT@
C1115

C1116

10U_0603_6.3V6M

OPT@

10U_0603_6.3V6M

OPT@
C1042

C1068

4.7U_0603_6.3V6K

OPT@

0.1U_0402_16V4Z

OPT@
C1043

C1050

0.1U_0402_16V4Z

OPT@

0.1U_0402_16V4Z

OPT@
C1065

C1067

0.1U_0402_16V4Z

OPT@

1U_0402_6.3V6K

OPT@

22U_0805_6.3V6M

OPT@

C1036

C1031

C1030

22U_0805_6.3V6M

OPT@

10U_0603_6.3V6M

C1035

C1029

10U_0603_6.3V6M

OPT@

OPT@

4.7U_0603_6.3V6K

1U_0402_6.3V6K

OPT@
C1034

OPT@
C1028

1U_0402_6.3V6K

2

1

2

C

+1.05VSDGPU

AA8
AA9

OPT@

2

22U_0805_6.3V6M

2

1

C1022

2

1

C1021

1

22U_0805_6.3V6M

OPT@

OPT@

OPT@

2

10U_0603_6.3V6M

2

1

C1020

2

1

10U_0603_6.3V6M

2

1

C1019

1

Near GPU
4.7U_0603_6.3V6K

Under GPU

AA22
AB23
AC24
AD25
AE26
AE27

PEX_3V3
+1.05VSDGPU

D22

R1139 1 OPT@

2 40.2_0402_1%

2

2

1

2

B

+1.5VSDGPU

under GPU
close to ball :
N6,M6

F3

16 mils

+IFPC_IOVDD

10K_0402_5% 2

@

1 R1087

+IFPEF_IOVDD

C1003

2

2

OPT@

+IFPEF_PLLVDD

1

1

C1120

1 R1094

OPT@

OPT@

+FBA_PLLVDD
OPT@

@

2

A

1

+1.05VSDGPU
OPT@

C1119

10K_0402_5% 2

1

OPT@

+IFPD_IOVDD

C158

+IFPD_PLLVDD

1 R1092

22U_0805_6.3VAM~D

1 R1091

@

OPT@

@

10K_0402_5% 2

0.1U_0402_16V4Z

10K_0402_5% 2

+1.05VSDGPU
OPT@
L1005
2
1
BLM18PG300SN1D_2P
22U_0805_6.3VAM~D

Under GPU Near GPU

16 mils

+CORE_PLLVDD

2

2

1

2

1

2

1

2

2
1 L1004
BLM18PG181SN1D_2P

1

2

1U_0402_6.3V6K

+IFPC_PLLVDD

1 R1088

C144

1 R1086

@

2

4.7U_0603_6.3V6K

@

10K_0402_5% 2

2

OPT@

10K_0402_5% 2

2

C142

+IFPAB_IOVDD

1

OPT@

1 R1131

1

C141

@

1

OPT@

2
1 L1003
BLM18PG181SN1D_2P

1U_0402_6.3V6K

10K_0402_5% 2

N13P-GV-S_FCBGA595~D

C143

+IFPAB_PLLVDD

OPT@

1 R1130

C1001

@

22U_0805_6.3VAM~D

OPT@

1

2
10K_0402_5% 2

+1.05VSDGPU

Near GPU

+GPU_PLLVDD

OPT@
R669
10K_0402_5%

C1122

FB_CLAMP

2 10K_0402_5%

+FBA_PLLVDD

1

0.1U_0402_16V4Z

FB_CAL_PD_VDDQ

IFPEF_PLLVDD
IFPEF_PLLVDD

W5

R1133 1 OPT@

1

OPT@
2 R449
1
0_0805_5%

OPT@

DACA_VDD
IFPD_PLLVDD
IFPD_PLLVDD

+GPU_PLLVDD
+CORE_PLLVDD

Near GPU

0.1U_0402_16V4Z

IFPC_PLLVDD
IFPC_PLLVDD

Under GPU

16 mils

C1002

IFPAB_PLLVDD
IFPAB_PLLVDD

PEX_PLLVDD
PEX_PLLVDD
VID_PLLVDD
SP_PLLVDD
CORE_PLLVDD
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD

AA14
AA15
N6
M6
L6
F16
P22
H22

OPT@

J7
K7

2

1

C1121

+IFPEF_PLLVDD

2

1

0.1U_0402_16V4Z

+IFPD_PLLVDD

2

D

0.1U_0402_16V4Z

Near GPU

1

0.1U_0402_16V4Z

2

R7
T7

2

1

4.7U_0603_6.3V6K

M7
N7

PEX_PLL_HVDD
PEX_PLL_HVDD

2

1

OPT@

+IFPC_PLLVDD

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD

2

C1053

OPT@
C1047

2

1

4.7U_0603_6.3V6K

OPT@
C1046

2

1

4.7U_0603_6.3V6K

OPT@
C1061

1

0.1U_0402_16V4Z

B

2

1

1U_0402_6.3V6K

+IFPAB_PLLVDD

V7
W7

1

3V3AUX
PEX_SVDD_3V3

1

Near GPU

OPT@

+IFPEF_IOVDD
+3VSDGPU
PEX_3V3

AB8
W6
Y6
P6
R6
H6
J6

+IFPAB_IOVDD
+IFPC_IOVDD
+IFPD_IOVDD

2

C1052

PEX_3V3

1

+1.05VSDGPU

Under GPU

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

0.1U_0402_16V4Z

2

F11

VDD33
VDD33
VDD33
VDD33

2

OPT@

C1060

1

G10
G12
G8
G9

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

2

1

C1051

OPT@

+VDD33
4.7U_0603_6.3V6K

OPT@

2

1U_0402_6.3V6K

2

1

C1059

OPT@

1

0.1U_0402_16V4Z

Near GPU

C1057

OPT@

2

0.1U_0402_16V4Z

1

C1056

OPT@

2

0.1U_0402_16V4Z

2

1

C1055

OPT@
C1054

1

0.1U_0402_16V4Z

Under GPU (one per pin)
R1068 1 OPT@ 2
0_0603_5%

VDD_SENSE

1

OPT@

+3VSDGPU

F2

2

C1018

VGA_VCCSENSE_R
0_0402_5%

2

1

1U_0402_6.3V6K

1

2

1

OPT@

2 OPT@
R1056

1

Near GPU

C1017

16mils

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21

OPT@

VGA_VCCSENSE

VGA_VCCSENSE

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

C1016

<55>

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

Under GPU

1

C

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18

POWER

+VGA_CORE

D

7200mA

1U_0402_6.3V6K

Part 4 of 5

A

near the ball

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

2012/12/31

Deciphered Date

Title

N13M-GS 4/7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

26

of

58

5

4

3

2

1

U48E
D

D

C

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

Part 5 of 5
AA7
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
K11
K13
K15
K17

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

FB_CAL_PU_GND
FB_CAL_TERM_GND
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF2_GND
GND_SENSE

B

L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
AB7

C

C24

RV98 1 OPT@

2 42.2_0402_1%

B25

RV101 1 OPT@

2 51.1_0402_1%

F6
F4
F5

R5537 1
R5538 1
R5539 1

2 40.2K_0402_1%
2 40.2K_0402_1%
2 40.2K_0402_1%

F1

VGA_VSSSENSE_R

@
@
@

1
R1057

OPT@

VGA_VSSSENSE
2
0_0402_5%

16mils
VGA_VSSSENSE

<55>

B

N13P-GV-S_FCBGA595~D

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

N13M-GS 5/7
Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

27

of

58

5

4

3

2

1

VRAM DDR3 chips (1GB)
128Mx16 DDR3 *4==>1GB
<24,29>
<24,29>
<24,29>
D

<24,29>
<24,29>

DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]

DQSA#[7..0]

UV13

DQMA[7..0]

+MEM_VREF0

MDA[63..0]

MDA[63..0]

CMDA[30..0]

CMDA[30..0]

1

+1.5VSDGPU

2

OPT@
R1096
1.33K_0402_1%
Near VRAM

C1069

2

2

0.1U_0402_16V4Z

1

OPT@

1

OPT@
R1097
1.33K_0402_1%

1

2

OPT@
C1091
0.1U_0402_16V4Z

M8
H1

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDA12
CMDA27
CMDA26

M2
N8
M3

+MEM_VREF0

CLKA0
CLKA0#
CMDA3

E3
F7
F2
F8
H3
H8
G2
H7

MDA4
MDA1
MDA5
MDA0
MDA6
MDA3
MDA7
MDA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA19
MDA20
MDA18
MDA23
MDA17
MDA22
MDA16
MDA21

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

Group2

+1.5VSDGPU

BA0
BA1
BA2

J7
K7
K9

+MEM_VREF1
Group0

CK
CK
CKE/CKE0

CMDA12
CMDA27
CMDA26

M8
H1

C

1

+1.5VSDGPU

2

OPT@
R1100
1.33K_0402_1%
Near VRAM

CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA0
DQSA2

F3
C7

DQSL
DQSU

DQMA0
DQMA2

E7
D3

DQSA#0
DQSA#2

G3
B7

1

C1070

OPT@
R1102
1.33K_0402_1%

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

1

2

DML
DMU
DQSL
DQSU

OPT@
C1092
0.1U_0402_16V4Z
CMDA5

T2

ZQ0

L8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RESET
ZQ/ZQ0

MDA12
MDA8
MDA15
MDA9
MDA13
MDA11
MDA14
MDA10

D7
C3
C8
C2
A7
A2
B8
A3

MDA25
MDA28
MDA24
MDA31
MDA26
MDA30
MDA27
MDA29

CK
CK
CKE/CKE0

CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA1
DQSA3

F3
C7

DQSL
DQSU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA1
DQMA3

E7
D3

DQSA#1
DQSA#3

DML
DMU

G3
B7

CMDA5

T2

ZQ1

L8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

ZQ/ZQ0

OPT@
RV1103
243_0402_1%

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Group3

ODT_L

CMD3

CKE

CMD4

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*

CLKA0#

CS0_H#
C

ODT_H

CMD18

CKE_H

CMD19
CMD20

A13

A13

CMD21

A8

A8

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

B1
B9
D1
D8
E2
E8
F9
G1
G9

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

B

Command Bit

Default Pull-down

ODTx

10k
10k

CKEx

DDR3

RST

10k

CS*

No Termination

@
1
2 R1101
80.6_0402_1%
1

CMDA2
CMDA3
CMDA5
CMDA18
CMDA19

2

C1090
OPT@

2

1

2

0.1U_0402_16V4Z

C1089
OPT@

2

1

0.1U_0402_16V4Z

C1088
OPT@

2

1

0.1U_0402_16V4Z

C1087
OPT@

2

1

0.1U_0402_16V4Z

C1086
OPT@

2

1

0.1U_0402_16V4Z

C1085
OPT@

1

1U_0402_6.3V6K

2

1U_0402_6.3V6K

C1084

C1083

2

1

OPT@

2

1

OPT@

1

1U_0402_6.3V6K

2

C1082

C1081
OPT@

2

1

0.1U_0402_16V4Z

C1080
OPT@

2

1

0.1U_0402_16V4Z

C1079
OPT@

2

1

0.1U_0402_16V4Z

C1078
OPT@

2

1

0.1U_0402_16V4Z

C1077
OPT@

2

1

0.1U_0402_16V4Z

C1076
OPT@

2

1

0.1U_0402_16V4Z

C1075
OPT@

2

1

1U_0402_6.3V6K

C1074
OPT@

2

1

1U_0402_6.3V6K

C1073

1

OPT@

2

+1.5VSDGPU

1U_0402_6.3V6K

C1072
OPT@

1

1U_0402_6.3V6K

+1.5VSDGPU

OPT@

@
C1071
0.01U_0402_16V7K

1U_0402_6.3V6K

CLKA0#

A14

CMD17

2

<24>

D

CMD2

CMD16

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@

OPT@
RV1
160_0402_1%

32..63

CS0_L#

CMD1
Group1

+1.5VSDGPU

J7
K7
K9

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@

@
1
2 R1099
80.6_0402_1%

1

E3
F7
F2
F8
H3
H8
G2
H7

1

2

J1
L1
J9
L9

B

CLKA0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CLKA0
CLKA0#
CMDA3

2

OPT@
RV1095
243_0402_1%

CLKA0

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

0..31

CMD0

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

1

2

2

0.1U_0402_16V4Z

1

OPT@

+MEM_VREF1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

<24>

Mode D
Address

UV12

DQMA[7..0]

RV112 1
RV113 1
RV115 1
RV116 1
RV117 1

OPT@
OPT@
OPT@
OPT@
OPT@

2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

Samsung :
Hynix :

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

2012/12/31

Deciphered Date

Title

N13M-GS 6/7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

28

of

58

5

4

3

2

1

VRAM DDR3 chips (1GB)
128Mx16 DDR3 *4==>1GB
Mode D
Address

D

DQMA[7..0]

<24,28>

DQMA[7..0]

<24,28>

CMDA[30..0]

<24,28>
<24,28>
<24,28>

UV10

CMDA[30..0]

+MEM_VREF2

M8
H1

DQSA#[7..0]

DQSA#[7..0]

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

DQSA[7..0]

DQSA[7..0]

MDA[63..0]

MDA[63..0]

1

+1.5VSDGPU

2

OPT@
RV119
1.33K_0402_1%
Near VRAM

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44
MDA42

D7
C3
C8
C2
A7
A2
B8
A3

MDA58
MDA60
MDA56
MDA61
MDA57
MDA63
MDA59
MDA62

+MEM_VREF3
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

Group5

Group7

+1.5VSDGPU

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34

D7
C3
C8
C2
A7
A2
B8
A3

MDA50
MDA53
MDA51
MDA55
MDA49
MDA54
MDA48
MDA52

Group4

Group6

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

CLKA1
CLKA1#
CMDA19

J7
K7
K9

CK
CK
CKE/CKE0

CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA5
DQSA7

F3
C7

DQMA5
DQMA7

E7
D3

DQSA#5
DQSA#7

G3
B7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CLKA1
CLKA1#
CMDA19

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA4
DQSA6

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA4
DQMA6

E7
D3

DQSA#4
DQSA#6

G3
B7

+1.5VSDGPU
C

1

+1.5VSDGPU

Near VRAM

CMDA5

T2

ZQ2

L8

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

2
@
RV125
80.6_0402_1%

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

OPT@
RV124
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CKE

D

CMD4

A14

CMD5

RST

A14
RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*
CS0_H#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

CMD18

ODT_H

CMD19

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

C

Not Available

B

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

1

2

CV152
OPT@

0.1U_0402_16V4Z

CV151
OPT@

0.1U_0402_16V4Z

CV149
OPT@

0.1U_0402_16V4Z

CV148
OPT@

0.1U_0402_16V4Z

CV144

CV147
OPT@

2

OPT@

CV143
OPT@

2

1

0.1U_0402_16V4Z

CV142
OPT@

2

1

0.1U_0402_16V4Z

CV141
OPT@

2

1

0.1U_0402_16V4Z

CV140
OPT@

2

1

0.1U_0402_16V4Z

CV139
OPT@

2

1

0.1U_0402_16V4Z

CV138
OPT@

1

0.1U_0402_16V4Z

CV137
OPT@

1U_0402_6.3V6K

CV136
OPT@

1U_0402_6.3V6K

OPT@

CV135

+1.5VSDGPU

1U_0402_6.3V6K

CV134
OPT@

1U_0402_6.3V6K

+1.5VSDGPU

1U_0402_6.3V6K

@
RV127
80.6_0402_1%
@
CV133
0.01U_0402_16V7K

RESET

CV146

CLKA1#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

OPT@

CLKA1#

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

OPT@
RV16
160_0402_1%
<24>

DML
DMU

1U_0402_6.3V6K

CLKA1

L8

CV145

CLKA1

ZQ3

OPT@

<24>

T2

2

OPT@
RV123
243_0402_1%

B

CMDA5

1U_0402_6.3V6K

2

OPT@
CV154
0.1U_0402_16V4Z

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

2

1

DML
DMU

ODT_L

CMD3

CMD17

1

0.1U_0402_16V4Z

1
2

1

CV132

OPT@
RV122
1.33K_0402_1%

OPT@

+MEM_VREF3

1U_0402_6.3V6K

2

OPT@
RV121
1.33K_0402_1%

CMD2

CMD16

+1.5VSDGPU

CV150

2

2

OPT@
CV153
0.1U_0402_16V4Z

CMDA12
CMDA27
CMDA26

OPT@

CV131

2

1

B2
D9
G7
K2
K8
N1
N9
R1
R9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

OPT@

1

OPT@
RV120
1.33K_0402_1%

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CS0_L#

CMD1

+MEM_VREF2
CMDA12
CMDA27
CMDA26

32..63

0..31

CMD0

UV11

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/05/23

2012/12/31

Deciphered Date

Title

N13M-GS 7/7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

29

of

58

5

4

3

2

1

+1.5V to +1.5VSDGPU
+VCCP to +1.05VSDGPU

@
C397
0.1U_0402_16V7K

2

1
2

2

D

@
R448
470_0603_5%

3

C387
OPT@

OPT@

2

1

1U_0402_6.3V6K

C386

1

10U_0603_6.3V6M

2

1
2
3

4

2

1.05VSG_GATE

OPT@
Q14B
2N7002DW-T/R7_SOT363-6
5

DGPU_PWROK#

4

1 OPT@ 2
R431
100K_0402_5%

4
OPT@
C395
0.01U_0603_25V7K

6

OPT@
Q15A
2N7002DW-T/R7_SOT363-6

1

DGPU_PWROK#
+VSB

2

C391

1

5

1

1

OPT@

OPT@
C390
10U_0603_6.3V6M

2

2

OPT@
C304
150U_B2_6.3VM_R35M

10U_0603_6.3V6M

+

OPT@
Q15B
2N7002DW-T/R7_SOT363-6

3

C389
OPT@

C388

1U_0402_6.3V6K

2

1.5VSG_GATE

6
OPT@ 2
R441
0_0402_5%

1

1
@
R430
470_0603_5%

DGPU_PWROK#

1

OPT@ 2
R445
0_0402_5%

2

@
C396
0.1U_0402_16V7K

1

DGPU_PWROK#

2

1

+1.05VSDGPU

1

1

OPT@
Q14A
2N7002DW-T/R7_SOT363-6

2

2

OPT@
C394
0.1U_0603_25V7K

1

1 OPT@ 2
R444
100K_0402_5%

+VSB

OPT@

2

1

+1.05VS_VTT
OPT@
U20
AO4304L_SO8
8
7
6
5

+1.5VSDGPU

10U_0603_6.3V6M

2

1

+1.5VSDGPU

1
2
3

4

1

OPT@

OPT@
C392
10U_0603_6.3V6M

OPT@
U21
AO4304L_SO8
8
7
6
5

10U_0603_6.3V6M

D

C393

+1.5V

1

2

C

C

+3VALW

1

+3VS to +3VSDGPU

1 OPT@ 2
R436
100K_0402_5%

1

DGPU_PWROK

OPT@
Q58A
2N7002DW-T/R7_SOT363-6

2

OPT@
Q18B
2N7002DW-T/R7_SOT363-6
DGPU_PWR_EN#

4

5

1

OPT@
R666
10K_0402_5%

2

3VSG_GATE

2
1

DGPU_PWROK

6

+VSB

<19,55>

OPT@
R435
470_0603_5%

3

2

1U_0402_6.3V6K

C399

2

1

OPT@

C398

2

1

OPT@

C401

1

2

DGPU_PWROK#

1

2

1

OPT@

OPT@
C400
10U_0603_6.3V6M

10U_0603_6.3V6M

3

+3VSDGPU

6

Q5
AP2301GN-HF_SOT23-3

10U_0603_6.3V6M

+3VS

2

OPT@
R665
100K_0402_5%

OPT@
Q18A
2N7002DW-T/R7_SOT363-6

B

1 OPT@ 2
R447
0_0402_5%

1

2

OPT@
C402
0.1U_0603_25V7K

B

1

+3VALW

2
1

@
C403
0.1U_0402_16V7K

2
1

DGPU_PWR_EN

3

DGPU_PWR_EN#

2

OPT@
R667
100K_0402_5%

OPT@
Q58B
2N7002DW-T/R7_SOT363-6

5
4

DGPU_PWR_EN

DGPU_PWR_EN

1

<15,18,55>

2

OPT@
R668
10K_0402_5%

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N13M-GE1-S-A1

Size
Document Number
Custom
LA-8971P
Date:

Rev
0.3

Wednesday, February 15, 2012
1

Sheet

30

of

58

4

3

2

600ohms @100MHz 1A
P/N: SM01000BU00

+3VS
+5VDDA_CODEC

+3VDD_CODEC

2

Place near Pin25

6
SDATA_IN

MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
MIC2-R(PORT-F-R)

2

SYNC

11

2 R1541 1
20K_0402_1%

JDREF

2

2 R1543 1
39.2K_0402_1%

SENSEA

SPK-OUT-L+

19

JDREF
SPK-OUT-LMONO-OUT(PORT-H)
SPK-OUT-R-

13

2.2U_0402_6.3V6M

Capless HP Sense
R940 place near pin34

2

2.2U_0402_6.3V6M
4.7U_0603_6.3V6K

CBN

35

1 C1239 CBP

36

2

1 C1240

34

2

1 C1241

28

LINE2-L(PORT-E-L)

Sense A

22

MIC_EXTR_C

C1237
2
1 2.2U_0402_6.3V6M

21

MIC_EXTL_C

2

2 R1534

C1229

C1228

1 1K_0402_5%

EXT_MIC

<32>

external MIC

1 2.2U_0402_6.3V6M

C1238

17

COMBO JACK detect (Normal OPen)

16
15
14

MIC_JD

SPK-OUT-R+

40

SPK_L+

1 R317
2
47K_0402_5%
1

Internal Speaker

41

SPK_L-

44

SPK_R-

45

SPK_R+

33

HPOUT_R 75_0402_5% 2 R1544

1

HP_OUTR

32

HPOUT_L

75_0402_5% 2 R1545

1

HP_OUTL

EXT_MIC

C165
4.7U_0603_6.3V6K
C

2

Sense-B
CBN

HPOUT-R(PORT-A-R)

CBP

HPOUT-L(PORT-A-L)

CPVEE

SPDIF-OUT
GPIO1/DMIC-CLK

MIC2-VREFO

30

<32>

+3VS

48

GPIO0/DMIC-DATA

3

DMIC_CLK_R

0_0402_5% 2 R1547

1

DMIC_CLK

2

DMIC_DATA_R

0_0402_5% 2 R1548

1

DMIC_DATA
@

1

C148

MIC1-VREFO-R

2

31

MIC1-VREFO-L

42
43
7

Headphone

<32>

MIC1

LDO-CAP

29

+MIC1_VREFO_L

23

PCBEEP

18

MIC Sense
R1543 place near pin13

LINE2-R(PORT-E-R)

RESET#

12

20
PLUG_IN#

C1227

1

SDATA-OUT

R1537
2.2K_0402_5%

24
2

LINE1-L(PORT-C-L)

SDATA-IN

10

PC_BEEP

<32>

C1226

9

1
DVDD1

25

38
AVDD2

AVDD1

LINE1-R(PORT-C-R)

PD#

BIT-CLK

8

HDA_SYNC_AUDIO

@
R1540
4.7K_0402_5%

Place near Pin9

PVSS1

VREF

PVSS2

AVSS1

DVSS

AVSS2
Thermal PAD

6
5
4

DMIC_DATA
DMIC_CLK

Internal D-MIC

0.1U_0402_16V4Z

5

HDA_BITCLK_AUDIO
2 R1536 1
22_0402_5%

DAPD/COMB_JACK

4

HDA_RST_AUDIO#

HDA_RST_AUDIO#

C

47

VDD
GND
DATA LEFT/RIGHT
CLOCK
GND

1
2
3

SPM0423HD4H-WB-2_6P

27
26
1
37
49

2

1
C1243

COMBO_JACK

DVDD-IO

2

EC_MUTE#_R
0_0402_5%

1

<14>

2

MIC2-L(PORT-F-L)
<14>

2

D

2

0.1U_0402_16V4Z

HDA_SDIN0

1 R1538

HDA_SDOUT_AUDIO

HDA_SDIN0

@

+MIC1_VREFO_L

C1242

HDA_BITCLK_AUDIO

Place near Pin1

1U_0603_10V4Z

HDA_SDOUT_AUDIO

<14>
1

<14>

<14>

@
R1535
4.7K_0402_5%

46

PVDD1
MIC_JD 0_0402_5% 1 R1533

+3VS

2

+IOVDD_CODEC

Power down (PD#) power stage for save power
0V: Power down power stage
3.3V: Power up power stage
EC_MUTE#

@

+3VDD_CODEC

PVDD2

2

39

1
C1236

2

U50

EC_MUTE#

2

1

Place near Pin38

0.1U_0402_16V4Z

1
C1235

2

0.1U_0402_16V4Z

C1234

1

<42>

1

2

1

+5VS_PVDD
4.7U_0603_6.3V6K

1 R1531 2
0_0805_5%

+5VS

2
C1233

C1232

1

4.7U_0603_6.3V6K

2

0.1U_0402_16V4Z

1
C1231

2

0.1U_0402_16V4Z

C1230

600ohms @100MHz 2A
P/N: SM01000EE00

4.7U_0805_10V4Z

1

1

10U_0603_6.3V6M

1 R1530 2
0_0402_5%
1

0.1U_0402_16V4Z

1 R1529 2
0_0603_5%

1
2
FBMA-L11160808601LMA10T_2P

D

+3VDD_CODEC

+5VDDA_CODEC
L37

1U_0603_10V4Z

+5VS

1

+IOVDD_CODEC

0.1U_0402_16V4Z

5

Place next to pin 27

ALC269Q-VC2-GR_QFN48_6X6

B

B

HDA_RST_AUDIO#

wide 40 mils

HDA_SYNC_AUDIO

Mic in

1 R1549 2
0_0402_5%

EC Beep

<42>

C1252 1

BEEP#

2 PC_BEEP1

0.1U_0402_16V4Z

1 R1557 2
33_0402_5%

1

2 C145 PC_BEEP
0.1U_0402_16V7K

1

C1253 1

PCH_SPKR

SPK_L-_CONN
SPK_L+_CONN

@

1

2

@

@
R1558
10K_0402_5%

2

5
6

GND1
GND2
ACES_88231-04001
CONN@

@
D39
PACDN042Y3R_SOT23-3

A

@
C162 1

2 0.1U_0402_16V4Z

@
C163 1

2 0.1U_0402_16V4Z

@
C164 1

2 0.1U_0402_16V4Z

Reserve for ESD request.

2

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

GND

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GNDA

Title

HD Audio Codec_ALC269Q-VC
Size
C

Document Number

4

3

2

Rev
0.1

LA-8971P

Date: Wednesday, February 15, 2012
5

1

1
2
3
4

2

0.1U_0402_16V4Z

PCH Beep <14>

SPK_R-_CONN

1

1 R1551 2 @
0_0402_5%

A

2

SPK_R+_CONN

@
D38
PACDN042Y3R_SOT23-3

1 R1550 2
0_0402_5%

PC Beep

1

C1251

External

2

@

1000P_0402_50V7K

MIC1(Pin21/22)

1

@

C1250

Headphone out

1000P_0402_50V7K

Int Speaker

External

C1249

Internal

Capless HP-OUT (Pin32/33)

1
2
3
4
1000P_0402_50V7K

EMI

SPK-OUT (Pin40/41/44/45)

C1248

@
C1247
33P_0402_50V8J

SPK_L+_CONN
SPK_L-_CONN
SPK_R+_CONN
SPK_R-_CONN
1000P_0402_50V7K

2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2

1

Function

2
2
2
2

3

2

Location

1
1
1
1

1

1

Pin Assignment

R1553
R1555
R1554
R1556

2

@

JSPK1
SPK_L+
SPK_LSPK_R+
SPK_R-

HDA_BITCLK_AUDIO

3

2

C1246

1

22P_0402_50V8J

@

C1245

2

22P_0402_50V8J

1

C1244

@

22P_0402_50V8J

HDA_SDOUT_AUDIO
1 R1552 2
27_0402_5%
@

Sheet
1

31

of

58

5

4

3

2

1

D

2

D

2
R315
470K_0402_5%
1

W=20mils

1

2

@
C161
100P_0402_50V8J

1

@
C156
100P_0402_50V8J
JHP1

EXT_MIC

<31>

PLUG_IN#

<31>

HP_OUTR

<31>

HP_OUTL

EXT_MIC_R

R2

1

2 0_0603_5%

PLUG_IN#

4

R1

1

2 0_0603_5%

HP_OUTR_R

R316 1

2 0_0603_5%

HP_OUTL_R

3
1
2

1

1

2

2

1

@
C159
10P_0402_50V8J

6
@
C160
10P_0402_50V8J

SUYIN_010036HR006G511ZL
CONN@

@
R313
0_0402_5%
2

@
R314
0_0402_5%
2

10
9
8
7
5

1

<31>

C

C

HP_OUTR_R
2

PLUG_IN#
3

2

HP_OUTL_R
3

EXT_MIC_R

D47
PJSOT24C 3P C/A SOT-23

1

1

D46
PJSOT24C 3P C/A SOT-23

PN: SCA00000T00

B

B

A

A

Compal Secret Data

Security Classification
2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.
Audio Combo Jack

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

32

of

58

5

4

3

2

1

+3V_LAN
1

D

+LAN_VDD10
L34
+LAN_REGOUT
2
1
2.2UH +-5% NLC252018T-2R2J-N

SA00003PO40

U47

LAN_CLKREQ#

<18,40,42>
<15>
<15>

C

PLT_RST#

CLK_PCIE_LAN
CLK_PCIE_LAN#

16

CLKREQB

PLT_RST#

25

PERSTB

CLK_PCIE_LAN
CLK_PCIE_LAN#

19
20

REFCLK_P
REFCLK_N

LAN_XTALI

43

CKXTAL1

LAN_XTALO

44

CKXTAL2

Pin 16 and Pin 28 are OD pins

<42>
<16,40>

R1508 1

LAN_WAKE#

2 0_0402_5%

R1509 1

PCH_PCIE_WAKE#

@

+3V_LAN

2 0_0402_5%

PCIE_WAKE#_R
ISOLATEB

@

2 R1510

1 10K_0402_5%

@

1 R1511

2 1K_0402_5%
ENSWREG

+LAN_VDDREG

2 R1513 1
2.49K_0402_1%

28
26

30
32

R1506 1
R1507 1

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

1
2
4
5
7
8
10
11

MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-

DVDD10
DVDD10
DVDD10

13
29
41

@
@

2 10K_0402_5%
2 10K_0402_5%

MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-

+LAN_VDD10

<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>

C1187
1U_0402_6.3V4Z

27
39

+3V_LAN

14
15
38

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

12
42
47
48

+3V_LAN

33

ENSWREG
EVDD10

21

+LAN_EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

3
6
9
45

+LAN_VDD10

REGOUT

36

RSET

24
49

GND
PGND

+3V_LAN

+LAN_VDDREG

1 L36
2
0_0603_5%
C1195
4.7U_0603_6.3V6K

C1189 2

1 0.1U_0402_16V4Z

C1190 2

1 0.1U_0402_16V4Z

C1191 2

1 0.1U_0402_16V4Z

C1192 2

1 0.1U_0402_16V4Z

GIGA@ C1193 2

1 0.1U_0402_16V4Z

GIGA@ C1194 2

1 0.1U_0402_16V4Z

C

C1196
0.1U_0402_16V4Z

X5R

Close to Pin 3,6,9,13,29,41,45
+LAN_VDD10
+3VS

+3V_LAN

C1197 2

1 0.1U_0402_16V4Z

C1198 2

1 0.1U_0402_16V4Z

C1199 2

1 0.1U_0402_16V4Z

GIGA@

C1200 2

1 0.1U_0402_16V4Z

GIGA@

C1201 2

1 0.1U_0402_16V4Z

GIGA@

C1202 2

1 0.1U_0402_16V4Z

GIGA@

C1203 2

1 0.1U_0402_16V4Z

+LAN_REGOUT

R366
1K_0402_5%

2

RTL8111F-CGT_QFN48_6x6
GIGA@

B

C1188
0.1U_0402_16V4Z

Close to Pin 21

+3V_LAN

DVDD33
DVDD33

46

Close to Pin 12,27,39,42,47,48

+LAN_VDD10

ISOLATEB

VDDREG
VDDREG

+LAN_EVDD10

1 L35
2
0_0603_5%

LANWAKEB

34
35

2

Rising time (10%~90%)1mS 

LAN_CLKREQ#

EECS
EEDI

2

LAN_LINK# <34>
LAN_ACTIVITY# <34>

1

HSIP
HSIN

LAN_LINK#
LAN_ACTIVITY#

1

JUMP_43X79

ENSWREG

1

SA00004Y700

ISOLATEB

R1515
0_0402_5%

2

17
18

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

31
37
40

@ J15

1

1

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

<15>
<15>

LED3/EEDO
LED1/EESK
LED0

1

HSON

2

HSOP

23

1

22

PCIE_DTX_PRX_N1

2

PCIE_DTX_PRX_P1

2 0.1U_0402_16V7K

1

2 0.1U_0402_16V7K

C1186 1

2

C1183 1

PCIE_DTX_C_PRX_N1

1

PCIE_DTX_C_PRX_P1

<15>

C1182
0.1U_0402_16V4Z

X5R

2

<15>

2

C1184
4.7U_0603_6.3V6K
Layout Note: L34 must be
within 200mil to Pin36,
C1184,C1182 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

RTL8105E-VL-CGT

+3V_LAN

+3VALW
1

LAN_CLKREQ#

D

Layout Notice : Place as close
chip as possible.

2

8105@

2

U47

1

@
R1512
10K_0402_5%

@
R1517
0_0402_5%

2

2

R365
15K_0402_5%

B

LAN_XTALI

C1204
27P_0402_50V8J

NC

1

OSC

OSC

3

NC

2

1 25MHZ_20PF_FSX3M-25.M20FDO 1

2

H: Enable internal Regulator
L: Disable

LAN_XTALO

Y4

4

C1205
27P_0402_50V8J

2

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/15

2012/07/11

Deciphered Date

Title

LAN-RTL8111F/8105E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Wednesday, February 15, 2012
Date:

Rev
0.1

LA-8971P

5

4

3

2

Sheet
1

33

of

58

5

4

3

2

1

Reserve gas tube for EMI go rural solution
TS2

Place Close to TS1,TS2

D

16
15
14
13
12
11
10
9

MDO3+
MDO3MCT3

GIGA@ 1 R1518

2 75_0603_5%

GIGA@ 1 R1519

2 75_0603_5%

MCT2
MCT2
MDO2+
MDO2-

MCT1

1

<33> MDI1+
<33> MDI1C1207
0.01U_0402_16V7K

MDI1+
MDI1-

TX+
TXCT
NC
NC
CT
RX+
RX-

16
15
14
13
12
11
10
9

MDO0+
MDO0MCT0
MCT1
MDO1+
MDO1-

@

1 R1520

2 75_0603_5%

1 R1521

2 75_0603_5%

2
DL4

2
@

@

1

BOTHHAND_NS0013LF

2

@

LSE-200NX3216TRLF_1206-2

TD+
TDCT
NC
NC
CT
RD+
RD-

1

1
2
3
4
5
6
7
8

1

MDI0+
MDI0-

DL3

2
DL1

TS1
MDI0+
MDI0-

LSE-200NX3216TRLF_1206-2

MCT0

BOTHHAND_NS0013LF
GIGA@

<33>
<33>

D

MCT3

1

TX+
TXCT
NC
NC
CT
RX+
RX-

2

MDI2+
MDI2-

TD+
TDCT
NC
NC
CT
RD+
RD-

LSE-200NX3216TRLF_1206-2

MDI2+
MDI2-

1
2
3
4
5
6
7
8

DL2

<33>
<33>

MDI3+
MDI3-

1

MDI3+
MDI3-

LSE-200NX3216TRLF_1206-2

<33>
<33>

2

C1206
47P_0402_50V8J

C

C

D13 @
MDI2+

1

2

MDI3-

3

I/O1

I/O3

GND

VDD

I/O2

I/O4

4

MDI3+

JLAN1

5

6

<33>

MDI2-

LAN_ACTIVITY#

2 510_0402_1%

@
C146
470P_0402_50V7K

AZC099-04S.R7G_SOT23-6

11

1

2

Place Close to TS2

B

1

I/O1

I/O3

4

MDI0+

<33>

1 R299

LAN_LINK#

GND

VDD

I/O2

I/O4

5
2

MDI0-

3

8

MDO3+

7

MDO1-

6

MDO2-

5

MDO2+

4

MDO1+

3

MDO0-

2

MDO0+

1

2 510_0402_1%
1

2

MDO3-

+3V_LAN

D14 @
MDI1+

12

+3V_LAN

1 R298

6

10
9

@
C147
470P_0402_50V7K

Yellow LED+

D15 @

3

Yellow LED-

1

PR4-

G1

PR4+

G2

13

2

14

PJDLC05C_SOT23-3

PR2PR3PR3+
PR2+

C154 2
@

1 0.1U_0402_16V7K

C155 2
@

1 0.1U_0402_16V7K

B

PR1PR1+
Green LED+
Green LEDSANTA_130452-D
CONN@

MDI1-

AZC099-04S.R7G_SOT23-6

Place Close to TS1

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/15

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

LAN_Transformer
Rev
0.1

LA-8971P

Wednesday, February 15, 2012
1

Sheet

34

of

58

5

4

3

2

LCD POWER CIRCUIT

1

CMOS Camera
+3VS

+LCDVDD

+5VALW
+3VS
1

1

1

W=60mils

3

2

G

IN

1

2

1

2

CMOS_ON#

1

2

+LCDVDD_CONN

+LCDVDD

2
CMOS@
C27
0.1U_0402_16V4Z

D

CMOS@
C28
0.1U_0402_16V4Z

1

2

@
C30
10U_0603_6.3V6M

L29
1
2
FBMA-L11-201209-221LMA30T_0805
Q73
DTC124EKAT146_SC59-3

C24
4.7U_0805_10V4Z

2

3

@
R179
100K_0402_5%

<42>

CMOS@
1 R185
2
150K_0402_5%

W=60mils

GND

OUT

1

3

PCH_ENVDD

PCH_ENVDD

1

D

<17>

C23
0.1U_0402_16V7K

1
Q72
PMV65XP_SOT23-3~D

2

G

S

1

S

1 2

3

1 R178
2
220K_0402_5%

2
G

CMOS@
1 R186
2
0_0603_5%

D

S

Q71
2N7002_SOT23

(20 MIL)

2

R177
100K_0402_5%

D

D

+3VS_CMOS
CMOS@
Q70
PMV65XP_SOT23-3~D

(20 MIL)

2

R102
150_0603_1%

C26
4.7U_0805_10V4Z

1

1

2

2

C25
0.1U_0402_16V4Z

+LEDVDD

B+
2 R187
1
0_0805_5%

@
C31
680P_0402_50V7K

+3VS

1

2

2

C32
4.7U_0805_25V6-K
C

1

C

1

@
R183
4.7K_0402_5%
2

1 R180
2
0_0402_5%

BKOFF#

BKOFF#
1

<42>

1

1 R303
2
0_0402_5%

DISPOFF#

2
D30 @
CH751H-40PT_SOD323-2

R182
10K_0402_5%

1 @
C34
470P_0402_50V7K

2

2

<18>

USB20_N8

USB20_N8

1

<18>

USB20_P8

USB20_P8

4

1

L11 @

2

4

3

2

USB20_N8_R

3

USB20_P8_R

LCD Conn.

WCM-2012-900T_4P

PCH_ENBKL

PCH_ENBKL

1 R181
2
0_0402_5%

ENBKL

ENBKL

<42>

1 R304
2
0_0402_5%

1

<17>

+LEDVDD

+LEDVDD

JLVDS2
R184
100K_0402_1%

2

(60 MIL)
DISPOFF#
INVT_PWM

B

CMOS

+3VS_CMOS

USB20_N8_R
USB20_P8_R

+3VS
+LCDVDD_CONN
EDID_DATA
EDID_CLK
LVDS_ACLK
LVDS_ACLK#
LVDS_A2
LVDS_A2#
LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

(60 MIL)

<17>
<42>

PCH_PWM

EC_INVT_PWM

PCH_PWM

1 R188

EC_INVT_PWM

1

DISPOFF#
INVT_PWM

2 0_0402_5%

@
2 0_0402_5%
R189 +3VS_CMOS

USB20_N8_R
USB20_P8_R

CMOS
+3VS
@
C33
680P_0402_50V7K

GND1
GND2
GND3
GND4
GND5
GND6

1
+LCDVDD_CONN
2

<17>
<17>
<17>
<17>

EDID_DATA
EDID_CLK
LVDS_ACLK
LVDS_ACLK#

<17>
<17>
<17>
<17>
<17>
<17>

31
32
33
34
35
36

<17>
<17>

STARC_107K30-000001-G2
CONN@

LVDS_A2
LVDS_A2#
LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#

LVDS_BCLK
LVDS_BCLK#

<17>
<17>
<17>
<17>
<17>
<17>

LVDS_B2
LVDS_B2#
LVDS_B1
LVDS_B1#
LVDS_B0
LVDS_B0#

EDID_DATA
EDID_CLK
LVDS_ACLK
LVDS_ACLK#
LVDS_A2
LVDS_A2#
LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#
LVDS_BCLK
LVDS_BCLK#
LVDS_B2
LVDS_B2#
LVDS_B1
LVDS_B1#
LVDS_B0
LVDS_B0#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43
44
45
46

G1
G2
G3
G4
G5
G6

B

STARC_107K40-000001-G2
CONN@

A

Compal Secret Data

Security Classification
2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.
LVDS/CAMERA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

A

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

35

of

58

1

2

2

3

3

2

4

3

5

D9
PJDLC05C_SOT23-3

+5VS

D10
PJDLC05C_SOT23-3

+CRT_VCC_R

+CRT_VCC

D2

40mil

F2
1

1

RB491D_SC59-3

1

1

2

2

1.1A_6V_SMD1812P110TF

1

D

L1

L2
1
2
FBMA-10-100505-800T 0402

L5
1
2
FBMA-10-100505-800T 0402

CRT_G_L

L3

2

1
C62

C48

2

1

BLUE

1
2
FBMA-10-100505-800T 0402
2.2P_0402_50V8C

2

1
C44

C36

2

1

2.2P_0402_50V8C

2

1
C59

C58

1

2.2P_0402_50V8C

2.2P_0402_50V8C

C50

2

2.2P_0402_50V8C

R197 1
2
150_0402_1%

R198 1
2
150_0402_1%

1

CRT_B_L

1
2
FBMA-10-100505-800T 0402

2.2P_0402_50V8C

PCH_CRT_B

PCH_CRT_B
R199 1
2
150_0402_1%

<17>

GREEN

L6

2

1

2

1

2

2.2P_0402_50V8C

PCH_CRT_G

C69

PCH_CRT_G

D

RED

1
2
FBMA-10-100505-800T 0402

2.2P_0402_50V8C

<17>

CRT_R_L

1
2
FBMA-10-100505-800T 0402

C63

PCH_CRT_R

2.2P_0402_50V8C

PCH_CRT_R

<17>

C70
0.1U_0402_16V7K

2

L4

Mini-VGA CONNECTOR
JCRT1
CRT_DDC_CLK
VSYNC
+CRT_VCC

BLUE
HSYNC
GREEN
CRT_DDC_DAT

C

RED
+CRT_VCC
C83

CRT_HSYNC

2

A

G

1 R286
2
33_0402_5%

3

PCH_CRT_HSYNC

P
OE#

0.1U_0402_16V4Z
<17>

1 R200
2
10K_0402_5%

2
5
1

1

+CRT_VCC

CRT_HSYNC_L

4

Y

L7
1
2
MBC1608121YZF_0603

HSYNC

L8
1
2
MBC1608121YZF_0603

VSYNC

1
2
3
4
5
6
7
8
9
10
11
12

DDC_CLK
GND
JVGA_VS
CRT_VCC
BLUE
JVGA_HS
GND
GREEN
DDC_DAT
GND
RED
GND

13
14
15
16

GND
GND
GND
GND

C

BELLW_WK2011-0090-2
CONN@

U12
SN74AHCT1G125GW_SOT353-5

C84
2

H1

H2
H_2P8

H3
H_2P8

H4
H_2P8

H6
H_2P8

H7
H_2P8

H8
H_2P8

H9
H_2P8

1

2

Screw Hole
1

1

1

2

@

1

1

C85

@

1

CRT_VSYNC_L

U14
SN74AHCT1G125GW_SOT353-5

1

4

Y

1

A

1

2

C89

CRT_VSYNC

10P_0402_50V8J

1 R290
2
33_0402_5%

G

PCH_CRT_VSYNC

3

<17>

P
OE#

0.1U_0402_16V4Z

10P_0402_50V8J

5
1

1

H_2P8

B

B

+CRT_VCC

@

4

@

@

H14
H_4P0

@

H_4P0

@

4

CRT_DDC_CLK

H21

Vp

5

H23
H_3P3

H_3P3

+CRT_VCC

2

Vn

H22
H_3P3

1

CH4

1

CH1

@

@

@

Q12A
CRT_DDC_DAT

6

3

CH2

CH3

6

CRT_DDC_DAT

CM1293-04SO_SOT23-6
2N7002DW-T/R7_SOT363-6

FD1
@

1

H5
H_2P8N

@

FIDUCIAL_C40M80

FD3

FD4

H10
H_2P8N

@

A

H_2P9X3P4N

@

@

FIDUCIAL_C40M80

Compal Secret Data

Security Classification
2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Date:

4

3

@

FIDUCIAL_C40M80

Compal Electronics, Inc.
Mini-VGA & Screw Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

@

FIDUCIAL_C40M80

1

H41

A

1

@
C94
68P_0402_50V8J

1

2

1

2

Q12B
@
2N7002DW-T/R7_SOT363-6
@
C97
C93
33P_0402_50V8K
68P_0402_50V8J

2

1

1

1

2

@
C95
33P_0402_50V8K

FD2

CRT_DDC_CLK

3

1

PCH_CRT_CLK

PCH_CRT_CLK

@

1

<17>

@

1

5

1

1

2

VSYNC
PCH_CRT_DATA

H13
H_4P0

@

1

1

1
2

HSYNC
R202
4.7K_0402_5%

2

R201
4.7K_0402_5%

PCH_CRT_DATA

@

D4 @

+3VS

<17>

H12
H_4P0

1

1

H11

@

1

@

1

@

2

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet
1

36

of

58

5

4

3

2

1

+5VS

HDMI@

+5VS

2

2

2

TMDS_B_HPD#

3

1

4

3

HDMI@
R1472
20K_0402_5%

HDMIDAT_R

HDMI@
R1470
2.2K_0402_5%
2

PCH_HDMIDAT

1

TMDS_B_HPD#

1

2

2
<17>

HDMICLK_R

1

2

HDMI@
C99
0.1U_0402_16V4Z

D

JHDMI1
HDMI_HPD

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+5VS_HDMI
HDMIDAT_R
HDMICLK_R
HDMIDAT_R
<17>

HDMI_CLK-_CK

HDMI_CLK-_CK R203 1

@

2 0_0402_5%

HDMI_CLK-_CONN

<17>
<17>

HDMI_CLK+_CK
HDMI_TX0-_CK

HDMI_CLK+_CKR204 1
HDMI_TX0-_CK R205 1

@
@

2 0_0402_5%
2 0_0402_5%

HDMI_CLK+_CONN
HDMI_TX0-_CONN

<17>
<17>

HDMI_TX0+_CK
HDMI_TX1-_CK

HDMI_TX0+_CK R206 1
HDMI_TX1-_CK R207 1

@
@

2 0_0402_5%
2 0_0402_5%

HDMI_TX0+_CONN
HDMI_TX1-_CONN

<17>
<17>

HDMI_TX1+_CK
HDMI_TX2-_CK

HDMI_TX1+_CK R208 1
HDMI_TX2-_CK R209 1

@
@

2 0_0402_5%
2 0_0402_5%

HDMI_TX1+_CONN
HDMI_TX2-_CONN

<17>

HDMI_TX2+_CK

HDMI_TX2+_CK R210 1

@

2 0_0402_5%

HDMI_TX2+_CONN

2

HDMICLK_R

3

1

HDMI@
R1471
2.2K_0402_5%

HDMI@
Q75B
2N7002DW-T/R7_SOT363-6

@
D33
PJDLC05_SOT23-3

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

C

SUYIN_100042GR019M26DZL
CONN@

1

C

+5VS_HDMI

2

HDMI@
1.1A_6VDC_FUSE

+5VS_HDMI

2

6

@
D32
BAT54S-7-F_SOT23-3

1

PCH_HDMIDAT

1
5

<17>

PCH_HDMICLK

D

PCH_HDMICLK

HDMI@
Q74
2N7002H_SOT23-3

S

<17>

HDMI@
R1469
1M_0402_5%

HDMI@
Q75A
2N7002DW-T/R7_SOT363-6

G

2

D

F1
+HDMI_5V

1

HDMI@
D6
C122
RB491D_SC59-3
0.1U_0402_16V4Z

1

3
1

2

1

2

1

+3VS
HDMI@
R211
0_0402_5%

+5VS_HDMI

W=40mils

+3VS

HDMI_CLK+_CK

1

HDMI_CLK-_CK

4

1

L30 HDMI@

4

2
3

2

HDMI_CLK+_CONN

3

HDMI_CLK-_CONN

WCM-2012HS-900T
HDMI_TX0+_CK
HDMI_TX0-_CK

1
4

1

L31 HDMI@

4

2
3

2
3

HDMI_CLK+_CONN @

C100 1

2 0.1U_0402_16V4Z

HDMI_CLK-_CONN @

C101 1

2 0.1U_0402_16V4Z

HDMI_TX0+_CONN @

C102 1

2 0.1U_0402_16V4Z

HDMI_TX0-_CONN @

C105 1

2 0.1U_0402_16V4Z

HDMI_TX1+_CONN @

C118 1

2 0.1U_0402_16V4Z

HDMI_TX1-_CONN @

C119 1

2 0.1U_0402_16V4Z

HDMI_TX0+_CONN
HDMI_TX0-_CONN

WCM-2012HS-900T
HDMI_TX1+_CK
HDMI_TX1-_CK

1
4

1

L32 HDMI@

4

2
3

2
3

HDMI_TX1+_CONN
HDMI_TX1-_CONN

WCM-2012HS-900T
B

HDMI_TX2+_CK

1

HDMI_TX2-_CK

4

1

L33 HDMI@

4

2
3

2

HDMI_TX2+_CONN

HDMI_TX2+_CONN @

C120 1

2 0.1U_0402_16V4Z

3

HDMI_TX2-_CONN

HDMI_TX2-_CONN @

C121 1

2 0.1U_0402_16V4Z

B

WCM-2012HS-900T

HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN

5
6
7
8

RP1 HDMI@
4
3
2
1

SD309680080
S ROW RES 1/16W 680 +-5% 8P4R

680 +-5% 8P4R
HDMI_TX2-_CONN
HDMI_TX2+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN

5
6
7
8

RP2 HDMI@
4
3
2
1

+3VS
1

680 +-5% 8P4R

D

3

S
A

2011/06/15

Issued Date

A

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

2
G
HDMI@
Q76
2N7002H_SOT23-3

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI CONN

Date: Wednesday, February 15, 2012

5

4

3

2

Rev
0.1

LA-8971P
Sheet
1

37

of

58

A

B

C

D

E

F

G

H

SATA HDD Conn.
1

1

JHDD1

<14> SATA_PRX_C_DTX_N1_R
<14> SATA_PRX_C_DTX_P1_R
<14> SATA_PTX_DRX_N1_R
<14> SATA_PTX_DRX_P1_R

SATA_PRX_C_DTX_N1_R
SATA_PRX_C_DTX_P1_R
SATA_PTX_DRX_N1_R
SATA_PTX_DRX_P1_R

HM77@
HM77@
HM77@
HM77@

C134
C135
C139
C140

2
2
2
2

1
1
1
1

0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

HM70@
HM70@
HM70@
HM70@

C132
C133
C138
C137

2
2
2
2

1
1
1
1

0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
+3VS_HDD

<14> SATA_PRX_C_DTX_N2
<14> SATA_PRX_C_DTX_P2
<14> SATA_PTX_DRX_N2
<14> SATA_PTX_DRX_P2

+3VS

1 R1527 2
0_0805_5%

+5VS

1 R1526 2
0_0805_5%

+5VS_HDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
ACES_50406-02071-001
CONN@

2

C1221

2

1

2

2

10U_0603_6.3V6M

2

1
C1220

2

1

1U_0603_10V4Z

1

C1219

1
C1222
0.1U_0402_16V4Z

C1218

+5VS_HDD

1000P_0402_50V7K

+3VS_HDD

0.1U_0402_16V4Z

2

3

3

4

4

Compal Secret Data

Security Classification
2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
SATA HDD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

E

F

Wednesday, February 15, 2012
G

Rev
0.1

LA-8971P
Sheet

of

38
H

58

5

4

3

2

1

SATA ODD FFC CONN.
JODD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14

<14> SATA_PTX_DRX_P4
<14> SATA_PTX_DRX_N4
<14> SATA_PRX_C_DTX_N4
<14> SATA_PRX_C_DTX_P4
<19>
D

ODD_DETECT#

ODD_DETECT#

<42>

ODD_DA#

ODD_DA#
+3VS

<18>

ODD_DETECT#_R
2
0_0402_5%
+5VS_ODD

1 R535
2
0_0402_5%

ODD_DA#_R

1 R318
2
10K_0402_5%
R537 1
@
2
0_0402_5%

PCH_ODD_DA#

ACES_88514-01201-071
CONN@

@

2 0_0805_5%

Place caps. near ODD CONN.
S

S

C629

2
G

ODD_EN#

1

2

C3604

10U_0805_10V4Z

C3603

1U_0402_6.3V4Z

C3602

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

Q5509
2N7002_SOT23-3
3

<19>

D

R681 2
1
1.5M_0402_5%

ODD_EN
C

+5VS_ODD
C3601

G

Q30
SI3456DDV-T1-GE3_TSOP6

1000P_0402_50V7K

4

3

C624

2

2

6
5
2
1

1U_0402_6.3V6K

1

D

R677 1

1
R678
470K_0402_5%

D

+5VS_ODD

+5VS
+VSB

@
1
R536

1
2
3
4
5
6
7
8
9
10
11
12
13
14

C

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/12

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SATA ODD Conn
Rev
0.3

LA-8971P

Wednesday, February 15, 2012

Sheet
1

39

of

58

A

B

C

D

Mini-Express Card for WLAN with BT(Half)

Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

R254 1
@
2 0_0402_5%
BT_DISABLE_R
WLAN_CLKREQ#

<15> CLK_PCIE_WLAN1#
<15> CLK_PCIE_WLAN1

<15>
<15>

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
+3VS_WLAN

EC_TX 1 R1498
EC_RX 1 R1499

EC_TX
EC_RX

2 100_0402_1%
2 100_0402_1%

+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
1 R1492

+3VS

+3VS_WLAN
noAOAC@
R7
1
2
0_0603_5%
1

2 0_0402_5%

R1494 1
R1495 1

@

R275 1
R277 1

@
@

2

+3VS_WLAN_AOAC

1

@

AOAC@
2 R1500 1
0_0603_5%

2

AOAC@
Q77
AO3413_SOT23-3

+3VALW

PCH_WL_OFF#

WL_RST#
2 0_0402_5%
2 0_0402_5%

<18>
R1493

3

1 PLT_RST#
0_0402_5%

PLT_RST#

1

AOAC@
1 R1502 2
150K_0402_5%

AOAC_ON#

PCH_SMBCLK <12,13,15,43>
PCH_SMBDATA
<12,13,15,43>

1

2

For Bluetooth

USB20_N10_WLAN

1 R1503 2
0_0402_5%

USB20_N10

USB20_P10_WLAN

1 R1504 2
0_0402_5%

USB20_P10

1

<18,33,42>
<42>

2 0_0402_5%
2 0_0402_5%

USB20_N10_WLAN
USB20_P10_WLAN

2

+3VALW
+3VS_WLAN

2

AOAC@
C1174
0.1U_0402_16V4Z

AOAC@
C1175
0.1U_0402_16V4Z

Intel AOAC function
JWLAN1 Pin2,24,52

contact to +3VS_WLAN for AOAC function

1

<42>
<42>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

G

<15>
<15>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

D

PCI_RST#_R
CLK_PCI_DB

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2

S

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<18>

1

C1173

BT_ACTIVE
WLAN_CLKREQ#

CLK_PCI_DB

2

<15>

2 0_0402_5%

R1488
0_0603_5%

JWLAN1

C1172

<43> BT_ACTIVE
2 0_0402_5%

2 0_0402_5%

LPC_FRAME#
<14,42>
LPC_AD3
<14,42>
LPC_AD2
<14,42>
LPC_AD1
<14,42>
LPC_AD0
<14,42>

C1171

@

1

+3VS_WLAN

2 0_0402_5%
@

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

10U_0603_6.3V6M

R1491 1

R255 1

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

C1170

BT_DISABLE

R1490 1

R294 1

PCH_PCIE_WAKE#

2
2
2
2
2
2

0.1U_0402_16V4Z

<19>

PCH_BT_ON#

EC_WL_WAKE#

@
@
@
@
@
@

1
1
1
1
1
1

0.1U_0402_16V4Z

<19,43>

EC_WL_WAKE#
PCH_PCIE_WAKE#

2

<42>

R1482
R1483
R1484
R1485
R1486
R1487

+1.5VS

1

+1.5VS

0.1U_0402_16V4Z

1

<16,33>

E

GND1

GND2

54

2

2

+3VALW

PLAST_SSM010-52-B-K
CONN@
U1
7
USB20_N10_WLAN
USB20_P10_WLAN

5
3
4

@

@

NC

VCC

D-

HSD-

D+
GND

HSD+
OE#

C1273 1

8
6

USB20_N10

2

USB20_P10

1

TS3USB31RSER_QFN8_1P5X1P5

2 0.1U_0402_16V4Z
USB20_N10

<18>

USB20_P10

<18>

WLAN_USB_ON#

<42>

1

53
R1501
100K_0402_5%

2

2

@
R1522
0_0402_5%

Mini-Express Card for SSD(Full)

3

3

SSD Active:4.5W(1.5A)

<14>
<14>

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

<14>
<14>

C2050 2
C2051 2

1 0.01U_0402_16V7K SATA_PRX_DTX_C_P0
1 0.01U_0402_16V7K SATA_PRX_DTX_C_N0

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

+3VS_SSD

4

<19>

mSATA_DET#

R278 1
@
2
0_0402_5%

mSATA_DET#_R

53

GND1

GND2

2

1
C1178

1

2

10U_0603_6.3V6M

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

C1177

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C1176

1
JSSD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

0.1U_0402_16V4Z

1 R295
2
0_0805_5%

0.01U_0402_25V7K

+3VS_SSD

+3VS

1

2

@
C1179
10U_0603_6.3V6M

4

54

MOLEX_67910-5700
CONN@

Compal Secret Data

Security Classification
Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

B

C

D

Document Number

Rev
0.1

LA-8971P
Date:

A

Compal Electronics, Inc.
W/L & m-SATA Card
Wednesday, February 15, 2012
E

Sheet

40

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/12

2012/12/31

Deciphered Date

Title

NULL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

LA-8971P

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

41

of

58

+EC_VCCA

KSO[0..17]

+3VALW

KSI[0..7]
<46>

KSI[0..7]

EC_SMB_CK1

2

2.2K_0402_5%
EC_SMB_DA1

2

2.2K_0402_5%

1

1

+3VS

1

2

2

R1576
2.2K_0402_5%

2

R1575
2.2K_0402_5%

@
C1267
100P_0402_50V8J

1

2

EC_SMB_CK2
EC_SMB_DA2
@
C1268
100P_0402_50V8J

<48,50>
<48,50>
<15,23,44>
<15,23,44>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#

<16> PM_SLP_S3#
<16> PM_SLP_S5#
<19> EC_SMI#
<35> CMOS_ON#
<16> SLP_SUS#
<45> CHG_MODE1
<39> ODD_DA#
<35> EC_INVT_PWM
<44> EC_TACH

<16>
<44>

+3VS

CHG_MODE1
ODD_DA#
EC_INVT_PWM
EC_TACH
EC_PME#
EC_TX
EC_RX
PCH_PWROK
EC_FAN_PWM

<40> EC_TX
<40> EC_RX
PCH_PWROK
EC_FAN_PWM

NUM_LED#: NC
1 R1581

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

<16>

SUSCLK

SUSCLK_R

122
123

XCLKI/GPIO5D
XCLKO/GPIO5E

1

EC_FAN_PWM

1 R1586 2
0_0402_5%

C1271
20P_0402_50V8

67

SPI Flash ROM

GPIO
Bus

GPIO

+3VALW

1

max
MP
PVT
DVT
EVT

V
V
V

97
98
99
109

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

2 R1565

1
1

EC_MUTE#
USB_ON#
USB3_ON#
TP_CLK
TP_DATA

VSBP_EN_R
ME_FLASH
NTC_V_R

@

73
74
89
90
91
92
93
95
121
127

124

+V18R

1

VSBP_EN 2 R325
1
0_0402_5%

2 R1566

USB3_ON#

10K_0402_5%
2 R1582 1
10K_0402_5%

1

EC_WL_WAKE# 2 R16
1
10K_0402_5%

@
R1572
100K_0402_1%

PCH_PWR_EN

<10,47>

PCH_PWR_EN
VSBP_EN

2 R58

CHG_MODE0

+3VALW

1

10K_0402_5%

<49>

<14>

+3VS

1 0_0402_5%

NTC_V

AOAC_ON#

R15
100K_0402_1%

<49>
PCH_PWR_EN
<21>
PWR_GPS_DOWN#
<55>

2 R256@ 1 0_0402_5%
<40>

ENBKL <35>
AC_PRESENT

R1567 1

2 4.7K_0402_5%

TP_DATA

R1569 1

2 4.7K_0402_5%

1 @ R300 2 0_0402_5%

WLAN_USB_ON#

@ C136 1

2 100P_0402_50V8J

BATT_TEMP

C1265 1

2 100P_0402_50V8J

ACIN

C1266 1

<40>

R1573 1

<43>

2 @ R257 1 0_0402_5%

PWR_LED
<43>
BATT_LOW_LED#
<43>
SYSON
<47,52>
VR_ON <56>
PM_SLP_S4# <16>

EC_RSMRST#
EC_LID_OUT#

TP_CLK

NTC_V_R

<16>

BATT_CHG_LED#

EC_RSMRST#
EC_LID_OUT#
Turbo_V
H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#
SUSWARN#
SA_PGOOD

USB_ON#

+3VALW

1 0_0402_5% VSBP_EN
ME_FLASH

ENBKL
AC_PRESENT
WLAN_USB_ON#_R
BATT_CHG_LED#
ACIN_BUF#
PWR_LED
BATT_LOW_LED#
SYSON
VR_ON
PM_SLP_S4#

ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
PCH_HOT#_R
PECI_KB9012

+3VALW

CPU1.5V_S3_GATE

R324 2

PCH_PWR_EN
PWR_GPS_DOWN#_R
AOAC_ON#

110
112
114
115
116
117
118

+5VALW

<16>

EC_MUTE# <31>
USB_ON#
<46>
CHG_MODE0
<45>
USB3_ON#
<45>
TP_CLK <43>
TP_DATA <43>

119
120
126
128

KB9012QF A3 LQFP 128P_14X14

R1564
33K_0402_5%

2
SUSACK#

2 R1571

100
101
102
103
104
105
106
107
108

BRDID

BATT_TEMP <48>
EC_WL_WAKE#
<40>
ADP_I <49,50>

BRDID

10K_0402_5%

83
84
85
86
87
88

R1562
100K_0402_1%

2

SUSACK#

<46>

1

68
70
71
72

LED_KB_PWM_R

<16>
<19>

R1580 1
R276 1

@

ACIN_BUF

2 100P_0402_50V8J
@

2 4.7K_0402_5%

<23>

+3VLP
SYSON
@
R1578
47K_0402_5%
Turbo_V <49>
PROCHOT
<49>
MAINPWON
<49,51>

2 0_0402_5%
2 0_0402_5%

1

@
C1272
0.1U_0402_10V6K

2

EMC Request

BKOFF# <35>
PBTN_OUT# <16>
SUSWARN#
<16>
SA_PGOOD
<53>

WLAN_USB_ON#_R

@
2 R301
1
100K_0402_1%

+3VALW

ACIN <16,23,50>
EC_ON <48,51>
ON/OFF
<43>
LID_SW#
<43>
R1583 2
R1584 1

@

1 0_0402_5%
2 43_0402_1%

SUSP# <10,47,52,54>
PCH_HOT#
<15>
H_PECI
<6,19>

C1270
4.7U_0805_10V4Z
<56>

2

VR_HOT#

VR_HOT#

1 R1579

2

H_PROCHOT#

0_0402_5%

H_PROCHOT#_EC 2
G
Q82
2N7002H_SOT23-3

ECAGND

PN : SA00004OB20

V
V
V

<31>
<43>
<50>

2

2

R1587
100K_0402_5%

1

@
2 R4
10K_0402_5%

1

SUSCLK

BATT_TEMP
EC_WL_WAKE#
ADP_I

SPI Device Interface

EC_TACH

2

10K_0402_5%

EC_VDD/AVCC

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1 R1577

63
64
65
66
75
76

2 0_0402_5%

BEEP#
NOVO#
ACOFF

CPU1.5V_S3_GATE

11
24
35
94
113

1 R1574

PS2 Interface

LED_KB_PWM
BEEP#
NOVO#
ACOFF

1

<46>

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

21
23
26
27

3

KSO[0..17]

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

KBL@
1 R266

1

KSO2

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

VAD_BID
0 V
0.289
0.538
0.875

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSO1

R1570 1
@
2
47K_0402_5%

9
22
33
96
111
125

PWRSHARE_EN#

2

R1568 1
@
2
47K_0402_5%

AD Input

V
V
V

typ

+3VALW

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

V AD_BID
0 V
0.250
0.503
0.819

U51

2

EC_SCI#

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

min

1

<45>

12
13
37
20
38

+EC_VCCA

VAD_BID
0 V
0.216
0.436
0.712

2

+3VALW

<19>

1

CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#

+3VALW

AGND/AGND

C1264
0.1U_0402_16V4Z

1
2
3
4
5
7
8
10

2

C1254
100P_0402_50V8J

2

69

2

47K_0402_5%

GATEA20
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

2

1
C1259

1 R1563

<18> CLK_PCI_EC
<18,33,40> PLT_RST#

2

1
C1261

22P_0402_50V8J

2

1
C1258

10_0402_5%

+3VALW

C1257

CLK_PCI_EC

1

C1256

C1255

2 R1560

1

2

1

<19> GATEA20
<19> KBRST#
<14> SERIRQ
<14,40> LPC_FRAME#
<14,40> LPC_AD3
<14,40> LPC_AD2
<14,40> LPC_AD1
<14,40> LPC_AD0

@

@

2

1

1000P_0402_50V7K

1

1000P_0402_50V7K

ECAGND

1

FBM-11-160808-601-T_0603

C1263 2

1

C1260
1000P_0402_50V7K

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

+3VALW

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

C1262
0.1U_0402_16V4Z
L39

2

3.3V +/- 5%
Vcc
R1562 100K +/- 5%
Board ID
R1564
0
0
8.2K +/- 5%
1
18K +/- 5%
2
33K +/- 5%
3

+3VLP

2

FBM-11-160808-601-T_0603

2

L38

1

+3VALW

D

S

1

<6,49>

C1269
47P_0402_50V8J

2

S IC KB9012QF A3 LQFP 128P KB CONTROLLER

2

R1585
10K_0402_5%

2 R1591

1

LAN_WAKE#

0_0402_5%

S

1

@
Q83
2N7002_SOT23

@

3

LAN_WAKE#

<33>

PCI_PME#

<18>

1 0_0402_5%

PCI_PME#

Compal Secret Data

Security Classification

2
G

EC_PME#

D

R1589 2

+3VALW

Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
ENE_KB9012

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
0.1

LA-8971P

Wednesday, February 15, 2012

Sheet

42

of

58

Power Board Conn.

SW1
SMT1-05_4P

1

+5VALW

@
R61
100K_0402_5%

2

R19
100K_0402_5%

J2 @
2

LED Board Conn.

1

4

1

2

+3VLP +3VALW

JPWR1
8
7

2

3

6
5

1

ON/OFF

R18 2
1
0_0402_5%

6
5
4
3
2
1

SHORT PADS
ON/OFFBTN#
<48>

ON/OFFBTN#

NOVO_BTN#
ON/OFFBTN#
PWR_LED#

GND
GND

+5VALW

6
5
4
3
2
1

+3VALW
JLED1

ACES_88514-00601-071
CONN@

ON/OFF

2
1

ON/OFF

10
9

E-T_6916K-Q08N-00L
CONN@

@
D43
PJSOT24C 3P C/A SOT-23

2

NOVO#

G2
G1

NOVO_BTN#

1

<42>

BATT_LOW_LED#
BATT_CHG_LED#

8
7
6
5
4
3
2
1

2

R5
100K_0402_5%
2

NOVO#

LID_SW#
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#

LID_SW#

NOVO_BTN#
ON/OFFBTN#
3

@
R17
100K_0402_5%

<42>

<42>
<42>

+3VALW
1

1

+3VLP

<42>

8
7
6
5
4
3
2
1

3
PWR_LED#
1
<42>

D

3

D40
DAN202UT106_SC70-3

S

Q19
2N7002_SOT23-3

2
G

PWR_LED

+3VS

C1301
0.1U_0402_16V4Z
JTP1
8
7

1

1

2

2

ACES_88514-00601-071
CONN@
@
C1305
0.1U_0402_10V6K

Blue Tooth Moudle
+3VS

+3VALW

@
C358
0.1U_0402_16V4Z

<19,40>

PCH_BT_ON#

1

1
2

2

BT@
C356
0.1U_0402_16V4Z

@
C612
4.7U_0805_10V4Z

2

BT@
1 R274
2
100K_0402_5%

3

@
C1304
0.1U_0402_10V6K

1

2

2

3

<12,13,15,40>
PCH_SMBCLK
<12,13,15,40>
PCH_SMBDATA
@
D42
PSOT24C_SOT23-3

1

1

C1303

@

100P_0402_50V8J

C1302

2

100P_0402_50V8J

1

6
5
4
3
2
1

G

@

PCH_SMBCLK
PCH_SMBDATA

D

TP_CLK
TP_DATA

TP_CLK
TP_DATA

GND
GND

S

<42>
<42>

6
5
4
3
2
1

1

W=40mils

BT@
Q17
PMV65XP_SOT23-3~D
+3VS_BT_R

2

+3VS_BT

BT@
1 R321
2
0_0603_5%

1

2

BT@
C357
0.1U_0402_16V4Z
JBT1

<18>
<18>

USB20_P9
USB20_N9

USB20_P9
USB20_N9

<40>

BT_ACTIVE

BT_ACTIVE

1
2
3
4
5
6

1
2
3
4
5 G1
6 G2

7
8

ACES_87213-0600G
CONN@

Compal Secret Data

Security Classification
Issued Date

2011/06/15

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

Compal Electronics, Inc.
PWR/LED/TP/BT Conn.
Document Number

Rev
0.1

LA-8971P
Wednesday, February 15, 2012

Sheet

43

of

58

5

4

3

2

1

Close to DDR

REMOTE1+

REMOTE1+

+3VS

E

2

D

U49

1

Under mSSD

REMOTE2+

1
C1212
0.1U_0402_16V4Z

REMOTE2+
1

2

10

EC_SMB_CK2

SMDATA

9

EC_SMB_DA2

ALERT#

8

1

VDD

SMCLK

REMOTE1+

2

DP1

REMOTE1-

3

DN1

REMOTE2+

4

DP2

THERM#

7

REMOTE2-

5

DN2

GND

6

C1213
2200P_0402_50V7K
REMOTE2-

@
2 R1524 1
10K_0402_5%

EC_SMB_CK2

<15,23,42>

EC_SMB_DA2

<15,23,42>

1

C1211
2200P_0402_50V7K
REMOTE1-

2

Q79
MMST3904-7-F_SOT323-3

2
B

REMOTE1-

Close U49

2

C

1

3

@
C1210
100P_0402_50V8J

+3VS

@
C1214
100P_0402_50V8J

C

1

Q80
MMST3904-7-F_SOT323-3

2
B
E

3

D

1

SMSC thermal sensor
placed near by VRAM

2

REMOTE2-

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

EMC1403-2-AIZL-TR_MSOP10

Address 1001_101xb
C

C

FAN Conn

JFAN1

2

2

1

@
D7
BAS16_SOT23-3

Close to Connector

2

C78

1

1000P_0402_50V7K

1

1SS355TE-17_SOD323-2
@
C1215
10U_0603_6.3V6M

5
6

@
D5

C35

2

+FAN1

B

G1
G2

ACES_88266-04001
CONN@

+5VS
1 R1525 2
0_0603_5%

1

1
2
3
4

10U_0805_10V6K

+5VS

1
2
3
4

EC_FAN_PWM
EC_TACH
+FAN1

EC_FAN_PWM
<42> EC_TACH

1

<42>

2

B

A

A

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification
2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EMC-Thermal IC/FAN
Document Number

Date: Wednesday, February 15, 2012

5

4

3

2

Rev
0.1

LA-8971P
Sheet
1

44

of

58

5

4

R285
10K_0402_5%

3

2

1

1 R1605 2
0_0402_5%

+5VALW

U2

USB20_P0

7

USB20_P0

6
5

+5VALW

1

C12
.1U_0402_16V7K

CB

CEN#

TDM
TDP
VDD

DM
DP
GND

Thermal Pad

D

2

U2DN0_L

3

U2DP0_L

+USB3_VCCA

<42>

U2DN0_L
U2DP0_L

1

55584@
R63
0_0402_5%

CHG_MODE1

CHG_MODE1

4

L43 @
1

2

U2DN0_U

2

4

3

U2DP0_U

3

W=80mils

WCM-2012-900T_4P

<42>

1 R1608 2
0_0402_5%

9
55566@
R64
0_0402_5%

SLG55566VTR_TDFN8_2X2

2

PWRSHARE_EN#

+5VALW

20 mil

4

0_0402_5%

C7
0.1U_0402_16V7K

C8

1

1
2

U52

1
2
3
4

2
1 R1609 2
0_0402_5%

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

C14

1

2

C9

<18>

USB20_N0

@
R264

1

1

2

470P_0402_50V7K

USB20_N0

8

SLG55566

<18>

CHG_MODE0

0.1U_0402_16V7K

CHG_MODE0

4.7U_0805_10V4Z

<42>

D

G547I2P81U_MSOP8
U3RXDN1

1

U3RXDP1

<18>

USB3_RX1_N

<18>

USB3_RX1_P

<18>

USB3_TX1_N

<18>

USB3_RX1_N

1

U3RXDN1_R
2 C1
0.1U_0402_16V7K

USB3_RX1_P

1

U3RXDP1_R
2 C2
0.1U_0402_16V7K

USB3_TX1_N

1

U3TXDN1_R
2 C3
0.1U_0402_16V7K

1

U3TXDP1_R
2 C4
0.1U_0402_16V7K

USB3_TX1_P

USB3_TX1_P

4

L44 @
1

2

4
3
WCM-2012-900T_4P

U3RXDN1_L

2
3

U3RXDP1_L

2

U3TXDN1_L

3

U3TXDP1_L

<42>

USB3_ON#

1 R149
2
0_0402_5%

2A/Active Low
USB_OC0#

USB_OC0#

<18,46>

1 R1612 2
0_0402_5%
1 R1613 2
0_0402_5%
U3TXDN1

1

2 C5 U3TXDN1_M
0.1U_0402_16V7K

1

U3TXDP1

1

2 C6 U3TXDP1_M
0.1U_0402_16V7K

4

L45 @
1

2

4
3
WCM-2012-900T_4P

+USB3_VCCA

1 R1616 2
0_0402_5%
1

Place TX AC coupling Cap (C843~C850). Close to connector

+

C13
150U_B2_6.3VM_R35M

C

2

C

W=80mils

U3TXDP1_L

9
1
8
3
7
2
6
4
5

JUSB1
U3TXDN1_L
U2DP0_U

+3VS

2

1

2

1

2

UR1

1
13

+3VS

+3VS

A_EQ1
A_DE0
A_EQ0
A_DE1

15
16
17
18

U3RXDP1
U3RXDN1

19
20

U3TXDP1_R
U3TXDN1_R

9
8

B_DE0

A

EQ
to
EQ
to
EQ
to

for channel
7dB
for channel
14.5dB
for channel
11.5dB

5

B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC

A_INp
A_INn

A_OUTp
A_OUTn

B_INp
B_INn

B_OUTp
B_OUTn

B_DE1

1

+3VS

@
R173
4.99K_0402_1%~D

2
1

R62

1
2 R150

@
4.99K_0402_1%~D

5
7
14
24

PD#
REXT
TEST
I2C_EN

GND
GND
GPAD

B_EQ1
B_DE0
B_EQ0
B_DE1

12
11

U3RXDP1_R
U3RXDN1_R

22
23

U3TXDP1
U3TXDN1

D45 @
U2DP0_U

3

2

I/O2

I/O4

GND

VDD

B

6

10
21
25

1

5

I/O1

I/O3

4

+USB3_VCCA

U2DN0_U

AZC099-04S.R7G_SOT23-6

PS8710BTQFN24GTR-A1_TQFN24_4X4

A_EQ1/B_EQ1

A_EQ0/B_EQ0

A_DE1/B_DE1

A_DE0/B_DE0

(Internal
pull Low)

(Internal
pull Low)

(Internal
pull Low)

(Internal
pull Low)

Low

Low

3.5dB de-emphasis

Low

Low

High

No de-emphasis

Low

High

Low

4
3
2
6

2

2

2

@
R171
4.99K_0402_1%~D

reserved
program
loss up
program
loss up
program
loss up

1

1

1
2

@
R169
4.99K_0402_1%~D

A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC

1
@
R172
4.99K_0402_1%~D
3.3K_0402_1%

@
R167
4.99K_0402_1%~D

VDD
VDD

2

@
R170
4.99K_0402_1%~D

2

A_DE1

2

2

A_DE0

@
R168
4.99K_0402_1%~D

1

1

1

B

@
R166
4.99K_0402_1%~D

10
11
12
13

2

@
R165
4.99K_0402_1%~D

2

+3VS

U3RXDN1_L

1

2

1

1

1

@
R163
4.99K_0402_1%~D

2

1

@
R160
4.99K_0402_1%~D

B_EQ1

1

2

2

B_EQ0

U2DN0_U
U3RXDP1_L

+3VS

C11

@
R154
4.99K_0402_1%~D

+3VS

@
R164
4.99K_0402_1%~D
C10

2

A_EQ1

@
R161
4.99K_0402_1%~D

0.1U_0402_16V7K

@
R157
4.99K_0402_1%~D

0.01U_0402_16V7K

A_EQ0

+3VS

1

+3VS

1

+3VS
@
R151
4.99K_0402_1%~D

SSTX+
VBUS
SSTXD+
GND
DGND
SSRX+
GND
GND
GND
SSRXGND
SANTA_373280-1
CONN@

High

Low

High

High

7dB de-emphasis

High

Low

5dB with boost
output swing

High

High

4

TEST
(Internal
pull Low)
Normal operation
(default)

Low

Test mode enable

High

1

1 U3RXDN1_L

8 9

2

2 U3RXDP1_L

U3TXDN1_L

7 7

4

4 U3TXDN1_L

U3TXDP1_L

6 6

5

5 U3TXDP1_L

3

3

8
YSCLAMP0524P_SLP2510P8-10-9
A

For EMI request

2011/06/15

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

D44 @
910

U3RXDP1_L

Compal Secret Data

Security Classification
Issued Date

U3RXDN1_L

2

Title

Compal Electronics, Inc.
USB3.0 Left Side

Size
Document Number
Custom
Date:

Rev
0.1

LA-8971P

Wednesday, February 15, 2012
1

Sheet

45

of

58

5

4

3

2

1

IO Board

+USB2_VCCB

2

U55
1
2
3
4

2
D

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

C16

1

2

1

C15

1

2

470P_0402_50V7K

C18

1

0.1U_0402_16V7K

W=80mils
C17
0.1U_0402_16V7K

4.7U_0805_10V4Z

+5VALW
+USB2_VCCB
+USB2_VCCC

G547I2P81U_MSOP8
<42>

1 R174
2
0_0402_5%

USB_ON#

USB20_P1
USB20_N1

<18> USB20_P1
<18> USB20_N1

USB20_P3
USB20_N3

<18> USB20_P3
<18> USB20_N3

2A/Active Low
USB_OC0#

USB_OC0#

<18,45>

USB20_P11
USB20_N11

<18> USB20_P11
<18> USB20_N11
+3VS

C1306
0.1U_0402_10V6K

JCR1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
17
18
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

D

GND
GND
ACES_51524-0160N-001
CONN@

+USB2_VCCC

2

U56
1
2
3
4

2
C

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

C20

1

2

1

2

470P_0402_50V7K

1

C19

C22

1

.1U_0402_16V7K

W=80mils
C21
0.1U_0402_16V7K

4.7U_0805_10V4Z

+5VALW

C

G547I2P81U_MSOP8
<42>

1 R176
2
0_0402_5%

USB_ON#

2A/Active Low
USB_OC1#

USB_OC1#

<18>

KB BackLight Connector
JKB2
1
2
3
4

+VCC_KB_LED
1

@
C129
0.1U_0402_16V4Z

B

2

5
6

1
2
3
4

B

GND
GND

KSI[0..7]
KSO[0..17]

JOINT_F1017WR-S-04P
CONN@

KBL@
Q81
PMV65XP_SOT23-3~D
D

S
2

KBL@
1 R265
2
100K_0402_5%

1

G

1

A

2

KBL@
C128
10U_0603_6.3V6M

1

2

KBL@
C126
0.1U_0402_16V4Z

KBL@
C130
0.01U_0402_16V7K

KSO[0..17]

JKB1

<42>
<42>

KSO16

C1277 1

2 @ 100P_0402_50V8J

KSO17

C1278 1

2 @ 100P_0402_50V8J

KSO2

C1275 1

2 @ 100P_0402_50V8J

KSO1

C1279 1

2 @ 100P_0402_50V8J

KSO15

C1280 1

2 @ 100P_0402_50V8J

KSO7

C1276 1

2 @ 100P_0402_50V8J

KSO6

C1281 1

2 @ 100P_0402_50V8J

KSI2

C1282 1

2 @ 100P_0402_50V8J

KSO8

C1283 1

2 @ 100P_0402_50V8J

KSO5

C1284 1

2 @ 100P_0402_50V8J

KSO13

C1285 1

2 @ 100P_0402_50V8J

KSI3

C1286 1

2 @ 100P_0402_50V8J

KSO12

C1287 1

2 @ 100P_0402_50V8J

KSO14

C1288 1

2 @ 100P_0402_50V8J

KSO11

C1289 1

2 @ 100P_0402_50V8J

KSI7

C1290 1

2 @ 100P_0402_50V8J

KSO10

C1291 1

2 @ 100P_0402_50V8J

KSI6

C1292 1

2 @ 100P_0402_50V8J

KSO3

C1293 1

2 @ 100P_0402_50V8J

KSI5

C1294 1

2 @ 100P_0402_50V8J

KSO4

C1295 1

2 @ 100P_0402_50V8J

KSI4

C1296 1

2 @ 100P_0402_50V8J

KSI0

C1297 1

2 @ 100P_0402_50V8J

KSO9

C1298 1

2 @ 100P_0402_50V8J

KSO0

C1299 1

2 @ 100P_0402_50V8J

KSI1

C1300 1

2 @ 100P_0402_50V8J

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17

KBL@
Q87
DTC124EKAT146_SC59-3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND
GND

31
32

A

TYCO_3-2041084-0
CONN@

2

@
R269
100K_0402_5%

IN

3

LED_KB_PWM_R

2
1

<42>

LED_KB_PWM_R

GND

OUT

1

2

3

1

KBL@
R268
10K_0402_5%

+VCC_KB_LED

2

+5VS

1

+5VALW

KSI[0..7]

Compal Secret Data

Security Classification
2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

KB & IO Board Conn
Rev
0.1

LA-8971P

Thursday, February 16, 2012

Sheet
1

46

of

58

A

B

C

D

E

+5VALW TO +5VS

+5VALW

+3VALW TO +3VS

+5VS
+3VALW

+3VS

U53
DMN3030LSS-13_SOP8L-8

1
@
R1618
470_0603_5%

1 2

C1318

2

1U_0603_10V4Z

C1317

10U_0603_6.3V6M

4

C1316

1

2

1

D

2 SUSP
G
@
Q86
2N7002_SOT23

S

D

S

1

2
SUSP

Q89
2N7002_SOT23

2
G

1

@
R1623
0_0402_5%

2

2

3

C1322
0.01U_0603_50V7K

2

S

1

1

Q88
2N7002_SOT23

1

R1621
470K_0402_1%

3

D

2
G

SUSP
2
G
@
Q85
2N7002_SOT23

1

1
2
3

3

3

2
1
SUSP

2
+VSB

S

2 R1622 1 5VS_GATE_R
82K_0402_5%

5VS_GATE

1

D

R1620
150K_0402_5%

8
7
6
5

10U_0603_6.3V6M

1
2

2

@
R1617
470_0603_5%

1

1
C1315

2

1U_0603_10V4Z

1
C1314

1

2

4

1

+VSB

U54
DMN3030LSS-13_SOP8L-8

1
2
3

10U_0603_6.3V6M

8
7
6
5

10U_0603_6.3V6M

C1313

1

C1323
0.01U_0603_50V7K

2

2

@
R1628
470_0603_5%

2

2

D

D

1

D

2 SYSON#
G
@
Q93
2N7002_SOT23

S

Q92 @
2N7002_SOT23

S

2 SUSP
G
@
Q94
2N7002_SOT23

@

2 R1630

1

CPU1.5V_S3_GATE

0_0402_5%

+1.5V to +1.5VS

<10,42>

SUSP

2
S

3

3

SUSP

3

2
G
S

3

D

1

2
1

R1629
22_0603_5%

2

@
R1627
470_0603_5%

1

@
R1626
470_0603_5%

1

+0.75VS

1

+1.05VS_VTT

1

+1.5V

1

+1.8VS

G
Q95
2N7002_SOT23
+1.5V_CPU_VDDQ

+1.5V
Q91
PMV65XP_SOT23-3~D

+1.5VS

J3
D

S

@
R1639
100K_0402_5%

SYSON

2

1
2
1
3

C1329

1

2

0.1U_0603_25V7K

C1328

1

2

0.1U_0603_25V7K

1

Q98
2N7002_SOT23

OUT
IN

C1327

2
S

2
G

GND

1
OUT

SYSON

1.5VS_GATE

4

2

4

<42,52>

IN

1

1

2

3

2

SUSP#

D

3

SUSP#

@
Q100
DTC124EKAT146_SC59-3

SUSP
2
G
@
Q96
2N7002_SOT23

0_0402_5%

SYSON#

GND

SUSP#

1

<10,42,52,54>

1

3

R1631
470_0603_5%
@

D

S

2 R1635

SUSP

Q99
DTC124EKAT146_SC59-3

2

2
PAD-OPEN 4x4m

3

SUSP

2

2
<6,10,52>

@
R1638
100K_0402_5%

@
R1637
100K_0402_5%

R1636
220K_0402_5%

2

1

1U_0603_10V4Z

2

1

R1633
100K_0402_5%

1

+5VALW

1

+5VALW
+RTCVCC

@

1

C1326

C1325

2

1

+3VALW

1

G

3

10U_0603_6.3V6M

3
1

10U_0603_6.3V6M

For Intel S3 Power Reduction.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DC Interface
Rev
0.1

LA-8971P
Sheet

Wednesday, February 15, 2012
E

47

of

58

5

4

3

2

1

VIN

ACES_50305-00441-001


1
2

1

PC4
1000P_0402_50V7K

1
2

+

2

2
1

D

PC3
100P_0402_50V8J

3

1

+

PL1
SMB3025500YA_2P
1
2

2

4

PC2
100P_0402_50V8J

-

PC1
1000P_0402_50V7K

PF1
7A_24VDC_429007.WRML
1
2 APDIN1

PAJ1

D

+3VLP

2

1

PR2
560_0603_5%
1
2

PR3
560_0603_5%
1
2

@ MAXEL_ML1220T10

PD1
RB751V-40_SOD323-2
2
1

1

PR1
0_0402_5%
+RTCBATT

1

+

JRTC1

2

+CHGRTC

-

2

RTCVREF

PD2
RB751V-40_SOD323-2

C

C

RTC Battery

Add battery reset circuit 2012/01/15 Wenwen
PJ401
BA

1

change PBJ1 2012/01/19 Wenwen
VMB

<42,50>

EC_SMB_DA1

<42,50>

2
PR213
1

+3VALW

BATT_TEMP <42>

B

PD303

EC_ON

<42,51>
1

PR214
2

2
G
PQ40

10K_0402_5%

BATT_RST

1

2
D

3

1
2
PR10
6.49K_0402_1%
1
2
PR14
10K_0402_5%

S

PC609
1500P_0402_50V7K

1

PC601
0.022U_0402_25V7K

2

0.01U_0402_25V7K
PC6

2

EC_SMB_CK1

BATT+

1

1
2
PR606
47K_0402_1%

PC5
1000P_0402_50V7K

A/D

B

8
7
6
5
4

1
2
3

1

1
2

2
1
PR5
100_0402_1%

PQ39
AO4423_SO8

PL2
SMB3025500YA_2P
1
2

2N7002KW_SOT323-3

ACES_50299-01001-001

2
1
PR4
100_0402_1%

10
9
8
7
6
5
4
3
2
1

10
9
8
7
6
5
4
3
2
1

2

PF2
12A_65V_451012MRL
1
2

JUMP_43X118
2
2

10K_0402_1%

VMB2
PBJ1

1

1

ON/OFFBTN#

<43>

RB751V-40_SOD323-2

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.
PWR DCIN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

C38-G series Chief River Schematic0.1

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

48

of

58

5

4

3

2

1

ADP_I need to write Charge Options Register (0x12H)=> bit6=1
0: IOUT is the 20x current amplifier output 
1: IOUT is the 40x current amplifier output
For KB930 --> Keep PU201 circuit
(Vth = 1.25V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205, PR211,PQ201,PR208,PR212

PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

D

D

VL

PROCHOT

OT2 RHYST2

5

1

PR17
2

1

@ PR13
0_0402_5%
1

@ PR15
0_0402_5%

10K_0402_1%

PR16

2

2

27.4K_0402_1%

G718TM1U_SOT23-8

PR18
2

1

@ 47K_0402_1%
2

1

MAINPWON

<42,51>

1
PR9
10K_0402_1%

2

ADP_OCP_2 1

2

4

2

+3VLP

Turbo_V_2
PR12

1

6

2

OT1 TMSNS2

3

NTC_V_2

OTP_N_002

0_0402_5%

Turbo_V

<42>

PR20 0_0402_5%
C

90W(DIS) : PR205=4.42K
PR210=27.4K
65W(UMA) : PR205=402(SD034020080)
PR210=5.11K

PR21
2

1

PH1
100K_0402_1%_NCP15WF104F03RC

<42>

PR19
0_0402_5%
1
2
@

7

1

3

2 ADP_OCP_1
G
S SSM3K7002FU_SC70-3

8

GND RHYST1

@

1

PQ1

1

D

VCC TMSNS1

2

OTP_N_003

2
1

H_PROCHOT#

100K_0402_1%

2
PR11

<6,42>

PU1
1

2
1
PR7
12.7K_0402_1%

PR6
4.42K_0402_1%

1

+3VS

PC7
0.1U_0603_16V7K

2

ADP_I

2
1
PR8
21.5K_0402_1%

+3VLP
<42,50>

C

+3VALW

<42>

NTC_V

47K_0402_1%

PQ2
TP0610K-T1-E3_SOT23-3

3

PR29
22K_0402_1%
1
2

1
2

PC10
0.1U_0603_25V7K

2

1
2

+VSBP

B

2

VL

1

PC9
0.22U_0603_25V7K

B

2
1
PR27
100K_0402_1%

B+

1

VSBP_EN

2 PR36
1
0_0402_5%

2

<42>

1

@
PR34 1
2
0_0402_5%

1

SPOK

D

S

PQ5
2N7002W-T/R7_SOT323-3

2
G

PC11
1U_0402_6.3V6K

PR35
1K_0402_5%
2

1
<51>

3

@
PR30
100K_0402_1%

PJ1
@ JUMP_43X39
1
2
1
2

+VSBP

+VSB

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.
PWR VSBP/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

C38-G series Chief River Schematic0.1

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

49

of

58

5

4

3

2

1

B+

P3
P2
PQ6
AO4407A_SO8

DISCHG_G

20

PHASE

19

HIDRV

18

BTST

17

2

3
2
1
4

1

2

1
2

1

15

14

PR63
10_0603_5%

13
1
2

11

6.8_0603_5%
1 12
PR62

RB751V-40_SOD323-2

2

1
3

BATT+

CHG
1

4

2

3

5
6
7
8
PR60
PC27
2.2_0603_5%
0.047U_0603_16V7M
1
2
2
1

PC29
1U_0603_25V6K

2

BQ24727VDD

DL_CHG

PR57
4.7_1206_5%

16

2

BM

1

DH_CHG

PD5
REGN

C

PL4
10UH_PCMB063T-100MS_4A_20%
PR55
0.01_1206_1%

16251_SN
2

PR61
100K_0402_1%

1U_0603_25V6K

BST_CHG

PACIN

2

LX_CHG

SA000051W00

2
G
S

SRP

SRN

PC30
680P_0603_50V7K

ILIM

2

5
6
7
8
4

PC26
BQ24727VCC 1

2N7002W-T/R7_SOT323-3

PC28
10U_0805_25V6K
2
1

VCC

D

PC31
10U_0805_25V6K
2
1

21

1

TP

PQ15
AO4466L_SO8

1
ACN

2
ACP

3

CMPIN

CMPOUT



PQ17
AO4466L_SO8

SCL

1

PD3

1DISCHG_G-1
1

1

1

PU3
SDA
BQ24727RGRR_VQFN20_3P5X3P5

10

PD4
1SS355_SOD323-2
2
PQ14

P2

IOUT

9

1

PC23
0.1U_0603_25V7K
2
1

PR46
2
1
10K_0603_1%

2

3
2
1

PR59
1
2
316K_0402_1%

4

5

100P_0603_50V8
8

+3VALW

1

LODRV

EC_SMB_CK1

2

GND

EC_SMB_DA1

<42,48>

7

PR42
200K_0402_1%

PC22

SRP

<42,48>

PC25
1
2

ACDET

SRN

PR56
1
2ACOFF-12
10K_0402_5%

100K_0402_1%

PR45
2
2
PR51 @
10K_0402_5%

ACOK

2
1

6

PQ11
DTC115EUA_SC70-3

0.1U_0603_25V7K

39.2K_0402_1%

ADP_I

PC24
0.1U_0603_25V7K

2

0.1U_0603_25V7K

PR48
@
@
1
2
4.7M_0603_1%

1

1

PR50 @
10K_0402_5%
1
2

1
PR49

@ PR47
2

1

ACOFF

<42,49>

3

<42>

1

PQ16
DTC115EUA_SC70-3

PR54
64.9K_0603_1%
1
2

2

5

ACON

390K_0603_1%

1
2
P2-2
3

PQ12B

PR52
47K_0402_1%
1
2

PACIN

4

PACIN

@
VIN

2N7002KDW-2N_SOT363-6

1
C

PR44
150K_0402_1%

6
PQ12A
2N7002KDW-2N_SOT363-6

2

2

PR53
10_1206_5%
2

3

1

ACPRN

PC21

1

+3VALW

DTC115EUA_SC70-3

PC20

3

+3VALW

0.1U_0603_25V7K

1

P2-1

PR41
10K_0402_1%

2ACOFF-1

VIN

2
1

ACP

PQ10

D

PR40
47K_0402_1%
1
2

ACN

2

8
7
6
5
4

1
2
3

PC17
2200P_0402_50V7K

PC16
4.7U_0805_25V6-K
1
2

2
1

2
1

PC19
4.7U_0805_25V6-K
1
2

PL3
1UH_PCMB061H-1R0MS_7A_20%

2

3

1

2

1

2

PC15
4.7U_0805_25V6-K
1
2

1

PC12
5600P_0402_25V7K

2

1

2

PC18
0.1U_0603_25V7K
2
1
PR39
200K_0402_1%

2

3

1
PR38
47K_0402_5%
2

DTA144EUA_SC70-3

PQ8
AO4407A_SO8

4

PQ9

D

CHG_B+

SH00000AA00

1

1SS355_SOD323-2

PR37
0.01_1206_1%

8
7
6
5

PC14
@ 10U_0805_25V6K

1
2
3

4

1
2
3

4

8
7
6
5

PC13
@ 10U_0805_25V6K

VIN

PQ7
AO4423_SO8

PC32
2
1

B

B

0.1U_0603_25V7K

CHGVADJ
0V

PC34
0.1U_0603_25V7K

2

4V

2

Vcell

1

1

CHGVADJ=(Vcell-4)/0.10627

4.2V

1.882V

4.35V

3.2935V

@
PC33
0.1U_0603_25V7K

BQ24727VDD
PR65
10K_0402_1%
1
2

1

1

CC=0.25A~3A
IREF=1.016*Icharge

PR66
10K_0402_1%

PR64
47K_0402_1%

D

3
A

<16,23,42>

S

1
PR67
2

PQ19
2
G

2N7002KW_SOT323-3

ACPRN

ACIN

PACIN

2

2

VCHLIM need over 95mV

1

IREF=0.254V~3.048V

12K_0402_1%

A

For disable pre-charge circuit.

Compal Secret Data

Security Classification
2010/01/25

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
PWR CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

50

of

58

Rev
0.1

5

4

3

2

1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

PC35
1U_0603_10V6K

2VREF_8205

Change PJ2 to PL16
2012/02/14 Wenwen
RT8205_B+
PL16
HCB2012KF-121T50_0805

PR71
19.6K_0402_1%
1
2

5
6
7
8

PC43
0.1U_0603_25V7K
2
1

3
2
1

PC53
4.7U_0805_10V6K

1
2
1
2
PC54
0.1U_0603_25V7K

2
3
2
1

TPC8A03-H_SO8

PC52
1U_0603_10V6K
2
1

Typ: 175mA

+5VALWP

1
+

1

4

VL

RT8205_B+

TPC8065-H_SO8

PQ21

RT8205EGQW_WQFN24_4X4

18

17

16

15

13

1

LG_5V

PR77
4.7_1206_5%

19

2

LGATE1

PC50
680P_0603_50V7K

LGATE2

C

PL6
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2

5
6
7
8

12

NC

LX_5V

VREG5

UG_5V

20

VIN

21

PHASE1

GND

UGATE1

PHASE2
SKIPSEL

UGATE2

11

PQ23

VFB=2.0V

10

PC51
150U_B2_6.3VM_R45M

2

B

PJ4

2
+5VALWP

@

2

1

1

JUMP_43X118

+5VALW

PR80
100K_0402_1%
2
1

PR81
2.2K_0402_5%
2
1

1

+3.3VALWP OCP(min)=5.81A
+5VALWP OCP(min)=8.44A

PQ25
DTC115EUA_SC70-3

PC55
4.7U_0603_6.3V6M

2

A

3

1

2
2
1
PR83
40.2K_0402_1%

<42,49> MAINPWON

PC42
2200P_0402_50V7K
2
1

PR75
PC47
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

2VREF_8205

5

1

2

PR82
0_0402_5%
2
1
A

PC41
4.7U_0805_25V6-K
2
1

22

PQ24B
2N7002KDW-2N_SOT363-6

VL

<42,48> EC_ON

PC45
4.7U_0805_25V6-K
2
1

ENTRIP1

1

3

2
FB1

4

23

BOOT1

1
2

3

+3VALW

PQ24A
2N7002KDW-2N_SOT363-6

REF

FB2

PGOOD

BOOT2

4

@ JUMP_43X118

ENTRIP2

6

+3VALWP

VREG3

PR78
499K_0402_1%
1
2

ENTRIP1

1

1

9

SPOK <49>

B+

PJ3

2

8

4
24

4

1
2
3

2

2

RT8205_B+

VO1

EN

PQ22
AO4712_SO8

PC48
150U_B2_6.3VM_R45M

PC49
680P_0603_50V7K
2
1

+

LG_3V

PR79
100K_0402_1%

1

8
7
6
5

PR76
4.7_1206_5%
2
1

+3VALWP

PL5
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2

VO2

14

1
2
3

PR74
2 1
2 BST_3V
2.2_0603_5%
PC46
UG_3V
0.1U_0603_25V7K
LX_3V

7

PR73
66.5K_0402_1%
2

ENTRIP1

4

1

ENTRIP2

6

P PAD

TONSEL

25

ENTRIP2

PU4

1

5

PR72
130K_0402_1%
1
2

1

PQ20
AO4466L_SO8

B

1

PR70
20K_0402_1%
1
2

2

PC44
4.7U_0805_10V6K

8
7
6
5

PC40
2200P_0402_50V7K
2
1

PC38
4.7U_0805_25V6-K
2
1

C

PR69
30K_0402_1%
1
2

+3VLP

2
PC39
4.7U_0805_25V6-K
2
1

1

PR68
13K_0402_1%
1
2

Typ: 175mA

PC37
0.1U_0603_25V7K
2
1

PC36
0.1U_0603_25V7K
2
1

B+

D

2

D

Compal Secret Data

Security Classification
2010/01/25

Issued Date

@

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
PWR 3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

51

of

58

Rev
0.1

A

Hi

Hi

On

On

S3

Lo

Hi

On

On

Lo

Lo

Off

Off

S4/S5

PL18
HCB1608KF-121T30_0603
1
2

1.5V_B+

1

On
Off
(Hi-Z)
+1.5VP

Off

PQ26
TPCA8065-H_PPAK56-8-5

1

UG_1.5V
PJ6 @
JUMP_43X39

1

Note: S3 - sleep ; S5 - power off

1

S0

0.75VSP

PC57
4.7U_0805_25V6-K

VTT_REFP

2

1.5VP

2

S5

D

PC56
4.7U_0805_25V6-K

S3

C

5

STATE

B

B+

Change PJ5 to PL18
2012/02/14 Wenwen

1

4

2

3
2
1

1

LX_1.5V

2

PR84
PC58
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2

BST_1.5V

<10,42,47,54> SUSP#

2
1
2

PQ27
TPCA8057-H_PPAK56-8-5

5
3
2
1

17

16
PGOOD

2

2
1
PR87
5.1_0603_5%

11

+3VALW

10

S5

TON
9

VDD

+5VALW

1

BOOT

19
S3

12

PC61
330U_D2_2.5VY_R15M

PC65
1U_0603_10V6K

PGOOD_1.5V

1

PJ7
2

2

@

2
3

VDDP

PR86
11K_0402_1%
2
1

PR92
5.9K_0402_1%
2
1
1

D

PR93
5.76K_0402_1%

<6,10,47> SUSP

CS

+
2

PC62 @
680P_0402_50V7K

S

FB=0.75V
To GND = 1.5V
To VDD = 1.8V

1

1

JUMP_43X118
PJ8

+1.5VP

2

+1.5V

2

@

1

1

JUMP_43X118

2

PQ28 @
2N7002KW_SOT323-3
2
G

14
13

1

PR91
887K_0402_1%
2
1 1.5V_B+

@ PC67
0.1U_0402_16V7K
1

2

1

<42,47> SYSON

PGND

4

PR85 @
4.7_1206_5%

@

PR90
0_0402_5%
1
2
PC66
1U_0402_16V6K

+1.5VP

1

PR89
0_0402_5%
1
2

8

VDDQ

7

VTTREF

5

S5_1.5V

4

FB

2

PC63
0.033U_0402_16V7K

RT8207MZQW_WQFN20_3X3

6

1

+1.5VP

GND

S3_1.5V

+VTT_REFP
2

18

VTTSNS

3

2

2

LGATE



LG_1.5V

15

2
1
PR88
10K_0402_5%
PC64
1U_0603_10V6K
2
1

VTTGND



PHASE

1

UGATE

PAD

VLDOIN

20

PU5
21

VTT

1

PC60
10U_0805_25V6K

2

1
2

PC59
10U_0805_25V6K

+0.75VSP

PL7
1UH_PCMC063T-1R0MN_11A_20%
1
2

PJ9

1

2

PR97
1M_0402_5%

1
2

1

PC71
22U_0805_6.3VAM

2
SY8033BDBC_DFN10_3X3

2

FB=0.6Volt

PR95
20K_0402_1%

PC69
68P_0402_50V8J
2
1

6

1

1

+0.75VS

JUMP_43X118

3

+1.8VSP

PC70
22U_0805_6.3VAM

1

2

0_0402_5%

NC

TP

EN_1.8VSP
PC73 @
0.1U_0402_10V7K

2

11

PR96
1

7

<10,42,47,54> SUSP#

FB

1

EN

2

SVIN

5

3

PL8
1UH_PH041H-1R0MS_3.8A_20%
1
2

PJ11
+1.8VSP

2

2

@

1

+1.8VS

1

JUMP_43X118

1.8VSP_FB

1.8VSP max current=4A

1

8

LX

1.8VSP_LX

PC72
PR94
680P_0603_50V7K 4.7_1206_5%

PVIN

2

1

9

LX

1 2

PVIN

NC

10

2

PC68
22U_0805_6.3VAM

4

PU6
1.8VSP_VIN

PG

PL17
HCB1608KF-121T30_0603
1
2

1

+3VALW

2

@

1

3

2

+0.75VSP

Change PJ10 to PL17
2012/02/14 Wenwen

2

PR98
10K_0402_1%
4

4

Compal Secret Data

Security Classification
Issued Date

2010/01/25

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
PWR 1.5VP/1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

A

B

C

Wednesday, February 15, 2012
D

Sheet

52

of

58

Rev
0.1

5

4

3

+3VS

PR99
1K_0402_5%
2
1

PR100
100K_0402_5%
1

Add PC610 PC611 for VID issue on ULV
2012/01/15 Wenwen

2

H_VCCSA_VID1

1

VID [0]
0
0
1
1

<10>

PC610
0.033U_0402_16V7K

VID[1]
0
1
0
1

VCCSA Vout
0.9V
0.85V
0.775V
0.75V

D

output voltage adjustable network

1

2

PR103
0_0402_5%
1
2

+V1.05S_VCCP_PWRGOOD

12

+VCCSA_BT 1

11

+VCCSA_PHASE

PR104
PC76
0_0603_5%
0.22U_0603_16V7K
2+VCCSA_BT_1 1
2
PL9
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

24

7

PC84
22U_0805_6.3V6M
1
2

@

PC83
22U_0805_6.3V6M
1
2

PC82
2200P_0402_50V7K
2
1

PC81
22U_0805_6.3V6M
1
2

PC80
22U_0805_6.3V6M
1
2

PC89
1000P_0603_50V7K

@

@

2

SW

@

PC79
0.1U_0402_10V7K
2
1

8

VIN

PC78
22U_0805_6.3V6M
1
2

2

9

1

SW

TP

6

COMP
3

GND

VREF
2

1

MODE

VIN

HCB1608KF-121T30_0603

VOUT

+VCCSA_PWR_SRC

SW

VIN

23

1

PR105
4.7_1206_5%

PC77
22U_0805_6.3V6M
1
2

1
TPS51463RGER_QFN24_4X4
22

2

10

PGND

SLEW

10U_0805_6.3V6M
PC88

2
1

1

21

5

2

2

SW

+VCCSAP
C

PGND

4

1

2

+VCCSA_PWR_SRC

10U_0805_6.3V6M
PC87

PL20

+3VALW

1

0.1U_0603_25V7K
PC86

2200P_0402_50V7K
PC85

Change PJ12 to PL20
2012/02/14 Wenwen

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

<54>

13
EN

14

BST
SW

20

C

+VCCSA_VID0

+VCCSA_VID1
15

PGND

<10>

PC611 @
0.033U_0402_16V7K

+VCCSA_EN

VID0

1
17

19

V5FILT

V5DRV

PU7

PGOOD

PC75
2.2U_0603_10V7K
1
2

VID1

PR102
10_0402_1%
2
1

18

2

+VCCSA_PWRGD

+5VALW

H_VCCSA_VID0
PR101
1K_0402_5%
2
1

PC74
1U_0603_10V6K

SA_PGOOD

16

<42>

+VCCSA_PWRGD

2

1

D

2

25

@

PR106
2

1

33K_0402_5%
PR107
100_0402_5%
2
1
2

1

2

1

PR108
5.1K_0402_1%

PR110
0_0402_5%
2
1

PR109
@ 0_0402_5%

VCCSA_SENSE

<10>

2

PC91
3300P_0402_50V7K

1

0.22U_0402_10V6K

PC92
0.01U_0402_25V7K
1
2

PC90
2
1

B

B

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

+VCCSAP

PJ13
2
@

2

1

+VCCSA

1

JUMP_43X118

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR VCCSAP
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

C38-G series Chief River Schematic
Wednesday, February 15, 2012
1

Sheet

53

of

58

Rev
0.1

5

4

3

2

1

D

D

EN

DL

10

DH_1.05VS_VCCP

TPS51219RTER_QFN16_3X3

TPCA8057-H_PPAK56-8-5

2
10_0402_5%
@

2

2

1

8

7

2

PC104
1U_0603_10V6K

1
2

3
2
1

TRIP
6

0.01UF_0402_25V7K

10_0402_1%

1

+5VALW

2

1

1

5

PC103

2

9

PGND

V5
GND

VSNS
COMP

VCCIO_SENSE

PC98
4.7U_0805_25V6-K
2
1

PC95
4.7U_0805_25V6-K
2
1

PC94
0.1U_0402_25V6
2
1

PQ30
DL_1.05VS_VCCP

PR123
75K_0402_1%
2
1

<9>

5
3
2
1

MODE

PGOOD

BST

11

PL10
S COIL 1UH +-20% PCMB063T-1R0MS
1
2

4

PR121

Change PJ14 to PL19
2012/02/14 Wenwen

C

+1.05VS_VTTP

PC101
330U_X_2VM_R9M

GSNS

DH

LX_1.05VS_VCCP

1

3

12

5

REFIN

PC100
0.01UF_0402_25V7K

1

PC97
2200P_0402_50V7K
2
1

13

15

14

17

16

PAD
2

2

SW

0_0402_5%

PR122

B+

4

VREF

4

PL19
HCB1608KF-121T30_0603
2
1

PC102
PR119
1000P_0603_50V7K 4.7_1206_5%

2

12K_0402_1%

1

10.7K_0402_1%
PR117
2

1
1

PC96
0.1U_0603_25V7K
1
2

1.05VS_B+

1

VSSIO_SENSE_L

1

1

PR120
<9>

PR118
2

PC99
0.1U_0402_25V6
2
1

C

PU8

PQ29
TPCA8065-H_PPAK56-8-5

PR116
2.2_0603_5%
BST_1.05VS_VCCP
1
2

1

PR114
2

100K_0402_1%

PR113
100K_0402_1%
2

1
2

PR115
0_0402_5%
1
2

+V1.05S_VCCP_PWRGOOD

+1.05VS_VTT OCP(min)=20.75A

+3VS

PC93
.1U_0402_16V7K

2
PR112

1
<53>

@ 10K_0402_1%

PR111
60.4K_0402_1%
1
2

<10,42,47,52> SUSP#

1
+

2

PC105
1000P_0402_50V7K
PR124

B

1

B

2

1

2

10_0402_1%
PC106
1000P_0402_50V7K

PJ15

2

2

1

1

@
+1.05VS_VTTP

JUMP_43X118
PJ16
2 2
1 1

@

+1.05VS_VTT

JUMP_43X118

A

A

Compal Secret Data

Security Classification
2010/01/25

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
PWR 1.05VS_VTT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

54

of

58

Rev
0.1

A

B

<23>

Change PQ31 from TPCA8065 TO MDU1516
Change PQ32 from TPCA8057-H to MDU1511
+VGA_B+
2012/02/06 Wenwen

<23>

OPT@ PL11
HCB2012KF-121T50_0805

22

3211_DRVH

1

21

3211_SW

PR134
0_0603_5%

33

1

+VGA_CORE

OPT@

1
2

OPT@ PC112
0.1U_0402_25V6

1
2

OPT@ PC111
2200P_0402_50V7K

2

1

OPT@ PC110
4.7U_0805_25V6M

2

@ PU10
1
VCC TMSNS1

8

2

7

1
GND RHYST1

3

2 @

<42>

PWR_GPS_DOWN#

4

OT1 TMSNS2
OT2 RHYST2

@

1
2
@ PR153
15.8K_0402_1%

5

PH3

2

PC149
4.7U_0603_6.3V6M

@

1

VL

@

4

@

Compal Secret Data

Security Classification

OPT@

Issued Date

2010/01/25

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

B

C

Compal Electronics, Inc.
PWR VGA_CORE

Size
C
Date:

A

@

6

G718TM1U_SOT23-8

@

2

2

1

PC142
22U_0805_6.3V6M

2 @

PC147
4.7U_0603_6.3V6M
2
1

PC141
22U_0805_6.3V6M

1

OPT@ PC146
4.7U_0603_6.3V6M
2
1

OPT@ PC140
22U_0805_6.3V6M

2

OPT@ PC144
4.7U_0603_6.3V6M
2
1

OPT@ PC139
22U_0805_6.3V6M

OPT@ PC138
22U_0805_6.3V6M

1

OPT@ PC143
4.7U_0603_6.3V6M
2
1

1

2

1

@ PH2
100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC

@ PC129
0.1U_0603_25V7K

2

@ PR148
19.6K_0402_1%

1

1

VL

PR152
3.48K_0402_1%

2

2

+

PR151
8.66K_0402_1%

2

1

1

+

Add PC502 for NV GPU Spec request
2012/02/03 Wenwen

PC162
0.1U_0402_10V7K

@

OPT@ PC502
47U_0805_6.3V6M

2

@

1

2

3211_CSCOMP

PC137
4.7U_0603_6.3V6M

PC136
4.7U_0603_6.3V6M
2
1

2

OPT@

PC161
0.1U_0402_10V7K
2
1

PC160
0.1U_0402_10V7K
2
1

PC159
0.1U_0402_10V7K
2
1

PC158
0.1U_0402_10V7K
2
1

PC157
0.1U_0402_10V7K
2
1

PC156
0.1U_0402_10V7K
2
1

OPT@

@

1

2

2

1

OPT@

@

MDU1516URH_POWERDFN56-8-5

3

1

1

@

2

Near VGA Core

OPT@ PC127
330U_D2_2V_Y

PC125 OPT@
1000P_0402_50V7K

PC154
4.7U_0603_6.3V6M

@

OPT@

PC152
4.7U_0603_6.3V6M
2
1

PC153
4.7U_0603_6.3V6M
2
1

PC151
4.7U_0603_6.3V6M
2
1

PC150
4.7U_0603_6.3V6M
2
1

PC148
4.7U_0603_6.3V6M
2
1

@

OPT@

+
2

@ PC121
680P_0603_50V7K

1

2
OPT@

@

OPT@

1

PR150 OPT@
0_0402_5%

PC135
4.7U_0603_6.3V6M
2
1

PC134
4.7U_0603_6.3V6M
2
1

PC133
4.7U_0603_6.3V6M
2
1

PC132
4.7U_0603_6.3V6M
2
1

PC131
4.7U_0603_6.3V6M
2
1

1

PC130
4.7U_0603_6.3V6M
2
1

2
1

PC145
4.7U_0603_6.3V6M
2
1

2
2

1

OPT@

PC155
0.1U_0402_10V7K
2
1

4

OPT@

+VGA_CORE

PR146 OPT@
143K_0603_1%

1
OPT@

3

2

2

PR149 @
0_0402_5%
2
1

OPT@

4

2

220K_0402_1%
PR145 OPT@

+

OPT@

4

1

1

2

PC123 OPT@
1000P_0402_50V7K

1

Shortest the
net trace

Under VGA Chip

1

1
4

@
PR135
4.7_1206_5%

1

17

PC122 @
560P_0402_50V7K

2

3

+VGA_CORE

2

5
5

5

1

OPT@ PC117
2.2U_0603_10V6K

18

PQ42
OPT@

2

2

PQ32
OPT@

MDU1511RH_POWERDFN56-8-5

19

+5VS
3211_DRVL

OPT@ PC126
330U_D2_2V_Y

OPT@ PC124
1000P_0402_50V7K

Change PL12 from SH00000IK00 TO SH00000IN00
2012/02/07 Wenwen
PL12
0.36UH_FDU1040J-H-R36M=P3_33A_20%

3
2
1

20

3211_RAMP-1

Connect to input caps

1

Add PQ41,PQ42 for heavy load (EDP Continuous current)
2012/02/10 Wenwen

2

16

15

14

13

12
3211_RAMP

OPT@ PR147
1K_0402_1%
2
1

4

3
2
1

OPT@ PR133
OPT@ PC114
0_0603_5%
0.22U_0603_25V7K
23 GPU_BOOST 1
2GPU_BOOST-1
1
2

24

PQ41
OPT@

MDU1511RH_POWERDFN56-8-5

AGND

1

2

<26>

<27>

VGA_VCCSENSE

VGA_VSSSENSE

+VGA_B+

1

OPT@

2

OPT@

OPT@ PC109
4.7U_0805_25V6M

1
2

3
2
1

CSCOMP

AGND

2
1
PR143 OPT@
422K_0402_1%

11
3211_RT

9

PR141 OPT@
300K_0402_1%
2
1

10

3211_RPM
237K_0402_1%~N
PR140 OPT@
2
1

1

OPT@ PR139
80.6K_0402_1%
3211_IREF
1
2

3211_CSCOMP

2

2

PR144
0_0402_5%
1

PR142
0_0402_5%

B+

3211_CSCOMP

Avoid high dV/dt

3211_CSFB

2

PR138 OPT@
3.4K_0402_1%

OPT@ PC108
4700P_0402_25V7K

2
MDU1516URH_POWERDFN56-8-5

5
4

3
2
1

3211_VCC

PQ31
OPT@

PC113 OPT@
1U_0603_16V6K

1

CSFB

ILIM

PR137 OPT@
20K_0402_1%

2

2
1

2
0_0402_5%
VID6
VID6

25

VID5
26
VID5

VID4
27
VID4

VID3
28
VID3

29
VID2

PGND
GPU

3211_ILIM 8

OPT@ PR136
1K_0402_1%

DRVL

COMP

3211_VCC
7

2
470P_0402_50V8J

2

3211_COMP 6

PVCC

OPT@ PU9

IREF

1

OPT@ PC118
47P_0402_50V8J
PC120 OPT@
1
2 3211_COMP-12
1

ADP3211AMNR2G_QFN32_5X5

FB

CSREF

220P_0402_50V7K

VID2

1
OPT@ PR128

FBRTN

5

1000P_0402_50V7K

LLINE

3211_FB

30

SW

4
PC116 OPT@
1
2

VID1

BST
DRVH
CLKEN#

RAMP

2

1

IMON

3

RT

1

PR129 OPT@
10_0603_1%

PWRGD

2
PC115

+5VS

VCC

1

32.4K_0402_1%
OPT@

VID1

2
0_0402_5%
3211_EN 1
OPT@ PR127
VID0
EN

PR132 @
1
2

31

10K_0402_1%

32

OPT@
2 PR131 13211_PWRGD
0_0402_5%

DGPU_PWROK

VID0

<19,30>

PR130 OPT@
2
1

+3VS

RPM

1

OPT@ PC128
330U_D2_2V_Y

100P_0402_50V8J
OPT@ PC107
2
1

1

OPT@ PC119
@330U_D2_2V_Y

<23>

<23>
GPU_VID4

<23>
GPU_VID5

<23>
GPU_VID3

GPU_VID2

DGPU_PWR_EN

PR126
0_0402_5%
2
1

GPU_VID1

OPT@
<15,18,30>

D

PR125 @
0_0402_5%
2
1

NVDD_PWR_EN

GPU_VID0

<18>

C

Document Number

C38-G series Chief River Schematic
Wednesday, February 15, 2012
D

Sheet

55

of

58

Rev
0.1

4

3

2

1

PL13
HCB4532KF-800T90_1812
1
2

+CPU_CORE
<9>

VCCSENSE

<9>

VSSSENSE

1
@ PR199
10_0402_1%

1

LGATE1

PC167
15U_D2_25VM_R90

PC166
33U_D2_25VM_R60

PC165
15U_D2_25VM_R90

PC177
10U_0805_25V6K
2
1

5
4

PC190
10U_0805_25V6K
2
1

PC189
10U_0805_25V6K
2
1

4

2

3

B

+CPU_CORE

1

VSUM-

PQ37

1

PR195
1_0402_5%

PR198
3.65K_0603_1%
VSUM- 2

4

Rds(on)
typ=2.7m Ω
max=3.3m Ω

10K_0402_1%_ERTJ0EG103FA

PC200
2
1

5

PQ38

3
2
1

1
PR189

12

2

PL15
0.36UH_VMPI1004AR-R36M-Z03_30A_20%

PC201
330P_0402_50V7K
2
1

2
2

A

4

PC193
0.22U_0603_16V7K

Close Phase 1 choke

2

2

PR190
2.2_0603_5%
BOOT1 2
1 1

PH7

2

PC199
150P_0402_50V8J
1
2
1
PR197
137K_0402_1%

PHASE1

0.1U_0402_16V7K

PR196
1.91K_0402_1%
2
1

2.61K_0402_1%

1
11K_0402_1%
2
PR194

1

1

1
PR192
499_0402_1%

2

PC195
68P_0402_50V8J
2
1

2

PC197
470P_0402_50V7K
2
1
2

@ PC192
10P_0402_50V8J
2
1

PC194
0.1U_0603_16V7K
PC196
1000P_0402_25V8J
1
2

PR188
42.2K_0402_1%
2
1

4

LGATE1

UGATE1



PQ36

3
2
1

5
PQ35

+3VS

MDU1511RH_POWERDFN56-8-5

1.91K_0402_1%
1

5

PR186
2

C

VSUM+
1

2

CPU_B+
<16>

PC198
680P_0402_50V7K
2
1 2
1
PR191
4.7_1206_5%

BOOT1
ISL95836HRTZ-T_TQFN40_5X5~D

PC188
10U_0805_25V6K
2
1

UGATE1

MDU1511RH_POWERDFN56-8-5

PHASE1

VGATE

+VGFX_CORE

For ULV 17W 1+1
CPU_CORE LL= -2.9mΩ,
GFX_CORE LL= -3.9mΩ,
OVP=0.9*115%=1.035V
Iocp=40A

UMA@

1

2
LGATE1

+5VS
PR185
0_0402_5%
1
2

3

PR171
1_0603_5%
PC183
1U_0603_10V6K

PR174
0_0603_5%

30
29
28
27
26
25
24
23
22
21

PR193
422_0402_1%

PR187
2K_0402_1%
2
1

3
2
1

1

1
BOOT2
UGATE2
PHASE2
LGATE2
VCCP
VDD
PWM3
LGATE1
PHASE1
UGATE1

VSUM+

1

2

40
39
38
37
36
35
34
33
32
31
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G

11
12
13
14
15
16
17
18
19
20

BOOT1G

Rds(on)
typ=2.7m Ω
max=3.3m Ω

4

2

2
1
PR168
1_0402_5%

PR169
2.2_0603_5%

B

PC191
470P_0402_50V7K
2

PC181
0.22U_0603_16V7K
4

1

VSUMG-

BOOT1G

MDU1516URH_POWERDFN56-8-5

PR183
27.4K_0402_1%

TP

PQ34

3
2
1

@ PC186
0.1U_0402_16V7K

ISUMPG
ISEN1G
ISEN2G
NTCG
SCLK
ALERT#
SDA
VR_HOT#
VR_ON
NTC

@

PL14
0.36UH_VMPI1004AR-R36M-Z03_30A_20%

3
2
1

2

1

2

+1.05VS_VTT

41

PR184
3.83K_0402_1%

1

1

@

PH6
470K_0402_5%_ TSM0B474J4702RE
2
1
2
1

2
PR179
0_0402_5%
1
2
PR180
130_0402_1%
1
2
PR181
75_0402_5%
1
2
PR182
54.9_0402_1%
@

2

@ PC184
47P_0402_50V8J

1

<9> VR_SVID_CLK
<9> VR_SVID_ALRT#
<9> VR_SVID_DAT
<42> VR_HOT#
<42> VR_ON

1
2
3
4
5
6
7
8
9
10

+

2

Change PL14 PL15 from SH00000HK00 to SH00000KK00
2012/02/07 Wenwen

1
PR166
4.7_1206_5%

1 1

UGATE1G

PC185
1U_0603_10V6K
2
1

ISEN2G
NTCG
SCLK
ALERT#
SDA

2

1

@

PC182
680P_0402_50V7K
2
1 2

PHASE1G

2

+5VS

PH5

2

@

5

LGATE1G

ISEN3/FB2
ISEN2
ISEN1
ISUMP
ISUMN
RTN
FB
COMP
PGOOD
BOOT1

PR173
0_0402_5%
1
2
1
470K_0402_5%_
TSM0B474J4702RE
1
2
1
2 PR175 0_0402_5%
PR176 0_0402_5%
1
2
PR177 0_0402_5%
1
2
PR178 0_0402_5%

PR172
3.83K_0402_1%
1
2

+

2
PR167
3.65K_0603_1%

3
2
1
PHASE1G

LGATE1G

PR170
27.4K_0402_1%
2
1

4

2

+5VS

+5VS
PU11

C

2

1

VSUMG+ 1

UGATE1G

PC176
10U_0805_25V6K
2
1

5
1 2

PR165 @
0_0402_5%
1
2

PWMG2 PR164

\

PC180
330P_0402_50V7K

MDU1516URH_POWERDFN56-8-5

1
VSUMG+

PQ33

PC174
10U_0805_25V6K
2
1

CPU_B+

2
1
PR159
2.61K_0402_1%

PR160
2K_0402_1%

2
1
PR162
154K_0402_1%

2
1
1.91K_0402_1%

+3VS

+

D

MDU1516URH_POWERDFN56-8-5

PC171
137K_0402_1%
150P_0402_50V8J
PR158 1
2
1

2

PC175
1000P_0402_25V8J
1
2

PC179
0.1U_0603_25V7K
1
2

2
1

PC178
0.022U_0402_16V7K
1
2

1

PR161
11K_0402_1%

2 1

1
2

PR163
2.61K_0402_1%

0.1U_0402_16V7K
PC172

@

1

CPU_B+

PC170
470P_0402_50V7K
2
1
2
1
PR156
499_0402_1%
PC173
10U_0805_25V6K
2
1

PC169
68P_0402_50V8J
2
1

2

MDU1511RH_POWERDFN56-8-5

1

PR157
422_0402_1%
2
1

2

PH4
10K_0402_1%_ERTJ0EG103FA
VSUMG-

+

2 2
PC168
0.01UF_0402_25V7K

@ PR155
10_0402_1%

D

1

PC164
33U_D2_25VM_R60

PC163
1000P_0402_50V7K

2

2

1

10_0402_1%

1

@ PR154
VCC_AXG_SENSE
VSS_AXG_SENSE

<10>
<10>

PC187
10U_0805_25V6K
2
1

2

+VGFX_CORE

1

B+

2

5

1

@PC202
0.01UF_0402_25V7K

A

@ PR200
10_0402_1%

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.
PWR CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

5

4

3

2

Sheet

Wednesday, February 15, 2012
1

56

of

58

Rev
0.1

1

1

1

1

PC296
10U_0603_6.3V6M

2

PC295
10U_0603_6.3V6M

2

PC294
10U_0603_6.3V6M

2

PC293
10U_0603_6.3V6M

PC292
10U_0603_6.3V6M
2
1

2

PC297
330U_D2_2V_Y

1

1

1

1

1

PC291
10U_0603_6.3V6M

2

PC290
10U_0603_6.3V6M

2

PC289
10U_0603_6.3V6M

2

PC288
10U_0603_6.3V6M

2

PC287
10U_0603_6.3V6M

2

PC259
1U_0402_6.3V6K
2
1
PC260
1U_0402_6.3V6K
2
1
PC261
1U_0402_6.3V6K
2
1
PC262
1U_0402_6.3V6K
2
1
PC263
1U_0402_6.3V6K
2
1
PC264
1U_0402_6.3V6K
2
1
PC265
1U_0402_6.3V6K
2
1
PC266
1U_0402_6.3V6K
2
1
PC267
1U_0402_6.3V6K
2
1
PC268
1U_0402_6.3V6K
2
1
PC269
1U_0402_6.3V6K
2
1
PC270
1U_0402_6.3V6K

PC276
1U_0402_6.3V6K
2
1
PC277
1U_0402_6.3V6K
2
1
PC278
1U_0402_6.3V6K
2
1
PC279
1U_0402_6.3V6K
2
1
PC280
1U_0402_6.3V6K
2
1
PC281
1U_0402_6.3V6K
2
1
PC282
1U_0402_6.3V6K
2
1
PC283
1U_0402_6.3V6K
2
1
PC284
1U_0402_6.3V6K
2
1
PC285
1U_0402_6.3V6K
2
1
PC286
1U_0402_6.3V6K

1

PC275
1U_0402_6.3V6K
2
1

2
PC258
1U_0402_6.3V6K
2
1

1

PC243
330U_D2_2V_Y

PC244
330U_D2_2V_Y

PC245
22U_0805_6.3V6M
PC246
22U_0805_6.3V6M

PC247
22U_0805_6.3V6M

PC248
22U_0805_6.3V6M

PC249
22U_0805_6.3V6M

PC250
22U_0805_6.3V6M

2

1

1

1

1

1

1

2

PC235
10U_0603_6.3V6M

2

PC234
10U_0603_6.3V6M

2

PC233
10U_0603_6.3V6M

2

PC232
10U_0603_6.3V6M

2

PC231
10U_0603_6.3V6M

2

PC230
10U_0603_6.3V6M

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1
PC229
2.2U_0402_6.3V6M

Wednesday, February 15, 2012

1

1

1

1

1

1

2

PC221
1U_0402_6.3V6K

2

PC220
1U_0402_6.3V6K

2

PC219
1U_0402_6.3V6K

2

PC218
1U_0402_6.3V6K

2

PC217
1U_0402_6.3V6K

2

PC216
1U_0402_6.3V6K

PC215
1U_0402_6.3V6K
2
1

PC214
1U_0402_6.3V6K
2
1

PC213
1U_0402_6.3V6K
2
1

PC212
1U_0402_6.3V6K
2
1

PC211
1U_0402_6.3V6K
2
1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1
PC210
2.2U_0402_6.3V6M

Date:

2

PC257
22U_0805_6.3V6M

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

PC242
22U_0805_6.3V6M

2

Title

2

PC228
2.2U_0402_6.3V6M

2012/07/11

1

PC209
2.2U_0402_6.3V6M

Compal Secret Data

2

PC256
22U_0805_6.3V6M

3

Deciphered Date

2

+

1

PC241
22U_0805_6.3V6M

2010/01/25
PC272
330U_D2_2V_Y

2

2

PC227
2.2U_0402_6.3V6M

2

+

1
PC255
22U_0805_6.3V6M

Issued Date

1

2

2

PC240
22U_0805_6.3V6M

Security Classification

PC271
330U_D2_2V_Y

1
PC254
22U_0805_6.3V6M

+
+

2

PC253
22U_0805_6.3V6M

2
1

2

1

2

PC239
22U_0805_6.3V6M

2

1

2

PC238
22U_0805_6.3V6M

1

1

2

1

PC208
2.2U_0402_6.3V6M

2

2

PC252
22U_0805_6.3V6M

4

2

1
PC237
22U_0805_6.3V6M

A

2

1
PC226
2.2U_0402_6.3V6M

2

1
1

PC207
2.2U_0402_6.3V6M

2

1

PC225
2.2U_0402_6.3V6M

2
1

1

PC206
2.2U_0402_6.3V6M

2
1

PC251
22U_0805_6.3V6M

5

+

1

PC224
2.2U_0402_6.3V6M

2
1

3

PC205
2.2U_0402_6.3V6M

+
PC223
2.2U_0402_6.3V6M

1
1

PC204
2.2U_0402_6.3V6M

1
PC236
22U_0805_6.3V6M

2

D

PC222
2.2U_0402_6.3V6M

C

4

PC203
2.2U_0402_6.3V6M

B

PC274
1U_0402_6.3V6K
2
1

5
2
1

+CPU_CORE

+VGFX_CORE

For BOT side

@

PWR CPU_CORE CAP

C38-G series Chief River Schematic

Sheet
57

1

of
58

Rev
0.1

D

+CPU_CORE

@

For TOP side
C

+1.05VS_VTT
+CPU_CORE

1

2

PC273
330U_D2_2V_Y

B

Compal Electronics, Inc.
A

5

4

3

2

Version change list (P.I.R. List)
Item

1

Page 1 of 1
for PWR

Reason for change

PG#

Modify List

Date

1

Add battery reset circuit

P47 add PJ401 PQ39 PR606 PC601 PC609 PR213 PR214 PQ40 PD303

2012/01/15

2

For VCCSA VID issue on Intel ULV

P52 add PC601 PC611

2012/01/15

3

Delete battery detector circuit

delete PR24,PR28,PR26,PC8,PU2,PR31,PR33,PR25,PR22,PR32,PR23,PQ3,PQ4;
2012/01/31
P48 delete PR43,PQ13; PR58,PQ18

Phase

D

D

4
5
6
7
8
C

C

9
10
11
12
13

14
B

B

15
16
17
A

A

Compal Secret Data

Security Classification
2010/01/25

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.
PWR PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C38-G series Chief River Schematic

Date:

5

4

3

2

Wednesday, February 15, 2012

Sheet
1

58

of

58

Rev
0.1

www.s-manuals.com
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Title                           : Compal LA-8971P - Schematics. www.s-manuals.com.
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