Compal LA 9331P Schematics. Www.s Manuals.com. Rx00 Schematics

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Page Count: 62

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
Cover Sheet
Custom
1 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
@ : Nopop Component
2012-06-22
RANGER 17
Rev: X00
Compal Confidential
Schematic Document
RANGER 17
PCB NO :
BOM P/N :
MODEL NAME :
LA-9331P
4619KL31L01
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B
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
Block Diagram
Custom
2 61Friday, June 22, 2012
2012/06/22 2013/06/21
P.26
P.33 P.33
USB3.0 Rediver
USB 3.0/USB 2.0 Conn.
USB 3.0/USB 2.0 Conn.
USB 3.0/USB 2.0 Conn.
USB 2.0 PS8713
USB3.0 Rediver
USB 2.0 PS8713
USB3.0
USB 2.0 PS8713
USB3.0 Rediver
USB3.0
USB 2.0 PS8713
USB3.0 Rediver
USB3.0
USB2.0
HDMI MUX
PCI-E 2.0
PS8271
DP/HDMI
DP/HDMI
Array Mics
PS8520BT
SATA Rediver
PS8520BT
SATA Rediver
SATA 3.0 HDD Conn. 1
Card Reader Board
USB3.0 Daughter Board
HDD Conn. 2
SATA 3.0
ODD Conn.
SATA 3.0
mSATA
Mini Card #3(Full)SATA 3.0
3D IR
( iPhone & Nokia compatible)
Combo Jack
AlienFX/ELC
P.6, 7, 8, 9, 10, 11, 12
P.17, 18, 19, 20, 21, 22, 23, 24, 25
rPGA-947
Int.KBD Touch Pad
Fan Control
EMC1412
CPU XDP
Conn.
HDMI
Digital Camera
MXM III
Conn.
Audio Codec
ALC3661
TI
TPA3113D2
HD Audio
USB2.0
5GT/s
100MHz
Card Reader
DMI x4
PEGx16
SPI
RTS5209
PCI-E 2.0
4C 47W/57W
LPC Bus
Processor
Intel
Haswell
PCH
Lynx Point
USB2.0
Intel
USB2.0
ENE KB9012
miniDP Conn.
USB2.0
RJ45 Conn.
SPI ROM
8MB
9 in 1 Conn.
E2201 Killer
LAN(GbE)
PCI-E 2.0
PCI-E 2.0
Int. Speaker (2.5W*4)
1.35V DDRIII 1600 MHz
Dual Channel
Memory Bus DDRIII
Headphone Jack
BANK 0, 1, 2, 3
204pin DDRIII SO-DIMM x4
ENE KC3810
BGA 695 Balls
eDP
Display MiniCard
HDMI SW
( USB Charger Port )
eDP Conn. P.30
4-lane eDP
USB 3.0/USB 2.0 Conn.
USB3.0
PS8321
eDP MUX
Gen 3
Headphone Jack
Scoket G3
P.32
P.32
P.27
P.41
P.36
P.35
P.34
P.42
P.42
P.43
P.42
P.43
P.42
P.47
P.46
P.47
P.47
P.49
P.48
P.48
P.47
P.45,46
P.49
P.49
P.49
P.51
P.40
P.13, 14, 15, 16
P.29
DP Redriver
PS8330
eDP MUX
HDMI 1.3 Input
HDMI 1.4a Output
Conn.
PS8321
STDP4028
HDMI to LVDS SW
STDP6038
LVDS to DP SW
PS121
HDMI Redriver
PS8271
HDMI MUX
HDMI
FFS
LNG3DMTR
VPK MCU
WLAN/WiMax
Mini Card #1(Half)
BT4.0+LE/WiGig
PS8520BT
SATA Rediver
DP1.2
Power Circuit DC/DC
DC/DC Interface CKT.
Power On/Off CKT.
RTC conn.
HM87
LVDS Conn. RTD2136
eDP to LVDS
PI3LVD1012
LVDS Mux
PI3LVD1012
LVDS Mux
LVDS
HDMI Redriver
PS121
TS3DV421
DMC
P.37
P.36
P.27
P.30
P.40
P.20
P.46
P.46
HDD Conn. 3
In ODD Bay (In place of ODD)
P.47
P.52
P.50
P.50
P.50
P.46
P.7
Digital Camera
USB2.0
P.30 with eDP Panel
with LVDS Panel
Array Mics
Camera with eDP Panel
Camera with LVDS Panel
P.39 P.39
P.54
P.39
P.30
P.38
VPK Daughter Board
USB3.0 Daughter Board
P.50
P.53
P.52
PS8338
eDP deMux
P.28
PI3LVD1012
LVDS Mux
P.31
P.54, 55, 56, 57, 58, 59, 60, 61
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1 1
2 2
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.1
3 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
Block Diagram
LA-9331P M/B
Project Code : VAS00
File Name : LA-9331P
Compal Confidential
INDICATOR/B
LS-9336P
LS-9335P
LS-9334P
POWER BUTTON/B
LOGO /B
Wire
12pin
Lid
Led x 2
Led-CapsLock
Led-Wireless
FFC
16 pin
Led x 2
Touch Pad
4 pin
HDD3ODD
LCD Panel
44 pin
Camera
20 pin
LF-XXXXP
FPC
on/off SW
FFC
6 pin
Led-HDD
LS-9333P LS-9331P LS-9332P
Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B
Led x 2Led x 2 Led x 2
WireWireWire
6pin 6pin6pin
LS-9338P
VPK Daughter/B
FFC
60 pin
VPK Keyboard
KSI/KSO
30 pin
Backlight / 8 Pressure-sense Analog Signals
40 pin
Coaxial/Wire Combo
VPK MCU MAX7313
HDD in ODD Bay Cable
LS-9339P
USB30 /B
USB3.0
USB3.0
RJ45
B To B conn.
B To B conn.
LS-9337P
CardReader /B
Card Slot
HDD1 conn.
HDD2 conn.
20 pin
FFC
Hot Key
6 pin
10 pin
PWM
Key Pad
FFC
30 pin
50pin
50pin
L R
FFC
Hot Bar
22 pin
22 pin
LS-933BP
Tron L/B
Led x 1
LS-933DP
Tron FL/B
Led x 1
LS-933EP
Tron FR/B
Led x 1
LS-933CP
Tron R/B
Led x 1
Wire
6pin
Wire
10pin
Wire
6pin
Tron Light
To M/B
To M/B
To USB30/B
Hot Bar
Hot Bar Hot Bar
A
A
1 1
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
Notes List
Custom
4 61Friday, June 22, 2012
2012/06/22 2013/06/21
None
1.0 (MP)
0.3 (ST)
0.4 (QT)
Lane 7
Lane 8
Lane 5
Lane 6
PCI EXPRESS
Lane 1/USB3.0 Port 3
DESTINATION
Lane 3
Lane 4
10/100/1G LAN
CARD READER
+1.35V_CPU_VDDQ
+3V_PCH
+3VMXM
+5VMXM
+1.05VS
PM TABLE
OFF
OFF
+VCC_CORE
+1.5VS
+0.675VS
+3VS
+3VALW
+5VS
+5VALW
S3
S0 ON
S5 S4/AC don't exist
ON
ON OFF
State
S5 S4/AC
power
plane
OFF
OFF
ONON
ON
+3VLP
OFF
ODD
HDD1
HDD2
SATA3
SATA2
SATA1
DESTINATION
SATA0
SATAIII
mSATA
None
ON ON
OFF
OFFOFFON
ON
OFFOFF OFF
OFFOFF
RUN
PLANE
SUS
PLANE
CLOCKS
S0 (Full ON) / M0
SLP
S3#
SLP
S5#
HIGH
POWER STATES
Signal
State
SLP
S4#
HIGH ON
S4
STATE#
ALWAYS
PLANE
HIGHHIGH
S5 (SOFT OFF) / M-OFF
LOW HIGH
SLP
M#
HIGH
LOW
HIGH LOW ONS3 (Suspend to RAM) / M-OFF
LOW
LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF
LOW LOW LOW LOW ON
HIGH
None
80port debug card
PCH_LOOPBACK
EC
PCI0
CLKOUT
None
PCI1
PCI2
PCI3
DESTINATION
PCI4
CLKOUT_PCIE7
CLKOUT_PCIE6
CLKOUT_PCIE4
CLKOUT_PCIE5
CLKOUT_PCIE1
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE0
DESTINATIONDIFFERENTIAL
CLK
CLKOUT_PEG_A
FLEX CLOCKS DESTINATION
CLKOUTFLEX1
CLKOUTFLEX2
CLKOUTFLEX3
CLKOUTFLEX0
None
MINI CARD-1 WLAN
MINI CARD-2 DMC
10/100/1G LAN
CARD READER
None
Symbol Note :
: means Digital Ground
: means Analog Ground
None
None
MXM
None
None
None
None
None
None
0x00-0x0C
EC AD3
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF
8.2K +/- 5%
2.433 V
2.420 V
0.250 V
0.2 (PT)
Vcc 3.3V +/- 5%
100K +/- 5%Ra
Board ID
Rb V min
0
1
2
3
0 0 V
0.168 V
0.375 V 0.503 V
0.819 V
0.362 V
0.621 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0.155 V
4
5
6
7NC
0.634 V
0.958 V
1.650 V
1.359 V
1.372 V
1.851 V 2.200 V
3.300 V
1.838 V
1.185 V
0.945 V
Board ID Table for AD channel
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1 (SSI)
None
Compal Electronics, Inc.
None
eDP CAMERA
AlienFX/ELC
LVDS CAMERA
JUSB4(USB3.0 P6)
JUSB3(USB3.0 P5)
JMINI1 (WLAN)
JMINI2 (DMC)
8
9
10
11
JUSB2(USB3.0 P2)
IR SENSOR
2
3
1
4
USB PORT#
0
DESTINATION
6
5
7
12
13
USB2.0
JUSB1(USB3.0 P1)
VPK K/B
+1.35V
+1.05V
V
V
2136
PCH_SML0DATA
PCH_SML0CLK PCH
FFS MXM
V
V
V
Link
V
XDP
PCH
V
V
DMC
EC_SMB_CK2
SOURCE
KB9012
WLAN BATT DIMM
SMBUS Control Table
PCH_SML1CLK
PCH_SML1DATA PCH
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
KB9012
MEM_SMBCLK
V
MEM_SMBDATA
Charger6038 Thermal
Sensor
None
None
None
6
NA
JUSB1 (Left side)
USB 3.0 PORT
1
Connetion
2
5
JUSB2 (Left side)
NA3
4
JUSB3 (Right side)
JUSB4 (Right side)
MINI CARD-1 WLAN
MINI CARD-2 DMC
SATA4/PCIE LANE1
SATA5/PCIE LANE2
Lane 2/USB3.0 Port 4
4028
V
VPK MCU
VV
TP mSATA
V V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
SMBus block diagram
Custom
5 61Friday, June 22, 2012
2012/06/22 2013/06/21
+3VS
SMBUS Address []
BATT CONN
2.2K
N11K6
SML0DATA
SML0CLK
2.2K +3V_PCH
+3V_PCH
2.2K
2.2K
SMBUS Address [A6]
DIMM1 SMBUS Address [A2]
DIMM2
SDA2
79
80
SCL2
SMBUS Address [TBD]
LNG3DM
SMBUS Address [A4]
DIMM3
6
4
SMBUS Address [A0]
DIMM4
KBC
MEM_SMBDATA
KB9012
R10
U11
SML1DATA
MEM_SMBCLK
SML1CLK
PCH
2.2K
+3VS
2.2K
SMBUS Address [TBD]
2.2K
2.2K
+3V_PCH
XDP
U8
R7
G sensor
53
202
51
200
202
200
202
200
202
200
QH9A
QH9B
SMBUS Address [TBD]
4.7K
VGA_SMB_DA1
VGA_SMB_CK1
0 Ω0 Ω
MXM_CURI2C_CLK
PCH_SMBCLK
PCH_SMBDATA
MXM_CURI2C_DATA
112
111
SMBUS Address [TBD]
RTD2136S
4.7K
SDA1
SCL1 77
78 EC_SMB_DA1
EC_SMB_CK1
2.2K
2.2K
+3VALW_EC
+3V_MXM
SMBUS Address []
MXM1 CONN
SMBUS Address []
HPA00900
MXM Current Monitor
70
68
6
5
4
5
SMBUS Address [TBD]
30
32 mSATA
30
32 DMC SMBUS Address [TBD]
100 Ω
100 Ω
4.7K
4.7K
+DVCC33
43
42
8
7SMBUS Address [100_1100]
ADM1032
SMBUS Address [0FFFFh to 0FF80h]
MSP430F5508
VPK
MXM FAN CONTROL
0 Ω
0 ΩVPK_SMB_DA2
VPK_SMB_CK2 Touch pad SMBUS Address [TBD]
15
16
0 Ω
0 Ω
MINI2_SMBCLK
MINI2_SMBDATA
DDR_XDP_SMBCLK_R1
DDR_XDP_SMBDAT_R1
+3VS
QH9B
QH9A
+3VS
QV2B
QV2A
+3VS
CSCL
CSDA
0 Ω
0 Ω
CIICSCL
CIICSDA
2.2K
2.2K
0 Ω
0 Ω
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2_R
EC_SMB_DA2_R
STDP4028 SMBUS Address [TBD]
C13
B14
EC_SMB_CK2
EC_SMB_DA2
72
71 SMBUS Address [TBD]
STDP6038
HDMI IN
EC_HDMI_CLK
EC_HDMI_DAT
0 Ω
0 Ω
22 Ω
22 Ω
EC_HDMI_CLK_R
EC_HDMI_DAT_R
4.7K
4.7K
+3VS
QV8
QV6
+3V_MXM
CLK_SMB
DAT_SMB
0 Ω
0 Ω
PU700
0 Ω
0 Ω
Thermal sensor
ADM1032
Thermal sensor
8
7
SYSTEM FAN CONTROL
SMBUS Address [100_1100]
LVDS transfer DP
SMBUS Address [000_1001]
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FDI_CSYNC_R
FDI_INT_R
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CTX_PRX_N0
DMI_CRX_PTX_N2
DMI_CTX_PRX_P2
DMI_CTX_PRX_P1
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_N3
DMI_CTX_PRX_N3
DMI_CRX_PTX_P3
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_N1
DMI_CRX_PTX_N1
DMI_CTX_PRX_N2
PEG_COMP
PEG_COMP
PEG_GTX_HRX_P15
PEG_GTX_HRX_P7
PEG_GTX_HRX_P6
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
PEG_GTX_HRX_P3
PEG_GTX_HRX_P2
PEG_GTX_HRX_P0
PEG_GTX_HRX_P1
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P15
PEG_HTX_GRX_N0
PEG_HTX_GRX_N2
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N1
PEG_HTX_GRX_N5
PEG_HTX_GRX_N6
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N9
PEG_HTX_GRX_N10
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N13
PEG_HTX_GRX_N14
PEG_HTX_GRX_N15
PEG_HTX_GRX_P0
PEG_HTX_GRX_P2
PEG_HTX_GRX_P4
PEG_HTX_GRX_P1
PEG_HTX_GRX_P3
PEG_HTX_GRX_P6
PEG_HTX_GRX_P8
PEG_HTX_GRX_P5
PEG_HTX_GRX_P7
PEG_HTX_GRX_P10
PEG_HTX_GRX_P12
PEG_HTX_GRX_P9
PEG_HTX_GRX_P11
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P15
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N1
PEG_GTX_HRX_P14
PEG_GTX_HRX_N7
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
PEG_GTX_HRX_N4
PEG_GTX_HRX_N3
PEG_GTX_HRX_N2
PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_P13
PEG_GTX_HRX_P12
PEG_GTX_HRX_N15
PEG_GTX_HRX_N14
PEG_GTX_HRX_N13
PEG_GTX_HRX_N12
PEG_GTX_HRX_N11
PEG_GTX_HRX_N10
PEG_GTX_HRX_N8
PEG_GTX_HRX_N9
PEG_GTX_HRX_P11
PEG_GTX_HRX_P10
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
+VCOMP_OUT
FDI_INT<17>
FDI_CSYNC<17>
DMI_CRX_PTX_P0<17>
DMI_CRX_PTX_N3<17>
DMI_CRX_PTX_P1<17>
DMI_CRX_PTX_N1<17>
DMI_CRX_PTX_P3<17>
DMI_CRX_PTX_N2<17>
DMI_CRX_PTX_P2<17>
DMI_CRX_PTX_N0<17>
DMI_CTX_PRX_N0<17>
DMI_CTX_PRX_N1<17>
DMI_CTX_PRX_N2<17>
DMI_CTX_PRX_N3<17>
DMI_CTX_PRX_P0<17>
DMI_CTX_PRX_P1<17>
DMI_CTX_PRX_P2<17>
DMI_CTX_PRX_P3<17>
PEG_HTX_C_GRX_N[0..15] <29>
PEG_GTX_HRX_P[0..15] <29>
PEG_GTX_HRX_N[0..15] <29>
PEG_HTX_C_GRX_P[0..15] <29>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU (1/7) DMI,PEG
Custom
6 61Friday, June 22, 2012
2012/06/22 2013/06/21
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
Compal Electronics, Inc.
Near MXM Connector
CC42 0.22U_0402_16V7K~D
1 2
CC40 0.22U_0402_16V7K~D
1 2
CC16 0.22U_0402_16V7K~D
1 2
CC8 0.22U_0402_16V7K~D
1 2
CC51 0.22U_0402_16V7K~D
1 2
CC18 0.22U_0402_16V7K~D
1 2
CC55 0.22U_0402_16V7K~D
1 2
CC6 0.22U_0402_16V7K~D
1 2
CC10 0.22U_0402_16V7K~D
1 2
CC27 0.22U_0402_16V7K~D
1 2
CC31 0.22U_0402_16V7K~D
1 2
CC58 0.22U_0402_16V7K~D
1 2
CC35 0.22U_0402_16V7K~D
1 2
CC36 0.22U_0402_16V7K~D
1 2
CC7 0.22U_0402_16V7K~D
1 2
CC11 0.22U_0402_16V7K~D
1 2
CC26 0.22U_0402_16V7K~D
1 2
CC48 0.22U_0402_16V7K~D
1 2
CC44 0.22U_0402_16V7K~D
1 2
CC33 0.22U_0402_16V7K~D
1 2
DMI FDI
PEG
Haswell rPGA EDS
1 OF 9
JCPU1A
INTEL_HASWELL_HASWELL
CONN@
PEG_TXP_15 B24
PEG_TXP_14 C25
PEG_TXP_13 B26
PEG_TXP_12 C27
PEG_TXP_11 B28
PEG_TXP_10 C29
PEG_TXP_9 B30
PEG_TXP_8 C31
PEG_TXP_7 A32
PEG_TXP_6 B33
PEG_TXP_5 H30
PEG_TXP_4 H31
PEG_TXP_3 G32
PEG_TXP_2 H33
PEG_TXP_1 G34
PEG_TXP_0 J35
PEG_TXN_15 A24
PEG_TXN_14 B25
PEG_TXN_13 A26
PEG_TXN_12 B27
PEG_TXN_11 A28
PEG_TXN_10 B29
PEG_TXN_9 A30
PEG_TXN_8 B31
PEG_TXN_7 B32
PEG_TXN_6 C33
PEG_TXN_5 G30
PEG_TXN_4 J31
PEG_TXN_3 H32
PEG_TXN_2 J33
PEG_TXN_1 H34
PEG_TXN_0 H35
PEG_RXP_15 D32
PEG_RXP_14 F33
PEG_RXP_13 E34
PEG_RXP_12 F35
PEG_RXP_11 E30
PEG_RXP_10 F31
PEG_RXP_9 E28
PEG_RXP_8 F29
PEG_RXP_7 K34
PEG_RXP_6 L35
PEG_RXP_5 K32
PEG_RXP_4 L33
PEG_RXP_3 K30
PEG_RXP_2 L31
PEG_RXP_1 L28
PEG_RXP_0 L29
PEG_RXN_15 E32
PEG_RXN_14 E33
PEG_RXN_13 D34
PEG_RXN_12 E35
PEG_RXN_11 D30
PEG_RXN_10 E31
PEG_RXN_9 D28
PEG_RXN_8 E29
PEG_RXN_7 L34
PEG_RXN_6 M35
PEG_RXN_5 L32
PEG_RXN_4 M33
PEG_RXN_3 L30
PEG_RXN_2 M31
PEG_RXN_1 K28
PEG_RXN_0 M29
PEG_RCOMP E23
FDI_INT
J29 FDI_CSYNC
H29
DMI_TXP_3
A18 DMI_TXP_2
B18 DMI_TXP_1
C18 DMI_TXP_0
D17
DMI_TXN_3
A17 DMI_TXN_2
B17 DMI_TXN_1
C17 DMI_TXN_0
D18
DMI_RXP_3
A20 DMI_RXP_2
B20 DMI_RXP_1
C20 DMI_RXP_0
D20
DMI_RXN_3
A21 DMI_RXN_2
B21 DMI_RXN_1
C21 DMI_RXN_0
D21
CC52 0.22U_0402_16V7K~D
1 2
CC12 0.22U_0402_16V7K~D
1 2
CC21 0.22U_0402_16V7K~D
1 2
CC22 0.22U_0402_16V7K~D
1 2
CC38 0.22U_0402_16V7K~D
1 2
CC3 0.22U_0402_16V7K~D
1 2
CC5 0.22U_0402_16V7K~D
1 2
CC29 0.22U_0402_16V7K~D
1 2
CC23 0.22U_0402_16V7K~D
1 2
CC25 0.22U_0402_16V7K~D
1 2
CC60 0.22U_0402_16V7K~D
1 2
CC43 0.22U_0402_16V7K~D
1 2
CC1 0.22U_0402_16V7K~D
1 2
CC4 0.22U_0402_16V7K~D
1 2
CC56 0.22U_0402_16V7K~D
1 2
CC49 0.22U_0402_16V7K~D
1 2
CC24 0.22U_0402_16V7K~D
1 2
CC46 0.22U_0402_16V7K~D
1 2
CC34 0.22U_0402_16V7K~D
1 2
CC13 0.22U_0402_16V7K~D
1 2
CC50 0.22U_0402_16V7K~D
1 2
CC64 0.22U_0402_16V7K~D
1 2
CC14 0.22U_0402_16V7K~D
1 2
CC28 0.22U_0402_16V7K~D
1 2
CC37 0.22U_0402_16V7K~D
1 2
CC47 0.22U_0402_16V7K~D
1 2
RC87 0_0402_5%~D
12
CC9 0.22U_0402_16V7K~D
1 2
CC19 0.22U_0402_16V7K~D
1 2
CC62 0.22U_0402_16V7K~D
1 2
CC2 0.22U_0402_16V7K~D
1 2
CC45 0.22U_0402_16V7K~D
1 2
CC39 0.22U_0402_16V7K~D
1 2
CC41 0.22U_0402_16V7K~D
1 2
CC57 0.22U_0402_16V7K~D
1 2
CC59 0.22U_0402_16V7K~D
1 2
CC20 0.22U_0402_16V7K~D
1 2
RC3 0_0402_5%~D
12
CC53 0.22U_0402_16V7K~D
1 2
CC15 0.22U_0402_16V7K~D
1 2
CC63 0.22U_0402_16V7K~D
1 2
CC30 0.22U_0402_16V7K~D
1 2
CC61 0.22U_0402_16V7K~D
1 2
CC32 0.22U_0402_16V7K~D
1 2
RC224.9_0402_1%~D
12
CC17 0.22U_0402_16V7K~D
1 2
CC54 0.22U_0402_16V7K~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG9
CFG8
PM_DRAM_PWRGD_CPU
XDP_TDI_R
XDP_TDO_R
XDP_TRST#
XDP_TCLK
XDP_TMS
XDP_PRDY#
XDP_PREQ#
CFG15
CFG14
XDP_OBS3_R
XDP_OBS5_R
XDP_OBS2_R
XDP_OBS1_R
XDP_OBS0_R
XDP_OBS4_R
XDP_OBS6_R
XDP_OBS7_R
XDP_TDO
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CFG17
CPU_SSC_DPLL
CFG2
CFG3
CPU_DMI
CPU_DMI#
CFG11
CFG10
XDP_OBS0
XDP_OBS1
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
H_CATERR#
H_PROCHOT#
H_THERMTRIP#
SM_RCOMP1
PCH_PLTRST#_BUF
CPU_PLTRST#_R
CPU_PLTRST#_R
XDP_DBRESET#_R
XDP_TCLK
XDP_TMS
XDP_TRST#
CFG13
CFG16
CFG12
XDP_TDO_R
XDP_TDI_R
XDP_PREQ#
VCCPWRGOOD_0_R
H_PM_SYNC
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#_R
PM_DRAM_PWRGD_CPU
VCCPWRGOOD_0_R
CLK_XDP
CLK_XDP#
XDP_TDI
CFD_PWRBTN#_XDP
XDP_TMS_R
XDP_PREQ#_R
XDP_PRDY#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#_R
XDP_TDI
XDP_TCLK_R
H_CPUPWRGD H_CPUPWRGD_XDP
XDP_RST#_RCPU_PW R_DEBUG_R
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
SYS_PWROK_XDP
CPU_PLTRST#_R
SM_RCOMP2
CFG1
CFG0
SM_RCOMP0
CFG19
DDR3_DRAMRST#_CPU
CFG4
CFG5
CFG6
CFG7
CFG18
XDP_DBRESET#
XDP_OBS0
XDP_OBS1
XDP_DBRESET#_R
H_PECI
CPU_SSC_DPLL
CPU_SSC_DPLL#
SYS_PWROK_XDP
RUNPWROK_AND
XDP_PREQ#_R
XDP_TCLK_R
XDP_TMS_R
XDP_TRST#_R
XDP_PRDY#_R
+VCCIO_OUT
+VCCIO_OUT +VCCIO_OUT
+1.05VS
+VCCIO_OUT
+1.05VS
+3VS
+3V_PCH
+3VS
+1.35V_CPU_VDDQ
+3V_PCH
+3V_PCH
+VCCIO_OUT
+3V_PCH
PBTN_OUT#<17,43>
H_CPUPWRGD<21>
H_PM_SYNC<17>
IMVP_PW RGD<17,43,62>
PCH_SMBCLK<12,13,14,15,19,49,50,51,53>
PCH_SMBDATA<12,13,14,15,19,49,50,51,53>
RUN_ON_CPU1.5VS3#<10,56>
PM_DRAM_PWRGD<17>
CLK_CPU_DMI<18>
CLK_CPU_DMI#<18>
XDP_DBRESET# <17>
CLK_CPU_SSC_DPLL#<18>
CLK_CPU_SSC_DPLL<18>
CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CPU_PW R_DEBUG<10>
CFG17 <9>
CFG16 <9>
CFG9 <9>
CFG8 <9>
CFG11 <9>
CFG10 <9>
CFG18 <9>
CFG19 <9>
CFG13 <9>
CFG12 <9>
CFG15 <9>
CFG14 <9>
CLK_CPU_ITP <18>
CLK_CPU_ITP# <18>
CLK_CPU_DPLL#<18>
CLK_CPU_DPLL<18>
H_THERMTRIP#<21>
H_PROCHOT#<43,63>
H_PECI<21,43>
CPU_PLTRST#<21>
PLT_RST#<17,43,44,51,53>
SYS_PWROK<17>
DDR3_DRAMRST#_CPU <12>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
CPU (2/7) PM,XDP,CLK
Custom
7 61Friday, June 22, 2012
2012/06/22 2013/06/21
CRB Rev 0.7 no pull up
Buffered reset to CPU
place RC134 near CPU
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
RC5 need to close to JCPU1
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
PU/PD for JTAG signals
SM_DRAMPWROK with DDR Power Gating Topology
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
CRB Rev 0.7 is depop
DDR3 COMPENSATION SIGNALS
Place near JXDP1
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
For ESD concern, please put near CPU
Compal Electronics, Inc.
UC1
SN74LVC1G07DCKR_SC70-5~D
NC
1
A
2
GND
3Y4
VCC 5
RC12 0_0402_5%~D
1 2
RC136 56_0402_5%~D@
1 2
RC55 75_0402_1%~D
1 2
RC27 51_0402_1%~D@
12
RC32 51_0402_1%~D@
12
RC46 0_0402_5%~D
1 2
RC19 1K_0402_1%~D
12
RC48 0_0402_5%~D
1 2
RC31 0_0402_5%~D
1 2
RC25 0_0402_5%~D
1 2
RC6 0_0402_5%~D
1 2
RC2110K_0402_5%~D @
1 2
RC8 0_0402_5%~D
1 2
RC5 1K_0402_1%~D
1 2
RC33 0_0402_5%~D
1 2
CC156
0.1U_0402_25V6K~D
1 2
RC145 0_0402_5%~D
1 2
RC26 0_0402_5%~D
12
RC42 51_0402_1%~D
12
RC35 51_0402_1%~D
12
RC2010K_0402_5%~D @
1 2
PWR
DDR3
MISC
THERMAL
CLOCK
JTAG
Haswell rPGA EDS
2 OF 9
JCPU1B
INTEL_HASWELL_HASWELL
CONN@
BPM_N_7 AP28
BPM_N_6 AP29
BPM_N_5 AN28
BPM_N_4 AP30
BPM_N_3 AP31
BPM_N_2 AN29
BPM_N_1 AN31
BPM_N_0 AR30
DBR AP33
TDO AL33
TDI AM31
TRST AM33
TMS AN33
TCK AM34
PREQ AT29
PRDY AR29
SM_DRAMRST AN3
SM_RCOMP_2 AP2
SM_RCOMP_1 AR3
SM_RCOMP_0 AP3
BCLKP
E26 BCLKN
D26 SSC_DPLL_REF_CLKP
E27 SSC_DPLL_REF_CLKN
F27 DPLL_REF_CLKP
H28 DPLL_REF_CLKN
G28
PWRGOOD
AL34 PM_SYNC
AT28
PROCHOT
AM30 RSVD
AK31 PECI
AR27 CATERR
AN32
SKTOCC
AP32
PLTRSTIN
AT26 SM_DRAMPWROK
AC10
THERMTRIP
AM35
RC53 0_0402_5%~D
12
RC40 0_0402_5%~D
1 2
RC51 0_0402_5%~D
12
RC94 0_0402_5%~D
@
12
RC16
1.8K_0402_1%
12
JXDP1
SAMTE_BSH-030-01-L-D-A CONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1 2
OBSFN_C0 4
OBSFN_C1 6
GND3 8
OBSDATA_C0 10
OBSDATA_C1 12
GND5 14
OBSDATA_C2 16
OBSDATA_C3 18
GND7 20
OBSFN_D0 22
OBSFN_D1 24
GND9 26
OBSDATA_D0 28
OBSDATA_D1 30
GND11 32
OBSDATA_D2 34
OBSDATA_D3 36
GND13 38
ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42
VCC_OBS_CD 44
RESET#/HOOK6 46
DBR#/HOOK7 48
GND15 50
TD0 52
TRST# 54
TDI 56
TMS 58
GND17 60
RC29 51_0402_1%~D
12
RC34 0_0402_5%~D
1 2
RC52 0_0402_5%~D
12
G
D
S
QC1
SSM3K7002FU_SC70-3~D
@
2
13
RC45 100_0402_1%~D
1 2
RC64
39_0402_5%~D
@
1 2
RC23 0_0402_5%~D
1 2
RC44 62_0402_5%~D
1 2
RC28 0_0402_5%~D
12
RC49 100_0402_1%~D
1 2
RC54 0_0402_5%~D@
12
RC47 0_0402_5%~D
1 2
RC10 43_0402_5%~D
1 2
RC134 0_0402_5%~D
1 2
RC88 0_0402_5%~D
12
CC140
0.1U_0402_25V6K~D
1
2
RC144 0_0402_5%~D
1 2
CC65
0.1U_0402_25V6K~D
1
2
RC38 0_0402_5%~D
1 2
RC127 0_0402_5%~D
1 2
RC36 0_0402_5%~D
1 2
RC41 51_0402_1%~D
12
RC14
3.3K_0402_1%~D
12
RC9 1K_0402_1%~D
12
RC37 0_0402_5%~D
1 2
CC66
0.1U_0402_25V6K~D
1
2
RC17
1K_0402_1%~D
12
RC128 49.9_0402_1%~D@
1 2
RC18 200_0402_1%~D
1 2
UC2
74AHC1G09GW_TSSOP5~D
B
1
A
2
G
3
O4
P5
RC125 1K_0402_1%~D@
1 2
RC135
10K_0402_5%~D
12
RC57 56_0402_5%~D
1 2
RC126 0_0402_5%~D
1 2
RC30 0_0402_5%~D
1 2
RC24 0_0402_5%~D
1 2
RC43 0_0402_5%~D
12
RC50 0_0402_5%~D
1 2
RC22 0_0402_5%~D
12
RC89
100K_0402_5%~D
@
12
RC15 0_0402_5%~D
12
RC13 0_0402_5%~D
12
RC39 0_0402_5%~D
1 2
T66PAD~D @
RC11
20K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_B_BS2
DDR_B_CAS#
DDR_B_BS1
DDR_B_BS0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#0
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_DQS#4
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_A_MA0
DDR_A_MA1
DDR_A_MA3
DDR_A_MA7
DDR_A_MA8
DDR_A_MA13
DDR_A_MA2
DDR_A_MA14
DDR_A_MA5
DDR_A_MA10
DDR_A_MA4
DDR_A_MA11
DDR_A_MA9
DDR_A_MA6
DDR_A_MA12
DDR_A_MA15
M_ODT1
M_ODT0
DDR_B_MA10
DDR_B_MA9
DDR_B_MA14
DDR_B_MA5
DDR_B_MA13
DDR_B_MA11
DDR_B_MA7
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6
DDR_B_MA1
DDR_B_MA12
DDR_B_MA4
DDR_B_MA8
DDR_B_MA3
DDR_B_MA15
DDR_A_BS1
DDR_A_BS2
DDR_A_BS0
DDR_B_RAS#
DDR_B_WE#
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS7
DDR_B_DQS4
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS0
M_ODT2
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
M_ODT3
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
DDR_A_DQS7
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS5
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS0
DDR_A_DQS6
DDR_A_DQS#5
DDR_A_DQS#7
DDR_A_DQS#2
DDR_A_DQS#1
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#6
DDR_B_D29
DDR_B_D59
DDR_B_D50
DDR_B_D49
DDR_B_D13
DDR_B_D11
DDR_B_D19
DDR_B_D14
DDR_B_D3
DDR_B_D55
DDR_B_D47
DDR_B_D52
DDR_B_D44
DDR_B_D41
DDR_B_D8
DDR_B_D5
DDR_B_D56
DDR_B_D48
DDR_B_D38
DDR_B_D35
DDR_B_D26
DDR_B_D25
DDR_B_D4
DDR_B_D63
DDR_B_D34
DDR_B_D32
DDR_B_D10
DDR_B_D17
DDR_B_D51
DDR_B_D40
DDR_B_D36
DDR_B_D31
DDR_B_D21
DDR_B_D20
DDR_B_D15
DDR_B_D7
DDR_B_D62
DDR_B_D46
DDR_B_D42
DDR_B_D18
DDR_B_D12
DDR_B_D1
DDR_B_D53
DDR_B_D37
DDR_B_D22
DDR_B_D57
DDR_B_D27
DDR_B_D54
DDR_B_D45
DDR_B_D39
DDR_B_D30
DDR_B_D9
DDR_B_D60
DDR_B_D58
DDR_B_D33
DDR_B_D0
DDR_B_D61
DDR_B_D43
DDR_B_D28
DDR_B_D23
DDR_B_D24
DDR_B_D16
DDR_B_D6
DDR_B_D2
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D31
DDR_A_D9
DDR_A_D50
DDR_A_D42
DDR_A_D29
DDR_A_D51
DDR_A_D46
DDR_A_D36
DDR_A_D18
DDR_A_D58
DDR_A_D55
DDR_A_D14
DDR_A_D24
DDR_A_D8
DDR_A_D63
DDR_A_D49
DDR_A_D41
DDR_A_D34
DDR_A_D28
DDR_A_D25
DDR_A_D35
DDR_A_D17
DDR_A_D13
DDR_A_D57
DDR_A_D54
DDR_A_D22
DDR_A_D21
DDR_A_D23
DDR_A_D7
DDR_A_D62
DDR_A_D48
DDR_A_D40
DDR_A_D33
DDR_A_D27
DDR_A_D44
DDR_A_D16
DDR_A_D12
DDR_A_D56
DDR_A_D53
DDR_A_D45
DDR_A_D38
DDR_A_D20
DDR_A_D60
DDR_A_D61
DDR_A_D47
DDR_A_D39
DDR_A_D32
DDR_A_D26
DDR_A_D10
DDR_A_D43
DDR_A_D15
DDR_A_D11
DDR_A_D52
DDR_A_D37
DDR_A_D30
DDR_A_D19
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR#2
M_CLK_DDR2
DDR_CS5_DIMMC#
DDR_CS4_DIMMC#
DDR_CS6_DIMMD#
DDR_CS7_DIMMD#
M_ODT6
M_ODT7
M_ODT5
M_ODT4
DDR_CKE4_DIMMC
M_CLK_DDR4
M_CLK_DDR#4
DDR_CKE5_DIMMC
M_CLK_DDR5
M_CLK_DDR#5 DDR_CKE6_DIMMD
M_CLK_DDR6
M_CLK_DDR#6
DDR_CKE7_DIMMD
M_CLK_DDR7
M_CLK_DDR#7
+V_SM_VREF_CNT
+1.35V
+V_SM_VREF
+DIMM0_1_VREF
+DIMM0_1_CA
+DIMM0_1_VREF_CPU
+1.35V
+DIMM0_1_CA_CPU
+1.35V
+DIMM0_1_CA +DIMM0_1_VREF
+V_SM_VREF
DDR_B_D[0..63]<13,15>
DDR_B_DQS[0..7] <13,15>
DDR_CS3_DIMMB# <15>
DDR_CS2_DIMMB# <15>
M_ODT3 <15>
DDR_CKE3_DIMMB <15>
DDR_CKE2_DIMMB <15>
M_ODT2 <15>
DDR_A_D[0..63]<12,14>
DDR_A_MA[0..15] <12,14>
DDR_A_DQS#[0..7] <12,14>
DDR_A_DQS[0..7] <12,14>
DDR_A_BS0 <12,14>
DDR_A_BS1 <12,14>
DDR_A_BS2 <12,14>
DDR_A_CAS# <12,14>
DDR_A_WE# <12,14>
DDR_A_RAS# <12,14>
DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
M_ODT0 <14>
M_ODT1 <14>
DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>
DDR_B_BS2 <13,15>
DDR_B_BS1 <13,15>
DDR_B_CAS# <13,15>
DDR_B_BS0 <13,15>
DDR_B_DQS#[0..7] <13,15>
DDR_B_MA[0..15] <13,15>
DDR_B_WE# <13,15>
DDR_B_RAS# <13,15>
M_CLK_DDR0 <14>
M_CLK_DDR#0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR#2 <15>
M_CLK_DDR2 <15>
M_CLK_DDR#3 <15>
M_CLK_DDR3 <15>
DDR_CS4_DIMMC# <12>
DDR_CS5_DIMMC# <12>
DDR_CS7_DIMMD# <13>
DDR_CS6_DIMMD# <13>
M_ODT7 <13>
M_ODT6 <13>
M_ODT4 <12>
M_ODT5 <12>
DDR_CKE4_DIMMC <12>
M_CLK_DDR4 <12>
M_CLK_DDR#4 <12>
DDR_CKE5_DIMMC <12>
M_CLK_DDR5 <12>
M_CLK_DDR#5 <12> DDR_CKE6_DIMMD <13>
M_CLK_DDR#6 <13>
M_CLK_DDR6 <13>
DDR_CKE7_DIMMD <13>
M_CLK_DDR#7 <13>
M_CLK_DDR7 <13>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU (3/7) DDRIII
Custom
8 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
T76 PAD~D@
RC150
24.9_0402_1%
12
T67 PAD~D@
Haswell rPGA EDS
4 OF 9
JCPU1D
INTEL_HASWELL_HASWELL
CONN@
RSVD AG8
SB_CKN0 Y4
SB_CK0 AA4
SB_CKE_0 AF10
SB_CKN1 Y3
SB_CK1 AA3
SB_CKE_1 AG10
SB_CKN2 Y2
SB_CK2 AA2
SB_CKE_2 AG9
SB_CKN3 Y1
SB_CK3 AA1
SB_CKE_3 AF9
SB_CS_N_0 P4
SB_CS_N_1 R2
SB_CS_N_2 P3
SB_CS_N_3 P1
SB_ODT_0 R4
SB_ODT_1 R3
SB_ODT_2 R1
SB_ODT_3 P2
SB_BS_0 R7
SB_BS_1 P8
SB_BS_2 AA9
RSVD R10
SB_RAS R6
SB_WE P6
SB_CAS P7
SB_MA_0 R8
SB_MA_1 Y5
SB_MA_2 Y10
SB_MA_3 AA5
SB_MA_4 Y7
SB_MA_5 AA6
SB_MA_6 Y6
SB_MA_7 AA7
SB_MA_8 Y8
SB_MA_9 AA10
SB_MA_10 R9
SB_MA_11 Y9
SB_MA_12 AF7
SB_MA_13 P9
SB_MA_14 AA8
SB_MA_15 AG7
SB_DQS_N_0 AP18
SB_DQS_N_1 AP11
SB_DQS_N_2 AP5
SB_DQS_N_3 AJ3
SB_DQS_N_4 L3
SB_DQS_N_5 H9
SB_DQS_N_6 C8
SB_DQS_N_7 C14
SB_DQS_P_0 AP17
SB_DQS_P_1 AP12
SB_DQS_P_2 AP6
SB_DQS_P_3 AK3
SB_DQS_P_4 M3
SB_DQS_P_5 H8
SB_DQS_P_6 C9
SB_DQS_P_7 C15
SB_DQ_0
AR18
SB_DQ_1
AT18
SB_DQ_2
AM17
SB_DQ_3
AM18
SB_DQ_4
AR17
SB_DQ_5
AT17
SB_DQ_6
AN17
SB_DQ_7
AN18
SB_DQ_8
AT12
SB_DQ_9
AR12
SB_DQ_10
AN12
SB_DQ_11
AM11
SB_DQ_12
AT11
SB_DQ_13
AR11
SB_DQ_14
AM12
SB_DQ_15
AN11
SB_DQ_16
AR5
SB_DQ_17
AR6
SB_DQ_18
AM5
SB_DQ_19
AM6
SB_DQ_20
AT5
SB_DQ_21
AT6
SB_DQ_22
AN5
SB_DQ_23
AN6
SB_DQ_24
AJ4
SB_DQ_25
AK4
SB_DQ_26
AJ1
SB_DQ_27
AJ2
SB_DQ_28
AM1
SB_DQ_29
AN1
SB_DQ_30
AK2
SB_DQ_31
AK1
SB_DQ_32
L2
SB_DQ_33
M2
SB_DQ_34
L4
SB_DQ_35
M4
SB_DQ_36
L1
SB_DQ_37
M1
SB_DQ_38
L5
SB_DQ_39
M5
SB_DQ_40
G7
SB_DQ_41
J8
SB_DQ_42
G8
SB_DQ_43
G9
SB_DQ_44
J7
SB_DQ_45
J9
SB_DQ_46
G10
SB_DQ_47
J10
SB_DQ_48
A8
SB_DQ_49
B8
SB_DQ_50
A9
SB_DQ_51
B9
SB_DQ_52
D8
SB_DQ_53
E8
SB_DQ_54
D9
SB_DQ_55
E9
SB_DQ_56
E15
SB_DQ_57
D15
SB_DQ_58
A15
SB_DQ_59
B15
SB_DQ_60
E14
SB_DQ_61
D14
SB_DQ_62
A14
SB_DQ_63
B14
CC138
0.022U_0402_25V7K~D
1
2
RC96
1K_0402_1%~D
12
RC148
0_0402_5%
1 2
CC137
0.022U_0402_25V7K~D
1
2
RC149
24.9_0402_1%
12
RC78
1K_0402_1%~D
12
RC147
0_0402_5%
1 2
RC86
1K_0402_1%~D
12
RC81
1K_0402_1%~D
12
CC139
0.022U_0402_25V7K~D
1
2
RC82
1K_0402_1%~D
12
Haswell rPGA EDS
3 OF 9
JCPU1C
INTEL_HASWELL_HASWELL
CONN@
RSVD_AC7 AC7
SA_CK_N_0 U4
SA_CK_P_0 V4
SA_CKE_0 AD9
SA_CK_N_1 U3
SA_CK_P_1 V3
SA_CKE_1 AC9
SA_CK_N_2 U2
SA_CK_P_2 V2
SA_CKE_2 AD8
SA_CK_N_3 U1
SA_CK_P_3 V1
SA_CKE_3 AC8
SA_CS_N_0 M7
SA_CS_N_1 L9
SA_CS_N_2 M9
SA_CS_N_3 M10
SA_ODT_0 M8
SA_ODT_1 L7
SA_ODT_2 L8
SA_ODT_3 L10
SA_BS_0 V5
SA_BS_1 U5
SA_BS_2 AD1
RSVD_V10 V10
SA_RAS U6
SA_WE U7
SA_CAS U8
SA_MA_0 V8
SA_MA_1 AC6
SA_MA_10 V6
SA_MA_11 AC1
SA_MA_12 AD4
SA_MA_13 V7
SA_MA_14 AD3
SA_MA_15 AD2
SA_MA_2 V9
SA_MA_3 U9
SA_MA_4 AC5
SA_MA_5 AC4
SA_MA_6 AD6
SA_MA_7 AC3
SA_MA_8 AD5
SA_MA_9 AC2
SA_DQS_N_0 AP15
SA_DQS_N_1 AP8
SA_DQS_N_2 AJ8
SA_DQS_N_3 AF3
SA_DQS_N_4 J3
SA_DQS_N_5 E2
SA_DQS_N_6 C5
SA_DQS_N_7 C11
SA_DQS_P_0 AP14
SA_DQS_P_1 AP9
SA_DQS_P_2 AK8
SA_DQS_P_3 AG3
SA_DQS_P_4 H3
SA_DQS_P_5 E3
SA_DQS_P_6 C6
SA_DQS_P_7 C12
SA_DQ_0
AR15
SA_DQ_1
AT14
SA_DQ_2
AM14
SA_DQ_3
AN14
SA_DQ_4
AT15
SA_DQ_5
AR14
SA_DQ_6
AN15
SA_DQ_7
AM15
SA_DQ_8
AM9
SA_DQ_9
AN9
SA_DQ_10
AM8
SA_DQ_11
AN8
SA_DQ_12
AR9
SA_DQ_13
AT9
SA_DQ_14
AR8
SA_DQ_15
AT8
SA_DQ_16
AJ9
SA_DQ_17
AK9
SA_DQ_18
AJ6
SA_DQ_19
AK6
SA_DQ_20
AJ10
SA_DQ_21
AK10
SA_DQ_22
AJ7
SA_DQ_23
AK7
SA_DQ_24
AF4
SA_DQ_25
AF5
SA_DQ_26
AF1
SA_DQ_27
AF2
SA_DQ_28
AG4
SA_DQ_29
AG5
SA_DQ_30
AG1
SA_DQ_31
AG2
SA_DQ_32
J1
SA_DQ_33
J2
SA_DQ_34
J5
SA_DQ_35
H5
SA_DQ_36
H2
SA_DQ_37
H1
SA_DQ_38
J4
SA_DQ_39
H4
SA_DQ_40
F2
SA_DQ_41
F1
SA_DQ_42
D2
SA_DQ_43
D3
SA_DQ_44
D1
SA_DQ_45
F3
SA_DQ_46
C3
SA_DQ_47
B3
SA_DQ_48
B5
SA_DQ_49
E6
SA_DQ_50
A5
SA_DQ_51
D6
SA_DQ_52
D5
SA_DQ_53
E5
SA_DQ_54
B6
SA_DQ_55
A6
SA_DQ_56
E12
SA_DQ_57
D12
SA_DQ_58
B11
SA_DQ_59
A11
SA_DQ_60
E11
SA_DQ_61
D11
SA_DQ_62
B12
SA_DQ_63
A12
SM_VREF
AM3
SA_DIMM_VREFDQ
F16
SB_DIMM_VREFDQ
F13
RC146
0_0402_5%
1 2
RC95
1K_0402_1%~D
12
RC151
24.9_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDP_COMP
EDP_HPD
EDP_HPD
EDP_COMP
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N3
CPU_HDMI_P3
CPU_DPD_DMC_P0
CPU_DPD_DMC_P1
CPU_DPD_DMC_N3
CPU_DPD_DMC_N1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_P3
CPU_DPD_DMC_N0
CPU_EDP_AUX
CPU_EDP_AUX#
CPU_EDP_N0
CPU_EDP_P0
CPU_EDP_P1
CPU_EDP_N1
CPU_EDP_N2
CPU_EDP_N3
CPU_EDP_P3
CPU_EDP_P2
+VCOMP_OUT
+VCCIO_OUT
CPU_EDP_HPD#<31>
CPU_HDMI_N0<36>
CPU_HDMI_N1<36>
CPU_HDMI_P1<36>
CPU_HDMI_P2<36>
CPU_HDMI_N3<36>
CPU_HDMI_N2<36>
CPU_HDMI_P3<36>
CPU_HDMI_P0<36>
CPU_DPD_DMC_N1<39>
CPU_DPD_DMC_P1<39>
CPU_DPD_DMC_N2<39>
CPU_DPD_DMC_P2<39>
CPU_DPD_DMC_N3<39>
CPU_DPD_DMC_P3<39>
CPU_DPD_DMC_N0<39>
CPU_DPD_DMC_P0<39>
CPU_EDP_AUX <31>
CPU_EDP_AUX# <31>
CPU_EDP_N0 <31>
CPU_EDP_P0 <31>
CPU_EDP_P1 <31>
CPU_EDP_N1 <31>
CPU_EDP_P2 <31>
CPU_EDP_N2 <31>
CPU_EDP_N3 <31>
CPU_EDP_P3 <31>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU (4/7) FDI,eDP,DDI
Custom
9 61Friday, June 22, 2012
2012/06/22 2013/06/21
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
COMPENSATION PU FOR eDP
HPD INVERSION FOR EDP
Compal Electronics, Inc.
DMC
HDMI
RC75
100K_0402_5%~D
12
RC124.9_0402_1%~D
12
T77PAD~D @
G
D
S
QC10
BSS138_SOT23~D
2
13
Haswell rPGA EDS
eDP
DDI
8 OF 9
JCPU1H
INTEL_HASWELL_HASWELL
CONN@
DDIB_TXBN_0
T28
DDIB_TXBP_0
U28
DDIB_TXBN_1
T30
DDIB_TXBP_1
U30
DDIB_TXBN_2
U29
DDIB_TXBP_2
V29
DDIB_TXBN_3
U31
DDIB_TXBP_3
V31
DDIC_TXCN_0
T34
DDIC_TXCP_0
U34
DDIC_TXCN_1
U35
DDIC_TXCP_1
V35
DDIC_TXCN_2
U32
DDIC_TXCP_2
T32
DDIC_TXCN_3
U33
DDIC_TXCP_3
V33
DDID_TXDN_0
P29
DDID_TXDP_0
R29
DDID_TXDN_1
N28
DDID_TXDP_1
P28
DDID_TXDN_2
P31
DDID_TXDP_2
R31
DDID_TXDN_3
N30
DDID_TXDP_3
P30
EDP_AUXN M27
EDP_AUXP N27
EDP_HPD P27
EDP_TXN_0 P35
EDP_TXN_1 N34
EDP_TXP_0 R35
EDP_TXP_1 P34
EDP_RCOMP E24
RSVD R27
FDI_TXN_0 P33
FDI_TXP_0 R33
FDI_TXN_1 N32
FDI_TXP_1 P32
RC65
10K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG7
CFG_RCOMP
H_CPU_RSVD
H_CPU_TESTLO
CFG4
CFG17
CFG16
CFG19
CFG18
CFG11
CFG10
CFG2
CFG1
CFG15
CFG14
CFG6
CFG5
CFG4
CFG3
CFG0
CFG9
CFG8
CFG7
CFG13
CFG12
CFG6
CFG5
CFG_RCOMP
H_CPU_RSVD
H_CPU_TESTLO
CFG2
+VCC_CORE
CFG18 <6>
CFG17 <6>
CFG19 <6>
CFG1<6>
CFG0<6>
CFG16 <6>
CFG4<6>
CFG3<6>
CFG2<6>
CFG8<6>
CFG7<6>
CFG6<6>
CFG5<6>
CFG11<6>
CFG10<6>
CFG9<6>
CFG13<6>
CFG14<6>
CFG15<6>
CFG12<6>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU (5/7) RSVD,CFG
Custom
10 61Friday, June 22, 2012
2012/06/22 2013/06/21
CFG2
PEG Static Lane Reversal - CFG2 is for the 16x
0:Lane Reversed
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
PCIE Port Bifurcation Straps
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
11: (Default) x16 - Device 1 functions 1 and 2 disabled
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
0: PEG Wait for BIOS for training
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately
following xxRESETB de assertion
CFG STRAPS for CPU
Compal Electronics, Inc.
T90PAD~D @
T81 PAD~D@
T94 PAD~D@
T86 PAD~D@
T108PAD~D@
T106PAD~D @
T78 PAD~D@
T83 PAD~D@
T100PAD~D @
T91PAD~D @
T92PAD~D @
T82 PAD~D@
RC91
1K_0402_1%~D
@
12
T96PAD~D @
RC58 49.9_0402_1%~D
12
T97PAD~D @
T79 PAD~D@
RC77
1K_0402_1%~D
12
RC76
1K_0402_1%~D
@
12
T80 PAD~D@
Haswell rPGA EDS
9 OF 9
JCPU1I
INTEL_HASWELL_HASWELL
CONN@
RSVD_TP
AT1
RSVD_TP
AT2
RSVD
AD10
RSVD_TP
A34
RSVD_TP
A35
RSVD
W29
RSVD
W28
RSVD
G26
RSVD
W33
RSVD
AL30
RSVD
AL29
VCC
F25
RSVD_TP
C35
RSVD_TP
B35
RSVD_TP
AL25
RSVD
W30
RSVD
W31
TESTLO
W34
CFG_0
AT20
CFG_1
AR20
CFG_2
AP20
CFG_3
AP22
CFG_4
AT22
CFG_5
AN22
CFG_6
AT25
CFG_7
AN23
CFG_8
AR24
CFG_9
AT23
CFG_10
AN20
CFG_11
AP24
CFG_12
AP26
CFG_13
AN25
CFG_14
AN26
CFG_15
AP25
RSVD_TP C23
RSVD_TP B23
RSVD_TP D24
RSVD_TP D23
CFG_RCOMP AT31
CFG_16 AR21
CFG_18 AR23
CFG_17 AP21
CFG_19 AP23
RSVD AR33
RSVD G6
RSVD AM27
RSVD AM26
RSVD F5
RSVD AM2
RSVD K6
RSVD_TP AR1
RSVD E18
RSVD A2
RSVD_TP E21
RSVD_TP E20
RSVD AP27
RSVD AR26
RSVD AL31
RSVD AL32
NC B1
RSVD U10
RSVD P10
T102PAD~D @
T109PAD~D @
T105PAD~D @
T107PAD~D @
T98PAD~D @
RC60 49.9_0402_1%~D
12
T95PAD~D @
T88PAD~D @
T104PAD~D @
RC92
1K_0402_1%~D
@
12
RC59 49.9_0402_1%~D
12
T89PAD~D @
T99PAD~D @
T101PAD~D@
T84 PAD~D@
T87PAD~D @
RC90
1K_0402_1%~D
@
12
T85 PAD~D@
T103PAD~D@
T111PAD~D @
T93PAD~D @
T110PAD~D@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RUN_ON_CPU1.5VS3#
VIDSOUT
VSSSENSE
CPU_PW R_DEBUG
VSSSENSE_R
VCCSENSE
VIDSCLK
VCCSENSE_R
H_CPU_SVIDALRT#
VCCSENSE_R
H_CPU_SVIDALRT#
RUN_ON_CPU1.5VS3RUN_ON_CPU1.5VS3
VIDSOUT
+VCC_CORE
+VCC_CORE
+1.35V_CPU_VDDQ
+VCCIO_OUT
+VCCIO_OUT
+VCOMP_OUT
+1.05VS
+1.35V
+VCC_CORE
+1.05VS
+VCC_CORE
+VCCIO_OUT
+3VALW
+1.35V
+VCCIO_OUT
B+_BIAS
+1.35V_CPU_VDDQ
+1.35V_CPU_VDDQ
VIDSOUT<62>
VIDSCLK<62>
VIDALERT_N<62>
VSSSENSE<62>
VCCSENSE<62>
CPU_PW R_DEBUG<6>
RUN_ON_CPU1.5VS3# <6,56>
CPU1.5V_S3_GATE<43>
VSSSENSE_R <11>
SUSP#<43,56,59,61>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
CPU (6/7) PWR
Custom
11 61Friday, June 22, 2012
2012/06/22 2013/06/21
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
VDDQ DECOUPLING
SVID ALERT
SVID DATA
VCC_SENSE
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
CAD Note: Place the PU resistors close to CPU
RC63 close to CPU 300 - 1500mils
+1.35V_CPU_VDDQ Source
Compal Electronics, Inc.
T114 PAD~D@
RC143
1M_0402_5%~D
12
CC169
10U_0603_6.3V6M~D
1
2
CC186
22U_0805_6.3V6M~D
C_0805NEW
1
2
CC166
10U_0603_6.3V6M~D
1
2
T156 PAD~D@
RC6943_0402_5%~D
12
CC161
10U_0603_6.3V6M~D
1
2
RC66
100_0402_1%~D
12
CC189
22U_0805_6.3V6M~D
C_0805NEW
1
2
T162 PAD~D@
T113 PAD~D@
CC180
10U_0603_6.3V6M~D
1
2
CC162
10U_0603_6.3V6M~D
1
2
CC168
10U_0603_6.3V6M~D
1
2
RC71
10K_0402_5%~D
@
12
CC181
22U_0805_6.3V6M~D
1
2
CC170
10U_0603_6.3V6M~D
1
2
T112 PAD~D@
T157 PAD~D@
T159 PAD~D@
T160 PAD~D@
CC187
22U_0805_6.3V6M~D
C_0805NEW
1
2
T152 PAD~D@
CC151 0.1U_0402_10V7K~D
12
T168 PAD~D@
RC73
20K_0402_5%~D
@
12
Haswell rPGA EDS
5 OF 9
JCPU1E
INTEL_HASWELL_HASWELL
CONN@
RSVD
K27
RSVD
L27
RSVD
T27
RSVD
V27
VDDQ
AB11
VDDQ
AB2
VDDQ
AB5
VDDQ
AB8
VDDQ
AE11
VDDQ
AE2
VDDQ
AE5
VDDQ
AE8
VDDQ
AH11
VDDQ
K11
VDDQ
N11
VDDQ
N8
VDDQ
T11
VDDQ
T2
VDDQ
T5
VDDQ
T8
VDDQ
W11
VDDQ
W2
VDDQ
W5
VDDQ
W8
RSVD
N26
VCC
K26
RSVD
AL27
RSVD
AK27
VCC_SENSE
AL35
RSVD
E17
VCCIO_OUT
AN35
VCCIO2PCH
A23
VCCIOA_OUT
F22
RSVD
W32
RSVD
AL16
VSS
J27
RSVD
AL13
VIDALERT
AM28
VIDSCLK
AM29
VIDSOUT
AL28
VSS
AP35
PWR_DEBUG
H27
RSVD
AP34
RSVD
AT35
RSVD
AR35
RSVD
AR32
RSVD
AL26
RSVD
AT34
RSVD
AL22
RSVD
AT33
RSVD
AM21
RSVD
AM25
RSVD
AM22
RSVD
AM20
RSVD
AM24
RSVD
AL19
RSVD
AM23
RSVD
AT32
VCC AA26
VCC AA28
VCC AA34
VCC AA30
VCC AA32
VCC AB26
VCC AB29
VCC AB25
VCC AB27
VCC AB28
VCC AB30
VCC AB31
VCC AB33
VCC AB34
VCC AB32
VCC AC26
VCC AB35
VCC AC28
VCC AD25
VCC AC30
VCC AD28
VCC AC32
VCC AD31
VCC AC34
VCC AD34
VCC AD26
VCC AD27
VCC AD29
VCC AD30
VCC AD32
VCC AD33
VCC AD35
VCC AE26
VCC AE32
VCC AE28
VCC AE30
VCC AG28
VCC AG34
VCC AE34
VCC AF25
VCC AF26
VCC AF27
VCC AF28
VCC AF29
VCC AF30
VCC AF31
VCC AF32
VCC AF33
VCC AF34
VCC AF35
VCC AG26
VCC AH26
VCC AH29
VCC AG30
VCC AG32
VCC AH32
VCC AH35
VCC AH25
VCC AH27
VCC AH28
VCC AH30
VCC AH31
VCC AH33
VCC AH34
VCC AJ25
VCC AJ26
VCC AJ27
VCC AJ28
VCC AJ29
VCC AJ30
VCC AJ31
VCC AJ32
VCC AJ33
VCC AJ34
VCC AJ35
VCC G25
VCC H25
VCC J25
VCC K25
VCC L25
VCC M25
VCC N25
VCC P25
VCC R25
VCC T25
VCC U25
VCC U26
VCC V25
VCC V26
VCC W 26
VCC W 27
VCC
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
RC670_0402_5%~D
12
T151 PAD~D@
T154 PAD~D@
CC163
10U_0603_6.3V6M~D
1
2
CC184
22U_0805_6.3V6M~D
C_0805NEW
1
2
CC164
10U_0603_6.3V6M~D
1
2
RC79 0_0402_5%~D
1 2
CC183
22U_0805_6.3V6M~D
C_0805NEW
1
2
CC136
0.022U_0402_25V7K~D
1
2
CC135
10U_0603_6.3V6M~D
1
2
CC152 0.1U_0402_10V7K~D
12
RC72
330K_0402_5%~D
12
T115 PAD~D@
T163 PAD~D@
CC182
22U_0805_6.3V6M~D
C_0805NEW
1
2
QC4B
DMN66D0LDW-7_SOT363-6~D
34
5
T158 PAD~D@
RC63
110_0402_1%~D
12
+
CC167
330U_D2_2VM_R6M~D
1
2
RC93 0_0402_5%~D@
1 2
T116 PAD~D@
RC74
100K_0402_5%~D
12
CC165
10U_0603_6.3V6M~D
1
2
QC3
AO4304L_SO8
6
2
4
1
3
5
7
8
QC4A
DMN66D0LDW-7_SOT363-6~D
61
2
CC188
22U_0805_6.3V6M~D
C_0805NEW
1
2
CC190
22U_0805_6.3V6M~D
C_0805NEW
1
2
RC4 0_0603_5%~D@
12
RC61
75_0402_1%~D
12
CC185
22U_0805_6.3V6M~D
C_0805NEW
1
2
T153 PAD~D@
RC680_0402_5%~D
12
RC80
10K_0402_5%~D
@
12
RC70
100_0402_1%~D
12
CC191
22U_0805_6.3V6M~D
C_0805NEW
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSSENSE_R <10>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU (7/7) VSS
Custom
12 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
Haswell rPGA EDS
6 OF 9
JCPU1F
INTEL_HASWELL_HASWELL
CONN@
VSS
A10
VSS
A13
VSS
A16
VSS
A19
VSS
A22
VSS
A25
VSS
A27
VSS
A29
VSS
A3
VSS
A31
VSS
A33
VSS
A4
VSS
A7
VSS
AA11
VSS
AA25
VSS
AA27
VSS
AA31
VSS
AA29
VSS
AB1
VSS
AB10
VSS
AA33
VSS
AA35
VSS
AB3
VSS
AC25
VSS
AC27
VSS
AB4
VSS
AB6
VSS
AB7
VSS
AB9
VSS
AC11
VSS
AD11
VSS
AC29
VSS
AC31
VSS
AC33
VSS
AC35
VSS
AD7
VSS
AE1
VSS
AE10
VSS
AE25
VSS
AE29
VSS
AE3
VSS
AE27
VSS
AE35
VSS
AE4
VSS
AE6
VSS
AE7
VSS
AE9
VSS
AF11
VSS
AF6
VSS
AF8
VSS
AG11
VSS
AG25
VSS
AE31
VSS
AG31
VSS
AE33
VSS
AG6
VSS
AH1
VSS
AH10
VSS
AH2
VSS
AG27
VSS
AG29
VSS
AH3
VSS
AG33
VSS
AG35
VSS
AH4
VSS
AH5
VSS
AH6
VSS
AH7
VSS
AH8
VSS
AH9
VSS
AJ11
VSS
AJ5
VSS
AK11
VSS
AK25
VSS
AK26
VSS
AK28
VSS
AK29
VSS
AK30
VSS
AK32
VSS
E19
VSS AK34
VSS AK5
VSS AL1
VSS AL10
VSS AL11
VSS AL12
VSS AL14
VSS AL15
VSS AL17
VSS AL18
VSS AL2
VSS AL20
VSS AL21
VSS AL23
VSS E22
VSS AL3
VSS AL4
VSS AL5
VSS AL6
VSS AL7
VSS AL8
VSS AL9
VSS AM10
VSS AM13
VSS AM16
VSS AM19
VSS E25
VSS AM32
VSS AM4
VSS AM7
VSS AN10
VSS AN13
VSS AN16
VSS AN19
VSS AN2
VSS AN21
VSS AN24
VSS AN27
VSS AN30
VSS AN34
VSS AN4
VSS AN7
VSS AP1
VSS AP10
VSS AP13
VSS AP16
VSS AP19
VSS AP4
VSS AP7
VSS W25
RSVD AR10
VSS AR13
VSS AR16
VSS AR19
VSS AR2
VSS AR22
VSS AR25
VSS AR28
VSS AR31
VSS AR34
VSS AR4
VSS AR7
VSS AT10
VSS AT13
VSS AT16
VSS AT19
VSS AT21
VSS AT24
VSS AT27
VSS AT3
VSS AT30
VSS AT4
VSS AT7
VSS B10
VSS B13
VSS B16
VSS B19
VSS B2
VSS B22 T120PAD~D @
Haswell rPGA EDS
7 OF 9
JCPU1G
INTEL_HASWELL_HASWELL
CONN@
VSS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
RSVD
J28
VSS
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS K10
VSS K2
VSS K29
VSS K3
VSS K31
VSS K33
VSS K35
VSS K4
VSS K5
VSS K7
VSS K8
VSS K9
VSS L11
VSS L26
VSS L6
VSS M11
VSS M26
VSS M28
VSS M30
VSS M32
VSS M34
VSS M6
VSS N1
VSS N10
VSS N2
VSS N29
VSS N3
VSS N31
VSS N33
VSS N35
VSS N4
VSS N5
VSS N6
VSS N7
VSS N9
VSS P11
VSS P26
VSS P5
VSS R11
VSS R26
VSS R28
VSS R30
VSS R32
VSS R34
VSS R5
VSS T1
VSS T10
VSS T29
VSS T3
VSS T31
VSS T33
VSS T35
VSS T4
VSS T6
VSS T7
VSS T9
VSS U11
VSS U27
VSS V11
VSS V28
VSS V30
VSS V32
VSS V34
VSS W1
VSS W10
VSS W3
VSS W35
VSS W4
VSS W6
VSS W7
VSS W9
VSS Y11
RSVD H11
RSVD AL24
RSVD F19
RSVD T26
VSS_SENSE AK35
RSVD AK33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_THERMAL#
DDR_A_D18
DDR3_DRAMRST#_R
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D19
DDR_A_D21
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D45
DDR_A_D46
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
DDR_A_MA3
DDR_A_MA4DDR_A_MA5
DDR_A_MA6DDR_A_MA8
DDR_A_MA7DDR_A_MA9
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS5_DIMMC#
DDR_CS4_DIMMC#
M_CLK_DDR4
M_CLK_DDR#4
M_CLK_DDR5
M_CLK_DDR#5
DDR_CKE4_DIMMC DDR_CKE5_DIMMC
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
M_ODT4
M_ODT5
DDR_A_D63
DDR_A_MA15
DDR_A_D23
DDR_A_D31
DDR_A_D17
DDR_A_D9 DDR_A_D13
DDR_A_D20DDR_A_D16
DDR_A_D25
DDR_A_D30
DDR_A_D24
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A_D39
DDR_A_D54
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D48
DDR3_DRAMRST#_R
+1.35V
+0.675VS
+1.35V
+1.35V+1.35V
+0.675VS+0.675VS
+V_SM_VREF_CNT
+1.35V
+DIMM0_1_VREF_CPU
+3VS
+3VS
M_THERMAL# <13,14,15,43>
DDR3_DRAMRST#_CPU <6>DDR3_DRAMRST#_R<13,14,15>
DDR_A_D[0..63]<7,14>
DDR_A_DQS[0..7]<7,14>
DDR_A_MA[0..15]<7,14>
DDR_A_DQS#[0..7]<7,14>
DDR_CKE4_DIMMC<7>
DDR_A_BS2<7,14>
DDR_CS5_DIMMC#<7>
DDR_A_WE#<7,14>
DDR_A_CAS#<7,14>
DDR_A_BS0<7,14>
DDR_A_BS1 <7,14>
M_ODT4 <7>
DDR_A_RAS# <7,14>
M_CLK_DDR5 <7>
M_CLK_DDR#5 <7>
M_CLK_DDR#4<7>
M_CLK_DDR4<7>
DDR_CKE5_DIMMC <7>
DDR_CS4_DIMMC# <7>
M_ODT5 <7>
PCH_SMBCLK <6,13,14,15,19,49,50,51,53>
PCH_SMBDATA <6,13,14,15,19,49,50,51,53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DDRIII DIMMA
Custom
13 61Friday, June 22, 2012
2012/06/22 2013/06/21
CRB Rev 0.7 is depop
Layout Note:
Place near JDIMMA.203,204
JDIMMA H=4mm
All VREF traces should
have 20 mil trace width
Layout Note:
Place near JDIMMA
SA0
SA1
1
0
0
1
1
DIMM1A
DIMMB
DIMMC
DIMMD
1
0
0
CPU
2(H8)
JDIMMA(H4)
3(H5.2)
4(H9.2)
Compal Electronics, Inc.
All VREF traces should
have 20 mil trace width
CD10
10U_0603_6.3V6M~D
1
2
CD5
1U_0402_6.3V6K~D
1
2
CD20
1U_0402_6.3V6K~D
1
2
CD6
1U_0402_6.3V6K~D
1
2
RD29 1K_0402_5%~D
1 2
JDIMM1
TYCO_2-2013022-1
CONN@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS 2
DQ4 4
DQ5 6
VSS 8
DQS0# 10
DQS0 12
VSS 14
DQ6 16
DQ7 18
VSS 20
DQ12 22
DQ13 24
VSS 26
DM1 28
RESET# 30
VSS 32
DQ14 34
DQ15 36
VSS 38
DQ20 40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21 42
VSS 44
DM2 46
VSS 48
DQ22 50
DQ23 52
VSS 54
DQ28 56
DQ29 58
VSS 60
DQS3# 62
DQS3 64
VSS 66
DQ30 68
DQ31 70
VSS 72
CKE1 74
VDD 76
A15 78
A14 80
VDD 82
A11 84
A7 86
VDD 88
A6 90
A4 92
VDD 94
A2 96
A0 98
VDD 100
CK1 102
CK1# 104
VDD 106
BA1 108
RAS# 110
VDD 112
S0# 114
ODT0 116
VDD 118
ODT1 120
NC 122
VDD 124
VREF_CA 126
VSS 128
DQ36 130
DQ37 132
VSS 134
DM4 136
VSS 138
DQ38 140
DQ39 142
VSS 144
DQ44 146
DQ45 148
VSS 150
DQS5# 152
DQS5 154
VSS 156
DQ46 158
DQ47 160
VSS 162
DQ52 164
DQ53 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
EVENT# 198
SDA 200
SA1
201
VTT
203
GND1
205
SCL 202
VTT 204
GND2 206
BOSS1
207 BOSS2 208
CD18
1U_0402_6.3V6K~D
1
2
CD2
0.1U_0402_25V6K~D
1
2
CD13
10U_0603_6.3V6M~D
@
1
2
CD7
10U_0603_6.3V6M~D
1
2
CD19
1U_0402_6.3V6K~D
1
2
CD8
10U_0603_6.3V6M~D
1
2
CD1
2.2U_0402_6.3V6M
1
2
CD11
10U_0603_6.3V6M~D
1
2
RD38
10K_0402_5%~D
1 2
CD4
1U_0402_6.3V6K~D
1
2
+
CD14
330U_SX_2VY~D
1
2
CD3
1U_0402_6.3V6K~D
1
2
RD22
10K_0402_5%~D
1 2
CD15
2.2U_0402_6.3V6M
1
2
CD21
0.1U_0402_25V6K~D
1
2
RD39
10K_0402_5%~D
@
1 2
CD74
10U_0603_6.3V6M~D
1
2
RD27
1K_0402_5%~D
@
12
CD17
1U_0402_6.3V6K~D
1
2
CD22
2.2U_0402_6.3V6M
1
2
RD21
10K_0402_5%~D
@
1 2
CD16
0.1U_0402_25V6K~D
1
2
CD9
10U_0603_6.3V6M~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_THERMAL#
DDR_B_D22
DDR_B_MA7
DDR_B_D20
DDR_B_MA14
M_ODT6
DDR_B_D52
DDR_B_MA6
DDR_B_D36
DDR_B_D37
DDR3_DRAMRST#_R
DDR_B_D27
DDR_B_D21
DDR_B_D23
DDR_B_DQS#3
DDR_B_D44
DDR_B_D14
DDR_CKE7_DIMMD
DDR_B_D46
DDR_B_D53
DDR_B_D54
DDR_B_MA4
DDR_B_D6
DDR_B_D7
DDR_B_DQS3
DDR_B_BS1
DDR_B_D38
DDR_B_D45
DDR_B_D15
M_ODT7
DDR_B_D47
DDR_B_D55
DDR_B_D28
M_CLK_DDR7
DDR_B_RAS#
DDR_B_D29
DDR_B_MA2
M_CLK_DDR#7
DDR_B_D30
DDR_B_MA11
DDR_B_DQS#5
DDR_B_D60
DDR_B_D12
DDR_B_MA0
DDR_B_D39
DDR_B_D31
DDR_CS6_DIMMD#
DDR_B_DQS5
DDR_CKE6_DIMMD
DDR_B_D13
DDR_B_D58
DDR_B_D59
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_D4
DDR_B_MA8
DDR_B_D5
DDR_B_MA5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR6
M_CLK_DDR#6
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA15
DDR_B_MA13
DDR_CS7_DIMMD#
DDR_B_D0
DDR_B_D1
DDR_B_D32
DDR_B_D33
DDR_B_D2
DDR_B_DQS#4
DDR_B_D3
DDR_B_DQS4
DDR_B_D8
DDR_B_D34
DDR_B_D9
DDR_B_D35
DDR_B_DQS#1
DDR_B_D40
DDR_B_D61
DDR_B_DQS1
DDR_B_D41
DDR_B_DQS#7
DDR_B_D10
DDR_B_DQS7
DDR_B_D11
DDR_B_D42
DDR_B_D62
DDR_B_D16
DDR_B_D43
DDR_B_D63
DDR_B_D17
DDR_B_D48
DDR_B_DQS#2
DDR_B_D49
DDR_B_DQS2
DDR_B_DQS#6
DDR_B_D18
DDR_B_DQS6
DDR_B_D19
DDR_B_D50
DDR_B_D24
DDR_B_D51
DDR_B_D25
DDR_B_D56
DDR_B_D57
DDR_B_D26
+0.675VS
+3VS
+3VS
+1.35V
+1.35V
+0.675VS
+1.35V
+1.35V
+V_SM_VREF_CNT
+DIMM0_1_CA_CPU
+0.675VS
M_THERMAL# <12,14,15,43>
DDR_B_DQS[0..7]<7,15>
DDR_B_D[0..63]<7,15>
DDR_B_CAS#<7,15>
DDR_B_DQS#[0..7]<7,15>
DDR_B_MA[0..15]<7,15>
DDR_B_BS0<7,15>
DDR_CKE6_DIMMD<7>
DDR_B_WE#<7,15>
DDR_CKE7_DIMMD <7>
DDR_B_BS2<7,15>
DDR_B_BS1 <7,15>
DDR_B_RAS# <7,15>
DDR_CS6_DIMMD# <7>
DDR_CS7_DIMMD#<7>
M_ODT6 <7>
M_ODT7 <7>
M_CLK_DDR#7 <7>
M_CLK_DDR7 <7>
DDR3_DRAMRST#_R <12,14,15>
M_CLK_DDR#6<7>
M_CLK_DDR6<7>
PCH_SMBDATA <6,12,14,15,19,49,50,51,53>
PCH_SMBCLK <6,12,14,15,19,49,50,51,53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DDRIII DIMMB
Custom
14 61Friday, June 22, 2012
2012/06/22 2013/06/21
SA0
SA1
1
0
0
1
1
DIMMA
DIMMB
DIMMC
DIMMD
1
0
0
Layout Note:
Place near JDIMMB
JDIMMB H=4mm
All VREF traces should
have 20 mil trace width
Layout Note:
Place near JDIMMB.203,204
CPU
JDIMMB(H8)
1(H4)
3(H5.2)
4(H9.2)
Compal Electronics, Inc.
All VREF traces should
have 20 mil trace width
CD39
1U_0402_6.3V6K~D
1
2
CD31
10U_0603_6.3V6M~D
1
2
CD26
1U_0402_6.3V6K~D
1
2
RD41
10K_0402_5%~D
@
1 2
CD41
1U_0402_6.3V6K~D
1
2
RD23
10K_0402_5%~D
@
1 2
CD38
0.1U_0402_25V6K~D
1
2
CD27
1U_0402_6.3V6K~D
1
2
CD32
10U_0603_6.3V6M~D
1
2
CD29
10U_0603_6.3V6M~D
1
2
CD37
2.2U_0402_6.3V6M
1
2
CD28
1U_0402_6.3V6K~D
1
2
CD24
0.1U_0402_25V6K~D
1
2
CD40
1U_0402_6.3V6K~D
1
2
JDIMM2
SUYIN_600025HB204G251ZL
CONN@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS 2
DQ4 4
DQ5 6
VSS 8
DQS0# 10
DQS0 12
VSS 14
DQ6 16
DQ7 18
VSS 20
DQ12 22
DQ13 24
VSS 26
DM1 28
RESET# 30
VSS 32
DQ14 34
DQ15 36
VSS 38
DQ20 40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21 42
VSS 44
DM2 46
VSS 48
DQ22 50
DQ23 52
VSS 54
DQ28 56
DQ29 58
VSS 60
DQS3# 62
DQS3 64
VSS 66
DQ30 68
DQ31 70
VSS 72
CKE1 74
VDD 76
A15 78
A14 80
VDD 82
A11 84
A7 86
VDD 88
A6 90
A4 92
VDD 94
A2 96
A0 98
VDD 100
CK1 102
CK1# 104
VDD 106
BA1 108
RAS# 110
VDD 112
S0# 114
ODT0 116
VDD 118
ODT1 120
NC 122
VDD 124
VREF_CA 126
VSS 128
DQ36 130
DQ37 132
VSS 134
DM4 136
VSS 138
DQ38 140
DQ39 142
VSS 144
DQ44 146
DQ45 148
VSS 150
DQS5# 152
DQS5 154
VSS 156
DQ46 158
DQ47 160
VSS 162
DQ52 164
DQ53 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
EVENT# 198
SDA 200
SA1
201
VTT
203
GND1
205
SCL 202
VTT 204
GND2 206
BOSS1
207 BOSS2 208
CD30
10U_0603_6.3V6M~D
1
2
+
CD36
330U_SX_2VY~D
1
2
CD34
10U_0603_6.3V6M~D
1
2
CD25
1U_0402_6.3V6K~D
1
2
CD35
10U_0603_6.3V6M~D
@
1
2
CD23
2.2U_0402_6.3V6M
1
2
CD33
10U_0603_6.3V6M~D
1
2
CD42
1U_0402_6.3V6K~D
1
2
RD24
10K_0402_5%~D
1 2
CD43
2.2U_0402_6.3V6M
1
2
RD40
10K_0402_5%~D
1 2
CD44
0.1U_0402_25V6K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_THERMAL#
DDR_A_D18
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D19
DDR_A_D21
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D45
DDR_A_D46
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
DDR_A_MA3
DDR_A_MA4DDR_A_MA5
DDR_A_MA6DDR_A_MA8
DDR_A_MA7DDR_A_MA9
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
M_ODT0
M_ODT1
DDR_A_D63
DDR_A_MA15
DDR_A_D23
DDR_A_D31
DDR_A_D17
DDR_A_D9 DDR_A_D13
DDR_A_D20DDR_A_D16
DDR_A_D25
DDR_A_D30
DDR_A_D24
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A_D39
DDR_A_D54
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D48
DDR3_DRAMRST#_R
+3VS
+0.675VS
+3VS
+0.675VS
+1.35V
+1.35V+1.35V
+0.675VS
+V_SM_VREF_CNT
+1.35V
+DIMM0_1_VREF_CPU
M_THERMAL# <12,13,15,43>
DDR_A_D[0..63]<7,12>
DDR_A_DQS[0..7]<7,12>
DDR_A_MA[0..15]<7,12>
DDR_A_DQS#[0..7]<7,12>
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7,12>
DDR_CS1_DIMMA#<7>
DDR_A_WE#<7,12>
DDR_A_CAS#<7,12>
DDR_A_BS0<7,12>
DDR_A_BS1 <7,12>
M_ODT0 <7>
DDR_A_RAS# <7,12>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>M_CLK_DDR#0<7>
M_CLK_DDR0<7>
DDR_CKE1_DIMMA <7>
DDR_CS0_DIMMA# <7>
M_ODT1 <7>
PCH_SMBCLK <6,12,13,15,19,49,50,51,53>
PCH_SMBDATA <6,12,13,15,19,49,50,51,53>
DDR3_DRAMRST#_R <12,13,15>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DDRIII DIMMC
Custom
15 61Friday, June 22, 2012
2012/06/22 2013/06/21
Layout Note:
Place near JDIMMC.203,204
JDIMMC H=5.2mm
All VREF traces should
have 20 mil trace width
Layout Note:
Place near JDIMMC
SA0
SA1
1
0
0
1
1
DIMMA
DIMMB
DIMMC
DIMMD
1
0
0
CPU
2(H8)
1(H4)
JDIMMC(H5.2)
4(H9.2)
Compal Electronics, Inc.
All VREF traces should
have 20 mil trace width
CD56
10U_0603_6.3V6M~D
1
2
CD53
0.1U_0402_25V6K~D
1
2
CD75
10U_0603_6.3V6M~D
1
2
CD58
0.1U_0402_25V6K~D
1
2
CD57
1U_0402_6.3V6K~D
1
2
CD60
2.2U_0402_6.3V6M
1
2
CD50
2.2U_0402_6.3V6M
1
2
CD46
10U_0603_6.3V6M~D
1
2
CD62
10U_0603_6.3V6M~D
1
2
CD64
1U_0402_6.3V6K~D
1
2
RD25
10K_0402_5%~D
@
1 2
RD42
10K_0402_5%~D
1 2
CD49
10U_0603_6.3V6M~D
1
2
CD54
1U_0402_6.3V6K~D
1
2
CD63
1U_0402_6.3V6K~D
1
2
CD12
1U_0402_6.3V6K~D
1
2
CD52
2.2U_0402_6.3V6M
1
2
JDIMM3
LCN_DAN06-K4526-0103
CONN@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS 2
DQ4 4
DQ5 6
VSS 8
DQS0# 10
DQS0 12
VSS 14
DQ6 16
DQ7 18
VSS 20
DQ12 22
DQ13 24
VSS 26
DM1 28
RESET# 30
VSS 32
DQ14 34
DQ15 36
VSS 38
DQ20 40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21 42
VSS 44
DM2 46
VSS 48
DQ22 50
DQ23 52
VSS 54
DQ28 56
DQ29 58
VSS 60
DQS3# 62
DQS3 64
VSS 66
DQ30 68
DQ31 70
VSS 72
CKE1 74
VDD 76
A15 78
A14 80
VDD 82
A11 84
A7 86
VDD 88
A6 90
A4 92
VDD 94
A2 96
A0 98
VDD 100
CK1 102
CK1# 104
VDD 106
BA1 108
RAS# 110
VDD 112
S0# 114
ODT0 116
VDD 118
ODT1 120
NC 122
VDD 124
VREF_CA 126
VSS 128
DQ36 130
DQ37 132
VSS 134
DM4 136
VSS 138
DQ38 140
DQ39 142
VSS 144
DQ44 146
DQ45 148
VSS 150
DQS5# 152
DQS5 154
VSS 156
DQ46 158
DQ47 160
VSS 162
DQ52 164
DQ53 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
EVENT# 198
SDA 200
SA1
201
VTT
203
GND1
205
SCL 202
VTT 204
GND2 206
BOSS1
207 BOSS2 208
CD51
1U_0402_6.3V6K~D
1
2
CD48
0.1U_0402_25V6K~D
1
2
+
CD45
330U_SX_2VY~D
1
2
RD26
10K_0402_5%~D
1 2
CD47
1U_0402_6.3V6K~D
1
2
CD59
10U_0603_6.3V6M~D
1
2
RD43
10K_0402_5%~D
@
1 2
CD55
1U_0402_6.3V6K~D
1
2
CD61
10U_0603_6.3V6M~D
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_THERMAL#
DDR_B_D22
DDR_B_MA7
DDR_B_D20
DDR_B_MA14
M_ODT2
DDR_B_D52
DDR_B_MA6
DDR_B_D36
DDR_B_D37
DDR3_DRAMRST#_R
DDR_B_D27
DDR_B_D21
DDR_B_D23
DDR_B_DQS#3
DDR_B_D44
DDR_B_D14
DDR_CKE3_DIMMB
DDR_B_D46
DDR_B_D53
DDR_B_D54
DDR_B_MA4
DDR_B_D6
DDR_B_D7
DDR_B_DQS3
DDR_B_BS1
DDR_B_D38
DDR_B_D45
DDR_B_D15
M_ODT3
DDR_B_D47
DDR_B_D55
DDR_B_D28
M_CLK_DDR3
DDR_B_RAS#
DDR_B_D29
DDR_B_MA2
M_CLK_DDR#3
DDR_B_D30
DDR_B_MA11
DDR_B_DQS#5
DDR_B_D60
DDR_B_D12
DDR_B_MA0
DDR_B_D39
DDR_B_D31
DDR_CS2_DIMMB#
DDR_B_DQS5
DDR_CKE2_DIMMB
DDR_B_D13
DDR_B_D58
DDR_B_D59
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_D4
DDR_B_MA8
DDR_B_D5
DDR_B_MA5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA15
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D0
DDR_B_D1
DDR_B_D32
DDR_B_D33
DDR_B_D2
DDR_B_DQS#4
DDR_B_D3
DDR_B_DQS4
DDR_B_D8
DDR_B_D34
DDR_B_D9
DDR_B_D35
DDR_B_DQS#1
DDR_B_D40
DDR_B_D61
DDR_B_DQS1
DDR_B_D41
DDR_B_DQS#7
DDR_B_D10
DDR_B_DQS7
DDR_B_D11
DDR_B_D42
DDR_B_D62
DDR_B_D16
DDR_B_D43
DDR_B_D63
DDR_B_D17
DDR_B_D48
DDR_B_DQS#2
DDR_B_D49
DDR_B_DQS2
DDR_B_DQS#6
DDR_B_D18
DDR_B_DQS6
DDR_B_D19
DDR_B_D50
DDR_B_D24
DDR_B_D51
DDR_B_D25
DDR_B_D56
DDR_B_D57
DDR_B_D26
+0.675VS
+3VS
+3VS
+1.35V
+1.35V
+0.675VS
+1.35V
+1.35V
+V_SM_VREF_CNT
+DIMM0_1_CA_CPU
+0.675VS
M_THERMAL# <12,13,14,43>
DDR_B_DQS[0..7]<7,13>
DDR_B_D[0..63]<7,13>
DDR_B_CAS#<7,13>
DDR_B_DQS#[0..7]<7,13>
DDR_B_MA[0..15]<7,13>
DDR_B_BS0<7,13>
DDR_CKE2_DIMMB<7>
DDR_B_WE#<7,13>
DDR_CKE3_DIMMB <7>
DDR_B_BS2<7,13>
DDR_B_BS1 <7,13>
DDR_B_RAS# <7,13>
DDR_CS2_DIMMB# <7>
DDR_CS3_DIMMB#<7>
M_ODT2 <7>
M_ODT3 <7>
M_CLK_DDR#3 <7>
M_CLK_DDR3 <7>
DDR3_DRAMRST#_R <12,13,14>
M_CLK_DDR#2<7>
M_CLK_DDR2<7>
PCH_SMBDATA <6,12,13,14,19,49,50,51,53>
PCH_SMBCLK <6,12,13,14,19,49,50,51,53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DDRIII DIMMD
Custom
16 61Friday, June 22, 2012
2012/06/22 2013/06/21
SA0
SA1
1
0
0
1
1
DIMMA
DIMMB
DIMMC
DIMMD
1
0
0
Layout Note:
Place near JDIMMD
JDIMMD H=9.2mm
All VREF traces should
have 20 mil trace width
Layout Note:
Place near JDIMMD.203,204
CPU
2(H8)
1(H4)
3(H5.2)
JDIMMD(H9.2)
Compal Electronics, Inc.
All VREF traces should
have 20 mil trace width
CD71
1U_0402_6.3V6K~D
1
2
CD69
0.1U_0402_25V6K~D
1
2
CD80
1U_0402_6.3V6K~D
1
2
RD45
10K_0402_5%~D
@
1 2
CD66
2.2U_0402_6.3V6M
1
2
CD87
10U_0603_6.3V6M~D
1
2
RD44
10K_0402_5%~D
1 2
RD31
10K_0402_5%~D
@
1 2
RD32
10K_0402_5%~D
1 2
JDIMM4
FOX_AS0A626-UARN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD83
0.1U_0402_25V6K~D
1
2
CD89
1U_0402_6.3V6K~D
1
2
CD81
10U_0603_6.3V6M~D
1
2
CD86
1U_0402_6.3V6K~D
1
2
CD84
2.2U_0402_6.3V6M
1
2
CD77
1U_0402_6.3V6K~D
1
2
CD76
0.1U_0402_25V6K~D
1
2
CD88
10U_0603_6.3V6M~D
1
2
+
CD68
330U_SX_2VY~D
1
2
CD82
1U_0402_6.3V6K~D
1
2
CD72
2.2U_0402_6.3V6M
1
2
CD65
10U_0603_6.3V6M~D
1
2
CD78
1U_0402_6.3V6K~D
1
2
CD79
10U_0603_6.3V6M~D
1
2
CD70
10U_0603_6.3V6M~D
@
1
2
CD67
10U_0603_6.3V6M~D
1
2
CD85
1U_0402_6.3V6K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_AZ_SYNCPCH_AZ_SYNC_Q
PCH_AZ_SDOUT
PCH_GPIO33
PCH_INTVRMEN
HDA_SPKR
PCH_GPIO21
PCH_RTCX1
PCH_RTCX2
PCIE_PTX_WANRX_N2
PCIE_PRX_WANTX_P2
PCIE_PRX_WANTX_N2
PCIE_PTX_WANRX_P2
SATA_IREF
SRTCRST#
PCH_RTCRST#
PCH_INTVRMEN
SATA_PTX_DRX_P0
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
INTRUDER#
+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS
PCH_TP25
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_P1
BBS_BIT0_R
PCH_GPIO21
MSATA_PRX_DTX_N3
SATA_ODD_PRX_DTX_N2
MSATA_PTX_DRX_P3
MSATA_PRX_DTX_P3
SATA_ODD_PRX_DTX_P2
MSATA_PTX_DRX_N3
SATA_ODD_PTX_DRX_N2
SATA_ODD_PTX_DRX_P2
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_BITCLK
PCIE_PTX_WLANRX_N1
PCIE_PTX_WLANRX_P1
PCIE_PRX_WLANTX_P1
PCIE_PRX_WLANTX_N1
PCH_AZ_SDOUT
HDA_SPKR
PCH_AZ_SYNC
PCH_RTCX1_R
BBS_BIT0_R
SATA_PTX_DRX_N0
SATA_COMP
PCH_GPIO33
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TCK
SATA_COMP
PCH_SATALED#
PCH_SATALED#
PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_BITCLK
PCH_AZ_RST#
DP_PCH_HPD
+5VS
+3VS
+3VS
+3V_PCH
+RTC_CELL
+RTC_CELL
+3V_PCH
+1.5VS
+3VS
+1.5VS
+3VLP
+RTCBATT
+RTC_CELL
MSATA_PTX_DRX_P3 <50>
MSATA_PTX_DRX_N3 <50>
MSATA_PRX_DTX_N3 <50>
MSATA_PRX_DTX_P3 <50>
SATA_PTX_DRX_P0 <49>
SATA_PRX_DTX_N0 <49>
SATA_PRX_DTX_P0 <49>
SATA_PTX_DRX_N0 <49>
SATA_ODD_PTX_DRX_P2 <50>
SATA_ODD_PTX_DRX_N2 <50>
SATA_ODD_PRX_DTX_N2 <50>
SATA_ODD_PRX_DTX_P2 <50>
SATA_PTX_DRX_P1 <49>
SATA_PTX_DRX_N1 <49>
SATA_PRX_DTX_N1 <49>
SATA_PRX_DTX_P1 <49>
PCIE_PRX_WANTX_N2 <51>
PCIE_PRX_WANTX_P2 <51>
PCIE_PRX_WLANTX_N1 <51>
PCIE_PRX_WLANTX_P1 <51>
PCIE_PTX_WANRX_N2 <51>
PCIE_PTX_WANRX_P2 <51>
PCIE_PTX_WLANRX_N1 <51>
PCIE_PTX_WLANRX_P1 <51>
PCH_AZ_CODEC_SDIN0<45>
HDA_SDO<43>
PCH_SATALED# <48>
HDA_SPKR<45>
PCH_AZ_CODEC_SYNC<45>
PCH_AZ_CODEC_SDOUT<45>
PCH_AZ_CODEC_RST#<45>
PCH_AZ_CODEC_BITCLK<45>
DP_PCH_HPD<30>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (1/9) RTC,HDA,SATA,XDP
Custom
17 61Friday, June 22, 2012
2012/06/22 2013/06/21
HDA_SYNC Isolation Circuit
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
NO REBOOT STRAP
High - Enable Internal VRs
Low - Enable External VRs
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
FLASH DESCRIPTOR SECURITY OVERRIDE
HDA for Codec
HDD1(Master)
HDD2(Slave)
mSATA
MiniDMC (Mini Card 2)
MiniWLAN (Mini Card 1)
CMOS setting
Shunt Clear CMOS
Keep CMOS
TPM setting
Shunt Clear ME RTC Registers
Keep ME RTC Registers
ME_CLR1
Open
CMOS_CLR1
Open
CMOS place near DIMM
ODD/HDD3 Bay
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
SATA Impedance Compensation
Compal Electronics, Inc.
W=20mils
W=20mils
W=20mils
RTC Battery
CH12
1U_0603_10V6K
1
2
RH31
1M_0402_5%~D
1 2
RH23 20K_0402_5%~D
1 2
RH56 33_0402_5%~D
1 2
RH39
330K_0402_1%~D
@
12
RH38
330K_0402_1%~D
12
CH101
27P_0402_50V8J~D
@
1
2
RH407.5K_0402_1%~D
1 2
RH524.7K_0402_5%~D
12
CH3
18P_0402_50V8J~D
1 2
RH59 51_0402_1%~D
12
G
D
S
QH8
SSM3K7002FU_SC70-3~D
2
13
RH287 1K_0402_1%~D@
1 2
RH289 0_0402_5%~D
1 2
RH44 210_0402_1%~D
@
1 2
CMOS1 SHORT PADS~D
@
1
122
ME1 SHORT PADS~D
@
1
122
RH29 33_0402_5%~D
1 2
RH5510K_0402_5%~D
1 2
T161PAD~D @
RH27 33_0402_5%~D
1 2
RH46 210_0402_1%~D
@
1 2
RH3010K_0402_5%~D
1 2
CH2
18P_0402_50V8J~D
1 2
RH2
10M_0402_5%~D
12
RH355 100K_0402_5%~D
1 2
RH34
1K_0402_5%
1 2
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
12
RH288
0_0603_5%~D
12
RH26 33_0402_5%~D
1 2
RH45 210_0402_1%~D
@
1 2
RH22 20K_0402_5%~D
1 2
RH286 0_0402_5%~D
1 2
T122 PAD~D@
CH4 1U_0402_6.3V6K~D
1 2
RH49
100_0402_1%~D
12
RH11 1M_0402_5%~D
1 2
T155PAD~D @
CH5 1U_0402_6.3V6K~D
1 2
RH35 10K_0402_5%~D@
1 2
RH48
100_0402_1%~D
12
RH50 1K_0402_1%~D
1 2
DH1
BAT54CW_SOT323-3
2
3
1
JTAGRTC AZALIA
SATA
LPT_PCH_M_EDS
5
1 OF 11
UH1A
LYNXPOINT_BGA695
TP20
AB6
TP25
F8
TP9 BA2
TP22
C26
RTCX1
B5
SATA_RXN_1 BC10
SATA_RXP_1 BE10
JTAG_TDI
AE2
JTAG_TDO
AD3
JTAG_TMS
AD1
JTAG_TCK
AB3
HDA_SDO
A24
HDA_SDI2
G22
HDA_SDI3
F22
HDA_SDI1
K22
HDA_SDI0
L22
RTCRST#
D9
INTRUDER#
A8
INTVRMEN
G10
SRTCRST#
B9
RTCX2
B4
SATA_IREF BD4
SATA0GP/GPIO21 AT1
SATA1GP/GPIO19 AU2
SATALED# AP3
SATA_RCOMP AY5
SATA_TXP5/PETP2 AR15
SATA_RXP5/PERP2 BE14
SATA_TXN5/PETN2 AP15
SATA_RXN5/PERN2 BC14
SATA_TXP4/PETP1 AW15
SATA_TXN4/PETN1 AV15
SATA_RXP4/PERP1 BB13
SATA_RXN4/PERN1 BD13
SATA_TXP_3 AT13
SATA_RXP_3 BE12
SATA_TXN_3 AR13
SATA_RXN_3 BC12
SATA_TXP_2 AW 13
SATA_TXN_2 AY13
SATA_RXN_2 BB9
SATA_RXP_2 BD9
SATA_TXP_1 AW 10
SATA_TXN_1 AV10
SATA_TXP_0 AY8
SATA_TXN_0 AW 8
SATA_RXP_0 BE8
SATA_RXN_0 BC8
HDA_RST#
C24
SPKR
AL10
HDA_SYNC
A22
HDA_BCLK
B25
HDA_DOCK_RST#/GPIO13
C22
DOCKEN#/GPIO33
B17
TP8 BB2
RH47
100_0402_1%~D
12
RH410_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
FDI_INT
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
PM_CLKRUN#
FDI_IREF
DMI_IREF
FDI_RCOMP
DSWODVREN
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PCIE_WAKE#
PM_SLP_SUS#
SUS_STAT#
H_PM_SYNC
DMI_RCOMP
ME_SUS_PWR_ACK_R SUSACK#_R
SUS_STAT#
PCH_RI#
ME_RESET#
SYS_RESET#
ME_RESET#
SUSPWRDNACK
PCIE_WAKE#
PM_CLKRUN#
PM_DRAM_PWRGD_R
PCH_BATLOW#
PCH_RI#
SUSACK#_R
ACIN_PCH
PCH_PW ROK_R
PM_APWROK_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SYS_RESET#
SIO_PWRBTN#_R
FDI_CSYNC
PCH_PLTRST#
DGPU_SELECT#
FFS_INT1
WL_OFF#
BBS_BIT1
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQB#
BT_ON#
ODD_DA#
DP_CBL_DET
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQD#
DGPU_HOLD_RST#
PCI_PIRQB#
DSWODVREN
SYS_PWROK_R
PM_CLKRUN#
PCH_DRWROK_R
PCH_RSMRST#_R
PLTRST_VGA#
DGPU_HOLD_RST#
PCH_PLTRST#
HDMI_IN_PWMSEL#
HDMI_IN_PWMSEL#
WL_OFF#
PCH_PLTRST#
ODD_DA#
BT_ON#
PLT_RST
PCH_DPB_HDMI_DAT
PCH_DPD_CLK
PCH_DPD_DAT
PCH_HDMI_HPD
PCH_DPB_HDMI_CLK
PCH_DMC_HPD
PCH_EDP_PWM
SYS_PWROK
PCH_PW ROK
BBS_BIT1
ACIN_PCH
+1.5VS
+1.5VS
+PCH_VCCDSW 3_3
+3V_PCH
+3VS
+3VS
+1.5VS
+1.5VS +3VS
+3VS
+RTC_CELL
+3VS
+3V_MXM
+3VS
+3VS
+3V_PCH
+3V_PCH
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N1<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N0<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_N2<5>
DMI_CRX_PTX_P3<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P1<5>
PBTN_OUT#<6,43>
PCH_PW ROK<43>
SG_AMD_BKL<42,43>
SYS_PWROK<6>
SUSPWRDNACK<43>
PCH_RSMRST#<43>
PM_DRAM_PWRGD<6>
XDP_DBRESET#<6>
PCH_DPWROK <43>
PCIE_WAKE# <43,44,51>
PM_SLP_S4# <43>
PM_SLP_S3# <43,47>
PM_SLP_S5# <43,47>
PM_SLP_SUS# <43>
FDI_CSYNC <5>
FDI_INT <5>
H_PM_SYNC <6>
BT_ON# <51>
ODD_DA# <50>
DGPU_SELECT#<32,36,42>
PLT_RST# <6,43,44,51,53>
PLTRST_VGA# <29>
HDMI_IN_PWMSEL#<42>
WL_OFF#<51>
FFS_INT1 <49>
DP_CBL_DET <30>
PCH_DPD_CLK <39>
PCH_DPD_DAT <39>
PCH_HDMI_HPD <36>
PCH_DPB_HDMI_DAT <36>
PCH_DPB_HDMI_CLK <36>
PCH_DMC_HPD <39>
PCH_EDP_PWM<40>
IMVP_PW RGD<6,43,62>
ACIN<29,43,47,57,63>
DGPU_HOLD_RST#<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (2/9) DMI,FDI,PM,DP,CRT
Custom
18 61Friday, June 22, 2012
2012/06/22 2013/06/21
PCI
GPIO51 has internal pull up.
0 1 Reserved (NAND)
1 0
11 SPI
SATA1GP/GPIO19
(BBS_BIT0)
Boot BIOS Strap
GNT1#/GPIO51
(BBS_BIT1) Boot BIOS Location
*
00 LPC
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
DSWODVREN - ON DIE DSW VR ENABLE
STP_A16OVR
A16 SWAP OVERRIDE STRAP
Compal Electronics, Inc.
HDMI
DMC
T124 PAD~D@
RH3258.2K_0402_5%~D
12
RH199 8.2K_0402_5%~D@
12
RH156 8.2K_0402_5%~D
1 2
RH3668.2K_0402_5%~D
12
RH196
100K_0402_5%~D
12
T126 PAD~D@
CH41
0.1U_0402_16V7K
1
2
RH185 0_0402_5%~D
1 2
RH139 649_0402_1%~D
1 2
RH32710K_0402_5%~D @
12
CH143
0.1U_0402_25V6K~D
@
1 2
RH172 10K_0402_5%~D
1 2
UH13
74AHC1G09GW_TSSOP5~D
@
B
1
A
2
G
3
O4
P5
RH163 0_0402_5%~D
1 2
CH144
0.1U_0402_25V6K~D
1 2
T139 PAD~D@
T141PAD~D @
RH43 0_0402_5%
12
RH2067.5K_0402_1%~D
12
RH204 7.5K_0402_1%~D
1 2
T144PAD~D @
RH3528.2K_0402_5%~D
12
RH149 0_0402_5%~D
1 2
RH3248.2K_0402_5%~D
12
QH13B
DMN66D0LDW-7_SOT363-6~D
34
5
CH147
0.1U_0402_25V6K~D
1 2
RH320 0_0402_5%~D
1 2
UH6
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O4
P5
RH148 10K_0402_5%~D
1 2
RH178
330K_0402_1%~D
@
1 2
RH323 0_0402_5%~D
1 2
RH318 10K_0402_5%~D@
1 2
QH13A
DMN66D0LDW-7_SOT363-6~D
61
2
RH153 10K_0402_5%~D
1 2
RH114 0_0402_5%~D@
1 2
RH186 0_0402_5%~D@
1 2
RH201
100K_0402_5%~D
12
T145PAD~D @
RH167 0_0402_5%~D
1 2
R1900
10K_0402_5%
12
RH3298.2K_0402_5%~D
12
T140 PAD~D@
RH152 8.2K_0402_5%~D@
1 2
RH138 8.2K_0402_5%~D
1 2
RH3628.2K_0402_5%~D
12
T148PAD~D @
RH191
330K_0402_1%~D
1 2
T127 PAD~D @
LPT_PCH_M_EDS
DMI
Management
FDI
System Power
5
4 OF 11
UH1B
LYNXPOINT_BGA695
TP21
AB10
TP10 AW44
TP16 AV43
TP12
AW17
TP17 AU42
TP7
AV17
TP5 AY45
TP13 AU44
SUSWARN#/SUSPWRNACK/GPIO30
J4
DMI_IREF
BE16
DMI_RCOMP
AY17
FDI_RCOMP AR44
SLP_W LAN#/GPIO29
D2
DRAMPWROK
H3
APW ROK
AB7
PWROK
F10
SYS_RESET#
AM1
DMI_RXP_2
AR17
DMI_RXP_3
AW20
DMI_TXN_0
BD21
DMI_TXN_1
BE20
SLP_LAN# G5
PMSYNCH AY3
SLP_SUS# F1
SLP_A# F3
SLP_S3# H1
SLP_S4# C6
SLP_S5#/GPIO63 Y7
SUSCLK/GPIO62 Y6
SUS_STAT#/GPIO61 U7
CLKRUN# AN7
WAKE# K3
DPW ROK L13
FDI_IREF AT45
FDI_CSYNC AL39
FDI_RXP_1 AL36
FDI_RXP_0 AJ36
FDI_RXN_1 AL35
FDI_RXN_0 AJ35
ACPRESENT/GPIO31
E6
SYS_PW ROK
AD7
SUSACK#
R6
DMI_TXP_2
BB17
DMI_TXP_0
BB21
DMI_RXP_1
AP20
DMI_RXN_2
AP17
DMI_TXP_3
BC18
DMI_TXP_1
BC20
DMI_TXN_3
BE18 DMI_TXN_2
BD17
DMI_RXP_0
AY22
DMI_RXN_3
AV20
PWRBTN#
K1
RI#
N4
BATLOW#/GPIO72
K7
RSMRST#
J2
FDI_INT AL40
DSW VRMEN C8
DMI_RXN_1
AR20 DMI_RXN_0
AW22
TP15 AV45
T129 PAD~D@
RH3268.2K_0402_5%~D
12
RH193 0_0402_5%~D
1 2
R1899
10K_0402_5%
12
T146PAD~D @
RH200 0_0402_5%~D
1 2
RH351 10K_0402_5%~D@
1 2
RH420_0402_5%
12
T125 PAD~D @
T123 PAD~D@
RH357 0_0402_5%~D
1 2
UH3
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O4
P5
RH144 0_0402_5%~D
1 2
RH367
10K_0402_5%~D
@
12
T128 PAD~D @
T147PAD~D @
LPT_PCH_M_EV
DISPLAY
LVDSCRT
PCI
5 OF 11
5UH1E
LYNXPOINT_BGA695
VGA_BLUE
T45
VGA_GREEN
U44
VGA_RED
V45
VGA_DDC_CLK
M43
DAC_IREF
U40
VGA_IRTN
U39
EDP_BKLTCTL
N36
EDP_BKLTEN
K36
EDP_VDDEN
G36
PIRQA#
H20
PIRQB#
L20
PIRQC#
K17
PIRQD#
M20
GPIO50
A12
GPIO52
B13
GPIO54
C12
GPIO51
C10
GPIO53
A10
GPIO55
AL6
DDPB_CTRLCLK R40
DDPB_CTRLDATA R39
DDPC_CTRLCLK R35
DDPC_CTRLDATA R36
DDPD_CTRLCLK N40
DDPD_CTRLDATA N38
DDPB_AUXN H45
DDPC_AUXN K43
DDPD_AUXN J42
DDPB_AUXP H43
DDPC_AUXP K45
DDPD_AUXP J44
DDPB_HPD K40
DDPC_HPD K38
DDPD_HPD H39
PIRQE#/GPIO2 G17
PIRQH#/GPIO5 M15
PME# AD10
PLTRST# Y11
PIRQG#/GPIO4 L15
PIRQF#/GPIO3 F17
VGA_VSYNC
N44
VGA_HSYNC
N42
VGA_DDC_DATA
M45
UH8
MC74VHC1G08DFT2G_SC70-5
IN1
1
IN2
2OUT 4
VCC 5
GND
3
RH215
100K_0402_5%~D
@
1 2
RH342
1K_0402_1%~D
@
12
RH3658.2K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_LPC CLK_PCI1
CLK_PCI2CLK_DEBUG
CLK_PCI_LPBACK CLK_PCI0
CLK_CPU_DPLL
CLK_CPU_DPLL#
XTAL25_IN
CLK_PEG_PCH#
CLK_PEG_PCH
CLK_BCLK_ITP
CLK_BUF_BCLK#
PCH_GPIO66
DMC_PCH_DET#
CAM_DET#
XTAL25_OUT
ICLK_IREF
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DMI#
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_BUF_BCLK#
CLK_CPU_SSC_DPLL
CLK_CPU_SSC_DPLL#
PCH_CLK_BIASREF
XTAL25_IN_R
CLK_PCH_14M
CLK_PCI_LPBACK
CLK_BCLK_ITP#
CLK_BUF_DOT96#
CLK_BUF_CKSSCD
CLK_BUF_BCLK
CLK_PCH_14M
CLK_BUF_DMI#
CLK_BUF_CKSSCD#
CLK_BUF_DOT96
CLK_BUF_DMI
LANCLK_REQ#
PCIE_LAN
PCIE_LAN#
MINI2CLK_REQ#
PCIE_MINI2
PCIE_MINI2#
PCIE_EXP#
PCIE_EXP
CDCLK_REQ#
MINI1CLK_REQ#
PCIE_MINI1#
PCIE_MINI1
CLK_PCI3
PEG_CLKREQ#
CAM_DET#
DMC_PCH_DET#
PCH_GPIO66
CLK_PCI4
+3V_PCH
+1.05V_+1.5V_RUN
+1.5VS
+3V_PCH
+3V_PCH
+3V_PCH
+3VS
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3VS
CLK_PEG_PCH# <29>
CLK_PEG_PCH <29>
CLK_CPU_ITP<6>
CLK_PCI_LPC<43>
CLK_CPU_ITP#<6>
CLK_CPU_DMI <6>
CLK_CPU_DMI# <6>
CLK_DEBUG<51>
CLK_CPU_DPLL# <6>
CLK_CPU_SSC_DPLL <6>
CLK_CPU_SSC_DPLL# <6>
CLK_CPU_DPLL <6>
CLK_PCIE_MINI1<51>
MINI1CLK_REQ#<51>
CLK_PCIE_MINI1#<51>
CLK_PCIE_LAN#<44>
CLK_PCIE_LAN<44>
LANCLK_REQ#<44>
CDCLK_REQ#<53>
CLK_PCIE_CD<53>
CLK_PCIE_CD#<53>
MINI2CLK_REQ#<51>
CLK_PCIE_MINI2<51>
CLK_PCIE_MINI2#<51>
PEG_CLKREQ# <29>
DMC_PCH_DET# <51>
CAM_DET# <33,42>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (3/9) CLK
Custom
19 61Friday, June 22, 2012
2012/06/22 2013/06/21
CLOCK TERMINATION for FCIM and need close to PCH
Compal Electronics, Inc.
10/100/1G LAN
DMC (Mini Card 2)
MiniWLAN (Mini Card 1)
Card Reader
RH126 10K_0402_5%~D
12
RH105 10K_0402_5%~D
1 2
RH280 0_0402_5%~D
12
RH307 0_0402_5%~D
12
RH2087.5K_0402_1%~D
1 2
T149PAD~D @
RH205 10K_0402_5%~D
1 2
RH128 10K_0402_5%~D
12
RH146 10K_0402_5%~D
1 2
RH124 0_0402_5%~D
12
RH131 1M_0402_5%~D
1 2
RH143 10K_0402_5%~D
1 2
YH4
25MHZ_10PF_Q22FA2380049900~D
IN 1
GND 2
OUT
3
GND
4
RH142 10K_0402_5%~D
12
RH28 10K_0402_5%~D
1 2
CH19
8.2P_0402_50V8D~D
1
2
RH147 0_0402_5%~D
12
RH76 10K_0402_5%~D
1 2
RH158 0_0402_5%~D
12
T150PAD~D @
T138 PAD~D@
RH54 0_0402_5%
1 2
RH281 0_0402_5%~D
12
RH75 10K_0402_5%~D
1 2
RH21810K_0402_5%~D
1 2
RH308 0_0402_5%~D
12
RH74 10K_0402_5%~D
1 2
RH21710K_0402_5%~D
1 2
RH132 10K_0402_5%~D
12
RH157 10K_0402_5%~D
1 2
RH127 10K_0402_5%~D
12
RH151 22_0402_5%~D
12
CH18
8.2P_0402_50V8D~D
1
2
RH21610K_0402_5%~D
1 2
LPT_PCH_M_EDS
CLOCK SIGNAL
5
2 OF 11
UH1C
LYNXPOINT_BGA695
PCIECLKRQ4#/GPIO26
V3 CLKOUT_PCIE_P_4
AF45
CLKOUT_PCIE_P_5
AE42
PCIECLKRQ5#/GPIO44
AA2
CLKOUT_PCIE_N_6
AB40
CLKOUT_PCIE_P_6
AB39
PCIECLKRQ6#/GPIO45
AE4
CLKOUT_PCIE_N_7
AJ44
CLKOUT_PCIE_P_7
AJ42
CLKOUTFLEX2/GPIO66 F36
CLKIN_SATA BE6
CLKIN_GND AR24
CLKIN_DMI AY24
PCIECLKRQ1#/GPIO18
AF1
CLKOUT_DP AJ40
CLKOUT_DMI AF39
CLKOUT_PCIE_N_0
Y43
CLKOUT_PCIE_P_0
Y45
CLKOUT_PEG_B Y39
CLKOUT_PEG_A AB35
PCIECLKRQ0#/GPIO73
AB1
CLKOUT_PEG_A_P AB36
PEGA_CLKRQ#/GPIO47 AF6
CLKOUT_PEG_B_P Y38
PEGB_CLKRQ#/GPIO56 U4
CLKOUT_PCIE_P_1
AA42
CLKOUT_PCIE_N_2
AB43
CLKOUT_ITPXDP
AH43
XTAL25_IN AL44
XTAL25_OUT AM43
CLKOUTFLEX0/GPIO64 C40
CLKOUTFLEX1/GPIO65 F38
DIFFCLK_BIASREF AN44
ICLK_IREF AM45
CLKOUTFLEX3/GPIO67 F39
CLKIN_33MHZLOOPBACK D17
REFCLK14IN F45
CLKIN_SATA_P BC6
CLKIN_DOT96P G33
CLKIN_DOT96N H33
CLKIN_GND_P AT24
CLKIN_DMI_P AW24
CLKOUT_DP_P AJ39
CLKOUT_DMI_P AF40
CLKOUT_PCIE_N_1
AA44
PCIECLKRQ7#/GPIO46
Y3
CLKOUT_ITPXDP_P
AH45
CLKOUT_33MHZ1
E44
CLKOUT_33MHZ0
D44
CLKOUT_33MHZ2
B42
CLKOUT_33MHZ3
F41
CLKOUT_33MHZ4
A40
CLKOUT_PCIE_N_4
AF43
CLKOUT_PCIE_N_3
AD43
CLKOUT_PCIE_P_3
AD45
PCIECLKRQ3#/GPIO25
T3
CLKOUT_PCIE_N5
AE44
CLKOUT_DPNS_P AF36
CLKOUT_DPNS AF35
PCIECLKRQ2#/GPIO20/SMI#
AF3
CLKOUT_PCIE_P_2
AB45
TP19 AD39
TP18 AD38
RH111 22_0402_5%~D
12
RH99 0_0402_5%~D
12
RH12510K_0402_5%~D
12
RH155 10K_0402_5%~D
1 2
RH133 10K_0402_5%~D
12
RH98 0_0402_5%~D
12
RH309 0_0402_5%~D
12
RH169 22_0402_5%~D
12
RH130 10K_0402_5%~D
1 2
RH129 0_0402_5%~D
12
T176PAD~D @
T142 PAD~D@
RH145 10K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SML0CLK
SML0DATA
DDR_HVREF_RST_PCH
SML1CLK
SML1DATA
PCH_GPIO74
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SERIRQ
PCH_SPI_DO3_R
PCH_SPI_DO2_R
SERIRQ
MEM_SMBDATA
SML0CLK
SML0DATA
MEM_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
PCH_SPI_DO2
PCH_SPI_DO2
PCH_TD_IREF
DDR_HVREF_RST_PCH
SML1CLK
SML1DATA
PCH_GPIO74
PCH_SPI_DO3
PCH_SPI_CLK_RPCH_SPI_DO2_R
PCH_SPI_SI_R
PCH_SPI_SO PCH_SPI_SO_R
PCH_SPI_SI
PCH_SPI_CLK
PCH_SPI_CS0# PCH_SPI_CS0#_R
PCH_SPI_CLK
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_CS0#
MEM_SMBCLK
MEM_SMBDATA
PCH_SPI_DO3PCH_SPI_DO3_R
SML1CLK
SML1DATA
PCH_LID_SW_IN#
PCH_SPI_CLK
PANEL_SW
+3V_PCH
+3V_PCH
+3V_PCH
+3VS
+3VS
+3V_PCH
+3VS
+3VS
+3V_PCH
LPC_AD0<43,51>
LPC_AD1<43,51>
LPC_AD2<43,51>
LPC_AD3<43,51>
PCH_SMBDATA <6,12,13,14,15,49,50,51,53>
PCH_SMBCLK <6,12,13,14,15,49,50,51,53>
LPC_FRAME#<43,51>
SERIRQ<43>
EC_SMB_CK2 <40,43,53,54>
EC_SMB_DA2 <40,43,53,54>
EC_LID_OUT# <43>
LID_SW_IN# <43,47,48,53>
PANEL_SW<31,34>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
PCH (4/9) SPI, SMBUS,LPC
Custom
20 61Friday, June 22, 2012
2012/06/22 2013/06/21
200 MIL SO8
64Mb Flash ROM
Reserve for EMI please
close to UH14
EON
QH10A
DMN66D0LDW-7_SOT363-6~D
6 1
2
RH377 33_0402_5%~D
1 2
RH374 33_0402_5%~D
1 2
RH58
3.3K_0402_5%
@
1 2
QH9A
DMN66D0LDW-7_SOT363-6~D
6 1
2
UH14
64M EN25Q64-104HIP_SO8
CLK 6
GND
4DIO 5
DO
2
/WP
3
VCC 8
/HOLD 7
/CS
1
CH56
0.1U_0402_25V6K~D
1 2
RH369 0_0402_5%~D
@
1 2
RH304
2.2K_0402_5%~D
12
T130PAD~D @
RH372 33_0402_5%~D
1 2
RH310
2.2K_0402_5%~D
12
T132PAD~D @
RH3022.2K_0402_5%~D
12
T133PAD~D @
T131PAD~D @
RH60
33_0402_5%~D
@
1 2
RH337 10K_0402_5%~D
1 2
RH3062.2K_0402_5%~D
12
RH2982.2K_0402_5%~D
1 2
CH8
22P_0402_50V8J~D
@
1
2
RH3001K_0402_1%~D
12
RH376 33_0402_5%~D
1 2
RH3032.2K_0402_5%~D
12
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
SPILPC
3 OF 11 5
UH1D
LYNXPOINT_BGA695
SML1ALERT#/PCHHOT#/GPIO74 H6
SPI_IO3
AJ2
SPI_MISO
AH3
SPI_IO2
AJ4
SPI_MOSI
AH1
SPI_CS2#
AJ10
SPI_CS1#
AL7
SPI_CS0#
AJ7
SPI_CLK
AJ11
LDRQ1#/GPIO23
G20
SERIRQ
AL11
LDRQ0#
D21
LFRAME#
B21
LAD_3
C18
LAD_2
A18
LAD_1
C20
LAD_0
A20
TD_IREF AY43
CL_DATA AF10
CL_RST# AF7
CL_CLK AF11
SML1DATA/GPIO75 N11
SML1CLK/GPIO58 K6
SML0DATA R7
SML0CLK U8
SML0ALERT#/GPIO60 N8
SMBDATA U11
SMBCLK R10
SMBALERT#/GPIO11 N7
TP2 BC45
TP4 BE43
TP1 BA45
TP3 BE44
RH368 0_0402_5%~D
1 2
QH10B
DMN66D0LDW-7_SOT363-6~D
3 4
5
RH375 33_0402_5%~D
1 2
RH373 0_0402_5%~D
1 2
RH30110K_0402_5%~D
12
RH3052.2K_0402_5%~D
12
RH2992.2K_0402_5%~D
1 2
RH322 8.2K_0402_1%
1 2
RH370 3.3K_0402_5%~D
1 2
RH371 3.3K_0402_5%~D
1 2
QH9B
DMN66D0LDW-7_SOT363-6~D
3 4
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USBRBIAS
PCH_PCIE_RCOMP
USB3TN2
USB3RP2
USB3RN2
USB3TP2
USB3RN1
USB20_N12
USB20_P12
USB_OC3#
USB_OC4#
USB_OC7#
USB_OC5#
USB_OC6#
USB_OC0#
USB_OC1#USB_OC3#
USB_OC2#
USB_OC6#
USB_OC5#
USB_OC4#
USB_OC1#
USB_OC0#
USB20_N11
USB20_P11
USB20_P7
USB20_P5
USB20_P3
USB20_P0
USB20_N0
USB20_N1
USB20_N3
USB20_P4
USB20_P2
USB20_N4
USB20_N7
USB20_N5
USB_OC2#
USB20_N6
USB20_P6
USB20_P1
USB20_N2
USB3RP1
USB3TN1
USB3TP1
USB3TN5
USB3RP5
USB3RN5
USB3TP5
USB_OC7#
PCH_PCIE_IREF
USBRBIAS
USB3TN6
USB3RP6
USB3RN6
USB3TP6
PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1
PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C
PCIE_PRX_CARDTX_P4
PCIE_PRX_CARDTX_N4
PCIE_PTX_CARDRX_P4_C
PCIE_PTX_CARDRX_N4_C
USB20_N13
USB20_P13
+1.5VS
+3V_PCH
+1.5VS
USB3RN2 <52>
USB3RN1 <52>
USB3TP2 <52>
USB3TN2 <52>
USB3RP2 <52>
USB3TP1 <52>
USB3TN1 <52>
USB3RP1 <52>
USB20_N11 <33>
USB20_P11 <33>
USB20_P3 <53>
USB20_N5 <51>
USB20_P4 <51>
USB20_N3 <53>
USB20_N4 <51>
USB20_P5 <51>
USB20_P1 <52>
USB20_N2 <53>
USB20_P2 <53>
USB20_P0 <52>
USB20_N0 <52>
USB20_N1 <52>
USB20_N7 <55>
USB20_P7 <55>
USB_OC0# <52>
USB_OC1# <52>
USB20_P6 <47>
USB20_N6 <47>
USB_OC3# <53>
USB_OC2# <53>
USB20_N12 <42>
USB20_P12 <42>
USB3RN5 <53>
USB3TP5 <53>
USB3TN5 <53>
USB3RP5 <53>
USB3RN6 <53>
USB3TP6 <53>
USB3TN6 <53>
USB3RP6 <53>
PCIE_PRX_GLANTX_P1<44>
PCIE_PRX_GLANTX_N1<44>
PCIE_PTX_GLANRX_N1<44>
PCIE_PTX_GLANRX_P1<44>
PCIE_PRX_CARDTX_N4<53>
PCIE_PRX_CARDTX_P4<53>
PCIE_PTX_CARDRX_N4<53>
PCIE_PTX_CARDRX_P4<53>
USB20_N13 <53>
USB20_P13 <53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (5/9) PCIE,USB
Custom
21 61Friday, June 22, 2012
2012/06/22 2013/06/21
10/100/1G LAN
CARD READER
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
IR sensor
ELC LED
JUSB2
JUSB3
JUSB1
Mini Card(DMC)
Mini Card(WLAN)
JUSB4
VPK K/B
eDP Camera
P1: JUSB1
P5: JUSB3
P2: JUSB2
P6: JUSB4
Compal Electronics, Inc.
LVDS Camera
CH150 0.1U_0402_25V6K~D
1 2
T135PAD~D @
LPT_PCH_M_EDS
USB
PCIe
9 OF 11 5
UH1I
LYNXPOINT_BGA695
USB3TP6 BE28
USB3TN6 BD27
USB3RP6 AP29
USB3RN6 AR29
USB3TP5 BC26
USB3TN5 BE26
USB3RP5 AV29
USB3RN5 AW29
PETP1/USB3TP3
BC32
PERP2/USB3RP4
AR31
PETP2/USB3TP4
BB33
USB3TP2 BC24
PETN2/USB3TN4
BD33
PERN2/USB3RN4
AT31
PETN1/USB3TN3
BE32
PERP1/USB3RP3
AY31 PERN1/USB3RN3
AW31
PERN_3
AW33
PERP_3
AY33
PETN_3
BE34
PETN_4
BE36
PERN_5
AW36
PERP_5
AV36
PETN_5
BD37
PERP_6
AW38
PETN_6
BC38
PERN_7
AT40
USB2N13 F24
USB2P13 G24
USB2N12 G26
USB2P12 F26
USB2P11 C28
USB2N11 A28
USB2P10 D29
USB2P9 C30
USB2N10 B29
USB2N9 A30
USB2P8 C32
USB2N8 A32
USB2N7 G29
USB2P7 H29
USB2P6 L31
USB2N6 K31
USB2P5 G31
USB2P4 D33
USB2N5 F31
USB2N4 B33
USB2P3 C34
USB2N3 A34
USB2P2 C36
USB2N2 A36
USB2P1 C38
USB2N1 A38
USB2P0 D37
USB2N0 B37
PETP_8
BD41
PCIE_IREF
BE30
PCIE_RCOMP
BD29
PETP_3
BC34
PERN_4
AT33
PERP_4
AR33
PETP_4
BC36
PETP_5
BB37
PERN_6
AY38
PETP_6
BE38
PERP_7
AT39
PETN_7
BE40
PETP_7
BC40
PERN_8
AN38
PERP_8
AN39
PETN_8
BD42
USB3RN1 AR26
USB3RP1 AP26
USB3TN1 BE24
USB3TP1 BD23
USB3RN2 AW26
USB3RP2 AV26
USB3TN2 BD25
USBRBIAS# K24
USBRBIAS K26
OC0#/GPIO59 P3
OC1#/GPIO40 V1
OC2#/GPIO41 U2
OC3#/GPIO42 P1
OC4#/GPIO43 M3
OC5#/GPIO9 T1
OC6#/GPIO10 N2
OC7#/GPIO14 M1
TP23 L33
TP6
BB29
TP11
BC30
TP24 M33
RH160
22.6_0402_1%~D
12
T136 PAD~D@
RH210 7.5K_0402_1%~D
1 2
CH154 0.1U_0402_25V6K~D
1 2
T134 PAD~D@
CH153 0.1U_0402_25V6K~D
1 2
T137PAD~D @
RPH1
10K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
CH149 0.1U_0402_25V6K~D
1 2
RPH2
10K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
RH51 0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
STP_PCI#
PCH_GPIO16
TP_VSS_NCTF
PCH_VSS_B45
VGA_PRSNT_L#
DGPU_HPD_INT#
PCH_GPIO37
PCH_GPIO49
PCH_GPIO15
DGPU_EDIDSEL#
PCH_GPIO16
EC_SMI#
PCH_GPIO28
PCH_GPIO35
PCH_GPIO22
PCH_VSS_A44
PCH_THRMTRIP#_R
PCH_VSS_B45
ODD_EN#
VGA_PRSNT_R#
FFS_INT2
ODD_EN#
PCH_GPIO15
HDD_DET#
ODD_DETECT#
ODD_DETECT#
DGPU_EDIDSEL#
PCH_GPIO22
DGPU_BKL_PWM_SEL#
LVDS_CAB_DET#
PCH_GPIO16
PCH_GPIO27
DMC_RADIO_OFF#
PCH_VSS_BD1
PCH_VSS_BD1
GATEA20
KB_RST#
PCH_GPIO37
EDP_CAB_DET#EDP_CAB_DET#
VGA_PRSNT_R# EC_SCI#
PCH_VSS_A44
VGA_PRSNT_L#
PCH_GPIO49
DGPU_HPD_INT#
PCH_GPIO49
STP_PCI#
PCH_GPIO28
H_CPUPWRGD
KB_RST#
GATEA20
ODD_DETECT#
PCH_GPIO37
DMC_RADIO_OFF#
PCH_GPIO27
PCH_GPIO35
HDD_DET#
CPU_PLTRST#
LVDS_CAB_DET#
EDP_CAB_DET#
EDP_DETECT#
WiGi_RADIO_DIS#
+5VALW+5VS
+3VS
+3VS
+3V_PCH
+3VS
+3V_PCH
+3VS
FFS_INT2<49,50>
DGPU_HPD_INT#<36,39>
HDD_DET#<49>
EC_SMI#<43>
ODD_DETECT#<50>
DGPU_BKL_PWM_SEL#<42>
LVDS_CAB_DET#<42>
GATEA20 <43>
H_CPUPWRGD <6>
KB_RST# <43>
EC_SCI#<43>
H_PECI <6,43>
DGPU_EDIDSEL#<32,36,42>
ODD_EN#<50>
VGA_PRSNT_L#<29>
VGA_PRSNT_R#<29>
H_THERMTRIP# <6>
CPU_PLTRST# <6>
DMC_RADIO_OFF#<51>
EDP_DETECT#<41>
EDP_CAB_DET#<33>
WiGi_RADIO_DIS#<51>
PCH_GPIO35<36>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (6/9) GPIO,MISC,NTFC
Custom
22 61Friday, June 22, 2012
2012/06/22 2013/06/21
ENABLED - HIGH(DEFAULT)
DISABLED - LOW
PLL ON DIE VR ENABLE
GPIO16,49
11
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
01USB X6,PCIEX8,SATAX4
Config
USB X4,PCIEX8,SATAX6
Compal Electronics, Inc.
*
RH354 1K_0402_1%~D
1 2
RH257 10K_0402_5%~D
1 2
RH272 10K_0402_5%~D@
1 2
RH164 10K_0402_5%~D
1 2
RH166
0_0402_5%~D
@
1 2
RH182 10K_0402_5%~D
12
RH176 200K_0402_5%
1 2
RH266 10K_0402_5%~D
12
RH181 10K_0402_5%~D
12
RH187 10K_0402_5%~D
12
RH16110K_0402_5%~D
12
RH170
0_0402_5%~D
1 2
RH271 10K_0402_5%~D
1 2
RH269 10K_0402_5%~D@
12
RH184
0_0402_5%~D
@
12
RH165
0_0402_5%~D
1 2
RH353
1K_0402_1%~D
@
12
RH53
4.7K_0402_5%~D
1 2
RH268 10K_0402_5%~D@
12
RH258 10K_0402_5%~D
1 2
RH179 10K_0402_5%~D
12
RH168
0_0402_5%~D
1 2
RH174 10K_0402_5%~D@
12
RH265 10K_0402_5%~D
12
RH20310K_0402_5%~D
12
RH267 10K_0402_5%~D
1 2
RH270 10K_0402_5%~D
1 2
RH262390_0402_5%
1 2
RH162 0_0402_5%~D
1 2
RH256 10K_0402_5%~D
1 2
LPT_PCH_M_EDS
NCTF
CPU/Misc
GPIO
6 OF 11 5
UH1F
LYNXPOINT_BGA695
TACH6/GPIO70
G13
TACH7/GPIO71
H15
VSS BA1
VSS BC1
VSS N10
VSS A2
VSS BD45
VSS BD2
VSS BD44
VSS BD1
VSS B45
VSS B2
VSS B1
VSS A44
VSS A41
LAN_PHY_PW R_CTRL/GPIO12
K13
GPIO15
AB11
VSS A43
VSS A4
VSS E45
VSS E1
VSS D1
VSS BE3
VSS BE2
TACH4/GPIO68
C16
GPIO57
U12
SDATAOUT1/GPIO48
AN4
GPIO35/NMI#
AP1
GPIO28
AD11
GPIO34
AN6
GPIO27
R11
GPIO24
Y10
SCLOCK/GPIO22
BB4
TACH3/GPIO7
G15
TACH1/GPIO1
F13
PLTRST_PROC# AU4
THRMTRIP# AV1
PROCPW RGD AV3
RCIN# AT6
PECI AY1
SATA5GP/GPIO49
AK3
VSS B44
TACH5/GPIO69
D13
SATA3GP/GPIO37
AK1
SATA2GP/GPIO36
AT3
VSS
A5 VSS
C45 VSS
BE5 VSS
BE41
SDATAOUT0/GPIO39
AM3
SLOAD/GPIO38
AT7
TACH0/GPIO17
C14
SATA4GP/GPIO16
AN2
GPIO8
Y1
TACH2/GPIO6
A14
BMBUSY#/GPIO0
AT8
TP14 AN10
RH264 10K_0402_5%~D
12
RH57 20K_0402_5%~D
1 2
RH175
0_0402_5%~D
@
1 2
RH171 200K_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+PCH_USB_DCPSUS1
+PCH_USB_DCPSUS1
+PCH_VCCDSW_R
+VCCADAC
+PCH_VCCDSW
+PCH_USB_DCPSUS3
+PCH_USB_DCPSUS3
+PCH_VCCDSW
+1.05VS
+1.5VS
+3VS
+1.5VS +1.05V_+1.5V_RUN
+1.05VS
+1.05VS
+1.05VS
+1.05V
+1.05V_+1.5V_RUN
+1.05VS
+1.05V
+1.05V_+1.5V_RUN
+1.05V_+1.5V_RUN
+1.05VS +1.05V
+3VS
+3V_PCH
+1.05V_+1.5V_RUN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (7/9) Power
Custom
23 61Friday, June 22, 2012
2012/06/22 2013/06/21 Compal Electronics, Inc.
V_PROC_IO 1.05V 0.004 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK 0.306 A1.05V
VCCCLK3_3 0.055 A
Voltage Rail
3.3V
VCCVRM 0.179 A1.5V
Voltage S0 Iccmax Current (A)
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
VCCSUSHDA 3.3V 0.01 A
VCCSPI 3.3V 0.022 A
PCH Power Rail Table
VCCSUS3_3 3.3V 0.261 A
VCC 1.05V 1.29 A
VCCIO 1.05V 3.629 A
VCCDSW3_3 3.3V 0.015 A
VCCADAC1_5 1.5V 0.070 A
RH37 5.11_0402_1%~D@
1 2
CH46
1U_0402_6.3V6K~D
1
2
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
USB3
HVCMOS
FDI
CRT DAC
SATA
7 OF 11 5
UH1G
LYNXPOINT_BGA695
VCCVRM AN11
VCC
AE18
VCC
AE22
VCCASW
U20
VCCASW
U22
VCCASW
U24
VCCASW
V22
VCCASW
V24
VCCASW
Y18
VCCASW
Y20
VCCASW
Y22
VCCADAC1_5 P45
VSS P43
VCCADACBG3_3 M31
VCCVRM BB44
VCCIO AN34
VCCIO AN35
VCC3_3_R30 R30
VCC3_3_R32 R32
DCPSUS1 Y12
VCCSUS3_3 AJ30
VCCSUS3_3 AJ32
DCPSUS3 AJ26
DCPSUS3 AJ28
VCCIO AK20
VCCVRM AK26
VCCVRM AK28
VCCIO AK18
VCCVRM BE22
VCCIO AM22
VCCIO AP22
VCCIO AR22
VCCIO AT22
VCCASW
V18
VCCASW
V20
VCCASW
U18 VCCASW
AA18 DCPSUSBYP
U14
VCC
Y26 VCC
AG24 VCC
AG22 VCC
AG20
VCC
AA24
VCC
AA26
VCC
AD20
VCC
AD24 VCC
AD22
VCC
AD26
VCC
AD28
VCCIO AK22
VCCIO AM20
VCCIO AM18
VCC
AG18 VCC
AE26 VCC
AE24
VCC
AE20
CH64
22U_0805_6.3V6M~D
C_0805NEW
1
2
CH60
0.1U_0402_10V7K~D
1
2
CH80
0.1U_0402_10V7K~D
1
2
CH34
1U_0402_6.3V6K~D
@
1
2
RH197 0_0603_5%~D
12
CH33
1U_0402_6.3V6K~D
1
2
CH61
1U_0402_6.3V6K~D
@
1
2
CH31
1U_0402_6.3V6K~D
1
2
RH2110_0603_5%~D
1 2
RH3600_0402_5%~D @
12
CH85
10U_0603_6.3V6M~D
@
1
2
CH39
1U_0402_6.3V6K~D
@
1
2
CH82
10U_0603_6.3V6M~D
@
1
2
CH156
10U_0603_6.3V6M~D
1
2
RH2090_0603_5%~D @
1 2
CH83
10U_0603_6.3V6M~D
@
1
2
CH48
1U_0402_6.3V6K~D
1
2
CH36
1U_0402_6.3V6K~D
1
2
LH1
BLM18PG181SN1_0603~D
12
CH32
1U_0402_6.3V6K~D
1
2
CH81
10U_0603_6.3V6M~D
@
1
2
CH86
1U_0402_6.3V6K~D
1
2
CH38
0.1U_0402_10V7K~D
1
2
CH57
0.01U_0402_16V7K~D
1
2
CH47
1U_0402_6.3V6K~D
1
2
CH44
10U_0603_6.3V6M~D
1
2
CH35
1U_0402_6.3V6K~D
1
2
CH45
1U_0402_6.3V6K~D
1
2
RH198 0_0603_5%~D@
12
CH40
10U_0603_6.3V6M~D
@
1
2
CH30
10U_0603_6.3V6M~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+PCH_USB_DCPSUS2
+PCH_USB_DCPSUS2
+PCH_VCCSST
+PCH_VCCCFUSE
+PCH_DCPRTC
+PCH_VPROC
+PCH_VPROC
+PCH_VCCDSW 3_3
+PCH_VCCCFUSE
+PCH_VCC+PCH_VCC
+PCH_VCC
+1.05VS
+1.05VS
+3VS
+1.05V_+1.5V_RUN
+3VS
+3V_PCH
+3VALW
+3VS
+1.05VS
+3V_PCH
+3V_PCH
+1.05VS
+3V_PCH
+3VS
+1.05V
+1.5VS
+1.05VS
+1.05VS +PCH_VCCCLK
+PCH_VCCCLK
+PCH_VCCCLK
+3V_PCH
+PCH_VCCCLK3_3
+PCH_VCCCLK3_3
+RTC_CELL
+3V_PCH
+1.05V
+3VS
+PCH_VCCDSW 3_3
+1.05VS_VCC+1.05VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
PCH (8/9) Power
Custom
24 61Friday, June 22, 2012
2012/06/22 2013/06/21
Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
Compal Electronics, Inc.
Place near pin AP45
CH75
1U_0402_6.3V6K~D
1
2
CH65
0.1U_0402_10V7K~D
1
2
CH67
1U_0402_6.3V6K~D
1
2
CH51
1U_0402_6.3V6K~D
1
2
CH77
1U_0402_6.3V6K~D
1
2
RH2200_0805_5%~D
12
CH53
1U_0402_6.3V6K~D
1
2
CH76
0.1U_0402_10V7K~D
1
2
CH72
0.1U_0402_10V7K~D
1
2
RH214 0_0805_5%~D
1 2
CH55
10U_0603_6.3V6M~D
1
2
CH74
1U_0402_6.3V6K~D
1
2
CH49
1U_0402_6.3V6K~D
1
2
CH63
0.1U_0402_10V7K~D
1
2
CH84 0.1U_0402_10V7K~D
1 2
RH361 0_0402_5%~D@
1 2
RH2210_0805_5%~D @
12
RH207 0_0603_5%~D
1 2
CH78
1U_0402_6.3V6K~D
1
2
CH79
1U_0402_6.3V6K~D
1
2
CH70
0.1U_0402_10V7K~D
1 2
CH87
1U_0402_6.3V6K~D
@
1
2
CH71
1U_0402_6.3V6K~D
1
2
RH2130_0402_5%~D @
12
CH155
0.1U_0402_10V7K~D
1
2
CH66
0.1U_0402_10V7K~D
1
2
CH42
10U_0603_6.3V6M~D
1
2
CH69
0.1U_0402_10V7K~D
1
2
RH212 0_0805_5%~D
1 2
LH100
4.7UH_LQM18FN4R7M00D_20%~D
1 2
RH2190_0805_5%~D
12
CH59
1U_0402_6.3V6K~D
1
2
RH2530_0402_5%~D
12
CH73
0.1U_0402_10V7K~D
1
2
CH50
1U_0402_6.3V6K~D
1
2
CH43
10U_0603_6.3V6M~D
@
1
2
CH62
0.1U_0402_10V7K~D
1
2
CH90
0.1U_0402_10V7K~D
1
2
CH52
1U_0402_6.3V6K~D
1
2
CH54
1U_0402_6.3V6K~D
1
2
CH58
1U_0402_6.3V6K~D
1
2
LPT_PCH_M_EDS
ICC
Thermal
Fuse
SPI
CPU
RTC
Azalia
GPIO/LPC
USB
8 OF 11 5
UH1H
LYNXPOINT_BGA695
VCCSUS3_3
R26
VCCSUS3_3
R28
VCCSUS3_3
U26
VSS
M24
VCCUSBPLL
U35
VCC3_3
L24
VCCIO
U30
VCCIO
V30 VCCIO
V28
VCCCLK
Y32
VCCCLK3_3
M29
VCCCLK3_3
L29
VCCCLK3_3
L26
VCCCLK3_3
M26
VCCCLK3_3
U32
VCCCLK3_3
V32
VCCCLK
AD34
VCCCLK
AA30
VCCCLK
AA32
VCCCLK
AD35
VCCCLK
AG30
VCCCLK
AG32
VCCCLK
AD36
VCCCLK
AE30
VCCCLK
AE32
VCCSUS3_3 R20
VCCSUS3_3 R22
VCCDSW3_3 A16
DCPSST AA14
VCC3_3 AE14
VCC3_3 AF12
VCC3_3 AG14
VCCIO U36
VCCSUSHDA A26
VCCSUS3_3 K8
VCCRTC A6
DCPRTC P14
DCPRTC P16
V_PROC_IO AJ12
V_PROC_IO AJ14
VCCSPI AD12
VCC P18
VCC P20
VCCASW L17
VCCASW R18
VCCVRM AW 40
VCC3_3 AK30
VCC3_3 AK32
VCC
AP45
VCCVRM
AF34
DCPSUS2
Y35
VCCIO
Y30
VCCSUS3_3
R24
CH37
1U_0402_6.3V6K~D
1
2
CH68
0.1U_0402_10V7K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
PCH (9/9) Power
Custom
25 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
LPT_PCH_M_EDS
511 OF 11
UH1K
LYNXPOINT_BGA695
VSS D4
VSS BC16
VSS G2
VSS G38
VSS G44
VSS G8
VSS H10
VSS H13
VSS
AB8
VSS BD31
VSS BD35
VSS BD39
VSS BD7
VSS AV7
VSS F20
VSS F33
VSS
AA16
VSS H36
VSS H26
VSS H17
VSS H22
VSS H24
VSS F29
VSS F15
VSS D25
VSS
AC2
VSS
AB38
VSS
AJ20 VSS
AJ18
VSS
AJ24 VSS
AJ22
VSS K33
VSS K29
VSS K20
VSS K15
VSS K10
VSS H7
VSS H40
VSS H31
VSS AT43
VSS AY36
VSS BD19
VSS BD15
VSS BD11
VSS BA40
VSS B7
VSS B39
VSS B35
VSS B31
VSS B27
VSS B23
VSS B19
VSS
AL2 VSS
AL12 VSS
AK45 VSS
AK43 VSS
AK24 VSS
AK14 VSS
AJ8 VSS
AJ6 VSS
AJ38 VSS
AJ34
VSS
AJ16
VSS
AG16 VSS
AF8 VSS
AF38 VSS
AE28 VSS
AE16 VSS
AD8
VSS
AD16 VSS
AD14 VSS
AC44
VSS
AB34 VSS
AB12 VSS
AA4 VSS
AA28 VSS
AA22 VSS
AA20
VSS
AG44 VSS
AG28 VSS
AG26 VSS
AG2
VSS
AD32 VSS
AD30 VSS
AD18
VSS
BB42 VSS
BC22
VSS BC28
VSS
AD6 VSS
AD40
LPT_PCH_M_EDS
510 OF 11
UH1J
LYNXPOINT_BGA695
VSS
AV31
VSS
BB25
VSS
AV40
VSS
AV33
VSS
AV13 VSS
D42
VSS
AT36
VSS
AT26 VSS
AT20 VSS
AT17
VSS
AT29
VSS
AV24
VSS N12
VSS N39
VSS N35
VSS N6
VSS P24
VSS P22
VSS P30
VSS P28
VSS P26
VSS P32
VSS R12
VSS R2
VSS R16
VSS R14
VSS R38
VSS R34
VSS R44
VSS T43
VSS R8
VSS U16
VSS U10
VSS U28
VSS U34
VSS U38
VSS U6
VSS U42
VSS V14
VSS V16
VSS V26
VSS W44
VSS W2
VSS V43
VSS Y16
VSS Y14
VSS Y24
VSS Y34
VSS Y28
VSS Y40
VSS Y36
VSS Y8
VSS
AT38
VSS
F43
VSS
AT15 VSS
AT10 VSS
AK16 VSS
AR2 VSS
AP43
VSS
AP24
VSS
AN40 VSS
AN36
VSS
AM30 VSS
AM28
VSS M22
VSS M17
VSS L44
VSS L2
VSS K39
VSS
B15 VSS
B11 VSS
AY7 VSS
AY29 VSS
AY26 VSS
AY20 VSS
AY15 VSS
AY10
VSS
AW2 VSS
AV6
VSS
AP31
VSS
AP13 VSS
AN8
VSS
AM32
VSS
AM26 VSS
AM24 VSS
AM14 VSS
AL8 VSS
AL38 VSS
AL34
VSS
AN42
VSS
AM16
VSS
AV22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPU_HDMI_TXD0+
PEG_GTX_HRX_N[0..15]
PEG_GTX_HRX_P[0..15]
PEG_HTX_C_GRX_N[0..15]
PEG_HTX_C_GRX_P[0..15]
VGA_DPD_P2
VGA_DPD_N2
VGA_SMB_DA1
GPU_HDMI_TXD1+
VGA_LCD_DAT
MXM_CURI2C_CLK
B+_MXM_A1
MXM_CURI2C_DATA
B+_MXM_A0
VGA_PS_0
VGA_LCD_CLK
GPU_HDMI_TXD2-
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15
PEG_GTX_HRX_N3
PEG_GTX_HRX_P3
PEG_GTX_HRX_N4
PEG_GTX_HRX_P4
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_P6
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_P10
PEG_GTX_HRX_N11
PEG_GTX_HRX_P11
PEG_GTX_HRX_N12
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_HRX_P12
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_HRX_P15
PEG_GTX_HRX_N15
VGA_DISABLE#
VGA_TH_OVERT#
MXM_DPB_AUXN/DDC
MXM_DPB_AUXP/DDC
MXM_TX2N
MXM_TX2P
MXM_TX3N
VGA_SMB_DA1
VGA_SMB_CK1
MXM_TX3P
MXM_TX1N
MXM_TX1P
MXM_TX0N
MXM_TX0P
DGPU_PW ROK
AC_BATT#
VGA_PRSNT_R#
DGPU_PW R_EN
VGA_WAKE#
VGA_LCD_CLK
VGA_LCD_DAT
VGA_SMB_CK1
VGA_DMC_HPD
VGA_DPD_P0
CLK_PEG_PCH#_R
MXM_CURI2C_DATA
VGA_DPD_P3
VGA_DPD_N3
GPU_HDMI_TXC+
GPU_HDMI_TXC-
PEG_GTX_HRX_P2
DGPU_PW ROK
PEG_GTX_HRX_N2
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0PEG_GTX_HRX_N0
PEG_GTX_HRX_P0
VGA_SMB_CK1
B+_MXM_A1
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
VGA_TH_OVERT#
GPU_HDMI_TXD2+
VGA_SMB_DA1
VGA_DISABLE#
VGA_HDMI_CEC
VGA_WAKE#
CLK_PEG_PCH_R
GPU_HDMI_TXD0-
VGA_DPD_P1
VGA_DPD_N1
PEG_CLKREQ#
PLTRST_VGA#
VGA_HDMI_DET
AC_BATT#
VGA_DPC_HPD
VGA_DPC_AUXP/DDC
GPU_HDMI_SCLK
GPU_HDMI_SDATA
VGA_DPC_AUXN/DDC
VGA_DPC_P1
VGA_DPC_N1
VGA_DPC_N2
VGA_DPC_N3
VGA_DPC_P3
VGA_DPC_P2
VGA_DPC_N0
VGA_DPC_P0
B+_MXM_A0
MXM_CURI2C_CLK
MXM_DPB_HPD
VGA_PS_0
VGA_PS_1
VGA_PS_2
GPU_HDMI_TXD1-
VGA_PS_2
VGA_HDMI_CEC
VGA_DPD_N0
VGA_PS_0
LVDS_MXM_TZCLK-
LVDS_MXM_TZCLK+
LVDS_MXM_TZOUT2-
LVDS_MXM_TZOUT2+
LVDS_MXM_TZOUT1-
LVDS_MXM_TZOUT1+
LVDS_MXM_TZOUT0-
LVDS_MXM_TZOUT0+
LVDS_MXM_TXCLK-
LVDS_MXM_TXCLK+
LVDS_MXM_TXOUT2-
LVDS_MXM_TXOUT2+
LVDS_MXM_TXOUT1-
LVDS_MXM_TXOUT1+
LVDS_MXM_TXOUT0-
LVDS_MXM_TXOUT0+
VGA_PS_1
AC_BATT#
+5V_MXM
+3V_MXM
+3V_MXM
+3V_MXM
+5V_MXM
+5VMXM
B+_MXM
+3V_MXM
+3V_MXM
B+_MXM
+3V_MXM+3V_MXM
+3V_MXM
+3V_MXM +3VALW
+3V_MXM
+3V_MXM +3VMXM
+3V_MXM
+3VALW
VGA_DPD_P0<39>
VGA_DPD_N0<39>
VGA_DPD_P1<39>
VGA_DPD_N1<39>
GPU_HDMI_SCLK<36>
EC_SMB_CK1<43>
EC_SMB_DA1<43>
MXM_TX1N <32>
MXM_TX1P <32>
GPU_HDMI_TXD0+<36>
GPU_HDMI_TXD0-<36>
GPU_HDMI_TXC+<36>
GPU_HDMI_TXC-<36>
PEG_HTX_C_GRX_P[0..15]<5>
ACIN<17,43,47,57,63>
VGA_DPC_P1 <30>
VGA_DPC_HPD <30>
VGA_DMC_HPD <39>
GPU_HDMI_SDATA<36>
VGA_DPC_P2 <30>
VGA_DPC_N2 <30>
MXM_DPB_AUXP/DDC <32>
MXM_TX0N <32>
MXM_TX0P <32>
MXM_DPB_AUXN/DDC <32>
GPU_HDMI_TXD2+<36>
GPU_HDMI_TXD2-<36>
EC_AC_BAT#<43>
MXM_TX2N <32>
MXM_TX2P <32>
PEG_GTX_HRX_P[0..15]<5>
VGA_PRSNT_R# <21>
VGA_DPC_N0 <30>
SPDIF_OUT
GPU_HDMI_TXD1+<36>
GPU_HDMI_TXD1-<36>
DGPU_PW ROK <30,43>
VIN+<63>
VIN-<63>
VGA_DPC_AUXP/DDC <30>
VGA_DPC_AUXN/DDC <30>
VGA_DPC_P3 <30>
VGA_DPC_N3 <30>
DGPU_ENVDD<42>
PEG_CLKREQ# <18>
VGA_DPD_P2<39>
VGA_DPD_N2<39>
VGA_DPD_P3<39>
VGA_DPD_N3<39>
DGPU_BKL_EN<42>
TH_OVERT# <43>
VGA_HDMI_DET <36>
PLTRST_VGA# <17>
PEG_HTX_C_GRX_N[0..15]<5>
DGPU_PW R_EN <43,56>
VGA_DPC_P0 <30>
VGA_PNL_PWM<42>
CLK_PEG_PCH#<18>
CLK_PEG_PCH<18>
VGA_DPD_AUXN/DDC<39>
VGA_PRSNT_L#<21>
VGA_DPD_AUXP/DDC<39>
MXM_TX3N <32>
MXM_TX3P <32>
MXM_DPB_HPD <32>
VGA_DPC_N1 <30>
PEG_GTX_HRX_N[0..15]<5>
LVDS_MXM_TXOUT1- <41>
LVDS_MXM_TXOUT1+ <41>
LVDS_MXM_TXCLK- <41>
LVDS_MXM_TXOUT2- <41>
LVDS_MXM_TXOUT2+ <41>
LVDS_MXM_TXCLK+ <41>
LVDS_MXM_TZOUT1-<41>
LVDS_MXM_TZOUT1+<41>
LVDS_MXM_TZOUT2-<41>
LVDS_MXM_TZOUT2+<41>
LVDS_MXM_TZOUT0-<41>
LVDS_MXM_TZOUT0+<41>
LVDS_MXM_TZCLK-<41>
LVDS_MXM_TZCLK+<41>
LVDS_MXM_TXOUT0+ <41>
LVDS_MXM_TXOUT0- <41>
VGA_LCD_DAT<42>
VGA_LCD_CLK<42>
FB_CLAMP<43>
FB_CLAMP_TGL_REQ# <43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
MXMIII Connector
Custom
26 61Friday, June 22, 2012
2012/06/22 2013/06/21
CRT
LVDS TZ
LVDS TX
SYSTEM
100mil(2.5A, 5VIA)
Add R7 increase NV MXM PEG Swing
DMC
mDP
LVDS DDC Module have 4.7K Pull-UP
400mil(10A)
40mil(1A)
eDP
HDMI
For B+_MXM
slave address : 1000010
please placemnet near R-sense
(Pull-UP 10K at PCH)
Place CV9, CV10, CV11
close MXM connector
Compal Electronics, Inc.
CV11 0.01U_0402_16V7K~D@
12
RV89 0_0402_5%~D
1 2
CV3
68P_0402_50V8J~D
1
2
CV9 0.01U_0402_16V7K~D@
12
J13
PAD-OPEN 4x4m
@
12
RV68 10K_0402_5%~D
1 2
CV10 0.01U_0402_16V7K~D@
12
RV69 10K_0402_5%~D@
1 2
UV4
MC74VHC1G09DFT2G_SC70-5
B
1
A
2Y4
VCC 5
G
3
CV5
0.1U_0402_25V6K~D
1
2
RV74
4.7K_0402_5%~D
12
RV67 10K_0402_5%~D
12
RV81 36K_0402_1%@
1 2
J12
PAD-OPEN 4x4m
@
12
RV72
10K_0402_5%~D
12
RV84
10K_0402_5%~D
@
1 2
RV94 0_0402_5%~D
@
1 2
CV1
10U_1206_25V6M~D
1
2
RV86
10K_0402_5%~D
@
1 2
E1 E2
E3 E4
JMXM1A
JAE_MM70-314-310B1-1-R300
CONN@
PRSNT_R# 38
WAKE# 40
PWR_GOOD 42
PWR_EN 44
RSVD 46
RSVD 48
RSVD 50
RSVD 52
PWR_LEVEL 54
TH_OVERT# 56
TH_ALERT# 58
TH_PW M 60
GPIO0 62
GPIO1 64
GPIO2 66
SMB_DAT 68
SMB_CLK 70
GND 72
OEM 74
OEM 76
OEM 78
OEM 80
GND 82
PEX_TX15# 84
PEX_TX15 86
GND 88
PEX_TX14# 90
PEX_TX14 92
GND 94
PEX_TX13# 96
PEX_TX13 98
GND 100
PEX_TX12# 102
PEX_TX12 104
GND 106
PEX_TX11# 108
PEX_TX11 110
GND 112
PEX_TX10# 114
PEX_TX10 116
GND 118
PEX_TX9# 120
PEX_TX9 122
GND 124
PEX_TX8# 126
PEX_TX8 128
GND 130
PEX_TX7# 132
PEX_TX7 134
GND 136
PEX_TX6# 138
PEX_TX6 140
GND 142
PEX_TX5# 144
PEX_TX5 146
GND 148
PEX_TX4# 150
PEX_TX4 152
GND 154
PEX_TX3# 156
PEX_TX3 158
GND 160
PWR_SRC
1
5V
37
5V
39
5V
41
5V
43
5V
45
GND
47
GND
49
GND
51
GND
53
PEX_STD_SW #
55
VGA_DISABLE#
57
PNL_PW R_EN
59
PNL_BL_EN
61
PNL_BL_PWM
63
HDMI_CEC
65
DVI_HPD
67
LVDS_DDC_DAT
69
LVDS_DDC_CLK
71
GND
73
OEM
75
OEM
77
OEM
79
OEM
81
GND
83
PEX_RX15#
85
PEX_RX15
87
GND
89
PEX_RX14#
91
PEX_RX14
93
GND
95
PEX_RX13#
97
PEX_RX13
99
GND
101
PEX_RX12#
103
PEX_RX12
105
GND
107
PEX_RX11#
109
PEX_RX11
111
GND
113
PEX_RX10#
115
PEX_RX10
117
GND
119
PEX_RX9#
121
PEX_RX9
123
GND
125
PEX_RX8#
127
PEX_RX8
129
GND
131
PEX_RX7#
133
PEX_RX7
135
GND
137
PEX_RX6#
139
PEX_RX6
141
GND
143
PEX_RX5#
145
PEX_RX5
147
GND
149
PEX_RX4#
151
PEX_RX4
153
GND
155
PEX_RX3#
157
PEX_RX3
159
GND
161
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
GND
33
GND
19
GND
25 GND
23
GND
29
GND
21
GND
27
GND
35
GND
31
PWR_SRC 10
PWR_SRC 2
PWR_SRC 18
PWR_SRC 14
PWR_SRC 16
PWR_SRC 6
PWR_SRC 12
PWR_SRC 8
PWR_SRC 4
GND 20
GND 26
GND 22
GND 36
GND 32
GND 30
GND 34
GND 24
GND 28
D
G
S
QV8
SSM3K7002F_SC59-3~D
1 3
2
RV87
10K_0402_5%~D
1 2
RV88 0_0402_5%~D
1 2
CV2
680P_0603_50V7K~D
1
2
CV4
0.1U_0603_25V7K~D
1
2
D
G
S
QV7
SSM3K7002F_SC59-3~D
13
2
RV78 0_0402_5%~D
1 2
CV8
4.7U_0805_10V4Z~D
1
2
UV5
HPA00900AIDCNR_SOT23-8
VIN+
1
SCL 5
VIN-
2
VS
4SDA 6
A0 7
GND
3
A1 8
RV82
10K_0402_5%~D
1 2
CV6
0.1U_0402_16V4Z~D
1
2
RV63 4.3K_0402_5%
1 2
RV77 0_0402_5%~D
1 2
RV92
0_0402_5%~D
1 2
RV64 3.3K_0402_5%@
1 2
JMXM1B
JAE_MM70-314-310B1-1-R300
CONN@
GND
163 GND 162
GND
169 GND 168
GND
175 GND 174
GND
181 GND 180
VGA_DDC_DAT 186
PEX_RX2#
165
PEX_RX1#
171
PEX_RX0#
177
PEX_TX2# 164
PEX_TX1# 170
PEX_TX0# 176
PEX_RX0
179
PEX_RX1
173
PEX_RX2
167
PEX_TX0 178
PEX_TX1 172
PEX_TX2 166
PEX_REFCLK#
183 PEX_CLK_REQ# 182
PEX_REFCLK
185 PEX_RST# 184
GND
187
RSVD
189 VGA_DDC_CLK 188
VGA_VSYNC 190
VGA_HSYNC 192
VGA_RED 196
VGA_GREEN 198
GND 202
GND 208
GND 214
GND 220
LVDS_LTX1# 222
LVDS_LTX2# 216
LVDS_LTX3# 210
LVDS_LCLK# 204
GND 226
GND 232
GND 238
GND 244
LVDS_LTX0# 228
DP_D_L0# 234
DP_D_L1# 240
DP_D_L2# 246
DP_D_L2 248
DP_D_L1 242
DP_D_L0 236
LVDS_LTX0 230
LVDS_LTX1 224
LVDS_LTX2 218
LVDS_LTX3 212
LVDS_LCLK 206
VGA_BLUE 200
GND 194
RSVD
191
RSVD
197
GND
203
GND
209
GND
215
GND
221
GND
227
GND
233
GND
239
GND
245
LVDS_UCLK#
199
LVDS_UTX3#
205
LVDS_UTX2#
211
LVDS_UTX1#
217
RSVD
193
RSVD
195
LVDS_UTX1
219
LVDS_UTX2
213
LVDS_UTX3
207
LVDS_UCLK
201
LVDS_UTX0#
223
DP_C_L0#
229
DP_C_L1#
235
DP_C_L2#
241
LVDS_UTX0
225
DP_C_L0
231
DP_C_L1
237
DP_C_L2
243
DP_C_L3#
247
DP_C_L3
249
GND
251
DP_C_AUX#
253 GND 250
DP_D_L3# 252
DP_C_AUX
255 DP_D_L3 254
RSVD
257 GND 256
RSVD
259 DP_D_AUX# 258
RSVD
261 DP_D_AUX 260
RSVD
263 DP_C_HPD 262
RSVD
265 DP_D_HPD 264
RSVD
267 RSVD 266
RSVD
269 RSVD 268
RSVD
271 RSVD 270
RSVD
273 GND 272
RSVD
275 DP_B_L0# 274
RSVD
277 DP_B_L0 276
RSVD
279
DP_A_L0
285
DP_A_L1
291
DP_A_L2
297
DP_A_L3
303
GND
305
DP_A_AUX#
307
DP_A_AUX
309
PRSNT_L#
310
GND
281
GND
287
GND
293
GND
299
GND 278
GND 284
GND 290
GND 296
DP_B_HPD 302
DP_A_HPD 304
3V3 306
3V3 308
DP_B_L1# 280
DP_B_L2# 286
DP_B_L3# 292
DP_B_AUX# 298
DP_A_L0#
283
DP_A_L1#
289
DP_A_L3#
301
DP_A_L2#
295
DP_B_AUX 300
DP_B_L3 294
DP_B_L2 288
DP_B_L1 282
GND
311 GND 312
CV7
10U_0603_6.3V6M~D
1
2
RV85
0_0402_5%~D
@
1 2
RV910_0402_5%~D
12
CV12
.1U_0402_16V7K~D
@
1
2
RV76 0_0402_5%~D
1 2
D
G
S
QV6
SSM3K7002F_SC59-3~D
1 3
2
RV83
0_0402_5%~D
@
1 2
RV75 10K_0402_5%~D@
1 2
RV65 4.3K_0402_5%
1 2
RV73
4.7K_0402_5%~D
12
RV80 10K_0402_5%~D@
1 2
RV900_0402_5%~D
12
RV66 3.3K_0402_5%@
1 2
RV79 10K_0402_5%~D
1 2
RV70 10K_0402_5%~D
12
RV71
10K_0402_5%~D
12
RV93 0_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DISP_HPD_SINK
CPU_MXM_MDP_AUXP
DP_CFG1_INPUT
CPU_MXM_MDP_AUXN
DP_PEQ
DP_RST#
DP_CFG0
CPU_MXM_MDP_AUXP
CPU_MXM_MDP_P0_R
CPU_MXM_MDP_N0_R
CPU_MXM_MDP_AUXN
CPU_MXM_MDP_P1_R
CPU_MXM_MDP_N1_R
MDP_CAB_DET
CPU_MXM_MDP_P2_R
CPU_MXM_MDP_N2_R
DISP_HPD_SINK
CPU_MXM_MDP_P3_R
CPU_MXM_MDP_N3_R
CPU_MXM_MDP_P2_C
CPU_MXM_MDP_N2_C
CPU_MXM_MDP_N1_C
CPU_MXM_MDP_P0_C
CPU_MXM_MDP_P1_C
CPU_MXM_MDP_N3_C
CPU_MXM_MDP_N0_C
CPU_MXM_MDP_P3_C
CPU_MXM_MDP_P0
CPU_MXM_MDP_N0
CPU_MXM_MDP_P1
CPU_MXM_MDP_N1
CPU_MXM_MDP_P2
CPU_MXM_MDP_N2
CPU_MXM_MDP_P3
CPU_MXM_MDP_N3
CAB_DET_SINKDP_POWER_DOW N#
VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC
CPU_MXM_MDP_P0
CPU_MXM_MDP_N0
CPU_MXM_MDP_P1
CPU_MXM_MDP_P3
CPU_MXM_MDP_N1
CPU_MXM_MDP_N3
CPU_MXM_MDP_P2
CPU_MXM_MDP_N2
DP_PEQ
DP_CFG1_INPUT
DP_POWER_DOW N#
DP_CFG0
DP_CFG0
DP_POWER_DOW N#
DP_PEQ
DP_CFG1_INPUT
DP_RST#
CPU_MXM_MDP_AUXP
CPU_MXM_MDP_AUXN
MDP_CAB_DET#
VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC
MDP_CAB_DET
CAB_DET_SINK
DISP_CEC
CAB_DET_SINK
DISP_CEC
DISP_HPD_SINK
CPU_MXM_MDP_AUXN_L_C
CPU_MXM_MDP_AUXP_L_C
VGA_DPC_HPD
VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC
VGA_DPC_P0
VGA_DPC_N0
VGA_DPC_P1
VGA_DPC_N1
VGA_DPC_P2
VGA_DPC_N2
VGA_DPC_P3
VGA_DPC_N3
VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC
VGA_DPC_HPD
DP_PCH_HPD
DP_PCH_HPD
+3VS
+3VS_DP
+3VS
+3VS_DP
+3VS
+3VS
+3VS
+5VS
+3VS_DP
+3VS
DP_MXM_CARD_SEL <32,43>
DP_CBL_DET<17>
VGA_DPC_AUXN/DDC<29>
VGA_DPC_AUXP/DDC<29>
VGA_DPC_P1<29>
VGA_DPC_N0<29>
VGA_DPC_P0<29>
VGA_DPC_N2<29>
VGA_DPC_P2<29>
VGA_DPC_N1<29>
VGA_DPC_N3<29>
VGA_DPC_P3<29>
VGA_DPC_HPD<29> DGPU_PWROK <29,43>
DP_PCH_HPD<16>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
Mini DP/Thunder Bolt power
Custom
27 61Friday, June 22, 2012
2012/06/22 2013/06/21
Mini DP CONN
Need apply CIS part
Co-lay
Compal Electronics, Inc.
DP Redriver
MXM_MFG_SEL
NVDIA
GPU Source
0
1 ATI
CV26 0.1U_0402_10V6K~D
12
RV127
100K_0402_5%~D
12
RV994.7K_0402_5%~D @
12
G
D
S
QV9
BSS138_SOT23~D
2
13
CV487
0.1U_0402_16V4Z~D
1 2
CV20 0.1U_0402_10V6K~D
12
CV28 0.1U_0402_10V6K~D
12
CV36
.1U_0402_16V7K~D
1
2
CV25 0.1U_0402_10V6K~D
12
CV19 0.1U_0402_10V6K~D
12
RV1064.7K_0402_5%~D @
12
CV17 0.1U_0402_10V6K~D
12
CV29 2.2U_0402_6.3V6M~D
12
RV124
1M_0402_5%~D
1 2
CV23 0.1U_0402_10V6K~D
12
RV118
0_0402_5%
1 2
CV41
0.1U_0402_16V4Z~D
1
2
CV38
0.1U_0402_25V6K~D
1
2
RV1014.7K_0402_5%~D
12
FV4
1.5A_6V_1206L150PR~D
1 2
RV126
100K_0402_5%~D
12
RV1004.7K_0402_5%~D @
12
RV398 100K_0402_5%~D
12
RV1044.7K_0402_5%~D @
12
RV121
1M_0402_5%~D
@
1 2
RV655
0_0402_5%~D
@
12
RV112 100K_0402_5%~D
12
RV1054.7K_0402_5%~D @
12
CV24 0.1U_0402_10V6K~D
12
CV27 0.1U_0402_10V6K~D
12
RV1084.7K_0402_5%~D @
12
RV114 0_1206_5%~D@
12
CV37
22U_0805_6.3V6M~D
1
2
CV13 0.1U_0402_10V6K~D
12
RV116
4.7K_0402_5%~D
1 2
RV115
4.7K_0402_5%~D
1 2
CV32
0.1U_0402_10V6K~D
12
RV117
100K_0402_5%~D
12
UV6
PS8330BQFN48GTR2-A0_QFN48_7X7
VCC4 25
OUT0p 23
OUT0n 22
OUT1p 20
OUT1n 19
OUT2p 17
OUT2n 16
OUT3p 14
OUT3n 13
VCC5 32
VCC6 36
IN0p
38
IN0n
39
IN1p
41
IN1n
42
IN2p
44
IN2n
45
IN3p
47
IN3n
48
CEXT 2
NC2 15
NC3 21
HPD_SRC
9
CAD_SNK 10
PD#
26
AUX_SNKN 27
AUX_SNKP 28
CFG1 40
HPD_SINK 11
VCC1 1
EPAD
49
VCC2 6
GND3
31
VCC3 12
GND1
18
GND2
24
SCL_CTL/PEQ
4
SDA_CTL/CFG0
5
REXT
7
CAD_SRC
8
I2C_ADDR
3
AUX_SRCN
29 AUX_SRCP
30
SDA_DDC
34 SCL_DDC
33
NC4 37
RST# 35
NC5 43
NC 46
CV31
0.1U_0402_10V6K~D
12
CV15 0.1U_0402_10V6K~D
12
RV984.7K_0402_5%~D @
12
CV302.2U_0402_6.3V6M~D
1 2
CV18 0.1U_0402_10V6K~D
12
RV1034.99K_0402_1%
1 2
CV22 0.1U_0402_10V6K~D
12
CV35
10U_0603_6.3V6M~D
1
2
RV113 100K_0402_5%~D
1 2
RV125
5.1M_0402_5%
1 2
CV14 0.1U_0402_10V6K~D
12
QV5B
DMN66D0LDW-7_SOT363-6~D
34
5
JMDP1
PS_613002-020121
CONN@
GND
19 AUX_CH_N
18 LANE2_N
17 AUX_CH_P
16 LANE2_P
15 GND
14 GND
13 LANE3_N
12 LANE1_N
11 LANE3_P
10 LANE1_P
9GND
8GND
7CONFIG2
6LANE0_N
5CONFIG1
4LANE0_P
3HPD
2GND
1
DP_PW R
20 GND4 24
GND3 23
GND2 22
GND1 21
RV10210K_0402_1%~D
12
UV8
CBTD3306PW_TSSOP8
1OE#
1
GND 4
2OE#
7
2A
51B 3
1A
2
2B 6
VCC 8
CV21 0.1U_0402_10V6K~D
12
CV16 0.1U_0402_10V6K~D
12
UV37
SN74AHC1G08DCKR_SC70-5
IN1 1
IN2 2
G
3
O
4
P5
QV5A
DMN66D0LDW-7_SOT363-6~D
61
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_EDP_P0_S
PC10
PC20
PEQ
CTL_EN
PL1
PL0
CFG_0
HPD_GPU
CPU_EDP_HPD# PEQ
PWDN
CFG_0
CFG_1
PC10
PC11
PC20
PC21
PL0
PL1
CTL_EN
HPD_GPU
CPU_EDP_HPD#
CPU_EDP_N0_S
CPU_EDP_N1_S
CPU_EDP_P1_S
2136_HPD#
CPU_EDP_P0_C
CPU_EDP_HPD#
CPU_EDP_N0_C
CPU_EDP_P1_C
CPU_EDP_N1_C
8338_EDP_P0_S
8338_EDP_N0_S
8338_EDP_P1_S
8338_EDP_N1_S
8338_EDP_P2_S
8338_EDP_N2_S
8338_EDP_P3_S
8338_EDP_N3_S
8338_EDP_P0
8338_EDP_N0
8338_EDP_P1
8338_EDP_N1
8338_EDP_P2
8338_EDP_N2
8338_EDP_P3
8338_EDP_N3
8338_EDP_HPD#
CPU_EDP_P0
CPU_EDP_N0
CPU_EDP_P1
CPU_EDP_N1
CPU_EDP_P2
CPU_EDP_N2
CPU_EDP_P3
CPU_EDP_N3
CPU_EDP_C_P0
CPU_EDP_C_N0
CPU_EDP_C_P1
CPU_EDP_C_N1
CPU_EDP_C_P2
CPU_EDP_C_N2
CPU_EDP_C_P3
CPU_EDP_C_N3
SW
CPU_EDP_AUX#
CPU_EDP_AUX CPU_EDP_AUXP
CPU_EDP_AUXN
8338_CA_DET
8338_CA_DET
8338_CA_DET
PC11
PC21
CFG_1
CPU_EDP_AUX_C
CPU_EDP_AUX#_C
8338_EDP_AUX
8338_EDP_AUX#
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
CPU_EDP_HPD#<8>
2136_HPD# <40>
CPU_EDP_P0_C <40>
CPU_EDP_N0_C <40>
CPU_EDP_P1_C <40>
CPU_EDP_N1_C <40>
8338_EDP_P0 <32>
8338_EDP_N0 <32>
8338_EDP_P1 <32>
8338_EDP_N1 <32>
8338_EDP_P2 <32>
8338_EDP_N2 <32>
8338_EDP_P3 <32>
8338_EDP_N3 <32>
8338_EDP_HPD# <32>
PANEL_SW <19,34>
CPU_EDP_N1<8>
CPU_EDP_N0<8>
CPU_EDP_P0<8>
CPU_EDP_P1<8>
CPU_EDP_P3<8>
CPU_EDP_P2<8>
CPU_EDP_N2<8>
CPU_EDP_N3<8>
CPU_EDP_AUX#<8>
CPU_EDP_AUX<8>
CPU_EDP_AUX_C <40>
8338_EDP_AUX# <32>
8338_EDP_AUX <32>
CPU_EDP_AUX#_C <40>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
CPU to EDP & LVDS MUX
Custom
28 61Friday, June 22, 2012
2012/06/22 2013/06/21
AUX interception disable for Port y (y = 1, 2). Internal pull
down at ~150K Ohm, 3.3V I/O;
L: AUX interception enable, driver configuration is set by
link training (default)
H: AUX interception disable, driver output with fixed 800mV
and 0dB
M: AUX interception disable, driver output with fixed 400mV
and 0dB
Output swing adjustment for Port y (y = 1, 2).
Internal pull down at ~150K Ohm, 3.3V I/O;
L: default
H: +20%
M: -16.7%
Programmable input equalization levels; Internal pull down at
~150K Ohm, 3.3V I/O.
L: default, LEQ, compensate channel loss up to 11.5dB @
HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
Chip operational mode configuration;
Internal pull down at ~150K Ohm, 3.3V I/O.
L: Control switching mode (default)
H: Automatic switching mode
Auto test enable; Internal pull down at ~150K Ohm, 3.3V I/O.
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
Chip operational mode configuration;
Internal pull down at ~150K Ohm, 3.3V I/O.
L: Automatic power down enable (default)
H: Automatic power down disable
Automatic EQ disable; Internal pull down at ~150K Ohm, 3.3V IO
L: Automatic EQ enable (default)
H: Automatic EQ disable
LVDS Panel
eDP Panel
CPU to EDP & LVDS MUX
CPU
SEL PANEL_SW
L
H
LVDS Panel
eDP Panel
CV324 0.1U_0402_16V7K
1 2
CV333 0.1U_0402_16V7K
1 2
UV7
PS8338BQFN60GTR-A0_QFN60_5X9
VDD33
5
IN_D0n
7
IN_D2p
12
IN_D2n
13
IN_D3p
15
IN_D3n
16
IN_D1p
9
IN_D1n
10
IN_D0p
6
VDD33
21
VDD33
30
VDD33
51
VDD33
57
GND
19 GND
11
PC21
53 PC20
54 PC11
55 PC10
56 CFG1
58 CFG0
59
OUT1_D0p 50
OUT1_D0n 49
OUT1_D1p 47
OUT1_D1n 46
OUT1_D2p 45
OUT1_D2n 44
OUT1_D3p 42
OUT1_D3n 41
IN_CA_DET
4
IN_HPD
3
I2C_CTL_EN
2
Pl1/SCL_CTL
1
IN_AUXp
24
IN_AUXn
25
OUT2_D0p 40
OUT2_D0n 39
OUT2_D1p 37
OUT2_D1n 36
OUT2_D2p 35
OUT2_D2n 34
OUT2_D3p 32
OUT2_D3n 31
OUT1_AUXp_SCL 26
OUT1_AUXn_SDA 27
OUT2_AUXp_SCL 28
OUT2_AUXn_SDA 29
OUT1_CA_DET 43
OUT1_HPD 48
OUT2_CA_DET 33
OUT2_HPD 38
PEQ 8
CEXT 17
GND
52
IN_DDC_SCL
22
IN_DDC_SDA
23
Pl0/SDA_CTL
60
PAD(GND)
61
PD 14
REXT 20
SW 18 RV41610K_0402_5% 12
CV337 0.1U_0402_16V7K
1 2
CV314
0.1U_0402_16V4Z
1
2
CV315
0.1U_0402_16V4Z
1
2
CV344 0.1U_0402_16V7K
1 2
RV513 4.7K_0402_5%
@1 2
CV334 0.1U_0402_16V7K
1 2
CV335 0.1U_0402_16V7K
1 2
RV509 4.7K_0402_5%
@1 2
RV521 4.7K_0402_5%
@1 2
RV405 1M_0402_5%~D
1 2
T143PAD~D
@
CV325 0.1U_0402_16V7K
1 2
RV511 4.7K_0402_5%
@1 2
CV331 0.1U_0402_16V7K
1 2
CV339 0.1U_0402_16V7K
1 2
RV512 4.7K_0402_5%
@1 2
CV1050.1U_0402_10V6K~D 12
RV518 4.7K_0402_5%
@1 2
G
D
S
QV54 SSM3K7002FU_SC70-3
2
13
CV338 0.1U_0402_16V7K
1 2
RV505 4.7K_0402_5%
@1 2
CV345 0.1U_0402_16V7K
1 2
CV1060.1U_0402_10V6K~D 12
CV317
2.2U_0402_6.3V6M
1
2
RV514 4.7K_0402_5%
@1 2
RV519 4.7K_0402_5%
1 2
RV510 4.7K_0402_5%
@1 2
RV506 4.7K_0402_5%
1 2
CV326 0.1U_0402_16V7K
1 2
CV323 0.1U_0402_16V7K
1 2
CV312
0.01U_0402_16V7K
1
2
CV342 0.1U_0402_16V7K
1 2
RV403 100K_0402_5%@
1 2
CV316
0.1U_0402_16V4Z
1
2
CV332 0.1U_0402_16V7K
1 2
RV515 4.7K_0402_5%
@1 2
RV520 4.7K_0402_5%
@1 2
CV340 0.1U_0402_16V7K
1 2
CV336 0.1U_0402_16V7K
1 2
CV346 0.1U_0402_16V7K
1 2
CV343 0.1U_0402_16V7K
1 2
RV508 4.7K_0402_5%
1 2
RV517 4.7K_0402_5%
@1 2
RV503 100K_0402_5%@1 2
RV516 4.7K_0402_5%
@1 2
RV404 100K_0402_5%
1 2
RV522 4.7K_0402_5%
@1 2
RV507 4.7K_0402_5%
@1 2
CV313
0.01U_0402_16V7K
1
2
RV504
4.99K_0402_1%
12
CV341 0.1U_0402_16V7K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU_MXM_EDP_AUXN
DGPU_SELECT#
LV_DP_HPD
MXM_DPB_AUXP/DDC_C
CFG_HPD_1
CPU_MXM_EDP_A1P
CPU_MXM_EDP_A0N
CPU_MXM_EDP_A0P
CPU_MXM_EDP_A1N
CPU_MXM_EDP_AUXN_L
MXM_DPB_AUXP/DDC
MXM_DPB_AUXN/DDC_C
MXM_DPB_AUXN/DDC
MXM_C_TX1P
MXM_C_TX3P
MXM_C_TX3N
MXM_C_TX0N
MXM_C_TX2N
MXM_C_TX1N
MXM_C_TX0P
MXM_C_TX2P DP_IN4_PEQ#
DP_IN4_AEQ#
DP_IN3_AEQ#
CFG_OUTPUT_1
DP_IN3_PEQ#
CFG_OUTPUT_1
CFG_HPD_1
DP_IN4_PEQ#
DP_IN3_PEQ#
DP_IN4_AEQ#
DP_IN3_AEQ#
CPU_MXM_EDP_A2N
CPU_MXM_EDP_A3N
CPU_MXM_EDP_A3P
CPU_MXM_EDP_A2P
CPU_MXM_EDP_AUXP_L
CPU_MXM_EDP_AUXP
8338_EDP_P1_C
8338_EDP_N1_C
8338_EDP_P0_C
8338_EDP_N0_C
8338_EDP_AUX#_C
8338_EDP_AUX_C
8338_EDP_P3_C
8338_EDP_P2_C
8338_EDP_N3_C
8338_EDP_N2_C
+3VS+3VS
+3VS+3VS
+3VS+3VS
MXM_DPB_HPD<29>
MXM_TX1N<29>
CPU_MXM_EDP_A0P <33>
8338_EDP_HPD#<31>
MXM_TX2N<29>
MXM_TX2P<29>
MXM_TX3N<29>
MXM_TX3P<29>
MXM_TX0N<29>
MXM_TX0P<29>
CPU_MXM_EDP_A0N <33>
CPU_MXM_EDP_A1P <33>
CPU_MXM_EDP_A1N <33>
CPU_MXM_EDP_A2P <33>
CPU_MXM_EDP_A2N <33>
CPU_MXM_EDP_A3P <33>
CPU_MXM_EDP_A3N <33>
DGPU_EDIDSEL# <21,36,42>
MXM_DPB_AUXN/DDC<29>
MXM_DPB_AUXP/DDC<29>
CPU_MXM_EDP_AUXN <33>
CPU_MXM_EDP_AUXP <33>
DGPU_SELECT# <17,36,42>
MXM_TX1P<29>
DP_MXM_CARD_SEL <30,43>
LV_DP_HPD <33>
8338_EDP_AUX#<31>
8338_EDP_AUX<31>
8338_EDP_P1<31>
8338_EDP_P0<31>
8338_EDP_N0<31>
8338_EDP_N1<31>
8338_EDP_P3<31>
8338_EDP_P2<31>
8338_EDP_N3<31>
8338_EDP_N2<31>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
eDP SW-CPU & MXM
Custom
29 61Friday, June 22, 2012
2012/06/22 2013/06/21
MXM_MFG_SEL
1
0
GPU Source
NVDIA
ATI
INy_AEQ# (y=1, 2),Automatic RX equalization enable
L:Disable input automatic equalization
H:Enable input automatic equalization
INy_PEQ(y = 1, 2),Programmable input
equalization level setting
L:Low EQ setting (LEQ), default
H:High EQ setting (HEQ)
M:No EQ
CFG_HPD,HPD switching configuration
L:HPD is switched by SW_ML
H:HPD is switched by SW_AUX
M:HPD is switched with overlap
CFG_OUTPUT: output configuration
L:Output is tracking DPCD register setting (auto interception)
H:Output swing level fixed at 600mV and no pre-emphasis
M:Output swing level is fixed at 400mV and no pre-emphasis
CPU & MXM SW for EDP
Compal Electronics, Inc.
MXM
SourceChanel
IN2
IN1 PS8838
1
0
AUX_SEL/SEL1&2
CV750.1U_0402_10V6K~D
12
CV3060.1U_0402_10V6K~D
12
RV137
100K_0402_5%~D
12
RV133
4.7K_0402_1%~D
@
12
RV132
4.7K_0402_1%~D
@
12
RV136
4.7K_0402_1%~D
@
1 2
CV730.1U_0402_10V6K~D
12
CV720.1U_0402_10V6K~D
12
RV140
4.7K_0402_1%~D
12
CV3080.1U_0402_10V6K~D
12
RV135
4.7K_0402_1%~D
1 2
CV760.1U_0402_10V6K~D
12
CV710.1U_0402_10V6K~D
12
CV680.1U_0402_10V6K~D
12
RV138
100K_0402_5%~D
12
CV81
2.2U_0402_6.3V6M~D
1
2
QV1B
DMN66D0LDW-7_SOT363-6~D
34
5
CV690.1U_0402_10V6K~D
12
RV130
4.7K_0402_1%~D
@
1 2
CV800.1U_0402_10V6K~D
12
CV62
0.1U_0402_16V4Z~D
1
2
RV129 4.7K_0402_1%~D
12
CV700.1U_0402_10V6K~D
12
UV9
PS8321QFN56GTR-A0_QFN56_7X7
IN1_D2p
1
IN1_D2n
2
IN1_AEQ#
3
IN1_D3p
4
IN1_D3n
5
IN1_HPD
6
IN2_D0p
7
IN2_D0n
8
IN2_HPD
9
IN2_D1p
10
IN2_D1n
11
GND 12
IN2_D2p
13
IN2_D2n
14
OUT_AUXp_SCL 28
OUT_AUXn_SDA 27
REXT 18
CEXT 17
IN2_D3n
16 IN2_D3p
15
OUT_D0p 42
OUT_D0n 41
PD 40
OUT_D1p 39
OUT_D1n 38
I2C_CTL_EN 37
OUT2_D2p 36
OUT2_D2n 35
CFG_OUTPUT 34
OUT_D3p 33
OUT_D3n 32
VDD
31
AC_AUXp 30
AC_AUXn 29
OUT_HPD 43
CA_DET 44
GND 45
SW_AUX 47
IN2_PEQ/SDA_CTL
49
IN1_PEQ/SCL_CTL
50
IN2_AEQ#
51
IN1_D0p
52
IN1_D0n
53
VDD
54
IN1_D1p
55
IN1_D1n
56
Epad 57
IN1_SDA
19 IN1_SCL
20
IN2_SDA
21 IN2_SCL
22
IN1_AUXn
23 IN1_AUXp
24
IN2_AUXn
25 IN2_AUXp
26
SW_ML/I2C_ADDR 48
CFG_HPD 46
QV1A
DMN66D0LDW-7_SOT363-6~D
61
2
RV131
4.7K_0402_1%~D
@
1 2
RV128 4.7K_0402_1%~D
12
CV790.1U_0402_10V6K~D
12
CV740.1U_0402_10V6K~D
12
CV63 0.1U_0402_10V6K~D
12
CV3070.1U_0402_10V6K~D
12
RV134
4.99K_0402_1%
12
CV64 0.1U_0402_10V6K~D
12
CV3050.1U_0402_10V6K~D
12
CV770.1U_0402_10V6K~D
12
CV650.1U_0402_10V6K~D
12
CV780.1U_0402_10V6K~D
12
RV139
4.7K_0402_1%~D
@
12
CV670.1U_0402_10V6K~D
12
RV406 1M_0402_5%~D
1 2
CV61
0.1U_0402_16V4Z~D
1
2
CV660.1U_0402_10V6K~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDP_A2P_CONN
EDP_A2N_CONNEDP_A2N
EDP_A2P
EDP_A0P_CONN
EDP_A0N_CONNEDP_A0N
EDP_A0P
USB20_P11_CONN
USB20_N11_CONN
EDP_AUX+
EDP_A0P
EDP_A0N
EDP_A1N
EDP_A1P
EDP_A1N_L
EDP_A1P_L
EDP_A0P_L
EDP_A0N_L
EDP_A2N
EDP_A3P
EDP_A3N
EDP_A2P
EDP_A2N_L
EDP_A2P_L
EDP_A3P_L
EDP_A3N_L
EDP_HPD
EDP_CAB_DET#_R
EDP_HPD
EDP_AUX-
EDP_AUX-
DMIC0_CONN
EDP_AUX+_CONN
EDP_AUX-_CONNEDP_AUX-
EDP_AUX+
EDP_A3P_CONN
DMIC_CLK_CONN
EDP_A3N_CONNEDP_A3N
EDP_A3P
EDP_AUX-_C
4028_EDP_AUXP_C
CPU_MXM_EDP_A2N
CPU_MXM_EDP_A1P
CPU_MXM_EDP_A0N
CPU_MXM_EDP_A0P
CPU_MXM_EDP_A3N
CPU_MXM_EDP_A3P
CPU_MXM_EDP_A2P
CPU_MXM_EDP_A1N
CPU_MXM_EDP_AUXP
4028_EDP_L2P
4028_EDP_L2N
4028_EDP_L0P
4028_EDP_L3P
4028_EDP_L3N
4028_EDP_L1P
4028_EDP_L1N
4028_EDP_L0N
DP_IN5_PEQ#
EDP_AUX+_CONN
CFG_OUTPUT_2
CFG_HPD_2
EDP_CAB_DET#
EDP_A0P_CONN
EDP_A0N_CONN
DMIC_CLK_CONN
DMIC0_CONN
DP_IN6_PEQ#
DP_IN5_PEQ#
EDP_AUX-_CONN
DP_IN6_AEQ#
EDP_A1N_CONN
EDP_A1P_CONN
EDP_A2N_CONN
EDP_A3P_CONN
EDP_A3N_CONN
EDP_A2P_CONN
HDMI_IN_SELECT#
4028_EDP_AUXN_C
DP_IN5_AEQ#
PWR_SRC_ON
CPU_MXM_EDP_AUXN
USB20_N11_CONN
EDP_HPD
CFG_OUTPUT_2
DMIC_CLK_CONN
DISPOFF#
DISPOFF#
LCD_TEST
CAM_DET# EDP_A1P_CONN
EDP_A1N_CONNEDP_A1N
EDP_A1P
USB20_P11_CONN
USB20_N11_CONN
USB20_P11
USB20_N11
EDP_AUX+
EDP_HPD
USB20_P11_CONN
EDP_AUX+_C
DP_IN6_PEQ#
DP_IN6_AEQ#
DP_IN5_AEQ#
CFG_HPD_2
DMIC0_CONN
EDP_CAB_DET#_R
+3VS
+EDPVDD
+EDPVDD+INVPWR_B++EDPVDD +5VS
+INVPWR_B+B+
+INVPWR_B+
+3VS
+EDPVDD
+3VS
+3VS
+3VS
+3VS_CAM
+3VS +3VS
+3VS_CAM
+3VS
+5VS
B+
+INVPWR_B+
+3VS
+EDPVDD
4028_EDP_AUXP<38>
4028_EDP_AUXN<38>
4028_EDP_L0N<38>
LCDVDD_ON<34,41,42>
EC_ENVDD<42,43>
4028_EDP_L1N<38>
4028_EDP_L1P<38>
CPU_MXM_EDP_AUXP<32>
CPU_MXM_EDP_AUXN<32>
CPU_MXM_EDP_A0N<32>
CPU_MXM_EDP_A1N<32>
CPU_MXM_EDP_A1P<32>
CPU_MXM_EDP_A2N<32>
CPU_MXM_EDP_A2P<32>
CPU_MXM_EDP_A0P<32>
CPU_MXM_EDP_A3N<32>
CPU_MXM_EDP_A3P<32>
4028_EDP_L2N<38>
4028_EDP_L2P<38>
4028_EDP_L0P<38>
DP_4028_HPD<38>
INV_PW M <42>
LV_DP_HPD<32>
USB20_P11<20>
USB20_N11<20>
DMIC0<42,45>
DMIC_CLK<42,45>
LCD_BKL_EN<43>
4028_EDP_L3N<38>
4028_EDP_L3P<38>
EDP_CAB_DET# <21>
LCD_TEST <42,43>
CAM_DET# <18,42>
HDMI_IN_SELECT# <42,43>
DISPOFF# <42>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
eDP SW-eDP CONN
Custom
30 61Friday, June 22, 2012
2012/06/22 2013/06/21
Close to JEDP1
Reserve
80 mil
CPU/MXM
Back light power
4028
SourceChanel
B
A
CPU/MXM1
0
AUX_SEL/SEL1&2
CPU/GPU & 4028 SW for DPB
80 mil
Panel backlight power control by EC
FDC654P: P CHANNAL
80 mil
4028
W=60mils
eDP POWER
Inverter power
INy_AEQ# (y=1, 2),Automatic RX equalization enable
L:Disable input automatic equalization
H:Enable input automatic equalization
INy_PEQ(y = 1, 2),Programmable input
equalization level setting
L:Low EQ setting (LEQ), default
H:High EQ setting (HEQ)
M:No EQ
CFG_HPD,HPD switching configuration
L:HPD is switched by SW_ML
H:HPD is switched by SW_AUX
M:HPD is switched with overlap
CFG_OUTPUT: output configuration
L:Output is tracking DPCD register setting (auto interception)
H:Output swing level fixed at 600mV and no pre-emphasis
M:Output swing level is fixed at 400mV and no pre-emphasis
Close to JEDP1
Compal Electronics, Inc.
CV113
120P_0402_50VNPO~D
@
1
2
RV158 47K_0402_5%~D
1 2
RV153 4.7K_0402_1%~D@
12
LV10
DLW21SN670HQ2L_4P~D
1 2
34
UV10
PS8321QFN56GTR-A0_QFN56_7X7
IN1_D2p
1
IN1_D2n
2
IN1_AEQ#
3
IN1_D3p
4
IN1_D3n
5
IN1_HPD
6
IN2_D0p
7
IN2_D0n
8
IN2_HPD
9
IN2_D1p
10
IN2_D1n
11
GND 12
IN2_D2p
13
IN2_D2n
14
OUT_AUXp_SCL 28
OUT_AUXn_SDA 27
REXT 18
CEXT 17
IN2_D3n
16 IN2_D3p
15
OUT_D0p 42
OUT_D0n 41
PD 40
OUT_D1p 39
OUT_D1n 38
I2C_CTL_EN 37
OUT2_D2p 36
OUT2_D2n 35
CFG_OUTPUT 34
OUT_D3p 33
OUT_D3n 32
VDD
31
AC_AUXp 30
AC_AUXn 29
OUT_HPD 43
CA_DET 44
GND 45
SW_AUX 47
IN2_PEQ/SDA_CTL
49
IN1_PEQ/SCL_CTL
50
IN2_AEQ#
51
IN1_D0p
52
IN1_D0n
53
VDD
54
IN1_D1p
55
IN1_D1n
56
Epad 57
IN1_SDA
19 IN1_SCL
20
IN2_SDA
21 IN2_SCL
22
IN1_AUXn
23 IN1_AUXp
24
IN2_AUXn
25 IN2_AUXp
26
SW_ML/I2C_ADDR 48
CFG_HPD 46
CV1040.1U_0402_10V7K~D
1 2
LV5
BLM18BB221SN1D_2P~D
1 2
CV116
0.1U_0603_50V4Z~D
1 2
RV176 0_0402_5%~D@
1 2
RV142
4.7K_0402_1%~D
@
1 2
RV164 0_0402_5%~D@
1 2
RV146
4.7K_0402_1%~D
@
12
RV174 0_0402_5%~D@
1 2
LV3
DLW21SN670HQ2L_4P~D
1 2
34
RV150
47K_0402_5%~D
12
QV4B
DMN66D0LDW-7_SOT363-6~D
34
5
RV167 0_0402_5%~D@
1 2
RV147
4.7K_0402_1%~D
@
12
CV950.1U_0402_10V7K~D
1 2
RV156
0_0402_5%~D @
1 2
CV115
0.1U_0402_16V4Z~D
1
2
RV145
4.7K_0402_1%~D
@
12
RV169 0_0402_5%~D@
1 2
CV91 0.1U_0402_10V7K~D
1 2
RV168 0_0402_5%~D@
1 2
RV157
100K_0402_5%~D
12
QV4A
DMN66D0LDW-7_SOT363-6~D
61
2
LV6
BLM18BB221SN1D_2P~D
1 2
RV175 0_0402_5%~D
@
1 2
RV160 100K_0402_5%~D
@
1 2
CV990.1U_0402_10V7K~D
1 2
RV165 0_0402_5%~D@
1 2
JEDP1
I-PEX_20505-044E-011G~D
CONN@
MIC_DAT 7
ALS_VCC 16
GND 14
PWR_LED 5
BATT1_LED 3
CONNTST 1
BL_PW R 23
BL_PW R 25
SMBUS_CLK 18
CAM_MIC_CBL_DET# 13
BL_GND 26
BL_GND 27
GND 29
LCD_VCC 31
LCD_VCC 33
AUX_CH_N 35
LANE1_N 42
LANE0_N 39
LANE1_P 41
GND 37
GND 6
ALS_INT# 15
USB+ 12
BATT2_LED 4
GND 2
BL_PW R 22
BL_PW R 24
SMBUS_DATA 17
BL_PW M 19
BL_GND 20
BL_GND 21
HPD 28
TEST 30
LCD_VCC 32
GND 34
AUX_CH_P 36
GND 43
GND 40
LANE0_P 38
CONNTST 44
MGND1
45
MGND2
46
MGND3
47
MGND4
48
MGND5
49
MGND6
50
MGND7
51
MGND8
52
MGND9
53
MGND10
54
MGND11
55
MGND12
56
MGND13
57
MIC_GND 8
USB_VCC 10
MIC_CLK 9
USB- 11
RV154
0_0402_5%~D
1 2
CV92 0.1U_0402_10V7K~D
1 2
CV93
0.1U_0603_50V4Z~D
1
2
CV960.1U_0402_10V7K~D
1 2
CV108 0.1U_0402_16V4Z~D
12
CV1030.1U_0402_10V7K~D
1 2
CV84
0.1U_0402_16V4Z~D
1
2
CV83
10U_0805_10V4Z~D
1
2
LV8
DLW21SN670HQ2L_4P~D
1 2
34
CV112
10P_0402_50V8J~D
@
12
RV143
4.7K_0402_1%~D
@
1 2
QV10
FDS4435BZ_SO8~D
4
7
8
6
5
1
2
3
CV88
0.1U_0603_25V7K~D
1
2
CV90
0.1U_0402_16V4Z~D
1
2
RV163 1M_0402_5%~D
12
RV173 0_0402_5%~D@
1 2
CV107 0.1U_0402_16V4Z~D
12
CV89
0.1U_0402_16V4Z~D
1
2
RV141
4.7K_0402_1%~D
12
RV152
200K_0402_5%
12
CV85
0.1U_0402_16V4Z~D
1
2
CV1020.1U_0402_10V7K~D
1 2
CV980.1U_0402_10V7K~D
1 2
RV151
220K_0402_1%
<BOM Structure>
12
RV159 100K_0402_5%~D
1 2
LV1
FBMA-L11-201209-221LMA30T_0805
@
1 2
CV114
0.1U_0402_16V4Z~D
1
2
CV94
1000P_0402_50V7K~D
1
2
RV144
4.7K_0402_1%~D
@
1 2
CV87
4.7U_0805_10V4Z~D
1
2
G
D
S
QV12
SSM3K7002FU_SC70-3~D
2
1 3
LV9
DLW21SN900SQ2L_0805_4P~D
1
122
33
4
4
CV82
0.1U_0402_16V4Z~D
1
2
CV111
10P_0402_50V8J~D
@
12
DV3
IP4223CZ6_SO6~D
V I/O
1
V I/O
3
V I/O 6
V I/O 4
Ground
2V BUS 5
RV149
100_0402_5%~D
12
RV162 100K_0402_5%~D
1 2
CV110
2.2U_0402_6.3V6M~D
1
2
CV1000.1U_0402_10V7K~D
1 2
RV148
4.7K_0402_1%~D
12
CV1010.1U_0402_10V7K~D
1 2
LV4
BLM18BB221SN1D_2P~D
1 2
LV7
DLW21SN670HQ2L_4P~D
1 2
34
RV171 0_0402_5%~D
@
1 2
CV86
4.7U_0805_10V4Z~D
1
2
CV970.1U_0402_10V7K~D
1 2
LV2
DLW21SN670HQ2L_4P~D
1 2
34
RV166
10K_0402_5%~D
@
12
RV161
4.99K_0402_1%
12
RV170 0_0402_5%~D@
1 2
RV155 4.7K_0402_1%~D@
12
RV172
0_0402_5%~D@
1 2
S
G
D
QV11
FDC654P-G_SSOT-6~D
3
6
2
4 5
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PANEL_SW
PANEL_SW
+3VS
+3VS
LVDS_TXOUT2-<42>
LVDS_TXOUT0-<42>
LCDVDD_ON<33,41,42>
PANEL_SW <19,31>
LVDS_TZOUT0-<42>
LVDS_TXCLK+<42>
LVDS_TXCLK-<42>
LVDS_TXOUT2+<42>
LVDS_TZCLK-<42>
LVDS_TZOUT2+<42>
LVDS_TZOUT2-<42>
LVDS_TZOUT1+<42>
LVDS_TZOUT1-<42>
LVDS_TZOUT0+<42>
LVDS_TXOUT1+<42>
LVDS_TXOUT1-<42>
LVDS_TXOUT0+<42>
LVDS_TZCLK+<42>
LVDS_6038_TXOUT0- <37>
LVDS_6038_TXOUT0+ <37>
LVDS_6038_TXOUT1- <37>
LVDS_6038_TXOUT1+ <37>
LVDS_6038_TXCLK+ <37>
LVDS_6038_TXCLK- <37>
LVDS_6038_TXOUT2+ <37>
LVDS_6038_TXOUT2- <37>
LVDS_6038_TZOUT0+ <37>
LVDS_6038_TZOUT0- <37>
LVDS_6038_TZOUT1- <37>
LVDS_6038_TZOUT2- <37>
LVDS_6038_TZOUT1+ <37>
LVDS_6038_TZCLK- <37>
LVDS_6038_TZCLK+ <37>
LVDS_6038_TZOUT2+ <37>
EDP_TXOUT2-<38>
EDP_TXOUT0-<38>
EDP_TXCLK+<38>
EDP_TXCLK-<38>
EDP_TXOUT2+<38>
EDP_TXOUT1+<38>
EDP_TXOUT1-<38>
EDP_TXOUT0+<38>
EDP_TZOUT0-<38>
EDP_TZCLK-<38>
EDP_TZOUT2+<38>
EDP_TZOUT2-<38>
EDP_TZOUT1+<38>
EDP_TZOUT1-<38>
EDP_TZOUT0+<38>
EDP_TZCLK+<38>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
STDP6038 to EDP & LVDS MUX
Custom
31 61Friday, June 22, 2012
2012/06/22 2013/06/21
eDP PANEL
Output
STDP6038 to EDP & LVDS MUX
LVDS PANEL
Input
PANEL_SW
LVDS
H
L
Y
eDP
CV309
4.7U_0603_6.3V6K~D
1
2
CV311
0.1U_0402_16V4Z~D
1
2
UV31
PI3LVD1012BE_BQSOP80
GND1
3VDD1 4
GND2
13
GND3
20
GND4
21
GND6
38
GND7
52
GND8
74
OE2#
25
VDD2 10
VDD3 19
VDD4 22
VDD5 28
GND5
31
VDD6 37
VDD7 47
VDD8 69
0B1
2
1B1
1
0B2
80
1B2
79
2B1
78
3B1
77
2B2
76
3B2
75
4B1
73
5B1
72
4B2
71
5B2
70
6B1
68
7B1
67
6B2
66
7B2
65
8B1
64
9B1
63
8B2
62
9B2
61
SLE1 16
A0 5
A1 6
A2 8
A3 9
SEL2 34
A4 11
A5 12
A6 14
A7 15
A8 17
A9 18
A10 23
A11 24
A12 26
A13 27
A14 29
A15 30
A16 32
A17 33
A18 35
A19 36
10B1
60
11B1
59
10B2
58
11B2
57
12B1
56
13B1
55
12B2
54
13B2
53
14B1
51
15B1
50
14B2
49
15B2
48
16B1
46
17B1
45
16B2
44
17B2
43
18B1
42
19B1
41
18B2
40
19B2
39
OE1#
7
RV397
100K_0402_5%~D
12
D
G
S
QV29
SSM3K7002F_SC59-3~D
13
2
CV310
0.1U_0402_16V4Z~D
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDMI_SW
HDMI_IN_D1+
HDMI_IN_CK+
HDMI_IN_D2+
HDMI_IN_D1-
HDMI_IN_D2-
HDMI_IN_D0+
HDMI_IN_D0-
HDMI_IN_CK-
HDMI_CLK
HDMI_IN_OUT_SDATA
HDMI_IN_OUT_SCLK
HDMI_SINK_HPD_R
HDMI_IN_OUT_DDC
HDMI_IN_OUT_TXC-_R
HDMI_IN_OUT_TXD2+_R
HDMI_IN_OUT_TXC+_R
HDMI_IN_OUT_TXD0+_R
HDMI_IN_OUT_TXD1+_R
HDMI_IN_OUT_TXD0-_R
HDMI_IN_OUT_TXD1-_R
HDMI_IN_OUT_TXD2-_R
HDMI_IN_OUT_SCLK
HDMI_IN_OUT_SDATA
HDMI_IN_OUT_HPD
HDMI_IN_OUT_TXC-
HDMI_IN_OUT_TXD2+
HDMI_IN_OUT_TXC+
HDMI_IN_OUT_TXD0+
HDMI_IN_OUT_TXD1+
HDMI_UART_RX
HDMI_IN_OUT_TXD0-
HDMI_IN_OUT_TXD1-
HDMI_IN_OUT_TXD2-
HDMI_UART_TX
HDMI_IN_OUT_HPD
HDMI_IN_DET#
DVI_SCLK
DVI_SDATA
HDMI_IN_OUT_DDC
HDMI_OUT_TXD1+
HDMI_OUT_TXC+
HDMI_OUT_TXD2+
HDMI_OUT_TXD1-
HDMI_OUT_TXD2-
HDMI_OUT_TXD0+
HDMI_OUT_TXD0-
HDMI_OUT_TXC-
HDMI_IN_HPD_R
HDMI_IN_OUT_TXD1-_R
HDMI_IN_OUT_TXD0+_R
HDMI_IN_OUT_TXD2-_R
HDMI_IN_OUT_TXD1+_R
HDMI_IN_OUT_TXC-_R
HDMI_IN_OUT_TXD0+
HDMI_IN_OUT_TXD0-
HDMI_IN_OUT_TXC-
HDMI_IN_OUT_TXC+
HDMI_IN_OUT_TXD1-
HDMI_IN_OUT_TXD2+
HDMI_IN_OUT_TXD2-
HDMI_IN_OUT_TXD1+
HDMI_IN_OUT_TXD2+_R
HDMI_IN_OUT_TXD0-_R
HDMI_IN_OUT_TXC+_R
HDMI_DAT
HDMI_SW
HDMI_IN_OUT_TXD1-
HDMI_IN_OUT_TXD1+
HDMI_IN_OUT_TXD0+
HDMI_IN_OUT_TXD2-
HDMI_IN_OUT_TXD2+
HDMI_IN_OUT_TXD0-
HDMI_IN_OUT_TXC-
HDMI_IN_OUT_TXC+
PCH_PW R_EN
HDMI_IN_OUT_DDC
HDMI_IN_OUT_HPD
+5VALW
+HDMI_5V_OUT
+5VS
+HDMI_5V_OUT
+1.5VS
+3.3VS
+5VS
+5VS
+1.5VS
DVI_SDATA <36>
DVI_SCLK <36>
HDMI_IN_CK- <37>
HDMI_IN_CK+ <37>
HDMI_IN_D0- <37>
HDMI_IN_D0+ <37>
HDMI_IN_D1- <37>
HDMI_IN_D1+ <37>
HDMI_IN_D2- <37>
HDMI_IN_D2+ <37>
HDMI_OUT_EN<43>
HDMI_DAT <37>
HDMI_CLK <37>
HDMI_IN_HPD_R <37>
HDMI_IN_DET# <37>
HDMI_SINK_HPD_R <36>
UART_TX_6038<37>
UART_RX_6038<37>
HDMI_SW<43>
HDMI_OUT_TXD0+ <36>
HDMI_OUT_TXD2- <36>
HDMI_OUT_TXD1- <36>
HDMI_OUT_TXD2+ <36>
HDMI_OUT_TXC- <36>
HDMI_OUT_TXC+ <36>
HDMI_OUT_TXD0- <36>
HDMI_OUT_TXD1+ <36>
PCH_PW R_EN<43,56>
HDMI_IN_OUT_HPD<43>
HDMI_IN_OUT_DDC<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
HDMI In/Out SW/Connector
Custom
32 61Friday, June 22, 2012
2012/06/22 2013/06/21
STDP6038
SEL OUTPUT
A
B
L
H
SEL OUTPUT
B1
B2
L
H
HDMI Input/Output Connector
CPU/MXM
Reserve for EMI please close to JHDMI2
Compal Electronics, Inc.
HDMI CONN
20120531 EMI ADD
RV182 0_0402_5%~D@
1 2
G
D
S
QV14
SSM3K7002FU_SC70-3~D
2
13
CV356 3.3P_0402_50V8C~D
1 2
CV121
0.1U_0402_16V4Z~D
1
2
CV354 3.3P_0402_50V8C~D
1 2
CV353 3.3P_0402_50V8C~D
1 2
RV177
102K_0402_1%
1 2
RV119
100K_0402_5%~D
12
CV123
0.1U_0402_16V4Z~D
1
2
RV186 0_0402_5%~D@
1 2
LV13
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
RV178
0_0402_5%~D
RV180 0_0402_5%~D@
1 2
RV120
4.7K_0402_5%~D
1 2
CV349 3.3P_0402_50V8C~D
1 2
S
G
D
QV13
SI3456DDV-T1-GE3_TSOP6~D
3
6
2
45
1
RV187 0_0402_5%~D@
1 2
RV181 0_0402_5%~D@
1 2
CV125
0.1U_0402_16V4Z~D
1
2
RV185 0_0402_5%~D
1 2
CV124
10U_1206_16V4Z
1
2
CV351 3.3P_0402_50V8C~D
1 2
RV184 0_0402_5%~D
1 2
CV120
10U_1206_16V4Z
1
2
RV189 0_0402_5%~D@
1 2
RV183 0_0402_5%~D@
1 2
CV350 3.3P_0402_50V8C~D
1 2
Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
ROYALTY HDMI W/LOGO46@
RV188 0_0402_5%~D@
1 2
JHDMI1
SUYIN_100042GR019M23UZL
CONN@
D2+
1D2_shield
2D2-
3D1+
4D1_shield
5D1-
6D0+
7D0_shield
8D0-
9CK+
10 CK_shield
11 CK-
12 CEC
13 Reserved
14 SCL
15 SDA
16 DDC/CEC_GND
17 +5V
18 HP_DET
19
GND 20
GND 21
GND 22
GND 23
LV11
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
CV118
1U_0402_6.3V6K~D
1
2
CV127
0.1U_0402_16V4Z~D
1
2
CV355 3.3P_0402_50V8C~D
1 2
RV179
0_0402_5%~D
@
CV117
10U_0603_6.3V6M~D
1
2
CV122
0.1U_0603_50V7K~D
1
2
LV12
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
UV11
TS3DV421RUAR_WQFN42_9X3P5
SEL
9
TMDS2+
3TMDS2-
4TMDS1+
6TMDS1-
7TMDS0+
11 TMDS0-
12 TMDSCLK+
14 TMDSCLK-
15
VDD
2VDD
8VDD
16 VDD
18 VDD
20 VDD
30 VDD
40 VDD
42
VSS 1
VSS 5
VSS 10
VSS 13
VSS 17
VSS 19
VSS 21
VSS 41
VSS 39
ATMDSCLK- 31
ATMDSCLK+ 32
ATMDS0- 33
ATMDS0+ 34
ATMDS1- 35
ATMDS1+ 36
ATMDS2- 37
ATMDS2+ 38
BTMDSCLK- 22
BTMDSCLK+ 23
BMTDS0- 24
BTMDS0+ 25
BTMDS1- 26
BMTDS1+ 27
BTMDS2- 28
BTMDS2+ 29
GND_PAD
43
CV126
0.1U_0402_16V4Z~D
1
2
LV14
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
UV12
SN74CBT3257CPW R_TSSOP16~D
S
1
1B1 2
1B2 3
2B1 5
2B2 6
1A
4
2A
7
GND
8
3A
9
3B2 10
3B1 11
4A
12
4B2 13
4B1 14
OE#
15
Vcc 16
CV119
0.1U_0402_16V4Z~D
1
2
CV352 3.3P_0402_50V8C~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI_PC1
HDMI_SW_SDA
HDMI_SW_SCL
HDMI_CFG1
HDMI_CFG0
HDMI_PC1
HDMI_PC0
HDMI_PC2
CPU_HDMI_P0_C
CPU_HDMI_N0_C
CPU_HDMI_N1_C
CPU_HDMI_P1_C
CPU_HDMI_P2_C
CPU_HDMI_N2_C
CPU_HDMI_P3_C
CPU_HDMI_N3_C
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N1
CPU_HDMI_N0
CPU_HDMI_N3
CPU_HDMI_P1
CPU_HDMI_P0
CPU_HDMI_P3
HDMI_CFG_HPD
HDMI_OE#
DGPU_SELECT# DGPU_SEL#
DGPU_EDIDSEL#_R
DGPU_SEL#
+HDMI_5V
HDMI_CFG0
HDMI_SINK_HPD_R
HDMI_PC0
DVI_SDATA_R
DVI_SCLK_R DVI_SCLK
DVI_SDATA
HDMI_CFG0
HDMI_CFG1
HDMI_PC2
HDMI_PC1
HDMI_PC0
DGPU_EDIDSEL#
HDMI_DDCBUF
DGPU_EDIDSEL#_R
PCH_DPB_HDMI_DAT
PCH_DPB_HDMI_CLK
GPU_HDMI_SCLK
GPU_HDMI_SDATA
HDMI_CFG1
HDMI_DDCBUF
GPU_HDMI_TXC-_C
GPU_HDMI_TXD1+_C
GPU_HDMI_TXD2-_C
GPU_HDMI_TXD0+_C
GPU_HDMI_TXD1-_C
GPU_HDMI_TXD2-
GPU_HDMI_TXD2+
GPU_HDMI_TXD1-
GPU_HDMI_TXD1+
GPU_HDMI_TXD0-
GPU_HDMI_TXD0+
GPU_HDMI_TXC-
GPU_HDMI_TXC+ GPU_HDMI_TXC+_C
GPU_HDMI_TXD0-_C
GPU_HDMI_TXD2+_C
HDMI_SINK_HPD
HDMI_SW _SCL
HDMI_SW _SDA
HDMI_SW _DETECT
HDMI_TXD1+
HDMI_TXD2-
HDMI_TXD0+
HDMI_TXD0-
HDMI_TXC-
HDMI_TXD1-
HDMI_TXC+
HDMI_TXD2+
HDMI_SW _DETECT
HDMI_SINK_HPD
DGPU_SEL#
HDMI_PC2
DVI_SCLK_R
DVI_SDATA_R
HDMI_OUT_TXD0-
HDMI_OUT_TXC-
HDMI_OUT_TXD1-
HDMI_OUT_TXC+
HDMI_OUT_TXD2+
HDMI_OUT_TXD1+
HDMI_OUT_TXD2-
HDMI_OUT_TXD0+
HDMI_IN1_PEQ
HDMI_IN2_PEQ
HDMI_OE#
PCH_DPB_HDMI_CLK
PCH_DPB_HDMI_DAT
GPU_HDMI_SCLK
GPU_HDMI_SDATA
HDMI_SW _SCL
HDMI_SW _SDA
HDMI_TXD0-
HDMI_TXC-
HDMI_TXD1-
HDMI_TXC+
HDMI_TXD2+
HDMI_TXD1+
HDMI_TXD2-
HDMI_TXD0+
DGPU_HPD_INT#
HDMI_IN2_PEQ
HDMI_CFG_HPD
HDMI_IN1_PEQ
HDMI_DDCBUF
HDMI_PWDN
HDMI_PWDN
PCH_GPIO35
+3VS
+3V_MXM
+3VS
+5VS +HDMI_5V_OUT
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+HDMI_5V_OUT
+HDMI_5V_OUT
+3VS
+5VS
HDMI_OUT_TXD0- <35>
HDMI_OUT_TXD2- <35>
HDMI_OUT_TXD1+ <35>
HDMI_OUT_TXC+ <35>
HDMI_OUT_TXD2+ <35>
HDMI_OUT_TXD0+ <35>
HDMI_OUT_TXD1- <35>
HDMI_OUT_TXC- <35>
HDMI_SINK_HPD_R<35>
DVI_SCLK <35>
PCH_DPB_HDMI_CLK<17>
PCH_DPB_HDMI_DAT<17>
GPU_HDMI_SCLK<29>
GPU_HDMI_SDATA<29>
VGA_HDMI_DET<29>
PCH_HDMI_HPD<17>
DGPU_EDIDSEL#_R <39>
DGPU_EDIDSEL#<21,32,42>
PCH_GPIO35<21>
GPU_HDMI_TXD0-<29>
GPU_HDMI_TXD0+<29>
GPU_HDMI_TXC-<29>
GPU_HDMI_TXD2-<29>
GPU_HDMI_TXD2+<29>
GPU_HDMI_TXD1-<29>
GPU_HDMI_TXD1+<29>
GPU_HDMI_TXC+<29>
CPU_HDMI_P0<8>
DVI_SDATA <35>
CPU_HDMI_N3<8>
CPU_HDMI_P3<8>
CPU_HDMI_N2<8>
CPU_HDMI_P2<8>
CPU_HDMI_N1<8>
CPU_HDMI_P1<8>
CPU_HDMI_N0<8>
DGPU_SEL# <39>
DGPU_SELECT#<17,32,42>
DGPU_HPD_INT#<21,39>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
HDMI SW-CPU & MXM/Re-driver
Custom
33 61Friday, June 22, 2012
2012/06/22 2013/06/21
Place LC Filter
closed to JHDMI
Close to U3 VCC pins
MXM
CPU
Close to UV2 VCC pins
W=40mils
IN2IN1
0
Y
1HDMI_SW_DET
MXM PCH
8/25 change RV53
from 430 to
499ohm
PS8271
PEQ=L, Middle level receiving equalization selection
PEQ=H, High level receiving equalization selection
PEQ=M, Low level receiving equalization selection
PS121
When DDCBUF_EN# is HIGH, the DDC channel is disabled,
SCL/SDA and SCLZ/SDAZ are disconnected
Compal Electronics, Inc.
CONN
PS121 CFG0/ CFG1
SCLZ/SDAZ output voltage select;
CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB
RV190
100K_0402_5%~D
12
RV195 4.7K_0402_5%~D@
1 2
UV14
PS8271QFN48GTR-A1_QFN48_7X7
IN1_D3p
2
VDD 6
RTERM 7
IN2_D1n
8
IN2_D1p
9
IN2_HPD
10
IN2_D2p
12
IN1_D4p
5
IN1_D3n
1
GND
18
REXT
24
OUT_D4n 27
VDD 31
OUT_D1n 36
OUT_SDA 37
GND
43
IN2_D2n
11
IN2_PEQ
15
SW_MAIN
21
OUT_D4p 26
OUT_D2n 33
DDCBUF 40
IN1_HPD
46
IN1_D4n
4
IN1_PEQ
3
IN2_D3n
13
IN2_D3p
14
IN2_D4n
16
IN2_D4p
17
IN2_SCL
19
IN1_D2p
48 IN1_D2n
47 IN1_D1p
45 IN1_D1n
44
IN1_SDA
42 IN1_SCL
41
OUT_SCL 38
PWDN_ASQ 25
CFG_HPD 28
OUT_D3p 29
OUT_D3n 30
OUT_D2p 32
IN2_SDA
20
SW_DDC
22
CEXT
23
OUT_HPD 39
PRE_EMI 34
OUT_D1p 35
PAD
49
CV128
0.01U_0402_16V7K~D
1
2
RV2154.7K_0402_5%~D @
12
RV224
1.5K_0402_5%
12
RV225 0_0402_5%~D
1 2
DV4
BAV99-7-F_SOT23-3
@
2
3
1
CV133
.1U_0402_16V7K~D
1
2
RV2132.2K_0402_5%~D
12
CV149 .1U_0402_16V7K~D
1 2
RV2084.7K_0402_5%~D @
12
RV218
499_0402_1%~D
12
CV154
0.01U_0402_16V7K~D
12
RV202 4.7K_0402_5%~D
1 2
RV201 4.7K_0402_5%~D
1 2
E
B
C
QV15
MMST3904-7-F_SOT323-3~D
@
2
3 1
CV135
10U_0603_6.3V6M~D
1
2
RV399
4.7K_0402_5%~D
@
1 2
D
G
S
QV16
SSM3K7002F_SC59-3~D
1 3
2
CV148 .1U_0402_16V7K~D
1 2
CV159
0.01U_0402_16V7K~D
12
CV138 .1U_0402_16V7K~D
12
CV131
0.01U_0402_16V7K~D
1
2
RV2202.2K_0402_5%~D
12
UV13
PS121QFN48G_QFN48_7X7
VCC4 33
OUT1p 23
OUT1n 22
OUT2p 20
OUT2n 19
OUT3p 17
OUT3n 16
OUT4p 14
OUT4n 13
VCC5 40
VCC6 46
IN1p
38
IN1n
39
IN2p
41
IN2n
42
IN3p
44
IN3n
45
IN4p
47
IN4n
48
POW
2
I2C_ADDR0/PC0
3
I2C_ADDR1/PC1
4
SDA
8
SCL
9
GND/PC2
1
REXT
6
CEXT
10
HPD 7
HPD_SINK
30
GND7
36
VCC1 11
GND4
24
GND6
31 GND5
27 VCC2 15
GND3
18
VCC3 21
GND1
5
GND2
12
GND8
37
GND9
43
SDA_CTL/CFG1
34
SCL_CTL/CFG0
35
NC/DDCBUF_EN#
32
NC/OE#
25
I2C_CTL_EN#
26
SDAZ 29
SCLZ 28
GND10
49
RV226 0_0402_5%~D
1 2
RV2142.2K_0402_5%~D
12
RV192 4.7K_0402_5%~D@
1 2
DV6
DAN217T146_SC59-3
@
2
3
1
RV2094.7K_0402_5%~D
12
CV136 .1U_0402_16V7K~D
12
RV2290_0402_5%~D
@
12
RV2224.7K_0402_5%~D @
12
RV2214.7K_0402_5%~D @
12
CV137 .1U_0402_16V7K~D
12
CV139 .1U_0402_16V7K~D
12
RV2102.2K_0402_5%~D
12
RV200
10K_0402_5%~D
@
1 2
RV203 4.7K_0402_5%~D
1 2
CV134
.1U_0402_16V7K~D
1
2
RV196 0_0402_5%~D
1 2
CV143 .1U_0402_16V7K~D
12
RV2124.7K_0402_5%~D
12
CV140 .1U_0402_16V7K~D
12
RV2162.2K_0402_5%~D
12
LV15
MBK1608221YZF_2P
1 2
RV2114.7K_0402_5%~D @
12
CV151 .1U_0402_16V7K~D
1 2
CV142 .1U_0402_16V7K~D
12
RV2270_0402_5%~D
@
12
CV158
1U_0603_10V6K~D
@
1
2
UV15
SN74AHC1G08DCKR_SC70-5
IN1
1
IN2
2
G
3
O4
P5
CV153
2.2U_0603_10V7K~D
1
2
CV129
0.1U_0402_16V4Z~D
1
2
CV146 .1U_0402_16V7K~D
1 2
CV130
0.1U_0402_16V4Z~D
1
2
CV156
10P_0402_50V8J~D
@
1
2
RV204
4.7K_0402_5%~D
@
1 2
RV191 4.7K_0402_5%~D
1 2
NC
DV7
BAT1000-7-F_SOT23-3~D
2 1
3
CV132
220P_0402_50V7K~D
1
2
D
G
S
QV17
SSM3K7002F_SC59-3~D
1
3
2
UV16
SN74AHC1G08DCKR_SC70-5
IN1
1
IN2
2
G
3
O4
P5
RV2280_1206_5%~D
@
12
CV147 .1U_0402_16V7K~D
1 2
RV2174.7K_0402_5%~D @
12
RV193
200K_0402_5%
@
1 2
RV401 4.7K_0402_5%~D@
1 2
RV197 4.7K_0402_5%~D
1 2
RV2194.7K_0402_5%~D @
12
CV141 .1U_0402_16V7K~D
12
RV2072.2K_0402_5%~D
12
RV205499_0402_1%~D
12
CV155
10P_0402_50V8J~D
@
1
2
RV199 4.7K_0402_5%~D
1 2
RV223
1.5K_0402_5%
12
CV152 .1U_0402_16V7K~D
1 2
RV2064.7K_0402_5%~D @
12
CV150 .1U_0402_16V7K~D
1 2
RV402 4.7K_0402_5%~D@
1 2
RV198
200K_0402_5%
1 2
CV157
1U_0603_10V4Z~D
1
2
CV1442.2U_0402_6.3V6M~D
12
DV5
DAN217T146_SC59-3
@
2
3
1
RV194 4.7K_0402_5%~D@
1 2
CV145 .1U_0402_16V7K~D
1 2
FV5
5A_125V_R451005.MRL~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART_RX_6038
HDMI_IN_AUD_CODEC
HDMI_IN_CK+
HDMI_IN_D1+
HDMI_IN_D0-
HDMI_IN_CK-
HDMI_IN_D2-
HDMI_IN_D1-
HDMI_IN_D0+
HDMI_IN_D2+
HDMI_PLUG_IN_CAB_DET
EDID_W P
DHMI_IN_NV_CLK_R
DHMI_IN_NV_DAT_R
EC_HDMI_CLK
TCLK
HDMI_SPI_CS# HDMI_SPI_CS#_R
BS_XTAL_TCLK_SEL
XTAL
+3.3V_DVDD
LVDS_6038_TZOUT1-
LVDS_6038_TZOUT1+
LVDS_6038_TZOUT0+
LVDS_6038_TZOUT0-
LVDS_6038_TZCLK+
LVDS_6038_TZCLK-
LVDS_6038_TZOUT2-
LVDS_6038_TZOUT2+
BS_XTAL_TCLK_SEL
HDMI_IN_CK+_R
HDMI_IN_CAB_DET#
BS_RESERVED_R
BS_OCM_BOOT_SEL
UART_RX_6038
TCLK
HDMI_IN_HPDHDMI_IN_HPD
HDMI_SPI_CLK_R
HDMI_IN_BKL_EN
HDMI_IN_D0-_R
+5VS_HDMI_IN_EDID
BS_INTERFACE_SEL1
BS_INTERFACE_SEL0
BS_UART_FUNCTION_SEL
BS_I2C_SRC_R
HDMI_SPI_SI
HDMI_SPI_CLK
HDMI_SPI_CS#
HDMI_SPI_SO
HDMI_IN_D0+_R
HDMI_IN_SW _HPD
HDMI_SPI_SO
HDMI_IN_D1-_R
HDMI_IN_PWM
HDMI_IN_CAB_DET#
HDMI_PLUG_IN_CAB_DET
BS_OSC_SEL
DHMI_IN_NV_CLK_R
DHMI_IN_NV_DAT_R
HDMI_IN_D1+_R
HDMI_SPI_SO_R
BS_EXTKEY_EN
UART_TX_6038
HDMI_IN_D2+_R
EC_HDMI_CLK
EC_HDMI_DAT
HDMI_IN_AUD_CODEC
HDMI_SW _DAT
HDMI_SW _CLK
EC_HDMI_DAT
HDMI_IN_ENVDD
HDMI_IN_CK-_R
BS_SPI_R
HDMI_IN_DET#
BS_INTERFACE_SEL0
HDMI_IN_HPD_R
HDMI_IN_HPD
BS_I2C_DEV_ID0
BS_SPI_R
BS_UART_FUNCTION_SEL
BS_I2C_SRC_R
BS_RESERVED_R
BS_EXTKEY_EN
BS_I2C_ON_R
BS_I2C_DEV_ID2
BS_I2C_DEV_ID1
HDMI_IN_SW _HPD
BS_OCM_BOOT_SEL
HDMI_SPI_CLKHDMI_SPI_CLK_R
HDMI_SW _DAT
HDMI_IN_D2-_R
HDMI_RST#
HDMI_SPI_SI_R HDMI_SPI_SI
BS_INTERFACE_SEL1
XTAL
LVDS_6038_TXOUT1-
LVDS_6038_TXOUT1+
LVDS_6038_TXOUT0-
LVDS_6038_TXOUT0+
LVDS_6038_TXCLK+
LVDS_6038_TXCLK-
LVDS_6038_TXOUT2-
LVDS_6038_TXOUT2+
HDMI_SW _CLK
BS_I2C_DEV_ID0
BS_I2C_DEV_ID1
BS_I2C_DEV_ID2
HDMI_CLK
HDMI_DAT
EDID_W P
BS_I2C_ON_R
BS_OSC_SEL
DHMI_IN_NV_CLK
DHMI_IN_NV_DAT
HDMI_IN_EN
+3.3V_DVDD
+3.3V_DVDD
+5VS
+3.3V_DVDD
+HDMI_5V_OUT
+3.3V_DVDD
+HDMI_5V_OUT
+HDMI_5V_OUT
+3.3VS_AVDD
+5VS+3VS
+1.2V_AVDD
+1.2V_DVDD
+1.2V_AVDD
+3.3V_DVDD
+3.3VS_AVDD
+3.3V_DVDD
+3.3V_AVDD_LVTX
+3.3V_AVDD_RPLL
+3.3V_AVDD_RPLL
+3.3VS_AVDD+3VS
+3.3V_AVDD_LVTX
+3.3V_AVDD_RPLL
+1.2VS_HDMI +1.2V_AVDD
+1.2VS_HDMI +1.2V_DVDD
+3.3VS_AVDD
+3VS +3.3V_DVDD
+HDMI_5V_OUT
+5VS
+1.2VS_A+1.2VS
+3.3VS_AVDD
+1.2VS_HDMI
+3.3V_DVDD
+3.3V_DVDD
+3.3V_DVDD
UART_RX_6038 <35>
HDMI_IN_CAB_DET# <43>
HDMI_TOGGLE <43>
HDMI_CLK <35>
LVDS_6038_TXOUT0+ <34>
HDMI_DAT <35>
LVDS_6038_TXOUT2+ <34>
LVDS_6038_TXOUT0- <34>
LVDS_6038_TZOUT0+ <34>
LVDS_6038_TZOUT2+ <34>
LVDS_6038_TZOUT0- <34>
LVDS_6038_TZOUT1- <34>
LVDS_6038_TZOUT1+ <34>
LVDS_6038_TZOUT2- <34>
LVDS_6038_TZCLK+ <34>
LVDS_6038_TZCLK- <34>
LVDS_6038_TXOUT1- <34>
LVDS_6038_TXOUT1+ <34>
LVDS_6038_TXOUT2- <34>
I2S_DAT/SPDIF_IN<45>
HDMI_IN_AUDIO_CODEC <45>
LVDS_6038_TXCLK+ <34>
LVDS_6038_TXCLK- <34>
HDMI_IN_DET# <35>
HDMI_IN_HPD_R <35>
HDMI_IN_PWM <42>
HDMI_IN_BKL_EN <42>
HDMI_IN_ENVDD <42>
HDMI_IN_D0-<35>
HDMI_IN_CK-<35>
HDMI_IN_D1-<35>
HDMI_IN_D2-<35>
HDMI_IN_D1+<35>
HDMI_IN_D2+<35>
HDMI_IN_CK+<35>
HDMI_IN_D0+<35>
EC_SMB_CK2_R<43> EC_HDMI_CLK <38>
EC_HDMI_DAT <38>EC_SMB_DA2_R<43>
UART_TX_6038 <35>
DHMI_IN_NV_CLK <42>
DHMI_IN_NV_DAT <42>
HDMI_IN_EN<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
HDMI to LVDS-STDP6038
Custom
34 61Friday, June 22, 2012
2012/06/22 2013/06/21
Close to respective power Pins
NVRAM
HDMI
LVDS
1.2V
TDC 0.52A
Peak Current 0.73A
OCP current 3.5A
AVDD_RPLL pin10 C610 0.1uF
to AVSS_RPLL pin7
Can not place large capacitor to
prevent pulse happened when LVDS
power switch off/on
For 4028
2Kbit
16KBit
2Mbit
SPI ROM
2KBit
Compal Electronics, Inc.
RV232 10K_0402_5%~D
1 2
RV278 10_0402_5%~D
1 2
RV252
15_0402_5%~D
12
CV203 0.1U_0402_16V4Z~D
1 2
LV20
BLM18AG601SN1D_0603~D
12
LV19
BLM18AG601SN1D_0603~D
12
UV17
RT9025-25PSP_SO8
NC 5
VIN
3
VDD
4
EN
2
PGOOD
1
VOUT 6
ADJ 7
GND 8
GND 9
CV192
10P_0402_50V8J~D
1
2
RV279 10_0402_5%~D
1 2
CV164
0.1U_0402_16V4Z~D
1
2
RV255 10K_0402_5%~D
1 2
T60PAD~D @
RV249 10K_0402_5%~D
1 2
CV174
1U_0402_6.3V6K~D
1
2
CV160
22U_0805_6.3VAM~D
1
2
UV19
CAT24C16WI-GT3_SO8
E0
1
E1
2
SDA 5
SCL 6
VCC 8
E2
3
VSS
4
WC 7
CV187
0.1U_0603_25V7K~D
1
2
CV188
0.1U_0603_25V7K~D
1
2
RV261
2.2K_0402_5%~D
1 2
CV179
0.1U_0603_25V7K~D
1
2
RV266
4.7K_0402_1%~D
12
DV10
BAV99-7-F_SOT23-3
@
2
3
1
RV245 10K_0402_5%~D
1 2
LV22
BLM18AG601SN1D_0603~D
1 2
RV272 100_0402_1%~D
1 2
CV189
0.1U_0603_25V7K~D
1
2
RV297 0_0402_5%~D
1 2
RV233 10K_0402_5%~D
1 2
CV177
22U_0805_6.3VAM~D
1
2
E
B
C
QV18
MMST3904-7-F_SOT323-3~D
2
3 1
LV21
BLM18BD601SN1D_0603~D
1 2
RV238 10K_0402_5%~D
1 2
RV239 10K_0402_5%~D
1 2
RV396 0_0402_5%~D
1 2
LV18
BLM18BD601SN1D_0603~D
1 2
CV168
0.1U_0603_25V7K~D
1
2
RV290 10K_0402_5%~D
12
RV274 0_0402_5%~D
1 2
UV20
CAT24C02WI-GT3A_SO8
E0
1
E1
2
SDA 5
SCL 6
VCC 8
E2
3
VSS
4
WC 7
RV298 0_0402_5%~D
1 2
RV284 10_0402_5%~D
1 2
CV180
0.1U_0603_25V7K~D
1
2
CV197
4700P_0402_25V7K~D
1
2
CV161
0.1U_0603_25V7K~D
1
2
RV269 22_0402_5%
1 2
RV267
4.7K_0402_1%~D
12
CV166
0.1U_0603_25V7K~D
1
2
T58PAD~D @
CV191
.1U_0402_16V7K~D
1
2
RV264 10K_0402_5%~D
1 2
CV200 0.1U_0402_16V4Z~D
1 2
CV190
15P_0402_50V8J~D
@
1
2
CV186
0.1U_0603_25V7K~D
1
2
CV167
0.1U_0603_25V7K~D
1
2
RV276 300_0402_1%
1 2
CV175
.1U_0402_16V7K~D
12
CV195 0.1U_0402_16V4Z~D
1 2
RV241
20K_0402_5%~D
12
RV283
1K_0402_1%~D
1 2
RV243 10K_0402_5%~D
1 2
CV163
0.1U_0603_25V7K~D
1
2
CV182
0.1U_0603_25V7K~D
1
2
CV194
0.1U_0402_16V4Z~D
1
2
CV162
0.1U_0603_25V7K~D
1
2
RV270 0_0402_5%~D
1 2
RV251 22_0402_5%
1 2
UV18
MX25L2006EM1I-12G_SOP8
S#
1
W#
3
VSS
4
Q
2
D5
C6
VCC 8
RESET# 7
RV282
4.7K_0402_5%~D
1 2
CV207
0.1U_0402_16V4Z~D
1
2
RV395 0_0402_5%~D
1 2
CV202 0.1U_0402_16V4Z~D
1 2
RV248 10K_0402_5%~D
1 2
CV173
22U_0805_6.3VAM~D
1
2
CV183
22U_0805_6.3VAM~D
1
2
RV25410K_0402_5%~D
12
G1 G2
YV1
27MHZ_10PF_X3S027000BA1H-U~D
1
2
3
4
RV409
4.7K_0402_5%~D
12
CV165
22U_0805_6.3VAM~D
1
2
RV242 10K_0402_5%~D
1 2
RV296 0_0402_5%~D
1 2
RV26822_0402_5%
1 2
RV231 100K_0402_5%~D
1 2
LV23
BLM18BD601SN1D_0603~D
1 2
RV29422_0402_5%
1 2
LV16
BLM18BD601SN1D_0603~D
1 2
CV176
10U_0805_4VAM~D
1
2
RV244
15_0402_5%~D
@
12
RV281 10_0402_5%~D
1 2
UV1
STDP6038-AC_PQFP128_20X14~D
GPO_2 / TTL_D7 / PW M2(BS_OCM_BOOT_SEL) 1
PPOWER / TTL_D8 / GPO_3 2
PBIAS / TTL_D9 / GPO_4 3
RESETn
4
VBUFC_RPLL 5
VDDA_1V2 6
VSSA_33 7
TCLK
9XTAL
8
AVDD_OUT_33
11
E_CH3P_LV / TTL_D10 / GPIO_48 12
E_CH3N_LV / TTL_D11 / GPIO_49 13
E_CLKP_LV / TTL_D12 / GPIO_50 14
E_CLKN_LV / TTL_D13 / GPIO_51 15
E_CH2P_LV / TTL_D14 / GPIO_52 16
E_CH2N_LV / TTL_D15 / GPIO_53 17
E_CH1P_LV / TTL_D16 / GPIO_54 18
E_CH1N_LV / TTL_D17 / GPIO_55 19
E_CH0P_LV / TTL_D18 / GPIO_56 20
E_CH0N_LV / TTL_D19 / GPIO_57 21
LVVSS 22
AVDD_OUT_33
23
O_CH3P_LV / TTL_D20 / GPIO_58 24
O_CH3N_LV / TTL_D21 / GPIO_59 25
O_CLKP_LV / TTL_D22 / GPIO_60 26
O_CLKN_LV / TTL_D23 / GPIO_61 27
O_CH2P_LV / TTL_D24 / GPIO_62 28
O_CH2N_LV / TTL_D25 / GPIO_63 29
O_CH1P_LV / TTL_D26 / GPIO_64 30
O_CH1N_LV / TTL_D27 / GPIO_65 31
O_CH0P_LV / TTL_D28 / GPIO_66 32
O_CH0N_LV / TTL_D29 / GPIO_67 33
LVVSS 34
CVDD_12 35
CRVSS 37
NC
36
RVDD_33
38
I2S_0 (S/PDIF) / GPO_12(BS_RESERVED)
39
I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL)
40
I2S_W S / GPO_14(BS_I2C_SRC_SEL)
41
I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN)
42
DPRX_HPD_OUT / GPO_5
43
D2_I2C_SDA / GPIO_24
44
D2_I2C_SCL / GPIO_25
45
CVDD_12 46
DPRX_VSSD
47
DPRX_AUXN
48
DPRX_AUXP
49
DPRX_VDDD_1V2 50
DPRX_REXT
51
DPRX_VDDA_1V2 52
DPRX_ML_L0P
53
DPRX_ML_L0N
54
DPRX_VSSA
55
DPRX_ML_L1P
56
DPRX_ML_L1N
57
DPRX_VDDA_1V2 58
DPRX_ML_L2P
59
DPRX_ML_L2N
60
DPRX_VSSA
61
DPRX_ML_L3P
62
DPRX_ML_L3N
63
DPRX_VDDA_1V2 64
SPI_CSn / IRQ_IN / GPO_8
65
SPI_CLK / GPO_9(BS_INTERFACE_SEL1)
66
SPI_DI / GPO_10(BS_INTERFACE_SEL0)
67
SPI_DO / GPO_11(BS_UART_FUNCTION_SEL)
68
CRVSS 69
VEDID_VDD_3V3
70
A_I2C_SDA
71
A_I2C_SCL
72
D1_I2C_SDA / GPIO_28
73
D1_I2C_SCL / GPIO_29
74
HDMI_RXCN
75
HDMI_RXCP
76
HDMI_VSSA
77
HDMI_RX0N
78
HDMI_RX0P
79
HDMI_VDDA_3V3
80
HDMI_RX1N
81
HDMI_RX1P
82
HDMI_VSSA
83
HDMI_RX2N
84
HDMI_RX2P
85
HDMI_VDDA_3V3
86
HDMI_REXT
87
ADC_DVDD_1V2 88
ADC_VSSD 89
ADC_AVDD_3V3
90
ADC_VSSA 91
ADC_A_N
92
ADC_A_P
93
ADC_VSSA 94
ADC_B_N
95
ADC_B_P
96
ADC_VSSA 97
ADC_C_N
98
ADC_C_P
99
ADC_AVDD_3V3
100
LBADC_IN1 / GPIO_32 / TTL_SYNC3 102
LBADC_IN2 / GPIO_33 / TTL_SYNC4 101
LBADC_IN3 / GPIO_34 104
LBADC_IN4 / GPIO_35 103
HSYNC_IN
105
VSYNC_IN
106
CVDD_12 108
CRVSS 107
RVDD_33
109
GPIO_45 110
GPIO_44 / S_I2C_SCL
111
GPIO_43 / S_I2C_SDA
112
HDMI_HPD / GPIO_22
113
HDMI_CEC / GPIO_23
114
CRVSS 115
CVDD_12 116
UART_RX / TTL_SYNC2 / GPO_6 117
UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) 118
TTL_CKOUT / GPIO16(BS_EXTKEY_EN) 119
TTL_D0 / GPIO17 / M_I2C_SDA 120
TTL_D1 / GPIO18 / M_I2C_SCL 121
TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) 122
TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) 123
TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) 124
STI_TM2
125
GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) 126
STI_TM1 / PWM1 / TTL_D6 / GPO_1 127
RVDD_33
128
VDDA_3V3
10
CV208
220P_0402_50V7K~D
1
2
G
D
S
QV19
SSM3K7002FU_SC70-3~D
2
13
RV289 10_0402_5%~D
1 2
RV295 0_0402_5%~D
1 2
RV293 0_0402_5%~D@
1 2
RV235 10K_0402_5%~D
1 2
RV286 10_0402_5%~D
1 2
CV199 0.1U_0402_16V4Z~D
1 2
RV260
4.7K_0402_1%~D
12
RV237 10K_0402_5%~D
1 2
RV258
4.7K_0402_1%~D
@
12
CV198 0.1U_0402_16V4Z~D
1 2
RV410
4.7K_0402_5%~D@
12
RV280 10_0402_5%~D
1 2
CV172
0.1U_0603_25V7K~D
1
2
CV171
0.1U_0603_25V7K~D
1
2
RV271 100_0402_1%~D
1 2
RV259
4.7K_0402_1%~D
12
RV262 22_0402_5%
1 2
RV285
100K_0402_5%~D
12
RV265
4.7K_0402_1%~D
12
RV230 10K_0402_5%~D
1 2
CV184
0.1U_0603_25V7K~D
1
2
RV292 10K_0402_5%~D
12
CV170
0.1U_0603_25V7K~D
1
2
RV253 15_0402_5%~D
1 2
RV25715_0402_5%~D
1 2
CV169
0.1U_0603_25V7K~D
1
2
LV24
MBK1608221YZF_2P
12
RV234
0_0402_5%~D
12
CV185
0.1U_0603_25V7K~D
1
2
DV8
1SS355TE-17_SOD323-2
2
211
RV275
10K_0402_5%~D
<BOM Structure>
12
CV196 0.1U_0402_16V4Z~D
1 2
DV9 1SS355TE-17_SOD323-2
22
1
1
RV25615_0402_5%~D
<BOM Structure>
1 2
CV178
0.1U_0603_25V7K~D
1
2
RV287 10K_0402_5%~D
12
CV206
.1U_0402_16V7K~D
1
2
CV181
22U_0805_6.3VAM~D
1
2
RV291 249_0402_1%~D
1 2
RV273 0_0402_5%~D
1 2
LV17
BLM18BD601SN1D_0603~D
1 2
RV277 33K_0402_5%
12
RV247 10K_0402_5%~D
1 2
E
B
C
QV20
MMST3904-7-F_SOT323-3~D
2
3 1
CV201 0.1U_0402_16V4Z~D
1 2
CV205
0.1U_0402_16V4Z~D
1
2
RV236
10K_0402_5%~D
12
CV193
10P_0402_50V8J~D
1
2
RV263 22_0402_5%
1 2
RV246 10K_0402_5%~D
1 2
RV288 10_0402_5%~D
1 2
RV240 10K_0402_5%~D
1 2
RV250 22_0402_5%
1 2
CV204 0.1U_0402_16V4Z~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3D_VIDEO
UART_TX
4028_EDP_AUXN
4028_EDP_L0P
AUX_UART_TX
IRQ/BOOT7
3D_VIDEO
GPIO_2/BOOT5
I2C_SDA
AUX_UART_RX
4028_EDP_L3N
4028_EDP_L3P
4028_EDP_L2N
4028_EDP_L2P
4028_EDP_L1N
4028_EDP_L1P
GPIO_3/BOOT6
I2C_SCL
I2C_SDA
GPIO_1/BOOT2
IRQ/BOOT7 I2C_SCL
AUX_UART_RX
GPIO_3/BOOT6
AUX_UART_TX
4028_EDP_L0N
TX_XTAL
SPI_DI_4028
SPI_CLK_4028
SPI_CSN_4028
SPI_DO_4028
EC_HDMI_CLK_R
UART_RX
SPI_CLK_4028
SPI_CSN_4028
SPI_DO_4028
4028_EDP_AUXP
SPI_DI_4028
UART_RX
RESET
DP_4028_HPD
GPIO_2/BOOT5
EC_HDMI_CLK_R
AUX_UART_TX
GPIO_3/BOOT6
TX_TCLK
TX_XTAL TX_TCLK
EC_HDMI_DAT_R
GPIO_1/BOOT2
UART_TX
GPIO_0/BOOT3
GPIO_0/BOOT3
EC_HDMI_DAT_R
EDP_TZOUT1+
EDP_TZOUT1-
EDP_TZOUT2+
EDP_TZOUT2-
EDP_TZCLK-
EDP_TZCLK+
EDP_TZOUT0+
EDP_TZOUT0-
EDP_TXCLK+
EDP_TXOUT0+
EDP_TXOUT2+
EDP_TXOUT1+
EDP_TXCLK-
EDP_TXOUT2-
EDP_TXOUT1-
EDP_TXOUT0-
+3VS +5VS
+5VS
+1.2VS_A +VDD_RPLL_1V2
+1.2VS_A
+1.2VS
+1.2VS_A
+3VS
+3VS
+3VS
+AVDD_3V3
+AVDD_OUT_LV_33
+AVDD_LVRX_1V2
+3VS
+1.2VS_A
+AVDD_3V3
+1.2VS
+3VS
+1.2VS_A
+AVDD_3V3
+VDD_RPLL_1V2
+AVDD_LVRX_1V2
+AVDD_OUT_LV_33
+3VS
4028_EDP_L3N<33>
EC_HDMI_DAT <37>
4028_EDP_L3P<33>
4028_EDP_AUXN<33>
4028_EDP_AUXP<33>
4028_EDP_L0N<33>
4028_EDP_L0P<33>
UART_TX
UART_RX
4028_EDP_L1N<33>
4028_EDP_L1P<33>
EC_HDMI_CLK <37>
4028_EDP_L2N<33>
4028_EDP_L2P<33>
DP_4028_HPD<33>
EDP_TZOUT1-<34>
EDP_TZOUT1+<34>
EDP_TZOUT2-<34>
EDP_TZOUT2+<34>
EDP_TZOUT0-<34>
EDP_TZCLK-<34>
EDP_TZCLK+<34>
EDP_TZOUT0+<34>
EDP_TXOUT1-<34>
EDP_TXOUT1+<34>
EDP_TXOUT2-<34>
EDP_TXOUT2+<34>
EDP_TXOUT0-<34>
EDP_TXCLK-<34>
EDP_TXCLK+<34>
EDP_TXOUT0+<34>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
LVDS to eDP-STDP4028
Custom
35 61Friday, June 22, 2012
2012/06/22 2013/06/21
VEGA STDP4028 DPTx BootStraps
20mils
LVDS
eDP
2Mbit
Compal Electronics, Inc.
RV302
4.7K_0402_5%~D
1 2
CV216
0.1U_0603_25V7K~D
1
2
RV318 4.7K_0402_5%~D
1 2
RV316 4.7K_0402_5%~D@
1 2
CV233
10P_0402_50V8J~D
1
2
CV217
22U_0805_6.3VAM~D
1
2
RV322 4.7K_0402_5%~D@
1 2
CV232
10P_0402_50V8J~D
1
2
CV212
0.1U_0603_25V7K~D
1
2
CV244
0.1U_0402_16V4Z~D
1
2
RV3170_0402_5%~D
12
RV303
2.7K_0402_5%
12
CV209
22U_0805_6.3VAM~D
1
2
RV320 4.7K_0402_5%~D
1 2
CV239
0.1U_0603_25V7K~D
1
2
CV214
0.1U_0603_25V7K~D
1
2
CV222
0.1U_0603_25V7K~D
1
2
RV323 4.7K_0402_5%~D
1 2
CV219
0.1U_0603_25V7K~D
1
2
RV309 4.7K_0402_5%~D
1 2
PWR & GND
UV2D
STDP4028-AB_LFBGA164
PVSS3 F6
PVSS3 F9
PVSS3 F7
VDDA_3V3
D6
VSS_RPLL A2
PVDD1
E7
DPTX_VDDA_1V2
B11
PVDD22
G5
AVDD_OUT_LVRX_33
H12
PVSS3 G7
AVSS_OUT_LVRX F2
PVSS3 A1
PVSS3 A14
PVSS3 F8
PVDD1
E8
VDD_RPLL
A3
PVDD1
K6
PVDD21
G11 PVSS3 G6
PVSS3 G8
PVSS3 G9
PVSS3 H6
PVSS3 H7
PVSS3 H8
PVSS3 H9
PVSS3 J6
PVSS3 J7
PVSS3 J8
PVSS3 J9
PVDD1
K9
DPTX_VDDA_1V2
C7
DPTX_VDDA_1V2
C8
AVSS_OUT_LVRX F13
AVSS_OUT_LVRX H10
AVSS_OUT_LVRX H5
AVSS_OUT_LVRX K8
AVDD_OUT_LVRX_33
H3
AVDD_OUT_LVRX_33
L8
AVDD_OUT_LVRX_33
N1
AVDD_OUT_LVRX_33
N14
DPTX_VSSA E10
AVSS_OUT_LVRX P14
DPTX_VSSA D7
DPTX_VSSA D8
DPTX_VDDA_1V2
D9
DPTX_VSSA E9
AVDD_LVRX_12
L7
AVSS_LVRX_12 K7
AVSS_OUT_LVRX P1
VDD33_TX
D5
VSSA_TX C5
RV319 4.7K_0402_5%~D
1 2
RV313 4.7K_0402_5%~D
1 2
RV3140_0402_5%~D
12
CV227
0.1U_0603_25V7K~D
1
2
E0 & E1 LVDS Input
UV2A
STDP4028-AB_LFBGA164
E1_LVRX_CH4N_VIDIN1
M1
E1_LVRX_CH1P_VIDIN10
H2
E1_LVRX_CH2N_VIDIN9
J2
E0_LVRX_CH3N_VIDIN5
N6
E0_LVRX_CH3P_VIDIN4
M6
E0_LVRX_CH4N_VIDIN1
P7
E0_LVRX_CH4P_VIDIN0
N7
E0_LVRX_CH5N_VIDIN_VSYNC M7
E0_LVRX_CH5P_VIDIN_HSYNC L6
E0_LVRX_CH2N_VIDIN9
N4
E0_LVRX_CH6N_VIDIN26 M3
E0_LVRX_CH0N_VIDIN13
P2
E0_LVRX_CH1N_VIDIN11
P3
E0_LVRX_CH6P_VIDIN27 L4
E1_LVRX_CH0N_VIDIN13
G1
E0_LVRX_CH0P_VIDIN12
N2
E1_LVRX_CLKN_VIDIN7
K3
E1_LVRX_CH2P_VIDIN8
J3
E0_LVRX_CLKP_VIDIN6
L5 E0_LVRX_CLKN_VIDIN7
M5
E0_LVRX_CH2P_VIDIN8
M4
E0_LVRX_CH1P_VIDIN10
N3
E1_LVRX_CH6N_VIDIN26 J4
E1_LVRX_CH5P_VIDIN_HSYNC H4
E1_LVRX_CH4P_VIDIN0
M2
E1_LVRX_CH5N_VIDIN_VSYNC J5
E1_LVRX_CH6P_VIDIN27 K5
E1_LVRX_CH1N_VIDIN11
H1
E1_LVRX_CH3P_VIDIN4
L3
E1_LVRX_CLKP_VIDIN6
K4
E1_LVRX_CH0P_VIDIN12
G2
E1_LVRX_CH3N_VIDIN5
L2
CV240
0.1U_0603_25V7K~D
1
2
CV223
22U_0805_6.3VAM~D
1
2
UV3
MX25L2006EM1I-12G_SOP8
S#
1
W#
3
VSS
4
Q
2
D5
C6
VCC 8
RESET# 7
RV310 4.7K_0402_5%~D
1 2
CV230
0.1U_0603_25V7K~D
1
2
CV224
0.1U_0603_25V7K~D
1
2
LV25
BLM18AG601SN1D_0603~D
12
RV301 0_0402_5%~D@
12
CV238
0.1U_0603_25V7K~D
1
2
CV243
47P_0402_50V8J~D
1
2
RV311 4.7K_0402_5%~D
1 2
CV234
22U_0805_6.3VAM~D
1
2
RV308 4.7K_0402_5%~D
1 2
RV300 240_0402_1%
12
CV226
0.1U_0603_25V7K~D
1
2
RV315 4.7K_0402_5%~D
1 2
CV241
0.1U_0603_25V7K~D
1
2
CV213
0.1U_0603_25V7K~D
1
2
CV215
0.1U_0603_25V7K~D
1
2
RV299 0_0402_5%~D@
12
RV305 4.7K_0402_5%~D
1 2
CV211
0.1U_0603_25V7K~D
1
2
CV220
22U_0805_6.3VAM~D
1
2
LV26
BLM18AG601SN1D_0603~D
12
RV307
10K_0402_5%~D
12
LV27
BLM18AG601SN1D_0603~D
12
CV231
0.1U_0603_25V7K~D
1
2
RV304
4.7K_0402_5%~D
@
1 2
CV242
0.1U_0402_16V4Z~D
@
1
2
LV28
BLM18AG601SN1D_0603~D
12
SYS, Audio & DPTX
UV2C
STDP4028-AB_LFBGA164
RESETn
E6
IRQ/BOOT7/GPIO_12
D12
I2S_3/GPIO_11 D3
I2S_2/GPIO_10 F4
I2S_W CLK/GPIO_4 E4
I2S_BCLK/GPIO_7 C1
TESTMODE0
F3
I2S_0/GPIO_8 D2
I2S_1/GPIO_9 F5
AUX_I2C_SCL/GPIO_15 C13
IR_IN/GPIO_6
G4
SPI_CSn/HOST_CS/GPIO_17
F10
SPI_DI/HOST_D1/GPO_19
D13
UART_RX/GPIO_14 B1
UART_TX/BOOT1/GPIO_13 C2
VBUFC_RPLL
C3
AUX_I2C_SDA_GPIO_16 B14
TESTMODE1
G3
SPI_CLK/HOST_CLK/GPIO_18
E12
I2C_SCL/GPIO_24 B13
SPI_DO/HOST_D0/GPO_20
C14
DPTX_HPD_IN/GPIO_23
C12
GPIO_2/BOOT5 G10
DPTX_REXT
C11
DPTX_AUXN
C10
DPTX_AUXP
D10
DPTX_ML_L3N
B9
DPTX_ML_L3P
C9
DPTX_ML_L2N
A8
DPTX_ML_L2P
B8
DPTX_ML_L1N
A7
DPTX_ML_L1P
B7
DPTX_ML_L0N
B6
DPTX_ML_L0P
C6
TX_TCLK
C4
TX_XTAL
B4
I2C_SDA/GPIO_25 A13
AUX_UART_TX/BOOT4/GPIO_21 B12
AUX_UART_RX/GPIO_22 A12
CLK_OUT/GPIO_5/BOOT0 E3
GPIO_3/BOOT6 F11
PWM0/GPIO_0/BOOT3 E5
GPIO_1/BOOT2 D4
NC1 F12
NC2 G12
NC3 D11
NC4 E11
NC5 B2
NC6 B3
CV237
22U_0805_6.3VAM~D
1
2
RV3210_0402_5%~D
12
CV228
0.1U_0402_16V4Z~D
1
2
CV218
0.1U_0603_25V7K~D
1
2
G1 G2
YV2
27MHZ_10PF_X3S027000BA1H-U~D
1
2
3
4
O0 & O1 LVDS Input
UV2B
STDP4028-AB_LFBGA164
O1_LVRX_CH4N_VIDIN3
G13
O1_LVRX_CH1P_VIDIN20
L13
O1_LVRX_CH2N_VIDIN19
K12
O0_LVRX_CH3N_VIDIN15
P12
O0_LVRX_CH3P_VIDIN14
N12
O0_LVRX_CH4N_VIDIN3
P13
O0_LVRX_CH4P_VIDIN2
N13
O0_LVRX_CH5N_VIDIN_CLK M8
O0_LVRX_CH5P_VIDIN_DE L9
O0_LVRX_CH2N_VIDIN19
M10
O0_LVRX_CH6N_VIDIN24 L11
O0_LVRX_CH0N_VIDIN23
P8
O0_LVRX_CH1N_VIDIN21
N9
O0_LVRX_CH6P_VIDIN25 M12
O1_LVRX_CH0N_VIDIN23
M13
O0_LVRX_CH0P_VIDIN22
N8
O1_LVRX_CLKN_VIDIN17
J12
O1_LVRX_CH2P_VIDIN18
K11
O0_LVRX_CLKP_VIDIN16
M11 O0_LVRX_CLKN_VIDIN17
N11
O0_LVRX_CH2P_VIDIN18
L10
O0_LVRX_CH1P_VIDIN20
M9
O1_LVRX_CH6N_VIDIN24 K10
O1_LVRX_CH5P_VIDIN_DE H11
O1_LVRX_CH4P_VIDIN2
G14
O1_LVRX_CH5N_VIDIN_CLK J10
O1_LVRX_CH6P_VIDIN25 J11
O1_LVRX_CH1N_VIDIN21
L12
O1_LVRX_CH3P_VIDIN14
H14
O1_LVRX_CLKP_VIDIN16
J13
O1_LVRX_CH0P_VIDIN22
M14
O1_LVRX_CH3N_VIDIN15
H13
CV225
0.1U_0603_25V7K~D
1
2
CV229
22U_0805_6.3VAM~D
1
2
CV235
0.1U_0603_25V7K~D
1
2
CV221
0.1U_0603_25V7K~D
1
2
CV236
0.1U_0603_25V7K~D
1
2
CV210
0.1U_0603_25V7K~D
1
2
RV312 4.7K_0402_5%~D
1 2
RV306
10K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMC_CFG_HPD
VGA_DPD_SW_N0
VGA_DPD_SW_P3
VGA_DPD_SW_N2
VGA_DPD_SW_P2
VGA_DPD_SW_P1
VGA_DPD_SW_N3
VGA_DPD_SW_P0
VGA_DPD_SW_N1
DGPU_SEL#
DGPU_EDIDSEL#_R
VGA_DPD_AUXN/DDC
VGA_DPD_AUXP/DDC
DMC_PWDN
DMC_PWDN
DMC_IN2_PEQ
DMC_CFG_HPD
DMC_PRE_EMI
DMC_DDCBUF
DMC_IN1_PEQ
DP_DMC_ML2N
DP_DMC_ML1N
DP_DMC_ML3N
DP_DMC_ML3P
DP_DMC_ML2P
DP_DMC_ML0N
DP_DMC_ML0P
DP_DMC_ML1P
DMC_SW _P3
DMC_SW _N2
DMC_SW _P2
DMC_SW _N3
DMC_SW _P1
DMC_SW _N0
DMC_SW _N1
DMC_SW _P0
VGA_DMC_HPD_R
PCH_DMC_HPD_R
CPU_DPD_SW_N2
CPU_DPD_SW_N3
CPU_DPD_SW_N1
CPU_DPD_SW_P1
CPU_DPD_SW_P3
CPU_DPD_SW_N0
CPU_DPD_SW_P0
CPU_DPD_SW_P2
DMC_IN2_PEQ
DMC_IN1_PEQ
DMC_CFG_HPD
DMC_IN2_PEQ
DMC_PWDN
DMC_PRE_EMI
DMC_DDCBUF
DMC_IN1_PEQ
DMC_PRE_EMI
DMC_DDCBUF
PCH_DPD_CLK
PCH_DPD_DAT
DMC_SINK_HPD
DP_DMC_ML0N
DP_DMC_ML0P
CPU_MXM_DMC_N2
CPU_MXM_DMC_N3
CPU_MXM_DMC_N0
CPU_MXM_DMC_P3
CPU_MXM_DMC_P2
DP_DMC_ML1P
CPU_MXM_DMC_P0
DP_DMC_ML3P
DP_DMC_ML1N
DP_DMC_HPD
DP_DMC_ML3N CPU_MXM_DMC_N1
CPU_MXM_DMC_P1
DP_DMC_ML2N
DP_DMC_ML2P
DMC_SINK_HPD
DGPU_HPD_INT#
DP_DMC_AUXP
DP_DMC_AUXN
DP_DMC_AUXN
DP_DMC_AUXP
DMC_CFG1
DMC_PC0
DMC_CFG0
DMC_PC1
DMC_PC2
DMC_CFG1
DMC_CFG0
DMC_PC2
DMC_PC1
DMC_PC0
DMC_SCLK_R
DMC_PC2
DMC_SDATA_R
DMC_OE#
DMC_PC1
DMC_CFG0
DMC_PC0
DMC_CFG1
DMC_DDCBUF
DP_DMC_AUXP
DP_DMC_AUXN
DMC_SW _DETECT
DMC_SDATA_R
DMC_SCLK_R CPU_MXM_DMC_AUXP
CPU_MXM_DMC_AUXN
DMC_SW _DETECT
DMC_OE#
+3VS
+3V_MXM
+3VS
+HDMI_5V_OUT
+HDMI_5V_OUT
+3VS
+3VS
+3VS
+3VS
+5VS
+3VS +3VS
+3VS
DGPU_SEL#<36>
DGPU_EDIDSEL#_R<36>
VGA_DPD_AUXP/DDC<29>
VGA_DPD_P0<29>
VGA_DPD_N0<29>
VGA_DPD_P1<29>
VGA_DPD_AUXN/DDC<29>
VGA_DPD_N1<29>
VGA_DPD_P2<29>
VGA_DPD_N2<29>
VGA_DPD_P3<29>
VGA_DPD_N3<29>
PCH_DPD_DAT<17>
PCH_DPD_CLK<17>
VGA_DMC_HPD<29>
PCH_DMC_HPD<17>
CPU_DPD_DMC_P0<8>
CPU_DPD_DMC_N0<8>
CPU_DPD_DMC_P1<8>
CPU_DPD_DMC_N1<8>
CPU_DPD_DMC_P2<8>
CPU_DPD_DMC_N2<8>
CPU_DPD_DMC_P3<8>
CPU_DPD_DMC_N3<8>
CPU_MXM_DMC_P1 <51>
CPU_MXM_DMC_N0 <51>
CPU_MXM_DMC_N1 <51>
CPU_MXM_DMC_N3 <51>
CPU_MXM_DMC_P2 <51>
CPU_MXM_DMC_P3 <51>
CPU_MXM_DMC_N2 <51>
DP_DMC_HPD<51>
CPU_MXM_DMC_P0 <51>
DGPU_HPD_INT#<21,36>
CPU_MXM_DMC_AUXP <51>
CPU_MXM_DMC_AUXN <51>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DP SW for DMC
Custom
36 61Friday, June 22, 2012
2012/06/22 2013/06/21 Compal Electronics, Inc.
IN2
IN1
SEL
0
Y
1
PCH/GPU AUX&LANE SW for DPB
Place LC Filter
closed to JHDMI
PS121 CFG0/ CFG1
SCLZ/SDAZ output voltage select;
CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB
Close to UV2 VCC pins
CPU
MXM
CV265
0.1U_0402_16V4Z~D
1
2
RV3654.7K_0402_5%~D @
12
RV327 2.2K_0402_5%~D
1 2
RV3614.7K_0402_5%~D @
12
RV335 4.7K_0402_5%~D@
1 2
CV256 0.1U_0402_16V4Z~D
1 2
RV61 4.7K_0402_5%~D
1 2
CV2682.2U_0402_6.3V6M~D
12
CV267
2.2U_0603_6.3V6K~D
1
2
CV248 0.1U_0402_10V6K~D
1 2
RV338 0_0402_5%~D
1 2
CV260 0.1U_0402_10V7K~D
1 2
E
B
C
QV21
MMST3904-7-F_SOT323-3~D
@
2
3 1
RV3544.7K_0402_5%~D @
12
LV29
MBK1608221YZF_2P
1 2
CV253 0.1U_0402_10V6K~D
1 2
CV247 0.1U_0402_10V6K~D
1 2
RV333 4.7K_0402_5%~D@
1 2
CV245
10U_0603_6.3V6M~D
1
2
D
G
S
QV23
SSM3K7002F_SC59-3~D
1
3
2
RV341 0_0402_5%~D
1 2
RV3624.7K_0402_5%~D @
12
CV266
0.01U_0402_16V7K~D
1
2
RV326 4.7K_0402_5%~D
1 2
RV332 4.7K_0402_5%~D@
1 2
CV246
0.1U_0402_16V4Z~D
1
2
RV346 10K_0402_5%~D
12
RV334 4.7K_0402_5%~D@
1 2
RV336 4.7K_0402_5%~D
1 2
RV3644.7K_0402_5%~D @
12
DV13
DAN217T146_SC59-3
@
2
3
1
RV329 4.7K_0402_5%~D
1 2
RV345 0_0402_5%~D
1 2
RV3584.7K_0402_5%~D
12
RV339 0_0402_5%~D
1 2
RV337 4.7K_0402_5%~D
1 2
CV271
10P_0402_50V8J~D
@
1
2
D
G
S
QV22
SSM3K7002F_SC59-3~D
1 3
2
RV348
499_0402_1%~D
12
RV344 0_0402_5%~D
1 2
RV349
100K_0402_5%~D
12
RV366
1.5K_0402_5%
12
CV251 0.1U_0402_10V6K~D
1 2
CV263
0.01U_0402_16V7K~D
1
2
RV331 4.7K_0402_5%~D
1 2
RV3554.7K_0402_5%~D @
12
CV258 0.1U_0402_16V4Z~D
1 2
CV264
0.1U_0402_16V4Z~D
1
2
CV255 0.1U_0402_16V4Z~D
1 2
RV352
200K_0402_5%
1 2
RV340 0_0402_5%~D
1 2
RV369 0_0402_5%~D
1 2
RV353
10K_0402_5%~D
@
1 2
RV330 2.2K_0402_5%~D
1 2
CV262 0.1U_0402_10V7K~D
1 2
UV21
PS8271QFN48GTR-A1_QFN48_7X7
IN1_D3p
2
VDD 6
RTERM 7
IN2_D1n
8
IN2_D1p
9
IN2_HPD
10
IN2_D2p
12
IN1_D4p
5
IN1_D3n
1
GND
18
REXT
24
OUT_D4n 27
VDD 31
OUT_D1n 36
OUT_SDA 37
GND
43
IN2_D2n
11
IN2_PEQ
15
SW_MAIN
21
OUT_D4p 26
OUT_D2n 33
DDCBUF 40
IN1_HPD
46
IN1_D4n
4
IN1_PEQ
3
IN2_D3n
13
IN2_D3p
14
IN2_D4n
16
IN2_D4p
17
IN2_SCL
19
IN1_D2p
48 IN1_D2n
47 IN1_D1p
45 IN1_D1n
44
IN1_SDA
42 IN1_SCL
41
OUT_SCL 38
PWDN_ASQ 25
CFG_HPD 28
OUT_D3p 29
OUT_D3n 30
OUT_D2p 32
IN2_SDA
20
SW_DDC
22
CEXT
23
OUT_HPD 39
PRE_EMI 34
OUT_D1p 35
PAD
49
RV347 10K_0402_5%~D
12
RV368 0_0402_5%~D
1 2
DV12
DAN217T146_SC59-3
@
2
3
1
RV350
200K_0402_5%
@
1 2
RV3634.7K_0402_5%~D @
12
RV3602.2K_0402_5%~D
12
CV269
220P_0402_50V7K~D
1
2
RV3592.2K_0402_5%~D
12
CV254 0.1U_0402_10V6K~D
1 2
CV259 0.1U_0402_10V7K~D
1 2
RV62499_0402_1%~D
12
RV351 0_0402_5%~D
1 2
RV325 4.7K_0402_5%~D@
1 2
RV342 0_0402_5%~D
1 2
RV343 0_0402_5%~D
1 2
RV324 4.7K_0402_5%~D@
1 2
CV261 0.1U_0402_10V7K~D
1 2
CV257 0.1U_0402_16V4Z~D
1 2
CV270
10P_0402_50V8J~D
@
1
2
CV250 0.1U_0402_10V6K~D
1 2
RV328 4.7K_0402_5%~D@
1 2
RV3564.7K_0402_5%~D
12
CV249 0.1U_0402_10V6K~D
1 2
RV31 2.2K_0402_5%~D
12
CV252 0.1U_0402_10V6K~D
1 2
RV3574.7K_0402_5%~D @
12
RV367
1.5K_0402_5%
12
RV30 2.2K_0402_5%~D
12
DV11
BAV99-7-F_SOT23-3
@
2
3
1
UV22
PS121QFN48G_QFN48_7X7
VCC4 33
OUT1p 23
OUT1n 22
OUT2p 20
OUT2n 19
OUT3p 17
OUT3n 16
OUT4p 14
OUT4n 13
VCC5 40
VCC6 46
IN1p
38
IN1n
39
IN2p
41
IN2n
42
IN3p
44
IN3n
45
IN4p
47
IN4n
48
POW
2
I2C_ADDR0/PC0
3
I2C_ADDR1/PC1
4
SDA
8
SCL
9
GND/PC2
1
REXT
6
CEXT
10
HPD 7
HPD_SINK
30
GND7
36
VCC1 11
GND4
24
GND6
31 GND5
27 VCC2 15
GND3
18
VCC3 21
GND1
5
GND2
12
GND8
37
GND9
43
SDA_CTL/CFG1
34
SCL_CTL/CFG0
35
NC/DDCBUF_EN#
32
NC/OE#
25
I2C_CTL_EN#
26
SDAZ 29
SCLZ 28
GND10
49
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_EDP_PWM
CSDA
CPU_EDP_P1_C
CPU_EDP_N1_C
MIIC_SCL
CIICSDA
+SWR_V12
TL_BKOFF#_R
EDID_CLK
EDID_DATA
EC_SMB_DA2
TL_INVT_PWM
+AVCC33
+DVCC33
CSDA
EC_SMB_CK2CSCL
CSCL
CPU_EDP_P0_C
CPU_EDP_N0_C
MIIC_SDA
+SW_LX
CIICSCL
CPU_EDP_AUX_C
CPU_EDP_AUX#_C
TL_ENVDD
+SWR_V12
CPU_EDP_AUX#_C
CPU_EDP_AUX_C
+AVCC33 +DVCC33
TL_BKOFF#_R
TL_BKOFF#_R
CSCL
CSDA
EDID_DATA
EDID_CLK
MIIC_SCL
LVDS_ACLK
LVDS_ACLK#
LVDS_A0
LVDS_A0#
LVDS_A1
LVDS_A1#
LVDS_A2
LVDS_A2#
LVDS_BCLK
LVDS_BCLK#
LVDS_B0
LVDS_B0#
LVDS_B1
LVDS_B1#
LVDS_B2
LVDS_B2#
MIIC_SDA
FW_ROM_SCL
FW_ROM_SDA
MIIC_SCL
EDID_CLK
MIIC_SDA
EDID_DATA
2136_HPD#
+3VS_RT
+DVCC33
+DVCC33
+DVCC33
+3VS_RT
+3VS_RT+3VS
+3VS_RT
+3VS_RT
+1.2VS
+DVCC33
+DVCC33
CPU_EDP_P0_C<31>
CPU_EDP_N0_C<31>
CPU_EDP_P1_C<31>
CPU_EDP_N1_C<31>
CPU_EDP_AUX_C<31>
CPU_EDP_AUX#_C<31>
LVDS_ACLK <41>
LVDS_ACLK# <41>
LVDS_A0 <41>
LVDS_A0# <41>
LVDS_A2 <41>
LVDS_A2# <41>
LVDS_A1 <41>
LVDS_A1# <41>
LVDS_BCLK <41>
LVDS_BCLK# <41>
LVDS_B0 <41>
LVDS_B0# <41>
LVDS_B2 <41>
LVDS_B2# <41>
LVDS_B1 <41>
LVDS_B1# <41>
EDID_CLK <42>
EDID_DATA <42>
TL_ENVDD <42,43>
TL_INVT_PWM <42>
PCH_EDP_PWM<17>
TL_INVT_BL <42>
EC_SMB_CK2 <19,43,53,54>
BKOFF#<42,43>
EC_SMB_DA2 <19,43,53,54>
ENBKL <42,43>
2136_HPD#<31>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
Translator RTD2136S
Custom
37 61Friday, June 22, 2012
2012/06/22 2013/06/21
60 mils
60 mils
40 mils
Close to 18 pin
30mil 30mil
AUX termination
60 mils
Close to LV11
Close to 5 pin
Close to 11 pin Close to 43 pin
Close to LV10Close to LV9 Close to 22 pin
Vendor advise reserve it
EEPROM
ROMLESS
EEROM
Addr: A8 (1010 100X)
RV19
100K_0402_5%
LVDS@
12
RV7 0_0805_5%
LVDS@
1 2
CV282
0.1U_0402_16V4Z
LVDS@
1
2
RV47 4.7K_0402_5%LVDS@
1 2
CV279
10U_0603_6.3V6M
LVDS@
1
2
LV30
FBMA-L11-201209-221LMA30T_0805
LVDS@
12
RV45
4.7K_0402_5%
LVDS@
1 2
RV23
0_0402_5%
LVDS@
1 2
RV46
4.7K_0402_5%
@
1 2
RV8 0_0805_5%
LVDS@
1 2
CV283
0.1U_0402_16V4Z
LVDS@
1
2
RV25 0_0402_5%LVDS@
1 2
QV2A
DMN66D0LDW-7_SOT363-6~D
LVDS@
61
2
RV18
4.7K_0402_5%
LVDS@
1 2
RV26 0_0402_5%LVDS@
1 2
RV16
100K_0402_5%
LVDS@
12
QV2B
DMN66D0LDW-7_SOT363-6~D
LVDS@
34
5
CV280
0.1U_0402_16V4Z
LVDS@
1
2
RV12 0_0402_5%
LVDS@
1 2
RV50
4.7K_0402_5%
LVDS@
1 2
RV52 4.7K_0402_5%
LVDS@
1 2
RV11 0_0402_5%
LVDS@
1 2
CV275
0.1U_0402_16V4Z
LVDS@
1
2
RV20 0_0402_5%
LVDS@
1 2
RV21 4.7K_0402_5%
LVDS@
1 2
CV276
10U_0603_6.3V6M
LVDS@
1
2
RV51 4.7K_0402_5%LVDS@
1 2
RV14 0_0402_5%
@
1 2
UV25
MC74VHC1G08DFT2G SC70 5P
LVDS@
B
2
A
1Y4
P5
G
3
CV284
0.1U_0402_16V7K
LVDS@
1 2
RV9 12K_0402_1%
LVDS@
1 2
LV31
FBMA-L11-201209-221LMA30T_0805
LVDS@
12
RTD2136S
PWR
DP
LVDSGND
OTHERS
UV24
RTD2136S-VE-CG_QFN48_6X6
TXOC- 36
TXOC+ 35
TXO3- 34
TXO3+ 33
TXO2- 38
TXO2+ 37
TXO1- 40
TXO1+ 39
TXO0- 42
TXO0+ 41
TXEC- 26
TXEC+ 25
TXE0- 32
TXE0+ 31
TXE1- 30
TXE1+ 29
TXE2- 28
TXE2+ 27
TXE3- 24
TXE3+ 23
DP_V33
5
LANE0P
7
LANE0N
8
LANE1P
9
LANE1N
10
AUX-CH_P
4
AUX-CH_N
3
DP_HPD
1
DP_GND 6
PWMIN
21
PANEL_VCC 20
PWMOUT 19
BL_EN 44
CIICSCL1
13
CIICSDA1
14
MIICSCL0
48
MIICSDA0
47
MIICSCL1 46
MIICSDA1 45
DP_V12
11
VCCK
43
SWR_VCCK
15
GND 16
SWR_LX
17
SWR_VDD
18
PVCC
22
TESTMODE
2
DP_REXT
12
PAD 49
CV273
0.1U_0402_16V4Z
LVDS@
1
2
CV274
0.1U_0402_16V4Z
LVDS@
1
2
LV32
4.7UH_PG031B-4R7MS_1.1A_20%
LVDS@
1 2
RV15 0_0402_5%
LVDS@
1 2
UV23
CAT24C64WI-GT3_SO8
LVDS@
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
CV277
0.1U_0402_16V4Z
LVDS@
1
2
RV24
0_0402_5%
LVDS@
1 2
RV22
100K_0402_5%
LVDS@
12
CV281
22U_0805_6.3V6M
LVDS@
1
2
CV272
22U_0805_6.3V6M
LVDS@
1
2
CV278
0.1U_0402_16V4Z
LVDS@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDP_DETECT#
EDP_DETECT#
LVDS_A0#
LVDS_A0
LVDS_MXM_TXOUT0-
LVDS_MXM_TXOUT0+
LVDS_MXM_TXOUT1-
LVDS_MXM_TXOUT1+
LVDS_MXM_TXOUT2-
LVDS_MXM_TXOUT2+
LVDS_MXM_TXCLK-
LVDS_MXM_TXCLK+
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
LVDS_ACLK#
LVDS_ACLK
LVDS_B0#
LVDS_B0
LVDS_B1#
LVDS_B1
LVDS_B2#
LVDS_B2
LVDS_BCLK#
LVDS_BCLK
LVDS_MXM_TZOUT0-
LVDS_MXM_TZOUT0+
LVDS_MXM_TZCLK-
LVDS_MXM_TZOUT1-
LVDS_MXM_TZOUT1+
LVDS_MXM_TZOUT2-
LVDS_MXM_TZOUT2+
LVDS_MXM_TZCLK+
LVDS_MUX_TZCLK+
LVDS_MUX_TZCLK-
LVDS_MUX_TZOUT2+
LVDS_MUX_TZOUT2-
LVDS_MUX_TXOUT0-
LVDS_MUX_TXOUT0+
LVDS_MUX_TXOUT1-
LVDS_MUX_TXOUT1+
LVDS_MUX_TXOUT2-
LVDS_MUX_TXOUT2+
LVDS_MUX_TXCLK-
LVDS_MUX_TXCLK+
LVDS_MUX_TZOUT0-
LVDS_MUX_TZOUT0+
LVDS_MUX_TZOUT1-
LVDS_MUX_TZOUT1+
+3VS
+3VS
EDP_DETECT# <21>
LCDVDD_ON<33,34,42>
LVDS_MUX_TXOUT0- <42>
LVDS_MUX_TXOUT2- <42>
LVDS_MUX_TXOUT2+ <42>
LVDS_MUX_TXCLK- <42>
LVDS_MUX_TXCLK+ <42>
LVDS_MUX_TZOUT0- <42>
LVDS_MUX_TZOUT2- <42>
LVDS_MUX_TZOUT2+ <42>
LVDS_MUX_TZCLK- <42>
LVDS_MUX_TZOUT0+ <42>
LVDS_MUX_TZOUT1- <42>
LVDS_MUX_TZOUT1+ <42>
LVDS_MUX_TZCLK+ <42>
LVDS_MUX_TXOUT0+ <42>
LVDS_MUX_TXOUT1- <42>
LVDS_MUX_TXOUT1+ <42>
LVDS_A0<40>
LVDS_MXM_TXOUT0+<29>
LVDS_MXM_TXOUT0-<29>
LVDS_A1<40>
LVDS_A1#<40>
LVDS_A0#<40>
LVDS_MXM_TXOUT1+<29>
LVDS_MXM_TXOUT1-<29>
LVDS_A2#<40>
LVDS_A2<40>
LVDS_ACLK<40>
LVDS_MXM_TXOUT2-<29>
LVDS_MXM_TXOUT2+<29>
LVDS_MXM_TXCLK-<29>
LVDS_MXM_TXCLK+<29>
LVDS_ACLK#<40>
LVDS_MXM_TZOUT0-<29>
LVDS_MXM_TZOUT0+<29>
LVDS_B0<40>
LVDS_B0#<40>
LVDS_B1#<40>
LVDS_B1<40>
LVDS_MXM_TZOUT1-<29>
LVDS_MXM_TZOUT1+<29>
LVDS_B2#<40>
LVDS_MXM_TZOUT2-<29>
LVDS_BCLK<40>
LVDS_B2<40>
LVDS_BCLK#<40>
LVDS_MXM_TZCLK+<29>
LVDS_MXM_TZCLK-<29>
LVDS_MXM_TZOUT2+<29>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
LVDS SW- 1 to 2 & GPU/PCH
Custom
38 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
DGPU_MXM
Input
STDP6038 SW STDP4028 PCH/GPU AUX for LVDS
RTD2136
SEL
Y
L
H
RTD2136
DGPU_MXM
Output
CV286
0.1U_0402_16V4Z~D
1
2
D
G
S
QV24
SSM3K7002F_SC59-3~D
13
2
RV370
100K_0402_5%~D
12
UV26
PI3LVD1012BE_BQSOP80
GND1
3VDD1 4
GND2
13
GND3
20
GND4
21
GND6
38
GND7
52
GND8
74
OE2#
25
VDD2 10
VDD3 19
VDD4 22
VDD5 28
GND5
31
VDD6 37
VDD7 47
VDD8 69
0B1
2
1B1
1
0B2
80
1B2
79
2B1
78
3B1
77
2B2
76
3B2
75
4B1
73
5B1
72
4B2
71
5B2
70
6B1
68
7B1
67
6B2
66
7B2
65
8B1
64
9B1
63
8B2
62
9B2
61
SLE1 16
A0 5
A1 6
A2 8
A3 9
SEL2 34
A4 11
A5 12
A6 14
A7 15
A8 17
A9 18
A10 23
A11 24
A12 26
A13 27
A14 29
A15 30
A16 32
A17 33
A18 35
A19 36
10B1
60
11B1
59
10B2
58
11B2
57
12B1
56
13B1
55
12B2
54
13B2
53
14B1
51
15B1
50
14B2
49
15B2
48
16B1
46
17B1
45
16B2
44
17B2
43
18B1
42
19B1
41
18B2
40
19B2
39
OE1#
7
CV287
4.7U_0603_6.3V6K~D
1
2
CV285
0.1U_0402_16V4Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DGPU_EDIDSEL_R#
DGPU_SELECT#
DISPOFF#BKOFF#
VGA_EC_PWM
DGPU_SELECT#
HDMI_IN_PW M_SELECT#
I2CC_SCL
I2CC_SDA
USB20_P12_CONN
LCD_TEST
INV_PWM
DISPOFF#
DMIC0
CAM_DET#
DMIC_CLK
USB20_N12_CONN
LVDS_CAB_DET#
TZCLK+
TZOUT2+
TZOUT2-
TXOUT1-
TXOUT1+
TZOUT0+
TZOUT0-
TZOUT1+
TZOUT1-
TXOUT0-
TXOUT0+
TXCLK+
TXOUT2+
TXOUT2-
LCDVDD_ON
HDMI_IN_PW M
TZOUT0-
LVDS_MUX_TZOUT0+ TZOUT0+
TZOUT1-
TZOUT1+
TZOUT2-
LVDS_MUX_TZCLK+
TZOUT2+
LVDS_MUX_TZOUT2-
LVDS_MUX_TZCLK-
LVDS_MUX_TZOUT2+
LVDS_MUX_TZOUT1+
LVDS_MUX_TZOUT0-
LVDS_MUX_TZOUT1-
LVDS_MUX_TXOUT0+
LVDS_MUX_TXOUT0-
LVDS_MUX_TXOUT1+
LVDS_MUX_TXOUT1-
TZCLK-
TZCLK+
TXOUT0+
TXOUT1-
HDMI_IN_SELECT#_R
TXOUT0-
TXOUT2-
TXOUT2+
TXCLK-
TXCLK+
LVDS_MUX_TXOUT2-
TXOUT1+
LVDS_MUX_TXOUT2+
LVDS_MUX_TXCLK-
LVDS_MUX_TXCLK+
HDMI_IN_SELECT#_R
HDMI_IN_PW M_SELECT#
ENBKL
INV_PWM
DGPU_SELECT#
HDMI_IN_SELECT#
I2CC_SCL
I2CC_SDA
USB20_P12_CONN
USB20_N12_CONN
LCDVDD_ON
VGA_LCD_CLK
EDID_CLK
VGA_LCD_DAT
EDID_DATA
DGPU_EDIDSEL_R#
HDMI_IN_SELECT#DHMI_IN_NV_CLK
DHMI_IN_NV_DAT
LCDVDD_ON
USB20_N12_CONNUSB20_N12
USB20_P12 USB20_P12_CONN
TL_INVT_PWM
LVDS_TZCLK-
LVDS_TZOUT1+
LVDS_TZOUT1-
LVDS_TZOUT2-
LVDS_TZOUT0+
LVDS_TZOUT2+
LVDS_TZCLK+
LVDS_TZOUT0-
LVDS_TXOUT1+
LVDS_TXOUT1-
LVDS_TXOUT0+
LVDS_TXOUT0-
LVDS_TXOUT2-
LVDS_TXCLK-
LVDS_TXOUT2+
LVDS_TXCLK+
TXCLK-
TZCLK-
DMIC_CLK
+LCDVDD
+5VALW
+LCDVDD
+3VS
+3VS
+3VS_CAM+3VS
+INVPWR_B+ B+
+LCDVDD
+3VS
+3VS_CAM
+3VS +3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+5VS
+3VS
+LCDVDD
DGPU_BKL_PWM_SEL# <21>
HDMI_IN_PW MSEL#<17>
EC_INV_PWM<43>
VGA_PNL_PWM<29>
HDMI_IN_PW M<37>
TL_INVT_PWM<40>
DGPU_BKL_EN<29>
HDMI_IN_BKL_EN<37>
TL_INVT_BL<40>
INV_PWM <33>
ENBKL <40,43>
DGPU_EDIDSEL#<21,32,36>
EC_ENVDD<33,43>
LVDS_MUX_TXOUT0-<41>
LVDS_MUX_TXOUT0+<41>
LVDS_MUX_TXOUT1-<41>
LVDS_MUX_TXOUT1+<41>
LVDS_MUX_TXOUT2-<41>
LVDS_MUX_TXOUT2+<41>
LVDS_MUX_TXCLK-<41>
LVDS_MUX_TXCLK+<41>
LVDS_MUX_TZOUT0-<41>
LVDS_MUX_TZOUT0+<41>
LVDS_MUX_TZOUT1-<41>
LVDS_MUX_TZOUT1+<41>
LVDS_MUX_TZOUT2-<41>
LVDS_MUX_TZOUT2+<41>
LVDS_MUX_TZCLK-<41>
LVDS_MUX_TZCLK+<41>
DGPU_ENVDD<29>
HDMI_IN_ENVDD<37>
TL_ENVDD<40,43>
DGPU_SELECT# <17,32,36>
LCDVDD_ON <33,34,41>
EN_CAM<43>
BKOFF#<40,43>
CAM_DET# <18,33>
DMIC_CLK <33,45>
DMIC0 <33,45>
DISPOFF# <33>
LVDS_CAB_DET# <21>
LCD_TEST <33,43>
VGA_LCD_CLK<29>
DHMI_IN_NV_CLK<37>
EDID_CLK<40>
VGA_LCD_DAT<29>
DHMI_IN_NV_DAT<37>
EDID_DATA<40>
HDMI_IN_SELECT# <33,43>
SG_AMD_BKL<17,43>
USB20_P12<20>
USB20_N12<20>
EC_INV_PWM<43>
LVDS_TZOUT0-<34>
LVDS_TZOUT0+<34>
LVDS_TZOUT1-<34>
LVDS_TZOUT1+<34>
LVDS_TZOUT2-<34>
LVDS_TZOUT2+<34>
LVDS_TZCLK-<34>
LVDS_TZCLK+<34>
LVDS_TXOUT0-<34>
LVDS_TXOUT0+<34>
LVDS_TXOUT1-<34>
LVDS_TXOUT1+<34>
LVDS_TXOUT2-<34>
LVDS_TXOUT2+<34>
LVDS_TXCLK-<34>
LVDS_TXCLK+<34>
Title
Size Document Number Rev
Date: Sheet of
LA-9331P
0.1
LVDS SW- 6038/SYSTEM & CONN
39 61Friday, June 22, 2012
Compal Electronics, Inc.
LCD Backlight Selector
W=60mils
LCD POWER
LVDS Conn.
HDMI IN (D)
HDMI IN (I)
UMA
DSC1
00
0
1
1 1
0
S1 S0 Y
EN_CAM control circuit
W=80mils
W=60mils
UMA
HDMI IN
0
1 DSC
0
11
1
0
0
S0S1 Y
HDMI IN
PCH/GPU MUX & 6038 MUX SW for LVDS
L
Y
SEL
B2
B1
H
Close to JLVDS1
LCD DDC Selector
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL,
TRADE SECRET, AND OTHER PROPRIETARY INFORMATION
OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN
AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS
SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
DELL'S EXPRESS WRITTEN CONSENT.
HDMI IN (D)
HDMI IN (I)
UMA
DSC1
00
0
1
1 1
0
S1 S0 Y
1A 2A
1B1 2B1
1B2 2B2
1B3 2B3
1B4 2B4
1A 2A
1B1 2B1
1B2 2B2
1B3 2B3
1B4 2B4
1A 2A
1B1 2B1
1B2 2B2
1B3 2B3
1B4 2B4
Output
HDMI IN(1:2)
CPU/MXM(MUX) Input
RV371
10K_0402_5%~D
@
12
RV379
100K_0402_5%~D
12
CV289
0.1U_0402_16V4Z~D
1
2
RV372 0_0402_5%~D@
1 2
LV33
DLW21SN900SQ2L_0805_4P~D
1
122
33
4
4
RV394
100K_0402_5%~D
12
RV390
220K_0402_1%
12
D
G
S
QV26
SSM3K7002F_SC59-3~D
1
3
2
CV296
0.1U_0402_16V4Z~D
1
2
CV295
10U_0805_10V4Z~D
1
2
RV382
0_0402_5%~D
@
1 2
RV381
100K_0402_5%~D
12
RV376
10K_0402_5%~D
@
12
CV290
0.1U_0402_16V4Z~D
1
2
DV14
IP4223CZ6_SO6~D
V I/O
1
V I/O
3
V I/O 6
V I/O 4
Ground
2V BUS 5
RV375 0_0402_5%~D@
1 2
CV300
4.7U_0805_10V4Z~D
1
2
RV384 0_0402_5%~D
@
1 2
RV385
100K_0402_5%~D
12
RV388
100_0603_5%~D
12
UV28
SN74CB3Q3253PWR_TSSOP16
1B2
51B1
6
1OE
1
S1 2
GND 8
1B3
4
1B4
3
VCC 16
S0 14
2B1
10
2B2
11
2B3
12
2B4
13
1A 7
2A 9
2OE 15
CV298
4.7U_0603_6.3V6K~D
1
2
RV392 0_0402_5%~D
@
1 2
CV297
0.1U_0402_16V4Z~D
1
2
G
D
S
QV25
SI2301CDS-T1-GE3_SOT23-3~D
2
13
RV387
47K_0402_5%~D
12
RV380
100K_0402_5%~D
12
CV318
10P_0402_50V8J~D
@
1
2
CV294
0.1U_0402_16V4Z~D
1
2
D
G
S
QV27
SSM3K7002F_SC59-3~D
13
2
CV288
0.1U_0402_16V4Z~D
1
2
CV301
4.7U_0805_10V4Z~D
1
2
CV292
0.1U_0402_16V4Z~D
1
2
RV389 0_0402_5%~D
@
1 2
CV299
0.1U_0402_16V4Z~D
1
2
CV303
0.1U_0402_16V4Z~D
1
2
CV320
10P_0402_50V8J~D
@
1
2
LV34
FBMA-L11-201209-221LMA30T_0805
@
1 2
RV400 0_0402_5%~D@
1 2
RV374 0_0402_5%~D
1 2
CV304
.047U_0402_16V7K~D
1
2
CV322
10P_0402_50V8J~D
@
1
2
CV321
10P_0402_50V8J~D
@
1
2
RV3910_0402_5%~D
1 2
RV386
10K_0402_5%~D
@
12
UV27
PI3LVD1012BE_BQSOP80
GND1
3VDD1 4
GND2
13
GND3
20
GND4
21
GND6
38
GND7
52
GND8
74
OE2#
25
VDD2 10
VDD3 19
VDD4 22
VDD5 28
GND5
31
VDD6 37
VDD7 47
VDD8 69
0B1
2
1B1
1
0B2
80
1B2
79
2B1
78
3B1
77
2B2
76
3B2
75
4B1
73
5B1
72
4B2
71
5B2
70
6B1
68
7B1
67
6B2
66
7B2
65
8B1
64
9B1
63
8B2
62
9B2
61
SLE1 16
A0 5
A1 6
A2 8
A3 9
SEL2 34
A4 11
A5 12
A6 14
A7 15
A8 17
A9 18
A10 23
A11 24
A12 26
A13 27
A14 29
A15 30
A16 32
A17 33
A18 35
A19 36
10B1
60
11B1
59
10B2
58
11B2
57
12B1
56
13B1
55
12B2
54
13B2
53
14B1
51
15B1
50
14B2
49
15B2
48
16B1
46
17B1
45
16B2
44
17B2
43
18B1
42
19B1
41
18B2
40
19B2
39
OE1#
7
RV373
0_0402_5%~D
1 2
CV319
10P_0402_50V8J~D
@
1
2
UV29
SN74CB3Q3253PWR_TSSOP16
1B2
51B1
6
1OE
1
S1 2
GND 8
1B3
4
1B4
3
VCC 16
S0 14
2B1
10
2B2
11
2B3
12
2B4
13
1A 7
2A 9
2OE 15
RV3930_0402_5%~D @
1 2
QV3B
DMN66D0LDW-7_SOT363-6~D
34
5
CV291
10U_0805_10V4Z~D
1
2
CV302
0.1U_0402_16V4Z~D
1
2
CV293
0.1U_0402_16V4Z~D
1
2
RV378 0_0402_5%~D
1 2
RV377
0_0402_5%~D
1 2
RV383
0_0402_5%~D
1 2
G
D
S
QV28
SI2301CDS-T1-GE3_SOT23-3~D
2
1 3
QV3A
DMN66D0LDW-7_SOT363-6~D
61
2
JLVDS1
JAE_FI-TD44SB-E-R750~D
CONN@
19 19
18 18
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
99
88
77
66
55
44
33
22
11
GND7
51 GND8
52 GND9
53 GND10
54
20 20
21 21
22 22
24 24
23 23
25 25
26 26
27 27
28 28
29 29
30 30
31 31
32 32
33 33
34 34
35 35
36 36
37 37
38 38
39 39
40 40
41 41
42 42
43 43
44 44
GND6
50
GND5
49
GND4
48
GND3
47
GND2
46
GND1
45
GND11
55
UV30
SN74CB3Q3253PWR_TSSOP16
1B2
51B1
6
1OE
1
S1 2
GND 8
1B3
4
1B4
3
VCC 16
S0 14
2B1
10
2B2
11
2B3
12
2B4
13
1A 7
2A 9
2OE 15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AD_BID0
CLK_PCI_LPC
ECAGND
EC_SMB_DA2
EC_SMB_CK2
EN_WOL#
EC_ESB_DAT
CPU1.5V_S3_GATE
PCH_PWR_EN
H_PROCHOT#_EC
BATT_CHG_LED#
TH_OVERT#_EC
ON/OFF
EC_SCI#
M_THERMAL#
BKOFF#
EAPD#_R
PM_SLP_S4#_R
EN_CAM
MXM1_FAN_FB
PCH_RSMRST#
ADP_I
EC_RST# RST#
LPC_AD1
PLT_RST#
SERIRQ
LPC_AD2
LPC_AD3
LPC_AD0
LPC_FRAME#
TP_DATA
EC_SMB_CK1
BKOFF#
EC_SMI#
EC_SMB_DA1
EC_SCI#
BEEP#
TP_CLK
PCH_PWROK EC_ON
PM_SLP_S5#_R
PM_SLP_S3#_R
ECAGND
SYSON
AD_BID0
IMVP_VR_ON
KB_RST#
GATEA20
SYSTEM_FAN_FB
BATT_TEMP
EC_RST#
E51TXD_P80DATA
E51RXD_P80CLK
EN_WOL#
EC_MUTE#
BATT_LOW_LED#
EC_SMB_DA2
+V18R
DEPOP#
EC_SMB_DA1
EC_SMB_CK1
EC_MUTE#
EC_SMI#
KSO1
KSO2
EC_ESB_CLK
EC_ESB_DAT
KSO[0..17]
LID_SW _IN#
PS_ID
DEPOP#_EC
DEPOP#
KSI[0..7]
EAPD#_R
EC_ESB_CLK_R
KSI3_EC
KSI1_EC
KSI0_EC
KSI6_EC
KSI7_EC
KSI4_EC
KSO15_EC
KSI2_EC
KSI5_EC
KSO4_EC
KSO8_EC
KSO14_EC
KSO13_EC
KSO12_EC
KSO9_EC
KSO1_EC
KSO0_EC
KSO3_EC
KSO6_EC
KSO2_EC
KSO10_EC
KSO11_EC
KSO7_EC
KSO5_EC
EC_SMB_CK2
MXM1_FAN_PWM
PCIE_WAKE#_EC
CLK_PCI_LPC
EC_ESB_CLK_R
SYSTEM_FAN_PWM
SG_AMD_BKL
HDA_SDO
LID_SW _IN#
CAPS_LED#
SUSPWRDNACK
ACIN
PBTN_OUT#
SUSP#
EC_ESB_CLK
LCD_BKL_EN
HDMI_IN_CAB_DET#
HDMI_IN_SELECT#
PWRSHARE_OE#
DP_MXM_CARD_SEL
RST#
USB_PWR_EN#
EC_ESB_CLK
EC_ESB_DAT
TL_ENVDD
TH_OVERT#_EC
HDMI_TOGGLE
EC_AC_BAT#
TP_DATA
TP_CLK
EC_ESB_CLK
+3VALW_EC +EC_VCCA
ECAGND
VCIN0_PH
VCIN1_PH
VCOUT0_PH#
H_PROCHOT#
H_PROCHOT#_EC
USBCHG_DET_PWR_EN#
USBCHG_DET_EC#
USBCHG_DET_EC#
ACOFF
PCH_DPWROK
WLES ON/OFF LED#
EN_TPLED#
ENBKL
M_THERMAL#
EC_ENVDD
LCD_TEST
IMVP_PWRGD
PWRSHARE_EN_EC#
3V_F347_ON
KB_DET#_EC
KSO16_EC
KSO17_EC
KSO17_EC
KSO16_EC
KSO17
KSO16
EC_INV_PWM
DEPOP#_EC
EC_LID_OUT#
HDMI_SW
HDMI_OUT_EN
KSO4
KSO6
KSO7
KSO5
KSI6_EC
KSI7_EC
KSI4_EC
KSI5_EC
KSI6
KSI7
KSI4
KSI5
KSO8_EC
KSO9_EC
KSO10_EC
KSO11_EC
KSO8
KSO9
KSO10
KSO11
KSO1_EC
KSO0_EC
KSO3_EC
KSO2_EC
KSO1
KSO0
KSO3
KSO2
KSO15_EC
KSO14_EC
KSO13_EC
KSO12_EC
KSO15
KSO14
KSO13
KSO12
KSI3_EC
KSI1_EC
KSI0_EC
KSI2_EC
KSI3
KSI1
KSI0
KSI2
KSO4_EC
KSO6_EC
KSO7_EC
KSO5_EC
FB_CLAMP
FB_CLAMP_TGL_REQ#
EC_PECI
DGPU_HOLD_RST#
DGPU_PWROK
DGPU_PWR_EN
PCH_PWROK
HDMI_IN_EN
HDMI_IN_OUT_DDC
HDMI_IN_OUT_HPD
VPK_DET#
VPK_EN
PWR_LED#
+3VALW_EC +3VALW_EC
+3VALW_EC
+3VALW_EC
+3VS
+3VALW_EC
+5VS
+3VALW
+3VLP
+3VALW_EC
+3VLPVL
EC_SMB_DA2_R<37>
DEPOP# <45>
MXM1_FAN_FB<53>
CLK_PCI_LPC<18>
SYSTEM_FAN_FB<54>
CAPS_LED# <53>
IMVP_VR_ON <62>
PBTN_OUT# <6,17>
E51RXD_P80CLK<50>
EC_SMI#<21>
TH_OVERT#<29>
PM_SLP_SUS# <17>
LPC_AD2<19,51>
PCH_PWR_EN <35,56>
KB_RST#<21>
LPC_AD1<19,51>
PCH_PWROK<17>
ACIN <17,29,47,57,63>
TP_CLK <53>
BATT_LOW_LED# <47>
LCD_BKL_EN <33>
EN_WOL# <44>
PLT_RST#<6,17,44,51,53>
PM_SLP_S3#<17,47>
EC_MUTE# <45>
PM_SLP_S5#<17,47>
KSI[0..7]<53>
PCIE_WAKE# <17,44,51>
ADP_I <57,63>
TP_DATA <53>
BEEP# <45>
SERIRQ<19>
HDA_SDO <16>
BKOFF# <40,42>
BATT_TEMP <57,63>
LPC_AD0<19,51>
PS_ID<57>
PM_SLP_S4# <17>
EC_SMB_CK1<29>
EC_SCI#<21>
EC_SMB_DA2<19,40,53,54>
EC_SMB_CK2<19,40,53,54>
LPC_FRAME#<19,51>
CPU1.5V_S3_GATE <10>
LID_SW _IN# <19,47,48,53>
PCH_RSMRST# <17>
KSO[0..17]<53>
EC_SMB_DA1<29>
SYSTEM_FAN_PWM <54>
H_PECI <6,21>
EN_CAM <42>
E51TXD_P80DATA<50>
EAPD# <45>
ON/OFF <55>
SUSPWRDNACK<17>
EC_SMB_CK2_R<37>
MXM1_FAN_PWM <53>
BATT_CHG_LED# <47>
LPC_AD3<19,51>
SUSP# <10,56,59,61>
SG_AMD_BKL<17,42>
SYSON <56,59,60>
EC_ON <58>
GATEA20<21>
HDMI_IN_SELECT#<33,42>
DP_MXM_CARD_SEL <30,32>
PWRSHARE_OE# <52>
HDMI_IN_CAB_DET#<37>
HDMI_TOGGLE<37>
TL_ENVDD <40,42>
EC_AC_BAT# <29>
USB_PWR_EN# <52,53>
VCIN0_PH <57>
VCIN1_PH <57>
VCOUT0_PH# <58>
VR_HOT# <62>H_PROCHOT#<6,63>
ECAGND <57>
USBCHG_DET_D <58>
USBCHG_DET#<52>
ACOFF<63>
PCH_DPWROK <17>
WLES ON/OFF LED#<53>
EN_TPLED# <48>
ENBKL <40,42>
ODD_EJECT# <50>
M_THERMAL# <12,13,14,15>
EC_ENVDD <33,42>
LCD_TEST <33,42>
IMVP_PWRGD <6,17,62>
PWRSHARE_EN_EC# <52>
3V_F347_ON <47>
KB_DET# <53>
EC_INV_PWM <42>
EC_LID_OUT# <19>
HDMI_OUT_EN <35>
HDMI_SW <35>
FB_CLAMP<29>
FB_CLAMP_TGL_REQ#<29>
DGPU_HOLD_RST#<17>
DGPU_PWROK<29,30>
DGPU_PWR_EN<29,56>
HDMI_IN_EN <37>
HDMI_IN_OUT_DDC<35>
HDMI_IN_OUT_HPD <35>
VPK_DET# <53>
VPK_EN <53>
PWR_LED#
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
EC ENE-KB9012QF,KC3810
Custom
40 61Friday, June 22, 2012
2012/06/22 2013/06/21
1.0 (MP)
0.3 (ST)
0.4 (QT)
0.2 (PT)
BOARD ID Table
Board
ID
0
1
2
3
4
5
6
7
PCB
Revision
0.1 (SSI)
8.2K +/- 5%
Rb
0
100K +/- 5%
56K +/- 5%
33K +/- 5%
18K +/- 5%
PCH_PWR_EN H_PROCHOT#_EC need add
Reserve for
EMI please
close to UE1
20mil
Ra
Rb
Board ID
Please place RE74
close to EC with in 750mil
Compal Electronics, Inc.
60 mil
Reserve for EMI
please close to UE2
Reserved for KB9012
*
CE46
0.1U_0402_16V4Z~D
1
2
RE61 0_0402_5%~D
1 2
LE3
FBMA-L11-160808-800LMT_0603
1 2
LPC & MISC
Int. K/B
Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
UE1
KB9012QF-A3_LQFP128_14X14
GATEA20/GPIO00
1
KBRST#/GPIO01
2
SERIRQ
3
LPC_FRAME#
4
LPC_AD3
5
PM_SLP_S3#/GPIO04
6
LPC_AD2
7
LPC_AD1
8
EC_VDD/VCC 9
LPC_AD0
10
GND/GND
11
CLK_PCI_EC
12
PCIRST#/GPIO05
13
PM_SLP_S5#/GPIO07
14
EC_SMI#/GPIO08
15
GPIO0A
16
GPIO0B
17
GPIO0C
18
GPIO0D
19
EC_SCII#/GPIO0E
20
GPIO0F 21
EC_VDD/VCC 22
BEEP#/GPIO10 23
GND/GND
24
EC_INVT_PW M/GPIO11
25
GPIO12 26
ACOFF/GPIO13 27
FAN_SPEED1/GPIO14
28
EC_PME#/GPIO15
29
EC_TX/GPIO16
30
EC_RX/GPIO17
31
PCH_PW ROK/GPIO18
32
EC_VDD/VCC 33
SUSP_LED#/GPIO19
34
GND/GND
35
NUM_LED#/GPIO1A
36
EC_RST#
37
GPIO1D
38
KSO0/GPIO20
39
KSO1/GPIO21
40
KSO2/GPIO22
41
KSO3/GPIO23
42
KSO4/GPIO24
43
KSO5/GPIO25
44
KSO6/GPIO26
45
KSO7/GPIO27
46
KSO8/GPIO28
47
KSO9/GPIO29
48
KSO10/GPIO2A
49
KSO11/GPIO2B
50
KSO12/GPIO2C
51
KSO13/GPIO2D
52
KSO14/GPIO2E
53
KSO15/GPIO2F
54
KSI0/GPIO30
55
KSI1/GPIO31
56
KSI2/GPIO32
57
KSI3/GPIO33
58
KSI4/GPIO34
59
KSI5/GPIO35
60
KSI6/GPIO36
61
KSI7/GPIO37
62
BATT_TEMP/AD0/GPIO38 63
AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65
AD3/GPIO3B 66
EC_VDD/AVCC 67
DAC_BRIG/GPIO3C 68
AGND/AGND
69
EN_DFAN1/GPIO3D 70
IREF/GPIO3E 71
CHGVADJ/GPIO3F 72
ENBKL/AD6/GPIO40 73
PECI_KB930/AD7/GPIO41 74
AD4/GPIO42 75
IMON/AD5/GPIO43 76
EC_SMB_CK1/GPIO44
77
EC_SMB_DA1/GPIO45
78
EC_SMB_CK2/GPIO46
79
EC_SMB_DA2/GPIO47
80
KSO16/GPIO48
81
KSO17/GPIO49
82
EC_MUTE#/GPIO4A 83
USB_EN#/GPIO4B 84
CAP_INT#/GPIO4C 85
EAPD/GPIO4D 86
TP_CLK/GPIO4E 87
TP_DATA/GPIO4F 88
FSTCHG/GPIO50 89
BATT_CHG_LED#/GPIO52 90
CAPS_LED#/GPIO53 91
PWR_LED#/GPIO54 92
BATT_LOW _LED#/GPIO55 93
GND/GND
94
SYSON/GPIO56 95
EC_VDD/VCC 96
CPU1.5V_S3_GATE/GPXIOA00 97
WOL_EN/GPXIOA01 98
ME_EN/GPXIOA02 99
EC_RSMRST#/GPXIOA03 100
EC_LID_OUT#/GPXIOA04 101
PROCHOT_IN/GPXIOA05 102
H_PROCHOT#_EC/GPXIOA06 103
VCOUT0_PH/GPXIOA07 104
BKOFF#/GPXIOA08 105
PBTN_OUT#/GPXIOA09 106
PCH_APWROK/GPXIOA10 107
SA_PGOOD/GPXIOA11 108
VCIN0_PH/GPXIOD00 109
AC_IN/GPXIOD01 110
EC_VDD0 111
EC_ON/GPXIOD02 112
GND0
113
ON/OFF/GPXIOD03 114
LID_SW #/GPXIOD04 115
SUSP#/GPXIOD05 116
GPXIOD06 117
PECI_KB9012/GPXIOD07 118
SPIDI/GPIO5B 119
SPIDO/GPIO5C 120
VR_ON/GPIO57 121
XCLKI/GPIO5D
122
XCLKO/GPIO5E
123 V18R 124
EC_VDD/VCC 125
SPICLK/GPIO58 126
PM_SLP_S4#/GPIO59 127
SPICS#/GPIO5A 128
CE35
0.1U_0402_16V7K
1
2
RE45 2.2K_0402_5%~D
1 2
RE57 4.7K_0402_5%~D
1 2
RE36 10K_0402_5%~D
1 2
RE50 47K_0402_5%~D
1 2
RE64 0_0402_5%~D
12
RE86
100K_0402_5%~D
1 2
CE32
0.1U_0402_16V7K
1
2
RE81 0_0402_5%~D
1 2
RE77 0_0402_5%~D
1 2
RE70
0_0402_5%
1 2
RP4
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RE62
0_0402_5%~D
1 2
UE2
KC3810_QFN24_4X4
GPIO0D/PW M1 19
GPIO0B 17
GPIO0A 16
GPIO09 15
GPIO08/CAS_DAT 14
GND
12
GPIO07/CAS_CLK
11
GPIO06
10
GPIO02
6
GPIO00
2
ESB_DAT
4
GPIO05
9
GPIO03
7
ESB_CLK
1
GPIO01
5
GPIO0E/PW M2 20
RST#
3
GPIO04
8
TEST_EN# 13
GPIO0C/PW M0 18
GPIO0F/PW M3 21
GPIO10/ESB_RUN# 22
GPIO11/BaseAddOpt 23
VCC 24
GND
25
CE48
4.7U_0805_10V4Z~D
1
2
RE48 2.2K_0402_5%~D
1 2
RE40
33_0402_5%~D
@
1 2
RP6
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RE115 0_0402_5%~D
1 2
DE83
BAT54CW_SOT323-3
2
3
1
RE53 100K_0402_5%~D
1 2
CE44
.1U_0402_16V7K~D
1
2
RE58 10K_0402_5%~D
1 2
CE43
0.1U_0402_16V4Z~D
1
2
RE47 0_0402_1%
@
1 2
RE49 47K_0402_5%~D
1 2
CE39
22P_0402_50V8J~D
@
1
2
RE116 0_0402_5%~D
1 2
RE37 0_0805_1%
@
1 2
RE76 0_0402_5%~D
1 2
RE66
33_0402_5%~D
@
12
CE31
0.1U_0402_16V7K
1
2
RE85 10K_0402_5%~D
1 2
RE68 0_0402_5%~D
12
RP2
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
CE37
1000P_0402_50V7K
1
2
CE34
0.1U_0402_16V7K
1
2
RE60 10K_0402_5%~D@
1 2
RE74 43_0402_1%
1 2
RP1
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RE63 0_0402_5%~D@
12
RE79 0_0402_5%~D
1 2
RE87
100K_0402_5%~D
12
RE65
10K_0402_5%~D
@
1 2
RE56
47K_0402_5%~D
12
CE45
22P_0402_50V8J~D
@
1
2
CE36
1000P_0402_50V7K
1
2
CE47 100P_0402_50V8J~D
12
RE44
0_0402_5%
KB930@
1 2
RE42 10K_0402_5%~D
1 2
LE44
FBMA-L11-160808-800LMT_0603
1 2
RE89 10K_0402_5%~D
1 2
RE80 0_0402_5%~D
1 2
RE75 0_0402_5%~D
1 2
G
D
S
QE321
SSM3K7002FU_SC70-3~D
2
13
RE38 10K_0402_5%~D
1 2
RP3
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
CE50
0.1U_0402_16V4Z~D
1
2
CE33
0.1U_0402_16V7K
1
2
RE51 10K_0402_5%~D
1 2
D
G
S
QE21
SSM3K7002F_SC59-3~D
@
1
3
2
RE414.7K_0402_5%~D
12
RE59 10K_0402_5%~D
12
D
G
S
QE22
SSM3K7002F_SC59-3~D
1
3
2
RE78 0_0402_5%~D
1 2
RE88
150K_0402_1%~D
1 2
RE354.7K_0402_5%~D
12
RE43 2.2K_0402_5%~D
1 2
RE82 0_0402_5%~D
1 2
RE54 4.7K_0402_5%~D
1 2
CE51 47P_0402_50V8J~D
@
12
RE67
100K_0402_5%~D
1 2
RE55
47K_0402_5%~D
1 2
CE42 100P_0402_50V8J~D
12
RP5
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RE52 1K_0402_1%~D@
1 2
RE46 2.2K_0402_5%~D
1 2
RE114 0_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+AVDDH+AVDDL +DVDDL
+LAN_IO_R
EN_WOL
CLKREQ_LAN#_R
PLT_RST#
PCIE_WAKE#
+DVDDL
CLK_PCIE_LAN
CLK_PCIE_LAN#
PLT_RST#
PCIE_WAKE#
LAN_ACTIVITY# +RBIAS
CLKREQ_LAN#_R
LAN_LINK#_R
LAN_LED2#_R
XTLO
XTLI
PCIE_PTX_GLANRX_P1
PCIE_PRX_GLANTX_N1_C
PCIE_PRX_GLANTX_P1_C
PCIE_PTX_GLANRX_N1
LAN_MDIN3
LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
+AVDDH
+AVDDL
LAN_LINK#_R
+3VALW
B+_BIAS
+LAN_IO
+3VALW
+LAN_IO
+LAN_IO
+LAN_IO
EN_WOL#<43>
PCIE_PRX_GLANTX_P1<20>
PCIE_PRX_GLANTX_N1<20>
PCIE_PTX_GLANRX_P1<20>
PCIE_PTX_GLANRX_N1<20>
CLK_PCIE_LAN<18>
CLK_PCIE_LAN#<18>
LANCLK_REQ#<18>
PLT_RST#<6,17,43,51,53>
PCIE_WAKE#<17,43,51>
LAN_MDIP0 <53>
LAN_MDIN0 <53>
LAN_MDIP1 <53>
LAN_MDIN1 <53>
LAN_MDIP2 <53>
LAN_MDIN2 <53>
LAN_MDIP3 <53>
LAN_MDIN3 <53>
LAN_ACTIVITY#<53>
LAN_LINK#_R<53>
LAN_LED2#_R<53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
41 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
GLAN AR8151 AL1A/ RJ45
W=20milsW=20mils
close to Lan pin9
close to Lan pin34 close to Lan pin6
close to Lan pin31
close to Lan pin22
close to Lan pin13
close to Lan pin19
W=20mils
close to Lan pin37
close to Pin 1
1A
The pull-up resisters might not be
necessory due to existence
on PCH side.
close to Pin 16
W=40mils W=40mils
W=40mils
CL27
0.1U_0402_16V7K~D
1
2
CL36
0.1U_0402_25V6
1
2
RL15
4.7K_0402_5%~D
12
CL34
0.1U_0402_16V7K~D
1
2
RL10
4.7K_0402_5%~D
12
YL1
25MHZ_10PF_7V25000014
OSC
1
OSC
3
GND 2
GND 4
RL19
1.5M_0402_5%~D
1 2
CL53
1U_0402_6.3V6K~D
1
2
CL29
0.1U_0402_16V7K~D
1
2
CL32
0.1U_0402_16V7K~D
1
2
UL1
E2201-BL3A-R_QFN40_5X5
RX_P
35
VDD33 1
TX_P
30
TX_N
29
RX_N
36
TRXP0 11
TRXN0 12
TRXP1 14
TRXN1 15
RBIAS 10
LX 40
LED_0
38
LED_1
39
NC
28
TESTMODE
27
SMCLK
25
SMDATA
26
WAKE#
3
PERST#
2
LED_2
23
REFCLK_P
33
REFCLK_N
32
AVDDL 31
AVDDL 34
AVDDL_REG 6
AVDDH 22
AVDDH_REG 9
PPS 24
DVDDL_REG 37
ISOLAT#
5
CLKREQ#
4
GND
41
XTLO
7XTLI
8
AVDD33 16
TRXP2 17
TRXN2 18
AVDDL 19
TRXP3 20
TRXN3 21
AVDDL 13
CL54
4.7U_0603_6.3V6K~D
1
2
RL11
4.7K_0402_5%~D
12
RL16
0_0805_5%~D
1 2
RL18
10K_0402_5%~D
1 2
CL51
15P_0402_50V8J~D
1
2
RL17
470K_0402_5%~D
1 2
CL24
10U_0603_6.3V6M~D
1
2
RL29
5.1K_0402_1%~D
1 2
RL12 0_0402_5%~D
12
CL52
15P_0402_50V8J~D
1
2
CL4 0.1U_0402_16V7K~D
12
CL25
10U_0603_6.3V6M~D
1
2
RL14
2.37K_0402_1%~D
1 2
CL41
1U_0402_6.3V6K~D
1
2
RL28
0_0402_5%
12
G
D
S
QL2
SSM3K7002FU_SC70-3
2
13
CL31
0.1U_0402_16V7K~D
1
2
CL23
1U_0402_6.3V6K~D
1
2
CL20
1U_0402_6.3V6K~D
1
2
RL7
0_0402_5%~D
12
CL50
0.1U_0402_16V7K~D
1
2
CL21
1000P_0402_50V7K~D
1
2
RL13 30K_0402_5%
1 2
CL28
0.1U_0402_16V7K~D
1
2
CL39
1U_0402_6.3V6K~D
1
2
G
D
S
QL1
FDC655BN_NL_SSOT6~D
1
2
3
45
6
CL33
1U_0402_6.3V6K~D
1
2
CL35
1U_0402_6.3V6K~D
1
2
CL26
0.1U_0402_16V7K~D
1
2
CL30
0.1U_0402_16V7K~D
1
2
CL1 0.1U_0402_16V7K~D
12
CL22
0.1U_0402_16V7K~D
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
MIC2-L
MIC2-R
HP1_A_R
HP1_A_L HP1_A_L_C
HP2_D_R
HP2_D_L
HP2_D_R1_JK
HP1_A_R_L
HP1_A_L_L
HP2_D_L_R
LINEIN_B_L_C
LINEIN_B_R_C
BEEP_C#
PCH_SPKR_C
HP1_A_L_L
HP2_D_R_R
HP2_D_R_R
HP2_D_L_R
PC_BEEP
HP1_A_R_L
HP2_D_L
HP2_D_R
MIC2-VREFO-L MIC_B_PLUG#
HP1_A_R
HP1_A_L
LINE2-VREFO
MIC2-R
MIC2-L
RING2
SLEEVE
MIC2-VREFO-R
DEPOP#_R
LINE_B_R_R
LINE_B_L_R
HDA_SDIN0_R
HPOUT-JD
HP2_D_L1_JK
HPOUT2-JD
HPOUT-JD
LINE_B_L_R
LINE_B_R_R
MIC_B_PLUG#
HPOUT2-JD
GPIO3
LINE2-VREFO
LINE2-VREFO
RING2
HP1_A_L_C
HP2_D_L1_JK
HP2_D_R1_JK
HP1_A_R_C
SLEEVE
HP_MUTE#
HP_MUTE#
MIC2-VREFO-L
MIC2-VREFO-R
LINE_B_L_RR
LINE_B_R_RR
HP_MUTE#
PC_BEEP
EC_MUTE#
EAPD#
SPK_MUTE#
DEPOP#
GPIO3
HP_MUTE#
HP1_A_R_C
SLEEVE
HPOUT2-JD
MIC_B_PLUG#
HPOUT-JD
LINEIN_B_R_C
LINEIN_B_L_C
RING2
+3.3V_AVDD
+3.3V_AVDD
+3VS +3V_DVDD +3.3V_AVDD+3V_DVDD
+3V_DVDD
+3.3V_AVDD
+5VS
+3V_DVDD
+3V_DVDD
+3V_DVDD
+3.3V_AVDD
+3V_DVDD
HDMI_IN_AUDIO_CODEC<37>
BEEP#<43>
HDA_SPKR<16>
PCH_AZ_CODEC_BITCLK<16>
PCH_AZ_CODEC_RST#<16>
PCH_AZ_CODEC_SDIN0<16>
PCH_AZ_CODEC_SYNC<16>
DMIC_CLK <33,42>
DMIC0 <33,42>
EAPD# <43>
I2S_DAT/SPDIF_IN <37>
PCH_AZ_CODEC_SDOUT<16>
INT-SPK-R <46>
INT-SPK-L <46>
EC_MUTE# <43>
SPK_MUTE#<46>
DEPOP# <43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
HD Audio ALC3661
Custom
42 61Friday, June 22, 2012
2012/06/22 2013/06/21
S1 (Out + In) : Front L/R + HP1 + MIC (auto-sense)
S3 (Out) : Rear L/R
Setting the Turn-Off Time:
Ton (ms) = 0.02 x Cset (pF)
S2 (Out) :Center + HP2
Place close to Jack
Setting the Turn-Off Time:
Ton (ms) = 0.02 x Cset (pF)
Compal Electronics, Inc.
Close to Pin39
Setting the Turn-Off Time:
Ton (ms) = 0.02 x Cset (pF)
Place close to Jack
Place close to Jack
Place close to Jack
Place close to Jack
AGNDGND
AGNDGND
CA1
4.7U_0805_25V6-K
12
RA15 100_0402_1%
1 2
CA13
10U_0805_10V4Z~D
1 2
UA2
MAX9892ERT+T_UCSP6~D
SET
B3
/MUTE
B1 INR
A3
INL
A1
VDD B2
GND
A2
LA2
0_0603_5%~D
1 2
RA77 18_0402_5%~D
1 2
RA55 100_0402_1%
1 2
LA1
FBMA-L11-201209-221LMA30T_0805
12
CA3
10U_0805_10V4Z~D
1
2
RA80
75_0402_1%~D
1 2
DA6
AZ5125-02S.R7G_SOT23-3
2
3
1
RA16 100_0402_1%
1 2
RA61
100K_0402_5%~D
1 2
CA58 0.1U_0402_16V4Z~D
1 2
RA76 18_0402_5%~D
1 2
CA30
0.1U_0402_10V6K~D
1
2
CA15
22P_0402_50V8J~D
1
2
RA14
20K_0402_1%~D
12
RA60
0_0402_5%~D
1 2
CA9
10U_0805_10V4Z~D
1
2
DA10
BAT54AW_SOT323-3~D
1
3
2
UA3 MAX9892ERT+T_UCSP6~D
SET
B3
/MUTE
B1 INR
A3
INL
A1
VDD B2
GND
A2
RA57 0_0402_5%
1 2
CA40
0.1U_0402_16V4Z~D
12
RA11
10K_0402_1%
1 2
CA5
0.1U_0402_10V6K~D
1 2
CA61 100P_0402_50V8J~D
1
2
LA6
0_0603_5%~D
1 2
+
CA20
100U_B3_6.3VM_R55M
1
2
CA38 0.1U_0402_16V4Z~D
1 2
RA47 0_0402_5%~D
1 2
CA23
10U_0805_10V4Z~D
1
2
CA12
4.7U_0805_25V6-K
12
CA18
0.1U_0402_10V6K~D
1
2
CA64
100P_0402_50V8J~D
1
2
RA17
10K_0402_1%
1 2
CA29
0.1U_0402_10V6K~D
1
2
RA59
100K_0402_5%~D
1 2
CA60 100P_0402_50V8J~D
1
2
RA54 100_0402_1%
1 2
CA4
0.1U_0402_10V6K~D
1
2
CA63
100P_0402_50V8J~D
1
2
RA82
100K_0402_5%~D
1 2
LA4
0_0603_5%~D
1 2
UA7 MAX9892ERT+T_UCSP6~D
SET
B3
/MUTE
B1 INR
A3
INL
A1
VDD B2
GND
A2
LA3
0_0603_5%~D
1 2
LA5
0_0603_5%~D
1 2
RA7 100_0402_1%
1 2
CA68 0.1U_0402_16V7K
1 2
RA78 18_0402_5%~D
1 2
G
G
JHP1
C-H_13-18200610CP
CONN@
6
1
3
4
5
2
7
8
DA12
AZ5125-02S.R7G_SOT23-3
2
3
1
CA22
1U_0402_6.3V6K~D
1
2
CA16
1U_0402_6.3V6K~D
1
2
CA19
2.2U_0402_6.3V6M~D
1
2
CA59
0.1U_0402_10V6K~D
1
2
CA62
100P_0402_50V8J~D
1
2
RA8
0_0402_5%
1 2
CA10
0.1U_0402_10V6K~D
1
2
RA4 0_0402_5%
1 2
RA48 0_0402_5%~D
1 2
CA14
0.1U_0402_16V4Z~D
12
RA62
10K_0402_5%~D
@
1 2
CA21 4.7U_0805_25V6-K
1 2
RA363
2.2K_0402_5%~D
@
12
RA1 0_0805_5%~D
1 2
RA360
2.2K_0402_5%~D
12
DA7
AZ5125-02S.R7G_SOT23-3
2
3
1
CA70 0.1U_0402_16V7K
1 2
RA2 0_0402_5%
1 2
RA79 18_0402_5%~D
1 2
CA2
0.1U_0402_10V6K~D
1
2
CA27
0.1U_0402_10V6K~D
1
2
CA8
0.1U_0402_10V6K~D
1
2
DA8
AZ5125-02S.R7G_SOT23-3
2
3
1
RA44 0_0402_5%~D
1 2
RA9
39.2K_0402_1%
1 2
CA24 4.7U_0805_25V6-K
1 2
DA11
AZ5125-02S.R7G_SOT23-3
2
3
1
RA6
22_0402_5%
1 2
UA1
ALC3661-CG_MQFN48_6X6~D
AVSS1
22
HVDD
23
CPVEE
20
MIC2-VREFO
1
VRP
38 VREF
41 LDO-CAP
40
FRONT-L 43
FRONT-R 44
LDO-IN
39
REGREF
10
AVSS2
42
CBP
24
DVDD-IO
7
CBN
21
JDREF
35 LFE 18
CEN 19
SURR-L 26
SURR-R 27
EAPD 14
LINE1-L 45
LINE2-IN-R/SLEEVE 32
LINE2-IN-L/RING2 31
MIC1-R 37
MIC1-L/MIC-CAP 36
MIC2-R 48
MIC2-L 47
LINE1-R 46
LINE2-VREFO
29 SENSE A 34
SENSE B 33
SPDIF-OUT 15
PCBEEP 2
RESETB
6SYNC
9
DVDD-IO-CP
25
SDATA-IN
8
DVDD
11
GPIO/DMIC-CLK 12
GPIO1/DMIC-DATA 13
CPVREF
28
BCLK
5SDATA-OUT
4
Thermal PAD
49
MIC1-VREFO
30
SPDIF-in 16
GPIO2/Combo-Jack1 17
GPIO3/Combo-Jack2 3
CA39 0.1U_0402_16V4Z~D
1 2
RA81
75_0402_1%~D
1 2
DA3
AZ5125-02S.R7G_SOT23-3
2
3
1
LA7
0_0603_5%~D
1 2
CA17
10U_0805_10V4Z~D
1
2
G
G
JHP2
C-H_13-18200610CP
CONN@
6
1
3
4
5
2
7
8
CA71 0.1U_0402_16V7K
1 2
CA69 0.1U_0402_16V7K
1 2
RA13
10K_0402_1%
1 2
CA37
0.1U_0402_10V6K~D
1
2
G
G
JHP3
C-H_13-18200610CP
CONN@
6
1
3
4
5
2
7
8
RA12
5.1K_0402_1%
1 2
DA9
BAT54CW_SOT323-3
2
3
1
RA3 0_0402_5%
1 2
RA5 100_0402_1%
1 2
CA11
0.1U_0402_10V6K~D
1
2
RA45 0_0402_5%~D
1 2
RA361
2.2K_0402_5%~D
12
CA25
0.1U_0402_16V4Z~D
12
RA362
2.2K_0402_5%~D
@
12
CA35
10U_0603_6.3V6M~D
1
2
CA28
0.1U_0402_10V6K~D
1
2
CA65
100P_0402_50V8J~D
1
2
CA31
10U_0603_6.3V6M~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPK_L1-_CONN
SPK_R2+_CONN
BSPR
GIN0
AMP_LEFT_C
PLIMIT
OUTPR
GIN1
BSPL
OUTNR
GIN1GIN0
OUTPL
OUTNL
BSNR
BSNL
OUTNL
OUTNR
OUTPR
OUTPL
EAPD_R
AMP_RIGHT_C
+GVDD
SPK_L2+_CONN
SPK_R1-_CONN
SPK_CD_L
SPK_CD_R
+AVCC
+PVDD
SPK_L1-_CONN
SPK_L2+_CONN
SPK_R1-_CONN
SPK_R2+_CONN
+PVDD
+AVCC
+GVDD
+GVDD
B+
+3VALW
+5VS
B+
SPK_MUTE#<45>
INT-SPK-L<45>
INT-SPK-R<45>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
Speaker AMP/CardReaser B
Custom
43 61Friday, June 22, 2012
2012/06/22 2013/06/21
Speaker amp impedance of JBL is 4 ohm.
Speaker Connector
15 mils trace
40mil
Close to UA2
Pin7,15,16,27,28
5A/120ohm/100MHz
5A/120ohm/100MHz
5A/120ohm/100MHz
5A/120ohm/100MHz
0
0
GAIN1 GAIN0
1
1 0
0
1 1
20dB
26dB
32dB
60Kohm
36dB
30Kohm
15Kohm
AV(inv) INPUT
IMPEDANCE
9Kohm
TPA3113 for Speaker
CA49
0.22U_0603_25V7K
1 2
CA52
0.22U_0603_25V7K
1 2
LA8
FBMA-L11-160808-121LMA30T_0805
1 2
RA71
100K_0402_5%
12
CA44
1U_0603_25V6K
12
CA48
0.22U_0603_25V7K
1 2
CA41
10U_1206_25V6M
1
2
RA67
28.7K_0402_1%
12
CA46
1U_0603_25V6K
12
UA8
TPA3113D2PWPR_HTSSOP28
SD#
1
FAULT#
2
LINP
3
LINN
4
GAIN0
5
GAIN1
6
AVCC
7
AGND 8
GVDD 9
PLIMIT 10
RINN
11
RINP
12
NC
13
PBTL 14
PVCCR
15
PVCCR
16
BSPR 17
OUTPR 18
PGND 19
OUTNR 20
BSNR 21
BSNL 22
OUTNL 23
PGND 24
OUTPL 25
BSPL 26
PVCCL
27
PVCCL
28
GND
29
CA33
1000P_0402_50V7K
1
2
RA72
100K_0402_1%
@
1 2
RA64
10K_0402_5%
@
12
CA47
1U_0603_25V6K
12
CA54
0.027U_0402_16V6K
1 2
CA67
470P_0402_50V7K~D
1 2
LA12
HCB2012KF-121T50_0805
1 2
CA34
1000P_0402_50V7K
1
2
CA57
1U_0603_25V6K
12
CA45
1U_0603_25V6K
12
RA69
0_0402_5%
1 2
LA9
HCB2012KF-121T50_0805
1 2
CA55
0.22U_0603_25V7K
1 2
CA43
1U_0603_25V6K
12
CA50
0.027U_0402_16V6K
1 2
CA72
10U_0603_6.3V6M~D
1
2
RA63
240K_0402_1%
1 2
CA36
1000P_0402_50V7K
1
2
CA42
0.1U_0402_25V6K~D
1
2
RA65
240K_0402_1%
1 2
RA68
100K_0402_5%
@
1 2
CA51
0.027U_0402_16V6K
1 2
RA74
100K_0402_1%
1 2
LA11
HCB2012KF-121T50_0805
1 2
RA70
10K_0402_1%
12
RA66
10K_0402_5%
@
12
RA75
100K_0402_1%
1 2
RA83
0_0402_5%
1 2
JSPK1
ACES_50279-0040N-001
CONN@
1
1
2
2
3
3
GND
5
GND
6
4
4
RA73
100K_0402_1%
@
1 2
DA5
AZ5125-02S.R7G_SOT23-3
2
3
1
CA32
1000P_0402_50V7K
1
2
DA4
AZ5125-02S.R7G_SOT23-3
2
3
1
CA56
1U_0603_25V6K
12
CA53
0.027U_0402_16V6K
1 2
CA66
470P_0402_50V7K~D
1 2
LA10
HCB2012KF-121T50_0805
1 2
RA364 10_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI_MOSI
SPI_MOCLK_R
SPI_MOCLK_R
+3.3V_F347_R
BATT_LOW_LED
USB20_N6
USB20_P6
ACIN#
BATT_CHG_LED
SPI_MOCLK
SPI_MOSO
SPI_MOSI
SPI_MOCS#
SLP_S3
ACIN#
BATT_CHG_LED
LID_SW _IN#
SLP_S5
SLP_S3
SPI_MOCS#
I2C_DAT
SPI_MOSO
I2C_CLK
I2C_DAT
BATT_LOW_LED
LID_SW _IN#_D
SLP_S5
I2C_CLK
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
+5VS
+5VALW
+3.3V_F347
+3VALW
B+_BIAS
+3VALW +3.3V_F347
+3.3V_F347
+3.3V_F347
+3.3V_F347
PM_SLP_S5#<17,43>
3V_F347_ON<43>BATT_LOW_LED#<43>
I2C_DAT <48,53>
PM_SLP_S3#<17,43>
ACIN<17,29,43,57,63>
I2C_CLK <48,53>
USB20_P6<20>
BATT_CHG_LED#<43>
USB20_N6<20>
LID_SW _IN# <19,43,48,53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
ELC (1)
Custom
44 61Friday, June 22, 2012
2012/06/22 2013/06/21
We are Green SA00003IR20
Cloase to JP1
place R1564 as close as U602
SMBUS ADDRESSDEVICE
MAXIM - LED
I2C EEPROM
0100 000b
1010 000b
MAXIM - GPIO 0100 001b
W=40mils
STATE
S0 S3 S4 S5
ON ON ON ON
ON ON OFF OFF
AC mode battery full in S5:turn off ELC controller
AC IN
BAT only
+3.3V_F347 behavior
Compal Electronics, Inc.
R22
100K_0402_1%~D
12
R24.7K_0402_5%~D
12
JP1
AMPHE_G846A06201EU
CONN@
11
22
33
44
55
66
GND1 7
GND2 8
C17 0.1U_0402_16V4Z~D
@
1
2
C16 0.1U_0402_16V4Z~D
@
1
2
J11
JUMP_43X118
@
11
2
2
D
G
S
Q2
SSM3K7002F_SC59-3~D
1
3
2
D70
SDMK0340L-7-F_SOD323-2~D
12
C14 0.1U_0402_16V4Z~D
@
1
2
D
G
S
Q7
SSM3K7002F_SC59-3~D
1
3
2
C13 0.1U_0402_16V4Z~D
@
1
2
D
G
S
Q1
SSM3K7002F_SC59-3~D
1
3
2
R34.7K_0402_5%~D
12
C15 0.1U_0402_16V4Z~D
@
1
2
R14 10K_0402_5%~D
1 2
R20
100K_0402_1%~D
1 2
R8
1K_0402_1%~D
1 2
R1015_0402_5%
12
C18 0.1U_0402_16V4Z~D
@
1
2
C2
22P_0402_50V8J~D
1
2
C9 0.1U_0402_16V4Z~D@
1 2
R19
100K_0402_1%~D
12
C5 0.1U_0402_16V4Z~D@
1 2
D
G
S
Q4
SSM3K7002F_SC59-3~D
1
3
2
C23
0.1U_0402_25V6K~D
1
2
R24
100K_0402_1%~D
12
R23
300K_0402_5%~D
1 2
C20
22P_0402_50V8J~D
1
2
U1
C8051F347-GQ_LQFP32_7X7
P0.0 2
P0.1 1
P0.2 32
P0.3 31
P0.4 30
P0.5 29
P0.6 28
P0.7 27
P1.0 26
P1.1 25
P1.2 24
P1.3 23
P1.4 22
P1.5 21
P1.6 20
P1.7 19
VDD
6
D+
4
D-
5
REGIN
7
VBUS
8
RST#/C2CK
9
P3.0/C2D
10
P2.0
18
P2.1
17
P2.2
16
P2.3
15
P2.4
14
P2.5
13
P2.6
12
P2.7
11 GND 3
R17
100K_0402_1%~D
12
R910K_0402_5%
12
C22
4.7U_0603_6.3V6M~D
1
2
C21
0.1U_0402_25V6K~D
1
2
C4
0.1U_0402_16V4Z~D
1
2
R1215_0402_5%
12
R1 0_0603_5%~D
1 2
R21
100K_0402_1%~D
12
R16
100K_0402_1%~D
12
U2
EN25Q80A-100HIP_SO8
CS
1
VCC
8
SO 2
HOLD
7
VSS 4
DI
5
CLK
6
WP
3
R4 0_0402_5%~D
1 2
C1
0.1U_0402_16V4Z~D
1
2
C19
0.1U_0402_16V4Z~D
1
2
C7
0.1U_0402_16V4Z~D
1
2
C12 0.1U_0402_16V4Z~D
@
1
2
R15 10K_0402_5%~D
1 2
C3
1U_0805_10V7
1
2
D
G
S
Q6
SSM3K7002F_SC59-3~D
1
3
2
R25
100K_0402_1%~D
12
D
G
S
Q8
SSM3K7002F_SC59-3~D
1
3
2
R18
100K_0402_1%~D
12
C10
0.1U_0402_16V4Z
1
2
S
G
D
Q3
SI3456DDV-T1-GE3_TSOP6~D
3
6
2
45
1
C6
1U_0805_10V7
1
2
R11 15_0402_5%
1 2
C11 0.1U_0402_16V4Z~D
@
1
2
R13 10K_0402_5%~D
1 2
R7 1K_0402_5%~D
1 2
R6 0_0603_5%~D@
1 2
R5 0_0603_5%~D
1 2
C8 0.1U_0402_16V4Z~D@
1 2
D
G
S
Q5
SSM3K7002F_SC59-3~D
1
3
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LTRON_LED_R_DRV#
LTRON_LED_G_DRV#
LTRON_LED_B_DRV#
EN_TPLED
ALIEN_LED_B_DRV#_1
ALIEN_LED_R_DRV#_1
ALIEN_LED_G_DRV#_1
LID_SW
RTRON_LED_B_DRV#
I2C_CLK
SATA_LED_ACT
HDD_R_7313#
HDD_B
HDD_B_7313#
HDD_G
HDD_G_7313#
TP_LED_B_DRV#
TP_LED_R_DRV#
TP_LED_G_DRV#
LOGO_LED_B_DRV#
RTRON_LED_G_DRV#
I2C_DAT
LTRON_LED_R_DRV#
LTRON_LED_G_DRV#
AD0_2
AD0_0
AD0_1
RTRON_LED_R_DRV#
LOGO_LED_R_DRV#
LOGO_LED_G_DRV#
LID_SW
LOGO_LED_R_DRV#
LOGO_LED_G_DRV#
LOGO_LED_B_DRV#
LED_G_7313#_1
LED_B_7313#_1
LED_R_7313#_1
AD2_2
AD2_1
AD2_0
I2C_CLK
I2C_DAT
PWR_R_7313#
PWR_G_7313#
PWR_B_7313#
HDD_R_7313#
HDD_G_7313#
HDD_B_7313#
SATA_LED_ACT
ALIEN_LED_G_DRV#_1
ALIEN_LED_B_DRV#_1
ALIEN_LED_R_DRV#_1
LID_SW
7313_INT#
HDD_R
LTRON_LED_B_DRV#
RTRON_LED_B_DRV#
RTRON_LED_G_DRV#
RTRON_LED_R_DRV#
LTRON_LED_R_DRV#
LTRON_LED_G_DRV#
LTRON_LED_B_DRV#
+5VS
+3.3V_F347
+3.3V_F347
+5VS
+3.3V_F347
+5VS
B+_BIAS +5VS +5VS_TP_LED
+3.3V_F347
+5VALW
+5VS
I2C_CLK<47,53>
I2C_DAT<47,53>
PCH_SATALED#<16>
EN_TPLED#<43>
LID_SW _IN#<19,43,47,53>
7313_INT#<53>
RTRON_LED_R_DRV# <53>
RTRON_LED_G_DRV# <53>
RTRON_LED_B_DRV# <53>
TP_LED_G_DRV#<53>
TP_LED_B_DRV#<53>
TP_LED_R_DRV#<53>
LED_R_7313#_1 <53>
LED_G_7313#_1 <53>
LED_B_7313#_1 <53>
PWR_R_7313# <53>
PWR_G_7313# <53>
PWR_B_7313# <53>
HDD_R <53>
HDD_B <53>
HDD_G <53> LID_SW <53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
ELC (2)
Custom
45 61Friday, June 22, 2012
2012/06/22 2013/06/21
20mil
TRON LED Board (F) CONN
TRON LED Board (L) CONN
Touchpad LED circuit
L/R Tron, Logo, Alien Head, TP
Indicator, Power
Reference AD2 AD1 AD0 MAX7313
U605
U608
0 1 0
0 1 1
Tron Lights,TP
A-panel,B-Panel Logo
Power Button,
Media and Status LED Color
Compal Electronics, Inc.
U? 1 0 0 Button,
Indicator Brightness
LOGO Board CONN
R37
1.5M_0402_5%~D
12
U3
MAX7313DATG+T_TQFN-EP24_4X4~D
P0 1
P1 2
P2 3
P3 4
P4 5
P5 6
P6 7
P7 8
P8 10
P9 11
P10 12
P11 13
P12
14
P13
15
P14
16
OSC
17
INT#/O16
22
SCL
19
SDA
20
V+ 21
AD0
18
AD1
23
AD2
24
GND
9GND 25
C32
1U_0603_10V4Z~D
1
2
R30
4.7K_0402_1%~D
12
G
D
S
Q15
SSM3K7002FU_SC70-3~D
2
13
S
G
D
Q11
SI3456DDV-T1-GE3_TSOP6~D
3
6
2
45
1
D
G
S
Q12
SSM3K7002F_SC59-3~D
1
3
2
R29
4.7K_0402_1%~D
12
D
G
S
Q13
SSM3K7002F_SC59-3~D
1
3
2
R28
4.7K_0402_1%~D
12
C26
0.1U_0402_16V4Z
1
2
C29
0.1U_0402_16V4Z
1
2
R27
4.7K_0402_1%~D
12
D
G
S
Q14
SSM3K7002F_SC59-3~D
1
3
2
C27
0.1U_0402_16V4Z
1
2
R26
4.7K_0402_1%~D
1 2
R31
4.7K_0402_1%~D
12
JTRONF
ACES_50224-01001-001
CONN@
1
1
2
2
3
3
4
4
GND1
11
GND2
12
5
5
6
6
7
7
8
8
9
9
10
10
U4
MAX7313DATG+T_TQFN-EP24_4X4~D
P0 1
P1 2
P2 3
P3 4
P4 5
P5 6
P6 7
P7 8
P8 10
P9 11
P10 12
P11 13
P12
14
P13
15
P14
16
OSC
17
INT#/O16
22
SCL
19
SDA
20
V+ 21
AD0
18
AD1
23
AD2
24
GND
9GND 25
R36
300K_0402_5%~D
1 2
JLOGO1
ACES_50224-0120N-001
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
G1
13
G2
14
C30
0.1U_0402_16V4Z
1
2
R34
100K_0402_5%~D
12
JTRONL
E-T_4260-F06N-10L
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
GND
7
GND
8
R32
4.7K_0402_1%~D
12
D
G
S
Q9
SSM3K7002F_SC59-3~D
1
3
2
R35
100K_0402_5%~D
12
C33
0.1U_0402_25V6K~D
1
2
D
G
S
Q10
SSM3K7002F_SC59-3~D
1
3
2
R33
4.7K_0402_1%~D
12
C25
0.1U_0402_16V4Z
1
2
D
G
S
Q16
SSM3K7002F_SC59-3~D
1
3
2
C24
0.1U_0402_16V4Z~D
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
FFS_INT2_CONN
SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C
SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C
FFS_INT2_CONN
FFS_INT1
FFS_INT2
PCH_SMBCLK
PCH_SMBDATA
SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
HDD_A_PRE1
HDD_B_PRE0
HDD_A_PRE1
HDD_REXT_SATA
HDD_REXT_SATA
HDD_A_PRE0
HDD_B_PRE0
HDD_B_PRE1
HDD_A_PRE0
HDD_B_PRE1
SATA_PTX_DRX_N1_R
SATA_PTX_DRX_P1_R
SATA_PRX_DTX_P1_RC
SATA_PRX_DTX_N1_RC
SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_RC SATA_PTX_DRX_N1_C
SATA_PRX_DTX_P1_R
SATA_PRX_DTX_N1_R
SATA_PTX_DRX_P1_RC
SATA_PRX_DTX_P1_C
SATA_PRX_DTX_N1_C
+5VS
+3VS
+3VS
+3VS
+3VS
+5VS
+5VS
+5VS
+3VS
+3VS
+3VS
+3VS
SATA_PTX_DRX_P0<16>
SATA_PRX_DTX_N0<16>
SATA_PTX_DRX_N0<16>
SATA_PRX_DTX_P0<16>
FFS_INT2_CONN<50>
HDD_DET#<21>
FFS_INT1<17>
FFS_INT2<21,50>
PCH_SMBCLK<6,12,13,14,15,19,50,51,53>
PCH_SMBDATA<6,12,13,14,15,19,50,51,53>
SATA_PTX_DRX_P1<16>
SATA_PTX_DRX_N1<16>
SATA_PRX_DTX_P1<16>
SATA_PRX_DTX_N1<16>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
SATA HDD1 & HDD2/FFS
Custom
46 61Friday, June 22, 2012
2012/06/22 2013/06/21
Close to JHDD2
Close to JHDD1
Free Fall Sensor
FFS_INT1 connect to PCH GPIO & EC
discuss with BIOS to use which pin
Compal Electronics, Inc.
Pin 20:
PARADE PS8250B:
Reserve RN46, Mount RN12
PERICOM PI3EQX6741ST:
Mount RN46, Reserve RN12
ASMEDIA ASM1466:
Mount RN46, Reserve RN12
Pin 9:
PARADE PS8250B:
Reserve RN11.
PERICOM PI3EQX6741ST:
Reserve RN11
ASMEDIA ASM1466:
Mount RN11 to pull down
CN15 0.01U_0402_16V7K~D
1 2
CN19 0.01U_0402_16V7K~D
1 2
RN11
2K_0402_5%
1 2
CN1
0.1U_0402_16V4Z~D
1
2
CN6 0.01U_0402_16V7K~D
1 2
CN20 0.01U_0402_16V7K~D
1 2
CN23
0.01U_0402_16V7K
1
2
RN3 0_0402_5%@
1 2
RN8 0_0402_5%@
1 2
CN10
0.1U_0402_16V4Z~D
1
2
RN7
0_0402_5%
@
12
RN6
0_0402_5%
@
12
RN10 0_0402_5%@
1 2
C35
10U_0805_10V4Z~D
1
2
CN9 0.01U_0402_16V7K~D
1 2
CN4
1U_0402_6.3V4Z~D
1
2
CN13
1U_0402_6.3V4Z~D
1
2
CN18 0.01U_0402_16V7K~D
1 2
JHDD1
FOX_LD2822F-SAQL6
CONN@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
VCC3.3
8
VCC3.3
9
VCC3.3
10
GND
11
GND
12
GND
13
VCC5
14
VCC5
15
VCC5
16
GND
17
DAS/DSS
18
GND
19
VCC12
20
VCC12
21
VCC12
22
G1 23
G2 24
RN1 0_0402_5%
1 2
CN16 0.01U_0402_16V7K~D
1 2
CN8 0.01U_0402_16V7K~D
1 2
CN60
47P_0402_50V8J~D
1
2
CN5
10U_0805_10V4Z~D
1
2
C34
0.1U_0402_16V4Z~D
1
2
CN12
0.1U_0402_16V4Z~D
1
2
JHDD2
FOX_LD2822F-SAQL6
CONN@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
VCC3.3
8
VCC3.3
9
VCC3.3
10
GND
11
GND
12
GND
13
VCC5
14
VCC5
15
VCC5
16
GND
17
DAS/DSS
18
GND
19
VCC12
20
VCC12
21
VCC12
22
G1 23
G2 24
CN3
0.1U_0402_16V4Z~D
1
2
UN1
PS8520BTQFN20GTR2_TQFN20_4X4
A_INp
1
A_INn
2
REXT 20
A_PRE1
19
B_OUTp
5
VDD 6
B_PRE0 8
A_PRE0 9
NC 10
TEST
18
GND
13 B_INp 11
B_INn 12
B_PRE1
17
A_OUTn 14
A_OUTp 15
VDD 16
GND
3
B_OUTn
4
EPAD
21
EN
7
CN59
47P_0402_50V8J~D
1
2
RN46
0_0402_5%
@
12
CN24
0.1U_0402_25V6K
1
2
RN9 0_0402_5%@
1 2
CN21 0.01U_0402_16V7K~D
1 2
CN7 0.01U_0402_16V7K~D
1 2
CN2
1000P_0402_50V7K~D
1
2
RN5
0_0402_5%
12
CN17 0.01U_0402_16V7K~D
1 2
RN4 0_0402_5%@
1 2
CN11
1000P_0402_50V7K~D
1
2
LNG3DM
UN4
LNG3DMTR_LGA16_3X3~D
VDD_IO
1
NC 2
NC 3
SCL/SPC
4
GND 5
VDD
14
CS
8
INT 1
11
INT 2
9
RES 10
GND 12
SDO/SA0
7
SDA / SDI / SDO
6
RES 13
RES 16
RES 15
RN12
5.1K_0402_1%
1 2
CN14
10U_0805_10V4Z~D
1
2
CN22 0.01U_0402_16V7K~D
1 2
RN2 0_0402_5%@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ODD_DA#_R
ODD_EN
FFS_INT2 FFS_INT2_CONN
ODD_A_PRE1
ODD_REXT_SATA
ODD_A_PRE0
ODD_B_PRE0
ODD_B_PRE1
SATA_PRX_DTX_N2_R
SATA_PRX_DTX_P2_R
SATA_PTX_DRX_P2_R
SATA_PTX_DRX_N2_R
ODD_A_PRE1
ODD_B_PRE0
ODD_REXT_SATA
ODD_A_PRE0
ODD_B_PRE1
SATA_PTX_DRX_P2_C
SATA_PTX_DRX_N2_RC SATA_PTX_DRX_N2_C
SATA_PRX_DTX_P2_RC
SATA_PTX_DRX_P2_RC
SATA_PRX_DTX_N2_RC
SATA_PRX_DTX_P2_C
SATA_PRX_DTX_N2_C
mSATA_A_PRE1
mSATA_REXT_SATA
mSATA_A_PRE0
mSATA_B_PRE0
mSATA_B_PRE1
mSATA_A_PRE1
mSATA_B_PRE0
mSATA_REXT_SATA
mSATA_A_PRE0
mSATA_B_PRE1
SATA_PRX_DTX_N3_RC
SATA_PTX_DRX_N3_RC
SATA_PTX_DRX_P3_RC
SATA_PRX_DTX_P3_RC SATA_PRX_DTX_P3_C
SATA_PRX_DTX_N3_C
SATA_PTX_DRX_N3_C
SATA_PTX_DRX_P3_C
SATA_PTX_DRX_N3_R
SATA_PTX_DRX_P3_R
SATA_PRX_DTX_P3_R
SATA_PRX_DTX_N3_R
ODD_DA#_R
SATA_PRX_DTX_P2_C
SATA_PRX_DTX_N2_C
SATA_PTX_DRX_N2_C
SATA_PTX_DRX_P2_C
FFS_INT2_CONN
SATA_PRX_DTX_N3_C
EC_TX_DAT
PCH_SMBDATA
PCH_SMBCLK
SATA_PRX_DTX_P3_C
EC_RX_CLK
SATA_PTX_DRX_N3_C
SATA_PTX_DRX_P3_C
+3VS
+3VS
+5VS
B+_BIAS
+5VS_ODD
+5VS_ODD
+5VS
+3VS
+1.5VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+5VS_ODD
+5VS
+3VS +1.5VS
+3VS
E51TXD_P80DATA<43>
E51RXD_P80CLK<43>
ODD_EN#<21>
FFS_INT2<21,49>
ODD_EJECT#<43>
PCH_SMBDATA <6,12,13,14,15,19,49,51,53>
PCH_SMBCLK <6,12,13,14,15,19,49,51,53>
FFS_INT2_CONN <49>
SATA_ODD_PRX_DTX_P2<16>
SATA_ODD_PRX_DTX_N2<16>
SATA_ODD_PTX_DRX_P2<16>
SATA_ODD_PTX_DRX_N2<16>
MSATA_PTX_DRX_N3<16>
MSATA_PTX_DRX_P3<16>
MSATA_PRX_DTX_P3<16>
MSATA_PRX_DTX_N3<16>
ODD_DA#<17>
ODD_DETECT#<21>
FFS_INT2_CONN<49>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
SATA ODD/mSATA
Custom
47 61Friday, June 22, 2012
2012/06/22 2013/06/21
Placea caps. near JP2 CONN.
ODD Redriver
SATA ODD Conn.
Placea caps. near ODD CONN.
m-SATA Re-Driver
ODD power
Placea caps. near JP2 CONN.
Compal Electronics, Inc.
Pin 20:
PARADE PS8250B:
Reserve RN18, Mount RN25
PERICOM PI3EQX6741ST:
Mount RN18, Reserve RN25
ASMEDIA ASM1466:
Mount RN18, Reserve RN25
Pin 9:
PARADE PS8250B:
Reserve RN24.
PERICOM PI3EQX6741ST:
Reserve RN24
ASMEDIA ASM1466:
Mount RN24 to pull down
Pin 20:
PARADE PS8250B:
Reserve RN35, Mount RN42
PERICOM PI3EQX6741ST:
Mount RN35, Reserve RN42
ASMEDIA ASM1466:
Mount RN35, Reserve RN42
Pin 9:
PARADE PS8250B:
Reserve RN41.
PERICOM PI3EQX6741ST:
Reserve RN41
ASMEDIA ASM1466:
Mount RN41 to pull down
1, Host generate Low pulse 40ms to eject ODD
2, After this pulse, signal remain high and no
pulse is allowed within 7s
CN45 0.01U_0402_16V7K~D
1 2
CN36
0.1U_0402_16V4Z~D
1
2
CN40
0.1U_0402_25V6K~D
1
2
CN32 0.01U_0402_16V7K~D
1 2
CN43 0.01U_0402_16V7K~D
1 2
RN14 0_0402_5%@
1 2
CN27 0.01U_0402_16V7K~D
1 2
RN32 0_0402_5%@
1 2
RN25
5.1K_0402_1%
1 2
CN52
0.1U_0402_16V4Z~D
1
2
CN54
10U_0805_10V4Z~D
1
2
CN39
1U_0402_6.3V6K~D
1
2
RN30 0_0402_5%
1 2
UN2
PS8520BTQFN20GTR2_TQFN20_4X4
A_INp
1
A_INn
2
REXT 20
A_PRE1
19
B_OUTp
5
VDD 6
B_PRE0 8
A_PRE0 9
NC 10
TEST
18
GND
13 B_INp 11
B_INn 12
B_PRE1
17
A_OUTn 14
A_OUTp 15
VDD 16
GND
3
B_OUTn
4
EPAD
21
EN
7
RN41
2K_0402_5%
1 2
RN42
5.1K_0402_1%
1 2
RN36
0_0402_5%
@
12
CN48 0.01U_0402_16V7K~D
1 2
RN17
0_0402_5%
12
RN38 0_0402_5%@
1 2
CN57
1U_0402_6.3V4Z~D
1
2
CN47 0.01U_0402_16V7K~D
1 2
RN27
1.5M_0402_5%~D
1 2
CN38
10U_0805_10V4Z~D
1
2
CN30 0.01U_0402_16V7K~D
1 2
RN40 0_0402_5%@
1 2
CN29 0.01U_0402_16V7K~D
1 2
DN1 SDM10U45-7_SOD523-2~D
21
RN47
100K_0402_5%~D
1 2
T61PAD~D @
CN26 0.01U_0402_16V7K~D
1 2
RN35
0_0402_5%
@
12
RN22 0_0402_5%@
1 2
RN26
300K_0402_5%~D
1 2
RN19
0_0402_5%
@
12
RN16 0_0402_5%@
1 2
RN21 0_0402_5%@
1 2
RN39 0_0402_5%@
1 2
T63PAD~D @
CN41 0.01U_0402_16V7K~D
1 2
RN24
2K_0402_5%
1 2
G
D
S
QN1
SSM3K7002FU_SC70-3~D
2
13
CN51
1000P_0402_50V7K~D
1
2
RN33 0_0402_5%@
1 2
CN56
0.1U_0402_16V4Z~D
1
2
T62PAD~D @
G
D
S
QN3
SSM3K7002FU_SC70-3~D
2
13
CN53
1U_0402_6.3V4Z~D
1
2
RN37
0_0402_5%
@
12
T59PAD~D @
T65PAD~D @
RN20
0_0402_5%
@
12
CN44 0.01U_0402_16V7K~D
1 2
G
D
S
QN4
2N7002E-T1-E3_SOT23-3
2
13
CN25 0.01U_0402_16V7K~D
1 2
S
G
D
QN2
SI3456DDV-T1-GE3_TSOP6~D
3
6
2
45
1
CN37
1U_0402_6.3V4Z~D
1
2
CN58
10U_0805_10V4Z~D
1
2
RN34
0_0402_5%
12
CN31 0.01U_0402_16V7K~D
1 2
CN50
0.1U_0402_25V6K
1
2
CN55
1000P_0402_50V7K~D
1
2
RN15 0_0402_5%@
1 2
CN49
0.01U_0402_16V7K
1
2
CN33
0.01U_0402_16V7K
1
2
RN43 0_0402_5%~D
1 2
CN42 0.01U_0402_16V7K~D
1 2
CN34
0.1U_0402_25V6K
1
2
RN28
100K_0402_5%~D
@
12
JP2
BELLW_80003-4041
CONN@
WAKE#
1
NC
3
NC
5
CLKREQ#
7
GND
9
REFCLK-
11
REFCLK+
13
GND
15
NC
17
NC
19
GND
21
PERn0
23
PERp0
25
GND
27
GND
29
PETn0
31
PETp0
33
GND
35
NC
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
GND
53
3.3V 2
GND 4
1.5V 6
NC 8
NC 10
NC 12
NC 14
NC 16
GND 18
NC 20
PERST# 22
+3.3Vaux 24
GND 26
+1.5V 28
SMB_CLK 30
SMB_DATA 32
GND 34
USB_D- 36
USB_D+ 38
GND 40
LED_W W AN# 42
LED_W LAN# 44
LED_W PAN# 46
+1.5V 48
GND 50
+3.3V 52
GND 54
RN31 0_0402_5%@
1 2
JODD1
E-T_0870K-F20C-22L
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
GND1 21
GND2 22
GND3 23
GND4 24
CN28 0.01U_0402_16V7K~D
1 2
RN45 0_0402_5%~D
1 2
RN18
0_0402_5%
@
12
RN44 0_0402_5%~D
1 2
CN46 0.01U_0402_16V7K~D
1 2
RN13 0_0402_5%
1 2
CN35
1000P_0402_50V7K~D
1
2
RN23 0_0402_5%@
1 2
UN3
PS8520BTQFN20GTR2_TQFN20_4X4
A_INp
1
A_INn
2
REXT 20
A_PRE1
19
B_OUTp
5
VDD 6
B_PRE0 8
A_PRE0 9
NC 10
TEST
18
GND
13 B_INp 11
B_INn 12
B_PRE1
17
A_OUTn 14
A_OUTp 15
VDD 16
GND
3
B_OUTn
4
EPAD
21
EN
7
T64PAD~D @
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
COEX2
COEX1
COEX2
COEX1
PLT_RST#
PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1
USB20_P4
USB20_N4
MINI1CLK_REQ#
PCIE_WAKE#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
PCIE_WAKE#
PCH_SMBCLK
PCH_SMBDATA
CPU_MXM_DMC_AUXP
CPU_MXM_DMC_AUXN
BT_ON#
WL_OFF#
CPU_MXM_DMC_P1
CPU_MXM_DMC_N1
PLT_RST#
DMC_RADIO_OFF#
CPU_MXM_DMC_AUXN
USB20_N5
CPU_MXM_DMC_P3
CLK_PCIE_MINI2#
MINI2_SMBDATA
CPU_MXM_DMC_P0
CPU_MXM_DMC_P2
CPU_MXM_DMC_N2
USB20_P5
CPU_MXM_DMC_N3
PCIE_PRX_WANTX_N2
CLK_PCIE_MINI2
MINI2_SMBCLK
CPU_MXM_DMC_N0
PCIE_PRX_WANTX_P2
DMC_PCH_DET#
MINI2CLK_REQ#
CPU_MXM_DMC_AUXP
DP_DMC_HPD
WiGi_RADIO_DIS#_R
WiGi_RADIO_DIS#_R WiGi_RADIO_DIS#
PCIE_PTX_W ANRX_N2_C
PCIE_PTX_W ANRX_P2_C
PCIE_PTX_W LANRX_N1_C
PCIE_PTX_W LANRX_P1_C
BT_ON#_R
+3VS_DMC
+1.5VS
+3VS
+3VS
+3VS
+1.5VS
+3VS_DMC
+1.5VS_DMC
+1.5VS
+3VS_DMC
+1.5VS_DMC +3VS_DMC
+3VS
PCIE_PRX_WLANTX_N1<16>
WL_OFF# <17>
PCIE_PTX_W ANRX_N2<16>
PCIE_PTX_W ANRX_P2<16>
CPU_MXM_DMC_N3 <39>
CPU_MXM_DMC_P3 <39>
CPU_MXM_DMC_N1 <39>
CPU_MXM_DMC_P1 <39>
PLT_RST# <6,17,43,44,53>
DMC_PCH_DET#<18>
PCIE_PRX_WLANTX_P1<16>
CLK_PCIE_MINI2#<18>
CLK_PCIE_MINI2<18>
MINI1CLK_REQ#<18>
PCIE_PTX_W LANRX_N1<16>
PCIE_PTX_W LANRX_P1<16>
USB20_N4 <20>
DMC_RADIO_OFF# <21>
USB20_P4 <20>
PLT_RST#<6,17,43,44,53>
CPU_MXM_DMC_AUXN<39>
CPU_MXM_DMC_AUXP<39>
CLK_PCIE_MINI1#<18>
CLK_PCIE_MINI1<18>
LPC_FRAME# <19,43>
LPC_AD0 <19,43>
LPC_AD3 <19,43>
LPC_AD1 <19,43>
LPC_AD2 <19,43>
PCIE_PRX_WANTX_N2<16>
CLK_DEBUG<18>
USB20_N5 <20>
USB20_P5 <20>
DP_DMC_HPD <39>
MINI2CLK_REQ#<18>
BT_ON#<17>
PCIE_WAKE#<17,43,44>
CPU_MXM_DMC_N2<39>
CPU_MXM_DMC_P2<39>
PCIE_PRX_WANTX_P2<16>
CPU_MXM_DMC_N0<39>
CPU_MXM_DMC_P0<39>
WiGi_RADIO_DIS# <21>
PCH_SMBCLK <6,12,13,14,15,19,49,50,53>
PCH_SMBDATA <6,12,13,14,15,19,49,50,53>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
Mini Card -WLAN/DMC/BT
Custom
48 61Friday, June 22, 2012
2012/06/22 2013/06/21
WLAN
Display Mini Card (DMC)
Compal Electronics, Inc.
RE31 0_0402_5%~D
1 2
C39
4.7U_0805_10V4Z~D
1
2
C41
0.1U_0402_16V4Z~D
1
2
C42
4.7U_0805_10V4Z~D
1
2
RE34 0_0402_5%~D@
1 2
R39 0_0402_5%~D
1 2
C44
0.1U_0402_16V4Z~D
1
2
C43
0.1U_0402_16V4Z~D
1
2
C61 0.1U_0402_10V7K~D
1 2
C40
0.1U_0402_16V4Z~D
1
2
RE32 0_0402_5%~D
1 2
L1
BLM18AG601SN1D_0603~D
12
R41 0_0402_5%~D
1 2
C37
0.1U_0402_16V4Z~D
1
2
C45
4.7U_0805_10V4Z~D
1
2
R44
1M_0402_5%~D
1 2
C59 0.1U_0402_10V7K~D
1 2
RE12 0_0402_5%~D@
1 2
C36
4.7U_0805_10V4Z~D
1
2
R40 0_0402_5%~D
1 2
JDMC1
TYCO_2041286-1
CONN@
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
GND1
77
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 78
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
56 56
54 54
58 58
60 60
62 62
64 64
66 66
68 68
69
69
71
71
73
73
75
75
70 70
72 72
74 74
76 76
1
1
GND3
79
RE33 0_0402_5%~D@
1 2
C63
47P_0402_50V8J~D
1
2
RE22 0_0402_5%~D
1 2
RE28 0_0402_5%~D
1 2
D3
SDMK0340L-7-F
@
2 1
C64
47P_0402_50V8J~D
1
2
RE30 0_0402_5%~D@
1 2
JMINI1
BELLW_80003-4041
CONN@
WAKE#
1
NC
3
NC
5
CLKREQ#
7
GND
9
REFCLK-
11
REFCLK+
13
GND
15
NC
17
NC
19
GND
21
PERn0
23
PERp0
25
GND
27
GND
29
PETn0
31
PETp0
33
GND
35
NC
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
GND
53
3.3V 2
GND 4
1.5V 6
NC 8
NC 10
NC 12
NC 14
NC 16
GND 18
NC 20
PERST# 22
+3.3Vaux 24
GND 26
+1.5V 28
SMB_CLK 30
SMB_DATA 32
GND 34
USB_D- 36
USB_D+ 38
GND 40
LED_W W AN# 42
LED_W LAN# 44
LED_W PAN# 46
+1.5V 48
GND 50
+3.3V 52
GND 54
C46
0.1U_0402_16V4Z~D
1
2
R43 100K_0402_5%~D
1 2
RE29 0_0402_5%~D
1 2
R38 0_0402_5%~D
1 2
RE1191K_0402_1%~D
1 2
C60 0.1U_0402_10V7K~D
1 2
R42 100K_0402_5%~D
1 2
RE27 0_0402_5%~D
1 2
L2
BLM18PG330SN1D_2P~D
12
C38
0.1U_0402_16V4Z~D
1
2
RE26 0_0402_5%~D
1 2
C62 0.1U_0402_10V7K~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB3TN2_L
USB3TP1_L
USB3_P1_PIN18
USB3_P1_PIN6
USB3RP2_R_C
USB3RN2_R_C USB3RN2_R
USB3RP2_R
USB3_P0_PIN6
USB3_P0_PIN18
USB3RP1
USB3RN1
USB3RP2_L
USB3RN2_L
SW_USB20_N0
USB3TP1_R_C
USB3TN1_R_C USB3TN1_R
USB3TP1_R
USB3_DE2_P0
USB3_EQ1_P0
USB3_P1_PIN6
USB3_OS2_P1
USB3_DE1_P0
USB3_DE2_P1
USB3_EQ2_P0
USB3_OS1_P1
USB3_DE1_P1
USB3_EQ2_P1
USB3_EQ1_P1
USB3_OS2_P0
USB3_OS1_P0
USB3_DE2_P0
USB3RN2_R
USB3RP2_R
USB3TP2_R
USB3TN2_R
USB3_OS2_P1
USB3_DE2_P1
USB3_EQ2_P1
USB3_EQ1_P1
USB3_OS1_P1
USB3_DE1_P1
USB3_P1_PIN6
USB3_P1_PIN18
USB3_EQ1_P0
USB3_OS2_P1
USB3_DE1_P0
USB3_DE2_P1
USB3_P0_PIN6
USB20_P0_CONN
USB20_N0_CONN
USB3RN1_R
USB3RP1_R
USB3TN1_R
USB3TP1_R
USB20_P1_CONN
USB20_N1_CONN
USB20_P0
USB20_N0
PWRSHARE_EN
PWRSHARE_OE#
PWRSHARE_EN
PWRSHARE_SEL#
SW_USB20_N0
SW_USB20_P0
PWRSHARE_SEL#
PWRSHARE_OE#
PWRSHARE_SEL#
USB3_CM_P0
USB3_ERD_P1
USB3_CM_P1
USB3_ERD_P0
USB3TN1_L
USB3TN2
USB3TP2
USB3TP1_RC
USB3RN1_R_C
USB3RP1_R_C
USB3TN1_RC
USB3_P0_PIN6
USB3_CM_P0
USB3_ERD_P1
USB3_CM_P1
USB3_ERD_P0
USB3TP2_R_C
USB3TN2_R_C USB3TN2_R
USB3TP2_R
USB3_EQ2_P0
USB3_ERD_P1
USB3_CM_P1
USB3_OS1_P1
USB3_DE1_P1
USB3_EQ2_P1
USB3_EQ1_P1
USB3RP2
USB3RN2
USB3TN2
USB3RN2_RL
USB3RP2_RL
USB3TN2_RL
USB3TP2_RLUSB3TP2
USB3RP1
USB3RN1 USB3RN1_RL
USB3RP1_RL
USB3TN1_RL
USB3TP1_RLUSB3TP1
USB3TN1
USB3_ERD_P0
USB3_CM_P0
USB3_P0_PIN18
USB3_P1_PIN18
USB3TN2_R_C
USB3TP2_R_CUSB3TP2_L
USB3_OS2_P0
USB3_DE2_P0
USB3_EQ2_P0
USB3_EQ1_P0
USB3_OS1_P0
USB3_DE1_P0
USB3RP1_L
USB3RN1_L
SW_USB20_P0
USB3RP1_R_C
USB3RN1_R_C USB3RN1_R
USB3RP1_R
USB3_P0_PIN18
USB20_N0_CONN
USB3_OS2_P0
USB3TP1_R_C
USB3TN1_R_C
USB3RP2_R_C
USB3RN2_R_C
USB3TP2_R_C
USB3TN2_R_C
USB3RP1_R_C
USB3RN1_R_C
USB3TN1_R_C
USB3TP1_R_C
USB3RN2_R_C
USB3RP2_R_C
USB3TP2_RC
USB3TN2_RC
USB3TP1
USB3TN1
USB3_OS1_P0
USB3RN2
USB3RP2
USB20_P0_CONN
PWRSHARE_EN_R#
USB_PWR_EN#
PWRSHARE_EN
USB3TP1_R USB3TP1_R
USB3RN1_R USB3RN1_R
USB3TN1_R USB3TN1_R
USB3RP1_R USB3RP1_R
USB20_P0_CONN
USB20_N0_CONN
USB3TP2_R USB3TP2_R
USB3RN2_R USB3RN2_R
USB3TN2_R USB3TN2_R
USB3RP2_R USB3RP2_R
USB20_N1_CONN
USB20_P1_CONN
USB20_N1_CONN
USB20_P1_CONNUSB20_P1
USB20_N1
+USB3_VCCB
+USB3_VCCB
+USB3_VCCA
+5VALW
+5VALW
+3VS
+USB3_VCCA
+3VS
+3VS
+USB3_VCCA
+5VALW
+USB3_VCCB
+5VALW
+5VALW
+3VALW
USB3RN2<20>
USB3RP2<20>
USBCHG_DET#<43>
USB20_N0<20>
USB20_P0<20>
PWRSHARE_OE#<43>
USB3TN2<20>
USB3TP2<20>
USB20_P1<20>
USB20_N1<20>
USB3RN1<20>
USB3RP1<20>
USB3TP1<20>
USB3TN1<20>
USB_OC0# <20>
USB_OC1# <20>
USB_PWR_EN#<43,53>
PWRSHARE_EN_EC#<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
USB 3.0/2.0 x2 (left side)
Custom
49 61Friday, June 22, 2012
2012/06/22 2013/06/21
Vendor
pin
pin17
pin16
pin15
PS8710B
(default)
pin2
pin3
pin4
pin6
pin18
pin14
pin5
AEQ0
ADE0
AEQ1
PD
BEQ0
BDE0
BEQ1
BDE1
ADE1
TEST
EQ2
DE2
OS2
CM
EN_RXD
EQ1
DE1
OS1
TI
PS8710
[A(B)_DE1, A(B)_DE0] ==
LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: 7dB de-emphasis
HH: 5dB with boost output swing
[A(B)_EQ1, A(B)_EQ0] ==
LL: reserved
LH: program EQ for channel loss up to 7dB
HL: program EQ for channel loss up to 14.5dB
HH: program EQ for channel loss up to 11.5dB
TEST ==
L: Normal operation (default)
H: Test mode enable
SN65LVPE502
EN==
1:normal operation(default)
0:sleep mode
CM==
0:normal operation(default)
1:Compliance test mode
USB CONN
Power share
For OPTION reserve
PCB footprint and CIS symbol use TI
(SN65LVPE502CPRGER)
Compal P/N and value use Parade
(PS8710B)
[Parade suggest]
PS8710 AEQ0,BEQ0 adjust 7db,
REXT use 3.3 K well get btter test result.
PCB footprint and CIS symbol use TI
(SN65LVPE502CPRGER)
Compal P/N and value use Parade
(PS8710B)
Compal Electronics, Inc.
80mil
2.0A
80mil
2.0A
RI71 0_0402_5%~D@
1 2
RI27 4.7K_0402_5%~D@
1 2
RI50 0_0402_5%~D@
1 2
LI2
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
RI46 4.7K_0402_5%~D@
1 2
UI4
PS8713BTQFN24GTR2-A0_TQFN24_4X4
VCC
1
EQ1
2DE1
3OS1
4
EN_RXD 5
GND 6
NC 7
RX1-
8
GND 10
TX2-
11
TX2+
12
VCC
13
CM 14
OS2
15
DE2
16
EQ2
17
TX1+ 22
RX2+ 19
RX2- 20
GND 21
GND 18
TX1- 23
NC 24
RX1+
9
PGND
25
RI9 10K_0402_5%~D
1 2
CI5 0.1U_0402_10V6K~D
1 2
CI7
0.01U_0402_16V7K~D
1 2
UI1
SLG55584AVTR_TDFN8_2X2
CEN 1
DP 3
SELCDP 4
DM 2
VDD
5TDP
6
CB
8
TDM
7
Thermal Pad 9
CI10 0.1U_0402_10V6K~D
1 2
RI66 0_0402_5%~D@
1 2
RI21 4.7K_0402_5%~D@
1 2
RI47 4.7K_0402_5%~D@
1 2
LI3
DLW21SN900SQ2L_0805_4P~D
1
122
33
4
4
RI74 0_0402_5%~D@
1 2
CI6
.1U_0402_16V7K~D
1 2
+
CI32
220U_6.3V_M
1
2
DI10
PESD5V0U2BT_SOT23-3~D
2
3
1
CI16
0.1U_0402_16V7K
1
2
CI28 0.1U_0402_10V6K~D
1 2
RI15 0_0402_5%~D@
1 2
RI75 0_0402_5%~D@
1 2
RI84 4.7K_0402_5%~D@
1 2
CI11 0.1U_0402_10V6K~D
1 2
RI6 0_0402_5%~D@
1 2
RI37 4.7K_0402_5%~D@
1 2
RI72 0_0402_5%~D@
1 2
RI61 0_0402_5%~D@
1 2
RI36 4.7K_0402_5%~D@
1 2
RI69 0_0402_5%~D@
1 2
RI8 10K_0402_5%~D@
1 2
CI37
0.1U_0402_16V7K
1
2
RI52 3.3K_0402_5%@
1 2
CI26
0.01U_0402_16V7K~D
1 2
RI30 4.7K_0402_5%~D@
1 2
RI45 4.7K_0402_5%~D@
1 2
CI35
4.7U_0805_10V4Z
1
2
RI1 0_0402_5%~D@
1 2
RI22 4.7K_0402_5%~D@
1 2
CI1
0.1U_0402_16V4Z~D
1
2
LI1
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
CI13
0.1U_0402_16V7K
1
2
RI38 4.7K_0402_5%~D@
1 2
CI18
4.7U_0805_10V4Z
1
2
RI3 0_0402_5%~D@
1 2
DI2
IP4292CZ10-TBR_XSON10_2.5X1~D
4
5
1
6
2
7
3
10
9
8
RI19 4.7K_0402_5%~D@
1 2
RI77 4.99K_0402_1%
1 2
CI30 0.1U_0402_10V6K~D
1 2
UI3
PS8713BTQFN24GTR2-A0_TQFN24_4X4
VCC
1
EQ1
2DE1
3OS1
4
EN_RXD 5
GND 6
NC 7
RX1-
8
GND 10
TX2-
11
TX2+
12
VCC
13
CM 14
OS2
15
DE2
16
EQ2
17
TX1+ 22
RX2+ 19
RX2- 20
GND 21
GND 18
TX1- 23
NC 24
RX1+
9
PGND
25
RI18 0_0402_5%~D@
1 2
RI10 10K_0402_5%~D@
1 2
RI28 4.7K_0402_5%~D@
1 2
LI5
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
RI23 4.7K_0402_5%~D@
1 2
LI4
DLW21SN900HQ2L_0805_4P~D
11
2
2
3
344
CI15
0.1U_0402_16V7K
1
2
RI31 4.7K_0402_5%~D@
1 2
RI42 4.7K_0402_5%~D@
1 2
CI34
10U_0603_6.3V6M~D
1
2
CI23 0.1U_0402_10V6K~D
1 2
RI49 0_0402_5%~D@
1 2
RI83
0_0402_1%
@
1 2
CI22
10U_0603_6.3V6M~D
1
2
RI67 0_0402_5%~D@
1 2
CI24 0.1U_0402_10V6K~D
1 2
DI8
IP4292CZ10-TBR_XSON10_2.5X1~D
4
5
1
6
2
7
3
10
9
8
LI6
DLW21SN900SQ2L_0805_4P~D
1
122
33
4
4
RI48 4.7K_0402_5%~D@
1 2
CI9 0.1U_0402_10V6K~D
1 2
UI5
AP2301MPG-13_MSOP8
FLG 5
VIN
3VOUT 6
GND
1
EN
4
VOUT 7
VIN
2VOUT 8
EPAD
9
RI20 4.7K_0402_5%~D@
1 2
RI55 3.3K_0402_5%@
1 2
RI29 4.7K_0402_5%~D@
1 2
RI64 0_0402_5%~D@
1 2
RI53 3.3K_0402_5%@
1 2
RI44 4.7K_0402_5%~D@
1 2
RI73 0_0402_5%~D@
1 2
CI29 0.1U_0402_10V6K~D
1 2
CI27 0.1U_0402_10V6K~D
1 2
+
CI20
220U_6.3V_M
1
2
RI68 0_0402_5%~D@
1 2
CI25
.1U_0402_16V7K~D
1 2
RI16 0_0402_5%~D@
1 2
RI24 4.7K_0402_5%~D@
1 2
RI60 0_0402_5%~D@
1 2
RI25 4.7K_0402_5%~D@
1 2
RI2 0_0402_5%~D@
1 2
RI14 0_0402_5%~D@
1 2
RI7 10K_0402_5%~D@
1 2
RI40 4.7K_0402_5%~D@
1 2
CI38
0.1U_0402_16V7K
1
2
RI54 3.3K_0402_5%@
1 2
RI41 4.7K_0402_5%~D@
1 2
RI87 4.7K_0402_5%~D@
1 2
RI57 0_0402_5%~D@
1 2
RI76 0_0402_5%~D@
1 2
RI13 0_0402_5%~D@
1 2
RI26 4.7K_0402_5%~D@
1 2
RI63 0_0402_5%~D@
1 2
DI7
SDMK0340L-7-F_SOD323-2~D
1 2
RI85 0_0402_5%~D@
1 2
JUSB1
TAIWI_USB006-107CRL-TWD
CONN@
SSTX-
8
SSTX+
9
GND 11
GND 12
VBUS
1
D+
3
D-
2
GND
4
SSRX-
5
SSRX+
6
GND
7
GND 14
GND 13
Plug_DET
10
DI9
PESD5V0U2BT_SOT23-3~D
2
3
1
RI33 4.7K_0402_5%~D@
1 2
RI65 0_0402_5%~D@
1 2
RI81
100K_0402_5%
1 2
RI56 4.99K_0402_1%
1 2
RI70 0_0402_5%~D@
1 2
JUSB2
TAITW_PUBAU5-09FLBS1NN4H0
CONN@
SSTX-
8
SSTX+
9
GND 10
GND 11
VBUS
1
D+
3
D-
2
GND
4
SSRX-
5
SSRX+
6
GND
7
GND 13
GND 12
RI43 4.7K_0402_5%~D@
1 2
RI5 0_0402_5%~D@
1 2
CI36
0.1U_0402_16V7K
1
2
RI62 0_0402_5%~D@
1 2
RI34 4.7K_0402_5%~D@
1 2
RI39 4.7K_0402_5%~D@
1 2
RI32 4.7K_0402_5%~D@
1 2
G
D
S
QI1
SSM3K7002FU_SC70-3~D
2
13
RI51 0_0402_5%~D@
1 2
RI4 0_0402_5%~D@
1 2
RI17 0_0402_5%~D@
1 2
RI82
10K_0402_5%
12
CI8 0.1U_0402_10V6K~D
1 2
RI86 0_0402_5%~D
1 2
RI35 4.7K_0402_5%~D@
1 2
RI80
0_0402_1%
@
1 2
CI4 0.1U_0402_10V6K~D
1 2
UI2
AP2301MPG-13_MSOP8
FLG 5
VIN
3VOUT 6
GND
1
EN
4
VOUT 7
VIN
2VOUT 8
EPAD
9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN_MDIN0
LAN_MDIP0
USB20_P2
USB20_N2
USB3TN5
USB3TP5
USB3RP5
USB3RN5
LAN_MDIN1
LAN_MDIP1
LAN_MDIN2
LAN_MDIP2
LAN_MDIN3
LAN_MDIP3
USB20_N3
USB3TN6
USB3TP6
USB3RN6
USB3RP6
USB20_P3
USB_OC2#
USB_PWR_EN#
USB_OC3#
LAN_ACTIVITY#
LAN_LINK#_R
LAN_LED2#_R
RTRON_LED_R_DRV#
RTRON_LED_G_DRV#
RTRON_LED_B_DRV#
PCIE_PTX_CARDRX_P4
PCIE_PTX_CARDRX_N4
PCIE_PRX_CARDTX_P4
PCIE_PRX_CARDTX_N4
CLK_PCIE_CD
CLK_PCIE_CD#
CDCLK_REQ#
PLT_RST#
LID_SW
LID_SW_IN#
TP_DATA
TP_CLK
TP_LED_B_DRV#
TP_LED_R_DRV#
TP_LED_G_DRV#
KP_DET#
I2C_CLK
I2C_DAT
KSI3
KSI0
KSI7
KSO8
KSO13
KSO9
KSO3
KSO2
KSO11
KSO5
KB_DET#
KSI1
KSI6
KSI4
KSI2
KSI5
KSO15
KSO4
KSO14
KSO12
KSO1
KSO0
KSO6
KSO10
KSO7
KSI[0..7]
KSO[0..17]
MXM1_FAN_FB MXM1_FAN_FB_D
MXM1_FAN_PWM
MXM1_FAN_PWM
MXM1_FAN_FB
TP_CLK
TP_DATA
ON/OFFBTN#
KSO16
KSO17
VPK_DET#
VPK_EN
+LAN_IO
+3VS
+5VALW +5VALW
+5VALW
+5VS
+3VALW
+3VS
+5VS
+5VALW
+5VS_TP_LED
+5VS
+3VS
+3.3V_F347
+3VS +5VS
LAN_MDIP2 <44>
LAN_MDIN3 <44>
USB20_N2<20>
USB20_P2<20>
USB3TP5<20>
LAN_MDIN0 <44>
USB3TN5<20>
LAN_MDIP0 <44>
USB3RP5<20>
LAN_MDIN1 <44>
USB3RN5<20>
LAN_MDIP3 <44>
USB20_N3<20>
USB20_P3<20>
USB3TP6<20>
USB3TN6<20>
USB3RP6<20>
USB3RN6<20>
LAN_ACTIVITY# <44>
USB_PWR_EN# <43,52>
USB_OC3#<20>
USB_OC2#<20>
LAN_MDIP1 <44>
LAN_MDIN2 <44>
LAN_LINK#_R <44>
LAN_LED2#_R <44>
RTRON_LED_R_DRV# <48>
RTRON_LED_G_DRV# <48>
RTRON_LED_B_DRV# <48>
PCIE_PTX_CARDRX_P4<20>
PCIE_PTX_CARDRX_N4<20>
PCIE_PRX_CARDTX_P4<20>
PCIE_PRX_CARDTX_N4<20>
CLK_PCIE_CD<18>
CLK_PCIE_CD#<18>
PLT_RST#<6,17,43,44,51>
CDCLK_REQ#<18>
WLES ON/OFF LED#<43>
CAPS_LED#<43>
LED_B_7313#_1<48>
LED_R_7313#_1<48>
HDD_G<48>
HDD_R<48>
PWR_R_7313#<48>
ON/OFFBTN#<55>
LED_G_7313#_1<48>
LID_SW<48>
PWR_G_7313#<48>
PWR_B_7313#<48>
HDD_B<48>
LID_SW_IN#<19,43,47,48>
TP_DATA<43>
TP_CLK<43>
PCH_SMBDATA<6,12,13,14,15,19,49,50,51>
PCH_SMBCLK<6,12,13,14,15,19,49,50,51>
EC_SMB_DA2<19,40,43,54>
EC_SMB_CK2<19,40,43,54>
USB20_N13<20>
USB20_P13<20>
7313_INT#<48>
I2C_CLK<47,48>
I2C_DAT<47,48>
KB_DET#<43>
KSI[0..7]<43> KSO[0..17]<43>
TP_LED_R_DRV#<48>
TP_LED_G_DRV#<48>
TP_LED_B_DRV#<48>
MXM1_FAN_PWM <43>
MXM1_FAN_FB <43>
VPK_DET#<43>
VPK_EN<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
IO BTB CONN
Custom
50 61Friday, June 22, 2012
2012/06/22 2013/06/21
BTB CONNECTOR TO USB3.0 Board
30pin Connector to CardReader
60 pin FFC connector To MB
Place close to JP3
Place close to JIO2
Reserve for Key Pad
(Viking only)
JIO2
ACES_88196-3041
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
G1
31
G2
32
C56
22U_0805_6.3VAM~D
1
2
D72
PESD24VS2UT_SOT23-3~D
2
3
1
R55
10K_0402_5%~D
1 2
C48
0.1U_0402_16V4Z~D
1
2
JIO1
E&T_1001-F50E-03R
CONN@
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
17
17 18 18
19
19
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39
15
15
20 20
16 16
40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
GND1
51 GND2 52
D66
SDMK0340L-7-F_SOD323-2~D
12
D71
PESD5V0U2BT_SOT23-3~D
2
3
1
R56
10K_0402_5%~D
1 2
R57
10K_0402_5%~D
1 2
JP3
CVILU_CF25602D0R0-05-NH
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60 G2 62
G1 61
C47
10U_0805_10V6K
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SYSTEM_FAN_FB
SYSTEM_FAN_PWM
REMOTE_P2
SENSOR_DIODE_N2
SENSOR_DIODE_P2
EC_SMB_DA2
REMOTE_N2
EC_SMB_CK2
REMOTE_P1SENSOR_DIODE_P1
SENSOR_DIODE_N1
EC_SMB_DA2
REMOTE_N1
EC_SMB_CK2
+3VS
+3VS +5VS
+3VS
+3VS
+3VS
SYSTEM_FAN_PWM<43>
EC_SMB_CK2 <19,40,43,53>
EC_SMB_DA2 <19,40,43,53>
SYSTEM_FAN_FB<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
Thermal Sensor & FAN
Custom
51 61Friday, June 22, 2012
2012/06/22 2013/06/21
MXM1 FAN Controller
System FAN Controller
Diode circuit s used for skin temp sensor
(placed between CPU and MXM).
Place C51 close to Q17 as possible.
Compal Electronics, Inc.
Address:100_1101
Address:100_1100
R53 0_0402_5%~D
1 2
C54
470P_0402_50V7K~D
1
2
E
B
C
Q19
MMBT3904WT1G_SC70-3~D
2
3 1
U6
ADM1032ARMZ-2REEL_MSOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
C55
100P_0402_50V8J~D
@
1
2
R47 0_0402_5%~D
1 2
D65
SDMK0340L-7-F_SOD323-2~D
12
R50
10K_0402_5%~D
1 2
U5
ADM1032ARMZ-REEL_MSOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R46 0_0402_5%~D
1 2
C49
0.1U_0402_10V7K~D
1
2
E
B
C
Q17
MMBT3904WT1G_SC70-3~D
2
3 1
C53
0.1U_0402_10V7K~D
1
2
JFAN1
ACES_50273-0040N-001
CONN@
1
1
2
2
3
3
G5
5
G6
6
4
4
R52 0_0402_5%~D
1 2
R54 6.8K_0402_5%~D
1 2
R49
10K_0402_5%~D
1 2
R51
10K_0402_5%~D
1 2
C50
470P_0402_50V7K~D
1
2
C52
22U_0805_6.3VAM~D
1
2
R48 4.7K_0402_5%~D
1 2
C51
100P_0402_50V8J~D
@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB20_N7
USB20_P7
ON/OFFBTN#
ON/OFFBTN#
+5VS
+3VLP
USB20_P7<20>
ON/OFF <43>
ON/OFFBTN#<53>
USB20_N7<20>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
KB & Power Button & IR
B
52 61Friday, June 22, 2012
2012/06/22 2013/06/21
Power Button
IR SENSOR connector
Fiducial Mark
ON/OFF switch
Pop only for
SSI debug
TOP Side
Bottom Side
A
B
C
D
E
F
H27
H_3P0
@
1
H24
H_3P0
@
1
H2
H_3P5
@
1
FD3
@
FIDUCIAL_C40M80
1
H29
H_3P0
@
1
H30
H_3P0
@
1
H11
H_3P0
@
1
H19
H_3P8
@
1
C57
0.1U_0402_16V4Z~D
1
2
H17
H_3P3
@
1
H10
H_3P0
@
1
ZZZ1
PCB-MB
H25
H_3P0
@
1
FD4
@
FIDUCIAL_C40M80
1
H26
H_3P0
@
1
H6
H_3P3
@
1
H8
H_3P3
@
1
H31
H_3P0
@
1
SW2
SMT1-05-A_4P
3
2
1
4
5
6
H16
H_3P0
@
1
H23
H_3P0
@
1
H3
H_3P5
@
1
H5
H_3P3
@
1
FD1
@
FIDUCIAL_C40M80
1
H20
H_3P8
@
1
D26
DAN202UT106_SC70-3
2
3
1
C58
0.1U_0402_25V6K~D
1
2
H9
H_3P0
@
1
H18
H_3P3
@
1
H14
H_3P0
@
1
H32
H_3P0
@
1
H22
H_3P8
@
1
FD2
@
FIDUCIAL_C40M80
1
H15
H_3P0
@
1
H7
H_3P3
@
1
H4
H_3P5
@
1
R58
100K_0402_5%~D
1 2
H12
H_3P0
@
1
H33
H_3P0
@
1
H21
H_3P8
@
1
SW1
SMT1-05-A_4P
3
2
1
4
5
6
JIR1
E-T_4260-F06N-10L
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
GND
7
GND
8
H13
H_3P0
@
1
H1
H_3P5
@
1
H34
H_2P0N
@
1
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+3VS_GATE
+5VS_GATE
+5VMXM_D
+3V_PCH_GATE
+3VS_D
SUSP
+5VS_D
DGPU_PWR_EN#
SYSON#
+3V_D
+5VMXM_GATE
SYSON#
+3VMXM_D
DGPU_PWR_EN#
DGPU_PWR_EN#
PCH_PWR_EN#
+DDR_CHG
+1.35V_CPU_VDDQ_CHG
SUSP
+1.35V_D
SUSP
PCH_PWR_EN#
SUSP
DGPU_PWR_EN#
SUSP
SUSP
+1.5VS_D
+3VMXM_GATE
DGPU_PWR_EN#
PCH_PWR_EN#
SUSP
+1.05VS_D
+1.05VS_GATE
SUSP
+5VS +3VMXM
+5VALW
+3V_PCH
+1.5VS
+3VS
+5VALW
+5VALW
+5VALW
B+_BIAS
+5VS
+3VALW
B+_BIAS
+3VS +5VMXM
B+_BIAS
+3VALW +3VMXM
B+_BIAS
+5VALW
+0.675VS+1.35V_CPU_VDDQ
+3VALW
B+_BIAS
+3V_PCH
+5VALW
+1.35V +3VALW
+5VMXM
+1.05VS
+1.05VS
+1.05V
B+_BIAS
SYSON<43,59,60>
RUN_ON_CPU1.5VS3#<6,10>
DGPU_PWR_EN<29,43>
PCH_PWR_EN<35,43> SUSP#<10,43,59,61>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-9331P
0.1
DC/DC Interface
Custom
53 61Friday, June 22, 2012
2012/06/22 2013/06/21
100mil(2.5A)
40mil(1A)
DC to DC
+5VALW to +5VS
Discharge Circuit
+3VALW to +3V_PCH
+3VALW to +3VS
+3VALW to +3VMXM Transfer
+5VALW to +5VMXM
Compal Electronics, Inc.
+1.05V to +1.05VS
RZ45
100K_0402_5%~D
12
CZ30
0.1U_0603_25V7K~D
@
1
2
CZ28
0.1U_0603_25V7K~D
@
1
2
CZ2
10U_0805_10V4Z~D
1
2
QZ8B
DMN66D0LDW-7_SOT363-6~D
34
5
RZ40
470_0603_5%
12
CZ15
0.1U_0603_25V7K~D
1
2
RZ53
330K_0402_5%~D
1 2
CZ17
1U_0603_10V4Z~D
1
2
D
G
S
QZ15
SSM3K7002F_SC59-3~D
1
3
2
QZ2A
DMN66D0LDW-7_SOT363-6~D
61
2
QZ20
SI4164DY-T1-GE3_SO8~D
36
5
7
8
2
4
1
RZ54
1M_0402_5%~D
12
CZ11
10U_0805_10V4Z~D
1
2
RZ33
0_0402_5%~D
@
12
G
D
S
QZ14
SSM3K7002FU_SC70-3~D
2
13
CZ29
0.1U_0603_25V7K~D
@
1
2
QZ8A
DMN66D0LDW -7_SOT363-6~D
61
2
RZ31
0_0402_5%~D
@
12
CZ23
10U_0805_10V4Z~D
1
2
RZ35
470_0603_5%
1 2
CZ10
0.1U_0603_25V7K~D
1
2
CZ22
0.1U_0603_25V7K~D
1
2
RZ47
100K_0402_5%~D
12
CZ24
10U_0805_10V4Z~D
1
2
QZ3
SI4800BDY-T1-E3_SO8~D
36
5
7
8
2
4
1
CZ5
10U_0805_10V4Z~D
1
2
D
G
S
QZ7
SSM3K7002F_SC59-3~D
1
3
2
RZ43
470_0603_5%
12
RZ41
470_0603_5%
12
RZ37
470_0603_5%
12
RZ44
10K_0402_5%~D
@
1 2
RZ38
220_0603_5%~D
12
RZ4
0_0402_5%~D
@
12
D
G
S
QZ4
SSM3K7002F_SC59-3~D
1
3
2
D
G
S
QZ17
SSM3K7002F_SC59-3~D
1
3
2
QZ11B
DMN66D0LDW-7_SOT363-6~D
34
5
CZ13
10U_0805_10V4Z~D
1
2
QZ6
SI4800BDY-T1-E3_SO8~D
36
5
7
8
2
4
1
G
D
S
QZ19
SSM3K7002FU_SC70-3~D
2
13
D
G
S
QZ5
SSM3K7002F_SC59-3~D
1
3
2
RZ2
0_0402_5%~D
@
1 2
D
G
S
QZ16
SSM3K7002F_SC59-3~D
1
3
2
CZ3
1U_0603_10V4Z~D
1
2
RZ48
100K_0402_5%~D
1 2
RZ3
102K_0402_1%
1 2
CZ25
10U_0805_10V4Z~D
1
2
RZ36
470_0603_5%
1 2
RZ5
102K_0402_1%
1 2
CZ14
1U_0603_10V4Z~D
1
2
CZ27
0.1U_0603_25V7K~D
1
2
QZ9B
DMN66D0LDW-7_SOT363-6~D
34
5
QZ1
SI4800BDY-T1-E3_SO8~D
36
5
7
8
2
4
1
RZ51
100K_0402_5%~D
12
RZ32
200K_0402_5%
1 2
CZ4
0.1U_0603_25V7K~D
1
2
RZ1
102K_0402_1%
1 2
CZ20
10U_0805_10V4Z~D
1
2
CZ6
10U_0805_10V4Z~D
1
2
RZ6
0_0402_5%~D
@
12
CZ1
10U_0805_10V4Z~D
1
2
QZ11A
DMN66D0LDW-7_SOT363-6~D
61
2
G
D
S
QZ12
SSM3K7002FU_SC70-3~D
2
13
CZ8
10U_0805_10V4Z~D
1
2
QZ9A
DMN66D0LDW -7_SOT363-6~D
61
2
RZ50
100K_0402_5%~D
12
RZ42
470_0603_5%
12
CZ12
10U_0805_10V4Z~D
1
2
CZ32
100P_0402_50V8J~D
1
2
RZ39
22_0603_5%~D
12
CZ21
0.1U_0402_16V4Z~D
1
2
RZ49
100K_0402_5%~D
12
UZ3
SI4800BDY-T1-E3_SO8~D
36
5
7
8
2
4
1
G
D
S
QZ10
SSM3K7002FU_SC70-3~D
2
13
CZ9
1U_0603_10V4Z~D
1
2
CZ31
0.1U_0603_25V7K~D
@
1
2
RZ30
200K_0402_5%
1 2
UZ2
SI4800BDY-T1-E3_SO8~D
36
5
7
8
2
4
1
CZ26
0.1U_0402_16V4Z~D
1
2
D
G
S
QZ18
SSM3K7002F_SC59-3~D
1
3
2
RZ46
100K_0402_5%~D
12
RZ34
470_0603_5%
1 2
QZ2B
DMN66D0LDW-7_SOT363-6~D
34
5
G
D
S
QZ13
SSM3K7002FU_SC70-3~D
2
13
CZ7
10U_0805_10V4Z~D
1
2
RZ52
100K_0402_5%~D
12
CZ16
10U_0805_10V4Z~D
1
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ADPIN
VSB_N_002
VSB_N_003
VSB_N_001
PSID
PSID-3
PSID-1
PSID-2
BATT+
BATT++
+DCIN_JACK
SYS_PRES
BATT_PRS
DAT_SMB
CLK_SMB
EC_SMB_DA1 <63>
EC_SMB_CK1 <63>
VIN
B+
+5VALW
B+_BIAS
+5VALW
+3VALW
+RTCBATT
+3VLP
+3VALW
BATT++BATT+
+3VLP+3VALW
VIN
ACIN<17,29,43,47,63>
POK<58>
ADP_I<43,63>
PS_ID <43>
BATT_TEMP <43,63>
VCIN1_PH<43>
VCIN0_PH<43>
ECAGND<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
54 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
PWR-DCIN / BATT CONN / OTP
PH1 under CPU botten side :
CPU thermal protection at 93 +/- 3 degree C
Erp lot6 Circuit
JRTC1
LOTES AAA-BAT-054-K01
@
+1
-
2
PC7
0.01U_0402_25V7K
12
PC2
100P_0402_50V8J
12
G
D
S
PQ7
FDV301N_NL_SOT23-3~D
2
1 3
PC13
.1U_0402_16V7K
@
1 2
PH1
100K_0402_1%_TSM0B104F4251RZ
12
PR4
33_0402_5%
1 2
PR20
100_0402_5%
1 2
PC9
100P_0402_50V8J
12
PL1
C8B BPH 853025_2P
1 2
PC11
0.1U_0402_25V6
12
PR1
200K_0402_1%
@
12
PL3
C8B BPH 853025_2P
1 2
PR15
100_0402_5%
1 2
PQ1A
2N7002BKS 2N SOT363-6
@
61
2
PR18
100_0402_5%
1 2
PR23
49.9K_0402_1%
1 2
PR16
10K_0402_1%
1 2
PR19
0_0402_5%
<BOM Structure>
1 2
PQ3
TP0610K-T1-E3_SOT23-3
2
13
PC8
1000P_0402_50V7K
12
PR5
3.3K_1206_5%~D
@
12
PC4
100P_0402_50V8J
12
PL2
BLM18BD102SN1D_0603~D
12
PR26
499K_0402_1%
1 2
PC10
0.22U_0603_25V7K
12
PC6
100P_0402_50V8J
12
PR17
0_0402_5%
1 2
PBATT1
MOLEX_87437-1342
@
11
33
44
22
55
66
77
88
99
10 10
11 11
12 12
13 13
PJPDC1
ACES 50493-0110N-001
@
11
33
44
22
55
66
77
88
99
10 10
11 11
PD4
PESD24VS2UT_SOT23-3
2
3
1
PR25
12.1K_0402_1%
@
1 2
PR13
100K_0402_1%
1 2
PR7
1M_0402_1%
@
1 2
PD5
BAS40CW _SOT323-3
2
3
1
G
D
S
PQ4
2N7002KW _SOT323-3
2
13
PR12
100K_0402_1%
12
PQ1B
2N7002BKS 2N SOT363-6
@
3
5
4
PR14
100K_0402_1%
1 2
PR24
12.1K_0402_1%
1 2
E
B
C
PQ2
MMST3904-7-F_SOT323~D
2
3 1
PC12
.1U_0402_16V7K
12
PR3
2.2K_0402_5%
1 2
PR6
100K_0402_1%
1 2
PC5
0.1U_0402_25V6
@
12
PC1
1000P_0402_50V7K
12
PD3
PESD24VS2UT_SOT23-3
2
3
1
PC3
1000P_0402_50V7K
12
PD1
SM24_SOT23
@
2
3
1
PR8
10K_0402_1%
12
PR9
15K_0402_1%
1 2
PR10
1M_0402_1%
@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LG_3V
SW1
FB_3V
UG_5V
BST_5V
LG_5V
SNUB_5V
5V_EN
BST_3V
UG_3V
SW2
FB_5V
SNUB_3V
3V_EN
5V_EN
3V_EN
+5VALWP
+3VALW +5VALW
+3VALWP
B++
+5VALWP
B++
B++
+3VALWP
B+
VL
+3VLP
VIN
POK<57>
VCOUT0_PH#<43>
EC_ON<43>
USBCHG_DET_D<43>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
55 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
PWR-3VALWP/5VALWP
3VALWP
TDC 6.08A
Peak Current 8.11A
OCP current 9.73A
TYP MAX
H/S Rds(on) :22mohm , 30mohm
L/S Rds(on) :12.1mohm ,17mohm
5VALWP
TDC 10.64A
Peak Current 14.19A
OCP current 17.03A
TYP MAX
H/S Rds(on) 11.2mohm , 14mohm
L/S Rds(on) :3.7mohm , 5mohm
PR115
1M_0402_1%
@
1 2
PD102
BAS40CW_SOT323-3
2
3
1
PC114
1U_0603_10V5K
12
PC105
0.1U_0402_25V6
12
TPS51225_QFN20_3X3
PU100
CS1 1
VFB1 2
VREG3 3
VFB2 4
CS2 5
EN2
6
PGOOD
7
DRVH2
10
VBST2
9
SW2
8
DRVL2
11
VIN
12
VREG5
13
EN1
20
DRVL1
15
SW1 18
VBST1 17
DRVH1 16
VCLK 19
VO1 14
PAD 21
PJP101
PAD-OPEN 4x4m
1 2
PR101
30.9K_0402_1%
12
PC119
680P_0603_50V7K
12
PC118
1U_0603_10V5K
12
PC117
0.1U_0603_25V7K
12
PC112
0.1U_0603_25V7K
1 2
PC110
10U_0805_25V6K
12
+
PC102
220U_6.3V_M
1
2
PC120
4.7U_0603_6.3V6K
12
PQ101
FDMC8884_POWER33-8-5
3 5
2
4
1
PQ103
FDMC8878_POWER33-8-5
3 5
2
4
1
PD101
LL4148_LL34-2
@
12
PC107
10U_0805_25V6K
@
12
PR100
13.7K_0402_1%~D
1 2
PR108
2.2_0603_5%
1 2
PC116
680P_0603_50V7K
12
PR110
4.7_1206_5%
12
PC121
100P_0402_50V8J
@
1 2
PL101
3.3UH_PCMB063T-3R3MS_6.5A_20%
1 2
PR107
2.2_0603_5%
1 2
PC109
10U_0805_25V6K
12
PQ102
AON7518 1N DFN
3 5
2
4
1
PJP102
PAD-OPEN 4x4m
1 2
PC108
2200P_0402_50V7K
12
PR104
20K_0402_5%~D
12
PR112 0_0402_5%
1 2
PR105
120K_0402_1%~D
1 2
PR118
0_0603_5%~D
1 2
PC111
0.1U_0603_25V7K
1 2
PJP100
PAD-OPEN 4x4m
1 2
PD100 SBR2U30P1-7_POWERDI123-2
1 2
PC106
2200P_0402_50V7K
12
PQ104
AON6508 1N DFN
3 5
2
4
1
PR103
0_0603_5%~D
1 2
PR109
4.7_1206_5%
12
PR116
402K_0402_1%
@
12
PR113
2.2K_0402_5%
1 2
PC122
100P_0402_50V8J
@
1 2
PC104
10U_0805_25V6K
@
12
PL103
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
PR111 0_0402_5%
1 2
PR102
20K_0402_5%~D
1 2
PC103
0.1U_0402_25V6
12
PL102
3.3UH +-20% PIMB104T-3R3MS 10A
12
PR106
59K_0402_1%~D
1 2
+
PC101
150U_B2_6.3VM_R35M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DH_1.35V
VLDOIN_1.35V
S3_1.35V
SW_1.35V
DL_1.35V
1.35V_B+
VDD_1.35V
S5_1.35V
VTTREF_1.35V
SNUB_1.35V
BOOT_1.35V
1.35V_B+
1.35V_FB
+1.35VP
VDDP_1.35V
CS_1.35V
VDDP_1.35V
+0.675VSP
+0.675VS
B+
+1.35VP
+5VALW
+5VALW
+1.35VP
+0.675VSP
+1.35VP
+1.35V +1.35VP
SYSON<43,56,60>
SUSP#<10,43,56,61>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
56 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
PWR-1.35VP/0.675VSP
0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.2A
1.35VP
TDC 13.75A
Peak Current 19.64A
OCP current 23.57A
TYP MAX
H/S Rds(on) :12.2mohm , 15mohm
L/S Rds(on) :2.7mohm , 3.3mohm
PR204
8.06K_0402_1%
12
PC203
4.7U_0805_25V6-K
12
PC209
0.033U_0402_16V7~D
PU200
RT8207MZQW_WQFN20_3X3
VTTSNS 2
FB
6
S5
8
PGOOD
10
VDDP
12
PHASE 16
BOOT 18
VTTREF 4
PGND
14
VTTGND 1
GND 3
VDDQ 5
S3
7
TON
9
VDD
11
CS
13
LGATE
15
UGATE 17
VTT 20
VLDOIN 19
PAD 21
PC206
0.22U_0603_10V7K
1 2
PJP204
PAD-OPEN 4x4m
@
1 2
PC211 220P_0402_50V8J~D
1 2
PQ203
SIR818DP-T1_POWERPAK-SO8-5~D
5
4
2
1
3
PC214
.1U_0402_16V7K
@
12
PC207
10U_0805_6.3V6M
12
+
PC201
330U_2.5V_M
1
2
PC205
2200P_0402_50V7K
12
PC210
1U_0603_10V6K
12
PC213
1U_0603_10V6K
1 2
PR200
2.2_0603_5%
1 2
PQ201
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PC216
0.1U_0402_10V7K
@
12
PR205
1M_0402_1%
1 2
PR208
0_0402_5%
1 2
PL201
0.68UH_PCMC063T-R68MN_15.5A_20%
1 2
PR206
0_0402_5%
1 2
PJP201
PAD-OPEN1x1m
12
PR201
6.04K_0402_1%
1 2
PC202
4.7U_0805_25V6-K
12
PR202
4.7_1206_5%
12
PR207
10K_0402_1%
1 2
PJP202
PAD-OPEN1x1m
@
12
PJP200
JUMP_43X118
@
11
2
2
PJP203
PAD-OPEN 4x4m
@
1 2
PC215
1U_0402_6.3VX5R
@
12
PC204
0.1U_0402_25V6
12
PC212
680P_0603_50V7K
12
PR203
5.1_0603_5%
1 2
PC208
10U_0805_6.3V6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BST_+1.05VP
SW_+1.05VP
UG_+1.05VP
LG_+1.05VP
+1.05VP_5V
TRIP_+1.05VP
EN_+1.05VP
FB_+1.05VP
RF_+1.05VP
SNB_1.05VP
+1.05VP_B+
B+
+5VALW
+1.05VP
+3VS
+1.05V +1.05VP
SYSON<43,56,59>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
57 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
PWR-+1.05VP
+1.05VP
TDC 4.56A
Peak Current 6.51A
OCP current 7.81A
TYP MAX
H/S Rds(on) :22mohm , 30mohm
L/S Rds(on) :10.8mohm ,13.6mohm
PC306
.1U_0603_25V7K
12
PC309
1000P_0402_50V7K
12
PR306
4.99K_0402_1%
12
PJP301
PAD-OPEN 4x4m
@
1 2
PR307
10K_0402_1%
1 2
PQ303
FDMC7692S_POWER33-8-5
3 5
2
4
1
PC305
4.7U_0805_25V6-K
12
PC308
1U_0603_10V6K
1 2
PR304
4.7_1206_5%
12
PL301
1UH_PCMC063T-1R0MN_11A_20%
1 2
PC302
0.1U_0402_25V6
12
PR305
470K_0402_1%
12
PJP300
JUMP_43X118
@
11
2
2
PR302
69.8K_0402_1%
1 2
PR303
0_0402_5%
1 2
PR300
100K_0402_5%
1 2
PC303
2200P_0402_50V7K
12
+
PC301
330U_2.5V_M
1
2
PQ301
FDMC8884_POWER33-8-5
3 5
2
4
1
PC304
4.7U_0805_25V6-K
12
PU300
TPS51212DSCR_SON10_3X3
EN
3
TRIP
2
V5IN 7
DRVH 9
SW 8
DRVL 6
VBST 10
TST
5
VFB
4
PGOOD
1
TP 11
PR301
2.2_0603_5%
1 2
PC307
0.22U_0402_16V7K
@
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
SNUB_1.5VSP
EN_1.5VSP
1.5VSP_VIN
1.5VSP_FB
1.5VSP_LX +1.5VSP
+1.5VS +1.5VSP
+3VALW
+3VS
SUSP#<10,43,56,59>
Title
Size Document Number Rev
Date: Sheet of
LA-9331P
0.1
PWR-1.5VSP
58 61Friday, June 22, 2012
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
+1.5VSP
TDC 0.66A
Peak Current 0.88A
OCP current 1.06A
PR405
20K_0402_1%
12
PC407
680P_0402_50V7K
@
12
PR401
4.7_0603_5%
@
12
PC400
22U_0805_6.3VAM
12
PL401
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
PC406
.1U_0402_16V7K
@
12
PC405
47P_0402_50V8J
12
PR404
47K_0402_5%
@
12
PC404
22U_0805_6.3VAM
12
PU400
SYN470DBC_DFN10_3X3
EN
5
PG 4
LX 3
FB 6
SVIN
8
TP
11
LX 2
PVIN
10
NC
7
PVIN
9
NC
1
PR403
0_0402_5%
1 2
PC402
22P_0402_50V8J
12
PR402
30.1K_0402_1%
12
PC403
22U_0805_6.3VAM
12
PJP401
PAD-OPEN 1x2m~D@
2 1
PJP400
PAD-OPEN 1x2m~D@
2 1
PC401
0.1U_0402_25V6
12
PR400
10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UGATE2
PHASE2
BOOT2
CPU_B+
UGATE2
UGATE1
PHASE2
BOOT2
LGATE2
CPU_B+
PHASE1
BOOT1
P1_SW
BOOT1
PHASE1
UGATE1
LGATE1
LGATE1
VR_HOT#1
LGATE2
P3_SW
PHASE3
V3N
CPU_B+
UGATE3
SNB_CPU_P1
SNB_CPU_P2
SNB_CPU_P3
CPU_B+
PWM3
SCLK
ALERT#
SDA
VR_ON
VCC_PGOOD
IMON
NTC
FBCOMP
COMP
FB
FB2/VSEN
ISEN3
ISEN2
ISEN1
ISUMP
ISUMN
ISUMN
ISUMP
V1N
ISUMN
V2N
V3N
ISEN1
P2_SW
ISUMP
V1N
V3N
ISEN2
V2N
ISUMN
ISUMP
ISEN3
V1N
V2N
ISUMN
BOOT3
LGATE3
PWM3
VCORE_VDDP
+VCC_CORE
+VCC_CORE
+1.05VS
+VCC_CORE
B+
+VCCIO_OUT
+3VS
+5VALW
+5VS
+5VALW
VR_HOT#<43>
VIDSCLK<10>
VIDALERT_N<10>
VIDSOUT<10>
IMVP_VR_ON<43>
IMVP_PWRGD<6,17,43>
VCCSENSE<10>
VSSSENSE<10>
Title
Size Document Number Rev
Date: Sheet of
LA-9331P
0.1
+VCC_CORE
59 61Friday, June 22, 2012
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
VCC_core (Base on PDDG rev 0.8)
TDC 33A
Peak Current 95A
DC Load line -1.5mV/A
Icc_Dyn_VID1 60A
OCP current 114A
DCR 0.82m ohm
Local sense put on HW site
PR508 0_0402_5%
1 2
PC545
0.082U_0402_16V7K
@
12
PR552
3.65K_0603_1%
1 2
PR510
10K_0603_1%
12
PC505
10U_0805_25V6K
12
PR544
10_0402_1%
12
PC519
1800P_0402_50V8F~D
@
12
PR524
0_0402_5%~D
1 2
PC546
0.01U_0402_50V7K
1 2
PR512
24.9K_0402_1%
1 2
PC506
10U_0805_25V6K
12
PR554
4.7_1206_5%
12
PQ508
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PH500
470K_0402_5%_ TSM0B474J4702RE
12
PC516
2200P_0402_50V7K~D
12
PC528
0.15U_0402_10V6K~D
1 2
PR549
11K_0402_1%
1 2
PR530
1_0402_1%~D
1 2
PL502
0.22UH +-20% PCMB104T-R22MS 35A
1
3
4
2
PC512
10U_0805_25V6K
12
+
PC530
100U_25V_M
1
2
PC523
22P_0402_50V8J~D
@
12
PC543
680P_0603_50V7K
12
PC507
2200P_0402_50V7K~D
12
PR501
0_0402_5%~D
1 2
PR537
2.94K_0402_1%
12
PR506 0_0402_5%
1 2
PR521
100K_0402_1%
12
PC541
330P_0402_50V7K
@
1 2
PR527
0_0402_5%
@
1 2
PR534
2.2_0603_5%
12
PR528
27.4K_0402_1%
12
PR550
2.2_0603_5%
12
PR525
3.83K_0402_1%
1 2
PR541
4.7_1206_5%
12
PC544
0.22U_0402_6.3V6K
12
PR526
0_0402_5%~D
1 2
PQ502
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PQ509
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PR557
10K_0402_1%
@
12
PR523
0_0402_5%~D
@
12
PC514
10U_0805_25V6K
12
PR542
154K_0402_1%
@
1 2
PR507
49.9K_0402_1%~D
1 2
PC502
1U_0603_10V6K
12
PH501
10KB_0402_5%_ERTJ0ER103J
1 2
PC538
0.033U_0603_25V7M~D
1 2
PR531
0_0402_5%
@
1 2
PR504 54.9_0402_1%
12
PR500 110_0402_1%~D
12
PC521
4700P_0402_50V7K~D
12
PC501
0.22U_0603_16V7K
1 2
PR515
10_0402_1%
1 2
PR518
1_0402_5%
@
1 2
PR505 0_0402_5%
1 2
PC504
0.1U_0402_25V6K~D
12
PR532
130K_0402_1%
@
12
PR536
3.65K_0603_1%
1 2
PR522
0_0402_5%~D
1 2
PR553
10K_0603_1%
1 2
PR503 75_0402_5%@
12
PQ512
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PC534
10U_0805_25V6K
12
PC522
0.22U_0603_16V7K
1 2
PQ507
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PR547
1_0402_5%
@
12
PL503
0.22UH +-20% PCMB104T-R22MS 35A
1
3
4
2
PC536
0.1U_0402_25V6K~D
12
PC539
0.22U_0402_6.3V6K
12
PC509
1U_0603_10V6K
1 2
PC510
47P_0402_50V8J~D
12
PC547
.1U_0402_16V7K
12
PC524
680P_0603_50V7K
12
PR513
4.7_1206_5%
12
PQ503
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PC540
0.22U_0402_6.3V6K
12
PC508
680P_0603_50V7K
12
PL501
0.22UH +-20% PCMB104T-R22MS 35A
1
3
4
2
+
PC532
100U_25V_M
1
2
PC513
10U_0805_25V6K
12
PQ501
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PR555
1_0402_5%
@
12
PC533
10U_0805_25V6K
12
PR540
0_0402_5%
1 2
PU500
ISL95812HRZ-T_QFN32_4x4
SCLK
1
VR_ON
2
PGOOD
3
IMON
4
VR_HOT#
5
NTC
6
COMP
7
FB
8
FB2/VSEN
9
ISEN3
10
ISEN2
11
ISEN1
12
RTN
13
ISUMN
14
ISUMP
15
VDD
16
VIN 17
BOOT1 18
UGATE1 19
PHASE1 20
LGATE1 21
PWM3 22
VDDP 23
LGATE2 24
PHASE2 25
UGATE2 26
BOOT2 27
PROG2 28
SLOPE/PROG1 30
SDA 31
ALERT# 32
PAD
33
PROG3 29
PU501
ISL6208BCRZ-T_QFN8_2X2
LGATE 5
PWM
3
GND
4
UGATE 1
VCC
6
FCCM
7
PHASE 8
BOOT 2
TP
9
PQ510
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PR516
1_0402_5%
@
1 2
PR519 1.91K_0402_1%
12
PC542
0.22U_0603_16V7K
1 2
PR502
2.2_0603_5%
12
PR551
2.61K_0402_1%
1 2
PC525
39P_0402_50V8J
1 2
PC511
0.22U_0603_25V7K
12
PL504
FBMA-L11-453215-800LMA90T_1812
1 2
PR539
909_0402_1%
1 2
PR529
0_0402_5%
@
1 2
PQ506
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PC518
1U_0603_10V6K
12
PR545
1.5K_0402_1%
1 2
PC520
390P_0402_50V7K
12
PR533
10_0402_1%
12
PQ505
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PC529
0.1U_0603_25V7K~D
1 2
PR543
2K_0402_1%
1 2
PR520
0_0402_5%~D
1 2
PR548
0_0402_5%
1 2
PC537
2200P_0402_50V7K~D
12
PQ511
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PR514
3.65K_0603_1%
1 2
PC535
10U_0805_25V6K
12
PC515
0.1U_0402_25V6K~D
12
PR511 0_0402_5%
1 2
PR546
1_0402_5%
@
12
PC527
330P_0402_50V7K~D
1 2
PC503
10U_0805_25V6K
12
PR538
10K_0603_1%
1 2
PC526
4700P_0402_50V7K~D
1 2
PC517
39P_0402_50V8J
@
12
+
PC531
100U_25V_M
1
2
PR535
453_0402_1%
12
PR509
34K_0402_1%
1 2
PR556
10_0402_1%
12
PQ504
SIR818DP-T1-GE3_POWERPAK8-5
5
4
2
1
3
PC500
0.01U_0402_50V7K
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DL_CHG
ACSETIN
CSIP
DH_CHG
Back_G1
SNUB_CHG
BST_CHGA
CHG
VDDP_LDO
CSIN
BST
VFB
ISL8731_EAJ
ISL8731_ICREF
DCIN
VDDP_LDO
Back_G2
V1
ACIN
ACIN
V1
LX_CHG
ISL8731_REF
V1
VDDP_LDO
Dis_G
ISL8731_ICREF
ISL8731_REF
Back_G2Back_G1
EC_SMB_DA1<57>
EC_SMB_CK1<57>
VIN
VIN
BATT+
P2 P3
B+
CHG_B+
VIN
BATT+
+5VALW
VIN
VIN
B+
B+_MXM
VIN P2 P3
BATT_TEMP<43,57>
H_PROCHOT#<6,43>
ACIN<17,29,43,47,57>
BATT_TEMP<43,57>
BATT_TEMP<43,57>
ACOFF
<43>
BATT_TEMP
<43,57>
ACOFF
ADP_I<43,57>
ACOFF<43>
VIN+<29>
VIN-<29>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-9331P
0.1
60 61Friday, June 22, 2012
2012/06/22 2013/06/21
Compal Electronics, Inc.
PWR-Charger
Iada=0~4.62A(90W)
CC = 3.52A (Normal)
CV = 13.3V
ADP_I = 19.9*Iadapter*Rsense
For DT Mode
PC702
0.1U_0603_25V7K
12
PQ711
DDTC115EUA-7-F_SOT323
2
13
PC712
1U_0603_25V6K
12
PQ710B
2N7002BKS 2N SOT363-6
3
5
4
PR705
200K_0402_1%
1 2
+
PC736
100U 25V M
1
2
PQ716B
2N7002BKS 2N SOT363-6
@
3
5
4
PR732
0_0402_5%
12
PR738
33K_0402_1%~D
@
12
PR701
3.3_1210_5%
12
PC716
1U_0603_10V6K
1 2
PQ705 SI7149DP
3
2
4
1
5
PC711
0.1U_0402_25V6K~D
1 2
PR736
33K_0402_1%~D
@
12
PU700
ISL88731CHRTZ-T_QFN28_5X5~D
UGATE 24
CSOP 18
PHASE 23
VFB 15
SDA
9
VICM
8
ICREF 1
DCIN
22
ACIN
2
VDDSMB
11
SCL
10
ACOK
13
NC
14
BOOT 25
NC 16
EAO
4
VDDP 21
ICOUT 26
CSSP 28
CSON 17
PGND 19
LGATE 20
FBO
6
EAI
5
CSSN 27
VREF
3
CE
7
GND
12
TP
29
PR740
0.004_2512_1%
1
3
4
2
PL701
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
PQ717B
2N7002BKS 2N SOT363-6
3
5
4
PC703
5600P_0402_25V7K~D
1 2
PC719
680P_0402_50V7K
@
12
PC706
0.1U_0603_25V7K
12
PR723
10K_0402_5%
1 2
PR707
150K_0402_1%
12
PR713
4.7_0603_5%
12
PQ707
PDTA144EU PNP_SOT323
2
1 3
PC720
10U_0805_25V5K~D
12
PR739
33K_0402_1%~D
@
12
PC707
2200P_0402_25V7K~D
12
PR735
33K_0402_1%~D
@
12
PC733
0.01U_0402_25V7K
12
PR709
10_0402_5%
12
PR704
200K_0402_1%
12
PR722
0_0402_5%
12
PC708
0.1U_0402_25V6K~D
1 2
PQ701
SIR472DP-T1-GE3_POWERPAK8-5~D
4
5
1
2
3
PR710
47K_0402_1%
1 2
PC722
10U_0805_25V5K~D
12
PR721
158K_0402_1%
12
PR717
100K_0402_1%
12
PC704
4.7U_0805_25V6-K
12
PR724
0_0402_5%
12
PR725
0.01_1206_1%
1
3
4
2
PR702
200K_0402_1%
12
PC701
2.2U_0805_25V6K
1 2
PQ706SI7149DP
3
2
4
1
5
PL702
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
1 2
PC714
1000P_0402_50V7K
1 2
PC705
4.7U_0805_25V6-K
12
PC715
0.1U_0603_25V7K
1 2
PQ718A
2N7002BKS 2N SOT363-6
61
2
PC710
0.1U_0402_10V7K
@
12
PR711
100K_0402_1%
1 2
PC726
0.22U_0603_25V7K
1 2
PR728
4.7_1206_5%
@
12
PR716
0_0603_5%
1 2
PQ702 SI7149DP
3
2
4
1
5
PQ716A
2N7002BKS 2N SOT363-6
@
61
2
PR703
0.005 +-1% 2512
1
3
4
2
PR730
4.7K_0402_5%
12
PC713
0.047U_0603_25V7M
1 2
PR712
10_1206_1%
1 2
PC732
.1U_0402_16V7K
1 2
PQ703SI7149DP
3
2
4
1
5
PC734
0.01U_0402_25V7K
@
12
PR719
49.9K_0402_1%
1 2
PC728
0.1U_0402_10V7K
@
12
G
D
S
PQ715
SSM3K7002FU_SC70-3
@
2
13
PR731
10_0402_5%
12
PR708
10_0402_5%
12
PQ714
FDMC7692S_POWER33-8-5
3 5
2
4
1
PR729
100_0402_1%
1 2
PR715
210K_0402_1%
1 2
PR720
47K_0402_5%
1 2
PC723
10U_0805_25V5K~D
@
12
PQ713
DDTC115EUA-7-F_SOT323
2
13
PC721
10U_0805_25V5K~D
12
PC729
1U_0603_25V6K
@
12
PC717
0.1U_0402_10V7K
12
PC709
1U_0603_10V6K
1 2
+
PC737
100U 25V M
1
2
PQ709
DDTC115EUA-7-F_SOT323
2
13
PR706
3.3_1210_5%
12
PR737
3.3K_1206_5%~D
12
PQ718B
2N7002BKS 2N SOT363-6
3
5
4
PC735
0.01U_0402_25V7K
12
PQ717A
2N7002BKS 2N SOT363-6
61
2
PR734
100_0402_5%
1 2
PQ704SI7149DP
3
2
4
1
5
PQ710A
2N7002BKS 2N SOT363-6
61
2
PL703
SMB3025500YA_2P
1 2
PC731
0.1U_0402_25V6K~D
@
1 2
PR714
10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE
+VCC_CORE+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
LA-9331P
0.1
PROCESSOR DECOUPLING
61 61Friday, June 22, 2012
Compal Electronics, Inc.
Based on PDDG rev 0.8 Table 5-1.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
PC911
10U_0805_4VAM
1
2
+
PC906
470U_D2_2VM_R4.5M~D
1
2
PC900
10U_0805_4VAM
1
2
PC926
22U_0805_6.3VAM
1
2
PC918
22U_0805_6.3VAM
1
2
PC922
22U_0805_6.3VAM
1
2
PC912
10U_0805_4VAM
1
2
PC903
10U_0805_4VAM
1
2
PC937
22U_0805_6.3VAM
1
2
PC904
10U_0805_4VAM
1
2
PC935
22U_0805_6.3VAM
1
2
PC913
10U_0805_4VAM
1
2
+
PC905
470U_D2_2VM_R4.5M~D
1
2
PC909
10U_0805_4VAM
1
2
PC940
22U_0805_6.3VAM
1
2
PC924
22U_0805_6.3VAM
1
2
PC914
10U_0805_4VAM
1
2
PC923
22U_0805_6.3VAM
1
2
PC920
22U_0805_6.3VAM
1
2
PC943
22U_0805_6.3VAM
1
2
PC902
10U_0805_4VAM
1
2
+
PC907
470U_D2_2VM_R4.5M~D
1
2
PC939
22U_0805_6.3VAM
1
2
PC941
22U_0805_6.3VAM
1
2
PC901
10U_0805_4VAM
1
2
PC919
22U_0805_6.3VAM
1
2
PC942
22U_0805_6.3VAM
1
2
PC925
22U_0805_6.3VAM
1
2
+
PC915
470U_D2_2VM_R4.5M~D
1
2
PC921
22U_0805_6.3VAM
1
2
PC938
22U_0805_6.3VAM
1
2
PC910
10U_0805_4VAM
1
2
PC936
22U_0805_6.3VAM
1
2
+
PC908
470U_D2_2VM_R4.5M~D
1
2
PC917
22U_0805_6.3VAM
1
2
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