Compal LA 9331P Schematics. Www.s Manuals.com. Rx00 Schematics
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A 1 B C D E MODEL NAME : RANGER 17 PCB NO : LA-9331P BOM P/N : 4619KL31L01 1 Compal Confidential 2 2 RANGER 17 Schematic Document Rev: X00 2012-06-22 3 3 @ : Nopop Component 4 4 Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 1 of 61 A B LVDS Mux PI3LVD1012 LVDS Conn. P.39 eDP Conn. 1 P.39 eDP MUX PS8321 P.30 P.30 LVDS Mux PI3LVD1012 C D E eDP to LVDS RTD2136 P.37 P.38 eDP deMux PS8338 P.28 eDP MUX PS8321 P.29 FFS P.46 LNG3DMTR 4-lane eDP DP/HDMI 4C 47W/57W Scoket G3 rPGA-947 eDP PEGx16 Gen 3 LVDS CPU XDP Conn. P.7 Intel Haswell Processor HDMI LVDS to DP SW STDP4028 P.35 Fan Control EMC1412 P.51 1 Memory Bus DDRIII Dual Channel 204pin DDRIII SO-DIMM x4 BANK 0, 1, 2, 3 P.13, 14, 15, 16 1.35V DDRIII 1600 MHz MXM III HDMI to LVDS SW STDP6038 P.34 HDMI Redriver PS121 P.33 2 HDMI 1.3 Input HDMI 1.4a Output P.32 Conn. HDMI Conn. LVDS Mux PI3LVD1012 P.31 P.6, 7, 8, 9, 10, 11, 12 DP1.2 DMI x4 100MHz 5GT/s DP/HDMI HDMI MUX PS8271 P.33 P.26 USB3.0 Rediver PS8713 P.49 USB3.0 USB 2.0 USB3.0 Rediver PS8713 P.49 USB3.0 USB 2.0 HDMI SW TS3DV421 P.32 USB 3.0/USB 2.0 Conn. 2 DP Redriver PS8330 P.27 P.27 Intel USB3.0 USB 2.0 USB3.0 Rediver PS8713 USB 3.0/USB 2.0 Conn. USB3.0 Rediver PS8713 USB 3.0/USB 2.0 Conn. Mini Card #1(Half) USB2.0 PCI-E 2.0 WLAN/WiMax BT4.0+LE/WiGig HDMI Redriver PS121 P.36 Lynx Point HDMI MUX PS8271 P.36 DMC USB2.0 PCI-E 2.0 Display MiniCard P.48 3 RJ45 Conn. USB3.0 Daughter Board LAN(GbE) E2201 Killer PCI-E 2.0 Card Reader RTS5209 PCI-E 2.0 USB2.0 PCH USB2.0 HM87 USB2.0 BGA 695 Balls 9 in 1 Conn. Card Reader Board SATA 3.0 SATA 3.0 Digital Camera P.54 SATA 3.0 P.50 SPI SPI ROM P.20 8MB RTC conn. HDD Conn. 2 3 P.46 P.47 of ODD) SATA Rediver PS8520BT P.47 ODD Conn. SATA Rediver PS8520BT P.47 Mini Card #3(Full) mSATA P.47 P.47 ( iPhone & Nokia compatible) P.42 HD Audio Audio Codec ALC3661 ENE KB9012 P.40 P.52 P.46 Combo Jack LPC Bus ENE KC3810 with LVDS Panel P.45,46 HDD Conn. 1 SATA Rediver PS8520BT P.46 with eDP Panel P.52 HDD Conn. 3 In ODD Bay (In place SATA 3.0 4 P.30 3D IR P.17, 18, 19, 20, 21, 22, 23, 24, 25 Power On/Off CKT. Digital Camera AlienFX/ELC P.41 P.50 P.50 USB3.0 Daughter Board USB2.0 P.48 P.49 P.49 USB3.0 USB 2.0 miniDP Conn. USB 3.0/USB 2.0 Conn. ( USB Charger Port ) P.40 DC/DC Interface CKT. Headphone Jack P.42 Headphone Jack P.42 Array Mics P.30 Array Mics P.39 Camera with eDP Panel 4 P.42 P.53 VPK MCU Int.KBD Touch Pad TI TPA3113D2 Power Circuit DC/DC P.54, 55, 56, 57, 58, 59, 60, 61 P.50 VPK Daughter Board Int. Speaker (2.5W*4) P.43 Compal Secret Data Security Classification Issued Date P.43 Camera with LVDS Panel 2012/06/22 Deciphered Date 2013/06/21 Title Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 2 of 61 A B C D E Compal Confidential Project Code : VAS00 File Name : LA-9331P LA-9331P M/B 1 Camera 50pin B To B conn. LS-9335P POWER BUTTON/B 1 LCD Panel 44 pin Coaxial/Wire Combo on/off SW Led x 2 Hot Bar 22 pin FFC 6 pin HDD2 conn. LS-9336P INDICATOR/B 20 pin Led-HDD 2 FFC FFC 30 pin LS-9337P CardReader /B 22 pin Led-CapsLock Lid ODD HDD3 20 pin Led-Wireless LF-XXXXP FPC HDD1 conn. 2 HDD in ODD Bay Cable Card Slot FFC 60 pin Wire 12pin KSI/KSO LS-9338P VPK Daughter/B 30 pin PWM Hot Key 6 pin 10 pin VPK Keyboard VPK MCU 40 pin MAX7313 RJ45 LS-9334P USB3.0 LOGO /B Key Pad Led x 2 Backlight / 8 Pressure-sense Analog Signals FFC 3 16 pin USB3.0 Wire Wire Wire 6pin 6pin 6pin Hot Bar Hot Bar LS-9333P LS-9331P Alien Slits-R Light/B Alien head badge/B Touch Pad To M/B Tron Light To USB30/B FFC L Wire 3 Hot Bar LS-9332P Alien Slits-L Light/B Led x 2 50pin B To B conn. Led x 2 R Wire 6pin 6pin To M/B LS-933BP Tron L/B Led x 2 4 pin LS-9339P USB30 /B LS-933CP Tron R/B Wire 10pin Led x 1 Led x 1 4 4 LS-933DP Tron FL/B LS-933EP Tron FR/B Led x 1 Led x 1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 2013/06/21 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Block Diagram Document Number Rev 0.1 Friday, June 22, 2012 Sheet E 3 of 61 A USB 3.0 PORT Board ID Table for AD channel Vcc Ra Board ID 0 1 2 3 4 5 6 7 3.3V +/100K +/Rb 0 8.2K +/18K +/33K +/56K +/100K +/200K +/NC 5% 5% BOARD ID Table V AD_BID min 0 V 0.168 V 0.375 V 0.634 V 0.958 V 1.372 V 1.851 V 2.433 V 5% 5% 5% 5% 5% 5% V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0.155 V 0.362 V 0.621 V 0.945 V 1.359 V 1.838 V 2.420 V 3.300 V EC AD3 0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF Board ID 0 1 2 3 4 5 6 7 PCB Revision 0.1 (SSI) 0.2 (PT) 0.3 (ST) 0.4 (QT) 1.0 (MP) Connetion 1 JUSB1 (Left side) 2 JUSB2 (Left side) 3 NA 4 NA 5 JUSB3 (Right side) 6 JUSB4 (Right side) USB PORT# DESTINATION PM TABLE POWER STATES Signal SLP S3# State S0 (Full ON) / M0 SLP S4# HIGH HIGH SLP S5# HIGH S4 STATE# HIGH SLP M# ALWAYS PLANE HIGH SUS PLANE ON ON RUN PLANE +5VS CLOCKS ON +5VALW power plane ON +3VS +3VALW +1.35V +1.5VS +3VLP +1.05V +1.05VS +3V_PCH S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON ON OFF USB2.0 +0.675VS OFF +3VMXM +5VMXM S4 (Suspend to DISK) / M-OFF S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW HIGH LOW LOW LOW LOW ON LOW OFF ON OFF OFF OFF OFF +VCC_CORE State +1.35V_CPU_VDDQ OFF Symbol Note : S0 ON ON ON S3 ON ON OFF S5 S4/AC ON OFF OFF S5 S4/AC don't exist OFF OFF OFF : means Digital Ground : means Analog Ground 0 JUSB1(USB3.0 P1) 1 JUSB2(USB3.0 P2) 2 JUSB3(USB3.0 P5) 3 JUSB4(USB3.0 P6) 4 JMINI1 (WLAN) 5 JMINI2 (DMC) 6 AlienFX/ELC 7 IR SENSOR 8 None 9 None 10 None 11 eDP CAMERA 12 LVDS CAMERA 13 VPK K/B 1 1 DIFFERENTIAL CLKOUT_PCIE0 CLK DESTINATION FLEX CLOCKS MINI CARD-1 WLAN DESTINATION CLKOUT_PCIE1 MINI CARD-2 DMC CLKOUTFLEX1 None CLKOUT_PCIE2 10/100/1G LAN CLKOUTFLEX2 None CLKOUT_PCIE3 CLKOUT_PCIE4 CARD READER SATAIII DESTINATION SATA0 HDD1 SATA1 HDD2 DESTINATION SATA2 ODD PCI0 PCH_LOOPBACK SATA3 mSATA CLKOUT_PCIE6 PCI1 EC SATA4/PCIE LANE1 MINI CARD-1 WLAN CLKOUT_PCIE7 PCI2 80port debug card SATA5/PCIE LANE2 MINI CARD-2 DMC CLKOUT_PEG_A PCI3 None PCI4 None None CLKOUTFLEX3 None CLKOUT CLKOUT_PCIE5 PCI EXPRESS None CLKOUTFLEX0 None None None MXM DESTINATION Lane 1/USB3.0 Port 3 None Lane 2/USB3.0 Port 4 None Lane 3 10/100/1G LAN Lane 4 CARD READER Lane 5 None Lane 6 None Lane 7 None Lane 8 None SMBUS Control Table SOURCE EC_SMB_CK1 EC_SMB_DA1 KB9012 EC_SMB_CK2 EC_SMB_DA2 KB9012 PCH_SML0CLK PCH_SML0DATA PCH PCH_SML1CLK PCH_SML1DATA PCH MEM_SMBCLK MEM_SMBDATA PCH WLAN DMC BATT DIMM 6038 4028 Thermal Sensor FFS 2136 VPK MCU V MXM XDP V V V V V Charger TP mSATA V V Link Compal Secret Data Security Classification V V V V V V Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A Friday, June 22, 2012 Sheet 4 of 61 5 4 SMBUS Address [TBD] 3 2.2K PCH MEM_SMBCLK U11 MEM_SMBDATA U8 SML0CLK R7 SML0DATA 1 2.2K +3VS +3V_PCH 2.2K R10 2 +3VS 2.2K QH9A PCH_SMBCLK 202 PCH_SMBDATA 200 QH9B D K6 DIMM1 SMBUS Address [A2] DIMM2 SMBUS Address [A6] DIMM3 SMBUS Address [A0] 202 2.2K 200 D +3V_PCH 2.2K 202 200 N11 2.2K SML1CLK 202 SML1DATA +3V_PCH 2.2K 200 DIMM4 SMBUS Address [A4] 4.7K +3VS 4.7K +3VS +DVCC33 0 Ω QH9B QH9A QV2B EC_SMB_CK2 CSCL EC_SMB_DA2 CSDA 0 Ω 0 Ω CIICSCL 111 CIICSDA 112 RTD2136S 4 +3VS EC_SMB_DA2 EC_SMB_DA2_R STDP6038 71 EC_HDMI_DAT 0 Ω VPK_SMB_CK2 43 VPK_SMB_DA2 42 MSP430F5508 Thermal sensor 8 ADM1032 7 C SMBUS Address [TBD] SMBUS Address [TBD] 30 32 0 Ω VPK 0 Ω MINI2_SMBCLK SMBUS Address [TBD] 22 Ω 0 Ω KBC 0 Ω 72 EC_HDMI_CLK mSATA SMBUS Address [TBD] HDMI IN 22 Ω EC_SMB_CK2_R 80 STDP4028 EC_HDMI_CLK_R C13 0 Ω SDA2 32 EC_HDMI_DAT_R B14 LNG3DM 30 LVDS transfer DP 0 Ω 0 Ω 6 +3VS 4.7K EC_SMB_CK2 SMBUS Address [TBD] G sensor 2.2K 79 XDP SMBUS Address [TBD] 4.7K C SCL2 DDR_XDP_SMBDAT_R1 51 0 Ω QV2A 2.2K DDR_XDP_SMBCLK_R1 53 DMC SMBUS Address [TBD] MINI2_SMBDATA 15 16 SMBUS Address [0FFFFh to 0FF80h] Touch pad SMBUS Address [TBD] MXM FAN CONTROL SMBUS Address [100_1100] B B Thermal sensor 8 2.2K 2.2K SCL1 77 EC_SMB_CK1 SDA1 78 EC_SMB_DA1 +3VALW_EC KB9012 ADM1032 7 SYSTEM FAN CONTROL SMBUS Address [100_1100] 4.7K +3V_MXM 4.7K QV8 +3V_MXM VGA_SMB_CK1 70 VGA_SMB_DA1 68 MXM1 CONN SMBUS Address [] QV6 0 Ω 0 Ω MXM Current Monitor MXM_CURI2C_CLK 5 MXM_CURI2C_DATA 6 100 Ω CLK_SMB A 100 Ω DAT_SMB HPA00900 SMBUS Address [] 4 5 BATT CONN A SMBUS Address [] 0 Ω PU700 0 Ω SMBUS Address [000_1001] Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. SMBus block diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 5 of 61 5 4 3 2 1 +VCOMP_OUT D PEG_COMP 2 24.9_0402_1%~D D 1 RC2 CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils. PEG_GTX_HRX_P[0..15] <29> PEG_GTX_HRX_N[0..15] <29> PEG_HTX_C_GRX_P[0..15] <29> PEG_HTX_C_GRX_N[0..15] <29> Haswell rPGA EDS D21 C21 B21 A21 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 D20 C20 B20 A20 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D18 C17 B17 A17 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D17 C18 B18 A18 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <17> <17> <17> <17> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 <17> <17> <17> <17> <17> <17> <17> <17> RC3 RC87 2 2 1 0_0402_5%~D 1 0_0402_5%~D FDI_CSYNC_R FDI_INT_R H29 J29 FDI_CSYNC FDI_INT FDI <17> FDI_CSYNC <17> FDI_INT DMI C DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <17> <17> <17> <17> PEG JCPU1A B PEG_RCOMP PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8 PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15 PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15 PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8 PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15 PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15 E23 M29 K28 M31 L30 M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29 L28 L31 K30 L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24 PEG_COMP PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P15 PEG_HTX_GRX_N0 PEG_HTX_GRX_N1 PEG_HTX_GRX_N2 PEG_HTX_GRX_N3 PEG_HTX_GRX_N4 PEG_HTX_GRX_N5 PEG_HTX_GRX_N6 PEG_HTX_GRX_N7 PEG_HTX_GRX_N8 PEG_HTX_GRX_N9 PEG_HTX_GRX_N10 PEG_HTX_GRX_N11 PEG_HTX_GRX_N12 PEG_HTX_GRX_N13 PEG_HTX_GRX_N14 PEG_HTX_GRX_N15 PEG_HTX_GRX_P0 PEG_HTX_GRX_P1 PEG_HTX_GRX_P2 PEG_HTX_GRX_P3 PEG_HTX_GRX_P4 PEG_HTX_GRX_P5 PEG_HTX_GRX_P6 PEG_HTX_GRX_P7 PEG_HTX_GRX_P8 PEG_HTX_GRX_P9 PEG_HTX_GRX_P10 PEG_HTX_GRX_P11 PEG_HTX_GRX_P12 PEG_HTX_GRX_P13 PEG_HTX_GRX_P14 PEG_HTX_GRX_P15 CC1 CC2 CC3 CC4 CC5 CC13 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC14 CC15 CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC32 CC33 CC34 CC35 CC36 CC37 CC38 CC39 CC40 CC41 CC42 CC43 CC44 CC45 CC46 CC47 CC48 CC49 CC50 CC51 CC52 CC53 CC54 CC55 CC56 CC57 CC58 CC59 CC60 CC61 CC62 CC63 CC64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_GTX_HRX_N0 PEG_GTX_HRX_N1 PEG_GTX_HRX_N2 PEG_GTX_HRX_N3 PEG_GTX_HRX_N4 PEG_GTX_HRX_N5 PEG_GTX_HRX_N6 PEG_GTX_HRX_N7 PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15 PEG_GTX_HRX_P0 PEG_GTX_HRX_P1 PEG_GTX_HRX_P2 PEG_GTX_HRX_P3 PEG_GTX_HRX_P4 PEG_GTX_HRX_P5 PEG_GTX_HRX_P6 PEG_GTX_HRX_P7 PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15 C B Near MXM Connector 1 OF 9 INTEL_HASWELL_HASWELL CONN@ A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. CPU (1/7) DMI,PEG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 6 of 61 5 4 3 2 1 +VCCIO_OUT CC156 1 2 5 +VCCIO_OUT 2 1 1 @ 2 G 3 <10,56> RUN_ON_CPU1.5VS3# 1 PM_DRAM_PWRGD_CPU 0_0402_5%~D 1 @ RC125 2 XDP_PREQ#_R XDP_PRDY#_R SYS_PWROK_XDP 1K_0402_1%~D <9> <9> CFG0 CFG1 CFG0 CFG1 <9> <9> CFG2 CFG3 CFG2 CFG3 <9> <9> CFG4 CFG5 CFG4 CFG5 <9> <9> CFG6 CFG7 CFG6 CFG7 XDP_OBS0 XDP_OBS1 RC5 need to close to JCPU1 H_CPUPWRGD D <17,43> PBTN_OUT# 2 1K_0402_1%~D H_CPUPWRGD_XDP 2 0_0402_5%~D CFD_PWRBTN#_XDP 1 1 RC8 1 RC12 1 <10> CPU_PWR_DEBUG <17,43,62> IMVP_PWRGD S RC5 RC6 RC126 RC127 <12,13,14,15,19,49,50,51,53> PCH_SMBDATA <12,13,14,15,19,49,50,51,53> PCH_SMBCLK 1 1 +VCCIO_OUT JXDP1 RC14 3.3K_0402_1%~D 1 0_0402_5%~D @ QC1 SSM3K7002FU_SC70-3~D @ RC64 39_0402_5%~D 3 1 RC28 UC2 74AHC1G09GW_TSSOP5~D 2 RC94 2 2 A 2 200_0402_1%~D 2 Place near JXDP1 +3V_PCH RUNPWROK_AND 4 O 2 1 RC18 1 P B 0_0402_5%~D <17> PM_DRAM_PWRGD +3V_PCH 2 0.1U_0402_25V6K~D 1 1 RC88 1 @ +3V_PCH G 2 <17> SYS_PWROK 2 RC16 1.8K_0402_1% 2 D RC89 100K_0402_5%~D 1 +1.35V_CPU_VDDQ CC66 0.1U_0402_25V6K~D 1 +3V_PCH CC65 0.1U_0402_25V6K~D SM_DRAMPWROK with DDR Power Gating Topology 2 0_0402_5%~D 2 0_0402_5%~D CPU_PWR_DEBUG_R SYS_PWROK_XDP 2 0_0402_5%~D 2 0_0402_5%~D DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1 XDP_TCLK_R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 SAMTE_BSH-030-01-L-D-A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 D CFG17 CFG16 CFG17 CFG16 CFG8 CFG9 CFG8 CFG9 <9> <9> CFG10 CFG11 CFG10 CFG11 <9> <9> CFG19 CFG18 CFG19 CFG18 <9> <9> CFG12 CFG13 CFG12 CFG13 <9> <9> CFG14 CFG15 CFG14 CFG15 CLK_XDP CLK_XDP# RC144 RC145 XDP_RST#_R XDP_DBRESET# <9> <9> <9> <9> 1 1 2 0_0402_5%~D 2 0_0402_5%~D 2 1 RC9 CLK_CPU_ITP <18> CLK_CPU_ITP# <18> CPU_PLTRST#_R 1K_0402_1%~D XDP_TDO XDP_TRST#_R XDP_TDI XDP_TMS_R CONN@ +VCCIO_OUT 2 1 2 H_THERMTRIP# 56_0402_5%~D H_CATERR# 49.9_0402_1%~D H_PROCHOT# 62_0402_5%~D RC44 Haswell rPGA EDS JCPU1B AP32 1 1 AN32 AR27 AK31 AM30 AM35 place RC134 near CPU H_PM_SYNC VCCPWRGOOD_0_R 2 0_0402_5%~D PM_DRAM_PWRGD_CPU CPU_PLTRST#_R 1 RC25 2 2 2 2 2 2 1 1 1 1 1 1 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CPU_DMI# CPU_DMI G28 H28 F27 E27 D26 E26 PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP CLOCK RC51 RC52 RC43 RC22 RC15 RC13 <18> CLK_CPU_DPLL# <18> CLK_CPU_DPLL <18> CLK_CPU_SSC_DPLL# <18> CLK_CPU_SSC_DPLL <18> CLK_CPU_DMI# <18> CLK_CPU_DMI AT28 AL34 AC10 AT26 CATERR PECI RSVD PROCHOT THERMTRIP PWR <17> H_PM_SYNC <21> H_CPUPWRGD C MISC THERMAL H_CATERR# H_PECI PAD~D T66 @ 2 56_0402_5%~D H_PROCHOT#_R 2 0_0402_5%~D H_THERMTRIP#_R <21,43> H_PECI RC57 RC134 <43,63> H_PROCHOT# <21> H_THERMTRIP# SKTOCC INTEL_HASWELL_HASWELL PRDY PREQ TCK TMS TRST TDI TDO DBR BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7 AP3 AR3 AP2 AN3 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR3_DRAMRST#_CPU AR29 AT29 AM34 AN33 AM33 AM31 AL33 AP33 XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI_R XDP_TDO_R XDP_DBRESET#_R RC50 RC36 RC46 RC47 RC48 RC23 RC24 RC26 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDP_PRDY#_R XDP_PREQ#_R XDP_TCLK_R XDP_TMS_R XDP_TRST#_R XDP_TDI XDP_TDO XDP_DBRESET# AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R RC30 RC31 RC33 RC34 RC37 RC40 RC38 RC39 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDP_OBS0 XDP_OBS1 DDR3_DRAMRST#_CPU <12> XDP_DBRESET# <17> For ESD concern, please put near CPU 2 OF 9 CONN@ +VCCIO_OUT CPU_SSC_DPLL 1 10K_0402_5%~D CPU_SSC_DPLL# 1 10K_0402_5%~D SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST DDR3 2 1 @ RC128 JTAG 1 @ RC136 C 2 RC20 @ 2 RC21 @ PU/PD for JTAG signals +3VS B SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21 XDP_DBRESET#_RRC19 2 B 1 1K_0402_1%~D +1.05VS VCCPWRGOOD_0_R +3VS NC VCC A GND Y 5 4 2 2 RC17 1K_0402_1%~D 2 UC1 1 2 3 <17,43,44,51,53> PLT_RST# CC140 0.1U_0402_25V6K~D 1 1 +1.05VS PCH_PLTRST#_BUF CRB Rev 0.7 no pull up DDR3 COMPENSATION SIGNALS 2 @ RC54 2 43_0402_5%~D 1 0_0402_5%~D CPU_PLTRST#_R CAD Note: Avoid stub in the PWRGD path while placing resistors RC25 & RC130 2 RC11 20K_0402_5%~D 1 SN74LVC1G07DCKR_SC70-5~D CAD Note: PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU XDP_TDI_R @ RC27 2 1 51_0402_1%~D RC29 2 1 51_0402_1%~D @ RC32 2 1 51_0402_1%~D XDP_PREQ# XDP_TDO_R RC35 2 1 51_0402_1%~D CRB Rev 0.7 is depop 1 RC10 RC135 10K_0402_5%~D 1 XDP_TMS Buffered reset to CPU <21> CPU_PLTRST# RC53 2 SM_RCOMP0 RC45 1 2 100_0402_1%~D XDP_TCLK RC42 2 1 51_0402_1%~D SM_RCOMP1 RC55 1 2 75_0402_1%~D XDP_TRST# RC41 2 1 51_0402_1%~D SM_RCOMP2 RC49 1 2 100_0402_1%~D CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil 1 0_0402_5%~D A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. CPU (2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 7 of 61 5 4 3 2 1 Haswell rPGA EDS JCPU1C D <12,14> DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B +V_SM_VREF +DIMM0_1_VREF +DIMM0_1_CA AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15 AM9 AN9 AM8 AN8 AR9 AT9 AR8 AT8 AJ9 AK9 AJ6 AK6 AJ10 AK10 AJ7 AK7 AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2 J1 J2 J5 H5 H2 H1 J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6 E12 D12 B11 A11 E11 D11 B12 A12 AM3 F16 F13 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ Haswell rPGA EDS @ T67 RSVD_AC7 SA_CK_N_0 SA_CK_P_0 SA_CKE_0 SA_CK_N_1 SA_CK_P_1 SA_CKE_1 SA_CK_N_2 SA_CK_P_2 SA_CKE_2 SA_CK_N_3 SA_CK_P_3 SA_CKE_3 AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8 M_CLK_DDR#0 M_CLK_DDR0 DDR_CKE0_DIMMA M_CLK_DDR#1 M_CLK_DDR1 DDR_CKE1_DIMMA M_CLK_DDR#4 M_CLK_DDR4 DDR_CKE4_DIMMC M_CLK_DDR#5 M_CLK_DDR5 DDR_CKE5_DIMMC SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3 SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3 SA_BS_0 SA_BS_1 SA_BS_2 M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS4_DIMMC# DDR_CS5_DIMMC# M_ODT0 M_ODT1 M_ODT4 M_ODT5 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 RSVD_V10 SA_RAS SA_WE SA_CAS V10 U6 U7 U8 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15 V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AP15 AP8 AJ8 AF3 J3 E2 C5 C11 AP14 AP9 AK8 AG3 H3 E3 C6 C12 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 M_CLK_DDR#0 <14> M_CLK_DDR0 <14> DDR_CKE0_DIMMA <14> M_CLK_DDR#1 <14> M_CLK_DDR1 <14> DDR_CKE1_DIMMA <14> M_CLK_DDR#4 <12> M_CLK_DDR4 <12> DDR_CKE4_DIMMC <12> M_CLK_DDR#5 <12> M_CLK_DDR5 <12> DDR_CKE5_DIMMC <12> DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14> DDR_CS4_DIMMC# <12> DDR_CS5_DIMMC# <12> M_ODT0 <14> M_ODT1 <14> M_ODT4 <12> M_ODT5 <12> DDR_A_BS0 <12,14> DDR_A_BS1 <12,14> DDR_A_BS2 <12,14> DDR_A_RAS# <12,14> DDR_A_WE# <12,14> DDR_A_CAS# <12,14> DDR_A_MA[0..15] <12,14> DDR_A_DQS#[0..7] DDR_A_DQS[0..7] <12,14> <12,14> AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11 AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6 AJ4 AK4 AJ1 AJ2 AM1 AN1 AK2 AK1 L2 M2 L4 M4 L1 M1 L5 M5 G7 J8 G8 G9 J7 J9 G10 J10 A8 B8 A9 B9 D8 E8 D9 E9 E15 D15 A15 B15 E14 D14 A14 B14 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 4 OF 9 3 OF 9 D JCPU1D <13,15> DDR_B_D[0..63] PAD~D RSVD SB_CKN0 SB_CK0 SB_CKE_0 SB_CKN1 SB_CK1 SB_CKE_1 SB_CKN2 SB_CK2 SB_CKE_2 SB_CKN3 SB_CK3 SB_CKE_3 SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3 SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3 SB_BS_0 SB_BS_1 SB_BS_2 RSVD SB_RAS SB_WE SB_CAS SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15 SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7 @ T76 AG8 M_CLK_DDR#2 Y4 AA4 M_CLK_DDR2 DDR_CKE2_DIMMB AF10 M_CLK_DDR#3 Y3 AA3 M_CLK_DDR3 AG10 DDR_CKE3_DIMMB M_CLK_DDR#6 Y2 AA2 M_CLK_DDR6 AG9 DDR_CKE6_DIMMD M_CLK_DDR#7 Y1 AA1 M_CLK_DDR7 AF9 DDR_CKE7_DIMMD P4 R2 P3 P1 DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_CS6_DIMMD# DDR_CS7_DIMMD# R4 R3 R1 P2 R7 P8 AA9 M_ODT2 M_ODT3 M_ODT6 M_ODT7 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 PAD~D M_CLK_DDR#2 <15> M_CLK_DDR2 <15> DDR_CKE2_DIMMB <15> M_CLK_DDR#3 <15> M_CLK_DDR3 <15> DDR_CKE3_DIMMB <15> M_CLK_DDR#6 <13> M_CLK_DDR6 <13> DDR_CKE6_DIMMD <13> M_CLK_DDR#7 <13> M_CLK_DDR7 <13> DDR_CKE7_DIMMD <13> DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_CS6_DIMMD# DDR_CS7_DIMMD# M_ODT2 M_ODT3 M_ODT6 M_ODT7 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 R10 DDR_B_RAS# R6 DDR_B_WE# P6 DDR_B_CAS# P7 R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AP18 AP11 AP5 AJ3 L3 H9 C8 C14 AP17 AP12 AP6 AK3 M3 H8 C9 C15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 <15> <15> <13> <13> <15> <15> <13> <13> <13,15> <13,15> <13,15> DDR_B_RAS# <13,15> DDR_B_WE# <13,15> DDR_B_CAS# <13,15> DDR_B_MA[0..15] <13,15> DDR_B_DQS#[0..7] <13,15> DDR_B_DQS[0..7] <13,15> C B INTEL_HASWELL_HASWELL INTEL_HASWELL_HASWELL CONN@ CONN@ +1.35V +V_SM_VREF 1 1 1 1 RC149 24.9_0402_1% A 2 2 2 2 2 1 1 0_0402_5% 2 0_0402_5% 2 RC151 24.9_0402_1% 2 RC150 24.9_0402_1% CC138 0.022U_0402_25V7K~D 2 2 1 CC137 0.022U_0402_25V7K~D 1 CC139 0.022U_0402_25V7K~D 2 RC81 1K_0402_1%~D A 0_0402_5% 1 RC82 1K_0402_1%~D 1 RC148 2 1 1 +DIMM0_1_VREF_CPU +V_SM_VREF_CNT 2 RC147 1 +DIMM0_1_VREF +DIMM0_1_CA_CPU RC146 RC78 1K_0402_1%~D 2 +DIMM0_1_CA RC95 1K_0402_1%~D RC96 1K_0402_1%~D 1 2 +1.35V RC86 1K_0402_1%~D 1 +1.35V Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. CPU (3/7) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 8 of 61 5 4 3 2 1 COMPENSATION PU FOR eDP +VCOMP_OUT EDP_COMP 2 24.9_0402_1%~D D 1 RC1 D CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils. Haswell rPGA EDS HDMI C DMC <36> <36> <36> <36> <36> <36> <36> <36> <39> <39> <39> <39> <39> <39> <39> <39> CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N3 CPU_HDMI_P3 CPU_DPD_DMC_N0 CPU_DPD_DMC_P0 CPU_DPD_DMC_N1 CPU_DPD_DMC_P1 CPU_DPD_DMC_N2 CPU_DPD_DMC_P2 CPU_DPD_DMC_N3 CPU_DPD_DMC_P3 CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N3 CPU_HDMI_P3 CPU_DPD_DMC_N0 CPU_DPD_DMC_P0 CPU_DPD_DMC_N1 CPU_DPD_DMC_P1 CPU_DPD_DMC_N2 CPU_DPD_DMC_P2 CPU_DPD_DMC_N3 CPU_DPD_DMC_P3 T28 U28 T30 U30 U29 V29 U31 V31 DDIB_TXBN_0 DDIB_TXBP_0 DDIB_TXBN_1 DDIB_TXBP_1 DDIB_TXBN_2 DDIB_TXBP_2 DDIB_TXBN_3 DDIB_TXBP_3 T34 U34 U35 V35 U32 T32 U33 V33 DDIC_TXCN_0 DDIC_TXCP_0 DDIC_TXCN_1 DDIC_TXCP_1 DDIC_TXCN_2 DDIC_TXCP_2 DDIC_TXCN_3 DDIC_TXCP_3 P29 R29 N28 P28 P31 R31 N30 P30 DDID_TXDN_0 DDID_TXDP_0 DDID_TXDN_1 DDID_TXDP_1 DDID_TXDN_2 DDID_TXDP_2 DDID_TXDN_3 DDID_TXDP_3 JCPU1H eDP EDP_AUXN EDP_AUXP EDP_HPD EDP_RCOMP RSVD M27 N27 P27 E24 R27 EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1 P35 R35 N34 P34 P33 R33 N32 P32 CPU_EDP_AUX# CPU_EDP_AUX EDP_HPD EDP_COMP CPU_EDP_AUX# <31> CPU_EDP_AUX <31> PAD~D T77 @ CPU_EDP_N0 CPU_EDP_P0 CPU_EDP_N1 CPU_EDP_P1 CPU_EDP_N2 CPU_EDP_P2 CPU_EDP_N3 CPU_EDP_P3 CPU_EDP_N0 CPU_EDP_P0 CPU_EDP_N1 CPU_EDP_P1 CPU_EDP_N2 CPU_EDP_P2 CPU_EDP_N3 CPU_EDP_P3 <31> <31> <31> <31> <31> <31> <31> <31> C DDI INTEL_HASWELL_HASWELL 8 OF 9 CONN@ 1 +VCCIO_OUT HPD INVERSION FOR EDP 10K_0402_5%~D RC65 B 2 B 1 S 2 G 2 RC75 100K_0402_5%~D 1 <31> CPU_EDP_HPD# QC10 BSS138_SOT23~D 3 EDP_HPD D A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. CPU (4/7) FDI,eDP,DDI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 9 of 61 5 4 3 2 1 CFG STRAPS for CPU CFG2 1 @ RC76 1K_0402_1%~D D 2 D PEG Static Lane Reversal - CFG2 is for the 16x 1:(Default) Normal Operation; Lane # definition matches socket pin map definition CFG2 0:Lane Reversed Haswell rPGA EDS JCPU1I CFG4 @ T110PAD~D @ T81 PAD~D A34 A35 RSVD_TP RSVD_TP @ T79 PAD~D @ T101PAD~D W29 W28 H_CPU_RSVD G26 W33 AL30 AL29 F25 @ T85 PAD~D AL25 H_CPU_TESTLO AT20 AR20 AP20 AP22 AT22 AN22 AT25 AN23 AR24 AT23 AN20 AP24 AP26 AN25 AN26 AP25 RSVD RSVD RSVD RSVD RSVD RSVD RSVD AR33 G6 AM27 AM26 F5 AM2 K6 PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D RSVD E18 PAD~D T96 @ U10 P10 PAD~D T98 @ PAD~D T97 @ B1 A2 AR1 PAD~D T100 @ PAD~D T109 @ E21 E20 PAD~D T102 @ PAD~D T107 @ RSVD_TP RSVD_TP RSVD_TP RSVD RSVD TESTLO CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 RSVD RSVD NC RSVD RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD CFG16 CFG18 CFG17 CFG19 C <6> <6> <6> <6> T91 @ T104@ T92 @ T89 @ T93 @ T95 @ T111@ Display Port Presence Strap CFG6 CFG5 AP27 AR26 PAD~D T105 @ PAD~D T106 @ AL31 AL32 B 2 RC60 2 RC58 2 RC59 1 H_CPU_TESTLO 49.9_0402_1%~D 1 CFG_RCOMP 49.9_0402_1%~D 1 H_CPU_RSVD 49.9_0402_1%~D INTEL_HASWELL_HASWELL 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port CFG4 @ RC92 1K_0402_1%~D CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 AT31 AR21 AR23 AP21 AP23 @ RC90 1K_0402_1%~D CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 W30 W31 W34 CFG_RCOMP CFG16 CFG18 CFG17 CFG19 CFG_RCOMP CFG_16 CFG_18 CFG_17 CFG_19 1 C35 B35 RSVD RSVD RSVD RSVD RSVD RSVD VCC 2 @ T82 PAD~D @ T94 PAD~D @ T84 PAD~D @ T86 PAD~D <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> T99 @ T90 @ T87 @ T88 @ 1 +VCC_CORE PAD~D PAD~D PAD~D PAD~D C23 B23 D24 D23 2 @ T83 PAD~D @ T108PAD~D RSVD_TP RSVD_TP RSVD_TP RSVD_TP 1 RSVD_TP RSVD_TP RSVD 2 AT1 AT2 AD10 RC77 1K_0402_1%~D C @ T103PAD~D @ T80 PAD~D @ T78 PAD~D 9 OF 9 CONN@ CFG[6:5] PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B 2 @ RC91 1K_0402_1%~D 1 CFG7 PEG DEFER TRAINING 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training CFG7 A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title A Compal Electronics, Inc. CPU (5/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 10 of 61 5 3 2 1 +1.35V_CPU_VDDQ Source 4 1 2 4 RUN_ON_CPU1.5VS3# 1 2 1 1 3 2 1 2 6 1 2 @ T113 @ T114 @ T112 @ T116 @ RC73 20K_0402_5%~D 1 CC136 0.022U_0402_25V7K~D 5 RC143 1M_0402_5%~D 2 1 2 3 RUN_ON_CPU1.5VS3 QC4B DMN66D0LDW-7_SOT363-6~D 1 RC79 QC4A DMN66D0LDW-7_SOT363-6~D 2 0_0402_5%~D 2 0_0402_5%~D 8 7 6 5 +1.35V_CPU_VDDQ CC135 10U_0603_6.3V6M~D RC72 330K_0402_5%~D RC74 100K_0402_5%~D <43> CPU1.5V_S3_GATE 1 @ RC93 D JCPU1E QC3 AO4304L_SO8 B+_BIAS RUN_ON_CPU1.5VS3# <43,56,59,61> SUSP# +VCC_CORE Haswell rPGA EDS +1.35V +3VALW 2 D 4 PAD~D PAD~D PAD~D PAD~D K27 L27 T27 V27 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD RSVD +1.35V_CPU_VDDQ +1.35V CC151 2 1 0.1U_0402_10V7K~D CC152 2 1 0.1U_0402_10V7K~D AB11 AB2 AB5 AB8 AE11 AE2 AE5 AE8 AH11 K11 N11 N8 T11 T2 T5 T8 W11 W2 W5 W8 <6,56> @ T115 PAD~D N26 K26 AL27 AK27 +VCC_CORE @ T151 @ T152 PAD~D PAD~D VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RSVD VCC RSVD RSVD C +1.05VS VCCSENSE_R 2 @ T153 1 @ RC4 CAD Note: Place the PU resistors close to CPU RC60 close to CPU 300 - 1500mils 2 <62> VIDALERT_N 1 0_0603_5%~D PAD~D +VCCIO_OUT @ T156 PAD~D +VCOMP_OUT RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES @ T160 @ T159 @ T168 @ T154 +1.05VS H_CPU_SVIDALRT# RC69 PAD~D PAD~D PAD~D PAD~D 2 @ T157 @ T158 @ T162 @ T163 1 CPU_PWR_DEBUG 1 VIDSOUT PAD~D PAD~D PAD~D PAD~D 2 @ <62> VIDSOUT AP35 H27 AP34 AT35 AR35 AR32 AL26 AT34 AL22 AT33 AM21 AM25 AM22 AM20 AM24 AL19 AM23 AT32 <6> CPU_PWR_DEBUG RC71 10K_0402_5%~D 2 CAD Note: Place the PU resistors close to CPU RC63 close to CPU 300 - 1500mils +VCC_CORE +1.35V_CPU_VDDQ VIDALERT VIDSCLK VIDSOUT VSS PWR_DEBUG RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 2 2 2 1 2 1 + 2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC INTEL_HASWELL_HASWELL C B U25 U26 V25 V26 W26 W27 5 OF 9 CONN@ 1 2 1 2 1 C_0805NEW 2 C_0805NEW 1 C_0805NEW 2 C_0805NEW 1 C_0805NEW 2 2 CC191 22U_0805_6.3V6M~D 1 CC190 22U_0805_6.3V6M~D 2 CC189 22U_0805_6.3V6M~D 1 CC188 22U_0805_6.3V6M~D 2 CC187 22U_0805_6.3V6M~D 1 CC186 22U_0805_6.3V6M~D 2 CC185 22U_0805_6.3V6M~D 1 CC184 22U_0805_6.3V6M~D 2 CC183 22U_0805_6.3V6M~D 1 CC182 22U_0805_6.3V6M~D 2 CC181 22U_0805_6.3V6M~D 1 C_0805NEW 1 RC70 100_0402_1%~D 2 2 1 CC167 330U_D2_2VM_R6M~D 2 1 CC166 10U_0603_6.3V6M~D 2 1 CC165 10U_0603_6.3V6M~D 2 1 CC164 10U_0603_6.3V6M~D 2 1 CC163 10U_0603_6.3V6M~D 2 1 CC162 10U_0603_6.3V6M~D <11> 1 CC161 10U_0603_6.3V6M~D VSSSENSE_R 1 CC168 10U_0603_6.3V6M~D VSSSENSE_R RC68 CC169 10U_0603_6.3V6M~D <62> VSSSENSE 1 CC170 10U_0603_6.3V6M~D 1 2 0_0402_5%~D CC180 10U_0603_6.3V6M~D CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU VSSSENSE Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 VDDQ DECOUPLING VCCSENSE_R 1 RC67 C_0805NEW 2 0_0402_5%~D C_0805NEW VCCSENSE C_0805NEW <62> VCCSENSE VCC_SENSE RSVD VCCIO_OUT VCCIO2PCH VCCIOA_OUT RSVD RSVD VSS RSVD +VCC_CORE CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU C_0805NEW 1 2 B RC66 100_0402_1%~D VCC_SENSE AL35 E17 AN35 A23 F22 W32 AL16 J27 AL13 H_CPU_SVIDALRT# AM28 VIDSCLK AM29 VIDSOUT AL28 <62> VIDSCLK @ +VCCIO_OUT RC80 10K_0402_5%~D 1 43_0402_5%~D RC63 110_0402_1%~D SVID DATA 2 RC61 75_0402_1%~D 1 SVID ALERT +VCCIO_OUT +VCCIO_OUT AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. CPU (6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 11 of 61 5 4 Haswell rPGA EDS D A10 A13 A16 A19 A22 A25 A27 A29 A3 A31 A33 A4 A7 AA11 AA25 AA27 AA31 AA29 AB1 AB10 AA33 AA35 AB3 AC25 AC27 AB4 AB6 AB7 AB9 AC11 AD11 AC29 AC31 AC33 AC35 AD7 AE1 AE10 AE25 AE29 AE3 AE27 AE35 AE4 AE6 AE7 AE9 AF11 AF6 AF8 AG11 AG25 AE31 AG31 AE33 AG6 AH1 AH10 AH2 AG27 AG29 AH3 AG33 AG35 AH4 AH5 AH6 AH7 AH8 AH9 AJ11 AJ5 AK11 AK25 AK26 AK28 AK29 AK30 AK32 E19 C B 3 Haswell rPGA EDS JCPU1F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS INTEL_HASWELL_HASWELL 2 AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22 B34 B4 B7 C1 C10 C13 C16 C19 C2 C22 C24 C26 C28 C30 C32 C34 C4 C7 D10 D13 D16 D19 D22 D25 D27 D29 D31 D33 D35 D4 D7 E1 E10 E13 E16 E4 E7 F10 F11 F12 F14 F15 F17 F18 F20 F21 F23 F24 F26 F28 F30 F32 F34 F4 F6 F7 F8 F9 G1 G11 G2 G27 G29 G3 G31 G33 G35 G4 G5 H10 H26 H6 H7 J11 J26 J28 J30 J32 J34 J6 K1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS 6 OF 9 D JCPU1G VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD RSVD RSVD RSVD VSS_SENSE RSVD INTEL_HASWELL_HASWELL CONN@ 1 K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33 C B VSSSENSE_R <10> PAD~D T120 @ 7 OF 9 CONN@ A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. CPU (7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 12 of 61 5 4 3 2 1 @ 2 JDIMMA H=4mm D DDR3_DRAMRST#_R 1 RD29 <13,14,15> DDR3_DRAMRST#_R +DIMM0_1_VREF_CPU +1.35V +1.35V RD27 1K_0402_5%~D 1 +1.35V CRB Rev 0.7 is depop D 2 1K_0402_5%~D DDR3_DRAMRST#_CPU <6> JDIMM1 2 1 2 CD2 0.1U_0402_25V6K~D 1 CD1 2.2U_0402_6.3V6M All VREF traces should have 20 mil trace width <7,14> DDR_A_DQS#[0..7] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 <7,14> DDR_A_D[0..63] <7,14> DDR_A_DQS[0..7] DDR_A_D10 DDR_A_D11 <7,14> DDR_A_MA[0..15] DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 Layout Note: Place near JDIMMA DDR_A_D24 DDR_A_D25 +1.35V DDR_A_D26 DDR_A_D27 C 2 1 2 1 2 CD6 1U_0402_6.3V6K~D 1 CD5 1U_0402_6.3V6K~D CD4 1U_0402_6.3V6K~D 2 CD3 1U_0402_6.3V6K~D 1 <7> DDR_CKE4_DIMMC <7,14> DDR_A_BS2 DDR_CKE4_DIMMC DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 +1.35V <7> M_CLK_DDR4 <7> M_CLK_DDR#4 2 + 2 CD14 330U_SX_2VY~D 2 1 @ CD13 10U_0603_6.3V6M~D 2 1 CD74 10U_0603_6.3V6M~D 2 1 CD11 10U_0603_6.3V6M~D 2 1 CD10 10U_0603_6.3V6M~D 2 1 CD9 10U_0603_6.3V6M~D 1 CD8 10U_0603_6.3V6M~D 2 CD7 10U_0603_6.3V6M~D 1 1 <7,14> DDR_A_BS0 <7,14> DDR_A_WE# <7,14> DDR_A_CAS# <7> DDR_CS5_DIMMC# M_CLK_DDR4 M_CLK_DDR#4 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS5_DIMMC# DDR_A_D34 DDR_A_D35 B DDR_A_D40 DDR_A_D41 Layout Note: Place near JDIMMA.203,204 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +0.675VS +3VS 2 2 DDR_A_D56 DDR_A_D57 @ RD39 10K_0402_5%~D DDR_A_D58 DDR_A_D59 1 2 RD38 10K_0402_5%~D 1 2 1 CD20 1U_0402_6.3V6K~D 2 1 CD19 1U_0402_6.3V6K~D 1 CD18 1U_0402_6.3V6K~D 2 CD17 1U_0402_6.3V6K~D 1 DDR_A_D50 DDR_A_D51 SA0 SA1 1 0 DIMM1A 1 1 DIMMB 0 0 DIMMC 0 1 DIMMD 2 1 1 RD22 10K_0402_5%~D 1 2 1 2 CD22 2.2U_0402_6.3V6M RD21 @ 10K_0402_5%~D CD21 0.1U_0402_25V6K~D 2 +3VS +0.675VS 205 207 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT GND1 BOSS1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST#_R DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE5_DIMMC C DDR_CKE5_DIMMC <7> DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR5 M_CLK_DDR#5 DDR_A_BS1 DDR_A_RAS# DDR_CS4_DIMMC# M_ODT4 M_CLK_DDR5 <7> M_CLK_DDR#5 <7> DDR_A_BS1 <7,14> DDR_A_RAS# <7,14> DDR_CS4_DIMMC# <7> M_ODT4 <7> M_ODT5 M_ODT5 <7> +V_SM_VREF_CNT DDR_A_D36 DDR_A_D37 1 DDR_A_D38 DDR_A_D39 2 DDR_A_D44 DDR_A_D45 1 2 CD16 0.1U_0402_25V6K~D DDR_A_DQS#4 DDR_A_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CD15 2.2U_0402_6.3V6M DDR_A_D32 DDR_A_D33 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 All VREF traces should have 20 mil trace width B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 2(H8) JDIMMA(H4) DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 CPU 3(H5.2) 4(H9.2) DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 M_THERMAL# M_THERMAL# <13,14,15,43> PCH_SMBDATA <6,13,14,15,19,49,50,51,53> PCH_SMBCLK <6,13,14,15,19,49,50,51,53> +0.675VS 206 208 TYCO_2-2013022-1 CONN@ A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DDRIII DIMMA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 13 of 61 5 4 3 2 1 JDIMMB H=4mm D D +DIMM0_1_CA_CPU +1.35V +1.35V JDIMM2 2 1 2 CD24 0.1U_0402_25V6K~D All VREF traces should have 20 mil trace width CD23 2.2U_0402_6.3V6M 1 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 <7,15> DDR_B_DQS#[0..7] DDR_B_DQS#1 DDR_B_DQS1 <7,15> DDR_B_D[0..63] DDR_B_D10 DDR_B_D11 <7,15> DDR_B_DQS[0..7] <7,15> DDR_B_MA[0..15] DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMMB DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 C +1.35V 2 1 2 <7> DDR_CKE6_DIMMD CD28 1U_0402_6.3V6K~D 2 1 CD27 1U_0402_6.3V6K~D 2 1 CD26 1U_0402_6.3V6K~D CD25 1U_0402_6.3V6K~D 1 <7,15> DDR_B_BS2 DDR_CKE6_DIMMD DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 +1.35V 2 <7,15> DDR_B_BS0 1 + 2 CD36 330U_SX_2VY~D 2 1 @ CD35 10U_0603_6.3V6M~D 2 1 CD34 10U_0603_6.3V6M~D 2 1 CD33 10U_0603_6.3V6M~D 2 1 CD32 10U_0603_6.3V6M~D 2 1 CD31 10U_0603_6.3V6M~D 1 CD30 10U_0603_6.3V6M~D 2 CD29 10U_0603_6.3V6M~D 1 <7> M_CLK_DDR6 <7> M_CLK_DDR#6 <7,15> DDR_B_WE# <7,15> DDR_B_CAS# <7> DDR_CS7_DIMMD# M_CLK_DDR6 M_CLK_DDR#6 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS7_DIMMD# DDR_B_D34 DDR_B_D35 B Layout Note: Place near JDIMMB.203,204 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 +0.675VS DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D56 DDR_B_D57 RD24 10K_0402_5%~D DDR_B_D58 DDR_B_D59 1 RD40 10K_0402_5%~D DDR_B_D50 DDR_B_D51 2 2 2 +3VS 1 2 1 CD42 1U_0402_6.3V6K~D 2 1 CD41 1U_0402_6.3V6K~D 1 CD40 1U_0402_6.3V6K~D 2 CD39 1U_0402_6.3V6K~D 1 DIMMA 1 1 DIMMB 0 0 DIMMC 0 1 DIMMD 2 1 0 1 1 @ RD41 10K_0402_5%~D 1 2 1 2 CD43 2.2U_0402_6.3V6M RD23 @ 10K_0402_5%~D SA0 SA1 CD44 0.1U_0402_25V6K~D 2 +3VS +0.675VS 205 207 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT GND1 BOSS1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR3_DRAMRST#_R DDR3_DRAMRST#_R <12,14,15> DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 C DDR_CKE7_DIMMD DDR_CKE7_DIMMD <7> DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR7 M_CLK_DDR#7 DDR_B_BS1 DDR_B_RAS# DDR_CS6_DIMMD# M_ODT6 M_ODT7 M_CLK_DDR7 <7> M_CLK_DDR#7 <7> DDR_B_BS1 <7,15> DDR_B_RAS# <7,15> DDR_CS6_DIMMD# <7> M_ODT6 <7> +V_SM_VREF_CNT M_ODT7 <7> DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 2 1 2 DDR_B_D44 DDR_B_D45 CD38 0.1U_0402_25V6K~D DDR_B_DQS#4 DDR_B_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CD37 2.2U_0402_6.3V6M DDR_B_D32 DDR_B_D33 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 All VREF traces should have 20 mil trace width B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 JDIMMB(H8) 1(H4) DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 CPU DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 3(H5.2) 4(H9.2) DDR_B_D62 DDR_B_D63 M_THERMAL# M_THERMAL# <12,14,15,43> PCH_SMBDATA <6,12,14,15,19,49,50,51,53> PCH_SMBCLK <6,12,14,15,19,49,50,51,53> +0.675VS 206 208 SUYIN_600025HB204G251ZL CONN@ A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DDRIII DIMMB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 14 of 61 5 4 3 2 1 JDIMMC H=5.2mm D D +DIMM0_1_VREF_CPU +1.35V +1.35V JDIMM3 2 1 2 CD53 0.1U_0402_25V6K~D All VREF traces should have 20 mil trace width CD50 2.2U_0402_6.3V6M 1 <7,12> DDR_A_DQS#[0..7] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 <7,12> DDR_A_D[0..63] <7,12> DDR_A_DQS[0..7] DDR_A_D10 DDR_A_D11 <7,12> DDR_A_MA[0..15] DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 Layout Note: Place near JDIMMC DDR_A_D24 DDR_A_D25 +1.35V DDR_A_D26 DDR_A_D27 C 2 1 2 1 2 CD47 1U_0402_6.3V6K~D 1 CD63 1U_0402_6.3V6K~D CD54 1U_0402_6.3V6K~D 2 CD12 1U_0402_6.3V6K~D 1 <7> DDR_CKE0_DIMMA <7,12> DDR_A_BS2 DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 +1.35V <7> M_CLK_DDR0 <7> M_CLK_DDR#0 2 1 + 2 CD45 330U_SX_2VY~D 2 1 @ CD61 10U_0603_6.3V6M~D 2 1 CD75 10U_0603_6.3V6M~D 2 1 CD49 10U_0603_6.3V6M~D 2 1 CD46 10U_0603_6.3V6M~D 2 1 CD62 10U_0603_6.3V6M~D 1 CD59 10U_0603_6.3V6M~D 2 CD56 10U_0603_6.3V6M~D 1 <7,12> DDR_A_BS0 <7,12> DDR_A_WE# <7,12> DDR_A_CAS# <7> DDR_CS1_DIMMA# M_CLK_DDR0 M_CLK_DDR#0 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_D34 DDR_A_D35 B DDR_A_D40 DDR_A_D41 Layout Note: Place near JDIMMC.203,204 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +0.675VS 2 DDR_A_D56 DDR_A_D57 @ RD43 10K_0402_5%~D DDR_A_D58 DDR_A_D59 1 2 DDR_A_D50 DDR_A_D51 RD25 @ 10K_0402_5%~D 1 2 1 CD55 1U_0402_6.3V6K~D 2 1 CD57 1U_0402_6.3V6K~D 1 CD51 1U_0402_6.3V6K~D 2 CD64 1U_0402_6.3V6K~D 1 2 +3VS A 1 0 DIMMA 1 1 DIMMB 0 0 DIMMC 0 1 DIMMD 2 1 1 SA0 SA1 RD26 10K_0402_5%~D 1 2 1 2 CD60 2.2U_0402_6.3V6M RD42 10K_0402_5%~D CD48 0.1U_0402_25V6K~D 2 +3VS +0.675VS 205 207 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND1 BOSS1 GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST#_R DDR3_DRAMRST#_R <12,13,15> DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA C DDR_CKE1_DIMMA <7> DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# <7> M_ODT0 <7> M_ODT1 M_ODT1 <7> <7> <7,12> <7,12> <7> +V_SM_VREF_CNT DDR_A_D36 DDR_A_D37 1 DDR_A_D38 DDR_A_D39 2 DDR_A_D44 DDR_A_D45 1 2 All VREF traces should have 20 mil trace width CD58 0.1U_0402_25V6K~D DDR_A_DQS#4 DDR_A_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CD52 2.2U_0402_6.3V6M DDR_A_D32 DDR_A_D33 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 2(H8) 1(H4) DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 CPU DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 JDIMMC(H5.2) 4(H9.2) DDR_A_D62 DDR_A_D63 M_THERMAL# M_THERMAL# <12,13,15,43> PCH_SMBDATA <6,12,13,15,19,49,50,51,53> PCH_SMBCLK <6,12,13,15,19,49,50,51,53> +0.675VS 206 208 LCN_DAN06-K4526-0103 CONN@ A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DDRIII DIMMC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 15 of 61 5 4 3 2 1 JDIMMD H=9.2mm D D +DIMM0_1_CA_CPU +1.35V +1.35V JDIMM4 2 1 2 CD76 0.1U_0402_25V6K~D All VREF traces should have 20 mil trace width CD84 2.2U_0402_6.3V6M 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 <7,13> DDR_B_DQS#[0..7] DDR_B_DQS#1 DDR_B_DQS1 <7,13> DDR_B_D[0..63] DDR_B_D10 DDR_B_D11 <7,13> DDR_B_DQS[0..7] <7,13> DDR_B_MA[0..15] DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMMD DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 +1.35V C 2 1 2 CD71 1U_0402_6.3V6K~D 2 1 CD78 1U_0402_6.3V6K~D 2 1 CD80 1U_0402_6.3V6K~D CD82 1U_0402_6.3V6K~D 1 <7> DDR_CKE2_DIMMB <7,13> DDR_B_BS2 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 <7> M_CLK_DDR2 <7> M_CLK_DDR#2 2 1 + 2 <7,13> DDR_B_BS0 CD68 330U_SX_2VY~D 2 1 @ CD70 10U_0603_6.3V6M~D 2 1 CD88 10U_0603_6.3V6M~D 2 1 CD65 10U_0603_6.3V6M~D 2 1 CD79 10U_0603_6.3V6M~D 2 1 CD81 10U_0603_6.3V6M~D 1 CD87 10U_0603_6.3V6M~D CD67 10U_0603_6.3V6M~D 2 <7,13> DDR_B_WE# <7,13> DDR_B_CAS# <7> DDR_CS3_DIMMB# M_CLK_DDR2 M_CLK_DDR#2 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 Layout Note: Place near JDIMMD.203,204 B DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 +0.675VS DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D56 DDR_B_D57 2 2 RD31 @ 10K_0402_5%~D DDR_B_D50 DDR_B_D51 RD32 10K_0402_5%~D DDR_B_D58 DDR_B_D59 1 2 +3VS 1 2 1 CD85 1U_0402_6.3V6K~D 2 1 CD86 1U_0402_6.3V6K~D 1 CD77 1U_0402_6.3V6K~D 2 CD89 1U_0402_6.3V6K~D 1 A DIMMA 1 1 DIMMB 0 0 DIMMC 0 1 DIMMD RD44 10K_0402_5%~D 2 @ RD45 10K_0402_5%~D 1 0 1 1 1 2 1 2 CD66 2.2U_0402_6.3V6M SA0 SA1 CD69 0.1U_0402_25V6K~D 2 +3VS +0.675VS 205 G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR3_DRAMRST#_R DDR3_DRAMRST#_R <12,13,14> DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 C DDR_CKE3_DIMMB DDR_CKE3_DIMMB <7> DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3 M_CLK_DDR3 <7> M_CLK_DDR#3 <7> DDR_B_BS1 <7,13> DDR_B_RAS# <7,13> DDR_CS2_DIMMB# <7> M_ODT2 <7> +V_SM_VREF_CNT M_ODT3 <7> DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 2 1 2 DDR_B_D44 DDR_B_D45 CD83 0.1U_0402_25V6K~D DDR_B_D32 DDR_B_D33 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 CD72 2.2U_0402_6.3V6M 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 +1.35V 1 DDR_CKE2_DIMMB VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 All VREF traces should have 20 mil trace width B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 2(H8) 1(H4) DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 CPU DDR_B_DQS#7 DDR_B_DQS7 3(H5.2) JDIMMD(H9.2) DDR_B_D62 DDR_B_D63 M_THERMAL# M_THERMAL# <12,13,14,43> PCH_SMBDATA <6,12,13,14,19,49,50,51,53> PCH_SMBCLK <6,12,13,14,19,49,50,51,53> +0.675VS 206 FOX_AS0A626-UARN-7F CONN@ A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DDRIII DIMMD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 16 of 61 5 4 3 2 1 2 D RH38 330K_0402_1%~D 1 +RTC_CELL D 2 @ RH39 330K_0402_1%~D 1 PCH_INTVRMEN INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs +3VS +3V_PCH HDA_SPKR 10K_0402_5%~D 2 1 2 @ RH287 PCH_AZ_SDOUT 1K_0402_1%~D +3VS FLASH DESCRIPTOR SECURITY OVERRIDE NO REBOOT STRAP CH2 2 PCH_RTCX1_R RH286 18P_0402_50V8J~D +3VS 1 PCH_RTCX1 2 0_0402_5%~D YH1 32.768KHZ_12.5PF_Q13FC1350000~D C PCH_GPIO33 100K_0402_5%~D RH22 1 2 20K_0402_5%~D RH11 1 2 1M_0402_5%~D PCH_RTCX2 B4 SRTCRST# B9 INTRUDER# PCH_INTVRMEN RH23 1 CMOS_CLR1 PCH_RTCRST# 2 20K_0402_5%~D CMOS setting Shunt Clear CMOS Open 1 1 2 2 1 1 2 2 Keep CMOS 1 Shunt Clear ME RTC Registers Open Keep ME RTC Registers CH5 CMOS place near DIMM +3V_PCH 1 RH50 C24 L22 SRTCRST# SPKR BB9 BD9 SATA_ODD_PRX_DTX_N2 SATA_ODD_PRX_DTX_P2 AY13 AW13 SATA_ODD_PTX_DRX_N2 SATA_ODD_PTX_DRX_P2 SATA_RXN_3 SATA_RXP_3 BC12 BE12 MSATA_PRX_DTX_N3 MSATA_PRX_DTX_P3 SATA_TXN_3 SATA_TXP_3 AR13 AT13 MSATA_PTX_DRX_N3 MSATA_PTX_DRX_P3 SATA_RXN_2 SATA_RXP_2 HDA_RST# HDA_SDI0 HDA_SDI3 B17 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_TXN_2 SATA_TXP_2 HDA_SYNC HDA_SDI2 C22 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 AV10 AW10 HDA_BCLK HDA_SDI1 DP_PCH_HPD BC10 BE10 SATA_TXN_1 SATA_TXP_1 RTCRST# F22 A24 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_RXN_1 SATA_RXP_1 INTVRMEN G22 PCH_AZ_SDOUT 1K_0402_1%~D PCH_GPIO33 AW8 AY8 SATA_TXN_0 SATA_TXP_0 INTRUDER# K22 SATA_RXN4/PERN1 SATA_RXP4/PERP1 SATA_TXN4/PETN1 SATA_TXP4/PETP1 HDA_SDO SATA_RXN5/PERN2 SATA_RXP5/PERP2 DOCKEN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_TXP5/PETP2 PCH_JTAG_TCK AB3 2 210_0402_1%~D PCH_JTAG_TMS AD1 2 210_0402_1%~D PCH_JTAG_TDI AE2 2 210_0402_1%~D PCH_JTAG_TDO AD3 2 RH47 100_0402_1%~D RH49 100_0402_1%~D RH48 100_0402_1%~D 1 @ RH46 1 @ RH45 1 RH55 1 2 RH289 PCH_TP25 0_0402_5%~D F8 C26 @ T122 PAD~D AB6 PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 PCIE_PTX_WANRX_N2 PCIE_PTX_WANRX_P2 SATA0GP/GPIO21 AT1 PCH_GPIO21 SATA1GP/GPIO19 AU2 BBS_BIT0_R BD4 SATA_IREF 0_0402_5% TP8 mSATA PCIE_PRX_WLANTX_N1 <51> PCIE_PRX_WLANTX_P1 <51> MiniWLAN (Mini Card 1) PCIE_PTX_WLANRX_N1 <51> PCIE_PTX_WLANRX_P1 <51> PCIE_PRX_WANTX_N2 <51> PCIE_PRX_WANTX_P2 <51> MiniDMC (Mini Card 2) PCIE_PTX_WANRX_N2 <51> PCIE_PTX_WANRX_P2 <51> B JTAG_TMS TP25 ODD/HDD3 Bay SATA_ODD_PTX_DRX_N2 <50> SATA_ODD_PTX_DRX_P2 <50> MSATA_PTX_DRX_N3 <50> MSATA_PTX_DRX_P3 <50> BC14 BE14 JTAG_TCK TP9 SATA_ODD_PRX_DTX_N2 <50> SATA_ODD_PRX_DTX_P2 <50> MSATA_PRX_DTX_N3 <50> MSATA_PRX_DTX_P3 <50> AP15 AR15 PCH_SATALED# JTAG_TDO HDD2(Slave) SATA_PTX_DRX_N1 <49> SATA_PTX_DRX_P1 <49> PCIE_PTX_WLANRX_N1 PCIE_PTX_WLANRX_P1 SATA_COMP SATA_IREF SATA_PRX_DTX_N1 <49> SATA_PRX_DTX_P1 <49> PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 AY5 JTAG_TDI HDD1(Master) SATA_PTX_DRX_N0 <49> SATA_PTX_DRX_P0 <49> BD13 BB13 AP3 PCH_SATALED# <48> 2 1 RH41 +1.5VS BA2 PAD~D T161 @ PAD~D T155 @ BB2 TP22 TP20 SATA Impedance Compensation LYNXPOINT_BGA695 +1.5VS 1 OF 11 RTC Battery SATA_COMP 1 7.5K_0402_1%~D +RTCBATT RH52 2 SATA_PRX_DTX_N0 <49> SATA_PRX_DTX_P0 <49> AV15 AW15 SATALED# JTAG 1 51_0402_1%~D RH44 1 @ RH59 2 1 +3.3V_ALW_PCH_JTAG 1 QH8 SSM3K7002FU_SC70-3~D AL10 RTCX2 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RCOMP 2 PCH_AZ_SYNC 2 D 2 1 S RH31 1M_0402_5%~D 1 3 2 2 G PCH_AZ_SYNC_Q 2 <30> DP_PCH_HPD RH288 0_0603_5%~D 1 +5VS B A22 PCH_AZ_CODEC_SDIN0 <45> PCH_AZ_CODEC_SDIN0 <43> HDA_SDO HDA_SYNC Isolation Circuit B25 PCH_AZ_SYNC PCH_AZ_RST# @ CMOS1 SHORT PADS~D 1 2 1U_0402_6.3V6K~D CH4 SHORT PADS~D 2 1U_0402_6.3V6K~D D9 PCH_AZ_BITCLK HDA_SPKR <45> HDA_SPKR @ ME1 TPM setting A8 G10 RTCX1 AZALIA ME_CLR1 1 C BC8 BE8 SATA_RXN_0 SATA_RXP_0 RTC CH3 2 18P_0402_50V8J~D 1 +RTC_CELL 5 SATA B5 2 2 RH30 LPT_PCH_M_EDS UH1A RH2 10M_0402_5%~D 2 1 2 1 1 RH355 PCH_GPIO21 1 10K_0402_5%~D BBS_BIT0_R 2 4.7K_0402_5%~D PCH_SATALED# 1 10K_0402_5%~D LOW = DESABLED (DEFAULT) HIGH = ENABLED DISABLED WHEN LOW (DEFAULT) ENABLED WHEN HIGH 1 1 @ RH35 2 RH40 CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. 2 HDA for Codec RH34 1K_0402_5% +3VLP <45> PCH_AZ_CODEC_SDOUT 1 W=20mils RH27 1 <45> PCH_AZ_CODEC_BITCLK 1 +RTC_CELL 2 CH12 1U_0603_10V6K @ CH101 27P_0402_50V8J~D RH26 1 W=20mils 1 2 1 <45> PCH_AZ_CODEC_RST# DH1 BAT54CW_SOT323-3 2 1 RH56 2 3 W=20mils A PCH_AZ_SDOUT 33_0402_5%~D PCH_AZ_SYNC_Q 33_0402_5%~D 2 PCH_AZ_RST# 33_0402_5%~D 2 PCH_AZ_BITCLK 33_0402_5%~D 1 RH29 <45> PCH_AZ_CODEC_SYNC A Compal Secret Data Security Classification 2 Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (1/9) RTC,HDA,SATA,XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 17 of 61 5 4 3 RH357 1 2 1 2 0_0402_5%~D +3VS B A 3 RH172 PCH_RI# 2 10K_0402_5%~D 2 1 2 RH153 1 1 @ UH13 74AHC1G09GW_TSSOP5~D U44 V45 M43 PM_CLKRUN# 8.2K_0402_5%~D ME_RESET# 2 8.2K_0402_5%~D 1 ME_SUS_PWR_ACK_R RH323 2 1 @ RH152 1 N42 SUSACK#_R 0_0402_5%~D 2 N44 1 RH139 2 649_0402_1%~D U40 U39 <5> DMI_CTX_PRX_N0 <5> DMI_CTX_PRX_N1 <5> DMI_CTX_PRX_N2 <5> DMI_CTX_PRX_N3 <5> DMI_CTX_PRX_P0 <5> DMI_CTX_PRX_P1 C <5> DMI_CTX_PRX_P2 <5> DMI_CTX_PRX_P3 <5> DMI_CRX_PTX_N0 <5> DMI_CRX_PTX_N1 <5> DMI_CRX_PTX_N2 <5> DMI_CRX_PTX_N3 <5> DMI_CRX_PTX_P0 <5> DMI_CRX_PTX_P1 <5> DMI_CRX_PTX_P2 <5> DMI_CRX_PTX_P3 2 +1.5VS 1 RH43 K36 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 AW22 AR20 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 AP17 AV20 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 AY22 AP20 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 AR17 AW20 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 BD21 BE20 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 BD17 BE18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 BB21 BC20 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 BB17 BC18 DMI_IREF 0_0402_5% BE16 AW17 @ T139 PAD~D AV17 +1.5VS @ T123 PAD~D DMI_RCOMP 2 7.5K_0402_1%~D 1 RH204 <40> PCH_EDP_PWM 5 AY17 DMI_RXN_0 DMI_RXN_1 G36 FDI_RXN_0 DMI_RXN_2 DMI_RXN_3 FDI_RXN_1 DMI_RXP_0 DMI_RXP_1 FDI_RXP_0 FDI FDI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI TP16 DMI_TXN_0 DMI_TXN_1 TP5 TP15 DMI_TXN_2 DMI_TXN_3 TP10 DMI_TXP_0 DMI_TXP_1 FDI_CSYNC DMI_TXP_2 DMI_TXP_3 AL35 PCI_PIRQA# H20 AJ36 PCI_PIRQB# L20 AL36 AV43 PAD~D AY45 PAD~D T141 @ AV45 PAD~D T147 @ AW44 PAD~D T148 @ FDI_INT AL40 FDI_INT AT45 FDI_IREF 0_0402_5% TP17 TP12 TP13 FDI_RCOMP T144 @ FDI_CSYNC AL39 FDI_IREF DMI_IREF TP7 AJ35 AU42 2 PCI_PIRQC# K17 PCI_PIRQD# M20 A12 <32,36,42> DGPU_SELECT# DGPU_SELECT# B13 C12 FDI_CSYNC <5> FDI_INT <5> 1 PAD~D RH42 T145 @ PAD~D T146 @ BBS_BIT1 <42> HDMI_IN_PWMSEL# +1.5VS <51> WL_OFF# C10 HDMI_IN_PWMSEL# A10 WL_OFF# AL6 DDPB_CTRLCLK VGA_GREEN DDPB_CTRLDATA VGA_RED DDPC_CTRLCLK VGA_DDC_CLK DDPC_CTRLDATA VGA_DDC_DATA DDPD_CTRLCLK VGA_HSYNC DDPD_CTRLDATA VGA_VSYNC DDPB_AUXN DAC_IREF DDPC_AUXN VGA_IRTN EDP_BKLTCTL DDPB_AUXP EDP_BKLTEN DDPC_AUXP EDP_VDDEN DDPD_AUXP DDPB_HPD PIRQA# DDPC_HPD PIRQB# DDPD_HPD FDI_RCOMP 2 7.5K_0402_1%~D AR44 1 RH206 R40 PCH_DPB_HDMI_CLK PCH_DPB_HDMI_CLK R39 PCH_DPB_HDMI_DAT R36 N40 PCH_DPD_CLK PCH_DPD_CLK <39> N38 PCH_DPD_DAT PCH_DPD_DAT <39> PCI PIRQE#/GPIO2 GPIO50 PIRQF#/GPIO3 GPIO52 PIRQG#/GPIO4 GPIO54 PIRQH#/GPIO5 GPIO51 PME# GPIO53 K43 J42 H43 K45 J44 K40 PCH_HDMI_HPD PCH_HDMI_HPD PLTRST# H39 PCH_DMC_HPD PCH_DMC_HPD G17 BT_ON# BT_ON# F17 DP_CBL_DET L15 ODD_DA# <30> ODD_DA# <50> FFS_INT1 @ T124 AD10 <49> PAD~D Y11 PCH_PLTRST# 5 OF 11 +3VS +3VS CH144 1 2 DMI_RCOMP <43> PCH_RSMRST# B RH367 10K_0402_5%~D @ <6,43> PBTN_OUT# 2 RH163 +PCH_VCCDSW3_3 1 2 RH156 @ T140 PCH_BATLOW# 8.2K_0402_5%~D PCH_RI# K7 N4 PAD~D AB10 D2 SUS_STAT#/GPIO61 DRAMPWROK RSMRST# PM_CLKRUN# U7 SUS_STAT# SUSCLK/GPIO62 Y6 SLP_S5#/GPIO63 Y7 PM_SLP_S5# SLP_S4# C6 PM_SLP_S4# H1 PM_SLP_S3# SUSWARN#/SUSPWRNACK/GPIO30 PWRBTN# SLP_S3# ACPRESENT/GPIO31 SLP_A# BATLOW#/GPIO72 SLP_SUS# RI# PMSYNCH TP21 SLP_LAN# 5 PCH_PLTRST# T129 PAD~D@ T126 PAD~D@ PM_SLP_S5# <43,47> T125 PAD~D @ PM_SLP_S4# <43> CH147 1 2 F1 PM_SLP_SUS# AY3 H_PM_SYNC T128 PAD~D @ PM_SLP_SUS# <43> T127 PAD~D @ H_PM_SYNC <6> <43> DGPU_HOLD_RST# DGPU_HOLD_RST# 1 PCH_PLTRST# 2 G5 B 2 1 Boot BIOS Strap SYS_PWROK 1 4 PLTRST_VGA# UH6 TC7SH08FU_SSOP5~D +3V_PCH R1900 10K_0402_5% * 2 1 A Boot BIOS Location LPC 0 0 0 1 1 0 PCI 1 1 SPI Reserved (NAND) 2 A16 SWAP OVERRIDE STRAP 2 1 RH366 2 1 2 1 2 1 2 1 2 1 2 1 2 1 RH365 RH362 RH352 RH324 RH325 RH326 RH329 2 1 @ RH327 LOW = A16 SWAP OVERRIDE HIGH = DEFAULT STP_A16OVR RH351 2 @ PM_CLKRUN# 10K_0402_5%~D DSWODVREN - ON DIE DSW VR ENABLE ACIN_PCH A HIGH = ENABLED (DEFAULT) LOW = DISABLED 3 R1899 10K_0402_5% <6,43,44,51,53> +3VS BT_ON# 8.2K_0402_5%~D ODD_DA# 8.2K_0402_5%~D WL_OFF# 8.2K_0402_5%~D HDMI_IN_PWMSEL# 8.2K_0402_5%~D PCI_PIRQA# 8.2K_0402_5%~D PCI_PIRQB# 8.2K_0402_5%~D PCI_PIRQC# 8.2K_0402_5%~D PCI_PIRQD# 8.2K_0402_5%~D DGPU_HOLD_RST# 10K_0402_5%~D PLTRST_VGA# <29> 1 1 2 +3V_PCH SATA1GP/GPIO19 (BBS_BIT0) 2 BBS_BIT1 MC74VHC1G08DFT2G_SC70-5 PLT_RST# DSWODVREN GNT1#/GPIO51 (BBS_BIT1) 1 4 @ RH342 1K_0402_1%~D 3 GND VCC 5 UH8 OUT PLT_RST RH215 100K_0402_5%~D @ 0.1U_0402_25V6K~D O A +RTC_CELL 4 OF 11 @ RH178 330K_0402_1%~D IN2 4 RH196 100K_0402_5%~D RH191 330K_0402_1%~D IN1 O UH3 TC7SH08FU_SSOP5~D B +3VS PM_SLP_S3# <43,47> F3 CH41 0.1U_0402_16V7K 2 <6,43,62> IMVP_PWRGD A RH201 100K_0402_5%~D 1 1 B +3V_MXM SLP_WLAN#/GPIO29 LYNXPOINT_BGA695 PCH_PWROK 1 2 <43,44,51> +3VS 2 2 AN7 @ PCIE_WAKE# 1 2 1 RH200 APWROK PCIE_WAKE# 2 1 RH185 <43> SUSPWRDNACK CLKRUN# PCH_DRWROK_R P 2 PWROK L13 K3 G 2 1 RH320 WAKE# PCH_RSMRST#_R 0_0402_5%~D 2 2 PCH_DPWROK <43> 0_0402_5%~D 3 2 1 RH149 <6> PM_DRAM_PWRGD DPWROK SYS_PWROK RH167 1 1 RH186 2 1 RH144 System Power Management SYS_RESET# DSWODVREN C8 1 2 DSWVRMEN 1 1 AM1 SYS_PWROK_R AD7 0_0402_5%~D PCH_PWROK_R F10 0_0402_5%~D PM_APWROK_R AB7 0_0402_5%~D PM_DRAM_PWRGD_R H3 0_0402_5%~D PCH_RSMRST#_R J2 0_0402_5%~D ME_SUS_PWR_ACK_R J4 0_0402_5%~D SIO_PWRBTN#_R K1 0_0402_5%~D ACIN_PCH E6 SUSACK# 5 2 R6 <39> <51> DP_CBL_DET M15 FFS_INT1 +1.5VS P 1 RH193 SUSACK#_R 0_0402_5%~D SYS_RESET# <36> K38 GPIO55 G <43> PCH_PWROK 2 DMC H45 C PIRQD# 3 <6> SYS_PWROK 1 @ RH114 HDMI <36> R35 0.1U_0402_25V6K~D <42,43> SG_AMD_BKL <36> PCH_DPB_HDMI_DAT PIRQC# LYNXPOINT_BGA695 AU44 DDPD_AUXN LVDS LPT_PCH_M_EDS UH1B PCH_EDP_PWM N36 5 VGA_BLUE CRT M45 +3VS RH138 LPT_PCH_M_EV UH1E T45 DISPLAY RH148 SUS_STAT# 10K_0402_5%~D SUSPWRDNACK 10K_0402_5%~D PCIE_WAKE# 2 10K_0402_5%~D 1 @ RH318 D SYS_RESET# 4 O 1 ME_RESET# 2 8.2K_0402_5%~D 1 2 @ RH199 +3V_PCH P 1 <6> XDP_DBRESET# D G 5 @ CH143 1 2 0.1U_0402_25V6K~D 2 GPIO51 has internal pull up. DMN66D0LDW-7_SOT363-6~D QH13B 4 6 5 Compal Secret Data Security Classification DMN66D0LDW-7_SOT363-6~D QH13A 2 Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (2/9) DMI,FDI,PM,DP,CRT 1 <29,43,47,57,63> ACIN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 18 of 61 5 4 3 2 1 D D LPT_PCH_M_EDS UH1C <51> CLK_PCIE_MINI1# MiniWLAN (Mini Card 1) DMC (Mini Card 2) <51> CLK_PCIE_MINI1 +3V_PCH <51> MINI1CLK_REQ# <51> CLK_PCIE_MINI2# <51> CLK_PCIE_MINI2 +3VS <51> MINI2CLK_REQ# <44> CLK_PCIE_LAN# 10/100/1G LAN C Card Reader <44> CLK_PCIE_LAN +3VS <44> LANCLK_REQ# <53> CLK_PCIE_CD# <53> CLK_PCIE_CD <53> CDCLK_REQ# +3V_PCH +3V_PCH +3V_PCH +3V_PCH RH307 2 1 0_0402_5%~D PCIE_MINI1# Y43 RH308 RH142 2 2 1 0_0402_5%~D 1 10K_0402_5%~D PCIE_MINI1 Y45 2 2 2 1 0_0402_5%~D 1 0_0402_5%~D 110K_0402_5%~D PCIE_MINI2# PCIE_MINI2 RH99 RH98 RH145 RH158 1 0_0402_5%~D 2 MINI1CLK_REQ# MINI2CLK_REQ# PCIE_LAN# 2 1 1 0_0402_5%~D 2 10K_0402_5%~D PCIE_LAN RH28 RH129 RH124 2 2 1 0_0402_5%~D 1 0_0402_5%~D PCIE_EXP# PCIE_EXP CDCLK_REQ# RH147 RH126 RH128 RH132 RH133 2 2 2 2 LANCLK_REQ# AB1 AA44 AA42 AF1 AB43 AB45 AF3 AD43 AD45 T3 1 10K_0402_5%~D 1 10K_0402_5%~D AF43 AF45 V3 1 10K_0402_5%~D AE44 AE42 AA2 AB40 AB39 AE4 1 10K_0402_5%~D AJ44 AJ42 +3V_PCH Y3 1 0_0402_5%~D CLK_BCLK_ITP# 2 1 0_0402_5%~D CLK_BCLK_ITP CLK_PCI_LPBACK RH169 2 1 22_0402_5%~D CLK_PCI0 D44 CLK_PCI_LPC RH111 2 1 22_0402_5%~D CLK_PCI1 E44 CLK_DEBUG 2 1 22_0402_5%~D CLK_PCI2 AH45 B42 @ T142 PAD~D CLK_PCI3 F41 @ T138 PAD~D CLK_PCI4 A40 PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 CLKOUT_PCIE_N_1 CLKOUT_PCIE_P_1 CLKOUT_PEG_B CLKOUT_PEG_B_P PCIECLKRQ1#/GPIO18 PEGB_CLKRQ#/GPIO56 CLKOUT_PCIE_N_2 CLKOUT_DMI CLKOUT_PCIE_P_2 CLKOUT_DMI_P PCIECLKRQ2#/GPIO20/SMI# CLKOUT_DP CLKOUT_DP_P CLKOUT_PCIE_N_3 CLKOUT_PCIE_P_3 PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLKOUT_DPNS_P CLKOUT_PCIE_N_4 CLKOUT_PCIE_P_4 PCIECLKRQ4#/GPIO26 CLKOUT_PCIE_N5 CLKOUT_PCIE_P_5 PCIECLKRQ5#/GPIO44 Y39 U4 2 10K_0402_5%~D AF39 CLK_CPU_DMI# RH125 AF40 CLK_CPU_DMI AJ40 AJ39 CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL AF35 AF36 CLK_CPU_DPLL# CLK_CPU_DPLL CLK_CPU_DMI CLK_BUF_CKSSCD# CLK_BUF_CKSSCD F45 D17 CLK_PCH_14M CLK_PCI_LPBACK PCH_GPIO66 CLKOUTFLEX3/GPIO67 F39 CAM_DET# AM45 ICLK_IREF ICLK_IREF CLKOUT_33MHZ3 TP19 TP18 CLKOUT_33MHZ4 DIFFCLK_BIASREF CLK_BUF_BCLK# CLK_BUF_BCLK RH105 1 RH157 1 2 10K_0402_5%~D 2 10K_0402_5%~D CLK_BUF_DOT96# CLK_BUF_DOT96 RH143 1 RH130 1 2 10K_0402_5%~D 2 10K_0402_5%~D CLK_BUF_CKSSCD# CLK_BUF_CKSSCD RH146 1 RH155 1 2 10K_0402_5%~D 2 10K_0402_5%~D CLK_PCH_14M RH205 1 2 10K_0402_5%~D 2 1 RH309 RH131 F36 CLKOUT_33MHZ2 2 10K_0402_5%~D 2 10K_0402_5%~D XTAL25_IN XTAL25_OUT F38 CLKOUT_33MHZ1 RH74 1 RH75 1 1 2 0_0402_5%~D 1M_0402_5%~D C40 CLKOUTFLEX2/GPIO66 CLKOUTFLEX1/GPIO65 CLKOUT_33MHZ0 CLK_BUF_DMI# CLK_BUF_DMI T176 @ DMC_PCH_DET# <51> CAM_DET# 1 RH54 AD39 AD38 C CLOCK TERMINATION for FCIM and need close to PCH PAD~D DMC_PCH_DET# CLKOUT_ITPXDP_P <6> CLK_CPU_SSC_DPLL# <6> CLK_CPU_SSC_DPLL <6> CLK_CPU_DPLL# <6> CLK_CPU_DPLL <6> BE6 BC6 AL44 AM43 +3V_PCH CLK_CPU_DMI# <6> CLK_BUF_DOT96# CLK_BUF_DOT96 XTAL25_IN XTAL25_OUT 2 +3V_PCH 10K_0402_5%~D 1 CLK_BUF_BCLK# CLK_BUF_BCLK CLKOUTFLEX0/GPIO64 PEG_CLKREQ# <29> 1 RH76 H33 G33 CLKOUT_ITPXDP <29> <29> Y38 CLK_BUF_DMI# CLK_BUF_DMI REFCLK14IN CLKIN_33MHZLOOPBACK CLK_PEG_PCH# CLK_PEG_PCH AR24 AT24 PCIECLKRQ7#/GPIO46 LYNXPOINT_BGA695 B AF6 PEG_CLKREQ# AY24 AW24 CLKIN_SATA CLKIN_SATA_P CLOCK SIGNAL CLK_PEG_PCH CLKIN_GND CLKIN_GND_P CLKOUT_PCIE_N_7 CLKOUT_PCIE_P_7 CLK_PEG_PCH# AB36 CLKIN_DMI CLKIN_DMI_P CLKIN_DOT96N CLKIN_DOT96P CLKOUT_PCIE_N_6 CLKOUT_PCIE_P_6 PCIECLKRQ6#/GPIO45 AB35 PAD~D PAD~D AN44 PCH_CLK_BIASREF 1 7.5K_0402_1%~D 2 0_0402_5% T149 @ T150 @ 2 RH208 YH4 25MHZ_10PF_Q22FA2380049900~D 3 OUT IN 1 <33,42> +1.5VS +1.05V_+1.5V_RUN 4 2 GND GND 2 2 1 1 CH19 8.2P_0402_50V8D~D RH151 AH43 CLKOUT_PEG_A_P XTAL25_IN_R 1 10K_0402_5%~D CLKOUT_PEG_A CLKOUT_PCIE_P_0 CH18 8.2P_0402_50V8D~D <51> CLK_DEBUG 2 RH280 2 <6> CLK_CPU_ITP <43> CLK_PCI_LPC RH127 RH281 <6> CLK_CPU_ITP# 5 CLKOUT_PCIE_N_0 2 OF 11 B +3VS CAM_DET# 10K_0402_5%~D1 2 RH216 DMC_PCH_DET# 10K_0402_5%~D1 2 RH217 PCH_GPIO66 2 RH218 10K_0402_5%~D1 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (3/9) CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 19 of 61 5 4 3 2 1 2 +3VS SML1CLK 6 1 5 SML1DATA D 3 4 1 1 1 PCH_SMBCLK <6,12,13,14,15,49,50,51,53> QH9A DMN66D0LDW-7_SOT363-6~D 5 MEM_SMBDATA 2 2.2K_0402_5%~D 2 2 RH310 2.2K_0402_5%~D 6 3 4 PCH_SMBDATA <6,12,13,14,15,49,50,51,53> +3V_PCH QH9B DMN66D0LDW-7_SOT363-6~D +3VS 1 RH337 2 SERIRQ 10K_0402_5%~D LPT_PCH_M_EDS UH1D <43,51> LPC_AD0 <43,51> LPC_AD1 C <43,51> LPC_AD3 <43,51> LPC_FRAME# A20 LAD_0 LPC_AD1 C20 LAD_1 LPC_AD2 A18 C18 LAD_3 LPC_FRAME# B21 LFRAME# D21 <31,34> PANEL_SW <43> SERIRQ LAD_2 LPC_AD3 PANEL_SW G20 SERIRQ AL11 AJ7 AL7 PCH_SPI_SI PCH_SPI_SO SMBDATA SML0ALERT#/GPIO60 N8 DDR_HVREF_RST_PCH SML0CLK U8 SML0CLK SML0DATA R7 SML0DATA SML1ALERT#/PCHHOT#/GPIO74 H6 PCH_GPIO74 K6 SML1CLK N11 SML1DATA SML1CLK/GPIO58 SERIRQ CL_RST# SPI_MOSI AJ4 AJ2 <43,47,48,53> MEM_SMBCLK 2.2K_0402_5%~D MEM_SMBDATA 2.2K_0402_5%~D DDR_HVREF_RST_PCH 1K_0402_1%~D PCH_GPIO74 10K_0402_5%~D SML1CLK 2.2K_0402_5%~D SML1DATA 2.2K_0402_5%~D 2 1 RH302 2 1 2 1 2 1 1 2 1 2 RH303 RH300 RH301 RH298 RH299 C +3V_PCH SML0CLK 2 2.2K_0402_5%~D SML0DATA 2 2.2K_0402_5%~D 1 RH305 1 RH306 AF11 AF10 AF7 SPI_CS1# SPI_CS2# PCH_SPI_DO3 CL_CLK CL_DATA C-Link SPI_CS0# AH1 PCH_SPI_DO2 LID_SW_IN# @ MEM_SMBDATA LDRQ1#/GPIO23 AJ10 AH3 20_0402_5%~D MEM_SMBCLK LDRQ0# SPI_CLK EC_LID_OUT# <43> RH3691 U11 SPI AJ11 PCH_SPI_CS0# 20_0402_5%~D R10 SML1DATA/GPIO75 PCH_SPI_CLK N7 PCH_LID_SW_IN# RH3681 SMBCLK SMBus LPC <43,51> LPC_AD2 SMBALERT#/GPIO11 LPC_AD0 D QH10B DMN66D0LDW-7_SOT363-6~D RH304 MEM_SMBCLK <40,43,53,54> EC_SMB_DA2 <40,43,53,54> +3VS +3VS EC_SMB_CK2 QH10A DMN66D0LDW-7_SOT363-6~D BA45 PAD~D T130 @ BC45 PAD~D T133 @ TP4 BE43 PAD~D T131 @ TP3 BE44 PAD~D T132 @ TP1 TP2 Thermal SPI_MISO SPI_IO2 SPI_IO3 TD_IREF B LYNXPOINT_BGA695 3 OF 11 AY43 PCH_TD_IREF 1 RH322 2 B 8.2K_0402_1% 5 +3V_PCH +3V_PCH PCH_SPI_CLK 64Mb Flash ROM RH60 @ 33_0402_5%~D 0.1U_0402_25V6K~D UH14 PCH_SPI_CS0#_R 2 2 33_0402_5%~D PCH_SPI_DO2_R 3 1 4 /CS VCC DO /HOLD /WP CLK GND DIO 8 7 PCH_SPI_DO3_R RH3741 2 33_0402_5%~D PCH_SPI_DO3 6 PCH_SPI_CLK_R RH3761 2 33_0402_5%~D PCH_SPI_CLK 5 PCH_SPI_SI_R RH3771 2 33_0402_5%~D PCH_SPI_SI 1 @ 2 33_0402_5%~D PCH_SPI_SO_R CH8 22P_0402_50V8J~D 2 0_0402_5%~D PCH_SPI_SO PCH_SPI_DO2 RH3751 2 200 MIL SO8 PCH_SPI_CS0# RH3731 RH3721 CH56 1 2 1 2 @ +3V_PCH 1 2 PCH_SPI_DO3_R 3.3K_0402_5%~D 2 PCH_SPI_DO2_R 3.3K_0402_5%~D RH58 3.3K_0402_5% 1 RH370 1 RH371 2 64M EN25Q64-104HIP_SO8 EON Reserve for EMI please close to UH14 A Compal Secret Data Security Classification Issued Date A 2012/06/22 2013/06/21 Deciphered Date Title PCH (4/9) SPI, SMBUS,LPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 20 of 61 5 4 3 2 1 D D LPT_PCH_M_EDS UH1I BD33 BB33 <44> PCIE_PRX_GLANTX_N1 <44> PCIE_PRX_GLANTX_P1 10/100/1G LAN <44> PCIE_PTX_GLANRX_N1 <44> PCIE_PTX_GLANRX_P1 <53> PCIE_PTX_CARDRX_N4 <53> PCIE_PTX_CARDRX_P4 AW33 AY33 CH149 CH150 1 1 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C BE34 BC34 PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 AT33 AR33 CH153 CH154 1 1 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C BE36 BC36 <53> PCIE_PRX_CARDTX_N4 <53> PCIE_PRX_CARDTX_P4 CARD READER C PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1 BD37 BB37 BC38 BE38 AT40 AT39 BE40 BC40 +1.5VS 1 RH51 @ T134 @ T136 +1.5VS 2 1 RH210 PCH_PCIE_IREF 0_0402_5% PAD~D PERN_3 PERP_3 PETN_3 PETP_3 PERN_4 PERP_4 PETN_4 PETP_4 PERN_5 PERP_5 PETN_5 PETP_5 PETN_6 PETP_6 PERN_7 PERP_7 PETN_7 PETP_7 PERN_8 PERP_8 BD42 BD41 PETN_8 PETP_8 BE30 BB29 PCH_PCIE_RCOMP BD29 7.5K_0402_1%~D USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 PERN_6 PERP_6 AN38 AN39 BC30 PAD~D 2 PETN2/USB3TN4 PETP2/USB3TP4 USBRBIAS# USBRBIAS PCIE_IREF TP24 TP23 TP11 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14 TP6 PCIE_RCOMP USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 K24 K26 USBRBIAS USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 M33 L33 P3 USB_OC0# V1 USB_OC1# U2 USB_OC2# P1 USB_OC3# M3 USB_OC4# T1 USB_OC5# N2 USB_OC6# M1 USB_OC7# USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 PAD~D PAD~D <52> <52> <52> <52> <53> <53> <53> <53> <51> <51> <51> <51> <47> <47> <55> <55> <33> <33> <42> <42> <53> <53> JUSB1 JUSB2 JUSB3 JUSB4 Mini Card(WLAN) Mini Card(DMC) ELC LED IR sensor eDP Camera C LVDS Camera VPK K/B USBRBIAS <52> <52> <52> <52> <52> <52> <52> <52> <53> <53> <53> <53> <53> <53> <53> <53> P1: JUSB1 P2: JUSB2 RH160 22.6_0402_1%~D AY38 AW38 PERN2/USB3RN4 PERP2/USB3RP4 PCIe AW36 AV36 PETN1/USB3TN3 PETP1/USB3TP3 B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24 1 AT31 AR31 USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9 USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13 2 BE32 BC32 PERN1/USB3RN3 PERP1/USB3RP3 USB AW31 AY31 P5: JUSB3 P6: JUSB4 CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils. T135 @ T137 @ USB_OC0# USB_OC1# USB_OC2# USB_OC3# +3V_PCH <52> <52> <53> <53> RPH1 USB_OC0# USB_OC1# USB_OC3# USB_OC4# 4 3 2 1 5 6 7 8 10K_1206_8P4R_5%~D RPH2 B LYNXPOINT_BGA695 9 OF 11 USB_OC5# USB_OC6# USB_OC7# USB_OC2# 5 4 3 2 1 B 5 6 7 8 10K_1206_8P4R_5%~D A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (5/9) PCIE,USB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 21 of 61 5 4 3 2 1 D D +3VS +3VS 2 1 2 1 2 RH257 RH258 EC_SMI# DGPU_HPD_INT# A14 EC_SCI# G15 EC_SMI# Y1 EDP_DETECT# <41> EDP_DETECT# K13 PCH_GPIO15 AB11 PCH_GPIO16 AN2 C14 +3V_PCH 2 1 RH187 HDD_DET# 10K_0402_5%~D <50> ODD_EN# PCH_GPIO22 BB4 ODD_EN# Y10 PCH_GPIO27 1 2 2 1 2 1 RH354 RH182 RH264 PCH_GPIO15 1K_0402_1%~D ODD_EN# 10K_0402_5%~D PCH_GPIO35 10K_0402_5%~D PCH_GPIO28 2 1 @ RH269 AP1 ODD_DETECT# AT3 PCH_GPIO37 AK1 <29> VGA_PRSNT_R# VGA_PRSNT_R# AT7 <29> VGA_PRSNT_L# VGA_PRSNT_L# AM3 FFS_INT2 AN4 PCH_GPIO49 AK3 HDD_DET# U12 <49,50> FFS_INT2 <49> HDD_DET# +3V_PCH DGPU_BKL_PWM_SEL# C16 <33> EDP_CAB_DET# <42> LVDS_CAB_DET# 1 LVDS_CAB_DET# G13 WiGi_RADIO_DIS# H15 PECI SATA4GP/GPIO16 RCIN# GPIO TACH0/GPIO17 PROCPWRGD SCLOCK/GPIO22 THRMTRIP# GPIO24 PLTRST_PROC# GPIO27 VSS 1 2 @ RH353 1K_0402_1%~D 1 2 TP_VSS_NCTF 0_0402_5%~D BE41 BE5 C45 A5 2 RH184 GATEA20 1 0_0402_5%~D AT6 KB_RST# AV3 H_CPUPWRGD AV1 PCH_THRMTRIP#_R AU4 CPU_PLTRST# <43> H_PECI <6,43> KB_RST# <43> H_CPUPWRGD <6> 1 2 RH262 390_0402_5% H_THERMTRIP# <6> CPU_PLTRST# <6> N10 GPIO34 GPIO35/NMI# SATA2GP/GPIO36 SATA3GP/GPIO37 C SLOAD/GPIO38 SDATAOUT0/GPIO39 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71 VSS VSS VSS VSS NCTF LYNXPOINT_BGA695 PLL ON DIE VR ENABLE GATEA20 GPIO28 PCH_GPIO28 RH162 AN10 AY1 6 OF 11 A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4 +5VS +5VALW PCH_VSS_A44 PCH_VSS_B45 PCH_VSS_BD1 PCH_VSS_A44 PCH_VSS_B45 PCH_VSS_BD1 RH170 0_0402_5%~D D13 TP14 GPIO15 RH168 0_0402_5%~D <51> WiGi_RADIO_DIS# EDP_CAB_DET# LAN_PHY_PWR_CTRL/GPIO12 RH165 0_0402_5%~D RH53 4.7K_0402_5%~D 2 <42> DGPU_BKL_PWM_SEL# GPIO8 @ RH175 0_0402_5%~D PCH_GPIO35 CPU/Misc TACH3/GPIO7 @ RH166 0_0402_5%~D AN6 <36> PCH_GPIO35 PCH_GPIO27 10K_0402_5%~D AD11 STP_PCI# <50> ODD_DETECT# C R11 TACH2/GPIO6 2 1 RH256 <43> EC_SCI# 1 2 <43> RH203 TACH1/GPIO1 @ 1 RH57 <36,39> DGPU_HPD_INT# F13 RH161 1 2 2 DGPU_EDIDSEL# BMBUSY#/GPIO0 1 1 1 RH267 AT8 2 2 RH179 <32,36,42> DGPU_EDIDSEL# DMC_RADIO_OFF# 1 1 2 LPT_PCH_M_EDS UH1F <51> DMC_RADIO_OFF# 2 1 RH164 DMC_RADIO_OFF# 10K_0402_5%~D DGPU_EDIDSEL# 10K_0402_5%~D DGPU_HPD_INT# 10K_0402_5%~D STP_PCI# 10K_0402_5%~D VGA_PRSNT_R# 10K_0402_5%~D VGA_PRSNT_L# 20K_0402_5%~D PCH_GPIO22 10K_0402_5%~D LVDS_CAB_DET# 10K_0402_5%~D EDP_CAB_DET# 10K_0402_5%~D 1 2 2 2 1 RH271 1 1 RH270 GATEA20 2 10K_0402_5%~D KB_RST# 2 10K_0402_5%~D 5 +3VS ENABLED - HIGH(DEFAULT) DISABLED - LOW 1 RH272 @ 2 RH266 2 B 2 1 1 RH265 2 RH268 @ 1 PCH_GPIO16 10K_0402_5%~D PCH_GPIO49 10K_0402_5%~D PCH_GPIO16 10K_0402_5%~D PCH_GPIO49 10K_0402_5%~D B +3VS Config GPIO16,49 1 2 1 2 2 1 2 1 RH176 * USB X4,PCIEX8,SATAX6 11 USB X6,PCIEX8,SATAX4 01 @ RH171 @ RH174 RH181 ODD_DETECT# 200K_0402_5% PCH_GPIO37 200K_0402_5% ODD_DETECT# 10K_0402_5%~D PCH_GPIO37 10K_0402_5%~D SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK. WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER PLRST_N DE-ASSERTS). NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED. A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (6/9) GPIO,MISC,NTFC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 22 of 61 5 4 3 2 1 D D LH1 2 1 1 BLM18PG181SN1_0603~D 0_0603_5%~D +VCCADAC 2 1 2 2 Voltage Rail +1.05V_+1.5V_RUN C +1.05VS VSS CRT DAC VCCADACBG3_3 VCCVRM FDI VCCIO DCPSUS1 Core VCCSUS3_3 VCCSUS3_3 +1.05V VCCMPHY BE22 VCCIO AK18 +PCH_USB_DCPSUS3 +1.05VS +1.05V_+1.5V_RUN +1.05VS AK22 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO AM18 AM20 AM22 AP22 AR22 AT22 1 +1.05VS 2 1 2 5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0_0603_5%~D +1.05VS 1 1.05V 1.29 A 3.629 A VCCADAC1_5 1.5V 0.070 A VCCADAC3_3 3.3V 0.0133 A VCCCLK 1.05V 0.306 A VCCCLK3_3 3.3V 0.055 A VCCVRM 1.5V 0.179 A VCC3_3 3.3V 0.133 A VCCASW 1.05V 0.67 A VCCSUSHDA 3.3V 0.01 A VCCSPI 3.3V 0.022 A C VCCSUS3_3 3.3V 0.261 A VCCDSW3_3 3.3V 0.015 A V_PROC_IO 1.05V 0.004 A 2 1 2 @ CH39 1U_0402_6.3V6K~D 1 2 1 RH360 @ +1.05V +PCH_USB_DCPSUS3 0_0603_5%~D 0_0603_5%~D @ CH40 10U_0603_6.3V6M~D 2 @ CH34 1U_0402_6.3V6K~D 1 2 @ RH198 VCCIO +1.05V +PCH_USB_DCPSUS1 0_0402_5%~D 1 RH197 S0 Iccmax Current (A) 1.05V B +1.05V_+1.5V_RUN 2 2 +1.05V_+1.5V_RUN +1.05V_+1.5V_RUN AN11 VCCIO 2 1 @ CH61 1U_0402_6.3V6K~D +PCH_VCCDSW_R VCCVRM 2 CH44 10U_0603_6.3V6M~D +1.5VS AJ30 AJ32 CH45 1U_0402_6.3V6K~D +PCH_VCCDSW 5.11_0402_1%~D 1 CH46 1U_0402_6.3V6K~D 2 +PCH_USB_DCPSUS1 CH47 1U_0402_6.3V6K~D 1 @ RH37 7 OF 11 Y12 1 CH86 1U_0402_6.3V6K~D LYNXPOINT_BGA695 +3V_PCH R30 R32 AJ26 AJ28 AK20 AK26 AK28 VCCVRM 2 AN35 DCPSUS3 DCPSUS3 VCCIO VCCVRM VCCVRM SATA B AN34 @ CH85 10U_0603_6.3V6M~D C_0805NEW PCIe/DMI +3VS @ CH82 10U_0603_6.3V6M~D 2 DCPSUSBYP VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW 1 BB44 @ CH83 10U_0603_6.3V6M~D 2 1 CH36 1U_0402_6.3V6K~D 1 CH35 1U_0402_6.3V6K~D 2 CH64 22U_0805_6.3V6M~D 1 USB3 +PCH_VCCDSW U14 AA18 U18 U20 U22 U24 V18 V20 V22 V24 Y18 Y20 Y22 +3VS CH60 0.1U_0402_10V7K~D VCC3_3_R30 VCC3_3_R32 HVCMOS +1.05VS M31 CH38 0.1U_0402_10V7K~D VCCIO P43 @ CH81 10U_0603_6.3V6M~D 2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Voltage VCC P45 CH48 1U_0402_6.3V6K~D 2 1 CH31 1U_0402_6.3V6K~D 2 1 CH33 1U_0402_6.3V6K~D 1 CH32 1U_0402_6.3V6K~D 2 CH30 10U_0603_6.3V6M~D 1 VCCADAC1_5 AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24 Y26 PCH Power Rail Table +1.5VS RH211 CH156 10U_0603_6.3V6M~D LPT_PCH_M_EDS UH1G 1 CH80 0.1U_0402_10V7K~D 2 CH57 0.01U_0402_16V7K~D 1 1 2 RH209 @ A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (7/9) Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 23 of 61 5 4 3 2 1 D D +PCH_VCCDSW3_3 LPT_PCH_M_EDS R24 R26 R28 U26 +1.05VS M24 U35 L29 L26 M26 U32 V32 AD34 +PCH_VCCCLK AA30 AA32 AD35 AG30 AG32 VCCSUSHDA A26 1 VCCVRM VCC VCCSUS3_3 VCCCLK VCCRTC RTC VCCCLK3_3 DCPRTC DCPRTC K8 +PCH_DCPRTC P14 P16 VCCCLK3_3 VCCCLK3_3 VCCCLK3_3 V_PROC_IO V_PROC_IO CPU VCCCLK3_3 VCCCLK3_3 VCCSPI SPI VCCCLK VCC VCC VCCCLK VCCCLK VCCASW Fuse VCCCLK VCCASW VCCCLK VCCCLK VCCVRM VCCCLK VCC3_3 Thermal VCCCLK VCCCLK VCC3_3 LYNXPOINT_BGA695 AJ12 AJ14 CH70 1 2 1 0.1U_0402_10V7K~D +PCH_VPROC +3V_PCH AD12 P18 +PCH_VCCCFUSE P20 L17 +1.05V 1 2 1 2 1 2 2 2 1 2 1 2 C +1.05VS AW40 +PCH_VPROC +1.5VS +3VS AK30 1 AK32 5 2 2 1 2 2 1 2 CH75 1U_0402_6.3V6K~D 1 B 2 1 0_0805_5%~D +PCH_VCCCFUSE Place near pin AP45 +1.05VS 2 R18 CH51 1U_0402_6.3V6K~D 1 8 OF 11 +RTC_CELL A6 RH219 CH71 1U_0402_6.3V6K~D +PCH_VCC 2 0_0603_5%~D 1 RH207 2 Azalia DCPSUS2 1 CH55 10U_0603_6.3V6M~D LH100 1 2 4.7UH_LQM18FN4R7M00D_20%~D 1 +3V_PCH CH72 0.1U_0402_10V7K~D AE30 AE32 +1.05VS_VCC +3V_PCH +1.05VS CH76 0.1U_0402_10V7K~D +1.05VS +3VS 2 0.1U_0402_10V7K~D AE14 AF12 AG14 U36 +3VALW RH253 CH73 0.1U_0402_10V7K~D AD36 VCCIO +PCH_VCCSST 1 CH84 CH67 1U_0402_6.3V6K~D M29 +PCH_VCCCLK3_3 VCC3_3 VCC3_3 VCC3_3 VCCIO VCCIO VCCIO VCCIO +PCH_VCCDSW3_3 AA14 CH74 1U_0402_6.3V6K~D 2 Y32 VCC3_3 ICC @ CH87 1U_0402_6.3V6K~D 1 AP45 DCPSST VCCUSBPLL A16 CH69 0.1U_0402_10V7K~D 2 +PCH_VCC +PCH_VCCCLK VCCDSW3_3 +3V_PCH RH213 @ CH59 1U_0402_6.3V6K~D 1 +PCH_USB_DCPSUS2 2 0_0402_5%~D 1 @ RH361 C Y35 AF34 2 GPIO/LPC VSS 1 CH68 0.1U_0402_10V7K~D +1.05V +PCH_USB_DCPSUS2 +1.05V_+1.5V_RUN CH42 10U_0603_6.3V6M~D 2 CH37 1U_0402_6.3V6K~D 1 R20 R22 1 2 0_0402_5%~D CH90 0.1U_0402_10V7K~D 2 U30 V28 V30 Y30 +1.05VS VCCSUS3_3 VCCSUS3_3 1 2 0_0402_5%~D CH65 0.1U_0402_10V7K~D L24 1 CH63 0.1U_0402_10V7K~D 2 +3VS VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 USB 1 CH62 0.1U_0402_10V7K~D 2 CH66 0.1U_0402_10V7K~D 1 +3V_PCH CH155 0.1U_0402_10V7K~D UH1H +3V_PCH 2 1 2 1 0_0805_5%~D RH220 0_0805_5%~D RH221 @ +3VS +1.05VS B +PCH_VCCCLK 1 2 RH214 0_0805_5%~D 1 2 Place near pin Y32,AA30,AA32 1 2 Place near pin AD34 Place near pin AD35,AD36 1 2 CH79 1U_0402_6.3V6K~D +3VS 2 CH78 1U_0402_6.3V6K~D Place near pin AP45 1 CH77 1U_0402_6.3V6K~D 2 CH50 1U_0402_6.3V6K~D 1 CH49 1U_0402_6.3V6K~D 2 @ CH43 10U_0603_6.3V6M~D 1 Place near pin AG30,AG32,AE30,AE32 +PCH_VCCCLK3_3 1 RH212 2 0_0805_5%~D Place near pin M29 Place near pin L29 1 2 Place near pin L26,M26 1 2 CH58 1U_0402_6.3V6K~D 2 CH53 1U_0402_6.3V6K~D 1 CH54 1U_0402_6.3V6K~D 2 CH52 1U_0402_6.3V6K~D 1 Place near pin U32,V32 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. PCH (8/9) Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 24 of 61 5 4 3 2 1 D D UH1J LPT_PCH_M_EDS AL34 AL38 AL8 AM14 AM24 AM26 AM28 AM30 AM32 AM16 AN36 AN40 AN42 AN8 AP13 AP24 AP31 AP43 AR2 AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38 D42 AV13 AV22 AV24 AV31 AV33 BB25 AV40 AV6 AW2 F43 AY10 AY15 AY20 AY26 AY29 AY7 B11 B15 C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS UH1K VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8 AA16 AA20 AA22 AA28 AA4 AB12 AB34 AB38 AB8 AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40 AD6 AD8 AE16 AE28 AF38 AF8 AG16 AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38 AJ6 AJ8 AK14 AK24 AK43 AK45 AL12 AL2 BC22 BB42 LPT_PCH_M_EDS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28 C B LYNXPOINT_BGA695 LYNXPOINT_BGA695 10 OF 11 11 OF 11 5 5 A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. PCH (9/9) Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 25 of 61 3 2 <63> 1 VINRV89 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 1 2 3 4 VIN+ VINGND VS 1 1 <17,43,47,57,63> ACIN 2 B @ MC74VHC1G09DFT2G_SC70-5 PEG_GTX_HRX_N1 PEG_GTX_HRX_P1 PEG_GTX_HRX_N0 PEG_GTX_HRX_P0 CLK_PEG_PCH#_R CLK_PEG_PCH_R 2 0_0402_5%~D 2 0_0402_5%~D 2 10K_0402_5%~D J13 @ 2 1 2 VGA_SMB_DA1 VGA_SMB_CK1 SYSTEM 0_0402_5%~D RV92 1 2 +3VMXM <41> LVDS_MXM_TZCLK<41> LVDS_MXM_TZCLK+ 1 LVDS TZ PAD-OPEN 4x4m <41> LVDS_MXM_TZOUT2<41> LVDS_MXM_TZOUT2+ <41> LVDS_MXM_TZOUT1<41> LVDS_MXM_TZOUT1+ FB_CLAMP_TGL_REQ# <43> PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_P15 +3V_MXM HDMI PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P7 <41> LVDS_MXM_TZOUT0<41> LVDS_MXM_TZOUT0+ LVDS_MXM_TZOUT1LVDS_MXM_TZOUT1+ LVDS_MXM_TZOUT0LVDS_MXM_TZOUT0+ GPU_HDMI_TXD2GPU_HDMI_TXD2+ <36> GPU_HDMI_TXD1<36> GPU_HDMI_TXD1+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ <36> GPU_HDMI_TXD0<36> GPU_HDMI_TXD0+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ <36> GPU_HDMI_TXC<36> GPU_HDMI_TXC+ GPU_HDMI_TXCGPU_HDMI_TXC+ <36> GPU_HDMI_SDATA <36> GPU_HDMI_SCLK @ LVDS_MXM_TZOUT2LVDS_MXM_TZOUT2+ <36> GPU_HDMI_TXD2<36> GPU_HDMI_TXD2+ GPU_HDMI_SDATA GPU_HDMI_SCLK VGA_PS_0 @ PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P5 DMC PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P3 LVDS_MXM_TZCLKLVDS_MXM_TZCLK+ Place CV9, CV10, CV11 close MXM connector VGA_PS_0 @ CV9 2 VGA_PS_1 @ CV10 2 VGA_PS_2 @ CV11 2 1 0.01U_0402_16V7K~D 1 0.01U_0402_16V7K~D 1 0.01U_0402_16V7K~D <39> VGA_DPD_N0 <39> VGA_DPD_P0 VGA_DPD_N0 VGA_DPD_P0 <39> VGA_DPD_N1 <39> VGA_DPD_P1 VGA_DPD_N1 VGA_DPD_P1 <39> VGA_DPD_N2 <39> VGA_DPD_P2 VGA_DPD_N2 VGA_DPD_P2 <39> VGA_DPD_N3 <39> VGA_DPD_P3 VGA_DPD_N3 VGA_DPD_P3 <39> VGA_DPD_AUXN/DDC <39> VGA_DPD_AUXP/DDC <21> VGA_PRSNT_L# (Pull-UP 10K at PCH) 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 310 311 A1 A0 SDA SCL B+_MXM_A1 B+_MXM_A0 MXM_CURI2C_DATA MXM_CURI2C_CLK 8 7 6 5 0_0402_5%~D 2 0_0402_5%~D 2 1 1 2 2 VGA_SMB_DA1 3 2 G QV6 SSM3K7002F_SC59-3~D VGA_SMB_CK1 S 2 PEG_GTX_HRX_N2 PEG_GTX_HRX_P2 2 0_0402_5%~D RV76 1 RV77 1 +3V_MXM PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P12 G 1 1 2 AC_BATT# 4 Y DGPU_PWROK <30,43> DGPU_PWR_EN <43,56> PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P14 1 <43> 1 <43> EC_SMB_CK1 UV4 3 A 1 RV94 VGA_PS_0 VGA_PS_1 VGA_PS_2 TH_OVERT# 3 QV8 SSM3K7002F_SC59-3~D JMXM1B <18> CLK_PEG_PCH# VGA_PRSNT_R# <21> <18> CLK_PEG_PCH AC_BATT# VGA_TH_OVERT# 1 RV79 <43> EC_SMB_DA1 1 QV7 SSM3K7002F_SC59-3~D CV5 0.1U_0402_25V6K~D 2 <43> EC_AC_BAT# VGA_PRSNT_R# VGA_WAKE# DGPU_PWROK DGPU_PWR_EN 3 1 GND GND PEX_RX2# PEX_TX2# PEX_RX2 PEX_TX2 GND GND PEX_RX1# PEX_TX1# PEX_RX1 PEX_TX1 GND GND PEX_RX0# PEX_TX0# PEX_RX0 PEX_TX0 GND GND PEX_REFCLK# PEX_CLK_REQ# PEX_REFCLK PEX_RST# GND VGA_DDC_DAT RSVD VGA_DDC_CLK RSVD VGA_VSYNC RSVD VGA_HSYNC RSVD GND RSVD VGA_RED LVDS_UCLK# VGA_GREEN LVDS_UCLK VGA_BLUE GND GND LVDS_UTX3# LVDS_LCLK# LVDS_UTX3 LVDS_LCLK GND GND LVDS_UTX2# LVDS_LTX3# LVDS_UTX2 LVDS_LTX3 GND GND LVDS_UTX1# LVDS_LTX2# LVDS_UTX1 LVDS_LTX2 GND GND LVDS_UTX0# LVDS_LTX1# LVDS_UTX0 LVDS_LTX1 GND GND DP_C_L0# LVDS_LTX0# DP_C_L0 LVDS_LTX0 GND GND DP_C_L1# DP_D_L0# DP_C_L1 DP_D_L0 GND GND DP_C_L2# DP_D_L1# DP_C_L2 DP_D_L1 GND GND DP_C_L3# DP_D_L2# DP_C_L3 DP_D_L2 GND GND DP_C_AUX# DP_D_L3# DP_C_AUX DP_D_L3 RSVD GND RSVD DP_D_AUX# RSVD DP_D_AUX RSVD DP_C_HPD RSVD DP_D_HPD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND RSVD DP_B_L0# RSVD DP_B_L0 RSVD GND GND DP_B_L1# DP_A_L0# DP_B_L1 DP_A_L0 GND GND DP_B_L2# DP_A_L1# DP_B_L2 DP_A_L1 GND GND DP_B_L3# DP_A_L2# DP_B_L3 DP_A_L2 GND GND DP_B_AUX# DP_A_L3# DP_B_AUX DP_A_L3 DP_B_HPD GND DP_A_HPD DP_A_AUX# 3V3 DP_A_AUX 3V3 PRSNT_L# GND GND 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P0 PEG_CLKREQ# PLTRST_VGA# PEG_CLKREQ# <18> PLTRST_VGA# <17> CRT LVDS_MXM_TXCLKLVDS_MXM_TXCLK+ LVDS_MXM_TXCLK- <41> LVDS_MXM_TXCLK+ <41> C LVDS TX LVDS_MXM_TXOUT2LVDS_MXM_TXOUT2+ LVDS_MXM_TXOUT1LVDS_MXM_TXOUT1+ LVDS_MXM_TXOUT0LVDS_MXM_TXOUT0+ MXM_TX0N MXM_TX0P LVDS_MXM_TXOUT2- <41> LVDS_MXM_TXOUT2+ <41> LVDS_MXM_TXOUT1- <41> LVDS_MXM_TXOUT1+ <41> LVDS_MXM_TXOUT0- <41> LVDS_MXM_TXOUT0+ <41> MXM_TX0N MXM_TX0P <32> <32> MXM_TX1N MXM_TX1P MXM_TX1N MXM_TX1P <32> <32> MXM_TX2N MXM_TX2P MXM_TX2N MXM_TX2P <32> <32> MXM_TX3N MXM_TX3P MXM_TX3N MXM_TX3P <32> <32> MXM_DPB_AUXN/DDC MXM_DPB_AUXP/DDC VGA_HDMI_DET MXM_DPB_HPD MXM_DPB_AUXN/DDC <32> MXM_DPB_AUXP/DDC <32> VGA_HDMI_DET <36> MXM_DPB_HPD <32> VGA_DPC_N0 VGA_DPC_P0 eDP VGA_DPC_N0 <30> VGA_DPC_P0 <30> VGA_DPC_N1 VGA_DPC_P1 VGA_DPC_N1 <30> VGA_DPC_P1 <30> VGA_DPC_N2 VGA_DPC_P2 VGA_DPC_N2 <30> VGA_DPC_P2 <30> VGA_DPC_N3 VGA_DPC_P3 VGA_DPC_N3 <30> VGA_DPC_P3 <30> VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC VGA_DPC_HPD VGA_DMC_HPD VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC VGA_DPC_HPD <30> VGA_DMC_HPD <39> B mDP <30> <30> +3V_MXM 40mil(1A) 312 JAE_MM70-314-310B1-1-R300 CONN@ For B+_MXM slave address : 1000010 please placemnet near R-sense UV5 2 2 0_0402_5%~D +3V_MXM 2 2 5 2 1 G VCC 2 1 2 +3VALW VGA_TH_OVERT# 1 RV83 0_0402_5%~D 1 2 GND GND GND GND GND E4 GND GND GND GND PRSNT_R# WAKE# PWR_GOOD PWR_EN RSVD RSVD RSVD RSVD PWR_LEVEL TH_OVERT# TH_ALERT# TH_PWM GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND 2 4 6 8 10 12 14 16 18 2 RV85 0_0402_5%~D 1 2 2 1 2 1 2 1 2 1 GND GND GND GND GND E3 GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW# VGA_DISABLE# PNL_PWR_EN PNL_BL_EN PNL_BL_PWM HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND 1 @ CV12 .1U_0402_16V7K~D D RV74 4.7K_0402_5%~D E2 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC JAE_MM70-314-310B1-1-R300 CONN@ 2 0_0402_5%~D 1 10K_0402_5%~D +3V_MXM RV73 4.7K_0402_5%~D RV88 2 RV70 D 1 VIN+ +3V_MXM +3VALW S <63> AC_BATT# CV8 4.7U_0805_10V4Z~D B 2 3.3K_0402_5% 2 3.3K_0402_5% CV4 0.1U_0603_25V7K~D SPDIF_OUT @ RV80 1 @ RV81 1 1 1 1 CV3 68P_0402_50V8J~D +3V_MXM 19 21 23 25 2 2 27 29 31 +5V_MXM 33 35 37 39 41 43 45 47 100mil(2.5A, 5VIA) 49 Add R7 increase NV MXM PEG Swing 51 53 RV781 55 2 0_0402_5%~D VGA_DISABLE# 57 59 <42> DGPU_ENVDD 61 <42> DGPU_BKL_EN 63 <42> VGA_PNL_PWM VGA_HDMI_CEC 65 67 VGA_LCD_DAT 69 <42> VGA_LCD_DAT VGA_LCD_CLK 71 <42> VGA_LCD_CLK 73 LVDS DDC Module have 4.7K Pull-UP 75 210K_0402_5%~D 77 236K_0402_1% 79 RV93 1 0_0402_5%~D 81 2 <43> FB_CLAMP 83 PEG_GTX_HRX_N15 85 +3V_MXM PEG_GTX_HRX_P15 87 89 PEG_GTX_HRX_N14 91 PEG_GTX_HRX_P14 93 RV82 95 10K_0402_5%~D PEG_GTX_HRX_N13 97 PEG_GTX_HRX_P13 99 101 PEG_GTX_HRX_N12 103 B+_MXM_A0 PEG_GTX_HRX_P12 105 107 PEG_GTX_HRX_N11 109 PEG_GTX_HRX_P11 111 RV84 @ 113 10K_0402_5%~D PEG_GTX_HRX_N10 115 PEG_GTX_HRX_P10 117 119 PEG_GTX_HRX_N9 121 PEG_GTX_HRX_P9 123 125 +3V_MXM PEG_GTX_HRX_N8 127 PEG_GTX_HRX_P8 129 131 PEG_GTX_HRX_N7 133 PEG_GTX_HRX_P7 @ RV86 135 10K_0402_5%~D 137 PEG_GTX_HRX_N6 139 PEG_GTX_HRX_P6 141 143 B+_MXM_A1 PEG_GTX_HRX_N5 145 PEG_GTX_HRX_P5 147 149 PEG_GTX_HRX_N4 151 PEG_GTX_HRX_P4 RV87 153 10K_0402_5%~D 155 PEG_GTX_HRX_N3 157 PEG_GTX_HRX_P3 159 161 1 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRCE1 PWR_SRC PWR_SRC PWR_SRC PWR_SRC CV2 680P_0603_50V7K~D C CV7 10U_0603_6.3V6M~D 1 PAD-OPEN 4x4m CV6 0.1U_0402_16V4Z~D 2 MXM_CURI2C_CLK @ RV64 MXM_CURI2C_DATA @ RV66 400mil(10A) CV1 10U_1206_25V6M~D +5V_MXM 4.3K_0402_5% 4.3K_0402_5% 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D B+_MXM JMXM1A 1 3 5 7 9 11 13 15 17 J12 @ @ @ 2 2 1 2 2 2 G B+_MXM 1 1 2 1 1 1 RV72 10K_0402_5%~D PEG_GTX_HRX_P[0..15] <5> PEG_GTX_HRX_P[0..15] RV63 RV65 RV67 RV68 RV69 RV75 RV71 10K_0402_5%~D PEG_GTX_HRX_N[0..15] <5> PEG_GTX_HRX_N[0..15] +5VMXM +3V_MXM +3V_MXM VGA_LCD_CLK VGA_LCD_DAT DGPU_PWROK VGA_HDMI_CEC VGA_DISABLE# VGA_WAKE# PEG_HTX_C_GRX_P[0..15] <5> PEG_HTX_C_GRX_P[0..15] D +3V_MXM PEG_HTX_C_GRX_N[0..15] <5> PEG_HTX_C_GRX_N[0..15] D 1 S 4 D 5 1 RV90 VGA_SMB_DA1 1 RV91 VGA_SMB_CK1 HPA00900AIDCNR_SOT23-8 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. MXMIII Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 26 of 61 5 4 3 2 1 DP Redriver D VGA_DPC_P0 VGA_DPC_N0 VGA_DPC_P1 VGA_DPC_N1 VGA_DPC_P2 VGA_DPC_N2 VGA_DPC_P3 VGA_DPC_N3 VGA_DPC_P0 VGA_DPC_N0 VGA_DPC_P1 VGA_DPC_N1 VGA_DPC_P2 VGA_DPC_N2 VGA_DPC_P3 VGA_DPC_N3 CV13 CV15 CV17 CV19 CV21 CV23 CV25 CV27 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D CPU_MXM_MDP_P0_R CPU_MXM_MDP_N0_R CPU_MXM_MDP_P1_R CPU_MXM_MDP_N1_R CPU_MXM_MDP_P2_R CPU_MXM_MDP_N2_R CPU_MXM_MDP_P3_R CPU_MXM_MDP_N3_R 38 39 41 42 44 45 47 48 IN0p IN0n IN1p IN1n IN2p IN2n IN3p IN3n VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 UV6 <29> <29> <29> <29> <29> <29> <29> <29> 1 6 12 25 32 36 +3VS OUT0p OUT0n OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n 23 22 20 19 17 16 14 13 CPU_MXM_MDP_P0_C CPU_MXM_MDP_N0_C CPU_MXM_MDP_P1_C CPU_MXM_MDP_N1_C CPU_MXM_MDP_P2_C CPU_MXM_MDP_N2_C CPU_MXM_MDP_P3_C CPU_MXM_MDP_N3_C 40 DP_CFG1_INPUT CV14 CV16 CV18 CV20 CV22 CV24 CV26 CV28 2 2 2 2 2 2 2 2 CPU_MXM_MDP_P0 CPU_MXM_MDP_N0 CPU_MXM_MDP_P1 CPU_MXM_MDP_N1 CPU_MXM_MDP_P2 CPU_MXM_MDP_N2 CPU_MXM_MDP_P3 CPU_MXM_MDP_N3 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 1 1 1 1 1 1 1 1 D +3VS 3 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 10K_0402_1%~D 1 RV98 @ 1 RV99 @ 1 RV100 @ 1 RV101 1 RV102 2 2 2 2 2 DP_PEQ DP_CFG0 DP_PEQ DP_CFG1_INPUT DP_CFG0 DP_POWER_DOWN# DP_RST# 1 RV104 @ 1 RV105 @ 1 RV106 @ 1 RV108 @ 2 2 2 2 I2C_ADDR CFG1 SCL_CTL/PEQ SDA_CTL/CFG0 NC RST# DP_POWER_DOWN# 4.99K_0402_1% 1 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4 5 DP_PEQ DP_CFG1_INPUT DP_CFG0 DP_POWER_DOWN# 2 RV103 26 7 <16> DP_PCH_HPD MDP_CAB_DET 8 DP_PCH_HPD 9 VGA_DPC_AUXP/DDC 33 VGA_DPC_AUXN/DDC 34 0.1U_0402_10V6K~D VGA_DPC_AUXP/DDC CV31 2 1CPU_MXM_MDP_AUXP_L_C VGA_DPC_AUXN/DDC CV32 2 1 CPU_MXM_MDP_AUXN_L_C <29> VGA_DPC_AUXP/DDC <29> VGA_DPC_AUXN/DDC 30 29 PD# CAD_SNK REXT HPD_SINK 46 DP_RST# CV29 35 2 10 CAB_DET_SINK 11 DISP_HPD_SINK 28 27 CPU_MXM_MDP_AUXP CPU_MXM_MDP_AUXN 1 2.2U_0402_6.3V6M~D CAD_SRC HPD_SRC AUX_SNKP AUX_SNKN SCL_DDC SDA_DDC CEXT NC2 NC3 NC4 NC5 AUX_SRCP AUX_SRCN 2 CV30 GND1 GND2 GND3 EPAD 0.1U_0402_10V6K~D 2.2U_0402_6.3V6M~D 1 2 15 21 37 43 1 +3VS_DP 18 24 31 49 2 RV398 VGA_DPC_HPD 100K_0402_5%~D PS8330BQFN48GTR2-A0_QFN48_7X7 CPU_MXM_MDP_AUXN CPU_MXM_MDP_AUXP C 1A VCC 2A 1B 1OE# 2B 2OE# GND 8 3 6 4 2 2 1 1 2 1 2 5 1 7 2 1 2 1 2 1 2 Mini DP CONN JMDP1 0_0402_5% CBTD3306PW_TSSOP8 D <17> DP_CBL_DET QV9 BSS138_SOT23~D 2 G 3 B 2 UV8 VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC MDP_CAB_DET# 1 RV116 4.7K_0402_5%~D RV117 100K_0402_5%~D MDP_CAB_DET 1 RV115 4.7K_0402_5%~D +3VS @ CV41 0.1U_0402_16V4Z~D 1 0_0402_5%~D 2 RV655 +3VS +5VS 1 P 5 DP_PCH_HPD 3 G 2 C CV38 IN2 1 0_1206_5%~D CV37 O @ RV114 2 DGPU_PWROK <29,43> 0.1U_0402_25V6K~D 1.5A_6V_1206L150PR~D 1 22U_0805_6.3V6M~D CV36 .1U_0402_16V7K~D 4 IN1 2 CV35 VGA_DPC_HPD <29> VGA_DPC_HPD +3VS 1 100K_0402_5%~D 2 100K_0402_5%~D Need apply CIS part FV4 1 10U_0603_6.3V6M~D CV487 0.1U_0402_16V4Z~D 1 2 UV37 SN74AHC1G08DCKR_SC70-5 +3VS_DP Co-lay +3VS RV112 2 RV113 1 1 2 RV118 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DISP_HPD_SINK CPU_MXM_MDP_P0 CAB_DET_SINK CPU_MXM_MDP_N0 DISP_CEC S CPU_MXM_MDP_P1 CPU_MXM_MDP_P3 CPU_MXM_MDP_N1 CPU_MXM_MDP_N3 CPU_MXM_MDP_P2 CPU_MXM_MDP_AUXP CPU_MXM_MDP_N2 CPU_MXM_MDP_AUXN +3VS_DP GND HPD LANE0_P CONFIG1 LANE0_N CONFIG2 GND GND LANE1_P LANE3_P LANE1_N LANE3_N GND GND LANE2_P AUX_CH_P LANE2_N AUX_CH_N GND DP_PWR B GND1 GND2 GND3 GND4 21 22 23 24 PS_613002-020121 CONN@ @ RV121 1 2 DISP_HPD_SINK 1M_0402_5%~D RV124 2 CAB_DET_SINK 1M_0402_5%~D 1 RV125 VGA_DPC_AUXP/DDC 1 1 A QV5A DMN66D0LDW-7_SOT363-6~D 2 DP_MXM_CARD_SEL <32,43> 1 3 1 2 RV127 100K_0402_5%~D 6 2 VGA_DPC_AUXN/DDC A DISP_CEC 2 5.1M_0402_5% RV126 100K_0402_5%~D DMN66D0LDW-7_SOT363-6~D QV5B 4 5 MXM_MFG_SEL GPU Source 0 NVDIA 1 ATI Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. Mini DP/Thunder Bolt power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 27 of 61 A B C D E CPU to EDP & LVDS MUX +3VS 1 1 50 49 CPU_EDP_P0_S CPU_EDP_N0_S OUT1_D1p OUT1_D1n 47 46 CPU_EDP_P1_S CPU_EDP_N1_S OUT1_D0p OUT1_D0n 6 7 IN_D0p IN_D0n OUT1_D2p OUT1_D2n 45 44 CPU_EDP_C_P1 CPU_EDP_C_N1 9 10 IN_D1p IN_D1n OUT1_D3p OUT1_D3n 42 41 CPU_EDP_C_P2 CPU_EDP_C_N2 12 13 IN_D2p IN_D2n 40 39 15 16 OUT2_D0p OUT2_D0n 8338_EDP_P0_S 8338_EDP_N0_S CPU_EDP_C_P3 CPU_EDP_C_N3 IN_D3p IN_D3n OUT2_D1p OUT2_D1n 37 36 8338_EDP_P1_S 8338_EDP_N1_S OUT2_D2p OUT2_D2n 35 34 8338_EDP_P2_S 8338_EDP_N2_S OUT2_D3p OUT2_D3n 32 31 8338_EDP_P3_S 8338_EDP_N3_S OUT1_AUXp_SCL OUT1_AUXn_SDA 26 27 CPU_EDP_AUX_C CPU_EDP_AUX#_C 28 29 8338_EDP_AUX 8338_EDP_AUX# 43 48 8338_CA_DET 2136_HPD# 33 38 8338_CA_DET 8338_EDP_HPD# CPU_EDP_AUXP CPU_EDP_AUXN CFG_0 CFG_1 PC10 PC11 PC20 PC21 2 100K_0402_5% 2 100K_0402_5% 4 3 2 1 60 IN_CA_DET IN_HPD I2C_CTL_EN Pl1/SCL_CTL Pl0/SDA_CTL 22 23 24 25 IN_DDC_SCL IN_DDC_SDA IN_AUXp IN_AUXn 59 58 56 55 54 53 11 19 52 61 CFG0 CFG1 PC10 PC11 PC20 PC21 OUT2_AUXp_SCL OUT2_AUXn_SDA OUT1_CA_DET OUT1_HPD OUT2_CA_DET OUT2_HPD SW PEQ PD CEXT REXT GND GND GND PAD(GND) SW PEQ PWDN 18 8 14 17 20 CPU_EDP_P0_C CPU_EDP_N0_C 1 CV331 1 CV332 1 CV333 1 CV334 1 CV335 1 CV336 1 CV337 1 CV338 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 8338_EDP_P0 8338_EDP_N0 2136_HPD# CPU_EDP_P1_C <40> CPU_EDP_N1_C <40> LVDS Panel 8338_EDP_P0 <32> 8338_EDP_N0 <32> 8338_EDP_P1 8338_EDP_N1 8338_EDP_P1 <32> 8338_EDP_N1 <32> 8338_EDP_P2 8338_EDP_N2 eDP Panel 8338_EDP_P2 <32> 8338_EDP_N2 <32> 2 8338_EDP_P3 8338_EDP_N3 8338_EDP_P3 <32> 8338_EDP_N3 <32> <40> 8338_CA_DET 8338_EDP_HPD# <32> PAD~D T143 1 RV416 RV405 2 1M_0402_5%~D 1 CPU_EDP_HPD# @ RV503 1 2 100K_0402_5% +3VS D 2 G 1 2 CPU_EDP_P0_C <40> CPU_EDP_N0_C <40> CPU_EDP_P1_C CPU_EDP_N1_C 8338_EDP_AUX <32> 8338_EDP_AUX# <32> 10K_0402_5% 2 RV504 S CV317 QV54 2.2U_0402_6.3V6M PANEL_SW <19,34> SSM3K7002FU_SC70-3 SEL PANEL_SW L LVDS Panel H eDP Panel 2 4.99K_0402_1% 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K CPU_EDP_AUX_C <40> CPU_EDP_AUX#_C <40> @ PS8338BQFN60GTR-A0_QFN60_5X9 1 CV323 1 CV324 1 CV325 1 CV326 1 1 CV105 1 CV106 VDD33 VDD33 VDD33 VDD33 VDD33 CPU_EDP_C_P0 CPU_EDP_C_N0 HPD_GPU CPU_EDP_HPD# CTL_EN PL1 PL0 2 2 UV7 5 21 30 51 57 3 CPU_EDP_HPD# RV404 1 @ 2 1 RV403 1 1 0.1U_0402_16V4Z HPD_GPU 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D CV316 <8> CPU_EDP_AUX <8> CPU_EDP_AUX# CPU_EDP_AUX CPU_EDP_AUX# 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K <8> CPU_EDP_HPD# 2 1 0.1U_0402_16V4Z 2 CV315 <8> CPU_EDP_P3 <8> CPU_EDP_N3 1 0.1U_0402_16V4Z <8> CPU_EDP_P2 <8> CPU_EDP_N2 2 CV314 <8> CPU_EDP_P1 <8> CPU_EDP_N1 1 0.01U_0402_16V7K CPU_EDP_P0 1 CPU_EDP_N0 CV340 1 CV339 CPU_EDP_P1 1 CPU_EDP_N1 CV342 1 CV341 CPU_EDP_P2 1 CPU_EDP_N2 CV344 1 CV343 CPU_EDP_P3 1 CPU_EDP_N3 CV346 1 CV345 <8> CPU_EDP_P0 <8> CPU_EDP_N0 CPU CV313 2 0.01U_0402_16V7K CV312 1 3 CTL_EN PL1 @ 1 RV505 1 RV506 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS @ 1 RV507 1 RV508 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS Auto test enable; Internal pull down at ~150K Ohm, 3.3V I/O. L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable PC10 @ 1 RV512 @ 1 RV513 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS PC20 @ 1 RV514 @ 1 RV515 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS PC11 @ 1 RV516 @ 1 RV520 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS PC21 @ 1 RV521 @ 1 RV517 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS PEQ @ 1 RV518 1 RV519 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS Automatic EQ disable; Internal pull down at ~150K Ohm, 3.3V IO L: Automatic EQ enable (default) H: Automatic EQ disable PL0 CFG_0 CFG_1 4 @ 1 RV510 2 4.7K_0402_5% +3VS @ 1 RV509 @ 1 RV511 2 4.7K_0402_5% 2 4.7K_0402_5% +3VS @ 1 RV522 2 4.7K_0402_5% +3VS Chip operational mode configuration; Internal pull down at ~150K Ohm, 3.3V I/O. L: Control switching mode (default) H: Automatic switching mode Chip operational mode configuration; Internal pull down at ~150K Ohm, 3.3V I/O. L: Automatic power down enable (default) H: Automatic power down disable AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K Ohm, 3.3V I/O; L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150K Ohm, 3.3V I/O; L: default H: +20% M: -16.7% Programmable input equalization levels; Internal pull down at ~150K Ohm, 3.3V I/O. L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2 4 Compal Secret Data Security Classification Issued Date 3 2012/06/22 2013/06/21 Deciphered Date Title CPU to EDP & LVDS MUX THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 28 of 61 5 4 3 2 1 D D +3VS <31> 8338_EDP_AUX <31> 8338_EDP_AUX# MXM_DPB_AUXP/DDC_C 24 MXM_DPB_AUXN/DDC_C 23 20 19 CV75 CV76 CV77 CV78 CV308 CV307 CV305 CV306 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 2 1 CV79 1 CV80 8338_EDP_P0_C 8338_EDP_N0_C 8338_EDP_P1_C 8338_EDP_N1_C 8338_EDP_P2_C 8338_EDP_N2_C 8338_EDP_P3_C 8338_EDP_N3_C 7 8 10 11 13 14 15 16 8338_EDP_AUX_C 26 8338_EDP_AUX#_C25 22 21 CA_DET OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n SW_ML/I2C_ADDR CFG_HPD OUT_HPD REXT CEXT IN1_HPD IN2_HPD GND GND Epad PD 44 2 1M_0402_5%~D 1 CPU_MXM_EDP_A0P CPU_MXM_EDP_A0N CPU_MXM_EDP_A1P CPU_MXM_EDP_A1N CPU_MXM_EDP_A2P CPU_MXM_EDP_A2N CPU_MXM_EDP_A3P CPU_MXM_EDP_A3N 48 DGPU_SELECT# 46 43 CFG_HPD_1 LV_DP_HPD CPU_MXM_EDP_A0P CPU_MXM_EDP_A0N CPU_MXM_EDP_A1P CPU_MXM_EDP_A1N CPU_MXM_EDP_A2P CPU_MXM_EDP_A2N CPU_MXM_EDP_A3P CPU_MXM_EDP_A3N <33> <33> <33> <33> <33> <33> <33> <33> LV_DP_HPD <33> +3VS IN1 PS8838 1 IN2 MXM RV136 4.7K_0402_1%~D CFG_OUTPUT_1 1 0 1 1 Source 1 2 QV1A DMN66D0LDW-7_SOT363-6~D 2 DP_MXM_CARD_SEL <30,43> Chanel CFG_HPD_1 RV139 4.7K_0402_1%~D 2 @ 3 DMN66D0LDW-7_SOT363-6~D QV1B +3VS RV135 @ 4.7K_0402_1%~D 6 2 RV138 100K_0402_5%~D B C RV133 @ 4.7K_0402_1%~D CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis RV137 100K_0402_5%~D AUX_SEL/SEL1&2 DP_IN4_PEQ# INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ DGPU_SELECT# <17,36,42> 18 17 1 DP_IN3_PEQ# RV132 @ 4.7K_0402_1%~D 1 MXM_DPB_AUXN/DDC 2 2 RV406 42 41 39 38 36 35 33 32 45 12 57 40 RV131 @ 4.7K_0402_1%~D CFG_OUTPUT_1 2 PS8321QFN56GTR-A0_QFN56_7X7 MXM_DPB_AUXP/DDC +3VS RV130 @ 4.7K_0402_1%~D 34 RV134 4.99K_0402_1% IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA +3VS 37 CV81 2.2U_0402_6.3V6M~D 6 9 <29> MXM_DPB_HPD <31> 8338_EDP_HPD# CFG_OUTPUT CPU_MXM_EDP_AUXP <33> CPU_MXM_EDP_AUXN <33> 1 0.1U_0402_10V6K~D 1 0.1U_0402_10V6K~D 1 1 1 IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n CPU_MXM_EDP_AUXP_L CV63 2 CPU_MXM_EDP_AUXN_L CV64 2 1 CV73 2 CV74 2 52 53 55 56 1 2 4 5 I2C_CTL_EN 30 29 <21,36,42> 2 CV65 CV66 CV67 CV68 CV69 CV70 CV71 CV72 AC_AUXp AC_AUXn DGPU_EDIDSEL# CPU_MXM_EDP_AUXP CPU_MXM_EDP_AUXN 1 1 1 1 1 1 1 1 1 IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# 47 28 27 2 8338_EDP_P0 8338_EDP_N0 8338_EDP_P1 8338_EDP_N1 8338_EDP_P2 8338_EDP_N2 8338_EDP_P3 8338_EDP_N3 2 2 2 2 2 2 2 2 SW_AUX OUT_AUXp_SCL OUT_AUXn_SDA 1 <31> <31> <31> <31> <31> <31> <31> <31> MXM_C_TX0P MXM_C_TX0N MXM_C_TX1P MXM_C_TX1N MXM_C_TX2P MXM_C_TX2N MXM_C_TX3P MXM_C_TX3N 49 50 3 51 VDD VDD B 1 PS8338 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DP_IN4_AEQ# INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization RV140 4.7K_0402_1%~D 2 <29> MXM_DPB_AUXP/DDC <29> MXM_DPB_AUXN/DDC 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DP_IN3_AEQ# 1 4.7K_0402_1%~D 1 C MXM_TX0P MXM_TX0N MXM_TX1P MXM_TX1N MXM_TX2P MXM_TX2N MXM_TX3P MXM_TX3N 1 4.7K_0402_1%~D 2 2 <29> <29> <29> <29> <29> <29> <29> <29> 2 RV129 2 54 31 DP_IN3_PEQ# DP_IN4_PEQ# DP_IN3_AEQ# DP_IN4_AEQ# MXM RV128 UV9 1 2 2 2 1 CV62 0.1U_0402_16V4Z~D CV61 0.1U_0402_16V4Z~D 1 +3VS CPU & MXM SW for EDP 5 MXM_MFG_SEL GPU Source CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap 4 0 NVDIA 1 ATI A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. eDP SW-CPU & MXM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 29 of 61 2 D 80 mil 4 DP_IN6_AEQ# G 4028 PWR_SRC_ON 1 2 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D <38> 4028_EDP_AUXP <38> 4028_EDP_AUXN UV10 54 31 <43> LCD_BKL_EN FDC654P: P CHANNAL Panel backlight power control by EC 1 1 EDP_A0P_CONN EDP_A0N_CONN 1 RV162 2 RV163 EDP_A3P_CONN EDP_A3N_CONN IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n 2 CV974028_EDP_AUXP_C 24 2 CV994028_EDP_AUXN_C 23 20 19 CFG_OUTPUT CA_DET OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA 7 8 10 11 13 14 15 16 CPU_MXM_EDP_AUXP CPU_MXM_EDP_AUXN 2 CV108 EDP_HPD 0.1U_0402_16V4Z~D DISPOFF# 1 0.1U_0402_16V4Z~D IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n 26 25 22 21 CFG_HPD OUT_HPD IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA 1 6 9 <38> DP_4028_HPD <32> LV_DP_HPD SW_ML/I2C_ADDR REXT CEXT GND GND Epad PD IN1_HPD IN2_HPD 30 29 EDP_AUX+ EDP_AUXEDP_AUX+_C EDP_AUX-_C CV91 1 CV92 1 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D 37 C 34 CFG_OUTPUT_2 44 EDP_CAB_DET#_R 42 41 39 38 36 35 33 32 EDP_A0P_L EDP_A0N_L EDP_A1P_L EDP_A1N_L EDP_A2P_L EDP_A2N_L EDP_A3P_L EDP_A3N_L 48 HDMI_IN_SELECT# 46 43 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 EDP_A0P EDP_A0N EDP_A1P EDP_A1N EDP_A2P EDP_A2N EDP_A3P EDP_A3N CV95 CV96 CV98 CV100 CV101 CV102 CV103 CV104 CFG_HPD_2 EDP_HPD AUX_SEL/SEL1&2 18 17 45 12 57 40 1 2 Close to JEDP1 <42,43> PS8321QFN56GTR-A0_QFN56_7X7 Chanel 0 A 1 B Source 4028 CPU/MXM DV3 2 USB20_N11_CONN 3 EDP_HPD LCD_TEST LCD_TEST 6 V I/O DMIC0_CONN RV164 1 RV165 1 Ground V BUS 5 V I/O 4 V I/O DMIC_CLK_CONN <42,45> DMIC0 DMIC0_CONN 2 @ CV111 10P_0402_50V8J~D EDP_A0N 4 1 CAM_DET# DISPOFF# RV168 @ EDP_A3P_CONN 2 EDP_A3N_CONN EDP_A1N @ RV171 1 +EDPVDD +3VS_CAM <20> USB20_N11 1 2 CV115 USB20_P11 USB20_N11 1 4 3 1 2 4 RV173 2 4 3 RV174 1 3 @ 1 USB20_P11_CONN 2 @ 2 0_0402_5%~D 2 0_0402_5%~D EDP_AUX+ 4 3 EDP_AUX+_CONN EDP_AUX- 1 2 EDP_AUX-_CONN EDP_A1P_CONN EDP_A1N_CONN 2 0_0402_5%~D 1 @ 1 2 0_0402_5%~D LV7 LV9 2 3 1 DLW21SN670HQ2L_4P~D RV172 @ 1 2 0_0402_5%~D DLW21SN670HQ2L_4P~D <20> USB20_P11 0.1U_0402_16V4Z~D 4 EDP_A3N 2 0_0402_5%~D LV8 EDP_A1P +3VS 2 @ CV113 @ 120P_0402_50VNPO~D +3VS_CAM +INVPWR_B+ EDP_A3P CV112 10P_0402_50V8J~D 2 Reserve 1 2 EDP_A0N_CONN RV169 1 RV170 1 <42> @ 1 DMIC_CLK_CONN 2 1 1 BLM18BB221SN1D_2P~D INV_PWM 1 CV114 EDP_A0P_CONN RV167 2 +EDPVDD 3 DLW21SN670HQ2L_4P~D LV5 LV6 1 2 BLM18BB221SN1D_2P~D <18,42> <42> B 2 0_0402_5%~D DLW21SN670HQ2L_4P~D 2 1 EDP_CAB_DET# <21> CAM_DET# DISPOFF# LV3 EDP_A0P 1 @ RV166 10K_0402_5%~D <42,45> DMIC_CLK EDP_CAB_DET# @ 2 0_0402_5%~D LV2 BLM18BB221SN1D_2P~D DMIC_CLK_CONN DMIC0_CONN @ +5VS LV4 IP4223CZ6_SO6~D <42,43>+3VS USB20_N11_CONN USB20_P11_CONN V I/O 1 USB20_P11_CONN 1 EDP_AUX+_CONN EDP_AUX-_CONN 1 I-PEX_20505-044E-011G~D CONN@ @ 1 RV160 EDP_A2P_CONN EDP_A2N_CONN CV107 2 RV159 EDP_A1P_CONN EDP_A1N_CONN I2C_CTL_EN 52 53 55 56 1 2 4 5 CPU_MXM_EDP_A0P CPU_MXM_EDP_A0N CPU_MXM_EDP_A1P CPU_MXM_EDP_A1N CPU_MXM_EDP_A2P CPU_MXM_EDP_A2N CPU_MXM_EDP_A3P CPU_MXM_EDP_A3N CPU_MXM_EDP_A0P CPU_MXM_EDP_A0N CPU_MXM_EDP_A1P CPU_MXM_EDP_A1N CPU_MXM_EDP_A2P CPU_MXM_EDP_A2N CPU_MXM_EDP_A3P CPU_MXM_EDP_A3N <32> CPU_MXM_EDP_AUXP <32> CPU_MXM_EDP_AUXN 2 EDP_AUX100K_0402_5%~D 2 EDP_HPD 100K_0402_5%~D 2 EDP_AUX+ 100K_0402_5%~D 1 EDP_CAB_DET#_R 1M_0402_5%~D 1 2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AC_AUXp AC_AUXn HDMI_IN_SELECT# RV161 4.99K_0402_1% CONNTST GND LANE1_N LANE1_P GND LANE0_N LANE0_P GND AUX_CH_P AUX_CH_N GND LCD_VCC LCD_VCC LCD_VCC TEST GND HPD BL_GND BL_GND BL_PWR BL_PWR BL_PWR BL_PWR BL_GND BL_GND BL_PWM SMBUS_CLK SMBUS_DATA ALS_VCC ALS_INT# GND CAM_MIC_CBL_DET# USB+ USBUSB_VCC MIC_CLK MIC_GND MIC_DAT GND PWR_LED BATT2_LED BATT1_LED GND CONNTST IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# 47 28 27 CV110 2.2U_0402_6.3V6M~D B MGND1 MGND2 MGND3 MGND4 MGND5 MGND6 MGND7 MGND8 MGND9 MGND10 MGND11 MGND12 MGND13 SW_AUX OUT_AUXp_SCL OUT_AUXn_SDA 49 50 3 51 +3VS 45 46 47 48 49 50 51 52 53 54 55 56 57 VDD VDD S 2 G <32> <32> <32> <32> <32> <32> <32> <32> CPU/MXM JEDP1 1 1 CPU/GPU & 4028 SW for DPB 4028_EDP_L0P 4028_EDP_L0N 4028_EDP_L1P 4028_EDP_L1N 4028_EDP_L2P 4028_EDP_L2N 4028_EDP_L3P 4028_EDP_L3N 4028_EDP_L0P 4028_EDP_L0N 4028_EDP_L1P 4028_EDP_L1N 4028_EDP_L2P 4028_EDP_L2N 4028_EDP_L3P 4028_EDP_L3N 3 D 2 1 47K_0402_5%~D 1 2 CV93 0.1U_0603_50V4Z~D 2 2 +INVPWR_B+ 80 mil <38> <38> <38> <38> <38> <38> <38> <38> 3 1 RV157 100K_0402_5%~D 1 RV158 2 +INVPWR_B+ QV12 SSM3K7002FU_SC70-3~D @ LV1 1 2 FBMA-L11-201209-221LMA30T_0805 1 DP_IN5_PEQ# DP_IN6_PEQ# DP_IN5_AEQ# DP_IN6_AEQ# 1 Inverter power B+ 80 mil 6 5 2 1 S CV94 1000P_0402_50V7K~D 2 DP_IN5_AEQ# 1 4.7K_0402_1%~D INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization C 1 1 4.7K_0402_1%~D 2 QV11 FDC654P-G_SSOT-6~D B+ Back light power 2 @ RV155 1 RV156 @ @ RV153 2 2 CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis +3VS QV4B DMN66D0LDW-7_SOT363-6~D 5 INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ +3VS 4 0_0402_5%~D 1 1 3 2 1 1 RV154 2D CFG_OUTPUT_2 RV148 4.7K_0402_1%~D CV90 0.1U_0402_16V4Z~D 2 1 RV151 220K_0402_1% CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap DP_IN6_PEQ# RV147 @ 4.7K_0402_1%~D CV89 0.1U_0402_16V4Z~D <42,43> EC_ENVDD 0_0402_5%~D 1 RV152 200K_0402_5% <34,41,42> LCDVDD_ON 2 DP_IN5_PEQ# RV144 @ 4.7K_0402_1%~D 2 1 1 2 RV143 @ 4.7K_0402_1%~D RV146 @ 4.7K_0402_1%~D RV145 @ 4.7K_0402_1%~D CV88 0.1U_0603_25V7K~D QV4A DMN66D0LDW-7_SOT363-6~D 2 Close to JEDP1 CFG_HPD_2 2 1 4 1 2 2 6 2 1 1 2 3 CV87 4.7U_0805_10V4Z~D 2 CV86 4.7U_0805_10V4Z~D 1 RV150 47K_0402_5%~D 2 RV149 100_0402_5%~D 1 CV85 0.1U_0402_16V4Z~D 2 CV84 0.1U_0402_16V4Z~D 1 CV83 10U_0805_10V4Z~D 2 CV82 0.1U_0402_16V4Z~D 1 8 7 6 5 RV142 @ 4.7K_0402_1%~D RV141 4.7K_0402_1%~D 1 +5VS QV10 FDS4435BZ_SO8~D 2 +EDPVDD 1 +INVPWR_B+ +3VS 1 +EDPVDD +3VS 2 +EDPVDD W=60mils D +3VS 1 +3VS eDP POWER 1 2 3 2 4 2 5 @ 2 0_0402_5%~D 2 0_0402_5%~D USB20_N11_CONN LV10 DLW21SN900SQ2L_0805_4P~D @ 2 0_0402_5%~D RV175 1 EDP_A2P 4 3 EDP_A2P_CONN EDP_A2N 1 2 EDP_A2N_CONN 0.1U_0402_16V4Z~D DLW21SN670HQ2L_4P~D CV116 0.1U_0603_50V4Z~D RV176 1 @ 2 0_0402_5%~D A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. eDP SW-eDP CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 30 of 61 5 4 3 2 1 STDP6038 to EDP & LVDS MUX D D UV31 SLE1 2 1 <42> LVDS_TXOUT0<42> LVDS_TXOUT0+ <38> EDP_TXOUT0<38> EDP_TXOUT0+ <42> LVDS_TXOUT1<42> LVDS_TXOUT1+ <38> EDP_TXOUT1<38> EDP_TXOUT1+ <42> LVDS_TXOUT2<42> LVDS_TXOUT2+ <38> EDP_TXOUT2<38> EDP_TXOUT2+ <42> LVDS_TXCLK<42> LVDS_TXCLK+ <38> EDP_TXCLK<38> EDP_TXCLK+ C LVDS PANEL eDP PANEL Output 0B1 1B1 80 79 0B2 1B2 78 77 2B1 3B1 76 75 2B2 3B2 73 72 4B1 5B1 71 70 4B2 5B2 68 67 6B1 7B1 66 65 6B2 7B2 64 63 8B1 9B1 62 61 8B2 9B2 <42> LVDS_TZOUT0<42> LVDS_TZOUT0+ 58 57 <38> EDP_TZOUT0<38> EDP_TZOUT0+ <42> LVDS_TZOUT1<42> LVDS_TZOUT1+ 56 55 <38> EDP_TZOUT1<38> EDP_TZOUT1+ 54 53 51 50 <42> LVDS_TZOUT2<42> LVDS_TZOUT2+ 49 48 <38> EDP_TZOUT2<38> EDP_TZOUT2+ 46 45 <42> LVDS_TZCLK<42> LVDS_TZCLK+ 44 43 <38> EDP_TZCLK<38> EDP_TZCLK+ B 42 41 40 39 PANEL_SW PANEL_SW <19,31> A0 A1 5 6 A2 A3 8 9 A4 A5 11 12 LVDS_6038_TXOUT2- <37> LVDS_6038_TXOUT2+ <37> A6 A7 14 15 LVDS_6038_TXCLK- <37> LVDS_6038_TXCLK+ <37> A8 A9 17 18 LVDS_6038_TXOUT0- <37> LVDS_6038_TXOUT0+ <37> LVDS_6038_TXOUT1- <37> LVDS_6038_TXOUT1+ <37> C Input SEL2 60 59 16 10B1 11B1 A10 A11 34 PANEL_SW 23 24 LVDS_6038_TZOUT0- <37> LVDS_6038_TZOUT0+ <37> 10B2 11B2 12B1 13B1 A12 A13 26 27 LVDS_6038_TZOUT1- <37> LVDS_6038_TZOUT1+ <37> 12B2 13B2 14B1 15B1 A14 A15 29 30 LVDS_6038_TZOUT2- <37> LVDS_6038_TZOUT2+ <37> 32 33 LVDS_6038_TZCLK- <37> LVDS_6038_TZCLK+ <37> 14B2 15B2 16B1 17B1 A16 A17 16B2 17B2 18B1 19B1 A18 A19 B 35 36 +3VS 18B2 19B2 2 D S 3 1 QV29 SSM3K7002F_SC59-3~D GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 1 2 1 2 1 2 CV309 4.7U_0603_6.3V6K~D G RV397 100K_0402_5%~D 2 3 13 20 21 31 38 52 74 25 7 CV310 0.1U_0402_16V4Z~D <33,41,42> LCDVDD_ON CV311 0.1U_0402_16V4Z~D 1 +3VS PI3LVD1012BE_BQSOP80 Y PANEL_SW L LVDS H eDP A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title STDP6038 to EDP & LVDS MUX THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 31 of 61 A B C D E 1 1 +5VALW QV13 SI3456DDV-T1-GE3_TSOP6~D 43 +1.5VS STDP6038 <43> HDMI_OUT_EN CPU/MXM <43,56> PCH_PWR_EN +1.5VS 39 41 21 19 17 13 10 5 1 1 2 1 2 1 2 0_0402_5%~D 1 D 2 PCH_PWR_EN 2 G QV14 SSM3K7002FU_SC70-3~D S 2 0_0402_5%~D LV11 DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD2+_R 2 HDMI_IN_OUT_TXD2+ 2 1 1 3 3 2 +HDMI_5V_OUT @ RV182 1 OUTPUT L A H 2 0_0402_5%~D LV12 DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD1-_R HDMI_IN_OUT_TXD13 3 4 4 HDMI_IN_OUT_TXD1+_R HDMI_IN_OUT_SDATA HDMI_IN_OUT_SCLK HDMI_IN_OUT_HPD HDMI_IN_OUT_DDC 4 7 9 12 HDMI_SW 15 1 8 1A 2A 3A 4A OE# S GND Vcc 16 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 2 3 5 6 11 10 14 13 DVI_SDATA HDMI_DAT DVI_SCLK HDMI_CLK HDMI_SINK_HPD_R HDMI_IN_HPD_R DVI_SDATA <36> HDMI_DAT <37> DVI_SCLK <36> HDMI_CLK <37> HDMI_SINK_HPD_R <36> HDMI_IN_HPD_R <37> HDMI_IN_DET# HDMI_IN_DET# <37> 2 1 2 CV127 0.1U_0402_16V4Z~D 1 UV12 JHDMI1 HDMI_IN_OUT_HPD HDMI_IN_OUT_TXD1+ 1 1 HDMI_IN_OUT_DDC HDMI_IN_OUT_SDATA HDMI_IN_OUT_SCLK 2 0_0402_5%~D HDMI_UART_TX 2 0_0402_5%~D HDMI_UART_RX HDMI_IN_OUT_TXC- 2 @ RV183 CV126 0.1U_0402_16V4Z~D +5VS 2 1 +5VS B 2 0_0402_5%~D <37> UART_TX_6038 <37> UART_RX_6038 RV184 1 RV185 1 @ RV186 1 HDMI_IN_OUT_TXD0+_R HDMI_IN_OUT_TXD0-_R 2 0_0402_5%~D LV13 DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD0+ 2 2 1 1 3 3 4 1 4 HDMI_IN_OUT_TXC+ HDMI_IN_OUT_TXD0HDMI_IN_OUT_TXD0+ HDMI_IN_OUT_TXD1- HDMI_IN_OUT_TXD0HDMI_IN_OUT_TXD1+ HDMI_IN_OUT_TXD2- 2 @ RV187 2 HDMI Input/Output Connector 0_0402_5%~D TS3DV421RUAR_WQFN42_9X3P5 SEL @ HDMI_IN_OUT_TXD2- 4 4 1 @ RV181 D G 3 RV178 1 2 RV177 102K_0402_1% @ RV180 1 HDMI_IN_OUT_TXD2-_R 1 2 1 HDMI_OUT_TXC- <36> HDMI_OUT_TXC+ <36> HDMI_OUT_TXD0- <36> HDMI_OUT_TXD0+ <36> HDMI_OUT_TXD1- <36> HDMI_OUT_TXD1+ <36> HDMI_OUT_TXD2- <36> HDMI_OUT_TXD2+ <36> 2 3 HDMI_OUT_TXCHDMI_OUT_TXC+ HDMI_OUT_TXD0HDMI_OUT_TXD0+ HDMI_OUT_TXD1HDMI_OUT_TXD1+ HDMI_OUT_TXD2HDMI_OUT_TXD2+ <37> <37> <37> <37> <37> <37> <37> <37> RV179 0_0402_5%~D 9 31 32 33 34 35 36 37 38 HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ CV125 0.1U_0402_16V4Z~D <43> HDMI_SW HDMI_SW HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ CV124 10U_1206_16V4Z 2 ATMDSCLKATMDSCLK+ ATMDS0TMDSCLKATMDS0+ TMDSCLK+ ATMDS1TMDS0ATMDS1+ TMDS0+ ATMDS2TMDS1ATMDS2+ TMDS1+ TMDS2TMDS2+ VSS VSS VSS VSS SEL VSS VSS VSS GND_PAD VSS VSS 1 22 23 24 25 26 27 28 29 CV123 0.1U_0402_16V4Z~D 15 14 12 11 7 6 4 3 BTMDSCLKBTMDSCLK+ BMTDS0BTMDS0+ BTMDS1BMTDS1+ BTMDS2BTMDS2+ CV122 0.1U_0603_50V7K~D HDMI_IN_OUT_TXC-_R HDMI_IN_OUT_TXC+_R HDMI_IN_OUT_TXD0-_R HDMI_IN_OUT_TXD0+_R HDMI_IN_OUT_TXD1-_R HDMI_IN_OUT_TXD1+_R HDMI_IN_OUT_TXD2-_R HDMI_IN_OUT_TXD2+_R HDMI CONN VDD VDD VDD VDD VDD VDD VDD VDD +HDMI_5V_OUT 4 0_0402_5%~D HDMI_IN_OUT_TXD2+ @ RV188 1 CV118 1U_0402_6.3V6K~D 2 42 40 30 20 18 16 8 2 CV117 10U_0603_6.3V6M~D 2 1 CV121 0.1U_0402_16V4Z~D 1 CV120 10U_1206_16V4Z 2 CV119 0.1U_0402_16V4Z~D 1 6 5 2 1 UV11 S +3.3VS 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 0_0402_5%~D HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 SUYIN_100042GR019M23UZL CONN@ LV14 HDMI_IN_OUT_TXC-_R 3 SN74CBT3257CPWR_TSSOP16~D 3 OUTPUT L B1 H B2 4 HDMI_IN_OUT_TXC3 HDMI_IN_OUT_TXC+_R SEL 3 4 HDMI_IN_OUT_TXC+ 2 1 1 DLW21SN900HQ2L_0805_4P~D 1 2 @ RV189 0_0402_5%~D 46@ 2 RO0000002HM Reserve for EMI please close to JHDMI2 1 RV120 4.7K_0402_5%~D 2 +5VS <43> HDMI_IN_OUT_DDC ROYALTY HDMI W/LOGO Part Number HDMI_IN_OUT_TXC- CV349 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXC+ CV350 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD0- CV351 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD0+ CV352 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD1- CV353 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD1+ CV354 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD2- CV355 1 2 3.3P_0402_50V8C~D HDMI_IN_OUT_TXD2+ CV356 1 2 3.3P_0402_50V8C~D Description HDMI W/Logo:RO0000002HM 20120531 EMI ADD HDMI_IN_OUT_DDC HDMI_IN_OUT_HPD RV119 100K_0402_5%~D 2 1 <43> HDMI_IN_OUT_HPD 4 4 Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. HDMI In/Out SW/Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 32 of 61 5 4 3 2 1 +3VS 1 SSM3K7002F_SC59-3~D 1 QV17 SSM3K7002F_SC59-3~D 2 G S UV13 HDMI_TXD2+ HDMI_TXD2HDMI_TXD1+ HDMI_TXD1HDMI_TXD0+ HDMI_TXD0HDMI_TXC+ HDMI_TXC- 3 +5VS DGPU_HPD_INT# Close to U3 VCC pins 2 +3VS HDMI_SINK_HPD_R <35> HDMI_SINK_HPD_R +3VS +3VS RV203 1 VDD VDD 6 31 GPU_HDMI_TXD2-_C GPU_HDMI_TXD2+_C GPU_HDMI_TXD1-_C GPU_HDMI_TXD1+_C GPU_HDMI_TXD0-_C GPU_HDMI_TXD0+_C GPU_HDMI_TXC-_C GPU_HDMI_TXC+_C PWDN_ASQ 44 45 47 48 1 2 4 5 IN1_D1n IN1_D1p IN1_D2n IN1_D2p IN1_D3n IN1_D3p IN1_D4n IN1_D4p CFG_HPD DDCBUF PRE_EMI RTERM 25 HDMI_PWDN 28 HDMI_CFG_HPD 40 34 7 HDMI_DDCBUF HDMI_OE# 25 8 9 HDMI_CFG1 HDMI_CFG0 RV204 @ 4.7K_0402_5%~D 1 2 RV399 4.7K_0402_5%~D @ 499_0402_1%~D 34 35 HDMI_PC0 HDMI_PC1 3 4 HDMI_PC2 1 1 RV205 2 2.2U_0402_6.3V6M~D2 6 CV144 10 1 CPU_HDMI_N2_C CPU_HDMI_P2_C CPU_HDMI_N1_C CPU_HDMI_P1_C CPU_HDMI_N0_C CPU_HDMI_P0_C CPU_HDMI_N3_C CPU_HDMI_P3_C <29> VGA_HDMI_DET <17> PCH_HDMI_HPD <29> GPU_HDMI_SCLK <29> GPU_HDMI_SDATA <17> PCH_DPB_HDMI_CLK <17> PCH_DPB_HDMI_DAT GPU_HDMI_SCLK GPU_HDMI_SDATA PCH_DPB_HDMI_CLK PCH_DPB_HDMI_DAT +3VS 2.2K_0402_5%~D 2 PCH_DPB_HDMI_DAT 1 RV207 2.2K_0402_5%~D 2 PCH_DPB_HDMI_CLK 1 RV210 8 9 11 12 13 14 16 17 IN2_D1n IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p 46 10 41 42 19 20 DGPU_EDIDSEL#_R DGPU_SEL# 22 21 HDMI_IN1_PEQ HDMI_IN2_PEQ 3 15 +3VS OUT_HPD OUT_SCL OUT_SDA HDMI_SW_DETECT HDMI_SW_SCL HDMI_SW_SDA 39 38 37 IN1_PEQ IN2_PEQ 1 18 43 49 NC/OE# REXT CEXT HDMI_CFG1 HDMI_CFG0 HDMI_PC0 HDMI_PC1 HDMI_PC2 HDMI_SW_SDA HDMI_SW_SCL 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 2 2 2 2 2 1 RV215 @ 1 RV217 @ 1 RV219 @ 1 RV221 @ 1 RV222 @ HDMI_CFG1 HDMI_CFG0 HDMI_PC0 HDMI_PC1 HDMI_PC2 B +HDMI_5V_OUT HDMI_SW_DET 0 1 Y IN1 IN2 MXM PCH +HDMI_5V_OUT 2 P G 3 1 5 DVI_SDATA DVI_SCLK 1 2 RV225 1 0_0402_5%~D 2 RV226 0_0402_5%~D 1 2 NC @ 1 @ 0_1206_5%~D 1 RV228 2 +3VS 1 2 DVI_SDATA DVI_SCLK <35> <35> CV159 1 PCH_GPIO35 2 UV16 SN74AHC1G08DCKR_SC70-5 P 5 A IN1 O 4 DGPU_SEL# IN2 G 1 <17,32,42> DGPU_SELECT# Compal Secret Data Security Classification DGPU_SELECT# @ CV156 3 2 0.01U_0402_16V7K~D A 2 @ DV6 DAN217T146_SC59-3 10P_0402_50V8J~D <39> @ DV5 DAN217T146_SC59-3 Place LC Filter closed to JHDMI CV157 1U_0603_10V4Z~D 2 CV158 1U_0603_10V6K~D 1 C PS121QFN48G_QFN48_7X7 1 RV206 @ 1 RV208 @ 1 RV209 1 RV211 @ 1 RV212 1 RV213 1 RV214 +HDMI_5V_OUT DV7 W=40mils BAT1000-7-F_SOT23-3~D FV5 3 2 1 +HDMI_5V 1 2 5A_125V_R451005.MRL~D HDMI_SW_SDA HDMI_SW_SCL 29 28 GND/PC2 @ CV155 +5VS HDMI_SINK_HPD 7 I2C_ADDR0/PC0 I2C_ADDR1/PC1 10P_0402_50V8J~D DGPU_EDIDSEL#_R @ SDAZ SCLZ SDA_CTL/CFG1 SCL_CTL/CFG0 2 2 2 2 2 2 2 RV224 DGPU_EDIDSEL#_R 1 RV227 2 HPD SDA SCL PS8271QFN48GTR-A1_QFN48_7X7 DVI_SDATA_R DVI_SCLK_R 0_0402_5%~D NC/DDCBUF_EN# 2 GND GND PAD IN2 UV15 SN74AHC1G08DCKR_SC70-5 DGPU_EDIDSEL# I2C_CTL_EN# 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 1.5K_0402_5% 4 O CONN CEXT REXT RV223 IN1 2 <21> PCH_GPIO35 HDMI_OUT_TXD2+ <35> HDMI_OUT_TXD2- <35> HDMI_OUT_TXD1+ <35> HDMI_OUT_TXD1- <35> HDMI_OUT_TXD0+ <35> HDMI_OUT_TXD0- <35> HDMI_OUT_TXC+ <35> HDMI_OUT_TXC- <35> PS121 CFG0/ CFG1 SCLZ/SDAZ output voltage select; CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V PS121 PC0/PC1/PC2 Inputs equalization control, default inputs equalization setting at 12 dB 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB 1.5K_0402_5% 1 <21,32,42> DGPU_EDIDSEL# D +3VS SW_DDC SW_MAIN 8/25 change RV53 from 430 to 499ohm CV154 2 1 0.01U_0402_16V7K~D 2 RV218 B 1 499_0402_1%~D GPU_HDMI_SCLK 1 RV220 CV153 1 RV216GPU_HDMI_SDATA 2.2K_0402_5%~D 2 2.2U_0603_10V7K~D 2.2K_0402_5%~D 2 HDMI_TXD2HDMI_TXD2+ HDMI_TXD1HDMI_TXD1+ HDMI_TXD0HDMI_TXD0+ HDMI_TXCHDMI_TXC+ 36 35 33 32 30 29 27 26 IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA 23 24 +3V_MXM OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p 2 3 .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D HDMI_OUT_TXD2+ HDMI_OUT_TXD2HDMI_OUT_TXD1+ HDMI_OUT_TXD1HDMI_OUT_TXD0+ HDMI_OUT_TXD0HDMI_OUT_TXC+ HDMI_OUT_TXC- 23 22 20 19 17 16 14 13 2 2 2 2 2 2 2 2 2 2 1 HPD_SINK 3 1 1 1 1 1 1 1 1 POW 2 CV145 CV146 CV147 CV148 CV149 CV150 CV151 CV152 1 CPU CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N3 CPU_HDMI_P3 CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N3 CPU_HDMI_P3 2 <8> <8> <8> <8> <8> <8> <8> <8> OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n OUT4p OUT4n 5 12 18 24 27 31 36 37 43 49 C 2 1 1 .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D 32 IN1p IN1n IN2p IN2n IN3p IN3n IN4p IN4n 1 1 1 1 1 1 1 1 1 2 CV136 2 CV137 2 CV138 2 CV139 2 CV140 2 CV141 2 CV142 2 CV143 2 1 MXM GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ 26 HDMI_DDCBUF DVI_SDATA_R DVI_SCLK_R +3VS GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ 30 2 4.7K_0402_5%~D UV14 PS121 When DDCBUF_EN# is HIGH, the DDC channel is disabled, SCL/SDA and SCLZ/SDAZ are disconnected <29> <29> <29> <29> <29> <29> <29> <29> 38 39 41 42 44 45 47 48 <21,39> DGPU_HPD_INT# PS8271 PEQ=L, Middle level receiving equalization selection PEQ=H, High level receiving equalization selection PEQ=M, Low level receiving equalization selection 2 +3VS D 11 15 21 33 40 46 2 1 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 3 1 1 HDMI_OE# GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 2 G S D 1 2 3 2 QV16 2 2 1 2 HDMI_IN1_PEQ 1 2 RV196 0_0402_5%~D 2 1 3 2 4.7K_0402_5%~D 2 2 4.7K_0402_5%~D RV202 1 E HDMI_SW_DETECT 1 @ RV201 1 HDMI_IN2_PEQ 1 1 2 4.7K_0402_5%~D 1 RV190 100K_0402_5%~D LV15 MBK1608221YZF_2P HDMI_SINK_HPD 1 2 CV131 0.01U_0402_16V7K~D RV199 1 HDMI_CFG_HPD @ RV193 200K_0402_5% 1 2 CV130 0.1U_0402_16V4Z~D 2 4.7K_0402_5%~D 2 B CV132 220P_0402_50V7K~D 2 4.7K_0402_5%~D RV197 1 C @QV15 MMST3904-7-F_SOT323-3~D DV4 @ BAV99-7-F_SOT23-3 2 4.7K_0402_5%~D @ RV195 1 +3VS HDMI_DDCBUF RV198 200K_0402_5% @ RV194 1 Close to UV2 VCC pins RV200 10K_0402_5%~D 2 4.7K_0402_5%~D CV135 10U_0603_6.3V6M~D 2 4.7K_0402_5%~D CV134 .1U_0402_16V7K~D RV191 1 @ RV192 1 +3VS +3VS +3VS HDMI_PWDN CV129 0.1U_0402_16V4Z~D 2 4.7K_0402_5%~D CV128 0.01U_0402_16V7K~D 2 4.7K_0402_5%~D @ RV401 1 CV133 .1U_0402_16V7K~D D @ RV402 1 0_0402_5%~D 1 RV229 DGPU_SEL# 2 DGPU_SEL# <39> Issued Date @ 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. HDMI SW-CPU & MXM/Re-driver THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 33 of 61 4 +1.2V_AVDD 1 1 1 2 1 7 ADJ 8 9 PGOOD GND GND 1 EN RT9025-25PSP_SO8 2 HDMI_SPI_CLK_R 1 2 6 VOUT 1 2 HDMI LVDS_6038_TZOUT0- <34> LVDS_6038_TZOUT0+ <34> LVDS_6038_TZOUT1- <34> LVDS_6038_TZOUT1+ <34> LVDS_6038_TZOUT2- <34> LVDS_6038_TZOUT2+ <34> LVDS_6038_TZCLK- <34> LVDS_6038_TZCLK+ <34> 3 2 HDMI_IN_BKL_EN HDMI_IN_ENVDD +HDMI_5V_OUT 1 1 HDMI_IN_BKL_EN <42> HDMI_IN_ENVDD <42> C 1 2 2 B 22_0402_5% RV268 E BS_OCM_BOOT_SEL HDMI_IN_AUD_CODEC RV270 1 2 0_0402_5%~D HDMI_IN_AUDIO_CODEC <45> HDMI_IN_PWM HDMI_IN_PWM <42> BS_I2C_DEV_ID2 BS_I2C_DEV_ID1 BS_OSC_SEL 1 2 BS_I2C_DEV_ID0 RV273 0_0402_5%~D DHMI_IN_NV_CLK_R DHMI_IN_NV_CLK 1 2 DHMI_IN_NV_CLK DHMI_IN_NV_DAT_R RV395 1 20_0402_5%~D DHMI_IN_NV_DAT DHMI_IN_NV_DAT RV396 0_0402_5%~D 1 2 BS_XTAL_TCLK_SEL RV274 0_0402_5%~D CV205 0.1U_0402_16V4Z~D 2 UV20 1 2 3 4 E0 E1 E2 VSS 8 7 6 5 VCC WC SCL SDA HDMI_IN_CAB_DET# 2KBit 2 RV282 4.7K_0402_5%~D 1 2 RV283 1K_0402_1%~D UART_RX_6038 HDMI_IN_HPD_R HDMI_TOGGLE <43> 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D HDMI_SPI_CS# HDMI_SPI_CLK HDMI_SPI_SO HDMI_SPI_SI HDMI_IN_HPD_R <35> 65 66 67 68 SPI_CSn / IRQ_IN / GPO_8 SPI_CLK / GPO_9(BS_INTERFACE_SEL1) SPI_DI / GPO_10(BS_INTERFACE_SEL0) SPI_DO / GPO_11(BS_UART_FUNCTION_SEL) 47 55 61 DPRX_VSSD DPRX_VSSA DPRX_VSSA 77 83 HDMI_VSSA HDMI_VSSA HDMI_IN_HPD 1 22_0402_5% VSSA_33 LVVSS LVVSS CRVSS CRVSS CRVSS CRVSS 2 2 RV294 B E 7 34 22 2 G S LV24 HDMI_IN_SW_HPD 2 1 MBK1608221YZF_2P HDMI_IN_HPD 1 BAV99-7-F_SOT23-3 DV10 @ 2 +HDMI_5V_OUT 115 107 69 37 A HDMI_IN_CAB_DET# ADC_VSSA ADC_VSSA ADC_VSSA ADC_VSSD <43> D QV19 SSM3K7002FU_SC70-3~D 3 I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) I2S_WS / GPO_14(BS_I2C_SRC_SEL) I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN) B 1HDMI_IN_CAB_DET# 33K_0402_5% 2 RV277 +HDMI_5V_OUT 1 <35> <35> +HDMI_5V_OUT 5 HDMI_CLK HDMI_DAT +3.3V_DVDD 2Kbit <42> <42> HDMI_PLUG_IN_CAB_DET 1 BS_INTERFACE_SEL1 RV295 1 BS_INTERFACE_SEL0 RV296 1 BS_UART_FUNCTION_SEL RV297 1 A 20_0402_5%~D BS_RESERVED_R 39 BS_SPI_R 40 BS_I2C_SRC_R 41 BS_I2C_ON_R 42 EDID_WP 2 22_0402_5% 2 100_0402_1%~D HDMI_CLK 2 100_0402_1%~D HDMI_DAT RV269 1 RV271 1 RV272 1 HDMI_SW_CLK HDMI_SW_DAT CAT24C02WI-GT3A_SO8 UART_TX_6038 <35> UART_RX_6038 <35> RV287 2 1 10K_0402_5%~D HDMI_PLUG_IN_CAB_DET RV290 2 1 10K_0402_5%~D RV292 2 1 10K_0402_5%~D 1 DV9 1SS355TE-17_SOD323-2 +5VS_HDMI_IN_EDID 1 3 @ RV293 1 1 2 2 C <45> I2S_DAT/SPDIF_IN DHMI_IN_NV_CLK_R DHMI_IN_NV_DAT_R 2 22_0402_5% 2 22_0402_5% +5VS 2 1 DV8 2 1 1SS355TE-17_SOD323-2 EDID_WP BS_EXTKEY_EN UART_TX_6038 UART_RX_6038 RV262 1 RV263 1 CAT24C16WI-GT3_SO8 +5VS 110 RV256 HDMI_SPI_CLK 2 RV257 HDMI_SPI_SI 2 2 LVDS_6038_TZOUT0LVDS_6038_TZOUT0+ LVDS_6038_TZOUT1LVDS_6038_TZOUT1+ LVDS_6038_TZOUT2LVDS_6038_TZOUT2+ LVDS_6038_TZCLKLVDS_6038_TZCLK+ GPIO_45 1 RV254 15_0402_5%~D 1 15_0402_5%~D 1 2 21 20 19 18 17 16 15 14 13 12 LBADC_IN4 / GPIO_35 LBADC_IN3 / GPIO_34 LBADC_IN2 / GPIO_33 / TTL_SYNC4 LBADC_IN1 / GPIO_32 / TTL_SYNC3 HDMI_IN_AUD_CODEC 2 1 GPIO_57 GPIO_56 GPIO_55 GPIO_54 GPIO_53 GPIO_52 GPIO_51 GPIO_50 GPIO_49 GPIO_48 103 104 101 102 2 10K_0402_5%~D 1 HDMI_RXCN HDMI_RXCP HDMI_RX0N HDMI_RX0P HDMI_RX1N HDMI_RX1P HDMI_RX2N HDMI_RX2P HDMI_REXT HDMI_HPD / GPIO_22 HDMI_CEC / GPIO_23 BS_OSC_SEL RV249 1 8 7 6 5 VCC WC SCL SDA 1 / / / / / / / / / / E0 E1 E2 VSS 1 TTL_D19 TTL_D18 TTL_D17 TTL_D16 TTL_D15 TTL_D14 TTL_D13 TTL_D12 TTL_D11 TTL_D10 VBUFC_RPLL 2 10K_0402_5%~D UV19 1 2 3 4 2 / / / / / / / / / / @ 1 E_CH0N_LV E_CH0P_LV E_CH1N_LV E_CH1P_LV E_CH2N_LV E_CH2P_LV E_CLKN_LV E_CLKP_LV E_CH3N_LV E_CH3P_LV 2 LVDS_6038_TXOUT0- <34> LVDS_6038_TXOUT0+ <34> LVDS_6038_TXOUT1- <34> LVDS_6038_TXOUT1+ <34> LVDS_6038_TXOUT2- <34> LVDS_6038_TXOUT2+ <34> LVDS_6038_TXCLK- <34> LVDS_6038_TXCLK+ <34> 119 118 117 BS_XTAL_TCLK_SEL RV248 1 CV208 220P_0402_50V7K~D 75 76 78 79 81 82 84 85 87 113 114 LVDS_6038_TXOUT0LVDS_6038_TXOUT0+ LVDS_6038_TXOUT1LVDS_6038_TXOUT1+ LVDS_6038_TXOUT2LVDS_6038_TXOUT2+ LVDS_6038_TXCLKLVDS_6038_TXCLK+ DPRX_AUXN DPRX_AUXP DPRX_ML_L0P DPRX_ML_L0N DPRX_ML_L1P DPRX_ML_L1N DPRX_ML_L2P DPRX_ML_L2N DPRX_ML_L3P TTL_CKOUT / GPIO16(BS_EXTKEY_EN) DPRX_ML_L3N UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) DPRX_REXT UART_RX / TTL_SYNC2 / GPO_6 DPRX_HPD_OUT / GPO_5 BS_INTERFACE_SEL0 2 10K_0402_5%~D RV285 100K_0402_5%~D 10_0402_5%~D HDMI_IN_CK-_R 10_0402_5%~D HDMI_IN_CK+_R 10_0402_5%~D HDMI_IN_D0-_R 10_0402_5%~D HDMI_IN_D0+_R 10_0402_5%~D HDMI_IN_D1-_R 10_0402_5%~D HDMI_IN_D1+_R 10_0402_5%~D HDMI_IN_D2-_R 10_0402_5%~D HDMI_IN_D2+_R 249_0402_1%~D HDMI_IN_SW_HPD 33 32 31 30 29 28 27 26 25 24 1 127 126 124 123 122 121 120 2 10K_0402_5%~D RV247 1 1 CV206 .1U_0402_16V7K~D 2 2 2 2 2 2 2 2 2 GPIO_67 GPIO_66 GPIO_65 GPIO_64 GPIO_63 GPIO_62 GPIO_61 GPIO_60 GPIO_59 GPIO_58 QV20 MMST3904-7-F_SOT323-3~D RV278 1 RV279 1 RV280 1 RV281 1 RV284 1 RV286 1 RV288 1 RV289 1 RV291 1 +3.3VS_AVDD / / / / / / / / / / CV207 0.1U_0402_16V4Z~D HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ 2 300_0402_1% TTL_D29 TTL_D28 TTL_D27 TTL_D26 TTL_D25 TTL_D24 TTL_D23 TTL_D22 TTL_D21 TTL_D20 GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL) STI_TM1 / PWM1 / TTL_D6 / GPO_1 GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) TTL_D1 / GPIO18 / M_I2C_SCL TTL_D0 / GPIO17 / M_I2C_SDA BS_INTERFACE_SEL1 RV246 1 2 1 RV276 GPIO_44 / S_I2C_SCL GPIO_43 / S_I2C_SDA 2 10K_0402_5%~D 16KBit NVRAM RV275 10K_0402_5%~D +1.2V_AVDD 48 49 53 54 56 57 59 60 62 63 51 43 / / / / / / / / / / PBIAS / TTL_D9 / GPO_4 PPOWER / TTL_D8 / GPO_3 BS_OCM_BOOT_SEL RV245 1 1 111 112 T60 @ T58 @ O_CH0N_LV O_CH0P_LV O_CH1N_LV O_CH1P_LV O_CH2N_LV O_CH2P_LV O_CLKN_LV O_CLKP_LV O_CH3N_LV O_CH3P_LV A_I2C_SDA A_I2C_SCL D1_I2C_SDA / GPIO_28 D1_I2C_SCL / GPIO_29 D2_I2C_SDA / GPIO_24 D2_I2C_SCL / GPIO_25 BS_EXTKEY_EN 2 10K_0402_5%~D 3 PAD~D PAD~D 2 4.7K_0402_5%~D RV410 VEDID_VDD_3V3 2 10K_0402_5%~D RV243 1 1 1 2 HDMI_IN_EN 71 72 73 74 44 45 6 1 1 4.7K_0402_5%~D RV409 70 RV242 1 D C 2 +3.3V_DVDD 0.1U_0402_16V4Z~D EC_HDMI_DAT EC_HDMI_CLK HDMI_SW_DAT HDMI_SW_CLK BS_I2C_ON_R RV267 4.7K_0402_1%~D 2 LVDS ADC_A_N ADC_A_P ADC_B_N ADC_B_P ADC_C_N ADC_C_P HSYNC_IN VSYNC_IN 2 10K_0402_5%~D 1 RV266 4.7K_0402_1%~D 1 RESETn STI_TM2 BS_I2C_SRC_R RV240 1 +3.3V_DVDD RV265 4.7K_0402_1%~D 0.1U_0402_16V4Z~D 92 0.1U_0402_16V4Z~D 93 0.1U_0402_16V4Z~D 95 0.1U_0402_16V4Z~D 96 0.1U_0402_16V4Z~D 98 0.1U_0402_16V4Z~D 99 0.1U_0402_16V4Z~D 105 0.1U_0402_16V4Z~D 106 BS_SPI_R 2 10K_0402_5%~D +3.3V_DVDD QV18 MMST3904-7-F_SOT323-3~D 2 2 2 2 2 2 2 2 BS_RESERVED_R 2 10K_0402_5%~D RV239 1 8 7 10K_0402_5%~D 2 HDMI_SPI_CLK_R 6 HDMI_SPI_SI_R 5 VCC RESET# C D 2 2 1 2 1 1 1 1 1 1 1 1 NC 2 10K_0402_5%~D RV238 1 RV260 4.7K_0402_1%~D CV195 CV196 CV198 CV199 CV200 CV201 CV202 CV203 1 4 125 RV237 1 2 +1.2V_AVDD RVDD_33 RVDD_33 RVDD_33 XTAL TCLK 2 10K_0402_5%~D BS_UART_FUNCTION_SEL RV259 4.7K_0402_1%~D 8 9 36 HDMI_RST# RV264 1 2 10K_0402_5%~D CV204 HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ VDDA_1V2 BS_I2C_DEV_ID0 RV235 1 MX25L2006EM1I-12G_SOP8 50 64 58 52 2 10K_0402_5%~D CV194 0.1U_0402_16V4Z~D RV261 CV197 2.2K_0402_5%~D 4700P_0402_25V7K~D XTAL TCLK +3.3V_DVDD <35> <35> <35> <35> <35> <35> <35> <35> DPRX_VDDA_1V2 DPRX_VDDA_1V2 DPRX_VDDA_1V2 S# Q W# VSS RV258 4.7K_0402_1%~D 38 109 128 HDMI_VDDA_3V3 HDMI_VDDA_3V3 ADC_AVDD_3V3 ADC_AVDD_3V3 88 BS_I2C_DEV_ID1 RV233 1 UV18 1 2 3 4 1 80 86 90 100 +3.3VS_AVDD +3.3V_DVDD B ADC_DVDD_1V2 DPRX_VDDD_1V2 +3.3V_DVDD @ AVDD_OUT_33 AVDD_OUT_33 XTAL 27MHZ_10PF_X3S027000BA1H-U~D <43> HDMI_IN_EN CVDD_12 CVDD_12 CVDD_12 CVDD_12 1 G1 11 23 +3.3V_AVDD_LVTX VDDA_3V3 RV252 15_0402_5%~D HDMI_SPI_CS# 2 HDMI_SPI_CS#_R 1 HDMI_SPI_SO HDMI_SPI_SO_R 1 2 RV253 1 15_0402_5%~D 2 +3.3V_DVDD RV255 10K_0402_5%~D +1.2V_DVDD BS_I2C_DEV_ID2 2 10K_0402_5%~D 2Mbit SPI ROM EC_HDMI_CLK <38> EC_HDMI_DAT <38> 116 108 46 35 3 C 3 G2 4 10 +3.3V_AVDD_RPLL 2 2 YV1 1 2 EC_HDMI_CLK EC_HDMI_DAT UV1 1 2 2 22_0402_5% 2 22_0402_5% 2 10K_0402_5%~D RV232 1 CV191 .1U_0402_16V7K~D 1 CV193 10P_0402_50V8J~D CV192 10P_0402_50V8J~D TCLK 1 RV250 1 RV251 1 <43> EC_SMB_CK2_R <43> EC_SMB_DA2_R +3.3V_AVDD_RPLL RV230 1 +3.3V_DVDD 2 1 2 1 5 NC VIN 2 2 1 2 2 1 VDD 1 @ RV244 CV190 15_0402_5%~D 15P_0402_50V8J~D 1 2 3 CV189 0.1U_0603_25V7K~D 1 2 CV188 0.1U_0603_25V7K~D 2 2 CV187 0.1U_0603_25V7K~D 1 2 CV186 0.1U_0603_25V7K~D 2 1 CV185 0.1U_0603_25V7K~D Close to respective power Pins 2 CV183 22U_0805_6.3VAM~D 1 AVDD_RPLL pin10 C610 0.1uF to AVSS_RPLL pin7 LV22 1 2 BLM18AG601SN1D_0603~D CV184 0.1U_0603_25V7K~D 1 +3.3V_AVDD_RPLL LV23 1 2 BLM18BD601SN1D_0603~D UV17 4 2 1 2 1 BLM18AG601SN1D_0603~D BLM18AG601SN1D_0603~D 2 RV234 0_0402_5%~D 2 1 +3.3VS_AVDD CV182 0.1U_0603_25V7K~D 1 2 CV181 22U_0805_6.3VAM~D 1 2 CV180 0.1U_0603_25V7K~D 2 CV179 0.1U_0603_25V7K~D CV178 0.1U_0603_25V7K~D 2 CV177 22U_0805_6.3VAM~D 1 +1.2V_DVDD 2 1 RV241 20K_0402_5%~D +1.2VS_HDMI CV176 10U_0805_4VAM~D +3.3V_DVDD LV21 1 2 BLM18BD601SN1D_0603~D +1.2VS_A LV20 CV173 22U_0805_6.3VAM~D 1 +1.2VS RV236 10K_0402_5%~D 1 1 2 100K_0402_5%~D CV175 .1U_0402_16V7K~D 1 2 +1.2VS_HDMI RV231 CV174 1U_0402_6.3V6K~D 1 2 +5VS LV19 CV169 0.1U_0603_25V7K~D 2 2 CV168 0.1U_0603_25V7K~D 1.2V TDC 0.52A Peak Current 0.73A OCP current 3.5A 2 CV167 0.1U_0603_25V7K~D 1 1 CV166 0.1U_0603_25V7K~D 1 2 +3.3V_DVDD For 4028 +3VS LV18 1 2 BLM18BD601SN1D_0603~D CV165 22U_0805_6.3VAM~D Can not place large capacitor to prevent pulse happened when LVDS 1 power switch off/on 2 CV172 0.1U_0603_25V7K~D 1 2 CV171 0.1U_0603_25V7K~D 1 2 CV170 0.1U_0603_25V7K~D 2 CV164 0.1U_0402_16V4Z~D 1 CV163 0.1U_0603_25V7K~D 2 CV162 0.1U_0603_25V7K~D +3VS 1 CV161 0.1U_0603_25V7K~D CV160 22U_0805_6.3VAM~D 2 2 LV17 1 2 BLM18BD601SN1D_0603~D 2 +1.2VS_HDMI 1 +3.3VS_AVDD LV16 1 2 BLM18BD601SN1D_0603~D 1 D +3.3V_AVDD_LVTX 2 2 +3.3VS_AVDD +3VS 3 @ 5 2 0_0402_5%~D HDMI_IN_DET# RV298 1 97 94 91 89 HDMI_IN_DET# <35> STDP6038-AC_PQFP128_20X14~D Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. HDMI to LVDS-STDP6038 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 34 of 61 3 2 +3VS +1.2VS_A UV2C @ 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 RV305 RV308 RV309 RV310 RV311 RV312 RV313 1 1 1 1 1 1 1 2 2 2 2 2 2 2 4.7K_0402_5%~D 3D_VIDEO 4.7K_0402_5%~D AUX_UART_TX 4.7K_0402_5%~D GPIO_3/BOOT6 4.7K_0402_5%~D I2C_SCL 4.7K_0402_5%~D I2C_SDA 4.7K_0402_5%~D EC_HDMI_DAT_R 4.7K_0402_5%~D EC_HDMI_CLK_R RV315 @ RV316 RV318 RV319 RV320 @ RV322 RV323 1 1 1 1 1 1 1 2 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D UART_TX AUX_UART_TX GPIO_0/BOOT3 GPIO_1/BOOT2 GPIO_2/BOOT5 GPIO_3/BOOT6 IRQ/BOOT7 2Mbit UV3 SPI_CSN_4028 SPI_DI_4028 1 2 3 4 S# Q W# VSS VCC RESET# C D E7 E8 K6 K9 8 7 6 5 <34> EDP_TZOUT2<34> EDP_TZOUT2+ <34> EDP_TZCLK<34> EDP_TZCLK+ N9 M9 EDP_TZOUT2EDP_TZOUT2+ M10 L10 EDP_TZCLKEDP_TZCLK+ N11 M11 P12 N12 P13 N13 M13 M14 L12 L13 K12 K11 J12 J13 H13 H14 G13 G14 O0_LVRX_CH1N_VIDIN21 O0_LVRX_CH1P_VIDIN20 O0_LVRX_CH6N_VIDIN24 O0_LVRX_CH6P_VIDIN25 L11 M12 <34> EDP_TXOUT1<34> EDP_TXOUT1+ O0_LVRX_CH2N_VIDIN19 O0_LVRX_CH2P_VIDIN18 <34> EDP_TXOUT2<34> EDP_TXOUT2+ O0_LVRX_CLKN_VIDIN17 O0_LVRX_CLKP_VIDIN16 <34> EDP_TXCLK<34> EDP_TXCLK+ O0_LVRX_CH3N_VIDIN15 O0_LVRX_CH3P_VIDIN14 O0_LVRX_CH4N_VIDIN3 O0_LVRX_CH4P_VIDIN2 O1_LVRX_CH0N_VIDIN23 O1_LVRX_CH0P_VIDIN22 O1_LVRX_CH1N_VIDIN21 O1_LVRX_CH1P_VIDIN20 O1_LVRX_CH2N_VIDIN19 O1_LVRX_CH2P_VIDIN18 O1_LVRX_CH4N_VIDIN3 O1_LVRX_CH4P_VIDIN2 P2 N2 EDP_TXOUT1EDP_TXOUT1+ P3 N3 EDP_TXOUT2EDP_TXOUT2+ N4 M4 EDP_TXCLKEDP_TXCLK+ M5 L5 N6 M6 P7 N7 G1 G2 H1 H2 J2 J3 K3 K4 O1_LVRX_CLKN_VIDIN17 O1_LVRX_CLKP_VIDIN16 O1_LVRX_CH3N_VIDIN15 O1_LVRX_CH3P_VIDIN14 EDP_TXOUT0EDP_TXOUT0+ O1_LVRX_CH5N_VIDIN_CLK O1_LVRX_CH5P_VIDIN_DE O1_LVRX_CH6N_VIDIN24 O1_LVRX_CH6P_VIDIN25 J10 H11 L2 L3 K10 J11 M1 M2 E0_LVRX_CH0N_VIDIN13 E0_LVRX_CH0P_VIDIN12 E0_LVRX_CH5N_VIDIN_VSYNC E0_LVRX_CH5P_VIDIN_HSYNC E0_LVRX_CH1N_VIDIN11 E0_LVRX_CH1P_VIDIN10 E0_LVRX_CH6N_VIDIN26 E0_LVRX_CH6P_VIDIN27 M7 L6 2 1 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 G11 PVDD21 G5 PVDD22 M3 L4 +1.2VS_A E0_LVRX_CH2N_VIDIN9 E0_LVRX_CH2P_VIDIN8 E0_LVRX_CLKN_VIDIN7 E0_LVRX_CLKP_VIDIN6 E0_LVRX_CH3N_VIDIN5 E0_LVRX_CH3P_VIDIN4 E0_LVRX_CH4N_VIDIN1 E0_LVRX_CH4P_VIDIN0 LVDS E1_LVRX_CH0N_VIDIN13 E1_LVRX_CH0P_VIDIN12 E1_LVRX_CH1N_VIDIN11 E1_LVRX_CH1P_VIDIN10 E1_LVRX_CH2N_VIDIN9 E1_LVRX_CH2P_VIDIN8 B11 C7 C8 D9 DPTX_VDDA_1V2 DPTX_VDDA_1V2 DPTX_VDDA_1V2 DPTX_VDDA_1V2 +AVDD_3V3 D6 D5 VDDA_3V3 VDD33_TX +VDD_RPLL_1V2 A3 DPTX_VSSA DPTX_VSSA DPTX_VSSA DPTX_VSSA VSS_RPLL VDD_RPLL VSSA_TX 1 C 20mils 1 2 A1 A14 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B D7 D8 E9 E10 A2 C5 +AVDD_LVRX_1V2 AVSS_LVRX_12 L7 E1_LVRX_CLKN_VIDIN7 E1_LVRX_CLKP_VIDIN6 E1_LVRX_CH5N_VIDIN_VSYNC E1_LVRX_CH5P_VIDIN_HSYNC E1_LVRX_CH4N_VIDIN1 E1_LVRX_CH4P_VIDIN0 E1_LVRX_CH6N_VIDIN26 E1_LVRX_CH6P_VIDIN27 J5 H4 J4 K5 K7 AVDD_LVRX_12 STDP4028-AB_LFBGA164 E1_LVRX_CH3N_VIDIN5 E1_LVRX_CH3P_VIDIN4 STDP4028-AB_LFBGA164 2 SPI_CLK_4028 SPI_DO_4028 PVDD1 PVDD1 PVDD1 PVDD1 PWR & GND B EDP_TZOUT1EDP_TZOUT1+ <34> EDP_TXOUT0<34> EDP_TXOUT0+ O0 & O1 LVDS Input <34> EDP_TZOUT1<34> EDP_TZOUT1+ M8 L9 1 UV2D UV2A O0_LVRX_CH5N_VIDIN_CLK O0_LVRX_CH5P_VIDIN_DE 2 MX25L2006EM1I-12G_SOP8 +1.2VS E0 & E1 LVDS Input UV2B O0_LVRX_CH0N_VIDIN23 O0_LVRX_CH0P_VIDIN22 1 +3VS 1 @ SYS, Audio & DPTX 1 2 2 +3VS P8 N8 2 CV227 0.1U_0603_25V7K~D 1 VEGA STDP4028 DPTx BootStraps EDP_TZOUT0EDP_TZOUT0+ 1 +1.2VS_A STDP4028-AB_LFBGA164 <34> EDP_TZOUT0<34> EDP_TZOUT0+ 2 RV307 10K_0402_5%~D TESTMODE1 2 CV226 0.1U_0603_25V7K~D GPIO_3/BOOT6 1 CV225 0.1U_0603_25V7K~D F11 1 CV244 0.1U_0402_16V4Z~D GPIO_3/BOOT6 2 CV241 0.1U_0603_25V7K~D G3 TESTMODE0 1 CV224 0.1U_0603_25V7K~D 1 RV321 2 F3 GPIO_1/BOOT2 G10 GPIO_2/BOOT5 2 CV240 0.1U_0603_25V7K~D 0_0402_5%~D 1 RV317 2 D4 2 CV239 0.1U_0603_25V7K~D GPIO_2/BOOT5 GPIO_0/BOOT3 1 AUX_UART_RX +3VS E5 2 CV223 22U_0805_6.3VAM~D GPIO_1/BOOT2 VBUFC_RPLL 1 CV215 0.1U_0603_25V7K~D C3 2 1 CV238 0.1U_0603_25V7K~D 1 RV314 2 1 2 CV222 0.1U_0603_25V7K~D IRQ/BOOT7/GPIO_12 2 1 D +AVDD_3V3 +1.2VS 1 +3VS 2 CV237 22U_0805_6.3VAM~D IR_IN/GPIO_6 F12 G12 D11 E11 B2 B3 2 2 1 CV220 22U_0805_6.3VAM~D D12 NC1 NC2 NC3 NC4 NC5 NC6 PWM0/GPIO_0/BOOT3 0_0402_5%~D E3 3D_VIDEO 1 2 CV236 0.1U_0603_25V7K~D IRQ/BOOT7 0_0402_5%~D 1 1 2 +AVDD_LVRX_1V2 LV28 2 1 BLM18AG601SN1D_0603~D C1 E4 1 RV306 10K_0402_5%~D G4 SPI_DI/HOST_D1/GPO_19 SPI_DO/HOST_D0/GPO_20 SPI_CLK/HOST_CLK/GPIO_18 SPI_CSn/HOST_CS/GPIO_17 +1.2VS_A 2 1 CV235 0.1U_0603_25V7K~D 1 D13 C14 E12 F10 UART_RX +5VS 2 SPI_DI_4028 SPI_DO_4028 SPI_CLK_4028 SPI_CSN_4028 2 2 2 +3VS LV27 2 1 BLM18AG601SN1D_0603~D CV234 22U_0805_6.3VAM~D CLK_OUT/GPIO_5/BOOT0 D2 F5 F4 D3 1 1 CV231 0.1U_0603_25V7K~D RESETn +5VS B12 AUX_UART_TX A12 AUX_UART_RX +VDD_RPLL_1V2 LV26 2 1 BLM18AG601SN1D_0603~D CV229 22U_0805_6.3VAM~D YV2 27MHZ_10PF_X3S027000BA1H-U~D E6 I2S_BCLK/GPIO_7 I2S_WCLK/GPIO_4 +1.2VS_A UART_TX UART_RX CV230 0.1U_0603_25V7K~D TX_TCLK TX_TCLK I2S_0/GPIO_8 I2S_1/GPIO_9 I2S_2/GPIO_10 I2S_3/GPIO_11 UART_TX UART_RX RV304 4.7K_0402_5%~D G1 3 G2 4 RESET C4 AUX_UART_TX/BOOT4/GPIO_21 AUX_UART_RX/GPIO_22 C2 B1 CV242 0.1U_0402_16V4Z~D 1 2 TX_TCLK CV243 47P_0402_50V8J~D TX_XTAL 1 RV303 2.7K_0402_5% C 2 CV233 10P_0402_50V8J~D 1 CV232 10P_0402_50V8J~D 2 eDP 1 CV221 0.1U_0603_25V7K~D TX_XTAL +3VS UART_TX/BOOT1/GPIO_13 UART_RX/GPIO_14 CV219 0.1U_0603_25V7K~D DPTX_ML_L0N DPTX_ML_L0P DPTX_ML_L1N DPTX_ML_L1P DPTX_ML_L2N DPTX_ML_L2P DPTX_ML_L3N DPTX_ML_L3P 2 CV214 0.1U_0603_25V7K~D DPTX_AUXN DPTX_AUXP CV217 22U_0805_6.3VAM~D B4 +AVDD_3V3 2 RV302 4.7K_0402_5%~D TX_XTAL B6 C6 A7 B7 A8 B8 B9 C9 I2C_SCL/GPIO_24 I2C_SDA/GPIO_25 1 EC_HDMI_CLK <37> EC_HDMI_DAT <37> CV218 0.1U_0603_25V7K~D 4028_EDP_L0N 4028_EDP_L0P 4028_EDP_L1N 4028_EDP_L1P 4028_EDP_L2N 4028_EDP_L2P 4028_EDP_L3N 4028_EDP_L3P 4028_EDP_L0N 4028_EDP_L0P 4028_EDP_L1N 4028_EDP_L1P 4028_EDP_L2N 4028_EDP_L2P 4028_EDP_L3N 4028_EDP_L3P DPTX_HPD_IN/GPIO_23 I2C_SCL I2C_SDA CV213 0.1U_0603_25V7K~D C10 D10 B13 A13 CV228 0.1U_0402_16V4Z~D <33> <33> <33> <33> <33> <33> <33> <33> 4028_EDP_AUXN 4028_EDP_AUXP AUX_I2C_SCL/GPIO_15 AUX_I2C_SDA_GPIO_16 DPTX_REXT CV212 0.1U_0603_25V7K~D <33> 4028_EDP_AUXN <33> 4028_EDP_AUXP C12 CV211 0.1U_0603_25V7K~D 1 C11 DP_4028_HPD 1 0_0402_5%~D 1 0_0402_5%~D 2 2 CV210 0.1U_0603_25V7K~D 1 240_0402_1% <33> DP_4028_HPD EC_HDMI_CLK_R @ RV299 EC_HDMI_DAT_R @ RV301 CV209 22U_0805_6.3VAM~D CV216 0.1U_0603_25V7K~D RV300 2 2 +AVDD_OUT_LV_33 LV25 2 1 BLM18AG601SN1D_0603~D C13 B14 2 D 1 1 4 2 5 AVSS_OUT_LVRX P1 +AVDD_OUT_LV_33 H12 H3 L8 N1 N14 STDP4028-AB_LFBGA164 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX F2 F13 H10 H5 K8 P14 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. LVDS to eDP-STDP4028 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 35 of 61 5 4 3 2 1 +3VS +3V_MXM VGA_DPD_AUXP/DDC 2 2.2K_0402_5%~D VGA_DPD_AUXN/DDC 2 2.2K_0402_5%~D +3VS 1 D 2 UV21 6 31 VDD VDD CV247 CV248 CV249 CV250 CV251 CV252 CV253 CV254 VGA_DPD_P0 VGA_DPD_N0 VGA_DPD_P1 VGA_DPD_N1 VGA_DPD_P2 VGA_DPD_N2 VGA_DPD_P3 VGA_DPD_N3 <8> CPU_DPD_DMC_P0 <8> CPU_DPD_DMC_N0 <8> CPU_DPD_DMC_P1 2 2 44 45 47 48 1 2 4 5 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D CPU_DPD_SW_P0 CPU_DPD_SW_N0 CPU_DPD_SW_P1 CPU_DPD_SW_N1 CPU_DPD_SW_P2 CPU_DPD_SW_N2 CPU_DPD_SW_P3 CPU_DPD_SW_N3 8 9 11 12 13 14 16 17 VGA_DMC_HPD_R PCH_DMC_HPD_R 1 10K_0402_5%~D 1 10K_0402_5%~D DGPU_EDIDSEL#_R DGPU_SEL# 22 21 DMC_IN1_PEQ DMC_IN2_PEQ 3 15 DMC_PWDN DMC_CFG_HPD 40 34 7 DMC_DDCBUF DMC_PRE_EMI 36 35 33 32 30 29 27 26 DMC_SW_P0 DMC_SW_N0 DMC_SW_P1 DMC_SW_N1 DMC_SW_P2 DMC_SW_N2 DMC_SW_P3 DMC_SW_N3 D +3VS Close to UV2 VCC pins OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p RV338 1 RV339 1 RV340 1 RV341 1 RV342 1 RV343 1 RV344 1 RV345 1 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N 1 OUT_HPD OUT_SCL OUT_SDA DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N DMC_SW_DETECT DP_DMC_AUXP DP_DMC_AUXN 39 38 37 IN1_PEQ IN2_PEQ DP_DMC_HPD 2 4.7K_0402_5%~D 1 +3VS RV61 1 38 39 41 42 44 45 47 48 2 +3VS <51> DP_DMC_HPD CEXT REXT GND GND PAD PS8271QFN48GTR-A1_QFN48_7X7 IN1p IN1n IN2p IN2n IN3p IN3n IN4p IN4n OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n OUT4p OUT4n POW HPD_SINK 26 I2C_CTL_EN# 32 DMC_OE# 25 8 9 NC/OE# HPD SDA SCL DMC_CFG1 DMC_CFG0 0 IN1 DMC_PC0 DMC_PC1 3 4 I2C_ADDR0/PC0 I2C_ADDR1/PC1 1 IN2 DMC_PC2 1 GND/PC2 499_0402_1%~D 1 RV62 2 1 CV268 10 +3VS 1 2 1 2 23 22 20 19 17 16 14 13 CPU_MXM_DMC_P0 CPU_MXM_DMC_N0 CPU_MXM_DMC_P1 CPU_MXM_DMC_N1 CPU_MXM_DMC_P2 CPU_MXM_DMC_N2 CPU_MXM_DMC_P3 CPU_MXM_DMC_N3 CPU_MXM_DMC_P0 CPU_MXM_DMC_N0 CPU_MXM_DMC_P1 CPU_MXM_DMC_N1 CPU_MXM_DMC_P2 CPU_MXM_DMC_N2 CPU_MXM_DMC_P3 CPU_MXM_DMC_N3 <51> <51> <51> <51> <51> <51> <51> <51> REXT CEXT DMC_SINK_HPD 7 29 28 DP_DMC_AUXN DP_DMC_AUXP PS121QFN48G_QFN48_7X7 1 +3VS SDAZ SCLZ SDA_CTL/CFG1 SCL_CTL/CFG0 5 12 18 24 27 31 36 37 43 49 2.2U_0402_6.3V6M~D2 6 2 NC/DDCBUF_EN# Y 34 35 1 C 30 DMC_DDCBUF DMC_SDATA_R DMC_SCLK_R SEL 2 +3VS UV22 SW_DDC SW_MAIN 18 43 49 2 RV348 499_0402_1%~D CV267 2.2U_0603_6.3V6K~D 2 DDCBUF PRE_EMI RTERM 25 28 IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA 23 24 1 CFG_HPD IN2_D1n IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p 46 10 41 42 19 20 C <36> DGPU_EDIDSEL#_R <36> DGPU_SEL# PWDN_ASQ IN1_D1n IN1_D1p IN1_D2n IN1_D2p IN1_D3n IN1_D3p IN1_D4n IN1_D4p 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D CV266 0.01U_0402_16V7K~D RV346 RV347 VGA_DPD_SW_P0 VGA_DPD_SW_N0 VGA_DPD_SW_P1 VGA_DPD_SW_N1 VGA_DPD_SW_P2 VGA_DPD_SW_N2 VGA_DPD_SW_P3 VGA_DPD_SW_N3 2 2 2 2 2 2 CV265 0.1U_0402_16V4Z~D <29> VGA_DMC_HPD <17> PCH_DMC_HPD <29> VGA_DPD_AUXP/DDC <29> VGA_DPD_AUXN/DDC <17> PCH_DPD_CLK <17> PCH_DPD_DAT 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D @ RV332 1 @ RV333 1 @ RV334 1 @ RV335 1 RV336 1 RV337 1 CV264 0.1U_0402_16V4Z~D <8> CPU_DPD_DMC_N2 <8> CPU_DPD_DMC_P3 <8> CPU_DPD_DMC_N3 CV255 CV256 CV257 CV258 CV259 CV260 CV261 CV262 2 2 2 2 2 2 2 2 DMC_PWDN DMC_CFG_HPD DMC_DDCBUF DMC_PRE_EMI DMC_IN1_PEQ DMC_IN2_PEQ CV263 0.01U_0402_16V7K~D CPU_DPD_DMC_N1 CPU <8> <8> CPU_DPD_DMC_P2 1 1 1 1 1 1 1 1 1 2.2K_0402_5%~D 2.2K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 11 15 21 33 40 46 MXM <29> <29> <29> <29> <29> <29> <29> <29> 2 CV246 0.1U_0402_16V4Z~D CV245 10U_0603_6.3V6M~D PCH/GPU AUX&LANE SW for DPB 1 1 2 2 2 2 2 2 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 1 RV330 RV30 2 RV31 2 @ RV324 1 @ RV325 1 RV326 1 @ RV328 1 RV329 1 RV331 1 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 RV327 PCH_DPD_CLK PCH_DPD_DAT DMC_PWDN DMC_CFG_HPD DMC_DDCBUF DMC_PRE_EMI DMC_IN1_PEQ DMC_IN2_PEQ 1 G 3 2 1 2 S D 2 1 @ 2 1 QV22 1 DV11 BAV99-7-F_SOT23-3 RV352 200K_0402_5% RV353 10K_0402_5%~D 1 2 RV351 0_0402_5%~D @ 3 2 B E DMC_SW_DETECT SSM3K7002F_SC59-3~D 2 B RV349 100K_0402_5%~D LV29 MBK1608221YZF_2P DMC_SINK_HPD 1 2 CV269 220P_0402_50V7K~D @QV21 MMST3904-7-F_SOT323-3~D @ RV350 200K_0402_5% 1 2 2 C 3 1 B D PS121 CFG0/ CFG1 SCLZ/SDAZ output voltage select; CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V PS121 PC0/PC1/PC2 Inputs equalization control, default inputs equalization setting at 12 dB 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB DMC_OE# 1 QV23 SSM3K7002F_SC59-3~D 2 G S 3 +5VS +3VS DGPU_HPD_INT# <21,36> DGPU_HPD_INT# +HDMI_5V_OUT 3 2 3 1 RV354 @ 1 RV355 @ 1 RV356 1 RV357 @ 1 RV358 1 RV359 1 RV360 DMC_CFG1 DMC_CFG0 DMC_PC0 DMC_PC1 DMC_PC2 DP_DMC_AUXP DP_DMC_AUXN 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 2 2 2 2 2 1 RV361 @ 1 RV362 @ 1 RV363 @ 1 RV364 @ 1 RV365 @ DMC_CFG1 DMC_CFG0 DMC_PC0 DMC_PC1 DMC_PC2 1 Place LC Filter closed to JHDMI @ DV13 DAN217T146_SC59-3 1 1 @ DV12 DAN217T146_SC59-3 2 2 2 2 2 2 2 A 2 2 RV367 1.5K_0402_5% DMC_SDATA_R DMC_SCLK_R RV366 1.5K_0402_5% A 1 2 +HDMI_5V_OUT 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXP 1 2 @ CV271 1 2 10P_0402_50V8J~D @ CV270 10P_0402_50V8J~D 1 2 RV368 1 0_0402_5%~D 2 RV369 0_0402_5%~D CPU_MXM_DMC_AUXN <51> CPU_MXM_DMC_AUXP <51> Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DP SW for DMC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 36 of 61 5 4 3 +3VS 2 1 +3VS_RT +1.2VS 30mil +DVCC33 60 mils LVDS@ 1 1 2 MIIC_SCL MIIC_SDA LVDS@ RV23 RV24 EDID_CLK RV25 EDID_DATA RV26 D Close to LV11 Close to 11 pin LVDS@ LVDS@ EEROM UV23 1 CV275 2 CV274 2 CV273 2 1 0.1U_0402_16V4Z +SWR_V12 LVDS@ 2 0_0805_5% 0.1U_0402_16V4Z 1 RV8 0.1U_0402_16V4Z CV272 2 0_0805_5% 22U_0805_6.3V6M 1 RV7 30mil 8 7 6 5 0_0402_5% FW_ROM_SCL 1 LVDS@ 2 FW_ROM_SDA 1 LVDS@ 2 0_0402_5% LVDS@ 0_0402_5% 1 2 1 LVDS@ 2 0_0402_5% VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 CAT24C64WI-GT3_SO8 Addr: A8 (1010 100X) D LVDS@ Close to 43 pin LVDS@ UV24 RTD2136S +DVCC33 +3VS_RT 2 Close to 5 pin Close to LV10 LVDS@ Close to 18 pin LVDS@ LVDS@ CPU_EDP_P1_C CPU_EDP_N1_C <31> CPU_EDP_P1_C <31> CPU_EDP_N1_C Close to 22 pin LVDS@ LVDS@ 2136_HPD# ENBKL LANE0P LANE0N 2 0_0402_5% TL_INVT_BL 41 42 LVDS_A0 LVDS_A0# TXO1+ TXO1- 39 40 LVDS_A1 LVDS_A1# TXO2+ TXO2- 37 38 LVDS_A2 LVDS_A2# TXO3+ TXO3- 33 34 TXEC+ TXEC- 25 26 LVDS_BCLK LVDS_BCLK# TXE0+ TXE0- 31 32 LVDS_B0 LVDS_B0# LANE1P LANE1N TXE1+ TXE1- 29 30 LVDS_B1 LVDS_B1# 4 3 AUX-CH_P AUX-CH_N TXE2+ TXE2- 27 28 LVDS_B2 LVDS_B2# 1 DP_HPD TXE3+ TXE3- 23 24 PWMIN TESTMODE DP_REXT CSCL CSDA <42> 1 RV11 2 0_0402_5% 1 RV20 2 0_0402_5% LVDS@ LVDS@ CIICSCL CIICSDA 13 14 MIICSCL0 MIICSDA0 CIICSCL1 CIICSDA1 +DVCC33 MIICSCL1 MIICSDA1 PANEL_VCC PWMOUT BL_EN 46 45 EDID_CLK EDID_DATA 20 19 44 TL_ENVDD TL_INVT_PWM TL_BKOFF#_R LVDS_ACLK LVDS_ACLK# <41> <41> LVDS_A0 LVDS_A0# <41> <41> LVDS_A1 LVDS_A1# <41> <41> LVDS_A2 LVDS_A2# <41> <41> LVDS_BCLK LVDS_BCLK# <41> <41> LVDS_B0 LVDS_B0# <41> <41> LVDS_B1 LVDS_B1# <41> <41> LVDS_B2 LVDS_B2# <41> <41> C EDID_CLK <42> EDID_DATA <42> TL_ENVDD <42,43> TL_INVT_PWM <42> 6 DP_GND LVDS@ 16 GND 1 RV15 2 0_0402_5% 49 PAD RTD2136S-VE-CG_QFN48_6X6 +3VS_RT RV50 4.7K_0402_5% 1 4 LVDS@ MC74VHC1G08DFT2G SC70 5P RV16 100K_0402_5% LVDS@ 1 G Y MIIC_SCL EEPROM LVDS@ +DVCC33 B CPU_EDP_AUX#_C CPU_EDP_AUX_C ROMLESS 1 +3VS_RT MIIC_SDA 2 RV19 100K_0402_5% LVDS@ EC_SMB_DA2 RV52 1 2 4.7K_0402_5% RV46 4.7K_0402_5% @ LVDS@ EDID_CLK RV21 1 CSCL RV47 1 LVDS@ 2 4.7K_0402_5% CSDA RV51 1 LVDS@ 2 4.7K_0402_5% 2 4.7K_0402_5% 5 QV2A DMN66D0LDW-7_SOT363-6~D 4 3 EC_SMB_DA2 <19,43,53,54> AUX termination TL_BKOFF#_R EC_SMB_CK2 EC_SMB_CK2 <19,43,53,54> LVDS@ QV2B DMN66D0LDW-7_SOT363-6~D RV22 100K_0402_5% LVDS@ 2 CSCL 1 6 1 1 Pull-Low 100K 2 2 +DVCC33 LVDS@ EDID_DATA CSDA RV45 4.7K_0402_5% LVDS@ 1 1 RV18 4.7K_0402_5% LVDS@ 2 2 2 B 7 8 MIIC_SCL 48 MIIC_SDA 47 CV284 0.1U_0402_16V7K 1 2 LVDS@ 5 A DP_V12 TXO0+ TXO0- P 1 UV25 3 <42,43> BKOFF# 11 21 2 12 2 12K_0402_1% <42,43> LVDS@ B VCCK LVDS_ACLK LVDS_ACLK# 2 2 0_0402_5% 1 2 43 OTHERS 1 RV9 @ +3VS_RT SWR_VCCK LVDS@ 1 RV12 PCH_EDP_PWM <17> PCH_EDP_PWM Vendor advise reserve it TL_BKOFF#_R SWR_LX 15 9 10 CPU_EDP_AUX_C CPU_EDP_AUX#_C <31> CPU_EDP_AUX_C <31> CPU_EDP_AUX#_C LVDS@ <31> 2136_HPD# RV14 17 35 36 DP Close to LV9 CPU_EDP_P0_C CPU_EDP_N0_C <31> CPU_EDP_P0_C <31> CPU_EDP_N0_C C LVDS@ LVDS@ DP_V33 TXOC+ TXOC- 1 CV283 2 SWR_VDD LVDS 1 CV282 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z CV281 2 CV280 2 1 22U_0805_6.3V6M 2 1 0.1U_0402_16V4Z CV279 10U_0603_6.3V6M 1 CV278 CV277 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z CV276 10U_0603_6.3V6M 2 1 18 5 +DVCC33 1 PVCC GND +AVCC33 +DVCC33 LV30 2 40 mils 1 FBMA-L11-201209-221LMA30T_0805 +AVCC33 LV31 2 1 FBMA-L11-201209-221LMA30T_0805 +SW_LX LV32 1 60 mils 2 4.7UH_PG031B-4R7MS_1.1A_20% 60 mils LVDS@ 22 PWR +SWR_V12 LVDS@ LVDS@ LVDS@ A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Translator RTD2136S THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 37 of 61 5 4 3 2 1 STDP6038 SW STDP4028 PCH/GPU AUX for LVDS D D UV26 SLE1 LVDS_A0# LVDS_A0 <40> LVDS_A0# <40> LVDS_A0 LVDS_MXM_TXOUT0LVDS_MXM_TXOUT0+ <29> LVDS_MXM_TXOUT0<29> LVDS_MXM_TXOUT0+ LVDS_A1# LVDS_A1 <40> LVDS_A1# <40> LVDS_A1 LVDS_MXM_TXOUT1LVDS_MXM_TXOUT1+ <29> LVDS_MXM_TXOUT1<29> LVDS_MXM_TXOUT1+ LVDS_A2# LVDS_A2 <40> LVDS_A2# <40> LVDS_A2 LVDS_MXM_TXOUT2LVDS_MXM_TXOUT2+ <29> LVDS_MXM_TXOUT2<29> LVDS_MXM_TXOUT2+ LVDS_ACLK# LVDS_ACLK <40> LVDS_ACLK# <40> LVDS_ACLK LVDS_MXM_TXCLKLVDS_MXM_TXCLK+ <29> LVDS_MXM_TXCLK<29> LVDS_MXM_TXCLK+ RTD2136 DGPU_MXM C Input LVDS_B0# LVDS_B0 <40> LVDS_B0# <40> LVDS_B0 LVDS_MXM_TZOUT0LVDS_MXM_TZOUT0+ <29> LVDS_MXM_TZOUT0<29> LVDS_MXM_TZOUT0+ LVDS_B1# LVDS_B1 <40> LVDS_B1# <40> LVDS_B1 LVDS_MXM_TZOUT1LVDS_MXM_TZOUT1+ <29> LVDS_MXM_TZOUT1<29> LVDS_MXM_TZOUT1+ LVDS_B2# LVDS_B2 <40> LVDS_B2# <40> LVDS_B2 LVDS_MXM_TZOUT2LVDS_MXM_TZOUT2+ <29> LVDS_MXM_TZOUT2<29> LVDS_MXM_TZOUT2+ LVDS_BCLK# LVDS_BCLK <40> LVDS_BCLK# <40> LVDS_BCLK LVDS_MXM_TZCLKLVDS_MXM_TZCLK+ <29> LVDS_MXM_TZCLK<29> LVDS_MXM_TZCLK+ 2 1 80 79 2B1 3B1 76 75 2B2 3B2 73 72 4B1 5B1 71 70 4B2 5B2 68 67 6B1 7B1 66 65 6B2 7B2 64 63 8B1 9B1 62 61 8B2 9B2 60 59 58 57 56 55 54 53 51 50 49 48 46 45 44 43 40 39 EDP_DETECT# EDP_DETECT# <21> 5 6 LVDS_MUX_TXOUT0LVDS_MUX_TXOUT0+ A2 A3 8 9 LVDS_MUX_TXOUT1LVDS_MUX_TXOUT1+ A4 A5 11 12 LVDS_MUX_TXOUT2LVDS_MUX_TXOUT2+ A6 A7 14 15 LVDS_MUX_TXCLKLVDS_MUX_TXCLK+ A8 A9 17 18 A0 A1 LVDS_MUX_TXOUT0- <42> LVDS_MUX_TXOUT0+ <42> 0B2 1B2 78 77 42 41 B 0B1 1B1 16 LVDS_MUX_TXOUT1- <42> LVDS_MUX_TXOUT1+ <42> LVDS_MUX_TXOUT2- <42> LVDS_MUX_TXOUT2+ <42> LVDS_MUX_TXCLK- <42> LVDS_MUX_TXCLK+ <42> C Output 10B1 11B1 EDP_DETECT# SEL2 34 A10 A11 23 24 LVDS_MUX_TZOUT0LVDS_MUX_TZOUT0+ 26 27 LVDS_MUX_TZOUT1LVDS_MUX_TZOUT1+ 29 30 LVDS_MUX_TZOUT2LVDS_MUX_TZOUT2+ 32 33 LVDS_MUX_TZCLKLVDS_MUX_TZCLK+ LVDS_MUX_TZOUT0- <42> LVDS_MUX_TZOUT0+ <42> 10B2 11B2 12B1 13B1 A12 A13 LVDS_MUX_TZOUT1- <42> LVDS_MUX_TZOUT1+ <42> 12B2 13B2 14B1 15B1 A14 A15 LVDS_MUX_TZOUT2- <42> LVDS_MUX_TZOUT2+ <42> 14B2 15B2 16B1 17B1 A16 A17 LVDS_MUX_TZCLK- <42> LVDS_MUX_TZCLK+ <42> 16B2 17B2 18B1 19B1 A18 A19 35 36 B +3VS 18B2 19B2 2 2 D S 3 1 3 13 20 21 31 38 52 74 25 7 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# QV24 SSM3K7002F_SC59-3~D VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 1 2 1 2 1 2 CV287 4.7U_0603_6.3V6K~D G RV370 100K_0402_5%~D CV286 0.1U_0402_16V4Z~D <33,34,42> LCDVDD_ON CV285 0.1U_0402_16V4Z~D 1 +3VS PI3LVD1012BE_BQSOP80 SEL L H Y RTD2136 DGPU_MXM A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. LVDS SW- 1 to 2 & GPU/PCH THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 38 of 61 5 4 3 2 1 PCH/GPU MUX & 6038 MUX SW for LVDS LCD Backlight Selector 1 +3VS RV371 @ 10K_0402_5%~D 2 0_0402_5%~D HDMI_IN_PWM_SELECT# <43> EC_INV_PWM RV375 1 2 0_0402_5%~D UV28 0_0402_5%~D RV377 1 2 VGA_EC_PWM HDMI_IN_PWM TL_INVT_PWM <29> VGA_PNL_PWM <37> HDMI_IN_PWM <40> TL_INVT_PWM RV400 1 2 0_0402_5%~D INV_PWM ENBKL DGPU_BKL_PWM_SEL# INV_PWM ENBKL 2 0_0402_5%~D 8 2 SN74CB3Q3253PWR_TSSOP16 S0 1A 0 0 1B1 2B1 0 Y 2A 1 1B2 2B2 1 0 1B3 2B3 1 1 1B4 2B4 C DGPU_SELECT# <41> LVDS_MUX_TXCLK<41> LVDS_MUX_TXCLK+ <34> LVDS_TXCLK<34> LVDS_TXCLK+ CPU/MXM(MUX) HDMI IN(1:2) DSC 76 75 LVDS_MUX_TXOUT2LVDS_MUX_TXOUT2+ 73 72 LVDS_TXOUT2LVDS_TXOUT2+ 71 70 LVDS_MUX_TXCLKLVDS_MUX_TXCLK+ 68 67 LVDS_TXCLKLVDS_TXCLK+ 66 65 Input 62 61 USB20_N12_CONN 2B1 3B1 A2 A3 <34> LVDS_TZOUT0<34> LVDS_TZOUT0+ +3VS 6 5 4 3 2 VGA_LCD_DAT DHMI_IN_NV_DAT EDID_DATA 10 11 12 13 1 1B1 1B2 1B3 1B4 VCC 2B1 2B2 2B3 2B4 1A 2A 2OE 1OE GND 16 S0 S1 14 2 HDMI_IN_SELECT# DGPU_EDIDSEL_R# 7 9 I2CC_SCL I2CC_SDA <34> LVDS_TZOUT1<34> LVDS_TZOUT1+ <41> LVDS_MUX_TZOUT2<41> LVDS_MUX_TZOUT2+ <34> LVDS_TZOUT2<34> LVDS_TZOUT2+ <41> LVDS_MUX_TZCLK<41> LVDS_MUX_TZCLK+ 15 <34> LVDS_TZCLK<34> LVDS_TZCLK+ 8 58 57 LVDS_MUX_TZOUT1LVDS_MUX_TZOUT1+ 56 55 LVDS_TZOUT1LVDS_TZOUT1+ 54 53 LVDS_MUX_TZOUT2LVDS_MUX_TZOUT2+ 51 50 LVDS_TZOUT2LVDS_TZOUT2+ 49 48 LVDS_MUX_TZCLKLVDS_MUX_TZCLK+ 46 45 LVDS_TZCLKLVDS_TZCLK+ 44 43 42 41 SN74CB3Q3253PWR_TSSOP16 1A 2A A4 A5 4B2 5B2 6B1 7B1 A6 A7 1 6B2 7B2 8B1 9B1 A8 A9 1B3 2B3 1 1 1B4 2B4 DSC 3 13 20 21 31 38 52 74 25 7 RV385 100K_0402_5%~D LCDVDD_ON HDMI IN (I) UMA 2 2 0 D S 3 LCD POWER +LCDVDD +LCDVDD 1 QV27 SSM3K7002F_SC59-3~D S +3VS QV28 SI2301CDS-T1-GE3_SOT23-3~D 12B1 13B1 A12 A13 TZOUT1TZOUT1+ 26 27 1 SEL L H 12B2 13B2 14B1 15B1 A14 A15 TZOUT2TZOUT2+ 29 30 16B1 17B1 A16 A17 TZCLKTZCLK+ 32 33 2 G 3 @ 2 RV393 <40,43> BKOFF# 16B2 17B2 2OE 1OE GND 7 9 LCDVDD_ON A18 A19 35 36 18B2 19B2 +3VS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 1 2 1 2 1 2 DMIC_CLK @ RV386 10K_0402_5%~D 1 2 DGPU_SELECT# <17,32,36> @ LCDVDD_ON <33,34,41> RV389 2 0_0402_5%~D 1 @ LV33 15 8 <20> <20> USB20_P12 USB20_N12 USB20_P12 4 USB20_N12 1 RV392 4 S1 S0 0 0 1B1 2B1 HDMI IN 0 1 1B2 2B2 DSC 1 0 1B3 2B3 HDMI IN 1 1 1B4 2B4 UMA 1A 2A Y 1 2 1 2 BKOFF# RV384 1 @ 2 0_0402_5%~D DISPOFF# JLVDS1 18B1 19B1 4 3 1 2 3 USB20_P12_CONN 2 USB20_N12_CONN DLW21SN900SQ2L_0805_4P~D RV394 100K_0402_5%~D 2 1A 2A 2 B1 B2 LVDS Conn. HDMI_IN_SELECT# DGPU_SELECT# Y 14B2 15B2 CV299 0.1U_0402_16V4Z~D 2 EN_CAM control circuit Close to JLVDS1 +3VS 14 2 SN74CB3Q3253PWR_TSSOP16 4 1 1 0_0402_5%~D 5 1 2B1 2B2 2B3 2B4 S0 S1 16 2 C 2 S D 1 2 1 2 6 1 2 RV391 2 10 11 12 13 <29> DGPU_ENVDD <37> HDMI_IN_ENVDD <40,43> TL_ENVDD VCC 1 2 0_0402_5%~D 1 55 54 53 52 51 50 49 48 47 46 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 JAE_FI-TD44SB-E-R750~D CONN@ GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ 1 TZOUT0TZOUT0+ 2 TZOUT1TZOUT1+ TZOUT2TZOUT2+ 1 @ 2 B @ TZCLKTZCLK+ 1 I2CC_SCL I2CC_SDA 2 USB20_N12_CONN USB20_P12_CONN CAM_DET# DMIC_CLK DMIC0 DISPOFF# INV_PWM LVDS_CAB_DET# LCD_TEST CAM_DET# DMIC_CLK DMIC0 DISPOFF# 1 @ <18,33> <33,45> <33,45> <33> 2 @ CV321 10P_0402_50V8J~D 1 QV3B DMN66D0LDW-7_SOT363-6~D 2 1B1 1B2 1B3 1B4 1 CV320 10P_0402_50V8J~D 0_0402_5%~D 5 1 6 5 4 3 2 +3VS CV322 10P_0402_50V8J~D <33,43> EC_ENVDD 2 UV30 1 CV304 .047U_0402_16V7K~D A LCDVDD_ON 1 RV390 2 1 220K_0402_1% 1 1 +LCDVDD 10B2 11B2 +3VS 3 CV301 4.7U_0805_10V4Z~D QV3A DMN66D0LDW-7_SOT363-6~D 2 CV300 4.7U_0805_10V4Z~D RV387 47K_0402_5%~D 2 RV388 100_0603_5%~D 1 CV303 0.1U_0402_16V4Z~D 2 CV302 0.1U_0402_16V4Z~D 1 1 3 TZOUT0TZOUT0+ PI3LVD1012BE_BQSOP80 W=60mils 1 2 G EN_CAM HDMI_IN_SELECT#_R 34 23 24 1 +5VALW D <43> A10 A11 3 Output 8B2 9B2 10B1 11B1 +3VS_CAM CV319 10P_0402_50V8J~D 1 17 18 +3VS HDMI IN (D) D CV318 10P_0402_50V8J~D 1B2 2B2 2 TXCLKTXCLK+ 14 15 CV298 4.7U_0603_6.3V6K~D 1B1 2B1 1 +5VS QV25 SI2301CDS-T1-GE3_SOT23-3~D CV297 0.1U_0402_16V4Z~D 0 40 39 G 0 0 Y 1 S0 5 4 V I/O V I/O IP4223CZ6_SO6~D +3VS 4B1 5B1 CV296 0.1U_0402_16V4Z~D B S1 6 CV295 10U_0805_10V4Z~D VGA_LCD_CLK DHMI_IN_NV_CLK EDID_CLK <41> LVDS_MUX_TZOUT1<41> LVDS_MUX_TZOUT1+ LVDS_TZOUT0LVDS_TZOUT0+ TXOUT2TXOUT2+ V I/O Ground V BUS CV294 0.1U_0402_16V4Z~D 1 DGPU_EDIDSEL_R# 60 59 11 12 V I/O CV292 0.1U_0402_16V4Z~D @ RV382 0_0402_5%~D 1 2 <41> LVDS_MUX_TZOUT0<41> LVDS_MUX_TZOUT0+ LVDS_MUX_TZOUT0LVDS_MUX_TZOUT0+ 8 9 TXOUT1TXOUT1+ 3 2B2 3B2 SEL2 LCD DDC Selector UMA 2 0B2 1B2 HDMI IN (I) CV293 0.1U_0402_16V4Z~D <29> VGA_LCD_DAT <37> DHMI_IN_NV_DAT <40> EDID_DATA <34> LVDS_TXOUT2<34> LVDS_TXOUT2+ 78 77 LVDS_TXOUT1LVDS_TXOUT1+ 64 63 UV29 <29> VGA_LCD_CLK <37> DHMI_IN_NV_CLK <40> EDID_CLK <41> LVDS_MUX_TXOUT2<41> LVDS_MUX_TXOUT2+ <33> <40,43> HDMI IN (D) RV383 0_0402_5%~D 1 2 <21,32,36> DGPU_EDIDSEL# <21> <34> LVDS_TXOUT1<34> LVDS_TXOUT1+ DV14 1 QV26 SSM3K7002F_SC59-3~D S1 <33,43> USB20_P12_CONN CV291 10U_0805_10V4Z~D 1 1 RV378 <17,43> SG_AMD_BKL HDMI_IN_SELECT# CV290 0.1U_0402_16V4Z~D 15 2 TXOUT0TXOUT0+ 5 6 D GND 7 9 <41> LVDS_MUX_TXOUT1<41> LVDS_MUX_TXOUT1+ LVDS_MUX_TXOUT1LVDS_MUX_TXOUT1+ A0 A1 G 1OE HDMI_IN_PWM_SELECT# 80 79 0B1 1B1 S 2OE 14 2 2 1 RV381 100K_0402_5%~D 1A 2A 1 CV289 0.1U_0402_16V4Z~D 2B1 2B2 2B3 2B4 S0 S1 RV380 100K_0402_5%~D 10 11 12 13 VCC 1 @ 2 16 1B1 1B2 1B3 1B4 RV379 100K_0402_5%~D <43> EC_INV_PWM <29> DGPU_BKL_EN <37> HDMI_IN_BKL_EN <40> TL_INVT_BL 6 5 4 3 LVDS_MUX_TXOUT0LVDS_MUX_TXOUT0+ LVDS_TXOUT0LVDS_TXOUT0+ <34> LVDS_TXOUT0<34> LVDS_TXOUT0+ @ RV376 10K_0402_5%~D 1 @ +3VS 1 1 <41> LVDS_MUX_TXOUT0<41> LVDS_MUX_TXOUT0+ 2 D RV373 HDMI_IN_SELECT#_R 16 0_0402_5%~D CV288 0.1U_0402_16V4Z~D +3VS SLE1 2 2 0_0402_5%~D 1 1 1 RV374 2 @ RV372 2 DGPU_SELECT# <17> HDMI_IN_PWMSEL# 2 UV27 LVDS_CAB_DET# <21> +3VS_CAM LCD_TEST <33,43> +3VS +LCDVDD W=60mils +INVPWR_B+ B+ @ LV34 1 2 FBMA-L11-201209-221LMA30T_0805 W=80mils A DELL CONFIDENTIAL/PROPRIETARY @ Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3 2 Title LVDS SW- 6038/SYSTEM & CONN Size Document Number Date: Friday, June 22, 2012 Rev 0.1 LA-9331P Sheet 1 39 of 61 5 4 3 2 1 +5VS 1 1 2 3 4 8 7 6 5 KSO4_EC KSO5_EC KSO6_EC KSO7_EC 0_0804_8P4R_5% 0_0804_8P4R_5% RP3 RP4 1 2 3 4 8 7 6 5 KSI4_EC KSI5_EC KSI6_EC KSI7_EC KSO8 KSO9 KSO10 KSO11 2 0_0804_8P4R_5% RP5 KSO0 1 KSO1 2 KSO2 3 KSO3 4 1 8 KSO8_EC 7 KSO9_EC 6 KSO10_EC 5 KSO11_EC 1 2 3 4 0_0804_8P4R_5% RE66 @ 33_0402_5%~D Reserve for EMI please close to UE1 RP6 8 KSO0_EC 7 KSO1_EC 6 KSO2_EC 5 KSO3_EC KSO12 KSO13 KSO14 KSO15 8 KSO12_EC 7 KSO13_EC 6 KSO14_EC 5 KSO15_EC 1 2 3 4 0_0804_8P4R_5% <29> EC_SMB_CK1 <29> EC_SMB_DA1 RE75 1 2 0_0402_5%~D <37> EC_SMB_CK2_R RE76 1 2 0_0402_5%~D <37> EC_SMB_DA2_R <19,40,53,54> EC_SMB_CK2 <19,40,53,54> EC_SMB_DA2 0_0804_8P4R_5% KSO16 RE115 1 KSO17 RE116 1 <17,47> PM_SLP_S3# <17,47> PM_SLP_S5# 2 0_0402_5%~D KSO16_EC 2 0_0402_5%~D KSO17_EC 2 0_0402_5%~D PM_SLP_S3#_R 2 0_0402_5%~D PM_SLP_S5#_R EC_SMI# <21> EC_SMI# PS_ID <57> PS_ID EC_ESB_CLK_R EC_ESB_DAT SUSPWRDNACK <17> SUSPWRDNACK RE77 1 RE78 1 <54> SYSTEM_FAN_FB <53> MXM1_FAN_FB <50> E51TXD_P80DATA <50> E51RXD_P80CLK <17> PCH_PWROK <53> WLES ON/OFF LED# <17,42> SG_AMD_BKL SYSTEM_FAN_FB MXM1_FAN_FB E51TXD_P80DATA E51RXD_P80CLK PCH_PWROK WLES ON/OFF LED# SG_AMD_BKL 77 78 79 80 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A XCLKI/GPIO5D XCLKO/GPIO5E H_PROCHOT# 1 RE80 2 0_0402_5%~D VR_HOT# <62> 1 D 2 CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 ME_EN/GPXIOA02 VCIN0_PH/GPXIOD00 @ RE68 2 M_THERMAL# EC_ENVDD LCD_TEST 83 84 85 86 87 88 EC_MUTE# IMVP_PWRGD LCD_BKL_EN EC_LID_OUT# TP_CLK TP_DATA EC_MUTE# IMVP_PWRGD LCD_BKL_EN EC_LID_OUT# TP_CLK TP_DATA 97 98 99 109 CPU1.5V_S3_GATE EN_WOL# HDA_SDO VCIN0_PH CPU1.5V_S3_GATE <10> EN_WOL# <44> HDA_SDO <16> VCIN0_PH <57> 119 120 126 128 PWRSHARE_EN_EC# PWRSHARE_OE# VPK_EN 3V_F347_ON PWRSHARE_EN_EC# <52> PWRSHARE_OE# <52> VPK_EN <53> 3V_F347_ON <47> 73 74 89 90 91 92 93 95 121 127 KB_DET#_EC RE114 1 2 0_0402_5%~D PCIE_WAKE#_EC RE82 1 2 0_0402_5%~D PCH_DPWROK PCH_DPWROK <17> BATT_CHG_LED# BATT_CHG_LED# <47> CAPS_LED# CAPS_LED# <53> PWR_LED# PWR_LED# BATT_LOW_LED# BATT_LOW_LED# <47> SYSON SYSON <56,59,60> IMVP_VR_ON IMVP_VR_ON <62> PM_SLP_S4#_R RE81 1 2 0_0402_5%~D 100 101 102 103 104 105 106 107 108 PCH_RSMRST# ADP_I ENBKL ECAGND 1 100P_0402_50V8J~D @ 1 0_0402_5%~D 1 0_0402_5%~D SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A SPI Flash ROM GPIO Bus GPIO ENBKL/AD6/GPIO40 PECI_KB930/AD7/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R VCIN1_PH 110 112 114 115 116 117 118 CE47 2 ACIN EC_ON ON/OFF LID_SW_IN# SUSP# USB_PWR_EN# EC_PECI RE74 1 124 +V18R 1 2 20mil KB9012QF-A3_LQFP128_14X14 Board ID ACIN <17,29,47,57,63> EC_ON <58> ON/OFF <55> LID_SW_IN# <19,47,48,53> SUSP# <10,56,59,61> USB_PWR_EN# <52,53> 2 43_0402_1% H_PECI <6,21> Please place RE74 close to EC with in 750mil PCB Revision 0.1 (SSI) 0 1 2 3 4 5 6 7 * Rb 0 0.2 (PT) 8.2K +/- 5% 0.3 (ST) 18K +/- 5% 0.4 (QT) 33K +/- 5% 56K +/- 5% 1.0 (MP) 100K +/- 5% B 1 47P_0402_50V8J~D CE51 @ PCH_PWR_EN H_PROCHOT#_EC need add <29> TH_OVERT# TH_OVERT#_EC 2 0_0402_5%~D 1 RE79 UE2 EC_ESB_CLK 1 HDMI_TOGGLE 2 RST# 3 EC_ESB_DAT 4 DEPOP#_EC 5 HDMI_IN_SELECT# 6 HDMI_IN_CAB_DET#7 DGPU_PWR_EN 8 DGPU_PWROK 9 <17> DGPU_HOLD_RST# DGPU_HOLD_RST#10 <35> HDMI_IN_OUT_DDC HDMI_IN_OUT_DDC11 2 1 3 2 CE46 0.1U_0402_16V4Z~D 2 BOARD ID Table ESB_CLK GPIO00 RST# TEST_EN# GPIO08/CAS_DAT GPIO09 ESB_DAT GPIO0A GPIO01 GPIO0B GPIO02 GPIO0C/PWM0 GPIO03 GPIO0D/PWM1 GPIO04 GPIO0E/PWM2 GPIO05 GPIO0F/PWM3 GPIO06 GPIO10/ESB_RUN# GPIO07/CAS_CLK GND KC3810_QFN24_4X4 1 1 2 S 1 RE70 0_0402_5% Rb <57> RE86 100K_0402_5%~D USBCHG_DET_PWR_EN# 2 G RE67 100K_0402_5%~D PM_SLP_S4# <17> <29,30> DGPU_PWROK USBCHG_DET_D @ QE21 SSM3K7002F_SC59-3~D AD_BID0 KB_DET# <53> PCIE_WAKE# <17,44,51> 12 D 3 GPIO11/BaseAddOpt VCC 13 14 HDMI_IN_OUT_HPD 15 HDMI_SW 16 HDMI_OUT_EN 17 TL_ENVDD 18 EC_INV_PWM EC_INV_PWM <42> 19 HDMI_IN_EN HDMI_IN_EN <37> 20 TH_OVERT#_EC 21 DP_MXM_CARD_SEL DP_MXM_CARD_SEL <30,32> 22 EC_AC_BAT# EC_AC_BAT# <29> 23 EN_CAM <58> <35> <35> HDMI_OUT_EN <35> TL_ENVDD EN_CAM <40,42> <42> +3VALW_EC 1 2 QE321 SSM3K7002FU_SC70-3~D HDMI_IN_OUT_HPD HDMI_SW 24 CE50 0.1U_0402_16V4Z~D RE87 100K_0402_5%~D S C <29,56> DGPU_PWR_EN +3VLP <45> 2 G Ra <37> HDMI_TOGGLE +3VALW_EC DEPOP# +3VALW_EC VCOUT0_PH# <58> BKOFF# <40,42> PBTN_OUT# <6,17> PCH_PWR_EN <35,56> VPK_DET# <53> 1100P_0402_50V8J~D 2 DEPOP# 1 Board ID LE44 FBMA-L11-160808-800LMT_0603 2 A RE62 0_0402_5%~D 1 2 PCH_RSMRST# <17> VCIN1_PH H_PROCHOT#_EC VCOUT0_PH# BKOFF# PBTN_OUT# PCH_PWR_EN VPK_DET# USBCHG_DET_EC# VL <57> BATT_TEMP <57,63> PM_SLP_SUS# <17> EAPD# <45> <45> <6,17,62> <33> <19> <53> <53> 1 1 <52> USBCHG_DET# ECAGND @ <37> HDMI_IN_CAB_DET# RE85 10K_0402_5%~D 1 2 D Reserve for EMI please close to UE2 D <33,42> HDMI_IN_SELECT# 3 2 <40,42> QE22 DE83 BAT54CW_SOT323-3 1 1 0_0402_5%~D ODD_EJECT# <50> M_THERMAL# <12,13,14,15> EC_ENVDD <33,42> LCD_TEST <33,42> SPI Device Interface RE89 10K_0402_5%~D 1 2 PCH_PWROK 2 H_PROCHOT#_EC G SSM3K7002F_SC59-3~D S 3 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F PS2 Interface 2 ECAGND <6,63> H_PROCHOT# 68 70 71 72 RE63 2 RE64 2 <57,63> 1 2 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 BATT_TEMP EAPD#_R ADP_I AD_BID0 USBCHG_DET_EC# ENBKL EN_TPLED# <48> BEEP# <45> SYSTEM_FAN_PWM <54> MXM1_FAN_PWM <53> 2 CE42 1 RE41 DEPOP#_EC DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F DA Output 11 24 35 94 113 FB_CLAMP_TGL_REQ# 122 FB_CLAMP 123 AD CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D 63 64 65 66 75 76 CE48 4.7U_0805_10V4Z~D <29> FB_CLAMP_TGL_REQ# <29> FB_CLAMP B EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 BATT_TEMP/AD0/GPIO38 AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 IMON/AD5/GPIO43 EN_TPLED# BEEP# SYSTEM_FAN_PWM MXM1_FAN_PWM 2 2 KSO4 KSO5 KSO6 KSO7 @ KSI0_EC KSI1_EC KSI2_EC KSI3_EC PWM Output 21 23 26 27 4.7K_0402_5%~D 1 KSI4 KSI5 KSI6 KSI7 RP2 8 7 6 5 CE45 22P_0402_50V8J~D C 1 2 3 4 2 RP1 KSI0 KSI1 KSI2 KSI3 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 TP_DATA RE65 10K_0402_5%~D KSI0_EC KSI1_EC KSI2_EC KSI3_EC KSI4_EC KSI5_EC KSI6_EC KSI7_EC KSO0_EC KSO1_EC KSO2_EC KSO3_EC KSO4_EC KSO5_EC KSO6_EC KSO7_EC KSO8_EC KSO9_EC KSO10_EC KSO11_EC KSO12_EC KSO13_EC KSO14_EC KSO15_EC KSO16_EC KSO17_EC CLK_PCI_LPC Reserved for KB9012 1 RE35 2 EC_SCI# ACOFF 12 13 37 20 38 +3VLP 2 1 <21> <63> CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# ACOFF GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 2 0_0402_1% 4.7K_0402_5%~D 2 <18> CLK_PCI_LPC <6,17,44,51,53> PLT_RST# @ RE40 33_0402_5%~D TP_CLK 1 1 1 2 3 4 5 7 8 10 0.1U_0402_16V7K CE33 ECAGND GND 2 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 2 @ EC_VDD/AVCC <21> GATEA20 <21> KB_RST# <19> SERIRQ <19,51> LPC_FRAME# <19,51> LPC_AD3 <19,51> LPC_AD2 <19,51> LPC_AD1 <19,51> LPC_AD0 CE44 .1U_0402_16V7K~D 2 KSO[0..17] <53> KSO[0..17] 1 AGND/AGND 1 2 2 RE56 47K_0402_5%~D 1 KSI[0..7] KSI[0..7] 1 1000P_0402_50V7K UE1 RST# CE43 0.1U_0402_16V4Z~D 2 EC_ESB_CLK_R 0_0402_5%~D 1 2 +3VALW_EC EC_RST# RE61 <53> +3VALW_EC RE55 47K_0402_5%~D EC_ESB_CLK 2 0.1U_0402_16V7K 1 RE47 1 D 2 1 2 RE44 0_0402_5% 67 EC_SMB_CK1 EC_SMB_DA1 KSO1 KSO2 EC_MUTE# EC_SMI# DEPOP# EC_ESB_CLK EC_ESB_DAT LID_SW_IN# EN_WOL# EAPD#_R 1000P_0402_50V7K 69 2.2K_0402_5%~D 2.2K_0402_5%~D 47K_0402_5%~D 47K_0402_5%~D 10K_0402_5%~D 1K_0402_1%~D 100K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 0.1U_0402_16V7K RE46 RE48 RE49 RE50 RE51 @ RE52 RE53 RE54 RE57 RE58 RE59 @ RE60 CE36 9 22 33 96 111 125 2 2 2 2 2 2 2 2 2 2 1 2 +3VALW_EC 2 EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC 1 1 1 1 1 1 1 1 1 1 2 1 1 RE37 +3VALW_EC GND/GND GND/GND GND/GND GND/GND GND0 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0_0805_1% 1 1 1 1 2 CE35 CE31 CE32 CE34 CE37 22P_0402_50V8J~D CE39 1 1 1 1 1 BKOFF# EC_SCI# M_THERMAL# EC_SMB_CK2 EC_SMB_DA2 EC_ESB_CLK LE3 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA @ 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 25 +3VALW RE36 RE38 RE42 RE43 RE45 KB930@ +3VS 60 mil A RE88 150K_0402_1%~D Compal Secret Data 1 Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. EC ENE-KB9012QF,KC3810 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 40 of 61 5 4 3 2 1 UL1 PCIE_PRX_GLANTX_P1_C 1 0.1U_0402_16V7K~D PCIE_PRX_GLANTX_N1_C 1 0.1U_0402_16V7K~D PCIE_PTX_GLANRX_P1 2 CL1 2 CL4 <20> PCIE_PRX_GLANTX_P1 <20> PCIE_PRX_GLANTX_N1 <20> PCIE_PTX_GLANRX_N1 2 <18> CLK_PCIE_LAN <18> CLK_PCIE_LAN# 2 RL12 <18> LANCLK_REQ# 1 PCIE_WAKE# <17,43,51> PCIE_WAKE# PCIE_WAKE# W=40mils RBIAS 1 +RBIAS 1 RL14 2 2.37K_0402_1%~D 1 W=20mils CL28 2 2 CL29 1 CL53 2 2 1U_0402_6.3V6K~D CL54 2 CL35 1 0.1U_0402_16V7K~D 2 1 CL41 1 0.1U_0402_16V7K~D 2 1 CL50 1U_0402_6.3V6K~D 2 1 CL25 W=20mils 1 2 1 CL30 2 1 CL31 2 1 CL32 2 +DVDDL 1 CL33 1 CL26 2 close to Lan pin34 close to Pin 16 C close to Lan pin19 2 close to Lan pin9 close to Lan pin13 1 CL34 2 1 CL39 close to Lan pin22 1 CL27 2 2 close to Lan pin37 RL19 1 S 1.5M_0402_5%~D 2 1 QL2 SSM3K7002FU_SC70-3 3 10 +AVDDH 1 1U_0402_6.3V6K~D 2 1 CL24 0.1U_0402_16V7K~D 2 1 CL23 close to Pin 1 D 2 G 40 24 E2201-BL3A-R_QFN40_5X5 close to Lan pin6 EN_WOL <53> <53> <53> <53> <53> <53> <53> <53> 2 15P_0402_50V8J~D 4 25MHZ_10PF_7V25000014 GND GND OSC OSC LED_0 LED_1 LED_2 LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 +AVDDL 10U_0603_6.3V6M~D 2 CL52 10U_0603_6.3V6M~D 2 2 1 CL22 0.1U_0402_16V7K~D G 1 D LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 RL29 5.1K_0402_1%~D 1A 2 0_0805_5%~D +DVDDL 37 11 12 14 15 17 18 20 21 close to Lan pin31 1000P_0402_50V7K~D RL16 1 RL17 470K_0402_5%~D 1 EN_WOL# PPS LAN_LINK#_R 1 1U_0402_6.3V6K~D D +LAN_IO_R +AVDDH W=20mils S 4 CL21 <43> LX ISOLAT# 38 39 23 +LAN_IO 6 5 2 1 +3VALW RL18 10K_0402_5%~D XTLI XTLO W=40mils 3 2 CL51 5 LAN_ACTIVITY# LAN_LINK#_R LAN_LED2#_R <53> LAN_ACTIVITY# <53> LAN_LINK#_R <53> LAN_LED2#_R 2 1 8 7 2 30K_0402_5% NC TESTMODE GND QL1 FDC655BN_NL_SSOT6~D +3VALW B+_BIAS 3 2 1 0_0402_5% 2 15P_0402_50V8J~D 1 YL1 2 1 RL13 +LAN_IO TRXP0 TRXN0 TRXP1 TRXN1 TRXP2 TRXN2 TRXP3 TRXN3 SMCLK SMDATA 28 27 41 XTLI XTLO 22 9 WAKE# 25 26 RL28 1 DVDDL_REG 3 RL15 CL20 1U_0402_6.3V6K~D PERST# CLKREQ_LAN#_R The pull-up resisters might not be necessory due to existence on PCH side. C AVDDH AVDDH_REG CLKREQ# 2 0.1U_0402_16V7K~D 1 RL11 REFCLK_N 1U_0402_6.3V6K~D RL10 D PLT_RST# REFCLK_P 4 1U_0402_6.3V6K~D 2 <6,17,43,51,53> AVDDL AVDDL AVDDL AVDDL AVDDL_REG RX_N 0.1U_0402_16V7K~D 2 4.7K_0402_5%~D PLT_RST# 32 RX_P +AVDDL 0.1U_0402_16V7K~D 4.7K_0402_5%~D 1 CLK_PCIE_LAN# +LAN_IO 13 19 31 34 6 0.1U_0402_16V7K~D 2 33 W=40mils 1 16 4.7U_0603_6.3V6K~D 4.7K_0402_5%~D 36 CLK_PCIE_LAN VDD33 AVDD33 TX_N 35 PCIE_PTX_GLANRX_N1 CLKREQ_LAN#_R 1 0_0402_5%~D PLT_RST# TX_P 29 0.1U_0402_16V7K~D 1 <20> PCIE_PTX_GLANRX_P1 RL7 0_0402_5%~D 30 0.1U_0402_16V7K~D +LAN_IO 1 2 CL36 0.1U_0402_25V6 B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 Deciphered Date 2013/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title GLAN AR8151 AL1A/ RJ45 Size 5 4 3 2 Document Number Rev 0.1 LA-9331P Date: Friday, June 22, 2012 Sheet 1 41 of 61 A B RA360 LINE2-VREFO 2 RA8 11 7 25 2 HDA_SDIN0_R 22_0402_5% 1 2 2 0_0402_5% CA15 1 1 2 1 8 4 5 9 6 1 29 30 24 21 35 40 41 38 CA19 2 1 1 + 2 2 2 1U_0402_6.3V6K~D CA22 1 1 2 10U_0805_10V4Z~D 2.2U_0402_6.3V6M~D 2 CA18 0.1U_0402_10V6K~D CA17 10U_0805_10V4Z~D 2 22P_0402_50V8J~D 1 RA6 23 39 PCBEEP HVDD LDO-IN LINE1-R LINE1-L LINE2-IN-R/SLEEVE LINE2-IN-L/RING2 CA12 DVDD DVDD-IO DVDD-IO-CP SDATA-IN SDATA-OUT BCLK SYNC RESETB MIC1-R MIC1-L/MIC-CAP MIC2-R MIC2-L 2 PC_BEEP HP1_A_R 1 HP1_A_R_L 2 RA77 0.1U_0402_10V6K~D 1 2 LA3 0_0603_5%~D 18_0402_5%~D HP1_A_R_C 1 SLEEVE RING2 37 36 48 47 MIC2-R MIC2-L 34 33 RA9 1 2 39.2K_0402_1% 1 HP1_A_L_L 2 RA5 HP1_A_R_L 10U_0805_10V4Z~D RA7 2100_0402_1% A1 1 2100_0402_1% A3 B1 1 MIC2-VREFO LINE2-VREFO MIC1-VREFO SENSE A SENSE B SURR-R SURR-L CEN LFE CBP CBN JDREF LDO-CAP VREF VRP FRONT-R FRONT-L SPDIF-OUT SPDIF-in GPIO/DMIC-CLK GPIO1/DMIC-DATA GPIO2/Combo-Jack1 GPIO3/Combo-Jack2 CPVREF AVSS1 AVSS2 Thermal PAD EAPD INT-SPK-R INT-SPK-L 15 16 I2S_DAT/SPDIF_IN GPIO3 EAPD# INR /MUTE 2 +3.3V_AVDD SET CA14 0.1U_0402_16V4Z~D <46> <46> DMIC_CLK DMIC0 Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) HPOUT-JD 2 DA11 3 AZ5125-02S.R7G_SOT23-3 Place close to Jack S2 (Out) :Center + HP2 <37> RA78 HP2_D_L 1 LA4 0_0603_5%~D 1 2 18_0402_5%~D HP2_D_L_R 2 1 CA63 2 LA5 0_0603_5%~D 1 2 18_0402_5%~D HP2_D_R_R 2 GND AGND HP2_D_L_R RA15 1 2 100_0402_1% A1 HP2_D_R_R RA16 1 2 100_0402_1% A3 B1 HP_MUTE# 2 1 1 2 1 2 CA35 10U_0603_6.3V6M~D 2 CA37 0.1U_0402_10V6K~D 2 1 CA59 0.1U_0402_10V6K~D 1 CA31 10U_0603_6.3V6M~D 2 CA30 0.1U_0402_10V6K~D 2 CA29 0.1U_0402_10V6K~D 2 CA28 0.1U_0402_10V6K~D CA27 0.1U_0402_10V6K~D 2 3 1 S3 (Out) : Rear L/R SET SPK_MUTE# EC_MUTE# <43> MIC2-L 1 2 CA21 LINE_B_L_R 4.7U_0805_25V6-K HP2_D_L1_JK 3 HP2_D_R1_JK Place close to Jack DA12 B2 2 HPOUT2-JD 3 MIC_B_PLUG# A2 AZ5125-02S.R7G_SOT23-3 RA362 @ 1 JHP3 75_0402_1%~D 1 2 LINE_B_L_RR LA6 0_0603_5%~D 1 2 6 1 2 LINEIN_B_L_C 100P_0402_50V8J~D 1 1 <46> SPK_MUTE# 2 1 RA802.2K_0402_5%~D EC_MUTE# 3 EAPD# CA64 2 1 CA24 2 LINE_B_R_R 4.7U_0805_25V6-K 2 LINE_B_R_RR 1 1 RA81 75_0402_1%~D 1 2 LA7 0_0603_5%~D RA363 @ MIC2-VREFO-R 2 1 1 CA65 2 2.2K_0402_5%~D 1 CA38 BEEP_C# 2 0.1U_0402_16V4Z~D 1 RA59 2 100K_0402_5%~D <16> HDA_SPKR 1 CA39 PCH_SPKR_C 2 0.1U_0402_16V4Z~D RA61 2 1 100K_0402_5%~D RA60 0_0402_5%~D 1 2 DA3 UA7 2 0.1U_0402_16V4Z~D 1 RA82 2 100K_0402_5%~D +3V_DVDD LINE_B_L_R RA54 1 2 100_0402_1% A1 LINE_B_R_R HP_MUTE# RA55 1 1 RA57 2 100_0402_1% A3 2 DEPOP#_R B1 0_0402_5% MAX9892ERT+T_UCSP6~D +3.3V_AVDD 1 HP_MUTE# 2 GPIO3 DEPOP# <43> 1 4 1 B3 VDD SET Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) Place close to Jack B2 GND 2 DEPOP# LINEIN_B_R_C AZ5125-02S.R7G_SOT23-3 INR /MUTE CA40 0.1U_0402_16V4Z~D 3 LINEIN_B_L_C 3 A2 RA17 10K_0402_1% DA10 2 1 INL 2 1 CA58 1 RA62 @ 10K_0402_5%~D <37> HDMI_IN_AUDIO_CODEC 7 8 PC_BEEP 2 BEEP# <43> G C-H_13-18200610CP CONN@ LINEIN_B_R_C 100P_0402_50V8J~D MIC2-R G 5 2 2 3 3 4 MIC_B_PLUG# RA13 10K_0402_1% 2 DA7 1 +3.3V_AVDD VDD MIC2-VREFO-L 2 DA9 BAT54CW_SOT323-3 7 8 AZ5125-02S.R7G_SOT23-3 INR /MUTE Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) +3.3V_AVDD G C-H_13-18200610CP CONN@ MAX9892ERT+T_UCSP6~D CA25 0.1U_0402_16V4Z~D +3V_DVDD G 5 INL B3 3 4 HPOUT2-JD HP2_D_R1_JK 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K UA3 JHP2 6 1 2 HP2_D_L1_JK GND AGND HPOUT-JD 2 1 GND SLEEVE Place close to Jack 5.1K_0402_1% <33,42> <33,42> CA68 1 CA69 1 CA70 1 CA71 1 HP1_A_R_C 3 1 <43> 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D 2 AZ5125-02S.R7G_SOT23-3 2 RA44 1 RA45 1 RA47 1 RA48 1 DA8 B2 VDD B3 1 MAX9892ERT+T_UCSP6~D 44 43 14 HPOUT2-JD RA12 1 12 13 17 3 2 10K_0402_1% HP1_A_R HP1_A_L HP2_D_L HP2_D_R HP1_A_L_C 1 1 27 26 19 18 RING2 3 Place close to Jack RA11 MIC_B_PLUG# 2 AZ5125-02S.R7G_SOT23-3 INL CA62 1 DA6 1 UA2 CA13 7 8 1 ALC3661-CG_MQFN48_6X6~D 1 G C-H_13-18200610CP CONN@ CA60 2 100P_0402_50V8J~D RA361 LINE2-VREFO 2 1 HP_MUTE# CA23 49 46 45 32 31 RA79 HP2_D_R 1 1 G 5 2.2K_0402_5%~D CA20 100U_B3_6.3VM_R55M 20 CPVEE 10 REGREF 28 22 42 2 CA5 1 100P_0402_50V8J~D CA11 2 MIC2-VREFO-L LINE2-VREFO MIC2-VREFO-R 1 3 4 HPOUT-JD 100P_0402_50V8J~D 100P_0402_50V8J~D 1 20K_0402_1%~D RA14 6 1 2 HP1_A_L_C UA1 CA10 2 1U_0402_6.3V6K~D 2 JHP1 SLEEVE RING2 LA2 0_0603_5%~D 1 2 18_0402_5%~D HP1_A_L_L 2 1 1 CA16 1 2.2K_0402_5%~D RA76 HP1_A_L 1 +3V_DVDD <16> PCH_AZ_CODEC_SDIN0 <16> PCH_AZ_CODEC_SDOUT <16> PCH_AZ_CODEC_BITCLK <16> PCH_AZ_CODEC_SYNC <16> PCH_AZ_CODEC_RST# 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 1 1 GND 2 H 2 1 1 G S1 (Out + In) : Front L/R + HP1 + MIC (auto-sense) A2 1 FBMA-L11-201209-221LMA30T_0805 CA9 1 F +3.3V_AVDD RA2 RA3 RA4 CA1 4.7U_0805_25V6-K 2 CA2 0.1U_0402_10V6K~D 1 E +3V_DVDD CA61 0.1U_0402_10V6K~D CA8 2 1 10U_0805_10V4Z~D 0.1U_0402_10V6K~D LA1 +3V_DVDD 1 CA4 2 2 2 2 0.1U_0402_10V6K~D 10U_0805_10V4Z~D CA3 1 D 1 2 0_0805_5%~D +3V_DVDD 4.7U_0805_25V6-K 0.1U_0402_10V6K~D 1 RA1 C Close to Pin39 +5VS 2 +3V_DVDD +3VS 4 BAT54AW_SOT323-3~D Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. HD Audio ALC3661 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D E F G Friday, June 22, 2012 Sheet 42 H of 61 5 4 UA8 LA11 HCB2012KF-121T50_0805 1 2 SPK_R2+_CONN RA75 100K_0402_1% 1 0 32dB 15Kohm 1 1 36dB 9Kohm 1 RA83 2 0_0402_5% 2 13 29 GAIN1 SD# PLIMIT PLIMIT GVDD 9 +GVDD PGND PGND AGND 24 19 8 FAULT# NC GND Speaker amp impedance of JBL is 4 ohm. Speaker Connector +GVDD RA70 10K_0402_1% 1 2 RA364 1 1 2 1 2 +AVCC 2 10_0402_5%~D 2 1 2 DA4 DA5 1 2 3 4 GND GND ACES_50279-0040N-001 CONN@ C CA72 10U_0603_6.3V6M~D 1 1 2 3 4 5 6 TPA3113D2PWPR_HTSSOP28 B+ JSPK1 15 mils trace SPK_L1-_CONN SPK_L2+_CONN SPK_R1-_CONN SPK_R2+_CONN 3 1 10 RA67 28.7K_0402_1% 2 EAPD_R 14 3 6 PBTL 2 GIN1 GAIN0 1 30Kohm 5 AZ5125-02S.R7G_SOT23-3 26dB 2 1 1 1 AZ5125-02S.R7G_SOT23-3 0 +GVDD BSNR CA55 0.22U_0603_25V7K GIN0 SPK_R1-_CONN 5A/120ohm/100MHz OUTNR 20 21 OUTNR OUTPR CA32 GIN1 2 D LA12 HCB2012KF-121T50_0805 1 2 1000P_0402_50V7K 60Kohm 1 CA52 0.22U_0603_25V7K CA33 BSNR BSPR 5A/120ohm/100MHz CA49 0.22U_0603_25V7K 1000P_0402_50V7K 20dB 2 1000P_0402_50V7K 1 0 1 1 RA74 100K_0402_1% INPUT IMPEDANCE 0 18 OUTNR 2 2 2 1 2 2 1 GIN0 @ RA73 100K_0402_1% AV(inv) 1 CA56 1U_0603_25V6K C @ RA72 100K_0402_1% GAIN0 17 RINP RA69 0_0402_5% 2 RA71 100K_0402_5% GAIN1 BSNL CA57 1U_0603_25V6K +5VS OUTPR CA54 1 <45> SPK_MUTE# BSPR OUTPR 2 11 0.027U_0402_16V6K RINN RA68 100K_0402_5% @ 1 2 @ +3VALW TPA3113 for Speaker CA51 1 22 BSNL 4 2 0.027U_0402_16V6K LINN CA53 1 2 0.027U_0402_16V6K AMP_RIGHT_C 12 OUTNL LINP @ RA66 10K_0402_5% 2 470P_0402_50V7K~D SPK_L1-_CONN 5A/120ohm/100MHz CA34 2 240K_0402_1% 23 OUTNL OUTNL CA36 1 OUTPL 1000P_0402_50V7K RA65 SPK_CD_R OUTPL 25 1 2 2 1 CA48 0.22U_0603_25V7K 2 26 1 1 RA64 10K_0402_5% 3 PVCCR PVCCR PVCCL PVCCL BSPL BSPL 2 470P_0402_50V7K~D CA50 1 2 0.027U_0402_16V6K AMP_LEFT_C AVCC 1 15 16 27 28 1 7 +PVDD 1 240K_0402_1% CA66 <45> INT-SPK-R 2 1 1 SPK_L2+_CONN LA10 HCB2012KF-121T50_0805 1 2 2 +AVCC 2 RA63 SPK_CD_L 2 2 1 <45> INT-SPK-L 1 D 1 LA9 HCB2012KF-121T50_0805 1 2 5A/120ohm/100MHz Close to UA2 Pin7,15,16,27,28 CA67 2 OUTPL 1U_0603_25V6K CA47 1U_0603_25V6K CA46 2 1 2 CA42 0.1U_0402_25V6K~D 3 40mil +PVDD 1U_0603_25V6K CA45 2 1 2 1 CA41 10U_1206_25V6M 1 2 1 1U_0603_25V6K CA44 2 1 B+ 1U_0603_25V6K CA43 2 1 LA8 FBMA-L11-160808-121LMA30T_0805 1 2 B B A A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Speaker AMP/CardReaser B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 43 of 61 5 4 3 2 1 +3.3V_F347 D <20> <20> 2 0_0603_5%~D +3.3V_F347 9 10 18 17 16 15 14 13 12 11 +3.3V_F347 4.7K_0402_5%~D 2 1 R2 C15 C16 C17 C18 1 1 1 1 1 1 2 2 2 2 2 2 2 2 VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 D+ DREGIN VBUS RST#/C2CK P3.0/C2D P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 GND 2 1 32 31 30 29 28 27 I2C_CLK 4.7K_0402_5%~D 2 1 R3 26 25 24 23 22 21 20 19 C5 C8 C9 SPI_MOCLK SPI_MOCLK_R 1 2 SPI_MOSO R4 0_0402_5%~D SPI_MOSI SPI_MOCS# I2C_DAT I2C_DAT <48,53> I2C_CLK I2C_CLK <48,53> @ 1 2 0.1U_0402_16V4Z~D R7 1 2 1K_0402_5%~D +3.3V_F347 SLP_S3 BATT_CHG_LED 10K_0402_5% 2 1 R9 +3.3V_F347 ACIN# LID_SW_IN#_D LID_SW_IN# 2 1 LID_SW_IN# BATT_LOW_LED D70 SLP_S5 SDMK0340L-7-F_SOD323-2~D @ 1 2 0.1U_0402_16V4Z~D @ 1 0.1U_0402_16V4Z~D 2 <19,43,48,53> 3 C8051F347-GQ_LQFP32_7X7 @ C14 1 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D Cloase to JP1 1 0.1U_0402_16V4Z~D CONN@ GND1 GND2 C13 1 2 3 4 5 6 1 2 3 4 5 6 C12 C 2 R8 1K_0402_1%~D C11 2 1 JP1 C10 0.1U_0402_16V4Z 1 4 5 7 8 @ +3.3V_F347 I2C_DAT U1 USB20_P6 USB20_N6 @ 2 +3.3V_F347 place R1564 as close as U602 +3.3V_F347 @ 2 1 C7 0.1U_0402_16V4Z~D C6 1U_0805_10V7 1 1 USB20_P6 USB20_N6 W=40mils 2 0_0603_5%~D @ @ @ 1 2 6 @ 1 R6 2 @ +5VS R5 2 1 C2 22P_0402_50V8J~D +5VALW 1 C4 0.1U_0402_16V4Z~D 2 C3 1U_0805_10V7 1 D 20_0603_5%~D +3.3V_F347_R 1 C1 0.1U_0402_16V4Z~D R1 We are Green SA00003IR20 U2 SPI_MOSI 15_0402_5% 2 1 R10 5 SPI_MOCLK_R 15_0402_5% 2 1 R12 6 DI +3.3V_F347 7 8 AMPHE_G846A06201EU 1 2 1 2 1 2 SPI_MOCS# 10K_0402_5%~D R13 3 C20 22P_0402_50V8J~D 2 8 C19 0.1U_0402_16V4Z~D 1 1 2 SPI_MOSO C WP 10K_0402_5%~D +3.3V_F347 2 15_0402_5% 1 HOLD 10K_0402_5%~D R15 R11 CS 7 R14 2 SO CLK 1 VCC 4 VSS EN25Q80A-100HIP_SO8 1 +3.3V_F347 DEVICE MAXIM - LED MAXIM - GPIO I2C EEPROM 1 1 +3.3V_F347 +3VALW J11 @ 2 2 G 1 3 B+_BIAS 3 1 +3VALW 1 +3.3V_F347 2 2 <43> BATT_CHG_LED# Q8 SSM3K7002F_SC59-3~D 2 G S D 3 <43> 3V_F347_ON 1 2 G S Q7 3 SSM3K7002F_SC59-3~D 2 G 1 Q6 SSM3K7002F_SC59-3~D S BATT_CHG_LED 1 1 2 G R25 100K_0402_1%~D D <43> BATT_LOW_LED# BATT_LOW_LED S 2 +3.3V_F347 behavior STATE S0 S3 S4 S5 1 2 AC IN ON ON ON ON BAT only ON ON OFF OFF AC mode battery full in S5:turn off ELC controller 3 2 1 D R24 100K_0402_1%~D 2 2 +3.3V_F347 1 1 C23 0.1U_0402_25V6K~D D R23 300K_0402_5%~D R22 100K_0402_1%~D Q5 SSM3K7002F_SC59-3~D R21 100K_0402_1%~D R20 100K_0402_1%~D 1 2 1 1 2 1 2 G S 3 4 C22 4.7U_0603_6.3V6M~D <17,29,43,57,63> ACIN 6 5 2 1 ACIN# Q4 SSM3K7002F_SC59-3~D B SI3456DDV-T1-GE3_TSOP6~D R19 100K_0402_1%~D D Q3 Q2 SSM3K7002F_SC59-3~D S 1 C21 0.1U_0402_25V6K~D R18 100K_0402_1%~D 1 JUMP_43X118 1 2 G <17,43> PM_SLP_S5# SLP_S5 2 2 D +3.3V_F347 B ADDRESS 000b 001b 000b +3.3V_F347 R17 100K_0402_1%~D 3 2 S 1 Q1 SSM3K7002F_SC59-3~D 2 G SMBUS 0100 0100 1010 D D <17,43> PM_SLP_S3# SLP_S3 S 2 R16 100K_0402_1%~D 3 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. ELC (1) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 44 of 61 5 4 3 2 1 L/R Tron, Logo, Alien Head, TP <53> 7313_INT# +3.3V_F347 D D +3.3V_F347 1 1 U3 22 2 <47,53> I2C_CLK <47,53> I2C_DAT I2C_CLK I2C_DAT 1 2 2 1 R29 4.7K_0402_1%~D 4.7K_0402_1%~D R28 AD0_0 AD0_1 AD0_2 <53> TP_LED_R_DRV# <53> TP_LED_G_DRV# <53> TP_LED_B_DRV# SCL SDA 18 23 24 P12 P13 P14 OSC 9 GND LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV# ALIEN_LED_R_DRV#_1 ALIEN_LED_G_DRV#_1 ALIEN_LED_B_DRV#_1 LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# 1 2 3 4 5 6 7 8 10 11 12 13 25 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND AD0 AD1 AD2 TP_LED_R_DRV# 14 TP_LED_G_DRV# 15 TP_LED_B_DRV# 16 17 2 21 INT#/O16 V+ 19 20 C24 0.1U_0402_16V4Z~D 4.7K_0402_1%~D R27 1 R26 2 4.7K_0402_1%~D RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV# <53> <53> <53> MAX7313DATG+T_TQFN-EP24_4X4~D +3.3V_F347 +3.3V_F347 1 2 1 1 2 2 19 20 AD2_0 AD2_1 AD2_2 18 23 24 HDD_R_7313# HDD_G_7313# HDD_B_7313# 14 15 16 17 9 INT#/O16 V+ SCL SDA P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND AD0 AD1 AD2 P12 P13 P14 OSC GND 21 1 2 3 4 5 6 7 8 10 11 12 13 25 +5VS 1 LED_R_7313#_1 LED_G_7313#_1 LED_B_7313#_1 PWR_R_7313# PWR_G_7313# PWR_B_7313# LED_R_7313#_1 <53> LED_G_7313#_1 <53> LED_B_7313#_1 <53> 2 HDD_B HDD_B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LID_SW LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# PWR_R_7313# <53> PWR_G_7313# <53> PWR_B_7313# <53> ALIEN_LED_R_DRV#_1 ALIEN_LED_G_DRV#_1 ALIEN_LED_B_DRV#_1 MAX7313DATG+T_TQFN-EP24_4X4~D D C +5VS 20mil <53> 1 JLOGO1 1 1 2 3 4 5 6 7 8 9 10 11 12 G1 G2 2 C27 0.1U_0402_16V4Z R33 4.7K_0402_1%~D 1 C I2C_CLK I2C_DAT C26 0.1U_0402_16V4Z 2 2 U4 22 7313_INT# C25 0.1U_0402_16V4Z 4.7K_0402_1%~D R32 4.7K_0402_1%~D R31 4.7K_0402_1%~D R30 1 Indicator, Power ACES_50224-0120N-001 CONN@ S +5VS LOGO Board CONN 3 D D 1 <19,43,47,53> LID_SW_IN# D 3 3 <43> EN_TPLED# MAX7313 D U605 0 1 0 U608 0 1 1 Power Button, Media and Status LED Color U? 1 0 0 Button, Indicator Brightness Q16 SSM3K7002F_SC59-3~D S S 1 LID_SW 2 G Tron Lights,TP A-panel,B-Panel Logo 2 G Q15 D G 2 1 2 C33 0.1U_0402_25V6K~D AD0 2 R37 1.5M_0402_5%~D AD1 1 EN_TPLED SATA_LED_ACT AD2 +5VS S Q13 SSM3K7002F_SC59-3~D S HDD_G_7313# Reference <53> SSM3K7002FU_SC70-3~D S LID_SW 1 2 G Q14 SSM3K7002F_SC59-3~D 2 G Q11 +5VS_TP_LED SI3456DDV-T1-GE3_TSOP6~D 6 5 4 2 1 1 3 <53> 1 HDD_G 3 HDD_G +5VS 1 LID_SW B+_BIAS 1 2 C30 0.1U_0402_16V4Z HDD_R_7313# 1 3 2 Q10 SSM3K7002F_SC59-3~D S 2 1 1 2 G 2 2 D SATA_LED_ACT C32 1U_0603_10V4Z~D 3 +5VALW 0.1U_0402_16V4Z C29 S <53> R36 300K_0402_5%~D <16> PCH_SATALED# HDD_R R35 100K_0402_5%~D 2 G TRON LED Board (F) CONN HDD_R Q12 SSM3K7002F_SC59-3~D B R34 100K_0402_5%~D 1 HDD_B_7313# 1 1 2 3 4 5 6 7 8 9 10 GND1 GND2 ACES_50224-01001-001 CONN@ Q9 SSM3K7002F_SC59-3~D 2 G D JTRONF 1 2 3 4 5 6 7 8 9 10 11 12 RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV# LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# B JTRONL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 GND GND E-T_4260-F06N-10L CONN@ Touchpad LED circuit TRON LED Board (L) CONN 3 A A Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. ELC (2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 45 of 61 A B C D E 1 1 +3VS +5VS Close to JHDD1 +3VS 2 1 2 2 1 CN59 47P_0402_50V8J~D 1 CN5 10U_0805_10V4Z~D 2 CN3 0.1U_0402_16V4Z~D <6,12,13,14,15,19,50,51,53> PCH_SMBDATA <6,12,13,14,15,19,50,51,53> PCH_SMBCLK 1 UN4 LNG3DM 1 14 <17> FFS_INT1 <21,50> FFS_INT2 2 CN4 1U_0402_6.3V4Z~D 2 1 CN2 1000P_0402_50V7K~D 2 1 CN1 0.1U_0402_16V4Z~D 1 C35 10U_0805_10V4Z~D 2 C34 0.1U_0402_16V4Z~D 1 Free Fall Sensor FFS_INT1 FFS_INT2 11 9 PCH_SMBDATA PCH_SMBCLK 7 6 4 VDD_IO VDD INT 1 INT 2 RES RES RES RES GND GND SDO/SA0 SDA / SDI / SDO SCL/SPC NC CS NC 8 10 13 15 16 JHDD1 5 12 <16> SATA_PTX_DRX_P0 <16> SATA_PTX_DRX_N0 <16> SATA_PRX_DTX_N0 <16> SATA_PRX_DTX_P0 2 3 CN6 CN7 1 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C SATA_PTX_DRX_N0_C CN8 CN9 1 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C SATA_PRX_DTX_P0_C 1 2 3 4 5 6 7 GND A+ AGND BB+ GND LNG3DMTR_LGA16_3X3~D FFS_INT1 connect to PCH GPIO & EC discuss with BIOS to use which pin +3VS 2 <21> HDD_DET# +5VS FFS_INT2_CONN <50> FFS_INT2_CONN 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND DAS/DSS GND VCC12 VCC12 VCC12 2 G1 G2 23 24 FOX_LD2822F-SAQL6 CONN@ Close to JHDD2 +3VS +5VS +3VS +3VS RN2 RN3 1 1 @ @ HDD_B_PRE1 17 2 0_0402_5% HDD_A_PRE1 19 2 0_0402_5% RN4 1 @ 2 0_0402_5% 18 3 13 21 B_PRE1 A_PRE1 TEST GND GND EPAD A_PRE0 B_PRE0 A_OUTp A_OUTn B_INp B_INn 1 1 1 2 2 1 2 2 1 2 1 2 NC REXT B_OUTp B_OUTn 2 CN60 47P_0402_50V8J~D 5 4 1 CN14 10U_0805_10V4Z~D SATA_PRX_DTX_P1_RC SATA_PRX_DTX_N1_RC 2 CN13 1U_0402_6.3V4Z~D 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 1 CN12 0.1U_0402_16V4Z~D CN18 1 CN17 1 VDD VDD A_INp A_INn 2 CN11 1000P_0402_50V7K~D <16> SATA_PRX_DTX_P1 <16> SATA_PRX_DTX_N1 3 EN @ 1 RN7 1 2 RN6 SATA_PTX_DRX_P1_R SATA_PTX_DRX_N1_R @ 0_0402_5% 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D RN46 7 CN15 1 CN16 1 @ 0_0402_5% 1 <16> SATA_PTX_DRX_P1 <16> SATA_PTX_DRX_N1 RN5 2 0_0402_5% 0_0402_5% UN1 RN1 2 0_0402_5% 2 CN24 0.1U_0402_25V6K CN23 0.01U_0402_16V7K 2 +3VS 1 CN10 0.1U_0402_16V4Z~D 1 1 JHDD2 6 16 10 20 HDD_REXT_SATA SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C 9 8 HDD_A_PRE0 HDD_B_PRE0 SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C 15 14 SATA_PTX_DRX_P1_RC CN19 1 SATA_PTX_DRX_N1_RC CN20 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C 11 12 SATA_PRX_DTX_P1_R SATA_PRX_DTX_N1_R 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P1_C SATA_PRX_DTX_N1_C CN21 1 CN22 1 +3VS PS8520BTQFN20GTR2_TQFN20_4X4 +5VS Pin 20: PARADE PS8250B: Reserve RN46, Mount RN12 Pin 9: PARADE PS8250B: Reserve RN11. PERICOM PI3EQX6741ST: Mount RN46, Reserve RN12 PERICOM PI3EQX6741ST: Reserve RN11 ASMEDIA ASM1466: Mount RN46, Reserve RN12 ASMEDIA ASM1466: Mount RN11 to pull down HDD_B_PRE0 RN8 1 @ 2 0_0402_5% HDD_B_PRE1 RN9 1 @ 2 0_0402_5% HDD_A_PRE1 RN10 1 @ 2 0_0402_5% HDD_A_PRE0 RN11 1 HDD_REXT_SATA RN12 1 FFS_INT2_CONN 2 2K_0402_5% 2 5.1K_0402_1% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND A+ AGND BB+ GND 3 VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND DAS/DSS GND VCC12 VCC12 VCC12 G1 G2 23 24 FOX_LD2822F-SAQL6 CONN@ 4 4 Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. SATA HDD1 & HDD2/FFS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 46 of 61 A B C D E ODD_DA#_R D S G ODD_EN 2 3 JODD1 1, Host generate Low pulse 40ms to eject ODD 2, After this pulse, signal remain high and no pulse is allowed within 7s 2 SATA_PRX_DTX_P2_C SATA_PRX_DTX_N2_C SATA_PRX_DTX_P2_R SATA_PRX_DTX_N2_R 5 4 +3VS RN14 1 RN15 1 @ @ ODD_B_PRE1 17 2 0_0402_5% ODD_A_PRE1 19 2 0_0402_5% RN16 1 @ 2 0_0402_5% 18 3 13 21 B_PRE1 A_PRE1 NC REXT A_PRE0 B_PRE0 A_OUTp A_OUTn TEST GND GND EPAD B_INp B_INn +5VS FFS_INT2_CONN 2 SDM10U45-7_SOD523-2~D FFS_INT2_CONN <49> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 21 22 23 24 GND1 GND2 GND3 GND4 E-T_0870K-F20C-22L CONN@ 1 1 1 2 B_OUTp B_OUTn FFS_INT2_CONN <49> FFS_INT2_CONN 2 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 1 DN1 @ RN20 1 1 VDD VDD A_INp A_INn RN19 CN25 CN26 EN @ 0_0402_5% 1 2 D SATA_PTX_DRX_P2_R SATA_PTX_DRX_N2_R 1 ODD_DA#_R SATA_PTX_DRX_N2_C SATA_PTX_DRX_P2_C G 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D @ RN18 <16> SATA_ODD_PRX_DTX_P2 <16> SATA_ODD_PRX_DTX_N2 7 1 1 3 0_0402_5% UN2 2 0_0402_5% CN27 CN28 FFS_INT2 0_0402_5% 2 RN17 +3VS 1 0_0402_5% 2 CN34 0.1U_0402_25V6K 1 CN33 0.01U_0402_16V7K ODD Redriver RN13 1 2 0_0402_5%~D QN3 SSM3K7002FU_SC70-3~D +3VS <16> SATA_ODD_PTX_DRX_P2 <16> SATA_ODD_PTX_DRX_N2 RN45 1 <21> ODD_DETECT# @ RN28 100K_0402_5%~D S <21,49> FFS_INT2 2 <17> ODD_DA# 1 +3VS 2 2 +5VS_ODD +5VS 2 1 QN1 SSM3K7002FU_SC70-3~D 1 S +3VS 1 2 1 3 2 1 QN4 2N7002E-T1-E3_SOT23-3 Placea caps. near ODD CONN. RN27 1.5M_0402_5%~D S 2 G ODD_EN# 2 1 CN40 0.1U_0402_25V6K~D <21> D 1 2 1 2 2 3 2 RN26 300K_0402_5%~D 1 4 CN38 10U_0805_10V4Z~D 1 6 5 2 1 CN37 1U_0402_6.3V4Z~D 1 CN39 1U_0402_6.3V6K~D B+_BIAS SATA ODD Conn. D 2 G <43> ODD_EJECT# QN2 +5VS_ODD SI3456DDV-T1-GE3_TSOP6~D CN36 0.1U_0402_16V4Z~D +5VS CN35 1000P_0402_50V7K~D ODD power 1 +5VS_ODD 6 16 ODD_B_PRE0 RN21 1 @ 2 0_0402_5% ODD_B_PRE1 RN22 1 @ 2 0_0402_5% ODD_A_PRE1 RN23 1 @ 2 0_0402_5% ODD_A_PRE0 RN24 1 ODD_REXT_SATA RN25 1 10 20 ODD_REXT_SATA 9 8 ODD_A_PRE0 ODD_B_PRE0 15 14 SATA_PTX_DRX_P2_RC CN29 1 SATA_PTX_DRX_N2_RC CN30 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P2_C SATA_PTX_DRX_N2_C 11 12 SATA_PRX_DTX_P2_RC CN31 1 SATA_PRX_DTX_N2_RC CN32 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P2_C SATA_PRX_DTX_N2_C 2 2K_0402_5% 2 5.1K_0402_1% Pin 20: PARADE PS8250B: Reserve RN18, Mount RN25 Pin 9: PARADE PS8250B: Reserve RN24. PERICOM PI3EQX6741ST: Mount RN18, Reserve RN25 PERICOM PI3EQX6741ST: Reserve RN24 ASMEDIA ASM1466: Mount RN18, Reserve RN25 ASMEDIA ASM1466: Mount RN24 to pull down 2 PS8520BTQFN20GTR2_TQFN20_4X4 +3VS +3VS mSATA_B_PRE1 17 2 0_0402_5% mSATA_A_PRE1 2 0_0402_5% 19 RN33 1 @ 2 0_0402_5% 18 3 13 21 TEST GND GND EPAD A_PRE0 B_PRE0 A_OUTp A_OUTn B_INp B_INn +3VS +1.5VS 1 PAD~D PAD~D T62 @ T63 @ PAD~D PAD~D T61 @ T59 @ 2 1 2 1 2 1 2 B_PRE1 A_PRE1 +3VS 10 20 mSATA_REXT_SATA 9 8 mSATA_A_PRE0 mSATA_B_PRE0 15 14 SATA_PTX_DRX_P3_RC CN45 1 SATA_PTX_DRX_N3_RC CN46 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P3_C SATA_PTX_DRX_N3_C 11 12 SATA_PRX_DTX_P3_RC CN47 1 SATA_PRX_DTX_N3_RC CN48 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P3_C SATA_PRX_DTX_N3_C 1 2 1 2 1 2 1 2 CN58 10U_0805_10V4Z~D @ @ 2 CN54 10U_0805_10V4Z~D RN31 1 RN32 1 B_OUTp B_OUTn 1 +1.5VS 6 16 CN57 1U_0402_6.3V4Z~D +3VS 5 4 NC REXT 2 SATA_PRX_DTX_P3_C SATA_PRX_DTX_N3_C SATA_PTX_DRX_N3_C SATA_PTX_DRX_P3_C Placea caps. near JP2 CONN. PS8520BTQFN20GTR2_TQFN20_4X4 RN43 1 RN44 1 PAD~D T65 PAD~D T64 2 0_0402_5%~D 2 0_0402_5%~D @ @ EC_TX_DAT EC_RX_CLK Pin 9: PARADE PS8250B: Reserve RN41. PERICOM PI3EQX6741ST: Mount RN35, Reserve RN42 PERICOM PI3EQX6741ST: Reserve RN41 ASMEDIA ASM1466: Mount RN35, Reserve RN42 ASMEDIA ASM1466: Mount RN41 to pull down @ 2 0_0402_5% mSATA_B_PRE1 RN39 1 @ 2 0_0402_5% mSATA_A_PRE1 RN40 1 @ 2 0_0402_5% mSATA_A_PRE0 RN41 1 mSATA_REXT_SATA RN42 1 RN47 100K_0402_5%~D 4 Pin 20: PARADE PS8250B: Reserve RN35, Mount RN42 RN38 1 1 2 <43> E51TXD_P80DATA <43> E51RXD_P80CLK mSATA_B_PRE0 3 JP2 CN56 0.1U_0402_16V4Z~D SATA_PRX_DTX_P3_R SATA_PRX_DTX_N3_R VDD VDD A_INp A_INn 1 Placea caps. near JP2 CONN. CN55 1000P_0402_50V7K~D 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D EN 2 @ RN37 1 1 1 2 RN36 SATA_PTX_DRX_P3_R SATA_PTX_DRX_N3_R @ 0_0402_5% 7 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D RN35 CN43 CN44 2 0_0402_5% 1 1 @ 0_0402_5% <16> MSATA_PRX_DTX_P3 <16> MSATA_PRX_DTX_N3 CN41 CN42 RN34 UN3 RN30 1 <16> MSATA_PTX_DRX_P3 <16> MSATA_PTX_DRX_N3 0_0402_5% 2 0_0402_5% 2 +3VS 1 CN50 0.1U_0402_25V6K 3 CN49 0.01U_0402_16V7K 1 1 CN53 1U_0402_6.3V4Z~D m-SATA Re-Driver 2 CN52 0.1U_0402_16V4Z~D CN51 1000P_0402_50V7K~D 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 PCH_SMBCLK PCH_SMBDATA PCH_SMBCLK <6,12,13,14,15,19,49,51,53> PCH_SMBDATA <6,12,13,14,15,19,49,51,53> 54 BELLW_80003-4041 CONN@ 2 2K_0402_5% 2 5.1K_0402_1% 4 Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. SATA ODD/mSATA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 47 of 61 A B C +1.5VS 1 1 2 1 2 1 2 2 1 C64 47P_0402_50V8J~D 2 C41 0.1U_0402_16V4Z~D 2 C40 0.1U_0402_16V4Z~D 1 C39 4.7U_0805_10V4Z~D 2 C63 47P_0402_50V8J~D 1 C38 0.1U_0402_16V4Z~D 2 C37 0.1U_0402_16V4Z~D WLAN E +3VS C36 4.7U_0805_10V4Z~D 1 1 D 1 JMINI1 PCIE_WAKE# COEX2 COEX1 @ RE12 1 2 0_0402_5%~D R38 1 2 0_0402_5%~D R39 1 2 0_0402_5%~D MINI1CLK_REQ# 1 3 5 7 <18> MINI1CLK_REQ# 9 CLK_PCIE_MINI1# 11 <18> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 <18> CLK_PCIE_MINI1 15 RE32 1 0_0402_5%~D 17 2 <6,17,43,44,53> PLT_RST# 19 <18> CLK_DEBUG 21 PCIE_PRX_WLANTX_N1 23 <16> PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 25 <16> PCIE_PRX_WLANTX_P1 27 C59 0.1U_0402_10V7K~D 29 PCIE_PTX_WLANRX_N1_C 31 1 2 <16> PCIE_PTX_WLANRX_N1 PCIE_PTX_WLANRX_P1_C 1 2 33 <16> PCIE_PTX_WLANRX_P1 35 C60 0.1U_0402_10V7K~D 37 39 +3VS 41 43 45 47 49 BT_ON# BT_ON#_R 1 2 51 <17> BT_ON# 1K_0402_1%~D RE119 53 <17,43,44> PCIE_WAKE# WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VS RE31 RE26 RE27 RE28 RE29 1 1 1 1 1 +1.5VS 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D LPC_FRAME# <19,43> LPC_AD3 <19,43> LPC_AD2 <19,43> LPC_AD1 <19,43> LPC_AD0 <19,43> WL_OFF# PLT_RST# WL_OFF# PLT_RST# WiGi_RADIO_DIS#_R RE22 1 2 0_0402_5%~D WiGi_RADIO_DIS# <21> USB20_N4 USB20_P4 USB20_N4 USB20_P4 @ WiGi_RADIO_DIS#_R 54 <17> <6,17,43,44,53> 2 <20> <20> D3 1 WiGi_RADIO_DIS# 2 2 SDMK0340L-7-F BELLW_80003-4041 CONN@ Display Mini Card (DMC) +1.5VS +3VS 1 1 C62 0.1U_0402_10V7K~D 2 PCIE_PTX_WANRX_N2_C 2 PCIE_PTX_WANRX_P2_C 0.1U_0402_10V7K~D +3VS_DMC <18> DMC_PCH_DET# <39> CPU_MXM_DMC_AUXN <39> CPU_MXM_DMC_AUXP <39> CPU_MXM_DMC_N2 <39> CPU_MXM_DMC_P2 <39> CPU_MXM_DMC_N0 <39> CPU_MXM_DMC_P0 DMC_PCH_DET# CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXP CPU_MXM_DMC_N2 CPU_MXM_DMC_P2 CPU_MXM_DMC_N0 CPU_MXM_DMC_P0 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 53 55 57 59 61 63 65 67 69 71 73 75 54 56 58 60 62 64 66 68 70 72 74 76 GND1 GND3 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 +1.5VS_DMC 1 +3VS_DMC 2 CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXP DMC_RADIO_OFF# PLT_RST# R42 1 R43 1 DMC_RADIO_OFF# 2 100K_0402_5%~D 2 100K_0402_5%~D 1 2 1 2 1 2 1 2 C44 0.1U_0402_16V4Z~D C61 <16> PCIE_PTX_WANRX_N2 <16> PCIE_PTX_WANRX_P2 PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 2 4 6 8 10 12 14 16 C43 0.1U_0402_16V4Z~D <16> PCIE_PRX_WANTX_N2 <16> PCIE_PRX_WANTX_P2 3 CLK_PCIE_MINI2# CLK_PCIE_MINI2 1 3 5 7 9 11 13 15 C42 4.7U_0805_10V4Z~D <18> CLK_PCIE_MINI2# <18> CLK_PCIE_MINI2 1 3 5 7 9 11 13 15 C46 0.1U_0402_16V4Z~D @ RE30 1 2 0_0402_5%~D R40 1 2 0_0402_5%~D R41 1 2 0_0402_5%~D MINI2CLK_REQ# <18> MINI2CLK_REQ# C45 4.7U_0805_10V4Z~D +3VS_DMC JDMC1 PCIE_WAKE# COEX2 COEX1 +1.5VS_DMC L1 2 1 BLM18AG601SN1D_0603~D +3VS_DMC L2 2 1 BLM18PG330SN1D_2P~D <21> 3 MINI2_SMBCLK RE33@1 MINI2_SMBDATA RE34@1 2 0_0402_5%~D PCH_SMBCLK 2 0_0402_5%~D PCH_SMBDATA USB20_N5 USB20_P5 PCH_SMBCLK <6,12,13,14,15,19,49,50,53> PCH_SMBDATA <6,12,13,14,15,19,49,50,53> USB20_N5 <20> USB20_P5 <20> R44 1M_0402_5%~D 1 2 DP_DMC_HPD CPU_MXM_DMC_N3 CPU_MXM_DMC_P3 CPU_MXM_DMC_N1 CPU_MXM_DMC_P1 DP_DMC_HPD <39> CPU_MXM_DMC_N3 <39> CPU_MXM_DMC_P3 <39> CPU_MXM_DMC_N1 <39> CPU_MXM_DMC_P1 <39> 78 TYCO_2041286-1 CONN@ 4 4 Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. Mini Card -WLAN/DMC/BT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 48 of 61 5 4 3 2 1 +5VALW Power share LI3 LI1 2 1 3 4 1 USB3RN1_R 4 USB3RP1_R @ RI5 USB3TP1_R_C 3 2 1 3 4 +5VALW PWRSHARE_SEL# RI9 1 PWRSHARE_OE# PWRSHARE_SEL# PWRSHARE_EN RI8 RI10 RI7 1 1 1 1 USB3TN1_R 4 USB3TP1_R +3VS @ @ 2 3.3K_0402_5% 2 3.3K_0402_5% USB3_P1_PIN6 USB3_P1_PIN18 RI53 RI52 1 1 @ @ 2 3.3K_0402_5% 2 3.3K_0402_5% USB3_P0_PIN6 USB3_P0_PIN18 RI421 RI431 RI441 RI411 @ @ @ @ 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D USB3_CM_P0 USB3_CM_P1 USB3_ERD_P0 USB3_ERD_P1 RI191 RI201 RI211 RI221 RI261 RI231 RI241 RI251 RI301 RI271 RI281 RI291 @ @ @ @ @ @ @ @ @ @ @ @ 2 2 2 2 2 2 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 USB3_OS2_P1 USB3_DE2_P1 USB3_EQ2_P1 USB3_OS1_P1 USB3_DE1_P1 USB3_EQ1_P1 RI871 RI311 RI361 RI401 RI351 RI321 RI331 RI341 RI391 RI371 RI381 RI841 @ @ @ @ @ @ @ @ @ @ @ @ 2 2 2 2 2 2 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 USB3_OS2_P1 USB3_DE2_P1 USB3_EQ2_P1 USB3_OS1_P1 USB3_DE1_P1 USB3_EQ1_P1 RI461 RI471 RI481 RI451 @ @ @ @ 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D USB3_CM_P0 USB3_CM_P1 USB3_ERD_P0 USB3_ERD_P1 2 0_0402_5%~D 2 0_0402_5%~D USB3_P0_PIN6 USB3_P0_PIN18 B 2 0_0402_5%~D 2 0_0402_5%~D USB3_P1_PIN6 USB3_P1_PIN18 1 1 RI85 RI51 1 1 @ @ <20> <20> USB3RN1 USB3RP1 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3TN1 USB3TP1 CI9 CI8 1 1 UI3 CI4 CI5 1 1 USB3RN1_L USB3RP1_L 11 12 USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 15 16 17 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D USB3TN1_L 2 0.1U_0402_10V6K~D USB3TP1_L USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 Vendor pin pin15 PS8710B (default) AEQ1 OS2 pin16 ADE0 DE2 pin17 AEQ0 EQ2 pin4 BEQ1 OS1 pin3 BDE0 DE1 SN65LVPE502 EN== 1:normal operation(default) 0:sleep mode CM== 0:normal operation(default) 1:Compliance test mode TI VCC VCC NC NC TX2TX2+ RX2RX2+ OS2 DE2 EN_RXD EQ2 CM 8 9 RX1RX1+ 4 3 2 TX1TX1+ OS1 DE1 EQ1 25 PGND 2 0_0402_5%~D <20> <20> USB20_P1 USB20_N1 USB20_P1 4 1 4 3 1 2 3 2 1 USB3RN2 CI27 USB3RP2 CI28 2 USB3TP2_R_C 3 3 4 1 USB3_P0_PIN6 <20> <20> USB3TN2 USB3TP2 USB3TN2 USB3TP2 CI23 CI24 4 USB3TP2_R USB3_P0_PIN18 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3RN1_RL USB3RP1_RL RI72 RI73 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3RN1_R_C USB3RP1_R_C @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3TN1_RL USB3TP1_RL RI74 RI75 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3TN1_R_C USB3TP1_R_C USB3RN2 USB3RP2 RI60 RI61 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3RN2_RL USB3RP2_RL RI68 RI69 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3RN2_R_C USB3RP2_R_C USB3TN2 USB3TP2 RI63 RI62 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3TN2_RL USB3TP2_RL RI71 RI70 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D USB3TN2_R_C USB3TP2_R_C +3VS C 1 2 2 11 12 15 16 17 8 9 4 3 2 VCC VCC NC NC TX2TX2+ RX2RX2+ OS2 DE2 EN_RXD EQ2 CM RX1RX1+ TX1TX1+ OS1 DE1 EQ1 GND GND GND GND PGND 7 24 RI77 @ RI76 20 19 USB3RN2_R_C USB3RP2_R_C 5 14 USB3_ERD_P1 USB3_CM_P1 23 22 USB3TN2_RC CI29 USB3TP2_RC CI30 6 10 18 21 USB3_P1_PIN6 USB3TN2_R USB20_P1_CONN 2 4.99K_0402_1% 2 0_0402_5%~D 1 1 9 1 8 3 7 2 6 4 5 USB20_N1_CONN USB3RP2_R USB3RN2_R SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX- 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 1 1 2.0A 0.1U_0402_16V7K 2 0_0402_5%~D <43,53> USB_PWR_EN# 2 2 1 1 USB3RN2_R USB3RP2_R_C 3 3 4 4 USB3RP2_R 1 2 DLW21SN900HQ2L_0805_4P~D @ RI16 1 2 0_0402_5%~D CI37 0.1U_0402_16V7K USB3RN2_R_C USB_PWR_EN# GND VIN VIN EN EPAD 1 2 3 4 9 1 LI4 USB3RP1_R USB3TN1_R 4 7 USB3TN1_R USB3TP1_R 5 6 USB3TP1_R 3 8 IP4292CZ10-TBR_XSON10_2.5X1~D B VOUT VOUT VOUT FLG 10 11 12 13 220U_6.3V_M 1 + 2 2 USB3_P1_PIN18 USB20_P1_CONN DI8 USB20_N1_CONN +USB3_VCCB 8 7 6 5 1 CI32 GND GND GND GND USB3TN2_R_C USB3TP2_R_C UI5 @ RI15 USB3RN1_R 9 TAITW_PUBAU5-09FLBS1NN4H0 CONN@ CI36 A 10 2 +USB3_VCCB 2 0_0402_5%~D 4.7U_0805_10V4Z 1 USB3RP1_R JUSB2 USB3TP2_R UI4 PCB footprint and CIS symbol use TI (SN65LVPE502CPRGER) Compal P/N and value use Parade (PS8710B) 1 USB3RN1_R +USB3_VCCB +5VALW CI35 2 DI2 PS8713BTQFN24GTR2-A0_TQFN24_4X4 USB3TN2_R 2 USB20_N0_CONN 1 1 USB3_OS1_P1 USB3_DE1_P1 USB3_EQ1_P1 1 1 + 11 12 13 14 USB20_P0_CONN 1 1 2 0.1U_0402_10V6K~D USB3TN2_L 2 0.1U_0402_10V6K~D USB3TP2_L 1 1 1 CI20 220U_6.3V_M TAIWI_USB006-107CRL-TWD CONN@ USB3TN1_R_C USB3TP1_R_C 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D RI66 RI67 USB20_P1_CONN DLW21SN900HQ2L_0805_4P~D @ RI18 6 10 18 21 <43> USBCHG_DET# 1 1 RI64 RI65 2 0_0402_5%~D 1 USB3TN1_RC CI11 USB3TP1_RC CI10 USB3TN1 USB3TP1 USB3_OS2_P1 USB3_DE2_P1 USB3_EQ2_P1 2 0_0402_5%~D 2 USB3_ERD_P0 USB3_CM_P0 23 22 80mil USB3RN2_R 1 10 USB3RN2_R USB3RP2_R 2 9 USB3RP2_R USB3TN2_R 4 7 USB3TN2_R USB3TP2_R 5 6 USB3TP2_R 3 8 IP4292CZ10-TBR_XSON10_2.5X1~D A 0_0402_1% 1 2 RI83 DI10 PESD5V0U2BT_SOT23-3~D USB3TN2_R_C 1 LI5 5 14 USB3RN1 USB3RP1 25 @ RI17 USB3RN1_R SSTX+ VBUS SSTXD+ GND DGND SSRX+ GND GND GND SSRXGND Plug_DET For OPTION reserve 2 0.1U_0402_10V6K~D USB3RN2_L 2 0.1U_0402_10V6K~D USB3RP2_L 1 1 USB20_N1_CONN DLW21SN900SQ2L_0805_4P~D @ RI14 USB3RN2 USB3RP2 D 0.1U_0402_16V7K CI34 10U_0603_6.3V6M~D <20> USB20_N1 USB20_N0_CONN USB3RP1_R 0.01U_0402_16V7K~D 1 2 1 2 LI6 <20> USB3RN1_R_C USB3RP1_R_C 20 19 9 1 8 3 7 2 6 4 5 10 USB3TN1_R USB20_P0_CONN 2 4.99K_0402_1% 2 0_0402_5%~D 1 1 PCB footprint and CIS symbol use TI (SN65LVPE502CPRGER) Compal P/N and value use Parade (PS8710B) 1 13 1 GND GND GND GND RI56 @ RI57 7 24 PS8713BTQFN24GTR2-A0_TQFN24_4X4 PS8710 [A(B)_DE1, A(B)_DE0] == LL: 3.5dB de-emphasis LH: No de-emphasis pin2 BEQ0 EQ1 HL: 7dB de-emphasis pin5 PD EN_RXD HH: 5dB with boost output swing pin14 TEST CM [A(B)_EQ1, A(B)_EQ0] == LL: reserved pin18 ADE1 LH: program EQ for channel loss up to 7dB pin6 BDE1 HL: program EQ for channel loss up to 14.5dB [Parade suggest] HH: program EQ for channel loss up to 11.5dB PS8710 AEQ0,BEQ0 adjust 7db, TEST == REXT use 3.3 K well get btter test result. L: Normal operation (default) CI26 H: Test mode enable <20> CI15 +USB3_VCCA USB3TP1_R CI25 .1U_0402_16V7K~D @ RI13 2 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 1 2 1 1 1 @ @ 2 10K_0402_5%~D @ @ @ USB_OC0# @ AP2301MPG-13_MSOP8 DI9 PESD5V0U2BT_SOT23-3~D RI55 RI54 RI49 RI50 S 2 0_0402_1% 1 2 RI80 USB CONN 1 13 <20> <20> C DI7 1 2 80mil JUSB1 2 0_0402_5%~D 1 2 G CI13 VOUT VOUT VOUT FLG +USB3_VCCA CI6 .1U_0402_16V7K~D DLW21SN900HQ2L_0805_4P~D @ RI6 2 0_0402_5%~D GND VIN VIN EN 8 7 6 5 CI22 10U_0603_6.3V6M~D 2 1 1 +3VS CI7 0.01U_0402_16V7K~D 1 2 1 2 2 0_0402_5%~D 1 LI2 USB3TN1_R_C PWRSHARE_EN RI86 D SDMK0340L-7-F_SOD323-2~D 2 0_0402_5%~D 1 1 <43> PWRSHARE_EN_EC# DLW21SN900HQ2L_0805_4P~D @ RI4 PWRSHARE_EN_R# 3 3 RI82 10K_0402_5% 1 2 3 4 2 2 USB3RP1_R_C SLG55584AVTR_TDFN8_2X2 +USB3_VCCA UI2 3 USB3RN1_R_C 2 2.0A 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0_0402_5%~D 1 CI16 9 D @ RI3 2 2 2 0_0402_5%~D 1 1 2 QI1 SSM3K7002FU_SC70-3~D CI1 0.1U_0402_16V4Z~D @ RI2 +5VALW CB CEN TDM DM TDP DP VDD SELCDP Thermal Pad +3VALW RI81 DLW21SN900SQ2L_0805_4P~D 4.7U_0805_10V4Z PWRSHARE_EN SW_USB20_N0 SW_USB20_P0 PWRSHARE_SEL# 1 2 3 4 9 1 2 <43> PWRSHARE_OE# <20> USB20_N0 <20> USB20_P0 USB20_N0_CONN 2 8 7 6 5 1 1 UI1 PWRSHARE_OE# USB20_N0 USB20_P0 3 1 1 USB20_P0_CONN 3 3 100K_0402_5% SW_USB20_N0 +5VALW CI18 4 1 4 2 SW_USB20_P0 EPAD 2 0_0402_5%~D 1 1 @ RI1 @ USB_OC1# 1 <20> CI38 AP2301MPG-13_MSOP8 2 0.1U_0402_16V7K Compal Secret Data Security Classification Issued Date 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. USB 3.0/2.0 x2 (left side) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 49 of 61 5 4 3 2 1 60 pin FFC connector To MB +5VALW TP_CLK <43> TP_CLK <43> TP_DATA TP_DATA +5VS +5VALW +5VALW <6,12,13,14,15,19,49,50,51> <6,12,13,14,15,19,49,50,51> <48> <48> <48> 3 2 JP3 +5VS_TP_LED 2 2 1 C48 0.1U_0402_16V4Z~D D C47 10U_0805_10V6K 1 BTB CONNECTOR TO USB3.0 Board PCH_SMBDATA PCH_SMBCLK TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV# TP_CLK TP_DATA TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV# JIO1 <20> USB20_N2 <20> USB20_P2 <20> USB3TP5 <20> USB3TN5 <20> USB3RP5 <20> USB3RN5 <20> USB20_N3 <20> USB20_P3 <20> USB3TP6 <20> USB3TN6 C <20> USB3RP6 <20> USB3RN6 +3VS <20> USB_OC2# <20> USB_OC3# USB20_N2 USB20_P2 USB3TP5 USB3TN5 USB3RP5 USB3RN5 USB20_N3 USB20_P3 USB3TP6 USB3TN6 USB3RP6 USB3RN6 USB_OC2# USB_OC3# 51 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND2 52 PESD5V0U2BT_SOT23-3~D D71 MXM1_FAN_PWM MXM1_FAN_FB RTRON_LED_G_DRV# RTRON_LED_R_DRV# RTRON_LED_B_DRV# USB_PWR_EN# LAN_ACTIVITY# LAN_LINK#_R LAN_LED2#_R LAN_MDIN0 LAN_MDIP0 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 MXM1_FAN_PWM <43> MXM1_FAN_FB <43> RTRON_LED_G_DRV# <48> RTRON_LED_R_DRV# <48> RTRON_LED_B_DRV# <48> USB_PWR_EN# <43,52> LAN_ACTIVITY# <44> LAN_LINK#_R <44> LAN_LED2#_R <44> +LAN_IO LAN_MDIN0 <44> LAN_MDIP0 <44> LAN_MDIN1 LAN_MDIP1 Place close to JP3 KP_DET# +3VS <19,40,43,54> EC_SMB_DA2 <19,40,43,54> EC_SMB_CK2 <20> <20> USB20_P13 USB20_N13 <47,48> I2C_CLK <47,48> I2C_DAT <48> 7313_INT# +3.3V_F347 <43> KB_DET# LAN_MDIN2 <44> LAN_MDIP2 <44> LAN_MDIN3 LAN_MDIP3 LAN_MDIN3 <44> LAN_MDIP3 <44> E&T_1001-F50E-03R CONN@ +5VS +3VS 2 1 2 1 2 1 R55 10K_0402_5%~D R57 10K_0402_5%~D R56 10K_0402_5%~D 2 <43> KSI[0..7] <43> KSO[0..17] C56 22U_0805_6.3VAM~D 1 MXM1_FAN_PWM MXM1_FAN_FB VPK_DET# VPK_EN +5VS LAN_MDIN1 <44> LAN_MDIP1 <44> LAN_MDIN2 LAN_MDIP2 <43> VPK_DET# <43> VPK_EN Reserve for Key Pad (Viking only) KSI[0..7] KSO[0..17] I2C_CLK I2C_DAT KB_DET# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 MXM1_FAN_FB_D 2 1 D66 SDMK0340L-7-F_SOD323-2~D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 D C G2 G1 62 61 CVILU_CF25602D0R0-05-NH CONN@ B B 30pin Connector to CardReader JIO2 <20> PCIE_PTX_CARDRX_P4 <20> PCIE_PTX_CARDRX_N4 <20> PCIE_PRX_CARDTX_P4 <20> PCIE_PRX_CARDTX_N4 <18> CLK_PCIE_CD <18> CLK_PCIE_CD# 2 3 ON/OFFBTN# D72 PESD24VS2UT_SOT23-3~D 1 A Place close to JIO2 <6,17,43,44,51> PLT_RST# <18> CDCLK_REQ# +3VALW +3VS +5VS +5VALW <48> LED_R_7313#_1 <48> LED_B_7313#_1 <48> LED_G_7313#_1 <43> CAPS_LED# <43> WLES ON/OFF LED# <48> HDD_R <48> HDD_G <48> HDD_B <55> ON/OFFBTN# <48> LID_SW <19,43,47,48> LID_SW_IN# <48> PWR_G_7313# <48> PWR_R_7313# <48> PWR_B_7313# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PCIE_PTX_CARDRX_P4 PCIE_PTX_CARDRX_N4 PCIE_PRX_CARDTX_P4 PCIE_PRX_CARDTX_N4 CLK_PCIE_CD CLK_PCIE_CD# PLT_RST# CDCLK_REQ# LID_SW LID_SW_IN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 G1 G2 ACES_88196-3041 CONN@ A Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title IO BTB CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: 5 4 3 2 Friday, June 22, 2012 Sheet 1 50 of 61 A B C D E 1 1 +3VS 1 R46 REMOTE_P1 2 0_0402_5%~D 1 1 1 1 2 3 @ C51 100P_0402_50V8J~D 2 SENSOR_DIODE_P1 C 2 B E Q17 MMBT3904WT1G_SC70-3~D 2 SENSOR_DIODE_N1 R47 C50 470P_0402_50V7K~D +3VS Diode circuit s used for skin temp sensor (placed between CPU and MXM). Place C51 close to Q17 as possible. R48 U5 REMOTE_N1 2 0_0402_5%~D 1 C49 0.1U_0402_10V7K~D System FAN Controller 2 4.7K_0402_5%~D 1 1 VDD SCLK 8 2 D+ SDATA 7 3 D- ALERT# 6 4 THERM# GND 5 EC_SMB_CK2 EC_SMB_CK2 <19,40,43,53> EC_SMB_DA2 EC_SMB_DA2 <19,40,43,53> ADM1032ARMZ-REEL_MSOP8 Address:100_1100 +5VS +3VS 2 1 2 1 2 1 R51 10K_0402_5%~D R50 10K_0402_5%~D R49 10K_0402_5%~D 2 C52 22U_0805_6.3VAM~D 1 2 2 JFAN1 SYSTEM_FAN_PWM SYSTEM_FAN_FB <43> SYSTEM_FAN_PWM <43> SYSTEM_FAN_FB 1 2 3 4 5 6 2 1 D65 SDMK0340L-7-F_SOD323-2~D 1 2 3 4 G5 G6 ACES_50273-0040N-001 CONN@ +3VS 1 2 SENSOR_DIODE_P2 @ 1 2 REMOTE_P2 2 0_0402_5%~D 1 1 1 C 3 100P_0402_50V8J~D C55 3 R52 2 B E Q19 MMBT3904WT1G_SC70-3~D 2 SENSOR_DIODE_N2 R53 1 2 0_0402_5%~D +3VS R54 1 C54 470P_0402_50V7K~D REMOTE_N2 2 6.8K_0402_5%~D C53 0.1U_0402_10V7K~D MXM1 FAN Controller U6 1 VDD SCLK EC_SMB_CK2 8 2 D+ SDATA 7 3 D- ALERT# 6 4 THERM# GND 5 3 EC_SMB_DA2 ADM1032ARMZ-2REEL_MSOP8 Address:100_1101 4 4 Compal Secret Data Security Classification Issued Date 2012/06/22 2013/06/21 Deciphered Date Title Compal Electronics, Inc. Thermal Sensor & FAN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 51 of 61 A B C D E ON/OFF switch IR SENSOR connector TOP Side 2 R58 100K_0402_5%~D 1 D26 JIR1 1 2 3 4 5 6 7 8 GND GND SW2 SMT1-05-A_4P 1 3 2 2 4 ON/OFF 1 <43> 3 DAN202UT106_SC70-3 6 5 2 1 Bottom Side 1 2 3 4 5 6 2 ON/OFFBTN# <53> ON/OFFBTN# 2 USB20_N7 USB20_P7 USB20_N7 USB20_P7 Power Button C58 0.1U_0402_25V6K~D C57 0.1U_0402_16V4Z~D <20> <20> ON/OFFBTN# 4 6 5 +5VS 1 +3VLP 2 SW1 SMT1-05-A_4P 1 3 1 1 2 E-T_4260-F06N-10L CONN@ Pop only for SSI debug 1 @ H5 @ H6 @ H7 @ H8 H_3P3 H_3P3 H_3P3 H_3P3 1 B 1 @ H1 @ H2 @ H3 @ H4 H_3P5 H_3P5 H_3P5 H_3P5 1 A 1 1 1 3 1 3 1 1 1 1 1 1 @ H17 @ H18 H_3P3 H_3P3 1 D 1 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H29 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 1 C @ H34 H_2P0N FD2 FD3 FD4 1 1 1 1 1 1 1 Issued Date Deciphered Date 2013/06/21 1 1 @ FIDUCIAL_C40M80 4 Title Date: B @ FIDUCIAL_C40M80 Compal Secret Data 2012/06/22 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A @ FIDUCIAL_C40M80 Fiducial Mark PCB-MB Security Classification 1 @ FIDUCIAL_C40M80 4 1 1 ZZZ1 1 1 F @ H23 @ H24 @ H25 @ H26 @ H27 @ H30 @ H31 @ H32 @ H33 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 1 @ H19 @ H20 @ H21 @ H22 H_3P8 H_3P8 H_3P8 H_3P8 1 E 1 1 1 1 FD1 C D KB & Power Button & IR Document Number Rev 0.1 LA-9331P Friday, June 22, 2012 Sheet E 52 of 61 A B C D E DC to DC +3VALW to +3V_PCH +3VALW RZ30 200K_0402_5% 1 2 2 QZ3 SI4800BDY-T1-E3_SO8~D 1 1 4 B+_BIAS 2 1 2 2 +5VMXM_GATE 6 1 QZ9A DMN66D0LDW-7_SOT363-6~D DGPU_PWR_EN# 2 1 2 1 2 4 1 @ RZ32 200K_0402_5% 1 2 1 CZ26 0.1U_0402_16V4Z~D 2 100mil(2.5A) CZ25 10U_0805_10V4Z~D 3 2 1 RZ33 0_0402_5%~D S 1 +5VMXM UZ3 SI4800BDY-T1-E3_SO8~D 8 1 7 2 6 3 5 CZ27 0.1U_0603_25V7K~D 1 2 G RZ54 1M_0402_5%~D D SUSP 2 CZ24 10U_0805_10V4Z~D 2 +1.05VS_GATE RZ53 330K_0402_5%~D 1 CZ17 1U_0603_10V4Z~D CZ16 10U_0805_10V4Z~D 1 1 B+_BIAS CZ32 100P_0402_50V8J~D 2 +5VALW 2 QZ7 SSM3K7002F_SC59-3~D 3 2 2 CZ9 1U_0603_10V4Z~D S 1 1 RZ4 0_0402_5%~D 2 G CZ10 0.1U_0603_25V7K~D 1 QZ4 SSM3K7002F_SC59-3~D D SUSP 2 +3VS_GATE 1 2 RZ3 102K_0402_1% B+_BIAS 2 1 CZ8 10U_0805_10V4Z~D 2 1 CZ7 10U_0805_10V4Z~D 1 CZ6 10U_0805_10V4Z~D 2 1 2 3 2 +5VALW to +5VMXM +1.05VS QZ20 SI4164DY-T1-GE3_SO8~D 8 1 7 2 6 3 5 +3VS 8 7 6 5 @ +1.05V to +1.05VS +1.05V +3VALW 2 4 +3VALW to +3VS 2 2 @ 1 3 4 3 2 1 1 RZ31 0_0402_5%~D S 1 RZ6 0_0402_5%~D 2 G CZ15 0.1U_0603_25V7K~D PCH_PWR_EN# 1 QZ5 SSM3K7002F_SC59-3~D 2 QZ8A DMN66D0LDW-7_SOT363-6~D DGPU_PWR_EN# 2 +3V_PCH_GATE D RZ2 0_0402_5%~D 5 CZ4 0.1U_0603_25V7K~D QZ2B DMN66D0LDW-7_SOT363-6~D SUSP RZ5 1 2 102K_0402_1% B+_BIAS 1 CZ22 0.1U_0603_25V7K~D +5VS_GATE 1 2 RZ1 102K_0402_1% B+_BIAS 1 +3VMXM_GATE 6 B+_BIAS 2 4 2 1 1 1 40mil(1A) @ 2 2 4 1 1 4 2 1 1 2 3 CZ21 0.1U_0402_16V4Z~D 1 +3VMXM UZ2 SI4800BDY-T1-E3_SO8~D 8 7 6 5 CZ23 10U_0805_10V4Z~D 2 CZ20 10U_0805_10V4Z~D 2 1 CZ14 1U_0603_10V4Z~D 2 1 +3VALW 1 2 3 CZ13 10U_0805_10V4Z~D 1 8 7 6 5 CZ12 10U_0805_10V4Z~D 2 CZ11 10U_0805_10V4Z~D 1 CZ3 1U_0603_10V4Z~D CZ2 10U_0805_10V4Z~D CZ1 10U_0805_10V4Z~D 2 +3VALW to +3VMXM Transfer +3V_PCH QZ6 SI4800BDY-T1-E3_SO8~D CZ5 10U_0805_10V4Z~D QZ1 SI4800BDY-T1-E3_SO8~D 8 1 7 2 6 3 5 1 1 +5VS @ +5VALW 2 +5VALW to +5VS Discharge Circuit +1.5VS +5VS +3VMXM +5VALW +5VMXM +3VALW +5VALW 1 2 2 2 1 1 2 S @ 3 2 @ 1 S 1 +5VALW 3 3 +5VALW RZ49 100K_0402_5%~D +3VS 1 2 2 2 2 @ @ 1 1 3 1 1 1 2 1 3 1 1 3 3 4 SSM3K7002FU_SC70-3~D 2 2 2 6 1 1 S 3 4 Compal Secret Data Security Classification Issued Date 1 QZ18 SSM3K7002F_SC59-3~D 3 D 2 G <29,43> DGPU_PWR_EN CZ31 0.1U_0603_25V7K~D S 2 G 2 S DGPU_PWR_EN# RZ51 100K_0402_5%~D S 1 QZ17 SSM3K7002F_SC59-3~D 2 G QZ13 D 1 CZ30 0.1U_0603_25V7K~D <6,10> RUN_ON_CPU1.5VS3# D QZ14 SSM3K7002FU_SC70-3~D S SSM3K7002FU_SC70-3~D 2 G QZ19 RZ50 100K_0402_5%~D SUSP D 2 G <43,59,60> SYSON +DDR_CHG 5 D +1.35V_CPU_VDDQ_CHG SUSP QZ11B DMN66D0LDW-7_SOT363-6~D QZ11A DMN66D0LDW-7_SOT363-6~D 2 +1.05VS_D +3VS_D +3V_D PCH_PWR_EN# 4 RZ41 470_0603_5% RZ39 22_0603_5%~D RZ43 470_0603_5% SYSON# +0.675VS 2 +1.35V_CPU_VDDQ RZ38 220_0603_5%~D RZ42 470_0603_5% RZ48 100K_0402_5%~D +1.05VS 1 1 +3V_PCH 2 1 4 4 1 2 3 3+5VMXM_D1 +3VMXM_D 1 2 1 3 SSM3K7002FU_SC70-3~D 6 1 1 3 SSM3K7002FU_SC70-3~D 2 CZ29 0.1U_0603_25V7K~D 1 D 2 G <10,43,59,61> SUSP# QZ16 SSM3K7002F_SC59-3~D 2 G <35,43> PCH_PWR_EN SUSP RZ47 100K_0402_5%~D DGPU_PWR_EN# 5 1 QZ15 SSM3K7002F_SC59-3~D DGPU_PWR_EN# 5 D CZ28 0.1U_0603_25V7K~D S PCH_PWR_EN# QZ9B DMN66D0LDW-7_SOT363-6~D 2 G QZ10 QZ8B DMN66D0LDW-7_SOT363-6~D 2 D RZ46 100K_0402_5%~D RZ45 100K_0402_5%~D @ RZ44 10K_0402_5%~D RZ52 100K_0402_5%~D SUSP SUSP RZ36 470_0603_5% RZ35 470_0603_5% +1.5VS_D S QZ2A DMN66D0LDW-7_SOT363-6~D SYSON# 2 G QZ12 D +5VS_D +1.35V_D 3 RZ40 470_0603_5% 1 RZ34 470_0603_5% 2 RZ37 470_0603_5% 2 2 1 2 1 1 +1.35V 2012/06/22 Deciphered Date 2013/06/21 Title Compal Electronics, Inc. DC/DC Interface THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-9331P Date: A B C D Friday, June 22, 2012 Sheet E 53 of 61 A B 1 2 4 @ 1M_0402_1% PR3 2.2K_0402_5% 2 1 S 2 G PR6 100K_0402_1% 1 2 1 +5VALW 10K_0402_1% 1 3 2 C PQ2 MMST3904-7-F_SOT323~D 2 B 3 E @ PD1 SM24_SOT23 JRTC1 @ 2 2 1 VSB_N_001 +5VALW 1 2 2 EC_SMB_CK1 <63> PR20 100_0402_5% 1 2 D S 2VSB_N_002 2 G EC_SMB_DA1 <63> 2 PQ3 TP0610K-T1-E3_SOT23-3 PQ4 2N7002KW _SOT323-3 1 PR19 0_0402_5% PR17 0_0402_5% 1 +3VALW <58> POK PR18 100_0402_5% 1 2 MOLEX_87437-1342 PR14 100K_0402_1% 1VSB_N_003 PR16 10K_0402_1% 1 2 PC12 .1U_0402_16V7K PR15 100_0402_5% 1 2 1 CLK_SMB DAT_SMB BATT_PRS SYS_PRES 3 2 BATT_TEMP <43,63> 2 3 +3VLP LOTES AAA-BAT-054-K01 1 PR13 100K_0402_1% BAS40CW _SOT323-3 PD4 B+_BIAS 1 PC11 0.1U_0402_25V6 3 B+ 2 +RTCBATT 1 1 3 2 3 2 1 2 + PC10 0.22U_0603_25V7K - PD3 PESD24VS2UT_SOT23-3 2 1 PR12 100K_0402_1% 1 1 PD5 2 PESD24VS2UT_SOT23-3 1 2 3 4 5 6 7 8 9 10 11 12 13 1 PR8 PSID-1 PBATT1 @ 1 2 3 4 5 6 7 8 9 10 11 12 13 <43> BATT++ PC9 100P_0402_50V8J 2 PC7 0.01U_0402_25V7K 1 1 PL3 C8B BPH 853025_2P 1 2 PC8 1000P_0402_50V7K 2 1 BATT+ 0.1U_0402_25V6 2 1 2 PC6 100P_0402_50V8J 2 1 @ PC5 @ PR10 @ 1 6 2 2 BATT++ 2 BATT+ PQ1A 2N7002BKS 2N SOT363-6 PR1 200K_0402_1% 5 PS_ID PSID-2 PR9 15K_0402_1% 1 2 1 1 @ 2 1M_0402_1% <17,29,43,47,63> ACIN @ 1 PR7 2N7002BKS 2N SOT363-6 1 @ 32 PSID 1 PQ1B PL2 BLM18BD102SN1D_0603~D 2 1 ACES 50493-0110N-001 PR4 33_0402_5% 3 PSID-3 1 2 PQ7 FDV301N_NL_SOT23-3~D D Erp lot6 Circuit VIN PR5 3.3K_1206_5%~D 1 2 PC4 100P_0402_50V8J 1 2 PC3 1000P_0402_50V7K PC2 100P_0402_50V8J 1 2 1 +DCIN_JACK D +3VALW 2 1 2 PJPDC1 @ 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 PC1 1000P_0402_50V7K ADPIN C VIN PL1 C8B BPH 853025_2P 1 2 3 3 ADP_I +3VLP 2 PR23 49.9K_0402_1% 2 +3VALW 2 PR25 @ 12.1K_0402_1% 1 1 PR24 12.1K_0402_1% 1 <43,63> PH1 under CPU botten side : CPU thermal protection at 93 +/- 3 degree C <43> VCIN0_PH 1 VCIN1_PH PR26 PC13 @ PH1 100K_0402_1%_TSM0B104F4251RZ .1U_0402_16V7K 1 1 499K_0402_1% 2 2 2 <43> 4 4 <43> Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 Deciphered Date 2013/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C ECAGND PWR-DCIN / BATT CONN / OTP Document Number Rev 0.1 LA-9331P Friday, June 22, 2012 Sheet D 54 of 61 A B C D E PR100 13.7K_0402_1%~D 1 2 1 @ PC122 2 @ 100P_0402_50V8J PC121 100P_0402_50V8J 1 2 +3VLP PR101 30.9K_0402_1% 2 1 PR106 59K_0402_1%~D 1 2 BST_5V SW1 18 SW1 4 PC111 0.1U_0603_25V7K 1 2 PC108 2200P_0402_50V7K 2 1 2 DRVL1 2 +5VALWP 1 B++ 3 2 1 PR118 0_0603_5%~D 1 2 PC118 1U_0603_10V5K 2 1 4 VL PR110 4.7_1206_5% 2 1 LG_5V 4 PC117 0.1U_0603_25V7K 2 1 PL102 3.3UH +-20% PIMB104T-3R3MS 10A PC119 680P_0603_50V7K 2 1SNUB_5V EN1 VREG5 3 2 1 PR107 2.2_0603_5% 1 2 PC104 10U_0805_25V6K 2 1 VBST1 17 PC109 10U_0805_25V6K 2 1 UG_5V PC103 0.1U_0402_25V6 2 1 5 2 VFB1 3 1 16 @ 15 5V_EN 20 LG_3V 13 VIN 12 SW2 DRVL2 8 11 5 VCLK DRVH1 VBST2 1 2 3 PQ103 FDMC8878_POWER33-8-5 PC116 PR109 680P_0603_50V7K 4.7_1206_5% 2 1 SNUB_3V 2 1 PC101 150U_B2_6.3VM_R35M 2 TPS51225_QFN20_3X3 19 PC102 220U_6.3V_M 9 SW2 + 4 DRVH2 PL101 3.3UH_PCMB063T-3R3MS_6.5A_20% 1 2 1 14 PGOOD 10 BST_3V 21 VO1 AON7518 1N DFN PQ102 PR108 2.2_0603_5% 1 2 PAD AON6508 1N DFN PQ104 UG_3V 4 VFB2 CS2 7 POK PC112 0.1U_0603_25V7K 1 2 EN2 B++ 5 <57> 6 VREG3 5 3V_EN 1 2 3 @ 2 +3VALWP FB_5V 5 FB_3V PU100 PQ101 FDMC8884_POWER33-8-5 PC107 10U_0805_25V6K 2 1 PC110 10U_0805_25V6K 2 1 PC106 2200P_0402_50V7K 2 1 PC105 0.1U_0402_25V6 2 1 PL103 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 2 1 PR104 20K_0402_5%~D 2 1 CS1 PR105 120K_0402_1%~D 1 2 B++ B+ PR103 0_0603_5%~D 1 2 PR102 20K_0402_5%~D 1 2 PC114 1U_0603_10V5K 2 1 1 1 + 2 3 3 3VALWP TDC 6.08A Peak Current 8.11A OCP current 9.73A TYP MAX H/S Rds(on) :22mohm , 30mohm L/S Rds(on) :12.1mohm ,17mohm 3V_EN 1 2 PR111 0_0402_5% 5V_EN 1 2 PR112 0_0402_5% PD102 <43> 2 EC_ON 1 PR113 2.2K_0402_5% 1 2 3 <43> USBCHG_DET_D BAS40CW_SOT323-3 <43> VCOUT0_PH# PD100 SBR2U30P1-7_POWERDI123-2 1 2 PJP100 +3VALWP 1 PJP101 2 +3VALW +5VALWP 1 2 1 PAD-OPEN 4x4m 2 1 @ PR116 402K_0402_1% VIN @ PR115 1M_0402_1% 1 2 2 +5VALW PAD-OPEN 4x4m PJP102 PC120 4.7U_0603_6.3V6K @ PD101 LL4148_LL34-2 2 1 5VALWP TDC 10.64A Peak Current 14.19A OCP current 17.03A TYP MAX H/S Rds(on) 11.2mohm , 14mohm L/S Rds(on) :3.7mohm , 5mohm 1 2 PAD-OPEN 4x4m 4 4 2012/06/22 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2013/06/21 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D PWR-3VALWP/5VALWP Document Number Rev 0.1 LA-9331P Friday, June 22, 2012 Sheet E 55 of 61 4 3 2 1 0.675Volt +/- 5% TDC 0.7A Peak Current 1A OCP Current 1.2A PJP201 VLDOIN_1.35V 2 PAD-OPEN1x1m PR200 1 2 2.2_0603_5% 1.35V_B+ SIR472DP-T1-GE3_POWERPAK8-5~D PQ201 B VTTSNS 2 GND 3 VTTREF 4 VTTREF_1.35V VDDQ 5 +1.35VP S3 1 FB C 2 PR205 1M_0402_1% 1 2 PR204 8.06K_0402_1% 2 1 1 PC213 1U_0603_10V6K PR207 10K_0402_1% S5_1.35V 2 PR208 0_0402_5% 1 2 PC214 @ .1U_0402_16V7K 1 1 PC209 0.033U_0402_16V7~D PC211 220P_0402_50V8J~D 1 2 @ S3_1.35V 1 1U_0402_6.3VX5R <10,43,56,61> SUSP# PC208 10U_0805_6.3V6M 1 2 VTT 1 1.35V_FB 1.35V_B+ PC215 PC207 10U_0805_6.3V6M 19 20 VLDOIN 17 18 BOOT 21 VDDP_1.35V +5VALW PR206 0_0402_5% 1 2 2 1.35VP TDC 13.75A Peak Current 19.64A OCP current 23.57A TYP MAX H/S Rds(on) :12.2mohm , 15mohm L/S Rds(on) :2.7mohm , 3.3mohm PAD VTTGND 6 PC210 1U_0603_10V6K VDD 7 11 VDDP S5 2 PU200 RT8207MZQW _W QFN20_3X3 8 1 VDD_1.35V UGATE CS TON 5 16 PHASE 13 9 1 2 CS_1.35V VDDP_1.35V 12 4 2 <43,56,60> SYSON PGND 5 PR203 5.1_0603_5% +5VALW 1 C 14 10 2 LGATE 1 PC201 330U_2.5V_M 15 4 2 + DL_1.35V PR201 6.04K_0402_1% 1 2 D +0.675VSP SW _1.35V 2 1 SIR818DP-T1_POWERPAK-SO8-5~D PQ203 680P_0603_50V7K 4.7_1206_5% PC212 PR202 2 1 SNUB_1.35V 2 1 +1.35VP PC206 0.22U_0603_10V7K 1 2 3 PL201 0.68UH_PCMC063T-R68MN_15.5A_20% 1 2 DH_1.35V 1 2 3 1 2 PC205 2200P_0402_50V7K 1 2 PC204 0.1U_0402_25V6 1 2 PC203 4.7U_0805_25V6-K 1 2 PC202 4.7U_0805_25V6-K JUMP_43X118 D BOOT_1.35V PGOOD @ PJP200 2 2 1 1 PC216 0.1U_0402_10V7K B+ +1.35VP 1 2 5 +1.35VP @ B @ +0.675VS 2 PJP202 @ PJP203 +0.675VSP 1 1 +1.35V 2 +1.35VP PAD-OPEN 4x4m PAD-OPEN1x1m @ PJP204 1 2 PAD-OPEN 4x4m A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 Issued Date Deciphered Date 2013/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR-1.35VP/0.675VSP Size Document Number Rev 0.1 LA-9331P Date: Friday, June 22, 2012 Sheet 1 56 of 61 5 4 3 2 1 @ PJP300 2 2 1 1 +1.05VP_B+ B+ JUMP_43X118 PC305 4.7U_0805_25V6-K 1 2 PC304 4.7U_0805_25V6-K 2 1 D 1 PR300 100K_0402_5% PC303 2200P_0402_50V7K 2 1 D 5 2 PC302 0.1U_0402_25V6 2 1 +3VS 4 1 2 TRIP_+1.05VP 69.8K_0402_1% EN_+1.05VP 2 TRIP DRVH 9 UG_+1.05VP 3 EN SW 8 SW _+1.05VP FB_+1.05VP 4 VFB V5IN 7 +1.05VP_5V RF_+1.05VP 5 TST DRVL 6 LG_+1.05VP TP PL301 1UH_PCMC063T-1R0MN_11A_20% 1 2 PC308 1 2 11 +1.05VP +5VALW 1 + PR304 4.7_1206_5% 1U_0603_10V6K 2 TPS51212DSCR_SON10_3X3 PR305 470K_0402_1% 1 4 SNB_1.05VP PC309 1000P_0402_50V7K 3 2 1 2 PQ303 FDMC7692S_POW ER33-8-5 PC301 330U_2.5V_M 2 2 PC307 0.22U_0402_16V7K 1 @ 1 <43,56,59> SYSON PQ301 FDMC8884_POW ER33-8-5 1 10 5 VBST 2 PR303 0_0402_5% 1 2 PR301 1 2 2.2_0603_5% BST_+1.05VP PGOOD 3 2 1 PU300 1 PR302 PC306 .1U_0603_25V7K 2 1 C C PR306 2 4.99K_0402_1% 2 1 1 PR307 10K_0402_1% @ PJP301 B 1 +1.05V 2 PAD-OPEN 4x4m B +1.05VP +1.05VP TDC 4.56A Peak Current 6.51A OCP current 7.81A TYP MAX H/S Rds(on) :22mohm , 30mohm L/S Rds(on) :10.8mohm ,13.6mohm A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 Issued Date Deciphered Date 2013/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR-+1.05VP Size Document Number Rev 0.1 LA-9331P Date: Friday, June 22, 2012 Sheet 1 57 of 61 A B C D 1 1 PR400 2 1 +1.5VSP TDC 0.66A Peak Current 0.88A OCP current 1.06A +3VS 2 2 @ PC402 22P_0402_50V8J 2 1 PR405 20K_0402_1% 1 2 1 2 PC405 47P_0402_50V8J 1 2 @ PC404 22U_0805_6.3VAM 2 1 1 2 PR402 30.1K_0402_1% PC403 22U_0805_6.3VAM SYN470DBC_DFN10_3X3 +1.5VSP 2 NC TP 2 1.5VSP_FB SNUB_1.5VSP @ PR404 47K_0402_5% FB 6 1 1 PR403 PC406 .1U_0402_16V7K 11 0_0402_5% 1 2EN_1.5VSP 1 <10,43,56,59> SUSP# EN 7 5 3 1 SVIN LX PL401 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 2 PR401 4.7_0603_5% 8 LX 1.5VSP_LX 2 PC401 0.1U_0402_25V6 PVIN 2 NC 1 PC400 22U_0805_6.3VAM 2 2 PVIN 9 2 1 @ PAD-OPEN 1x2m~D 10 1 1.5VSP_VIN 1 PC407 680P_0402_50V7K PJP400 2 PG PU400 +3VALW 4 10K_0402_5% @ 3 3 PJP401 +1.5VS 2 1 @ PAD-OPEN 1x2m~D +1.5VSP DELL CONFIDENTIAL/PROPRIETARY 4 4 Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWR-1.5VSP Size B C Rev 0.1 LA-9331P Date: A Document Number Friday, June 22, 2012 Sheet D 58 of 61 2 1 +5VALW 2 ISUMP ISUMN <10> VSSSENSE Local sense put on HW site PC507 2200P_0402_50V7K~D 2 1 PC504 0.1U_0402_25V6K~D 2 1 PC506 10U_0805_25V6K 2 1 PC505 10U_0805_25V6K 2 1 PC503 10U_0805_25V6K 2 1 SIR472DP-T1-GE3_POWERPAK8-5~D 5 1 2 PC516 2200P_0402_50V7K~D 2 1 PC515 0.1U_0402_25V6K~D 2 1 PC514 10U_0805_25V6K 2 1 PC513 10U_0805_25V6K 2 1 1 2 B PC530 + 2 1 + 2 1 + 2 100U_25V_M ISUMN 1 PC531 PC537 2200P_0402_50V7K~D 2 1 @ PR547 1_0402_5% 2 1 PC536 0.1U_0402_25V6K~D 2 1 V3N PR544 10_0402_1% PC532 ISUMP @ PR546 1_0402_5% 2 1 100U_25V_M PC524 680P_0603_50V7K PC535 10U_0805_25V6K 2 1 V1N 100U_25V_M PC512 10U_0805_25V6K 2 1 SIR472DP-T1-GE3_POWERPAK8-5~D 1 2 PR541 4.7_1206_5% 2 1 5 3 2 1 4 V2N PL503 0.22UH +-20% PCMB104T-R22MS 35A 4 1 +VCC_CORE 3 2 P1_SW PR552 SNB_CPU_P1 3.65K_0603_1% 1 2 ISEN1 @ PR555 V2N V3N DELL CONFIDENTIAL/PROPRIETARY V1N PR553 10K_0603_1% 1 2 1 LGATE1 +VCC_CORE 2 ISEN2 PC543 680P_0603_50V7K 2.61K_0402_1% 1 2 2 PC542 0.22U_0603_16V7K 4 PQ512 PL504 FBMA-L11-453215-800LMA90T_1812 1 2 2 PR556 10_0402_1% 1 1_0402_5% A ISUMN 2 0.01U_0402_50V7K PR551 PH501 10KB_0402_5%_ERTJ0ER103J 1 2 PQ511 PR554 4.7_1206_5% 2 1 PC545 1 @ PR550 BOOT1 2 1 1 2.2_0603_5% 3 2 1 PC547 .1U_0402_16V7K 2 1 A PC546 1 2 2 330P_0402_50V7K PC544 0.22U_0402_6.3V6K 2 1 4 CPU_B+ PHASE1 PR549 11K_0402_1% 1 2 @ PC541 1 2 ISUMN 4 PQ510 C PL502 0.22UH +-20% PCMB104T-R22MS 35A 4 1 ISUMP <10> VCCSENSE 0.082U_0402_16V7K PC540 0.22U_0402_6.3V6K 2 1 UGATE1 PC538 0.033U_0603_25V7M~D 1 2 5 PC539 0.22U_0402_6.3V6K 2 1 PC529 0.1U_0603_25V7K~D 1 2 3 2 1 PR548 0_0402_5% 1 2 ISEN1 @ PR518 1_0402_5% V2N 1 2 PR536 3 3.65K_0603_1% P2_SW 1 2 PR538 SNB_CPU_P2 10K_0603_1% 1 2 PC534 10U_0805_25V6K 2 1 5 PQ509 ISEN3 ISEN2 SIR472DP-T1-GE3_POWERPAK8-5~D 3 2 1 1 PC528 0.15U_0402_10V6K~D 1 2 SIR818DP-T1-GE3_POWERPAK8-5 1 PC527 330P_0402_50V7K~D 4 PC533 10U_0805_25V6K 2 1 1 2 1 PC525 39P_0402_50V8J PQ508 3 2 1 2 PR543 2K_0402_1% PR534 PQ507 BOOT2 2 1 1 2 2.2_0603_5% PC522 0.22U_0603_16V7K LGATE2 4 SIR472DP-T1-GE3_POWERPAK8-5~D 1 2.94K_0402_1% @ PR516 1_0402_5% V1N 1 2 B+ CPU_B+ PHASE2 PC518 1U_0603_10V6K 5 2 22P_0402_50V8J~D 4 3 2 1 PR537 PQ506 SIR818DP-T1-GE3_POWERPAK8-5 2 PC523 2 1 4 +5VALW 3 2 1 1 2 2 10_0402_1% 1 1 2 1 PC526 PR539 4700P_0402_50V7K~D 909_0402_1% 1 2 PR542 154K_0402_1% 1 2 2 @ FB 1 130K_0402_1% PC520 390P_0402_50V7K 2 1 PR540 0_0402_5% 2 2 1800P_0402_50V8F~D @ PR533 1 PR532 UGATE2 PR530 1_0402_1%~D 1 2 @ @ PC519 2 1 PQ505 PR535 453_0402_1% FB2/VSEN PC521 4700P_0402_50V7K~D 1 @ PC517 1 2 2 39P_0402_50V8J B 2 0_0402_5% @ COMP PR526 0_0402_5%~D 1 2CPU_B+ 5 @ PR529 1 PR523 PU500 ISL95812HRZ-T_QFN32_4x4 PR545 1.5K_0402_1% 2 1 2 PAD @ 2 1 0_0402_5%~D 5 PR528 27.4K_0402_1% 2 1 2 0_0402_5% 33 PWM3 LGATE1 PHASE1 UGATE1 BOOT1 SIR472DP-T1-GE3_POWERPAK8-5~D 1 PH500 3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE @ PR527 1 PC510 47P_0402_50V8J~D +1.05VS COMP FB LGATE2 24 23 22 21 20 19 18 17 ISEN3 VCC_core (Base on PDDG rev 0.8) TDC 33A Peak Current 95A DC Load line -1.5mV/A Icc_Dyn_VID1 60A OCP current 114A DCR 0.82m ohm SIR818DP-T1-GE3_POWERPAK8-5 <43> VR_HOT# NTC LGATE2 VDDP PWM3 LGATE1 PHASE1 UGATE1 BOOT1 VIN 1 PR524 1 2 VR_HOT#1 0_0402_5%~D PR525 1 2 2 SCLK VR_ON PGOOD IMON VR_HOT# NTC COMP FB 2 IMON 1 2 3 4 5 6 7 8 PR531 0_0402_5% 1 2 C SCLK VR_ON 9 10 11 12 13 14 15 16 PR522 0_0402_5%~D 1 2 VCC_PGOOD PR521 100K_0402_1% 2 1 ALERT# SDA SLOPE/PROG1 PROG3 PROG2 BOOT2 UGATE2 PHASE2 0.01U_0402_50V7K FB2/VSEN ISEN3 ISEN2 ISEN1 RTN ISUMN ISUMP VDD PC500 1 2 5 PC509 1U_0603_10V6K 1 2 32 31 30 29 28 27 26 25 <6,17,43> IMVP_PWRGD +VCC_CORE V3N 2 PR510 10K_0603_1% 2 1 SNB_CPU_P3 PR520 0_0402_5%~D 3 2 1 SDA ALERT# VCORE_VDDP 1 +3VS BOOT2 UGATE2 PHASE2 1.91K_0402_1% 1 PC511 0.22U_0603_25V7K PR519 2 3 1 2 PR515 10_0402_1% PR512 24.9K_0402_1% 1 2 4 P3_SW ISUMN 4 PQ504 2 PR514 3.65K_0603_1% ISL6208BCRZ-T_QFN8_2X2 PR509 34K_0402_1% 1 2 0_0402_5% 2 5 3 2 1 PQ503 1 LGATE3 ISUMP PHASE3 5 1 8 2 LGATE PL501 0.22UH +-20% PCMB104T-R22MS 35A 4 1 PC508 680P_0603_50V7K GND TP D PR513 4.7_1206_5% 2 1 PWM PHASE 4 9 SIR818DP-T1-GE3_POWERPAK8-5 3 BOOT3 SIR818DP-T1-GE3_POWERPAK8-5 PR511 1 <43> IMVP_VR_ON PWM3 PR507 49.9K_0402_1%~D 1 2 UGATE3 1 2 4 5 <10> VIDSCLK 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 UGATE FCCM BOOT PQ502 5 VCC CPU_B+ 3 2 1 6 3 2 1 PR505 1 PR506 1 PR508 1 <10> VIDSOUT 4 5 54.9_0402_1% 1 7 <10> VIDALERT_N 1 PR502 2.2_0603_5% PU501 D PR504 2 1 PC502 2 1 110_0402_1%~D 1 75_0402_5% 1 PQ501 2 PR503 2 PC501 0.22U_0603_16V7K 1U_0603_10V6K PR500 2 @ 1 +VCCIO_OUT PR501 0_0402_5%~D 2 2 +5VS 3 2 1 3 SIR472DP-T1-GE3_POWERPAK8-5~D 4 SIR818DP-T1-GE3_POWERPAK8-5 5 @ PR557 2 1 10K_0402_1% Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 +VCC_CORE Size Document Number Date: Friday, June 22, 2012 Rev 0.1 LA-9331P Sheet 1 59 of 61 A B VIN PGND CSOP 19 18 7 CE CSON 17 VFB GND NC 15 VFB 1 PR734 5 4 2 3 4 6 3 1 PQ717A 2N7002BKS 2N SOT363-6 3 PC726 1 2 @ 0.22U_0603_25V7K ISL88731CHRTZ-T_QFN28_5X5~D PC731 1 2 0.1U_0402_25V6K~D <29> + 2 4 2 3 Issued Date PL703 SMB3025500YA_2P 1 2 B+ 100U 25V M PC737 100U 25V M PC736 + 2 1 1 VIN<29> 4 VIN+ Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/22 Deciphered Date 2013/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A PQ717B 2N7002BKS 2N SOT363-6 PQ711 DDTC115EUA-7-F_SOT323 @ @ @ PQ716A 2N7002BKS 2N SOT363-6 6 2 @ SNUB_CHG @ 1 1 <43,57> BATT_TEMP 1 BATT+ TP V1 PQ718B PR737 2N7002BKS 2N SOT363-6 3.3K_1206_5%~D 1 2 3 ACOFF 4 <43> 2 100_0402_5% 16 B+_MXM @ PC707 2200P_0402_25V7K~D 2 1 4 PC723 10U_0805_25V5K~D 2 1 VREF PC722 10U_0805_25V5K~D 2 1 3 PQ714 DL_CHG BATT+ PC721 10U_0805_25V5K~D 2 1 20 2 3 PC720 10U_0805_25V5K~D 2 1 LGATE 2 PR732 0_0402_5% 1 EAO 5 EAI 2 ACOFF 2 LX_CHG PR740 0.004_2512_1% VIN PC706 0.1U_0603_25V7K 2 1 1 23 2 PR731 10_0402_5% 2 1 PHASE 1 PR725 PL702 0.01_1206_1% 5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D 1 2 CHG 1 4 PR728 4.7_1206_5% DH_CHG <43> PC719 680P_0402_50V7K 24 PR714 VDDP_LDO 10K_0402_5% 1 UGATE 3 2 1 VDDP_LDO For DT Mode 4 PC705 4.7U_0805_25V6-K 2 1 PC704 4.7U_0805_25V6-K 2 1 21 4 29 2 4 VDDP 5 12 1 1U_0603_10V6K 5 2 FBO V1 2 2 1 6 PC716 3 2 1 VICM 0.1U_0603_25V7K 1 2 2BST_CHGA SIR472DP-T1-GE3_POWERPAK8-5~D 1 27 25 BST NC 8 PC715 FDMC7692S_POWER33-8-5 SDA BOOT PR711 1 5 SCL 9 PR710 47K_0402_1% PQ701 26 VIN 100K_0402_1% 2 2 VDDSMB 10 CSSN ACOK 11 PR716 0_0603_5% 1 ICOUT PR705 200K_0402_1% 1 2 Dis_G PC709 1U_0603_10V6K 1 PC711 0.1U_0402_25V6K~D 2 PR709 1 10_0402_5% 10_0402_5% PR708 1 PC708 13 28 1 ACIN CSSP DCIN 2 14 PC728 0.1U_0402_10V7K 2 1 PR738 33K_0402_1%~D 2 1 PC735 0.01U_0402_25V7K 2 1 ICREF 22 1 5 CHG_B+ PR713 4.7_0603_5% 1 2 @ ISL8731_ICREF PR739 33K_0402_1%~D 2 1 1 2 0.1U_0402_25V6K~D 1 2 1 2 PR715 210K_0402_1% 4 1 @ ISL8731_REF 4 4 PC703 5600P_0402_25V7K~D 1 2 3 PQ716B 2N7002BKS 2N SOT363-6 <57> EC_SMB_DA1 PR724 0_0402_5% 2 1 @ PC734 0.01U_0402_25V7K 2 1 PQ715 @ SSM3K7002FU_SC70-3 PC733 0.01U_0402_25V7K 2 1 2 1 2 1 3 PC732 .1U_0402_16V7K S DCIN ACSETIN ISL8731_REF PR736 PR735 33K_0402_1%~D 33K_0402_1%~D 2 1 2 1 2 ADP_I <6,43> H_PROCHOT# D PC710 0.1U_0402_10V7K 2 1 PC717 0.1U_0402_10V7K 2 1 PR721 158K_0402_1% 2 1 PR722 0_0402_5% 2 1 @ 2 G PU700 <57> EC_SMB_CK1 PR730 4.7K_0402_5% 2 1 3 <43,57> PC713 0.047U_0603_25V7M 1 2 ISL8731_ICREF ISL8731_EAJ 3 <43,57> BATT_TEMP PC712 1U_0603_25V6K +5VALW PR729 100_0402_1% @ PC729 1U_0603_25V6K PR712 10_1206_1% 1 2 PR719 2 49.9K_0402_1% 1 SI7149DP PQ704 1 2 3 PL701 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 2 VIN PC714 1000P_0402_50V7K 1 2 1 1 2 3 2 4 1 PR702 200K_0402_1% 2 1 2 6 PQ718A 2N7002BKS 2N SOT363-6 ACOFF @ Back_G2 CSIP 1 2 3 4 2 10K_0402_5% 7> BATT_TEMP ACIN PQ713 DDTC115EUA-7-F_SOT323 1 PR723 2 PC702 0.1U_0603_25V7K 3 1 PR720 1 5 Back_G1 CSIN VIN <43,57> BATT_TEMP 47K_0402_5% <17,29,43,47,57> ACIN 1 2 CC = 3.52A (Normal) 5 4 2 @ 2 ACIN B+ 1 PR707 150K_0402_1% 5 1 2 3 CV = 13.3V PR703 0.005 +-1% 2512 Back_G2 PQ710B PR717 2N7002BKS 2N SOT363-6 100K_0402_1% VDDP_LDO 2 1 6 1 2 PQ710A 2N7002BKS 2N SOT363-6 3 2 1 2 3 5 P3 SI7149DP PQ706 5 1 2 PQ709 DDTC115EUA-7-F_SOT323 1 PQ707 PDTA144EU PNP_SOT323 V1 Iada=0~4.62A(90W) ADP_I = 19.9*Iadapter*Rsense 1 2 3 Back_G1 PR704 200K_0402_1% 2 PC701 2.2U_0805_25V6K PR706 1 2 2 1 3.3_1210_5% 1 2 PR701 1 3.3_1210_5% 4 5 P3 SI7149DP PQ703 P2 1 2 3 D P2 PQ705 SI7149DP 2 PQ702 SI7149DP C VIN B C PWR-Charger Document Number Rev 0.1 LA-9331P Friday, June 22, 2012 Sheet D 60 of 61 5 4 3 2 1 Based on PDDG rev 0.8 Table 5-1. +VCC_CORE +VCC_CORE 1 D 1 2 1 PC900 10U_0805_4VAM 2 1 2 1 PC901 10U_0805_4VAM 1 PC909 10U_0805_4VAM 2 2 1 PC902 10U_0805_4VAM 1 PC910 10U_0805_4VAM 2 2 1 PC903 10U_0805_4VAM 1 PC911 10U_0805_4VAM 2 2 1 PC912 10U_0805_4VAM 2 1 + PC904 10U_0805_4VAM PC905 + 1 PC906 + 1 PC907 + 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 2 2 2 2 1 PC908 + 470U_D2_2VM_R4.5M~D 2 D PC915 470U_D2_2VM_R4.5M~D 1 PC913 10U_0805_4VAM 2 PC914 10U_0805_4VAM +VCC_CORE 1 2 C 1 PC917 22U_0805_6.3VAM 2 1 2 1 PC922 22U_0805_6.3VAM 2 1 2 2 2 2 2 2 2 2 2 PC921 22U_0805_6.3VAM C 1 PC925 22U_0805_6.3VAM 1 PC937 22U_0805_6.3VAM 1 PC941 22U_0805_6.3VAM 2 1 PC920 22U_0805_6.3VAM 1 PC924 22U_0805_6.3VAM 1 PC936 22U_0805_6.3VAM 1 PC940 22U_0805_6.3VAM 2 1 PC919 22U_0805_6.3VAM 1 PC923 22U_0805_6.3VAM 1 PC935 22U_0805_6.3VAM 1 2 1 PC918 22U_0805_6.3VAM 2 PC926 22U_0805_6.3VAM 1 PC938 22U_0805_6.3VAM 2 PC939 22U_0805_6.3VAM 1 PC942 22U_0805_6.3VAM 2 PC943 22U_0805_6.3VAM B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 PROCESSOR DECOUPLING Size Document Number Date: Friday, June 22, 2012 Rev 0.1 LA-9331P Sheet 1 61 of 61 www.s-manuals.com
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