Compal LA 9531P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-9531P V5WE2, V5WC2, V5WT2 - Schematics. Free.

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C

D

E

Compal Confidential
Model Name : V5WE2/T2/C2 (EA/EG/BA50_HW)
File Name : LA-9531P
1

1

Compal Confidential
2

2

EA50_HW M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx Point-LP)
AMD MARS / SUN

2013-04-11

3

3

REV:1.0

4

4

ZZZ

Part Number
DAZ0VR00100
V5WE2_PCB

Description
PCB V5WE2 LA-9531P LS-9531P/9532P

2012/07/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/07/10

Deciphered Date

Title

Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Thursday, April 11, 2013
E

1

of

52

Rev
1.0

A

B

C

D

E

CRT Conn.

Fan Control

page 28

1

page 36

DP to VGA
ITE IT6511FN

HDMI Conn.

eDP Conn.

page 26

1

page 25

page 27

eDP

DP x 2 lanes

HDMI x 4 lanes

2.7GT/s

2.97GT/s

DDI

204pin DDR3L-SO-DIMM X1

Intel Haswell ULT

page 15

BANK 0, 1, 2, 3

Memory BUS
Dual Channel

Haswell ULT

204pin DDR3L-SO-DIMM X1

1.35V DDR3L 1333/1600

Processor

page 16

BANK 4, 5, 6, 7

MINI Card
WLAN
USB port 4 page 31

2

OPI

AMD SUN/MARS
with DDR3 x4 or 8
page 17~23

PCIe 2.0
5GT/s

PCIe 2.0 x4
5GT/s

port 4

port 5

Flexible IO

Lynx Point - LP
PCH

PCIe 2.0
5GT/s

USBx8
SATA3.0

port 3

LAN(GbE)

6.0 Gb/s

SATA HDD
Conn.

6.0 Gb/s

3

port 2

page 32

page 04~14

LPC BUS

2 in 1
(SD)

USB/B (port 1,2)
page 33

USB port 7

Finger
Print

2

(port 5)
page 26

USB

page 25

48MHz

3.3V 24MHz

Touch
Screen

ENE
KB9012
page

(port 6)
page 25

USB

HDA Codec
ALC3225

page 36

SPI

3

SPI ROM x2

CLK=24MHz

page 30

Int. Speaker

page 7

Int. MIC

page 36

Combo Jack

page 36

page 36

34

Sub Board
page 6

Touch Pad
LS-9531P

Power On/Off CKT.

page 38

page 35

page 33

EC ROM x1
(reserved)
page 34

LS-9532P
DC/DC Interface CKT.

Int.KBD

page 35

PWR/B

page 35

4

USB port 0
page 33

1168pin BGA

Card Reader

RTC CKT.

CMOS
Camera

HD Audio

SATA CDROM
Conn.

page 32

29

USB 2.0
conn x2

SATA3.0

port 0

Boardcom
57786Xpage

USB 3.0
conn x1

USB/B

(port 1,2)
page 33

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Power Circuit DC/DC

2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

V5WE2 M/B LA-9531P Schematic

Date:

A

Block Diagrams

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 39~49
B

C

D

Tuesday, March 26, 2013

Sheet
E

2

of

52

Rev
1.0

A

B

C

D

SIGNAL

STATE

Voltage Rails
VIN

1

Description
Adapter power supply (19V)

S1

S3

S5

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

HIGH

ON

ON

ON

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

Board ID / SKU ID Table for AD channel

OFF

OFF

ON

OFF

OFF

+0.95VSDGPU

+0.95VSDGPU switched power rail for GPU

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.35V

+1.35V power rail for DDR3L

ON

ON

OFF

Board ID

+1.5VS

+1.5V power rail for CPU

ON

OFF

OFF

0
1
2
3
4
5
6
7

ON

OFF

OFF

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VLP

B+ to +3VLP power rail for suspend power

ON

ON

ON

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+3VSDGPU

+3VS to +3VSDGPU power rail for GPU

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VS

+3VALW to +5VS power rail

ON

OFF

OFF

+RTCVCC

RTC power

ON

ON

ON

Address

Smart Battery

0001 011X

EC SM Bus2 address
Device
On Board Thermal Senser

Address
0100 110x

VGA Internal Thermal Senser 0100 000x
G Senser

USB 2.0

1001 000x

JDIMM1

ChannelB

DIMM1

1001 010x

JDIMM2

3

PCB Revision
0.1
0.2
0.3
0.4
0.5
1.0

3 External
USB Port
USB Port(Left 3.0)
USB Port(Right 2.0)
USB Port(Right 2.0)

Port
0
1
2
3
4
5
6
7

Address
DIMM0

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

USB Port Table

0011 000x

PCH SM Bus address
ChannelA

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

EHCI1

Mini Card (WLAN+BT)

Camera

USB 3.0 Port
0
1
XHCI
2
3

4

USB Port(Left 3.0)

BTO Item
BOM Structure
Unpop
@
Connector
CONN@
EC 932
940@
EC 9012
9012@
UMA@
UMA Component
VGA@
AMD GPU
1 SPI ROM
1ROM@
2 SPI ROM
2ROM@
Assembly Level
45@
Cable for Power
45PWR@
KB Backlight
BL@
Debug Only
DEG@
EMC Component
EMC@
Reservec for EMC
XEMC@
eDP to LVDS
TL@
TPM Module
TPM@
G-Sensor
GSEN@
V5WE2/T2/C2
EA50@
Reserved
BA51@
Touch Screen
TS@
For IOAC
IOAC@
For EDP panel
EDP@
Mars component
SUN component
VRAM x 8pcs

128@

VRAM Selection
Micron 4G x 8
Hynix 2G x 4
Hynix 2G x 8

X76@
X7601@
X7603@
X7604@

2012/07/10

2

3

MARS@
SUN@

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Option Table

Board ID
0
1
2
3
4
5
6
7

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Device

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

BOARD ID Table

2

EC SM Bus1 address

ON

HIGH

HIGH

ON

+1.5VSDGPU power rail for GPU

Clock

HIGH

+1.05V power rail for CPU

+1.8VSDGPU power rail for GPU

+VS

LOW

+0.675VS power rail for DDR3L terminator

+1.5VSDGPU

+V

HIGH

+0.675VS

+1.8VSDGPU

+VALW

S1(Power On Suspend)

+1.05VS_VTT

Device

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON

Power Plane

E

2013/07/10

Deciphered Date

Title

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Thursday, April 11, 2013
E

3

of

52

Rev
1.0

5

4

3

2

DP to CRT

27
27
27
27

C54
C55
B58
C58
B55
A55
A57
B57

CPU_DP1_N0
CPU_DP1_P0
CPU_DP1_N1
CPU_DP1_P1

D

26
26
26
26
26
26
26
26

HDMI

C51
C50
C53
B54
C49
B50
A53
B53

CPU_DP2_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

1

HASWELL_MCP_E

U1A

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

DDI

EDP

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL

C45
B46
A47
B47

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

25
25
25
25

C47
C46
A49
B49

D

A45
B45
D20
A43

EDP_AUXN 25
EDP_AUXP 25
EDP_COMP R1 1

2 24.9_0402_1%

+VCCIOA_OUT

Trace width=20 mils,Spacing=25mil,Max length=100mils
EDP_DISP_UTIL 25

Rev1p2

1 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

Reserved for ESD
1
C94
XEMC@

T20
T2

+1.05VS_VTT

2

1
R68
62_0402_5%

1

34,39,40 H_PROCHOT#
C

Reserved for ESD

2

R184
470_0603_5%

DIMM_DRAMRST# 15,16

C96
6.8P_0402_50V8C
XEMC@

R8
56_0402_5%
1
2 H_PROCHOT#_R K63

1
C95
XEMC@
1
R6

2 6.8P_0402_50V8C

1
C60
XEMC@

2 6.8P_0402_50V8C

2 10K_0402_5% H_CPUPWRGD

C61

PROC_DETECT
CATERR
PECI

MISC

PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO

JTAG

PROCHOT

PROCPWRGD

THERMAL

R11
R13
R41

Close to AV15

1
1
1

2 200_0402_1% SM_RCOMP0
AU60
2 120_0402_1% SM_RCOMP1
AV60
2 100_0402_1% SM_RCOMP2
AU61
DIMM_DRAMRST# AV15
AV61
DDR_PG_CTRL
15 DDR_PG_CTRL

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

DDR3

DDR3 Compensation Signals

Reserved for ESD 1120

J62
K62
E60
E61
E59
F63
F62

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R

@
@
@
@
@
@
@

T157
T158
T159
T160
T161
T162
T163

@
@

T164
T165

C

PWR

Reserved for ESD

2

1

D61
K61
N62

@
@

34 H_PECI

+1.35V

HASWELL_MCP_E

U1B

2 6.8P_0402_50V8C

J60
H60
H61
H62
K59
H63
K60
J61

XDP_BPM#0_R
XDP_BPM#1_R
@
T148
@
T149
@
T150
@
T151
@
T152
@
T153

Rev1p2

2 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

B

B

U1

A

U1

CPU_SR16Q_C1
SR16Q@

CPU_SR170_C1
SR170@

SA00006SX70

SA00006SMB0

A

U1

U1

U1

U1

CPU_QEK2_C0
QEK2@

CPU_QEK4_C0
QEK4@

CPU_QEVG_C0
QEVG@

CPU_QEVE_C0
QEVE@

SA00006SJ40

SA00006NM50

SA00006SX30

SA00006SM30

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(1/11) DDI,MSIC,XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Monday, April 08, 2013

Sheet
1

4

of

52

Rev
1.0

5

4

U1C

3

2

HASWELL_MCP_E

U1D

D

C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

1

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2

DDR CHANNEL A

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#1
SA_CLK_DDR1

AU43
AW43
AY42
AY43

AY34
AW34
AU34
AU35
AV35
AY41

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDRA_CKE0_DIMMA 15
DDRA_CKE1_DIMMA 15

AP33
AR32
AP32 DDRA_ODT0

15
15
15
15

DDRA_CS0_DIMMA# 15
DDRA_CS1_DIMMA# 15
@

T4
DDR_A_RAS# 15
DDR_A_WE# 15
DDR_A_CAS# 15
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15

AU36 DDR_A_MA0
AY37 DDR_A_MA1
AR38 DDR_A_MA2
AP36 DDR_A_MA3
AU39 DDR_A_MA4
AR36 DDR_A_MA5
AV40 DDR_A_MA6
AW39DDR_A_MA7
AY39 DDR_A_MA8
AU40 DDR_A_MA9
AP35 DDR_A_MA10
AW41DDR_A_MA11
AU41 DDR_A_MA12
AR35 DDR_A_MA13
AV42 DDR_A_MA14
AU42 DDR_A_MA15
AJ61 DDR_A_DQS#0
AN62 DDR_A_DQS#1
AM58 DDR_A_DQS#2
AM55 DDR_A_DQS#3
AV57 DDR_A_DQS#4
AV53 DDR_A_DQS#5
AL43 DDR_A_DQS#6
AL48 DDR_A_DQS#7
AJ62 DDR_A_DQS0
AN61 DDR_A_DQS1
AN58 DDR_A_DQS2
AN55 DDR_A_DQS3
AW57DDR_A_DQS4
AW53DDR_A_DQS5
AL42 DDR_A_DQS6
AL49 DDR_A_DQS7
AP49
AR51
AP51

15 DDR_A_D[0..63]
15 DDR_A_MA[0..15]
15 DDR_A_DQS#[0..7]
15 DDR_A_DQS[0..7]

SM_DIMM_VREFCA 15
SA_DIMM_VREFDQ 15
SB_DIMM_VREFDQ 16

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

HASWELL_MCP_E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

DDR CHANNEL B

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#1
SB_CLK_DDR1

AY49
AU50
AW49
AV50

16
16
16
16

DDRB_CKE0_DIMMB 16
DDRB_CKE1_DIMMB 16
D

AM32
AK32

DDRB_CS0_DIMMB# 16
DDRB_CS1_DIMMB# 16

AL32 DDRB_ODT0
AM35
AK35
AM33

@

T5
DDR_B_RAS# 16
DDR_B_WE# 16
DDR_B_CAS# 16

AL35
AM36
AU49

DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16

AP40 DDR_B_MA0
AR40 DDR_B_MA1
AP42 DDR_B_MA2
AR42 DDR_B_MA3
AR45 DDR_B_MA4
AP45 DDR_B_MA5
AW46DDR_B_MA6
AY46 DDR_B_MA7
AY47 DDR_B_MA8
AU46 DDR_B_MA9
AK36 DDR_B_MA10
AV47 DDR_B_MA11
AU47 DDR_B_MA12
AK33 DDR_B_MA13
AR46 DDR_B_MA14
AP46 DDR_B_MA15

C

AW30DDR_B_DQS#0
AV26 DDR_B_DQS#1
AN28 DDR_B_DQS#2
AN25 DDR_B_DQS#3
AW22DDR_B_DQS#4
AV18 DDR_B_DQS#5
AN21 DDR_B_DQS#6
AN18 DDR_B_DQS#7
AV30 DDR_B_DQS0
AW26DDR_B_DQS1
AM28 DDR_B_DQS2
AM25 DDR_B_DQS3
AV22 DDR_B_DQS4
AW18DDR_B_DQS5
AM21 DDR_B_DQS6
AM18 DDR_B_DQS7

16 DDR_B_D[0..63]
16 DDR_B_MA[0..15]
16 DDR_B_DQS#[0..7]

B

B

16 DDR_B_DQS[0..7]

Rev1p2

3 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

Rev1p2

4 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(2/11) DDRIII

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

5

of

52

Rev
1.0

5

4

3

2

1

PCH_RTCX1

2
10M_0402_5%

PCH_RTCX2
+RTCVCC

Y1
32.768KHZ_12.5PF_Q13FC135000040
2
1

1
D

2

R69
20K_0402_1%
1
2
1
2
R70
20K_0402_1%
C150
1U_0402_10V6K

1
C153
15P_0402_50V8J

C154
15P_0402_50V8J

2

C149
1U_0402_10V6K

ME CMOS

2

R72

1
@

PCH_RTCX1
PCH_RTCX2
2 1M_0402_5% SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

1

2
1
1

R73
R74

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

CMOS

RTCRST close RAM door

T6
T7
T8
T9

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
@
HDA_SDOUT
@
@
@

AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

2 330K_0402_5%
2 330K_0402_5%

@

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

RTC

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

36 HDA_SDIN0

PCH_INTVRMEN

AW5
AY5
AU6
AV7
AV6
AU7

R71
0_0603_5%

2

+RTCVCC

HASWELL_MCP_E

U1E

+RTCVCC

1

1

1
R101

INTVRMEN
H：Integrated VRM enable
L：Integrated VRM disable

AUDIO

SATA

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

*

T95
51_0402_5% 1

@

2 R97
T21
T19
T15
T10
T11
T22
T12

HDA for AUDIO
C

1
2
3
4

36 HDA_BITCLK_AUDIO
36 HDA_SYNC_AUDIO
36 HDA_RST_AUDIO#
36 HDA_SDOUT_AUDIO

RP14 EMC@
8
7
6
5

@
PCH_JTAG_RST#
PCH_JTAG_TCK
@ PCH_JTAG_TDI
@ PCH_JTAG_TDO
@ PCH_JTAG_TMS
@
@
@ PCH_TCK_JTAGX
@

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD

SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED

JTAG

J5
H5
B15
A15

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

32
32
32
32

HDD

J8
H8
A17
B17

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

32
32
32
32

ODD

D

J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11 @
K10 @
C12
U3

R937
0_0402_5%
1
2
@
PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
SATA_IREF
T13
T14
SATA_RCOMP
PCH_SATALED#
R10 1
10K_0402_5%

EC_SCI# 34,9

PCH_GPIO34 9
PCH_GPIO35 9
PCH_GPIO36 9
PCH_GPIO37 9

2

R75

1

@

+1.05VS_ASATA3PLL

2 0_0603_5%

within 500 mils

R2

1

2 3.01K_0402_1%

PCH_SATALED# 35
+3VS
C

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDOUT

Rev1p2

5 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

33_0804_8P4R_5%
R163 1 9012@ 2 0_0402_5%

34 HDA_SDO

R161 1 940@

32,34,7 SPI_WP1#_R

2 4.7K_0402_5%

ME Debug

W=20mils

trace width 10mil

+RTCBATT

+CHGRTC

B

W=20mils
+RTCVCC
B

D23

2
1
3
BAS40-04_SOT23-3

1

C151
0.1U_0402_16V4Z

2

+RTCBATT

2

3 1

R446
1K_0402_5%
@

20mil

+RTCBATT_R

20mil

A

2

D32
CHN202UPT_SC70-3
@

C168
0.1U_0402_16V4Z
@

2

1

-

+RTCVCC

1

A

+

2

+CHGRTC

1

+RTCBATT

JBATT1
LOTES_AAA-BAT-054-K01
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

SP07000H700

Deciphered Date

2013/07/10

Title

HSW MCP(3/11) RTC,SATA,XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Thursday, April 18, 2013

Sheet
1

6

of

52

Rev
1.0

5

4

3

2

HASWELL_MCP_E

U1F

PCH_GPIO18

C43
C42
U2

PCH_GPIO19

B41
A41
Y5

XTAL24_IN

2
1M_0402_5%

1
R48

XTAL24_OUT

9 PCH_GPIO18

Y2
24MHZ_12PF_X3G024000DC1H
1
3
2
4

9 PCH_GPIO19

PCIE LAN

1
C2
10P_0402_50V8J

C3
10P_0402_50V8J

2

2

1

D

WLAN

29 CLK_PCIE_LAN#
29 CLK_PCIE_LAN
+3VS
29 LAN_CLKREQ#
31 CLK_PCIE_MINI1#
31 CLK_PCIE_MINI1
31,8 MINI1_CLKREQ#

CLK_PCIE_LAN#
CLK_PCIE_LAN
2 10K_0402_5%
R52 1

C41
B42
AD1

CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1_CLKREQ#

B38
C37
N1

1

+3VS

9 PCH_GPIO23

R216
10K_0402_5%
@

2

VGA_CLKREQ#

A39
B39
U5

PCH_GPIO23

B37
A37
T2

CLK_PEG_VGA#
CLK_PEG_VGA

17 CLK_PEG_VGA#
17 CLK_PEG_VGA

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

CLOCK

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

SIGNALS

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

1
2

34,35 LPC_AD0
34,35 LPC_AD1
34,35 LPC_AD2
34,35 LPC_AD3
34,35 LPC_FRAME#

PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP1#
PCH_SPI_HOLD1#
DEG@
DEG@
DEG@
DEG@
DEG@

2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

A25
B25

XTAL24_IN
XTAL24_OUT

K21 @
M21 @
C26
C35
C34
AK8
AL8

T16
T17
XCLK_BIASREF

1
1
1
1

R140
R141
R142
R148

AN15
AP15

2
2
2
2

CLKOUT_LPC0
CLKOUT_LPC1

B35
A35

R78

1

2 3.01K_0402_1%

+1.05VS_AXCK_LCPLL

D

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 EMC@ 1 22_0402_5%
2 TPM@ 1 22_0402_5%

R390
R395

CLK_BCLK_ITP#
CLK_BCLK_ITP

@
@

CLK_PCI_LPC 34
CLK_PCI_TPM 35

T184
T183

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
Rev1p2

HASWELL_MCP_E

U1G

1
1
1
1
1

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22

AU14
LPC_AD0
AW12
LPC_AD1
AY12
LPC_AD2
AW11
LPC_AD3
LPC_FRAME# AV12

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

R572
R599
R603
R602
R604

RSVD
RSVD
DIFFCLK_BIASREF

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19

6 OF 19

C

PCH_SPI_CLK_1_R
PCH_SPI_CS0#_1_R
PCH_SPI_MOSI_1_R
PCH_SPI_MISO_1_R
32 SPI_HOLD1#_R

XTAL24_IN
XTAL24_OUT

HASWELL-MCP-E-ULT_BGA1168
@

VGA_CLKREQ#
R221
10K_0402_5%

32
32
32
32

1

AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1

PCH_SPI_CLK_1
PCH_SPI_CS0#
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_HOLD1#

LAD0
LAD1
LAD2
LAD3
LFRAME

SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74

LPC

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

SPI

C-LINK

CL_CLK
CL_DATA
CL_RST

D29 design for Debug
board flash SPI ROM
(can be short after MP)

PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

AF2
AD2
AF4

@
@
@

PCH_GPIO11 9
PCH_SMBCLK 31
PCH_SMBDATA 31
PCH_GPIO60 9

C

PCH_GPIO73 9
+3VALW_PCH
T23
T24
T25

SML0CLK
RP8
SML0DATA
PCH_SMBDATA
PCH_SMBCLK
SML1CLK
SML1DATA

1
2
3
4

8 2.2K_0804_8P4R_5%
7
6
5

R114 1
R113 1

2 2.2K_0402_5%
2 2.2K_0402_5%

Rev1p2

7 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

+BIOS_SPI

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

+3VS
+3VS

C66

1

2 940@ RB751V40_SC76-2
2

Q7A
DMN66D0LDW-7_SOT363-6

+BIOS_SPI

8
7
6
5

RP19
PCH_SPI_IO3_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1

PCH_SPI_MOSI_1
PCH_SPI_CLK_1
PCH_SPI_IO3_1
PCH_SPI_MISO_1

EN25QH64-104HIP_SO8
1ROM@

R105 1 1ROM@ 2 1K_0402_5%
R106 1 1ROM@ 2 1K_0402_5%

PCH_SPI_IO2_1
PCH_SPI_IO3_1

R103 1 2ROM@ 2 1K_0402_5%
R102 1 2ROM@ 2 1K_0402_5%
R564 1 940@ 2 1K_0402_5%

PCH_SPI_HOLD1#
PCH_SPI_WP1#

A

PCH_SPI_CS1#
PCH_SPI_MISO_2
PCH_SPI_IO2_2

1
2
3
4

CS#
DO
WP#
GND

SA00004G600

5

D_CK_SDATA 15,16,37

4

D_CK_SCLK

D_CK_SCLK 15,16,37

Q7B
DMN66D0LDW-7_SOT363-6

VCC
HOLD#
CLK
DI

8
7
6
5

+3VS

1 PCH_SPI_CLK_1
XEMC@ 33_0402_5%

PCH_SPI_IO3_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

1

SML1CLK

Q8A
DMN66D0LDW-7_SOT363-6

6

PU 2.2K at EC side (+3VS)

1

EC_SMB_CK2 18,24,34

SML1DATA

3

4

EC_SMB_DA2 18,24,34

Q8B
DMN66D0LDW-7_SOT363-6

Reserve for EMI(Near SPI ROM)

2ROM is SPI ROM 2M + 4M Byte
RP19

MX25L6406EM2I-12G_SO8
940@

3

PCH_SMBCLK

2 0.1U_0402_16V7K
2ROM@
RP20
8 PCH_SPI_MOSI
PCH_SPI_MOSI_2 1
2
7 PCH_SPI_CLK
PCH_SPI_CLK_2
3
6 PCH_SPI_HOLD1#
PCH_SPI_IO3_2
5 PCH_SPI_MISO
PCH_SPI_MISO_2 4
33_0804_8P4R_5%
2ROM@

C67

EN25QH32-104HIP_SO8
2ROM@

SPI ROM ( 8MByte for Chrome)
U6

8 PCH_SPI_MOSI
7 PCH_SPI_CLK
6 PCH_SPI_HOLD1#
5 PCH_SPI_MISO
1ROM@
15_0804_8P4R_5%

+3VS

U7
33_0402_5% 2 2ROM@ 1 R109

D_CK_SDATA

Reserve for EMI(Near SPI ROM)

C152
10P_0402_50V8J
1
2
2
R104
XEMC@

SPI ROM ( 4MByte )
PCH_SPI_WP1#

1
2
3
4

2

32,34,6 SPI_WP1#_R

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

1
5

1
2
3
4

PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_IO2_1

6

5

R108
15_0402_5%
2 1ROM@ 1

PCH_SMBDATA

R119
4.7K_0402_5%
B

0.1U_0402_16V7K

U6
PCH_SPI_WP1#

R116
4.7K_0402_5%

1

1

1

D29

2

SPI ROM ( 8MByte )

B

2

2

+3VS
R305 1 9012@ 2 0_0402_5%

U6

R108
33_0402_5%
2ROM@
2
1

C453
10P_0402_50V8J
1
2
2
R402
XEMC@

1 PCH_SPI_CLK_2
XEMC@ 33_0402_5%

2012/07/10

Issued Date
33_0804_8P4R_5%
2ROM@

EN25QH16-104HIP_SO8
2ROM@

SA00004UG00

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

SD309330A80

A

Deciphered Date

2013/07/10

Title

HSW MCP(4/11) CLK,SPI,SMBUS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

3

2

Tuesday, March 26, 2013

Sheet
1

7

of

52

Rev
1.0

5

4

3

2

1

1

+3VS

R59

32 XDP_DBRESET#

1 DEG@ 2 0_0402_5%

2

R227
10K_0402_5%

DSWODVREN - On Die DSW VR Enable

H：Enable(DEFAULT)
* L：Disable

SYS_RESET#

R124 1
R125 1

D

SUSWARN#

1

@

SYS_PWROK R61
R62
R63

1
1
1

@

34 PCH_PWROK
11,34 VCCST_PG_EC

PCH_PWROK_R

@

2

R117 1

PCH_RSMRST#

1

@

R110 1

@

R79

34 PCH_RSMRST#
9 SUSWARN#
34 PBTN_OUT#

2 10K_0402_5%

Note: EC is +3VL change to @

+3VALW_PCH

R156 1

AK2
AC3
AG2
AY7
AB5
AG7

SUSACK#
SYS_RESET#
2 0_0402_5% SYS_PWROK_R
2 0_0402_5%
PCH_PWROK_R
2 0_0402_5%
PM_APWROK

1 R64

0_0402_5%
PLT_RST#

2 0_0402_5% PCH_RSMRST#_R
SUSWARN#
2 0_0402_5%
PBTN_OUT#_R
PCH_ACIN
2 8.2K_0402_5% PCH_BATLOW#
T31
@

AW6
AV4
AL7
AJ8
AN4
AF3
AM5

SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST

AW7
AV5
AJ5

DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

V5
AG4
AE6
AP5

DSWODVREN
PCH_RSMRST#_R
PCH_PCIE_WAKE#
1
1K_0402_5%
1
8.2K_0402_5%
CLKRUN#
LPCPD#
SUSCLK
PM_SLP_S5#

AJ6
AT4
AL5
AP4
AJ7

PM_SLP_S4#
PM_SLP_S3#
@
@
PM_SLP_LAN#

1
C

5

(Have internal PD)
PCH_PWROK

R207
10K_0402_5%
@

B

11,46 VGATE

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

eDP SIDEBAND

2
VCC

A
Y

3

B8
A9
C6

24,25 PCH_INV_PWM
34 ENBKL
25 PCH_ENVDD

5
4

EC_SMI#
VGA_ON
DGPU_HOLD_RST#
PCH_GPIO80
T26

34 EC_SMI#
38,9 VGA_ON
9 DGPU_HOLD_RST#

R310
10K_0402_5%
@
VGATE_3V

9 PCH_GPIO55
37 G_SEN_INT
9 PCH_GPIO51

2

U17

NC

+3VS

1

+1.05VS_VTT

2

HASWELL_MCP_E

U1I

2

+3VS

1

0: Port B or C is not detected

1

U43
MC74VHC1G08DFT2G_SC70-5
@

2

R208
10K_0402_5%

R65
0_0402_5%
1

C

1: Port B or C is detected

G

A

SYS_PWROK

3

1

P
Y

1

VGATE_3V

+3VALW_PCH

DDPC_CTRLDATA: Port C Detected

*
4

2

DDPB_CTRLDATA: Port B Detected

PCH_ACIN

B

T29

not support Deep S4,S5 can NC

HASWELL-MCP-E-ULT_BGA1168
@

+3VS

2

@

PM_SLP_S4# 34
PM_SLP_S3# 34

T30
T96
R118 1
@
10K_0402_5%

RB751V40_SC76-2

PCH_PWROK

T27
T28

Rev1p2

8 OF 19

Note: Deep Sx need use EC GPIO for
ACPRESENT function

2

34,39,41 ACIN

D

PCH_PCIE_WAKE# 29
+3VALW_PCH
+3VS
CLKRUN# 35
LPCPD# 35
SUSCLK 34
PM_SLP_S5# 34

2 R120
2 R157

@
@

SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN

+3VALW_PCH

R245
100K_0402_5%
@
@ D21
1
2

2 330K_0402_5%
2 330K_0402_5%

@

SYSTEM POWER MANAGEMENT

R206
2 0_0402_5%

34,35 PLT_RST#

+RTCVCC

HASWELL_MCP_E

U1H

VGATE_3V 34

U6
P4
N4
N2
AD4

@

U7
L1
L3
R5
L4

PCH_GPIO55
G_SEN_INT
Project_ID1
PCH_GPIO51
Project_ID0

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

DISPLAY

GPIO

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD
EDP_HPD

B9
2 2.2K_0402_5%
C9
R271 1
D9 DDI2_CTRL_CK
DDI2_CTRL_CK 26
D11 DDI2_CTRL_DATA
DDI2_CTRL_DATA 26

C5
B6
B5
A6

DDI1_AUX_DN

DDI1_AUX_DN 27

DDI1_AUX_DP

DDI1_AUX_DP 27

C8
A8
D6

CPU_DP_HPD 27
CPU_HDMI_HPD 26
CPU_EDP_HPD 25

B

GND
74AUP1G07GW_TSSOP5
@
9 OF 19

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@
+3VS

R405
0_0402_5%
2
1
@

R403
0_0402_5%
2
1
@

+3VS
MINI1_CLKREQ# 31,7
DEVSLP0 32,9

+3VS

R391
100K_0402_5%
VGA@

IN1
IN2

OUT

4

PLT_RST_BUF# 29,31

1

2

R416
100K_0402_5%

2

U30
MC74VHC1G08DFT2G_SC70-5

1
2

R214
10K_0402_5%

R215
10K_0402_5%

1

2

Project_ID0

Project ID

2

Project_ID1

R204
10K_0402_5%
@

2

R205
10K_0402_5%
@

1

A

U37
MC74VHC1G08DFT2G_SC70-5
VGA@

+3VS

1

+3VS

1

PLT_RST#

PLTRST_VGA# 17

2

4

VCC

OUT

GND

IN2

3

IN1

1

2

GND

1

DGPU_HOLD_RST#

3

PLT_RST#

VCC

5

8
G_SEN_INT
7
PCH_GPIO80
6
MINI1_CLKREQ#
5
DEVSLP0
10K_0804_8P4R_5%

5

RP27 1
2
3
4

*V5WE2/T2
Reserved
Reserved
Reserved

Project_ID1 Project_ID0
GPIO54 GPIO53
0
0
1
0
1
0
1
1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

HSW MCP(5/11) PM,GPIO,DDI

3

2

Tuesday, March 26, 2013

Sheet
1

8

of

52

Rev
1.0

5

4

3

2

1

+3VS
+3VS

RP24 1
2
3
4
D

RP25 1
2
3
4
RP26 1
2
3
4
RP16 1
2
3
4
RP28 1
2
3
4
RP29 1
2
3
4
RP30 8
7
6
5

C

RP31 8
7
6
5
RP32 8
7
6
5
R311 1
10K_0402_5%

1
PCH_GPIO67
2
PCH_GPIO65
3
PCH_GPIO6
4
PCH_GPIO64
10K_0804_8P4R_5%
1
PCH_GPIO84
2
PCH_GPIO0
3
PCH_GPIO3
4
PCH_GPIO89
10K_0804_8P4R_5%
1
PCH_GPIO17
2
PCH_GPIO23
3
PCH_GPIO76
4
PCH_GPIO50
10K_0804_8P4R_5%
2
PCH_GPIO70

PCH_GPIO51 8
PCH_GPIO55 8

RP36

1
2
3
4

8
7
6
5

PCH_GPIO88
PCH_GPIO92
PCH_GPIO85
PCH_GPIO39
10K_0804_8P4R_5%

+1.05VS_VTT

1

8
PCH_GPIO51
7
PCH_GPIO83
6
PCH_GPIO55
5
SERIRQ
10K_0804_8P4R_5%
8
EC_IN_RW
7
PCH_GPIO69
6
PCH_GPIO4
5
PCH_GPIO7
10K_0804_8P4R_5%
8
PCH_GPIO5
7
PCH_GPIO1
6
PCH_GPIO94
5
PCH_GPIO93
10K_0804_8P4R_5%
8
PCH_GPIO2
7
PCH_GPIO91
6
PCH_GPIO90
5
PCH_GPIO38
10K_0804_8P4R_5%
8
PCH_GPIO19
7
PCH_GPIO36
6
VGA_ON
5
EC_KBRST#
10K_0804_8P4R_5%
8
PCH_GPIO18
7
PCH_GPIO35
6
PCH_GPIO48
5
PCH_GPIO34
10K_0804_8P4R_5%
8
PCH_GPIO71
7
PCH_GPIO49
6
PCH_GPIO16
5
PCH_GPIO37
10K_0804_8P4R_5%

HASWELL_MCP_E

U1J

R144
1K_0402_5%
D

P1
PCH_GPIO76
PCH_GPIO8 AU2
AM7
EC_LID_OUT# AD6
Y1
PCH_GPIO16
T3
PCH_GPIO17
PCH_GPIO24 AD5
PCH_GPIO27 AN5
PCH_GPIO28 AD7
PCH_GPIO26 AN3

34 EC_LID_OUT#

PCH_GPIO19 7
PCH_GPIO36 6
VGA_ON 38,8

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

PCH_GPIO18 7
PCH_GPIO35 6
PCH_GPIO34 6

PCH_GPIO37 6

EC_SCI#

34,6 EC_SCI#

R66
0_0402_5%
1
2
@

AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3

PCH_GPIO9 AM3
PCH_GPIO10 AM2
P2
DEVSLP0
C4
PCH_GPIO70
L2
PCH_GPIO38
N5
PCH_GPIO39
V2
PCH_SPKR

32,8 DEVSLP0

36 PCH_SPKR

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

CPU/
MISC

GPIO

LPIO

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

PCH_GPIO23 7

THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD

GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

D60
H_THERMTRIP#
V4
T4
SERIRQ
AW15
PCH_OPIRCOMP
AF20 @
T106
AB21 @
T32

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86
DGPU_PRSNT#
PCH_GPIO88
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
EC_IN_RW
PCH_GPIO69

2

RP23 1
2
3
4

1

EC_KBRST# 34
SERIRQ 34,35

2 R145
49.9_0402_1%

C

EC_IN_RW 35

Rev1p2

10 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

+3VALW_PCH

B

+3VS

RP37 1
2
3
4
RP38 1
2
3
4
RP39 1
2
3
4
RP40 1
2
3
4
R248 1
10K_0402_5%

PCH_GPIO11 7
SUSWARN# 8
USB_OC3# 10

+3VALW_PCH
+3VALW_PCH

USB_OC1# 10
R301
10K_0402_5%
PCH_GPIO56

+3VS

1

RP35 8
7
6
5

PCH_GPIO10
PCH_GPIO11
SUSWARN#
USB_OC3#
10K_0804_8P4R_5%
1
PCH_GPIO8
2
USB_OC1#
3
PCH_GPIO13
4
PCH_GPIO26
10K_0804_8P4R_5%
8
PCH_GPIO45
7
PCH_GPIO14
6
PCH_GPIO44
5
PCH_GPIO46
10K_0804_8P4R_5%
8
DGPU_HOLD_RST#
7
PCH_GPIO47
6
PCH_GPIO24
5
PCH_GPIO28
10K_0804_8P4R_5%
8
PCH_GPIO58
7
PCH_GPIO59
6
PCH_GPIO27
5
PCH_GPIO25
10K_0804_8P4R_5%
8
USB_OC2#
7
PCH_GPIO60
6
USB_OC0#
5
PCH_GPIO9
10K_0804_8P4R_5%
2
PCH_GPIO73

R269 1

R303
10K_0402_5%

2

8
7
6
5

1

1
2
3
4

2

RP34

@

2 1K_0402_1%

PCH_SPKR
B

PCH_GPIO57

SPKR / GPIO81 :

NO

REBOOT

DGPU_HOLD_RST# 8

1: ENABLED

*
USB_OC2# 10
PCH_GPIO60 7
USB_OC0# 10,33

0: DISABLED (Have internal PD)

+3VS

+3VALW_PCH

PCH_GPIO66
PCH_GPIO86
R247 1

PCH_GPIO73 7

@

2 10K_0402_5%

EC_LID_OUT#

GPIO15 : TLS Confidentiality

R272 1
R273 1

R270 1

@

2 1K_0402_1%

2 1K_0402_1%
2 1K_0402_5%

@

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

SDIO_D0 / GPIO66 : Top-Block Swap Override

1

+3VS

R306
10K_0402_5%
UMA@

2

*

1: Intel ME TLS with confidentiality

1: ENABLED

0: Intel ME TLS with no confidentiality

0: SPI ROM (Have internal PD)

(Have internal PD)

*

1: ENABLED

*

0: DISABLED (Have internal PD)

A

GPIO87

DGPU_PRSNT#

2

DGPU_PRSNT#

DIS,Optimus
UMA

R219
10K_0402_5%
VGA@

1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0
1

2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(6/11) GPIO,LPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

9

of

52

Rev
1.0

5

4

3

2

HASWELL_MCP_E

U1K
C76
C77

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N0 F10
PEG_GTX_C_HRX_P0 E10

PEG_HTX_C_GRX_N0 C78
PEG_HTX_C_GRX_P0 C79

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N0
PEG_HTX_GRX_P0

PEG_GTX_HRX_N1
PEG_GTX_HRX_P1

C80
C81

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N1 F8
PEG_GTX_C_HRX_P1 E8

PEG_HTX_C_GRX_N1 C82
PEG_HTX_C_GRX_P1 C83

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N1
PEG_HTX_GRX_P1

PEG_GTX_HRX_N2
PEG_GTX_HRX_P2

C84
C85

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N2 H10
PEG_GTX_C_HRX_P2 G10

PEG_HTX_C_GRX_N2 C86
PEG_HTX_C_GRX_P2 C87

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N2
PEG_HTX_GRX_P2

PEG_GTX_HRX_N3
PEG_GTX_HRX_P3

C88
C89

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N3 E6
PEG_GTX_C_HRX_P3 F6

PEG_HTX_C_GRX_N3 C90
PEG_HTX_C_GRX_P3 C91

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N3
PEG_HTX_GRX_P3

B22
A21

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

G11
F11

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

C29
B30

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

F13
G13

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

B29
A29

PEG_GTX_HRX_N0
PEG_GTX_HRX_P0

PEG_GTX_HRX_N[0..3] 17
PEG_GTX_HRX_P[0..3] 17
D

PEG_HTX_C_GRX_N[0..3] 17
PEG_HTX_C_GRX_P[0..3] 17

PCIE LAN

29 PCIE_PRX_DTX_N3
29 PCIE_PRX_DTX_P3
C155
C160

29 PCIE_PTX_C_DRX_N3
29 PCIE_PTX_C_DRX_P3

WLAN

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

31 PCIE_PRX_DTX_N4
31 PCIE_PRX_DTX_P4
C156
C157

31 PCIE_PTX_C_DRX_N4
31 PCIE_PTX_C_DRX_P4

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C23
C22

B23
A23

B21
C21

G17
F17
C

C30
C31
F15
G15
B31
A31

PERN5_L0
PERP5_L0

USB2N0
USB2P0

PETN5_L0
PETP5_L0

USB2N1
USB2P1

PERN5_L1
PERP5_L1

USB2N2
USB2P2

PETN5_L1
PETP5_L1

USB2N3
USB2P3

PERN5_L2
PERP5_L2

USB2N4
USB2P4

PETN5_L2
PETP5_L2

USB2N5
USB2P5

PERN5_L3
PERP5_L3

USB2N6
USB2P6

PETN5_L3
PETP5_L3

USB2N7
USB2P7

PERN3
PERP3
USB3.0 P1

PETN3
PETP3

USB

PCIe

USB3.0 P2

PETN4
PETP4

R232
R155

1
1

@

2 3.01K_0402_1%
2 0_0603_5%

@ E15
@ E13
A27
B27

USB3RN1
USB3RP1
USB3TN1
USB3TP1

PERN4
PERP4

USB3RN2
USB3RP2
USB3TN2
USB3TP2

AN8
AM8

USB20_N0
USB20_P0

AR7
AT7

USB20_N1
USB20_P1

AR8
AP8

USB20_N2
USB20_P2

USB20_N0 33
USB20_P0 33

USB2 Port 0 (USB3.0 P0)

USB20_N1 33
USB20_P1 33

USB2 Port 1

USB20_N2 33
USB20_P2 33

USB2 Port 2

AR10
AT10

D

AM15
AL15

USB20_N4
USB20_P4

AM13
AN13

USB20_N5
USB20_P5

AP11
AN11

USB20_N6
USB20_P6

AR13
AP13

USB20_N7
USB20_P7

G20
H20

USB20_N4 31
USB20_P4 31

Mini Card(WLAN+BT)

USB20_N5 33
USB20_P5 33

Finger Print

USB20_N6 25
USB20_P6 25

Touch Screen

USB20_N7 25
USB20_P7 25

Camera

PCH_USB3_RX0_N 33
PCH_USB3_RX0_P 33

C33
B34

USB3 Port 0

PCH_USB3_TX0_N 33
PCH_USB3_TX0_P 33

E18
F18
B33
A33

PERN1/USB3RN3
PERP1/USB3RP3

C

USB3.0 P3 / PCIE P1

PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4

USB3.0 P4 / PCIE P2

USBRBIAS
USBRBIAS
RSVD
RSVD

PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

+1.05VS_AUSB3PLL
T33
T34
PCIE_RCOMP
PCIE_IREF

1

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

AJ10
USBRBIAS
AJ11
AN10 @
T35
AM10@
T36

AL3
AT1
AH2
AV3

R154 1

2 22.6_0402_1%

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

1

2
11 OF 19

CAD note:
Route single‐end 50‐ohms and max 450‐mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils
33,9
9
9
9

C612
0.1U_0402_16V4Z
@

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(7/11) PCIE,USB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

10

of

52

Rev
1.0

5

4

3

2

1

Shark Bay ULT have internal gate for VDDQ
+1.35V

T37
T38

+1.35V_CPU

@ J2

1

@
@

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

Q5
@
AO4304L_SO8

8
7
6
5

1
2
3
+CPU_CORE

4

D

1

@

2

R182
0_0402_5%

1

2

T39
T40

@
@

VCC_SENSE_R
T41

@

T42
T43
T44

@
@
@

+VCCIO_OUT
C5
0.1U_0603_25V7K
@

2

46 VR_SVID_CLK

R164
1 0_1206_5%

@

0_0402_5%

1

2
C

2

34,8 VCCST_PG_EC

3

NC

VCC

A
Y

R309
10K_0402_5%

5
4

46 VR_ON
46,8 VGATE

0_0402_5%
0_0402_5%

1
1

1

+3VALW_PCH
U16

VCCST_PG_EC_R

CPU_PWR_DEBUG

2

1

+1.05VS_VTT

R166
0_0402_5%
1
2
@

2 R165

1

2 R167
2 R168
@ C167
2 0.1U_0402_16V7K

Reserved Only

T45
T46
T47
T48
T98
T142
T143
T144
T141
T140
T147
T145
T146

VCCST_PWRGD 34,45

GND

74AUP1G07GW_TSSOP5

2

+1.05VS_VTT

SVID ALERT

+1.05VS_VTT
R169
150_0402_1%
@

AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32

R170
10K_0402_5%
@

RSVD
RSVD

H_CPU_SVIDALRT#

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

HSW ULT POWER

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC

1

2

R172
43_0402_1%
2
1

@
@
@
@
@
@
@
@
@
@
@
@
@

CPU_PWR_DEBUG

R171
75_0402_1%

46 VR_ALERT#

D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

+CPU_CORE

1

Place the PU
resistors close to CPU

L62
N63
L63
B59
F60
C59

2

1

+1.05VS_VTT

E63
AB23
A59
E20
AD23
AA23
AE59

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
VIDSOUT
VCCST_PG_EC_R
PCH_VR_EN
VR_READY

@

+3VS

1

F59
N58
AC58

+1.05VS_VTT

+VCCIOA_OUT

R422
100K_0402_5%
@

L59
J58

2

JUMP_43X118

38 3VS_GATE

+CPU_CORE

HASWELL_MCP_E

U1L

+1.35V_CPU

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

D

C

Rev1p2

12 OF 19
HASWELL-MCP-E-ULT_BGA1168
@
+1.35V_CPU

B

SVID DATA

B

VDDQ DECOUPLING

2

+CPU_CORE

C6
22U_0805_6.3V6M

1
2

Note: 0 ohm PLACED CLOSE TO CPU
2

@

1 R178
0_0402_5%

VCC_SENSE 46

1

2

C7
1U_0402_6.3V6K

VCC_SENSE_R

2

1

2

1

2

1

2

1
+

C18
330U_2.5V_M

2

For ESD
@

R177
100_0402_1%

2

EMC@

1

C17
10U_0603_6.3V6M

2

1

C16
10U_0603_6.3V6M

2

EMC@

1

C15
10U_0603_6.3V6M

2

1

C14
10U_0603_6.3V6M

+1.05VS_VTT

VIDSOUT

2

1

C13
10U_0603_6.3V6M

2

1

C12
10U_0603_6.3V6M

46 VR_SVID_DATA

1

C11
2.2U_0402_6.3V6M

R174
0_0402_5%
2
1
@

@

C10
2.2U_0402_6.3V6M

R173
130_0402_1%

C9
2.2U_0402_6.3V6M

Place the PU
resistors close to CPU

C8
2.2U_0402_6.3V6M

1

+1.05VS_VTT

1

2

@

+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4

A

A

2

@

1 R235
0_0402_5%

VSS_SENSE 46

1

13 VSS_SENSE_R

2012/07/10

Issued Date
2

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R233
100_0402_1%

Deciphered Date

2013/07/10

Title

HSW MCP(8/11) Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

11

of

52

Rev
1.0

4

D

+

2

Near PJ602

+1.05VS_VTT

1

2

Near K9

1

2

1

HDA --> 3.3V or 1.5V
I2C --> 1.8V

Near B18

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

2

1 C38
1U_0402_6.3V6K

+1.05VS_ASATA3PLL

C46
1
2
L2
C61
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%
+1.05VS_APLLOPI
R210
0_0805_5%
1 @
2
C47
1
2
L3
C22
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

Near AC9

2

Near AH10

2

Near V8

2

VCCSUS3_3
VCCRTC
DCPRTC

RTC

SPI

RSVD
VCCAPLL
VCCAPLL

VCCSPI

OPI

VCCASW
VCCASW
@

J13
AH14

@ AH13

+3VALW_PCH
C28
1 22U_0805_6.3V6M
AC9
AA9
C59 @
1 0.1U_0402_16V7K
AH10
V8
C29
1 22U_0805_6.3V6M
W9

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1

AXALIA/HDA

VCCHDA
DCPSUS2

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL

VRM/USB2/AZALIA
CORE

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

GPIO/LCC

THERMAL SENSOR

Near J17

+1.05VS_AXCK_DCB

Near R21

Near J18

1
1

2
2

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

C57
1 1U_0402_6.3V6K
C56
1 1U_0402_6.3V6K

T100
T101
T102

+3VALW_PCH

J18
K19
A20
J17
R21
T21
@ K18
@ M20
@ V21
AE20
AE21

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

+RTCVCC

1

2 1U_0402_6.3V6K

AH11
AG10
AE7 +VCCRTCEXT 1
C54
+3VS
Y8

C58

+RTCVCC

2

0.1U_0402_16V7K

2
@

1 0.1U_0402_16V7K

AG14
AG13

SDIO/PLSS

VCCTS1_5
VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

1

2

@

1

2

@

1

2
D

+1.05VS_VTT
+1.05VS_VTT

USB3

DCPSUS3

+3VS

C

C48
1
2
L4
C23
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

C30
mPHY

Near AA21

+1.05VS_VTT
+1.05VS_VTT

+3VALW_PCH
T105

T116

Near B11

Y20
AA21
W21

+1.05VS_APLLOPI

Near L10 Near M9

+1.05VS_AUSB3PLL

C42
1
2
L1
C32
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL

C31
1U_0402_6.3V6K
2
EMC@

+3VALW_PCH

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

0.1U_0402_16V7K
C50

C408
220U_6.3V_M

C20
1U_0402_6.3V6K

1

1

HASWELL_MCP_E

U1M

K9
L10
M9
N8
P9
B18
B11

2

0.1U_0402_16V7K
C51

+1.05VS_VTT

C21
1U_0402_6.3V6K

+1.05VS_VTT

3

1U_0402_6.3V6K
C52

5

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16

U8
T9

C27 1
C33 1
C40 1
EMC@

2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 10U_0603_6.3V6M

+PCH_VCCDSW 1
R209
C36 1
C37 1
C43 @1

C55

1

@

C41
1U_0402_6.3V6K
2+PCH_VCCDSW_R 1
2
0_0402_5%

2 22U_0805_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

2 0.1U_0402_16V7K

C44 1

2

1U_0402_6.3V6K

+1.05VS_VTT

+1.5VS
+3VS

+3VS
C

LPT LP POWER
SUS OSCILLATOR

USB2

DCPSUS4
RSVD
VCC1_05
VCC1_05

AB8
AC20
AG16
AG17

C53 @1
C25 @1
@

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
T103

+1.05VS_VTT
C45 1

2

1U_0402_6.3V6K

+1.05VS_AXCK_LCPLL
C49
1
2
L5
C24
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

Near A20

1
1

13 OF 19

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@

+3VALW TO +3VALW(PCH AUX Power)
Short J5 for PCH VCCSUS3.3
+3VALW
B

1

J5 @
JUMP_43X39
2
1
2

+3VALW_PCH
B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(9/11) Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

12

of

52

Rev
1.0

5

U1N
D

C

B

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

4

3

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1O

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

14 OF 19
HASWELL-MCP-E-ULT_BGA1168

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

HASWELL_MCP_E

U1P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19 Rev1p2 VSS
HASWELL-MCP-E-ULT_BGA1168

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

1

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS
HASWELL-MCP-E-ULT_BGA1168

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

D

C

V58
AH46
V23
E62
AH16

VSS_SENSE_R 11

@

B

@

Rev1p2

@

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(10/11) GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

13

of

52

Rev
1.0

5

4

U1Q

AY2
DC_TEST_AY2_AW2
AY3
DC_TEST_AY3_AW3
AY60
@
DC_TEST_AY61_AW61 AY61
DC_TEST_AY62_AW62 AY62
B2
@
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
DC_TEST_B62_B63
B63
C1
DC_TEST_C1_C2
C2

T49
T50

D

3

2

HASWELL_MCP_E

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

1

HASWELL_MCP_E

U1R

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2

A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

DC_TEST_A3_B3
@
@
DC_TEST_A61_B61
@
@
@
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
@

T58
T59
T60
T61
T62

T51
T52
T53
T54

@
@
@
@

AT2
AU44
AV44
D15

T55
T56
T57

@
@
@

F22
H22
J21

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

T63

HASWELL-MCP-E-ULT_BGA1168
@

N23
R23
T23
U10

@
@
@
@

T64
T65
T66
T67

AL1
AM11
AP7
AU10
AU15
AW14
AY14

@
@
@
@
@
@
@

T68
T69
T70
T71
T72
T73
T74

D

Rev1p2

18 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

T176
T175
T174
T173

@
@
@
@

CFG16
CFG18
CFG17
CFG19

AA62
U63
AA61
U62
V63

CFG_RCOMP
T90

@

A5

T91
T92
T93
T94
TD_IREF

@
@
@
@

E1
D1
J20
H18
B12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP

RESERVED

RSVD
RSVD
RSVD
PROC_OPI_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD

CFG_RCOMP

VSS
VSS

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

AV63
AU63

@
@

T75
T76

C63
C62
B43

@
@
@

T77
T78
T79

A51
B51

@
@

T80
T81

L60

@

T82

N60

@

T83

W23
Y22
AY15

@
@

T84
T85
OPI_COMP

AV62
D58

@
@

T86
T87

@
@

T88
T89

CFG Straps for Processor
C

CFG3

1

@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

R224
1K_0402_1%
@

2

C

T104
T107
T108
T166
T167
T168
T169
T170
T171
T172
T182
T181
T180
T179
T178
T177

HASWELL_MCP_E

Physical Debug Enable

P22
N21
P20
R20

(DFX Privacy)

1: DISABLED

CFG3

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR
CFG4

1

U1S

Rev1p2

19 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

R225
1K_0402_5%

B

2

B

2

1
CFG_RCOMP
49.9_0402_1%
1
OPI_COMP
49.9_0402_1%
1
TD_IREF
8.2K_0402_5%

R222

2
R223

2
R226

Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HSW MCP(11/11) RSVD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

14

of

52

Rev
1.0

A

B

C

D

E

+1.35V
+1.35V

DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47

+1.35V

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

2

@

1

2

1

2

C110
1U_0402_6.3V6K

1

C109
1U_0402_6.3V6K

2

C108
1U_0402_6.3V6K

1

C107
1U_0402_6.3V6K

@

DDRA_CKE0_DIMMA

5 DDRA_CKE0_DIMMA

DDR_A_BS2

5 DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
2

+1.35V

2

1

2

DDR_A_MA3
DDR_A_MA1

C114
10U_0603_6.3V6M

2

1

C113
10U_0603_6.3V6M

1

C112
10U_0603_6.3V6M

2

C111
10U_0603_6.3V6M

1

DDR_A_MA8
DDR_A_MA5

5 SA_CLK_DDR0
5 SA_CLK_DDR#0

+1.35V

EMC@

5 DDR_A_WE#
5 DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

5 DDRA_CS1_DIMMA#

DDR_A_MA13
DDRA_CS1_DIMMA#

1
+

2

@
C118
330U_2.5V_M

SF000002Z00
330U 2.5V H4.2
17mohm OSCON

1

2

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20

3

DDR_A_D17
DDR_A_D16

+0.675VS

DDR_A_D36
DDR_A_D33

2

1

2

1

2

C124
1U_0402_6.3V6K

1

C123
1U_0402_6.3V6K

2

@

C122
1U_0402_6.3V6K

1

C121
1U_0402_6.3V6K

@

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

Layout Note:
Place near JDIMM1.203,204
+3VS

2
@

1

@

1

2

205
R212
0_0402_5%

1

R211
0_0402_5%

4

@

C126
2.2U_0402_6.3V6M

2

C125
0.1U_0402_16V7K

1

2

+0.675VS

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

+5VALW

DDR_A_D27
DDR_A_D26

A
Y

2

SA_ODT0

+1.35V
R191
R188 1
66.5_0402_1%
100K_0402_5%
Q18
LBSS138LT1G_SOT-23-3
D
R189 1
2
66.5_0402_1%
G
S
M_A_B_DIMM_ODT
R190 1
66.5_0402_1%

2

SA_ODT1

1

3

DIMM_DRAMRST# 16,4

2

SB_ODT0

2

SB_ODT1

2

2

R186
100K_0402_5%
@

5

1

VCC

R187 1
66.5_0402_1%

2

1

2

4 DDR_PG_CTRL
DIMM_DRAMRST#

NC

+5VS

1

U45

1

DDR_A_D25
DDR_A_D24

4

GND
74AUP1G07GW_TSSOP5

DDR_A_D45
DDR_A_D40

SB_ODT0 16

SB_ODT1 16

DDR_A_D42
DDR_A_D46

DDR_A_DQS#[0..7]

5

DDR_A_DQS[0..7]

5

DDR_A_D[0..63]

DDR_A_D52
DDR_A_D53

5

DDR_A_MA[0..15] 5

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA 5

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
2

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1

SA_CLK_DDR1 5
SA_CLK_DDR#1 5

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 5
DDR_A_RAS# 5

DDRA_CS0_DIMMA#
SA_ODT0

DDRA_CS0_DIMMA# 5

+1.35V

R56
1.8K_0402_1%

SA_ODT1
+VREF_CA
DDR_A_D5
DDR_A_D4
@
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19

1

2

1

2

R296
1
2
2_0402_1%

SM_DIMM_VREFCA 5
@

R295
1.8K_0402_1%

1

2

C162
0.022U_0402_25V7K

@

R294
24.9_0402_1%

DDR_A_DQS#2
DDR_A_DQS2

3

DDR_A_D22
DDR_A_D23

+VREF_CA 16

DDR_A_D37
DDR_A_D32

DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 16,37,7
D_CK_SCLK 16,37,7

+0.675VS

206

TYCO_2-2013022-1
CONN@

Channel A

SP07000JN10
4



DIMM_1 STD H:4mm
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

DDRIII DIMMA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

1

DDR_VTT_PG_CTRL 43

C120
0.1U_0402_16V7K

DDR_A_D0
DDR_A_D1

EMC@

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D15
DDR_A_D11

C119
2.2U_0402_6.3V6M

2

5 DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

C161
10U_0603_6.3V6M

2

1

C117
10U_0603_6.3V6M

1

C116
10U_0603_6.3V6M

2

C115
10U_0603_6.3V6M

1

SA_CLK_DDR0
SA_CLK_DDR#0

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

@

DDR_A_DQS#1
DDR_A_DQS1

3

DDR_A_D30
DDR_A_D31

DDR_A_D9
DDR_A_D12

1

DDR_A_DQS#3
DDR_A_DQS3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2

DDR_A_D29
DDR_A_D28

2

R176
24.9_0402_1%
@

2

DDR_A_D14
DDR_A_D10

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

2

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

2

1
1

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

2
1
@
R185
1.8K_0402_1%

2

C106
0.1U_0402_16V7K

@
C158
0.022U_0402_25V7K

1

DDR_A_D13
DDR_A_D8

2

1

JDIMM1
+V_DDR_REFA
R54
1.8K_0402_1%
C105
2.2U_0402_6.3V6M

5 SA_DIMM_VREFDQ

+1.35V
C34
0.1U_0402_16V7K

R293
2_0402_1%
1
2

+1.35V

C

D

Sheet

Tuesday, March 26, 2013
E

15

of

52

Rev
1.0

A

B

C

D

E

+1.35V
+1.35V

1

JDIMM2

1

1

@
R213
1.8K_0402_1%

2

1

2

1

1

2

2

DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

2

R179
24.9_0402_1%
@

1

C128
0.1U_0402_16V7K

@
C159
0.022U_0402_25V7K

DDR_B_D8
DDR_B_D14
C127
2.2U_0402_6.3V6M

5 SB_DIMM_VREFDQ

R297
2_0402_1%
2

+V_DDR_REFB
R57
1.8K_0402_1%

2

1

DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42

+1.35V

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

2

@

1

2

1

2

C132
1U_0402_6.3V6K

1

C131
1U_0402_6.3V6K

2

C130
1U_0402_6.3V6K

1

C129
1U_0402_6.3V6K

@

DDRB_CKE0_DIMMB

5 DDRB_CKE0_DIMMB

DDR_B_BS2

5 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
2

+1.35V

DDR_B_MA8
DDR_B_MA5

2

1

2

DDR_B_MA3
DDR_B_MA1

C136
10U_0603_6.3V6M

2

1

C135
10U_0603_6.3V6M

1

C134
10U_0603_6.3V6M

2

C133
10U_0603_6.3V6M

1

5 DDR_B_WE#
5 DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

5 DDRB_CS1_DIMMB#

DDR_B_MA13
DDRB_CS1_DIMMB#

DDR_B_D4
DDR_B_D1

DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20

3

DDR_B_D22
DDR_B_D23

+0.675VS

DDR_B_D36
DDR_B_D33

2

@

1

2

DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49

+3VS

2

2

1

C146
1U_0402_6.3V6K

1

C145
1U_0402_6.3V6K

@

C144
1U_0402_6.3V6K

2

C143
1U_0402_6.3V6K

1

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D48
DDR_B_D53

1

Layout Note:
Place near JDIMM1.203,204

R229
10K_0402_5%

+3VS
+0.675VS

2

205

2
@

1

1

R231
0_0402_5%

4

@

C148
2.2U_0402_6.3V6M

2

C147
0.1U_0402_16V7K

1

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D12
DDR_B_D9

DDR_B_DQS#[0..7]

5

DDR_B_DQS[0..7]

5

DDR_B_D[0..63]

DDR_B_DQS#1
DDR_B_DQS1

5

DDR_B_MA[0..15] 5

DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
1

DIMM_DRAMRST#

DIMM_DRAMRST# 15,4

DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44

DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB 5

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
2

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1

SB_CLK_DDR1 5
SB_CLK_DDR#1 5

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 5
DDR_B_RAS# 5

DDRB_CS0_DIMMB#
SB_ODT0

DDRB_CS0_DIMMB# 5
SB_ODT0 15

SB_ODT1

SB_ODT1 15

+VREF_CA

+VREF_CA 15

DDR_B_D5
DDR_B_D0
@
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17

1

2

1

2

C142
0.1U_0402_16V7K

DDR_B_DQS#0
DDR_B_DQS0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C141
2.2U_0402_6.3V6M

2

1
@
2

5 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

C139
10U_0603_6.3V6M

1

C138
10U_0603_6.3V6M

2

C137
10U_0603_6.3V6M

1

SB_CLK_DDR0
SB_CLK_DDR#0

5 SB_CLK_DDR0
5 SB_CLK_DDR#0

+1.35V

+1.35V

DDR_B_DQS#2
DDR_B_DQS2

3

DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 15,37,7
D_CK_SCLK 15,37,7

+0.675VS

206

TYCO_2-2013022-1
CONN@

Channel B

SP07000JN10
4



DIMM_2 STD H:4mm
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, March 26, 2013
E

16

of

52

Rev
1.0

A

B

C

D

E

GFX PCIE LANE REVERSAL
U51A
PEG_HTX_C_GRX_P[0..3]

10 PEG_HTX_C_GRX_P[0..3]

PEG_GTX_HRX_P[0..3]

PART 1 0F 9

PEG_GTX_HRX_P[0..3] 10

PEG_HTX_C_GRX_N[0..3]

10 PEG_HTX_C_GRX_N[0..3]

PEG_GTX_HRX_N[0..3]

PEG_GTX_HRX_N[0..3] 10
U51G

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

AA38
Y37

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36
U38
T37
T35
R36
R38
P37
P35
N36

2

N38
M37

L38
K37
K35
J36
J38
H37
H35
G36
G38
F37

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

NC#N38
NC#M37
NC#M35
NC#L36
NC#L38
NC#K37

NC#N33
NC#N32
PCI EXPRESS INTERFACE

M35
L36

PCIE_RX0P
PCIE_RX0N

NC#N30
NC#N29
NC#L33
NC#L32

NC#K35
NC#J36

NC#L30
NC#L29

NC#J38
NC#H37

NC#K33
NC#K32

NC#H35
NC#G36

NC#J33
NC#J32

NC#G38
NC#F37

NC#K30
NC#K29

NC#F35
NC#E37

NC#H33
NC#H32

Y33
Y32

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0

W33
W32

PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

U33
U32

PEG_GTX_HRX_P2
PEG_GTX_HRX_N2

U30
U29

PEG_GTX_HRX_P3
PEG_GTX_HRX_N3

PART 7 0F 9

1

RSVD/VARY_BL
RSVD/DIGON

AK27
AJ27

LVDS CONTROL

TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N

T33
T32

TX5P_DPB0P
TX5M_DPB0N

T30
T29

LVTMDP

1

P33
P32

NC#AF35
NC#AG36

TXCAP_DPA3P
TXCAM_DPA3N

P30
P29

TX0P_DPA2P
TX0M_DPA2N

N33
N32

TX1P_DPA1P
TX1M_DPA1N

N30
N29

TX2P_DPA0P
TX2M_DPA0N
NC#AN36
NC#AP37

L33
L32
L30
L29

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

AP34
AR34
AW37
AU35

2

AR37
AU39
AP35
AR35
AN36
AP37

2160842006A0MARSXT_FCBGA962
@

K33
K32
J33
J32
K30
K29

3

3

F35
E37

AB35
AA36

7 CLK_PEG_VGA
7 CLK_PEG_VGA#

H33
H32

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

PCIE_CALR_TX
2 VGA@ 1
AH16
R795
1K_0402_5%

3.3-V tolerant
8 PLTRST_VGA#

PLTRST_VGA#

AA30

TEST_PG

PCIE_CALR_RX

Y30
Y29

VGA_PCIE_CALRP
VGA_PCIE_CALRN

R794 1 VGA@
R796 1

2 1.69K_0402_1%

VGA@ 2 1K_0402_1%

+0.95VSDGPU
+0.95VSDGPU

PERSTB
2160842006A0MARSXT_FCBGA962
@

4

4

U51

U51

SUN_XT_M2_962P
SUN@

MARS_XT_M2_962P
MARS@

SA00006G610

SA000061J20

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

MARS-Pro_PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Thursday, April 11, 2013
E

17

of

52

Rev
1.0

A

B

C

D

U51B

External VGA Thermal Sensor

GPU_VID_5

47 GPU_VID_5

R806 10K_0402_5%1

2

@

GPIO_19_CTF
GPU_VID_2

47 GPU_VID_2

(GPIO1, 2, 7, 11, 12, 13, 18, 21

is NC at SUN)

AG32
AG33

VREFG:Use a voltage divider to set
VREFG = 1.80 V / 3 (or 0.60-V nominal).

I2C

R
AVSSN

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

G
AVSSN

DAC1

+1.8VSDGPU

R810 1 MARS@ 2 499_0402_1%

AK24

20mil

R811 1 MARS@ 2 249_0402_1%
1
C841
MARS@

2 0.1U_0402_16V4Z

AH13
(SUN NC)

+VGA_VREF

Place VREFG divider and cap close to ASIC
2

Pull high @ VGA side

XTALOUT

VDD1DI
VSS1DI
NC#V13
NC#U13
NC#AF33
NC#AF32
NC#AA29
NC#AG21
NC#AC32
NC_SVI2#AC31
NC_SVI2#AD30
NC_SVI2#AD32

1
2
3
4

XTALIN

IN

4

8
7
6
5

PX_EN

PS_3

10K_0804_8P4R_5%
T18
@

AM23
AN23
AK23
AL24
AM24

@

DDC/AUX

27MHZ_10PF_X3G027000BA1H-U

TESTEN

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

1

Crystals must have a max ESR of 80 ohm

1
2
@
R819
10K_0402_5%
1 VGA@ 2
R820
10K_0402_5%
+1.8VSDGPU
L69
1

MLPS_EN#

AF29
AG29
AK32
AL31

@
2

13mA
0_0603_5%

10U_0603_6.3V6M 2
1U_0402_6.3V6K 2
0.1U_0402_16V4Z 2

1 @
1 @
1 VGA@

10mil
C844
C845
C846

+TSVDD

AJ32
AJ33

AG31

PS_2

AD33

PS_3

AM19
AL19

DDC2CLK
DDC2DATA

AN20
AM20

AUX2P
AUX2N

100
101
101
101
101
100
101

DPLUS
DMINUS

NC#AL29
NC#AM29

TS_A
TSVDD
TSVSS

AL30
AM30

1

AL29
AM29

2

AN21
AM21

NC#AN21
NC#AM21
GPIO_28_FDO

-

Mars MLPS configuration
Bits[5:1] PU(1%)

:
:
:
:
:

B

NC

4.75k

xx001

8.45k

2.00k

xx010

4.53k

2.00k

xx011

6.98k

4.99k

xx100

4.53k

4.99k

xx101

3.24k

5.62k

xx110

3.40k

10.0k

xx111

4.75k

NC

2

00xxx

680nF

01xxx

82nF

10xxx

10nF

11xxx

NC

Since the frame buffer size is 512 MB
same as GPIO_11
the aperture size is set to 256 MB.
same as GPIO_12
same as GPIO_13
Reserved for internal use only. Must be 1
AUD_PORT_CONN_PINSTRAP[0]

512Kbit
1Mbit
2Mbit
4Mbit
8Mbit
512Kbit
1Mbit

M25P05A
M25P10A
M25P20
M25P40
M25P80
Pm25LV512
Pm25LV010

(ST)
(ST)
(ST)
(ST)
(ST)
(Chingis)
(Chingis)

+VDDC_CT

@
1

2

@
1

2

2

0
0
0
1
1

:
:
:
:
:

PCIeR GEN3 is not supported.
Reserved for internal use only
Reserved for internal use only
TX_PWRS_ENB: Full Tx output swing.
TX_DEEMPH_EN: Tx deemphasis enabled.

PS_2[1]
PS_2[2]
PS_2[3]
PS_2[4]
PS_2[5]

=
=
=
=
=

0
0
0
0
1

:
:
:
:
:

Reserved.
Reserved.
BIOS_ROM_EN :Disable the external BIOS ROM device.
VGA_DIS : 0=VGA controller capacity enabled.
Reserved.

+VDDC_CT

@
R816
10K_0402_5%

@
1

=
=
=
=
=

+VDDC_CT

VGA@
R808
8.45K_0402_1%

PS_3[1]
PS_3[2]
PS_3[3]
PS_3[4]
PS_3[5]

=
=
=
=
=

=======
001
010
011

x
x
x
1
1

:
:
VRAM ID
:
: AUD_PORT_CONN_PINSTRAP[1]
: AUD_PORT_CONN_PINSTRAP[2]

VRAM ID for Mars

=======

Micron MT41K256M16HA-107G:E x 8
Hynix
H5TQ2G63DFR-11C x 4
Hynix
H5TQ2G63DFR-11C x 8

X76@
R815
R823
R818
R809
10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
VGA@
VGA@
VGA@

4

AK30
AK29

NC#AK30
NC#AK29

AJ30
AJ31

DDCVGACLK
DDCVGADATA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

MARS-Pro_STRAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
@

V5WE2 M/B LA-9531P Schematic

Date:

A

PD(1%) Cap

xx000

PS_1[1]
PS_1[2]
PS_1[3]
PS_1[4]
PS_1[5]

X76@
@
R812
R821
10K_0402_5% 10K_0402_5%
PS_0
PS_1
PS_2
PS_3
@

NC#AL30
NC#AM30

GPU_THERM_D+
GPU_THERM_D-

PS_1

AM27
AL27

THERMAL

+3VSDGPU

C849
12P_0402_50V8J
VGA@

AD31

AM26
AN26

DDC1CLK
DDC1DATA

1
2

PS_0

PS0_[1]=1
PS0_[2]=0
PS0_[3]=0
PS0_[4]=1
PS0_[5]=1

+VDDC_CT
DEBUG

AUX1P
AUX1N

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS

AM34

C840
0.1U_0402_16V7K

C848
12P_0402_50V8J
1
VGA@

GND

PS_2

BACO

@

2

L66
BLM18AG121SN1D_2P
1
+0.95VSDGPU
VGA@

3

C843
0.1U_0402_16V7K

2

GND

DBG_VREFG

PS_1

2

10mil

C847
0.01U_0402_16V7K

4

OUT

MLPS

1

2 10K_0402_5%
2 10K_0402_5%

C842
0.1U_0402_16V7K

2

HPD1

RP21

X2
VGA@
Crystal
3

AD28

R803 1 @
R804 1
@

RSET
R805 1 MARS@ 2 499_0402_1%
(SUN NC)
L67
70mA
AD34
2
1
+AVDD
+1.8VSDGPU
(SUN NC)
AE34
MARS@
0_0603_5%
1
1
AC33 +VDD1DI
AC34
@
@
2
2
(SUN NC)
V13
U13
AF33
10mil
AF32
L68
AA29
0_0603_5%
117mA
AG21
2
1
+1.8VSDGPU
AC32
MARS@
@
1
1
AC31
@
AD30
AD32
2
2

AVDD
AVSSQ

1

2 VGA@ 1
TESTEN
R817
1K_0402_5%

+3VSDGPU

T155
AUD_1
AUD_0

@

AUD[1:0]:
00 - No audio function

CEC_1

R813
0_0402_5%
@

R814
+3VSDGPU 5.11K_0402_1%
2 @
1
VGA@
R822
1M_0402_5%
2
1

AL21

T156

AB34

RSET

PS_0
AC30

AE36
AD35

AC36
AC38

HSYNC
VSYNC

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

T154

AF37
AE38

B
AVSSN

GPIO_29
GPIO_30

AD39
AD37

C838
1U_0402_6.3V6K

3

@

AT23
AR22

C837
0.1U_0402_16V4Z

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

2160842006A0MARSXT_FCBGA962
@

AU22
AV21

NC#AT23
NC#AR22

1

2

AT21
AR20

NC#AU22
NC#AV21

2

T137
T138

C835
0.1U_0402_16V4Z

GPU_VID_1
GPU_VID_3
THM_ALERT#

47 GPU_VID_1
47 GPU_VID_3

NC_XTAL_PVDD
NC_XTAL_PVSS

AK10
AL10

1

47 GPU_VID_4

CLKTESTA
CLKTESTB

@

C834
1U_0402_6.3V6K

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

GPU_ACIN_D
GPU_VID_4

AF30
AF31

2

AH20
AH18
AN16

SPLL_PVSS

1

GPU_DPRSLPVR

47 GPU_DPRSLPVR

GPU_ACIN_D

XO_IN2

AU20
AT19

NC#AU20
NC#AT19

DPD

SCL
SDA

SPLL_VDDC

SPLL_PVSS

AT17
AR16

NC#AT17
NC#AR16

SMBCLK SMBus
SMBDATA

SPLL_PVSS AN10

AU16
AV15

NC#AU16
NC#AV15

2

+SPLL_VDDC

1

2

2
1

D22
RB751V40_SC76-2
VGA@
1
2

34 GPU_ACIN

DPC

100mA
AW35 XO_IN2 2
1
@
0_0402_5% R802
VGA@ 1 VGA@ 1

AT15
AR14

NC#AT15
NC#AR14

SPLL_PVDD

2

L65
BLM18AG121SN1D_2P
1
+1.8VSDGPU
VGA@

C833
10U_0603_6.3V6M

AK26
AJ26

2

R409
100K_0402_5%
VGA@

NC#AU14
NC#AV13

+SPLL_VDDC AN9

2
@
XO_IN 1
0_0402_5% R799

C891
R841
0.1U_0402_16V4Z 51.1_0402_1%

AJ23
AH23

Slave ID: 0x41

+3VSDGPU

AU14
AV13

NC#AT21
NC#AR20

0_0402_5%
2VGA_SMB_CK2_R
2VGA_SMB_DA2_R
0_0402_5%

@
@

AT33
AU32

NC#AT33
NC#AU32

AW34

C892
R904
0.1U_0402_16V4Z 51.1_0402_1%

R898
1
VGA_SMB_CK2
1
VGA_SMB_DA2
R899

XO_IN
+SPLL_PVDD AM10

C832
1U_0402_6.3V6K

EC_SMB_DA2 24,34,7

2

AR32
AT31

NC#AR32
NC#AT31

1

EC_SMB_CK2 24,34,7

MPLL_PVDD
MPLL_PVDD

2

EC_SMB_CK2

H7
H8

+MPLL_PVDD

1

5
2

1

VGA_SMB_DA2

3

Q54A
VGA@
DMN66D0LDW-7_SOT363-6
6
EC_SMB_DA2

VGA@ 1 VGA@ 1

AV31
AU30

NC#AV31
NC#AU30

DPB

XTALOUT

AR30
AT29

NC#AR30
NC#AT29

2

+SPLL_PVDD

2

2

2

1

1

4

Q54B
VGA@
DMN66D0LDW-7_SOT363-6

75mA

2

SM010030010 200ma
120ohm@100mhz DCR 0.2

C830
10U_0603_6.3V6M

VGA_SMB_CK2

T112
T113
T114
T115
T118
T117
T119
T121
T120
T122
T124
T123
T125
T127
T126
T128
T130
T129
T131
T133
T132
T134
T136
T135

XTALOUT

AT27
AR26

NC#AT27
NC#AR26

C829
1U_0402_6.3V6K

+3VSDGPU

AU34

2

1

T111

+3VSDGPU

NC#AR8
NC#AU8
DBG_CNTL0
NC#AW8
NC#AR3
NC#AR1
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

XTALIN

AU26
AV25

PLLS/XTAL

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

1

R801
4.7K_0402_5%
VGA@

DPA

NC#AU26
NC#AV25

ADM1032ARMZ-2REEL_MSOP8

R800
4.7K_0402_5%
VGA@

SWAPLOCKA
SWAPLOCKB

2

+3VSDGPU

XTALIN

1

2
4.7K_0402_5%

@

AV33

2

1
R798

VGA@ 1 VGA@ 1

AT25
AR24

NC#AT25
NC#AR24

1

5

AJ21
AK21

2

GND

THM_ALERT#

AU24
AV23

NC#AU24
NC#AV23

1

ALERT#

THERM#

VGA_SMB_DA2

+MPLL_PVDD
PART 9 0F 9

MUTI GFX

GENLK_CLK
GENLK_VSYNC

2

D-

4

7
6

AD29
AC29

T109
T110

1

SDATA

VGA_SMB_CK2

2

D+

3

8

C826
10U_0603_6.3V6M

2

2

GPU_THERM_D+
2200P_0402_50V7K
2
C827 1
@
GPU_THERM_D-

SCLK

C825
1U_0402_6.3V6K

1

C823
0.1U_0402_16V4Z

@

VDD

1

U52 @
1

L64
BLM18AG121SN1D_2P
2
1
+1.8VSDGPU
VGA@

130mA

2

+3VSDGPU

E

U51I
PART 2 0F 9

C

D

Sheet

Tuesday, March 26, 2013
E

18

of

52

Rev
1.0

B

C

D

E

MAA[0..15]

U51D

MAA[0..15] 22

U51C
PART 4 0F 9

R828

1

2

40.2_0402_1%
MARS@

1 MARS@

2

2

C852
1U_0402_6.3V6K

R830
100_0402_1%
MARS@

15mil
MVREFSA

3

L18
L20
L27
N12
AG12

R835 1 VGA@
120_0402_1%

2

MEM_CALRP0 M27

CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC#L27
NC#N12
NC#AG12

WEA0B
WEA1B

MEM_CALRP0
NC#M12
NC#AH12

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD

J21
G19

ODTA0
ODTA1

H27
G27

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#

M13
K16

CSA1#

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19
M21
M20

MAA13
MAA14
MAA15

ODTA0 22
ODTA1 22
CLKA0 22
CLKA0# 22
CLKA1 22
CLKA1# 22
RASA0# 22
RASA1# 22
CASA0# 22
CASA1# 22
CSA0# 22
CSA1# 22

MVREFDB Y12
MVREFSB AA12

CKEA0 22
CKEA1 22

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

WEB0B
WEB1B

WEA0# 22
WEA1# 22

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

MAB[0..15] 23
1

DQMB#[0..7]

DQMB#[0..7] 23

QSB[0..7]

QSB[0..7] 23

QSB#[0..7]

B_BA2 23
B_BA0 23
B_BA1 23

QSB#[0..7] 23

+1.5VSDGPU

VGA@

CASB0#
CASB1#
CSB0#

AD10
AC10

CSB1#

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8
U12
V12

MAB13
MAB14
MAB15

2160842006A0MARSXT_FCBGA962
@

MAB[0..15]

R824

P10
L10

15mil
MVREFDB
1 VGA@

R827 VGA@
100_0402_1%

ODTB0 23
ODTB1 23

2

2

R901
0_0402_5%
@

+1.5VSDGPU

CLKB0 23
CLKB0# 23
CLKB1 23
CLKB1# 23

R829
VGA@

RASB0# 23
RASB1# 23

40.2_0402_1%

15mil

CASB0# 23
CASB1# 23

MVREFSB
1 VGA@

R831
VGA@

CSB0# 23

100_0402_1%

2

CSB1# 23
CKEB0 23
CKEB1 23

3

WEB0# 23
WEB1# 23

1
2
1
2
VGA@
VGA@
R838
R839
10_0402_5% 1 VGA@ 51.1_0402_1%
VGA@
C854
R840
120P_0402_50V8
4.99K_0402_1%
2

VRAM_RST# 22,23

1

2160842006A0MARSXT_FCBGA962
@

QSA#[0..7] 22

40.2_0402_1%

W10
AA10

AH11

QSA[0..7] 22

QSA#[0..7]

1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

DQMA#[0..7] 22

QSA[0..7]

2

A34
E30
E26
C20
C16
C12
J11
F8

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

2

M12
AH12

ADBIA0/ODTA0
ADBIA1/ODTA1

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

C853
1U_0402_6.3V6K

MVREFDA
MVREFSA

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

C34
D29
D25
E20
E16
E12
J10
D7

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

2

1
2

1

2

R900
0_0402_5%
@

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

1

2
1

+1.5VSDGPU

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

A32
C32
D23
E22
C14
A14
E10
D9

A_BA2 22
A_BA0 22
A_BA1 22

GDDR5/DDR3

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

2

2

2

100_0402_1%
MARS@

1 MARS@
C850
1U_0402_6.3V6K

R826

15mil
MVREFDA

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7

C5
MDB0
C3
MDB1
E3
MDB2
E1
MDB3
F1
MDB4
F3
MDB5
F5
MDB6
G4
MDB7
H5
MDB8
H6
MDB9
MDB10 J4
MDB11 K6
MDB12 K5
MDB13 L4
MDB14 M6
MDB15 M1
MDB16 M3
MDB17 M5
MDB18 N4
MDB19 P6
MDB20 P5
MDB21 R4
MDB22 T6
MDB23 T1
MDB24 U4
MDB25 V6
MDB26 V1
MDB27 V3
MDB28 Y6
MDB29 Y1
MDB30 Y3
MDB31 Y5
MDB32 AA4
MDB33 AB6
MDB34 AB1
MDB35 AB3
MDB36 AD6
MDB37 AD1
MDB38 AD3
MDB39 AD5
MDB40 AF1
MDB41 AF3
MDB42 AF6
MDB43 AG4
MDB44 AH5
MDB45 AH6
MDB46 AJ4
MDB47 AK3
MDB48 AF8
MDB49 AF9
MDB50 AG8
MDB51 AG7
MDB52 AK9
MDB53 AL7
MDB54 AM8
MDB55 AM7
MDB56 AK1
MDB57 AL4
MDB58 AM6
MDB59 AM1
MDB60 AN4
MDB61 AP3
MDB62 AP1
MDB63 AP5

1

R825
40.2_0402_1%
MARS@

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

2

1

+1.5VSDGPU

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

1

1

GDDR5/DDR3

MEMORY INTERFACE A

(SUN 64 bin on at Channel B)

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

C851
1U_0402_6.3V6K

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA#[0..7]

MDB[0..63]

2

MDA[0..63]

22 MDA[0..63]

23 MDB[0..63]

MEMORY INTERFACE B

PART 3 0F 9

1

A

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
The suggested components are tested on the AMD
reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
the DRAM specification.

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

4

2013/07/10

Title

MARS-Pro_MEMORY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

19

of

52

Rev
1.0

A

B

C

D

E

U51E
PART 5 0F 9

+1.5VSDGPU

VGA@

@

2

2

2

10mil

VGA@
1

2

300mA

20mil
+1.8VSDGPU

2

1

2

C908
1U_0402_6.3V6K

2

C907
10U_0603_6.3V6M

MARS@

MARS@ MARS@
1
1
1
@

2

AF23
AF24
AG23
AG24
AD12
AF11
AF12
AF13
AF15
AG11
AG13
AG15

I/O

VDDR3
VDDR3
VDDR3
VDDR3
DVP

VDDR4
VDDR4
VDDR4
VDDR4

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDR4
VDDR4
VDDR4
VDDR4

(SUN NC)

C899
0.1U_0402_16V4Z

L72
BLM18AG121SN1D_2P

+VDDR4

VDD_CT
VDD_CT
VDD_CT
VDD_CT

25mA

+VDDR3

C898
0.1U_0402_16V4Z

2

VGA@
1

C897
1U_0402_6.3V6K

@
1

VGA@

C896
1U_0402_6.3V6K

2
1
L71
BLM18AG121SN1D_2P

+3VSDGPU

1
@

LEVEL
TRANSLATION

FB_VDDCI
FB_GND

1

47 VSS_GPU_SENSE

AG28

2

@
R842
0_0402_5%

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

+0.95VSDGPU

1.4A 60mil
VGA@
1

VGA@
1

VGA@
1

2

2

2

+VGA_CORE

30A (TBD)

+0.95VSDGPU

Must always be connected to PCIE_VDDC.
0.95 V for "Mars" and
"Heathrow"/"Chelsea" on both BACO and
non-BACO designs.
2

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

3

360mil
+VGA_CORE
VGA@

3.5A (DDR3)
1

2

VGA@

1

2

VGA@

1

2

C919
0.1U_0402_16V4Z

T139

VSS_GPU_SENSE AH29

FB_VDDC

VGA@
1

C918
0.1U_0402_16V4Z

VCC_GPU_SENSE AF28

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

1

VGA@
1

C917
0.1U_0402_16V4Z

VOLTAGE
SENESE

10mil
47 VCC_GPU_SENSE

ISOLATED
CORE I/O

3

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

2

C888
10U_0603_6.3V6M

2

C887
0.1U_0402_16V4Z

VGA@
1

C886
1U_0402_6.3V6K

VGA@
1

VGA@

C885
10U_0603_6.3V6M

L70
BLM18AG121SN1D_2P

2

13mA

+VDDC_CT AF26
AF27
AG26
AG27

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

N27
T27

100mil

C889
1U_0402_6.3V6K

20mil

1

CORE

BIF_VDDC
BIF_VDDC

2.5A

C890
1U_0402_6.3V6K

+VDDC_CT

2

+1.8VSDGPU

BACO

2

+1.8VSDGPU

C876
10U_0603_6.3V6M

2

2

100mA

@
1

C875
1U_0402_6.3V6K

2

@
1

C874
1U_0402_6.3V6K

2

VGA@
1

C873
1U_0402_6.3V6K

2

VGA@
1

C884
2.2U_0402_6.3V6M

2

VGA@
1

C883
2.2U_0402_6.3V6M

2

VGA@
1

C882
2.2U_0402_6.3V6M

2

@
1

C881
2.2U_0402_6.3V6M

2

C880
2.2U_0402_6.3V6M

@
1

C879
10U_0603_6.3V6M

VGA@
1

C878
10U_0603_6.3V6M

VGA@
1

C877
10U_0603_6.3V6M

VGA@
1

2

NC For Mars

C872
1U_0402_6.3V6K

2

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

20mil

C869
1U_0402_6.3V6K

2

VGA@
1

C868
0.1U_0402_16V4Z

@
1

C867
0.1U_0402_16V4Z

2

VGA@
1

C866
0.1U_0402_16V4Z

2

C865
0.1U_0402_16V4Z

@
1

C864
0.1U_0402_16V4Z

VGA@
1

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

C863
10U_0603_6.3V6M

1

NC#AA31
NC#AA32
NC#AA33
NC#AA34
NC#W30
NC#Y31
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD

C862
1U_0402_6.3V6K

2

MEM I/O

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C861
1U_0402_6.3V6K

2

VGA@

1

C860
0.01U_0402_16V7K

2

@

1

C859
0.01U_0402_16V7K

2

VGA@

1

C858
0.01U_0402_16V7K

1

C857
0.01U_0402_16V7K

2

C856
0.01U_0402_16V7K

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

PCIE

1.5A

2160842006A0MARSXT_FCBGA962
@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

MARS-Pro_PWR/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, March 26, 2013
E

20

of

52

Rev
1.0

A

B

C

D

E

U51F
PART 6 0F 9

1

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

NC#AG22

AP20
AP21
AP22
AP23
AU18
AV19

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

237mA
+1.8VSDGPU

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

@
1

2

VGA@
1

VGA@
1

2

2

AH34
AJ34
AF34
AG34
AM37
AL38
AM32

DP_VDDC

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

NC#AN24
NC#AP24
NC#AP25
NC#AP26
NC#AU28
NC#AV29
NC#AP20
NC#AP21
NC#AP22
NC#AP23
NC#AU18
NC#AV19

NC#AP13
NC#AT13
NC#AP14
NC#AP15

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

CALIBRATION

AW28

AW18
R845
150_0402_1%
2 MARS@ 1 AM39

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

20mil
+0.95VSDGPU

280mA

1 VGA@ 1 VGA@ 1 VGA@

2

AP13
AT13
AP14
AP15

2

2

2

DP GND

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

C938
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AN24
AP24
AP25
AP26
AU28
AV29

C937
1U_0402_6.3V6K

4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PART 8 0F 9
DP_VDDR

C936
10U_0603_6.3V6M

3

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U51H

C929
10U_0603_6.3V6M

2

1

C928
1U_0402_6.3V6K

GND

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

C927
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC#AW28

NC#AW18

DP_CALR

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

3

2160842006A0MARSXT_FCBGA962
@

AG22

4

VSS_MECH
VSS_MECH
VSS_MECH

A39
AW1
AW39

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
@

V5WE2 M/B LA-9531P Schematic

Date:

A

MARS-Pro_PWR/GND

B

C

D

Sheet

Tuesday, March 26, 2013
E

21

of

52

Rev
1.0

B

C

QSA2
QSA0

F3
C7

DQMA#2
DQMA#0

E7
D3

QSA#2
QSA#0

G3
B7

2

VRAM_RST#

19,23 VRAM_RST#

T2

1

L8

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

R846
243_0402_1%
128@

J1
L1
J9
L9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA3
QSA1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#3
DQMA#1

E7
D3

QSA#3
QSA#1

G3
B7

+1.5VSDGPU

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R847
243_0402_1%
128@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R848
243_0402_1%
128@

J1
L1
J9
L9

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

CLKA1
CLKA1#
CKEA1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1
CSA1#
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

+1.5VSDGPU

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R849
243_0402_1%
128@

2

15mil

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

X76
ZZZ1
X7601@

X76402BOL01
4Gbx8 Micron 256M16
1

ZZZ3
X7603@

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

X76402BOL03
2Gbx4 HYN 128M16

ZZZ4
X7604@

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

X76402BOL04
2Gbx8 HYN 128M16

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

3

15mil

VREFCA_A3
1

C943

VREFDA_Q3

128@

2

R863
4.99K_0402_1%
128@

C944

1

128@

2

+1.5VSDGPU

+1.5VSDGPU

2

2

2

2

2

2

2

2

2

+1.5VSDGPU

128@
1

2

2

2

2

2

C966
1U_0402_6.3V6K

2

128@
1

C965
1U_0402_6.3V6K

2

128@
1

C964
1U_0402_6.3V6K

2

128@
1

C963
1U_0402_6.3V6K

2

128@
1

C962
1U_0402_6.3V6K

2

C961
1U_0402_6.3V6K

2

C960
1U_0402_6.3V6K

128@
1

C959
1U_0402_6.3V6K

128@
1

C958
1U_0402_6.3V6K

128@
1

C957
1U_0402_6.3V6K

128@
1

C956
1U_0402_6.3V6K

128@
1

C955
1U_0402_6.3V6K

128@
1

C954
1U_0402_6.3V6K

128@
1

C953
1U_0402_6.3V6K

128@
1

C952
1U_0402_6.3V6K

128@
1

+1.5VSDGPU

+1.5VSDGPU

2

2

2

2

2

2

2

2

2012/07/10

C1030
10U_0603_6.3V6M

128@
1

C1027
10U_0603_6.3V6M

128@
1

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

128@
1

C1028
10U_0603_6.3V6M

2

128@
1

C1029
10U_0603_6.3V6M

2

128@
1

128@
1

C975
10U_0603_6.3V6M

2

128@
1

128@
1

C974
10U_0603_6.3V6M

C406
0.01U_0402_16V7K
2
128@

2

128@
1

C1025
10U_0603_6.3V6M

2

128@
1

C1023
10U_0603_6.3V6M

2

128@
1

C1026
10U_0603_6.3V6M

2

128@
1

128@
1

C973
10U_0603_6.3V6M

128@
1

128@
1

C972
10U_0603_6.3V6M

128@
1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

R855
4.99K_0402_1%
128@

128@
1

+1.5VSDGPU

J1
L1
J9
L9

VREFCA
VREFDQ

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

+1.5VSDGPU

1

2

C940
128@

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

1

1
2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

R862
4.99K_0402_1%
128@

C1024
10U_0603_6.3V6M

1

QSA#4
QSA#5

ODT/ODT0
CS/CS0
RAS
CAS
WE

M8
H1

A_BA0
A_BA1
A_BA2

128@
1

C971
10U_0603_6.3V6M

2
40.2_0402_1%

E7
D3

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

128@
1

2

128@

DQMA#4
DQMA#5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

128@
1

C970
10U_0603_6.3V6M

1
R869

F3
C7

+1.5VSDGPU

C969
10U_0603_6.3V6M

19 CLKA1#

2
40.2_0402_1%

QSA4
QSA5

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

128@
1

C968
10U_0603_6.3V6M

1
R868

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

K1
L2
J3
K3
L3

D7
C3
C8
C2
A7
A2
B8
A3

VREFDA_Q3
VREFCA_A3

0.1U_0402_16V4Z

1

C951
1U_0402_6.3V6K

128@
19 CLKA1

19 ODTA1
19 CSA1#
19 RASA1#
19 CASA1#
19 WEA1#

ODTA1

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

+1.5VSDGPU

VREFDA_Q1

C950
1U_0402_6.3V6K

4

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

15mil

R859
4.99K_0402_1%
128@

C949
1U_0402_6.3V6K

C395
0.01U_0402_16V7K
2
128@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CLKA1
CLKA1#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

128@
1

2
40.2_0402_1%
1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M2
N8
M3

19 CKEA1

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A_BA0
A_BA1
A_BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

0.1U_0402_16V4Z

2

C948
1U_0402_6.3V6K

19 CLKA0#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

0.1U_0402_16V4Z

128@

0.1U_0402_16V4Z

1

C939

128@
1
R867

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

1

1
2

15mil

C947
1U_0402_6.3V6K

2
40.2_0402_1%

+1.5VSDGPU

BA0
BA1
BA2

+1.5VSDGPU

128@

MDA14
MDA11
MDA12
MDA10
MDA13
MDA9
MDA15
MDA8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

R854
4.99K_0402_1%
128@

VREFCA_A1

1
R866

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

VREFCA_A3
VREFDA_Q3

R851
4.99K_0402_1%
128@

R858
4.99K_0402_1%
128@

19 CLKA0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

+1.5VSDGPU

R850
4.99K_0402_1%
128@

3

J1
L1
J9
L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

K1
L2
J3
K3
L3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

19 ODTA0
19 CSA0#
19 RASA0#
19 CASA0#
19 WEA0#

ODTA0

+1.5VSDGPU

VREFCA
VREFDQ

1

19 CKEA0

J7
K7
K9

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

2

CLKA0
CLKA0#

D7
C3
C8
C2
A7
A2
B8
A3

VREFDA_Q1
VREFCA_A1

1

M2
N8
M3

19 A_BA0
19 A_BA1
19 A_BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA23
MDA19
MDA22
MDA18
MDA21
MDA16
MDA20
MDA17

1

QSA#[0..7]

19 QSA#[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

2

QSA[0..7]

19 QSA[0..7]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

U57

2

DQMA#[0..7]

19 DQMA#[0..7]

VREFCA
VREFDQ

1

MDA[0..63]

19 MDA[0..63]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

MAA[0..15]

19 MAA[0..15]
1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

E

U56

2

VREFCA_A1 M8
VREFDA_Q1 H1

D

U55

2

U54

2

A

2013/07/10

Deciphered Date

Title

VRAM_DDR3 / Channel A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, March 26, 2013
E

22

of

52

Rev
1.0

B

C

19 QSB[0..7]
19 QSB#[0..7]

DQMB#[0..7]
QSB[0..7]
QSB#[0..7]

M2
N8
M3

19 B_BA0
19 B_BA1
19 B_BA2

CLKB0
CLKB0#
19 CKEB0
19 ODTB0
19 CSB0#
19 RASB0#
19 CASB0#
19 WEB0#

ODTB0

J7
K7
K9
K1
L2
J3
K3
L3

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

2

VRAM_RST#

19,22 VRAM_RST#

T2

1

L8

R870
243_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB31
MDB26
MDB25
MDB29
MDB28
MDB30
MDB24
MDB27

D7
C3
C8
C2
A7
A2
B8
A3

MDB12
MDB11
MDB15
MDB9
MDB13
MDB8
MDB14
MDB10

VREFDB_Q1 M8
VREFCB_A1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

VGA@

J1
L1
J9
L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB0
CLKB0#
CKEB0

J7
K7
K9

ODTB0
CSB0#
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R871
243_0402_1%

J1
L1
J9
L9

VGA@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

MDB23
MDB16
MDB22
MDB18
MDB21
MDB19
MDB20
MDB17

D7
C3
C8
C2
A7
A2
B8
A3

MDB2
MDB4
MDB0
MDB6
MDB3
MDB7
MDB1
MDB5

VREFCB_A3 M8
VREFDB_Q3 H1
N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#

J7
K7
K9

19 CKEB1

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

19 ODTB1
19 CSB1#
19 RASB1#
19 CASB1#
19 WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODTB1

K1
L2
J3
K3
L3

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R872
243_0402_1%

VGA@

J1
L1
J9
L9

U61

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

D7
C3
C8
C2
A7
A2
B8
A3

MDB46
MDB43
MDB47
MDB41
MDB44
MDB42
MDB45
MDB40

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODTB1
CSB1#
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB6
QSB7

F3
C7

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R873
243_0402_1%

J1
L1
J9
L9

VGA@

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

2

+1.5VSDGPU

1

1

VREFDB_Q3
C982

2

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

2

2

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

C1000
1U_0402_6.3V6K

2

VGA@
1

+1.5VSDGPU

+1.5VSDGPU

1 VGA@

2

1
VGA@ VGA@
2

1

2

VGA@
C1037
10U_0603_6.3V6M

2012/07/10

2

1

C1035
10U_0603_6.3V6M

2

VGA@

VGA@

C1036
10U_0603_6.3V6M

1

C1013
10U_0603_6.3V6M

2

C1012
10U_0603_6.3V6M

2

1
VGA@ VGA@

2013/07/10

Deciphered Date

Title

VRAM_DDR3 / Channel B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

C1011
10U_0603_6.3V6M

2

VGA@

C1038
10U_0603_6.3V6M

1

C1010
10U_0603_6.3V6M

2

1

C1008
10U_0603_6.3V6M

2

C1007
10U_0603_6.3V6M

2

C1006
10U_0603_6.3V6M

2

C1034
10U_0603_6.3V6M

2

2

C1033
10U_0603_6.3V6M

2

C1032
10U_0603_6.3V6M

1 VGA@

C1031
10U_0603_6.3V6M

1 VGA@ 1 VGA@ 1 VGA@

C1009
10U_0603_6.3V6M

2

2

VGA@
1

C999
1U_0402_6.3V6K

+1.5VSDGPU

VGA@
1

C998
1U_0402_6.3V6K

2

VGA@
1

C1005
1U_0402_6.3V6K

2

VGA@

1

C1004
1U_0402_6.3V6K

2

R887
4.99K_0402_1%
VGA@

C1003
1U_0402_6.3V6K

2

VGA@

C997
1U_0402_6.3V6K

2

1
C410
0.01U_0402_16V7K
VGA@

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

1
2

2
1

1

C981

C996
1U_0402_6.3V6K

2

VGA@
1

C995
1U_0402_6.3V6K

2

VGA@
1

C994
1U_0402_6.3V6K

2

VGA@
1

C993
1U_0402_6.3V6K

VGA@
1

C992
1U_0402_6.3V6K

VGA@
1

C991
1U_0402_6.3V6K

VGA@
1

C985
1U_0402_6.3V6K

VGA@
1

+1.5VSDGPU

2

1

+1.5VSDGPU

BA0
BA1
BA2

C1002
1U_0402_6.3V6K

2

2

R886
4.99K_0402_1%
VGA@

C1001
1U_0402_6.3V6K

2

1

1 VGA@ 1 VGA@ 1 VGA@

R893
40.2_0402_1%
1 VGA@ 2

MDB59
MDB62
MDB58
MDB63
MDB56
MDB61
MDB57
MDB60

3

0.1U_0402_16V4Z

VGA@

VGA@
1

C990
1U_0402_6.3V6K

R892
40.2_0402_1%
1 VGA@ 2

C409
0.01U_0402_16V7K
VGA@

D7
C3
C8
C2
A7
A2
B8
A3

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

VREFCB_A3
C978

+1.5VSDGPU

C989
1U_0402_6.3V6K

R891
40.2_0402_1%
1 VGA@ 2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

R879
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

2

C988
1U_0402_6.3V6K

19 CLKB1#

J7
K7
K9

+1.5VSDGPU

2

4

CLKB1
CLKB1#
CKEB1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

1
2
1

VREFDB_Q1

R883
4.99K_0402_1%
VGA@

+1.5VSDGPU

1

19 CLKB1

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

R878
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

VGA@

0.1U_0402_16V4Z

1

C977

C987
1U_0402_6.3V6K

19 CLKB0#

B_BA0
B_BA1
B_BA2

VREFCA
VREFDQ

+1.5VSDGPU

VREFCB_A1

R890 40.2_0402_1%
1 VGA@ 2

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

R875
4.99K_0402_1%
VGA@

R882
4.99K_0402_1%
VGA@

19 CLKB0

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VSDGPU

BA0
BA1
BA2

+1.5VSDGPU
R874
4.99K_0402_1%
VGA@

3

VREFDB_Q3 M8
VREFCB_A3 H1

1

1

MDB[0..63]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

19 MDB[0..63]
19 DQMB#[0..7]

MAB[0..15]

VREFCA
VREFDQ

1

19 MAB[0..15]

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

E

U60

2

VREFCB_A1 M8
VREFDB_Q1 H1

D

U59

2

U58

2

A

D

Sheet

Tuesday, March 26, 2013
E

23

of

52

Rev
1.0

5

4

3

2

1

+3VS_TL
+3VS_TL

2
R928

1
TL@

U50 TL@

30mil
0_0603_5%

60mil

40mil 3
60mil13
18

60mil12

11
27
7

+1.2V_TL

60mil

DP_V33

TXEC+
TXEC-

SWR_VDD
PVCC

TXE2+
TXE2-

SWR_LX
SWR_VCCK
VCCK
DP_V12

Close to Pin3

2

1

25 EDP_TXP0_C_TL
25 EDP_TXN0_C_TL

1

2

Close to P18

2

1

2

Close to
Pin27

Close to
L6

LANE0P
LANE0N

8
4

TL@
R938
12K_0402_1%

CIICSCL1
CIICSDA1
HPD

TXOUT2+ 25
TXOUT2- 25

23
24

TXOUT1+
TXOUT1-

TXOUT1+ 25
TXOUT1- 25

25
26

TXOUT0+
TXOUT0-

TXOUT0+ 25
TXOUT0- 25

14
15
16
17

R932 1 TL@
R948 1 TL@
R934 1 TL@

29
28

I2CC_SCL
I2CC_SDA

31
30

MODE_CFG1
MODE_CFG0

D

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

TL_INVT_PWM 25
TL_ENVDD 25
PCH_INV_PWM 25,8
TL_BKOFF# 25

MIICSCL0
MIICSDA0
GND

I2CC_SCL 25
I2CC_SDA 25

C

33

+3VS_TL

TL@
RP41
I2CC_SCL
I2CC_SDA
CSCL
CSDA

1
2
3
4

8
7
6
5

+3VS_TL
+3VS_TL

2

2
R944
4.7K_0402_5%
TL@

B

2

1

2

@
R943
4.7K_0402_5%

1

MODE_CFG0
MODE_CFG1
CSDA 1
@
R946
4.7K_0402_5%

6

EC_SMB_DA2 18,34,7

DMN66D0LDW-7_SOT363-6
CSCL

1

1

R945
4.7K_0402_5%
TL@

@
Q53A

5

2

ROM

MIICSCL1
MIICDA1

4.7K_8P4R_5%

2

1

LVDS
EDID

2

1

2

TXOUT2+
TXOUT2-

use 2132S symbol

2

1

21
22

RTD2132R-CG_QFN32_5X5
Part Number = SA000069200

1

Close to
Pin7
C1021
TL@
0.1U_0402_16V4Z

C1017
TL@
0.1U_0402_16V4Z

2

C1022
TL@
0.1U_0402_16V4Z

C1014
TL@
10U_0603_6.3V6M

1

GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)

DP_REXT
DP_GND

+1.2V_TL

B

TXOUT_CLK+ 25
TXOUT_CLK- 25

1

C1018
TL@
0.1U_0402_16V4Z

C1019
TL@
0.1U_0402_16V4Z

C986
TL@
22U_0805_6.3V6M

C1020
TL@
0.1U_0402_16V4Z

C984
TL@
10U_0603_6.3V6M

2

1

32

TL_HPD

R936
1K_0402_5%
TL@

SWR_VDD

2

AUX_P
AUX_N

Other

Close to Pin13

1

9
10

CSCL
CSDA

25 EDP_HPD

1

TXOUT_CLK+
TXOUT_CLK-

2

C

Close to L64

5
6

2

1

TXE0+
TXE0-

DP-IN

2

C983
TL@
0.1U_0402_16V4Z

C1015
TL@
0.1U_0402_16V4Z

C1016
TL@
10U_0603_6.3V6M

1

2
1

TXE1+
TXE1-

19
20

RTD2132S

DP_V33
25 EDP_AUXP_C_TL
25 EDP_AUXN_C_TL

Power

+1.2V_TL

D

TL@
1 DP_V33
L63 2
HCB2012KF-221T30_0805
TL@
1 SWR_VDD
L73 2
HCB2012KF-221T30_0805
2
TL@ L6 1
+1.2V_TL_OUT
4.7UH_PG031B-4R7MS_1.1A_20%

LVDS

30mil

GPIO

+3VS

4

@
Q53B
3

EC_SMB_CK2 18,34,7

DMN66D0LDW-7_SOT363-6

MODE_CFG0(PIN30)
0
1
X
EP MODE
0
MODE_CFG1(PIN31)
1 ROM ONLY MODE* EEPROM MODE

A

Compal Secret Data

Security Classification
Issued Date

A

2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

LVDS Translator - RTD2132R
Document Number

Rev
1.0

V5WE2 M/B LA-9532P Schematic
Tuesday, March 26, 2013

Sheet
1

24

of

52

A

B

C

D

E

Place closed to JLVDS1
+LCDVDD
+3VS

LCD POWER CIRCUIT

1
+3VS

+LCDVDD
U8

1

OUT

5

W=60mils

1

IN

1

2

1

IN

1

EN

2
C367 2
4.7U_0603_6.3V6K

3

L11
HCB2012KF-221T30_0805
2
1
XEMC@
EMC@
1
1 XEMC@
C365
SM01000EJ00
68P_0402_50V8J

C368
0.1U_0402_16V4Z
@

G5243T11U_SOT23-5

2

R947 1

8 PCH_ENVDD

@

B+

W=60mils

2

2 0_0402_5%

C364
1000P_0402_50V7K

C140
1U_0402_6.3V6K

GND

4

+INVPWR_B+

2

W=60mils

C375

@

0.1U_0402_16V4Z

1

2

C419
0.1U_0402_16V4Z

1

3000ma
220ohm@100mhz
DCR 0.04

2

24 TL_ENVDD

5

+3VS

2

GND OUT Y

4

P

B

INVTPWM

INVTPWM

1

A

4 EDP_DISP_UTIL

2 0_0402_5%

R404 1

@

2 0_0402_5%

2 220P_0402_50V7K
2 220P_0402_50V7K

LCD/ LED PANEL Conn.
2

@
1 R959
2
100K_0402_5%

3
R949 1

@

2 0_0402_5%

R280 1

@

2 10K_0402_5%
+INVPWR_B+

W=60mils

R393
@ 10K_0402_5%

24 TL_INVT_PWM

+LCDVDD
+3VS

INVTPWM
DISPOFF#

2

24 I2CC_SCL
24 I2CC_SDA

eDP
3

C372
C371
C377
C376

4 EDP_TXN0
4 EDP_TXP0

1
1
1
1

2
2
2
2

C374 1
C373 1

4 EDP_TXN1
4 EDP_TXP1

24 TXOUT024 TXOUT0+
EDP@ 0.1U_0402_16V7K
EDP@ 0.1U_0402_16V7K
TL@ 0.1U_0402_16V7K
TL@ 0.1U_0402_16V7K

24 TXOUT124 TXOUT1+

EDP_TXN0_C
EDP_TXP0_C
EDP_TXN0_C_TL
EDP_TXP0_C_TL

+5VS

EDP_TXN0_C_TL 24
EDP_TXP0_C_TL 24

+5VS_TS

24 TXOUT224 TXOUT2+

R81
0_0603_5%
1 TS@
2

2 0.1U_0402_16V7K EDP_TXN1_C
2 0.1U_0402_16V7K EDP_TXP1_C

24 TXOUT_CLK24 TXOUT_CLK+

EDP@
C369 1
C370 1
EDP@
C388 1
C389 1

2 0.1U_0402_16V7K EDP_AUXN_C R613 2
2 0.1U_0402_16V7K EDP_AUXP_C R614 2
2 TL@
2 TL@

34 TS_EN

0.1U_0402_16V7K
0.1U_0402_16V7K

EDP_AUXN_C_TL 24
EDP_AUXP_C_TL 24

+3VS

R414 1 TS@
R424 1
@

2 0_0402_5%
2 0_0402_5%

TS_EN_1

R425 1
@
R426 1 TS@

2 0_0402_5%
2 0_0402_5%

TS_EN_2

TS_INT_1 for TS one chip solution
TS_INT_2 for TS two chip solution
+5VS

3

TXOUT_CLKTXOUT_CLK+

EDP_HPD
USB20_P6
USB20_N6

10 USB20_P6
10 USB20_N6

Touch Screen

+3VS
10 USB20_P7
10 USB20_N7

USB20_P7
USB20_N7

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

3

SP010014B00

CONN@
EDP_HPD

EDP_HPD 24

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R364
100K_0402_5%

2012/07/10

Deciphered Date

2013/07/10

Title

eDP Connector

2

2

TS_EN_2
TXOUT2TXOUT2+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

ACES_50203-04001-001

D

S
1
@
R406
0_0402_5%

TS_EN_1
TXOUT1TXOUT1+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1

2

2

G

4

8 CPU_EDP_HPD

Q13
L2N7002LT1G_SOT23-3
@
1

+5VS_TS

EDP_AUXN_C
EDP_AUXP_C

For Camera

1
R383
10K_0402_5%
@

TXOUT0TXOUT0+

EDP_TXN1_C
EDP_TXP1_C

1 100K_0402_1%
1 100K_0402_1%

@
@

I2CC_SCL
I2CC_SDA

EDP_TXN0_C
EDP_TXP0_C

+3VS
4 EDP_AUXN
4 EDP_AUXP

JLVDS1

W=60mils

2 100K_0402_5%

1

24,8 PCH_INV_PWM

@

DISPOFF#

XEMC@
C549 1
XEMC@
C528 1

U22
TL@
NC7SZ08P5X_NL_SC70-5

R951 1 TL@
R363 1

4

Y

1
R401
1K_0402_5%
@

IN A

3

TL_BKOFF#

24 TL_BKOFF#

2

1
2
@
R362
100K_0402_5%

2

34 BKOFF#

+3VS

2

G

+3VS
U20
@
M74VHC1GT125DF2G_SC70-5
5
1
OE
Vcc

BKOFF#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

25

of

52

Rev
1.0

B

C

U3

1

OUT
1
1
C398
0.1U_0402_16V4Z
2
EMC@

1
C396
0.1U_0402_16V4Z
2
EMC@

3

W=40mils

C381
C382
C379
C380

2
2
2
2

1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+

4
3
2
1

4
4
4
4

CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

C383
C384
C385
C386

2
2
2
2

1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+

4
3
2
1

C378
0.1U_0402_16V4Z
2 EMC@

2

5
6
7
8

HDMI_CLK-

R368 1 XEMC@ 2 0_0402_5%

HDMI_R_CK-

HDMI_CLK+

R369 1 XEMC@ 2 0_0402_5%

HDMI_R_CK+

HDMI_TX0-

R370 1 XEMC@ 2 0_0402_5%

HDMI_R_D0-

HDMI_TX0+

R371 1 XEMC@ 2 0_0402_5%

HDMI_R_D0+
1

RP18
680_8P4R_5%

1

IN
GND

CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N0
CPU_DP2_P0

3

+5VS

4
4
4
4

E

SM070001310 400ma 90ohm@100mhz DCR 0.3

HDMI_GND

+HDMI_5V_OUT

D

RP17
680_8P4R_5%
5
6
7
8

5
Q14B
DMN66D0LDW-7_SOT363-6

HDMI_TX1-

R372 1 XEMC@ 2 0_0402_5%

HDMI_R_D1-

HDMI_TX1+

R373 1 XEMC@ 2 0_0402_5%

HDMI_R_D1+

HDMI_TX2-

R374 1 XEMC@ 2 0_0402_5%

HDMI_R_D2-

HDMI_TX2+

R375 1 XEMC@ 2 0_0402_5%

HDMI_R_D2+

+3VS

AP2330W-7_SC59-3

Reserved for ESD

4

A

+3VS
1

+3VS

2

Q14A
DMN66D0LDW-7_SOT363-6

1

6

HDMI_HPD
1

8 CPU_HDMI_HPD

2

R376
1M_0402_5%

1
R121
100K_0402_5%
2

2

3

+HDMI_5V_OUT
+3VS

1
2
3
4

2

C387
220P_0402_50V7K
EMC@

RP15
2.2K_0804_8P4R_5%
8
HDMI_SCLK
7
HDMI_SDATA
6 DDI2_CTRL_CK
5 DDI2_CTRL_DATA

2

HDMI connector
HDMI_HPD

32 HDMI_HPD
+HDMI_5V_OUT

HDMI_SDATA
HDMI_SCLK

2

6

4

HDMI_R_CK-

Q15A
DMN66D0LDW-7_SOT363-6

HDMI_R_CK+
HDMI_R_D0-

HDMI_SCLK

3
HDMI_SDATA
Q15B
DMN66D0LDW-7_SOT363-6

HDMI_R_D0+
HDMI_R_D1-

D2
XEMC@

YSLC05CH_SOT23-3

5

1

8 DDI2_CTRL_CK
8 DDI2_CTRL_DATA

2

3

+3VS

1

+3VS

3

JHDMI1

Place closed to JHDMI1

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

Reserved for ESD

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

20
21
22
23

ACON_HMR2U-AK120C
CONN@

ZZZ

DC232002700

4

Issued Date

45@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

HDMI_ROYALTY
ROYALTY HDMI W/LOGO+HDCP

RO0000003HM

2012/07/10

Deciphered Date

4

2013/07/10

Title

HDMI Conn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

26

of

52

5

4

3

2

+1.8VS_6511

+1.8VS_RXVDD

1

+1.8VS_6511

+1.8VS_DAC

+3VS_6511

+1.8VS_6511

8 DDI1_AUX_DP
8 DDI1_AUX_DN
+3VS

C70
C71

2
2

1 0.1U_0402_16V7K CPU_DP1_C_P1
1 0.1U_0402_16V7K CPU_DP1_C_N1

33
34

R50 2
R421 2

@
@

1 1M_0402_5%
1 100K_0402_5%

R400 1
R415 1

@
@

2 0_0402_5%
2 0_0402_5%

R420 2
R51 2

@
@

1 100K_0402_5%
1 1M_0402_5%

2
2

4.2mA

100.5mA

RX0P
RX0N

MCUVDD

RX1P
RX1N

MCURSTN

ISPSCL
ISPSDA

24
23

RXAUXP
RXAUXN

22
21

VGADDCCLK
VGADDCSDA

DCAUXP
DCAUXN

VSYNC
HSYNC

1

2 0.1U_0402_16V4Z
C496 1
1
2
1
2
R133
4.7K_0402_5%
C614
MCURSTN
0.1U_0402_16V4Z

50
53
32

@

1
1
1
1

T97

19
20

ISPSCL_R
ISPSDA_R

27
25

R397 2
R398 2

2
2
2
2

@
@

R413
R412
R411
R410

CRT_CLK_1

@

CRT_DATA 28

4

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

ISPSCL 28
ISPSDA 28
C

1 22_0402_5%
1 22_0402_5%

1
2

CRT_CLK_1
CRT_DATA_1

CRT_CLK_1 28
CRT_DATA_1 28

VSYNC 28
HSYNC 28
+3VS

DVDD18
DVDD18
DVSS18

47.3mA

IORN
IORP
VGADETECT

39

ASPVCC

RSET

6.158mA
0.293mA

R193 1
R194 1

@

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

42

6511_PWR_EN

VDDA

INT#
COMP

48
47

PCSDA
PCSCL

Note: need external PU to 2K ~ 10K

XTALIN
XTALOUT

43

SYSRSTN

IT6511FN_QFN56_7X7

3

1

10
9

R76

7
6

R147 1

1

2

37.4_0402_1%
CRT_B

1

2

CRT_B 28

6511_PWR_EN#

R396
1K_0402_5%
2@
1

Q25
DMG2301U-7_SOT23-3

@

37.4_0402_1%
CRT_G

2

CRT_G 28

1

CRT_R 28

2

37.4_0402_1%
CRT_R

18

C411
0.1U_0402_16V7K
@

VGADETECT 28
R196 1

3

2 100_0402_1%

5

+1.8VS_DAC

1

4
41
40

2 C500
0.1U_0402_16V4Z

XTALIN_6511
XTALOUT_6511

B

+3VS

GND

R134 1

R53

@
R584
100K_0402_5%

R419
1M_0402_5%

57

+3VS

B

13
12

+3VS_6511

2

+1.8VS_RXVCC

R80
0_0603_5%
1
2
@

1

28
37
36

+1.8VS_DAC

1

IOBN
IOBP
IOGN
IOGP

+1.8VS_RXVDD

8
11
14

1

41.6mA

IT6511FN

VDDC
VDDC
VDDC

C35
EMC@
470P_0402_50V7K
1
2

R197
75_0402_1% 2
R199
75_0402_1% 2
R201
75_0402_1% 2

PVCC
PVCC

65.5mA

45

G

26
38

56.95mA

CRT_CLK 28

Q27B
DMN66D0LDW-7_SOT363-6

D

AVCC
AVCC

1

6
Q27A
DMN66D0LDW-7_SOT363-6
3

S

+1.8VS_RXVCC

35
29

R123
2.2K_0402_5%

2

2

R127
2.2K_0402_5%
2
1

1

C477
2 0.1U_0402_16V4Z

1

51

For EMI

OSCOUT
+1.8VS_RXVCC

C579
0.1U_0402_16V4Z

C75
1U_0402_6.3V6K

C473 @
0.1U_0402_16V4Z

R230
4.7K_0402_5%

CRT_DATA_1

MCUVDDH

URDBG
C72
0.1U_0402_16V7K
1
DDI1_AUX_C_DP
1
DDI1_AUX_C_DN
C73
0.1U_0402_16V7K
DDI1_AUX_DP_R
DDI1_AUX_DN_R

+HDMI_5V_OUT
+3VS

+3VS

1.52mA

IVDD
IVDD
IVDD
IVDD

OVDD
OVDD
OVDD

DDCSCL
DDCSDA

30
31

+3VS

XTALOUT_6511

XTALIN_6511

2

GND

IN

2
G
Q52
L2N7002LT1G_SOT23-3
@

1
C74

2

D

S

6511_PWR_EN

45 6511_PWR_EN

1
18P_0402_50V8J

1
C65

18P_0402_50V8J

2

6511_PWR_EN#

38 6511_PWR_EN#

X4
27MHZ_10PF_X3G027000BA1H-U
Crystal
3
4
OUT
GND

1

C

1 0.1U_0402_16V7K CPU_DP1_C_P0
1 0.1U_0402_16V7K CPU_DP1_C_N0

2

1

+3VS

2
2

1

3

4 CPU_DP1_P1
4 CPU_DP1_N1

C68
C69

HPD

2

2

4 CPU_DP1_P0
4 CPU_DP1_N0

44

1

D

R234
4.7K_0402_5%

2

U42
DP_HPD

2

5

R418
4.7K_0402_5%

1

2

Q24
L2N7002LT1G_SOT23-3
@

R240
4.7K_0402_5%
1
2
@
1
2
@
R241
4.7K_0402_5%

1

2

+1.8VS_RXVDD

17
15
49
52

D

+3VS

2
2

S

DP_HPD

55
56

1
1

3

@

1
1
2

G

8 CPU_DP_HPD

+3VS_6511

2 0_0603_5%

2 0_0603_5%

@

ISPSCL_R
ISPSDA_R

R407
22_0402_5%

2

@

2

Can be remove after MP

+5VS

1

1

+1.8VS_RXVCC

1

L47

16
46
54

2 0_0402_5%

@

R408
22_0402_5%

1

R399

2

1

D

1

C472
0.1U_0402_16V4Z

2

C498
0.1U_0402_16V4Z

2

1

C519
4.7U_0603_6.3V6K

2

1

L48

C457
0.1U_0402_16V4Z

1

C455
10U_0603_6.3V6M

@

2 0_0603_5%

@

C476
4.7U_0603_6.3V6K

1

L30

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

ITE IT6511FN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, March 26, 2013
1

27

of

52

Rev
1.0

A

B

C

D

E

W=40mils

1

1

+HDMI_5V_OUT

CRB1.0 use 47ohm@100Mhz Bead

27 CRT_R
27 CRT_G
27 CRT_B

JCRT1

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_G_2
CRT_B_2

2

1

2

1

2

C616
10P_0402_50V8J

1

C618
10P_0402_50V8J

2

CRT_R_2

C647
10P_0402_50V8J

2

1

C611
10P_0402_50V8J

1

C615
10P_0402_50V8J

2

C648
10P_0402_50V8J

1

CRT Connector

27 ISPSDA
27 ISPSCL

L42
EMC@
BLM18BA470SN1D_2P
1
2
L45
EMC@
BLM18BA470SN1D_2P
1
2
L46
EMC@
BLM18BA470SN1D_2P
1
2

G
G

16
17

C-H_13-12201560CP
CONN@
R175
1 XEMC@ 2 0_0603_5%

2

+HDMI_5V_OUT
U24

1
R439
0_0402_5%
2
1
@

27 HSYNC

2

CRT_HSYNC

Vcc

5

0.1U_0402_16V4Z

2

@
1 C447

R180
1 XEMC@ 2 0_0603_5%
@
C448
10P_0402_50V8J

IN A
GND OUT Y

4

CRT_HSYNC_1

2

CRT_HSYNC_2

1

2

@

CRT_CLK 27
CRT_DATA 27

CRT_VSYNC_2
1

2

C449
10P_0402_50V8J
VGADETECT 27

1

3

OE

DC060006E00

M74VHC1GT125DF2G_SC70-5

2
@
R441
0_0402_5%

27 VSYNC

1

R312
0_0402_5%
@

+HDMI_5V_OUT

R239
0_0402_5%
2
1
@

2

CRT_VSYNC

3

OE

Vcc

2

U23

1

5

IN A
GND OUT Y

4

CRT_VSYNC_1

M74VHC1GT125DF2G_SC70-5
3

3

C451 @
2 0.1U_0402_16V4Z
2
C452 @
0.1U_0402_16V4Z

VCC_SYNC
VCC_VIDEO
VCC_DDC

U10

+HDMI_5V_OUT
+3VS

1
2
7

1
1

CRT_CLK_1
CRT_DATA_1

10
11

1
2
C454
0.1U_0402_16V4Z
@

4

For contact

8

discharge ESD +/-8kV

SYNC_IN1
SYNC_IN2
DDC_IN1
DDC_IN2

VIDEO_1
VIDEO_2
VIDEO_3

SYNC_OUT1
SYNC_OUT2
DDC_OUT1
DDC_OUT2

BYP
GND

13
15

6

27 CRT_CLK_1
27 CRT_DATA_1

HSYNC
VSYNC

3
4
5

CRT_R_2
CRT_G_2
CRT_B_2

14
16

CRT_HSYNC_1
CRT_VSYNC_1

9
12

CRT_CLK
CRT_DATA

4

DDC_CLK/DAT reserved PU Resistor
CM2009-00QR_QSOP16
@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

28

of

52

Rev
1.0

5

4

3

2

1

+1.2V_LAN
+VDDO_CR

VDDC
VDDC

XTALVDDH
AVDDH
AVDDH

+3V_LAN

D

VDDO
VDDO
VDDO
TRD3_N
TRD3_P
TRD2_N
TRD2_P

39
45
51

+LAN_AVDDL

R02 modify

for ESD

+LAN_GPHYPLLVDDL

36

+LAN_PCIEPLLVDD

32

AVDDL
AVDDL
AVDDL

TRD1_N
TRD1_P
TRD0_N
TRD0_P

GPHY_PLLVDDL

2 0.1U_0402_16V4Z PLT_RST_BUF#

SO_LINKLED#

1
1

0.1U_0402_16V7K
0.1U_0402_16V7K

R763 1

34 EC_PME#

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N

TRAFFICLED#_SERIALDI
GPIO1_LR_OUT
GPIO_0

2 4.7K_0402_5%

R765 1

8 PCH_PCIE_WAKE#

PCIE_PRX_C_DTX_P3 28
PCIE_PRX_C_DTX_N3 27
33
34

2 0_0402_5%

@

R764 1

+3V_LAN

C

2 C788
2 C791

2 0_0402_5%

@

SI_EEDATA
CS#_EECLK

3

LAN_PME#

PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SD_DETECT/XD_WE#

30
30
30
30

CR_DATA0 R768
CR_DATA1 R769
CR_DATA2 R770
CR_DATA3 R771

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

1
1
1
1

EMC@
EMC@
EMC@
EMC@

2
2
2
2

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R

SR_DISABLE/XD_DETECT#

25
24
23
22
52
53
54
55

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
CR_CLK/XD_RY_BY#

+3VS
R776 1

2 1K_0402_5%

R777 1

2 4.7K_0402_5% 6

LAN_MIDI3LAN_MIDI3+

47
46

LAN_MIDI2LAN_MIDI2+

43
44

LAN_MIDI1LAN_MIDI1+

41
40

LAN_MIDI0LAN_MIDI0+

1

LAN_MIDI3- 30
LAN_MIDI3+ 30

EMC@

C815
0.1U_0402_16V4Z

2 R781
10K_0402_5%
1
2

LAN_MIDI2- 30
LAN_MIDI2+ 30

1

LAN_MIDI1- 30
LAN_MIDI1+ 30

2

65

20mil
+LAN_XTALVDDH
C785

20mil

1

66

1

R760 2

@

1

R761 1

@

2 0_0603_5%

5

5IN1_LED_R#

R762 2

@

1

64
63

SPROM_DOUT
SPROM_CLK

1

CR_XD_WE#_SD_DETECT_R

R767 2

@

1

0_0402_5%

CR_XD_WE#_SD_DETECT

0_0402_5%

0_0402_5%

D

+3V_LAN

1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
L58

C789
@
0.1U_0402_16V4Z

LAN_ACTIVITY# 30
+VDDO_CR

2

L57

1
2
BLM18AG601SN1D_2P

+LAN_AVDDH

+VDDO_CR_R

2

2

20mil

2

8

1

@

L56
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

2

LAN_LINK# 30

67

1

LAN_PWR_EN# 34

C792
0.1U_0402_16V4Z

2

LAN_MIDI0- 30
LAN_MIDI0+ 30

2

60mil

1

C790

2

1

2

0.1U_0402_16V4Z

+VDDO_CR

5IN1_LED# 35

C

WAKE#

11
31
30

31,8 PLT_RST_BUF#
7 CLK_PCIE_LAN
7 CLK_PCIE_LAN#

49
50

2

@

C787

SCLK_SPD1000LED#

PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

+LAN_AVDDH

+3V_LAN
1

+LAN_BIASVDDH

PCIE_PLLVDDL

SPD100LED#_SERIALDO
10
10
10
10

48
42

DMG2301U-7_SOT23-3
Q6
3
1

1

L74
BLM31PG601SN1_2P +3V_LAN
EMC@
1
2
1

PCIE_PLLVDDL

29
C786 1
EMC@

+LAN_XTALVDDH

G

7
56
62

17

2

@

C784
0.1U_0402_16V4Z

2

35
61

1

C783
4.7U_0603_6.3V6K

2

R759
0_0805_5%

+3VALW

+LAN_BIASVDDH

C780
0.1U_0402_16V4Z

2

37

VDDO_CR

2

1

EMC@
+1.2V_LAN
1

C779
4.7U_0603_6.3V6K

BIASVDDH

20

1

0.1U_0402_16V4Z
C803

@

C777
4.7U_0603_6.3V6K

2

C774
0.1U_0402_16V4Z

C773
0.1U_0402_16V4Z

1

D

C772
0.1U_0402_16V4Z

2

@

C820
1U_0402_6.3V6K

2

1

S

C771
4.7U_0603_6.3V6K

U48
1

CR_CMD_XD_CLE

58

CR_XD_WE#_SD_DETECT 30,32

68
59
9
57

CR_WP#_XD_WP#_R

R772 2

@

1

0_0402_5%

CR_WP#_XD_WP#

60

CR_PWR_EN_R

R773 2

@

1

0_0402_5%

CR_PWR_EN

21

CR_CLK_XD_RY_BY#_R

R774 1 EMC@ 2 56_0402_5%

26

CR_CMD_XD_CLE_R

R775

1

CR_WP#_XD_WP# 30

For EMI request

CR_PWR_EN 30
CR_CLK_XD_RY_BY# 30

2 22_0402_5%

CR_CMD_XD_CLE 30

VMAIN_PRSNT

+3V_LAN

1

2

R778

TEST1

10

SR_LX
4

B

LOW_PWR

19
18

LAN_XTALO_R
LAN_XTALI

40mil

TEST2

4.7K_0402_5%

SR_VFB

C793
0.1U_0402_16V4Z

1

RDAC

12

+1.2V_LAN
1

2

2

EMI Request...2010/07/27

C794
10U_0603_6.3V6M

B

SM010005500 500ma 600ohm@100mhz DCR 0.38

R02 Modify
GND PLANE

@

R896
0_0402_5%

15mil38

2 LAN_RDAC
1.24K_0402_1%

40mil
1

CLK_REQ#

SR_VDDP
SR_VDD

20mil

40mil

15
14

+3V_LAN

BCM57786XA1KMLG_QFN68_8X8

1 0.1U_0402_16V4Z
C795

1

2

2

L60
1
2
BLM18AG601SN1D_2P

+LAN_PCIEPLLVDD

4.7U_0603_6.3V6K
C796

C797
0.1U_0402_16V4Z

1

1

2

2

20mil

1

3
GND

2
C799
15P_0402_50V8J
2

GND

SPROM_CLK
(EECLK)

SPROM_DOUT
(EEDATA)

On chip

1

0

AT24C02

1

1

3LAN_XTALO
1

4
2

C800
15P_0402_50V8J

1

2
1
1

1

2

2

1

1

2

2

20mil

C804
0.1U_0402_16V4Z

2012/07/10

+1.2V_LAN

C802
4.7U_0603_6.3V6K

L62
1
2
BLM18AG601SN1D_2P

+1.2V_LAN

C805
4.7U_0603_6.3V6K
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

+LAN_AVDDL
2

SPROM_CLK
SPROM_DOUT

1
2
R783
1K_0402_5%

R779
200_0402_1%

0.1U_0402_16V4Z

R784
1K_0402_5%

1

LAN_XTALI
LAN_XTALO_R

L61
1
2
BLM18AG601SN1D_2P

+LAN_GPHYPLLVDDL
C801

A

4.7U_0603_6.3V6K

PLACE NEXT P14

+3V_LAN

Y6
25MHZ 10PF X3G025000DA1H-X

+1.2V_LAN

C798

69

2

7 LAN_CLKREQ#

13

XTALO
XTALI

Reserved for leakage current
1
R780

L59
2
+1.2V_LAN_OUT 1
4.7UH_PG031B-4R7MS_1.1A_20%

16

2013/07/10

Deciphered Date

Title

Broadcom BCM57786X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, March 26, 2013
1

29

of

52

Rev
1.0

5

4

3

2

1

10
11
12

2

1

2

1

2

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

RJ45_MIDI2RJ45_MIDI2+

18
17
16

RJ45_MIDI1+
RJ45_MIDI1-

15
14
13

RJ45_MIDI0RJ45_MIDI0+

R787
1K_0402_5%
D

C806 1
XEMC@
C807 1
XEMC@

JRJ45

GST5009-E
SP050006B10

1

2

1

TCT3
TD3+
TD3-

21
20
19

R786
1K_0402_5%

LAN Connector

2

29 LAN_MIDI029 LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

MCT2
MX2+
MX2-

RJ45_MIDI3+
RJ45_MIDI3-

2

7
8
9

TCT2
TD2+
TD2-

24
23
22

2

2

CARD READER_2in1 SP07000TF00

RJ45_MIDI0+

R790
75_0402_1%
1
R791
75_0402_1%

LAN_MIDI1+
LAN_MIDI1-

MCT1
MX1+
MX1-

1

RJ45_MIDI0-

2

RJ45_MIDI1+

3

RJ45_MIDI2+

4

RJ45_MIDI2-

5

RJ45_MIDI1-

6

RJ45_MIDI3+

7

RJ45_MIDI3-

8

PR1+

9

LED_YELLOW_A1
PR1LED_YELLOW_A2

LED_GREEN_B1
PR3LED_GREEN_B2

10

C808 1
XEMC@

11

LAN_LINK#

12

C809 1
XEMC@

PR2PR4+

2 220P_0402_50V7K

LAN_ACTIVITY#

PR2+
PR3+

2 220P_0402_50V7K

LAN_ACTIVITY# 29

2 68P_0402_50V8J

LAN_LINK# 29

2 68P_0402_50V8J

13
14

GND
GND

40mil

PR4SANTA_130451-F
CONN@

DC234005300

2

29 LAN_MIDI1+
29 LAN_MIDI1-

TCT1
TD1+
TD1-

1
R788
75_0402_1%
2
1
R789
75_0402_1%
1

4
5
6

C813
0.1U_0402_16V4Z

29 LAN_MIDI229 LAN_MIDI2+

LAN_MIDI2LAN_MIDI2+

C812
0.1U_0402_16V4Z

LAN_MIDI3+
LAN_MIDI3-

C811
0.1U_0402_16V4Z

29 LAN_MIDI3+
29 LAN_MIDI3-

C810
0.1U_0402_16V4Z

D

1

T1

1
2
3

1

+3V_LAN

RJ45_GND

Place close to TCT pin

C

BOTHHAND: S X'FORM_ GST5009-E LF LAN, SP050006B10
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00
MHPC:S X'FORM_ NS892403 LAN , SP050008500

JP1
XEMC@
B88069X9231T203_4P5X3P2-2
2
1

2
C814 1
EMC@
10P_0402_50V8J
1

JP2
XEMC@
B88069X9231T203_4P5X3P2-2

1

+XDPWR_SDPWR_MSPWR

2

2
2

Card Reader Connector

2

1

J15
JUMP_43X118
@

40mil

LANGND

3

1

RJ45_GND

D39 EMC@
L30ESDL5V0C3-2

C

JREAD1

R793
10K_0402_5%

WP SW
CD SW
GND SW
GND SW

Q9
DMG2301U-7_SOT23-3

1 EMC@

Q23
L2N7002LT1G_SOT23-3 D
2
29 CR_PWR_EN
G
S

R782
10K_0402_5%
1
2

2

CR_CLK

R26
1 XEMC@ 2
22_0402_5%

3

SP07000TF00

1
C822
0.1U_0402_16V4Z

T-SOL_156-1000302601_NR
CONN@

C26

1

2
XEMC@

1

2

@

1

2

C819
0.1U_0402_16V4Z

1

40mil
C818
0.1U_0402_16V4Z

3

1

10
11
12
13

DAT0
DAT1
DAT2
CD/DAT3

C821
1U_0402_6.3V6K

CR_WP#_XD_WP#
CR_XD_WE#_SD_DETECT

+XDPWR_SDPWR_MSPWR
L75
BLM31PG601SN1_2P
EMC@
1
2

+3VALW

G

29 CR_WP#_XD_WP#
29,32 CR_XD_WE#_SD_DETECT

8
9
1
2

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

D

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

S

29
29
29
29

B

C817
4.7U_0603_6.3V6K

29 CR_CLK_XD_RY_BY#

SM01000LU00 300ma 22ohm@100mhz DCR 0.3

CMD
VSS
VDD
CLK
VSS

2

R897 2 EMC@ 1
CR_CLK
BLM15BA220SN1D_0402

1

For EMI change to 22 ohm Bead

3
4
5
6
7

CR_CMD_XD_CLE

2

29 CR_CMD_XD_CLE

B

@

1

2

2

6.8P_0402_50V8C

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

LAN Magnetic & RJ45

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

30

of

52

Rev
1.0

A

B

C

D

E

For Wireless LAN
+1.5VS

60mil

+3VS

+3VS_WLAN

1

@ J3

1

2
1

C458

+1.5VS_WLAN

@

1
C459
C460
@
0.1U_0402_16V4Z
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2
2
2

JUMP_43X118

J13
JUMP_43X39
2
1
2

1

@

1

C463
0.1U_0402_16V4Z

2

1

1

+3VS_WLAN

Mini Card Power Rating
+3VS_WLAN

+1.5VS_WLAN
R429 1

2 4.7K_0402_5%
JMINI1

WLAN_PME#
R423
0_0402_5%
1
2
@

34 WLAN_PME#
+3VS_WLAN

7,8 MINI1_CLKREQ#

+3VALW
U9

5
IOAC@
C165
1U_0402_6.3V6K

4
1

OUT

1

W=60mils

7 CLK_PCIE_MINI1#
7 CLK_PCIE_MINI1

IN
GND

2

IN
EN

10 PCIE_PRX_DTX_N4
10 PCIE_PRX_DTX_P4

3

G5243T11U_SOT23-5
IOAC@

2

10 PCIE_PTX_C_DRX_N4
10 PCIE_PTX_C_DRX_P4

34 WLAN_ON
+3VS_WLAN
R435
0_0402_5%
1
2
@
1
2
@

2

1

1

34 E51TXD_P80DATA
34 E51RXD_P80CLK

R436
0_0402_5%
R438
1K_0402_5%
@

2
1

D

3

2

R437
100K_0402_5%

34 BT_ON#

E51TXD_P80DATA_R
E51RXD_P80CLK_R

S

2
G

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GNDGND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

WL_OFF#
PLT_RST_BUF#

WL_OFF# 34
PLT_RST_BUF# 29,8

MINI1_SMBCLK R432 1
MINI1_SMBDATA R434 1

@
@

2 0_0402_5%
2 0_0402_5%

PCH_SMBCLK 7
PCH_SMBDATA 7

USB20_N4 10
USB20_P4 10
R443 1

2 100K_0402_5%

+3VS_WLAN
MINI1_LED# 34

2

54

BELLW_80053-1021
CONN@

DC040009P00

Q20
L2N7002LT1G_SOT23-3
@

3

3

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

MINI CARD (WLAN)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

31

of

52

Rev
1.0

A

B

C

D

E

SATA HDD1 Conn.
CL 4.0 mm

SATA HDD1 Conn.

JHDD2

1

6 SATA_PTX_DRX_P0
6 SATA_PTX_DRX_N0
6 SATA_PRX_DTX_N0
6 SATA_PRX_DTX_P0

C534 1
C535 1

2 BA51@
2 BA51@

0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

C536 1
C537 1

2 BA51@
2 BA51@

0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

+3VS

+5VS

1

JHDD1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

EA50@
EA50@

C392 1
C393 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0_1
SATA_PTX_C_DRX_N0_1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

EA50@
EA50@

C391 1
C394 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N0_1
SATA_PRX_C_DTX_P0_1

R308
0_0402_5%
1
2
@

+3VS

8,9 DEVSLP0

+3VS

R307 1

@

2 0_0402_5%

1

@

2 0_0805_5%

R49

+5VS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS_HDD

+5VS_HDD

+5VS

ACES_50406-02071-001
CONN@

2

1

2

C397
0.1U_0402_16V4Z

C420
10U_0603_6.3V6M

2

C390
0.1U_0402_16V4Z

@

1

1

100mils

2

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

GND
GND
GND
GND

23
24
25
26

CCM_C127043HR022M27FZR_22P-T

2

CONN@

DC231211190

Debug Board
JDB1

29,30 CR_XD_WE#_SD_DETECT
3

26 HDMI_HPD
8 XDP_DBRESET#
34,35 KSI0
34,35 KSO2

51

G1

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

SATA ODD Conn.

PCH_SPI_CLK_1_R 7
PCH_SPI_MOSI_1_R 7
+BIOS_SPI

JODD1
EC_SPICS#/FSEL#_R 34
EC_SI_SPI_SO_R1 34
EC_RST# 34,35

6 SATA_PTX_DRX_P1
6 SATA_PTX_DRX_N1
6 SATA_PRX_DTX_N1
6 SATA_PRX_DTX_P1

ON/OFFBTN# 33,35

+5VS
REC_MODE_L 34
EC UART_RXD 34

C401 1
C402 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C403 1
C405 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

R593
0_0805_5%
1
2
@

+3VALW_EC

SPI_WP1#_R 34,6,7
LID_SW# 33,34
KSI2 34,35
KSO3 34,35
KSO4 34,35

80mils
1

2

C407
0.1U_0402_16V4Z

34 EC UART_TXD

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

1

+EC_SPI

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2

7 PCH_SPI_CS0#_1_R
7 PCH_SPI_MISO_1_R
7 SPI_HOLD1#_R
34 EC_SPICLK
34 EC_SO_SPI_SI_R1

C404
10U_0603_6.3V6M

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

+5VS_ODD
ODD_MD
T185

@

1
2
3
4
5
6
7
8
9
10
11
12
13

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND

3

GND
GND

14
15

SANTA_201902-1_13P-T
CONN@

LTCX004HZ00

52

E&T_1001K-F50C-05R
CONN@

4

Ctrl (L, 58)
Ctrl (R, 64)
D (33)
F3 (114)
Enter (43)
Space (61)

C03,
C01,
C01,
C03,
C01,
C03,

R04
R04
R03
R03
R05
R05

(KSI2,
(KSI0,
(KSI0,
(KSI2,
(KSI0,
(KSI2,

KSO3)
KSO3)
KSO2)
KSO2)
KSO4)
KSO4)

Kill SW
4

SPI_WP1#_R 34,6,7
R569
1K_0402_1%
1 940@ 2

JP5

1
2

+3VALW

1
2

G1
G2

3
4

ACES_87212-02G0
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

HDD/ODD/Debug Board

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

32

of

52

Rev
1.0

A

B

C

D

U3RXDN0

D15
1 1

U3RXDP0

2 2

L24
10 PCH_USB3_TX0_P
10 PCH_USB3_TX0_N

2
C484

1 PCH_USB3_TX0_P_C
0.1U_0402_16V7K

2
C482

1 PCH_USB3_TX0_N_C
0.1U_0402_16V7K

2
3

2

1

3

4

1
4

U3TXDP0

E

+5VALW

For ESD request
U3RXDN0

98

U3RXDP0

U3TXDN0
U3TXDN0

4 4

77

U3TXDN0

U3TXDP0

5 5

66

U3TXDP0

U25

C483 EMC@
0.1U_0402_16V4Z
1
2

XEMC@
109

+USB3_VCCA

1
2
3
4

34 USB_CHARGE_2A#

GND
IN
IN
EN/ENB

W=60mils

8
7
6
5

OUT
OUT
OUT
OCB

1

R454
0_0402_5%
2
@

USB_OC0# 10,9

SY6288D10CAC_MSOP8

DLW21SN900HQ2L-0805_4P
EMC@

3 3
L25
1

PCH_USB3_RX0_P

10 PCH_USB3_RX0_P

2

2

1

1

8

U3RXDP0

1

L05ESDL5V0NA-4 SLP2510P8
PCH_USB3_RX0_N

10 PCH_USB3_RX0_N

3

3

4

4

U3RXDN0

+USB3_VCCA

DLW21SN900HQ2L-0805_4P
EMC@

USB20_N0

10 USB20_N0

2

2

@
@

2 0_0402_5%
2 0_0402_5%

1
C486

4
1

4

220U_6.3V_M

1

+

U2DP0_L

EMC@
1
C487

2
2

U2DN0_L

WCM2012F2SF-670T04_0805
XEMC@

0.1U_0402_16V4Z

USB20_P0

10 USB20_P0

R458 1
R461 1
L26
3
3

W=100mils

U2DN0_L
U2DP0_L
U3RXDN0
U3RXDP0
U3TXDN0
U3TXDP0

SF000002Y00
220U 6.3V OSCON
ESR 17mohm@100Khz

USB3.0 Conn.
JUSB1

1
2
3
4
5
6
7
8
9

VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+

GND
GND
GND
GND

10
11
12
13

OCTEK_USB-09EAAB
CONN@
2

2

DC233008O20

3

3

USB/B
(USB Port 1, Port2)
PWR/B

+5VALW

Finger Print /B

JUSB2

JPWR1

GND
GND

+3VALW
+3VLP
LID_SW# 32,34
PWR_LED# 35
ON/OFFBTN# 32,35

JFP1
USB20_P5
USB20_N5

10 USB20_P5
10 USB20_N5

7
8

4
3
2
1

3

LID_SW#
PWR_LED#
ON/OFFBTN#

+3VS

2

1
2
3
4
5
6

1
2
3
4
5
6

4
3
2
1

G2
G1

6
5

34 USB_EN#
10 USB20_N1
10 USB20_P1

ACES_50504-0040N-001
CONN@

10 USB20_N2
10 USB20_P2

SP01000Z300

ACES_88514-00601-071
CONN@

USB_EN#
USB20_N1
USB20_P1
USB20_N2
USB20_P2

D38
YSLC05CH_SOT23-3
XEMC@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_88514-01201-071
CONN@

SP01001BF00

1

SP010014M00

1
2
3
4
5
6
7
8
9
10
11
12
13
14

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

USB3.0 Conn/USB_B/PWR_B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

33

of

52

Rev
1.0

6,9 EC_SCI#
31 WLAN_ON

12
13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

R488
R492
C511
XEMC@

2 10K_0402_5%
2 10K_0402_5%

@
@
1

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_SMI#
EC_SCI#

2 0.01U_0402_16V7K

PLT_RST#

ESD request

KSI[0..7]

32,35 KSI[0..7]

2

X1 @
32.768KHZ_12.5PF_FC-135
1 EC_XCLK0
EC_XCLK1 2
1
@

2

KSO[0..17]

32,35 KSO[0..17]

1
C513
15P_0402_50V8J

C514
15P_0402_50V8J

2

@

40,41
40,41
18,24,7
18,24,7

8 PM_SLP_S3#
8 PM_SLP_S5#
8 EC_SMI#

R605 1 DEG@ 2 E51TXD_P80DATA
0_0402_5%
R606 1 DEG@ 2 E51RXD_P80CLK
0_0402_5%

32 EC UART_TXD
32 EC UART_RXD

3

32 REC_MODE_L

R565
0_0402_5%

2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

@

25 TS_EN
11,8 VCCST_PG_EC
31 WL_OFF#
40 EC_SPOK
1 37 FAN_SPEED1
31 E51TXD_P80DATA
31 E51RXD_P80CLK
35 PWR_SUSP_LED#

For abnormal shutdown

EC_SPOK

8 SUSCLK

D25
RB751V40_SC76-2
1
2
D26
RB751V40_SC76-2
2
@ 1

TS_EN
VCCST_PG_EC
WL_OFF#
EC_SPOK
FAN_SPEED1
REC_MODE_L_R
E51TXD_P80DATA
E51RXD_P80CLK
9012_PCH_PWROK
PWR_SUSP_LED#

R502 1 940@
R504 2 940@

EC_XCLK1
2
EC_XCLK0
0_0402_5%
1
100K_0402_5%

122
123

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

PCH_RSMRST#
1
C516
940@
PCH_PWROK

2 20P_0402_50V8

9012@

ECAGND

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

63
64
65
66
75
76

BATT_TEMP

68
70
71
72

ADP_I
AD_BID0

EN_DFAN1

2
1

+3VS

EC_MUTE#

R481

1

2 10K_0402_5%

VGATE_3V
USB_CHARGE_2A#
HDA_SDO
VCIN0_PH_R

SPI Flash ROM

GPIO
Bus

GPIO

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

119
120
126
128

1
EC_SI_SPI_SO
R158 2 940@ 49.9_0402_1% EC_SI_SPI_SO_R
1
EC_SO_SPI_SI
R159 2 940@ 49.9_0402_1% EC_SO_SPI_SI_R
1 R160
2 940@ 49.9_0402_1%
EC_SPICLK_R
EC_SPICLK
1 R146
2 49.9_0402_1% EC_SPICS#/FSEL#_R
EC_SPICS#/FSEL#
940@
1 100K_0402_5%
R691 2
ENBKL
ENBKL 8
930_PECI
FSTCHG
FSTCHG 41
BATT_BLUE_LED#
BATT_BLUE_LED# 35
EC_WLAN_LED#
EC_WLAN_LED# 35
PWR_LED
PWR_LED 35
BATT_AMB_LED#
BATT_AMB_LED# 35
SYSON
SYSON 38,43

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

GPI

V18R

73
74
89
90
91
92
93
95
121
127

PM_SLP_S4#

1

1

2 10K_0402_5%

@

R482
0_0402_5%
2
1
@

H_PROCHOT# 39,4,40

D

S

Q50
L2N7002LT1G_SOT23-3

EC_MUTE# 36
LAN_PWR_EN# 29
WLAN_PME# 31
EC_ENTERING_RW 35
TP_CLK 35
TP_DATA 35
VGATE_3V 8
USB_CHARGE_2A# 33
HDA_SDO 6

1

2 0_0402_5%

@

ACIN 39,41,8
2

EC_ACIN

2

C512

1 100P_0402_50V8J

KB930&9012 Co-Layout Item
EC_SPICLK 32
1
R494
R495 1

+EC_VCC

PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT
H_PROCHOT#_EC
GPXIOA07
BKOFF#
PBTN_OUT#
GPU_ACIN
MINI1_LED#

110
112
114
115
116
117
118

EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
VCCST_PWRGD
9012_PECI

124

+V18R

+3VALW
+3VLP

930_PECI

R496 1 940@

9012_PECI

R497 1 9012@ 2 43_0402_1%

2 43_0402_1%

H_PECI 4

Pin74(KB930),Pin118(KB9012) are with different PECI pin location,
so HW must co-layout for it.
Please make sure which EC pin will be connected to PECI circuit.

H_PROCHOT#_EC 40
BKOFF# 25
PBTN_OUT# 8
GPU_ACIN 18
MINI1_LED# 31

2 9012@ 1
9012_PCH_PWROK
R498
0_0402_5%
2 940@ 1
GPXIOA07
R499
0_0402_5%
2 9012@ 1
R500
0_0402_5%

+3VALW_EC

@

@

R697
10K_0402_5%

PCH_PWROK 8
MAINPWON 40,42

KB9012QF-A3_LQFP128_14X14

2

C515
4.7U_0603_6.3V6K

R696
10K_0402_5%
R501 1

VCIN0_PH_R
VCIN1_PROCHOT

2 0_0402_5%

@

PU will disable PH function

D28 design for Debug board flash SPI ROM
(can be short after MP)

VCIN0_PH 40
VCIN1_PROCHOT 40

1 940@
R601
1K_0402_5%

+3VALW_EC

KSO1

R507 2 940@

1 47K_0402_5%

KSO2

R508 2 940@

1 47K_0402_5%

+EC_SPI
KB932 use 256KB ROM
KB9012 Embedded 128KB ROM
D28

EC_SPICS#/FSEL#_R
1 DEG@ 2 EC_SI_SPI_SO_R
R598
0_0402_5%
R510
1
2 4.7K_0402_5% SPI_WP#
@
2

U29
1
2
3
4

/CS
VCC
DO_IO1 /HOLD
/WP
CLK
GND DIO_IO0

8
7
6
5

W25X20BVSNIG_SO8
SA00003GM10
940@

+3VALW_EC
1

2 940@ RB751V40_SC76-2

2 940@ 0.1U_0402_16V4Z
C518 1
R511
1 940@ 2 4.7K_0402_5%
SPI_HOLD#
+EC_SPI
EC_SPICLK
1 DEG@ 2
EC_SO_SPI_SI_R
EC_SO_SPI_SI_R1 32
R600
0_0402_5%
EC_SPICLK

2012/07/10

2 XEMC@ 1
R513
0_0402_5%

4

XEMC@
33P_0402_50V8K

C520

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/07/10

Deciphered Date

Title

EC ENE-KB9012

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

3

Pin104 This co-layouted circuit is for power fail function of
KB930 and KB9012.At KB930, PCH_PWROK will be connected to pin 104.
At KB9012,PCH_PWROK will be connected to pin 32,
and VCOUT0_PH will be connected to pin 104.

20mil

Issued Date

0_0402_5%
2 0_0402_5%

1

+EC_SPI

KB932QF-A0_LQFP128
940@

2

@

Pin 111 is a power source for HW operation of KB9012.
So, power plan will be different between KB930 and KB9012.

PCH_RSMRST# 8
EC_LID_OUT# 9

EC_ON 35,42
ON/OFF 35
LID_SW# 32,33
SUSP# 38,41,43,44,45
VCCST_PWRGD 11,45

32 EC_SPICS#/FSEL#_R
32 EC_SI_SPI_SO_R1

C517
0.1U_0402_16V4Z
@

@

PM_SLP_S4# 8

100
101
102
103
104
105
106
107
108

2
ECAGND 1
L32
BLM18AG121SN1D_2P

SA000055I00

@

Latest design guide suggest change to
74LVC1G06.

EN_DFAN1 37

1
2

4.7K_0402_5%
4.7K_0402_5%

EC_PME# 29

U28

2

2
2

H_PROCHOT#_EC 2
G

97
98
99
109

Analog Board ID definition,
Please see page 3.

1

1 940@
1 940@

46 VR_HOT#

EC_MUTE#
LAN_PWR_EN#
WLAN_PME#
EC_ENTERING_RW
TP_CLK
TP_DATA

Board ID

R506
100K_0402_5%

R478
R479

ADP_I 40,41

EC_PME#

32,6,7 SPI_WP1#_R

Rb

TP_CLK
TP_DATA

SPI Device Interface

Follow KB930 checking List

AD_BID0

+5VS

R588

2 100K_0402_5%

BATT_TEMP 39,40

KB932&9012 Co-Layout Item

Ra

4.7K_0402_5%
4.7K_0402_5%

1 100P_0402_50V8J ECAGND

83
84
85
86
87
88

+3VALW_EC

4

1 9012@ 2
1 9012@ 2

EC_ENTERING_RW

BT_ON# 31
BEEP# 36
USB_EN# 33

SM010030010 200ma 120ohm@100mhz DCR 0.2

R503
100K_0402_5%

R485
R483

R509
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

11
24
35
94
113

1
1

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output

GND/GND
GND/GND
GND/GND
GND/GND
GND0

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

67

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

BT_ON#
BEEP#
USB_EN#
C510 2

PWM Output

2.2K_0804_8P4R_5%
+3VS

EC_VDD/AVCC

CLK_PCI_LPC
PLT_RST#
EC_RST#_R
EC_SCI#
WLAN_ON

21
23
26
27

1

1

7 CLK_PCI_LPC
35,8 PLT_RST#

EC_SMB_DA1
EC_SMB_CK1
EC_SMB_CK2
EC_SMB_DA2

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

2

+3VS

8
7
6
5

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

ECAGND 40

2

RP12
1
2
3
4

1
2
3
4
5
7
8
10

+3VALW_EC
R476

LID_SW#

1

PU at LAN side

KBL_EN#
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

E

DCR 0.2

1

+3VALW_EC

U28

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

35 KBL_EN#
9 EC_KBRST#
35,9 SERIRQ
35,7 LPC_FRAME#
35,7 LPC_AD3
35,7 LPC_AD2
35,7 LPC_AD1
35,7 LPC_AD0

2 100K_0402_5% EC_PME#

@

2

AGND/AGND

1

2

2
DEG@ 0_0402_5%

+3VALW_EC

R484

2

C507
1000P_0402_50V7K

R591

1

2

R236
0_0805_5%

C506
1000P_0402_50V7K

1

32,35 EC_RST#

EC_RST#_R

0.1U_0402_16V4Z

1
@

C505
0.1U_0402_16V4Z

1

1
@

C504
0.1U_0402_16V4Z

1 47K_0402_5%

C509 2

1

C503
0.1U_0402_16V4Z

R480 2

C502
0.1U_0402_16V4Z

1
2

@

D

L31
SM010030010 200ma 120ohm@100mhz
BLM18AG121SN1D_2P
1
2 +EC_VCCA
+EC_VCCA
XEMC@ XEMC@
1
2
2
+EC_VCC
C508
0.1U_0402_16V4Z
2
1
1

69

+3VLP
1

+3VALW_EC

C

+3VALW_EC
R24
0_0805_5%
1
2
@

3

B

+3VALW

9
22
33
96
111
125

A

C501
22P_0402_50V8J
2
1
2 XEMC@ 1
CLK_PCI_LPC
XEMC@ R477
33_0402_5%

Sheet

Thursday, April 11, 2013
E

34

of

52

Rev
1.0

27
28

G1
G2

ON/OFF

2

F3_BTN

3

10
7
8

1
2
3
4
5
6

5
6

EC_ENTERING_RW 34
R586 1 940@
0_0402_5%
R589 1 940@
0_0402_5%

7

EC_IN_RW

8

EC_RST#

2

EC_IN_RW 9
EC_RST# 32,34

GND
GND

F3 + Power BTN --> Reset EC

9

PAD

2

1
2
3
4
5
6

TP_DATA 34
TP_CLK 34

LEFT_BTN#

2
5
6

SW9 BA51NFP@
TJE-532QR5_4P
1

3

RIGHT_BTN#

2

RIGHT_BTN#
LEFT_BTN#

3

1

SW6 BA51NFP@
TJE-532QR5_4P
1

4

SW4 EA50@
TJE-532QR5_4P
1

4

3

RIGHT_BTN#

2

7
8

2

SW5 EA50@
TJE-532QR5_4P
1

4

100g for Press

SP010014M00

2

100g for Press

2

KB BackLight Conn.
+5VS
JBL1

4
3
2
1

+5VS_BL

2

G

BL@
R451
Q44
100K_0402_5% DMG2301U-7_SOT23-3
1
BL@ 2 KBL_EN_R

2
G
Q26
L2N7002LT1G_SOT23-3
@

34 KBL_EN#

G2
G1

6
5

34 PWR_LED

SP01000Z300
D

2

C524
0.1U_0603_25V7K
@

avoid flash issue when
abnormall shutdown

D

PWR_LED# 33

Q17
L2N7002LT1G_SOT23-3

2
G

R535
100K_0402_5%

1

S

LED

PWR_LED#

ACES_50504-0040N-001
CONN@

2
1

1
@
R592
0_0402_5%

4
3
2
1

1

1

3

D

3

+5VALW

S

34 BATT_BLUE_LED#

1

34 BATT_AMB_LED#

BATT_AMB_LED#

3

B
A

2

1
R699

2
51_0402_5%

4

1
R698

2
680_0402_5%

34 PWR_SUSP_LED#

PWR_LED#

1

PWR_SUSP_LED#

3

B

2

1
R700

2
51_0402_5%

A

4

1
R701

2
680_0402_5%

HDD LED

2

+3VS
+3VS

1

MEDIA_LED#

4

ON/OFFBTN#

R534
100K_0402_5%
9012@

51ON#

1
4
@

3

1

D

2
G

2
499_0402_1%

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

LPC_AD3
LPC_AD2
CLK_PCI_TPM
LPC_FRAME#
LPC_AD1
LPC_AD0
LPCPD#_R
SERIRQ

FOX_QT510166-L010-7H
CONN@

8 LPCPD#

SP020011OA0
2012/07/10

Issued Date

Deciphered Date

+3VS

R392

2 TPM@

1

SERIRQ 34,9
R444
1
2
@
0_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LPC_AD3 34,7
LPC_AD2 34,7
CLK_PCI_TPM 7
LPC_FRAME# 34,7
LPC_AD1 34,7
LPC_AD0 34,7

10K_0402_5%

12/9 modify pin define

S Q39
L2N7002LT1G_SOT23-3
940@

3

2
R624
10K_0402_5%
940@

1
R702

JTPM1

1
3
5
7
9
11
13
15

CLKRUN#
PLT_RST#

+3VALW
+3VS
EC_ON

2

LTST-C191KFKT-2CA_ORANGE

51ON# 39

1

2

34,42 EC_ON

A

MC74VHC1G08DFT2G_SC70-5

8 CLKRUN#
34,8 PLT_RST#

BAV70W_SOT323-3

SW3
TJE-532QR5_4P
1
3

PCH_SATALED# 6

TPM Board

ON/OFF 34

1
3

1

1

1

2

A

LED8

1

EC_WLAN_LED#

34 EC_WLAN_LED#

5IN1_LED# 29

+3VLP

R522
100K_0402_5%
940@
D24

3

+3VS

2

2

+3VALW_EC

U39
2
B

Y

LTST-C191TBKT-CA_BLUE

ON/OFF BTN

P

A

LTST-C295TBKF-CA_AMBER-BLUE

For BCM57786X
R632
10K_0402_5%

G

5

+3VS

6
5

+3VALW

LED6

BATT_BLUE_LED#

LTST-C295TBKF-CA_AMBER-BLUE
LED7

27
28

G1
G2

R740
LED4
51_0402_5%
1
2 2

TOP

4

+5VS
C663
9012@
0.1U_0402_16V4Z
1
2

ACES_88514-00601-071
CONN@

SLG4N059VTR_TDFN8_2X2

SP01000IJ00

Test Only

3
4

E-T_6905-E26N-01R
CONN@

4

2

SW8 BA51FP@
TJE-532QR5_4P
1

To TP/B Conn.

EC_ENT_RW

BTN_B

2

KSI0
F3_BTN
ON/OFF

GND

BTN_A

4

2

4

ON/OFF

JTP2

PWR_BTN#

S

3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

KSO5

1

LEFT_BTN#

+3VALW_EC
C523
940@
0.1U_0603_25V7K
U44
940@
2
1
1
VDD

KB Conn.
JKB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2Y1
2Y0
2S

GND
PAD

2
5
4

NX3L4684TK_MO-229-10_3X3
940@

SP01000IJ00

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5_SW
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0_SW
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1Z
2Z

6
11

E-T_6905-E26N-01R
CONN@

2

1Y1
1Y0
1S

1

3

RIGHT_BTN#

5
6

3
9

KSO5_SW
KSI0_SW

KSI0
KSO5

SW7 BA51FP@
TJE-532QR5_4P
1

5
6

+3VALW_EC
C522 940@
0.1U_0603_25V7K
U41
2
1
1
VCC

0_0402_5%
0_0402_5%

3

5
6

1 9012@ 2
1 9012@ 2

R577
R585

LEFT_BTN#
XEMC@ C551
100P_0402_50V8J

KSI0_SW
KSO5_SW

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

TP_CLK
TP_DATA

KSO[0..17] 32,34

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

E

KSI[0..7] 32,34

KSO[0..17]

3

1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5_SW
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0_SW
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSI[0..7]

D

XEMC@
C553
100P_0402_50V8J

KB Conn.
JKB1

C

5
6

B

5
6

A

2013/07/10

Title

KB & TP & TPM Connector & LED

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

32,33 ON/OFFBTN#

Date:

A

B

C

D

Tuesday, March 26, 2013

Sheet
E

35

of

52

Rev
1.0

4

A

B

C

D

E

Int. Speaker Conn.
+VDDA

1

1

JUMP_43X118
@

40mil
4.75V

GND

HD Audio Codec

18

21
19
20
35

1

37
29

10mil
30

3

+INTMIC_VREFO

GND

C583 1
R546 2

68mA 600mA

35mA

SPK_OUT_L+

2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1 20K_0402_1%

10mil31
10mil27
39
7
15

HP_PLUG#_1
MIC2JD_1

R545
R549

GND

2
2

39.2K_0402_1%
20K_0402_1%

@

1
1

C575 1

2 2.2U_0402_6.3V6M

CPVEE

SENSE_A

34

10mil13
14

MIC2JD

48

MIC2_R

SPK_OUT_L-

SPKL-

LINE1_L

SPK_OUT_R+

LINE1_R

45

SPKR+

44

SPK_OUT_RMIC1_L
HPOUT_L

SPKR-

32

MIC1_R
HPOUT_R

HP_LEFT

CBN
CBP

SDATA_OUT

MIC2_VREFO

SYNC
RESETB

MIC1_VREFO_R
BCLK

33
8

10

6

GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
JDREF

CPVEE

PCBEEP

SENSE A
SENSE B

MONO_OUT
AVSS2
VREF

GNDA

GND

1
2

1

15mil

47

12

2

MONO_IN

16
38
28

1

BEEP#_R

R529
47K_0402_5%
1
2
@

1

R530
47K_0402_5%
1
2

CODEC_VREF
1
@

2

1

2

1
BEEP# 34

2

C555
1U_0402_6.3V6K

10mil
25

INT_MIC_R

EC_MUTE# 34

1

2

GNDA Place next pin27

2

XEMC@

1
L51
0_0603_5%
1 XEMC@ 2

15mil

JMIC1

1
2

INT_MIC_R_1

C550
XEMC@
220P_0402_50V7K

3
4

1
2
G1
G2
ACES_88266-02001
CONN@

GND

PCH_SPKR 9

100P_0402_50V8J
C556

J12
JUMP_43X39
1
2
2
@ 1

Int. MIC

R417
10K_0402_5%

4.7K_0402_5%
R531

GND

J11
JUMP_43X39
1
2
2
@ 1

GND

C578
10U_0603_6.3V6M

4

3

+INTMIC_VREFO

XEMC@
2 C573
22P_0402_50V8J

2

GND

GND
J14
JUMP_43X39
1
2
2
@ 1

6
HDA_RST_AUDIO# 6

@

AVSS1

HDA_SDIN0 6

3

SPDIFO
DVSS

GND

HDA_BITCLK_AUDIO 6

LDO1_CAP

ALC3225-CG_MQFN48_6X6

J7
JUMP_43X39
1
2
2
@ 1

HDA_SYNC_AUDIO
HDA_RST_AUDIO#

1 XEMC@ 2
1
R548 0_0402_5%

LDO3_CAP

GNDA

HDA_SDOUT_AUDIO 6

MIC1_VREFO_L

LDO2_CAP

2

COM_MIC

HP_RIGHT

2
HDA_SDIN0_AUDIO 1 R547
33_0402_5%

5

11

GNDA

D1
AZ5125-02S.R7G_SOT23-3
EMC@

R543
22K_0402_5%

2

GNDA

C577
2.2U_0402_6.3V6M

49

43

C576
0.1U_0402_16V4Z

4

SPKL+

MIC2_L

PD#

Place near
codec

42

R539
2.2K_0402_5%

DC230009K00

1

DVDD

9

1

36

46

41

LINE2_R

R542
22K_0402_5%
1
2

GNDA

SDATA_IN

C570
2.2U_0402_6.3V6M

+MIC2_VREFO

C574 1

40

3

17

LINE2_L

Q28 @
LBSS138LT1G_SOT-23-3
2
MIC2JD
G
1
C571
10U_0603_6.3V6M

DVDD_IO

23

22

GNDA

D

GND Place near Pin1, 9

CPVDD

24

PVDD2

LINE2_C_L
4.7U_0603_6.3V6K
2
LINE2_C_R
4.7U_0603_6.3V6K
2
MIC2_C_L
4.7U_0603_6.3V6K
2
MIC2_C_R
4.7U_0603_6.3V6K

PVDD1

2

26

U34

HP_PLUG#

MIC2JD_1

10U_0603_6.3V6M
2

2
0.1U_0402_16V4Z

COM_MIC

0_0603_5%

1
C564

7
SINGA_2SJ3053-100111F
CONN@

+MIC2_VREFO
+3VS

S

GNDA

C584 1

2

@

6

2

2

C562
@

2
0.1U_0402_16V4Z

2

1
C636

1

C561

GNDA

1
@ C582

1

L52

1

20mil

0.1U_0402_16V4Z
1

1
INT_MIC
C770 1
1K_0402_5%
2
C769 1
1000P_0402_50V7K
C568 1
1 COM_MIC_R
1K_0402_5%
C569 1

GNDA

2
5

1

2
R540

1

HPOUT_R_2

2

GNDA

COM_MIC

HPOUT_L_2

1 XEMC@ 2 0_0603_5%

20mil
+3VS_DVDD 0.1U_0402_16V4Z

2

Combo MIC

2
R726
C62 1
EMC@

L36
1 XEMC@ 2 0_0603_5%

2 60.4_0603_1% HPOUT_R_1

2

GNDA

AVDD2

INT_MIC_R

2 60.4_0603_1% HPOUT_L_1

HP_RIGHT R237 1

GNDA
HP_PLUG#

Place near Pin25, 38

Internal MIC

HP_LEFT R238 1

2

2

JHP1

4

L38

1

1

Place near Pin46

AVDD1

1
2

0_0603_5%

1

Headphone Out

GNDA
C445
XEMC@
COM_MIC
330P_0402_50V7K
1

2

+3VS_VDDA

0.1U_0402_16V4Z
1
C604

C567
10U_0603_6.3V6M

+VDDA
2

2

C444
XEMC@
330P_0402_50V7K

2

3

+AVDD1_HDA
@

HP_PLUG#

GND

Place near Pin40

1

2
G
S

2

SM010030010 200ma 120ohm@100mhz DCR 0.2

L54

GND

1

@

2

2

C605
10U_0603_6.3V6M

0_0603_5%

GND

D
Q31
L2N7002LT1G_SOT23-3

0.1U_0402_16V4Z
1
C559

GNDA

2

@

SP02000K200

1

3

1
2

C608
10U_0603_6.3V6M

0.1U_0402_16V4Z
1
C558

Place near Pin41

1

L55

5
6

D37
AZ5125-02S.R7G_SOT23-3
XEMC@

1
+PVDD_HDA

40mil
1
L33 2
HCB2012KF-221T30_0805

G1
G2

ACES_88266-04001
GND
CONN@

2

SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04

1
2
3
4

R523
100K_0402_5%

HP_PLUG#_1

+3VS

1
2
3
4

SPK_R+
SPK_RSPK_L+
SPK_L-

D27
AZ5125-02S.R7G_SOT23-3
XEMC@

1

(output = 300 mA)

GND

+VDDA

JSPK1

40mil

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

+VDDA

Reserved for ESD

1

XEMC@ 2
XEMC@ 2
XEMC@ 2
XEMC@ 2

2

0.1U_0402_16V4Z
EMC@ 2

1
1
1
1

3

C554

2

R527
R528
R532
R533

3

40mil

SPKR+
SPKRSPKL+
SPKL-

2

J6

3

+5VS

SP020008Y00

GNDA

GNDA
4

GNDA

GNDA
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

HD Audio Codec ALC3225

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, March 26, 2013
E

36

of

52

Rev
1.0

FAN1 Conn

1

1

1

1

1

1

1

1

@

@

@

@

@

JFAN1
1
2
3

34 FAN_SPEED1
C630
1000P_0402_50V7K
XEMC@

1

1

1

@

@

@

@

@

@

1
2 GND
3 GND

1

@

FD3

FD4

1

FIDUCIAL_C40M80

@

@

FIDUCIAL_C40M80

H27
H_3P7

1

1
2

40mil
+VCC_FAN1

@

@

4
5
H22
H_2P5N

ACES_88231-03041
CONN@

SP020020710

H23
H_2P5X3P5N

@

@

1

2

@

H21
H_3P0

@ C631
1000P_0402_50V7K
1
2

R516
10K_0402_5%

@

1

C627
4.7U_0603_10V6K
1
2

+3VS

1

@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

C626
0.1U_0402_16V4Z
@

2

@

H13
H14
H15
H16
H20
H24
H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0

AP2113AMTR-G1_SO8

1

@

FD2

1

R515
0_0402_5%

GND
GND
GND
GND

1

1

EN
VIN
VOUT
VSET

1

34 EN_DFAN1

+VCC_FAN1
2
@

8
7
6
5

1

U31
1
2
3
4

FD1

1

H3
H4
H5
H6
H9
H10
H11
H12
H17
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1

C632
4.7U_0603_10V6K
1
2

1

+5VS

1

+3VS

+3VS

2

R518
10K_0402_5%
GSEN@
U2

15,16,7 D_CK_SCLK
15,16,7 D_CK_SDATA
+3VS

R519 1
@
2 10K_0402_5%
R520 1 GSEN@ 2 10K_0402_5%

Vdd_IO

8
4
6
7

CS
SCLSPC
SDA/SDI/SDO
SDO/SA0

16
15
13

INT1
INT2

ADC1
ADC2
ADC3

2
3

Vdd

RES

NC
NC

GND
GND

1

C633 1

14

C628 1

11
9

G_SEN_INT

GSEN@
2 10U_0603_6.3V6M
GSEN@
2 0.1U_0402_16V4Z

G_SEN_INT 8

10
5
12

LIS3DHTR_LGA16_3X3
GSEN@

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

FAN & Screw Hole & G-Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, March 26, 2013

Sheet

37

of

52

Rev
1.0

A

B

C

D

E

Normall Platform (Not support M-STATE and Deep Sleep)
+5VALW TO +5VS
+5VALW

R553 1 35V@
100K_0402_5%

2

2
1

5
1

2

47K_0402_5%
2 R927
1
C980
1
2
0.1U_0402_16V4Z
2
1
@
R926
C979
0_0402_5%
1
2
EMC@
0.1U_0402_16V4Z
Reserved for ESD

SUSP#

+5VS_R

5VS_GATE

2

SUSP

2

R551
470_0603_5%
35V@

3

4

10mil

2

6

+VSB

35V@

C592
0.1U_0603_25V7K
35V@

1
2

+3VALW

1
35V@

SUSP

Q30B
DMN66D0LDW-7_SOT363-6
35V@

4

20mil

2

C588
1U_0402_10V6K

2

1
35V@

U11

1

C587
4.7U_0603_10V6K

1

C586
4.7U_0603_10V6K

C585
4.7U_0603_10V6K

1

+5VS
U33
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

3

3VS_ON

6
7

+5VALW

CT2

VIN2
VIN2

VOUT2
VOUT2

2

1

1

2

2

+3VS

JUMP_43X118
1

10

330P_0402_50V7K
C967
@ J37
1
+5VS_OUT
1
2

9
8
15

GPAD

Reserved

2

C976
1 330P_0402_50V7K

1

11

GND

ON2

+3VS_OUT

12

CT1

VBIAS

5

5VS_ON

14
13

VOUT1
VOUT1

ON1

4

+5VALW

@ J36

VIN1
VIN1

2

+5VS

JUMP_43X118

TPS22966DPUR_SON14_2X3

1

Q30A
DMN66D0LDW-7_SOT363-6
35V@

+5VALW
+1.05VS_VTT

+1.8VS_6511

2

3

3

3

+1.05VS_VTT

1

SYSON#

1
2
C93
22U_0805_6.3V6M
EMC@

2
Q40A
DMN66D0LDW-7_SOT363-6
@

3
SYSON#

5
SYSON
Q40B
DMN66D0LDW-7_SOT363-6
@

SYSON 34,43

3

+3VSDGPU

2

A

2
1

IN1
IN2

OUT

2

4

U38
MC74VHC1G08DFT2G_SC70-5
VGA@

Q41A
DMN66D0LDW-7_SOT363-6
@

1

R571
47_0603_5%
@

1
+VGA_CORE_R

+1.5VSDGPU_R

5 VGA_ON#
Q41B
DMN66D0LDW-7_SOT363-6
@

3

+0.95VSDGPU_R

VGA_ON# 2

2

2

2

R570
47_0603_5%
@

VGA_ON# 2
Q45A
DMN66D0LDW-7_SOT363-6
@

4

1

2 VGA_ON#
Q55A
DMN66D0LDW-7_SOT363-6
@

5 VGA_ON#
Q45B
DMN66D0LDW-7_SOT363-6
@

VGA_ON_R 47

Compal Electronics, Inc.

Compal Secret Data

Security Classification

3

C63 VGA@
0.1U_0402_16V7K

R77 1 VGA@
20K_0402_1%

GND

1

8,9 VGA_ON
+3VSDGPU

VCC

5

VGA_ON 5
Q55B
DMN66D0LDW-7_SOT363-6
@

4

+3VS
4

+1.8VSDGPU_R

6

+3VSDGPU_R

3

VGA_ON#

R575
47_0603_5%
@

R557
47_0603_5%
@

6

G5243T11U_SOT23-5

1

R574
470_0603_5%
@

+1.5VSDGPU

1

R556
100K_0402_5%
@

1

C621
VGA@
1 4.7U_0603_6.3V6K

3

+VGA_CORE

3

EN

+1.8VSDGPU +0.95VSDGPU

4

2

2

IN

+3VSDGPU

2

GND

+5VALW

1

IN

6

100mil(1.5A)

2

1

1

4
2

OUT

2

5

VGA@

1

U12

1

+3VS

1

C92
10U_0603_6.3V6M

1

C39
C64
EMC@
EMC@
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M

+3VS to +3VSDGPU for GPU

1

1

1

R554
100K_0402_5%
@

4

EMC@

+CPU_CORE

S

6

+3VALW_PCH

2

2
6511_PWR_EN# 27
G
Q38
L2N7002LT1G_SOT23-3
@

+5VALW

+1.35V_R

+5VS

+1.8VS_6511_R
D

2
SUSP
G
Q37
L2N7002LT1G_SOT23-3
@

S

1

For ESD

3

1
+1.05VS_VTT_R

+1.35V

Q32A
DMN66D0LDW-7_SOT363-6
35V@

1

2

2

2

1

1
1
3

2

1

S

S
Q29
L2N7002LT1G_SOT23-3

R568
470_0603_5%
@

D

2
SUSP
G
Q36
L2N7002LT1G_SOT23-3
@

R573
470_0603_5%
@

3VS_GATE 11

C620
4.7U_0603_6.3V6K
VGA@

+0.675VS_R
D

D

2

3

2

5

Q32B
DMN66D0LDW-7_SOT363-6
35V@

SUSP

R567
470_0603_5%
@

1

SUSP

C598
0.1U_0603_25V7K
35V@

@
2
G

R555
10K_0402_5%
@

2
1

34,41,43,44,45 SUSP#

+3VS_R

3VS_GATE

R559
150K_0402_1%

1
330P_0402_50V7K

2

35V@ 1

2

R558
470_0603_5%
35V@

6 1

4

10mil

2

+VSB

1

1
35V@

1

20mil

35V@

C19 2
XEMC@
Reserved for ESD

R566
470_0603_5%
@

4

1

2

C597
1U_0402_6.3V6K

2
35V@

SUSP

43 SUSP
C596
4.7U_0603_6.3V6K

1

U35
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

C595
4.7U_0603_6.3V6K

2

C594
4.7U_0603_6.3V6K

2

R552
100K_0402_5%
@

+3VS

2

+3VALW TO +3VS
+3VALW

1

2

+0.675VS

2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC Interface

V5WE2 M/B LA-9531P Schematic

Date:

B

C

D

Sheet

Tuesday, March 26, 2013
E

38

of

52

Rev
1.0

4

A

B

C

D

+5VS

VIN

1

1

@ PR102
47K_0402_1%
2

8
-

3

BATT_TEMP 34,40

2

1

@ PR104
1.5M_0402_5%
@ PC106
100P_0402_50V8J

@ PR101
100K_0402_1%

1

2

2

2

@ PD102
LL4148_LL34-2

+

O

1

1

S

1

@ PU102A
LM393DR_SO8

1

1

2

2

6

G

P

@ PC105
0.022U_0402_16V7K
2
1

D
@ PQ101A
DMN66D0LDW-7_SOT363-6

@ PR103
10K_0402_1%

G

34,4,40 H_PROCHOT#

4

EMI@ PC104
1000P_0603_50V7K

2

2

EMI@ PC102
100P_0603_50V8

1

+3VALW

1
ESD@ PC101
0.1U_0603_25V7K

2

1

DC_IN_S1

2

1
2
3
4
GND
GND

1

EMI@ PL101
HCB2012KF-121T50_0805
1
2

1

CONN@ PJP101
ACES_50305-00441-001_4P

@ PR106
47K_0402_1%

3

@ PR108
68_1206_5%

-

5
6

1

ACIN 34,41,8

2

2

@ PR107
1.5M_0402_5%

@ PR109
68_1206_5%

1

VS

3

35 51ON#

2

3

@ PR105
0_0402_5%
1
2

+3VLP

-

@ PC109
0.1U_0603_25V7K

2

930@ PC108
0.22U_0603_25V7K

2

930@ PR111
22K_0402_1%
1
2

2

930@ PR110
100K_0402_1%

1

1

1

3

2

930@ PQ102
TP0610K-T1-E3_SOT23-3

+

O
4

4

1

JUMP_43X39

N1

@ PD103
LL4148_LL34-2

1

2

S

7

2

1

2

1

BATT+

@ PJ101
1

5
1

2

@ PQ101B
DMN66D0LDW-7_SOT363-6

@ PD101
LL4148_LL34-2
930@ PD104
LL4148_LL34-2
2
1

G

8

@ PC107
0.022U_0402_16V7K
2
1

D

2

@ PU102B
LM393DR_SO8

P

VIN

G

H_PROCHOT#

2

2

PBJ101 @
2

+
1

PR113
560_0603_5%
1
2

PR112
560_0603_5%
1
2

+CHGRTC

+RTCBATT

ML1220T13RE
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

DCIN
V5WE2 M/B LA-9531P Schematic

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Tuesday, March 26, 2013
D

Sheet

39

of

52

Rev
0.1

A

B

C

D

+3VLP

1

1
2

1

1

1

@ PR230
10K_0402_1%

1

BATT_TEMP 34,39

@ PU204
1

@ PR231
100K_0402_1%

EC_SMB_CK1 34,41

2
2

EC_SMB_DA1 34,41

MAINPWON

3
4

8

VCC TMSNS1

2

7

GND RHYST1

6

OT1 TMSNS2

1
1

2

2

@ PR229
10K_0402_1%
2

PR203
1K_0402_1%

PR208
1K_0402_1%
1
2

2

PR201
100_0402_1%

@ PC209
0.1U_0603_25V7K

EMI@ PC202
1000P_0402_50V7K

2

PR202
100_0402_1%

+3VLP

2

1

2
1
PR206
6.49K_0402_1%

BATT+ <45,47>

1

EMI@ PL201
HCB2012KF-121T50_0805
1
2

1

1

CONN@ PJP201
SUYIN_200275GR008G13GZR
10
GND 9
GND 8
BATT_S1
8 7
7 6
BI
6 5
TH
5 4
EC_SMCK
4 3
EC_SMDA
3 2
2 1
1

@ PR232
47K_0402_1%

5

OT2 RHYST2

@ PH202
100K_0402_1%_TSM0B104F4251RZ
2

G718TM1U_SOT23-8

2

2

For KB9012
OTP

@ PQ202
TP0610K-T1-E3_SOT23-3

1.2V, Active

65W

84W,1.2V

56W,1.2V

56℃

2.255V, Recovery

90W

117W,1.2V

77W,1.2V

PH201 under CPU botten side :
CPU thermal protection at 92 degree C ( shutdown )
Recovery at 56 degree C
+3VLP

120W

3

34,42 MAINPWON

1

D

S

G
3

S

3

MAINPWON

2

1

@ PQ204
2N7002KW_SOT323-3

@ PR221
1_0402_1%

2

4

8

VCC TMSNS1

7

GND RHYST1

6

~OT1TMSNS2

1

PH201
100K_0402_1%_TSM0B104F4251RZ
1

2

2

@
PR222
10.5K_0402_1%

B value:4250K±1%

+VSB

PR204
127K_0402_1%
1
2

H_PROCHOT#_EC 34
65W@ PR225
78.7K_0402_1%

90W@ PR225
53.6K_0402_1%

2

1

+VSBP

VCIN1_PROCHOT 34

2

@
PR222
16.2K_0402_1%

G718TM1U_SOT23-8

@ PJ201

1

1

VCIN0_PH 34

2
1
@ PR220
9.53K_0402_1%

5

~OT2 RHYST2

90W@ PR218
78.7K_0402_1%

1

2

2

2

PU201

2

@
1

65W@ PR218
23.2K_0402_1%

2

1

@ PR217
100K_0402_1%

PR228
12.4K_0402_1%

1

3

1

@ PR214
21K_0402_1%

2

1
2

1
1

34,39,4 H_PROCHOT#

@ PQ203
2N7002KW_SOT323-3

2

@ PC208
1U_0402_6.3V6K

@ PC207
0.1U_0603_25V7K

@ PR216
100K_0402_1%

D

2
G

+EC_VCCA
ADP_I 34,41

1
2

42 SPOK

Recovery

@

@ PR213
100K_0402_1%
@ PR219
0_0402_5%
1
2

Active

92℃

1

1
2

2

@

+VSBP
PC206
0.1U_0603_25V7K

VL

2

@ PR212
22K_0402_1%
2
1

1

2

1

1
@ PR211
100K_0402_1%

34 EC_SPOK
3

PC205
0.22U_0603_25V7K

3

B+

For KB9012
sense 20mΩ

1

PR227
1_0402_1%

@

@
2

2

For 65W adapter==>action 84W , Recovery 56W
For 90W adapter==>action 117W , Recovery 77W

4

PR226
0_0402_5%

1

2

JUMP_43X39

4

34 ECAGND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

Tuesday, March 26, 2013
D

Sheet

40

of

52

A

B

C

D

1

D

3

for reverse input protection

S

2
G

SRN

1

2

SRN 1

11

1

PR322
422K_0402_1%

L-->H
H-->L

1

PR305
1_0402_1%

1

PC308
0.01U_0402_50V7K

2

1

PC318
10U_0603_25V6M

2

1

PC315
10U_0603_25V6M

2

1 CSON1

PC317
0.1U_0402_25V6

Typ
18.006V
17.593V

Max.
18.504V
18.237V

Close EC

Typ
Max.
4.006A 4.108A

ADP_I 34,40
@ PC325
0.1U_0402_25V6

4

2

3

S

Min.
3.906A

EC_SMB_DA1 34,40

1

2

1

PC324
100P_0402_50V8J

4

Min.
17.520V
16.967V

ILIM and external DPM

EC_SMB_CK1 34,40

2

3

D

PC326
2200P_0402_50V7K
2
1

PQ308
2N7002KW_SOT323-3
2
G

2

Vin Detector

PR324
64.9K_0402_1%
@ PR325
0_0402_5%
1
2

1 CSOP1

+3VALW

2
1 2
34,38,43,44,45 SUSP#

2

1

34 FSTCHG

BATT+

3

3

PR317
316K_0402_1%
2
1

ACDET
PQ307
PDTC115EU_SOT323-3

PR323
100K_0402_1%
1
2

2

1

2

1

5

2 CSON1
PR315
6.8_0603_5%
BQ24735_BATDRV

3
2
1

PR314
10_0603_5%
2 CSOP1

2

12

2

2
1
PR321
2M_0402_1%

SRP 1

PC322
0.01U_0402_25V7K

VIN

PR318
2M_0402_1%

13

2

ILIM
1

1

ACDET

PR320
100K_0402_1%

6

34,39,8 ACIN

3

BATDRV
SCL

ACOK

9

5

ACDRV

4

DL_CHG

14

10

ACOK

SRP

SDA

2
PR316
100K_0402_1%

CMSRC

PL302
PR312
10UH_FDSD0630-H-100M-P3_3.8A_20%
0.01_1206_1%
2
4
BQ24735_LX 1
CHG 1
PQ306
SIS412DN-T1-GE3_POWERPAK8-5

15

PC321
0.1U_0603_25V7K

GND

8

1

2

PC314
0.1U_0402_25V6

2

@EMI@ PC316 @EMI@ PR313
680P_0402_50V7K 4.7_1206_5%

3
2
1

2

ACP

IOUT

4

PQ305
SIS412DN-T1-GE3_POWERPAK8-5

PC313
1U_0603_25V6K

LODRV

7

BQ24735_ACDRV

2
5

1
PR310
0_0603_5%
1
BQ24735_BST 2

1

16

17
BTST

18

DH_CHG

BQ24735_LX

ACN

ACDET

+3VLP

3

PR306
4.12K_0603_1%

PD303
RB751V-40_SOD323-2

BQ24735RGRR_QFN20_3P5X3P5
BQ24735_CMSRC

@

2

4

DH_CHG-1

1

2

PAD

PR311
0_0603_5%
2
DH_CHG 1

REGN

1

HIDRV

21

VCC

PU301

19

2

PC312
1U_0603_25V6K

PHASE

1

4

1

2
2

3
1
1
2

BQ24735_ACP

BQ24735_ACN

2

BQ24735_BATDRV 1

1

PC310
0.047U_0402_25V7K
1
2
PR309
10_1206_1%

1

1
2

PD302
BAS40CW_SOT323-3

EMI@ PC307
2200P_0402_50V7K

1
VIN

@EMI@ PC305
0.1U_0402_25V6
2
1

4x4x2

2

3

1

2

EMI@ PL301
1.2UH_PNS40201R2YAF_3A_30%
1
2
PC304
10U_0603_25V6M
2
1

4

2

1

PC306
0.1U_0402_25V6
1
2

PR308
4.12K_0603_1%

1

PR307
4.12K_0603_1%
2
1

2

CHG_B+

PR303
0.02_1206_1%

2

1

PC302
0.1U_0402_25V6

2

1

4

2

@

B+

PC303
10U_0603_25V6M

P2
PQ303
SIS412DN-T1-GE3_POWERPAK8-5
1
2
3
5

1
2
3

5
PC301
2200P_0402_50V7K
2
1

100ppm

P1

PQ302
AON6414AL_DFN8-5

PR304
1_0402_1%

VIN

PR301
3M_0402_5%

PC311
0.1U_0603_25V7K

PR302
1M_0402_5%

1

PQ304
SIS412DN-T1-GE3_POWERPAK8-5
1
2
5
3

2

20

1

PC309
0.1U_0402_25V6

2

4

1

PQ301
2N7002KW_SOT323-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHARGER

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

Tuesday, March 26, 2013
D

Sheet

41

of

52

Rev
0.1

5

4

3

2

1

D

D

@ PR415
0_0402_5%
1
2

LDO

4
5

+3VLP
PC422
4.7U_0603_6.3V6K

1

2

SY8208BQNC_QFN10_3X3

PR416
100K_0402_1%

40 SPOK

1
2

1

1K_0402_1%
2

2

+3VALWP

1UH_FDSD0630-H-1R0M-P3_11A_20%

@EMI@ PC423
2

3.3V LDO 150mA~300mA

2

C

PR414
1

PL402

1

LX_3V

0.01U_0402_25V7K
1
2
FB-1_3V

B+

PC413
22U_0805_6.3V6M

PG

10

PC428

PR401
499K_0402_1%
1
2

ENLDO_3V5V

PC414
22U_0805_6.3V6M
2
1

OUT

PR404
PC401
2BST-1_3V
1
2
0_0603_5%
0.1U_0603_25V7K

PC416
22U_0805_6.3V6M
2
1

2

+3VALWP

GND

1
BST_3V

@ PR413
0_0402_5%
1
2

1

9

6

3V5V_EN

2

LX

@

FB_3V

PC411
22U_0805_6.3V6M
2
1

BS

3

PR410
1K_0402_1%
1
2

2

EN2

3V_EN_R

680P_0603_50V7K 4.7_1206_5%

IN

1

@EMI@ PR409
13V_SN
2
1

PC405
10U_0805_25V6K
2
1

PC408
10U_0805_25V6K
2
1

EMI@ PC410
2200P_0402_50V7K
2
1

@EMI@ PC403
0.1U_0402_25V6
2
1

EN1

1

8

3V_VIN

IN

@ PC425
4.7U_0603_6.3V6K
PR405
150K_0402_1%
2
1

EN1 and EN2 dont't floating

PU401
7

EMI@ PL401
HCB2012KF-121T50_0805
1
2

@ PC426
4.7U_0603_6.3V6K

B+

C

Vout is 3.234V~3.366V
TDC=8A
@ PJ401
1

+3VALWP

1

2

2

+3VALW

1ENLDO_3V5V

JUMP_43X118

@ PR411
0_0402_5%

BS

3V5V_EN

3

FB_5V

6

PC427
6800P_0402_25V7K
1
2 FB-1_5V
PR403 0_0603_5% PC404 0.1U_0603_25V7K
1
2BST-1_5V 1
2
BST_5V

PR412
1K_0402_1%
1
2
B

PL403

7

VL

SY8208CQNC_QFN10_3X3

2

+5VALWP

1UH_FDSD0630-H-1R0M-P3_11A_20%
PC412
22U_0805_6.3V6M

LDO

1

LX_5V

PC415
22U_0805_6.3V6M
2
1

PG

10
4

PC418
22U_0805_6.3V6M
2
1

OUT

PC417
22U_0805_6.3V6M
2
1

LX

VCC

1

2

GND

2

5

680P_0603_50V7K 4.7_1206_5%

9

@ PJ402

+5VALWP

1

1

2

2

+5VALW

JUMP_43X118

Vout is 4.998V~5.202V

5V LDO 150mA~300mA

PR407
2.2K_0402_5%
1
2
1

1

PC421
4.7U_0603_6.3V6K

PC420
4.7U_0603_6.3V6K

1

34,40 MAINPWON

EN2

SPOK

2

34,35 EC_ON

EN1

1

VCC_3.3V

IN

2

@

@EMI@ PC402
0.1U_0402_25V6
2
1

EMI@ PC409
2200P_0402_50V7K
2
1

PC407
10U_0805_25V6K
2
1

B

8

5V_VIN

2

PU402

@EMI@ PC424 @EMI@ PR408
2
15V_SN
2
1

EMI@ PL404
HCB2012KF-121T50_0805
1
2
PC406
10U_0805_25V6K
2
1

B+

TDC=8A

@ PR402
2

0_0402_5%

A

A

1
2

PR406
1M_0402_1%

PC419
4.7U_0603_6.3V6K

2

1

3V5V_EN

2012/07/10

Issued Date

EN1 and EN2 dont't floating
5

Compal Secret Data

Security Classification

@

4

2013/07/10

Deciphered Date

Title

Compal Electronics, Inc.
3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, March 26, 2013
Date:

Rev
0.1

V5WE2 M/B LA-9532P Schematic

3

2

Sheet
1

42

of

52

A

G

3
2
1

PR504
8.45K_0402_1%
2
1

1
2

1

2

1

+

PC506
330U_2.5V_M

Rds=4.2mΩ(Typ)
5.0mΩ(Max)

12
2

11

1

+5VALW

PR505
5.1_0603_5%

PC509
1U_0603_10V6K
2
1

+3VALW

@ PJ504
1

1

+1.35VP

1

2

+1.35V

1

2

2

2

JUMP_43X118

PGOOD_1.35V

@ PJ506
1

+0.675VSP

1

2

1

2

+0.675VS

JUMP_43X79

FB=0.75V
To GND = 1.5V
To VDD = 1.8V

@ PJ511
1

+0.95VSDGPUP

1

2

2

JUMP_43X118

+0.95VSDGPU

2

S

PR510
10K_0402_1%

2

@ PJ505
1

@

PR509
8.06K_0402_1%
2
1

1

@ PC511
0.1U_0402_25V6

1

JUMP_43X118
PC510
1U_0603_10V6K

VGA@ PR532
0_0402_5%
1
2

On

On

Hi

On

On

Lo

Lo

On
Off
(Hi-Z)

Off
Off
Off
(Discharge) (Discharge) (Discharge)

Note: S3 - sleep ; S5 - power off

14

2012/07/10

VGA@ PC538
22U_0805_6.3V6M

VGA@ PC537
22U_0805_6.3V6M
2
1

VGA@ PC536
22U_0805_6.3V6M
2
1

1
2

VGA@ PC535
22U_0805_6.3V6M
2
1

1

@EMI@ PR533
4.7_0402_1%
2
1

VGA@ PR536
100K_0402_1%

2

@EMI@ PC539
680P_0402_50V7K

RT/CLK

1
2

1
2

BOOT

13

FB=0.799V

+0.95VSDGPUP
Ipeak=4.28A ; 1.2Ipeak=5.136A ;Imax=2.996A
F=131904/(PR534^0.9492)=1000KHz, PR534=169KΩ

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

9

VGA@ PC540
22P_0402_50V8J

Hi

Lo

10

+0.95VSDGPUP

VGA@ PR535
19.1K_0402_1%
2
1

Hi

S3

0.675VSP

11

1

S0

PWRGD

SS/TR

PWRPD

COMP

GND

VGA@ PL506
1UH_PCMB063T-1R0MS_12A_20%
1
2

LX_0.95V

2

VTT_REFP

15

PH
VSENSE

GND

5

S5

PH

VGA@ PU504
TPS54618

12

VGA@ PC542
2200P_0402_50V7K

VIN

PH

SNUB_0.95V

17

VIN

6
VGA@ PC541
VGA@ PR537
3300P_0402_50V7K 18K_0402_1%
7
2
1 2
1
VGA@ PR534
169K_0402_1%
8
2
1

2

EN

16
VIN
1

AGND

VGA@ PC534
22U_0805_6.3V6M

1
2

PC533
22U_0805_6.3V6M

2

@

4

S3

VGA@ PC531
0.22U_0603_10V7K
2
1

0.95V_VIN
1

VGA@EMI@ PL505
HCB2012KF-121T50_0805
1
2

3

S4/S5

2

ESD@ PC507
680P_0402_50V7K

PR508
887K_0402_1%
2
1 1.35V_B+

+3VALW

1.35VP

EMI@ PC503
2200P_0402_50V7K

2

1

2

ESD@ PR503
4.7_1206_5%

44,45,47 VGA_PG

STATE

PC502
10U_0805_25V6K

1
13

DCR:8.5mΩ

2

14

+1.35VP

6.6x7.3x3.8 TAI-TECH

1

PQ503
S TR MDU1512RH 1N POWERDFN56-8

5
4

LG_1.35V

PR506
10K_0402_1%
2
1

PGOOD

TON

10

S5

FB

VDD

15

B+

PL501
S COIL 1.5UH 20% TMPB0604M-1R5MN-Z01 11A
1
2

16

UGATE

18

17

PHASE
CS
VDDP

VDDQ

2

1

D

2

2

3

SUSP

@ PC512
0.1U_0402_25V6
1

@ PQ501
2N7002KW_SOT323-3

PQ502
MDV1525URH_PDFN33-8-5

5
3
2
1

JUMP_43X39

1
VLDOIN

BOOT

20

19

RT8207MZQW_WQFN20_3X3

VTTREF

6

1

PGND

@ PR507
0_0402_5%
1
2

34,38 SYSON

38 SUSP

PC508
0.033U_0402_16V7K

GND

@ PR501
680K_0402_1%
1
2

34,38,41,44,45 SUSP#
1

+1.35VP

2

15 DDR_VTT_PG_CTRL

5

VTTSNS

9

4

+VTT_REFP

LGATE

S5_1.35V 8

3

VTTGND

S3

1

PAD

PC504
0.1U_0603_25V7K
1
BST_1.35V-1 2

LX_1.35V

VTT

1

PU501
21

2

@ PR513
0_0402_5%
1
2

PR502
2.2_0603_5%
1
BST_1.35V 2

靠近Output Cap PAD

S3_1.35V 7

2

1

PC501
10U_0805_25V6K

+0.675VSP

PC505
10U_0805_25V6K

120%

2

115%

4

UG_1.35V

2

@

2

PJ503

1

+1.35VP

2012/9/6

OVP=110%

EMI@ PL507
HCB2012KF-121T50_0805
2
1

1.35V_B+

ESD@ PC521
0.1U_0402_25V6

+1.35VP
Ipeak = max{ 0.7*Ibudget, 1st +2nd max loading}
Ipeak = max{ 12.34*0.7 ,
4.2+8.14
}
Ipeak=12.34A ; 1.2Ipeak=14.808A ;Imax=8.638A
1/2Delta I=0.7353A (F=300K Hz)
PR504=(1.2Ipeak-1/2Delta I) *Rds(on)(max)*1.2/9uA=8.45Kohm
choose PR504=8.45Kohm (for safety >1.2Ipeak)
Rds(on)=5.0m ohm(max) ; Rds(on)=4.2m ohm(typical)
Ilimit_min=(8.366K*9uA)/(5.0m*1.2)=15.058A
Ilimit_max=(8.535K*11uA)/(4.2m*1.2)=22.352A
Iocp=Ilimit+1/2Delta I=15.79A~23.09A
Iocp(min)>1.2Ipeak

Deciphered Date

2013/07/10

Title

1.35VP/0.675VSP/0.95VSDGPUP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

A

Tuesday, March 26, 2013

Sheet

43

of

52

2

VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V
Freq=290KHz(typ)

DRVL
TP

470
200
100
39

C

VGA@ PR514
470K_0402_1%

7

+5VALW

6

DL_1.5VSG

11

TPS51212DSCR_SON10_3X3

4

VGA@ PC515
1U_0603_10V6K

2

290
340
380
430

Rds=13.5mΩ(Typ)
16.5mΩ(Max)
VGA@ PR515
11.5K_0402_1%
2
1

1
2

1
2

1
2

1

@ PC518
10U_0603_25V6M

+1.5VSDGPUP

1
+

VGA@EMI@ PR518
4.7_1206_5%

VGA@ PC523
330U_2.5V_M

2
VGA@EMI@ PC522
680P_0402_50V7K

C

1

FB=0.704V

2

VGA@ PL502
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2

2

Resistance(KΩ) Frequency(KHz)

SW_1.5VSG

D

1

V5IN

TST

DH_1.5VSG

2

VFB

9
8

VGA@ PC514
0.1U_0603_25V7K
1
2

1

5

SW

BST_1.5VSG

B+

5

4

DRVH

EN

1

FB_1.5VSG
RF_1.5VSG

TRIP

10

3
2
1

3

VBST

1

2

TRIP_1.5VSG

43,45,47 VGA_PG

PGOOD

3
2
1

VGA@ PR517
2.2_0603_1%
1
2

VGA@ PU502

1

VGA@ PC517
10U_0603_25V6M

4

VGA@ PQ504
SIS412DN-T1-GE3_POWERPAK8-5

5

Cesr= 15m ohm
Ipeak= 4.7A Imax= 3.29A Iocp=5.64A
Iocp= 5.72A~6.43A

VGA@ PR512
56.2K_0402_1%
2
1

VGA@EMI@ PL504
HCB2012KF-121T50_0805
2
1

1.5VSG_B+

VGA@ PQ505
SI7716ADN-T1-GE3_POWERPAK8-5

D

1

@EMI@ PC519
0.1U_0402_25V6

3

VGA@EMI@ PC516
2200P_0402_50V7K

4

2

5

+3VS
1

2

VGA@ PR516
10K_0402_1%

2

@ PC526
1U_0402_6.3V6K

2

+1.5VSDGPU

1

1
2

@

PC524
22U_0805_6.3V6M

1
@ PR522
22K_0402_5%

@ PC527
0.1U_0402_25V6

PC525
22U_0805_6.3V6M

FB_1.5VSP

PR521
22.6K_0402_1%

2

2

FB=0.8V

2

1

PR519
20K_0402_1%

B

+1.5VSP

2

1
1

1

2

@ PJ509

+1.5VSDGPUP

2

+1.5VSP_ON

1

34,38,41,43,45 SUSP#

@ PR523
0_0402_5%
1
2

FB

2

EN
POK

GND

1

8
7

2

PC528
4.7U_0603_6.3V6K

1

PU503
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT

B

PC529
0.022U_0402_16V7K
2
1

Note:Iload(max)=3A

JUMP_43X118
@ PJ510

1

1

2

2

JUMP_43X118

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

@ PJ508

A

1

+1.5VSP

1

2

2

+1.5VS

A

JUMP_43X39

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5VSP/+1.5VSDGPUP
Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, March 26, 2013

Sheet
1

44

of

52

5

4

3

2

1

+1.05VSP Ipeak=5.36A ; Imax=3.752A ; 1.2Ipeak=6.432
Delta I=0.xxxxA=>1/2Delta I=0.xxxxA,F= 800K Hz(typ)

PR603
1K_0402_1%
2
1

D

D

SUSP# 34,38,41,43,44

@ PR607
1M_0402_1%
1
2

B+

PC606
0.1U_0402_25V6
1
2

2

2

1

PC629
22U_0805_6.3V6M

1
2

PC628
22U_0805_6.3V6M

1
2

PC627
22U_0805_6.3V6M

@

@EMI@ PC607
680P_0402_50V7K

2

PC608
4.7U_0603_6.3V6K

1
+3VS

PC601
4.7U_0603_6.3V6K
2
1

2
PR618
10K_0402_1%
2
1

C

@EMI@ PR604
4.7_0805_5%

SY8208DQNC_QFN10_3X3

2

@ PC614
0.1U_0402_25V6

+3VALW

5

1

LDO

7

2

PG

FB_+1.05VSP

+1.05VSP
PC626
22U_0805_6.3V6M

1

2
PR619
1M_0402_1%

4

PL601
0.68UH_PCMC063T-R68MN_15.5A_20%
1
2

1

BYP

SW_+1.05VSP

2

ILMT

BST_+1.05VSP

PC625
22U_0805_6.3V6M

1

3

6
10

1

LX

PR602
PC605
0_0603_5% 0.1U_0603_25V7K
1
2
1
2

2

GND

EN_+1.05VSP

PC624
22U_0805_6.3V6M

BS
9

1

1

EN

1 2

PC623
10U_0805_25V6K
2
1

IN

FB

1
2
@ PR613
10K_0402_1%

+3VS

PC604
10U_0805_25V6K
2
1

@EMI@ PC602
0.1U_0402_25V6
2
1

EMI@ PC603
2200P_0402_50V7K
2
1

PU601
8

VFB=0.6V

@ PJ602
1

+1.05VSP

1

2

2

+1.05VS_VTT

JUMP_43X118
@ PJ603
1
2
1
2

1

11,34 VCCST_PWRGD

C

PR605
100K_0402_1%
2
1
PC609
4700P_0402_25V7K
2
1

JUMP_43X118
PR608
127K_0402_1%

1

2

+3VS

2

@ PC615
1U_0402_6.3V6K

+3VS

Note:Iload(max)=3A
1
2

2
1
1

@

1

VGA@ PR616
15.8K_0402_1%

2

2

@ PR617
22K_0402_5%

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

PC622
22U_0805_6.3V6M

1

2

2

FB_1.8VSDGPU

43,44,47 VGA_PG

2

1
VGA@ PR614
20K_0402_1%

FB=0.8V

1

2

+1.8VSDGPU
VGA@ PC621
22U_0805_6.3V6M

FB

VGA@ PC620
0.022U_0402_16V7K
2
1

EN
POK

2

8
7

GND

VGA@ PC618
4.7U_0603_6.3V6K

PR611
15.8K_0402_1%

@ PR612
22K_0402_5%

VGA@ PU603
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
1

1

PC612
22U_0805_6.3V6M

2

@

B

Note:Iload(max)=3A

2

1

1

1

+1.8VS_6511_ON

@ PC617
1U_0402_6.3V6K

2

@ PC616
0.1U_0402_25V6

1
2

FB_1.8VS_6511

+1.8VS_6511
PC613
22U_0805_6.3V6M

PR609
20K_0402_1%

FB=0.8V

PC611
0.022U_0402_16V7K
2
1

1

2

1

@ PR610
0_0402_5%
1
2

27 6511_PWR_EN

FB

2

EN
POK

2

8
7

GND

PC610
4.7U_0603_6.3V6K

B

1

PU602
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT

A

A

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

+1.05VSP/+1.8VSDGPU/+1.8VS_6511

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, March 26, 2013
1

45

of

52

Rev
0.1

5

4

3

2

1

PC706
68U_25V_M_R0.36

2

1

@EMI@ PC705
0.1U_0402_25V6

1
2

EMI@ PC704
2200P_0402_50V7K

1
2

PC709
10U_0805_25V6K

PR715
2.21K_0402_1%
2
1

EMI@ PC714
EMI@ PR714
680P_0402_50V7K 4.7_1206_5%

1 2
1

PR716
24.9K_0402_1%
1
2
PH702
PR717
10K_0402_1%_TSM0A103F34D1RZ
3.01K_0402_1%
1
2
1
2

Close choke.

B value:3435K

PC711
0.1U_0402_25V6
1
2

C

CSN1
CSP1

3
2

VGATE 11,8
2

VDD

1

2

1

+3VS

@ PR724
0_0402_5%
PC746
1U_0402_6.3V6K

Use X7R is better or far away inductor.

Maximum current: 32A

@ PR725
2K_0402_1%

2

1

PC741
0.1U_0402_25V6

1
PR731
130_0402_1%

1

PR730
75_0402_1%

@

2

2

51622_VREF

2

1
PR729
54.9_0402_1%

+1.05VS_VTT

Close to PWR IC

VR_ALERT# 11

1

VR_SVID_CLK 11
VR_HOT# 34
V5A

1

PC743
PR728
PC744
1500P_0402_50V7K 10K_0402_1% 0.33U_0402_10V6K
2
1 1
2

3

DCR:0.82mΩ±5%

PC712
0.082U_0402_16V7K
1
2

2

4

CSP1-1 2

VR_SVID_DATA 11

2

COMP
PR727
3.48K_0402_1%
2
1

PR734
10K_0402_1%

33

32

31

30

29

28

27

26

25
PR726
10K_0402_1%
2
1

1

2
VDIO

PWM1

5

2

VDD

6

DROOP
PC742
100P_0402_50V8J
2
1

D

1

PGOOD

GFB
VFB

2

CPU_PHASE1
PC740
1U_0603_10V6K

VR_ON 11
SKIP#

1

N/C

2

B+

+CPU_CORE

9

10
F-IMAX

12

11

OCP-I

B-RAMP

14

13
IMON

THERM

O-USR

N/C

8
7

PAD

24

TPS51622RSM_QFN32_4X4~D

PU3

ALERT#

VFB

PWM2

VCLK

23

PWM1
PU701

CSP2

VR_HOT#

GFB

CSN2

GND

0_0402_5%
2
0_0402_5%
2

SKIP#

V5A

PR721
1
PR722
1

VR_ON

CSN1

VREF

11 VCC_SENSE

@

15

16
22
@
11 VSS_SENSE

SLEWA

VBAT
21

+3VS

CSP1

+

PL702
0.22UH_PCMB104T-R22MS_35A_20%
1
4

+5VS

1

PU702
CSD97374CQ4M_SON8_3P5X4P5
5
1 SKIP#
SKIP# 2
6 VIN
BOOT_R VDD 3
PGND1 4
7
BOOT
VSW
8
9 PWM
PGND2

1

2.2_0603_5%
1CPU_BOOT1
0.1U_0603_25V7K
2CPU_BOOT1-1
PWM1

2

PR701
2
PC701
1

COMP

@
C

17

DROOP

CSP1

1

1
EMI@ PC749
1000P_0402_50V7K

F-IMAX

PR713
10K_0402_1%
1
2 VBAT

18
CSN1
PR718 0_0402_5%
2
1
19
PR719 0_0402_5%
1
2
20

EMI@ PL701
HCB2012KF-121T50_0805
2
1

2

B-RAMP

O-USR

@

@

OCP-I

PR712
39K_0402_1%
2
1

CPU_B+

PC703
10U_0805_25V6K

1
2

PR709
PR710
392K_0402_1% 56K_0402_1%
1
2
1
2

@ PR711
10K_0402_1%
1
2 SLEWA

CPU_B+

PC702
10U_0805_25V6K

THERM

PC747
0.1U_0402_25V6
2
1

D

@

PR707
PR704
392K_0402_1% 8.87K_0402_1%
2
1
2
1

Close MOS.
PC748
4700P_0402_25V7K
1
2

2

PR708
10K_0402_1%
2
1

PR705
PR702
150K_0402_1% 100K_0402_1%
2
1
2
1

1

B value:4250K

PR706
PR703
39K_0402_1% 274K_0402_1%
2
1
2
1

51622_VREF
PH705
100K_0402_1%_TSM0B104F4251RZ

2

B

2

1

+5VS

PR732
22_0603_5%
PC745
2.2U_0402_6.3V6M

B

Consider use 0603 for inrush power.

VIN

12V-20V

MAX current

32A

Thermal current

10A

Dynamic current

27A

Over current level

45A

Switching frequency

600KHz

Boot voltage

1.7V

DC Load- line

2m Ohm

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, March 26, 2013
1

46

of

52

Rev
0.1

1

1

0

0

0

0
5

+3VSDGPU

4

2
1
@ PR837
10K_0402_1%

VGA@ PR802
2.2_0603_5%
2
1

BOOT2_VGA

VGA@ PC806
0.22U_0603_10V7K
2
BOOT2_2_VGA 1
UGATE2_VGA

VGA@ PR848
2.2_0603_5%
1
2 UGATE2-1_VGA

VGA@ PL804
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
1
2

3
2
1

+VGA_CORE

1
2

VGA@EMI@ PR805
4.7_1206_5%

VGA@ PR806
3.65K_0402_1%
2
1

V2N_VGA
1

5
4

LGATE2_VGA

2
1
VGA@ PR838
10K_0402_1%

2
1
VGA@ PR840
10K_0402_1%

2
1
VGA@ PR842
10K_0402_1%

2

2
1
@ PR846
10K_0402_1%

1
@ PR844
10K_0402_1%

GPU_VID_1
GPU_VID_2
GPU_VID_3
GPU_VID_4
GPU_VID_5

2

D

PHASE2_VGA

2

2
1
@ PR839
10K_0402_1%

1
@ PR804
0_0402_5%

2
1
@ PR841
10K_0402_1%

2
1
VGA@ PR845
10K_0402_1%

@ PR803
1_0402_1%
1
2
18 GPU_DPRSLPVR

2
1
VGA@ PR843
10K_0402_1%

2

@
PC805
0.1U_0402_25V6

B+

VGA@EMI@ PL803
HCB2012KF-121T50_0805
2
1

1

0

VGA@EMI@ PL801
HCB2012KF-121T50_0805
2
1

DCR: 0.97mΩ±5%

7x7x4

VGA@ PR809
10K_0402_1%
1
2V1N_VGA

VSUM+_VGA

2

0.9V

+VGA_B+

VGA@ PC804
10U_0805_25V6K
2
1

VID0

VGA@ PC803
10U_0805_25V6K
2
1

VID1

VGA@ PR807
10K_0402_1%

VID2

VGA@EMI@ PC802
2200P_0402_50V7K
2
1

VID3

@EMI@ PC801
0.1U_0603_25V7K
2
1

VID4

3
2
1

1

38 VGA_ON_R

VID5

1

1

@ PR801
0_0402_5%
1
2

D

VID6

18
18
18
18
18

GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1

AMD
MARS XT

Default
Voltage

VGA@ PQ804
MDU1511RH_POWERDFN56-8-5

VGA Chipset

2

VGA@ PR808
1_0402_1%

3

VGA@ PQ803
MDU1516URH_POWERDFN56-8-5

4

2

5

VSUM-_VGA
ISEN2_VGA

VGA@EMI@ PC807
680P_0402_50V7K

30
29
28
27
26
25
24
23
22
21

C

@ PR812
0_0402_5%
2
1

@ PR813
0_0402_5%
2
1

+5VS

VGA_CORE
Freq.=400KHz
Imax=27.00A
Ipeak=40.50A
Iocp=49.00A
LL= disable
Cesr= xx mOHM

VGA@ PC810
1U_0603_10V6K

11
12
13
14
15
16
17
18
19
20

2

AGND

VGA@ PU801
ISL62883CHRTZ-T_TQFN40_5X5

2
@ PR817
0_0402_5%
2
1
@ PR819
0_0402_5%
2
1

3
2
1

VGA@ PR836
953_0402_1%
1
2

Layout Note:
Place near Phase1 Choke

1
2

VGA@ PC819
10U_0603_25V6M

VGA@ PC820
10U_0603_25V6M
2
1

+VGA_CORE

7x7x4

2

VGA@ PR833
10K_0402_1%
1
2V2N_VGA

VSUM-_VGA

VSUM+_VGA
VGA@EMI@ PC828
680P_0402_50V7K

1

DCR: 0.97mΩ±5%

VGA@ PR832
1_0402_1%

2

VGA@EMI@ PR829
4.7_1206_5%

VGA@ PR830
3.65K_0402_1%
2
1

2

1

1

V1N_VGA

1

5
4

LGATE1_VGA

B

VGA@ PL802
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
1
2
VGA@ PR831
10K_0402_1%

VGA@ PR826
2.61K_0402_1%
2
1

4

PHASE1_VGA

1

VGA@ PR828
11K_0402_1%
2
1

@ PC824
0.1U_0603_25V7K
2
1

VGA@ PC823
0.22U_0603_16V7K
2
1

2
1

UGATE1-1_VGA

VGA@ PC821
0.22U_0603_10V7K
1
2

2

VGA@ PR835
10_0402_5%
1
2

VGA@ PR824
2.2_0603_5%
2
1 BOOT1_1_VGA

VGA@ PH801
10K_0402_1%_TSM0A103F34D1RZ
2

20 VSS_GPU_SENSE

2

2
1

VGA@ PC826
1000P_0402_50V7K

2

VGA@ PC822
330P_0402_50V7K

@ PC825
330P_0402_50V7K
2
1

1

1

20 VCC_GPU_SENSE

@ PR827
82.5_0402_5%

VSUM+_VGA

@ PC827
0.01U_0402_25V7K

+VGA_CORE

VGA@ PR847
2.2_0603_5%
1
2

UGATE1_VGA

VGA@ PR823
10_0402_5%
1
2

VGA@ PQ801
MDU1516URH_POWERDFN56-8-5

VGA@ PC818
0.22U_0603_25V7K

1
2

VSUM-_VGA

+VGA_B+

+5VS

BOOT1_VGA

B

VGA@ PC817
1U_0603_10V6K
2
1

1

VGA@ PR820
324K_0402_1%

+VGA_B+

VGA@ PR821
1_0402_1%
2
1

ISEN1_VGA

VGA@ PQ802
MDU1511RH_POWERDFN56-8-5

ISEN2_VGA

2

+5VS

5

1
2
VGA@ PR818
3.57K_0402_1%

3
2
1

VGA@ PC812
470P_0402_50V7K

VGA@ PC816
0.22U_0402_10V4Z
2
1

1

41

VGA@ PR816
499_0402_1%
1
2
1

2

VGA@ PC814
150P_0402_50V8J

2

2

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

1

1

@ PC809
33P_0402_50V8J

VGA@ PC813
47P_0402_50V8J
1
2

1

1
2
3
4
5
6
7
8
9
10

43,44,45 VGA_PG
1
2

VGA@ PC815
0.22U_0402_10V4Z

1
2

VGA@ PC811
1000P_0402_50V7K

VGA@ PR815
5.9K_0402_1%
1
2

+3VS

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

VGA@ PR810
100K_0402_1%
VGA@ PR811
47K_0402_1%
2
1

VGA@ PC808
1U_0603_10V6K
1
2

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

C

40
39
38
37
36
35
34
33
32
31

2
1
VGA@ PR814
10K_0402_1%

+3VSDGPU

ISEN1_VGA

VSUM-_VGA

A

VGA@ PC829
0.1U_0402_25V6

2

1

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

+GPU_COREP
Document Number

V5WE2 M/B LA-9531P Schematic
Sheet

Tuesday, March 26, 2013
1

47

of

52

Rev
0.1

4

3

2

PWR Rule
CPU DCLL=1.5m ohm dedign 330uF/9m *0, 22uF *30

1

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

2
1
2

2

1

1
2
1

2
1

D

For BOT side

PC927
22U_0805_6.3V6M

PC926
22U_0805_6.3V6M

PC925
22U_0805_6.3V6M

2

@

PC909
22U_0805_6.3V6M

PC908
22U_0805_6.3V6M

PC907
22U_0805_6.3V6M

@

PC924
22U_0805_6.3V6M

@

PC906
22U_0805_6.3V6M

@

PC923
22U_0805_6.3V6M

PC922
22U_0805_6.3V6M

PC921
22U_0805_6.3V6M

PC920
22U_0805_6.3V6M

@

PC905
22U_0805_6.3V6M

PC904
22U_0805_6.3V6M

D

PC903
22U_0805_6.3V6M

PC902
22U_0805_6.3V6M

1

+CPU_CORE

2

5

+CPU_CORE

2

1

2

For TOP side

C

PC956
22U_0805_6.3V6M

2

1

PC941
22U_0805_6.3V6M

2

1

PC955
22U_0805_6.3V6M

1

2

PC940
22U_0805_6.3V6M

2

2

1

PC954
22U_0805_6.3V6M

1

1

PC939
22U_0805_6.3V6M

2

2

PC953
22U_0805_6.3V6M

1

1

PC938
22U_0805_6.3V6M

2

2

PC952
22U_0805_6.3V6M

2

1

1

PC937
22U_0805_6.3V6M

1

PC951
22U_0805_6.3V6M

@

2

PC950
22U_0805_6.3V6M

2

PC949
22U_0805_6.3V6M

1

2

1

@

PC936
22U_0805_6.3V6M

22u *25, @*7

C

1

PC935
22U_0805_6.3V6M

2

PC934
22U_0805_6.3V6M

1

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

CPU_CORE_CAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

5

4

3

2

Date:

Tuesday, March 26, 2013

1

Sheet

48

of

52

Rev
0.1

5

VGA@ PC1031
2.2U_0402_6.3V6M
2
1
VGA@ PC1032
10U_0402_6.3V6M
2
1

VGA@ PC1042
22U_0805_6.3V6M
2
1
VGA@ PC1043
22U_0805_6.3V6M

4

2

VGA@ PC1026
560U_2.5V_M

+
+

2@

PC1027
330U_D2_2.5VY_R9M

1

Issued Date
VGA@ PC1038
10U_0402_6.3V6M

VGA@ PC1025
560U_2.5V_M

2

1

VGA@ PC1037
10U_0402_6.3V6M
2
1

VGA@ PC1014
10U_0402_6.3V6M
2
1

VGA@ PC1024
2.2U_0402_6.3V6M
+

VGA@ PC1036
10U_0402_6.3V6M
2
1

VGA@ PC1013
2.2U_0402_6.3V6M
2
1

VGA@ PC1023
10U_0402_6.3V6M
2
1

VGA@ PC1018
10U_0402_6.3V6M

VGA@ PC1017
2.2U_0402_6.3V6M
2
1

VGA@ PC1016
2.2U_0402_6.3V6M
2
1

VGA@ PC1015
2.2U_0402_6.3V6M
2
1

VGA@ PC1012
10U_0402_6.3V6M
2
1

VGA@ PC1022
10U_0402_6.3V6M
2
1

1

VGA@ PC1035
2.2U_0402_6.3V6M
2
1

VGA@ PC1034
10U_0402_6.3V6M
2
1

VGA@ PC1011
10U_0402_6.3V6M
2
1

VGA@ PC1021
2.2U_0402_6.3V6M
2
1

1

VGA@ PC1010
2.2U_0402_6.3V6M
2
1

2

VGA@ PC1020
2.2U_0402_6.3V6M
2
1

1
VGA@ PC1009
10U_0402_6.3V6M
2
1

2

C

VGA@ PC1019
2.2U_0402_6.3V6M
2
1

1

VGA@ PC1008
2.2U_0402_6.3V6M

VGA@ PC1007
10U_0402_6.3V6M
2
1

VGA@ PC1006
2.2U_0402_6.3V6M
2
1

VGA@ PC1005
10U_0402_6.3V6M
2
1

VGA@ PC1004
2.2U_0402_6.3V6M
2
1

VGA@ PC1003
10U_0402_6.3V6M
2
1

VGA@ PC1002
10U_0402_6.3V6M
2
1

VGA@ PC1001
2.2U_0402_6.3V6M
2
1

2

D

VGA@ PC1033
10U_0402_6.3V6M
2
1

VGA@ PC1030
2.2U_0402_6.3V6M
2
1

VGA@ PC1041
22U_0805_6.3V6M
2
1

1

VGA@ PC1029
10U_0402_6.3V6M
2
1

2

VGA@ PC1040
22U_0805_6.3V6M
2
1

1
VGA@ PC1028
10U_0402_6.3V6M
2
1

2

B

VGA@ PC1039
22U_0805_6.3V6M
2
1

5
4
3

+VGA_CORE

+VGA_CORE

Security Classification

2012/07/10

3

2

Deciphered Date
2013/07/10

2

1

AMD MARS
GPU_CORE
560uF*2+330uF*1
10uF*8+2.2uF*16
D

C

AMD MARS
meet ripple
22uF*5+10uF*11

B

A
A

Compal Secret Data

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VGA_CORE CAP

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, March 26, 2013

Sheet
1

49
of
52

Rev
0.1

5

4

3

2

Version change list (P.I.R. List)
Item

D

C

Fixed Issue

Reason for change

Rev.

PG#

Modify List

1

Page 1 of 2
for PWR

Date

PR801 change to 20K
Add PC805, PR814
Delete PR615, PC619, PR511, PC513, PR530,
PR531, PC530

1

Tune VGA sequence

Tune VGA sequence

VGA

2
3
4

Module Design

Module Design change 3/5V solution
Change RTC type to non-charge
Check no need keep with HW

3/5V
39
39

5

EMI request

6

EMI request

7
8

Costdown

Phase

11/06 DVT
11/13 DVT
11/13 DVT
11/20 DVT

Un-pop PR112, PR113
Delete PR112, PR113, PBJ101

EMI

Add PR518, PC522, PR714, PC714, PR829, PC828,
PR806, PC807, PC749
Change PR701 to 2.2

EMI confirm remove

EMI

Delete PL102, PC103, PC101, PL202, PC201 and PL703

SY8208B/C update

42
42

Adjust output voltage and add Cff

45

Modify VR_ON to VGA_ON_R net

47

11

Improve CPU transient character

46

Change PL402, PL403 from 5x5x3 to 7x7x3 12/13 DVT2
12/22 DVT2
Add PR411, PR413
Add PC609 into 4700P
12/22 DVT2
Change PR608 from 133K to 127K
Change PR801 from 20K to 0
01/04 DVT2
Reserve PC805
Change PR709 from 150K to 390K, PR732 from 10 to 22,
01/09 DVT2

12
13

Improve CPU transient character
Tune sequence

48
42

14
15
16
17
18
19
20

0 ohm reduce
To meet MARS/AMD ripple SPEC
Provide 3/5V PG signal to EC
Modify H-Gate resistor

9

+1.05V ripple close
upper and mean too low

10

VGA_CORE can't disable

21

EMI request
ESD request
ESD request
ME issue

Use HW to control VCIN1 function

D

Recovery at PVT phase

11/20 DVT
11/26 DVT

PC745 from 1U to 2.2U, PC711 from 0.082U to 0.1U

Unpop PC902

01/09 DVT2
02/04 PVT

Change PR801,PR507,PR513,PR523 to R-pad
Add PC1028~PC1043
Add PR416
Change PR847, PR848 from 0 to 2.2
Add PC101 into 0.1uF
Add PC521, PR503, PC507
Add PR204
Change PC303,PC304,PC315,PC318,PC517,
PC819,PC820 from 0805 to 0603

02/22
02/22
02/22
02/25
02/26
02/26
03/05

Change PC428 from 4700p to 10n,
PC427 from 0.047u to 6.8n

49
42
47
39
43
40

Shrink component to reduce Z height

C

PVT
PVT
PVT
PVT
PVT
PVT
PVT

03/26 PVT2

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, March 26, 2013
1

50

of

52

Rev
0.1

A

B

A --> B1 Change List

1

2

C

D

1123A------------------1.Delete +3VALW to +3VALW_PCH MOS Circuit:
Page12, Delete C589,C414,R77,Q10,C590,C591
Page34, Delete U28.16 PCH_PWR_EN# off page
2.Page12, Unpop R210 ,Pop L3 and C22 for +1.05VS_VTT high ripple
3.Unpop and Componment reduce----------------------------Page16, Delete C824,C828,C831,C836,C839 for unpop reduce.
Page20, Delete C870,C871,C923,C922,C921,C920 for unpop reduce.
Page27, Change R399,L30,L47 TO R_Short
Delete C456,C637,C474,C497,C580,C581
Pop R80 and unpop R396,Q25,C411,R584,Q52
Page28, Delete C606,C646,C607
Change R239 to R_short
Page29, Delete C775,C776,C778,C781,C782
Page31, Delete C461,C462
Change R423 to R_short
Page32, Delete C161
Change R308 to R_short
Page34, Change R495 to R_short
Page36, Chagne L55,L54,L52 to R_short
4.Page24, SWAP RP41.1,RP41.2
5.Page27, Change R123,R127 Pull high to +HDMI_5V_OUT
1122A------------------1. Page22, Add X7603@ for VRAM 2Gb*4 HYN 128M16
Add X7604@ for VRAM 2Gb*8 HYN 128M16
1121A------------------1. Page06, Add R937 for EC_SCI# Path to GPIO34
2. Page09, RP28.5 connect to GPIO34
1120A------------------1. Page06, Delete chargeable RTC circuit
Change ODD to SATA port1
Page32, Modify ODD SATA netname to SATA port 1 .

1203A------------------1.Page11, R169 change to @
2.Page36, Mound R417 (Cancel AMIC@)
3.Page18, R898, R899, R409, D22 change BOM Structure to VGA@
4.Page34, R485, R483 change to 9012@
R479, R478 change to 940@
5.Page35, C663, SW4, SW5 change to 9012@
6.Page19, Delete R1035, X7601/X7603/X7604
7.Page17, R1006 change to VGA@
8.Page09, R306 add BOM structure UMA@
9.Page06, C153, C154 change to 15P_0402
10. Page18, C848, C849 change to 12P_0402
11.Page07, C2, C3 change to 10P_0402
1129A------------------1.Page32, JODD1.11 Reserve a TestPoint for DFT
2.Page29, Pop C779, C783
3.Page17, Update U51 BOM Structure for BOM Select
4.Page04, Add QDJC@ BOM Structure for U1
1128A------------------1.Page18, Add D22 to prevent GPU_ACIN leakage
2.Broadcom recommend modify(Add componment Function Field is 45.1)
Page29, Add C803 0.1uF to U48.20(VDDO_CR),
Page29, Add L74(BLM31PG601SN1) between Q6.1 and +3V_LAN
Add C820 (1uF) to Q6.1
Page30, Add L75(BLM31PG601SN1) between Q9.1 and
+XDPWR_SDPWR_MSPWR
Add C820 (1uF) to Q9.1
3.Page18, Change L69 to R_Short
4.Page20, Change L72 to BLM18AG121SN1D (the same to L71)
5.SW confirmed function
Page08, unpop R245,d21
(ACPRESENT tp PCH no need)
Page36, unpop R529
(EC_BEEP no need)
6.Default EC_SCI# to GPIO34
Page06, Pop R937
Page09, Unpop R66
7.Reserve DGPU_HOLD_RST# direct to PLTRST_VGA# path
Page08, Add R405 0ohm connect DGPU_HOLD_RST# and PLTRST_VGA#
8.Page35, Chagne R702 to 680ohm (ME confirm)
9.Page35, Delete SW1 (debug) for Layout convenience
10.Page24,Change L6 to (4.7uH_SH00000GS00) same as Q5WV8
11.Page29,Change RP22 to R768,R769,R770.R771 for SD 3.0 EMI
1127A------------------1.Page24, Change U50.11 connect from L6.2 to L6.1
2.Page34, Change R502 from R_short to 940@ 0ohm
3.Page36, Change R237,R238 to 60 Ohm(Codec vendor recommend)
4.Page09, Add R67 for EC_SCI# -> GPIO 10 option
1126A------------------1.Page36, Delete D26 (ESD Confirm)
2.EMI part Schematics modify(EMI confirm1123)
Page26, Change R368,R369,R370,R371,R372,R373,R374,R375 to 0403
R_short
Page28, Change R175,R180 to 0603 R_short
Page36, Change L36,L38,L51,R527,R528,R532,R533 to 0603 R_short
Page32, Delete C408,C398
Page33, Delete R453,R455,R456,R457
3.Page38, Change 3/5 VS circut BOM Structer to 35V@
4.Page32, Modfiy JHDD1 to LTCX004LGA0 (S H-CONN CCM
C127043HR022M27FZR 22P H3.05 HDD)
Modfiy JODD1 to LTCX004HZ00 (S H-CONN SANTA 20190X-X 13P
H3.6 ODD)

2. Page29, +1.2V_LAN_OUT add 680P for EMI
3. Page37, Modify H21 from 2P5 to 3P0
4. Page38, Add 2 jump for power cousumption measure
J36(+3VS),J37(+5VS)
5. Delete XDP port and related circuit
Page04, Delete C63,C64,C96,C97,C98,R20,R21,R22,R23,R27~R31
Delete R3,R86,R87,R88,R89,R90,R91,R4,C92,C93
Delete R5,R14,R15,R16,R7,R19,R25,C35,JXDP1
Page07, Delete R66,R67
6. ESD DVT Modify:
Page08, Delete C39
Page24, Delete D6
Page28, Delete D7,D18
Page30, Delete D38
Page33, Delete D16
Page35, Delete D25,D30,D34
Page36, Delete D26,R544,C572
Page37, Delete ESD TP JUMPs:
J10,J20,J17,J21,J16,J19,J18
J22,J24,J28,J25,J29,J23,J27
J26,J30,J31,J33,J32,J34,J35
Page29, C786 change to EMC@
Page04, Add C96 to DIMM_DRAMRST#
Page33, C487 change to EMC@ and 0.1uf
Delete D4
Page26, C378 change to EMC@
C387 change to EMC@
1119A------------------1. Page06, Add a nochargeable RTC battery.
2. Page15, Add R191 for DDR_VTT_PG_CTRL pull high +5VS option.
3. Add page24, Reserve eDP to LVDS translator (RTD2132R)
Add bom structure TL@(translate) and EDP@(eDP mode)
4. Page25, Add R947 for ENVDD option.
Add connect TL_INVT_PW to INVTPWM
Add connect RTD2132R TL_HPD to EDP_HPD
Modify JLVDS1 pin net name fo Co-Lay eDP & LVDS

3

E

1107A------------------1. Page04, Move R25 to JXDP1.60
Update U1 option component for CPU
2. Page6,8, Change EC_SMI from GPIO77 to GPIO34
Delete R445
3. Page07, Change Y2 to X3G024000DC1H(SJ10000CS00)
4. Page08, U17, U43, R310 change to @
Mount R65
R310.1 change to +3VS
5. Change all 932@ to 940@
R161, D29, R564, U6, R569, C522, C523, C552, D36, Q39, R522,R586, R589, R607,
R610, R624, R693, U41, U44, C516, C518, D28, R146, R158, R159, R160, R496, R499,
R504, R507, R508, R511, R601, U28, U29
6. Page11, R169 change to XDP@
7. Page12, add C414 and change PCH_PWR_EN to PCH_PWR_EN#
delete Q33, R561, R563
8. Page16, delete R58, R298, R300, C163, R299, R302
9. Page17, Add option component (U51) for SUN_XT
10. Page19, Add R900, R901 with BOM structure @
11. Page24, delete R405, U20, R362, R401, C164
Change U8 to G5243AT11U(SA000028Y10)
12. Page25, delete R367, D7, F1, D8, D19
13. Page26, change L47, L48 to BLM18AG121SN1D(SM010030010)
14. Page27, Delete D31, F2, C450
15. Page28, Delete R781, D23, R782, R785, U49, C803
16. Page29, Delete R792
change T1 to GST5009-E (SP050006B10)
17. Page30, delete R414, C166
R438, Q20 change to @
Change U9 to G5243AT11U(SA000028Y10) with BOM@
18. Page31, delete R595, R587, Q34, R597, R596, R562
19. Page32, Change U25 to SY6288D10CAC_MSOP8(SA00004KB10)
Change JUSB1 to OCTEK_USB-09EAAB(DC233008O20)
Delete R472, R469, R460, R462, C635, U46, R459, R463, R464
20. Page33, Mount R503
Change R506 to 8.2K
Change R509 to R_Short with BOM @
Delete R491, R493, D20
21. Page34, add R535 (100K_0402)
Mount R632
21. Page35, L51 change to BLM18AG121SN1D(SM010030010)
Change JMIC1 to ACES_88266-02001(SP020008Y00)
Delete R143, R668, R162, R181, C719, R671
23. Page37, delete R424, C169
Change U12 to G5243AT11U(SA000028Y10)
24. Page43, SW1 change BOM Structure to @
1015A------------------1. Modify BOM Structure/Function Field for EMC@(45.1)
Page06, RP14
Page07, RP19, R390
Page24, L11
Page25, R368, R369, R370, R371, R372, R373, R374, R375
Page27, L42, L45, L46,R175, R180
Page28, R774
Page29, R897, C814, D39
Page32, L24, L25, R458, R461
Page35, R527, R528, R532, R533, L36, L38, D1, C62
2. Modify BOM Structure/Function Field for XEMC@(45.1)
Page04, C63, C64, C96, C97, C98, C94, C95, C60, C92, C93, C35
Page07, R104, C152, R402, C453
Page08, C39
Page24, C528, C549, C364, C365, D6
Page25, D2, L13, L14, L15, L16
Page28, C792, C786
Page29, R26, C26, C806, C807, C808, C809, JP1, JP2, D38
Page31, C408, C398
Page32, D15, D16, D4, C487, R453,R455, R456, R457, L26
Page33, R477, C501, R513, C520, C506, C507, C511
Page34, C551, C553, D25, D30, D34
Page35, R548, C573, R671, C719, C556, C550, C444, C445, D27, D37, D26, R544, C572
Page36, C630
3. Modify Function Field to 45.1 only (BOM Structure is same as before)
Page04, R27, R28, R29, R30, R31
Page07, RP20
Page33, R160
Page35, R143, L51
4. Display BOM structure and Value of U1 (CPU)
5. Display BOM structure of R0402_0OHM-NEW and R0603_0OHM-NEW (R Short Pad show BOM Structure @)
6. Page08, Update note of GPIO66

1

2

3

4

4

2012/07/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR-HW1

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, March 26, 2013
E

51

of

52

Rev
1.0

A

1

2

3

B

C

D

E

C --> Pre-MP Change List

B1 --> B2 Change List

B2 --> C Change List

0114---------------------------1.Page03, Add U1 with QDJA@
2.Page30, R897 change to SM01000LU00
3.Page24, L63,L73 change to SM01000EJ00
4.Page25, L11 change to SM01000EJ00
5.Page36, L33 change to SM01000EJ00
6.Page31, U9, C165 with IOAC@
0110---------------------------1.Page32, Delete R312,R313,R314,R315
Add C392,C393,C391,C394 with EA50@
2.Page27, Add C35
3.Page38, Delete Q45,R570,R571
0108---------------------------1. Page33, R458, R461 change to R0402_0OHM-NEW
Add JFP1
2. Page26, Delete L13, L14, L15, L16
3. Page29, Delete C792, C99
4. Page31, Delete J4
5. Page10,25 change Touch screen port from USB port 5 to port6.
6. Page25,34 change net name of TS_INT to TS_EN
7. Page10 add USB port 5 for Finger Print
8. Page38, Add C19
9. Page26, Add C396, C398
10.Page36, Mount C554
11.Page38, Mount C979
12.Page35, Reserved SW6,SW7,SW8,SW9
13.Page32, Add C534, C535, C536, C537 for JHDD2 with BA51@
change C391,C392,C393,C394 to R312,R313,R314,R315
Update Power schematics
0107---------------------------1. Page06, R937 change to R0402_0OHM-NEW
R75 change to R0603_0OHM-NEW
2. Page07, R108 change to 15_0402_5% with 1ROM@
RP19 change to 15_0804_8P4R_5% with 1ROM@
Add R105, R106 with 1ROM@ for PCH_SPI_IO2_1, PCH_SPI_IO3_1
Change R102, R103, R109, U7, C67, PR20 to 2ROM@
3. Page08, R62, R65 change to 0402_0OHM-NEW
4. Page10, Change Touch Screen USB port frum Port3 to Port5.
R155 change to R0603_0OHM-NEW
5. Page24, Change Q53 to @
6. Page25, R947,R363,R949 change to R0402_0OHM-NEW
Add C376,C377,C388,C389 with TL@
Add R414, R426
Add R424, R425 with @
7. Page27, R80 change to R0603_0OHM-NEW
L48 change to R0603_0OHM-NEW
8. Page29, C99 change to XEMC@
R774 change to 56_0402_5%
9. Page32, R49, R593 change to R0805_0OHM-NEW
9. Page34, R236 change to R0805_0OHM-NEW
10. Page38, R926 change to R0402_0OHM-NEW
0103---------------------------1.Page35, R698,R701 change to 680 ohm
R702 change to 499 ohm
2.Page18, Un-mount C847
3.Page38, Add U38, R77, C63
Update Power Schematics
1228---------------------------1. Page25, Add USB20_P3/N3 on JLVDS1.35/36
Add R81
2. Page35, Delete JTP1, R609, R610, C552, R693, R607, R608, D36
3. Page34, change Q50 to L2N7002LT1G_SOT23-3
change R506 to 18K_0402_5%

0306--------------------1.Page27, Mount R410, R411
Change R240, R241 with @
Change R418 to 4.7K
0304--------------------1.Page20, Mount C872, C873, C874, C889, C917, C918, C919
2.Page25, change C371,C372, C369, C370 with EDP@
3.Page33, Change L24, L25 to SM070001E00
0301--------------------1.Page08, change R62,R65 to 0 ohm
2.Page12, Add C408
3.Page34, Add D25
Reserved D26
0227--------------------1.Page29, Del R766
2.Page32, change JDB1 to E-T_1001K-F50C-05R_50P-S
0226B-------------------Modify for ESD
1.Page11, Mount C13,C14 (10U_0603)
1.Page12, Change C40 to 10U_0603
Mount C31 (1U_0402)
3.Page15, Mount C117 (10U_0603)
Add C161 10U_0603
4.Page33, Mount C483 with 0.1U
Reserved D3 with XEMC@
5.Page38, Add C39, C64,C92,C93 22U_0805
Update power schematics
0226-------------------1.Page12, Del T99
2.Page27, Mount R204,R241, R407,R408
Change R412,R413 with @
3.Page28, Add R312 with @
4.Page34, Del R590 (Add offpage for H_PROCHOT#_EC)
Del R505
Update Power Schematics
0221-------------------1.Page18, R898, R899 change to R0402_0OHM-NEW
2.Page25, Add TS@ for R81, R414, R426

0411--------------------1. Change U51 PN to R3 (SA00006G610, SA000061J20)
2. Page06, unmount R446, C168, D32
Mount D23, C151
0329--------------------1.Page04, Add SR16Q@ and SR170@ for U1
2.Page06, Change C151, D23 with @
Mount R446, D32, C168
0326--------------------1.Page1, Change PCB PN to DA60000XL10
2.Page29, Mount C815
Update Power Schematics
0321--------------------1.Page8, G_SEN_INT change from GPIO80 to GPIO52.
2.Page34, change R506 to 100K_0402_5%

1

2

0219-------------------1.Page08,34,37 G_SEN_INT connecto to PCH_GPIO80
Change U2.4, U2.6 to D_CK_SCLK/D_CK_SDATA
2.Page29, Reserved C815
3.Page22, Add C1024, C1025, C1026, C1023, C1027, C1028, C1029, C1030 with 128@
4.Page23, Add C1031, C1032, C1033, C1034, C1038, C1036, C1037, C1035 with VGA@
5.Page38, Reserved R556, R574, Q55, R557, R575, Q41, R570, R571, Q45
0218-------------------1.Page06, Update Y1 CIS Symbol
Add D23, C151
Change R446, D32, C168 to @
2.Page18, Change C823, C827, U52, R798 with @
2.Page29, Add R781, C792
3.Page30, Add R782 and Mount C822
2.Page34, Change R506 to 33K

3

4

4

2012/07/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR-HW1

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Friday, April 26, 2013
E

52

of

52

Rev
1.0

www.s-manuals.com



---

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Create Date                     : 2015:03:12 06:30:35+04:00
Creator Tool                    : PDFsharp 1.2.1269-g (www.pdfsharp.com)
Modify Date                     : 2015:11:11 22:04:58+02:00
Metadata Date                   : 2015:11:11 22:04:58+02:00
Producer                        : PDFsharp 1.2.1269-g (www.pdfsharp.com)
Format                          : application/pdf
Title                           : Compal LA-9531P - Schematics. www.s-manuals.com.
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Subject                         : Compal LA-9531P - Schematics. www.s-manuals.com.
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