Compal LA 9591P Schematics. Www.s Manuals.com. R0.4 Schematics
User Manual: Motherboard Compal LA-9591P VAUA0 Goliad 14 - Schematics. Free.
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : VAUA0
LA-9591P (DAA00005W10)
PCB NO :
BOM P/N : 4319LK31L01
1
GPIO MAP: 3.0
Goliad 14"
2
2
Haswell ULT
2013-05-17
REV : 1.0 (A00)
3
@ : Nopop Component
1@ : M/B SPI ROM
2@ : TAA/B SPI ROM
EMC@ : EMI, ESD and RF Component
XDP@ : XDP Component
CONN@ : Connector Component
3@ : M/B for non support WWAN
4@ : M/B SPI 4M ROM Component
5@ : TAA/B SPI 4M ROM Component
7@ : M/B for Non-Vpro
SPI on M/B
TAA
3
Vpro
1@/3@/4@/EMC@
2@/3@/5@/EMC@
non-Vpro
1@/EMC@
2@/EMC@
4
4
MB PCB
Part Number
Description
DAA00005W10
PCB 0VN LA-9591P REV1 M/B
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Cover Sheet
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
E
1
of
58
A
B
C
D
E
Goliad 14 Block Diagram
Memory BUS (DDR3L)
eDP CONN
1
DDR3L-DIMM X2
1333/1600MHz
eDP
BANK 0, 1, 2, 3
PAGE 22
PAGE 18 19
DP
Mini-DP
PAGE 27
USB2.0[3]
INTEL
DP
For MB/Dock
DP Video Switch
IDT VMM2320
VGA
DP
1
Pericom
PI3VDP12412
PAGE 22
Trough eDP Cable
DOCKED_LIO_EN
DDI2
SLGC55584A
HASWELL ULT
PAGE 27
PAGE 21
Camera
USB2.0[0]
NX3DV221
SW_USB2.0[0] USB POWER SHARE
PAGE 33
USB20 Switch
PAGE 33
USB
DOCKING
PORT
2
HDMI
HDMI CONN
PAGE 23
Reduce Level
ShifterPAGE 23
PAGE 6~17
Card reader
SD4.0
PAGE 30
O2 Micro OZ777FJ2LN
PAGE 30
PCIE4
WLAN+BT/
60GHz
PAGE 28
PAGE 31
3
USB2.0[2]
LAN SWITCH
PI3L720
W25Q64CVSSIQ
PAGE 29
RFID
RJ45
PAGE 35
Fingerprint
CONN
32M 4K sector
FP_USB
PAGE 35
HDA Codec
ALC3226
PAGE 7
SMSC SIO
ECE5048
PAGE 26
Vol bottom SW
IO/B
DAI
CPU XDP Port
PAGE 9
To Docking side
Trough eDP Cable
Automatic Power
Switch (APS) PAGE 9
Dig. MIC
PAGE 22
WiFi ON/OFF
PAGE 35
Trough eDP Cable
PAGE 29 USH board
PAGE 37
IO/B
DC/DC Interface
SMSC KBC
MEC5075
FAN CONN
3
PAGE 40
Combo Jack
Touch Screen
Conn
PAGE 36
USB2.0[4]
PAGE 20
Near Field
Communications con
PAGE 26
PAGE 22
USH
BCM5882
TDA8034HN
USB3.0/2.0
INT.Speaker
SATA Conn
W25Q32BVSSIQ
LPC
PAGE 35
2
PAGE 25
64M 4K sector
USB2.0[6]
PAGE 28
Transformer
PAGE 33
DOCK _USB2.0[5]
DOCK_USB3.0[3]
Free Fall sensor
PAGE 25
SATA3
Smart Card
PAGE 33
USB3.0/2.0
HD Audio I/F
SATA1
USB2.0[7]
Discrete TPM
AT97SC3204
PAGE 31
USB3.0/2.0+PS
IO/B
PCIE6_L0
Full Mini Card
WWAN+mSATA
SW_USB2.0[5]
SW_USB3.0[3]
USB3.0[1]
SPI
PCIE3
USB3.0[2]
USB2.0[1]
PCIE5_L0
PCI Express BUS
Intel Clarkville
I218LM
DOCK _USB2.0[0]
USB2.0[5] PI3USB3102
Switch
USB3.0[3] USB3&2PAGE
32
PAGE 34
DAI
DOCK_USB3.0[3]
SATA0
DOCK_USB2.0[0]
DOCK_USB2.0[5]
DOCKED
DDI1
BC BUS
PAGE 39
PAGE 37
Power On/Off
SW & LED PAGE 40
4
KB and TP CONN
PAGE 38
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Block diagram
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
E
2
of
58
5
4
3
2
1
POWER STATES
SLP
S3#
SLP
S4#
SLP
S5#
SLP
A#
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
S4 (Suspend to DISK) / M3
LOW
LOW
S5 (SOFT OFF) / M3
LOW
S3 (Suspend to RAM) / M-OFF
Signal
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
ON
ON
HIGH
ON
ON
ON
OFF
OFF
HIGH
HIGH
ON
ON
OFF
OFF
OFF
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
LOW
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
State
D
C
ALWAYS
PLANE
PCIE
CLOCKS
PCIE 1
USB3.0
USB3.0 1
JUSB3-->IO-->Right
USB3.0 2
JUSB1-->Rear left
USB3.0 3
JUSB2-->Rear Right//DOCK
power
plane
+3.3V_SUS
+5V_RUN
+3.3V_M
+3.3V_M
+3.3V_ALW
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+1.05V_M
+3.3V_ALW_PCH
+0.675V_DDR_VTT
+3.3V_RTC_LDO
+1.05V_RUN
D
PCIE 2
PCIE 3
LOM
PCIE 4
WLAN (WiGi)
PCIE 5
MMI (CARD READER)
PCIE 6
PM TABLE
+5V_ALW
DESTINATION
SATA
(M-OFF)
SATA 3
WWAN(PP/mSATA)
SATA 2
NA
SATA 1
HDD
SATA 0
DOCK
C
+VCC_CORE
USB PORT#
State
B
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
HSW
ULT
need to update Power Status and
PM Table
USH
DESTINATION
0
JUSB1 // E-Dock 1
1
IO/ JUSB3
2
WLAN + BT
3
CAMERA
4
USH->SMART CARD
5
JUSB2 // E-Dock 2
6
WWAN
7
TOUCH
0
BIO
1
NA
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Port assignment
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
3
of
58
4
3
2
+1.05V_RUN
1
A_ON
5
+3.3V_RUN
PWRSHARE_EN# ESATA_USB_PWR_EN#
TPS51212
(PU300)
DOCKED
D
EN_INVPWR
ADAPTER
FDC654P
(Q2)
+1.05V_M
+1.05V_RUN_VMM
+5V_USB_
CHG_PWR
MPHYP_PWR_EN
+BL_PWR_SRC
+PWR_SRC
G471
(U35)
D
TPS22966
(U31)
BATTERY
G471
(U35)
SI3456
(Q125)
+3.3V_RUN_VMM
ALWON
C
CHARGER
+USB_PWR
+1.05V_MOD_PHY
TPS51225
(PU100)
C
+5V_ALW
RUN_ON
G471
(IO/B)
RUN_ON
PCH_ALW_ON
TPS22966
(U46)
RUN_ON
APL3512
(U9)
RUN_ON
RUN_ON
TPS22966
(U22)
EN_LCDPWR
3.3V_HDD_EN
SIO_SLP_LAN#
MCARD_WWAN_PWREN
SUS_ON
AUX_EN_WOWL
TPS22966
(U3)
TPS22966
(U43)
+USB_IO_PWR
TPS22966
(U18)
+3.3V_ALW_PCH
+5V_RUN
_AUDIO
+3.3V_M
+0.675V_DDR_VTT
+3.3V_WLAN
+3.3V_SUS
+3.3V_LAN
+3.3V_mSATA
_WWAN
+LCDVDD
+3.3V_RUN
3.3V_CAM_EN#
+1.35V_MEM
0.675V_DDR_VTT_ON
+VCC_CORE
TPS22966
(U45)
+3.3V_ALW
B
SUS_ON
B
RT8207
(PU11)
H_VR_EN
TPS51622
(PU500)
A_ON
USB_SIDE_EN#
+3.3V_HDD
+1.05V_RUN
+5V_RUN
3.3V_TS_EN
LP2301ALT1G
(Q1)
+5V_TSP
LP2301ALT1G
(Q3)
+3.3V_CAM
A
+3.3V_RUN
_AUDIO
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power rails
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
4
of
58
5
4
3
2
1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
202
2N7002
DIMMA
200
2N7002
1K
202
PCH
D
+3.3V_ALW_PCH
1K
AN1
AH3
AU3
AK1
SML1_SMBCLK
3A
0ohm
LAN_SMBCLK
28
SML0DATA
0ohm
LAN_SMBDATA
31
LOM
53
SML1_SMBDATA
A5
SML0CLK
2.2K
XDP
51
2.2K
+3.3V_ALW_PCH
2.2K
B6
3A
2.2K
0ohm
NFC_SMBCLK
0ohm
NFC_SMBDATA
10K
NFC
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
+3.3V_RUN
10K
4
+3.3V_ALW
6
B4
1A
1A
D
DIMMB
200
G Sensor
127
129
DOCKING
30
2.2K
WWAN
32
C
C
2.2K
1B
B5
LCD_SMBCLK
A4
LCD_SMDATA
+3.3V_ALW
1B
2.2K
KBC
2.2K
1C
1C
A56
B59
PBAT_SMBCLK
PBAT_SMBDAT
+3.3V_ALW
100 ohm
7
100 ohm
6
BATTERY
CONN
2.2K
2.2K
A50
1E
B53
1E
B
+3.3V_SUS
M9
USH_SMBCLK
L9
USH_SMBDAT
USH
B
2.2K
2.2K
MEC 5075
2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
+3.3V_ALW
10K
10K
B50
1G
A47
1G
+3.3V_ALW
9
CHARGER_SMBCLK
8
CHARGER_SMBDAT
Charger
2.2K
2.2K
2D
B7
A
2D
A7
+3.3V_ALW
BAY_SMBDAT
A
BAY_SMBCLK
2.2K
2.2K
2A
2A
5
B48
B49
GPU_SMBDAT
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_ALW
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
GPU_SMBCLK
4
3
2
Title
SMbus Block diagram
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
5
of
58
5
4
3
2
1
2
D
RC1
330K_0402_1%
1
+RTC_CELL
+3.3V_ALW_PCH
1
2
D
PCH_AZ_SDOUT
1K_0402_5%
@ RC3
2
FLASH DESCRIPTOR SECURITY OVERRIDE
@ RC2
330K_0402_1%
1
PCH_INTVRMEN
LOW = ENABLE (DEFAULT)
HIGH = DISABLE
+3.3V_RUN
1
CC1
2
PCH_RTCX1_R
2
1
1
1M_0402_5%
2
2 20K_0402_5%
20K_0402_5%
2
@
ME1
1
CC3
2
1
2
1
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
AW5
AY5
AU6
AV7
AV6
AU7
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
PCH_RTCRST#
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
2
@
CMOS1 SHORT PADS~D
1
2
1U_0402_6.3V6K
CC4
SHORT PADS~D
2
1U_0402_6.3V6K
CMOS place near DIMM
<26>
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_SDIN0
<36>
1
ME_FWP
2
RC9
PCH_AZ_SDOUT
1K_0402_5%
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
AUDIO
SATA
Shunt
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
Clear CMOS
Keep CMOS
Open
ME_CLR1
<9>
<9>
<9>
<9>
<9>
TPM setting
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
<9>
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PAD~D
PAD~D
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
@ T3
@ T4
PCH_JTAG_JTAGX
@ T5
PAD~D
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
CMOS setting
CMOS_CLR1
2
1
2
RC11
RC12
HASWELL_MCP_E
UC1E
18P_0402_50V8J
1
1
HDD_DET#
100K_0402_5%
mCARD_PCIE_SATA#
10K_0402_5%
PCH_RTCX2
C
1
2
YC1
32.768KHZ_12.5PF_Q13FC135000040
CC2
2
<9>
1
PCH_RTCX1
1
2
1
RC7
RC8
RC6
2
0_0402_5%
18P_0402_50V8J
1
+RTC_CELL
1
@ RC4
RC5
10M_0402_5%
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
JTAG
J5
H5
B15
A15
SATA_PRX_DKTX_N0_C
SATA_PRX_DKTX_P0_C
SATA_PTX_DKRX_N0_C
SATA_PTX_DKRX_P0_C
J8
H8
A17
B17
<34>
<34>
<34>
<34>
SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
<25>
<25>
<25>
<25>
DOCK
C
SATA HDD
J6
H6
B14
C15
F5
E5
C17
D17
SATA_PRX_MSATATX_N3
SATA_PRX_MSATATX_P3
SATA_PTX_MSATARX_N3
SATA_PTX_MSATARX_P3
V1
U1
V6
AC1
MPCIE_RST#
HDD_DET#
A12
L11
K10
C12
U3
2
SATA_IREF
@ RC14
SATA_COMP
SATA_ACT#
<31>
<31>
<31>
<31>
WWAN mSATA
MPCIE_RST#
<12,31>
HDD_DET#
<25>
PCH_GPIO36
<12>
MCARD_PCIE_SATA#
<36>
1
0_0402_5%
PAD~D T1 @
PAD~D T2 @
SATA_ACT#
+PCH_ASATA3PLL
<40>
+1.05V_M
B
1
@RC16
@
RC16
0_0603_5%
2
B
Rev1p2
5 OF 19
+1.05V_M_JTAG
RC17
2
1
2
1
PCH_JTAG_TDI
51_0402_1%
PCH_JTAG_TDO
51_0402_1%
1
PCH_JTAG_TMS
51_0402_1%
1
PCH_JTAG_JTAGX
1K_0402_1%
RC18
2
RC20
2
@ RC10
2
@ RC22
1
PCH_JTAG_TCK
51_0402_1%
SATA Impedance Compensation
HDA for Codec
+PCH_ASATA3PLL
1
SATA_COMP
3.01K_0402_1%
<26>
<26>
<26>
2
RC19
2
PCH_AZ_SDOUT
33_0402_5%
1
2
PCH_AZ_SYNC
RC24
33_0402_5%
1
2
PCH_AZ_RST#
RC25
33_0402_5%
1 EMC@ 2
PCH_AZ_BITCLK
RC26
33_0402_5%
RC23
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
2
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
@ CC5
27P_0402_50V8J
1
<26>
1
PCH_AZ_CODEC_SDOUT
Reserve for EMI
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (1/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
6
of
58
5
4
3
2
1
+3.3V_RUN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
D
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
AU14
AW12
AY12
AW11
AV12
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
LPC
SPI
CL_CLK
CL_DATA
CL_RST
C-LINK
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
AF2
AD2
AF4
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
SML0CLK
SML0DATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
7 OF 19
1
R2
DDR_XDP_WAN_SMBCLK
SML0DATA
Rev1p2
2 PCH_SPI_DO2
1K_0402_5%
2 PCH_SPI_DO3
1K_0402_5%
4
DDR_XDP_WAN_SMBDAT
@ RC35
@ RC33
@ RC29
D
2
1
2
1
2
1
2
1
LAN_SMBCLK
0_0402_5%
LAN_SMBDATA
0_0402_5%
NFC_SMBCLK
0_0402_5%
<28>
<20>
NFC_SMBDATA
0_0402_5%
PCH_SMB_ALERT#
10K_0402_5%
MEM_SMBCLK
2.2K_0402_5%
MEM_SMBDATA
2.2K_0402_5%
SML1_SMBCLK
2.2K_0402_5%
SML1_SMBDATA
2.2K_0402_5%
SML0CLK
1K_0402_5%
SML0DATA
1K_0402_5%
<28>
<20>
+3.3V_M
1@ C5
1
2
64Mb Flash ROM
U1
<36>
SPI_WP#_SEL
SPI_WP#_SEL
@ R8
2
2 0_0402_5%
2 33_0402_5%
2 33_0402_5%
SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64
1
2
3
4
1
0_0402_5%
VCC
/HOLD(IO3)
CLK
DI(IO0)
8
7
6
5
SPI_PCH_DO3_64 1@ R5 1
1@ R7 1
SPI_CLK64
SPI_DO64
1@ R9 1
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
32Mb Flash ROM
2
SPI_WP#_SEL
@ R23
2 0_0402_5%
2 33_0402_5%
2 33_0402_5%
1
0_0402_5%
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
1
2
3
4
1
2
1
1
2
1
2
2
1
2
1
RC27
RC28
RC30
RC36
RC37
RC38
RC39
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
TAA Config
4@ C6
1
2
U2
1
2
1@
/CS
DO(IO1)
/WP(IO2)
GND
W25Q64FVSSIQ_SO8
C
2
0.1U_0402_25V6
+3.3V_M
PCH_SPI_CS1# 4@ R14 1
PCH_SPI_DIN 4@ R15 1
PCH_SPI_DO2 4@ R19 1
<18,19,25,31,9>
QC1B
DMN66D0LDW-7_SOT363-6
@ RC31
PCH_SPI_CS0# 1@ R3 1
PCH_SPI_DIN 1@ R4 1
PCH_SPI_DO2 1@ R6 1
<18,19,25,31,9>
+3.3V_ALW_PCH
+3.3V_M
R1
1
QC1A
DMN66D0LDW-7_SOT363-6
3
MEM_SMBDATA
<31>
<31>
<31>
SML0CLK
1
6
MEM_SMBCLK
PCH_GPIO73
<12>
SML1_SMBCLK
<37>
SML1_SMBDATA
<37>
SML1_SMBCLK
SML1_SMBDATA
5
<29,36,37>
<29,36,37>
<29,36,37>
<29,36,37>
<29,36,37>
2
HASWELL_MCP_E
UC1G
0.1U_0402_25V6
4@
/CS
VCC
DO/IO1
/HOLD/IO3
/WP/IO2
CLK
GND
DI/IO0
W25Q32FVSSIQ_SO8
8
7
6
5
SPI_PCH_DO3_32 4@ R16
SPI_CLK32
4@ R20
4@ R21
SPI_DO32
1
1
1
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
+3.3V_M
JTAA1
PCH_SPI_DO
PCH_SPI_DO
2@
5@
R11
R12
1
1
2 33_0402_5%
2 33_0402_5%
PCH_SPI_CLK
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
2@
5@
2@
5@
R13
R18
R10
R17
1
1
1
1
2
2
2
2
PCH_SPI_DIN
PCH_SPI_DIN
2@
5@
R22
R41
1
1
2 33_0402_5%
2 33_0402_5%
33_0402_5%
33_0402_5%
0_0402_5%
0_0402_5%
1
3
5
7
TAA_CLK64
9
TAA_CLK32
TAA_CS0#_R 11
TAA_CS1#_R 13
15
17
TAA_DIN64
19
TAA_DIN32
TAA_DO64
TAA_DO32
21
23
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
G
G
G
G
2
4
6
8
10
12
14
16
18
20
TAA_DO3_64
TAA_DO3_32
TAA_DO2_64
TAA_DO2_32
2@
5@
2@
5@
R43
R48
R58
R59
1
1
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
C
PCH_SPI_DO3
PCH_SPI_DO3
PCH_SPI_DO2
PCH_SPI_DO2
22
24
ACES_50185-02041-001
CONN@
SPI_CLK32
2
Reserve for EMI
1
@ CC15
1
@ CC14
10/100/1G LAN --->
<28>
<28>
<12,28>
WLAN (Mini Card 2)--->
<31>
<31>
<12,31>
MMI --->
WWAN (Mini Card 1)--->
<30>
<30>
<30>
<31>
<31>
<12,31>
PCH_TPM_LPC_EN
+3.3V_RUN
CLK_PCIE_LAN#
CLK_PCIE_LAN
LANCLK_REQ#
RC57 1
C43
C42
2 10K_0402_5% PCIECLK_REQ0# U2
B41
A41
Y5
RC56 1
2 10K_0402_5%
C41
B42
AD1
B38
C37
N1
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
MINI2CLK_REQ#
CLK_PCIE_MMI#
CLK_PCIE_MMI
MMICLK_REQ#
+3.3V_RUN
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1CLK_REQ#
A39
B39
U5
RC55 1
2 10K_0402_5%
B37
A37
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLOCK
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
A25
B25
3
4
YC2
24MHZ_12PF_X3G024000DC1H
CC6
2
XTAL24_IN
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
C34
AK8
AL8
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
AN15
AP15
PCI_CLK_LPC_0
PCI_CLK_LPC_1
1
1
2
2
1
2
1
1
2
2
1
+3.3V_RUN
B
2
PCI_CLK_LPC_0
12P_0402_50V8J
HASWELL_MCP_E
XTAL24_IN_R
18P_0402_50V8J
RC44
1M_0402_5%
UC1F
<29>
PCI_CLK_LPC_1
12P_0402_50V8J
2
0_0402_5%
@ RC40
@ C76
@ R57
33P_0402_50V8J
33_0402_5%
@ C85
@ R45
33P_0402_50V8J
33_0402_5%
2
1
1
CC7
2
SPI_CLK64
PAD~D T6
PAD~D T7
1
18P_0402_50V8J
@
@
B
0_0402_5%
22_0402_5%
22_0402_5%
1
1
1
2 RC65 @
2 RC64 EMC_3@
2 RC66 EMC@
PCI_CLK_LPC
CLK_PCI_DOCK
CLK_PCI_LPDEBUG
B35
A35
<34>
<37>
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
6 OF 19
Rev1p2
+PCH_VCCACLKPLL
PCI_CLK_LPC
RC58 1 EMC@ 2 22_0402_5%
RC61 1 EMC@ 2 22_0402_5%
RC63 1 EMC@ 2 22_0402_5%
CLK_PCI_TPM_TCM
<29>
CLK_PCI_5048
<36>
CLK_PCI_MEC
<37>
1
CLK_BIASREF
3.01K_0402_1%
2
1
2
1
2
1
2
1
2
MCP_TESTLOW1
10K_0402_5%
MCP_TESTLOW2
10K_0402_5%
MCP_TESTLOW3
10K_0402_5%
MCP_TESTLOW4
10K_0402_5%
RC45
RC46
RC47
RC50
RC52
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (2/12)
Size
Document Number
Date:
Friday, May 17, 2013
LA-9591P
Sheet
1
Rev
0.4
7
of
58
5
4
D
UC1C
<18>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
3
HASWELL_MCP_E
<19>
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
3 OF 19
AU37
AV37
AW36
AY36
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
AU43
AW43
AY42
AY43
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP33
AR32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
2
<18>
<18>
<18>
<18>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
<18>
<18>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
<18>
<18>
AP32
AY34
AW34
AU34
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
AU35
AV35
AY41
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AP49
AR51
AP51
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
UC1D
DDR_B_D[0..63]
<18>
<18>
<18>
DDR_A_BS0
<18>
DDR_A_BS1
<18>
DDR_A_BS2
<18>
DDR_A_MA[0..15]
<18>
DDR_A_DQS#[0..7]
<18>
DDR_A_DQS[0..7]
<18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
1
HASWELL_MCP_E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
D
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
DDR CHANNEL B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
AY49
AU50
AW49
AV50
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AM32
AK32
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
<19>
<19>
<19>
<19>
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<19>
<19>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<19>
<19>
AL32
AM35
AK35
AM33
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
<19>
<19>
<19>
DDR_B_BS0
<19>
DDR_B_BS1
<19>
DDR_B_BS2
<19>
DDR_B_MA[0..15]
<19>
C
DDR_B_DQS#[0..7]
<19>
DDR_B_DQS[0..7]
<19>
B
4 OF 19
Rev1p2
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (3/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
8
of
58
4
3
2 0_0402_5%
+3.3V_RUN
@ RC74
2
5
0.1U_0402_25V6
O
A
4
SYS_RESET#
1
B
1
PCH_PLTRST#
B
A
O
2
@ UC2
74AHC1G09GW_TSSOP5
3
1
1 ME_RESET#
8.2K_0402_5%
3
RC98
2
@ RC76
4
PCH_PLTRST#_EC
PCH_PLTRST#_EC
DSWODVREN
<29,31,36,37>
+3.3V_ALW2
@ CC82
1
2
UC3
TC7SH08FU_SSOP5~D
0.1U_0402_25V6
+PCH_VCCDSW3_3
PCH_AUDIO_EN
<12>
10K_8P4R_5%
ME_SUS_PWR_ACK_R
@ RC82
1
2
SUSACK#_R
0_0402_5%
RESET_OUT#
1
2
SYS_PWROK_R
0_0402_5%
@ RC84
5
1
SIO_SLP_A#
<37>
4
O
2
PM_APWROK
PM_APWROK
B
A
2
PCH_RSMRST#_R
10K_0402_5%
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
2
@ RC144
1
PM_APWROK_R
UC7
TC7SH08FU_SSOP5~D
1
RC136
D
P
PCH_BATLOW#
AC_PRESENT
PCH_PCIE_WAKE#
PCH_RSMRST#_R
0_0402_5%
G
5
6
7
8
2
3
4
3
2
1
1
PCH_DPWROK
@ RC79
RP12
1
D
@ RC78
330K_0402_1%
ME_SUS_PWR_ACK
10K_0402_5%
SUSACK#
10K_0402_5%
2 SUS_STAT#/LPCPD#
10K_0402_5%
P
2
2
0.1U_0402_25V6
G
5
2
1
G
1
XDP_DBRESET#
1
RC70
P
+3.3V_ALW_PCH
2
RC73
330K_0402_1%
@ CC9
1
+3.3V_RUN
@ CC8
1
1
+RTC_CELL
2
1
@ RC72
2
2
5
0_0402_5%
LOW = DISABLED
HASWELL_MCP_E
UC1H
SYSTEM POWER MANAGEMENT
<36>
1
2
ME_RESET#
8.2K_0402_5%
@ RC81
SUSACK#
<36>
SYS_PWROK
<15,37>
RESET_OUT#
<20>
PLTRST_NFC#
<29>
PLTRST_USH#
<30>
PLTRST_MMI#
<28>
PLTRST_LAN#
<21>
PLTRST_VMM2320#
<38>
PCH_RSMRST#_Q
<37>
ME_SUS_PWR_ACK
+3.3V_RUN
@ RC86 1
2 0_0402_5%
@ RC87 1
@ RC88 1
@ RC139 1
@ RC89 1
@ RC90 1
@ RC91 1
@ RC92 1
@ RC93 1
@ RC94 1
2
2
2
2
2
2
2
2
2
<37,9>
<37>
<37>
<36>
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SIO_PWRBTN#
AC_PRESENT
SIO_SLP_S0#
SIO_SLP_WLAN#
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PCH_PLTRST#
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
SIO_SLP_WLAN#
AK2
AC3
AG2
AY7
AB5
AG7
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
AW7
AV5
AJ5
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
V5
AG4
AE6
AP5
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
AJ6
AT4
AL5
AP4
AJ7
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#
PCH_DPWROK
PCH_PCIE_WAKE#
JAPS1
<36>
<37>
+3.3V_ALW_PCH
CLKRUN#
T10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
CONN@
ACES_50506-01841-P01
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
<12,29,36,37>
PAD~D @
SIO_SLP_S5#
T11
PAD~D @
T12
PAD~D @
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SIO_SLP_S3#
+PCH_VCCDSW3_3
+PCH_VCCDSW3_3
<37>
<6>
<36,39,43>
<36,39,43>
<36,39,44>
<36>
<28,36>
PCH_RTCRST#
<37,40>
PCH_RTCRST#
POWER_SW#_MB
SYS_RESET#
SIO_SLP_S0#
Rev1p2
8 OF 19
+3.3V_RUN
UC6 XDP@
14
2
TDI_XDP
0_0402_5%
<6>
PCH_JTAG_TMS
1
RC103
XDP@
2 TDI_XDP_R
0_0402_5%
3A
10
CPU_XDP_TDI
8
3B
4A
CPU_XDP_TMS
13
11
4OE
RC5 need to close to JCPU1
<15>
15
74CBTLV3126BQ_DHVQFN14_2P5X3
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
PCH_JTAG_JTAGX
2
1
CPU_XDP_TRST#
RC135
2
1
CPU_XDP_TCLK
RC97
@ 0_0402_5%
@ 0_0402_5%
<18,19,25,31,7>
<18,19,25,31,7>
CFG2
CFG3
<13>
<13>
CFG4
CFG5
CFG4
CFG5
CFG6
<13>
CFG6
2 1K_0402_5%
RC105 1
CFG7
<13>
CFG7
H_VCCST_PWRGD
XDP@
2 1K_0402_5%
H_CPUPWRGD @ RC106 1
H_VCCST_PWRGD_XDP
2 0_0402_5%
@ RC107 1
CFD_PWRBTN#_XDP
<37,9>
SIO_PWRBTN#
<15>
CPU_PWR_DEBUG#
2 0_0402_5%
@ RC108 1
CPU_PWR_DEBUG#_R
2 0_0402_5%
SYS_PWROK @ RC110 1
SYS_PWROK_XDP
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<6>
PCH_JTAG_TCK
@ RC111
@ RC112
@ RC142
1
1
1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK_R
CPU_XDP_TCLK
2
H_CATERR#
49.9_0402_1%
2
H_PROCHOT#
62_0402_5%
@ RC113
1
B
PCH_JTAG_TRST#
<6>
CFG2
CFG3
RC114
2
0_0402_5%
2
PCH_JTAG_TDO
0_0402_5%
HASWELL_MCP_E
UC1B
CPU_DETECT#
<37>
PECI_EC
CPU_DETECT#
H_CATERR#
PECI_EC
D61
K61
N62
H_PROCHOT#_R
56_0402_5%
K63
PROC_DETECT
CATERR
PECI
MISC
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
1
1
2
RC117
RC115
10K_0402_5%
2
H_PROCHOT#
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
<18>
CFG10
CFG11
<13>
<13>
CFG19
CFG18
CFG19
CFG18
<13>
<13>
CFG12
CFG13
CFG12
CFG13
<13>
<13>
CFG14
CFG15
CFG14
CFG15
<13>
<13>
2
RC109
XDP@
1
XDP_RST#_R
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP
1
CFG3_R
RC99
XDP@
XDP_DBRESET#
DDR3_DRAMRST#_CPU
<18>
DDR_PG_CTRL
C61
AU60
AV60
AU61
AV15
AV61
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
THERMAL
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3
J62
K62
E60
E61
E59
F63
F62
CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
100_0402_1%
1 RC125
SM_RCOMP0
2
1 RC129
SM_RCOMP1
2
1 RC133
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
1
2
B
@ RC280
+3.3V_RUN
1 RC116
1
+1.05V_RUN
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T122
T126
T129
T130
T131
T132
2
1 @ RC118
2
1 @ RC119
2
1 @ RC120
2
1
RC122
2
CPU_XDP_TCLK
51_0402_1%
2
CPU_XDP_TRST#
51_0402_1%
1
RC127
CPU_XDP_TMS
51_0402_1%
CPU_XDP_TDI
51_0402_1%
CPU_XDP_PREQ#
51_0402_1%
CPU_XDP_TDO
51_0402_1%
@
@
@
@
@
@
1 @ RC131
A
H_CPUPWRGD
2
121_0402_1%
+1.05V_RUN
1
2
XDP_DBRESET#
1K_0402_5%
Rev1p2
2 OF 19
200_0402_1%
2
CFG3
1K_0402_5%
Place near JXDP1.47
A
DDR3 COMPENSATION SIGNALS
PCH_PLTRST#_EC
1K_0402_5%
2
@ CC48
0.1U_0402_25V6
2
<37,46,47,48>
CFG10
CFG11
<13>
<13>
<13>
<13>
Place near JXDP1.48
SYS_PWROK_XDP
H_CPUPWRGD
CFG8
CFG9
CC68 XDP@
0.1U_0402_25V6
1
H_PROCHOT#
<36>
CFG17
CFG16
CFG8
CFG9
2
TDO_XDP
51_0402_1%
XDP@
RC102
1K_0402_5%
1
CPU_XDP_TCLK
RC124 @
@
CC149
22P_0402_50V8J
EMI request add
CFG17
CFG16
+3.3V_ALW_PCH
1
TDI_XDP_R
RC104 @
PCH_JTAG_TCK 2
0_0402_5%
1
GND0
GND1
OBSFN_A0
OBSFN_C0
OBSFN_A1
OBSFN_C1
GND2
GND3
OBSDATA_A0
OBSDATA_C0
OBSDATA_A1
OBSDATA_C1
GND4
GND5
OBSDATA_A2
OBSDATA_C2
OBSDATA_A3
OBSDATA_C3
GND6
GND7
OBSFN_B0
OBSFN_D0
OBSFN_B1
OBSFN_D1
GND8
GND9
OBSDATA_B0
OBSDATA_D0
OBSDATA_B1
OBSDATA_D1
GND10
GND11
OBSDATA_B2
OBSDATA_D2
OBSDATA_B3
OBSDATA_D3
GND12
GND13
PWRGOOD/HOOK0
ITPCLK/HOOK4
HOOK1
ITPCLK#/HOOK5
VCC_OBS_AB
VCC_OBS_CD
HOOK2
RESET#/HOOK6
HOOK3
DBR#/HOOK7
GND14
GND15
SDA
TD0
SCL
TRST#
TCK1
TDI
TCK0
TMS
GND16
GND17
SAMTE_BSH-030-01-L-D-A CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
TDO_XDP
RC123 @
2
1
<6>
<13>
<13>
CFG0
CFG1
XDP_OBS0_R
XDP_OBS1_R
CPU_XDP_TRST#
7
GND
GND PAD
+1.05V_VCCST
CFG0
CFG1
Place near JXDP1
4B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
CPU_XDP_PREQ#
CPU_XDP_PRDY#
<13>
<13>
3OE
12
RUNPWROK
6
2B
+1.05V_RUN
JXDP1
2OE
9
TRST#_XDP
RUNPWROK
2A
4
2 TMS_XDP
0_0402_5%
RUNPWROK
<36,37>
1OE
5
RUNPWROK
1
RC101
XDP@
CPU_XDP_TDO
2
1
RC96
XDP@
3
1B
2
PCH_JTAG_TDI
1A
1
RUNPWROK
<6>
+1.05V_RUN
VCC
2
1
2 TDO_XDP
0_0402_5%
@ CC11
0.1U_0402_25V6
1
RC95
XDP@
PCH_JTAG_TDO
@ CC10
0.1U_0402_25V6
<6>
C
+1.05V_RUN
0.1U_0402_25V6
1
CC41 XDP@
1
1
2
2
C
@
CC90
100P_0402_50V8J
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
ESD request add
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
CPU (4/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
9
of
58
5
4
3
2
1
D
D
HASWELL_MCP_E
UC1A
+3.3V_RUN
1
2
1
2
1
2
1
2
1
2
CONTACTLESS_DET#
10K_0402_5%
DGPU_PWROK
10K_0402_5%
TOUCHPAD_INTR#
10K_0402_5%
PIRQC#
10K_0402_5%
PIRQD#
10K_0402_5%
RC137
C
RC138
RC140
RC146
RC148
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
C54
C55
B58
C58
B55
A55
A57
B57
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
C51
C50
C53
B54
C49
B50
A53
B53
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
COMPENSATION PU FOR eDP
<22>
<22>
<22>
<22>
+VCCIOA_OUT
C47
C46
A49
B49
2
EDP_COMP
24.9_0402_1%
A45
B45
EDP_CPU_AUX#
EDP_CPU_AUX
D20
A43
EDP_COMP
EDP_CPU_AUX#
EDP_CPU_AUX
1
RC134
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
<22>
<22>
C
Rev1p2
1 OF 19
+3.3V_RUN
1
2
@ RC152
2
1
@ RC154
ENVDD_PCH
100K_0402_5%
CODEC_IRQ
1K_0402_5%
<25>
2 PIRQC#
0_0402_5%
<29>
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
CONTACTLESS_DET#
HDD_FALL_INT
1
R494
RP3
1
2
3
4
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
<22>
<22>
<22,36>
1
@ R495
HASWELL_MCP_E
UC1I
2 PIRQD#
0_0402_5%
@ T13
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
PIRQC#
PIRQD#
PAD~D
TOUCHPAD_INTR#
<12>
TOUCH_RST_N_GYRO_INT1
CODEC_IRQ
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
DISPLAY
GPIO
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
C5
B6
B5
A6
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
C8
A8
D6
DPB_HPD
DPC_HPD
Rev1p2
2
9 OF 19
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
<23>
<23>
<27>
<27>
CPU_DPC_AUX#
CPU_DPC_AUX
DPB_HPD
DPC_HPD
EDP_CPU_HPD
2.2K_0804_8P4R_5%
2
CPU_DPB_AUX#
100K_0402_5%
2
CPU_DPC_AUX#
100K_0402_5%
1
2
100K_0402_5%
2
CPU_DPB_AUX
100K_0402_5%
2
CPU_DPC_AUX
100K_0402_5%
1
RC147
1
RC149
<27>
<27>
<23>
<27>
<22>
DPC_HPD
RC151
1
RC153
1
RC155
B
RC158
100K_0402_5%
1
B
B8
A9
C6
8
7
6
5
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (5/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
10
of
58
5
4
3
2
1
D
D
HASWELL_MCP_E
UC1K
<30>
<30>
PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5
PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5
PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5
F10
E10
PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
C
E6
F6
B22
A21
10/100/1G LAN --->
WLAN (Mini Card 2)--->
<28>
<28>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
<28>
<28>
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
<31>
<31>
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
<31>
<31>
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
Ext USB Port 2 <----
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
G11
F11
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
C29
B30
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
F13
G13
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
B29
A29
<32>
<32>
USB3RN3
USB3RP3
<32>
<32>
USB3TN3
USB3TP3
G17
F17
C30
C31
F15
G15
B31
A31
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN1
USB3RP1
PCIe
USB
USB3TN1
USB3TP1
PERN4
PERP4
USB3RN2
USB3RP2
PETN4
PETP4
USB3TN2
USB3TP2
1
1
AR8
AP8
USBP2USBP2+
AR10
AT10
USBP3USBP3+
AM15
AL15
USBP4USBP4+
AM13
AN13
USBP5USBP5+
AP11
AN11
USBP6USBP6+
AR13
AP13
USBP7USBP7+
G20
H20
C33
B34
E18
F18
B33
A33
-----> Ext Port 1 and DOCK2 (USB SW)
USBP0USBP0+
<33>
<33>
USBP1USBP1+
<35>
<35>
----->Ext Port 2 IO/B
USBP2USBP2+
<31>
<31>
----->WLAN/BT
USBP3USBP3+
<22>
<22>
----->Camera
USBP4USBP4+
<29>
<29>
----->USH
USBP5USBP5+
<32>
<32>
----->Ext Port 3 and DOCK1(USB SW)
USBP6USBP6+
<31>
<31>
----->WWAN
USBP7USBP7+
<22>
<22>
----->Touch
USB3RN1
USB3RP1
<35>
<35>
USB3TN1
USB3TP1
<35>
<35>
USB3RN2
USB3RP2
<33>
<33>
USB3TN2
USB3TP2
<33>
<33>
C
----->Ext USB3 Port 3 IO/B
----->Ext USB3 Port 1
PETN1/USB3TN3
PETP1/USB3TP3
USBRBIAS
USBRBIAS
RSVD
RSVD
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBRBIAS
PAD~D T14@
PAD~D T15@
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
USBRBIAS
<33>
<35>
<12,33>
2
RC161
@ RC163
USBP1USBP1+
RC159
22.6_0402_1%
+PCH_AUSB3PLL
E15
E13
A27
B27
USBP0USBP0+
AR7
AT7
PERN1/USB3RN3
PERP1/USB3RP3
B
@ T16 PAD~D
@ T17 PAD~D
2 3.01K_0402_1% PCH_PCIE_RCOMP
2 0_0402_5%
PCH_PCIE_IREF
AN8
AM8
1
<30>
<30>
MMI -->
B
Rev1p2
11 OF 19
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
+3.3V_ALW_PCH
1
USB_OC0#
10K_0402_5%
1
USB_OC1#
10K_0402_5%
1
USB_OC3#
10K_0402_5%
2
RC160
2
RC165
2
RC166
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (6/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
11
of
58
5
4
3
2
1
+PCH_VCCDSW3_3
D
LAN_WAKE#
<28,37>
+3.3V_RUN
2
1
2
1
MPHYP_PWR_EN
100K_0402_5%
SIO_EXT_SCI#
100K_0402_5%
RC170
RC199
ESD request add
+PCH_VCCDSW3_3
<28>
2
1
RC197
<9>
PCH_AUDIO_EN
<36>
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
<28>
PM_LANPHY_ENABLE
10K_0402_5%
<37>
<20>
<20>
<30>
<30>
+3.3V_ALW_PCH
2
1
2
1
2
1
1
2
RC175
RC200
RC171
RC230
5
6
7
8
NFC_DET#
MEDIACARD_IRQ#
@ T140 PAD~D
@ T141 PAD~D
<22>
TOUCH_PANEL_INTR#
<39>
MPHYP_PWR_EN
<38>
KB_DET#
@ T138 PAD~D
<22>
3.3V_CAM_EN#
<37>
SIO_EXT_SMI#
USB_OC2#
<11,33>
<31>
<25>
<37>
RP14
5
6
7
8
NFC_IRQ
<30>
10K_8P4R_5%
4
3
2
1
EC_WAKE#
MEDIACARD_RST#
MEDIACARD_PWREN
SIO_EXT_SMI#
SLATE_MODE_R
MEDIACARD_IRQ#
PCH_GPIO9
SIO_EXT_WAKE#
KB_DET#
PCH_GPIO73
PCH_GPIO15
PCH_GPIO17
EC_WAKE#
PCH_NFC_RST
NFC_IRQ
<20>
MEDIACARD_PWREN
10K_0402_5%
PCH_GPIO44
10K_0402_5%
MEDIACARD_RST#
10K_0402_5%
PCH_GPIO46
10K_0402_5%
RP13
4
3
2
1
LAN_RST#
@ T139 PAD~D
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
PCH_AUDIO_EN
SIO_EXT_WAKE#
@ T137 PAD~D
mSATA_DEVSLP
HDD_DEVSLP
SIO_EXT_SCI#
<26>
SPKR
MEDIACARD_RST#
SLATE_MODE_R
PCH_GPIO44
PCH_GPIO48
PCH_GPIO49
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO46
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2
PCH_GPIO9
PCH_GPIO10
SIO_EXT_SCI#
SPKR
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
GPIO
LPIO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
@ 0_0402_5%2
H_THERMTRIP#_R
SIO_RCIN#
IRQ_SERIRQ
PCH_OPI_COMP
SIO_RCIN#
IRQ_SERIRQ
1 RC172
H_THERMTRIP#
<37>
<37>
<29,36,37>
@ T18 PAD~D
@ T19 PAD~D
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
PCH_GPIO87
3.3V_TP_EN
1
D
R24
RC183
1
RC282
1
RC185
1
RC193
1
RC284
1
RC285
1
RC289
1
RC290
1
RC291
1
RC294
RP4
3.3V_TS_EN
<22>
3.3V_HDD_EN
<28>
CPPE#
<31>
CPUSB#
<31>
CPPE#
CPUSB#
2
FFS_INT2
100K_0402_5%
2
USH_DET#
10K_0402_5%
2
CPPE#
100K_0402_5%
CAM_MIC_CBL_DET#2
10K_0402_5%
2
TPM_ID0
10K_0402_5%
2
TPM_ID1
20K_0402_5%
SLP_ME_CSW_DEV#2
10K_0402_5%
2
PCH_GPIO83
10K_0402_5%
2
PCH_GPIO84
10K_0402_5%
2
3.3V_TS_EN
10K_0402_5%
5
6
7
8
PCH_GPIO85
3.3V_TP_EN
TOUCH_PANEL_INTR#
<10>
TOUCH_RST_N_GYRO_INT1
4
3
2
1
C
10K_8P4R_5%
FFS_INT2
LCD_CBL_DET#
RP5
FFS_INT2
<25>
LCD_CBL_DET#
<22>
I2C0_SDA
I2C0_SCL
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
TPM_ID0
TPM_ID1
SLP_ME_CSW_DEV#
5
6
7
8
3.3V_HDD_EN
LCD_CBL_DET#
CPUSB#
<28,7>
LANCLK_REQ#
4
3
2
1
10K_8P4R_5%
USH_DET#
<29>
CAM_MIC_CBL_DET#
SLP_ME_CSW_DEV#
RP6
<22>
5
6
7
8
SIO_RCIN#
<31,7>
<31,7>
<36>
<31,6>
MINI1CLK_REQ#
MINI2CLK_REQ#
MPCIE_RST#
Rev1p2
10 OF 19
<7>
D60
V4
T4
AW15
AF20
AB21
1
+3.3V_RUN
HASWELL_MCP_E
UC1J
2
H_THERMTRIP#
1K_0402_5%
@
CC91
100P_0402_50V8J
2
2
RC177 @
1
1 EC_WAKE#
1
10K_0402_5% 0_0402_5%
RC206
C
+1.05V_VCCST
H_THERMTRIP#_R
2
4
3
2
1
10K_8P4R_5%
10K_8P4R_5%
RP7
2
1
2
1
2
1
RC211
RC210
@ RC169
3.3V_CAM_EN#
100K_0402_5%
NFC_IRQ
100K_0402_5%
MPHYP_PWR_EN
10K_0402_5%
I2C1_SDA_TCH_PAD @ RC174
2
1 0_0402_5%
I2C1_SCL_TCH_PAD @ RC176
2
1 0_0402_5%
I2C1_SDA_VMM
I2C1_SCL_VMM
I2C1_SDA_TCH_PAD
+3.3V_RUN
I2C1_SCL_TCH_PAD
+3.3V_RUN
1
2
3
4
I2C0_SDA
I2C0_SCL
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
<21>
<21>
2.2K_0804_8P4R_5%
<38>
<38>
RP11
B
5
6
7
8
1
@
2
1
2
2
1
1
2
@ RC287
1K_0402_5%
@ RC288
1K_0402_5%
TOP-BLOCK SWAP OVERRIDE
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITY
HIGH depop RC288
HIGH
LOW(DEFAULT)
HIGH
LOW(DEFAULT)
LOW pop RC288 (DEFAULT)
ENABLE
DISABLE
B
4
3
2
1
10K_8P4R_5%
PCH_GPIO15
LPC
SPI
PCH_GPIO87
1
PCH_OPI_COMP
49.9_0402_1%
PCH_GPIO83
100_0402_5%
@ RC222
1K_0402_5%
BBS_BIT
CLKRUN#
PCH_GPIO36
+3.3V_RUN
RC190
1K_0402_5%
PCH_GPIO66
1
2
2
RC218
10K_0402_5%
@ RC283
1K_0402_5%
1
IRQ_SERIRQ
<29,36,37,9>
<6>
+3.3V_ALW_PCH
8
7
6
5
2
RC168
2
7@ RC292
1
SPKR
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (7/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
12
of
58
5
4
3
2
1
D
D
CFG STRAPS for CPU
UC1S
CFG0
CFG8
CFG9
CFG10
AA62
U63
AA61
U62
V63
CFG_RCOMP
A5
@ T33 PAD~D
@ T35
@ T37
@ T38
@ T39
E1
D1
J20
H18
B12
PAD~D
PAD~D
PAD~D
PAD~D
TDI_IREF
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RESERVED
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
19 OF 19
AV63
AU63
PAD~D T20@
PAD~D T21@
C63
C62
B43
PAD~D T22@
PAD~D T23@
PAD~D T24@
A51
B51
PAD~D T25@
PAD~D T26@
L60
PAD~D T27@
N60
PAD~D T28@
W23
Y22
AY15 PROC_OPI_RCOMP
PAD~D T29@
PAD~D T30@
2
CFG16
CFG18
CFG17
CFG19
CFG4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
C
CFG1
AV62
D58
PAD~D T31
PAD~D T32
@
@
PAD~D T34
PAD~D T36
@
@
P22
N21
P20
R20
PCH/PCH LESS MODE SELECTION
Rev1p2
CFG1
2
RC235
1
RC236
1
2
CFG_RCOMP
49.9_0402_1%
TDI_IREF
8.2K_0402_1%
1:(Default) Normal Operation; No stall
0:Lane Reversed
1
<9>
<9>
<9>
<9>
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG0
CFG1
@ RC233
1K_0402_1%
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
2
C
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
@ RC232
1K_0402_1%
1
HASWELL_MCP_E
PROC_OPI_RCOMP
49.9_0402_1%
1
1:(Default) Normal Operation
0:Lane Reversed
2
RC237
B
B
CFG9
CFG8
CFG4
2
1
1
2
2
2
ALLOW THE USE OF NOA ON LOCKED UNITS
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
CFG8
units
0:
Enable Noa will be available pegardless of
the locking of the unit
RC238
1K_0402_1%
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: VRS support SVID protocol are present
0:No VR support SVID is present
CFG9
The chip will not generate(OR Respond to)
SVID activity
@ RC241
1K_0402_1%
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING
RESET
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
@ RC240
1K_0402_1%
@ RC239
1K_0402_1%
1
1
CFG10
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (8/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
13
of
58
5
4
3
2
1
D
D
2
1
1
RC254 @
0_0402_5%
HASWELL_MCP_E
UC1Q
AY2
DC_TEST_AY2_AW2
AY3
DC_TEST_AY3_AW3
AY60
DC_TEST_AY60
DC_TEST_AY61_AW61 AY61
DC_TEST_AY62_AW62 AY62
B2
TP_DC_TEST_B2
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
B63
DC_TEST_B62_B63
C1
C2
DC_TEST_C1_C2
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2
C
A3
A4
DC_TEST_A3_B3
DC_TEST_A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63
2
2
0_0402_5%
2
0_0402_5%
1
@ RC266
1
@ RC268
4
C
3
2
0_0402_5%
1
RC269 @
Package Daisy Chain:
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R
@T50
@T52
@T54
@T55
B
@T58
@T60
@T62
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
RSVD_F22
RSVD_H22
RSVD_J21
AT2
AU44
AV44
D15
F22
H22
J21
HASWELL_MCP_E
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
18 OF 19
N23
R23
T23
U10
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
PAD~D
PAD~D
PAD~D
PAD~D
T48
T49
T51
T53
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T56
T57
T59
T61
T63
T64
T65
@
@
@
@
B
@
@
@
@
@
@
@
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (9/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
14
of
58
5
4
3
ESD test request
+VCC_CORE
2
1
+1.35V_MEM
EMC@CC57
EMC@
CC57
1
+1.05V_RUN
2
+1.05V_RUN
+VCCIO_OUT
+1.35V_MEM
VDDQ DECOUPLING
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
CC21
10U_0603_6.3V6M
1
2
1
2
PAD~D
PAD~D
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
RESET_OUT#
1
0_0402_5%
2
3
VCC
A
4
Y
1
@ CC24
2
2
0.1U_0402_25V6
1
2
@ RC263
NC
5
RC243
1K_0402_5%
+3.3V_ALW
UC4
1
H_VCCST_PWRGD
@ T68
@ T69
GND
+VCC_CORE
PAD~D
PAD~D
VCCSENSE
74AUP1G07GW_TSSOP5
@ T70 PAD~D
+VCCIO_OUT
+VCCIOA_OUT
@ T71 PAD~D
@ T72 PAD~D
@ T73 PAD~D
+1.05V_VCCST
<46>
2
RC244
75_0402_1%
1
SVID ALERT
1
<9>
<46>
<46>
@ RC245
@ RC246
@ RC247
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
1
1
1
CPU_PWR_DEBUG#
@ T74
@ T75
@ T76
@ T77
@ T78
@ T79
@ T80
@ T81
@ T82
@ T83
@ T84
@ T85
@ T86
VIDSOUT
1
2
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
+1.05V_VCCST
+VCC_CORE
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
C
B
Rev1p2
+1.05V_VCCST
@ PJP11
2
1
2
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
A
CC26
1U_0402_6.3V6K
PAD-OPEN1x1m
1
VCCSENSE
@
1
CC50
22U_0603_6.3V6M
VCCSENSE
E63
AB23
A59
E20
AD23
AA23
AE59
HASWELL_MCP_E
12 OF 19
+1.05V_RUN
2
2
RC250
100_0402_1%
1
VCC_SENSE
+VCC_CORE
F59
N58
AC58
H_CPU_SVIDALRT# L62
N63
VIDSCLK
L63
VIDSOUT
B59
VCCST_PWRGD
F60
VR_EN
C59
VR_READY
check
<9>
H_CPU_SVIDALRT#
RC248
CAD Note: Place the PU resistors close to CPU
RC249close to CPU 300 - 1500mils
VIDSOUT
VIDSCLK
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
+1.05V_VCCST
RC249
110_0402_1%
SVID DATA
CAD Note: Place the PU resistors close to CPU
RC224 close to CPU 300 1500mils
2
43_0402_5%
VIDALERT_N
<46>
@ CC20
10U_0603_6.3V6M
@ T66
+1.35V_MEM @ T67
H_VR_READY
RC256
C
<46>
CC19
10U_0603_6.3V6M
UC1L
L59
J58
+1.05V_VCCST
B
CC18
10U_0603_6.3V6M
+VCC_CORE
@ RC259
10K_0402_5%
1
+3.3V_RUN
@ RC255
10K_0402_5%
2
H_VR_EN
10K_0402_5%
<46>
D
@ RC258
10K_0402_5%
+1.05V_VCCST
<37,9>
@ CC17
10U_0603_6.3V6M
CPU_PWR_DEBUG#
CC16
10U_0603_6.3V6M
0_0603_5%
CC13
2.2U_0402_6.3V6M
@RC242
@
RC242
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
CC12
2.2U_0402_6.3V6M
2 VCCST_PWRGD
100P_0402_50V8J
@ CC52
2.2U_0402_6.3V6M
1
@ CC22
1
@ CC81
2.2U_0402_6.3V6M
D
2
RC253
150_0402_1%
1
22U_0603_6.3V6M
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (10/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
15
of
58
5
4
3
+1.05V_M
2
ESD test request
+1.05V_RUN
+1.05V_RUN
+1.05V_MODPHY
+VCC_CORE
+1.05V_MODPHY_PCH
1
2
1
2
1
2
1
1
2
2
+
@
CC72
330U_D3_2.5VY_R6M
+
@
CC71
330U_D3_2.5VY_R6M
+
@ CC73
330U_D3_2.5VY_R6M
CC29
1U_0402_6.3V6K
CC29 place near K9;
CC27 place near L10
CC74 place near M9
CC27
1U_0402_6.3V6K
1
1
@ CC74
1U_0402_6.3V6K
@ RC262
2
0_0805_5%
2
1
D
1
EMC@ CC83
1
+1.05V_RUN EMC@ CC84
1
EMC@ CC85
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
+3.3V_RUN
2
D
22U_0603_6.3V6M
+RTC_CELL
DCPSUS4
AB8
+PCH_DCPSUS4
+1.05V_RUN
AC20
AG16
AG17
1
2
2
1
1
2
1
1
2
2
1
RC272 @
B
CC54 place near AD10
+PCH_VCCACLKPLL
0_0402_5%
+1.05V_RUN
LC6
1
2
2.2UH_LQM2MPN2R2NG0L_30%
1
2
1
2
1
1
+1.05V_M
@ LC4
2
1
2.2UH_LQM2MPN2R2NG0L_30%
@ CC75
100U_1206_6.3V6M
@ CC53
1U_0402_6.3V6K
2
CC58 place near A20
CC58
1U_0402_6.3V6K
@ CC32
1U_0402_6.3V6K
CC32 place near AH10
+PCH_DCPSUS4
CC78
100U_1206_6.3V6M
2 0_0402_5%
2
+3.3V_ALW
@ RC267 1
+1.05V_M
2
0_0402_5%
+PCH_VCCDSW3_3
2
1
@ RC265
CC30 place near AH11
+PCH_DCPSUS1
1
1
CC51 place near J18
2
1
2
2
LC3
1
2
2.2UH_LQM2MPN2R2NG0L_30%
2
1
1
RC264 @
0_0402_5%
@ CC54
1U_0402_6.3V6K
+3.3V_ALW_PCH
2
0_0402_5%
CC51
1U_0402_6.3V6K
2
Rev1p2
1
RC261 @
+PCH_VCC1P05
CC79
100U_1206_6.3V6M
@ CC62
10U_0603_6.3V6M
@ CC61
1U_0402_6.3V6K
@ CC66
1U_0402_6.3V6K
B
CC66 place near AH13
CC61 CC62 place near J13
1
+1.05V_RUN
1
2
0_0603_5%
1
1
@ RC276
13 OF 19
2
+PCH_DCPSUS
2
+1.05V_M
+3.3V_ALW_PCH
2
+3.3V_ALW
CC60 place near AG16
CC30
1U_0402_6.3V6K
RSVD
VCC1_05
VCC1_05
+PCH_RTC_VCCSUS3_3
CC60
1U_0402_6.3V6K
USB2
2
1
LPT LP POWER
SUS OSCILLATOR
2
1
CC45 place near U8
C
1
U8
T9
2
VCCSDIO
VCCSDIO
@
1
2
SDIO/PLSS
2
CC59 place near K14
1
+3.3V_ALW_PCH
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
CC65 place near AG19
2
1
1
2
2
2
1
2
1
1
2
1
1
2
1
2
+PCH_VCCACLKPLL
CC63 close to Pin J17
CC64 close to Pin R21
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
1
5.11_0402_1%
+3.3V_RUN
+1.5V_THERMAL
CC45
1U_0402_6.3V6K
1
J15
K14
K16
+PCH_DCPSUS1
CC59
0.1U_0402_10V7K
VCCTS1_5
VCC3_3
VCC3_3
CC46 CC47 place near AE9
2
+PCH_VCCDSW
RC275
CC65
1U_0402_6.3V6K
GPIO/LCC
+PCH_VCCDSW
+3.3V_RUN
+PCH_VCC1P05
CC64
1U_0402_6.3V6K
2
CORE
+1.05V_M
+PCH_VCCDSW_R
VRM/USB2/AZALIA
+1.05V_RUN
CC34 and CC33 place near
J11; CC37 place near AE8
CC34
10U_0603_6.3V6M
AXALIA/HDA
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
CC33
1U_0402_6.3V6K
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
+1.05V_M
CC37
1U_0402_6.3V6K
DCPSUS2
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
THERMAL SENSOR
+1.05V_RUN
CC63
1U_0402_6.3V6K
CC56
1U_0402_6.3V6K
CC55
100U_1206_6.3V6M
1
2
2.2UH_LQM2MPN2R2NG0L_30%
CC56 place near AA21
CC43 place near V8
VCCHDA
AG14
AG13
USB3
CC47
22U_0805_6.3V6M
+V1.05S_APLLOPI
LC5
+PCH_VCCDSW3_3
AC9
AA9
AH10
V8
W9
DCPSUS3
CC46
1U_0402_6.3V6K
+3.3V_RUN
CC43
22U_0603_6.3V6M
+1.05V_RUN
AH13
CC28 place near AC9
C
J13
AH14
+3.3V_ALW_PCH
CC28
22U_0603_6.3V6M
CC44
0.1U_0402_10V7K
2
+PCH_DCPSUS
CC44 place near AH14
CC49
22U_0603_6.3V6M
CC49 place near B11
CC77
22U_0603_6.3V6M
LC2
1
2
2.2UH_LQM2MPN2R2NG0L_30%
+3.3V_ALW_PCH
1
+PCH_ASATA3PLL
CC40 place near Y8
1
VCCASW
VCCASW
+1.05V_MODPHY
+3.3V_M
Y8
@
VCCSPI
OPI
AH11
+PCH_RTC_VCCSUS3_3
AG10
AE7 +DCPRRTC 1
2
CC36
0.1U_0402_10V7K
2
SPI
VCCSUS3_3
VCCRTC
DCPRTC
1
RTC
2
RSVD
VCCAPLL
VCCAPLL
mPHY
2
1
2
1
2
1
2
+V1.05S_APLLOPI
Y20
AA21
W21
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
@ CC40
0.1U_0402_10V7K
@ CC31
1U_0402_6.3V6K
CC42
22U_0603_6.3V6M
CC76
22U_0603_6.3V6M
CC42 place near B18
+PCH_AUSB3PLL
+PCH_ASATA3PLL
K9
L10
M9
N8
P9
B18
B11
CC35
1U_0402_6.3V6K
+1.05V_MODPHY_PCH
+1.05V_RUN
CC39
0.1U_0402_10V7K
LC1
1
2
2.2UH_LQM2MPN2R2NG0L_30%
HASWELL_MCP_E
UC1M
CC38
0.1U_0402_10V7K
+PCH_AUSB3PLL
1
CC35,CC38, CC39 place near AG10
+1.05V_MODPHY
CC53 place near AB8
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (11/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
16
of
58
5
4
3
2
1
D
D
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
C
B
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_MCP_E
15 OF 19 Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
UC1P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
C
V58
AH46
V23
E62
AH16
VSSSENSE
<46>
B
VSSSENSE
RC260
1
2
100_0402_1%
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (12/12)
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
17
of
58
5
3
DDR_A_DQS#[0..7]
+DIMM1_VREF_DQ
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
+1.35V_MEM
DDR_A_D27
DDR_A_D26
DDR_A_D45
DDR_A_D40
<19>
DDR3_DRAMRST#
DDR_A_D52
DDR_A_D53
<8>
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
+0.675V_DDR_VTT
1
2
1
2
1
2
1
2
1
2
2
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
1
2
@ RD5
@ RD6
0_0402_5% +3.3V_RUN
0_0402_5%
+0.675V_DDR_VTT
1
2
CD24
0.1U_0402_25V6
@ CD25
2.2U_0402_6.3V6M
A
1
2
2
1
205
G1
G2
1
2
DDR_CS0_DIMMA#
M_ODT0
DDR_CS0_DIMMA#
M_ODT1
<8>
+SM_VREF_CA_DIMM1
+SM_VREF_CA_DIMM
1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
2
0_0402_5%
@ RD12
+5V_ALW
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR3L SODIMM ODT GENERATION
+1.35V_MEM
1
3
1
R29
1
R30
1
0.675V_DDR_VTT_ON
R31
1
DDR_A_D37
DDR_A_D32
R33
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
B
QD1
BSS138-G_SOT23-3
2
M_ODT0
66.5_0402_1%
2
M_ODT1
66.5_0402_1%
2
66.5_0402_1%
2
66.5_0402_1%
M_ODT2
<19>
M_ODT3
<19>
@ R32
2M_0402_5%
DDR_A_DQS#4
DDR_A_DQS4
<8>
<8>
R28
220K_0402_5%
CD31
10U_0603_6.3V6M
CD30
10U_0603_6.3V6M
CD29
0.1U_0402_25V6
CD28
0.1U_0402_25V6
CD27
0.1U_0402_25V6
CD26
0.1U_0402_25V6
1
DDR_A_D2
DDR_A_D6
<8>
<8>
DDR_A_BS1
DDR_A_RAS#
CD12
2.2U_0402_6.3V6M
DDR_A_DQS#0
DDR_A_DQS0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
CD13
0.1U_0402_25V6
DDR_A_D0
DDR_A_D1
M_CLK_DDR1
M_CLK_DDR#1
D
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA10
DDR_A_BS0
DDR_A_MA2
DDR_A_MA0
2
G
<8>
<8>
<8>
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA6
DDR_A_MA4
1
Layout Note:
Place near
JDIMM1.203,204
M_CLK_DDR0
M_CLK_DDR#0
2
2_0402_1%
RC173
DDR_A_MA11
DDR_A_MA7
2
<8>
<8>
1
DDR_A_MA15
DDR_A_MA14
C
+SM_VREF_DQ0
RC195
24.9_0402_1%
DDR_A_MA3
DDR_A_MA1
<8>
2
DDR_A_MA8
DDR_A_MA5
DDR_CKE1_DIMMA
1
DDR_A_MA12
DDR_A_MA9
DDR_CKE1_DIMMA
1
DDR_A_BS2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
2
DDR_A_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
1
<8>
DDR_CKE0_DIMMA
<9>
+1.35V_MEM
DDR_A_D54
DDR_A_D55
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CD22
330U_D3_2.5VY_R6M
CD21
10U_0603_6.3V6M
CD20
10U_0603_6.3V6M
CD19
10U_0603_6.3V6M
@ CD18
10U_0603_6.3V6M
CD17
10U_0603_6.3V6M
CD16
10U_0603_6.3V6M
@ CD15
10U_0603_6.3V6M
CD14
10U_0603_6.3V6M
+
DDR_CKE0_DIMMA
DDR3_DRAMRST#_CPU
0_0402_5%
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_A_DQS#6
DDR_A_DQS6
+SM_VREF_DQ0_DIMM1
<8>
2
DDR_A_D42
DDR_A_D46
C
B
1
@ RC279
CC70
0.022U_0402_16V7K
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR3_DRAMRST#
RC221
1.8K_0402_1%
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_A_D25
DDR_A_D24
RC217
1.8K_0402_1%
DDR_A_D49
DDR_A_D48
DDR_A_D15
DDR_A_D11
1
1
2
1
2
1
2
1
2
1
2
2
1
2
CD11
1U_0402_6.3V6K
CD10
1U_0402_6.3V6K
CD9
1U_0402_6.3V6K
CD8
1U_0402_6.3V6K
CD7
1U_0402_6.3V6K
CD6
1U_0402_6.3V6K
CD5
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
1
DDR_A_D44
DDR_A_D41
+1.35V_MEM
2
+1.35V_MEM
D
DDR_A_DQS#1
DDR_A_DQS1
@ CD3
0.1U_0402_25V6
DDR_A_D30
DDR_A_D31
DDR_A_D9
DDR_A_D12
1
DDR_A_DQS#3
DDR_A_DQS3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
DDR_A_D29
DDR_A_D28
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
1
DDR_A_D14
DDR_A_D10
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
1
2
DDR_A_D13
DDR_A_D8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
RD3
470_0402_5%
Layout Note:
Place near JDIMM1
CD2
0.1U_0402_25V6
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
CD1
2.2U_0402_6.3V6M
0_0402_5%
1
2
2
1
D
1
+1.35V_MEM
JDIMM1
DDR_A_MA[0..15]
@ RD1
2
H=4mm
Reverse Type
+1.35V_MEM
1
S
<8>
+SM_VREF_DQ0_DIMM1
1
DDR_A_DQS[0..7]
2
2
DDR_A_D[0..63]
<8>
1
<8>
2
<8>
4
+1.35V_MEM
DDR_A_DQS#7
DDR_A_DQS7
U5
1
DDR_A_D56
DDR_A_D57
<9>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
DDR_PG_CTRL
<19,25,31,7,9>
<19,25,31,7,9>
+0.675V_DDR_VTT
2
3
NC
VCC
A
Y
5
4
1
@ CD23
2
0.1U_0402_25V6
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
<43>
GND
74AUP1G07GW_TSSOP5
206
A
FOX_AS0A621-U4R6-7H
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DDR3L
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
18
of
58
4
3
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
<8>
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
B
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
+0.675V_DDR_VTT
1
2
1
2
1
2
1
2
1
2
2
DDR_B_D36
DDR_B_D33
CD59
10U_0603_6.3V6M
CD58
10U_0603_6.3V6M
CD57
0.1U_0402_25V6
CD56
0.1U_0402_25V6
CD55
0.1U_0402_25V6
CD54
0.1U_0402_25V6
1
DDR_B_D22
DDR_B_D23
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+3.3V_RUN
+3.3V_RUN
+0.675V_DDR_VTT
2
1
CD60
0.1U_0402_25V6
2
205
@ CD61
2.2U_0402_6.3V6M
@ RD11
0_0402_5%
A
2
0_0402_5%
1
1
1
2
@ RD10
G1
G2
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
<8>
<8>
<8>
<8>
DDR_CS2_DIMMB#
M_ODT2
<18>
M_ODT3
1
2
+SM_VREF_CA_DIMM
0_0402_5%
DDR_B_D5
DDR_B_D0
2_0402_1%
<8>
<18>
+SM_VREF_CA_DIMM2
1
DDR_B_D2
DDR_B_D6
2
RC126
DDR_B_BS1
DDR_B_RAS#
1
+SM_VREF_DQ1
1
M_CLK_DDR3
M_CLK_DDR#3
2
1
2
1
2
+SM_VREF_DQ1_DIMM2
DDR_B_MA6
DDR_B_MA4
2
@ RD13
CD43
2.2U_0402_6.3V6M
Layout Note:
Place near
JDIMM2.203,204
C
+1.35V_MEM
DDR_B_MA11
DDR_B_MA7
CD44
0.1U_0402_25V6
DDR_B_D4
DDR_B_D1
<8>
RC128
24.9_0402_1%
<8>
<8>
<8>
DDR_B_MA10
DDR_B_BS0
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
1
M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE3_DIMMB
2
<8>
<8>
M_CLK_DDR2
M_CLK_DDR#2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D63
DDR_B_D62
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DDR_B_MA3
DDR_B_MA1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_B_DQS#7
DDR_B_DQS7
RC132
1.8K_0402_1%
2
DDR_B_MA8
DDR_B_MA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
2_0402_1%
CC69
0.022U_0402_16V7K
+
CD53
330U_D3_2.5VY_R6M
CD52
10U_0603_6.3V6M
CD51
10U_0603_6.3V6M
CD50
10U_0603_6.3V6M
CD49
10U_0603_6.3V6M
CD48
10U_0603_6.3V6M
@ CD47
10U_0603_6.3V6M
@ CD46
10U_0603_6.3V6M
CD45
10U_0603_6.3V6M
1
DDR_B_MA12
DDR_B_MA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
2
DDR_B_BS2
DDR_B_BS2
1
RC68
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
+SM_VREF_CA
RC130
1.8K_0402_1%
+1.35V_MEM
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<8>
+SM_VREF_CA_DIMM
1
<8>
C
DDR_B_D45
DDR_B_D44
<18>
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CD42
1U_0402_6.3V6K
CD41
1U_0402_6.3V6K
CD40
1U_0402_6.3V6K
CD39
1U_0402_6.3V6K
CD38
1U_0402_6.3V6K
CD37
1U_0402_6.3V6K
CD36
1U_0402_6.3V6K
CD35
1U_0402_6.3V6K
DDR_B_D59
DDR_B_D58
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
RC83
24.9_0402_1%
DDR_B_D56
DDR_B_D57
DDR3_DRAMRST#
1
DDR_B_D46
DDR_B_D42
+1.35V_MEM
DDR_B_D25
DDR_B_D24
RC69
1.8K_0402_1%
DDR_B_DQS#5
DDR_B_DQS5
+1.35V_MEM
CC67
0.022U_0402_16V7K
DDR_B_D40
DDR_B_D41
D
DDR_B_D13
DDR_B_D15
2
DDR_B_D26
DDR_B_D27
DDR_B_DQS#1
DDR_B_DQS1
@ CD34
0.1U_0402_25V6
Layout Note:
Place near JDIMM2
DDR_B_D12
DDR_B_D9
1
DDR_B_DQS#3
DDR_B_DQS3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
RC67
1.8K_0402_1%
DDR_B_D28
DDR_B_D29
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
DDR_B_D10
DDR_B_D11
CONN@
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
DDR_B_MA[0..15]
DDR_B_D8
DDR_B_D14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
1
<8>
0_0402_5%
2
DDR_B_DQS[0..7]
2
1
<8>
+1.35V_MEM
JDIMM2
1
@ RD7
CD33
0.1U_0402_25V6
DDR_B_D[0..63]
CD32
2.2U_0402_6.3V6M
D
+1.35V_MEM
DDR_B_DQS#[0..7]
<8>
2
<8>
1
H=4mm
Reverse Type
+DIMM2_VREF_DQ
1
+SM_VREF_DQ1_DIMM2
2
2
5
B
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<18,25,31,7,9>
<18,25,31,7,9>
+0.675V_DDR_VTT
206
FOX_AS0A621-U4R6-7H
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DDR3L
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
19
of
58
5
4
3
2
1
D
D
+3.3V_ALW_PCH
5
@ C388
2
1
2
O
A
U29
TC7SH08FU_SSOP5~D
C
P
B
4
NFC_RST
G
1
PLTRST_NFC#
PCH_NFC_RST
NFC CONN
3
<9>
<12>
0.1U_0402_25V6
+3.3V_ALW_PCH
@ T87
@ T88
<7>
+3.3V_ALW_PCH
1
1
2
NFC_DET#
100K_0402_5%
2 TP_NFC_RSVD3
0_0402_5%
<12>
NFC_SMBCLK
NFC_SMBDATA
TP_NFC_RSVD3
NFC_IRQ
@ T89
<12>
TP_NFC_SWP_PWR_RSVD
TP_NFC_RSVD4
NFC_RST
PAD~D
NFC_DET#
TP_NFC_RSVD1
NFC_DET#
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
+3.3V_ALW_PCH
2
1
E-T_6705K-Y15N-00L
CONN@
@ C1
0.1U_0402_16V4Z
@ R37
NFC_SMBCLK
NFC_SMBDATA
<7>
R38
PAD~D
PAD~D
C
JNFC1
C1 close to JNFC1
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
NFC
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
20
of
58
2
1
J2
C3
C4
C11
C12
K3
K4
K11
K12
J4
+3.3V_RUN_VDDA
VDDTX0
VDDTX0
VDDTX1
VDDTX1
VDDXT1V
VDDLP
VDDRXA0
VDDRXA1
VDDRXA2
VDDTX0A0
VDDTX0A1
VDDTX0A2
VDDTX1A0
VDDTX1A1
VDDTX1A2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VGA_AVDD
VGA_AVDD
VGA_AVDD
VGA_AVDD
VDDSA
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDXT3V
VSS
VSS
VSS
VSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
1
+3.3V_RUN_VMM
L2
1
2
BLM18AG102SN1D_2P
2
1
2
1
1
2
C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7
2
H5
C10
H12
K6
K7
U6A
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
DP12412_P0
DP12412_N0
DP12412_P1
DP12412_N1
DP12412_P2
DP12412_N2
DP12412_P3
DP12412_N3
DP12412_AUX
DP12412_AUX#
<27>
G6
G7
G8
G9
G10
G11
H4
D4
2
1
2
1
2
1
2
1
2
1
2
1
2
100K_0402_5%
1
1M_0402_5%
1M_0402_5%
1M_0402_5%
150_0402_1%
150_0402_1%
J5
J11
J12
K5
H10
J6
J7
J8
J9
150_0402_1%
VMM_GPIO9
R63
SW_DPC_AUX
R92
SW_DPB_AUX
R47
RED_DOCK
R311
GREEN_DOCK
R312
BLUE_DOCK
R351
LP_CTL
R207 @
1
CLK_27M_IN_R
DOCKED
5
6
7
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
C433
2
470P_0402_50V7K
1
C394
2
470P_0402_50V7K
11
10
9
8
GND
B5
B6
B1
VMM_SPI_CS#
VMM_SPI_CLK
VMM_SPI_DIN
VMM_SPI_DO
A4
B3
B4
A3
2
D14
D13
C14
C13
B14
B13
C1
M12
M13
L3
B2
A5
CLK_27M_IN
K1
CLK_27M_OUT
L1
RxP0
RxN0
RxP1
RxN1
RxP2
RxN2
RxP3
RxN3
RxAUXP
RXAUXN
RxSRCDET
RxHPD
Tx0P0
Tx0N0
Tx0P1
Tx0N1
Tx0P2
Tx0N2
Tx0P3
Tx0N3
CAD0
Tx0AUXP
Tx0AUXN
Tx0DDCSCL
Tx0DDCSDA
Tx0HPD
RSTN_IN
Tx1P0
Tx1N0
Tx1P1
Tx1N1
Tx1P2
Tx1N2
Tx1P3
Tx1N3
CAD1
Tx1AUXP
Tx1AUXN
Tx1DDCSCL
Tx1DDCSDA
Tx1HPD
MESCL
MESDA
ROMWP
SPICS
SPICLK
SPIDI
SPIDO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/INT
GPIO7/MSCL
GPIO8/MSDA
GPIO9
LP_CTL
LP_EN
VGA_VSYNC
VGA_HSYNC
VGA_RP
VGA_RN
VGA_GP
VGA_GN
VGA_BP
VGA_BN
VGA_SCL
VGA_SDA
VGA_DET
VGA_IREF
VGA_NC
RX_STS
TX0_STS
TX1_STS
TX2_STS
SSDA
SSCL
TRSTN
TCK
TMS
TMS2
TDI
TDO
XIN
4
XOUT
B7
A7
B8
A8
B9
A9
B10
A10
A14
B11
SW_DPC_AUX
A11
SW_DPC_AUX#
B12 VMM_DPC_CTRLCLK
A12 VMM_DPC_CTRLDAT
A6
E13
E14
F13
F14
G13
G14
H13
H14
M14
J13
J14
K13
L14
K14
L9
M9
M6
L6
M7
L7
M8
L8
L4
M4
M3
M5
L5
15
1
TPS22966DPUR_SON14_2X3
DPC_LANE_P0
<34>
DPC_LANE_N0
<34>
DPC_LANE_P1
<34>
DPC_LANE_N1
<34>
DPC_LANE_P2
<34>
DPC_LANE_N2
<34>
DPC_LANE_P3
<34>
DPC_LANE_N3
<34>
DPC_CA_DET
<24,34>
SW_DPC_AUX
<24>
SW_DPC_AUX#
<24>
VMM_DPC_CTRLCLK
<24>
VMM_DPC_CTRLDAT
<24>
DPC_DOCK_HPD
<34>
DPB_LANE_P0
<34>
DPB_LANE_N0
<34>
DPB_LANE_P1
<34>
DPB_LANE_N1
<34>
DPB_LANE_P2
<34>
DPB_LANE_N2
<34>
DPB_LANE_P3
<34>
DPB_LANE_N3
<34>
DPB_CA_DET
<24,34>
SW_DPB_AUX
<24>
SW_DPB_AUX#
<24>
VMM_DPB_CTRLCLK
<24>
VMM_DPB_CTRLDAT
<24>
DPB_DOCK_HPD
<34>
SW_DPB_AUX
SW_DPB_AUX#
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
VMM2310_TX2N2
VMM2310_TX2N1
VMM2310_SCL
VMM2310_SDA
VMM2310_HDP
VMM2310_AUXN
VMM2310_AUXP
@ T40 PAD~D
I2C1_SDA_VMM
I2C1_SCL_VMM
<12>
<12>
M11
M10
L12
L13
L11
L10
+3.3V_RUN_VMM
1
SW_DPB_AUX#
1M_0402_5%
1
VMM_GPIO6
2.2K_0402_5%
1
SRCDET
1M_0402_5%
IDTVMM2320BKG8_BGA168
B
VMM2310_TX2P0
VMM2310_TX2N0
VMM2310_TX2N3
A1
A2
+3.3V_RUN_VMM
C392
0.1U_0402_10V7K
GPAD
12
GND
1
CT1
1
ON1
2
4
+5V_ALW
+3.3V_RUN
3
2
0.1U_0402_10V7K
2
DOCKED
1
C432
A13
K2
L2
M1
M2
C43
22P_0402_50V8J
DOCKED
14
13
C42
22P_0402_50V8J
<27,28,32,36>
VOUT1
VOUT1
2
2
VIN1
VIN1
G1
G2
F1
F2
E1
E2
D1
D2
H1
H2
C2
J1
VMM_MESCL
VMM_MESDA
VMM_SPI_WP#
R66
1M_0402_5%
Y1
27MHZ_12PF_X1E000021042600
1
3
IN
OUT
U31
1
2
DP12412_P0_C
DP12412_N0_C
DP12412_P1_C
DP12412_N1_C
DP12412_P2_C
DP12412_N2_C
DP12412_P3_C
DP12412_N3_C
DP12412_AUX_C
DP12412_AUX#_C
SRCDET
DP12412_HPD
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
VMM_GPIO9
LP_CTL
2
0_0402_5%
@ R107
+1.05V_RUN_VMM
C155
C156
C157
C158
C159
C160
C161
C162
C19
C20
PLTRST_VMM2320#
IDTVMM2320BKG8_BGA168
+1.05V_RUN
2
2
2
2
2
2
2
2
2
2
DP12412_HPD
<9>
F8
F9
F10
F11
G4
G5
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
2
C29
0.01U_0402_16V7K
C27
0.1U_0402_25V6
C28
0.01U_0402_16V7K
C26
1U_0603_10V6K
1
+3.3V_RUN_VDDIO
VDDRX
VDDRX
1 V Analog
1
1
2
1
1
2
2
J10
K8
K9
K10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3.3V IO
1
1
2
2
1
2
1
2
1
2
1
1
2
2
2
1
2
2
C24
0.01U_0402_16V7K
C22
0.1U_0402_25V6
C23
0.01U_0402_16V7K
E10
C7
C6
H11
E12
D12
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
C16
1U_0603_10V6K
H3
F3
D3
+3.3V_RUN_VDDA
3.3V Analog
C15
0.1U_0402_25V6
J3
E5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C14
0.01U_0402_16V7K
C18
0.01U_0402_16V7K
C17
0.1U_0402_25V6
C25
1U_0603_10V6K
C21
1U_0603_10V6K
+3.3V_RUN_VMM
L5
1
2
BLM18AG102SN1D_2P
E3
G3
C8
C9
F12
G12
+1.05V_VMM_VDDTX
B
E6
E7
E8
E9
H6
H7
H8
H9
C13
0.01U_0402_16V7K
C12
0.01U_0402_16V7K
C11
0.1U_0402_25V6
L4
1
2
BLM18AG102SN1D_2P
C9
0.1U_0402_25V6
+1.05V_RUN_VMM
C10
0.01U_0402_16V7K
+1.05V_VMM_VDD
C8
1U_0603_10V6K
1
U6B
C132
10U_0603_6.3V6M
L1
1
2
BLM18AG102SN1D_2P
1V Digital
+1.05V_RUN_VMM
2
R44
2
R52
2
R69
RP9
EEPROM
+3.3V_RUN_VMM
C34
2
1
U7
1
2
3
4
VMM_SPI_CS#
VMM_SPI_DIN
VMM_SPI_WP#
VMM_DPB_CTRLCLK 1
VMM_DPB_CTRLDAT 2
3
VMM_GPIO7
4
VMM_GPIO8
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
2.2K_0804_8P4R_5%
VMM_MESCL
2.2K_0402_5%
VMM_MESDA
2.2K_0402_5%
VMM_DPC_CTRLCLK
2.2K_0402_5%
VMM_DPC_CTRLDAT
2.2K_0402_5%
SW_DPC_AUX#
1M_0402_5%
VMM_SPI_CS#
10K_0402_5%
VMM_SPI_HOLD
2.2K_0402_5%
0.1U_0402_25V6
8
7
6
5
8
7
6
5
VMM_SPI_HOLD
VMM_SPI_CLK
VMM_SPI_DO
W25X10CVSNIG_SO8
1
2
1
2
1
2
1
2
1
2
2
1
2
1
R40
R42
R49
R46
R91
R64
R65
+3.3V_RUN_VMM
A
1
VMM2310_TX2N3
@ R73
2
RED_DOCK
0_0402_5%
RED_DOCK
1
VMM2310_TX2N2
@ R75
2 GREEN_DOCK
0_0402_5%
GREEN_DOCK
<34>
1
VMM2310_TX2N1
@ R76
2 BLUE_DOCK
0_0402_5%
BLUE_DOCK
<34>
1
2 CLK_DDC2_DOCK
0_0402_5%
CLK_DDC2_DOCK
1
2 DAT_DDC2_DOCK
0_0402_5%
VMM2310_SCL
@ R77
VMM2310_SDA
@ R81
<34>
2
VMM2310_HDP
10K_0402_5%
1
3@ R74
A
<34>
DAT_DDC2_DOCK
<34>
1
VMM2310_TX2N0
@ R84
2
HSYNC_DOCK
0_0402_5%
HSYNC_DOCK
<34>
1
VMM2310_TX2P0
@ R88
2
VSYNC_DOCK
0_0402_5%
VSYNC_DOCK
<34>
1
VMM2310_AUXN
3.74K_0402_1%
2
3@ R85
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
DP 1.2 MST HUB
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
21
of
58
5
4
3
2
1
+5V_TSP
JEDP1
USBP7USBP7+
<12>
+BL_PWR_SRC
EMC@LE1
EMC@
LE1 1
DISP_ON
1
3
<26>
1
CAM_MIC_CBL_DET#
LOOP_BACK
2
+3.3V_CAM
JLED1
<40>
<40>
<40>
<40>
<12>
@ D8
L30ESDL5V0C3-2_SOT23-3
DMIC_CLK
USBP3_DUSBP3_D+
<11>
<11>
<26>
2
DMIC0
@ CE2
100P_0402_50V8J
<36>
<10,36>
SS
2
LCD_VCC_TEST_EN
1
3
ENVDD_PCH
EN_LCDPWR
1
Backlight POWER
2
1
3
1
1
2
1
S
2
2
1
@
2
G
G
D
S
2
2nd source SA000028Y10
B
6
5
2
1
D
R97
100K_0402_5%
2
0_0402_5%
2
0_0402_5%
C66
1000P_0402_50V7K
1
@ R102
1
@ R106
CCD_OFF
3.3V_CAM_EN#
C67
0.1U_0402_25V6
<36>
<12>
APL3512ABI-TRG_SOT23-5
+BL_PWR_SRC
4
3
4
EN
Q2
FDC654P-G_SSOT-6
+3.3V_RUN
Q3
LP2301ALT1G_SOT23-3
3
5
C65
0.1U_0603_50V7K
PJP9
PAD-OPEN1x1m
+PWR_SRC
GND
@
2
D2
B
+3.3V_CAM
VIN
10U_0603_6.3V6M
<36>
1
BAT54CW_SOT323-3
VOUT
2
PANEL_BKEN_EC
BAT54CW_SOT323-3
1
1
3
U9
1
C430
0.01U_0402_16V7K
2
@ C431
2
1
<10>
R104
100K_0402_5%
R96
100K_0402_5%
R95
10K_0402_5%
BAT54CW_SOT323-3
+3.3V_CAM_Q
S
2
2
<37>
1
BIA_PWM_EC
PANEL_BKLEN
1
DISP_ON
BIA_PWM_EC
+LCDVDD
+3.3V_ALW
<10>
2
EDP_BIA_PWM
4
6
1
LCDVDD POWER
3
1
2
1
EDP_BIA_PWM
C
Q17B
DMN66D0LDW-7_SOT363-6
5
Close to JLED1.2
D21
3
2
3.3V_TS_EN
@
1
2
@
1
2
1
2
@
1
2
@
1
2
@
Close to JLED1.40
<12>
C64
0.1U_0402_25V6
Close to JLED1.1
+3.3V_RUN
C62
0.1U_0402_25V6
Close to JEDP1.33
+5V_TSP
C3
0.1U_0402_16V4Z
1
+5V_ALW
C68
0.1U_0402_25V6
Close to JEDP1.11,12
3
<12>
+3.3V_CAM
C63
0.1U_0402_25V6
C52
0.1U_0603_50V7K
2
+LCDVDD
1
+5V_TSP_Q
2
G
1
<10>
<10>
<10>
<10>
<10>
<10>
2
EDP_CPU_AUX#
EDP_CPU_AUX
EDP_CPU_LANE_P0
EDP_CPU_LANE_N0
EDP_CPU_LANE_P1
EDP_CPU_LANE_N1
+5V_RUN
Q1
LP2301ALT1G_SOT23-3
Q17A
DMN66D0LDW-7_SOT363-6
LCD_CBL_DET#
+3.3V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
D
+5V_RUN
1
1
1
1
1
1
C61
0.1U_0402_25V6
C54 2
C55 2
C59 2
C56 2
C60 2
C57 2
R94
47K_0402_5%
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
1
@
<36>
+LCDVDD
D10
2
PJP10
PAD-OPEN1x1m
LCD_TST
+5V_TSP
For Touchscreen
2
1
<10>
R108
1K_0402_5%
EDP_CPU_HPD
Close to JEDP1.24~27
WebCAM
D
LOOP_BACK
+BL_PWR_SRC
BIA_PWM
1
2
3
4
5
6
GND
GND
E-T_4260K-Q06N-23L
CONN@
ACES_50398-04071-001
CONN@
C
1
2
3
4
5
6
7
8
+5V_ALW
BATT_WHITE_LED#
BATT_YELLOW_LED#
PANEL_HDD_LED#
BREATH_WHITE_LED#
TOUCH_PANEL_INTR#
ESD depop location
2
BIA_PWM
BLM15BB221SN1D_2P~D
2
D
LED CONN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
@ CE1
100P_0402_50V8J
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
G5
G4
G3
G2
G1
2
45
44
43
42
41
PWR_SRC_ON
Q4
L2N7002WT1G_SC-70-3
R99
3
S
2
1
47K_0402_5%
D
1
change back to CCD_OFF at Goliad project
A
<11>
USBP3+
<11>
USBP3-
4
1
2
4
3
2
USBP3_D+
3
USBP3_D-
2
G
L8 EMC@
1
<37>
A
EN_INVPWR
DLW21HN900SQ2L_4P
1
2
@ R100
0_0402_5%
1
@ R101
DELL CONFIDENTIAL/PROPRIETARY
2
0_0402_5%
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
eDP CONN & Touch screen
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
22
of
58
5
4
3
2
1
L9 @
1
2
9NH_0402HS-9N0EJTS_5%
2
1
TMDS_CLK_C
0.1U_0402_10V7K
4
2
1
TMDS_CLK#_C
0.1U_0402_10V7K
1
C103
DDI1_LANE_N3
C191
L10
4
3
1
2
3
TMDSB_CON_CLK
2
TMDSB_CON_CLK#
1
2
L11 @
1
2
9NH_0402HS-9N0EJTS_5%
@ C274
1.8P_0402_50V8
D
@ C273
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P
1
<10>
DDI1_LANE_P3
2
EMC@
<10>
D
L12 @
1
2
9NH_0402HS-9N0EJTS_5%
DDI1_LANE_N2
C209
3
1
2
3
TMDSB_CON_P0
2
TMDSB_CON_N0
1
2
L14 @
1
2
9NH_0402HS-9N0EJTS_5%
@ C276
1.8P_0402_50V8
@ C275
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P
L15 @
1
2
9NH_0402HS-9N0EJTS_5%
4
1
TMDS_N1_C
0.1U_0402_10V7K
1
3
3
TMDSB_CON_P1
2
TMDSB_CON_N1
C270
2
<10>
DDI1_LANE_N0
2
1
TMDS_P2_C
0.1U_0402_10V7K
4
2
1
TMDS_N2_C
0.1U_0402_10V7K
1
C271
4
1
2
2
C88
10U_0603_6.3V6M
L19
DDI1_LANE_P0
C
@ C87
0.1U_0402_10V7K
L18 @
1
2
9NH_0402HS-9N0EJTS_5%
<10>
+VHDMI_VCC
U48
AP2330W-7_SC59-3
L17 @
1
2
9NH_0402HS-9N0EJTS_5%
@ C278
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P
@ C277
1.8P_0402_50V8
C
1
GND
DDI1_LANE_N1
2
<10>
1
@
4
1
1
TMDS_P1_C
0.1U_0402_10V7K
2
IN
2
C269
1
DDI1_LANE_P1
2
<10>
+5V_RUN
EMC@
C333
0.1U_0402_16V4Z
L16
1
1
2
1
TMDS_N0_C
0.1U_0402_10V7K
1
2
EMC@
4
2
4
OUT
1
TMDS_P0_C
0.1U_0402_10V7K
3
2
C199
1
<10>
DDI1_LANE_P2
2
L13
<10>
EMC@
3
3
TMDSB_CON_P2
JHDMI1 CONN@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPD_SINK
1
2
1
@ C382
1.8P_0402_50V8
@ C279
1.8P_0402_50V8
L20 @
1
2
9NH_0402HS-9N0EJTS_5%
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
20
CKGND 21
CK_shield GND 22
CK+
GND 23
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
LCN_AUF05-1922S10-0019
TMDSB_CON_N2
2
C272
2
1
2
DLW21SN900HQ2L-0805_4P
CPU_DPB_CTRLDAT_R
CPU_DPB_CTRLCLK_R
HDMI_CEC
TMDSB_CON_CLK#
TMDSB_CON_CLK
TMDSB_CON_N0
TMDSB_CON_P0
TMDSB_CON_N1
+5V_RUN
TMDSB_CON_P1
TMDSB_CON_N2
+3.3V_RUN
2
CPU_DPB_CTRLCLK_R
<10>
CPU_DPB_CTRLDAT
4
3
CPU_DPB_CTRLDAT_R
1
R471
1
R470
2
+5V_HDMI_DDC
2.2K_0402_5%
2
2.2K_0402_5%
2
@
6
1
2
CPU_DPB_CTRLCLK
5
<10>
Q120A
DMN66D0LDW-7_SOT363-6
1
@ R472
0_0402_5%
D65
RB751VM-40TE-17_SOD323-2
1
TMDSB_CON_P2
B
B
+3.3V_RUN
2
HDMI_CEC
10K_0402_5%
1
@ R473
Q120B
DMN66D0LDW-7_SOT363-6
R460
2
2
2
2
2
2
2
2
1
470_0402_1%
470_0402_1%
470_0402_1%
470_0402_1%
470_0402_1%
470_0402_1%
470_0402_1%
470_0402_1%
2 10K_0402_5%
3
1
1
HDMI_HPD_SINK
D
A
DPB_HPD
S
<10>
R474
2
20K_0402_5%
HDMI_OB
1
G
2
1
1
1
1
1
1
1
1
1
2
R475
1M_0402_5%
+3.3V_RUN
R465
R468
R467
R469
R462
R463
R464
R466
D
3
TMDS_P2_C
TMDS_N2_C
TMDS_P1_C
TMDS_N1_C
TMDS_P0_C
TMDS_N0_C
TMDS_CLK_C
TMDS_CLK#_C
+3.3V_RUN
S
2
G
Q29
L2N7002WT1G_SC-70-3
Q121
L2N7002WT1G_SC-70-3
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
HDMI CONN
Size
Document Number
Date:
Friday, May 17, 2013
LA-9591P
Sheet
Rev
0.4
23
of
58
5
4
3
2
1
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK
1
C93
2
0.1U_0402_25V6
U11
<21>
D
<34>
<21>
<34>
1
2
2
1 SW_DPB_AUX_C
C94
0.1U_0402_10V7K
DPB_DOCK_AUX
SW_DPB_AUX
DPB_DOCK_AUX
3
DPB_DOCK_AUX#
VCC
BE3
B0
4
5
2
1 SW_DPB_AUX#_C
C95
0.1U_0402_10V7K
DPB_DOCK_AUX#
SW_DPB_AUX#
BE0
A0
A3
BE1
A1
6
7
B3
BE2
B1
A2
GND
B2
14
13
D
12
VMM_DPB_CTRLCLK
<21>
11
10
9
VMM_DPB_CTRLDAT
<21>
8
PI3C3125LEX_TSSOP14~D
2
R60
100K_0402_5%
1
+3.3V_RUN_VMM
1
DPB_CA_DET
D
S
Q10
BSS138W-7-F_SOT323-3
<21,34>
3
DPB_CA_DET#
2
G
DPB_CA_DET
C
C
+3.3V_RUN_VMM
AUX/DDC SW for DPC to E-DOCK
1
C97
2
0.1U_0402_25V6
U13
<21>
<34>
<21>
<34>
SW_DPC_AUX
2
C98
1 SW_DPC_AUX_C
0.1U_0402_10V7K
DPC_DOCK_AUX
2
C99
1 SW_DPC_AUX#_C
0.1U_0402_10V7K
DPC_DOCK_AUX#
DPC_DOCK_AUX
SW_DPC_AUX#
DPC_DOCK_AUX#
1
2
3
4
5
6
7
BE0
A0
VCC
BE3
B0
A3
BE1
A1
B3
BE2
B1
A2
GND
B2
14
13
12
VMM_DPC_CTRLCLK
<21>
11
10
9
VMM_DPC_CTRLDAT
<21>
8
PI3C3125LEX_TSSOP14~D
B
B
1
S
1
2
R56
100K_0402_5%
D
3
+3.3V_RUN_VMM
DPC_CA_DET#
A
DPC_CA_DET
DPC_CA_DET
1
R120
2
DPB_CA_DET
1M_0402_5%
1
R121
2
DPC_CA_DET
1M_0402_5%
2
G
Q6
BSS138W-7-F_SOT323-3
<21,34>
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DP SW
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
24
of
58
5
4
3
2
1
D
D
2
+3.3V_RUN
@ PJP2
PAD-OPEN1x1m
1
+3.3V_RUN
+5V_HDD
8
GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC
5
12
2
3
<12>
FFS_INT2
FFS_INT2
2
LNG3DMTR_LGA16_3X3~D
1
2
3
1
5
4
7
6
4
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
INT 1
INT 2
FFS_INT2_Q
Q19B
DMN66D0LDW-7_SOT363-6
<18,19,31,7,9>
<18,19,31,7,9>
11
9
FFS_INT2
10
13
15
16
Q19A
DMN66D0LDW-7_SOT363-6
C
HDD_FALL_INT
RES
RES
RES
RES
6
LNG3DM
VDD_IO
VDD
2
U15
1
14
<10>
+3.3V_RUN
1
2
Free Fall Sensor
R126
100K_0402_5%
2
1
DDR_XDP_WAN_SMBDAT
10K_0402_5%
DDR_XDP_WAN_SMBCLK
10K_0402_5%
@ R125
100K_0402_5%
2
C102
0.1U_0402_25V6
2
C101
10U_0603_6.3V6M
1
R122
1
R123
1
+3.3V_RUN_FFS
C
+3.3V_HDD
1
2
@ R188
HDD_DEVSLP
10K_0402_5%
JSATA1
<6>
<6>
SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C
<6>
<6>
SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C
C105 2
C106 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
C109 2
C108 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
+3.3V_HDD
<12>
HDD_DEVSLP
B
+5V_HDD
<6>
+3.3V_HDD
HDD_DET#
HDD_DET#
@ PJP3
1
2
1
2
1
2
2
C114
0.1U_0402_25V6
@ C113
0.1U_0402_25V6
C112
0.1U_0402_25V6
C111
1000P_0402_50V7K
1
+5V_RUN
1
2
+5V_HDD
PAD-OPEN1x1m
FFS_INT2_Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
B
ACES_50406-02071-001
CONN@
Place near HDD CONN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
HDD CONN
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
25
of
58
2
1
+3.3V_RUN_AUDIO
DAI_12MHZ#
DAI_BCLK#
DAI_DO#
<34>
DAI_LRCK#
<34>
DAI_DI
2
2
2
2
I2S_MCLK
22_0402_5%
I2S_BCLK
22_0402_5%
I2S_DO
Place R142 close to codec
33_0402_5%
I2S_LRCLK
0_0402_5%
I2S_DI#
0_0402_5%
SPK-R+
SPK-RI2S_MCLK
PCBEEP
16
I2S_SCLK
17
18
I2S_LRCK
24
I2S_DIN
MONO-OUT/CBP
12
2
4
46
48
2
1
@ R186
1
0.1U_0402_25V6
DMIC_CLK
33_0402_5%
2
0_0402_5%
2
1
2
1
1
2
2
1
2
1
2
1K_0402_5%
BEEP
1
<37>
<22>
<22>
EN_I2S_NB_CODEC#
37
<36>
DMIC_CLK
1
2
ALC3226-CG_QFN48_7X7
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
1
@
1
place close to pin2
C140
10U_0603_6.3V6M
GND
30
26
R39
20K_0402_1%
MIC1-VREFO
AVSS1
Place close to Codec
2
PVSS
49
+ALC290_LDO_CAP
+ALC3226_CPVEE
+ALC3226_VREF
1
42
21
22
34
25
2
DVSS
36
1
LDO-CAP
JDREF
CPVEE
VREF
2
2
CBP/AVSS2
EAPD/PD
C138
2.2U_0603_6.3V6K
1
MIC1-R
1
7
2
10K_0402_5%
Place C134 close to Codec
2
1
1
2
R150
47
1
2.2U_0603_6.3V6K
C169
2.2U_0603_6.3V6K
1
+3.3V_RUN_AUDIO
1
AUD_NB_MUTE#
2
C134
C167
0.1U_0402_25V6
@ C136
10P_0402_50V8J
<35,36>
1
3 2
1
2
0.1U_0402_25V6
1
2
0.1U_0402_25V6
@ C144
2
PAD-OPEN1x1m
+5V_RUN_AUDIO
U18
+5V_ALW
RUN_ON
1
@ R154
2
0_0402_5%
1
2
3
5
SLEEVE
Add for solve pop noise and detect issue
+3.3V_ALW
A
+RTC_CELL
6
7
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
2
5
4
1
DOCK_HP_DET
DOCK_MIC_DET
Q21B
DMN66D0LDW-7_SOT363-6
<36>
2
1
C147
2
0.1U_0402_10V7K
2
470P_0402_50V7K
1
C148
2
1000P_0402_50V7K
11
10
9
8
+3.3V_RUN_AUDIO
15
TPS22966DPUR_SON14_2X3
2
A
5
Q123A
DMN66D0LDW-7_SOT363-6
1
6
Q123B
DMN66D0LDW-7_SOT363-6
4
3
1
1
2
3
2
6
+3.3V_RUN_AUDIO
R159
100K_0402_5%
R158
100K_0402_5%
2
Q21A
DMN66D0LDW-7_SOT363-6
R157
20K_0402_1%
+3.3V_RUN_AUDIO
R156
39.2K_0402_1%
1
AUD_SENSE_B
R202
100K_0402_5%
1
Place closely to Pin 14
1
@ C188
12
@ C139
0.1U_0402_10V7K
GPAD
14
13
1
2
1
1
AUD_HP_NB_SENSE
4
6
2
0.1U_0402_25V6
@ C142
5
@ C408
10U_0603_6.3V6M
1
1
@ C141
C137
0.1U_0402_25V6
Q20B
DMN66D0LDW-7_SOT363-6
R152
39.2K_0402_1%
@ PJP4
1
place at AGND and DGND plane
2
@ C135
0.1U_0402_10V7K
2
AUD_NB_MUTE#
C410
1U_0603_10V6K
@ R149
33_0402_5%
@ R148
47_0402_5%
<36>
35
4
1
1
R151
DMIC_CLK
DMIC0
2
PCH_AZ_CODEC_BITCLK
CBN
<36,37,39>
2
1
2
1
DMIC_CLK_L
EMC@ R170
B
+VREFOUT
AUD_SENSE_A
2
Q20A
DMN66D0LDW-7_SOT363-6
<36>
2
1
1
2
C146
AUD_PC_BEEP
R197
C130
22P_0402_50V8J
MIC1-L
20
1
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA
DMIC1/GPIO2
GPIO3
I2S_DOUT
44
43
2
@
RESET#
15
40
41
RING2
<35>
SLEEVE/RING2 please keep 40 mils trace width
SLEEVE
<35>
+VREFOUT
1
2
C385
10U_0603_6.3V6M
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
1
2
AUD_OUT_L
AUD_HP_OUT_L
AUD_HP_OUT_L
<35>
2 18_0402_5% AUD_HP_OUT_R
AUD_OUT_R R162 1
AUD_HP_OUT_R
<35>
R166
18_0402_5%
1
2
INT_SPK_L+
INT_SPK_L@ R194
10K_0402_5%
1
2
INT_SPK_R+
@ R153
10K_0402_5%
2
1
1
2
INT_SPK_RSPKR
<12>
C145
0.1U_0402_25V6
R147
1K_0402_5%
R187
Close to U17 pin6
PCH_AZ_CODEC_SDOUT
2
SPK-L+
SPK-L-
31
33
32
RING2
SLEEVE
2
2
11
19
Place closely to Pin 13.
2
1
2
SDATA-IN
28
29
23
2
1
1
1
1
2
2
2
2
<34>
<34>
2
HPOUT-L/MIC-CAP
AVSS2/HPOUT-L
HP-OUT-R
SYNC
8
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
1
EMC_3@ R137
1
EMC_3@ R139
1
3@ R142
1
@ R143
1
@ R144
2
1
2
@
1
2
1
1
2
1
2
2
2
33_0402_5%
+VREFOUT
1
RING2
2.2K_0402_5%
1
SLEEVE
2.2K_0402_5%
C131
1U_0603_10V4Z
1
R136
PCH_AZ_CODEC_RST#
<34>
Close to U17 pin5
Place R136 close to codec
AUD_SENSE_A
AUD_SENSE_B
@ R130
0_0805_5%
<6>
SDATA-OUT
10
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_SDIN0
LINE1-L/RING2
LINE1-R/SLEEVE
LINE1-VREFO
BIT-CLK
+VDDA_PVDD
13
14
C122
10U_0603_6.3V6M
<6>
<6>
Close to U17
Sense A
Sense B
45
39
C123
0.1U_0402_25V6
B
PCH_AZ_CODEC_SDOUT
5
DVDD
27
38
place close to pin45
C128
10U_0603_6.3V6M
<6>
6
PCH_AZ_CODEC_SDOUT
PVDD2
PVDD1
place close to pin39
C129
0.1U_0402_25V6
@ C127
1000P_0402_50V7K
@ C126
1000P_0402_50V7K
@ C125
1000P_0402_50V7K
@ C124
1000P_0402_50V7K
9
PCH_AZ_CODEC_BITCLK
AVDD1
AVDD2/HVDD(3.3)
DVDD-IO
C116
10U_0603_6.3V6M
DREG_OUT
3
PCH_AZ_CODEC_BITCLK
+VDDA_AVDD2
U17
1
E-T_4280K-F04N-05L
<6>
place close to pin38
C150
0.1U_0402_25V6
1
2
3
4
GND1
GND2
C121
10U_0603_6.3V6M
1
2
3
4
5
6
INT_SPKR_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R-
BLM18PG330SN1_2P
BLM18PG330SN1_2P
BLM18PG330SN1_2P
BLM18PG330SN1_2P
C120
0.1U_0402_25V6
2
2
2
2
C405
1U_0603_10V6K
1
1
1
1
C119
0.1U_0402_25V6
L22
L23
L24
L25
C118
1U_0603_10V6K
EMC@
EMC@
EMC@
EMC@
+5V_RUN_AUDIO
@ R140
0_0603_5%
+DVDD_CORE
CONN@
JSPK1
40 mils trace keep 10 mil spacing
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
+3.3V_RUN_AUDIO
L21
1
2
PBY160808T-600Y-N_2P
C117
10U_0603_6.3V6M
+3.3V_RUN_AUDIO
Internal Speakers Header
C115
0.1U_0402_25V6
+VDDA_AVDD1
1
+5V_RUN_AUDIO
place close to pin27
2
1
@ R213
2
PCH_AZ_CODEC_RST#
0_0402_5%
1
@ R220
2
AUD_NB_MUTE#
0_0402_5%
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Codec _ALC3226
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
26
of
58
5
4
3
2
1
1
GND
GND
GND
HGND
OE
DP12412_N0
DP12412_P0
DP12412_N1
DP12412_P1
DP12412_N2
DP12412_P2
DP12412_N3
DP12412_P3
DP12412_AUX#
DP12412_AUX
DP12412_HPD
25
2
R161
mDP_LANE_N0_C
mDP_LANE_P0_C
mDP_LANE_N1_C
mDP_LANE_P1_C
mDP_LANE_N2_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_P3_C
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
+3.3V_RUN
1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
IN
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
OUT
AUXAUX+
AUX_HPD_SEL
HPD
33
32
31
30
29
28
27
26
19
20
15
C163
C164
C165
C166
C168
C170
C172
C173
GND
D0-B
D0+B
D1-B
D1+B
D2-B
D2+B
D3-B
D3+B
AUX-B
AUX+B
HPD_B
mDP_LANE_N0
mDP_LANE_P0
mDP_LANE_N1
mDP_LANE_P1
mDP_LANE_N2
mDP_LANE_P2
mDP_LANE_N3
mDP_LANE_P3
mDP_AUX#
mDP_AUX
mDP_HPD
3
1
17
22
43
GPU_SEL
D0D0+
D1D1+
D2D2+
D3D3+
42
41
40
39
38
37
36
35
24
23
16
2
DOCKED
DPC_HPD
13
14
5
18
D0-A
D0+A
D1-A
D1+A
D2-A
D2+A
D3-A
D3+A
AUX-A
AUX+A
HPD_A
2
1
2
1
2
CPU_DPC_AUX#
CPU_DPC_AUX
<10>
2
3
4
6
7
8
9
10
11
VDD
VDD
VDD
+VDISPLAY_VCC
1
+3.3V_RUN
4.7K_0402_5%
1
PI3VDP12412ZHEX_TQFN42_9X3P5~D
DOCKED
2
C
function
1
Dock
0
mini DP
JmDP1
mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C
+3.3V_RUN
AUX/DDC SW for DPC to Mini DP
1
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C
C411
2
0.1U_0402_25V6
DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD
U49
mDP_AUX
2
C174
2
mDP_AUX#
C175
1
SW_mDP_AUX_C
0.1U_0402_10V7K
mDP_AUX_C
1
SW_mDP_AUX#_C
0.1U_0402_10V7K
mDP_AUX#_C
B
1
2
3
4
5
6
7
BE0
A0
VCC
BE3
B0
A3
BE1
A1
B3
BE2
B1
A2
GND
B2
C171
0.01U_0402_16V7K
R168
2
1
2
2
R167
<10>
<10>
U19
12
21
34
U50
AP2337SA-7 SOT-23
1
R165
mDP_HPD
100K_0402_5%
2
mDP_AUX_C
100K_0402_5%
1
mDP_CA_DET
1M_0402_5%
2
DPB_MB_P14
5.1M_0402_5%
DOCKED
D
@ C383
0.1U_0402_16V4Z
R164
2
C154
0.1U_0402_25V6
1
2
mDP_AUX#_C
100K_0402_5%
DOCKED
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
@ C153
0.1U_0402_25V6
1
R163
<21,28,32,36>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
C152
0.1U_0402_25V6
+3.3V_RUN
C151
4.7U_0603_6.3V6K
D
1
+3.3V_RUN
14
13
12
CPU_DPC_CTRLCLK
<10>
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
11
10
C
CONN@
DP_PWR
GND
AUX_CH_N
LANE2_N
AUX_CH_P
LANE2_P
GND
GND
LANE3_N
LANE1_N
LANE3_P
LANE1_P
GND
GND
CONFIG2
LANE0_N
CONFIG1
LANE0_P
HOT_PLUG
GND
GND4
GND3
GND2
GND1
24
23
22
21
ACON_MAR2F-20K1800
9
CPU_DPC_CTRLDAT
<10>
B
8
PI3C3125LEX_TSSOP14~D
2
R67
100K_0402_5%
1
+3.3V_RUN
1
D
S
2
G
Q31
BSS138W-7-F_SOT323-3
mDP_CA_DET
3
mDP_CA_DET#
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Mini DP
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
27
of
58
5
4
3
2
1
U21
1
2
1
2
1
2
2
1
2
1
2
30
12
XTAL_OUT
XTAL_IN
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
@ R181
+0.9V_LAN
47
46
37
Place C177, C180 and L26 close to U21
0_0603_5%
+3.3V_LAN
Pin 6 is SVR_EN in Clarkville
+0.9V_LAN
43
11
40
22
16
8
CTRL0P9
VSS_EPAD
7
1
15
19
29
Note:
+1.0V_LAN will work at 0.95V to 1.15V
TEST_EN
RBIAS
1
+3.3V_LAN
1
2
JTAG
VDD0P9_11
2
+3.3V_LAN_OUT
C187
22U_0805_6.3V6M
RES_BIAS
VDD0P9_43
4
C186
0.1U_0402_10V7K
LAN_TEST_EN
R185
3.01K_0402_1%
2
1
GND
25MHZ_18PF_7V25000034
REGCTL_PNP10
49
WGI218LM-SLK3A-B1_QFN48_6X6~D
C
1
R145
@ 0_0402_5%
2
R331
GND
1
R184
1K_0402_5%
+3.3V_RUN
IN
C190
33P_0402_50V8J
C189
33P_0402_50V8J
C
4
OUT
VDD0P9_47
VDD0P9_46
VDD0P9_37
0_0402_5%
1 4.7K_0402_5%
C185
0.1U_0402_10V7K
R206
1M_0402_5%
Y3
3
9
10
XTALO
XTALI
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
@ R175
+RSVD_VCC3P3_1 R178 2
D
5
C184
0.1U_0402_10V7K
2
0_0402_5%
32
34
33
35
1
1
2
2
LED0
LED1
LED2
VDD3P3_15
VDD3P3_19
VDD3P3_29
2
26
27
25
2
1
VDD3P3_IN
VCT_LAN_R1
2
RSVD_VCC3P3_1
LANWAKE_N
LAN_DISABLE_N
6
C183
0.1U_0402_10V7K
1
XTALO_R
@ R183
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
L26
1
SVR_EN_N
VDD3P3_4
PAD~D
PAD~D
LAN_TX3+
LAN_TX3-
C182
1U_0603_10V6K
@ R182
10K_0402_5%
@ T92
@ T93
LAN_TX2+
LAN_TX2-
23
24
2
2
3
SMB_CLK
SMB_DATA
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
20
21
2
1
MDI
MDI_PLUS3
MDI_MINUS3
1
1
28
31
SMBus Device Address 0xC8
<36>
MDI_PLUS2
MDI_MINUS2
2
LAN_SMBDATA
LAN_WAKE#
PERp
PERn
+0.9V_LAN
1
REGCTL_PNP10
4.7UH_CBC2012T4R7M_20%
1
<7>
<12,37>
PETp
PETn
LAN_TX1+
LAN_TX1-
2
LAN_SMBCLK
41
42
MDI_PLUS1
MDI_MINUS1
LAN_TX0+
LAN_TX0-
17
18
1
PM_LANPHY_ENABLE
2
0_0402_5%
PCIE_PTX_GLANRX_N3
<7>
2
1
@ R180
<11>
38
39
PE_CLKP
PE_CLKN
13
14
2
TP_LAN_JTAG_TMS
10K_0402_5%
TP_LAN_JTAG_TCK
10K_0402_5%
1
LAN_WAKE#_R
4.7K_0402_5%
2
1
<12>
2
@ R173
10K_0402_5%
1
@ R171
1
@ R172
2
@ R176
D
PCIE_PTX_GLANRX_P3
1 PCIE_PRX_GLANTX_P3_C
0.1U_0402_10V7K
1 PCIE_PRX_GLANTX_N3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_P3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_N3_C
0.1U_0402_10V7K
2 LAN_SMBCLK_R
0_0402_5%
2 LAN_SMBDATA_R
0_0402_5%
2 LAN_WAKE#_R
0_0402_5%
LAN_DISABLE#_R
PCIE
PCIE_PRX_GLANTX_N3
<11>
2
C179
2
C176
1
C178
1
C181
1
@ R174
1
@ R177
1
@ R179
MDI_PLUS0
MDI_MINUS0
C180
10U_0603_6.3V6M
<11>
+3.3V_LAN
44
45
CLK_REQ_N
PE_RST_N
C177
0.1U_0402_10V7K
<11>
CLK_PCIE_LAN
CLK_PCIE_LAN#
PCIE_PRX_GLANTX_P3
2 0_0402_5% LANCLK_REQ#_R 48
36
PLT_LAN_RST#
SMBUS
<7>
<7>
+3.3V_LAN
@ R169 1
LANCLK_REQ#
LED
<12,7>
+3.3V_RUN
LAN_RST#
10K_0402_5%
@ C406
2
1
+3.3V_LAN
U22
O
A
1
2
2
@ R25
100K_0402_5%
@ U20
TC7SH08FU_SSOP5~D
4 PLT_LAN_RST#
<36,9>
SIO_SLP_LAN#
2
@ R196
3.3V_HDD_EN
1
@ R129
1
0_0402_5%
3
2
0_0402_5%
VOUT1
VOUT1
ON1
4
+5V_ALW
<12>
VIN1
VIN1
CT1
VBIAS
5
6
7
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
2
1
C407
2
470P_0402_50V7K
1
C429
2
470P_0402_50V7K
10
9
8
+3.3V_HDD
15
2
2
3
LAN_TX1+ 1
EMC@ L29
1
LAN_TX1EMC@ L30
2
LAN_TX1+R
12NH_0603CS-120EJTS_5%
2
LAN_TX1-R
12NH_0603CS-120EJTS_5%
6
LAN_TX2+ 1
EMC@ L31
1
LAN_TX2EMC@ L32
2
9
LAN_TX3+ 1
EMC@ L33
1
LAN_TX3EMC@ L34
2
<21,27,32,36>
LAN_TX2+R
12NH_0603CS-120EJTS_5%
2
LAN_TX2-R
12NH_0603CS-120EJTS_5%
2
DOCKED
LAN_TX3+R
12NH_0603CS-120EJTS_5%
LAN_TX3-R
12NH_0603CS-120EJTS_5%
7
10
11
12
DOCKED
13
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
15
16
42
5
A
DOCKED
1: TO DOCK
43
A0+
B1+
B1-
A0-
B2+
B2-
A1+
A1-
B3+
B3-
A2+
A2-
LEDB0
LEDB1
LEDB2
A3+
C0+
C0-
A3-
C1+
C1-
SEL
C2+
C2-
LEDA0
LEDA1
LEDA2
C3+
C3LEDC0
LEDC1
LEDC2
PD
34
33
SW_LAN_TX1+
SW_LAN_TX1-
29
28
SW_LAN_TX2+
SW_LAN_TX2-
25
24
SW_LAN_TX3+
SW_LAN_TX3-
17
18
41
SW_ACTLED_YEL#
SW_100_ORG#
SW_10_GRN#
36
35
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
32
31
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
27
26
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
23
22
19
20
40
DOCK_LOM_TRD3+
DOCK_LOM_TRD3DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
<35>
<35>
SW_LAN_TX1+
SW_LAN_TX1-
<35>
<35>
SW_LAN_TX2+
SW_LAN_TX2-
<35>
<35>
SW_LAN_TX3+
SW_LAN_TX3-
<35>
<35>
2
A
O
Q32A
DMN66D0LDW-7_SOT363-6
1
6
SW_ACTLED_YEL#
WLAN_LAN_DISB#
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
<34>
<34>
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
<34>
<34>
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
<34>
<34>
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
<34>
<34>
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
MASK_BASE_LEDS#
SW_100_ORG#
<36>
U24
NL17SZ08DFT2G_SSOP5~D
LAN_ACTLED_YEL#
<35>
MASK_BASE_LEDS#
<40>
SW_10_GRN#
Q33A
DMN66D0LDW-7_SOT363-6
1
6
LED_10_GRN#
<35>
2
LAN_TX0+R
12NH_0603CS-120EJTS_5%
LAN_TX0-R
12NH_0603CS-120EJTS_5%
SW_LAN_TX0+
SW_LAN_TX0-
MASK_BASE_LEDS#
Q33B
Q32B
DMN66D0LDW-7_SOT363-6
4
3
LED_100_ORG#
DMN66D0LDW-7_SOT363-6
4
3
<35>
5
2
SW_LAN_TX0+
SW_LAN_TX0-
4
2
2
38
37
B
0.1U_0402_10V7K
5
LAN_TX0+ 1
EMC@ L27
1
LAN_TX0EMC@ L28
B0+
B0-
B
3
LOM_SPD10LED_GRN#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U23
1
P
LOM_SPD100LED_ORG#
G
5
@ C198
1
2
39
30
21
14
8
4
1
1
2
1
2
2
C194
0.1U_0402_25V6
C193
0.1U_0402_25V6
Layout Notice : Place bead as
close PI3L500 as possible
C192
0.1U_0402_25V6
1
+3.3V_LAN
B
0.1U_0402_10V7K
11
TPS22966DPUR_SON14_2X3
LAN ANALOG SWITCH
+3.3V_LAN
1
C426
12
@ C428
0.1U_0402_10V7K
GPAD
14
13
1
PLTRST_LAN#
B
1
<9>
2
G
LAN_RST#
3
<12>
P
5
+3.3V_ALW
1
0.1U_0402_10V7K
MASK_BASE_LEDS#
<34>
<34>
<34>
A
PAD_GND
0: TO RJ45
PI3L720ZHEX_TQFN42_9X3P5~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
LAN
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
28
of
58
5
4
3
2
1
D
D
+3.3V_RUN
+3.3V_RUN_TPM
@ PJP5
1
2
+3.3V_RUN_TPM
26
23
20
17
LPCPD#
V_BAT
NBO_13
NBO_14
LAD0
LAD1
LAD2
LAD3
GPIO6
<7>
CLK_PCI_TPM_TCM
<36,37,7>
LPC_LFRAME#
<31,36,37,9>
PCH_PLTRST#_EC
<12,36,37>
IRQ_SERIRQ
<12,36,37,9>
CLKRUN#
C
21
22
16
27
15
LPC_LFRAME#
IRQ_SERIRQ
CLKRUN#
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
TESTBI
TESTI
1
2
1
2
1
6
9
8
C
NC_7
1
2
3
12
13
14
2
1
28
2
1
2
2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
2
10_0402_5%
2
SP_TPM_LPC_EN_R
0_0402_5%
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
C204
0.1U_0402_25V6
<36,37,7>
<36,37,7>
<36,37,7>
<36,37,7>
SB3V
10
19
24
@ C384
2200P_0402_50V7K
SP_TPM_LPC_EN
5
+3.3V_RUN_TPM
VCC_0
VCC_1
VCC_2
C202
2200P_0402_50V7K
1
@ R198
1
@ R193
PCH_TPM_LPC_EN
U25
C203
2200P_0402_50V7K
<36>
ATMEL TPM for E4
C201
4700P_0402_25V7K
<7>
@ C200
0.1U_0402_25V6
1
PAD-OPEN1x1m
ATEST_1
ATEST_2
ATEST_3
GND_4
GND_11
GND_18
GND_25
7
4
11
18
25
AT97SC320412-ABF _TSSOP28
USH CONN
JUSH1
+3.3V_SUS
1
2
USH_SMBCLK
2.2K_0402_5%
2
USH_SMBDAT
2.2K_0402_5%
R190
1
R191
1
<11>
<11>
<37>
<37>
<36>
2
USH_PWR_STATE#
1M_0402_5%
R195
B
USBP4USBP4+
USH_SMBCLK
USH_SMBDAT
BCM5882_ALERT#
+3.3V_SUS
<9>
<36>
<10>
<12>
USH_DET#
GND2
GND1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B
CONN@
ACES_50506-02041-P01
@
@
1
2
1
2
@
+3.3V_SUS
C206
0.1U_0402_25V6
2
+3.3V_RUN
C207
0.1U_0402_25V6
C208
0.1U_0402_25V6
1
+5V_RUN
+3.3V_RUN
+5V_RUN
PLTRST_USH#
USH_PWR_STATE#
CONTACTLESS_DET#
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Close to JUSH1
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USH & TPM
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
29
of
58
A
B
2
BLM15AG601SN1D_2P
1
2
1
2
1
2
1
2
1
2
C215
0.1U_0402_25V6
C214
0.1U_0402_25V6
C213
4.7U_0603_6.3V6K
C212
0.1U_0402_25V6
C211
4.7U_0603_6.3V6K
C210
0.1U_0402_25V6
C210 close to U27.42
C211 C212 close to
U27.23
E
+3.3V_RUN_AIN
1
L35
2
1
1
D
C215 close to U27.9
C213 C214 close to
U27.35
+3.3V_RUN
+3.3V_RUN
C
1
+3.3V_RUN
+1.2V_LDO
10
AUX _33VIN
SD_SKT_33VOUT
MAIN_LDO_VIN
SD_SKT_18VOUT
22
+3.3V_RUN_CARD
24
+1.8V_RUN_CARD
2
1
2
SD_SKT_33VIN
2
+SD_IO_LDO
SD_33VCCD
1
13
+AUX_LDO
25
1
2
1
1
2
1
2
1
2
1
MAIN_LDO_12VOUT
+1.2V_LDO_AIN
PCIE_PRX_MMITX_P5
PCIE_PRX_MMITX_N5
C237 1
C238 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
<7>
<7>
PCIE_PRX_MMITX_P5_C
PCIE_PRX_MMITX_N5_C
15
14
MEDIACARD_PWREN
17
MMICLK_REQ#
IO_LDOSEL
18
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
PE_REFCLKM
PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
SD_REXT/NC
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
1
29
30
32
33
34
35
26
R211 1
@ R410 1
@ R341 1
2 0_0402_5%
2 0_0402_5%
SD/MMCDAT3_R
SD/MMCDAT2_R
EMI solution for SD card
EMI depop location
+3.3V_RUN_CARD
DEV_WAKE#
CLKREQ#
LED#
IO0_LDOSEL
GND
+1.8V_RUN_CARD
2 4.7K_0402_1%
19
49
@ C228
4.7U_0603_6.3V6K
16
MEDIACARD_IRQ#
PE_TXP
PE_TXM
SD/MMCDAT3
SD/MMCDAT2
SD/MMCDAT1
SD/MMCDAT0
2
@ C229
0.1U_0402_25V6
<7>
PE_RXP
PE_RXM
SD/MMCCLK
@ C227
0.1U_0402_25V6
<12>
7
8
2
3
CLK_PCIE_MMI#
CLK_PCIE_MMI
PE_RST#
<12>
6
5
39
40
44
46
47
48
37
38
R230 1 EMC@ 2 10_0402_5%
1
<11>
<11>
R205
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
C235 1
C236 1
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
PE_REXT
SD/MMCCLK_R
SD/MMCCMD
2
PCIE_PTX_MMIRX_P5
PCIE_PTX_MMIRX_N5
4
SDWP
SD/MMCCD#
43
45
1
<11>
<11>
2
PE_REXT
191_0402_1%
PCIE_PTX_MMIRX_P5_C
PCIE_PTX_MMIRX_N5_C
SD_CLK
SD_CMD
PE_12VCCAIN
20
21
2
1
SD_WPI
SD_CD#
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
2
1
CORE_12VCCD
1
2
1
1
2
1
2
1
2
1
36
31
28
@ C255
5P_0402_50V8C
C234
0.1U_0402_25V6
C233
0.1U_0402_25V6
@ C232
0.1U_0402_25V6
C231
0.1U_0402_25V6
C230
4.7U_0603_6.3V6K
2
2
41
2
2
2
1
23
12
C222
1U_0402_6.3V6K
1
AUX_LDO_CAP
UHSII_33VCCAIN/NC
SD_IO_LDO_CAP
42
11
L36
1
2
BLM15AG601SN1D_2P
OZ777FJ2LN
PE_33VCCAIN
@ C221
4.7U_0603_6.3V6K
2
27
C216
0.1U_0402_25V6
1
9
C220
4.7U_0603_6.3V6K
C226
0.1U_0402_25V6
C225
4.7U_0603_6.3V6K
C218
0.1U_0402_25V6
C217
0.1U_0402_25V6
C223
4.7U_0603_6.3V6K
C219
0.1U_0402_25V6
C224
4.7U_0603_6.3V6K
2
U27
+1.2V_LDO
OZ777FJ2LN_QFN48_6X6
please routing daisy chain
1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4
2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
+3.3V_RUN
C227 near U27.22
C228 C229 near U27.24
R212
100K_0402_5%
R231 1
3
1
3
1
2
2
SD/MMCDAT1_D
JSD1
DLW21SN900SQ2L-0805_4P
2
2 @ 0_0402_5%
1
SD/MMCCD#
SDWP
18
19
SD/MMCDAT0_D
SD/MMCDAT1_D
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P_D
SD_UHS2_D0N_D
SD_UHS2_D1P_D
SD_UHS2_D1N_D
7
8
9
1
11
12
16
15
PE_RST#
CONN@
VDD/VDD1
VDD2
CMD
CLK
CARD DETECT
WRITE PROTEC
DAT0/RCLK+
DAT1/RCLKDAT2
CD/DAT3
D0+
DOD1+
D1-
3
6
10
13
17
Near to JSD1
4
GND1
GND2
GND3
GND4
GND5
GND6
GND7
VSS1
VSS2
VSS3
VSS4
VSS5
20
21
22
23
24
25
26
ALPS_SCDADA0101_NR
1
@ R27
100K_0402_5%
L48 @
2
A
R333 1
4
14
2
5
P
5
2
2 @ 0_0402_5%
0.1U_0402_25V6
O
@U26
@
U26
TC7SH08FU_SSOP5~D
R315 1
SD/MMCCMD
SD/MMCCLK
G
MEDIACARD_RST#
B
3
<12>
4
SD_UHS2_D0N_D
DLW21SN900SQ2L-0805_4P
C341 @
2
1
1
2
R493
1M_0402_5%
0_0402_5%
+3.3V_RUN
PLTRST_MMI#
2
SD_UHS2_D0P_D
2
@ R443
<9>
1
3
C247
4.7U_0603_6.3V6K
1
3
C246
0.1U_0402_25V6
SD_UHS2_D0N
4
@ C240
4.7U_0603_6.3V6K
1
4
C239
0.1U_0402_25V6
L47 @
SD_UHS2_D0P
2
2 @ 0_0402_5%
+1.8V_RUN_CARD
1
R306 1
+3.3V_RUN_CARD
2
2 @ 0_0402_5%
1
R297 1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
C256
0.1U_0402_25V6
@ R214
100K_0402_5%
1
4
SD/MMCDAT0_D
1
SD/MMCDAT1
3
2
4
1
SD/MMCDAT0
2
IO_LDOSEL
2
2 @ 0_0402_5%
L46 @
2
2
3
1
1
R231,R297,R306,R315,R333,R337 for EMI solution
SD_UHS2_D1P
1
SD_UHS2_D1N
4
1
4
2
3
2
SD_UHS2_D1P_D
3
SD_UHS2_D1N_D
4
DLW21SN900SQ2L-0805_4P
R337 1
DELL CONFIDENTIAL/PROPRIETARY
2 @ 0_0402_5%
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Card Reader
Size
Document Number
Date:
Friday, May 17, 2013
LA-9591P
Sheet
E
Rev
0.4
30
of
58
5
4
3
2
1
Mini WLAN/WIiGi/BT H=4
Mini WWAN/GPS/LTE/mSATA/PP H=4
+3.3V_WLAN
+3.3V_mSATA_WWAN
<37>
<12,7>
PCIE_WAKE#
MINI1CLK_REQ#
MINI1CLK_REQ#
<7>
<7>
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
D
JMINI1
C244 1
C245 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
<36>
SATA_PTX_mSATARX_N3_C
SATA_PTX_mSATARX_P3_C
HW_GPS_DISABLE2#
53
GND1
GND2
<12,7>
MINI2CLK_REQ#
+SIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
<7>
<7>
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
<36,37>
<37>
WWAN_RADIO_DIS#
MINI_CARD_RST#
<11>
<11>
WWAN_SMBCLK
WWAN_SMBDAT
<11>
<11>
USBP6USBP6+
EC5048_TX
MSCLK
<36>
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
C242 1
C243 1
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
<11>
<11>
<12>
PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_C
CPPE#
LED_WWAN_OUT#
mSATA_DEVSLP
<12>
<7>
<7>
<7>
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
@ R223 1
2 0_0402_5%
BT_RADIO_DIS#_R
53
54
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
MSDATA
C241
2
4700P_0402_25V7K
HOST_DEBUG_TX
<37>
WLAN_RADIO_DIS#_R
MINI_CARD_RST#
D
WIGIG60GHZ_DIS#_R
USBP2USBP2+
CPUSB#
WIMAX_LED#
WLAN_LED#
BT_LED#
1
@ R222
<11>
<11>
<12>
2
0_0402_5%
MSDATA
<37>
54
LCN_DAN08-52406-0500
CONN@
LCN_DAN08-52406-0500
CONN@
+3.3V_mSATA_WWAN
+3.3V_WLAN
1
@ R215
+3.3V_mSATA_WWAN
2
WIGIG60GHZ_DIS#_R
1
2
2
1
2
1
1
1
2
0_0402_5%
1
WIGIG60GHZ_DIS#
1
1
@ R224
<36>
2
1
1
2
2
2
1
1
2
2
1
1
2
2
1
2
2
D12
RB751S40T1G_SOD523-2
C262
4.7U_0603_6.3V6K
WLAN_RADIO_DIS#_R
C261
0.1U_0402_25V6
WLAN_RADIO_DIS#
2
C260
0.1U_0402_25V6
1
+
@ C254
150U_B2_6.3VM_R35M
0_0402_5%
3@ C253
150U_B2_6.3VM_R35M
C252
33P_0402_50V8J
C251
22U_0805_6.3V6M
C250
33P_0402_50V8J
WWAN_SMBCLK
C249
0.047U_0402_16V4Z
DDR_XDP_WAN_SMBDAT
1
C248
0.047U_0402_16V4Z
<18,19,25,7,9>
2
@ R218
2
@ R219
@ R217
2.2K_0402_5%
DDR_XDP_WAN_SMBCLK
+
1
C259
0.047U_0402_16V4Z
<36>
@ R216
2.2K_0402_5%
<18,19,25,7,9>
2
0_0402_5%
+3.3V_mSATA_WWAN
C258
0.047U_0402_16V4Z
mSATA_DEVSLP
10K_0402_5%
1
2
@C257
0.1U_0402_25V6
1
@ R160
2
SATA_PTX_MSATARX_N3
SATA_PTX_MSATARX_P3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
<6>
<6>
SATA_PRX_MSATATX_P3
SATA_PRX_MSATATX_N3
SATA_PRX_MSATATX_P3
SATA_PRX_MSATATX_N3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
PCIE_WAKE#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
<6>
<6>
+3.3V_WLAN
+3.3V_mSATA_WWAN
JMINI2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
PCIE_WAKE#
D13
RB751S40T1G_SOD523-2
WWAN_SMBDAT
1
@ R225
0_0402_5%
C
<36>
2
0_0402_5%
1
BT_RADIO_DIS#
2
C
BT_RADIO_DIS#_R
D14
RB751S40T1G_SOD523-2
PWR
Rail
Primary Power
Voltage
Tolerance
Aux Power
Peak
Normal
+3.3V
+-9%
1000
750
+3.3Vaux
+-9%
330
250
Normal
250 (Wake enable)
5 (Not wake enable)
SIM Card Push-Push
+SIM_PWR
1
2
1
2
R50
11
12
13
14
15
16
17
18
R51
LED control circuit
MCARD_WWAN_PWREN
100K_0402_5%
AUX_EN_WOWL
100K_0402_5%
+3.3V_WLAN
B
+3.3V_ALW
+3.3V_mSATA_WWAN
@ U28
5
3
4
VOUT2
VOUT2
C409
9
8
+SIM_PWR
1
5
2
1
2
1
2
2
MINI_CARD_RST#
1
G
4
2
3
A
@ U30
TC7SH08FU_SSOP5~D
A
0.1U_0402_25V6
O
2
MPCIE_RST#
C338
2
@ R26
100K_0402_5%
<12,6>
B
5
2
1
P
1
6
6
+3.3V_mSATA_WWAN
@
1
PCH_PLTRST#_EC
<36,40>
Q30A
DMN66D0LDW-7_SOT363-6
2 0_0402_5%
+3.3V_RUN
<29,36,37,9>
WIRELESS_LED#
Q22A
DMN66D0LDW-7_SOT363-6
LED_WWAN_OUT#
R226
100K_0402_5%
@ C267
33P_0402_50V8J
@ C266
33P_0402_50V8J
@ C265
33P_0402_50V8J
@ C264
33P_0402_50V8J
1
@ R232 1
SRV05-4.TCT_SOT23-6~D
BT_LED#
UIM_DATA
3
Q22B
DMN66D0LDW-7_SOT363-6
1
WLAN_LED#
2
UIM_VPP
4
WIMAX_LED#
+3.3V_WLAN
15
GPAD
TPS22966DPUR_SON14_2X3
UIM_CLK
2
470P_0402_50V7K
1
1
2
2
470P_0402_50V7K
10
1
6
2
CT2
VIN2
VIN2
C427 1
11
2
1
ON2
12
@ C422
0.1U_0402_10V7K
UIM_RESET
GND
2
6
7
CT1
VBIAS
5
AUX_EN_WOWL
ON1
2
<36>
5
1
4
+5V_ALW
2
0.1U_0402_10V7K
R228
100K_0402_5%
3
MCARD_WWAN_PWREN
VOUT1
VOUT1
1
@ C425
R227
100K_0402_5%
<36>
T-SOL_159-1000302602
VIN1
VIN1
14
13
2
U3
1
2
R229
100K_0402_5%
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
1
UIM_VPP
UIM_DATA
VCC
RST
CLK
D+
GND_1
VPP
I/O
DDET
COM
1
2
B
3@ C263
1U_0402_6.3V6K
1
JSIM1 CONN@
1
2
3
4
5
6
7
8
9
10
UIM_RESET
UIM_CLK
4
3
Q30B
DMN66D0LDW-7_SOT363-6
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Mini Card
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
31
of
58
5
4
3
2
1
D
D
1
2
1
2
1
2
1
2
1
2
1
2
2
C416
0.1U_0402_25V6
C414
0.1U_0402_25V6
@ C417
0.1U_0402_25V6
<11>
<11>
<11>
<11>
<11>
<11>
C415
0.1U_0402_25V6
@ C418
0.1U_0402_25V6
@ C419
0.1U_0402_25V6
C
C420
4.7U_0603_6.3V6K
1
+3.3V_SUS
U33
3
9
12
16
20
29
1
2
4
5
6
7
8
USB3TP3
USB3TN3
USB3RP3
USB3RN3
USBP5+
USBP5-
VDD
VDD
VDD
VDD
VDD
VDD
TX+A
TX-A
RX+A
RX-A
D+A
D-A
USB_IDA
TX+B
TX-B
RX+B
RX-B
D+B
D-B
USB_IDB
TX+
TXRX+
RXD+
DUSB_ID
OE#
<21,27,28,36>
DOCKED
10
32
SS_SEL
HS_SEL
GND
GND
HGND
31
30
27
26
19
18
17
SW_USB3TP3
SW_USB3TN3
SW_USB3RP3
SW_USB3RN3
SW_USBP5+
SW_USBP5-
<33>
<33>
<33>
<33>
<33>
<33>
25
24
23
22
15
14
13
DOCK_USB3TP3
DOCK_USB3TN3
DOCK_USB3RP3
DOCK_USB3RN3
DOCK_USBP5+
DOCK_USBP5-
<34>
<34>
<34>
<34>
<34>
<34>
C
11
21
28
33
PI3USB3102ZLEX_TQFN32_6X3
check port mapping
DOCKED
B
function
1
Dock
0
M/B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB SW
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
32
of
58
5
4
3
2
1
+USB_PWR
JUSB2
USB3RP3_D+
2
8
USB3RP3_D+
USB3TN3_D-
4
7
USB3TN3_D-
USB3TP3_D+
5
6
USB3TP3_D+
1
@ R235
1
@ R236
D
2
DLW21SN900HQ2L-0805_4P
2
0_0402_5%
2
3
0_0402_5%
+
USBP5_DUSBP5_D+
USB3RN3_DUSB3RP3_D+
2
USB3RN3_D-
1
TVWDF1004AD0_DFN9
L38 EMC@
<32>
SW_USB3TN3
<32>
SW_USB3TP3
2
1
SW_USB3TN3_C
0.1U_0402_10V7K
4
2
1
SW_USB3TP3_C
0.1U_0402_10V7K
1
C282
D16 EMC@
L30ESDL5V0C3-2_SOT23-3
9
3
USB3RP3_D+
1
1
2
USB3RN3_D-
2
2
USB3RN3_D-
1
1
3
1
1
3
C281
0.1U_0402_25V6
SW_USB3RP3
1
2
3
4
5
6
7
8
9
D15 EMC@
4
@ C280
150U_D2_6.3VY_R15M
<32>
4
C86
100U_1206_6.3V6M
SW_USB3RN3
2
L37 EMC@
<32>
USB3TN3_DUSB3TP3_D+
CONN@
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
GND
GND
GND
GND
10
11
12
13
D
SANTA_373070-1
L39 EMC@
4
3
1
2
3
USB3TN3_D-
2
USB3TP3_D+
<32>
SW_USBP5+
<32>
SW_USBP5-
1
1
2
4
3
2
USBP5_D+
3
USBP5_D-
+USB_PWR
+5V_ALW
U32
1
2
3
4
DLW21HN900SQ2L_4P
<36>
1
2
0_0402_5%
2
0_0402_5%
2
1
@ R238
1
@ R240
C285
0.1U_0402_25V6
2
0_0402_5%
2
0_0402_5%
C284
10U_0603_6.3V6M
1
@ R237
1
@ R239
1
DLW21SN900HQ2L-0805_4P
2
C283
4
ESATA_USB_PWR_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC2#
<11,12>
G547I2P81U_MSOP8
C
C
1
R243
100K_0402_5%
2
+5V_ALW
PWRSHARE_EN#
0_0402_5%
CEN
DM
DP
SELCDP
Thermal Pad
1
2
3
4
9
S
2
G
PWRSHARE_EN
PS_USBP0_DPS_USBP0_D+
SEL
SLGC55594AVTR_TDFN8_2X2
1
<34>
<34>
2
DOCK_USBP0+
DOCK_USBP0-
JUSB1 CONN@
+5V_ALW
SEL
10K_0402_5%
1
2
R244
check port mapping
B
DOCKED_LIO_EN
+
USB3RN2_DUSB3RP2_D+
function
Dock
0
M/B
1
1
1
2
3
4
5
6
7
8
9
USBP0_DUSBP0_D+
D18 EMC@
L30ESDL5V0C3-2_SOT23-3
2
NX3DV221GM_XQFN10U10_2X1P55
+5V_USB_CHG_PWR
C291
0.1U_0402_25V6
2
SW_USBP0+
SW_USBP0-
@ C290
150U_D2_6.3VY_R15M
1
2
3
4
5
1D+
1D2D+
2DGND
C89
100U_1206_6.3V6M
VCC
S
D+
DOE#
C287
0.1U_0402_25V6
<36>
DOCKED_LIO_EN
<11>
USBP0+
<11>
USBP0-
C322
0.1U_0402_25V6
1
U36
10
9
8
7
6
3
support APR/SPR/LIO Dock
CB
TDM
TDP
VDD
2
+5V_ALW
+3.3V_ALW
8
7
6
5
1
SB#
SW_USBP0SW_USBP0+
2
2
0_0402_5%
1
1
@ R242
2
USB_PWR_SHR_EN#
D
1
<36>
1
2
U39
3
1
@ R241
USB_PWR_SHR_VBUS_EN
Q7
L2N7002WT1G_SC-70-3
<36>
USB3TN2_DUSB3TP2_D+
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAU4-09FLBS1NN4H0
B
D17 EMC@
L40 EMC@
USB3RP2
1
4
3
1
2
3
2
USB3RP2_D+
2
USB3RN2_D-
2
8
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
USB3TP2_D+
5
6
USB3TP2_D+
0_0402_5%
@ R247
+5V_USB_CHG_PWR
+5V_ALW
3
0_0402_5%
2
TVWDF1004AD0_DFN9
C289
0.1U_0402_25V6
2
1
9
USB3RP2_D+
C288
10U_0603_6.3V6M
1
1
U35
DLW21SN900HQ2L-0805_4P
@ R246
USB3RN2_DUSB3RN2_D-
1
<11>
4
2
USB3RN2
1
<11>
PWRSHARE_EN#
1
2
3
4
8
7
6
5
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
USB_OC0#
<11>
G547I2P81U_MSOP8
L42 EMC@
L41 EMC@
<11>
<11>
USB3TN2
USB3TP2
2
C292
2
C293
1 USB3TN2_C
0.1U_0402_10V7K
1 USB3TP2_C
0.1U_0402_10V7K
4
1
4
1
3
2
3
2
PS_USBP0_D+
1
2
USBP0_D+
PS_USBP0_D-
4
3
USBP0_D-
USB3TN2_DUSB3TP2_D+
CMM0805-120Y-N_4P
DLW21SN900HQ2L-0805_4P
A
1
@ R248
1
@ R250
1
@ R249
1
@ R251
2
0_0402_5%
2
A
2
0_0402_5%
2
0_0402_5%
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB3.0
Size
Document Number
Rev
0.4
LA-9591P
Date:
Friday, May 17, 2013
Sheet
1
33
of
58
5
4
3
2
1
JDOCK1 CONN@
1 0.1U_0402_10V7K DPC_LANE_P3_C
1 0.1U_0402_10V7K DPC_LANE_N3_C
EMC@
EMC@
R265 1
R266 1
2 33_0402_5% DPC_DOCK_LANE_P3
2 33_0402_5% DPC_DOCK_LANE_N3
<24>
<24>
DPC_DOCK_AUX
DPC_DOCK_AUX#
DPC_DOCK_HPD
2
Close to DOCK
Its for Enhance ESD on
dock issue.
+NBDOCK_DC_IN_SS
@ C310
0.033U_0402_16V7K
1
DPC_DOCK_HPD
<21>
<21>
DPC_DOCK_HPD
2
GREEN_DOCK
HSYNC_DOCK
VSYNC_DOCK
<37>
<37>
CLK_MSE
DAT_MSE
<26>
<26>
DAI_BCLK#
DAI_LRCK#
<26>
<26>
DAI_DI
DAI_DO#
<26>
DAI_12MHZ#
D_LAD0
D_LAD1
<36>
<36>
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
CLK_PCI_DOCK
<37>
DOCK_SMB_CLK
DOCK_SMB_DAT
DOCK_SMB_ALERT#
<41>
DOCK_PSID
<37>
DOCK_PWR_BTN#
SLICE_BAT_PRES#
SLICE_BAT_PRES#
145
146
147
2
3
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
GND2
PWR2
PWR2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
DPB_DOCK_LANE_P3
DPB_DOCK_LANE_N3
EMC@
EMC@
R258 1
R267 1
2 33_0402_5% DPB_LANE_P3_C
2 33_0402_5% DPB_LANE_N3_C
C308 2
C309 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPB_DOCK_AUX
DPB_DOCK_AUX#
<24>
<24>
ACAV_DOCK_SRC#
<48>
DAT_DDC2_DOCK
CLK_DDC2_DOCK
2
C312 2
C313
1
C314 1
C315
SATA_PRX_DKTX_P0
SATA_PRX_DKTX_N0
SATA_PTX_DKRX_P0
SATA_PTX_DKRX_N0
DOCK_USBP0_D+
DOCK_USBP0_DDOCK_USBP5+
DOCK_USBP5CLK_KBD
DAT_KBD
<21>
<21>
1
1 0.01U_0402_16V7K
0.01U_0402_16V7K
2
2 0.01U_0402_16V7K
0.01U_0402_16V7K
2
2
3
<32>
<32>
<37>
<37>
DOCK_USB3RN3
DOCK_USB3RP3
<32>
<32>
DOCK_USB3TN3
DOCK_USB3TP3
<32>
<32>
SATA_PRX_DKTX_P0_C
SATA_PRX_DKTX_N0_C
SATA_PTX_DKRX_P0_C
SATA_PTX_DKRX_N0_C
1
1
3
4
<21>
<21>
DPB_LANE_P3
DPB_LANE_N3
<21>
<21>
DPB_DOCK_HPD
<21>
<6>
<6>
DOCK_USBP0+
<33>
DOCK_USBP0-
<33>
C
EMI solution for E-Docking USB
DPB_DOCK_HPD
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
<28>
<28>
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
<28>
<28>
<28>
+3.3V_ALW
+LOM_VCT
+LOM_VCT
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
<28>
<28>
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
<28>
<28>
DOCK_DCIN_IS+
DOCK_DCIN_ISDOCK_POR_RST#
<21>
<21>
DPB_LANE_P2
DPB_LANE_N2
D
Close to DOCK
Its for Enhance ESD on dock
issue.
<6>
<6>
4
DPB_LANE_P1
DPB_LANE_N1
DLW21SN900SQ2L-0805_4P
@ L43
2
1
@ R269
0_0402_5%
2
1
@ R270
0_0402_5%
BREATH_LED#
<36,40>
DOCK_LOM_ACTLED_YEL#
1
DOCK_DET#
10K_0402_5%
2
R272
<47>
<47>
B
<37>
D19
1
DOCK_DET_R#
148
149
150
157
158
159
160
161
162
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
2
DOCK_DET#
<36,48>
RB751S40T1G_SOD523-2
+DOCK_PWR_BAR
DAI_12MHZ#
1
CLK_PCI_DOCK
@ C319
@ R273 12P_0402_50V8J
33_0402_5%
@ CE9
@ RE5
4.7P_0402_50V8C
10_0402_1%
2
DAI_BCLK#
@ CE8
@ RE4
4.7P_0402_50V8C
10_0402_1%
WD2F144WB7
JAE_WD2F144WB7-DT
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2
1
1
2
2
151
152
153
154
155
156
GND1
PWR1
PWR1
C305 2
C307 2
C318
0.1U_0603_50V7K
D20 @
L30ESD24VC3-2_SOT23-3
C317
0.1U_0603_50V7K
@ CE7
4.7U_0805_25V6-K
1
+DOCK_PWR_BAR
2 33_0402_5% DPB_LANE_P2_C
2 33_0402_5% DPB_LANE_N2_C
@ C316
1U_0402_6.3V6K
D_SERIRQ
D_DLDRQ1#
<7>
<37>
<36,41,48>
GREEN_DOCK
R262 1
R264 1
<21>
<21>
R271
100K_0402_5%
<36>
<36>
<36>
<36>
<36,41,48>
RED_DOCK
RED_DOCK
<21>
<21>
<36>
<36>
B
BLUE_DOCK
<21>
R268
100K_0402_5%
1
C
BLUE_DOCK
EMC@
EMC@
C311
0.033U_0402_16V7K
<21>
DPC_DOCK_AUX
DPC_DOCK_AUX#
DPB_DOCK_LANE_P2
DPB_DOCK_LANE_N2
DPB_LANE_P0
DPB_LANE_N0
1
C300 2
C301 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2
2 33_0402_5% DPC_DOCK_LANE_P2
2 33_0402_5% DPC_DOCK_LANE_N2
C298 2
C303 2
1
R257 1
R263 1
2 33_0402_5% DPB_LANE_P1_C
2 33_0402_5% DPB_LANE_N1_C
@
EMC@
EMC@
R254 1
R256 1
2
1 0.1U_0402_10V7K DPC_LANE_P2_C
1 0.1U_0402_10V7K DPC_LANE_N2_C
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
EMC@
EMC@
1
C304 2
C306 2
C294 2
C296 2
DPB_DOCK_LANE_P1
DPB_DOCK_LANE_N1
2
2 33_0402_5% DPC_DOCK_LANE_P1
2 33_0402_5% DPC_DOCK_LANE_N1
1
R253 1
R255 1
2
DPC_LANE_P3
DPC_LANE_N3
EMC@
EMC@
<28>
2 33_0402_5% DPB_LANE_P0_C
2 33_0402_5% DPB_LANE_N0_C
1
<21>
<21>
1 0.1U_0402_10V7K DPC_LANE_P1_C
1 0.1U_0402_10V7K DPC_LANE_N1_C
DPB_DOCK_LANE_P0
DPB_DOCK_LANE_N0
2
DPC_LANE_P2
DPC_LANE_N2
C297 2
C299 2
DOCK_AC_OFF
<48>
DOCK_LOM_SPD100LED_ORG#
DPB_CA_DET
<21,24>
EMC@
R260 1
EMC@
R261 1
DPB_CA_DET
1
DPC_LANE_P1
DPC_LANE_N1
<21>
<21>
1 0.1U_0402_10V7K DPC_LANE_P0_C
1 0.1U_0402_10V7K DPC_LANE_N0_C
DOCK_AC_OFF
2
<21>
<21>
C302 2
C295 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
DPC_LANE_P0
DPC_LANE_N0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
<21>
<21>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
D
DOCK_LOM_SPD10LED_GRN#
DPC_CA_DET
<21,24>
DPC_CA_DET
2 33_0402_5% DPC_DOCK_LANE_P0
EMC@
R259 1
2 33_0402_5% DPC_DOCK_LANE_N0
EMC@
R252 1
1
<28>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
2
DOCK_DET_1
EMI depop location
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
E-Dock
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
34
of
58
5
4
3
2
1
T94
SW_LAN_TX1- 1
<28>
SW_LAN_TX1-
<28>
SW_LAN_TX1+
1:1
TD1+
TX1+
24 NB_LAN_TX1+3.3V_LAN
TX1TXCT1
TDCT2
TD2+
TXCT2
TX2+
21 Z2807
20 NB_LAN_TX0-
2
1:1
22 Z2805
1
2
2
SW_LAN_TX0-
TDCT1
<28>
SW_LAN_TX0+ 6
SW_LAN_TX0+
TD2-
TX2-
TD3TX3-
9
SW_LAN_TX2-
TXCT3
TDCT4
TD4+
TXCT4
TX4+
1:1
SW_LAN_TX2+12
SW_LAN_TX2+
TD4-
TX4-
2
R274
10
LAN_ACTLED_YEL_R#
150_0402_5%
18 NB_LAN_TX3-
9
NB_LAN_TX3-
8
NB_LAN_TX3+
7
NB_LAN_TX1-
6
16 Z2806
NB_LAN_TX2-
5
NB_LAN_TX2+
4
15 Z2808
14 NB_LAN_TX2-
NB_LAN_TX1+
3
NB_LAN_TX0-
2
13 NB_LAN_TX2+
NB_LAN_TX0+
1
1
1
350uH_IH-115-F
1
1
<28>
<28>
LED_10_GRN#
LED_100_ORG#
1
R275
1
R276
2
2
Yellow LED+
PR4PR4+
PR2PR3PR3+
PR2+
C
PR1GND
PR1+
GND
11
LED_10_GRN_R#
150_0402_5%
LED_100_ORG_R#
150_0402_5%
CONN@
Yellow LED-
17 NB_LAN_TX3+
1
<28>
2
C326
0.47U_0603_10V7K
C325
0.47U_0603_10V7K
<28>
10
SW_LAN_TX2-11
TDCT3
1
LAN_ACTLED_YEL#
75_0402_1%
TX3+
75_0402_1%
SW_LAN_TX3+ 8
SW_LAN_TX3+
1:1
TD3+
75_0402_1%
SW_LAN_TX3- 7
SW_LAN_TX3-
75_0402_1%
<28>
1
+3.3V_LAN:20mils
JLOM1
<28>
2
RJ45 LOM circuit
19 NB_LAN_TX0+
<28>
C
C321
0.1U_0402_10V7K
<28>
4
SW_LAN_TX0- 5
C320
470P_0402_50V7K
C324
0.47U_0603_10V7K
C323
0.47U_0603_10V7K
1
3
D
23 NB_LAN_TX1+
1
TD1-
2
SW_LAN_TX1+ 2
1
D
15
14
Green LED-
13
Orange LED-
12
Green-Orange LED+
GND
CHASSIS
2
R476
1
10
3.01K_0402_1%
3
13
21
EQ0
DE
REXT
GND
GND
GND
EQ1
EQ_INC#
PD#
I2C_EN
NC
NC
NC
USB3RN1_RPC335 2
USB3RP1_RPC286 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
R280 2
R279 2
USB3RN1
USB3RP1
<11>
<11>
<11>
<11>
<11>
<11>
12
17
11
EQ1
1
4.7K_0402_5%
USB3TP1
USB3TN1
USBP1+
USBP1USB3RP1_IO
USB3RN1_IO
2 @
@R477
R477
<36,40>
20
5
7
8
9
<26,36>
<26>
PS8711BTQFN20GTR-A0_TQFN20_3X3
LID_CL#
+3.3V_ALW
AUD_HP_NB_SENSE
+3.3V_RUN
AUD_HP_OUT_R
<26>
<26>
RING2
SLEEVE
<26>
AUD_HP_OUT_L
+5V_ALW
+3.3V_ALW
+3.3V_RUN
1
19
18
NC
15
14
2
EQ0
DE
NC
16
1
1
DE
4.7K_0402_5%
OUTn
OUTp
2
@ R480 2
VDD
INn
INp
B
@ C77
0.1U_0402_16V4Z
4
VDD
WIRELESS_ON#/OFF
<11>
USB_OC1#
<36>
USB_SIDE_EN#
@ C4
0.1U_0402_16V4Z
1
EQ1
4.7K_0402_5%
1
2
<36>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
GND
1
1
U51
6
USB3RN1_IO
USB3RP1_IO
JIO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
@ C50
0.1U_0402_16V4Z
R479 2
1
EQ0
4.7K_0402_5%
+5V_ALW
2
R478 2
I/O CONN
+3.3V_RUN
2
+3.3V_RUN
+GND_CHASSIS
C381
0.1U_0402_10V7K
B
2
EMC@
150P_1808_2.5KV8J
use 40mil trace if necessary
+3.3V_RUN
C395
0.01U_0402_16V7K
2
1
USB3.0 repeater
1
C327
R278 2
R277 2
rev1
SANTA_130456-341
ACES_50506-02641-P01
CONN@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
RJ45 & I/O
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
35
of
58
5
4
3
+3.3V_ALW
2
1
+3.3V_ALW_U37
PJP6
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
R289
R291
R292
R293
R295
R298
@R302
@
R302
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WWAN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
<35>
<26>
<29>
<48>
<22>
<10,22>
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
<22>
LCD_TST
<41>
PSID_DISABLE#
<41,48>
PBAT_PRES#
<21,27,28,32>
DOCKED
<34,48>
DOCK_DET#
<26>
AUD_NB_MUTE#
<31>
MCARD_WWAN_PWREN
<22>
LCD_VCC_TEST_EN
<22>
CCD_OFF
<26,35>
AUD_HP_NB_SENSE
<33>
ESATA_USB_PWR_EN#
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
+3.3V_RUN
C
1
2
1
2
@ R304
R309
1
R310
1
R313
<48>
<34,41,48>
SP_TPM_LPC_EN
10K_0402_5%
MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
@ T106 PAD~D
SLICE_BAT_ON
SLICE_BAT_PRES#
@ T107 PAD~D
CHARGE_PBATT
@ T110 PAD~D
LCD_TST
100K_0402_5%
2
SYS_LED_MASK#
10K_0402_5%
2
CHARGE_EN
100K_0402_5%
<31>
<31,37>
<6>
<9>
WIGIG60GHZ_DIS#
EC5048_TX
WIGIG60GHZ_DIS#
EC5048_TX
mCARD_PCIE_SATA#
CPU_DETECT#
XFR_ID_BIT#
MCARD_PCIE_SATA#
CPU_DETECT#
DP_HDMI_HPD
@ T115 PAD~D
<29>
BCM5882_ALERT#
BCM5882_ALERT#
<9>
SUSACK#
@ T118 PAD~D
EDID_SELECT#
VGA_ID
<12>
B
<33>
SLP_ME_CSW_DEV#
SLP_ME_CSW_DEV#
<28>
LAN_DISABLE#_R
<40>
SYS_LED_MASK#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
ALS_INT#
SIO_EXT_WAKE#
WIRELESS_LED#
<12>
SIO_EXT_WAKE#
<31,40>
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
<31>
WLAN_RADIO_DIS#
<35>
<31>
<31>
<9>
<9>
PCH_DPWROK
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
DGPU_SELECT#
CPU_VTT_ON
2 0_0402_5%
@ R319 1
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
BC_INT#
BC_DAT
BC_CLK
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
1
1
2
1
2
2
SIO_SLP_A#
<39,44,9>
SIO_SLP_S4#
SIO_SLP_S3#
IMVP_PWRGD
IMVP_VR_ON
DOCK_AC_OFF_EC
B67
A64
A5
B6
A6
B7
A7
B8
AUX_EN_WOWL
A8
B9
B10
A10
B11
A11
B12
A12
ME_FWP
MASK_SATA_LED#
USB_PWR_SHR_EN#
LED_SATA_DIAG_OUT#
B60
A57
B64
B68
A9
B1
A18
A44
SUS_ON
B34
B39
B51
HW_GPS_DISABLE2#
BREATH_LED#
A27
A26
B26
B25
A21
B22
A28
B20
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
CLK_PCI_5048
CLKRUN#
A22
B21
A32
B35
LPC_LDRQ1#
IRQ_SERIRQ
B29
B28
A25
A24
B23
A19
B24
A20
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
A29
B31
A30
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
A4
RUNPWROK
B56
SP_TPM_LPC_EN
SIO_SLP_LAN#
SIO_SLP_SUS#
MODC_EN
DOCK_HP_DET
DOCK_MIC_DET
<39,43,9>
<39,43,9>
<46>
<46>
<48>
AUX_EN_WOWL
<31>
WLAN_LAN_DISB#
<28>
SIO_SLP_LAN#
<28,9>
SIO_SLP_SUS#
<9>
GPIO_PSID_SELECT
<41>
PAD~D T101 @
DOCK_HP_DET
<26>
DOCK_MIC_DET
<26>
ME_FWP
<6>
MASK_SATA_LED#
USB_PWR_SHR_EN#
LED_SATA_DIAG_OUT#
RUN_ON
BAT1_LED#
BAT2_LED#
<39,43>
BAT1_LED#
<40> trace width 20 mils
BAT2_LED#
<40> trace width 20 mils
USH_PWR_ON
PAD~D T100 @
FP_POA_EN
OUT65
IRQ_SERIRQ
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
100K_0402_5%
C
1
100K_0402_5%
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
B
<37>
<37>
<37>
B19
B46
B27
C1
1
R321
+CAP_LDO
RUNPWROK
2
1K_0402_5%
<37,9>
SP_TPM_LPC_EN
<29>
+CAP_LDO trace width 20 mils
2
R325
LID_CL_SIO#
1
LID_CL#
10_0402_1%
<35,40>
CLK_PCI_5048
2
1
2
2
1
2
1
1
@ R320
100K_0402_5%
2
100K_0402_5%
<37>
@ C339
@ R324
33P_0402_50V8J
33_0402_5%
R317
100K_0402_5%
@ R326
1K_0402_5%
0
100K_0402_5%
1
<12,29,37>
EMI depop location
VGA_ID0
1
1
LPC_LAD0
<29,37,7>
LPC_LAD1
<29,37,7>
LPC_LAD2
<29,37,7>
LPC_LAD3
<29,37,7>
LPC_LFRAME#
<29,37,7>
PCH_PLTRST#_EC
<29,31,37,9>
CLK_PCI_5048
<7>
CLKRUN#
<12,29,37,9>
VGA_ID
UMA
2
R303
2
R305
SLICE_BAT_ON 2
R307
2
SUS_ON
R308
HW_GPS_DISABLE2#
<31>
BREATH_LED#
<34,40>
DIS_BAT_PROCHOT#
<48>
+3.3V_ALW
Discrete
1
CPU_VTT_ON
C337
0.047U_0402_16V4Z
VSS
EP
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
ME_FWP
RUN_ON
<39>
EC_32KHZ_ECE5048
C336
4.7U_0603_6.3V6K
CAP_LDO
A
100K_0804_8P4R_5%
+3.3V_ALW
PWRGD
TEST_PIN
ME_FWP PCH has internal 20K PD.
(suspend power rail)
8
7
6
5
<40>
<33>
<40>
RUN_ON
<26,37,39>
AC_DIS
<41,48>
SPI_WP#_SEL
<7>
SUS_ON
+3.3V_RUN
RP8
1
2
3
4
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
LPC_LDRQ1#
R322
100K_0402_5%
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
<9>
SYS_PWROK
@ T121 PAD~D
SIO_SLP_WLAN#
WLAN_RADIO_DIS#
B32
A31
B33
B15
A15
B16
A16
1
1
2
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
SIO_SLP_A#
1
2
1
R288
DOCK_SMB_ALERT#
@ T98 PAD~D
A23
B63
A60
A61
B65
A62
B66
A63
2
1
R287
<34,41,48>
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
1
R286
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
2
2
<47>
B52
A49
B53
A50
B54
A51
B55
A52
1
1
R285
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
@ T97 PAD~D
PROCHOT_GATE
1
2
DOCKED_LIO_EN
2
1
<33>
D
B5
A17
B30
A43
A54
2
R284
VCC1
VCC1
VCC1
VCC1
VCC1
1
2
2
1
R283
U37
C332
0.1U_0402_25V6
1
R282
ALS_INT#
10K_0402_5%
HW_GPS_DISABLE2#
100K_0402_5%
PROCHOT_GATE
100K_0402_5%
CPU_DETECT#
100K_0402_5%
SLICE_BAT_PRES#
100K_0402_5%
WWAN_RADIO_DIS#
100K_0402_5%
USB_PWR_SHR_EN#
100K_0402_5%
USB_SIDE_EN#
10K_0402_5%
WIGIG60GHZ_DIS#
100K_0402_5%
USB_PWR_SHR_VBUS_EN
100K_0402_5%
DOCK_SMB_ALERT#
100K_0402_5%
WIRELESS_ON#/OFF
100K_0402_5%
ESATA_USB_PWR_EN#
100K_0402_5%
BT_RADIO_DIS#
100K_0402_5%
XFR_ID_BIT#
100K_0402_5%
C331
0.1U_0402_25V6
2
C334
0.1U_0402_10V7K
2
1
C330
0.1U_0402_25V6
1
R281
C329
0.1U_0402_25V6
C328
10U_0603_6.3V6M
+3.3V_ALW
D
2
PAD-OPEN1x1m
2
1
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ECE5048
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
36
of
58
4
3
2
1
2
2
<34>
DOCK_POR_RST#
<12>
EC_WAKE#
<39,44>
A_ON
<39>
PCH_ALW_ON
<22>
BIA_PWM_EC
100K_0804_8P4R_5%
1
2
1
2
R366
R371
1
2
@ R373
<36>
EC_32KHZ_ECE5048
MEC_XTAL2 2
@ R378 1
@ R379
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
A6
A27
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
MEC_XTAL1
1
MEC_XTAL2_R
2 0_0402_5%
0_0402_5%
A61
A62
B62
GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO032/BCM_E_CLK
GPIO031/GPTP-OUT2/BCM_E_DAT
GPIO030/GPTP-IN2/BCM_E_INT#
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT
GPIO045/LSBCM_D_INT#
2
MEC_XTAL2
1
B66
2
1
2
1
2
2
2
2
1
2
1
1
1
1
1
VREF_PECI
PECI_DAT
DN1-THERM
DP1-VREF_T
DN2
DP2
DN3
DP3
DN4
DP4
VIN
VSET
VCP
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
V_ISYS
<40>
1
VOL_DOWN
PS_ID
<41>
ALW_PWRGD_3V_5V
<42>
1.05V_A_PWRGD
1.05V_A_PWRGD
<44>
1
2
VOL_MUTE
<40>
R352
1K_0402_5%
ME_SUS_PWR_ACK
1.35V_SUS_PWRGD
1.35V_SUS_PWRGD
<43>
PM_APWROK
PM_APWROK
<9>
RESET_OUT#
RESET_OUT#
<15,9>
PCH_PCIE_WAKE#
PCH_PCIE_WAKE#
<9>
PCH_RSMRST#
PCH_RSMRST#
<38>
AC_PRESENT
AC_PRESENT
<9>
SIO_PWRBTN#
SIO_PWRBTN#
<9>
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
USH_SMBDAT
USH_SMBCLK
DOCK_SMB_DAT
DOCK_SMB_CLK
1
3
S
H_PROCHOT#
<46,47,48,9>
+3.3V_ALW
<9>
DYN_TUR_CURRNT_SET#
100K_0402_5%
BAY_SMBDAT
2.2K_0402_5%
BAY_SMBCLK
2.2K_0402_5%
DDR_HVREF_RST_GATE
100K_0402_5%
2
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
1
2
3
4
1
R363
2
1
2
1
2
1
R453
R452
R353
RP15
<34>
<34>
8
7
6
5
2.2K_0804_8P4R_5%
RP16
CHARGER_SMBDAT
CHARGER_SMBCLK
USH_SMBDAT
USH_SMBCLK
<29>
<29>
ACAV_IN
ALWON
POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2#
POA_WAKE#
B51
A48
+PECI_VREF
PECI_EC_R
ACAV_IN
ALWON
<47,48>
<42>
C
R367
2
1K_0402_5%
RP17
+3.3V_ALW2
R375
PECI_EC
43_0402_5%
C358 1
2 2200P_0402_50V7K
C359 1
2 2200P_0402_50V7K
REM_DIODE4_N
REM_DIODE4_P
C361 1
8
7
6
5
+RTC_CELL
100K_0804_8P4R_5% +3.3V_ALW
2
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
1
2
3
4
THERMATRIP3#
DEVICE_DET#
POA_WAKE#
VCI_IN2#
RP19
R866 close to U38 at least 250mils
1
8
7
6
5
2.2K_0804_8P4R_5%
1
A64
A60
B67
A63
B63
B68
1
2
3
4
GPU_SMBDAT
GPU_SMBCLK
CARD_SMBCLK
CARD_SMBDAT
<47>
<47>
A59
B13
A13
B14
A14
A15
B16
A16
B17
B15
A17
A12
B34
A2
B29
A46
B61
1
2
2 1K_0402_5%
D
2
G
0_0402_5%
1
@ R374
<9>
2
0_0402_5%
1
2
3
4
HOST_DEBUG_RX
CHARGER_SMBDAT
CHARGER_SMBCLK
PCH_RSMRST#
+1.05V_RUN
8
7
6
5
10K_8P4R_5%
2 2200P_0402_50V7K
C283, C285, C286, C287 Place near U38
VSET_5075
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
PROCHOT#_EC
1
2
R381
4.7K_0402_5%
VCP
<47>
V_SYS
<47>
MEC5075-LZY_DQFN132_11X11~D
C366
4.7U_0603_6.3V6K
C365
22P_0402_50V8J
C364
22P_0402_50V8J
@ R384
100_0402_1%
JTAG1 CONN@
@SHORT PADS~D
C362
1U_0402_6.3V6K
15mil
VSS
1
JTAG_RST#
Y4
32.768KHZ_12.5PF_Q13FC135000040
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
XTAL1
XTAL2
GPIO160/32KHZ_OUT
32 KHz Clock
MEC_XTAL1
SYSPWR_PRES
GPIO011/nSMI/GANG_DATA0
GPIO061/LPCPD#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/NEC_SCI
AGND
2
R380
100K_0402_5%
1
+3.3V_ALW
A43
B45
A42
B20
A18
B19
A20
B21
A19
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
FWP#
R349 1
DEVICE_DET#
PS_ID
2
@ R334
PROCHOT#_EC
C360
0.1U_0402_25V6
<12>
SIO_EXT_SMI#
<12>
SIO_RCIN#
<12,29,36>
IRQ_SERIRQ
<29,31,36,9>
PCH_PLTRST#_EC
<7>
CLK_PCI_MEC
<29,36,7>
LPC_LFRAME#
<29,36,7>
LPC_LAD0
<29,36,7>
LPC_LAD1
<29,36,7>
LPC_LAD2
<29,36,7>
LPC_LAD3
<12,29,36,9>
CLKRUN#
<12>
SIO_EXT_SCI#
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
ACAV_IN_NB
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
GPIO003/I2C1A_DATA/GANG_MODE
GPIO004/I2C1A_CLK/GANG_START
GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE
GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL
GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
<47>
R370
100K_0402_5%
<36>
BC_CLK_ECE5048
<36>
BC_DAT_ECE5048
<36>
BC_INT#_ECE5048
<47,48>
ACAV_IN_NB
<9>
SIO_SLP_S5#
<26>
BEEP
<38>
BC_CLK_ECE1117
<38>
BC_DAT_ECE1117
<38>
BC_INT#_ECE1117
B11
C
MSDATA
10K_0402_5%
EN_INVPWR
100K_0402_5%
RESET_OUT#
8.2K_0402_5%
A_ON
PCH_ALW_ON
BIA_PWM_EC
FAN1_PWM
GPIO050/FAN_TACH1/GTACH
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3/GPWM
1
<31>
1
B22
A21
B23
B24
A23
B25
A24
DYN_TUR_CURRNT_SET#
SIO_SLP_S0#
<9>
MSDATA
<31>
MSCLK
<31>
MSDATA
MSCLK
+1.05V_RUN
2
BC_DAT_ECE1117
PCH_ALW_ON
DOCK_POR_RST#
A_ON
B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
A44
B47
A54
B58
SYSTEM_ID
BOARD_ID
2 1K_0402_5%
R338 1
VOL_UP
<40>
LAN_WAKE#
LAN_WAKE#
<12,28>
HOST_DEBUG_TX
HOST_DEBUG_TX
<31>
HOST_DEBUG_RX
RUNPWROK
RUNPWROK
<36,9>
EN_INVPWR
EN_INVPWR
<22>
PCH_SATA_MOD_EN#
PAD~D T123 @
SLICE_PERF_EN
<48>
PCIE_WAKE#
PCIE_WAKE#
DDR_HVREF_RST_GATE
1
1
2
3
4
EP
FAN1_TACH
DOCK_POR_RST#
RP18
8
7
6
5
H_VSS
A51
B55
B56
A53
A57
C1
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
VSS_RO
A5
B6
A37
B40
A38
B41
A39
B42
B59
A56
B18
+3.3V_ALW
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
VR_CAP
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
B54
<38>
<38>
<34>
<34>
<34>
<34>
<41>
<41>
VSS_ADC
1
1
1
1
1
1
2
2
2
2
2
2
1
R376
2
2
<7>
<7>
A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65
@ R342
100K_0402_5%
2
1
C351
0.1U_0402_25V6
2
1
R408
C356
0.1U_0402_25V6
2
1
@ R362
PAD-OPEN1x1m
C355
0.1U_0402_25V6
1
@ R360
VOL_MUTE
100K_0402_5%
VOL_DOWN
100K_0402_5%
VOL_UP
100K_0402_5%
FAN1_PWM
10K_0402_5%
FAN1_TACH
10K_0402_5%
C350
0.1U_0402_25V6
2
C354
0.1U_0402_25V6
1
2
@C349
0.1U_0402_25V6
C348
10U_0603_6.3V6M
4.7K_8P4R_5%
+3.3V_RUN
@ R358
B3
A11
A26
B35
A41
A52
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
H_VTR
GPIO025/UART_CLK
GPIO120/UART_TX
GPIO124/GPTP-OUT5/UART_RX
VTR_ADC
VCC_PWRGD
GPIO060/KBRST/BCM_B_INT#
GPIO101/ECGP_SCLK/GANG_DATA5
VTR
GPIO103/ECGP_MISO/GANG_DATA7
VTR
GPIO105/ECGP_MOSI
VTR
GPIO102/BCM_C_INT#/GANG_DATA6
VTR
GPIO104
VTR
GPIO106
VTR
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO117/MSCLK/V2P_COUT_HI
GPIO127/A20M
NFWP
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR
GPIO110/PS2_CLK2/GPTP-IN6
GPIO156/LED0
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO157/LED1
GPIO112/PS2_CLK1A
GPIO153/LED2
GPIO113/PS2_DAT1A
GPIO027/GPTP-OUT1
GPIO114/PS2_CLK0A
GPIO026/GPTP-IN1
GPIO115/PS2_DAT0A
GPIO001/ECSPI_CS1
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO015/GPTP-OUT7/GANG_DATA3
GPIO155/I2C1C_CLK/PS2_DAT1B
GPIO016/GPTP-IN8/GANG_DATA4
GPIO017/GPTP-OUT8
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO107/NRESET_OUT
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO125/GPTP-IN5
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO126
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
GPIO151/GPTP-IN4
JTAG_RST#
GPIO152/GPTP-OUT4
+VR_CAP B12
2
+3.3V_ALW_U38
A58
PJP7
1
<34>
@ Q9
L2N7002WT1G_SC-70-3
+3.3V_ALW
DOCK_PWR_BTN#
@ R335
10K_0402_5%
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
C347
1U_0402_6.3V4Z
8
7
6
5
C353
0.1U_0402_25V6
RP2
1
2
3
4
A22
+3.3V_VTR_ADC
+5V_RUN
2
10K_0402_5%
D
VBAT
B60
2
0_0402_5%
1
R330
DOCK_PWR_SW#
<40,9>
2
1
1
2
1
1
@ R354
POWER_SW#_MB
U38
B64
+3.3V_ALW_U38
1
R339
2
2
R345
2
1
PCIE_WAKE#
10K_0402_5%
BC_DAT_ECE5048
100K_0402_5%
PBAT_SMBDAT
2.2K_0402_5%
PBAT_SMBCLK
2.2K_0402_5%
1
2
2
2
1
C352
1U_0402_6.3V4Z
2
1
R343
C346
0.1U_0402_25V6
1
R340
1
+3.3V_VTR
0_0402_5%
10K_0402_5%
C343
1U_0402_6.3V6K
2
2
@ C342
1
2
1U_0402_6.3V6K
C344
1U_0402_6.3V6K
C345
0.1U_0402_25V6
1
@ R336
+3.3V_ALW
D
1
R329
POWER_SW_IN#
+3.3V_ALW_U38
1U_0402_6.3V6K
2
+RTC_CELL_VBAT
0_0402_5%
2
2
@ C340
1
2
R328
100K_0402_5%
1
@ R332
+RTC_CELL
R327
100K_0402_5%
1
+RTC_CELL
+RTC_CELL
2
5
5075 Setting for Thermal Design
ESR <2ohms
JFAN1
1
1
1
3
1
1
3
3
1
2
1
2
B
Q14
MMBT3904WT1G_SC70-3~D
REM_DIODE4_N
1
VSET_5075
2
1
2
1
E
2
1
3
2
2
1
3
1
2
2
FWP#
1
1
2
1
2
2
2
2
2
6
8
7
6
5
4
1
2
1
1
1
2
1
2
1
1
1
1
2
2
2
2
2
1
2
3
4
1
1
1
2
2
1
SYSTEM_ID
C
C371
0.1U_0402_25V6
REM_DIODE2_N
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke.
C
H_THERMTRIP#
R394
1.58K_0402_1%
BOARD_ID
2
2
2.2K_0402_5% B
Q12
MMST3904-7-F_SOT323-3
<12>
C367
0.1U_0402_25V6
+3.3V_ALW
@C373
100P_0402_50V8J
HB_A531015-SCHR21
1
R403
1
THSEL_STRAP
R383
2
1K_0402_5%
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
A
Rest=1.58K , Tp=96 degree
@ R399
10K_0402_5%
A00
BOARD_ID rise time is measured from 5%~68%.
<7>
THERMATRIP2#
+1.05V_RUN
C
2
B
E Q13
MMBT3904WT1G_SC70-3~D
R402
8.2K_0402_5%
@ C372
100P_0402_50V8J
***
***
***
***
2
B
Q11
MMBT3904WT1G_SC70-3~D
REM_DIODE1_N
REM_DIODE4_P
X00
X01
X02
E
E
R393
10K_0402_5%
*
CLK_PCI_LPDEBUG
4700p
4700p
4700p
4700p
4700p
4700p
4700p
4700p
C
REM_DIODE2_P
+3.3V_ALW
C369
4700P_0402_25V7K
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
240K
130K
62K
33K
8.2K
4.3K
2K
1K
+3.3V_ALW
REV
reserve for DC fan
DP2/DN2 for SODIMM on Q13, place Q13 close
to SODIMM and C372 close to Q13
R386
1K_0402_5%
<31,36>
C368
C368
4700P_0402_25V7K
1
2
3
4
5
6
7
8
9
10
5
@ C370
100P_0402_50V8J
Q5A
DMN66D0LDW-7_SOT363-6
RUN_ON
2
R392
1K_0402_5%
11
12
EC5048_TX
+3.3V_RUN
CONN@
JLPDE1
1
2
3
4
5
G1 6
G2 7
8
9
10
R392
HOST_DEBUG_TX
Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug
HB_A531015-SCHR21
A
R397
10K_0402_5%
2
0_0402_5%
V.R
B
REM_DIODE1_P
@ R398
100K_0402_5%
1
@ R400
R396
10K_0402_5%
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEB_TX
R395
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
DP4/DN4
+5V_RUN
ACES_50271-0040N-001
CONN@
+3.3V_ALW
Q5B
DMN66D0LDW-7_SOT363-6
RUN_ON#
+3.3V_ALW
RP1
10K_8P4R_5%
1
2
3
4
5
G1 6
G2 7
8
9
10
DIMM
FAN1_PWM
FAN1_TACH
5
6
Place under CPU
Place C266 close to the Q11 as possible
RUNPWROK
Place close pin A21
<26,36,39>
R388
49.9_0402_1%
11
12
DP2/DN2
GND1
GND2
@ D1
RB751V40_SC76-2
R36
100K_0402_5%
EMI depop location
R35
10K_0402_5%
C357
0.1U_0402_25V6
@ C363
4.7P_0402_50V8C
@ R382
10_0402_1%
+3.3V_ALW
+3.3V_ALW
CONN@
JDEG1
CPU
+3.3V_RUN
DOCK_POR_RST#
Place close pin A29
DP1/DN1
C7
22U_0805_6.3V6M
CLK_PCI_MEC
1
2
3
4
2
1
2
3
4
5075 Channel Location
1
Thermal diode mapping
B
CHIPSET_ID for BID function
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
MEC5075
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
1
Sheet
37
of
58
5
4
3
2
1
D
D
Touch Pad
Keyboard
JKBTP1
1
2
1
2
<37>
BC_CLK_ECE1117
+3.3V_TP
TP_DATA
TP_CLK
+3.3V_TP +3.3V_ALW +5V_RUN
CONN@
ACES_50506-01641-P01
1
2
1
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117
BC_DAT_ECE1117
2
1
1
2
C
@ C377
10P_0402_50V8J
1
2
TP_CLK
2 0_0402_5%
<37>
<37>
@ C380
10P_0402_50V8J
2 0_0402_5%
@ R449 1
@ C379
10P_0402_50V8J
@ R441 1
@ C378
10P_0402_50V8J
TP_DATA
2
CLK_TP_SIO
I2C1_SCL_TCH_PAD
2 0_0402_5%
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
@ C376
0.1U_0402_25V6
<37>
<12>
2 0_0402_5%
@ R450 1
GND2
GND1
@ C375
0.1U_0402_25V6
I2C1_SDA_TCH_PAD
@ R444 1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KB_DET#
@ C374
0.1U_0402_25V6
<12>
DAT_TP_SIO
R405
4.7K_0402_5%
<37>
R404
4.7K_0402_5%
PAD-OPEN1x1m
<12>
1
18
17
2
2
+3.3V_TP
1
1
+3.3V_TP
PJP8
2
+3.3V_RUN
Place close to JKBTP1
C
EMI depop location
RSMRST circuit
@IO FFC
@ R414 1
+5V_ALW_U41
<37>
VCC
RESET#
3
DA30000GZ00
@eDP TS Cable
0.1U_0402_25V6
Part Number
DC02C004S00
5
PCH_RSMRST#
1
2
RSMRST#
B
O
A
GND
3
1
2
C387
0.01U_0402_16V7K
2
Part Number
@ C386
1
2
P
1
B
2 0_0402_5%
+3.3V_ALW
G
1
2
U41
R440
10K_0402_5%
2
+3.3V_ALW
R411
33_0402_5%
1
+5V_ALW
4
1
@ R413
2
0_0402_5%
PCH_RSMRST#_Q
<9>
FPC 0VN LF-9591P REV0 M/B-IO/B
Part Number
NBX0001CW00
Description
FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@KBTP FFC
Description
H-CONN SET 0VN MB-LCD-LED-CAM-TS
@eDP Cable
Part Number
NBX0001CZ00
Description
FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@NFC Board FFC
B
Part Number
U42
TC7SH08FU_SSOP5~D
@MEDIA Board FFC
Description
DC02C004T00
Description
H-CONN SET 0VN MB-LCD-LED-CAM
Part Number
NBX0001CZ00
Description
FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
RT9818A-44GU3_SC70-3
@SATA Cable
Part Number
DC02C004K00
@USH Board FFC
Description
H-CONN SET 0VN MB-HDD
@DC-IN Cable
Part Number
DC30100MF00
DC30100MF00
NBX0001CY00
Description
FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@FP FFC
Description
CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
Part Number
Part Number
Part Number
NBX0001D100
Description
FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@ Speak
Description
CONN SET 0VN DCJACK-MB 2DW1003-038110F
Part Number
Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@FAN
Part Number
Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Keyboard
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
38
of
58
4
PCH_ALW_ON
2
3
0_0402_5%
4
+5V_ALW
<26,36,37>
<36,43,9>
RUN_ON
SIO_SLP_S3#
1
@ R418
1
@ R417
2
5
0_0402_5%
2
0_0402_5%
6
7
+1.05V_M
VOUT1
VOUT1
ON1
CT1
VBIAS
CT2
VIN2
VIN2
VOUT2
VOUT2
1
1
C389
2
0.1U_0402_10V7K
12
1
C390
2
470P_0402_50V7K
1
C391
2
470P_0402_50V7K
D
11
GND
ON2
14
13
10
9
8
+1.05V_RUN
15
GPAD
TPS22966DPUR_SON14_2X3
2
2
1
2
<37>
1
@ R416
VIN1
VIN1
1
1
G
3
1
2
3
4
1
2
6
1
1
2
+3.3V_ALW
C393
0.1U_0402_10V7K
2
2
0_0402_5%
5
U43
@ R447
20K_0402_5%
1
@ R420
+3.3V_ALW_PCH
C412
2200P_0402_50V7K
MPHYP_PWR_EN
Q124A
DMN66D0LDW-7_SOT363-6
<12>
4
1.05V_MODPHY_EN
Q124B
DMN66D0LDW-7_SOT363-6
MPHYP_PWR_EN#
1
+3.3V_ALW_PCH/+1.05V_RUN source
+1.05V_MODPHY
C413
10U_0603_6.3V6M
R442
100K_0402_5%
D
6
5
2
1
R445
10K_0402_5%
+3.3V_ALW2
Q125
SI3456DDV-T1-GE3_TSOP6
2
+1.05V_M
+5V_ALW
2
D
+1.05V_MODPHY
3
S
5
+3.3V_SUS/+3.3V_M source
C
C
+3.3V_ALW
USH_PWR_ON
SIO_SLP_S4#
<36,43>
SUS_ON
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
1
@ R423
1
@ R424
2
0_0402_5%
2
0_0402_5%
+3.3V_SUS
U45
1
2
3
4
+5V_ALW
<36,44,9>
SIO_SLP_A#
<37,44>
A_ON
5
6
7
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
C396
2
12
1
C397
2
470P_0402_50V7K
1
C398
2
470P_0402_50V7K
0.1U_0402_10V7K
11
10
9
8
+3.3V_M
15
2
TPS22966DPUR_SON14_2X3
C399
0.1U_0402_10V7K
GPAD
14
13
1
<36>
<36,43,9>
1
@ R439
1
@ R421
1
@ R422
+3.3V_RUN/+5V_RUN source
B
B
+5V_ALW
+5V_RUN
U46
3
SIO_SLP_S3#
RUN_ON
1
@ R425
1
@ R426
2
4
0_0402_5%
2
5
0_0402_5%
+3.3V_ALW
6
7
VIN1
VIN1
ON1
VBIAS
VOUT1
VOUT1
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
C400
2
12
1
C401
2
470P_0402_50V7K
1
C402
2
1000P_0402_50V7K
0.1U_0402_10V7K
11
10
9
8
+3.3V_RUN
15
2
TPS22966DPUR_SON14_2X3
C403
0.1U_0402_10V7K
GPAD
14
13
1
1
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power control
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
39
of
58
5
4
3
2
HDD LED solution for White LED
1
Battery LED
SATA_ACT#
2
3
Q24A
DMN66D0LDW-7_SOT363-6
1
6
D23
1
2
<36>
2
RB751S40T1G_SOD523-2
D24
<36>
BAT2_LED#_Q
1
R427
2
390_0402_5%
BATT_WHITE#
1
2
W
3
BATT_YELLOW#
4
D
Y
MASK_BASE_LEDS#
MASK_SATA_LED#
1
<36>
LED7
LTW-295DSKS-5A_YEL-WHITE
Q23B
DMN66D0LDW-7_SOT363-6
4
3
Q15
PDTA114EU_SC70-3
2
5
D
BAT2_LED#
5
<6>
Q24B
DMN66D0LDW-7_SOT363-6
4
3
+5V_ALW
+5V_ALW
R428
10K_0402_5%
1
+3.3V_ALW
1
LED_SATA_DIAG_OUT#
LED6
LTW-193ZDS5_WHITE
2 SATA_LED
2
1
330_0402_5%
2
1
R430
MASK_BASE_LEDS#
RB751S40T1G_SOD523-2
PANEL_HDD_LED#
<22>
BAT1_LED#
3
<36>
Q23A
DMN66D0LDW-7_SOT363-6
1
6
2
220_0402_5%
1
BAT1_LED#_Q
R431
2
330_0402_5%
1
R433
2
330_0402_5%
BATT_WHITE_LED#
<22>
BATT_YELLOW_LED#
<22>
2
Q25B
DMN66D0LDW-7_SOT363-6
4
3
1
R429
2
MASK_BASE_LEDS#
1
5
Q26
PDTA114EU_SC70-3
1
R438
SYS_LED_MASK#
2
150_0402_5%
WLAN LED solution for White LED
Breath LED
2
3
5
C
Q25A
DMN66D0LDW-7_SOT363-6
1
6
2
WIRELESS_LED#
+5V_ALW
Q16
PDTA114EU_SC70-3
<34,36>
BREATH_LED#
Q28A
LED1
DMN66D0LDW-7_SOT363-6
LTW-193ZDS5_WHITE
1
6 BREATH_LED#_Q 1
2
BREATH_WHITE_LED_SNIFF
2
<31,36>
Q28B
DMN66D0LDW-7_SOT363-6
4
3
+5V_ALW
R432
100K_0402_5%
1
+3.3V_ALW
C
1
R434
2
330_0402_5%
2
1
Place LED1 close to SW5
MASK_BASE_LEDS#
1
R435
2 WLAN_LED
390_0402_5%
2
1
MASK_BASE_LEDS#
LED5
LTW-193ZDS5_WHITE
1
R436
2
220_0402_5%
BREATH_WHITE_LED#
<22>
+3.3V_ALW
@ C404
1
2
1
SYS_LED_MASK#
2
LID_CL#
B
A
O
4
MASK_BASE_LEDS#
<28>
U47
TC7SH08FU_SSOP5~D
3
<35,36>
P
<36>
G
5
0.1U_0402_25V6
B
B
POWER & INSTANT ON SWITCH
<37,9>
2 SW1
POWER_SW#_MB
Media board CONN
EMI CLIP
1
JMEDIA
CLIP1
EMI_CLIP
4
3
GND
<37>
<37>
<37>
1
VOL_MUTE
VOL_DOWN
VOL_UP
1
2
3
4
5
6
1
2
3
4
5 GND
6 GND
7
8
SKRBAAE010_4P
CONN@
ACES_50506-00641-P01
LED Circuit Control Table
Fiducial Mark
@ FD1
1
SYS_LED_MASK#
LID_CL#
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
@ FD2
1
A
FIDUCIAL MARK~D
0
1
1
X
0
1
A
1
@ ST2
CLIP_C5P5
DELL CONFIDENTIAL/PROPRIETARY
1
@ ST1
@ H24
CLIP_C5P5
H_2P1X2P6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FIDUCIAL MARK~D
@ H21
@ H22
@ H23
H_1P0N H_1P0N H_2P1
1
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19
H_2P8 H_2P8 H_3P1 H_2P8 H_2P8 H_3P1 H_3P8 H_3P8 H_3P8 H_3P8 H_5P0 H_2P8 H_2P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
1
FIDUCIAL MARK~D
@ FD4
1
1
@ FD3
1
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PAD, LED
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
40
of
58
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR1
1K_0402_5%~D
Z4012
2
+3.3V_RTC_LDO
@ JRTC1
1
3
2 1 G 4
2 G
+COINCELL
Primary Battery Connector
8
7
6
5
2
1
1
PC1
1U_0603_10V4Z~D
2
+PBATT
PR2
2
PRP2
1
@ PC2
0.1U_0603_25V7K~D
BAS40CW SOT-323
100K_0402_5%~D
2
1
2
3
4
PBAT_SMBCLK
PBAT_SMBDAT
<37>
<37>
PBAT_PRES#
<36,48>
PQ1
ME2301D-G 1P SOT-23-3
100_0804_8P4R_5%
PD4
2
1
3
3
1
1
PC3
2200P_0402_50V7K~D
2
1
+3.3V_ALW
PL2
FBMJ4516HS720NT_2P~D
1
2
PBATT+_C
P2
Z4304
Z4305
Z4306
PD3
PL1
FBMJ4516HS720NT_2P~D
1
2
1
PD2
TVNST52302AB0_SOT523-3
3
2
3
2
PD1
TVNST52302AB0_SOT523-3
LLTOP_ALLTOP C144LS-109A9-L 9P BATT
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
GND 11
GND
D
TYCO_2-1775293-2~D
+RTC_CELL
1
1
3
D
DOCK_SMB_ALERT#
<34,36,48>
SDMK0340L-7-F_SOD323-2~D
2
2
@ PBATT1
GND
<34,36,48>
@ PR6
1
SLICE_BAT_PRES#
2
1
0_0402_5%
PC4
2
C
C
1500P_0402_7K~D
+5V_ALW
PR7
1
2
0_0402_5%~D
S
2
G
2
PR10
PQ2
FDV301N_G_NL_SOT23-3~D
2
2
2.2K_0402_5%~D
PR9
33_0402_5%~D
1
2
3
D
1
1
DOCK_PSID
NO
IN
6
GPIO_PSID_SELECT
GND
V+
5
<36>
+5V_ALW
1
PL3
BLM15AG102SN1D_2P
2
1
NB_PSID
PU111
<34>
PR8
1
PN: SM010028600
GND
2
@
change from 0603 to 0402 size
3
+3.3V_ALW
@ PD5
DA204U_SOT323~D
3
NB_PSID_TS5A63157
NC
COM
4
PS_ID
<37>
TS5A63157DCKR_SC70-6~D
+5V_ALW
1
1
1
100K_0402_1%~D
B
C
2
B
PQ3
MMST3904-7-F_SOT323~D
B
PR11
10K_0402_1%~D
2
2
3
E
PR12
15K_0402_1%~D
1
1
@ PR13
2
PSID_DISABLE#
<36>
10K_0402_5%~D
DC_IN+ Source
+DC_IN_SS
1
AC_DIS
PC10
2
1
10U_0805_25V6K
1
2
1
100K_0402_5%~D
PR15
PC8
2
@
0.1U_0603_25V7K~D
1
2
PC7
2
<48> @
0.1U_0603_25V7K~D
SOFT_START_GC @
A
PR18
2
DCX124EK-7-F PNP/NPN_SC74-6~D
PC6
1
<36,48>
2
10K_0402_5%~D
0.1U_0603_25V7K~D
4
1
PR14
2
1M_0402_5%~D
PR17
1
4
1
1
PR16
2
5
5
1
PQ6A
6
PJP1
@ PJPDC1
@
@
4.7K_0805_5%~D
1
PC11
2
2
+DCIN_JACK
@
0.1U_0603_25V7K~D
-DCIN_JACK
PD6
PC9
1000P_0603_50V7K~D
2
1
5
4
3
2
1
2
1
2
3
1M_0402_5%~D
2
DELL CONFIDENTIAL/PROPRIETARY
1
PAD-OPEN 1x3m
Compal Electronics, Inc.
PC12 @
2
A
5
4
3
2
1
1
VZ0603M260APT_0603
PQ6B
ACES_50299-00501-003
7
GND 6
GND
PQ4
FDMC6679AZ_MLP8-5
+DC_IN
PC5
0.022U_0805_50V7K~D
1
2
3
PL4
FBMJ4516HS720NT_2P~D
1
2
DCX124EK-7-F PNP/NPN_SC74-6~D
+DC_IN
Title
0.1U_0603_25V7K~D
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
+DCIN
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
41
of
57
A
B
C
D
E
+3.3V_RTC_LDO
1
1
+3.3V_ALW2
PR100
6.49K_0402_1%~D
1
2
PR101
15K_0402_1%
2
1
ALW_PWRGD_3V_5V
PR105
PAD-OPEN 1x3m
1
VCLK
10
TPS51285BRUKR QFN 20P
DRVH2
DRVH1
9
VBST2
1
2
3
BST_3V
BST_5V
18
SW1
PC110
0.1U_0603_25V7K
1
2
DRVL1
EN1
2
@
1
2
4
2
+DC1_PWR_SRC
+5V_ALWP
@
1
+
2
@
PR112 @
2
FDMC7692S_POWER33-8-5
PC114 @
680P_0603_50V7K
1
PQ103
3
2
1
1
2
3
1
FDMC7692S_POWER33-8-5
PC118
4.7U_0603_10V6K
2
1
PQ102
3VALWP
TDC 6.7 A
Peak Current 8.1 A
OCP Current 9.72 A
Rds(on): 13.6m ohm (max)
PC115
220U_6.3V_R18M
5
LG_5V
4
20130510:
PC113_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
PC103
10U_0805_25V6K
2
1
PQ101
PL102
3.3UH_ETQP3W3R3WFN_7A_20%
1
2
EN
LG_3V
2
FDMC8884_POWER33-8-5
1
@ PC111
680P_0603_50V7K
PC117
0.1U_0603_25V7K
2
1
+
@
15
20
VREG5
13
VIN
12
SW1
@
4
PR109
2.2_0603_5%
1
2
5
1
@ PR111
4.7_1206_5%
3
UG_5V
17
2
1
PC113
220U_6.3V_R18M
2
PC112
@
0.1U_0603_25V7K
11
SW2
DRVL2
PL101
2.2UH_ETQP3W2R2WFN_8.5A_20%
2
1
+3.3V_ALWP
8
16
@
3
2
1
VBST1
SW2
PR114
200_0402_1%
1
1
PR110
2.2_0603_5%
1
2
2
PC116
0.1U_0603_25V7K
UG_3V
PC109
0.1U_0603_25V7K
1
2
19
2
4
14
PC102
10U_0805_25V6K
2
1
PGOOD
PC106
2200P_0402_50V7K
2
1
7
PGOOD_3V_5V
21
5
VO1
0_0402_5%
PQ100
FDMC8884_POWER33-8-5
PAD
PC101
0.1U_0402_25V6
2
1
1
CS1
2
VREG3
VFB1
3
4
EN2
1
@ PR108
1
2
@
CS2
6
EN
VFB2
5
1
2
PU100
PR107
100K_0402_1%~D
5
PC104
10U_0805_25V6K
2
1
@
PC107
10U_0805_25V6K
2
1
PC105
2200P_0402_50V7K
2
1
PC108
0.1U_0402_25V6
2
1
+PWR_SRC
16.9K_0402_1%
+3.3V_ALW
PL100
1UH_PCMB053T-1R0MS_7A_20%
2
1
@
+DC1_PWR_SRC
PR106
20K_0402_1%~D
+DC1_PWR_SRC
2
2
<37>
2
1
PJP100
1
PR104
10K_0402_5%~D
2
1
PC100
4.7U_0603_10V6K
2
1
@ PR103
0_0402_5%
2
@
2
PR102
10K_0402_5%~D
1
2
4.7_1206_5%
20130510:
PC115_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
+5V_ALW2
3
EN
@ PR113
<37>
ALWON
2
PJP101
1
+5V_ALWP
0_0402_5%
1
2
+5V_ALW
5VALWP
TDC 4.88 A
Peak Current 6.89 A
OCP Current 8.268 A
Rds(on):13.6m ohm (max)
PAD-OPEN 1x3m
PJP102
+3.3V_ALWP
1
2
+3.3V_ALW
PC119
1U_0603_10V6K
2
1
PAD-OPEN 1x3m
@
4
4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
+5V_ALW/3.3V_ALW
Document Number
Rev
0.4
LA-9591P
Friday, May 17, 2013
Sheet
E
42
of
57
5
4
3
2
1
1.35Volt +/- 5%
TDC: 7.2 A
Peak Current: 10 A
OCP current: 12 A
Rds(on): 13.6m ohm(max)
+PWR_SRC
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
PJP200
2
D
1
1.35V_B+
D
PJP201
PR200
1
2
2.2_0603_5%~D
PAD-OPEN 1x2m~D
BOOT_1.35V
+VLDOIN_1.35V
2
+1.35V_MEN_P
1
PQ200
15
1
2
3
PR201
23.7K_0402_1%
1
2
13
1
2
VTT
VTTSNS
21
12
1
2
CS
GND
+V_DDR_REF
RT8207MZQW_WQFN20_3X3
VDDP
VTTREF
3
4
+V_DDR_REF
PR202
+5V_ALW
+3.3V_ALW
+1.35V_MEN_P
5
FB
1
1.35V_FB
2
PR204
100K_0402_1%~D
PC213
100P_0402_50V8J~D
2
1
2
<37>
1.35V_SUS_PWRGD
PC212
0.033U_0402_16V7~D
PR205
8.06K_0402_1%~D
2
1
1
@ PR203
4.7_1206_5%
C
FB sense trace
when FB pull down to GND
6
1
2
3
1U_0603_10V6K~D
S3
PC211
FDMC7692S_POWER33-8-5
VDDQ
S5
VDD
7
11
8
VDD_1.35V
TON
2
5.1_0603_5%~D
9
+5V_ALW
PGOOD
1
4
PQ201
PC205
22U_0805_6.3V6M
20
19
18
BOOT
PAD
VTTGND
PGND
10
1
5
PC209
1U_0603_10V6K~D
680P_0603_50V7K
20130510:
PC207_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
PU11
CS_1.35V
@ PC208
SNUB_1.35V 2
2
PC207
330U_2.5V_ESR16M
+
C
@
14
LGATE
VLDOIN
4
FDMC8884_POWER33-8-5
PL200
1UH_PCMB063T-1R0MS_12A_20%
1
2
16
DL_1.35V
17
SW _1.35V
UGATE
+1.35V_MEN_P
1
+0.675V_P
PHASE
2
1
PC204
1
2
5
@
0.22U_0603_16V7K~D
@
PC203
2200P_0402_50V7K~D
1
2
PC202
0.1U_0402_25V6
1
2
PC201
4.7U_0805_25V6K~D
2
1
PC200
4.7U_0805_25V6K~D
PAD-OPEN1x1m
DH_1.35V
1.35V_SUS_PWRGD
PR206
SIO_SLP_S4#
1
1.35V_B+
2
1M_0402_1%~D
S5_1.35V
@ PR208
1
2
1
<18>
1
0.675V_DDR_VTT_ON
@ PC215
2
B
0.1U_0402_16V7K~D
<36,39,9>
Mode
S5
S3
S0
S3
L
L
H
S5
L
H
H
+1.5V_MEN
off
on
on
+V_DDR_REF
off
on
on
PR209
10K_0402_1%
@ PR210
0_0402_5%
@ PC214
0.1U_0402_16V7K~D
2
SUS_ON
2
0_0402_5%
1
<36,39>
1
2
<36,39,9>
@ PR207
0_0402_5%~D
1
2
B
@ PR211
1
2
0_0402_5%~D
SIO_SLP_S3#
+0.75V_P
off
off(Hi-Z)
on
+1.35V_MEN_P
FB sense trace
PJP203
2
2
1
1
JUMP_1x3m
+1.35V_MEN_P
PJP204
2
2
1
1
PJP202
+1.35V_MEM
+0.675V_P
JUMP_1x3m
2
+0.675V_DDR_VTT
1
PAD-OPEN1x1m
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.35V_MEN/+0.675V_DDR_VTT
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
43
of
57
5
4
3
2
1
PJP300
2
+V1.05SP_B+
1
+PWR_SRC
PR301
2.2_0603_5%
1
2
PU300
0_0402_5%~D
3
FB_+V1.05SP
4
RF_+V1.05SP
5
VBST
TRIP
DRVH
EN
SW
VFB
V5IN
RF
DRVL
TP
C
@ PR304
<37,39>
1
A_ON
10
UG_+V1.05SP
8
SW_+V1.05SP
6
11
4
PQ301
FDMC7692S_POWER33-8-5
1
10U_0805_25V
PC307
C
220U_B2_2.5VM_R15M
@ PR306
3
2
1
1
+
680P_0603_50V7K
2
4.7_1206_5%
2
2
2
470K_0402_1%
@ PC308
1
@ PC306
PC305
1U_0402_6.3V6K~D
PR305
0.1U_0402_16V7K
+1.05V_MP
+5V_ALW
LG_+V1.05SP
1
0_0402_5%
PL300
2.2UH_ETQP3W2R2WFN_8.5A_20%
1
2
7
TPS51212DSCR_SON10_3X3
2
4.7U_0805_25V6K~D
PC303
2
1
BST_+V1.05SP
9
1
SIO_SLP_A#
S0 mode be high level
EN_+V1.05SP
PGOOD
2
<36,39,9>
@ PR303
1
2
2
5
95.3K_0402_1%
TRIP_+V1.05SP
PQ300
FDMC8884_POWER33-8-5
1
PR302 2
2
1
1
@
D
1
1.05V_A_PWRGD
PC304
0.1U_0603_25V7K
1
2
3
2
1
2
100K_0402_1%~D
<37>
@
@
4
PR300
PC302
2
1
PC300
2
5
+3.3V_ALW
2200P_0402_50V7K
1
D
0.1U_0402_25V6
PC301
2
1
PAD-OPEN 1x2m~D
PR307
2
1
4.99K_0402_1%
2
+1.05Volt +/- 5%
TDC 3.67 A
Peak Current 5.25 A
OCP current 6.3 A
Rds(on): 13.6m ohm (max)
B
PR308
10K_0402_1%
1
PJP301
+1.05V_MP
2
+1.05V_M
1
B
PAD-OPEN 1x2m~D
DELL CONFIDENTIAL/PROPRIETARY
A
A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05V_M
Size
4
3
2
Rev
0.4
LA-9591P
Date:
5
Document Number
Friday, May 17, 2013
Sheet
1
44
of
57
5
4
3
2
1
+3.3V_RUN +3.3V_ALW
D
1
+5V_ALW
1
D
PJP400
@ PJP402
2
2
PC400
1U_0402_6.3V6K
PAD-OPEN1x1m
PU400
1
1
1
PR402
1.54K_0402_1%
APL5930KAI-TRG_SO8
+1.5V_THERMAL
PC403
0.01U_0402_25V7K
1
VIN
9
1
PAD-OPEN1x1m
PC404
22U_0805_6.3V6M
2
47K_0402_5%
0.1U_0402_16V7K
2
PJP401
2
1.5VSP
2
@ PC402
2
@ PR401
FB
PC401
4.7U_0805_6.3V6K
3
2
1
1
100K_0402_5%~D
EN
4
2
8
GND
2
5
1
VIN
VOUT
VOUT
1
1
PR400
POK
2
7
+3.3V_RUN
VCNTL
6
2
1
PAD-OPEN1x1m
PR403
1.74K_0402_1%
C
2
C
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
Title
+1.05VS_VTTP/+1.0VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.4
Chief River VC
Friday, May 17, 2013
Sheet
1
45
of
57
5
4
3
2
1
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately.
So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse.
So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
VREF
1
100K_0402_1%_NCP15WF104F03RC
2
1 PR504
+PWR_SRC
@ PJP500
8
7
6
5
4
3
2
1
@ PR513
1
2
75_0402_1%
2
2
@ PR539
1
0_0402_5%
@ PR540
1
0_0402_5%
1
@ PR516
2
1.91K_0402_1%~D
H_VR_READY
<15>
IMVP_PWRGD
<36>
1
PR512
2.1K_0402_1%~D
2
1
1
PC511
0.1U_0402_25V6
VIDSCLK
<15>
VIDALERT_N
<15>
VIDSOUT
CSP1
PR514
43.2K_0402_1%
2
1
1
2
PR529
110_0402_1%
1
2
PR528
75_0402_1%
1
2
1
2
<15>
PR527
54.9_0402_1%
B
@
2
<15>
VCCSENSE
2
@ PR531
1
VFB
2
@
+5V_RUN
3
1
@
VIDALERT_N
VIDSCLK
CSD97374CQ4M_SON8_3P5X4P5
1
2
PC502
0.068U_0402_16V7K
+1.05V_VCCST
2
SKIP#
PH501
10K_0402_1%_TSM0A103F34D1RZ
H_PROCHOT#
PR520
@ 0_0402_5%
PC509
1U_0603_10V7K~D
C
PL500
0.22UH_FDUE0640J-H-R22M=P3_25A_20%
4
1
PR515
3.01K_0402_1%
2
1
2
PC514
<37,47,48,9>
@
2
PC510
1U_0603_10V7K~D
1
PR526
10_0603_1%
2
+5V_ALW
2
1
2
1
PC507
1
2
0.33U_0603_10V7K~D
PC512
1500P_0402_50V7K
2
1
1
PR535
4.87K_0402_1%
TI recommend 1nF
+VCC_CORE
4
3
2
1SKIP#1 1
47P_0402_50V8J~D
2
VREF
PR534
0_0402_5%
1VR_HOT#
1 PR523 2
10K_0402_5%~D
6
5
PGND2
PWM
BOOT VSW
PGND1
BOOT_R VDD
VIN
SKIP#
PC508
2
2
9
8
7
PC513
0.068U_0402_16V7K
2
PC503
1000P_0402_50V7K~D
1
2
1
2
0.1U_0402_25V6
2
1
PR517
0_0603_5%~D
1
PC504
PWM1
+3.3V_RUN
4.7_1206_5%~D
1
1 2 PR522
PR519
1_0603_5%
TPS51622RSM
2.32K_0402_1%
100P_0402_50V8~D
PC739
PU501
2
1
1
PR521
PC738
+3.3V_RUN
PC505
1U_0603_10V6K
@ PC506
1
2
+
2
680P_0603_50V7K~D
25
26
27
28
29
30
31
32
33
<36>
@
PWM1
VR_ON
SKIP#
PWM1
PWM2
N/C
PGOOD
VDD
VDIO
C
<15>
IMVP_VR_ON
2
1
SKIP#
DROP
COMP
VREF
V5A
GND
VR_HOT#
VCLK
ALERT#
GND
VFB
CSP1
CSN1
CSN2
CSP2
PU3
N/C
GFB
VFB
2
+
2
17
18
19
20
21
22
23
24
H_VR_EN
VIDSOUT
+3.3V_RUN
+3.3V_RUN
VBAT
SLEWA
THERM
IMON
OCP-I
B-RAMP
F-IMAX
O-USR
CSN1
1
@
1
330U_2.5V_ESR17M
16
15
14
13
12
11
10
9
PU500
@PR536
@
PR536
0_0402_5%
2
1
@ PR537 0_0402_5%
+
100U_D3L_20VM_R55M
2
CSP1
PC735
10K_0402_5%~D
GFB
1
2
FBMA-L11-453215-121LMA90T
2
1
33U_D_25VM_R60M
PR511
PL501
PC734
10U_0805_25V6K
2
1
1
+VCC_PWR_SRC
PC732
10U_0805_25V6K
2
1
+VCC_PWR_SRC
2
PAD-OPEN 4x4m
PC731
10U_0805_25V6K
2
1
1
PC736
10U_0805_25V6K
2
1
2
PR509
1
PR508
1
D
150K_0402_1%
2
O-USR
150K_0402_1%
2
PR507
1
150K_0402_1%
8.87K_0402_1%
PR503
1
2
1M_0402_1%
2
PR502
1
75_0402_1%
2
PR501
1
365K_0402_1%
PC500
1
2
2
F-IMAX
1
PR510
39K_0402_5%~D
B-RAMP
1 PR506
2
SLEWA
@
OCP-I
75K_0402_1%
D
PC501
0.1U_0402_16V7K~D
2
1
PR505
10K_0402_5%~D
1
2
1
2
@ PR500
75_0402_1%
4700P_0603_50V7K
2
PH500
IMON
B
CSN1
0_0402_5%
from processor
<17>
VSSSENSE
2
@ PR532
1
GFB
0_0402_5%
CPU
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DCR: 0.82m +-5% ohm
PH500 B value: 4250k 1%
PH501 B value: 3435k 1%
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+VCC_CORE
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
46
of
57
1
2
G
PQ701
NTR4502PT1G_SOT23-3~D
1
PR707
100K_0402_1%~D
2
1
2
DK_CSS_GC
19
SCL
GND
15
CHG_LGATE
14
10K_0402_1%~D
@
4
3
2
1
PQ706
10K_0402_1%~D
@
2
@ PR751
1
GNDA_CHG
2
1
BQ24715_REGN
ACAV_IN
PQ712B
4
Adapter Protection Circuit for Turbo Mode
<37,47,48>
DMN66D0LDW-7 2N SOT363-6
PR739
10K_0402_1%~D
2
1
PU2B
@ PR741
1
4
LM393DR_SO8~D
1
7
G
O
-
ACAV_IN_NB
2
<37,48>
0_0402_5%
A
2
+
PR744
5
6
PC730
100P_0402_50V8J~D
2
1
3
TC7SH08FU_SSOP5~D
PR743
42.2K_0402_1%~D
2
1
<36>
3
PROCHOT_GATE
PR742
22.6K_0402_1%~D
2
1
2
A
5
P
8
+5V_ALW
10K_0402_1%~D
PR738
48.7K_0402_1%
2
1
PR740
100K_0402_5%~D
PC729
100P_0402_50V8J~D
2
1
P
1
B
O
G
1
PC728
0.1U_0402_25V4Z~D
1
1
3
PU3
4
A
PR737
232K_0402_1%~D
2
1
2
PR736
1M_0402_1%~D
1
2
2
1
+DC_IN
+3.3V_ALW
+3.3V_ALW
5
220P_0402_50V8J
5
4
2
@ PC740
2
DYN_TUR_CURRNT_SET#
B
1
LM393DR_SO8~D
1
4
1
6
8
1
2
PC727
220P_0402_50V8J~D
PC726
100P_0402_50V8J~D
2
1
PR735
69.8K_0402_1%
2
1
PR734
210K_0402_1%
1
6 2
<37>
-
<48>
<37,46,48,9>
+3.3V_ALW2
PU2A
O
2
PQ712A
DMN66D0LDW-7 2N SOT363-6
+
P
3
2
@ PR728
0_0402_5%
DMN66D0LDW-7 2N SOT363-6
PQ710B
2
PR732
20K_0402_1%~D
1
2
@
0.1U_0603_25V7K~D
2
H_PROCHOT#
PQ710A
DMN66D0LDW-7 2N SOT363-6
VCP
G
PR730
150K_0402_1%
PC722
1
2
PR727
221K_0402_1%~D
PR729
1.8M_0402_1%
1
2
2
PC724
100P_0402_50V8J~D
2
1
PC725
0.01U_0402_25V7K~D
2
1
Low
PC721
0.1U_0603_25V7K~D
1
2
GNDA_CHG
@
1
65W
@
+5V_ALW
@
@
@ PC720
0.1U_0603_25V7K~D
1
2
BATDRV#
+3.3V_ALW2
@
@
PAD-OPEN1x1m
10K_0402_1%~D
+5V_ALW
High
2
2
B
DYN_TUR_CURRENT_SET#
3
GNDA_CHG
PJP701
0_0402_5%
1
+3.3V_ALW2
SIRA06DP-T1-GE3_POWERPAKSO-8
GNDA_CHG
@ PR750
1
CHARGER_CELL_PIN
PR724
1
GNDA_CHG
PR722
4.02K_0402_1%
1
2
11
BQ24715RGRR_QFN
2
1
PR718
0_0402_5%
/BATDRV
2
CELL
2
SRN
12
4.7_1206_5%~D
IOUT
1
5
10
TP
@ PR726
2
4
13
10U_0805_25V6K
1
2
SRP
+VCHGR
PR716
0.01_1206_1%~D
PC716
2
1
ACOK
21
2
PC719
100P_0402_50V8J~D
1
PR746
121K_0402_1%~D
2
1
V_SYS
<48>
45W
+PWR_SRC
PL701
PC737
10U_0805_25V6K
2
1
5
7
GNDA_CHG
C
PQ704
SIRA14DP-T1GE3_POWERPAK-SO8-5
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
2
1
2
@
PC746
10U_0805_25V6K
2
1
LODRV
@
PC745
10U_0805_25V6K
2
1
SDA
@
PC718
10U_0805_25V6K
2
1
9
CHARGER_SMBCLK
PR711
CSSP_1
PC744
22U_0805_25V6M
2
1
PHASE
4
CHG_UGATE
PC717
10U_0805_25V6K
2
1
ACDET
18
PC743
22U_0805_25V6M
2
1
HIDRV
PC715
0.1U_0603_25V7K~D
2
1
ACDRV
PR715
2.2_0603_5%
1
2
PC742
22U_0805_25V6M
2
1
2
BTST
PC741
22U_0805_25V6M
2
1
17
CMSRC
PC712
22U_0805_25V6M
2
1
1U_0603_10V6K~D
PD702
BAT54HT1G_SOD323-2~D
PC711
22U_0805_25V6M
2
1
BQ24715_REGN
PC710
0.1U_0603_25V7K~D
2
1
16
PR719
0_0402_5%
1
2
8
BQ24715_REGN1
1
<48>
PC707
2200P_0402_50V7K~D
2
1
3
4
1
PR749
59_0402_1%
Discrete current monitor circuit
1
5
2
1
+3.3V_ALW
4
INA199A1DCKR_SC70-6~D
0.1U_0603_25V7K~D
0_0402_5%
<37>
IN+
@ PR709
1
REGN
0.1U_0402_25V6
1
IN-
V+
2
PR705
1
3
PR704
10_0402_5%~D
1
CSSP_1
PC733
@ PR717
ACAV_IN
GND
2
<34>
PC714
1000P_0603_50V7K~D
PR747
100K_0402_1%~D
1
VCC
0_0402_5%
CHARGER_SMBDAT
2
DOCK_DCIN_IS-
3
0_0402_5%
BQ24715_REGN
<37>
+SDC_IN
PC709
1
2
2
20
6
<37>
4
PR748
44.2_0402_1%~D
2
1
5
3
2
1
@ PR725
GNDA_CHG
<37,47,48>
2
1
1
1
6
<34>
PQ703B
SI3993CDV-T1-GE3_TSOP6~D
PC713
0.047U_0603_25V7M
2
1
2
PC708
C
1
PU700
+DCIN
+SDC_IN
Out
GNDA_CHG
GNDA_CHG
ACN
PR713
261K_0402_1%
PR714
49.9K_0402_1%~D
2
PC705
1
2
REF
2
0.1U_0603_25V7K~D
ACP
2
PC706
10U_0805_25V6K
2
1
PC704
0.1U_0603_25V7K~D
1
2
2
PR745
10_1206_5%~D
2
1
+SDC_IN
2
PC703
1U_0603_25V6K
1
2
D
PU703
1
DOCK_DCIN_IS+
D
2
1_0805_1%~D
2
0_0402_5%
G
1
+CHGR_DC_IN
PR703
10K_0402_5%~D
2
1
1
@
CSSN_1
6
S
<48>
@ PR708
5
D
BAT54CW_SOT323~D
S
@ PR710
VCP
G
1
3
+DC_IN_SS
PQ703A
SI3993CDV-T1-GE3_TSOP6~D
S
PQ702
NTR4502PT1G_SOT23-3~D
PD701
2
S
sense adapter
<37>
3
D
2
G
+DOCK_PWR_BAR
@
PR706
100K_0402_1%~D
1
0_0402_5%
D
2
D
2
CSS_GC
PAD-OPEN 4x4m
3
<48>
1
2
CSSN_1
<48>
@ PR702
1
2
1
3
10_0402_5%~D
DC_BLOCK_GC
2
2
0_0402_5%
CHAGER_SRC
PJP700
4
1
@ PR701
1
@
@
1
4
PR700
0.01_1206_1%~D
1
1
+SDC_IN
1
2
3
5
+DC_IN_SS
2
PL700
1UH_PCMB042T-1R0MS_4.5A_20%
2
1
+PWR_SRC_AC
V30415-T1-GE3 1P POWERPAK1212-8
PC700
0.1U_0603_25V7K~D
PQ700
3
PC702
0.1U_0603_25V7K~D
2
1
4
PC701
47P_0402_50V8J~D
2
1
5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
+GPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
47
of
57
PQ802A
DMN66D0LDW-7 2N_SOT363-6~D
O
A
2
+3.3V_ALW
1
+PWR_SRC_AC
6 2
1
2
1
3301_DSCHRG_FET_GC
8
7
6
5
<36,48>
4
B
A
@ PR812
1
DIS_BAT_PROCHOT#
6
4
O
2
PU804
TC7SH08FU_SSOP5~D
2
PQ805A
DMN66D0LDW-7 2N_SOT363-6~D
2
1
6
PQ806A
2
@ PD818
SDMK0340L-7-F_SOD323-2~D
1
2
CHARGER_CELL_PIN
<47>
0_0402_5%
+DOCK_PWR_BAR
5
2
PC811
0.01U_0603_25V7K~D
<36>
1
PR814
330K_0402_5%~D
2
1
1
SLICE_BAT_ON
3
5
PQ810
FDS6679AZ-G_SO8~D
2
PQ812B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
PBAT_PRES#
4
PD808
PDS5100H-13_POWERDI5-3~D
PR821
820_0603_5%~D
1
2
4
STSTART_DCBLOCK_GC
1
2
3
1
2
PBAT_PRES#
DMN66D0LDW-7 2N_SOT363-6~D
5
SLICE_BAT_ON
1
4
0.47U_0805_25V7K~D @ 0_0402_5%
FDS6679AZ-G_SO8~D
+3.3V_ALW
PC805
0.1U_0402_10V7K
1
2
5
2200P_0402_50V7K~D
PC807
PR811
1
2
2
1
<34,36,41,48>
P
SLICE_BAT_PRES#
G
5
2
3
2 DMN66D0LDW-7 2N_SOT363-6~D
PQ807B
3
PR817
330K_0402_5%~D
3
4
1
PQ806B
8
7
6
5
1
1
2
3
D
0.1U_0603_25V7K~D
PC806
1
2
PQ811
+PBATT
PR816
100K_0402_5%~D
PQ805B
DMN66D0LDW-7 2N_SOT363-6~D
5
PR810
100K_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
2
1
2
2
DMN66D0LDW-7 2N_SOT363-6~D
PQ807A
<37,46,47,9>
1
PR807
100K_0402_5%~D
+3.3V_ALW
PC803
1
2
H_PROCHOT#
3
TC7SH08FU_SSOP5~D
PR808
+3.3V_ALW
6
4
3
2
1
B
2
SLICE_BAT_ON
1
4
PR804
100K_0402_5%~D
+3.3V_ALW2
1
<36,41>
1
SLICE_BAT_PRES#
PU801
+3.3V_ALW2
PQ812A
DMN66D0LDW-7 2N_SOT363-6~D
PR801
100K_0402_5%~D
2
1
5
2
+NBDOCK_DC_IN_SS
PR802
100K_0402_5%~D
PC801
0.1U_0402_10V7K
1
2
100K_0402_5%~D
PR815
10K_0402_5%~D
2 2
1
6
BATDRV#
1
PR813
100K_0402_5%~D
1
2
PD811
4
<47>
3
1
SDMK0340L-7-F_SOD323-2~D
PQ800
SI4835DDY-T1-GE3_SO8~D
1
8
2
7
3
6
5
1
PQ809
SI4835DDY-T1-GE3_SO8~D
1
8
2
7
3
6
5
1
+3.3V_ALW
Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.
2
+VCHGR
2
1
D
PD800
PDS5100H-13_POWERDI5-3~D
3
1
2
+PBATT_IN_SS
2
PQ801
NTR4502PT1G 1P SOT23-3
3
+BATT_SUM
3
PD807
SDMK0340L-7-F_SOD323-2~D
P
4
PD806
PDS5100H-13_POWERDI5-3~D
3
1
2
G
5
PQ826
FDMC6679AZ_MLP8-5
+3.3V_ALW2
@ PR820
5
1
D
S
3
TP
ERC3
ERC2
CSS_GC
DK_CSS_GC
P33ALW
0_0402_5%
@
STSTART_DCBLOCK_GC
PQ819B
DMN66D0LDW-7 2N_SOT363-6~D
1
6
PQ818
1
1
2
1
1
1
+3.3V_ALW2
3
PR837
100K_0402_5%~D
3
PC814
0.1U_0402_10V7K
2
1
2
G
3
+3.3V_ALW2
5
1
1
B
A
3
O
1
2
SLICE_BAT_PRES#
DOCK_DET#
<34,36,41,48>
<34,36,48>
PR864
100K_0402_5%~D
PU808
TC7SH08FU_SSOP5~D
2
4
+PBATT
P
2
G
NTR4502PT1G_SOT23-3~D
PQ830
3
2
DOCK_DET#
3
PR866
0_0402_5%
2@
1
EN_DOCK_PWR_BAR
<36>
@ PR869
1
@ PR856
D
2
G
3
@ PR877
1
2
0_0402_5%
PQ831
2
2
@ PQ823
ME2301D-G 1P SOT-23-3
<37,47,48>
ACAV_IN#
2
0_0402_5%~D
2
1
PQ827 @
DMN65D8LW-7_SOT323-3~D
DOCK_DET#
<34,36,48>
<37,48>
+3.3V_ALW2
1
ACAV_IN
2
PQ825
DMN65D8LW-7_SOT323-3~D
+NBDOCK_DC_IN_SS
S
@ PQ824A
DMN66D0LDW-7 2N_SOT363-6~D
1
6
@ PR870
1
2
47K_0402_5%~D
1
D
2
G
0_0402_5%
1
240K_0402_5%~D
PR874
1
2
1M_0402_5%~D
B
<34,36,41,48>
@ PR872
<34,36,41,48>
+3.3V_ALW
S
3301_PWRSRC
1
2
2
SLICE_PERF_EN
SLICE_BAT_PRES#
DMN65D8LW-7_SOT323-3~D
1
S
3
1
2
PR853
0_0402_5%
2
PR848
1
1
2
@ PR868
1
2
3
+DC_IN_SS
EN_DK_PWRBAR
PC817
0.1U_0402_25V4Z~D
2
1
PC816
0.047U_0603_25V7M
2
1
PC815
0.1U_0603_25V7K~D
2
1
<47>
<47>
PQ822
NTR4502PT1G 1P SOT23-3
<34,36,48>
2
A
<37,48>
2
2
1M_0402_5%~D
SLICE_BAT_PRES#
@ PR863
1
2
0_0402_5%
CD3301BRHHR_QFN36_6X6~D
<36>
<37,48>
PD821
SDMK0340L-7-F_SOD323-2~D
PR836
100K_0402_5%~D
@ PR852
0_0402_5%
<37,47>
DOCK_AC_OFF_EC
PR858
1
@ PR860
0_0402_5%
2
1
10
11
12
13
14
15
16
17
18
37
ACAV_IN_NB
1
2
@ PR857
0_0402_5%
DK_AC_OFF_EN
SL_BAT_PRES#
1
2
2
1 PR840 2
100K_0402_5%~D
1
@ PR862
1
2
0_0402_5%
@ PR851
0_0402_5%~D
@ PR855
0_0402_5%
2
3301_ACAV_IN_NB 1
DK_AC_OFF
3
+3.3V_ALW2
@ PR859
1
2
0_0402_5%
27
26
25
24
23
22
21
20
19
SLICE_PERF_EN
@ PQ819A
DMN66D0LDW-7 2N_SOT363-6~D
1
ACAV_IN
P50ALW
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
GND
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
ACAV_IN#
3
<37,47,48>
DC_BLOCK_GC
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
<36,48>
2
@ PR834
5
2
@ PQ824B
@ PR875
100K_0402_5%~D
4
A
DMN66D0LDW-7 2N_SOT363-6~D
3
5
0_0402_5%
CD3301_SDC_IN
<47>
1
2
3
4
5
6
7
8
ACAVIN
P33ALW2 9
SDMK0340L-7-F_SOD323-2~D
DMN65D8LW-7_SOT323-3~D
2
ERC1
PD816
PQ828
+3.3V_ALW2
SLICE_BAT_ON
@
100K_0402_5%~D
0_0402_5%
1
@ PR854
1
2
@PR850
@
PR850
1
2
CD_PBATT_OFF
0_0402_5%
2
2
+SDC_IN
@ PR847
1
2ACAVDK_SRC
0_0402_5%
+5V_ALW
BAT54CW_SOT323~D
2
G
S
1
PQ821A
DMN66D0LDW-7 2N_SOT363-6~D
PR839
1
6 2
1
100K_0402_5%~D
DOCK_AC_OFF
<34>
PQ821B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
PR849
@ PR844
2
1
10K_0402_5%~D
100K_0402_5%~D
2
ACAV_DOCK_SRC#
1
3
@ PR843
0_0402_5%
2
1
<34,36,41>
D
+NBDOCK_DC_IN_SS
<34,36,48>
+PBATT
P50ALW
DOCK_DET#
<34,36,41,48>
1
100K_0402_5%~D
<34>
PU800
1
0_0402_5%
NC
CHARGERVR_DCIN
DC_IN_SS
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
PR846
<41> 1
SOFT_START_GC
2
2
@PR838
@
PR838
CSS_GC
DK_CSS_GC
ERC3
ERC2
GND
PWR_SRC
SS_DCBLK_GC
EN_DK_PWRBAR
P33ALW
+3.3V_ALW2
SLICE_PERF_EN
2
36
35
34
33
32
31
30
29
28
2
PC813
0.1U_0603_50V4Z~D
<37,48>
PD815
SLICE_BAT_PRES#
1
2
@ PR861
0_0402_5%
5
1
47_0805_5%~D
0_0402_5%
0_0402_5%~D
2
@ PR833
0_0402_5%
1
1
@
2
CD3301_DCIN
@
1
+CHGR_DC_IN
DSCHRG_MOSFET_GC
2
CHGVR_DCIN
DC_IN_SS
DK_PWRBAR
PR835
+DOCK_PWR_BAR
1 3301_DSCHRG_FET_GC
G
<47>
1
@
2 PR841
D
+DC_IN_SS
DMN65D8LW-7_SOT323-3~D
3
PR827
1
2
100K_0402_5%~D
DOCK_SMB_ALERT#
1
G
A
<36,48>
1
S
@ PR831
0_0402_5%
1
2
B
+DC_IN
@ PR832
0_0402_5%
2
1
2
2
100K_0402_5%~D
SLICE_BAT_ON
@ PR825
2
0_0402_5%
2
for Slice battery discharge
without AC exist
PR824 @
PR823
3
1
2
2
5
+3.3V_ALW2
PD819
SDMK0340L-7-F_SOD323-2~D
1
2
+3.3V_ALW2 Purpose: Turn on the PQ817
+3.3V_ALW2
1
B
O
D
1
<34,36,48>
1
PR829
2
100K_0402_5%~D
1
PQ813B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
3
S
100K_0402_5%~D
2
DOCK_DET#
G
PQ817
DMN65D8LW-7_SOT323-3~D
2 ACAV_IN#
1
4
C
+3.3V_ALW2
1
1
PR819 2
3
2
3
2
P
3
5
P
G
1
PU807
TC7SH08FU_SSOP5~D
PD814
SDMK0340L-7-F_SOD323-2~D
1
2
1
1
PC812
0.1U_0402_10V7K
2
1
PQ814
NTR4502PT1G 1P SOT23-3
2
D PQ832
DMN65D8LW-7_SOT323-3~D
2
G
6 2
PR826
2
PR828
1
2
10K_0402_5%~D
AC_DIS
1
<36,41>
PQ813A
DMN66D0LDW-7 2N_SOT363-6~D
1
3
<34,36,41,48>
PD820
SDMK0340L-7-F_SOD323-2~D
1
2
SLICE_BAT_PRES#
SLICE_BAT_PRES#
2
100K_0402_5%~D
+3.3V_ALW2
2
2
1
1
0_0402_5%
2
G
SDMK0340L-7-F_SOD323-2~D
PR830
100K_0402_5%~D
A
3
1
A
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
<34,36,41,48>
5
3
B
O
S
PD813
1
3
+3.3V_ALW
1
PQ829
SI2301CDS-T1-GE3 1P_SOT23-3
0_0402_5%~D
@ PR895
1
2
0_0402_5%
4
P
2
2
B
O
D
2
1
+3.3V_ALW2
@ PR894
1
PD810
3
8
7
6
5
PQ816
AO3418_SOT23-3
FDS6679AZ-G_SO8~D
4
0.1U_0402_10V7K
SDMK0340L-7-F_SOD323-2~D
PR822
4
PQ815
PC810
2
1
PU806
TC7SH08FU_SSOP5~D
2
1
10K_0402_5%~D
1
2
3
1
2
PR818
1
@
PC809
1500P_0402_7K~D
100K_0402_5%~D
C
G
1
2
3
PC808
0.1U_0402_10V7K
2
1
PU805
TC7SH08FU_SSOP5~D
+3.3V_ALW2
4
4
SLICE_PERF_EN
+PWR_SRC_AC
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Selector
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
1
Sheet
48
of
57
5
4
3
2
1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
D
D
1
2
1
PC900 @
22U_0805_6.3V6M
1
2
1
PC905
22U_0805_6.3V6M
1
2
2
1
PC901
22U_0805_6.3V6M
2
1
PC906
22U_0805_6.3V6M
1
PC910
22U_0805_6.3V6M
2
2
1
PC902 @
22U_0805_6.3V6M
2
1
PC907 @
22U_0805_6.3V6M
1
PC911@
22U_0805_6.3V6M
2
2
1
PC903 @
22U_0805_6.3V6M
2
1
PC908 @
22U_0805_6.3V6M
1
PC912 @
22U_0805_6.3V6M
2
2
PC904 @
22U_0805_6.3V6M
2
PC909
22U_0805_6.3V6M
1
PC913
22U_0805_6.3V6M
2
PC914
22U_0805_6.3V6M
C
C
1
2
1
PC915 @
22U_0805_6.3V6M
2
1
2
1
PC917
22U_0805_6.3V6M
1
PC921
22U_0805_6.3V6M
2
2
1
PC918
22U_0805_6.3V6M
1
PC922 @
22U_0805_6.3V6M
2
2
PC919 @
22U_0805_6.3V6M
1
PC923
22U_0805_6.3V6M
2
PC924 @
22U_0805_6.3V6M
1
1
2
+
PC928 @
22U_0805_6.3V6M
PC930
330U_D2_2.5VY_R9M
2
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR DECOUPLING
Size
Document Number
Date:
Friday, May 17, 2013
Rev
0.4
LA-9591P
Sheet
1
49
of
57
5
4
3
Version Change List ( P. I. R. List )
Item Page#
1
Title
P45
1.5VSP
Date
8/17
Request
Owner
Compal
2
1
Page 1
Issue Description
Base power budget request, add 1.5V powre rail
Solution Description
Rev.
Add PU400
D
D
2
P42
+5V/+3.3V
8/17
Compal
reserver PR114 for TPS51282 application
ADD @PR114
3
P47
Charger
8/17
Compal
EC can't detect charger IC cause can't charger
modify SMBus net for correct connect
4
P46
Vcore
8/17
Compal
schematic control error cause can't set OCP
add Vref net for correct connect
5
P48
Selector
8/17
Compal
in order to meet latest multi-battery request
change control signal for meet E5 request
6
P43
1.35V/0.675V
8/17
Compal
chagne OCP setting
change PR201 from 20k to 24.9k.
7
P42
+5V/+3.3V
10/22
Compal
Reserve 0ohm for 3v5v enable debug
Change PR113
from SD03420018L (S RES 1/16W 2K +-1% 0402)
to
SD028000080 (S RES 1/16W 0 +-5% 0402)
8
P44
+1.05V_MP
10/22
Compal
+1.05V_MP EA for ripple portion can't meet
spec. 31.5mv, after change from 1u to 2.2u test is pass
9
P42
+5V/+3.3V
10/22
Compal
Original 3v5v IC -TPS51225 can't support 2cell battery
follow TI suggestion, When TPS51285A/B is used,
please update the below four components.
1)VREG5 cap to 4.7uF
2)VREG3 cap to 4.7uF
3)CS1 resistor to 1/5 of the Tps51275’s value
4)CS2 resistor to 1/5 of the Tps51275’s value
5)VCLK connection (when not be used): add 200-ohm to GND
C
X01
C
Change PL300
from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A) X01
to
SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A)
Change PU100
from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM)
to
SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
X01
1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap)
from SE080105K80(S CER CAP 1U 10V K X5R 0603)
to
SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
3) Change PR106(for CS1)
from SD03484528L (S RES 1/16W 84.5K +-1% 0402)
to
SD034169280 (S RES 1/16W 16.9K +-1% 0402)
4) Change PR105(for CS2)
from SD03410038L (S RES 1/16W 100K +-1% 0402)
to
SD034200280 (S RES 1/16W 20K +-1% 0402)
5) Add
B
10
P47
P48
Charger
Selector
10/22
Compal
To avoid HW and Power SMT materials can't entirely
replace
11
P47
Charger
10/22
Compal
follow E5- Salado 14"15" schematic
12
P46
Vcore
11/02
Compal
follow TI suggestion modify setting value to meet Intel
VR12.6(ULV) validation EA
1) Imon
2) Loadline
3) transient
PR114 SD034200080(S RES 1/16W 200 +-1% 0402)
Change PU3,PU801,PU804,PU805,PU806,PU807
from SA74108040L(S IC 74AHC1G08GW SOT353 AND)
to
SA00708012L(S IC TC7SH08FU SSOP 5P AND)
X01
1) @PQ819, @PQ824
2) EMI request for add PL700
SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A)
1) Change PR501
from SD034422380 (S RES 1/16W 422K +-1% 0402)
to
SD034365380 (S RES 1/16W 365K +-1% 0402)
X01
B
X01
2) Change PR521
from SD000009M80 (S RES 1/16W 2.61K +-1% 0402)
to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402)
3) @PC506 100p_0402 and change PR535
from SD02810028L(S RES 1/16W 10K +-5% 0402)
to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF))
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 1
Size
4
3
2
Rev
0.4
LA-9591P
Date:
5
Document Number
Friday, May 17, 2013
Sheet
1
50
of
57
5
4
3
Version Change List ( P. I. R. List )
Item Page#
13
Title
P47
Charger
Date
Request
Owner
11/05 Compal
D
2
Page 1
Issue Description
1) TI suggestion BQ24715 cell pin pull high 3.3V change
to V_regn(6v) for sequence issue
2) Reserve 0 ohm for debug
14
+5V/+3.3V
P42
11/05
Compal
1
Solution Description
Rev.
1) Change PR711
from SD02800008L (S RES 1/16W 0 +-5% 0402)
to
SD034100280 (S RES 1/16W 10K +-1% 0402)
,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
X01
D
2) Add @PR751
follow E5- Salado 14"15" schematic
1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823
X01
2) Add @PR848, @PR851
and add PR834, PR852, PR853, all is
SD028000080(S RES 1/16W 0 +-5% 0402)
3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402)
4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
15
P47
Charger
11/05
Compal
16
P47
Charger
11/05
Compal
17
P44
+1.05VTTP
11/05
18
P48
+5V/+3.3V
11/05
Improve charger efficiency
Change PR715
from SD028200A80 (S RES 1/16W 20 +-5% 0402)
to
SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
follow E5- Salado 14"15" schematic
Delete @PR731, @PR733, @PU702
X01
C
C
1.35V/0.675V
+1.05V_MP
B
19
P48
Selector
11/15
Compal
Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip
-QAD team
resistance to 95K, Cpk value will pass specification.
-Huang.Hanks
(PCP)
Compal
- EMC team
Wen. Andy
Compal
EMC team suggestion
follow E5- Salado 14"15" schematic
for undock shutdown issue
X01
Change PR302
from SD00000H880 (S RES 1/16W 54.9K +-1% 0402)
to
SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
X01
@PC105, @PC203, @PC301
X01
Add
PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
@PR856 SD028000080 (S RES 1/16W 0 +-5% 0402),
PQ816 SB534020000 (S TR AO3402 1N SOT-23),
PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
X01
B
PR802, PR827, PR840 change
from SD028240380 (S RES 1/16W 240K +-5% 0402)
to SD028470280 (S RES 1/16W 47K +-5% 0402),
PR804, PR826, PR839 change
from SD028470280 (S RES 1/16W 47K +-5% 0402),
to SD028240380 (S RES 1/16W 240K +-5% 0402)
20
P47
Charger
P48
Selector
P41
+DCIN
Change PR713
from SD034294380 (S RES 1/16W 294K +-1% 0402)
to
SD034261380 (S RES 1/16W 261K +-1% 0402)
12/12 Compal
A
21
2013
Compal/01/11 ESD team
ESD team's PD1 vendor(NXP) proposal PD1 pin 5
connected to the VCC (5V or 3.3V).
X01
@PR844
PD1 pin5 connect to +3.3V_ALW
A
X01_2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 2
Size
4
3
2
Rev
0.4
LA-9591P
Date:
5
Document Number
Friday, May 17, 2013
Sheet
1
51
of
57
5
4
3
Version Change List ( P. I. R. List )
Item Page#
22
P48
Title
Date
Selector
2013/
01/23
D
Request
Owner
Compal
2
Page 1
Issue Description
To avoid +DOCK_PWR_BAR leakage voltage when system
only with main battery
1
Solution Description
Rev.
1). Add PU808
P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
X01_2
D
2). Add PQ830
P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3)
3). Add PQ831
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
4). Add PD821
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
5). Add PR836, PR837
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
6). Add PC814
P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
23
P41
+DCIN
C
24
P48
Selector
2013
Compal
/02/07
2013/ Compal
02/18
PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight
SB000009N8L will shortage after 2013/05
AC_DIS# should be change to AC_DIS because it’s
high active not low active for our application.
Change PQ6
From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62)
To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
X02
1). Change PQ6A.5 and PR828.1 net name from AC_DIS#
to AC_DIS
X02
2). Add PQ829
P/N: SB00000H500
, PQ832
P/N: SB00000UO00
, PD820
P/N: SCS0340L010
, @PR894
, PR895
P/N: SD028000080
C
(S TR SI2301CDS-T1-GE3 1P SOT23-3)
(S TR DMN65D8LW-7 1N SOT323-3)
(S SCH DIO SDMK0340L-7-F SOD-323)
(S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830
4). Delete PQ820
5). Delete PL5, add PJP1
B
25
P41
+DCIN
2013/ Compal-ME
02/18
26
P48
Selector
2013/ Compal
02/18
27
P41
+DCIN
2013
Compal/02/21 ESD team
Anderson
B
Battery connetor(locattion:PBATT1) footprint follow
ME team Iris requesti to change
from SUYIN_200277GR009M262ZR_9P-T
to ALLTO_C144LS-109A9-L_9P-T
X02
layout spec limit
Delete PD817, modify PD815 footprint same as PD701,
from SDMK0340L-7-F_SOD323-2
to RB717F_SOT323-3
X02
follow ESD team request
Goliad 14 need change PD1(6 pin*1) as Goliad 12
(3 pin*2), the main and 2nd source also,
these two ESD diode need to close battery connector
as possible.
X02
DFX highlight Battery connetor(locattion:PBATT1)
hard to insert.
Change PD1 and add PD2
From : SC300001100 (S DIO(BR) IP4223CZ6 SO-6 ESD)
To : SCA00001W00 (S ZEN ROW TVNST52302AB0 C/C SOT523
ESD after check 1.75X1.7xH=0.9mm
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Title : Compal LA-9591P - Schematics. www.s-manuals.com.
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