Compal LA 9611P Schematics. Www.s Manuals.com. R0.4 Schematics

User Manual: Motherboard Compal LA-9611P VIUS1 - Schematics. Free.

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2

3

4

5

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů
A

DŽĚĞůEĂŵĞ͗s/h^ϭ
&ŝůĞEĂŵĞ͗>ͲϵϲϭϭW
KDWͬE͗

A

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů

B

B

Dͬ^ĐŚĞŵĂƚŝĐƐŽĐƵŵĞŶƚ
/ŶƚĞů/ǀǇƌŝĚŐĞWƌŽĐĞƐƐŽƌǁŝƚŚZ///нWĂŶƚŚĞƌWŽŝŶƚW,
'WhD

ϮϬϭϮͲϬϮͲϭϴ
Zs͗Ϭ͘ϰ

C

C

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
Cover Sheet
LA-9611P
Tuesday, February 26, 2013
Sheet
1
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

A

B

C

D

E

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů
1

DŽĚĞůEĂŵĞ͗s/h^ϭ
&ŝůĞEĂŵĞ͗>ͲϵϲϭϭW
KDWͬE͗

D^ƵŶyd

ϮϯŵŵΎϮϯŵŵ
ZϯΎϰ
sZDϭϮϴDΎϭϲ
WĂŐĞϮϮΕϮϵ

W/Ͳyϴ

DĞŵŽƌǇƵƐ
Zϯ>ϭϲϬϬD,ǌ;ϭ͘ϱsͿ

h>s;ϭϳtͿ
'

ĞW

WĂŐĞϭϮ

DMI x4

,ƵĚŝŽ

;^ƵďŽĂƌĚͿ ,D/ŽŶŶĞĐƚŽƌ

/ŶƚĞů
WĂŶƚŚĞƌWŽŝŶƚ

,D/

2

;ŽĐŬŝŶŐͿ ŝƐƉůĂǇWŽƌƚ

W

WĂŐĞϯϭ

ƵĚŝŽĐŽŵďŽ:ĂĐŬ
h^ϯ͘Ϭ

Z:ϰϱKEE

^d

WĂŐĞϭϯΕϮϭ

WĂŐĞϯϯ

>Wh^

^W/ZKD /K^ϴD
WĂŐĞϯϯ

WĂŐĞϭϯ

3

h^WKZdϯ͘Ϭ

h^Ϯ͘Ϭ

^W/

Realtek RTL8111F

dWD

h^WKZdϯ͘Ϭ ;^ƵďŽĂƌĚͿ
h^WKZdϯ͘Ϭ ;ŽĐŬŝŶŐͿ

WĂŐĞϯϳ

dŽƵĐŚWĂŶĞů



ENE KBC9012 WĂŐĞϯϴ

W/ǆƉƌĞƐƐDŝŶŝĐĂƌĚ
WLAN / WiMAX / BT

WĂŐĞϯϱ

W/Ͳ;t>EͿ

/Ŷƚ͘<

h^;dͿ

ůŝĐŬWĂĚ
dƌĂĐŬWŽŝŶƚ

UCPU1

UCPU1

UCPU1

3

DK^ĂŵĞƌĂ
&ŝŶŐĞƌWƌŝŶƚĞƌ ;^ƵďŽĂƌĚͿ

WĂŐĞϯϲ

'Ͳ^ĞŶƐŽƌ

UPEK TCS5DH6C0

WĂŐĞϯϲ

dŚĞƌŵĂů^ĞŶƐŽƌ

^dϯ͘Ϭ,KEE

Fintek F75303M
CPU & RAM

WĂŐĞϯϲ

E'&&^^

dŚĞƌŵĂů^ĞŶƐŽƌ
Nuvuton NCT7718
Panel
;^ƵďŽĂƌĚͿ

4

UCPU1

ŝŐŝƚĂůD/

WĂŐĞϯϮ

2

&'ϵϴϵ
ϮϱŵŵΎϮϱŵŵ

Realtek RTS5229

ƵĚŝŽŽĚĞĐ
Realtek ALC3202

,Dϳϲ

W/Ͳ

;^ƵďŽĂƌĚͿ ĂƌĚZĞĂĚĞƌ
>E

ϮŚĂŶŶĞů^ƉĞĂŬĞƌ

100MHz
5GB/s

100MHz
2.7GT/s

WĂŐĞϯϬ

ZϯͲ^KͲ/DDyϭ

WĂŐĞϱΕϭϭ
FDI x8
(UMA)

ĞWŽŶŶĞĐƚŽƌ

1

/ŶƚĞů
/ǀǇƌŝĚŐĞ

UCPU1

;^ƵďŽĂƌĚͿ
4

ZZZ

LA-9611P
DA_PCB

DA8000X7000

CPU2@

i5-3337U

SA00006CU20

CPU3@

i3-3227U

SA00006ED20

CPU4@

i5-3437U

SA00006D940

CPU5@

i7-3537U

SA00006D840

Compal Secret Data

Security Classification

CPU6@

Ivy Bridgei7-3537U

Issued Date

SA00006DB30

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
Block Diagram
LA-9611P
Tuesday, February 26, 2013
Sheet
2
of
53

Size Document Number
Custom
Date:

E

Rev
0.4

1

2

3

4

5

Voltage Rails
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

STATE
+5VS

Full ON

Clock

+3VS
power
plane

+1.5VS
+VCCP
+5VALW

A

+CPU_CORE
+1.5V

+B

A

+VGA_CORE
+3VM

+3VALW

+VCC_GFXCORE_AXG
+1.05VM

+1.8VS
State

(SBA Only)

+0.75VS

BOARD ID Table

+1.05VS

O

S0

O

O

O

O

M3 Supported

S3

O

O

O

X

M3 Supported

S5 S4/AC

O

O

X

X

S5 S4/ Battery only

X

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

O
O
M3 Supported

Board ID
0
1
2
3
4
5
6
7

USB Port Table
USB 2.0 Port

PCB Revision
0.1
0.2
0.3

UHCI0
UHCI1
EHCI1
USB3.0

UHCI2
UHCI3
UHCI4

B

EHCI2

UHCI5
UHCI6

EC SM Bus1 address

BOM Structure Table
0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB 3.0 Port (I/O Board)
USB 3.0 Port (MB)
USB 3.0 Port (Docking)
Camera

BTO Item
Connector
Unpop
AMD
Intel UMA
VRAM Option
TPM
AOAC

BOM Structure
CONN@
@
DIS@
UMA@
X76@
TPM@
AOAC@

Touch Panel
(Test point)
Mini Card (WLAN/BT)
FPR

B

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011X b

Thermal Sensor Fintek F75303M

1001_101xb

PCH SM Bus address
Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

C

C

60%86&RQWURO7DEOH
6285&(
60%B(&B&.
60%B(&B'$
60%B(&B&.
60%B(&B'$
60%&/.
60%'$7$
60/&/.
60/'$7$
60/&/.
60/'$7$

.%
9$/:
.%
9$/:
3&+
9$/:
3&+
9$/:
3&+
9$/:

9*$

%$77

.(

:/$1
62',00 ::$1

7KHUPDO
6HQVRU

3&+

9

;

;

;

;

;

;

;

;

;

;

;

9
96

;

;

;

96

9

96

9

;

;

;

;

;

;

;

;

;

9

;

96

9

;

;

96

9

;

;

96

9$/:

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
Notes List
LA-9611P
Tuesday, February 26, 2013
Sheet
3
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

G3

4

5

S0

S5

RTC
RTCRST

MB Bottom view

EC_111 pin
EC_ON

FIDUCIAL_C40M80

FD3
@

FIDUCIAL_C40M80

MAINPWON

FD4
@

FIDUCIAL_C40M80

A

+5VALW

@

1

1

1

FD2
@

1

FD1

A

FIDUCIAL_C40M80

+3VALW/VCCDSW
ON/OFF#
EC_RSMRST#
PBTN_OUT#
SLP_S5#
SLP_S4#
SYSON
SYSON
M_PWR_ON
PCH_APWROK

B

B

SLP_S3#
SUSP#
+1.5V_CPU_VDDQ
+1.8VS

PCH

+5VS
+3VS
+1.5VS

GPU

+0.75VS
+V1.05VS(VCCP)
+VCCSA

RAM

SA_PGOOD

CPU

99ms

VR_ON

C

C

PCH_POK
PCH_CLKOUT
DRAMPWROK
H_CPUPWRGD
CPU_VID
CPU_CORE
VGATE
SYS_PWROK
ME and BIOS
activity will continue

BUF_PLT_RST#
SPI

H12
H_4P0

H13
H_4P0

H14
H_4P0

H15
H_4P0

H16
H_4P0

H18
H_4P2

H21
H_2P3

H22
H_2P5

@

H23
H_2P3

JLB1
SHAPE354X512
@

1

@

H10
H_4P0

1

@

H9
H_4P0

1

@

H8
H_2P3

1

@

H7
H_3P3

1

@

H6
H_2P3

1

@

H5
H_2P7

1

@

H3
H_4P2

1

@

H4
H_4P2

1

1

H2
H_4P2

1

H1
H_4P2
D

H24
H_2P2X1P8N

DMI

Tralning
D

@

JLB2
CLIP_3X15

Compal Secret Data

@

1

@

1

@

1

@

1

@

1

@

1

@

1

@

1

@

1

1

1

Security Classification
@

@

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
Screw Hole
LA-9611P
Tuesday, February 26, 2013
Sheet
4
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

A

A

+1.05VS
UCPU1A

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

N3
P7
P3
P11

[15]
[15]
[15]
[15]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

[15]
[15]
[15]
[15]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

K1
M8
N4
R2
K3
M7
P4
T3

U7
W11
W1
AA6
W6
V4
Y2
AC9
U6
W10
W3
AA7
W7
T4
AA3
AC8
AA11
AC12

[15] FDI_FSYNC0
[15] FDI_FSYNC1

U11

[15] FDI_INT

AA10
AG8

[15] FDI_LSYNC0
[15] FDI_LSYNC1

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

+1.05VS
2
R2 1
24.9_0402_1%

EDP_COMP

[30] CPU_eDP_HPD#

AF3
AD2
AG11
AG4
AF4

[30] CPU_eDPC_AUXN
[30] CPU_eDPC_AUXP

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX

[30] CPU_eDPC_N0
[30] CPU_eDPC_N1

AC1
AA4
AE10
AE6

[30] CPU_eDPC_P0
[30] CPU_eDPC_P1

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP

C

AC3
AC4
AE11
AE7

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PCI EXPRESS -- GRAPHICS

[15]
[15]
[15]
[15]

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

Intel(R) FDI

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

B

[15]
[15]
[15]
[15]

M2
P6
P1
P10

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

G3
G1
G4

PEG_COMP

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P7

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N7

C1
C2
C3
C4
C5
C6
C7
C8

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P7

C10
C11
C13
C12
C15
C14
C16
C17

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7

R1

1

2 24.9_0402_1%

PCIE_CRX_GTX_N[0..7]

[23]

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2
PCIE_CRX_GTX_P[0..7]

*

[23]

1: Normal Operation; Lane #
socket pin map definition

definition matches

0:Lane Reversed

B

PCIE_CTX_GRX_N[0..7]

[23]

PCIE_CTX_GRX_P[0..7]

[23]

C

ŚĞĐŬ'WhW/ͲĞh^ƐƉĞĞĚ
'ĞŶϮ͗сϬ͘ϭƵ&
'ĞŶϯ͗сϬ͘ϮϮƵ&

IVY-BRIDGE_BGA1023
CPU1@

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEGRev
0.4
LA-9611P
Tuesday, February 26, 2013
Sheet
5
of
53

Size Document Number
Custom
Date:

5

1

2

3

4

5

UCPU1B

1

C57

2 10K_0402_5%

@

PROC_DETECT#

+1.05VS
1

T1
1

C49

H_CATERR#

TPC12
R5
62_0402_5%

A48

PECI

2

[18,38] H_PECI

R12

[38] H_PROCHOT#

1

2 56_0402_5%

C45

H_PROCHOT#_R

D45

[18] H_THRMTRIP#

1

C2215

2 100P_0402_50V8J
@

PROCHOT#

PWR MANAGEMENT

B46

[18] H_CPUPWRGD

PM_SYS_PWRGD_BUF

2

1

R25

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

C48

2 130_0402_5% PM_DRAM_PWRGD_R

C33
220P_0402_50V7K
@

BUF_CPU_RST#

ESD Request

BE45

D44

CLK_CPU_DMI_R
CLK_CPU_DMI#_R

R4
R7

1
1

@
@

2 0_0402_5%
2 0_0402_5%

AG3
AG1

CLK_CPU_DP_R
CLK_CPU_DP#_R

R20
R23

1
1

@
@

2 0_0402_5%
2 0_0402_5%

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

R13
R14
R15

1
1
1

A

CLK_CPU_DMI [14]
CLK_CPU_DMI# [14]
CLK_CPU_DP [14]
CLK_CPU_DP# [14]

AT30
BF44
BE43
BG43

H_DRAMRST#

[7]

2 140_0402_1%
2 25.5_.402_1%
2 200_0402_1%

ZϯŽŵƉĞŶƐĂƚŝŽŶ^ŝŐŶĂůƐ

THERMTRIP#

PM_SYNC

B

1

SM_DRAMRST#

ESD Request

[15] H_PM_SYNC

J3
H2

CATERR#

THERMAL

WƌŽĐĞƐƐŽƌWƵůůƵƉƐ

DPLL_REF_CLK
DPLL_REF_CLK#

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

TCK
TMS
TRST#

JTAG & BPM

R8

PROC_SELECT#

BCLK
BCLK#

DDR3
MISC

[18] H_SNB_IVB#

MISC

F49

CLOCKS

A

TDI
TDO

DBR#

N53
N55

XDP_PRDY#
XDP_PREQ#

L56
L55
J58

XDP_TCK
XDP_TMS
XDP_TRST#

R21
R17
R22

1
1
1

@
@
@

2 51_0402_5%
2 51_0402_5%
2 51_0402_5%

M60
L59

XDP_TDI
XDP_TDO

R18
R19

1
1

@
@

2 51_0402_5%
2 51_0402_5%

K58

XDP_DBRESET#

WhͬWĨŽƌ:d'ƐŝŐŶĂůƐ

1

+1.05VS

B

T4

TPC12
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

G58
E55
E59
G55
G59
H60
J59
J61

IVY-BRIDGE_BGA1023
CPU1@

+3VALW

+1.5V_CPU_VDDQ

Buffered reset to CPU

C34 @
0.1U_0402_10V6K

+3VS

2

1
R34
75_0402_5%

2

[17] PCH_PLTRST#

NC

Y
A

4

BUFO_CPU_RST#

R36
43_0402_1%
1
2

U2
SN74LVC1G07DCKR_SC70-5

G

2

D
2

[39] SUSP

BUF_CPU_RST#
R38
0_0402_5%
@

1 2

3

3

1

1
R37
39_0402_5%
@

1

5

PM_SYS_PWRGD_BUF

P

4

2

5

C35
0.1U_0402_10V6K

2

P
O

A

1

U1 @
74AHC1G09GW_TSSOP5

G

2

[15] PM_DRAM_PWRGD

B

+1.05VS

R33
200_0402_5%

2
R35 @
10K_0402_5%
1
2 1

C

1

1

G

+3VS
C

Q1
2N7002K_SOT23-3
@

3

S
PM_DRAM_PWRGD

R214 1

@

2 0_0402_5%

PM_SYS_PWRGD_BUF

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLKRev
0.4
LA-9611P
Tuesday, February 26, 2013
Sheet
6
of
53

Size Document Number
Custom
Date:

5

1

2

3

4

UCPU1C

5

UCPU1D

[12] DDR_A_D[0..63]

B

BD37
BF36
BA28

[12] DDR_A_BS0
[12] DDR_A_BS1
[12] DDR_A_BS2

SA_BS[0]
SA_BS[1]
SA_BS[2]

C

BE39
BD39
AT41

[12] DDR_A_CAS#
[12] DDR_A_RAS#
[12] DDR_A_WE#

SA_CAS#
SA_RAS#
SA_WE#

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

M_CLK_DDR0 [12]
M_CLK_DDR#0 [12]
DDR_CKE0_DIMMA [12]

AT40
AU40
BB26

M_CLK_DDR1 [12]
M_CLK_DDR#1 [12]
DDR_CKE1_DIMMA [12]

BB40
BC41

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

AY40
BA41

[12]
[12]

M_ODT0 [12]
M_ODT1 [12]

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

[12]

[12]

[12]

BG39
BD42
AT22

AV43
BF40
BD45

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

CPU1@

CPU1@

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

DDR SYSTEM MEMORY B

A

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

DDR SYSTEM MEMORY A

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22
A

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

B

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

C

+1.5V

1

2 0_0402_5%

@

1

R39

D

S

1

1

R41
1K_0402_5%
1
2

DDR3_DRAMRST#

[12]

Q2
BSS138_NL_SOT23-3

2

2

G

R42
4.99K_0402_1%

DDR3_DRAMRST#_R

2

R40
1K_0402_5%
3

[6] H_DRAMRST#

D

[10,14] DRAMRST_CNTRL_PCH

D

DRAMRST_CNTRL
1

DRAMRST_CNTRL

[10,14]

C36
0.047U_0402_16V4Z

Compal Secret Data

Security Classification

2

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
LA-9611P
Tuesday, February 26, 2013
Sheet
7
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

CFG Straps for Processor
1

CFG2

2

A

R45
1K_0402_1%
@

A

PEG Static Lane Reversal - CFG2 is for the 16x
UCPU1E

CFG2

CFG4
CFG5
CFG6
CFG7

R48
49.9_0402_1%
2

1

@

@

2 100_0402_1%

VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE

2 100_0402_1%

R47

1

@

2 49.9_0402_1%

VSS_AXG_VAL_SENSE

R49

1

@

2 49.9_0402_1%

VSS_VAL_SENSE

T2

1

H45
K45
F48

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40

M13
M14
U14
W14
P13

R50
1K_0402_1%

AT49
K24

Display Port Presence Strap
B

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AH2
AG13
AM14
AM15

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

*

N50

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

TPC12
H48
K48
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

C

CFG5
CFG6

RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

1

R176

1

VCC_VAL_SENSE
VSS_VAL_SENSE

CFG4

R52 @
1K_0402_1%

R51
1K_0402_1%
2

R179

H43
K43

VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD30
RSVD31
RSVD32
RSVD33

P+

definition matches

0:Lane Reversed

N42
L42
L45
L47

1

@

@
2

B

BCLK_ITP
BCLK_ITP#

1: Normal Operation; Lane #
socket pin map definition

2

R46
49.9_0402_1%

1

+CPU_CORE

1

+VCC_GFXCORE_AXG

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

*

N59
N58

1

CFG2

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

2

XDP_CFG0

RESERVED

T3

1

PCIE Port Bifurcation Straps

CFG[6:5]

*

—
—
—
—

00
01
10
11

=
=
=
=

1 x8, 2 x4 PCI Express*
reserved
2 x8 PCI Express*
1 x16 PCI Express*

C

IVY-BRIDGE_BGA1023
CPU1@

1

CFG7

2

@ R53
1K_0402_1%

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
LA-9611P
Sheet
Tuesday, February 26, 2013
8
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

2

3

+CPU_CORE
UCPU1F

ͺǤͷ

PEG IO AND DDR IO

A

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

B

+1.05VS
W16
W17

VCCIO50
VCCIO51

Chief-River platforms
VCCIO_SEL = pulled high
BC22

VCCIO_SEL

H_VCCP_SEL

R78

1

+3VS

2 10K_0402_5%
+1.05VS

+1.05VS

+1.05VS

1

1
R54
130_0402_5%

2

R55
75_0402_5%

A44
B43
C44

VIDALERT#
VIDSCLK
VIDSOUT

H_CPU_SVIDALRT#

R56

1

2 43_0402_1%

VR_SVID_ALRT# [48]
VR_SVID_CLK [48]
VR_SVID_DAT [48]

+CPU_CORE

Trace Impedance = 27 ~ 33 ohm
Trace Length Match < 25 mils
VCCSENSE
VSSSENSE
R64
AN16
AN17

1

Place the PU
resistors close to CPU
VCCSENSE [48]
VSSSENSE [48]

+1.05VS
2 10_0402_1%

VCCIO_SENSE
VSSIO_SENSE

R62
100_0402_1%

VCCIO_SENSE [46]
VSSIO_SENSE [46]
1

2

VCCIO_SENSE
VSS_SENSE_VCCIO

R59
100_0402_1%

2 100_0402_1%

1

F43
G43

VCC_SENSE
VSS_SENSE

@

2

R174 1

SENSE LINES

2

C

C38
0.1U_0402_10V6K

1

SVID

2

C37
0.1U_0402_10V6K

2

C161
1U_0402_6.3V6K

Place the PU
resistors close to VR

1

1

AM25
AN22

VCCPQE[1]
VCCPQE[2]

2

C

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

QUIET
RAILS

B

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

CORE SUPPLY

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

5

+1.05VS

POWER

͵͵
ȋȌ
A

4

1

1

R63
10_0402_1%
IVY-BRIDGE_BGA1023

D

2

D

CPU1@

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
Rev
0.4
LA-9611P
Tuesday, February 26, 2013
9
of
53
Sheet

Size Document Number
Custom
Date:

5

2

3

+VREF_DQ_DIMMA

1

1

1

2

D

S
2

1

R79
1K_0402_1%
@

G

VREF

2 0_0402_5%

@

3

+V_DDR_REFA_R

A

DRAMRST_CNTRL

DRAMRST_CNTRL

[14,7]

2

- 1.5V RAILS
DDR3

2

1

2

@

1

2

@

1

2

1
+
2

330U_D2_2V_Y

2

1

C46

2

1

10U_0603_6.3V6M

1

C45

GRAPHICS

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

C44

2

1

ͷ
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

10U_0603_6.3V6M

1

R67

Q3
BSS138_NL_SOT23-3

R72
1K_0402_5%

C43

[48] VCC_AXG_SENSE
[48] VSS_AXG_SENSE

+V_DDR_REFA_R
+V_DDR_REFB_R

10U_0603_6.3V6M

2 100_0402_1%

@

+V_SM_VREF_CNT

BE7
BG7

C42

1

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

AY43

10U_0603_6.3V6M

R73

SM_VREF

C41

+VCC_GFXCORE_AXG

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

Dϯ^ƵƉƉŽƌƚ

R68
1K_0402_5%

10U_0603_6.3V6M

B

POWER

C40

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

A

R65
10_0402_1%

UCPU1G

͵͵
ȋ ʹȌ

5

+1.5V_CPU_VDDQ

+V_SM_VREF should
have 10 mil trace width

+VCC_GFXCORE_AXG

4

2

1

B

2 0_0805_5%

@

1
+

@

2

330U_D2_2V_Y

@ 2

C59

1

1U_0402_6.3V6K

2

C58

1

1U_0402_6.3V6K

2

C57

1

10U_0603_6.3V6M

C56

C

+VCCSA

+
@

2

330U_D2_2V_Y

2

C52

@

1

10U_0603_6.3V6M

2

C51

1

10U_0603_6.3V6M

2

C50

1

10U_0603_6.3V6M

C49

2

10U_0603_6.3V6M

C48

1

1

BB3
BC1
BC4

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

͸
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

SA RAIL

1

R76

1.8V RAIL

+1.5V_CPU_VDDQ

AM28
AN26
1

VCCDQ[1]
VCCDQ[2]

2

ͳǤʹ

C162
1U_0402_6.3V6K

+1.5V

C47

1

2 0.1U_0402_10V6K

C53

1

2 0.1U_0402_10V6K

@

C54

1

2 0.1U_0402_10V6K

@

C55

1

2 0.1U_0402_10V6K

C

SENSE LINES

+1.8VS_VCCPLL
+1.8VS

VDDQ_SENSE
VSS_SENSE_VDDQ

BC43
BA43

ΪͳǤͷ̴̴ 
+1.5V_CPU_VDDQ

+1.5V
JP1 @
2
VCCSA_SENSE

U10

R75

1

@

2 0_0402_5%

1

PAD-OPEN 4x4m
U2409
+5VALW

VCCSA VID
lines

VAXG_SENSE
VSSAXG_SENSE

SENSE
LINES

2

F45
G45

QUIET RAILS

1

+1.5V_CPU_VDDQ
R66
10_0402_1%

@
C2327

VCCSA_VID[0]
VCCSA_VID[1]

D48
D49

H_VCCSA_VID0
H_VCCSA_VID1

1

2 1U_0402_6.3V6K

6
4

[45]
[45]

CT

GND
GND

9
5

VBIAS
+1.5V_CPU_VDDQ

+1.5V
2
1

R203
IVY-BRIDGE_BGA1023

[25,38,39,44,46,47]

SUSP#

1

3

2RUN_ON_CPU1.35VS3

VIN

VOUT

VIN

VOUT

8
7

ON

15K_0402_5%

CPU1@

1
D

C65
0.047U_0402_16V4Z

TPS22965DSGR_SON8_2X2~D
D

2

Vaxg
Ʉ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
Ʉ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

1

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(6/7) PWR
LA-9611P
Tuesday, February 26, 2013
Sheet
10
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

2

3

4

UCPU1H

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

A

B

C

5

UCPU1I

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS

NCTF

1

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

A

B

1
1
1

1
1

1

T101
T102
T103

PAD @
PAD @
PAD @

T108
T109

PAD @
PAD @

T114

PAD @
C

IVY-BRIDGE_BGA1023
CPU1@

IVY-BRIDGE_BGA1023
CPU1@

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PROCESSOR(7/7) VSS
LA-9611P
Tuesday, February 26, 2013
Sheet
11
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

+1.5V

5

+1.5V

1

+1.5V

4

2

R2001
1K_0402_1%
JDIMM1

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

All VREF traces should
have 10 mil trace width

DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2

1

1

+
@

2

B

DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 [7]
M_CLK_DDR#1 [7]

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 [7]
DDR_A_RAS# [7]

DDR_CS0_DIMMA#
M_ODT0

DDR_CS0_DIMMA# [7]
M_ODT0 [7]

M_ODT1

M_ODT1 [7]

+1.5V

R2004
1K_0402_1%

+0.75VS
@

+VREF_CA

@

DDR_A_D36
DDR_A_D37
@

1

2

DDR_A_D38
DDR_A_D39

1

2

R2005
1K_0402_1%

1

2

1

2

1

2

1

2

Layout Note:
Place near
JDIMM1.203,204

C

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3

SMB_DATA_S3 [14,30,35,36]
SMB_CLK_S3 [14,30,35,36]
+0.75VS

206

LCN_DAN06-K4406-0102
CONN@

D

2

2

1

330U_D2_2V_Y

G2

2

C2014

G1

@

1

10U_0603_6.3V6M

205
R2007
0_0402_5%
@

2

C2013

2

R2006 0_0402_5%

@

1

2.2U_0603_6.3V6K

2

C2022

@

1

0.1U_0402_10V6K

2

C2046

@

0.1U_0402_10V6K

C2021

1

D

1

10U_0603_6.3V6M

+3VS
+0.75VS

2

1U_0402_6.3V6K

DDR_A_D58
DDR_A_D59

1

C2012

DDR_A_D56
DDR_A_D57

2

C2020

DDR_A_D50
DDR_A_D51

@

1

10U_0603_6.3V6M

DDR_A_DQS#6
DDR_A_DQS6

2

1U_0402_6.3V6K

DDR_A_D48
DDR_A_D49

@

1

C2019

DDR_A_D42
DDR_A_D43

DDR_A_MA6
DDR_A_MA4

2

1U_0402_6.3V6K

DIMM_A H:4.0mm

2

1

C2018



DDR_A_MA11
DDR_A_MA7

1

1U_0402_6.3V6K

DDR_A_D40
DDR_A_D41

DDR_A_MA15
DDR_A_MA14

C2017

C

DDR_CKE1_DIMMA [7]

0.1U_0402_10V6K

DDR_A_D34
DDR_A_D35

DDR_CKE1_DIMMA

C2016

PN:SP07000LB00

2

+1.5V

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

2.2U_0603_6.3V6K

DDR_A_DQS#4
DDR_A_DQS4

2

1

DDR_A_D30
DDR_A_D31

C2015

DDR_A_D32
DDR_A_D33

2

1

C2011

[7] DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

2

DDR_A_DQS#3
DDR_A_DQS3

1

10U_0603_6.3V6M

DDR_A_WE#
DDR_A_CAS#

1

Layout Note:
Place near
JDIMM1

0.1U_0402_10V6K

[7] DDR_A_WE#
[7] DDR_A_CAS#

@

C2010

[7] DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

DDR_A_D28
DDR_A_D29

C2006

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D22
DDR_A_D23

10U_0603_6.3V6M

[7] M_CLK_DDR0
[7] M_CLK_DDR#0

+1.5V

0.1U_0402_10V6K

DDR_A_MA3
DDR_A_MA1

DDR_A_D20
DDR_A_D21

C2009

DDR_A_MA8
DDR_A_MA5

DDR3_DRAMRST# [7]

10U_0603_6.3V6M

DDR_A_MA12
DDR_A_MA9

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

A

[7]

DDR_A_D14
DDR_A_D15

C2005

DDR_A_BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR3_DRAMRST#

0.1U_0402_10V6K

[7] DDR_A_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

[7]

DDR_A_D12
DDR_A_D13

C2008

DDR_CKE0_DIMMA

[7]
[7]

DDR_A_MA[0..15]

10U_0603_6.3V6M

[7] DDR_CKE0_DIMMA

DDR_A_D[0..63]

DDR_A_D6
DDR_A_D7

C2007

B

DDR_A_DQS#0
DDR_A_DQS0

C2004

DDR_A_D26
DDR_A_D27

DDR_A_DQS[0..7]

0.1U_0402_10V6K

DDR_A_D24
DDR_A_D25

DDR_A_DQS#[0..7]

DDR_A_D4
DDR_A_D5

C2003

DDR_A_D18
DDR_A_D19

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

DDR_A_D8
DDR_A_D9

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_A_D2
DDR_A_D3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

2

DDR_A_D0
DDR_A_D1

2

1
2

1

0.1U_0402_10V6K

2

C2002

@

1

2.2U_0603_6.3V6K

C2001

R2003
1K_0402_1%

A

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+VREF_DQ_DIMMA

+VREF_DQ_DIMMA

@

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
DDRIII DIMMA
LA-9611P
Tuesday, February 26, 2013
Sheet
12
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

PCH_RTCX1
1

R87

2 10M_0402_5%

PCH_RTCX2

W=20mils
+RTCVCC

PIN2

+RTCBATT

Y1
1

PIN1

W=20mils

RTC conn

R106
1K_0402_5%
1
2

2

2

2

C64
18P_0402_50V8J

C179
1U_0402_6.3V6K

CLRP1
SHORT PADS

CLRP1, JCMOS1, JME1 place near the door

2

1
1
C63
18P_0402_50V8J

1

32.768KHZ_12.5PF_CM31532768DZFT
1

2

CMOS

1

2 20K_0402_5%

PCH_SRTCRST#

G22

ME

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

2 330K_0402_5%

PCH_INTVRMEN

C66
1U_0402_6.3V6K

1

2

1

SM_INTRUDER#

@

H烉
烉Integrated VRM enable
L烉
烉Integrated VRM disable

(INTVRMEN should always be pull high.)

HDA_BIT_CLK

N34

HDA_SYNC

L34
T10

HDA_SPKR

[32] HDA_SPKR

K34

HDA_RST#

+3VS
1

R93

*

@

2 1K_0402_5%

HDA_SPKR

E34

HDA_SDIN0

[32] HDA_SDIN0

G34

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

C34
A34

B

+3VS

[38] ME_FLASH

+3V_PCH
R95

1

@

2 1K_0402_5%

R202 1

HDA_SDOUT

2 10K_0402_5% WLBT_OFF_5#

*

R209 1

R96

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

1

@

2 0_0402_5%

1

@

A36

HDA_SDOUT
WLBT_OFF_5#

C36

2 10K_0402_5%

PCH_GPIO13

N32

2 51_0402_5%

PCH_JTAG_TCK

J3

PCH_JTAG_TMS

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

[35] WLBT_OFF_5#
+3V_PCH

HDA_SDO

R94

LPC

D20

R89

RTCX2
RTCRST#

P+ FWH0 / LAD0
P+ FWH1 / LAD1
P+ FWH2 / LAD2
P+ FWH3 / LAD3
FWH4 / LFRAME#

SRTCRST#
INTRUDER#
INTVRMEN

P+
P+

SERIRQ

HDA_BCLK
HDA_SYNC

P-

SPKR

P-

HDA_RST#
HDA_SDIN0

P-

HDA_SDIN1

P-

HDA_SDIN2

P-

HDA_SDIN3

P-

HDA_SDO

P-

LDRQ0#
LDRQ1# / GPIO23

SATA 6G

PCH_RTCRST#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_DOCK_EN# / GPIO33

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA

2 20K_0402_5%

RTCX1

RTC

C20

1

INTVRMEN

*

PCH_RTCX2

R88

2

1

R91

A20

IHDA

2 1M_0402_5%

A

U2408A
PCH_RTCX1

JME1
SHORT PADS

1

R90

@

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

P-

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

P+

SATAICOMPO

JTAG_TDI

P+

JTAG_TDO

JTAG

2

+RTCVCC

1

1

2

C62
1U_0402_6.3V6K

+RTCVCC

JCMOS1
SHORT PADS

A

SATAICOMPI
SATA3RCOMPO
SATA3COMPI

+3V_PCH

*

1

2 1K_0402_5%

HDA_SYNC

SPI_CLK_PCH_R

T3
Y14

This signal has a weak internal pull-down

SPI_SB_CS0#

On Die PLL VR Select is supplied by
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

SPI_SI

V4

SPI_SO_R

U3

T1

SPI_CLK

SATA3RBIAS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

D36

LPC_FRAME#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

[37,38]
[37,38]
[37,38]
[37,38]

LPC_FRAME#

[37,38]

E36
K36
V5

SERIRQ

AM3
AM1
AP7
AP5

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0

AM10
AM8
AP11
AP10

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

SERIRQ [37,38]
SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0

[34]
[34]
[34]
[34]

HDD

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

[34]
[34]
[34]
[34]

m-SATA

AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1

+3VS
RP5

Y7
Y5
AD3
AD1

[18,38] GATEA20
[14] CLK_BUF_PCIE_SATA#
[14] CLK_BUF_PCIE_SATA

SPI_CS1#
SPI_MOSI

P-

SPI_MISO

P+

SATALED#
SATA0GP / GPIO21

P+

SATA1GP / GPIO19

B

1
2
3
4

SERIRQ
GATEA20
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

Y3
Y1
AB3
AB1

8
7
6
5
10K_8P4R_5%

+1.05VS
Y11
Y10

SATA_COMP

+1.05VS_VCC_SATA

SATA_COMP

R97

1

2 37.4_0402_1%

+1.05VS_SATA3

SATA3_COMP

R98

1

2 49.9_0402_1%

RBIAS_SATA3

R100 1

AB12
AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

PCH_GPIO19

2 750_0402_1%
+3VS

RP3
1
2
3
4

PCH_GPIO21
PCH_GPIO49
PCH_GPIO22
KB_RST#

SPI_CS0#

SPI

R99

C38
A38
B37
C37

[18] PCH_GPIO49
[18] PCH_GPIO22
[18,38] KB_RST#

8
7
6
5
10K_8P4R_5%

PANTHER-POINT_FCBGA989

PCH_SATALED#

R101 1

2 10K_0402_5%

PCH_GPIO19

R103 1

2 10K_0402_5%

C

C

Prevent back drive issue.
+5VS

3

1

ϴD^W/ZKD&KZϭ͘ϱDD
ΘEŽŶͲƐŚĂƌĞZKD͘

HDA_SYNC

D

+3VS
+3VS

U5 8M

Q8
BSS138_NL_SOT23-3

1

HDA_BIT_CLK
HDA_SYNC_R
HDA_RST#
HDA_SDOUT

S

8
7
6
5

G

1
2
3
4

[32] HDA_BITCLK_AUDIO
[32] HDA_SYNC_AUDIO
[32] HDA_RST_AUDIO#
[32] HDA_SDOUT_AUDIO

2

EMI

RP9

C191 1

2 0.1U_0402_10V6K

SPI_WP#

R334

1

2

3.3K_0402_5%

SPI_HOLD#

R335

1

2

3.3K_0402_5%

33_8P4R_5%
R303
1M_0402_5%

U5

2

SPI_SB_CS0#
SPI_SO_R
SPI_WP#

1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DI

8
7
6
5

SPI_HOLD#
SPI_CLK_PCH_R
SPI_SI

W25Q32BVSSIG_SO8

KE
ϴD͗^ϬϬϬϬϰϲϰϬϬ^/&>ϲϰDEϮϱYϲϰͲϭϬϰ,/W^KWϴW

+3V_PCH

+3V_PCH

+3V_PCH

2

PCH_JTAG_TMS

PCH_JTAG_TDI

1

Compal Secret Data

Security Classification

R125 @
100_0402_1%

Issued Date

2

R124 @
100_0402_1%
2

2

R123 @
100_0402_1%

R122 @
200_0402_5%

1

2

R121 @
200_0402_5%

1

PCH_JTAG_TDO

1

2

R120 @
200_0402_5%

1

1

D

1

D

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3

4

Title

Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC
LA-9611P
Tuesday, February 26, 2013
Sheet
13
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

+3V_PCH
PCH_SMBCLK

R128

1

@

2

2.2K_0402_5%

PCH_SMBDATA

R129

1

@

2

2.2K_0402_5%

PCH_SML0CLK

R130

1

2

2.2K_0402_5%

PCH_SML0DATA

R131

1

2

2.2K_0402_5%

U2408B

BG36
BJ36
AV34
AU34
[33]
[33]
[33]
[33]

PCIE LAN

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

C80
C81

1
1

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38

R147 1
R149 1

[37] CLK_PCIE_CARD#
[37] CLK_PCIE_CARD

B

Card Reader

@
@

2 0_0402_5%
2 0_0402_5%

CARD_CLKREQ#

[37] CARD_CLKREQ#
R141 1
R142 1

[35] CLK_PCIE_WLAN1#
[35] CLK_PCIE_WLAN1

Wireless LAN

CLK_CARD#
CLK_CARD

@
@

2 0_0402_5%
2 0_0402_5%

CLK_MINI1#
CLK_MINI1
WLAN_CLKREQ1#

[35] WLAN_CLKREQ1#

Y40
Y39
J2
AB49
AB47
M1
AA48
AA47

R145 1
R146 1

[33] CLK_PCIE_LAN#
[33] CLK_PCIE_LAN

PCIE LAN

@
@

2 0_0402_5%
2 0_0402_5%

PCH_GPIO20

V10

CLK_LAN#
CLK_LAN

Y37
Y36

LAN_CLKREQ#

[33] LAN_CLKREQ#

A8
Y43
Y45

+3VS
R170 1
R162 1

@

2 10K_0402_5%

WLAN_CLKREQ1#

2 10K_0402_5%

PCH_GPIO20

PCH_GPIO26

L12
V45
V46

+3V_PCH
PCH_GPIO44
R177 1

2 10K_0402_5%

CARD_CLKREQ#

2 10K_0402_5%

PCH_GPIO26

L14

PERN2
PERP2
PETN2
PETP2

SMBDATA

PERN3
PERP3
PETN3
PETP3

PERN6
PERP6
PETN6
PETP6

SML0CLK
SML0DATA

1

@

2

2.2K_0402_5%

H14

PCH_SMBCLK

PCH_SML1DATA

R132

1

@

2

2.2K_0402_5%

C9

PCH_SMBDATA

PCH_HOT#

A12

DRAMRST_CNTRL_PCH

C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

PCH_SML1CLK

M16

PCH_SML1DATA

DRAMRST_CNTRL_PCH

[10,7]

R133

1

2

10K_0402_5%

PCH_GPIO11

R135

1

2

10K_0402_5%

DRAMRST_CNTRL_PCH

R127

1

2

1K_0402_5%

+3VS

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

SML0ALERT# / GPIO60

R126

SML1ALERT# / PCHHOT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75

6

1

Q9A

PERN8
PERP8
PETN8
PETP8

P+/PP+/P-

CL_CLK1
CL_DATA1

@
3

PCH_SMBCLK
Q9B

CL_RST1#

4

SMB_DATA_S3 [12,30,35,36]

2.2K_0402_5%
2

+3VS

SMB_CLK_S3

SMB_CLK_S3 [12,30,35,36]

2N7002KDWH_SOT363-6
R163 1
R164 1

PCH_SMBDATA
PCH_SMBCLK

PEG_A_CLKRQ# / GPIO47

DDR, WALN

P10

PCH_GPIO47

CLKOUT_PCIE0N
CLKOUT_PCIE0P

+3VS

A

2N7002KDWH_SOT363-6

M7
T11

2.2K_0402_5%
2

SMB_DATA_S3

R137
1

PERN7
PERP7
PETN7
PETP7

M10

PCH_GPIO47

R139 1

@

2 0_0402_5%

R144 1
R151 1

@
@

2 0_0402_5%
2 0_0402_5%

2 0_0402_5%
2 0_0402_5%

@
@

SMB_DATA_S3
SMB_CLK_S3

[18]

GPU_CLKREQA

+3VS

[24]

B

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

AB37
AB38

@

CLK_PCIE_VGA# [23]
CLK_PCIE_VGA [23]
PCH_SML1DATA

CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_CPU_DMI# [6]
CLK_CPU_DMI [6]

Pull up at EC side.

6

1

CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P

AM12
AM13

CLK_CPU_DP#
CLK_CPU_DP

BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

R148
R150

1
1

2
2

10K_0402_5%
10K_0402_5%

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

R152
R153

1
1

2
2

10K_0402_5%
10K_0402_5%

G24
E24

CLK_BUF_DREF_96M# R154
CLK_BUF_DREF_96M R155

1
1

2
2

10K_0402_5%
10K_0402_5%

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47
V49

XTAL25_IN
XTAL25_OUT

EC_SMB_DA2

EC_SMB_DA2 [24,30,36,38]

Q10A 2N7002KDWH_SOT363-6
@

PCIECLKRQ1# / GPIO18

CLK_CPU_DP# [6]
CLK_CPU_DP [6]

EC, VGA, Theraml

3

PCH_SML1CLK

4EC_SMB_CK2

EC_SMB_CK2 [24,30,36,38]

Q10B 2N7002KDWH_SOT363-6
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_GND1_N
CLKIN_GND1_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44

@
PCH_SMBDATA

R136
1

5

BE34
BF34
BB32
AY32

PCH_SML1CLK

2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCH_GPIO11

5

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K

SMBCLK

E12

2

C82
C83

1
1

SMBALERT# / GPIO11

SMBUS

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K

PERN1
PERP1
PETN1
PETP1

Link

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

1
1

BG34
BJ34
AV32
AU32

Controller

[35]
[35]
[35]
[35]

C86
C79

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

CLOCKS

Wireless LAN

A

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

PCI-E*

Card Reader

[37]
[37]
[37]
[37]

REFCLK14IN

R165 1
R166 1

PCH_SML1DATA
PCH_SML1CLK

2 0_0402_5%
2 0_0402_5%

@
@

EC_SMB_DA2
EC_SMB_CK2

CLK_BUF_PCIE_SATA# [13]
CLK_BUF_PCIE_SATA [13]
R158

1

2

10K_0402_5%
XTAL25_IN

P+

CLKIN_PCILOOPBACK

CLK_PCI_LPBACK

[17]

R161 1

XTAL25_OUT

2 1M_0402_5%

C

C

R184 1

@
@

2 10K_0402_5%

AB42
AB40

PCH_GPIO46
PCH_GPIO56

E6

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

LAN_CLKREQ#
PCIE_WAKE#
RI#
EC_SMI#

V40
V42

1
+1.05VS_VCCDIFFCLKN

PCIE_WAKE# [15,33]
RI# [15]
EC_SMI# [18,38]

PCH_GPIO45

V38
V37

10K_8P4R_5%
PCH_GPIO46
RP6 @
8
7
6
5

1
2
3
4

T13

PCH_GPIO45
PCH_GPIO56
PCH_GPIO44
PCH_GPIO72

T227
T226
PCH_GPIO72

1
1

CLK_XDP_CLK#
CLK_XDP_CLK

K12
AK14
AK13

XCLK_RCOMP

Y47

XCLK_RCOMP

R160 1

2 90.9_0402_1%

1

CLKOUT_PCIE6N
CLKOUT_PCIE6P

C87
15P_0402_50V8J

P-

CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

P+

CLKOUTFLEX0 / GPIO64

P-

CLKOUTFLEX1 / GPIO65

P-

CLKOUTFLEX2 / GPIO66

P-

CLKOUTFLEX3 / GPIO67

K43

PCH_GPIO64

F47

PCH_GPIO65

H47

PCH_GPIO66

K49

PCH_GPIO67

3
GND

GND

2

4

3
1

2

2

C88
15P_0402_50V8J

+3VS
PCH_GPIO67

[18]

+3VS

PANTHER-POINT_FCBGA989

[15]

1

PCIECLKRQ6# / GPIO45

FLEX CLOCKS

1
2
3
4

25MHZ 20PF +-20PPM X3G025000DK1H-X

+1.05VS

PEG_B_CLKRQ# / GPIO56

RP7
8
7
6
5

Y2

1

R181 1

R172
10K_0402_5%
@
U8

2

10K_8P4R_5%

[17,23,33,35,37,38]

PLT_RST#

PLT_RST#

1
2
3
4

NC
NC
PROT#
GND

VCC
WP
SCL
SDA

8
7
6
5

PCA24S08D_SO8
EEPROM SA00004MK00
EEPROM SA00004ML00

ROM_WP
SMB_CLK_S3
SMB_DATA_S3

1

C91
0.1U_0402_10V6K

2

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK
LA-9611P
Tuesday, February 26, 2013
Sheet
14
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

U2408C
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BE20
BG18
BG20

[5]
[5]
[5]
[5]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

[5]
[5]
[5]
[5]

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

[5]
[5]
[5]
[5]

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

A

[5]
[5]
[5]
[5]

FDI_INT

+1.05VS
BJ24
R186 1

2 49.9_0402_1% DMI_IRCOMP

BG25

R188 1

2 750_0402_1% RBIAS_CPY

BH21

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place
within 500mil of the PCH

FDI_LSYNC1

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWODVREN

FDI_INT

A

[5]

FDI_FSYNC0

[5]

FDI_FSYNC1

[5]

FDI_LSYNC0

[5]

FDI_LSYNC1

[5]
+RTCVCC

DSWVRMEN
T8
R24

[38] PCH_PWROK

PCH_PWROK

1

TPC12
2 1K_0402_5%

1

R197 1

@

2 0_0402_5%

R198 1

@

2 0_0402_5%
APWROK

[6] PM_DRAM_PWRGD

SUSACK#_R
SYS_RST#

C12
K3

SYS_PWROK

P12

PCH_POK_R

L22

PM_DRAM_PWRGD

B13

L10

C21

[38] EC_RSMRST#
SUSWARN#

K16
E20

[38] PBTN_OUT#
1

D3

[38,42] ACIN

2
AC_PRESENT_R
RB751V-40_SOD323-2

[14] PCH_GPIO72
[14] RI#

H20

PCH_GPIO72

E10

RI#

A10

SUSACK#

System Power Management

+3VS
B

DSWODVREN

P+

SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

SLP_S3#

P+

SLP_A#

ACPRESENT / GPIO31

P-

SLP_SUS#

BATLOW# / GPIO72 P+

PMSYNCH

RI#

SLP_LAN# / GPIO29

E22

EC_RSMRST#

B9

PCIE_WAKE#

N3

PCIE_WAKE#

PM_CLKRUN#

PM_CLKRUN#

[14,33]

*

R185

1

R187

1

2 330K_0402_5%
@

2 330K_0402_5%
B

DSWODVREN - On Die DSW VR Enable
H烉Enable
L烉Disable

[18]

G8
N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

PCH_SLPA#

G16

PM_SLP_SUS#

AP14

H_PM_SYNC

K14

PCH_GPIO29

+3V_PCH

SUSCLK [38]
1

T11
PM_SLP_S5# [38]

1

T12
PM_SLP_S4# [38]

1

T13
PM_SLP_S3# [38]

1

T16

1

T14

1

T15
H_PM_SYNC

PCH_GPIO29

R195

1

@

2 10K_0402_5%

PM_CLKRUN#

R199

1

@

2 10K_0402_5%

EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)
Use CLKRUN# Requires a 8.2- k weak
pull-up resistor to Vcc3_3S
[6]

Can be left NC when
IAMT is not support on
the platfrom

PANTHER-POINT_FCBGA989
C

C

+3VS
PM_DRAM_PWRGD

+3VS

2 200_0402_5%

PM_DRAM_PWRGD

R205 1

2 10K_0402_5%

SUSWARN#

R206 1

2 200K_0402_5%

AC_PRESENT_R

@

[48] VGATE

1
2

IN1
IN2

R210 1

2 10K_0402_5%

4

SYS_PWROK

R211
100K_0402_5%
2

MC74VHC1G08DFT2G_SC70-5

OUT

1

PCH_PWROK
R305 1

5

U9

+3V_PCH

VCC

2 200_0402_5%

GND

@

3

R204 1

EC_RSMRST#

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,
LA-9611P
Sheet
Tuesday, February 26, 2013
15
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

A

A

U2408D

1 100K_0402_5%

ENBKL

P45

[30] PCH_PWM

T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
B

AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43

N48
P49
T49
T39
M40

L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA

P-

PP-

SDVO_TVCLKINN
SDVO_TVCLKINP

PP-

SDVO_STALLN
SDVO_STALLP

PP-

SDVO_INTN
SDVO_INTP

LVD_IBG
LVD_VBG

SDVO_CTRLCLK
P- SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
P- DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
P- DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD

C

M47
M49

2

CRT_IREF
R223
1K_0402_5%

T43
T42

AP43
AP45
AM42
AM40
AP39
AP40

L_CTRL_CLK
L_CTRL_DATA

Digital Display Interface

2

LVDS

R253

CRT

J47
M45

[38] ENBKL
[30] PCH_ENVDD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

P38
M39

HDMICLK_NB
HDMIDAT_NB

HDMICLK_NB
HDMIDAT_NB

AT49
AT47
AT40

PCH_DPB_HPD

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

[37]
+3VS

HDMI

[37]
[37]
[37]
[37]
[37]
[37]
[37]
[37]

B

PCH_DPC_CLK
PCH_DPC_DAT

AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

[37]
[37]

HDMICLK_NB
HDMIDAT_NB

2.2K_0402_1%
2.2K_0402_1%

2
2

PCH_DPC_CLK
PCH_DPC_DAT

2.2K_0402_5%
2.2K_0402_5%

2
2

1 R2148
1 R2143

@

1 R2146
1 R2145

PCH_DPC_AUXN [31]
PCH_DPC_AUXP [31]
PCH_DPC_HPD [31]

PCH_DPC_N2
PCH_DPC_P2
PCH_DPC_N3
PCH_DPC_P3

1
1
1
1

PCH_DPC_N0
PCH_DPC_P0
PCH_DPC_N1
PCH_DPC_P1

DP

[31]
[31]
[31]
[31]

T222
T223
T224
T225

M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

1

PANTHER-POINT_FCBGA989

ŝŐŝƚĂůŝƐƉůĂǇWŽƌƚƐŶĂďůĞĂŶĚŝƐĂďůĞ'ƵŝĚĞůŝŶĞƐ
WŽƌƚ

^ƚƌĂƉ

,ŽǁƚŽŶĂďůĞ͍

,ŽǁƚŽŝƐĂďůĞ͍

>s^

>ͺͺd

WƵůůͲŚŝŐŚƚŽϯ͘ϯsǁŝƚŚϮ͘ϮŬͺϱйKŚŵ

EŽŽŶŶĞĐƚ

WŽƌƚ

^sKͺdZ>d

WƵůůͲŚŝŐŚƚŽϯ͘ϯsǁŝƚŚϮ͘ϮŬͺϱйKŚŵ

EŽŽŶŶĞĐƚ

WŽƌƚ

WͺdZ>d

WƵůůͲŚŝŐŚƚŽϯ͘ϯsǁŝƚŚϮ͘ϮŬͺϱйKŚŵ

EŽŽŶŶĞĐƚ

WŽƌƚ

WͺdZ>d

WƵůůͲŚŝŐŚƚŽϯ͘ϯsǁŝƚŚϮ͘ϮŬͺϱйKŚŵ

EŽŽŶŶĞĐƚ

C

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
LA-9611P
Tuesday, February 26, 2013
Sheet
16
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

U2408E

1
2
3
4
5

PCH_GPIO4
PCH_GPIO5
PCH_GPIO2
PCH_GPIO3

10
9
8
7
6

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQA#

10K_1206_10P8R_5%

+3VS

R239 1

PCH_GPIO51

R240 1

@

2 10K_0402_5%

PCH_GPIO53

R235 1

@

2 10K_0402_5%

PCH_GPIO55

2 10K_0402_5%

PCH_GPIO50

2 10K_0402_5%

PCH_GPIO52

2 10K_0402_5%

PCH_GPIO54

R231 1
B

2 10K_0402_5%

R236 1

@

R246 1

R244 1

@

2 10K_0402_5%

PCH_GPIO54

R232 1

@

2 10K_0402_5%

PCH_GPIO50

R234 1

@

2 10K_0402_5%

PCH_PLTRST#

2 10K_0402_5%

PCH_GPIO52

2 1K_0402_5%

PCH_GPIO51

R190 1
R243 1

@

B21
M20
AY16
BG46

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

[37] USB3_RX0_N
[35] USB3_RX1_N
[31] USB3_RX2_N
[37] USB3_RX0_P
[35] USB3_RX1_P
[31] USB3_RX2_P
[37] USB3_TX0_N
[35] USB3_TX1_N
[31] USB3_TX2_N
[37] USB3_TX0_P
[35] USB3_TX1_P
[31] USB3_TX2_P

'W/KϱϬͬϱϮͬϱϰĚĞĨĂƵůƚсEĂƚŝǀĞ
DIS@

[23] DGPU_HOLD_RST#
[30] TS_ON
[25,47,51] DGPU_PWR_EN

DIS@

R254 1
R337 1
R264 1

@
@
@

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

Boot BIOS Strap bit1 BBS1
GPIO51 GPIO19
Bit11 Bit10

C

R245 1

@

Boot BIOS
Destination
[35] BT_DET#

0

1

Reserved

1

0

PCI

1

1

SPI (Default)

0

0

*

2 1K_0402_5%

LPC

PCH_GPIO55

[34] MSATS_DEVSLP

R332 1

@

2 0_0402_5%

R296 1

@

2 0_0402_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

K40
K38
H38
G38

PCH_GPIO50
PCH_GPIO52
PCH_GPIO54

C46
C44
E40

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44
K10

[38] PCI_PME#
PCH_PLTRST#

[6] PCH_PLTRST#
[14]
[38]
[37]
[37]

CLK_PCI_LPBACK
CLK_PCI_EC
CLK_PCI_DB
CLK_PCI_TPM

CLK_PCI_EC
TPM@

R248
R249
R250
R350

1
1
1
1

2
2
2
2

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3

H49
H43
J48
K42
H40

TP21
TP22
TP23
TP24

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

PPIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

P+
P+
P+

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#

USBRBIAS#
USBRBIAS

P+

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PPPPP-

AY7
AV7
AU3
BG4
A

AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

C33

USBRBIAS

B

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N8
USB20_P8
1
1
USB20_N10
USB20_P10
USB20_N11
USB20_P11

[37]
[37]
[35]
[35]
[31]
[31]
[30]
[30]

h^ϯ͘Ϭ;/ͬKŽĂƌĚͿ
h^ϯ͘Ϭ;DͿ
h^ϯ͘Ϭ;ŽĐŬŝŶŐͿ
DK^ĂŵĞƌĂ;>s^Ϳ

USB20_N8 [30]
USB20_P8 [30]

dŽƵĐŚƉĂŶĞů

USB20_N10 [35]
USB20_P10 [35]
USB20_N11 [37]
USB20_P11 [37]

DŝŶŝĂƌĚ;t>EͬdͿ

T26
T28

;dĞƐƚWŽŝŶƚĨŽƌ/K^ĞďƵŐͿ
&ŝŶŐĞƌWƌŝŶƚ

OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2

Within 500 mils
R247 1

2

22.6_0402_1%

+3V_PCH

B33
A14
K20
B17
C16
L16
A16
D14
C14

R233
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#

1
2
3
4

USB_OC1#
USB_OC0#
USB_OC2#
USB_OC3#

USB_OC0# [35,37]

KϬηh^ϯ͘Ϭ;/ͬKŽĂƌĚͿ;DͿ

8
7
6
5

C

10K_8P4R_5%
USB_OC4#

R180 2

1 10K_0402_5%

PANTHER-POINT_FCBGA989

A16 swap overide Strap/Top-Block
Swap Override jumper
PCI_GNT3#

C6

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

USB

+3VS

RP8
+3VS

'EdϬη͕'Edϭηͬ'W/Kϱϭ͕'EdϮηͬ'W/Kϱϯ͕'Edϯηͬ'W/Kϱϱ
W/'ƌĂŶƚƐ͗dŚĞW,ƐƵƉƉŽƌƚƐƵƉƚŽϰŵĂƐƚĞƌƐŽŶƚŚĞW/
ďƵƐ͘
'Ed΀ϯ͗ϭ΁ηƉŝŶƐĐĂŶŝŶƐƚĞĂĚďĞƵƐĞĚĂƐ'W/K͘
WƵůůͲƵƉƌĞƐŝƐƚŽƌƐĂƌĞŶŽƚƌĞƋƵŝƌĞĚŽŶƚŚĞƐĞƐŝŐŶĂůƐ͘/ĨƉƵůůͲ
ƵƉƐĂƌĞƵƐĞĚ͕ƚŚĞǇƐŚŽƵůĚďĞƚŝĞĚƚŽƚŚĞsĐĐϯͺϯƉŽǁĞƌƌĂŝů͘
EKd^͗
ϭ͘'Ed΀ϯ͗ϭ΁ηͬ'W/K΀ϱϱ͕ϱϯ͕ϱϭ΁ĂƌĞƐĂŵƉůĞĚĂƐĂ
ĨƵŶĐƚŝŽŶĂůƐƚƌĂƉ͘^ĞĞ^ĞĐƚŝŽŶϮ͘ϮϳĨŽƌĚĞƚĂŝůƐ͘

RSVD5
RSVD6

RSVD

A

RSVD1
RSVD2
RSVD3
RSVD4

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default *

R251 1

2 0_0402_5%

@

U11
Y

A

4

PLT_RST# [14,23,33,35,37,38]
R255
100K_0402_5%
2

@
TC7SH08FUF_SSOP5

1

B

G

2

3

1

PCH_PLTRST#

P

5

+3VS

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PCH (5/9) PCI, USB, NVRAM
LA-9611P
Sheet
Wednesday, February 27, 2013
17
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

*

H烉On-Die voltage regulator enable
L烉On-Die PLL Voltage Regulator disable
R265

1

@

2 1K_0402_5%

PCH_GPIO28

R274

1

@

2 1K_0402_5%

EC_SMI#

+3VS

U2408F

[30] TS_INT#
[31] DOCK_PRSNT#
[38] EC_SCI#
[14,38] EC_SMI#

+3VS

R178 1

[38] EC_WAKE#
@

2 10K_0402_5%
2 10K_0402_5%

WLBT_OFF_51#

@

2 0_0402_5%

TS_INT#

A42

DOCK_PRSNT#

H36

EC_SCI#

E38

EC_SMI#

C10

PCH_GPIO12

C4

PCH_GPIO15

G2

PCH_GPIO16

U2

BMBUSY# / GPIO0

P+ TACH4 / GPIO68

C40

TS_PRSNC#

TACH1 / GPIO1

P+

P+ TACH5 / GPIO69

B41

PCH_GPIO69

TACH2 / GPIO6

P+

P+ TACH6 / GPIO70

C41

PCH_GPIO70

P+ TACH7 / GPIO71

A40

TACH3 / GPIO7
GPIO8

P+

GPIO15

A20GATE

P-PECI
SATA4GP / GPIO16

[13] PCH_GPIO22
PCH_GPIO24

+3VS
R285 1
R284 1
+3V_PCH

+3VS

@

2 10K_0402_5%
2 10K_0402_5%

B

[35] WLBT_OFF_51#
8
7
6
5

E8

PCH_GPIO27

E16

PCH_GPIO28

P8

PCH_GPIO34

K1

PCH_GPIO35

K4

WLBT_OFF_51#

V8

PCH_GPIO37

M5

PCH_GPIO37

RP4
1
2
3
4

PCH_GPIO24

PCH_GPIO0
PM_CLKRUN#
PCH_GPIO28
PCH_GPIO47

PM_CLKRUN#
PCH_GPIO47

[15]
[14]

PCH_GPIO38

N2

PCH_GPIO39

M3

PCH_GPIO48

V13

PCH_GPIO49

V3

10K_8P4R_5%
+3VS
[13] PCH_GPIO49

D6

PCH_GPIO57
R266 1

@

2 10K_0402_5%

DOCK_PRSNT#

R344 1

@

2 10K_0402_5%

EC_SCI#

R275 1

2 10K_0402_5%

R268 1

2 10K_0402_5%

DGPU_PWROK

2 10K_0402_5%

PCH_GPIO34

R283 1

@

2 10K_0402_5%

PCH_GPIO35

R287 1

@

2 10K_0402_5%

PCH_GPIO39

2 10K_0402_5%

T22

1

A4

T24

1

A44

PCH_GPIO16

@

@

T26

A45

T28

A46

T30

1

A5

T32

1

A6

T34

1

B3

PCH_GPIO48

+3V_PCH

B47

T36
R293 1

2 100K_0402_5%

PCH_GPIO27

R271 1

2 10K_0402_5%

PCH_GPIO12

R273 1

2 1K_0402_5%

T38

1

BD1

T40

1

BD49

T42

1

BE1

T44

1

BE49

T46

1

BF1

T48

1

BF49

PCH_GPIO15

C

R292 1

@

2 10K_0402_5%

GPIO24
GPIO27

P+

GPIO28

P+

PROCPWRGD

PCH_GPIO57

A

PCH_GPIO71

THRMTRIP#

4
3
2
1

PCH_PECI_R

P5

KB_RST#

AY11

H_CPUPWRGD

AY10

P-

AY1

DF_TVS
TS_VSS1
TS_VSS2

GPIO35
TS_VSS3

SATA2GP / GPIO36

P-

TS_VSS4

SATA3GP / GPIO37

P-

NC_1

GATEA20 [13,38]

AU16

T14

STP_PCI# / GPIO34

SLOAD / GPIO38

P4

P+INIT3_3V#

R267 1

@

2 0_0402_5%

H_PECI [38,6]
KB_RST# [13,38]
H_CPUPWRGD

R278 1

2 390_0402_5% H_THRMTRIP#

H_THRMTRIP#

[6]
[6]

INIT3_3V
DF_TVS

This signal has weak internal
PU, can't pull low

AH8
AK11

+1.8VS

AH10
AK10

Intel schematic reviwe recommand.

R226
2.2K_0402_5%

P37

SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

GPIO57

VSS_NCTF_17
VSS_NCTF_18

R346 1

R289 1

SCLOCK / GPIO22

2 10K_0402_5%
RP10

5
6
7
8

B

2

2 10K_0402_5%
2 10K_0402_5%

TACH0 / GPIO17

CPU/MISC

@

T5

R256 1

PCH_GPIO71
PCH_GPIO70
PCH_GPIO69
TS_INT#

10K_8P4R_5%

P-

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

NCTF

R288 1
R290 1

PCH_GPIO22

TS_PRSNC#

LAN_PHY_PWR_CTRL / GPIO12

GPIO

[38,47] DGPU_PWROK

+3V_PCH

D40

[30]

P+

RCIN#
DGPU_PWROK

TS_PRSNC#

1

A

R280 1
R282 1

T7

PCH_GPIO0

VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6

VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2

1

BG48

1

DF_TVS

T18
T19

BH3

1

T20

BH47

1

T21

BJ4

1

T23

BJ44

1

T25

BJ45

1

BJ46

1

T29

BJ5

1

T31

BJ6

1

T33

C2

1

T35

1

T39

1

T43

R229 1

2 1K_0402_5%

H_SNB_IVB#

[6]

DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
CLOSE TO THE BRANCHING POINT

T27

C48
D1
D49
E1
E49
C

F1

1

T47

F49

PANTHER-POINT_FCBGA989

PCH_GPIO69

PCH_GPIO38

PCH_GPIO67

0

0

0

Optimus

0

0

1

Reserved

0

1

0

DIS

0

1

1

UMA

Function

R311
10K_0402_5%
UMA@

PCH_GPIO67

[14]

(MB_ID_2)
(MB_ID_1)
(MB_ID_0)

1

1

PCH_GPIO69
PCH_GPIO38
PCH_GPIO67
Connect to RP10

D

2

2

R330
10K_0402_5%
UMA@
2

R259
10K_0402_5%
@

D

1

1

1

+3VS

R286
10K_0402_5%
DIS@

Compal Secret Data

Security Classification
Issued Date

2

2

R329
10K_0402_5%
DIS@

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC
LA-9611P
Tuesday, February 26, 2013
Sheet
18
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

+3VS
+VCCADAC

A

A

AN16
AN17

AP21
AP23
AP24
AP26
AT24

+3VS
AN33
AN34
1

2

C112
0.1U_0402_10V6K

BH29

1
@ C114
1U_0402_6.3V6K

2

+1.05VS

BG6
AP17
AU20

1
R216
0_0402_5%
@

VCC3_3[6]

V33
1

VCC3_3[7]

V34

B

C104
0.1U_0402_10V6K

2

ϭϰϳŵ VCCVRM[3]

AT16

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP

ϰϳŵ

AT20

+1.05VS

VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCDMI[1]

+1.05VS

ϳϱŵ VCCCLKDMI

AB36

2

1

2

1
C110
1U_0402_6.3V6K

C111
1U_0402_6.3V6K

VCCIO[25]

Ϯŵ

VCCIO[26]
VCC3_3[3]

VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]

VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]

+1.8VS

AG16
AG17
AJ16

C163
0.1U_0402_10V6K

1

1

2

2

@
C113
1U_0402_6.3V6K

AJ17
C

+3VS

ϭϬŵ VCCSPI

FDI

+1.05VS_VCCAPLL_FDI

R215
0_0402_5%
@

AP37

+1.5VS

VCCIO[19]

Place C167 Near BG6 pin
C

AP36

VCCIO[18]

+1.5VS
AP16

AM38

2

VCCIO[17]

DMI

2

Disable LVDS VCCTX_LVDS and VCCA_LVD
can be connected to ground(DG 471984 P196)
+VCCTX_LVDS

2

LVDS

ϯ͘ϳϵϵ

VCCIO[16]

DFT / SPI

1

1U_0402_6.3V6K

2

C109

1

1U_0402_6.3V6K

2

C108

1

1U_0402_6.3V6K

C107

2

1U_0402_6.3V6K

C106

10U_0603_6.3V6M

C105

1

AN27

AM37

+3VS

VCCIO

AN26

VCCALVDS

AK37

VCCAPLLEXP

+1.05VS
AN21

AK36

VCCIO[28]

VCCIO[15]

2

U47

1

CRT

VCC CORE

VCCTX_LVDS[4]

HVCMOS

TPC12
This pin can be left
as no connect in
On-Die VR enabled mode (default).

2

VCCTX_LVDS[2]

@

1

10U_0603_6.3V6M

BJ22

1+VCCAPLLEXP

T50

1

ϰϬŵ VCCTX_LVDS[1]

VCCTX_LVDS[3]
AN19

B

VSSALVDS

2

C160

+1.05VS

ϭŵ VCCALVDS

@

1

10U_0603_6.3V6M

2

VSSADAC

2

C100

1

1U_0402_6.3V6K

2

C98

1

1U_0402_6.3V6K

2

C97

1

1U_0402_6.3V6K

C96

2

10U_0603_6.3V6M

C95

1

2

U48

1

0.1U_0402_10V6K

@

ϲϯŵ VCCADAC

VCCCORE[1] ϭ͘ϳϯ
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

C99

POWER

U2408G
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

1U_0402_16V7K

C94

+1.05VS

1

V1
1

C115
1U_0402_6.3V6K

2

PANTHER-POINT_FCBGA989

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Compal Electronics, Inc.
PCH (7/9) PWR
LA-9611P
Date:
Tuesday, February 26, 2013
Sheet
19
of
53
Title

Size Document Number
Custom

5

Rev
0.4

1

2

3

4

5

VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
+1.05VS

Have internal VRM
2 0_0603_5%

+VCCACLK

VCCIO[30]

ϭŵ

VCCDSW3_3

VCCIO[31]

+3VS
C121

1

2

1

2

+PCH_VCCDSW

V12

DCPSUSBYP

VCCIO[32]

0.1U_0402_10V6K
T38
C123

@

2

1

BH23
10U_0603_6.3V6M
AL29
нsW>>ͺWz
C124

@

1

VCCIO[33]

2

+VCCSUS1

AL24

ϭϭϵŵ

VCCAPLLDMI2

VCCSUS3_3[7]
VCCSUS3_3[8]

VCCIO[14]
DCPSUS[3]

VCCSUS3_3[9]
VCCSUS3_3[10]

1U_0402_6.3V6K

VCCSUS3_3[6]

AA24

+1.05VS

AA26
AA27

2

AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24

+1.05VS
W26
W29
L4
1
2
10UH_LB2012T100MR_20%

W31

+1.05VS_VCCA_A_DPL
C136

220U_B2_2.5VM_R35

W33

C137

1
1

+

C143 1

1U_0402_6.3V6K

2

2

1

VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]

V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]

ϭŵ V5REF

+1.05VS_VCCA_A_DPL
C144
1U_0402_6.3V6K

BD47
BF47
AF17
AF33
AF34
AG34

C146
1U_0402_6.3V6K

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]

ϭϳϴŵ VCC3_3[8]
VCC3_3[4]

AG33

+1.05VS

V16

+3V_PCH

T29
1
T23

C122
0.1U_0402_10V6K

2

T24
V23

1

V24
P24

+3V_PCH

C125
0.1U_0402_10V6K
+1.05VS

2

T26
M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

+3V_PCH

1

2

+PCH_V5REF_SUS
C132
@
1U_0402_6.3V6K

+3V_PCH

R315
10_0402_5%

1

C126
0.1U_0402_10V6K

2
1

P34

2

+PCH_V5REF_RUN

C133
0.1U_0402_10V6K

B

N20

+5VS

+3V_PCH
1

N22
P20

C134
1U_0402_6.3V6K

2

D5
RB751V-40_SOD323-2

+3VS

P22
+PCH_V5REF_RUN
AA16
1

W16
T34

C135
1U_0402_6.3V6K
C140
0.1U_0402_10V6K

R318
10_0402_5%

1

2

2

VCCASW[18]
VCCASW[19]

VCC3_3[2]

VCCASW[20]
DCPRTC
VCCVRM[4]

VCCADPLLA
VCCADPLLB

VCCIO[13]

ϳϱŵ
ϳϱŵ

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCIO[6]
VCCAPLLSATA
VCCVRM[1]

VCCSSC

1

AJ2

C142
0.1U_0402_10V6K

2

AF13

+1.05VS

AH13
AH14

Place C199 Near AK1 pin
+VCCSATAPLL

AF14
AK1

1

2

C147
10U_0603_6.3V6M
@

+1.05VS_SATA3

1

C145
1U_0402_6.3V6K

2
C

+1.5VS

AF11
+1.05VS

ϱϱŵ

VCCIO[2]

ϵϱŵ

VCCIO[4]

AC16
AC17

+1.05VS_VCC_SATA
1

AD17

C148
1U_0402_6.3V6K

2
DCPSST
+1.05VS

+VCCSST

DCPSUS[1]
DCPSUS[2]

VCCASW[22]

2
C150
0.1U_0402_10V6K

1

BJ8

1
C151
1U_0402_6.3V6K
2
@

+1.05VS

A22

V_PROC_IO Ϯŵ

VCCRTC

CPU

+1.05VM_VCCSUS

2

PANTHER-POINT_FCBGA989

1

2

0.1U_0402_10V6K

2

C153

D

VCCASW[23]
VCCASW[21]

ϭϬŵ

VCCSUSHDA

T21
V21
+3V_PCH
T19

P32
1

C158
0.1U_0402_10V6K

2
D

+RTCVCC

1

2

0.1U_0402_10V6K

2

C157

1

1U_0402_6.3V6K

C155

4.7U_0603_6.3V6K

C152

1

MISC

C149
1U_0402_6.3V6K

T17
V19

HDA

+1.05VS_SSCVCC

RTC

2 0_0402_5%
1

ŶƐƵƌĞŝŶĚĞƉĞŶĚĞŶƚƉŽǁĞƌ
ƌŽƵƚŝŶŐĨŽƌ^^ĂŶĚ/&&>ŽŽŬƵƉ>ĂďůĞ

A

NC#AH3
NC#AH1
NC#AK3
NC#AK1

DVO

NC#AK5
NC#AM3
NC#AK6
NC#AM5

DPB

NC#AJ7
NC#AH6
NC#AK8
NC#AL7

W6
V6
AC6
AC5
+3VS_VGA

AA5
AA6

NC#W6
NC#V6
NC#V4
NC#U5

NC#AC5
NC#AC6
NC#AA5
NC#AA6

NC#W3
NC#V2

DPC

2

2

2
G

U1
W1
U3
Y6
AA1

DIS@
R328
10K_0402_5%

1

VGA_SMB_DA2_R

R301 1

2 0_0402_5%

@

ϬϭϬ

ϰ͘ϵϵŬ

Ϭϭϭ

ϰ͘ϱϯŬ

ϰ͘ϵϵŬ

ϭϬϬ

ϯ͘ϮϰŬ

ϱ͘ϲϮŬ

ϭϬϭ

ϯ͘ϰŬ

ϭϬŬ

ϭϭϬ

ϰ͘ϳϱŬ

E

ϭϭϭ

ĂƉ;Ŷ&Ϳ
ϱϮϬϲ
V4
U5
W3
V2
Y4
W5

ŝƚĚ΀ϱ͗ϰ΁

ϴϮŶ&

Ϭϭ

^ϬϳϲϴϮϯ<ϴϬ

ϭϬŶ&

ϭϬ

^ϬϳϰϭϬϯW^
+1.8VS_VGA

7

1
1

W^ͺϮ΀ϭ΁Eͬ

1

AM26
AK26

DĞŵŽƌǇ/
PS_0

DDC/AUX

T219
T220

^ƚƌĂƉEĂŵĞ͗

C

SWAPLOCKA
SWAPLOCKB
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE
NC#AJ9
NC#AL9

DDC2CLK
DDC2DATA

1

W^ͺϭ΀ϱ΁^dZWͺdyͺDW,ͺE

2

R
AVSSN#AK26

PLL/CLOCK

AM28
AK28

W^ͺϭ΀ϰ΁^dZWͺdyͺ&'ͺZsͺ&h>>ͺ^t/E'
DIS@
R5168
4.75K_0402_1%

+1.8VS_VGA

PS_2

0.1U_0402_10V6K

XTALIN
XTALOUT

W^ͺϭ΀ϯ΁Eͬ

2

SCL
SDA

AUX1P
AUX1N

VGA_DPLUS

2

W^ͺϮ΀ϯ͗ϭ΁сϬϬϬ

+1.8VS_VGA

NC

1

1

L6
L5
L3
L1
K4
K7
AF24
AB13
W8
W9
W7
AD10
AJ9
AL9

Y6

4

1

1

VGA_AC__BATT

W^ͺϭ΀Ϯ΁dZWͺ/&ͺ><ͺWDͺE

2

2 10K_0402_5%

W^ͺϭ΀ϭ΁^dZWͺ/&ͺ'EϯͺEͺ

1

ϬϵϮϰ

^ƚƌĂƉEĂŵĞ͗

2

2

A

J8

C437

1

U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
AK10
AM10
N7

W^ͺϬ΀ϱ΁hͺWKZdͺKEEͺW/E^dZW΀Ϭ΁

AA3
Y2

C413

VGA_SMB_DA2
VGA_SMB_CK2
VGA_AC__BATT

W^ͺϬ΀ϰ΁Eͬ

@
R5167
8.45K_0402_1%
PS_1

^ϬϬϬϬϬz:ϴϬ

W^ͺϬ΀ϯ΁ZKDͺKE&/'΀Ϯ΁

DIS@
R5166
2K_0402_1%

ŽŵƉĂůWE

ϬϬ

W^ͺϬ΀Ϯ΁ZKDͺKE&/'΀ϭ΁

+1.8VS_VGA

W^ͺϭ΀ϱ͗ϰ΁сϭϭ

1U_0402_6.3V4Z
@

VGA_SMB_CK2

D2416

@

2

W^ͺϭ΀ϯ͗ϭ΁сϬϬϭ

ϲϴϬŶ&

C436

2 0_0402_5%

@

RB751V-40_SOD323-2

R1456 1

1

@
C5208
0.68U_0402_X6S

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AK8
AL7

1

PS_0

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AJ7
AH6

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@
R5175
4.75K_0402_1%

D

R304 1

[38,47] VGA_AC_DET

@
C2506
0.1U_0402_10V6K

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ϲ͘ϵϴŬ

1U_0402_6.3V4Z
@

VGA_SMB_CK2_R

+3VS_VGA

D

ϰ͘ϱϯŬ

10U_0603_6.3V6M
@

G

4

Q2416B
DIS@

+3VS_VGA

ϬϬϭ

I2C

S

3

EC_SMB_CK2

[14,30,36,38] EC_SMB_CK2

DIS@
C341
10P_0402_50V8J

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W^ͺϮ΀ϱ͗ϰ΁сϬϬ

R1
R3

2

NC#J8

AK6
AM5

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DIS@
R5165
8.45K_0402_1%

VGA_SMB_DA2

B

XTALIN

NC#AA3
NC#Y2

AK5
AM3

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5

Q2416A
DIS@

R1439

NC#U1
NC#W1
NC#U3
NC#Y6
NC#AA1

AK3
AK1

ϰ͘ϳϱŬ

D

S

6

EC_SMB_DA2

[14,30,36,38] EC_SMB_DA2

1

1

NC#Y4
NC#W5
DIS@
R327
10K_0402_5%

AH3
AH1

E

W^ͺϬ΀ϱ͗ϰ΁сϭϭ

2

NC#AG3
NC#AG5

DPA

+1.8VS_VGA

W^ͺϬ΀ϯ͗ϭ΁сϬϬϭ
ŝƚĚ΀ϯ͗ϭ΁

1

DBG_DATA16
DBG_DATA15
DBG_DATA14
DBG_DATA13
DBG_DATA12
DBG_DATA11
DBG_DATA10
DBG_DATA9
DBG_DATA8
DBG_DATA7
DBG_DATA6
DBG_DATA5
DBG_DATA4
DBG_DATA3
DBG_DATA2
DBG_DATA1
DBG_DATA0

AF2
AF4
AG3
AG5

ZͺƉĚ;ŽŚŵͿ
Zϱϭϲϵ

1

T201
T202
T203
T204
T205
T206
T207
T208
T209
T210
T211
T212
T213
T214
T215
T216
T217

N9
L9
AE9
Y11
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

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Zϱϭϳϰ

2

U?

NC#AF2
NC#AF4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

5

1

DIS@
U666B

4

2

3

2

2

1

1

3

4

LA-9611P
Sheet

Wednesday, February 27, 2013
5

Rev
0.4
24

of

53

1

2

нϯs^dKнϯs^ͺs'

+5VALW

3

+3VS

4

5

+3VS_VGA
J1401 @
1

1

2

2

1

1

2

0.1U_0402_10V6K

1

2

DIS@

DIS@

3

1

C1632

D

A

1

2

A

S

R297
470K_0402_1%
DIS@

10U_0603_6.3V6M

C1514

JUMP_43X79
Q1405
DIS@
AO3413_SOT23-3

@

2 0_0402_5%

@

2 0_0402_5%

1

R1477 1
R1478 1
DIS@

2

10K_0402_5%

12

SUSP#

D
2
G

2

3

1

D

R1479 @
1
2 DGPU_PWR_EN#
10K_0402_5%

2
Q1407
2N7002K_SOT23-3 S
@

G

2

@

1

2

0.1U_0402_10V6K

DIS@

R1480
@
100K_0402_5%

1

C1521

S

Q1406
2N7002K_SOT23-3
DIS@

0.1U_0402_10V6K

DGPU_PWR_EN

C1515

[17,47,51]

R1533
470_0603_5%
@

2

3

[10,38,39,44,46,47]

G

R1475
DIS@
DGPU_PWR_EN# 1

DIS@
U666E

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EŽhƐĞ'WhŝƐƉůĂǇWŽƌƚŽƵƚƉƵĚ
ϭϴϴŵ;ŝƐƉůĂǇWŽƌƚͿ DIS@

+1.8VS_VGA
@

2

+1.8VS_VGA
+1.8VS

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

10
9
8

2

1

2

1

2

+0.95VS_VGA

ϮϴϬŵ

@
R320 1

2 0_0603_5%+DP_VDDC

1.5VSVGA

C450

1
2

ON2

@

DIS@

6
7

1

11

0.1U_0402_10V6K

5
+1.5V

1

2

J509
2

2

1

1

DIS@

2

1

2

0.1U_0402_10V6K

1

C1628

DIS@

DIS@

2

10U_0603_6.3V6M

1

C1523

@ JUMP_43X79

10U_0603_6.3V6M

DIS@

1

1

+1.5VS_VGA

15

TPS22966DPUR_SON14_2X3

C1516

0.1U_0402_10V6K

2

C1524
DIS@

GND

1

12

DIS@

1

VBIAS

2

@ JUMP_43X79

C1633

4

CT1

2

10U_0603_6.3V6M

+5VS
R143
0_0402_5%
@

ON1

1.8VSVGA

C1520

3

2 110K_0402_1%

14
13

10U_0603_6.3V6M

R1482 1

VOUT1
VOUT1

C1522

DGPU_PWR_EN

J508

VIN1
VIN1

1U_0402_6.3V4Z
@

1
2

DIS@

U666G

U?
NC/DP POWER

DP POWER

1

2

C451

U2302

110K

C447

1

1U_0402_6.3V4Z
@

C446

2 0_0603_5%
+DP_VDDR

0.1U_0402_10V6K
@

R319 1

0.1U_0402_10V6K
@

B

нϭ͘ϴs^dKнϭ͘ϴs^ͺs'
нϭ͘ϱsdKнϭ͘ϱs^ͺs'

2

AG15
AG16
AF16
AG17
AG18
AG19
AF14

AG20
AG21
AF22
AG22
AD14

AG14
AH14
AM14
AM16
AM18
AF23
AG23
AM20
AM22
AM24
AF19
AF20
AE14

C

AF17

DP_VDDR#AG15
DP_VDDR#AG16
DP_VDDR#AF16
DP_VDDR#AG17
DP_VDDR#AG18
DP_VDDR#AG19
DP_VDDR#AF14

NC#AE11
NC#AF11
NC#AE13
NC#AF13
NC#AG8
NC#AG10

DP_VDDC#AG20
DP_VDDC#AG21
DP_VDDC#AF22
DP_VDDC#AG22
DP_VDDC#AD14

NC#AF6
NC#AF7
NC#AF8
NC#AF9

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

NC#AE1
NC#AE3
NC#AG1
NC#AG6
NC#AH5
NC#AF10
NC#AG9
NC#AH8
NC#AM6
NC#AM8
NC#AG7
NC#AG11

DPAB_CALR

NC#AE10

AE11
AF11
AE13
AF13
AG8
AG10

AF6
AF7
AF8
AF9

AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11

AE10

216-0842024-A11-MAR_FCBGA631
?

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

M6
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11
AA11
M12
N11
V11

U?

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

VSS_MECH
VSS_MECH
VSS_MECH

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

B

C

A32
AM1
AM32

216-0842024-A11-MAR_FCBGA631
?

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
MARS_Power/GND
LA-9611P
Tuesday, February 26, 2013
Sheet
25
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

Ϭ

Ϭ

Ϭ

sZϯ

Ϯϱŵ

ϭƵ&

Ϭ͘ϭƵ&

Ϭ

Ϯ;ϭΛͿ

ϭ

C394

1U_0402_6.3V4Z
DIS@

0.1U_0402_10V6K
DIS@

C387

2

1

1

2

L8
+1.8VS_VGA
L52 DIS@
1
2
BLM15BD121SN1D_0402

ϳϱŵ
1

2

2

+0.95VS_VGA
L53 DIS@
1
2
BLM15BD121SN1D_0402

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

SPLL_PVDD

ϭϬϬŵ
1

2

1

2

+SPLL_VDDC

H8

1

J7

2

C388

2

1

2

1

2

C449

1

1

2

1

1U_0402_6.3V4Z
@

2

C420

1

1U_0402_6.3V4Z
@

2

C419

1

1U_0402_6.3V4Z
DIS@

2

C418

1

1U_0402_6.3V4Z
DIS@

2

C417

1

1U_0402_6.3V4Z
DIS@

2

C416

1

1U_0402_6.3V4Z
DIS@

2

C415

1

1U_0402_6.3V4Z
DIS@

2

C432

1

1U_0402_6.3V4Z
DIS@

2

C431

1

1U_0402_6.3V4Z
DIS@

2

1U_0402_6.3V4Z
DIS@

1

C448

+VGA_CORE

R21
U21

2

+0.95VS_VGA

+BIF_VDDC

R398 1

2 0_0805_5%

@

SPLL_VDDC
SPLL_PVSS

216-0842024-A11-MAR_FCBGA631
?

M13
M15
M16
M17
M18
M20
M21
N20

1

2

C

+VGA_CORE

ϯ͘ϱ;ZϯͿ

ISOLATED
CORE I/O

H7

1

B

MPLL_PVDD

+SPLL_PVDD
1

2

d

ϭ͘ϰ

2

2

1

PLL

1
BIF_VDDC
BIF_VDDC

2

C403

C383

2

1

1U_0402_6.3V4Z
DIS@

C399

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
DIS@

C398

1

1U_0402_6.3V4Z
@

C380

2

1

1U_0402_6.3V4Z
DIS@

1

C426

C429

C428

C410

ϭϯϬŵ

Ϭ

ϭϬƵ&

VDDR4
VDDR4
VDDR4

+0.95VS_VGA

Ϯ͘ϱ

+MPLL_PVDD

2

нϯs^ͺs'

V12
Y12
U12

VDDR3
VDDR3
VDDR3
VDDR3

2

1

2

C461

Ϭ

I/O

AA17
AA18
AB17
AB18

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
AA12
M11
N12
U11

1

1

2

1

1U_0402_6.3V4Z
DIS@

Ϭ

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

CORE

2

C460

ϭ

VDD_CT
VDD_CT
VDD_CT
VDD_CT

ϬŽŚŵWͬE

C435

ϭ

+VDDR4

0.1U_0402_10V6K
DIS@

нWͺs

ϭ

+1.8VS_VGA
L51 DIS@
1
2
BLM15BD121SN1D_0402

ϯϬϬŵ

L25
@
1
2
BLM15BD121SN1D_0402

C412

ϭ

+1.8VS_VGA

1U_0402_6.3V4Z
DIS@

ϭ

2

C411

Ϭ

2

10U_0603_6.3V6M
DIS@

Ϭ

1

0.1U_0402_10V6K
DIS@

;ϯϬϬŵͿ Ϭ

1U_0402_6.3V4Z
@

ϭ

1

C434

ϭ

1

0.1U_0402_10V6K
DIS@

ϭ

нWͺsZ

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1U_0402_6.3V4Z
DIS@

ϳϱŵ

ϭϯŵ

2 0_0402_5%

C409

^W>>ͺWs

нd^s

@

1U_0402_6.3V4Z
DIS@

ϭ

ϭ

Ϯϱŵ
1

C408

ϭ

AA20
AA21
AB20
AB21

POWER

ϭ

ϭϯŵ

L24

ϭ

ϭϯϬŵ

sͺd

2

10U_0603_6.3V6M
DIS@

ϭ

2

2

C406

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sZϰ

C

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10U_0603_6.3V6M
DIS@

W/ͺWs

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C422

+3VS_VGA
2

нϭ͘ϴs^ͺs'

C405

ϱ

1

0.1U_0402_10V6K
DIS@

ϱ

C433

ϯ

1

0.1U_0402_10V6K
DIS@

ϭ͘ϱ

10U_0603_6.3V6M
DIS@

sZϭ

+VDD_CT

1

1

C425

1
2
BLM15BD121SN1D_0402
C404

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1U_0402_6.3V4Z
DIS@

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C407

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1U_0402_6.3V4Z
DIS@

нϭ͘ϱs^ͺs'
B

2

10U_0603_6.3V6M
DIS@

LEVEL
TRANSLATION

L56 DIS@

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

1

10U_0603_6.3V6M
DIS@

C392

C381

C391

C390

C389

C374

C373

C372

C371

C370

ϭϯŵ

+1.8VS_VGA

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

C465

ϭ

NC#AB23
NC#AC23
NC#AD24
NC#AE24
NC#AE25
NC#AE26
NC#AF25
NC#AG26

+PCIE_PVDD

1U_0402_6.3V4Z
DIS@

ϭ

2

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

AM30

1U_0402_6.3V4Z
DIS@

ϭ

2

PCIE_PVDD

10U_0603_6.3V6M
DIS@

ϭϬϬŵ

^W>>ͺs

2

1

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

+1.8VS_VGA

ϭϬϬŵ

U?

MEM I/O

C386

Ϭ

2

1

0.1U_0402_10V6K
@

Ϭ

2

1

0.1U_0402_10V6K
DIS@

Ϭ

2

1

0.1U_0402_10V6K
DIS@

ϭ͘ϰ

2

1

0.1U_0402_10V6K
DIS@

/&ͺs

2

1

0.1U_0402_10V6K
DIS@

Ϭ

2

1

1U_0402_6.3V4Z
DIS@

ϱ;ϭΛͿ

2

1

1U_0402_6.3V4Z
DIS@

Ϯ;ϭΛͿ

1

1U_0402_6.3V4Z
DIS@

Ϯ͘ϱ

2

1

1U_0402_6.3V4Z
@

W/ͺs

2

1

1U_0402_6.3V4Z
DIS@

2

1

C375

Ϭ͘ϭƵ&

1

C367

ϭ͘ϱ

10U_0603_6.3V6M
DIS@

ϭƵ&

Ϭ
C365

ϭϬƵ&

ϯ

10U_0603_6.3V6M
DIS@

нϬ͘ϵϱs^ͺs'

ϭ

10U_0603_6.3V6M
DIS@

ϯ͘ϱ

PCIE

s/

C384

DIS@
U666D
+1.5VS_VGA

10U_0603_6.3V6M
@

Ϭ

10U_0603_6.3V6M
DIS@

ϭϬ;ϮΛͿ

C424

ϱ;ϭΛͿ

A

C423

Ϭ͘ϭƵ&

10U_0603_6.3V6M
DIS@

d

ϭƵ&

5

10U_0603_6.3V6M
DIS@

s

ϭϬƵ&

4

C466

нs'ͺKZ

3

10U_0603_6.3V6M
DIS@

A

2

2

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
MARS_Power
LA-9611P
Tuesday, February 26, 2013
Sheet
26
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

[28,29] M_DA[63..0]
[28,29] M_MA[15..0]
[28,29] M_DQM[7..0]
[28,29] M_DQS[7..0]

A

[28,29] M_DQS#[7..0]

3

M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]
A

M_DQS#[7..0]

1
2

DIS@
R365
40.2_0402_1%

2

DIS@
R363
40.2_0402_1%

1

+MVREFSA

1

+MVREFDA

DIS@
R457
100_0402_1%

2

DIS@
C514
1U_0402_6.3V4Z

2

DIS@
C467
1U_0402_6.3V4Z

2

2

1

B

DIS@
R5160
49.9_0402_1%
1
2

DIS@
R455
10_0402_1%
2
1

DRAM_RST
1

[28,29] DRAM_RST#

2

1

DIS@
R5161
5.1K_0402_1%

2

DIS@
C5186
68P_0402_50V8J

2

DIS@
C469
120P_0402_50V8J

1

WůĂĐĞĐůŽƐĞƚŽ'Wh;ǁŝƚŚŝŶϮϱŵŵͿ
ĂŶĚƉůĂĐĞĐŽŵƉŽŶŵĞŶƚĐůŽƐĞƚŽĞĂĐŚŽƚŚĞƌ
;ĚĂŝƐǇĐŚĂŝŶ㕡⺷崘⇘⚃柮sZDͿ
C

+MVREFDA
+MVREFSA
R5162

1 DIS@

2 120_0402_1%

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
K26
J26
J25
K25

U?

GDDR5/DDR3

GDDR5/DDR3

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA0_8/MAA_13
MAA0_9/MAA_15

MEMORY INTERFACE

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

+1.5VS_VGA

1

+1.5VS_VGA

DIS@
R364
100_0402_1%

5

M_DA[63..0]

DIS@
U666C

1

4

MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
MAA1_8/MAA_14
MAA1_9/RSVD
WCKA0_0/DQMA0_0
WCKA0B_0/DQMA0_1
WCKA0_1/DQMA0_2
WCKA0B_1/DQMA0_3
WCKA1_0/DQMA1_0
WCKA1B_0/DQMA1_1
WCKA1_1/DQMA1_2
WCKA1B_1/DQMA1_3
EDCA0_0/QSA0_0
EDCA0_1/QSA0_1
EDCA0_2/QSA0_2
EDCA0_3/QSA0_3
EDCA1_0/QSA1_0
EDCA1_1/QSA1_1
EDCA1_2/QSA1_2
EDCA1_3/QSA1_3
DDBIA0_0/QSA0_0B
DDBIA0_1/QSA0_1B
DDBIA0_2/QSA0_2B
DDBIA0_3/QSA0_3B
DDBIA1_0/QSA1_0B
DDBIA1_1/QSA1_1B
DDBIA1_2/QSA1_2B
DDBIA1_3/QSA1_3B

MVREFDA
MVREFSA
NC#J25
MEM_CALRP0

ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1

DRAM_RST
R460
R373

@
@

1
1

2 51.1_0402_1%
2 51.1_0402_1%

C515
C517

@1
@
@
@1

2 0.1U_0402_10V6K
2
0.1U_0402_10V6K

ZŽƵƚĞϱϬŽŚŵƐƐŝŶŐůĞͲĞŶĚĞĚͬϭϬϬŽŚŵĚŝĨĨĂŶĚŬĞĞƉƐŚŽƌƚ
ĚĞďƵŐŽŶůǇ͕ĨŽƌĐůŽĐŬŽďƐĞƌǀĂƚŝŽŶ͕ŝĨŶŽƚŶĞĞĚ͕E/͘

L10
K8
L7

DRAM_RST

WEA0B
WEA1B

K17
J20
H23
G23
G24
H24
J19
K19
G20
L17

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA13
M_MA15

J14
K14
J11
J13
H11
G11
J16
L15
G14
L16

M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1
M_MA14

E32
E30
A21
C21
E13
D12
E3
F4

M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7

H28
C27
A23
E19
E15
D10
D6
G5

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

H27
A27
C23
C19
C15
E9
C5
H4

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

L18
K16

VRAM_ODT0
VRAM_ODT1

H26
H25

M_CLK0
M_CLK#0

G9
H9

M_CLK1
M_CLK#1

G22
G17

M_RAS#0
M_RAS#1

G19
G16

M_CAS#0
M_CAS#1

H22
J22

M_CS#0

G13
K13

M_CS#1

K20
J17

M_CKE0
M_CKE1

G25
H10

M_WE#0
M_WE#1

M_BA2 [28,29]
M_BA0 [28,29]
M_BA1 [28,29]

B

VRAM_ODT0 [28]
VRAM_ODT1 [29]
M_CLK0 [28]
M_CLK#0 [28]
M_CLK1 [29]
M_CLK#1 [29]
M_RAS#0 [28]
M_RAS#1 [29]
C

M_CAS#0 [28]
M_CAS#1 [29]
M_CS#0 [28]
M_CS#1 [29]
M_CKE0 [28]
M_CKE1 [29]
M_WE#0 [28]
M_WE#1 [29]

CLKTESTA
CLKTESTB
216-0842024-A11-MAR_FCBGA631
?

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
MARS_MEM
LA-9611P
Tuesday, February 26, 2013
Sheet
27
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

Memory Partition A - Lower 32 bits
M_DA[63..0]

[27,29] M_DA[63..0]

M_MA[15..0]

[27,29] M_MA[15..0]

M_DQM[7..0]

[27,29] M_DQM[7..0]

M_DQS[7..0]

[27,29] M_DQS[7..0]

M_DQS#[7..0]

[27,29] M_DQS#[7..0]

+1.5VS_VGA

+1.5VS_VGA
1

A

1

A

DIS@
R452
4.99K_0402_1%

[27,29] M_BA0
[27,29] M_BA1
[27,29] M_BA2

[27] M_CLK0
[27] M_CLK#0
[27] M_CKE0

M2
N8
M3

M_CLK0
M_CLK#0
M_CKE0

J7
K7
K9

M_DQS2
M_DQS0

F3
C7

M_DQM2
M_DQM0

E7
D3

M_DQS#2
M_DQS#0

G3
B7

ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C

2

R5170
40.2_0402_1%
DIS@

M2
N8
M3

M_CLK0
M_CLK#0
M_CKE0

J7
K7
K9

2

VRAM_ODT0 K1
L2
M_CS#0
J3
M_RAS#0
K3
M_CAS#0
L3
M_WE#0
M_DQS3
M_DQS1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_DQM3
M_DQM1

E7
D3

M_DQS#3
M_DQS#1

G3
B7

DRAM_RST#

T2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@

M_DA30
M_DA27
M_DA31
M_DA24
M_DA29
M_DA26
M_DA28
M_DA25

D7
C3
C8
C2
A7
A2
B8
A3

M_DA8
M_DA14
M_DA9
M_DA12
M_DA10
M_DA15
M_DA11
M_DA13

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B

+1.5VS_VGA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

J1
L1
J9
L9

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VS_VGA

BA0
BA1
BA2

L8

DIS@
R456
243_0402_1%

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@

DIS@
C506
0.01U_0402_16V7K

+1.5VS_VGA
+1.5VS_VGA

1

1

C479

1

C534

1

C478

1

C477

1

C476

1

C474

1

C516

1

C533

1

C518

1

C499

1

C498

C497

C496

1

1

2

2

2

2

2

2

0.1U_0402_10V6K
@

2

0.1U_0402_10V6K
@

2

0.1U_0402_10V6K
DIS@

2

0.1U_0402_10V6K
DIS@

2

1U_0402_6.3V4Z
@

2

1U_0402_6.3V4Z
DIS@

2

1U_0402_6.3V4Z
DIS@

2

1U_0402_6.3V4Z
DIS@

2

1U_0402_6.3V4Z
@

2

1U_0402_6.3V4Z
DIS@

C486

C531

C483

C485

C482

C481

C480

C520

C532

C521

C510

C519

C511

C512

C490

1

2

1U_0402_6.3V4Z
DIS@

2

1

10U_0603_6.3V6M
DIS@

2

1

0.1U_0402_10V6K
@

2

1

0.1U_0402_10V6K
DIS@

2

1

hϭϰϬϳƐŝĚĞ

0.1U_0402_10V6K
@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

1U_0402_6.3V4Z
@

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
@

10U_0603_6.3V6M
DIS@

2

1

1U_0402_6.3V4Z
DIS@

1

1U_0402_6.3V4Z
DIS@

C491

hϭϰϬϲƐŝĚĞ

0.1U_0402_10V6K
DIS@

2

M_BA0
M_BA1
M_BA2

VREFCA
VREFDQ

C475

1

DIS@
C540
0.1U_0402_10V6K

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

0.1U_0402_10V6K
DIS@

2

R5171
40.2_0402_1%
DIS@

2

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

A1
A8
C1
C9
D2
E9
F1
H2
H9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

DIS@
R454
243_0402_1%

1

1

M_CLK0
M_CLK#0

1

+1.5VS_VGA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

L8

M_DA3
M_DA2
M_DA5
M_DA1
M_DA7
M_DA0
M_DA6
M_DA4

DIS@
R464
4.99K_0402_1%

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

T2

[27,29] DRAM_RST#

D7
C3
C8
C2
A7
A2
B8
A3

U1407
M8
H1

+FBA_VREF1

+1.5VS_VGA

BA0
BA1
BA2

VRAM_ODT0 K1
L2
M_CS#0
J3
M_RAS#0
K3
M_CAS#0
L3
M_WE#0

VRAM_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA17
M_DA23
M_DA21
M_DA22
M_DA18
M_DA19
M_DA16
M_DA20

0.1U_0402_10V6K
DIS@

[27]
[27]
[27]
[27]
[27]

M_BA0
M_BA1
M_BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

DIS@
C472
0.1U_0402_10V6K

2

2

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

1

1

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

VREFCA
VREFDQ

1

M8
H1

+FBA_VREF0

2

2

U1406

DIS@
R453
4.99K_0402_1%

B

DIS@
R463
4.99K_0402_1%

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
MARS_VRAM A Lower
LA-9611P
Tuesday, February 26, 2013
Sheet
28
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

Memory Partition A - Upper 32 bits
+1.5VS_VGA

1

1

+1.5VS_VGA

DIS@
R461
4.99K_0402_1%

M_DQM[7..0]
M_DQS[7..0]

[27,28] M_DQS[7..0]
[27,28] M_DQS#[7..0]

1

DIS@
R459
4.99K_0402_1%

M_DQS#[7..0]

2

DIS@
C473
0.1U_0402_10V6K

[27,28] M_BA0
[27,28] M_BA1
[27,28] M_BA2

[27] M_CLK1
[27] M_CLK#1
[27] M_CKE1
[27]
[27]
[27]
[27]
[27]

B

M_CLK1
M_CLK#1

VRAM_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

[27,28] DRAM_RST#

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK1
M_CLK#1
M_CKE1

J7
K7
K9

VRAM_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

K1
L2
J3
K3
L3

M_DQS4
M_DQS5

F3
C7

M_DQM4
M_DQM5

E7
D3

M_DQS#4
M_DQS#5

G3
B7

DRAM_RST#

T2

D7
C3
C8
C2
A7
A2
B8
A3

M_DA41
M_DA44
M_DA43
M_DA45
M_DA42
M_DA46
M_DA40
M_DA47

+FBA_VREF3

+FBA_VREF3

M8
H1

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK1
M_CLK#1
M_CKE1

J7
K7
K9

VRAM_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

K1
L2
J3
K3
L3

M_DQS6
M_DQS7

F3
C7

M_DQM6
M_DQM7

E7
D3

M_DQS#6
M_DQS#7

G3
B7

DRAM_RST#

T2

1

M_DA38
M_DA36
M_DA37
M_DA35
M_DA39
M_DA32
M_DA34
M_DA33

DIS@
R462
4.99K_0402_1%

1

2

DIS@
C539
0.1U_0402_10V6K

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_DA49
M_DA53
M_DA51
M_DA54
M_DA50
M_DA55
M_DA48
M_DA52

D7
C3
C8
C2
A7
A2
B8
A3

M_DA60
M_DA63
M_DA57
M_DA56
M_DA62
M_DA58
M_DA61
M_DA59

A

+1.5VS_VGA

DQSL
DQSU
DML
DMU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

+1.5VS_VGA

+1.5VS_VGA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

J1
L1
J9
L9

DIS@
R444
243_0402_1%

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DIS@
C507
0.01U_0402_16V7K

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@

C

VREFCA
VREFDQ

+1.5VS_VGA

2
2

E3
F7
F2
F8
H3
H8
G2
H7

1

1

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

J1
L1
J9
L9

DIS@
R410
243_0402_1%

2
1

U1409

2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

L8
R5172
40.2_0402_1%
DIS@

2

R5173
40.2_0402_1%
DIS@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

[27,28] M_DQM[7..0]

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

VREFCA
VREFDQ

C

+1.5VS_VGA

+1.5VS_VGA

2

2

C537

C493

C489

C488

1

1

2

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

C484

C522

C538

C487

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

1U_0402_6.3V4Z
@

C523

C500

2

1

1U_0402_6.3V4Z
@

2

1

1U_0402_6.3V4Z
DIS@

C503

C501

C502

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
@

2

1

1U_0402_6.3V4Z
DIS@

C530

C535

C529

C509

C505

C508

C504

C528

C536

C492

2

1

1U_0402_6.3V4Z
DIS@

2

1

10U_0603_6.3V6M
DIS@

2

1

0.1U_0402_10V6K
@

2

1

0.1U_0402_10V6K
DIS@

2

1

hϭϰϬϵƐŝĚĞ

0.1U_0402_10V6K
@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

0.1U_0402_10V6K
DIS@

2

1

1U_0402_6.3V4Z
@

1

1U_0402_6.3V4Z
DIS@

2

C527

C513

C524

C526

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
DIS@

2

1

1U_0402_6.3V4Z
DIS@

1

1U_0402_6.3V4Z
@

10U_0603_6.3V6M
DIS@

2

C525

1

1U_0402_6.3V4Z
DIS@

C495

hϭϰϬϴƐŝĚĞ

C494

1

[27,28] M_MA[15..0]

1

M8
H1

+FBA_VREF2

M_MA[15..0]

2

2

[27,28] M_DA[63..0]

2

A

U1408

1

2

0.1U_0402_10V6K
@

DIS@
R458
4.99K_0402_1%
M_DA[63..0]

D

D

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
MARS_VRAM A Upper
LA-9611P
Tuesday, February 26, 2013
Sheet
29
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

Panel 30+10 PIN

LCD PANEL Conn.

+3VS

@

DISPOFF#

modify

1

[38] BKOFF#

2 0_0402_5%

1

A

R2114 1

R2113
R2109

1
1

@
@

2 0_0402_5%
2
0_0402_5%

R2110
R2112

1
1

@
@

2 0_0402_5%
2 0_0402_5%

JLVDS2
1
2
3
4
5
6
7
8
9
10
11
12

[17] TS_ON
[17] USB20_N8
[17] USB20_P8

Touch Panel

R2116
10K_0402_5%
@

[12,14,35,36]
[12,14,35,36]
[18]
[18]

2

2

R2115
10K_0402_5%

+5VS

For power on screen flash issue

SMB_CLK_S3
SMB_DATA_S3
TS_INT#
TS_PRSNC#

A

1
2
3
4
5
6
7
8
9
10
GND
GND

E&T_4260K-F10N-00L
CONN@

+3VS

1

B+

+LEDVDD
2

R2108

@

1

0_0805_5%

R2118
10K_0402_5%

1

2

C2113
4.7U_0805_25V6-K

2

R2107

[16] PCH_PWM

1 0_0402_5%

@

INVPWM
JLVDS1

Place closed to JLVDS1

STARC_107K30-000001-G2

1

1

+3VS

B

R2153
10K_0402_5%

(20 MIL)

R2137
10K_0402_5%
@

1

2

2

@

@

2

C2103
0.1U_0402_10V6K

R2486

1

2 0_0603_5%

2

INVPWM
DISPOFF#
EMB_HPD

+LCDVDD_CONN

CPU_eDP_AUXN
CPU_eDP_AUXP
[32] DMIC_DATA
[32] DMIC_CLK

Thermal Sensor

[17] USB20_P3
[17] USB20_N3
+3VS
+3VS_CMOS
+3VS
[14,24,36,38] EC_SMB_DA2
[14,24,36,38] EC_SMB_CK2

A LOGO RED LIGHT
+1.05VS

+3VS
1

1

LCD Panel
R104
1K_0402_5%

[5]
[5]
[5]
[5]

R1237 1
C555
C554
C557
C556

CPU_eDPC_N1
CPU_eDPC_P1
CPU_eDPC_N0
CPU_eDPC_P0

1
1
1
1

2 750_0402_5% +3VALW_LOGO
@2
@2
2
2

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K

CPU_eDP_N1
CPU_eDP_P1
CPU_eDP_N0
CPU_eDP_P0

R674
100K_0402_5%

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

36
35
34
33
32
31

GND6
GND5
GND4
GND3
GND2
GND1

B

CONN@

2

HPD Inversion for eDP

[37,38] LOGO_LED#
+3VALW

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

PIN10

2

[5] CPU_eDP_HPD#
1

C

D

[5] CPU_eDPC_AUXN

C553 1

2 0.1U_0402_10V6K

CPU_eDP_AUXN

[5] CPU_eDPC_AUXP

C552 1

2 0.1U_0402_10V6K

CPU_eDP_AUXP

PIN1

1

EMB_HPD

PIN1

PIN30

PIN31

C

PIN32

1

S

3

R677
100K_0402_5%

R673
100K_0402_5%

PIN35

PIN33

PIN34

PIN36

2

2

Q11
2N7002K_SOT23-3

2
G

>WKtZ/Zh/d

DK^ĂŵĞƌĂŽŶŶ
+LCDVDD
+3VS

1
C2101
0.1U_0402_10V6K

2
2

D

[16] PCH_ENVDD

1

R2111

VOUT

5

1

VIN
GND

4

1

+LCDVDD_CONN

EN

PCH_ENVDD_R

R314

1

@

(20 MIL)

CMOS SUSPEND 2.4mA
2 0_0603_5%

2
C2109 1

1

3
0.1U_0402_10V6K

APL3512ABI-TRG_SOT23-5

0.1U_0402_10V6K
@
2
1 0_0402_5%

+3VS_CMOS

(20 MIL)

1
2
FBMA-L11-201209-221LMA30T_0805
L2102

SS

C2110
@

+3VS

W=60mils

U2412

W=60mils

Css

Tss

0.1uF

100mS

10nF

10mS

1nF

1mS

Open or
tied to
VIN

1mS

2

2

2

@
C2114
0.1U_0402_10V6K

C2124
0.1U_0402_10V6K

SS table

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

4

Title

1

2

2

@
C2115
10U_0603_6.3V6M

Compal Electronics, Inc.
LVDS Connector
LA-9611P
Wednesday, February 27, 2013
Sheet
30
of
53

Size Document Number
Custom
Date:

1

5

D

Rev
0.4

1

2

3

4

5

Docking (USB3.0)
D2403
1

USB20_P2

I/O1

I/O3

+5VALW
2

[17] USB3_TX2_P
A

[17] USB3_TX2_N

GND

VDD

I/O2

I/O4

DPA_AUX_P

D44
1 

 9

DPA_AUX_P

DPA_AUX_N

2 

 8

DPA_AUX_N

mDP_HPD

4 

 7

mDP_HPD

5 

 6

4

5

USB3_TX2_P

3

USB3_TX2_N

AZC099-04S.R7G_SOT23-6

6

3 

USB20_N2

8
A

YSCLAMP0524P_SLP2510P8-10-9
USB3_RX2_P

[17] USB3_RX2_P

PN: SC300001G00

USB3_RX2_N

[17] USB3_RX2_N

USB20_P2

[17] USB20_P2

USB20_N2

[17] USB20_N2

USB3_TX2_N

D2415
1 

 9

USB3_TX2_N

PCH_DPC_P0_C

D43
1 

 9

PCH_DPC_P0_C

USB3_TX2_P

2 

 8

USB3_TX2_P

PCH_DPC_N0_C

2 

 8

PCH_DPC_N0_C

USB3_RX2_N

4 

 7

USB3_RX2_N

PCH_DPC_P1_C

4 

 7

PCH_DPC_P1_C

USB3_RX2_P

5 

 6

USB3_RX2_P

PCH_DPC_N1_C

5 

 6

PCH_DPC_N1_C

3 

3 

8

8

YSCLAMP0524P_SLP2510P8-10-9

ESD

YSCLAMP0524P_SLP2510P8-10-9

Docking (Display Port)
B

B

Docking Connector
+3VS

DK_DETECT#

JDOCK1

[16] PCH_DPC_P1
[16] PCH_DPC_N1

2 0.1U_0402_10V6K PCH_DPC_P0_C
2 0.1U_0402_10V6K PCH_DPC_N0_C

C545 1
C544 1

2 0.1U_0402_10V6K PCH_DPC_P1_C
2 0.1U_0402_10V6K PCH_DPC_N1_C

1
3
5
7
9
11
13
15
17
19
21
23

DPA_AUX_P
DPA_AUX_N
PA_CFG1_LSEO0
DOCK_CONSUMP
mDP_HPD

[42] DOCK_CONSUMP

+3VS

25
27
29

1

[40] ADP_ID_Dok
R5137
100K_0402_5%

GND
POWER BUTTON
ML_LANE0(P)
RETURN
ML_LANE0(N) VBUS(500mA)
GND
USB2.0(P)
ML_LANE1(P)
USB2.0(N)
ML_LANE1(N)
GND
GND
USB3.0_RX(P)
AUX_CH(P) USB3.0_RX(N)
AUX_CH(N)
GND
CONFIG1
USB3.0_TX(P)
CONFIG2
USB3.0_TX(N)
HOT PLUG DETECT
GND
GROUND
DETECT
GROUND

POWER1
POWER2
GROUND

2
4
6
8
10
12
14
16
18
20
22
24

F1
1

2 1.1A_6V_SMD1812P110TF

USB20_P2
USB20_N2

C1145

USB3_RX2_P
USB3_RX2_N
USB3_TX2_P
USB3_TX2_N
Adap+

1

LANE1

C242 1
C243 1

+5VALW

ON/OFFBTN# [37]
DOCK_PRSNT# [18]
+5VALW_DOCK

2

2

[16] PCH_DPC_P0
[16] PCH_DPC_N0

1 100K_0402_5%
@

1000P_0402_50V7K

LANE0

R678 2

ON/OFFBTN#
DK_DETECT# R338 1
0_0402_5%

ESD

26
28
30

DRAPH_PJSS0296-MB11H

C

2

C

1

2 0.1U_0402_10V6K

DPA_AUX_N

[16] PCH_DPC_AUXP

C5185

1

2 0.1U_0402_10V6K

DPA_AUX_P

Footprint:DRAPH_PJSS0296-MB11H_24P-T

1

[16] PCH_DPC_AUXN

C5184

R5158
100K_0402_5%

SB00000VL00
2

SB00000EO10==>for Lenovo 2nd source

+5VALW

+5VALW_DOCK
R928
0_0402_5%
2
1

+5VS
+5VALW

1

1

Q2404

AP2301GN-HF_SOT23-3

D

check pull up

D

mDP_HPD

@ 2 1M_0402_5%

PA_CFG1_LSEO0

R110 1

@ 2 1M_0402_5%

DOCK_CONSUMP
[38] +5VALW_DOCK_ON

D

Issued Date

Compal Secret Data

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

1

R5140

Security Classification

1

3

R2412
150K_0402_5%
2

1

100K_0402_5%
2
1

3
S

[16] PCH_DPC_HPD

R105 1

2

Q12
BSS138_NL_SOT23-3

2

G

2

R112
1M_0402_5%
@

3

4

Title

Compal Electronics, Inc.
Docking
LA-9611P
Tuesday, February 26, 2013
Sheet
31
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

+3VS

A

WůĂĐĞŶĞĂƌWŝŶϮϱ

D/

2

C5110

1

2

WůĂĐĞŶĞĂƌWŝŶϯϴ

0.1U_0402_10V6K

C648

C5095

1

1

0.1U_0402_10V6K

2

2

4.7U_0603_6.3V6K

1

R1355
@
0_0603_5%
1
1 C693

2

WůĂĐĞŶĞĂƌWŝŶϭ
+IOVDD_CODEC

@

C1143

1

2 0.1U_0402_10V6K

C1144

1

2 0.1U_0402_10V6K

C1147

1

2 0.1U_0402_10V6K

C1148

1

2 0.1U_0402_10V6K

A

1

2

1

2

C654

change to short pad

1

C656

C5096

2

@

1

2

0.1U_0402_10V6K

+5VS_PVDD

EMI

0.1U_0402_10V6K

HDA_BITCLK_AUDIO

D/

R927
0_0402_5%
1
2
@

+5VS_PVDD

R929 @
0_0603_5%
1
2

C657

+5VS

@

0.1U_0402_10V6K

C651 2

33_0402_5%
2

4.7U_0603_6.3V6K

@

R108
1 22P_0402_50V8J 1

2

EMI
change to short pad

1U_0402_6.3V6K

1

C646

2

C5094

EMI
change to short pad

+3VDD_CODEC

0.1U_0402_10V6K

+5VDDA_CODEC

R943 @
0_0603_5%
1
2

4.7U_0603_6.3V6K

+5VS

2

EMI

1

2

1
2MM
@

@
C655 change to short pad
10U_0603_6.3V6M

J11

GND

GNDA

1
R5065
4.7K_0402_5%
@

R942 1
R940 1

[37] PLUG_IN

2

10
11
12

HDA_RST_AUDIO#
PC_BEEP
2 20K_0402_1%

JDREF

2 39.2K_0402_1%

SENSEA

D/^ĞŶƐĞZϵϰϬƉůĂĐĞŶĞĂƌƉŝŶϭϯ
CBN
C666
C5099
C5100

1
1
1

2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K
2 4.7U_0603_6.3V6K

CBP

1

9
HPOUT-R(PORT-A-R)
HPOUT-L(PORT-A-L)
SPDIF-OUT

GNDA

+MIC1_VREFO_L

2
SPK-OUT-L+
SPK-OUT-LSPK-OUT-RSPK-OUT-R+

JDREF
MONO-OUT(PORT-H)
SENSE A
SENSE B
CBN
CBP
CPVEE
LDO-CAP

GPIO1/DMIC-CLK

29
30
31

MIC2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L

42

GPIO0/DMIC-DATA

VREF
AVSS1
AVSS2

PVSS1

43

C5097
2.2U_0603_6.3V6K
2
1

MIC_EXT_C

external MIC
EXT_MIC [37]
R931
470K_0402_5%

40
41
44
45

SPK_L2+
SPK_L1SPK_R1SPK_R2+

B

Internal Speaker

33
32
48

HP_OUTR [37]
HP_OUTL [37]

3

DMIC_CLK_R

2

DMIC_DATA

L2407
1
2
SBY100505T-301Y-N

27
26
37

THERMAL PAD

DMIC_DATA

C5101 1
1U_0402_6.3V6K

DVSS

DMIC_CLK

EMI

PVSS2

7

R930
2.2K_0402_5%

R933
1K_0402_5%
2
1

1

24
23
22
21
17
16
15
14

2

DVDD

DVDD-IO

25

38
AVDD2

AVDD1

SYNC
RESET#
PCBEEP

19
20
13
18
35
36
34
28

sĞŶĚŽƌƌĞĐŽŵŵĞŶĚ͘Ϯ͘ϮƵ
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)

49

ALC3202-GR_MQFN48_6X6

2

1

2

Headphone

[30]
[30]

WůĂĐĞŶĞǆƚƚŽƉŝŶϮϳ

ŽŵďŽ:ĂĐŬĚĞƚĞĐƚ;ŶŽƌŵĂůŽƉĞŶͿ

>ϯϮϬϮsϯ

W,ĞĞƉ [13]

^ϬϬϬϬϱϴϯϭϬ

C5102
1

PC_BEEP_C

2

PC_BEEP

C1140
0.1U_0402_10V6K
1
2

HDA_SPKR

1

1

[38] BEEP#

R1124
33_0402_5%
1
2

@
R1131
10K_0402_5%

2

ĞĞƉ

C1138
0.1U_0402_10V6K
1
2
PC_BEEP_C_R

@ 1U_0402_6.3V6K
C1141
1000P_0402_50V7K

Pin Assignment

Location

R1123 47K_0402_5%
1
2

MIC_JD

Function

2

SPK-OUT (Pin40/41/44/45)

Internal

Int Speaker

Capless HP-OUT (Pin32/33)

External

Headphone out

MIC1(Pin21/22)

External

Mic in

C1134

WĞĞƉ

1

EXT_MIC
C

EMI

2

C

4.7U_0603_6.3V6K

1

[13] HDA_SYNC_AUDIO

[13] HDA_RST_AUDIO#
B

EAPD/COMB-JACK
PD#
SDATA-OUT
BIT-CLK
SDATA-IN

1

1 22_0402_5%

+MIC1_VREFO_L

C659

R938 2

47
4
5
6
8

MIC_JD
EC_MUTE#
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO
SDATA_IN

sĞŶĚŽƌZĞĐŽŵŵĂŶĚĂĚĚϭϬh&

0.1U_0402_10V6K

2

[38] EC_MUTE#
[13] HDA_SDOUT_AUDIO
[13] HDA_BITCLK_AUDIO
[13] HDA_SDIN0

R5071
4.7K_0402_5%
@

39
PVDD1

+3VS

PVDD2

U900

46

WůĂĐĞŶĞĂƌWŝŶϵ
Power down (PD#) power stage for save power
0V: Power down power stage
3.3V: Power up power stage

Vendor Recommand connect to GNDA

ǁŝĚĞϮϱD/>

PN:SP02000TS00
JSPK1

R1356 1

2 0_0603_5% @

SPK_R1-_CONN

SPK_R2+

R1357 1

2 0_0603_5% @

SPK_R2+_CONN

SPK_L1-

R1358 1

2 0_0603_5% @

SPK_L1-_CONN

SPK_L2+

R1359 1

2 0_0603_5% @

SPK_L2+_CONN

D/

@

1
C1136
1000P_0402_50V7K

EMI

1
2
3
4

@

@

D2402
1

SPK_R1-_CONN

1
2
3
4

5
6

2

Width 20 mil
D

2
1
C1135
1000P_0402_50V7K

SPK_R1-

2
1
C1139
1000P_0402_50V7K

< 0.05 ohms
Rated Current > 2A

2
1
C1137
1000P_0402_50V7K

/ŶƚĞƌŶĂů^ƉĞĂŬĞƌ Rdc

GND1
GND2

2

3

SPK_R2+_CONN

ACES_50271-0040N-001
ME@

@

I/O1

I/O3

GND

VDD

I/O2

I/O4

4

SPK_L1-_CONN

5

6

SPK_L2+_CONN

AZC099-04S.R7G_SOT23-6

@

D

ESD request 0830
PIN1

ZĞƐĞƌǀĞĨŽƌ^ƌĞƋƵĞƐƚ͘
Compal Secret Data

Security Classification

PIN4

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
Audio Codec ALC3202
LA-9611P
Tuesday, February 26, 2013
Sheet
32
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

+3V_LAN

4

dŚĞZŶĞĞĚĐŚĞĐĐŬнϯsͺ>E͕н>EͺsĂƉĂĐŝƚŽƌƉůĂĐĞŵĞŶƚ

+LAN_VDD

1.5A
1

2

0.1U_0402_10V6K

2

C1257

1

0.1U_0402_10V6K

2

C1253

1

0.1U_0402_10V6K

C1252

0.1U_0402_10V6K

C1255

A

2

;^ŚŽƵůĚďĞƉůĂĐĞǁŝƚŚŝŶϮϬϬŵŝůƐͿ

1

2

0.1U_0402_10V6K

1

C1245

2

EMI
dŚĞƐĞĐŽŵƉŽŶĞŶƚƐĐůŽƐĞƚŽhϭϮϬϭ͗WŝŶϯϲ

4.7U_0603_6.3V6K

1

W=60mils
C1248

2

L1201
2
2.2UH_NLC252018T-2R2J-N_5%

W=60mils 1

+LAN_SROUT1.05
1U_0402_6.3V6K

1

C1242

2

EMI

0.1U_0402_10V6K

1

2 0_0603_5% +LAN_EVDD10
C1246

0.1U_0402_10V6K

2

C1260

2

1

4.7U_0603_6.3V6K

C1249

1

2

2

+LAN_VDD

R1240 1

+LAN_VDDREG

+3V_LAN
J1203 @

1

@
20_0603_5%

EMI

нϯͺ>EZŝƐŝŶŐƚŝŵĞ;ϭϬйΕϵϬйͿхϭŵ^ĂŶĚфϭϬϬŵ^

1

2

+LAN_VDD
@

R1239 1

W=60mils

1

dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭ͗WŝŶϯ͕ϲ͕ϵ͕ϭϯ͕Ϯϵ͕ϰϭ͕ϰϱ

+3V_LAN

+3VALW

2

0.1U_0402_10V6K

dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭ͗WŝŶϭϮ͕Ϯϳ͕ϯϵ͕ϰϮ͕ϰϳ͕ϰϴ

A

1

C1254

2

0.1U_0402_10V6K

1

C1256

0.1U_0402_10V6K

2

C1258

1

0.1U_0402_10V6K

2

C1259

1

0.1U_0402_10V6K

2

C1241

1

0.1U_0402_10V6K

2

C1243

1

0.1U_0402_10V6K

2

C1247

1

0.1U_0402_10V6K

2

C1250

0.1U_0402_10V6K

C1251

1

5

370mA

JUMP_43X39

dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭ
[14] PCIE_PRX_DTX_P4
[14] PCIE_PRX_DTX_N4

U1201

PCIE_PRX_DTX_P4

C1238 1

2 0.1U_0402_10V6K

PCIE_PRX_C_DTX_P4

22

PCIE_PRX_DTX_N4

C1236 1

2 0.1U_0402_10V6K

PCIE_PRX_C_DTX_N4

23

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

17
18

LAN_CLKREQ#

16

PLT_RST#

25

CLK_PCIE_LAN
CLK_PCIE_LAN#

19
20

XTLO

43

XTLI

44

LAN_WAKE#

28

ISOLATEB

26

[14] PCIE_PTX_C_DRX_P4
[14] PCIE_PTX_C_DRX_N4
B

[14] LAN_CLKREQ#
[14,17,23,35,37,38]

PLT_RST#

[14] CLK_PCIE_LAN
[14] CLK_PCIE_LAN#

R1236
0_0402_5%
1
2
@

[38] LAN_WAKE#
[14,15] PCIE_WAKE#

XTLI

1

+3VS

R1232 1

Y1201
25MHZ_12PF_7V25000012

1

R1235

1

@

2 0_0402_5%

2 1K_0402_5%

R1233
15K_0402_5%

GND
2

2

PCIE_WAKE#
1

C1239
15P_0402_50V8J
1
2
XTLI_R

+3V_LAN

R1228
R1231

1
1

+3V_LAN

R1234

1

@
@

2 10K_0402_5%
2 1K_0402_5%

14
15
38

2 0_0402_5%

33

HSOP

LED3/EEDO
LED1/EESK
LED0

HSON
HSIP
HSIN

EECS
EEDI

CLKREQB

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

PERSTB
REFCLK_P
REFCLK_N

GND

3.3V : Enable switching regulator
0V
: Disable switching regulator

3
C1237
15P_0402_50V8J
1
2

34
35

+LAN_VDDREG

CKXTAL2

R1227

1

46

2 2.49K_0402_1%

24
49

8111F-VB support X'tal free

R1230
R1229

1
2
4
5
7
8
10
11

1
1

@
@

2 10K_0402_5%
2 10K_0402_5%
B

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

DVDD10
DVDD10
DVDD10

13
29
41

+LAN_VDD

LANWAKEB
ISOLATEB

DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

27
39

+3V_LAN

2
3

EVDD10
VDDREG
VDDREG

4

AVDD10
AVDD10
AVDD10
AVDD10

RSET
GND
PGND

REGOUT

21

+LAN_EVDD10

6
7

3
6
9
45

8

+LAN_VDD

36

2

LAN_MDI0+

3
4

LAN_MDI1-

5

LAN_MDI1+

6
7

LAN_MDI2-

8

LAN_MDI2+

9
10
11

LAN_MDI3-

12

LAN_MDI3+
1

TCT1

MCT1

ŽŶŶĞĐƚŽƌd

TD1+

MX1+

TD1-

MX1-

TCT2
TD2
TD2TCT3

MCT2
MX2+
MX2MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

MCT1

23

RJ45_MDO0-

RJ-45 Conn.
㕘㕁嘇&footprint check

D1207
LAN_MDI0-

22

RJ45_MDO0+

21

MCT2

20

RJ45_MDO1-

19

RJ45_MDO1+

18

MCT3

17

RJ45_MDO2-

16

RJ45_MDO2+

15

MCT4

14

RJ45_MDO3-

6

I/O4

I/O2

3

LAN_MDI1+

D1209
MCT1

2

@
1

R1241
LAN_ACTIVITY#

2

JRJ45
1

LANLED_ACT#

9

RP1
LSE-200NX3216TRLF_1206-2
1
2
3
4

8
7
6
5

5

RJ45_GND

VDD

GND

D1210
MCT2
LAN_MDI0+

4

75_0804_8P4R_1%

I/O3

I/O1

510_0402_5%

1

2

10

+3V_LAN

2

RJ45_MDO0+

1

RJ45_MDO0-

2

RJ45_MDO1+

3

NEW(referDC234005L00拵湹捛)
MB TO TOP 4.95 move up 1.35)

RJ45_MDO2+

4

RJ45_MDO2-

5

NEW(refer 130452-D拵湹捛)
MB TO TOP 4.95 move up 1.35)

RJ45_MDO1-

6

RJ45_MDO3+

7

RJ45_MDO3-

8

@
1

LAN_MDI1-

EMI

LSE-200NX3216TRLF_1206-2

AZC099-04S.R7G_SOT23-6
D1211

1
C1287
10P_1206_2KV8J

EMI

MCT3

2

D1208
2

LAN_MDI2-

6

I/O4

I/O2

3

LAN_MDI3+

LSE-200NX3216TRLF_1206-2

D1212
13

@
1

5

RJ45_MDO3+

VDD

GND

2

MCT4

2

@
1
R1246
LANLINK_STATUS#

LSE-200NX3216TRLF_1206-2
C1288
0.01U_0402_16V7K

C

PN:XXXXXXXXXX

24

@

350UH_IH-160
C1262

1

2

0.01U_0402_16V7K

C1261

1

2

0.1U_0402_10V6K

LAN_MDI2+

2

4

I/O3

I/O1

1

EMI

LAN_MDI3-

2

1

510_0402_5%

LANLED_LINK#
+3V_LAN

11
12

AZC099-04S.R7G_SOT23-6

D

Yellow LEDYellow LED+
PR1+
PR1PR2+
PR3+
PR3PR2PR4+

G2

PR4-

G1

14
13

Green LEDGreen LED+
SANTA_130452-D

D

Reserve for Surge
CONN@

D1027 D1028
2nd :SC300001G00
3nd :SC300001100

EMI

ESD
Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

Green

+LAN_SROUT1.05

TS1202
1

B1

B2

RTL8111F-CGT_QFN48_6x6

LAN_MDI0-

yellow

1

C

+V_DAC

A1

A2

12
42
47
48

5

ENSWREG

3
XTLO

LANLINK_STATUS#
LAN_ACTIVITY#

30
32

CKXTAL1

@
4

31
37
40

2

3

4

Title

Compal Electronics, Inc.
LAN RTL8111F
LA-9611P
Wednesday, February 27, 2013
Sheet
33
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

SATA HDD BTB CONN.

SATA HDD CONN.

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

19
17

A_PRE1_HDD
B_PRE1_HDD
R703 2

+3VS

@

1

5
4

SATA_DTX_PRX_P0
SATA_DTX_PRX_N0

10K_0402_5%

18
3
13
21

EN

10
20

VDD
VDD

A_INp
A_INn

6
16

NC
NC

B_OUTp
B_OUTn

A_PRE0
B_PRE0

A_PRE1
B_PRE1

A_OUTp
A_OUTn

TEST
GND
GND
EPAD

B_INp
B_INn

R704

@

1

PN:XXXXXXXXXX

2

2
C2401 1
C2402 1

1
2

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

2

C706

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

C705

[13] SATA_DTX_C_PRX_P0
[13] SATA_DTX_C_PRX_N0

1
1

C68
C67

1

0.01U_0402_16V7K

U702
7

[13] SATA_PTX_C_DRX_P0
[13] SATA_PTX_C_DRX_N0

0.1U_0402_10V6K

R713
10K_0402_5%

@

1

+3VS

1

+3VS

A

5

JHDD1
1
2
3
4
5
6
7

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
2

4.99K_0402_1%

SATA_DTX_PRX_N0_C
SATA_DTX_PRX_P0_C

+3VS

9
8

A_PRE0_HDD
B_PRE0_HDD

15
14

SATA_PTX_DRX_P0_R C710 2
SATA_PTX_DRX_N0_R C709 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C

11
12

SATA_DTX_PRX_P0_R C711 2
SATA_DTX_PRX_N0_R C712 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_DTX_PRX_P0_C
SATA_DTX_PRX_N0_C

+5VS

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

[38] HDD_DETECT#
@ J2401
1

PS8520CTQFN20GTR2-A_TQFN20_4X4

1

2

2

5VS_HDD

JUMP_43X79

1
2

1

2

2

1

1
2

Low

ϭ͘ϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ

Low

High

Ϯ͘ϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ

High

Low

ϯ͘ϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ

High

High

ı
ĸ
Ĳ
ĵ

R2402
100K_0402_5%
2

U2401
2

ST

Xout
Yout
Zout

+3VS_GS

J2402

1

2
2MM
APS_GND

D

[38] GS_ON#

1

GS_ON#

1

2

1

2

Ņ
Ŧ
ŷŅ
ŪŦĩ
Ťťŷ
ŦŪŦ
ġŧŤ
Ņ
ŢŦ
ŪŶġ
Ŵŭņ
Ţŵů
ţĪŢ
ŭţ
Ŧŭ
ťŦ
[38] ť
[38]
ġ

@

2

1

2

PIN15

PIN1
B

mSATA CONN.

C

+3VS

JMSTA1
[13] SATA_PTX_C_DRX_N1
[13] SATA_PTX_C_DRX_P1

0.1U_0402_10V6K

@

2

GS_VOUTX
GS_VOUTY

C2415

LIS34ALTR_LGA16_4X4
APS_GND

1

2 56K_0402_5%
2 56K_0402_5%

0.1U_0402_10V6K

COM
COM
COM
COM

1
4
9
11
13
16

1
1

C2412

NC
NC
NC
NC
NC
NC

ϭ

0.1U_0402_10V6K

2

3
5
6
7

Ϭ

R2403
R2404

2

1

ĞǀŝĐĞ&ƵŶĐƚŝŽŶͲх
^ƚĂŶĚǇDŽĚĞ

E

C2414

1

0.1U_0402_10V6K

C2410

2

10U_0603_6.3V6M

C2413

1

Vs
Vs

0.1U_0402_10V6K

14
15

2 0_0603_5%

12
10
8

C2411

[38] GS_SELFTEST
+3VS
@
1
R2405

Ņ
Ŧ
ŷŅ
ŪĩŦ
ŤųĮŰ
Ŧűņ
Ņ
ġŮ
ŤŦ
ŦŇ
Űűĩų
ŶũųĮŢŮ
Ű
ŢűŦņ
ůŵŮ
ŴŤŮ
ŦŦ
ŵůŪųŰűŴ
ũŴŮ
ŪġťŢ
ŢŰŦġŵŮ
ŢŴ
ůťő
ŦŦŵ
ĮġŶŴůŪġ
ŴĮŴŭġť
VOUTX
Ŕ
VOUTY
ĮŴŦġŢł
ő
Ŀ
ŵŦťŕ
ġŶł
ŵ
Ŵŭ
Ņ
Ŕ
1
ġŪŘ
ŪŦŴņ
ůł
ĲŦ
ŵį
ġŨťŕ
2
ġŵŘ
Ķġł
Ř
ũġİ
ŪŸ
ŪťũġĲů APS_GND
Ĵť
ŵŦŔ
įŨ
ŵũůĶġ
ıũ
ġŰŸ
İ
ġŧŭųĴũ
ķō
ŰŵŦįŪ
ųıůŰ
ġůŬġ
ŭŨ
ń
ġň
ŉ
ţŪ
Ĳűů @ R2138
İŴŬ150K_0402_5%
ń
ġġĪ
ŉ
Ŵ R2410
1ĳ
2
ű
150K_0402_5%
Ŧ
Ŧ@
ť
ġ
Ű
ů
ŭ

[13] SATA_DTX_C_PRX_N1
[13] SATA_DTX_C_PRX_P1

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

C2408 1
C2409 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_PRX_N1
SATA_DTX_PRX_P1

C69
C70

1
3
5
7
9
11
13

1
3
5
7
9
11
13

2
4
6
8
10
12
14

J2404 @
2
4
6
8
10
12
14

2

2

1

1

JUMP_43X79

mSATA_DETEC# [38]
MSATS_DEVSLP [17]

ACES_50169-01441-001
CONN@

+3VS

PIN13

+3VS_GS

PIN1

Q2402
@
AP2301GN-HF_SOT23-3
3

1
1

1
2

ŵ
Ī

APS G-Sensor

Ņ
ņ
Ņ
Ř
ņ
ĲŘ
ı
ĳĩ
ń
ĩ
ŉ
ń
Ĳŉġ
ĳĪ ġĩ
Ī ťġ
ġŦ
ŧġ
Ţġ
ŶĲ
ŭ
ŵ
Ī

1

Ĵ

ń
ŉ
ņ
ĲťŲ
Ŷİ
Ń
ġŢń
ŭŉ
ĩ
ĳŁ
Ū
ķŻ
Ţ
ň
ţŵ
űŪ
ŴŰ
ůĪ

C2426
0.01U_0402_16V7K
2@

2

ŵ
Ī

ņ
Œ
ņ
ĲĩŒ
ĳĩ
Ń
ł
Šĩń
Šŉ ŏ
ń
ő
ő
Ĳœ
ĩ
ŉń
œ
ĳĪ ť
ņ
ņ
ĲĪĲ Ŧ ı
ŠŠ ŧ
ŉŢ
ŉ
Ĳ
Ņ
ŅŶ
Ņ
Ņ
Īİ ŭ
1

C

ń
ŉ
Ņ
ĲťŦ
Įİ
Ń
ń
ĩņ
ŉ
Ů
Ł Į
ĳķű
ũ ķ
ň
ţŢ
ı
űŴ
ŴŪ
Ŵ Į

1

10U_0603_6.3V6M

Low

C2406

ϬĚ͕ŶŽƉƌĞͲĞŵƉŚĂƐŝƐ

1U_0402_6.3V6K

@

ͺWZϬͬͺWZϬ
;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ

@

Ņ
ņ
Ņ
Ĳĩņ
ĳĩ
ł
Ń
Šĩń
Šŉ ŏ
ń
ő
ő
Ĳœ
ĩ
ŉń
œ
ĳĪ ť
ņ
ņ
ıĪİı Ŧ ı
ŠŠ ŧ
ŉŢ
ŉ
Ĳ
Ņ
ŅŶ
Ņ
Ņ
Īİ ŭ

23
24

+5VS

ͺWZϭͬͺWZϭ
;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ

R716
10K_0402_5%

C2405

R712
10K_0402_5%

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
NC
V12
NC

High

1000P_0402_50V7K

R710
@
10K_0402_5%

A

SANTA_191901-1

C2403

B

B_PRE1_HDD

(PIN17)

WŝŶϭϴƚŽ'EĨŽƌ'ĞŶϯ

Low

1

B_PRE0_HDD

(PIN8)

EŽƌŵĂůŽƉĞƌĂƚŝŽŶ
;ĚĞĨĂƵůƚͿ
ŽŵƉůŝĂŶĐĞƚĞƐƚŝŶŐ
ŵŽĚĞĞŶĂďůĞ

R715
10K_0402_5%

2

A_PRE1_HDD

(PIN19)
R708
10K_0402_5%

R711
10K_0402_5%

2

A_PRE0_HDD

(PIN9)

@

d^d
;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ

+3VS

1
R709
10K_0402_5%

2

R707
10K_0402_5%

2

@

+3VS

1

+3VS

1

+3VS

GND
A+
AGND
BB+
GND

1

2

2

2

@
C2417
0.1U_0402_10V6K

1

2

D

@
C2420
10U_0603_6.3V6M

PIN14

Compal Secret Data

Security Classification
@
C2418
0.01U_0402_16V7K

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

4

Title

PIN2

Compal Electronics, Inc.
HDD/mSATA/G-Sensor
LA-9611P
Wednesday, February 27, 2013
Sheet
34
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

+5V_CHGUSB

C9
0.1U_0402_10V6K
2
1

13

[17,37] USB_OC0#

A

2
3

[17] USB20_N1
[17] USB20_P1
R16

1

4
5

2 0_0402_5%

@

USB20_N1_C

3

USB20_P1_C

2

USB3_RX1_N

2

U2004
1

[38] AOU_EN

6
7
8

[38] AOU_CTL2
[38] AOU_CTL3

IN

OUT

FAULT#

NC

DM_OUT
DP_OUT

DM_IN
DP_IN

ILIM_SEL
EN/DSC

ILIM1
ILIM0

CTL1
CTL2
CTL3

GND
GPAD

+

3

WCM-2012-900T_4P
4
4

USB20_N1_C_R

2

12
9
11
10
R11

1

1

1

USB20_P1_C_R

1

USB3_RX1_C_N

L2405
WCM-2012HS-900T

USB20_N1_C
USB20_P1_C

15
16

2

C1146
1

1

L2401

2

+5V_CHGUSB

150U_B2_6.3VM_R35M

+5VALW

C2434

Superworld’s common mode choke(SM070001V00) has quality issue for USB 3.0

1000P_0402_50V7K

USB 3.0 Charger & Conn.

[17] USB3_RX1_N

2 19.1K_0402_1%

USB3_RX1_P

[17] USB3_RX1_P

14
17
[17] USB3_TX1_N

TPS2541ARTER_QFN16_3X3

[17] USB3_TX1_P

0.1U_0402_10V6K

1

2 C2444 USB3TXDN1

0.1U_0402_10V6K

1

2 C2445 USB3TXDP1

3

2

1

3

4

L2404
WCM-2012HS-900T
2
2
1
3

3

4

ESD
A

4

USB3_RX1_C_P

1

USB3_TX1_C_N

4

USB3_TX1_C_P

JUSB1
1
2
3
4
5
6
7
8
9

VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND
STDA_SSTXSTDA_SSTX+

10
11
12
13

EMI

GND
GND
GND
GND

SINGA_2UB4039-200011F
CONN@
D2410
D2401
1

USB20_P1_C_R

I/O1

I/O3

3

GND

VDD

I/O2

I/O4

1

9

USB3_TX1_C_P

USB3_TX1_C_N

2

8

USB3_TX1_C_N

USB3_RX1_C_P

4

7

USB3_RX1_C_P

USB3_RX1_C_N

5

6

USB3_RX1_C_N

5

6

USB20_N1_C_R
3

AZC099-04S.R7G_SOT23-6

B

PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9

4
+5V_CHGUSB

2

USB3_TX1_C_P

VBUS
DD+
GND
RXRX+
GND
TXTX+

5
1
6
2
7
3
8
4
9

ESD

TVWDF1004AD0_DFN9

B

Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card(WLAN/WiMAX)

R2427

[17] BT_DET#

1

1

2 1K_0402_5%

CLK_PCI_DB_R

[14] PCIE_PRX_DTX_N2
[14] PCIE_PRX_DTX_P2
[14] PCIE_PTX_C_DRX_N2
[14] PCIE_PTX_C_DRX_P2
+3VS_AOAC

R2432
EC_TX_P80_DATA
EC_RX_P80_CLK

[37,38] EC_TX_P80_DATA
[37,38] EC_RX_P80_CLK

1
1

2 100_0402_1%
2 100_0402_1%

1
2

CONCR_159SBBA32010NNN
2
1
2 4
3
4 6
5
6 8
7
8 10
9
10 12
11
12 14
13
14 16
15
16 18
17
18 20
19
20 22
21
22 24
23
24 26
25
26 28
27
28 30
29
30 32
31
32 34
33
34 36
35
36 38
37
38 40
39
40 42
41
42 44
43
44 46
45
46 48
47
48 50
49
50 52
51
52

1

2

+3VALW

+3VS_AOAC
J2406

RF_OFF#
PLT_RST#

1

For AOAC assessment

RF_OFF# [38]
PLT_RST# [14,17,23,33,37,38]

1

2

SMB_CLK_S3
SMB_DATA_S3

3

USB20_N10 [17]
USB20_P10 [17]

1

11/17

1
R2411

AOAC_WLAN#

[38] AOAC_WLAN#

AOAC@
1
2
150K_0402_5%

1

EĞĞĚĐŚĞĐŬt>EͬdŵŽĚƵůĞK&&ƉŝŶ

PIN53

D

PIN52

PIN2

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

C2422
AOAC@
0.01U_0402_16V7K

PIN1

PIN54

NEW(apply compal PN)
159SBBA32010NNN

C2419
AOAC@
0.1U_0402_10V6K

1

PIN51

2

D

2

2

&ŽƌƚŽĚĞƚĞĐƚ R2435
100K_0402_5%
ĚĞďƵŐĐĂƌĚ
ŝŶƐĞƌƚ͘

2

Q2403
AOAC@
AP2301GN-HF_SOT23-3

SMB_CLK_S3 [12,14,30,36]
SMB_DATA_S3 [12,14,30,36]

53
54

2 R2470
1K_0402_5%

C

@

JUMP_43X79

G1
G2

R2433
1

[18] WLBT_OFF_51#

2
2

2
[14] CLK_PCIE_WLAN1#
[14] CLK_PCIE_WLAN1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1

0.1U_0402_10V6K

WLBT_OFF_5#
WLAN_CLKREQ1#

J2403
JUMP_43X79
@

JMINI1
CONN@

C2455

C

+3VS_AOAC +1.5VS

10U_0603_6.3V6M

WLAN_WAKE#

[13] WLBT_OFF_5#
[14] WLAN_CLKREQ1#

+1.5VS

C2452

R2243
10K_0402_5%
@

[38] WLAN_WAKE#

+3VS_AOAC

2

+3VS

1

+3VS_AOAC

3

4

Title

Compal Electronics, Inc.
USB 3.0 Connector & WLAN
LA-9611P
Tuesday, February 26, 2013
Sheet
35
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

INT_KBD Conn.
KSO[0..17]

Track point
PN:SP01001CH00

[38]

KSO[0..17]

[38]

<ƉŝŶŶĞĞĚĐŽŶĨŝƌŵ

JKB1

+3VS

Vcc 3V for LEDs
KB_LED1 for Fn
KB_LED2 for F1
KB_LED3 for F4
Fn (S9)

[38] KB_LED1_FN
[38] KB_LED2_F1
[38] KB_LED3_F4
[38] KSI8

FN(S9)

D17 (GND)

JAE_FL10F032HA2

Pin1

+5VS

Pin32

1

+5VS
2

A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

2

C2508
0.1U_0402_10V6K

A

R2226
10K_0402_5%

nwe footprint
Pin
1

JTP1
TP_DATA2
TP_RESET

+5VS

Pin
32

TP_CLK2

[38] KB_LED_DET#

Cable

KB_LED_PWM

[38] KB_LED_PWM

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11 GND1
12 GND2

13
14

CONN@
JAE_FL10F012HA1
TP_DATA2

PIN1

PIN12

TP_CLK2
33
34

GND1
GND2

3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

1

KSI[0..7]

JAE_FL10S032HA1

Pin32

JAE_FL10F032HA2

2

KSI[0..7]

5

D2409

Pin1

change footprint & PN

check PIN1

@
PJDLC05_SOT23-3

Pin
1

Pin
12

1

old footprint

B

B

ESD
Cable

Fintek thermal sensor
placed near CPU Core

Click pad

+3VS

PIN1

PIN12

1

+3VS

R2448
10K_0402_5%
@

PN:XXXXXXXX

2

U2407

JCP1

C

1

C2498
0.1U_0402_10V6K

1

2

REMOTE1+

2

REMOTE1-

3

REMOTE2+

4

REMOTE2-

5

VDD

SMCLK

DP1

SMDATA

DN1

ALERT#

DP2/DN3

THERM#

DN2/DP3

GND

10

EC_SMB_CK2

9

EC_SMB_DA2

EC_SMB_CK2 [14,24,30,38]
+5VS

EC_SMB_DA2 [14,24,30,38]

[12,14,30,35]

SMB_CLK_S3

[12,14,30,35]

SMB_DATA_S3

R2469 1

@

2 0_0402_5%

R2479 1

@

TP_DATA2
TP_CLK2
2 0_0402_5%

+5VS

8
2
R2450 1
@
0_0402_5%

7

MAINPWON

[38,43]

R2443

1

@

2 4.7K_0402_5%

TP_CLK2

R2444

1

@

2 4.7K_0402_5%

TP_DATA2

R2447

1

2 100K_0402_1%

CP_RESET#

to EC

6

to EC
to EC

F75303M_MSOP10

ĚĚƌĞƐƐϭϬϬϭͺϭϬϭǆď
ϮŶĚƐŽƵƌĐĞ
^ϬϬϬϬϮϵϮϭϬͲͲхDϭϰϬϯͲϮͲ/>ͲdZ

[38]
[38]
[38]
[38]
[38]

1
2
3
4
5
6
7
8
9
10
11
12

CP_RESET#
TP_CLK
TP_DATA
TP_RESET
BYPASS

CP_RESET#
TP_CLK
TP_DATA
TP_RESET
BYPASS

1
2
3
4
5
6
7
8
9
10
11
12

C

GND
GND

13
14

ACES_51522-01201-001
CONN@

check rest voltage

TP_CLK

2

3

TP_DATA

1

1

Q2407 near PCH
Q2408 near DIMM

REMOTE2+
1
@
C2505
2200P_0402_25V7K
REMOTE2-

1

1

REMOTE2+

REMOTE2-

2

2

D

ESD

REMOTE1-

1
C2504
2200P_0402_25V7K

E

REMOTE12

Q2407
MMST3904-7-F_SOT323-3

2
B

C
Q2408
MMST3904-7-F_SOT323-3

E

3

C2502
2200P_0402_25V7K

D2408
PJDLC05_SOT23-3
@

C

2
B
3

1
D

@
C2500
2200P_0402_25V7K

2

REMOTE1+

1

REMOTE1+

ůŽƐĞhϮϰϬϳ

2

ZDKdϭ͕Ϯ;нͬͲͿ͗
dƌĂĐĞǁŝĚƚŚͬƐƉĂĐĞ͗ϭϬͬϭϬŵŝů
dƌĂĐĞůĞŶŐƚŚ͗фϴΗ

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

4

Title

Compal Electronics, Inc.
KB/CP/TP/FP/Thermal Sensor
LA-9611P
Tuesday, February 26, 2013
Sheet
36
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

Power Button

3

4

5

I/O Board CONN.
+3VLP
1

Connector: 0.3A / pin
JBTB1

R2453
100K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

2

+3VS

D2412
1

ON/OFFBTN#

[31] ON/OFFBTN#

2
RB751V-40_SOD323-2

2

A

ON/OFF

[38]

Audio combo Jack

1

J2405
SHORT PADS

[32,37]
[32,37]
[32,37]
[32,37]

HP_OUTL
HP_OUTR
EXT_MIC
PLUG_IN

[16,37] PCH_DPB_HPD
[16,37] HDMICLK_NB
[16,37] HDMIDAT_NB

HDMI
JBTB2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

+3VS

[32,37]
[32,37]
[32,37]
[32,37]
+5VS

HP_OUTL
HP_OUTR
EXT_MIC
PLUG_IN

+3VS
[16,37] PCH_DPB_HPD
[16,37] HDMICLK_NB
[16,37] HDMIDAT_NB

1

1

40mil
B

[16,37] PCH_DPB_P0
[16,37] PCH_DPB_N0

R2449
10K_0402_5%
2

R2478
0_0603_5%
2

JFAN1

[38] EC_FAN_ID

1
2
3
4
5
6
7

+5VS_FAN

[38] EC_TACH
[38] EC_FAN_PWM
C2503
1000P_0402_50V7K
@

[16,37] PCH_DPB_P1
[16,37] PCH_DPB_N1

1

1

2

2

C2499
1U_0402_6.3V6K
@

[16,37] PCH_DPB_P2
[16,37] PCH_DPB_N2

1
2
3
4
5
GND1
GND2

[16,37] PCH_DPB_P3
[16,37] PCH_DPB_N3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

[16,37] PCH_DPB_P0
[16,37] PCH_DPB_N0
[16,37] PCH_DPB_P1
[16,37] PCH_DPB_N1

CONN@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
ON/OFFBTN#
29
31
33
N38433539
35
37
39
41
43
45
47
49
51
53
55
57
59

+5VALW
[16,37] PCH_DPB_P2
[16,37] PCH_DPB_N2
[16,37] PCH_DPB_P3
[16,37] PCH_DPB_N3
+5VS

62
64

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

+5VALW

A

+5VS

ON/OFFBTN#
N38433539

Power Button

+3VLP
LID_SW# [37,38]
T9
USB_ON# [37,38]
USB_OC0# [17,35,37]

1

Lid Switch & LED

USB3_TX0_P [17,37]
USB3_TX0_N [17,37]

to EC

USB3_RX0_P [17,37]
USB3_RX0_N [17,37]

USB3.0

USB20_P0 [17,37]
USB20_N0 [17,37]

61
63

GND_2 GND_1
GND_4 GND_3

PANAS_AXK8L60114BG

+3VLP
LID_SW# [37,38]
USB_ON# [37,38]
USB_OC0# [17,35,37]

B

USB3_TX0_P [17,37]
USB3_TX0_N [17,37]
USB3_RX0_P [17,37]
USB3_RX0_N [17,37]
USB20_P0 [17,37]
USB20_N0 [17,37]

D2417
ON/OFFBTN#

ACES_50281-00501-001
CONN@

62
64

FAN PWM

GND_2 GND_1
GND_4 GND_3

61
63

1
3

ACES_51015-06001-002

PIN1

2

L30ESD24VC3-2_SOT23-3
@

PIN5

ESD request 0827

PIN5

PIN1

TPM

Card Reader CONN.

Debug Conn.

C

C

+3VS
+3VS

+3VALW
JDB3

CHECK

U10
1
2
3
7
6
9
4
11
18
5
8
12
13
14

NC
NC
NC
PP
NC
VNC
GND
GND
GND
NC
VNC
NC
NC
NC

VPS
VPS
LPCPD#
SERIRQ
LAD0
LAD1
LFRAME#
LAD2
LAD3
NC
LCLK
NC
NC
LRESET#

24
10
28
27
26
23
22
20
17
25
21
19
15
16

C589 1
C645 1

TPM@
2 10U_0603_6.3V6M
2 0.1U_0402_10V6K
TPM@
1
R680 0_0402_5%

2
@
SERIRQ
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD2
LPC_AD3

+3VS

[13,37,38]
[13,37,38]
[13,37,38]
[13,37,38]
[13,37,38]
[14,17,23,33,35,37,38]
[17]
[35,38]
[35,38]

SERIRQ [13,38]
LPC_AD0 [13,37,38]
LPC_AD1 [13,37,38]
LPC_FRAME# [13,37,38]
LPC_AD2 [13,37,38]
LPC_AD3 [13,37,38]

CLK_PCI_TPM

CLK_PCI_TPM

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
CLK_PCI_DB
EC_TX_P80_DATA
EC_RX_P80_CLK

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

JCARD1
+3VS

GND
GND

[14] PCIE_PRX_DTX_P1
[14] PCIE_PRX_DTX_N1

13
14

Card Reader

ACES_85201-1205N

[17]

CONN@
PLT_RST#

PLT_RST# [14,17,23,33,35,37,38]

LOGO LED

ST33ZP24AR28PVSP_TSSOP28
TPM@

[14] CLK_PCIE_CARD
[14] CLK_PCIE_CARD#
[14]
[14]
[14]
[14,17,23,33,35,37,38]
+3VALW
[30,38]
[38]
+3VLP

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
CARD_CLKREQ#
PLT_RST#
LOGO_LED#
LID_SW1#
USB20_N11
USB20_P11

[17] USB20_N11
[17] USB20_P11

FP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

D

CLK_PCI_TPM

R317 1

2

10_0402_5%
@

C159 1

2

䡢娵LID 妲嘇,暨18PIN CONN

22P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
G1
G2

ACES_50208-0180N-P01
CONN@

@

RF 11/17

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

Compal Electronics, Inc.
PBTN/FAN/TPM/RTC/IO BoardRev
0.4
LA-9611P
Tuesday, February 26, 2013
Sheet
37
of
53

Size Document Number
Custom
Date:

5

D

1

2

+3VALW_EC

+EC_AVCC

3

+3VLP +3VALW

+3VALW_EC

4

2 0_0603_5%

1

@

2

+3VALW_EC

2 330K_0402_5%

[17] CLK_PCI_EC
[14,17,23,33,35,37]
PLT_RST#

R2201
10_0402_5%
1
2

2

CLK_PCI_EC

B

RF EMI

KSO[0..17]

[36] KSO[0..17]

KSI[0..7]

[36] KSI[0..7]

+3VALW

R2225

1

2 47K_0402_5%

KSO1

R2227

1

2 47K_0402_5%

KSO2

R2231

1

@

2 2.2K_0402_5%

EC_SMB_CK1

R2232

1

@

2 2.2K_0402_5%

EC_SMB_DA1

12
13
37
20
38

EC_RST#
EC_SCI#

[18] EC_SCI#
[41] ADP_65W

1
C2210
0.1U_0402_10V6K

T6
[31] +5VALW_DOCK_ON

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
1 KSO16
TPC12

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

2 10K_0402_5%

KSI8

R2228

1

2 2.2K_0402_5%

EC_SMB_CK1

R2230

1

2 2.2K_0402_5%

EC_SMB_DA1

[41,42]
[41,42]
[14,24,30,36]
[14,24,30,36]

[15] PM_SLP_S3#
[15] PM_SLP_S5#
[14,18] EC_SMI#

+3VS

for 5 button
R2452

1

2 10K_0402_5%

EC_FAN_PWM

R2451

1

2 10K_0402_5%

EC_TACH

R2236

1

2 2.2K_0402_5%

EC_SMB_CK2

R2237

1

2 2.2K_0402_5%

EC_SMB_DA2

@

C

C2220 @

1

2 100P_0402_50V8J

EC_SMB_CK2

C2221 @

1

2 100P_0402_50V8J

EC_SMB_DA2

1

R2239

2 10K_0402_5%

PCH_PWROK

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

+VSB_EN

[36]
[34]
[35]
[36]
[37]
[35,37]
[35,37]
[15]
[37]
[34]

TP_RESET
GS_ON#
RF_OFF#
KB_LED_PWM
EC_TACH

EC_TACH
EC_PME#
EC_TX_P80_DATA
EC_RX_P80_CLK
PCH_PWROK
EC_FAN_PWM

EC_TX_P80_DATA
EC_RX_P80_CLK
PCH_PWROK
EC_FAN_PWM
GS_SELFTEST

R2221 1

[15] SUSCLK

@

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_SMI#
KB_LED3

2 0_0402_5%

122
123

EC_RTCX1
SUSCLK_R
1

change 0 ohm

1

2

2

S RES 1/16W 33K +-1% 0402

BRDID

R2213
20K_0402_1%

67

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

C2213
20P_0402_50V8
KB9012QF A4 LQFP 128P_14X14
@

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

21
23
26
27

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

SPI Flash ROM

GPIO

GPIO

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPI

typ

V AD_BID
0 V
0.354
0.430
0.550
0.702
0.819

V
V
V
V
V

V
V
V
V
V

VAD_BID
0 V
0.360
0.438
0.559
0.713
0.831

max Phase
SDV
V
FVT
V
SIT
V
SVT
V
V

A

63
64
65
66
75
76

ACOFF
BATT_TEMP

BRDID

97
98
99
109

AOU_CTL2 [35]
EC_FAN_ID [37]
AOU_CTL3 [35]
AOAC_WLAN# [35]

PTC_PROTECT [41]
VGA_AC_DET [24,47]
ME_FLASH [13]
NTC_V [41]

NTC_V

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108

mSATA_DETEC#
LID_SW# [37]
BYPASS [36]

LID_SW#
BYPASS
KB_LED2

H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#

124

+V18R

ECAGND

Turbo_V

R2218 1

@

2 10K_0402_5%

NTC_V

R2219 1

@

2 10K_0402_5%

BATT_TEMP

R2240 1

@

2 10K_0402_5%

Turbo_V

R2217 1

@

2 47K_0402_5%

NTC_V

R2206 1

@

2 10K_0402_5%

ADP_65W

R2207 1

2 10K_0402_5%

ADP_90W

R2214 1

2 10K_0402_5%

EC_MUTE#

R2202 1

2 10K_0402_5%

HDD_DETECT#

R2204 1

2 100K_0402_5%

mSATA_DETEC#

R2242 1

2 10K_0402_5%

HDD_DETECT#

R2246 1

@

2 100K_0402_5%

mSATA_DETEC#

R2244 1

@

2 10K_0402_5%

USB_ON#

R2209 1

@

2 10K_0402_5%

TP_CLK

R2211 1

2 4.7K_0402_5%

TP_DATA

R2212 1

2 4.7K_0402_5%

TP_CLK

R2216 1

@

2 4.7K_0402_5%

TP_DATA

R2241 1

@

2 4.7K_0402_5%

B

+5VALW

for 5 button

+5VS

+3VS
@

2 0_0402_5%

MAINPWON

[36,43]

C

ACIN [15,42]
EN_3V [43]
ON/OFF [37]
LCD
LID_SW1# [37]
SUSP# [10,25,39,44,46,47]

SUSP#
KB_LED1
EC_PECI

on/off
R2245 1

ECAGND [41]

2 100K_0402_5%

+3VALW_EC

BKOFF# [30]
PBTN_OUT# [15]
EN_5V [43]
SA_PGOOD [45]

ON/OFF

C2214

R2208 1

For LCD thermal

R2215 1

SA_PGOOD
ACIN

LID_SW1#

EC_RSMRST# [15]
EC_WAKE# [18]
Turbo_V [41]

EC_WAKE#

110
112
114
115
116
117
118

[34]

ENBKL [16]
ADP_ID [40]
KSI8 [36]
AOU_EN [35]
ADP_90W [41]
HDD_DETECT# [34]
CP_RESET# [36]
SYSON [44]
VR_ON [48]
PM_SLP_S4# [15]

SYSON

2 100K_0402_5%

+3VALW

EC_MUTE# [32]
USB_ON# [37]
KB_LED_DET# [36]
DGPU_PWROK [18,47]
TP_CLK [36]
TP_DATA [36]

TP_CLK
TP_DATA

R2203 1

+3VLP

IMVP_IMON [48]

EC_MUTE#
USB_ON#

LID_SW#

LED on/off

BATT_TEMP [41]
GS_VOUTX [34]
ADP_I [41,42]
GS_VOUTY [34]

68
70
71
72
83
84
85
86
87
88

LCD for thermal

LOGO_LED# [30,37]
BEEP# [32]
WLAN_WAKE# [35]
ACOFF [42]

BEEP#

SPI Device Interface

Bus

min

+3VALW_EC
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

EMI

2

SD034330280

4.7U_0603_6.3V6K

R2223
100K_0402_5%
@

S RES 1/16W 27K +-1% 0402

VAD_BID
0 V
0.347
0.423
0.541
0.691
0.807

U2201

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1

S RES 1/16W 20K +-1% 0402

SD034270280

PWM Output

11
24
35
94
113

R2454

SD034200280

R2210
100K_0402_1%

EC 天㯪枰㓡䁢1%

+3VLP
77
78
79
80

S RES 1/16W 15K +-1% 0402

EC_VDD/AVCC

1
2
3
4
5
7
8
10

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

S RES 1/16W 12K +-1% 0402

SD034150280

@

2

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

[13,18]
[13,18]
[13,37]
[13,37]
[13,37]
[13,37]
[13,37]
[13,37]

SD034120280

2 43_0402_1%

H_PECI [18,6]

1

2

+3VALW
1

1

9
22
33
96
111
125

2

1000P_0402_50V7K

1

C2207

@

1000P_0402_50V7K

2

C2208

1

0.1U_0402_10V6K

@

C2206

2

0.1U_0402_10V6K

1

C2205

0.1U_0402_10V6K

C2204

0.1U_0402_10V6K

1

2

R2205 1

C2209
22P_0402_50V8J
1
2

2 0_0603_5%

EMI
C2203

GPIO44
GPIO45
GPIO46
GPIO47
GPIO4A
GPIO4B
GPIO4E
GPIO4F
GPIO50
GPIO5B

2 0_0603_5%

@

+3VALW_EC

EMI

Can't internal pull up
A

@

1

1

2
ECAGND

R310 1
R313

2

2 0_0603_5%

C2202
1000P_0402_50V7K
@

AGND/AGND

1

2

@
L2202 1

1

69

C2201
0.1U_0402_10V6K

3.3V +/- 5%
Vcc
R2210 100K +/- 1%
Board ID
R2213
0K +/- 5%
0
12K +/- 5%
1
15K +/- 5%
2
20K +/- 5%
3
27K +/- 5%
4
33K +/- 5%
5

1

@
L2201 1

5

+3VALW

+EC_AVCC

R2220
10K_0402_5%
2

(EC_PME#)
@
R2222 1

add resister

SUSCLK_R
@

BOTTOM SIDE
2

32.768KHZ_12.5PF_CM31532768DZFT

1

2

C2218
18P_0402_50V8J
@

VR_HOT# R2233 1

2 0_0402_5%

1

2

2

1

SW4

D
[41] H_PROCHOT#_EC

2

[43] PWR_RESET

PWR_RESET

4
SKRBAAE010_4P

3

2

R2234
R2235
R2238

2
2
2

1 100_0402_1%
1 150_0402_1%
1 100_0402_1%

KB_LED1_FN [36]
KB_LED2_F1 [36]
KB_LED3_F4 [36]

1
Q2203
2N7002K_SOT23-3
@

EC_PME#

Q2202
2N7002K_SOT23-3

Compal Secret Data

Security Classification
Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GND
1

KB_LED1
KB_LED2
KB_LED3

[33]

D

3

PCI_PME# [17]
+3VALW

G
S

C2219
18P_0402_50V8J
@

[6]

1

SN111005800
by ME drawing

H_PROCHOT#

3

1

[48] VR_HOT#

11/14

S

2 10M_0402_5%

Y2202

D

@
@

LAN_WAKE#

2 0_0402_5%

@

2

R2229 1

D

R2224 1

G

EC_RTCX1

2 0_0402_5%

3

4

Title

Compal Electronics, Inc.
EC ENE-KB9012
LA-9611P
Tuesday, February 26, 2013
Sheet
38
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

1

2

3

4

5

+5VS
+5VALW

J510

3

5

+3VALW

6
7

4

A

1

1

2

2

C2322

CT1

VBIAS

C2309

9
8

VOUT2
VOUT2

3VS
@

1

15

0.01U_0402_16V7K

0.01U_0402_16V7K

GPAD

2

TPS22966DPUR_SON14_2X3

+3VALW

1

2

PU502
+1.8VS
PU1202
+0.95VS_VGA

10

CT2

VIN2
VIN2

2

11

GND

ON2

1

@
C2307
10U_0603_6.3V6M

12

@

1

2

1U_0402_6.3V6K

3VS_GATE

1

1

C2326

2 470K_0402_5%

R2318
1

10mil

ON1

14
13

1U_0402_6.3V6K

5VS_GATE
+5VALW

VOUT1
VOUT1

C2325

2 200K_0402_5%

VIN1
VIN1

10U_0603_6.3V6M

R2313
1

SUSP#

2

@ JUMP_43X79

U2301
1
2

[10,25,38,39,44,46,47]

2

5VS

C2308

нϱs>tdKнϱs^
нϯs>tdKнϯs^

+5VALW

PU401

U2301

+3VALW

+3VS

+5VALW

+5VS

A

+3VS
J511
1

1

2

1

2

10U_0603_6.3V6M

@

C2323

@ JUMP_43X79

10U_0603_6.3V6M

2

2

1
C2324

@

1

10U_0603_6.3V6M

2

C2305

1

10U_0603_6.3V6M

2

C2306

@

1

10U_0603_6.3V6M

C2318

2

10U_0603_6.3V6M

C2316

1

2

PU501

U2303
+1.5VS

+1.5VP

нϭ͘ϱsƚŽнϭ͘ϱs^

B+

B

R2322
@

2

S

1

+CPU_CORE

1

C2321

G

D
2
S
3

1

0_0402_5%

2

Q2306
2N7002K_SOT23-3

+VCCSA

PU901

3

SUSP#

2

0.1U_0402_10V6K

[10,25,38,39,44,46,47]

+1.05VS
R2311
470_0603_5%
@

10mil

D
SUSP#

PU601

21.5VS_GATE

1

2

2
1

1

1U_0402_6.3V6K

20mil

2

C2320

2 100K_0402_5%

1

10U_0603_6.3V6M

1

PU701

1
C2319

R2312

0.1U_0402_10V6K
C2317

10U_0603_6.3V6M

C2315

2

1

3

1

+1.5VS

U2303
AP2301GN-HF_SOT23-3

B

2

+1.5V

+3VALW

PU501
+0.75VS

SUSP

G
Q2311
2N7002K_SOT23-3
@

+GPU_CORE

C

C

1

нϯs>tdKнϯs>t;W,hyWŽǁĞƌͿ

+3V_PCH

2

SUSP

[6] SUSP

L

1

+3VALW

+VGA_CORE

R2303
100K_0402_5%
2

@
R2308
100K_0402_5%

Short J2301 for PCH VCCSUS3.3

PU801

+5VALW
1

VL

D
[10,25,38,39,44,46,47]

2

SUSP#

Q2302
2N7002K_SOT23-3

G

H

S
3

40mil

1

40mil

2

R2306
10K_0402_5%

&Žƌ/ŶƚĞů^ϯWŽǁĞƌZĞĚƵĐƚŝŽŶ

1

1

1

1 2

1 2
S

2

SUSP

S

Compal Secret Data

Security Classification

G
Q2310
2N7002K_SOT23-3

3

S

SUSP

G
Q2309
2N7002K_SOT23-3
@

D

R2319
470_0603_5%

D
2

SUSP

G
Q2308
2N7002K_SOT23-3
@

3

S

D
2

SUSP

G

+3VS

R2317
470_0603_5%

D
2

SUSP

Q2307
2N7002K_SOT23-3
@

3

3

1

D
2
G

R2316
470_0603_5%
@

3

D

+5VS

1 2

R2315
470_0603_5%
@
1 2

1 2

R2314
22_0603_5%
@

S

+1.8VS

1

+1.05VS

1

+0.75VS
D

Q2312
2N7002K_SOT23-3

Issued Date

2011/07/12

Deciphered Date

2012/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3

4

Title

Compal Electronics, Inc.
DC Interface
LA-9611P
Tuesday, February 26, 2013
Sheet
39
of
53

Size Document Number
Custom
Date:

5

Rev
0.4

5

4

3

2

1

VIN
ADP_ID
1
2

SMB3025500YA_2P

PC104
1000P_0603_50V7

1

PL101

2

1

PC102
100P_0603_50V8

[31] ADP_ID_Dok
D

2

2

PF101
7A_24VDC_429007.WRML

2
PC103
100P_0603_50V8

1

APDIN1

1

2

PC101
1000P_0603_50V7

1

Adap+

AC Adapter 45W
65W
90W
R(ohm)
118
287
549
ADP_ID(V) 0.449 0.913
1.395
Detection <=0.663, <=1.134, <=1.618,
-Voltage(V) >0.234 >0.693
>1.172

135W
1000
1.886
<=2.109,
>1.663

D

PR101
1

2

@

1
2

PC107
.1U_0402_16V7K

2

1

+3VALW

@

PC108
680P_0603_50V7K

0_0402_5%
PR106
750_0402_1%
1
2

ADP_ID [38]

A/D

+CHGRTC
@

PR111
1K_0603_5%
1
2

1

PD103

PR112

2
0_0603_5%

2

C

+RTCBATT

C

1
3
JRTC1
1
S SCH DIO BAS40CW SOT-323
1K_0402_5%
PR113

2

1
2
3
4

1
2
GND
GND
ACES_50271-0020N-001
@

+3VLP

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR DCIN

Size Document Number
Custom

Rev
0.4

VIUS1

Date:

Tuesday, February 26, 2013

Sheet
1

40

of

53

5

4

3

2

1

Rsistance between Turbo_V and ECAGND:
VMB2

PL201
SMB3025500YA_2P
1
2

45 W: 10K
65 W: 4.4K
90 W: 2.27K

ACES_51202-00901-001

2

1

1

EC_SMCA
EC_SMDA

BATT+
PC202
0.01U_0603_25V7K

PF201
12A_65V_451012MRL
2

2

1

2
1
PR202
100_0402_1%

D

1
2
3
4
5
6
7
8
9
10
11

2
1
PR201
100_0402_1%

1
2
3
4
5
6
7
8
9
GND
GND

PC201
1000P_0603_50V7

JBATT1

VMB

(Default)
(ADP_65W to High,ADP_90W to Low)
(ADP_90W to High,ADP_65W to Low)
D

Trigger Power:
45 W ĺ 55 W ĺ ADP_I:1.65
65 W ĺ 74 W ĺ ADP_I:2.22
90 W ĺ 106 W ĺ ADP_I:3.18

@

PH201 under CPU botten side :
CPU thermal protection at 100 degree C

1

4

1

1

2
PR211
1
@

10K_0402_1%

PR210

5

1

2

C

NTC_V [38]

PQ204B

PQ204A

PR207
10K_0402_1%

2

Turbo_V [38]

2

1
[38] ADP_65W

10K_0402_1%

2N7002KDW-2N_SOT363-6

+EC_AVCC

3 2

C

1

A/D

PR209

BATT_TEMP [38]

6 2

1
2
PR205
10K_0402_5%

2.94K_0402_1%

2

+3VALW

PR208
7.87K_0402_1%

1
2
PR203
6.49K_0402_1%

1

[38,42] ADP_I

EC_SMB_DA1 [38,42]

PR206
3.74K_0402_1%

EC_SMB_CK1 [38,42]

PH201
100K_0402_1%_TSM0B104F4251RZ

2N7002KDW-2N_SOT363-6

VMB2

+3VLP

2

H_PROCHOT#_EC [38]

+3VALW

2

2

@

PR213
100K_0402_1%

[38,41] ECAGND

1

1

1000P_0402_25V8J

[38,41] ECAGND
PR212
100K_0402_1%
1

2

[38] ADP_90W
PR214
768K_0402_1%

BATT_OUT [42]
@

PQ201
2N7002KW_SOT323-3
D
2
OT1
G
S
3

2

PR217

2

1

1

1

PC205

2

@

@

B

PH201:
PR221
0_0402_5%

Temp.

Rman.

Rnor.

Rmin. (Kohm)

1

@

VL
@
2

1

@
B

PC206
0.1U_0603_25V7K

2

90.9K_0402_1%

PC204
0.1U_0603_25V7K

TMSNS1
@

1

2

PU201
1

PC207

1

2
.1U_0603_25V7K
OT1

[38] PTC_PROTECT

3
4

VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2

8

TMSNS1

93

7.3419

7.0792

6.8253

7
6

TMSNS2

5

G718TM1U_SOT23-8

Posestor

1

2

TMSNS21

2

VL

316K_0402_1%

PR1211
2

1K_0402_50%

1

2

MOS_OTP:
Default:High
Active :Low

PR1201
100K_0402_1%

MOS_OTP [43]

2

1K_0402_50%
PQ203
2N7002KW_SOT323-3
D

A

PTC_PROTECT:
Default:Low
Active :High

1

1K_0402_50%

1

PR1207
2 1

1K_0402_50% 1K_0402_50% 1K_0402_50%

PR1210
2

PR1206
2 1

PTC_PROTECT2
G

Compal Secret Data

Security Classification
3

1

1

1K_0402_50%

PR1208
A

PR1205
2

1

PR1204
2

1K_0402_50%

2

PR1203
1

PR1202
100K_0402_1%

1

+3VLP
PR1209

S

Issued Date

2010/01/25

2010/12/31

Deciphered Date

Title

Compal Electronics, Inc.
PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
1

41

of

53

3

8
7
6
5

1

@

@

2

@

1

PC311
2

1

2

1
2
PR310
200K_0402_1%

2
PR306
100K_0402_1%

1

1
2

1

@

RB751V40_SC76-2
PC321
1U_0603_16V6K

@

BQ24727VDD

DL_CHG

6

1
3

1

2N7002W-T/R7_SOT323-3

5
C

4
1
CHG

4

2

3

PR324
4.7_1206_5%

2

16

2

SRP

BA+

SRN

PC318
10U_0805_25V6K
2
1

3
2
1
4

PD302
REGN

PQ312B
2N7002KDW -2N_SOT363-6
@

5
6
7
8

PR323
PC317
2.2_0603_5% 0.047U_0603_16V7K
1
2
2
1

BST_CHG

16251_SN
2

17

15

14

6.8_0402_5%
1 12
PR327
2

PC322

1

DH_CHG

2

[41] BATT_OUT

2

SRN

19

@

PL302
10UH +-20% PCMB104T-100MS 6A
PR321
0.01_1206_1%

PQ314
AO4466L_SO8

BTST
LODRV

ILIM

BM

1U_0603_25V6K

18

S

@

PACIN_2
PQ312A
2N7002KDW -2N_SOT363-6

PC320
10U_0805_25V6K
2
1

4

2
G
3

PC313
0.1U_0603_25V7K
2
1
5
6
7
8
PQ313
AO4466L_SO8

1
ACN

ACP

2

3
CMPOUT

2

PQ311

0_0603_5%

LX_CHG
HIDRV

SA000051W00

SCL

11

118K_0402_1%

PHASE

PU301
BQ24737RGRR_VQFN20_3P5X3P5

2
S DIO GLZ22B LL-34

2

3
2
1

SDA

PR326
PD303

1

20

IOUT

GND

10

PR335
1

PC315

SRP

+3VALW

PR325
1
2
316K_0402_1%

1

9

21

PR328
10_0402_5%

3
1

100P_0603_50V8
8

TP
VCC

1 13

[38,41] EC_SMB_DA1

7

ACDET

2

PC314
0.1U_0603_25V7K

PC316
1
2

CMPIN

6
1

59K_0402_1%

ACOK

[38,41] ADP_I

2

4

5

PR316
2
1
392K_0402_1%

PR318
1

PR319
10_1206_5%
1
2

0.1U_0402_25V6

VIN

1SS355_SOD323-2

VIN

P2
PC312

[38,41] EC_SMB_CK1

2
ACOFF-1

2

D

PC319
680P_0603_50V7K

1

2

[38] ACOFF

1

ACPRN

2

PQ318
DTC115EUA_SC70-3
PD301
2

1

4

5

PR313
150K_0402_1%

2
PQ310B

PR320
47K_0402_1%
1
2

PACIN

3

P2-2

1

PACIN_2

C

2N7002KDW-2N_SOT363-6

1

6
PQ310A
2N7002KDW -2N_SOT363-6

2

PQ309
DTC115EUA_SC70-3

1

2

0.1U_0402_25V6

0.1U_0402_25V6

3

3

DTC115EUA_SC70-3

100K_0402_1%

2

D

1

1

PC310

PQ307

@

2200P_0402_50V7K

PR312

1

DOCK_CONSUMP [31]

V1 2
1

PC303
1

2

VIN

1
2
3

V1

10_0402_1%

Lenovo request

BATT+

200K_0402_1%

PR308
1

@
2

1

ACP

1

1

JUMP_43X118
PQ303
AO4423L SO8

4
2

@
PR329

1

PR311

2

@

47K_0402_5%

ACN

P2-1

PC309
2200P_0402_50V7K

PC308
4.7U_0805_25V6-K
1
2

PC307
10U_0805_25V6K
1
2

2
1

2

2

PC306
10U_0805_25V6K
1
2

3

0_0402_5%

4

2

PR314
1

@

1

PR315
1

2
1

1

PC302
10U_0805_25V6K

2
1

PC301
0.1U_0603_25V7K
2
1
PR305
200K_0402_1%

2

3

1
PR301
47K_0402_5%

2

PC304
5600P_0402_25V7K

2

0_0402_5%

PL301

2

8
7
6
5

PR302
0.015_1206_1%

1

4

4

8
7
6
5

1

2

1
2
3

1UH_PCMB061H-1R0MS_7A_20%

1
2
3

PQ306
DTA144EUA_SC70-3

SH00000AA00

2

PQ304
AO4423L SO8

1
2
3

PC305
10U_0805_25V6K

P2

8
7
6
5

D

1

PJ301
2

PQ302
AO4407A_SO8

P3

PQ301
AO4407A_SO8

VIN

2

B+

4

4

DCR ㎃ㆸ 15m ohm,CP,Throttling....need redefine with EC

PR309
100K_0402_1%

5

B

B

1

2

PC324
0.1U_0402_25V6

1
2

1
2

PC323
0.1U_0402_25V6

0.1U_0402_25V6

@

PR332
10K_0402_1%
1
2

1

1

BQ24727VDD

PR331
10K_0402_1%

ACIN [15,38]

PACIN

D

S

PR334
2

2
G
2N7002W-T/R7_SOT323-3

A

1

PQ316
ACPRN

3

1

2

2

PR330
47K_0402_1%

12K_0402_1%
A

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

CHARGER
Document Number

Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
1

42

of

53

D

PR402
ENTRIP1-1

0_0402_5%
2

5
4

PC424
68P_0402_50V8J
2
1

5
6
7
8

PC410
0.1U_0402_25V6
2
1

PC409
2200P_0402_50V7K
2
1

LG_5V

Typ: 175mA

1
+

2
@

0_0402_5%

2

1

2

TON (1)SMPS1=305KHZ (+5VALWP)
(2)SMPS2=357KHZ(+3VALWP)
3

PR420

@

MAINPWON [36,38]

PC413
150U_B2_6.3VM_R45M

2

1

SI4634DY-T1-GE3_SO8

4.7U_0603_6.3V6K

@

3
2
1

PC417
4.7U_0603_6.3V6K

1

ENABLE

2

VL

2

+5VALWP

PC418
680P_0603_25V8J

PC416

PR417
1

1

1

PR415
2

PC406
10U_0805_25V6K
2
1

16

2

PL402
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2
LX_5V
PR412
4.7_1206_5%
2
1

LDO3

LX_5V

PQ404

15

LDO5

ENM

14

13

UG_5V

17

Typ: 175mA

PR416
0_0402_5%

PQ405B
2N7002KDW-2N_SOT363-6

1

18

4

4

PR413
499K_0402_1%
1
2

PR418
100K_0402_1%

3

6

[38] PWR_RESET
2

PR411
PC411
2.2_0603_5%
0.1U_0603_50V_X7R
1
2 BST_5V_1
1
2
BST_5V

RT8243_B+

ENTRIP2-1

PQ405A
2N7002KDW-2N_SOT363-6

LGATE1

+3VLP

EN
Rising=1.2-1.6- 2V
Falling0.9-0.95- 1V

@

PQ402
SI4172DY-T1-GE3_SO8

19

1

RT8243_B+
ENTRIP1-1

11

0.1U_0603_50V_X7R
2
1

ENLDO

VIN

4

12

8
7
6
5

PC415

2

2

LGATE2

PQ403
AO4712L_SO8

3V5V_ENLDO

+

PHASE2

PC419
1U_0402_16V6K
2
1

1

10

LG_3V

@

SNUB_5V

UGATE2

PHASE1

1
2
3

PC414
@ PR401
680P_0603_25V8J 4.7_1206_5%
2
1
2
1

PC412
150U_B2_6.3VM_R45M

+3VALWP

@

3
2
1

BOOT2

UGATE1
9

LX_3V

PL401
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2

PC407
10U_0805_25V6K
2
1

64.9K_0402_1%
1
FB1

2

TON

@

20

RT8243AZQW_WQFN20_3X3BOOT1
8

RT8243_B+

21

PAD
BYP1

2

3

PR406
20K_0402_1%
1
2

5
6
7
8

1
2
3

7

ENTRIP1

PR410
2 BST_3V_1
1
2 BST_3V
2.2_0603_5%
PC408
UG_3V
0.1U_0603_50V_X7R
1

PGOOD

ENTRIP2

4

FB2

6

AO4466L_SO8

3

ENTRIP22
5

PU401

PQ401

4

8
7
6
5

PC405
2200P_0402_50V7K
2
1

@

PC422
10U_0805_25V6K
2
1

@

PC404
10U_0805_25V6K
2
1

2
PC401
0.1U_0402_25V6
2
1

1

PC423
68P_0402_50V8J
2
1

B+

HCB2012KF-121T50_0805

PR404
30K_0402_1%
1
2

2

PR405
21.5K_0402_1%
1
2

RT8243_B+
PL400

1

FB_5V

PR408

PR403
14K_0402_1%
1
2

PC402
100P_0402_50V8J
1
2

ENTRIP11

PC403
100P_0402_50V8J
1
2
FB_3V

1

E

@

C

1 ENTRIP2-1
PR407
124K_0402_1%
71.5K_0402_1%
2
1
3V5V_TON

B

@

A

1

MOS_OTP [41]

0_0402_5%

PD401
1

+3.3VALWP
Ipeak=6.4A ; 1.2Ipeak=6.72A; Imax=3.92A
f=375KHz, L=4.7UH
Rdson=13.5~16.5m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=1.48/2=0.74A
Vlimit=10*10^-6*150Kohm/10=0.15V
Ilimit=0.15/(16m*1.2)~0.15/(13m)=7.82A~11.53A
Iocp=7.7A (8.536A>8.4A -> ok)

PD402
2

2

S SCH DIO RB751V40 SC76

1

S SCH DIO RB751V40 SC76

@
+3VALWP

+5VALWP

PJ402

1

2

+3VALW

PAD-OPEN 4x4m
PJ403
1
2

+5VALW

PAD-OPEN 4x4m

[38] EN_5V

PR419
2

PR421
1

1

@

1

PC425
4.7U_0402_6.3V6M

2

@

1
PR423
402K_0402_1%

@

2

402K_0402_1%
2 PR422 1

4

2.2K_0402_5%

4.7U_0402_6.3V6M
PC421
2
1

2.2K_0402_5%

EN_3V [38]

2

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=1UH,Rentrip=64.9k ohm
Rdson=4.1~5.2m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*1UH)=6A
Vlimit=10*10^-6*64.9Kohm/10=0.0649V
Ilimit=0.0649/(5.2m*1.2)~0.0649/(4.1m)=10~13A
Iocp=16~19A

@

4

@

Compal Secret Data

Security Classification
2011/10/03

Issued Date

2012/10/19
check the EN circuit

2014/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.
PWR- 3VALWP/5VALWP

B

C

D

Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
E

43

of

53

A

B

C

D

0.75Volt +/- 5%
TDC A
Peak Current 1A
OCP Current A

PJ502
1
PL500
2

1

1.5V_B+

PR502 2

BOOT_1.5V

+1.5VP

2

JUMP_43X39
@

VLDOIN_1.5V

14

1UH_PCMB063T-1R0MS_12A_20%
PR503
7.87K_0402_1%
1
2

PL501

12

CS

VTTREF

3
4

VTTREF_1.5V

+1.5VP

6

1.5VP
TDC A
Peak Current 11.027 A
OCP current 13.36~18.27 A
TYP
MAX
H/S Rds(on) :11.7mohm , 14.5mohm
L/S Rds(on) :2.6mohm ,3.2mohm

2

PR509 change for HW power sequence 10/17/2012

PC515
@.1U_0402_16V7K

2

2

PR508
5.76K_0402_1%

S3_1.5V

1

1U_0402_6.3V6K

PR509
30K_0402_5%
1
2

PC517
0.1U_0402_10V7K

1

S5_1.5V
PC516

@
[10,25,38,39,44,46,47]
SUSP#
2

0_0402_5%

2

1

1

1.5V_B+

PR506
1M_0402_1%
1
2

2 @

PR505
5.9K_0402_1%
1
2

1

7

10

1

1.5V_FB

2

PC509
0.033U_0402_16V7K

220P_0402_50V8J
PC512

PC514
1U_0603_10V6K

PR507

2

VDDQ
FB

VDD

S3

PC511
1U_0603_10V6K

5

+5VALW

1

1

1
2

1

VDDP

S5

11

VDD_1.5V
1

@

GND

RT8207MZQW _W QFN20_3X3

TON

2

SI4634DY-T1-GE3_SO8

[38] SYSON

PC508
10U_0805_6.3V6M

21

2

1
2

20
VTT

19
VLDOIN

18

17

VTTSNS

8

8
7
6
5

4

1

PGND

PGOOD

+5VALW

2

1

PQ502
PR504
5.1_0603_5%

@

2

PAD

VTTGND

2

2

2

+

PC510
10U_0603_6.3V6M

@
1

CS_1.5V 13

1
2
3

+1.5VP

2
680P_0603_50V7K
4.7_1206_5%
PC513
PR501
2
1 SNUB_1.5V 2
1

1

LGATE

PU501

1

1
2
3

15

BOOT

PQ501

UGATE

1

DL_1.5V
4

SI4172DY-T1-GE3_SO8

PC507
10U_0805_6.3V6M

2

+0.75VSP

SW _1.5V

PC502
0.22U_0603_10V7K

9

@

8
7
6
5

1
2

2

1

PC505
0.1U_0402_25V6

1
2

DH_1.5V

PC506
2200P_0402_50V7K

@

PC504
4.7U_0805_25V6-K

1
2

1

PC503
4.7U_0805_25V6-K

PC524
68P_0402_50V8J
2
1

HCB2012KF-121T50_0805

PC501
330U_D2_2.5VY_R15M

2

2.2_0603_5%

16

1

PHASE

B+

1

+1.5VP
PJ503
2

STATE
S0
S3
S4/S5

S3
Hi
Lo
Lo

S5
Hi
Hi
Lo

3

VDDQ
VTTREF
VTT
On
On
On
On
On
Off (Hi-Z)
Off
Off
Off
(Discharge) (Discharge) (Discharge)

2

1

1

@ JUMP_43X79
PJ504
2

+1.5VP

2

+1.5V
1

1

@ JUMP_43X79
PJ505
1

+0.75VSP

1

2

2

+0.75VS

3

JUMP_43X39
@

+1.5VP OCP(min)=12.6A
2011_0801 JP504 form
43x118 change to 43x79

1

2

PR513
1M_0402_5%

1

1

1

PC519
68P_0402_50V8J
2
1

PC521
22U_0805_6.3V6M

SY8033BDBC_DFN10_3X3

2011_0801 JP505 form
43x118 change to 43x79

PJ507
1.8VSP_FB

+1.8VSP
1

1

2

0_0402_5%

PC523
0.1U_0402_10V7K

@

2

1
FB=0.6Volt

PR511
20K_0402_1%

2

EN_1.8VSP

@

+1.8VSP

2

2

6

1 2

FB
EN

11

PR512
1

3

PC520
22U_0805_6.3V6M

25,38,39,44,46,47] SUSP#

LX

1.8VSP_LX

SVIN

TP

5

PVIN

2

2

2

1

8

PC518
22U_0805_6.3VAM

LX

PC522
PR510
680P_0603_50V7K 4.7_1206_5%

9

@ JUMP_43X79

PVIN

NC

10

1.8VSP_VIN

1

1

PG

1

NC

2

7

2

PL502
1UH_PH041H-1R0MS_3.8A_20%
1
2

4

PU502
PJ506

+3VALW

2

2

1

1

+1.8VS

@ JUMP_43X79

PR514
10K_0402_1%

4

1.8VSP max current=4A

2

4

Compal Secret Data

Security Classification
Issued Date

2010/01/25

Deciphered Date

2010/12/31

Title

Compal Electronics, Inc.
PWR-+1.5VP/+1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
0.4

VIUS1

Tuesday, February 26, 2013
D

Sheet

44

of

53

5

VID [0]
0
0
1
1

4

VID[1]
0
1
0
1

3

2

VCCSA Vout
0.9V
0.85V
0.775V
0.75V

1

+VCC_SAP
TDC 2.9A
Peak Current 4A
OCP current 5.4A

D

D

output voltage adjustable network
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

+VCCSAP

C

5
6

+5VALW

7

[38] SA_PGOOD

PR612

1

2
1

PR611
1M_0402_1%

0_0402_5%

PC624
1U_0603_6.3V6M

2
2

1

PC629
1U_0603_6.3V6M
1
2

8

[46] 1.05VS_VCCP_PWRGOOD

1

GND
VIN

Vo

VPP

Vo

POK

D1

VEN/MODE

D0

G978F11U_SO8

+VCCSAP

4
3
2

2

1

2

PR621
0_0402_5%
1
@
1
@

PR622
0_0402_5%

H_VCCSA_VID1 [10]

H_VCCSA_VID0 [10]

0.9V

PC618
22U_0805_6.3V6M
1
2

@ JUMP_43X79

1

PU601
9

+1.05VS_VIN

PC616
22U_0805_6.3V6M
1
2

1

1

1

2

PC615
22U_0805_6.3V6M
1
2

PJ602
2

PC613
22U_0805_6.3V6M
1
2

+1.05VS

PR610
100K_0402_5%

2

@ JUMP_43X79
PC626
22U_0805_6.3V6M
2
1

PC628
22U_0805_6.3V6M
2
1

2

+3VS

+VCCSA

PJ601
2

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Date:
5

4

3

2

Compal Electronics, Inc.
PWR +VCCSAP

Size
C

Document Number

Rev
0.4

VIUS1
Wednesday, February 27, 2013
1

Sheet

45

of

53

5

4

3

2

1

D

D

2011_0801 del PJ705 and "+V1.05S_VCCP"

Ivy Bridge CPU ES2 Using
C

C

+1.05VS_VCCPP OCP(min)=15.76A

1

1

@

PC706
4.7U_0805_25V6-K
2
1

PC705
4.7U_0805_25V6-K
2
1

2
HCB2012KF-121T50_0805

B+

8

LX_1.05VS_VCCP

4

11

TPS51212DSCR_SON10_3X3

VFB=0.7V

PC710
1U_0603_10V6K

1
@

2

+5VALW
DL_1.05VS_VCCP

@

B

1
+

2

1
+

2

2011_0815 PC1166, PC1167
PC1168 change place
form"+1.05VS"
to"+1.05VS_VCCPP"

@ PR709
10_0402_5%
2
1

VSSIO_SENSE [9]

PR710
0_0402_5%

2

TP

6

1

V5IN
DRVL

7

PQ702

2

RF

SW

2

PC711
PR705
1000P_0603_50V7K 4.7_1206_5%

VFB

DRVH

SIRA10DP-T1-GE3_POWERPAK8-5

EN

+1.05VS

PL701

1

PC712
330U_D2_2V_Y

DH_1.05VS_VCCP

PC709
330U_D2_2V_Y

9

1UH_PCMB063T-1R0MS_12A_20%

1

PR704
PC707
2.2_0603_5% 0.22U_0603_16V7K
1
2
1
2
BST_1.05VS_VCCP

5

TRIP

VBST

3
2
1

PR708
470K_0402_1%
1
2

5
PR707
54.9K_0402_1%
2
1

1
2

4

PGOOD

2

2
3

PC701
.1U_0402_16V7K

2
PR706

1

TRIP_1.05VS_VCCP

@ 10K_0402_1%

[10,25,38,39,44,47] SUSP#

10

PU701

PR701
60.4K_0402_1%
1
2

@

3
2
1

1
1

B

4

1

2

[45] 1.05VS_VCCP_PWRGOOD

0_0402_5%

1

1

PR703

PC704
2200P_0402_50V7K
2
1

SIR472DP-T1-GE3_POW ERPAK8-5

PR702
100K_0402_5%

PC703
0.1U_0402_25V6
2
1

PQ701

2

2011_0801 mount
PR704, PR706

5

+3VS

PC702
68P_0402_50V8J
2
1

PL700
1.05VS_B+

2

PR711
4.99K_0402_1%

PR713 @
10_0402_5%
2
1

VCCIO_SENSE [9]

2

PR712
10K_0402_1%
A

A

Compal Secret Data

Security Classification
2010/01/25

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR +1.05VS_VCCPP

Size
Document Number
Custom
Date:

Rev
0.4

VIUS1

Tuesday, February 26, 2013

Sheet
1

46

of

53

A

 FM

 GN

 FN

 EI

 I

 H

 G

 F

 E

N

E

E

N

N

ETFNN

N

E

E

N

E

ETEKI

10K_0402_1%
2

10K_0402_1%
2

10K_0402_1%
2

PR811
1

PR812
1
GPU_VID0

10K_0402_1%
2
PR809
1

GPU_VID1

10K_0402_1%
2
PR808
1
GPU_VID4

PQ801

@

PR863

@

@

1

UGATE2_VGA

2

0_0603_5%

BOOT2_VGA

PC806
0.22U_0603_10V7K
1
2

BOOT2_2_VGA

PL802
0.36UH 20% PDME064T-R36MS1R405 24A
1
2

.1U_0402_16V7K
PHASE2_VGA

PR829
10K_0402_1%

1
2

PR828
3.65K_0402_1%
2
1

1
2

PC810
680P_0603_50V7K

PC813
22U_0805_6.3V6M

PC812
22U_0805_6.3V6M

@

5

PC842
.1U_0402_16V7K

Issued Date

2012/07/03

Deciphered Date

D

1
2
1

@

2

PR854
3.65K_0402_1%
2
1

PR853 @

PC837
330U_D2_2V_Y

4

ISEN2_VGA㗗⏎天≈

2013/07/03

Title

Date:

C

+

2

@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1

+

2

VSUM-_VGA
ISEN2_VGA
ISEN1_VGA

Compal Secret Data

Security Classification

2

1

Layout Note:
Place near Phase1 Choke

1

VSUM+_VGA
PC841
680P_0603_50V7K

3
2
1

VSUM-_VGA

4.7_1206_5%
2
1
SNUB1_VGA

1

LGATE1_VGA
PH802
10K_0402_1%_TSM0A103F34D1RZ

+VGA_CORE

PQ805

1

PR860
1.47K_0402_1%
1
2

PC831
10U_0805_25V6K
2
1

3
2
1

PL803
0.36UH 20% PDME064T-R36MS1R405 24A
1
2

PHASE1_VGA

4
PR857
11K_0402_1%
2
1

PC835
0.01U_0603_25V7K
2
1

PC834
0.22U_0603_10V7K
2
1

PC832
0.22U_0603_10V7K
1
2

PC830
10U_0805_25V6K

@
PR850
2.2_0603_5%
2
1 BOOT1_1_VGA

PC829
@ 2200P_0402_50V7K
2
1

4

2

PC828
0.1U_0402_25V6
2
1

PC844
68P_0402_50V8J
2
1

1

UGATE1_VGA

0_0603_5%

PR849 @
82.5_0402_5%
PC840 @
0.01U_0402_25V7K

VSUM_VGA_N001

1

PQ804

SIR472DP-T1-GE3_POWERPAK8-5
PR864

0_0402_5%

A

@

ISEN1_VGA㗗⏎天≈

+VGA_B+

2

1

2

3

SIRA10DP-T1-GE3_POWERPAK8-5

PR859

2

2

1
2
2

4

1

PC838
1000P_0402_50V7K

PC839 @
330P_0402_50V7K
2
1

PC833
330P_0402_50V7K

PR827 @
4.7_1206_5%
2
1
SNUB2_VGA

1
2

3
2
1
PC827
0.22U_0603_25V7K

PC826
1U_0603_10V6K
2
1

1
2

+5VS

2

0_0402_5%

2

VGA_IMVP_IMON

VSUM+_VGA

VSUM-_VGA
1

1

2

1

1

2

PR848
+VGA_CORE

+VGA_B+

+5VS

BOOT1_VGA

2

PR847
56K_0402_1%

0_0402_5%
1

@ 0_0402_5%
2

5

PR843

2
PR846
1_0402_5%
1
2

PC825
0.22U_0402_10V6K

ISEN1_VGA

2

PR844
267K_0402_1%

2

1

ISEN2_VGA

1

PC822
150P_0402_50V8J

2

2

PR841

VSEN_VGA

PC824
0.22U_0402_10V6K

2FB2_VGA1

2

ISL62883CHRTZ-T_TQFN40_5X5

VIN_VGA

1

2

2

PR842
1.69K_0402_1%
1
2

+

PC820
10U_0603_6.3V6M
2
1

390P_0402_50V7K

PC821
33P_0402_50V8J
1
2

PC815
1U_0603_10V6K

1

PC819
10U_0603_6.3V6M
2
1

PR840
PC817
499_0402_1%
2FB1_VGA1
2

2

PC818
10U_0603_6.3V6M
2
1

11
12
13
14
15
16
17
18
19
20

AGND

1

+5VS

PR851
2.61K_0402_1%~N
2
1
NTC_VGA

1

41

RTN_VGA
ISUM-_VGA

1
2

PC814
22P_0402_50V8J

PC816
1000P_0402_50V7K

PR839
8.06K_0402_1%
2
1

PR838 @
249K_0402_1%
1
2

COMP_VGA
FB_VGA
2ISEN3_VGA

1

1

VW_VGA

@

ISEN1_VGA

1

+

Near VGA Core

2

PH801

@

+VGA_CORE

30
29
28
27
26
25
24
23
22
21

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

PC823
2
1

470K_0402_5%_TSM0B474J4702RE
2
1
2

1
2
3
4
5
6
7
8
9
10

2

1

PC811
1U_0603_10V6K
1
2

.047U_0402_16V7K
1
2
PR845
11K_0402_1%

2

PR836 @
0_0402_5%

1

2

2
1

[24,38] VGA_AC_DET

PU801

PR830
1_0402_1%

VSUM-_VGA
VSUM+_VGA ISEN2_VGA

@

VDD_VGA

PR835
@ 100K_0402_5%
1
2

RBIAS_VGA

+3VS_VGA

4.02K_0402_1%

4
LGATE2_VGA

2
PR834
147K_0402_1%
2
1

PR837

0_0402_5%

VRON_VGA
GPU_VID6

PR833
100K_0402_5%
2

40
39
38
37
36
35
34
33
32
31

1

+3VS_VGA

[18,38] DGPU_PWROK

PR826

0_0402_5%

@

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

1

0_0402_5%

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

PR832

2

PR825

0_0402_5%

PSI#_VGA

@

PR831
2
1
1.91K_0402_1%

0_0402_5%

PR824

1

PR823

0_0402_5%

+VGA_CORE

PQ803

0_0402_5%

2

3

PR822

1

PR821

1

PR820
0_0402_5%

1

1

10K_0402_1%
+3VS_VGA

1

DPRSLPVR_VGA-1

SIRA10DP-T1-GE3_POWERPAK8-5

2

5

PR819

1

PC808
330U_D2_2V_Y

PR817
2.2_0603_5%
2
1

330U_D2_2V_Y
PC836

2

4

330U_D2_2V_Y
PC807

GPU_VID5

SUSP#

1

@

1

PR818 @
0_0402_5%
1
2

PC801

5

SIR472DP-T1-GE3_POWERPAK8-5
0_0402_5%

PR815

2
PR816
91K_0402_1%
1
2

[17,25,51] DGPU_PWR_EN

PR810
1
GPU_VID2

10K_0402_1%
2
PR807
1

2

@

1

NTLNN

2

NTLFI

N

1_0402_1%

NTLIN

E

N

1

N

E

E

B+

PR862
10K_0402_1%
PR856
2
1

E

N

E

2

@

N

E

E

PQ802B
2N7002KDWH_SOT363-6

PR861
10K_0402_1%

E

E

@
PQ802A
2N7002KDWH_SOT363-6

2

E

@

1

NTLKI

2

E

1

FBMA-L11-453215800LMA90T_2P

1

N

PL800

2

2

N

1

10K_0402_5%

PC805
10U_0805_25V6K
2
1

E

+VGA_B+

PR814

2

10K_0402_5%

PR855
10K_0402_1%

E

PR813

1

'(#7.6

PC804
10U_0805_25V6K

NTMNN

PC803
2200P_0402_50V7K
2
1

NTMFI

N

PC802
0.1U_0402_25V6
2
1

E

N

PC843
68P_0402_50V8J
2
1

E

N

@

5

NTMIN

E

E

@

3
2
1

N

N

E

@

+3VS_VGA

3

N

E

@

1

4

E

@

+3VALW

GPU_VID0
[24]

NTMKI

GPU_VID3

10K_0402_1%
2

ETNNN

E

GPU_VID5

10K_0402_1%
2

N

N

[10,25,38,39,44,46]

PR806
1
GPU_VID0

N

E

GPU_VID1
[24]

E

N

E

10K_0402_1%
2

E

N

E

E

@

ETNFI

E

E

1

N

PR805
1

ETNIN

GPU_VID1

ETNKI

N

GPU_VID2
[24]

E

E

10K_0402_1%
2

N

N

PR804
1
GPU_VID2

N

N

10K_0402_1%
2

N

E

PR803
1

E

GPU_VID3

ETENN

6

ETEIN
ETEFI

N

GPU_VID3
[24]

N
E

N

10K_0402_1%
2

E
E

N

PR802
1

E
E

N

PR801
1

E
E

E

N

E

+3VS_VGA

GPU_VID4

N
N

E

D



GPU_VID5

1

C

GPU_VID4
[24]

 FE

B

Compal Electronics, Inc.
VGA_COREP
Document Number

Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
E

47

of

53

4

PR910
6.04K_0402_1%

1

2200P_0402_50V7K

1

2

PC909
2

PR908
165K_0402_1%
PR911
2 SWN1A

1

CSREFA

0_0402_5%

PR932
10K_0402_5%

1

2

1

6132P_VCCP
PR929
2

LG1 [49]

PC918
2.2U_0603_10V7K
2
0_0402_5%
1

+5VS
SW1 [49]

BST1

HG1 [49]
1

2

1

BST1_1

2

PC920
0.1U_0603_50V_X7R

2

TSENSE

TSENSE

2 PC922
.1U_0402_16V7K

0_0402_5%
PR937

1

+5VS

SWN1 [49]

PH903
100K_0402_1%_TSM0B104F4251RZ

1

CSREF

2

6.49K_0402_1%
PC928
0.068U_0402_16V7K

2

PR945
866_0402_1%

1

PR941

1

CSP1
PC927
1000P_0402_50V7K

2

B

CSREF [49]

1

1

1

PR934
26.1K_0402_1%
2

2

2

2

CSSUM

1

2

PC931
.1U_0402_16V7K
1
2

2

PR946
27K_0402_1%

1

1

PC933
1000P_0402_50V7K
DROOP

SW1A [49]
LG1A [49]

PR930
2.2_0603_5%

1

1

CSCOMP

C

HG1A [49]

PR943
@ 8.25K_0402_1%

PR944
10K_0402_1%
PC929
0.033U_0402_16V7K

PR950
910_0402_1%

0.1U_0603_50V_X7R
2
BSTA1_1 1

2

1

FB_CPU2

2

2

PC915

2.2_0603_5%
1
2

CSP1

1

1

TRBST#

2

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA

PC923
10P_0402_50V8J

PR939
PC924
10_0402_1%
680P_0402_50V7K
PR942
PC926
1
2FB_CPU1 1
2
2
1COMP_CPU1 2
1
10_0402_1%
0.033U_0402_16V7K
1
2FB_CPU3 2
1
PR940
PC925
6.04K_0402_1%
2200P_0402_50V7K

B

BSTA1

100K_0402_1%_TSM0B104F4251RZ

PUT COLSE
TO V_GT
HOT SPOT

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

1

PR938
1K_0402_1%
1
2

CSCOMP

[9] VCCSENSE

PC921
1000P_0402_50V7K
VSP

ILIM_CPU
DROOP

PR935
0_0402_5%
2
1

VSN

2

1

PR933
0_0402_5%
2
1

[15] VGATE
[9] VSSSENSE

TRBST#
FB_CPU
COMP_CPU

2

[38] VR_HOT#

PR919
26.1K_0402_1%
2

PR921

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM

PR931
75_0402_1%
@

2

2

PC913
.1U_0402_16V7K

PH902

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

2

PC934
47P_0402_50V8J
@

1

1

+3VS

2

VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT NCP6132AMNR2G_QFN60_7X7
SW2
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1

IMVP_IMON
1
PR936
13K_0402_1%

+1.05VS

2

@

[9] VR_SVID_DAT
[9] VR_SVID_ALRT#
[9] VR_SVID_CLK

SWN1A [49]

PU901

PC914
1
2
6132_VCC
1
2.2U_0603_10V7K
2
3
PR923 0_0402_5%
4
2
1
VR_ON_CPU
[38] VR_ON
5
VR_SVID_DAT
PR926
VR_SVID_ALRT# 6
7
PR928
10K_0402_1% VR_SVID_CLK
8
1
2 VBOOT
95.3K_0402_1%
9
1
2
ROSC_CPU
10
1
2
VRMP
CPU_B+
11
VR_HOT#
12
PR927
VGATE
13
1K_0402_1%
14
15
PC919
DIFF_CPU
0.01U_0402_25V7K

2

1

PC917

.1U_0402_16V7K

PR924
54.9_0402_1%
1
2

1

2

1
2

PR922
130_0402_1%

PC916

C

.1U_0402_16V7K

+5VS

1

1

PR920
2_0603_5%
1
2

2

CSREFA [49]

CSP1A
TSENSEA

+1.05VS

PR913

1

6.49K_0402_1%

+5VS

DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA

PR917

CSP1A

2

1

D

0_0402_5%
PR912

PC910
0.068U_0402_16V7K

PC911
1000P_0402_50V7K

1

PC912
1000P_0402_50V7K

2

[10] VSS_AXG_SENSE

2
1
PR915
16.9K_0402_1%

2

0_0402_5%
1

1

PR914
2

CSREFA

TSENSEA

53.6K_0603_1%

[10] VCC_AXG_SENSE

2

2

COMPA1

NTC_PH203

1

PR909
1K_0402_1%

1

1

PC906
1000P_0402_50V7K

1

DROOPA

2

2

2

2

1

2

PC908
10P_0402_50V8J
2

1

1

CSCOMPA

1

PC907
470P_0402_50V7K
2

PR906
806_0402_1%

220K_0402_5%_ERTJ0EV224J

PR916
@ 8.25K_0402_1%

1

1

FBA2

PUT COLSE
TO GT
Inductor

PH901

1

PR907
10_0402_1%
2

1

1

CSCOMPA

2

26.7K_0402_1%
PR903
1K_0402_1%

PR902
10K_0402_1%
PC905
0.033U_0402_16V7K

D

2

2

2

1

FBA1

1

2

2

1

1

TRBSTA#

2

2

PR904

PR905
75K_0402_1%

1
1

1

1

2

FBA3

1

2

PC903
1200P_0402_50V7K

1

2

806 ohm

PC902
.1U_0402_16V7K

PC901
0.033U_0402_16V7K
2

CSSUMA

PR901
10_0402_1%

3

PC904
1000P_0402_50V7K

5

2

PC930
1200P_0402_50V7K

1

PUT COLSE
TO VCORE
Phase 1
Inductor

2

PR947

1

1000P_0402_50V7K
2NTC_PH201 1

PR948
75K_0402_1%

CSREF

䡢娵㗗⏎天ᶲ

PC932
2
1

2

SWN1

71.5K_0603_1%

㰺ᶲ䲬100⹎枪⇘
PUT COLSE
TO VCORE
HOT SPOT

2

PR949
165K_0402_1%

1
PH904
220K_0402_5%_ERTJ0EV224J

[38] IMVP_IMON
A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

2010/12/31

Deciphered Date

Compal Electronics, Inc.

Title

PWR-CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.4

VIUS1

Tuesday, February 26, 2013

Sheet
1

48

of

53

5

4

3

2

1

4

@
0_0603_5%

PC1005
2200P_0402_25V7K
2
1

2

PC1004
0.1U_0402_25V6
2
1

PQ1001
PR1003
1

[48] HG1

PC1003
10U_0805_25V6K
2
1

PC1001
68P_0402_50V8J
2
1

5

SIR472DP-T1-GE3_POWERPAK8-5

PC1002
10U_0805_25V6K
2
1

CPU_B+

FBMA-L11-453215800LMA90T_2P

B+

PL1003
1

2

CPU_B+

3
2
1

@

+CPU_CORE

2

4
5

5

1

[48] SW1
PQ1002

+
2

1
+
2

D

1

3

2

SIRA10DP-T1-GE3_POWERPAK8-5

2
PL1001
0.36UH_PDME104T-R36MS0R825_37A_20%

1SNUB_CPU1

CSREF [48]

@

ULV 17W CPU
VID1=0.9V
IccMax=33A
Icc_Dyn=28A
Icc_TDC=16A
R_LL=2.9m ohm

SWN1 [48]
PC1011
680P_0603_50V7K

2

4

3
2
1

3
2
1
@

SIRA10DP-T1-GE3_POWERPAK8-5

4

2

1

PQ1003
PR1001
4.7_1206_5%

[48] LG1

+

PC1010
33U_25V_M

DCR=0.779~0.861m ohm

+

PC1009
33U_25V_M

Choke PN:SH00000L400

PC1008
33U_25V_M

D

1
PC1006
33U_25V_M

1

@

C

C

PQ1004

@

PC1016
68P_0402_50V8J
2
1

PC1015
2200P_0402_25V7K
2
1

PC1014
0.1U_0402_25V6
2
1

PC1013
10U_0805_25V6K
2
1

5

SIR472DP-T1-GE3_POWERPAK8-5
B

PC1012
10U_0805_25V6K
2
1

CPU_B+

@

B

@

PR1004
[48] HG1A

1

2

4

Choke PN:SH00000L400

0_0603_5%
3
2
1

DCR=0.779~0.861m ohm
4

5

1

[48] SW1A

3

2

PL1002
0.36UH_PDME104T-R36MS0R825_37A_20%

1

SNUB_GFX1

@

CSREFA [48]

PC1017
SWN1A [48]

680P_0603_50V7K
2

3
2
1

SIRA10DP-T1-GE3_POWERPAK8-5

4

2

PQ1005
PR1002
4.7_1206_5%

[48] LG1A

+VCC_GFXCORE_AXG

1

@

ULV GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm

A

A

Compal Secret Data

Security Classification
Issued Date

2009/12/01

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

PWR-CPU_CORE
Size
Document Number
Custom
Date:

5

4

3

2

Rev
0.4

VIUS1

Tuesday, February 26, 2013
1

Sheet

49

of

53

4

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
1

2

1
PC1164
22U_0805_6.3V6M

2

PC1167
22U_0805_6.3V6M

2

1
PC1165
22U_0805_6.3V6M

2

1
PC1168
22U_0805_6.3V6M

2

PC1169
22U_0805_6.3V6M

2

+

2011_0815 PC714 change place
form "+1.05VS_VCCPP" to "+1.05VS"

1
PC1170
22U_0805_6.3V6M

2

+

1
2

1

1
2

2

@

1

1
+

PC1181

330U_D2_2VM_R9M
2

2

1

@
B

PC1180
10U_0603_6.3V6M

+CPU_CORE

2

PC1174
22U_0805_6.3V6M

@
PC1179
10U_0603_6.3V6M

PC1178
10U_0603_6.3V6M

PC1177
10U_0603_6.3V6M

@

1

@

2

@

2

1
PC1173
22U_0805_6.3V6M

2

2

1
PC1172
22U_0805_6.3V6M

PC1176
10U_0603_6.3V6M

2

1
PC1171
22U_0805_6.3V6M

PC1175
10U_0603_6.3V6M

1
B

1

@

2

@

1

PC1166
330U_V_2.5VM_R6M

1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2

1

1
2

2

2

1
2

1

PC1149
330U_D2_2V_Y

PC1148
330U_D2_2V_Y

PC1163
1U_0402_6.3V6K

PC1162
1U_0402_6.3V6K

PC1161
1U_0402_6.3V6K

PC1160
1U_0402_6.3V6K

PC1159
1U_0402_6.3V6K

PC1155
22U_0805_6.3V6M

C

PC1147
10U_0603_6.3V6M

PC1146
1U_0402_6.3V6K

PC1145
1U_0402_6.3V6K

PC1144
1U_0402_6.3V6K

1

1
2

1
2

1
2

1
2

2

1
1
2

1

1
2

2

1
2

1

PC1134
10U_0603_6.3V6M

PC1129
10U_0603_6.3V6M

PC1128
10U_0603_6.3V6M

PC1143
1U_0402_6.3V6K

2

PC1127
10U_0603_6.3V6M

2

1
PC1154
22U_0805_6.3V6M

PC1158
1U_0402_6.3V6K

2

1
PC1153
22U_0805_6.3V6M

PC1142
1U_0402_6.3V6K

2

1
PC1152
22U_0805_6.3V6M

2

PC1124
22U_0805_6.3V6M

2

1
PC1151
22U_0805_6.3V6M

1

+1.05VS

@
PC1157
1U_0402_6.3V6K

2

1
PC1150
22U_0805_6.3V6M

PC1141
1U_0402_6.3V6K

1

+
2

PC1156
1U_0402_6.3V6K

2

1

2

@

PC1140
1U_0402_6.3V6K

+

PC1139
1U_0402_6.3V6K

1

+CPU_CORE

2

1

PC1123
22U_0805_6.3V6M

@

PC1122
22U_0805_6.3V6M

+1.05VS
1
1

PC1138
1U_0402_6.3V6K

PC1137
1U_0402_6.3V6K

C

PC1136
1U_0402_6.3V6K

2

2011_0808 place power name
change form +V1.05S_VCCP
to +1.05VS
PC1121
22U_0805_6.3V6M

1

2

2
PC1135
1U_0402_6.3V6K

2

2

1

PC1115
22U_0805_6.3V6M

2

1

PC1114
22U_0805_6.3V6M

@

1

PC1120
10U_0603_6.3V6M

2

2

PC1119
10U_0603_6.3V6M

2

1

PC1118
22U_0805_6.3V6M

PC1133
10U_0603_6.3V6M

@

PC1132
10U_0603_6.3V6M

PC1131
10U_0603_6.3V6M

PC1130
10U_0603_6.3V6M

PC1126
10U_0603_6.3V6M

PC1125
10U_0603_6.3V6M

@

1

PC1117
22U_0805_6.3V6M

2

PC1116
22U_0805_6.3V6M

1

2

1

PC1113
22U_0805_6.3V6M

@

2

1

PC1112
22U_0805_6.3V6M

@

2

1

PC1111
22U_0805_6.3V6M

@

PC1108
2.2U_0402_6.3V6M

PC1110
22U_0805_6.3V6M

PC1107
2.2U_0402_6.3V6M

PC1109
22U_0805_6.3V6M

1
PC1106
2.2U_0402_6.3V6M

D

+VCC_GFXCORE_AXG

2

2

PC1105
2.2U_0402_6.3V6M

1

1
PC1104
2.2U_0402_6.3V6M

1

+VCC_GFXCORE_AXG

2

1
PC1103
2.2U_0402_6.3V6M

2

1
PC1102
2.2U_0402_6.3V6M

2

1
PC1101
2.2U_0402_6.3V6M

D

2

1
2

+CPU_CORE

2

1

+CPU_CORE

3

2

5

@

1
PC1182
330U_D2_2VM_R9M

+
2

PC1183
330U_D2_2VM_R9M

A

A

Compal Secret Data

Security Classification
2008/09/15

Issued Date

Deciphered Date

2009/09/15

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
PWR - PROCESSOR DECOUPLING
Document Number

Rev
0.4

VIUS1
Tuesday, February 26, 2013

Sheet
1

50

of

53

5

4

3

2

1

D

D

PR1230,PD1201 add for HW power sequence required 10/31/2012
PR1230
82K_0402_1%

PD1201
2

1 1

2

S SCH DIO RB751V40 SC76
PR1222
130K_0402_1%
1

2

EN_0.95V
PR1223
100K_0402_1%

PR1224
0_0402_5%
1

13

@

PC1212
22U_0805_6.3VAM

PC1211
22U_0805_6.3VAM
2
1

PC1210
22U_0805_6.3VAM
2
1

1
2

PC1209
22U_0805_6.3VAM
2
1

PC1213
22P_0402_50V8J
2
1

PR1226
19.1K_0402_1%
1
2

C

Ϭ͘ϴs
PR1228
100K_0402_1%
1

PR1229
182K_0402_1%
2
1

PC1216
3300P_0402_50V7K

2

1 1

PR1227
18K_0402_1%

@

1

1

9

+VGA_PCIEP

2

10

PC1214
680P_0402_50V7K

PR1225
4.7_0402_1%
2
1

11

2

RT/CLK

SS/TR

PL1201
1UH_PCMB042T-1R0MS_4.5A_20%
1
2

LX_0.95V

2

5

PH

12

2

BOOT

14

EN

PH

PU1202
TPS54618RTER_QFN16_3X3

GND
PWRPD

PH

8

GND

COMP

4
17

VIN

VSENSE

3

VIN

7

2

PWRGD

16
PC1208
10U_0805_6.3V6M

2

PC1205
0.22U_0603_10V7K
1
2

SNUB_0.95V

@

2

2

1

JUMP_43X79
@

1

1
1

1
PC1207
10U_0805_6.3V6M

1

PC1206
0.1U_0402_10V7K

2

15

VIN

PJ1202
2

AGND

+3VALW
C

2

@

6

1

2

PC1204
0.1U_0402_10V7K

PC1215
2200P_0402_50V7K

1

2

[17,25,47] DGPU_PW R_EN

PJ1203
2

+VGA_PCIEP

2

1

1

+0.95VS_VGA

JUMP_43X79
@

B

B

A

A

Compal Secret Data

Security Classification
2011/07/01

Issued Date

Deciphered Date

2012/07/01

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PWR-PROSESTOR
Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
1

51

of

53

5

4

3

2

9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP

D

5HDVRQIRUFKDQJH

3*

1

3DJHRI
IRU3:5

0RGLI\/LVW

'DWH

3KDVH



2012/06/05



2012/06/08



2012/06/08



2012/06/08

D





C

C








B

B




A

A

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2009/01/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PIR (PWR)
Rev
0.4

VIUS1
Sheet

Tuesday, February 26, 2013
1

52

of

53

1

2

3

4

5

9HUVLRQ&KDQJH/LVW 3,5/LVW
Phase

Date

No.

2011/09/13

No1

BOM

Sch
V

Layout
V

Description

function

Add C2325,C2326,C2327,C2328,C2329,R2319,R2324,Q2312

Add SBA function (+3VM) power

A

A

B

B

C

C

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/12

Deciphered Date

2012/07/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
1

2

3

4

PIR (EE)
Rev
0.4

LA-8133P

Tuesday, February 26, 2013
5

Sheet

53

of

53

www.s-manuals.com

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Producer                        : Acrobat Distiller 9.0.0 (Windows)
Modify Date                     : 2015:11:07 00:40:08+02:00
Create Date                     : 2014:08:05 22:01:11+07:00
Creator Tool                    : PScript5.dll Version 5.2.2
Metadata Date                   : 2015:11:07 00:40:08+02:00
Document ID                     : 37b4a7f8-833a-11e2-0000-15d267537a69
Instance ID                     : uuid:698ee1da-444a-401f-8928-6b4826ea5c03
Format                          : application/pdf
Title                           : Compal LA-9611P - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Compal LA-9611P - Schematics. www.s-manuals.com.
Chinafix 0020logo               : {224EA6EC-17AD-4650-AA0B-2DA64735702B}
Chinafix 3                      : {93BAAD10-9EAC-4803-843E-B4EF98EADCE7}
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Compal LA 9611P Schematics. Www.s Manuals.com. R0.4 Schematics

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