Compal LA 9866P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-9866P VSKAA - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 58
| Download | |
| Open PDF In Browser | View PDF |
A
B
C
D
E
1
1
Compal Confidential
VSKAA Schematics Document
2
2
Haswell with DDR3L + Lynx Point PCH
nVIDIA N14P-GV2 (Dual Rank)
nVIDIA N14M-GL
LA-9866P REV 1.0 Schematic
3
3
Intel Processor (Haswell) / PCH(Lynx Point)
2013-04-28 Rev 1.0
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
1
of
57
A
B
C
D
VGA (DDR3)
Intel CPU
Memory BUS(DDR3L) 204pin DDR3-SO-DIMM X2
Haswell (37W)
Dual Channel
PCI-Express 4X Gen3 8GT/s
nVIDIA N14P-GV2 & N14M-GL
rPGA946
37.5mm x 37.5mm
page 13,14,15,16,17,18,19,20,21
LVDS Conn.
Colay eDP
LVDS Translator
RTD2132R (Single)
page 23
page 11,12
BANK 0, 1, 2
eDP 1X 5.4GT/s
1
E
1
1.35V DDR3L 1333/1600 MT/s
page 5,6,7,8,9,10
GCLK
SLG3NB304VTR
page 22
FDI X2
2.7GT/s
page 38
DMI X4
5GT/s
None 4K2K
Support 4K2K
HDMI Conn.
USB30 2x
HDMI Re-driver
PS8201&PS8401
page 25
page 24
Intel PCH
Lynx Point
HM86
PCIe Gen1 1x
PCIeMini Card
port 4
WLAN PCIe
page 38
1.5V 5GT/s
PCIeMini Card
USB20 port 9
WIMAX page
38
USB20 1x
LAN (Port 3)+USB (Port 2)/B
RTL8106E/RTL8111G
SATA ODD
Power/B
USB20 port 3
page 40
Touch Screen
USB20 1x
5V 480MHz
SATA Gen3 port 4
USB20 port 8
page 23
Int. Camera
USB20 1x
5V 480MHz
USB20 port 11
page 23
SATA Gen2 port 2
SATA port 2 5V 6GHz(600MB/s)
page 37
CRT
page 27,28,29,30,31,32,33,34,35,36
page 39
3
5V 480MHz
FCBGA 695Balls
20mm x 20mm
5V 480MHz
2
CardReader GL834L
USB20 1x
SATA port 4 5V 6GHz(600MB/s)
page 37
Sub Boards
USB20 port 0,1
USB30 port 1,2
page 41
5V 480MHz
2
SATA HDD
USB Right
5V 5GT/s
USB20 2x
page 26
3
page 44
SPI ROM
8MB
RTC CKT.
page 27
page 30
Debug Port
LPC BUS
HD Audio
3.3V 33 MHz
3.3V 24MHz
HDA Codec
KB9012
page 45
ALC259 (w/o S&M)
ALC269 (w/ S&M)
page 44
page 42
DC/DC Interface CKT.
page 46
Touch Pad
page 45
Int.KBD
page 45
G-Sensor
page 37
SPK Conn
JLINE & JEXMIC
page 43
Power Circuit DC/DC
page 43
page 47,48,49,50,51,52,53,54,55
4
4
Power On/Off CKT.
page 45
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Block Diagram
Document Number
Rev
1.0
VSKAA
Thursday, May 09, 2013
Sheet
E
2
of
57
5
4
3
DESIGN CURRENT 0.1A
2
1
+3VL
B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7
DESIGN CURRENT 5A
+5VALW
D
D
SUSP#
DESIGN CURRENT 4A
+5VS
DESIGN CURRENT 5A
+3VALW
TPS22966
Ipeak=5A, Imax=3.5A, Iocp min=6.2A
RT8243AZQW
WOL_EN#
P-CHANNEL
AO-3413
SUSP#
DESIGN CURRENT 330mA
DESIGN CURRENT 4A
TPS22966
+3V_LAN
+3VS
LCD_ENVDD
DESIGN CURRENT 1.5A
+LCD_VDD
DESIGN CURRENT 60mA
+3VS_DGPU
APL3512
DGPU_PWR_EN
C
P-CHANNEL
AO-3413
DESIGN CURRENT 2A
C
+3V_WLAN
PJ6
VR_ON
DESIGN CURRENT 55A
+CPU_CORE
TPS51631
SUSP#
B
TPS51212
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A
+1.05VS_VCCP
B
VGA_PWROK
DESIGN CURRENT 60mA
P-CHANNEL
AO-3416
+1.05VS_DGPU
SUSP#
DESIGN CURRENT 2A
TPS51212
+1.5VS
VGA_PWROK
DESIGN CURRENT 8.6A
N-CHANNEL
+VRAM_1.5VS
FDS6676AS
SYSON
RT8207M
Ipeak=15A, Imax=10.5A, Iocp min=18A
0.675VR_EN
DESIGN CURRENT 10A
DESIGN CURRENT 1.5A
+1.35V
+0.675VS
A
A
DGPU_PWR_EN
NCP81172
Ipeak=33.8A, Imax=23.4A, Iocp min=40A
DESIGN CURRENT 20.5A
+VGA_CORE
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Power Tree
Document Number
Rev
1.0
VSKAA
Thursday, May 09, 2013
1
Sheet
3
of
57
A
B
( O MEANS ON
Voltage Rails
+RTCVCC
C
X MEANS OFF )
B+
Platform
+5VL
+5VALW
+3VL
+3VALW
+1.35V
SKU
CPU
+5VS
+3VS
+1.8VS
+VSB
power
plane
D
E
VGA
PCH
Ivy Bridge i3
HM77C1(HM77@)
(CPUI3@)
nVIDIA N13P-GL
Ivy Bridge i5 HM77C1_R1(HM77R1@) (N13PGL@)
HM77C1_R3(HM77R3@)
(CPUI5@)
Chief River
+1.5VS
+CPU_CORE
+VGA_CORE
1
+VRAM_1.5VS
BTO Option Table
+3VS_DGPU
SKU
Function
+1.05VS_DGPU
1
MIC
LAN
description
State
explain
BTO
2
S0
O
O
O
O
O
O
S1
O
O
O
O
O
O
S3
O
O
O
O
O
X
O
O
O
O
X
X
S5 S4/AC
Function
2
description
S5 S4/ Battery only
O
O
O
X
X
X
explain
S5 S4/AC & Battery
don't exist
O
X
X
X
X
X
BTO
Function
PCH SM Bus Address
description
explain
Power
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
BTO
Function
description
3
3
explain
BTO
EC SM Bus1 Address
Power
Device
HEX
EC SM Bus2 Address
Address
Power
Device
HEX
Address
+3VL
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
+3VL
Smart Charger
12 H
0001 0010 b
+3VS
NVIDIA GPU
9E H
1001 1010 b
Power
Device
HEX
Address
SIGNAL
STATE
SLP_S3# SLP_S4# SLP_S5#
HIGH
HIGH
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
HIGH
Full ON
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Notes List
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
4
of
57
A
B
C
D
E
+VCCIO_OUT
RC44 2
RC45 2
1 62_0402_5%
H_PROCHOT#
1 10K_0402_5%
H_PWRGOOD
H_DRAMRST#
@
1
2
CC34
180P_0402_50V8J
by ESD requestion and place near CPU
If no use eDP, please stuff them.
DDR3 Compensation CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
Haswell rPGA EDS
JCPUB
AP32
TP@
<44,47>
1
H_PROCHOT#
H_CATERR#
H_PECI
PAD
H_PECI
RC60
<33>
H_THERMTRIP#
<28>
<33>
<28>
<33>
H_PM_SYNC
H_PWRGOOD
DRAMPWROK
CPU_PLTRST#
2
H_PROCHOT#_R
56_0402_5%
AN32
AR27
AK31
AM30
AM35
SKTOCC
CATERR
PECI
FC_AK31
PROCHOT
THERMTRIP
THERMAL
T2
<44>
MISC
DRAMPWROK
ESD@
100P_0402_50V8J
H_PWRGOOD
CC63
AT28
AL34
AC10
AT26
H_PM_SYNC
H_PWRGOOD
DRAMPWROK
CPU_PLTRST#
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN
PWR
1 CC62
JTAG
@
1000P_0402_50V7K 2
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST
DDR3
1
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
@
1 CC70
H_PECI
1 CC67
H_PM_SYNC
135 MHz
@
1000P_0402_50V7K 2
@
1000P_0402_50V7K 2
100P_0402_50V8J
2
1 CC66
CPU_PLTRST#
135 MHz
100 MHz
<29>
<29>
<29>
<29>
<29>
<29>
CLK_CPU_EDP#
CLK_CPU_EDP
CLK_CPU_SSC_EDP#
CLK_CPU_SSC_EDP
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_SSC_EDP#
CLK_CPU_SSC_EDP
G28
H28
F27
E27
D26
E26
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP
Conn@
@ESD@
1
2 CC2
CLOCK
1000P_0402_50V7K 2
INTEL_HASWELL_HASWELL
PRDY
PREQ
TCK
TMS
TRST
TDI
TDO
DBR
AP3
AR3
AP2
AN3
RC56 1
RC59 1
RC61 1
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
H_DRAMRST#
H_DRAMRST#
AR29 XDP_PRDY#
AT29 XDP_PREQ#
AM34 XDP_TCLK
AN33 XDP_TMS
AM33 XDP_TRST#
AM31 XDP_TDI
AL33 XDP_TDO
AP33 XDP_DBRESET#
AR30
AN31
AN29
AP31
AP30
AN28
AP29
AP28
1
2 100_0402_1%
2 75_0402_1%
2 100_0402_1%
PAD
PAD
T42 TP@
T43 TP@
PAD
T19 TP@
PAD
T18 TP@
PAD
T35 TP@
<11>
Close to CPU side
@ESD@
1
2
XDP_DBRESET#
CC3
100P_0402_50V8J
2 OF 9
H_THERMTRIP#
XDP Connector reserve test point
Please place near JCPU
2
PU/PD for JTAG signals
+1.05VS_VCCP
SM_DRAMPWROK for nonsupport Deep S3
1
+1.35V
XDP_TDO
RC49 1
2 51_0402_1%
XDP_TCLK
RC42 1
2 51_0402_1%
XDP_TRST#
RC41 1
2 51_0402_1%
RC16
2
1.8K_0402_1%
+1.05VS_VCCP
DRAMPWROK
ESD@
1
100P_0402_50V8J
CC68
ESD@
RC14
100P_0402_50V8J
3.3K_0402_1%
CC69
ESD@
2
100P_0402_50V8J
CC83
3
3
Buffered Rest to CPU
FAN Control Circuit
1
+3VS
R2
10K_0402_5%
JFAN Conn@
2
6
5
4
3
2
1
<44>
<44>
FAN_SPEED1
1
2
+FAN1
C4
0.01U_0402_25V7K
@
G6
G5
4
3
2
1
ACES_50273-0040N-001
1
+5VS
FANPWM
R1
1
Rshort@
1
2 +FAN1
0_0603_5%
D1
BAS16_SOT23-3
C5
2
1A
4
2012/04/19
Issued Date
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2
10U_0603_6.3V6M
2015/04/19
Deciphered Date
Title
Haswell_JTAG/XDP/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
5
of
57
A
B
C
D
E
1
+VCOMP_OUT
RC1
24.9_0402_1%
Haswell rPGA EDS
<28>
<28>
<28>
<28>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
<28>
<28>
<28>
<28>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<28>
<28>
<28>
<28>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<28>
<28>
FDI_CSYNC
FDI_INT
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
DISP_INT
FDI
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
DMI
<28>
<28>
<28>
<28>
PEG
1
2
PEG_RCOMP
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
E23
M29
K28
M31
L30
M33
L32
M35
L34
E29
D28
E31
D30
E35
D34
E33
E32
L29
L28
L31
K30
L33
K32
L35
K34
F29
E28
F31
E30
F35
E34
F33
D32
H35
H34
J33
H32
J31
G30
C33
B32
B31
A30
B29
A28
B27
A26
B25
A24
J35
G34
H33
G32
H31
H30
B33
A32
C31
B30
C29
B28
C27
B26
C25
B24
PEG_COMP
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
2
JCPUA
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PCIE_GTX_C_CRX_N[0..3]
<13>
1
PCIE_GTX_C_CRX_P[0..3]
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
<13>
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
CC8
CC11
CC16
CC20
1
1
1
1
2
2
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N[0..3]
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
CC10
CC5
CC6
CC7
1
1
1
1
2
2
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P[0..3]
<13>
2
<13>
3
3
Conn@
INTEL_HASWELL_HASWELL
1 OF 9
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Haswell_DMI/PEG/FDI
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
6
of
57
A
<11>
B
C
DDR_A_D[0..63]
<12>
D
E
DDR_B_D[0..63]
Haswell rPGA EDS
JCPUC
Haswell rPGA EDS
1
1
JCPUD
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
2
3
+V_SM_VREF
+VREF_DQA_M3
+VREF_DQB_M3
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AN9
AM8
AN8
AR9
AT9
AR8
AT8
AJ9
AK9
AJ6
AK6
AJ10
AK10
AJ7
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
E12
D12
B11
A11
E11
D11
B12
A12
AM3
F16
F13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
RSVD
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
AC7
U4
V4
AD9
U3
V3
AC9
U2
V2
AD8
U1
V1
AC8
M7
L9
M9
M10
M8
L7
L8
L10
V5
U5
AD1
V10
U6
U7
U8
V8
AC6
V9
U9
AC5
AC4
AD6
AC3
AD5
AC2
V6
AC1
AD4
V7
AD3
AD2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AP15
AP8
AJ8
AF3
J3
E2
C5
C11
AP14
AP9
AK8
AG3
H3
E3
C6
C12
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDRA_CLK0#
DDRA_CLK0
DDRA_CKE0
DDRA_CLK1#
DDRA_CLK1
DDRA_CKE1
<11>
<11>
<11>
<11>
<11>
<11>
DDRA_SCS0#
DDRA_SCS1#
<11>
<11>
DDRA_ODT0
DDRA_ODT1
<11>
<11>
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
<11>
<11>
<11>
DDR_A_RAS# <11>
DDR_A_WE# <11>
DDR_A_CAS# <11>
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
<11>
<11>
<11>
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AT5
AT6
AN5
AN6
AJ4
AK4
AJ1
AJ2
AM1
AN1
AK2
AK1
L2
M2
L4
M4
L1
M1
L5
M5
G7
J8
G8
G9
J7
J9
G10
J10
A8
B8
A9
B9
D8
E8
D9
E9
E15
D15
A15
B15
E14
D14
A14
B14
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
Conn@
Conn@ INTEL_HASWELL_HASWELL
RSVD
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2
AA2
AG9
Y1
AA1
AF9
P4
R2
P3
P1
R4
R3
R1
P2
R7
P8
AA9
R10
R6
P6
P7
R8
Y5
Y10
AA5
Y7
AA6
Y6
AA7
Y8
AA10
R9
Y9
AF7
P9
AA8
AG7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AP18
AP11
AP5
AJ3
L3
H9
C8
C14
AP17
AP12
AP6
AK3
M3
H8
C9
C15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDRB_CLK0#
DDRB_CLK0
DDRB_CKE0
DDRB_CLK1#
DDRB_CLK1
DDRB_CKE1
<12>
<12>
<12>
<12>
<12>
<12>
DDRB_SCS0#
DDRB_SCS1#
<12>
<12>
DDRB_ODT0
DDRB_ODT1
<12>
<12>
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
<12>
<12>
<12>
DDR_B_RAS# <12>
DDR_B_WE# <12>
DDR_B_CAS# <12>
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
2
<12>
<12>
<12>
3
INTEL_HASWELL_HASWELL 4 OF 9
3 OF 9
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Haswell_DDR3
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
7
of
57
A
B
C
D
E
1
1
COMPENSATION PU FOR eDP
1
+VCOMP_OUT
T28
U28
T30
U30
U29
V29
U31
V31
H_HDMI_TX2H_HDMI_TX2+
H_HDMI_TX1H_HDMI_TX1+
H_HDMI_TX0H_HDMI_TX0+
H_HDMI_TXCH_HDMI_TXC+
T34
U34
U35
V35
U32
T32
U33
V33
2
P29
R29
N28
P28
P31
R31
N30
P30
DDIB_TXBN_0
DDIB_TXBP_0
DDIB_TXBN_1
DDIB_TXBP_1
DDIB_TXBN_2
DDIB_TXBP_2
DDIB_TXBN_3
DDIB_TXBP_3
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
EDP_DISP_UT IL
DDIC_TXCN_0
DDIC_TXCP_0
DDIC_TXCN_1
DDIC_TXCP_1
DDIC_TXCN_2
DDIC_TXCP_2
DDIC_TXCN_3
DDIC_TXCP_3
DDID_TXDN_0
DDID_TXDP_0
DDID_TXDN_1
DDID_TXDP_1
DDID_TXDN_2
DDID_TXDP_2
DDID_TXDN_3
DDID_TXDP_3
INTEL_HASWELL_HASWELL
P35
R35
N34
P34
P33
R33
N32
P32
H_EDP_AUXN
H_EDP_AUXP
<22>
<22>
EDP_RCOMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
H_EDP_TXN0 <22>
H_EDP_TXP0 <22>
H_EDP_TXN1 <22>
H_EDP_TXP1 <22>
FDI_CTX_PRX_N0 <28>
FDI_CTX_PRX_P0 <28>
FDI_CTX_PRX_N1 <28>
FDI_CTX_PRX_P1 <28>
2
DDI
+VCCIO_OUT
RC5
10K_0402_5%
8 OF 9
2
Conn@
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
M27
N27
P27 H_EDP_HPD#
E24 EDP_RCOMP
R27
PAD T12 TP@
1
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
RC2
24.9_0402_1%
JCPUH
2
Haswell rPGA EDS
H_EDP_HPD
2
IN
3
<22,23>
GND
OUT
1
H_EDP_HPD#
QC1
DTC124EKAT146_SC59-3
3
3
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Haswell_DDI/eDP
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
8
of
57
A
B
C
D
E
+CPU_CORE
Haswell rPGA EDS
JCPUE
1
VCC_SENSE
VDDQ DECOUPLING
+1.35V
K27
L27
T27
V27
+CPU_CORE
<10,54,9>
VSSSENSE
CC52
2
1
VCCSENSE
1
1
CC54
2
1
CC55
2
1
CC56
2
1
CC57
2
1
CC58
2
1
CC59
2
1
CC60
2
1
CC61
2
1
2
CC53
AB11
AB2
AB5
AB8
AE11
AE2
AE5
AE8
AH11
K11
N11
N8
T11
T2
T5
T8
W11
W2
W5
W8
VCCSENSE
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
VSSSENSE
VSSSENSE
<10,54,9>
1
RC95
100_0402_1%
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
CC64
1
CC73
2
Close to CPU
1
CC74
2
1
2
CC75
1
CC76
2
1
CC77
2
1
2
CC78
1
2
CC79
1
CC80
2
1
2
CC81
1
2
CC82
1
2
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2
N26
K26
AL27
AK27
+CPU_CORE
Reserve 0.1u to avoid noise
+VCCIO_OUT
0.1U_0402_10V7K
1
2
CC50
@
<54>
<54>
<54>
VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DAT
RC91
130_0402_5%
+VCOMP_OUT
+1.05VS_VCCP
2
2
RC89
75_0402_5%
RC96 1
RC88 1
RC92 1
T13 PAD
TP@
AL35
E17
AN35
A23
F22
W32
AL16
J27
AL13
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
AM28
AM29
AL28
VCCSENSE
+VCCIO_OUT
1
1
+VCCIO_OUT
0.1U_0402_10V7K
1
2
CC49
@
+VCCIO_OUT
@
2 43_0402_1% H_CPU_SVIDALRT#
2 0_0402_5%
H_CPU_SVIDCLK
Rshort@
2 0_0402_5%
H_CPU_SVIDDAT
Rshort@
1
RC10
RSVD
RSVD
RSVD
RSVD
+1.35V
47U_0805_6.3V6M
2
<54>
CC51
1
Reserve short pad on power side
RC93
100_0402_1%
2
2
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
0_0603_5%
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
Pull high resistor on VR side
TP@T57
TP@
T57 PAD
TP@T14
TP@T14
TP@T15
TP@
T15
TP@T16
TP@
T16
TP@T17
TP@
T17
PAD
PAD
PAD
PAD
3
AP35
H27
AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
+CPU_CORE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
4.2A
RSVD
VCC
RSVD
RSVD
VCC
55A
VCC_SENSE
RSVD
VCCIO_OUT
RSVD
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Conn@
VCC
VCC
VCC
VCC
VCC
VCC
INTEL_HASWELL_HASWELL
1
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
2
3
U25
U26
V25
V26
W26
W27
5 OF 9
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Haswell_POWER
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
9
of
57
D
E
CFG Straps for Processor
Haswell rPGA EDS
JCPUG
(CFG[17:0] internal pull high 5~15K to VCCIO)
JCPUI
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
RSVD
CFG2
TP@T20
TP@T20
TP@T21
TP@
T21
PAD
PAD
AT1
AT2
AD10
TP@T22
TP@T22
TP@T23
TP@
T23
PAD
PAD
A34
A35
TP@T24
TP@T24
TP@T25
TP@
T25
PAD
PAD
W29
W28
G26
W33
AL30
AL29
F25
CPU_TESTLO_G26
+CPU_CORE
TP@T26
TP@T26
TP@T27
TP@
T27
PAD
PAD
C35
B35
TP@T28
TP@
T28
PAD
AL25
TP@T29
TP@T29
TP@T30
TP@
T30
PAD
PAD
W30
W31
W34
CPU_TESTLO
TP@T41
TP@T41
TP@T44
TP@
T44
AT20
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25
PAD
PAD
CFG2
TP@T40
TP@
T40
PAD
CFG4
CFG5
CFG6
Conn@
1
RC100
1
RC101
1
RC102
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
TESTLO_G26
RSVD
RSVD
RSVD
VCC
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
TESTLO
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
FC_G6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
RSVD
RSVD
NC
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
VSS
VSS
INTEL_HASWELL_HASWELL
C23
B23
D24
D23
PAD
PAD
PAD
PAD
T31 TP@
T32 TP@
T33 TP@
T34 TP@
PAD
PAD
PAD
PAD
T53 TP@
T54 TP@
T55 TP@
T56 TP@
PAD
T39 TP@
RC79
1K_0402_1%
@
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
AT31
AR21
AR23
AP21
AP23
1
CFG_RCOMP
AR33
G6
AM27
AM26
F5
AM2
K6
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
*
1: Normal Operation; Lane # definition
matches socket pin map definition
0:Lane Reversed
CFG4
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B34
B4
B7
C1
C10
C13
C16
C19
C2
C22
C24
C26
C28
C30
C32
C34
C4
C7
D10
D13
D16
D19
D22
D25
D27
D29
D31
D33
D35
D4
D7
E1
E10
E13
E16
E4
E7
F10
F11
F12
F14
F15
F17
F18
F20
F21
F23
F24
F26
F28
F30
F32
F34
F4
F6
F7
F8
F9
G1
G11
G2
G27
G29
G3
G31
G33
G35
G4
G5
H10
H26
H6
H7
J11
J26
J28
J30
J32
J34
J6
K1
E18
RC82
1K_0402_1%
U10
P10
B1
A2
AR1
PAD
T36 TP@
E21
E20
PAD
PAD
T37 TP@
T38 TP@
Embedded Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
AP27
AR26
CFG4
AL31
AL32
*
0 : Enabled; An external Display Port
device is connected to the Embedded
Display Port
2 CPU_TESTLO_G26
49.9_0402_1%
2
CPU_TESTLO
49.9_0402_1%
2
CFG_RCOMP
49.9_0402_1%
3
VSSSENSE
<54,9>
CFG6
CFG5
INTEL_HASWELL_HASWELL 6 OF 9
INTEL_HASWELL_HASWELL 7 OF 9
Conn@
RC83
1K_0402_1%
@
RC84
1K_0402_1%
@
2
Conn@
2
9 OF 9
1
3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22
2
1
A10
A13
A16
A19
A22
A25
A27
A29
A3
A31
A33
A4
A7
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AJ5
AK11
AK25
AK26
AK28
AK29
AK30
AK32
E19
1
Haswell rPGA EDS
JCPUF
C
1
Haswell rPGA EDS
B
2
A
PCIE Port Bifurcation Straps
*
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2
disabled
10: x8, x8 - Device 1 function 1 enabled;
function 2 disabled
01: Reserved - (Device 1 function 1 disabled;
function 2 enabled)
4
4
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
Haswell_GND/RSVD/CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
10
of
57
A
B
JDDR3L
CD1
DDR_A_D0
DDR_A_D1
1
0.1U_0402_10V7K
2
DDR_A_D2
DDR_A_D3
Close to JDDR3L.1
1
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
<7>
<7>
DDRA_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
2
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<7>
<7>
DDRA_CLK0
DDRA_CLK0#
DDR_A_MA10
<7>
DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_MA13
<7>
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
3
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
+3VS
CD26
1
2
4
0.1U_0402_10V7K
DDR_A_D58
DDR_A_D59
+0.675VS
D
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR3 SO-DIMM A
Reverse Type
H=4.0mm
DDR_A_DQS[0..7]
<7>
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
DDR_A_D6
DDR_A_D7
<7>
<7>
DDR_A_MA[0..15]
<7>
DDR_A_D12
DDR_A_D13
1
SM_DRAMRST#
+1.35V
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
2
+VREF_DQA
C
+1.35V
RC80
@ 1K_0402_5%
DDR_A_D22
DDR_A_D23
1
+1.35V
RC78
<12>
DDR_A_D28
DDR_A_D29
SM_DRAMRST#
SM_DRAMRST#
2
1
H_DRAMRST#
<5>
SM_DRAMRST#
1K_0402_5%
1
CD2
DDR_A_DQS#3
DDR_A_DQS3
2
100P_0402_50V8J
@ESD@
DDR_A_D30
DDR_A_D31
DDRA_CKE1
<7>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
2
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1
<7>
+V_SM_VREF_CNT
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
CD16
1
0.1U_0402_10V7K
2
3
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
close to JDDR3L.126
Layout Note:
Place near JDDR3L
DDR_A_D52
DDR_A_D53
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA
Layout Note:
Place near JDDR3L.203 and 204
+1.35V
DDR_A_D54
DDR_A_D55
+1.35V
+0.675VS
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_SMBDATA <12,30,38,45>
PM_SMBCLK <12,30,38,45>
+0.675VS
CD8
1
2 10U_0603_6.3V6M
CD9
1
2 10U_0603_6.3V6M
CD10 1
2 10U_0603_6.3V6M
CD11 1
2 10U_0603_6.3V6M
CD13 1
2 10U_0603_6.3V6M
CD14 1
2 10U_0603_6.3V6M
CD17 1
2 1U_0402_6.3V6K
CD18 1
2 1U_0402_6.3V6K
CD19 1
2 1U_0402_6.3V6K
CD20 1
2 1U_0402_6.3V6K
CD24 2
1 1U_0402_6.3V6K
CD21 2
1 1U_0402_6.3V6K
206
LCN_DAN06-K4406-0103_204P
4
Conn@
SPD setting (SA0, SA1)
PU/PD by Channel A/B
->Channel A 00
->Channel B 01
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDRIII-SODIMM0
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
11
of
57
A
B
+1.35V
C
D
E
+1.35V
JDDR3H
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_MA[0..15]
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
All VREF traces should have 20 mil trace width
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
+1.35V
DDR_B_D30
DDR_B_D31
RC121
1K_0402_1%
DDR_B_MA3
DDR_B_MA1
<7>
<7>
DDRB_CLK0
DDRB_CLK0#
DDR_B_MA10
<7>
DDR_B_BS0
<7>
<7>
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
<7>
DDRB_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
3
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+3VS
1
RD15 1
10K_0402_5%
2
+0.675VS
205
4
CD49
2
0.1U_0402_10V7K
G1
G2
<7>
2
DDRB_CKE1
2 2_0402_1%
RC1881
DDR_B_MA11
DDR_B_MA7
@
DDR_B_MA6
DDR_B_MA4
CC71
0.022U_0402_25V7K
RC8
24.9_0402_1%
@
DDR_B_MA2
DDR_B_MA0
@
RC110
1K_0402_1%
2 2_0402_1%
CC72
0.022U_0402_25V7K
RC9
24.9_0402_1%
@
+V_SM_VREF_CNT
RC120
1K_0402_1%
+V_SM_VREF
RC1891
1
RC1871
DDR_B_MA15
DDR_B_MA14
+1.35V
@
RC111
1K_0402_1%
2 2_0402_1%
CC65
0.022U_0402_25V7K
RC3
24.9_0402_1%
@
2
DDR_B_MA8
DDR_B_MA5
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1
DDR_B_MA12
DDR_B_MA9
2
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
+VREF_DQB
RC122
1K_0402_1%
+VREF_DQB_M3
2
DDR_B_BS2
+1.35V
1
DDRB_CKE0
1 2
<7>
+VREF_DQA
2
<7>
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
<7>
DDR_B_D14
DDR_B_D15
+VREF_DQA_M3
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
<7>
<11>
1
DDR_B_D18
DDR_B_D19
DDR_B_D[0..63]
SM_DRAMRST#
<7>
<7>
2
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS[0..7]
1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#[0..7]
DDR_B_D12
DDR_B_D13
2
RC109
1K_0402_1%
2
DDR_B_D10
DDR_B_D11
DDR_B_D6
DDR_B_D7
1
Close to JDDR3H.1
DDR3 SO-DIMM B
Reverse Type
H=9.0mm
1 2
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#0
DDR_B_DQS0
2
DDR_B_D8
DDR_B_D9
DDR_B_D4
DDR_B_D5
1
1
DDR_B_D2
DDR_B_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
2
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
1
1
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
CD27
0.1U_0402_10V7K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1 2
DDR_B_D0
DDR_B_D1
1
+VREF_DQB
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
DDRB_ODT1
<7>
+V_SM_VREF_CNT
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
CD47
1
0.1U_0402_10V7K
2
3
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
Layout Note:
Place near JDDR3H
Close to JDDR3H.126
DDR_B_D52
DDR_B_D53
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB
Layout Note:
Place near JDDR3H.203 and 204
+1.35V
+1.35V
DDR_B_D54
DDR_B_D55
CD31 1
2 47U_0805_6.3V6M
DDR_B_D60
DDR_B_D61
CD41 1
2 10U_0603_6.3V6M
CD36 1
2 10U_0603_6.3V6M
CD37 1
2 10U_0603_6.3V6M
CD39 1
2 10U_0603_6.3V6M
CD40 1
2 10U_0603_6.3V6M
CD58 1
2 10U_0603_6.3V6M
DDR_B_DQS#7
DDR_B_DQS7
SE00000PL00
CD29 2
1 1U_0402_6.3V6K
CD30 2
1 1U_0402_6.3V6K
CD32 2
1 1U_0402_6.3V6K
CD33 2
DDR_B_D62
DDR_B_D63
PM_SMBDATA <11,30,38,45>
PM_SMBCLK <11,30,38,45>
+0.675VS
CD45 2
1 1U_0402_6.3V6K
CD42 2
1 1U_0402_6.3V6K
1 1U_0402_6.3V6K
+0.675VS
206
LCN_DAN06-K4806-0103_204P
Conn@
4
SPD setting (SA0, SA1)
PU/PD by Channel A/B
->Channel A 00
->Channel B 01
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDRIII-SODIMM1
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
12
of
57
A
B
C
D
E
UV1A
Part 1 of 6
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
2
AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DACA_HSYNC
DACA_VSYNC
120mA
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
52mA CORE_PLLVDD
71mA
@
2
PEX_TSTCLK_OUT
200_0402_1% PEX_TSTCLK_OUT#
AF22
AE22
3
AC7
AF25
PLTRST_VGA#
<44>
GPS_DOWN#
GPU_EVENT
XTAL_OUTBUFF
XTAL_SSIN
For GC6
2
2N7002KW_SOT323-3
8
7
6
5
10K_8P4R_5%
OPT@
1
DGPU_VID <55>
GPS_DOWN# <44>
PSI <55>
RPV2
VGA_EDID_CLK
VGA_EDID_DATA
SMB_CLK_GPU
SMB_DATA_GPU
1
2
3
4
8
7
6
5
2.2K_8P4R_5%
OPT@
RPV3
VGA_CRT_CLK
VGA_CRT_DATA
HDCP_SDA
HDCP_SCL
AB6
1
2
3
4
8
7
6
5
2.2K_8P4R_5%
OPT@
AG3
AF4
AF3
RPV12
FB_CLAMP
FB_CLAMP_REQ#
FB_CLAMP_MON
OVERT#_VGA
AE3
AE4
1
2
3
4
8
7
6
5
10K_8P4R_5%
OPT@
W5
AE2
AF2
RPV13
CLK_REQ_GC6#
<15>
<15>
B7
A7
VGA_CRT_CLK
VGA_CRT_DATA
C9
C8
HDCP_SCL
HDCP_SDA
A9
B9
VGA_EDID_CLK
VGA_EDID_DATA
JTAG_TRST
TESTMODE
CLK_REQ_GPU#
1
2
3
4
8
7
6
5
+3VS
2
D9
D8
SMB_CLK_GPU
SMB_DATA_GPU
L6
M6
+PLLVDD
Internal Thermal Sensor
+3VS_DGPU
VID_PLLVDD
N6
+GPU_PLLVDD
1
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
OPT@
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
1
2
3
4
XTAL_IN
XTAL_OUT
PEX_RST_N
PEX_TERMP
XTAL_SSIN
XTAL_OUTBUFF
C11
B10
XTALIN
XTAL_OUT
A10
C10
XTAL_SSIN
XTAL_OUTBUFF
2
1
2
OPT@
1
2
+1.05VS_DGPU
LV1
BLM18PG181SN1D_2P
1
2
OPT@
1
1
OPT@
2
OPT@
2
OPT@
QV1B
3
4
SMB_CLK_GPU
OPT@
QV1A
1
SMB_DATA_GPU
EC_SMB_CK2
<24,30,37,44>
2N7002DW-T/R7_SOT363-6
6
EC_SMB_DA2
<24,30,37,44>
2N7002DW-T/R7_SOT363-6
3
OPT@
CV42, CV43 under GPU
close to ball : AE8,AD7
2
<31>
SP_PLLVDD
CLK
1
RV4
AE8
AD8
AC6
CLK_REQ_GC6#
10K_8P4R_5%
OPT@
41mA
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
<29> CLK_PCIE_VGA
<29> CLK_PCIE_VGA#
DACA_VDD
DACA_VREF
DACA_RSET
QV8
N14PGV2@
1
DGPU_VID
GPS_DOWN#
PSI
+3VS_DGPU
RPV1
5
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
<14,17,44>
2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
FB_CLAMP
CV13
10U_0603_6.3V6M
2
2
2
2
2
2
2
2
3
OVERT#_VGA
GPU_EVENT
1
RB751V40_SC76-2
OPT@
CV12
22U_0805_6.3V6M
1
1
1
1
1
1
1
1
CV1
CV2
CV3
CV4
CV5
CV6
CV7
CV8
DACA_RED
DACA_GREEN
DACA_BLUE
FB_CLAMP_REQ#
DV1
CV11
4.7U_0603_6.3V6K
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
NC
+3VS_DGPU
CV10
0.1U_0402_10V7K
PCIE_CTX_C_GRX_N[0..3]
2
FB_CLAMP_MON
CV9
0.1U_0402_10V7K
PCIE_CTX_C_GRX_N[0..3]
1
GPIO
<6>
PCIE_CTX_C_GRX_P[0..3]
DACs
PCIE_CTX_C_GRX_P[0..3]
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
D
<6>
PCIE_GTX_C_CRX_N[0..3]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
S
PCIE_GTX_C_CRX_N[0..3]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G
<6>
AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
I2C
PCIE_GTX_C_CRX_P[0..3]
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCI EXPRESS
<6>
PCIE_GTX_C_CRX_P[0..3]
N14P-GV2-S-A2_FCBGA595
RV5
2.49K_0402_1%
OPT@
1
N14PGV2R1@
XTALIN
1
under GPU
close to AD8
NOGCLK@
CLK_REQ_VGA#
YV1
6
XTALIN
1
1
1
2
2N7002DW-T/R7_SOT363-6
OPT@
3
GND
QV2A
1
+3VS_DGPU
2
CV17
18P_0402_50V8J
NOGCLK@
RV7
10_0402_5%
@EMI@
2
27MHZ_16PF
2
3
XTAL_OUT
CV113
10P_0402_50V8J
GND
4
CV18
18P_0402_50V8J
NOGCLK@
2
2
<29>
1
1
1
OPT@ CV15
22U_0805_6.3V6M
2
0_0402_5%
GCLK@
OPT@ CV14
0.1U_0402_10V7K
1
RV8
VGA_X1
1
<38>
2
OPT@ CV16
10U_0603_6.3V6M
+1.05VS_DGPU
LV2
OPT@
1
2
FBMA-L11-160808300LMA25T_2P 1
+PLLVDD
@EMI@
2
for EMI
2
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x PEG & DAC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
1.0
Thursday, May 09, 2013
Sheet
E
13
of
57
A
VRAM Interface
1
30ohms (ESR=0.01)
1
OPT@
2
0.1U_0402_10V7K
OPT@
2
CV114
1
0.1U_0402_10V7K
OPT@
1
CV22
2
0.1U_0402_10V7K
OPT@
2
CV21
1
22U_0805_6.3V6M
Place close to BGA
Close to P22
Close to H22
+FB_PLLAVDD
CV20
+1.05VS_DGPU
LV3
OPT@
1
2
FBMA-L11-160808300LMA25T_2P
F16
P22
+FB_PLLAVDD
D23
Near GPU
Close to F16
H22
<13,17,44>
F3
FB_CLAMP
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FB_PLLAVDD_1
FB_PLLAVDD_2
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
62mA
62mA
F22
J22
PAD
PAD
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
35mA
FB_CLAMP
TP@
TV1
TV2
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FB_VREF_PROBE
FB_DLLAVDD
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DEBUG0
FBA_DEBUG1
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
RPV4
100_1206_10P8R_5%
RPV5
100_1206_10P8R_5%
OPT@
OPT@
1
2
3
4
5
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
<18,19,20,21>
CMDA11
CMDA4
CMDA5
CMDA6
+VRAM_1.5VS
CMDA22
CMDA9
CMDA21
CMDA24
D19
D14
C17
C22
P24
W24
AA25
U25
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
F19
C14
A16
A22
P25
W22
AB27
T27
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
E19
C15
B16
B22
R25
W23
AB26
T26
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
D24
D25
DQMA[3..0]
<18,20>
DQMA[7..4]
<19,21>
RPV6
100_1206_10P8R_5%
RPV7
100_1206_10P8R_5%
OPT@
DQSA#[3..0]
<18,20>
DQSA#[7..4]
<19,21>
OPT@
CMDA23
CMDA13
CMDA8
CMDA10
1
+VRAM_1.5VS
DQSA[3..0]
DQSA[7..4]
<18,20>
<19,21>
RPV9
RPV8
8
7
6
5
1
2
3
4
CMDA26
CMDA25
CMDA27
CMDA28
CMDA28
CMDA27
CMDA25
CMDA26
100_0804_8P4R_5%
OPT@
2
1
CMDA29
RV10
100_0402_5%
OPT@
2
1
CMDA30
RV12
100_0402_5%
OPT@
CLKA0 <18,20>
CLKA0# <18,20>
N22
M22
10
9
8
7
6
MDA[63..48]
CMDA[30..0]
10
9
8
7
6
Part 2 of 6
MDA[63..48]
1
2
3
4
5
<19,21>
CMDA12
CMDA14
CMDA15
CMDA7
MDA[47..32]
10
9
8
7
6
MDA[47..32]
+VRAM_1.5VS
UV1B
MDA[31..16]
1
2
3
4
5
<19,21>
MDA[15..0]
10
9
8
7
6
MDA[31..16]
1
2
3
4
5
MDA[15..0]
<18,20>
MEMORY
INTERFACE A
<18,20>
Place close to the first T point
1
2
3
4
8
7
6
5
100_0804_8P4R_5%
OPT@
2
1
RV11
100_0402_5%
OPT@
2
1
RV13
100_0402_5%
OPT@
CLKA1 <19,21>
CLKA1# <19,21>
D18
C18
D17
D16
T24
U24
V24
V25
Command Bit
DDR3
Default Pull-down
ODTx
10k
CKEx
10k
RST
TP@
10k
CS*
No Termination
N14P-GV2-S-A2_FCBGA595
N14PGV2R1@
CMDA16
CMDA19
CMDA3
CMDA0
CMDA20
Issued Date
2012/09/28
Deciphered Date
1
1
1
1
1
OPT@
OPT@
OPT@
OPT@
OPT@
2013/09/28
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
2
2
2
2
2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
RV36
RV37
RV38
RV40
RV15
N14x VRAM Interface
Thursday, May 09, 2013
Rev
1.0
Sheet
14
of
57
4
3
2
Physical
Strapping pin
UV1C
VGA_DEVICE
PEX_PLLEN_TERM
FB[1]
FB[0]
ROM_SCLK
+3VS_DGPU
PCI_DEVID[4]
SUB_VENDOR
PCI_DEVID[5]
ROM_SI
+3VS_DGPU
RAMCFG[3]
RAMCFG[2]
RAMCFG[1]
RAMCFG[0]
STRAP0
STRAP1
+3VS_DGPU
USER[3]
USER[2]
USER[1]
USER[0]
+3VS_DGPU
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
3GIO_PADCFG[0]
STRAP2
+3VS_DGPU
PCI_DEVID[3]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
+3VS_DGPU
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
STRAP4
+3VS_DGPU
RESERVED
PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED
E9
E10
000000
F6
F4
F5
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
MULTI_STRAP_REF0_GND
N14PGV2@
1
2
RV17
40.2K_0402_1%
MULTI LEVEL STRAPS
RV26
100_0402_1%
OPT@
F2
VGA_VCC_SENSE
F1
STRAP0
STRAP1
STRAP2
VGA_VCC_SENSE
VGA_VSS_SENSE
1001
0001
15K
1010
0010
20K
1011
0011
25K
1100
0100
30K
1101
0101
35K
1110
0110
45K
1111
0111
+3VS_DGPU
C
+3VS_DGPU
F12
E12
0000
10K
VGA_VSS_SENSE
STRAP3
STRAP4
ROM_SI
ROM_SO
ROM_SCLK
<55>
<55>
RV31
10K_0402_1%
N14MGL@
N14PGV2@
2
1
RV25
4.99K_0402_1%
D1
D2
E4
E3
D3
C1
trace width: 16mils
differential voltage sensing.
differential signal routing.
GND_SENSE
0x1140
Pull-down to Gnd
N14MGL@
2
1
RV34
10K_0402_1%
NC
NC
VDD_SENSE
N14M-GL
5K
N14PGV2@
2
1
RV24
4.99K_0402_1%
NC
NC
NC
NC
NC
010010
2
1
@
RV22
10K_0402_1%
THERMDP
0x1292
F10
+VGA_CORE
THERMDN
N14P-GV2
DP_PLL_VDD33V
Pull-up to +3VS
_DGPU
1000
Resistor Values
D10
N14PGV2@
2
1
RV31
45.3K_0402_1%
NC
NC
NC
NC
NC
NC
NC
NC
biit5 to bit0
2
@ 1
RV21
4.99K_0402_1%
MULTI_STRAP_REF0_GND
NC
NC
Device ID
N14PGV2@
2
1
RV30
4.99K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC
SKU
@ 1
2
RV20
10K_0402_1%
NC
2 10K_0402_5%
@ 1
2
RV19
10K_0402_1%
NC
RV16 1
D
STRAP3
N14PGV2@
2
1
RV29
15K_0402_1%
K5
J4
SMB_ALT_ADDR
+3VS_DGPU
2
@ 1
RV27
4.99K_0402_1%
M4
M5
L3
L4
K4
Logical
Strapping Bit0
N14MGL@
2
1
RV33
10K_0402_1%
NC
NC
D11
1
N1
M1
M2
M3
K2
K3
K1
J1
Logical
Strapping Bit1
ROM_SO
N14PGV2@
2
1
RV28
45.3K_0402_1%
C
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
Logical
Strapping Bit2
OPT@
BUFRST_N
NC
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
F11
AD10
AD7
B19
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
N14PGV2@
2
1
RV18
45.3K_0402_1%
V3
V4
U3
U4
T4
T5
R4
R5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
T2
T3
T1
R1
R2
R3
N2
N3
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
GENERAL
AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5
LVDS/TMDS
D
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
Logical
Strapping Bit3
2
@ 1
RV23
4.99K_0402_1%
Part 3 of 6
AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5
Power Rail
1
N14MGL@
2
1
RV32
10K_0402_1%
5
OPT@
J5
N4
N5
P3
P4
B
J2
J3
H3
H4
NC
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
2
1
RV35
100_0402_1%
TEST
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
AD9
AE5
AE6
AF6
AD6
AG4
D12
B12
A12
C12
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PAD
PAD
PAD
PAD
TV3
TV4
TV5
TV6
TP@
TP@
TP@
TP@
For X76 (N14M-GL)
For X76 (N14P-GV2)
TESTMODE <13>
GPU
ROM_SI
FB Memory gDDR3
GPU
STRAP[3:0]
FB Memory gDDR3
B
JTAG_TRST
<13>
900MHz
K4W2G1646E-BC11
1GHz
K4W2G1646E-BC1A
900MHz
H5TQ2G63DFR-11C
1GHz
H5TQ2G63DFR-N0C
Micron
900MHz
MT41K128M16JT-107G PD 30K
Samsung
900MHz
K4W4G1646B-HC11
900MHz
MT41K256M16HA-107G PD 10K
Samsung
1
2
8
M Hynix
ROM_SI
ROM_SO
ROM_SCLK
x
1
6
N14P-GV2-S-A2_FCBGA595
N14PGV2R1@
Samsung
PD 45.3K
1
2
8
M Hynix
PD 34.8K
N14P-GV2
x
1
6
PD 20K
Samsung
2
5
6
M Hynix
x
1
6
x
1
6
Micron
1GHz
K4W2G1646E-BC1A
900MHz
H5TQ2G63DFR-11C
1GHz
H5TQ2G63DFR-N0C
900MHz
MT41K128M16JT-107G
0001
900MHz
K4W4G1646B-HC11
1011
900MHz
H5TC4G63AFR-11C
0100
900MHz
MT41K256M16HA-107G
1101
2012/09/28
2013/09/28
Deciphered Date
3
A
VGA_N14x LVDS&TMDS
Date:
4
0110
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
0101
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
K4W2G1646E-BC11
N14M-GL
2
5
6
M Micron
A
Micron
900MHz
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
15
of
57
2
IFPD_PLLVDD_2
IFPD_PLLVDD_1
IFPD_RSET
IFPD_IOVDD
2
OPT@ CV30
22U_0805_6.3V6M
OPT@ CV29
10U_0603_6.3V6M
OPT@ CV28
10U_0603_6.3V6M
OPT@ CV27
4.7U_0603_6.3V6K
2
1
1
2
D
2
1
2
OPT@ CV42
22U_0805_6.3V6M
2
1
OPT@ CV41
22U_0805_6.3V6M
2
1
OPT@ CV40
10U_0603_6.3V6M
2
1
OPT@ CV39
10U_0603_6.3V6M
2
1
OPT@ CV38
4.7U_0603_6.3V6K
OPT@ CV36
1U_0402_6.3V6K
AA22
AB23
AC24
AD25
AE26
AE27
1
+3VS_DGPU
Under GPU
2
1
2
OPT@ CV49
4.7U_0603_6.3V6K
2
1
OPT@ CV48
1U_0402_6.3V6K
2
1
OPT@ CV47
0.1U_0402_10V7K
2
1
OPT@ CV46
0.1U_0402_10V7K
G10
G12
G8
G9
Near GPU
C
Near Ball
FB_CAL_PD_VDDQ
FB_CAL_TERM_GND
D22
C24
B25
1
2
+FB_CAL_PD_VDDQ
40.2_0402_1%
RV39
OPT@
2
1
FB_CAL_PU_GND
42.2_0402_1%
RV41
+VRAM_1.5VS
OPT@
2
1
FB_CAL_TERM_GND
51.1_0402_1%
RV42
OPT@
Under GPU
Close to AH12/AG12
+3VS_DGPU
Near GPU
PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
PEX_SVDD_3V3
J7
K7
K6
H6
J6
2
1
NC
NC
NC
NC
NC
120mA
PEX_PLLVDD_1
PEX_PLLVDD_2
AA8
AA9
1
AB8
AA14
AA15
1
B
2
1
2
1
2
+1.05VS_DGPU
LV4
1
+PEX_PLLVDD 2
BLM18PG121SN1D_0603
N14MGL@
2
1
2
1
2
1
2
OPT@ CV53
4.7U_0603_6.3V6K
T7
R7
U6
R6
IFPC_PLLVDD_1
IFPC_PLLVDD_2
IFPC_RSET
IFPC_IOVDD
1
1
VDD33_1
VDD33_2
VDD33_3
VDD33_4
FB_CAL_PU_GND
M7
N7
T6
P6
2
1
+1.05VS_DGPU
2
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
2
1
OPT@ CV52
4.7U_0603_6.3V6K
IFPAB_PLLVDD_1
IFPAB_PLLVDD_2
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
2
1
+1.05VS_DGPU
OPT@ CV51
0.1U_0402_10V7K
V7
W7
AA6
W6
Y6
1
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
midway between GPU
and Power supply
OPT@ CV50
0.1U_0402_10V7K
C
2000 mA
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
Near GPU
OPT@ CV45
0.1U_0402_10V7K
2
Part 4 of 6
OPT@ CV56
4.7U_0603_6.3V6K
2
1
OPT@ CV44
10U_0603_6.3V6M
1
OPT@ CV43
22U_0805_6.3V6M
Near GPU
2
3500 mA
FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
OPT@ CV55
1U_0402_6.3V6K
2
1
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21
OPT@ CV54
0.1U_0402_10V7K
2
1
OPT@ CV35
0.1U_0402_10V7K
2
1
OPT@ CV25
0.1U_0402_10V7K
2
1
UV1D
OPT@ CV34
1U_0402_6.3V6K
2
1
OPT@ CV33
1U_0402_6.3V6K
1
OPT@ CV24
4.7U_0603_6.3V6K
D
OPT@ CV32
4.7U_0603_6.3V6K
Under GPU
POWER
+VRAM_1.5VS
OPT@ CV26
1U_0402_6.3V6K
Under GPU
1
OPT@ CV31
22U_0805_6.3V6M
3
OPT@ CV23
1U_0402_6.3V6K
4
OPT@ CV37
1U_0402_6.3V6K
5
RV1
2
1
0_0603_5%
N14PGV2@
B
N14P-GV2-S-A2_FCBGA595
N14PGV2R1@
Under GPU
Near GPU
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
16
of
57
5
4
3
2
1
+1.05VS_VCCP to +1.05VS_DGPU
+VGA_CORE
UV1E
Part 6 of 6
+5VALW
+1.05VS_VCCP
QV3
2
D
RV44
22_0805_5%
2
+1.05VS_DGPU
3
6
1
CV57
OPT@
OPT@
QV4A
2
VGA_PWROK#
2N7002DW-T/R7_SOT363-6
OPT@
QV4B
5
2N7002DW-T/R7_SOT363-6
1
S
0.01U_0402_25V7K
1
2
G
AO3416_SOT23-3
OPT@
4
D
+1.05VS_DGPU
RV43
270K_0402_5%
OPT@
2
OPT@
1
Vgs=4.5V,Id=6.5A,Rds<22mohm
1
V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14
VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021
+5VALW
QV5A
6
1
2
100K_0402_5% RV45
OPT@
D
2
G
VGA_PWROK
2N7002KDWH_SOT363-6
S
1
OPT@
N14P-GV2-S-A2_FCBGA595
N14PGV2R1@
+1.5V to +VRAM_1.5VS
+1.5VS
Y
4
1.5V_PWR_EN
NC7SZ32P5X_SC70-5
2
2
OPT@
1
3
6
2 1.5V_PWR_EN# 5
2N7002DW-T/R7_SOT363-6
OPT@
QV7B
2N7002DW-T/R7_SOT363-6
OPT@
+5VALW
1
2
100K_0402_5%
RV49
OPT@
1
2
RV50
0_0402_5%
N14MGL@
N14P-GV2-S-A2_FCBGA595
N14PGV2R1@
B+
QV7A
4
A
RV48
820K_0402_5%
QV5B
1.5V_PWR_EN
B
3
B
1
2
180K_0402_5%
VRAM_1.5VS_GATE
1
CV60
OPT@
D
5
G
OPT@
2N7002KDWH_SOT363-6
S
B
4
1
3
AA7
AB7
FB_CLAMP
VGA_PWROK
1
CV59
OPT@
0.01U_0402_25V7K
<33,55>
UV2
N14PGV2@
RV46
470_0805_5%
OPT@
OPT@
RV47
FDS6676AS_SO8
2
2
Vgs=10V,Id=14.5A,Rds=6mohm
OPT@
1
S 2
S 3
S 4
G
1
D
D
D
D
1
QV6
8
7
6
5
+3VS
C
+VRAM_1.5VS
2
For GC6
<13,14,44>
GND
GND
VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
3
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
4.7U_0603_6.3V6K
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
5
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
POWER
Part 5 of 6
G Vcc
C
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND
D
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
+VGA_CORE
UV1F
+3VS to +3VS_DGPU
+3VS
+3VS_DGPU
+3VS
1
Vgs=-4.5V,Id=3A,Rds<97mohm
CV61
0.1U_0402_10V7K
OPT@
QV11
2
2
33K_0402_5%
OPT@
2
AO3413_SOT23
OPT@
1
1
6
5
+3VS_DGPU
QV9A
4
DGPU_PWR_EN#
4
5
QV2B
2N7002DW-T/R7_SOT363-6
OPT@
2
RV54
1
DGPU_PWR_EN#
QV9B
2N7002DW-T/R7_SOT363-6
OPT@
RV53
10K_0402_5%
3
2
2
3 1
3 1
OPT@
G
RV52
470_0805_5%
OPT@
D
RV51
470_0805_5%
OPT@
S
2
+VGA_CORE
DGPU_PWR_EN
CV62
OPT@ 0.01U_0402_25V7K
1
2
2N7002DW-T/R7_SOT363-6
OPT@
1
<31>
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
A
2013/09/28
Deciphered Date
Title
VGA_N14x POWER & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
17
of
57
5
RANK 0
4
3
2
1
[31...0]
VRAM DDR3 Chips
Rank 0
Mode E
Address
0..31
CMD0
ODT
Rank 1
32..63
0..31
CMD1
<14,20>
DQSA#[3..0]
DQMA[3..0]
DQMA[3..0]
<14,20>
,19,20,21>
DQSA[3..0]
DQSA[3..0]
DQSA#[3..0]
UV3
MDA[31..0]
MDA[31..0]
+MEM_VREF_CA0 M8
+MEM_VREF_DQ0 H1
CMDA[30..0]
CMDA[30..0]
1
+VRAM_1.5VS
+MEM_VREF_CA0
1
2
RV55
1K_0402_1%
OPT@
+MEM_VREF_CA0
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
2
2
CV63
0.01U_0402_25V7K
OPT@
C
1
+VRAM_1.5VS
+MEM_VREF_DQ0
+MEM_VREF_DQ0
1
2
RV57
1K_0402_1%
OPT@
1
2
CV64
0.01U_0402_25V7K
OPT@
M2
N8
M3
CLKA0
CLKA0#
CMDA3
J7
K7
K9
CMDA0
CMDA2
CMDA11
CMDA15
CMDA28
K1
L2
J3
K3
L3
DQSA1
DQSA2
F3
C7
DQMA1
DQMA2
E7
D3
DQSA#1
DQSA#2
G3
B7
CMDA20
T2
ZQ0
L8
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA9
MDA12
MDA8
MDA15
MDA13
MDA11
MDA10
MDA14
D7
C3
C8
C2
A7
A2
B8
A3
MDA18
MDA22
MDA16
MDA23
MDA17
MDA20
MDA19
MDA21
+MEM_VREF_CA0 M8
+MEM_VREF_DQ0 H1
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
Group1
Group2
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA29
CMDA13
CMDA27
M2
N8
M3
CLKA0
CLKA0#
CMDA3
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA0
CMDA2
CMDA11
CMDA15
CMDA28
K1
L2
J3
K3
L3
DQSA0
DQSA3
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA0
DQMA3
E7
D3
+VRAM_1.5VS
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
OPT@
RV61
243_0402_1%
2
J1
L1
J9
L9
OPT@
RV60
243_0402_1%
B
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+VRAM_1.5VS
1
2
RV58
1K_0402_1%
OPT@
CMDA29
CMDA13
CMDA27
UV4
DQSA#0
DQSA#3
G3
B7
CMDA20
T2
ZQ1
L8
@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA6
MDA1
MDA5
MDA0
MDA4
MDA2
MDA7
MDA3
D7
C3
C8
C2
A7
A2
B8
A3
MDA30
MDA26
MDA29
MDA24
MDA28
MDA27
MDA31
MDA25
Group0
Group3
+VRAM_1.5VS
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
CMD3
CKE
CMD4
A9
A9
A11
A11
CMD5
A6
A6
A7
A7
CMD6
A3
A3
BA1
BA1
CMD7
A0
A0
A12
A12
CMD8
A8
A8
A8
A8
CMD9
A12
A12
A0
A0
CMD10
A1
A1
A2
A2
CMD11
RAS#
RAS#
RAS#
RAS#
CMD12
A13
A13
A14
A14
CMD13
BA1
BA1
A3
A3
CMD14
A14
A14
A13
A13
CMD15
CAS#
CAS#
CAS#
CAS#
CMD16
B2
D9
G7
K2
K8
N1
N9
R1
R9
CKE
ODT
ODT
CMD17
CS1#
CS0#
CMD18
CKE
CMD19
+VRAM_1.5VS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
D
CKE
CMD20
RST
RST
RST
RST
CMD21
A7
A7
A6
A6
CMD22
A4
A4
A5
A5
CMD23
A11
A11
A9
A9
CMD24
A2
A2
A1
A1
CMD25
A10
A10
WE#
WE#
CMD26
A5
A5
A4
A4
CMD27
BA2
BA2
CMD28
WE#
WE#
A10
A10
CMD29
BA0
BA0
BA0
BA0
BA2
BA2
CMD30
C
1
1
RV56
1K_0402_1%
OPT@
@
CS0#
J1
L1
J9
L9
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Place close to the first T point
B
<14,20>
CLKA0
1
<14,20>
CS1#
CMD2
OPT@
RV63
160_0402_1%
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
2
<14,20>
D
32..63
ODT
<14,20>
CLKA0#
Place close to RANK0 VRAM
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
OPT@ CV87
22U_0805_6.3V6M
2
OPT@ CV86
0.1U_0402_10V7K
1
OPT@ CV85
0.1U_0402_10V7K
2
OPT@ CV84
0.1U_0402_10V7K
1
OPT@ CV83
0.1U_0402_10V7K
2
OPT@ CV82
0.1U_0402_10V7K
1
OPT@ CV81
1U_0402_6.3V6K
2
OPT@ CV80
1U_0402_6.3V6K
1
OPT@ CV79
1U_0402_6.3V6K
2
+VRAM_1.5VS
OPT@ CV78
1U_0402_6.3V6K
1
OPT@ CV77
1U_0402_6.3V6K
2
OPT@ CV76
0.1U_0402_10V7K
1
OPT@ CV75
0.1U_0402_10V7K
2
OPT@ CV74
0.1U_0402_10V7K
1
OPT@ CV73
0.1U_0402_10V7K
2
OPT@ CV72
0.1U_0402_10V7K
1
OPT@ CV71
1U_0402_6.3V6K
2
OPT@ CV70
1U_0402_6.3V6K
1
OPT@ CV69
1U_0402_6.3V6K
2
+VRAM_1.5VS
OPT@ CV68
1U_0402_6.3V6K
1
OPT@ CV67
1U_0402_6.3V6K
+VRAM_1.5VS
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x VRAM RANK 0L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
18
of
57
5
RANK 0
4
3
2
1
[63...32]
VRAM DDR3 Chips
Rank 0
Mode E
Address
0..31
CMD0
ODT
Rank 1
32..63
0..31
CMD1
D
<14,21>
DQSA[7..4]
<14,21>
DQSA#[7..4]
<14,21>
<14,21>
MDA[63..32]
<14,18,20,21>
CMDA[30..0]
CS0#
DQSA[7..4]
CMD3
CKE
DQSA#[7..4]
CMD4
A9
A9
A11
A11
CMD5
A6
A6
A7
A7
CMD6
A3
A3
BA1
BA1
CMD7
A0
A0
A12
A12
CMD8
A8
A8
A8
A8
CMD9
A12
A12
A0
A0
CMD10
A1
A1
A2
A2
CMD11
RAS#
RAS#
RAS#
RAS#
CMD12
A13
A13
A14
A14
UV5
MDA[63..32]
+MEM_VREF_CA1 M8
+MEM_VREF_DQ1 H1
CMDA[30..0]
1
RV59
1K_0402_1%
OPT@
+MEM_VREF_CA1
+MEM_VREF_CA1
UV6
@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
1
2
2
CV65
0.01U_0402_25V7K
OPT@
M2
N8
M3
CMDA29
CMDA13
CMDA27
J7
K7
K9
CLKA1
CLKA1#
CMDA19
C
+MEM_VREF_CA1 M8
+MEM_VREF_DQ1 H1
MDA35
MDA37
MDA32
MDA36
MDA33
MDA38
MDA34
MDA39
D7
C3
C8
C2
A7
A2
B8
A3
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
Group4
MDA58
MDA62
MDA56
MDA63
MDA57
MDA61
MDA59
MDA60
Group7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+VRAM_1.5VS
1
2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
+VRAM_1.5VS
RV62
1K_0402_1%
OPT@
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA29
CMDA13
CMDA27
CLKA1
CLKA1#
CMDA19
M2
N8
M3
J7
K7
K9
+VRAM_1.5VS
@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA45
MDA41
MDA46
MDA40
MDA44
MDA43
MDA47
MDA42
D7
C3
C8
C2
A7
A2
B8
A3
Group5
MDA54
MDA50
MDA55
MDA48
MDA53
MDA51
MDA52
MDA49
Group6
+VRAM_1.5VS
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
CV66
0.01U_0402_25V7K
OPT@
DQMA4
DQMA7
E7
D3
DQSA#4
DQSA#7
G3
B7
CMDA20
T2
ZQ2
L8
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
K1
L2
J3
K3
L3
DQSA5
DQSA6
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA5
DQMA6
E7
D3
DQSA#5
DQSA#6
G3
B7
CMDA20
T2
ZQ3
L8
1
2
2
F3
C7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
CMDA16
CMDA18
CMDA11
CMDA15
CMDA28
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
OPT@
RV72
243_0402_1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
J1
L1
J9
L9
OPT@
RV71
243_0402_1%
B
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
A3
A3
A14
A13
A13
CMD15
CAS#
CAS#
CAS#
CAS#
ODT
ODT
CS1#
CS0#
CMD18
CKE
CMD19
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
CKE
CMD20
RST
RST
RST
RST
CMD21
A7
A7
A6
A6
CMD22
A4
A4
A5
A5
CMD23
A11
A11
A9
A9
CMD24
A2
A2
A1
A1
CMD25
A10
A10
WE#
WE#
CMD26
A5
A5
A4
A4
CMD27
BA2
BA2
CMD28
WE#
WE#
A10
A10
CMD29
BA0
BA0
BA0
BA0
BA2
BA2
CMD30
C
J1
L1
J9
L9
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Place close to the first T point
<14,21>
B
CLKA1
1
1
DQSA4
DQSA7
ODT/ODT0
CS/CS0
RAS
CAS
WE
A1
A8
C1
C9
D2
E9
F1
H2
H9
BA1
A14
OPT@
RV74
160_0402_1%
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
2
+MEM_VREF_DQ1
K1
L2
J3
K3
L3
BA1
CMD14
CMD17
+VRAM_1.5VS
D
1
1
+MEM_VREF_DQ1
1
2
RV64
1K_0402_1%
OPT@
CMDA16
CMDA18
CMDA11
CMDA15
CMDA28
CKE
CMD13
CMD16
B2
D9
G7
K2
K8
N1
N9
R1
R9
+VRAM_1.5VS
RV65
1K_0402_1%
OPT@
CS1#
CMD2
DQMA[7..4]
DQMA[7..4]
32..63
ODT
<14,21>
CLKA1#
Place close to RANK1 VRAM
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DRANK@ CV112
22U_0805_6.3V6M
2
OPT@ CV111
0.1U_0402_10V7K
1
OPT@ CV110
0.1U_0402_10V7K
2
OPT@ CV109
0.1U_0402_10V7K
1
OPT@ CV108
0.1U_0402_10V7K
2
OPT@ CV107
0.1U_0402_10V7K
1
OPT@ CV106
1U_0402_6.3V6K
2
OPT@ CV105
1U_0402_6.3V6K
1
OPT@ CV104
1U_0402_6.3V6K
2
+VRAM_1.5VS
OPT@ CV103
1U_0402_6.3V6K
1
OPT@ CV102
1U_0402_6.3V6K
2
OPT@ CV101
0.1U_0402_10V7K
1
OPT@ CV100
0.1U_0402_10V7K
2
OPT@ CV99
0.1U_0402_10V7K
1
OPT@ CV98
0.1U_0402_10V7K
2
OPT@ CV97
0.1U_0402_10V7K
1
OPT@ CV96
1U_0402_6.3V6K
2
OPT@ CV95
1U_0402_6.3V6K
1
OPT@ CV94
1U_0402_6.3V6K
2
+VRAM_1.5VS
OPT@ CV93
1U_0402_6.3V6K
1
OPT@ CV92
1U_0402_6.3V6K
+VRAM_1.5VS
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x VRAM RANK 0H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
19
of
57
5
4
3
2
1
RANK 1 [31...0]
VRAM DDR3 Chips
Rank 0
Mode E
Address
0..31
CMD0
ODT
Rank 1
32..63
0..31
CS1#
CMD1
CMD2
D
<14,18>
DQSA[3..0]
<14,18>
DQSA#[3..0]
<14,18>
<14,18>
14,18,19,21>
DQMA[3..0]
MDA[31..0]
CMDA[30..0]
DQSA[3..0]
DQSA#[3..0]
DQMA[3..0]
MDA[31..0]
CMDA[30..0]
+MEM_VREF_CA0
+MEM_VREF_DQ0
DRANK@
0.01U_0402_25V7K
2
1
UV7
@
CV88
M8
H1 VREFCA
VREFDQ
N3
CMDA9
P7 A0
CMDA24
P3 A1
CMDA10
N2 A2
CMDA13
P8 A3
CMDA26
P2 A4
CMDA22
R8 A5
CMDA21
R2 A6
CMDA5
T8 A7
CMDA8
R3 A8
CMDA23
L7 A9
CMDA28
R7 A10/AP
CMDA4
N7 A11
CMDA7
T3 A12
CMDA14
T7 A13
CMDA12
M7 A14
A15/BA3
CMDA29
CMDA6
CMDA30
C
<14,18>
<14,18>
CLKA0
CLKA0#
CMDA3
M2
N8
M3
J7
K7
K9
CMDA0
CMDA1
CMDA11
CMDA15
CMDA25
K1
L2
J3
K3
L3
DQSA1
DQSA2
F3
C7
DQMA1
DQMA2
E7
D3
DQSA#1
DQSA#2
G3
B7
CMDA20
T2
ZQ4
L8
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DQSL
DQSU
RESET
ZQ/ZQ0
D7
C3
C8
C2
A7
A2
B8
A3
MDA12
MDA9
MDA15
MDA8
MDA14
MDA10
MDA11
MDA13
MDA22
MDA18
MDA23
MDA16
MDA21
MDA19
MDA20
MDA17
M8
H1
+MEM_VREF_CA0
+MEM_VREF_DQ0
Group1
CV89
0.01U_0402_25V7K
DRANK@
Group2
1
2
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+VRAM_1.5VS
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
E3
F7
F2
F8
H3
H8
G2
H7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA29
CMDA6
CMDA30
CLKA0
CLKA0#
CMDA3
+VRAM_1.5VS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
M2
N8
M3
J7
K7
K9
CMDA0
CMDA1
CMDA11
CMDA15
CMDA25
K1
L2
J3
K3
L3
DQSA0
DQSA3
F3
C7
DQMA0
DQMA3
E7
D3
DQSA#0
DQSA#3
G3
B7
CMDA20
T2
ZQ5
L8
@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DQSL
DQSU
RESET
ZQ/ZQ0
MDA1
MDA6
MDA0
MDA5
MDA3
MDA7
MDA2
MDA4
D7
C3
C8
C2
A7
A2
B8
A3
Group0
MDA26
MDA30
MDA24
MDA29
MDA25
MDA31
MDA27
MDA28
Group3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CMD3
CKE
CMD4
A9
A9
A11
A11
CMD5
A6
A6
A7
A7
CMD6
A3
A3
BA1
BA1
CMD7
A0
A0
A12
A12
CMD8
A8
A8
A8
A8
CMD9
A12
A12
A0
A0
CMD10
A1
A1
A2
A2
CMD11
RAS#
RAS#
RAS#
RAS#
CMD12
A13
A13
A14
A14
CMD13
BA1
BA1
A3
A3
CMD14
A14
A14
A13
A13
CMD15
CAS#
CAS#
CAS#
CMD16
CKE
CAS#
CS1#
CMD18
CS0#
+VRAM_1.5VS
A1
A8
C1
C9
D2
E9
F1
H2
H9
CKE
CKE
CMD19
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMD20
RST
RST
RST
RST
CMD21
A7
A7
A6
A6
CMD22
A4
A4
A5
A5
CMD23
A11
A11
A9
A9
CMD24
A2
A2
A1
A1
CMD25
A10
A10
WE#
WE#
CMD26
A5
A5
A4
A4
CMD27
BA2
BA2
CMD28
WE#
WE#
A10
A10
CMD29
BA0
BA0
BA0
BA0
BA2
BA2
CMD30
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
D
ODT
ODT
CMD17
+VRAM_1.5VS
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
E3
F7
F2
F8
H3
H8
G2
H7
CS0#
C
B
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
RV77
243_0402_1%
J1
L1
J9
L9
DRANK@
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
RV78
243_0402_1%
2
1
1
B
BA0
BA1
BA2
UV8
32..63
ODT
DRANK@
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x VRAM RANK 1L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
20
of
57
5
4
3
2
1
RANK 1 [63...32]
VRAM DDR3 Chips
0..31
CMD0
ODT
<14,19>
DQSA#[7..4]
DQMA[7..4]
<14,19>
MDA[63..32]
,18,19,20>
CMDA[30..0]
0..31
DQSA[7..4]
DQSA#[7..4]
DQMA[7..4]
MDA[63..32]
CMDA[30..0]
+MEM_VREF_CA1
+MEM_VREF_DQ1
DRANK@
0.01U_0402_25V7K
2
1
UV9
@
CV90
M8
H1 VREFCA
VREFDQ
N3
CMDA9
P7 A0
CMDA24
P3 A1
CMDA10
N2 A2
CMDA13
P8 A3
CMDA26
P2 A4
CMDA22
R8 A5
CMDA21
R2 A6
CMDA5
T8 A7
CMDA8
R3 A8
CMDA23
L7 A9
CMDA28
R7 A10/AP
CMDA4
N7 A11
CMDA7
T3 A12
CMDA14
T7 A13
CMDA12
M7 A14
A15/BA3
CMDA29
CMDA6
CMDA30
C
<14,19>
<14,19>
CLKA1
CLKA1#
CMDA19
J7
K7
K9
CMDA16
CMDA17
CMDA11
CMDA15
CMDA25
K1
L2
J3
K3
L3
DQSA4
DQSA7
F3
C7
DQMA4
DQMA7
E7
D3
DQSA#4
DQSA#7
G3
B7
CMDA20
T2
ZQ6
L8
BA0
BA1
BA2
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DQSL
DQSU
RESET
ZQ/ZQ0
D7
C3
C8
C2
A7
A2
B8
A3
MDA37
MDA35
MDA36
MDA32
MDA39
MDA34
MDA38
MDA33
MDA62
MDA58
MDA63
MDA56
MDA60
MDA59
MDA61
MDA57
M8
H1
+MEM_VREF_CA1
+MEM_VREF_DQ1
Group4
CV91
0.01U_0402_25V7K
DRANK@
1
2
Group7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA29
CMDA6
CMDA30
M2
N8
M3
CLKA1
CLKA1#
CMDA19
+VRAM_1.5VS
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA16
CMDA17
CMDA11
CMDA15
CMDA25
K1
L2
J3
K3
L3
DQSA5
DQSA6
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA5
DQMA6
E7
D3
DQSA#5
DQSA#6
G3
B7
CMDA20
T2
ZQ7
L8
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
RV80
243_0402_1%
DRANK@
2
2
RV79
243_0402_1%
DRANK@
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
+VRAM_1.5VS
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
E3
F7
F2
F8
H3
H8
G2
H7
1
B
M2
N8
M3
UV10
@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DQSL
DQSU
RESET
ZQ/ZQ0
MDA41
MDA45
MDA40
MDA46
MDA42
MDA47
MDA43
MDA44
D7
C3
C8
C2
A7
A2
B8
A3
MDA50
MDA54
MDA48
MDA55
MDA49
MDA52
MDA51
MDA53
Group5
CS1#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CS0#
CMD3
CKE
CMD4
A9
A9
A11
A11
CMD5
A6
A6
A7
A7
CMD6
A3
A3
BA1
BA1
CMD7
A0
A0
A12
A12
CMD8
A8
A8
A8
A8
CMD9
A12
A12
A0
A0
CMD10
A1
A1
A2
A2
CMD11
RAS#
RAS#
RAS#
RAS#
CMD12
A13
A13
A14
A14
CMD13
BA1
BA1
A3
A3
CMD14
A14
A14
A13
A13
CMD15
CAS#
CAS#
CAS#
CMD16
Group6
+VRAM_1.5VS
A1
A8
C1
C9
D2
E9
F1
H2
H9
D
CAS#
ODT
CS1#
CMD17
CS0#
CKE
CKE
CMD19
B2
D9
G7
K2
K8
N1
N9
R1
R9
CKE
ODT
CMD18
+VRAM_1.5VS
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
E3
F7
F2
F8
H3
H8
G2
H7
32..63
ODT
CMD20
RST
RST
RST
RST
CMD21
A7
A7
A6
A6
CMD22
A4
A4
A5
A5
CMD23
A11
A11
A9
A9
CMD24
A2
A2
A1
A1
CMD25
A10
A10
WE#
WE#
CMD26
A5
A5
A4
A4
CMD27
BA2
BA2
CMD28
WE#
WE#
A10
A10
CMD29
BA0
BA0
BA0
BA0
BA2
BA2
CMD30
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B
1
D<14,19>
DQSA[7..4]
Rank 1
32..63
CMD1
CMD2
<14,19>
Rank 0
Mode E
Address
J1
L1
J9
L9
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/28
2013/09/28
Deciphered Date
Title
VGA_N14x VRAM RANK 1H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
Thursday, May 09, 2013
Sheet
1
21
of
57
5
4
3
2
1
Mode Configure
Close to LT3
+SWR_VDD
+SWR_V12
2
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@
MIIC_SDA
Close to
Pin27
LVDS@
Close to Pin7
LVDS@
+3VS_RT
PIN30
UT2
LDO
SWR
Do not support
mount LT3
2132R
Use 0 ohm
mount LT3
<44>
<44>
2
1
H_EDP_TXP0_C_TL
H_EDP_TXN0_C_TL
5
6
AUX_P
AUX_N
LANE0P
LANE0N
CIICSCL1
CIICSDA1
32
TXE1+
TXE1TXE0+
TXE0-
19
20
2
MIIC_SCL
RT6
4.7K_0402_5%
RT7
4.7K_0402_5%
@
PIN31
LCD_TXCLK+ <23>
LCD_TXCLK- <23>
21
22
LCD_TXOUT2+ <23>
LCD_TXOUT2- <23>
23
24
LCD_TL_TXOUT1+
LCD_TL_TXOUT1-
25
26
LCD_TL_TXOUT0+
LCD_TL_TXOUT0-
+3VS_RT
LVDS@
LCD_EDID_DATA_TL RT9
1
2 4.7K_0402_5%
LVDS@
RT10 1
LCD_EDID_CLK_TL
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
LVDS
EDID
ROM
MIICSCL1
MIICDA1
MIICSCL0
MIICSDA0
DP_REXT
DP_GND
GND
LVDS@
14
15
16
17
2 4.7K_0402_5%
29
28
31
30
PIN16
PIN15
TL_INVT_PWM
80mil +LCD_VDD_TL
Accept voltage input (high level)
<23>
PCH_PWM <23,31>
EC_ENBKL <23,31,44>
LCD_EDID_CLK_TL
LCD_EDID_DATA_TL
2132S
TL_ENVDD
2132S
3.3V
2132R
+LCD_VDD *
2132R
1.5~3.3V
* Version R internal Power Switch, can
output 1A, Rds(on)=0.2 ohm
MIIC_SCL
MIIC_SDA
33
C
* Version R has internal level shifter, remove
level shifter circuit on AMD platform
Different between 2132S and 2132R
RTD2132R-VE-CG_QFN32_5X5
2132S
1
RT8
12K_0402_1%
LVDS@
HPD
8
4
2
H_EDP_HPD
D
RTD2132R
9
10
EC_SMB_CK3
EC_SMB_DA3
<23,8>
SWR_LX
SWR_VCCK
VCCK
DP_V12
Other
※ If use 2132R, please select LDO mode as default.
C
H_EDP_AUXP_C_TL
H_EDP_AUXN_C_TL
TXE2+
TXE2-
DP-IN
2132S
SWR_VDD
PVCC
LVDS
40mil
40mil
40mil
12
11
27
7
TXEC+
TXEC-
GPIO
SWR / LDO Mode select
13
18
DP_V33
Power
100mil
3
RT12
4.7K_0402_5%
LVDS@
Close to Pin13
LVDS@
1 +DP_V33
LT1 2
40mil
FBMA-L11-201209-221LMA30T_0805
LVDS@
100mil
1 +SWR_VDD
LT2 2
40mil
FBMA-L11-201209-221LMA30T_0805
+SWR_V12
40mil
LVDS@
2
LVDS@ LVDS@
RT4
4.7K_0402_5%
@
LVDS@
2
+3VS_RT
1
2
+3VS_RT
1
CT12
0.1U_0402_16V4Z
2
1
CT11
0.1U_0402_16V4Z
2
1
CT10
CT9
2
1
0.1U_0402_16V4Z
22U_0603_6.3V6M
1
CT8
2
0.1U_0402_16V4Z
2
1
CT7
CT6
2
1
0.1U_0402_16V4Z
LVDS@
2
1
CT5
2
1
CT3
LVDS@
CT2
CT1
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
1
1
22U_0603_6.3V6M
+DP_V33
0.1U_0402_16V4Z
CT4
10U_0603_6.3V6M
Close to Pin3
1
Close to Pin18
Close to LT2
2
100mil
2
0_0603_5%
1
1
RT1
2
100mil
D
only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
※ROM
EP mode
: PIN 30 4.7k pull high, Pin 31 4.7k pull low.
EEPROM
: PIN 30 4.7k pull high, Pin 31 4.7k pull high.
〈 ※Default mode 〉
+3VS_RT
Rshort@
1
+3VS
2132R
Close to Pin8
1. Support SWR mode
B
<8>
H_EDP_AUXP
<8>
H_EDP_AUXN
<8>
<8>
H_EDP_TXP0
H_EDP_TXN0
C7
IEDP@
1
2 0.1U_0402_10V6K
H_EDP_AUXP_C_R
C8
IEDP@
1
2 0.1U_0402_10V6K
H_EDP_AUXN_C_R
C9
LVDS@
1
2 0.1U_0402_10V6K
H_EDP_AUXP_C_TL
C10
LVDS@
1
2 0.1U_0402_10V6K
H_EDP_AUXN_C_TL
C11
LVDS@
1
2 0.1U_0402_10V6K
H_EDP_TXP0_C_TL
C12
LVDS@
1
2 0.1U_0402_10V6K
H_EDP_TXN0_C_TL
C13
IEDP@
1
2 0.1U_0402_10V6K
H_EDP_TXP0_C_R
C14
IEDP@
1
2 0.1U_0402_10V6K
H_EDP_TXN0_C_R
1
2
3
4
LCD_EDID_CLK_TL
LCD_EDID_DATA_TL
LCD_TL_TXOUT0LCD_TL_TXOUT0+
RP4 LVDS@
8
7
6
5
1. Support LDO mode and SWR mode
2. Internal ROM
3. Support LCD_VDD(internal Power switch)
4. Integrates Level shifter
LCD_EDID_CLK <23>
LCD_EDID_DATA <23>
LCD_TXOUT0- <23>
LCD_TXOUT0+ <23>
0_0804_8P4R_5%
1
2
3
4
H_EDP_AUXP_C_R
H_EDP_AUXN_C_R
H_EDP_TXN0_C_R
H_EDP_TXP0_C_R
RP5 IEDP@
8
7
6
5
B
0_0804_8P4R_5%
Place co-lay Resistor back to back on TOP and BOT
Change RT106 to short pad on PreMP
C914
<8>
H_EDP_TXN1
C915
IEDP@
1
2
0.1U_0402_10V7K
LCD_TXOUT1+ <23>
0.1U_0402_10V7K
LCD_TXOUT1-
1
RT106
Rshort@
<23>
Close to Pin15
R524 1
LCD_TL_TXOUT1-
R490 1
A
2
RT113
100K_0402_5%
LVDS@
2 0_0402_5%
CT13
4.7U_0603_6.3V6K
LVDS@ 1
2 0_0402_5%
Close to Panel conn.
LVDS@
LCD_TL_TXOUT1+
+LCD_VDD
2
0_0805_5%
1
H_EDP_TXP1
+LCD_VDD_TL
2
<8>
IEDP@
1
2
A
LVDS@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/30
2013/06/30
Deciphered Date
Title
LVDS Translator - RTD2132S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
VSKAA
Sheet
Thursday, May 09, 2013
1
22
of
57
A
B
C
D
E
LCD POWER CIRCUIT (For EDP panel only)
@TOUCH_EMI@
1
2
R104
0_0402_5%
When you use 2132R series type of LVDS translator,
You can delete this portion. If you use 2132S, please don't.
TOUCH_EMI@
1
USB20_P8_R
BTO : TOUCH@EMI@
1
2
USB20_P8
2
Change R83 to short pad on PreMP
<32>
+3VS
4
3
USB20_N8
3
+LCD_VDD
<32>
L57 WCM-2012-900T_0805
U18
W=80mils
@TOUCH_EMI@
1
2
R105
0_0402_5%
+LCD_VDD_SS
5
4
VOUT
1
4
3
1
2
3
USB20_P11
<32>
2
USB20_N11
<32>
Rshort@
GND
2
SS
EN
3
LCD_ENVDD
<31>
R112
0.015u_0402_16V_X7R
100K_0402_5%
IEDP@
2
WCM-2012-900T_0805
3
1
2
0_0805_5%
R83
APL3512ABI-TRG_SOT23-5
IEDP@
IEDP@
C17
1
+LCD_VDD_OUT
1
USB20_N11_R
CAM_EMI@
1
VIN
1
4
2
L55
USB20_P11_R
W=80mils
W=80mils
2
4
USB20_N8_R
1
1
D89
YSLC05CH_SOT23-3
@ESD@
+5VS
2
2
Rshort@
JLVDS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
1
R390
+5VS_LVDS_TOUCH
USB20_N8_R
USB20_P8_R
BKOFF#
USB20_P11_R
USB20_N11_R
+3VS_LVDS_CAM
20mils
D3
INT_MIC_DATA
INT_MIC_CLK
INT_MIC_DATA <42>
INT_MIC_CLK <42>
INT_MIC_DATA
2
INT_MIC_CLK
2
+3VS
Rshort@
1
R389
2
0_0603_5%
20mils
+LCD_VDD Irush=1.5A
+3VS
60mils
ESD@
1
CK0402101V05_0402-2
D2
ESD@
1
CK0402101V05_0402-2
LCD_EDID_CLK <22>
LCD_EDID_DATA <22>
LCD_TXOUT0- <22>
LCD_TXOUT0+ <22>
LCD_TXOUT1- <22>
LCD_TXOUT1+ <22>
LCD_TXOUT2- <22>
LCD_TXOUT2+ <22>
LCD_TXCLK- <22>
LCD_TXCLK+ <22>
H_EDP_HPD <22,8>
LED_PWM
BKOFF#_R
+LCD_INV
31
32
33
34
35
GND
GND
GND
GND
GND
2
0_0603_5%
Irush=1.5A
60mils
3
+LCD_INV
B+
L2
2
1
FBMA-L11-201209-221LMA30T_0805
EMI@
Conn@
Mount U19 for flash line issue on LVDS panel and change R103 to short pad for PreMP
+3VS
IN2
2
EC_ENBKL
BKOFF#
BKOFF#
<22,31,44>
LED_PWM
<44>
PCH_PWM
1
D18
TL_INVT_PWM
2
RB751V40_SC76-2
<22,31>
<22>
LVDS@
SN74AHC1G08DCKR_SC70-5
R131
47K_0402_5%
1
R147
@
2
0_0402_5%
4
2
2
1
IEDP@
1
2
D17
RB751V40_SC76-2
1
O
@
R114
10K_0402_5%
4
IN1
3
1
2
4
RB751V40_SC76-2
U19
P
1
D16
BKOFF#_R
2
0_0402_5%
G
1
R103
5
Rshort@
Reserve for LVDS panel
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LVDS
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
23
of
57
5
4
3
2
1
Default to PS8401 & PS8201 I2C Control Mode
If PS8401 use I2C Mode , EQ=I2C_ADDR0 , CFG = I2C_ADDR1
For PS8401
I2C control bus address LSB; Internal pull down at 150kohz±20%, 3.3V I/O.
[I2C_ADDR1, I2C_ADDR0] ; I2C Address (W/R)=
LL: 0x4C/4D (default)
LH: 0x5C/5D
HL: 0xCC/CD
HH: 0xEC/ED
36
Use Automatic Power Management ; PD# set to NC
Interanl pull up at 150kΩ±20% 3.3 I/O
+3VS
EHDMI@
1 R167
2
4.7K_0402_5%
13
14
<13,30,37,44> EC_SMB_CK2
<13,30,37,44> EC_SMB_DA2
34
I2C Control Mode Use;
Pull up 3.3VS Power at EC Side
If PS8401 use I2C Mode , EQ=I2C_ADDR
38
39
<25,31> UMA_HDMI_CLK
<25,31> UMA_HDMI_DATA
For PS8201
I2C control bus address LSB; Internal pull down at ~150k ohz, 3.3V I/O.
[I2C_ADDR] ; I2C Address (W/R)=
L: 0x64/65 (default)
H: 0xE4/E5
8
+3VS
+3VS
@
1 R168
2
4.7K_0402_5%
@
1 R169
2
4.7K_0402_5%
23
VDD33
VDD33 / NC
I2C Mode HDMI ID Setting
6
7
4
5
1
2
9
10
HDMI_TXD0+_C_U
HDMI_TXD0-_C_U
HDMI_TXD1+_C_U
HDMI_TXD1-_C_U
HDMI_TXD2+_C_U
HDMI_TXD2-_C_U
HDMI_TXC+_C_U
HDMI_TXC-_C_U
IN_D0p
IN_D0n
IN_D1p
IN_D1n
IN_D2p
IN_D2n
IN_CKp
IN_CKn
OUT_D0p
OUT_D0n
OUT_D1p
OUT_D1n
OUT_D2p
OUT_D2n
OUT_CKp
OUT_CKn
PD#
I2C_CTL_EN
DCIN_EN / SCL_CTL
DDCBUF / SDA_CTL
For Pin 31
C185
EHDMI@
C187
EHDMI@
For Pin 19
1
2
1
For Pin 20
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
C183
8401@
2
0.1U_0402_16V7K
C182
EHDMI@
1
0.1U_0402_16V7K
0.01U_0402_25V7K
1
2
D
For Pin 40
25
24
27
26
30
29
22
21
HDMI_TXD0+_U <25>
HDMI_TXD0-_U <25>
HDMI_TXD1+_U <25>
HDMI_TXD1-_U <25>
HDMI_TXD2+_U <25>
HDMI_TXD2-_U <25>
HDMI_TXC+_U <25>
HDMI_TXC-_U <25>
ISET / NC
SCL_SRC
SDA_SRC
SCL_SNK
SDA_SNK
CFG/I2C_ADDR1 / I2C_ADDR
HPD_SNK
17
16
EHDMI@
For Pin 12
U17
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
C195
C194
EHDMI@
For Pin 37
1
2
12
40
20
31
19
For Pin 11
2
0.01U_0402_25V7K
1
11
37
D
2
VDDRX / NC
VDDRX / VDD15
VDDTX / VDD15
VDDTX / VDD15
VDDTA / VDD15
1
C186
EHDMI@
2
0.1U_0402_16V7K
1
C197
EHDMI@
2
0.1U_0402_16V7K
C196
EHDMI@
+1.5VS
0.01U_0402_25V7K
+3VS
32
33
28
HDMI_SCLK <25>
HDMI_SDATA <25>
HDMI_HPD_C
<25>
Connector to Re-dirver
EQ / I2C_ADDR0
PRE
C
C
<25,31,33>
3
HDMI_HPD
2 R79
1
4.99K_0402_1%
H:3.3V
M:1.65V
L:0V
PS8401
Net name
DDCBUF
ISET
B
CFG
EQ
DC cou;ing enable; Internal pull down at 150k ohz ±20%, 3.3V I/O.
L: default, AC coupling input
H: DC coupling input
I2C_CTL_EN
PS8201
I2C Control Mode
Pin Control Mode
PS8401ATQFN40GTR-A3_TQFN40_5X5
EHDMI@
SA00005CW00
I2C Control Mode
L
Become
I2C Bus
Control
L
Become
I2C Bus
Control
Enable active DDC buffer; Internal pull down at 150k?±20%, 3.3V I/O.
L: default, passive DDC pass-through
H: active DDC buffer with default threshold
M: active DDC buffer without internal pull up resistor
M
Become
I2C Bus
Control
M
Become
I2C Bus
Control
TMDS output swing adjustment; Internal pull down at 150kΩ±20%, 3.3V I/O.
For PS8401 Only ISET = L:
Default
H:
Increase +13%
M:
Reduce -13%
L
NC
NC
NC
H
NC
H
NC
M
NC
M
NC
Output pre-emphasis setting; Internal pull down at 150kΩ±20%, 3.3V I/O.
PRE = L:
No pre-emphasis
H:
1.6dB pre-emphasis
M:
2.5dB pre-emphasis
L
NC
L
NC
I2C Control enable. Internal pull down at 150kΩ±20%. 3.3V I/O
I2C_CTL_EN = LOW (L):
Pin Control is selected.
HIGH (H):
I2C Control is selected.
L
H
L
H
CFG: Configuration pin, 3.3V IO, internal pull down at 150kΩ±20%. 3.3V I/O
CFG = L: HDMI ID disable
H: HDMI ID enable
EQ:Receiver equalization setting;; Internal pull down at ~150k?, 3.3V I/O.
For PS801 EQ = L:programmable EQ for channel loss up to 6.5dB @ 3.0Gbps
H:programmable EQ for channel loss up to 9.5dB @ 3.0Gbps
M:programmable EQ for channel loss up to 3dB @ 3.0Gbps
For PS8401 EQ = L:programmable EQ for channel loss up to 12.4dB
H:programmable EQ for channel loss up to 4.3dB
M:programmable EQ for channel loss up to 8.6dB
PRE
REXT
Description
Pin Control Mode
DCIN_EN
18
15
35
41
Strap
EHDMI@
HPD_SRC
GND / NC
GND
GND_PAD
Re-dirver to CPU
B
A
A
Note: PS8401 have Jitter cleaning function and
can control TMDS output swing
, PS8201 don't have.
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/??/??
Deciphered Date
2015/??/??
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
HDMI Re-driver
Document Number
PS8201A & PS8401A
Thursday, May 09, 2013
Sheet
1
24
of
57
Rev
1.0
A
H_HDMI_TXC+
H_HDMI_TXC-
<8>
H_HDMI_TX0+
C29
EHDMI@
1
2 0.1U_0402_10V7K
C22
IHDMI@
1
2 0.1U_0402_10V7K
C30
EHDMI@
1
2 0.1U_0402_10V7K
C23
IHDMI@
1
2 0.1U_0402_10V7K
C31
EHDMI@
1
2 0.1U_0402_10V7K
C24
IHDMI@
1
2 0.1U_0402_10V7K
C32
EHDMI@
1
2 0.1U_0402_10V7K
C25
IHDMI@
1
2 0.1U_0402_10V7K
C33
EHDMI@
1
2 0.1U_0402_10V7K
C26
IHDMI@
1
2 0.1U_0402_10V7K
C34
EHDMI@
1
2 0.1U_0402_10V7K
C27
IHDMI@
1
2 0.1U_0402_10V7K
1
<8>
<8>
H_HDMI_TX0-
H_HDMI_TX1+
<8>
<8>
E
H_DVI_TXC+
HDMI_TXC+_C_U
<24>
HDMI_TXC-_C_U
<24>
PS8401
PS8201
H_DVI_TXC-
H_DVI_TXD0+
Choke
HDMI TMDS BUS
1
HDMI_TXD0+_C_U
<24>
HDMI_TXD0-_C_U
<24>
HDMI_TXD1+_C_U
<24>
Colay Cap
H_HDMI_TX1-
Componet close to Conn.
Impedance depend on platform design guide
H_DVI_TXD1+
H_DVI_TXD1-
RO0000003HM
RP3
HDMI W/Logo + HDCP
+3VS
HDMI_TXD1-_C_U
1
2
3
4
<24>
8
7
6
5
HDMI_SCLK
HDMI_SDATA
UMA_HDMI_CLK
UMA_HDMI_DATA
+3VS
+3VS
H_DVI_TXD2+
EHDMI@
1
2 0.1U_0402_10V7K
C28
IHDMI@
1
2 0.1U_0402_10V7K
C36
EHDMI@
1
2 0.1U_0402_10V7K
HDMI_TXD2+_C_U
<24>
HDMI_TXD2-_C_U
<24>
please manually load
this virtual material to 45@ BOM
H_DVI_TXD2-
<24,31>
UMA_HDMI_CLK
UMA_HDMI_CLK
3
UMA_HDMI_DATA
Y
4
2
2
C265
0.1U_0402_10V7K
IHDMI@
1
HDMI_HPD
IHDMI@
2
1
R571
2.2K_0402_5%
74AHCT1G125GW_SOT353-5
IHDMI@
HDMI_HPD
R9
1
VIN = 5V, IOUT = 0.5A , RDS(ON)
Current Limit: TYP=0.8A ; MAX=1A
<24>
HDMI_TXC-_U
R6
R7
EHDMI@
1
2 0_0402_5%
1
3
HDMI_SDATA
<24>
TYP=95m
; MAX=115m
+HDMI_5V_OUT
2 0_0402_5%
U16
1
HDMI_TXC+_U
2
HDMI POWER CIRCUIT
<24,31,33>
IHDMI@
H_DVI_TXC+
HDMI_SDATA
+3VS
1
5
1
OE#
P
3
G
A
U9
<24>
Q19
BSH111_SOT23-3
IHDMI@
HDMI_HPD_C
R186
100K_0402_5%
IHDMI@
HDMI_HPD
HDMI_SCLK
D
S
R145
2
HDMI_HPD_U 1
1K_0402_5%
IHDMI@
HDMI_SCLK
D
S
G
<24,31>
1
Q18
BSH111_SOT23-3
1
IHDMI@
UMA_HDMI_DATA 3
+HDMI_5V_OUT
<24>
HDMI W/O Logo: RO0000001HM
HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM
G
2
C35
HDMI45@
HDMI Royalty
+HDMI_5V_OUT
2.2K_0804_8P4R_5%
H_HDMI_TX2-
2
Colay Resistor
H_DVI_TXD0-
ZZZ
H_HDMI_TX2+
<8>
D
2
<8>
C16
C
2
<8>
B
IHDMI@
1
2 0.1U_0402_10V7K
EHDMI@
2 0_0402_5%
H_DVI_TXC+_R
1
L8
EMI@
1
2
4
3
2
HDMI_R_CK+
C259
OUT
2
1
3
H_DVI_TXC-_R
4
IHDMI@
3
HDMI_R_CK-
0.1U_0402_10V7K
2
R8
1
H_DVI_TXD0-
R14
1
2 0_0402_5%
R11
1
EHDMI@
2 0_0402_5%
H_DVI_TXD0-_R 4
R12
EHDMI@
1
2 0_0402_5%
H_DVI_TXD0+_R 1
+5VS
FLG
4
EN
AP2151DWG-7_SOT25-5
3
SA00006H000
WCM-2012HS-900T_4P
H_DVI_TXC-
5
IN
GND
2 0_0402_5%
IHDMI@
<24>
<24>
HDMI_TXD0-_U
HDMI_TXD0+_U
IHDMI@
H_DVI_TXD0+ R13
1
H_DVI_TXD1+ R18
1
WCM-2012HS-900T_4P
3
4
3
1
L9
2
EMI@
2
HDMI_R_D0-
HDMI Connector
HDMI_R_D0+
HDMI_R_D0+
HDMI_R_D0HDMI_R_CK+
HDMI_R_CK-
2 0_0402_5%
1
2
3
4
RP1 IHDMI@
8
7
6
5
JHDMI
<24>
HDMI_HPD_C
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
IHDMI@
R15
H_DVI_TXD1+_R 1
EHDMI@
2 0_0402_5%
H_DVI_TXD1-_R 4
R16
1
H_DVI_TXD1-
R17
1
H_DVI_TXD2-
R22
1
2 0_0402_5%
R19
1
EHDMI@
2 0_0402_5%
H_DVI_TXD2-_R 4
R20
1
EHDMI@
2 0_0402_5%
H_DVI_TXD2+_R 1
HDMI_TXD1-_U
IHDMI@
EMI@
1
2
4
3
2
HDMI_R_D1+
3
HDMI_R_D1-
HDMI_R_D2+
HDMI_R_D2HDMI_R_D1+
HDMI_R_D1-
1
2
3
4
<24>
HDMI_TXD2-_U
<24>
HDMI_TXD2+_U
1
HDMI_R_D0+
HDMI_R_D1-
680_8P4R_5%
Q24
+5VS
IHDMI@
H_DVI_TXD2+ R21
HDMI_R_CK+
HDMI_R_D0-
WCM-2012HS-900T_4P
2 0_0402_5%
IHDMI@
4
HDMI_R_CK-
RP2 IHDMI@
8
7
6
5
WCM-2012HS-900T_4P
3
4
3
1
L11
2
EMI@
2
2 0_0402_5%
S 2N7002KW_SOT323-3
IHDMI@
HDMI_R_D2+
B
Conn@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND
23
22
21
20
4
TYCO_2041343-1~D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_R_D2+
Issued Date
Common CHOKE use 90ohm
D
2
G
HDMI_R_D2-
HDMI_R_D1+
HDMI_R_D2-
1
<24>
HDMI_TXD1+_U
680_8P4R_5%
L10
3
<24>
2 0_0402_5%
EHDMI@
1
2 0_0402_5%
HDMI_HPD_C
C
D
HDMI Conn.
Document Number
Rev
1.0
VSKAA
Thursday, May 09, 2013
Sheet
E
25
of
57
A
B
C
D
E
CRT CONNECTOR
BTO : CRT_EMI@
1
1
UMA_CRT_R
L3
<31>
UMA_CRT_G
L4
<31>
UMA_CRT_B
L5
<31>
CRT_EMI@
2 NBQ100505T-800Y_0402
CRT_EMI@
1
2 NBQ100505T-800Y_0402
CRT_EMI@
1
2 NBQ100505T-800Y_0402
1
CRT_R_L
CRT_G_L
CRT_B_L
T65, T66: for ATE
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
TP@
2
1
C241
2
CRT@
1
C242
2
1
C243
2
2.2P_0402_50V8C
2
CRT@
2.2P_0402_50V8C
2
1
C240
CRT@
2.2P_0402_50V8C
1
2
3
4
1
C239
2.2P_0402_50V8C
8
7
6
5
1
R138
C238
150_0804_8P4R_1%
CRT@
CRT@
2.2P_0402_50V8C
CRT@
2.2P_0402_50V8C
CRT@
CRT_R_L
T65 PAD
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+HDMI_5V_OUT
VSYNC
TP@ T66 PAD
CRT_DDC_CLK
G
G
16
17
C-H_13-12201513CP
Conn@
2
2
VCC_VIDEO
BYP
VIDEO1
8
C15
+HDMI_5V_OUT
CRT@
1
2
0.22U_0402_16V7K
3
CRT_R_L
4
<31>
UMA_CRT_DATA
10
<31>
UMA_CRT_CLK
11
<31>
<31>
UMA_CRT_VSYNC
UMA_CRT_HSYNC
13
15
6
VCC_DDC
VIDEO2
CRT_G_L
5
CRT_B_L
DDC_IN1
VIDEO3
DDC_IN2
DDC_OUT1
SYNC_IN1
SYNC_IN2
GND
DDC_OUT2
SYNC_OUT1
SYNC_OUT2
R153
4.7K_0402_5%
CRT@
1
+3VS
7
2
2
CRT@
VCC_SYNC
2
+5VS
1
R159
4.7K_0402_5%
CRT@
1
U3
+HDMI_5V_OUT
9
CRT_DDC_DAT
12
14
16
CRT_DDC_CLK
R62
CRT@
1
2 22_0402_5%
VSYNC_R
HSYNC_R
R63
1 CRT@ 2 22_0402_5%
VSYNC
HSYNC
3
3
TPD7S019-15DBQR_SSOP16
4
4
2011/11/11
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/12/31
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
CRT
Document Number
Rev
1.0
VSKAA
Thursday, May 09, 2013
Sheet
E
26
of
57
A
B
C
D
LPT_PCH_M_EDS
UH1A
1
PCH_RTCX1_R
1 GCLK@ 2 PCH_RTCX1
RH26
0_0402_5%
YH1
32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@
2
CH3
JME SP@
1
2
2 PCH_SRTCRST#
1 NOGCLK@
15P_0402_50V8J
PCH_RTCX2 B4
PCH_SRTCRST# B9
SM_INTRUDER#
PCH_RTCRST#
CH5 1
1U_0402_6.3V6K
A8
PCH_INTVRMEN G10
D9
2
B25
AZ_BITCLK
A22
AZ_SYNC
Integrated SUS 1.05V VRM Enable
High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
<42>
AL10
PCH_SPKR
PCH_SPKR
C24
AZ_RST#
L22
AZ_SDIN0_HD
K22
+3VALW_PCH
G22
2
RH207
2
1
EC_LID_OUT#
1K_0402_5%
F22
Rshort@
<44>
+RTCVCC
PWRME_CTRL
1
RH25
2
0_0402_5%
AZ_SDOUT
A24
B17
RH12 1
2
SM_INTRUDER#
1M_0402_5%
2
PCH_INTVRMEN
330K_0402_5%
RH33 1
+3VS
Rshort@
<44>
EC_LID_OUT#
1
RH27
2
EC_LID_OUT#_R
0_0402_5%
C22
SRTCRST#
NA
INTRUDER#
INTVRMEN
Gen2
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDI0
NA
Gen3
HDA_SDI2
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
HDA_SDI3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
HDA_SDO
Gen3
DOCKEN#/GPIO33
HDA_DOCK_RST#/GPIO13
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
PCH_SPKR
SATALED#
PCH_SPKR
High = Enabled "No Reboot Mode"
Low = Disabled (Default)
TP@T45
TP@
T45 PAD
PCH_JTAG_TCK AB3
TP@T9
TP@
T9
PAD
PCH_JTAG_TMS AD1
TP@T10
TP@
T10 PAD
PCH_JTAG_TDI AE2
TP@T11
TP@
T11 PAD
PCH_JTAG_TDO AD3
HDA_SDO
F8
C26
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
AB6
JTAG_TCK
SATA0GP/GPIO21
JTAG_TMS
SATA1GP/GPIO19
JTAG_TDI
JTAG
*
2
1K_0402_5%
SATA_RXN_1
SATA_RXP_1
HDA_SDI1
@
1
RH36
SATA_TXN_0
SATA_TXP_0
RTCRST#
AZALIA
<42>
Gen2
RTCX1
RTCX2
1
SATA_RXN_0
SATA_RXP_0
SATA_IREF
JTAG_TDO
TP9
TP25
TP8
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
BD9
SATA_PRX_C_DTX_N2 <37>
SATA_PRX_C_DTX_P2 <37>
AY13
AW13
ODD
SATA_PTX_DRX_N2 <37>
SATA_PTX_DRX_P2 <37>
BC12
BE12
AR13
AT13
BD13
BB13
SATA_PRX_C_DTX_N4 <37>
SATA_PRX_C_DTX_P4 <37>
AV15
AW15
HDD
SATA_PTX_DRX_N4 <37>
SATA_PTX_DRX_P4 <37>
+3VS
2
BC14
BE14
PCH_GPIO21
RH34 2
1 10K_0402_5%
PCH_GPIO19
RH28 1
2 10K_0402_5%
AP15
AR15
AY5 SATAICOMP
1
RH43
2
+1.5VS
7.5K_0402_1%
AP3
AT1 PCH_GPIO21
AU2 PCH_GPIO19
BOOT BIOS Strap Bit 0
BD4 SATAIREF
+1.5VS
BA2
BB2
TP22
TP20
+RTCBATT
1 OF 11
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
1
RH24 1
20K_0402_5%
<38>
SATA
iME Setting.
2
B5
PCH_RTCX1
HM86
RTC
CH4 1
1U_0402_6.3V6K
1 NOGCLK@
15P_0402_50V8J
NOGCLK@
PCH_RTCRST#
2
CH2
2
2
JCMOS SP@
1
2
RH2
10M_0402_5%
2
1
RH23 1
20K_0402_5%
+RTCVCC
Placement near to YH1
1
CMOS Setting, near DDR Door
E
DH2
BAS40-04_SOT23-3
+RTCVCC
2
3
3
3
+3VL
1
RPH1
<42>
<42>
<42>
<42>
1
2
3
4
AZ_BITCLK_HD
AZ_SDOUT_HD
AZ_RST_HD#
AZ_SYNC_HD
2
8
7
6
5
CH15
0.1U_0402_10V7K
AZ_BITCLK
AZ_SDOUT
AZ_RST#
AZ_SYNC
Un-mount for reduce power consumption at S0, S3 state
33_8P4R_5%
EMI@
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
PCH_HDA/JTAG/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
27
of
57
A
B
C
D
E
+3VALW_PCH
LPT_PCH_M_EDS
UH1B
1
2
RH235
1
10K_0402_5%
PCH_SUSPWRDN#_R
2
RH158
1
10K_0402_5%
RI#
2
RH156
1
10K_0402_5%
PCH_LOW_BAT#
2
RH169
1
PCH_RSMRST#
10K_0402_5%
2
RH284
1
PM_PWROK
10K_0402_5%
<6>
<6>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
<6>
<6>
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
<6>
<6>
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<6>
<6>
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
<6>
<6>
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
<6>
<6>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
<6>
<6>
AW22
AR20
AP17
AV20
AY22
AP20
AR17
AW20
BD21
BE20
BD17
BE18
BB21
BC20
BB17
BC18
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
BE16
DMI_IREF
+1.5VS
AW17
AV17
1
+1.5VS
<44>
2
SUSACK#
+3VS
<54>
<44>
2
RH48
VGATE
PM_PWROK
DMI_RCOMP
7.5K_0402_1%
1
2 SUSACK#_R
@
RH134
0_0402_5%
1
2 SYS_RESET#
RH1
1K_0402_1%
1 Rshort@ 2 SYS_PWROK
RH283
0_0402_5%
PM_PWROK
AY17
R6
AM1
AD7
F10
AB7
<5>
<44>
DRAMPWROK
+3VALW_PCH
PCH_RSMRST#
PCH_RSMRST#
PAD
<44>
H3
T94
TP@ 1
PBTN_OUT#
1
RH168
J2
2 PCH_SUSPWRDN#_R J4
@
RH135 0_0402_5%
K1
2
330K_0402_5%
PCH_ACIN
E6
PCH_LOW_BAT#K7
DH8
<44,47,49>
ACIN
1
2
N4
RI#
AB10
CH751H-40PT_SOD323-2
D2
DMI_RXN_0
DMI_RXN_1
FDI_RXN_0
DMI_RXN_2
DMI_RXN_3
FDI_RXN_1
DMI_RXP_0
DMI_RXP_1
FDI_RXP_0
FDI_RXP_1
DMI_RXP_2
DMI_RXP_3
TP16
DMI_TXN_0
DMI_TXN_1
TP5
DMI
FDI
TP15
DMI_TXN_2
DMI_TXN_3
TP10
DMI_TXP_0
DMI_TXP_1
FDI_CSYNC
FDI_INT
DMI_TXP_2
DMI_TXP_3
FDI_IREF
DMI_IREF
TP17
TP12
TP13
TP7
FDI_RCOMP
AJ35
AL35
AJ36
AL36
FDI_CTX_PRX_N0
<8>
FDI_CTX_PRX_N1
<8>
FDI_CTX_PRX_P0
<8>
FDI_CTX_PRX_P1
<8>
1
AV43
AY45
+RTCVCC
AV45
AW44
DSWVREN
AL39
FDI_CSYNC
AL40
AT45
FDI_INT
FDI_IREF
+1.5VS
AU42
1 330K_0402_5%
DSWVREN must be always pulled high to +RTCVCC
<6>
<6>
2
RH152
*
：：
DSWVREN - Internal Deep Sleep 1.05V regulator
H Enable
L Disable
AU44
AR44
FDI_RCOMP 1
RH49
2
+1.5VS
7.5K_0402_1%
DMI_RCOMP
SUSACK#
DSWVRMEN
SYS_RESET#
DPWROK
SYS_PWROK
WAKE#
PWROK
System Power
Management
APWROK
CLKRUN#
SUS_STAT#/GPIO61
DRAMPWROK
SUSCLK/GPIO62
RSMRST#
SLP_S5#/GPIO63
SUSWARN#/SUSPWRNACK/GPIO30
SLP_S4#
PWRBTN#
SLP_S3#
ACPRESENT/GPIO31
SLP_A#
BATLOW#/GPIO72
SLP_SUS#
RI#
PMSYNCH
TP21
SLP_LAN#
C8
DSWVREN
L13
PCH_RSMRST#
K3
EC_SWI#
2
EC_SWI#
<39,44>
Change PCIE_WAKE# to EC_SWI# for common net name
AN7 PM_CLKRUN#
U7
SUS_STAT#
@
TP@
T90
PAD
CLK_EC
Y7
1
PM_CLKRUN#
32.768 KHz
Y6
RH172
2
10K_0402_5%
<44>
PM_SLP_S5# <44>
C6
PM_SLP_S4# <44>
H1
PM_SLP_S3# <44>
F3
PM_SLP_A#
T92
PAD TP@
F1
PM_SLP_SUS#
T91
PAD TP@
AY3
H_PM_SYNC
<5>
+3VALW_PCH
G5
SLP_WLAN#/GPIO29
EC_SWI#
RH1711
2 10K_0402_5%
DH82LPMS-QC4C-A1_FCBGA695~D 4 OF 11
HM86R1@
3
3
DH9
PM_PWROK
SUSACK#_R
2
@
RH289
1 PCH_SUSPWRDN#_R
0_0402_5%
2
1
PCH_RSMRST#
CH751H-40PT_SOD323-2
DH10
4
Stuff RH289 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit
<44,50>
1
POK
2
CH751H-40PT_SOD323-2
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
PCH_DMI/FDI/PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
28
of
57
A
B
C
D
E
1
1
Y45
AB1
PCH_GPIO73
1
RH95
2
CLKREQ_LAN#
AA44
AA42
10K_0402_5%
AF1
LAN
<39>
CLK_LAN#
<39>
CLK_LAN
<39>
AB43
AB45
AF3
CLKREQ_LAN#
CLKREQ_LAN#
<38> CLK_WLAN#
WLAN <38> CLK_WLAN
<38> CLKREQ_WLAN#
CLKREQ_WLAN#
AD43
AD45
T3
AF43
AF45
V3
2
PCH_GPIO44
AE44
AE42
AA2
PCH_GPIO45
AB40
AB39
AE4
AJ44
AJ42
Y3
PCH_GPIO46
AH43
AH45
EMI@
<44>
CLK_PCI_EC
1
2 CLK_EC_R
D44
RH7
22_0402_5%
1 Rshort@ 2 CLK_PCILOOP_R E44
CLK_PCILOOP
RH6
0_0402_5%
1
B42
CH29
F41
22P_0402_50V8J
2
RF@
A40
CLKOUT_PCIE_N_0
CLKOUT_PEG_A
CLKOUT_PCIE_P_0
CLKOUT_PEG_A_P
PCIECLKRQ0#/GPIO73
PEGA_CLKRQ#/GPIO47
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PCIECLKRQ1#/GPIO18
PEGB_CLKRQ#/GPIO56
CLKOUT_PCIE_N_2
CLKOUT_DMI
CLKOUT_PCIE_P_2
CLKOUT_DMI_P
PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLOCK SIGNAL
CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44
CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
CLKOUT_PCIE_N_7
CLKOUT_PCIE_P_7
REFCLK14IN
CLKIN_33MHZLOOPBACK
PCIECLKRQ7#/GPIO46
XTAL25_IN
XTAL25_OUT
CLKOUT_ITPXDP
CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P
CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0
CLKOUTFLEX2/GPIO66
CLKOUT_33MHZ1
CLKOUTFLEX3/GPIO67
CLKOUT_33MHZ2
ICLK_IREF
CLKOUT_33MHZ3
TP19
TP18
CLKOUT_33MHZ4
DIFFCLK_BIASREF
+3VALW_PCH
AB35
CLK_PCIE_VGA#
AB36
AF6
CLK_REQ_VGA#
+3VALW_PCH
<13>
CLK_PCIE_VGA
<13>
CLK_REQ_VGA#
<13>
CLK_REQ_VGA#
VGA
1
RH104
1
RH99
2
CLKREQ_WLAN#
+3VALW_PCH
PASSWORD_CLEAR#
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
AJ39
JPW
SP@
2
RH115
RPH4
CLK_CPU_EDP# <5>
CLK_CPU_EDP <5>
AY24
AW24
PCH_CLK_DMI#
PCH_CLK_DMI
AR24
AT24
CLKIN_GND1#
CLKIN_GND1
H33
G33
CLK_DOT#
CLK_DOT
BE6
BC6
CLK_SATA#
CLK_SATA
F45
D17
CLK_14M_PCH
CLK_PCILOOP
AM43
AL44
PCH_X1
PCH_X2
C40
CLK_FLEX0
T72
PAD TP@
F38
CLK_FLEX1
T74
PAD TP@
F36
CLK_FLEX2
F39
1
DGPU_PRSNT#
RH261
ICLK_IREF
1
2
3
4
PCH_CLK_DMI
PCH_CLK_DMI#
CLKIN_GND1
CLKIN_GND1#
From Clock Gen.
T73
CLK_DOT#
CLK_DOT
CLK_SATA#
CLK_SATA
CLK_14M_PCH
RH80
RH81
RH83
RH84
RH87
@
AN44
PCH_CLK_BIASREF1
RH52
2
7.5K_0402_1%
RH42
1
2
0_0402_5%
GCLK@
+1.05V_+1.5V_RUN
<38>
PCH_X1_R
1
RH119
@
2
10K_0402_5%
PCH_GPIO46
PCH_X1
3
2 OF 11
Placement near to YH2
M/B SKU
NOGCLK@
2
1 1M_0402_5%
NOGCLK@YH2 25MHZ_20PF_7V25000016
DGPU_PRSNT#
PCH_GPIO44
PCH_GPIO45
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+1.5VS
RH117
2
10K_0402_5%
2
2
2
2
2
AD39
AD38
H
PCH_X1
L
CH26
1
RH112
1
1
1
1
1
PAD TP@
PCH_GPIO73
2
10K_0402_5%
2
2
10K_0402_5%
10K_0402_5%
@
8
7
6
5
10K_0804_8P4R_5%
DGPU_PRSNT#
1
RH110
1
10K_0402_5%
CLK_CPU_SSC_EDP# <5>
CLK_CPU_SSC_EDP <5>
AF35
AF36
AM45
<5>
<5>
2
PASSWORD_CLEAR#
10K_0402_5%
@
1
10K_0402_5%
Y38
U4
3
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
2
RH89
Y39
1
Y43
+3VS
LPT_PCH_M_EDS
2
UH1C
UMA
OPT
27P_0402_50V8J
NOGCLK@
1
1
1
3
GND
GND
2
4
3
PCH_X2
1
CH27
27P_0402_50V8J
2 NOGCLK@
2
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2015/04/19
Title
PCH_CLOCK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
29
of
57
A
B
C
D
E
1
1
+3VS
RPH2
1
10K_0402_5%
2
RH47
SERIRQ
1
2
3
4
LPT_PCH_M_EDS
UH1D
8
7
6
5
3
PCH_SMBDATA
PCH_SMBCLK
PCH_SMLDATA1
PCH_SMLCLK1
4.7K_0402_5%
4.7K_0402_5%
4
PM_SMBDATA <11,12,38,45>
2
+3VS
RH102
RH103
5
+3VALW_PCH
QH3B
12N7002KDWH_SOT363-6
6
PM_SMBCLK <11,12,38,45>
2.2K_8P4R_5%
LPC_AD2
<44>
LPC_AD3
A18
C18
B21
LPC_FRAME#
D21
G20
<44>
2
AL11
SERIRQ
SERIRQ
SMBALERT#/GPIO11
LAD_0
SMBus
SMBCLK
LAD_1
LAD_2
SMBDATA
SML0ALERT#/GPIO60
LAD_3
SML0CLK
LFRAME#
SML0DATA
LDRQ0#
SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23
SML1CLK/GPIO58
SERIRQ
SML1DATA/GPIO75
PCH_SPICLK
AJ11
PCH_SPICS0#
AJ7
AL7
AJ10
AH1
PCH_SPIDO1
AH3
PCH_SPIDO2
PCH_SPIDO3
AJ4
AJ2
CL_DATA
C-Link
SPI_CS0#
CL_RST#
PCH_SMBALERT#
R10 PCH_SMBCLK
+3VS
U11 PCH_SMBDATA
N8
PCH_GPIO60
U8
PCH_SMLCLK0
R7
PCH_SMLDATA0
H6
LAN_EN
K6
PCH_SMLCLK1
3
SPI_CS2#
TP1
SPI_MOSI
TP2
Thermal
SPI_MISO
TP4
SPI_IO2
TP3
SPI_IO3
TD_IREF
DH82LPMS-QC4C-A1_FCBGA695~D
4
EC_SMB_DA2
QH4B
12N7002KDWH_SOT363-6
EC_SMB_CK2
6
LAN_EN
<13,24,37,44>
<13,24,37,44>
<39>
QH4A
2N7002KDWH_SOT363-6
2
N11 PCH_SMLDATA1
AF11
+3VALW_PCH
AF10
AF7
SPI_CS1#
SPI
PCH_SPIDI
CL_CLK
SPI_CLK
N7
5
LPC_AD1
<44>
C20
LPC
<44>
<44>
A20
LPC_AD0
2
<44>
QH3A
2N7002KDWH_SOT363-6
PCH_SMBALERT#
RH2621
2 10K_0402_5%
PCH_GPIO60
RH76 1
2 1K_0402_5%
LAN_EN
RH75 1
2 10K_0402_5%
PCH_SMLCLK0
RH73 2
1 2.2K_0402_5%
PCH_SMLDATA0
RH77 2
1 2.2K_0402_5%
BA45
BC45
BE43
BE44
AY43
PCH_TD_IREF 1
RH337
2
8.2K_0402_1%
3 OF 11
HM86R1@
+3VALW_PCH
3
3
SPI ROM for Win8 (8MByte )
2
1 1K_0402_5%
PCH_SPIDO2
RH16 2
1 1K_0402_5%
PCH_SPIDO3
RH5
+3VALW_PCH
CH10
1
0.1U_0402_10V7K
2
UH4
<44>
<44>
EC_CS0#
PCH_SPIDO1
PCH_SPIDO2
RH62 1 885@
RH96 1
RH97 1
RH79 1 885@
EC_SDIO
2 15_0402_5% PCH_SPICS0#
1
8
VCC 7
2 15_0402_5% PCH_SPI0_DO1 2 CS#
PCH_SPI0_DO3
HOLD# 6
2 15_0402_5% PCH_SPI0_DO2 3 SO
PCH_SPI0_CLK
SCLK 5
4 WP#
PCH_SPI0_DI
GND
SI
2 15_0402_5%
64M EN25QH64-104HIP SOP 8P
2 15_0402_5% PCH_SPIDO3
RH92 1
PCH_SPICLK
RH93 1 Rshort@ 2 0_0402_5%
2 15_0402_5% PCH_SPIDI
RH94 1
RH74 1 885@
2 15_0402_5%
RH78 1 885@
2 15_0402_5%
EC_SCK
EC_SDI
<44>
<44>
Socket: SP07000F500/SP07000H900
Please place UH4 close to UH1 PCH
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
PCH_LPC/SPI/SMBUS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
30
of
57
A
B
C
D
E
+3VS
CRT@
2
1
UMA_CRT_DATA
RH142
2.2K_0402_5%
CRT@
2
1
UMA_CRT_CLK
RH144
2.2K_0402_5%
1
1
RH155
150_0804_8P4R_1%
8
7
6
5
1
2
3
4
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
CRT@
2
EC_ENBKL
100K_0402_5%
+3VS
10K_0402_5%
1
RH188
2
10K_0402_5%
1
RH181
2
PCH_GPIO52
DGPU_RST#
UMA_CRT_B
<26>
UMA_CRT_G
<26>
UMA_CRT_R
<26>
UMA_CRT_CLK
<26>
UMA_CRT_DATA
<26>
UMA_CRT_HSYNC
<26>
UMA_CRT_VSYNC
UMA_CRT_B
T45
UMA_CRT_G
U44
UMA_CRT_R
V45
UMA_CRT_CLK
M43
UMA_CRT_DATA
M45
N42
N44
CRT_IREF
U40
DGPU_PWR_EN
U39
2
VGA_BLUE
DDPB_CTRLCLK
VGA_GREEN
DDPB_CTRLDATA
VGA_RED
DDPC_CTRLCLK
VGA_DDC_CLK
DDPC_CTRLDATA
CRT
8.2K_0402_5% RH332
1
2
LPT_PCH_M_EDS
UH1E
<26>
VGA_DDC_DATA
DDPD_CTRLCLK
VGA_HSYNC
DDPD_CTRLDATA
VGA_VSYNC
DISPLAY
1
RH125
DAC_IREF
VGA_IRTN
DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
PCH_PWM
<22,23,44>
EC_ENBKL
PCH_PWM
1
2
EC_ENBKL_R
R462 IEDP@ 0_0402_5%
<23>
RPH3
8
7
6
5
K36
G36
LCD_ENVDD
+3VS
1
2
3
4
N36
ODD_DA#
PCH_GPIO4
PCH_GPIO5
PCI_PIRQC#
PCI_PIRQA#
H20
PCI_PIRQB#
L20
PCI_PIRQC#
K17
PCI_PIRQD#
M20
DGPU_RST#
A12
PCH_GPIO52
B13
10K_0804_8P4R_5%
<17>
DGPU_PWR_EN C12
DGPU_PWR_EN
C10
A10
RPH6
1
2
3
4
8
7
6
5
AL6
PCH_GPIO2
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQA#
EDP_BKLTCTL
DDPB_AUXP
LVDS
<22,23>
EDP_BKLTEN
DDPC_AUXP
EDP_VDDEN
DDPD_AUXP
DDPB_HPD
PIRQA#
DDPC_HPD
PIRQB#
DDPD_HPD
R40
PIRQE#/GPIO2
GPIO50
PIRQF#/GPIO3
PCI
GPIO52
PIRQG#/GPIO4
GPIO54
PIRQH#/GPIO5
GPIO51
PME#
GPIO53
PLTRST#
UMA_HDMI_DATA
<24,25>
R35
N40
N38
H45
K43
2
J42
H43
K45
J44
K40
HDMI_HPD
K38
1
RH127
1
RH128
H39
G17
PCH_GPIO2
F17
ODD_DA#
L15
PCH_GPIO4
M15
PCH_GPIO5
AD10
PCI_PME#
Y11
PLT_RST#
HDMI_HPD
<24,25,33>
2
100K_0402_5%
2
100K_0402_5%
ODD_DA#
ESD@
2
ODD_DA# 1
CH6
180P_0402_50V8J
<37>
ESD@
PLT_RST#
CH104
100P_0402_50V8J
PAD T93 TP@
PLT_RST#
<38,39,44>
GPIO55
DH82LPMS-QC4C-A1_FCBGA695~D
5 OF 11
For Optimus
HM86R1@
3
<24,25>
R36
PIRQC#
PIRQD#
UMA_HDMI_CLK
R39
3
10K_0804_8P4R_5%
+3VS
1K_0402_5% 1
2 RH296 DGPU_PWR_EN
@
LPC
2
Reserved
SPI
1
*
UH6
P
2
IN1
O
4
PLTRST_VGA#
<13>
IN2
SN74AHC1G08DCKR_SC70-5
CH12
OPT@
0.47U_0402_6.3V6K
@
PLT_RST#
Low= A16 swap override Enable
High= A16 swap override Disable
2
*
1
DGPU_RST#
Reserved
A16 Swap Override Strap
WL_OFF#
PLT_RST#
G
0
1
0
1
0
0
1
1
Boot BIOS Loaction
3
PCH_GPIO19
5
Boot BIOS Strap
RF_OFF#
PCH_GPIO51
RH173
100K_0402_5%
4
1
CRT Disabling
4
CRT@
1
RH126
2
RH126
CRT_IREF
649_0402_1%
NOCRT@
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1K_0402_5%
2015/04/19
Deciphered Date
Title
PCH_CRT/LVDS/HDMI/PCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
31
of
57
B
C
UH1I
AW31
AY31
BE32
BC32
1
AT31
AR31
BD33
BB33
LAN
<39> PCIE_PTX_C_LANRX_N3
<39> PCIE_PTX_C_LANRX_P3
WLAN
AW33
AY33
<39> PCIE_PRX_C_LANTX_N3
<39> PCIE_PRX_C_LANTX_P3
CH13 2
CH11 2
1 0.1U_0402_10V7K PCIE_PTX_LANRX_N3
1 0.1U_0402_10V7K PCIE_PTX_LANRX_P3
AT33
AR33
<38> PCIE_PRX_WLANTX_N4
<38> PCIE_PRX_WLANTX_P4
<38> PCIE_PTX_C_WLANRX_N4
<38> PCIE_PTX_C_WLANRX_P4
BE34
BC34
CH14 2
CH17 2
1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4 BE36
1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4 BC36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
2
BE40
BC40
AN38
AN39
BD42
BD41
+1.5VS
PCIE_IREF
BE30
BC30
BB29
+1.5VS
1
RH53
2
PCIE_RCOMP
7.5K_0402_1%
BD29
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
EHCI 1
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
EHCI 2
PETN_4
PETP_4
PERN_5
PERP_5
PCIe
AW36
AV36
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
D
E
LPT_PCH_M_EDS
USB
A
NA
NA
PETN_8
PETP_8
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
PCIE_IREF
TP24
TP23
TP11
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
TP6
PCIE_RCOMP
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
<41>
<41>
<41>
<41>
<39>
<39>
<40>
<40>
USB20_N8
USB20_P8
USB20_N9
USB20_P9
<23>
<23>
<38>
<38>
USB20_N11
USB20_P11
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
<23>
<23>
U3RXDN1
U3RXDP1
U3TXDN1
U3TXDP1
U3RXDN2
U3RXDP2
U3TXDN2
U3TXDP2
USB-Right Rear
USB-Right Front
USB-Left
1
CardReader
Touch Screen
WiMAX/BT
Int. Camera
<41>
<41>
<41>
<41>
<41>
<41>
<41>
<41>
2
+3VALW_PCH
1
RH183
2
10K_0402_5%
USB_CHG_OC#1
RH186
2
10K_0402_5%
USB_OC#2
K24
K26
M33
L33
USBBIAS
1
RH165
2
22.6_0402_1%
Within 500 mils
P3 USB_OC#0
V1 USB_CHG_OC#
U2 USB_OC#2
P1 SLP_CHG_CB1
M3 SLP_CHG_CB0
T1
N2
M1
USB_OC#5
USB_OC#0 <41,44> USB-Right
USB_CHG_OC# <41,44>
USB-Right
USB_OC#2 <39,44> USB-Left
SLP_CHG_CB1 <41>
SLP_CHG_CB0 <41>
+3VALW_PCH
Rear
Front
RPH5
1
USB_OC#0
SLP_CHG_CB1 2
3
USB_OC#5
SLP_CHG_CB0 4
8
7
6
5
10K_0804_8P4R_5%
DH82LPMS-QC4C-A1_FCBGA695~D 9 OF 11
HM86R1@
3
3
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCH_PCIE/USB
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
32
of
57
A
B
C
AT8
HDMI_HPD
F13
PCH_GPIO1
1
<44>
EC_SCI#
<44>
EC_SMI#
PCH_GPIO6
A14
EC_SCI#
G15
EC_SMI#
Y1
K13
AB11
+3VS
RPH7
1
2
3
4
8
7
6
5
<17,55>
PCH_GPIO49
PCH_GPIO39
PCH_GPIO16
PCH_GPIO34
AN2
PCH_GPIO16
For OPT
C14
VGA_PWROK
VRAM_DR_SR# BB4
Y10
R11
10K_0804_8P4R_5%
PCH_GPIO27
RPH8
PCH_GPIO34
AN6
PCH_GPIO35
AP1
AD11
1
2
3
4
8
7
6
5
SPK_DET
PCH_GPIO71
EC_SCI#
ODD_EN#
TP@ T81 PAD
<37>
ODD_DETECT# AT3
ODD_DETECT#
PCH_GPIO37
AK1
OPTIMUS_EN#
AT7
PCH_GPIO39
AM3
SM_DET
AN4
PCH_GPIO49
AK3
10K_0804_8P4R_5%
+3VALW_PCH
RPH9
2
1
2
3
4
+3VS
8
7
6
5
EC_SMI#
PCH_GPIO1
PROJECT_ID
PCH_GPIO6
U12
10K_0804_8P4R_5%
<46>
<43>
+3VS
1
RH185
ODD_EN#
SPK_DET
ODD_EN#
C16
PROJECT_ID
D13
SPK_DET
G13
PCH_GPIO71
H15
DRANK@
2
VRAM_DR_SR#
10K_0402_5%
1
RH178
BE41
BE5
C45
A5
2
ODD_DETECT#
200K_0402_5%
1 269@
RH304
2
SM_DET
10K_0402_5%
+3VS
BMBUSY#/GPIO0
TACH1/GPIO1
KB_RST#
CPU/Misc
TACH3/GPIO7
1
H_THERMTRIP#
LAN_PHY_PWR_CTRL/GPIO12
TP14
GPIO15
PECI
SATA4GP/GPIO16
RCIN#
GPIO
TACH0/GPIO17
PROCPWRGD
SCLOCK/GPIO22
THRMTRIP#
GPIO24
PLTRST_PROC#
GPIO27
VSS
AN10
GATEA20
AV3
AV1
GPIO35/NMI#
SATA2GP/GPIO36
SATA3GP/GPIO37
SLOAD/GPIO38
SDATAOUT0/GPIO39
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
VSS
VSS
VSS
VSS
NCTF
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
2
6 OF 11
UMA
Optimus
SKU
SharkBay SV
SharkBay ULT
1
10K_0402_5%
<5>
<5>
GPIO34
SKU
2
RH201
<5>
N10
L
PCH_GPIO27
H_THERMTRIP#
GPIO28
H
1
10K_0402_5%
<44>
CPU_PLTRST#
PROJECT_ID
SM_DET
259@ 2
10K_0402_5%
2
390_0402_5%
AU4
L
@
KB_RST#
H_PWRGOOD
PCH_THRMTRIP#1
RH191
H
1
RH307
<44>
2
100P_0402_50V8J
@ESD@
KB_RST#
OPTIMUS_EN#
2
RH199
GATEA20
1
CH7
AY1
AT6
OPTIMUS_EN#
PCH_GPIO37
2
10K_0402_5%
2
10K_0402_5%
GPIO8
1
RH198
2
10K_0402_5%
1
RH182
1
RH184
GATEA20
TACH2/GPIO6
SRANK@
1
2
VRAM_DR_SR#
RH187
10K_0402_5%
3
E
LPT_PCH_M_EDS
UH1F
<24,25,31>
D
PROJECT_ID
SM_DET
BIOS setup
Speaker Type
BOM
1
S&M option
Harman/Kardon
269@
Non Harman
259@
3
0
Non-Harman detection
OPTIMUS_EN#
Follow Compal ORB
and Intel Check list 460603 V1.5
0
ONKYO
1
Non-Brand
SPK_DET
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCH_CPU/GPIO
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
33
of
57
A
B
C
D
E
+1.5VS
1
RH20
+VCCA_DAC
LPT_PCH_M_EDS
UH1G
CH35
1
0.1U_0402_10V7K
1
CH36
CH37
1
1
1
LH1
2 +VCCA_DAC_R
0_0402_5%
Rshort@
2
1
BLM18PG181SN1D_0603
CRT@
+1.05VS_VCCP
0.07A
JP@ PJ4
2
2
1
1
JUMP_43X79
CH32
10U_0603_6.3V6M
1
2
CH33
1
CH31
2
1
CH34
2
1U_0402_6.3V6K
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
Y26
+1.05VS_PCH
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
0.0133A
U14
+PCH_VCCDSW
AA18
1U_0402_6.3V6K
U18
U20
1
1
1
U22
CH64 CH67 CH68
U24
V18
2
2
2
V20
V22
V24
22U_0805_6.3V6M
1U_0402_6.3V6K
Y18
Y20
Y22
2
RH9
5.1_0402_1%
1
2
1
2
CH50
1U_0402_6.3V6K
VCCADACBG3_3
0.183A
VCCIO
VCCIO
HVCMOS
VCC3_3_R30
VCC3_3_R32
0.133A
DCPSUS1
VCCSUS3_3
VCCSUS3_3
0.261A
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
USB3
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW 0.67A
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCVRM
PCIe/DMI
VCCIO
VCCVRM
SATA
VCCIO
VCCMPHY
HM86R1@
VCCVRM
FDI
1.312A
+1.05VS_PCH
+PCH_VCCDSW
VSS
CRT DAC
Core
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCADAC1_5
3.629A
DH82LPMS-QC4C-A1_FCBGA695~D
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
P45
CRT@
0.01U_0402_16V7K 2
CRT@
CRT@
2
2
10U_0603_6.3V6M
P43
M31
+VCCADACBG3_3
BB44
+VCCAFDI_VRM
Voltage Rail
1
+1.05VS_PCH
AN34
AN35
+3VS
1
R30
R32
Y12
PCH Power Rail Table (EDS Rev1.0)
+1.05V_+1.5V_RUN
+3VALW_PCH
+VCCA_USBSUS1
AJ30
AJ32
+1.05VS_PCH
AJ26 +VCCA_USBSUS3
AJ28
AK20
AK26
AK28
1
2
1
2
2
CH44
2
CH41
@
10U_0603_6.3V6M
CH43
CH45
0.1U_0402_10V7K
VCCADAC1_5
1.5V
0.07 A
VCCADAC3_3
3.3V
0.0133 A
VCCCLK
1.05V
0.306 A
VCCCLK3_3
3.3V
0.055 A
VCCVRM
1.5V
0.183 A
VCC3_3
3.3V
0.133 A
VCCASW
1.05V
0.67 A
2
AN11
+1.05V_+1.5V_RUN
AM18
AM20
AM22
AP22
AR22
AT22
+1.05VS_PCH
1
7 OF 11
1U_0402_6.3V6K 1U_0402_6.3V6K
1
1
1
1
CH99
CH97
CH57
CH80
+1.05V_+1.5V_RUN
Rshort@
1
3.629 A
+1.05VS_PCH
2
2
2
2
2
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
RH70
1.05V
AK22
CH98
+1.5VS
1.312 A
VCCIO
0.1U_0402_10V7K
+1.05V_+1.5V_RUN
AK18
S0 Iccmax Current (A)
1.05V
1U_0402_6.3V6K
+1.05V_+1.5V_RUN
BE22
Voltage
VCC
VCCSUSHDA
3.3V
0.01 A
VCCSPI
3.3V
0.022 A
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
1.05V
0.004 A
+1.05VS_PCH
2
0_0603_5%
+VCCA_USBSUS1 1
1
3
CRT Disabling
@
RH59
0_0402_5%
CH53
@
10U_0603_6.3V6M
3
+3VS
2
2
2
RH4
0_0402_5%
CRT@
+3VALW to +3VALW_PCH
2
+VCCA_USBSUS3 1
RH60
@ 0_0402_5%
1
1
CH102
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
+3VALW_PCH
JP@
2
PJ2
2
2
+VCCADACBG3_3
CH103
1
1 JUMP_43X39
RH19
0_0402_5%
NOCRT@
1
+3VALW
1
+1.05VS_PCH
QH2
AO3413_SOT23
+VCCA_DAC
PCH_PWR_EN#
PCH_PWR_EN#
2
RH3
2
CH113
0.1U_0402_10V7K
RH21
0_0402_5%
NOCRT@
1
1
CH112
0.01U_0402_25V7K
2
CH111
0.1U_0402_25V6
<46>
2
G
4
1
D
1
S
3
2
1
47K_0402_5%
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCH_POWER-1
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
34
of
57
A
B
C
D
E
Check use which power rail
+3VALW_PCH
+VCCDSW3_3
LPT_PCH_M_EDS
UH1H
+3VALW_PCH
1
CH65
+1.05VS_PCH
0.1U_0402_10V7K
2
M24
1
U35
L24
0.1U_0402_10V7K
1
2
2
+1.05VS_PCH
CH73
CH81
+1.05VS_PCH
1U_0402_6.3V6K
1
2
U30
V28
V30
Y30
0.1U_0402_10V7K
1
+1.05V_+1.5V_RUN
2
CH83
1
2
CH78
1U_0402_6.3V6K
@
Y35
AF34
+V1.05M_VCCDUSBSUS
@
RH63 0_0402_5%
+V1.05M_VCCDUSBSUS
10U_0603_6.3V6M
1
AP45
+PCH_VCC
Y32
+PCH_VCCCLK
2
M29
+PCH_VCCCLK3_3
L29
+1.05VS_PCH
L26
M26
2
1
2
4.7UH_LQM18FN4R7M00D_20%
+PCH_VCC
AD34
+PCH_VCCCLK
CH84
10U_0603_6.3V6M
1
1
2
AA30
AA32
CH79
1U_0402_6.3V6K
2
AD35
AG30
AG32
Place near pin AP45
AD36
AE30
AE32
0.015A
VCCDSW3_3
VSS
DCPSST
VCCUSBPLL
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
CH72
2
A16
+VCCDSW3_3
CH70
1
+VCCSST
AA14
0.01A
VCCSUSHDA
1
RH71
2
RH88
VCCSUS3_3
VCCCLK
VCCRTC
RTC
VCCCLK3_3
DCPRTC
DCPRTC
1
0.055A
VCCCLK3_3
VCCCLK3_3
CPU
0.004A
V_PROC_IO
V_PROC_IO
0.022A
SPI
VCCSPI
VCCCLK
VCC
VCC
VCCCLK
VCCCLK
VCCASW
VCCCLK
VCCASW
VCCCLK
VCCCLK
0.306A
VCCVRM
VCCCLK
VCC3_3
Thermal
VCCCLK
VCCCLK
VCC3_3
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
2
0.1U_0402_10V7K
2
+3VS
CH74
U36
+3VALW_PCH
0.1U_0402_10V7K
+1.05VS_PCH
1
+3VALW_PCH
A26
2
K8
1
+RTCVCC
A6
P14
P16
CH95
1
+DCPRTC
0.1U_0402_10V7K
2
0.1U_0402_10V7K
1
AJ12
AJ14
+V_PROC
+3VALW_PCH
CH77
1
2
2
0.1U_0402_10V7K
2
PCH Power Rail Table (EDS Rev1.0)
Voltage Rail
1
2
CH75
0.1U_0402_10V7K
CH93
1
+VCCCFUSE
2
+1.05V_+1.5V_RUN
1U_0402_6.3V6K
RH13
0_0805_5%
1 Rshort@ 2
+V_PROC
0.1U_0402_10V7K
1
1
1
CH109
CH108 CH107
+3VS
AK30
2
2
0.1U_0402_10V7K
AK32
1
8 OF 11
2
1.05V
1.312 A
3.629 A
VCCADAC1_5
1.5V
0.07 A
VCCADAC3_3
3.3V
0.0133 A
VCCCLK
1.05V
0.306 A
VCCCLK3_3
3.3V
0.055 A
VCCVRM
1.5V
0.183 A
VCC3_3
3.3V
0.133 A
VCCASW
1.05V
0.67 A
2
1U_0402_6.3V6K
+1.05VS_PCH
AW40
VCCIO
2
CH96
L17
R18
S0 Iccmax Current (A)
1.05V
1
CH76 CH94
AD12
P18
P20
Voltage
VCC
1U_0402_6.3V6K
+1.05VS_PCH
2
1U_0402_6.3V6K
CH106
0.1U_0402_10V7K
+VCCCFUSE
1
+1.05VS_PCH
+3VALW
0_0402_5%
AE14
AF12
AG14
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
+3VALW_PCH
@
VCCVRM
VCC
2
0_0402_5%
1
0.1U_0402_10V7K
Azalia
DCPSUS2
ICC
U32
V32
LH2
VCCSUS3_3
VCCSUS3_3
0.1U_0402_10V7K
GPIO/LPC
USB
CH69
+3VS
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
R20
R22
1
1
CH66
R24
R26
R28
U26
1
+PCH_VCCCLK
CH110
RH14
0_0805_5%
1 Rshort@ 2
+1.05VS_PCH
RH15
0_0805_5%
1
2
@
+3VS
VCCSUSHDA
3.3V
0.01 A
VCCSPI
3.3V
0.022 A
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
1.05V
0.004 A
2
RH10
0_0805_5%
1
2
1U_0402_6.3V6K
Rshort@
1
1
CH85
1U_0402_6.3V6K
2
1
CH86
1U_0402_6.3V6K
2
CH87
1U_0402_6.3V6K
2
1
CH88
1U_0402_6.3V6K
2
3
3
Place near pin Y32,AA30,AA32
+3VS
Place near pin AD34
Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+PCH_VCCCLK3_3
1
RH11
0_0805_5%
2
Rshort@
1
CH89
1U_0402_6.3V6K
2
Place near pin M29
1
CH90
1U_0402_6.3V6K
2
Place near pin L29
1
1
CH91
1U_0402_6.3V6K
2
Place near pin L26,M26
CH92
1U_0402_6.3V6K
2
Place near pin U32,V32
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
PCH_POWER-2
Size Document Number
Custom
Rev
1.0
VSKAA
Date:
Sheet
Friday, May 10, 2013
E
35
of
57
A
B
C
D
E
1
1
UH1J
AL34
AL38
AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36
AN40
AN42
AN8
AP13
AP24
AP31
AP43
AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
D42
AV13
AV22
AV24
AV31
AV33
BB25
AV40
AV6
AW2
F43
AY10
AY15
AY20
AY26
AY29
AY7
B11
B15
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LPT_PCH_M_EDS
UH1K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8
AA16
AA20
AA22
AA28
AA4
AB12
AB34
AB38
AB8
AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AD6
AD8
AE16
AE28
AF38
AF8
AG16
AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AJ6
AJ8
AK14
AK24
AK43
AK45
AL12
AL2
BC22
BB42
LPT_PCH_M_EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
2
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
11 OF 11
DH82LPMS-QC4C-A1_FCBGA695~D
HM86R1@
10 OF 11
3
3
4
4
2012/04/19
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCH_GND
Rev
1.0
VSKAA
Date:
A
B
C
D
Friday, May 10, 2013
Sheet
E
36
of
57
A
B
C
D
E
SATA HDD Conn.
G-Sensor
Close to JHDD
JHDD
Conn@
GND
RX+
RXGND
TXTX+
GND
1
26
25
boss
boss
24
23
GND
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P4
SATA_PTX_C_DRX_N4
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P4 <27>
SATA_PTX_DRX_N4 <27>
UG1
+3VS_HDP
SATA_PRX_C_DTX_N4 <27>
SATA_PRX_C_DTX_P4 <27>
2
12
SELF_TEST
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
4
6
8
GSENSOR@
Vdd1
Vdd2
ST
PD
FS
NC1
NC2
NC3
NC4
NC5
+3VS
+5VS
CG12
1U_0402_6.3V6K
GSENSOR@
+5VS
+5VS
1.2A
2
2
UG3
1
1
C357
0.1U_0402_10V7K
2
1
C358
0.1U_0402_10V7K
SHDN#
BP
9
Rev
GND1
GND2
3
5
7
VOUTXCG1
VOUTYCG2
VOUTZCG3
GSENSOR@
1
2
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2GSENSOR@
0.033U_0402_16V7K
GSENSOR@
10
11
14
15
16
1
1
13
TSH352TR LGA 16P
CG13
1U_0402_6.3V6K
1 GSENSOR@
5
GND
3
1
C356
10U_0805_10V4Z
VOUT
+3VS_HDP
2
GSENSOR@
VIN
2
Place closely JHDD SATA CONN.
1
SANTA_191501-1
+3VS_HDP
Voutx
Vouty
Voutz
Place UG1 and UG4
on TOP Layer
4
G9191-330T1U_SOT23-5
2
UG5
SATA ODD Conn
+5VS_ODD
1.1A
2
2
15
14
GND
GND
P1_6/CLK0/SSI01
P3_7/CNTR0#/SSO/TXD1
P1_5/RXD0/CNTR01/INT11#
11
HDPACT
2
8
9
10
11
12
13
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
C376 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
C378 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD_DETECT#
1
2
3
4
8
7
6
5
RESET#
GXOUT
GXIN
MODE
3
GXOUT
4
5
6
GXIN
7
+3VS_HDP
SATA_PTX_DRX_P2 <27>
SATA_PTX_DRX_N2 <27>
8
MODE
SATA_PRX_C_DTX_N2 <27>
SATA_PRX_C_DTX_P2 <27>
RG7
HDPINT
2
1 1K_0402_5%
GSENSOR@
<33>
1
+5VS_ODD
ODD_DA#
RESET#
RPG1
C372
0.1U_0402_10V7K
4.7K_8P4R_5%
GSENSOR@
1
2
3
4
5
6
7
12
<44>
RG9
47K_0402_5%
GSENSOR@
CG7
0.1U_0402_10V7K
GSENSOR@ 2
<31>
9
RESET#
P1_4/TXD0
XOUT/P4_7
P1_3/KI3#/AN11/TZOUT
VSS/AVSS
P1_2/KI2#/AN10/CMP0_2
XIN/P4_6
P4_2/VREF
VCC/AVCC
P1_1/KI1#/AN9/CMP0_1
MODE
P1_0/KI0#/AN8/CMP0_0
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
10
1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_10V7K
R5F211B4D34SP
2
P3_4/SCS#/SDA/CMP1_1
13
1
1
C380
0.1U_0402_10V7K
<44>
DP
+5V
+5V
MD
GND
GND
P3_5/SSCK/SCL/CMP1_2
+3VS_HDP
1
C355
10U_0805_10V4Z
Conn@
GND
A+
AGND
BB+
GND
2
SELF_TEST
Place components closely ODD CONN.
1
2
JODD
1
EC_SMB_CK2
2
<13,24,30,44>
2
14
15
HDPLOCK
VOUTZ
<44>
RG10 47K_0402_5%
2
1
GSENSOR@
16
+3VS_HDP
17
VOUTX
18
VOUTY
1
2
CG6
0.1U_0402_10V7K
GSENSOR@
19
20
EC_SMB_DA2
<13,24,30,44>
GSENSOR@
SANTA_202401-1
3
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
HDD/Gsensor
Document Number
Rev
1.0
VSKAA
Sheet
Thursday, May 09, 2013
E
37
of
57
A
B
C
D
Slot 1 Half PCIe Mini Card-WLAN
E
Slot 2 Full PCIe Mini Card- mSATA 14" no support
WLAN&BT Combo module circuits
40 mils
+3V_WLAN
1
1
0.1U_0402_10V7K
1
CM1
CM2
BT
on module
BT
on module
Enable
Disable
H
L
BT_ON
1
1
CM3
2
0.1U_0402_10V7K
2
2
4.7U_0603_6.3V6K
<44>
BT_ON
BT_ON
1 RM27 2 E51_RXD
1K_0402_5%
For isolate Intel Rainbow Peak and
Compal Debug Card.
+3V_WLAN
JWLAN
To EC
(Need pull-up +3VL)
<44>
WLAN_WAKE#
<29>
CLKREQ_WLAN#
BT_ON
<29>
<29>
2
1 RM25 2 BT_CTRL_R
@ 0_0402_5%
CLK_WLAN#
CLK_WLAN
<32>
<32>
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
<32>
<32>
PCIE_PTX_C_WLANRX_N4
PCIE_PTX_C_WLANRX_P4
WLAN/ WiFi
+3V_WLAN
E51_TXD
E51_RXD
<44> E51_TXD
<44> E51_RXD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
Debug card using
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
PLT_RST#
PLT_RST#
<44>
<31,39,44>
2
PM_SMBCLK <11,12,30,45>
PM_SMBDATA <11,12,30,45>
USB20_N9
USB20_P9
<32>
<32>
WiMax/ BT
LED_WIMAX#
1
RM6
<45>
2
+3VS
100K_0402_5%
54
ACES_88914-5204
Conn@
2
CCL1
GCLK@
1
2
CCL3
GCLK@
1
2
CCL4
GCLK@
+3VALW
0.1U_0402_10V7K
1
+3VS_DGPU
0.1U_0402_10V7K
+1.05VS_VCCP
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VL
3
1
2
CCL5
GCLK@
+RTC
CCL6
22U_0805_6.3V6M
RCL4
GCLK@
120_0603_5%
2
1
+RTCGCLK
GCLK@
1
1
UCL1 GCLK@
2
10
15
+3VL
+3VALW
2
+3VS_DGPU
11
VBAT
2
VDD_RTC_OUT
3
CCL9
2.2U_0402_6.3V6M
GCLK@
14
+V3.3A
VDD
32kHz
9
PCH_RTCX1_R
<27>
GCLK@
25MHz_B
XTAL_IN
XTAL_OUT
SLG3NB304VTR_TQFN16_2X3
CLK_X1
1
1
3
GND
1
2
CCL7
18P_0402_50V8J
GCLK@
5
VGA_X1
<13>
22 ohm for NV chip
PCH_X1_R_R
GCLK@
25MHZ 12PF X3G025000DK1H-X
YCL1
4
6
2
22_0402_5%
GND4
1
16
25MHz_A
VDDIO_25M_B
GND1
GND2
GND3
CLK_X1
CLK_X2
VDDIO_25M_A
VGA_X1_R 1
RCL3
17
3
27MHz
4
7
13
8
+1.05VS_VCCP
VDDIO_27M
12
2
3
Rshort@
CLK_X2
PCH_X1_R_R
GND
4
1
2
1
RCL1
2
0_0402_5%
PCH_X1_R
<29>
4
CCL8
18P_0402_50V8J
GCLK@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
PCIe-WLAN/mSATA/GCLK
Document Number
Rev
1.0
VSKAA
Thursday, May 09, 2013
Sheet
E
38
of
57
A
B
C
D
E
1
1
Left USB 2.0 x 1
W=80mils
+5VALW
+USB_VCCC
2.0A
EMI@
<32>
2
USB20_P2
2
1
1
USB20_P2_L
<44>
<32>
3
USB20_N2
2
3
4
1
LR5
3
4
4
USB_EN#2
USB20_N2_L
IN
IN
EN/ENB
GND
+USB_VCCC
For EMI
U13
@EMI@
2
1
CR38
1000P_0402_50V7K
6
7
8
5
OUT
OUT
OUT
OCB
USB_OC#2
<32> PCIE_PRX_C_LANTX_P3
<32> PCIE_PRX_C_LANTX_N3
<32> PCIE_PTX_C_LANRX_P3
<32> PCIE_PTX_C_LANRX_N3
<32,44>
SY6288DCAC_MSOP8
SA00004KB00
SA00003TV00
WCM-2012-900T_0805
<29>
<29>
<28,44>
<31,38,44>
CLK_LAN
CLK_LAN#
EC_SWI#
PLT_RST#
+3V_LAN
W=80mils 20
19
USB20_N2_L 18
USB20_P2_L 17
16
15
14
13
12
11
10
9
8
7
6
5
4
ISOLATE#
3
LANCLK_REQ#
2
1
JLAN Conn@
24
G4 23
G3 22
G2 21
G1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
18
16
14
12
10
8
6
4
2
ACES_50559-02001-001
2
2
+3VS
For LAN function
PJ7
+3VALW_PCH
1
+3VS
1 10K_0402_5%
LANCLK_REQ#
JP@
1
1
+3V_LAN
Rshort@
2 0_0402_5%
2
WOL_EN#
<44>
G
1
3
S
CLKREQ_LAN#
D
<29>
LAN_EN
2
1K_0402_5%
RL6
@
ISOLATE# RL433 1
<30>
2
JUMP_43X39
2
RL24 2
LANCLK_REQ#
RL7
15K_0402_5%
Sx Enable Sx Disable
Wake up
Wake up
QL53
2N7002KW_SOT323-3
WOL_EN#
LOW
HIGH
S0
HIGH
3
3
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
LAN
LAN_EN
ISOLATEB
S0
Sx
S0
Sx
---------------------------------------------0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0*
4
WOL
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
4
Compal Secret Data
Security Classification
Issued Date
2012/04/19
2015/04/19
Deciphered Date
Title
Compal Electronics, Inc.
PCIe-LAN-RTL8105E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
VSKAA
Date:
A
B
C
D
Thursday, May 09, 2013
Sheet
E
39
of
57
4
3
2
1
For EMI request
(Place close to chip)
SD_DATA0
LW 1 EMI@
2
1 SD_DATA0_R
BLM15BB121SN1D_0402
SD_DATA1
LW 2 EMI@
2
1 SD_DATA1_R
BLM15BB121SN1D_0402
SD_DATA2
LW 3 EMI@
2
1 SD_DATA2_R
BLM15BB121SN1D_0402
SD_DATA3
LW 4 EMI@
2
1 SD_DATA3_R
BLM15BB121SN1D_0402
D
1
UW 1
30mils
+3VS
2
3
USB20_N3
USB20_P3
Rshort@
1
2
RW 1
0_0402_5%
+3VS_CR
+VCC_3IN1
1 CW 1
2.2U_0402_6.3V6M
please close the pin19 of UW1
30mils
19
23
20
+3VS_CR
+VDD18
4
18
1
CW 5
0.1U_0402_16V4Z
1
2
+3VS_CR
+3VS_CR
12mils
+3VS_CR
C
MS_INS
SD_D2/MS_D5/SB13
SD_D3/MS_D4/SB12
SD CMD/SD_CMD
SD CLK/SD_CLK
SD_CDZ
SD_D0/MS_D6/SB9
SD_D1/MS_D7/SB8
MS BS/MS_BS
SD_WP/MS_D1/SB5
SD_D4/MS_D0/SB4
SD_D5/MS_D2/SB3
SD_D6/MS_D3/SB1
SD_D7/MS_CLK/SB0
DM
DP
DVDD
PMOS
30mils
2
+3VS_CR
1
24
RSTZ
CW 2
0.1U_0402_16V4Z
25
DVDD
DVDD
GPIO0
AVDD
VDD18
5
17
16
15
14
21
13
12
11
10
9
8
7
6
SD_DATA2
SD_DATA3
SDCMD
SDCLK
SDCD#
SD_DATA0
SD_DATA1
SDCMD_R
2
LW 5 EMI@
2
1
BLM15BB121SN1D_0402
SDCLK_R
2
CW 14 EMI@
4.7P_0402_50V8J
1
SDW P
1
CW 9
EMI@
4.7P_0402_50V8J
EMI@
2
EMI@
2
EMI@
2
2
1
1
1
1
Thermal pad
GL834L-OGY01_QFN24_4X4
2
EMI@
LW 6 EMI@
2
1
BLM15BB121SN1D_0402
CW10
4.7P_0402_50V8J
22
<32>
<32>
CW11
4.7P_0402_50V8J
2
D
CW12
4.7P_0402_50V8J
CW 8
0.1U_0402_16V4Z
CW13
4.7P_0402_50V8J
5
NC (default)
10K pull down
GPIO0 Power saving mode Normal mode
C
please close the pin4 of UW1
De-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket
+3VS_CR
+3VS_CR
30mils
CW 3
2.2U_0402_6.3V6M
1
2
1
CW 4
0.1U_0402_16V4Z
2
< 2 in 1 Card Reader >
Close to connector
Conn@
JCARD
5
3
6
7
4
VDD
CMD
CLK
VSS
VSS
DAT0
DAT1
DAT2
CD/DAT3
1
10
11
SDW P#
SDCD
1
CW 6
0.1U_0402_16V4Z
2
SD_DATA0_R
SD_DATA1_R
SD_DATA2_R
SD_DATA3_R
30mil
+VCC_3IN1
SDCMD_R
SDCLK_R
8
9
1
2
Close to IC
CW 7
4.7U_0402_6.3V6M
2
B
B
12
13
GND_SW
GND_SW
WP_SW
CD_SW
T-SOL_156-2000302604
"Normal Close" type connector
Close
Open
Close
SDCD#
SDW P
RW 3
100K_0402_5%
RW 4
100K_0402_5%
Open
SDCD
2
QW 1A
Card Insertion
6
2
Close
D
2
G
QW 1B
SDW P#
2N7002KDW H_SOT363-6
3
Protect Enable
Close
+3VS_CR
1
Protect disable
Card Uninsertion
+3VS_CR
WP_SW
1
CD_SW
For normal close type connector invert circuit
D
5
G
S
1
2N7002KDW H_SOT363-6
4
S
A
A
Compal Secret Data
Security Classification
2012/04/19
Issued Date
Deciphered Date
2015/04/19
Title
Compal Electronics, Inc.
USB-CardReader Genesys GL834L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
VSKAA
Thursday, May 09, 2013
Sheet
1
40
of
57
5
4
3
2
1
Right side USB 3.0 x 2/ Sleep&Charge
+3VALW_PCH
U5
14641@
1
RR189
<44>
2
EC_CB0
10K_0402_5%
14641@
1
RR305
<32>
2
EC_CB1
10K_0402_5%
CHG_PWR_GATE#
@
SLP_CHG_CB1
<44>
RR2
EC_CB1
EC_CB1
RR5
+3VALW
D
USB20_N1_S
USB20_P1_S
CHG_CB1
0_0402_5%
14641@
0_0402_5%
1
2
3
4
9
0_0402_5% 14641@ RR6
EC_CB0
0_0402_5%
SLP_CHG_CB0
<44>
14641@
CEN
DM
DP
CB1
PGND
CB0
TDM
TDP
VCC
8
7
6
5
CHG_CB0
USB20_N1
USB20_P1
@
USB20_N1
USB20_P1
+5VALW
1
State table for MAX14641
RR1
<32>
<32>
<32>
C892
MAX14641ETA+TGH7_TDFN-EP8_2X2
0.1U_0402_10V7K
2
+3VALW
U5
<44,48,49>
<32>
<32>
EC_SMB_DA1
1
1
2N7002KDWH_SOT363-6 QR1B
14640@
3
Right rear USB3.0 Conn.
1
6
EC_SMB_CK1
RR4
4.7K_0402_5%
14640@
3
2
USB20_N0
WCM-2012-900T_0805
4
3
4
2
1
EMI@
LR7
AM2
2A auto-detection charger mode for Apple device.
Resistor dividers are connected to DP/DM. Including DCP
STATUS
0
1
AP1
Forced 1A charger mode for Apple devices.
Resistor dividers are connected to DP/DM.
1
0
PM
USB pass-through mode.DP/DM are connected to TDP/TDM
1
1
CM
USB pass-through mode with CDP emulation.
Auto connects DP/DM to TDP/TDM depending
on CDP detection status.
D
CHG_CB1
4
CHG_CB0
Right front USB3.0 Conn.
(Support S&C function)
USB20_P1_S
3
WCM-2012-900T_0805
4
3
4
USB20_P1_R
USB20_N1_S
2
1
USB20_N1_R
USB20_P0_R
1
Mode
0
MAX14640ETA+TGH7
14640@
2N7002KDWH_SOT363-6
14640@
USB20_P0
CB1
0
5
<44,48,49>
RR3
4.7K_0402_5%
14640@
2
QR1A
2
2
Address
0x35
CB0
USB20_N0_R
2
1
EMI@
LR8
C
C
<32>
<32>
<32>
<32>
KINGCORE WCM-2012HS-670T
1
2
1
2
U3RXDP1
4
U3RXDN1
1
C904
U3TXDN1
3
2U3TXDN1_C
0.1U_0402_10V7K
4
U3RXDP1_L
<32>
U3RXDN1_L
<32>
U3RXDP2
4
U3RXDN2
EMI@
KINGCORE WCM-2012HS-670T
1
2
1
2
1
2U3TXDP1_C
C903 0.1U_0402_10V7K
U3TXDP1
4
L56
3
KINGCORE WCM-2012HS-670T
1
2
1
2
4
L60
3
3
<32>
U3TXDP2
<32>
U3TXDN2
U3TXDP2
1
2U3TXDP2_C
C905 0.1U_0402_10V7K
U3TXDN2
1
2U3TXDN2_C
C906 0.1U_0402_10V7K
4
L58
U3RXDP2_L
3
3
U3RXDN2_L
EMI@
KINGCORE WCM-2012HS-670T
1
2
1
2
U3TXDP2_C_L
U3TXDP1_C_L
4
U3TXDN1_C_L
4
L59
3
EMI@
3
U3TXDN2_C_L
EMI@
+USB_VCCA
USB_EN#0
B
IN
IN
EN/ENB
GND
OUT
OUT
OUT
OCB
6
7
8
5
USB_OC#0
C900
1
C901
1
<32,44>
SY6288DCAC_MSOP8
2
<44>
CR7
@
USB_CHG_EN#
SE00000PL00
IN
IN
EN/ENB
GND
OUT
OUT
OUT
OCB
6
7
8
5
W=80mils
@EMI@
2
1
CR40
1000P_0402_50V7K
USB_CHG_OC#
+USB_VCCB
USB20_N0_R
USB20_P0_R
U3RXDN1_L
U3RXDP1_L
U3TXDN1_C_L
U3TXDP1_C_L
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
1
C987
1
C898
2
CR8
@
2
B
47U_0805_6.3V6M
SE00000PL00
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+USB_VCCA
Conn@
USB20_N1_R
USB20_P1_R
U3RXDN2_L
U3RXDP2_L
GND
GND
GND
GND
<32,44>
SA00006DN00
JUSBF
JUSBR
1
2
3
4
5
6
7
8
9
0.1U_0402_10V7K
For EMI
SY6288DCAC_MSOP8
2
47U_0805_6.3V6M
SA00004KB00
SA00003TV00
+USB_VCCA
U14
2
3
4
1
0.1U_0402_10V7K
2
<44>
2
3
4
1
W=80mils
For EMI
@EMI@
2
1
CR39
1000P_0402_50V7K
W=80mils
2.5A
1
+USB_VCCB
U15
+5VALW
2
2.0A
1
+5VALW
+USB_VCCB
W=80mils
10
11
12
13
U3TXDN2_C_L
U3TXDP2_C_L
1
2
3
4
5
6
7
8
9
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
Conn@
GND
GND
GND
GND
10
11
12
13
LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
D87
U3TXDP1_C_L 1 1
D88
U3TXDP2_C_L 1 1
@ESD@
10 9
U3TXDP1_C_L
9 8
U3TXDN1_C_L
U3TXDN1_C_L 2 2
U3RXDP1_L
4 4
7 7
U3RXDP1_L
U3RXDN1_L
5 5
6 6
U3RXDN1_L
@ESD@
10 9
U3TXDP2_C_L
U3TXDN2_C_L 2 2
9 8
U3TXDN2_C_L
U3RXDP2_L
4 4
7 7
U3RXDP2_L
U3RXDN2_L
5 5
6 6
U3RXDN2_L
3 3
A
A
3 3
8
8
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
Compal Secret Data
Security Classification
Issued Date
2012/04/19
Deciphered Date
2015/04/19
Title
Compal Electronics, Inc.
RUSB/S&C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
VSKAA
Sheet
Thursday, May 09, 2013
1
41
of
57
A
B
C
D
20 mil
35mA for 3.3V level
UA1
MIC1_LINE1_R_R
MIC1_LINE1_R_L
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
22
21
CA58
CA57
17
16
<44>
1
31
30
29
+MIC1_VREFO_L
+MIC1_VREFO_R
EC_MUTE_INT
20
<27>
<27>
12
MONO_IN
AZ_SYNC_HD
2
1
AC_JDREF
1
2
LDO_CAP
RA30
20K_0402_1%
AC_VREF
CA60 10U_0603_6.3V6M
1
2
CPVEE
CBN
CA54
2.2U_0402_6.3V6M
1
1
2
CBP
CA55
CA53 2.2U_0402_6.3V6M
0.1U_0402_10V7K
2
<23> INT_MIC_DATA
INT_MIC_CLK_R
RA42
1
1
2
INT_MIC_CLK
MONO_OUT
SPK_OUT_L+
SPK_OUT_LHPOUT_R
HPOUT_L
JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP
AVSS1
AVSS2
PVSS1
PVSS2
DVSS
EAPD
PD#
Thermal Pad
RA50
4.7K_0402_5%
1
+AVDD
+AVDD
39
46
+PVDD
+PVDD
45
44
SPKR+
SPKR-
40
41
SPKL+
SPKL-
33
32
75_0402_1%
HPOUT_R RA19
HPOUT_L RA20
75_0402_1%
+3VS
close to pin 25
2
CA42
CA3
2.2U_0402_6.3V6M
CA45
0.1U_0402_16V4Z
CA47
10U_0603_6.3V6M 1
CA37
2
5
8
AZ_SDIN0_HD_R
6
AZ_BITCLK_HD
23
24
48
LINE1_R_C_L
LINE1_R_C_R
<43>
HP_L
<43>
2
CA33
0.1U_0402_10V7K
AZ_BITCLK_HD
1
269@
2
close to pin46
For P/N and footprint
Please place them to ISPD page
269@
2
259@
No
269@
For EMI reserve
close to codec
Yes
2
AZ_BITCLK_HD
10_0402_5%
@EMI@
CA51
1
1
2 @EMI@
RA41
10P_0402_50V8J
MIC/LINE IN
For EMI reserve
close to codec
1 Rshort@ 2
RA7
0_0603_5%
SPK_L1
SPKL-
1 Rshort@ 2
RA8
0_0603_5%
MONO_IN
CA31
1000P_0402_50V7K
@EMI@
<43>
MIC1_L
<43>
<43>
2
1
1K_0402_5%
RA45
<43>
1
2
1
+MIC1_VREFO_L
RA46 2.2K_0402_5%
3
CA30
1000P_0402_50V7K
2
@EMI@
6
MIC_SENSE
CA27
100P_0402_50V8J
RA29 269@
100K_0402_5%
QA1A
2N7002DW-T/R7_SOT363-6
269@
For better sound
by customer request
2
1
1
2
1
+MIC1_VREFO_R
RA48 2.2K_0402_5%
MIC1_R
SPKR+
SPKR-
1 Rshort@ 2
RA9
0_0603_5%
1 Rshort@ 2
RA10
0_0603_5%
<43>
+3VL
SPK_R2
1
1
2
2
<43>
<44>
RA35
RA37
0_0402_5%
100K_0402_5%
259@
SM_SENSE#
CA36
1000P_0402_50V7K
@EMI@
EC
QA1B
2N7002DW-T/R7_SOT363-6
269@
5
JACK_SENSE
<43>
4
CA34
1000P_0402_50V7K
@EMI@
SPK_R1
3
2
0.1U_0402_10V7K
SPK_L2
1
2
RA47
1K_0402_5%
2
1
MIC1_LINE1_R_L
RA49
4.7K_0402_5%
2
1 Rshort@ 2
RA44
0_0603_5%
1 Rshort@ 2
RA43
0_0603_5%
1 Rshort@ 2
RA39
0_0603_5%
1 @EMI@ 2
RA38
0_0603_5%
1 @EMI@ 2
RA31
0_0603_5%
MIC1_LINE1_R_R
47K_0402_5%
2
49
SPKL+
PCH_SPKR
1
Sleep and Music
AGND
2W 4ohm =40mil
1W 8ohm =20mil
<27>
CA35
1 10U_0603_6.3V6M
ALC269Q-VB6-CG
269@
For S&M
Enable
Disable
CA70
1
2
2
MIC1_LINE1_R_R
0.1U_0402_10V6K
DGND
2
2
+5VALW
<27>
SPK
1 RA52
1
1 Rshort@ 2
RA24
0_0603_5%
+PVDD
1
UA1
26
37
42
43
7
Beep sound
PCI Beep
+5VALW
CA50
MIC1_LINE1_R_L
0.1U_0402_10V6K
CA9
1
CA10
CA32
0.1U_0402_10V7K
AZ_SDOUT_HD <27>
AZ_SDIN0_HD <27>
2
1
RA23 33_0402_5%
1 Rshort@ 2
RA18
0_0603_5%
1
2
10U_0603_6.3V6M
close to pin39
HP_R
0.1U_0402_10V7K
1
2
60 mil
close to pin9
Internal AMP
3
close to pin 38
0.1U_0402_10V7K
2
1
1
To solve S&M noise issue
EC_MUTE#
Hight
LOW
2
close to pin1
650mA for 5V level
40 mil
+AVDD
1
CA4
0.1U_0402_16V4Z
25
38
ALC259-VC2-CG_MQFN48_6X6
259@
2
269@
LINE1_L
LINE1_R
NC
SENSE_A
SENSE_B
47
4
2 INT_MIC_CLK_R
FBMA-10-100505-301T_2P
CAM_EMI@
BCLK
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
13
18
EC_MUTE#
For EMI reserve
<23>
SPK_OUT_R+
SPK_OUT_R-
SDATA_OUT
SDATA_IN
2
3
SENSE_A
SENSE_B
1
20K_0402_1%
<44>
LINE2_R
LINE2_L
RA22
1 Rshort@ 2
0_0402_5%
+DVDD
1
+DVDD
+DVDD
RESET#
19
28
27
34
35
36
close to pin 28
2
PVDD1
PVDD2
10 mil
close to pin19
2 @
RA34
AVDD1
AVDD2
SYNC
11
CA25
2.2U_0603_10V6K
MIC2_R
MIC2_L
1
9
PCBEEP
10
AZ_RST_HD#
DVDD
DVDD_IO
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
15
14
@ESD@
CA65
0.01U_0402_25V7K
1
2
MIC1_R
MIC1_L
E
Sense Pin
SENSE A
4
Impedance
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
place close to chip
2
MIC_SENSE
RA32
SENSE_A
4
(PIN 48)
5.1K
<43>
SENSE B
1
20K_0402_1%
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
2012/04/19
PORT-H (PIN 20)
10K
2015/04/19
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
39.2K_0402_1%
Title
Date:
A
RA33
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
NBA_PLUG
D
HDA-ALC259-VC
Rev
Thursday, May 09, 2013
Sheet
E
42
of
57
SPK Conn.
SM_DET
1
S&M option
!
"#
0
JSPK
8
7
6
5
4
3
2
1
<42> SPK_R1
<42> SPK_R2
<42> SPK_L1
<42> SPK_L2
<33> SPK_DET
BIOS setup
Speaker Type
BOM
Harman/Kardon
269@
Non Harman
259@
GND
GND
Non-Harman detection
6
5
4
3
2
1
SPK_DET
ACES_50228-0067N-001
Conn@
0
ONKYO
1
Non-Brand
HeadPhone/LINE Out JACK
Conn@
JLINE
HP_R
RA53 1 Rshort@ 2 0_0402_5% HP_R_R
3
DA6
2
HP_L
<42>
3
<42>
6
1
2
RA54 1 Rshort@ 2 0_0402_5% HP_R_L
<42>
4
NBA_PLUG
YSDA0502C_SOT23-3
@ESD@
5
1
SINGA_2SJ-0960-D11
MIC/LINE IN JACK
JEXMIC
RA55 1 Rshort@ 2 0_0402_5%
MIC1_R_R
DA7
3
2
MIC1_R
Conn@
6
1
2
3
MIC1_L
<42>
MIC1_R_L
<42>
+3VL
YSDA0502C_SOT23-3
@ESD@
4
JACK_SENSE
5
RA40
4.7K_0402_5%
269@
SINGA_2SJ-0960-D11
RA36
0_0402_5%
259@
1
<42>
RA56 1 Rshort@ 2 0_0402_5%
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
AUDIO CONN
Document Number
Thursday, May 09, 2013
Rev
1.0
Sheet
43
of
57
B
C
RB4
10_0402_5%
@EMI@
CB11
22P_0402_50V8J
@EMI@
1
2
<29> CLK_PCI_EC
<31,38,39> PLT_RST#
+3VL
RB2
47K_0402_5%
1
2
<45>
<45>
KSI[0..7]
KSI[0..7]
KSO[0..15]
KSO[0..15]
2
1
RB12
2 CHG_PWR_GATE#
10K_0402_5%
<41>
RPB1
+3VL
+3VS
1
2
3
4
8
7
6
5
12
13
37
20
38
CLK_PCI_EC
EC_RST#
<33> EC_SCI#
<46> WOWL_EN#
EC_RST#
1
2
CB12 0.1U_0402_10V7K
+3VL
1
2
3
4
5
7
8
10
<33> GATEA20
<33> KB_RST#
<30> SERIRQ
<30> LPC_FRAME#
<30> LPC_AD3
<30> LPC_AD2
<30> LPC_AD1
<30> LPC_AD0
2
1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
CHG_PWR_GATE#
<41,48,49>
<41,48,49>
<13,24,30,37>
<13,24,30,37>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
TRANS_SEL
CHG_PWR_GATE#
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
AD Input
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
SPI Flash ROM
GPIO
Bus
RB27
100K_0402_5%
1
2
E51_TXD
3
1
RB17
2
EC_MUTE_INT_R
4.7K_0402_5%
<42>
EC_MUTE_INT
<28> CLK_EC
POK
PM_PWROK
RB38 0_0402_5%
1 Rshort@ 2 EC_MUTE_INT_R 122
1
2
123 XCLKI/GPIO5D
POK_R
@
XCLKO/GPIO5E
RB13
0_0402_5%
1 Rshort@ 2
RB14
0_0402_5%
1
RB22
CB16
100K_0402_5%
20P_0402_50V8
1
<28,50>
E51_TXD
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
2
2
GPIO
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
GND/GND
GND/GND
GND/GND
GND/GND
GND0
PM_SLP_S3#
PM_SLP_S5#
<33> EC_SMI#
<32,39> USB_OC#2
<32,41> USB_CHG_OC#
<41> USB_CHG_EN#
<39> USB_EN#2
<45> KB_LED
<5> FAN_SPEED1
<38> WL_OFF#
<38> E51_TXD
<38> E51_RXD
<28> PM_PWROK
<38> BT_ON
<42> SM_SENSE#
21
23
26
27
WL_BT_LED# <45>
USB_EN#0 <41>
FANPWM <5>
CLK_REQ_GC6# <13>
FANPWM
63
64
65
66
75
76
BATT_PRES
BATT_PRES <47,48>
USB_OC#0 <32,41>
ADP_I <48,49>
ADP_V <49>
HDPLOCK <37>
EC_ENBKL <22,23,31>
H_PROCHOT#
1
V18R
HDPINT
885_EC_ON
CB8
47P_0402_50V8J
2
3
BATT_PRES
1
CB9
ACIN_D
1
2
CB10 100P_0402_50V8J
FANPWM
1
2
CB17 100P_0402_50V8J
ON/OFFBTN#
1
2
CB18 100P_0402_50V8J
1
2
100P_0402_50V8J
@ESD@
<37>
+3VS
EC_CB0 <41>
SUSACK# <28>
Reserve this signal to EC by SW demand
<42>2011/10/18a
83
84
85
86
87
88
EC_MUTE#
PM_SLP_S4# <28>
EC_SMB_CK3 <22>
EC_SMB_DA3 <22>
TP_CLK <45>
TP_DATA <45>
EC_SMB_CK3
EC_SMB_DA3
TP_CLK
TP_DATA
97
98
99
109
LID_SW#
1
RB35
2
47K_0402_5%
WLAN_WAKE#
1
RB37
2
47K_0402_5%
TP_CLK
1
RB8
2
4.7K_0402_5%
TP_DATA
1
RB9
2
4.7K_0402_5%
EC_SMB_CK3
1
RB15
2
2.2K_0402_5%
EC_SMB_DA3
1
RB16
2
2.2K_0402_5%
SYSON
1
RB10
2
4.7K_0402_5%
SUSP#
1
RB21
2
10K_0402_5%
VR_ON
1
RB23
2
10K_0402_5%
2
+3VS
WLAN_WAKE#
SYSON
VR_ON
RB5
100
101
102
103
104
105
106
107
108
WLAN_WAKE# <38>
WOL_EN# <39>
HDPACT <37>
BATT_FULL_LED# <45>
CAPS_LED# <45>
PWR_SUSP_LED# <45>
BATT_CHG_LOW_LED# <45>
SYSON <51>
VR_ON <54>
1
2
FB_CLAMP <13,14,17>
Rshort@
0_0402_5%
PCH_RSMRST# <28>
EC_LID_OUT# <27>
PROCHOT_IN <48>
H_PROCHOT#_EC
VCOUT0_PH_L
PROCHOT_IN connect
to power portion (9012 only)
BKOFF# <23>
PBTN_OUT# <28>
PCH_PWR_EN <46>
EC_SWI# <28,39>
110
112
114
115
116
117
118
ACIN_D
EC_ON_R
ON/OFFBTN#
LID_SW#
SUSP#
+VTT_EC
EC_PECI
124
+EC_V18R
1
2
KB9012QF-A3_LQFP128_14X14
9012@
UB1
NPCE885NB0DX LQFP 128P
885@
2
10K_0402_5%
@
VCIN0_PH connect to
power portion (9012 only)
EC_SDIO <30>
EC_SDI <30>
EC_SCK <30>
EC_CS0# <30>
73
74
89
90
91
92
93
95
121
127
H_PROCHOT#_EC 1
RB6
+3VL
EC_CB1 <41>
GPS_DOWN# <13>
PWRME_CTRL <27>
VCIN0_PH <48>
119
120
126
128
Rshort@
VCOUT0_PH_L 1
RB34
2
0_0402_5%
VS_ON
<50>
VCOUT0_PH connect to power portion (9012 only)
ON/OFFBTN# <45>
LID_SW# <45>
SUSP# <46,52,53>
1 885@
RB3 1
RB19
2
2 0_0402_5%
43_0402_5%
RB18
330K_0402_5%
2
1
+1.05VS_VCCP
H_PECI <5>
ACIN_D
2
RB751V40_SC76-2
CB15
4.7U_0805_10V4Z
3
+3VL
1
DB1
ACIN
<28,47,49>
+3VALW_PCH
RB7
10K_0402_5%
LVDS@
1 9012@ 2
RB36
0_0402_5%
+3VL
RB11
10K_0402_5%
IEDP@
<50>
1
EC_ON
2
TRANS_SEL
885@
2
1
RB20
330K_0402_5%
EC_ON_R
<47,5>
@ESD@
68
70
71
72
SPI Device Interface
11
24
35
94
113
<28>
<28>
@ESD@
1
2
PM_PWROK
CB19 100P_0402_50V8J
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
2.2K_8P4R_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
2 0_0402_5%
1
D
QB1
SSM3K7002F_SC59-3 S
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
RB1 1
VR_HOT#
H_PROCHOT#_EC 2
G
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
Rshort@
<54>
2
CB6
2
2
1000P_0402_50V7K
UB1
1
2
E
67
CB4
2
0.1U_0402_10V7K
EC_VDD/AVCC
2
CB3
0.1U_0402_10V7K
1
2
AGND/AGND
2
CLK_PCI_EC
1000P_0402_50V7K
1
CB7
9
22
33
96
111
125
For EMI
1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
CB2
CB5
1
CB1
0.1U_0402_10V7K
D
+3VL
1
+3VL
69
A
1
S
3
QB2
D
1
885@
2
@ 1U_0402_6.3V6K
CB50
Close to EC
@
SUSP#
G
2N7002K_SOT23-3
2
4
885_EC_ON
Voltage Comparator Pins FOR 9012 A3
VCIN0 pin109
VCIN1 pin102
>1.2V
VCOUT0 pin104
HIGH
(default)
VCOUT1 pin103
HIGH
Issued Date
2012/04/19
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
LOW
(default)
2
180P_0402_50V8J
RB24
885@
2
1
10K_0402_5%
For KB9012 EC_ON low pulse work around
<1.2V
LOW
1
CB14
C
D
LPC-EC-KB9012&930
Document Number
Rev
1.0
Thursday, May 09, 2013
Sheet
E
44
of
57
4
Power Button
3
Conn.
1
3
5
7
2
+3VL
JPWR Conn@
2
1
2 4
3
4 6
5
6 8
7
8
1
Conn@
15
15 13
13 11
11 9
9 7
7 5
5 3
3 1
1
JTP
+5VS
16
14
12
10
8
6
4
2
ACES_50611-0040N-001
ON/OFFBTN#
Battery Reset
ON/OFFBTN#
100K_0402_5%
ON/OFFBTN#
1
Touchpad Connector
R395
D
2
<44>
Place on TOP
16
14
12
10
8
6
4
2
3
+3VS
TP_DATA <44>
TP_CLK <44>
<50>
TJG-533-V-T/R_6P
1
4
ENLDO
2
5
6
5
SW2
D
PM_SMBDATA <11,12,30,38>
PM_SMBCLK <11,12,30,38>
HB_A060877-SAVR01
@ TJG-533-V-T/R_6P
3
1
4
2
SW4
Keyboard LED
Conn@ JBLG
C
BATT_FULL_LED#
<44>
HT-F196BP5_WHITE
+5VALW
2
H1
ACES_50578-0040N-001
VGA
H2
H_4P6
@
H3
H_4P6x4P2
@
H4
WLAN standoff
H5
H_4P2
@
H_3P3
@
H29
H_3P3
@
H_3P3
@
1
1
CPU
+5VS_LED
1
+5VS_LED
2
2
R587
10K_0402_5%
KBL@
1
1
1
3
R60
390_0402_5%
1
2
G
D24
1
2
3
4
5
6
1
1
2
3
4
GND
GND
D
S
BATT CHARGE /FULL LED
Screw Hole
Q38
KBL@
AO3413_SOT23
+5VS
1
LED/LID
1
5
6
Place on BOT
C
Q52
2N7002KW_SOT323-3
KBL@
PTH
1
PWR_SUSP_LED#
<44>
<44>
White LED bright when system is power on.
White LED blink when system is sleep mode.
WLAN/WiMAX
LED
<38>
2
LED_WIMAX#
R819
2
1
10K_0402_5%
@
WOWL@
1
2
R268
0_0402_5%
6
5
+5VALW
D26
+5VS
1
2
2
1
R269
0_0402_5%
NOWOWL@ HT-191UD5_AMBER_0603
H12
1
2
R66
510_0402_5%
3
4
1
Q157A
2N7002DW-T/R7_SOT363-6
@
Q157B 2N7002DW-T/R7_SOT363-6
@
WL_BT_LED#
<44>
CAPS_LED#
+3VS
R3
2
1
300_0402_5%
KSI1
KSI6
KSI5
KSI0
KSI4
KSI3
KSI2
KSI7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2
H13
H_3P0
@
<44>
JKB
HT-F196BP5_WHITE
B
<44>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND1
GND2
H17
H18
H19
H_3P2x3P7
@
H_3P2N
@
1
H_3P2
@
1
1
H_3P0
@
1
H14
H_3P0
@
H11
H_3P0
@
1
H10
H_3P0
@
H15
H_7P0
@
H_3P0
@
PCB Fedical Mark PAD
FD1
@
FD2
@
1
2
+5VALW
R61
390_0402_5%
1
2
KSI[0..7]
KSO[0..15]
NPTH
H9
H_3P2
@
FD3
@
FD4
@
1
KSO[0..15]
1
KSI[0..7]
POWER LED
H8
H_4P0
@
1
NEW KEYBOARD CONN.
D25
H7
H_3P0
@
1
H6
1
White LED bright when both AC-adaptor is plugged in and Battery is full charged
Amber LED bright while charging battery from AC-adaptor.
Amber LED blink during Critical Low Battery
1
S
2
G
1
KB_LED
1
<44>
D
1
<44>
1
HT-191UD5_AMBER_0603
BATT_CHG_LOW_LED#
1
1
2
R5
510_0402_5%
1
1
3
D23
2
B
ISPD
35
36
GPU
ZZZ
UH1
DAZ0WI00100
SA00006PF50
HM86R3@
SA00006DO40
UV1
N14PGV2R3@
PCB LA-9866P
HM86
N14P-GV2-S-A1 FCBGA
(Default)
N14PGV2R1@
N14P-GV2-S-A1
SA00006DO00
CVILU_CF17341U0R0-NH
Conn@
Amber LED bright while Wireless and/or WiMAX turns on.
UV1
N14MGLR1@
UV1
N14MGLR3@
SA000069000
SA000069010
N14M-GL
N14M-GL-S-A2 FCBGA
+3VL
A
2
VDD
VOUT
C453
0.1U_0402_16V4Z
NFC
3
LID_SW#
1
1
1
GND
U21
APX9132ATI-TRL_SOT23-3
2
C452
10P_0402_50V8J
<44>
@
A
2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
TP/ISPD/KB/Screw
Document Number
Rev
1.0
VSKAA
Friday, May 10, 2013
Sheet
1
45
of
57
SUSP#
+3VALW
1
5
6
7
CT1
VBIAS
ON2
VIN2
VIN2
GND
CT2
VOUT2
VOUT2
GPAD
@
1
2
12
C19
1
180P_0402_50V8J
2
2
PAD-OPEN 4x4m
1
11
10
9
8
C18
1
+3VALW
1
ON1
1
+5VS_LS
330P_0402_50V7K
2
WOWL@
C20
@
2 0.1U_0402_10V7K
+3VS
<44>
15
1
2
PAD-OPEN 4x4m 1
TPS22966DPUR_SON14_2X3
C44
2
2
47K_0402_5%
R1458
2
WOWL@
RM2
100K_0402_5%
C21
@
Vgs=-4.5V,Id=3A,Rds<97mohm
1
1
WOWL_EN#
PJ5 JP@
+3VS_LS
2 WOWL@
C910
0.1U_0402_10V7K
R1459
10K_0402_5%
2
4
+5VALW
2
3
14
13
1
1U_0402_6.3V6K
SUSP#
VOUT1
VOUT1
1
AO3413_SOT23
Q211
WOWL@
C911
0.01U_0402_25V7K
+3V_WLAN
WOWL@
1
RM1
1
2
0_0603_5%
2
C45 1
@
VIN1
VIN1
3
+5VS
PJ3 JP@
U1
1
2
E
+3VALW
1
VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
D
+3VALW TO +3V_WLAN
for AOAC and WOWL
G
+5VALW
C
D
+3VALW TO +3VS
+5VALW TO +5VS
Load Switch
B
S
A
2 0.1U_0402_10V7K
+3VS
NOWOWL@
1U_0402_6.3V6K
+5VALW
+3VL
2
For S3 CPU Power Saving
2
R5545
10K_0402_5%
2
0.675VR_EN
220K_0402_5%
0.675VR_EN
<51>
<44>
2
PCH_PWR_EN#
<34>
D
2
G
PCH_PWR_EN
Q5527
2
S SB00000EN00
2N7002E-T1-E3_SOT23-3
4
3
Q6B
2N7002KDWH_SOT363-6
5
SUSP
PCH_PWR_EN#
1
1
R158
1
VCCP_PWRGOOD
3
<52>
1
R4
10K_0402_5%
885@
+5VALW
2
S
G
S 2N7002KW_SOT323-3
2N7002KW_SOT323-3
3
SUSP#
D
2
SUSP
G
1
<44,52,53>
Q60
2
1
D Q189
Q6A
2N7002KDWH_SOT363-6
2
3
1
6
1
R468
470_0805_5%
1
R421
22_0805_5%
1
R422
100K_0402_5%
SUSP
+1.05VS_VCCP
2
+0.675VS
2
Reserve CAP to avoid Power Noise
+5VS_ODD
3
+5VS TO +5VS_ODD
2
3
R457
470_0805_5%
6 1
ZPODD@
Q53A
ODD_EN#
+5VS
1
NONZP@
R120
0_0805_5%
47K_0402_5%
ZPODD@
2
1
AO3413_SOT23
C217
0.01U_0402_25V7K
2
2N7002DW-T/R7_SOT363-6
Q53B
ZPODD@
Q45
2
Vgs=-4.5V,Id=3A,Rds<97mohm
3
3
1
4
ODD_EN#
C471
0.1U_0402_10V7K
ZPODD@
1
<33>
1
G
5
2
2
R441
100K_0402_5%
ZPODD@
R440
1
2
D
1
+5VS
+3VS
S
2
2N7002DW-T/R7_SOT363-6
ZPODD@
+5VS_ODD
ZPODD@
ZPODD@
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Deciphered Date
2015/04/19
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
4
DC-DC INTERFACE
Document Number
Rev
1.0
VSKAA
Sheet
Thursday, May 09, 2013
E
46
of
57
A
B
EMI Part (47.1)
A51 need add fuse
EMI@ PL101
FBMA-L11-201209-121LMA50T_0805
1
2
PF1
1
2
DC_IN_S1
1
1
EMI@ PC101
100P_0603_50V8
2
EMI@ PC103
100P_0603_50V8
1
1
2
EMI@ PL102
FBMA-L11-201209-121LMA50T_0805
2
EMI@ PC102
1000P_0603_50V7K
2
2
1
7A_32V_S1206-H-7.0A
1
@ PJP1
@PJP1
ACES_50299-00401-001
1
1 2
2 3
3 4
4
D
VIN
Other component (37.1)
1
C
EMI@ PC104
1000P_0603_50V7K
2
2
Other component (37.1)
For ML1220 RTC (38.2)
+5VS
1
PR101
560_0603_5%
1
2
+RTC_R
PR102
560_0603_5%
1
2
+RTCBATT
+3VALW
1
2
+
@PR104
@
PR104
47K_0402_1%
-
3
BATT_PRES
<44,48>
2
1
4
@ PD102
LL4148_LL34-2
1
@ PR108
@PR108
1.5M_0402_5%
PC106
100P_0402_50V8J
PR105
100K_0402_1%
2
2
2
+
O
PU102A
LM393DR_SO8
1
1
1
S
2
8
1
2
2
G
PQ101A
DMN66D0LDW-7_SOT363-6
P
6
@PC105
@
PC105
0.022U_0402_16V7K
2
1
D
PR103
10K_0402_1%
G
H_PROCHOT#
2
<44,5>
+RTC
1
@ PBJ101
ML1220T13RE
-
3
1
3
Dual package?
8
+
-
O
5
6
ACIN
<28,44,49>
1
7
4
4
2
PD103
LL4148_LL34-2
PR107
1.5M_0402_5%
2
S
1
G
PQ101B
DMN66D0LDW-7_SOT363-6
PU102B
LM393DR_SO8
P
5
G
3
PC107
0.022U_0402_16V7K
2
1
D
2
PR106
47K_0402_1%
Remark :
Check Adapter/Battery surge load when Iccmax.
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/24
Deciphered Date
2012/07/12
Title
DCIN/Surge load protect
VSKAA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Sheet
D
47
Rev
1.0
of
57
A
B
C
Other component (37.1)
EMI Part (47.1)
D
OTP (39.7)
VMB
1
EMI@ PL2
FBMA-L11-201209-121LMA50T_0805
1
2
2
BATT+
+3VL
10A_125V_TR2/6125FF10-R
1
1
@ PC11
0.1U_0402_10V7K
2
1
+3VL
1
PR16
6.49K_0402_1%
2
1
@ PR5
0_0402_5%
1
2
VCIN0_PH
1
<44>
2
2
1
@ PR2
0_0402_5%
1
2
PROCHOT_IN
2
<44>
PR1
1K_0402_1%
1
EMI@ PC8
0.01U_0402_25V7K
2
1
EMI@ PC7
1000P_0402_50V7K
ADP_I
2
2
PR14
1K_0402_1%
<44,49>
PR3
20K_0402_1%
1
2
EMI@ PL3
FBMA-L11-201209-121LMA50T_0805
1
BATT_P5
EC_SMDA
EC_SMCA
PR19
1K_0402_1%
BATT_PRES
<44,47>
1
PR21
100_0402_1%
1
PR20
100_0402_1%
2
2
2
2
2
PR4
12.1K_0402_1%
PF2
1
BATT_S1
2
@ PJP2
ACES_50299-01001-W01
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10
PH1
100K_0402_1%_TSM0B104F4251RZ
1
EC_SMB_DA1
<41,44,49>
EC_SMB_CK1
<41,44,49>
Initial
Recovery
75W
N14M-GL
0.90V
0.72V
90W
N14P-GV2
1.05V
0.90V
Initial
Recovery
3
3
CPU
OTP
90 C
70 C
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/24
Deciphered Date
2012/07/12
Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Rev
1.0
VSKAA
Date:
Sheet
D
48
of
57
A
B
C
D
for reverse input protection
1
3
Charger controller (40.1), Support component (40.2)
D
S
2
G
PR225
1
PR226
2
1
1M_0402_5%
1
PQ209
SSM3K7002FU_SC70-3
2
3M_0402_5%
1
EMI Part (47.1)
B+
2
1
4
1
5
BQ24735_REGN2
PR210
0_0603_5%
2
2
10
1
PC243
0.01U_0402_25V7K
2
1
PR242
100K_0402_1%
2
BQ24735_ACDET
PR244
422K_0402_1%
1
2
1
2
PC223
10U_0805_25V6K
1
2
PR241
357K_0402_1%
For A51 ADP_V function
VIN
1
<41,44,48>
EC_SMB_DA1
<41,44,48>
PR247
309K_0402_1%
PR248
10K_0402_1%
1
2
4
PR249
47K_0402_1%
@ PC246
0.1U_0402_10V7K
Please locate the RC
Near EC chip
2011-02-22
4
2011/06/24
Deciphered Date
Compal Electronics, Inc.
2012/07/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CHARGER
B
C
Rev
1.0
VSKAA
Date:
A
<44>
@ PC247
0.1U_0402_10V7K
Compal Secret Data
Security Classification
Issued Date
1
<44,48>
2
ADP_I
2
@ PR246
0_0402_5%
ADP_V
1
2
2
100P_0402_50V8J
1
1
PC245
2
1
ILIM and external DPM
3.61A
EC_SMB_CK1
2
PR245
66.5K_0402_1%
1
2
1
PC244
0.1U_0402_25V6
Max.
2
Typ
17.23V
17.63V
H-->L
L-->H
PC241
0.1U_0402_25V6
CSOP1
1
3
1
Vin Dectector
Min.
2
3
CSON1
2
EMI Part (47.1)
BQ24735_ILIM
VIN
PR227
0.01_1206_1%
4
+3VALW
3
<28,44,47> ACIN
PC242
0.1U_0603_16V7K
2
2
BQ24735_BATDRV
1
11
2
12
PR236
10_0603_1%
2 CSOP1
SRP 1
PR237
6.8_0603_5%
2 CSON1
SRN 1
13
ILIM
SCL
SDA
BATDRV
9
BQ24735_ACOK
ACOK
6
+3VL
SRN
8
5
PR239
10K_0402_1%
1
2
ACDRV
IOUT
4
SRP
7
BQ24735_ACDRV
CMSRC
3
2
1
GND
1
ACP
ACDET
3
CHG
PC240
0.1U_0402_25V6
1
4
DL_CHG
14
BQ24735RGRR_QFN20_3P5X3P5
BQ24735_CMSRC
2
5
PQ202
AON7406L
15
1
1
BQ24735_LX
LODRV
1
2
PC205
1U_0603_25V6K
@EMI@ PR206
4.7_1206_5%
1
2
3
2
1
PL202
4.7UH_ETQP3W4R7WFN_5.5A_20%
PC222
10U_0805_25V6K
BATT+
REGN
ACN
PQ201
AON7408L
4
2
2
2BQ24735_BATDRV_1
1
1
DH_CHG
16
PR229
2.2_0603_5%
1
BQ24735_BST 2
DH_CHG
18
17
BTST
PAD
HIDRV
BQ24735_LX
19
PHASE
1
PD231
RB751V-40_SOD323-2
@EMI@ PC206
680P_0603_50V8J
PR228
10_1206_1%
2
1 1
BQ24735_VCC
1
2
21
20
1
2
PC235
0.1U_0402_25V6
PU200
VCC
1
PR235
4.12K_0603_1%
2
1
PR233
4.12K_0603_1%
PC237
0.047U_0402_25V7K
1
2
PC239
1U_0603_25V6K
BQ24735_ACN
2
BQ24735_BATDRV
PD230
BAS40CW_SOT323-3
1
BQ24735_ACP
2
1
2
PR234
4.12K_0603_1%
PC238
0.1U_0603_25V7K
BQ24735_ACDRV_1
PC234
0.01U_0402_50V7K
PQ207
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
5
3
PC213
10U_0805_25V6K
2
PC236
0.1U_0402_25V6
2
3
2
2
VIN
1
1
3
PC211
10U_0805_25V6K
2
EMI@ PL201
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
2
PR211
0.01_1206_1%
4
1
1
4
1
4
2
1
PC230
2200P_0402_50V7K
2
P2
PQ205
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
3
5
@EMI@ PC214
2200P_0402_25V7K
P1
PQ203
TPCA8057-H_PPAK56-8-5
1
2
5
3
PC231
0.1U_0402_25V6
VIN
Sheet
D
49
of
57
B
C
D
3/5VALW controller (35.1), Support component (35.2)
5V
Peak Current 10 A
OCP current 12 A
FSW=390kHz
Delta I= 1.28 A,ripple V = 1.28 * 25 m= 32 mV
DCR 13.2mohm +/-5%
TYP
MAX
H/S Rds(on) : 27mohm ,
34mohm
L/S Rds(on) :10.8mohm , 13.6mohm
5VALW
Ipeak : 12.5 A
Imax : 8.75 A
Iocp : 15 A
FSW : 390 kHz
1
1
BYP1
BOOT2
BOOT1
16
LG_5V
PU330
RT8243AZQW_WQFN20_3X3
4
PQ352
FDMC7692S_MLP8-5
PC341
4.7U_0603_10V6K
3
2
1
1
PC344
4.7U_0603_10V6K
2
PC342
1U_0603_10V6K
2
1
PR338
100K_0402_1%
2
1
Rds=10.8mΩ(Typ)
13.6mΩ(Max)
1
+
2
ENLDO <45>
PR340
2.2K_0402_1%
1
2
EMI Part (47.1)
3
@ PR332
100K_0402_5%
2
1
2
1
@ PR341
0_0402_5%
1
2
PC343
4.7U_0603_6.3V6K
1
2
<44> VS_ON
PC360
0.1U_0603_25V7K
3/5V_B+
1
+3VLP
PR334
499K_0402_1%
1
2
AON7406L
PQ332
+5VALWP
PC352
LGATE1
PL352
2.2UH_ETQP3W2R2WFN_8.5A_20%
1
2
150U_D2_6.3VY_R15M
LDO3
15
LDO5
SECFB
14
ENLDO
12
VIN
11
Rds= 19mΩ(Typ)
23.5mΩ(Max)
<44> EC_ON
3.3V
Peak Current 6 A
OCP current 7.2 A
Delta I= 4.29 A ,ripple= 4.29 x m= mV
FSW=455kHz
DCR 35mohm +/-15%
TYP
MAX
H/S Rds(on) :27mohm ,
34mohm
L/S Rds(on) :19mohm ,
23.5mohm
LGATE2
13
5
3
4
1
2
3
@EMI@ PC336
@EMI@ PR336
680P_0603_50V8J
4.7_1206_5%
2
1 SNUB_3V 2
1
2
EMI Part (47.1)
PC332
150U_D2_6.3VY_R15M
1
+
10
LX_5V
1
PHASE2
PHASE1
LG_3V
17
2
@EMI@ PR356
4.7_1206_5%
9
UG_5V
PC355
0.1U_0402_10V7K
2
BST1_5V 1
SNUB_5V 2
UGATE2
UGATE1
LX_3V
18
PR355
0_0402_5%
1
2
2
+3VALWP
8
4
BST_5V
1
UG_3V
20
19
3
2
1
2
PQ351
AON7408L_DFN8-5
21
2
7
PAD
@EMI@ PC356
680P_0603_50V8J
BST_3V
PGOOD
5
VFB=2V
5
6
PL332
4.7UH_ETQP3W4R7WFN_5.5A_20%
2
1
1
ENTRIP_5V
2
PR351
19.1K_0402_1%
1
2
FB_5V
2
POK
PC335
PR333
0.1U_0402_10V7K
0_0402_5%
1
2 BST1_3V 1
2
3/5V_B+
FB1
<28,44>
TON
4
1
PR350
30K_0402_1%
1
2
ENTRIP1
5
PQ331
AON7408L
+3VL
TON_35V
5
PR335
100K_0402_1%
1
2
ENTRIP_3V
FB_3V
VFB=2V
1
2
3
2
1
PC340
10U_0805_25V6K
@EMI@ PC339
2200P_0402_50V7K
2
1
PR331
20K_0402_1%
1
2
3
3/5V_B+
EMI@ PL331
HCB2012KF-121T50_0805
1
2
4
PR330
14K_0402_1%
1
2
ENTRIP2
EMI Part (47.1)
FB2
B+
1
2
PR337
165K_0402_1%
1
2
PR342
56K_0402_1%
1
2
PR357
143K_0402_1%
@ PC345
100P_0402_50V8J
1
2
PC361
10U_0805_25V6K
A
3VALW
Ipeak : 8 A
Imax : 5.6 A
Iocp : 9.6 A
FSW : 455 kHz
@ PJ332
2
+3VLP
2
1
@
1
+3VL
+3VALWP
JUMP_43X39
1
1
PJ331
2
2
+3VALW
JUMP_43X118
(100mA,40mils ,Via NO.= 2)
@
+5VALWP
1
1
PJ351
2
2
+5VALW
JUMP_43X118
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/24
Deciphered Date
2012/07/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3VALW/5VALW
VSKAA
Date:
A
B
C
Sheet
D
Rev
1.0
50
of
57
A
DDR controller (35.3), Support component (35.4)
EMI Part (47.1)
1.35V_B+
PR155
0_0603_5%
1
2
1
2
PC160
10U_0805_6.3V6K
2
2
3
4
VTTREF_1.35V
+1.35VP
5
FB
6
7
8
+1.35VP
2
VFB=0.75V
PR161
510K_0402_1%
1
2
1
PR162
10K_0402_1%
1
PR164
0_0402_5%
2
1
1
<46> 0.675VR_EN
PC163
0.033U_0402_16V7K
EN_0.675VSP
@ PC166
0.1U_0402_10V7K
PR160
8.06K_0402_1%
2
1
FB_1.35V
EN_1.35V
@ PC167
0.1U_0402_10V7K
2
1
PC159
10U_0805_6.3V6K
1
1
VDDQ
S3
VDD
21
2
1.35V_B+
@ PR163
0_0402_5%
1
2
2
SYSON
VTT
VLDOIN
20
19
18
1
+5VALW
1
DDR 1.35V
Ipeak : 10 A
Imax : 7A
Iocp : 12 A
FSW : 495 kHz
BOOT
VTTREF
@EMI@ PC156
680P_0402_50V7K
<44>
UGATE
VDDP
TON_1.35V
Rds=10.8mΩ(Typ)
13.6mΩ(Max)
2
PC164
1U_0603_10V6K
GND
RT8207MZQW_WQFN20_3X3
1
+5VALW
PAD
VTTSNS
S5
5
FDMC7692S_MLP8-5
PQ152
11
4
1
2
3
1
12
VDD_1.35V
PR159
5.1_0603_5%
1
2
CS
PU150
VTTGND
PGND
1
SNUB_+1.35VP 2
PC162
1U_0603_10V6K
1
2
LGATE
TON
14
17
16
PR158
15.4K_0402_1%
1
2CS_1.35V
PHASE
15
PGOOD
4
9
5
PQ151
AON7408L
DL_1.35V
13
@EMI@ PR156
4.7_1206_5%
2
2
EMI Part (47.1)
PC157
+
330U_D2_2.5VY_R9M
1
+0.675VSP
SW_1.35V
1
2
3
PL152
0.68UH_PCMB053T-1R0MS_8.5A_20%
2
1
+1.35VP
+1.35V
BST_1.35V
DH_1.35V
PC155
0.1U_0603_25V7K
1
2
1
2
PC154
10U_0805_25V6K
1
2
@EMI@ PC152
2200P_0402_50V7K
BST_1.35V-1
10
EMI@ PL151
HCB1608KF-121T30_0603
1
2
B+
+0.675VSP
2
@ PJ675
1
1
2
+0.675VS
+1.35VP
JUMP_43X39
Issued Date
Deciphered Date
Compal Electronics, Inc.
2012/07/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
+1.35V
(7A, 600mils ,Via NO.= 15)
Compal Secret Data
2011/06/24
@ PJ1351
1
1
2
JUMP_43X118
(0.5A,40mils ,Via NO.= 1)
Security Classification
2
1.35VP/0.675VSP
VSKAA
Sheet
Rev
1.0
51
of
57
5
4
3
2
1
D
D
1.05VCCP controller (35.5), Support component (35.6)
SUSP#
<44,46,53>
@ PC402
0.1U_0402_16V7K
2
1
PR402
0_0402_5%
2
1
EMI Part (47.1)
EMI Part (47.1)
VFB=0.6V
1
2
PC411
22U_0603_6.3V6M
1
2
PC410
22U_0603_6.3V6M
2
1
PC409
22U_0603_6.3V6M
1
2
1
2
VCCP_PWRGOOD
PC408
22U_0603_6.3V6M
PR401
100K_0402_5%
<46>
+3VALW
5
1
LDO
2
PG
1
2
2
2
4
7
+1.05VS_VCCPP
PR406
PC407
1K_0402_1% 4700P_0402_16V7K
BYP
1
ILMT
PC406
0.1U_0603_25V7K
PL402
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2
SW_+1.05VSP
PR404
75K_0402_1%
1
3
10
2
2
LX
FB
+3VS
+3VS
GND
@EMI@ PC403
680P_0603_50V7K
1
2
C
1
PC413
2.2U_0603_6.3V6K
BS
9
6
1
PC401
10U_0805_25V6K
2
1
@EMI@ PC404
2200P_0402_50V7K
2
1
B+
PU400
SY8208DQNC_QFN10_3X3
8
1
IN
EN
PC412
4.7U_0603_6.3V6K
2
1
C
EMI@ PL401
HCB2012KF-121T50_0805
2
1
@EMI@ PR403
4.7_1206_5%
1
2
SNUB_+1.05VSP
PR405
100K_0402_1%
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high respectively.
@ PJ401
2
2
+1.05VS_VCCPP
2
1
1
+1.05VS_VCCP
JUMP_43X118
(17A,680mils ,Via NO.=34)
OCP=23.91A
B
B
1.05V
Peak Current 11.35 A
OCP current 16 A
FSW=800kHz
Delta I= 1.24 A,Rippe= x m= mV
DCR 8.3~10 mohm
TYP
MAX
H/S Rds(on) :22 mohm , mohm
L/S Rds(on) :11 mohm ,
mohm
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/24
2012/07/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05VS_VCCP
VSKAA
Date:
5
4
3
2
Sheet
1
52
Rev
1.0
of
57
5
4
3
2
1
EMI Part (47.1)
EMI@ PL601
HCB2012KF-121T50_0805
2
1
TPS51212DSCR_SON10_3X3
4
PC606
1U_0603_10V6K
C
PR606
11.5K_0402_1%
2
1
1
1
+
2
@EMI@ PC608
680P_0402_50V7K
1
+
2
EMI Part (47.1)
C
1
FB=0.704V
Rds=13.5mΩ(Typ)
16.5mΩ(Max)
1
@EMI@ PR604
4.7_1206_5%
GL@ PC609
330U_2V_M_R15M
11
+5VALW
DL_1.5VSG
2
PR605
470K_0402_1%
7
6
+1.5VSP
GV@ PC607
330U_2.5V_M
TP
PL602
2.2UH_ETQP3W 2R2W FN_8.5A_20%
1
2
1
DRVL
SW _1.5VSG
2
V5IN
TST
DH_1.5VSG
8
1
VFB
9
2
5
SW
PQ602
SI7716ADN-T1-GE3_POWERPAK8-5
4
DRVH
EN
PC604
0.1U_0603_25V7K
1
2
D
5
FB_1.5VSG
RF_1.5VSG
TRIP
BST_1.5VSG
3
2
1
3
10
1
2
EN_1.5VSG
VBST
1
PC605
0.1U_0402_16V7K
TRIP_1.5VSG
PGOOD
2
1
SUSP#
2
<44,46,52>
PR601
1K_0402_1%
1
2
1
B+
3
2
1
PR603
0_0603_5%
1
2
PU600
PR602
133K_0402_1%
2
1
2
4
2
PQ601
AON7408L
D
PC601
10U_0805_25V6K
5
1.5VSG_B+
@EMI@ PC602
2200P_0402_50V7K
1.5VS controller (35.31), Support component (35.32)
2
PR607
10K_0402_1%
1.5V
Peak Current 0.75 A
OCP current 0.95 A
FSW= 290 kHz
Delta I= A,Rippe= x m= mV
DCR 8.3~10 mohm
TYP
MAX
H/S Rds(on) : 27 mohm ,
34 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm
B
+1.5VSP
2
@ PJ150
1
1
2
+1.5VS
JUMP_43X118
(15A, 600mils ,Via NO.= 30)
OCP=18A
TPS51212 for DIS SKU
APL5930 for UMA SKU
Confirm with HW for sequence control
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/07/10
Issued Date
Deciphered Date
2013/07/10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size
Document Number
Custom
Date:
Thursday, May 09, 2013
+1.5VS
VSKAA
Sheet
1
Rev
1.0
53
of
57
B
D
PR541
64.9K_0402_1%
2
1
PR543
549K_0402_1%
2
1
1
2
PR542
20K_0402_1%
2
1
PR546
150K_0402_1%
2
1
PR544
150K_0402_1%
2
1
@ PR545
100K_0402_1%
2
1
PR547
196K_0402_1%
2
1
PC526
4700P_0402_16V7K
2
1
2
1
PC959
22U_0603_6.3V6M
1
PC969
22U_0603_6.3V6M
1
2
2
1
PC960
22U_0603_6.3V6M
2
1
PC970
22U_0603_6.3V6M
1
PC979
22U_0603_6.3V6M
2
2
1
PC961
22U_0603_6.3V6M
2
1
PC971
22U_0603_6.3V6M
1
PC980
22U_0603_6.3V6M
2
2
1
PC962
22U_0603_6.3V6M
2
1
PC972
22U_0603_6.3V6M
1
PC981
22U_0603_6.3V6M
2
2
1
PC963
22U_0603_6.3V6M
2
1
PC973
22U_0603_6.3V6M
1
PC982
22U_0603_6.3V6M
2
2
1
PC964
22U_0603_6.3V6M
2
1
PC974
22U_0603_6.3V6M
1
PC983
22U_0603_6.3V6M
2
2
1
PC965
22U_0603_6.3V6M
2
2
2
1
PC975
22U_0603_6.3V6M
1
PC984
22U_0603_6.3V6M
2
1
PC966
22U_0603_6.3V6M
2
1
PC976
22U_0603_6.3V6M
2
1
PC985
22U_0603_6.3V6M
2
1
PC967
22U_0603_6.3V6M
2
PC968
22U_0603_6.3V6M
1
PC977
22U_0603_6.3V6M
1
PC986
22U_0603_6.3V6M
2
2
PC978
22U_0603_6.3V6M
1
1
PC987
22U_0603_6.3V6M
2
PC988
22U_0603_6.3V6M
2
1
PC994
22U_0603_6.3V6M
2
1
PC995
22U_0603_6.3V6M
2
1
PC996
22U_0603_6.3V6M
2
2
@ PC998
22U_0603_6.3V6M
@ PC1000
22U_0603_6.3V6M
EMI Part (47.1)
EMI@ PL503
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
2
1
1
2
5
1
2.2_0402_1%
PR527
1
6
2
7
.1U_0402_16V7K
8
PC516
PWM1
VIN
PGND2
VSW
BOOT_R PGND1
BOOT
VDD
PWM
SKIP#
4
1
2
PL502
0.15UH_ETQP4LR15AFM_29A_20%
3
2
1
PU501
CSD97374CQ4M_SON8_3P5X4P5
2
SKIP
@ PR538
0_0402_5%
+CPU_CORE
PC525
1U_0402_6.3V6K
MAX
mohm
mohm
3
PWM2
<44> VR_HOT#
9
PGND2
VSW
BOOT_R PGND1
BOOT
PWM
VDD
SKIP#
4
1
2
@ PC538
0.12U_0402_10V6K~D
1
2
1
2
PL505
0.15UH_ETQP4LR15AFM_29A_20%
3
2
+CPU_CORE
+5VS
1
1
PU504
CSD97374CQ4M_SON8_3P5X4P5
1
PC529
0.15U_0402_10V6K
PC533
2
1
2
7
.1U_0402_16V7K
8
VIN
CSN2
@ PR561
0_0402_5%
2
SKIP
PC535
1U_0402_6.3V6K
4
2
@ PC566
47P_0402_50V8J
6
CSP2
1
1
PC530
<9> VR_SVID_DAT
5
1
2.2_0402_1%
PR558
@EMI@ PR559
4.7_1206_5%
2
1
2
2
1000P_0402_25V8J
10U_0805_25V6K
PC532
2
1
10U_0805_25V6K
PC531
2
1
PR540
130_0402_1%
2
1
PR536
54.9_0402_1%
1
2
1
2
<9> VR_SVID_CLK
@EMI@ PC534
680P_0402_50V7K
1
2
PR557
3.01K_0402_1%
2
1 2
PR563
18.7K_0402_1%
2
1
1
2
PR562
2.26K_0402_1%
2
1
EMI Part (47.1)
<9> VR_SVID_ALRT#
CSN1
+5VS
1
CPU_B+
PC524
.1U_0402_16V7K
2
@EMI@ PR535
4.7_1206_5%
2
1
9
PC521
2
1
1000P_0402_25V8J
PC520
2
1
10U_0805_25V6K
10U_0805_25V6K
PC518
2
1
CPU_CORE
TDC 16A
Peak Current 29A
OCP current 48.5A
Load line -2.9mV/A
FSW=1MHz
DCR 0.62mohm +/-5%
TYP
H/S Rds(on) : mohm ,
L/S Rds(on) : mohm ,
@EMI@ PC523
680P_0402_50V7K
1
2
CSP1
@ PC537
0.12U_0402_10V6K~D
EMI Part (47.1)
1
PR554
2.26K_0402_1%
2
1
PC555
100U_25V_M
1
2
PC528
0.15U_0402_10V6K
PC554
100U_25V_M
CPU_B+
+3VS
1
CPU_B+
+
1
PR539
10K_0402_1%
2
2
1
1
PAD
PC522
1U_0603_25V6
1
2
VR_SVID_DAT
2
2
1
2
1
+
2
B+
PH502
10K_0402_1%_TSM0A103F34D1RZ
VGATE <28>
PR556
3.01K_0402_1%
2
1 2
3
PR555
18.7K_0402_1%
2
1
PWM2
2
<44>
+VCCIO_OUT
4
2
1
PC997
22U_0603_6.3V6M
1
@ PC999
22U_0603_6.3V6M
4
PR533
10_0402_1%
1
2
PC519
1U_0402_6.3V6K
2
1
PC993
22U_0603_6.3V6M
1
PWM1
5
1
+5VALW
2
1
PC992
22U_0603_6.3V6M
PH503
10K_0402_1%_TSM0A103F34D1RZ
3
2
1
PC991
22U_0603_6.3V6M
2
SKIP
33
ALERT#
32
7
6
2
PC517
0.33U_0402_10V6K
VR_ON
PR534
10_0402_1%
O-USR
F-IMAX
VCLK
VDIO
8
VREF
PR531
PC515
10K_0402_1% 330P_0402_50V7K
1
2
1
2
2
1
PC990
22U_0603_6.3V6M
9
10
11
12
OCP-I
B-RAMP
VR_HOT#
VR_SVID_ALRT#
PR530
10K_0402_1%
1
2
PR532
3.24K_0402_1%
1
2
VDD
31
@ PC514
2.2P_0402_50V8C
1
2
13
GFB
VFB
PW M3
PGOOD
VR_SVID_CLK
@ PR567
0_0402_5%
IMON
CSN3
GND
2
CSP3
30
1
TPS51631RSMR_QFN32_4X4
29
24
23
PW M2
VR_HOT#
VFB
@ PR566
0_0402_5%
1
2
CSP2
V5A
22
PW M1
28
2
0_0402_5%
GFB
SLEWA
1
@ PR529
21
THERM
20
SKIP#
CSN2
VREF
CSP2
@ PR528
0_0402_5%
1
2
VR_ON
CSN1
COMP
19
27
18
CSN2
14
15
16
VBAT
VCCSENSE
CSN1
CSP1
DROOP
VSSSENSE
<9>
17
25
10,9>
CSP1
2
1
PC989
22U_0603_6.3V6M
1
26
+3VS
1
F-IMAX
O-USR
PU500
2
B-RAM
SLEWA
PR552
10K_0402_1%
2
1
CPU_B+
OCP-I
2
PR551
39K_0402_1%
1
PR548
39K_0402_1%
2
1
1
1
C
+CPU_CORE
PC527
.1U_0402_16V7K
2
1
2
@ PR550
10K_0402_1%
PR549
10K_0402_1%
2
1
1
VREF
PH501
100K_0402_1%_TSM0B104F4251RZ
2
1
A
Issued Date
CPU_CORE controller (36.1), Support component (36.3)
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/24
Deciphered Date
2012/07/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CPU_CORE-37W
A
B
C
Rev
1.0
VSKAA
Date:
Sheet
D
54
of
57
A
@ PC902
4.7U_0603_6.3V6M
D
EMI Part (47.1)
VGA_CORE controller (43.1), Support component (43.2)
+VGA_B+
EMI@ PL901
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
2
1
18 Kohm
27 Kohm
1.8 nF
GL@ PR915
30K_0402_1%
GL@ PR930
3K_0402_1%
GL@ PR914
27K_0402_1%
PVCC_VGA
20
2
1
@ PR901
0_0402_5%
PC931
560U_D2_2VM_R4.5M
+5VS
+VGA_B+
UGATE2_2_VGA
10K_0402_5%
+3VS
1
4
1
PQ903
AON7518
<17,33>
PR924
2.2_0603_5%
2
1
PC944
0.22U_0603_10V7K
2
BOOT2_2_VGA 1
3
3
2
1
VGA_PWROK
2
1
PR923
0_0603_5%
2
1
2
BOOT2_VGA
PC943
10U_0805_25V6K
19
PC942
10U_0805_25V6K
18
17
16
14
1
2
22
21
4.7U_0603_10V6K
1
2
5
GL@ PC940
1800P_0402_50V7K
2
1
2
1
1 SNUB1_VGA 2
1
2
GV@ PR911
35.7K_0402_1%
PHASE1_VGA
EMI Part (47.1)
PC935
UGATE2_VGA
PR927
2
2
23
NCP81172MNTWG_QFN24_4X4
PR925
2
PC917
10U_0805_25V6K
1
2
3
2
1
5
BOOT1_VGA
PC930
1
2
HG1
BST1
24
BST2
HG2
PGOOD
VCC
TALERT#
3
2
1
<13,15,16,17,38>
.1U_0402_16V7K
10K_0402_5%
2
1
PR912
<13>
+3VS_DGPU
+3VS_DGPU
<13>
1
2
EN_VGA
3
EN
PSI_VGA
4
5
VID
6
VIDBUF
2
TSNS
PH2
2
@EMI@ PC906
680P_0402_50V7K
7x7
2.2_0402_5%
+5VS
1
PL904
0.22UH_MMD-06DZNR22MEO1L_25A_20%
1
2
PHASE2_VGA
+VGA_CORE
PQ904
TPCA8059
@EMI@ PR916
4.7_1206_5%
1
4
LGATE2_VGA
@EMI@ PC916
680P_0402_50V7K
2
Rds=3.8mΩ(Typ)
4.8mΩ(Max)
+
2
@ PC947
330U_D2_2V_Y
PR914
COMP
+
1
R4
LG2
Rds=3.8mΩ(Typ)
4.8mΩ(Max)
1 SNUB2_VGA 2
3 Kohm
FB
1
5
2 Kohm
PVCC
+VGA_CORE
@EMI@ PR906
4.7_1206_5%
4
3
2
1
30 Kohm
GL@ PR913
39K_0402_1%
PQ902
TPCA8059
PC946
1U_0402_10V6K
39 Kohm
2
PR922
82K_0402_1%
12
PGND
FBRTN
VCC_VGA
20 Kohm
2.7 nF
2FB2_VGA1
11
FS
2
N14M-GL
PR930
PC940
1
PC939
100P_0402_50V8J
N14P-GV2
20 Kohm
FB_VGA
PC938 10P_0402_50V8J
1
2
COMP_VGA
LG1
13
@ PR920
0_0402_5%
1
2
PC937
PR919
47P_0402_50V8J
51_0402_1%
1
2 FB1_VGA1
2
PR921
10K_0402_1%
1
2
R3
C
9
7x7
LGATE1_VGA
PH1
4
B+
1
PL903
0.22UH_MMD-06DZNR22MEO1L_25A_20%
1
2
UGATE1_VGA
VREF
1
PR915
FS
REFIN
VREF
R2
PR913
1
34K_0402_1%
8
10
3
R1
2
PR931
PC934
.01U_0603_16V7K
7
GND
VGA_VCC_SENSE
@ PR917
0_0402_5%
1
2
1 GV@ PC940
REFIN
2700P_0402_50V7K
VREF
25
<15>
VGA_VSS_SENSE
PC936
1000P_0402_50V7K
2
1
<15>
2
PU900
PR926 5.9K_0402_1%
2
1
2
1
1
1
GV@ PR914
18K_0402_1%
2
1
PRV11 = 34K ==>Fsw = 450KHz
GV@ PR930
2K_0402_1%
2
@ PC933
1500P_0402_50V7K
PSI
VIDBUF
2
UGATE1_2_VGA
PR907
PC922
2.2_0603_5%
0.22U_0603_10V7K
2
1BOOT1_2_VGA 1
2
GPU_VID
15
GV@ PR913
20K_0402_1%
2
1
PSI
DGPU_VID
PR929 10K_0402_5%
2
1
@ PR932 0_0402_5%
1
2
1
@ PR909
0_0402_5%
2
@ PC956
4.7U_0603_6.3V6M
@ PC954
4.7U_0603_6.3V6M
2
1
@ PC955
4.7U_0603_6.3V6M
2
1
@ PC953
4.7U_0603_6.3V6M
2
1
@ PC952
4.7U_0603_6.3V6M
2
1
PC929
4.7U_0603_6.3V6M
2
1
PC928
4.7U_0603_6.3V6M
2
1
PC927
4.7U_0603_6.3V6M
2
1
GV@ PR915
20K_0402_1%
1
VREF 2
PR908
0_0603_5%
2
1
PC910
10U_0805_25V6K
5
PC921
0.1U_0402_10V7K
PC926
4.7U_0603_6.3V6M
2
1
1
PC925
4.7U_0603_6.3V6M
2
1
2
2
PQ901
AON7518
Near VGA Core
PC924
47U_0805_6.3V6M
1
PC923
22U_0603_6.3V6M
2
1
+VGA_CORE
PC920
0.1U_0402_10V7K
2
1
PC919
0.1U_0402_10V7K
2
1
1
2
PC918
0.1U_0402_10V7K
2
1
1
@EMI@ PC915
2200P_0402_50V7K
@ PC949
4.7U_0603_6.3V6M
2
1
@ PC951
4.7U_0603_6.3V6M
2
1
@ PC950
4.7U_0603_6.3V6M
2
1
PC913
4.7U_0603_6.3V6M
2
1
PC912
4.7U_0603_6.3V6M
2
1
PC911
4.7U_0603_6.3V6M
2
1
PC958
4.7U_0603_6.3V6M
2
1
PC908
4.7U_0603_6.3V6M
2
1
PC907
4.7U_0603_6.3V6M
2
1
PC909
4.7U_0603_6.3V6M
2
1
PC905
4.7U_0603_6.3V6M
2
1
C
GB4-128 package
Under VGA Core
PC904
4.7U_0603_6.3V6M
2
1
1
2
PC903
4.7U_0603_6.3V6M
2
1
+VGA_CORE
B
EMI Part (47.1)
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/09/24
Deciphered Date
2013/09/24
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+VGA_COREP
Date:
A
B
C
Rev
1.0
VSKAA
Sheet
D
55
of
57
A
B
C
D
E
PW R PIR (Pro d u ct Im p ro ve Re co rd )
VS K A A LA -9866P S ch em a tic Ch a n g e List
1
2
It e m
1
2
3
4
5
6
Tim e (W h e n )
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
P age (W h e re )
P 4 8 -P W R-BA TTERY C O N N / O TP
P 4 8 -P W R-BA TTERY C O N N / O TP
P 4 9 -P W R-CH A RGER
P 5 0 -P W R-3 V A L W / 5 V A L W
P 5 1 -P W R-1 .3 5 V P / 0 .6 7 5 V SP
P 5 1 -P W R-1 .3 5 V P / 0 .6 7 5 V SP
7
EV T--2 0 1 2 / 1 0 / 2 4
P 5 4 -P W R-CP U_C O RE-3 7 W
P R5 4 1 / 4 7 5 K chan ge t o 1 6 9 K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
EV T--2 0 1 2 / 1 0 / 2 4
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
P 5 4 -P W R-CP U_C O RE-3 7 W
P 5 4 -P W R-CP U_C O RE-3 7 W
P 5 4 -P W R-CP U_C O RE-3 7 W
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 0 -P W R-3 V A L W / 5 V A L W
P 5 0 -P W R-3 V A L W / 5 V A L W
P 5 1 -P W R-1 .3 5 V P / 0 .6 7 5 V SP
P 5 5 -P W R-GP U_CO RE
P 5 4 -P W R-CP U_C O RE-3 7 W
P 5 4 -P W R-CP U_C O RE-3 7 W
P 5 5 -P W R-GP U_CO RE
P 4 8 -P W R-BA TTERY C O N N / O TP
P 4 9 -P W R-CH A RGER
@ P R5 5 3 / Re m ove (P W M 3 float in g)
@ P C 5 3 7 / A d d 0 4 0 2 C ap foot p rin t
@ P C 5 3 8 / A d d 0 4 0 2 C ap foot p rin t
P R9 2 9 / A d d 1 0 K re sist or
P R9 1 3 / 3 9 K ch an ge t o 2 0 K(G V @ )
P R9 1 5 / 3 9 K ch an ge t o 2 0 K(G V @ ), 3 0 K(G L @ )
P R9 3 0 / 1 .5 K ch an ge t o 2 K(GV @ ), 3 K(GL @ )
P R9 1 4 / 3 0 K ch an ge t o 1 8 K(G V @ ), 2 4 K(G L @ )
P R9 0 4 / 1 .5 K ch an ge t o 0 (GV @ ), 3 K(GL @ )
P C 9 4 0 / A d d 2 .7 n F(GV @ ), 1 .8 n F(GL @ )
P C 9 3 3 / Re se rve
P R3 3 7 / 2 3 5 K chan ge t o 1 6 5 K
P R3 5 7 / 1 5 6 K chan ge t o 1 4 3 K
P R1 5 8 / 1 6 .2 K ch an ge t o 1 5 .4 K
P R9 3 1 / 7 1 .5 K ch an ge t o 3 4 K
P C 5 2 1 / A d d 1 0 0 0 P _0 4 0 2 C ap acit or
P C 5 3 3 / A d d 1 0 0 0 P _ 0 4 0 2 C apacit or
P R9 2 7 / ch an ge re sist or P N
P F2 / ch an ge com p on e nt for cost d ow n
P Q 2 0 3 / A O N 6 5 0 4 C h an ge t o TP CA 8 0 5 7
P C 3 5 1 , P C 3 5 2 / Re m ove O SC O N m ou n t p olym e r
CAP
P R4 0 9 / A d d 1 0 0 K
P C 3 4 1 , P C 3 4 4 / A d d 4 .7 U for L DO 5 & C h an ge P C 3 4 1
size t o 0 6 0 3
P L 1 5 2 / C h an ge ch oke valu e
P L 4 0 1 / C h an ge b e ad
P R4 0 3 , P C 4 0 3 / Re se rve P R4 0 3 & P C 4 0 3
P L 5 0 2 , P L 5 0 5 / C h an ge ch oke valu e
P C 5 2 8 , P C 5 2 9 , P C 5 3 7 , P C 5 3 8 / A d d 0 4 0 2 C ap
foot p rin t
PC993, PC994, PC995, PC996, PC997, PC1101,
P C 1 1 0 3 / A d d M L C C P C 9 9 3 ~P C 9 9 7 , re m ove
p olym e r P C 1 1 0 1 , P C 1 1 0 3
PC934 /
P L 9 0 3 , P L 9 0 4 / C h an ge ve n d or
P R9 1 2 / C han ge short p ad t o 1 0 K
PC407 /
P R5 4 1 ch an ge from 1 6 9 K t o 6 4 .9 K
P R5 4 2 ch an ge from 1 5 0 K t o 2 0 K
P R5 4 7 ch an ge from 1 7 4 K t o 1 9 6 K
P C 5 1 4 re se rve
P R5 3 2 ch an ge from 3 .1 6 K t o 3 .2 4 K
P R5 5 4 ,P R5 6 2 ch an ge from 2 .3 7 K t o 2 .2 6 K
P R5 5 5 ,P R5 6 3 ch an ge from 1 7 .8 K t o 1 8 .7 K
P R9 0 4 ,P R9 1 8 ,P R9 2 8 ,P C 9 4 5 re m ove
P R9 1 4 ch an ge from 2 4 K t o 2 7 K
P R4 0 6 ad d 1 K
P C 4 0 7 ch an ge from 3 3 0 p t o 4 7 0 0 p
P R9 1 1 m ou n t
P C 9 4 7 re se rve
P R6 0 2 ch an ge t o 1 3 3 K
add P R4 0 6
ch ange P L 1 5 2 p art n u m b e r
28
D V T--2 0 1 2 / 1 2 / 0 7
P 5 0 -P W R-3 V A L W / 5 V A L W
29
D V T--2 0 1 2 / 1 2 / 0 7
P 5 0 -P W R-3 V A L W / 5 V A L W
30
D V T--2 0 1 2 / 1 2 / 0 7
P 5 0 -P W R-3 V A L W / 5 V A L W
31
32
33
34
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
P 5 1 -P W R-1 .3 5 V P / 0 .6 7 5 V SP
P 5 2 -1 .0 5 V S_V C CP
P 5 2 -1 .0 5 V S_V C CP
P 5 4 -P W R-CP U_C O RE-3 7 W
35
D V T--2 0 1 2 / 1 2 / 0 7
P 5 4 -P W R-CP U_C O RE-3 7 W
36
D V T--2 0 1 2 / 1 2 / 0 7
P 5 5 -P W R-GP U_CO RE
37
38
39
40
41
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
D V T--2 0 1 2 / 1 2 / 0 7
P V T--2 0 1 3 / 0 2 / 2 5
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 5 -P W R-GP U_CO RE
P 5 2 -1 .0 5 V S_V C CP
P 5 4 -P W R-CP U_C O RE-3 7 W
42
P V T--2 0 1 3 / 0 3 / 0 4
P 5 5 -P W R-V GA _C O RE
43
P V T--2 0 1 3 / 0 3 / 0 4
P 5 2 -1 .0 5 V S_V C CP
44
45
46
47
48
P V T-2 0 1 3 / 0 3 / 2 1
P V T-2 0 1 3 / 0 3 / 2 1
P V T-2 0 1 3 / 0 3 / 2 1
P V T-2 0 1 3 / 0 3 / 2 1
P V T-2 0 1 3 / 0 3 / 2 1
P 5 5 -P W R-V GA _C O RE
P 5 5 -P W R-V GA _C O RE
P 5 3 -P W R-1 .5 V S
P 5 2 -P W R-1 .0 5 V S_V C C P
P 5 1 -P W R-1 .3 5 V P / 0 .6 7 5 V SP
3
4
L ocat ion / Discrip t ion ( H ow / W hat )
@ P D5 / Re m ove ESD d iod e
@ P D6 / Re m ove ESD d iod e
@ P C 2 2 1 / Re m ove 1 0 u F capacit or
P C 3 3 1 ,@ P C 3 3 2 / P C 3 3 1 Re se rve & P C3 3 2 M ou n t
@ P J6 7 5 / JUM P _4 3 x7 9 ch an ge t o JUM P _4 3 x3 9
@ P J1 3 5 2 / Re m ove
Re qu e st (W h o)
COMPAN Y
COMPAN Y
COMPAN Y
ME
PW R
PW R
PW R
COMPAN Y
PW R
PW R
HW
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
COMPAN Y
PW R
ME
PW R
Re son (W h y)
For p art cou n t re d u cat ion
For p art cou n t re d u cat ion
For p art cou n t re d u cat ion
M E lim it at ion
For d e sign ch an ge
For d e sign ch an ge
For TP S5 1 6 3 1 u n d e r -sh oot
se t t in g
For p art cou n t re d u cat ion
For TP S5 1 6 3 1 t h e rm al se t t in g
For TP S5 1 6 3 1 t h e rm al se t t in g
P u ll h igh P SI p ort
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For N 1 4 P W M V ID se t t in g
For RT8 2 4 3 3 V O C P se t t in g
For RT8 2 4 3 5 V O C P se t t in g
For RT8 2 0 8 1 .3 5 V O C P se t t in g
For N C P 8 1 1 7 2 Fsw se t t in g
For d e sign ch an ge
For d e sign ch an ge
For P N se t t in g e rror
For cost dow n
For d e sign issu e
1
2
M E lim it at ion
P u ll h igh for P GO O D p ort
PW R
for IC d e fau lt se t t ing
PW R
PW R
C om m on d e sign ch an ge
C om m on d e sign ch an ge
PW R
C om m on d e sign ch an ge
PW R
C om m on d e sign ch an ge
PW R
For H F d e sign
PW R
PW R
PW R
PW R
PW R
C om m on d e sign ch an ge
C h an ge for losin g
P u ll h igh for EN p ort
C om m on d e sign ch an ge
for IC TP S5 1 6 3 1 e d it ion ch an ge
from ES1 .1 t o ES2 .1 fin e t u n e
PW R
PW R
Re m ove an d ch an ge for Rich t e k
solu t ion se t t in g
C om m on d e sign ch an ge
PW R
PW R
PW R
PW R
PW R
M ou n t for GV 2 se t t in g
For p art cou n t re d u cat ion
ad ju st cu rr e n t lim it value
circu it p rot e ct ion fu n ct ion
for d e sign ch an ge
3
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/04/19
Issued Date
4
2015/04/19
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
DC-DC INTERFACE
Rev
1.0
Thursday, May 09, 2013
Sheet
E
56
of
57
5
4
3
2
1
HW PIR (Product Improve Record)
VSKAA LA-9866P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/12/05
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
----------------------------------------------------------------------------------------------------------------------------------------------------------------D
C
B
A
Item
Date
Page
Action
Component
Request
----------------------------------------------------------------------------------------------------------------------------------------------------------------1)
11/19
24
Delete
R23,R24,R25,R26
HDMI Redriver SMBus connect to EC directly
2)
11/19
31
Change Config
RH17 to LVDS@
3)
11/19
31
Change Config
RH18 to IEDP@
4)
11/19
44
Change
RB36 from 2.2K to 0 ohm
Change EC_ON workround to power side
5)
11/19
44
Change Config
CB50 to @
6)
11/19
42
Change Config
CA32 to always mount
7)
11/19
30
Change
PCH_SPICS1# to UH3, PCH_SPICS0# to UH4
For Shark Bay ME code location
8)
11/19
44
Change
EC pin128 from EC_CS0# to EC_CS1#
For SW request
9)
11/22
33
Change
PCH_GPIO69 to PROJECT_ID
For SW request
10)
11/22
33
Change
PCH_GPIO22 to VRAM_DR_SR#
For VBIOS setting of DRANK or SRANK
11)
11/23
26
Change Config
C238~C243 to CRT@EMI@
12)
11/23
23
Add
D92
For isolate the +3VL power rail form LID_SW#
13)
11/28
41
Change
Change C987,C900 from 1206 to 0805
To avoid MLCC from cracking
14)
11/29
23
Change
Change JLVDS.4 from LID_SW# to BK_OFF#
Common design change
15)
11/29
43
Change
Change JSPK from 8 pins to 6 pins
Common design change
16)
11/29
33
Change
Delete SPK_DET1 and change SPK_DET0 netname to SPK_DET
SPK detection method was changed
17)
11/29
42
Change
Change RA50 to 269@
Used for avoiding from S&M noise issue
18)
11/29
12
Change
Change CD31 from 1206 to 0805
To avoid MLCC from cracking
19)
11/29
24
Change
Stuff 8401@ as default add reserve R168,R169
For the purpose of HDMI 4K2K jetter cleaner
20)
11/29
40
Add
Add QW1,RW3,RW4 to have inversion circuit
For normal close connector type
21)
11/29
45
Add
Add H19, change H7 to H_4P0,change H4,H5 to H_3P3
ME's requirement
22)
12/02
26
Add
Add R62 R63 22ohm
For CRT undershoot issue
23)
12/02
44
Change
Change PM_SLP_S4# from pin127 to pin84
For EC fix code design
24)
12/02
44
Change
Change USB_EN#0 from pin84 to pin23
For EC fix code design
25)
12/02
44
Change
Change FB_CLAMP from pin23 to pin127
For EC fix code design
26)
12/03
05
Add
Add CC63,CC68,CC69,CC83 100P
For ESD
27)
12/03
31
Change
Change CH104 to 0.1U
For ESD
28)
12/03
10
Change
Change CC53 to 47U
For cost down
29)
12/03
41
Add
Add QR1,RR1,RR2,RR3,RR4
For colay 14640 Charge IC
==================== PVT Modify Items ===================
1)
02/03
05
Del
Del C6 (1000P on +FAN1)
2)
02/03
11
Change
Change RC78 to 1K
For SM_DRAMRST# rising smoothly
3)
02/03
11
Del
Del CD15,CD2,CD22,CD23,CD12
For cost down
4)
02/03
12
Del
Del CD28,CD46,CD43,CD44,CD38
For cost down
5)
02/03
12
Change
RC109,RC110,RC111,RC120,RC121,RC122 from 0.5% to 1%
For cost down
6)
02/03
12
Reserve
CC65,CC71,CC72,RC3,RC8,RC9
For common design
7)
02/03
17
Del
CV58
For part coumt
8)
02/03
25
Del
C264
For part coumt
9)
02/03
25
Change
U16 to SA00006H000
For common design
10)
03/08
23
Reserve
D89
For ESD request
11)
03/15
44
Reserve
CB17, CB18, CB19
For ESD request
12)
03/15
05
Reserve
CC2,CC3
For ESD request
13)
03/15
33
Reserve
CH7
For ESD request
14)
03/15
23
Add
D2, D3 on INT_MIC_DATA & INT_MIC_CLK
For ESD request
15)
03/15
40
Add
CW10~CW14, LW1~LW6
For solving EMI test fail
16)
03/15
23
Reserve
R104, R105
For colay EMI common mode choke
17)
03/15
26
Change
R138 to 150ohm array chip resistor
For part count reduce
18)
03/15
45
Add
R268,R269
For WOWL LED behavior requested by customer
19)
03/15
42
Change
RA42 from 0 ohm to bead
For EMI request
20)
03/15
44
Add
RB17, RB38
For solving bobo noise
21)
03/15
44
Add
RB14 & link EC pin 123 to POK
For power request
22)
03/15
11
Change
RC78 from o ohm to 1K
For making SM_DRAMRST# rising more better
23)
03/15
31
Add
RH127, RH128
For HDMI_HPD no use port to default pull down
24)
03/15
35
Change
RH14 to short pad & reserve RH15 to ohm
For change +VCCCFUSE to +1.05VS_PCH
25)
03/15
31
Change
RH155 to 150ohm array chip resistor
For part count reduce
26)
03/15
25
Change
U16 from AP2330 to AP2151
For common design
27)
03/15
30
Change
4M+2M solution to 8M only solution
For common design
28)
03/15
25
Del
C264
For part count reduce
29)
03/15
17
Del
CV58
For part count reduce
30)
03/15
22
Del
LT3
For no colay RTD2132S
31)
03/15
23
Del
R81, R82
For no colay RTD2132S
Security Classification
Compal Secret Data
Compal Electronics, Inc.
32)
03/15
40
Change
CW9 from 10P to 4.7P
For vendor recommendation
Title
2010/09/03
2012/12/31
Issued Date
Date
33)
03/15
45
Del
SW3
For Deciphered
ME limitation
HW-PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
D
C
B
A
Rev
1.0
Thursday, May 09, 2013
Sheet
1
57
of
57
www.s-manuals.com
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.6
Linearized : No
XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Format : application/pdf
Creator : Compal LA-9866P - Schematics. www.s-manuals.com.
Title : Compal LA-9866P - Schematics. www.s-manuals.com.
Create Date : 2013:05:30 10:41:16
Creator Tool : PScript5.dll Version 5.2.2
Modify Date : 2015:11:11 22:06:55+02:00
Metadata Date : 2015:11:11 22:06:55+02:00
Producer : A-PDF Watermark 4.7.2 ; modified using iTextSharp 4.1.6 by 1T3XT
Text 0020 Watermark : {1BB492FB-9723-446D-9965-8F106C72B29A}
Document ID : uuid:34d5ae0b-8fe3-4d08-9bed-680759b0dc58
Instance ID : uuid:95803ddd-52ee-4606-8adf-e29eef5391a9
Has XFA : No
Page Count : 58
Author : Compal LA-9866P - Schematics. www.s-manuals.com.
Text Watermark : {1BB492FB-9723-446D-9965-8F106C72B29A}
Warning : [Minor] Ignored duplicate Info dictionary
EXIF Metadata provided by EXIF.tools