Compal LA 9941P Schematics. Www.s Manuals.com. R0.1 Schematics
User Manual: Motherboard Compal LA-9941P VAUB0 - Schematics. Free.
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A
B
C
D
E
MODEL NAME : VAUB0
PCB NO : LA-9941P
DAA0006W000
Dell/Compal Confidential
BOM P/N : TBD
1
ZZZ
ZZZ
PCB
PCB
R1@
R3@
1
Schematic Document
Phantom(Shark Bay)
Hasweill(BGA) + Lynx Point
DISCRETE VGA N14P(optimus) --- Testarossa
DISCRETE VGA N15P(optimus) --- Testarossa-P
2
2
2013-01-02
Rev: 0.1 (X00)
R3@U6
R1@U6
CPU
PCH
UV1
UV1
N15R3@
@ : Nopop Component
CONN@ : Connector Component
TPM@ : TPM function
DSP@ : DSP function
N14@ : DGPU N14P-GT
N15@ : DGPU N15P-Q1
R3@U7
N15P-Q1
N14R3@
CPU
PCH
UV1
UV1
N15R1@
N14P-GT
R1@U7
N15P-Q1
N14R1@
N14P-GT
3
Samsung 2G
Samsung 2G
UV5
UV6
UV5
UV6
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
UV9
UV10
UV9
UV10
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
K4G41325FC-HC04_FBGA170P~D
VRAMSR3@
VRAMSR3@
VRAMSR3@
VRAMSR3@
Hynix 2G
4
3
VRAMSR1@
VRAMSR1@
VRAMSR1@
VRAMSR1@
Hynix 2G
UV5
UV6
UV5
UV6
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
UV9
UV10
UV9
UV10
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
H5GC4H24MFR-T2C_FBGA170P~D
VRAMHR3@
VRAMHR3@
VRAMHR3@
VRAMHR3@
VRAMHR1@
VRAMHR1@
4
VRAMHR1@
VRAMHR1@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2011/08/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Cover Page
Document Number
Rev
0.1
LA-9941P
Wednesday, September 04, 2013
E
Sheet
1
of
62
A
B
C
D
E
128M*16 x4 =1G
VRAM * 4
GDDR5
P.29~30
Memory Bus (DDR3L)
GB4-128
GPU
N14P-GT
1
Mini DP
mDP
Redriver
P.37
page 14,15
1
16GB Max
HDMI
BGA 1364
DP
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3L 1600 MHz
Intel
Haswell
Processor
35W QC
P.24~28
CPU XDP
Conn. P.6
DDRIII-DIMM X2
Dual Channel
PEG 3.0 x16
P.37
eDP
P.5~13
HDMI
Redriver
P.36
FHD
(eDP 1.3)
P.35
HDMI
P.36
DMI x4
100MHz
5GB/s
PCI-E x1
Port 3
2
SATA3.0
Port 1
Card Reader
RTS5249
Mini Card-1 (Half)
(WLAN+BT4.0)
P.42
Port 2
Port 4
Intel
Lynx Point LP
3 in 1
Socket
Daughter board
Daughter board
SPI Flash
(BIOS 8MB)
USB 3.0
BGA 695 Balls
SATA ODD Conn.
USB 3.0
Re-driver
P.43
USB Powershare
TPS2543 X2
P.45
Port 0,1
P.16
Port 12
USB 3.0 Conn. X2
( USB Charger )
P.45
Digital Camera
P.35
SMBus
Port 9
P16~23
P.43
Touch Panel
Conn.
P.40
HD Audio
ALC5505
DSP
33MHz
3
P.46
Digi Mic
P.40
Audio Codec
ALC3661
ENE KBC
KB9012 +
KC3810 P.38
P.46
P.16
Power On/Off CKT.
2
P.42
P.44
Discrete TPM
AT97SC3204
RTC CKT.
P.43
Mini Card-2 (mSATA)
USB2.0
LPC Bus
RTC Counter
IDT 1337
Port 1,2
HDD
SPI
NFC
P.49
Magnetic Peak
FFS
SATA3 Re-driver
PS8520
P.43
( Full )
USB2.0
3
Port 0
Port 4
Headphone / Mic. Jack
P.47
( Combo )
SMBus
PS/2
PWM
P.47
P.39
DC/DC Interface CKT.
Fan Control
P.39
P.33~34
Int.KBD
P.39
Touch Pad
AMP TI 3113
ALS Sensor
P.39
P.48
P.35
4
4
Int. Speaker x2
P.48
Issued Date
Compal Electronics,Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
A
B
C
D
Document Number
Rev
0.1
Tuesday, September 03, 2013
E
Sheet
2
of
62
A
B
C
D
E
Compal Confidential
Project Code : VAUB0
File Name : LA-9941P
1
1
JTS
LA-9941P M/B
JeDP
6 pin
Wire
40 pin
Wire
Touch screen
LCD Panel
2
2
JHDD
HDD
24 pin
8 pin
Wire
FFC
JTB1
90 pin
Touch Pad
3
3
FFC
JIO1
I/O B
4
4
2011/08/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
E
3
of
62
A
USB PORT#
PCH
PCI EXPRESS
1
DESTINATION
SATA
DESTINATION
CLKOUT
None
SATA0
HDD
PCI0
Lane 2
None
SATA1
SSD
PCI1
EC LPC
Lane 3
MINI CARD-1 WLAN
SATA2
None
PCI2
None
Lane 4
CARD READER
SATA3
None
PCI3
None
Lane 5
None
SATA4
None
PCI4
None
Lane 6
None
SATA5
None
Lane 7
None
Lane 8
None
CLK
DESTINATION
FLEX CLOCKS
1
USB Conn 3 (Power share)
2
USB Conn 2 (Power share)
3
USB Conn 4 (Power share)
4
JMINI1 (WLAN)
5
None
6
None
7
None
8
None
9
Touch screen
10
None
11
None
12
CAMERA
13
None
1
USB3
DESTINATION
1
USB Conn 1 (Power share)
2
USB Conn 3 (Power share)
3
USB Conn 2 (Power share)
4
USB Conn 4 (Power share)
DESTINATION
None
CLKOUTFLEX0
CLK_PCI_TPM
CLKOUT_PCIE1
None
CLKOUTFLEX1
None
CLKOUT_PCIE2
None
CLKOUTFLEX2
None
CLKOUT_PCIE3
MINI CARD-1 WLAN
CLKOUTFLEX3
None
CLKOUT_PCIE4
CARD READER
CLKOUT_PCIE5
None
CLKOUT_PCIE6
None
CLKOUT_PCIE7
None
None
USB Conn 1 (Power share)
PCH_LOOPBACK
CLKOUT_PCIE0
CLKOUT_PEG_B
0
DESTINATION
Lane 1
DIFFERENTIAL
DESTINATION
Symbol Note :
: means Digital Ground
: means Analog Ground
2011/08/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2012/07/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
Notes List
Document Number
LA-9941P
Tuesday, September 03, 2013
Rev
0.1
Sheet
4
of
62
5
4
3
2
1
2.2K
D
R10
SMBCLK
U11
SMBDATA
2.2K
2.2K
SMBUS Address [0x9a]
+3V_PCH
2.2K
+3VS
D
+3VS
202
DMN66D0
200
DIMMA
SMBUS Address [A0]
DIMMB
SMBUS Address [A0]
TP
SMBUS Address [TBD]
FFS
SMBUS Address [TBD]
XDP
SMBUS Address [TBD]
Touch
Screen
SMBUS Address [TBD]
DMN66D0
DMN66D0
202
+3VS_NGFF
200
DMN66D0
2.2K
2.2K
4
PCH
5
2.2K
4
60
2.2K
U8
SML0CLK
R7
SML0DATA
6
+3V_PCH
58
51
2.2K
+3V_PCH
2.2K
9
SML1CLK
SML1DATA 2.2K
C
53
+3VS
2.2K
K6
SMBUS Address [TBD]
DMN66D0
DMN66D0
N11
NGFF
10
C
8
9
10
NFC
9
SMBUS Address [TBD]
ALS
SMBUS Address [TBD]
DMN66D0 DMN66D0
2.2K
2.2K
+3VS
B8
EC_SMB_CK1
8
A6
EC_SMB_DA1
7
ADS1115
SMBUS Address [TBD]
ADS1115
SMBUS Address [TBD]
KBC
8
B
7
B
2.2K
2.2K
A8
EC_SMB_CK1
A7
EC_SMB_DA1
+3VALW_EC
100 ohm
4
100 ohm
5
BATT
SMBUS Address [16]
9
8
CHARGER
SMBUS Address [12]
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/15
Deciphered Date
Title
Compal Electronics, Inc.
SMBus Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
5
of
62
5
4
3
2
1
XDP CONN
+VCCIO_OUT
+VCCIO_OUT
JXDP
D
[8]
[8]
[8]
[8]
XDP_PREQ#
XDP_PRDY#
XDP_PREQ#
XDP_PRDY#
[10]
[10]
CFG0
CFG1
[10]
[10]
CFG2
CFG3
CFG0
CFG1
CFG2
CFG3
XDP_BPM#0
XDP_BPM#1
XDP_BPM#0
XDP_BPM#1
[10]
[10]
CFG4
CFG5
[10]
[10]
CFG6
CFG7
CFG4
CFG5
CFG6
CFG7
1
RU7
[20,8] H_CPUPWRGD
[18,38] PBTN_OUT#
2 1K_0402_5%~D H_CPUPWRGD_XDP
PT
[12] CPU_PWR_DEBUG
[18,38,58] IMVP_VR_PG
[14,15,17,39,43] PCH_SMBDATA
[14,15,17,39,43] PCH_SMBCLK
[8]
C
The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net
XDP_TCK
XDP_TCK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
D
CFG17
CFG16
CFG17
CFG16
CFG8
CFG9
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
[10]
[10]
[10]
[10]
CFG10
CFG11
[10]
[10]
CFG19
CFG18
[10]
[10]
CFG12
CFG13
[10]
[10]
CFG14
CFG15
[10]
[10]
CLK_CPU_ITP [17]
CLK_CPU_ITP# [17]
RU12 1
2 1K_0402_5%~D
XDP_DBRESET#
PLT_RST#
[18,38,40,42,8]
[18,8]
PT
XDP_TDO [8]
XDP_TRST# [8]
XDP_TDI [8]
XDP_TMS [8]
SAMTE_BSH-030-01-L-D-A-TR
CONN@
C
PT
+3VS
RU36 1
2 1K_0402_5%
IMVP_VR_PG
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
6
of
62
5
4
3
2
PEG_COMP
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
D
U6A
[18]
[18]
[18]
[18]
[18]
[18]
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
[18]
[18]
[18]
[18]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
[18]
[18]
[18]
[18]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AB2
AB3
AC3
AC1
AB1
AB4
AC4
AC2
AF2
AF4
AG4
AG2
AF1
AF3
AG3
AG1
F11
F12
FDI_CSYNC
FDI_INT
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
PEG
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI
C
[18]
[18]
[18]
[18]
HASWELL_BGA
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
FDI_CSYNC
DISP_INT
FDI
B
PEG_RCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
AH6
E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1
C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2
PEG_COMP
RU1 1
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0
PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0
PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0
1
D
+VCCIOA_OUT
2 24.9_0402_1%
PEG_GTX_C_HRX_N[0..15]
PEG_GTX_C_HRX_P[0..15]
PEG_HTX_C_GRX_N[0..15]
PEG_HTX_C_GRX_P[0..15]
PEG_GTX_C_HRX_N[0..15]
[24]
PEG_GTX_C_HRX_P[0..15]
[24]
PEG_HTX_C_GRX_N[0..15]
[24]
PEG_HTX_C_GRX_P[0..15]
[24]
C
CU1
CU2
CU3
CU4
CU5
CU6
CU7
CU8
CU9
CU10
CU11
CU12
CU13
CU14
CU15
CU16
CU17
CU18
CU19
CU20
CU21
CU22
CU23
CU24
CU25
CU26
CU27
CU28
CU29
CU30
CU31
CU32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
B
1 OF 12
@
HASWELL_BGA1364
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
7
of
62
4
3
C51
+VCCIO_OUT
2 62_0402_5%
H_PROCHOT#
place RU33,RU30 near CPU
RU33 1
RU32 1
2 56_0402_5%
E50
D53
H_PROCHOT#_R
CATERR
PECI
PROCHOT
THERMTRIP
2 10K_0402_5%~D H_CPUPWRGD
JTAG
D
H_PROCHOT#
H_PROCHOT#
[20] H_THERMTRIP#
[38,53,58]
G50
G51
H_PECI
DDR3L Compensation Signals
MISC
PROC_DETECT
THERMAL
RU30 1
PT
[38]
[18] H_PM_SYNC
[20,6] H_CPUPWRGD
[20]
@ RU37 1
CPU_PLTRST#
ST
+VCCIO_OUT
2 10K_0402_5%~D
CLK_CPU_SSC_DPLL
@ RU44 1
2 10K_0402_5%~D
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
PRDY
PREQ
TCK
TMS
TRST
TDI
TDO
DBR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
CLOCK
@ RU40 1
[17] DPLL_REF_CLK#
[17] DPLL_REF_CLK
[17] CLK_CPU_SSC_DPLL#
[17] CLK_CPU_SSC_DPLL
[17] CLK_CPU_DMI#
[17] CLK_CPU_DMI
AC6
AE6
V6
Y6
AB6
AA6
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN
PWR
D52
F50
AP48
PM_SYS_PWRGD_BUF_R
2 0_0402_5%
BUF_CPU_RST# L54
1
HASWELL_BGA
U6B
Processor Pullups
2
DDR3L
5
BB51
BB53
BB52
BE51
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_DRAMRST#
N53
N52
N54
M51
M53
N49
M49
F53
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_PRDY#
[6]
XDP_PREQ# [6]
XDP_TCK [6]
XDP_TMS [6]
XDP_TRST# [6]
XDP_TDI [6]
XDP_TDO [6]
XDP_DBRESET#
XDP_DBRESET#
R51
R50
P49
N50
R49
P53
U51
P51
XDP_BPM#0
XDP_BPM#1
SM_RCOMP0
RU58 1
2 100_0402_1%~D
SM_RCOMP1
RU59 1
2 75_0402_1%~D
SM_RCOMP2
RU61 1
2 100_0402_1%~D
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
[18,6]
PU/PD for JTAG signals
[6]
[6]
+VCCP
For ESD concern, please put near CPU
2 OF 12
SSC CLOCK TERMINATION,
IF NOT USED, stuff RU40,RU44
@
D
HASWELL_BGA1364
XDP_TDO
RU66 1
2 51_0402_5%
XDP_TCK
RU67 1
2 51_0402_5%
XDP_TRST#
RU68 1
2 51_0402_5%
+3VS
XDP_DBRESET#
RU35 1
2 1K_0402_5%~D
HASWELL_BGA
U6J
C
C
+3VS
+VCCP
2
1
C16
D16
A16
B16
EDP_AUXN
EDP_AUXP
EDP_HPD
DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1
FDI_TXN0
FDI_TXP0
FDI_TXN1
FDI_TXP1
2
[38]
B
2
close CPU chip
HASWELL_BGA1364
+1.35V
RU72
1K_0402_5%~D
2
2
G
VCIN0_PH
HU101
100K_0402_1%_TSM0B104F4251RZ
+3VALW
1
2 0_0402_5%~D
2
DDR3_DRAMRST#_R
RU73 1
2 1K_0402_5%~D
DDR3_DRAMRST#
[14,15]
1
1
O
A
2
4PM_SYS_PWRGD_BUF
1
@ RU43
3
2
2 200_0402_5%
R59
3.32K_0402_1%~D
+3VALW
RU76 1
1
QU3
BSS138-G_SOT23-3
2
5
B
RU74
4.99K_0402_1%~D
RU60
1.82K_0402_1%
UU3
74AHC1G09GW_TSSOP5
1
2 0_0402_5%~D CPU1.5V_S3_GATE_R
@ RU51 1
3
H_DRAMRST#
P
@ RU50 1
+3VALW
G
1
ST
A
2
PM_SYS_PWRGD_BUF_R
0_0402_5%
DRAMRST_CNTRL_S3
ST
[14,38]
DRAMRST_CNTRL_S3
1
RU62
Issued Date
2
Compal Secret Data
2011/08/25
A
1
2
100K_0402_5%~D
For deep S3
Security Classification
Deciphered Date
CU39
0.047U_0402_16V7K
Compal Electronics,TitleInc.
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number
Custom
Date:
5
ST
1
DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1
S3 circuit:DRAM_RST# to memory
should be high during S3
PM_SYS_PWRGD_BUF_R
0_0402_5%~D
2
PM_DRAM_PWRGD
[35]
[35]
[35]
[35]
+3VALW
G
[18]
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
1
3
1
@ RU56
0_0402_5%
2 0_0402_5%~D
+V1.05S_VCCP_PWRGOOD
+VCCIOA_OUT
2 24.9_0402_1%
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
D
[38,56]
1
C12
D12
A14
B14
S
PT
RU2
10 OF 12
@
R29
100K_0402_5%~D
DRAMRST_CNTRL_S3
2
EDP_COMP
[35]
[35]
[35]
[35]
DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3
+1.35V_CPU_VDDQ
1
AG6
E12
EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1
1
C17
D17
A17
B17
BUF_CPU_RST#
2
2 43_0402_1%
1
1
S
PM_SYS_PWRGD_BUF
@ RU53
@ RU54 1
C14
A12
D14
B12
RU11
20K_0402_5%~D
QU7
BSS138-G_SOT23-3
+1.35V_PWROK
EDP_AUXN [35]
EDP_AUXP [35]
EDP_HPD
[35]
RU118
10K_0402_1%~D
@ RU48 1
BUFO_CPU_RST#
NOTE: S3 POWER REDUCTION IS NOT POR
THIS CIRCUIT IS FOR INTERNAL TESTING PURPOSES ONLY.
[55]
F15
F14
E14
1
4
SN74LVC1G07DCKR_SC70-5
D
SM_DRAMPWROK
DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3
UU2
Y
A
C21
D21
A21
B21
C20
D20
A20
B20
RU13
1K_0402_5%~D
3
B
NC
G
1
PLT_RST# 2
PLT_RST#
mDP_A0N_CPU
mDP_A0P_CPU
mDP_A1N_CPU
mDP_A1P_CPU
mDP_A2N_CPU
mDP_A2P_CPU
mDP_A3N_CPU
mDP_A3P_CPU
P
5
2
@ RU42
75_0402_5%
[18,38,40,42,6]
[37]
[37]
[37]
[37]
[37]
[37]
[37]
[37]
C25
D25
A25
B25
C24
D24
A24
B24
2
+3VS
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA
2
Buffered reset to CPU
[36]
[36]
[36]
[36]
[36]
[36]
[36]
[36]
4
3
2
Rev
0.1
Tuesday, September 03, 2013
1
Sheet
8
of
62
5
[14]
HASWELL_BGA
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
D
C
+V_SM_VREF
B
[14]
[14]
4
AH54
AH52
AK51
AK54
AH53
AH51
AK52
AK53
AN54
AN52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53
AY52
AY51
AV51
AV54
AY54
AY53
AY47
AY49
BA47
BA45
AY45
AY43
BA49
BA43
BF14
BC14
BC11
BF11
BE14
BD14
BD11
BE11
BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2
AW3
AW2
BB3
BB2
AW4
AW1
AU3
AU1
AR1
AR4
AU2
AU4
AR2
AR3
AM6
AR6
AN6
+V_DDR_REFA_R
+V_DDR_REFB_R
BC53
3
U6C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
RSVD
SA_CKN0
SA_CK0
SA_CKE0
SA_CKN1
SA_CK1
SA_CKE1
SA_CKN2
SA_CK2
SA_CKE2
SA_CKN3
SA_CK3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_BS0
SA_BS1
SA_BS2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
[15]
BD31
BE25
BF25
BE34
BD25
BC25
BF34
BE23
BF23
BC34
BD23
BC23
BD34
2
HASWELL_BGA
DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR#0 [14]
M_CLK_DDR0 [14]
DDR_CKE0_DIMMA [14]
M_CLK_DDR#1 [14]
M_CLK_DDR1 [14]
DDR_CKE1_DIMMA [14]
BE16
BC17
BE17
BD16
BC16
BF16
BF17
BD17
BC20
BD21
BD32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
BC21
BF20
BF21
BE21
BD28
BD27
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BD20
BF31
BC31
BE20
BE32
BE31
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
AW39
AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AW40
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
[14]
[14]
[14]
[14]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
[14]
[14]
[14]
DDR_A_RAS# [14]
DDR_A_WE# [14]
DDR_A_CAS# [14]
DDR_A_MA[0..15] [14]
DDR_A_DQS#[0..7]
[14]
DDR_A_DQS[0..7]
1
[14]
AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
U6D
RSVD
SB_CKN0
SB_CK0
SB_CKE0
SB_CKN1
SB_CK1
SB_CKE1
SB_CKN2
SB_CK2
SB_CKE2
SB_CKN3
SB_CK3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_BS0
SB_BS1
SB_BS2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD
BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
3 OF 12
AY36
AW27
AV27
AU36
AW26
AV26
AU35
BA26
AY26
AV35
BA27
AY27
AV36
M_CLK_DDR#2 [15]
M_CLK_DDR2 [15]
DDR_CKE2_DIMMB [15]
M_CLK_DDR#3 [15]
M_CLK_DDR3 [15]
DDR_CKE3_DIMMB [15]
BA20
AY19
AU19
AW20
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
AY20
BA19
AV19
AW19
AY23
BA23
BA36
AU30
AV23
AW23
AV20
M_ODT2
M_ODT3
D
[15]
[15]
[15]
[15]
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
[15]
[15]
[15]
DDR_B_RAS# [15]
DDR_B_WE# [15]
DDR_B_CAS# [15]
DDR_B_MA[0..15] [15]
BA30 DDR_B_MA0
AW30DDR_B_MA1
AY30 DDR_B_MA2
AV30 DDR_B_MA3
AW32DDR_B_MA4
AY32 DDR_B_MA5
AT30 DDR_B_MA6
AV32 DDR_B_MA7
BA32 DDR_B_MA8
AU32 DDR_B_MA9
AU23 DDR_B_MA10
AY35 DDR_B_MA11
AW35DDR_B_MA12
AU20 DDR_B_MA13
AW36DDR_B_MA14
BA35 DDR_B_MA15
C
DDR_B_DQS#[0..7]
AD52 DDR_B_DQS#0
AU46 DDR_B_DQS#1
BD48 DDR_B_DQS#2
BD43 DDR_B_DQS#3
AW16DDR_B_DQS#4
AW10DDR_B_DQS#5
AW8 DDR_B_DQS#6
AL2 DDR_B_DQS#7
BE38
AD53 DDR_B_DQS0
AV46 DDR_B_DQS1
BE48 DDR_B_DQS2
BE43 DDR_B_DQS3
AW15DDR_B_DQS4
AW12DDR_B_DQS5
AW6 DDR_B_DQS6
AL3 DDR_B_DQS7
BD38
[15]
DDR_B_DQS[0..7]
[15]
B
BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37
4 OF 12
HASWELL_BGA1364
HASWELL_BGA1364
@
@
1
+1.35V_CPU_VDDQ
RU83
1K_0402_1%~D
2
+V_SM_VREF
1
20mil
RU84
1K_0402_1%~D
A
2
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Close CPU side
Date:
5
4
3
2
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
9
of
62
4
3
RSVD_TP
RSVD_TP
TESTLOW_F21
VSS
VSS
VSS
VCC
L52
L53
RSVD_TP
RSVD_TP
L51
1
1
CPU_TESTLOW0
RH31
49.9_0402_1%
2
2
RH30
49.9_0402_1%
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD_TP
F24
F25
F20
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
L50
L49
E5
C
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
CFG2
CFG16 [6]
CFG18 [6]
CFG17 [6]
CFG19 [6]
B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8
1
R54
Y52
V53
Y51
V52
RU77
1K_0402_1%~D
RH27
49.9_0402_1%
1: Normal Operation; Lane #
socket pin map definition
CFG2
RSVD
D
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
RSVD_TP
RSVD_TP
TESTLOW_F20
AG49
AD49
AC49
AE49
Y50
AB49
V51
W51
Y49
Y54
Y53
W53
U53
V54
R53
R52
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
F16
*
definition matches
0:Lane Reversed
CFG4
1
+VCC_CORE
RSVD_TP
RSVD_TP
G21
G24
F21
G19
F51
F52
F22
CFG Straps for Processor
F1
E1
A5
A6
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
G12
G10
RU115
1K_0402_1%~D
H54
H53
2
D
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
F6
G6
CPU_TESTLOW1
HASWELL_BGA
2
BE4
BD3
1
1
U6K
2
2
5
H51
H52
N51
G53
H50
Display Port Presence Strap
C
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
11 OF 12
HASWELL_BGA1364
*
@
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
1
CFG5
1
U6L
HASWELL_BGA
B
A52_B52
A53_B53
B54_C54
B52
B53
B54
BE1_BD1
BC1
BC54
BD1
BE54_BD54 BD54
BE1
BE1_BD1
BE2
BE2_BF2
BE3
BE3_BF3
BE52_BF52 BE52
BE53_BF53 BE53
BE54_BD54 BE54
BF2
BE2_BF2
BF3
BE3_BF3
BF4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BF51
BF52
BF53
C1_C2
C1_C2
C3_B2
C54
D1
B54_C54
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
D54
CFG[6:5]
*10: x8, x8 - Device 1 function 1 enabled ; function 2
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
B
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
2
BE52_BF52
BE53_BF53
C1
C2
C3
AN35
AN37
AF9
AE9
G14
G17
AD45
AG45
CFG7
1
B2
B3
C3_B2
B3_A3
RSVD
RSVD
@ RU86
1K_0402_1%~D
@ RU87
1K_0402_1%~D
2
A51
A52
A53
A52_B52
A53_B53
2
@ RU85
1K_0402_1%~D
A3
A4
B3_A3
PEG DEFER TRAINING
12 OF 12
CFG7
HASWELL_BGA1364
@
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
A
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
10
of
62
5
4
3
2
1
55A
+VCC_CORE
U6F
AB45
AB46
AB8
AC46
AC47
AC8
AC9
AD46
AD8
AE46
AE47
AE8
AF8
AG46
AG8
AH46
AH47
AH8
AJ45
AJ46
AK46
AK47
AK8
AL45
AL46
AL8
AL9
AM46
AM47
AM8
AM9
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN8
AN9
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AP8
AP9
AR35
AR37
AR39
AR41
AR43
AR45
AR46
H30
H31
H32
D
C
B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
+VCC_CORE
HASWELL_BGA
6 OF 12
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H33
H34
H36
H37
H38
H39
H40
H42
H43
H45
H46
H48
H8
H9
J10
J14
J19
J24
J29
J33
J36
J37
J38
J39
J40
J42
J43
J45
J46
J48
J8
J9
K38
K40
K43
K44
K45
K46
K48
K8
K9
L37
L38
L39
L40
L42
L43
L44
L46
L47
L8
M37
M38
M39
M40
M42
M43
M44
M45
M46
M8
M9
N37
N38
N39
N40
N42
N43
N44
N46
N47
N8
N9
P45
P46
P8
R46
R47
R8
R9
T45
T46
U46
U47
U8
U9
V45
V46
V8
W46
W47
W8
Y45
Y46
Y8
A27
A28
A31
A32
A34
B27
B28
B31
B32
B34
B36
B38
B39
B42
D
C
B
HASWELL_BGA1364
A
A
@
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
PROCESSOR(5/7) PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Sheet
Tuesday, September 03, 2013
1
11
of
62
5
4
3
2
1
+VCC_CORE
+1.35V_CPU_VDDQ
+1.35V_CPU_VDDQ
+1.35V_CPU_VDDQ
+1.35V
2
2
2
1
2
1
2
+
2
CU168
330U_D2_2V_Y
2
1
CU176
10U_0603_6.3V6M~D
D
2
1
CU175
10U_0603_6.3V6M~D
2
1
CU174
10U_0603_6.3V6M~D
1 0.1U_0402_10V7K~D
1
CU173
10U_0603_6.3V6M~D
2
1
CU172
10U_0603_6.3V6M~D
CU178
1
CU171
10U_0603_6.3V6M~D
1 0.1U_0402_10V7K~D
CU170
10U_0603_6.3V6M~D
2
CU169
10U_0603_6.3V6M~D
CU177
1
1
2
1
2
1
2
1
2
1
2
CU201
1U_0402_6.3V6K~D
2
CU200
1U_0402_6.3V6K~D
1
CU199
1U_0402_6.3V6K~D
2
CU198
1U_0402_6.3V6K~D
1
CU197
1U_0402_6.3V6K~D
2
CU196
1U_0402_6.3V6K~D
1
CU195
1U_0402_6.3V6K~D
2
CU194
1U_0402_6.3V6K~D
1
CU193
1U_0402_6.3V6K~D
CU192
1U_0402_6.3V6K~D
2
+VCCIO_OUT
+VCC_CORE
CU36
0.01U_0402_16V7K~D
CAD Note: RU96 SHOULD BE PLACED CLOSE TO CPU
RU96
100_0402_1%~D
C
[58]
ST
+VCCP
@ R58 1
2 0_0805_5%
+VCCIO2PCH
30mA
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
300mA
+VCCIO2PCH
+VCCIOA_OUT
VR_SVID_ALRT#
[58] VR_SVID_ALRT#
[58] VR_SVID_CLK
[58] VR_SVID_DAT
+VCCIO_OUT
RU91 1
2 75_0402_5%
RU90 1
2 130_0402_1%~D VR_SVID_DAT
+VCCIO_OUT
+VCCIO_OUT
RU93 1
2 43_0402_1%
VR_SVID_ALRT#
[6]
CPU_PWR_DEBUG
CPU_PWR_DEBUG
CAD Note: Place the PU resistors close to CPU
RU90/RU91 close to CPU 300 - 1500mils
1
+VCCP
2
RU94
150_0402_1%~D
CPU_PWR_DEBUG
+VCC_CORE
B
4210mA
+1.35V_CPU_VDDQ
@ JP3
1
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DAT
VCC_SENSE
RSVD
VCCIO_OUT
RSVD
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
J53
J52
J50
VIDALERT
VIDSCLK
VIDSOUT
B51
F19
E52
V49
U49
AM49
W49
V50
AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A36
A38
A39
A42
A43
A45
A46
A48
AA46
AA47
AA8
AA9
+1.35V_CPU_VDDQ Source
+1.35V
RSVD
VCC
VCC
RSVD
RSVD
C50
AH9
D51
F17
AK6
AN33
W9
J12
AR49
VCCSENSE
2
PAD-OPEN 4x4m
@ JP4
1
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AN31
L6
M6
AN22
AN18
+VCC_CORE
2
1
1
2
CAD Note: CU36 SHOULD BE
PLACED CLOSE TO CPU
RSVD
RSVD
RSVD
RSVD
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
+1.35V_CPU_VDDQ
1
HASWELL_BGA
U6E
J17
J21
J26
J31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC_D5
FC_D3
B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
D5
D3
D
C
B
CPU_FC_PWR
CPU_FC_PWROK
PAD
PAD
T172
T173
@
@
5 OF 12
HASWELL_BGA1364
PAD-OPEN 4x4m
@
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Document Number
Custom
Date:
5
4
3
2
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
Rev
0.1
Tuesday, September 03, 2013
1
Sheet
12
of
62
4
3
2
U6I
HASWELL_BGA
U6G
U6H
C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7
AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4
AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT5
AT50
AT51
AT52
AT53
AT54
AT6
AT8
AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AU5
AU9
AV1
AV13
AV18
AV2
AV22
AV25
AV29
AV3
AV33
AV4
AV42
AV5
AV50
AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
7 OF 12
HASWELL_BGA1364
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
8 OF 12
HASWELL_BGA1364
B
HASWELL_BGA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SENSE
G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
R48
R7
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9
D
C
B
AR22
AB48
P9
G18
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
D50
VSSSENSE
[58]
RU99
100_0402_1%~D
CAD Note: RU99 SHOULD BE PLACED CLOSE TO CPU
A
9 OF 12
A
2
D
A11
A15
A19
A22
A26
A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4
AA48
AA5
AA7
AB5
AB51
AB52
AB53
AB54
AB7
AB9
AC48
AC5
AC50
AC7
AD48
AD51
AD54
AD7
AD9
AE1
AE2
AE3
AE4
AE48
AE5
AE50
AE7
AF5
AF6
AF7
AG48
AG5
AG51
AG52
AG53
AG54
AG7
AG9
AH1
AH2
AH3
AH4
AH48
AH5
AH50
AH7
BC10
BC12
BC15
BC18
BC22
BC26
BC3
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC5
BC50
BC52
BC7
BD10
BD15
BD18
BD36
BD41
BD46
BD5
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
BF7
C11
C15
C19
C22
C26
C30
C33
C37
C4
C40
C44
C49
C52
C8
D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49
D8
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53
E8
F2
F26
F3
F30
F33
F37
F4
F40
F44
F49
F5
G11
G13
G16
HASWELL_BGA
1
1
5
HASWELL_BGA1364
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
13
of
62
5
4
3
M1
+1.35V
D
2
All VREF traces should
have 10 mil trace width
CD2
0.1U_0402_16V7K~D
1
DDR_A_D3
DDR_A_D7
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D11
DDR_A_D16
DDR_A_D17
Layout Note:
Place near JDIMM1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
+1.35V
DDR_A_D26
DDR_A_D24
2
1
2
CD6
1U_0402_6.3V6K~D
2
1
CD5
1U_0402_6.3V6K~D
2
1
CD4
1U_0402_6.3V6K~D
CD3
1U_0402_6.3V6K~D
1
DDR_A_D28
DDR_A_D27
[9]
DDR_CKE0_DIMMA
DDR_CKE0_DIMMA
[9]
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
C
+1.35V
DDR_A_MA8
DDR_A_MA5
2
1
+
2
CD7
330U_D2_2.5VY_R15M~D
2
1
CD13
10U_0603_6.3V6M~D
2
1
CD12
10U_0603_6.3V6M~D
2
1
CD11
10U_0603_6.3V6M~D
2
1
CD10
10U_0603_6.3V6M~D
1
CD9
10U_0603_6.3V6M~D
2
CD8
10U_0603_6.3V6M~D
1
DDR_A_MA3
DDR_A_MA1
[9]
[9]
[9]
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
[9]
DDR_A_BS0
[9]
[9]
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_CS1_DIMMA#
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
+0.675VS
DDR_A_D40
DDR_A_D41
B
2
@
1
2
CD20
1U_0402_6.3V6K~D
2
1
CD19
1U_0402_6.3V6K~D
1
CD18
1U_0402_6.3V6K~D
2
CD17
1U_0402_6.3V6K~D
1
DDR_A_D42
DDR_A_D43
@
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
Layout Note:
Place near JDIMM1.199
DDR_A_D58
DDR_A_D59
RD81
2 10K_0402_5%~D
RD91
2 10K_0402_5%~D
+3VS
+0.675VS
+3VS
205
207
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND1
BOSS1
GND2
BOSS2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D1
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D12
DDR_A_D13
D
DDR3_DRAMRST#
DDR3_DRAMRST#
[15,8]
DDR_CKE1_DIMMA
[9]
DDR_A_D14
DDR_A_D10
DDR_A_D21
DDR_A_D20
DDR_A_D22
DDR_A_D23
DDR_A_D25
DDR_A_D30
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D29
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
C
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
All VREF traces should
have 10 mil trace width
M_CLK_DDR1 [9]
M_CLK_DDR#1 [9]
+V_DDR_REF
DDR_A_BS1 [9]
DDR_A_RAS# [9]
DDR_CS0_DIMMA#
M_ODT0 [9]
M_ODT1
[9]
DDR_A_D36
DDR_A_D37
1
DDR_A_D38
DDR_A_D39
2
DDR_A_D44
DDR_A_D45
[9]
CD16
0.1U_0402_16V7K~D
DDR_A_D32
DDR_A_D33
Layout Note:
Place near JDIMM1.203,204
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
M3
DDR_A_D52
DDR_A_D53
1
+V_DDR_REF
3
S
+V_DDR_REF
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
+V_DDR_REFA_R
[9]
+V_DDR_REFB_R
[9]
QD1
BSS138-G_SOT23-3
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
[38,8]
DRAMRST_CNTRL_S3
DRAMRST_CNTRL_S3
For deep S3
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PCH_SMBDATA
PCH_SMBCLK
1
+V_DDR_REF
PCH_SMBDATA [15,17,39,43,6]
PCH_SMBCLK [15,17,39,43,6]
3
S
DDR_A_MA[0..15]
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
D
DDR_A_D[0..63]
[9]
DDR_A_D4
DDR_A_D0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
G
[9]
+V_DDR_REF
+V_DDR_REF
D
DDR_A_DQS[0..7]
+1.35V
JDIMM1
DDR_A_DQS#[0..7]
[9]
1
QD2
BSS138-G_SOT23-3
+0.675VS
2
G
[9]
2
206
208
A
A
DRAMRST_CNTRL_S3
1
2
CD22
2.2U_0603_6.3V6K~D
2
CD21
0.1U_0402_16V7K~D
1
BELLW_80001-1021
For deep S3
CONN@
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
DDRIII DIMMA
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
14
of
62
5
4
M1
3
2
+1.35V
DDR_B_D2
DDR_B_D3
[9]
+V_DDR_REF
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
1
[9]
DDR_B_D[0..63]
[9]
DDR_B_MA[0..15]
2
All VREF traces should
have 10 mil trace width
CD24
0.1U_0402_16V7K~D
[9]
DDR_B_D15
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
DDR_B_D13
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
Layout Note:
Place near JDIMMB
[9]
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
[9]
DDR_B_BS2
DDR_B_BS2
+1.35V
DDR_B_MA12
DDR_B_MA9
C
2
1
2
DDR_B_MA8
DDR_B_MA5
CD28
1U_0402_6.3V6K~D
2
1
CD27
1U_0402_6.3V6K~D
1
CD26
1U_0402_6.3V6K~D
2
CD25
1U_0402_6.3V6K~D
1
DDR_B_MA3
DDR_B_MA1
+1.35V
[9]
2
M_CLK_DDR2
M_CLK_DDR#2
[9]
DDR_B_BS0
[9]
[9]
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D44
DDR_B_D40
B
DDR_B_D42
DDR_B_D46
Layout Note:
Place near JDIMMB.203,204
DDR_B_D48
DDR_B_D52
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D51
DDR_B_D56
DDR_B_D57
+0.675VS
2
@
1
2
CD42
1U_0402_6.3V6K~D
2
1
CD41
1U_0402_6.3V6K~D
1
CD40
1U_0402_6.3V6K~D
2
CD39
1U_0402_6.3V6K~D
1
@
DDR_B_D62
DDR_B_D59
Layout Note:
Place near JDIMMB.199
+3VS
RD16 1
2 10K_0402_5%~D
RD15 1
2 10K_0402_5%~D
+3VS
+0.675VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
+3VS
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D14
DDR_B_D9
D
DDR3_DRAMRST#
DDR3_DRAMRST#
[14,8]
DDR_B_D12
DDR_B_D10
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB
[9]
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
C
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
All VREF traces should
have 10 mil trace width
M_CLK_DDR3 [9]
M_CLK_DDR#3 [9]
+V_DDR_REF
DDR_B_BS1 [9]
DDR_B_RAS# [9]
DDR_CS2_DIMMB#
M_ODT2 [9]
M_ODT3
[9]
[9]
DDR_B_D36
DDR_B_D37
1
DDR_B_D38
DDR_B_D39
2
DDR_B_D45
DDR_B_D41
CD38
0.1U_0402_16V7K~D
2
1
[9]
[9]
M_CLK_DDR2
M_CLK_DDR#2
CD35
10U_0603_6.3V6M~D
2
1
CD34
10U_0603_6.3V6M~D
2
1
CD33
10U_0603_6.3V6M~D
2
1
CD32
10U_0603_6.3V6M~D
1
CD31
10U_0603_6.3V6M~D
2
CD30
10U_0603_6.3V6M~D
1
+1.35V
JDIMM2
+V_DDR_REF
+V_DDR_REF
DDR_B_D0
DDR_B_D1
D
1
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D47
DDR_B_D43
DDR_B_D53
DDR_B_D49
DDR_B_D54
DDR_B_D50
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D58
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA [14,17,39,43,6]
PCH_SMBCLK [14,17,39,43,6]
+0.675VS
206
208
A
A
1
2
CD44
2.2U_0603_6.3V6K~D
2
CD43
0.1U_0402_16V7K~D
1
BELLW_80001-1021
CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
DDRIII DIMMB
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
15
of
62
5
4
3
2
1
RTC CRYSTAL
PCH_RTCX1
1
RH1
2 10M_0402_5% PCH_RTCX2
YH1
2
CH6
1U_0603_10V6K~D
+RTCVCC
2
RH4
1
2
CLRP2
SHORT PADS
2 20K_0402_5%~D
+RTCVCC
2 20K_0402_5%~D
PCH_RTCX2
B4
PCH_SRTCRST#
B9
SM_INTRUDER#
A8
PCH_RTCRST#
1
2 1M_0402_5%~D SM_INTRUDER#
CH5
1U_0603_10V6K~D
2
1
PCH Strap PIN
HDA_BIT_CLK
CLRP1
SHORT PADS
[47]
INTVRMEN Integrated 1.05V VRM Enable/Disable
HDA_SYNC
A22
HDA_SPKR
AL10
HDA_RST#
C24
HDA_SDIN0
HDA_SDIN0
B25
L22
K22
G22
+RTCVCC
F22
RH13
@ RH16
*
H
L
C
1
2 330K_0402_5%
1
2 330K_0402_5%
PCH_INTVRMEN
HDA_SDOUT
A24
B17
PCH_INTVRMEN
：
VRM enable
：Integrated
Integrated VRM disable
[18,37]
DP_PCH_HPD
DP_PCH_HPD
C22
RTCX2
SATA_TXN_0
SATA_TXP_0
SRTCRST#
SATA_RXN_1
SATA_RXP_1
INTRUDER#
INTVRMEN
SATA_TXN_1
SATA_TXP_1
RTCRST#
SATA_RXN_2
SATA_RXP_2
HDA_BCLK
SATA_TXN_2
SATA_TXP_2
HDA_SYNC
SPKR
SATA_RXN_3
SATA_RXP_3
HDA_RST#
HDA_SDI0
SATA_TXN_3
SATA_TXP_3
HDA_SDI1
SATA_RXN4/PERN1
SATA_RXP4/PERP1
HDA_SDI2
HDA_SDI3
SATA_TXN4/PETN1
SATA_TXP4/PETP1
HDA_SDO
SATA_RXN5/PERN2
SATA_RXP5/PERP2
DOCKEN#/GPIO33
HDA_DOCK_RST#/GPIO13
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
SPKR No Reboot
PCH_JTAG_TCK AB3
PCH_JTAG_TMS AD1
+3VS
2 1K_0402_5%~D
PCH_JTAG_TDO AD3
HDA_SPKR
F8
*LOW=Default
HIGH=No Reboot
C26
AB6
If the signal is sampled high, this indicate that
the system is strapped to the "No Reboot" mode
JTAG_TCK
SATA0GP/GPIO21
JTAG_TMS
SATA1GP/GPIO19
JTAG
PCH_JTAG_TDI AE2
@ RH17 1
SATA_RXN_0
SATA_RXP_0
AZALIA
[46]
HDA_SPKR
D9
REV = 5
RTCX1
JTAG_TDI
SATA_IREF
JTAG_TDO
TP9
TP25
TP8
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
SATA_PTX_DRX_N1 CH18 1
SATA_PTX_DRX_P1 CH17 1
2 0.01U_0402_16V7K~D
2 0.01U_0402_16V7K~D
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
[43]
[43]
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
[43]
[43]
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
[42]
[42]
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
AY13
AW13
BC12
BE12
AR13
AT13
BD13
BB13
AV15
AW15
SATA Impedance Compensation
BC14
BE14
CAD note:
Place the resistor within 500 mils of the PCH.
Avoid routing next to clock pins.
AP15
AR15
+1.5VS
RH21 1
2 7.5K_0402_1%~D
@ RH14 1
2 10K_0402_5%~D
AT1 PCH_GPIO21
RH12 1
2 10K_0402_5%~D
AU2 BBS_BIT0
RH29 1
2 10K_0402_5%~D
AY5 SATA_RCOMP
AP3 PCH_SATALED#
+3VS
C
+1.5VS
BD4
BA2
BB2
TP22
Boot BIOS Strap
TP20
1 OF 11
@ RH245
1
2 1K_0402_5%~D BBS_BIT0
@ RH244
1
2 1K_0402_5%~D
HDA_SYNC
Boot BIOS Strap
PT
*
This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
BBS_BIT[1]
HD Audio
[46]
HDA_SDO
Flash Descriptor Security Override/Intel ME Debug Mode
[46]
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
RH5
1
2 33_0402_5%~D
HDA_BIT_CLK
*
RH7
1
2 33_0402_5%~D
RH8
1
2 1M_0402_5%~D
HDA_SYNC
2 1K_0402_5%~D
BBS_BIT[0]
Boot BIOS Location
0
0
LPC
0
1
Reserved (NAND)
1
0
PCI
1
1
SPI
B
RTC Battery
+3V_PCH
HDA_SDOUT
+RTCBATT
= Disabled
*Low
High = Enabled
[46,47]
ME debug mode , this signal has a weak internal PD
1
HDA_RST#
HDA_SDOUT_AUDIO
[38]
HDA_SDO
RH15 1
2 33_0402_5%
HDA_SDOUT
RH11 1
2 1K_0402_5%~D
+3VLP
RTCR1
1K_0402_5%~D
1
[46]
for enable ME code programing
W=20mils
3
L=>security measures defined in the Flash
Descriptor will be in effect (default)
H=>Flash Descriptor Security will be overridden
2 33_0402_5%~D
RH6
HDA_RST_AUDIO#
2
@ RH23 1
[18]
GPIO19 => BBS_BIT0
GPIO51 => BBS_BIT1
+3V_PCH
B
BBS_BIT1
@
HDA_SYNC On-Die PLL Voltage Regulator Voltage Select
2 1K_0402_5%~D
SSD
[42]
[42]
BB9
BD9
LYNXPOINT_BGA695
@ RH32 1
D
HDD
W=20mils
2
1
1
2
RH2
B5
PCH_INTVRMEN G10
RH3
+RTCVCC
PCH_RTCX1
RTC
2
1
CH4
18P_0402_50V8J~D
1
1
CH3
18P_0402_50V8J~D
2
1
D
LPT_PCH_M_EDS
U7A
32.768KHZ_12.5PF_FC-135
SATA
1
RTCD1
BAT54CW_SOT323-3
Reserve for EMI
RH24
100_0402_1%~D
1
W=20mils 1
RH25
100_0402_1%~D
PCH_JTAG_TDI
PCH_JTAG_TCK
@ CH1
1
2 10P_0402_50V8J~D
HDA_BIT_CLK
@ CH2
1
2 10P_0402_50V8J~D
HDA_SDOUT
RH26
100_0402_1%~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
2
2
2
2
A
Reserve for RF please close to UH1
RH35
51_0402_5%
Security Classification
2011/08/25
Deciphered Date
2012/07/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
CH12
1U_0603_10V6K~D
1
PCH_JTAG_TMS
2
RH20
210_0402_1%~D
2
2
RH19
210_0402_1%~D
1
PCH_JTAG_TDO
1
2
RH18
210_0402_1%~D
1
A
+RTCVCC
+3V_PCH
1
+3V_PCH
1
+3V_PCH
1
JTAG
4
3
2
PCH (1/8) SATA,HDA
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
1
Sheet
16
of
62
5
4
3
2
1
LPT_PCH_M_EDS
U7C
XTAL25_IN
AA44
AA42
AF1
LANCLK_REQ#
AB43
D
AB45
AF3
PCH_GPIO20
[40]
[40]
[40]
MiniWLAN (Mini Card 1)--->
[40]
[40]
[40]
Card Reader --->
+3V_PCH
RPH24
4
3
2
1
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
MINI3CLK_REQ#
MINI3CLK_REQ#
AD43
AD45
T3
CDCLK_REQ#
AF43
AF45
V3
CLK_PCIE_CD#
CLK_PCIE_CD
CDCLK_REQ#
AE44
AE42
PCH_GPIO44 AA2
PT
5
6
7
8
NFC_RST#
PCIECLKREQ0#
PCH_GPIO44
NFC_DET#
[49]
10K_0804_8P4R_5%
+3VS
+3V_PCH
RPH25
4
5
CDCLK_REQ#
3
6
MINI3CLK_REQ#
2
7
PCH_GPIO20
1
8
LANCLK_REQ#
AJ44
AJ42
[49]
[6]
10K_0804_8P4R_5%
[6]
[38]
[42]
NFC_RST#
NFC_RST#
AB40
AB39
AE4
CLK_PCI_LPC
CLK_PCI_DEBUG
Y3
NFC_DET#
NFC_DET#
AH43
CLK_CPU_ITP#
AH45
CLK_CPU_ITP
CLK_PCI_LPBACK
RH144
1
2 22_0402_5%
CLK_PCI0
D44
CLK_PCI_LPC
RH145
1
2 22_0402_5%
CLK_PCI1
E44
CLK_PCI_DEBUG
RH146
1
2 22_0402_5%
CLK_PCI2
B42
C
F41
A40
CLKOUT_PEG_A
CLKOUT_PCIE_P_0
CLKOUT_PEG_A_P
PCIECLKRQ0#/GPIO73
PEGA_CLKRQ#/GPIO47
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PCIECLKRQ1#/GPIO18
PEGB_CLKRQ#/GPIO56
CLKOUT_PCIE_N_2
CLKOUT_DMI
CLKOUT_PCIE_P_2
CLKOUT_DMI_P
PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26
CLKIN_DMI
CLKIN_DMI_P
CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45
CLKIN_SATA
CLKIN_SATA_P
CLKOUT_PCIE_N_7
REFCLK14IN
CLKIN_33MHZLOOPBACK
CLKOUT_PCIE_P_7
PCIECLKRQ7#/GPIO46
XTAL25_IN
XTAL25_OUT
CLKOUT_ITPXDP
CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P
CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0
CLKOUTFLEX2/GPIO66
CLKOUT_33MHZ1
CLKOUTFLEX3/GPIO67
CLKOUT_33MHZ2
ICLK_IREF
CLKOUT_33MHZ3
TP19
TP18
CLKOUT_33MHZ4
2 OF 11
DIFFCLK_BIASREF
CLK_PEG_VGA#
AB36
CLK_PEG_VGA
CLK_PEG_VGA
AF6
PEG_A_CLKRQ#
PEG_A_CLKRQ#
CLK_PEG_VGA#
Y39
RH64 1
YH2
4
[24]
NC
1
[24]
2 10K_0402_5%~D
OSC
OSC
NC
25MHZ_10PF_X3G025000DA1H~D
+3V_PCH
PT
U4
PEG_B_CLKREQ#
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
AJ39
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
AF35
AF36
DPLL_REF_CLK#
DPLL_REF_CLK
AY24
AW24
CLKIN_DMI#
CLKIN_DMI
AR24
AT24
CLK_BUF_BCLK#
CLK_BUF_BCLK
H33
G33
CLKIN_DOT96#
CLKIN_DOT96
BE6
BC6
CLKIN_SATA#
CLKIN_SATA
F45
D17
CLK_PCH_14M
CLK_PCI_LPBACK
AL44
AM43
XTAL25_IN
XTAL25_OUT
PEG_B_CLKREQ#
CLK_CPU_DMI#
CLK_CPU_DMI
1
[19]
[8]
2
1
CH27
12P_0402_50V8J
2
2 10P_0402_50V8J~D
CLK_PCI_LPC
@ CH26 1
2 10P_0402_50V8J~D
CLK_PCI_DEBUG
DPLL_REF_CLK#
DPLL_REF_CLK
[8]
[8]
D
PT
RPH27
4
3
2
1
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLKIN_DMI#
CLKIN_DMI
[8]
[8]
5
6
7
8
10K_0804_8P4R_5%
RH66
RH67
RH68
RH69
CLK_PCH_14M
RH62
1
1
1
1
2
2
2
2
1
2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
CLOCK TERMINATION for FCIM and need
close to PCH
+3V_PCH
C40 CLK_PCI_TPM_R
F38
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
RH97 1
RH98 1
2 22_0402_1% CLK_PCI_TPM
2 100K_0402_5%~D
+3VS
KB_DET#
KB_DET#
CLK_PCI_TPM
[39]
F36
F39
+1.5VS
PT
[40]
@ CH13
10P_0402_50V8J~D
Reserve for EMI
AM45
AD39
AD38
SMBCLK
RH448
1
2 2.2K_0402_5%~D
SMBDATA
RH456
1
2 2.2K_0402_5%~D
NFC_IRQ
@ RH65 1
2 10K_0402_5%~D
CCD_INT
RH63 1
2 10K_0402_5%~D
1
DRAMRST_CNTRL_PCH
RH53
+1.5VS
C
2 1K_0402_5%~D
RPH14
AN44
PCH_CLK_BIASREF
RH28 1
2 7.5K_0402_1%~D
1
2
3
4
SML1CLK
SML1DATA
PCH_SMBCLK
PCH_SMBDATA
+3VS
8
7
6
5
+3V_PCH
2.2K_8P4R_5%
@
SML0CLK
+3VS
SML0DATA
LPT_PCH_M_EDS
U7D
CH28
12P_0402_50V8J
[8]
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
LYNXPOINT_BGA695
@ CH14 1
3
2
Y38
CLOCK SIGNAL
Reserve for EMI
2 1M_0402_5%~D
[24]
1
AB1
PCIECLKREQ0#
CLKOUT_PCIE_N_0
AB35
2
Y45
RH89 1
XTAL25_OUT
REV = 5
Y43
PT
RH724
1
RH725
1
2 499_0402_1%
N14@
2 499_0402_1%
N14@
REV = 5
LPC_AD1
[38,40,42]
LPC_AD2
[38,40,42]
[38,40,42]
LPC_AD3
LPC_FRAME#
A20
LPC_AD1
C20
LPC_AD2
LPC_AD3
LPC_FRAME#
A18
C18
B21
D21
+3VS
[38,40]
RH75 1
SERIRQ
G20
2 10K_0402_5%~D
AL11
SERIRQ
SMBALERT#/GPIO11
LAD_0
SMBus
SMBCLK
LAD_1
LAD_2
SMBDATA
LPC
[38,40,42]
LPC_AD0
SML0ALERT#/GPIO60
LAD_3
SML0CLK
LFRAME#
SML0DATA
LDRQ0#
SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23
SML1CLK/GPIO58
SERIRQ
SML1DATA/GPIO75
B
T7
AJ11
PCH_SPI_CS#
AJ7
PCH_SPI_CS1#
@
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_WP#
AL7
AJ10
RPH5
1
2
3
4
8
7
6
5
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_WP#_R
15_0804_8P4R_5%
RH41 1
PCH_SPI_HOLD#
2 15_0402_1%
PCH_SPI_SI_R
AH1
PCH_SPI_SO_R
AH3
PCH_SPI_WP#_R
AJ4
PCH_SPI_HOLD#_R
AJ2
SPI_CLK
CL_CLK
SPI
PAD~D
PCH_SPI_CLK_R
CL_DATA
C-Link
SPI_CS0#
CL_RST#
N7
CCD_INT
R10
SMBCLK
U11
SMBDATA
N8
DRAMRST_CNTRL_PCH
SMBCLK
U8
SML0CLK
R7
SML0DATA
QH2A
DMN66D0LDW-7_SOT363-6~D
3
SMBDATA
H6
NFC_IRQ
K6
SML1CLK
N11
SML1DATA
SML0CLK
[49]
SML0DATA
NFC_IRQ
PCH to NFC
[49]
6
PCH to DDR, XDP, TP, FFS, AMP
1
PCH_SMBCLK
[14,15,39,43,6]
5
LPC_AD0
2
[38,40,42]
4
PCH_SMBDATA
[14,15,39,43,6]
QH2B
DMN66D0LDW-7_SOT363-6~D
[49]
B
AF11
No support iAMT
AF10
AF7
SPI_CS1#
SPI_CS2#
TP1
SPI_MOSI
TP2
Thermal
SPI_MISO
TP4
SPI_IO2
TP3
SPI_IO3
BC45
BE43
BE44
AY43
PCH_TD_IREF
1
TD_IREF
BA45
RH322
8.2K_0402_1%
3 OF 11
LYNXPOINT_BGA695
2
SPI ROM FOR ME ( 8MByte )
+3VS
@
A
2 3.3K_0402_5%
PCH_SPI_CS#
RH38 1
2 1K_0402_5%~D
PCH_SPI_WP#
RH40 1
2 1K_0402_5%~D
PCH_SPI_HOLD#
SML1CLK
1
QH3A
DMN66D0LDW-7_SOT363-6~D
3
SML1DATA
1
2
6
CH11
0.1U_0402_16V7K~D
PCH_SMLCLK
[25,35,38,40]
5
+3V_PCH
@ RH33 1
PCH to EC
2
+3V_PCH
4
PCH_SMLDATA
[25,35,38,40]
A
QH3B
DMN66D0LDW-7_SOT363-6~D
UH2
PCH_SPI_CS#
PCH_SPI_SO
PCH_SPI_WP#
1
2
3
4
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
W25Q64FVQ_SO8
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (2/8) SMBUS, CLK, SPI, LPC
Document Number
Rev
0.1
LA-9941P
Tuesday, September 17, 2013
1
Sheet
17
of
62
5
4
3
2
1
+3VS
[7]
[7]
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
AP17
AV20
[7]
[7]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
AY22
AP20
[7]
[7]
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AR17
AW20
[7]
[7]
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
BD21
BE20
[7]
[7]
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
[7]
[7]
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
BD17
BE18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
BB21
BC20
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
BB17
BC18
BE16
+1.5VS
AW17
+1.5VS
AV17
RH99 1
2 7.5K_0402_1%~D
For deep S3, connector to EC
[38]
[6,8]
@PAD~D
DMI_RCOMP AY17
R6
AM1
XDP_DBRESET#
AD7
SYS_PWROK
F10
AB7
@PAD~D
T175
PM_DRAM_PWRGD
[38]
@PAD~D
PCH_RSMRST#
@PAD~D
PCH_RSMRST#
For deep S3
[38]
H3
PM_DRAM_PWRGD
T177
J2
T178
J4
PCH_SUSWARN#
[38,6]
[38]
K1
PBTN_OUT#
@PAD~D
T81
AC_PRESENT
@PAD~D
T171
PBTN_OUT#
AC_PRESENT
E6
K7
PCH_GPIO72
C
N4
RI#
AB10
@PAD~D
FDI_RXN_1
DMI_RXP_0
DMI_RXP_1
FDI_RXP_0
FDI
FDI_RXP_1
DMI
TP16
DMI_TXN_0
DMI_TXN_1
TP5
TP15
DMI_TXN_2
DMI_TXN_3
TP10
DMI_TXP_0
DMI_TXP_1
FDI_CSYNC
FDI_INT
DMI_TXP_2
DMI_TXP_3
FDI_IREF
DMI_IREF
TP17
TP12
TP13
TP7
FDI_RCOMP
AJ36
AY45
AV45
M43
PT
N42
N44
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#
U40
U39
8.2K_0804_8P4R_5%
AL39
FDI_CSYNC
FDI_CSYNC
[7]
[35]
AL40
FDI_INT
eDP_PWM
[7]
[35,38]
AT45
[35]
AU42
D2
SLP_WLAN#
T170
5
6
7
8
N36
eDP_PWM
ENBKL
eDP_LVDDEN
ENBKL
K36
eDP_LVDDEN
G36
AU44
PCI_PIRQA#
AR44
PCI_PIRQB#
L20
PCI_PIRQC#
K17
PCI_PIRQD#
M20
DMI_RCOMP
SUSACK#
SYS_RESET#
DSWVRMEN
System Power
Management
DPWROK
SYS_PWROK
WAKE#
PWROK
CLKRUN#
APWROK
SUS_STAT#/GPIO61
DRAMPWROK
SUSCLK/GPIO62
RSMRST#
SLP_S5#/GPIO63
SUSWARN#/SUSPWRNACK/GPIO30
SLP_S4#
PWRBTN#
SLP_S3#
ACPRESENT/GPIO31
SLP_A#
BATLOW#/GPIO72
SLP_SUS#
RI#
PMSYNCH
TP21
SLP_LAN#
C8
DSWODVREN
H20
K3
POK
U7
PM_CLKRUN#
PT
T46
T39
PAD~D
PAD~D
@
@
T41
PAD~D
@
Y7
PM_SLP_S5#
C6
PM_SLP_S4#
H1
PM_SLP_S3#
T42
PAD~D
@
T44
PAD~D
@
F3
PM_SLP_A#
SUSCLK_R
[16]
[38,40]
[40]
PM_SLP_S5#
[38]
PM_SLP_S4#
[38,55]
PM_SLP_S3#
[34,38,40,43,55,56]
T37
T40
PAD~D
PAD~D
@
@
T38
PAD~D
@
PAD~D
T8
WL_OFF#
DGPU_PWR_EN#
C12
BBS_BIT1
C10
EN_CAM
A10
WL_OFF#
AL6
DDPB_CTRLCLK
VGA_GREEN
DDPB_CTRLDATA
VGA_RED
DDPC_CTRLCLK
VGA_DDC_CLK
DDPC_CTRLDATA
VGA_DDC_DATA
DDPD_CTRLCLK
VGA_HSYNC
DDPD_CTRLDATA
VGA_VSYNC
DDPB_AUXN
DAC_IREF
DDPC_AUXN
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
EDP_VDDEN
DDPD_AUXP
DDPB_HPD
PIRQA#
DDPC_HPD
PIRQB#
DDPD_HPD
R40
HDMI_DDB_CTRLCLK
R39
HDMI_DDB_CTRLDATA
R35
mDP_DDC_CTRLCLK
R36
mDP_DDC_CTRLDATA
N40
HDMI_DDB_CTRLCLK
[36]
HDMI_DDB_CTRLDATA
[36]
mDP_DDC_CTRLCLK
[37]
mDP_DDC_CTRLDATA
PT
[37]
N38
H45
K43
PT
mDP_AUXN_PCH
mDP_AUXN_PCH
[37]
D
J42
H43
K45
mDP_AUXP_PCH
mDP_AUXP_PCH
[37]
J44
K40
HDMI_PCH_HPD
K38
DP_PCH_HPD
HDMI_PCH_HPD
DP_PCH_HPD
[36]
[16,37]
PT
H39
PIRQC#
PIRQD#
PCI
PIRQE#/GPIO2
GPIO50
PIRQF#/GPIO3
GPIO52
PIRQG#/GPIO4
GPIO54
PIRQH#/GPIO5
GPIO51
PME#
GPIO53
PLTRST#
G17
FFS_INT1
F17
ODD_DA#
L15
CAB_DET_SINK
M15
PCH_GPIO5
AD10
Y11
FFS_INT1
T6
[43]
CAB_DET_SINK
PAD~D
[37]
@
PCH_PLTRST#
GPIO55
5 OF 11
@
+3VS
For deep S3
PM_SLP_SUS#
AY3 H_PM_SYNC
H_PM_SYNC
SLP_LAN#
BBS_BIT1
REV = 5
VGA_BLUE
LYNXPOINT_BGA695
F1
G5
[40]
@
Y6
B13
PCH_GPIO52
[52,54]
WAKE#
AN7 PM_CLKRUN#
A12
DGPU_HOLD_RST#
For deep S3
L13
PT
RPH16
[34,38]
[8]
HDMI_DDB_CTRLCLK
HDMI_DDB_CTRLDATA
mDP_DDC_CTRLCLK
mDP_DDC_CTRLDATA
RH138
1
2 100K_0402_5%~D
ENBKL
RH132
1
2 100K_0402_5%~D
eDP_LVDDEN
1
2
3
4
8
7
6
5
C
2.2K_8P4R_5%
SLP_WLAN#/GPIO29
PCH Strap PIN
+3VS
RH136
1
2 8.2K_0402_5%~D
@ RH120
1
2 10K_0402_5%~D
GNT3# A16 Top-Block Swap Override
(Internal PU 20K)
PM_CLKRUN#
RPH4
4
3
2
1
M45
AW44
+3VALW
+3V_PCH
V45
PCH_GPIO52
ODD_DA#
DGPU_HOLD_RST#
WL_OFF#
8.2K_0804_8P4R_5%
+3VS
RPH1
8
1
7
2
6
3
5
4
@
+3VALW
1
2
3
4
AL36
AV43
LYNXPOINT_BGA695
+3V_PCH
T45
U44
RPH2
8
7
6
5
AL35
4 OF 11
PT
PCH_GPIO5
DGPU_PWR_EN#
T176
SUSACK#
XDP_DBRESET#
PCH_PWROK_EC
[8]
DMI_RXN_2
DMI_RXN_3
2 8.2K_0402_5%~D
2 8.2K_0402_5%~D
+3VS
AJ35
LVDS
[7]
[7]
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
FDI_RXN_0
DMI_RXP_2
DMI_RXP_3
1
1
RH167
@ RH164
REV = 5
DMI_RXN_0
DMI_RXN_1
LPT_PCH_M_EV
U7E
CRT
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
[7]
[7]
D
AW22
AR20
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
LPT_PCH_M_EDS
DISPLAY
U7B
*
PCH_GPIO72
RI#
WAKE#
PCH_SUSWARN#
@ RH243
H
L
：：Enable
Default
1
2
1K_0402_5%~D
WL_OFF#
10K_0804_8P4R_5%
RH130
1
2 10K_0402_5%~D
SYS_PWROK
@ RH193
1
2 10K_0402_5%~D PCH_PWROK_EC
+3VS
[38]
[38,58,6]
For deep S3
RH121
1
2 10K_0402_5%~D
IMVP_VR_PG
PCH_PWROK_EC
IMVP_VR_PG
1
2
IN1
IN2
3
+3VALW
PCH_PWROK_EC
AC_PRESENT
UH3
OUT
4
SYS_PWROK
PT
+3VS
MC74VHC1G08DFT2G_SC70-5
2
PCH_RSMRST#
5
2 10K_0402_5%~D
VCC
1
GND
RH127
@ RH247
10K_0402_5%~D
+3VS_DELAY
1
H
L
P
3
1
1 330K_0402_5%
P
[24]
4
PLTRST_VGA#
UH4
1
PCH_PLTRST#
IN1
O
3
G
IN2
2
DGPU_HOLD_RST#
SN74AHC1G08DCKR_SC70-5
PCH_PLTRST#
@ RH416 1
2 0_0402_5%
2
ST
SN74AHC1G08DCKR_SC70-5
RH155
100K_0402_5%~D
：Disable
Enable
：
2
*
2
UH5
1
IN1
O
IN2
1 330K_0402_5%
S
2
DGPU_PWR_EN#
G
@ QH6
2N7002_SOT23-3
2
5
@ RH122
2
4
PLT_RST#
D
RH154
100K_0402_5%~D
G
[38,40,42,6,8]
RH119
2
+3VS
+RTCVCC
1
1
@ CH99
0.01U_0402_16V7K~D
DSWVRMEN
Deep S4/S5 Well On-Die Voltage Regulator Enable
DSWODVREN
B
DGPU_PWR_EN
1
[24,33,59]
5
PCH Strap PIN
3
B
If strap is sampled high, the Integrated Deep S4/S5 Well
(DSW) On-Die VR mode is enabled
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (3/8) DMI,FDI,PM,GFX,DP
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
1
Sheet
18
of
62
4
3
AW31
AY31
BE32
BC32
AT31
AR31
BD33
BB33
MiniWLAN (Mini Card 1)--->
CARD_READER --->
[40]
[40]
PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
[40]
[40]
PCIE_PTX_WLANRX_N3
PCIE_PTX_WLANRX_P3
[40]
[40]
PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
[40]
[40]
PCIE_PTX_CARDRX_N4
PCIE_PTX_CARDRX_P4
PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
CH19 1
CH20 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_PTX_WLANRX_N3_C BE34
PCIE_PTX_WLANRX_P3_C BC34
PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
CH21 1
CH22 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
AW33
AY33
AT33
AR33
PCIE_PTX_CARDRX_N4_C BE36
PCIE_PTX_CARDRX_P4_C BC36
BD37
BB37
AY38
AW38
C
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
+1.5VS
BE30
BC30
BB29
+1.5VS
RH1131
2 7.5K_0402_1%~D PCIE_RCOMP BD29
REV = 5
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PCIe
AW36
AV36
1
LPT_PCH_M_EDS
U7I
D
2
PERN_5
PERP_5
USB
5
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
PETN_5
PETP_5
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
USBRBIAS#
USBRBIAS
PCIE_IREF
TP24
TP23
TP11
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
TP6
PCIE_RCOMP
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N9
USB20_P9
USB20_N12
USB20_P12
[44]
[44]
[44]
[44]
[40]
[40]
[40]
[40]
[40]
[40]
USB20_N9
USB20_P9
[35]
[35]
USB20_N12
USB20_P12
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN3
USB3RP3
USB3TN3
USB3TP3
USB3RN4
USB3RP4
USB3TN4
USB3TP4
USBRBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN3
USB3RP3
USB3TN3
USB3TP3
USB3RN4
USB3RP4
USB3TN4
USB3TP4
RH143
1
[40]
[40]
[45]
[45]
[45]
[45]
[45]
[45]
[45]
[45]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
D
USB Conn 1 (Power share)
USB Conn 3 (Power share)
USB Conn 2 (Power share)
USB Conn 4 (Power share)
Mini Card(WLAN)
Touch Screen
Camera
C
USB Conn 1 (Power share)
USB Conn 3 (Power share)
USB Conn 2 (Power share)
2 22.6_0402_1%
USBRBIAS
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0#
USB_OC1#
[44]
[40]
PT +3V_PCH
RPH29
4
3
2
1
USB_OC4#
USB_OC7#
USB_OC6#
USB_OC0#
5
6
7
8
10K_0804_8P4R_5%
9 OF 11
LYNXPOINT_BGA695
B
B
+3V_PCH
@
RPH30
[17]
PEG_B_CLKREQ#
USB_OC3#
USB_OC2#
USB_OC5#
PEG_B_CLKREQ#
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
+3V_PCH
USB_OC1#
RH84 1
2 10K_0402_5%~D
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (4/8) PCI, USB
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
19
of
62
5
4
3
2
1
+VCCP
LPT_PCH_M_EDS
U7F
PT
+3V_PCH
+3VALW
RPH7
+3V_PCH
4
3
2
1
5
6
7
8
EC_SMI#
PCH_GPIO12
HDD_DETECT#
PCH_GPIO24
PCH_GPIO0
AT8
PCH_GPIO1
F13
PCH_GPIO6
[38]
EC_RUNTIME_SCI#
EC_RUNTIME_SCI#
10K_0804_8P4R_5%
[38]
D
PT
RPH8
4
3
2
1
5
6
7
8
PCH_GPIO0
DGPU_PWROK
PCH_GPIO6
PCIE_MCARD1_DET#
[33,59]
[38]
4
3
2
1
5
6
7
8
EC_RUNTIME_SCI#
ODD_EN#
LCD_DBC
LCD_DCR
[40]
WAKE_PCH#
LCD_DBC
1
1
1
2 8.2K_0402_5%~D
BT_RADIO_DIS#
2 200K_0402_5%
ODD_DETECT#
2 10K_0402_5%~D USB_MCARD1_DET#
@ RH178
1
2 1K_0402_5%~D
LCD_DBC
PT
for ST test
+3V_PCH
[35]
LCD_DCR
[43]
FFS_INT2
AN2
PCH_GPIO24
Y10
WAKE_PCH#
R11
PCH_GPIO28
AD11
AP1
LCD_DBC
+3VS
RH174
RH171
RH177
AB11
PCH_GPIO16
BT_RADIO_DIS# AN6
BT_RADIO_DIS#
[35]
10K_0804_8P4R_5%
PCH_GPIO15
ODD_DETECT# BB4
+3VS
RPH9
K13
DGPU_PWROK C14
DGPU_PWROK
For deep S3,
PCH_GPIO27 connect from EC PCH_WAKE#
10K_0804_8P4R_5%
Y1
EC_SMI#
EC_SMI#
PCH_GPIO12
+3VS
A14
G15
PCH_GPIO36
AT3
PCH_GPIO37
AK1
PCIE_MCARD1_DET#
AT7
LCD_DCR
AM3
FFS_INT2
AN4
PCH_GPIO49
AK3
C
@ RH158
1
2 1K_0402_5%~D PCH_GPIO15
PT
[43]
HDD_DETECT# U12
HDD_DETECT#
[39]
KB_BL_DET
C16
KB_BL_DET
D13
PCH_GPIO70
G13
USB_MCARD1_DET# H15
PCH Strap PIN
BE41
BE5
C45
A5
GPIO37 TLS Confidentiality
*
ODD_EN#
Low - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality
@ RU45 1
REV = 5
BMBUSY#/GPIO0
2 1K_0402_1%~D
H_THERMTRIP#_C
TACH1/GPIO1
TACH2/GPIO6
CPU/Misc
TACH3/GPIO7
+3VS
GPIO8
RH159
LAN_PHY_PWR_CTRL/GPIO12
TP14
GPIO15
PECI
SATA4GP/GPIO16
RCIN#
GPIO
TACH0/GPIO17
PROCPWRGD
SCLOCK/GPIO22
THRMTRIP#
GPIO24
PLTRST_PROC#
GPIO27
VSS
AN10
1
D
2 10K_0402_5%~D
GATEA20
GATEA20
[38]
+3VS
AY1
AT6
KB_RST#
AV3
H_CPUPWRGD
AV1
H_THERMTRIP#_C
AU4
CPU_PLTRST#
KB_RST#
[38]
H_CPUPWRGD
RH162
1
KB_RST#
2 10K_0402_5%~D
[6,8]
2 390_0402_5%
CPU_PLTRST#
RH175
1
H_THERMTRIP#
[8]
[8]
N10
GPIO28
GPIO34
GPIO35/NMI#
SATA2GP/GPIO36
SATA3GP/GPIO37
SLOAD/GPIO38
SDATAOUT0/GPIO39
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
VSS
VSS
VSS
VSS
NCTF
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
C
6 OF 11
LYNXPOINT_BGA695
@
B
1
2 10K_0402_5%~D
PCH_GPIO37
GPIO28 On-Die PLL Voltage Regulator
+3VS
This signal has a weak internal pull up
H
L
：：On-Die
voltage regulator enable
On-Die PLL Voltage Regulator disable
@ RH165
1
2 1K_0402_5%~D
+3VS
1
2 10K_0402_5%~D
1
2 10K_0402_5%~D
PCH_GPIO49
B
RH176
1
2 10K_0402_5%~D
@ RH191
1
2 10K_0402_5%~D
+3VS
+3VS
PCH_GPIO16
N14@ RH168
10K_0402_5%~D
PCH_GPIO28
2
*
RH180
@ RH188
1
RH169
PCH_GPIO1
USB X4,PCIEX8,SATAX6
11
USB X6,PCIEX8,SATAX4
01
2 10K_0402_5%~D
PCH_GPIO70
PCH_GPIO70
PCH_GPIO1
N14P
N15@ RH172
10K_0402_5%~D
1
1 = N14P-GT
0 = N15P
DIS
1
UMA
0
2
*
SATA2GP/GPIO36 Reserved
GPIO16,GPIO49
1
config
RH163
DGPU Board ID Optional
When Unused as GPIO or SATA*GP Use 8.2K-10K pull-down to ground
@ RH194
1
2 10K_0402_5%~D
PCH_GPIO36
A
A
+3VALW
RH173
1
2 10K_0402_5%~D
@ RH170
1
2 10K_0402_5%~D
WAKE_PCH#
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (5/8) GPIO, CPU, MISC
Document Number
Rev
0.1
LA-9941P
Sheet
Tuesday, September 03, 2013
1
20
of
62
5
4
3
2
1
D
D
U7G
LPT_PCH_M_EDS
+VCCP
JP2
@
2
1
1
2
CH38
1U_0402_6.3V6K~D
2
CH37
1U_0402_6.3V6K~D
2
1
2
1
2
CH70
1U_0402_6.3V6K~D
2
1
CH69
1U_0402_6.3V6K~D
1
PAD-OPEN 43x39
U14
AA18
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
M31
VCCADACBG3_3
+VCCAFDI_VRM
BB44
VCCVRM
FDI
VCCIO
Y12
DCPSUS1
AJ30
AJ32
1
+3VS
1
+1.05VM_VCCSUS1
AK18
VCCIO
AN11
VCCVRM
SATA
+VCCP
VCCIO
2
1
2
@ CH66
10U_0805_10V6M~D
@ CH67
10U_0805_10V6M~D
@ CH68
10U_0805_10V6M~D
+VCCP
3.629A
@ JP5
2
2
1
2
CH75
10U_0603_6.3V6M~D
2
1
CH76
1U_0402_6.3V6K~D
2
1
CH78
1U_0402_6.3V6K~D
2
+PCH_VCCDSW
5.11_0402_1%~D
1
CH72
1U_0402_6.3V6K~D
+PCH_VCCDSW_R
+VCCAFDI_VRM
+VCCP
CH95
1U_0402_6.3V6K~D
2
C
2
1
+VCCAFDI_VRM
1
CH56
1U_0402_6.3V6K~D
1
B
1
+VCCAFDI_VRM
+VCCAFDI_VRM
AM18
AM20
AM22
AP22
AR22
AT22
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
@
RH37
2
+VCCAFDI_VRM
AK22
7 OF 11
2
CH33
0.1U_0402_10V7K~D
2
+PCH_USB_DCPSUS3
LYNXPOINT_BGA695
1
2
+3V_PCH
BE22
VCCVRM
VCCMPHY
+1.5VS
@ CH60
10U_0805_10V6M~D
+VCCAFDI_VRM
AJ26
AJ28
AK20
AK26
AK28
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
PCIe/DMI
+VCCP
R30
R32
VCCSUS3_3
VCCSUS3_3
ST
2 0_0805_5%
1
AN35
VCC3_3_R30
VCC3_3_R32
HVCMOS
0.179A
@ R56 1
+VCCAFDI_VRM
AN34
VCCIO
USB3
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
P43
VSS
CH46
1U_0402_6.3V6K~D
+PCH_VCCDSW
1
P45
VCCADAC1_5
CRT DAC
Core
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
+1.05VM_VCCASW
CH65
22U_0805_6.3V6M~D
C
@
1
CH36
1U_0402_6.3V6K~D
JP19
CH35
10U_0805_10V6M~D
1
2
2
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
Y26
+1.05VS_VCCCORE
PAD-OPEN 43x39
+VCCP
REV = 5
1.29A
2
1
1
JUMP_43X118
0.098A
+1.05VM_VCCSUS1
0_0603_5%~D
1
1
2 @ RH220
+VCCP
B
@ CH94
1U_0402_6.3V6K~D
2
0.476A
1
+PCH_USB_DCPSUS3
1
2
@ CH62
1U_0402_6.3V6K~D
2
@ CH63
10U_0603_6.3V6M~D
1
0_0603_5%~D
2
@ RH201
+VCCP
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (6/8) PWR
Size
Date:
5
4
3
2
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
1
Sheet
21
of
62
5
4
3
2
1
+3V_PCH
For deep S3
U7H
+3V_PCH
JP6
D
@
2
1
2
+VCCP
1
R24
R26
R28
U26
M24
1
+3VS
U35
L24
1
2
+VCCP
CH100
0.1U_0402_10V7K~D
JP7
U30
V28
V30
Y30
@
PAD-OPEN 43x39
1
2
1
+1.05VM_VCCSUS2 Y35
+VCCAFDI_VRM
CH82
1U_0402_6.3V6K~D
2
1
2
AF34
AP45
+PCH_VCC
CH81
10U_0805_10V6M~D
Y32
+PCH_VCCCLK
M29
+PCH_VCCCLK3_3
L29
0.055A
L26
M26
AD34
+PCH_VCCCLK
AA30
AA32
0.306A
C
AD35
AG30
AG32
AD36
AE30
AE32
2
R20
R22
CH64
0.1U_0603_25V7K~D
+3VALW
1
VCCDSW3_3
VSS
DCPSST
VCCUSBPLL
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
D
CH55
0.1U_0402_10V7K~D
2
GPIO/LPC
A16
AA14
+VCCSST
CH85 1
+3VS
2 0.1U_0402_10V7K~D
AE14
AF12
AG14
0.01A
U36
+VCCP
+3V_PCH
1
+3VALW
Azalia
DCPSUS2
VCCSUSHDA
A26
1
VCCVRM
VCC
VCCSUS3_3
VCCCLK
VCCRTC
RTC
VCCCLK3_3
DCPRTC
DCPRTC
+RTCVCC
K8
2
VCCCLK3_3
VCCCLK3_3
V_PROC_IO
V_PROC_IO
CPU
VCCCLK3_3
VCCCLK3_3
VCCSPI
SPI
VCCCLK
VCC
VCC
VCCCLK
VCCCLK
VCCASW
Fuse
VCCCLK
VCCASW
VCCCLK
VCCCLK
VCCVRM
VCCCLK
VCC3_3
Thermal
VCCCLK
VCCCLK
VCC3_3
P14
P16
+VCCRTCEXT
1
1
0.004A
AJ12
AJ14
+PCH_VPROC
AD12
+3V_VCCPSPI
P18
P20
+PCH_VCCCFUSE
@
JP18
2
CH79
0.1U_0402_10V7K~D
2
+PCH_VCCASW
R18
0.67A
2
1
CH93
0.1U_0402_10V7K~D
2
CH71
1U_0402_6.3V6K~D
1
CH92
1U_0402_6.3V6K~D
2
JP17
1
+3V_PCH
+VCCP
2
CH54
1U_0402_6.3V6K~D
C
PAD-OPEN 43x39
+1.5VS
+3VS
0.133A
AK32
1
LYNXPOINT_BGA695
2
CH98
0.1U_0402_10V7K~D
@
ST
+VCCIO2PCH
0.028A
@ R53 1
+PCH_VPROC
+VCCP
1
2 0_0603_5%~D
+1.05VM_VCCSUS2
1
1
@ CH86
2
1U_0402_6.3V6K~D
2
CH73
0.1U_0402_10V7K~D
2
PAD-OPEN
43x39
1
AW40
AK30
CH91
0.1U_0402_10V7K~D
2
@
L17
1
CH90
0.1U_0402_10V7K~D
0.022A2
8 OF 11
@ RH219
1
A6
VCCCLK3_3
ICC
U32
V32
VCCSUS3_3
VCCSUS3_3
USB
2
CH84
0.1U_0402_10V7K~D
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
0.015A
1
REV = 5
0.261A
PAD-OPEN 43x39
CH61
0.1U_0402_10V7K~D
LPT_PCH_M_EDS
1
CH88
0.1U_0402_10V7K~D
2
2 0_0805_5%
1
CH89
0.1U_0402_10V7K~D
2
CH87
4.7U_0603_6.3V6K~D
ST
+VCCP
@ R54 1
+PCH_VCCCFUSE
LH100
1
2
4.7UH_LQM18FN4R7M00D_20%~D
+PCH_VCC
2
1
2
CH101
1U_0402_6.3V6K~D
B
CH102
10U_0603_6.3V6M~D
1
1
@ R55 1
CH77
1U_0402_6.3V6K~D
2 0_0805_5%
+3VS
2 0_0805_5%~D
+VCCP
2
B
Place near pin AP45
+VCCP
@ RH202 1
+PCH_VCCCLK
2 0_0805_5%
Place near pin AD34
2
1
2
1
2
CH30
15P_0402_50V8J~D
2
1
CH111
1U_0402_6.3V6K~D
2
1
CH106
1U_0402_6.3V6K~D
Place near pin Y32,AA30,AA32
1
CH110
1U_0402_6.3V6K~D
2
CH103
1U_0402_6.3V6K~D
1
CH105
1U_0402_6.3V6K~D
ST
Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3VS
@ RH213 1
+PCH_VCCCLK3_3
2 0_0805_5%
Place near pin L29
1
2
1
2
Place near pin L26,M26
CH109
1U_0402_6.3V6K~D
2
CH107
1U_0402_6.3V6K~D
Place near pin M29
1
CH108
1U_0402_6.3V6K~D
2
CH104
1U_0402_6.3V6K~D
1
1
2
CH24
15P_0402_50V8J~D
ST
A
A
Place near pin U32,V32
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (7/8) PWR
Size
Date:
5
4
3
2
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
1
Sheet
22
of
62
5
4
3
2
1
D
D
U7J
AL34
AL38
AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36
AN40
AN42
AN8
AP13
AP24
AP31
AP43
AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
D42
AV13
AV22
AV24
AV31
AV33
BB25
AV40
AV6
AW2
F43
AY10
AY15
AY20
AY26
AY29
AY7
B11
B15
C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U7K
LPT_PCH_M_EDS
REV = 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA16
AA20
AA22
AA28
AA4
AB12
AB34
AB38
AB8
AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AD6
AD8
AE16
AE28
AF38
AF8
AG16
AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AJ6
AJ8
AK14
AK24
AK43
AK45
AL12
AL2
BC22
BB42
K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LPT_PCH_M_EDS
REV = 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
C
11 OF 11
LYNXPOINT_BGA695
10 OF 11
@
LYNXPOINT_BGA695
@
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (8/8) VSS
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
23
of
62
5
4
3
2
1
UV1A
1
@ RV505
PEG_GTX_C_HRX_N[0..15]
PEG_GTX_C_HRX_N[0..15]
D
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0
CV531
CV532
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1
CV533
CV534
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
CV535
CV536
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P2
PEG_GTX_HRX_N2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3
CV537
CV538
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4
CV539
CV540
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5
CV541
CV542
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6
CV543
CV544
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P6
PEG_GTX_HRX_N6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7
CV545
CV546
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8
CV547
CV548
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P8
PEG_GTX_HRX_N8
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P10
PEG_GTX_HRX_N10
PEG_GTX_C_HRX_P11 CV558
PEG_GTX_C_HRX_N11 CV559
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P11
PEG_GTX_HRX_N11
PEG_GTX_C_HRX_P12 CV560
PEG_GTX_C_HRX_N12 CV561
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P12
PEG_GTX_HRX_N12
PEG_GTX_C_HRX_P13 CV562
PEG_GTX_C_HRX_N13 CV563
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_C_HRX_P14 CV564
PEG_GTX_C_HRX_N14 CV565
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_C_HRX_P15 CV566
PEG_GTX_C_HRX_N15 CV567
2
2
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
PEG_GTX_HRX_P15
PEG_GTX_HRX_N15
DACA_HSYNC
DACA_VSYNC
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
1
PLTRST_VGA#
[38]
AK9
AL10
AL9
10K_0804_8P4R_5%
+3VS_DELAY
+3VS_DELAY
AM9
AN9
FB_Clamp_REQ#_Q
RPH15
4
3
FB_Clamp_REQ#
1
2
3
4
[38]
QV42B
2N7002DW-7-F_SOT363-6
8
7
6
5
AG10
AP9
AP8
@ RV479
1
2 10K_0402_5%~D
@ RPH13
1
2
3
4
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
PT
R4
R5
I2CA_SCL
I2CA_SDA
R7
R6
I2CB_SCL
I2CB_SDA
R2
R3
I2CC_SCL @ RV299
I2CC_SDA @ RV300
T4
T3
EC_SMB_CK2_PX
EC_SMB_DA2_PX
THM_OVERT#_R
3
1
THM_OVERT#
[38]
+3VS_DELAY
QV40
2N7002_SOT23-3
1
1
VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_SSIN
XTAL_OUTBUFF
C
2.2K_8P4R_5%
2 2.2K_0402_5%~D
2 2.2K_0402_5%~D
I2CC_SCL
I2CC_SDA
EC_SMB_CK2_PX [25]
EC_SMB_DA2_PX [25]
RV319
RV331
1
1
2 2.2K_0402_5%~D
2 2.2K_0402_5%~D
LV14
BLM18PG300SN1D_2P
1
2
1
CV773
0.1U_0402_10V7K~D
2
AD8
8
7
6
5
+1.05VSDGPU
CV574
22U_0805_6.3V6M~D
2
+PLLVDD
AE8
AD7
LV2
BLM18PG181SN1_0603~D
1
2
+CLK_PLLVDD
H3
H2
CLK_27M_IN
CLK_27M_OUT
H1
J4
XTALSSIN
XTALOUTBUFF
1
2
PEX_RST_N
PEX_TERMP
@
1
2
@
1
2
1
2
1
2
1
2
+1.05VSDGPU
B
N14P-GT-A2
2
DGPU_PWR_EN
GPU_HOT#
2
[18,33,59]
@
RV290
2.49K_0402_1%~D
6
5
6
7
8
CV573
22U_0805_6.3V6M~D
[18]
AJ12
AP29
PLTRST_VGA#
1
CV572
4.7U_0603_6.3V6K~D
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
B
GPU_HOT#_R
4
3
2
1
CLK_REQ#
FB_Clamp_REQ#_Q
XTALSSIN
XTALOUTBUFF
AJ11
CV571
0.1U_0402_10V7K~D
AJ26
AK26
PT RPH32
1
CLK
CLK_REQ#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
D
+3VS_DELAY
+3VS_DELAY
+3VS_DELAY
SP_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
8
7
6
5
100K_0804_8P4R_5%
CV570
0.1U_0402_10V7K~D
2 200_0402_1%
1
2
3
4
GPU_HOT#_R
THM_OVERT#_R
THM_ALERT#
FBVREF_ALTV
[59]
PT
CV569
0.1U_0402_10V7K~D
1
AL13
AK13
AK12
GPU_PSI
CV568
0.1U_0402_10V7K~D
@ RV286
CLK_PEG_VGA
CLK_PEG_VGA#
2 0_0402_5%~D
2.2K_8P4R_5%
DACA_VDD
DACA_VREF
DACA_RSET
PLLVDD
[17]
[17]
+3VS_DELAY
QV42A
2N7002DW-7-F_SOT363-6
DACA_RED
DACA_GREEN
DACA_BLUE
8
7
6
5
RPH33
FBVREF_ALTV [29,30,31,32]
GPU_VID_0 [59]
D
1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D
2
2
RPH12
1
2
3
4
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
GPU_GPIO7
[33]
100K_0804_8P4R_5%
FB_Clamp_REQ#_Q
GPU_GPIO7
THM_OVERT#_R
THM_ALERT#
FBVREF_ALTV
GPU_VID_0
GPU_HOT#_R
GPU_GPIO13
@ RV10 1
S
2
2
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
ST
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
[28,33,38]
FB_CLAMP_MON
G
CV550
CV551
PEG_GTX_C_HRX_P10 CV552
PEG_GTX_C_HRX_N10 CV557
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9
C
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
PEG_GTX_HRX_P2
PEG_GTX_HRX_N2
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_HRX_P6
PEG_GTX_HRX_N6
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
PEG_GTX_HRX_P8
PEG_GTX_HRX_N8
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
PEG_GTX_HRX_P10
PEG_GTX_HRX_N10
PEG_GTX_HRX_P11
PEG_GTX_HRX_N11
PEG_GTX_HRX_P12
PEG_GTX_HRX_N12
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_HRX_P15
PEG_GTX_HRX_N15
PEX_WAKE_N
FB_Clamp
2 0_0402_5%
2
PEG_GTX_C_HRX_P[0..15]
2 0_0402_5%~D
@ RV503 1
FB_CLAMP_MON_R
5
[7]
PEG_HTX_C_GRX_N[0..15]
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
2
PEG_GTX_C_HRX_P[0..15]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO
PEG_HTX_C_GRX_N[0..15]
[7]
Part 1 of 7
DACs
[7]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
I2C
PEG_HTX_C_GRX_P[0..15]
PEG_HTX_C_GRX_P[0..15]
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
PCI EXPRESS
[7]
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15
RV289
10K_0402_5%~D
PEG_A_CLKRQ#
1
3
S
[17]
D
2 1
G
PT
CLK_REQ#
CLK_27M_IN
1
QV39
2N7002_SOT23-3
2
PT
YV1
27MHZ_12PF_X3G027000FC1H-H~D
1
3
CLK_27M_OUT
IN
OUT
2
4
1
GND GND
CV575
10P_0402_25V8J
2
PT
CV576
10P_0402_25V8J
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
24
of
62
5
4
3
2
1
Straps
ST
UV1D
+3VS_DELAY
Part 4 of 7
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
THERMDP
THERMDN
34.8K_0402_1%~D
RV304
1
2
15K_0402_1%~D
N15@ RV305
1
2
30.1K_0402_1%~D
@ RV306
1
2
10K_0402_1%~D
RV307
1
2
45.3K_0402_1%~D
RV308
10K_0402_1%~D
VRAMS@ RV312
1
2
15K_0402_1%~D
N14@ RV313
1
2
24.9K_0402_1%~D
N14@ RV314
1
2
4.99K_0402_1%~D
RV315
1
2
10K_0402_1%~D
RV316
4.99K_0402_1%~D
RV303
1
2
10K_0402_1%~D
RV311
1
2
@
C
34.8K_0402_1%~D
N15@
K3
K4
SPI ROM for N14E-GL ( 2M bit/256K byte )
VDD_SENSE
L4
GPU_VDD_SENSE
[59]
GPU_VSS_SENSE
[59]
QT
+3VS_DELAY
+3VS_DELAY
GND_SENSE
L5
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
2
TEST
AK11
AM10
AM11
AP12
AP11
AN11
GPU_TESTMODE
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST#
@ T174
@ T11
@ T12
@ T13
H6
H5
H7
H4
ROM_CS_GPU
ROM_SI_GPU
ROM_SO_GPU
ROM_SCLK_GPU
2
RV324
10K_0402_5%~D
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
+3VS_DELAY
1
@
RV506
10K_0402_1%~D
@
@
CV3509
0.1U_0402_10V7K~D
2
@
U23
1
2 CS#
3 DO
4 WP#
GND
ROM_CS_GPU_R
ROM_SO_GPU
VCC
HOLD#
CLK
DIO
8
7
6
5
B
ROM_SCLK_GPU_R
ROM_SI_GPU_R
W25X20AVSNIG_SO8
ROM_CS_GPU
@
RV507 1
2 0_0402_5%~D ROM_CS_GPU_R
ROM_SI_GPU
@
RV508 1
2 0_0402_5%~D ROM_SI_GPU_R
ROM_SCLK_GPU
@
RV509 1
2 0_0402_5%~D ROM_SCLK_GPU_R
+3VS_DELAY
N14P-GT-A2
+3VS_DELAY
RV326
2.2K_0402_5%~D
[24]
EC_SMB_CK2_PX
2
2
2
RV325
2.2K_0402_5%~D
1
EC_SMB_CK2_PX
A
6
PCH_SMLCLK
QV21A
DMN66D0LDW-7_SOT363-6~D
[24]
EC_SMB_DA2_PX
A
4
EC_SMB_DA2_PX
[17,35,38,40]
5
1
@
Hynix “0”. ROM_SI=PD 5K ohm
Samsung”1”. ROM_SI=PD 10K ohm
2
AF3
AF2
4.99K_0402_1%~D
@ RV302
1
2
4.99K_0402_1%~D
1
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
@
RV314
VRAMH@
RV323
10K_0402_5%~D
AB3
AB4
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
@
1
AK3
AK2
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
4.99K_0402_1%~D
RV310
1
2
2
1
RV318
40.2K_0402_1%~D
1
AG3
AG2
B
10K_0402_1%~D
RV301
1
2
NC
2
MULTI_STRAP_REF0_GND
1
J1
RV320
10K_0402_5%~D
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
RV312
MULTI_STRAP_REF0_GND
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
J2
J7
J6
J5
J3
45.3K_0402_1%~D
RV309
1
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
L3
1
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
CEC
@
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
N14x GPU don't support CEC.
Leave the CEC pin as NC
L2
@
D
Change to PU35K in N15
for use ext ROM
1
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
QT
2
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
C
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
BUFRST_N
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
1
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
2
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
GENERAL
D
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
LVDS/TMDS
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
3
PCH_SMLDATA
[17,35,38,40]
QV21B
DMN66D0LDW-7_SOT363-6~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
25
of
62
5
4
3
2
1
+1.05VSDGPU
PLACE UNDER BGA
+1.5VSDGPU
2
PEX_IOVDD/Q 3.3A
D
2
1
2
1
2
2
@
1
2
1
2
+1.05VSDGPU
CV613
1U_0402_6.3V6K~D
2
1
CV601
22U_0805_6.3V6M~D
2
1
CV600
22U_0805_6.3V6M~D
2
1
CV599
10U_0603_6.3V6M~D
1
CV598
10U_0603_6.3V6M~D
POWER
2
1
CV586
22U_0805_6.3V6M~D
1
CV585
22U_0805_6.3V6M~D
CV584
10U_0603_6.3V6M~D
2
@
CV612
4.7U_0603_6.3V6K~D
+3.3V_RUN_VDD33
0.15A
+3VS_DELAY
J27
FB_CAL_PD_VDDQ
2 40.2_0402_1%~D
H25
FB_CAL_TERM_GND
RV329
1
2 60.4_0402_1%~D
F2
RV330
1
2 100_0402_1%~D
F1
RV332
1
2 100_0402_1%~D
2
FB_GND_SENSE
FB_VDDQ_SENSE
+3VS_DELAY
IFPD_PLLVDD
IFPD_RSET
IFPD_IOVDD
IFPEF_PLLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
1
2
@
1
2
2
1
2
1
2
1
2
ST
0.21A
CV616
4.7U_0603_6.3V6K~D
1
CV615
4.7U_0603_6.3V6K~D
AG12
PEX_SVDD_3V3
1
2 0_0603_5%
+1.5VSDGPU
AH12
PEX_PLL_HVDD
1
CV617
4.7U_0603_6.3V6K~D
1
CV619
1U_0402_6.3V6K~D
2 40.2_0402_1%~D
C
Near GPU
+3.3V_RUN_VDD33 @ RV337
CV621
0.1U_0402_10V7K~D
1
Under GPU
+1.5VSDGPU
CV622
0.1U_0402_10V7K~D
RV328
1
CV623
0.1U_0402_10V7K~D
H27
FB_CAL_PU_GND
RV327
2
AB8
AD6
AC7
AC8
1
LV3
BLM18AG121SN1D_0603~D
2
1
CV614
0.1U_0402_10V7K~D
AG7
AN2
AG6
IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD
2
CV597
4.7U_0603_6.3V6K~D
AF7
AF8
AF6
IFPAB_PLLVDD
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
VDD33_0
VDD33_1
VDD33_2
VDD33_3
2
@
1
+PEX_PLLVDD
1
J8
K8
L8
M8
2
CV611
1U_0402_6.3V6K~D
AH8
AJ8
AG8
AG9
AG26
PEX_PLLVDD
1
CV596
1U_0402_6.3V6K~D
PT
2
CV610
0.1U_0402_10V7K~D
2
1
AG19
AG21
AG22
AG24
AH21
AH25
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
1
+1.05VSDGPU
CV595
1U_0402_6.3V6K~D
2
1
@
CV609
0.1U_0402_25V6K~D
1
2
CV594
0.1U_0402_25V6K~D
2
2
1
CV608
0.1U_0402_25V6K~D
1
@
1
CV593
0.1U_0402_25V6K~D
2
@
2
CV607
1U_0402_6.3V6K~D
1
1
CV592
1U_0402_6.3V6K~D
2
2
CV606
1U_0402_6.3V6K~D
1
1
CV591
1U_0402_6.3V6K~D
2
@
2
CV605
4.7U_0603_6.3V6K~D
C
1
1
CV590
4.7U_0603_6.3V6K~D
2
2
CV604
4.7U_0603_6.3V6K~D
1
1
CV589
4.7U_0603_6.3V6K~D
2
CV603
10U_0603_6.3V6M~D
2
CV602
22U_0805_6.3V6M~D
1
1
CV588
10U_0603_6.3V6M~D
2
CV587
22U_0805_6.3V6M~D
1
Close to Pin
2
@
CV583
10U_0603_6.3V6M~D
close to the GPU
2
1
CV582
4.7U_0603_6.3V6K~D
D
1
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
CV581
1U_0402_6.3V6K~D
Part 5 of 7
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
CV580
1U_0402_6.3V6K~D
UV1E
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
PLACE NEAR GPU
B
B
@
N14P-GT-A2
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
26
of
62
5
4
3
2
1
UV1F
C
B
Part 6 of 7
GND_OPT
GND_OPT
A
@
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
D
+GPU_CORE
UV1G
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
@
+GPU_CORE
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
Part 7 of 7
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
POWER
D
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND
AG11
A2
A33
AA13
AA15
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
C
B
N14P-GT-A2
C16
W32
A
N14P-GT-A2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
27
of
62
5
[29]
FBA_D[0..31]
[30]
FBA_D[32..63]
[29,30]
D
4
FBA_D[0..31]
FBA_D[32..63]
FBA_CMD[0..31]
FBA_CMD[0..31]
[30]
FBA_DBI[4..7]
[29]
FBA_DBI[0..3]
[30]
FBA_EDC[4..7]
[29]
FBA_EDC[0..3]
3
[31]
FBB_D[0..31]
[32]
FBB_D[32..63]
[31,32]
FBA_DBI[4..7]
FBA_DBI[0..3]
FBA_EDC[4..7]
FBA_EDC[0..3]
2
FBB_D[0..31]
FBB_D[32..63]
FBB_CMD[0..31]
FBB_CMD[0..31]
[32]
FBB_DBI[4..7]
[31]
FBB_DBI[0..3]
[32]
FBB_EDC[4..7]
[31]
FBB_EDC[0..3]
1
FBB_DBI[4..7]
FBB_DBI[0..3]
FBB_EDC[4..7]
FBB_EDC[0..3]
D
UV1B
UV1C
Part 3 of 7
2
16mil
1
+FB_VREF
1
2
B
@
@
RV343
1.1K_0402_1%~D
2
CV638
0.01U_0402_16V7K~D
+FBA_PLL_AVDD
+FB_VREF
PT
+FBA_PLL_AVDD
[24,33,38]
ST
FB_Clamp
CV639 1
@ RV510 1
2 0.1U_0402_10V7K~D
2 0_0402_5%
+FBA_DLL_AVDD
@ RV8
1
2 0_0402_5%
RV501
1
2 10K_0402_5%~D
U27
H26
K27
E1
2
2
R28
AC28
@
@
1
1
PT
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_CLK0
FBA_CLK0_N
FBA_PLL_AVDD
FBA_CLK1
FBA_CLK1_N
FB_VREF
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FB_DLL_AVDD
FB_CLAMP
FBA_DEBUG0
FBA_DEBUG1
THE FBA_ECKBxx ARE
USED ON GK107.
NC FBA_WCKB01
ON GF108 AND GF117 FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
@
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
CKE_L
RV339
10K_0402_5%~D
2
FBA_CMD14 1
RST_H*
FBA_CMD29
RV340
10K_0402_5%~D
1
2
RST_L*
FBA_CMD13
RV341
10K_0402_5%~D
1
2
for Test/Debug
M30
H30
E34
M34
AF30
AK31
AM34
AF32
M31
G31
E33
M33
AE31
AK30
AN33
AF33
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
R32
AC32
R30
R31
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
+FBA_PLL_AVDD
CLKA0 [29]
CLKA0# [29]
AB31
AC31
+FBA_PLL_AVDD
CLKA1 [30]
CLKA1# [30]
FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
1
[29]
[29]
[29]
[29]
[30]
[30]
[30]
[30]
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
H17
FBB_D00
FBB_D01
FBB_D02
FBB_D03
FBB_D04
FBB_D05
FBB_D06
FBB_D07
FBB_D08
FBB_D09
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CLK0
FBB_CLK0_N
FBB_PLL_AVDD
FBB_CLK1
FBB_CLK1_N
G14
G20
RV346
60.4_0402_1%~D
+1.5VSDGPU
N14P-GT-A2
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_CMD_RFU0
FBB_CMD_RFU1
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
2
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
CV636
0.1U_0402_10V7K~D
@
+1.5VSDGPU
RV345
60.4_0402_1%~D
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
P30
F31
F34
M32
AD31
AL29
AM32
AF34
CKE_H
+1.5VSDGPU
RV338
10K_0402_5%~D
2
FBA_CMD30 1
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
@
RV344
60.4_0402_1%~D
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
MEMORY INTERFACE
B
@
RV342
1.1K_0402_1%~D
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
2
1
+1.5VSDGPU
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
RV347
60.4_0402_1%~D
1
2
Part 2 of 7
2
2
1
CV637
0.1U_0402_10V7K~D
1
CV3513
22U_0805_6.3V6M~D
2
CV3512
1U_0402_6.3V6K~D
1
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
1
+FBA_DLL_AVDD
LV21
BLM18PG300SN1D_2P~D
1
2
+FBA_DLL_AVDD
C
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MEMORY INTERFACE
A
+1.05VSDGPU
NEED FIND 30R BEAD
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBB_DEBUG0
FBB_DEBUG1
THE FBA_ECKBxx ARE
FBB_WCKB01
USED ON GK107.
FBB_WCKB01_N
NC ON GF108 AND
FBB_WCKB23
GF117
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
@
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
E11
E3
A3
C9
F23
F27
C30
A24
FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7
CKE_H
+1.5VSDGPU
RV409
10K_0402_5%~D
2
FBB_CMD30 1
CKE_L
FBB_CMD14
RV410
10K_0402_5%~D
1
2
RST_H*
FBB_CMD29
RV414
10K_0402_5%~D
1
2
RV418
10K_0402_5%~D
2
FBB_CMD13 1
RST_L*
C
for Test/Debug
D9
E4
B2
A9
D22
D28
A30
B23
D10
D5
C3
B9
E23
E28
B30
A23
FBB_EDC0
FBB_EDC1
FBB_EDC2
FBB_EDC3
FBB_EDC4
FBB_EDC5
FBB_EDC6
FBB_EDC7
B
C12
C20
D12
E12
CLKB0 [31]
CLKB0# [31]
E20
F20
CLKB1 [32]
CLKB1# [32]
F8
E8
A5
A6
D24
D25
B27
C27
FBB_WCK01
FBB_WCK01#
FBB_WCK23
FBB_WCK23#
FBB_WCK45
FBB_WCK45#
FBB_WCK67
FBB_WCK67#
FBB_WCK01
FBB_WCK01#
FBB_WCK23
FBB_WCK23#
FBB_WCK45
FBB_WCK45#
FBB_WCK67
FBB_WCK67#
[31]
[31]
[31]
[31]
[32]
[32]
[32]
[32]
D6
D7
C6
B6
F26
E26
A26
A27
N14P-GT-A2
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
28
of
62
5
4
3
Memory Partition A - Lower 32
bits 64X32 GDDR5
D
RV348
40.2_0402_1%~D
1
2
CLKA0
RV349
40.2_0402_1%~D
1
2
CLKA0#
MF=0
[28]
[28]
CLKA0
CLKA0#
1
2
CV643
0.01U_0402_16V7K~D
C2
C13
R13
R2
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
D2
D13
P13
P2
CLKA0
CLKA0#
FBA_CMD14
J12
J11
J3
FBA_CMD9
J5
FBA_CMD6
FBA_CMD7
FBA_CMD4
FBA_CMD3
K4
K5
K10
K11
FBA_CMD1
FBA_CMD2
FBA_CMD11
FBA_CMD10
H10
H11
H5
H4
A5
U5
RV352 1
RV353 1
RV354 1
2 1K_0402_1%~D
2 1K_0402_1%~D FBA_SEN0
2 121_0402_1%~D
FBA_CMD8
FBA_CMD12
FBA_CMD0
FBA_CMD15
FBA_CMD5
C
[28]
[28]
[28]
[28]
FBA_WCK01#
FBA_WCK01
FBA_WCK23#
FBA_WCK23
J1
J10
J13
J4
G3
G12
L3
L12
FBA_WCK01#
FBA_WCK01
D5
D4
FBA_WCK23#
FBA_WCK23
P5
P4
MF=1
EDC0
EDC1
EDC2
EDC3
EDC3
EDC2
EDC1
EDC0
DBI0#
DBI1#
DBI2#
DBI3#
DBI3#
DBI2#
DBI1#
DBI0#
CK
CK#
CKE#
A12/A13
A8/A7
A11/A6
BA1/A5
BA2/A4
A10/A0
A9/A1
BA3/A3
BA0/A2
BA3/A3
BA0/A2
A9/A1
A10/A0
BA1/A5
BA2/A4
A11/A6
A8/A7
NC
NC
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
1
2
J2
VREFD
VREFD
VREFC
RESET#
S
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
2
1
3
RV356
+1.5VSDGPU
1.33K_0402_1%~D
2
B
@
1
2
1
2
CV663
0.1U_0402_10V7K~D
2
CV662
0.1U_0402_10V7K~D
2
1
CV661
1U_0402_6.3V6K~D
1
CV660
1U_0402_6.3V6K~D
2
CV659
10U_0603_6.3V6M~D
1
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
[28,30]
[28]
FBA_DBI[0..3]
[28]
D
FBA_EDC[0..3]
FBA_EDC[0..3]
[28]
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5
A
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
C
1
2
1
2
1
2
1
2
1
2
1
2
CV658
0.1U_0402_10V7K~D
CV651
820P_0402_50V7K~D
FBA_D[0..31]
FBA_DBI[0..3]
CV657
0.1U_0402_10V7K~D
QV22
L2N7002WT1G
FBA_CMD[0..31]
FBA_D[0..31]
CV656
0.1U_0402_10V7K~D
D
2
G
FBVREF_ALTV
FBA_CMD[0..31]
CV655
0.1U_0402_10V7K~D
[24,30,31,32]
1
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
CV654
1U_0402_6.3V6K~D
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1
FBA_CMD13
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV653
1U_0402_6.3V6K~D
+FBA_VREFC_L
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV652
10U_0603_6.3V6M~D
+FBA_VREFC_L
2
A10
U10
J14
RV355
1.33K_0402_1%~D
RV360
549_0402_1%~D
2
1
1
CV650
820P_0402_50V7K~D
RV359
931_0402_1%
2
1
+FBA_VREFD_L
1
CV776
820P_0402_50V7K~D
+1.5VSDGPU
RV358
549_0402_1%~D
2
1
MF=0
+1.5VSDGPU
MF
SEN
ZQ
+FBA_VREFD_L
RV357
931_0402_1%
2
1
1
NORMAL
UV5
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
2
@
1
2
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
B
A
K4G41325FC-HC04_FBGA170~D
@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Block Diagram
Size
Date:
5
4
3
2
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
29
of
62
5
4
3
Memory Partition A - Upper 32 bits
MF=0
RV361
40.2_0402_1%~D
1
2
D
RV362
40.2_0402_1%~D
1
2
CLKA1
[28]
[28]
CLKA1#
CLKA1
CLKA1#
1
2
CV668
0.01U_0402_16V7K~D
C2
C13
R13
R2
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
D2
D13
P13
P2
CLKA1
CLKA1#
FBA_CMD30
J12
J11
J3
FBA_CMD25
J5
FBA_CMD22
FBA_CMD23
FBA_CMD20
FBA_CMD19
K4
K5
K10
K11
FBA_CMD17
FBA_CMD18
FBA_CMD27
FBA_CMD26
H10
H11
H5
H4
A5
U5
1
1
1
RV363
RV366
RV365
2 1K_0402_1%~D
2 1K_0402_1%~D FBA_SEN2
2 121_0402_1%~D
FBA_CMD24
FBA_CMD28
FBA_CMD16
FBA_CMD31
FBA_CMD21
C
[28]
[28]
1
A8/A7
A11/A6
BA1/A5
BA2/A4
A10/A0
A9/A1
BA3/A3
BA0/A2
BA3/A3
BA0/A2
A9/A1
A10/A0
BA1/A5
BA2/A4
A11/A6
A8/A7
NC
NC
1
1
CV676
820P_0402_50V7K~D
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFD
VREFD
VREFC
RESET#
+1.5VSDGPU
RV369
1.33K_0402_1%~D
2
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
B
2
1
2
CV688
0.1U_0402_10V7K~D
2
1
CV687
0.1U_0402_10V7K~D
2
1
CV686
1U_0402_6.3V6K~D
1
CV685
1U_0402_6.3V6K~D
2
CV684
10U_0603_6.3V6M~D
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
FBA_DBI[4..7]
[28,29]
FBA_D[32..63]
[28]
FBA_DBI[4..7]
[28]
D
FBA_EDC[4..7]
FBA_EDC[4..7]
[28]
+1.5VSDGPU
MF
SEN
ZQ
+FBA_VREFC_H
2
1
A12/A13
FBA_CMD[0..31]
FBA_D[32..63]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5
A
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
C
1
2
1
2
1
2
1
2
1
2
1
2
@
1
2
CV683
0.1U_0402_10V7K~D
3
CK
CK#
CKE#
FBA_CMD[0..31]
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
CV682
0.1U_0402_10V7K~D
QV23
L2N7002WT1G
J2
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV681
0.1U_0402_10V7K~D
FBA_CMD29
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV680
0.1U_0402_10V7K~D
S
P5
P4
EDC3
EDC2
EDC1
EDC0
MF=0
CV679
1U_0402_6.3V6K~D
D
2
G
FBVREF_ALTV
D5
D4
FBA_WCK67#
FBA_WCK67
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV678
1U_0402_6.3V6K~D
[24,29,31,32]
2
FBA_WCK45#
FBA_WCK45
MF=1
CV677
10U_0603_4V6M~D
+FBA_VREFC_H
2
J4
G3
G12
L3
L12
A10
U10
J14
RV368
1.33K_0402_1%~D
RV373
549_0402_1%~D
2
1
FBA_WCK67#
FBA_WCK67
CV675
820P_0402_50V7K~D
RV372
931_0402_1%
2
1
1
CV777
820P_0402_50V7K~D
RV371
549_0402_1%~D
2
1
+FBA_VREFD_H
1
2
[28]
[28]
+1.5VSDGPU
+FBA_VREFD_H
RV370
931_0402_1%
2
1
FBA_WCK45#
FBA_WCK45
J1
J10
J13
1
NORMAL
UV6
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
2
ST
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
B
A
K4G41325FC-HC04_FBGA170~D
@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Block Diagram
Size
Date:
5
4
3
2
Document Number
Rev
0.1
Tuesday, September 17, 2013
Sheet
1
30
of
62
5
4
3
Memory Partition B - Lower 32
bits 64X32 GDDR5
D
RV374
40.2_0402_1%~D
1
2
CLKB0
RV375
40.2_0402_1%~D
1
2
CLKB0#
[28]
[28]
1
2
MF=0
CLKB0
CLKB0#
CV693
0.01U_0402_16V7K~D
C2
C13
R13
R2
FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
D2
D13
P13
P2
CLKB0
CLKB0#
FBB_CMD14
J12
J11
J3
FBB_CMD9
J5
FBB_CMD6
FBB_CMD7
FBB_CMD4
FBB_CMD3
K4
K5
K10
K11
FBB_CMD1
FBB_CMD2
FBB_CMD11
FBB_CMD10
H10
H11
H5
H4
A5
U5
1
1
1
RV378
RV379
RV380
2 1K_0402_1%~D
2 1K_0402_1%~D FBB_SEN0
2 121_0402_1%~D
FBB_CMD8
FBB_CMD12
FBB_CMD0
FBB_CMD15
FBB_CMD5
C
FBB_CMD13
1
A8/A7
A11/A6
BA1/A5
BA2/A4
A10/A0
A9/A1
BA3/A3
BA0/A2
BA3/A3
BA0/A2
A9/A1
A10/A0
BA1/A5
BA2/A4
A11/A6
A8/A7
NC
NC
2
2
1
2
FBB_D[0..31]
FBB_DBI[0..3]
FBB_DBI[0..3]
FBB_EDC[0..3]
[28,32]
[28]
[28]
FBB_EDC[0..3]
D
[28]
+1.5VSDGPU
MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFD
VREFD
VREFC
RESET#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
FBB_CMD[0..31]
FBB_D[0..31]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5
A
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
C
1
2
1
2
1
2
1
2
1
2
@
1
2
1
2
CV708
0.1U_0402_10V7K~D
1
CV713
0.1U_0402_10V7K~D
2
A12/A13
FBB_CMD[0..31]
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
CV707
0.1U_0402_10V7K~D
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
CV712
0.1U_0402_10V7K~D
1
CK
CK#
CKE#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV706
0.1U_0402_10V7K~D
2
CV711
1U_0402_6.3V6K~D
2
CV710
1U_0402_6.3V6K~D
CV709
10U_0603_6.3V6M~D
2
1
DBI3#
DBI2#
DBI1#
DBI0#
RV382
+1.5VSDGPU
1.33K_0402_1%~D
B
1
J2
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV705
0.1U_0402_10V7K~D
1
P5
P4
EDC3
EDC2
EDC1
EDC0
MF=0
CV704
1U_0402_6.3V6K~D
S
D5
D4
FBB_WCK23#
FBB_WCK23
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV703
1U_0402_6.3V6K~D
CV701
820P_0402_50V7K~D
1
FBB_WCK01#
FBB_WCK01
MF=1
CV702
10U_0603_6.3V6M~D
QV24
L2N7002WT1G
3
2
J4
G3
G12
L3
L12
A10
U10
J14
RV381
1.33K_0402_1%~D
+FBB_VREFC_L
1
D
2
G
FBVREF_ALTV
2
RV386
549_0402_1%~D
2
1
+FBB_VREFC_L
[24,29,30,32]
+FBB_VREFD_L
1
CV700
820P_0402_50V7K~D
RV385
931_0402_1%
2
1
+1.5VSDGPU
RV384
549_0402_1%~D
2
1
CV778
820P_0402_50V7K~D
+FBB_VREFD_L
RV383
931_0402_1%
2
1
FBB_WCK23#
FBB_WCK23
2
[28]
[28]
FBB_WCK01#
FBB_WCK01
1
[28]
[28]
J1
J10
J13
1
NORMAL
UV9
FBB_EDC0
FBB_EDC1
FBB_EDC2
FBB_EDC3
2
B
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
A
K4G41325FC-HC04_FBGA170~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
@Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
31
of
62
5
4
Memory Partition B - Upper 32 bits
RV387
40.2_0402_1%~D
1
2
D
RV388
40.2_0402_1%~D
1
2
MF=0
CLKB1
[28]
[28]
CLKB1#
CLKB1
CLKB1#
1
2
CV718
0.01U_0402_16V7K~D
FBB_EDC4
FBB_EDC5
FBB_EDC6
FBB_EDC7
C2
C13
R13
R2
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7
D2
D13
P13
P2
CLKB1
CLKB1#
FBB_CMD30
J12
J11
J3
FBB_CMD25
J5
FBB_CMD22
FBB_CMD23
FBB_CMD20
FBB_CMD19
K4
K5
K10
K11
FBB_CMD17
FBB_CMD18
FBB_CMD27
FBB_CMD26
H10
H11
H5
H4
A5
U5
1
1
1
RV389
RV392
RV391
2 1K_0402_1%~D
2 1K_0402_1%~D
2 121_0402_1%~D
C
FBB_WCK67#
FBB_WCK67
FBB_CMD24
FBB_CMD28
FBB_CMD16
FBB_CMD31
FBB_CMD21
J4
G3
G12
L3
L12
FBB_WCK45#
FBB_WCK45
D5
D4
FBB_WCK67#
FBB_WCK67
P5
P4
1
2
J2
A12/A13
A8/A7
A11/A6
BA1/A5
BA2/A4
A10/A0
A9/A1
BA3/A3
BA0/A2
BA3/A3
BA0/A2
A9/A1
A10/A0
BA1/A5
BA2/A4
A11/A6
A8/A7
NC
NC
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
+FBB_VREFC_H
1
+1.5VSDGPU
2
G
QV25
L2N7002WT1G
3
FBVREF_ALTV
CV726
820P_0402_50V7K~D
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
RV395
1.33K_0402_1%~D
2
2
1
1
[24,29,30,31]
S
B
2
CV738
0.1U_0402_10V7K~D
2
1
CV737
0.1U_0402_10V7K~D
2
1
CV736
1U_0402_6.3V6K~D
1
CV735
1U_0402_6.3V6K~D
2
CV734
10U_0603_6.3V6M~D
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
@
1
2
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_CMD[0..31]
FBB_CMD[0..31]
FBB_D[32..63]
FBB_DBI[4..7]
[28,31]
FBB_D[32..63]
[28]
FBB_DBI[4..7]
[28]
D
FBB_EDC[4..7]
FBB_EDC[4..7]
[28]
+1.5VSDGPU
MF
SEN
ZQ
+FBB_VREFC_H
D
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
C
1
2
1
2
1
2
1
2
1
2
1
2
@
1
2
CV733
0.1U_0402_10V7K~D
FBB_CMD29
CK
CK#
CKE#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV732
0.1U_0402_10V7K~D
2
DBI3#
DBI2#
DBI1#
DBI0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV731
0.1U_0402_10V7K~D
2
2
MF=0
CV730
0.1U_0402_10V7K~D
RV399
549_0402_1%~D
2
1
RV394
1.33K_0402_1%~D
RV398
931_0402_1%
2
1
1
CV725
820P_0402_50V7K~D
1
CV789
820P_0402_50V7K~D
RV397
549_0402_1%~D
2
1
DBI0#
DBI1#
DBI2#
DBI3#
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV729
1U_0402_6.3V6K~D
A10
U10
J14
+FBB_VREFD_H
RV396
931_0402_1%
2
1
J1
J10
J13
EDC3
EDC2
EDC1
EDC0
CV728
1U_0402_6.3V6K~D
+1.5VSDGPU
FBB_WCK45#
FBB_WCK45
[28]
[28]
FBB_SEN2
MF=1
EDC0
EDC1
EDC2
EDC3
CV727
10U_0603_6.3V6M~D
+FBB_VREFD_H
[28]
[28]
3
NORMAL
UV10
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
B
A
K4G41325FC-HC04_FBGA170~D
@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Issued Date
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Block Diagram
Size
Date:
5
4
3
2
Document Number
Tuesday, September 03, 2013
1
Rev
0.1
Sheet
32
of
62
5
4
3
2
1
+3VS to +3VS_DELAY
+1.05VS to +1.05VSDGPU
+VCCP
+1.05VSDGPU
+3VS
3.5A
1
3.3VS_GFX_EN
2
3
RZ3
100K_0402_5%~D
PT
1
3.3VS_GFX_ON#
5
DGPU_PWR_EN
DGPU_PWR_EN
2
2
CZ7
0.01U_0402_16V7K~D
QZ2A
DMN66D0LDW-7_SOT363-6~D
1
[18,24,59]
QZ2B
DMN66D0LDW-7_SOT363-6~D
4
2
CZ8
0.047U_0402_16V4Z~D
CZ6
0.047U_0402_16V4Z~D
2
1
2
PT
1
D
3
1
2 60.4K_0402_1%~D
6
1
4
G
RZ8
100K_0402_5%~D
ST
RZ5
6
5
2
1
+3VALW
4
D
3.3VS_GFX_EN
+3VS_DELAY
1.4A
QZ1
SI3456DDV-T1-GE3_TSOP6~D
+VSBP
D
1
2
3
S
UZ1
SI4634DY-T1-GE3
8
7
6
5
GC6
PT
+3VS
2
FB_Clamp
RZ484
10K_0402_5%~D
3
S
1
FB_Clamp
[24,28,38]
QZ25
AO3413_SOT23-3~D
G
2
C
GPU Power Up Power Rail Sequence
D
S
QZ18
2N7002_SOT23-3
2
G
FB_CLAMP_MON
FB_CLAMP_MON
T1
RZ472
10K_0402_5%~D
Power EN
1
@ RZ9
1
[20,59]
NV3V3Pgood
27Mhz
+1.5V_GPU
2 0_0402_5%~D
DZ2
2
DGPU_PWROK
1
DGPU_FB_EN
CLK REQ#
The ramp time for any rail must be more than 40us.
[57]
1
DGPU_FB_EN
T1 Custom
T2 >0
T3 >0
T4 >0
T5 >100us
T6 >0
T7 <48ms
T8 500ms
T9 >0
GPU all PG
+1.05V_GPU
3
FB_Clamp
100MHz
@ RZ485
100K_0402_5%~D
2
BAT54CW-7-F_SOT323-3~D
C
T8
Driver call
to enable GPU
+3V_GPU
+GPU_CORE
PT
GPU Power Up Sub-system Sequence
[24]
2
1
DGPU_PWR_EN
3
1
D
GPU Power Down Sequence
PT
GPU Reset#
PCIe Training
First rail to power down
B
B
Last rail to power down
Toff < 10ms
T9
T2
T3
T4
T5
T6
T7
GPU Power Down Sub-system Sequence
T1
T7
GPU Disable call
Link tear
down
GPU Reset#
Power EN
Discharge
1
1
NV3V3Pgood
2
2
2
2
3
5
4
5
6
3
3.3VS_GFX_ON#
1
1
100MHz
A
Call Return
4
2
1
3
PT
RZ6
100_0603_5%~D
QZ17B
2N7002DW-7-F_SOT363-6
S
T1 Custom
T2 >0
T3 >0
T4 <=0
T5 >=0
T6 Custom
T7 Custom
27Mhz
+3VS_DELAY
RZ15
1_0402_5%
QZ17A
2N7002DW-7-F_SOT363-6
QZ19
2N7002_SOT23-3
+GPU_CORE
RZ11
1_0402_5%
QZ5B
2N7002DW-7-F_SOT363-6
2
D
2
G
QZ5A
2N7002DW-7-F_SOT363-6
RZ12
100K_0402_5%~D
6 2
1
RZ10
10_0402_1%
A
DGPU_FB_EN
PT
1
+3VALW
+1.05VSDGPU
1
+1.5VSDGPU
T2
Issued Date
T3
2011/08/25
2012/07/25
Deciphered Date
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
T5
T6
Title
Date:
5
T4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2
Block Diagram
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
33
of
62
A
B
+5VALW to +5VS
+3VALW to +3VS
3
PM_SLP_S3#
PM_SLP_S3#
PT
+5VALW
4
5
PM_SLP_S3#
6
7
+3VALW
VIN1
VIN1
14
13
VOUT1
VOUT1
ON1
12
CT1
VBIAS
CT2
VIN2
VIN2
VOUT2
VOUT2
10
9
8
1
1
+5VS
JUMP_43X118
2 470P_0603_50V7K
CZ38 1
+3VS_TPS
2
2 470P_0603_50V7K
@ JP803
1
+3VS
2
1
JUMP_43X118
15
GPAD
1
CZ15 1
2
E
11
GND
ON2
2
+5VS_TPS
D
1495mA
@ JP802
UZ4
1
2
+5VALW
[18,38,40,43,55,56]
C
2041mA
1
TPS22966DPUR_SON14_2X3~D
Close UZ4
Close UZ4
+5VALW
1
2
+5VS
+3VALW
+3VS
1
@ CZ29
1U_0603_10V6K~D
2
1
@ CZ28
1U_0603_10V6K~D
CZ11
10U_0805_10V6M~D
2
2
+3VS
+3VS To +1.5VS
CZ20
10U_0805_10V6M~D
+3VALW to +3V_PCH
RZ602
100K_0603_1%
1
2
2
ST
+3VALW
CZ602
0.1U_0402_25V6
2
1
1
2
CZ600
1U_0603_10V6K
1
JP14
5
1
2
CZ32
1U_0603_10V6K~D
4
@
+3V_PCH_APL 2
UZ14
VOUT
2
SS
2
EN
483mA
+3V_PCH
1
VIN
GND
PAD-OPEN 43x39
1
1
CZ45
10U_0805_10V6M~D
2
3
G5243AT11U_SOT23-5
UZ600
JP11
2
@
PAD-OPEN 43x39
1
+1.5VS_G9141
VSET
1
PT
SHDN#
IN
OUT
SET
GND
GND
GND
GND
8
7
6
5
For deep S3
[18,38]
G9141P11U_SO8
PM_SLP_SUS#
RZ30
100K_0402_5%~D
1
2
2
1
RZ600
11K_0402_1%
2
CZ601
4.7U_0603_6.3VAK
1
2
3
4
1
464mA
+1.5VS
2
RZ601
20K_0402_1%
3
Discharge
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
DC/DC Interface
Size
Date:
A
B
C
D
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
E
Sheet
34
of
62
5
4
3
2
[38]
2
BKOFF#
BKOFF#
1
[18,38]
1
DV13
eDP Conn.
eDP Redriver
2 0_0402_5%~D 3
2
[18]
eDP_PWM
2
1
RV12 1
BKOFF#
2 0_0402_5%~D
INV_PWM
1
QT
3
BAT54CW-7-F_SOT323-3~D
EC_INV_PWM
RV408
100K_0402_5%~D
1 RB751V40_SC76-2
2
@
[38]
JEDP1
+INV_PWR_SRC
2 0_0402_5%
ST
QT
D
Color_CLK
Color_DAT
[8]
EDP_TXP0
CH23 1
[8]
EDP_TXN0
CH25 1
2 0.1U_0402_10V7K~D
EDP_TXP0_C
2 0.1U_0402_10V7K~D
EDP_TXN0_C
INV_PWM
DISPOFF#
EMC@ LV16
1
2
EDP_TXP0_R
3
EDP_TXN0_R
EDP_HPD_S
4
QT
[20]
DLP11SN900HL2L_4P
ST
@ RV481 1
LCD_DCR
2 0_0402_5%
+EDPVDD
W=60mils
ST
[20]
[8]
[8]
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
W=60mils
@ RV480 1
LCD_TEST
2
[38]
DV21 2
@
QT
1
CV3508
10U_0805_10V4Z~D
1
DV10
2
CV3501
0.1U_0402_16V7K~D
RV403
10K_0402_5%~D
BAT54CW-7-F_SOT323-3~D
QT
+EDPVDD
DISPOFF#
1
RV11 1
ENBKL
EDP_TXP1
CH29 1
2 0.1U_0402_10V7K~D
EDP_TXP1_C
EDP_TXN1
CH32 1
2 0.1U_0402_10V7K~D
EDP_TXN1_C
EMC@ LV17
1
4
QT
@ RV482 1
LCD_DBC
2 0_0402_5%
2
EDP_TXP1_R
EDP_AUXN_R
EDP_AUXP_R
3
EDP_TXN1_R
EDP_TXP0_R
EDP_TXN0_R
EDP_TXP1_R
EDP_TXN1_R
DLP11SN900HL2L_4P
EDP_TXP2_R
EDP_TXN2_R
[8]
EDP_TXP2
CH31 1
2 0.1U_0402_10V7K~D
EDP_TXP2_C
[8]
EDP_TXN2
CH40 1
2 0.1U_0402_10V7K~D
EDP_TXN2_C
EMC@ LV19
1
4
QT
EDP_TXP3
CH41 1
2 0.1U_0402_10V7K~D
EDP_TXP3_C
QT4
[8]
EDP_TXN3
CH42 1
2 0.1U_0402_10V7K~D
EDP_TXN3_C
1
EDP_TXP2_R
3
EDP_TXN2_R
EDP_TXP3_R
EDP_TXN3_R
DLP11SN900HL2L_4P
D
ACES_59003-04006-001
CONN@
DLP11SN900HL2L_4P
+VCCIO_OUT
3
EDP_TXP3_R
2
EDP_TXN3_R
1
[8]
2
41
42
43
44
45
46
CONNTST
MGND1
LCD_VDD
MGND2
LCD_VDD
MGND3
V_EDID
MGND4
BIST
MGND5
EDID_CLK
MGND6
EDID_DATA
LVDS_A0LVDS_A0+
LVDS_A1LVDS_A1+
LVDS_A2LVDS_A2+
GND
LVDS_A_CLKLVDS_A_CLK+
GND
LVDS_B0LVDS_B0+
LVDS_B1LVDS_B1+
LVDS_B2LVDS_B2+
GND
LCD_B_CLKLCD_B_CLK+
VR_GND
VR_GND
VR_GND
CONNTST_GND
PWM
DISP_ON/OFF#
NC
VR_SRC
VR_SRC
VR_SRC
BREATH_WHITE_LED
BATT_YELLOW_LED
BATT_WHITE_LED
GND
RV470
10K_0402_5%~D
2
EMC@ LV20
EDP_HPD
1
C
[8]
EDP_AUXN
[8]
EDP_AUXP
2 0.1U_0402_10V7K~D
EDP_AUXN_C
CH44 1
2 0.1U_0402_10V7K~D
EDP_AUXP_C
1
EMC@ LV18
1
2
EDP_AUXN_R
3
EDP_AUXP_R
3
CH43 1
C
QV38
SSM3K7002FU_SC70-3~D
S
RV469
100K_0402_5%~D
4
QT
2
LCD PWR CTRL
[8]
D
2
G
EDP_HPD_S
DLP11SN900HL2L_4P
+EDPVDD
UV12
VOUT
5
GND
W=60mils
2
@RV416
1_0402_5%
EN
3
APL3512ABI-TRG_SOT23-5
RV334
2.2K_0402_5%~D
RV333
2.2K_0402_5%~D
RV419
1
2 1_0402_5%
1
[18]
eDP_LVDDEN
1 RB751V40_SC76-2
3
@ DV19 2
1 RB751V40_SC76-2
@ RV415 1
2 0_0402_5%
[17,25,38,40]
[17,25,38,40]
1
EC_ENVDD
PCH_SMLDATA
RV405
10K_0402_5%~D
2
[38]
4
QV7B
DMN66D0LDW-7_SOT363-6~D
+LCDVDD_R
EC_ENVDD
PCH_SMLCLK
5
QV7A
DMN66D0LDW-7_SOT363-6~D
Color_DAT
DV18 2
[38]
2
2
6
Color_CLK
PT
eDP_LVDDEN
LCD_DELAY
PCH to EC
2
QT
PT
+EDPVDD
+EDPVDD
2
SS
1
2
1
VIN
4
CV26
1U_0603_10V6K~D
1
W=60mils
1
1
+3VS
Touch Screen
ST
B
B
LCD backlight PWR CTRL
+3VS
+INV_PWR_SRC
B+
60mil
PT
D
QV29
SI3457BDV-T1-E3_TSOP6~D
S
60mil
[19]
USB20_P9
USB20_N9
1
LI4
DLW21SN900HQ2L_0805_4P~D
3
4
3
1
2
2
JTS
USB20_P9_R
USB20_N9_R
USB20_N9_R
[38]
2
1
2 0_0402_5%~D
EMC@ RI8
1
2 0_0402_5%~D
[38,40]
1
1
+LCDVDD_R
D
3
2
RV413
1M_0402_5%~D
S
2
G
3
EMC@ RI9
2
CV752
0.1U_0402_25V6K~D
PWR_SRC_ON
TS_sleep#
DV17 1
LID_SW_IN#
DV20 1
PT
+3VS
RV5 1
2RB751V40_SC76-2
2RB751V40_SC76-2
2 10K_0402_5%~D
1
2
3
4
5
6
GND
GND
ACES_50208-00601-P01
CONN@
1
2
1
1
2
3
4
5
6
7
8
USB20_P9_R
PESD5V0U2BT_SOT23-3~D
@
DI3
RV412
1M_0402_5%~D
CV751
0.1U_0402_25V6K~D
3
1
2
[19]
6
5
2
1
4
G
1
4
@
QV30
SSM3K7002FU_SC70-3~D
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
eDP /camera conn.
Size
Date:
5
4
3
2
Document Number
LA-9941P
Wednesday, September 04, 2013
1
Rev
0.1
Sheet
35
of
62
5
4
3
2
1
Place close to JHDMI1
HDMI Active Level Shift(ALS type)
+3VS
For EMI
VDD15_1
VDD15_2
VDD15_3
VDD15_4
2
@ RV431
4.7K_0402_5%~D
HDMI_A2P_VGA
HDMI_A2N_VGA
[8]
[8]
HDMI_A1P_VGA
HDMI_A1N_VGA
1
HDMI_BUF
[8]
[8]
2
@ RV430
4.7K_0402_5%~D
[8]
[8]
HDMI_A0P_VGA
HDMI_A0N_VGA
[8]
[8]
HDMI_A3P_VGA
HDMI_A3N_VGA
CV765 2
CV764 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
TMDS_TX2P
TMDS_TX2N
1
2
CV763 2
CV762 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
TMDS_TX1P
TMDS_TX1N
4
5
CV761 2
CV760 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
TMDS_TX0P
TMDS_TX0N
6
7
CV759 2
CV758 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
TMDS_TXCP
TMDS_TXCN
9
10
+3VS
RV458 1
@ T118
RV444 1
HDMI_BUF
2 4.7K_0402_5%~D
HDMI_EQ
14
13
17
8
HDMI_HPLUG
28
2 4.99K_0402_1%~D
HDMI_PD#
PAD
2 4.7K_0402_5%~D
HDMI_PRE
18
36
23
16
SDA_SRC
SCL_SRC
SDA_SNK
SCL_SNK
IN_CLK+
IN_CLKDDCBUF/SDA_CTL
DCIN_EN/SCL_CTL
EQ/I2C_ADDR
I2C_CTL_EN
HPD_SNK
REXT
PD#
CFG
PRE
+3VS
1
1
@ RV460
4.7K_0402_5%~D
@ RV448
4.7K_0402_5%~D
2
HDMI_DDB_CTRLDATA
HDMI_DDB_CTRLCLK
DDC_DAT_HDMI
DDC_CLK_HDMI
3
HDMI_PCH_HPD
HPD_SRC
12
15
34
37
NC_1
NC_2
NC_3
NC_4
CV771
TMDS_L_TXCP
4
3
2
TMDS_L_TX0N
3
TMDS_L_TX0P
4
2
4
3
2
TMDS_L_TX1N
3
TMDS_L_TX1P
HDMI_PCH_HPD
+3VS
[18]
+1.5VS
HDMI_ISET
+3VS
1
35
41
2
1
2
C
EMC@ LV10
1
1
TMDS_RD_TX2N
4
TMDS_RD_TX2P
2
4
3
2
TMDS_L_TX2N
3
TMDS_L_TX2P
DLW21SN900HQ2L_0805_4P~D
close pin12,37
PS8201A --- SA00005PJ00
PS8401A --- SA00005CW10
HDMI_ISET
TMDS_L_TXCN
DV4
1 1
10 9
TMDS_L_TXCN
TMDS_L_TX2P
DV5
1 1
10 9
TMDS_L_TX2P
TMDS_L_TXCP
2 2
9 8
TMDS_L_TXCP
TMDS_L_TX2N
2 2
9 8
TMDS_L_TX2N
TMDS_L_TX0N
4 4
7 7
TMDS_L_TX0N
TMDS_L_TX1P
4 4
7 7
TMDS_L_TX1P
TMDS_L_TX0P
5 5
6 6
TMDS_L_TX0P
TMDS_L_TX1N
5 5
6 6
TMDS_L_TX1N
@
2
2
Output pre-emphasis setting;
Internal pull down at ~150kΩ, 3.3V I/O.
L: no pre-emphasis
H: 1.6dB pre-emphasis
M: 3.0dB pre-emphasis
2
EMC@ LV9
1
1
TMDS_RD_TX1N
[18]
[18]
TMDS_RD_TX1P
for PS8401, PS8201 NC
@ RV459
4.7K_0402_5%~D
@ RV449
4.7K_0402_5%~D
ST
HDMI_DDB_CTRLDATA
HDMI_DDB_CTRLCLK
+1.5VS
2
@RV451
10K_0402_1%~D
39
38
33
32
1
HDMI_EQ
1
HDMI_PRE
1
2
2
RV450
10K_0402_1%~D
TMDS_RD_TXCP
TMDS_RD_TXCN
PS8201ATQFN40GTR2A0_TQFN40_5X5
1
+3VS
TMDS_RD_TX0P
TMDS_RD_TX0N
22
21
3
DLW21SN900HQ2L_0805_4P~D
GND
EPAD
+3VS
PT
25
24
TMDS_L_TXCN
DLW21SN900HQ2L_0805_4P~D
0.01U_0402_16V7K~D
+3VS
1
OUT_CLK+
OUT_CLK-
IN_D0+
IN_D0-
4
TMDS_RD_TX1P
TMDS_RD_TX1N
0.01U_0402_16V7K~D
C
Enable active DDC buffer;
Internal pull down at ~150KΩ, 3.3V I/O
L: default, passive DDC pass-through
H: active DDC buffer with internal pull up2.36K resistor
M: active DDC buffer without internal pull up resistor
@ RV429
27
26
OUT_D0+
OUT_D0-
IN_D1+
IN_D1-
TMDS_RD_TX2P
TMDS_RD_TX2N
TMDS_RD_TX0P
OUT_D1+
OUT_D1-
IN_D2+
IN_D2-
3
EMC@ LV8
1
1
TMDS_RD_TX0N
30
29
4
2
D
11
VDD33
OUT_D2+
OUT_D2-
2
DLW21SN900HQ2L_0805_4P~D
CV774
19
20
31
40
2
4
TMDS_RD_TXCP
CV745
CV756
CV744
CV772
CV775
2
U22
1
2
1
0.1U_0402_10V7K~D
2
1
0.01U_0402_16V7K~D
1
0.01U_0402_16V7K~D
+3VS
2
0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
D
1
0.01U_0402_16V7K~D
1
1
EMC@ LV7
1
1
TMDS_RD_TXCN
CV743
+1.5VS
@
3 3
Receiver equalization setting;
Internal pull down at ~150kΩ, 3.3V I/O.
L: programmable EQ for channel loss up to 5.3dB
H: programmable EQ for channel loss up to 10dB
M: programmable EQ for channel loss up to 14dB
3 3
8
8
AZ1045-04F_DFN2510P10E-10-9
AZ1045-04F_DFN2510P10E-10-9
B
B
HDMI DDC
HDMI conn
W=40mils
+5VS
JHDMI
1
DV11
RB751V40_SC76-2
1
1
1
2
+5V_HDMI_DDC
RV445
2.2K_0402_5%~D
RV447
2.2K_0402_5%~D
1
2
CV767
10U_0603_6.3V6M~D
1
2
2
DDC_DAT_HDMI
DDC_CLK_HDMI
HDMI_Reserved
HDMI_CEC
TMDS_L_TXCN
TMDS_L_TXCP
TMDS_L_TX0N
TMDS_L_TX0P
TMDS_L_TX1N
For EMI Reserve
DDC_CLK_HDMI
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPLUG
+VDISPLAY_VCC
1.5A_6V_1206L150PR~D
CV766
0.1U_0402_10V7K~D
DV8
2
1
HDMIF1 2
3 NC
BAT1000-7-F_SOT23-3~D
2
+5VS
Place close to JHDMI1
@ CV768
1
2 0.1U_0402_25V6K~D
HDMI_HPLUG
TMDS_L_TX1P
TMDS_L_TX2N
@ CV795
1
2 0.1U_0402_25V6K~D
HDMI_Reserved
TMDS_L_TX2P
@ CV796
1
2 0.1U_0402_25V6K~D
HDMI_CEC
DDC_DAT_HDMI
A
HPD
+5V
DDC/CEC GND
SDA
SCL
Reserved
CEC
CKCK_Shield
CK+
D0D0_Shield
D0+
D1D1_Shield
D1+
GND1
D2GND2
D2_Shield GND3
D2+
GND4
20
21
22
23
A
ACON_HMRB9-AK120C
CONN@
close to JHDMI
Compal Secret Data
Security Classification
Issued Date
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
HDMI
Size Document Number
Custom
4
3
2
Rev
0.1
LA-9941P
Date:
5
Compal Electronics, Inc.
Tuesday, September 03, 2013
1
Sheet
36
of
62
5
4
3
2
1
DP Re-Driver config
Mini DP
+3VS
+3VS_mDPR
@ R8 1
+3VS_mDPR
2 0_0805_5%
R2534
C2021
1
mDP_PEQ
@ R2532
@ R2535
1
1
2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
mDP_CFG1_INPUT
@ R2536
@ R2533
1
1
2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
mDP_CFG0
@ R2530
@ R2531
1
1
2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
mDP_RST#
1
C38
2
2
0.1U_0402_10V7K~D
1
C48
2
0.1U_0402_10V7K~D
1
C37
2
0.1U_0402_10V7K~D
C43
1
0.1U_0402_10V7K~D
ST
1
2
2 10K_0402_1%~D
2.2U_0402_6.3V6M~D
+3VS_mDPR
+3VS_mDPR
U11
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
mDP_A0P_CPU
mDP_A0N_CPU
mDP_A1P_CPU
mDP_A1N_CPU
mDP_A2P_CPU
mDP_A2N_CPU
mDP_A3P_CPU
mDP_A3N_CPU
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
DISP_C_A0P
DISP_C_A0N
DISP_C_A1P
DISP_C_A1N
DISP_C_A2P
DISP_C_A2N
DISP_C_A3P
DISP_C_A3N
38
39
41
42
44
45
47
48
DISP_C_A0P
DISP_C_A0N
DISP_C_A1P
DISP_C_A1N
DISP_C_A2P
DISP_C_A2N
DISP_C_A3P
DISP_C_A3N
3
4
5
mDP_PEQ
mDP_CFG0
D
+3VS_mDPR
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
PT
CV779
CV780
CV781
CV782
CV783
CV784
CV785
CV786
+3VS_mDPR
1
6
12
25
32
36
D
IN0p
IN0n
IN1p
IN1n
IN2p
IN2n
IN3p
IN3n
OUT0p
OUT0n
OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
I2C_ADDR
CFG1
SCL_CTL/PEQ
SDA_CTL/CFG0
NC
RST#
26
4.99K_0402_1% 1
2 R2515
7
8
9
mDP_HPD
PT
mDP_AUXP_PCH
mDP_AUXN_PCH
33
34
mDP_DDC_CTRLCLK
mDP_DDC_CTRLDATA
2
2
CV813
CV812
1 0.1U_0402_10V6K~D
1 0.1U_0402_10V6K~D
mDP_AUXP_PCH_C
mDP_AUXN_PCH_C
30
29
CAD_SNK
REXT
HPD_SINK
mDP_A0P_R
mDP_A0N_R
mDP_A1P_R
mDP_A1N_R
mDP_A2P_R
mDP_A2N_R
mDP_A3P_R
mDP_A3N_R
40
mDP_CFG1_INPUT
2
2
2
2
2
2
2
2
C93
C47
C42
C53
C59
C57
C54
C56
1
1
1
1
1
1
1
1
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
DISP_A0P_R
DISP_A0N_R
DISP_A1P_R
DISP_A1N_R
DISP_A2P_R
DISP_A2N_R
DISP_A3P_R
DISP_A3N_R
46
35
mDP_RST#
10
CAB_DET_SINK
11
mDP_HPD_SINK
CAD_SRC
HPD_SRC
AUX_SNKP
AUX_SNKN
SCL_DDC
SDA_DDC
CEXT
NC2
NC3
NC4
NC5
AUX_SRCP
AUX_SRCN
28
27
DISP_CLK_AUXP_CONN
DISP_DAT_AUXN_CONN
2
15
21
37
43
1
2
18
24
31
49
GND1
GND2
GND3
EPAD
[18]
[18]
[18]
[18]
PD#
23
22
20
19
17
16
14
13
C2020
2.2U_0402_6.3V6M~D
PS8330BQFN48GTR-A0_QFN48_7X7
DV9
DPF1
2
1
1
2
+3VS_DP
3 NC
BAT1000-7-F_SOT23-3~D 1.5A_6V_1206L150PR~D
C
+3VS
C
DV2
DISP_A3P_R
1 1
10 9
DISP_A3P_R
DISP_A3N_R
2 2
9 8
DISP_A3N_R
DISP_A0P_R
4 4
7 7
DISP_A0P_R
DISP_A0N_R
5 5
6 6
DISP_A0N_R
2
CV770
0.1U_0402_16V7K~D
2
@
1
CV769
10U_0603_6.3V6M~D
1
JMDP
CAB_DET_SINK
+3VS
PT
2
1
1
+3VS
RV452
100K_0402_5%~D
RV491
100K_0402_5%~D
2
DISP_A2P_R
DISP_CLK_AUXP_CONN
DISP_A2N_R
DISP_DAT_AUXN_CONN
DISP_A1P_R
3 3
1
1
3
1
RV453
1M_0402_5%~D
1
2
2
2
DISP_A1N_R
6 6
2
DISP_A2P_R
7 7
5 5
1
8
B
AZ1045-04F_DFN2510P10E-10-9
5.1M_0402_5%
9 8
4 4
DISP_A1P_R
600032GB020M207ZL
CONN@
RV490
100K_0402_5%~D
0.1U_0402_10V6K~D
2 2
DISP_A1N_R
21
22
23
24
GND1
GND2
GND3
GND4
RV456
DISP_A2P_R
2
22U_0805_6.3V6M~D
S
DISP_A2N_R
CV788
2
G
QV37
2N7002_SOT23-3
10 9
CV787
DV3
1 1
D
CV32
0.01U_0402_16V7K~D
@
DISP_A2N_R
1
CAB_DET_SINK#
Close to JMDP1
DISP_A1P_R
DISP_A3P_R
DISP_A1N_R
DISP_A3N_R
GND
HPD
LANE0_P
CONFIG1
LANE0_N
CONFIG2
GND
GND
LANE1_P
LANE3_P
LANE1_N
LANE3_N
GND
GND
LANE2_P
AUX_CH_P
LANE2_N
AUX_CH_N
GND
DP_PWR
1
8
AZ1045-04F_DFN2510P10E-10-9
2
[18]
3 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
mDP_HPD_SINK
DISP_A0P_R
CAB_DET_SINK
DISP_A0N_R
DISP_CEC
B
DP HPD to PCH (iGPU)
DDC Dongle SW for DP
@ RV411 1
2 0_0402_5%
ST
PT
mDP_HPD
[16,18]
DP_PCH_HPD
DP HPD for DGPU output (Optimus)
PT
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
4
3
2
Rev
0.1
LA-9941P
Date:
5
Compal Electronics, Inc.
Mini DP
Size
Document Number
Custom
Tuesday, September 03, 2013
Sheet
1
37
of
62
5
4
EC KB9012 PT
3
2
+3VALW_EC
2
1
2
2
RE9
100K_0402_5%~D
Ra
1
CE10
0.1U_0402_16V7K~D
RE12
QT
AD_BID0
2
CE12 @
0.1U_0402_16V7K~D
1
+3VLP
@ RE13
33_0402_5%~D
N15@
RPE2
1
2
3
4
8
7
6
5
[20] EC_RUNTIME_SCI#
[14,8] DRAMRST_CNTRL_S3
TP_CLK
TP_DATA
ESB_CLK
ESB_DAT
[39]
RE11 1
4.7K_8P4R_5%
2 47K_0402_5%~D
@ RE28 1
2 10K_0402_5%~D
EAPD#
@ RE76 1
2 10K_0402_5%~D
WAKE_PCH#
KSI[0..7]
[39]
EC_RST#
KSI[0..7]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
PCH_SUSWARN#
KSO[0..16]
KSO[0..16]
+3VALW_EC
+3VS
RPH19
1
2
3
4
8
7
6
5
PCH_SMLCLK
PCH_SMLDATA
EC_SMB_CK1
EC_SMB_DA1
2.2K_8P4R_5%
@ RE43 1
2 10K_0402_5%~D
@ RE57 1
CE14 1
KSO3
2 10K_0402_5%~D
PLT_RST#
2 0.1U_0402_16V7K~D
EC_RST#
[18]
EC to BAT,Charge
[17,25,35,40]
[17,25,35,40]
PCH_SUSWARN#
[52,53]
[52,53]
N5
M5
K13
N6
M6
D9
E12
E13
D12
D13
C12
C13
D10
J13
J12
H12
H13
H10
H9
G9
G10
G13
G12
F13
F12
F10
F9
E10
E9
E8
D8
A8
A7
B8
A6
EC_SMB_CK1
EC_SMB_DA1
PCH_SMLCLK
PCH_SMLDATA
EC_SMB_CK1
EC_SMB_DA1
PCH_SMLCLK
PCH_SMLDATA
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
INVT_PWM/PWM0/GPIO0F
BEEP#/PWM1/GPIO10
FANPWM0/GPIO12
ACOFF/FANPWM1/GPIO13
PWM Output
AD Input
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
PS2 Interface
SDICS#/GPXIOA00
SDICLK/GPXIOA01
SDIDO/GPXIOA02
SDIDI/GPXIOD00
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
SM Bus
[49]
T43
BATT_LED#_LV5
EC_INV_PWM
SYSTEM_FAN_FB
SYSTEM_FAN2_FB
QT[39][35]
PAD
[40]
[42]
[42]
SYSTEM_FAN_FB
SYSTEM_FAN2_FB
EC_TX
EC_RX
AUD_MUTE
EC_TX
EC_RX
[48]
[20]
AUD_MUTE
[18] SUSACK#
WAKE_PCH#
[58]
J1
K1
VR_ON
VR_ON
EMC@ RE39 1
SUSCLK_R
2 0_0402_5%~D
EC_CRY2
GPI
EMC@ CE18
KB9012BF A4 LFBGA128P
20P_0402_50V8J~D
B10
A9
A10
B9
BATT_LED#_LV1
ACOFF
EC_ENVDD
BATT_LED#_LV2
[40]
[39]
+3VALW
MEM_TEMP0 [41]
FAN_TEMP0
[41]
ADP_I [52,53]
SKIN_TEMP0
SKIN_TEMP1
FB_Clamp_REQ#
RE33 1
2 10K_0402_5%~D
USB_ILIM_SEL
RE61 1
2 10K_0402_5%~D
@ RE58 1
AC_IN
[41]
[41]
D6
E6
E5
D5
A5
B5
BATT_LED#_LV1
[49]
ACOFF
[53]
EC_ENVDD
[35]
BATT_LED#_LV2
[49]
TP_CLK
TP_DATA
PM_SLP_S4#/GPXIOD01
ENBKL/GPXIOD02
GPXIOD03
GPXIOD04
GPXIOD05
GPXIOD06
GPXIOD07
2 10K_0402_5%~D
EMC@ CE16 1
2 100P_0402_50V8J~D
CE23 1
2 0.1U_0402_16V7K~D
EC_ON
USB0_PWR_EN_EC
[44]
IMVP_VR_PG
[18,58,6]
HDA_SDO
[16]
VCIN0_PH
[8]
HDA_SDO
J2
K2
M1
N2
AC_IN
EAPD# [47]
PCH_PWROK_EC
[18]
AC_PRESENT
[18]
USB1_PWR_EN_EC
[44]
TP_CLK [39]
TP_DATA [39]
PCH_PWROK_EC
AC_PRESENT
B1
A1
C1
C2
2 100K_0402_5%~D
RE36 1
USB1_DET_EC#_D
USB0_DET_EC#_D
EC_BATT_PRS#
BATT_LED#_LV3
EC_BATT_PRS#
BATT_LED#_LV3
[52,53]
[49]
C
B6
B7
B4
A4
B3
A3
A2
B2
H5
N1
MEM_TEMP1 [41]
FAN_TEMP1
[41]
USB0_CTL1
[44]
BATT_LOW_LED#
[49]
CAPS_LED#
[39]
PWRBTN_LED#
[39]
BATT_LED#_LV4
[49]
5VA_EN [54]
LID_SW_IN#
[35,40]
PM_SLP_S4# [18,55]
CAPS_LED#
PWRBTN_LED#
BATT_LED#_LV4
5VA_EN
LID_SW_IN#
PM_SLP_S4#
D4
D1
D2
E2
E4
E1
F4
F2
F1
PCH_RSMRST#
PCH_RSMRST#
PAD
T126 @
@ RE32 1
2 10K_0402_5%~D
[18]
VCIN1_PH
H_PROCHOT#_EC
H_PROCHOT#_EC
VCOUT0_PH#
BKOFF#
EN_WLANPWR#
PM_SLP_SUS#
HWPG
+3VLP
VCOUT0_PH#
BKOFF# [35]
EN_WLANPWR#
PM_SLP_SUS#
+3VALW_EC
[52]
[53]
RE66
10K_0402_5%~D
[40]
[18,34]
F5
G1
G5
H1
G4
H4
H2
AC_IN
EC_ON
AC_IN
DE12 1
EC_WLAN_WAKE#
2 RB751V40_SC76-2
[53]
EC_ON_CTRL#
BATBTN#
PBTN_OUT#
RE38 1
EC_PECI
+V18R
L1
1
USB1_CTL1
[44]
PBTN_OUT#
[18,6]
2 43_0402_1%
H_PECI
[8]
CE17
4.7U_0805_10V6
HWPG
+3VALW_EC
20mil
LE2
1
RE29
10K_0402_5%~D
2 FBMA-L11-160808-800LMT_0603
2
ECAGND
+3VALW_EC
B
[56,8]
[24]
LCD_TEST
9
FB_Clamp_REQ#
FB_Clamp_REQ#
[35]
11
LCD_TEST
+3VS
12
GPIO02
GPIO0C/PWM0
GPIO03
GPIO0D/PWM1
GPIO04
GPIO0E/PWM2
GPIO05
GPIO0F/PWM3
GPIO06
GPIO07/CAS_CLK
GPIO10/ESB_RUN#
GPIO11/BaseAddOpt
GND
5
2
[39]
PBTN_SW#
+3VLP
RE48 1
USB1_DET_EC#
[40]
USB2_DET_EC#
[40]
USB3_DET_EC#
DE7
1
2 RB751V40_SC76-2
DE13 1
2 RB751V40_SC76-2
DE14 1
2 RB751V40_SC76-2
DE17 1
2 RB751V40_SC76-2
USB0_DET_EC#_D
USB1_DET_EC#_D
USB2_DET_EC#_D
USB3_DET_EC#_D
+3VLP
1
RE341
2.2K_0402_1% DE303
1
2
2
RE340
2.2K_0402_1% DE304
1
2
1
@ RE321
0_0402_5% DE306
1
2
1
@ RE322
0_0402_5%
ST
RB751V40_SC76-2
1
2 RB751V40_SC76-2
DE9
1
2 RB751V40_SC76-2
RB751V40_SC76-2
2
3VA_EN
RE50
100K_0402_5%~D
3VA_EN
2
DE10 1
2 RB751V40_SC76-2
DE15 1
2 RB751V40_SC76-2
DE16 1
2 RB751V40_SC76-2
DE18 1
2 RB751V40_SC76-2
D
2
G
QE1
2N7002_SOT23-3
@ RE44
150K_0402_5%
S
@
Issued Date
CE26
0.1U_0402_25V6K~D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
4
A
USBCHG_DET#_D
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
Date:
5
USBCHG_DET_D
[54]
RB751V40_SC76-2
2
EC_ON_CTRL#
2
RE59
100K_0402_5%~D
+3VLP
RB751V40_SC76-2
1
2
DE305
2
2
1
1
2
DE8
2 10K_0402_5%~D
PBTN_SW#
[45]
60 mil
2 10K_0402_5%~D
1
THM_OVERT#
RE49
100K_0402_5%~D
2 10K_0402_5%~D
BATBTN#
ENBKL [18,35]
[45] USB0_DET_EC#
+3VALW_EC
1
RE34 1
1
VCOUT0_PH#
2
Power on Circuit
RE47 1
2
ENBKL
0_0402_5%~D
CCD_INT#
QT
3
1
EC_ON
RE42
100K_0402_5%~D
[24]
+3VLP
1
RE469 @
QT
[40,44]
1
USBCHG_DET_D
+3VLP
BATBTN#
QT
24
[40]
USB_ILIM_SEL
+3VS
2
H_PROCHOT#_EC
CE21
47P_0402_50V8J~D
2
[49]
23
CCD_INT#
QT
1
A
2
3
1
1
A
USB_ILIM_SEL
1
P
Y
CCD_INT#
WLAN_WAKE#
2
G
4
20
22
[40]
UE2 SN74LVC1G06DCKR_SC70-5
NC
H_PROCHOT#
H_PROCHOT#
+3VALW_EC
USB3_PWR_EN_EC
21
CE19
0.1U_0402_16V7K~D
[40]
[46]
USB3_DET_EC#_D
19
25
1
DSP_PD#
CE15
0.1U_0402_16V7K~D
KC3810_QFN24_4X4
VCC
[40]
USB2_PWR_EN_EC
17
18
[40]
USB3_CTL1
16
1
GPIO0B
USB2_CTL1
15
2
8
10
GPIO01
14
CE322
1U_0603_10V6K~D
2 10K_0402_5%~D
PT
GPIO0A
RE55
10K_0402_5%~D
LCD_DELAY
USB2_DET_EC#_D
PT
+3VALW
GPIO09
ESB_DAT
RE69
10K_0402_5%~D
[35]
7
GPIO08/CAS_DAT
RST#
RE71
10K_0402_5%~D
USB_D_PD#
6
GPIO00
RE72
10K_0402_5%~D
[40,45]
5
B
HWPG
+3VALW_EC
1
TS_sleep#
4
2 4.7K_0402_5%~D
2
[35]
3
ESB_DAT
RE74 1
1
FB_Clamp
2
KC3810_RST#
13
2
[24,28,33]
GPU_HOT#
TEST_EN#
2
GPU_HOT#
ESB_CLK
GND
[24]
1
2 0_0402_5%
PT
UE36
ESB_CLK
@ RE27 1
+V1.05S_VCCP_PWRGOOD
KC3810_RST#
2 0.1U_0402_16V7K~D
1
2 47K_0402_5%~D
CE20 1
2
RE20 1
@ RE64 1
WLAN_WAKE#
2
2
2
ADP_I
AD_BID0
KB_LED_PWM
[39]
BEEP# [47]
SYSTEM_FAN2_PWM
SYSTEM_FAN_PWM
[40]
V18R
1
RE40
100K_0402_5%~D
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
EC_ON/GPXIOA05
EC_SWI#/GPXIOA06
ICH_PWROK/GPXIOA07
GPO
BKOFF#/GPXIOA08
WL_OFF#/GPXIOA09
GPXIOA10
GPXIOA11
XCLKI
XCLKO
1
[18,40]
WAKE_PCH#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB0/GPIO14
FANFB1/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
GND
GND
GND
GND
GND
@
J5
N9
L13
K6
N7
M7
N8
K8
M11
N11
K10
K9
N12
M13
L12
B13
A13
B12
A12
E7
D7
AGND
EC_SMI#
PS_ID
ESB_CLK
ESB_DAT
BATT_LED#_LV5
[20] EC_SMI#
[52] PS_ID
A11
PM_SLP_S3#
PM_SLP_S5#
MOSI
MISO
SPICLK/GPIO58
SPICS#
SPI Flash ROM
J8
J9
N13
J10
G2
[18,34,40,43,55,56]
[18]
KB_LED_PWM
BEEP#
SPI Device Interface
GPIO
SCL0/GPIO44
SDA0/GPIO45
SCL1/GPIO46
SDA1/GPIO47
M9
M8
M10
N10
VR_ON
DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D
IREF/DA2/GPO3E
DA3/GPO3F
EC to Ambient Light Sensor, GPU,RTC Counter
T43 revrese under Keyboard
for easy to debug
BATT_TEMP/AD0/GPI38
BATT_OVP/AD1/GPI39
ADP_I/AD2/GPI3A
AD3/GPI3B
AD4/GPI42
SELIO2#/AD5/GPI43
MISC
D
Close to pin B13
1
CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_RUNTIME_SCI#
[17] CLK_PCI_LPC
[18,40,42,6,8]
PLT_RST#
+3VS
+3VALW_EC
M2
L2
M3
K4
N3
M4
K5
N4
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
[20] GATEA20
[20] KB_RST#
[17,40] SERIRQ
[17,40,42]
LPC_FRAME#
[17,40,42]
LPC_AD3
[17,40,42]
LPC_AD2
[17,40,42]
LPC_AD1
[17,40,42]
LPC_AD0
Analog Board ID definition,
Please see page 4.
2 100P_0402_50V8J~D ECAGND
1
@ CE11
22P_0402_50V8J~D
2
EC_BATT_PRS# EMC@ CE13 1
2
1
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
2
UE1
B11
J7
K12
M12
K7
J4
J6
100K_0402_1%
D
[53,58,8]
1
RE12
33K_0402_1%
N14@
Rb
2
2
1
CE9
1000P_0402_50V7K~D
2
1
CE8
1000P_0402_50V7K~D
2
1
CE7
0.1U_0402_16V7K~D
1
CE6
0.1U_0402_16V7K~D
2
CE5
0.1U_0402_16V7K~D
1
CE4
0.1U_0402_16V7K~D
2
CLK_PCI_LPC
CE22
10U_0603_6.3V6M~D
1
LE1
FBMA-L11-160808-800LMT_0603
1
2
+EC_VCCA
1
2 0_0402_5%
2
2 0_0402_5%~D
@ RE60 1
1
@ RE56 1
Board ID
ECAGND
+3VLP
+3VALW
ST
C
1
+3VALW_EC
3
2
EC ENE-KB930/ ENE3810
Document Number
LA-9941P
Tuesday, September 17, 2013
1
Sheet
38
Rev
0.1
of
62
5
4
3
2
1
PWM FAN
Power on Button
+5VS
1
2
SW1
D
4
3
R67
1
2 3.3K_0402_1%
+5VALW
6
5
R66
1
2 3.3K_0402_1%
+5VALW
2
G
ST
+3VS
+5VS
S
[38]
PT
+5VS
RE53
10K_0402_5%~D
RE51
100K_0402_5%~D
QZ20
2N7002_SOT23-3
2
PWRBTN_LED#
3
[38]
@ DE2
PESD24VS2UT_SOT23-3~D
[38]
2
1
TML-3WWW-Q-T-R_6P
D
[38]
3
PBTN_SW#
1
1
1
2
2
PT
1
D
2
DE4
SYSTEM_FAN_FB
1
1
CH751H-40PT_SOD323-2~D
CE27
0.01U_0402_16V7K~D
ACES_50224-00401-001
CONN@
C
Touch pad
INT_KBD CONN
1
6
2
3
2
@
DE5
PESD5V0U2BT_SOT23-3~D
3
1
B
1
@
DE6
PESD5V0U2BT_SOT23-3~D
+3VS
9
10
[38]
2
CAPS_LED#
1
[14,15,17,43,6] PCH_SMBDATA
[14,15,17,43,6] PCH_SMBCLK
1
2
3
4
5
6
7
8
ST
2
20mil
F1
0.5A_13.2V_NANOSMDC050F-13.2-2
KB_BL_DET
KB_BL_DET R30
1
2 47K_0402_5%~D
KB_BL_PWM
1
[20]
2
[38]
1
2
4 G2
3 G1
2
1
A150420-SAHR22
CONN@
R31
100K_0402_5%~D
C12
10U_0603_6.3V6M~D
D
3
A
1
C11
1U_0603_10V6K~D
JKBL
4
3
2
1
2
1
S
2
G
KB_LED_PWM
1
2
@ CE58
0.1U_0402_25V6K~D
B
JKB
[38]
+5VS_KBL
1
KB_CAPS_LED
GND1
GND2
Keyboard back light
+5VS_KBL
2 470_0402_5%~D
ACES_50506-00841-P01
CONN@
Q11
SSM3K7002FU_SC70-3~D
6
5
KSI[0..7]
KSI[0..7]
[17]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KB_DET#
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KB_CAPS_LED
KB_DET#
KB_DET# @ CE29 1
2 100P_0402_50V8J~D
KSO7
@ CE31 1
2 100P_0402_50V8J~D
2 100P_0402_50V8J~D
KSO6
@ CE33 1
2 100P_0402_50V8J~D
@ CE34 1
2 100P_0402_50V8J~D
KSO5
@ CE35 1
2 100P_0402_50V8J~D
KSO12
@ CE36 1
2 100P_0402_50V8J~D
KSO4
@ CE37 1
2 100P_0402_50V8J~D
KSI0
@ CE38 1
2 100P_0402_50V8J~D
KSO3
@ CE39 1
2 100P_0402_50V8J~D
KSO11
@ CE40 1
2 100P_0402_50V8J~D
KSI4
@ CE41 1
2 100P_0402_50V8J~D
KSO10
@ CE42 1
2 100P_0402_50V8J~D
KSO2
@ CE43 1
2 100P_0402_50V8J~D
KSI1
@ CE44 1
2 100P_0402_50V8J~D
KSO1
@ CE45 1
2 100P_0402_50V8J~D
KSI2
@CE46 1
2 100P_0402_50V8J~D
KSO0
@ CE47 1
2 100P_0402_50V8J~D
KSO9
@ CE48 1
2 100P_0402_50V8J~D
KSI5
@ CE49 1
2 100P_0402_50V8J~D
KSI3
@CE50 1
2 100P_0402_50V8J~D
KSI6
@ CE51 1
2 100P_0402_50V8J~D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KSO8
@CE52 1
2 100P_0402_50V8J~D
KSI7
@ CE53 1
2 100P_0402_50V8J~D
ACES_50692-03041-001
CONN@
[38]
20mil
QZ24A
2N7002DW-7-F_SOT363-6
JTP
1
2
3
4
5
6
7
8
TP_DATA_R
TP_CLK_R
RE84 1
2
RE52
100K_0402_5%~D
4
QZ24B
2N7002DW-7-F_SOT363-6
5
EMC@ C16
10P_0402_50V8J~D
3
RE54
100K_0402_5%~D
1
1
EMC@ C15
10P_0402_50V8J~D
+5VS
+VSBP
+3VALW
2
EMC@ C14
10P_0402_50V8J~D
TP_CLK_R
TP_DATA_R
2
1
2 BLM18AG601SN1D_0603~D
2 BLM18AG601SN1D_0603~D
1
EMC@ C13
10P_0402_50V8J~D
2
1
2
1
1
2
EMC@ L1
EMC@ L2
[38] TP_CLK
[38] TP_DATA
+5VS
PT
JFAN1
1
2 1
3 2
4 3
5 4
6 G1
G2
SYSTEM_FAN_PWM
2
C
CE57
2.2U_0603_6.3V6K~D
KSO16
@CE28 1
2 100P_0402_50V8J~D
KSO15
@CE30 1
2 100P_0402_50V8J~D
KSO14
@CE32 1
KSO13
Compal Secret Data
Security Classification
Issued Date
KSO[0..16]
KSO[0..16]
2011/08/25
2012/07/25
Deciphered Date
Title
GND
GND
31
32
A
Compal Electronics, Inc.
SW/TP/SCREW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-9941P
Date:
5
4
3
2
Tuesday, September 03, 2013
Sheet
1
39
of
62
5
4
3
ATMEL TPM
2
M/B to D/B conn.
+3VS
CONN@
[19]
[19]
D
1
2
TPM@ C2
4700P_0402_25V7K~D
2
TPM@ C1
0.1U_0402_25V6K~D
1
[19]
[19]
+3VS
LPCPD#
26
23
20
17
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
V_BAT
NBO_13
NBO_14
LAD0
LAD1
LAD2
LAD3
GPIO6
21
22
16
27
15
CLK_PCI_TPM
LPC_LFRAME#
PLT_RST#
[17] CLK_PCI_TPM
[17,38,42]
LPC_FRAME#
[18,38,42,6,8]
PLT_RST#
[17,38] SERIRQ
[18] PM_CLKRUN#
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
TESTBI
TESTI
ATEST_1
ATEST_2
ATEST_3
GND_4
GND_11
GND_18
GND_25
NC_7
1
2
3
2
1
2
1
2
[17]
[17]
TPM@ C6
0.1U_0402_25V6K~D
PT
2
12
13
14
1
TPM@ C5
2200P_0402_50V7K~D
28
[17,38,42]
[17,38,42]
[17,38,42]
[17,38,42]
1
2 10K_0402_5%~D
TPM@ C4
2200P_0402_50V7K~D
1
SB3V
10
19
24
TPM@ C3
2200P_0402_50V7K~D
TPM@ R72
VCC_0
VCC_1
VCC_2
[17] CLK_PCIE_CD
[17] CLK_PCIE_CD#
[19]
[19]
[19]
[19]
PCIE_PRX_CARDTX_P4
PCIE_PRX_CARDTX_N4
PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
9
8
+3VS
@ R1 1
PP
USB20_P12
USB20_N12
CLK_PCIE_MINI3
CLK_PCIE_MINI3#
6
7
USB20_P4
USB20_N4
USB20_P2
USB20_N2
[19]
[19]
U1
2 4.7K_0402_5%~D
4
11
18
25
[19]
[19]
TPM@ AT97SC3204-X2A1D-AB_TSSOP28
USB3RP4
USB3RN4
[19]
[19]
USB3RP3
USB3RN3
[19]
[19]
USB3TN3
USB3TP3
[19]
[19]
USB3TP4
USB3TN4
PCIE_PTX_WLANRX_N3
PCIE_PTX_WLANRX_P3
[19]
[19]
PCIE_PTX_CARDRX_P4
PCIE_PTX_CARDRX_N4
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
USB2_DET_EC#
[38]
USB2_PWR_EN_EC
[38]
USB2_CTL1
[38]
USB_OC1#
[19]
USB_ILIM_SEL
[38,44]
USB3_DET_EC#
[38]
USB3_PWR_EN_EC
[38]
USB3_CTL1
[38]
MINI3CLK_REQ#
[17]
EC_WLAN_WAKE#
[38]
SUSCLK_R
[18,38]
BT_RADIO_DIS#
[20]
WL_OFF#
[18]
EN_WLANPWR#
[38]
PLT_RST#
CDCLK_REQ#
DMIC0_R
DMIC_CLK_R
D
[17]
PCH_SMLCLK
[17,25,35,38]
PCH_SMLDATA
[17,25,35,38]
SYSTEM_FAN2_PWM
[38]
SYSTEM_FAN2_FB
[38]
USB_D_PD#
[38,45]
PM_SLP_S3# [18,34,38,43,55,56]
CCD_INT#
[38]
PLT_RST#
1
2
QT
+3VALW
close JB1 33pin
+RTCBATT
+RTCBATT
+5VS
+5VALW
+3VS
+5VS
1
2
HRS_DF40HC(3P0)-90DS-0P4V(51)
2
C
1
2
@ CM22
1000P_0402_50V7K~D
1
2
1
2
1
2
CM32
4.7U_0603_6.3V6K~D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
CM31
0.047U_0402_16V4Z~D
+3VS
@ R2
33_0402_5%~D
JTB1
CM30
0.01U_0402_25V7K
CLK_PCI_TPM
[19]
[19]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
CM33
0.1U_0402_16V4Z~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
USB20_P3
USB20_N3
[19]
[19]
5
+3VS
1
C
@ C8
27P_0402_50V8J~D
PT
DMIC0
EMC@ RV424 1
2 0_0402_5%~D
DMIC0_R
2
1
[47]
Lid Switch
+3VALW
[47]
DMIC_CLK
EMC@ RV417 1
2 68_0402_1%~D
DMIC_CLK_R
@ R28
47K_0402_5%~D
2
FD1
FD2
@ FIDUCAL @ FIDUCIAL
Wedcam PWR CTRL
1
1
1
EMIST_SUL-12A2M_1P
@ H23
EMIST_SUL-12A2M_1P
@ H27
QT
1
1
EMIST_SUL-12A2M_1P
@ H17
EMIST_SUL-12A2M_1P
@ H21
1
EMIST_SUL-12A2M_1P
@ H20
1
H16
EMIST_SUL-12A2M_1P
@ H25
EMIST_SUL-12A2M_1P
@ H24
EMIST_SUL-12A2M_1P
@ H26
A
CPU x 4
H_2P1
@
1
1
H6
H_3P9
@
1
1
H_3P7
@
1
@ H5
H_4P1X3P7
ST
CLIP_C5
@ H28
CLIP_C5
@ H29
QT
1
PCH x 2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
1
1
H18
H4
@ H3
H_3P9
1
1
1
H_2P5
@
EMIST_SUL-12A2M_1P
@ H14
1
EMIST_SUL-12A2M_1P
@ H19
ST
1
H_3P3
@
1
1
H_2P1X2P5
@
FD3
FD4
@ FIDUCAL @ FIDUCIAL
H15
EMIST_SUL-12A2M_1P
@ H7
H10
A
B
1
H_2P5
@
H_3P3
@
H13
H_2P5
@
PT
C18
10P_0402_50V8J~D
H8
1
H12
1
H_2P3
@
[35,38]
1
H11
1
1
H9
H_2P3
@
LID_SW_IN#
GPU x 2
QT
@ CV754
10P_0402_50V8J~D
2
2
PCB x 9
H_2P3
@
LID_SW_IN#
1
Screw Hole
H2
3
1
C17
0.1U_0402_16V7K~D
B
VOUT
1
VDD
1
2
GND
U5
APX9131AAI-TRG_SOT23-3
1
2
1
1
+3VALW
@ CV753
10P_0402_50V8J~D
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CONN & LID
Size
Date:
5
4
3
2
Document Number
Rev
0.1
LA-9941P
Thursday, September 05, 2013
1
Sheet
40
of
62
5
4
3
2
1
Thermal sensor
D
D
+5VS
+3V_Thermal
Close JDIMM1
+5VS
SHDN
SET
2
2
5
1
MEM_TEMP1
1
OUT
[38]
GND
3
16.9K_0402_1%
RT3
MEM_TEMP0
HT1
HT3
100K_0402_1%_TSM0B104F4251RZ~D
100K_0402_1%_TSM0B104F4251RZ~D
4
1
NCT3705U-33_SOT23-5
CT21
0.01U_0402_16V7K~D
2
IN
2
16.9K_0402_1%
RT5
[38]
1
1
1
1
U4
+3V_Thermal
2
2
2
CT22
4.7U_0603_6.3V6K~D
CT44
1U_0402_6.3V6K
1
Close JDIMM2
+3V_Thermal
2
C
C
B
B
+3V_Thermal
+3V_Thermal
+3V_Thermal
16.9K_0402_1%
RT1
FAN_TEMP0
[38]
SKIN_TEMP0
[38]
SKIN_TEMP1
1
HT6
1
1
1
[38]
2
16.9K_0402_1%
RT6
1
FAN_TEMP1
1
16.9K_0402_1%
RT4
1
[38]
1
16.9K_0402_1%
RT2
2
2
2
+3V_Thermal
HT5
HT2
HT4
100K_0402_1%_TSM0B104F4251RZ~D
100K_0402_1%_TSM0B104F4251RZ~D
100K_0402_1%_TSM0B104F4251RZ~D
2
2
2
2
100K_0402_1%_TSM0B104F4251RZ~D
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Document Number
Custom LA-9941P
Date:
5
4
3
2
Compal Electronics, Inc.
Thermal Sensor EMC1412
Tuesday, September 03, 2013
1
Sheet
41
Rev
0.1
of
62
5
4
3
2
1
WLAN / BT4.0 PCIE Mini Card
D
D
C
C
+3VS
+3V_mSATA
@ JP12
mSATA SSD
2
1
1
[18,38,40,6,8] PLT_RST#
[17] CLK_PCI_DEBUG
[16]
[16]
[16]
[16]
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
[38]
[38]
CLK_PCI_DEBUG
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
EC_TX
EC_RX
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
A
2
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
LPC_LFRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME# [17,38,40]
LPC_AD3 [17,38,40]
LPC_AD2 [17,38,40]
LPC_AD1 [17,38,40]
LPC_AD0 [17,38,40]
2
1
2
1
2
CM14
4.7U_0805_10V6
JSSD
1
CM13
0.1U_0402_25V6K~D
1
CM12
0.047U_0402_16V7K
JUMP_43X39
+3V_mSATA
B
CM11
0.01U_0402_25V7K
+3V_mSATA
2
B
54
A
ACES_50711-0520W-001
CONN@
RM12 1
2 100K_0402_5%~D
EC_TX
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
Title
Compal Electronics, Inc.
WLAN/WWAN/SIM/BT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-9941P
Date:
5
4
3
2
Tuesday, September 03, 2013
Sheet
1
42
of
62
5
4
3
SATA III Re-driver for HDD
2
1
HDD CONN
JHDD
+3VS_RD
+3VS
PM_SLP_S3#
PM_SLP_S3#
+3VS_RD
STUN1
SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
1
2
SATA_PRX_DTX_P0_C
SATA_PRX_DTX_N0_C
5
4
@ RN10 1
@ RN11 1
2 0_0402_5%~D
2 0_0402_5%~D
SATA_BPRE1
SATA_APRE1
17
19
@ RN12 1
HDDT@ RN13 1
2 0_0402_5%~D
2 0_0402_5%~D
SATA_TEST
18
3
13
21
VDD
VDD
A_INp
A_INn
B_OUTp
B_OUTn
B_PRE1
A_PRE1
NC
REXT
A_PRE0
B_PRE0
A_OUTp
A_OUTn
TEST
GND
GND
EPAD
B_INp
B_INn
6
16
1
2
[16]
[16]
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
2
+3VS
[20]
HDD_DETECT#
HDD_DETECT#
DEW2
DEW2
@ RN21 1
+5VS_HDD
2 0_0402_5%~D
ST
FFS_INT2_Q
+3VS_RD
10
20
REXT_SATA
9
8
SATA_APRE0
SATA_BPRE0
15
14
SATA_PTX_DRX_P0_RC
SATA_PTX_DRX_N0_RC
CN12
CN13
1
1
2 0.01U_0402_16V7K~D
2 0.01U_0402_16V7K~D
SATA_PTX_DRX_P0_RC1
SATA_PTX_DRX_N0_RC1
11
12
SATA_PRX_DTX_P0_RC
SATA_PRX_DTX_N0_RC
CN8
CN9
1
1
2 0.01U_0402_16V7K~D
2 0.01U_0402_16V7K~D
SATA_PRX_DTX_P0_RC1
SATA_PRX_DTX_N0_RC1
@ RN3
@ RN4
1
1
2 0_0402_5%~D
2 0_0402_5%~D
1
1
2 0.01U_0402_16V7K~D
2 0.01U_0402_16V7K~D
SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
CN11
CN10
1
1
2 0.01U_0402_16V7K~D
2 0.01U_0402_16V7K~D
SATA_PRX_DTX_P0_C
SATA_PRX_DTX_N0_C
+3VS
+5VS_HDD
2
CN19
CN18
D
Place near HDD CONN (JHDD1)
+3VS_RD
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
GND
GND
GND
J-L_UCNR2234B020-0
CONN@
RN16
0_0402_5%~D
1
1
[16]
[16]
HDDT@
CN29
0.1U_0402_25V6K~D
2
PI3EQX6741STZDEX TQFN 20P _4X4
SN75LVCP601
1
CN28
0.01U_0402_16V7K~D
1
2
1
2
@ RN42 1
@
RN17
0_0402_5%~D
4,38,40,55,56]
ST
HDDP@ UN1
2 0_0402_5%~D
7
EN
@
RN18
0_0402_5%~D
D
2
CN2
0.1U_0402_25V6K~D
RN19
0_0402_5%~D
2
SATA_PRX_DTX_N0_RC1
SATA_PRX_DTX_P0_RC1
@JP13
PAD-OPEN1x1m
1
2
1
CN1
0.01U_0402_16V7K~D
+3VS_RD
+3VS_RD
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SATA_PTX_DRX_P0_RC1
SATA_PTX_DRX_N0_RC1
+3VS
2
1
CN3
0.1U_0402_16V7K~D
2
1
CN4
1000P_0402_50V7K~D
2
1
CN5
0.1U_0402_16V7K~D
2
1
CN6
1U_0402_6.3V6K~D
2
CN7
10U_0805_10V6M~D
1
REXT_SATA
@ RN40
4.99K_0402_1%~D
C
HDDP@ RN14 1
2 0_0402_5%~D
SATA_BPRE1
SATA_APRE0
@ RN15 1
2 0_0402_5%~D
SATA_APRE1
SATA_BPRE0
1
2 0_0402_5%~D
@ RN20 1
2 0_0402_5%~D
HDDP@ RN6
2
ST
C
Free Fall Sensor
HDD power control for AOAC
+5VS
1300mA
+3VS
+5VALW
1
ST
RN26
100K_0402_5%~D
2
[14,15,17,39,6]
[14,15,17,39,6]
FFS_INT1
FFS_INT2
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA
PCH_SMBCLK
7
6
4
8
INT 1
INT 2
GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC
10
13
15
16
4
5
6
11
9
VOUT
+5VS_HDDAPL
VIN
2
2
1
1
JUMP_43X118
GND
2
SS
EN
3
G5243AT11U_SOT23-5
QN2B
DMN66D0LDW-7_SOT363-6~D
5
12
PM_SLP_S3#
FFS_INT2
2
2
3
QN2A
DMN66D0LDW-7_SOT363-6~D
1
[18]
[20]
FFS_INT1
FFS_INT2
RES
RES
RES
RES
1
LNG3DM
VDD_IO
VDD
2
FFS_INT2_Q
4
CN34
1U_0603_10V6K~D
+5VS_HDD
@ JP15
1
2
UN2
1
14
1
2
CN15
0.1U_0402_25V6K~D
3
2
1
1
CN14
10U_0603_6.3V6M~D
5
RN23
100K_0402_5%~D
+3VS
1
UN3
RN30
100K_0402_5%~D
2
LNG3DMTR_LGA16_3X3~D
+3VS
B
B
RN33 1
2 100K_0402_5%~D
FFS_INT1
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
Document Number
Custom
4
3
2
Rev
0.1
LA-9941P
Date:
5
Compal Electronics, Inc.
DC/DC INTERFACE
Sheet
Tuesday, September 03, 2013
1
43
of
62
5
4
3
2
1
USB Powershare
+5VALW
+5VALW
RI19
D
1
2 10K_0402_5%~D
RE63 1
2 100K_0402_5%~D
USB0_CTL1
RE62 1
2 100K_0402_5%~D
CTL2/3_1
+5V_CHGUSB_1
2
CI24
0.1U_0402_25V6K~D
US1
1
[19]
1
2 10K_0402_5%~D
USB0_PWR_EN_EC
USB_OC0#
USB_OC0#
[19]
[19]
+3VALW
RI17
2.1A
1
PWRSHARE_OE#1
USB_ILIM_SEL
USB0_PWR_EN_EC
USB0_CTL1
CTL2/3_1
OUT
FAULT# STATUS#
2
3
USB20_N0
USB20_P0
[38,40] USB_ILIM_SEL
[38] USB0_PWR_EN_EC
[38]
IN
13
DM_OUT
DP_OUT
4
5
DM_IN
DP_IN
ILIM_SEL ILIM_LO
EN
ILIM_HI
6
7
8
CTL1
CTL2
CTL3
GND
GPAD
12
9
PWRSHARE_OE#1
11
10
USBP0_DUSBP0_D+
15
16
ILIM_LO1 R47
ILIM_HI1 R48
D
USBP0_D- [45]
USBP0_D+ [45]
1
1
2 48.7K_0402_1%
2 22.1K_0402_1%
14
17
TPS2546RTER_QFN16_3X3
C
RI30
C
+5VALW
+5VALW
1
2 10K_0402_5%~D
2 100K_0402_5%~D
CTL2/3_3
RE65 1
2 100K_0402_5%~D
USB1_CTL1
2
CI26
0.1U_0402_25V6K~D
1
2 10K_0402_5%~D
US2
1
USB_OC0#
[19]
[19]
+3VALW
RI32
2.1A
1
PWRSHARE_OE#3
RE68 1
+5V_CHGUSB_3
USB1_PWR_EN_EC
[38]
USB1_PWR_EN_EC
[38]
13
2
3
USB20_N1
USB20_P1
USB_ILIM_SEL
USB1_PWR_EN_EC
USB1_CTL1
CTL2/3_3
4
5
6
7
8
IN
OUT
FAULT# STATUS#
DM_OUT
DP_OUT
DM_IN
DP_IN
ILIM_SEL ILIM_LO
EN
ILIM_HI
CTL1
CTL2
CTL3
GND
GPAD
12
9
PWRSHARE_OE#3
11
10
USBP1_DUSBP1_D+
15
16
ILIM_LO3 R52
ILIM_HI3 R51
USBP1_D- [45]
USBP1_D+ [45]
1
1
2 48.7K_0402_1%
2 22.1K_0402_1%
14
17
TPS2546RTER_QFN16_3X3
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
USB Powershare
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
44
of
62
5
4
3
2
USB3.0 Re-driver
+3VALW
1
+3V_PS8723
2 0_0805_5%
2
1
CI27
CI50
1
0.1U_0402_10V7K~D
ST
D
ST
+3V_PS8723
2
UI5USBP@
0.01U_0402_16V7K~D
@ RI74
1
ST
[19]
[19]
USB3RN1
USB3RP1
USB3RN1 CI5 1
USB3RP1 CI6 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
USB3RN1_C
USB3RP1_C
[19]
[19]
USB3TN1
USB3TP1
USB3TN1 CI7 1
USB3TP1 CI8 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
[19]
[19]
USB3RN2
USB3RP2
USB3RN2 CI111
USB3RP2 CI121
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
USB3TN1_C
USB3TP1_C
I2C_EN8723
USB3RN2_C
USB3RP2_C
USB3TN2
USB3TP2
USB3TN2 CI131
USB3TP2 CI201
+3V_PS8723
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
USB3TN2_C
USB3TP2_C
[19]
[19]
[38,40]
USB_D_PD#
B_EQ0
B_EQ1
B_DE0
B_DE1
UI5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A1_OUTn
A1_OUTp
GND
B1_INn
B1_INp
I2C_EN
A2_OUTn
A2_OUTp
VDD
B2_INn
B2_INp
PD#
B_EQ0/SDA_CTL
B_EQ1/SCL_CTL
B_DE0
B_DE1
EPAD
A_EQ0
A_EQ1
REXT
A_DE0
A_DE1
A1_INn
A1_INp
VDD
B1_OUTn
B1_OUTp
TEST
A2_INn
A2_INp
GND
B2_OUTn
B2_OUTp
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A_EQ0
A_EQ1
1
RI320
A_DE0
A_DE1
USB3RN1_8723
USB3RP1_8723
USB3TN1_8723
USB3TP1_8723
USB8723_test
USB3RN2_8723
USB3RP2_8723
A_EQ0USBN@ RI460 1
A_EQ1USBN@ RI461 1
2 0_0402_5%~D
2 0_0402_5%~D
B_EQ0
@ RI464 1
B_EQ1USBN@ RI465 1
2 4.7K_0402_5%~D
2 0_0402_5%~D
@ RI462 1
@ RI463 1
2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
@ RI467 1
@ RI466 1
2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
@ RI468 1
2 4.7K_0402_5%~D
+3V_PS8723
2 4.99K_0402_1%~D
+3V_PS8723
I2C_EN8723 RI6 1
D
+3V_PS8723
A_DE0
A_DE1
+3V_PS8723
USB3TN2_8723
USB3TP2_8723
B_DE0
B_DE1
2 0_0402_5%~D
USB8723_test
LFPS swing adjust.
3.3V tolerant. Internally pulled down at ~150KΩ.
TST ==
L: Normal LFPS swing (default)
H: Tune down LFPS swing
USBN@
[44]
USBP0_D-
[44]
USBP0_D+
EMC@ LI1
DLW21SN900HQ2L_0805_4P~D
3
4
3
USBP0_D-
4
USBP0_D+
1
2
C
USBP0_R_D+
2
USB3TP1_D+
2 2
9 8
USB3RP1_D+
USB3TN1_D-
4 4
7 7
USB3TN1_D-
USB3TP1_D+
5 5
6 6
USB3TP1_D+
3 3
1
1
CI1
2
2
8
EMC@ LI3
DLW21SN900HQ2L_0805_4P~D
4
3
4
3
USB3RN1_8723
1
USB3RP1_8723
1
2
2
USB3RN1_DUSB3RP1_D+
1
2
USBP0_R_DUSB3RP1_D+
3
2
USB3RP1_D+
USB3TN1_DUSBP0_R_D+
2
1
USB3RN1_D-
3
1
JUSB1
USB3TP1_D+
10 9
EMC@ DI2
AZC199-02SPR7G_SOT23-3
USB3T_P1
0.1U_0402_10V7K~D
EMC@ DI1
1 1
2
2
USB3RN1_DUSB3TN1_D-
CI2
0.1U_0402_25V6K~D
1
CI4
4
CI19
10U_0805_10V6K~D
CI3
EMC@ LI2
DLW21SN900HQ2L_0805_4P~D
3
4
3
USB3T_N1
0.1U_0402_10V7K~D
1
2
1
1
USB3TP1_8723
2
+5V_CHGUSB_1
ST
USB3TN1_8723
1
USB3.0 / USB2.0 Port1
USBP0_R_D-
47U_1206_6.3V6M~D
C
Programmable output de-emphasis level setting for channel A1&A2/B1&B2
3.3V tolerant. Internally pulled down at ~150KΩ
[DE1, DE0] ==
LL: 3.5dB de-emphasis (default)
LH: No de-emphasis
HL: 2.7dB de-emphasis
HH: 5.0dB de-emphasis
+3V_PS8723
PS8723BTQFN32GTR-A0_TQFN32_3X6
PTN36242LBS HVQFN
Equalizer control and program for channel A1&A2/B1&B2
3.3V tolerant. Internally pulled down at ~150KΩ
[EQ1, EQ0] ==
LL: equalization for channel loss up to 9.5dB (default)
LH: equalization for channel loss up to 13 dB
HL: equalization for channel loss up to 4.5dB
HH: equalization for channel loss up to 7.5dB
AZ1045-04F_DFN2510P10E-10-9
Place close to JUSB1
[38]
USB0_DET_EC#
USB3RN1_DUSB0_DET_EC#
9
1
8
3
7
2
6
4
5
10
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRXPlug_DET
GND
GND
GND
GND
11
12
13
14
TAIWI_USB019-107CRL-TWD
CONN@
B
B
USB3.0 / USB2.0 Port3
2
USBP1_R_D+
+5V_CHGUSB_3
USB3RN2_D-
1
CI17
2
USB3T_N2
0.1U_0402_10V7K~D
USB3T_P2
0.1U_0402_10V7K~D
1
1
2
USB3RP2_D+
2 2
9 8
USB3RP2_D+
USB3TN2_D-
4 4
7 7
USB3TN2_D-
USB3TP2_D+
5 5
6 6
USB3TP2_D+
USB3TN2_D-
2
USB3TP2_D+
3 3
8
USB3TN2_DUSBP1_R_D+
1
1
CI9
2
2
1
2
USBP1_R_DUSB3RP2_D+
EMC@ LI9
DLW21SN900HQ2L_0805_4P~D
3
4
3
USB3RN2_8723
4
USB3RP2_8723
1
1
2
USB3RN2_D-
2
1
AZ1045-04F_DFN2510P10E-10-9
A
Place close to JUSB3
[38]
USB1_DET_EC#
USB3RN2_DUSB1_DET_EC#
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRXPlug_DET
GND
GND
GND
GND
11
12
13
14
TAIWI_USB019-107CRL-TWD
CONN@
A
USB3RP2_D+
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
2012/07/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
9
1
8
3
7
2
6
4
5
10
USB3TP2_D+
EMC@ DI5
AZC199-02SPR7G_SOT23-3
2
USB3RN2_D-
CI15
0.1U_0402_25V6K~D
USB3TP2_8723
1
CI16
JUSB3
10 9
CI23
10U_0805_10V6K~D
ST
USB3TN2_8723
EMC@ LI8
DLW21SN900HQ2L_0805_4P~D
4
3
4
3
EMC@ DI6
1 1
3
1
USBP1_R_D-
2
3
1
2
USBP1_D+
2
USBP1_D+
USBP1_D-
1
[44]
USBP1_D-
47U_1206_6.3V6M~D
[44]
EMC@ LI7
DLW21SN900HQ2L_0805_4P~D
4
3
4
3
4
3
2
USB conn.
Document Number
Rev
0.1
LA-9941P
Tuesday, September 03, 2013
Sheet
1
45
of
62
5
4
3
2
1
HD Audio DSP
1
DSP@ LA3
2 4.7UH_NRH3010T4R7MN_20%
+1.2V_5505SWR
30mil
30mil
2
CA40/CA43 close pin1
CA41/CA44 close pin25
CA42/CA45 close pin37
D
GND_DSP
Close to Pin 13
2
1
DSP@ CA63
0.1U_0402_16V7K~D
2
1
DSP@ CA80
0.1U_0402_16V7K~D
1
1
DSP@ CA83
0.1U_0402_16V7K~D
1
2
DSP@ CA84
4.7U_0603_6.3V6K~D
1
2
DSP@ CA64
4.7U_0603_6.3V6K~D
2
2
DSP@ CA78
4.7U_0603_6.3V6K~D
1
1
DSP@ CA81
0.1U_0402_16V7K~D
2
DSP@ CA82
4.7U_0603_6.3V6K~D
2
DSP@ CA66
10U_0805_10V6K~D
1
D
+2.5V_5505LDO_S
+3VS
DSP@ CA90 1
210U_0805_10V6K~D
9
15
13
+1.2V_5505SWR
+1.2V_5505SWR_S
DVDD-33-LDO-I
FB-SWR
DVDD-12-SWR
ALC5505
DVDD-25-LDO-O
DDR-VERF
MCLKO
I2SCLKO
I2SCLRCKO
I2SSDO0
I2SCLKI
I2SLRCKI
I2SSDI0
DSP-PD#
HDA_SDIN0
When not support DSP, RA13 change to 0ohm
When support DSP, RA13 change to 33ohm
6
5
8
10
11
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN0_C
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
DSP@ RA81 1
[16]
[16,47]
2 33_0402_5%~D
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
45
46
47
48
PT
RA81
2
3
XTAL_5505_IN
XTAL_5505_OUT
12
44
49
0_0402_5%~D
NDSP@
BITCLK/I2SCLKI-2
SDTA-OUT/I2SSDO0-2
SDATA-IN/I2SSDI0-2
SYNC/I2SLRCLKI-2
RESETB
BITCLK-V/MCLKI-2
SDATA-OUT-V/I2SSDO1
VGPIO1/SDATA-IN-V/I2SSDI3
SYNC-V/I2SSDO2
RESETB-V/I2SSDO3
VDMIC-CLK2/I2SSDI1
VDMIC-DAT2/I2SSDI2
VGPIO0/TRST#
VGPIO2/TMS
VGPIO3/VOL-DN/TDI
VGPIO4/VOL-UP/TCLK
VGPIO5/VOL-MUTE/TDO
VDIMC-CLK1
VDMIC-DAT1
XTAL-IN
XTAL-OUT
I2C-MASTER-SCL/I2C-SLAVE-SCL
I2C-MASTER-SDA/I2C-SLAVE-SDA
CS-L
SCK
SI
SO
DVSS-SWR
DVSS
DGND
GND_DSP
GND_DSP
Close pin14
Close pin16
1
2
1
2
Close pin42
14
16
42
32
29
30
31
+3VS
38
39
41 DSP@ RA75 1
2 10K_0402_5%~D
17
DSP_PD#
23
24
21
19
18
HDA_BITCLK_5505
HDA_SDOUT_5505
HDA_SDIN_5505
HDA_SYNC_5505
HDA_RST_5505
HDA_SDOUT_5505
[47]
HDA_SDIN_5505
[47]
HDA_SYNC_5505
[47]
HDA_RST_5505
[47]
C
[38]
7
28
4
20
22
DSP_PD#
DSP_PD#
When DSP_ON/OFF is high,trun on DSP.
When DSP_ON/OFF is low,trun off DSP.
Recommend : DSP set power up/down state when HD-A should be in D3Cold.
26
27
33
34
35
36
HDA_BITCLK_5505
ALC5505_QFN48_7X7~D
GND_DSP
HDA_BITCLK_5505
[47]
@ RA76
0_0402_5%~D
2
[16]
[16]
[16]
C
2
DSP@ RA91
10K_0402_5%~D
43
40
+2.5V_5505LDO_S
DDR_VREF_IN
DVDD-33-SWR-C
DVDD-IO
1
1
+3VS
DVDD-33-SWR
2
1
2
2
1
Close to Pin 40
DVDD-12-I
DVDD-12-I
DVDD-12-I
1
DSP@ CA86
10U_0805_10V6K~D
1
25
37
2
DSP@ CA89
0.1U_0402_16V7K~D
DSP@ U12
+1.2V_5505SWR
1
30mil
DSP@ CA85
10U_0805_10V6K~D
2
DSP@ CA65
0.1U_0402_16V7K~D
DSP@ RA59
20K_0402_1%~D
1
2
DSP@ CA87
0.1U_0402_16V7K~D
1
DDR_VREF_IN
+3VS
30mil
DSP@ CA88
10U_0805_10V6K~D
2
+3VS
30mil
DSP@ CA92
0.1U_0402_16V7K~D
1
1
DSP@ CA77
0.1U_0402_16V7K~D
2
DSP@ CA67
10U_0805_10V6K~D
1
DSP@ RA62
20K_0402_1%~D
2
DSP@ CA79
0.1U_0402_16V7K~D
1
2
+1.2V_5505SWR_S
1
PT
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN0_C
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
NDSP@
NDSP@
NDSP@
NDSP@
NDSP@
1
1
1
1
1
RA50
RA63
RA56
RA57
RA58
2
2
2
2
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
HDA_BITCLK_5505_R
HDA_SDOUT_5505_R
HDA_SDIN_5505_R
HDA_SYNC_5505_R
HDA_RST_5505_R
NDSP@
NDSP@
NDSP@
NDSP@
NDSP@
RA67
RA68
RA64
RA65
RA66
1
1
1
1
1
2
2
2
2
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
HDA_BITCLK_5505
HDA_SDOUT_5505
HDA_SDIN_5505
HDA_SYNC_5505
HDA_RST_5505
2
@ CA91
22P_0402_50V8J~D
When not support DSP, need POP
HDA_SYNC_AUDIO
XTAL_5505_IN
XTAL_5505_OUT
HDA_BITCLK_AUDIO
B
DSP@ YA2
24MHZ_12PF_X3G024000DC1H
1
3
2
4
2
DSP@ CA93
10P_0402_50V8J~D
1
1
B
2
1
2
2
1
@ CA95
10P_0402_50V8J~D
2 0_0805_5%~D
@ RA89
0_0402_5%~D
1
HDA_SDOUT_AUDIO
GND_DSP and GND moat 20mil
DSP@ RA90 1
2
DSP@ CA96
18P_0402_50V8J~D
1
DSP@ CA97
18P_0402_50V8J~D
GND_DSP
2
@ CA94
22P_0402_50V8J~D
Green Clock
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/25
2012/07/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Date:
5
4
3
2
Compal Electronics, Inc.
RTC Counter/Green Clock
Size
Document Number
Custom
Rev
Wednesday, September 04, 2013
Sheet
1
46
of
62
A
B
C
D
E
F
G
H
HDA_Audio Codec
+VDDA
+5VS
@ RA33
0_0402_5%
1
2
LA1 1
+3VS
+VDDA
1
+3VS
2
2 BLM21PG600SN1D_0805~D
1
2
1
2
2
1
1
2
1
2
2
CA13
0.1U_0402_16V7K~D
1
CA12
10U_0805_10V6K~D
2
CA11
4.7U_0603_6.3V6K~D
2
CA10
0.1U_0402_16V7K~D
1
CA9
0.1U_0402_16V7K~D
2
CA8
4.7U_0603_6.3V6K~D
1
CA7
0.1U_0402_16V7K~D
CA5
10U_0805_10V6K~D
2
CA6
0.1U_0402_16V7K~D
1
1
1
CA4
0.1U_0402_16V7K~D
+3VS
CA3
10U_0805_10V6K~D
ST
+3VS
1
PT
RA9 1
2 47K_0402_5%~D
RA10 1
2 47K_0402_5%~D
RA11 1
2 1K_0402_5%~D
BEEP#
EC Beep
[38]
U15
RA24 1
2 22_0402_1%~D
HDA_SDIN_R
RA26 1
2 33_0402_5%~D
HDA_BITCLK_R
8
4
5
9
6
1
29
30
MIC2_VREF
+MIC1_VREFO
MIC1_VREF
1
EMC@ CA39
Close to Chip Side
2
HDA_BITCLK_R
22P 50V +-5% NPO 0402
2
CA15 1
RA7 1
AGND
CA16 1
2
CA26
24
21
35
40
41
38
2 1U_0402_6.3V6K
2 20K_0402_1%~D
LDO_OUT
2 2.2U_0603_10V6K
+
JP10
CA18
10U_0805_10V6K
2
1
CA19
0.1U_0402_16V7K~D
1
AGND
1
100U_B2_6.3VM_R35M
2 1U_0402_6.3V6K
2 10U_0805_10V6K
20
10
28
22
42
1
AGND
49
PAD-OPEN 43x39
2
JP8
MIC1-R
MIC1-L/MIC-CAP
MIC2-R
MIC2-L
SENSE A
SENSE B
SURR-R
SURR-L
CEN
LFE
CBP
CBN
JDREF
LDO-CAP
VREF
VRP
FRONT-R
FRONT-L
SPDIF-OUT
SPDIF-in
CPVEE
REGREF
GPIO/DMIC-CLK
GPIO1/DMIC-DATA
GPIO2/Combo-Jack1
GPIO3/Combo-Jack2
CPVREF
AVSS1
AVSS2
Thermal PAD
EAPD
@
2
1
AGND
@ CA17 1
MONO_IN
2 1U_0402_6.3V6K
HDA_SPKR
PT
37
36
48
47
SLEEVE
RING2
34
33
2 10U_0805_10V6K
SPK_LC+
PT
[48]
1
2
AGND
1
RA22
SENSE_B#
10mil
27
26
19
18
PCI Beep
[16]
1 100P_0402_25V8K
PT
@RA5
4.7K_0402_5%~D
CA14 1
MIC2R
MIC2L
CA30 2
@CA32
100P_0402_25V8K
PT
JACK_PLUG#_DL_R
JACK_PLUG#_DL
Close to U2 pin33
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO
PT
CA20 1
CA21 1
AGND
@
2
SDATA-IN
SDATA-OUT
BCLK
SYNC
RESETB
2
46
45
32
31
2
5.1K_0402_1%~D
1
HP2_OUTR
HP2_OUTL
S
2
G
QA5
SSM3K7002FU_SC70-3~D
2
JACK_PLUG#_DL_R
D
@CA31
10U_0805_10V6K
Combo JACK
AGND
44
43
CA24 1
CA25 1
AUD_SPK_RC_R+_C
AUD_SPK_RC_L+_C
2 1U_0402_16V6K
2 1U_0402_16V6K
AUD_SPK_R+
AUD_SPK_L+
[48]
[48]
15
16
12
13
17
3
DMIC_CLK_RA
DMIC0_RA
1
RA961 EMC@
RA97 EMC@
2
20_0402_5%~D
0_0402_5%~D
DMIC_CLK
DMIC0
DMIC_CLK
[40]
DMIC0 [40]
DMIC_CLK
1
HDA_SDIN_5505
HDA_SDOUT_5505
HDA_BITCLK_5505
HDA_SYNC_5505
HDA_RST_5505
[46] HDA_SDIN_5505
[46] HDA_SDOUT_5505
[46] HDA_BITCLK_5505
[46] HDA_SYNC_5505
[46] HDA_RST_5505
DVDD
DVDD-IO
DVDD-IO-CP
LINE1-R
LINE1-L
LINE2-IN-R/SLEEVE
LINE2-IN-L/RING2
1
11
7
25
PCBEEP
HVDD
LDO-IN
14
EAPD#
EAPD#
EMC@ CA27
10P_0402_50V8J~D
[38]
2
2
23
39
3
AGND
2
AGND
1
AGND
ALC3661-CG_MQFN48_6X6~D
DMIC0
@
EMC@ CA23
10P_0402_50V8J~D
1
PAD-OPEN 43x39
2
JP9
1
PAD-OPEN 43x39
2
Close to U2
AGND
GND
Prevent S3/S4/S5 Noise
Reserved Delay Circuit
For De-pop noise
1
+3VS
+3VS
6
2
6
1
1
3
2 100K_0402_5%~D
1
1
5
JACK_PLUG#
QA3B
DMN66D0LDW-7_SOT363-6~D
1
@ RA99
1
MUTE#
@ RA100
EAPD#
@ RA55 1
5
@ QA4B
DMN66D0LDW-7_SOT363-6~D
2
2
1
2
2
3
QA3A
DMN66D0LDW-7_SOT363-6~D
@ UA2
MAX9892ERT+T_UCSP6~D
JACK_PLUG#_DL
@
[48]
@ QA4A
DMN66D0LDW-7_SOT363-6~D
MUTE#
HP2_OUTL_R
A1
HP2_OUTR_R
2
0_0402_5%~D
2
0_0402_5%~D
A3
B1
B3
INL
INR
/MUTE
2
1
+3VS
VDD
SET
B2
2
GND
2
0_0402_5%~D
2
4
2 0_0402_5%
4
2
1
@ RA101 1
1
MUTE#
@ RA102
@ RA44
100K_0402_5%~D
@
CA22
0.1U_0402_16V7K~D
HDA_RST_AUDIO#
RA43
100K_0402_5%~D
RA42
10K_0402_5%~D
ST
[16,46]
@ RA54
100K_0402_5%~D
SLEEVE
+3VS
@ CA28
0.1U_0402_16V7K~D
@ CA29
0.1U_0402_16V7K~D
1
A2
+RTCVCC
PT
AGND
3
3
AGND
AGND
AGND
AGND
@ RA98 1
2 0_0402_5%
ST
HeadPhone / Mic. combo JACK
HeadPhone / Mic. combo JACK
MIC1_VREF
MIC2L
MIC2R
1
CA68
1
CA69
2
2.2U_0603_10V6K
2
2.2U_0603_10V6K
MIC2L_C
MIC2R_C
2
2.2K_0402_5%~D
1
2.2K_0402_5%~D
2
1K_0402_5%~D
2
1K_0402_5%~D
@ RA2
1
2 10K_0402_1%~D
@ RA3
1
2 10K_0402_1%~D
PT
+3VS
AGND
PT
2
1
RA93
2
RA95
1
RA92
1
RA94
MIC2_VREF
RA4
10K_0402_1%~D
HP2_OUTL
1
PT
1
2
1
2
RA18
HP2_OUTR
8.2_0402_1%~D
RA17
8.2_0402_1%~D
1
LA5 EMC@
1
LA6 EMC@
2
BLM15GA750SN1D_2P
2
BLM15GA750SN1D_2P
HP2_OUTL_R
JHP2
3
1
HP2_OUTR_R
5
6
2
4
7
JACK_PLUG#
RING2
2
3
2
SINGA_2SJ3080-000111F
RA70
100K_0402_5%~D
1
AGND
2
1
CA37
@
1
CA34
@
CA33
@
CA38
@
1
3
1
SLEEVE
2
EMC@ DA2
PJDLC05_SOT23-3
1
2
1
2
100P_0402_25V8K
4
2
100P_0402_25V8K
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
100P_0402_25V8K
1
RA19
1
RA20
100P_0402_25V8K
+MIC1_VREFO
CONN@
PT
wait symbol and PN.
EMC@ DA3
PJDLC05_SOT23-3
AGND
4
PT
For ESD
AGND
AGND
Compal Secret Data
Security Classification
2011/08/25
Issued Date
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Date:
A
B
C
D
E
F
Compal Electronics, Inc.
HD Audio ALC275/Audio Jack
Size
Document Number
Custom
G
Tuesday, September 03, 2013
Rev
47
Sheet
H
of
62
A
B
C
D
E
Audio AMP
+VSBP
@ RA53 1
2 0_0805_5%
ST
RA47 1
2 10_0805_5%~D
+VSBP_AMP_AVCC
+VSBP_AMP_PVCC
1
2
1
2
1
2
Close to UA5 pin3,pin4,pin11,pin12
[47]
AUD_SPK_L+
RA45
1
2 60.4K_0402_1%~D
1
AUD_SPK_L+_R
AGND
RA46 1
2
1U_0603_25V6-K~D
CA71
2
10U_0805_25V6K
CA43
1
10U_0805_25V6K
CA46
2
10U_0805_25V6K
CA45
1
100P_0402_25V8K
CA42
2
100P_0402_25V8K
CA41
1
1
AGND
2
1
UA5
7
15
16
27
28
[47]
SPK_LC+
CA53
1
AUD_SPK_L-_R
30K_0402_1%
CA58
AVCC
BSPL
PVCCR
PVCCR
PVCCL
PVCCL
PT
3
SPK_LC+
0.022U_0402_25V7K
2
SPK_LC0.022U_0402_25V7K
4
ST
OUTPL
OUTNL
BSNL
RA48
1
2 60.4K_0402_1%~D
ST
1
RA51 1
ST
2
2
LINN
BSPR
SPK_RC+
0.022U_0402_25V7K
2
SPK_RC0.022U_0402_25V7K
CA59
1
AUD_SPK_R-_R
30K_0402_1%
CA60
RA52
60.4K_0402_1%~D
12
11
5
6
SPK_OUT_L+
RINP
OUTNR
RINN
BSNR
GAIN0
PBTL
GAIN1
PLIMIT
CA61 1
23
SPK_OUT_L-
22
SPKL-
2 0.22U_0603_16V7K
EMC@ LA11 1
2 BLM18PG181SN1D_2P SPK_L+
1
2 BLM18PG181SN1D_2P SPK_L-
EMC@ LA8
1
2
CA62
0.22U_0603_16V7K
CA72 1
2 0.22U_0603_16V7K
17
SPKR+
18
SPK_OUT_R+
EMC@ LA7
1
2 BLM18PG181SN1D_2P SPK_R+
20
SPK_OUT_R-
EMC@ LA9
1
2 BLM18PG181SN1D_2P SPK_R-
21
SPKR-
1
CA73
2
0.22U_0603_16V7K
14
10
1
2
2
RA49
60.4K_0402_1%~D
1
AUD_SPK_R+_R
AGND
1
AUD_SPK_R+
SPKL+
25
LINP
OUTPR
[47]
26
2
13
29
+5VS
GVDD
FAULT#
NC
GND
PGND
PGND
AGND
9
RA61
10K_0402_1%~D
24
19
8
1
SD#
1
RA60
10K_0402_1%~D
1
TPA3113D2PWPR_HTSSOP28
CA76
1U_0603_25V6-K~D
2
CA75
1U_0603_25V6-K~D
1
2
2
2
2
2
1
MUTE#
AGND
RZ38
100K_0402_5%~D
1
D
S
2
G
AUD_MUTE
3
QA2
L2N7002WT1G
[38]
3
2
AGND
MUTE#
[47]
3
Int. Speaker Conn.
40mil = For 4ohm 2W Speaker
2
PJDLC05C_SOT23-3
3
DA5
@
1
2
3
DA4
@
1
PJDLC05C_SOT23-3
1
2
1
2
1
2
2
EMC@ CA57
680P_0603_50V7K
EMC@ CA56
680P_0603_50V7K
EMC@ CA55
680P_0603_50V7K
EMC@ CA54
680P_0603_50V7K
1
SPK_L+
SPK_LSPK_R+
SPK_R-
JSPK1
1
2 1
3 2
4 3
5 4
6 G1
G2
ACES_50224-00401-001
CONN@
For ESD
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
4
2011/08/25
2012/07/21
Deciphered Date
Title
Speaker/Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Tuesday, September 03, 2013
LA-9941P
Sheet
E
Rev
0.1
48
of
62
4
2 820_0402_5%~D BAT5
2
D
Q16B
1
4
D
EMC@ D8
PESD24VS2UT_SOT23-3~D
S
4
6
D
1
S
Q16A
[38]
DMN66D0LDW-7_SOT363-6~D
SW2
2
NTC311-EA1T-A160T_4P
D
DMN66D0LDW-7_SOT363-6~D
S
2
G
BATT_LED#_LV5
3
BATBTN#
5
G
4
6
1
[38]
D
BAT3
[38]
DMN66D0LDW-7_SOT363-6~D
Q15A
2 820_0402_5%~D
2
2
3
Q15B
1
R21
100K_0402_5%~D
5
G
D
R19
IBAT3
R20
100K_0402_5%~D
2
2
BATT LED Power Button
3
1
R12
100K_0402_5%~D
1
1
1
IBAT5 R10
R11
100K_0402_5%~D
2
+5VALW
1
1
+5VALW
3
BATT LED
3
1
5
S
2
G
BATT_LED#_LV3
DMN66D0LDW-7_SOT363-6~D
+5VALW
1
1
+5VALW
IBAT2 R16
1
2 820_0402_5%~D
R26
100K_0402_5%~D
BAT2
R25
100K_0402_5%~D
1
2 820_0402_5%~D
BAT4
[38]
1
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
D
2 820_0402_5%~D
27-21-T3D-CP1Q2B16Y-3C_WHITE
2
27-21-T3D-CP1Q2B16Y-3C_WHITE
BAT5
LED6 1
2
27-21-T3D-CP1Q2B16Y-3C_WHITE
R34
100K_0402_5%~D
BAT1
R33
100K_0402_5%~D
3
BATT_LOW
Q20B
1
2 820_0402_5%~D
BATT_LOW_LED#_D
+5VALW
D
Yellow
DMN66D0LDW-7_SOT363-6~D
2
BAT1
S
2
G
BATT_LOW_LED#
S
D
4
Q20A
6
DMN66D0LDW-7_SOT363-6~D
S
1
BATT_LOW_LED#_D
1
D
R24
5
G
4
6
2
LED9 1
C
D
[38]
1
LED8 1
BAT4
2
1
2
R23
2
IBAT1
2
G
DMN66D0LDW-7_SOT363-6~D
BAT3
S
DMN66D0LDW-7_SOT363-6~D
Q19A
27-21-T3D-CP1Q2B16Y-3C_WHITE
1
1
1
1
2
R27
100K_0402_5%~D
Q19B
BATT_LED#_LV1
2
+5VALW
5
G
B
LED7 1
S
+5VALW
R32
100K_0402_5%~D
S
2
G
BATT_LED#_LV4
3
BATT_LED#_LV2
6
Q18A
S
1
D
2
G
C
D
BAT2
5
G
DMN66D0LDW-7_SOT363-6~D
4
6
Q17A
3
Q18B
D
DMN66D0LDW-7_SOT363-6~D
[38]
R22
ST
4
3
Q17B
5
G
[38]
IBAT4
2
2
R18
100K_0402_5%~D
2
R17
100K_0402_5%~D
2
1
1
+5VALW
3
B
S
LED3 White
12-22/Y2ST3D-C30/2C
ST
RTC counter
NFC Connector
+3V_NFC
ST
+3V_PCH
@ RN5
1
+3V_NFC
2 0_0402_5%
+3V_NFC
1
C1135
0.1U_0402_10V7K~D
2 N14@
[17]
+3V_NFC
@ RN8
@ RN9
2
1
2 0_0402_5%
NFC_DET#
@ RN7
[17]
NFC_IRQ
1
2 0_0402_5%~D
NFC_VDD_SIM
NFC_IRQ
2
ST
NFC_RST#
NFC_RST#
[17] SML0CLK
[17] SML0DATA
1 10K_0402_5%~D
1
NFC_VDD_SIM
A
[17]
NFC_DET#
RN1
100K_0402_5%~D
N14@
NFC_DET#
JNFC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15. MOD_GND
14. VDD_IO
13. MOD_VDD
12. SWP*1
11. SE_DOUT_CLK*1
10. SE_DIN_DIO*1
9. MOD_GND
8. I2C_SCL
7. I2C_SDA
6. VDD_SIM*2
5. IRQ
4. SE_PWR*1
3. SWP_PWR*1
2. MOD_GND
1. MOD_VDD
A
GND
GND
CONN@
HB_A531515-SCHR21
@
DN2
SML0CLK
2
SML0DATA
3
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
PESD5V0U2BT_SOT23-3~D
2011/08/25
Deciphered Date
2012/07/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Speaker/Audio Jack
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.1
LA-9941P
Tuesday, September 17, 2013
1
Sheet
49
of
62
5
Module
4
3
REV
D
2
1
Change list
From
To
X00
Remove Audio codec to DB --- page 47
X
X00
X00
Add GC6 function for GPU N14P --- page 24/28/33
X
X00
X00
Modify USB port detect pin to independent --- page 38 and page 45
X
X00
X00
Follow GPIO table modify pin assign --- page 38
X
X00
X00
Change to PWM FAN --- page 39
X
X00
X00
Change mDP output from GPU --- page 25
X
X00
CCD connector change to 11 pin, add CCD_INT signal. --- page 35
X
X00
X00
Change R45 PU to +3VALW for leakage current --- page 38
X
X00
X00
Rmovie Audio DSP chip and add KC3801 --- page 46 and page 38
X
X00
X00
Add RTC counter and add SSC chip for Audio bit clock --- page 46 and page 40
X
X00
X00
Just support N14P-GS, so remove GPU board ID. --- page 20
X00
X00
X
X00
Co-layout Sata Re-driver PS8520B/C --- page 43
X
X00
X00
EMC request add CM22 to close JTB1 pin17 --- page 40
X
X00
X00
Buyer request Change YH2/YL1 to SJ10000DE00 --- page 17/41
X
X00
X00
Buyer request Change YH1/Y4 to SJ10000DE00 --- page 16/46
X
X00
X00
Change RH85 connector to +1.5VS --- page 17
X
X00
X00
Change RPH1/RPH2/RPH3/RPH4/RPH5 tp single resister --- page 18/19
X
X00
X00
Modify eDP connector pin define, remove +3VS --- page 35
X
X00
X00
Modify support quad ROM, add RH10/RH41
X
X00
X00
Change HDMI level shift to active --- page 36
X
X00
X00
EMC request add CA36 --- page 40
X
X00
X00
NFC SMBus change to PCH SMBus0 --- page 17
X
X00
X00
CCD SMBus reserve connector to PCH, and CCD INT reserve connector to EC --- page 35
X
X00
X00
Modify USB charger schematic, change RI17/RI31/RI32connect to +3VALW, and remove RI18/RI28 --- page 44
X
X00
X00
Update VRAM PN --- page 1
X
X00
X00
Remove NFC function --- page 49
X
X00
X00
SWAP DA4 pin2 and pin3 --- page 48
X
X00
X00
Use array resister to reduce component
Change RH45/RH46/RH47/RH49 to array resister RPH11 --- page 17
Change RH50/RH51 to array resister RPH14 --- page 17
Change RH66/RH83/RH88/RH90 to array resister RPH24 --- page 17
Change RH69/RH74/RH77/RH81 to array resister RPH25 --- page 17
Change RH71/RH72 to array resister RPH15 --- page 17
Change RH137/RH139/RH140/RH141 to array resister RPH1 --- page 18
Change RH147/RH149/RH150/RH153 to array resister RPH2 --- page 18
Change RH116/RH117/RH118/RH124 to array resister RPH4 --- page 18
Change RH134/RH135/RH142/RH168/RH178/RH186/RH192/RH187 to array resister RPH26 --- page 19
Change RH189/RH183/RH179/RH181 to array resister RPH7 --- page 20
Change RH160/RH185/RH184/RH172 to array resister RPH8 --- page 20
Change RH190/RH178/RH177/RH182 to array resister RPH9 --- page 20
Change RV291/RV293/RV295/RV400 to array resister RPH12 --- page 24
Change RV292/RV294/RV296/RV297 to array resister RPH13 --- page 24
Change RV299/RV300 to array resister RPH16 --- page 24
Change RV325/RV326 to array resister RPH17 --- page 25
Change RV331/RV333/RV334/RV335 to array resiter RPH10 --- page 26
Change RH94/RH96 to array resister RPH27 --- page 35
Change RV445/RV447 to array resister RPH18 --- page 36
Change RE72/RE73 to array resister RPH20 --- page 38
Change RE17/RE18/RE36/RE37 to array resiter RPH19 --- page 38
Change RE14/RE15 to array resister RPH21 --- page 38
Change RH82/RH93 to array resister RPH22 --- page 42
Change R136/R137 to array resister RPH23 --- page 46
X
X00
X00
Use dual MOSFET to reduce single MOSFET
Change QZ15/QZ20 to dual MOS QZ23 --- page 34
Change QE4/QE6 to dual MOS QZ24 --- page 39
X
X00
X00
Use Anpec APL3512 to reduce Component
Remove RV401/RV402/QV26/QV28/RV404/CV745/QV27, Add CV26/CV28/UV12 --- page 35
X
X00
X00
Use TI TPS22966 to reduce Component
Remove RZ20/RZ14/QZ6/QZ10/CZ15/RZ17/QZ9/CZ38/QZ8/QZ7/RZ37, Add UZ4/RZ132/RZ133/CZ28/CZ29/QZ9/RZ17 --- page 34
X
X00
X00
Add DV9 for display have leakage issue --- page 37
X
X00
X00
Use Green Clock to reduce component
Unstuff RH1/YH1/CH3/CH4, add RH96 --- page 16
Unstuff RH89/YH2/CH27/CH28, add RH102 --- page 17
Unstuff YV1/CV575/CV576, add RV13 --- page 24
Unstuff YL1/CL22/CL25, Stuff RL10 --- page 41
Add C28/C27/C26/C84/R67/R68/U3/C34/R91/Y5/C41/C32 --- page 46
X
X00
--- page 17
X01
Remove DV7 for EMC component should close device connector side
X00
X01
X01
Remove +1.5V_PWROK and +1.35V_PWROK connect to HWPG for power good issue --- page 38
X00
X01
X01
Change S3_DRAMPWRGD circuit, that change 1.5VPWRGD to +V1.05S_VCCP_PWRGOOD and un-stuff RU50 ---- page 8
X00
X01
X01
Remove RZ13 for power value issue --- page 34
--- page 40
X00
X01
X01
Remove RV471 for Touch screen power issue --- page 35
X00
X01
X01
Un-stuff RE56 and stuff RE60 for EC power on issue --- page 38
X00
X01
X01
Un-stuff RH32 for +3V backdrive --- page 16
X00
X01
X01
Un-stuff RH158 for +3V backdrive --- page 20
X00
X01
X01
Remove PCH control TPM PD pin for +3V backdrive --- page 40
X00
X01
X01
Crete EC 3810 GPIO11 SUS_ON for DDR power enable --- page 38
X00
X01
X01
Stuff RV450/RV451 10K ohm for HDMI EA measure issue --- page 36
X00
X01
X01
Change RZ600 to 11K ohm for 1.5V power value issue --- page 34
X00
X01
X01
For GPU power sequence issue
Stuff CZ7 to 0.01u
change CZ6 to 0.047u and add CZ8 0.047u cap for 1.05VDGPU delay --- page 33
Stuff RZ10 10 ohm, RZ11/RZ15 1 ohm, RZ6 100 ohm.
change DZ2 enable pin2 to DGPU_PWROK and remove RZ485
Change RZ5 to 100k ohm
X00
X01
D
C
C
B
X01
RZ484 change PU to +3VS for GPU GC6 function issue --- page 33
X00
X01
X01
Remove RV504 and add QV40 for GPU thermal function --- page 24
X00
X01
X01
Audio vendor suggest for Iphone
Add RA11/CA30/RA2/RA3
Change CA26 to 100U
Change RA18/RA17 to 8.2 ohm
X00
X01
Change PCH_GPIO72 and WAKE# PU to +3VALW for DSx issue --- page 18
X00
X01
X01
Update power circuit
Add +1.35V enable signal SUS_ON and rename PM_SLP_S5# to PM_SLP_S4#.
Add 33uF*1 OS-CON for acoustic issue.
X00
X01
X01
Un-stuff QZ26/QZ27 for EC multi SPI function --- page 17
X00
X01
X01
SML0CLK/ SML0DATA PU to 499 ohm and reserve RH65 for NFC suggest --- page 17
X00
X01
X01
Change RPH11 8P4R to RH448/RH456 single type --- page 17
X00
X01
X01
Change DP from GPU output to Internal output
X00
X01
X01
Add DSP bypass circuit --- page 46
X00
X01
X01
Modify I/O connector JTB1 pin define --- page 40
X00
X01
X01
Add DI15 for Touch screen function --- page 35
X00
X01
X01
Add LCD_TEST RE64 PU to +EDPVDD --- page38
X00
X01
X01
Power SW LED resistor R66 change to 560 ohm --- page39
X00
X01
X01
Add JP802/JP803/JP11/JP14/JP15 for power measure
X00
X01
X01
Add JRTC to MB --- page 16
X00
X01
X01
Change JP5 size --- page 21
X00
X01
X01
Change FAN connector --- page 39
X00
X01
X01
PCH_GPIO12 change to PU +3VALW --- page 20
X01
change CH27,CH28=12pF,CV575,CV576=10pF
X00
X01
Change LA7/LA8/LA9/LA11 to 180 ohm bead --- page 48
X00
X01
X01
Remove JRTC --- page 16
X00
X01
X00
X01
Add RV411 for mDP voltage issue --- page 36
X00
X01
Add RF shielding EMIST_SUL-15A3M_1P footprint 12pcs --- page 40
X00
X01
X01
Change ODD_DA# to RPH2, un-stuff RH164, and RH416 for GPU enable issue --- page 18
X00
X01
X01
BIOS setting request PCH_GPIO70 for UMA/DIS, PCH_GPIO1 for GPU N14/N15 --- page 20
X00
X01
Change SW1 connector --- page 39
X00
Change NFC connector --- page 49
X01
X01
X00
X01
Stuff RU7/RU12/RU36 --- page 6
X00
X01
X01
Change Touch screen sleep circuit, remove DI5, add DV17/DV20/RV5 --- page 35
X00
X01
X01
Un-stuff RV466--- page 37
X00
X01
X01
Change DSP bypass circuit --- page 46
X00
X01
X01
Update power circuit
X00
X01
X01
Remove GPU DP HDP circuit --- page 24/37
X00
X01
X01
Remove GPU DP port power --- page 26
X00
X01
X01
Remove GPU VRAM power for N14E-GL --- page 28
X00
X01
X01
Change JHP2 connector --- page 47
X00
X01
X01
Add CV639 for vendor request --- page 28
X00
X01
X01
Change SD302100280 to SD309100280 for EOL
X00
X01
X01
CA17 un-stuff for pop issue
X00
X01
X01
Remove DV16, add DV18/DV19/RV415 for LCD power control --- page 35
Add RV416/RV419 for EC control LCD SMBUS --- page 35
X00
X01
X01
Remove RV483 and add RH178 for ST test --- page 20
X00
X01
X02
RZ5 change to 60.4K ohm for GPU sequence --- page 33
X01
X02
USB3.0 CAP CI5,CI6,CI7,CI8,CI11,CI12,CI13,CI20,CI3,CI4,CI16,CI17 change to 0.1uF for USB3.0 issue --- page 45
X01
X02
X02
modify eDP chock LV16~LV20 for footprint issue --- page 35
X01
X02
X02
LA7/LA8/LA9/LA11 change footprint size --- page 48
X01
X02
X02
CA53/CA58/CA59/CA60 change to 22nf for pop issue --- page 48
X01
X02
X02
Hynix “0”. ROM_SI=PD 5K ohm, Samsung”1”. ROM_SI=PD 10K ohm for VRAM SETTING --- page 25
X01
X02
X02
RA45/48 change to 60Kohm,RA46/51 changr to 30Kohm for Audio issue --- page 48
X01
X02
X02
change F1 to SP040002400 --- page 39
X01
X02
X02
Stuff RV460 and change RV458 to 4.7K ohm for HDMI EA issue --- page 36
X01
X02
X02
Change CV677 to X6S --- page 30
X01
X02
Change UZ14 for G5243 for +3V_PCH issue --- page 34
X01
X02
Add TI HDD redriver co-layout --- page 43
X01
X02
X02
Change LED footprint and change LED control circuit --- page 49
X01
X02
X02
Add PD resistor for SATA redriver EA issue --- page 43
X01
X02
X02
Change RU118 to 10K for OTP issue --- page 8
X01
X02
X02
X02
X02
X02
Change Board ID --- page38
X01
X02
Change H10/H18 footprint --- page 40
X01
X02
X02
Reserve PD resistor for SATA redriver --- page 43
X01
X02
X02
Change RA33/RA98/RA101/RE60/RE321/RE322/RN5/RN9/RU37/RU43/RU53/RV8/RV480/RV481/RV482/RV503/RV510/RH416
RV411/RV415/RV337/R8/R53/R54/R56/R58/RA53/RH202/RH213/RI74 to 0ohm short pad
X01
X02
X02
Change UV12 and UN3 to GMT G5243
X01
X02
A00
UV12 change to APL3512ABI-TRG_SOT23-5 for bring up issue --- page 35
Remove CV3508 for panel EA issue --- page 35
Add CCD_INT# pin --- page 38
X02
A00
A00
EMI shielding clip footprint change to SOLUTION_ICSRC6510-015SFR-B_1P(H7/H14/H17/H27/H19/H20/H21/H23/H25/H24/H26) --- page 40
change SM070002000 to SM070002Q00 --- page 35
X02
A00
A00
EMI shielding clip footprint change to EMIST_SUL-12A2M_1P(H7/H14/H17/H27/H19/H20/H21/H23/H25/H24/H26) --- page 40
Remove N15P external ROM and strap --- page 25
X02
A00
X02
A00
A00
Remove eDP co-layout component, and add EC_INV_PWM conntrol PWM from EC --- page 35
Issued Date
2011/08/25
Deciphered Date
2012/07/25
T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUT HORIZED BY COMPAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORMAT ION IT CONT AINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y WIT HOUT PRIOR WRIT T EN CONSENT OF COMPAL ELECT RONICS, INC.
Title
Block Diagram
Size
Date:
3
2
A
Compal Electronics, Inc.
Compal Secret Data
Security Classif ication
4
B
X01
X01
X02
5
X01
X01
X01
A
X01
Document Number
Rev
0.1
Tuesday, September 03, 2013
Sheet
1
50
of
62
5
4
3
2
1
AC mode Ta -> Tb -> Tc
DC mode Tc -> Ta -> Tb
+3V/+5V_ALW
EN_INVPWR
SI3457BDV
QV29
Power Button &
BATBTN &
USBCHG_DET
+INV_PWR_SRC
CPU1.5V_S3_GATE
+1.5V
SYSON
ADAPTER
RT8207MZQW
PU300
Tc
+1.5V_CPU_VDDQ
+1.5VS
TPS51212DSCR
PU500
+VCCP
VR_ON
ISL95836HRTZ
PU700
+VCC_CORE /
+VCC_GFXCORE_AXG
TPS2062ADR
UI2
+5V_CHGUSB
CHARGER
SUSP#
EC_ON /
VCOUT0_PH
+5VALW
RT8205LZQW
PU200
PCH_PWR_EN
SI3456DDV
QN1
SI4800BDY
QZ6
AO3419L
QH5
+5VS_HDD
+5VS
ODD_EN#
EN_DFAN1
FDC655BN
QN4
APE8873M
UE4
PBTN_OUT#
DPWROK
5
RSMRST#
6
PCH_RSMRST#
7
AC_PRESENT
ACPRESENT
PM_SLP_S3#
TP0610K
D
B+
PWRSHARE_EN_EC#
Tb
+3V/+5V_PCH
4
PWRBTN#
PCH
SUSP#
+VSBP
PGOOD
ON/OFF
ENE KB9012
+0.75VS
D
BATTERY
SUSP#
AO4728L
QU6
SI3456DDV
UZ4
RT8205LZQW
Ta
EC_ON
+5VS_ODD
PCH_PWR_EN
4
SYSON
9
SUSP#
12
AO3419L/SI3456DDV
PCH_DPWROK
SLP_S5#
8
PM_SLP_S5#
SLP_S3#
10
PM_SLP_S3#
+1.5V/+0.75VS
RT8207MZQW
PGOOD
+1.8VS
SY8033BDBC
PGOOD
+3VS
+FAN_POWER
APWROK
11
PCH_APWROK
PWROK
17
PCH_PWROK
SI4800BDY
+5V_PCH
+5VS
+3VALW
+V1.05S_VCCP_PWRGOOD
TPS51461RGER
PU600
+VCCSA
SYS_PWROK
18
SI4800BDY
PCH_PWR_EN
EN_WOL
SUSP#
SUSP#
SI3456DDV
QZ12
AO3419L
QL3
SY8033BDBC
PU400
SI4800BDY
QZ8
+3V_PCH
+1.5VS
+LAN_IO
+1.8VS
+3VS
SI3456DDV
+VCC_CORE/+VCC_GFXCORE_AXG
+VCCP
16
ISL95836HRTZ-T
EC_ENVDD /
VGA_LVDDEN
VR_ON
PGOOD
AO3419L
QV27
+LCDVDD
SI2301CDS
QV31
+3VS_CAM
TPS51212DSCR
PGOOD
EN_CAM
WLAN_EN
GPU
C
+1.5V_CPU_VDDQ
14
AO4728L
13
+3VS_WLAN
TPS51461RGER
PGOOD
15
SA_PGOOD
CPU1.5V_S3_GATE
+VCCP
+1.5V
B+
+3VS
SI3456DDV
QM1
+VCCSA
VGATE
C
+3V_ALW
DGPU_PWR_EN
AO3419L
QZ1
RC delay
ISL62883CHRTZ
PU800
RC delay
SI4634DY
UZ2
RC delay
SI4634DY
UZ1
+3VLP
+3VLP
100k
+3VS_DELAY
+GPU_CORE
+1.5VSDGPU
+3VLP
100k
ENE KB9012
100k
+1.05VSDGPU
2
ON/OFF
EC check which
button is pressed
4
Power Button
PCH_PWR_EN
A1
Turn on Other
system power
BATT_CAP_LED#_LV[1...5]
B1
Turn on
Battery LED
PWRSHARE_OE# &
PWRSHARE_EN_EC#
C1
Turn on USB
power charge
...
A
PBTN_SW#
PCH_PWROK
BATBTN
B
BATBTN#
+3V_ALW
B
B
+3V/+5V_ALW
10k
USBCHG_DET
C
USBCHG_DET#
EC_ON
Charger_LDO
3
+3V_ALW
RT8205LZQW
10k
+3VLP
VCOUT0_PH#
100k
100k
2n7002
150k
When press power button : A -> 2 -> 3 -> A1
When press Battery button : B -> 2 -> 3 -> B1
When USB charge device plug in : C -> 2 -> 3 -> C1
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power Sequence
Size
Document Number
Tuesday, September 03, 2013
Date:
5
4
3
2
1
Rev
0.1
Sheet
51
of
62
PQ100
FDV301N-G_SOT23-3
1
1
PR102
2.2K_0402_1%
PR103
33_0402_5%
1
2
3
PSID-3
D
@
2
PC130
15P_0402_50V8J
@ PR101
0_0402_5%
1
2
+3VALW
2
EMI Parts
PC103
100P_0402_50V8J
2
1
1
PD100
BAV99W-7-F_SOT323-3
3
VIN
PC102
1000P_0402_50V7K
2
1
1
2
1
PC101
100P_0402_50V8J
6
6
PC100
1000P_0402_50V7K
1
5
5
2
4
2
4
PC120
0.1U_0402_25V6
3
D
+5VALW
ESD Parts
PL106
FBMA-L11-201209-221LMA35_2P
1
2
2
3
38 1
PS_ID
7
+5VALW
2
G
1
PR105
10K_0402_1%
1
2
PSID-2
1
2
PR104
100K_0402_1%
3
PSID
PL101
BLM15AG102SN1D_2P
1
2
2
2
B
PSID-1
@ PD102
PESD24VS2UT_SOT23-3~D
1
C
PQ101
MMST3904-7-F_SOT323-3
E
3
1
PR106
15K_0402_1%
2
1
PC121
0.1U_0402_25V6
2
PL103
FBMA-L11-201209-221LMA35_2P
2
1
7
PL108
FBMA-L11-201209-221LMA35_2P
2
1
1
ADPIN
2
CONN@ ADP100
ACES_50290-00701-001
1
1
2
C
1
B
PL100
FBMA-L11-201209-221LMA35_2P
1
2
S
A
2
@ PR112
0_0402_5%
1
2VSB_N_002 2
G
PC110
.1U_0402_16V7K
D
S
2
3
VSB_N_001
PQ103
L2N7002W T1G_SC70-3
2
PR114
10K_0402_1%
1
2
PR113
100_0402_1%
1
2
1
2
POK
1VSB_N_003
18,54
1
38,53
3
1
EC_SMB_DA1
2
38,53
PC108
0.22U_0603_25V7K
1
1
EC_SMB_CK1
PR110
100K_0402_1%
EC_BATT_PRS# 38,53
CLK_SMB
DAT_SMB
BATT_PRS
PR108
37.4K_0402_1%
1
2
3
2
+3VALW
+VSBP
PC109
0.1U_0402_25V6
2
1
1
3
2
PC107
100P_0402_50V8J
PC106
1000P_0402_50V7K
2
1
1
2
1
2
PC105
0.01UF_0402_25V7K
PR111
100_0402_1%
1
2
PR107
1M_0402_5%
ESD Parts
@ PD104
PESD24VS2UT_SOT23-3~D
G
1
B+
@ PD103
PESD24VS2UT_SOT23-3~D
PR109
100_0402_1%
1
2
CONN@ BAT100
ACES_50290-01201-P01
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
11 12
12
PQ102
SI3457CDV-T1-GE3_TSOP6
6
5
2
4
1
ESD Parts
D
2
BATT++
PL105
HCB2012KF-121T50_0805
1
2
PL102
HCB2012KF-121T50_0805
1
2
S
2
PC104
100P_0402_50V8J
BATT+
+3VALW_EC
38,53
ADP_I
3
3
1
JIMBTY battery connector
PR116
13.7K_0402_1%
2
SMART
Battery:
01.BAT+
02.BAT+
03.BAT+
04.BAT+
05.CLK_SMB
06.DAT_SMB
07.BATT_PRS
08.SYS_PRS
09.GND
10.GND
11.GND
12.GND
PR118
13.7K_0402_1%
2
@
close EC
1
VCIN1_PH
PC111
0.1U_0402_25V6
2
1
38
4
4
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
Title
PWR-DCIN / BATT CONN / OTP
Size
Document Number
Date:
W ednesday, September 04, 2013
Rev
0.1
LA-9941P
D
Sheet
52
of
62
5
4
3
2
1
PR200
2
1
PC207
10U_0805_25V6K
1
2
PC206
10U_0805_25V6K
1
2
PC205
10U_0805_25V6K
1
2
PC204
10U_0805_25V6K
PC203
2200P_0402_50V7K
2
1
1
1
1
2
PC271
15P_0402_50V8J
2
2
PC211
0.1U_0402_25V6
1
2
EMI Parts
B+
PC230
10U_0805_16V6K
1
2
1
PC231
10U_0805_16V6K
1
2
1
PR223
120K_0402_1%
EC_SMB_CK1
ACN
ACP
ACDRV
CMSRC
20
VCC
18
HIDRV
VCC
CHG_LX
CHG_UGATE
PC216
0.047U_0603_25V7K~D
PL203
2.2UH_FDVE1040-H-2R2M-P3_14.2A_20%
1
2
2
PR215
2.2_0603_5%
EMI Parts
1
CSOP_B
+VCHGR
PR219
0.01_2512_1%
4
2
3 CSON_B
1
BTST
16
1
17
BTST
REGN
1
PR222
4.7_1206_5%
2
PD201
BAT54HT1G_SOD323-2
EC_BATT_PRS#
1
1
15
14
13
SRP
BATDRV#
2
PC226
0.1U_0402_25V6
1
2
PC227
0.1U_0402_25V6
1
2
@ PR218
0_0402_5%
1
2
@ PQ207
2N7002KW_SOT323-3
3
@ PC225
0.1U_0402_25V6
1
2
@ PR221
0_0402_5%
1
2
B
S
PD202
SX34H_SMA2
1
2
2
@ PR225
100K_0402_1%
PC224
680P_0603_50V7K
CHG_LGATE
D
2
G
1
38,52
2
PC212
1U_0603_10V6K
For LEARN mode disable (pulse)
B
1
REGN
REGN
Pull high for 3 CELL operation
@ PC228
0.01UF_0402_25V7K
1
2
12
PR224
10K_0402_1%
1
2
ADP_I
ADP_I
SRN
38,52
11
2
CELL
LODRV
SCL
GND
9
10
SRP
EC_SMB_CK1_R
SRN
1
2
@ PR231
0_0402_5%
CELL
/BATDRV
PC219
100P_0402_50V8J
1
2
C
PC217
10U_0805_16V6K
1
2
19
PHASE
PU200
BQ24715RGRR_QFN20_3P5x3P5
SDA
PC215
10U_0805_16V6K
1
2
21
PAD
1
ACN
3
2
ACP
PQ204
CSD87351Q5D_SON8-7
1
IOUT
PC233
10U_0805_16V6K
1
2
PC223
10U_0805_16V6K
2
1
EC_SMB_CK1
8
4
PC222
10U_0805_16V6K
2
1
38,52
EC_SMB_DA1_R
3
CHG_LGATE
PC220
0.1U_0402_25V6
2
1
EC_SMB_DA1
@ PR230
0_0402_5%
1
2
ACDET
CHG_LX
2
38,52
EC_SMB_DA1
CMSRC
6
ACOK
5
2
PC214
1U_0805_25V6K
PC232
10U_0805_16V6K
1
2
7
6
5
8
1
VCC
PC218
0.01UF_0402_25V7K
2
CHG_UGATE
ACOK
PR213
10_1206_5%
1
2
PC221
10U_0805_16V6K
2
1
AC_IN
7
2
1
CSSN_1
CSSP_1
4
@ PR220
0_0402_5%
1
2
ACDET
1
PC210
0.1U_0402_25V6
1
2
2
2
PD200
1
1
2
PR214
499K_0402_1%
RB751V-40_SOD323-2
1
2
38
C
2
D
@ PR210
0_0402_5%
PR217
100K_0402_1%
VIN
PR216
82.5K_0402_1%
1
2
PL206
FBMA-L11-201209-221LMA35_2P
REGN
@
@
4
1
S
@ PR212
200K_0402_1%
2
ACOK 1
PC209
1U_0603_25V6K
1
2
ACDRV
2
G
3
1
D
2
PL205
FBMA-L11-201209-221LMA35_2P
1
2
2
6
@
@ PC213
.1U_0402_16V7K
PR208
4.02K_0402_1%
1
2
ACDRV
2
S
PR201
0.01_2512_1%
4
@ PR209
0_0402_5%
For ErpLot6
5
G
1
EMI Parts
@ PR207
0_0603_5%
PR211
1M_0402_5%
2
1
@
PC208
0.022U_0402_25V7K
2
D
PQ203A
DMN66D0LDW-7_SOT363-6
S
DMN66D0LDW-7_SOT363-6
PQ203B
4
3
1
D
2
G
PQ202
2N7002-7-F_SOT23-3
ACOFF
3
38
1
2
@
D
PC200
0.1U_0402_25V6
P1
1
1
@
For DT mode
1
2
3
4
PR204
1M_0402_5%
2
1
1
2
2
@
PR203
5.1K_0805_1%
1
PR202
5.1K_0805_1%
VIN
CMSRC
4.02K_0402_1%
PQ201
MDS1521URH_SO8
1
8
2
7
3
6
5
PQ200
MDS1521URH_SO8
8
7
6
5
2
PC202
0.1U_0402_25V6
2
1
1
+VCHGR
PQ208
AO4407AL_SO8
4
S
1
3
4
S
2
EMI Parts
PQ231B
DMN66D0LDW-7_SOT363-6
6
PR293
1M_0402_1%
D
2
G
D
5
G
PR294
100K_0402_1%
@ PR284
10_0402_1%
PR227
4.02K_0402_1%
1
2
H_PROCHOT#
PC261
1U_0603_10V6K
1
2
2
1
@ PR283
10_0402_1%
+3VALW
PR292
10K_0402_1%
PR291
1M_0402_1%
1
2
@
VIN
@
@ PC251
1U_0402_6.3V6K
1
2
BATDRV#
1
ININ+
2
5
4
CSON_B
A
IN+
INA199A2DCKR_SC70-6~D
S
PC260
.01U_0402_16V7K
2
1
160K_0402_1%
PQ230
L2N7002WT1G_SC70-3
IN-
V+
asserts H_PROCHOT# when adaptor is
unplugged, keep low for 10ms
till SW PROCHOT# is issued by EC
2
2
G
GND
1
2
3
@ PR282
1_0402_5%
D
2
2
1
1
3
H_PROCHOT#_EC
1
PR290
1
2
+3VALW
CSOP_B
ST change to short pads
38,58,8
PC252
0.1U_0402_25V6
H_PROCHOT#
Battery protection:
1
0_0402_5%
@ PR280
0_0402_5%
H_PROCHOT#
@ PR281
2
1
Out
BMON_OUT 1
PQ231A
DMN66D0LDW-7_SOT363-6
REF
6
1
1
2
2
PC250
0.1U_0402_25V6
2
1
@ PU202
1
38
@ PAD
PT200
Battery Current Sensor - BMON circuits
2
Delay Adaptor OC H_PROCHOT# 200us
while Hybrid power transition
BATT+
8
7
6
5
PC270
15P_0402_50V8J
1
2
3
3S3P
CC = 5.28A
CV = 3S (12.6V)
A
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PWR-Charger
Size
Document Number
Date:
Wednesday, September 04, 2013
Rev
0.1
LA-9941P
1
Sheet
53
of
62
A
B
C
D
E
1
+3VLP
2
PC307
1U_0603_10V6K
1
2
@ PR335
0_0402_5%
@ PC301
100P_0402_50V8J
1
2
@ PC302
100P_0402_50V8J
1
2
PR300
13.7K_0402_1%
1
2
PR301
30.9K_0402_1%
1
2
B++
VBST2
12
11
VO1
4
DRVH1
LX_5V
17
PR308
PC311
2.2_0603_5%
0.1U_0603_50V7K
2 BST1_5V 1
2
BST_5V 1
16
UG_5V
PQ303
15
DRVH2
DRVL1
VBST1
10
14
PR307
2.2_0603_5% UG_3V
9
VREG5
BST_3V
DRVL2
PC310
0.1U_0603_50V7K
2
13
BST1_3V 1
VIN
2
LG_3V
4
LG_5V
@ PC315
.1U_0402_16V7K
1
1
PC309
10U_0805_25V6K
PC308
2200P_0402_50V7K
2
1
1
PL300
1.5UH_ETQP3W1R5WFN_9.5A_20%
1
2
18
@ PC314
.1U_0402_16V7K
2
2
1
2
PC316
680P_0603_50V7K
2
1
SNUB_3V 2
+
PC312
150U_B2_6.3VM_R35M
1
PR309
4.7_1206_5%
PQ302
MDV1524URH_PDFN33-8-5
1
2
3
5
1
2
+5VALWP
PR310
4.7_1206_5%
1
+
2
PC313
150U_B2_6.3VM_R35M
SW1
5VA_EN 38
PC317
680P_0603_50V7K
VCLK
SW2
5VA_EN
@ PR350
1
2
200_0402_1%
1
8
19
2
LX_3V
PGOOD
SNUB_5V
7
@ PR341
0_0402_5%
1
2
3
2
1
20
1
1
CS1
3
2
VFB1
21
PAD
5
18,52 POK
PL301
3.3UH_FDSD0630-H-3R3M-P3_6.6A_20%
1
2
EN2
EN1
@ PR337
1
2
0_0402_5%
4
TPS51225CRUKR_QFN20_3X3
3
2
1
1
2
3
EMI Parts
6
VREG3
3VA_EN
3VA_EN
VFB2
38
@ PR340
0_0402_5%
1
2
4
5
PU300
4
2
5
PQ301
PC306
0.1U_0402_25V6
2
1
PR306
40.2K_0402_1%
1
2
MDU1516URH_POWERDFN56-8-5
EMI Parts
PQ300
MDV1528URH_PDFN33-8-5
2
+3VALWP
PR304
20K_0402_1%
1
2
5
PR305
62K_0402_1%
1
2
PC305
10U_0805_25V6K
PC304
2200P_0402_50V7K
2
1
PC303
0.1U_0402_25V6
2
1
2
1
PC340
15P_0402_50V8J
2
1
@ PJP300
JUMP_43X118
1
2
1
2
FB_5V
2
PR302
20K_0402_1%
1
2 FB_3V
B++
CS2
B+
1
MDU1512RH_POWERDFN56-8-5
1
EMI Parts
EMI Parts
1
2
PC319
1U_0603_10V6K
2
@ PR338
0_0402_5%
0.1U_0402_25V6
PC320
2
1
3
1
3
B++
@ PJP303
1
2
PAD-OPEN 4x4m
@ PJP302
+3VALWP
1
@ PJP301
2
+3VALW
+5VALWP
PAD-OPEN 4x4m
1
2
+5VALW
PAD-OPEN 4x4m
3.3VALWP
TDC 4.6A
Peak Current 6.5A
OCP current 7.8A
5VALWP
TDC 7.9A
Peak Current 11.3A
OCP current 13.4A
4
4
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
PWR-3VALWP/5VALWP
Size
Document Number
Date:
Wednesday, September 04, 2013
Rev
0.1
LA-9941P
Sheet
E
54
of
62
1
PR400
2.2_0603_5%
1
2
1
+0.675VS
+0.675VSP
PAD-OPEN1x1m
1
D
1
PC406
10U_0805_6.3V6M
+V_DDR_REF
4
5
+1.35V_MEN_P
C
2
PC411
.1U_0402_16V7K
6
S3
7
10
2
3
1
VDDQSNS
1
VDDQSET
VCC
21
2
1
VTT
VLDOIN
BST
VTTREF
PC410
1U_0603_10V6K
ST change to short pads
GND
VPP
S5
11
VDD_1.35V
CS
VTTSNS
PU400
G5616ARZ1U_TQFN20_3X3
TON
4
12
PAD
VTTGND
PGND
PGOOD
1
+5VALW
PR402
5.1_0603_5%
1
2
13
8
14
PR401
7.15K_0402_1%
1
2
CS_1.35V
PC407
1U_0603_10V6K
1
2
DL
9
15
DL_1.35V
DH
2
20
19
18
17
16
LX
4
PC405
10U_0805_6.3V6M
SW _1.35V
2
PQ401
MDV1522URH_PDFN33-8-5
1
2
3
5
2
PAD-OPEN 3x3m
PR405
16.2K_0402_1%
1
2
+5VALW
2
PC409
680P_0603_50V7K
BOOT_1.35V
2
@ PJP402
1
+
2
PR403
4.7_1206_5%
1 SNUB_1.35V 2
1
+VLDOIN_1.35V
DH_1.35V
PQ400
MDV1527URH_POWERDFN33-8-5
1
2
3
5
1
PC403
2200P_0402_50V7K
2
1
PC402
0.1U_0402_25V6
2
1
2
PC401
10U_0805_25V6K
PC404
0.22U_0603_16V7K
1
2
PL400
1UH_FDSD0630-H-1R0M-P3_11A_20%
1
2
PC408
330U_B2_2.5VM_R9M
C
@ PJP404
PAD-OPEN 4x4m
2
1
2
@ PJP401
1.35V_B+
2
@ PJP403
PAD-OPEN 4x4m
2
1
+1.35V_MEN_P
+1.35V
3
EMI Parts
@ PJP400
JUMP_43X118
1
2
1
2
1
B+
PC400
10U_0805_25V6K
D
4
+1.35V_MEN_P
5
1.35V_FB
@ PC412
22P_0402_50V8J
1
2
EMI Parts
+1.35V_PWROK
18,38
PM_SLP_S4#
@ PR407
0_0402_5%
1
2
1.35V_B+
PR406
1M_0402_1%
1
2
S5_1.35V
1
8
+1.35V_PW ROK
2
PR408
20K_0402_1%
B
B
18,34,38,40,43,56
PM_SLP_S3#
@ PR409
0_0402_5%
1
2
FB sense trace
0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.1A
1.35Volt +/- 5%
TDC 7.2A
Peak Current 10.2A
OCP current 12.2A
A
A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.35V_MEN/+0.675V_DDR_VTT
Size
Document Number
Date:
Thursday, September 05, 2013
Rev
0.1
LA-9941P
Sheet
1
55
of
62
5
4
3
2
1
EMI Parts
@ PJP500
2
RF_+V1.05V
5
PHASE
FB
VCC
RF
LGATE
1
TP
9
UG_+V1.05V
8
SW _+V1.05V
7
6
11
RT8237EZQW (2)_W DFN10_3X3
PR505
200K_0402_1%
PR501
2.2_0603_5%
1
2
PC504
0.1U_0603_50V7K
1
2
B+
1
PC511
0.1U_0402_25V6
2
1
PC503
10U_0805_25V6K
2
1
PC502
10U_0805_25V6K
2
1
PC501
2200P_0402_50V7K
2
1
PL500
1UH_FDSD0630-H-1R0M-P3_11A_20%
1
2
PR510
10_0603_5%
1
2
D
@ PJP501
1
2
+VCCP
PAD-OPEN 4x4m
+5VALW
LG_+V1.05V
1
2
PC506
1U_0603_10V6K
2
4
3
2
1
C
PR504
4.7_1206_5%
1
+
2
PC509
1000P_0402_50V7K
PC507
150U_B2_6.3VM_R35M
4
UGATE
EN
BST_+V1.05V
1
1
1
FB_+V1.05V
CS
10
2
3
BOOT
1
18,34,38,40,43,55
2
EN_+V1.05V
PGOOD
PQ501
MDV1524URH_PDFN33-8-5
@ PR503
0_0402_5%
1
2
PM_SLP_S3#
1
2
JUMP_43X118
@ PJP502
1
2
PAD-OPEN 4x4m
2
PU500
PR502
90.9K_0402_1%
1
2 TRIP_+V1.05V
3
2
1
+V1.05S_VCCP_PWRGOOD
5
38,8
PC500
0.1U_0402_25V6
4
2
D
PQ500
MDV1528URH_PDFN33-8-5
5
+V1.05V_B+
C
@ PC510
1000P_0402_50V7K
1
2
EMI Parts
+VCCP(1.05V)
TDC 6.5A
Peak Current 9.2A
OCP current 11.1A
1
PR507
10.5K_0402_1%
1
2
2
PR508
20K_0402_1%
B
B
A
A
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PWR-V1.05S_VCCPP
Size
Document Number
Date:
W ednesday, September 04, 2013
Rev
0.1
LA-9941P
Sheet
1
56
of
62
5
4
3
2
1
+5VALW
D
D
EMI Parts
27
PU600
TPS51367RVER_QFN28_4P5X3P5
VREF
PGND
RA
PGND
EN
PC621
4.7U_0805_16V7K
2
1
PC610
4.7U_0805_16V7K
2
1
11
PC607
33P_0603_50V8J
2
SW
1
10
1
PR607
10_1206_5%
2
@ PT601
PAD
PC603
4.7U_0805_16V7K
2
1
12
BST_+1.5VRUN
B
PC601
2200P_0402_50V7K
2
1
13
9
SW
8
SW
7
SW
6
BST
5
NC
4
MODE
PGND
3
TP
1
29
LP#
DGPU_FB_EN
2
28
PGOOD
33
C
SW_+1.5VRUN
1
2
1
2
PC613
22U_0805_6.3VAM
PGND
26
REF_+1.5V_RUNP
@
14
PC612
22U_0805_6.3VAM
REFIN
PC600
.1U_0402_16V7K
2
1
PC620
47P_0402_50V8J
2
1
15
VIN
16
VIN
17
VIN
V5
18
19
GND
20
PGND
25
@ PJP600
PAD-OPEN 3x3m
2
1
+1.5V_RUN_B+
TRIP
SLEW
21
+1.5V_VSNS
PC602
4700P_0402_25V7K
2
1
22
23
B+
PC611
22U_0805_6.3VAM
PC605
.1U_0402_16V7K
1
2
REFIN2
GSNS
2
24
PR600
100K_0402_1%
1
2
VSNS
1
PR602
300K_0402_1%
C
PC604
1U_0603_10V7K
1
2
+1.5VSDGPU
1
@ PJP601
1
2
2
PAD-OPEN 4x4m
PL600
0.68UH_PCMC063T-R68MN_15.5A_20%
1
2
B
@ PJP602
1
+1.5V_VSNS
2
2
2
PC614
.1U_0603_25V7K
EMI Parts
PR608
5.1_0603_5%
1
1
PAD-OPEN 4x4m
1.5Volt +/-5%
TDC 9.7A
Peak Current 13.8A
OCP current 16A (Fix)
DELL CONFIDENTIAL/PROPRIETARY
A
A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PWR_+1.5VRUN
Size
Document Number
Date:
Wednesday, September 04, 2013
Rev
0.1
LA-9941P
Sheet
1
57
of
62
2
PC733
0.022U_0402_25V7K
1
2
PC762
47P_0402_50V8J
2
1
PC705
2200P_0402_50V7K
2
1
PC704
0.1U_0402_25V6
2
1
PC703
10U_0805_25V6K
2
1
PC702
10U_0805_25V6K
2
1
PC701
10U_0805_25V6K
2
1
1
2
1
2
1
3
4
1
2
PC761
47P_0402_50V8J
2
1
PC719
2200P_0402_50V7K
2
1
PC721
0.1U_0402_25V6
2
1
PC717
10U_0805_25V6K
2
1
PC716
10U_0805_25V6K
2
1
2
PR741
3.65K_0603_1%
1
2
V1N
PR742
100K_0603_1%
1
2
1
PC728
33P_0603_50V8J
2
PR732
PC718
1K_0402_1% 100P_0402_50V8J
1
2
1
2
ISEN1
PR745
10_0402_1%
@ PR744
1_0402_5%
1
2
@ PC729
0.082U_0402_16V7K
1
2
1
+VCC_CORE
3
P1_SW
PR743
10_1206_5%
PC727
0.22U_0603_16V7K
C
@ PL700
HCB2012KF-121T50_0805
1
2
PL702
0.36UH_FDUE1040J-H-R36M-P3_33A_20%
1
4
7
6
5
1
PR740
2.2_0603_5%
2
BOOT1 1
1
1
2
PHASE1
2
PQ703
CSD87351Q5D_SON8-7
+5VS
PC714
0.1U_0603_16V7K
2
1
2
2
V2N
B
PC730
0.33U_0603_10V7K
1
2
@ PR747
0_0402_5%
1
2
PC731
0.022U_0603_50V7K
1
2
@ PC725
330P_0402_50V7K
PR748
11K_0402_1%
1
2
2
1
UGATE1
+
LGATE1
2
1
+VCC_PWR_SRC1
1
JUMP_43X118
EMI Parts
@ PR738
2K_0402_1%
VCCSENSE
1
2
PR749
3.57K_0402_1%
1
2
PH701
10K_0402_5%_ERTJ0ER103J
1
@ PC734
330P_0402_50V7K
1
2
2
PC737
0.01U_0402_50V7K
1
2
PC736
0.082U_0402_16V7K
12
8
@ PJP701
2
+VCC_PWR_SRC2
PR725
@ 0_0402_5%
1
2
2
PC738
.1U_0402_16V7K
PR717
10_0402_1%
@ PR721
1_0402_5%
1
2
V1N
@
PR733
1.65K_0402_1%
1
2
ISUMN
ISEN2
ISUMN
FB
PR715
100K_0603_1%
1
2
B+
LGATE1
PHASE1
UGATE1
BOOT1
2
2
1
B
PR739
845_0402_1%
ISEN1
V2N
EMI Parts
PR734
390_0402_1%
1
2
@
3
P2_SW
EMI Parts
PU700
ISL95812HRZ-T_QFN32_4x4
PC722
2700P_0402_50V7K
1
1
1
2
2
PC724
33P_0402_50V8J
ISEN2
PC732
0.022U_0402_25V7K
1
2
PC707
33P_0603_50V8J
FB2/VSEN
2
PC726
0.022U_0402_16V7K
PC706
0.22U_0603_16V7K
LGATE2
PR730
1_0603_1%
1
2
PR736
2K_0402_1%
+VCC_CORE
PR716
10_1206_5%
ISUMP
9
10
11
12
13
14
15
16
PR728
6.04K_0402_1%
1
2
2
2
PR714
3.65K_0603_1%
1
2
LGATE2
2
PR727
27.4K_0402_1%
1
PC715
10U_0805_25V6K
2
1
PAD
24
23
22
21
20
19
18
17
LGATE2
VDDP
PWM3
LGATE1
PHASE1
UGATE1
BOOT1
VIN
@ PL705
HCB2012KF-121T50_0805
1
2
PL701
0.36UH_FDUE1040J-H-R36M-P3_33A_20%
1
4
7
6
5
2
33
PH700
470K_0402_5%_TSM0B474J4702RE
1
4
PC700
100U_D2_16VM_R50M
PR724
3.83K_0402_1%
1
2
2
3
PR713
2.2_0603_5%
2
BOOT2 1
1
NTC
COMP
FB
SCLK
VR_ON
PGOOD
IMON
VR_HOT#
NTC
COMP
FB
1
2
1
1
PC710
47P_0402_50V8J
+VCCP
@ PR726
100K_0402_5%
1
2
VR_HOT_CPU
1
2
3
4
5
6
7
8
1
IMON
PR722
499_0402_1%
1
2
38,53,8 H_PROCHOT#
PHASE2
VCORE_VDDP
32
31
30
29
28
27
26
25
SCLK
VR_ON_VCORE
VCC_PGOOD
ALERT#
SDA
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
PC709
1000P_0402_50V8-J
1
2
1
JUMP_43X118
ISUMN
PC708
1U_0603_10V6K
1
2
ALERT#
@ PR719
0_0402_5%
1
2
2
2
SDA
PR718
95.3K_0402_1%
1
2
UGATE2
@ PR712
0_0402_5%
PHASE2
2
1
PQ700
CSD87351Q5D_SON8-7
ISUMP
UGATE2
PR711
1.91K_0402_1%
1
2
18,38,6 IMVP_VR_PG
C
BOOT2
FB2/VSEN
ISEN3
ISEN2
ISEN1
RTN
ISUMN
ISUMP
VDD
+3VS
+5VS
PR709
16.9K_0402_1%
1
2
2
D
PR707
3.24K_0402_1%
1
2
@ PR710
0_0402_5%
1
2
VR_ON
MAX
8.8mohm
3.1mohm
PR704
73.2K_0402_1%
1
2
PR706
@ 0_0402_5%
1
2
VR_SVID_CLK
38
TYP
H/S Rds(on) : 7.4mohm,
L/S Rds(on) : 2.6mohm,
PR705
@ 0_0402_5%
1
2
VR_SVID_ALRT#
12
75_0402_5%
2
54.9_0402_1%
2
PR703
@ 0_0402_5%
1
2
VR_SVID_DAT
12
130_0402_5%
2
@ PJP700
2
12
B+
EMI Parts
+VCC_PWR_SRC1
8
D
1
VCC_core (Base on PDDG rev 1.0) (1.8V)
TDC 21A
TDC PL2 (40Sec):26A
Peak Current 55A
DC Load line -1.5mV/A
AC Load line -2.4mV/A
Icc_Dyn_VID1 35A
OCP Current 66A
DCR 0.82mohm +/-5%
1
@ PR701
1
PR702
1
2
PC711
0.22U_0603_25V7K
PR700
1
+VCCIO_OUT
3
1
4
1
5
ISUMP
ISUMN
@
A
A
13
VSSSENSE
Local sense put on HW site
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+VCC_CORE
Size
Document Number
Date:
Wednesday, September 04, 2013
Rev
0.1
LA-9941P
1
Sheet
58
of
62
GPU_CORE (0.95V)
TDC 45A
Peak Current 75A
OCP current 86A
DCR 0.97mohm +/- 5%
PR836
@ 0_0402_5%
1
2
24
GPU_VID_0
TYP
MAX
H/S Rds(on) : 7.4mohm , 8.1mohm
L/S Rds(on) : 2.6mohm , 3.1mohm
+3VS_DELAY
PR803
2.2K_0402_1%
PC806
2200P_0402_50V7K
2
1
PC805
0.1U_0402_25V6
2
1
PC850
47P_0402_50V8J
2
1
PC804
4.7U_0805_16V7K
2
1
+
2
1
+
2
1
2
PC809
33P_0603_50V8J
1
PC831
330U_B2_2.5VM_R9M
+
2
2
EMI Parts
U2_PHASE2
PC814
4.7U_0805_16V7K
2
1
1
PC823
.1U_0603_25V7K
RT8813AGQW_WQFN24_4X4
@
EMI Parts
PQ801
CSD87351Q5D_SON8-7
2
PR813
2.2_0603_5%
1
2
U2_BOOT2
@
PC819
2200P_0402_50V7K
2
1
U2_LGATE2
19
PC818
0.1U_0402_25V6
2
1
GPU_PVCC
20
PC851
47P_0402_50V8J
2
1
21
PR821
2.2_0603_5%
1
2
PC817
4.7U_0805_16V7K
2
1
U2_PWM3
PC816
4.7U_0805_16V7K
2
1
U2_LGATE1
22
PC815
4.7U_0805_16V7K
2
1
+5VS
23
U2_BOOT2
PC813
0.1U_0603_50V7K
1
2
PL802
0.22UH_FDUE0640-H-R22M=P3_25A_20%
1
2
7
6
5
3
1
4
U2_PHASE2
PR822
10_1206_5%
U2_LGATE2
8
EMI Parts
PR842
1_0402_5%
1
2
DGPU_PWROK
PC822
33P_0603_50V8J
2
1
2
PR850
10K_0402_1%
1
2
+VGA_B+
20,33
6
9
EN
VCC
PWM
UGATE
BOOT
PHASE
GND
GND
LGATE
1
U2_UGATE3
PR832
2.2_0603_5%
1
2
PC839
0.1U_0603_50V7K
1
2
PC836
2200P_0402_50V7K
2
1
PC837
0.1U_0402_25V6
2
1
PC852
47P_0402_50V8J
2
1
PC835
4.7U_0805_16V7K
2
1
PC834
4.7U_0805_16V7K
2
1
PQ802
CSD87351Q5D_SON8-7
2
4
U2_BOOT3
2
U2_PHASE3
3
7
U2_LGATE3
4
7
6
5
PL803
0.22UH_FDUE0640-H-R22M=P3_25A_20%
1
2
1
8
5
3
PR830
10_1206_5%
1
U2_PWM3
@
EMI Parts
PC838
33P_0603_50V8J
2
+5VS
1
@
EMI Parts
PU801
RT9610BZQW_WDFN8_2X2~D
8
@ PR853
0_0402_5%
1
2
PC833
4.7U_0805_16V7K
2
1
PC832
4.7U_0805_16V7K
2
1
Pull high by EE side
2
PR852
10K_0402_1%
1
2
PR851
10K_0402_1%
1
2
+VGA_B+
U2_PHASE1
2
BOOT2
18
PGOOD
UGATE2
17
VCC/ISNE1
PHASE2
24
1
U2_PHASE1
1
2
U2_BOOT1
PVCC
LAGTE2
16
SS
2
U2_PHASE2
PC803
4.7U_0805_16V7K
2
1
PR806
10_1206_5%
U2_UGATE2
U2_PHASE3
+GPU_CORE
PC830
330U_B2_2.5VM_R9M
4
1
U2_UGATE1
1
BOOT1
EN
UGATE1
4
PSI
VID
REFADJ
2
7
6
5
3
8
GPU_EN
2
GPU_VID
5
3
GPU_REFADJ
6
VSNS
15
12
RGND
TALERT/ISEN2
11
LGATE1
GND/PWM3
TSNS/ISEN3
10
GPU_FB
PC824
.01U_0402_16V7K
1
2
@ PC825
0.01UF_0402_25V7K
PC800
0.1U_0603_50V7K
1
2
PR837
10.5K_0402_1%
PHASE1
TON
U2_UGATE2
1
GPU_FBRTN
GPU_COMP
@ PR824
0_0402_5%
B+
PL801
0.22UH_FDUE0640-H-R22M=P3_25A_20%
1
2
U2_LGATE1
VREF
GPU_PGOOD
@ PR827
15.8K_0402_1%
1
2
@ PC821
33P_0402_50V8J
2 1
2
9
14
PR825
100_0402_1%
1
2
1
8
GPU_TON
REFIN
GND
+GPU_CORE
@ PR823
0_0402_5%
1
2
GPU_VREF
@
25 GPU_VDD_SENSE
GPU_REFIN
13
PR819
100_0402_1%
1
2
PU800
7
25
25 GPU_VSS_SENSE
@ PR818
0_0402_5%
1
2
1
EMI Parts
PQ800
CSD87351Q5D_SON8-7
U2_PHASE1
PR817
620K_0402_1%
1
2
@ PC820
.01U_0402_16V7K
PR815
20_0402_1%
1
2
1
+VGA_B+
PR801
2.2_0603_5%
1
2
PC812
0.01UF_0402_25V7K
2
1
U2_BOOT1
@
PC829
330U_B2_2.5VM_R9M
18,24,33
1
2
U2_UGATE1
DGPU_PWR_EN
@
2
JUMP_43X118
1
PR841
47K_0402_1%
1
2
1
1
Pull high by EE side
PC811
2700P_0402_50V7K
PC802
4.7U_0805_16V7K
2
1
2
PR809
20K_0402_1%
1
2
2
1
2
@ PC810
.01U_0402_16V7K
1
2
24
GPU_PSI
PR807
2K_0402_1%
1
2
PR812
18.2K_0402_1%
@ PJP800
2
2
PR804
19.6K_0402_1%
PC801
4.7U_0805_16V7K
2
1
1
PC807
0.1U_0402_25V6
2
1
1
+VGA_B+
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VGA_CORE
Size
Document Number
Date:
Wednesday, September 04, 2013
Rev
0.1
LA-9941P
Sheet
59
of
62
4
3
PC915
4.7U_0603_6.3VAK
2
1
PC916
4.7U_0603_6.3VAK
2
1
PC917
4.7U_0603_6.3VAK
2
1
PC918
4.7U_0603_6.3VAK
2
1
PC919
4.7U_0603_6.3VAK
PC940
4.7U_0603_6.3VAK
2
1
PC941
4.7U_0603_6.3VAK
2
1
PC942
4.7U_0603_6.3VAK
2
1
PC943
4.7U_0603_6.3VAK
2
1
PC944
4.7U_0603_6.3VAK
PC912
4.7U_0603_6.3VAK
2
1
PC939
.1U_0402_16V7K
2
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
PC1001
15P_0402_50V8J
@
2
@
PC999
15P_0402_50V8J
@
1
1
PC969
22U_0805_6.3VAM
2
2
2
2
1
PC968
22U_0805_6.3VAM
PC1002
15P_0402_50V8J
2
1
PC967
22U_0805_6.3VAM
2
2
1
PC966
22U_0805_6.3VAM
PC1000
15P_0402_50V8J
2
1
PC965
22U_0805_6.3VAM
2
@
C
+GPU_CORE
(place near GPU)
EMI Parts
+VCC_CORE
1
PC914
4.7U_0603_6.3VAK
2
1
PC911
4.7U_0603_6.3VAK
2
1
PC938
.1U_0402_16V7K
2
1
1
PC910
4.7U_0603_6.3VAK
2
1
2
PC937
.1U_0402_16V7K
2
1
PC923
330U_D2_2.5VY_R9M
PC924
330U_D2_2.5VY_R9M
PC936
.1U_0402_16V7K
2
1
+GPU_CORE
PC958
47U_0805_6.3V6M
@
PC997
15P_0402_50V8J
@
PC995
15P_0402_50V8J
2
1
@
PC998
15P_0402_50V8J
2
1
@
PC996
15P_0402_50V8J
2
1
PC994
15P_0402_50V8J
2
1
PC993
15P_0402_50V8J
2
1
PC992
15P_0402_50V8J
2
1
PC991
15P_0402_50V8J
2
1
1
2
PC956
10U_0805_6.3V6K
PC955
10U_0805_6.3V6K
PC954
10U_0805_6.3V6K
@
Design guilde:
+VCC_CORE
1. 470uF*4 (SGA0000420L)
2. 22uF*20 (SE000008L80)
3. 10uF*4 (SE160106M8L)
4. 1uF*20 (SE000000K8L)
PC990
4.7U_0805_6.3V6K
@
D
2@
PC964
4.7U_0805_6.3V6K
@
+
PC963
4.7U_0805_6.3V6K
2
2
1
PC962
4.7U_0805_6.3V6K
2
+
PC961
4.7U_0805_6.3V6K
2
1
2@
1
PC959
22U_0805_6.3V6M
2
PC953
10U_0805_6.3V6K
C
1
+
Based on PDDG
rev 1.1 Table 5-2.
+VCC_CORE
1
1
PC922
330U_D2_2.5VY_R9M
1
2
PC935
1U_0402_6.3V6K
2
1
PC934
1U_0402_6.3V6K
PC933
1U_0402_6.3V6K
2
1
PC932
1U_0402_6.3V6K
2
1
PC931
1U_0402_6.3V6K
2
1
1
PC930
1U_0402_6.3V6K
2
1
2
PC929
1U_0402_6.3V6K
PC928
1U_0402_6.3V6K
2
1
PC927
1U_0402_6.3V6K
2
1
2
1
PC926
1U_0402_6.3V6K
2
1
2
PC921
330U_D2_2.5VY_R9M
1
+
1
+GPU_CORE
(place under GPU)
+VCC_CORE
PC909
1U_0402_6.3V6K
PC908
1U_0402_6.3V6K
PC907
1U_0402_6.3V6K
2
1
PC906
1U_0402_6.3V6K
2
1
PC905
1U_0402_6.3V6K
2
1
1
PC904
1U_0402_6.3V6K
2
1
2
PC903
1U_0402_6.3V6K
PC902
1U_0402_6.3V6K
2
1
D
1
+GPU_CORE
PC901
1U_0402_6.3V6K
2
1
2
1
PC900
1U_0402_6.3V6K
2
1
+VCC_CORE
2
PC913
4.7U_0603_6.3VAK
2
1
5
@
B
B
1
2
1
PC970
22U_0805_6.3VAM
1
2
1
PC975
22U_0805_6.3VAM
1
2
2
1
PC971
22U_0805_6.3VAM
2
1
PC976
22U_0805_6.3VAM
1
PC980
22U_0805_6.3VAM
2
2
1
PC972
22U_0805_6.3VAM
2
1
PC977
22U_0805_6.3VAM
1
PC981
22U_0805_6.3VAM
2
2
1
PC973
22U_0805_6.3VAM
2
2
PC974
22U_0805_6.3VAM
Under:
1. 4.7uF*10 (SE000008L80)
2. 0.1uF*4 (SE160106M8L)
Near:
1. 4.7uF*5 (SE093475K80)
2. 22uF*1 (SE000001120)
3. 47uF*1 (SE00000PL0L)
4. 33uF*1 (SGA20331E10)
1
PC978
22U_0805_6.3VAM
1
PC982
22U_0805_6.3VAM
2
2
PC979
22U_0805_6.3VAM
1
PC983
22U_0805_6.3VAM
2
PC984
22U_0805_6.3VAM
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR DECOUPLING
Size
Document Number
Date:
W ednesday, September 04, 2013
Rev
0.1
LA-9941P
Sheet
1
60
of
62
5
4
3
B+
NVDC
CHARGER
BQ24715
DC IN
D
2
+VCC_CORE
ISL95812
TDC: 21A
VGA_CORE
RT8813A
TDC: 45A
1
+VCC_CORE
D
Page 58
Page 53
+GPU_CORE
Page 59
Battery
(3S3P)
C
+VCCP
RT8237E
TDC:6.5A
+1.35V
+0.675VS
G5616A
TDC:7.2A
TDC:0.7A
+VCCP
Page 56
+1.35V
C
+0.675VS
Page 55
+3VALW
TDC:4.6A
+5VALW
TDC:7.9A
TPS51225C
+1.5V_RUN TDC: 9.7A
TPS51367
+5VALW
+3VALW
Page 54
+1.5VS
Page 57
B
B
A
A
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
POWER BLOCK DIAGRAM
Size
Date:
5
4
3
2
Document Number
LA-9941P
Wednesday, September 04, 2013
1
Rev
0.1
Sheet
61
of
62
5
4
[AC in]
2
EC pay attention timing
[Battery only, AC absent]
B+
B+
ACIN
ACIN
Ta
+3VLP
+5VALW
Td
+3VALW
Te
+VSBP
Tf
ITEM
Ta
Tb
Tc
Td
Te
Tf
Tg
Td
Te
+5VALW
PBTN_SW#
[AC in]
+3VALW
Tf
+VSBP
Tg
ITEM
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42
T43
T1
Output PCH_PWR_EN
T2
+3V_PCH
Output
10ms < T3 (DPWROK assert at least 10 ms after VccDSW power are valid)
PCH_DPWROK
10ms < T4 (RSMRST# de-assert at least 10 ms after VccSUS power are valid)
Output PCH_RSMRST#
T5
PCH Output SUSCLK
T6 < 90ms
Output AC_PRESENT
C
16ms < T7 < 4s
Output PBTN_OUT#
Input
PM_SLP_S5#
Input
PM_SLP_S4#
Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable
30us < T8
T9
Output WLAN_EN
T10
+3VS_WLAN
T11
Output SYSON
T12
+1.5V
T13
+1.5V_PWROK
Input
30us < T14
PM_SLP_S3#
T15
Output SUSP#
T16
+5VS
T17
+3VS
T18
+1.5VS
B
T19
+1.8VS
[Battery only, AC absent]
Tc
EC_ON
1ns < Tg < 4s
Discrete Power On Sequence
1ns < Tg < 4s
+3VLP
Tc
1
Ta
PBTN_SW#
Tb
EC_ON
D
3
T20
B+
ACIN
+3VLP
EC_ON
EC_ON
EC_ON
Measure Point
To ACIN
To +3VLP
To EC_ON
To +5VALW
To +3VALW
To +VSBP
PBTN_SW#
Time
Low pluse width
N/A
ITEM
Ta
Tb
Tc
Td
Te
Tf
Tg
B+
Measure Point
To ACIN
PBTN_SW#
Low pluse width
PBTN_SW#
+3VLP
+3VLP
EC_ON
EC_ON
EC_ON
To
To
To
To
To
Time
N/A
D
EC_ON
+5VALW
+3VALW
+VSBP
Time
Measure Point
To PCH_PWR_EN
To +3V_PCH
+3V_PCH
To PCH_DPWROK
+3V_PCH
To PCH_RSMRST#
PCH_RSMRST#
To SUSCLK
PCH_RSMRST#
To AC_PRESENT
PBTN_OUT#
To Low pluse width
PM_SLP_S5#
To PM_SLP_S4#
PM_SLP_S5#
To WLAN_EN
WLAN_EN
To +3VS_WLAN
PM_SLP_S4#
To SYSON
SYSON
To +1.5V
+1.5V
To +1.5V_PWROK
PM_SLP_S4#
To PM_SLP_S3#
PM_SLP_S3#
To SUSP#
SUSP#
To +5VS
SUSP#
To +3VS
SUSP#
To +1.5VS
SUSP#
To +1.8VS
+1.8VS
To +1.8V_PWROK
SUSP#
To +VCCP
+VCCP
To +V1.05S_VCCP_PWRGOOD
+V1.05S_VCCP_PWRGOOD To +VCCSA
+VCCSA
To SA_PGOOD
SA_PGOOD
To VR_ON
CPU1.5V_S3_GATE
To VR_ON
CPU1.5V_S3_GATE
To +1.5V_CPU_VDDQ
CPU1.5V_S3_GATE
To +0.75VSP
+0.75VSP
To HWPG
HWPG
To VR_ON
HWPG
To PCH_PWROK
PCH_PWROK
To PM_DRAM_PWRGD
PM_DRAM_PWRGD
To H_CPUPWRGD
VR_ON
To SVID
H_CPUPWRGD
To +VCC_CORE
+VCC_CORE
To VGATE
VGATE
To SYS_PWROK
SYS_PWROK
To PCH_PLTRST#
SUSP#
To DGPU_PWREN
DGPU_PWREN
To +3VS_DELAY
DGPU_PWREN
To +GPU_CORE
DGPU_PWREN
To +1.5VSDGPU
DGPU_PWREN
To +1.05VSDGPU
PBTN_SW#
PCH_PWR_EN
C
B
+1.8V_PWROK
T21
+VCCP
T22
+V1.05S_VCCP_PWRGOOD
T23
+VCCSA
T24
SA_PGOOD
T25
T26
Output CPU1.5V_S3_GATE
T27
+1.5V_CPU_VDDQ
T28
+0.75VSP
GPU power on sequence
T29
Input HWPG
T30
SUSP#
Output VR_ON
T39
DGPU_PWREN
99ms < T31
Output PCH_PWROK
T40 RC Delay
T32
PCH Output PM_DRAM_PWRGD
+3VS_DELAY
T41 RC Delay
T33
H_CPUPWRGD
+GPU_CORE
T42 RC Delay
5ms > T34
A
SVID
+VCC_CORE
A
+1.5VSDGPU
T35
T43 RC Delay
T36
+1.05VSDGPU
Input VGATE
T37
SYS_PWROK
T38
PCH Output PCH_PLTRST#
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/08/25
Deciphered Date
2012/07/25
Title
Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Wednesday, September 04, 2013
1
Rev
0.1
Sheet
62
of
62
www.s-manuals.com
Source Exif Data:
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