Compal LA A041P Schematics. Www.s Manuals.com. R2.0 Schematics
User Manual: Tablet Acer Iconia Tab W701 - Service manuals and Schematics, Disassembly / Assembly. Free.
Open the PDF directly: View PDF 
.
Page Count: 53
| Download | |
| Open PDF In Browser | View PDF |
A B C D E Compal Confidential 1 Model Name : SAGE 3G Compal Project Name : V1JB1 File Name : LA-A041P 1 Compal Confidential 2 2 V1JB1 UMA M/B Schematics Document Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8 2013-03-26 3 3 REV:2.0 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Tuesday, March 26, 2013 Sheet E 1 of 52 Rev 2.0 A B C D E DDRIII-ON BOARD Memory BUS(DDR3L) 1 1 Dual Channel Fan (PWM) Intel Ivy Bridge ULV eDP Conn. page 34 page 22 Processor BGA1023 120MHz eDP page 11,12 page 4~10 HDMI Conn. FDI x8 page 23 100MHz 100MHz 1GB/s x4 100MHz PCI-Express x 8 (PCIE2.0 5GT/s) port 2 port 1 WLAN Realtek RTS5209 On Board WLAN/BT MD222 page 32 Intel Panther Point-M SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz PCH SMLink Camera1 JCMOS1(FRONT) Camera2 JCMOS2(REAR) Sub/Board USB port 3 page 22 USB port 10 page 27 USB port 11 page 33 Ext. USB3.0 JUSB1 BT - On Board WLAN 3G Module MU736 USB20 port 1 USB30 port 2 USB port 8 USB port 2 page 24 page 13~21 3.3V 24MHz HDA Codec ALC271X-VB6 SUB/B SPI Sub/Board page 25 SPI ROM (ME-2MB) page 13 PROX SENSOR STM8T143 Connect to 2 page 31 page 27 989pin BGA mSATA Module page 24 Touch Screen JEDP1 3.3V 48MHz USBx14 HD Audio port 0,1 Card Reader DMI x4 2.7GT/s TMDS 2 DDRIII-ON BOARD 1.35V DDR3L 1333 Sub/Board Int. Speaker Phone Jack COM_MIC Int. MIC Digital MIC page 33 LPC BUS 33MHz EC 3 3 HSPI RTC CKT. ITE IT 8518 page SMLink1 page 13 Power On/Off CKT. Sub/Board Sensor Hub STM32F page 30 page 29 DC/DC Interface CKT. page 34 Power Circuit DC/DC page 35~46 4 I2C1 Sub/Board ALS CM3218 page 30 TPM SLB9655 page 26 28 WLAN Frequency : 802.11b/g/n : 2.412 ~ 2.4835 GHz 802.11a/n : 5.15 ~ 5. 85GHz BT Frequency : 2.402~2.480 GHz USB Port 0 SMBUS1 FSPI Battery Charger IC WWAN: WCDMA/HSDPA/HSUPA/HSPA+: 850 MHz/900 MHz/1700 MHz(AWS)/1900 MHz/2100 MHz GPRS/EDGE: 850 MHz/900 MHz/1800 MHz/1900 MHz GPS: L1 page 36, 37 ACCEL with E-COMPASS LSM303D GYRO L3GD20TR page 30 SPI ROM (BIOS+EC) (4MB)page 28 SMBUS2 Thermal Sensor 4 page 11 page 30 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Tuesday, March 26, 2013 Sheet E 2 of 52 Rev 0.1 A B C D Voltage Rails Power Plane 1 Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF +1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF +1.35V +1.35VP to +1.35V power rail for DDR3L ON ON OFF +1.35VS +1.35V to +1.35VS switched power rail ON OFF OFF +0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator ON OFF OFF +1.5VS +1.5VSP to +1.5VS power rail for PCH ON OFF OFF +1.8VS (+5VALW or +3VALW) to 1.8VS switched power rail for PCH ON OFF OFF +3VALW +3VALWP to +3VALW always on power rail ON ON ON* +VCCSUS3_3 +3VALW to +VCCSUS3_3 power rail for PCH ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW always on power rail ON ON ON* +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +V5REF_SUS +5VALW to +V5REF_SUS power rail for PCH ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# Vcc Ra/Rc/Re 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. EC SM Bus1 address Device Address Smart Battery 0001 011X b PCH SM Bus address Device EC SM Bus2 address Device Sensor HUB SM Bus address Address Device ChannelA A0 1010 000X Gyroscope ChannelB A4 1010 010X 3 Address Address D1 1101 000X b D3 1101 001X b E-compass + G sensor 33 0011 001X b ALS sensor 21 0010 000X b BOM Config Board ID 0 1 2 3 4 5 6 7 Note : USB Port Table USB 2.0 USB 1.1 Port UHCI1 Sensors List EHCI1 Function Gyroscope Accel+E-Compass Sensor Hub ALS Prox Device ST - L3GD20TR ST - LSM303DLHCTR ST - STM32F103RCY6TR Capella - CM3218 ST-STM8T143AU62TTRC06 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 4 UHCI6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 2 External USB Port Sensor Hub Ext. USB Connector 3G Module - MU736/ME906 Touch Screen BlueTooth(WLAN Module) Debug Port(Reserve) Camera(Front) Camera(Rear) BTO Item BOM Structure Unpop @ Connector CONN@ UMA UMA@ CPU IVB@ DDR3 DDR3@ DDR3L DDR3L@ On Board DRAM X76@ Dual Channel DDR 128@ eDP eDP@ PCH HM77@ Normal S3 S3@ Deep S3 DS3@ TPM TPM@ Non TPM SKU WOTPM@ Hall Sensor LID@ Foxconn MD222 FOXMD222@ Lite-On MD222 LIONMD222@ For EMI/RF(Pop) EMC@ For EMI/RF(Unpop) XEMC@ Sensor(Intel F/W) INTEL@ Sensor(ST F/W) ST@ 3G@ 3G SKU 3G SKU(EMC part) 3GEMC@ 2011/06/24 3 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 2.0* UHCI0 Connect to Sensor Hub Sensor Hub PCH(USB P3) Sensor Hub EC 1 Board ID / SKU ID Table for AD channel Board ID 2 SIGNAL STATE E 2012/06/02 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 3 of 52 Rev 0.1 A B C D E +1.05VS_VTT 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms R532 24.9_0402_1% 15 15 15 15 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 N3 P7 P3 P11 15 15 15 15 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 15 15 15 15 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 15 15 15 15 15 15 15 15 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 15 15 15 15 15 15 15 15 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U7 W11 W1 AA6 W6 V4 Y2 AC9 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11 1 15 FDI_INT 2 R118 24.9_0402_1% Add eDP circuit W=4mil,S=15mil,L=500mil EDP_HPD# AF3 AD2 AG11 AG4 AF4 22 EDP_AUXN 22 EDP_AUXP AC3 AC4 AE11 AE7 1 22 EDP_TXN0 22 EDP_TXN1 AC1 AA4 AE10 AE6 22 EDP_TXP0 22 EDP_TXP1 2 R809 1K_0402_5% EDP_COMP EDP_HPD# DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP +1.05VS_VTT AA10 AG8 15 FDI_LSYNC0 15 FDI_LSYNC1 W=12mil,S=15mil,L=500mil 22 EDP_HPD# K3 M7 P4 T3 15 FDI_FSYNC0 15 FDI_FSYNC1 3 eDP@ K1 M8 N4 R2 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS -- GRAPHICS M2 P6 P1 P10 Intel(R) FDI +1.05VS_VTT eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms should not be left floating ,even if disable eDP function... DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI 2 15 15 15 15 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] G3 G1 G4 H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 PEG_ICOMPO signals should be routed with - max length = 500 milstypical impedance = 14.5 mohms 2 UCPU1A 1 PEG_COMP 1 G3,W=4mil,S=15mil,L=500mil G1,W=12mil,S=15mil,L=500mil G4,W=4mil,S=15mil,L=500mil UCPU1_B22 @ T25 PAD @ T26 PAD @ T27 PAD @ T22 @ T34 PAD PAD @ T39 PAD UCPU1_A19 UCPU1_B14 UCPU1_A11 UCPU1_B10 SAGE 3G PVT For DFB demand UCPU1_B6 2 UMA only=>PEG NC G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 3 IVY-BRIDGE_BGA1023 IVB@ CPU P/N: 1.I3-3217 SA00005L5C0:S IC AV8063801058401 SR0N9 L1 1.8G ABO! 2.I5-3317 SA00005K6B0:S IC AV8063801058002 SR0N8 L1 1.7G ABO! 3.I3-2365 SA000051H60:S IC AV8062701047904 SR0CV J1 1.4G ABO! 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title PROCESSOR(1/7) DMI,FDI,PEG Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Sheet W ednesday, March 13, 2013 E 4 of 52 A B C D E 1 1 UCPU1B 17 H_SNB_IVB# Follow DG 1.2 & CRB1.0 C57 T1 @ PAD H_CATERR# C49 H_PECI A48 PROC_DETECT# @ 1 0.1U_0201_10V6K H_CPUPWRGD 1 10K_0402_5% H_CPUPWRGD Processor Pullups follow CRB1.0 R223 2 R220 2 +1.05VS_VTT 28 H_PECI 1 62_0402_5% H_PROCHOT# 28,36 H_PROCHOT# R216 56_0402_5% 1 2 H_PROCHOT#_R D45 18 H_THRMTRIP# Follow DG 1.2 & CRB1.0 +3VS SAGE 3G 5 P 2 R227 43_0402_1% 1 2 BUFO_CPU_RST# R80 18 H_CPUPWRGD 1 UNCOREPWRGOOD: BUF_CPU_RST# 0_0402_5% 2 H_CPUPWRGD_R B46 @ 除除CPU_CORE以以以以OK PM_DRAM_PWRGD_R G 3 RESET#: C48 15 H_PM_SYNC R226 75_0402_5% BE45 都ok後後CPU做reset BUF_CPU_RST# SAGE 3G D44 +1.05VS_VTT CLK_CPU_DPLL 14 CLK_CPU_DPLL# 14 CLK_CPU_DPLL# R116 2 @ 1 1K_0402_5% CLK_CPU_DPLL R117 2 @ 1 1K_0402_5% SM_DRAMRST# BF44 BE43 BG43 SM_RCOMP0 R149 SM_RCOMP1 R486 SM_RCOMP2 R484 SM_DRAMRST# 6 2 2 2 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK SM_DRAMPWROK:DRAM power ok SN74LVC1G07DCKR_SC70-5 CLK_CPU_DPLL CLK_CPU_DPLL# AT30 THERMTRIP# TCK TMS TRST# C396 0.1U_0402_16V4Z 4 Y A SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] +1.05VS_VTT U15 NC 2 17,26,28,31,32 PLT_RST# SM_DRAMRST# PRDY# PREQ# 2 1 PROCHOT# PWR MANAGEMENT 1 PECI Use open drain MOS: +1.05VS_VTT PH pop 75ohm series resister pop 43ohm 1 Buffered reset to CPU 2 C45 AG3 AG1 CLK_CPU_DMI 14 CLK_CPU_DMI# 14 Checklist1.0 P.64 Processor Graphis Disable Guide DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT RESET# JTAG & BPM 2 C784 DPLL_REF_CLK DPLL_REF_CLK# J3 H2 CATERR# THERMAL 偵偵CPU有有有有 XBOX 三三三三 PROC_SELECT# BCLK BCLK# CLOCKS F49 DDR3 MISC 外外外 PCH->CPU UNCOREPWRGOOD: CORE OK SM_DRAMPWROK:DRAM power ok RESET#: ok CPU reset MISC 非 都 後後 做 PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS TDI TDO N53 N55 L56 L55 J58 XDP_TCK XDP_TMS XDP_TRST# @ PAD @ PAD @ PAD T2 T3 T4 M60 L59 XDP_TDI XDP_TDO @ PAD @ PAD T5 T6 K58 XDP_DBRESET# 2 +3VS DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_DBRESET# R569 2 XDP_DBRESET# 15 G58 E55 E59 G55 G59 H60 J59 J61 1 2 1 1K_0402_5% CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm SAGE 3G C102 XEMC@ 100P_0402_50V8J For EMI IVY-BRIDGE_BGA1023 IVB@ 3 3 +3VALW Follow DG 1.2 & CRB1.0 1 1 C101 0.1U_0402_16V4Z +1.35VS R88 200_0402_5% 2 0_0402_5% R81 1 @ 2 0_0402_5% 1 B A Y 3 15 PM_DRAM_PWRGD U5 2 5 @ P 1 G 15 SYS_PWROK R82 2 2 28,42 VR_ON Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm 4 PM_SYS_PWRGD_BUF 1 R97 2 130_0402_5% PM_DRAM_PWRGD_R MC74VHC1G09DFT2G_SC70-5 SAGE 3G 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 5 of 52 Rev 0.1 A B C D UCPU1C UCPU1D 12 DDR_B_D[0..63] 2 BD37 BF36 BA28 11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2 3 AT40 AU40 BB26 DDR_A_CLK1 DDR_A_CLK1# R263 75_0402_1% DDR_A_CKE1 11 SA_CS#[0] SA_CS#[1] BB40 BC41 DDR_A_CS0# 11 DDR_A_CS1# 11 SAGE 3G PVT SA_ODT[0] SA_ODT[1] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_CAS# SA_RAS# SA_WE# AY40 BA41 DDR_A_ODT0 11 DDR_A_ODT1 11 AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS#[0..7] 11 AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS[0..7] 11 BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA[0..15] 11 BG39 BD42 AT22 12 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2 AV43 BF40 BD45 12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE# IVY-BRIDGE_BGA1023 IVB@ SB_CK[0] SB_CK#[0] SB_CKE[0] BA34 AY34 AR22 DDR_B_CLK0 12 DDR_B_CLK0# 12 DDR_B_CKE0 12 1 SB_CK[1] SB_CK#[1] SB_CKE[1] BA36 BB36 BF27 DDR_B_CLK1 DDR_B_CLK1# R264 75_0402_1% DDR_B_CKE1 12 SB_CS#[0] SB_CS#[1] BE41 BE47 DDR_B_CS0# 12 DDR_B_CS1# 12 SAGE 3G PVT SB_ODT[0] SB_ODT[1] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AT43 BG47 DDR_B_ODT0 12 DDR_B_ODT1 12 AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0..7] 12 AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0..7] 12 BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 2 DDR_B_MA[0..15] 12 3 Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16 IVY-BRIDGE_BGA1023 IVB@ +1.35V 1 Follow CRB1.0 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] 1 DDR_A_CLK0 11 DDR_A_CLK0# 11 DDR_A_CKE0 11 AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 2 AU36 AV36 AY26 1 SA_CK[1] SA_CK#[1] SA_CKE[1] SA_BS[0] SA_BS[1] SA_BS[2] BE39 BD39 AT41 11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE# SA_CK[0] SA_CK#[0] SA_CKE[0] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 2 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR SYSTEM MEMORY A AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR SYSTEM MEMORY B 11 DDR_A_D[0..63] 1 E 通通DIMM做reset SAGE 3G DVT R66 1K_0402_5% 2 CPU 1 DIMM_DRAMRST#_R Q6 BSS138_NL_SOT23-3 2 SM_DRAMRST# D 3 S 5 SM_DRAMRST# 1 2 G R79 4.99K_0402_1% 4 14 DRAMRST_CNTRL_PCH 28 DRAMRST_CNTRL_EC R413 1 DS3@ 2 0_0402_5% 1 C78 .047U_0402_16V7K 2 SAGE 3G 1 R63 1K_0402_5% 2 DIMM_DRAMRST# 11,12 S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B PROCESSOR(3/7) DDRIII C D Wednesday, March 13, 2013 Sheet E 6 of 52 Rev 0.1 A B C D E Default "1",EDS R1.0 P.88 CFG Straps for Processor UCPU1E CFG2 +CPU_CORE CFG4 CFG5 CFG6 CFG7 2 1 1 R810 @ 49.9_0402_1% VCC_VAL_SENSE 2 VSS_VAL_SENSE R812 @ 49.9_0402_1% H43 K43 1 VCC_VAL_SENSE VSS_VAL_SENSE H45 K45 VAXG_VAL_SENSE VSSAXG_VAL_SENSE +VGFX_CORE F48 PAD @ VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE BCLK_ITP BCLK_ITP# RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 N59 N58 CLK_RES_ITP 14 CLK_RES_ITP# 14 1: Normal Operation; Lane # definition matches socket pin map definition CFG2 * N42 L42 L45 L47 0:Lane Reversed 1 CFG2 M13 M14 U14 W14 P13 R234 1K_0402_1% AT49 K24 eDP enable AH2 AG13 AM14 AM15 CFG4 * 1:Disable 0:Enable N50 2 T56 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] 1 B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CFG0 2 PAD @ RESERVED T72 PEG Static Lane Reversal - CFG2 is for the 16x IVY-BRIDGE_BGA1023 IVB@ 3 2 1 CFG4 DC_TEST_C4_D3 eDP@ R204 1K_0402_1% DC_TEST_A59_C59 2 A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1 DC_TEST_A61_C61 PCIE Port Bifurcation Straps DC_TEST_BE59_BE61 DC_TEST_BG59_BG61 CFG[6:5] (Default) 1x16 PCI Express *11: 10: 2x8 PCI Express 01: Reserved DC_TEST_BE3_BG3 00: 1x8,2x4 PCI Express DC_TEST_BE1_BG1 These pins are for solder joint reliability and non-critical to function. For BGA only. CFG6 CFG5 1 1 R813 @ 49.9_0402_1% RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 1 2 VSSAXG_VAL_SENSE BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 R230 1K_0402_1% @ @ 2 1 VAXG_VAL_SENSE RSVD6 RSVD7 2 H48 K48 R811 @ 49.9_0402_1% 2 PEG DEFER TRAINING CFG7 3 R228 1K_0402_1% CRB1.0 P.12 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training 1 CFG7 R224 1K_0402_1% 2 @ 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C 4 D Title PROCESSOR(4/7) RSVD,CFG Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Sheet W ednesday, March 13, 2013 E 7 of 52 A B C UCPU1F ULV SC/DC 33A D POWER E 8.5A +1.05VS_VTT VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] 3 INTEL Recommend VCCIO PD 0.9 1 330uF 1+1 10uF (0603) *5 1uF (0201) *16 +1.05VS_VTT AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 330uF 1 10uF (0603) *5 1uF (0201) *10 +3VALW 2 VCCIO_SEL For 2012 CPU support R521 10K_0402_5% +1.05VS_VTT A19 W16 W17 BC22 1 : +1.05VS_VTT 0: +1.0VS_VTT VCCIO_SEL R520 10K_0402_5% VCCIO_SEL * 1 VCCIO50 VCCIO51 2 1 VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] 1 VCCIO_SEL_R @ 2 2 AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 R582 @ 2 0_0402_5% +1.05VS_VTT +1.05VS_VTT VCCPQE[1] VCCPQE[2] AM25 AN22 C951 1U_0402_6.3V6K R574 130_0402_5% 3 VIDALERT# VIDSCLK VIDSOUT A44 B43 C44 R576 1 R577 1 R578 1 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT VR_SVID_ALRT# 42 VR_SVID_CLK 42 VR_SVID_DAT 42 +CPU_CORE VCC_SENSE VSS_SENSE F43 VCCSENSE_R G43 VSSSENSE_R R579 1 R581 1 2 0_0402_5% 2 0_0402_5% @ @ R588 100_0402_1% 2 Place the PU,PD resistors close to CPU VCCSENSE 42 VSSSENSE 42 1 R107 AN16 AN17 2 10_0402_5% VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE 1 VCCIO_SENSE VSS_SENSE_VCCIO 1 +1.05VS_VTT R589 100_0402_1% 40 Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor. VSSSENSE:100ohm ±1% pull-down to GND near processor. 2 SENSE LINES 2 43_0402_1% 2 0_0402_5% 2 0_0402_5% @ @ 1 SVID 2 2 Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7 SAGE 3G 1 1 1 VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] QUIET RAILS A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 CORE SUPPLY INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9 PEG IO AND DDR IO +CPU_CORE R105 10_0402_5% 2 IVY-BRIDGE_BGA1023 IVB@ 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 4 Should change to connect from power cirucit & layout differential with VCCIO_SENSE. 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(5/7) PWR,BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 8 of 52 Rev 0.1 B ULV SC/DC GT1: 18A GT2: 33A C1181 2 1 2 C1179 1 2 1U_0402_6.3V6K 1 C1180 1U_0402_6.3V6K 2 C607 330U_B2_2VM_R15M SGA00004700 1U_0402_6.3V6K 1 1 2 2 1 C997 10U_0603_6.3V6M 1 C996 10U_0603_6.3V6M 2 C995 10U_0603_6.3V6M INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402) PD0.9 2 1 1 2 2 1 + C599 330U_B2_2VM_R15M SGA00004700 C970 1 C987 1 C989 @ 2 2 @ 2 2 C990 1 C998 1 SAGE 3G C999 1 1 2 @ 2 2 2 C979 1 2 C978 1 Place BOT OUT Conn 6A L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 VCCPLL[1] VCCPLL[2] VCCPLL[3] VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16] QUIET RAILS SENSE LINES VCCDQ[1] VCCDQ[2] 2 AM28 AN26 1 2 SAGE 3G 3 VDDQ_SENSE VSS_SENSE_VDDQ BC43 BA43 VCCSA_VID For 2012 future CPU VCCSA voltage select SAGE 3G VCCSA_SENSE VCCSA_VID[0] VCCSA_VID[1] U10 @ VCCSA_SENSE CPU EDS1.3 P.93 VCCSA_VID0 Must PD D48 D49 H_VCCSA_VID0 H_VCCSA_VID1 VCCSA T55 PAD H_VCCSA_VID0 H_VCCSA_VID1 VID0 VID1 Vout SNB IVB ULV 0 0 0.9V V V V 0 1 0.8V V V 1 0 0.725V X V V 1 1 0.675V X V V 41 41 R129 0_0402_5% @ 0.85V V 2 IVY-BRIDGE_BGA1023 IVB@ 4 2 1 VREF - 1.5V RAILS DDR3 GRAPHICS 2 1 BB3 BC1 BC4 1.8V RAIL 1.2A SENSE LINES SAGE 3G +VCCSA + VAXG_SENSE VSSAXG_SENSE VCCSA VID lines +VCCSA C977 1 +1.35VS 10U_0603_6.3V6M 2 Short for +1.35VS to +1.35V_CPU_VDDQ 10U_0603_6.3V6M 2 INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9 10U_0603_6.3V6M 2 C606 220U_B2_2.5VM_R15M SGA00004I00 1 @ R68 1K_0402_1% SAGE 3G AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 R540 1K_0402_1% 2 5A VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26] 1 C647 0.1U_0402_16V4Z 10U_0603_6.3V6M + C584 1U_0402_6.3V6K 1 100_0402_5% +1.8VS_VCCPLL R500 0_0805_5% 2 @ SA_DIMM_VREFDQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ @ R69 1K_0402_1% 2 1 +V_SM_VREF BE7 BG7 10U_0603_6.3V6M 1 1 AY43 C985 1U_0402_6.3V6K F45 G45 R396 C583 1U_0402_6.3V6K +1.35VS R534 1K_0402_1% +1.35VS 42 VCC_AXG_SENSE 42 VSS_AXG_SENSE 1 SM_VREF 2 100_0402_5% +1.8VS SAGE 3G VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56] 1U_0402_6.3V6K +VGFX_CORE R381 1 3 +V_SM_VREF should have 20 mil trace width 10U_0603_6.3V6M Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor. J16 @ 2 1 2 JUMP_43X39 POWER 1U_0402_6.3V6K 2 INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9 E +1.35VS 1U_0402_6.3V6K AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 1 1 UCPU1G D SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC +VGFX_CORE SA RAIL INTEL Recommend VAXG 2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9 C 1 A 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 9 of 52 Rev 0.1 A B C D E UCPU1H UCPU1I A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 2 3 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] 1 AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS NCTF 1 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48 A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61 2 @ @ @ @ @ @ @ @ @ @ @ @ @ @ PAD T58 PAD T59 PAD T60 PAD T61 PAD T62 PAD T63 PAD T64 PAD T65 PAD T66 PAD T67 PAD T68 PAD T69 PAD T70 PAD T71 3 CR CheckList Rev1.5 IVY-BRIDGE_BGA1023 IVB@ IVY-BRIDGE_BGA1023 IVB@ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 10 of 52 Rev 0.1 A B C D E Channel A DDR_A_MA[0..15] 6 DDR_A_MA[0..15] DDR_A_DQS#[0..7] 6 DDR_A_DQS#[0..7] DDR_A_DQS[0..7] 6 DDR_A_DQS[0..7] DDR_A_D[0..63] DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 DDR_A_DQS1 DDR_A_DQS0 F3 C7 E7 D3 12,6 DIMM_DRAMRST# SAGE 3G PVT DDR_A_DQS#1 DDR_A_DQS#0 G3 B7 DIMM_DRAMRST# T2 1 R992 2 240_0402_1% L8 DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1 1 R996 2 240_0402_1% J1 L1 J9 L9 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 SAGE 3G A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 M2 N8 M3 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 J7 K7 K9 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 DDR_A_DQS2 DDR_A_DQS3 F3 C7 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 SAGE 3G PVT DDR_A_DQS#2 DDR_A_DQS#3 G3 B7 DIMM_DRAMRST# T2 1 R993 2 240_0402_1% L8 DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1 1 R997 2 240_0402_1% J1 L1 J9 L9 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +VREFDQ_A 1 2 +1.35V BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 B2 D9 G7 K2 K8 N1 N9 R1 R9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 M2 N8 M3 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 J7 K7 K9 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 DDR_A_DQS4 DDR_A_DQS5 F3 C7 @ SAGE 3G A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 SAGE 3G PVT DDR_A_DQS#4 DDR_A_DQS#5 G3 B7 DIMM_DRAMRST# T2 1 R994 2 240_0402_1% L8 DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1 1 R998 2 240_0402_1% J1 L1 J9 L9 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR_A_D32 DDR_A_D34 DDR_A_D33 DDR_A_D39 DDR_A_D37 DDR_A_D35 DDR_A_D36 DDR_A_D38 D7 C3 C8 C2 A7 A2 B8 A3 DDR_A_D42 DDR_A_D45 DDR_A_D47 DDR_A_D44 DDR_A_D46 DDR_A_D40 DDR_A_D43 DDR_A_D41 BA0 BA1 BA2 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DML DMU DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 1 2 2 R1104 1K_0402_1% +1.35V Layout Note: Place near each memory part 1 R1108 1K_0402_1% 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C1464 330U_D2_2V_Y C1474 10U_0603_6.3V6M C1472 10U_0603_6.3V6M C1473 10U_0603_6.3V6M C1465 10U_0603_6.3V6M C1475 10U_0603_6.3V6M C1463 10U_0603_6.3V6M C1479 10U_0603_6.3V6M C1469 10U_0603_6.3V6M + 2 R1107 1K_0402_1% 1 2 2.2U_0603_6.3V6K C1482 0.1U_0402_16V4Z C1483 +1.35V 4 2 near U57 near U58 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 G3 B7 T2 DIMM_DRAMRST# SAGE 3G PVT 1 R995 2 240_0402_1% L8 DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1 1 R999 2 240_0402_1% J1 L1 J9 L9 RP32 1 2 3 4 8 7 6 5 RP33 1 2 3 4 8 7 6 5 RP34 1 2 3 4 8 7 6 5 RP35 1 2 3 4 8 7 6 5 1 R332 2 1 R333 1 R335 1 R336 2 DDR_A_D63 DDR_A_D57 DDR_A_D58 DDR_A_D60 DDR_A_D59 DDR_A_D56 DDR_A_D62 DDR_A_D61 +1.35V BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU 2 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 3 0.1U_0402_16V4Z 6 6 6 6 R1102 30.1_0402_1% R1103 30.1_0402_1% DDR_A_CS0# 6 DDR_A_WE# 6 END topology 6 DDR_A_CLK0 DDR_A_BS0 6 DDR_A_BS1 6 DDR_A_BS2 6 6 DDR_A_CLK0# 1 C1457 1.8P_0402_50V8 2 External DDR Thermal Sensor+3VS 1.CAD Note: Cterm= 1.8pF should be kept near feeding point of first SDRAM C97 1 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM 2 0.1U_0402_16V4Z U4 1 33 TM_D+ 33 TM_D- DDR_A_MA7 36_0201_1% DDR_A_CKE1 36_0201_1% 2 DDR_A_CS1# 36_0201_1% 2 DDR_A_ODT1 36_0201_1% D7 C3 C8 C2 A7 A2 B8 A3 1 1 8 7 6 5 DDR_A_ODT0 DDR_A_RAS# DDR_A_CAS# DDR_A_CKE0 1 RP31 1 2 3 4 DDR_A_ODT0 DDR_A_RAS# DDR_A_CAS# DDR_A_CKE0 36_8P4R_5% DDR_A_CS0# DDR_A_MA10 DDR_A_WE# DDR_A_MA15 36_8P4R_5% DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA12 36_8P4R_5% DDR_A_MA3 DDR_A_MA4 DDR_A_MA0 DDR_A_MA1 36_8P4R_5% DDR_A_MA2 DDR_A_MA11 DDR_A_MA5 DDR_A_MA6 36_8P4R_5% DDR_A_MA9 DDR_A_MA14 DDR_A_MA13 DDR_A_MA8 36_8P4R_5% DDR_A_D52 DDR_A_D54 DDR_A_D48 DDR_A_D50 DDR_A_D53 DDR_A_D55 DDR_A_D49 DDR_A_D51 2 8 7 6 5 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR3 CLK Termination C1458 1 2 RP30 1 2 3 4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ TM_D+ 2 TM_D- 3 4 DDR_A_CS1# 6 C233 DDR_A_ODT1 6 2 VDD D+ SCLK SDATA D- ALERT# THERM# GND 8 EC_SMB_CK2 14,28 7 6 EC_SMB_DA2 14,28 1 R546 2 +3VS 10K_0402_5% 5 W83L771AWG-2 TSSOP8P SA00003PU00 1 DDR_A_CKE1 6 4 SA00003PU00 S IC W83L771AWG-2 TSSOP 8P SENSOR 2200P_0402_50V7K SAGE 3G PVT Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title DDRIII DIMMA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. near U59 Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: A F3 C7 VREFCA VREFDQ SAGE 3G Issued Date near U56 J7 K7 K9 1 +VREFCA_A 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 C1468 1U_0402_6.3V6K C1478 1U_0402_6.3V6K C1471 1U_0402_6.3V6K C1470 1U_0402_6.3V6K C1467 1U_0402_6.3V6K C1477 1U_0402_6.3V6K C1476 1U_0402_6.3V6K C1466 1U_0402_6.3V6K 1 +1.35V 1 C1481 0.1U_0402_16V4Z SAGE 3G DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 DDR_A_DQS#6 DDR_A_DQS#7 2 2 +VREFDQ_A 1 1 2 1 2 1 2 1 2 1 2 1 2 2 1 R1106 1K_0402_1% C1480 2.2U_0603_6.3V6K 2 C1511 1U_0402_6.3V6K C1512 1U_0402_6.3V6K C1513 1U_0402_6.3V6K C1514 1U_0402_6.3V6K C1459 1U_0402_6.3V6K C1460 1U_0402_6.3V6K C1461 1U_0402_6.3V6K C1462 1U_0402_6.3V6K 1 1 +1.35V M2 N8 M3 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +0.675VS SAGE 3G DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_A_DQS6 DDR_A_DQS7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 @ SAGE 3G SAGE 3G +0.675VS 2 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU 2 1 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD 1 +VREFDQ_A +1.35V DDR3 CTL/ADD Termination 3 M8 H1 1 DDR_A_D25 DDR_A_D29 DDR_A_D27 DDR_A_D28 DDR_A_D31 DDR_A_D30 DDR_A_D26 DDR_A_D24 1 U59 +VREFCA_A VREFCA VREFDQ 2 D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 1 1 2 2 VDD VDD VDD VDD VDD VDD VDD VDD VDD @ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DDR_A_D16 DDR_A_D19 DDR_A_D20 DDR_A_D18 DDR_A_D22 DDR_A_D23 DDR_A_D17 DDR_A_D21 C1263 2.2U_0603_6.3V6K J7 K7 K9 BA0 BA1 BA2 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 C1262 0.1U_0402_16V4Z DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 C1261 2.2U_0603_6.3V6K M2 N8 M3 2 +VREFDQ_A +1.35V N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 U58 +VREFCA_A VREFCA VREFDQ C1260 0.1U_0402_16V4Z SAGE 3G DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_D3 DDR_A_D1 DDR_A_D2 DDR_A_D4 DDR_A_D7 DDR_A_D0 DDR_A_D6 DDR_A_D5 1 C1259 2.2U_0603_6.3V6K @ D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 C1254 0.1U_0402_16V4Z C1258 2.2U_0603_6.3V6K C1253 0.1U_0402_16V4Z 2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DDR_A_D8 DDR_A_D10 DDR_A_D13 DDR_A_D11 DDR_A_D12 DDR_A_D15 DDR_A_D9 DDR_A_D14 0.1U_0402_16V4Z C1257 +VREFDQ_A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_16V4Z C1256 2 1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 0.1U_0402_16V4Z C1255 0.1U_0402_16V4Z C1252 1 U57 +VREFCA_A VREFCA VREFDQ 1 M8 H1 2 U56 +VREFCA_A 1 2 6 DDR_A_D[0..63] B C D Wednesday, March 13, 2013 E Sheet 11 of 52 B 6 DDR_B_D[0..63] 6 DDR_B_MA[0..15] 6 SAGE 3G DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 F3 C7 E7 D3 2 11,6 DIMM_DRAMRST# SAGE 3G PVT DDR_B_DQS#1 DDR_B_DQS#0 G3 B7 DIMM_DRAMRST# T2 1 R1005 2 128@ 240_0402_1% L8 DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1 1 R1009 2 240_0402_1% J1 L1 J9 L9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 128@ B2 D9 G7 K2 K8 N1 N9 R1 R9 2 1 1 2 DDR_B_DQS1 DDR_B_DQS0 BA0 BA1 BA2 1 @ SAGE 3G A1 A8 C1 C9 D2 E9 F1 H2 H9 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 DDR_B_DQS2 DDR_B_DQS3 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 F3 C7 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 SAGE 3G PVT DDR_B_DQS#2 DDR_B_DQS#3 G3 B7 DIMM_DRAMRST# T2 1 R1006 2 128@ 240_0402_1% L8 DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1 1 R1010 2 240_0402_1% J1 L1 J9 L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DDR_B_D24 DDR_B_D26 DDR_B_D29 DDR_B_D31 DDR_B_D25 DDR_B_D30 DDR_B_D28 DDR_B_D27 BA0 BA1 BA2 128@ CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DML DMU DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 F3 C7 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_B_DQS4 DDR_B_DQS5 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 @ SAGE 3G A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU 1 2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD 2 128@ +VREFDQ_B +1.35V 128@ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ D7 C3 C8 C2 A7 A2 B8 A3 1 SAGE 3G PVT DDR_B_DQS#4 DDR_B_DQS#5 G3 B7 DIMM_DRAMRST# T2 1 R1007 2 128@ 240_0402_1% L8 DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1 1 R1011 2 240_0402_1% J1 L1 J9 L9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 DDR_B_D40 DDR_B_D46 DDR_B_D45 DDR_B_D42 DDR_B_D41 DDR_B_D43 DDR_B_D44 DDR_B_D47 M8 H1 1 2 128@ +VREFDQ_B 1 128@ +1.35V BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 128@ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ DDR_B_D34 DDR_B_D36 DDR_B_D39 DDR_B_D37 DDR_B_D35 DDR_B_D32 DDR_B_D38 DDR_B_D33 2 B2 D9 G7 K2 K8 N1 N9 R1 R9 C1302 2.2U_0603_6.3V6K J7 K7 K9 128@ +1.35V VREFCA VREFDQ U63 +VREFCA_B E3 F7 F2 F8 H3 H8 G2 H7 C1301 0.1U_0402_16V4Z DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 +VREFDQ_B N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 C1291 2.2U_0603_6.3V6K M2 N8 M3 DDR_B_D5 DDR_B_D6 DDR_B_D2 DDR_B_D3 DDR_B_D0 DDR_B_D7 DDR_B_D4 DDR_B_D1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 C1300 0.1U_0402_16V4Z SAGE 3G DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 D7 C3 C8 C2 A7 A2 B8 A3 2 128@ C1293 2.2U_0603_6.3V6K @ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 1 C1299 0.1U_0402_16V4Z 2 C1292 2.2U_0603_6.3V6K 1 C1298 0.1U_0402_16V4Z 128@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M8 H1 0.1U_0402_16V4Z C1297 +VREFDQ_B VREFCA VREFDQ DDR_B_D23 DDR_B_D21 DDR_B_D18 DDR_B_D17 DDR_B_D19 DDR_B_D20 DDR_B_D22 DDR_B_D16 SAGE 3G U62 +VREFCA_B E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_16V4Z C1296 2 128@ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 M8 H1 0.1U_0402_16V4Z C1295 0.1U_0402_16V4Z C1294 1 DDR_B_D14 DDR_B_D8 DDR_B_D15 DDR_B_D9 DDR_B_D11 DDR_B_D12 DDR_B_D10 DDR_B_D13 SAGE 3G U61 +VREFCA_B E3 F7 F2 F8 H3 H8 G2 H7 2 M8 H1 1 SAGE 3G U60 +VREFCA_B E 1 6 DDR_B_DQS[0..7] 1 DDR_B_DQS#[0..7] D 2 Channel B C 2 A N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 B1 B9 D1 D8 E2 E8 F9 G1 G9 SAGE 3G PVT G3 B7 DIMM_DRAMRST# T2 1 R1008 2 128@ 240_0402_1% L8 DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1 1 R1012 2 240_0402_1% J1 L1 J9 L9 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 DDR_B_D49 DDR_B_D55 DDR_B_D52 DDR_B_D51 DDR_B_D53 DDR_B_D50 DDR_B_D48 DDR_B_D54 1 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 128@ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ DDR_B_D58 DDR_B_D56 DDR_B_D63 DDR_B_D60 DDR_B_D62 DDR_B_D61 DDR_B_D59 DDR_B_D57 +1.35V BA0 BA1 BA2 E7 D3 DDR_B_DQS#7 DDR_B_DQS#6 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 F3 C7 DDR_B_DQS7 DDR_B_DQS6 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VREFCA VREFDQ @ SAGE 3G A1 A8 C1 C9 D2 E9 F1 H2 H9 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 E3 F7 F2 F8 H3 H8 G2 H7 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +1.35V +0.675VS 1 +1.35V 2 128@ 1 1 2 1 2 1 2 1 2 1 2 1 2.2U_0603_6.3V6K C1507 @ C1496 10U_0603_6.3V6M @ C1485 10U_0603_6.3V6M @ C1500 10U_0603_6.3V6M C1490 10U_0603_6.3V6M @ 128@ 0.1U_0402_16V4Z C1508 R1119 1K_0402_1% 128@ +1.35V +VREFCA_B 2 @ 2 2 @ 2 1 1 1 2 2 @ R1120 1K_0402_1% 128@ C1488 1U_0402_6.3V6K @ C1498 1U_0402_6.3V6K C1497 1U_0402_6.3V6K C1487 1U_0402_6.3V6K 1 1 +1.35V 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 DDR_B_ODT0 DDR_B_CKE0 DDR_B_RAS# DDR_B_CAS# 6 6 6 6 DDR_B_CS0# 6 DDR_B_WE# 6 DDR_B_BS0 6 DDR_B_BS2 DDR_B_BS1 6 6 SAGE 3G 128@ DDR3 CLK Termination C1506 1 2 0.1U_0402_16V4Z 1 memory part DDR_B_ODT0 DDR_B_CKE0 DDR_B_RAS# DDR_B_CAS# 36_8P4R_5% DDR_B_CS0# DDR_B_WE# DDR_B_MA10 DDR_B_BS0 36_8P4R_5% DDR_B_MA15 DDR_B_BS2 DDR_B_BS1 DDR_B_MA0 36_8P4R_5% DDR_B_MA12 DDR_B_MA3 DDR_B_MA1 DDR_B_MA2 36_8P4R_5% DDR_B_MA4 DDR_B_MA5 DDR_B_MA11 DDR_B_MA9 36_8P4R_5% DDR_B_MA6 DDR_B_MA7 DDR_B_MA14 DDR_B_MA13 36_8P4R_5% 1 2 5 6 7 8 R1117 30.1_0402_1% 128@ R1118 30.1_0402_1% 128@ 2 1 RP36 4 3 2 1 128@ RP37 4 3 2 1 128@ RP38 4 3 2 1 128@ RP39 4 3 2 1 128@ RP40 4 3 2 1 128@ RP41 4 3 2 1 128@ 2 2 2 R1121 1K_0402_1% 128@ 128@ Layout Note: Place near each DDR3 CTL/ADD Termination 3 128@ C1510 0.1U_0402_16V4Z 1 1 2 2 SAGE 3G @ +VREFDQ_B 2 1 1 1 2 2 @ +0.675VS C1509 2.2U_0603_6.3V6K @ SAGE 3G R1123 1K_0402_1% 128@ C1501 1U_0402_6.3V6K @ C1502 1U_0402_6.3V6K C1503 1U_0402_6.3V6K 3 C1504 1U_0402_6.3V6K 1 SAGE 3G END topology 1 128@ R390 1 128@ R339 1 128@ R340 1 128@ R342 4 2 DDR_B_MA8 36_0201_1% 6 DDR_B_CLK0 2 DDR_B_CKE1 6 2 DDR_B_CS1# 6 DDR_B_ODT1 6 DDR_B_CKE1 36_0201_1% DDR_B_CS1# 36_0201_1% 2 DDR_B_ODT1 36_0201_1% 6 DDR_B_CLK0# 1 2 C1505 1.8P_0402_50V8 128@ 1.CAD Note: Cterm= 1.8pF should be kept near feeding point of first SDRAM 4 SAGE 3G PVT 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DDRIII DIMMB Size Document Number Custom Date: V1JB1 M/B LA-A041P Schematic Wednesday, March 13, 2013 E Sheet 12 of Rev 0.1 52 A B C PCH_RTCX1 1 1 R638 R568 0_0603_5% @ X1 2 PCH_RTCRST# 1 R561 0_0603_5% @ 2 2 D5 BAS40-04_SOT23-3 +RTCVCC 2 SAGE 3G 1 2 C502 1U_0402_6.3V6K 1 32.768KHZ_12.5PF_1TJF125DP1A000D SJ100004Z00 1 1 C756 C757 15P_0402_50V8J 15P_0402_50V8J PCH_SRTCRST# 1 1 +RTCBATT PCH_RTCX2 1 1 2 R338 20K_0402_5% 1 2 R337 20K_0402_5% E SAGE 3G DVT 1 2 2 2 +RTCVCC C516 1U_0402_6.3V6K 2 10M_0402_5% 3 1 D +CHGRTC C197 0.1U_0402_16V4Z 2 20MIL RTC Battery:Chargeable R561, R568 put on TOP +RTCVCC R353 1 2 1M_0402_5% SM_INTRUDER# R347 1 2 330K_0402_5% PCH_INTVRMEN INTVRMEN * ：Integrated VRM enable ：Integrated VRM disable H L (INTVRMEN should always be pull high.) U37A A20 PCH_SPKR PCH_RTCX2 C20 HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature PCH_RTCRST# D20 LOW= Disable (Default internal PD) +VCCSUS3_3 2 @ R322 1K_0402_5% 2 1 PCH_SRTCRST# G22 SM_INTRUDER# K22 PCH_INTVRMEN C17 HDA_BITCLK_PCH N34 HDA_SYNC_PCH L34 RTCX2 RTCRST# FWH4 / LFRAME# SRTCRST# INTRUDER# LDRQ0# LDRQ1# / GPIO23 INTVRMEN SERIRQ 0_0402_5% 2 1 @ 28 HDA_SDO R320 HDA_SDO * HDA_SDOUT_PCH ME debug mode,this signal has a weak internal PD Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide] 33 PCH_SPKR PCH_SPKR T10 HDA_RST_PCH# K34 HDA_BCLK HDA_SYNC SPKR HDA_RST# +VCCSUS3_3 HDA_SDIN0 33 HDA_SDIN0 HDA_SYNC_PCH E34 G34 C34 On Die PLL VR Select is supplied by A34 Prevent back drive issue. 1.5V when smapled high * HDA_SDOUT_PCH 2 G SAGE 3G 3 D S SAGE 3G RP11 4 HDA_BITCLK_PCH 3 HDA_SYNC_PCH_R 2 HDA_RST_PCH# 1 HDA_SDOUT_PCH R302 1 1 3 5 6 7 8 2 @ N32 R672 51_0402_5% 2 1 PCH_JTAG_TCK J3 T57 PAD @ PCH_JTAG_TMS H7 T73 PAD @ PCH_JTAG_TDI K5 T75 PAD @ PCH_JTAG_TDO H1 0_0402_5% R468 1M_0402_5% 2 33_8P4R_5% A36 C36 Q20 BSS138W-7-F_SOT323 1 HDA_SYNC_PCH SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 +5VS 1.8V when sampled low Needs to be pulled High for Huron River platfrom 33 HDA_BITCLK_AUDIO 33 HDA_SYNC_AUDIO 33 HDA_RST_AUDIO# 33 HDA_SDOUT_AUDIO HDA_SDIN0 HDA_SDO HDA_DOCK_EN# / GPIO33 SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA 1 1K_0402_5% IHDA 2 This signal has a weak internal pull-down SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TCK JTAG_TMS JTAG_TDI JTAG R328 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 SATA 6G * RTCX1 SATAICOMPO SATAICOMPI JTAG_TDO SATA3RCOMPO 2 PCH_SPI_CLK_0 R739 2 PCH_SPI_CLK_1 R704 XEMC@ 1.8P_0402_50V8 2 1 C103 PCH_SPI_CLK T3 33_0402_5% PCH_SPI_CS0# Y14 PCH_SPI_CS1# T1 PCH_SPI_CLK_0 XEMC@ 1.8P_0402_50V8 2 1 C104 PCH_SPI_CLK_1 XEMC@ 1.8P_0402_50V8 2 1 C105 HDA_BITCLK_AUDIO SAGE 3G LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 26,28 26,28 26,28 26,28 CRB:10K ohm Check List 1.0:8.2K ohm D36 LPC_FRAME# LPC_FRAME# 26,28 E36 K36 PCH_GPIO23 PCH_GPIO23 18 V5 SERIRQ SERIRQ 26,28 14 PCH_GPIO20 2 R688 AM3 AM1 AP7 AP5 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 25 25 25 25 AM10 AM8 AP11 AP10 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 25 25 25 25 Switchable * Non SG AD7 AD5 AH5 AH4 SAGE 3G 2 PCH_SPI_MOSI_0 R737 2 PCH_SPI_MOSI_1 R734 1 2 PCH_SPI_MISO_0 R736 2 PCH_SPI_MISO_1 R738 1 V4 33_0402_5% 1 PCH_SPI_MOSI U3 33_0402_5% R703 1 +3VS 2 3.3K_0402_5% Y3 Y1 AB3 AB1 3 +1.05VS_PCH SATA_COMP R389 37.4_0402_1% 1 2 R388 49.9_0402_1% 1 2 +1.05VS_PCH SATA3_COMP Y11 Y10 AB12 AB13 SPI_CLK SATA3RBIAS AH1 +3VS 1 RBIAS_SATA3 R650 2 750_0402_1% R674 4.7K_0402_5% SPI_CS0# SPI_CS1# SPI_MOSI SATALED# SATA0GP / GPIO21 SPI_MISO SATA1GP / GPIO19 P3 PCH_SATALED# V14 PCH_GPIO21 P1 PCH_GPIO19 PCH_GPIO19 No use PH 10K +3VS Debug Port DG 1.2 PH 4.7K +3VS GPIO19 has internal Pull up COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 1 33_0402_5% 2MB=16Mb CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 W25Q16CVSSIG_SO8 SA00003FO10 A GPIO21 0 1 PCH_SPI_MISO 33_0402_5% U42 1 2 3 4 2 1 10K_0402_5% Y7 Y5 AD3 AD1 Boot BIOS Strap Boot BIOS * PCH_SPI_CS0# PCH_SPI_MISO_0 SPI_WP0# @ AB8 AB10 AF3 AF1 PCH_SPI_CS1# PCH_SPI_CLK_1 PCH_SPI_MISO_1 PCH_SPI_MOSI_1 28 PCH_SPI_CS1# 28 PCH_SPI_CLK_1 28 PCH_SPI_MISO_1 28 PCH_SPI_MOSI_1 +3VS 5 6 7 8 10K_8P4R_5% Switchable Graph HSPI to EC 4 4 3 2 1 RP28 SERIRQ PCH_SATALED# PCH_GPIO20 PCH_GPIO21 33_0402_5% 1 SPI SAGE 3G Reserve for RF / Close to PCH SATA3COMPI 1 C38 A38 B37 C37 1 2 1K_0402_5% 2 R405 1 LPC PCH_RTCX1 @ RTC +3VS B +3VS SPI_HOLD0# R701 2 PCH_SPI_CLK_0 PCH_SPI_MOSI_0 Issued Date +3VS 2011/06/24 2012/06/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C GPIO51 0 0 1 1 GPIO19 0 1 0 1 4 Compal Electronics, Inc. Compal Secret Data Security Classification 1 3.3K_0402_5% LPC Reserved SPI D Title PCH (1/8) SATA,HDA,SPI, LPC, XDP Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Wednesday, March 13, 2013 Sheet E 13 of 52 A B C D E +VCCSUS3_3 U37B BF36 BE36 AY34 BB34 BG37 BH37 AY36 BB36 BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40 BE38 BC38 AW 38 AY38 Y40 Y39 No use PH 10K +3VALW 2 PCH_GPIO73 A8 Y43 Y45 32 CLK_PCIE_CARD# 32 CLK_PCIE_CARD CARD_CLKREQ# 32 CARD_CLKREQ# L12 V45 V46 PCH_GPIO44 No use PH 10K +3VALW 3 L14 AB42 AB40 No use PH 10K +3VALW PEG_CLKREQ# E6 V40 V42 No use PH 10K +3VALW PCH_GPIO45 T13 V38 V37 PCH_GPIO46 7 CLK_RES_ITP# 7 CLK_RES_ITP R1134 R1135 2 2 @ @ 1 0_0201_5% 1 0_0201_5% CLK_BCLK_ITP# CLK_BCLK_ITP No use PH 10K +3VALW AK14:CLKOUT_ITPXDP_N AK13:CLKOUT_ITPXDP_P K12 AK14 AK13 SML1DATA / GPIO75 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CL_CLK1 CL_DATA1 CL_RST1# PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P CLKOUT_PCIE1N CLKOUT_PCIE1P DRAMRST_CNTRL_PCH C8 PCH_SML0CLK G12 PCH_SML0DATA C13 PCH_GPIO74 E14 PCH_SML1CLK M16 PCH_SML1DATA DRAMRST_CNTRL_PCH 6 S3 reduse No use PH 10K +3VALW S3 reduse PCH_SML1CLK R375 1 2 2.2K_0402_5% PCH_SML1DATA R369 1 2 2.2K_0402_5% DRAMRST_CNTRL_PCH R648 1 2 1K_0402_5% RP23 No use PH 10K +3VALW 4 3 2 1 SMB_ALERT# PCH_GPIO74 PCH_GPIO47 DGPU_PRSNT# PH 2.2K +3VALW CLKOUT_PEG_A_N CLKOUT_PEG_A_P GPIO67 T11 DGPU_PRSNT# DIS,Optimus UMA P10 M10 PCH_GPIO47 AB37 AB38 Pull up at EC side. For DDR,EC 3 PCH_SML1DATA CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI AM12 AM13 CLK_CPU_DPLL# CLK_CPU_DPLL 4 EC_SMB_DA2 PCIECLKRQ1# / GPIO18 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_DMI2_N CLKIN_GND1_P CLKIN_DMI2_P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLKOUT_PEG_B_N CLKOUT_PEG_B_P XTAL25_IN XTAL25_OUT BF18 BE18 CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5 CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI 2 10K_0402_5% 2 10K_0402_5% BJ30 BG30 CLKIN_GND1# CLKIN_GND1 R330 1 R331 1 2 10K_0402_5% 2 10K_0402_5% G24 E24 CLK_BUF_DREF_96M# CLK_BUF_DREF_96M R346 1 R345 1 2 10K_0402_5% 2 10K_0402_5% AK7 AK5 CLK_BUF_PCIE_SATA# R387 1 CLK_BUF_PCIE_SATA R393 1 2 10K_0402_5% 2 10K_0402_5% K45 CLK_BUF_ICH_14M R292 1 2 10K_0402_5% H45 CLK_PCI_LPBACK V47 V49 XTAL25_IN XTAL25_OUT Y47 XCLK_RCOMP K43 CLK_FLEX0 @ F47 CLK_FLEX1 @ H47 CLK_FLEX2 @ K49 DGPU_PRSNT# 1 EC_SMB_CK2 Q22B DMN66D0LDW-7_SOT363-6 Pull down 10K ohm for using internal Clock 2 1 1 2 R293 33_0402_5% C421 22P_0402_50V8J XEMC@ XEMC@ CLK_PCI_LPBACK 17 3 Reserve for EMI please close to PCH R289 90.9_0402_1% 1 2 +1.05VS_PCH CLKOUT_PCIE6N CLKOUT_PCIE6P PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 T52 PAD T53 PAD T21 PAD XTAL25_IN 1 R611 XTAL25_OUT COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ C744 12P_0402_50V8J +3VS 5 6 7 8 10K_8P4R_5% PCH_GPIO73 PCH_GPIO44 PCH_GPIO45 PCH_GPIO46 3 Issued Date 2011/06/24 1 GND 4 1 GND Y1 1 2 2 2 C745 12P_0402_50V8J Compal Electronics, Inc. Compal Secret Data Security Classification 2012/06/02 Deciphered Date Title PCH (2/8) PCIE, SMBUS, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: A 2 1M_0402_5% 25MHZ_10PF_7V25000014 SAGE 3G DVT 4 3 2 1 RP21 EC_SMB_CK2 11,28 SAGE 3G PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP 6 PCH_SML1CLK 120MHz for eDP. R357 1 R358 1 +VCCSUS3_3 CARD_CLKREQ# PCH_GPIO25 PEG_CLKREQ# MINI1_CLKREQ# 2 EC_SMB_DA2 11,28 Q22A DMN66D0LDW-7_SOT363-6 CLK_CPU_DMI# 5 CLK_CPU_DMI 5 3 5 6 7 8 10K_8P4R_5% 0 1 +3VS No use PH 10K +3VALW 1 4 3 2 1 RP22 +3VS 5 6 7 8 M7 SAGE 3G 4 1 10K_8P4R_5% PERN6 PERP6 PETN6 PETP6 PCIECLKRQ0# / GPIO73 A12 5 6 7 8 2.2K_8P4R_5% S PCH_GPIO25 No use PH 10K +3VALW SML1CLK / GPIO58 PCH_SMBDATA D Y37 Y36 SML1ALERT# / PCHHOT# / GPIO74 C9 4 3 2 1 G V10 SML0DATA RP18 PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA PH 2.2K +3VALW S PCH_GPIO20 13 PCH_GPIO20 No use PH 10K +3VS SAGE 3G M1 AA48 AA47 PERN5 PERP5 PETN5 PETP5 SML0CLK PCH_SMBCLK D MINI1_CLKREQ# 24 MINI1_CLKREQ# No use PH 10K +3VS PERN4 PERP4 PETN4 PETP4 SML0ALERT# / GPIO60 H14 No use PH 10K +3VALW G AB49 AB47 24 CLK_PCIE_MINI1# 24 CLK_PCIE_MINI1 Mini Card 1 (On Board WLAN) J2 PERN3 PERP3 PETN3 PETP3 SMB_ALERT# 2 BG36 BJ36 AV34 AU34 SAGE 3G 1 SMBDATA E12 5 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K PERN2 PERP2 PETN2 PETP2 Link C574 1 C575 1 BE34 BF34 BB32 AY32 SMBCLK SMBUS Card Reader PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 SMBALERT# / GPIO11 Controller 32 PCIE_PRX_DTX_N2 32 PCIE_PRX_DTX_P2 32 PCIE_PTX_C_DRX_N2 32 PCIE_PTX_C_DRX_P2 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K SAGE 3G PERN1 PERP1 PETN1 PETP1 FLEX CLOCKS C573 1 C572 1 BG34 BJ34 AV32 AU32 CLOCKS Mini Card 1 On Board WLAN PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 PCI-E* 24 PCIE_PRX_DTX_N1 24 PCIE_PRX_DTX_P1 24 PCIE_PTX_C_DRX_N1 24 PCIE_PTX_C_DRX_P1 B C D Wednesday, March 13, 2013 Sheet E 14 of 52 4 A B C D E U37C 2 1 100K_0402_5% PCH_ACIN +VCCSUS3_3 1 R373 2 4 3 2 RP24 1 1 200_0402_5% PM_DRAM_PWRGD 5 6 7 8 10K_8P4R_5% PCH_GPIO72 PCH_GPIO30 RI# PCH_RSMRST# DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 BC24 BE20 BG18 BG20 4 4 4 4 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 4 4 4 4 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 AW24 AW20 BB18 AV18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AY24 AY20 AY18 AU18 4 4 4 4 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI R341 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI SAGE 3G +3VLP 4 4 4 4 FDI_INT +1.05VS_PCH BJ24 1 R625 1 R632 2 DMI_IRCOMP 49.9_0402_1% 2 DMI2RBIAS 750_0402_1% BG25 BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC1 4mil width and place within 500mil of the PCH SAGE 3G not support Deep S4,S5 mux with SUS_PWR_DN_ACK 28 SUSACK# 1 @ 1 @ 2 0_0402_5% 2 0_0402_5% 2 XDP_DBRESET#_R 0_0402_5% R372 5 XDP_DBRESET# R661 SYS_PWROK SAGE 3G not support AMT APWROK can mux with PWROK (check list1.0 P.40) 2 @ 2 PCH_PWROK_R 0_0402_5% 0_0402_5%1 1 0_0402_5% @ 2 R487 APWROK L10 2 R493 PM_DRAM_PWRGD B13 @ 5 PM_DRAM_PWRGD 28 PCH_RSMRST# 1 28 SUSWARN# 2 @ R412 28 PBTN_OUT# SAGE 3G 1 28 ACPRESENT 0_0402_5% 2 @ L22 PCH_RSMRST# C21 PCH_GPIO30 0_0402_5% K16 PBTN_OUT# E20 PCH_ACIN H20 R456 1 28 PCH_BATLOW# @ R502 Ring Indicator CRB1.0 PH 10K +3VALW SAGE 3G K3 P12 1 PCH_PWROK R382 28,41 SA_PGOOD No use PH 10K +3VALW C12 2 PCH_GPIO72 0_0402_5% E10 RI# A10 System Power Management DSWVRMEN 1 S3@ PCH_GPIO30 R409 SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST# DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 PMSYNCH RI# SLP_LAN# / GPIO29 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 4 4 4 4 4 4 4 4 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 4 4 4 4 4 4 4 4 AW16 FDI_INT AV12 FDI_FSYNC0 BC10 FDI_FSYNC1 AV14 FDI_LSYNC0 BB10 A18 @ PAD FDI_FSYNC0 4 FDI_FSYNC1 4 DSWODVREN FDI_LSYNC0 4 FDI_LSYNC1 * FDI_LSYNC1 4 DSWODVREN 1 S3@ R421 1 @ B9 PCH_PCIE_WAKE# N3 CLKRUN# 2 PCH_RSMRST# 0_0402_5% 2 DPWROK 0_0402_5% SUS_STAT# T19 @ PAD SUSCLK T18 @ PAD H4 PM_SLP_S4# F4 PM_SLP_S3# G10 SLP_A# G16 SLP_SUS# AP14 H_PM_SYNC K14 PCH_GPIO29 1 330K_0402_5% 1 330K_0402_5% @ ： ： DSWODVREN - On Die DSW VR Enable H Enable internal DSW +1.05VS not support Deep S4,S5 DPWROK mux with RSMRST# check list1.0 P.42 CRB=>1k ohm Follow Check List R1.5 No use PH 10K +3VS N14 PM_SLP_S5# 2 PCH_PCIE_WAKE# 24 G8 D10 DPWROK 28 2 R360 L Disable Must always PH at +RTCVCC SAGE 3G R426 R361 1 PCH_GPIO29 1 R395 +VCCSUS3_3 2 10K_0402_5% @ 2 2 10K_0402_5% +3VS CLKRUN# PM_SLP_S5# 28 PM_SLP_S4# 28 Can be left NC when IAMT is not support on the platfrom PM_SLP_S3# 28 T51 @ PCH_PCIE_WAKE# R656 PAD SLP_SUS# 28 DPWROK R653 1 2 8.2K_0402_5% R667 1 2 100K_0402_5% CR CHKLST Rev2.0 not support Deep S4,S5 can NC PCH EDS1.2 P.74 H_PM_SYNC 5 No use PH 10K +3VALW 是是是是NC PM_DRAM_PWRGD T16 0.1U_0201_10V6K 2 3 +RTCVCC FDI_INT 4 E22 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 1 1 C753 XDP_DBRESET# XEMC@ 3 For EMI 5 Y 4 SYS_PWROK SYS_PWROK 5 1 MC74VHC1G08DFT2G_SC70-5 R681 10K_0402_5% 2 2 R680 10K_0402_5% 3 1 42 VGATE ALL power OK P 28 PCH_PWROK +3VS U39 2 B 1 A G tell PCH all power ok but cpu core C603 1 .047U_0402_16V7K @ 2 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PCH (3/8) DMI,FDI,PM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Sheet Wednesday, March 13, 2013 E 15 of 52 Rev 0.1 A B C D E UMA Panel Backlight ON/OFF ENBKL R612 2 @ 1 0_0402_5% IGPU_BKLT_EN U37D J47 M45 P45 44 INVTPWM 1 T40 K47 Delete LVDS function T45 P39 AF37 AF36 AE48 AE47 AK39 AK40 AN48 AM47 AK47 AJ48 AN47 AM49 AK49 AJ47 AF40 AF39 2 LVDS disable: DATA/Clock/Control can NC VCC_TX_LVDS,VCCA_LVDS connected to GND AH45 AH47 AF49 AF45 AH43 AH49 AF47 AF43 N48 P49 T49 CRT disable: DATA/Clock/Control can NC DAC_IREF still need PD VCCADAC connected to +3VS T39 M40 M47 M49 CRT_IREF L_BKLTCTL AM42 AM40 SDVO_STALLN SDVO_STALLP L_DDC_CLK L_DDC_DATA AP39 AP40 SDVO_INTN SDVO_INTP L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG SDVO_CTRLCLK SDVO_CTRLDATA LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 DDPB_AUXN DDPB_AUXP DDPB_HPD CRT_BLUE CRT_GREEN CRT_RED DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DAC_IREF CRT_IRTN SDVO_SCLK SDVO_SDATA AT49 AT47 AT40 PCH_DPB_HPD AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 SDVO_SCLK 23 SDVO_SDATA 23 PCH_DPB_HPD 23 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 23 23 23 23 23 23 23 23 HDMI D2 HDMI D1 HDMI D0 HDMI CLK AP47 AP49 AT38 DDPC_AUXN DDPC_AUXP DDPC_HPD 2 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P M43 M36 AT45 AT43 BH41 DDPD_AUXN DDPD_AUXP DDPD_HPD BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P CRT_HSYNC CRT_VSYNC P38 M39 P46 P42 DDPD_CTRLCLK DDPD_CTRLDATA CRT_DDC_CLK CRT_DDC_DATA 1 SDVO_CTRLDATA strap pull high at level shift page 3 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ R307 1K_0402_5% 2 For CRT diable =>Change 1K 0.5% to 5% T43 T42 AP43 AP45 SDVO_TVCLKINN SDVO_TVCLKINP 1 3 L_BKLTEN L_VDD_EN Digital Display Interface IGPU_BKLT_EN 22 PCH_ENVDD LVDS PD 100K at EC side CRT 28 ENBKL 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 Title PCH (4/9) LVDS,CRT,DP,HDMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 16 of 52 Rev 0.1 A B C SAGE 3G RP9 4 3 2 1 5 6 7 8 PCH_GPIO55 PCH_GPIO53 PCH_GPIO52 PCH_GPIO5 10K_8P4R_5% RP12 4 3 2 1 PCH_GPIO51 PCH_GPIO2 ODD_DA# PCH_GPIO4 10K_8P4R_5% R267 1 B21 M20 AY16 BG46 2 10K_0402_5% DGPU_PWR_EN 接接+3VS還還GND +3VS NV_RB# PCH_USB3_RX2_N PCH_USB3_RX2_P 27 PCH_USB3_RX2_P USB3.0 PCH_USB3_TX2_N 27 PCH_USB3_TX2_N 2 Boot BIOS Strap Internal PH Only GPIO function GPIO19 GPIO51 Boot BIOS Bit10 Destination 27 PCH_USB3_TX2_P Bit11 0 1 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 BE28:USB3Rn1 BC30:USB3Rn2 BE32:USB3Rn3 BJ32:USB3Rn4 BC28:USB3Rp1 BE30:USB3Rp2 BF32:USB3Rp3 BG32:USB3Rp4 AV26:USB3Tn1 BB26:USB3Tn2 AU28:USB3Tn3 AY30:USB3Tn4 AU26:USB3Tp1 AY26:USB3Tp2 AV28:USB3Tp3 AW30:USB3Tp4 NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P Reserved 1 0 PCI 1 1 SPI 0 0 LPC * PCI Interrupt Requests SAGE 3G Reserve for RF / Close to PCH 3 PCH_USB3_TX2_P 只只GPIO的的的的的strap function 不如GPIO要PH +3VS,如如GPIO PH +3VS 只只GPIO的的的的的strap function 無無PH(Internal PH),如如GPIO PH +3VS XEMC@ XEMC@ XEMC@ NV_RCOMP 2 8.2K_0402_5% DGPU_HOLD_RST# 27 PCH_USB3_RX2_N GNT1#/ GPIO51 NV_ALE NV_CLE 1.8P_0402_50V8 2 1.8P_0402_50V8 2 1.8P_0402_50V8 2 1 C106 1 C107 1 C108 SAGE 3G CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_TXM PAD CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_TXM K40 K38 H38 G38 DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN C46 C44 E40 PCH_GPIO51 PCH_GPIO53 PCH_GPIO55 D47 E42 F46 PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 G42 G40 C42 D44 K10 T13 @ 26,28,31,32,5 PLT_RST# 14 CLK_PCI_LPBACK 28 CLK_PCI_LPC 26 CLK_PCI_TXM PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 5 6 7 8 PLT_RST# 4 RP43 3 22_8P4R_5% CLK_PCI0 2 CLK_PCI1 1 CLK_PCI2 CLK_PCI3 CLK_PCI4 T7 @ T8 @ PAD PAD SAGE 3G R10 1 H49 H43 J48 K42 H40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS# USBRBIAS AT10 BC8 DMI,FDI Termination Voltage AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 Set to Vcc when HIGH DF_TVS 1 Set to Vss when LOW DG1.2 CRB1.0 PH 2.2K series 1K For 2012 support +1.8VS R651 2.2K_0402_5% Ball AY1 : DF_TVS AV5 AY1 2 R654 DF_TVS 1 1K_0402_5% H_SNB_IVB# 5 AV10 CLOSE TO THE BRANCHING POINT AT8 AY5 BA2 AT12 BF3 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB20_N0 USB20_P0 USB20_N1_R USB20_P1_R USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 C33 USBRBIAS R713 1 R710 1 2 0_0402_5% 2 0_0402_5% @ @ USB20_N2 USB20_P2 USB20_N3 USB20_P3 31 31 22 22 @ T15 @ T17 PAD PAD USB20_N0 USB20_P0 USB20_N1 USB20_P1 30 30 27 27 Sensor Hub 2 USB Connector 3G Touch Screen EHCI 1 Some PCH config not support USB port 6 & 7. USB20_N8 USB20_P8 2 USB20_N9 R714 1 @ 2 USB20_P9 R715 1 @ USB20_N10 USB20_N10 USB20_P10 USB20_P10 USB20_N11 USB20_N11 USB20_P11 USB20_P11 1 R620 0_0402_5% USB20_N1 0_0402_5% USB20_P1 27 27 33 33 USB20_N8 24 USB20_P8 24 Bluetooth Debug Port CMOS Camera EHCI 2 CMOS Camera 2 22.6_0402_1% SAGE 3G Within 500 mils B33 +VCCSUS3_3 PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 3 RP14 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# USB_OC0# USB_OC2# USB_OC7# USB_OC5# USB_OC0# 27 4 3 2 1 5 6 7 8 10K_8P4R_5% +VCCSUS3_3 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ SAGE 3G PLT_RST# C1214 C6 PIRQA# PIRQB# PIRQC# PIRQD# USB R310 1 TP21 TP22 TP23 TP24 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 PCI +3VS 5 6 7 8 NV_DQS0 NV_DQS1 1 10K_8P4R_5% AY7 AV7 AU3 BG4 2 PCI_PIRQC# PCI_PIRQB# PCI_PIRQA# PCI_PIRQD# NVRAM 5 6 7 8 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RP8 1 E U37E +3VS 4 3 2 1 D RP15 USB_OC1# USB_OC4# USB_OC3# USB_OC6# 2 1U_0402_6.3V6K 4 3 2 1 5 6 7 8 10K_8P4R_5% Y 4 PLT_RST_BUF# 24 R376 100K_0402_5% 3 SAGE 3G 1 28 IRST_RST# U26 2 B 1 A G PLT_RST# P 5 +3VS 2 MC74VHC1G08DFT2G_SC70-5 4 4 Sideband signal for Touch screen 2 22 TS_INT# R463 1 @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification PCH_GPIO4 0_0402_5% 2011/06/24 2012/06/02 Deciphered Date Title PCH (5/9) PCI, USB, NVRAM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 17 of 52 Rev 0.1 A B C D E HDA_SYNC PH(PLL =+1.5VS) +3VS +3VS 30 HUB_PWRGATE +VCCSUS3_3 1 25 RAID0_DET 1 2 1 @ 0_0402_5% 2 PCH_GPIO68 R256 2 PCH_GPIO35 R249 1 1 @ 0_0402_5% 1 @ 0_0402_5% @R616 @ R616 10K_0402_5% R617 10K_0402_5% TPM@ PCH_GPIO69 SAGE 3G PCH_GPIO1 R258 R619 10K_0402_5% R621 10K_0402_5% WOTPM@ 1 PCH_GPIO0 T7 No use PH 10K +3VS PCH_GPIO1 A42 No use PH 10K +3VS DGPU_HPD_INT# H36 EC_SCI# E38 EC_SMI# C10 28 EC_SCI# 28 EC_SMI# Deep S4,S5 wake event signal RTC alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) R506 1 DS3@ No use PH +3VALW SAGE 3G EC LID SW OUT No use PH +3VALW 28 EC_LID_OUT# No use PH +3VS PCH_GPIO12 C4 EC_LID_OUT# G2 MSATA_DET# 25 MSATA_DET# @ 2 10K_0402_5% PCH_GPIO27 No use PH 10K +3VS PCH_GPIO22 T5 CRB1.0 PH 10K +3VALW PCH_GPIO24 E8 PCH_GPIO27 0_0402_5% PCH_GPIO28 E16 No use PD 10K to GND 28 2 EC_DS3_WAKE# 1 @ R595 No use PH 10K +3VALW 1 R364 2 10K_0402_5% WWAN_OFF# SATA2GP/GPIO36,SATA3GP/GPIO37 1.Used as for Mechanical Presence detect Use a weak external pull-up (150K-200k Ohms) to Vcc3_3 or use 10K external pull-up that is enabled only after PLTRST# de-assertion. 2.Used as GP Input (Pin HW default) Ensure GPI is not driven high during strap sampling window D40 2 P8 No use PH 10K +3VS PCH_GPIO34 K1 No use can NC(+3VS power plane) PCH_GPIO35 K4 Can't PH ODD_DETECT# V8 Can't PH WWAN_OFF# M5 No use PH 10K +3VS Optimus(L)/ non optimus(H) OPTIMUS_EN# N2 No use PH 10K +3VS PCH_GPIO39 M3 No use PH 10K +3VS PCH_GPIO48 V13 SATA5GP&TEMP_ALERT# CRB PH 10K +3VS PCH_GPIO49 V3 No use PH +3VALW PCH_GPIO57 D6 TACH4 / GPIO68 TACH1 / GPIO1 TACH5 / GPIO69 TACH2 / GPIO6 TACH6 / GPIO70 TACH3 / GPIO7 TACH7 / GPIO71 A44 UMA@ +3VS R429 1 R430 1 2 10K_0402_5% OPTIMUS_EN# A45 RP16 4 3 2 1 3 5 6 7 8 PCH_GPIO0 PCH_GPIO1 DGPU_HPD_INT# MSATA_DET# A46 @ 2 10K_0402_5% A5 A6 10K_8P4R_5% B3 GPIO38 RP17 4 3 2 1 5 6 7 8 DGPU_PWROK PCH_GPIO34 PCH_GPIO48 PCH_GPIO49 OPTIMUS_EN# * 10K_8P4R_5% Muxless nonMuxless B47 BD1 0 1 BD49 BE1 SAGE 3G Define Q5LJ1(DDR3) or V1JV1(DDR3L) +VCCSUS3_3 R458 BE49 BF1 1 2 10K_0402_5% PCH_GPIO24 BF49 DDR3@ R457 +VCCSUS3_3 +3VS R391 1 2 1K_0402_5% 2 10K_0402_5% DDR3L@ C41 PCH_GPIO70 A40 PCH_GPIO71 +3VS @ T45 PAD GPIO15 A20GATE SATA4GP / GPIO16 TACH0 / GPIO17 SCLOCK / GPIO22 GPIO24 / MEM_LED PECI RCIN# PROCPWRGD THRMTRIP# INIT3_3V# P4 PCH_PECI_R P5 EC_KBRST# @ T46 PAD AY11 AY10 PCH_THRMTRIP#_R 1 R385 STP_PCI# / GPIO34 NC_2 GPIO35 NC_3 SATA2GP / GPIO36 NC_4 SATA3GP / GPIO37 NC_5 CTRL+ALT+DEL 5 6 7 8 PCH_GPIO12 PCH_GPIO57 EC_KBRST# ODD_DETECT# Check list1.0 P.59 +3VS This signal has weak internal PU, can't pull low,leave NC AH8 R324 1 PCH_GPIO68 * DDR3L(V1JV1) DDR3 AH10 TS_VSS1~4 PD to GND AK10 P37 SLOAD / GPIO38 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 VSS_NCTF_15 SATA5GP / GPIO49 VSS_NCTF_16 GPIO57 VSS_NCTF_17 VSS_NCTF_1 VSS_NCTF_19 VSS_NCTF_2 VSS_NCTF_20 VSS_NCTF_3 VSS_NCTF_21 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_6 VSS_NCTF_24 VSS_NCTF_7 VSS_NCTF_25 VSS_NCTF_8 VSS_NCTF_26 VSS_NCTF_9 VSS_NCTF_27 VSS_NCTF_10 VSS_NCTF_28 VSS_NCTF_11 VSS_NCTF_29 VSS_NCTF_12 VSS_NCTF_30 VSS_NCTF_13 VSS_NCTF_31 VSS_NCTF_14 VSS_NCTF_32 BG2 SA000059110 / ELPIDA DDR3L-1333 SA00005FV10 / HYNIX DDR3L-1333 SA00005HT80 / ELPIDA DDR3L-1600 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 DDR3L-1333 DDR3L-1333 DDR3L-1333 DDR3L-1333 DDR3L-1600 DDR3L-1600 DDR3L-1600 DDR3L-1600 GPIO39 GPIO23 GPIO22 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Elpida Mono 512MB*4(Ch A) Hynix Mono 512MB*4(Ch A) Elpida Mono 512MB*8(Ch A,B) Hynix Mono 512MB*8(Ch A,B) Elpida Mono 512MB*4(Ch A) Elpida Mono 512MB*8(Ch A,B) E1 E49 +3VS F1 R274 1 X76@ 2 10K_0402_5% R275 1 X76@ 2 10K_0402_5% R278 1 X76@ 2 10K_0402_5% R279 1 X76@ 2 10K_0402_5% R281 1 X76@ 2 10K_0402_5% R282 1 X76@ 2 10K_0402_5% PCH_GPIO22 F49 0 1 PCH_GPIO23 PCH_GPIO23 13 Issued Date 2011/06/24 B PCH_GPIO39 4 Compal Electronics, Inc. Compal Secret Data Security Classification 3 D49 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ GPIO36/GPIO37 is Strap functionality that requires internal pull down to be sampled at rising PWROK. When uses as SATA2GP/SATA3GP for mechanical presence detect -use a external pull up 150K-200K ohm to Vcc3_3 When used as GP input -ensure GPI is not driven high during strap sampling window When Unused as GPIO or SATA*GP -use 8.2K-10K pull-down check list page 47 2 2 10K_0402_5% AK11 2012/06/02 Deciphered Date Title PCH (6/9) GPIO, CPU, MISC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A 130c shut sown H_THRMTRIP# 5 T14 10K_8P4R_5% GPIO24 Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. CRB1.0 PH10K to +3VALW non CPU power ok 2 H_THRMTRIP# 390_0402_5% INIT3_3V NC_1 PECI CPU-EC EC_KBRST# 28 H_CPUPWRGD 5 GPIO27 GPIO28 SAGE 3G GPIO24 EC_LID_OUT# RP29 GPIO69 GPIO70 0 0 0 1 1 0 1 1 GATEA20 28 AU16 PCH_GPIO24 4 3 2 1 4 1 PCH_GPIO69 R419 10K_0402_5% NCTF A4 +3VS PCH_GPIO68 B41 LAN_PHY_PWR_CTRL / GPIO12 VSS_NCTF_18 3.Unused as GPIO or SATA*GP Use 8.2K-10K pull-down to ground. C40 GPIO8 2 100K_0402_5% DGPU_PWROK R362 1 U2 BMBUSY# / GPIO0 2 1 No use PH 10K +3VS TPM Status HW, SW without support TPM Infineon TPM SLB9655 x x 1 R417 1K_0402_5% CPU/MISC 2 U37F Debug Port DG 1.2 PH 4.7K +3VALW_PCH +3VLP 1 SW base on TPM table to detect HW TPM status PCH_GPIO28 GPIO 2 R422 4.7K_0402_5% @ PCH_GPIO70 2 30 HUB_DFU_EN# 2 H On-Die PLL voltage regulator enable L On-Die PLL Voltage Regulator disable 1 * 2 ：： This signal has a weak internal pull up 2 On-Die PLL Voltage Regulator 1 GPIO28 C D Wednesday, March 13, 2013 Sheet E 18 of 52 Rev 0.1 A B C D E Thermal Senser share with VCCADAC power rail so can't remove this power CRT 1mA ：On-Die PLL voltage regulator enable AN16 H AN17 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA AN21 AN26 AN27 SAGE 3G +1.05VS_PCH AP21 2 AP23 2 1 2 C492 1U_0402_6.3V6K 2 1 @ C474 1U_0402_6.3V6K 2 1 C486 1U_0402_6.3V6K 1 C496 1U_0402_6.3V6K 2 C543 10U_0603_6.3V6M 1 AP24 AP26 @ AT24 AN33 Place Near AN16,AN21,AN33 AN34 +3VS SAGE 3G 1 Place Near BH29 2 BH29 AP16 @ PAD T14 +1.05VS_VCCAPLL_FDI BG6 C420 0.1U_0402_16V7K 2 1 C418 10U_0603_6.3V6M 2 AK36 +VCCA_LVDS SAGE 3G AK37 VCCTX_LVDS[4] AM37 0_0402_5% R270 AM38 AP36 1 @ +3VS VCCAPLLEXP VCCIO[15] VCCIO[16] PPT:3711mA CPT:3709mA VCC3_3[6] 0_0402_5% R280 V33 228mA 1 VCC3_3[7] SAGE 3G +VCCTX_LVDS AP37 VCCIO[28] V34 Place Near V33 C449 0.1U_0402_16V7K I/O Buffer Voltage 2 VCCIO[17] PPT:167mA CPT:175mA VCCIO[18] VCCIO[19] PPT:47mA CPT:42mA VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] AT16 +VCCAFDI_VRM VCCDMI[1] AT20 Trace 20mil AB36 1 VCCVRM[2] VCCFDIPLL VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] C480 1U_0402_6.3V6K place near AT20 DMI buffer logic Core Well I/O Buffer place near AB36 AG16 +1.8VS VccDFTERM should PH +1.8VS or +3VS AG17 1 AJ16 2 VCCPNAND[4] C477 1U_0402_6.3V6K 2 2 VCC3_3[3] 1 +1.05VS_PCH 2mA Internal PLL and VRM(+1.5VS) +1.05VS_PCH VCCIO[25] VCCIO[26] PCH Power Rail Table SAGE 3G VCCVRM[3] VCCIO[1] C749 0.1U_0402_16V7K +VCCAFDI_VRM VCCTX_LVDS[2] 40mA VCCTX_LVDS[3] DMI On-Die PLL Voltage Regulator BJ22 C419 0.01U_0402_16V7K 2 @ VCCTX_LVDS[1] NAND / SPI +VCCAPLLEXP T33 @ VCCALVDS VSSALVDS VCCIO PAD U47 1 1 +1.05VS_PCH AN19 VSSADAC 1 SAGE 3G R10 L23 HCB1608KF-221T2_2P 2 1 Place Near U48 +VCCADAC 2 Place Near AA23 VCCADAC U48 1 2 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] +3VS PPT:63mA CPT:1mA 2 2 2 1 C505 1U_0402_6.3V6K 2 1 C517 1U_0402_6.3V6K @ 1 C519 1U_0402_6.3V6K 1 C754 10U_0603_6.3V6M PAD-OPEN 4x4m AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 LVDS +1.05VS_PCH PPT:1700mA CPT:1300mA HVCMOS 1 1 2 POWER U37G J3 @ VCC CORE SAGE 3G +1.05VS_VCCPP AJ17 Voltage Rail Voltage S0 Iccmax Current(A) V_PROC_IO 1.05 0.001 Processor I/F V5REF 5 0.001 PCH Core Well Reference Voltage V5REF_Sus 5 0.001 Suspend Well Reference Voltag Vcc3_3 3.3 0.266 I/O Buffer Voltage VccADAC 3.3 0.001 Display DAC Analog Power. This power is supplied by the core well. 2 VccADPLLA 1.05 0.08 Display PLL A power C523 0.1U_0201_10V6K VccADPLLB 1.05 0.08 Display PLL B power place near AG16 VccCore 1.05 1.3 Internal Logic Voltage VCCPNAND change to VccDFTERM VccDMI 1.05 0.042 DMI Buffer Voltage VccIO 1.05 2.925 Core Well I/O buffers VccASW 1.05 1.01 1.05 V Supply for Intel R Management Engine and Integrated LAN VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well H VccpNAND 1.8 0.19 1.8V power supply for DF_TVS VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA VccRTC 3.3 6 uA Battery Voltage VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage +1.05VS_PCH +3VS 1 3 SAGE 3G On-Die PLL Voltage Regulator 2 AU20 C491 1U_0402_6.3V6K Near AU20 Trace 20mil VCCIO[27] FDI AP17 VCCDMI[2] 10mA VCCSPI V1 For SPI control logi 1 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 2 C770 1U_0402_6.3V6K 3 ：On-Die PLL voltage regulator enable +VCCAFDI_VRM +1.5VS R394 1 @ 2 0_0402_5% +VCCAFDI_VRM VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP VCCVRM = 160mA detal waiting for newest spec 配HDA_SYNC PH(PLL =+1.5VS) 4 3.3 / 1.5 0.01 VccVRM 1.8 / 1.5 0.16 High Definition Audio Controller Suspend Voltage 1.8 V Internal PLL and VRMs (1.8 V for Desktop) VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage VccSSC 1.05 0.095 Spread Modulators Power Supply VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.06 Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only) 2011/06/24 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date VccSusHDA 2012/06/02 Deciphered Date Title PCH (7/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Tuesday, March 26, 2013 Sheet E 19 of 52 Rev 0.1 A B C D E For Deep S3 turn off +V5REF_SUS,+VCCSUS3_3 +1.05VS_PCH PAD On-Die PLL Voltage Regulator ：On-Die PLL voltage regulator enable BH23 +VCCAPLL_CPY_PCH T32 @ H AL29 +1.05VS_PCH PAD suppied by internal 1.05V VR must NC T9 AL24 +VCCSUS1 @ AA24 C552 22U_0805_6.3V6M 1 C547 22U_0805_6.3V6M 1 2 0_0402_5% 2 2 AA26 AA27 AA29 AA31 AC26 2 C513 1U_0402_6.3V6K 2 AC27 AC29 AC31 AD29 AD31 Near AA19 W21 2 W23 Near BD47 W26 Near N16 Near BF47 2 C521 N16 +VCCRTCEXT Y49 +1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL 2 1 C467 1U_0402_6.3V6K Place near AF17 +1.05VS_PCH suppied by internal 1.05V VR Must NC 2 C526 Near V16 PAD 1 +VCCSST 0.1U_0201_10V6K V16 +1.05VM_VCCSUS T17 V19 T10 @ +1.05VS_PCH BJ8 2 2 1 2 C495 0.1U_0402_16V7K 1 C494 0.1U_0402_16V7K 1 Near A22 SAGE 3G VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS +VCCSUS3_3 VCCSUS3_3[1] 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCC3_3[4] +1.05VS_PCH T26 M26 +PCH_V5REF_SUS AN23 +VCCA_USBSUS 1 AN24 P34 T11 PAD 2 suppied by internal 1.05V VR Must NC DCPRTC VCCVRM[4] VCCIO[13] VCCIO[6] VCCAPLLSATA VCCVRM[1] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11] 55mA VCCIO[2] VCCIO[3] VCCIO[10] 95mA VCCIO[4] D14 +PCH_V5REF_RUN +VCCSUS3_3 1 N22 P20 C470 1U_0402_10V6K C501 0.1U_0201_10V6K 2 SAGE 3G Near N20 P22 1 T34 C771 @ 0.1U_0402_16V7K 2 Place near AJ2 1 AH13 2 AH14 1 (RF requirement) 1 C522 0.1U_0402_16V7K 2 Place near AA16,W16 C471 @ 0.1U_0402_16V7K 2 Place +VCCSUS3_3 +1.05VS_PCH near T34 XEMC@ 1 XEMC@ 1 2 2 2 2 2 C533 1U_0402_6.3V6K GPIO28 +VCCSATAPLL @ T48 PAD SAGE 3G 3 On-Die PLL Voltage Regulator ：On-Die PLL voltage regulator enable H AF11 AC16 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA +VCCAFDI_VRM +1.05VS_PCH AC17 Near AC16 AD17 1 C482 1U_0402_6.3V6K +1.05VS_PCH 2 DCPSUS[1] DCPSUS[2] 1mA +PCH_V5REF_SUS XEMC@ XEMC@ XEMC@ 1 1 1 Near AH13,AH14,AF13 AF14 AK1 2 Near P34 +1.05VS_PCH AF13 2 +3VS SAGE 3G AA16 W16 R321 100_0402_5% 1 N20 DCPSST V_PROC_IO +5VS RB751V-40_SOD323-2 VCCASW[18] VCC3_3[2] +3VS 0.1U_0402_16V4Z @ +VCCSUS3_3 VCCASW[17] VCCASW[20] 1 R334 100_0402_5% RB751V-40_SOD323-2 Near M26 AJ2 VCCASW[19] 2 +V5REF_SUS C484 DCPSUS[4] VCCASW[16] VCCADPLLB 2 1 2 2 Near P24 2 P24 VCCASW[22] VCCASW[23] VCCASW[21] T21 V21 T19 +VCCSUS3_3 A22 2 Place near BJ8 C497 0.1U_0402_16V7K +RTCVCC C493 1U_0402_6.3V6K 4 2 1 C541 0.1U_0201_10V6K 2 1 C537 0.1U_0402_16V7K 1 C544 4.7U_0603_6.3V6K isolation between SSC (AG33) and DIFFCLKN(AF33,AF34,AG34) 18mil width(DIFFCLKN) 10mil (SSC) VCCASW[8] BF47 VCCIO[8,9,11] change to VccDIFFCLKN VCCIO[10] change to VccSSC Place near AG33 VCCASW[7] CPT:75mA 1 C476 1U_0402_6.3V6K 2 VCCASW[6] VCCADPLLA PPT:80mA AG33 2 Place near AF33, AF34,AG34 VCCASW[5] BD47 AF17 AF33 AF34 AG34 SAGE 3G 1 C524 1U_0402_6.3V6K VCCASW[4] VCCIO[12] +VCCAFDI_VRM +1.05VS_PCH +1.05VS_PCH 1mA VCCASW[3] VCCIO[5] 1 0.1U_0201_10V6K Near T23 2 V24 1 C490 0.1U_0402_16V7K C514 18P_0201_50V8J W33 1 V23 C512 18P_0201_50V8J 2 C429 1U_0402_6.3V6K 3 C752 22U_0805_6.3V6M 2 1 W31 SAGE 3G T24 D16 VCCIO[34] 2 VCCRTC 10mA VCCSUSHDA P32 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ Need +3VALW and 0.1U close PCH 1 C473 0.1U_0201_10V6K 4 2 Near P32 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2011/06/24 2012/06/02 Deciphered Date Title PCH (8/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B 1 T23 C525 18P_0201_50V8J SAGE 3G 2 2 1 +VCCSUS3_3 SAGE 3G C515 18P_0201_50V8J W29 +1.05VS_VCCA_B_DPL 1 W24 Near N26 T29 C511 18P_0201_50V8J C426 1U_0402_6.3V6K 1 2 L49 10UH_LB2012T100MR_20% C751 22U_0805_6.3V6M 2 1 VCCASW[2] 903mA SATA +1.05VS_VCCA_A_DPL 1 VCCSUS3_3[9] VCCSUS3_3[10] MISC L54 10UH_LB2012T100MR_20% 1 2 @ 1 C478 1U_0402_6.3V6K 2 SAGE 3G 1 C518 1U_0402_6.3V6K 1 VCCASW[1] HDA 2 +1.05VS_PCH DCPSUS[3] PCI/GPIO/LPC AA21 +VCCDSW3_3 @ VCCIO[14] Clock and Miscellaneous AA19 R276 1 Deep S3 VCCSUS3_3[7] PPT:126mA CPT:119mA VCCSUS3_3[8] VCCAPLLDMI2 VCCSUS3_3[6] +1.05VS_PCH +3VLP VCCIO[33] CPU VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA VCCIO[32] VCC3_3[5] 1 GPIO28 DCPSUSBYP T27 2 1 1 2 T38 34 PCH_PWR_EN# C468 1U_0402_6.3V6K 2 DS3@ 2 PCH_PWR_EN# 1 R757 1K_0402_5% DS3@ C820 0.01U_0402_16V7K DS3@ 2 +3VS_VCC_CLKF33 P28 1 Q64 AP2301GN-HF_SOT23-3 1 V12 VCCIO[31] 1 1 +PCH_VCCDSW VCCIO[30] 1mA 1 R756 2 2.2K_0402_5% DS3@ C819 0.01U_0402_16V7K DS3@ 2 T12 @ VCCDSW3_3 1 P26 1 T16 Near T16 USB PAD suppied by internal 1.05V VR must NC VCCIO[29] DS3@ R752 20K_0402_5% Near T38 VCCACLK Q68 AP2301GN-HF_SOT23-3 N26 10mil 2 0_0402_5% 3 +1.05VS_PCH 2 SAGE 3G 1 S3@ R751 C816 0.1U_0402_16V7K 2 AD49 +V5REF_SUS +5VALW 20mil 2 2 JUMP_43X39 3 1 POWER U37J C520 0.1U_0402_16V7K 1 R755 20K_0402_5% 2 1 1 Not support Deep S4,S5 connect to +3VALW J13 @ 1 C817 0.1U_0201_10V6K +3VS_VCC_CLKF33 1 C440 1U_0402_6.3V6K 1 C465 10U_0603_6.3V6M 2 +VCCACLK 0_0402_5% RTC L26 10UH_LB2012T100MR_20% 1 2 +VCCSUS3_3 +3VALW @ R273 1 +VCCDSW3_3 2 +1.05V analog internal clock PLL Can NC +3VS C D Wednesday, March 13, 2013 Sheet E 20 of 52 Rev 0.1 A B C D E U37I 1 U37H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 2 3 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 1 2 3 4 4 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PCH (9/9) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 21 of 52 Rev 0.1 5 4 3 2 1 Panel POWER CIRCUIT SM010014520 3000ma 220ohm@100mhz DCR 0.04 +LCDVDD W=60mils SAGE 3G C562 4.7U_0603_6.3V6K +3VS D +LCDVDD U2007 5 4 OUT 1 2 2 C10 0.1U_0402_16V4Z D C7 68P_0402_50V8J IN GND 2 R186 0_0402_5% 1 2 @ IN 1 2 1 W=60mils 1 EN G5243T11U_SOT23-5 C489 1U_0402_6.3V6K W=40mils +LG_VOUT +INVPWR_B+ L1 FBMA-L11-201209-221LMA30T_0805 2 1 3 1 SA000028Y00 2 C542 0.1U_0402_16V4Z @ 1 1 2 2 C11 680P_0402_50V7K PCH_ENVDD 16 SAGE 3G PVT eDP PANEL Conn. +INVPWR_B+ W=40mils JEDP1 44 44 44 44 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FB4 FB3 FB2 FB1 EDP_HPD SAGE 3G 60mils SAGE 3G 4 EDP_AUXN 4 EDP_AUXP 4 EDP_TXP0 4 EDP_TXN0 4 EDP_TXP1 4 EDP_TXN1 +LCDVDD 0.1U_0402_16V7K 1 0.1U_0402_16V7K 1 2eDP@ 2eDP@ C915 C914 EDP_AUXN_C EDP_AUXP_C 0.1U_0402_16V7K 1 0.1U_0402_16V7K 1 2eDP@ 2eDP@ C910 C911 EDP_TXP0_C EDP_TXN0_C 0.1U_0402_16V7K 1 0.1U_0402_16V7K 1 2eDP@ 2eDP@ C912 C913 EDP_TXP1_C EDP_TXN1_C +3VS Touch Screen R465 2 +5V_TS 1 0_0402_5% @ 17 USB20_N3 17 USB20_P3 17 TS_INT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C G1 G2 G3 G4 31 32 33 34 I-PEX_20455-030E-12 CONN@ B B JEDP1 +5V_TS +5VS I-PEX_20455-030E-12_30P-T J18 @ 1 1 2 2 10mil JUMP_43X39 4 EDP_HPD# SAGE 3G 1 D15 D EDP_HPD USB20_N3 3 USB20_P3 2 1 1 2 G S 3 eDP@ R480 100K_0402_5% TVNST52302AB0_SOT523-3 XEMC@ SCA00001W00 2 eDP@ Q29 DMN65D8LW-7_SOT323-3 SB00000UO00 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 Title LVDS Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Wednesday, March 13, 2013 Sheet 1 22 of 52 5 4 W=40mils +HDMI_5V_OUT D10 1 1 +HDMI_5V RB491D-YS_SOT23-3 1 SM070001310 400ma 90ohm@100mhz DCR 0.3 HDMI_R_CK- D3 1 1 10 9 HDMI_R_CK- HDMI_SCLK D7 1 1 10 9 HDMI_SCLK HDMI_R_CK+ 2 2 9 8 HDMI_R_CK+ HDMI_SDATA 2 2 9 8 HDMI_SDATA R575 1 HDMI_CLK- F1 2 +5VS 2 2 1 1 1.1A_6VDC_FUSE C345 0.1U_0402_16V4Z HDMI_R_D0- 4 4 7 7 HDMI_R_D0- HDMI_R_D0+ 5 5 6 6 HDMI_R_D0+ 2 D HDMI_HPD 4 4 7 7 5 5 6 6 3 3 3 3 8 8 XEMC@ HDMI_HPD HDMI_TX2HDMI_TX2+ 16 PCH_DPB_N1 16 PCH_DPB_P1 C283 C282 2 2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K HDMI_TX1HDMI_TX1+ 16 PCH_DPB_N2 16 PCH_DPB_P2 C287 C286 2 2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K HDMI_TX0HDMI_TX0+ 16 PCH_DPB_N3 16 PCH_DPB_P3 C285 C284 2 2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K HDMI_CLKHDMI_CLK+ TVWDF1004AD0_DFN 2 0_0402_5% HDMI_R_CK+ HDMI_TX0- R565 1 @ 2 0_0402_5% HDMI_R_D0- 1 HDMI_R_D2+ D13 1 1 10 9 HDMI_R_D2+ HDMI_R_D2- 2 2 9 8 HDMI_R_D2- HDMI_R_D1+ 4 4 7 7 HDMI_R_D1+ HDMI_R_D1- 5 5 6 6 HDMI_R_D1- 1 L36 DLW21SN900HQ2L_0805 4 XEMC@ 4 XEMC@ G HDMI_TX1- R584 1 @ 2 0_0402_5% HDMI_R_D1- 2 3 2 SM070001E00 3 HDMI_TX1+ R586 1 @ 2 0_0402_5% HDMI_R_D1+ HDMI_TX2- R591 1 @ 2 0_0402_5% HDMI_R_D2- 1 1 L40 DLW21SN900HQ2L_0805 4 XEMC@ 4 R593 1 2 3 @ 2 2 C SM070001E00 3 0_0402_5% HDMI_R_D2+ HDMI_SCLK 6 SAGE 3G DVT SD034499080 S RES 1/16W 499 +-1% 0402 HDMI_TX2HDMI_TX2+ R592 1 R594 1 2 499_0402_1% 2 499_0402_1% HDMI_TX1HDMI_TX1+ R583 1 R587 1 2 499_0402_1% 2 499_0402_1% HDMI_TX0HDMI_TX0+ R564 1 R570 1 2 499_0402_1% 2 499_0402_1% HDMI_CLK- R573 1 HDMI_CLK+ R590 1 2 499_0402_1% 2 499_0402_1% HDMI_GND 6 5 G S 3 Q16A DMN66D0LDW-7_SOT363-6 1 HDMI_R_D0+ HDMI_SDATA D SDVO_SDATA S 16 SDVO_SDATA 0_0402_5% SAGE 3G R10 D 4 SDVO_SCLK 2 16 SDVO_SCLK 2 1 L39 DLW21SN900HQ2L_0805 4 XEMC@ 4 2 2 SAGE 3G Pull high at connector side @ HDMI_TX2+ 1 SDVO_SDATA SM070001E00 3 D11 RB751V-40_SOD323-2 1 2 R255 2.2K_0402_5% 2 2.2K_0402_5% D12 RB751V-40_SOD323-2 1 1 +3VS SDVO_SCLK 3 R571 1 TVWDF1004AD0_DFN 1 2 R257 2.2K_0402_5% R253 2 2.2K_0402_5% D 2 HDMI_TX0+ SC300002800 S DIO(BR) TVWDF1004AD0 DFN ESD 8 1 2 1 +HDMI_5V_OUT R250 SM070001E00 3 @ 3 3 +3VS 3 HDMI_R_CK- 2 R585 1 2 +3VS Q16B DMN66D0LDW-7_SOT363-6 G C 16 PCH_DPB_N0 16 PCH_DPB_P0 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K 0_0402_5% 2 XEMC@ TVWDF1004AD0_DFN 2 2 2 HDMI_CLK+ SAGE 3G C280 C281 @ 1 L38 DLW21SN900HQ2L_0805 4 XEMC@ 4 D @ R242 0_0603_5% 1 2 3 S 1 Q14B DMN66D0LDW-7_SOT363-6 Place closed to JHDMI1 B B Micro HDMI connector PCB Footrpint : E-T_0733K-S19M-00R_19P-T-S +3VS JHDMI1 1 +HDMI_5V_OUT R198 1M_0402_5% 5 HDMI_R_CK- G D 4 HDMI_R_D0+ HDMI_R_D1- 1 1 S HDMI_R_CK+ HDMI_R_D0- Q14A DMN66D0LDW-7_SOT363-6 3 HDMI_HPD 2 16 PCH_DPB_HPD HDMI_SDATA HDMI_SCLK R219 100K_0402_5% 2 C324 100P_0402_50V8J HDMI_R_D1+ HDMI_R_D2- 2 HDMI_R_D2+ HDMI_HPD A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +5V SDA SCL DDC/CEC_GND CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield GND D2+ GND Utility GND HP_DET GND 20 21 22 23 A E&T_0733K-S19M-00R E-T_0733K-S19M-00R_19P-T CONN@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 Title HDMI Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Tuesday, March 26, 2013 Sheet 1 23 of 52 Rev 0.1 5 4 For Wireless LAN 2 1 SAGE 3G 60mil +3VS 3 +3VS_W LAN Mini Card Power Rating +3VS_W LAN U1 +3VS_W LAN J10 1 D 2 1 JUMP_43X79 @ C403 4.7U_0603_6.3V6K 2 1 C735 0.1U_0402_16V4Z 2 1 2 +3VS_W LAN C387 0.1U_0402_16V4Z @ +3VALW +3VS_W LAN 17 PLT_RST_BUF# 15 PCH_PCIE_W AKE# 28,31 EC_PCIE_WAKE# U2008 5 4 OUT R702 1 R490 1 @ @ 28 W L_OFF# BT_CTRL R491 1 GND @ 2 R185 0_0402_5% 1 2 @ IN 3 G5243T11U_SOT23-5 SA000028Y00 1 C 40mil(1A) IN EN C2109 1U_0402_6.3V6K 1 G9 G10 17 USB20_P8 17 USB20_N8 SAGE 3G SAGE 3G 1 2 2 BT BT Enable Disable BT_ON# L H BT_CTRL H L +3VS_W LAN AOAC_ON 28 R427 1 C539 0.1U_0402_16V4Z @ R464 1 REFCLKREFCLK+ CLKREQ_L L6 L7 L8 L9 14 PCIE_PRX_DTX_N1 14 PCIE_PRX_DTX_P1 14 PCIE_PTX_C_DRX_P1 14 PCIE_PTX_C_DRX_N1 Support ISCT 3V3 3.3VAUX L4 L5 F1 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1 14 MINI1_CLKREQ# Without Support ISCT F12 G4 @ D1 2 0_0402_5% PCH_PCIE_W AKE#_R E1 2 0_0402_5% G6 G7 E12 G8 2 0_0402_5% BT_CTRL_R BT_LED F4 T74PAD @ 2 10K_0402_5% PCH_PCIE_W AKE#_R 2 10K_0402_5% MINI1_CLKREQ# SAGE 3G PVT A4,D12,F5,F9,F10,G5 -> GND at MD225 -> NC at MD222 1 3 S 2 G 28 BT_ON# Clock PERN0 PERP0 PETN0 PETP0 PCIE signal USB_D+ USB_D- USB signal PERST_L WAKE_L WIFI_DISABLE WIFI_LED BT_DISABLE BT_LED Control GND NC G1 G3 G5 G12 H1 H2 H11 H12 L1 L2 L3 L10 L11 L12 F10 F9 F8 GND[1] GND[2] GND[3] GND[4] GND[5] GND[6] GND[7] GND[8] GND[9] GND[10] GND[11] GND[12] GND[13] GND[14] GND[15] GND[16] GND[17] GND[18] GND[19] GND[20] GND[21] GND[22] GND[23] GND[24] GND[25] GND[26] GND[27] GND[28] GND[29] GND[30] GND[31] GND[32] GND[33] GND[34] GND[35] GND[36] GND[37] GND[38] GND[39] GND[40] GND[41] GND[42] GND[43] GND[44] GND[45] GND[46] GND[47] GND[48] GND[49] GND[50] GND[51] GND[52] GND[53] GND[54] GND[55] GND[56] GND[57] GND[58] GND[59] GND[60] GND[61] GND[62] GND[63] A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B11 B12 C1 C4 C5 C6 C7 C8 C9 C10 C12 D3 D4 D5 D6 D7 D8 D9 D10 D12 E3 E4 E5 E6 E7 E8 E9 E10 F3 F5 F6 F7 D C T77H281.01_81P PK29S003M00 FOXMD222@ BT_CTRL D Power Q62 2N7002KW _SOT323-3 B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title On Board WLAN Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: W ednesday, March 13, 2013 Sheet 1 24 of 52 A B For mSATA D E SAGE 3G 60mil +3VS C +3VS_FULL 20mil +3VS_FULL +1.5VS J8 1 2 1 JUMP_43X79 @ 2 1 C455 4.7U_0603_6.3V6K 1 2 C475 0.1U_0402_16V4Z 1 C466 0.1U_0402_16V4Z 2 1 2 C442 0.1U_0402_16V4Z 1 C441 0.1U_0402_16V4Z 2 1 Function SAGE 3G +1.5VS +3VS_FULL RAID0_DET Port0,1 H Port0 L JMINI1 C625 1 C627 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 @ @ C628 1 C626 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 From DG=>Change to 0.01u 13 SATA_PRX_DTX_P0 13 SATA_PRX_DTX_N0 13 SATA_PTX_DRX_N0 13 SATA_PTX_DRX_P0 C621 1 C622 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 C623 1 C624 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 +3VS_FULL 1 28 E51TXD_P80DATA 28 E51RXD_P80CLK 18 MSATA_DET# R300 8 7 6 5 RP42 R476 1 1 2 3 4 @ 2 0_0402_5% E51TXD_P80DATA_R E51RXD_P80CLK_R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 GND2 RAID0_DET 18 1 13 SATA_PRX_DTX_P1 13 SATA_PRX_DTX_N1 @ @ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 R329 100K_0402_5% 2 13 SATA_PTX_DRX_N1 13 SATA_PTX_DRX_P1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 54 1K_8P4R_5% ACES_51700-0520W -001 CONN@ 2 100K_0402_5% JMINI1 SP07000LL00 ACES_51700-0520W-001_52P 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title mSATA HDD Connector Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: W ednesday, March 13, 2013 Sheet E 25 of 52 5 D 4 3 2 1 D TPM SAGE 3G 10mil +3V_TPM J15 @ 1 2 TPM - Infineon SA00005XH40 S IC SLB9655TT1.2 FW4.31 TSSOP 28P TPM 2 2 2 1 2 0.1U_0402_16V4Z C538 TPM@ 2 1 0.1U_0402_16V4Z C536 TPM@ 2 1 0.1U_0402_16V4Z C535 TPM@ @ C1 10U_0603_6.3V6M 1 0.1U_0402_16V4Z C534 TPM@ JUMP_43X39 1 +3VS 1 +3V_TPM near pin10 near pin19 near pin24 U7 C VDD VDD VDD VDD C 24 19 10 5 near pin5 SAGE 3G R966 1 @ 13,28 SERIRQ 21 22 16 9 27 0_0402_5% 0_0402_5% 1 1 2 R967 2 R988 @ @ TPM_PP 7 LAD0 LAD1 LAD2 LAD3 GPIO TPM SLB 9655 TT 1.2 LCLK LFRAME# LRESET# LRESET# SERIRQ PP 4 11 18 25 +3V_TPM CLK_PCI_TXM LPC_FRAME# PLT_RST# 2 0_0402_5% SERIRQ LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 17 CLK_PCI_TXM 13,28 LPC_FRAME# 17,28,31,32,5 PLT_RST# 26 23 20 17 GND GND GND GND 13,28 13,28 13,28 13,28 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 CLK_PCI_TXM XEMC@ 1 R716 2 33_0402_5% 1 NC NC NC NC NC NC NC NC NC 6 28 15 14 13 8 1 3 12 2 SLB9655TT1.2_TSSOP28 TPM@ SA00005XH40 XEMC@ C724 2 22P_0402_50V8J B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/11/1 2011/11/1 Deciphered Date Title TPM Infineon-SLB9655 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Wednesday, March 13, 2013 Sheet 1 26 of 52 Rev 0.1 1 @ R9 3 For ESD request 2 0_0402_5% EMC@ 17 PCH_USB3_TX2_P 17 PCH_USB3_TX2_N 2 1 C424 2 PCH_USB3_TX2_N_C 0.1U_0402_16V7K 2 1 1 1 @ 2 0_0402_5% C110 1.8P_0402_50V8 SAGE 3G R10 D R11 U3TXDP2 D35 1 1 U3TXDN2 U3RXDP2 U3TXDP2 SM070001E00 3 4 U3TXDN2 3 4 XEMC@ L3 DLW 21SN900HQ2L_0805 1 2 0_0402_5% R10 1 @ 2 XEMC@ 1 2 1.8P_0402_50V8 C109 C422 1 2 PCH_USB3_TX2_P_C 0.1U_0402_16V7K U3RXDN2 U3TXDN2 4 4 7 7 U3RXDP2 5 5 SM070001E00 3 4 U3RXDN2 3 4 XEMC@ L4 DLW 21SN900HQ2L_0805 1 2 0_0402_5% R12 1 @ 2 0_0402_5% 2 2 3 17 USB20_P1 2 1 3 4 1 SM070001E00 4 +USB3_VCCA W=80mils SGA00002N80 For USB2.0 ESD request XEMC@ 1 2 D24 U2DP0 3 U2DN0 2 SAGE 3G 1 1 + 2 2 1 U3TXDN2 U2DP0 U2DN0 U3RXDP2 U2DP0 U3RXDN2 8 7 6 5 1 R314 @ 2 USB_OC0# 17 0_0402_5% AP2301MPG-13_MSOP8 1 C443 0.1U_0201_10V6K @ 2 D SGA00001E00 S POLY C 150U 6.3V M B2LESR45M PSL H1.9 9 1 8 3 7 2 6 4 5 SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX- JUSB1 E-T_6120K-S09N-00R_9P-T GND GND GND GND 10 11 12 13 E&T_6120K-S09N-00R CONN@ E-T_6120K-S09N-00R_9P-T L52 DLW 21SN900HQ2L_0805 1 2 @ R689 0_0402_5% Resister overlap with L52 C VOUT VOUT VOUT FLG JUSB1 U3TXDP2 TVNST52302AB0_SOT523-3 XEMC@ SCA00001W 00 SAGE 3G Reserve for RF U2DN0 GND VIN VIN EN U3RXDN2 C393 470P_0402_50V7K 1 EMC@ 17 USB20_N1 6 6 U17 1 2 3 4 28 USB_EN# 8 1.8P_0402_50V8 C111 @ 9 8 U3RXDP2 C112 1.8P_0402_50V8 1 2 2 +USB3_VCCA @ C432 0.01U_0402_16V7K 1 2 SC300002800 TVW DF1004AD0_DFN 1 SAGE 3G R10 R691 U3TXDP2 +5VALW C394 PCH_USB3_RX2_N 17 PCH_USB3_RX2_N 2 10 9 150U_B2_6.3VM_R35M 17 PCH_USB3_RX2_P XEMC@ 1 3 3 EMC@ 2 PCH_USB3_RX2_P 2 SC300002800 S DIO(BR) TVWDF1004AD0 DFN ESD SAGE 3G EPAD 4 9 5 C USB3.0 Conn. JCMOS2.5 to GND (Shielding GND as SED's requirement) SAGE 3G +3VS CAMERA1 JCMOS1 3 2 17 USB20_N10 17 USB20_P10 D17 TVNST52302AB0_SOT523-3 XEMC@ 1 2 3 4 5 6 1 2 3 4 5 G1 6 G2 7 8 JCMOS1 SP010013W00 ACES_88460-00601-P01_6P S H-CONN ACES 88460-00601-P01 6P P0.8 ACES_88460-00601-P01 CONN@ 1 SCA00001W 00 B B SAGE 3G A A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/06/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title USB3.0 Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Tuesday, March 26, 2013 Sheet 1 27 of 52 2 3 2 2 RB751V-40_SOD323-2 SAGE 3G EC SMI/SCI default PH R697 1 1 D40 @ R708 1 @ 2 18 EC_SCI# 31 EC_3G_PWR_EN# 44 BKOFF# 2 0_0402_5% @ 2 18 EC_SMI# EC_SMI#_R RB751V-40_SOD323-2 1 1 100K_0402_5% C528 2 1 SAGE 3G R20 EC_SCI#_R RB751V-40_SOD323-2 0_0402_5% R724 1 2 @ 1 2 @ 33 VOL_UP# 33 VOL_DOWN# B R938 2 18 GATEA20 EC_RST# R725 0_0402_5% 1U_0402_6.3V6K +3VALW_EC SAGE 3G DVT RP25 R962 1 R954 R953 1 1 EC_SMI# VOL_UP#_R VOL_DOWN#_R HOME_KEY R952 1 2 10K_0402_5% IRST_RST# 2 2.2K_0402_5% 2 2.2K_0402_5% EC_SMB_DA3 EC_SMB_CK3 +3VS 36,37 36,37 11,14 11,14 C 5 6 7 8 2.2K_8P4R_5% R946 1 R949 1 EC_SMB_DA1 EC_SMB_CK1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_PECI LID_SW# EC_SMB_CK3 EC_SMB_DA3 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 2 33 LID_SW# 2 0_0402_5% 0_0402_5% 15 PM_SLP_S3# 15 PM_SLP_S4# 15 PCH_RSMRST# 33 ON/OFF 38 EC_ON 31 3G_OFF# 15 PCH_PWROK 36 MAINPWON_L 31,34 PCH_PWR_EN 2 10K_0402_5% EC_SCI# 2 100K_0402_5% PLT_RST# 1 C1209 1 1 R719 R709 33 HOME_KEY 33 D_LOCK RP27 4 3 2 1 2 0.01U_0402_16V7K EMC@ ESD request +3VS 2 1K_0402_5% 2 D_LOCK 1 2 @ PM_SLP_S3# PM_SLP_S4# PCH_RSMRST# ON/OFF N1 N3 A1 E2 EC_ON 3G_OFF# MAINPWON_L PCH_PWR_EN N2 M3 N7 N8 D8 EC_CK32KE EC_CK32K G1 F2 FSCE# FMOSI FMISO FSCK RXD/SIN0/GPB0 TXD/SOUT0/GPB1 EGAD/WUI25/GPE1 EGCS#/WUI26/GPE2 EGCLK/WUI27/GPE3 GPJ1 SSCE0#/GPG2 SSCE1#/GPG0 DSR0#/GPG6 DTR1#/SBUSY/GPG1/ID7 RI1#/WUI0/GPD0 GPC0 WAKE UP RI2#/WUI1/GPD1 TMA0/GPB2 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 PWRSW/GPE4 TACH2/GPJ0 L80HLAT/BAO/WUI24/GPE0 TACH1A/TMA1/GPD7 L80LLAT/WUI7/GPE7 TACH0A/GPD6 GINT/CTS0#/GPD5 GPIO RTS1#/WUI5/GPE5 CLKRUN#/WUI16/GPH0/ID0 1 CK32KE/GPJ7 CK32K/GPJ6 @ 1 10K_0402_5% 1 1 2 2 XEMC@ C450 0.1U_0201_10V6K BKOFF# R934 1 @ 2 10K_0402_5% R936 R935 2 2 @ 1 200K_0402_5% 1 200K_0402_5% PROX_DET_EC POUT PWR_LED# BATT_AMB_LED# FAN_PWM USB_EN#_R HDA_SDO BEEP# EC_ACIN BI_DET G10 G13 G12 F9 F13 F10 F12 E13 AD_BID0 AD_PID0 CHG_TEMP BATT_TEMP EC_PCIE_WAKE# ADP_I SUSWARN# SLP_SUS# D12 C13 B13 C12 PCH_BATLOW# SA_PGOOD AOAC_ON EC_MUTE# A11 B11 A10 B10 D9 B9 EAPD IRST_RST# ENBKL WL_OFF# ON/OFF_R EC_LID_OUT# A9 B8 A8 B7 PCH_SPI_CS1# PCH_SPI_CLK_1 PCH_SPI_MISO_1 PCH_SPI_MOSI_1 A7 B6 A6 B5 EC_SPICS#/FSEL# EC_SO_SPI_SI EC_SI_SPI_SO EC_SPICLK 0_0402_5% 2 A4 A3 E51RXD_P80CLK E51TXD_P80DATA PROX_DET_EC 31 POUT 33 PWR_LED# 33 BATT_AMB_LED# 33 FAN_PWM 29 EC_ACIN GPIO 10P_0402_50V8J 2 R940 0_0402_5% 2 1 @ H_PROCHOT# 36,5 BI_DET 33 PCH_BATLOW# 15 SA_PGOOD 15,41 AOAC_ON 24 EC_MUTE# 33 EAPD 33 IRST_RST# 17 ENBKL 16 WL_OFF# 24 R726 @ 1 0_0402_5% 2 ON/OFF EC_LID_OUT# 18 PCH_SPI_CS1# 13 PCH_SPI_CLK_1 13 PCH_SPI_MISO_1 13 PCH_SPI_MOSI_1 13 @ 1 R698 1 E51RXD_P80CLK 25 E51TXD_P80DATA 25 A13 A12 B12 SYSON SUSP# VR_ON D13 E7 E6 D6 A5 D1 D2 PBTN_OUT# DPWROK H_PROCHOT#_EC BT_ON# GPS_OFF# EC_DS3_WAKE# SUSACK# E12 M12 M11 ACPRESENT EC_3G_USB_ON FAN_SPEED1 S Q60 2N7002KW_SOT323-3 2 ENBKL R950 1 BATT_TEMP 2 C1206 1 ECAGND 100P_0402_50V8J 2 CHG_TEMP C1208 1 ECAGND 100P_0402_50V8J 100K_0402_5% PLT_RST# EC_SPICLK_R D 2 G H_PROCHOT#_EC CHG_TEMP 36 BATT_TEMP 36 EC_PCIE_WAKE# 24,31 ADP_I 36,37 SUSWARN# 15 SLP_SUS# 15 C764 B EMC@ 1 2 0.1U_0402_16V4Z EC_ON T20 PAD @ SYSON T24 PAD @ C766 1 PCH_PWROK C1486 1.8P_0402_50V8 XEMC@ 2 0.1U_0201_10V6K XEMC@ For EMI SYSON 34,39 SUSP# 34,39,40,41 VR_ON 42,5 SAGE 3G Reserve for RF / Close to EC PBTN_OUT# 15 DPWROK 15 BT_ON# 24 GPS_OFF# 31 EC_DS3_WAKE# 18 SUSACK# 15 C SAGE 3G ACPRESENT 15 EC_3G_USB_ON 31 FAN_SPEED1 29 SAGE 3G R20 5 H_PECI 27 USB_EN# 43_0402_1% R951 2 AD_BID0 5 6 +3VALW_EC L57 1 ECAGND 2 FBMA-L11-160808-800LMT_0603 EC_PECI R958 +3VALW_EC R694 1 R690 1 EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD# 1 0_0402_5% USB_EN#_R @ G1 G2 ACES_50208-0040N-001 SP01000Q810 ACES_50208-0040N-001_4P CONN@ SAGE 3G Reserve for RF 1 3 7 4 4MB=32Mb CS# WP# HOLD# GND 8 6 5 2 VCC SCLK SI SO C723 1 C722 1 XEMC@ 2 47P_0402_50V8J 2 0.1U_0402_16V4Z EC_SPICLK_R EC_SO_SPI_SI_R R705 1 EC_SI_SPI_SO_R R692 1 @ @ 2 0_0402_5% EC_SO_SPI_SI 2 0_0402_5% EC_SI_SPI_SO D W25Q32BVSSIG_SO8 SA00003K800 EC_SPICLK_R SAGE 3G XEMC@ R695 1 XEMC@ C727 2 0_0402_5% 17,26,31,32,5 PLT_RST# 56K_0402_5% R960 Rb 1 1 2 3 4 IT8518VG-HX_VFBGA128 U40 2 1 2 3 4 EC_SMB_CK3 EC_SMB_DA3 E51RXD_P80CLK E51TXD_P80DATA 10P_0402_50V8J 2 C1213 0.1U_0402_16V4Z PLT_RST# 1 R711 @ 2 PLT_RST#_R 0_0402_5% Issued Date 2011/06/24 2012/06/02 Deciphered Date Title EC ITE-IT8518 Rev 0.1 V1JB1 M/B LA-A041P Schematic Wednesday, March 13, 2013 Date: 2 33P_0402_50V8K Compal Electronics, Inc. Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SAGE 3G R20 1 ACIN 34,37 1 100P_0402_50V8J VR_HOT# 42 VR_HOT# A +3VLP +3VALW 1 RB751V-40_SOD323-2 2 C1207 HDA_SDO 13 BEEP# 33 Clock 32.768KHZ_12.5PF_1TJF125DP1A000D SJ100004Z00 1 C758 C759 1 C1217 0.1U_0402_16V4Z SPI Flash ROM UART 1 Analog Board ID definition, Please see page 3. 1 2 HSCE#/WUI19/GPH3/ID3 HSCK/GPH4/ID4 HMISO/GPH5/ID5 HMOSI/GPH6/ID6 M5 N5 M6 N6 K6 J6 M7 K7 C2 E1 Board ID 1 Rb R455 56K_0402_5% PS2CLK0/TMB0/GPF0 PS2DAT0/TMB1/GPF1 PS2CLK1/DTR0#/GPF2 PS2DAT1/RTS0#/GPF3 PS2CLK2/WUI20/GPF4 PS2DAT2/WUI21/GPF5 SMCLK0/GPB3 SM Bus SMDAT0/GPB4 SMCLK1/GPC1 SMDAT1/GPC2 SMCLK2/PECI/WUI22/GPF6 SMDAT2/PECIRQT#/WUI23/GPF7 WUI17/SIN1/SMCLK3/GPH1/ID1 WUI18/SOUT1/GPH2/SMDAT3/ID2 2 AD_PID0 X3 R957 100K_0402_5% Ra 1 1 Ra +3VALW_EC Analog Project ID definition R454 100K_0402_5% 2 D Project ID 2 2 +3VALW_EC B4 A2 B3 B2 B1 C1 E8 D7 XTAL SAGE 3G DVT @ DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3 DAC4/DCD0#/GPJ4 DAC5/RIG0#/GPJ5 PS2 2 JEC2 SAGE 3G R758 1 ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/WUI28/GPI4 ADC5/DCD1#/WUI29/GPI5 ADC6/DSR1#/WUI30/GPI6 ADC7/CTS1#/WUI31/GPI7 DAC XEMC@ C451 0.1U_0201_10V6K 2 SAGE 3G +3VALW_EC IO/B_DET EC_3G_ON_OFF# EC_3G_RST# PM_SLP_S5# DRAMRST_CNTRL_EC 33 IO/B_DET 31 EC_3G_ON_OFF# 31 EC_3G_RST# 15 PM_SLP_S5# 6 DRAMRST_CNTRL_EC 100K_8P4R_5% 2 100K_0402_5% EC_PCIE_WAKE# @ @ @ 2 100K_0402_5% KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 KSO0/PD0 Int. K/B KSO1/PD1 Matrix KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5 R928 2 ADC VSS/GND VSS/GND VSS/GND VSS/GND VSS/GND VSS/GND 1 5 6 7 8 J12 J13 J9 H12 H9 H10 H13 G9 M8 J7 N9 M9 K8 J8 N10 M10 N11 K9 N12 N13 M13 L12 L13 K12 K13 J10 EC_MUTE# FAN_PWM D37 PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM PWM4/GPA4 PWM5/GPA5 PWM6/SSCK/GPA6 PWM7/RIG1#/GPA7 TMRI0/WUI2/GPC4 TMRI1/WUI3/GPC6 E5 F4 F5 G4 G5 H5 R943 VOL_UP#_R VOL_DOWN#_R IO/B_DET = 1 -> IO/B connected. IO/B_DET = 0 -> IO/B disconnected. 4 3 2 1 KBRST#/GPB6 SERIRQ/GPM6 LFRAME#/GPM5 LAD3/GPM3 LAD2/GPM2 LAD1/GPM1 LAD0/GPM0 LPC LPCCLK/GPM4 WRST# ECSMI#/GPD4 PWUREQ#/BBO/SMCLK2ALT/GPC7 LPCPD#/WUI6/GPE6 LPCRST#/WUI4/GPD2 ECSCI#/GPD3 GA20/GPB5 2 0_0402_5% D48 XEMC@ C1205 XEMC@ R933 22P_0402_50V8J 33_0402_5% 2 1 2 1 CLK_PCI_LPC +3VALW_EC H4 G2 H1 H2 J1 J2 K1 K2 L1 L2 M2 M1 M4 N4 F1 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_LPC EC_RST# EC_SMI#_R EC_3G_PWR_EN# BKOFF# PLT_RST#_R EC_SCI#_R GATEA20 18 EC_KBRST# 13,26 SERIRQ 13,26 LPC_FRAME# 13,26 LPC_AD3 13,26 LPC_AD2 13,26 LPC_AD1 13,26 LPC_AD0 17 CLK_PCI_LPC 33 EC_RST# 1 100K_0402_5% +3VS FAN_SPEED1 AVSS/AGND 1 C1219 0.1U_0402_16V4Z 2 C1216 0.1U_0402_16V4Z 1 1 D58 2 2 1 +EC_VBAT 2 1 R948 3 +RTCVCC E10 +3VS VBAT/VCC SAGE 3G A 1 ECAGND +EC_VBAT E9 2 +3VS LID_SW# SAGE 3G DVT AVCC 2 1 +3VALW 1 FBMA-L11-160808-800LMT_0603 C1202 1000P_0402_50V7K 1 U53 +EC_VBAT 8 +3VALW_EC 0.1U_0402_16V4Z C1204 2 7 L56 2 +EC_AVCC +VCORE_EC C1210 0.1U_0402_16V4Z 2 1 6 +EC_VCCPLL SAGE 3G C1212 0.1U_0402_16V4Z 2 1 C1211 0.1U_0402_16V4Z 2 1 C1203 0.1U_0402_16V4Z 1 C1201 0.1U_0402_16V4Z 2 C1200 0.1U_0402_16V4Z 2 1 C1199 0.1U_0402_16V4Z SAGE 3G C1198 0.1U_0402_16V4Z 1 +3VALW_EC L58 1 2 FBMA-L11-160808-800LMT_0603 12mil J5 D4 K4 K10 D5 D10 E4 +3VALW_EC EXTERNAL SERIAL FLASH 2 2 5 K5 1 JUMP_43X39 4 +EC_VCCPLL VCC/VCC VSTBY/VCC VSTBY/VCC VSTBY/VCC VSTBY/VCC VSTBY/VCC VSTBY/VCC J11 @ 1 +3VALW_EC J4 +3VALW_EC VCORE/VCC 1 +3VLP 3 4 5 6 7 Sheet 28 8 of 52 FAN Conn SAGE 3G 1 1 2 2 JUMP_43X39 定定螺 C585 10U_0805_25V6K 1 2 C587 1000P_0402_50V7K 1 2 FD1 FD2 @ 1 +3VS 1 FIDUCIAL_C40M80 R489 10K_0402_5% FD3 @ FIDUCIAL_C40M80 FD4 @ 1 J17 @ 1 +5VS 1 20mil FIDUCIAL_C40M80 Thermal module @ FIDUCIAL_C40M80 mSATA Stand-Off 3G Stand-Off @ @ @ H19 H_3P2 @ @ 1 @ H5 H_3P2 1 ACES_50208-0040N-001 SP01000Q810 ACES_50208-0040N-001_4P CONN@ 螺螺 H12 H_2P5 1 @ H7 H_3P0 @ H15 H_2P5 @ H16 H_2P5 @ H20 H_2P5 @ 1 H11 H_2P5 1 JFAN1 conn SP01000Q810 ACES_50208-0040N-001_4P S H-CONN ACES 50208-0040N-001 4P P.8 1 2 H4 H_4P2 1 5 6 H3 H_4P2 1 C579 1000P_0402_50V7K G1 G2 H2 H_4P2 1 28 FAN_PWM H1 H_4P2 1 1 1 2 3 4 1 28 FAN_SPEED1 1 2 3 4 1 2 JFAN1 FAN_SPEED1 FAN_PWM @ H6 H_4P0x3P0 1 @ 1 CLIP30 ICSRC6510-015SFR_1P CLIP42 ICSRC6510-015SFR_1P CLIP44 ICSRC6510-015SFR_1P 1 CLIP43 ICSRC6510-015SFR_1P CLIP20 ICSRC6510-015SFR_1P 1 1 CLIP28 ICSRC6510-015SFR_1P 1 CLIP29 ICSRC6510-015SFR_1P CLIP10 ICSRC6510-015SFR_1P 1 1 1 CLIP18 ICSRC6510-015SFR_1P 1 CLIP19 ICSRC6510-015SFR_1P 1 CLIP37 ICSRC6510-015SFR_1P CLIP8 ICSRC6510-015SFR_1P 1 1 1 CLIP27 ICSRC6510-015SFR_1P CLIP9 ICSRC6510-015SFR_1P 1 CLIP36 ICSRC6510-015SFR_1P CLIP17 ICSRC6510-015SFR_1P 1 1 1 CLIP26 ICSRC6510-015SFR_1P CLIP7 ICSRC6510-015SFR_1P 1 CLIP35 ICSRC6510-015SFR_1P CLIP16 ICSRC6510-015SFR_1P 1 1 1 CLIP25 ICSRC6510-015SFR_1P CLIP6 ICSRC6510-015SFR_1P 1 CLIP34 ICSRC6510-015SFR_1P CLIP15 ICSRC6510-015SFR_1P 1 1 1 CLIP24 ICSRC6510-015SFR_1P CLIP5 ICSRC6510-015SFR_1P 1 CLIP33 ICSRC6510-015SFR_1P CLIP14 ICSRC6510-015SFR_1P 1 1 1 CLIP23 ICSRC6510-015SFR_1P 1 1 1 CLIP31 ICSRC6510-015SFR_1P CLIP13 ICSRC6510-015SFR_1P CLIP4 ICSRC6510-015SFR_1P 1 1 CLIP32 ICSRC6510-015SFR_1P CLIP21 ICSRC6510-015SFR_1P CLIP3 ICSRC6510-015SFR_1P 1 1 CLIP22 ICSRC6510-015SFR_1P CLIP11 ICSRC6510-015SFR_1P 1 1 CLIP12 ICSRC6510-015SFR_1P CLIP2 ICSRC6510-015SFR_1P 1 1 CLIP1 ICSRC6510-015SFR_1P SAGE 3G DVT Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date CLIP47 ICSRC6510-015SFR_1P 1 CLIP48 ICSRC6510-015SFR_1P 1 CLIP49 ICSRC6510-015SFR_1P 1 CLIP45 ICSRC6510-015SFR_1P 1 CLIP46 ICSRC6510-015SFR_1P 1 CLIP41 ICSRC6510-015SFR_1P 1 CLIP40 ICSRC6510-015SFR_1P 1 CLIP39 ICSRC6510-015SFR_1P 1 1 CLIP38 ICSRC6510-015SFR_1P 2011/06/24 Deciphered Date 2012/06/02 Title FAN,Screw Hole THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Wednesday, March 13, 2013 Sheet 29 of 52 +3V_SEN +3V_SEN +3V_SEN GYRO SA00005HQ00 L3GD20TR C481 0.1U_0402_16V7K U143 C483 1 2 0.1U_0402_16V7K 1 I2C_1_SCL_SENSOR 2 I2C_1_SDA_SENSOR 3 4 GYRO_SA0 CS : 1 -> I2C mode 0 -> SPI mode 5 GYRO_DRDY 6 GYRO_INT 7 ST design Co-lay BOM control 8 VDD_IO RES_1 SCL/SPC RES_2 SDA/SDI/SDO RES_3 SDO/SA0 RES_4 CS GND DRDY/INT2 RES_5 INT1 RES_6 RES_0 VDD 1 1 2 2 ACCEL+E-COMPASS +3V_SEN C1269 10U_0603_6.3V6M +3V_SEN 9 C487 1 2 0.1U_0402_16V7K 1 C1290 2 1 10 1 11 C1288 0.22U_0402_10V6K 12 6 12 13 4.7U_0603_6.3V6K 2 13 8 9 10 11 MAG_DRDY 14 C630 1 2 0.01U_0402_16V7K 15 C485 0.1U_0402_16V7K U141 7 +3V_SEN Vdd_IO Vdd C1 SDA SETP SETC SCL INT1 Reserved Reserved Reserved Reserved INT2 14 3 I2C_1_SDA_SENSOR 2 I2C_1_SCL_SENSOR 5 ACCEL_INT1 4 ACCEL_INT2 1 1 2 2 C510 10U_0603_6.3V6M 1 INTEL@ 2 R481 100K_0402_5% SAGE 3G GND 16 LSM303DLHCTR_LGA14_3X5 L3GD20TR_LGA16_4X4 INTEL@ R524 +3V_SEN 1 ST@ 2 0_0402_5% R240 1 GYRO_SA0 2 100K_0402_5% SAGE 3G Resister overlap with L68 +3VALW +3VLP 2 2 2 2 1 2 1 2 1 2 AP2301GN-HF_SOT23-3 Q69 100K_0402_5% 1 2 1 1 R1328 1M_0402_5% @ R1331 2 G S HUB_PWRGATE 3 1 X4 1 To PCH GPIO35 D Q83 2N7002K_SOT23-3 HUB_32_OUT 2 SAGE 3G 2 1 1 2 1 1M_0402_5% R469 1 USB20_P1_HUB 1 1U_0402_6.3V6K C531 2 0_0402_5% @ 1 0.1U_0402_16V7K C530 R707 1 17 USB20_P0 SM070001E00 4 DLW21SN900HQ2L_0805 1U_0402_6.3V6K C509 4 0.1U_0402_16V7K C507 1 3 3 SAGE 3G R10 0.1U_0402_16V7K C506 2 1 +3V_SEN +3V_SEN 0.1U_0402_16V7K C504 Sensor Hub +3VALW USB20_N1_HUB 0.1U_0402_16V7K C503 2 @ L68 3 2 0_0402_5% @ 2 R706 1 17 USB20_N0 18 R1329 0.1U_0402_16V7K 2 HUB_32_IN 32.768KHZ_12.5PF_1TJF125DP1A000D SJ100004Z00 INTEL@ 1 1 C762 C763 18P_0402_50V8J 18P_0402_50V8J INTEL@ INTEL@ 2 2 SAGE 3G +3V_SEN 4 3 2 1 HUB_DBG_PB3 HUB_DBG_PB4 HUB_DBG_PA13 HUB_DBG_PA15 SAGE 3G HUB_XCLKOUT RP26 +3V_SEN INTEL@ C760 2 18P_0402_50V8J INTEL@ C761 2 18P_0402_50V8J INTEL@ R1322 R1319 1 2 0_0402_5% @ 1 INTEL@ 2 0_0402_5% HUB_BOOT0 R1323 R473 1 INTEL@ 2 0_0402_5% 1 INTEL@ 2 10K_0402_5% HUB_BOOT1 HUB_DBG_PA14 1 ST@ C761 2 33 ALS_INT ACCEL_INT1 R477 1 INTEL@ 2 0_0402_5% ALS_INT R478 1 INTEL@ 2 0_0402_5% GYRO_INT R479 1 INTEL@ 2 0_0402_5% JHDB1 1 15P_0402_50V8J 1 2 3 4 5 6 7 8 9 10 GND GND ST@ C760 2 1 15P_0402_50V8J 12MHZ_12PF_X1H012000DC1H-HX ST design Co-lay BOM control 1 2 3 4 5 6 7 8 9 10 11 12 HUB_DBG_PB4 HUB_DBG_PA15 HUB_DBG_PA13 HUB_DBG_PA14 HUB_DBG_PB3 HUB_RST# 2 0_0402_5% R1320 1 HUB_RST# @ MAG_DRDY R488 1 INTEL@ 2 0_0402_5% GYRO_DRDY R492 1 INTEL@ 2 0_0402_5% ACCEL_INT2 R494 1 INTEL@ 2 0_0402_5% @ PAD T31 ACES_85201-1005N CONN@ SP01000H400 TO Sensor (HUB Host) For Sensor Orientation Setting (303I, 303m, 303n)=(PA1, PA2, PA3)= 1,0,0 (4200I, 4200m, 4200n)=(PA4, PA5, PA6)= 1,1,0 +3V_SEN +3V_SEN +3V_SEN +3V_SEN HUB_PA8 HUB_PA9 HUB_PA10 USB20_N1_HUB USB20_P1_HUB HUB_DBG_PA13 HUB_DBG_PA14 HUB_DBG_PA15 HUB_PB0 HUB_PB1 HUB_BOOT1 HUB_DBG_PB3 HUB_DBG_PB4 I2C_1_SCL_SENSOR I2C_1_SDA_SENSOR 33 I2C_1_SCL_SENSOR 33 I2C_1_SDA_SENSOR To PCH GPIO68 2 0_0402_5% HUB_PB13 R497 1 @ R496 1 INTEL@ 2 0_0402_5% HUB_DFU_EN#_R HUB_PB15 18 HUB_DFU_EN# +3V_SEN F6 E6 H8 G7 H7 E5 G5 G4 E4 D2 D3 C1 C2 D4 B2 C3 H4 F4 H3 A4 B4 A5 B5 C5 D5 B6 G3 F3 G2 G1 F2 F1 PA0-WKUP PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 NRST BOOT0 Vref+ Vbat 2 R603 10K_0402_5% @ 1 2 HUB_PA5 @ R597 10K_0402_5% 1 ST@ R600 10K_0402_5% 2 1 2 HUB_PA4 1 1 2 HUB_PA3 ST@ R580 10K_0402_5% ST@ R602 10K_0402_5% 1 1 2 1 HUB_PA2 ST@ R605 10K_0402_5% @ R599 10K_0402_5% 2 2 2 R607 10K_0402_5% @ @ R601 10K_0402_5% 2 1 2 1 HUB_PA1 1 2 1 ST design Co-lay ST@ R606 10K_0402_5% @ R598 10K_0402_5% HUB_PA10 R1110 1 ST@ 2 USB20_P1_HUB 1.5K_0402_1% 1 ALS_INT R1346 HUB_PA6 ST@ R596 10K_0402_5% R1343 ST@ 1 ACCEL_INT1 1 ACCEL_INT2 R1342 ST@ 2 0_0402_5% 2 0_0402_5% R1345 ST@ 1 GYRO_INT 1 GYRO_DRDY R1344 ST@ 2 0_0402_5% HUB_BOOT1 2 0_0402_5% HUB_DBG_PB3 ST@ 2 0_0402_5% ST@ 2 0_0402_5% 1 MAG_DRDY R1347 PC0 PC1 PC2 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PD2 F5 A7 B1 H2 E7 +3V_SEN HUB_PA0 HUB_PA1 HUB_PA2 HUB_PA3 HUB_PA4 HUB_PA5 HUB_PA6 SAGE 3G PVT ST design Co-lay C508 0.1U_0402_16V7K 2 U140 ST@ HUB_RST# SAGE 3G +3V_SEN Y3 R459 100K_0402_5% ST@ SAGE 3G 2 5 6 7 8 INTEL@ 10K_8P4R_5% G6 A8 A1 H1 G8 8MHZ_12PF_FSX5M-8.000000M12FAO 3 HUB_XCLKIN 2 1 VDD_4 VDD_3 VDD_2 VDD_1 VDDA 1 2 0_0402_5% @ Y3 4 1 I2C_1_SCL_SENSOR I2C_1_SDA_SENSOR USB20_P1_HUB VSS_4 VSS_3 BYPASS/VSS_2 VSS_1 VSSA R495 1 1 2 2.2K_0402_1% 1 2 2.2K_0402_1% 1 INTEL@ 2 1.5K_0402_1% 1 +3V_SEN R453 R466 R1109 E8 F8 D6 H6 H5 E1 E2 E3 D1 A2 B3 C4 C8 B8 B7 HUB_32_IN HUB_32_OUT A3 C7 A6 F7 C6 HUB_RST# HUB_BOOT0 R1326 1 R1330 1 INTEL@ 2 0_0402_5% 1 C456 OSC_IN OSC_OUT D8 D7 +3V_SEN ST@ 2 0_0402_5% +3VLP 2 0.1U_0402_16V7K HUB_XCLKIN HUB_XCLKOUT STM32F103RCY6TR_WLCSP64 SA00005P210 S IC STM32F103RCY6TRC16 WLCSP MCU V1JV1 HUB_PB15 HUB_DFU_EN#_R HUB_PB0 HUB_PB1 ST@ HUB_BOOT0 R1319 2 1 20K_0402_5% BOM control Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SENSOR Size C Date: Document Number Rev 0.1 V1JB1 M/B LA-A041P Schematic Tuesday, March 26, 2013 Sheet 30 of 52 5 4 3 1 XEMC@ 2 2 3G@ EC_3G_PWR_EN# 5 2 3G@ Q93A DMN66D0LDW-7_SOT363-6 3G@ SAGE 3G R20 nOE Y+ X H Hi-Z Hi-Z L L M+ M- H L D+ D- 2 1 2 3G@ 2 3G@ 1 1 2 3G@ 1 + 2 3G@ 1 + 2 3G@ 2 3G@ 1 + 2 3G@ D EC_3G_PWR_EN# Connect to EC GPS_DISABLE# R645 1 3G@ 2 0_0402_5% GPS_OFF# W_DISABLE# R655 1 3G@ 2 0_0402_5% 3G_OFF# PWR_ON_OFF# R1333 1 3G@ 2 100K_0402_5% GPS_OFF# 28 3G_OFF# 28 +3VS_WWAN Y- 1 470P_0402_50V7K C395 33P_0402_50V8K C397 C 2 SAGE 3G DVT SAGE 3G R20 3G Module Connector (NGFF) +3VS_WWAN J3G1 PAD 1 2 3 4 5 6 7 8 SIM_CLK SIM_IO SIM_DET SIM_RST SIM_PWR 2 3G@ CLK I/O SIM Card Detect RST Vpp Vcc GND GND C549 1 SIM_PWR GND GND GND GND GND GND 9 10 11 12 13 14 PAD 2 33P_0402_50V8K 24,28 EC_PCIE_WAKE# SIM_CLK C398 1 3G@ 2 33P_0402_50V8K SIM_RST C399 1 2 33P_0402_50V8K 2 0_0402_5% @ T28 @ 1 3G@ 1 TPC32 PAD TPC32 PAD PAD PAD TVNST52302AB0_SOT523-3 XEMC@ SCA00001W00 T35 T36 T37 T38 33P_0402_50V8K 2 1 C401 3G@ 330P_0402_50V7K 330P_0402_50V7K 330P_0402_50V7K 330P_0402_50V7K 2 2 2 2 1 C825 1 C826 1 C827 1 C828 @ @ @ @ ANT_TUNE_0_AP ANT_TUNE_1_AP ANT_TUNE_2_AP ANT_TUNE_3_AP 3G_RESET# @ @ @ @ 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 1 1 1 1 1 @ @ @ @ @ 2 2 2 2 2 2 R644 3G_CONFIG0 WAKE_OUT_WWAN BODYSAR_DET# ANT_TUNE_0 ANT_TUNE_1 ANT_TUNE_2 ANT_TUNE_3 3G_RESET#_R 3G_CONFIG1 R639 R640 R641 R642 R643 PAD T29 @ PAD T30 @ 1 3 5 7 9 11 2 10K_0402_5% R485 For Tunable Antenna D25 SIM_RST 1 3G@ 3G@ 3 USB20_P2_R USB20_N2_R SAGE 3G R10 3G@ 2 1U_0402_6.3V6K C400 1 MOLEX_503960-0694 CONN@ MOLEX_503960-0694_8P-T SIM_DET 3G_CONFIG3 T23 @ +3VS_WWAN JSIM1 2 3G@ 2 C548 0.1U_0603_25V7K 3G@ SAGE 3G DVT 1 2 1 Q93B DMN66D0LDW-7_SOT363-6 3G@ 1 SAGE 3G PVT USB SW truth table SEL 1 SAGE 3G R20 6 3VS_WWAN_GATE 1 2 100K_0402_5% 3 R499 1 3G@ 28 EC_3G_PWR_EN# 2 4 PI3USB102ZLEX_TQFN10_1P6X1P3 3G@ SA000036200 1 G 1 2 1 4 10mil 3G@ 1 R637 33_0402_5% S USB20_P2_SW USB20_N2_SW 20mil D EC_3G_USB_ON_R 1 JUMP_43X118 R482 200_0603_5% 3G@ S 10 9 8 7 6 0.1U_0402_16V7K C488 SEL Vdd OE D+ D- 2 @ J12 1 220U_B2_2.5VM_R15M C610 3G@ 1 R483 47K_0402_5% +3VS_WWAN 240mil 33P_0402_50V8K C404 XEMC@ 2 +VSB +3VALW 0.01U_0402_16V7K C631 USB20_P2 USB20_N2 1 +3VALW D U24 1 2 Y+ 3 Y4 GND 5 MM+ 1 2 C545 3G@ 4.7U_0603_6.3V6K 2 0_0402_5% @ 3G@ 2 0_0402_5% 2 100K_0402_5% @ 2 2 C546 3G@ 4.7U_0603_6.3V6K R728 1 R729 1 R451 1 28,34 PCH_PWR_EN 28 EC_3G_USB_ON 2 1 0.1U_0402_16V4Z C553 XEMC@ Resister overlap with L53 SAGE 3G R10 33P_0402_50V8K C402 XEMC@ 1 +3VS_WWAN +3VS 240mil 220U_B2_2.5VM_R15M C609 SM070001E00 4 3GEMC@ USB20_N2_R L53 +3VS_WWAN U23 3G@ SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 220U_B2_2.5VM_R15M C608 4 DLW21SN900HQ2L_0805 1 XEMC@ 2 R727 0_0402_5% +3VALW Rds=13.5mΩ(Typ) 16.5mΩ(Max) 22U_0805_6.3V6M C550 3 USB20_P2_R 0.1U_0402_16V4Z C540 3 USB20_N2_SW 0_0402_5% 1 1U_0402_6.3V6K C551 2 @ R731 1 330P_0402_50V7K C824 1 17 USB20_N2 2 1 +3VALW to +3VS_WWAN 0_0402_5% 2 USB20_P2_SW 0_0402_5% D 2 @ R730 G R712 1 17 USB20_P2 2 3G_CONFIG2 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 CONFIG_3 Ground Ground USB_D+ USB_DGround 3.3V 3.3V Power_On_Off W_DISABLE# LED# CONFIG_0 Reserved Wake_On_WWAN# Reserved BODYSAR_N Reserved Ground GPS_DISABLE# NC Reserved NC UIM-RESET Ground UIM-CLK NC UIM-DATA NC UIM-PWR Ground NC NC Reserved NC Reserved Ground Reserved NC Reserved NC Reserved Ground NC NC NC NC NC Ground NC ANTCTL0 NC ANTCTL1 Reserved ANTCTL2 Reserved ANTCTL3 Reserved Reset# SIM_DET CONFIG_1 NC Ground 3.3V Ground 3.3V CONFIG_2 3.3V GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 PWR_ON_OFF# W_DISABLE# WWAN_LED# @ T44 PAD GPS_DISABLE# SIM_RST SIM_CLK SIM_IO SIM_PWR C SIM_DET BELLW_80149-3223_67P BELLW_80149-3223_67P-T SAGE 3G R20 CONN@ +1.8VS R501 1 3G@ 2 BODYSAR_DET# 10K_0402_5% 28 PROX_DET_EC PROX_DET_EC 1 B D Q94 3 B S 2N7002KW_SOT323-3 3G@ 2 G PLT_RST# R1136 2 @ 1 0_0201_5% R1137 2 @ 1 0_0201_5% 1 R311 2 @ 8.2K_0402_5% C407 0.1U_0402_16V4Z @ SAGE 3G PVT +3VALW_EC 3G_RESET# 1 28 EC_3G_RST# 17,26,28,32,5 1 2 2 R260 100K_0402_5% @ 2 1 +3VS_WWAN 10K_0402_5% R505 @ R504 1 @ 2 100K_0402_5% A 28 EC_3G_ON_OFF# A 2 R1138 @ 1 PWR_ON_OFF# 0_0201_5% SAGE 3G R10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title 3G/GPS HUAWEI MU736 Size C Date: 5 4 3 2 Document Number Rev 0.1 V1JB1 M/B LA-A041P Schematic Tuesday, March 26, 2013 Sheet 1 31 of 52 5 4 3 +3VS +3VS_CARD 1 40 mils 1 2 2 JUMP_43X39 40 mils U145 14 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_P2 1 14 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_N2 2 14 CLK_PCIE_CARD CLK_PCIE_CARD 3 14 CLK_PCIE_CARD# CLK_PCIE_CARD# 4 D 1 C1521 PCIE_PRX_DTX_P2 1 C1522 PCIE_PRX_DTX_N2 1 C1519 14 PCIE_PRX_DTX_N2 20 mils 2 AV12 4.7U_0603_6.3V6K 2 PCIE_PRX_C_DTX_P2 0.1U_0402_10V7K 2 PCIE_PRX_C_DTX_N2 0.1U_0402_10V7K 5 6 7 8 +ODR_PW R 20 mils 9 40 mils 10 40 mils 11 1 2 DV12 0.1U_0402_10V7K C1523 +3VS_CARD 1 2 C1525 0.1U_0402_10V7K 2 12 13 @ 20 mils 2 C 1 2 DV33_18 C1527 0.1U_0402_10V7K 1 @ C1526 4.7U_0603_6.3V6K C1524 10U_0603_6.3V6M 1 14 15 16 17 18 19 @ 1 1 J14 @ Card Reader 14 PCIE_PRX_DTX_P2 2 2 C1529 5P_0402_50V8C 1 SD_D1_R R1573 1 SD_D0_R R1574 SD_CLK_R 1 R1575 SD_CMD_R 1 R1576 1 SD_D3_R R1577 @ @ @ @ 2 SD_D1 0_0402_5% 2 SD_D0 0_0402_5% 2 SD_CLK 10_0402_5% 2 SD_CMD 0_0402_5% 2 SD_D3 0_0402_5% 20 21 22 23 24 RREF HSIN 3V3_IN REFCLKP CLK_REQ# REFCLKN PERST# EEDO HSOP EECS HSON EESK GPIO/EEDI DV12 MS_INS# SD_CD# 3V3_IN SP15 Card2_3V3 SP14 XD_CD# SP13 DV33_18 SP12 GND SP11 SP1 SP10 SP2 SP9 SP3 SP8 SP4 SP7 SD_D1 SP6 SD_D0 SP5 DV12_S SD_CMD GND SD_D3 RREF R1572 2 47 40 mils 46 CARD_CLKREQ# 45 PLT_RST# 1 6.2K_0603_1% 2 C1520 1 0.1U_0402_10V7K D CARD_CLKREQ# 14 PLT_RST# 17,26,28,31,5 43 42 41 GND SD_CLK 48 44 AV12 Card1_3V3 +3VS_CARD 10 mils HSIP SD_D2 40 39 38 SD_CD# SAGE 3G PVT SP15_SDW P_XDD7 R720 1 @ 2 0_0402_5% 37 36 35 34 33 32 C 31 30 29 20 mils 28 27 1 2 4.7U_0603_6.3V6K 1 @ 2 0.1U_0402_10V7K C1528 DV12_S C1530 26 25 SD_D2 R1578 1 @ 2 SD_D2_R 0_0402_5% RTS5209-GR_LQFP48_7X7 Reserve for EMI please close to JREAD1 B XEMC@ 2 1 1 XEMC@ 2 C1531 6P_0402_50V8D R1579 33_0402_5% JREAD1 SD_D2_R SD_D3_R SD_CMD_R +ODR_PW R SD_CLK_R SD_D0_R SD_D1_R SD_CD# 1 2 @ R1581 0_0402_5% 1 2 3 4 5 6 7 8 9 10 B DAT2 CD/DAT3 G5 CMD G4 VDD G3 CLK G2 VSS G1 DAT0 DAT1 SWITCH TERM CD DET TERM (GND) 15 14 13 12 11 +ODR_PW R 1 2 2 2 1 1 @ 2 C1535 0.1U_0402_10V7K 1 @ C1534 0.1U_0402_10V7K A 1 C1533 10U_0603_6.3V6M R1580 100K_0402_5% @ C1532 0.1U_0402_10V7K PROCO_879S-N010-03A0 SP07000US00 S SOCKET PROCONN 879S-N010-03A0 10P M-SD PROCO_879S-N010-03A0_10P CONN@ @ 2 A Close to connector Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Card Reader RTS5209 Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: W ednesday, March 13, 2013 Sheet 1 32 of 52 5 4 3 2 1 D D JIO1 11 TM_D11 TM_D+ 28 D_LOCK 28 VOL_DOWN# 28 VOL_UP# 28 HOME_KEY +3VLP +3V_SEN +3VS_WWAN +RTCBATT_R +RTCVCC +5VS SAGE 3G DVT TM_DTM_D+ ON/OFFBTN# D_LOCK VOL_DOWN# VOL_UP# HOME_KEY +3VS 28 IO/B_DET IO/B_DET 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 USB20_P11 USB20_N11 USB20_P11 17 USB20_N11 17 DMIC_CLK HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_SDIN0 HDA_RST_AUDIO# HDA_SDOUT_AUDIO I2C_1_SDA_SENSOR I2C_1_SCL_SENSOR DMIC_DATA EAPD BEEP# EC_MUTE# PCH_SPKR ALS_INT PWR_LED# BATT_AMB_LED# POUT BI BI_DET BI_GATE HDA_BITCLK_AUDIO 13 HDA_SYNC_AUDIO 13 HDA_SDIN0 13 HDA_RST_AUDIO# 13 HDA_SDOUT_AUDIO 13 I2C_1_SDA_SENSOR 30 I2C_1_SCL_SENSOR 30 EAPD 28 BEEP# 28 EC_MUTE# 28 PCH_SPKR 13 ALS_INT 30 PWR_LED# 28 BATT_AMB_LED# 28 POUT 28 SAGE 3G PVT BI 36 BI_DET 28 SAGE 3G PVT 52 54 C PANAS_AXK8L50124BG PANAS_AXK8L50124BG_50P-T CONN@ 2 +3VLP R348 10K_0402_5% 6 1 EC_RST# 28 D G 2 3 1 S D 5 G BI_GATE 1 4 S Q80A DMN66D0LDW-7_SOT363-6 Q80B DMN66D0LDW-7_SOT363-6 C346 0.1U_0402_16V4Z 2 B B SAGE 3G PVT +3VLP 2 SAGE 3G DVT R147 100K_0402_5% LID Switch ON/OFF 28 C13 0.1U_0402_16V4Z LID@ 4 U9 2 6 5 BAV70W_SOT323-3 1 OUTPUT GND S IC AH180WG-7 SC-59 3P SENSOR SW LID@ +3VS A Digital MIC +3VS_DMIC R658 0_0402_5% MIC2 1 2 6 1 GND 2 5 VDD DMIC_DATA 4 DATA LEFT/RIGHT 3 DMIC_CLK CLOCK GND XEMC@ 2 220P_0402_50V7K 1 C23 SPM0423HD4H-WB-2_6P 2 220P_0402_50V7K 1 C22 D6 3 1 1 1 SAGE 3G R10 ON/OFF BTN LID@ R13 47K_0402_5% 2 ON/OFF 1 3 2 2 2 ON/OFFBTN# 1 D21 VDD @ SW5 SMT1-05-A_4P 1 3 +3VALW 1 SW5 -Reserve for Debug 2 2 LID_SW# LID@ RB751V-40_SOD323-2 LID_SW# 28 C15 LID@ 10P_0402_50V8J +3VS_DMIC A XEMC@ XEMC@ 1 SCA00001W00 3 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2 D55 TVNST52302AB0_SOT523-3 2010/11/1 2011/11/1 Deciphered Date Title IO Board ( Audio / WIN / RST/ LED ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Thursday, March 14, 2013 Sheet 1 33 of 52 Rev 0.1 A B C D E +5VALW to +5VS +5VALW 1 2 XEMC@ 1 2 47P_0402_50V8J C731 XEMC@ 1 2 47P_0402_50V8J C728 XEMC@ 1 2 47P_0402_50V8J C732 XEMC@ 1 2 47P_0402_50V8J C729 XEMC@ 1 2 47P_0402_50V8J C733 XEMC@ 1 2 47P_0402_50V8J C737 XEMC@ 1 2 47P_0402_50V8J C734 XEMC@ 1 2 47P_0402_50V8J C738 XEMC@ 1 2 47P_0402_50V8J C736 XEMC@ 1 2 47P_0402_50V8J 2 +1.05VS_VCCPP 6 5VS_GATE 3 2 SUSP C499 .1U_0603_25V7K +5VS +5VALW Q19B DMN66D0LDW-7_SOT363-6 1 1 +3VS SAGE 3G For RF Requirement (Cross Moat) 2 D 5 G SUSP C726 S 20mil 1 0_0402_5% XEMC@ 1 2 47P_0402_50V8J 1 D +VSB R633 2 +3VALW C730 R440 470_0603_5% 10mil 2 1 R437 20K_0402_5% +3VS XEMC@ 1 2 47P_0402_50V8J 1 4 1 +5VS C725 +1.35V C469 1U_0603_10V6K 1 +3VALW C498 4.7U_0603_10V6K 1 1 2 C464 4.7U_0603_10V6K C472 4.7U_0603_10V6K 2 @ +5VS U22 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 G Rds=13.5mΩ(Typ) 16.5mΩ(Max) 4 S Q19A DMN66D0LDW-7_SOT363-6 +3VALW to +3VS +3VALW 2 2 39 SUSP SUSP 3 C463 .1U_0603_25V7K Q59A DMN66D0LDW-7_SOT363-6 3 1 Q25B DMN66D0LDW-7_SOT363-6 28,39,40,41 SUSP# 5 100K_8P4R_5% S 4 2 D G 4 6 S 2 G 28,39 SYSON D Q25A DMN66D0LDW-7_SOT363-6 2 1 2 3 4 S 1 G 5 SUSP 1 3VS_GATE 8 7 6 5 SUSP# SYSON# SUSP SYSON D 20mil 1 0_0402_5% +5VALW RP45 D 1 R635 2 R368 47K_0402_5% 2 SAGE 3G R436 470_0603_5% 6 4 10mil 2 +VSB 1 1 C458 1U_0402_6.3V6K 1 C461 4.7U_0603_6.3V6K 2 C459 4.7U_0603_6.3V6K 1 2 C460 4.7U_0603_6.3V6K @2 +3VS U21 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 G Rds=13.5mΩ(Typ) 16.5mΩ(Max) S 1 Q59B DMN66D0LDW-7_SOT363-6 +1.35V to +1.35VS 1 1 @ 2 2 R245 470_0603_5% 1 4 @ C338 1U_0402_6.3V6K 3 1 10K_0402_5% 1.35VS_GATE 1 SUSP +5VALW D S 2 G 2 Q15B DMN66D0LDW-7_SOT363-6 2 R449 100K_0402_5% 20 PCH_PWR_EN# @ Q21 2N7002KW_SOT323-3 28,31 PCH_PWR_EN 1 ACIN 3 4 28,37 ACIN C380 .1U_0603_25V7K 1 2 G S Q15A DMN66D0LDW-7_SOT363-6 1 1 3 D 5 2 S R268 510K_0402_5% SUSP 1 @ 1 R636 2 D 2 1 R269 33K_0402_5% +VSB 20mil 6 10mil D 3 1 SAGE 3G +1.35VS U12 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 C339 4.7U_0603_6.3V6K 3 2 C378 4.7U_0603_6.3V6K 1 C375 4.7U_0603_6.3V6K @2 +1.35V G Rds=2.6mΩ(Typ) 3.2mΩ(Max) S 2 G Q26 2N7002KW_SOT323-3 2 R450 100K_0402_5% S D S 2 1 1 Q23 2 SUSP G 2N7002KW_SOT323-3 4 R508 470_0603_5% D Q5 2 SUSP G 2N7002KW_SOT323-3 S 3 D 1 1 Q24 @ 2 SYSON# G 2N7002KW_SOT323-3 +1.8VS R29 470_0603_5% 3 3 S 1 2 D R366 22_0603_5% 3 1 1 @ R365 470_0603_5% +1.05VS_VTT 2 1 +0.675VS 2 +1.35V 4 Q34 2 SUSP G 2N7002KW_SOT323-3 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DC Interface Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 34 of 52 A B C D PL101 1 1 VIN 2 1 HCB2012KF-121T50_0805 CONN@ PJP101 2 PC102 100P_0603_50V8 1 PC103 100P_0603_50V8 2 1 1 PC101 1000P_0603_50V7K 2 HCB2012KF-121T50_0805 1 1 DC_IN_S1 2 1 2 3 4 5 6 7 2 1 2 3 4 5 GND1 GND2 PL102 PC104 1000P_0603_50V7K ACES_88266-05001 ADAPDET 37 2 2 3 +CHGRTC +RTCBATT_R @ PR101 0_0402_5% 1 2 PR102 560_0603_5% 1 2 3 +3VLP PR103 560_0603_5% 1 2 +RTCBATT 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title DCIN/PRECHARGE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: A B C Sheet D 35 of 52 A B C D PR202 @ 1 EC_SMDA EC_SMCA TH BI+ 1 1 2 4 PR215 1K_0402_1% 1 2 H_PROCHOT# BATT_TEMP 28 2 5 ~OT2 RHYST2 1 2 @ PQ202B DMN66D0LDW-7_SOT363-6 @ PH201 100K_0402_1%_NCP15WF104F03RC 2 4 S 風風 PH11 near PH2 near charger 2 PJ201 2 2 @ PR220 100K_0402_1% PR219 100K_0402_1% 2 38 MAINPWON D 2 PR218 21K_0402_1% 28 MAINPWON_L 1 @ PU202 1 2 2 MAINPWON 3 0_0402_5% 4 PR224 G VCC TMSNS1 GND RHYST1 ~OT1 TMSNS2 ~OT2 RHYST2 8 7 6 2 1 PR223 9.53K_0402_1% 5 3 1 G718TM1U_SOT23-8 2 PR226 39K_0402_1% S 3 S 此此此此此EC pin PR229 33K_0402_1% 2 PQ204 2N7002KW_SOT323-3 PC207 1000P_0402_50V7K 2 3 1 G PC208 1U_0402_6.3V6K For 45W adapter==>action 48W , Recovery 37W PH203 100K_0402_1%_NCP15WF104F03RC 2 1 1 D 2 2 38 SPOK PR228 1K_0402_5% 1 2 1 2 1 PR227 100K_0402_1% PR221 3.92K_0402_1% 2 1 28,5 H_PROCHOT# PQ203 2N7002KW_SOT323-3 1 PC204 0.1U_0603_25V7K 1 2 1 +VSBP 2 2 @ 1 PC206 .1U_0603_25V7K VL 2 PR225 22K_0402_1% 2 1 1 1 PR222 100K_0402_1% 3 PC205 0.22U_0603_25V7K 3 B+ 1 PQ201 TP0610K-T1-E3_SOT23-3 28,37 ADP_I 1 2 1 2 JUMP_43X39 2 PJ202 PH9 under CPU botten side : CPU thermal protection at 92 degree C 1 PR216 1 +3VLP +3VALW @ @ 1 2 +VSB 2 2 @ PR217 2 0_0402_5% 1 1 JUMP_43X39 0_0402_5% 1 2 @ 1 +VSBP 28 CHG_TEMP @ PR214 10.5K_0402_1% 5 G @ PR212 2 0_0402_5% 1 G718TM1U_SOT23-8 D BI 33 1 2 2 1 @ PR211 9.53K_0402_1% 6 ~OT1 TMSNS2 S +3VLP 7 GND RHYST1 3 G PR209 3.92K_0402_1% 8 PH202 100K_0402_1%_NCP15WF104F03RC 2 1 PC203 0.01U_0402_25V7K 2 6 PR213 6.49K_0402_1% 2 1 @ 2 @ PQ202A DMN66D0LDW-7_SOT363-6 @ PU201 VCC TMSNS1 1 PC201 1000P_0402_50V7K D +3VALWP 1 @ PR205 21K_0402_1% 3 2 PR207 1K_0402_5% 1 HCB2012KF-121T50_0805 2 1 2 BATT+ 2 @ PR210 6.49K_0402_1% 2 1 1 PL202 1 BATT_S1 @ EC_SMB_CK1 28,37 1 HCB2012KF-121T50_0805 1 @ PR208 100K_0402_1% H_PROCHOT# 2 EC_SMB_DA1 28,37 2 2 PR206 100K_0402_1% 1 2 PL201 1 1 1 PR201 100_0402_1% PR204 100_0402_1% PC202 .1U_0402_16V7K 1 2 3 4 5 6 7 8 9 10 2 1 1 2 3 4 5 6 7 8 GND1 GND2 PJP201 0_0402_5% 1 2 CONN@ ACES_88231-08001 @ PR203 2 0_0402_5% 1 +3VLP +3VALW 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: A B C Sheet D 36 of 52 A B C D 1 for reverse input protection D 2 3 G 1 2 1 PR301 1M_0402_5% 1 VIN S PQ301 2N7002KW_SOT323-3 2 PR302 3M_0402_5% 1 100ppm P1 PQ302 SIS412DN-T1-GE3_POWERPAK8-5 B+ PR303 0.02_1206_1% P2 PQ303 SIS412DN-T1-GE3_POWERPAK8-5 CHG_B+ PQ304 SIS412DN-T1-GE3_POWERPAK8-5 PJ301 1 1 2 1 PR305 0_0402_5% 2 1 1 PC319 0.01U_0402_50V7K 2 PC318 2200P_0402_50V7K PC315 10U_0805_25V6K 2 1 PC314 10U_0805_25V6K 2 1 2 RF@ PC328 0.1U_0402_25V6 1 PC317 0.1U_0402_25V6 2 1 CSON1 1 1 CSOP1 1 PR313 4.7_1206_5% 2 1 PC316 0.1U_0402_25V6 Typ 19.06V 2.65V Max. 22.66V 3.15 V ILIM and external DPM Min. 3.906A Typ Max. 3.966A 4.027A PC322 0.01U_0402_25V7K 1 ADP_I 28,36 @ PC325 0.1U_0402_16V7K 2 @ PR324 0_0402_5% Min. 17.26V 2.4V 1 1 PC324 100P_0402_50V8J PC308 0.01U_0402_50V7K 2 ILIM 1 2 1 2 VIN ACDET EC_SMB_CK1 28,36 2 PQ307 2N7002KW_SOT323-3 @ Vin Dectector EC_SMB_DA1 28,36 3 S @ 2 PR318 316K_0402_1% PR322 66.5K_0402_1% 2 3 1 PR325 100K_0402_5% 4 3 3 2 2 G 2 1 ACDET PC323 0.22U_0402_16V7K 2 1 2 PQ308 PDTC115EU_SOT323-3 1 1 D PR312 0.01_1206_1% 4 +3VLP PR320 422K_0402_1% 2 PR321 100K_0402_5% 2 PR323 100K_0402_5% 2 CSON1 PR315 6.8_0603_5% BQ24725_BATDRV 1 2 BATT+ +3VALW 2 6 VIN 1 VIN 1 VIN SRN 1 PR314 10_0603_5% 2 CSOP1 1 2 @ PR317 316K_0402_1% PR319 100K_0402_1% 28,34 ACIN 3 12 11 BATDRV SCL ACOK 9 5 SRN SRP 1 10 ACOK ACDRV SDA 2 PR316 100K_0402_1% SRP 8 1 +3VLP CMSRC IOUT 4 7 BQ24725_ACDRV 13 PC320 680P_0402_50V7K 14 GND ACDET 3 3 2 1 ACP BQ24725A_VQFN20_3P5X3P5 BQ24725_CMSRC 4 DL_CHG 2 15 LODRV 1 ACN PQ306 SIS412DN-T1-GE3_POWERPAK8-5 5 REGN 16 BTST HIDRV 17 18 19 20 VCC PAD 2 PC321 0.1U_0603_25V7K 2 PHASE 1 PL302 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2 CHG BQ24725_LX 2 3 2 1 PC313 1 2 RF@ PC327 68P_0402_50V8J 2 1 PQ305 SIS412DN-T1-GE3_POWERPAK8-5 1U_0603_25V6K PU301 2 5 1 PR310 2.2_0603_5% 1 PR311 2.2_0603_5% 2DH_CHG-1 4 DH_CHG 1 PD302 RB751V-40_SOD323-2 2 BQ24725_BST 2 DH_CHG BQ24725_LX 1U_0603_25V6K @ PR306 4.12K_0603_1% 2 1 1 BQ24725_BATDRV 1 PC310 0.047U_0402_25V7K 1 2 2 PC312 1 2 21 4 PC305 C305 0.1U_0402_25V6 2 1 2 2 3 @ @P 1 2 3 5 PD301 BAS40CW_SOT323-3 PR309 10_1206_1% 1 PC309 0.1U_0402_25V6 2 BQ24725_ACP 1 PC311 0.1U_0603_25V7K 2 BQ24725_ACN 2 PC306 2200P_0402_50V7K 2 1 2 VIN PC307 0.1U_0402_25V6 1 2 PR308 4.12K_0603_1% 1 PR307 4.12K_0603_1% 2 1 2 1 PC304 10U_0805_25V6K 2 1 1 JUMP_43X79 2 3 PC303 10U_0805_25V6K 4 2 1 1 RF@ PC326 68P_0402_50V8J 2 1 5 4 1 1 2 3 PC302 0.1U_0402_25V6 2 @ 2 1 4 PC301 2200P_0402_50V7K 2 1 PR304 0_0402_5% 1 2 3 5 4 Close EC Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 35 ADAPDET 2011/06/24 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CHARGER Rev 1.0 SAGE 3G Date: A B C Sheet D 37 of 52 5 4 3 2 1 PR402 499K_0402_1% 2 1 BS PC429 PR414 0.01U_0402_25V4Z 1K_0402_5% 1 2 1 2 FB_3V PR401 6 2 BST_3V_1 BST_3V 1 2.2_0603_5% PC402 1 2 0.1U_0603_25V7K OUT PG LDO 4 5*5*3 5 D +3VALWP NW00 1 GND 1 2 PL402 1UH_PCMB053T-1R0MS_7A_20% 1 2 LX_3V +3VLP SY8208BQNC_QFN10_3X3 PR404 4.7_1206_5% PC410 4.7U_0603_6.3V6K PC411 680P_0402_50V7K 2 1 2 36 SPOK 2 9 10 1 LX PC406 1U_0603_25V6K 2 1 ENM 3 PR403 150K_0402_1% 2 1 1 B+ PC409 22U_0805_6.3VAM EN2 PC408 22U_0805_6.3VAM 2 1 EN1 IN 2 IN PC407 22U_0805_6.3VAM 2 1 PC405 10U_0805_25V6K 2 1 PC404 10U_0805_25V6K 2 1 @ PC403 2200P_0402_50V7K 2 1 PC401 0.1U_0603_25V7K 2 1 D 8 RF@ PC424 68P_0402_50V8J 2 1 PU401 7 RF@ PC425 2200P_0402_50V7K 2 1 PL401 HCB2012KF-121T50_0805 1 2 RF@ PC426 0.1U_0603_25V7K 2 1 ENLDO_3V5V B+ C C B+ 5*5*3 NW00 PL404 1UH_PCMB053T-1R0MS_7A_20% 2 1 2 1 PR408 2.2K_0402_5% 1 2 28 EC_ON B @ PJ401 +3VALWP @ PD401 SBR2U30P1-7_POWERDI123-2 1 2 1 1 2 2 +3VALW JUMP_43X118 @ PJ402 @ PR409 2 0_0402_5% +5VALWP 1 1 2 2 +5VALW PC423 4.7U_0603_6.3V6K JUMP_43X118 1 2 1 @ PR411 402K_0402_1% 1 2 36 MAINPWON A PC420 22U_0805_6.3VAM PR406 4.7_1206_5% PC419 22U_0805_6.3VAM 2 1 VL 1 7 SY8208CQNC_QFN10_3X3 +5VALWP 2 LX_5V 4 PC418 22U_0805_6.3VAM 2 1 LDO 10 PC416 0.1U_0603_25V7K 2 BST_5V_1 1 RF@ PC427 68P_0402_50V8J 2 1 OUT PG PR405 2.2_0603_5% 1 2 2 @ PR407 2 0_0402_5% VCC BST_5V 1 B LX 6 PC421 4.7U_0603_6.3V6K 2 PC417 4.7U_0603_6.3V6K 1 2 GND 3 1 @ ENM PC422 680P_0402_50V7K BS 5 1 EN1 EN2 9 ENM IN 1 2 8 PC428 PR410 6800P_0402_25V7K 1K_0402_5% 1 2 1 2 FB_5V PU402 PC414 0.1U_0603_25V7K 2 1 PC413 2200P_0402_50V7K 2 1 PC415 10U_0805_25V6K 2 1 PC412 10U_0805_25V6K 2 1 PL403 HCB2012KF-121T50_0805 1 2 For EC use +3VALW, mark "@" if use +3VLP A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: 5 4 3 2 Sheet 1 38 of 52 A 4 +VTT_REFP 2 3 2 1 PC501 2200P_0402_50V7K 2 1 @ PC504 0.1U_0402_25V6 2 1 1 1 +1.35VP 5 1.5UH_MMD-06CZ-1R5M-V1_9A_20% PL502 PR503 4.7_1206_5% CS VDDP 1 4 LG_1.35V 14 13 PQ502 PR504 18.7K_0402_1% 2 1 2 PGND 15 2 2 PHASE OVP=110%~120% 2 1 LX_1.35V 16 UG_1.35V UGATE BST_1.35V 18 BOOT 17 2 LGATE VTTREF PC509 680P_0402_50V7K 1 + PC508 330U_D2_2V_Y 2 MDV1525URH_PDFN33-8-5 Rds=11.5mΩ(Typ) 14mΩ(Max) 12 11 2 1 PR505 5.1_0603_5% 1 +1.35VP +5VALW 1 PJ504 2 2 +1.35V JUMP_43X118 1 +3VALW 2 VDD 2 1 PR506 10K_0402_5% PC511 1U_0603_10V6K 2 1 PGOOD 10 TON 9 S5_1.35V 8 PR507 680K_0402_1% 2 S5 VDDQ S3 5 FB 2 PC510 0.033U_0402_16V7K PC512 1U_0603_10V6K @ @ 1 +0.675VSP PGOOD_1.35V 1 PJ506 2 2 +0.675VS JUMP_43X79 @ PR508 0_0402_5% 1 2 PR501 887K_0402_1% 2 1 1.35V_B+ 1 DDR3L@ PR509 4.64K_0402_1% 2 1 2 2 1 1 PC513 0.1U_0402_16V4Z @ PC514 0.1U_0402_16V7K 1 1 1.35VP D PR510 FB=0.75V To GND = 1.5V To VDD = 1.35V SUSP 2 G S3 S5 S0 Hi Hi On On S3 Lo Hi On On Lo Lo S PQ503 2N7002KW_SOT323-3 VTT_REFP 5.76K_0402_1% 2 34 SUSP S4/S5 prevent the switching too fast to short through RT8207MZQW_WQFN20_3X3 6 1 +1.35VP 28,34 SYSON STATE 1 @ 3 1 19 20 GND B+ 2 MDV1528URH_PDFN33-8-5 PR502 PC505 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_1.35V-1 1 2 VTTSNS S3_1.35V 7 1 28,34,40,41 SUSP# 1 2 3 VTTGND 2 PQ501 3 2 1 2 PAD VLDOIN 1 VTT PU501 21 PJ501 1 JUMP_43X118 4 1 1 1 2 2 1 2 PC507 10U_0805_25V6K PC506 10U_0805_25V6K 1 2 RF@ PC516 68P_0402_50V8J 2 1 靠靠Output Cap PAD 2 PJ503 @ JUMP_43X39 PC503 4.7U_0805_25V6-K 1 PJ507 @ JUMP_43X39 PC502 4.7U_0805_25V6-K +1.35VP 5 +1.35VS 2012/08/01 +0.675VSP @ 1 1.35V_B+ RF@ PC515 68P_0402_50V8J Ipeak=12.2A ; Imax=8.54A ;Iocp=14.64A Delta I=3.23=>1/2Delta I=1.62A (F=285K Hz) Rds(on)=14m ohm(max) ; Rds(on)=11.5m ohm(typical) Ilimit_min=(18.7K*10uA)/(14m)=13.36A Ilimit_max=(18.7K*10uA)/(11.5m)=16.26A Iocp=Ilimit+1/2Delta I =14.97~17.88A 0.675VSP On Off (Hi-Z) Off Off Off (Discharge) (Discharge) (Discharge) Note: S3 - sleep ; S5 - power off Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title 1.5VP/0.75VSP/1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: A Sheet 39 of 52 5 4 3 2 1 D D PR602 330K_0402_1% 2 1 B+ PL602 0.68UH_PCMC063T-R68MN_15.5A_20% 1 2 1 2 1 2 PC612 22U_0805_6.3V6M 1 2 PC611 22U_0805_6.3V6M 1 2 PC610 22U_0805_6.3V6M 1 2 PC609 22U_0805_6.3V6M 1 1 2 PR605 4.7_0805_5% PC608 22U_0805_6.3V6M 1 1 +3VALW 5 SY8208DQNC_QFN10_3X3 PR608 10K_0402_1% 2 1 PC622 .1U_0402_16V7K PC607 22U_0805_6.3V6M LDO FB_+1.05VSP 7 2 PG 4 C @ PC614 680P_0402_50V7K @ PJ601 +1.05VS_VCCPP 1 BYP 1 2 2 ILMT +1.05VS_VCCPP 5K80 2 1 SW_+1.05VSP 2 @ PC613 0.1U_0402_16V7K 2 1 RF@ PC620 2200P_0402_50V7K BST_+1.05VSP 10 7*7*3 FB PR606 1M_0402_1% 6 PR601 PC601 0_0603_5% 0.1U_0603_25V7K 1 2 1 2 RF@ PC618 68P_0402_50V8J 2 1 LX EN_+1.05VSP 2 GND 1 PC616 4.7U_0603_6.3V6K PC606 10U_0805_25V6K 2 1 PC605 10U_0805_25V6K 2 1 EN PC615 4.7U_0603_6.3V6K 2 1 +3VS PC604 2200P_0402_50V7K 2 1 @ PC603 0.1U_0402_25V6 2 1 RF@ PC621 68P_0402_50V8J 2 1 1 2 C IN BS 9 3 RF@ PC619 68P_0402_50V8J 2 1 1 2 @ PR604 10K_0402_1% @ PC602 0.1U_0402_16V7K 1 2 PU601 8 VFB=0.6V 1 1 2 2 +1.05VS_VTT JUMP_43X118 PR607 1 PL601 HCB2012KF-121T50_0805 1 2 +3VS SUSP# 28,34,39,41 @ PR603 1M_0402_1% 1 2 PC617 220P_0402_50V8J 2 2 100K_0402_1% 1 41 VCCPPWRGOOD 2 PR609 133K_0402_1% B PC623 PR610 @ 1000P_0402_50V7K @ 1.2K_0402_1% 2 1 2 1 B PR611 100_0402_1% 1 2 VCCIO_SENSE 8 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title 1.05VS_VTTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: 5 4 3 2 Sheet 1 40 of 52 5 4 3 2 1 +VCCSA_PWRGD 1 40 VCCPPWRGOOD 7 2 8 PC711 1U_0603_6.3V6M 1 2 @ PR704 0_0402_5% POK D1 VEN/MODE D0 4 2 3 @ PR703 0_0402_5% 2 1 2 1 1 2 G978F11U_SO8 @ PR705 0_0402_5% 1 H_VCCSA_VID1 9 H_VCCSA_VID0 9 @ PR706 1K_0402_5% 2 0.9V RF@ PC726 68P_0402_50V8J 2 1 Vo PC710 22U_0805_6.3V6M 1 2 Vo VPP PC709 2200P_0402_50V7K 2 1 1 +5VALW VIN PC712 1U_0603_6.3V6M 1 2 2 6 PC708 22U_0805_6.3V6M 1 2 5 15,28 SA_PGOOD PR702 1K_0402_5% GND PC707 22U_0805_6.3V6M 1 2 PU701 +3VS D +VCCSAP 9 PR701 100K_0402_5% VCCSA Vout 0.9V 0.85V 0.775V 0.75V output voltage adjustable network PC706 0.1U_0402_16V7K 2 1 1 VID[1] 0 1 0 1 PC704 22U_0805_6.3V6M 2 1 2 PC705 22U_0805_6.3V6M 1 2 +1.05VS_VTT @ PC703 0.1U_0603_25V7K 1 2 PC702 2200P_0402_50V7K D PC701 22U_0805_6.3V6M 2 1 RF@ PC725 68P_0402_50V8J 1 2 VID [0] 0 0 1 1 @ PJ701 1 1 1 2 2 JUMP_43X39 @ PJ705 +VCCSAP 1 1 2 +VCCSA 2 JUMP_43X39 C C +3VS @ PR707 0_0402_5% 2 2 PR716 10K_0402_1% 2 +1.5VSP_ON 1 2 1 PC718 22U_0805_6.3V6M 2 1 @ FB_1.5VSP @ PR714 22K_0402_5% PC721 0.1U_0402_16V7K B PR715 22.6K_0402_1% 2 2 Rdown PC717 22U_0805_6.3V6M PR710 20K_0402_1% FB=0.8V 2 1 2 2 GND FB +1.5VSP RF@ PC727 68P_0402_50V8J 1 3 4 2 2 Note:Iload(max)=3A PC724 680P_0402_50V7K FB=0.6V 1 1 FB_1.8V EN POK PR711 1_0402_1% 28,34,39,40 SUSP# VOUT VOUT PC716 0.022U_0402_16V7K 2 1 Rup 8 7 VCNTL VIN VIN 1 PR713 20K_0402_1% PC715 4.7U_0603_6.3V6K 1 +1.8VSP 2 2 SY8003DFC_DFN8_2X2 2 1 5 1 1 NC LX_1.8V 2 PGND 6 1 LX RF@ PC728 68P_0402_50V8J EN IN PC723 22U_0805_6.3VAM 2 1 4 2 JUMP_43X79PC719 22U_0805_6.3VAM PG 1 3 2 2 PU702 APL5930KAI-TRG_SO8 6 5 9 PC722 22U_0805_6.3VAM 2 1 2 @ PC713 1U_0402_6.3V6K Note:Iload(max)=3A PL701 1UH_PH041H-1R0MS_3.8A_20% PC720 68P_0402_50V8J 2 1 1 Note:Iload(max)=2.5A 1 1 7 PR709 1M_0402_5% 2 +3VALW 1 B FB PR712 4.7_0603_5% 2 @ PJ702 PGND SGND 1 1 9 8 SUSP# 1 0.1U_0402_16V7K @ PC714 2 1 PU703 2 1 1 +1.8VSP_ON Vout=0.6V* (1+Rup/Rdown) @ +1.8VSP 1 1 Ien=10uA, Vth=0.3V, notice the res. and pull high voltage from HW PJ704 2 2 +1.8VS JUMP_43X79 @ PJ703 1 +1.5VSP 1 2 2 +1.5VS JUMP_43X39 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title VCC_SAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: 5 4 3 2 Sheet 1 41 of 52 4 3 @ PC802 1000P_0402_50V7K 1 22 19 LGATE1 18 PHASE1 17 UGATE1 2 20 1 PR822 1_0603_5% 1 +3VS 8 VCCSENSE 8 VSSSENSE 2 2 1 @ PR847 10_0402_1% 1 PR816 1_0402_5% 1 1 2 3 2 1 56via PR843 1_0402_5% 3.65K_0603_1% PR842 VSUM- 4 2 PC834 0.22U_0603_16V7K LGATE1 VSUM- +CPU_CORE SAGE 3G VSUM+ 2 B PL804 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 2 PC836 680P_0402_50V7K 2 1 2 1 PR841 4.7_1206_5% PR840 2.2_0603_5% 1 1 BOOT1 2 B+ PC827 2200P_0402_50V7K 2 1 2 @ PC826 0.1U_0402_25V6 2 1 + RF@ PC845 68P_0402_50V8J 2 1 PC841 33U_D2_25VM_R60M PC823 10U_0805_25V6K 2 1 4 PC822 10U_0805_25V6K 2 1 2UGATE1-1 PQ803 MDV1525URH_PDFN33-8-5 5 1 3 2 1 1 UGATE1 1 PHASE1 PC837 0.1U_0402_16V7K @ PC838 330P_0402_50V7K 2 1 PH804 2.61K_0402_1% 10K_0402_1%_ERTJ0EG103FA PR835 2 1 2 1 11K_0402_1% 2 PR838 PC833 0.1U_0603_25V7K @ PC829 0.01UF_0402_25V7K 1 2 1 2 2 2 A 2 1 @ PR846 10_0402_1% PC839 330P_0402_50V7K 2 1 +CPU_CORE PR832 0_0603_5% Close Phase 1 choke 1 PC835 150P_0402_50V8J 2 1 2 1 PR845 130K_0402_1% PR836 511_0402_1% 2 PC832 56P_0402_50V8 2 1 PC831 6800P_0402_25V7K PR834 42.2K_0402_1% 2 1 PL802 HCB2012KF-121T50_0805 1 2 CPU_B+ PQ804 MDU1511RH_POWERDFN56-8-5 1.91K_0402_1% 1 1 PR844 1.91K_0402_1% 2 1 PC814 10U_0805_25V6K 2 1 PL801 HCB2012KF-121T50_0805 1 2 For17 W 1+1 CPU_CORE LL= -2.9mΩ, OCP ~40A GFX_CORE LL= -3.9mΩ, OCP ~34A 1 1 PR837 499_0402_1% 1 BOOT1 PR831 2 +5VS PR839 649_0402_1% 2 1 PC830 470P_0402_50V7K 2 1 2 2 2 VSUM+ PR833 2K_0402_1% 2 1 VSUMG+ 1 +5VS 21 VGATE 15 B PC828 470P_0402_50V7K 2 1 C PC819 1U_0603_10V6K BOOT1 UGATE1 23 +VGFX_CORE OVP=VID +(120mV~ 200mV) 16 15 @ PR829 0_0402_5% 14 ISEN2 PGOOD PHASE1 COMP NTC FB LGATE1 42via PC817 1U_0603_10V6K 2 1 PW M2 VR_HOT# 3 2 1 25 27 28 29 30 31 32 33 26 BOOTG PGOODG COMPG FBG RTNG ISUMNG UGATEG VDD ISL95833HRTZ-T_TQFN32_4X4 SDA 2 8 ALERT# 24 5 2 1 1 PR828 3.83K_0402_1% 1 2 2 @ PC820 0.1U_0402_16V7K 7 PR830 27.4K_0402_1% 2 PR824 0_0402_5% 1 2 PR825 130_0402_1% 1 2 PR826 75_0402_5% 1 2 PR827 54.9_0402_1% 1 6 @ +1.05VS_VTT 5 SDA @ PR823 0_0402_5% 28 VR_HOT# VCCP 13 4 LGATEG SCLK RTN ALERT# VR_ON 12 3 2 @ PR821 0_0402_5% 1 2 @ PC818 47P_0402_50V8J PAD 2 SCLK ISUMN 0_0402_5% 0_0402_5% 11 @ Rds(on)=2.7m-3.3m ohm LGATEG PHASEG ISUMP PR818 2 @ PR820 PHASEG NTCG 10 2 1 PH803 470K_0402_5%_ TSM0B474J4702RE 2 1 2 1 8 VR_SVID_DAT 1 1 1 NTCG ISEN1 28,5 VR_ON 8 VR_SVID_CLK 8 VR_SVID_ALRT# PR819 3.83K_0402_1% 1 2 9 PH802 470K_0402_5%_ TSM0B474J4702RE 2 1 C ISUMPG PU801 SAGE 3G PC816 680P_0402_50V7K 2 1 2 4 LGATEG PQ802 MDU1511RH_POWERDFN56-8-5 PR813 2.2_0603_5% UGATEG1 1 PR814 4.7_1206_5% PC815 0.22U_0603_16V7K 1 1 2 2 BOOTG 2 3 2 1 BOOTG PR817 27.4K_0402_1% 2 1 PL803 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 2 PHASEG VSUMG- 4 UGATEG1-1 PC813 10U_0805_25V6K 2 1 PR811 0_0603_5% 1 2 UGATEG1 2 1 PR812 1.91K_0402_1% +3VS PR807 1.65K_0402_1% PR810= 24.9 Kohm==>Freq= 400KHz 2 1 PR810 24.9K_0402_1% PC809 0.01UF_0402_25V7K 1 2 @ PC812 1000P_0402_50V7K 2 1 PC808 0.1U_0603_25V7K 1 2 1 PR808 280_0402_1% D CPU_B+ 1 PR815 3.65K_0603_1% 2 VSUMG+ PR809 11K_0402_1% 1 2 PR801 2.61K_0402_1% 1 2 1 1 2 PC801 0.1U_0402_16V7K 2 2 RF@ PC843 2200P_0402_50V7K 2 1 PC807 150P_0402_50V8J 1 2 1 PR805 137K_0402_1% 2 RF@ PC844 68P_0402_50V8J 2 1 PC806 PR806 2200P_0402_50V7K 649_0402_1% 1 2 1 2 VSUMG- PC805 470P_0402_50V7K 2 1 2 1 PR804 499_0402_1% 5 PH801 10K_0402_1%_ERTJ0EG103FA PC804 68P_0402_50V8J 2 1 PQ801 MDV1525URH_PDFN33-8-5 @ PR803 10_0402_1% D For ULV 17W 1+1 CPU_CORE LL= -2.9mΩ,Iocp_cpu=39.6A GFX_CORE LL= -4.6mΩ,Iocp_gfx=21.6A RF@ PC842 0.1U_0402_25V6 2 1 PC803 0.01UF_0402_25V7K 1 5 2 1 10_0402_1% 2 2 @ PR802 9 VCC_AXG_SENSE 9 VSS_AXG_SENSE 1 1 2 +VGFX_CORE 2 1 5 A @ PC840 0.01UF_0402_25V7K Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title CPU_CORE/VGFX_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 SAGE 3G Date: 5 4 3 2 Sheet 1 42 of 52 Compal Secret Data Date of EOP 2 1 1 1 1 PC994 10U_0603_6.3V6M 2 PC993 10U_0603_6.3V6M 2 PC992 10U_0603_6.3V6M 2 PC991 10U_0603_6.3V6M PC990 10U_0603_6.3V6M 2 1 2 PC995 330U_D2_2V_Y 1 1 1 1 1 PC989 10U_0603_6.3V6M 2 PC988 10U_0603_6.3V6M 2 PC987 10U_0603_6.3V6M 2 PC986 10U_0603_6.3V6M 2 PC985 10U_0603_6.3V6M 2 PC956 1U_0402_6.3V6K 2 1 PC957 1U_0402_6.3V6K 2 1 PC958 1U_0402_6.3V6K 2 1 PC959 1U_0402_6.3V6K 2 1 PC960 1U_0402_6.3V6K 2 1 PC961 1U_0402_6.3V6K 2 1 PC962 1U_0402_6.3V6K 2 1 PC963 1U_0402_6.3V6K 2 1 PC964 1U_0402_6.3V6K 2 1 PC965 1U_0402_6.3V6K 2 1 PC966 1U_0402_6.3V6K 2 1 PC967 1U_0402_6.3V6K 2 1 PC968 1U_0402_6.3V6K PC972 1U_0402_6.3V6K 2 1 PC973 1U_0402_6.3V6K 2 1 PC974 1U_0402_6.3V6K 2 1 PC975 1U_0402_6.3V6K 2 1 PC976 1U_0402_6.3V6K 2 1 PC977 1U_0402_6.3V6K 2 1 PC978 1U_0402_6.3V6K 2 1 PC979 1U_0402_6.3V6K 2 1 PC980 1U_0402_6.3V6K 2 1 PC981 1U_0402_6.3V6K 2 1 PC982 1U_0402_6.3V6K 2 1 PC983 1U_0402_6.3V6K 2 1 PC984 1U_0402_6.3V6K PC969 330U_D2_2V_Y PC970 330U_D2_2V_Y PC971 330U_D2_2V_Y PC941 330U_D2_2V_Y PC942 330U_D2_2V_Y PC943 22U_0805_6.3V6M PC944 22U_0805_6.3V6M PC945 22U_0805_6.3V6M PC946 22U_0805_6.3V6M PC947 22U_0805_6.3V6M PC948 22U_0805_6.3V6M 2 1 1 1 1 1 1 2 PC933 10U_0603_6.3V6M 2 PC932 10U_0603_6.3V6M 2 PC931 10U_0603_6.3V6M 2 PC930 10U_0603_6.3V6M 2 PC929 10U_0603_6.3V6M 2 PC928 10U_0603_6.3V6M 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 PC927 2.2U_0402_6.3V6M 3 Deciphered Date 2 1 1 1 1 1 1 2 PC919 1U_0402_6.3V6K 2 PC918 1U_0402_6.3V6K 2 PC917 1U_0402_6.3V6K 2 PC916 1U_0402_6.3V6K 2 PC915 1U_0402_6.3V6K 2 PC914 1U_0402_6.3V6K PC913 1U_0402_6.3V6K 2 1 PC912 1U_0402_6.3V6K 2 1 PC911 1U_0402_6.3V6K 2 1 PC910 1U_0402_6.3V6K 2 1 PC901 1U_0402_6.3V6K 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 PC909 2.2U_0402_6.3V6M 2011/06/24 + 2 PC955 22U_0805_6.3V6M Issued Date 1 1 PC940 22U_0805_6.3V6M Security Classification 2 + 2 2 PC926 2.2U_0402_6.3V6M ESR=9m ohm 1 1 PC954 22U_0805_6.3V6M + + 2 PC953 22U_0805_6.3V6M 2 1 2 PC952 22U_0805_6.3V6M motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed PC951 22U_0805_6.3V6M ‧ VAXG can be left floating in a common 2 1 2 PC939 22U_0805_6.3V6M ‧ Can connect to GND if motherboard only 2 1 2 PC938 22U_0805_6.3V6M 2 1 2 PC937 22U_0805_6.3V6M Vaxg 1 PC936 22U_0805_6.3V6M 1 1 2 1 PC908 2.2U_0402_6.3V6M 2 2 PC950 22U_0805_6.3V6M 4 2 2 PC925 2.2U_0402_6.3V6M 2 1 1 PC907 2.2U_0402_6.3V6M 2 1 PC924 2.2U_0402_6.3V6M 2 1 1 PC906 2.2U_0402_6.3V6M 2 1 PC935 22U_0805_6.3V6M 5 2 1 PC923 2.2U_0402_6.3V6M 2 1 1 PC905 2.2U_0402_6.3V6M ESR=9m ohm + 1 PC922 2.2U_0402_6.3V6M C 1 3 PC904 2.2U_0402_6.3V6M + PC921 2.2U_0402_6.3V6M 1 1 PC903 2.2U_0402_6.3V6M 1 PC949 22U_0805_6.3V6M 1 D PC934 22U_0805_6.3V6M 2 PWR Rule 17W@ULV(CR BGA1023_GT2) CPU2.9m GFx3.9m CPU 330uF/9m *3, 22uF(0805) *12, 2.2uF(0402)*16 GFX 330uF/9m*2, 22uF(0805)*6, 10uF(0603)*6, 1uF(0402)*11 1.05V 330uF*2,10uF(0603)*10,1uF(0402)*26 PC920 2.2U_0402_6.3V6M B 1 +VGFX_CORE 4 PC902 2.2U_0402_6.3V6M 2 5 2 1 +CPU_CORE For BOT side @ A Title Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SAGE 3G CPU_CORE_CAP Rev 1.0 Date: 1 Sheet 43 of 52 D +CPU_CORE @ For TOP side C supports external graphics and if GFX VR is not stuffed in a common motherboard design, +1.05VS_VTT +CPU_CORE 2 B ESR=9m ohm A 3 2 SW 0.1U_0603_50V7K PC1403 2 1 2.2U_1206_50V7K @ PC1402 2 1 2.2U_1206_50V7K PC1408 2 1 VOUT 2.2U_1206_50V7K PR1401 1 1 2 +LG_VOUT 1 D 2 PC1401 S CER CAP 220P 50V J NPO 0603 PC1406 2 1 2 13 IFB5 14 15 FAULT IFB4 SW DCTRL 12 11 FB4 22 C DCTRL TPS61181ARTER_QFN16_3X3 9 FB3 22 8 CIN 6 62K_0402_1% PC1414 2 1 PR1409 2 B 10 IFB2 IFB3 IFB1 VO 7 4 1 100P_0402_50V8J 1 @ PC1412 2 PC1411 2 1 1U_0805_50V7K VOUT GND ISET 100P_0402_50V8J @ PC1410 2 1 1 2 PR1408 VBAT 0.1U_0402_10V7K 3 EN 1M_0402_1% 10K_0402_1% PGND 5 PR1407 2 2 EN 16 17 TPAD 1 1 SW EN 1 PU1401 C 28 BKOFF# 2.2U_1206_50V7K 1 2 LL4148_LL34-2 2 2 2 1 PC1409 2 1 2 PR1406 100P_0402_50V8J DCTRL 1 10K_0402_1% PR1405 51_1206_5% PR1404 2 1M_0402_1% 1 16 INVTPWM PD1401 PR1403 0_0603_5% 2 PR1402 1 100K_0402_5% PC1405 100P_0402_50V8J 2 1 1 2 0.1U_0603_50V7K PC1404 1 G D PD1402 SBR3U40P1-7_POWERDI123-2 4.7UH_PCMC063T-4R7MN_5.5A_20% PL1401 1 2 D S 3 B+ 1 PC1407 2 1 PQ1401 P5103EMG_SOT23-3 10_1206_1% 4 IFB6 5 FB2 22 B FB1 22 @ PJ1401 GND 1 2 GND_SIGNAL PAD-OPEN1x1m A A Compal Secret Data Security Classification Issued Date 2011/06/13 Deciphered Date 2012/06/13 Title Compal Electronics, Inc. LED Converter THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Wednesday, March 13, 2013 Date: Rev 0.1 SAGE 3G 5 4 3 2 Sheet 1 44 of 52 5 4 3 2 Version change list (P.I.R. List) Item Fixed Issue Reason for change Rev. PG# Modify List Design Change. Design Change of IC Application. 0.2 38 Add Add Add Add Design Change. Design Change of IC Application. 0.2 44 35 Add Adapter Detection Circuit. Design Change of DC Jack Application. 4 Design Change. Design Change of IC Application. 0.2 42 5 Change Component Part Number. Factory lack of material. 0.2 44 6 Change Component Part Number. Factory lack of material. 0.2 Change Component Part Number. X1 Code. 8 Design Change. 9 1 1 Page 1of 2 for PWR Date @PR410.@PR414 to SD028100180(S RES 1/16W 1K +-5% 0402) @PC429 to SE075472K80(S CER CAP 4700P 25V K X7R 0402) @PC428 to SE075472K80(S CER CAP 0.047U 25V K X7R 0402) PR412.@PR413.PR415 to SD028000080(S RES 1/16W 0 +-5% 0402) Phase 2012/12/13 DVT Delete PC1413. 2012/12/13 DVT Add Add Add Add 2012/12/13 DVT 2012/12/24 DVT Change PL1401 to SH000006J80 (S COIL 4.7UH +-20% PCMC063T-4R7MN 5.5A) 2012/12/24 DVT 42 Change PC841 to SGA00007I00 (S POLY C 33U 25V M D2 ESR60M TQC H1.9) 2012/12/26 DVT 0.2 44 Change PD1402 to SCS00005Y00 (S SCH DIO SBR3U40P1-7 POWERDI123-2) 2012/12/26 DVT Design Change of IC Application. 0.3 38 Delete PR412.PR413.PR415. 2012/01/29 PVT Design Change. Design Change of IC Application. 0.3 38 Change @PR410.@PR414.@PC428.@PC429 to PR410.PR414.PC428.PC429. 2012/01/29 PVT 10 Design Change. Design Change of IC Application. 0.3 38 Change PC428 to SE075682K80(S CER CAP 6800P 25V K X7R 0402) Change PC429 to SE072103Z80(S CER CAP .01U 25V Z Y5V 0402) 2013/02/22 PVT 11 Design Change. Design Change of Adapter Detection. 0.4 37 Change PQ307 to SB000009Q80(S TR 2N7002KW 1N SOT323-3) Add PR325 to SD028100380(S RES 1/16W 100K +-5% 0402) 2013/02/23 Pre MP D 2 3 0.2 37 PR325 to SD028000080(S RES 1/16W 0 +-5% 0402) PR321.PR323 to SD028100380(S RES 1/16W 100K +-5% 0402) PQ307 to SB201440000(S TR PDTA144EU PNP SOT323) PQ308 to SB301150200(S TR PDTC115EU NPN SOT323) Change PC831 to SE075682K80(S CER CAP 6800P 25V K X7R 0402) Change PC832 to SE071560J80(S CER CAP 56P 50V J NPO 0402) D C C 7 B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PIR (PWR) Rev 1.0 EG51_HX M/B LA-9491P Schematics Date: 5 4 3 2 Sheet 1 45 of 52 5 4 3 VIN = B+ QFN10 +5VALW D Page 38 SUSP# LDO = +3VLP VIN = B+ (+VCCDSW3_3 = +3VLP) EC_ON QFN10 SYSON Page 38 WQFN20 ADAPTER +3VALW SUSP# PU703 SY8003DFC_2X2 DFN8 +1.35V PU601 SY8208DQNC_3X3 SUSP# +1.05VS_VCCP (+1.05VS_VTT) (+1.05VS_PCH) (VCCPPWRGOOD) C QFN10 BATTERY Page 40 VIN = B+ PU701 G978F11U TQFN32 SO8 QFN16 C SUSP Page 34 Q68 AP2301GN-HF POWERPAK8-5 Page 34 SOT23-3 +3VS +LG_VOUT (+INVPWR_B+) Page 44 PCH_PWR_EN# U21 SI7716ADN-T1-GE3 +1.35VS PU1401 TPS61181ARTER_3X3 BKOFF# +3VALW POWERPAK8-5 VIN = +5VS CHARGER Page 41 U12 SI7716ADN-T1-GE3 +CPU_CORE (VGATE) +VGFX_CORE Page 42 +VCCSA (SA_PGOOD) VIN = +1.05VS_VTT VCCPPWRGOOD SUSP PU801 ISL95833HRTZ-T_4X4 VR_ON +1.8VS Page 41 VIN = +3VALW +0.675VS Page 39 VIN = +5VALW B+ +1.5VS Page 41 VIN = +3VS PU501 RT8207MZQW_3X3 SUSP# PU702 APL5930KAI-TRG SO8 PU401 SY8208BQNC_3X3 MAINPWON (VIN) 1 LDO = VL PU402 SY8208CQNC_3X3 D 2 LED & LID +VCCSUS3_3 HUB_PWRGATE @SENSOR +3VALW (LED & LID) Page 33 VIN = B+ Page 20 +3V_SEN Page 30 AUDIO CODEC AOAC_ON @WIFI +3VS_WLAN B Page 24 +5VALW SUSP USB_EN# +3VS_WWAN Page 31 U22 SI7716ADN-T1-GE3 U17 AP2301MPG-13 Q64 AP2301GN-HF POWERPAK8-5 Page 34 MSO8 SOT23-3 +5VS +USB3_VCCA B +3VS (CAMERA) Page 27,33 TPM +3V_TPM Page 26 PCH_PWR_EN# Page 27 +3VS (MIC)Page 33 CAMERA mSATA +3VS_FULL Page 25 Page 20 PCH_ENVDD @LCD +LCDVDD Page 22 +V5REF_SUS AUDIO CODEC JIO1 (Audio) Page 33 +3VS_WWAN Page 31 WIFI (w/o IOAC) FAN A A +3VS_WLAN Page 24 +5VS (FAN) Page 29 EC HDMI +HDMI_5V_OUT Page 23 +3VS_CARD Page 32 +3VLP +3VALW_EC Page 28 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title POWER TREE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Wednesday, March 13, 2013 Sheet 1 46 of 52 Rev 0.1 5 4 AC DC Adapter IN Battery_IN 3 2 EC_ON (S5 enable) EC_ON (S5 enable) -8 -8 +3VALWP EN +5VALWP EN -7 LX D 3V BATT+ -3 -11 Switch MosFET LDO Charger VIN Switch MosFET B+ PGOOD +3VLP 1 GPE0 SPOK VIN ON/OFF GPE4 PWR BTN GPB7 C GPI7 DPWROK -6 PCH_RSMRST# -1 VR_ON 9 10 GPJ3 GPD5 DRAMPWROK SLP_SUS# GPF1 GPE1 GPD0 GPE2 GPD1 GPJ1 SYSON 5 SUSP# 6 PM_DRAM_PWRGD PLTRST# KBC VO PWRBTN# -4 PBTN_OUT# 2 +V5REF_SUS PLT_RST# 17 SLP_S4# KBC VO BUF_CPU_RST# RESET# B+ +5VS +5VALW 7 +VSB VI EN KBC VO +5VS 10 3 VDD/VCCP VR_ON VR_ON KBC 14 SUSP 4 7 5 SYSON 6 SUSP# EN_S5 KBC PHASE EN_S3 +VSB VTT 7 VLDOIN SUSP# EN KBC 6 +VSB SUSP# VCCPPWRGOOD 8 VI EN KBC KBC VO VI EN KBC VO VCCPPWRGOOD VI EN KBC VO PGOOD VI EN 15 B +1.35VS +1.5VS +1.05VS_VTT 8 +3VALW SUSP# VGATE +3VS SW PGOOD A 6 VO +3VS +1.05VS_VCCP (+1.05VS_VTT) (+1.05VS_PCH) 6 KBC +VGFX_CORE SUSP -2 -2 PHASEG +CPU_CORE +1.35V +1.35V +0.675VS SVID PHASE1 PGOOD VI EN SUSP VDD/VDDP SVID_CLK/DATA/ALERT# +3VALW +1.35V +VCCSUS3_3 Buffer Y SLP_S3# +3VALW VI UNCOREPWRGOOD CPU P A B+ EN C 13 SVID +5VALW VI SM_DRAMPWROK +3VS +5VALW EN PM_DRAM_PWRGD_R A H_CPUPWRGD B+ PCH_PWR_EN# 12 AND Gate Y NC B -3 P B PWROK PCH_PWR_EN PM_SLP_S3# 16 PCH APWROK GPH0 PM_SLP_S4# +3VALW PROCPWRGD 11 PCH_PWROK AND Gate A Y SYS_PWROK RSMRST# SLP_SUS# -9 -1 PGOOD SYS_PWROK KBC SA_PGOOD LDO P DPWROK -5 VL +3VS -10 -2 B GPG2 5V -9 -1 EC_ON VCC D SW2 -8 +3VLP -7 LX SW2 VIN 1 VO +VCCSA A SA_PGOOD 9 +1.8VS Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title POWER TREE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Wednesday, March 13, 2013 Sheet 1 47 of 52 Rev 0.1 A B C V1JV1 CLOCK MAP D XTAL 32.768K Hz E XTAL 25M Hz 1 1 RTCX1 RTCX2 WLAN MD222 CLK_PCIE_MINI1 CLK_PCIE_MINI1# 100MHz XTAL25_IN XTAL25_OUT CLKOUT_DP_P CLKOUT_DP_N CLKOUT_PCIE1P CLKOUT_PCIE1N CLKOUT_DMI_P CLKOUT_DMI_N Card Reader RTS5209 CLK_PCIE_CARD CLK_PCIE_CARD# 100MHz 120MHz CLK_CPU_DPLL CLK_CPU_DPLL# 100MHz CLK_CPU_DMI CLK_CPU_DMI# 33MHz CLK_PCI0 Panther Point-M CLKOUT_PCI0 HDA_BITCLK_AUDIO PCH HDA_BITCLK_PCH 24MHz CLKOUT_PCI2 PCH_SPI_CLK_0 33 Ohm PCH_SPI_CLK 33MHz CLK_PCI2 33MHz CLK_PCI1 2 22 Ohm TPM SLB9655 CLK_PCI_TXM CLKOUT_PCIE7P CLKOUT_PCIE7N CLKOUT_PCI1 2MB SPI ROM 22 Ohm CLK_PCI_LPBACK CLKIN_PCILOOPBACK 33 Ohm Ivy Bridge Intel CLKOUT_PCIE4P CLKOUT_PCIE4N 2 Audio Codec AL271X CPU 22 Ohm CLK_PCI_LPC SPI_CLK 33 Ohm 3 3 PCH_SPI_CLK_1 LPCCLK HSCK CLK_PCI_LPC EC IT8518 4MB SPI ROM EC_SPICLK XTAL 32.768K Hz CK32K CK32KE FSCK 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title CLOCK MAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 48 of 52 Rev 0.1 A B C D E SMBUS Block Diagram 1 1 +3VS SDVO_SCLK SDVO_SDATA HDMI_SCLK HDMI_SDATA HDMI Connector I2C_SCL_GYRO I2C_SDA_GYRO +VCCSUS3_3 Intel Panther Point-M PCH 2 I2C_1_SCL_SENSOR I2C_1_SDA_SENSOR ST Sensor HUB PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA I2C_SCL_ACCEL I2C_SDA_ACCEL I2C_SCL_ALS I2C_SDA_ALS (USB interface) +3VS PCH_SML1CLK PCH_SML1DATA ST Gyroscope ST G-sensor+E-compass Capella Light sensor 2 EC_SMB_CK2 EC_SMB_DA2 DDR Thermal sensor +3VS +3VS_LC EC_SMB_CK2 EC_SMB_DA2 ThunderBolt +3VALW_EC EC ITE 8518 3 TB_SMB_CK TB_SMB_DA Cactus - Ridge EC_SMCA EC_SMDA EC_SMB_CK1 EC_SMB_DA1 3 Battery EC SM Bus1 address Device Smart Battery XX XXXX XXXX b DCIN / Charge 13 0001 001X b PCH SM Bus address Device ST sensor HUB 4 EC SM Bus2 address Address XX Device PCH SM Bus address(Link 1) Address Device XXXX XXXX b DDR Thermal sensor 99 Address Thunderbolt 29 0010 100X b(CIO P1) 2B 0010 101X b(CIO P2) 2D 0010 110X b(CIO P3) 2F 0010 111X b(CIO P4) Sensor HUB SM Bus address Device DCIN / charge Address 1001 101X b 4 Address Gyroscope D1 1101 000X b D3 1101 001X b Security Classification E-compass + G sensor 33 0011 001X b Issued Date ALS sensor 21 0010 000X b Compal Electronics, Inc. Compal Secret Data 2011/06/24 2012/06/02 Deciphered Date Title SMBUS Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 49 of 52 Rev 0.1 A B C D E V1JB1 SYSTEM Diagram 1 1 SYSTEM MB IO BOARD FPC between MB & IO Board JIO1 JIO1 Audio Codec Rear Camera ALS RTC Battery 2 JSW1,JSW2 2 JWIN1 Wire between IO/B & WIN/B FFC between IO/B & SW/B ( FFC x 2 ) 3 3 JWIN1 JSW1,JSW2 SWITCH BOARD ON/OFF BTN VOL UP/DOWN BTN POWER LED (BLUE/AMB) WIN BUTTON BOARD Window Home Key Reset BTN Prox Sensor 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title SYSTEM MAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 50 of 52 Rev 0.1 5 4 3 2 V ersion Change L ist ( P. I. R . L ist ) Item Page# D Title D ate R equest O w ner 1 Page 1 Issue D escription Solution D escription R ev. DVT D 01. Add net " IO/B_DET" to detect IO/B - Avoid thermal sensor wrong action by remote mode cause system auto shut down 02. Add 3 clips at ext USB area (RF requirement) 03. Move D_LOCK pull up resistor from IO/B to M/B side (Reserve function) 04. Move ON/OFFBTN# circuit from IO/B to M/B side(Sub/B just SW BTN only) 05. Change R960 to 8.2k ohm (Board ID update) 06. Change RP19, RP20 package to R_0402*8 (HDMI signal fine tune requirement) 07. Change C451,C450 BOM structure to XEMC@ 08. Delete R78 for Layout components reduce 09. Change SIM Card Connecotor as MOLEX_503960-0694 (ME requirement) 10. Change C548 to 0 ohm resistor (3G power from +3VS, not +3VALW) 11. Base on crystal vender suggest, change C756, C757 to 15pF, C744 & C745 to 12pF PVT C 01. Add test point at CPU pin B22, A19, B14, A11, B10, B6 (DFB requirement) 02. Modify EC_RST# circuit for Reset Button (Dual Mosfet) 03. Add ODT1, CKE1, CS1# net to DDR for 8Gb DRAMs 04. Remove EC_ON, MAINPWON net from JIO1 (un-used net) 05. Change R960 to 18k ohm (Board ID update) 06. Change R185, R186, R720 to short pad 07. Change R637 to 33 ohm (3G PWR SEQ) 08. Reserve 0 ohm resistor to GND for sensor PB13 as ST suggestion 09. Remove Screw "H18" (ME outline modify) 10. Unstuff 3G power switch circuit (un-used -> 3G power source tie to +3VS directly) 11. Add 3G@ BOM option for WiFi only sku 12. Change R499, R503, R504 from 10k to 100k for DS5 power consumption C R10 B 01. Change RP43 part number from SD302220A00(22 ohm) to SD309220A80 (22 ohm) for Green BOM request 02. Unstuff component of reserve circuit (un-used function) -> R503, Q7 (SIM_DET# to EC), R504 (EC_3G_ON_OFF#), R260, R311, R505, C407 (3G Ext. RST#) 03. Change R960 to 33k ohm (Board ID update) 04. Unstuff R485 to avoid leakage to wlan module ( 3G provide power when S3/DS3) 05. Unstuff SW5 (for test phase only, MP remove) 06. Update PCB PN to R10 07. As source request (cancel vender-Cheng Hann), change below parts~ 1. Change L23 PN from SM01000AX00 to SM01000EP00 2. Change L3, L4, L36, L38, L39, L40, L53, L68 PN from SM070001600 to SM070001E00 3. Change L52 PN from SM070001310 to SM070001E00 B R20 01. Add USB switch to 3G USB signals for avoid DS3 leakage 02. Delete Q7, R503 (un-used component) 03. Rename EC_SIM_DET# to EC_3G_PWR_EN# (correct net name to meet actual function) 04. Change EC GPD7 (U53.M12) to EC_3G_USB_ON for 3G USB switch 05. Change R960 to 56k ohm (Board ID update) 06. Update PCB PN to R20 A A Compal Secret Data Security Classification Issued Date 2011/06/13 2012/06/13 Deciphered Date Title Compal Electronics, Inc. EE P.I.R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: 5 4 3 2 Tuesday, March 26, 2013 Sheet 1 51 of 52 A ZZZ1 C D E WLAN/BT Module PCB 1 B LA-A041P MB Rev0: DAA0006P000 U1 PK29S004B00 S_W/L_MOD WCBN3501A W/BT MD222 ABO! LA-A041P MB Rev2: DAA0006P020 LA-A041P REV2 DAA0006P020 1 LIONMD222@ LA-A041P MB Rev1: DAA0006P010 W CBN3501A W /BT MD222 CPU UCPU1 UCPU1 S IC AV8063801058401 SR0N9 L1 1.8G ABO! I33217@ S IC AV8063801119500 SR0XF L1 1.9G ABO! I33227@ SA00005L5C0 SA00006D990 AV8063801119500 SR0XF L1 1.9G ABO! AV8063801058401 SR0N9 L1 1.8G ABO! UCPU1 UCPU1 S IC AV8063801058002 SR0N8 L1 1.7G ABO! I53317@ S IC AV8063801129900 SR0XL L1 1.8G ABO! I53337@ SA00005K6B0 SA00006D860 AV8063801129900 SR0XL L1 1.8G ABO! AV8063801058002 SR0N8 L1 1.7G ABO! 2 2 UCPU1 UCPU1 S IC AV8062701313000 SR0U3 J1 1.4G ABO! I32365M@ S IC AV8062701313100 SR0U4 J1 1.5G ABO! I32375M@ SA00005UH40 SA00006ED50 AV8062701313100 SR0U4 J1 1.5G ABO! SAGE 3G AV8062701313000 SR0U3 J1 1.4G ABO! 3 3 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Option Component Size Document Number Custom V1JB1 M/B LA-A041P Schematic Date: Sheet Thursday, March 14, 2013 E 52 of 52 Rev 0.1 www.s-manuals.com
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2013:03:26 17:03:44Z Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2016:03:02 17:58:52+02:00 Metadata Date : 2016:03:02 17:58:52+02:00 Format : application/pdf Creator : Title : Compal LA-A041P - Schematics. www.s-manuals.com. Subject : Compal LA-A041P - Schematics. www.s-manuals.com. Producer : GPL Ghostscript 8.15 Document ID : uuid:7919fbae-5d1e-441b-8e33-174ab965c1bc Instance ID : uuid:571f155b-0d75-4a54-a1e8-6e090de08e23 Page Count : 53 Keywords : Compal, LA-A041P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools