Compal LA B291P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Notebook Lenovo B50-45 - Service manuals and Schematics, Disassembly / Assembly. Free.

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A

B

C

D

E

1

1

Compal Confidential
2

2

ZAWBA/ZAWBB
DIS M/B Schematics Document
AMD Beema SOC with DDR3L
AMD Jet LE

2014-03-03
3

3

LA-B291P
REV：
：1.0

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Cover Page
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

1

of

46

A

B

C

VRAM 1G/2G
256M16 x 4 (2G)
128M16 x 4 (1G)
DDR3L

1

D

E

1

AMD Beema

AMD Jet LE

PCIe x 4

Gen2

VRAM 1GB/2GB
DDR3L x4

Memory BUS(DDR3L)

204pin DDR3L SO-DIMM X2

Single Channel

GFX

BANK 0, 1, 2

1.35V DDRIIIL 1600MHz

eDP Conn.

DP0

HDMI Conn.

CMOS
Camera

DP1

AMD FT3b APU

CRT Conn.
2

GPP0

Card Reader
Realtek

GPP2

NGFF
(WLAN/BT)

USB

Port 8

8111G/8106E

(reserved)

In IO/B

Port 1

Port 9

Port 0
2

Port 7

MB
3.0 Conn. LP2

Port 0

USB

Right USB 2.0
Conn.

Touch screen

Port 5

MB
3.0 Conn. LP1

BGA 769-balls

Transformer
RJ45

Finger Print

Port 1

USB3.0
HDA

HD Audio

SPI ROM (8MB)

SPI

Nuvoton
NPCE288NB0DX

Int.KBD

USB2.0

GPP1

LAN 10/100/1G
Realtek

RTS5229

3

Port 3

DAC
GPP

WLAN/BT
Combo

SATA

Gen3 Port 0

Port 1

HDD
Conn.

ODD
Conn.

Audio
Realtek
ALC233VB

LPC

3

Thermal Sensor

Touch Pad

Int. MIC

Int. Speaker Conn.

Audio Combo Jacks
In IO/B

15" Sub-borad
14" Sub-borad
IO/B
USB2.0 x 1
Combo Jack
Novo button

4

IO/B
USB2.0 x 1
Combo Jack
Novo button

ODD/B

LED/B

4

LED/B

Battery/B

14" Power/B
2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

15" Power/B

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Block Diagram
Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

2

of

46

A

B

C

Voltage Rails

2

Description

S0

S3

S5

VIN

Adapter power supply (19V)

ON

ON

ON

B+

AC or battery power rail for power circuit.

ON

ON

ON

Board ID
0
1
2
3
4
5
6
7

+APU_CORE

Core voltage for APU

ON

OFF

OFF

+APU_CORE_NB

Voltage for On-die VGA of APU

ON

OFF

OFF

+VGA_CORE

0.95-1.2V switched power rail

ON

OFF

OFF

+VDDCI

0.95-1.2V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+1.8VALW

1.8V always on power rail

ON

ON

ON*

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+0.95VALW

0.95V always on power rail

ON

OFF

OFF

+0.95VS

0.95V switched power rail

ON

OFF

OFF

+1.35V

1.35V power rail for APU and DDR

ON

ON

OFF

Board ID

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+3VGS

3.3V switched power rail for VGA

ON

OFF

OFF

+1.8VGS

1.8V switched power rail for VGA

ON

OFF

OFF

+1.35VGS

1.35V switched power rail for VGA

ON

OFF

OFF

+0.95VGS

0.95V switched power rail for VGA

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_APU

RTC power

ON

ON

ON

0
1
2
3
4
5
6
7

+0.675VS

0.675V switched power rail for DDR terminator

ON

OFF

PCB Revision
MP
PVT
DVT
EVT

3.3V +/- 5%
100K +/- 5%
R1564
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

SOURCE

3

288N

+3VALW

VGA

BATT

KB9012

X

V
+3VALW

X

X

X

X

X

APU

X

+3VS

X

X

X

V
+3VS

V
+3VS

X

X

X

X

288N

V

X

X

X

X

V

X

V

X

APU_SCLK0
APU_SDATA0
SMB_EC_CK2
SMB_EC_DA2

+3VS

APU

+3VS

+3VS

+3VS

HIGH

ON

ON

ON

ON

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

ON

OFF

OFF

OFF

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

0
1
2
3

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

EC SM Bus2 address

Device

Address

HEX

Device

Address

HEX

Smart Battery

0001 011X b

16H

Thermal Sensor

1001 101X b

9AH

SB-TSI (APU)

1001 100X b

98H

VGA Internal Thermal

4

USB 2.0 USB 3.0

1000 001X b

Card Reader
LAN
WLAN

XHCI

Device

Address

HEX

DDR DIMM1

1010 000Xb

A0H

DDR DIMM2

1010 001Xb

A2H

Port

0
1

USB20 port1,2,8,9

3 External
USB Port
Touch Screen
RIGHT USB
Camera
WLAN/BT Combo
Finger Print
LEFT USB3.0
LEFT USB3.0

2014/03/03

2015/03/03

Deciphered Date

Date:

B

C

BTO Item
for HDMI Logo
for 14" componect
2

for 15" componect
15W 2.4GHz BGA APU
15W 1.8GHz BGA APU
15W 1.5GHz BGA APU
10W 1.5GHz BGA APU
10W 1.35GHz BGA APU
UMA part
Common VGA circuit
Jet LE GPU
Topaz XT GPU
CMOS Camera part
HDMI part
Realtek RTL8106E with LDO mode
Realtek RTL8106E with SWR mode
Realtek RTL8111G with LDO mode
Realtek RTL8111G with SWR mode

3

Touch Screen
Zero Power ODD part
Non-Zero Power ODD part
USB Charger function
Non-USB Charger function
Full HD Panel
VRAM Dual Rank
VRAM Single Rank
USB 2.0
USB 3.0
Realtek ALC233-VB Audio IC
ME part
EMI pop component
EMI Un pop component
ESD pop component
ESD Un pop component

4

EMI Un pop for LAN GIGA function
Unpop

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

USB30 port0,1

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

0
1
2
3
4
5
6
7
8
9

USB Port
USB20 port0

BOM Structure
45@
14@
15@
B5@
B4@
B3@
B2@
B1@
UMA@
PX@
JET@
TOPAZ@
CMOS@
HDMI@
8106ELDO@
8106ESW@
8111GLDO@
8111GSW@
TS@
ZODD@
NOZODD@
CHG@
NOCHG@
FHD@
DR@
SR@
USB2@
USB3@
233VB@
ME@
EMIP@
EMIU@
ESDP@
ESDU@
GIGAEMIP@
@

Device

82H

APU
SM Bus address

1

BOM Structure Table

USB Port Table
EC SM Bus1 address

Clock

HIGH

OC#

0
1
2
3

X

+VS

USB OC MAPPING

Port

RTD2132

+V

HIGH

OFF

Thermal
Sensor FCH

+VALW

S1(Power On Suspend)

APU PCIE PORT LIST
WLAN
SODIMM WWAN

SLP_S3# SLP_S5#

Full ON

Board ID / SKU ID Table for AD channel
Vcc
R1562

SIGNAL

STATE

SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1

E

BOARD ID Table

Power Plane

1

D

D

NOTES LIST
Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

3

of

46

5

4

3

Jet LE VRAM STRAP
X76@

Vendor

ID

UV5, UV6, UV7, UV8
D

ZZZ10
1GBytes JM1G@

1

Power-Up/Down Sequence

X76@

ZZZ09
1GBytes JH1G@

2

Hynix 2048Mbits
SA00006H400
128Mx16 H5TC2G63FFR-11C
Micron 2048Mbits
SA000067500
128Mx16 MT41J128M16JT-093G:K

PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]

R_pu
RV21

0

0

0

0

NC

R_pd
RV24

4.75K

1

0

0

1

8.45K

2K

ZZZ11
1GBytes JS1G@

Samsung 2048Mbits
SA000068U40
128Mx16 K4W2G1646Q-BC1A

2

0

1

0

4.53K

2K

ZZZ12
2GBytes JH2G@

Hynix 4096Mbits
SA00006E800
256Mx16 H5TC4G63AFR-11C

3

0

1

1

6.98K

4.99K

ZZZ13
2GBytes JS2G@

Samsung 4096Mbits
SA000076P00
256Mx16 K4W4G1646D-BC1A

4

1

0

0

4.53K

4.99K

ZZZ14
2GBytes JM2G@

Micron 4096Mbits
SA000077K00
256Mx16 MT41J256M16HA-093G:E

5

1

0

1

3.24K

5.62K

6

1

1

0

3.4K

10K

7

1

1

1

4.75K

"Jet" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
The maximum slew rate on all rails is 50 mV/µs.
It is recommended that the 3.3-V rail ramp up frist.
It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
than 2ms from the start of VDDC ramping up.
The power rails that are shared with other components on the system should be gated for
the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
all the power rails are removed from the dGPU.
50mV/us)
The gate circuits must meet the slew rate requirement (such as
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.

‧
‧‧
‧

D

≦

‧
‧

Micron 4096Mbits

ZZZ08 SA000065D00
2GBytes JM2G2@ 256Mx16 MT41K256M16HA-107G:E
ZZZ16
1GBytes JM1G2@

Micron 2048Mbits
SA00005XB00
128Mx16 MT41K128M16JT-107G:K

VDDR3(+3VGS)
NC

PCIE_VDDC(+0.95VGS)

C

ZZZ

ZZZ

ZZZ

C

ZZZ

VDDR1(+1.35VGS)
JH1G@

1G HYNIX

X7653638L07

JM1G@

1G MICRON

X7653638L08

JS1G@

1G SAMSUNG

X7653638L09

JH2G@

VDDC/VDDCI(+VGA_CORE)

2G HYNIX

X7653638L04

VDD_CT(+1.8VGS)
PERSTb
REFCLK
Straps Reset
Straps Valid
B

B

Global ASIC Reset
T4+16clock

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

VGA Notes List
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

4

of

46

A

B

DDRAB_SDQ[63..0]

MEMORY

1

M_ADD0

M_DATA0

M_ADD1

M_DATA1

M_ADD2

M_DATA2

M_ADD3

M_DATA3

M_ADD4

M_DATA4

M_ADD5

M_DATA5

M_ADD6

M_DATA6

M_ADD7

M_DATA7

M_ADD9

M_DATA8

M_ADD10

M_DATA9

M_ADD11

M_DATA10

M_ADD12

M_DATA11

M_ADD13

M_DATA12

M_ADD14

M_DATA13

M_ADD15

M_DATA14

B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40

M_BANK1

M_DATA16

M_BANK2

M_DATA17

M_DM0

M_DATA19

M_DM1

M_DATA20

M_DM2

M_DATA21

M_DM3

M_DATA22

M_DM4

M_DATA23

2

M_DM6

M_DATA24

M_DM7

M_DATA25

M_DM8

M_DATA26

M_DQS_H0

M_DATA28

M_DQS_L0

M_DATA29

M_DQS_H1

M_DATA30

M_DQS_L1

M_DATA31

<10,9>
<10,9>

M_DQS_L2

M_DATA32

M_DQS_H3

M_DATA33

M_DQS_L3

M_DATA34

M_DQS_H4

M_DATA35

M_DQS_L4

M_DATA36

M_DQS_H5

M_DATA37

M_DQS_L5

M_DATA38

M_DQS_H6

M_DATA39

M_DQS_H7

M_DATA40

M_DQS_L7

M_DATA41

M_DQS_H8

M_DATA42

M_DQS_L8

M_DATA43

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

<9>
<9>
<10>
<10>

DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1

<9>
<9>
<10>
<10>

DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#

<10,9>
<10,9>
<10,9>

M_CLK_H0

M_DATA45

M_CLK_L0

M_DATA46

M_CLK_H1

M_DATA47

AJ34
AR38
AL38
AN35

M_DATA48

M_CLK_L2

M_DATA49

M_CLK_H3

M_DATA50

M_CLK_L3

M_DATA51

M_RESET_L

M_DATA53

M_EVENT_L

M_DATA54

AJ37
AL34
AL35

+MEM_VREF

+VREF_DQ_APU

AD40
AC38

M0_CKE1

M_DATA56

M1_CKE0

M_DATA57

M1_CKE1

M_DATA58

M0_ODT0

M_DATA60

M0_ODT1

M_DATA61

M1_ODT0

M_DATA62

M1_ODT1

M_DATA63

M0_CS_L0

M_CHECK0

M0_CS_L1

M_CHECK1

M1_CS_L0

M_CHECK2

M1_CS_L1

M_CHECK3

M_RAS_L

M_CHECK5

M_CAS_L

M_CHECK6

M_WE_L

M_CHECK7

14@

LAB291P
DA60014S000

AM41
AN40
AT41
AU40
AL40
AM40
AR40
AT40

DDRAB_SDQ40
DDRAB_SDQ41
DDRAB_SDQ42
DDRAB_SDQ43
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQ46
DDRAB_SDQ47

AV41
AW40
BA38
AY37
AU41
AV40
AY39
AY38

DDRAB_SDQ48
DDRAB_SDQ49
DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDQ54
DDRAB_SDQ55

BA36
AY35
BA32
AY31
BA37
AY36
BA33
AY32

DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDQ58
DDRAB_SDQ59
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQ62
DDRAB_SDQ63

15@

DA60014S100

AD41

M_ZVDDIO

EDP_TXP1
EDP_TXN1

A11
B11

TDP1_TXP2

A12
B12

TDP1_TXP3

TDP1_TXN1

TDP1_TXN2

TDP1_AUXN

D17
E17

TDP1_HPD

H19

TDP1_AUXP

TDP1_TXN3

A4
B4

LTDP0_TXP0

LTDP0_AUXP

LTDP0_TXN0

LTDP0_AUXN

D15
E15

A5
B5

LTDP0_TXP1

LTDP0_HPD

H17

DAC_RED

B14

A6
B6

LTDP0_TXP2
LTDP0_TXN2

DAC_GREEN

A14

A7
B7

LTDP0_TXP3

R1644 1
R1645 1
R1646 1

APU_SVT
APU_SVC
APU_SVD

R1124 1
R1127 1

<12,25,27> EC_SMB_CK2
<12,25,27> EC_SMB_DA2

DAC_BLUE

B15

DAC_HSYNC

G19
E19

DISP_CLKIN_H

@
@

APU_PWRGD

APU_SVT_R
APU_SVC_R
APU_SVD_R

G31
D27
E29

2 0_0402_5%
2 0_0402_5%

APU_SIC
APU_SID

B22
B21

SIC

APU_RST#
TEMPIN1

B20
A20

APU_RST_L

APU_PWRGD
TEMPIN2

B19
A19

APU_PWROK

<27,7>

A22
B18

PROCHOT_L

2 R118
1 KABINI@
0_0402_5%
2 0_0402_5% APU_PROCHOT#
R1120 1
@
APU_ALERT#

H_PROCHOT#

ESDU@
C186
100P_0402_50V8J

1

1

2

2

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

ESDU@
C175
100P_0402_50V8J

HDT

D29
D31
D35
D33
G27
B25
A25
D23
G23
E25
E23

<40> APU_VDDNB_SEN
<40> APU_VDD_SEN
<40>

APU_VDD_RUN_FB_L

AV33
AU33

ENBKL <20,27>
APU_ENVDD <20>
APU_INVT_PWM <20>
HDMI_CLK <22>
HDMI_DATA <22>
HDMI_DET

DAC_VSYNC

DAC_SDA

D19
D21

SVT

EDP_HPD

DAC_ZVSS

A16

<21>

DAC_BLU

LDT_PWROK

ALERT_L
TDI
TDO

CRT

<21>

CRT_HSYNC
CRT_VSYNC

<21>
<21>

CRT_DDC_CLK <21>
CRT_DDC_DATA <21>
R416 1

DAC_ZVSS

2 499_0402_1%
+3VS

H27
THERMDC H29
DIECRACKMON D25
BP0 A27
BP1 B27
BP2 A26
BP3 B26
PLLTEST1 B28
PLLTEST0 A28
BYPASSCLK_H B24
BYPASSCLK_L A24
PLLCHRZ_H AV35
PLLCHRZ_L AU35
M_TEST E33

LDT_RST_L

APU_BP0
APU_BP1
APU_BP2
APU_BP3
APU_PLLTEST1
APU_PLLTEST0
APU_BPCLK_H
APU_BPCLK_L

Test14
EDP_AUXP
EDP_AUXN

R255 2
R256 2

@
@

1 4.7K_0402_5%
1 4.7K_0402_5%

RP23
8
7
6
5

T39
T40
T41

1
2
3
4

DAC_BLU
DAC_GRN
DAC_RED
DP_150_ZVSS

2

150_0804_8P4R_1%

TCK
TMS

A29

FREE_2

TEMPIN0
APU_SCLK
APU_CLKINT

GIO_TSTDTM0_SERIALCLK H21

TRST_L
DBRDY

GIO_TSTDTM0_CLKINIT

H25

T42

DBREQ_L
VDDCR_NB_SENSE

USB_ATEST1

VDDCR_CPU_SENSE

M_ANALOGIN

VDDIO_MEM_S_SENSE

M_ANALOGOUT

VSS_SENSE

TMON_CAL

AJ10
AJ8
R32
N32
AP29

HDMI_EN/DP_STEREOSYNCE21

VDD_095_FB_H

T45
T43
T44
T46
T47
DP_STEREOSYNC

T48

VDD_095_FB_L

FT3 REV 0.51

A6@

PU +3VS

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

APU_PWRGDC1270

ESDU@
1
2 22P_0402_50V8J

+3VS

APU_RST#

ESDU@
1
2 22P_0402_50V8J

C1273

+3VS

RP4
1
2
3
4

APU_ALERT#
APU_SID
APU_PROCHOT#
APU_SIC

8
7
6
5
1K_0804_8P4R_5%
3

PU +1.8VS

1

+1.8VS

RP5 @

PU +1.8VS + PD

1

3
5

APU_TRST#

9

RP11
8
7
6
5

13
15

10K_0804_8P4R_5%

17
19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17
19

R1080 1
R1082 1
R1018 1

APU_RST#
APU_PWRGD
APU_BPCLK_L

8
7
6
5
1K_0804_8P4R_5%
2 300_0402_5%
2 300_0402_5%
2 511_0402_1%

+1.8VS

JHDT2
1
2

1
2
3
4

APU_SVT
APU_SVC
APU_SVD

+1.8VS

RP2

18
20

2

APU_TCK

4

APU_TMS

6

APU_TDI

8

APU_TDO

RP6
APU_TDI
APU_TMS
APU_TCK
APU_DBREQ#

1
2
3
4

APU_SCLK
APU_CLKINT
APU_SCLK
APU_CLKINT

1K_0804_8P4R_5%
10

APU_PWRGD

12

APU_RST#

14

APU_DBRDY

16

APU_DBREQ#

18

APU_PLLTEST0

20

APU_PLLTEST1

+1.8VS

RP3 @
8
7
6
5

1
2
3
4

8
7
6
5
1K_0804_8P4R_5%

PD

RP7 @

APU_BP2
APU_BP3
APU_BP0
APU_BP1

1
2
3
4

APU_TRST#
APU_PLLTEST0
APU_PLLTEST1

1
2
3
4

8
7
6
5
1K_0804_8P4R_5%
RP8
+1.8VS
8
7
6
5
4

1K_0804_8P4R_5%

RP11, RP6 will @ when MP
R1019 1

APU_BPCLK_H

2 511_0402_1%

+MEM_VREF

C1371

0.1U_0402_16V7K

MEM_MAB_EVENT#

@ SAMTE_ASP-136446-07-B
1

1K_0804_8P4R_1%
2

2
C337
1U_0402_6.3V6K

1

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
C1163
0.1U_0402_16V7K

2015/03/03

Deciphered Date

Title

FT3 DDR3/DISP/MISC//HDT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

<21>

DAC_GRN

THERMDA

SID

1

<20>

DAC_RED

SVC
SVD

<22>

EDP_AUXP <20>
EDP_AUXN <20>

DISP_CLKIN_L

2 33_0402_5%
2 33_0402_5%
2 33_0402_5%

2 R117
1 KABINI@
0_0402_5%
<40>

2 2K_0402_1%

LTDP0_TXN3

DAC_SCL

<40>
<40>
<40>

R400 1

LTDP0_TXN1

HDT+

UAPU
ESDU@ C1195
E1-6050 ZM1332M2J2370 1.35G BGA769P
0.1U_0402_16V7K
E1@

4

1 ESDP@

<20>
<20>

TDP1_TXP1

R1113
1K_0402_5%

UAPU
E2-6200 ZM151103J4470 1.5G BGA 769P
E2@

1
2
3
4

2

EDP_TXP0
EDP_TXN0

A10
B10

K15
H15

11

8
7
6
5

<20>
<20>

DP_150_ZVSS
DP_2K_ZVSS

2
+1.35V
R1074
39.2_0402_1%
A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

M_ZVDDIO_MEM_S

MEMORY VREF

1
2
3
4

DP2_TXP3
DP2_TXN3

EDP use 2 Lane for FHD

7

+1.35V

<22>
<22>

V41
W40
AB40
AC40
U41
V40
AA41
AB41

UAPU
A4-6300 ZM181103J4470 1.8G BGA 769P
A4@

LAB291P

DP2_TXP2
DP2_TXN2

DP_2K_ZVSS

CRT_HSYNC

M_VREFDQ

A6@
DAX

DDRAB_SDQ32
DDRAB_SDQ33
DDRAB_SDQ34
DDRAB_SDQ35
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDQ38
DDRAB_SDQ39

<22>
<22>

B16
A21
B17
DP_DIGON A17
DP_VARY_BL A18

DP_150_ZVSS

TDP1_TXN0

DP_BLON

M_VREF

FT3 REV 0.51

DAX

AF40
AF41
AK40
AK41
AE40
AE41
AJ40
AJ41

DP2_TXP1
DP2_TXN1

UAPUC
DISPLAY/SVI2/JTAG/TEST
TDP1_TXP0

M0_CKE0

M_CHECK4

DDRAB_SRAS#
DDRAB_SCAS#
DDRAB_SWE#

DDRAB_SDQ24
DDRAB_SDQ25
DDRAB_SDQ26
DDRAB_SDQ27
DDRAB_SDQ28
DDRAB_SDQ29
DDRAB_SDQ30
DDRAB_SDQ31

<22>
<22>

A9
B9

USB_ATEST0

M_CLK_H2

M_DATA59

AN38
AU38
AN37
AR37

M41
N40
T41
U40
L40
M40
R40
T40

EDP

DP2_TXP0
DP2_TXN0

M_CLK_L1

M_DATA55

L34
J38
J37
J34

DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SDQ20
DDRAB_SDQ21
DDRAB_SDQ22
DDRAB_SDQ23

M_DQS_L6

M_DATA52

G38
MEM_MAB_EVENT# AE34

MEM_MAB_RST#
MEM_MAB_EVENT#
<9>
<9>
<10>
<10>

3

AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

F40
F41
K40
K41
E40
E41
J40
J41

M_DQS_H2

M_DATA44

<9>
<9>
<9>
<9>
<10>
<10>
<10>
<10>

DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ12
DDRAB_SDQ13
DDRAB_SDQ14
DDRAB_SDQ15

<22>
<22>

E

M_DM5

M_DATA27

B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41

DDRAB_SDQS0
DDRAB_SDQS0#
DDRAB_SDQS1
DDRAB_SDQS1#
DDRAB_SDQS2
DDRAB_SDQS2#
DDRAB_SDQS3
DDRAB_SDQS3#
DDRAB_SDQS4
DDRAB_SDQS4#
DDRAB_SDQS5
DDRAB_SDQS5#
DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS7
DDRAB_SDQS7#

B37
A38
D40
D41
B36
A37
B41
C40

HDMI

M_BANK0

M_DATA18

DDRAB_SDM0
DDRAB_SDM1
DDRAB_SDM2
DDRAB_SDM3
DDRAB_SDM4
DDRAB_SDM5
DDRAB_SDM6
DDRAB_SDM7

DDRAB_SDQ0
DDRAB_SDQ1
DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ4
DDRAB_SDQ5
DDRAB_SDQ6
DDRAB_SDQ7

M_ADD8

M_DATA15

AJ38
AG35
N34

<10,9> DDRAB_SBS0#
<10,9> DDRAB_SBS1#
<10,9> DDRAB_SBS2#
<10,9> DDRAB_SDM[7..0]

B30
A32
B35
A36
B29
A30
A34
B34

D

HDMI & LVDS should be reverse in KABINI:
APU TX0 to Connector TX2 ; APU TX1 to Connector TX1
APU TX2 to Connector TX0 ; APU TX3 to Connector CLK

<10,9>

2

DDRAB_SMA0 AG38
DDRAB_SMA1 W35
DDRAB_SMA2 W38
DDRAB_SMA3 W34
DDRAB_SMA4 U38
DDRAB_SMA5 U37
DDRAB_SMA6 U34
DDRAB_SMA7 R35
DDRAB_SMA8 R38
DDRAB_SMA9 N38
DDRAB_SMA10 AG34
DDRAB_SMA11 R34
DDRAB_SMA12 N37
DDRAB_SMA13 AN34
DDRAB_SMA14 L38
DDRAB_SMA15 L35

<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>
<10,9>

C

UAPUA

DDRAB_SMA[15..0]

1

<10,9>

B

C

D

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

5

of

46

A

B

C

D

UAPUB

APU POWER SEQUENCE

PCIE

Card Reader

<31>
<31>

PCIE_DTX_C_ARX_P0
PCIE_DTX_C_ARX_N0

LAN

<29>
<29>

PCIE_DTX_C_ARX_P1
PCIE_DTX_C_ARX_N1

<24>
<24>

WLAN

R10
R8

P_GPP_RXP0

P_GPP_TXP0

P_GPP_RXN0

P_GPP_TXN0

R5
R4

P_GPP_RXP1

P_GPP_TXP1

P_GPP_RXN1

P_GPP_TXN1

N5
N4

P_GPP_RXP2

P_GPP_TXP2

P_GPP_RXN2

P_GPP_TXN2

N10
N8

P_GPP_RXP3

P_GPP_TXP3

P_GPP_RXN3

P_GPP_TXN3

PCIE_DTX_C_ARX_P2
PCIE_DTX_C_ARX_N2

E

L2
L1

PCIE_ATX_DRX_P0
PCIE_ATX_DRX_N0

C1021
C1022

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

K2
K1

PCIE_ATX_DRX_P1
PCIE_ATX_DRX_N1

C1019
C1020

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

J2
J1

PCIE_ATX_DRX_P2
PCIE_ATX_DRX_N2

C1017
C1018

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_ATX_C_DRX_P0 <31>
PCIE_ATX_C_DRX_N0 <31>

Card Reader

PCIE_ATX_C_DRX_P1 <29>
PCIE_ATX_C_DRX_N1 <29>

LAN

PCIE_ATX_C_DRX_P2 <24>
PCIE_ATX_C_DRX_N2 <24>

WLAN

+RTC

G-A

EC_ON
+3VALW/+5VALW

G-B

H2
H1

+1.8VALW

1

1

+0.95VALW
1

+0.95VS_APU_GFX

VGA

2 P_TX_ZVDD_095
R404
1.69K_0402_1%

<11>
<11>

PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_N0

<11>
<11>

PCIE_GTX_C_ARX_P1
PCIE_GTX_C_ARX_N1

<11>
<11>

PCIE_GTX_C_ARX_P2
PCIE_GTX_C_ARX_N2

<11>
<11>

PCIE_GTX_C_ARX_P3
PCIE_GTX_C_ARX_N3

W8

P_RX_ZVDD_095 W7

P_TX_ZVDD_095

L5
L4

P_GFX_RXP0

P_GFX_TXP0

P_GFX_RXN0

P_GFX_TXN0

J5
J4

P_GFX_RXP1

P_GFX_TXP1

P_GFX_RXN1

P_GFX_TXN1

G5
G4

P_GFX_RXP2

P_GFX_TXP2

P_GFX_RXN2

P_GFX_TXN2

D7
E7

P_GFX_RXP3

P_GFX_TXP3

P_GFX_RXN3

P_GFX_TXN3

2

P_RX_ZVDD_095

1
R73
1K_0402_1%

+0.95VS_APU_GFX

G2
G1

PCIE_ATX_GRX_P0
PCIE_ATX_GRX_N0

C1001 PX@ 1
C1002 PX@ 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

F2
F1

PCIE_ATX_GRX_P1
PCIE_ATX_GRX_N1

C1003 PX@ 1
C1004 PX@ 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

E2
E1

PCIE_ATX_GRX_P2
PCIE_ATX_GRX_N2

C1005 PX@ 1
C1006 PX@ 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

D2
D1

PCIE_ATX_GRX_P3
PCIE_ATX_GRX_N3

C1007 PX@ 1
C1008 PX@ 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

SYSON
+1.5V

G-C
PCIE_ATX_C_GRX_P0 <11>
PCIE_ATX_C_GRX_N0 <11>

SUSP#
+3VS

G-D

PCIE_ATX_C_GRX_P1 <11>
PCIE_ATX_C_GRX_N1 <11>

+1.8VS

VGA

PCIE_ATX_C_GRX_P2 <11>
PCIE_ATX_C_GRX_N2 <11>

+1.5VS
+0.95VS

PCIE_ATX_C_GRX_P3 <11>
PCIE_ATX_C_GRX_N3 <11>

VR_ON
+APU_CORE

G-E

FT3 REV 0.51

A6@

+APU_CORE_NB

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

UAPUE
2

2

CLK/SATA/USB/SPI/LPC

<23>
<23>

SATA_ATX_DRX_P1
SATA_ATX_DRX_N1

<23>
<23>

SATA_DTX_C_ARX_N1
SATA_DTX_C_ARX_P1
R90
R96

+0.95VS

2
2

BA16
AY16

SATA_TX0N
USB_ZVSS

AG4

USB_HSD0P

AL4
AL5

SATA_RX0P

SATA_TX1N

USB_HSD1P

AY17
BA17

SATA_RX1N

AR19
AP19

SATA_ZVSS

BA30

SATA_ACT_L/GPIO67

AY12

SATA_X1

BA12

SATA_X2

SATA_RX1P

USB_HSD2P
USB_HSD2N

SATA_ZVDD_095

USB_HSD3P
USB_HSD3N

<26>

SATALED#

SATALED#

USB_HSD4P
USB_HSD4N
USB_HSD5P
USB_HSD5N
USB_HSD6P
USB_HSD6N

VGA
Card Reader
3

LAN
WLAN

<11>
<11>

CLK_PCIE_GPU
CLK_PCIE_GPU#

<31>
<31>

CLK_PCIE_CR
CLK_PCIE_CR#

<29>
<29>
<24>
<24>

U4
U5

CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#

GFX_CLKP

USB_HSD7P

GFX_CLKN

USB_HSD7N

AC8
AC10

GPP_CLK0P

USB_HSD8P

GPP_CLK0N

USB_HSD8N

AE4
AE5

GPP_CLK1P

USB_HSD9P

GPP_CLK1N

USB_HSD9N

AC4
AC5

GPP_CLK2P

AA5
AA4

GPP_CLK3P

USB_SS_0TXP

GPP_CLK3N

USB_SS_0TXN

X14M_25M_48M_OSC

USB_SS_0RXP

AP13

USB_SS_ZVSS

USB_SS_1TXN

N1

<27,7>
<7>

R1133 1
R1134 1

LPC_CLK0_EC
LPC_CLK1

@
@

2 0_0402_5%
2 0_0402_5%

AY2
AW2

T50

AT2
AT1
AR2
AR1
AP2
AP1
AV29
AP25
AV2

<27>

SERIRQ

USB20_P1
USB20_N1

<28>
<28>

Right USB port

AG1
AG2

USB20_P3
USB20_N3

<20>
<20>

CAMERA

USB20_P5
USB20_N5

<24>
<24>

WLAN/BT combo

AE1
AE2

48M_X2

AC1
AC2
AB1
AB2
AA1
AA2
AE10

USBSS_ZVSS R644 1
USBSS_ZVDD R645 1

T2
T1

<28>
<28>

Finger Print

USB30_P8
USB30_N8

<28>
<28>

MB USB3.0 port0

USB30_P9
USB30_N9

<28>
<28>

MB USB3.0 port1

2 1K_0402_1%
2 1K_0402_1%

V2
V1

SPI_DO/GPIO163 AR11
SPI_DI/GPIO164 AR7
SPI_HOLD_L/GEVENT9_LAU11
SPI_WP_L/GPIO161 AU9

LAD1
LAD2
LAD3
LFRAME_L

3

+0.95VALW

USB30_MTX_C_DRX_P1 <28>
USB30_MTX_C_DRX_N1 <28>

APU_SPI_CLK
APU_SPI_CS1#
APU_SPI_AOSI
APU_SPI_AISO
APU_SPI_HOLD#
APU_SPI_WP#

T51

APU_SPI_AISO
APU_SPI_AOSI_U
APU_SPI_CLK_U
APU_SPI_CS1#_U

1
2
3
4

8
7
6
5

EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#

0_0804_8P4R_5%

R109,R110,R111 close to APU

R110 1
R111 1

2 33_0402_5% APU_SPI_CLK_U
2 33_0402_5% APU_SPI_CS1#_U

R109 1

2 33_0402_5% APU_SPI_AOSI_U

3

4

EC_SPI_AISO <27>
EC_SPI_AOSI <27>
EC_SPI_CLK <27>
EC_SPI_CS1# <27>
+3VALW

1

4

RP13

APU_SPI_CS1#_U1
APU_SPI_WP# 2
APU_SPI_HOLD# 3
4

C794
6P_0402_50V8

C795
6P_0402_50V8

8
7
6
5
+3VALW

10K_0804_8P4R_5%
2

8MB SPI ROM
U1

APU_SPI_AISO

R108 1

2 33_0402_5%

R108 close to ROM

SERIRQ/GPIO48

APU_SPI_CS1#_U
APU_SPI_AISO_U
APU_SPI_WP#

LPC_CLKRUN_L

A6@

1

@

LDRQ0_L

LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

2

Y2
48MHZ_8PF_X3S048000D81H-W
RP12

USB30_MRX_DTX_P1 <28>
USB30_MRX_DTX_N1 <28>

SPI_CS2_L/GPIO166 AR4

48M_X1

3

USB30_MRX_DTX_P0 <28>
USB30_MRX_DTX_N0 <28>

R1
R2

AU7

2

USB30_MTX_C_DRX_P0 <28>
USB30_MTX_C_DRX_N0 <28>

EMIP@
SPI_CLK/GPIO162

R938
1M_0402_5%

USB20_P7
USB20_N7

LPCCLK0

LAD0

48MHz CRYSTAL

AD1
AD2

USB_SS_1RXP

LPCCLK1

Touch Screen (reserved)

AF1
AF2

W1
USB_SS_1RXN W2

X48M_X2

FT3 REV 0.51

4

<20>
<20>

AG7
AG8

SPI_CS1_L/GPIO165 AW9

<27> LPC_AD0
<27> LPC_AD1
<27> LPC_AD2
<27> LPC_AD3
<27,7> LPC_FRAME#

USB20_P0
USB20_N0

X48M_X1
USB_SS_1TXP

48M_X2

AJ4
AJ5

AE8
USB_SS_ZVDD_095_USB3_DUAL

GPP_CLK2N

USB_SS_0RXN

N2

48M_X1

2 11.8K_0402_1%

SATA_TX1P
USB_HSD1N

1 1K_0402_1% SATA_ZVSS
1 1K_0402_1% SATA_ZVDD

R641 1

SATA_RX0N
USB_HSD0N

AY19
BA19

USB_ZVSS

1

SATA_DTX_C_ARX_N0
SATA_DTX_C_ARX_P0

W4
USBCLK/14M_25M_48M_OSC

SATA_TX0P

2

<23>
<23>

BA14
AY14

1

ODD

SATA_ATX_DRX_P0
SATA_ATX_DRX_N0

2

HDD

<23>
<23>

APU->EC->ROM must route as
Daisy Chain for Share ROM quality
(RP12 was request to added for the recoverable
solution as original method)

1
2
3
4

/CS
DO(IO1)
/WP(IO2)
GND

VCC
/HOLD(IO3)
CLK
DI(IO0)

8
7
6
5

4

APU_SPI_CLK_U 1

2
1
2
R617 EMIU@
10_0402_5%
C636 EMIU@
10P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data
2014/03/03

Issued Date

C635
0.1U_0402_16V4Z
APU_SPI_HOLD#
APU_SPI_CLK_U
APU_SPI_AOSI_U

W25Q64FVSSIQ_SO8

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

Security Classification

1

2015/03/03

Deciphered Date

Title

FT3 PCIE/SATA/CLK/USB/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-B291P

Date:

A

B

C

D

Monday, March 03, 2014

Sheet
E

6

of

46

A

B

C

ACPI/SD/AZ/GPIO/RTC/MISC

EC_RSMRST#_R

AY4
AY9

LPC_RST_L

AY5

RSMRST_L

SD_PWR_CTRL

PCIE_RST_L

SD_CLK/GPIO73
SD_CMD/GPIO74
SD_CD/GPIO75

<24>

PBTN_OUT#

APU_PCIE_WAKE#
<27>
<27>

1

BA8
AM19
AY7
AW11

PWR_GOOD_APU
SYS_RESET_L
APU_PCIE_WAKE#

AY3
BA5

SLP_S3#
SLP_S5#

<27>

KBRST#

<27>
<27>

EC_SCI#
EC_SMI#

SD_WP/GPIO76

TEST0
CS_JTAG_TMS_TEST1
TEST2

AU13
AY10
AY6
AR23
AR31
AN5
AL7

GATEA20

SD_DATA3/GPIO80

BA22
AY21
AY24
BA24

SD_LED/GPIO45

AY25

TEST1/TMS

SCL0/GPIO43

TEST2

SDA0/GPIO47

AU25
AV25

SYS_RESET_L/GEVENT19_L

SD_DATA0/GPIO77

WAKE_L/GEVENT8_L

SD_DATA1/GPIO78

SLP_S3_L

KBRST_L

SCL1/GPIO227

GA20IN/GEVENT0_L

<12>

R290 1

VGA_CLKREQ#

2 0_0402_5%

@

<28> USB_OC0#
<28> USB_OC1#
<23> ODD_PLUGIN#

2

<30>

AY8
AW1
AV1
AY1

T54

HDA_SDIN0

T55
T56
T57

AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SYNC
HDA_RST#

SDA1/GPIO228

LPC_SMI_L/GEVENT23_L

GPIO49

AC_PRES/IR_RX0/GEVENT16_L

GPIO55

IR_TX0/GEVENT21_L

GPIO57

IR_TX1/GEVENT6_L

GPIO58

IR_RX1/GEVENT20_L

GPIO59

IR_LED_L/LLB_L/GPIO184

GPIO64

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

GPIO68

CLK_REQ1_L/GPIO61

GPIO69

CLK_REQ2_L/GPIO62

GPIO70

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

GPIO71

CLK_REQG_L/GPIO65/OSCIN

GPIO174

AJ2

USB_OC1_L/TDI/GEVENT13_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167

GENINT1_L/GPIO32

AZ_SDIN3/GPIO170

GENINT2_L/GPIO33

AJ1

BA29
AP23

R2122 1

@

FANOUT0/GPIO52

1

BT_OFF#

<24>

ODD_EN

<23>

UMA@

2 0_0402_5%
R661 1
@
APU_GPIO174

H_PROCHOT#

0

PX5.5

1

UMA

PX@ R912
10K_0402_5%

<27,5>

32.768KMHz CRYSTAL

GEVENT2#

32K_X1
ODD_DA#_APU_R
BLINK
EC_LID_OUT#

R292 1

2 0_0402_5%

@

EC_LID_OUT#

DGPU_PWROK

ODD_DA#_APU

1

<23>

DGPU_PWROK

2

2

Y1
32.768KHZ_12.5P_1TJF125DP1A000D

<41>

AV31
AU31

1

2

1
AV11

32K_X2

R914
20M_0402_5%

<27>

X32K_X1

X32K_X2

R911
10K_0402_5%

Board_ID1

Function

Board_ID1

PXS_RST# <11>
APU_SPKR <30>
DGPU_PWR_EN <13,27>

DGPU_PWR_EN

AZ_SYNC
AZ_RST_L

<11,24,29,31>

2

If use as SMBUS :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
Qty: 1; Value: 2.2 KΩ; Tol: 5%
If no use :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
Qty: 1; Value: 10 KΩ; Tol: 5%

USE

Board_ID1
2 0_0402_5%

AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169

APU_PCIE_RST#
1

+3VS

APU_SCLK0 <10,9>
APU_SDATA0 <10,9>

APU_SCLK1
APU_SDATA1NO

AP27
AY28
BA28
AV23
AP21
BA26
AV19
AY27
BA27
AU21
AY26
AV21
AM21
BA3

GEVENT2_L

RTCCLK

32K_X2

APU_SCLK0
APU_SDATA0

AY11
BA11

AV17
GEVENT4_L BA4
GEVENT7_L AR15
GEVENT10_L AP17
GEVENT11_L AP11
GEVENT17_L AN8
BLINK/GEVENT18_L AU17
GEVENT22_L BA6

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

FANIN0/GPIO56

32K_X1

C912
150P_0402_50V8J

LPC_PME_L/GEVENT3_L

SPKR/GPIO66

AU29
AW29
AR27
AV27
VGA_CLKREQ#_R AY29

CR_CLKREQ#
LAN_CLKREQ#
WLAN_CLKREQ#

<31> CR_CLKREQ#
<29> LAN_CLKREQ#
<24> WLAN_CLKREQ#

2
R907
33_0402_5%

TEST0

GPIO51

AP15
AV13
BA9
BA10
AV15

1

APU_PCIE_RST#_BUF

SLP_S5_L

GPIO50

C1376
1000P_0402_50V7K
2 ESDP@

AY23
AY20
BA20

PWR_GOOD

SD_DATA2/GPIO79

ATE Test

1

PWR_BTN_L

BA23
AY22

1

LPC_RST_A#
APU_PCIE_RST#_BUF

2

2
R602
33_0402_5%

1

1

LPC_RST#

<27>

<27>

E

UAPUD

C615
150P_0402_50V8J
<27>

D

2

2

1

RTC_CLK

<24>

2

1
C682
22P_0402_50V8J

2

C686
18P_0402_50V8J

FT3 REV 0.51

A6@

STRAPS OF APU

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

HDA for AUDIO
RP15

+3VALW

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
HDA_SDOUT_AUDIO

PU +3VALW + PD
R691 1

8
7
6
5

HDA_BITCLK
HDA_SYNC
HDA_RST#
HDA_SDOUT

LPC_FRAME#

33_0804_8P4R_5%

1

EMIU@
C264
22P_0402_50V8J

2 10K_0402_5%

@

R686 1

2 10K_0402_5%

LPC_CLK0_EC

LPC_CLK1

GEVENT2_L

SYS_RESET_L RTC_CLK

H

SPI ROM
(DEFAULT)

BOOT FAIL TIMER
ENABLED

CLKGEN
ENABLE
(DEFAULT)

1.8V SPI ROM

NORMAL POWR
UP/RESET TIMING
(DEFAULT)

L

LPC ROM

BOOT FAIL TIMER
DISABLED
(DEFAULT)

CLKGEN
DISABLED

3.3V SPI ROM
(DEFAULT)

EMI

2

<30>
<30>
<30>
<30>

1
2
3
4

APU_GPIO174

reserved

Coin Battery

Direct DC

3

3

HDA_SDIN0

RP10 @
VGA_CLKREQ#_R

TEST0
CS_JTAG_TMS_TEST1
TEST2

1
2
3
4

8
7
6
5
15K_0804_8P4R_5%

2015/03/03

Deciphered Date

B

1

1

1

2

2

2

1

1

1

1

1

1

Title

FT3 GPIO/AZ/MISC/STRAPS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-B291P

Date:

A

2

1

1
1

1

2014/03/03

Issued Date

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@

2

2 10K_0402_5%

PX@ 2 10K_0402_5%

2

@

R689 1

@

2

R688 1

1K_0804_8P4R_5%

2

HDA_BITCLK

2

2 10K_0402_5%

2

@

@

2.2K_0402_5%

R684 1

@

2.2K_0402_5%

BT_OFF#

8
7
6
5

2.2K_0402_5%

2 10K_0402_5%

@
1
2
3
4

2.2K_0402_5%

@

RTC_CLK

+3VALW

RP9 @

2K_0402_5%

R687 1

PU +3VALW + PD

GEVENT2#

2K_0402_5%

VGA_CLKREQ#_R

1U_0402_6.3V6K
C212

2K_0402_5%

R618 1 UMA@ 2 8.2K_0402_5%

2

2

LAN_CLKREQ#
APU_SCLK0
APU_SDATA0

2

R953

2 8.2K_0402_5%
2 2.2K_0402_5%
2 2.2K_0402_5%

1

R951

@

1

R950

R621 1
R673 1
R674 1

1U_0402_6.3V6K
C209

R929

CR_CLKREQ#
WLAN_CLKREQ#

R927

2 8.2K_0402_5%
2 8.2K_0402_5%

LPC_FRAME#
LPC_CLK0_EC
LPC_CLK1

R926

@
@

2

2
BLINK
<27,6>
<27,6>
<6>

RB751V-40TE17_SOD323-2
R623 1
R622 1

2

1
2

2

1

PWR_GOOD_APU

R903

PD

SYS_RESET_L
SCS00005C00
2

10K_0402_5%

1

SYS_PWRGD_EC

R954

D15
<27>

+3VS

4

EC_RSMRST#_R

10K_0402_5%

PU +3VS

2

RB751V-40TE17_SOD323-2

R952

1

EC_RSMRST#

@
10K_0402_5%

<27>

R949

0_0402_5%
EC_LID_OUT#
USB_OC0#
USB_OC1#

@

10K_0402_5%

2 100K_0402_5%
2 100K_0402_5%
2 100K_0402_5%

@

R928

@

D13

2

R685
10K_0402_5%

10K_0402_5%

R656 1
R650 1
R651 1

R345
47K_0402_5%

SCS00005C00

R925

R1650

1
@
R1649

+1.8VALW

Must connected to 10 ms RC delay
circuit on +1.8-V S5 power rail.

10K_0402_5%

2
10K_0402_5%

@

EC_RSMRST# , POWER_GOOD
follow CRB
(APU side 1.8V power rail)

R904

1

@

APU_SCLK1
APU_SDATA1
APU_PCIE_WAKE#
2
DGPU_PWR_EN
0_0402_5%

10K_0402_5%

8
7
6
5
1
R1648
10K_0804_8P4R_5%

R902

1
2
3
4

1

RP14
+3VS

+3VALW

PU +3VALW

+3VALW

C

D

Monday, March 03, 2014

Sheet
E

7

of

46

B

C

VDDBT_RTC_G

U102

180P_0402_50V8J

2

C1365
0.22U_0402_10V6K

2

+3VALW
@

VDD_33

2

1U_0402_6.3V6K

2

1

C1253

1

1U_0402_6.3V6K

2

2

C1252

2

1

180P_0402_50V8J

1U_0402_6.3V6K

180P_0402_50V8J

2

1

C1257

1

C1249

C1197

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C1194

1

C1193

2

C1191

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C1192

C1202

C1201

C1200

2

1

2
R582

1
0_0603_5%

0_0402_5%

2
UAPUF

C1232

1

180P_0402_50V8J

2

1U_0402_6.3V6K

2

1

C1255

2

1

1U_0402_6.3V6K

@

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1

1

C1254

2

C1256

C1161

0.1U_0402_16V7K ESDP@

1

C1373

2

2

1

2

C1233

1

180P_0402_50V8J

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C1240

1U_0402_6.3V6K

2

1

C1239

1U_0402_6.3V6K

2

1

C1238

1U_0402_6.3V6K

10U_0603_6.3V6M

2

1

C1237

C1236

1

+0.95VALW

2

AL10
AL11

+1.5VS

2

B1
B2

+1.8VALW

VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23

L13
VDDCR_NB_2 L17
VDDCR_NB_3 N11
VDDCR_NB_4 N13
VDDCR_NB_5 N17
VDDCR_NB_6 R11
VDDCR_NB_7 R13
VDDCR_NB_8 R17
VDDCR_NB_9 U13
VDDCR_NB_10 U17
VDDCR_NB_11 W13
VDDCR_NB_12 W17
VDDCR_NB_13 AA13
VDDCR_NB_14 AA17
VDDCR_NB_15 AC13
VDDCR_NB_16 AC17
VDDCR_NB_17 AE15
VDDCR_NB_18 AE17
VDDCR_NB_19 AE19
VDDCR_NB_20 AG17
VDDCR_NB_21 AG21

2

180P_0402_50V8J

2

1

C1245

1

1U_0402_6.3V6K

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

VDDIO_AZ_ALW_1

AL13
AM13
AR5
AU4
AV7
AW5

1

AE11
AE13
AJ11
AJ13

+0.95VALW
2

VDD_18_ALW_1

VDD_18_1

VDD_18_ALW_2

VDD_18_2

VDD_33_ALW_1

VDD_33_1

VDD_33_ALW_2

VDD_33_2
VDD_095_1

VDD_095_USB3_DUAL_2
VDD_095_USB3_DUAL_3
VDD_095_USB3_DUAL_4
VDD_095_ALW_1
VDD_095_ALW_2
VDD_095_ALW_3
VDD_095_ALW_4

VDD_095_GFX_2 W10

AN4

+APU_CORE_NB

+1.8VS

+3VS
+0.95VS

A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31

UAPUH
GND

VSS_1

VSS_63

VSS_2

VSS_64

VSS_3

VSS_65

VSS_4

VSS_66

VSS_5

VSS_67

VSS_6

VSS_68

VSS_7

VSS_69

VSS_8

VSS_70

VSS_9

VSS_71

VSS_10

VSS_72

VSS_11

VSS_73

VSS_12

VSS_74

VSS_13

VSS_75

VSS_14

VSS_76

VSS_15

VSS_77

VSS_16

VSS_78

VSS_17

VSS_79

VSS_18

VSS_80

VSS_19

VSS_81

VSS_20

VSS_82

VSS_21

VSS_83

VSS_22

VSS_84

VSS_23

VSS_85

VSS_24

VSS_86

VSS_25

VSS_87

VSS_26

VSS_88

VSS_27

VSS_89

VSS_28

VSS_90

VSS_29

VSS_91

VSS_30

VSS_92

VSS_31

VSS_93

VSS_32

VSS_94

VSS_33

VSS_95

VSS_34

VSS_96

VSS_35

VSS_97

VSS_36

VSS_98

VSS_37

VSS_99

VSS_38

VSS_100

VSS_39

VSS_101

VSS_40

VSS_102

VSS_41

VSS_103

VSS_42

VSS_104

VSS_43

VSS_105

VSS_44

VSS_106

VSS_45

VSS_107

VSS_46

VSS_108

VSS_47

VSS_109

VSS_48

VSS_110

VSS_49

VSS_111

VSS_50

VSS_112

VSS_51

VSS_113

VSS_52

VSS_114

VSS_53

VSS_115

VSS_54

VSS_116

VSS_55

VSS_117

VSS_56

VSS_118

VSS_57

VSS_119

VSS_58

VSS_120

VSS_59

VSS_121

VSS_60

VSS_122

VSS_61

VSS_123

VSS_62

VSS_124

J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W11
W15
W19
W25

W29
W39
W41
Y1
Y2
AA3
AA7
AA8
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE3
AE7
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ3
AJ7
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL3
AL8
AL15
AL17
AL19
AL25
AL29

VSS_188

VSS_127

VSS_189

VSS_128

VSS_190

VSS_129

VSS_191

VSS_130

VSS_192

VSS_131

VSS_193

VSS_132

VSS_194

VSS_133

VSS_195

VSS_134

VSS_196

VSS_135

VSS_197

VSS_136

VSS_198

VSS_137

VSS_199

VSS_138

VSS_200

VSS_139

VSS_201

VSS_140

VSS_202

VSS_141

VSS_203

VSS_142

VSS_204

VSS_143

VSS_205

VSS_144

VSS_206

VSS_145

VSS_207

VSS_146

VSS_208

VSS_147

VSS_209

VSS_148

VSS_210

VSS_149

VSS_211

VSS_150

VSS_212

VSS_151

VSS_213

VSS_152

VSS_214

VSS_153

VSS_215

VSS_154

VSS_216

VSS_155

VSS_217

VSS_156

VSS_218

VSS_157

VSS_219

VSS_158

VSS_220

VSS_159

VSS_221

VSS_160

VSS_222

VSS_161

VSS_223

VSS_162

VSS_224

VSS_163

VSS_225

VSS_164

VSS_226

VSS_165

VSS_227

VSS_166

VSS_228

VSS_167

VSS_229

VSS_168

VSS_230

VSS_169

VSS_231

VSS_170

VSS_232

VSS_171

VSS_233

VSS_172

VSS_234

VSS_173

VSS_235

VSS_174

VSS_236

VSS_175

VSS_237

VSS_176

VSS_238

VSS_177

VSS_239

VSS_178

VSS_240

VSS_179

VSS_241

VSS_180

VSS_242

VSS_181

VSSBG_DAC

VSS_182

VBURN

VSS_183

PSEN

AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29

2

3

VSS_184
VSS_185
VSS_186

FT3 REV 0.51

A6@

FT3 REV 0.51

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P
A6@

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

+0.95VS_APU_GFX

4

A6-6400 AM6400ITJ44JBA 2.4G BGA 769P

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

VSS_187

VSS_126

FT3 REV 0.51

Issued Date

A

VSS_125

VDD_095_GFX_3 AA10

VDDBT_RTC_G

A6@

VDD_18_ALW

AM15
AM17

AG23
VDD_095_2 AG27
VDD_095_3 AJ21
VDD_095_4 AJ27
VDD_095_5 AL21
VDD_095_6 AL23
VDD_095_7 AL27
VDD_095_8 AM23
VDD_095_9 AM25

VDD_095_USB3_DUAL_1

@

VDD_095_ALW

A2
A3
B3
C3

VDD_095_GFX_1 U10

+RTCBATT_R

+APU_CORE

VDDIO_AZ_ALW_2

VDD_18_4

C1248

1

C1246

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

2

1

C1250

1

C1244

C1160

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C1222

1U_0402_6.3V6K

2

1

VDDIO_MEM_S_4

VDD_18_3

+1.8VALW

C1219

1U_0402_6.3V6K

2

1

C1217

VDD_095_USB3_DUAL

1

C1220

@

2

180P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C1218

1

C1221

2

C1214

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

2

1

VDDIO_MEM_S_3

1

+3VALW_APU

C1216

C938

C937

4

2

1

VDDIO_MEM_S_2

VDD_18

+1.8VS

+0.95VALW

1

VDDCR_CPU_2 L23
VDDCR_CPU_3 L25
VDDCR_CPU_4 L27
VDDCR_CPU_5 L29
VDDCR_CPU_6 N21
VDDCR_CPU_7 N23
VDDCR_CPU_8 N27
VDDCR_CPU_9 R21
VDDCR_CPU_10 R23
VDDCR_CPU_11 R27
VDDCR_CPU_12 U21
VDDCR_CPU_13 U23
VDDCR_CPU_14 U27
VDDCR_CPU_15 W21
VDDCR_CPU_16 W23
VDDCR_CPU_17 W27
VDDCR_CPU_18 AA21
VDDCR_CPU_19 AA23
VDDCR_CPU_20 AA27
VDDCR_CPU_21 AC21
VDDCR_CPU_22 AC23
VDDCR_CPU_23 AC27
VDDCR_CPU_24 AE21
VDDCR_CPU_25 AE23
VDDCR_CPU_26 AE27
VDDCR_NB_1

@

+0.95VALW

VDDCR_CPU_1 L21

VDDIO_MEM_S_1

+1.8VALW/+1.8VS OF APU

C933

2

2

0.1U_0402_16V7K ESDP@

2

1

C1372

1

1U_0402_6.3V6K

10U_0603_6.3V6M

2

C1203

C936

2

1

1

@

VDD_095_GFX

L22
2
1
FBMA-L11-201209-121LMA50T_0805

2

180P_0402_50V8J

@

180P_0402_50V8J

2

1

C1259

180P_0402_50V8J

2

1

C1258

2

1

C1231

1

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

2

C1230

C1207

C1208

1

180P_0402_50V8J

1U_0402_6.3V6K

2

C1213

1

C1260

2

1U_0402_6.3V6K

2

1

C1206

@

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C1204

1U_0402_6.3V6K

2

1

C1205

10U_0603_6.3V6M

1U_0402_6.3V6K

2

1

C1199

1

2

1

+0.95VS_APU_GFX

VDD_095
C1198

10U_0603_6.3V6M

2

C934

C935

1

2

1

@

+0.95VALW/+0.95VS OF APU
+0.95VS

1

180P_0402_50V8J

0.1U_0402_16V7K

2

C1210

1

180P_0402_50V8J

2

C1211

0.1U_0402_16V7K

2

1

C932

0.1U_0402_16V7K

2

1

C930

1

C931

2

0.1U_0402_16V7K

0.1U_0402_16V7K

2

1

C929

1

C928

2

0.1U_0402_16V7K

2

1

0.1U_0402_16V7K

2

1

C927

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C926

1

C923

C949

10U_0603_6.3V6M

2

C925

C924

1

@

3

+1.5VS

VDDIO_MEM_S

UAPUG
GND

POWER

J35
L32
L37
N35
R31
R37
U32
U35
W31
W32
W37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35

+1.35V

VDD_33_ALW

PLANE SPLIT

R131
KABINI@
2
TEMPINRETUNE 1

1

VDDIO_AZ_ALW
(Could be S0 or S5 power rail)
+1.35V

AP2138N-1.5TRG1_SOT23-3

Need use+3.3V transfer to +1.5V LDO to APU side for Beema

+3VALW/+3VS OF APU
+3VALW_APU

2

1

需需LDO轉1.5V, 20130930 added

+3VS

1

1

1

+RTCBATT

VDDCR_NB

1

Need OPEN

Vin
GND

for Clear CMOS

INTEGRATED GPU POWER OF APU

1

CLRP1 @
SHORT PADS

Vout

2

@

+APU_CORE_NB

2 10K_0402_5%

1

1
1

1

2

2

1

R93

2

C1190

2

1U_0402_6.3V6K

2

1

C1189

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C1188

1

C1187

2

1U_0402_6.3V6K

2

1

C1186

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C1184

1

C1183

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C1182

1

C1181

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C1180

C1179

1

W=20mils

2

+RTCBATT_R

3

+RTCBATT

1

+RTCBATT

C810
680P_0603_50VK

VDDBT_RTC_G

VDDCR_CPU

+APU_CORE

E

+RTCBATT_3V

RTC OF APU

CORE POWER OF APU

D

C811
0.1U_0603_25V7K

A

C

D

FT3 PWR/GND
Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

8

of

46

B

+1.35V

<10,5>
<10,5>

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ16
DDRAB_SDQ17

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDM7
DDRAB_SDQ58
DDRAB_SDQ59
R69 1

2 10K_0402_5%

+3VS

1

+0.675VS
4

205
R70

+3VS

GND2

DDRA_ODT1

2

2

+1.35V

+1.35V

R65
1K_0402_1%
DDRA_CLK1 <5>
DDRA_CLK1# <5>
DDRAB_SBS1#
DDRAB_SRAS#

R66
1K_0402_1%
+VREF_CA

+VREF_DQ

<10,5>
<10,5>

DDRA_SCS0# <5>
DDRA_ODT0 <5>
DDRA_ODT1

R68
1K_0402_1%

R67
1K_0402_1%

<5>

15mil
+VREF_CA
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQS5#
DDRAB_SDQS5

1

2

1

2

3

DDRAB_SDQS5# <10,5>
DDRAB_SDQS5 <10,5>

DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDM6
DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQS7# <10,5>
DDRAB_SDQS7 <10,5>

DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT#

MEM_MAB_EVENT# <10,5>
APU_SDATA0 <10,7>
APU_SCLK0 <10,7>

+0.675VS

206
4

10K_0402_5%
2

C1135
2.2U_0603_6.3V6K

GND1

DDRA_SCS0#
DDRA_ODT0

2

1

@

DDRAB_SMA2
DDRAB_SMA0

DDRAB_SBS1#
DDRAB_SRAS#

2

1

4.7U_0603_6.3V6K

<10,5>
<10,5>

DDRAB_SMA6
DDRAB_SMA4

DDRA_CLK1
DDRA_CLK1#

0.1U_0402_16V4Z

DDRAB_SDQ48
DDRAB_SDQ49

2

1

C1127

DDRAB_SDQ42
DDRAB_SDQ43

@

2

C1126

DDRAB_SDM5

@

2

1

0.1U_0402_16V4Z

DDRAB_SDQ40
DDRAB_SDQ41

@

2

1

C1167

DDRAB_SDQ34
DDRAB_SDQ35
3

@

2

1

VREF for DIMM1,2

DDRAB_SMA11
DDRAB_SMA7

C1134

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQS4#
DDRAB_SDQS4

2

1

<5>

0.1U_0402_25V6K

<10,5>
<10,5>

DDRA_CKE1

DDRAB_SMA15
DDRAB_SMA14

1000P_0402_50V7K

DDRAB_SDQ32
DDRAB_SDQ33

DDRA_CKE1

2

1

0.1U_0402_16V4Z

DDRA_SCS1#

@

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

2

1

C1123

<5>

DDRAB_SMA13
DDRA_SCS1#

DDRAB_SDQ30
DDRAB_SDQ31

2

1

0.1U_0402_16V4Z

DDRAB_SWE#
DDRAB_SCAS#

DDRAB_SDQS3# <10,5>
DDRAB_SDQS3 <10,5>

1

C1122

DDRAB_SBS0#

<10,5> DDRAB_SWE#
<10,5> DDRAB_SCAS#

DDRAB_SDQS3#
DDRAB_SDQS3

1

0.1U_0402_16V4Z

DDRAB_SMA10
DDRAB_SBS0#

DDRAB_SDQ28
DDRAB_SDQ29

C1121

<10,5>

DDRA_CLK0
DDRA_CLK0#

DDRAB_SDQ22
DDRAB_SDQ23

0.1U_0402_16V4Z

<5>
<5>

DDRA_CLK0
DDRA_CLK0#

+0.675VS

C1120

DDRAB_SMA3
DDRAB_SMA1

+1.35V

DDRAB_SDM2

0.1U_0402_16V4Z

DDRAB_SMA8
DDRAB_SMA5

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDRAB_SDQ20
DDRAB_SDQ21

C1119

DDRAB_SMA12
DDRAB_SMA9

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

+1.35V/+0.675VS OF DIMM1

0.1U_0402_16V4Z

DDRAB_SBS2#

MEM_MAB_RST# <10,5>

DDRAB_SDQ14
DDRAB_SDQ15

C1118

2

DDRA_CKE0
DDRAB_SBS2#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRAB_SDM1
MEM_MAB_RST#

0.1U_0402_16V4Z

<5>
<10,5>

DDRA_CKE0

<10,5>

1

C1117

DDRAB_SDQ26
DDRAB_SDQ27

DDRAB_SMA[0..15]

<10,5>
<10,5>

DDRAB_SDQ12
DDRAB_SDQ13

0.1U_0402_16V4Z

DDRAB_SDM3

DDRAB_SMA[0..15]

0.1U_0402_16V4Z

DDRAB_SDQ24
DDRAB_SDQ25

DDRAB_SDM[0..7]

DDRAB_SDQ6
DDRAB_SDQ7

C1116

DDRAB_SDQ18
DDRAB_SDQ19

DDRAB_SDQS0# <10,5>
DDRAB_SDQS0 <10,5>

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

C1115

DDRAB_SDQS2#
DDRAB_SDQS2

DDRAB_SDQS0#
DDRAB_SDQS0

DDRAB_SDQ[0..63]

C1114

<10,5>
<10,5>

DDRAB_SDQS2#
DDRAB_SDQS2

DDRAB_SDQ4
DDRAB_SDQ5

2

DDRAB_SDQ8
DDRAB_SDQ9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

1

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

2

DDRAB_SDQ2
DDRAB_SDQ3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

1

DDRAB_SDM0

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

DDRAB_SDQ0
DDRAB_SDQ1

C1142

C1176

1000P_0402_50V7K

0.1U_0402_25V6K

2

1

E

2

15mil
1

JDIMM2
Reverse Type
Near CPU

+1.35V
JDIMM2

D

1

+VREF_DQ

C

1

A

1

1

2

2

C1136
0.1U_0402_16V4Z

ARGOS_DS2RK-20401-TP4B
ME@ SP070014D00

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_A H:4mm

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.



Date:

A

B

C

D

DDR3 SODIMM-I Socket
Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

9

of

46

A

B

+VREF_DQ

+1.35V

1

<5,9>
<5,9>

1

C1143

C1177

2

1000P_0402_50V7K

0.1U_0402_25V6K

1

DDRAB_SDQ0
DDRAB_SDQ1
DDRAB_SDM0

2

DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ16
DDRAB_SDQ17

<5,9>
<5,9>

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDM7
DDRAB_SDQ58
DDRAB_SDQ59
R71 1

2 10K_0402_5%

1

2 10K_0402_5%

+3VS
R72

+0.675VS

205
207

4

GND1
BOSS1

2

1

2

4.7U_0603_6.3V6K

DDRAB_SDQ48
DDRAB_SDQ49

@

2

1

0.1U_0402_16V4Z

DDRAB_SDQ42
DDRAB_SDQ43

2

1

C1158

DDRAB_SDM5

2

1

C1175

DDRAB_SDQ40
DDRAB_SDQ41

@

2

1

1

@

1
+

2

C250
330U_D3_2.5VY_R6M

2

@

2

DDRAB_SMA6
DDRAB_SMA4
DDRAB_SMA2
DDRAB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRAB_SBS1#
DDRAB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 <5>
DDRB_CLK1# <5>
DDRAB_SBS1#
DDRAB_SRAS#

<5,9>
<5,9>

DDRB_SCS0# <5>
DDRB_ODT0 <5>
DDRB_ODT1

<5>

15mil
+VREF_CA
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQS5#
DDRAB_SDQS5

1

2

1

C1174

DDRAB_SDQ34
DDRAB_SDQ35
3

2

1

DDRAB_SMA11
DDRAB_SMA7

C1139

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQS4#
DDRAB_SDQS4

2

1

<5>

0.1U_0402_25V6K

<5,9>
<5,9>

+1.35V

DDRAB_SMA15
DDRAB_SMA14

1000P_0402_50V7K

DDRAB_SDQ32
DDRAB_SDQ33

DDRB_CKE1

2

1

0.1U_0402_16V4Z

DDRB_SCS1#

@
DDRB_CKE1

2

1

0.1U_0402_16V4Z

<5>

DDRAB_SMA13
DDRB_SCS1#

DDRAB_SDQS3# <5,9>
DDRAB_SDQS3 <5,9>

DDRAB_SDQ30
DDRAB_SDQ31

2

1

C1172

<5,9> DDRAB_SWE#
<5,9> DDRAB_SCAS#

DDRAB_SDQS3#
DDRAB_SDQS3

1

0.1U_0402_16V4Z

DDRAB_SWE#
DDRAB_SCAS#

DDRAB_SDQ28
DDRAB_SDQ29

C1171

DDRAB_SBS0#

DDRAB_SDQ22
DDRAB_SDQ23

0.1U_0402_16V4Z

DDRAB_SMA10
DDRAB_SBS0#

+0.675VS

C1170

<5,9>

DDRB_CLK0
DDRB_CLK0#

+1.35V

DDRAB_SDM2

0.1U_0402_16V4Z

<5>
<5>

DDRB_CLK0
DDRB_CLK0#

DDRAB_SDQ20
DDRAB_SDQ21

C1169

DDRAB_SMA3
DDRAB_SMA1

<5,9>

+1.35V/+0.675VS OF DIMM2

0.1U_0402_16V4Z

DDRAB_SMA8
DDRAB_SMA5

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

MEM_MAB_RST# <5,9>

DDRAB_SDQ14
DDRAB_SDQ15

C1168

DDRAB_SMA12
DDRAB_SMA9

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDRAB_SDM1
MEM_MAB_RST#

0.1U_0402_16V4Z

DDRAB_SBS2#

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRAB_SMA[0..15]

1

C1165

DDRB_CKE0
DDRAB_SBS2#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

<5,9>

DDRAB_SDQ12
DDRAB_SDQ13

0.1U_0402_16V4Z

<5>
<5,9>

DDRB_CKE0

DDRAB_SMA[0..15]

<5,9>

DDRAB_SDM[0..7]

DDRAB_SDQ6
DDRAB_SDQ7

C1162

DDRAB_SDQ26
DDRAB_SDQ27

DDRAB_SDQS0# <5,9>
DDRAB_SDQS0 <5,9>

E

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

0.1U_0402_16V4Z

DDRAB_SDM3

DDRAB_SDQS0#
DDRAB_SDQS0

DDRAB_SDQ[0..63]

0.1U_0402_16V4Z

DDRAB_SDQ24
DDRAB_SDQ25

DDRAB_SDQ4
DDRAB_SDQ5

C1132

DDRAB_SDQ18
DDRAB_SDQ19

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

C1155

DDRAB_SDQS2#
DDRAB_SDQS2

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

C1133

<5,9>
<5,9>

DDRAB_SDQS2#
DDRAB_SDQS2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

D

JDIMM1
Standard Type
Near User

+1.35V
JDIMM1

15mil

2

C

2

3

DDRAB_SDQS5# <5,9>
DDRAB_SDQS5 <5,9>

DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDM6
DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQS7# <5,9>
DDRAB_SDQS7 <5,9>

DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT# <5,9>
APU_SDATA0 <7,9>
APU_SCLK0 <7,9>
+0.675VS

206
208

GND2
BOSS2

4

ARGOS_DS2SK-20401-TP4B
ME@
SP070014E00

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_B H:4mm

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.



Date:

A

B

C

D

DDR3 SODIMM-II Socket
Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

10

of

46

1

2

3

UV1A

4

5

PX@

AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF

A

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

AF30
AE31

PCIE_ATX_C_GRX_P0
PCIE_ATX_C_GRX_N0

AE29
AD28

PCIE_ATX_C_GRX_P1
PCIE_ATX_C_GRX_N1

AD30
AC31

PCIE_ATX_C_GRX_P2
PCIE_ATX_C_GRX_N2

AC29
AB28

PCIE_ATX_C_GRX_P3
PCIE_ATX_C_GRX_N3

AB30
AA31
AA29
Y28
Y30
W31
W29
V28

B

V30
U31
U29
T28

R29
P28
P30
N31
N29
M28
M30
L31
L29
K30

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

NC#V30
NC#U31

NC#W24
NC#W23

NC#U29
NC#T28

NC#V27
NC#U26

NC#T30
NC#R31
NC#R29
NC#P28

PCI EXPRESS INTERFACE

T30
R31

PCIE_RX0P
PCIE_RX0N

NC#U24
NC#U23
NC#T26
NC#T27

PCIE_GTX_ARX_P0
PCIE_GTX_ARX_N0

AG29
AF28

PCIE_GTX_ARX_P1
PCIE_GTX_ARX_N1

AF27
AF26
AD27
AD26

.1U_0402_16V7K
.1U_0402_16V7K

2
2

1 PX@
1 PX@

CV1
CV2

.1U_0402_16V7K
.1U_0402_16V7K

2
2

1 PX@
1 PX@

CV3
CV4

PCIE_GTX_ARX_P2
PCIE_GTX_ARX_N2

.1U_0402_16V7K
.1U_0402_16V7K

2
2

1 PX@
1 PX@

CV5
CV6

PCIE_GTX_ARX_P3
PCIE_GTX_ARX_N3

.1U_0402_16V7K
.1U_0402_16V7K

2
2

1 PX@
1 PX@

CV7
CV8

NC#T24
NC#T23

NC#N29
NC#M28

NC#P27
NC#P26

NC#M30
NC#L31

NC#P24
NC#P23
NC#M27
NC#N26

PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_N0

<6>
<6>

PCIE_GTX_C_ARX_P1
PCIE_GTX_C_ARX_N1

<6>
<6>

PCIE_GTX_C_ARX_P2
PCIE_GTX_C_ARX_N2

<6>
<6>

PCIE_GTX_C_ARX_P3
PCIE_GTX_C_ARX_N3

<6>
<6>

AC25
AB25
Y23
Y24
AB27
AB26
Y27
Y26

B

W24
W23
V27
U26
U24
U23

No Use GPU Display Port outpud

T26
T27

UV1F

NC#P30
NC#N31

NC#L29
NC#K30

AH30
AG31

PX@

+VGA_CORE

T24
T23
VARY_BL
DIGON

P27
P26
P24
P23

TXCAP_DPA3P
TXCAM_DPA3N

M27
N26

TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N

C

<6>
<6>

CLK_PCIE_GPU
CLK_PCIE_GPU#

CLK_PCIE_GPU
CLK_PCIE_GPU#

AK30
AK32

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TX2P_DPA0P
TX2M_DPA0N
+0.95VGS

+3VGS

PXS_RST#

APU_PCIE_RST#

2

PXS_RST#

1

2 1K_0402_5%

B

AL27
Y

A

TEST_PG

PCIE_CALR_RX

RV1

2 1.69K_0402_1%

RV3

1 PX@

2 1K_0402_1%

4

GPU_RST#

TXCBP_DPB3P
TXCBM_DPB3N

PERSTB

TX3P_DPB2P
TX3M_DPB2N

3

216-0841018 A0 SUN PRO S3
RV4
100K_0402_5%
PX@

TX4P_DPB1P
TX4M_DPB1N

2

MC74VHC1G08DFT2G_SC70-5

AB11
AB12

0_0402_5%
0_0402_5%

2 TOPAZ@
TOPAZ@1 RV177
2 TOPAZ@1
TOPAZ@ RV176

FOR TOPAS CORE POWER USE

AL15
AK14
AH16
AJ15
AL17
AK16

C

AH18
AJ17
AL19
AK18

TMDP

AA22

1

<7>

1 PX@

1 PX@

G

APU_PCIE_RST#

RV2

Y22

UV2 PX@

P

5

N10

<24,29,31,7>

NC_TXOUT_L3P
NC_TXOUT_L3N

CALIBRATION

PCIE_CALR_TX

A

TX5P_DPB0P
TX5M_DPB0N
NC_TXOUT_U3P
NC_TXOUT_U3N

AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23

216-0841018 A0 SUN?PRO S3

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

JET/TOPAL(1/5)_PCIE/DP
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
5

11

of

46

1

2

3

4

5

AC6
AC5

33_0402_5% JET@
RV16
4.7K_0402_5%
TOPAZ@

2 0_0402_5% GPU_SVD
2 0_0402_5% GPU_SVC

3.3V TO 1.8V LEVEL SHIF
For JET/SUN to support SVI2 reaulator
DNI for TOPAZ

FB_VDDCI

1

PLL_ANALOG_IN

NC#J8

GPIO19_CTF

2

<7>

VGA_CLKREQ#

1
@
RV26
1 PX@
RV27

1

+3VGS

+3VGS
C

+VGA_CORE

1 4.7K_0402_5% THM_ALERT#

2
5.11K_0402_5%
2
1K_0402_5%

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN

L6
L5
L3
L1
K4
K7
AF24

RV169 1 TOPAZ@2 0_0402_5%

AB13
W8
W9
W7
AD10
AJ9
AL9

TV24

1

RV171 1 TOPAZ@2 0_0402_5%

TV22

2

1

RV175 1 TOPAZ@2 0_0402_5%
1
PX_EN
TV25

GPU_GPIO5

2

AC14
AB16

AC16

10K_0402_5%

Y4
W5

Cap (nF)

AA3 PLL_ANALOG_OUT
Y2

1
PX@ 2
RV17
16.2K_0402_1%

G
AVSSN#AJ25
B
AVSSN#AG25
DAC1

HSYNC
VSYNC

AM26
AK26

+3VGS

AL25
AJ25

@

AH24
AG25

RV371
4.7K_0402_5%
@

AH26
AJ27

RSET
AVDD
AVSSQ
VDD1DI
VSS1DI

AD22

RV372
4.7K_0402_5%
PX@

AG24
AE22

FutureASIC/SEYMOUR/PARK

CEC_1
RSVD#AK12
RSVD#AL11
RSVD#AJ11

D

GENLK_CLK
GENLK_VSYNC

PS_0
PS_1
PS_2

HPD1
PX_EN

PS_3
TS_A

DDC1CLK
DDC1DATA

DDC2CLK
DDC2DATA
XTALIN
XTALOUT
XTALOUT

2 10K_0402_5%
2 10K_0402_5%

AM28
AK28
AC22
AB22

1
2
PX@

1

NC

XTALIN
XTALOUT

AUX2P
AUX2N

XO_IN
XO_IN2

NC#AD20
NC#AC20
NC#AE16
NC#AD16

OSC

OSC
NC

3

SEYMOUR/FutureASIC

2

27MHZ 10PF +-10PPM 7V27000050
SJ10000FH00
CV19
10P_0402_50V8J

TO EXTERNAL THERMAL SENSOR

1

RV180 1
RV181 1

REMOTE1+
REMOTE1-

RV33 1 JET@
CV20
10P_0402_50V8J

2 0_0402_5%
2 0_0402_5%

2 10K_0402_5%

GPIO28

@
LV4 1

2 0_0402_5%
1

2

THERM_D+ T4
THERM_D- T2

Enable MLPS

+1.8VGS

2
PX@

<25>
<25>

+TSVDD

R5
AD17
AC17

DPLUS
DMINUS

1
2
1
2
1
2
1

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

2

PS_1[5] STRAP_TX_DEEMPH_EN

00

82nF

01

PS_2[3:1]=000

10nF

10

PS_2[5:4]=00

NC

11

+1.8VGS

Strap Name :
PS_2[1] N/A

@
RV57
8.45K_0402_1%

PS_2[2] N/A

2

PS_2[3] STRAP_BIOS_ROM_EN

RV373
4.7K_0402_5%

1

PX@
RV19
4.75K_0402_1%

2

3

1

GPU_WAKEB

+1.8VGS

PS_3[3:1]=000
PS_3[5:4]=11

PS_2[5] N/A

AE23
AD23

Strap Name :
PS_3[1] BOARD_CONFIG[0] (Memory ID)

X76@
RV21
8.45K_0402_1%

OBFF OPTION:
reserve by AMD request

Pull down for none OBFF design

PS_3

AM12
AK12
AL11
AJ11

PS_3[2] BOARD_CONFIG[1] (Memory ID)

SVI2_SVD RV166 1 TOPAZ@2 0_0402_5% GPU_SVD
SVI2_SVT RV167 1 TOPAZ@2 0_0402_5% GPU_SVT
SVI2_SVC RV168 1 TOPAZ@2 0_0402_5% GPU_SVC

GPU_SVD
GPU_SVT
GPU_SVC

<41>
<41>
<41>

1

PS_3[3] BOARD_CONFIG[2] (Memory ID)
PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
X76@
RV24
2K_0402_1%

@

2

PS_3[5] AUD_PORT_CONN_PINSTRAP[2]

AL13
AJ13
AG13
AH12

Memory ID

AC19

PS_0

AD19

PS_1

AE17

PS_2

AE20

PS_3

(default)

AE19

DDCVGACLK
DDCVGADATA

THERMAL

Memory Type

Configuration

Size

R5174

R5169

000

SA000068U00

Samsung K4W2G1646E-BC1A

001

SA000067500

Micron MT41J128M16JT-093G:K

1GB

NC

4.75K

X7641338L31

1GB

8.45K

2K

010

SA00006H400

X7641338L32

Hynix H5TC2G63FFR-11C

1GB

4.53K

2K

011

X7641338L33

SA000068R00

Samsung K4W4G1646B-HC11

2GB

6.98K

4.99K

100

X7641338L34

SA000065D00

Micron MT41k256M16HA-107G:E 2GB

4.53K

4.99K

X7641338L35

OPTIAN FOR 3.3V tolerance VR,
Check with VR vendor

AD2
AD4
AC11
AC13

+VGA_CORE
RV178 1 TOPAZ@2 0_0402_5%
RV179 1 TOPAZ@2 0_0402_5%

+1.8VGS

FOR TOPAZ CORE POWER USE

AD13
AD11
AD20
AC20

RV185
1 TOPAZ@2
0_0402_5%

RV164
10K_0402_5%
TOPAZ@
FB_GND RV37 1 TOPAZ@2 0_0402_5%
FB_VDDC RV51 1 TOPAZ@2 0_0402_5%
ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN

GPU_VDD_RUN_FB_L
GPU_VDD_SEN
<41>

<41>

AE16
AD16

SVI2_SVD
SVI2_SVC

+3VGS
RV186
1 @
2
0_0402_5%
RV163
10K_0402_5%
@

D

AC1
AC3
GPU_VDD_RUN_FB_L

RV30 1 @

2 0_0402_5%

GPU_VDD_SEN

RV32 1 @

2 0_0402_5%

@
RV165
10K_0402_5%

TOPAZ@
RV184
10K_0402_5%

+VGA_CORE

GPIO28_FDO
TSVDD
TSVSS

CV21
1U_0402_6.3V6K
PX@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
216-0841018 A0 SUN PRO ?S3

2014/03/03

Deciphered Date

2015/03/03

Title

JET/TOPAL(2/5)_MSIC

Date:

2

X76 P/N

AE6
AE5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

B

PS_2[4] STRAP_BIF_VGA_DIS

1
PX@
CV32

2N7002H_SOT23-3
@ QV20

DBG_VREFG

AUX1P
AUX1N

RV29 1 PX@
RV31 1 PX@

PS_1[3] N/A
PX@
RV14
4.75K_0402_1%

C

SWAPLOCKA
SWAPLOCKB
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE
NC#AJ9
NC#AL9

YV1 PX@

4

@

1

FOR TOPAZ
JET/SUN DOESN'T HAVE NATIVE SVI2

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
NC#AF24

DDC/AUX

10K_8P4R_5%

PS_1[2] TRAP_BIF_CLK_PM_EN

Bitd [5:4]

680nF

J8

PS_1[1] STRAP_BIF_GEN3_EN_A

2

R
AVSSN#AK26

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
SMBDATA
SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
GPIO_29
GPIO_30
CLKREQB

PLL/CLOCK

XTALIN

PS_1

+3VGS

JTAG_TRSTB
JTAG_TDI
JTAG_TMS
JTAG_TCK

RV28
1M_0402_5%
PX@

111

PS_2

+3VGS

RPV1 @
8
7
6
5

NC

Strap Name :

@
RV9
8.45K_0402_1%

Capacitor Divider Lookup Lable

SCL
SDA

JTAG_TDO

VGA_AC_BATT
pull up
1
2
3
4

4.75k

PS_1[5:4]=11

CV31

10K_0402_5%
@

110

+1.8VGS

PS_1[3:1]=000

1

U6
U10
T10
U8
VGA_SMB_DA2
U7
VGA_SMB_CK2
T9
GPU_GPIO5
T8
GPU_GPIO6
T7
P10
P4
P2
N6
N5
N3
Y9
N1
GPU_VID3
M4
THM_ALERT#_R R6
W10
M2
GPIO19_CTF
P8
GPU_VID1
P7
N8
AK10
AM10
N7

FOR TOPAS CORE POWER USE
+3VGS

RV20 1

10k

A

2

2 0_0402_5%
RV194 1 PX@
RV173 1 TOPAZ@2 0_0402_5%

+1.8VGS

RV22
10K_0402_5%
@

3.4k

D

THM_ALERT#

THM_ALERT#

101

PS_0[5] AUD_PORT_CONN_PINSTRAP[0]

1

2

RB751V_SOD323

<41>

<25>

5.62k

2

2

1

@ DV1 1

VCIN1_AC_IN

+VGA_CORE

FOR TOPAS CORE POWER USE

100

3.24k

S

GPU_PROCHOT#

4.99k

0.68U_0402_10V

RV170 1 TOPAZ@2 0_0402_5%
RV174 1 TOPAZ@2 0_0402_5%

RV172 1 TOPAZ@2 0_0402_5%

RV58 1 @

NC#AA3
NC#Y2

011

4.53k

W3
V2

PS_0[4] N/A

G

<26,27,35>
GPU_PROCHOT#

CV17
.1U_0402_16V7K
2
TOPAZ@

RV18 2 PX@

NC#U1
NC#W1
NC#U3
NC#Y6
NC#AA1

010

4.99k

CV33
0.68U_0402_10V

2

+VGA_CORE

FOR TOPAS CORE POWER USE

RV10
10K_0402_5%
TOPAZ@

RV15
1K_0402_5%
1
2
TOPAZ@

RV13 2
10K_0402_5%
@

NC#W3
NC#V2

DPC

+3VGS

REAK CURRENT CONTROL ( Topaz only )

1

NC#AA5
NC#AA6

001

2k

6.98k

0402 1% resistors are equired

V4
U5

PS_0[3] ROM_CONFIG[2]
PX@
RV7
2K_0402_1%

I2C

R1
R3

1

NC#AC5
NC#AC6

NC#Y4
NC#W5
U1
W1
U3
Y6
AA1

B

GPU_GPIO6

NC#V4
NC#U5

2k

4.53k

2

1 .1U_0402_16V7K

JET@

TV18

1

NC#W6
NC#V6

8.45k

2

CV196

TV23

AA5
AA6

RV11
4.7K_0402_5%
TOPAZ@

1

RV182 1 @
RV183 1 @

JET@
CV180
10U_0603_6.3V6M
2
1

2

W6
V6

AK8
AL7

000

1

2

+1.8VGS

AJ7
AH6

4.75k

1

JET@

NC#AK8
NC#AL7

AK6
AM5

NC

1

10K_0402_5%
1 DIR

NC#AJ7
NC#AH6

AK5
AM3

PS_0[2] ROM_CONFIG[1]

1

JET@
33_0402_5%
1
2 GPU_SVD
1
2 GPU_SVC

RV134
10K_0402_5%
@

1

1

RV136 2

DPB

@

2

8
7 RV131
6 RV130
4

GPU_VID3
GPU_VID1
+3VGS

NC#AK6
NC#AM5

AK3
AK1

CV30

Bitd [3:1]

R_pd (ohm)

2

VCCB
B1
B2
GND

SN74LVC2T45DCTR_SM8
RV135
10K_0402_5%
JET@

NC#AK5
NC#AM3

R_pu (ohm)

1

VCCA
A1
A2
DIR

DVO

FOR TOPAZ,JET/SUN DOESN'T HAVE

JET@

2

2

GPU_VID3
GPU_VID1

1
2
3
5

NC#AK3
NC#AK1

Resistor Divider Lookup Lable

AH3
AH1

1

2

1
UV13

JET@ 33_0402_5%
2GPU_VID3_GPIO_15
RV162 1
1
2GPU_VID1_GPIO_20
RV81
JET@ 33_0402_5%DIR

CV182
.1U_0402_16V7K

2

1

RV161
10K_0402_5%
JET@

1

.1U_0402_16V7K
JET@

RV71
10K_0402_5%
@

1

CV195

JET@

2

2

2

+1.8VGS

NC#AH3
NC#AH1

PS_0

2

+3VGS +3VGS

2

+3VGS

1

A

DPA

AG3
AG5

0.68U_0402_10V

VGA_SMB_CK2

QV9B
ME2N7002D1KW-G 2N_SOT363-6
@

NC#AG3
NC#AG5

2 1

4

DBG_DATA16
DBG_DATA15
DBG_DATA14
DBG_DATA13
DBG_DATA12
DBG_DATA11
DBG_DATA10
DBG_DATA9
DBG_DATA8
DBG_DATA7
DBG_DATA6
DBG_DATA5
DBG_DATA4
DBG_DATA3
DBG_DATA2
DBG_DATA1
DBG_DATA0

0.68U_0402_10V

N9
L9
AE9
Y11
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

PS_0[1] ROM_CONFIG[0]

PX@
RV12
8.45K_0402_1%

AF2
AF4

2

3

EC_SMB_CK2

NC#AF2
NC#AF4

VGA_SMB_DA2

2

<25,27,5>

PS_0[5:4]=11

5

QV9A
ME2N7002D1KW-G 2N_SOT363-6
@

Strap Name :

U?

1

1

+1.8VGS

PS_0[3:1]=001

PX@

1

2

6

EC_SMB_DA2

UV1B
RV158
47K_0402_5%
@

2

RV157
47K_0402_5%
@

2
<25,27,5>

1

1

+3VGS

3

4

Rev
1.0

LA-B291P

Monday, March 03, 2014
5

Sheet

12

of

46

1

2

3

4

5

+1.35VS to +1.35VGS

UV1E

+1.35V

+1.35VGS arises after VGA_CORE

2

CV24

CV23

1U_0402_6.3V6K
PX@
2

4
2

1

QV10B
ME2N7002D1KW-G 2N_SOT363-6
PX@

PX@
CV27
0.1U_0402_16V7K

CV29

U?
NC/DP POWER

DP_VDDR#AG15
DP_VDDR#AG16
DP_VDDR#AF16
DP_VDDR#AG17
DP_VDDR#AG18
DP_VDDR#AG19
DP_VDDR#AF14

NC#AE11
NC#AF11
NC#AE13
NC#AF13
NC#AG8
NC#AG10

DP_VDDC#AG20
DP_VDDC#AG21
DP_VDDC#AF22
DP_VDDC#AG22
DP_VDDC#AD14

NC#AF6
NC#AF7
NC#AF8
NC#AF9

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

NC#AE1
NC#AE3
NC#AG1
NC#AG6
NC#AH5
NC#AF10
NC#AG9
NC#AH8
NC#AM6
NC#AM8
NC#AG7
NC#AG11

DPAB_CALR

NC#AE10

AE11
AF11
AE13
AF13
AG8
AG10

AF6
AF7
AF8
AF9

AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11

AE10

added on 9/28

VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+0.95VGS

2

U1895V
1
2
@

DGPU_PWR_EN

2

R1642

1 0_0402_5% DGPU_PWR_EN_R

3
4

VL

5
2

GPU_PWR_EN R1643

1 0_0402_5%

@

+1.8VALW

6
7

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13

+0.95VGS_LS

12

1
PX@
2200P_0402_50V7K

2
C28

1
PX@
2200P_0402_50V7K

2
C27

RV5

1

2 0_0805_5%

@

2

1U_0402_6.3V6K

M6
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11
AA11
M12
N11
V11

216-0841018 A0 SUN PRO? S3

1

11
10

1

@

AG14
AH14
AM14
AM16
AM18
AF23
AG23
AM20
AM22
AM24
AF19
AF20
AE14

2

AF17

9
8

1

+1.8VGS_LS RV6

2 0_0805_5%

15

1

APE8990GN3B DFN 14P
@

1

PX@
C32
0.1U_0402_16V7K

+1.8VGS
@

2

C29

1

.1U_0402_16V7K
PX@

1U_0402_6.3V6K
PX@

CV28

PX@

+1.8VALW TO +1.8VGS
+0.95VALW TO +0.95VGS
Load switch

+0.95VALW

2

AG20
AG21
AF22
AG22
AD14

2

B

AG15
AG16
AF16
AG17
AG18
AG19
AF14

+0.95VGS

1

PX@
DP POWER

1

10U_0603_6.3V6M
PX@

3 1

4

ME2N7002D1KW-G 2N_SOT363-6
QV10A

UV1G
RV34
10_0603_5%
@

5 GPU_PWR_EN#

1

6

2 PX@

PX@
2
1.35VSG_GATE 1
RV36 100K_0402_5%

2
1

2 PX@

1

CV22

2 PX@

1

1U_0402_6.3V6K

GPU_PWR_EN#

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

No Use GPU Display Port outpud
+1.8VGS

CV26

PX@
2
200K_0402_5%

UV14
PX@
AP4800BGM-HF 1N SO-8
1
2
3
10U_0603_6.3V6M

1
RV35

B+

8
7
6
5
CV25

.1U_0402_16V7K

A

1

PX@

U?

+1.35VGS

PX@
C31
0.1U_0402_16V7K

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

VSS_MECH
VSS_MECH
VSS_MECH

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A

B

A32
AM1
AM32

PX@

C30

?
216-0841018 A0 SUN PRO
S3

C

1U_0402_6.3V6K

2

C

+3VS to +3VS_VGA
+5VALW

RV40
470_0603_5%
@

1

D
QV17
DGPU_PWR_EN#

PX@RV43
PX@
RV43

@
2

R1640

<27>

3VGS_PWR_EN

R1641

2

D

1 0_0402_5% 2
G
3

DGPU_PWR_EN

<27,41>

@

S

PX@
5

GPU_PWR_EN

PX@
RV41
100K_0402_5%

2
G
2N7002H_SOT23-3

QV11B
@

20K_0402_5%
1

20K_0402_5%

3

RV42 PX@
D

3

CV37

2

S

PX@
QV18
2N7002H_SOT23-3

1

PX@
CV38
.1U_0402_16V7K

PX@
2

DGPU_PWR_EN#

QV11A

2

2
RV39
470_0603_5%

RV53
470_0603_5%
@

2

RV56
470_0603_5%
@

DGPU_PWR_EN#

QV21A
@

5

DGPU_PWR_EN#

QV21B
@

D

DGPU_PWR_EN#

2

1 0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

+0.95VGS

ME2N7002D1KW-G 2N_SOT363-6
4
3 1

@

4

CV36

1

2

2

PX@

+5VALW

<27,7>

GPU_PWR_EN#

ME2N7002D1KW-G 2N_SOT363-6
1
6 1

1U_0603_10V6K
1

2

2

1

ME2N7002D1KW-G 2N_SOT363-6

4.7U_0603_6.3V6K

1

1

QV16
LP2301ALT1G_SOT23-3

1

@
3

PX@

ME2N7002D1KW-G 2N_SOT363-6
1
6 1

RV38
100K_0402_5%

PX@

2

+3VGS

+1.8VGS

+VGA_CORE

2
+3VALW

2

3

4

Title

JET/TOPAL(3/5)_PWR/GND
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
5

13

of

46

2

2

2

13mA

+1.8VGS

B

1.5A

5(3@)

5

5

1

0

+3VGS
1U_0402_6.3V6K
PX@

VDDR1

25mA

0.1uF

100mA

1

1

0

MPLL_PVDD

130mA

2

1

0

SPLL_PVDD

75mA

0

1

0

(300mA) 0

0

0

VDDR4

V12
Y12
U12

2

+1.8VGS

90mA

@

0

+TSVDD

13mA

0

1

0

1

1

0

LV1 1

0

+3VGS
VDDR3

10uF
25mA

0

1

1uF
1

2

1

2

1

0.1uF

VDDR4
VDDR4
VDDR4

BIF_VDDC
BIF_VDDC

1
L8

+1.8VGS
2

75mA

@
LV2 1

2 0_0402_5%

1

2

H7

LV3 1

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

SPLL_PVDD

100mA

@

2

2 0_0402_5%

+SPLL_VDDC

H8
J7

0

1

2

SPLL_VDDC
SPLL_PVSS

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
AA12
M11
N12
U11

CV48
1

2

1

2

1

2

1

2

1

2

B

+VGA_CORE

VGA_CORE Cap in power side sheet

21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))

R21
U21

+0.95VGS

0.8A

C

M13
M15
M16
M17
M18
M20
M21
N20

1

2

VGA_CORE Cap in power side sheet

1

2

1

2

+VGA_CORE

ISOLATED
CORE I/O

1
+0.95VGS

+0.95VGS

+PCIE_VDDC: 1A

MPLL_PVDD

+SPLL_PVDD

1U_0402_6.3V6K
PX@
CV46

+DP_VDDC

1

VDDR3
VDDR3
VDDR3
VDDR3

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

2

PLL

+MPLL_PVDD

10U_0603_6.3V6M
PX@
CV42

C

+DP_VDDR

2 0_0603_5%

1U_0402_6.3V6K
PX@
CV43

1

10U_0603_6.3V6M
PX@
CV41

0

1U_0402_6.3V6K
PX@
CV40

13mA

10U_0603_6.3V6M
PX@
CV39

VDD_CT

CORE

POWER

PCIE_PVDD

1

1U_0402_6.3V6K
PX@

1uF

VDD_CT
VDD_CT
VDD_CT
VDD_CT
I/O

AA17
AA18
AB17
AB18

.1U_0402_16V7K
PX@
CV90

10uF

CV56

2

+1.8VGS

LEVEL
TRANSLATION

AA20
AA21
AB20
AB21

0.01uF
CV55

+1.35VGS

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

1

CV54

2

2

CV53

0.1uF

2

1

1U_0402_6.3V6K
@

1uF

2

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

CV52

10uF

2

AM30

1U_0402_6.3V6K
PX@

1

2

NC#AB23
NC#AC23
NC#AD24
NC#AE24
NC#AE25
NC#AE26
NC#AF25
NC#AG26

1U_0402_6.3V6K
PX@

1

2

1

PCIE_PVDD

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

1U_0402_6.3V6K
PX@

0

2

1

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

+1.35VGS

+PCIE_PVDD:
50mA (PCIE2.0) +1.8VGS
100mA (PCIE3.0)

CV51

100mA

2

1

.1U_0402_16V7K
PX@
CV85

0

2

1

.1U_0402_16V7K
PX@
CV86

1(1@)

2

1

.1U_0402_16V7K
PX@
CV89

0

2

1

.1U_0402_16V7K
PX@
CV82

0.8A

2

1

1U_0402_6.3V6K
PX@
CV81

BIF_VDDC

2

1

1U_0402_6.3V6K
PX@
CV79

0

1

1U_0402_6.3V6K
PX@
CV78

5(1@)

1

1U_0402_6.3V6K
PX@
CV77

1

1

1U_0402_6.3V6K
PX@
CV76

1A

1

10U_0603_6.3V6M
@
CV87

PCIE_VDDC

+

@

1

10U_0603_6.3V6M
PX@
CV83

0.1uF

1

10U_0603_6.3V6M
@
CV80

1uF

10U_0603_6.3V6M
@
CV74

10uF

1

U?

MEM I/O

1A
1

PX@

1U_0402_6.3V6K
PX@

3.5A

+0.95VGS

SPLL_VDDC

UV1D

CV47

+1.35VGS

10U_0603_6.3V6M
PX@

3

CV50

4

CV49

16

TBD

1U_0402_6.3V6K
PX@

7

A

10U_0603_6.3V6M
PX@

0.1uF

CV62

1uF

5

PCIE

VDDCI

2.2uF

10U_0603_6.3V6M
PX@
CV88

VDDC

10uF

4

.1U_0402_16V7K
PX@
CV84

+VGA_CORE

3

220U_B2_2.5VM_R35
CV75

A

2

1U_0402_6.3V6K
@

1

216-0841018 A0 SUN PRO S3?

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

JET/TOPAL(4/5)_PWR
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P
Sheet

Monday, March 03, 2014
5

14

of

46

2

<16,17>
A

M_MA[15..0]

<16,17>

M_DQM[7..0]

<16,17>

M_DQS[7..0]

<16,17>

M_DQS#[7..0]

PX@
UV1C

M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]

1
2

PX@
RV44
40.2_0402_1%

1

B

1

PX@
CV65
1U_0402_6.3V6K

2

2

1

+1.35VGS

1

2

PX@
RV45
40.2_0402_1%

1

PX@
CV66
1U_0402_6.3V6K
2

RV52

C

DRAM_RST

1

2

2 120_0402_1%

J25
K25

L10

DRST

PX@
RV50
5.1K_0402_1%

1

@
CV67
68P_0402_50V8J

2

RV54 @
RV55 @

1
1

2 51.1_0402_1%
2 51.1_0402_1%

CV69
CV70

@1
@
@
@1

2 .1U_0402_16V7K
2
.1U_0402_16V7K

K8
L7

Route 50ohms single-ended/100ohm diff and keep short
debug only, for clock observation,if not need, DNI.

5

U?

GDDR5/DDR3

GDDR5/DDR3

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA0_8/MAA_13
MAA0_9/MAA_15
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
MAA1_8/MAA_14
MAA1_9/RSVD
WCKA0_0/DQMA0_0
WCKA0B_0/DQMA0_1
WCKA0_1/DQMA0_2
WCKA0B_1/DQMA0_3
WCKA1_0/DQMA1_0
WCKA1B_0/DQMA1_1
WCKA1_1/DQMA1_2
WCKA1B_1/DQMA1_3

MVREFDA
MVREFSA
NC#J25
MEM_CALRP0

EDCA0_0/QSA0_0
EDCA0_1/QSA0_1
EDCA0_2/QSA0_2
EDCA0_3/QSA0_3
EDCA1_0/QSA1_0
EDCA1_1/QSA1_1
EDCA1_2/QSA1_2
EDCA1_3/QSA1_3
DDBIA0_0/QSA0_0B
DDBIA0_1/QSA0_1B
DDBIA0_2/QSA0_2B
DDBIA0_3/QSA0_3B
DDBIA1_0/QSA1_0B
DDBIA1_1/QSA1_1B
DDBIA1_2/QSA1_2B
DDBIA1_3/QSA1_3B
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1

2

PX@
CV68
120P_0402_50V8J

1 PX@

PX@
RV49
10_0402_1%
2
1
1

<16,17>

PX@
RV48
49.9_0402_1%
1
2

K26
J26

+MVREFDA
+MVREFSA

2

PX@
RV47
100_0402_1%

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

+1.35VGS

PX@
RV46
100_0402_1%

4

M_DA[63..0]

M_DA[63..0]

<16,17>

3

MEMORY INTERFACE

1

DRAM_RST

WEA0B
WEA1B

K17
J20
H23
G23
G24
H24
J19
K19
G20
L17

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA13
M_MA15

J14
K14
J11
J13
H11
G11
J16
L15
G14
L16

M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1
M_MA14

E32
E30
A21
C21
E13
D12
E3
F4

M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7

H28
C27
A23
E19
E15
D10
D6
G5

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

H27
A27
C23
C19
C15
E9
C5
H4

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

L18
K16

VRAM_ODT0
VRAM_ODT1

H26
H25

M_CLK0
M_CLK#0

G9
H9

M_CLK1
M_CLK#1

G22
G17

M_RAS#0
M_RAS#1

G19
G16

M_CAS#0
M_CAS#1

H22
J22

M_CS0B#0

G13
K13

M_CS1B#0

K20
J17

M_CKE0
M_CKE1

G25
H10

M_WE#0
M_WE#1

A

M_BA2
M_BA0
M_BA1

<16,17>
<16,17>
<16,17>

B

VRAM_ODT0
VRAM_ODT1

<16>
<17>

M_CLK0 <16>
M_CLK#0 <16>
M_CLK1 <17>
M_CLK#1 <17>
M_RAS#0
M_RAS#1

<16>
<17>

M_CAS#0
M_CAS#1

<16>
<17>

M_CS0B#0
M_CS1B#0

<16>
<17>
C

M_CKE0
M_CKE1

<16>
<17>

M_WE#0
M_WE#1

<16>
<17>

CLKTESTA
CLKTESTB
216-0841018 A0 SUN PRO S3
?

Place close to GPU (within 25mm)
and place componment close to each other

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

JET/TOPAL(5/5)_MEM
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
5

15

of

46

1

2

3

4

5

DDR3L Memory Channel Rank 0:A0
+1.35VGS

M_DQS#[7..0]

PX@
RV63
4.99K_0402_1%

<15,17>
<15,17>
<15,17>

1

2

PX@
RV102
40.2_0402_1%

PX@
RV103
40.2_0402_1%

2

B

1

M_CLK0
M_CLK#0

1

2

M8
H1

+FBA_VREF0

1
2

PX@
RV75
4.99K_0402_1%

PX@
RV62
4.99K_0402_1%

UV5

1

2

PX@
CV72
.1U_0402_16V7K

M_BA0
M_BA1
M_BA2

<15>
<15>
<15>

M_CLK0
M_CLK#0
M_CKE0

<15>
<15>
<15>
<15>
<15>

VRAM_ODT0
M_CS0B#0
M_RAS#0
M_CAS#0
M_WE#0

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK0
M_CLK#0
M_CKE0

J7
K7
K9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_DA8
M_DA14
M_DA10
M_DA13
M_DA9
M_DA12
M_DA11
M_DA15

D7
C3
C8
C2
A7
A2
B8
A3

M_DA5
M_DA3
M_DA6
M_DA2
M_DA4
M_DA1
M_DA7
M_DA0

A

UV6
M8
H1

+FBA_VREF1

1

PX@
RV66
4.99K_0402_1%

2

PX@
CV71
.1U_0402_16V7K

+1.35VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35VGS

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK0
M_CLK#0
M_CKE0

J7
K7
K9

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2

CK
CK
CKE/CKE0

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_DA18
M_DA19
M_DA16
M_DA20
M_DA21
M_DA23
M_DA17
M_DA22

D7
C3
C8
C2
A7
A2
B8
A3

M_DA31
M_DA27
M_DA30
M_DA24
M_DA28
M_DA25
M_DA29
M_DA26
+1.35VGS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35VGS
B

VRAM_ODT0 K1
L2
M_CS0B#0
J3
M_RAS#0
K3
M_CAS#0
L3
M_WE#0

PX@
CV73
0.01U_0402_16V7K

<15,17>

M_DQS1
M_DQS0

F3
C7

M_DQM1
M_DQM0

E7
D3

M_DQS#1
M_DQS#0

G3
B7

DRAM_RST

DRAM_RST

T2

1

L8
J1
L1
J9
L9

SINGLE RANK:RV102,RV103 install 40.2 ohm(SR@)
DUAL RANK:RV102,RV103 install 80.6 ohm(DR@)

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

PX@
RV111
243_0402_1%

ODT/ODT0
CS/CS0
RAS
CAS
WE

C

A1
A8
C1
C9
D2
E9
F1
H2
H9

VRAM_ODT0 K1
L2
M_CS0B#0
J3
M_RAS#0
K3
M_CAS#0
L3
M_WE#0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_DQS2
M_DQS3

F3
C7

M_DQM2
M_DQM3

E7
D3

M_DQS#2
M_DQS#3

G3
B7

DRAM_RST

T2
L8

1

M_DQS#[7..0]

M_DQS[7..0]

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

PX@
RV110
243_0402_1%
2

<15,17>

+1.35VGS

M_DQM[7..0]

1

M_DQS[7..0]

2

<15,17>

M_MA[15..0]

1

M_DQM[7..0]

2

<15,17>

M_DA[63..0]

1

M_DA[63..0]
M_MA[15..0]

2

A

<15,17>
<15,17>

96-BALL
SDRAM DDR3
H5TC2G63FFR-11C_FBGA96
X76@

+1.35VGS

DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

C

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CV124
@
1U_0402_6.3V6K

2

CV122
PX@
1U_0402_6.3V6K

1

CV123
PX@
1U_0402_6.3V6K

2

CV126
PX@
1U_0402_6.3V6K

1

CV121
PX@
1U_0402_6.3V6K

2

CV120
PX@
1U_0402_6.3V6K

1

CV117
PX@
1U_0402_6.3V6K

2

+1.35VGS

CV116
PX@
10U_0603_6.3V6M

1

CV115
@
10U_0603_6.3V6M

2

CV125
@
.1U_0402_16V7K

1

CV113
PX@
1U_0402_6.3V6K

2

CV112
PX@
1U_0402_6.3V6K

1

CV109
PX@
1U_0402_6.3V6K

2

CV108
PX@
1U_0402_6.3V6K

1

CV107
PX@
1U_0402_6.3V6K

CV106
PX@
1U_0402_6.3V6K

CV105
PX@
10U_0603_6.3V6M

2

DQSL
DQSU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

96-BALL
SDRAM DDR3
H5TC2G63FFR-11C_FBGA96
X76@

+1.35VGS

1

ODT/ODT0
CS/CS0
RAS
CAS
WE

1

2

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

JET/TOPAL_DDR3L_A1 Rank 0
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
5

16

of

46

1

2

3

4

5

DDR3L Memory Channel Rank 0:A1
+1.35VGS

1

1

+1.35VGS

PX@
RV119
4.99K_0402_1%

<15,16>

M_DQM[7..0]

<15,16>

M_DQS[7..0]

<15,16>

M_DQS#[7..0]

M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]

PX@
RV126
4.99K_0402_1%

M_DQS#[7..0]

1

<15,16>
<15,16>
<15,16>

PX@
RV140
40.2_0402_1%

2

2

PX@
RV139
40.2_0402_1%

1

M_CLK1
M_CLK#1

B

1

2

1

2

PX@
CV119
.1U_0402_16V7K

PX@
CV154
0.01U_0402_16V7K

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

<15,16>

M_BA0
M_BA1
M_BA2

M_CLK1
M_CLK#1
M_CKE1
VRAM_ODT1
M_CS1B#0
M_RAS#1
M_CAS#1
M_WE#1

DRAM_RST

M8
H1

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK1
M_CLK#1
M_CKE1

J7
K7
K9

VRAM_ODT1
M_CS1B#0
M_RAS#1
M_CAS#1
M_WE#1

K1
L2
J3
K3
L3

M_DQS7
M_DQS6

F3
C7

M_DQM7
M_DQM6

E7
D3

M_DQS#7
M_DQS#6

G3
B7

DRAM_RST

T2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA58
M_DA61
M_DA59
M_DA62
M_DA56
M_DA63
M_DA57
M_DA60

D7
C3
C8
C2
A7
A2
B8
A3

M_DA52
M_DA51
M_DA55
M_DA50
M_DA54
M_DA49
M_DA53
M_DA48

UV4
+FBA_VREF3

M8
H1

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_BA0
M_BA1
M_BA2

M2
N8
M3

M_CLK1
M_CLK#1
M_CKE1

J7
K7
K9

VRAM_ODT1
M_CS1B#0
M_RAS#1
M_CAS#1
M_WE#1

K1
L2
J3
K3
L3

M_DQS4
M_DQS5

F3
C7

M_DQM4
M_DQM5

E7
D3

M_DQS#4
M_DQS#5

G3
B7

DRAM_RST

T2

1

PX@
RV127
4.99K_0402_1%

2

PX@
CV118
.1U_0402_16V7K

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

L8

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

J1
L1
J9
L9

PX@
RV138
243_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_DA34
M_DA38
M_DA35
M_DA39
M_DA32
M_DA37
M_DA33
M_DA36

D7
C3
C8
C2
A7
A2
B8
A3

M_DA47
M_DA43
M_DA46
M_DA42
M_DA44
M_DA41
M_DA45
M_DA40

A

+1.35VGS

+1.35VGS

+1.35VGS

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.35VGS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

B

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CV148
PX@
1U_0402_6.3V6K

2

CV193
@
1U_0402_6.3V6K

1

CV147
@
.1U_0402_16V7K

2

CV146
PX@
1U_0402_6.3V6K

1

CV145
PX@
1U_0402_6.3V6K

2

CV144
PX@
1U_0402_6.3V6K

1

CV141
PX@
1U_0402_6.3V6K

2

C

+1.35VGS

CV139
PX@
10U_0603_6.3V6M

1

CV138
@
10U_0603_6.3V6M

2

CV136
PX@
1U_0402_6.3V6K

1

CV135
PX@
1U_0402_6.3V6K

2

CV134
@
.1U_0402_16V7K

1

CV164
PX@
1U_0402_6.3V6K

2

CV132
PX@
1U_0402_6.3V6K

1

CV158
PX@
1U_0402_6.3V6K

2

CV152
PX@
1U_0402_6.3V6K

CV128
PX@
10U_0603_6.3V6M

1

BA0
BA1
BA2

96-BALL
SDRAM DDR3
H5TC2G63FFR-11C_FBGA96
X76@

96-BALL
SDRAM DDR3
H5TC2G63FFR-11C_FBGA96
X76@

C

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.35VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

2

SINGLE RANK:RV139,RV140 install 40.2 ohm(SR@)
DUAL RANK:RV139,RV140 install 80.6 ohm(DR@)

J1
L1
J9
L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

2

1
PX@
RV137
243_0402_1%

VREFCA
VREFDQ

+1.35VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9

1

L8

VREFCA
VREFDQ

E3
F7
F2
F8
H3
H8
G2
H7

2

M_MA[15..0]

+FBA_VREF2

2

<15,16>

M_DA[63..0]

2

M_DA[63..0]

1

<15,16>

2

A

UV3

1

PX@
RV118
4.99K_0402_1%

1

2

D

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

Title

JET/TOPAL_DDR3L_A2 Rank 0
Size Document Number
Custom
Date:

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
5

17

of

46

5

4

3

2

1

D

D

C

C

B

B

A

A

Title
Reserved
Size
A
Date:
5

4

3

Document Number
LA-B291P
Monday, March 03, 2014
2

Rev
1.0
Sheet

18

of
1

46

5

4

3

2

1

D

D

C

C

B

B

A

A

Title
Reserved
Size
A
Date:
5

4

3

Document Number
LA-B291P
Monday, March 03, 2014
2

Rev
1.0
Sheet

19

of
1

46

5

4

3

2

1

LCD POWER CIRCUIT
CMOS Camera
+3VS

W=60mils

W=60mils

SA00006Y800

3

(40 MIL)

1

R119 CMOS@
150K_0402_5%

1

<27>

10U
1

C129
CMOS@
0.1U_0402_16V7K

2

@
C130
10U_0603_6.3V6M

CMOS_ON#
1

R120
100K_0402_5%

2

(40 MIL)

G

2

G524B1T11U SOT-23 5P

1

1

3

OC

+3VS_CMOS

D

EN

CMOS@
Q4
PMV65XP_SOT23-3
S

4

APU_ENVDD

D

1 0_0603_5%

2

2

GND
<5>

+LCDVDD_CONN_R R139 2

2

1

OUT

4.7U_0603_6.3V6K

IN

C128

5

+LCDVDD_CONN

@

U5

C132

2

+3VS
D

CMOS@
0.1U_0402_16V7K

C

C

VGA LCD/PANEL BD. Conn.

+3VS

<27>

1

BKOFF#

B

+LEDVDD

Y
A

4

B+

R121 1

DISPOFF#
1

2

3

2

From EC

2

ENBKL

P

<27,5>

G

From APU

5

@
U15

U74AHC1G08G-AL5-R_SOT353-5

R124
10K_0402_5%

@

2

1

1

R211
100K_0402_5%

2 0_0805_5%

@

@
C133
4.7U_0805_25V6-K

JLVDS1
R123 1

2 0_0402_5%

APU_INVT_PWM
1

<5>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

<5>

R126 1

EDP_HPD

2 0_0402_5% EDP_HPD_R

R826
100K_0402_5%

2

Camera

<6>

USB20_P3

<6>

USB20_N3

(60 MIL)

EDP_AUXN
EDP_AUXP

C134 1
C135 1

2
2

0.1U_0402_16V7K EDP_AUXN_C
0.1U_0402_16V7K EDP_AUXP_C

<5>
<5>

EDP_TXP0
EDP_TXN0

C136 1
C137 1

2
2

0.1U_0402_16V7K EDP_TXP0_C
0.1U_0402_16V7K EDP_TXN0_C

<5>
<5>

EDP_TXP1
EDP_TXN1

FHD@ C138 1
FHD@ C139 1

2
2

0.1U_0402_16V7K EDP_TXP1_C
0.1U_0402_16V7K EDP_TXN1_C

<5>
<5>

2 0_0402_5%

COM FI_ INPAQ MCM2012D900FBE ET88
1
2 USB20_P3_R
1
2
4

+LCDVDD_CONN

eDP

1

R128
100K_0402_5%

R125 1

DISPOFF#
EDP_HPD_R

@

2

B

Touch Screen (reserved)

USB20_P0_R
USB20_N0_R

3

4

3
L6
USB20_N3_R
EMIU@
SM070002Z00
1
2
R127
0_0402_5%

<27>

TS_DISABLE#
+3VS

R122 1
R270 2

2 0_0402_5%
TS_RST#
1 0_0603_5% +3VS_TS

+3VS_CMOS

CMOS

Camera
DMIC

<30>
<30>

USB20_N3_R
USB20_P3_R

DMIC_CLK
DMIC_DAT
+3VS

<6>

USB20_P0

<6>

USB20_N0

Touch Screen

4

2

1 0_0402_5%

SM070002Z00
@
L7

4

3

3

2

B

A

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1
0_0402_5%

Date:

5

41
42
43
44
45
46

USB20_P0_R

1
2
USB20_N0_R
1
2
COM FI_ INPAQ MCM2012D900FBE ET88

R130

G1
G2
G3
G4
G5
G6

E-T_0871K-F40N-00L
ME@
SP010011Z00

A

R129

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

4

3

2

EDP CONN / Camera
Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

20

of

46

A

EMIP@

EMIP@

EMIP@

C1094
6P_0402_50V8

EMIP@

C1103
6P_0402_50V8

C1104
6P_0402_50V8

1

EMIP@

EMIP@

C1107
6P_0402_50V8

2

DAC_BLU
DAC_GRN
DAC_RED

2

1
2
3
4

2

RP22
8
7
6
5

1

BLUE

1

1

DAC_BLU

2

DAC_BLU

1

GREEN

1

<5>

DAC_GRN

E

RED

2

DAC_GRN

1

<5>

D

FCM1608CF-121T03 0603
2
EMIP@ 1
L36
FCM1608CF-121T03 0603
2
EMIP@ 1
L37
FCM1608CF-121T03 0603
2
EMIP@ 1
L38

DAC_RED

2

DAC_RED

C

1

<5>

B

C1105
6P_0402_50V8

C1106
6P_0402_50V8

150_0804_8P4R_1%

+3VS
2

2

RP1
1
2
3
4

CRT_DDC_DATA
CRT_DDC_CLK
CRT_DDC_DAT_CONN
CRT_DDC_CLK_CONN

+5V_Display

8
7
6
5
4.7K_8P4R_5%

+5VS

+5V_Display

1
C529
0.1U_0402_16V7K

U25
2

1
2

+3VS

3

7
1
C537
0.1U_0402_16V7K

2

<5>

CRT_DDC_DATA

<5>

CRT_DDC_CLK

<5>

CRT_VSYNC

<5>

CRT_HSYNC

10
11
13

VCC_SYNC

BYP

VCC_VIDEO

VIDEO1

VCC_DDC

VIDEO2

DDC_IN1

VIDEO3

DDC_IN2

DDC_OUT1

SYNC_IN1

DDC_OUT2

SYNC_IN2

SYNC_OUT1

8

1
C23

2
0.22U_0402_10V6K

JCRT1

3

RED

4

GREEN

CRT_DDC_DAT_CONN
GREEN

5

BLUE

JVGA_HS
BLUE

9

CRT_DDC_DAT_CONN

JVGA_VS

12

CRT_DDC_CLK_CONN

CRT_DDC_CLK_CONN

14

JVGA_VS_U

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T49

RED

T58

3

G
G

16
17

EMIP@
15

R106 1

2 22_0402_5%

JVGA_VS

2 22_0402_5%

JVGA_HS

C-K_80443-5K1-152
ME@

TPD7S019-15DBQR_SSOP16

16

JVGA_HS_U

R107 1

R106 R107 for EMI

U25 have embeded ESD protection, and place it near CRT connector.
4

1

2

@

1

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

@

DC060006H00

10P_0402_50V8J

SYNC_OUT2

C412

GND

C411

6

10P_0402_50V8J

EMIP@

2014/03/03

Deciphered Date

2015/03/03

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

CRT CONN
Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

21

of

46

5

4

3

2

ZZZ1

1

45@

HDMI Logo
RO0000003HM
D

D

<5>
<5>

+5V_Display

EMI

Near HDMI CONN
DP2_TXN3

HDMI@
2 .1U_0402_16V7K
C229 1

DP2_TXP3

HDMI@
2 .1U_0402_16V7K
C230 1

L8
1

HDMI_CLKN

4

HDMI_CLKP

U6
+5VS
2

2

4

1

HDMI_CLK-_CONN
1

3

3

HDMI_CLK+_CONN

.1U_0402_16V7K

<5>

DP2_TXN2

HDMI@
2 .1U_0402_16V7K
C231 1

HDMI_TX0N

1

DP2_TXP2

HDMI@
2 .1U_0402_16V7K
C232 1

L9

HDMI_TX0P

4

HDMI@

1

2

4

2

HDMI_TX0-_CONN

3

HDMI_TX0+_CONN

2

HDMI_TX1+_CONN

3

HDMI_TX1-_CONN

1

IN

C140
2

GND

C141

WCM-2012HS-900T

<5>

OUT

HDMI@

1

2

W=40mils

3

.1U_0402_16V7K

2

AP2330W-7_SC59-3

+3VS

For CRT and HDMI

3

WCM-2012HS-900T
HDMI_TX1P

1

DP2_TXN1

HDMI@
2 .1U_0402_16V7K
C234 1

L10 HDMI@

HDMI_TX1N

4

1

2

4

3

HDMI@ C
Q5
MMBT3904_NL_SOT23-3

DP2_TXP0

<5>

DP2_TXN0

HDMI@
2 .1U_0402_16V7K
C236 1

HDMI_TX2P

1

HDMI_TX2N

4

1

2

4

3

2

HDMI_TX2+_CONN

3

HDMI_TX2-_CONN

<5>

HDMI_DET

HDMIDAT_R
HDMICLK_R

@
R138
200K_0402_5%

HDMI@
R137
100K_0402_5%

HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN

2

WCM-2012HS-900T

JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_DET_R
+5V_Display

E

1

<5>

L11 HDMI@

HDMI@
R133
1
2
150K_0402_5%

HDMI_TX0+_CONN
HDMI_TX1-_CONN
+5V_Display

HDMI_TX1+_CONN
HDMI_TX2-_CONN
2 2.2K_0402_5%

HDMIDAT_R

R676 1

2 2.2K_0402_5%

HDMICLK_R

HDMI_TX2+_CONN

2
R660 2

1 4.7K_0402_5%

Q6A
HDMI@
ME2N7002D1KW-G 2N_SOT363-6

RP29

<5>

HDMI_CLK

<5>

HDMI_DATA

1

6

HDMICLK_R

HDMI_CLK
4

HDMIDAT_R
RP30

ESDU@
9 10

HDMICLK_R

8

HDMI_DET

7
6

6

D1
HDMIDAT_R

HDMI_TX0+_CONN

ESDU@
9 10

2

HDMICLK_R

HDMI_TX0-_CONN

8

4

HDMI_DET

HDMI_CLK+_CONN

7

HDMI_CLK-_CONN

6

6

1

1

9

2

7

4
5

5

3

3

8

D2
1

1

HDMI_TX0+_CONN

HDMI_TX1+_CONN

ESDU@
9 10

9

2

2

HDMI_TX0-_CONN

HDMI_TX1-_CONN

8

7

4

4

HDMI_CLK+_CONN

HDMI_TX2+_CONN

7

5

5

HDMI_CLK-_CONN

HDMI_TX2-_CONN

6

6

3

3

4
3
2
1
499 +-1% 8P4R
HDMI@

D3
1

1

HDMI_TX1+_CONN

9

2

2

HDMI_TX1-_CONN

7

4

4

HDMI_TX2+_CONN

5

5

HDMI_TX2-_CONN

3

3

8

YSCLAMP0524P_SLP2510P8-10-9

5
6
7
8

HDMI_CLKN
HDMI_CLKP
HDMI_TX0N
HDMI_TX0P

ESD
HDMIDAT_R

4
3
2
1
499 +-1% 8P4R
HDMI@

3

Q6B
HDMI@
ME2N7002D1KW-G 2N_SOT363-6

B

5
6
7
8

HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N

HDMI_DATA
5

1 4.7K_0402_5%

C

CONCR_099ATAC19NBLCNF
ME@
DC232001K00

+3VS

+3VS

R657 2

20
21
22
23

B

+3VS
1

R675 1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

D
Q7
HDMI@
2N7002H_SOT23-3

2
G
S

3

C

HDMI@
2 .1U_0402_16V7K
C235 1

2
B

3

WCM-2012HS-900T

2

HDMI@
2 .1U_0402_16V7K
C233 1

1

<5>

DP2_TXP1

1

<5>

8

YSCLAMP0524P_SLP2510P8-10-9

YSCLAMP0524P_SLP2510P8-10-9

ESD protection needs to be placed near connector side

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HDMI CONN
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

22

of

46

A

B

C

D

E

F

G

H

HDD
SATA HDD Conn.

Near Connector

JHDD1
<6>
<6>
<6>
<6>

SATA_ATX_DRX_P0
SATA_ATX_DRX_N0
SATA_DTX_C_ARX_N0
SATA_DTX_C_ARX_P0
R141 1

+3VS

1

<27>

C142
C143

2
2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_ATX_C_DRX_P0
SATA_ATX_C_DRX_N0

C144
C145

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_ARX_N0
SATA_DTX_ARX_P0

2 0_0805_5%

@

2
C1374

2 0_0402_5%

ESDU@
0.1U_0402_16V7K

HDD_DETECT#_R

R142 1

+5VS

2 0_0805_5% +5V_HDD

@

GND
RX+
RXGND
TXTX+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3V_HDD

R280 1

HDD_DETECT#

1
2
3
4
5
6
7

1

Near HDD

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

+5V_HDD

1

2

@
C146
1000P_0402_50V7K

1

2

2

GND1
GND2

23
24

ALLTO_C166KH-122H9-L
ME@
SP011310171

1
C147
.1U_0402_16V7K

1

C148
10U_0603_6.3V6M

ODD
2

2

+3VALW

FOR 15"

2

ODD Power Control

SATA ODD FFC Conn.

R151
100K_0402_5%
ZODD@

JODD1

1
+5VALW

+5VS

1

2 0_0805_5%

<6>
<6>

1

R147

<6>
<6>

+5V_ODD

NOZODD@

<7>
3

0_0402_5%

+5V_ODD

+5V_ODD

Q8
LP2301ALT1G_SOT23-3
ZODD@

2

2

ZODD@
R150
100K_0402_5%
1
2

1

1

OUT
IN

3

3

2

2
ZODD@

ODD_DA#

GND

ODD_EN

1
R285

1

G

<7>

SATA_DTX_C_ARX_N1
SATA_DTX_C_ARX_P1

ODD_PLUGIN#

SATA_DTX_ARX_N1
SATA_DTX_ARX_P1
ODD_DETECT#

D

S

ZODD@
R149
10K_0402_5%

1
2
3
4
5
6
7
8
9
10

SATA_ATX_C_DRX_P1_15
SATA_ATX_C_DRX_N1_15

SATA_ATX_DRX_P1
SATA_ATX_DRX_N1

2

GND
GND

2

11
12

ACES_88058-100N
ME@
SP010016C00

1
C149
0.01U_0402_16V7K
ZODD@

1
2
3
4
5
6
7
8
9
10

C150
10U_0603_6.3V6M

3

Q9
DTC124EKAT146_SC59-3
ZODD@

FOR 14"

SATA ODD Conn.
Near Connector
+3VS

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_ATX_C_DRX_P1_14
SATA_ATX_C_DRX_N1_14

SATA_DTX_C_ARX_N1 14@
SATA_DTX_C_ARX_P1 14@

C153 1
C154 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_ARX_N1_14
SATA_DTX_ARX_P1_14

2
R154
10K_0402_5%
ZODD@

ODD_DETECT#
+5V_ODD

1

ODD_DA#

D

S

ODD_DA#_EC

3

C151 1
C152 1

1

2

G

<27>

ODD_DA#_EC

@

JODD2

14@
14@

SATA_ATX_DRX_P1
SATA_ATX_DRX_N1

Q22
2N7002H_SOT23-3
2 0_0402_5%
@

<7>

1
ODD_DA#_APU
R284

ODD_DA#_APU

8
9
10
11
12
13

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND

GND
GND

14
15

ALLTO_C185S1-113H9-L
ME@
SP011312061

ZODD@
R282 1

1
2
3
4
5
6
7

2
0_0402_5%

4

4

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/03/03

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDD/ODD
Size
C
Date:

A

B

C

D

E

F

G

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet

23
H

of

46

A

B

C

D

E

1

1

NGFF for WLAN / BT(Key E)

+3VS

+3VS_WLAN

Support ISCT(Intel Smart Connect Technology)
R153 1

@

2 0_0805_5%

+3VS_WLAN
JWLAN1
<6>
<6>

BT

1
3
5
7
9
11
13
15
17
19
21
23

USB20_P5
USB20_N5

2

WLAN

<6>
<6>

PCIE_ATX_C_DRX_P2
PCIE_ATX_C_DRX_N2

<6>
<6>

PCIE_DTX_C_ARX_P2
PCIE_DTX_C_ARX_N2

<6> CLK_PCIE_WLAN
<6> CLK_PCIE_WLAN#
<7> WLAN_CLKREQ#
<7> APU_PCIE_WAKE#
<27,29>

LAN_WAKE#

R158 1
R160 1
R162 1

@

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

WLAN_CLKREQ#_R
APU_PCIE_WLAN_WAKE#

25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

GND
USB_D+
USB_DGND
SIDO_CLK
SDIO_CMD
SDO_DAT0
SDO_DAT1
SDO_DAT2
SDO_DAT3
SDIO_WAKE#
SDIO_RESET#

GND
PETP0
PETN0
GND
PERP0
PERN0
GND
REFCLKP0
REFCLKN0
GND
CLKEQ0#
PEWAKE0#
GND
RSRVD/PETP1
RSRVD/PETN1
GND
RSRVD/PERP1
RSRVD/PERN1
GND
RESERVED
RESERVED
GND

3.3VAUX
3.3VAUX
LED1#
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
LED2#
GND
UART_WAKE#
UART_RX

UART_TX
UART_CTS
UART_RTS
RESERVED
RESERVED
RESERVED
COEX3
COEX2
COEX1
SUSCLK
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DATA
I2C_CLK
ALERT
RESERVED
RESERVED
RESERVED
RESERVED
3.3VAUX
3.3VAUX

MTG77

MTG76

2

1

C155
4.7U_0603_6.3V6K

@

2

C156
.1U_0402_16V7K

2

24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

SUSCLK_R
APU_PCIE_RST#
BT_DISABLE_R

R155 1
R156 1

2 0_0402_5%
2 0_0402_5%

R157 1

2 0_0402_5%

R159 1
R161 1

2 0_0402_5%
2 0_0402_5%

EC_TX
EC_RX

<26,27>
<26,27>

RTC_CLK <7>
APU_PCIE_RST#
<11,29,31,7>
BT_OFF# <7>
EC_WL_OFF#
<27>

Note: The real behavior of BT_DISABLE are
BT_DISABLE=LOW, BT=OFF
BT_DISABLE=HIGH, BT=ON

68

3

R1647
100K_0402_5%
1

3

1

2

LCN_DAN05-67306-0102
ME@
SP070013F00

2
4
6
8
10
12
14
16
18
20
22

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

NGFF WLAN/BT
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

24

of

46

5

4

3

2

1

3 Channel
+3VGS
2

2

+3VS

PX@
R166
0_0402_5%

2

D

<12>

REMOTE1+
C159
2200P_0402_50V7K

GPU

Near DDR

REMOTE2+

REMOTE2-

2

2
B

<12>

REMOTE1-

2
1

C
Q12
MMST3904-7-F_SOT323-3

C161
2200P_0402_50V7K

E

3

C160
100P_0402_50V8J

1

1

1

1
R167
10K_0402_5%
@

U7

1
+3V_Thermal

1

REMOTE1+

2

REMOTE1-

3

REMOTE2+

4

REMOTE2-

5

2

2

@
C158
.1U_0402_16V7K

+3V_Thermal

SMSC thermal sensor
placed near JWLAN1

1

1

UMA@
R165
0_0402_5%

VDD

SMCLK

DP1

SMDATA

DN1

ALERT#

DP2

THERM#

DN2

10

EC_SMB_CK2

9

EC_SMB_DA2

D

EC_SMB_CK2

<12,27,5>

EC_SMB_DA2

<12,27,5>

8

THM_ALERT#

7

<12>

THERM#

6

GND

EMC1403-2-AIZL-TR_MSOP10

Address 1001_101xb

Placed near U7
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

2 Channel
+3V_Thermal

@
C329
.1U_0402_16V7K

C

SMSC thermal sensor
placed near JWLAN1

2

1
1
@
C251
2200P_0402_50V7K

1

2

C

@
U17

REMOTE1+

2

REMOTE1-

3

THERM#

4

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

8

EC_SMB_CK2

7

EC_SMB_DA2

6

THM_ALERT#

5

EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb

H2
HOLEA

H3
HOLEA

H17
HOLEA

H14
HOLEA

H5
HOLEA

H13
HOLEA

H15
HOLEA

Battery BD
H22
HOLEA

H23
HOLEA

H24
HOLEA

H8
HOLEA

B

H9
HOLEA

C162
10U_0603_6.3V6M

H_4P0

H_4P0

H_3P3

H_3P3

H_3P2

H_2P6N

H_2P6X4P0N H_2P6X4P0N

1

1

H_4P0

1

1

H_4P0

1

1

1

1

<27> EC_TACH
0_0603_5%<27> EC_FAN_PWM

1
2
3
4
G5
G6

1

1
2
3
4
5
6

+FAN

1

JFAN1

H_3P3

H_3P3

H_2P0N

FD1

FD2

FD3

FD4

1

1

1

H_2P5

H16
HOLEA

H19
HOLEA

1

H20
HOLEA

1

H7
HOLEA

1

H_2P8X4P8

1

H_2P8X5P1

H11
HOLEA

H21
HOLEA

1

LANGAN
H_2P8X4P6

H18
HOLEA

1

1

H6
HOLEA

1

H10
HOLEA

1

ACES_85205-04001
ME@
SP020008X00

1

1

2

1

H1
HOLEA

NPTH

1

R168
2

NGFF

1

FAN Conn

+5VS

VGA

1

CPU

B

H_2P5

H_2P8

H_2P8

H_3P3

H_6P0

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

EMC1403-2/FAN/Screw Hole
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

25

of

46

KB For B15

+3VALW

KB For B14/E14

JKB2
KSI[0..7]

For Debug

+3VALW

R263 2
R264 2 15@

1 470_0402_5% NUM_LED#_R

+3VLP

<27>

KSO16
KSO17

CAPS_LED#

R259 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

JKB1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
CAPS_LED#_R
CAPS_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND2
GND1

31
32

GND
GND

27
28

ACES_88514-02601-071
ME@
SP01000R500

ACES_88514-3001
ME@
SP010011A00

ESDP@

0.1U_0402_16V7K

R258 1

+5VS

ESDP@

C1379

0.1U_0402_16V7K

+3VS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

NUM_LED#
C1378

ESD

<26,27>
<26,27>
<27>

1

SCA00002M00

SCA00002M00
SHORT PADS

+3VS

2

ON/OFF#

1

@
2

D29

GND
GND
ACES_88058-060N
ME@
SP010010T00

1

ESDP@
D24
L30ESD24VC3-2 3P C/A SOT23 ESD

7
8

1
2
3
4
5
6

2

2
1

1

ESDP@

1

J2

2

@
2

SHORT PADS
1

LID_SW#

3

LID_SW#

2

<27>

ON/OFF#

3

ON/OFF#

JPWRB1
1
2
3
4
5
6

PWR_LED#

L30ESD24VC3-2 3P C/A SOT23 ESD

1

<27>

@

100K_0402_5%

J1

ESDP@

R170

J11: TOP
J12: BOT

2

100K_0402_5%

ACES_85205-0400
ME@

2

R274

ESDP@

1

C1368 1U_0402_6.3V6K

1
2
3
4

C1377 1U_0402_6.3V6K

1
2
3
4

+3VALW
EC_TX
EC_RX

1

2

KSO[0..17]
JP3

<24,27>
<24,27>

KSI1
KSI[0..7]
<27>
KSI7
KSI6
KSO[0..17]
<27>
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
1 470_0402_5% CAPS_LED#_R

For B15

2 0_0402_5%
2 0_0402_5%

@

@
C163
.1U_0402_16V7K

EC team

建建

LED2
RP33

2

@
C165
100P_0402_50V8J

0_0804_8P4R_5%
15@

ESDU@
D5
PSOT24C_SOT23-3

4
3
2
1

For B15/E14 TP module(100*50)

@

1

2

.1U_0402_16V7K
C167

.1U_0402_16V7K
C166

1

TP_L
TP_R

ESD

@

1

VCC

6

1

VCC

1

VCC

CLK

2

CLK

5

2

CLK

2

CLK

3

3

DAT

3

DAT

4

3

DAT

3

DAT

4

4

GND

4

L

3

4

GND

4

L

5

5

L

5

R

2

5

L

5

R

6

R

6

R172
1
2
470_0402_5%

2

+3VLP

<27>

CHG (Green)
(B14/B15/E14)

R295 1

BATT_CHG_LED#
<27>

2 0_0402_5%
LED3

PWR_LED#

PWR_LED#

R294 1

2 0_0402_5%

@

1

R173
1
2
470_0402_5%

2

+3VLP

LED4
<6>

1

SATALED#

SATALED#

R174
1
2
470_0402_5%

2

+3VS

LTST-C190KGKT-INV 0603 GREEN
SC590KGK020

VCC

1

1

BATT_LOW_LED#

BATT_LOW_LED#

LTST-C190KGKT-INV 0603 GREEN
SC590KGK020

For B14 TP module(84*42)

GND

<27>

19-217/S2C-FM2P1VY/3T 0603 ORANGE
SC500005T00

HDD (Green)
(B14/B15/E14)

2

6

B15_R_B14_VCC

GND
GND
ACES_88058-060N
ME@
SP010010T00

Battery (Amber)
(B14/B15/E14)

2

1

R

7
8

15@
0_0804_8P4R_5%
5
6
7
8

1
2
3
4
5
6

RP34

2

6

1
2
3
4
5
6

1

1

6

JTP1
B15_VCC_B14_R
B15_CLK_B14_L
B15_DATA_B14_GND
B15_GND_B14_DATA
B15_L_B14_CLK

TP_VCC
TP_CLK
TP_DATA

4
3
2
1

14@
0_0804_8P4R_5%
5
6
7
8

B15_R_B14_VCC
B15_L_B14_CLK
B15_GND_B14_DATA

+3VLP

RP35

JLED1

DC-In LED (Green)
(B14/B15/E14)

<35>

ACPRN#

R289 1

@

2 0_0402_5%

GND
RP36
TP_L
TP_R

1
2
3
4

8
7
6
5

<12,27,35>

B15_DATA_B14_GND
B15_CLK_B14_L
B15_VCC_B14_R

D

S

2
G

VCIN1_AC_IN

1
2
3
4

DC_LED

1

1

2

8
7
6
5

3

1

3

@
C164
100P_0402_50V8J

2

TP_CLK
TP_DATA

1
2
3 G1
4 G2

5
6

ACES_51512-0040N-P01
ME@
SP01001J100

Q20
2N7002H_SOT23-3

0_0804_8P4R_5%
14@

For B14
R278 1

2 0_0402_5%

R

2
1

2

VDD

15@
C248
.1U_0402_16V7K

R

OUTPUT

1

L

C1367
0.1U_0402_16V7K
ESDP@

4

2

4

2

TP_L
3

1

SW2
SMT1-05_4P

4

2

3

1

TP_L
3

1

5
6

14@
SW3
SMT1-05_4P

5
6

5
6

15@
SW1
SMT1-05_4P

3

LID_SW#

GND

2

L

15@
1 R279
2
100K_0402_5%

+VCC_LID

1

+3VALW

5
6

<27>
<27>

1
2
3
4

TP_VCC
TP_CLK
TP_DATA

@
SW4
SMT1-05_4P

2
15@
U16

1

15@
C249
10P_0402_50V8J

TCS20DLR SOT-23F 3P

4

2

3

1

TP_R

TP_R

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

KB/PWR BTN/LED/TP
Size
C
Date:

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet

26

of

46

4

3

2

+3VALW

<26>
<26>

+3VALW_EC

R201 1

2 2.2K_0402_5%

EC_SMB_CK1

R202 1

2 2.2K_0402_5%

EC_SMB_DA1

<34,35>
<34,35>
<12,25,5>
<12,25,5>

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

0.1U_0402_16V7K

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

B

<7> SLP_S3#
<7> SLP_S5#
<7> EC_SMI#
<20> CMOS_ON#
USB_CHG_EN#
<13,41> GPU_PWR_EN
<23> ODD_DA#_EC
<33> ADP_ID_CLOSE
<25> EC_TACH
<24,29> LAN_WAKE#
<24,26> EC_TX
<24,26> EC_RX
<7> SYS_PWRGD_EC
<28> NOVO#
<26> NUM_LED#

For GPU

ESD
2

1 10K_0402_5% GPU_PWR_EN

9
22
33
96
111
125

67

1

EC_VDD/AVCC

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

PWM Output
BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43

AD

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

21
23
26
27

ADP_65
BEEP#
EC_FAN_PWM
ACOFF

63
64
65
66
75
76

VCIN1_BATT_TEMP

VCIN1_BATT_TEMP

ADP_I
ADP_ID
BRDID
ENBKL

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
EC_MUTE#/GPIO4A
KSI4/GPIO34
USB_EN#/GPIO4B
KSI5/GPIO35
CAP_INT#/GPIO4C
PS2
Interface
KSI6/GPIO36
EAPD/GPIO4D
KSI7/GPIO37
TP_CLK/GPIO4E
KSO0/GPIO20
TP_DATA/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
CPU1.5V_S3_GATE/GPXIOA00
KSO4/GPIO24
WOL_EN/GPXIOA01
KSO5/GPIO25 Int. K/B
ME_EN/GPXIOA02
KSO6/GPIO26 Matrix
VCIN0_PH/GPXIOD00
SPI
Device
Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/GPIO5B
KSO10/GPIO2A
SPIDO/GPIO5C
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#/GPIO5A
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
ENBKL/AD6/GPIO40
KSO16/GPIO48
PECI_KB930/AD7/GPIO41
KSO17/GPIO49
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO
EC_SMB_CK1/GPIO44
PWR_LED#/GPIO54
EC_SMB_DA1/GPIO45
BATT_LOW_LED#/GPIO55
SM Bus
EC_SMB_CK2/GPIO46
SYSON/GPIO56
EC_SMB_DA2/GPIO47
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPIO

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

XCLKI/GPIO5D
XCLKO/GPIO5E

V18R

68
70
71
72

MP

BRDID

ENBKL

+5VS +3VS +5VS +3VS

<34>

ADP_I <34,35>
ADP_ID <33>

3VGS_PWR_EN

DVT@
R1564

<20,5>

3VGS_PWR_EN

EC_WL_OFF#

EC_WL_OFF#

83
84
85
86
87
88

EC_MUTE#
USB_ON#
PTC_PROTECT

97
98
99
109

TS_DISABLE#
HDD_DETECT#
095VS_PWR_EN
VCIN0_PH1
EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#

73
74
89
90
91
92
93
95
121
127

APU_IMON_R
VGATE
USB_CHG_CTL1
USB_CHG_CTL2
CAPS_LED#
PWR_LED#
BATT_LOW_LED#
SYSON
VR_ON
095_18ALW_PWR_EN

1

R200

1

TP_DATA R261

1

<24>

2 4.7K_0402_5%
2 4.7K_0402_5%

@

2 4.7K_0402_5%

R1564
8.2K_0402_5%

C

+3VS

VCIN1_AC_IN
EC_ON
ON/OFF#
LID_SW#
SUSP#
NUVOTON_VTT

2

1 0_0402_5%
1 0_0402_5%

@
@

USB_CHG_STATUS#
APU_IMON <40>

VGATE <40>
USB_CHG_CTL1
USB_CHG_CTL2
CAPS_LED# <26>
PWR_LED# <26>
BATT_LOW_LED# <26>
+3VLP
SYSON <32,37>
@
VR_ON <40>
095_18ALW_PWR_EN <38,39>
R343
47K_0402_5%
EC_RSMRST#
EC_LID_OUT#

<7>
<7>

EC_MUTE#

R198 1

LAN_WAKE#

R212 1

2 10K_0402_5%

HDD_DETECT#

R281 1

2 100K_0402_5%

LID_SW#

R344 1

BKOFF# <20>
PBTN_OUT# <7>
BATT_CHG_LED#
USB_CHG_CTL3

VCIN1_AC_IN
EC_ON <36>

@

@

2 47K_0402_5%

1
1

R203

<32,37,39>

R1567
0_0402_5%

1
R207

ESDU@
2
C1369 1

<12,26,35>

2

1

B

2
100P_0402_50V8J
2
100P_0402_50V8J
2
@
4.7K_0402_5%
2
100K_0402_5%

100P_0402_50V8J
<26>
<26>

VCOUT1_PROCHOT#
<40>

2 10K_0402_5%

ESDP@
1 0.1U_0402_16V7K
1

VCIN1_BATT_TEMP
C189
VCIN1_AC_IN
C190
095VS_PWR_EN

<26>

ON/OFF#
LID_SW#
SUSP#

2

C1366

VCIN1_ADP_PROCHOT
<34>
VCOUT1_PROCHOT# <34>
VCOUT0_MAIN_PWR_ON
<36>

ESDU@
1

2 10K_0402_5%

+3VALW

R309 2
R308 2

110
112
114
115
116
117
118

BKOFF#
PBTN_OUT#
BATT_CHG_LED#
USB_CHG_CTL3

R214 1

EC_TACH

PROCHOT#

R204 1

2 0_0402_5%

R205 1

2 0_0402_5%

2
G
Q13
2N7002H_SOT23-3
9012@

D

S

VCOUT1_PROCHOT#

H_PROCHOT#

1

2

<5,7>

@
C191
47P_0402_50V8J

A

ECAGND
1

2014/03/03

Issued Date

2

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/03/03

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

2 4.7K_0402_5%

@

PVT@

EC_SPI_AISO <6>
EC_SPI_AOSI <6>
EC_SPI_CLK <6>
EC_SPI_CS1# <6>

EC_RSMRST#
EC_LID_OUT#
VCIN1_ADP_PROCHOT

20mil

1

R260

TS_DISABLE# <20>
HDD_DETECT# <23>
095VS_PWR_EN <32>
VCIN0_PH1 <34>

100
101
102
103
104
105
106
107
108

+V18R

R199
TP_CLK

R1564 @
0_0402_5%

TP_CLK <26>
TP_DATA <26>

119
120
126
128

124

<13>

EC_MUTE# <30>
USB_ON# <28>
PTC_PROTECT <34>

TP_CLK
TP_DATA

SYSON
ESDU@

R1562
100K_0402_5%
ADP_65 <34>
BEEP# <30>
EC_FAN_PWM <25>
AC_OFF <35>

18K_0402_5%

NPCE288NB0DX_LQFP128_14X14
Part Number = SA000079Y00

@
.1U_0402_16V7K
C193

A

R310

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

11
24
35
94
113

+3VS

122
123

D

C1370

DGPU_PWR_EN

MP
PVT
DVT
EVT

V
V
V

+3VALW

100P_0402_50V8J

DGPU_PWR_EN

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

V
V
V

max

10K_0402_5%

C823 4.7U_0603_6.3V6K

<13,7>

SLP_S3#
SLP_S5#
EC_SMI#
CMOS_ON#
USB_CHG_EN#
GPU_PWR_EN
ODD_DA#_EC
ADP_ID_CLOSE
EC_TACH
LAN_WAKE#
EC_TX
EC_RX
SYS_PWRGD_EC
NOVO#
NUM_LED#

VAD_BID
0 V
0.289
0.538
0.875

1

KSI[0..7]

12
13
37
20
38

V
V
V

typ

3

KSO[0..17]

KSI[0..7]

LPC_CLK0_EC
LPC_RST#
EC_RST#
EC_SCI#
BATT_LEN#

V AD_BID
0 V
0.250
0.503
0.819

2

C187

1
2
3
4
5
7
8
10

2

min

1

<7> EC_SCI#
<34> BATT_LEN#

GATEA20
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

USB_ON# 1

2

1

2

LPC_RST#

C

KSO[0..17]

U11

@

R194

+EC_VCCA

VAD_BID
0 V
0.216
0.436
0.712

2

<7>

1
47K_0402_5%
1

+3VALW_EC

@

2

1

AGND/AGND

<7> GATEA20
<7> KBRST#
<6> SERIRQ
<6,7> LPC_FRAME#
<6> LPC_AD3
<6> LPC_AD2
<6> LPC_AD1
<6> LPC_AD0

LPC_CLK0_EC
2
R192

2

1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

2

1

69

<6,7>

1

ESDP@
2
1 1000P_0402_50V7K

EMIU@
R1560
1 22P_0402_50V8J2 EMIU@ 1
10_0402_5%

+5VALW

2

1000P_0402_50V7K

C1375

2

2 0_0603_5%

@

ECAGND

C1263

1@
C179
100P_0402_50V8J

2

R189 1

+3VALW_EC

2 0_0603_5%

C183
1000P_0402_50V7K

2

+EC_VCCA
C185

@

C182
1000P_0402_50V7K

C184
.1U_0402_16V7K
2 ECAGND
2
L21
FBM-11-160808-601-T_0603

R188 1

C181
.1U_0402_16V7K

D

1

C180
.1U_0402_16V7K

1

L20
FBM-11-160808-601-T_0603
2
1

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1

+3VLP

1

+3VALW_EC

1

3.3V +/- 5%
Vcc
R1562 100K +/- 5%
Board ID
R1564
0
0
8.2K +/- 5%
1
18K +/- 5%
2
33K +/- 5%
3

+3VLP

2

5

4

3

2

EC-Nuvoton 288N
Rev
1.0

LA-B291P
Sheet

Monday, March 03, 2014
1

27

of

46

5

4

3

2

1

ESD

Finger Print

ESDU@
U3RXDN0 9 10

D6
1 1 U3RXDN0

U3RXDP0 8

2

U3TXDN0 7
U3TXDP0 6

9
7
6

+3VS
JFP1
R291 1

2 0_0402_5% +3VS_FP

1
2
3
4
5
6

3

USB20_P7
USB20_N7

2

<6>
<6>

Finger Print
(For B14/E14/B15)

D

2

1

SCA00000U10

ESD

C247
.1U_0402_16V7K

ESDP@
D25
L30ESD24VC3-2 3P C/A SOT23 ESD

D7
1 1U3RXDN1

U3RXDP1 8

2

2U3RXDP1

9

ESDU@

3

U2DN0

D8

I/O2

I/O4

ESDU@

6

3

U2DP1

D9

I/O2

I/O4

GND

VDD

I/O1

I/O3

6

4 U3TXDN0

5

5 U3TXDP0

3

3

U3TXDN1 7

7

4

4U3TXDN1

U3TXDP1 6

6

5

5U3TXDP1

3

3

2

1

8
8

1
2
3
4
5
6

7
8

1

4

ESDU@
U3RXDN1 9 10

2 U3RXDP0

GND

VDD

I/O1

I/O3

5

2

+USB3_VCCA

4

1

U2DP0

AZC099-04S.R7G_SOT23-6

5

4

+USB3_VCCA

U2DN1

AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9

D

ESD protection needs to be placed near connector side

GND
GND

USB3.0_Port

ACES_88058-060N
ME@
SP010010T00

EMI
<6>

USB30_N9

<6>

USB30_P9

COM FI_ INPAQ MCM2012D900FBE ET88
1
2
U2DN1
1
2

4

4

3
L12
USB2@
SM070002Z00

3

U2DP1

Left USB CONN
WCM-2012HS-900T
+USB_VCCB

<6>

USB20_N1

<6>

USB20_P1

4

3

3

@
R275

USB20_N1_C

2
R169

1

EMIP@
L14

1 0_0402_5%

1

4

@

+3VLP

C170
220U_6.3V_M

1
2
USB20_P1_C
2
COM FI_1INPAQ MCM2012D900FBE
ET88
SM070002Z00
R178 2

@

<30>
<30>

HPOUT_R
PLUG_IN
USB20_N1_C
USB20_P1_C

Right USB2__I/O Port
2A/Active Low

+5VALW

<27>

4

USB_ON#

OUT
IN
GND
EN

W=80mils

1

@
USB_OC0#_U8 R179 1

1

3

G524B2T11U SOT-23 5P
SA00007BW00

1

2

2 0_0402_5% USB_OC0#

USB_OC0#

USB3@ 3

U3RXDN1

3

U3RXDP1

W=80mils
JUSB1
U3TXDP1
U3TXDN1
U2DP1

+

U2DN1
U3RXDP1

<6>

USB30_MTX_C_DRX_N1

<6>

USB30_MTX_C_DRX_P1

14
12 G2 13
11 G1
10
9
8
7
6
5
4
3
2
1
ACES_88058-120N
ME@
SP010015H00

1
1

C168
USB3@
.1U_0402_16V7K
2 U3TXDN1_L

2

WCM-2012HS-900T

1

1

4

U3TXDP1_L

4
L15

C169
USB3@
.1U_0402_16V7K

<6>

USB30_N8

<6>

USB30_P8

2
USB3@ 3

U3RXDN1

2

U3TXDN1

3

U3TXDP1

9
1
8
3
7
2
6
4
5

SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
J-L_TNBNRAC70010009
ME@
DC23300ET10

C

Near HDMI CONN

COM FI_ INPAQ MCM2012D900FBE ET88
1
2 U2DN0
1
2

4

3 U2DP0

4

3
L16
USB2@
SM070002Z00

2

2

OCB
C195
.1U_0402_16V7K

NOVO#

+USB_VCCB

U8

5
<27>

12
11
10
9
8
7
6
5
4
3
2
1

<30> HGNDB
<30> HGNDA
<30> HPOUT_L

1 0_0402_5%

2

4
L13

JIO1

Right USB2__I/O Port

1

4

+USB3_VCCA

2

2

100K_0402_5%

2

+3VALW
100K_0402_5%

R177 2

USB30_MRX_DTX_P1

1

EMI

USB2.0_Port

USB30_MRX_DTX_N1

<6>

For B14 / B15

W=80mils

C

<6>

1

<7>

Left USB CONN

@
C171
470P_0402_50V7K

+USB3_VCCA

WCM-2012HS-900T
<6>

USB30_MRX_DTX_N0

<6>

USB30_MRX_DTX_P0

1

1

4

2

4

USB3@

3

2

U3RXDN0

3

U3RXDP0

W=80mils
JUSB2
U3TXDP0

L17

B

U3TXDN0
U2DP0
U2DN0
U3RXDP0

<6>
<6>

1

USB30_MTX_C_DRX_N0

1

USB30_MTX_C_DRX_P0

C172USB3@
.1U_0402_16V7K
2
U3TXDN0_L

2

WCM-2012HS-900T

1
4

U3TXDP0_L

C173USB3@
.1U_0402_16V7K

1

2

4

USB3@

3

U3RXDN0

2

U3TXDN0

3

U3TXDP0

9
1
8
3
7
2
6
4
5

SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
J-L_TNBNRAC70010009
ME@
DC23300ET10

B

Near End User

L18

Place TX AC coupling Cap (C843~C850). Close to connector

2A/Active Low
+5VALW

+USB3_VCCA
U10

W=80mils
5
USB_ON#

4

OUT
IN
GND
EN

2

1

OCB
C196
.1U_0402_16V7K

2
@

3

R185 1

2014/03/03

Deciphered Date

2 0_0402_5%

+

2

1

2

A

Compal Electronics, Inc.
2015/03/03

Title

Date:

4

3

2

<7>

@
C177
470P_0402_50V7K

USB Port/FP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

USB_OC1#

1

SA00007BW00

Compal Secret Data

Security Classification
Issued Date

USB_OC1#_R

G524B2T11U SOT-23 5P

C178
220U_6.3V_M

A

W=80mils

1

Rev
1.0

LA-B291P

Monday, March 03, 2014
1

Sheet

28

of

46

5

4

+3V_LAN

W=60mil

2
0_0603_5%
8111GLDO@
+LAN_VDD

LL1

CL15
8111GLDO@

2

D

LL1
8106ESW@

W=60mils

CL16
8111GSW@

1
1

1
2
2.2UH +-5% NLC252018T-2R2J-N
8111GSW@

.1U_0402_16V7K

+LAN_SROUT1.05

2
CL1
1U_0402_6.3V6K

1

CL16
8106ESW@
CL17
8106ESW@

1

2

1

CL17

2

.1U_0402_16V7K

1

60mil

2

RL11

2 0_0603_5%

8111GSW@

RL18 1

4.7U_0603_6.3V6K

+3VALW

3

D

LL1, CL16, and CL17 close to Pin24
( Should be place within 200 mils )

RJ-45 CONN.
+3V_LAN

要>1mS and <100mS

2

2

2

2

2

2

Pin3

Close to Pin23

C

CL5
2

CL6
2

Pin8

Pin22

CL7
2

Pin30

2
510_0402_5%

12
11

1
CL8

CL4

1

1
RL15

2

1U_0402_6.3V6K

CL9
8106ESW@

1

1

.1U_0402_16V7K

@
CL21

CL10

1

.1U_0402_16V7K

@
CL20

1

8111GSW@

2

CL3

1

4.7U_0603_6.3V6K

CL2

1

CL9
4.7U_0603_6.3V6K

1

.1U_0402_16V7K

1

.1U_0402_16V7K

0_0603_5%

1

.1U_0402_16V7K

2+LAN_VDDREG

.1U_0402_16V7K

W=60mils

LED0

W=40mils

RL1
1
@

.1U_0402_16V7K

+3V_LAN

4.7U_0603_6.3V6K

Rising Ɵme (10%~90%)
+3V_LAN

JLAN1

+LAN_VDD

Pin22

+3V_LAN
1
LED2
RL16

CL2 close to Pin 11
CL3 close to Pin 32

RJ45_TX3-

8

RJ45_TX3+

7

RJ45_RX1-

6

RJ45_TX2-

5

RJ45_TX2+

4

RJ45_RX1+

3

RJ45_TX0-

2

RJ45_TX0+

1

2
510_0402_5%

10
9

Yellow LEDYellow LED+
PR4PR4+
PR2PR3PR3+
PR2+

C

PR1SHLD2
SHLD1

PR1+

13
14

Green LEDGreen LED+
SANTA_130452-0P
ME@
DC234007O00
LANGAN1

+LAN_VDD

LANGAN

+LAN_VDD
+3VS

LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2

EMI
RL4

1

2 0_0402_5%

RL5

1

2 0_0402_5%

LAN_MDIP3
LAN_MDIN3
+3V_LAN
<7> LAN_CLKREQ#
PCIE_ATX_C_DRX_P1
PCIE_ATX_C_DRX_N1
<6> CLK_PCIE_LAN
<6> CLK_PCIE_LAN#

<6>
<6>
LANGAN

B

EMIU@RL6
EMIU@
RL6

1

2 0_0402_5%

EMIU@RL7
EMIU@
RL7

1

2 0_0402_5%

MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N

HSOP
HSON
PERSTB
ISOLATEB
LANWAKEB
DVDD10
VDDREG
REGOUT
LED2
LED1/GPIO
LED0
CKXTAL1
CKXTAL2
AVDD10
RSET
AVDD33
GND

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

PCIE_DTX_ARX_P1
PCIE_DTX_ARX_N1
APU_PCIE_RST#
ISOLATE#
LAN_WAKE#

1
CL11
1
CL12
<11,24,31,7>

APU_PCIE_RST#
LAN_WAKE#

.1U_0402_16V7K
2

PCIE_DTX_C_ARX_P1

<6>

.1U_0402_16V7K

PCIE_DTX_C_ARX_N1

<6>

+3V_LAN
1
RL17

LED1_GPIO

@

2
10K_0402_5%

UL2
SA000065Y00
S IC RTL8106E-CG QFN 32P E-LAN CTRL
8106ELDO@

RL10
15K_0402_5%

TPL2

reserved GPIO pin

2.49K_0402_1% 2

1 RL9

+3V_LAN

UL2
SA00005O700
RTL8111GS-CG_QFN32_4X4
8111GLDO@

EMI

TL1
UL2
SA00006N910
S IC RTL8106EUL-CG QFN 32P E-LAN CTRL
8106ESW@

CL13
2

RL20

2

1 0_0402_5%

@

XTLO

LAN_MDIP2
XTLI

1
2
3
4
5

1
2
3
4
5

10
9
8
7
6

+V_DAC

1

LAN_MDIP3

2

LAN_MDIN3

3

+V_DAC

4

LAN_MDIP2

5

LAN_MDIN2

6

+V_DAC

7

LAN_MDIP1

8
9

LAN_MDIP3

LAN_MDIN1

LAN_MDIN3

+V_DAC

10

LAN_MDIP0

11

LAN_MDIN0

12

RCLAMP3304N.TCT_SLP2626P10-10
GIGAEMIU@
SC300001J00

11

10P_0402_50V8J

10
9
8
7
6

GND

1

NC
OSC

4

OSC
NC

EMI
LAN_MDIN2

CL14
2

CL18
1
2
0.01U_0402_16V7K
EMIP@

DL1

3

2

YL1
25MHZ_10PF_7V25000014

EMI

UL2
SA00006ML10
S IC RTL8111GUL-CG QFN 32P E-LAN CTRL
8111GSW@

10P_0402_50V8J

1

ISOLATE#

B

LANGAN1

1

RL8
1K_0402_5%

<24,27>

+LAN_VDDREG
+LAN_SROUT1.05
LED2
TPL1
LED0
XTLO
XTLI

2

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2

LAN_MDIP0
LAN_MDIN0

TL1
S0 X'FORM_ HH-065 10/100
8106ELDO@

TCT1
TD1+

MCT1
MX1+

TD1-

MX1-

TCT2

MCT2

TD2

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

24

MCT
RL19

23

RJ45_TX3+

1

22

RJ45_TX3-

75_0805_5%
EMIP@

CL19
1
2

2

10P_0603_50V
EMIP@

21
LANGAN
20

RJ45_TX2+

19

RJ45_TX2-

18

2

17

RJ45_RX1+

16

RJ45_RX1-

EMIP@

15
14

RJ45_TX0+

13

RJ45_TX0-

1

DL3
BS4200N-C-LV_SMB-F2

EMI

350UH_IH-160
8111GLDO@

DL2
1
2
3
4
5

10
9
8
7
6

11

LAN_MDIP0

1
2
3
4
5

GND

LAN_MDIN0

A

10
9
8
7
6

A

LAN_MDIP1

FOR 10/100 data transferring 2013/08/27

LAN_MDIN1
TL1
S0 X'FORM_ HH-065 10/100
8106ESW@

RCLAMP3304N.TCT_SLP2626P10-10
EMIU@
SC300001J00

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

TL1
S0 X'FORM_ 350UH_IH-160
8111GSW@

2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LAN_RTL8111G/RTL8106E
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

29

of

46

B

C

D

E

+3VS

+3VDD_CODEC

+IOVDD_CODEC

+1.5VS

RA2

RA3

2
+5VS_PVDD

External DMIC

<20>
<20>

DMIC_DAT
DMIC_CLK

EMIP@

LA1
RA8

<7>

31
30

+LINE1-VREFO-R
SM01000I000
1

2 0_0402_5%
1

DMIC_CLK_R

2 10K_0402_5%
RA11 1

@

<27> EC_MUTE#
HDA_RST_AUDIO#

2
3

2 0_0402_5%

47
11
12

PC_BEEP

2

PLUG_IN_R

CA15 2

13
14
37
35

1 1U_0402_6.3V6K

36

+3VDD_CODEC

@ CA17 2
+3VLP

1 4.7U_0603_6.3V6K

233VB@ RA161

2 100K_0402_5%

CA19 2
RA18 1

1 2.2U_0402_6.3V6M
@

2 0_0402_5%

RA18 pop on ALC283, NC on ALC233

20
19
4
49

MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE
LINE1-VREFO-L
LINE1-VREFO-R
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
PDB
RESETB

ALC233-CG

HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
SYNC
BCLK

SPK_R2+
SPK_R1-

32
33

PCBEEP
MONO-OUT
SENSE A
SENSE B
MIC2-VREFO

HP_OUTL
HP_OUTR

HDA_RST_AUDIO#

Headphone

10
6

HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO

LDO3-CAP
LDO2-CAP
LDO1-CAP

5
8

HDA_SDIN0_AUDIO

VREF
CPVREF
JDREF
CPVEE

CA12 EMIU@

RA12 1

<7>
<7>

HDA_SDOUT_AUDIO
HDA_SDIN0
<7>

AVSS1
AVSS2

29
7
39
27

LDO3
LDO2
LDO1

28
15
34

CA14 2

1 2.2U_0402_6.3V6M

CA16 2

1 2.2U_0402_6.3V6M

25
38

1
100K_0402_5%

3

CA5
1

CA6

QA1
MESS138W-G_SOT323-3
233@

+3VS

2

233VB@
RA38
100K_0402_5%

RA13 1 233@

PLUG_IN_R

2 1U_0402_6.3V6K

RA17 1

2 20K_0402_1%

W=40mils
W=40mils

233@

1

S

Combo Jack
(Normal Open)

EXT_MIC_SLEEVE
EXT_MIC_RING2
HP_OUTL
HP_OUTR

EMIP@
EMIP@
EMIP@
EMIP@

RA19
RA20
RA22
RA23

CA20
1U_0402_6.3V6K

For Universal Audio Jack

2 39.2K_0402_1%

SM010010710
SM010010710
2
1
2
1
1
2
1
2
SM01000FH00
SM01000FH00

0_0603_5%
0_0603_5%
47_0402_5%
47_0402_5%

PLUG_IN

LINE1-L

CA21 2

1 1U_0402_6.3V6K

LINE1-R

CA22 2

1 1U_0402_6.3V6K

RA29 1

2 4.7K_0402_5%

2 0_0402_5%

RA24 1

2 0_0402_5%

RA25 1

2 0_0402_5%

+LINE1-VREFO-R

RA32 1

2 4.7K_0402_5%

PLUG_IN

EMI

UA1
ALC233-VB2-CG MQFN 48P
233VB@

RA21 1

QA2
MESS138W-G_SOT323-3
233@

Vendor recommended 10/16

2
RA15
CA18 1

JDREF
CPVEE

D

2
G

For ALC233VB only

16
1 2.2U_0402_6.3V6M

2

233VB@
RA13
200K_0402_1%

ALC233-CG_MQFN48_6X6

EMI

<7>

+MIC2-VREFO
CA13 2

S

22P_0402_50V8J

2
DVSS
Thermal PAD

233@
RA14 1
10K_0402_5%

D

2
G

EMI

2 33_0402_5%

48

CPVDD

MIC-CAP

KABINI need to use this part
Due to RST is 1.5V power rail
Intel project can use dual 2N7002

RA101 EMIU@ 2 33_0402_5%
SDATA-OUT
SDATA-IN
SPDIF-OUT/GPIO2

CBP
CBN

SPK_L1SPK_L2+

45
44

1

SPK-OUT-R+
SPK-OUT-R-

43
42

EXT_MIC_SLEEVE

3

SPK-OUT-LSPK-OUT-L+

233@
RA9
100K_0402_5%

2

26

46

9

41

40
AVDD2

AVDD1

PVDD2

Place near Pin26

HGNDB
HGNDA
HPOUT_L
HPOUT_R

2

RA7

EMI

+3VLP

@

@

<28>

HGNDB
<28>
HGNDA
<28>
HPOUT_L <28>
HPOUT_R
<28>

10K_0402_5%
RA27

17
18

2

2

EXT_MIC_RING2
EXT_MIC_SLEEVE

2

Place near Pin40

0_0603_5%

Place RA4 on AGND/DGND moat

1

2 2.2K_0402_5%
2 2.2K_0402_5%

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)

2 1U_0402_6.3V6K

1

1

RA6
1
1

+MIC2-VREFO

LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

1

1

2

24
23

PVDD1

DVDD

wide 40MIL

DVDD-IO

1

CA8

2 0_0402_5%

3

1

RA5

2

1

+3VDD_CODEC

22
21

1

RA4
1
+1.5VS

LINE1-L
LINE1-R

Place near Pin9

+5VS

+IOVDD_CODEC

233@ UA1

connect to +VDDIO_AZ_ALW

1

2

CA11

2

Place near Pin1
+5VDDA_CODEC

2.2U_0402_6.3V6M

1

1

CA7
.1U_0402_16V7K

1

1

.1U_0402_16V7K

CA1

2

2

2
0_0603_5%

RA26
10K_0402_5%

2 0_0805_5%
.1U_0402_16V7K
CA3

1

4.7U_0603_6.3V6K
CA2

RA1

2

CA4
+5VS

1

.1U_0402_16V7K

1
1

1U_0402_6.3V6K

2
0_0603_5%

.1U_0402_16V7K

1

1

A

3

RA28
1 EMIU@ 2
0_0402_5%

GND

GNDA

11/20 Change symbol of JSPK1 to SP02000H700

EMI
wide 40MIL
JSPK1

1 RA34
CA24 1

2

CA25
1
2

PC_BEEP

2 .1U_0402_16V7K
1K_0402_5%

.1U_0402_16V7K

1

2

1

2

1

2

1

2

1000P_0402_50V7K

2 .1U_0402_16V7K

1
2
3
4
5
6

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
1000P_0402_50V7K
EMIP@ CA31

APU_SPKR

CA23 1

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

1000P_0402_50V7K
EMIP@ CA30

<7>

BEEP#

2
2
2
2

EMIP@ CA28

<27>

1
1
1
1

ESD

ACES_85205-04001
ME@
SP020008X00

+5VS
ESDU@
SPK_R1-_CONN

1
2
3
4
G5
G6

6

DA3

I/O4

I/O2

VDD

GND

I/O3

I/O1

3

SPK_L2+_CONN

1

EC Beep
APU Beep

LA5
LA6
LA7
LA8

1000P_0402_50V7K
EMIP@ CA29

SPK_R1SPK_R2+
SPK_L1SPK_L2+

PC Beep

@
RA36
10K_0402_5%

5

2
4

2

4

SPK_R2+_CONN

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HD Audio Codec_ALC233
Size
C
Date:

A

B

C

D

SPK_L1-_CONN

AZC099-04S.R7G_SOT23-6

ESD protection needs to be placed near connector side
Security Classification

1

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
E

30

of

46

5

4

3

2

1

D

D

+AV12

2

+DV12S

CC2

1

CC3

2

+3VS

1

2

CC4

.1U_0402_16V7K

2

1

4.7U_0603_6.3V6K

1

.1U_0402_16V7K

4.7U_0603_6.3V6K

CC1

CC5

1

2 4.7U_0603_6.3V6K

CC6

1

2 .1U_0402_16V7K

UCR1

+Card_3V3
LC1
1
2
PBY160808T-301Y-N_0603

+Card_3V3

+DV33_18
+AV12
+DV12S

9
15
7
11

+Card_3V3_R

10

1
RC1

8

2
6.2K_0402_1%

3V3_IN
DV33_18
AV12
DV12_S
Card_3V3
GND

25

RREF
1

2 0_0402_5%

SD_D1

RC3 1
SD_CLK_R
RC5 1
RC6 1
RC7 1

2 0_0402_5%

SD_D0

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

SD_CMD
SD_D3
SD_D2

RC2
<6>
<6>
<6>
<6>

C

PCIE_ATX_C_DRX_P0
PCIE_ATX_C_DRX_N0
PCIE_DTX_C_ARX_P0
PCIE_DTX_C_ARX_N0

CC7
CC8

<6>
<6>

+DV33_18

2

1

1U_0402_6.3V6K

<11,24,29,7>
CC10

1
1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

1
2
5
6

PCIE_DTX_ARX_P0
PCIE_DTX_ARX_N0

3
4

CLK_PCIE_CR
CLK_PCIE_CR#

23

APU_PCIE_RST#
<7>

24

CR_CLKREQ#
+3VS

2
RC8

1

19

SD_GPIO1
10K_0402_5%

HSIP
HSIN
HSOP
HSON

SP1
SP2
SP3
SP4
SP5
SP6

12
13
14
16
17
18

EMI
RC9

1 EMIP@ 2 33_0402_5%

REFCLKP
REFCLKN
PERST#

SD_WP

CLK_REQ#

SD_CD#

GPIO

MS_INS#

20

SD_WP

21

SD_CD#

SD_CLK
C

1

2

EMIU@
CC13
5.6P 50V D NPO 0402

EMI

22

RTS5229-GR_QFN24_4X4

+Card_3V3
JSD1
7

SD_D1

8

SD_D2

9

SD_D3

1

SD_CLK

5

SD_CMD

2

D0

VDD

4
B

D1
D2
D3
CLK
CMD

WP
CD
VSS1
VSS2
Shading
Shading

10

SD_WP

11

SD_CD#

3
6
12
13

CC11

1

2

CC12

1

2

.1U_0402_16V7K

SD_D0

4.7U_0603_6.3V6K

B

TAITW_PSDBTC-09GLBS1N14H0
ME@
SP07000LN00

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Card Reader RTS5229
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-B291P
Monday, March 03, 2014

Sheet
1

31

of

46

A

B

+5VALW TO +5VS
+3VALW TO +3VS
Load switch

C

D

E

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+3VALW

VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+3VS

3

SUSP#

4

VL

2

5

SUSP#
1

6
7

+5VALW

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13
12

@

1

+3VS_LS
C9
1

330P_0402_50V7K
2

C10
1

180P_0402_50V8J
2

2
PAD-OPEN 4x4m
2

1 C12

VOUT1
VOUT1

11
10

+5VS
9
8

J5

15

2
PAD-OPEN 4x4m

C11
1U_0402_6.3V6K

+1.8VALW

3

SUSP#

4

VL

2

095VS_PWR_EN

095VS_PWR_EN

5
6
7

+0.95VALW

2

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13
12

1

+1.8VS_LS
C21
1

2

180P_0402_50V8J
2
@

PAD-OPEN 4x4m
2

1 C24

VIN1
VIN1

11
10
9
8

C15
1

330P_0402_50V7K
2
@
J95V @
1
+0.95VS_LS

15

+0.95VS
2

2

PAD-OPEN 4x4m

1

C22

C25
0.1U_0402_16V7K

1U_0402_6.3V6K

2

1

APE8990GN3B DFN 14P
@

C26
0.1U_0402_16V7K

+1.35V

+1.5VS discharge circuit only for Beema

+0.675VS

1

only 1.5VS from PWR

R1627
470_0603_5%
@

D

S

3

1

only for Beema

R1629
470_0603_5%
@

1 2

1 2

+1.5VS

1

<27>

+1.8VS
J18V @

U1895P
1
2

1

@

VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

2

1U_0402_6.3V6K

+1.8VALW TO +1.8VS
+0.95VALW TO +0.95VS
Load switch

D

2 SYSON#
G Q25
2N7002H_SOT23-3
@

2 SUSP
G Q21
2N7002H_SOT23-3
@

S

3

2

C14
0.1U_0402_16V7K

1

1

1

@

1

+5VS_LS

APE8990GN3B DFN 14P
@

C13
0.1U_0402_16V7K

1

@

J4

VIN1
VIN1

2

1U_0402_6.3V6K

U13
1
2

3

3

R1461
220_0603_5%
2
1

+3VLP

D

2

+5VALW

1

R1639
100K_0402_5%

OUT
SYSON

SYSON

@

2

IN

R239
100K_0402_5%

Q24
DTC124EKAT146_SC59-3
@

2

2

@

<27,37>

1

IN

GND

2

SUSP#
1

SUSP#

SYSON#

DTC124EKAT146_SC59-3

OUT

@

<27,37,39>

1

Q101

2

@
R1638
100K_0402_5%

3

SUSP

GND

@

1

R1636
100K_0402_5%
1

3

S

2 SUSP
G Q23
2N7002H_SOT23-3
@

3

@

4

4

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DC Interface
Document Number

Rev
1.0

LA-B291P
Sheet

Monday, March 03, 2014
E

32

of

46

5

4

3

EMI@ PL101
HCB2012KF-121T50_0805

@ PR101
2
PQ101A
0_0402_5% 2N7002KDW-2N_SOT363-6
1
2
6
1
PR102
750_0402_1%

1
2

1

2

EMI@ PC104
1000P_0402_50V7K

D

EMI@
PL102
1

HCB2012KF-121T50_0805

2

2

1

ACES_88299-0510
CONN@

VIN

2

EMI@ PC103
100P_0402_50V8J

1

PF101
7A_24VDC_429007.WRML
1
2 APDIN1

1

APDIN

2

1
2
3
4
5

EMI@ PC102
100P_0402_50V8J

1
2
3
4
5

EMI@ PC101
1000P_0402_50V7K

JDCIN1

2

1

ADP_ID
AC Adapter 90W 65W
R(K ohm) open 10
ADP_ID(V) 3.3 1.65
Detection voltage >2.64 1.32~1.98

D

PR104

2

100K_0402_5%

+CHGRTC
PR105
1K_0603_5%
1
2

C

+RTCBATT_3V

PD101
S SCH DIO BAS40CW SOT-323
2
1
3

1
2

PC106
680P_0603_50V7K

PQ101B
2N7002KDW-2N_SOT363-6
4
3

PR103
100K_0402_5%
1
2
1

VIN

2

2

1

+3VALW

PC105
0.1U_0402_16V7K

1

5

ADP_ID

<27>

A/D

ADP_ID_CLOSE

<27>

+3VLP

+CHGRTC_R
JBATT1
PR106
1K_0603_5%
1
2

1

+

C

-

2

LOTES_AAA-BAT-019-K01
CONN@

RTC Battery

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2014/03/03

2015/03/03

Deciphered Date

Title

Compal Electronics, Inc.
Power Map

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
1

33

of

46

3

VL

PR225
OTP@
2

1

OTP@

PR230
PR229
PR233
OTP@
OTP@
OTP@
2 1
2 1
2

VGA

2

MOS_OTP

<36>

OTP@

1.5V

1.8V

1K_0402_50%

1K_0402_50% 1K_0402_50% 1K_0402_50%

CPU

OTP@

1

2

0.1U_0603_25V7K
OT1

<27> PTC_PROTECT
OTP@

3
4

VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2

OTP@
8

OTP@
TMSNS1

OTP@

OTP@

PQ202
2N7002KW_SOT323-3
D
PTC_PROTECT2
G
S

7
6

TMSNS2

MOS_OTP:
Default:High
Active :Low
PTC_PROTECT:
Default:Low
Active :High

5

G718TM1U_SOT23-8

OTP@

OTP@

PH201 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

VCIN1_BATT_TEMP <27,34>

A/D

20120314
Change to +EC_VCCA from +3VLP

+5VALW

+EC_VCCA
2
1
PR215
16.5K_0402_1%

2

1
2
PR223
75K_0402_1%

1

1

2

1

1

ECAGND
D

3

1
2

1

B

1.5M_0402_5%

PR221
100K_0402_1%

PQ201B
2N7002KDW-2N_SOT363-6

5

PR226
PC206
100P_0402_50V8J

3

2

4

1

PH201
100K_0402_1%_TSM0B104F4251RZ

S

2
G

PQ203
2N7002KW_SOT323-3

+3VLP
2

2

1

1N4148WS-7-F_SOD323-2

O

PU202A
AS393MTR-E1 SO 8P OP

2
PD201
1

-

4

2

6 1

1
2
8

PC205
0.068U_0402_16V7K

+

P

3

G

VCIN1_BATT_TEMP

BATT_OUT <35>
PQ201A
2N7002KDW-2N_SOT363-6

2

VCIN0_PH1

VCIN1_ADP_PROCHOT

100K_0402_1%

100K_0402_1%
PR220
47K_0402_1%

<27>

<27>

C

1

PR219

@

1

2
2

PR218

PR217
30K_0402_1%

1

VCOUT1_PROCHOT#

+3VALW

1

1

<27>

ADP_I
PR216
10K_0402_1%

<27,35>
PR231
0_0402_5%
@

2

PR222
75K_0402_1%

2

PR209
100K_0402_1%

+3VALW

1

PC204

2

2

316K_0402_1%

2

VL

0.01U_0402_25V7K

1

TMSNS21

+3VLP

VL

1

2

32
PR224
0_0402_5%
@

PR227
100K_0402_1%

2 1

12/23 improve DC mode S5 power consumtpion

C

<27,34>

PR207

1K_0402_50% 1K_0402_50% 1K_0402_50%

2

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2 1

PR206

D

OTP@
PU201

1
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2

31

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

<27,35>

1

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
2
PR212
16.49K_0402_1%
2
PR213
@ 6.49K_0402_1%
1
2
PR214
10K_0402_5%

<27,35>

EC_SMB_DA1

2

Charger

2

PC202 EMI@
0.01U_0402_25V7K

OTP@
PC203

EC_SMB_CK1

PR205

1K_0402_50%

1

0.95V
1K_0402_50%

2

CONN@
JBAT3

3V

PR204

2
1

OTP@
PR234
1
2

PR210
0_0402_5%

1
PC201 EMI@
1000P_0402_50V7K

5V

PR203
1

1K_0402_5%

2

1

2
1
PR211
100_0402_1%

ALLTO_C144PF-K07H9-L

1

2

+3VLP

1.35V

VL

EMI@ PL202
HCB2012KF-121T50_0805

P/N:SP040006C00
SP040006A00
SP040006B00

Posestor

PR202
1

2

EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%

D

Reserve

2

BATT+

2

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
GND
GND

1

1

VMB
PF201
12A_32VDC_0501012WR
1
2

1

3

12/23 PF201 change to 1206 SIZE
VMB2
CONN@
JBAT1

2

PR202 pop 1k ohm

1

EMI@ PL201
HCB2012KF-121T50_0805

1

4

PR208
100K_0402_1%

5

B

PR228

<27>

ADP_65
ECAGND

BATT_LEN#

1

<27>

D

3

1

100K_0402_1%

S

2
G

PQ205
2N7002KW_SOT323-3

135W: 150W active and 135W recovery
90W : 120W active and 90W recovery
65W : 85W active and 65W recovery
45W : 65W active and 45W recovery

A

A

Compal Secret Data

Security Classification
Issued Date

2014/03/03

2015/03/03

Deciphered Date

Title

Compal Electronics, Inc.
PWR- BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
1

34

of

46

SH00000MW00

2

1
2

2ACOFF-1
PD302

PR306
200K_0402_1%

PD303
1SS355_UMD2-2
1
2

2

2

4

1U_0603_25V6K

1

17

DH_CHG

PD301
REGN

16

PC315
1
2
4

0.047U_0603_16V7K

2

1

2

1

3
2
1

RB751V-40_SOD323-2
PC319
1U_0603_16V7

1

PR318
2.2_0603_5%
1
2

BST_CHG

16251_SN
2

18

2

LODRV

BTST

BQ24737VDD

1
3

2CHG 1

4

2

3

SRP

BATT+

SRN

DL_CHG

PC321
1

4.7UH_ETQP3W4R7WFN_5.5A_20% 0.01_1206_1%

5

HIDRV

ILIM

@ PR323
10K_0402_5%

4.7uH DCR = 35+/- 15% mohm
Power Rating = 1W
Idc~Isat = 5.5~6 A
VACP~VACN spec < 81.28mV
PL302
PR314

@EMI@ PR319
4.7_1206_5%

19

PC311
0.1U_0603_25V7K
2
1

3
5

1

@EMI@ PC320
680P_0603_50V7K

2

PR310
10_1206_5%
2
1

ACN

CMPOUT

ACP

3

4

1

BQ24737VCC

2PACIN_2
G
S

B

2
0.1U_0402_25V6

A

5

4

1
@ PC322
0.1U_0402_25V6

Module model information

VCIN1_AC_IN

PR325
10K_0402_1%

PR324
47K_0402_1%

<12,26,27>

PACIN

D

2
G
S

PR327
2

ACPRN#

3

ACPRN#

1

PQ314
<26>

2N7002KW_SOT323-3

1

2

BQ24737_V1.mdd for dual layer

PR326
10K_0402_1%
1
2

1

1

BQ24737VDD

2

**Design Notes**
Maximum Charging current 2.0A
Battery discharge power 55W.
#Register Setting
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
2. 0X12 bit3 set 1 (default 0) to enable turbo boost function
3. 0X12 bit[12:11] set 00 (default 11) to set BAT
Depletion Comparator Threshold
Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell)
4. Disable turbo when AC only
#Circuit Design
1. Make sure there is pull high for SMB on HW side
2. Use 10X10 choke and 3X3 H/L side MOSFET
Charge current 2.0A
Power loss : 1.82W
Power density : 0.81 (15X15)
3. If use 4S per cell 4.35V battery, need change PR313 to 59K for ACDET setting)
4. For hybrid design, need double check PQ301,PQ302,PQ303,PQ309 component rating
#Protect function
1. ACOVP : ACDET voltage > 3.15V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting(default)
4. CHGOCP : 3/4.5/6A based on current current setting
5. BATOVP : 104%
6. BATLOWV : 2.5V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default)
9. IFAULT LOW : 135mV (default)

PC323
0.1U_0402_25V6

2

+3VALW

2

1

Battery out function just for C38/A39 only,
other customers please remove
PQ313,PQ314,PR310,PR326

20

0_0402_5%

PQ309
2N7002KW _SOT323-3

D

C

LX_CHG

SA000051W00

SCL

1

VILIM = 20 X (VSRP - VSRN)
= 20 X ICHG X RSR

PHASE

15

Make sure this pull high
Voltage is same with EC VCC

ACOK

1

+3VLP

10

GND

PR317
316K_0402_1%
1
2

14

EC_SMB_CK1

@ PR313
1

PC314

PU301
BQ24727RGRR_VQFN20_3P5X3P5

SRP

9

SDA

2
13
1
PR321
10_0603_5%

100P_0603_50V8
8

EC_SMB_DA1

21

IOUT

SRN

7

CMPIN

5

PC312
2
2200P_0402_25V7K

TP
VCC

BM

PC313
1
2

ACDET

11

6

1

1

ADP_I

6.8_0603_5%
2
1 12
PR322

<27,34>

PR312
59K_0402_1%
1
2

PR320
100K_0402_1%

3

PR309
2
1
392K_0402_1%

0.1U_0402_25V6

PQ310
MDV1528URH 1N PDFN33-8

Rds(on) = 30mohm max
Vgs = 20V
Vds = 30V
ID = 7A (Ta=70C)

PC310
1
2

VIN

S

2

3
B

S

P2

PQ312
MDV1528URH 1N PDFN33-8

G

ACPRN#

<34,35>

3
2
1

BATT_OUT

2

1

2

PC316
0.01U_0402_25V7K
2
1

D

2N7002KW_SOT323-3

1

PQ313
2
G

1SS355_UMD2-2

1
PQ306
DTC115EUA_SC70-3

PQ308

2

PR316 @
0_0402_5%

D

VIN

1

1

ACOFF-1 2

3

2

10K_0402_1%

BATT_OUT

PC309
0.1U_0402_25V6
1
2

2

Make sure <27,34>
there is pull
high for SMB<27,34>
on
HW side!

1

AC_OFF

1 PR315

2N7002KW_SOT323-3

2
4

5

1

PQ311
DTC115EUA_SC70-3

<27>

PC308
0.1U_0402_25V6
1
2

PR305
47K_0402_1%

2
PQ307B

PR311
47K_0402_1%
1
2

PACIN

3

P2-2

1

PACIN_2

C

2N7002KDW-2N_SOT363-6

PR308
150K_0402_1%

6
PQ307A
2N7002KDW -2N_SOT363-6

D

PR304
200K_0402_1%
1
2

ACP

4 CELL: PR312 = 59.0k
Typ
Worst
L => H 18.346V
18.529V
H => L 17.925V
17.589V

PR307
20K_0402_1%

3

DTC115EUA_SC70-3

DISCHG_G

1DISCHG_G-1
2

1

P2-1
PQ305

8
7
6
5

ACN

3 CELL: PR312 = 64.9k
Typ
Worst
L => H 16.896V
17.065V
H => L 16.509V
16.199V

2

2

@EMI@ PC303
10U_0805_25V6K

ACDET

1

V1

2

PC302
5600P_0402_25V7K

1

2

PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%

2

2

3

1
PR301
47K_0402_5%

1
DTA144EUA_SC70-3

PQ303
AO4407AL_SO8
1
2
3

PC318
10U_0805_25V6K
2
1

3
1

4

2

PQ304

D

35>

1

AO4407AL Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V
ID = 10A (Ta=70C)

CHG_B+

EMI@ PL301
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

PC317
10U_0805_25V6K
2
1

PR302
0.01_1206_1%

2
1
EMI@ PC307
2200P_0402_50V7K

8
7
6
5

1

Need EC write ChargeOption() bit[8]=0
to disable iFault_Hi function.

Isat: 4A
DCR: 27mohm

2
1
@EMI@ PC306
0.1U_0402_25V6

1
2
3

4

1
2
3

4

8
7
6
5

VIN

Power Rating = 1W
VACP~VACN spec < 80.64mV

PQ302
AO4455_SO8

2
1
PC305
10U_0805_25V6K

PQ301
AO4407AL_SO8

2

2
1
PC304
10U_0805_25V6K

P2

3

B+

4

4

AO4423L Vds=-30V
Rds_on=9.4~12mohm@Vgs=-6V
P3
ID = 12.1A (Ta=70C)

2
1
@RF@
PC324
0.022U_0402_25V7K

5

AO4407AL Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V
ID = 10A (Ta=70C)

12K_0402_1%

A

For disable pre-charge circuit

2014/03/03

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/03/03

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

3

2

PWR- CHARGER_BQ24727
Document Number

Rev
1.0

LA-B291P
Sheet

Monday, March 03, 2014
1

35

of

46

A

B

C

D

E

Module model information
SY8208B_V2.mdd

1

1

EN1 and EN2 dont't floating

Change 3V5V_EN to 3VALW_EN

PC407
C407
10U_0805_25V6K
2
1

IN

EN1

IN

EN2

3
6

BS

PC403
PR403
0.01U_0402_25V7K 1K_0402_5%
1
2
1
2

3V5V_EN

1
BST_3V

3V_FB
PR405
2
2.2_0603_5%

1

PC404
2
PL402

3.3V LDO 150mA~300mA

2

PR407
2.2K_0402_5%
1
2
1

<27> VCOUT0_MAIN_PWR_ON

@ PR408
2

PC411
22U_0603_6.3V6M

1

2

2

+3VALW

JUMP_43X118

1

3V5V_EN

2

1
PR410
1M_0402_1%

1

+3VALWP

2

B+

TDC=6A
@ PJ401

0_0402_5%
1
2
0_0402_5%
@PR409
@
PR409

<34> MOS_OTP

2

Vout is 3.234V~3.366V

PC414
4.7U_0402_6.3V6M

<27> EC_ON

PC410
22U_0603_6.3V6M
2
1

2

+3VLP
Check pull up resistor of SPOK at HW side

+3VLP
PC412
4.7U_0603_6.3V6M

1

5

+3VALWP

2

LDO

@EMI@
PR406
1 3V_SN
2
1

PG

SY8208BQNC_QFN10_3X3

2

1.5UH_PCMB053T-1R5MS_6A_20%
680P_0603_50V7K 4.7_1206_5%

OUT

@EMI@ PC413
2

PR402
100K_0402_1%
1
2

GND

1

LX_3V

4

1

9

PC409
22U_0603_6.3V6M
2
1

10

LX

2

<38,39> 3V/5VALW_PG

B+

0.1U_0603_25V7K

@
@P

PC408
22U_0603_6.3V6M
2
1

PC406
10U_0805_25V6K
2
1

EMI@
PC405
2200P_0402_50V7K
2
1

8

3V_VIN

1

PR404
150K_0402_1%
2
1

PU401
7

EMI@ PL401
HCB2012KF-121T50_0805
1
2
@EMI@ PC401
0.1U_0402_25V6
2
1

B+

PR401
499K_0402_1%
1
2

ENLDO_3V5V

EN1 and EN2 dont't floating

EMI@ PL403
HCB2012KF-121T50_0805
1
2

5V_VIN

@EMI@ PC420
0.1U_0402_25V6
2
1

8

EN1
EN2
BS

1

3V5V_EN

3

5V_FB

6

BST_5V

1

PC415
PR412
6800P_0402_25V7K 1K_0402_5%
1
2
1
2
PR413
2.2_0603_5%
2

TDC=6A

PC417
0.1U_0603_25V7K
1
2

3

PL404

PC428
22U_0603_6.3V6M

PC425
22U_0603_6.3V6M
2
1

VL

PC424
22U_0603_6.3V6M
2
1

7

PC423
22U_0603_6.3V6M
2
1

LDO

+5VALWP
1

PG

SY8208CQNC_QFN10_3X3

2

1.5UH_PCMB053T-1R5MS_6A_20%

2

OUT

1

LX_5V

PC422
22U_0603_6.3V6M
2
1

VCC

10
4

680P_0603_50V7K 4.7_1206_5%

LX

@EMI@ PC427
@EMI@ PR414
2
1 5V_SN
2
1

GND

1

1

2
PC421
4.7U_0603_6.3V6M

2

5

2

9
5V_VCC

Module model information

IN

PC426
4.7U_0603_6.3V6M

@
@P

EMI@ PC419
2200P_0402_50V7K
2
1

3

PC418
C418
10U_0805_25V6K
2
1

PC416
10U_0805_25V6K
2
1

Vout is 4.998V~5.202V
PU402

@ PJ402

+5VALWP

1

1

2

2

+5VALW

JUMP_43X118

5V LDO 150mA~300mA

SY8208C_V2.mdd

4

4

Compal Secret Data

Security Classification
2014/03/03

Issued Date

2015/03/03

Deciphered Date

Title

Compal Electronics, Inc.
PWR- 3VALW/5VALW-SY8208B/C

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

36

of

46

5

4

3

2

1

Module model information
RT8207M_V1.mdd
RT8207M_V2.mdd

For Single layer
For Dual layer

D

D

PR501
2.2_0603_5%
1
2

BOOT_1.35V

+0.675VSP

PAD

VTTGND

Change CS R to your estimation value

CS

12

VDDP

VTTREF

+0.75VSP
off
off
on

VTTREF_1.5V
off
on
on

1
2

2
3
4

+VTTREFP

5

+1.35VP

FB

PC509
0.033U_0402_16V7K

FB_1.35V

6

S3

PR506
8.2K_0402_1%
1
2

+1.35VP
B

Change FB Rtop to 8.2K for 1.35V
1

7
EN_0.675VSP

TON

2

<27,32>

L/S Rds(on): 9.7mohm(Typ), 11.6mohm(Max)
Idsm: 15.4A@Ta=25C, 12.4A@Ta=70C

1

SYSON

PR508
10K_0402_1%

@ PR509
2

2

Level
L
L
H

1

0_0402_5%
@ PC514
0.1U_0402_10V7K

Choke: 7x7x3
Rdc=8.3mohm(Typ), 10mohm(Max)

1

Mode
S5
S3
S0

C

2

Co-Lay

MOSFET: 3x3 DFN
H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max)
Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C

8

B

9

PR507
887K_0402_1%
1
2
1.35V_B+

EN_1.35V

+5VALW

10

PC512
1U_0603_10V6K

VDDQ
S5

VDD

TON_1.35V

11

GND

RT8207MZQW _W QFN20_3X3

1

VDD_1.35V

13

VTTSNS

PGOOD

+5VALW

4

2

@EMI@ PC513
680P_0402_50V7K

PQ502
MDV1524_DFN8-5

PR504
5.1_0603_5%
1
2

PGND

1
2
3

2

1 2

+

@EMI@ PR503
4.7_1206_5%

2

1

ESR=9m ohm

ESR=15m ohm

PC510
330U_6.3V_M

5

1

1
2
3

PR502
13.7K_0402_1%
1
2 CS_1.35V
PC508
1U_0603_10V6K
1
2

21

2

14

PL502
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2

PC506
10U_0805_6.3V6K

20
VTT

PU501

1

LGATE

19

1
15

MDV1528URH 1N PDFN33-8

VLDOIN

DL_1.35V

BOOT

4

17

PHASE

PQ501

18

16

2

5

1

SW _1.35V
PC505
0.1U_0603_25V7K

PC507
10U_0805_6.3V6K

DH_1.35V

C

+1.35VP

0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A

+1.35VP

UGATE

1
2

BST_1.35V

PC504
10U_0805_25V6K

2

1

PC503
10U_0805_25V6K

1
2

EMI@
PC502
2200P_0402_50V7K

2

1

1.35V_B+
@EMI@
PC501
0.1U_0402_25V6

B+

Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question,
you can change from +1.35VP to +1.35VS.

EMI@ PL501
HCB2012KF-121T50_0805
1
2

Note: S3 - sleep ; S5 - power off
Switching Frequency: 285kHz
Ipeak=10A
Iocp~13A
OVP: 110%~120%
MOSFET footprint: SIS412DN

PR510
1
2
0_0402_5%

@ PJ501

1

+1.35VP

2

1

2

2

+1.35V

JUMP_43X118
@ PJ502
1
2
1
2

1

<27,32,39> SUSP#

@ PC515
0.1U_0402_10V7K

JUMP_43X118
PJ503 @

1

+0.675VSP

1

2

2

+0.675VS

JUMP_43X39

A

Compal Secret Data

Security Classification
Issued Date

2014/03/03

Deciphered Date

2015/03/03

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.

PWR-+1.35VP/ +0.675VS

Size
Document Number
Custom
Date:

A

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
1

37

of

46

A

B

C

D

Module model information
SY8208D_V2.mdd
1

1

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
PR601
0_0402_5%
1
2

095_18ALW_PWR_EN

3V/5VALW_PG

<27,39>

<36,39>

1

1

@ PR610
0_0402_5%
1
2

+0.95VALW P
1

@ PC601
0.22U_0402_10V6K

1

PJ601
2
2

JUMP_43X118

+0.95VALW

@

2

2

1M_0402_1%
PR602

@EMI@ PR603
@EMI@ PC602
4.7_1206_5%
680P_0603_50V7K
1
2SNB_0.95V1
2

2

2

1

PC612
22U_0603_6.3V6M

2

1

PC611
22U_0603_6.3V6M

1

2

FB = 0.6V

PR609

Rdown

20K_0402_1%
2

2

+3VALW

1

SY8208DQNC_QFN10_3X3
PR608 @
0_0402_5%

PC614
4.7U_0603_6.3V6K

0.95LDO_3V

2

5

2

Rup

7

1

4

1

FB
ILMT_0.95V3

2

LDO

+0.95VALWP
PC610
47U_0805_6.3V6M

PG

TDC 8A

PL602
1UH_11A_20%_7X7X3_M
1
2

1

BYP

LX_0.95V

2

ILMT

PC606
0.1U_0603_25V7K
1
2

PC609
47U_0805_6.3V6M

LX

10

PR604
0_0603_5%
2

1

GND

1
BST_0.95V

1

9

6

2

BS

PC608
330P_0402_50V7K

EN

PR606
11.8K_0402_1%

IN

1

PC613
4.7U_0603_6.3V6K

10U_0805_25V6K
PC605
2
1

8

2

ILMT_0.95V

1

2

PR605 @
0_0402_5%

B+_0.95V
10U_0805_25V6K
PC607
2
1

1

0.95LDO_3V

2

PU601

@EMI@
PC604
0.1U_0402_25V6
2
1

EMI@
PC603
2200P_0402_50V7K
2
1

B+

EMI@ PL601
HCB2012KF-121T50_0805
1
2

Pin 7 BYP is for CS.
Common NB can delete

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

+3VALW and PC15

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

3

3

Vout=0.95V

4

4

Compal Secret Data

Security Classification
Issued Date

2014/03/03

Deciphered Date

2015/03/03

Title

Compal Electronics, Inc.
PWR- +0.95VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

LA-B291P

Monday, March 03, 2014
D

Sheet

38

of

46

A

B

C

D

Module model information
SY8003_V2.mdd

1

1

PR701
0_0402_5%
1
2

1

0.1U_0402_16V7K
PC701
2
1

2

FB_1.8V

FB=0.6V

2

Note:Iload(max)=3A

PR706
10K_0402_1%

1
2

Rup

@
2

2

+1.8VALW

PC705
22U_0603_6.3V6M

PR705
20K_0402_1%

1

2

SY8003DFC_DFN8_2X2

PJ701
1
1

+1.8VALWP

JUMP_43X79
1

5

+1.8VALWP

2

NC

1
2
1UH_2.8A_30%_4X4X2_F

PC704
22U_0603_6.3V6M

PGND

PL701

LX_1.8V

6

PC703
68P_0402_50V8J
2
1

2

22U_0603_6.3V6M

2

LX

1

4

PC702

IN

7

Note:Iload(max)=2.5A

2

JUMP_43X79

EN

<36,38>

2

Rdown
2

2

3

1

1

2

PGND
SGND

PG

@EMI@
PC706
680P_0402_50V7K

1

1

+3VALW

FB

1

2

@EMI@
PR704
4.7_0603_5%

1
@
PJ702

9
8

3V/5VALW_PG

<27,38>

PR703
1M_0402_5%

@

PU701

095_18ALW_PWR_EN

@ PR712
0_0402_5%
1
2

+1.8VSP_ON

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)

+3VS

+5VALW

3

3

2

2

JUMP_43X79
@ PJ703

2

1

1

1

Ultra Low Dropout 0.23V(typical) at 3A Output Current
PC707
1U_0402_6.3V6K

Module model information

2

Rdown

APL5930_V2.mdd

@
1

+1.5VSP

PJ704
1

2

2

+1.5VS

2

1

JUMP_43X79
PC711
22U_0603_6.3V6M

1
2

Rup

PC710
0.01U_0402_25V7K

1
2

PR709
1.54K_0402_1%

FB

2

EN
POK

1

@ PR708
100K_0402_5%

2

+1.5VSP

PR711
1.74K_0402_1%

1

8
7

GND

2

+3VS
PC709
0.1U_0402_16V7K

2

2

PR710
47K_0402_5%

1

SUSP#

1

<27,32,37>

PR707
100K_0402_5%
1
2

1

1

PU702
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT

PC708
4.7U_0603_6.3V6K

4

4

Vout=0.8V* (1+Rup/Rdown)
Compal Secret Data

Security Classification
Issued Date

2014/03/03

Deciphered Date

2015/03/03

Title

Compal Electronics, Inc.
PWR- +1.8VALW/ +1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

LA-B291P

Monday, March 03, 2014
D

Sheet

39

of

46

5

4

3

2

10_0402_5%
1
2

PC808
100P_0402_50V8J
1
2

PHASE_NB1

BOOT_NB1

2

PR814 set 390 ohm to OCP 19A
3
2
1

2
@PC815
@
PC815
220P_0402_50V7K
1
2

@ PR816
100_0402_1%
1
2

LGATE_NB1

PC801
33U_25V_M

PC802
33U_25V_M

B+

PL802
.36UH 20% PDME064T-R36MS1R405 24A

1

4

2

3

+APU_CORE_NB

@EMI@
PR811
4.7_1206_5%

D

PR813
3.65K_0402_1%
2
VSUMP_NB 1

@EMI@
PC813

PR815
1_0402_1%
2
VSUMN_NB 1

APU_CORE_NB
TDC 13A
Peak Current 17A
OCP current 21.49A
Load line -4mV/A
FSW=300kHz

+APU_CORE_NB

+5VALW

@ PR829

PR831
2.2_0603_1%
2
BOOT11

3
2
1

+

2
<5>

+

2

1
+

2

@

1
PC861
1
PC862
1
PC863
1
PC864
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M

@

@

@

2014/03/03

@

A

Compal Secret Data

Security Classification
Issued Date

@

1
PC857
1
PC858
1
PC859
1
PC860

2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M

@

2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M

1
PC853
1
PC854
1
PC855
1
PC856

1
PC850
1
PC851
1
PC852
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M

@

@

PC868
2
1

1
PC846
1
PC847
1
PC848
1
PC849

10U_0603 * 4
+APU_CORE_NB

0.01U_0402_25V7K~N

@

@

B

Power Dissipation: H/S 0.720W
L/S 0.876W

10U_0603 *3
+APU_CORE

2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M

APU_VDD_RUN_FB_L

1

PC840
330U_D2_2V_Y

1
<5>

PC867
2
1

A

APU_core
TDC 15A
Peak Current 21A
OCP current 26.32A
Load line -4mV/A
FSW=300kHz

+APU_CORE

APU_VDD_SEN

+APU_CORE

MDU1511RH_POWERDFN56-8-5

2

0_0402_5%
@ PR846
PR847
10_0402_5%
1
2

3

+APU_CORE

PC865
2
1

2

1

PC841
0.01U_0402_50V7K

1

4

2

PR839
1_0402_1%
1
2

VSUM-

0.01U_0402_25V7K~N

PR1046 set 536 ohm to OCP 26.32A

PC835
330P_0402_50V7K
1
2

@EMI@
PC830
680P_0603_50V7K

0.1U_0402_25V7K~N

@ PR845
0_0402_5%
1
2

4

LGATE1

1

PR835
3.65K_0402_1%
1
2
VSUM+

PC839
330U_D2_2V_Y

PR843
10_0402_5%
1
2

@ PC837
@ PR844 820P_0402_50V7K
100_0402_1%
1
2
1
2

PR1039=3.65K, PR1040=1.58K and
PR1046=453 to set loadline -4mV/A
while PR1013=453 to set OCP 22.54A
for EDC 18A application.

PR841
2K_0402_1%
1
2

PQ804

1
PC842
1
PC843
1
PC844
1
PC845

PC836
0.1U_0603_50V7K

PR838
PC832
137K_0402_1% 390P_0402_50V7K
1
2
1
2

2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M

PR842
536_0402_1%
1
2

@ PR834
32.4K_0402_1%
1
2

PC866
2
1

330P_0402_50V7K

1
2

@ PC831

PC834
0.15U_0603_16V7K

1
2

PC833
0.01U_0402_50V7K
2
1

1
PR840
11K_0402_1%
2

PR1039=3.65K, PR1040=1.87K and
PR1046=536 to set loadline -4mV/A

2

0.1U_0402_25V7K~N

2

@

PR837
1.87K_0402_1%
1
2

1

@EMI@
PR832
4.7_1206_5%

1 2

PC828
PR833
1000P_0402_50V7K 301_0402_1%
1
2
1
2

PC827
0.22U_0603_25V7K
1
2

5

PC829
100P_0402_50V8J

SH00000NX00 (DCR:1.4± 5%)
PL803
.36UH 20% PDME064T-R36MS1R405 24A

2

ISEN1

PR830
10K_0402_1%

1

VSUM-

4

PHASE1

PH804
10K_0402_5%_ERTJ0ER103J
2
1 2
1
PR836
2.61K_0402_1%

B

2

0_0402_5%

3
2
1

+5VS

VSUM+

PH1003 near APU_CORE_NB choke

1

1

UGATE1
<27>

EMI@ PC826
0.1U_0402_25V6K
2
1

PR826
100K_0402_1%

@EMI@ PC825
2200P_0402_50V7K
2
1

5

1

PGOOD

+3VS

PC838
330U_D2_2V_Y

BOOT1

PC824
10U_0805_25V6K
2
1

21

C

CPU_B+

PC823
10U_0805_25V6K
2
1

UGATE1

2

22

2

LGATE1
PHASE1

1

1
2
1_0603_5%

24

1

25

23

PC821
1U_0603_10V6K

PR822

VGATE

2

Power Dissipation: H/S 0.5811W
L/S 0.6756W

26

1
2
PH803
470K_0402_5%_TSM0B474J4702RE

1

+

2

29

27

PH1002 near APU_CORE H/S mos

VRHOT Assert Threshold : 0.64V
TSENSE Bias Current : 30uA
PH1002=27.4K, 110C active
Reset Threshold: 0.66V, 98C active
110C Assert Threshold: PR1031=27.4K
100C Assert Threshold: PR1031=16.9K

1

PC818
330U_D2_2V_Y

2

PC816
330U_D2_2V_Y

ISL62771_V1B.mdd for SW portion

PQ803
MDU1516URH_POWERDFN56-8-5

PR827
10.5K_0402_1%
2

COMP

BOOT1

+

28

PC820
1U_0603_10V6K

32

31
BOOT_NB

UGATE_NB

34

33

LGATE_NB

PHASE_NB

36

37

38

35
PGOOD_NB

COMP_NB

FB_NB

IMON

1

ISL62771_V1A.mdd for IC portion

2

1

VSEN_NB

40

39

UGATE1

30

20

10

IMON

<27> APU_IMON
2 PC822
1000P_0402_50V7K
PR828
27.4K_0402_1%
1
2

PHASE1

PWROK

FB

1

ENABLE

RTN

2

PR825
133K_0402_1%

LGATE1

19

1

SVC, SVD, SVT, ENABLE and
PWROK no need pull high for
AMD KABINI

VDD

SVT

18

9

1.8VS for DDRII voltage level <5> APU_PWRGD
1.5VS for DDRIII voltage level

VDDIO

17

VR_ON

8

ENABLE

VSEN

<27>

7
@ PR824
1
2
0_0402_5%

NTC

VDDIO pin:

2
0_0402_5%
PC819
0.1U_0402_25V6K

16

6

VDDIO

1PR823

VDDP

ISL62771HRTZ-T_TQFN40_5X5

ISUMN

APU_SVT

1 @ PR821 2 0_0402_5%
@

LGATE2

SVD

ISUMP

+1.5VS

VR_HOT_L

ISEN1

<5>

5

15

APU_SVD

PHASE2

12

<5>

BOOT2
UGATE2

SVC

11

100K_0402_1%
2

2

C

2

Module model information

IMON_NB

14

4

NTC_NB

13

3

APU_SVC

1

+1.8VS

2

IMON_NB
<5>

ISEN2

1

ISUMN_NB

PU801

41

2

TP

1

PH802 470K_0402_5%_TSM0B474J4702RE

PH1001 near APU_CORE_NB H/S mos

@ PR820
1

+

BOOT_NB1
PR817
10.5K_0402_1%
1
2

2

ISUMP_NB

PR818
27.4K_0402_1%
1

2
PC817 1000P_0402_50V7K

PROCHOT#

2

1

UGATE_NB1

133K_0402_1%
1
2

+3VS

+

PHASE_NB1

VRHOT Assert Threshold : 0.64V
TSENSE Bias Current : 30uA
PH1001=27.4K, 110C active
Reset Threshold: 0.66V, 98C active
110C Assert Threshold: PR1016=27.4K
100C Assert Threshold: PR1016=16.9K

<27>

4

LGATE_NB1
PR814
390_0402_1%

0.1U_0603_50V7K

1

5

PR1012=3.65K, PR1003=1.33K and
PR1013=374 to set loadline -4mV/A
while PR1013=374 to set OCP 18.8A
for EDC 15A application.

1

SH00000NX00 (DCR:1.4± 5%)

PR810
PC809
2.2_0603_1%
0.22U_0603_25V7K
1
2 1
2
PQ802

PC812
0.15U_0603_16V7K

2

1

@ PC811
0.022U_0402_25V7K
2
1

2

1
PR812
11K_0402_1%

PH801
10K_0402_5%_ERTJ0ER103J
2
1 2
1
PR809
2.61K_0402_1%

1
PC814

2

1

1

PH1000 near APU_CORE_NB choke

PR819

4

1

PC807
0_0402_5% 1000P_0402_50V7K
1
2
1
2 1
2
PR808
PC810
301_0402_1%
0.01U_0402_50V7K

VSUMP_NB

VSUMN_NB

2

0_0402_5%

MDU1511RH 1N POWERDFN56-8

@ PR807

D

1

3
2
1

+APU_CORE_NB

@ PR806
PR805
PC806
137K_0402_1% 390P_0402_50V7K
41.2K_0402_1%
1
2
1
2
1
2

PC804
10U_0805_25V6K
2
1

@ PR801
UGATE_NB1

PR804
1.33K_0402_1%
1
2

680P_0603_50V7K
2
1 2

PR802
2K_0402_1%
1
2

PR803

APU_VDDNB_SEN

PC803
10U_0805_25V6K
2
1

PQ801
MDU1516URH_POWERDFN56-8-5

5
PC805
330P_0402_50V7K
1
2
<5>

PR1012=3.65K, PR1003=1.5K and
PR1013=432 to set loadline -4mV/A

1

EMI@ PL801
HCB2012KF-121T50_0805
1
2

CPU_B+

Deciphered Date

2015/03/03

Title

Compal Electronics, Inc.
PWR- APU_CORE/APU_CORE_NB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

LA-B291P

Monday, March 03, 2014
1

Sheet

40

of

46

5

4

3

2

1

+VGA_CORE
AMD JET LE
TDC 20A
EDC 30A

GPU_B+

Module model information
EMI@ PL901
HCB2012KF-121T50_0805

ISL62771_V1A.mdd for IC portion

1

PQ901

7
@ PR904
UGATE1

1

2

1

0_0402_5%

2

G2
S1/D2
S2
G1
S2
D1
S2

6
5

1
2

PC906
0.22U_0603_25V7K
1
2

B+

2

PC905
10U_0805_25V6K
2
1

PR905
2.2_0603_1%
2
BOOT11

PC904
10U_0805_25V6K

@EMI@ PC902
0.1U_0402_25V6
2
1

PHASE1

D

EMI@ PC903
2200P_0402_50V7K
2
1

LGATE1

ISL62771_V1B.mdd for SW portion

D

4
3

PR902
LGATE_NB1

PHASE2

27

LGATE2

VSUM+

PR908
3.65K_0603_1%
1
2

VSUM-

PR910
1_0402_1%
1
2

+5VALW

PC909
330U_D2_2V_Y

PC908
330U_D2_2V_Y

PC907
390U_2.5V_M

+

2

PHASE2
PC922
0.22U_0603_25V7K
1
2

PQ902

1

PR928
2.2_0603_1%
2
BOOT21

7
0_0402_5% PR921
1
2
UGATE2 25W@
25W@

PR917
100K_0402_1%

1
2

G2
S1/D2
S2
G1
S2
D1
S2

<41,7>

6

@EMI@

5

@EMI@

1

+3VS

2

BOOT1

C

PC918
10U_0805_25V6K
2
1

21

2

4
3

25W@

25W@

AON6932A_DFN5X6-8-7
25W@

2

+VGA_CORE

1

@ PR923
32.4K_0402_1%
1
2

PR925
PC923
137K_0402_1% 390P_0402_50V7K
1
2
1
2

PC926
330P_0402_50V7K
1
2

2

PR930
2K_0402_1%
1
2

+VGA_CORE

ISEN1

25W@

B

Power Dissipation: H/S 0.720W
L/S 0.876W
PC944
2.2U_0402_6.3V6M
2
1

PC945
2.2U_0402_6.3V6M
2
1

PC959
0.1U_0402_10V7K
2
1

PC960
0.1U_0402_10V7K
2
1

PC946
2.2U_0402_6.3V6M

PC943
2.2U_0402_6.3V6M
2
1
PC958
0.1U_0402_10V7K
2
1

PC942
2.2U_0402_6.3V6M
2
1

PC957
1U_0402_6.3V6K
2
1

PC941
2.2U_0402_6.3V6M
2
1

PC937
2.2U_0402_6.3V6M
2
1
PC953
10U_0603_6.3V6M

PC940
2.2U_0402_6.3V6M
2
1

PC936
2.2U_0402_6.3V6M
2
1
PC952
10U_0603_6.3V6M
2
1

2

PC956
1U_0402_6.3V6K
2
1

PC935
2.2U_0402_6.3V6M
2
1
PC951
10U_0603_6.3V6M
2
1

15W@ PC925
0.1U_0603_25V7K

PC939
2.2U_0402_6.3V6M
2
1

PC934
2.2U_0402_6.3V6M
2
1

<12>

PC950
10U_0603_6.3V6M
2
1

GPU_VDD_RUN_FB_L

1

15W@ PR924
1K_0402_1%

25W@

<12>

PC933
2.2U_0402_6.3V6M
2
1

GPU_VDD_SEN

PC932
2.2U_0402_6.3V6M
2
1

@ PR933
0_0402_5%
2

@ PR935
0_0402_5%
1
2
PR936
10_0402_5%
1
2

15W@ PR931
536_0402_1%

PR931=536 ohm, PR924=1K ohm, PC925=0.1uF,
PR944 =0 ohm, PR920=10K ohm,
PC961 @, PC962 @, PR938 @ and PR939 @
while PR931=536 ohm to set OCP for GPU 15W application.

PR943
10K_0402_1%
1
2

PR941
1_0402_1%
25W@
1
2

VSUM-

2

1
2

GPU 15W setting

25W@

PC927 @EMI@
680P_0603_50V7K

PC949
10U_0603_6.3V6M
2
1

1

PR940
10K_0402_1%
1
2

PR942
3.65K_0603_1%
25W@
1
2
VSUM+

PC948
10U_0603_6.3V6M
2
1

@ PC929
@ PR934 820P_0402_50V7K
100_0402_1%
1
2
1
2

ISEN2

+VGA_CORE

1

PR932
10_0402_5%
1
2

PR929 @EMI@
4.7_1206_5%

PC931
2.2U_0402_6.3V6M
2
1

25W@PR931
332_0402_1%
1
2

4
PL903
0.22UH_PCME064T-R22MS_28A_20%
3

2

1 2

330P_0402_50V7K

1
2

@ PC921

25W@PR924
1.54K_0402_1%
1
2

1

1

PC920
100P_0402_50V8J

PC919
PR922
1000P_0402_50V7K 301_0402_1%
1
2
1
2

PC947
10U_0603_6.3V6M
2
1

1

PC925
0.15U_0603_16V7K

PC924
0.047U_0402_25V7K
2
1

1
2

1
PR927
11K_0402_1%
2

PC928
0.1U_0603_50V7K

2

1

GPU_B+

LGATE2

PC917
10U_0805_25V6K

UGATE1

1

22

2

LGATE1
PHASE1

25W@

PC930
0.01U_0402_50V7K

2

1

VSUM-

PH902
10K_0402_5%_ERTJ0ER103J
2
1 2
1
PR926
2.61K_0402_1%

B

+

1/7 change to H=6 CAP_SF000002O00

PC916
2200P_0402_50V7K
2
1

1
2
1_0603_5%

24

1

25

23

25W@

25W@

2

1

PR913

ISEN1

ISEN2
25W@
VSUM-

2

+

26

DGPU_PWROK

PC962
0.22U_0402_10V6K

15W

VSUM+

ISEN2

1

2

PC911 @EMI@
680P_0603_50V7K

25W

2

10K_0402_1%

15W@

PC961
0.22U_0402_10V6K
2
1

2
PR944

15W@
+5VS

1

VRHOT Assert Threshold : 0.64V
TSENSE Bias Current : 30uA
PH1002=27.4K, 110C active
Reset Threshold: 0.66V, 98C active
110C Assert Threshold: PR1031=27.4K
100C Assert Threshold: PR1031=16.9K

0_0402_5%
PR920
1
2

1
2
PH901
470K_0402_5%_TSM0B474J4702RE

+

25W@PR939
25W@
PR939
10K_0402_1%
1
2

PC910
390U_2.5V_M

1

25W@PR938
25W@
PR938
10K_0402_1%
1
2
ISEN1

2
28

1

UGATE2

PGOOD

COMP

RTN

BOOT2

29

20

19

18

FB

BOOT1

30

PC913
1U_0603_10V6K

UGATE1

17

1
PR907 @EMI@
4.7_1206_5%

2

PHASE1

PWROK

PR918
10.5K_0402_1%
1
2

+5VALW

PC912
1U_0603_10V6K

32

31
BOOT_NB

UGATE_NB

34

33

LGATE_NB

PHASE_NB

ENABLE

IMON

4
PL902
0.22UH_PCME064T-R22MS_28A_20%
3

2

PC915
0.1U_0402_25V6
2
1

2
36

37

38

35
PGOOD_NB

COMP_NB

FB_NB

LGATE1

2 PC914
1000P_0402_50V7K
PR919
27.4K_0402_1%
1
2

VSEN_NB

40

39

VDD

SVT

NTC

1

VDDIO

VSEN

10

IMON

PR916
133K_0402_1%

VDDP

ISL62771HRTZ-T_TQFN40_5X5

16

9

0_0402_5%

2

8

SVD

11

1

DGPU_PWROK

ENABLE

LGATE2

12

<41,7>

7
@ PR915
1
2
0_0402_5%
1 @ PR937 2

PHASE2

VR_HOT_L

ISUMN

6

VDDIO

0_0402_5%
<12> GPU_SVT
2
PC901
<13,27> GPU_PWR_EN
0.1U_0402_25V6K

SVC

ISUMP

5

ISEN1

4

BOOT2
UGATE2

15

3

1
1_0402_5%

IMON_NB

14

GPU_SVC

NTC_NB

13

2

ISUMN_NB

1

100K_0402_1%
1
2 IMON_NB

ISEN2

100K_0402_1%
1
2

PR909

GPU_SVD

SVC, SVD, SVT, ENABLE and
PWROK no need pull high for
AMD KABINI

41
TP

PR901

<12>

@PR914
1

ISUMP_NB

PU901

GPU_PROCHOT#
@ PR911 100K_0402_1%
1
2
+3VS
<12>
@ PR912
1
20_0402_5%
+1.8VGS

+1.5VS

+VGA_CORE

1

PR906

2

C

PR903
10K_0402_1%
2
UGATE_NB1 1
BOOT_NB12

1

<12>

SH00000NX00 (DCR:1.4± 5%)

10K_0402_1%
1
2

PHASE_NB1

PC955
1U_0402_6.3V6K
2
1

VRHOT Assert Threshold : 0.64V
TSENSE Bias Current : 30uA
PH1001=27.4K, 110C active
Reset Threshold: 0.66V, 98C active
110C Assert Threshold: PR1016=27.4K
100C Assert Threshold: PR1016=16.9K

PR945
41.2K_0402_1%

PC938
2.2U_0402_6.3V6M
2
1

Fsw=400K Hz

@ PR947
1
2
0_0402_5%

PC954
1U_0402_6.3V6K
2
1

@ PR946
1
2
0_0402_5%

1

AON6932A_DFN5X6-8-7

A

A

Compal Secret Data

Security Classification
Issued Date

2014/03/03

Deciphered Date

2015/03/03

Title

Compal Electronics, Inc.
PWR- +VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

LA-B291P

Monday, March 03, 2014
1

Sheet

41

of

46

A

B

C

B+

D

E

+3VLP

EC_ON

+EC_VCCA

PU401
SY8208BQNC

+3VALW

+3V_LAN

1

1

SUSP#

U13
APE8990GN3B

+3VS
3VGS_PWR_EN

QV16
LP2301ALT1G

+3VGS
SUSP#

PU702
APL5930KAI

+1.5VS

095_18ALW_PWR_EN

PU701

+1.8VALW
SUSP#

U1895P
APE8990GN3B

+1.8VS

2

2

GPU_PWR_EN

U1895V
APE8990GN3B

+1.8VGS

EC_ON

+VL

PU402
SY8208CQNC

+5VALW
SUSP#

U13
APE8990GN3B

+5VS

SUSP# / SYSON

+0.675VS

PU501
RT8207MZQW

+1.35V
GPU_PWR_EN#

UV3
AP4800BGM-HF

3

+1.35VGS
3

095_18ALW_PWR_EN

PU601
SY8208DQNC

+0.95VALW
095VS_PWR_EN

U1895P
APE8990GN3B

+0.95VS
GPU_PWR_EN

U1895V
APE8990GN3B

+0.95VGS

GPU_PWR_EN

PU901
ISL62771HRTZ-T

+VGA_CORE

VR_ON

+APU_CORE

PU801
ISL62771HRTZ-T

+APU_CORE_NB

4

4

Compal Secret Data

Security Classification
2014/03/03

Issued Date

2015/03/03

Deciphered Date

Title

Compal Electronics, Inc.
PWR DCIN / RTC Battery

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
E

42

of

46

5

4

B+

+3VS / +1.8VS / +1.5VS / +0.95VS

+3VALW

+APU_CORE / +APU_CORE_NB

3B

KBRST#

5

SYS_PWRGD_EC

17

LPC_RST#

19

V

13

GPU_PWR_EN

12

+5VS / +3VS / +1.8VS

095VS_PWR_EN

+3VALW +5VALW

V
V

V

21

QV16
+3VGS

UV14
+1.35VGS

+3VALW

V

+5VALW

+0.95VALW +5VALW

B+

PU501
+0.675VS

V
4

LAN

+1.5V +5VALW

U1895P
+1.8VS

Issued Date

5

U1895V
+0.95VGS

U1895P
+0.95VS

A

Compal Secret Data

Security Classification

COMPAL CONFIDENTIAL

+3VS +5VALW

B

+1.8VALW +5VALW

+1.5V

MODEL NAME:
PCB NAME:
REVISION:
DATE: 2014/03/03

+3V_LAN

+0.95VALW +5VALW

U13
+5VS

V

V

U13
+3VS

PU702
+1.5VS

A

+5VS +3VS

PU901
+VGA_CORE

V

BATT+

PU301
B+

+1.8VALW +5VALW

9

B+

PU102
+RTCBATT

11

WLAN / WiMAX
NGFF WLAN/BT Card
C

V

+5VALW

PU501
+1.35V

VGA_PEWGD

+1.5VA

+5VALW

V

+3VALW

VIN

14

GPU
Jet LE S3

+3VS

B+

U1895V
+1.8VGS
SUSP#

VGATE

SYSON

PU801
+APU_CORE /
+APU_CORE_NB

8

+CHGRTC_R +3VLP

APU_PWRGD

16

RTC Battery
+CHGRTC_R
B

18

GPU_RST#

V

V

15

V

VR_ON

APU_PCIE_RST#

V

BATT MODE
BATT+

20

B+

18
APU_PWRGD

23

AND
GATE

V
DGPU_PWR_EN

V

V

V V

V

ON/OFF

PXS_RST#

V

EC_ON

1B

AC MODE
VIN

10

V

2B

ACIN

+5VALW

22

3B

C

4A

APU

7

SLP_S3# / SLP_S5#

V

1A

D

5

SPOK

PU401
+3VALW/+3VLP
2A

6

V

3A

PU402
+5VALW / VL

PBTN_OUT#

+VGA_CORE

+3VGS

V

V V

V

4A
B+

5

+1.8VGS / +0.95VGS

V V

095_18ALW_PWR_EN

EC_RSMRST#

V V

EC

3B

V

V V

V

3A

B+

+3VGS / +1.35VGS

+RTCBATT

PU601
+0.95VALW

V

PU502
+1.8VALW

1

+3VALW / +1.8VALW / +1.5VALW / +0.95VALW
+3VLP

D

2

V

+3VALW

3

2014/03/03

2015/03/03

Deciphered Date

Title

Compal Electronics, Inc.
Power Sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

3

2

Rev
1.0

LA-B291P

Monday, March 03, 2014

Sheet
1

43

of

46

www.s-manuals.com



---

Source Exif Data:

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XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Format                          : application/pdf
Creator                         : 
Title                           : Compal LA-B291P - Schematics. www.s-manuals.com.
Subject                         : Compal LA-B291P - Schematics. www.s-manuals.com.
Create Date                     : 2014:03:03 15:11:57Z
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Modify Date                     : 2015:04:06 01:40:06+03:00
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Page Count                      : 44
Keywords                        : Compal, LA-B291P, -, Schematics., www.s-manuals.com.
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