Compal LA B541P Schematics. Www.s Manuals.com. R0.1 Schematics
User Manual: Motherboard Compal LA-B541P ZAR00 Delray 17 - Schematics. Free.
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : ZAR00
PCB NO : LA-B541P
BOM P/N : i5 - 4319TQ31L01 (HSW)
i7 - 4319TQ31L02 (HSW)
1
GPIO MAP: GPIO map rev 3.6C
Delray 17
Broadwell H-type (2 chip)
2
2
REV : 0.1 (X00)
2014.01.13
@ : Nopop Component
EMC@ : EMI/ESD/RF part
CONN@ : Connector Component
PXDP@,CXDP@ : Total debug Component (pop them until ST)
3
3
TB@ : Thunderbolt function
BDW@ : HSW_BDW compatibility circuit
Layout Dell logo
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: X00
PWB: XXXXX
DATE: 1403-06
4
4
PCB_178_LA-B541P_REV0_MB
Part
Description
Number
DAA0008R000
DELL CONFIDENTIAL/PROPRIETARY
PCB 178 LA-B541P REV0 MB
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Power CKT: 0108
Title
Cover Sheet
Size
B
C
D
Rev
0.1
LA-B541P
Date:
A
Document Number
Monday, January 13, 2014
Sheet
E
1
of
67
A
B
C
D
E
Lane x2
eDP
eDP MUX
PS8331
P.30
P.29
DDID
PEG x16 (Gen3)
M.2
WiGig
Conn P.42
1
DP DEMUX
PS8338
P.37
Docking DP Port1
P.31
DPB
DP/HDMI
DEMUX
PS8339 P.38
HDMI 1.4a
Conn
P.38
CRT Conn
2
P.35
P.35
CRT
Port 2
SATA Port 5
Intel Clarkville
WGI218LM
P.39
P.6
M.2 Card slot_3
SSD/HCA/Cache
P.43
Port 7
Port 1
SATA Port 4
USB 3.0 Conn
Right Side
USB Charger
USB Power Share
TPS2544 P.47
P.47
HD Audio
USB 3.0 Conn
Left Side
USB3 Port 6
USB 3.0 Repeater
PS8713B P.7
USB 3.0 Conn
Left Side
P.7
USB 3.0 Repeater
PS8713B P.8
USB 3.0 Conn
Left Side
P.8
USB2 Port 0
USB Port 4
LPC BUS
SMSC SIO
ECE5048
BC BUS
P.50
P.40
W25Q64FVSSIQ
USB2 Port 8
Digital Camera
USB2 Port 11
Touch screen
P.21
P.30
64M 4K sector
P.30
W25Q32FVSSIQ
SMSC KBC
MEC5085
3
P.21
32M 4K sector
BCM20793
P.51
Discrete TPM
AT97SC3205
FAN CONN
P.42
SATA Port 2
KB/TP CONN
P.27
USB Port 7
P.53
BRCM5882
TPM 1.2
Smart Card
RFID
DAI
LNG3DMTR
P.45
Current Monitor
INA219AIDCNRG4
P.28
FP_USB
RGB
LAN
3
NFC
TDA8034HN
P.41
USB2 Port 3
USB2 Port 6
Free Fall Sensor
P.7
On I/O board
Docking LAN
Micro SIM Card
2
USB 3.0 Repeater
PS8713B P.7
USB3 Port 1
P.39
RJ45
P.46
USB3 Port 5
USB2 Port 9
P.18~26
USB 3.0 Repeater
PS8713B P.47
USB2 Port 2
USB3.0
USB2.0
P.42
USB Port 5
USB2 Port 1
Port 8
PI3L720ZHEX
On I/O board
Intel
Lynx Point
BGA
695 Pins
M.2 Card slot_2
M.2 Card slot_1
WWAN/LTE/HCA/ WLAN/BT/WiGig
Cache
P.42
USB Port 10
LAN switch
SDXC P.6
ODD Conn.
USB3 Port 2
PCIE BUS
OZ777FJ2LN-B
SD4.0/MMC
DMI x4 gen 2
P.17
CRT
Port 3
2nd HDD Conn.
SATA Port 1
CRT (MXM)
Port 4
SATA Port 3
DPC
Docking RGB
1
P.45
FDI x2
Docking DP Port2
CRT switch
MAX14885
1st HDD Conn.
SATA3.0
SATA2.0
CRT
PCIE
Port 5, Port 6
P.13~16
P.45
DP_C
P.31
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
SATA Port 0
P.6~12
MXM Conn.
DP_A
TYPE B
DDRIII-DIMM X4
(DDRIII) Memory Bus
1.5V DDRIII 1333 /1600 /1866MHz (Overclocking)
DP_B
P.36
P.32 - 34
PEG
DP_D
DP MUX
PS8331
DP SW
PS8338B
TBT
P.33
DDID
DPA
DP 1.2
Conn
TBT
Conn
Intel
Broadwell
BGA CPU
1364 Pins
(H type)
Lane x4
SPI
eDP Panel
Conn
On USH/B
E-Dock
USB3.0 Port 3
Fingerprint
CONN
P.41
Universal Jack P.5
LPC
Audio Codec
ALC3235
Docking DP
Array MIC Jack
P.4
Int. Speaker
P.4
P.4
4
4
Docking DP
P.48
On I/O board
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Block Diagram
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
E
Sheet
2
of
67
5
4
3
2
1
POWER STATES
SLP
S3#
SLP
S4#
SLP
S5#
S4
STATE#
SLP
M#
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
HIGH
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
S4 (Suspend to DISK) / M1
LOW
LOW
HIGH
S5 (SOFT OFF) / M1
LOW
LOW
S3 (Suspend to RAM) / M-OFF
LOW
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
State
D
ALWAYS
PLANE
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
ON
ON
HIGH
ON
ON
ON
OFF
OFF
LOW
HIGH
ON
ON
OFF
OFF
OFF
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
HIGH
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
LOW
LOW
HIGH
LOW
LOW
ON
OFF
OFF
OFF
OFF
LOW
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
USB PORT#
CLOCKS
PCH
PM TABLE
C
power
plane
+PWR_SRC
+3.3V_SUS
+5V_RUN
+3.3V_M
+3.3V_M
+PWR_SRC_S
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+1.05V_M
+5V_ALW
+1.5V_RUN
+3.3V_ALW
+0.675V_DDR_VTT
+3.3V_ALW_PCH
+VCC_CORE
+3.3V_RTC_LDO
(M-OFF)
SATA
+1.05V_RUN
+3.3V_MXM
+5V_MXM
State
+MXM_PWR_SRC
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
B
DESTINATION
SATA 0
HDD 1
SATA 1
ODD
SATA 2
Dock
SATA 3
HDD 2
SATA 4
M.2 Slot-2
SATA 5
M.2 Slot-3
USH
DESTINATION
0
IO Board- JUSB3 (Ext Left Side)
1
JUSB1 (Ext Right Side)
2
IO Board- JUSB1 (Ext Left Side)
3
Docking USB3.0
4
M.2 Slot-1 (WLAN/BT/WiGig)
5
M.2 Slot-2 (WWAN/LTE/HCA)
6
Docking USB 2.0
7
USH
8
Camera
9
IO Board- JUSB2 (Ext Left Side)
10
M.2 Slot-3 (SSD/HCA/Cache)
11
Touch Screen
12
NA
13
NA
0
BIO
1
NA
PCI EXPRESS
D
C
DESTINATION
B
Stack up
Lane 1
M.2 Slot-2 (WWAN/LTE/HCA)
Lane 2
M.2 Slot-3 (SSD/HCA/Cache)
DESTINATION
Lane 3
10/100/1G LOM
Port 1
IO Board- JUSB3
Lane 4
MMI(Card reader)
Port 2
JUSB1 (Ext Right Side)
Lane 5
TBT-1
Port 3
Docking
Lane 6
TBT-2
Port 4
NA
Lane 7
M.2 Slot-1 (WLAN/BT/WiGig)
Port 5
IO Board- JUSB1
Lane 8
M.2 Slot-1 (WLAN/BT/WiGig)
Port 6
IO Board- JUSB2
USB3.0
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Index and Config.
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
3
Rev
0.1
of
67
5
4
3
Docking
2
FDC654P
EN_INVPWR
1
+BL_PWR_SRC
(Q21)
D
D
3.3V_RUN_GFX_ON
SI4835DDY
(Q186)
ADAPTER
+PWR_SRC
+MXM_PWR_SRC
ISL95812
(PU500)
IMVP_VR_ON
BATTERY
TPS2544
(UI1)
+5V_USB_PWR1
TPS2560
(U6)
+5V_USB1
+5V_USB2
+VCC_CORE
USB_PWR_EN2#
TPS2560
(U9)
1.05V_0.8V_PWROK
+5V_USB3
IO Board
ALWON
CHARGER
+5V_ALW
TPS51225
(PU101)
RUN_ON
MODC_EN
+5V_HDD
+5V_RUN
TPS22966
(U37)
+5V_MOD
C
C
TPS22966
(U63)
TPS22966
(U42)
TPS22965
(U34)
+3.3V_MXM
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_RUN
TPS22966
(U40)
+3.3V_WLAN
+3.3V_SUS
MXM_ENVDD
LCD_VCC_TEST_EN
ENVDD_PCH
A_ON
SIO_SLP_S4#
SIO_SLP_WLAN#
AUX_EN_WOWL
RUN_ON
3.3V_RUN_GFX_ON
PCH_ALW_ON
SIO_SLP_LAN#
3.3V_WWAN_EN
TPS22965
(U43)
+3.3V_WWAN
+1.05V_RUN
+5V_MXM
+3.3V_SSD
SI4164DY
(Q63)
+5V_ALW
NVRAM_PWR_EN
TPS22966
(U49)
+12VS_TB
APL3512ABI
(U33)
B
+3.3V_M
+LCDVDD
CCD_OFF
B
+1.35V_MEM
SIO_SLP_S3#
+0.675V_DDR_VTT
RUN_ON
+1.05V_M
+V_DDR_REF
3.3V_RUN_GFX_ON
SIO_SLP_A#
A_ON
SIO_SLP_S4#
TPS51212
(PU300)
RT8207
(PU200)
SIO_SLP_A#
RT9297
(PU600)
TBT_HV_EN
+3.3V_ALW
DMG2301U
(Q24)
+CAMERA_VDD
APL5930
(PU400)
+1.5V_RUN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power Rail
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
4
of
67
5
4
3
2
+3.3V_ALW_PCH
2.2K
R10
MEM_SMBCLK
U11
MEM_SMBDATA
202
DMN66D0LDW
200
DMN66D0LDW
2.2K
2.2K
N11
200
+3.3V_LAN
U8
LAN_SMBCLK
28
R7
LAN_SMBDATA
31
SMBUS Address [A0h]
A0h --> 1010 0000
DIMM2
SMBUS Address [A0h]
A0h --> 1010 0000
DIMM3
SMBUS Address [A4h]
A4h --> 1010 0100
DIMM4
SMBUS Address [A4h]
A4h --> 1010 0100
XDP1
SMBUS Address [TBD]
202
200
SMBUS Address [0xC8]
LOM
202
K6
2.2K
SML1_SMBDATA
SML1_SMBCLK
A5
DIMM1
202
PCH
D
1
2.2K
SMBUS Address [0x9a]
2.2K
200
+3.3V_ALW_PCH
D
53
2.2K
51
B6
1D
+3.3V_ALW
2.2K
1D
53
SMBUS Address
1A
1A
B4
A3
DOCK_LCD_SMBCLK
127
DOCK_LCD_SMBDAT
129
DOCKING
Difference with Diesel
20
21
C
XDP2
51
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
Difference with Diesel
DMN66D0LDW
eDP Panel
DMN66D0LDW
2.2K
A56
PBAT_SMBCLK
B59
PBAT_SMBDAT
+3.3V_RUN
4
LNG3DMTR
6
1C
C
2.2K
2.2K
1C
SMBUS Address
SMB_ADM1032: 0x98
SMB_DIAG_DUMP: 0x04
SMB_DIAG_DUMP2: 0x05
SMB_BLACKTOP: 0x60
remove WWAN
SMBUS Address [TBD]
2.2K
SMBUS Address [TBD]
+3.3V_ALW
100 ohm
7
100 ohm
6
BATTERY
CONN
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
SMBUS Address [TBD]
2.2K
2.2K
KBC
+3.3V_SUS
A50
USH_SMBCLK
5
B53
USH_SMBDAT
6
1E
1E
MEC 5085
Difference with Diesel
B
B
remove EXP card
2.2K
2.2K
+3.3V_ALW
B50
CHARGER_SMBCLK
9
A47
CHARGER_SMBDAT
8
1G
1G
Charger
SMBUS Address [0xFF]
@2.2K
@2.2K
1H
B49
GPU_SMBCLK
1H
B48
GPU_SMBDAT
+3.3V_RUN
DMN66D0LDW
DMN66D0LDW
70
68
SMBUS Address [TBD]
MXM
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
SMBUS Bolck Diagram
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
5
of
Rev
0.1
67
5
4
3
2
1
+VCOMP_OUT
PEG_COMP
24.9_0402_1%
1
PEG_CRX_GTX_C_P[0..15]
RC2
PEG_CRX_GTX_C_N[0..15]
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
D
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
CPU1A
AB2
AB3
AC3
AC1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AB1
AB4
AC4
AC2
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
AF2
AF4
AG4
AG2
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AF1
AF3
AG3
AG1
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<19>
<19>
<19>
<19>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
FDI_CSYNC
FDI_INT
F11
F12
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
PEG
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<19>
<19>
<19>
<19>
PEG_CRX_GTX_C_P[0..15]
<17>
PEG_CRX_GTX_C_N[0..15]
<17>
PEG_CTX_GRX_P[0..15]
<17>
PEG_CTX_GRX_N[0..15]
<17>
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
FDI_CSYNC
DISP_INT
FDI
B
PEG_RCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
AH6
E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1
C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2
PEG_COMP
PEG_CRX_GTX_N0
PEG_CRX_GTX_N1
PEG_CRX_GTX_N2
PEG_CRX_GTX_N3
PEG_CRX_GTX_N4
PEG_CRX_GTX_N5
PEG_CRX_GTX_N6
PEG_CRX_GTX_N7
PEG_CRX_GTX_N8
PEG_CRX_GTX_N9
PEG_CRX_GTX_N10
PEG_CRX_GTX_N11
PEG_CRX_GTX_N12
PEG_CRX_GTX_N13
PEG_CRX_GTX_N14
PEG_CRX_GTX_N15
PEG_CRX_GTX_P0
PEG_CRX_GTX_P1
PEG_CRX_GTX_P2
PEG_CRX_GTX_P3
PEG_CRX_GTX_P4
PEG_CRX_GTX_P5
PEG_CRX_GTX_P6
PEG_CRX_GTX_P7
PEG_CRX_GTX_P8
PEG_CRX_GTX_P9
PEG_CRX_GTX_P10
PEG_CRX_GTX_P11
PEG_CRX_GTX_P12
PEG_CRX_GTX_P13
PEG_CRX_GTX_P14
PEG_CRX_GTX_P15
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N15
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P15
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
CC9
CC10
CC11
CC12
CC13
CC14
CC15
CC16
CC17
CC18
CC19
CC20
CC21
CC22
CC23
CC24
CC25
CC26
CC27
CC28
CC29
CC30
CC31
CC32
CC44
CC45
CC53
CC73
CC46
CC74
CC47
CC56
CC75
CC48
CC59
CC76
CC49
CC62
CC77
CC50
CC67
CC68
CC51
CC52
CC69
CC54
CC55
CC70
CC57
CC58
CC71
CC60
CC61
CC72
CC63
CC64
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_P15
PEG_CTX_GRX_N0
PEG_CTX_GRX_N1
PEG_CTX_GRX_N2
PEG_CTX_GRX_N3
PEG_CTX_GRX_N4
PEG_CTX_GRX_N5
PEG_CTX_GRX_N6
PEG_CTX_GRX_N7
PEG_CTX_GRX_N8
PEG_CTX_GRX_N9
PEG_CTX_GRX_N10
PEG_CTX_GRX_N11
PEG_CTX_GRX_N12
PEG_CTX_GRX_N13
PEG_CTX_GRX_N14
PEG_CTX_GRX_N15
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_P2
PEG_CTX_GRX_P3
PEG_CTX_GRX_P4
PEG_CTX_GRX_P5
PEG_CTX_GRX_P6
PEG_CTX_GRX_P7
PEG_CTX_GRX_P8
PEG_CTX_GRX_P9
PEG_CTX_GRX_P10
PEG_CTX_GRX_P11
PEG_CTX_GRX_P12
PEG_CTX_GRX_P13
PEG_CTX_GRX_P14
PEG_CTX_GRX_P15
C
B
1 OF 12
A
DELL CONFIDENTIAL/PROPRIETARY
HASWELL_BGA1364
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
D
HASWELL_BGA
DMI
C
2
3
2
Broadwell (1/7)
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
Rev
0.1
6
of
67
A
5
4
3
2
1
+VCCIO_OUT
SM_DRAMPWROK with DDR Power Gating Topology
1
2
CC66
1U_0402_6.3V6K
2
CXDP@ CC65
0.1U_0402_25V6K
1
Difference with Diesel
+PCH_VCCDSW3_3
+VCCIO_OUT
JXDP1
D
2 RUNPWROK_R
100K_0402_5%
1
RC18
1
+PCH_VCCDSW3_3
@ CC156
1
2
2 PM_DRAM_PWRGD_A
100K_0402_5%
P
B
4
O
A
1
2
@ RC46
2
@ RC28
2
1 1
3
S
@ QC1
L2N7002WT1G_SC-70-3
<51,54>
D
2
G
RUN_ON_ENABLE#
@ RC20
39_0402_5%
CIS LINK OK
2
@ RC124
RUNPWROK_AND
74AHC1G09GW_TSSOP5~D
XDP_PREQ#
follow E6 common boot code.
1 1.35V_SUS_PWRGD
6.8K_0402_5%
<18,19> SIO_PWRBTN#_R
<11,18,19,51> RESET_OUT#
1PM_DRAM_PWRGD_CPU
0_0402_5%
CPU_PLTRST#_R
RESET_OUT#_XDP
1K_0402_1%
CXDP@ RC6
@ RC9
1
1
2 0_0402_5%
2 0_0402_5%
CFD_PWRBTN#_XDP
RESET_OUT#_XDP
CXDP@ RC8
1
2 1K_0402_1%
XDP_RST#_R
XDP_TRST#
XDP_TMS
RC14
3.3K_0402_1%
@ RC89
2
1
2
1
RUNPWROK_R
0_0402_5%
1
PM_DRAM_PWRGD_A
0_0402_5%
2
@ RC88
PM_DRAM_PWRGD
1
3
<19>
2
RUNPWROK
UC2
G
<50,51>
2
5
0.1U_0402_25V6K
+3.3V_ALW_PCH
RC16
1.8K_0402_1%
1
@ RC47
30
28
Place near JXDP1
+1.35V_MEM
26
24
22
20
18
16
14
12
10
8
6
4
2
GND GND
GND GND
26
24
22
20
18
16
14
12
10
8
6
4
2
25
23
21
19
17
15
13
11
9
7
5
3
1
29
27
D
25
23
21
19
17
15
13
11
9
7
5
3
1
XDP_PRDY#
CFG3
CFG3 <10>
2
H_CPUPWRGD_XDP CXDP@ RC5
CPU_PWR_DEBUG_R
CXDP@ RC21 1
RC5 need to close to JCPU1
1 1K_0402_1%
2 0_0402_5%
H_CPUPWRGD
CPU_PWR_DEBUG
<11>
XDP_DBRESET#
XDP_TDO
XDP_TDI
XDP_TCLK
ACES_50559-02601-001
CONN@
Difference with Diesel
CIS link OK
2
CFG3
1 @ RC131
1K_0402_1%
@ QC2
DMN65D8LW-7_SOT323-3
1
3
D
2
1
<13,15,21>
DDR_HVREF_RST_PCH
2
1
2
1
@ RC104
1.35V_SUS_PWRGD
0_0402_5%
@ RC103
0_0402_5%
1
2
+1.05V_RUN
1
2
@ RC126
RUNPWROK_R
CC138
0.01U_0402_16V7K
<57>
C
PM_DRAM_PWRGD_CPU
0_0402_5%
2
G
@ RC101
H_THERMTRIP#
100_0402_1%
CPU1B
<50>
+VCCIO_OUT
CPU_DETECT#
1
RC44
2
H_CATERR#
49.9_0402_1%
2
H_PROCHOT#
62_0402_5%
RC57 1
@ RC129 1
<51,61,62> H_PROCHOT#
<23,51> H_THERMTRIP#
G50
G51
H_PROCHOT#_R
H_THERMTRIP#_R
E50
D53
place RC129 near CPU
H_PM_SYNC
2 0_0402_5% VCCPWRGOOD_0_R
PM_DRAM_PWRGD_CPU
CPU_PLTRST#_R
@ RC25 1
MISC
CATERR
PECI
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
PROCHOT
THERMTRIP
PRDY
PREQ
TCK
TMS
TRST
TDI
TDO
DBR
D52
F50
AP48
L54
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN
PWR
<19> H_PM_SYNC
<23> H_CPUPWRGD
Difference with Diesel
2 56_0402_5%
2 0_0402_5%
H_CATERR#
PECI_EC
HASWELL_BGA
PROC_DETECT
JTAG
1
@ RC128
PECI_EC
C51
THERMAL
<51>
CPU_DETECT#
DDR3L
RUNPWROK_AND
S
C
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
B
<20> CLK_CPU_DPLL#
<20> CLK_CPU_DPLL
<20> CLK_CPU_SSC_DPLL#
<20> CLK_CPU_SSC_DPLL
<20> CLK_CPU_DMI#
<20> CLK_CPU_DMI
Remove +1.05V_RUN to +VCCST circuit
for rPGA usage.
2
2
2
2
2
2
1
1
1
1
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CPU_DMI#
CPU_DMI
AC6
AE6
V6
Y6
AB6
AA6
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP
CLOCK
@ RC51
@ RC52
@ RC43
@ RC22
@ RC15
@ RC13
BB51
BB53
BB52
BE51
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3_DRAMRST#_CPU
N53
N52
N54
M51
M53
N49
M49
F53
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCLK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R
XDP_DBRESET#_R
R51
R50
P49
N50
R49
P53
U51
P51
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
DDR3_DRAMRST#_CPU
CXDP@ RC48
CXDP@ RC50
CXDP@ RC56
CXDP@ RC62
CXDP@ RC64
CXDP@ RC23
CXDP@ RC24
@ RC26
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
<13>
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_DBRESET#
<18,19>
@ T167
@ T168
@ T169
@ T170
@ T173
@ T174
@ T171
@ T172
B
PU/PD for JTAG signals
+3.3V_RUN
For ESD concern, please put near CPU
2 OF 12
XDP_DBRESET#_R RC19 2
1 1K_0402_1%
XDP_TMS_R
@ RC27 2
1 51_0402_1%
XDP_TDI_R
@ RC29 2
1 51_0402_1%
XDP_PREQ#_R
@ RC32 2
1 51_0402_1%
XDP_TDO_R
RC35 2
1 51_0402_1%
HASWELL_BGA1364
+1.05V_RUN
VCCPWRGOOD_0_R
NC
Y
A
1
4
2
1
2
@ UC1
P
5
2
PCH_PLTRST#
1
PCH_PLTRST#_BUF
@ RC10
2
@ RC54 2
SM_RCOMP0
RC42 1
2 100_0402_1%
XDP_TCLK_R
RC40 2
1 51_0402_1%
SM_RCOMP1
RC55 1
2 75_0402_1%
XDP_TRST#_R
RC41 2
1
<23>
2
CPU_PLTRST#
@ RC53
CPU_PLTRST#_R
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
1 51_0402_1%
SM_RCOMP2
RC49 1
2 100_0402_1%
1
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
A
0_0402_5%
@
2
CIS LINK OK
RC11
20K_0402_5%
SN74LVC1G07DCKR_SC70-5~D
1 0_0402_5%
43_0402_5%
A
3
DDR3L COMPENSATION SIGNALS
@
G
1
<18,19>
@
RC17
1K_0402_1%
2
CC140
0.1U_0402_25V6K
1
Buffered reset to CPU
+1.05V_RUN
RC130
10K_0402_5%
+3.3V_RUN
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Broadwell (2/7)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
7
of
67
5
4
D
CPU1C
<13,14>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
AH54
AH52
AK51
AK54
AH53
AH51
AK52
AK53
AN54
AN52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53
AY52
AY51
AV51
AV54
AY54
AY53
AY47
AY49
BA47
BA45
AY45
AY43
BA49
BA43
BF14
BC14
BC11
BF11
BE14
BD14
BD11
BE11
BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2
AW3
AW2
BB3
BB2
AW4
AW1
AU3
AU1
AR1
AR4
AU2
AU4
AR2
AR3
AM6
AR6
AN6
+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
BC53
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
3
HASWELL_BGA
<15,16>
RSVD
SA_CKN0
SA_CK0
SA_CKE0
SA_CKN1
SA_CK1
SA_CKE1
SA_CKN2
SA_CK2
SA_CKE2
SA_CKN3
SA_CK3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_BS0
SA_BS1
SA_BS2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BD31
BE25 M_CLK_DDR#0
BF25 M_CLK_DDR0
BE34 DDR_CKE0_DIMM2
BD25 M_CLK_DDR#1
BC25 M_CLK_DDR1
BF34 DDR_CKE1_DIMM2
BE23 M_CLK_DDR#4
BF23 M_CLK_DDR4
BC34 DDR_CKE4_DIMM1
BD23 M_CLK_DDR#5
BC23 M_CLK_DDR5
BD34 DDR_CKE5_DIMM1
BE16 DDR_CS0_DIMM2#
BC17 DDR_CS1_DIMM2#
BE17 DDR_CS4_DIMM1#
BD16 DDR_CS5_DIMM1#
BC16 M_ODT0
BF16 M_ODT1
BF17 M_ODT4
BD17 M_ODT5
BC20 DDR_A_BS0
BD21 DDR_A_BS1
BD32 DDR_A_BS2
BC21
BF20 DDR_A_RAS#
BF21 DDR_A_WE#
BE21 DDR_A_CAS#
BD28 DDR_A_MA0
BD27 DDR_A_MA1
BF28 DDR_A_MA2
BE28 DDR_A_MA3
BF32 DDR_A_MA4
BC27 DDR_A_MA5
BF27 DDR_A_MA6
BC28 DDR_A_MA7
BE27 DDR_A_MA8
BC32 DDR_A_MA9
BD20 DDR_A_MA10
BF31 DDR_A_MA11
BC31 DDR_A_MA12
BE20 DDR_A_MA13
BE32 DDR_A_MA14
BE31 DDR_A_MA15
AJ52 DDR_A_DQS#0
AP53 DDR_A_DQS#1
AW52 DDR_A_DQS#2
AY46 DDR_A_DQS#3
BD12 DDR_A_DQS#4
BE7 DDR_A_DQS#5
BA3 DDR_A_DQS#6
AT2 DDR_A_DQS#7
AW39
AJ53 DDR_A_DQS0
AP52 DDR_A_DQS1
AW53 DDR_A_DQS2
BA46 DDR_A_DQS3
BE12 DDR_A_DQS4
BD7 DDR_A_DQS5
BA2 DDR_A_DQS6
AT3 DDR_A_DQS7
AW40
@T60
@
T60
PAD~D
M_CLK_DDR#0 <14>
M_CLK_DDR0 <14>
DDR_CKE0_DIMM2 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR1 <14>
DDR_CKE1_DIMM2 <14>
M_CLK_DDR#4 <13>
M_CLK_DDR4 <13>
DDR_CKE4_DIMM1 <13>
M_CLK_DDR#5 <13>
M_CLK_DDR5 <13>
DDR_CKE5_DIMM1 <13>
DDR_CS0_DIMM2# <14>
DDR_CS1_DIMM2# <14>
DDR_CS4_DIMM1# <13>
DDR_CS5_DIMM1# <13>
M_ODT0 <14>
M_ODT1 <14>
M_ODT4 <13>
M_ODT5 <13>
DDR_A_BS0 <13,14>
DDR_A_BS1 <13,14>
DDR_A_BS2 <13,14>
DDR_A_RAS# <13,14>
DDR_A_WE# <13,14>
DDR_A_CAS# <13,14>
DDR_A_MA[0..15] <13,14>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
<13,14>
<13,14>
2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3
D
HASWELL_BGA
CPU1D
DDR_B_D[0..63]
1
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
RSVD
SB_CKN0
SB_CK0
SB_CKE0
SB_CKN1
SB_CK1
SB_CKE1
SB_CKN2
SB_CK2
SB_CKE2
SB_CKN3
SB_CK3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_BS0
SB_BS1
SB_BS2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD
BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
3 OF 12
AY36
@T64
@
T64
AW27M_CLK_DDR#2
AV27 M_CLK_DDR2
AU36 DDR_CKE2_DIMM4
AW26M_CLK_DDR#3
AV26 M_CLK_DDR3
AU35 DDR_CKE3_DIMM4
BA26 M_CLK_DDR#6
AY26 M_CLK_DDR6
AV35 DDR_CKE6_DIMM3
BA27 M_CLK_DDR#7
AY27 M_CLK_DDR7
AV36 DDR_CKE7_DIMM3
BA20 DDR_CS2_DIMM4#
AY19 DDR_CS3_DIMM4#
AU19 DDR_CS6_DIMM3#
AW20DDR_CS7_DIMM3#
AY20 M_ODT2
BA19 M_ODT3
AV19 M_ODT6
AW19M_ODT7
AY23 DDR_B_BS0
BA23 DDR_B_BS1
BA36 DDR_B_BS2
AU30
AV23 DDR_B_RAS#
AW23DDR_B_WE#
AV20 DDR_B_CAS#
PAD~D
M_CLK_DDR#2 <16>
M_CLK_DDR2 <16>
DDR_CKE2_DIMM4 <16>
M_CLK_DDR#3 <16>
M_CLK_DDR3 <16>
DDR_CKE3_DIMM4 <16>
M_CLK_DDR#6 <15>
M_CLK_DDR6 <15>
DDR_CKE6_DIMM3 <15>
M_CLK_DDR#7 <15>
M_CLK_DDR7 <15>
DDR_CKE7_DIMM3 <15>
DDR_CS2_DIMM4#
DDR_CS3_DIMM4#
DDR_CS6_DIMM3#
DDR_CS7_DIMM3#
<16>
<16>
<15>
<15>
M_ODT2 <16>
M_ODT3 <16>
M_ODT6 <15>
M_ODT7 <15>
DDR_B_BS0 <15,16>
DDR_B_BS1 <15,16>
DDR_B_BS2 <15,16>
DDR_B_RAS# <15,16>
DDR_B_WE# <15,16>
DDR_B_CAS# <15,16>
DDR_B_MA[0..15]
BA30 DDR_B_MA0
AW30DDR_B_MA1
AY30 DDR_B_MA2
AV30 DDR_B_MA3
AW32DDR_B_MA4
AY32 DDR_B_MA5
AT30 DDR_B_MA6
AV32 DDR_B_MA7
BA32 DDR_B_MA8
AU32 DDR_B_MA9
AU23 DDR_B_MA10
AY35 DDR_B_MA11
AW35DDR_B_MA12
AU20 DDR_B_MA13
AW36DDR_B_MA14
BA35 DDR_B_MA15
AD52 DDR_B_DQS#0
AU46 DDR_B_DQS#1
BD48 DDR_B_DQS#2
BD43 DDR_B_DQS#3
AW16DDR_B_DQS#4
AW10DDR_B_DQS#5
AW8 DDR_B_DQS#6
AL2 DDR_B_DQS#7
BE38
AD53 DDR_B_DQS0
AV46 DDR_B_DQS1
BE48 DDR_B_DQS2
BE43 DDR_B_DQS3
AW15DDR_B_DQS4
AW12DDR_B_DQS5
AW6 DDR_B_DQS6
AL3 DDR_B_DQS7
BD38
C
<15,16>
DDR_B_DQS#[0..7]
<15,16>
DDR_B_DQS[0..7]
<15,16>
B
BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37
4 OF 12
HASWELL_BGA1364
HASWELL_BGA1364
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Broadwell (3/7)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
8
of
67
5
4
D
C21
D21
A21
B21
C20
D20
A20
B20
C
<36>
<36>
<36>
<36>
DPD_CPU_LANE_N2
DPD_CPU_LANE_P2
DPD_CPU_LANE_N3
DPD_CPU_LANE_P3
<36>
<36>
<36>
<36>
DPD_CPU_LANE_N0
DPD_CPU_LANE_P0
DPD_CPU_LANE_N1
DPD_CPU_LANE_P1
DPD_CPU_LANE_N2
DPD_CPU_LANE_P2
DPD_CPU_LANE_N3
DPD_CPU_LANE_P3
C16
D16
A16
B16
DPD_CPU_LANE_N0
DPD_CPU_LANE_P0
DPD_CPU_LANE_N1
DPD_CPU_LANE_P1
C17
D17
A17
B17
2
1
HASWELL_BGA
CPU1J
C25
D25
A25
B25
C24
D24
A24
B24
3
DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3
EDP_AUXN
EDP_AUXP
EDP_HPD
DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1
FDI_TXN0
FDI_TXP0
FDI_TXN1
FDI_TXP1
F15
F14
E14
CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD#
C14
A12
D14
B12
CPU_EDP_LANE_N0
CPU_EDP_LANE_N1
CPU_EDP_LANE_P0
CPU_EDP_LANE_P1
AG6
E12
EDP_COMP
CPU_EDP_AUX#
<29>
CPU_EDP_AUX <29>
CPU_EDP_LANE_N0
CPU_EDP_LANE_N1
CPU_EDP_LANE_P0
CPU_EDP_LANE_P1
PAD~D T69 @
FDI_CTX_PRX_N0
FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1
FDI_CTX_PRX_P1
C12
D12
A14
B14
<29>
<29>
<29>
<29>
D
<19>
<19>
<19>
<19>
DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3
DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1
C
10 OF 12
HASWELL_BGA1364
HPD INVERSION FOR EDP
COMPENSATION PU FOR eDP
B
1
B
RC65
10K_0402_5%
2
+VCCIO_OUT
+VCOMP_OUT
1
QC6
RC1
<29>
D
S
2
G
2
1
CPU_EDP_HPD
RC75
100K_0402_5%
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
1
2
3
EDP_HPD#
EDP_COMP
24.9_0402_1%
LBSS138LT1G_SOT-23-3
DELL CONFIDENTIAL/PROPRIETARY
A
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Broadwell (4/7)
Size
4
3
Rev
0.1
LA-B541P
Date:
5
Document Number
2
Monday, January 13, 2014
Sheet
9
1
of
67
A
5
4
@ T75 PAD~D
@ T76 PAD~D
D
H_CPU_RSVD
+VCC_CORE
@ T92 PAD~D
@ T72 PAD~D
L52
L53
@ T85 PAD~D
L51
@ T84 PAD~D
@ T83 PAD~D
H_CPU_TESTLO
@ T104PAD~D
@ T90 PAD~D
@ T103PAD~D
<7>
CFG3
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
F24
F25
F20
AG49
AD49
AC49
AE49
Y50
AB49
V51
W51
Y49
Y54
Y53
W53
U53
V54
R53
R52
L50
L49
E5
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD_TP
RSVD_TP
TESTLOW_F21
VSS
VSS
VSS
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
PAD~D
PAD~D
PAD~D
PAD~D
R54
Y52
V53
Y51
V52
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
T86 @
T78 @
T87 @
T88 @
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T136
T137
T139
T138
T140
B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
F16
PAD~D T91 @
G12
G10
PAD~D T89 @
PAD~D T93 @
CFG2
@
@
@
@
@
@
T95 @
T94 @
T96 @
T98 @
T97 @
T100 @
T99 @
T102 @
T101 @
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
CFG2
0:Lane Reversed
RSVD_TP
RSVD_TP
TESTLOW_F20
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD
D
CFG4
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
H54
H53
RC77
1K_0402_1%
@ T105PAD~D
@ T107PAD~D
@ T106PAD~D
@ T108PAD~D
@ T109PAD~D
@ T117PAD~D
@ T111PAD~D
@ T116PAD~D
@ T119PAD~D
@ T128PAD~D
@ T127PAD~D
@ T135PAD~D
@ T82 PAD~D
@ T81 PAD~D
@ T80 PAD~D
C
G21
G24
F21
G19
F51
F52
F22
RSVD_TP
RSVD_TP
F1
E1
A5
A6
1
F6
G6
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
1
@ T73 PAD~D
@ T74 PAD~D
CFG STRAPS for CPU
HASWELL_BGA
2
BE4
BD3
1
RC76
1K_0402_1%
@ T70 PAD~D
@ T71 PAD~D
2
2
CPU1K
3
H51
H52
N51
G53
H50
C
Display Port Presence Strap
PAD~D T79 @
11 OF 12
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
HASWELL_BGA1364
CFG6
1
H_CPU_TESTLO
49.9_0402_1%
1 CFG_RCOMP
49.9_0402_1%
1 H_CPU_RSVD
49.9_0402_1%
B3_A3
@ T180PAD~D
B
@ T166PAD~D
A52_B52
A53_B53
C3_B2
B3_A3
A51
A52
A53
B2
B3
B52
B53
B54
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BF51
BF52
BF53
C1
C2
C3
C1_C2
C1_C2
C3_B2
C54
D1
B54_C54
D54
1
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PAD~D T114@
BE52_BF52
BE53_BF53
CFG[6:5]
PAD~D T164@
CFG7
BC1
BC54
BD1
RSVD
RSVD
RSVD
2
BE1_BD1
BE54_BD54
BE1_BD1
BE2_BF2
BE3_BF3
BE52_BF52
BE53_BF53
BE54_BD54
BE2_BF2
BE3_BF3
@ T178PAD~D
BD54
BE1
BE2
BE3
BE52
BE53
BE54
BF2
BF3
BF4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AN35
AN37
AF9
AE9
G14
G17
AD45
AG45
CFG7
@ RC86
1K_0402_1%
@ T179PAD~D
@ T177PAD~D
B
PAD~D T161@
1
A52_B52
A53_B53
B54_C54
A3
A4
HASWELL_BGA
2
CPU1L
1
RC59
CFG5
@ RC85
1K_0402_1%
2
@ RC83
1K_0402_1%
2
RC58
2
2
RC45
PEG DEFER TRAINING
1: (Default) PEG Train immediately
following xxRESETB de assertion
0: PEG Wait for BIOS for training
A
A
12 OF 12
DELL CONFIDENTIAL/PROPRIETARY
HASWELL_BGA1364
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Broadwell (5/7)
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
10
Rev
0.1
of
67
5
4
3
2
1
55A
+VCCIO_OUT
SVID ALERT
+VCC_CORE
2
2
VIDALERT_N
H_CPU_SVIDALRT#
RC61
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
+1.35V_MEM
+VCCIO_OUT
2
1
RC63
130_0402_1%
SVID DATA
<61>
1
43_0402_5%
CAD Note: Place the PU resistors close to CPU
RC63 close to CPU 300 - 1500mils
VIDSOUT
VIDSOUT
+VCC_CORE
1
2
<61>
RC66
100_0402_1%
VCC_SENSE
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
2
VCCSENSE
VCCSENSE
1
VCCSENSE_R
0_0402_5%
@RC67
@
RC67
C
@T115
@
T115
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
2
VSSSENSE
VSSSENSE
1
VSSSENSE_R
0_0402_5%
@RC68
@
RC68
2
VSSSENSE_R
@ T151
@T151
@T152
@
T152
PAD~D
PAD~D
@T153
@
T153
PAD~D
VCCSENSE_R
<12>
RC70
100_0402_1%
1
<61>
AN31
L6
M6
AN22
AN18
PAD~D
+VCC_CORE
HSW_BDW
compatibility CKT
+VCCIO_OUT
+VCCIO2PCH
+VCOMP_OUT
@ T160
@T160
@T159
@
T159
@T154
@
T154
PAD~D
PAD~D
PAD~D
H_CPU_SVIDALRT#
<61>
<7>
VIDSOUT
Difference with Diesel
@ T157
@T157
@T158
@
T158
@T162
@
T162
@T163
@
T163
PAD~D
PAD~D
PAD~D
PAD~D
VDDQ DECOUPLING
+1.35V_MEM
1
2
1
2
1
2
1
+
2
+1.05V_RUN
+1.05V_RUN
+VCCIO_OUT
2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
VCC
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
RSVD
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC_D5
FC_D3
D5
D3
HSW_BDW
compatibility CKT
+VCCIO2PCH
FC_D3
1
@
HSW
BDW
RC105
X
V
CC137
X
V
CC173
X
V
RC72
X
V
RC73
X
V
HSW_BDW compatibility CKT
RESET_OUT#
2
1
2
BDW@CC137
BDW@CC137
22U_0805_6.3V6M
place CC173 close to CPU
BDW@CC173
BDW@
CC173
0.1U_0402_10V7K
1
4
6 OF 12
D
C
B
A
BDW@
RC72
2.67K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H33
H34
H36
H37
H38
H39
H40
H42
H43
H45
H46
H48
H8
H9
J10
J14
J19
J24
J29
J33
J36
J37
J38
J39
J40
J42
J43
J45
J46
J48
J8
J9
K38
K40
K43
K44
K45
K46
K48
K8
K9
L37
L38
L39
L40
L42
L43
L44
L46
L47
L8
M37
M38
M39
M40
M42
M43
M44
M45
M46
M8
M9
N37
N38
N39
N40
N42
N43
N44
N46
N47
N8
N9
P45
P46
P8
R46
R47
R8
R9
T45
T46
U46
U47
U8
U9
V45
V46
V8
W46
W47
W8
Y45
Y46
Y8
A27
A28
A31
A32
A34
B27
B28
B31
B32
B34
B36
B38
B39
B42
2
1 0_0603_5%
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
<18,19,51,7>
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
+VCC_CORE
HASWELL_BGA
HASWELL_BGA1364
0_0603_5%
2
RESET_OUT#
BDW@
RC73
6.04K_0402_1%
FC_D3
+VCCIO2PCH
BDW@RC105
BDW@
RC105
B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
HASWELL_BGA1364
HSW_BDW compatibility CKT
1
@RC4
@
RC4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
5 OF 12
+1.05V_RUN
2
A36
A38
A39
A42
A43
A45
A46
A48
AA46
AA47
AA8
AA9
CPU_PWR_DEBUG
2
2
+VCC_CORE
RC71
10K_0402_5%
2
1
@ CC86
1U_0402_6.3V6K~D
2
1
@ CC83
1U_0402_6.3V6K~D
2
1
@ CC82
1U_0402_6.3V6K~D
2
1
@ CC81
1U_0402_6.3V6K~D
2
1
@ CC80
1U_0402_6.3V6K~D
2
1
@ CC43
1U_0402_6.3V6K~D
2
1
CC87
1U_0402_6.3V6K~D
2
1
@ CC88
1U_0402_6.3V6K~D
1
CC84
1U_0402_6.3V6K~D
2
CC85
1U_0402_6.3V6K~D
1
B51
F19
E52
V49
U49
AM49
IVR_ERROR
IST_TRIGGER W49
V50
AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50
RC69
150_0402_1%
1
2
CC172
330U_D2_2VM_R6M
1
CC165
10U_0603_6.3V6M~D
2
CC171
10U_0603_6.3V6M~D
1
@CC166
@
CC166
10U_0603_6.3V6M~D
2
CC163
10U_0603_6.3V6M~D
1
@CC168
@
CC168
10U_0603_6.3V6M~D
2
@CC164
@
CC164
10U_0603_6.3V6M~D
1
@CC170
@
CC170
10U_0603_6.3V6M~D
2
@CC161
@
CC161
10U_0603_6.3V6M~D
1
B
J53
J52
J50
CPU_PWR_DEBUG
CPU_PWR_DEBUG
Difference with Diesel (follow HSW-BGA CRB Rev 0.7)
A
VIDSCLK
VIDSCLK
C50
AH9
D51
F17
AK6
AN33
W9
J12
AR49
RSVD
RSVD
RSVD
RSVD
1
<61>
J17
J21
J26
J31
PAD~D
PAD~D
PAD~D
PAD~D
2
D
HASWELL_BGA
CPU1E
@ T110
@T110
@T77
@
T77
@T112
@
T112
@T113
@
T113
CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils
CPU1F
AB45
AB46
AB8
AC46
AC47
AC8
AC9
AD46
AD8
AE46
AE47
AE8
AF8
AG46
AG8
AH46
AH47
AH8
AJ45
AJ46
AK46
AK47
AK8
AL45
AL46
AL8
AL9
AM46
AM47
AM8
AM9
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN8
AN9
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AP8
AP9
AR35
AR37
AR39
AR41
AR43
AR45
AR46
H30
H31
H32
1
RC60
75_0402_1%
1
+VCC_CORE
3
2
Broadwell (6/7)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
11
of
67
5
4
3
2
CPU1I
D
HASWELL_BGA
CPU1G
C
B
A11
A15
A19
A22
A26
A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4
AA48
AA5
AA7
AB5
AB51
AB52
AB53
AB54
AB7
AB9
AC48
AC5
AC50
AC7
AD48
AD51
AD54
AD7
AD9
AE1
AE2
AE3
AE4
AE48
AE5
AE50
AE7
AF5
AF6
AF7
AG48
AG5
AG51
AG52
AG53
AG54
AG7
AG9
AH1
AH2
AH3
AH4
AH48
AH5
AH50
AH7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CPU1H
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7
AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4
AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT5
AT50
AT51
AT52
AT53
AT54
AT6
AT8
AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AU5
AU9
AV1
AV13
AV18
AV2
AV22
AV25
AV29
AV3
AV33
AV4
AV42
AV5
AV50
AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
7 OF 12
HASWELL_BGA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_BGA1364
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
8 OF 12
HASWELL_BGA1364
A
BC10
BC12
BC15
BC18
BC22
BC26
BC3
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC5
BC50
BC52
BC7
BD10
BD15
BD18
BD36
BD41
BD46
BD5
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
BF7
C11
C15
C19
C22
C26
C30
C33
C37
C4
C40
C44
C49
C52
C8
D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49
D8
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53
E8
F2
F26
F3
F30
F33
F37
F4
F40
F44
F49
F5
G11
G13
G16
1
HASWELL_BGA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SENSE
G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
R48
R7
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9
D
C
B
AR22
AB48
P9
G18
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
D50
VSSSENSE_R
<11>
A
9 OF 12
HASWELL_BGA1364
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
Title
Broadwell (7/7)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
2
12
Sheet
1
of
67
5
4
3
2
1
All VREF traces should
have 10 mil trace width
Top Side
JDIMM1 STD Type H=9.2
+1.35V_MEM
DDR_A_D21
DDR_A_D20
DDR_A_D23
DDR_A_D22
DDR_A_D30
DDR_A_D25
DDR_A_D28
DDR_A_D27
CD14 change to SGA20331E10
2
1
+
2
DDR_CKE4_DIMM1
<14,8>
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
<8>
DDR_CS5_DIMM1#
DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D44
DDR_A_D47
DDR_A_D46
DDR_A_D53
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
+3.3V_RUN
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
1
@ RD8
0_0402_5%
2
DIMM Select
DDR_A_D58
DDR_A_D62
+3.3V_RUN
1
DIMM1
1
0
DIMM3
1
1
DIMM1_SA1
1
2
1
0
A
1
2
@ CD22
2.2U_0402_6.3V6M
0
DIMM4
CD21
0.1U_0402_16V4Z
SA1
0
DIMM1_SA0
@ RD13
0_0402_5%
*
SA0
DIMM2
2
DIMM1_SA0
DIMM1_SA1
+0.675V_DDR_VTT
205
G1
1
DDR_CKE5_DIMM1
<8>
C
DDR_A_MA15
DDR_A_MA14
+1.35V_MEM
+SM_VREF
DDR_A_MA11
DDR_A_MA7
+SM_VREF_Q
1
@ RD10
DDR_A_MA6
DDR_A_MA4
2
0_0402_5%
@ QD7
L2N7002WT1G_SC-70-3
DDR_A_MA2
DDR_A_MA0
3
M_CLK_DDR5
M_CLK_DDR#5
DDR_A_BS1
DDR_A_RAS#
M_ODT4
M_ODT5
M_CLK_DDR5
<8>
M_CLK_DDR#5
<8>
1
RD45 1
DDR_A_BS1 <14,8>
DDR_A_RAS#
<14,8>
DDR_CS4_DIMM1#
M_ODT4 <8>
M_ODT5
2
+DIMM1_VREF_CA
<8>
1
DDR_A_D33
DDR_A_D32
1
DDR_A_D34
DDR_A_D38
1
DDR_HVREF_RST_PCH
<8>
2
2
+SM_VREF_DIMM
0_0402_5%
@ RD7
1
2
+SM_VREF_DIMM
2 2_0402_1%
RC110
24.9_0402_1%
2
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D31
DDR_A_D29
CD16
0.1U_0402_16V4Z
2
1
CD20
1U_0402_6.3V6K
2
1
CD19
1U_0402_6.3V6K
2
1
CD18
1U_0402_6.3V6K
B
CD17
1U_0402_6.3V6K
1
2
DDR_A_DQS#3
DDR_A_DQS3
@ CD15
2.2U_0402_6.3V6M
DDR_A_D37
DDR_A_D36
+0.675V_DDR_VTT
1
DDR_HVREF_RST_PCH
DDR_HVREF_RST_PCH
RD46
1K_0402_1%
DDR_A_MA10
DDR_A_BS0
<15,21,7>
+SA_DIMM1_VREFDQ
2 2_0402_1%
CD90
0.022U_0402_16V7K
DDR_A_BS0
<14,8> DDR_A_WE#
<14,8> DDR_A_CAS#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D24
DDR_A_D26
G
<14,8>
M_CLK_DDR4
M_CLK_DDR#4
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_A_D19
DDR_A_D18
RD41 1
D
Layout Note:
Place near JDIMM1.203,204
M_CLK_DDR4
M_CLK_DDR#4
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
2
0_0402_5%
@ QD6A
DMN66D0LDW-7_SOT363-6
1
6
S
<8>
<8>
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
1
@ RD9
DDR_A_D17
DDR_A_D16
RD47
1K_0402_1%
2
1
CD14
330U_SX_2VY
2
1
@ CD13
10U_0603_6.3V6M
2
1
CD12
10U_0603_6.3V6M
1
CD11
10U_0603_6.3V6M
2
CD10
10U_0603_6.3V6M
2
1
CD9
10U_0603_6.3V6M
1
CD8
10U_0603_6.3V6M
2
CD7
10U_0603_6.3V6M
1
<8>
+SA_DIMM_VREFDQ_Q
DDR_A_D14
DDR_A_D10
RC109
24.9_0402_1%
+1.35V_MEM
C
+1.35V_MEM
+SA_DIMM_VREFDQ
DDR3_DRAMRST#_R
RD43
1K_0402_1%
2
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D13
DDR_A_D12
CD89
0.022U_0402_16V7K
2
1
CD5
1U_0402_6.3V6K
2
1
CD4
1U_0402_6.3V6K
1
CD3
1U_0402_6.3V6K
2
CD2
1U_0402_6.3V6K
1
DDR_A_D2
DDR_A_D3
RD44
1K_0402_1%
DDR_A_D15
DDR_A_D11
DDR_A_DQS#0
DDR_A_DQS0
2
DDR_A_DQS#1
DDR_A_DQS1
Bottom Side
1
DDR_A_D8
DDR_A_D9
D
DDR_A_D1
DDR_A_D5
2
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
2
DDR_A_MA[0..15]
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
JDIMM4
JDIMM2
CONN@
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
DDR_A_D[0..63]
DDR_A_D7
DDR_A_D6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
<14,8>
1
DDR_A_D4
DDR_A_D0
1
<14,8>
1
DDR_A_DQS[0..7]
CD6
0.1U_0402_16V4Z
DDR_A_DQS#[0..7]
<14,8>
@ CD1
2.2U_0402_6.3V6M
@ RD2
2
JDIMM1
+V_DDR_REF
1
2
0_0402_5%
+1.35V_MEM
2
1
@ RD1
+1.35V_MEM
2
2
0_0402_5%
2
+SA_DIMM1_VREFDQ
1
JDIMM3
C
B
A
+DIMM1_VREF_DQ
D
<14,8>
D
CPU
2
Populate RD1, De-Populate RD2 for Intel DDR3
VREFDQ multiple methods M1
Populate RD2, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
JDIMM1
B
DDR_A_D41
DDR_A_D40
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D48
DDR_A_D54
DDR_A_D50
<7>
DDR3_DRAMRST#_CPU
1
@ RD6
2
0_0402_5%
DDR3_DRAMRST#_R
<14,15,16>
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D63
DDR_A_D59
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
+0.675V_DDR_VTT
<14,15,16,18,21,45>
<14,15,16,18,21,45>
206
G2
TYCO_2-2013310-1
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DDRIII-SODIMM SLOT1
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
13
of
67
4
3
1
@ RD14
2
0_0402_5%
1
@ RD15
2
0_0402_5%
+1.35V_MEM
<13,8>
DDR_A_D[0..63]
DDR_A_MA[0..15]
2
1
@
1
2
CD24
0.1U_0402_16V4Z
<13,8>
DDR_A_DQS[0..7]
CD23
2.2U_0402_6.3V6M
<13,8>
D
+V_DDR_REF
DDR_A_DQS#[0..7]
+1.35V_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_A_D1
DDR_A_D5
DDR_A_D2
DDR_A_D3
DDR_A_D13
DDR_A_D12
DDR_A_DQS#1
DDR_A_DQS1
+1.35V_MEM
DDR_A_D14
DDR_A_D10
2
1
2
CD28
1U_0402_6.3V6K
2
1
CD27
1U_0402_6.3V6K
1
CD26
1U_0402_6.3V6K
2
CD25
1U_0402_6.3V6K
1
DDR_A_D17
DDR_A_D16
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D19
DDR_A_D18
DDR_A_D24
DDR_A_D26
+1.35V_MEM
DDR_A_D31
DDR_A_D29
CD36 change to SGA20331E10
2
1
+
2
CD36
330U_SX_2VY
2
1
@CD35
@
CD35
10U_0603_6.3V6M
2
1
CD34
10U_0603_6.3V6M
2
1
CD33
10U_0603_6.3V6M
2
1
CD32
10U_0603_6.3V6M
2
1
CD31
10U_0603_6.3V6M
1
CD30
10U_0603_6.3V6M
2
CD29
10U_0603_6.3V6M
1
C
<8>
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
Layout Note:
Place near JDIMM2.Pin 203,204
<8>
<8>
M_CLK_DDR0
M_CLK_DDR#0
<13,8>
DDR_A_BS0
<13,8> DDR_A_WE#
<13,8> DDR_A_CAS#
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
2
1
2
DDR_A_D33
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
B
DDR_A_D41
DDR_A_D40
DDR_A_D43
DDR_A_D42
DIMM Select
DDR_A_D52
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D60
DDR_A_D61
DIMM2_SA0
0
DIMM3
1
1
DIMM2_SA1
1
2
2
A
1
2
@
1
1
1
DIMM2_SA0
CD44
2.2U_0402_6.3V6M
0
DIMM1
DDR_A_D63
DDR_A_D59
+3.3V_RUN
CD43
0.1U_0402_16V4Z
DIMM4
1
0
2
0
DIMM2_SA1
@RD20
@
RD20
0_0402_5%
DIMM2
SA1
@RD19
@
RD19
0_0402_5%
*
SA0
+0.675V_DDR_VTT
205
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
CONN@
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
D
CPU
DDR_A_DQS#0
DDR_A_DQS0
JDIMM3
A
C
B
JDIMM2
JDIMM4
DDR_A_D4
DDR_A_D0
DDR_A_D7
DDR_A_D6
D
Bottom Side
DDR_A_D8
DDR_A_D9
DDR3_DRAMRST#_R
<13,15,16>
DDR_A_D15
DDR_A_D11
DDR_A_D21
DDR_A_D20
DDR_A_D23
DDR_A_D22
DDR_A_D30
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D28
DDR_A_D27
DDR_CKE1_DIMM2
<8>
C
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
M_ODT0
M_ODT1
M_CLK_DDR1
M_CLK_DDR#1
<8>
<8>
DDR_A_BS1 <13,8>
DDR_A_RAS#
<13,8>
DDR_CS0_DIMM2#
M_ODT0 <8>
M_ODT1
<8>
+DIMM2_VREF_CA
<8>
1
@ RD16
DDR_A_D37
DDR_A_D36
1
DDR_A_D39
DDR_A_D35
2
1
2
2
0_0402_5%
+SM_VREF_DIMM
CD42
0.1U_0402_16V4Z
1
DDR_CS1_DIMM2#
CD40
1U_0402_6.3V6K
2
CD39
1U_0402_6.3V6K
1
CD38
1U_0402_6.3V6K
2
CD37
1U_0402_6.3V6K
1
<8>
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CD41
2.2U_0402_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_CKE0_DIMM2
<13,8>
+0.675V_DDR_VTT
Top Side
JDIMM1
+DIMM2_VREF_DQ
JDIMM2
<13,8>
1
JDIMM2 STD Type H=5.2
All VREF traces should
have 10 mil trace width
+SA_DIMM1_VREFDQ
2
@
5
DDR_A_D45
DDR_A_D44
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D53
DDR_A_D49
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D62
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<13,15,16,18,21,45>
<13,15,16,18,21,45>
+0.675V_DDR_VTT
206
TYCO_2-2013289-1~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DDRIII-SODIMM SLOT2
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
14
of
67
5
4
3
2
1
All VREF traces should
have 10 mil trace width
Top Side
JDIMM3 STD Type H=5.2
2
+1.35V_MEM
2
DDR_B_D0
DDR_B_D4
DDR_B_D7
DDR_B_D3
DDR_B_D8
DDR_B_D9
2
1
2
DDR_B_DQS#1
DDR_B_DQS1
CD48
1U_0402_6.3V6K
2
1
CD47
1U_0402_6.3V6K
1
CD46
1U_0402_6.3V6K
2
CD50
1U_0402_6.3V6K
1
1
DDR_B_D11
DDR_B_D13
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D29
DDR_B_D24
+
2
DDR_B_D31
DDR_B_D30
@
<8>
DDR_B_BS2
DDR_B_BS2
Layout Note:
Place near JDIMM3.Pin 203,204
DDR_B_MA3
DDR_B_MA1
<8>
<8>
M_CLK_DDR6
M_CLK_DDR#6
<16,8>
DDR_B_BS0
<16,8> DDR_B_WE#
<16,8> DDR_B_CAS#
M_CLK_DDR6
M_CLK_DDR#6
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
1
<8>
DDR_CS7_DIMM3#
DDR_B_D37
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
B
DDR_B_D38
DDR_B_D34
DDR_B_D44
DDR_B_D40
+3.3V_RUN
DDR_B_D46
DDR_B_D47
DIMM2
0
0
DIMM4
0
1
DIMM1
1
0
DIMM3
1
1
2
1
1
SA1
DDR_B_D48
DDR_B_D53
@RD27
@
RD27
0_0402_5%
*
SA0
@RD26
@
RD26
0_0402_5%
2
DIMM Select
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D50
DDR_B_D57
DDR_B_D56
DIMM3_SA1
DIMM3_SA0
DDR_B_D62
DDR_B_D58
+3.3V_RUN
DIMM3_SA0
DIMM3_SA1
1
2
@ CD66
2.2U_0402_6.3V6M
2
CD65
0.1U_0402_16V4Z
1
A
+0.675V_DDR_VTT
205
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G1
G2
TYCO_2-2013289-1~D
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
D
Bottom Side
DDR_B_D2
DDR_B_D6
DDR_B_D14
DDR_B_D15
DDR3_DRAMRST#_R
DDR3_DRAMRST#_R
<13,14,16>
DDR_B_D10
DDR_B_D12
DDR_B_D17
DDR_B_D16
+SB_DIMM_VREFDQ
DDR_B_D19
DDR_B_D18
+SB_DIMM_VREFDQ_Q
+1.35V_MEM
1
@RD11
@
RD11
2
0_0402_5%
DDR_B_D28
DDR_B_D25
@ QD6B
DMN66D0LDW-7_SOT363-6
4
3
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D27
DDR_B_D26
RD48 1
DDR_CKE7_DIMM3
1
DDR_HVREF_RST_PCH
DDR_HVREF_RST_PCH
2
<8>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR7
M_CLK_DDR#7
DDR_B_BS1
DDR_B_RAS#
M_ODT6
M_ODT7
M_CLK_DDR7
M_CLK_DDR#7
+SB_DIMM2_VREFDQ
2 2_0402_1%
C
<8>
<8>
DDR_B_BS1 <16,8>
DDR_B_RAS#
<16,8>
DDR_CS6_DIMM3#
M_ODT6 <8>
M_ODT7
<8>
<8>
+DIMM3_VREF_CA
1
@RD25
@
RD25
DDR_B_D36
DDR_B_D32
1
DDR_B_D35
DDR_B_D39
2
1
2
2
0_0402_5%
+SM_VREF_DIMM
CD64
0.1U_0402_16V4Z
2
CD62
1U_0402_6.3V6K
2
CD61
1U_0402_6.3V6K
2
CD60
1U_0402_6.3V6K
CD59
1U_0402_6.3V6K
2
1
JDIMM4
RC111
24.9_0402_1%
DDR_B_MA8
DDR_B_MA5
+0.675V_DDR_VTT
JDIMM2
DDR_B_DQS#0
DDR_B_DQS0
@CD63
@
CD63
2.2U_0402_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_CKE6_DIMM3
DDR_B_MA12
DDR_B_MA9
1
DDR_B_D1
DDR_B_D5
<13,21,7>
<16,8>
1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
RD49
1K_0402_1%
2
1
CD58
330U_SX_2VY
2
1
@CD57
@
CD57
10U_0603_6.3V6M
2
1
CD56
10U_0603_6.3V6M
2
1
CD55
10U_0603_6.3V6M
2
1
CD54
10U_0603_6.3V6M
2
1
CD53
10U_0603_6.3V6M
2
CD52
10U_0603_6.3V6M
CD51
10U_0603_6.3V6M
C
1
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
RD50
1K_0402_1%
DDR_B_D22
DDR_B_D23
+1.35V_MEM
1
C
B
CONN@
CD91
0.022U_0402_16V7K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
1
CD45
0.1U_0402_16V4Z
DDR_B_MA[0..15]
@CD49
@
CD49
2.2U_0402_6.3V6M
<16,8>
A
+1.35V_MEM
JDIMM3
+V_DDR_REF
D
+1.35V_MEM
2
2
0_0402_5%
1
1
@RD24
@
RD24
2
DDR_B_D[0..63]
+DIMM3_VREF_DQ
1
DDR_B_DQS[0..7]
<16,8>
2
0_0402_5%
2
<16,8>
1
+SB_DIMM2_VREFDQ
@RD23
@
RD23
JDIMM3
D
CPU
DDR_B_DQS#[0..7]
5
<16,8>
JDIMM1
B
DDR_B_D41
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D42
DDR_B_D52
DDR_B_D49
DDR_B_D51
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D59
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<13,14,16,18,21,45>
<13,14,16,18,21,45>
+0.675V_DDR_VTT
A
206
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DDRIII-SODIMM SLOT3
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
15
of
67
5
4
3
All VREF traces should
have 10 mil trace width
<15,8>
DDR_B_DQS[0..7]
<15,8>
DDR_B_D[0..63]
<15,8>
+SB_DIMM2_VREFDQ
1
@ RD32
2
0_0402_5%
+V_DDR_REF
1
@ RD33
2
0_0402_5%
2
2
1
2
CD69
1U_0402_6.3V6K
1
CD72
1U_0402_6.3V6K
2
CD71
1U_0402_6.3V6K
CD70
1U_0402_6.3V6K
1
1
2
CD68
0.1U_0402_16V4Z
+1.35V_MEM
CD67
2.2U_0402_6.3V6M
1
2
DDR_B_D1
DDR_B_D5
DDR_B_D2
DDR_B_D6
DDR_B_D14
DDR_B_D15
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D12
DDR_B_D17
DDR_B_D16
DDR_B_DQS#2
DDR_B_DQS2
+1.35V_MEM
DDR_B_D19
DDR_B_D18
2
1
+
2
DDR_B_D28
DDR_B_D25
CD80
330U_SX_2VY
2
1
@CD79
@
CD79
10U_0603_6.3V6M
2
1
CD78
10U_0603_6.3V6M
2
1
CD77
10U_0603_6.3V6M
2
1
CD76
10U_0603_6.3V6M
2
1
CD75
10U_0603_6.3V6M
1
CD74
10U_0603_6.3V6M
2
CD73
10U_0603_6.3V6M
1
+1.35V_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_B_D27
DDR_B_D26
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CONN@
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
JDIMM3
D
CPU
+1.35V_MEM
D
1
Top Side
JDIMM1
+DIMM4_VREF_DQ
JDIMM4
DDR_B_MA[0..15]
1
JDIMM4 REV Type H=5.2
DDR_B_DQS#[0..7]
@
<15,8>
2
C
B
A
DDR_B_D0
DDR_B_D4
JDIMM4
JDIMM2
DDR_B_DQS#0
DDR_B_DQS0
D
Bottom Side
DDR_B_D7
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR3_DRAMRST#_R
DDR3_DRAMRST#_R
<13,14,15>
DDR_B_D11
DDR_B_D13
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D30
C
C
<15,8>
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
Layout Note:
Place near JDIMM4.Pin 203,204
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<8>
<8>
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
+0.675V_DDR_VTT
<15,8>
2
1
2
DDR_B_BS0
<15,8> DDR_B_WE#
<15,8> DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
<8>
DDR_CS3_DIMM4#
DDR_B_D36
DDR_B_D32
DDR_B_DQS#4
DDR_B_DQS4
B
DDR_B_D35
DDR_B_D39
DDR_B_D41
DDR_B_D45
DDR_B_D43
DDR_B_D42
1
2
+3.3V_RUN
DDR_B_D52
DDR_B_D49
@ RD36
0_0402_5%
DIMM Select
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D54
DIMM4_SA1
0
DIMM4
0
1
DIMM1
1
0
DIMM3
1
1
1
*
DDR_B_D60
DDR_B_D61
DIMM4_SA0
2
SA1
0
@ RD37
0_0402_5%
SA0
DIMM2
DDR_B_D63
DDR_B_D59
+3.3V_RUN
DIMM4_SA0
DIMM4_SA1
2
@
1
CD88
2.2U_0402_6.3V6M
2
CD87
0.1U_0402_16V4Z
1
A
+0.675V_DDR_VTT
205
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G1
G2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_CKE3_DIMM4
<8>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
M_ODT2
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
<8>
<8>
DDR_B_BS1 <15,8>
DDR_B_RAS#
<15,8>
DDR_CS2_DIMM4#
M_ODT2 <8>
M_ODT3
<8>
<8>
+DIMM4_VREF_CA
1
@ RD34
DDR_B_D37
DDR_B_D33
1
DDR_B_D38
DDR_B_D34
2
1
2
2
0_0402_5%
+SM_VREF_DIMM
CD86
0.1U_0402_16V4Z
CD84
1U_0402_6.3V6K
2
1
CD83
1U_0402_6.3V6K
1
CD82
1U_0402_6.3V6K
2
CD81
1U_0402_6.3V6K
1
DDR_B_MA10
DDR_B_BS0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
CD85
2.2U_0402_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_CKE2_DIMM4
@
<8>
B
DDR_B_D44
DDR_B_D40
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D53
DDR_B_D55
DDR_B_D50
DDR_B_D57
DDR_B_D56
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D58
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<13,14,15,18,21,45>
<13,14,15,18,21,45>
+0.675V_DDR_VTT
A
206
TYCO_2-2013290-1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DDRIII-SODIMM SLOT4
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
16
of
67
5
4
3
2
1
+3.3V_MXM
+3.3V_MXM
2
2
CONN@
100mil(2.5A, 5VIA)
@ R1970 1
@ R1971 1
<30> MXM_ENVDD
<30> MXM_PANEL_BKEN
<30> MXM_BIA_PWM
2 0_0402_5%
2 0_0402_5%
C
pin 71, 73: Remove MXM_LVDS_DDC
T176 @ PAD~D
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P4
1
2
@
<51>
GPU_SMBCLK
<51>
D
JMXM1B
1
2
1
2
1
2
1
2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0
GND
GND
GND
GND
GND
E3
GND
GND
GND
GND
5V
5V
5V
5V
5V
GND
GND
GND
GND
PEX_STD_SW#
VGA_DISABLE#
PNL_PWR_EN
PNL_BL_EN
PNL_BL_PWM
HDMI_CEC
DVI_HPD
LVDS_DDC_DAT
LVDS_DDC_CLK
GND
OEM
OEM
OEM
OEM
GND
PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
GND
GND
GND
GND
GND
E4
GND
GND
GND
GND
PRSNT_R#
WAKE#
PWR_GOOD
PWR_EN
RSVD
RSVD
RSVD
RSVD
PWR_LEVEL
TH_OVERT#
TH_ALERT#
TH_PWM
GPIO0
GPIO1
GPIO2
SMB_DAT
SMB_CLK
GND
OEM
OEM
OEM
OEM
GND
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
<20>
<20>
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
@ R1972 1
DGPU_PWROK
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_VGA
MXM_PRESENTR#
<23>
PCIE_WAKE#
<32,42,50>
2 0_0402_5%
DGPU_PWR_EN
<19>
MXM_PWR_LEVEL
MXM_OVERT#
MXM_ALERT#
GPU_SMBDAT_R
GPU_SMBCLK_R
SYSTEM
MB_HDMI/
Docking DP port 2
PAD~D @ T175
MXM_PIN80_R for 3D function usage (JMXM1_pin 80).
PEG_CTX_GRX_N15
PEG_CTX_GRX_P15
<38>
<38>
MXM_DPC_N0
MXM_DPC_P0
MXM_DPC_N0
MXM_DPC_P0
<38>
<38>
MXM_DPC_N1
MXM_DPC_P1
MXM_DPC_N1
MXM_DPC_P1
<38>
<38>
MXM_DPC_N2
MXM_DPC_P2
MXM_DPC_N2
MXM_DPC_P2
<38>
<38>
MXM_DPC_N3
MXM_DPC_P3
MXM_DPC_N3
MXM_DPC_P3
<38>
<38>
PEG_CTX_GRX_N14
PEG_CTX_GRX_P14
MXM_DPC_AUX#
MXM_DPC_AUX
MXM_DPC_AUX#
MXM_DPC_AUX
PEG_CTX_GRX_N13
PEG_CTX_GRX_P13
PEG_CTX_GRX_N12
PEG_CTX_GRX_P12
PEG_CTX_GRX_N11
PEG_CTX_GRX_P11
PEG_CTX_GRX_N10
PEG_CTX_GRX_P10
PEG_CTX_GRX_N9
PEG_CTX_GRX_P9
PEG_CTX_GRX_N8
PEG_CTX_GRX_P8
MB_DP/TBT
PEG_CTX_GRX_N7
PEG_CTX_GRX_P7
PEG_CTX_GRX_N6
PEG_CTX_GRX_P6
<31>
<31>
MXM_DPA_N0
MXM_DPA_P0
MXM_DPA_N0
MXM_DPA_P0
<31>
<31>
MXM_DPA_N1
MXM_DPA_P1
MXM_DPA_N1
MXM_DPA_P1
<31>
<31>
MXM_DPA_N2
MXM_DPA_P2
MXM_DPA_N2
MXM_DPA_P2
<31>
<31>
MXM_DPA_N3
MXM_DPA_P3
MXM_DPA_N3
MXM_DPA_P3
MXM_DPA_AUX#
MXM_DPA_AUX
MXM_PRESENTL#
<31> MXM_DPA_AUX#
<31> MXM_DPA_AUX
<23> MXM_PRESENTL#
PEG_CTX_GRX_N5
PEG_CTX_GRX_P5
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
263
265
267
269
271
273
275
277
279
281
283
285
287
289
291
293
295
297
299
301
303
305
307
309
310
311
PEG_CTX_GRX_N4
PEG_CTX_GRX_P4
CONN@
GND
PEX_RX2#
PEX_RX2
GND
PEX_RX1#
PEX_RX1
GND
PEX_RX0#
PEX_RX0
GND
PEX_REFCLK#
PEX_REFCLK
GND
RSVD
RSVD
RSVD
RSVD
RSVD
LVDS_UCLK#
LVDS_UCLK
GND
LVDS_UTX3#
LVDS_UTX3
GND
LVDS_UTX2#
LVDS_UTX2
GND
LVDS_UTX1#
LVDS_UTX1
GND
LVDS_UTX0#
LVDS_UTX0
GND
DP_C_L0#
DP_C_L0
GND
DP_C_L1#
DP_C_L1
GND
DP_C_L2#
DP_C_L2
GND
DP_C_L3#
DP_C_L3
GND
DP_C_AUX#
DP_C_AUX
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
DP_A_L0#
DP_A_L0
GND
DP_A_L1#
DP_A_L1
GND
DP_A_L2#
DP_A_L2
GND
DP_A_L3#
DP_A_L3
GND
DP_A_AUX#
DP_A_AUX
PRSNT_L#
GND
PEX_TX2#
PEX_TX2
GND
PEX_TX1#
PEX_TX1
GND
PEX_TX0#
PEX_TX0
GND
PEX_CLK_REQ#
PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK
VGA_VSYNC
VGA_HSYNC
GND
VGA_RED
VGA_GREEN
VGA_BLUE
GND
LVDS_LCLK#
LVDS_LCLK
GND
LVDS_LTX3#
LVDS_LTX3
GND
LVDS_LTX2#
LVDS_LTX2
GND
LVDS_LTX1#
LVDS_LTX1
GND
LVDS_LTX0#
LVDS_LTX0
GND
DP_D_L0#
DP_D_L0
GND
DP_D_L1#
DP_D_L1
GND
DP_D_L2#
DP_D_L2
GND
DP_D_L3#
DP_D_L3
GND
DP_D_AUX#
DP_D_AUX
DP_C_HPD
DP_D_HPD
RSVD
RSVD
RSVD
GND
DP_B_L0#
DP_B_L0
GND
DP_B_L1#
DP_B_L1
GND
DP_B_L2#
DP_B_L2
GND
DP_B_L3#
DP_B_L3
GND
DP_B_AUX#
DP_B_AUX
DP_B_HPD
DP_A_HPD
3V3
3V3
GND
GND
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
MXM_CLK_REQ#
DGPU_PEX_RST#
MXM_CRT_VSYNC
MXM_CRT_HSYNC
MXM_CRT_DDC_DAT
<35>
MXM_CRT_DDC_CLK
<35>
MXM_CRT_VSYNC
<35>
MXM_CRT_HSYNC
<35>
MXM_CRT_RED
MXM_CRT_GRN
MXM_CRT_BLU
MXM_CRT_RED
MXM_CRT_GRN
MXM_CRT_BLU
MXM_EDP_LANE_N0
MXM_EDP_LANE_P0
MXM_EDP_LANE_N0
MXM_EDP_LANE_P0
<29>
<29>
MXM_EDP_LANE_N1
MXM_EDP_LANE_P1
MXM_EDP_LANE_N1
MXM_EDP_LANE_P1
<29>
<29>
MXM_EDP_LANE_N2
MXM_EDP_LANE_P2
MXM_EDP_LANE_N2
MXM_EDP_LANE_P2
<29>
<29>
MXM_EDP_LANE_N3
MXM_EDP_LANE_P3
MXM_EDP_LANE_N3
MXM_EDP_LANE_P3
<29>
<29>
CRT
<35>
<35>
<35>
C
MXM_EDP_AUX#
MXM_EDP_AUX
MXM_DPC_HPD_GATE
MXM_EDP_HPD
eDP MUX
MXM_EDP_AUX# <29>
MXM_EDP_AUX <29>
MXM_EDP_HPD
<29>
MXM_RSVD1
MXM_RSVD2
MXM_DPB_N0
MXM_DPB_P0
MXM_DPB_N0
MXM_DPB_P0
<36>
<36>
MXM_DPB_N1
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_P1
<36>
<36>
MXM_DPB_N2
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P2
<36>
<36>
MXM_DPB_N3
MXM_DPB_P3
MXM_DPB_N3
MXM_DPB_P3
<36>
<36>
MXM_DPB_AUX#
MXM_DPB_AUX
MXM_DPB_HPD_GATE
MXM_DPA_HPD_GATE
WiGig/
Docking DP port 1
MXM_DPB_AUX# <36>
MXM_DPB_AUX <36>
+3.3V_MXM
40mil(1A)
+3.3V_MXM
312
JAE_MM70-314-310B1-1-R300
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
LInk CIS
1
2
JAE_MM70-314-310B1-1-R300
LInk CIS
1
2
B
C8
0.1U_0402_16V4Z
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P3
GPU_SMBDAT
3
C332
10U_0603_6.3V6M
B
4
Q295B
DMN66D0LDW-7_SOT363-6
C1
0.1U_0603_25V7K
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
+5V_MXM
6
Q295A
DMN66D0LDW-7_SOT363-6
<50>
400mil(10A)
2
4
6
8
10
12
14
16
18
C4
68P_0402_50V8J
E2
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
C3
680P_0603_50V7K
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC E1
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
C2
10U_0805_25VAK
C7
0.1U_0402_16V7K
2
C328
10U_0603_6.3VAM
2
DGPU_ALERT#
Q5
DMN65D8LW-7_SOT323-3
+5V_MXM
1
1
+MXM_PWR_SRC
JMXM1A
1
3
5
7
9
11
13
15
17
1
1
GPU_SMBDAT_R
3
GPU_SMBCLK_R
D
+MXM_PWR_SRC
2
@
2
MXM_ALERT#
5
2
2
2
@ R5
PEG_CTX_GRX_N[0..15]
D
2
@ R3
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
S
1
1
R1977
1
R1978
1
@ R6
1
@ R1979
PEG_CRX_GTX_C_N[0..15]
PEG_CTX_GRX_P[0..15]
MXM_CRT_DDC_DAT
4.3K_0402_5%
MXM_CRT_DDC_CLK
4.3K_0402_5%
DGPU_PWROK
10K_0402_5%
MXM_CLK_REQ#
10K_0402_5%
MXM_RSVD1
0_0402_5%
MXM_RSVD2
0_0402_5%
G
<6>
2
1
PEG_CRX_GTX_C_N[0..15]
<6>
1
2
<6>
PEG_CRX_GTX_C_P[0..15]
R2
4.7K_0402_5%
PEG_CRX_GTX_C_P[0..15]
R4
10K_0402_5%
<6>
R1
4.7K_0402_5%
1
+3.3V_MXM
+3.3V_MXM
PCB Footprint: JAE_MM70-314-310B1-1-R3_310P-S
+3.3V_MXM
+3.3V_MXM
5
MXM_DPC_HPD
<38>
2
P
4
IN1
O
2
IN2
G
5
P
G
3
2
P
G
1
2
MXM_DPA_HPD_GATE
2
U25
SN74AHC1G08DCKR_SC70-5
MXM_DPA_HPD
2
ACAV_IN
<51,62,63>
2
GPU_PWR_LEVEL
<50>
1
DGPU_PEX_RST#
2
1
MXM_OVERT#
3
1
A
U17
74AHC1G09GW_TSSOP5~D
DGPU_THERMTRIP#
D
A
S
B
O
3
4
P
5
1
DGPU_PWROK
1
<23,50>
G
1
RB751VM-40TE-17_SOD323-2
<51>
Q4
DMN65D8LW-7_SOT323-3
D18
2
+3.3V_ALW
2
@ C92
1
2
0.1U_0402_10V7K
G
1
2
<50>
MXM_PWR_LEVEL
MXM_DPB_HPD
<31>
U27
SN74AHC1G08DCKR_SC70-5
R11
10K_0402_5%
MXM_DP_HDMI_HPD
D8
2
IN2
+3.3V_MXM
RB751VM-40TE-17_SOD323-2
MXM_DPA_HPD
IN1
O
2
DGPU_PWROK
R10
10K_0402_5%
1
4
1
R135
100K_0402_5%
2
<36>
DGPU_PWROK
+3.3V_MXM
R37
100K_0402_5%
A
MXM_DPB_HPD
1
0.1U_0402_10V7K
+3.3V_ALW
0_0402_5%
D7
MXM_DPC_HPD
MXM_DPC_HPD_GATE
2
U14
SN74AHC1G08DCKR_SC70-5
2
@ R19
0.1U_0402_10V7K
2
2
1
<19>
IN2
3
1
PLTRST_GPU#
<19>
R51
100K_0402_5%
3
2
U16
74AHC1G09GW_TSSOP5~D
1
P
G
A
O
DGPU_HOLD_RST#
IN1
O
DGPU_PWROK
@ C94
1
2
@ R60
100K_0402_5%
B
4
1
@ R519
100K_0402_5%
5
MXM_DPB_HPD_GATE
1
@ R758
100K_0402_5%
2
0.1U_0402_10V7K
4
DGPU_PEX_RST#
0.1U_0402_10V7K
5
@ C90
1
2
+3.3V_MXM
@ C95
1
3
@ C96
1
2
1
+3.3V_ALW
R38
750_0402_1%
1
+3.3V_MXM
1
RB751VM-40TE-17_SOD323-2
DELL CONFIDENTIAL/PROPRIETARY
Remove DYN_TURB_GPU_PWR_ALRT#
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
MXM
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
17
of
67
5
4
3
2
1
PCH XDP
+3.3V_ALW_PCH
1
3
5
7
9
XDP_FN0
1
11
XDP_FN1
13
15
XDP_FN2
2
17
XDP_FN3
19
21
23
25
27
XDP_FN4
29
XDP_FN5
31
33
XDP_FN6
35
XDP_FN7
37
39
RSMRST#_XDP
2
41
PCH_PWRBTN#_XDP
43
0_0402_5%
45
47
49
0_0402_5%
2
51
DDR_XDP_WAN_SMBDAT_R2
2
53
DDR_XDP_WAN_SMBCLK_R2
55
0_0402_5%
57
PCH_JTAG_TCK
59
+3.3V_ALW_PCH
+RTC_CELL
PXDP@
CH2
0.1U_0402_25V6K
2
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
<13,14,15,16,21,45>
<13,14,15,16,21,45>
1
PXDP@ RH28
SIO_PWRBTN#_R
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
PXDP@ RH30
1
1
PXDP@ RH31
SAMTE_BSH-030-01-L-D-A
2
@RH35
@
RH35
NO REBOOT STRAP
PCH_AZ_SDOUT
1K_0402_1%
FLASH DESCRIPTOR SECURITY OVERRIDE
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
<23> PCH_GPIO36
<23,45> HDD2_DET#
<23,50> SATA4_PCIE1#
<23,51> SSD_SATA5_PCIE2#
<20,39> LANCLK_REQ#
<20,49> CARDCLK_REQ#
<23,51> SIO_EXT_WAKE#
<23> PCH_GPIO35
<19,53> PCH_RSMRST#_Q
<11,19,51,7> RESET_OUT#
+3.3V_ALW_PCH
+3.3V_RUN
1
2
RH40
PCH_GPIO33
10K_0402_5%
1
2
PCH_AZ_SYNC
1K_0402_1%
1
2
PCH_GPIO13
10K_0402_5%
@ RH41
C
RH60
CMOS_CLR1
Clear CMOS
Keep CMOS
CH4
2
18P_0402_50V8J
PCH_RTCX1_R 1
@ RH38
2
0_0402_5%
YH1
32.768KHZ_12.5PF_Q13FC1350000
TPM setting
Clear ME RTC Registers
Open
Keep ME RTC Registers
1
RH42 1
+RTC_CELL
2 20K_0402_5%
RH43 1
CH5
2
18P_0402_50V8J
2 1M_0402_5%
RH44 1
<41>
B5
PCH_RTCX2
B4
SRTCRST#
B9
A8
G10
1
1
2
2
SPKR
PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_SDIN0
2
L22
K22
G22
A
B
C
G1
G2
F22
ME_FWP
1
RH45
2
A24
PCH_GPIO13
C22
B17
SATA_RXN_0
SATA_RXP_0
RTCX1
RTCX2
SRTCRST#
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
INTRUDER#
INTVRMEN
SATA_TXN_1
SATA_TXP_1
RTCRST#
SATA_RXN_2
SATA_RXP_2
HDA_BCLK
SATA_TXN_2
SATA_TXP_2
HDA_SYNC
SPKR
SATA_RXN_3
SATA_RXP_3
HDA_RST#
HDA_SDI0
SATA_TXN_3
SATA_TXP_3
HDA_SDI1
SATA_RXN4/PERN1
SATA_RXP4/PERP1
HDA_SDI2
HDA_SDI3
SATA_TXN4/PETN1
SATA_TXP4/PETP1
HDA_SDO
SATA_RXN5/PERN2
SATA_RXP5/PERP2
DOCKEN#/GPIO33
HDA_DOCK_RST#/GPIO13
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
RH48 1
2 210_0402_1%
PCH_JTAG_TMS
AD1
RH50 1
2 210_0402_1%
PCH_JTAG_TDI
AE2
RH52 1
2 210_0402_1%
PCH_JTAG_TDO
1
2
RH56
100_0402_1%
RH55
100_0402_1%
@R793
@
R793
1K_0402_1%
RH54
100_0402_1%
ME_FWP
1
AB3
1
PCH_JTAG_TCK
1
RH53 @
AD3
2 PCH_TP25
0_0402_5%
F8
C26
@T59
@
T59
PAD~D
PCH_JTAG_RST
AB6
JTAG_TCK
SATA0GP/GPIO21
JTAG_TMS
JTAG_TDI
SATA1GP/GPIO19
JTAG
ME_FWP PCH has internal 20K PD.
(suspend power rail)
1 51_0402_1%
2
+3.3V_ALW_PCH_JTAG
RH47 2
2
2
PCH_AZ_SDOUT
1K_0402_1%
PCH_GPIO33
PXDP@ RH46
0_0603_5%
1
+3.3V_ALW_PCH
LOW = ENABLE (DEFAULT)
-->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
1
C24
PCH_AZ_RST#
<49>
SS3-CMFTQR9_3P
2
AL10
SPKR
CMOS place near DIMM
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
SATA_IREF
JTAG_TDO
TP9
TP25
TP8
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
BD9
AY13
AW13
BC12
BE12
AR13
AT13
BD13
BB13
AV15
AW15
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
<45>
<45>
SATA_PTX_DRX_N0_C
SATA_PTX_DRX_P0_C
<45>
<45>
PCH_AZ_CODEC_SDOUT
<49>
<49>
1
2
RH36
1
2
RH37
1
2
1
2
1
2
RH59
PCH_AZ_CODEC_SYNC
RH61
PCH_AZ_CODEC_RST#
RH63
1
PCH_AZ_CODEC_BITCLK
1
2
EMC@ CH9
15P_0402_50V8J
EMC@ RH65
A
HDD1
SATA_ODD_PRX_DTX_N1_C
SATA_ODD_PRX_DTX_P1_C
<46>
<46>
SATA_ODD_PTX_DRX_N1_C
SATA_ODD_PTX_DRX_P1_C
<46>
<46>
SATA_PRX_DKTX_N2_C
SATA_PRX_DKTX_P2_C
<48>
<48>
SATA_PTX_DKRX_N2_C
SATA_PTX_DKRX_P2_C
<48>
<48>
SATA_PRX_DTX_N3_C
SATA_PRX_DTX_P3_C
<45>
<45>
SATA_PTX_DRX_N3_C
SATA_PTX_DRX_P3_C
<45>
<45>
PCIE_PRX_SATATX_N4
PCIE_PRX_SATATX_P4
<42>
<42>
PCIE_PTX_SATARX_N4
PCIE_PTX_SATARX_P4
<42>
<42>
ODD
DOCK
HDD2
M.2 Slot-2
B
BC14
BE14
AP15
AR15
AY5
SATA_COMP
AP3
SATA_ACT#
AT1
HDD1_DET#
AU2
BBS_BIT0_R
BD4
2
SATA_IREF
0_0402_5%
PCIE_PRX_SATATX_N5
PCIE_PRX_SATATX_P5
<43>
<43>
PCIE_PTX_SATARX_N5
PCIE_PTX_SATARX_P5
<43>
<43>
SATA_ACT#
<52>
HDD1_DET#
M.2 Slot-3
QH5
BSS138-G_SOT23-3
<18,45>
1
1
@ RH51
3
BA2
PAD~D
T57 @
PAD~D
T58 @
PCH_SATA_MOD_EN#
<50>
+1.5V_RUN
PCH_PLTRST#
<19,7>
BB2
TP22
TP20
SATA Impedance Compensation
+1.5V_RUN
1
SATA_COMP
7.5K_0402_1%
<49>
<19,7>
PCH_JTAG_RST
0_0402_5%
CONN@
1 OF 11
HDA for Codec
<49>
2
LPT_PCH_M_EDS
AZALIA
B
A22
PCH_AZ_SYNC
<49>
SW2
1
2
3
4
5
B25
PCH_AZ_BITCLK
1
@
CMOS1 SHORT PADS~D
1
2
CH7
1U_0402_6.3VAK
R3728
1K_0402_5%
D9
PCH_RTCRST#
PCH_RTCRST#
2
1 ME_FWP
ME_FWP_EC
@ RC301
0_0402_5%
PT,ST pop R3728 and SW2; MP pop RC301
ME_FWP
XDP_DBRESET#
PCH_JTAG_TDO
1
PCH_JTAG_RST_R
PCH_JTAG_TDI @ RH32
PCH_JTAG_TMS
+3.3V_RUN
UH1A
INTRUDER#
2 20K_0402_5%
+3.3V_ALW_PCH
ME_FWP_EC
+3.3V_ALW_PCH
Change PN from SA00005NE2L to SA00006P30L
RH39
10M_0402_5%
PCH_INTVRMEN
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
<51>
+1.05V_RUN
RESET_OUT#_R
XDP_DBRESET#
HDD1_DET#
10K_0402_5%
BBS_BIT0_R
10K_0402_5%
RTC
Shunt
D
XDP_FN14
XDP_FN15
PCH_RTCX1
2
ME_CLR1
XDP_FN12
XDP_FN13
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
RSMRST#_XDP
RESET_OUT#_R
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1K_0402_1%
1K_0402_1%
2
Shunt
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
XDP_FN10
XDP_FN11
C
1
CMOS setting
Open
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XDP_FN8
XDP_FN9
D
@RH34
@
RH34
1
SPKR
10K_0402_5%
RH3
RH4
RH6
RH7
RH8
RH9
RH17
RH10
RH11
RH13
RH12
RH14
RH16
RH19
RH20
RH22
RH24
RH25
RH26
RH27
SATA
2
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
1
1
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
HDD1_DET#
BBS_BIT0_R
PCH_GPIO36
HDD2_DET#
SATA4_PCIE1#
SSD_SATA5_PCIE2#
LANCLK_REQ#
CARDCLK_REQ#
SIO_EXT_WAKE#
PCH_GPIO35
PCH_RSMRST#_Q
RESET_OUT#
<22> USB_OC0#_R
<22> USB_OC1#_R
<22,49> USB_OC2#
<22> USB_OC3#
<22> USB_OC4#_R
<22> USB_OC5#
<22> USB_OC6#
<22,51> SIO_EXT_SMI#
<18,45> HDD1_DET#
+3.3V_ALW_PCH
1
+3.3V_RUN
XDP_FN16
XDP_FN17
S
1
@RH18
@
RH18
330K_0402_1%
<19,7>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
2
G
2
1
RH5
330K_0402_1%
PCH_INTVRMEN
D
JXDP2
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
PCH_AZ_SDOUT
33_0402_5%
PCH_AZ_SYNC
33_0402_5%
PCH_AZ_RST#
33_0402_5%
2 PCH_AZ_BITCLK
33_0402_5%
2
RH57
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (1/9)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
18
of
67
5
4
3
2
1
+3.3V_RUN
2
0_0402_5%
+3.3V_RUN
A
3
CIS LINK OK
2
4
SYS_RESET#
SYS_RESET#
<41>
@ UC3
74AHC1G09GW_TSSOP5~D
+3.3V_ALW2
@ CH11
1
2
CIS LINK OK
1
RH75
1
RH84
1
2
PCH_RSMRST#_R
0_0402_5%
<51>
2
CLKRUN#
8.2K_0402_5%
2
ME_RESET#
8.2K_0402_5%
2
DGPU_PWR_EN
10K_0402_5%
1
@ RH93
1
RH330
ME_SUS_PWR_ACK_R
@ RH91
<6>
<6>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
<6>
<6>
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<6>
<6>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
<6>
<6>
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<6>
<6>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
<6>
<6>
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
+1.5V_RUN
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
AW22
AR20
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
AP17
AV20
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
AY22
AP20
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AR17
AW20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
BD21
BE20
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
BD17
BE18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
BB21
BC20
BB17
BC18
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
2
1
DMI_IREF
0_0402_5%
@ RH98
BE16
AW17
@ T65
PAD~D
@ T67
1
+1.5V_RUN
2
1
SUSACK#
PAD~D
DMI_RCOMP
7.5K_0402_1%
AY17
2
SUSACK#_R
0_0402_5%
SYS_RESET#
R6
RH100
@RH101
@
RH101
<11,18,51,7>
RESET_OUT#
<61>
PCH_PWROK
<18,53>
PCH_RSMRST#_Q
<51> ME_SUS_PWR_ACK
<18,7> SIO_PWRBTN#_R
<51> SIO_PWRBTN#
<51>
1
@ RH104
1
PCH_RSMRST#_Q
@ RH105
1
@ RH258
1
@ RH259
AC_PRESENT
+PCH_VCCDSW3_3
1
RH112
@ T144
<44,50>
AM1
AD7
PCH_PWROK
F10
2
AB7
PM_DRAM_PWRGD_R
0_0402_5%
2
PCH_RSMRST#_R
0_0402_5%
2
ME_SUS_PWR_ACK_R
0_0402_5%
2
SIO_PWRBTN#_R
0_0402_5%
AC_PRESENT
H3
2
K7
PCH_BATLOW#
8.2K_0402_5%
PCH_RI#
J2
J4
K1
E6
N4
AB10
PAD~D
SIO_SLP_WLAN#
2
SIO_SLP_WLAN#
D2
DSWODVREN - ON DIE DSW VR ENABLE
FDI_RXN_0
DMI_RXN_2
DMI_RXN_3
FDI_RXN_1
DMI_RXP_0
DMI_RXP_1
FDI_RXP_0
FDI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
TP16
TP5
DMI
FDI
TP15
DMI_TXN_2
DMI_TXN_3
TP10
DMI_TXP_0
DMI_TXP_1
FDI_CSYNC
FDI_INT
DMI_TXP_2
DMI_TXP_3
FDI_IREF
DMI_IREF
TP17
TP12
TP13
TP7
FDI_RCOMP
AJ35
FDI_CTX_PRX_N0
AL35
FDI_CTX_PRX_N1
AJ36
FDI_CTX_PRX_P0
AL36
FDI_CTX_PRX_P1
FDI_CTX_PRX_N0
AV43
PAD~D
T132 @
AY45
PAD~D
T133 @
AV45
PAD~D
T130 @
AW44
PAD~D
T131 @
AL39
FDI_CSYNC
AL40
FDI_INT
AT45
AU42
2
FDI_IREF
@ RH96
PAD~D
AU44
PAD~D
AR44
FDI_RCOMP
7.5K_0402_1%
<9>
FDI_CTX_PRX_P0
<9>
FDI_CTX_PRX_P1
<9>
<35>
<35>
FDI_CSYNC
2
<35>
<6>
<35>
FDI_INT <6>
1
+1.5V_RUN
0_0402_5%
T134 @
PCH_CRT_BLU
<35>
PCH_CRT_GRN
<35>
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_CRT_HSYNC
PCH_CRT_BLU
T45
PCH_CRT_GRN
U44
PCH_CRT_RED
V45
PCH_CRT_DDC_CLK
M43
PCH_CRT_DDC_DAT
M45
1
2
N42
1
2
N44
HSYNC
20_0402_1%
VSYNC
20_0402_1%
2 CRT_IREF
649_0402_1%
RH94
PCH_CRT_VSYNC
RH95
1
RH97
SUSACK#
DSWVRMEN
SYS_RESET#
DPWROK
SYS_PWROK
WAKE#
PWROK
CLKRUN#
System Power
Management
APWROK
SUS_STAT#/GPIO61
DRAMPWROK
SUSCLK/GPIO62
RSMRST#
SLP_S5#/GPIO63
SUSWARN#/SUSPWRNACK/GPIO30
SLP_S4#
PWRBTN#
SLP_S3#
ACPRESENT/GPIO31
SLP_A#
BATLOW#/GPIO72
SLP_SUS#
RI#
PMSYNCH
TP21
SLP_LAN#
C8
DSWODVREN
L13
PCH_DPWROK
K3
PCH_PCIE_WAKE#
AN7
CLKRUN#
1
RH99
SUS_STAT#/LPCPD#
Y6
SUSCLK_R
@ R3731
Y7
SIO_SLP_S5#
C6
SIO_SLP_S4#
H1
SIO_SLP_S3#
F3
SIO_SLP_A#
F1
SIO_SLP_SUS#
AY3
H_PM_SYNC
G5
SIO_SLP_LAN#
DDPB_CTRLCLK
VGA_GREEN
DDPB_CTRLDATA
VGA_RED
DDPC_CTRLCLK
VGA_DDC_CLK
DDPC_CTRLDATA
VGA_DDC_DATA
DDPD_CTRLCLK
VGA_HSYNC
DDPD_CTRLDATA
VGA_VSYNC
DAC_IREF
VGA_IRTN
<30>
BIA_PWM_PCH
<30>
PANEL_BKEN_PCH
+1.5V_RUN
BIA_PWM_PCH
N36
PANEL_BKEN_PCH
K36
ENVDD_PCH
G36
PCI_PIRQA#
H20
ENVDD_PCH
<51>
PCH_PCIE_WAKE#
<51>
<50,51>
Diesel connect to TPM
1
DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
PCH_DPWROK
CLKRUN#
U7
U40
U39
2 0_0402_5%
SUSCLK
T146 PAD~D @
SIO_SLP_S5# <32,41,51>
T118 PAD~D @
SIO_SLP_S4# <41,51,54,57>
SIO_SLP_S3#
<17>
<42,43>
L20
PCI_PIRQC#
K17
PCI_PIRQD#
M20
DGPU_HOLD_RST# A12
DGPU_HOLD_RST#
<17>
B13
DGPU_PWR_EN
DGPU_PWR_EN
C12
C10
BBS_BIT1
A10
<32,41,51,54>
Remove
PCH_GPIO55
USB_MCARD1_DET#
SIO_SLP_A# <41,51,54,58>
T145 PAD~D @
SIO_SLP_SUS# <51>
T129 PAD~D @
H_PM_SYNC
<7>
SIO_SLP_LAN#
PCI_PIRQB#
Remove CPPE#
AL6
EDP_BKLTCTL
DDPB_AUXP
EDP_BKLTEN
DDPC_AUXP
EDP_VDDEN
DDPD_AUXP
DDPB_HPD
PIRQA#
DDPC_HPD
PIRQB#
DDPD_HPD
R40
R39
C
R35
R36
N40
PCH_DDPD_CTRLCLK
N38
PCH_DDPD_CTRLDATA
PCH_DDPD_CTRLCLK
<36>
PCH_DDPD_CTRLDATA
<36>
H45
K43
J42
PCH_DDPD_AUX#
PCH_DDPD_AUX#
<36>
H43
K45
J44
PCH_DDPD_AUX
PCH_DDPD_AUX
<36>
K40
K38
H39
DPD_PCH_HPD
DPD_PCH_HPD
<36>
PIRQC#
PIRQD#
PIRQE#/GPIO2
GPIO50
PCI
GPIO52
PIRQF#/GPIO3
PIRQG#/GPIO4
GPIO54
PIRQH#/GPIO5
GPIO51
PME#
GPIO53
PLTRST#
G17
LCD_CBL_DET#
F17
PCH_GPIO3
L15
CAM_MIC_CBL_DET#
LCD_CBL_DET#
Y11 PCH_PLTRST#
5 OF 11
2
2
2
2
2
1
1
1
1
1
B
<30>
1
HDD_FALL_INT
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
GPIO55
<30>
CAM_MIC_CBL_DET#
M15 FFS_PCH_INT
2
@ RH106
AD10
@ T141 PAD~D
<45>
@ RH109
@ RH110
@ RH111
@ RH129
@ RH114
PLTRST_USH# <41>
PLTRST_MMI# <49>
PLTRST_LAN# <39>
PLTRST_TBT# <32>
PLTRST_GPU# <17>
+3.3V_RUN
<39,51>
@ CH12
1
2
SLP_WLAN#/GPIO29
1
RH118
0
0
0
1
1
0
PCI
1
1
SPI
PCH_PLTRST#
1
2
B
P
PCH_PLTRST#
A
O
4
PCH_PLTRST#_EC
PCH_PLTRST#_EC
<41,42,43,50,51>
UH3
NL17SZ08DFT2G_SC70
Boot BIOS Location
LPC
Reserved (NAND)
2
@ RH119
1K_0402_1%
BBS_BIT1
SATA_SLPD
(BBS_BIT0)
<18,7>
G
1
RH117
3
1
RH116
2 PCH_CRT_BLU
150_0402_1%
2 PCH_CRT_GRN
150_0402_1%
2 PCH_CRT_RED
150_0402_1%
2 ENVDD_PCH
100K_0402_5%
5
0.1U_0402_25V7K
Boot BIOS Strap
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
VGA_BLUE
T66 @
2PCH_RSMRST#_Q
10K_0402_5%
Remove DGPU_PWR_EN inverter circuit.
A
DELL CONFIDENTIAL/PROPRIETARY
GPIO51 has internal pull up.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
RH86
LPT_PCH_M_EDS
UH1E
<35>
DMI_RCOMP
*
2
2
2
2
<9>
FDI_CTX_PRX_N1
1
A
R97 1
R1251
R1261
R1281
RH83
LPT_PCH_M_EDS
DMI_RXN_0
DMI_RXN_1
RH115
BBS_BIT1
1
A16 SWAP OVERRIDE STRAP
STP_A16OVR
4 OF 11
1
RH89
1
2
0_0402_5%
SUSACK#_R
0_0402_5%
<30,51>
RESET_OUT#
PM_APWROK_R
follow E6 common boot code.
PM_DRAM_PWRGD
1
LVDS
AV17
<7>
2
CRT
<6>
<6>
D
2
PCH_GPIO3
10K_0402_5%
CAM_MIC_CBL_DET#
10K_0402_5%
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_DDPD_CTRLCLK
PCH_DDPD_CTRLDATA
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
UH1B
B
NL17SZ08DFT2G_SC70
@ RH87
1
4PM_APWROK_R
OUT Y
1
RH90
<51>
IN A
0.1U_0402_25V7K
Remove
+3.3V_RUN
C
2
PM_APWROK
PM_APWROK
IN B
PCH_GPIO55
DSWODVREN
UH2
DISPLAY
@ RH73
PCH_DPWROK
@ RH79
3
1
1
SIO_SLP_A#
VCC
PCH_PCIE_WAKE#
10K_0402_5%
2
SUS_STAT#/LPCPD#
10K_0402_5%
2
ME_SUS_PWR_ACK
10K_0402_5%
2
PCH_RI#
10K_0402_5%
GND
2
8.2K_8P4R_5%
2
1
@ RH148
2
1
RH77
DGPU_HOLD_RST#
8.2K_0402_5%
LCD_CBL_DET#
10K_0402_5%
@ RH76
1K_0402_1%
1
@ RH88
@ RH81
330K_0402_1%
D
8
7
6
5
@@
B
O
2
1
1 ME_RESET#
8.2K_0402_5%
2
2
@ RH70
1
2
3
4
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQC#
1
1
XDP_DBRESET#
P
<18,7>
+3.3V_ALW_PCH
0.1U_0402_25V6K
G
1
RH78
5
SIO_SLP_LAN#
10K_0402_5%
2
PCH_PCIE_WAKE#
10K_0402_5%
5
2
RH67
330K_0402_1%
@ CH10
1
2
1
@ RH80
RPH1
1
+PCH_VCCDSW3_3
+RTC_CELL
2
1
@ RH66
4
3
2
Compal Electronics, Inc.
Title
PCH (2/9)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
19
of
67
5
4
3
2
1
1
D
RH128
10K_0402_5%
2
+3.3V_ALW_PCH
D
M.2 card slot 3
<43>
<43>
<43>
CLK_PCIE_NGFF2
+3.3V_ALW_PCH
NGFF2_CLK_REQ#
CLK_PCIE_NGFF3#
CLK_PCIE_NGFF3
+3.3V_ALW_PCH
NGFF3_CLK_REQ#
<39>
10/100/1G LAN
CLK_PCIE_LAN#
<39> CLK_PCIE_LAN
+3.3V_RUN
LANCLK_REQ#
Y45
RH123
2
1 10K_0402_5%
NGFF2_CLK_REQ# AB1
AA44
AA42
RH329
2
1 10K_0402_5%
NGFF3_CLK_REQ# AF1
@ RH82
@ RH92
RH145
2
2
2
1 0_0402_5%
1 0_0402_5%
1 10K_0402_5%
MMI
TBT
<49> CLK_PCIE_CARD#
<49> CLK_PCIE_CARD
<18,49> CARDCLK_REQ#
+3.3V_RUN
<32> CLK_PCIE_TBT#
<32> CLK_PCIE_TBT
+3.3V_ALW_PCH
<32> TBT_PCIECLK_REQ#
+3.3V_ALW_PCH
WLAN (M.2 card slot 1)
WiGig (M.2 card slot 1)
<42> CLK_PCIE_WLAN#
<42> CLK_PCIE_WLAN
+3.3V_ALW_PCH
<42> WLANCLK_REQ#
<42> CLK_PCIE_WIGIG#
<42>
<42>
CLK_PCIE_WIGIG
+3.3V_ALW_PCH
WIGIGCLK_REQ#
AB45
PCIE_LAN
AF3
LANCLK_REQ#
<18,39>
C
AB43
PCIE_LAN#
@ RH121 2
@ RH122 2
RH120
@ RH137
@ RH139
RH125
1
2
2
2
1 0_0402_5%
1 0_0402_5%
2
1
1
1
AD43
PCIE_CARD#
AD45
PCIE_CARD
T3
CARDCLK_REQ#
10K_0402_5%
0_0402_5%
0_0402_5%
10K_0402_5%
AF43
PCIE_TBT#
AF45
PCIE_TBT
TBT_PCIECLK_REQ# V3
2
1 10K_0402_5%
AE44
AE42
AA2
@ RH127 2
@ RH126 2
RH124 2
1 0_0402_5%
1 0_0402_5%
1 10K_0402_5%
AB40
PCIE_WLAN#
AB39
PCIE_WLAN
WLANCLK_REQ# AE4
@ RH144 2
1 0_0402_5%
PCIE_WIGIG#
AJ44
@ RH142 2
1 0_0402_5%
PCIE_WIGIG
AJ42
1 10K_0402_5%
WIGIGCLK_REQ#
RH147
RH140
2
Y3
AH43
AH45
<50>
CLK_PCI_5048
<51>
CLK_PCI_MEC
1 22_0402_5%
PCI_5048
D44
2
1 22_0402_5%
PCI_MEC
E44
EMC@RH162
EMC@
RH162
2
1 22_0402_5%
B42
PCI_DOCK
F41
B
CLK_PCI_LOOPBACK EMC@
EMC@RH164
RH164
2
1 22_0402_5%
PCI_LOOPBACKOUT A40
PEGA_CLKRQ#/GPIO47
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PCIECLKRQ1#/GPIO18
PEGB_CLKRQ#/GPIO56
CLKOUT_PCIE_N_2
CLKOUT_DMI
CLKOUT_PCIE_P_2
CLKOUT_DMI_P
PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLOCK SIGNAL
CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45
CLKIN_SATA
CLKIN_SATA_P
CLKOUT_PCIE_N_7
REFCLK14IN
CLKIN_33MHZLOOPBACK
CLKOUT_PCIE_P_7
PCIECLKRQ7#/GPIO46
XTAL25_IN
XTAL25_OUT
CLKOUT_ITPXDP
CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P
CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0
CLKOUTFLEX2/GPIO66
CLKOUT_33MHZ1
CLKOUTFLEX3/GPIO67
CLKOUT_33MHZ2
ICLK_IREF
CLKOUT_33MHZ3
TP19
TP18
CLKOUT_33MHZ4
DIFFCLK_BIASREF
AB36
CLK_PCIE_VGA
AF6
GFX_CLK_REQ#
CLK_PCIE_VGA#
CLK_PCIE_VGA
if can place closed or not suggest use 8P4R
Y38
RPH3
AF39
PEG_B_CLKRQ# 2
10K_0402_5%
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
AJ39
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
AF35
AF36
CLK_CPU_DPLL#
CLK_CPU_DPLL
AY24
AW24
CLK_BUF_DMI#
CLK_BUF_DMI
AR24
AT24
CLK_BUF_BCLK#
CLK_BUF_BCLK
H33
G33
CLK_BUF_DOT96#
CLK_BUF_DOT96
BE6
BC6
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
F45
D17
CLK_PCH_14M
CLK_PCI_LOOPBACK
AM43
AL44
1
RH130
CLK_BUF_DMI
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_BCLK#
+3.3V_ALW_PCH
CLK_CPU_DMI#
CLK_CPU_DMI
<7>
CLK_CPU_SSC_DPLL# <7>
CLK_CPU_SSC_DPLL <7>
CLK_CPU_DPLL# <7>
CLK_CPU_DPLL <7>
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
RH1501
RH1511
RH1671
RH1691
2
2
2
2
CLK_PCH_14M
RH1461
2 10K_0402_5%
XTAL25_IN
XTAL25_OUT
1
SIO_14MEMC@
EMC@RH157
RH157
2
1 22_0402_5%
F36
CLK_80HEMC@
EMC@RH159
RH159
2
1 22_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
C
CLK_SIO_14M
<50>
CLK_PCI_LPDEBUG
<51>
ICLK_IREF 0_0402_5% 1
2 @ RH163
PAD~D T148 @
PAD~D T147 @
1
PCH_CLK_BIASREF
7.5K_0402_1%
2
RH165
+1.5V_RUN
+1.5V_RUN
2
RH153
F39
AN44
8
7
6
5
CLOCK TERMINATION for FCIM and need close to PCH
F38
AD39
AD38
1
2
3
4
10K_8P4R_5%
<7>
C40
AM45
1
<17>
Y39
U4
S
<17>
2
1M_0402_5%
YH2
25MHZ_10PF_Q22FA2380049900
3
1
OUT
IN
4
2
GND GND
2
1
1
CH14
12P_0402_50V8J
CLK_PCI_DOCK
2
EMC@RH160
EMC@
RH160
CLKOUT_PEG_A_P
PCIECLKRQ0#/GPIO73
CLK_PCIE_VGA#
CH13
12P_0402_50V8J
<48>
EMC@RH158
EMC@
RH158
CLKOUT_PCIE_P_0
AB35
RH152
0_0402_5%
Difference with Diesel
CLKOUT_PEG_A
1
<42>
<42>
CLKOUT_PCIE_N_0
2
G
3.3V_RUN_GFX_ON
2
M.2 card slot 2
Y43
CLK_PCIE_NGFF2#
D
QH3
L2N7002WT1G_SC-70-3
<42>
<44,50,54>
LPT_PCH_M_EDS
UH1C
3
GFX_CLK_REQ#
B
2 OF 11
CLK_PCI_5048
2
@
1
Remove cap
2
CLK_PCI_LPDEBUG
1
Remove cap
2
Remove CLK_PCI_TPM (C40),
JETWAY_CLK14M (F39)
CH83
12P_0402_50V8J
2
1
CLK_SIO_14M
CH79
12P_0402_50V8J
1
CLK_PCI_LOOPBACK
@ CH77
10P_0402_50V8J
2
CLK_PCI_DOCK
CH76
12P_0402_50V8J
2
1
CH16
12P_0402_50V8J
1
CLK_PCI_MEC
CH15
10P_0402_50V8J
PCIECLK REQ Pull UP Power Rail:
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (3/9)
Size
Document Number
Rev
0.1
LA-B541P
Date:
Monday, January 13, 2014
Sheet
1
20
of
67
5
4
3
2
1
2
+3.3V_RUN
6
5
MEM_SMBCLK
1
DDR_XDP_WAN_SMBCLK
<13,14,15,16,18,45>
QH4A
DMN66D0LDW-7_SOT363-6
+3.3V_ALW_PCH
D
D
3
MEM_SMBDATA
DDR_XDP_WAN_SMBDAT
<13,14,15,16,18,45>
QH4B
DMN66D0LDW-7_SOT363-6
+3.3V_RUN
1
RH168
4
2
IRQ_SERIRQ
10K_0402_5%
PCH_SMB_ALERT#
10K_0402_5%
DDR_HVREF_RST_PCH
1K_0402_1%
GPIO74
10K_0402_5%
2
SML1_SMBCLK
SML1_SMBDATA
MEM_SMBCLK
MEM_SMBDATA
1
2
3
4
1
RH166
2
1
2
1
RH170
RH331
RPH5
LPT_PCH_M_EDS
UH1D
<50,51>
LPC_LAD0
LPC_LAD1
<50,51>
LPC_LAD2
<50,51>
LPC_LAD3
<50,51>
LPC_LFRAME#
A20
LPC_LAD1
C20
LPC_LAD2
A18
LPC_LAD3
C18
LPC_LFRAME#
B21
LPC_LDRQ1#
G20
IRQ_SERIRQ
AL11
D21
<50>
<50,51>
LPC_LDRQ1#
IRQ_SERIRQ
SMBALERT#/GPIO11
LAD_0
SMBus
SMBCLK
LAD_1
SMBDATA
LPC
<50,51>
LPC_LAD0
LAD_2
SML0ALERT#/GPIO60
LAD_3
SML0CLK
LFRAME#
SML0DATA
LDRQ0#
SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23
SML1CLK/GPIO58
SERIRQ
SML1DATA/GPIO75
N7
PCH_SMB_ALERT#
R10
MEM_SMBCLK
U11
MEM_SMBDATA
N8
DDR_HVREF_RST_PCH
U8
LAN_SMBCLK
R7
LAN_SMBDATA
H6
2.2K_0804_8P4R_5%
Intel request.
DDR_HVREF_RST_PCH
LAN_SMBCLK
K6
SML1_SMBCLK
N11
SML1_SMBDATA
AF11
PCH_CL_CLK1
AF10
PCH_CL_DATA1
AF7
PCH_CL_RST1#
<13,15,7>
LAN_SMBCLK
499_0402_1%
2
1 RH174
LAN_SMBDATA
499_0402_1%
2
1 RH175
<39>
LAN_SMBDATA
GPIO74
8
7
6
5
PU to always power
<39>
Remove TEMP_ALERT#.
SML1_SMBCLK <51>
SML1_SMBDATA <51>
C
C
PCH_SPI_DIN
AJ7
PCH_SPI_CS1#
AL7
PCH_SPI_CS2#
AJ10
AH1
PCH_SPI_DO
AH3
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
AJ4
AJ2
CL_DATA
C-Link
SPI_CS0#
CL_RST#
PCH_CL_CLK1
<42>
PCH_CL_DATA1
<42>
PCH_CL_RST1#
<42>
SPI_CS1#
SPI_CS2#
TP1
SPI_MOSI
TP2
Thermal
SPI_MISO
TP4
SPI_IO2
TP3
SPI_IO3
TD_IREF
BA45
PAD~D
T149 @
BC45
PAD~D
T150 @
BE43
PAD~D
T120 @
BE44
PAD~D
T121 @
SPI_CLK32
AY43
PCH_TD_IREF 1
RH176
SPI_CLK64
1
<41>
PCH_SPI_CS0#
CL_CLK
SPI_CLK
@
RE2
33_0402_5%
2
8.2K_0402_1%
1
3 OF 11
2
+3.3V_SPI
1
R3664
1
R3668
2 SPI_PCH_DO2_64
1K_0402_5%
2 SPI_PCH_DO3_64
1K_0402_5%
@
RE1
33_0402_5%
2
PCH_SPI_CS2#
PCH_SPI_DO
AJ11
SPI
<41>
<41>
PCH_SPI_CLK
1
PCH_SPI_CLK
2
<41>
1
@
CE2
27P_0402_50V8J
2
@
CE1
27P_0402_50V8J
+3.3V_SPI
200 MIL SO8
1
64Mb Flash ROM
B
C746
2
B
0.1U_0402_25V6K
JSPI1
U52
SPI_PCH_CS0# R7
SPI_PCH_DIN R8
SPI_PCH_DO2 R9
1
1
1
2 47_0402_5%
2 33_0402_5%
2 33_0402_5%
SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64
1
2
3
4
/CS
DO(IO1)
/WP(IO2)
GND
VCC
/HOLD(IO3)
CLK
DI(IO0)
8
7
6
5
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
SPI_PCH_DO3
SPI_PCH_CLK
SPI_PCH_DO
1
2
1
RH177
0_0402_5%
RH178
2
1
2
1
2
1
2
1
2
1
0_0402_5%
W25Q64FVSSIQ_SO8
remove SPI_WP#_SEL
2
0_0402_5%
SPI_PCH_DO3_64 R3669 1
SPI_CLK64 EMC@
EMC@R899
R899 1
SPI_DO64
R901 1
RH179
0_0402_5%
CIS LINK OK
RH181
0_0402_5%
+3.3V_SPI
RH182
0_0402_5%
RH183
0_0402_5%
1
R3665
1
R3666
2 SPI_PCH_DO2_32
1K_0402_5%
2 SPI_PCH_DO3_32
1K_0402_5%
RH184
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
SPI_PCH_CS0#
PCH_SPI_CS0#
SPI_PCH_DO2
PCH_SPI_DO2
SPI_PCH_DO3
PCH_SPI_DO3
+3.3V_SPI
+3.3V_M
+3.3V_SPI
200 MIL SO8
32Mb Flash ROM
1
2
RH185
C1216
2
1
0_0402_5%
21
22
0.1U_0402_25V6K
U53
SPI_PCH_CS1#
SPI_PCH_DIN
SPI_PCH_DO2
R936 1
R895 1
R3667 1
2 47_0402_5%
2 33_0402_5%
2 33_0402_5%
remove SPI_WP#_SEL
A
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
1
2
3
4
/CS
DO/IO1
/WP/IO2
GND
VCC
/HOLD/IO3
CLK
DI/IO0
8
7
6
5
SPI_PCH_DO3_32 R3670 1
SPI_CLK32 EMC@
EMC@R897
R897 1
SPI_DO32
R900 1
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
SPI_PCH_DO3
SPI_PCH_CLK
SPI_PCH_DO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND1
GND2
E-T_6712K-Y20N-07L
CONN@
CIS link OK
W25Q32FVSSIQ_SO8
A
CIS LINK OK
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (4/9)
Size
Document Number
Rev
0.1
LA-B541P
Date:
Monday, January 13, 2014
Sheet
1
21
of
67
5
4
3
2
1
D
D
USB3TN3
USB3TP3
AW31
AY31
USB3TN3
USB3TP3
BE32
BC32
AT31
AR31
BD33
BB33
<39>
<39>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
10/100/1G LAN
C
<39>
<39>
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
<49>
<49>
PCIE_PRX_MMITX_N4
PCIE_PRX_MMITX_P4
MMI
PCIE_PTX_MMIRX_N4
PCIE_PTX_MMIRX_P4
<32>
<32>
PCIE_PRX_TBTX_N5
PCIE_PRX_TBTX_P5
<32>
<32>
TBT-2
WLAN
WIGIG
PCIE_PTX_TBRX_N5
PCIE_PTX_TBRX_P5
PCIE_PRX_TBTX_N6
PCIE_PRX_TBTX_P6
<32>
<32>
PCIE_PTX_TBRX_N6
PCIE_PTX_TBRX_P6
<42>
<42>
PCIE_PRX_WLANTX_N7
PCIE_PRX_WLANTX_P7
<42>
<42>
PCIE_PTX_WLANRX_N7
PCIE_PTX_WLANRX_P7
<42>
<42>
PCIE_PRX_WIGIGTX_N8
PCIE_PRX_WIGIGTX_P8
<42>
<42>
PCIE_PTX_WIGIGRX_N8
PCIE_PTX_WIGIGRX_P8
+1.5V_RUN
BE34
BC34
PCIE_PRX_MMITX_N4
PCIE_PRX_MMITX_P4
AT33
AR33
PCIE_PTX_MMIRX_N4
PCIE_PTX_MMIRX_P4
BE36
BC36
PCIE_PRX_TBTX_N5
PCIE_PRX_TBTX_P5
AW36
AV36
PCIE_PTX_TBRX_N5
PCIE_PTX_TBRX_P5
BD37
BB37
PCIE_PRX_TBTX_N6
PCIE_PRX_TBTX_P6
AY38
AW38
PCIE_PTX_TBRX_N6
PCIE_PTX_TBRX_P6
BC38
BE38
PCIE_PRX_WLANTX_N7
PCIE_PRX_WLANTX_P7
AT40
AT39
PCIE_PTX_WLANRX_N7
PCIE_PTX_WLANRX_P7
BE40
BC40
PCIE_PRX_WIGIGTX_N8
PCIE_PRX_WIGIGTX_P8
AN38
AN39
PCIE_PTX_WIGIGRX_N8
PCIE_PTX_WIGIGRX_P8
BD42
BD41
1
2
@ RH188
PCH_PCIE_IREF
0_0402_5%
BE30
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
USBRBIAS#
USBRBIAS
PCIE_IREF
TP24
TP23
B
@ T124
@ T125
+1.5V_RUN
1
RH192
PAD~D
PAD~D
2
BC30
BB29
PCH_PCIE_RCOMP BD29
7.5K_0402_1%
TP11
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
TP6
PCIE_RCOMP
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
K24
K26
USBRBIAS
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
<49>
<49>
<47>
<47>
<49>
<49>
<48>
<48>
<42>
<42>
<42>
<42>
<48>
<48>
<41>
<41>
<30>
<30>
<49>
<49>
<43>
<43>
<30>
<30>
----->Left Side JUSB3
----->Right Side
----->Left Side JUSB1
----->MLK DOCK
----->M.2 Slot-1 (WLAN/BT/WiGig)
----->M.2 Slot-2 (WWAN/LTE/HCA)
----->MLK DOCK
----->USH
----->Camera
----->Left Side JUSB2
----->M.2 Slot-3 (SSD/HCA/Cache)
----->Touch Screen
C
USBRBIAS
M33
L33
P3 USB_OC0#_R
V1 USB_OC1#_R
U2 USB_OC2#
P1 USB_OC3#
M3 USB_OC4#_R
T1 USB_OC5#
N2 USB_OC6#
M1 SIO_EXT_SMI#
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
PAD~D
PAD~D
<49>
<49>
<49>
<49>
<47>
<47>
<47>
<47>
<49>
<49>
<49>
<49>
<49>
<49>
<49>
<49>
----->Left Side JUSB3
RH187
22.6_0402_1%
<32>
<32>
AW33
AY33
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
PETN1/USB3TN3
PETP1/USB3TP3
PCIe
TBT-1
<49>
<49>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
LPT_PCH_M_EDS
PERN1/USB3RN3
PERP1/USB3RP3
1
<48>
<48>
USB3RN3
USB3RP3
USB
MLK DOCK
USB3RN3
USB3RP3
2
UH1I
<48>
<48>
----->Right Side
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
----->Left Side JUSB1
----->Left Side JUSB2
T122 @
T123 @
+3.3V_ALW_PCH
@ RH189
@ RH190
1
1
2 0_0402_5%
2 0_0402_5%
@ RH191
1
2 0_0402_5%
9 OF 11
USB_OC0# <47>
USB_OC1# <49>
USB_OC2# <18,49>
USB_OC3# <18>
USB_OC4# <49>
USB_OC5# <18>
USB_OC6# <18>
SIO_EXT_SMI# <18,51>
USB_OC0#_R
USB_OC1#_R
USB_OC4#_R
1
2
3
4
USB_OC1#_R
USB_OC2#
USB_OC5#
USB_OC0#_R
B
RPH6 PN change to SD30910020L
8
7
6
5
10K_8P4R_5%
<18>
<18>
<18>
1
2
3
4
USB_OC3#
USB_OC6#
SIO_EXT_SMI#
USB_OC4#_R
RPH7 PN change to SD30910020L
8
7
6
5
10K_8P4R_5%
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (5/9)
Size
Document Number
Rev
0.1
LA-B541P
Date:
Monday, January 13, 2014
Sheet
1
22
of
67
5
4
+PCH_VCCDSW3_3
3
1
2
1
2
1
2
1
RH217
LAN_WAKE#
10K_0402_5%
PM_LANPHY_ENABLE
10K_0402_5%
+3.3V_RUN
LPT_PCH_M_EDS
UH1F
RH208
RH214
PCH_GPIO35
10K_0402_5%
TPM_PIRQ#
10K_0402_5%
<51>
for TBT GPIO pin
difference with Diesel
1
2
RH200
TPM_ID1
20K_0402_5%
RPH8
1
2
3
4
8
7
6
5
10K_8P4R_5%
RPH9
1
8
2
7
3
6
4
5
10K_8P4R_5%
RPH10
1
8
2
7
3
6
4
5
<32>
Remove TBT_CIO_PLUG_EVENT#,
due to double PU.
<18,51>
SIO_EXT_WAKE#
2
1
2
1
RH212
2
1
RH213
SIO_EXT_WAKE#
10K_0402_5%
2
0_0402_5%
AT8
TBT_CIO_PLUG_EVENT#
A14
MXM_PRESENTL#
G15
SIO_EXT_WAKE#
Y1
PM_LANPHY_ENABLE
TBT_FORCE_PWR
SATA4_PCIE1#
<17,50>
TPM_ID0
SIO_RCIN#
SIO_EXT_SCI#
PCH_GPIO34
1
@RH195
@
RH195
USH_DET#
PM_LANPHY_ENABLE
<32>
for TBT GPIO pin <18,50>
MXM_PRESENTR#
USH_DET#
PCH_GPIO71
USH_DET#
MXM_PRESENTL#
TBT_FORCE_PWR
SATA4_PCIE1#
TPM_PIRQ#
TPM_PIRQ#
PCH_GPIO24
change from EC wake# to
<39,51> LAN_WAKE#
LAN_wake#
Remove SLP_ME_CSW_DEV#
<18>
PCH_GPIO35
<18>
PCH_GPIO36
<18,45>
HDD2_DET#
difference with Diesel
KB_DET#
10K_0402_5%
PCH_GPIO24
10K_0402_5%
<45>
<18,51>
SSD_SATA5_PCIE2#
<53>
<41>
FFS_INT2
KB_DET#
CONTACTLESS_DET#
<17>
MXM_PRESENTR#
1
@RH219
@
RH219
F13
K13
AB11
AN2
C14
DGPU_PWROK
<41>
10K_8P4R_5%
RH210
<41>
<17>
<39>
CONTACTLESS_DET#
MXM_PRESENTL#
PCH_GPIO69
SIO_EXT_SCI#
TBT_CIO_PLUG_EVENT#
+3.3V_ALW_PCH
C
1
Support Deep S3 mode
2
RH216
D
2
BB4
Y10
R11
AD11
PCH_GPIO34
AN6
PCH_GPIO35
AP1
PCH_GPIO36
AT3
HDD2_DET#
AK1
TPM_ID0
AT7
TPM_ID1
AM3
FFS_INT2
AN4
SSD_SATA5_PCIE2#
AK3
KB_DET#
U12
CONTACTLESS_DET#
C16
PCH_GPIO69
D13
MXM_PRESENTR#
G13
PCH_GPIO71
H15
2 TP_VSS_NCTF
0_0402_5%
BE41
BE5
C45
A5
BMBUSY#/GPIO0
TACH1/GPIO1
Remove 56 ohm from PCH_AV1
TACH2/GPIO6
HSW
BDW
X
V
D
CPU/Misc
TACH3/GPIO7
GPIO8
RH206
Remove SIO_A20GATE
LAN_PHY_PWR_CTRL/GPIO12
TP14
GPIO15
PECI
SATA4GP/GPIO16
GPIO
RCIN#
TACH0/GPIO17
PROCPWRGD
SCLOCK/GPIO22
THRMTRIP#
GPIO24
PLTRST_PROC#
GPIO27
VSS
AN10
+1.05V_RUN
AY1
PAD~D
T126 @
BDW@RH206
RH206 1
H_THERMTRIP#_PCH BDW@
AT6
SIO_RCIN#
AV3
H_CPUPWRGD
SIO_RCIN#
AV1H_THERMTRIP#_PCHRH172
AU4
CPU_PLTRST#
<51>
H_CPUPWRGD
1
HSW_BDW compatibility CKT
<7>
2 390_0402_5%
CPU_PLTRST#
2 1K_0402_1%~D
H_THERMTRIP#
H_THERMTRIP#
<51,7>
<7>
N10
GPIO28
GPIO34
Remove 0.1uF cap from PCH_AV1
GPIO35/NMI#
SATA2GP/GPIO36
SATA3GP/GPIO37
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
VSS
VSS
VSS
VSS
NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
C
6 OF 11
Remove SLP_ME_CSW_DEV#
+3.3V_RUN
1
2
2
1
2
1
2
1
SATA4_PCIE1#
10K_0402_5%
HDD2_DET#
10K_0402_5%
RH224
RH225
PLL ON DIE VR ENABLE
B
SATA4_PCIE1#
10K_0402_5%
HDD2_DET#
10K_0402_5%
@RH226
@
RH226
ENABLED - HIGH(DEFAULT)
DISABLED - LOW
@RH227
@
RH227
B
+3.3V_RUN
2
1
2
1
2
1
2
1
@RH228
@
RH228
RH229
RH230
Note: GPIO strap option is only
available for SATA/PCIE muxed
signals to support
mSATA/mini PCIE port switching
GPIO16
GPIO49
0: PCIE1
0: PCIE2
1: SATA4
1: SATA5
@RH231
@
RH231
00b or 01b: Assign muxed signal to desired port
10b: Reserved
11b: Assign desired port based on GPIO
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
Muxed
Muxed
Signals Fixed Signals
Signals Fixed Signals
USB3 USB3 USB3 USB3 PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE SATA SATA SATA SATA SATA SATA
1
2
5
6
1
2
3
4
5
6
7
8
4
5
0
1
2
3
(00) (00)
(00) (00)
Fixed Signals
A
USB3 USB3
3
4
(01) (01)
A
PCIE PCIE
1
2
(01) (01)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
PCH_GPIO36
1K_0402_1%
SSD_SATA5_PCIE2#
1K_0402_1%
PCH_GPIO36
10K_0402_5%
SSD_SATA5_PCIE2#
10K_0402_5%
4
3
2
Compal Electronics, Inc.
Title
PCH (6/9)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
23
of
67
5
4
3
2
LH1
2
1
BLM18PG181SN1D_2P
+VCCADAC
+1.05V_RUN
VCCADAC1_5
2
@
CRT DAC
VCCADACBG3_3
VCCVRM
FDI
VCCIO
VCCIO
HVCMOS
VCCSUS3_3
VCCSUS3_3
USB3
VCCVRM
VCCIO
VCCVRM
SATA
VCCIO
VCCMPHY
+3.3V_RUN
1
BB44
1
AN34
+3.3V_RUN
AN35
2
R30
R32
Y12
+PCH_USB_DCPSUS1
AJ26
AJ28
AK20
AK26
AK28
2
+PCH_USB_DCPSUS3
2
+1.5V_RUN
+1.05V_RUN
+1.5V_RUN
1
BE22
AK18
+1.5V_RUN
+1.05V_RUN
1
AN11
AK22
1
+1.05V_RUN
AM18
AM20
AM22
AP22
AR22
AT22
2
1
2
1
2
1
2
1
2
CH38
10U_0603_6.3V6M
2
CH37
1U_0402_6.3VAK
1
CH36
1U_0402_6.3VAK
+PCH_VCCDSW_R
+3.3V_ALW_PCH
CH35
1U_0402_6.3VAK
B
2
1
AJ30
AJ32
7 OF 11
1
RH232
+1.05V_RUN
CH34
1U_0402_6.3VAK
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
M31
2
2
@ CH31
10U_0603_6.3VAM
PCIe/DMI
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
Voltage Rail
+1.5V_RUN
Voltage
S0 Iccmax Current (A)
P43
@ CH33
10U_0603_6.3VAM
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
P45
@ CH32
10U_0603_6.3VAM
2
VCC3_3_R30
VCC3_3_R32
DCPSUS1
Core
2
1
CH30
1U_0402_6.3VAK
1
CH29
1U_0402_6.3VAK
2
CH28
22U_0805_6.3VAM
1
+PCH_VCCDSW U14
AA18
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
VSS
CH27
0.1U_0402_10V7K
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
+1.05V_M
C
PCH Power Rail Table
@CH26
@
CH26
10U_0603_6.3VAM
+
D
CH25
1U_0402_6.3VAK
2
1
CH60
330U_SX_2VY
2
1
CH24
1U_0402_6.3VAK
2
1
CH23
1U_0402_6.3VAK
1
CH22
1U_0402_6.3VAK
2
CH21
10U_0603_6.3VAM
1
2
+1.5V_RUN
LPT_PCH_M_EDS
UH1G
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
Y26
2
1
CH20
10U_0603_6.3VAM
2
1
CH19
0.1U_0402_10V7K
1
CH18
0.01U_0402_16V7K
D
1
+PCH_VCCDSW
5.11_0402_1%
VCC
1.05V
VCCIO
1.05V
1.29 A
3.629 A
VCCADAC1_5
1.5V
0.070 A
VCCADAC3_3
3.3V
0.0133 A
VCCCLK
1.05V
0.306 A
VCCCLK3_3
3.3V
0.055 A
VCCVRM
1.5V
0.179 A
VCC3_3
3.3V
0.133 A
VCCASW
1.05V
0.67 A
VCCSUSHDA
3.3V
0.01 A
VCCSPI
3.3V
0.022 A
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
1.05V
0.004 A
C
+1.05V_M
+PCH_USB_DCPSUS1
0_0402_5%
2
1
RH234 @
B
2
2
CH40
1U_0402_6.3VAK
1
@CH39
@
CH39
1U_0402_6.3VAK
1
2
1
2
+1.05V_M
1
2
RH236 @
@ CH42
1U_0402_6.3VAK
1
@ CH41
10U_0603_6.3VAM
+PCH_USB_DCPSUS3
0_0603_5%
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (7/9)
Size
Document Number
Rev
0.1
LA-B541P
Date:
Monday, January 13, 2014
Sheet
1
24
of
67
5
4
3
2
1
Support DEEP SX: populated RH238/RH246, de-populated RH237/RH240
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
1
+1.05V_RUN
M24
U35
L24
+1.05V_RUN
M29
L29
L26
M26
U32
V32
AA30
AA32
AD35
AG30
AG32
+1.05V_RUN_VCC
2
0_0603_5%
1
2
+PCH_VCC
4.7UH_LQM18FN4R7M00D_20%
1
2
1
+1.05V_RUN
Azalia
VCCSUSHDA
A26
1
VCCVRM
VCC
VCCSUS3_3
VCCCLK
VCCRTC
RTC
VCCCLK3_3
DCPRTC
DCPRTC
K8
P14
P16
+PCH_DCPRTC
CH54
1
2
1
0.1U_0402_10V7K
VCCCLK3_3
VCCCLK3_3
V_PROC_IO
V_PROC_IO
CPU
VCCCLK3_3
VCCCLK3_3
VCCSPI
SPI
VCCCLK
VCC
VCC
VCCCLK
VCCCLK
VCCASW
VCCCLK
VCCASW
VCCCLK
VCCCLK
VCCVRM
VCCCLK
VCC3_3
Thermal
VCCCLK
VCCCLK
VCC3_3
+RTC_CELL
+3.3V_VCCPRTCSUS
2
A6
VCCCLK3_3
CH64
1U_0402_6.3V6K
2
CH63
10U_0603_6.3V6M
1
U36
AJ12
AJ14
+VCCIO2PCH
2
+3.3V_M
1
2
1
2
AD12
P18
P20
1
+PCH_VCCCFUSE
L17
2
+1.05V_M
R18
+VCCIO2PCH
AW40
+1.5V_RUN
+3.3V_RUN
AK30
1
AK32
1
8 OF 11
2
CH65
0.1U_0402_10V7K
1
@ RH241
Voltage Rail
+3.3V_ALW_PCH
2
DCPSUS2
PCH Power Rail Table
+3.3V_RUN
2
0.1U_0402_10V7K
AE14
AF12
AG14
2
1
2
CH81
1U_0402_6.3VAK
AE30
AE32
LH2
VCCIO
1
+PCH_VCCSST
CH46
D
CH82
0.1U_0402_10V7K
+1.05V_RUN
AD36
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCIO
VCCIO
VCCIO
AA14
+3.3V_ALW
CH59
1U_0402_6.3VAK
AD34
+PCH_VCCCLK
VCC3_3
+PCH_VCCDSW3_3
+3.3V_ALW_PCH
CH57
1U_0402_6.3V6K
+PCH_VCCCLK3_3
DCPSST
VCCUSBPLL
ICC
2
C
Y32
@ CH58
1U_0402_6.3VAK
1
+PCH_VCCCLK
VCCDSW3_3
VSS
A16
CH56
0.1U_0402_10V7K
2
+PCH_USB_DCPSUS2
0_0402_5%
AP45
+PCH_VCC
2
GPIO/LPC
CH55
0.1U_0402_10V7K
2
1
Y35
AF34
1
+1.05V_M
@ RH239
+PCH_USB_DCPSUS2
+1.5V_RUN
CH52
10U_0603_6.3V6M
2
CH50
1U_0402_6.3VAK
1
2
1
CH51
0.1U_0402_10V7K
2
U30
V28
V30
Y30
VCCSUS3_3
VCCSUS3_3
R20
R22
1
@ RH237
1
@ RH238
2
0_0603_5%
CH49
0.1U_0402_10V7K
1
CH48
0.1U_0402_10V7K
2
+3.3V_RUN
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
USB
1
CH47
0.1U_0402_10V7K
2
CH45
0.1U_0402_10V7K
D
R24
R26
R28
U26
2
0_0603_5%
CH44
0.1U_0402_10V7K
1
+3.3V_ALW_PCH
CH43
0.1U_0402_10V7K
LPT_PCH_M_EDS
UH1H
Voltage
S0 Iccmax Current (A)
VCC
1.05V
VCCIO
1.05V
1.29 A
3.629 A
VCCADAC1_5
1.5V
0.070 A
VCCADAC3_3
3.3V
0.0133 A
VCCCLK
1.05V
0.306 A
VCCCLK3_3
3.3V
0.055 A
VCCVRM
1.5V
0.179 A
VCC3_3
3.3V
0.133 A
VCCASW
1.05V
0.67 A
VCCSUSHDA
3.3V
0.01 A
0.022 A
VCCSPI
3.3V
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
1.05V
0.004 A
C
Place near pin AP45
2
+PCH_VCCCFUSE
+1.05V_RUN
+PCH_VCCCLK
1
@ RH242
1
@ RH243
0_0805_5%
2
2
@ RH244
1
0_0805_5%
Place near pin AD34
2
1
2
CH71
1U_0402_6.3VAK
Place near pin Y32,AA30,AA32
2
1
CH70
1U_0402_6.3VAK
2
1
CH69
1U_0402_6.3VAK
1
@ CH68
1U_0402_6.3VAK
2
CH67
1U_0402_6.3VAK
1
B
2
CH66
1U_0402_6.3VAK
1
0_0805_5%
+3.3V_RUN
+1.05V_RUN
B
Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
2
+3.3V_VCCPRTCSUS
0_0603_5%
2
+PCH_VCCCLK3_3
1
1
2
0_0805_5%
RH245
2
Place near pin L29
2
Place near pin L26,M26
1
2
0_0603_5%
1
@ RH240
1
@RH246
@
RH246
+3.3V_ALW_PCH
+3.3V_ALW
CH75
1U_0402_6.3VAK
2
1
CH74
1U_0402_6.3VAK
Place near pin M29
1
CH73
1U_0402_6.3VAK
2
CH72
1U_0402_6.3VAK
1
CH53
1U_0402_6.3VAK
+3.3V_RUN
Place near pin U32,V32
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (8/9)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
25
of
67
5
4
3
2
1
D
D
UH1J
AL34
AL38
AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36
AN40
AN42
AN8
AP13
AP24
AP31
AP43
AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
D42
AV13
AV22
AV24
AV31
AV33
BB25
AV40
AV6
AW2
F43
AY10
AY15
AY20
AY26
AY29
AY7
B11
B15
C
B
LPT_PCH_M_EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8
UH1K
AA16
AA20
AA22
AA28
AA4
AB12
AB34
AB38
AB8
AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AD6
AD8
AE16
AE28
AF38
AF8
AG16
AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AJ6
AJ8
AK14
AK24
AK43
AK45
AL12
AL2
BC22
BB42
10 OF 11
LPT_PCH_M_EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
C
B
11 OF 11
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
PCH (9/9)
Size
Document Number
Rev
0.1
LA-B541P
Date:
Monday, January 13, 2014
Sheet
1
26
of
67
5
4
3
2
1
D
D
Difference with Diesel
CPU FAN
JFAN1
<51> FAN1_PWM
<51> FAN1_TACH_FB
+5V_RUN
C
FAN1_PWM
FAN1_TACH_FB
1
2
C364
0.1U_0402_25V6K
2
C329
10U_0805_10V6K
1
1
2
3
4
5
6
1
2
3
4
C
+3.3V_RUN
GND1
GND2
ACES_50271-0040N-001
CONN@
Link CIS OK
FAN2_PWM_D
10K_0402_5%
FAN1_PWM
10K_0402_5%
FAN2_PWM
10K_0402_5%
FAN2_TACH_FB
10K_0402_5%
FAN1_TACH_FB
10K_0402_5%
2
1
2
1
2
1
R403
R407
@ R409
2
1
2
1
R405
R408
MXM FAN
@ R213 2
1 0_0603_5%
JFAN2
D90
<51>
FAN2_PWM
1
2
RB751S40T1_SOD523-2
<51>
FAN2_PWM_D
FAN2_TACH_FB
FAN2_TACH_FB
+5V_RUN
C330 change to 0603
due to height limitation.
1
2
1
2
C370
0.1U_0402_25V6K
C330
10U_0603_6.3V6M
B
1
2
3
4
5
6
1
2
3
4
GND1
GND2
B
ACES_50271-0040N-001
CONN@
Link CIS OK
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
FAN control
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size
4
3
Rev
0.1
LA-B541P
Date:
5
Document Number
2
Monday, January 13, 2014
Sheet
1
27
of
67
5
4
3
2
1
D
D
Remove current sensor Monitor (SW solution)
C
C
B
B
Remove current sensor Monitor (HW solution)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Current Sensor
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
28
of
67
5
4
3
2
1
+3.3V_RUN
C561
C563
C565
C567
1
1
1
1
2
2
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
CPU_EDP_LANE_P0_C
CPU_EDP_LANE_N0_C
CPU_EDP_LANE_P1_C
CPU_EDP_LANE_N1_C
1
2
4
5
6
7
9
10
CPU
<9>
<9>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
C
MXM
<17>
<17>
CPU_EDP_AUX
CPU_EDP_AUX#
MXM_EDP_LANE_P0
MXM_EDP_LANE_N0
MXM_EDP_LANE_P1
MXM_EDP_LANE_N1
MXM_EDP_LANE_P2
MXM_EDP_LANE_N2
MXM_EDP_LANE_P3
MXM_EDP_LANE_N3
MXM_EDP_AUX
MXM_EDP_AUX#
CPU_EDP_AUX
CPU_EDP_AUX#
C558
C555
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
CPU_EDP_AUX_C
CPU_EDP_AUX#_C
28
27
23
22
MXM_EDP_LANE_P0
MXM_EDP_LANE_N0
MXM_EDP_LANE_P1
MXM_EDP_LANE_N1
MXM_EDP_LANE_P2
MXM_EDP_LANE_N2
MXM_EDP_LANE_P3
MXM_EDP_LANE_N3
C549
C537
C557
C556
C560
C559
C564
C562
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
MXM_EDP_LANE_P0_C
MXM_EDP_LANE_N0_C
MXM_EDP_LANE_P1_C
MXM_EDP_LANE_N1_C
MXM_EDP_LANE_P2_C
MXM_EDP_LANE_N2_C
MXM_EDP_LANE_P3_C
MXM_EDP_LANE_N3_C
11
12
14
15
16
17
19
20
C566
C568
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_EDP_AUX_C
MXM_EDP_AUX#_C
30
29
25
24
MXM_EDP_AUX
MXM_EDP_AUX#
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
<9> CPU_EDP_HPD
<17> MXM_EDP_HPD
CPU_EDP_HPD
MXM_EDP_HPD
3
13
IN2_PEQ/SCL_CTL
IN1_PEQ/SDA_CTL
IN1_AEQ#
IN2_AEQ#
I2C_CTL_EN
PI0
PC0
PC1
IN1_D0p
IN1_D0n
IN1_D1p
IN1_D1n
IN1_D2p
IN1_D2n
IN1_D3p
IN1_D3n
CA_DET
OUT_D0p
OUT_D0n
OUT_D1p
OUT_D1n
OUT2_D2p
OUT2_D2n
OUT_D3p
OUT_D3n
IN1_AUXp
IN1_AUXn
IN1_SCL
IN1_SDA
IN2_D0p
IN2_D0n
IN2_D1p
IN2_D1n
IN2_D2p
IN2_D2n
IN2_D3p
IN2_D3n
32
31
LCD_EDP_AUX
LCD_EDP_AUX#
LCD_EDP_AUX <30>
LCD_EDP_AUX# <30>
2 4.7K_0402_5%
EDP_IN1_AEQ# @ R140 1
2 4.7K_0402_5%
EDP_IN2_AEQ# @ R142 1
2 4.7K_0402_5%
EDP_IN1_PEQ @ R127 1
2 4.7K_0402_5%
EDP_IN2_PEQ @ R133 1
2 4.7K_0402_5%
D
2 4.7K_0402_5%
53
MUX_CET
56
38
55
EDP_MUX_PI0
EDP_MUX_PC0
EDP_MUX_PC1
48
1
R3722
46
45
43
42
40
39
37
36
2
2
C98
1 2.2U_0402_6.3V6M
EDP_MUX_PI0 @ R139 1
2 4.7K_0402_5%
EDP_MUX_PC0 @ R136 1
2 4.7K_0402_5%
EDP_MUX_PC1 @ R141 1
2 4.7K_0402_5%
EDP_IN1_PEQ @ R137 1
2 4.7K_0402_5%
EDP_IN2_PEQ @ R138 1
2 4.7K_0402_5%
1M_0402_5%
LCD_EDP_LANE_P0
LCD_EDP_LANE_N0
LCD_EDP_LANE_P1
LCD_EDP_LANE_N1
LCD_EDP_LANE_P2
LCD_EDP_LANE_N2
LCD_EDP_LANE_P3
LCD_EDP_LANE_N3
LCD_EDP_LANE_P0
LCD_EDP_LANE_N0
LCD_EDP_LANE_P1
LCD_EDP_LANE_N1
LCD_EDP_LANE_P2
LCD_EDP_LANE_N2
LCD_EDP_LANE_P3
LCD_EDP_LANE_N3
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
eDP Conn
C
SW
OUT_HPD
REXT
CEXT
IN2_AUXp
IN2_AUXn
IN2_SCL
IN2_SDA
GND
GND
GND
GND
GND
Epad
PD
IN1_HPD
IN2_HPD
54
DGPU_SELECT
44
LCD_EDP_HPD
34
47
8
18
33
41
57
61
50
MUX_REXT
MUX_CET
@ RV46 1
LCD_EDP_HPD
2 0_0402_5%
DGPU_SELECT#
<30,35,50>
<30>
R101
4.99K_0402_1%
+3.3V_RUN
2
DGPU_SELECT#
DGPU_SELECT
D
S
2
G
INy_AEQ# = Automatic EQ disable
L: Automatic EQ enable (default)
H: Automatic EQ disable
PI0 = Auto test enable
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
QV1
DMN65D8LW-7_SOT323-3
INy_PEQ = Programmable input equalization levels
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
RV48
8.2K_0402_5%
1
+3.3V_RUN
RV47
10K_0402_5%
PS8331BQFN60GTR-A0_QFN60_5X9
B
EDP_MUX_PC1 @ R109 1
EDP_MUX_PI0 @ R143 1
1
CPU_EDP_LANE_P0
CPU_EDP_LANE_N0
CPU_EDP_LANE_P1
CPU_EDP_LANE_N1
OUT_AUXp_SCL
OUT_AUXn_SDA
2
CPU_EDP_LANE_P0
CPU_EDP_LANE_N0
CPU_EDP_LANE_P1
CPU_EDP_LANE_N1
51
52
59
58
VDD33
VDD33
VDD33
VDD33
VDD33
1
<9>
<9>
<9>
<9>
EDP_IN2_PEQ
EDP_IN1_PEQ
EDP_IN1_AEQ#
EDP_IN2_AEQ#
CIS LINK OK
3
U630
21
26
35
49
60
2 4.7K_0402_5%
2
2
+3.3V_RUN
EDP_MUX_PC0 @ R100 1
1
2
1
C502
0.1U_0402_16V4Z
2
1
C554
0.1U_0402_16V4Z
2
1
C501
0.1U_0402_16V4Z
D
1
C500
0.1U_0402_16V4Z
2
C784
4.7U_0603_6.3V6K
1
B
for DP Lane bus layout routing smoothly.
PC0 = AUX interception disable
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
PC1 = Output swing adjustment
L: default
H: +20%
M: -16.7%
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
eDP MUX (PS8331)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
29
of
67
5
4
3
2
1
40mil
+LCDVDD
Q21
FDC654P-G_SSOT-6
+PWR_SRC
3
DMIC0
DOCK_LCD_SMBCLK
<48,51>
2
5
DOCK_LCD_SMBDAT_Q 4
PESD5V0U2BT_SOT23-3
<49>
3
DOCK_LCD_SMBDAT
2
1
PWR_SRC_ON
<48,51>
1
R423
USBP8_DUSBP8_D+
<19>
<51>
LCD_EDP_LANE_N3_C
LCD_EDP_LANE_P3_C
LCD_EDP_LANE_N2_C
LCD_EDP_LANE_P2_C
LCD_EDP_LANE_N1_C
LCD_EDP_LANE_P1_C
LCD_EDP_LANE_N0_C
LCD_EDP_LANE_P0_C
DOCK_LCD_SMBCLK_Q
DOCK_LCD_SMBDAT_Q
1 C371
0.1U_0402_10V6K 2
1 C373
0.1U_0402_10V6K 2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2
2
2
2
2
2
2
2
1 C374
1 C372
1 C376
1 C375
1 C378
1 C377
1 C380
1 C379
3
LCD_EDP_AUX
LCD_EDP_AUX#
<29>
<29>
LCD_EDP_LANE_N3
LCD_EDP_LANE_P3
LCD_EDP_LANE_N2
LCD_EDP_LANE_P2
LCD_EDP_LANE_N1
LCD_EDP_LANE_P1
LCD_EDP_LANE_N0
LCD_EDP_LANE_P0
1
2
PANEL_BKEN_PCH
<19>
MXM_PANEL_BKEN
<17>
EN_INVPWR
Panel backlight power control by EC
Difference with Diesel
Daisy Chain with Docking SMBus
LCD_TST <50>
LCD_EDP_HPD
<29>
LCD_EDP_AUX_C
LCD_EDP_AUX#_C
1
<19>
D65
RB751VM-40TE-17_SOD323-2
<29>
<29>
<29>
<29>
<29>
<29>
<29>
<29>
+3.3V_ALW
D64
1
DISP_ON
1
LCD_CBL_DET#
2
47K_0402_5%
2
G
CAM_MIC_CBL_DET#
1 0_0603_5% BIA_PWM
D
Q22
DMN65D8LW-7_SOT323-3
QV2B @
DMN66D0LDW-7_SOT363-6
<49>
R208 @EMC@2
DISP_ON
1
3
6
QV2A @
DMN66D0LDW-7_SOT363-6
D
+CAMERA_VDD
+3.3V_RUN
DMIC_CLK
1
DOCK_LCD_SMBCLK_Q
1
2
2
2
DMIC0
C296
0.1U_0603_50V7K
DMIC_CLK
40mil
G
D22 change to H: 1.1mm
due to height limitation.
@EMC@
D22
+LCDVDD
1
S
D
Close to JEDP1
+BL_PWR_SRC
2
ACES_50398-04041-001
CONN@
R1138
100K_0402_5%
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R422
100K_0402_5%
G5
G4
G3
G2
G1
C297
1U_1206_50V7K
45
44
43
42
41
+BL_PWR_SRC
6
5
2
1
D
4
JEDP1
S
Difference with Diesel
2
2
@R426
@
R426
TOUCH_SCREEN_PD#
RB751VM-40TE-17_SOD323-2
1
100K_0402_5%
D69
1
2
PANEL_BKEN_EC
<50>
RB751VM-40TE-17_SOD323-2
CIS link OK
C
C
Touch Screen
+BL_PWR_SRC
1
LCD_EDP_AUX#
100K_0402_5%
2
+LCDVDD
1
LCD_EDP_HPD 4.7K_0402_5%
2
Difference with Diesel
R339
D66
1
2
1
2
1
2
BIA_PWM_PCH
<19>
<50>
TOUCH_SCREEN_PD#
RB751VM-40TE-17_SOD323-2
+5V_RUN
R222
+3.3V_RUN
R336
C248
1
2
4
2
RB751VM-40TE-17_SOD323-2
1
2
3
4
5
6
7
8
GND
GND
ACES_50228-0067N-001
CONN@
LInk CIS
5
A
G
Y
3
R1137
10K_0402_5%
1
2
OE#
D68
1
BIA_PWM
2
1
0.1U_0402_10V7K
1
Close to JEDP1
DGPU_SELECT#
Follow P5_17 TS spec about 140mA (+5V_RUN)
Close to JTS1
P
<29,35,50>
1
2
3
4
5
6
USBP11_DUSBP11_D+
TOUCH_SCREEN_PD#
@C310
@
C310
LCD_EDP_HPD
100K_0402_5%
LCD_EDP_AUX
100K_0402_5%
JTS1
1 R103
0.1U_0402_25V6K
2
+3.3V_RUN
C298
0.1U_0402_25V6K
1
C249
0.1U_0603_50V7K
2
+LCDVDD
2
MXM_BIA_PWM
<17>
@EMC@ D20
U3
TC7SH125FU_SSOP5
USBP11_D-
2
USBP11_D+
3
1
L30ESDL5V0C3-2_SOT23-3
D71
1
2
BIA_PWM_EC
<51>
RB751VM-40TE-17_SOD323-2
EMC request change main source
to SM070002J00
B
Webcam PWR CTRL
USBP11-
<22>
USBP11+
+CAMERA_VDD
Q24
DMG2301U-7_SOT23-3
@EMC@ L11
1
1
D
S
1
4
3
4
3
LPF0805F2SF-900T04 _4P
1
2
0_0402_5%
2
<50>
2
0.1U_0402_25V6K
C299
CCD_OFF
@ C300
10U_0603_6.3V6M
G
0.1U_0402_25V6K
C301
2
1
B
USBP11_DUSBP11_D+
LCD Power
2
@ R430
1
2
@ R429
1
3
2
0_0402_5%
+LCDVDD
@ C396
10U_0603_6.3V6M
2
1
1
Difference with Diesel
2
EMC request change main source
to SM070001N00
C300 change to 0603
due to height limitation.
<19,51>
ENVDD_PCH
+3.3V_ALW
U33
1
VOUT
VIN
2
D92
RB751VM-40TE-17_SOD323-2
2
1
GND
SS
3
5
4
EN
APL3512ABI-TRG_SOT23-5
USBP8-
L10 DLW21SN121SQ2L_4P
4
3
4
3
USBP8_D<50>
1
EMC@
2
2
1
2
@ R427
@ R428
2
1
USBP8_D+
<17>
1
2
MXM_ENVDD
3
2
1
0_0402_5%
2
USBP8+
3
<22>
LCD_VCC_TEST_EN
D93
BAT54CW_SOT323-3
@EMC@ D21
PESD5V0U2BT_SOT23-3
0_0402_5%
1
A
R3727
100K_0402_5%
<22>
1
+3.3V_RUN
<22>
A
D21 change to H: 1.1mm
due to height limitation.
Close to JEDP1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
eDP / CAM / TS
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
30
Rev
0.1
of
67
5
4
3
2
1
MB_DP will have higher priority over TBT.
UV1
2
MB_DEMUX_CFG0
4.7K_0402_5%
2 MB_DEMUX_SW
4.7K_0402_5%
2 MB_DEMUX_P0
4.7K_0402_5%
<17>
<17>
MXM
1
MXM_DPA_P0
MXM_DPA_N0
<17>
<17>
MXM_DPA_P1
MXM_DPA_N1
<17>
<17>
MXM_DPA_P2
MXM_DPA_N2
2
2 0.1U_0402_25V6
CV18 1
CV16
2
2 0.1U_0402_25V6
CV19
6
7
MXM_DPA_P1_C
MXM_DPA_N1_C
9
10
MXM_DPA_P2_C
MXM_DPA_N2_C
12
13
MXM_DPA_P3_C
MXM_DPA_N3_C
15
16
0.1U_0402_25V6
1
2
2 0.1U_0402_25V6
CV20 1
CV21
0.1U_0402_25V6
1
CV22 1
<17> MXM_DPA_P3
<17> MXM_DPA_N3
MXM_DPA_P0_C
MXM_DPA_N0_C
0.1U_0402_25V6
1
CV17 1
2
2 0.1U_0402_25V6
CV23
0.1U_0402_25V6
VDD33
VDD33
VDD33
VDD33
VDD33
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
IN_D0p
IN_D0n
OUT1_D2p
OUT1_D2n
IN_D1p
IN_D1n
OUT1_D3p
OUT1_D3n
IN_D2p
IN_D2n
OUT2_D0p
OUT2_D0n
IN_D3p
IN_D3n
OUT2_D1p
OUT2_D1n
+3.3V_RUN
@ RV15
4.7K_0402_5%
2
1
@ RV14
4.7K_0402_5%
2
1
@ RV13
4.7K_0402_5%
2
1
@ RV12
4.7K_0402_5%
2
1
@ RV11
4.7K_0402_5%
2
1
@ RV10
4.7K_0402_5%
2
1
MXM_DPA_HPD
MB_DEMUX_P1
MB_DEMUX_P0
22
23
2
24
MXM_DPA_AUX_C
2 0.1U_0402_25V6 MXM_DPA_AUX#_C 25
1
<17> MXM_DPA_AUX
<17> MXM_DPA_AUX#
MB_DEMUX_P1
4
3
2
1
60
CV24 1
CV25
0.1U_0402_25V6
MB_DEMUX_PC10
MB_DEMUX_CFG0
MB_DEMUX_PC11
MB_DEMUX_PC10
MB_DEMUX_PC11
MB_DEMUX_PC20
MB_DEMUX_PC21
MB_DEMUX_PC20
59
58
56
55
54
53
MB_DEMUX_PC21
11
19
52
61
RV18
4.7K_0402_5%
2
1
IN_DDC_SCL
IN_DDC_SDA
IN_AUXp
IN_AUXn
CFG0
CFG1
PC10
PC11
PC20
PC21
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
SW
PEQ
PD
CEXT
REXT
GND
GND
GND
PAD(GND)
42
41
40
39
MB_DP_RP_P0
MB_DP_RP_N0
37
36
MB_DP_RP_P1
MB_DP_RP_N1
35
34
MB_DP_RP_P2
MB_DP_RP_N2
32
31
MB_DP_RP_P3
MB_DP_RP_N3
28
29
H
CFG0
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
TBT_DP_P2
TBT_DP_N2
<32>
<32>
TBT_DP_P3
TBT_DP_N3
<32>
<32>
D
TBT
MB_DP
TBT_DP_AUX <32,33>
TBT_DP_AUX# <32,33>
TBT_CONFIG1_BUF
<32,33>
TBT_DP_HPD
<32>
33
38
MB_DP_CA_DET
MB_DP_HPD
18
8
14
17
20
MB_DEMUX_SW
MB_DEMUX_PEQ
+3.3V_RUN
MB_DP_RP_AUX#
100K_0402_5%
2
1
MB_DP_RP_AUX
100K_0402_5%
MB_DP_CA_DET
1M_0402_5%
DP_MB_P14
5.1M_0603_1%
2
1
2
1
2
1
R56
C
R59
R62
R801
Difference with Diesel
L
+3.3V_RUN
V
V
1
2
4
OUT
MB_DP_RP_AUX
DP_MB_P14
MB_DP_CA_DET
1
3
4
3
2
2
6
1
2
3
1
2
6
1
2
B
JDP1
MB_DP_HPD
MB_DP_RP_AUX#
Q335B
DMN66D0LDW-7_SOT363-6
5
1
C482
10U_0805_10V6K
2
MXM_DPA_AUX
+3.3V_RUN
R2157
4.7K_0402_5%
2
C1332
0.01U_0402_16V7K
1
2
1
C313
0.01U_0402_16V7K
5
DMN66D0LDW-7_SOT363-6
Q336A
MB_DP_DEMUX_CA_DET
+DP_VCC
Q335A
DMN66D0LDW-7_SOT363-6
2
MB_DP_DEMUX_CA_DET_Q
DMN66D0LDW-7_SOT363-6
Q336B
R2152
100K_0402_5%
B
R2153
100K_0402_5%
+3.3V_RUN
1
R2151
4.7K_0402_5%
+5V_RUN
GND
+3.3V_RUN
MXM DP_A Dongle DDC
U30
AP2337SA-7_SOT23-3
IN
1
SW
<32>
<32>
MB_DP_RP_AUX
MB_DP_RP_AUX#
43
48
PS8338BQFN60GTR-A0_QFN60_5X9
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
<32>
<32>
TBT_DP_P1
TBT_DP_N1
26
27
@
RV22
4.7K_0402_5%
2
1
@
@ RV21
4.7K_0402_5%
2
1
RV17
4.7K_0402_5%
2
1
@
@ RV16
4.7K_0402_5%
2
1
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
45
44
TBT_DP_P0
TBT_DP_N0
CV26
2.2U_0402_6.3V6M
@ RV20
4.7K_0402_5%
2
1
MB_DEMUX_PEQ
C
IN_CA_DET
IN_HPD
I2C_CTL_EN
Pl1/SCL_CTL
Pl0/SDA_CTL
47
46
RV19
4.99K_0402_1%
2
1
MB_DP_DEMUX_CA_DET
<17>
OUT2_D2p
OUT2_D2n
50
49
1
5
21
30
51
57
2
1
1
2
2
1
1
1
2
2
2
CV15
0.1U_0402_25V6
1
CV14
0.1U_0402_25V6
1
RV2
@ RV3
CV12
0.1U_0402_25V6
RV1
CV11
0.01U_0402_16V7K
1
CV13
0.01U_0402_16V7K
+3.3V_RUN
D
Doc: Dell Graphics Behavior Specification Addendum for Nvidia Optimus
Implementatio for Delray.092
+3.3V_RUN
CV62 CV90 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
MB_DP_RP_N3
C282
1
2 0.1U_0402_10V6K MB_DP_RP_N3_C
MB_DP_RP_P3
MB_DP_RP_N2
C279
C286
1
1
2 0.1U_0402_10V6K MB_DP_RP_P3_C
2 0.1U_0402_10V6K MB_DP_RP_N2_C
MB_DP_RP_P2
MB_DP_RP_N1
C281
C283
1
1
2 0.1U_0402_10V6K MB_DP_RP_P2_C
2 0.1U_0402_10V6K MB_DP_RP_N1_C
MB_DP_RP_P1
MB_DP_RP_N0
C280
C1407
1
1
2 0.1U_0402_10V6K MB_DP_RP_P1_C
2 0.1U_0402_10V6K MB_DP_RP_N0_C
MB_DP_RP_P0
C1408
1
2 0.1U_0402_10V6K
MB_DP_RP_P0_C
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DP_PWR
RTN
HP_DET
AUX_CHGND
AUX_CH+
GND
CA_DET
LANE3LANE3_shield
LANE3+
LANE2LANE2_shield
LANE2+
LANE1LANE1_shield
LANE1+
LANE0LANE0_shield
LANE0+
GND
GND
GND
GND
21
22
23
24
FOX_3V11211-N1YD7-7H
CONN@
CIS link OK
MXM_DPA_AUX#
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Compal Electronics, Inc.
DP SW (PS8338) & DP Conn
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
31
of
67
5
4
TBT_ROM_HOLD#
TBT_ROM_CLK
TBT_ROM_DI
D
VCC
HOLD#
CLK
DI(IO0)
1
2
3
4
CS#
DO(IO1)
WP#
GND
1
TB@ R766
10K_0402_5%
2
1
TB@ R769
10K_0402_5%
2
1
TB@UT2
TB@
UT2
8
7
6
5
2
+3.3V_TBT_LC
TB@ R767
10K_0402_5%
2
1
TB@ R770
10K_0402_5%
2
1
TB@ CT1
.1U_0402_16V7K
2
1
+3.3V_TBT_LC
3
Lane N/P Swap configuration
TBT_ROM_CS#
TBT_ROM_DO
TBT_ROM_WP#
D
DPSRC_3_P
DPSRC_3_N
W25X40CLSSIG_SO8
+3.3V_TBT
TB@UT1B
PCIE_PTX_TBRX_P5_C R13
PCIE_PTX_TBRX_N5_C N13
TB@C602 1
TB@C602
TB@C609
TB@
C609 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PRX_TBTX_P6_C T12
PCIE_PRX_TBTX_N6_C T13
TB@C624 1
TB@C624
TB@C625
TB@
C625 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_TBRX_P6_C R15
PCIE_PTX_TBRX_N6_C N15
<20>
<20>
CLK_PCIE_TBT
CLK_PCIE_TBT#
<20>
TBT_PCIECLK_REQ#
<19>
C
<31>
<31>
TBT_DP_P0
TBT_DP_N0
<31>
<31>
TBT_DP_P1
TBT_DP_N1
<31>
<31>
<31>
<31>
<31,33>
<31,33>
TBT_DP_P2
TBT_DP_N2
TBT_DP_P3
TBT_DP_N3
TBT_DP_AUX
TBT_DP_AUX#
CLK_PCIE_TBT
CLK_PCIE_TBT#
TBT_PCIECLK_REQ# R2
PLTRST_TBT#
PLTRST_TBT#
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
TBT_DP_P0_C
TBT_DP_N0_C
B12
A12
TB@C351
TB@C351
TB@C363
TB@
C363
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
TBT_DP_P1_C
TBT_DP_N1_C
B10
A10
TB@C352
TB@C352
TB@C1415
TB@
C1415
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
TBT_DP_P2_C
TBT_DP_N2_C
B8
A8
TB@C354
TB@C354
TB@C365
TB@
C365
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
TBT_DP_P3_C
TBT_DP_N3_C
B6
A6
TB@C1412
TB@C1412
TB@C1413
TB@
C1413
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
TBT_DP_AUX_C
TBT_DP_AUX#_C
D2
D1
TBT_DP_HPD
T3
TBT_ROM_DI
TBT_ROM_DO
TBT_ROM_CS#
TBT_ROM_CLK
T4
T6
S6
S5
T5
TBT_JTAG_TDI
TBT_JTAG_TMS
TBT_JTAG_TCK
TBT_JTAG_TDO
P2
S3
R1
S4
TBT_DP_HPD
TB@ R3729
10K_0402_5%
2
1
TB@ R780
10K_0402_5%
2
1
+3.3V_TBT_LC
TB@ R777
10K_0402_5%
2
1
S7
TB@C355
TB@C355
TB@C353
TB@
C353
<31>
TB@ R778
10K_0402_5%
2
1
N16
N17
TBT_JTAG_TDI
TBT_JTAG_TMS
TBT_JTAG_TCK
TBT_JTAG_TDO
B
T15
S15
T16
T17
E7
+3.3V_TBT_LC
1
TB@R784
TB@
R784
1
TB@R783
TB@
R783
2 TBT_TEST_EN
100_0402_1%
2 TBT_TEST_PWRG
10K_0402_5%
L2
N1
T7
T1
K4
PERP_0
PERN_0
G14 TBT_CIO_RX_P0_C
F14 TBT_CIO_RX_N0_C
CIO0_RX_P
CIO0_RX_N
PETP_1
PETN_1
PERP_1
PERN_1
J1
G2
CONFIG1
CONFIG2
CIO1_RX_P
CIO1_RX_N
PCIE_CLKREQ_OD_N
TB@CT42
TB@CT42
TB@CT43
TB@
CT43
TBT_CONFIG1_BUF
TBT_CONFIG2_BUF
LSTX
LSRX
1
1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
TB@CT32 1
TB@CT32
TB@CT33
TB@
CT33 1
TBT_CIO_TX_P0_C <33>
TBT_CIO_TX_N0_C <33>
TBT_CIO_RX_P0 <33>
TBT_CIO_RX_N0 <33>
TBT_DP_PWRDN
TB@RT102
TB@
RT102 1
2 10K_0402_5%
TBT_BATLOW#_BUFF TB@
TB@RT103
RT103 1
2 10K_0402_5%
<31,33>
<33>
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
+3.3V_TBT
TBT_CIO_TX_P1_C
TBT_CIO_TX_N1_C
K14
J14
TBT_CIO_RX_P1_C
TBT_CIO_RX_N1_C
J2
H1
TBT_LSTX
TBT_LSRX
B14
A14
DP_TBT_ML1_P
DP_TBT_ML1_N
TB@CT38 1
TB@CT38
TB@CT39
TB@
CT39 1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
DP_TBT_ML1_P_C
DP_TBT_ML1_N_C
B16
A16
DP_TBT_ML3_N
DP_TBT_ML3_P
TB@CT36 1
TB@CT36
TB@CT37
TB@
CT37 1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
DP_TBT_ML3_N_C
DP_TBT_ML3_P_C
E2
E1
DPSRC_AUX
DPSRC_AUX#
1 0.1U_0402_10V6K
1 0.1U_0402_10V6K
DPSRC_AUX_C
DPSRC_AUX#_C
F2
DPSRC_HPD
K1
TBT_HV_EN
F1
TBT_CIO_SEL
K2
TBT_DP_PWRDN
S16
XTAL_25_IN
TB@CT44
TB@CT44
TB@CT50
TB@
CT50
1
1
TBT_CIO_TX_P0_C
TBT_CIO_TX_N0_C
2 0.47U_0402_6.3V6K TBT_CIO_RX_P0
2 0.47U_0402_6.3V6K TBT_CIO_RX_N0
TBT_CONFIG1_BUF
TBT_CONFIG2_BUF
H17 TBT_CIO_TX_P1
G17 TBT_CIO_TX_N1
CIO1_TX_P_DPSRC_2_P
CIO1_TX_N_DPSRC_2_N
REFCLK_100_IN_P
REFCLK_100_IN_N
TB@CT28 1
TB@CT28
TB@CT29
TB@
CT29 1
2 0.47U_0402_6.3V6K TBT_CIO_RX_P1
2 0.47U_0402_6.3V6K TBT_CIO_RX_N1
TBT_CIO_TX_P1_C <33>
TBT_CIO_TX_N1_C <33>
TBT_CIO_PLUG_EVENT#2
TB@RT10
TB@
RT10
TBT_CIO_RX_P1 <33>
TBT_CIO_RX_N1 <33>
TB@
1
TBT_HV_EN
TBT_RTD3_PWR_EN 2
3
TBT_FORCE_PWR
4
TBT_LSTX <33>
TBT_LSRX <33>
PERST_N_OD
DP_SNK0_0_P
DP_SNK0_0_N
DP_SNK0_1_P
DP_SNK0_1_N
DPSRC_1_P
DPSRC_1_N
DPSRC_3_P
DPSRC_3_N
DP_SNK0_2_P
DP_SNK0_2_N
DPSRC_AUX_P
DPSRC_AUX_N
DPSRC_HPD
DP_SNK0_3_P
DP_SNK0_3_N
HV_EN
DP_SNK0_AUX_P
DP_SNK0_AUX_N
CIO_SEL
DP_PWRDN
TB@CT40
TB@CT40
TB@CT41
TB@
CT41
2
2
DPSRC_HPD
DP_TBT_ML1_P_C <33>
DP_TBT_ML1_N_C <33>
1
3.3K_0402_5%
RPT5
8
7
6
5
C
10K_0804_8P4R_5%
DP_TBT_ML3_N_C <33>
DP_TBT_ML3_P_C <33>
Lane N/P Swap
DPSRC_AUX_C <33>
DPSRC_AUX#_C <33>
TBT_CIO_SEL
1
TB@RT2
TB@
RT2
2
100K_0402_5%
<33>
TBT_HV_EN
TBT_CIO_SEL
<60>
<33>
TBT_DP_PWRDN
<33>
DPSNK0_HPD
EE_DI
EE_DO
EE_CS_N
EE_CLK
RSVD
XTAL_25_IN
R17 XTAL_25_OUT
XTAL_25_OUT
RSENSE
TDI
TMS
TCK
TDO
RBIAS
EN_CIO_PWR_N_OD
MONDC0
MONDC1
SVR_AMON
WAKE_N_OD
SLP_S3#
TEST_EN
RTD3_PWR_EN
TEST_PWR_GOOD
FORCE_PWR
THERMDA
RSVD1_GND
RSVD2_GND
2
TBT_RSENSE
TB@RT25
TB@
RT25
L17
TBT_RBIAS
P1
TBT_CIO_PLUG_EVENT#
2
0_0402_5%
1 XTAL_25_OUT_R
TB@R1145
TB@
R1145
1
1K_0402_1%
TB@YT1
TB@
YT1
3
CIO_PLUG_EVENT_N_OD
MONOBSP
MONOBSN
L16
BATLOW_N_OD
POC_RST_N
N2
EN_CIO_PWR#
S2
TBT_WAKE#
M2
1
TB@RT26
TB@
RT26
TBT_SLP_S3#_BUFF
L1
TBT_RTD3_PWR_EN
H2
TBT_FORCE_PWR
G1
TBT_BATLOW#_BUFF
M1
TBT_POC_RST#
TBT_CIO_PLUG_EVENT#
<23>
EN_CIO_PWR# <34>
2
PCIE_WAKE#
0_0402_5%
TBT_FORCE_PWR
4
OUT
IN
GND
GND
1
2
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
E17 TBT_CIO_TX_P0
D17 TBT_CIO_TX_N0
CIO0_TX_P_DPSRC_0_P
CIO0_TX_N_DPSRC_0_N
2 10K_0402_5%
25MHZ_18PF_X3G025000DI1H-H
TB@CT52
TB@CT52
20P_0402_50V8
<17,42,50>
B
TB@CT54
TB@
CT54
20P_0402_50V8
2
TB@C616 1
TB@C616
TB@C620
TB@
C620 1
PETP_0
PETN_0
1
PCIE_PTX_TBRX_P6
PCIE_PTX_TBRX_N6
PCIE_PRX_TBTX_P5_C T9
PCIE_PRX_TBTX_N5_C T10
TB@RT101
TB@
RT101 1
2
<22>
<22>
PCIE_PRX_TBTX_P6
PCIE_PRX_TBTX_N6
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIe
<22>
<22>
PCIE_PTX_TBRX_P5
PCIE_PTX_TBRX_N5
TB@C599 1
TB@C599
TB@C600
TB@
C600 1
TBT Port
<22>
<22>
PCIE_PRX_TBTX_P5
PCIE_PRX_TBTX_N5
DP_Port
<22>
<22>
EN_CIO_PWR#
<23>
DSL5110-QFW9-A0_FSSCP185_8X8~D
TBT_SLP_S5#_BUFF
4
1
O
NC
I
2
1
2
5
P
4
1
O
NC
SIO_SLP_S5#
2
I
G
TBT_SLP_S3#_BUFF
Remove BATT low CKT
3
5
<33>
P
GND
TPS3895ADRYT_SON6
TB@ CT155
2700P_0402_50V7K
G
CT
2
TB@R790
TB@
R790
10K_0402_5%
2
TB@R792
TB@
R792
10K_0402_5%
TBT_POC_RST#
2
4
1
1
OUT
SENSE
3
1
5
EN
2
1
3
2
TB@ RT5
TB@ RT4
31.6K_0402_1%~D 100K_0402_5%
1
2
1
2
1
2
TB@ CT153
.1U_0402_16V7K
A
TBT_SLP_S5#_BUFF
VCC
TB@ CT151
.1U_0402_16V7K
+3.3V_TBT
TB@UT3
TB@
UT3
6
TB@ CT154
.1U_0402_16V7K
+3.3V_TBT
1
+3.3V_TBT
SIO_SLP_S3#
<19,41,51,54>
TB@ UT12
74LVC1G17GW_TSSOP5
<19,41,51>
A
TB@ UT14
74LVC1G17GW_TSSOP5
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
BWD-TBT-LP(1/3) DP,PCIE
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
32
of
67
5
4
3
2
1
+12VS_TB
+3.3V_TBT
OPEN
1
0
V3P3
1
1
VHV
1
2
2
6
+12VS_TB
TB@ CT160
10U_0805_25V6K
1
1
TB@RT98
TB@
RT98
2
2
10K_0402_5%
1
TB@ CT129
.1U_0402_16V7K
2
1
1
VHV
VHV
TPS22981RGPR_QFN20_4X4
TB@ CT158
.1U_0402_16V7K
2
1
2
18
TB@CT127
TB@
CT127
0.01U_0402_16V7K
2
1
+VCC3V3_SW_TBT
15
16
2
3
4
1
6
7
2
TB@ CT142
4.7U_0805_25V6-K
+VCC_TBT
TB@ CT159
10U_0805_10V4Z
1
GND
ENHVU
12
14
TPad
ISET_V3P3
ISET_S3
ISET_S0
1
2
3
4
13
0
OUT
OUT
V3P3OUT
8
9
10
TB@ RT94
35.7K_0402_1%
OPEN
TB@ RT95
35.7K_0402_1%
2
1
0
2
0
19
20
V3P3
V3P3
EN
HV_EN
S0
OUT
1
HV_EN
5
11
17
TBT_SLP_S5#_BUFF
TPS22980_HV_EN
2
UT6_S0
100K_0402_5%
ISET_V3P3
ISET_S3
ISET_S0
21
1
TB@RT7
TB@
RT7
TB@ RT96
35.7K_0402_1%
2
1
EN
TBT_SLP_S5#_BUFF
GND
GND
GND
FAULTZ
GND
<32>
+3.3V_TBT
5
TB@ QT353A
DMN66D0LDW-7_SOT363-6
TB@UT6
TB@
UT6
TB@ CT132
.1U_0402_16V7K
2
1
TB@ CT131
.1U_0402_16V7K
TB@ CT134
22U_0805_6.3VAM
2
1
2
TPS22980_HV_EN
1
TB@RT45
TB@
RT45
1
TB@RT46
TB@
RT46
1
TBT_CIO_TX_P1_C
TB@RT47
TB@
RT47
1
TBT_CIO_TX_N1_C
TB@RT48
TB@
RT48
1
DP_TBT_ML3_P_C
TB@RT50
TB@
RT50
1
DP_TBT_ML3_N_C
TB@RT49
TB@
RT49
D
2
470K_0402_5%
2
470K_0402_5%
2
470K_0402_5%
2
470K_0402_5%
2
470K_0402_5%
2
470K_0402_5%
TBT_CIO_TX_P0_C
TBT_CIO_TX_N0_C
Current design (12V) = 1.06A
Current design (3V) = 1.18A
TB@ QT353B
DMN66D0LDW-7_SOT363-6
+
TB@ RT100
10K_0402_5%
D
1
TB@ CT133
100U_B2_6.3VM_R35M
2
1
+3.3V_TBT
Design guide:
1*100u
1*22u
1*0.1u
TB@ RT99
10K_0402_5%
1
+3.3V_TBT
C
C
+VCC3V3_SW_TBT
TBT_CONFIG1_BUF
<32>
DPSRC_HPD
<32>
<32>
DP_TBT_ML1_P_C
DP_TBT_ML1_N_C
B
TBT_CONFIG1_BUF
16
DPSRC_HPD
12
DP_TBT_ML1_P_C
DP_TBT_ML1_N_C
11
10
TBT_LSTX
TBT_LSRX
14
13
AUX+
AUXDDC_CLK
DDC_DAT
1
<32>
<32>
TBT_CONFIG2_BUF
4
1
O
NC
+3.3V_TBT_LC
I
22
23
TBT_AUX_CHP
TBT_AUX_CHN
18
TBT_CONFIG1_RC
17
TBT_HPD
19
20
DP_LSTX_ML1_P
DP_LSRX_ML1_N
6
TBT_DP_PWRDN
TBT_CONFIG1_RC
TBT_CONFIG2_RC
2
TB@ UT9
74LVC1G17GW_TSSOP5
HIGH= DDC
S LOW = AUX
CA_DET
HPDOUT
LSTX
LSRX
TBT_CIO_SEL
P
5
AUXIO+
AUXIO-
CA_DETOUT
DP+
DP-
TBT_CIO_SEL
3
10G
MUX
2:1
AUX
MUX
2:1
HPD
DP
MUX
2:1
DPMLO+
DPMLO-
S
HIGH= LSXX
DP_PD
B
TBT_DP_PWRDN
JTHB1
<32>
TB@CT45
TB@
CT45 1
LOW = DPX
CBTL05024BS_HVQFN24_3X3
2
25
9
21
TPAD
GND
GND
<32> TBT_LSTX
<32> TBT_LSRX
5
4
24
1
TBT_DP_AUX
TBT_DP_AUX#
<31,32>
2
1
TBT_DP_AUX
TBT_DP_AUX#
15
2
<31,32>
<31,32>
DPSRC_AUX_C
DPSRC_AUX#_C
TB_ENA
AUXIO_EN
TB@CT49
0.01U_0402_16V7K
DPSRC_AUX_C
DPSRC_AUX#_C
Control
E
TB+
TB-
1
<32>
<32>
TBT_CIO_RX_P1
TBT_CIO_RX_N1
8
7
TB@ RT54
100K_0402_5%
<32>
<32>
TBT_CIO_RX_P1
TBT_CIO_RX_N1
G
UT11
VDD
TB@
3
2
TB@CT51
TB@CT51
0.47U_0402_6.3V6K
TB@ CT150
.1U_0402_16V7K
2
1
+3.3V_TBT
TB@ RT61
1K_0402_5%
1
2
TBT_CIO_RX_P0
TBT_CIO_RX_N0
+VCC3V3_SW_TBT
TB@CT56
TB@
CT56
330P_0402_50V7K
2
1
TBT_DP_AUX#
TB@ RT60
1K_0402_5%
1
2
TBT_DP_AUX
1 4.7K_0402_5%
TB@CT55
TB@
CT55
330P_0402_50V7K
2
1
1 4.7K_0402_5%
2
TB@ RT65
1M_0402_5%
1
2
2
TB@RT105
TB@
RT105
TB@ RT64
1M_0402_5%
1
2
TB@RT104
TB@
RT104
<32>
<32>
<32>
<32>
<32>
<32>
2 0.01U_0402_16V7K
TBT_HPD
TBT_CIO_TX_P0_C
TBT_CIO_TX_P0_C
TBT_CIO_RX_P0
TBT_CIO_RX_P0
TBT_CIO_TX_N0_C
TBT_CIO_TX_N0_C
TBT_CIO_RX_N0
TBT_CIO_RX_N0
1
2
TB@CT46
TB@
CT46
0.01U_0402_16V7K
DP_LSTX_ML1_P
DP_TBT_ML3_P_C
DP_TBT_ML3_P_C
DP_LSRX_ML1_N
DP_TBT_ML3_N_C
DP_TBT_ML3_N_C
<32>
TBT_CIO_TX_P1_C
<32>
TBT_CIO_TX_N1_C
TBT_CIO_TX_P1_C
TBT_AUX_CHP
TBT_CIO_TX_N1_C
TBT_AUX_CHN
+VCC_TBT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PWR_IN
HPD_GND
TBT_HD2CA_0+
TBT_CA2HD_0+
TBT_HD2CA_0TBT_CA2HD_0GND
GND
LSTX
RESERVED
LSRX
RESERVED
GND
GND
TBT_HD2CA_1+
TBT_CA2HD_1+
TBT_HD2CA_1TBT_CA2HD_1RETURN
G
PWR_OUT
G
21
22
1
LOTES_GAP-ADIS0008-P005A01
CONN@
TB@ RT66
12.1_0402_1%
1 2
CIS link OK
2
TB@CT53
TB@
CT53
0.01U_0402_16V7K
A
A
2012/10/18 INTEL: this 12.1 ohm is still required
for JAE or Lintes TBT connector
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
BWD-TBT-LP(2/3) HOST,mDP
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
33
of
67
A
B
C
D
E
SVR_VSS
SVR_VSS
SVR_VSS
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TB@ CT139
1U_0402_6.3V6K
2
1
TB@ CT140
1U_0402_6.3V6K
2
1
TB@ CT138
1U_0402_6.3V6K
2
1
TB@ CT145
1U_0402_6.3V6K
2
1
TB@ CT144
1U_0402_6.3V6K
2
1
2
TB@ CT146
1U_0402_6.3V6K
2
1
TB@ CT149
1U_0402_6.3V6K
2
1
TB@ CT148
1U_0402_6.3V6K
2
1
1
TB@ CT147
1U_0402_6.3V6K
2
1
1
TB@ CT163
10U_0805_10V4Z
2
TB@ CT164
10U_0805_10V4Z
TB@ CT165
10U_0805_10V4Z
2
1
2
+1.05V_TBT_SVR
TB@LT702
TB@
LT702 1
+1.0_TBT_SVR_OUT
2 0.68UH_PHT25201B-R68MS_2.97A_20%
A2
A3
B3
TB@DT92
TB@
DT92
NSR1020MW2T1G_SOD323-2
P14
P16
P17
R16
S8
S9
S10
S11
S12
S13
S14
S17
T8
T11
T14
C1
C2
G5
G7
G11
H11
K7
K10
L4
L7
L10
L11
N7
P7
S1
T2
1
2
1
2
TB@ CT162
10U_0805_10V4Z
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
A1
B1
B2
1
TB@ CT161
10U_0805_10V4Z
A5
A7
A9
A11
A13
A15
A17
B5
B7
B9
B11
B13
B15
B17
C16
C17
D8
D10
E13
E14
E16
F16
F17
G13
G16
H14
J16
J17
K13
K16
L13
L14
M16
N11
P11
SVR_IND
SVR_IND
SVR_IND
VCC3P3_LC
A4
B4
D4
TB@ CT143
10U_0805_10V4Z
N4
G4
E4
E5
+3.3V_TBT
TB@ CT130
10U_0805_10V4Z
TB@ CT137
1U_0402_6.3V6K
2
1
SVR_VCC3P3
SVR_VCC3P3
SVR_VCC3P3
H5
H8
H10
M17
1
VCC3P3_RDV_DECAP
+3.3V_TBT_LC
2
VCC3P3
VCC3P3
VCC3P3A
1
+1.05V_TBT_SVR
2
VCC3P3_RDV_DP
VCC3P3_RDV_DP
VCC3P3_RDV_CIO
VCC3P3_RDV_DP_AUX
SVR_VCC1P0
SVR_VCC1P0
SVR_VCC1P0
VCC1P0_SVR_ANA
H7
K5
K8
L5
L8
N5
N8
P5
P8
TB@ CT166
10U_0805_10V4Z
VCC1P0_RDV_DECAP
VCC1P0_RDV_DECAP
VCC1P0_RDV_DECAP
VCC1P0_RDV_DECAP
VCC1P0_RDV_DECAP
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
VCC1P0_CIO
OUT
P4
VCC1P0_RDV_ANA
VCC1P0_RDV_ANA
VCC1P0_RDV_ANA
VCC1P0_RDV_ANA
VCC1P0_RDV_ANA
VCC1P0_RDV_ANA
VCC1P0_RDV_DPAUX
IN
D13
G8
G10
E11
K11
D7
D11
K17
D5
TB@ CT125
1U_0402_6.3V6K
2
1
TB@ CT126
1U_0402_6.3V6K
2
1
TB@ CT124
1U_0402_6.3V6K
2
1
TB@ CT136
1U_0402_6.3V6K
2
1
TB@ CT135
1U_0402_6.3V6K
2
1
+3.3V_RDV_DECAP
D14
E8
E10
H13
N10
P10
H4
IN
TB@ CT123
1U_0402_6.3V6K
2
1
TB@ CT122
1U_0402_6.3V6K
2
1
TB@ CT121
1U_0402_6.3V6K
2
1
TB@ CT115
1U_0402_6.3V6K
2
1
TB@ CT116
1U_0402_6.3V6K
2
1
TB@ CT114
1U_0402_6.3V6K
2
1
TB@ CT113
1U_0402_6.3V6K
2
1
TB@ CT119
1U_0402_6.3V6K
2
1
2
TB@ CT118
1U_0402_6.3V6K
2
1
1
TB@ CT117
1U_0402_6.3V6K
2
1
2
TB@ CT120
10U_0805_10V4Z
TB@ CT128
10U_0805_10V4Z
1
OUT
TB@UT1A
1
TB@ CT141
1U_0402_6.3V6K
2
1
+1.05V_TBT_CIO
+1.05V_RDV_DECAP
1
2
1
2
2
DSL5110-QFW9-A0_FSSCP185_8X8~D
3
3
TBT Power circuit
+3.3V_ALW
+1.05V_TBT_CIO
1
TB@U633
TB@
U633
3
4
S
3
TBT_PWR_EN
1
2
VIN
VIN
VIN
ON
VOUT
VOUT
VOUT
GND
A1
B1
C1
D1
+1.05V_CIO_U39
1
2
TPS22920YZPR_BGA8
TB@ CT156
10U_0805_10V4Z
EN_CIO_PWR_EN
A2
B2
C2
D2
2
TB@UT39
TB@
UT39
TB@ QT56
DMN65D8LW-7_SOT323-3
2
1
1
D
2
G
EN_CIO_PWR#
+1.05V_TBT_SVR
TBT_PWR_EN
4
+5V_ALW
6
1
2
TB@C1417
TB@
C1417
470P_0402_50V7K
<32>
<50>
PJP@
PJP12
PAD-OPEN1x1m
+3.3V_TBT_PWR
ON
VIN
VOUT
VIN
VOUT
VBIAS
CT
GND
GND
+3.3V_TBT
7
PJP603
8
2
1
5
9
2
TPS22965DSGR_SON8_2X2~D
TB@C1416
TB@
C1416
10U_0805_10V4Z
TB@ RT6
100K_0402_5%
+3.3V_TBT
2
1
1
JUMP_43X79
PJP@
4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Compal Electronics, Inc.
Title
BWD-TBT-LP(3/3) VCC/VSS
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
E
34
of
67
5
4
3
2
+5V_RUN
<17>
<19>
8
18
MXM_CRT_GRN
PCH_CRT_GRN
9
19
<17> MXM_CRT_BLU
<19> PCH_CRT_BLU
Channel A (MXM)
5
15
<17> MXM_CRT_DDC_CLK
<19> PCH_CRT_DDC_CLK
D
6
16
<17> MXM_CRT_DDC_DAT
<19> PCH_CRT_DDC_DAT
1
R421
+3.3V_RUN
2 CRT_EN
100K_0402_5%
2
3
13
<17> MXM_CRT_HSYNC
<19> PCH_CRT_HSYNC
Channel B (PCH)
4
14
<17> MXM_CRT_VSYNC
<19> PCH_CRT_VSYNC
<50> EDID_SELECT#
<50> CRT_SWITCH
<29,30,50> DGPU_SELECT#
1
40
39
38
CRT_SWITCH
CRT_SWITCH
30
20
10
41
CRT_SWITCH
DGPU_SELECT#
EDID_SELECT#
+3.3V_RUN
1
MAX14885E
REDA
REDB
VCC
VCC
GRNA
GRNB
VL
BLUA
BLUB
RED1
RED2
SCLA
SCLB
GRN1
GRN2
SDAA
SDAB
EN
BLU1
BLU2
SHA
SHB
SCL1
SCL2
SVA
SVB
SDA1
SDA2
S00
S01
S10
S11
SH1
SH2
SV1
SV2
GND
GND
GND
NC
29
2
21
C1181
1U_0402_6.3V6K
U19
7
17
<17> MXM_CRT_RED
<19> PCH_CRT_RED
1
1
C1182
1U_0603_10V7K
2
11
33
24
RED_CRT
32
23
GREEN_CRT
31
22
BLUE_CRT
35
26
CLK_DDC2_CRT
34
25
DAT_DDC2_CRT
37
28
HSYNC_BUF
36
27
VSYNC_BUF
RED_DOCK
<48>
D
GREEN_DOCK
BLUE_DOCK
Port 1 (MB_CRT)
<48>
<48>
CLK_DDC2_DOCK
<48>
DAT_DDC2_DOCK
<48>
HSYNC_DOCK
<48>
VSYNC_DOCK
<48>
Port 2 (Dock_CRT)
12
GPAD
MAX14885EETL+T_TQFN40_5X5~D
Output
SDAA to SDA1
SCLA to SCL1
DSC mode output to MB VGA
0
0
REDA to RED1
GRNA to GRN1
BLUA to BLU1
SHA to SH1
SVA to SV1
0
SDAA to SDA2
SCLA to SCL2
REDA to RED2
GRNA to GRN2
BLUA to BLU2
SHA to SH2
SVA to SV2
C
DSC mode output to docking VGA
1
0
0
C
SDAB to SDA1
SCLB to SCL1
UMA mode output to MB VGA
1
0
REDB to RED1
GRNB to GRN1
BLUB to BLU1
SHB to SH1
SVB to SV1
1
SDAB to SDA2
SCLB to SCL2
1
1
REDB to RED2
GRNB to GRN2
BLUB to BLU2
SHB to SH2
SVB to SV2
1
+5V_RUN
+CRT_VCC
2
2
1
2
1
2
1
2
IN
C13
10P_0402_50V8J
2
C12
10P_0402_50V8J
1
C21
10P_0402_50V8J
2
C22
22P_0402_50V8J
1
C23
22P_0402_50V8J
2
C20
22P_0402_50V8J
R55
150_0402_1%
R54
150_0402_1%
R53
150_0402_1%
1
B
@ T61
PAD~D
CRT_11
BLUE_CRT_L
OUT
GREEN_CRT_L
2 BLM15BB220SN1D_2P
GND
2 BLM15BB220SN1D_2P
EMC@ L3 1
3
EMC@ L2 1
BLUE_CRT
2
2
GREEN_CRT
1
RED_CRT_L
1
2 BLM15BB220SN1D_2P
1
EMC@ L1 1
2
B
RED_CRT
U6
AP2330W-7_SC59-3
Difference with Diesel
C14
1U_0402_6.3V6K
1
1
UMA mode output to docking VGA
+CRT_VCC
+CRT_VCC
M_ID2#
1
2
1
2
@
@
1
2
2
@ R52
1K_0402_5%
R48
2.2K_0402_5%
@ R50
1K_0402_5%
R47
2.2K_0402_5%
1
DAT_DDC2_CRT
CLK_DDC2_CRT
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
G
G
16
17
18
19
DAT_DDC2_CRT
SUYIN_070449HR015M223ZR
CONN@
CLK_DDC2_CRT
HSYNC_BUF
VSYNC_BUF
2
EMC@1
BLM15AG121SN1D_L0402_2P
L5
2
EMC@1
BLM15AG121SN1D_L0402_2P
HSYNC_L
2
VSYNC_L
C15
0.1U_0402_16V4Z
1
L4
CIS link OK
A
A
@
1
2
C19
22P_0402_50V8J
2
C18
22P_0402_50V8J
1
@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
VGA CONN
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
Rev
0.1
35
of
67
5
4
3
2
1
+3.3V_RUN
U629
21
26
35
49
60
DP1_MUX_IN2_PEQ
DP1_MUX_IN1_PEQ
DP1_MUX_IN1_AEQ#
DP1_MUX_IN2_AEQ#
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
MXM
<17>
<17>
C
MXM_DPB_AUX
MXM_DPB_AUX#
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
CPU
MXM_DPB_P0
MXM_DPB_N0
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P3
MXM_DPB_N3
DPD_CPU_LANE_P0
DPD_CPU_LANE_N0
DPD_CPU_LANE_P1
DPD_CPU_LANE_N1
DPD_CPU_LANE_P2
DPD_CPU_LANE_N2
DPD_CPU_LANE_P3
DPD_CPU_LANE_N3
<19>
<19>
PCH_DDPD_AUX
PCH_DDPD_AUX#
MXM_DPB_P0
MXM_DPB_N0
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P3
MXM_DPB_N3
C523
C525
C524
C527
C526
C529
C530
C528
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
MXM_DPB_AUX
MXM_DPB_AUX#
C532
C531
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
DPD_CPU_LANE_P0
DPD_CPU_LANE_N0
DPD_CPU_LANE_P1
DPD_CPU_LANE_N1
DPD_CPU_LANE_P2
DPD_CPU_LANE_N2
DPD_CPU_LANE_P3
DPD_CPU_LANE_N3
PCH_DDPD_AUX
PCH_DDPD_AUX#
1
1
1
1
1
1
1
1
C516
C515
C518
C517
C520
C519
C521
C522
2
2
2
2
2
2
2
2
1
1
C533
C534
<19>
<19>
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
PCH_DDPD_CTRLCLK
PCH_DDPD_CTRLDATA
<17> MXM_DPB_HPD
<19> DPD_PCH_HPD
MXM_DPB_P0_C
MXM_DPB_N0_C
MXM_DPB_P1_C
MXM_DPB_N1_C
MXM_DPB_P2_C
MXM_DPB_N2_C
MXM_DPB_P3_C
MXM_DPB_N3_C
1
2
4
5
6
7
9
10
MXM_DPB_AUX_C
MXM_DPB_AUX#_C
28
27
23
22
DPD_CPU_LANE_P0_C
DPD_CPU_LANE_N0_C
DPD_CPU_LANE_P1_C
DPD_CPU_LANE_N1_C
DPD_CPU_LANE_P2_C
DPD_CPU_LANE_N2_C
DPD_CPU_LANE_P3_C
DPD_CPU_LANE_N3_C
PCH_DDPD_AUX_C
PCH_DDPD_AUX#_C
PCH_DDPD_CTRLCLK
PCH_DDPD_CTRLDATA
MXM_DPB_HPD
DPD_PCH_HPD
11
12
14
15
16
17
19
20
30
29
25
24
3
13
OUT_AUXp_SCL
OUT_AUXn_SDA
IN2_PEQ/SCL_CTL
IN1_PEQ/SDA_CTL
IN1_AEQ#
IN2_AEQ#
CA_DET
OUT_D0p
OUT_D0n
OUT_D1p
OUT_D1n
OUT2_D2p
OUT2_D2n
OUT_D3p
OUT_D3n
IN1_AUXp
IN1_AUXn
IN1_SCL
IN1_SDA
IN2_D0p
IN2_D0n
IN2_D1p
IN2_D1n
IN2_D2p
IN2_D2n
IN2_D3p
IN2_D3n
IN1_HPD
IN2_HPD
I2C_CTL_EN
PI0
PC0
PC1
IN1_D0p
IN1_D0n
IN1_D1p
IN1_D1n
IN1_D2p
IN1_D2n
IN1_D3p
IN1_D3n
IN2_AUXp
IN2_AUXn
IN2_SCL
IN2_SDA
+3.3V_RUN
SW
OUT_HPD
32
31
DP1_MUX_AUX
DP1_MUX_AUX#
DP1_MUX_AUX <37>
DP1_MUX_AUX# <37>
53
56
38
55
DP1_MUX_PI0
DP1_MUX_PC0
DP1_MUX_PC1
48
DP1_MUX_CA_DET
46
45
43
42
40
39
37
36
DP1_MUX_P0
DP1_MUX_N0
DP1_MUX_P1
DP1_MUX_N1
DP1_MUX_P2
DP1_MUX_N2
DP1_MUX_P3
DP1_MUX_N3
54
PBA_GPU_SEL#
44
DP1_MUX_HPD
DP1_MUX_CA_DET
DP1_MUX_P0
DP1_MUX_N0
DP1_MUX_P1
DP1_MUX_N1
DP1_MUX_P2
DP1_MUX_N2
DP1_MUX_P3
DP1_MUX_N3
PBA_GPU_SEL#
DP1_MUX_HPD
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
DP1_MUX_PC0
@R98
@
R98
1
2 4.7K_0402_5%
DP1_MUX_PC1
@R99
@
R99
1
2 4.7K_0402_5%
DP1_MUX_IN1_AEQ#
@R117
@
R117 1
2 4.7K_0402_5%
DP1_MUX_IN2_AEQ#
@R118
@
R118 1
2 4.7K_0402_5%
DP1_MUX_IN1_PEQ
@R119
@
R119 1
2 4.7K_0402_5%
DP1_MUX_IN2_PEQ
@R120
@
R120 1
2 4.7K_0402_5%
DP1_MUX_PI0
@R124
@
R124 1
2 4.7K_0402_5%
DP1_MUX_CEXT
<37>
To DEMUX
(PS8338)
C97
2
1 2.2U_0402_6.3V6M
DP1_MUX_PI0
@R123
@
R123 1
2 4.7K_0402_5%
DP1_MUX_PC0
@R115
@
R115 1
2 4.7K_0402_5%
DP1_MUX_PC1
@R116
@
R116 1
2 4.7K_0402_5%
DP1_MUX_IN1_PEQ
@R121
@
R121 1
2 4.7K_0402_5%
DP1_MUX_IN2_PEQ
@R122
@
R122 1
2 4.7K_0402_5%
<50>
<37>
C
REXT
CEXT
34
47
DP1_MUX_REXT
DP1_MUX_CEXT
8
GND 18
GND 33
GND 41
GND 57
GND 61
Epad 50
PD
PS8331BQFN60GTR-A0_QFN60_5X9
R96
4.99K_0402_1%
INy_PEQ = Programmable input equalization levels
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
DOCK DPD (PORT1) DDC-before PS8331
INy_AEQ# = Automatic EQ disable
L: Automatic EQ enable (default)
H: Automatic EQ disable
+3.3V_RUN
9/21
B
PI0 = Auto test enable
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
B
1
2
6
2
MXM_DPB_AUX#
4.7K_0402_5%
2DP1_MUX_CA_DET
1
R132
4
1
R129
PC0 = AUX interception disable
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
PC1 = Output swing adjustment
L: default
H: +20%
M: -16.7%
5
DMN66D0LDW-7_SOT363-6
Q347A
2
MXM_DPB_AUX
4.7K_0402_5%
DMN66D0LDW-7_SOT363-6
Q347B
1
3
2
1
2
R722
100K_0402_5%
1
6
+3.3V_RUN
R721
100K_0402_5%
5
DMN66D0LDW-7_SOT363-6
Q343A
DMN66D0LDW-7_SOT363-6
Q343B
3
+5V_RUN
4
51
52
59
58
D
CIS LINK OK
VDD33
VDD33
VDD33
VDD33
VDD33
2
2
1
2
1
C494
0.1U_0402_16V4Z
2
1
C504
0.1U_0402_16V4Z
2
1
C499
0.1U_0402_16V4Z
1
C495
0.1U_0402_16V4Z
2
D
C783
4.7U_0603_6.3V6K
1
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
MXM/CPU MUX(PS8331)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
36
of
67
5
4
3
2
1
+3.3V_RUN
DP1_MUX_P1
DP1_MUX_N1
<36>
<36>
DP1_MUX_P2
DP1_MUX_N2
1
CV35 1
1
CV38 1
CV39
@ RV34
4.7K_0402_5%
2
1
@ RV33
4.7K_0402_5%
2
1
@ RV32
4.7K_0402_5%
2
1
<36>
<36>
@ RV31
4.7K_0402_5%
2
1
DP1_MUX_P0_C
DP1_MUX_N0_C
6
7
DP1_MUX_P1_C
DP1_MUX_N1_C
9
10
DP1_MUX_P2_C
DP1_MUX_N2_C
12
13
DP1_MUX_P3_C
DP1_MUX_N3_C
15
16
1
1
2
2
1
0.1U_0402_25V6
2
2 0.1U_0402_25V6
0.1U_0402_25V6
1
CV36 1
CV37
+3.3V_RUN
@ RV30
4.7K_0402_5%
2
1
2
2 0.1U_0402_25V6
CV34
<36> DP1_MUX_P3
<36> DP1_MUX_N3
@ RV29
4.7K_0402_5%
2
1
2
1
1
CV32 1
CV33
2
2 0.1U_0402_25V6
0.1U_0402_25V6
2
2 0.1U_0402_25V6
0.1U_0402_25V6
4
3
2
1
60
DP1_MUX_CA_DET
DP1_MUX_HPD
DP1_DEMUX_PI1
DP1_DEMUX_PI0
DP1_DEMUX_PI1
22
23
24
25
<36> DP1_MUX_AUX
<36> DP1_MUX_AUX#
DP1_DEMUX_PC10
59
58
56
55
54
53
DP1_DEMUX_CFG0
DP1_DEMUX_PC11
DP1_DEMUX_PC10
DP1_DEMUX_PC11
DP1_DEMUX_PC20
DP1_DEMUX_PC21
DP1_DEMUX_PC20
DP1_DEMUX_PC21
11
19
52
61
RV40
4.7K_0402_5%
2
1
IN_D1p
IN_D1n
OUT1_D3p
OUT1_D3n
IN_D2p
IN_D2n
OUT2_D0p
OUT2_D0n
IN_D3p
IN_D3n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
IN_CA_DET
IN_HPD
I2C_CTL_EN
Pl1/SCL_CTL
Pl0/SDA_CTL
OUT2_D3p
OUT2_D3n
IN_DDC_SCL
IN_DDC_SDA
IN_AUXp
IN_AUXn
CFG0
CFG1
PC10
PC11
PC20
PC21
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
SW
PEQ
PD
CEXT
REXT
GND
GND
GND
PAD(GND)
45
44
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
42
41
DPD_GPU_LANE_P3
DPD_GPU_LANE_N3
40
39
37
36
35
34
32
31
26
27
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
43
48
DP1_DEMUX_SW
DP1_DEMUX_PEQ
DPD_CA_DET
DPD_GPU_HPD
WIGIG_HPD
<48>
<48>
<48>
<48>
<42>
C
L
V
V
1
6
2
1
1
1
B
DPD_DOCK_AUX
+3.3V_RUN
3
2
5
4
4
DPD_DOCK_AUX
DPD_DOCK_AUX#
WiGig
Q357B
DMN66D0LDW-7_SOT363-6
3
4
<42>
<42>
18
8
14
17
20
2
6
1
2
3
1
2
<42>
<42>
WIGIG_LANE_P3
WIGIG_LANE_N3
Docking
Q357A
DMN66D0LDW-7_SOT363-6
6
<42>
<42>
DPD_CA_DET
DPD_GPU_HPD
R2196
4.7K_0402_5%
1
<48>
<48>
WIGIG_LANE_P2
WIGIG_LANE_N2
W IGIG_CA_DET
DPD_CA_DET_Q
Q355B
DMN66D0LDW-7_SOT363-6
5
<48>
<48>
DPD_GPU_LANE_P3
DPD_GPU_LANE_N3
<42>
<42>
33
38
DP1_MUX_AUX
+3.3V_RUN
R2198
4.7K_0402_5%
DMN66D0LDW-7_SOT363-6
Q353B
2
C1344
0.01U_0402_16V7K
1
DMN66D0LDW-7_SOT363-6
Q353A
2
DPD_CA_DET
2
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
D
+3.3V_RUN
Q355A
DMN66D0LDW-7_SOT363-6
R2189
100K_0402_5%
R2197
100K_0402_5%
5
DPD_CA_DET_Q
<48>
<48>
WIGIG_AUX <42>
WIGIG_AUX# <42>
R2195
4.7K_0402_5%
R2194
4.7K_0402_5%
+5V_RUN
+3.3V_RUN
SW
<48>
<48>
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
WIGIG_LANE_P1
WIGIG_LANE_N1
DPD_DOCK_AUX
DPD_DOCK_AUX#
+3.3V_RUN
DOCK DPD (PORT1) DDC
B
H
CFG0
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
WIGIG_LANE_P0
WIGIG_LANE_N0
28
29
PS8338BQFN60GTR-A0_QFN60_5X9
@
@ RV39
4.7K_0402_5%
2
1
RV37
4.7K_0402_5%
2
1
@
RV38
4.7K_0402_5%
2
1
@
OUT1_D2p
OUT1_D2n
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
CV42
2.2U_0402_6.3V6M
@ RV36
4.7K_0402_5%
2
1
C
@ RV35
4.7K_0402_5%
2
1
DP1_DEMUX_PEQ
IN_D0p
IN_D0n
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
47
46
1
DP1_MUX_P0
DP1_MUX_N0
<36>
<36>
50
49
2
From MUX
(PS8331)
<36>
<36>
OUT1_D1p
OUT1_D1n
RV41
4.99K_0402_1%
2
1
RV26
2
1
2
W IGIG_CA_DET
1M_0402_5%
DP1_MUX_CA_DET
1M_0402_5%
W IGIG_AUX
100K_0402_5%
OUT1_D0p
OUT1_D0n
1
2
VDD33
VDD33
VDD33
VDD33
VDD33
1
2
1
UV2
5
21
30
51
57
2
2
1
RV45
Dock has high priority when both ports plugged
CV31
0.1U_0402_25V6
1
RV28
CV29
0.1U_0402_25V6
RV25
CV28
0.1U_0402_25V6
1
D
CV30
0.01U_0402_16V7K
1
@ RV44
DP1_DEMUX_CFG0
4.7K_0402_5%
2
DP1_DEMUX_SW
4.7K_0402_5%
2
DP1_DEMUX_PI0
4.7K_0402_5%
2
W IGIG_AUX#
100K_0402_5%
CV27
0.01U_0402_16V7K
1
@ RV43
+3.3V_RUN
2
2
CV62 CV90 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
1
RV42
DP1_MUX_AUX#
DPD_DOCK_AUX#
A
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Compal Electronics, Inc.
DP DeMUX (PS8338)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
37
of
67
2
1
+3.3V_RUN
TMDS_RT
4.7K_0402_5%
DP_CFG0
4.7K_0402_5%
TMDS_DDCBUF
4.7K_0402_5%
PEQ
4.7K_0402_5%
DP_CFG1
4.7K_0402_5%
MODE
4.7K_0402_5%
TMDS_PRE
4.7K_0402_5%
+3.3V_RUN
2
@
1
2
C418
0.1U_0402_16V4Z
2
1
C445
0.1U_0402_16V4Z
2
1
C419
0.1U_0402_16V4Z
2
1
C420
0.1U_0402_16V4Z
C768
4.7U_0603_6.3V6K
1
U21
14
28
41
56
44
45
38
DP_CFG0
DOCKED#
MXM
<17>
<17>
MXM_DPC_P0
MXM_DPC_N0
<17>
<17>
MXM_DPC_P1
MXM_DPC_N1
<17>
<17>
MXM_DPC_P2
MXM_DPC_N2
<17>
<17>
MXM_DPC_P3
MXM_DPC_N3
<17>
<17>
MXM_DPC_AUX
MXM_DPC_AUX#
MXM_DPC_P0
MXM_DPC_N0
C551
C552
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_DPC_P0_C
MXM_DPC_N0_C
3
4
MXM_DPC_P1
MXM_DPC_N1
C535
C540
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_DPC_P1_C
MXM_DPC_N1_C
6
7
MXM_DPC_P2
MXM_DPC_N2
C545
C546
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_DPC_P2_C
MXM_DPC_N2_C
9
10
MXM_DPC_P3
MXM_DPC_N3
C548
C550
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_DPC_P3_C
MXM_DPC_N3_C
12
13
C1404
C1405
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
52
MXM_DPC_AUX_C
MXM_DPC_AUX#_C 51
50
49
B
11
<17>
MXM_DPC_HPD
MXM_DPC_HPD
5
CEXT
1
VDD33
VDD33
VDD33
VDD33
DP_D0p
DP_D0n
DP_D1p
DP_D1n
DP_CFG0/SCL_CTL
SW/SDA_CTL
I2C_CTL_EN
DP_D2p
DP_D2n
IN_D0p
IN_D0n
DP_D3p
DP_D3n
IN_D1p
IN_D1n
DP_AUXp_SCL
DP_AUXn_SDA
DP_HPD
IN_D2p
IN_D2n
DP_CA_DET
IN_D3p
IN_D3n
DP_CFG1
IN_AUXp
IN_AUXn
TMDS_CH0p
TMDS_CH0n
IN_DDC_SCL
IN_DDC_SDA
TMDS_CH1p
TMDS_CH1n
IN_CA_DET
TMDS_CH2p
TMDS_CH2n
IN_HPD
TMDS_CLKp
TMDS_CLKn
2
1
27
REXT3
D
53
MODE
1
TMDS_DDCBUF
TMDS_HPD
PEQ
TMDS_RT
TMDS_PRE
REXT
PD
GND
GND
GND
Thermal/GND
MODE
2
16
15
TMDSE_RP_CLK
TMDSE_RP_CLK#
48
47
HDMI_SCL_SINK
HDMI_SDA_SINK
17
HDMI_HPD_SINK
23
20
TMDS_RT
TMDS_PRE
<48>
<48>
<48>
MB_HDMI
1
2
1
2
26
35
43
57
TMDSE_CON_P0
TMDSE_CON_CLK#
TMDSE_CON_N0
1
2
1
2
1
2
1
2
1
2
1
2
1
@ R88
@ R80
R89
@ R84
R75
@ R83
R495
1
2
6
1
+VDISPLAY_VCC
TMDSE_CON_P1
1
2
0_0402_5%
@
1
2
@
GND
OUT
IN
1
1
2
Remove 10K ohm
@
1
2
HDMI_SDA_SINK
HDMI_SCL_SINK
@
+VDISPLAY_VCC
HDMI_CEC
TMDSE_CON_CLK#
R465 1
R462 1
2 1.5K_0402_5% HDMI_SDA_SINK
2 1.5K_0402_5% HDMI_SCL_SINK
+3.3V_RUN
TMDSE_CON_P1
TMDSE_CON_N1
1
HDMI_CEC
10K_0402_5%
HDMI_HPD_SINK 1
100K_0402_5%
TMDSE_CON_N2
DLW21HN900HQ2L_4P
1
2
2
0_0402_5%
EMI request non-pop R451~R456,R458,R459 and
pop L19,L23~25 and HDMI EA have verify it.
@
1
2
C1338
3.3P_0402_50V8C
TMDSE_CON_N2
C1337
3.3P_0402_50V8C
2
@
1
2
@
1
2
C1342
3.3P_0402_50V8C
2
TMDSE_CON_P1
TMDSE_CON_N2
TMDSE_CON_P2
TMDSE_CON_P2
C1339
3.3P_0402_50V8C
1
TMDSE_CON_CLK
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_CON_N1
0_0402_5%
3
2
TMDSE_CON_P2
R1165
2
1
2
A
JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
CONCR_099BAAC19BBLCNF-A1
CONN@
@ R1128
CIS link OK
@
46@ HDMI
Part Number
RO0000002HM
Description
HDMI W/Logo:RO0000002HM
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
2
DPC_DOCK_SW _AUX#
2
3
1
3
5
C1336
3.3P_0402_50V8C
2
2
4
@ R458
2
+5V_RUN
2
3
TMDSE_CON_CLK
C1335
3.3P_0402_50V8C
2
1
R85
@ R79
DPC_DOCK_SW _AUX
+3.3V_RUN
TMDSE_CON_N1
EMC@ L25
1
1
2
1
1
MXM_DPC_AUX
EMI request reserve C(3.3pF) for HDMI signals.
C1340
3.3P_0402_50V8C
1
3
C1334
3.3P_0402_50V8C
3
@ R459
TMDSE_RP_N2
1
2
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
HDMI_HPD_SINK
4
@ R456
4
2
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
2
DPC_DOCK_AUX_Q
MXM_DPC_AUX#
DLW21HN900HQ2L_4P
TMDSE_RP_P2
@ R81
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
+3.3V_RUN
3
4
TMDSE_CON_N0
0_0402_5%
1
R86
@ R76
TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
EMC@ L24
1
1
TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors
4
2
5
TMDSE_CON_P0
4
3
0_0402_5%
@ R455
1
2
@ R77
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
internal 150K ohm PD.
A
TMDSE_RP_P1
1
C47
10U_0805_10V6K
2
@ R454
TMDSE_RP_N1
1
2
MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
C46
0.1U_0402_10V7K
3
DLW21HN900HQ2L_4P
4
1
2
B
U5
AP2330W-7_SC59-3
0_0402_5%
1
TMDSE_RP_P2
TMDSE_RP_N2
DP_CFG0
4.7K_0402_5%
TMDS_DDCBUF
4.7K_0402_5%
PEQ
4.7K_0402_5%
DP_CFG1
4.7K_0402_5%
MODE
4.7K_0402_5%
TMDS_PRE
4.7K_0402_5%
DPC_CA_DET
1M_0402_5%
Docking DP2
Q350B
DMN66D0LDW-7_SOT363-6
1
TMDSE_RP_P1
TMDSE_RP_N1
25
24
Q351B
DMN66D0LDW-7_SOT363-6
TMDSE_RP_N0
TMDSE_RP_P0
TMDSE_RP_N0
22
21
R2162
4.7K_0402_5%
2
2
C1333
0.01U_0402_16V7K
1
+3.3V_RUN
R2161
4.7K_0402_5%
5
DPC_CA_DET
EMC@ L23
4
DP_CFG1
19
18
2
TMDS_RT
<48>
<48>
DPC_DOCK_SW _AUX
DPC_DOCK_SW _AUX#
DPC_GPU_HPD
<48>
DPC_CA_DET
29
1
TMDSE_CON_CLK
0_0402_5%
@ R453
4
DPC_CA_DET
2
2
1
2
2
@ R452
TMDSE_RP_P0
42
<48>
<48>
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
1
6
1
2
6
1
2
2
TMDSE_CON_CLK#
3
1
3
DLW21HN900HQ2L_4P
1
DPC_DOCK_SW _AUX
DPC_DOCK_SW _AUX#
DPC_GPU_HPD
<48>
<48>
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
Q350A
DMN66D0LDW-7_SOT363-6
3
1
55
54
32
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
R2156
4.7K_0402_5%
4
DMN66D0LDW-7_SOT363-6
Q352B
1
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
Q351A
DMN66D0LDW-7_SOT363-6
0_0402_5%
EMC@ L19
2
DPC_DOCK_AUX_Q
DMN66D0LDW-7_SOT363-6
Q352A
R2163
100K_0402_5%
2
@ R451
TMDSE_RP_CLK
31
30
+3.3V_RUN
R2155
4.7K_0402_5%
+3.3V_RUN
R2188
100K_0402_5%
For Control Switching:
SW = L: DP output is selected
SW = H: TMDS output is selected
4
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
Difference with Diesel
R78
S
+5V_RUN
TMDSE_RP_CLK#
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
34
33
<48>
<48>
CIS LINK OK
DOCK DPC (PORT2) DDC
1
37
36
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
1
PS8339BQFN56GTR2-A0_QFN56_7X7
DMN65D8LW -7_SOT323-3
Q328
3
TMDS_SCL
TMDS_SDA
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
2
2
C87
2.2U_0402_6.3V6M
R87
4.99K_0402_1%
1
CEXT
46
2
G
DOCKED
8
PEQ
REXT3
DOCKED#
<39,50>
2
TMDS_DDCBUF
R521
10K_0402_5%
1
+3.3V_RUN
CEXT
40
39
2
1
Compal Electronics, Inc.
Title
HDMI CONN
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
38
of
67
5
4
3
@ R546
TP_LAN_JTAG_TMS
10K_0402_5%
TP_LAN_JTAG_TCK
10K_0402_5%
U31
+3.3V_LAN
<18,20>
<19>
2
1
@ R559
D
LAN_WAKE#_R
4.7K_0402_5%
<20> CLK_PCIE_LAN
<20> CLK_PCIE_LAN#
<22> PCIE_PRX_GLANTX_P3
R549
10K_0402_5%
PCIE_PTX_GLANRX_P3
PCIE_PTX_GLANRX_N3
38
39
41
42
28
31
<21> LAN_SMBCLK
<21> LAN_SMBDATA
@
SMBus Device Address 0xC8
<23,51>
2
1
<22>
<22>
44
45
LAN_WAKE#
<50>
@ R556 1
LAN_DISABLE#_R
2 0_0402_5%
LAN_WAKE#_R
LAN_DISABLE#_R
2
3
CLK_REQ_N
PE_RST_N
MDI_PLUS0
MDI_MINUS0
PE_CLKP
PE_CLKN
MDI_PLUS1
MDI_MINUS1
PETp
PETn
PERp
PERn
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SMB_CLK
SMB_DATA
SVR_EN_N
RSVD_VCC3P3_1
LANWAKE_N
LAN_DISABLE_N
VDD3P3_IN
VDD3P3_4
2 0_0402_5%
2
@ T142
@ T143
PAD~D
PAD~D
2
0_0402_5%
GND GND
1
2
1
2
1
2
2
2
12
1 4.7K_0402_5%
R554 2
1 4.7K_0402_5%
VCT_LAN_R1
1
+RSVD_VCC3P3_2
VDD0P9_43
VDD0P9_11
XTAL_OUT
XTAL_IN
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
4
+3.3V_LAN_OUT
15
19
29
@ R209 1
1
47
46
37
+0.9V_LAN
2 0_0603_1%
CTRL0P9
VSS_EPAD
2
+3.3V_LAN
Place C462, C463 and L29 close to U31
+0.9V_LAN
+3.3V_LAN
43
11
1
40
22
16
8
2
TEST_EN
RBIAS
1
5
2
VDD0P9_47
VDD0P9_46
VDD0P9_37
2
+3.3V_LAN
7
1
2
1
2
1
2
1
2
1
2
REGCTL_PNP10
1
2
C
Intel request.
49
WGI218LM-QQ89-B0_QFN48_6X6~D
Note: +1.0V_LAN will work at 0.95V to 1.15V
C471
27P_0402_50V8J
C470
22P_0402_50V8J
4
30
RES_BIAS
R562
3.01K_0402_1%
Y3
25MHZ_18PF_X3G025000DI1H-H
3
1
OUT
IN
R561
1K_0402_1%
XTALI
1
LAN_TEST_EN
XTALO
@ R553 2
6
1
C1178
22U_0805_6.3V6M
1
@ R1144
C
2 0_0402_5%
C1418
0.1U_0402_10V7K
XTALO_R
9
10
Idc min=500mA
DCR=100m ohm
@ R558 1
C1177
22U_0805_6.3V6M
XTALO
XTALI
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
LAN_TX3+
LAN_TX3-
D
C469
0.1U_0402_10V7K
32
34
33
35
VDD3P3_15
VDD3P3_19
VDD3P3_29
23
24
+0.9V_LAN
L29
1
2
REGCTL_PNP10
4.7UH_BRC2012T4R7MD_20%
C468
0.1U_0402_10V7K
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
LED0
LED1
LED2
LAN_TX2+
LAN_TX2-
C467
0.1U_0402_10V7K
26
27
25
LAN_TX1+
LAN_TX1-
20
21
C466
0.1U_0402_10V7K
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
LED
@ R557
10K_0402_5%
1
LAN_DISABLE#_R
JTAG
@ R555 1
PM_LANPHY_ENABLE
LAN_TX0+
LAN_TX0-
17
18
C464
1U_0603_10V7K
<23>
13
14
C463
0.1U_0402_10V7K
+3.3V_LAN
PCIE_PRX_GLANTX_N3
2
C458
2
C459
1
C460
1
C461
CLK_PCIE_LAN
CLK_PCIE_LAN#
1 PCIE_PRX_GLANTX_P3_C
0.1U_0402_10V7K
1 PCIE_PRX_GLANTX_N3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_P3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_N3_C
0.1U_0402_10V7K
C462
10U_0603_6.3V6M
<22>
48
36
LANCLK_REQ#
PLTRST_LAN#
MDI
2
PCIE
2
1
SMBUS
1
1
Difference with Diesel
+3.3V_LAN
@ R545
2
Place C1178 close to pin5
+3.3V_LAN Source
+3.3V_ALW_PCH Source
+3.3V_LAN_PWR
U63
+3.3V_ALW
<19,51>
SIO_SLP_LAN#
+5V_ALW
<51>
3
4
5
6
7
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
14
13
10
+3.3V_ALW_PCH_PWR
9
8
15
2
1
LAN_TX1+
LAN_TX0LAN_TX0+
<38,50>
6
1
L67
1
L68
2
LAN_TX1-R
12NH_0603CS-120EJTS_5%
2
LAN_TX1+R
12NH_0603CS-120EJTS_5%
9
1
L69
1
L70
2
LAN_TX0-R
12NH_0603CS-120EJTS_5%
2
LAN_TX0+R
12NH_0603CS-120EJTS_5%
7
10
11
12
13
DOCKED
43
FROM NIC
DOCKED
A1+
A1-
B3+
B3-
A2+
A2-
LEDB0
LEDB1
LEDB2
A3+
C0+
C0-
A3-
C1+
C1-
SEL
C2+
C2-
LEDA0
LEDA1
LEDA2
C3+
C3LEDC0
LEDC1
LEDC2
PD
SW_LAN_TX2SW_LAN_TX2+
B
29
28
SW_LAN_TX1SW_LAN_TX1+
25
24
SW_LAN_TX0SW_LAN_TX0+
17
18
41
LAN_ACTLED_YEL#
LED_100_ORG#
LED_10_GRN#
36
35
DOCK_LOM_TRD3DOCK_LOM_TRD3+
32
31
DOCK_LOM_TRD2DOCK_LOM_TRD2+
27
26
DOCK_LOM_TRD1DOCK_LOM_TRD1+
23
22
DOCK_LOM_TRD0DOCK_LOM_TRD0+
19
20
40
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
SW_LAN_TX3- <40>
SW_LAN_TX3+ <40>
+3.3V_LAN
SW_LAN_TX2- <40>
SW_LAN_TX2+ <40>
@ C478
1
2
SW_LAN_TX1- <40>
SW_LAN_TX1+ <40>
SW_LAN_TX0- <40>
SW_LAN_TX0+ <40>
DOCK_LOM_TRD3DOCK_LOM_TRD3+
<48>
<48>
DOCK_LOM_TRD2DOCK_LOM_TRD2+
<48>
<48>
DOCK_LOM_TRD1DOCK_LOM_TRD1+
<48>
<48>
DOCK_LOM_TRD0DOCK_LOM_TRD0+
<48>
<48>
Q325A
DMN66D0LDW-7_SOT363-6
1
6
LAN_ACTLED_YEL#
LAN_ACTLED_YEL#_Q
LOM_SPD100LED_ORG#
1
LOM_SPD10LED_GRN#
2
0.1U_0402_10V7K
B
A
O
<40>
SYS_LED_MASK#
TO DOCK
LED_100_ORG#
DOCK_LOM_ACTLED_YEL#
<48>
DOCK_LOM_SPD100LED_ORG#
<48>
DOCK_LOM_SPD10LED_GRN#
<48>
SYS_LED_MASK#
4
WLAN_LAN_DISBL#
<50>
U15
TC7SH08FU_SSOP5~D
<50,52>
Q327
L2N7002WT1G_SC-70-3
Q325B
DMN66D0LDW-7_SOT363-6
4
3
LED_100_ORG#_Q
<40>
LED_10_GRN#
3
1
LED_10_GRN#_Q
<40>
A
SYS_LED_MASK#
SYS_LED_MASK#
PAD_GND
1: TO DOCK
0: TO RJ45
DELL CONFIDENTIAL/PROPRIETARY
PI3L720ZHEX_TQFN42_9X3P5~D
Compal Electronics, Inc.
CIS LINK OK
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
1
G
5
1
D
A
15
16
42
B2+
B2-
SW_LAN_TX3SW_LAN_TX3+
34
33
S
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
A0-
38
37
5
2
LAN_TX2-R
12NH_0603CS-120EJTS_5%
2
LAN_TX2+R
12NH_0603CS-120EJTS_5%
B1+
B1-
P
1
L65
1
L66
B0+
B0-
A0+
G
LAN_TX1-
3
3
LAN_TX2+
2
2
2
JUMP_43X79
2
LAN_TX2-
2
LAN_TX3-R
12NH_0603CS-120EJTS_5%
2
LAN_TX3+R
12NH_0603CS-120EJTS_5%
1
1
2
LAN_TX3+
1
L63
1
L64
5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U32
LAN_TX3-
2
39
30
21
14
8
4
1
2
+3.3V_ALW_PCH
@ PJP95
2
C421
10U_0603_6.3V6M
1
1
1
Intel request: Remove 10uF
11
C474
0.1U_0402_25V6K
2
C473
0.1U_0402_25V6K
2
C472
0.1U_0402_25V6K
Layout Notice : Place bead as
close PI3L720 as possible
1
2
JUMP_43X79
12
TPS22966DPUR_SON14_2X3~D
1
2
+3.3V_LAN_PWR
C547
470P_0402_50V7K
GPAD
B
+3.3V_LAN
@ PJP93
VIN1
VIN1
C422
470P_0402_50V7K
LAN ANALOG SWITCH
+3.3V_LAN
PCH_ALW_ON
+3.3V_ALW
1
2
4
3
2
Title
LAN/LAN SW
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
39
of
67
5
4
3
2
1
+3.3V_LAN/+3.3V_LAN_LOM:20mils
+3.3V_LAN
D
D
For IEEE EA request
1
@ R575
1
@ R576
1
NB_LAN_TX1+
@ R577
1
NB_LAN_TX1@ R578
NB_LAN_TX0+
NB_LAN_TX0-
change TAIMAG to be main source
<39>
SW_LAN_TX0+
<39>
SW_LAN_TX0-
SW_LAN_TX0-
1
2
NB_LAN_TX0+_R
JLOM1
NB_LAN_TX0-_R
<39>
LAN_ACTLED_YEL#_Q
1
R1171
1:1
TD1+
TX1+
TD1TX1-
24
3
+TRM_CT2
23
NB_LAN_TX0-
22
Z2805
SW_LAN_TX1+
4
5
TDCT2
TD2+
1:1
TXCT2
TX2+
NB_LAN_TX1-_R
7
NB_LAN_TX1-_R
6
NB_LAN_TX2-
5
NB_LAN_TX2+
4
NB_LAN_TX1+_R
3
NB_LAN_TX0-_R
2
NB_LAN_TX0+_R
1
PR4PR4+
PR2PR3-
<39>
LED_10_GRN#_Q
1
R1170
2
150_0402_5%
10
<39>
LED_100_ORG#_Q
1
R1167
2
150_0402_5%
11
PR3+
PR2+
SHLD2
PR1+
SHLD1
15
C
14
Green_LED-
9
Z2807
NB_LAN_TX1+
PR1-
LED+
ORANGE_LED-
SW_LAN_TX3-
12
TXCT3
16
Z2806
15
14
Z2808
NB_LAN_TX3+
TDCT4
TD4+
1:1
TD4-
TXCT4
TX4+
TX4-
13
1
2
1
2
B
NB_LAN_TX3-
75_0402_1%
SW_LAN_TX3-
TDCT3
75_0402_1%
<39>
SW_LAN_TX3+
NB_LAN_TX2-
1
SW_LAN_TX3+
17
1
R574 2
<39>
NB_LAN_TX2+
75_0402_1%
9
18
2
TD3-
LInk CIS
+3.3V_LAN
1
8
TX3+
NB_LAN_TX1-
R573 2
SW_LAN_TX2-
1:1
TD3+
19
75_0402_1%
SW_LAN_TX2-
7
TX2-
1
<39>
SW_LAN_TX2+
TD2-
1
SW_LAN_TX2+
6
C1167
470P_0402_50V7K
<39>
SW_LAN_TX1-
10
11
2
NB_LAN_TX3+
Yellow_LED+
C483
0.1U_0402_10V7K
SW_LAN_TX1-
+TRM_CT4
1
8
C481
1U_0603_10V6K
<39>
+TRM_CT3
C486
0.47U_0603_10V7K
2
C484
0.47U_0603_10V7K
1
NB_LAN_TX3-
SANTA_130454-H
CONN@
TX3B
21
20
R572 2
2
SW_LAN_TX1+
TXCT1
Yellow_LED-
NB_LAN_TX0+
R571 2
1
C480
0.47U_0603_10V7K
2
C479
0.47U_0603_10V7K
1
<39>
TDCT1
13
12
C
+TRM_CT1
2
150_0402_5%
NB_LAN_TX1+_R
Placement close to T156
T156
SW_LAN_TX0+
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
Close to JLOM1
350uH_IH-115-F
1
EMC@ C485
2
GND_CHASSIS
150P_1808_3KV8J
A
DELL CONFIDENTIAL/PROPRIETARY
GND CHASSIS
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
RJ45
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
40
of
67
A
5
4
3
2
1
Difference with Diesel
D
D
+3.3V_SUS
1
2
USH_SMBCLK
2.2K_0402_5%
2
USH_SMBDAT
2.2K_0402_5%
RZ8
1
RZ9
1
Difference with Diesel
JUSH1
<22>
<22>
2
USH_PWR_STATE#
1M_0402_5%
RZ10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
USBP7USBP7+
<51> USH_SMBCLK
<51> USH_SMBDAT
<50> BCM5882_ALERT#
+3.3V_SUS
PJP@
PJP11
SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R
25
18
11
4
1
1
2
B
@EMC@
@EMC@
CZ9
RZ35
0.1U_0402_25V6
33_0402_5%
2
SPI_CLKTPM
MISO
MOSI
SPI_CLK
SPI_CS#
SPI_RST#
PIRQ#
GPIO_1
GPIO_2
GPIO_3
GPIO-Express-00
PP/GPIO
GND
GND
GND
GND
TESTBI
TESTI
NBO_1
NBO_2
NBO_3
NBO_4
NBO_5
NBO_6
1
2
17
6
7
@
1
2
@
@
1
V_BAT
2
1
2
1
1
2
2
2
PCH_PLTRST#_EC
<23> TPM_PIRQ#
26
23
21
22
16
20
VCC
VCC
VCC
VCC
12
<23>
1
Close to JUSH1
2
9
8
5
13
14
15
27
28
USH_DET#
2
4
6
8
10
12
14
16
18
20
G1
G2
G3
G4
PLTRST_USH#
CZ57
0.047U_0402_16V4Z
3
10
19
24
+3.3V_RUN
+5V_RUN
<19> PLTRST_USH#
<50> USH_PWR_STATE#
<23> CONTACTLESS_DET#
+3.3V_SUS
CZ12
0.1U_0402_25V6
UZ1
+3.3V_RUN
CZ11
0.1U_0402_25V6
33_0402_5%
33_0402_5%
33_0402_5%
0_0402_5%
+5V_RUN
CZ10
0.1U_0402_25V6
<19,42,43,50,51>
2
2
2
2
+3.3V_M_TPM
2
PAD-OPEN1x1m
CZ7
2200P_0402_50V7K
1
1
1
1
CZ6
2200P_0402_50V7K
<21> PCH_SPI_DIN
<21> PCH_SPI_DO
<21> PCH_SPI_CLK
<21> PCH_SPI_CS2#
RZ30
RZ29
RZ26
RZ17
CZ5
4700P_0402_25V7K
C
@ CZ4
0.1U_0402_25V6
1
1
1
+3.3V_M_TPM
2
+3.3V_M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C
21
22
23
24
ACES_50559-02001-001
CONN@
ESD request
CIS link OK
Check ME about wire to board PN
JAPS1
+3.3V_ALW_PCH
SIO_SLP_S3#
+PCH_VCCDSW3_3
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
+PCH_VCCDSW3_3
<19,32,51,54>
<19,32,51>
<19,51,54,57>
<19,51,54,58>
AT97SC3205_TSSOP28~D
<18>
<49,51>
PCH_RTCRST#
POWER_SW#_MB
<19>
SYS_RESET#
15: SIO_SLP_S0# for MCP only
Intel Management Engine Test Suite
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
B
CONN@
ACES_50506-01841-P01
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
TPM/USH
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
41
of
67
5
4
3
2
1
WLAN/BT/WiGig
NGFF slot_1 Key A
+3.3V_WLAN
JNGFF1
PCIE_PTX_WLANRX_P7
PCIE_PTX_WLANRX_N7
1
1
CV5
CV7
<37> WIGIG_HPD
2 0.1U_0402_10V7K
PCIE_PTX_WLANRX_P7_C
2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N7_C
CZ3 1
CZ58 1
<22>
<22>
PCIE_PRX_WLANTX_P7
PCIE_PRX_WLANTX_N7
<20>
<20>
<22>
<22>
PCIE_PTX_WIGIGRX_P8
PCIE_PTX_WIGIGRX_N8
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
<20> WLANCLK_REQ#
PCIE_WAKE#
<17,32,50> PCIE_WAKE#
2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_P8_C
CZ59 1
2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_N8_C
CZ60 1
<22>
<22>
PCIE_PRX_WIGIGTX_P8
PCIE_PRX_WIGIGTX_N8
69
GND
GND
BT_LED#
WIGIG_AUX#_C
WIGIG_AUX_C
0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N1_C
WIGIG_LANE_P1_C
0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N0_C
WIGIG_LANE_P0_C
0.1U_0402_25V6
0.1U_0402_25V6
2
2
2
2
2
2
1
1CV3
CV4
1
1CV6
CV8
1
1CV9
CV10
WLAN_WIGIG60GHZ_DIS#_R
RB751S40T1G_SOD523-2
2
BT_RADIO_DIS#_R
RB751S40T1G_SOD523-2
2
1
WLAN_WIGIG60GHZ_DIS#
D31
<50>
WIGIG_AUX# <37>
WIGIG_AUX <37>
WIGIG_LANE_N1
WIGIG_LANE_P1
<37>
<37>
WIGIG_LANE_N0
WIGIG_LANE_P0
<37>
<37>
1
BT_RADIO_DIS#
D36
<50>
PCH_CL_RST1# <21>
PCH_CL_DATA1 <21>
PCH_CL_CLK1 <21>
SUSCLK <19,42,43>
PCH_PLTRST#_EC
PCH_PLTRST#_EC <19,41,43,50,51>
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
+3.3V_WLAN
PCH_PLTRST#_EC
WIGIGCLK_REQ#
PCIE_WAKE#
<20>
68
R705
100K_0402_5%
CLK_PCIE_WIGIG
CLK_PCIE_WIGIG#
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
R718
100K_0402_5%
<20>
<20>
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
D
WLAN_LED#
5
WIGIG_LANE_N2
WIGIG_LANE_P2
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
2
WIGIG_LANE_N3_C
2 0.1U_0402_25V6 WIGIG_LANE_P3_C
0.1U_0402_25V6
2
WIGIG_LANE_N2_C
2 0.1U_0402_25V6 WIGIG_LANE_P2_C
0.1U_0402_25V6
2
4
6
2
<37>
<37>
1
1
CV1
CV2
2
4
6
2
WIGIG_LANE_N3
WIGIG_LANE_P3
1
3
5
7
1
<22>
<22>
<37>
<37>
1
3
5
7
USBP4+
USBP4-
1
<22>
<22>
D
4
BT_LED#
2
FOX_AS0BC21-S48BA-7H
CONN@
CIS link OK
WLAN_LED#
3
WIRELESS_LED#
<50,52>
Q124B
DMN66D0LDW-7_SOT363-6
1
6
Q124A
DMN66D0LDW-7_SOT363-6
+3.3V_WLAN
C
2
1
+
2
C1402
330U_D2E_6.3VM_R25
1
1
C608
4.7U_0603_6.3V6K
1
2
C607
0.1U_0402_25V6K
2
2
C606
0.1U_0402_25V6K
2
1
C605
0.047U_0402_16V4Z
1
C604
0.047U_0402_16V4Z
2
@ C603
0.1U_0402_25V6K
1
C
WWAN/LTE/HCA/Cache
+3.3V_WWAN
2 WWAN_PWR_EN
0_0402_5%
NGFF slot_2 Key B
2
WWAN_RADIO_DIS#_R
1
WWAN_RADIO_DIS#
<50>
DZ1
RB751S40T1G_SOD523-2
+3.3V_WWAN
SIM Card Push-Push
JNGFF2
1
3
5
7
9
11
NGFF_CONFIG_3
<22>
<22>
USBP5+
USBP5-
1
3
5
7
9
11
2
4
6
8
10
2
4
6
8
10
WWAN_PWR_EN
WWAN_RADIO_DIS#_R
WWAN_LED#
2
HW_GPS_DISABLE#_R
1
HW_GPS_DISABLE#
JSIM1
<50>
2
DZ2
RB751S40T1G_SOD523-2
4
UIM_DATA
6
69
GND
GND
18
+3.3V_WWAN
VCC
GND
GND
GND
GND
GND
GND
GND
GND
B
3
5
UIM_CLK
7
UIM_RESET
+SIM_PWR
9
11
13
15
17
T-SOL_159-1000302602
CONN@
CIS link OK
PCH_PLTRST#_EC
PCIE_WAKE#
RST
NC
1
NGFF2_CLK_REQ#
<20>
SUSCLK
WWAN_LED#
<19,42,43>
3
1
WIRELESS_LED#
D
NGFF_CONFIG_2
16
S
NGFF_CONFIG_1
<50>
14
+SIM_PWR
GND
CLK
G
<50>
UIM_RESET
UIM_CLK
UIM_DATA
NC
VPP
2
CLK_PCIE_NGFF2#
CLK_PCIE_NGFF2
12
2
<20>
<20>
8
10
HW_GPS_DISABLE#_R
1
PCIE_PTX_SATARX_N4
PCIE_PTX_SATARX_P4
PCIE_PRX_SATATX_P4
PCIE_PRX_SATATX_N4
2 0.1U_0402_10V7K PCIE_PTX_SATARX_N4_C
2 0.1U_0402_10V7K PCIE_PTX_SATARX_P4_C
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
DETECT
I/O
C1356
1U_0402_6.3V6K
<18>
<18>
<18>
<18>
CZ1 1
CZ2 1
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
R719
100K_0402_5%
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
<50> NGFF_CONFIG_0
<50> WWAN_WAKE#
NC
1
<50>
B
2
1
RZ3
Q77
DMN65D8LW-7_SOT323-3
UIM_RESET
68
UIM_CLK
UIM_DATA
0
Module Type
SSD-SATA
8
1
0
0
0
WWAN
14
1
0
1
1
HCA-PCIE
15
1
1
1
1
1
0
2
CONFIG_3
0
1
CONFIG_2
0
2
CONFIG_1
0
2
STATE # CONFIG_0
+3.3V_WWAN
@EMC@ CZ67
33P_0402_50V8J
CIS link OK
@EMC@ CZ66
33P_0402_50V8J
@EMC@ CZ65
33P_0402_50V8J
CONN@
1
FOX_AS0BC21-S48BB-7H
A
2
2
C613 change to 0603
due to height limitation.
+
2
1
+
2
@ C1176
330U_D2E_6.3VM_R25
1
1
EMC@ C615
330U_D2E_6.3VM_R25~D
2
EMC@ C613
22U_0603_6.3V6M
1
EMC@ C614
33P_0402_50V8J
2
EMC@ C612
33P_0402_50V8J
1
EMC@ C611
0.047U_0402_16V4Z
2
EMC@ C610
0.047U_0402_16V4Z
1
1
A
For RF Team request
NA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C615 footprint change to C_APXK2R5ARA331MF451
5
4
3
2
Title
M.2 Card-1/2
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
42
of
67
5
4
3
2
1
D
D
SSD/HCA/Cache
NGFF slot_3 Key B
+3.3V_SSD
JNGFF3
<22>
<22>
<50>
1
3
5
7
9
11
USBP10+
USBP10-
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
SLOT3_CONFIG_0
C
<18>
<18>
PCIE_PTX_SATARX_N5
PCIE_PTX_SATARX_P5
<18>
<18>
CZ61 1
CZ13 1
<20>
<20>
PCIE_PRX_SATATX_P5
PCIE_PRX_SATATX_N5
2 0.1U_0402_10V7K PCIE_PTX_SATARX_N5_C
2 0.1U_0402_10V7K PCIE_PTX_SATARX_P5_C
CLK_PCIE_NGFF3#
CLK_PCIE_NGFF3
69
1
3
5
7
9
11
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
C
PCH_PLTRST#_EC
NGFF3_CLK_REQ#
SUSCLK
<19,41,42,50,51>
<20>
<19,42>
68
FOX_AS0BC21-S48BB-7H
CONN@
CIS link OK
B
Module Type
1
2
1
2
1
2
1
2
1
2
1
+
2
C619
330U_V_6.3VM
HCA-PCIE
C617
33P_0402_50V8J
1
C622
22U_0805_6.3VAM
14
B
+3.3V_SSD
C618
33P_0402_50V8J
SSD-SATA
C621
0.047U_0402_16V4Z
0
C623
0.047U_0402_16V4Z
0
@
STATE # CONFIG_0
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
M.2 Card-2/2
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
Rev
0.1
43
of
67
5
4
3
2
1
D
D
Power Control for M.2 slot 1.
& +3.3V_RUN Source
Power Control for M.2 slot 2.
+3.3V_WLAN_PWR
U42
3
AUX_EN_WOWL_R
1
0_0402_5%
2
5
6
7
+3.3V_ALW
ON1
VBIAS
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
12
1
11
2
10
9
8
1
0_0402_5%
2
RZ51
@ CZ87
100P_0402_50V8J
2
C
1
1
3
3.3V_WWAN_EN
2
1
ON
1
+3.3V_RUN_PWR
+3.3V_RUN
@ PJP91
2
+3.3V_RUN_PWR
2
1
1
1
2
2
4
+5V_ALW
1
2
2
VIN
VOUT
VIN
VOUT
VBIAS
6
C541
470P_0402_50V7K
RUN_ON
<50>
C538
470P_0402_50V7K
15
TPS22966DPUR_SON14_2X3~D
<51,54>
+3.3V_WWAN
U43
JUMP_43X79
C436
3300P_0402_50V7-K
GPAD
1
C450
10U_0603_6.3V6M
2
0_0402_5%
4
+5V_ALW
2
JUMP_43X79
8
1
2
5
9
GND
GND
CT
7
C762
10U_0603_6.3V6M
1
@ R820
2
+3.3V_ALW
1
R720
100K_0402_5%
SIO_SLP_WLAN#
1
@ R840
R723
100K_0402_5%
<19,50>
AUX_EN_WOWL
VOUT1
VOUT1
C536
10U_0603_6.3V6M
<50>
VIN1
VIN1
2
+3.3V_WLAN_PWR
1
+3.3V_ALW
Difference with Diesel
+3.3V_WLAN
@PJP99
@
PJP99
14
13
2
1
2
TPS22965DSGR_SON8_2X2~D
C
Power Control for M.2 slot 3.
& +5V_MXM Source
+5V_MXM_PWR
+5V_MXM
U49
B
+5V_ALW
3.3V_RUN_GFX_ON
+5V_ALW
5
6
7
ON1
VBIAS
ON2
CT2
VOUT2
VOUT2
@ PJP98
2
+5V_MXM_PWR
1
12
11
2
10
9
8
15
GPAD
TPS22966DPUR_SON14_2X3~D
2
1
B
1
JUMP_43X79
+3.3V_SSD_PWR
+3.3V_SSD
@PJP97
@
PJP97
2
+3.3V_SSD_PWR
2
1
1
C764
10U_0603_6.3V6M
VIN2
VIN2
CT1
GND
14
13
JUMP_43X79
2
1
2
1
C437
470P_0402_50V7K
2
+3.3V_ALW
4
VOUT1
VOUT1
C542
470P_0402_50V7K
R739
100K_0402_5%
1
NVRAM_PWR_EN
@
<50>
NVRAM_PWR_EN
3
VIN1
VIN1
C357
10U_0603_6.3V6M
<20,50,54>
1
2
1
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
M.2 Card PWR
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
44
of
67
5
4
3
2
1
D
D
+3.3V_RUN
+3.3V_RUN
1
Free Fall Sensor
1
R502
1
R503
1
R504
1
2
1
2
C391
0.1U_0402_25V6K
R501
C392
10U_0603_6.3V6M
2 DDR_XDP_WAN_SMBDAT
10K_0402_5%
2 DDR_XDP_WAN_SMBCLK
10K_0402_5%
2 HDD_FALL_INT
100K_0402_5%
2 FFS_INT2
100K_0402_5%
U88
LNG3DM
1
14
<19>
<13,14,15,16,18,21>
<13,14,15,16,18,21>
HDD_FALL_INT
11
9
HDD_FALL_INT
FFS_INT2
INT 1
INT 2
GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC
7
6
4
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
RES
RES
RES
RES
VDD_IO
VDD
8
HDD PWR
10
13
15
16
+5V_HDD
PJP@
PJP3
5
12
1
1
+5V_RUN
2
2
JUMP_43X79
2
3
SHORT DEFAULT
LNG3DMTR_LGA16_3X3~D
CIS LINK OK
C
C
HDD2 CONN
HDD1 CONN
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
1
HDD1_DET#
+5V_HDD
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PTX_DRX_P3
SATA_PTX_DRX_N3
C414
C412
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_DTX_N3
SATA_PRX_DTX_P3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
@ R1636
<18,23>
HDD2_DET#
2
0_0402_5%
HDD2_DET#
+5V_HDD
+3.3V_RUN
GND1
GND2
23
24
1
2
OCTEK_SAT-22PDAB
CONN@
1
2
LInk CIS
Main SATA +5V Default
C5 change to 0603
due to height limitation.
FFS_INT2_Q
+5V_HDD
Pleace near HDD2 CONN
1
2
1
2
C415
0.1U_0402_25V6K
2
1
2
2
1
C409
1000P_0402_50V7K
Pleace near HDD1 CONN
2
1
C5
10U_0603_6.3V6M
2
1
C406
0.1U_0402_25V6K
2
1
C395
1000P_0402_50V7K
1
FFS_INT2_Q
+5V_HDD
SATA_PRX_DTX_N3_C
SATA_PRX_DTX_P3_C
C498
22U_0603_6.3V6M
+3.3V_RUN
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
<18>
<18>
C413
C411
+3.3V_RUN
@ C407
0.1U_0402_25V6K
4
2
0_0402_5%
HDD1_DET#
@ R1635
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SATA_PTX_DRX_P3_C
SATA_PTX_DRX_N3_C
1
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
GND
RX+
RXGND
TXTX+
GND
<18>
<18>
2
1
2
3
1
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
C385 2
C386 2
1
2
3
4
5
6
7
@ C408
0.1U_0402_25V6K
6
C383 2
C384 2
<18>
@ C403
0.1U_0402_25V6K
1
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
@ C404
0.1U_0402_25V6K
FFS_INT2
Q29A
DMN66D0LDW-7_SOT363-6
<23>
SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
<18>
<18>
FFS_INT2_Q
Q29B
DMN66D0LDW-7_SOT363-6
2
R513
100K_0402_5%
B
<18>
<18>
+3.3V_RUN
5
2
@ R506
100K_0402_5%
+3.3V_RUN
JSATA2
JSATA1
+5V_HDD
GND
RX+
RXGND
TXTX+
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
GND1
GND2
23
24
OCTEK_SAT-22PDAB
CONN@
B
LInk CIS
Main SATA +5V Default
C498 change to 0603
due to height limitation.
Pleace near HDD2 CONN
Pleace near HDD1 CONN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
HDD CONN
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
45
of
67
5
4
3
2
1
D
D
+3.3V_ALW_PCH
1
R796
1
R520
Combine +5VMOD with +5V_RUN
2
ZODD_WAKE#
10K_0402_5%
2
MOD_MD
10K_0402_5%
C
C
Q81A
DMN66D0LDW-7_SOT363-6
1
6
2
MOD_MD
ZODD_WAKE#
ZODD_WAKE#
<50>
MODC_EN#
ODD CONN
JODD1
+3.3V_ALW
<18>
<18>
SATA_ODD_PRX_DTX_N1_C
SATA_ODD_PRX_DTX_P1_C
2
1
SATA_ODD_PTX_DRX_P1_C
SATA_ODD_PTX_DRX_N1_C
MODC_EN#
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_ODD_PTX_DRX_P1
SATA_ODD_PTX_DRX_N1
C432 2
C430 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_ODD_PRX_DTX_N1
SATA_ODD_PRX_DTX_P1
<50>
DEVICE_DET#
MOD_MD
<50,54>
MODC_EN
MODC_EN
DMN66D0LDW-7_SOT363-6
Q81B
5
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
GND
14
15
B
SANTA_201901-1
CONN@
4
B
1
2
3
4
5
6
7
8
9
10
11
12
13
+5V_MOD
3
R515
100K_0402_5%
<18>
<18>
C433 2
C434 2
CIS link OK
+5V_MOD
1
2
C429
0.1U_0402_16V4Z
2
C428
1000P_0402_50V7K
1
Pleace near ODD CONN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ODD CONN
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
46
of
67
5
4
3
2
1
+5V_USB_PW R1
+5V_ALW
+5V_ALW
Remove TPS2560
UI1
2
1
<22>
RI1
2
D
3
2
G
S
<50>
DMN65D8LW-7_SOT323-3
@ Q55
1
PW RSHARE_EN#
USB_PW R_SHR_VBUS_EN
2
3
<22> USBP1<22> USBP1+
+5V_ALW
1
100K_0402_5%
@ R816
D
13
USB_OC0#
1
4
ILIM_SEL
10K_0402_5%
5
USB_PW R_SHR_VBUS_EN
<51>
6
7
8
USB_PW R_SHR_EN#
IN
12
OUT
DM_OUT
DP_OUT
DP_IN
DM_IN
FAULT#
D
10
11
USBP1_D+
USBP1_D-
15
16
RI2
ILIM_SEL
EN
ILIM_LO
ILIM_HI
CTL1
CTL2
CTL3
NC
GND
GNDP
2
1
22.1K_0402_1%
Remove SLG55594
9
14
17
TPS2544RTER_W QFN16_3X3
OC[3:0]# for Device 29 (Port 0 - 7)
OC[7:4]# for Device 26 (Port 8 - 13)
@ R3687 1
2 0_0402_5%
@ Q348
DMG2301U-7_SOT23-3
2
@ R3690
1
2
@ R3691
1
2
@ R3692
1
2
@ R3693
1
2
@ R3694
1
2
@ R3695
1
2
@ R3696
Difference with Diesel
S
D
1
SHORT DEFAULT
1
2
1
2
Reserve for USB3 reconnect issue from S3 to S0
PW RSHARE_EN#
C
LInk CIS ok
U632
1
13
<22>
<22>
USB3TP2
USB3TN2
C1374 2
C1376 2
15
16
17
18
USB3TP2_C
USB3TN2_C
19
20
USB3RP2_RP_R
USB3RN2_RP_R
9
8
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2
2 0_0402_5%
0_0402_5%
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
A_INp
A_INn
A_OUTp
A_OUTn
B_INp
B_INn
B_OUTp
B_OUTn
4
3
2
6
USB1_B_EQ1
USB1_B_DE0
USB1_B_EQ0
USB1_B_DE1
12
11
USB3TP2_RP_C
USB3TN2_RP_C
C1375 2
C1377 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
22
23
USB3RP2_C
USB3RN2_C
C1378 2
C1379 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
USB3_RX2_N_DUSB3_RX2_P_D+
USB3TP2_RP
USB3TN2_RP
USB3RP2
USB3RN2
USB3_TX2_N_DUSB3_TX2_P_D+
2
2
5
7
14
24
PD#
REXT
TEST
I2C_EN
GND
GND
GPAD
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
10
21
25
+5V_USB_PW R1
USBP1_D-
2
1
USBP1_R_D-
USBP1_D+
3
4
USBP1_R_D+
1
+
2
OCE2012120YZF_4P
1
2
1
2
@ R754
0_0402_5%
@ R764
A_EQ0 A_EQ1 B_EQ0 B_EQ1
0
0
0
0
1
0
1
loss up to 4.5dB
0
1
0
loss up to 13dB
1
1
1
1
loss up to 7.5dB
B
Close to JUSB2
loss up to 9.5dB
1
2
0_0402_5%
Recommended EQ
0
1
C794
10U_0603_6.3V6M
EMC@ L41
Parade_PS8713B
10
11
12
13
CIS link OK
C323
150U_D2_6.3VY_R15M~D
CPN: SA00005OR20
MPN: PS8713BTQFN24GTR2-A1
PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4
B
GND
GND
GND
GND
LOTES_GAP-AUSB0041-P005A
CONN@
<22>
<22>
PS8713BTQFN24GTR2_TQFN24_4X4
1
@
1
1
R3705
0_0402_5%
R3704
4.99K_0402_1%
R3703
2K_0402_5%
2
USB1_TEST
@
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
JUSB1
1
2
3
4
5
6
7
8
9
USBP1_R_DUSBP1_R_D+
EMC@ D17
L30ESDL5V0C3-2_SOT23-3
1
USB3RP2_RP
USB3RN2_RP @ R3697 1
@ R3698
USB1_A_EQ1
USB1_A_DE0
USB1_A_EQ0
USB1_A_DE1
+5V_USB_PW R1
VDD
VDD
2
1
C
2
USB1_A_EQ1
4.7K_0402_5%
USB1_A_DE0
4.7K_0402_5%
USB1_A_EQ0
4.7K_0402_5%
USB1_A_DE1
4.7K_0402_5%
USB1_TEST
4.7K_0402_5%
USB1_B_EQ1
4.7K_0402_5%
USB1_B_DE0
4.7K_0402_5%
USB1_B_EQ0
4.7K_0402_5%
USB1_B_DE1
4.7K_0402_5%
C1373
0.1U_0402_16V4Z
2
C1372
0.01U_0402_16V7K
1
@ R3689
3
3
2
@ R3688
1
+USB1_repeater_VDD
1
1
PJP@
PJP96
PAD-OPEN1x1m
+3.3V_ALW
+3.3V_RUN
2
G
+USB1_repeater_VDD
EMC@ L44
USB3RP2_RP
3
USB3RN2_RP
2
3
4
1
2
1
DLW21HN900HQ2L_4P
1
2
@ R750
0_0402_5%
1
Both A_EQ&B_EQ have internal pull-down 150k
4
USB3_RX2_P_D+
USB3_RX2_N_D-
For ESD request
EMC@ D16
USB3_RX2_N_D-
9
1
USB3_RX2_N_D-
USB3_RX2_P_D+
8
2
USB3_RX2_P_D+
USB3_TX2_N_D-
7
4
USB3_TX2_N_D-
USB3_TX2_P_D+
6
5
USB3_TX2_P_D+
2
@ R751
0_0402_5%
EMC@ L43
USB3TP2_RP
USB3TN2_RP
3
2
3
4
4
3
1
2
1
DLW21HN900HQ2L_4P
A
1
USB3_TX2_N_D-
TVW DF1004AD0_DFN9
A
2
@ R752
0_0402_5%
1
@ R753
USB3_TX2_P_D+
2
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
USB3.0
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
47
of
67
5
4
<39>
<37>
<37>
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
<37>
<37>
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
<37>
<37>
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
<37>
<37>
DPD_GPU_LANE_P3
DPD_GPU_LANE_N3
DOCK_LOM_SPD10LED_GRN#
<37> DPD_CA_DET
C366 2
C367 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPD_DOCK_LANE_P0 EMC@ R2164
DPD_DOCK_LANE_N0 EMC@ R2165
1
1
2 33_0402_5%
2 33_0402_5%
C368 2
C369 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPD_DOCK_LANE_P1 EMC@ R2166
DPD_DOCK_LANE_N1 EMC@ R2167
1
1
2 33_0402_5%
2 33_0402_5%
DPD_DOCK_LANE_P1_R
DPD_DOCK_LANE_N1_R
C424 2
C425 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPD_DOCK_LANE_P2 EMC@ R2168
DPD_DOCK_LANE_N2 EMC@ R2169
1
1
2 33_0402_5%
2 33_0402_5%
DPD_DOCK_LANE_P2_R
DPD_DOCK_LANE_N2_R
C426 2
C427 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPD_DOCK_LANE_P3 EMC@ R2170
DPD_DOCK_LANE_N3 EMC@ R2171
1
1
2 33_0402_5%
2 33_0402_5%
DPD_DOCK_LANE_P3_R
DPD_DOCK_LANE_N3_R
DPD_DOCK_AUX
DPD_DOCK_AUX#
<37> DPD_DOCK_AUX
<37> DPD_DOCK_AUX#
DPD_GPU_HPD
DPD_GPU_HPD
2
Close to DOCK
Its for Enhance ESD on dock issue.
+NBDOCK_DC_IN_SS
@ C695
0.033U_0402_16V7K
1
1
<35>
RED_DOCK
RED_DOCK
GREEN_DOCK
GREEN_DOCK
<35>
<35>
HSYNC_DOCK
VSYNC_DOCK
<51>
<51>
CLK_MSE
DAT_MSE
<49>
<49>
DAI_BCLK#
DAI_LRCK#
<49>
<49>
DAI_DI
DAI_DO#
<49>
DAI_12MHZ#
<50>
<50>
D_LAD0
D_LAD1
<50>
<50>
D_LAD2
D_LAD3
<50> D_SERIRQ
<50> D_DLDRQ1#
<20>
CLK_PCI_DOCK
<30,51> DOCK_LCD_SMBCLK
<30,51> DOCK_LCD_SMBDAT
<50,55>
<51>
<50,55,63>
DOCK_SMB_ALERT#
<55> DOCK_PSID
DOCK_PWR_BTN#
SLICE_BAT_PRES#
2
2
3
@
1
1
153
154
155
156
157
158
GND1
PWR1
PWR1
PWR1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
DOCK_AC_OFF
<63>
DOCK_LOM_SPD100LED_ORG#
DPC_CA_DET
<38>
Dock DPC (Port 2)
<39>
DPC_DOCK_LANE_P0_R EMC@ R2172
DPC_DOCK_LANE_N0_R EMC@ R2173
1
1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_C_P0 0.1U_0402_10V7K
DPC_DOCK_LANE_C_N0 0.1U_0402_10V7K
1
1
2 C431
2 C438
DPC_DOCK_LANE_P1_R EMC@ R2174
DPC_DOCK_LANE_N1_R EMC@ R2175
1
1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_C_P1 0.1U_0402_10V7K
DPC_DOCK_LANE_C_N1 0.1U_0402_10V7K
1
1
2 C439
2 C440
DPC_DOCK_LANE_P2_R EMC@ R2176
DPC_DOCK_LANE_N2_R EMC@ R2177
1
1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_C_P2 0.1U_0402_10V7K
DPC_DOCK_LANE_C_N2 0.1U_0402_10V7K
1
1
2 C441
2 C442
DPC_DOCK_LANE_P3_R EMC@ R2178
DPC_DOCK_LANE_N3_R EMC@ R2179
1
1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_C_P3 0.1U_0402_10V7K
DPC_DOCK_LANE_C_N3 0.1U_0402_10V7K
1
1
2 C443
2 C444
DPC_DOCK_SW_AUX
DPC_DOCK_SW_AUX#
DPC_DOCK_SW_AUX
DPC_DOCK_SW_AUX#
<63>
DAT_DDC2_DOCK
CLK_DDC2_DOCK
1
<35>
<35>
SATA_PRX_DKTX_P2
SATA_PRX_DKTX_N2
C697 2
C698 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PTX_DKRX_P2
SATA_PTX_DKRX_N2
C699 1
C700 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
USBP6+
USBP6-
<22>
<22>
CLK_KBD
DAT_KBD
<51>
<51>
USB3RN3
USB3RP3
<22>
<22>
USB3TN3
USB3TP3
<22>
<22>
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
<38>
<38>
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
<38>
<38>
D
SATA_PRX_DKTX_P2_C
SATA_PRX_DKTX_N2_C
SATA_PTX_DKRX_P2_C
SATA_PTX_DKRX_N2_C
<18>
<18>
2
DPC_GPU_HPD
<38>
Close to DOCK
Its for Enhance ESD on dock issue.
<18>
<18>
DPC_GPU_HPD
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
<39>
<39>
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
<39>
<39>
<39>
+LOM_VCT
1
<39>
<39>
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
<39>
<39>
DOCK_DCIN_IS+
DOCK_DCIN_ISDOCK_POR_RST#
C
audio not transfer to DP display if
play movie when attached external DP display
+LOM_VCT
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
DOCK_DET_R#
<38>
<38>
<22>
<22>
USBP3+
USBP3-
BREATH_LED# <51,52>
DOCK_LOM_ACTLED_YEL#
149
150
151
152
<38>
<38>
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
<38>
<38>
DPC_GPU_HPD
ACAV_DOCK_SRC#
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
2
+3.3V_ALW
DOCK_DET#
10K_0402_5%
2
1
R755
System hangs after hot dock.
<62>
<62>
D32
<51>
RB751S40T1_SOD523-2
1
2
DOCK_DET#
<50>
+DOCK_PWR_BAR
1
159
160
161
162
163
164
2
C703
0.1U_0603_50V7K
2
@CE6
@
CE6
4.7U_0805_25V6-K
1
C702
0.1U_0603_50V7K
B
@D33
@
D33
L30ESD24VC3-2_SOT23-3
+DOCK_PWR_BAR
145
146
147
148
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
@C701
@
C701
1U_0402_6.3V6K
<50> D_LFRAME#
<50> D_CLKRUN#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
100K_0402_5%
R2160
100K_0402_5%
R757
2
BLUE_DOCK
<35>
DPD_GPU_HPD
C
<35>
BLUE_DOCK
CONN@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
@ C696
0.033U_0402_16V7K
<37>
DPD_DOCK_LANE_P0_R
DPD_DOCK_LANE_N0_R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
JDOCK1
DOCK_DET_1
D
1
EMI request add 33ohm for DOCK DVI signals.
2
DPD_CA_DET
1M_0402_5%
R492
2
2
1
3
B
@
JAE_WD2F144WB5R400
CIS LINK OK
1
CLK_PCI_DOCK
1
2
EMC@
CE8
4.7P_0402_50V8C
EMC@
R756
33_0402_5%
2
EMC@
RE12
10_0402_1%
2
2
DAI_BCLK#
1
1
DAI_12MHZ#
EMC@
RE11
10_0402_1%
1
2
EMC@
CE9
4.7P_0402_50V8C
1
2
EMC@
C704
12P_0402_50V8J
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Docking
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
Rev
0.1
48
of
67
5
D
4
3
2
1
Difference with Diesel
D
JIO1
Left Side JUSB1 ----->
Left Side JUSB2----->
<22>
<22>
USB3RN6
USB3RP6
<22>
<22>
USB3TN6
USB3TP6
<22>
<22>
USB3RN5
USB3RP5
<22>
<22>
USB3TN5
USB3TP5
Left Side JUSB3-----> <22>
<22>
USBP0USBP0+
<18> PCH_AZ_CODEC_BITCLK
<18> PCH_AZ_CODEC_SDIN0
<18> PCH_AZ_CODEC_SDOUT
<18> PCH_AZ_CODEC_SYNC
<18> PCH_AZ_CODEC_RST#
<48> DAI_12MHZ#
<50> DOCK_HP_DET
<50> DOCK_MIC_DET
<50> AUD_HP_NB_SENSE
C
<22> PCIE_PRX_MMITX_P4
<22> PCIE_PRX_MMITX_N4
<22> PCIE_PTX_MMIRX_P4
<22> PCIE_PTX_MMIRX_N4
+1.5V_RUN
+5V_ALW
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
CONN@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
Difference with Diesel
WireLess ON/OFF CONN
USBP2USBP2+
<22>
<22>
<----- Left Side JUSB1
USB_OC1# <22>
USB_OC4# <22>
USB_OC2# <18,22>
USB_PWR_EN2# <50>
USBP9USBP9+
<22>
<22>
<----- Left Side JUSB2
USB3RN1
USB3RP1
<22>
<22>
USB3TN1
USB3TP1
<22>
<22>
<----- Left Side JUSB3
DAI_DI <48>
DAI_DO# <48>
DAI_BCLK# <48>
DAI_LRCK# <48>
EN_I2S_NB_CODEC#
<50>
DMIC_CLK <30>
DMIC0 <30>
AUD_NB_MUTE# <50>
BEEP <51>
SPKR <18>
CLK_PCIE_CARD#
CLK_PCIE_CARD
C
<20>
<20>
CARDCLK_REQ#
<18,20>
LID_CL# <50,52>
PLTRST_MMI# <19>
Power Button CONN
94: remove PCIE_WAKE#
Add LID_CL#
JPB1
1
2
3
4
5
6
POWER_SW#_MB
+5V_ALW
+3.3V_ALW
<52>
BREATH_WHITE_LED
+5V_RUN
CONN@
1
2
3
4
5
6
7
8
GND
GND
ACES_50228-0067N-001
+3.3V_RUN
Link CIS OK
B
+RTC_CELL
Power Switch for debug
142
FOX_QTSA1401-7011-9H
Link CIS OK
2
@
1
2
@
+3.3V_ALW
1
2
1
1
2
2
1
@ PWRSW1
@SHORT PADS~D
2
Place on Bottom
C723
0.1U_0402_16V4Z
1
C722
0.1U_0402_16V4Z
@
+3.3V_RUN
C721
0.1U_0402_16V4Z
2
C763
0.1U_0402_16V4Z
1
+5V_ALW
POWER_SW#_MB
@ C759
100P_0402_50V8J
+5V_RUN
<41,51>
@
SW1
POWER_SW#_MB
2
1
4
3
SKRBAAE010_4P
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
IO / PWR Button
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
49
Rev
0.1
of
67
5
4
3
2
1
+3.3V_ALW
1
2 USB_PWR_SHR_VBUS_EN
100K_0402_5%
2
WWAN_RADIO_DIS#
100K_0402_5%
2
CPU_DETECT#
100K_0402_5%
2
SLOT3_CONFIG_0
100K_0402_5%
RE13
1
RE14
1
RE15
+3.3V_ALW
1
R2158
1
R759
1
R773
1
R1125
CIS LINK OK
U46
<35>
<39>
8
7
6
5
NGFF_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_3
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
GPU_PWR_LEVEL
DOCKED
DOCK_DET#
AUD_NB_MUTE#
3.3V_WWAN_EN
LCD_VCC_TEST_EN
WWAN_WAKE#
AUD_HP_NB_SENSE
<38,39> DOCKED
<48> DOCK_DET#
<49> AUD_NB_MUTE#
<44> 3.3V_WWAN_EN
<30> LCD_VCC_TEST_EN
<42> WWAN_WAKE#
<49> AUD_HP_NB_SENSE
Remove SP_TPM_LPC_EN
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
USB_PWR_EN2#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
HW_GPS_DISABLE#
PANEL_BKEN_EC
LCD_TST
PSID_DISABLE#
<49> USB_PWR_EN2#
<49> EN_I2S_NB_CODEC#
<41> USH_PWR_STATE#
<63> EN_DOCK_PWR_BAR
<42> HW_GPS_DISABLE#
<30> PANEL_BKEN_EC
<30> LCD_TST
<55> PSID_DISABLE#
100K_0804_8P4R_5%
+3.3V_RUN
LAN_DISABLE#_R
LAN_DISABLE#_R
<48,55> DOCK_SMB_ALERT#
<30> TOUCH_SCREEN_PD#
<17> GPU_PWR_LEVEL
RP9
1
2
3
4
B52
A49
B53
A50
B54
A51
B55
A52
CRT_SWITCH
CRT_SWITCH
Remove DDR_1.35V_CNTRL1
RP3
C
1
2
3
4
8
7
6
5
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
DGPU_ALERT#
100K_0804_8P4R_5%
2
1
GPU_PWR_LEVEL
100K_0402_5%
R782
Remove DDR_1.35V_CNTRL1
<42>
<41>
ZODD_WAKE#
BCM5882_ALERT#
<46> ZODD_WAKE#
BCM5882_ALERT#
EDID_SELECT#
DGPU_PWROK
VGA_ID
3.3V_RUN_GFX_ON
<35> EDID_SELECT#
<17,23> DGPU_PWROK
<20,44,54>
Remove DYN_TURB_GPU_PWR_ALRT#
3.3V_RUN_GFX_ON
B58: Remove SLP_ME_CSW_DEV#
<39,52>
B
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
@ R800
100K_0402_5%
Remove WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
<42> BT_RADIO_DIS#
<42> WWAN_RADIO_DIS#
<29,30,35>
<19,44>
DGPU_SELECT#
SIO_SLP_WLAN#
GPIOH6
DGPU_SELECT#
SIO_SLP_WLAN#
Remove CPU_VTT_ON
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
GPIOG1
SYS_LED_MASK#
SYS_LED_MASK#
A46: Remove DYN_TURB_GPU_PWR_ALRT#
<42,52> WIRELESS_LED#
<47> USB_PWR_SHR_VBUS_EN
+3.3V_ALW
1
A1
B2
A2
B3
A3
B45
A42
B4
WLAN_WIGIG60GHZ_DIS#
EC5048_TX
WLAN_WIGIG60GHZ_DIS#
<51> EC5048_TX
CPU_DETECT#
<7> CPU_DETECT#
B45: change DGPU_PWR_EN to PCH.
DGPU_ALERT#
<17> DGPU_ALERT#
MXM_DP_HDMI_HPD
<17> MXM_DP_HDMI_HPD
Remove SLICE_BST_CHG_EN
2
B32
A31
B33
B15
A15
B16
A16
NVRAM_PWR_EN
SLICE_BAT_ON
SLICE_BAT_PRES#
TB_STAT#
PBA_GPU_SEL#
<44> NVRAM_PWR_EN
<63> SLICE_BAT_ON
<48,55,63>
SLICE_BAT_PRES#
<62> TB_STAT#
<36> PBA_GPU_SEL#
B13
A13
A53
B57
B14
A14
B17
B18
2
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
BC_INT#
BC_DAT
BC_CLK
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
PWRGD
OUT65
TEST_PIN
CAP_LDO
VGA_ID0
Discrete
0
UMA
1
2
2
VSS
EP
A23
B63
A60
A61
B65
A62
B66
A63
B67
A64
A5
B6
A6
B7
A7
B8
A8
B9
B10
A10
B11
A11
B12
A12
B60
A57
B64
B68
A9
B1
A18
A44
B34
B39
B51
TBT_PWR_EN
TBT_PWR_EN
0.675V_DDR_VTT_ON
DEVICE_DET#
<34>
0.675V_DDR_VTT_ON
DEVICE_DET#
<46>
SATA4_PCIE1#
SATA4_PCIE1#
<57>
<18,23>
Move IMVP_VR_ON from 5048_B66 to 5085_A1
DOCK_AC_OFF_EC
AUX_EN_WOWL
PCH_SATA_MOD_EN#
AUX_EN_WOWL
PCH_SATA_MOD_EN#
GPIO_PSID_SELECT
MODC_EN
DOCK_HP_DET
DOCK_MIC_DET
MASK_SATA_LED#
<52>
PCIE_WAKE#
<17,32,42>
LED_SATA_DIAG_OUT#
<52>
NGFF_CONFIG_0
NGFF_CONFIG_3
NGFF_CONFIG_0
<42>
SLOT3_CONFIG_0
<43>
C
SLOT3_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
<18>
GPIO_PSID_SELECT
<55>
MODC_EN
<46,54>
DOCK_HP_DET
<49>
DOCK_MIC_DET
<49>
MASK_SATA_LED#
PCIE_WAKE#
LED_SATA_DIAG_OUT#
WLAN_LAN_DISBL#
CCD_OFF
<63>
<44>
D
WLAN_LAN_DISBL#
<39>
CCD_OFF
<30>
PAD~D @ T165
NGFF_CONFIG_1
<42>
NGFF_CONFIG_2
<42>
NGFF_CONFIG_3
<42>
B51: Remove DIS_BAT_PROCHOT#
A27
A26
B26
B25
A21
B22
A28
B20
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
CLK_PCI_5048
CLKRUN#
A22
B21
A32
B35
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
EC_32KHZ_ECE5048
B29
B28
A25
A24
B23
A19
B24
A20
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
LPC_LAD0
<21,51>
LPC_LAD1
<21,51>
LPC_LAD2
<21,51>
LPC_LAD3
<21,51>
LPC_LFRAME#
<21,51>
PCH_PLTRST#_EC
<19,41,42,43,51>
CLK_PCI_5048
<20>
CLKRUN#
<19,51>
RP4
GPIOH6
0.675V_DDR_VTT_ON
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
A4
RUNPWROK
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
RUNPWROK
8
7
6
5
100K_0804_8P4R_5%
LPC_LDRQ1#
<21>
IRQ_SERIRQ
<21,51>
CLK_SIO_14M
<20>
EC_32KHZ_ECE5048
<51>
RP8
GPIOG1
LCD_TST
SLICE_BAT_ON
D_LAD0 <48>
D_LAD1 <48>
D_LAD2 <48>
D_LAD3 <48>
D_LFRAME#
<48>
D_CLKRUN#
<48>
D_DLDRQ1#
<48>
D_SERIRQ
<48>
A29
B31
A30
1
2
3
4
1
2
3
4
8
7
6
5
100K_0804_8P4R_5%
2
SYS_LED_MASK#
10K_0402_5%
2
MXM_DP_HDMI_HPD
100K_0402_5%
<51>
<51>
<51>
1
R775
B
1
R17
Remove R102 for double PD.
<51,7>
B56
B19
B46
1
R804
+CAP_LDO
B27
C1
2
1K_0402_1%
1
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
2
C714
4.7U_0603_6.3V6K
R803
100K_0402_5%
1
VGA_ID
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
2
SHORT DEFAULT
1
B5
A17
B30
A43
A54
1
R779
VCC1
VCC1
VCC1
VCC1
VCC1
R763
2
C719
0.1U_0402_10V7K
2
DOCK_SMB_ALERT#
10K_0402_5%
2
HW_GPS_DISABLE#
10K_0402_5%
2
SLICE_BAT_PRES#
100K_0402_5%
2
PCIE_WAKE#
10K_0402_5%
2
WWAN_WAKE#
10K_0402_5%
2
DEVICE_DET#
100K_0402_5%
2
1
C718
0.1U_0402_10V7K
1
2
USB_PWR_EN2#
1
C717
0.1U_0402_10V7K
2
10K_0402_5%
1
C708
0.1U_0402_10V7K
1
R768
1
C709
0.1U_0402_25V6K
1
Remove "WIRELESS_ON#/OFF" PU
for eDP_DET# pull high usage (RP2_pin 5).
D
Remove SYS_PWROK,
SPI_WP#_SEL
WLAN_RADIO_DIS#
PROCHOT_GATE
MSATA_PCIE_PIN51
IMVP_PWRGD
SP_TPM_LPC_EN
MCARD_MISC_PWREN
TEMP_ALERT#
MASK_SATA_LED#
LPC_LDRQ0#
SLICE_BST_CHG_EN
DIS_BAT_PROCHOT#
DDR_1.35V_CNTRL0
DDR_1.35V_CNTRL1
@ PJP29
PAD-OPEN1x1m
2
1
C710
0.1U_0402_25V6K
1
RE16
+3.3V_ALW_U46
+3.3V_ALW
+CAP_LDO trace width 20 mils
CLK_PCI_5048
R805
100K_0402_5%
1
2
2
2
A
@ R795
10_0402_1%
@ R794
10_0402_1%
1
1
CLK_SIO_14M
R807
2
4
1
2
1
10_0402_1%
C716
0.047U_0402_16V4Z
5
1
@ C713
4.7P_0402_50V8C
2
@ C712
4.7P_0402_50V8C
1
A
2
LID_CL_SIO#
LID_CL#
<49,52>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
SIO (ECE5048)
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
Rev
0.1
50
of
67
3
2
2
+RTC_CELL_VBAT
1
0_0402_5%
1
remove EC wake circuit.
2
1
1
R811
POWER_SW_IN#
1
@ R1985
2
10K_0402_5%
2
POWER_SW#_MB
<41,49>
CIS LINK OK
D
U51
2
+3.3V_VTR
2
USB_PWR_SHR_EN#
100K_0402_5%
2
1
2
0_0402_5%
@ R845
1
remove "HOST_DEBUG_RX" PU (5085_B46)
1
R814
1
R817
PJP@
PJP65
1
1
2
1
2
C780
0.1U_0402_25V6K
2
C777
0.1U_0402_25V6K
2
1
C1355
0.1U_0402_25V6K
2
1
C1348
0.1U_0402_25V6K
2
1
C1345
0.1U_0402_25V6K
2
1
C781
0.1U_0402_25V6K
1
2.2K_8P4R_5%
PN change to SD309470180
8
DAT_KBD
7
DAT_MSE
6
CLK_KBD
5
CLK_MSE
RP6
B3
A11
A26
B35
A41
A52
2
PAD-OPEN1x1m
SHORT DEFAULT
+5V_RUN
1
2
3
4
2
A58
+VTR_ADC
+3.3V_ALW_U51
C782
10U_0603_6.3V6M
2
BC_DAT_ECE5048
100K_0402_5%
2
BC_DAT_ECE1117
100K_0402_5%
PN change to SD309220180
8
PBAT_SMBDAT
7
PBAT_SMBCLK
6
CHARGER_SMBDAT
5
CHARGER_SMBCLK
RP5
1
2
3
4
2
+3.3V_ALW
A22
1
C757
1U_0402_6.3V4Z
2
B64
+3.3V_ALW_U51
C736
0.1U_0402_25V6K
1
R818
1
C1349
1U_0402_6.3V4Z
+3.3V_ALW
C739
0.1U_0402_25V6K
1
<21>
<21>
SML1_SMBDATA
SML1_SMBCLK
<53> CLK_TP_SIO
<53> DAT_TP_SIO
<48> CLK_KBD
<48> DAT_KBD
<48> CLK_MSE
<48> DAT_MSE
<55> PBAT_SMBDAT
<55> PBAT_SMBCLK
DOCK_POR_RST#
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
A51
B55
B56
A53
B47
FAN1_TACH_FB
DOCK_POR_RST#
FAN2_TACH_FB
PS_ID
FAN2_PWM
BIA_PWM_EC
FAN1_PWM
B22
A21
B23
B24
A23
B25
A24
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
ACAV_IN_NB
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
A43
B45
A42
B20
A18
B19
A20
B21
A19
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
A6
A27
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
4.7K_0804_8P4R_5%
<27> FAN1_TACH_FB
<48> DOCK_POR_RST#
<27> FAN2_TACH_FB
<55> PS_ID
<27> FAN2_PWM
<30> BIA_PWM_EC
<27> FAN1_PWM
+3.3V_RUN
1
2
1
2
R822
1
2
GPU_SMBDAT
2.2K_0402_5%
GPU_SMBCLK
2.2K_0402_5%
R829
C
1
2
C737
0.1U_0402_25V6K
remove "VOL_MUTE" PU
remove "VOL_DOWN" PU
remove "VOL_UP" PU
<50> BC_CLK_ECE5048
<50> BC_DAT_ECE5048
<50> BC_INT#_ECE5048
<62,63> ACAV_IN_NB
<19,32,41>
SIO_SLP_S5#
<49> BEEP
<53> BC_CLK_ECE1117
<53> BC_DAT_ECE1117
<53> BC_INT#_ECE1117
Place close pin A21
MSDATA
10K_0402_5%
R869
RP7
1
2
3
4
8
7
6
5
DOCK_POR_RST#
PCH_ALW_ON
EN_INVPWR
1.05V_0.8V_PWROK
100K_0804_8P4R_5%
1
2
RESET_OUT#
8.2K_0402_5%
1
2
1
2
1
2
PCH_RSMRST#
10K_0402_5%
A_ON
47K_0402_5%
RUN_ON
100K_0402_5%
@ R843
R892
R432
R3730
remove "CPU1.5V_S3_GATE" PD (5085_A36)
A61
A62
MEC_XTAL1
1
MEC_XTAL2_R
0_0402_5%
2
MEC_XTAL2
@ R1068
VTR_ADC
VTR
VTR
VTR
VTR
VTR
VTR
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
GPIO151/GPTP-IN4/GANG_DATA2
GPIO152/GPTP-OUT4
GPIO050/FAN_TACH1/GTACH0/GANG_START
GPIO051/FAN_TACH2/GANG _MODE
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
GPIO053/PWM0
GPIO054/PWM1/GPWM1
GPIO055/PWM2
GPIO056/PWM3/GPWM0
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA/BCM_B_DAT
GPIO006/I2C1B_CLK/BCM_B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO032/BCM_E_CLK
GPIO031/GPTP-OUT2/BCM_E_DAT
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT/GANG_STROBE
GPIO045/LSBCM_D_INT#
SYSPWR_PRES
BGP0
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
GPIO011/nSMI
GPIO061/LPCPD#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/NEC_SCI
VREF_PECI
PECI_DAT
XTAL1
XTAL2
2
1
2
Place close pin A29
<19>
2 100K_0402_5%
+RTC_CELL
BREATH_LED#
BAT1_LED#
BAT2_LED#
IMVP_VR_ON
SIO_SLP_A#
2
1
2
1
RUN_ON
PM_APWROK
RESET_OUT#
PCH_PCIE_WAKE#
A54
B58
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
AC_PRESENT
SIO_PWRBTN#
AC_PRESENT
SIO_PWRBTN#
100K_0402_5%
+PECI_VREF
PECI_EC_R
B13
A13
B14
A14
A15
B16
A16
B17
B15
A17
A12
B34
A2
B29
A46
B61
A57
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE3_N
REM_DIODE3_P
REM_DIODE4_N
REM_DIODE4_P
DOCK_LCD_SMBDAT
2.2K_0402_5%
DOCK_LCD_SMBCLK
2.2K_0402_5%
2
1
R835
1
R838
1
R841
2
remove "DYN_TUR_CURRNT_SET#" PU (5085_A35)
C
1
B51
A48
2
+3.3V_ALW
SYSPWR_PRES
ACAV_IN
ALWON
POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2#
VCI_IN3#
AC_PRESENT
10K_0402_5%
<19>
<19>
DOCK_LCD_SMBDAT
<30,48>
DOCK_LCD_SMBCLK
<30,48>
1 @ R797 A_ON <54,58>
0_0402_5% 2
SIO_EXT_WAKE#
<18,23>
SUSACK#
SUSACK#
<19>
ENVDD_PCH
ENVDD_PCH
<19,30>
GPU_SMBDAT
GPU_SMBDAT
<17>
GPU_SMBCLK
GPU_SMBCLK
<17>
CHARGER_SMBDAT
CHARGER_SMBDAT
<62>
CHARGER_SMBCLK
CHARGER_SMBCLK
<62>
SIO_SLP_SUS#
SIO_SLP_SUS#
<19>
PBAT_PRES#
PBAT_PRES#
<55,62>
USH_SMBDAT
USH_SMBDAT
<41>
USH_SMBCLK
USH_SMBCLK
<41>
B62
A64
A60
B67
A63
B63
B68
R880
+PCH_VCCDSW3_3
DOCK_LCD_SMBDAT
DOCK_LCD_SMBCLK
A59
R870
VCI_IN3#
BREATH_LED#
<48,52>
BAT1_LED#
<52>
trace width 20 mils
trace width 20 mils
BAT2_LED#
<52>
IMVP_VR_ON
<61>
SIO_SLP_A#
<19,41,54,58>
EC_32KHZ_ECE5048
<50>
ME_SUS_PWR_ACK
<19>
RUN_ON
<44,54>
PM_APWROK
<19>
RESET_OUT#
<11,18,19,7>
PCH_PCIE_WAKE#
<19>
ACAV_IN
<17,62,63>
ALWON
<56>
R874
2
1K_0402_5%
+3.3V_ALW2
R866 close to U51 at least 250mils
1
R952
C1343 1
2
43_0402_5%
2 2200P_0402_50V7K
C1350 1
2 2200P_0402_50V7K
C1351 1
2 2200P_0402_50V7K
C1346 1
2 2200P_0402_50V7K
PECI_EC
<7>
1
@ R866
1
2
PAD~D @ T155 C1343, C1350, C1351, C1346 Place
VSET_5085
2
1 I_ADP
I_ADP_R
I_ADP <62>
THERMATRIP2#
R134
4.7K_0402_5%
DGPU_THERMTRIP#
DGPU_THERMTRIP#
<17>
THSEL_STRAP
PROCHOT#_EC
Remove THERMATRIP3# CKT.
I_BATT
I_BATT <62>
2
0_0402_5%
+1.05V_RUN
+3.3V_ALW
near U51
THERMATRIP2#
+VCCIO_OUT
1 R399
2
2.2K_0402_5%
MEC5085-LZY_DQFN132_11X11
C1
EP
H_VSS
VSS_RO
B18
B54
VR_CAP
VSS_ADC
AGND
VSS
B60
B11
B66
+VR_CAP B12
2
2
1
2
@
1
1
1
1
15mil
DN1_DP1A/THERM
DP1_DN1A/VREF_T
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
VIN
VSET
VCP
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
V_ISYS0
V_ISYS1
2
B
E
1
THSEL_STRAP
R1069
C779
4.7U_0603_6.3V6K
2
MEC_XTAL2
Y6
32.768KHZ_12.5PF_Q13FC1350000
C741
22P_0402_50V8J
1
2
C743
22P_0402_50V8J
R836
100_0402_1%
2
C735
1U_0402_6.3V6K
C292 Place near U51.A48
2
1K_0402_5%
PECI_EC_R
1
@ C292
2
47P_0402_50V8J
<23,7>
1
C
2
H_THERMTRIP#
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
ESR <2ohms
B
2
2
@SHORT PADS~D
JTAG1 CONN@
B
2
@ C747
4.7P_0402_50V8C
1
1
PCH_DPWROK
<53>
VCI_IN2#
B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
A44
<61,62,7>
By pass PROCHOT CKT.
R808 1
PCH_RSMRST#
H_PROCHOT#
C327
0.1U_0402_25V6K
@ R885
10_0402_1%
MEC_XTAL1
JTAG_RST#
1
32 KHz Clock
ME_FWP_EC
<18>
RUNPWROK
<50,7>
EN_INVPWR
<30>
SIO_SLP_S4#
<19,41,54,57>
SIO_SLP_LAN#
<19,39>
USB_PWR_SHR_EN#
<47>
PCH_ALW_ON
<39>
SIO_SLP_S3#
<19,32,41,54>
1 R802 @
D
2
0_0402_5%
Q28
PMST3904_SOT323-3
R1981
100K_0402_5%
1
+3.3V_ALW
CLK_PCI_MEC
AC_DIS
BOARD_ID
SSD_SATA5_PCIE2#
LAN_WAKE#
HOST_DEBUG_TX
ME_FWP_EC
RUNPWROK
EN_INVPWR
SIO_SLP_S4#
SIO_SLP_LAN#
USB_PWR_SHR_EN#
PCH_ALW_ON
SIO_SLP_S3#
0_0402_5% 2
MSDATA
MSCLK
PCH_RSMRST#
FWP#
100K_0402_5%
GPIO156/LED1/GANG_DATA1
GPIO157/LED0
GPIO153/LED2/GANG_DATA4
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO001/ECSPI_CS1/32KHZ_OUT
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
<48>
R396
8.2K_0402_5%
<18,22> SIO_EXT_SMI#
<23> SIO_RCIN#
<21,50> IRQ_SERIRQ
<19,41,42,43,50>
PCH_PLTRST#_EC
<20> CLK_PCI_MEC
<21,50> LPC_LFRAME#
<21,50> LPC_LAD0
<21,50> LPC_LAD1
<21,50> LPC_LAD2
<21,50> LPC_LAD3
<19,50> CLKRUN#
<23> SIO_EXT_SCI#
H_VTR
A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65
C740
0.1U_0402_25V6K
A5
B6
A37
B40
A38
B41
A39
B42
B59
A56
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
GPIO025/UART_CLK
GPIO120/UART_TX/V2P_COUT_HI1
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1
VCC_PWRGD
GPIO060/KBRST/BCM_B_INT#
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#
GPIO104/SLP_S0#
GPIO106
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO117/MSCLK/V2P_COUT_HI
GPIO127/A20M
nFWP
R876
100K_0402_5%
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
VBAT
DOCK_PWR_BTN#
3
0_0402_5%
1
@ R834
2
1
+3.3V_ALW_U51
2
10K_0402_5%
1
1
+RTC_CELL
<61>
2
5
2
1.05V_0.8V_PWROK
C1353
0.1U_0402_25V6K
3
4
U50
NL17SZ08DFT2G_SC70
@ C733
1
2
1U_0402_6.3V6K
C734
1U_0402_6.3V6K
A
@ C1354
1
2
1U_0402_6.3V6K
C1352
1U_0402_6.3V6K
B
O
2
RUNPWROK
P
1
1.5V_RUN_PWRGD
G
<59>
R810
100K_0402_5%
C720
1
2
R819
100K_0402_5%
+3.3V_ALW
0.1U_0402_25V6K
1
+RTC_CELL
Remove LCD_SMBDAT,
LCD_SMBCLK,
CARD_SMBDAT
CARD_SMBCLK
VOL_MUTE
1
DOCK_PWR_SW#
EMC4021_BC_DAT
R825
1
EMC4021_BC_CLK
1.35V_SUS_PWRGD
2
VOL_DOWN
CPU1.5V_S3_GATE
SYSTEM_ID
HOST_DEBUG_RX
EC_WAKE#
1.05V_A_PWRGD
AC_DIS
<55,63>
1
PROCHOT#_EC
DYN_TUR_CURRNT_SET#
@ R1180
SSD_SATA5_PCIE2#
<18,23>
EMC4021_BC_INT#
LAN_WAKE#
<23,39>
+RTC_CELL
2
4
1
5
ACES_50506-01041-P01
2
FWP#
RUNPWROK
4
1
3
REM_DIODE3_N
DP4/DN4 for WiGig on Q15,
place Q15 close to WiGig and C288 close to Q15
REM_DIODE4_P
Channel
1
1
C
2
3
1
1
2
B
Q27
MMBT3904WT1G_SC70-3
REM_DIODE2_N
2
B
Q14
MMBT3904WT1G_SC70-3
E
2
B
Q15
MMBT3904WT1G_SC70-3
REM_DIODE4_N
Location
DP1/DN1
CPU OTP
DP1a/DN1a
CPU VR
DP2/DN2
MXM(TOP)
DP2a/DN2a
MXM(BOT)
DP3/DN3
DIMM(TOP)
DP4/DN4
A
WiGig
1
BOARD_ID
RUN_ON_ENABLE#
D
2
G
Q45
DMN65D8LW-7_SOT323-3
3
<54,7>
1
S
2
CIS link OK
5
3
3
1
1
2
1
2
remove Q52
11
12
3
C744
4700P_0402_25V7K
remove SYSTEM_ID
(5085_A10)
2
<20>
E
E
R875
240K_0402_5%~D
CLK_PCI_LPDEBUG
C
2
C
2
+3.3V_ALW
R799
10K_0402_5%
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
@ R879
10K_0402_5%
GND1
GND2
1
2
3
4
5
6
7
8
9
10
+3.3V_RUN
R872
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
2
B
E Q16
MMBT3904WT1G_SC70-3
REM_DIODE1_N
1
Difference with Diesel
+3.3V_ALW
1
A
1
3
2
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
2
2
1
3
MMBT3904WT1G_SC70-3
Q17
2
1
Difference with Diesel
+3.3V_RUN
C
2
Remove THERMATRIP3# CKT.
REM_DIODE3_P
@ C288
100P_0402_50V8J
CIS link OK
1
@ C291
100P_0402_50V8J
@ C340
100P_0402_50V8J
11
12
C
<50>
ACES_50506-01041-P01
CONN@
CONN@
JLPDE1
1
DP2/DN2 for MXM(TOP side) on Q27, place Q27 close
to MXM(TOP side) and C291 close to Q27.
DN2a/DP2a for MXM(BOT) on Q17, place Q17 close
to MXM(BOT) and C340 close to Q17
REM_DIODE2_P
E
2
1
B
EC5048_TX
MMBT3904WT1G_SC70-3
Q26
2
C
HOST_DEBUG_TX
EC5048_TX
2
@ C272
100P_0402_50V8J
BOARD_ID rise time is measured from 5%~68%.
MSCLK
MSDATA
DP3/DN3 for SODIMM(TOP) on Q14,
place Q14 close to SODIMM(TOP) and C272 close to Q14
REM_DIODE1_P
@ C273
100P_0402_50V8J
2
DP1/DN1 for CPU OTP on Q16, place Q16 close
to CPU and C273 close to Q16.
DN1a/DP1a for CPU VR on Q26, place Q26 close
to CPU and C339 close to Q26
@ R850
100K_0402_5%
R849
10K_0402_5%
R848
10K_0402_5%
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
X00
X01
X02
***
***
A00
@ C339
100P_0402_50V8J
+3.3V_ALW
R847
10K_0402_5%
R860
10K_0402_5%
GND1
GND2
1
2
3
4
5
6
7
8
9
10
R861
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
R859
10K_0402_5%
JDEG2
R858
10K_0402_5%
Rest=1.33k, Tp=93degree
R864
49.9_0402_1%
R425
1.33K_0402_1%
2
C320
0.1U_0402_25V6K
1
+3.3V_ALW
REV
E
VSET_5085
C744
4700p
4700p
4700p
4700p
4700p
4700p
B
R875
240K
130K
33K
4.3K
2K
1K
*
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Compal Electronics, Inc.
Title
KBC (MEC5085)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
1
Sheet
51
of
67
5
4
3
2
1
Breath LED
Difference with Diesel
Q359
1
<49>
2
G
2
BREATH_WHITE_LED
D
MASK_BASE_LEDS#
R932
10K_0402_5%
Q74B
DMN66D0LDW-7_SOT363-6
4
3
2
BREATH_WHITE_LED
100_0402_5%
R956
+3.3V_ALW
SATA_ACT#
1
D
1
S
3
BREATH_LED#
HDD LED
D
<18>
BREATH_LED TOP view.
DMN65D8LW-7_SOT323-3
<48,51>
1
R955
2
BREATH_LED#_Q
220_0402_5%
BREATH_LED side view.
D59
1
2
+5V_ALW
5
RB751S40T1_SOD523-2
MASK_SATA_LED#
3
<50>
Q74A
DMN66D0LDW-7_SOT363-6
1
6
D62
<50>
1
LED_SATA_DIAG_OUT#
2
2
RB751S40T1_SOD523-2
BATT LED
1
2
PDTA114EU_SC70-3
Q86
SYS_LED_MASK#
1
2
SATA_SIDE_LED
150_0402_5%
R943
<51>
BAT2_LED#
<51>
BAT1_LED#
1
R130
BAT2_LED#
2
BATT_WHITE_LED
475_0402_1%
C
C
1
R131
BAT1_LED#
2 BATT_YELLOW_LED
150_0402_1%
WWAN/WLAN LED
+3.3V_ALW
+3.3V_ALW
1
+5V_ALW
@ C778
1
2
2
3
WIRELESS_LED#
1
5
<39,50>
2
SYS_LED_MASK#
<49,50>
LID_CL#
SYS_LED_MASK#
1
LID_CL#
2
B
A
0.1U_0402_25V6K
3
O
4
MASK_BASE_LEDS#
U58
TC7SH08FU_SSOP5~D
1
2
G
PDTA114EU_SC70-3
Q79
P
D
S
<42,50>
3
Q78
DMN65D8LW-7_SOT323-3
G
R937
100K_0402_5%
SYS_LED_MASK#
1
R939
2
WLAN_LED
1.2K_0402_1%
B
B
Difference with Diesel
+5V_ALW
1
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
C6
SYS_LED_MASK#
LID_CL#
0
1
1
X
0
1
2
0.1U_0402_16V4Z
LED Circuit Control Table
BREATH_LED#_Q
WLAN_LED
BATT_YELLOW_LED
BATT_WHITE_LED
SATA_SIDE_LED
JLED1
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GND
GND
11
12
ACES_51522-01001-001
CONN@
CIS link OK
Fiducial Mark
@FD1
@
FD1
1
@ H4
H_3P0
@ H5
@H5
H_3P0
@ H6
H_3P0
@ H7
@H7
H_3P8
@ H8
H_3P8
@ H9
H_3P8
@ H10
@H10
H_3P0
@ H11
H_3P0
@ H12
@H12
H_3P8
@ H13
H_3P8
@ H14
H_3P0
@ H15
@H15
H_3P0
1
@ H3
H_3P0
1
@ H2
H_3P8
1
A
@ H1
@H1
H_3P0
1
FIDUCIAL MARK~D
1
@ H20
@H20
H_3P0
@ H21
H_3P0
1
1
@ H19
@H19
H_3P6
1
1
@ H18
H_3P0
1
1
@ H17
H_3P6
1
1
@ H16
@H16
H_3P0
1
1
@FD2
@
FD2
1
@ H24
H_3P6
@ H25
H_3P0
@ H26
@H26
H_1P2
@ H27
H_1P2
@ H28
@H28
H_3P0
FIDUCIAL MARK~D
@FD3
@
FD3
1
@ H22
@H22
@H23
@
H23
H_3P6X3P0 H_3P6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
1
1
1
1
1
1
1
1
1
1
@ FD4
@FD4
1
1
FIDUCIAL MARK~D
1
A
FIDUCIAL MARK~D
5
4
3
2
Title
LED / Screw hole
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
52
of
67
5
4
3
2
1
D
D
+5V_ALW
1
RSMRST#
2
@ R1623
+3.3V_ALW_PCH
0_0402_5%
+3.3V_ALW
+3.3V_ALW_PCH
VCC
3
1
2
5
1
PCH_RSMRST#
2
RSMRST#
B
A
O
GND
3
@C290
@
C290
0.01U_0402_16V7K
RESET#
2
P
<51>
1
1
0.1U_0402_25V6K
G
2
1
2
1
2
@ C289
1
2
4
R1624
8.2K_0402_5%
@R1633
@
R1633
10K_0402_5%
@ U18
@R1622
@
R1622
10K_0402_5%
@ R1630
@R1630
33_0402_5%
1
+3.3V_ALW
@
PCH_RSMRST#_Q
<18,19>
Remove RSMRST cost down circuit.
U12
NL17SZ08DFT2G_SC70
RT9818A-44GU3_SC70-3~D
2
<56>
1
ALW_PWRGD_3V_5V
RZ52
2
0_0402_5%
C
C
Touch Pad
Keyboard
+3.3V_RUN
+3.3V_TP
JKBTP1
+3.3V_TP
<23>
PJP@
PJP16
2
1
2
2
RZ19
4.7K_0402_5%
RZ18
4.7K_0402_5%
PAD-OPEN1x1m
1
1
+5V_RUN
+3.3V_ALW
<51> BC_INT#_ECE1117
<51> BC_DAT_ECE1117
<51>
B
1
2
2
1
DAT_TP_SIO
CLK_TP_SIO
@ C1411
0.1U_0402_25V6
@ C1414
0.1U_0402_25V6
@ C1410
0.1U_0402_25V6
EMI depop location
1
+3.3V_TP +3.3V_ALW +5V_RUN
@EMC@ CZ31
10P_0402_50V8J
@EMC@ CZ30
10P_0402_50V8J
2
BC_CLK_ECE1117
+3.3V_TP
CLK_TP_SIO
2
CLK_TP_SIO
1
<51>
DAT_TP_SIO
2
DAT_TP_SIO
1
<51>
KB_DET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
17
12
G 18
13
G 19
14
G 20
15
G
16
ACES_50554-01601-001
CONN@
B
CIS link OK
Place close to JKBTP1
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
KB / TP / RSMRST#
LA-B541P
Size
Document Number
Date:
Monday, January 13, 2014
Sheet
1
53
Rev
0.1
of
67
3
2
1
Remove +PWR_SRC_S PU
+PWR_SRC
+1.05V_RUN Source
Q63
MDS1521URH_SO8
5
9
<51,7>
RUN_ON_ENABLE#
<44,51,54>
<19,32,41,51>
TPS22965DSGR_SON8_2X2~D
RUN_ON
1
2
1
2
0_0402_5%
@ R762
SIO_SLP_S3#
2
0_0402_5%
@ R781
4
4
1
1
2
3
2
2
1
GND
GND
CT
2
JUMP_43X79
6
1
5
RUN_ON_ENABLE#
1
@
1
2
8
2
D
C773
100P_0402_50V8J
C539
470P_0402_50V7K
2
VOUT
VBIAS
6
1
VOUT
VIN
2
4
+5V_ALW
VIN
1
Q304A
DMN66D0LDW-7_SOT363-6
2
2
R1611
1M_0402_5%
+3.3V_ALW
@ PJP92
7
C400
10U_0603_6.3V6M
2
C362
0.1U_0603_25V7K
R301
100K_0402_5%
1
ON
1
Q304B
DMN66D0LDW-7_SOT363-6
3
3.3V_RUN_GFX_ON
3.3V_RUN_GFX_ON
1
+1.05V_RUN_ENABLE
D
<20,44,50>
+1.05V_RUN
1
2
3
R931
20K_0402_5%
+3.3V_MXM
8
7
6
5
C772
10U_0603_6.3V6M
+3.3V_MXM_PWR
U34
R909
100K_0402_5%
+3.3V_ALW to +3.3V_MXM
R933
330K_0402_5%
1
+1.05V_M
+3.3V_ALW2
1
4
2
5
1
2
+5V_RUN Source
+5VMOD Source
+5V_RUN_PWR
U37
1
RUN_ON
@ R881
MODC_EN
MODC_EN
4
1
2
2
1
2
1
VOUT2
VOUT2
11
1
PAD-OPEN 4x4m
PJP@
10
2
9
8
+5V_MOD_PWR
C
+5V_MOD_PWR
+5V_MOD
@ PJP105
15
2
2
1
2
1
2
1
2
C767
10U_0603_6.3V6M
1
CT2
VIN2
VIN2
1
C543
470P_0402_50V7K
1 2
ON2
2
+5V_RUN_PWR
12
C544
470P_0402_50V7K
3
GND
GPAD
2
1
1
JUMP_43X79
Combine +3.3V_WLAN and +3.3V_RUN
into M.2 card power control page.
R935
100K_0402_5%
C774
0.01U_0402_50V7K
2
Q87
DMN65D8LW-7_SOT323-3
VBIAS
14
13
TPS22966DPUR_SON14_2X3~D
@ PJP79
1
2
D
2
G
CT1
+MXM_PWR_SRC
1
R944
20K_0402_5%
3.3V_RUN_GFX_ON
5
6
7
+5V_ALW
VOUT1
VOUT1
ON1
2
PAD-OPEN 4x4m
1
4
VIN1
VIN1
PAD-OPEN 4x4m
+MXM_SRC_EN#
B
3
@ PJP78
1
+MXM_PWR
C776
10U_1206_25V6M
R940
100K_0402_5%
Q186
SI4835DDY-T1-E3_SO8
1
8
2
7
3
6
5
RUN_ON_R
0_0402_5%
+5V_ALW
R514
100K_0402_5%
MXM_PWR_SRC Source
+PWR_SRC_MXM
2
C514
10U_0805_10V4Z
<44,51,54>
<46,50>
+PWR_SRC_MXM
1
2
+5V_ALW
Combine +3.3V_SSD and +5V_MXM
into M.2 card power control page
C
+5V_RUN
PJP82
Combine +3.3V_LAN and +3.3V_ALW_PCH
into LAN page
B
S
+3.3V_M Source
+3.3V_SUS Source
+3.3V_M_PWR
+3.3V_M
U40
<51,58>
<19,41,51,58>
@ R878
SIO_SLP_A#
1
@ R877
2
0_0402_5%
1
2
+3.3V_ALW
2
0_0402_5%
A_ON_R
1
SIO_SLP_S4#
1
R3732
2
0_0402_5%
SIO_SLP_S4#_R
5
6
7
+3.3V_ALW
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
3
S
2
G
2
10
9
8
15
@ Q70
DMN65D8LW-7_SOT323-3
2
1
1
JUMP_43X79
+3.3V_SUS_PWR
2
2
1
+3.3V_SUS
@ PJP94
2
1
2
C475
10U_0603_6.3V6M
RUN_ON_ENABLE#
1
11
1
A
D
12
TPS22966DPUR_SON14_2X3~D
Remove USH_PWR_ON
SUS_ON
2
+3.3V_M_PWR
C477
470P_0402_50V7K
GPAD
14
13
C476
470P_0402_50V7K
+1.05V_RUN_CHG
2
@ R925
39_0402_5%
4
+5V_ALW
<19,41,51,57>
3
@ PJP90
VIN1
VIN1
C513
10U_0603_6.3V6M
+1.05V_RUN
1
A_ON
2
1
1
JUMP_43X79
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Power Control
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
54
of
67
5
4
3
2
1
+COINCELL
EMI Part (47.1)
COIN RTC Battery
+PWR_SRC
1
EMC@ PL1
FBC-78-302585-L-T
1
2
PR1
1K_0402_5%
+PWR_SRC_MXM
2
Z4012
PC1
@
JRTC1
1
2
+COINCELL
3
4
2
@
+
2
3
D
1
100U_25V_M
PC31
0.1U_0603_25V7K
2
1
PC30
10U_0805_25V6K
2
1
+3.3V_RTC_LDO
+RTC_CELL
ESD Diodes
1
2
D
GND
GND
1
ACES_50271-0020N-001
PD1
BAS40CW_SOT323-3
ESD (47.2)
1
PC2
1U_0603_10V4Z
1
1
2
EMC@
PD2
TVNST52302AB0_SOT523-3
Move to power schematic
EMC@
PD3
TVNST52302AB0_SOT523-3
3
Primary Battery Connector
EMI Part (47.1)
CONN@
+3.3V_ALW
EMC@ PL6
FBMJ4516HS720NT_2P
1
2
PBATT+
100_0804_8P4R_5%
1
2
3
4
Z4304
Z4305
Z4306
8
7
6
5
PBAT_SMBCLK
PBAT_SMBDAT
<51>
<51>
PBAT_PRES#
PR3
PD5
2
1
3
D
1
<51,62>
PQ1
NTR4502PT1G_SOT23-3
S
SUYIN_200045GR009M28QZR
9
1 8
2 7
3 6
4 5
5 4
6 3
7 2
8 1
9 10
GND 11
GND
PBATT1
C
DOCK_SMB_ALERT#
<48,50>
SDMK0340L-7-F_SOD323-2
2
G
EMC@ PC4
2200P_0402_50V7K
2
1
C
PBATT+_C
2
PR2
100K_0402_5%
2
1
2
3
2
EMI Part (47.1)
EMC@ PL2
FBMJ4516HS720NT_2P
1
GND
SLICE_BAT_PRES#
PR33
0_0402_5%
1
2
2
1
<48,50,63>
PC5
1500P_0402_50V7K
+3.3V_ALW
EMC@ PL3
BLM15BX102SN1D_2P
2
1
S
2
B
2
3
PQ2
FDV301N_G_NL_SOT23-3~D
NO
GND
NC
IN
V+
COM
6
GPIO_PSID_SELECT
5
<50>
+5V_ALW
4
PS_ID
<51>
74LVC1G3157GW SC-88 6P MUX
+5V_ALW
C
PQ3
MMST3904-7-F_SOT323-3
E
2
3
PR12
15K_0402_1%
1
2
1
DOCK_PSID
NB_PSID_TS5A63157
1
2
G
1
B
PR9
33_0402_5%
1
2
3
D
1
PR10
100K_0402_1%
1
2
NB_PSID
PU1
<48>
PR11
10K_0402_1%
EMI Part (47.1)
PR8
2.2K_0402_5%
1
2
@ PR7
0_0402_5%
1
2
B
PR13
1
@
2
PSID_DISABLE#
<50>
10K_0402_5%
DC_IN+ Source
SI7149DP
4
SOFT_START_GC
<63>
1
2
PC14
10U_0805_25V6K
2
10K_0402_5%
1M_0402_5%
1
PR22
<51,63>
2
AC_DIS
PR18
100K_0402_5%
2
1
1M_0402_5%
PC9
PR20
1
IMD2AT-108_SC74-6~D
5
5
1
2
0.022U_0603_50V7K
+DC_IN_SS
1
2
3
PR16
3
2
4
1
PQ8B
PQ8A
IMD2AT-108_SC74-6~D
6
1
ACES_50493-0110N-001
@ PR19
4.7K_0805_5%
2
1
+DCIN_JACK
@
2
+DC_IN
2
@EMC@ PC15
0.1U_0603_25V7K
2
1
EMC@ PC11
1000P_0402_50V7K
2
1
A
1
PD8
VZ0603M260APT_0603
EMC@ PL4
FBC-78-302585-L-T
1
2
PJPDC1
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
11
PQ5
+DC_IN
EMI Part (47.1)
A
DELL CONFIDENTIAL/PROPRIETARY
CONN@
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+DCIN
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
55
of
67
A
B
C
1
D
E
1
+3.3V_ALW2 +3.3V_RTC_LDO
1
2
PR106
143K_0402_1%
TPS51225CRUKR_QFN20_3X3
DRVH2
DRVH1
16
UG_5V
VBST2
17
BST_5V
18
SW1
DRVL1
SW1
+5VALWP
2
5
LG_5V
4
4
3
2
1
PC118
1U_0603_10V6K
2
1
PC117
0.1U_0603_25V7K
2
1
PL102
3.3UH_PIMB104T-3R3MS_10A_20%
1
2
15
20
3V_5V_EN
LG_3V
EN1
VREG5
VIN
13
5
12
SW2
11
8
PC110
0.1U_0603_25V7K
2
BST_5V_C 1
3
2
1
VBST1
SW2
4
PR109
2.2_0603_5%
1
2
1
1
9
+
PR112 @
2
BST_3V
2
4.7_1206_5%
2
PC115
220U_6.3V_M
X76_1@
SNUB_5V
10
UG_3V
PC109
PR110
0.1U_0603_25V7K
2.2_0603_5%
1
2
2
BST_3V_C 1
19
FDMC7692S_MLP8-5
PQ103
4
14
SIS412DN-T1-GE3_POWERPAK8-5
PQ101
PGOOD
21
5
CS1
VFB1
VREG3
VFB2
1
1
2
3
4
+DC1_PWR_SRC
3
+5V_ALW2
1
+DC1_PWR_SRC
2
2
@ PC111
680P_0603_50V7K
PAD
VCLK
1
3
5
FB_5V
7
PGOOD_3V_5V
1
2
3
1
@ PR111
4.7_1206_5%
SNUB_3V
2
PC113
220U_6.3V_M
X76_1@
2
+
PQ102
SI7716ADN-T1-GE3_POWERPAK8-5
1
EN2
VO1
PL101
2.2UH_7.8A_20%
1
2
+3VALWP
PC100
1U_0603_10V6K
2
1
PR103
0_0402_5%
2
1
3V_5V_EN6
1
5
PR108
0_0402_5%
1
2
PR104
10K_0402_1%
2
1
1
2
3
PQ100
SIS412DN-T1-GE3_POWERPAK8-5
1
2
PR107
100K_0402_1%
PC101
10U_0805_25V6K
+PWR_SRC
EMC@ PC105
2200P_0402_50V7K
2
1
2
PU101
2
2
CS2
+DC1_PWR_SRC
EMC@ PC103
0.1U_0402_25V6
2
1
1
+3.3V_ALW
DRVL2
PL100
1UH_PCMB053T-1R0MS_7A_20%
ALW_PWRGD_3V_5V
FB_3V
<53>
PR102
10K_0402_1%
2
PR105
86.6K_0402_1%
2
1
1
PR101
15K_0402_1%
1
2
PC102
10U_0805_25V6K
PR100
6.49K_0402_1%
1
2
3VALWP
Ripple voltage Static load 3% / Dynamic load 5%
Frequency 350kHz
TDC 4.5 A
Peak Current 6.5 A
OCP current 7.8 A
TYP
MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR:15.5
Bulk cap ESR 15mohm
PC114 @
680P_0603_50V7K
3V_5V_EN
ALWON
PC119
1U_0603_10V6K
2
1
<51>
5VALWP
Ripple voltage Static load 3% / Dynamic load 5%
Frequency 300kHz
TDC 7.8 A
Peak Current 11.15 A
OCP current 13.38 A
TYP
MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.8mohm , 13.6mohm
Choke DCR Max:11.8mohm
Choke Ityp:10A / Isat:16A
Bulk cap ESR 15mohm
PR113
2K_0402_1%
1
2
@
PJP100
1
+3VALWP
PJP102
2
+3.3V_ALW+5VALWP
1
2
PAD-OPEN 43x118
PJP101
1
2
PAD-OPEN 43x118
PJP103
1
2
PAD-OPEN 43x118
PAD-OPEN 43x118
+5V_ALW
4
4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
+5V_ALW/3.3V_ALW
Document Number
Rev
0.1
LA-B541P
Monday, January 13, 2014
Sheet
E
56
of
67
5
4
3
2
1
0.675Volt +/- 5%
TDC 1.05A
Peak Current 1.5A
OCP Current 1.8A
PJP201
VLDOIN_1.35V 2
+1.35V_MEN_P
1
EMI Part (35.33)
PAD-OPEN1x1m
PJP200
2
1
1.35V_B+
1
2
3
PR201
6.49K_0402_1%
1
2
5
1
VTT
PGND
VTTSNS
2
20
19
VLDOIN
18
17
BOOT
PAD
VTTGND
21
1
2
12
CS
GND
RT8207MZQW_WQFN20_3X3
+V_DDR_REF
VDDP
VTTREF
3
4
+V_DDR_REF
PJP203
2
2
10
+3.3V_ALW
FB sense trace
when FB pull down to GND
1
1
PJP204
2
2
1
+1.35V_MEM
1
JUMP_1x3m
PJP202
+0.675V_P
PR204
10K_0402_1%
2
1
1.35V_FB
2
+0.675V_DDR_VTT
1
PAD-OPEN1x1m
1.35V_SUS_PWRGD
PR205
1M_0402_1%
1
2
1
2
0.675V_DDR_VTT_ON
2
1
PR207
12.4K_0402_1%
S5_1.35V
<50>
C
2
1.35V_B+
PR206
200K_0402_5%
1
2
PR208
100K_0402_5%
1
2
PC214
@ .1U_0402_16V7K
1
1.35Volt +/- 5%
TDC: 10.5 A
Peak Current: 15 A
OCP current: 18 A
Rds(on): 3.5m ohm(max)
Choke DCR
3.5mohm(max)
+1.35V_MEN_P
PC211
220P_0402_50V8J
1
2
C
SIO_SLP_S4#
2
JUMP_1x3m
+5V_ALW
1
1.35V_SUS_PWRGD
PC209
0.033U_0402_16V7K
+1.35V_MEN_P
FB
PC210
1U_0603_10V6K
VDDQ
S3
+5V_ALW
VDD
5
6
1
4
S5
11
VDD_1.35V
7
2
8
1
2
<7>
D
CS_1.35V
PC213
1U_0603_10V6K
2
1
VDDP_1.35V
PR203
5.1_0603_5%
LGATE
PR209
100K_0402_1%
EMI Part (35.33)
<19,41,51,54>
PHASE
16
14
UGATE
15
PU200
PC207
22U_0805_6.3VAM
2
1
5
4
3
2
1
PQ202
SIRA06DP-T1_POWERPAK-SO8-5
2
PC201
330U_2.5V_M
X76_1@
DL_1.35V
13
@EMC@
@EMC@
680P_0603_50V7K
4.7_1206_5%
PC212
PR202
2
1 SNUB_1.35V 2
1
1
+0.675V_P
SW_1.35V
PC206
0.22U_0603_10V7K
TON
PL201
1.0UH_PCMB104T-1R0MH_18A_20%
1
2
+
BOOT_1.35V
DH_1.35V
PQ201
SIR472DP-T1-GE3_POWERPAK8-5
1
2
PC205 EMC@
2200P_0402_50V7K
1
2
PC204 EMC@
0.1U_0402_25V6
@
PC203
10U_0805_25V6K
2
1
PC202
10U_0805_25V6K
2
1
D
+1.35V_MEN_P
PR200 2
2.2_0603_5%
PGOOD
1
PAD-OPEN 1x2m~D
9
+PWR_SRC
S3_1.35V
PC215
1U_0402_6.3VX5R
+1.35V_MEN_P
FB sense trace
B
B
Mode
S5
S3
S0
S3
L
L
H
S5
L
H
H
+1.35V_MEN +V_DDR_REF
off
off
on
on
on
on
+0.675V_P
off
off(Hi-Z)
on
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
1.35VP/0.675VSP
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
57
of
67
5
4
3
2
1
PJP300
2
+1.05VSP_B+
1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_ALW
4
5
V5IN
TST
DRVL
9
UG_+1.05VSP
8
SW _+1.05VSP
7
6
2
1
PC305
10U_0805_25V6K
EMC@ PC302
0.1U_0402_25V6
2
1
PL301
1UH_11A_20%_7X7X3_M
1
2
+1.05V_MP
+5V_ALW
LG_+1.05VSP
1
2
11
PC308
1U_0603_10V6K
TPS51212DSCR_SON10_3X3
1
4
PR305
470K_0402_1%
3
2
1
2
PC307
0.22U_0402_16V7K
VFB
TP
2
C
SW
1
1
4
RF_+1.05VSP
DRVH
EN
EMI Part (35.33)
+
PR304 @EMC@
4.7_1206_5%
2
2
FB_+1.05VSP
TRIP
PR301
1
2
2.2_0603_5%
PC301
330U_2.5V_M
X76_1@
C
1
A_ON
3
1
<51,54>
PR315
0_0402_5%
1
2
2
BST_+1.05VSP
PC309 @EMC@
1000P_0402_50V7K
2
SIO_SLP_A#
PR302
1
2 TRIP_+1.05VSP
84.5K_0402_1%
EN_+1.05VSP
10
SI7716ADN-T1-GE3_POWERPAK8-5
PQ303
<19,41,51,54>
@ PR303
0_0402_5%
1
2
VBST
5
S0 mode be high level
PGOOD
3
2
1
PU300
1
PC306
.1U_0603_25V7K
2
1
SIS412DN-T1-GE3_POWERPAK8-5
PQ301
5
1
PR300
100K_0402_5%
EMC@ PC303
2200P_0402_50V7K
2
1
D
2
D
PR306
4.99K_0402_1%
2
1
2
+1.05VSP
Ripple voltage Static load 3% / Dynamic load 5%
Frequency 290kHz
TDC 4.82A
Peak Current 6.89A
OCP current 7.5A
TYP
MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 11mohm
Bulk cap ESR 17mohm
PR307
10K_0402_1%
PJP301
2
B
1
1
PAD-OPEN 1x2m~D
+1.05V_MP
PJP302
2
1
+1.05V_M
PAD-OPEN 1x2m~D
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Date:
5
4
3
2
+1.05V_M
Document Number
Rev
0.1
LA-B541P
Monday, January 13, 2014
Sheet
1
58
of
67
5
4
3
2
1
1.5Volt +/- 5%
TDC: 0.15A
Peak Current: 0.2 A
OCP current: 4 A
+3.3V_RUN
D
D
1
+5V_ALW
PJP400
+3.3V_RUN
2
PU400
1
1
PR402
1.54K_0402_1%
APL5930KAI-TRG_SO8
+1.5V_RUN
PC403
0.01U_0402_25V7K
1
VIN
9
2
PAD-OPEN1x1m
PC404
22U_0805_6.3V6M
2
47K_0402_5%
.1U_0402_16V7K
2
2
@ PC402
2
@ PR401
FB
PJP401
1
+1.5V_RUNP
2
1
1
100K_0402_5%
EN
PC401
4.7U_0805_6.3V6K
3
1
8
4
2
2
5
1
VIN
VOUT
VOUT
GND
1
PR400
POK
2
7
VCNTL
1.5V_RUN_PWRGD
+3.3V_RUN
1
<51>
PC400
1U_0402_6.3V6K
6
2
PR407
10K_0402_5%
2
1
1
PAD-OPEN1x1m
PR403
1.74K_0402_1%
C
2
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Date:
5
4
3
2
+1.5V_RUN
Document Number
Rev
0.1
LA-B541P
Monday, January 13, 2014
Sheet
1
59
of
67
5
4
3
2
1
D
D
12VSP_TB +/-5%
TDC 0.7A
Peak Current 1A
OCP 3A(Input)
PC601
PR601
680P_0603_50V7K
4.7_1206_5%
1
2
1
2
@EMC@
@EMC@
PQ601
COMP_12VSP_TB
2
2
PC617 10U_0805_25V6K
C
1
2
1
PC616 10U_0805_25V6K
2
1
2
1
PC614 10U_0805_25V6K
2
1
PC613 10U_0805_25V6K
1
2
PC612 10U_0805_25V6K
2
1
1
2
2
PC615 10U_0805_25V6K
TB@
TB@
TB@
TB@
PR613
10K_0402_1%
D
S
2
G
TB@
PQ604
S TR 2N7002KW 1N SOT323-3
+PWR_SRC
4
+
0
PU602A
LM393DR_SO8
TB@
2
1
TB@
3
2
1
1
PR617
B
2
OVP 14.4V
10K_0402_1%
PR618
+PWR_SRC
2
TB@
31.6K_0402_1%
10K_0402_1%
2
TB@
PR616
1
1
TB@
2
TB@
RT9297GQW _W DFN10_3X3
2
+3.3V_ALW
1
4700P_0402_25V7K
TB@
G
PC608
1 1
110K_0402_1%
TB@
TB@
TB@
P
GND
GND
PAD
TB@
5
4
PR611
2
TB@
11
1
2
TB@
0.1U_0402_16V7K
PC606
PR610
10K_0402_1%
1
86.6K_0402_1%
PR612
PC609
TB@
1
1
TB@
3
SS_12VSP_TB
@
866_0402_1%
PR619
8
COMP
10
2
EN
TB@
PC611 10U_0805_25V6K
SS
FB_12VSP_TB
2
FREQ
2
@
1
FB
1
Vin
0.01U_0402_16V7K
6
7
LX
TB@
8
PR609
TB@0_0402_5%
1
2FREQ_12VSP_TB
9
PR608
2.49K_0402_1%
1
2 EN_12VSP_TB
3
+5V_ALW
PU600
LX
10U_0805_25V6K
2
1
PR615
1.5M_0402_1%
1
TB@
PQ602A
DMN66D0LDW-7_SOT363-6
1
6
1
SX35H_SMA2
PC610
0.01U_0402_50V7K
2
1
PD602
2
TB@
PC607
TB@
PR605
0_0402_5%
B
1
SX35H_SMA2
1
3
4
TB@
PC604
TB@
PC605
10U_0805_25V6K
2
TB@
LX_12VSP_TB
2
1
1
100K_0402_1%
2
@
PR604
PR607
49.9K_0402_1%
DMN66D0LDW-7_SOT363-6
TB@ PQ602B
@
0.1U_0402_16V7K
PC602
TBT_HV_EN
5
2
<32>
TB@PR603
TB@PR603
10K_0402_1%
1
2
1
1500P_0402_50V7K
2
1
TB@
2
4
1
2
TB@
0.022U_0402_25V7K
2
1
TB@
C
100K_0402_1%
PR606
TB@
1
PR614
402K_0402_1%
2
PAD-OPEN 1x2m~D
PC603
+12VSP_TB
PD601
5
2
2
1
+5V_ALW
1
2
3
2
1
TB@PL601
TB@
PL601
4.7UH_5.5A_20%_7X7X3_M
AON7403L_DFN8-5
PJP601
TB@
PJP602
1
+12VSP_TB
2
+12VS_TB
A
A
PAD-OPEN1x1m
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12VS_TB
Size
4
3
2
Rev
0.1
LA-B541P
Date:
5
Document Number
Monday, January 13, 2014
Sheet
1
60
of
67
5
4
3
2
1
+5V_ALW
PQ500
CSD87350Q5D_SON8~D
PU501
VR12.5->PR509=3.24K
VR12.6->PR509=16.9K
PR514
21K_0402_1%
1
2
+5V_ALW
LGATE2
PC528
0.15U_0402_10V6K
1
2
ISEN1
PC544
1
@
0.01U_0402_50V7K
2
330P_0402_50V7K
0.082U_0402_16V7K
@ PC542
1
2
BOOT1 2
2.2_0603_5%
1 1
2
PR551
2.61K_0402_1%
1
2
LGATE1
PR558
5.1M_0402_5%
1
2
ISUMN
V1N
@ PR546
2
1
10K_0402_1%
V3N
@ PR547
2
1
10K_0402_1%
PR544
10_0402_1%
B
2
1
+
2
1
+
2
PL502
0.22UH_PCME064T-R22MS_28A_20%
1
4
+VCC_CORE
2
3
V1N
P1_SW_1
PR552
PR553
3.65K_0603_1%
10K_0603_1%
1
2
1
2
ISEN1
V2N
@ PR556
2
1
10K_0402_1%
V3N
@ PR557
2
1
10K_0402_1%
ISUMP
VSSSENSE
Local sense put on HW site
+
100U_25V_M
1
PC531
PC533
10U_0805_25VAK
2
1
PR549
PC540
0.22U_0603_16V7K
PH501
10KB_0402_5%_ERTJ0ER103J
1
2
EMC@ PR554
4.7_1206_5%
2
1 SNB_CPU_P1
2
1
PR550
11K_0402_1%
1
2
+VCC_CORE
V2N
ISEN2
P1_SW
4
PC546
1
2
PC547
.1U_0402_16V7K
2
1
7
6
5
3
PHASE1
VCCSENSE
ISUMN
<11>
2
UGATE1
8
<11>
PC543
0.22U_0402_6.3V6K
2
1
A
PQ502
CSD87350Q5D_SON8~D
@ PC538
0.033U_0603_25V7K
1
2
PC539
0.22U_0402_6.3V6K
2
1
PC541
0.22U_0402_6.3V6K
2
1
PC532
0.1U_0603_25V7K
1
2
1
ISEN2
3
CPU_B+
ISEN3
PR548
0_0402_5%
1
2
4
1
PC521
0.22U_0603_16V7K
1
2
PR535
3.65K_0603_1% P2_SW_1
1
2
PR539
10K_0603_1%
1
2
2
1
2
2
ISUMN
1
PC527
330P_0402_50V7K~D
1 1
PC530
1
2 1
B
BOOT2 2
2.2_0603_5%
PL501 0.22UH_PCME064T-R22MS_28A_20%
P2_SW
4
PR534
100U_25V_M
2
2
2.87K_0402_1%
PR543
2K_0402_1%
7
6
5
3
PC519
.1U_0603_25V7K
100U_25V_M
1
2
UGATE2
PHASE2
DELL CONFIDENTIAL/PROPRIETARY
1
PR536
2
+5V_ALW
2
PR537
576_0402_1%
1
2
499_0402_1%
PC522
4700P_0402_25V7K
1
1
PR545
1.5K_0402_1%
2
2
1
2 1
PC526
PR541
4700P_0402_25V7K 909_0402_1%
1
2
2
PQ501
CSD87350Q5D_SON8~D
PR555
10_0402_1%
A
ISUMN 2
2
PC520
680P_0402_50V7K
2
1
VCCSENSE
+PWR_SRC
EMC@ PL510
FBMA-L11-453215-800LMA90T_1812
1
2
CPU_B+
PU500
ISL95812HRZ-T_QFN32_4x4
PR531
1_0402_1%
1
PR533
ISUMP
PR526
0_0402_5%
1
2CPU_B+
6.04K_0402_1%
PC525
39P_0402_50V8J
C
EMI Part (47.1)
PC529
PR529
1
@ PR518
1
V2N 2
10K_0402_1%
EMC@ PC516
470P_0402_50V7K
2
1
1
2
PR525
3.83K_0402_1%
PAD
+VCC_CORE
V3N
@ PR516
1
V1N 2
10K_0402_1%
@EMC@ PC515
0.1U_0402_25V6
2
1
PR528
27.4K_0402_1%
2
1
33
PWM3
LGATE1
PHASE1
UGATE1
BOOT1
3
ISEN3
VCC_core (Base on PDDG rev 2.0)
TDC 33A
Peak Current 95A
DC Load line -1.5mV/A
Icc_Dyn_VID1 60A
OCP current 114A
DCR 0.98m ohm
PC512
10U_0805_25VAK
2
1
2
1
PH500
470K_0402_5%_ TSM0B474J4702RE
LGATE2
4
2
PR510
10K_0603_1%
2
1
PR520
0_0603_5%
EMC@ PR542
4.7_1206_5%
2
1 SNB_CPU_P2
2
1
COMP
FB
NTC
24
23
22
21
20
19
18
17
1
2 VR_HOT#
0_0402_5%
LGATE2
VDDP
PWM3
LGATE1
PHASE1
UGATE1
BOOT1
VIN
2
1
PR524
SCLK
VR_ON
PGOOD
IMON
VR_HOT#
NTC
COMP
FB
ALERT#
SDA
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
32
31
30
29
28
27
26
25
2
1
H_PROCHOT#
IMON
PC510
47P_0402_50V8J
C
1
2
3
4
5
6
7
8
SCLK
VR_ON
VCC_PGOOD
9
10
11
12
13
14
15
16
PR522
0_0402_5%
1
2
PR521
93.1K_0402_1%
2
1
FB2/VSEN
ISEN3
ISEN2
ISEN1
RTN
ISUMN
ISUMP
VDD
PC509
1
2
820P_0402_50V7K
<51,62,7>
PC508
1U_0603_10V6K
1
2
VCORE_VDDP 1
SDA
ALERT#
PCH_PWROK
1
1.91K_0402_1%
1
BOOT2
UGATE2
PHASE2
8
PR519
2
PR517
0_0402_5%
1
2
2
1.05V_0.8V_PWROK
PC511
0.22U_0603_25V7K
+3.3V_RUN
<19>
<51>
1
P3_SW_1
PC514
10U_0805_25VAK
2
1
1
PC504
10U_0805_25VAK
2
1
P3_SW
1
2
PR512
10_0402_1%
7
6
5
ISUMN
4
2
PR511
3.65K_0603_1%
3
LGATE3
ISL6208BCRZ-T_QFN8_2X2
PR509
3.24K_0402_1%
1
2
@ PR513
0_0402_5%
2
IMVP_VR_ON
LGATE
PHASE3
5
PC513
10U_0805_25VAK
2
1
<51>
GND
TP
8
PL500
ISUMP
VIDSCLK
PWM PHASE
4
9
0.22UH_PCME064T-R22MS_28A_20%
PC535
10U_0805_25VAK
2
1
<11>
PR507
21K_0402_1%
1
2
EMI Part (47.1)
ISUMP
VIDALERT_N
3
PWM3
1
PR506
2
BOOT3
8
<11>
VIDSOUT
UGATE3
2
EMC@ PC523
680P_0603_50V7K
0_0402_5%
2
0_0402_5%
1
2
PR508 0_0402_5%
1
2
PR505
<11>
D
UGATE
FCCM BOOT
1
VCC
7
1
EMC@ PC507
680P_0603_50V7K
6
54.9_0402_1%
1
PC534
10U_0805_25VAK
2
1
PR504
2
EMC@ PR515
4.7_1206_5%
2
1 SNB_CPU_P3
2
1
D
PC503
10U_0805_25VAK
2
1
1
1
PC500
2
1
PR502
2.2_0603_5%
EMC@ PC545
680P_0603_50V7K
75_0402_5%
1
1
PR503
2
2
@
PR501
0_0402_5%
130_0402_1%
1
1U_0603_10V6K
2
PR500
2
1
+VCCIO_OUT
PC502
10U_0805_25VAK
2
1
2
CPU_B+
PC501
0.22U_0603_16V7K
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+VCC_CORE
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
61
of
67
A
B
C
Iada=0~12.3A240W)
ADP_I = 20*Iadapter*Rsense
PR701
0.005_1206_1%
+SDC_IN
S
PQ702
NTR4502PT1G_SOT23-3
S
PQ700
PQ703A
SI3993CDV
NTR4502PT1G_SOT23-3
1
D
6
<51,55>
16
29
PR757
10K_0402_5%
2
1
+3.3V_ALW
1
2
3
5
4
IADP
IDCHG
LODRV
23
LX_CHG
EMI Part (35.33)
PL701
4.7UH_5.5A_20%_7X7X3_M
1
PROCHOT#
GND
CMPIN
ILIM
22
LGATE_CHG
PR764
46.4K_0402_1%
1
2
21
1
PMON
PQ705
+3.3V_ALW
4
CMPOUT
BATPRES#
SRN
TB_STAT#
BATDRV
PWPD
BATSRC
BQ24780
GNDA_CHG
20
19
18
17 CHG
1
21
PR760
14.7K_0402_1%
6
DMN66D0LDW-7_SOT363-6
PQ707A
TB_STAT#
<50,62>
2
1
CHG
4
2
3
CSOP_1
SNUB_CHG
PC712
0.1U_0402_25V6
1
2
2
+VCHGR
PR723
0.01_1206_1%
CSON_1
PC710
0.1U_0402_25V6
1
2
PD703
MM3Z22VST1G_SOD323-2
@
PC713
0.1U_0402_25V6
1
2
PJP701
1
<50,62>
UGATE_CHG
27
3
2
1
PHASE
26
1
HIDRV
ACOK
2
CSSN_2
1
ACN
SCL
PC708
10U_0805_25V6K
2
1
CSSP_2
4
ACP
SDA
SRP
15
PR765
PC734
2.2_0603_5%
0.047U_0603_50V7
1
2
2
1
PC715
10U_0805_25V5K~D
2
1
CMPOUT 14
25
EMI Part (47.1)
2
13
CMPIN
PQ704
1
10
PR728
0_0402_5%
1
2
PBAT_PRES#
2
1
2
0_0402_5%
2
BTST
<48>
PC719
10U_0805_25V5K~D
2
1
H_PROCHOT#
PR725
1
ACDRV
1
PR706
2
9
REGN
ACDET
DOCK_DCIN_IS-
PC718
10U_0805_25V5K~D
2
1
GNDA_CHG
Current limit
Charger :5.12A Vilim=1.024V
8 Cell (0.8C )
Max Boost Charger :6.4A, Vilim=0.32V
4.12K_0603_1%
PR719
316K_0402_1%
2
8
0_0402_5%
2
0_0402_5%
2
GNDA_CHG
<51,61,7>
5
CMSRC
2.2U_0603_10V6K
24
2
I_BATT
12
7
2
<51>
I_ADP
11
<63>
PC714
1
2
BQ24780_REGN
4.99K_0402_1%
1
<51>
PR720
121K_0402_1%
PR716
1
PR726
1
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
VCC
1
0_0402_5% DK_CSS_GC
2
CHARGER_SMBCLK
2
PR714
PR758
2
<51>
ACAV_IN
1
<17,51,63>
6
1
CHARGER_SMBDAT
PU700
28
+DCIN
3
PR727
1
PR729
1
PR721
1
0.1U_0402_25V4Z~D
<51>
PC709
1U_0603_25V6K
2
1
PC720
100P_0402_50V8J
1
2
1
2
PC711
GNDA_CHG
PR722
100K_0402_1%
1
PR718
49.9K_0402_1%
2
1
2
PR717
10_1206_5%
+SDC_IN
PC721
100P_0402_50V8J
1
2
BQ24780_REGN
AC Det (typ 2.4V)
Max:17.77V
Typ :17.60V
Min :17.42V
0.1U_0402_25V6
PR712
100K_0402_1%
2
1
PC704
1
2
SDMK0340L-7-F_SOD323-2~D
PR709
2
1
100K_0402_1%
PC703
0.1U_0402_25V6
1
2
PR711
0_0402_5%
PR713
100_0402_1%
2
1
@EMC@ PC706
0.1U_0603_25V7K
2
1
CSSN_1
1
1
2
PC702
1U_0603_25V6K
1
2
1
PR710
0_0402_5%
4
D
PD702
2
PBATT+
2
<48>
G
BAT54CW_SOT323-3
PQ703B
SI3993CDV
S
PR704
1K_0402_1%
2
1
2
1
3
+DC_IN_SS
DOCK_DCIN_IS+
PR715
110_0402_1%
G
CSSP_1
1
PD701
2
+DOCK_PWR_BAR
PC707
10U_0805_25V6K
2
1
S
5
2
<63>
EMC@ PC717 EMC@ PR724
680P_0402_50V7K
4.7_1206_5%
2
G
@EMC@ PC705
2200P_0402_50V7K
2
1
DC_BLOCK_GC
D
2
G
SIR472DP-T1-GE3_POWERPAK8-5
1
0_0402_5%
D
FDMC7692S_MLP8-5
2
PR700
1
PR703
0_0402_5%
@
5
1
2
CSS_GC
3
3
2
1
4
<63>
4
2
1
2
1
1
2
3
5
EMI Part (47.1)
1
3
+DC_IN_SS
1
ES2AA-13-F
PQ701 SI7149DP
3
1
PC700
0.1U_0603_25V7K
@ PD700
2
D
+CHAGER_SRC
EMC@ PL700
1UH_PCMB053T-1R0MS_7A_20%
2
1
+PWR_SRC
2
2
TB_STAT#
PR761
10_0402_1%
1
GNDA_CHG
GNDA_CHG
PAD-OPEN1x1m
GNDA_CHG
PR762
10_0402_1%
2
1
3
3
+DC_IN
1
CMP_REF=2.3V
+DC_IN>17.6V then ACAV_IN_NB high
2
PR737
665K_0402_1%
PC737
100P_0402_50V8J
CMPOUT
2
PR738
3M_0402_5%
1
CMPIN
1
PR745
100K_0402_1%
2
1
1
2
2
1
ACAV_IN_NB
2
PR743
<51,63>
PC741
100P_0402_50V8J
2
PR740
10K_0402_1%
1
0_0402_5%
4
4
+3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Charger
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
D
Sheet
62
of
67
5
4
3
2
1
PD1001 PDS5100H-13_POWERDI5-3~D
2
1
3
1
+DOCK_PWR_BAR
PQ1001
SI7149DP
1
2
3
2
1
4
5
D
PC1001
0.47U_0805_25V7K~D
2
PR1001
330K_0402_5%
D
2
PR1002
1 STSTART_DCBLOCK_GC
0_0402_5%
PD1002
2
1
3
PR1003
330K_0402_5%
PDS5100H-13_POWERDI5-3~D
+PWR_SRC
2
4
1
AO4407AL_SO8
1
2
3
@
PC1003
0.1U_0402_25V6
2
1
PQ1004
8
7
6
5
PC1005
1U_0603_25V6K
1
PC1004
1U_0603_25V6K
2
1
2BLK_MOSFET_GC
0_0402_5%
2
1
PR1006
2
PBATT_IN_SS
4
1
PR1004
0_0402_5%
4
2
AO4407AL_SO8
8
7
6
5
PR1005
1K_1206_5%
PQ1003
1
2
3
PC1002
2200P_0402_50V7K
2
1
1
PBATT+
PQ1002
SI4835DDY-T1-E3_SO8
8
1
7
2
6
3
5
+VCHGR
@
PQ1072
NTR4502PT1G_SOT23-3
<48>
+SDC_IN
SOFT_START_GC
1
PR1017
1
PR1015
PU1001
2
ACAVDK_SRC
0_0402_5%
2
0_0402_5%
ERC1
CD3301_SDC_IN
<62>
<17,51,62>
ACAV_IN
B
DC_BLOCK_GC
1
PR1021
1
2
3
4
5
6
7
8
ACAVIN
P33ALW2 9
2
0_0402_5%
37
2
0_0402_5%
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
TP
P50ALW
CD_PBATT_OFF
P50ALW
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
GND
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
1
PD1010
3
1
1
PR1012
2
+5V_ALW
0_0402_5%
1
PR1016
2
0_0402_5% SLICE_BAT_ON
DOCK_AC_OFF
<48>
2
PQ1011
SSM3K7002FU_SC70-3~D
2
2
1
3
S
2
PR1031
330K_0402_5%
BAT54CW_SOT323-3
<50>
1
2
PR1014 0_0402_5%
27
26
25
24
23
22
21
20
19
1
DK_AC_OFF
3301_ACAV_IN_NB
1
PR1019
DK_AC_OFF_EN
SL_BAT_PRES#
2
0_0402_5%
1
PR1020
ACAV_IN_NB
<51,62>
2
0_0402_5%
2
1M_0402_5%
PR1018
DOCK_AC_OFF_EC
<50>
BLKNG_MOSFET_GC
1
2
PR1023 0_0402_5%
1
2
CD3301_NBDOCK_DC_IN_SS
PR1024 0_0402_5%
B
SLICE_BAT_PRES#
<48,50,55,63>
+NBDOCK_DC_IN_SS
CD3301BRHHR
CSS_GC
DK_CSS_GC
ERC3
ERC2
<62>
1
2
+3.3V_ALW
PR1025 0_0402_5%
P33ALW
EN_DK_PWRBAR
PC1009
0.1U_0402_25V6
2
1
<62>
PC1008
0.047U_0603_25V7K~D
2
1
PC1007
0.1U_0603_25V7K
2
1
100K_0402_5%
PR1100
2
1
1
SDMK0340L-7-F_SOD323-2
10
11
12
13
14
15
16
17
18
+3.3V_ALW2
1
PR1022
D
2
G
SLICE_BAT_PRES#
1
2
@ PR1032 0_0402_5%
100K_0402_5%
2
ACAV_DOCK_SRC#
2
PR1009
0_0402_5%
1
PR1013
1
1
PD1100
36
35
34
33
32
31
30
29
28
<55>
+3.3V_ALW2
PR1030
2
1
<48,50,55,63>
NC
CHARGERVR_DCIN
DC_IN_SS
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
0.1U_0603_50V4Z
AC_DIS
10K_0402_5%
CSS_GC
DK_CSS_GC
ERC3
ERC2
GND
PWR_SRC
SS_DCBLK_GC
EN_DK_PWRBAR
P33ALW
PC1006
<51,55>
DSCHRG_MOSFET_GC
2 CD3301_DCIN
47_0805_5%
1
+DC_IN
3301_DC_IN_SS
2
1
PR1011
PR1008
0_0402_5%
DK_PWR_BAR
1
G
+DC_IN_SS
3
+3.3V_ALW2
C
D
1
2
PR1007 0_0402_5%
1
2
0_0402_5%
PR1010
+DOCK_PWR_BAR
S
2
C
@
1
2
PR1027 0_0402_5%
EN_DOCK_PWR_BAR
1
3301_PWRSRC
1
<50>
2
1M_0402_5%
@ PR1028
STSTART_DCBLOCK_GC
2
PR1029
0_0402_5%
+PWR_SRC
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Selector
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
63
of
67
5
4
3
2
1
Based on SB PDDG rev 2.0 Table 5-2
+VCC_CORE
+VCC_CORE
1
D
1
2
1
PC900
10U_0603_4VAM
2
1
PC901
10U_0603_4VAM
2
1
PC902
10U_0603_4VAM
2
1
+
PC903
10U_0603_4VAM
+
PC905
1
+
PC906
1
PC907
+
D
PC908
330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D
2
2
2
2
+VCC_CORE
1
2
1
PC917
22U_0805_6.3VAM
2
1
PC918
22U_0805_6.3VAM
2
1
PC919
22U_0805_6.3VAM
2
1
PC920
22U_0805_6.3VAM
2
PC921
22U_0805_6.3VAM
1
2
1
PC966
22U_0805_6.3VAM
2
1
PC965
22U_0805_6.3VAM
2
1
PC967
22U_0805_6.3VAM
2
1
2
1
2
1
2
1
PC953
1U_0402_6.3V6K
2
1
PC962
1U_0402_6.3V6K
2
PC961
1U_0402_6.3V6K
PC957
1U_0402_6.3V6K
1
2
2
PC958
1U_0402_6.3V6K
PC964
22U_0805_6.3VAM
1
PC968
22U_0805_6.3VAM
1
2
PC959
1U_0402_6.3V6K
2
PC960
1U_0402_6.3V6K
PC956
1U_0402_6.3V6K
PC952
1U_0402_6.3V6K
1
PC943
22U_0805_6.3VAM
2
2
B
C
PC963
1U_0402_6.3V6K
2
2
PC954
1U_0402_6.3V6K
1
2
1
PC942
22U_0805_6.3VAM
2
2
1
PC941
22U_0805_6.3VAM
1
2
1
PC940
22U_0805_6.3VAM
PC948
1U_0402_6.3V6K
PC939
22U_0805_6.3VAM
2
1
1
PC955
1U_0402_6.3V6K
1
2
PC951
1U_0402_6.3V6K
2
PC938
22U_0805_6.3VAM
PC949
1U_0402_6.3V6K
1
2
PC947
1U_0402_6.3V6K
2
PC937
22U_0805_6.3VAM
PC950
1U_0402_6.3V6K
1
2
1
1
PC936
22U_0805_6.3VAM
PC946
1U_0402_6.3V6K
2
2
1
2
PC935
22U_0805_6.3VAM
1
1
2
1
2
1
1
2
PC945
1U_0402_6.3V6K
PC926
22U_0805_6.3VAM
1
2
PC925
22U_0805_6.3VAM
PC944
1U_0402_6.3V6K
2
2
PC924
22U_0805_6.3VAM
1
1
2
PC923
22U_0805_6.3VAM
1
2
PC922
22U_0805_6.3VAM
1
1
2
1
1
1
2
C
2
1
+VCC_CORE
B
PC969
22U_0805_6.3VAM
1
PC971
22U_0805_6.3VAM
2
PC970
22U_0805_6.3VAM
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR DECOUPLING
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
64
of
67
5
4
3
2
+1.05V_RUN
Timing Diagram for S5 to S0 mode
+1.05V_M
VCC
VCCIO
VCCUSBPLL
V_PROC_IO
VCCCLK
PWRBTN#
SIO_PWRBTN#
RSMRST#
PCH_RSMRST#_R
SLP_S5#
VCCASW
+1.5V_RUN
VCCADAC
VCCVRM
13
PM_DRAM_PWRGD_CPU
VCCADACBG3_3
VCC3_3_R30
VCC3_3_R32
VCC3_3
VCCCLK3_3
VCC
SM_DRAMPWROK
+VCCIO_OUT
VCCIO_OUT
14
H_CPUPWRGD
3
+VCOMP_OUT
PWRGOOD
CPU_PLTRST#_R
SIO_SLP_S3#
SLP_WLAN#/GPIO29
VCCDSW3_3
+1.35V_MEM
PLTRSTIN
SLP_S3#
SIO_SLP_A#
PWROK
DRAMPWROK
+RTC_CELL
VDDQ
5
SIO_SLP_WLAN#
D
SYS_PWROK
RESET_OUT#
PCH_PWROK
+3.3V_ALW
VCOMP_OUT
16
SIO_SLP_S4#
SLP_LAN# SIO_SLP_LAN#
+3.3V_RUN
+VCC_CORE
D
4
SIO_SLP_S5#
SLP_S4#
SLP_A#
+3.3V_ALW_PCH
VCCSUS3_3
VCCSUSHDA
1
15
12
PM_DRAM_PWRGD_R
13
VCCRTC
PROCPWRGD H_CPUPWRGD
+3.3_M
CPU
VCCSPI
1.35V_SUS_PWRGD
14
RT8207
15
PCH_PLTRST#
7
4
PLTRST#
PM_APWROK_R
APWROK
PCH_DPWROK
DPWROK
PCH
+3.3V_ALW
ENVDD_PCH
+LCDVDD
LCD_VCC_TEST_EN
APL3512
DGPU_PWR_EN
10
MXM
MXM_ENVDD
EC
MXM
C
C
Power Button
+5V_ALW
RUN_ON
+5V_RUN
TPS22966
+5V_HDD
1BAT
2AC
+3.3V_ALW
TPS22966
+PWR_SRC
9
+3.3V_RUN
ADAPTER
ALWON
1BAT
+5V_ALW
+3.3V_ALW
TPS51225
2AC
ALW_PWRGD_3V_5V
APL5930
+1.5V_RUN
+1.05V_M
BATTERY
SI4164DY
+1.05V_RUN
4
B
PCH_RSMRST#
B
+3.3V_ALW
PCH_ALW_ON
+PWR_SRC
IMVP_VR_ON
ISL95812
SIO 5048
PCH
+VCC_CORE
11
RT8207MZ
TPS22966
12
8
+1.35V_MEM
VDDQ
+0.675V_DDR_VTT
VTT
1.35V_SUS_PWRGD
+3.3V_SSD
TPS22966
+3.3V_ALW
SIO_SLP_S3#
A_ON
SIO_SLP_S4#
3
6
6
TPS22966
+3.3V_M
SIO_SLP_S5#
SIO_SLP_LAN#
NVRAM_PWR_EN
SIO_SLP_S4#
TPS22966
+3.3V_SUS
+PWR_SRC
8
A_ON
+5V_ALW
AUX_EN_WOWL
TPS22966
+5V_MOD
11
EN_INVPWR
3.3V_WWAN_EN
A
+1.05V_M
TPS51212
6
+PWR_SRC
+3.3V_ALW
TPS22965
+3.3V_LAN
+3.3V_ALW
MODC_EN
+3.3V_WWAN
TPS22966
EC 5085
DDR
5
CPU
RESET_OUT#
+3.3V_ALW
+3.3V_WLAN
+3.3V_ALW_PCH
SIO_SLP_LAN#
PCH
+PWR_SRC
+3.3V_ALW
PM_APWROK
PCH_PWROK
SIO_SLP_S4#
0.675V_DDR_VTT_ON
7
FDC654P
+BL_PWR_SRC
A
BC BUS
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power Sequence
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
65
of
67
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist )
Item Page#
Title
D ate
R equest
O w ner
Issue D escription
Solution D escription
R ev.
D
D
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
EE P.I.R (1/4)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
66
of
67
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist )
Item Page#
Title
D ate
R equest
O w ner
Issue D escription
Solution D escription
R ev.
D
D
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PWR P.I.R (1/1)
Size
Document Number
Date:
Monday, January 13, 2014
Rev
0.1
LA-B541P
Sheet
1
67
of
67
www.s-manuals.com
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