Compal NM A032 Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal NM-A032 VIQY1 - Schematics. Free.

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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Intel Haswell Processor with DDRIII + Lynx point PCH
2013-03-19 Rev1.0
nVIDIA N14P GT + 2nd VGA N14P GT
VIQY1
NM_A032 Rev1.0 Schematic
(Y510)
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Cover Page
Custom
1 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Cover Page
Custom
1 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Cover Page
Custom
1 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Page 52 Page 50
NOVO/B Conn.
Page 52
ODD/B Conn.
page 44
GDDR5* 8
2nd VGA, N14P-GT1
VRAM 64*32
N14P-GT1
GDDR5* 8
VRAM 64*32
Intel CPU
Haswell
rPGA946
37.5mm*37.5mm
Memory BUS (DDRIII)
Dual Channel
1.35V DDRIIIL 1066/1333/1600 MT/s
Atheros
QCA8171-BL3A-R
PCIe port 3
RJ45 Conn.
1.5V 5GT/s
PCIe Gen1
Page 41
Intel PCH
Lynx point
FCBGA 695Balls
20mm*20mm
Page 13,14,15,16,17,18,19,20,21,22
Page 5,6,7,8,9,10
SPI ROM
(4MB+2MB)
Page 17
EC
ITE IT8586E-FX
Page 46
Debug Port
Page 40
3.3V 33MHz
POWER/B Conn. AUDIO, USB/B Conn.
Page 42
Page 32 Page 23,24,25,26,27,28,29,30,31,33
PEG 0~7PEG 8~15
Page 35
SPI BUS
3.3V 33MHz
Page 56,57,58,59,60,61,
62,63,64,65,66
Power Circuit DC/DC
Page 55
DC/DC Interface CKT.
Page 56
RTC CKT.
Touch Pad
Page 47
Int.KBD
Page 47
Thermal Sensor
EMC 1403
Page 43
Sub/B
UP TO 16G
PCI-Express 16X Gen3
LPC BUS
BANK 0, 1, 2, 3
DDR3-SO-DIMM X2
LVDS Conn.
DMI *4
5GT/s
USB 2.0 Port 2
USB 3.0 Port 2
USB Left
Page 49
USB 2.0 Port1
5V 480MHz
USB 3.0
5V 5GT/s
PCIeMini Card
WLAN
page 40
PCIe Port 4
NGFF SSD
page 40
SATA Port 4
PCIeMini Card
WLAN
USB Port 10
page 40
USB 2.0
5V 480MHz
PCIe Gen1
5V 480MHz
SATA Gen3
5V 6GHz(600MB/s)
SATA Gen3 Port 5
3V 6GHz(600MB/s)
SATA HDD
SATA Port 5
SATA Gen1 Port2
3V 3GHz(300MB/s)
SATA ODD
SATA Port 2
Page 45
Codec
ALC282CG
HD Audio
3.3V 24MHz
Page 45
Int. MIC Conn.
(JCMOS Conn.)
Page 35 Page 50
Ext. MIC Conn.
Sub/B
Page 50
HP Conn.
Sub/B
SPK Conn.
MUX
eDP
eDP
LVDS
Page 38
eDP to LVDS
Page 34
PS8625
Page 35
Int. Camera
USB 2.0 Port 0
USB Charger
Page 50
Sub/B
5V 5GT/s
USB 3.0 Port6
5V 480MHz
USB 2.0 Port4
Card reader
Page 48
USB Charger IC
Page 50
5V 480MHz
USB 2.0
Card reader IC
GL3213
Page 48
USB 2.0 Port 3
USB 3.0 Port 5
Page 49
USB Left
page 44
page 44
Page 39 Page 36
HDMI Conn. CRT Conn.
MUX
Page 37
MUX
Page 37
HDMI
CRT
HDMI1.4b
Page 50
Touch panel
USB 2.0 Port 8
FDI *2
2.7GT/s
Conn.
GL887T
Conn.
Page 11,12
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Block Diagram
Custom
2 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Block Diagram
Custom
2 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Block Diagram
Custom
2 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+3VALW
+3VALW
SOURCE
IT8580EEC_SMB_CK1
EC_SMB_DA1 X
STATE SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
+3VS
+5VS
+CPU_CORE
+VCCSA
Power Plane
O
State
+1.5VS
+GFX_CORE
+1.8VS
+1.5VS_VGA
+1.05VS
+VGA_CORE
Thermal Sensor EMC1403-2
1001_101xb
EC SM Bus1 address
Device
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
PCH SM Bus address
Device Address
Address
Address
EC SM Bus2 address
Device
Smart Battery
0001 011X b
+0.75VS
+1.05VS_VGA
+V1.5S_VCCP
+3.3VS_VGA
Master VGA
0x9E
Slave VGA
0x9C
LAN
6
4
5
3
2
1
7
8
PCIE PORT LIST
USB Port (Left Side)
WLAN
Card Reader
Port Device
Camera
USB 3.0USB 2.0 Port 4 External
USB Port
USB Port (Right Side)
0
1
2
5
4
5
6
7
8
9
10
11
12
13
EHCI1
EHCI2
USB Port Table
Mini Card(WLAN)
XHCI
2
3
6
S0
S3
S5 S4/AC Only
S5 S4
Battery only
S5 S4
AC & Battery
don't exist
B+
+3VALW
+5VALW
+1.5V
O O O
OO
O
O
O
O
X X
X X
X
X
X
X
X
X
SMBUS Control Table
( O --> Means ON , X --> Means OFF )
X X XV
Main
VGA
2nd
VGA BATT SODIMM WLAN
WiMAX
Thermal
Sensor PCH
IT8580E
+3VS
IT8580E
+3VS
PCH
V
+3V_PCH
X
EC_SMB_CK2
EC_SMB_DA2 V
+3VS +3VS
V+3VS
V
SMB_CLK_S3
SMB_DATA_S3 +3VS
V V
+3V_PCH+3VS
V
TP
Module
X
+3VS
V
XX
X
X
X
X
X
X X X X X
USB Port (Left Side)
Touch panel
AOAC support part
NV GT750M
GT@
@
Unpop
AOAC@
ME@
KBL@
NOGC6@
CMOS@
CMOS Camera part
Deep S3 support part
ME part
DS3@
X76@
X76 Level part for VRAM
K/B Light part
GC6@
NV CG6 support part
NV no CG6 support part
SURGE@
QCA8171 LAN surge part
BTO ItemBOM Structure
BOM Structure Table
GT1@
NV GT755M
887T@
GENESYS 887T USB charger solution
TI@
TI USB charger solution
887@
GENESYS 887 USB charger solution
SLI@
For SLI function part
47W@
37W@
For 37W CPU part
For 47W CPU part
Support daul channel panel function
daul@
Support EDP panel function
EDP@
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Notes List
Custom
3 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Notes List
Custom
3 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Notes List
Custom
3 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
ZZZ1
DAZ0SF00100
ZZZ1
DAZ0SF00100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5VS_VGA
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
+3VS_VGA
+1.05VS_VGA
+VGA_CORE
Products
GPU Mem NVCLK
/MCLK NVVDD FBVDD FBVDDQ PCI Express I/O and
PLLVDD I/O and
PLLVDD Other
(3.3V)(1.05V)(1.8V)
(1.05V)
(1.35V)(1.35V) (GPU+Mem)
(4) (1,5) (6)
(V) (A) (W) (A) (W)
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
N14X
128bit
1GB
GDDR5
(W) (W) (MHz)
TBD TBDTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
tFBVDDQ >0
tNVVDD >0
tPEX_VDD >0
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
FB[1]
3GIO_PAD_CFG_ADR[0]
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP3
STRAP4
+3VS_VGA
+3VS_VGA
SOR3_EXPOSED
RESERVED PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED DP_PLL_VDD33V
SOR2_EXPOSED SOR1_EXPOSED
Power Rail
+3VS_VGA
ROM_SCLK
SOR0_EXPOSED
Logical
Strapping Bit3
Logical
Strapping Bit2
SLOT_CLK_CFG
Logical
Strapping Bit0
SUB_VENDOR PEX_PLL_EN_TERM
RAM_CFG[0]
STRAP0
STRAP1
STRAP2
ROM_SI RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
VGA_DEVICESMB_ALT_ADDR
PCI_DEVID[4]
ROM_SO FB[0]
Logical
Strapping Bit1
Physical
Strapping pin
N13P-GT
(28nm) 0x0FCD
Device ID
1.all GPU power rails should be turned off within 10ms
Tpower-off <10ms
+3VS_VGA
Other Power rail
SMB_ALT_ADDR 0
I2C Slave addrees ID
1
0x9E
0x9C
(ROM_SO Bit 1)
setting
IN FB_CLAMP_MON-
NVVDD PWM_VID-OUT
-
-
-
-
-
- VGA_ENBKL
VGA_BL_PWM
VGA_ENVDD
-
-
NA
DGPU_HDMI_HPD
-
NA
NA
-NA
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
NA
FB_CLAMP_TOGGLE_REQ#
-
GPIO I/O ACTIVE Function Description
-
-
IN
OUT
IN
IN
IN
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
VGA and GDDR5 Voltage Rails (N14Px GPIO)
(10K pull High)
OVERT#
VGA_ALERT#
Memory VREF Control
AC Power Detect Input
VGA_EDP_HPD
-
-
-
Hot plug detect for IFP link E
NAOUT
DPRSLPVR_VGA -
-
NA
PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K
Master
Slave
N14P-GT1
ROM_SI
64Mx32 PD 25K
64Mx32
64Mx32
K4G20325FD-FC04
H5GQ2H24AFR-T2CHynix
2500MHz
Samsung
2500MHz
H5GQ2H24AFR-R0C
K4G20325FD-FC03
ROM_SI
Samsung
3000MHz
GPU
PD 30K
FB Memory (GDDR5)
Hynix
3000MHz
64Mx32
PD 15K
N14P-GT
28nm
PD 5K
ROM_SO ROM_SCLK
GPU STRAP2STRAP1STRAP0
PU 45K
PD 30K
PD 25K
PU 10K PD 25K
N14P-GT
STRAP3
PU 5K PD 45K
STRAP4
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA Notes List
Custom
4 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA Notes List
Custom
4 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA Notes List
Custom
4 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
DMI_CRX_PTX_N0
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P1
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CSYNC_R
FDI_INT_R
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PEG_COMP
PEG_COMP
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N12
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N12
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P4
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P3
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
PCIE_CRX_GTX_N[0..15] <23,32>
PCIE_CRX_GTX_P[0..15] <23,32>
PCIE_CTX_C_GRX_N[0..15] <23,32>
PCIE_CTX_C_GRX_P[0..15] <23,32>
FDI_CSYNC<15>
FDI_INT<15>
+VCCIOA_OUT
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
0.1
CPU (1/7) DMI, FDI, PEG
Custom
5 69
Wednesday, March 20, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
0.1
CPU (1/7) DMI, FDI, PEG
Custom
5 69
Wednesday, March 20, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
0.1
CPU (1/7) DMI, FDI, PEG
Custom
5 69
Wednesday, March 20, 2013
2012/07/01 2014/07/01
CC7 0.22U_0402_10V6KCC7 0.22U_0402_10V6K
1 2
CC11 0.22U_0402_10V6KCC11 0.22U_0402_10V6K
1 2
CC2 0.22U_0402_10V6KCC2 0.22U_0402_10V6K
1 2
RC224.9_0402_1% RC224.9_0402_1%
12
CC27 0.22U_0402_10V6KCC27 0.22U_0402_10V6K
1 2
RC3 0_0402_5%RC3 0_0402_5%
12
CC22 0.22U_0402_10V6KCC22 0.22U_0402_10V6K
1 2
CC6 0.22U_0402_10V6KCC6 0.22U_0402_10V6K
1 2
CC31 0.22U_0402_10V6KCC31 0.22U_0402_10V6K
1 2
DMI FDI
PEG
Haswell rPGA EDS
1 OF 9
JCPUA
INTEL_HASWELL_HASWELL
DMI FDI
PEG
Haswell rPGA EDS
1 OF 9
JCPUA
INTEL_HASWELL_HASWELL
PEG_TXP_15 B24
PEG_TXP_14 C25
PEG_TXP_13 B26
PEG_TXP_12 C27
PEG_TXP_11 B28
PEG_TXP_10 C29
PEG_TXP_9 B30
PEG_TXP_8 C31
PEG_TXP_7 A32
PEG_TXP_6 B33
PEG_TXP_5 H30
PEG_TXP_4 H31
PEG_TXP_3 G32
PEG_TXP_2 H33
PEG_TXP_1 G34
PEG_TXP_0 J35
PEG_TXN_15 A24
PEG_TXN_14 B25
PEG_TXN_13 A26
PEG_TXN_12 B27
PEG_TXN_11 A28
PEG_TXN_10 B29
PEG_TXN_9 A30
PEG_TXN_8 B31
PEG_TXN_7 B32
PEG_TXN_6 C33
PEG_TXN_5 G30
PEG_TXN_4 J31
PEG_TXN_3 H32
PEG_TXN_2 J33
PEG_TXN_1 H34
PEG_TXN_0 H35
PEG_RXP_15 D32
PEG_RXP_14 F33
PEG_RXP_13 E34
PEG_RXP_12 F35
PEG_RXP_11 E30
PEG_RXP_10 F31
PEG_RXP_9 E28
PEG_RXP_8 F29
PEG_RXP_7 K34
PEG_RXP_6 L35
PEG_RXP_5 K32
PEG_RXP_4 L33
PEG_RXP_3 K30
PEG_RXP_2 L31
PEG_RXP_1 L28
PEG_RXP_0 L29
PEG_RXN_15 E32
PEG_RXN_14 E33
PEG_RXN_13 D34
PEG_RXN_12 E35
PEG_RXN_11 D30
PEG_RXN_10 E31
PEG_RXN_9 D28
PEG_RXN_8 E29
PEG_RXN_7 L34
PEG_RXN_6 M35
PEG_RXN_5 L32
PEG_RXN_4 M33
PEG_RXN_3 L30
PEG_RXN_2 M31
PEG_RXN_1 K28
PEG_RXN_0 M29
PEG_RCOMP E23
FDI_INT
J29 FDI_CSYNC
H29
DMI_TXP_3
A18 DMI_TXP_2
B18 DMI_TXP_1
C18 DMI_TXP_0
D17
DMI_TXN_3
A17 DMI_TXN_2
B17 DMI_TXN_1
C17 DMI_TXN_0
D18
DMI_RXP_3
A20 DMI_RXP_2
B20 DMI_RXP_1
C20 DMI_RXP_0
D20
DMI_RXN_3
A21 DMI_RXN_2
B21 DMI_RXN_1
C21 DMI_RXN_0
D21
CC3 0.22U_0402_10V6KCC3 0.22U_0402_10V6K
1 2
CC32 0.22U_0402_10V6KCC32 0.22U_0402_10V6K
1 2
CC15 0.22U_0402_10V6KCC15 0.22U_0402_10V6K
1 2
CC5 0.22U_0402_10V6KCC5 0.22U_0402_10V6K
1 2
CC24 0.22U_0402_10V6KCC24 0.22U_0402_10V6K
1 2
CC12 0.22U_0402_10V6KCC12 0.22U_0402_10V6K
1 2
CC17 0.22U_0402_10V6KCC17 0.22U_0402_10V6K
1 2
CC4 0.22U_0402_10V6KCC4 0.22U_0402_10V6K
1 2
CC20 0.22U_0402_10V6KCC20 0.22U_0402_10V6K
1 2
CC30 0.22U_0402_10V6KCC30 0.22U_0402_10V6K
1 2
CC8 0.22U_0402_10V6KCC8 0.22U_0402_10V6K
1 2
CC29 0.22U_0402_10V6KCC29 0.22U_0402_10V6K
1 2
CC21 0.22U_0402_10V6KCC21 0.22U_0402_10V6K
1 2
CC9 0.22U_0402_10V6KCC9 0.22U_0402_10V6K
1 2
RC87 0_0402_5%RC87 0_0402_5%
12
CC10 0.22U_0402_10V6KCC10 0.22U_0402_10V6K
1 2
CC13 0.22U_0402_10V6KCC13 0.22U_0402_10V6K
1 2
CC14 0.22U_0402_10V6KCC14 0.22U_0402_10V6K
1 2
CC28 0.22U_0402_10V6KCC28 0.22U_0402_10V6K
1 2
CC25 0.22U_0402_10V6KCC25 0.22U_0402_10V6K
1 2
CC1 0.22U_0402_10V6KCC1 0.22U_0402_10V6K
1 2
CC26 0.22U_0402_10V6KCC26 0.22U_0402_10V6K
1 2
CC23 0.22U_0402_10V6KCC23 0.22U_0402_10V6K
1 2
CC18 0.22U_0402_10V6KCC18 0.22U_0402_10V6K
1 2
CC16 0.22U_0402_10V6KCC16 0.22U_0402_10V6K
1 2
CC19 0.22U_0402_10V6KCC19 0.22U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
DDR3 COMPENSATION SIGNALS
Reserve for Deep S3
Buffered Reset to CPU
SM_DRAMPWROK with DDR Power Gating Topology
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
1.05V
PU/PD for JTAG signals
For ESD concern, please put near CPU
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
For ESD
20120806 VA
change XDP connector to 28 pin
Place near JXDP1
XDP Connector
RC5 need to close to JCPU1
497750_497750_SHRKBY_MBL_SCH_CHKLST 0.5
page19 item 3.6 SM_DRAMPWROK
CLK_CPU_DMI#
CLK_CPU_DMI
XDP_TCLK
BUF_CPU_RST#
XDP_DBRESET#XDP_DBRESET#_R
XDP_TDO XDP_TDO_R
XDP_TRST#
XDP_TDI XDP_TDI_R
XDP_TMS
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
H_DRAMRST#
H_DRAMRST#
DRAMRST_CNTRL
H_CATERR#
H_CATERR#
H_PROCHOT#
H_THRMTRIP#
H_PECI
H_PROCHOT#_R
H_THRMTRIP#
H_PM_SYNC
PM_DRAM_PWRGD_CPURUNPWROK_AND
PM_DRAM_PWRGD_CPU
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL#
CPU_SSC_DPLL
XDP_DBRESET#_R
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDO
XDP_TDI
XDP_PREQ#
XDP_PREQ#
XDP_PRDY#
XDP_OBS3_R
XDP_OBS5_R
XDP_OBS2_R
XDP_OBS1_R
XDP_OBS0_R
XDP_OBS4_R
XDP_OBS6_R
XDP_OBS7_R
XDP_OBS0
XDP_OBS1
VCCPWRGOOD_0_R
BUF_CPU_RST#
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_OBS2
XDP_OBS3
VCCPWRGOOD_0_RBUF_CPU_RST#
XDP_PREQ#_R
XDP_PRDY#_R
CPU_PWR_DEBUG
XDP_TDO_R
VGATE
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_DBRESET#
CLK_CPU_ITP
CLK_CPU_ITP#
CFD_PWRBTN#_XDP
XDP_OBS2
XDP_OBS3
XDP_OBS1
XDP_OBS0
H_CPUPWRGD H_CPUPWRGD_XDP
XDP_RST#_RBUF_CPU_RST#
DDR3_DRAMRST#_R
VCCPWRGOOD_0_R
CLK_CPU_DMI#<16>
CLK_CPU_DMI<16>
DRAMRST_CNTRL_EC<46>
DRAMRST_CNTRL<7>
DDR3_DRAMRST# <11,12>
DRAMRST_CNTRL_PCH<17>
H_PECI<46>
H_THRMTRIP#<19>
H_PROCHOT#<46,57>
H_PM_SYNC<15>
H_CPUPWRGD<19>
CLK_CPU_DPLL#<16>
CLK_CPU_DPLL<16>
CLK_CPU_SSC_DPLL#<16>
CLK_CPU_SSC_DPLL<16>
SYS_PWROK<15>
PM_DRAM_PWRGD<15>
RUN_ON_CPU1.5VS3#<10>
CPU_PLTRST#<19>
CPU_PWR_DEBUG<9>
SIO_PWRBTN#_R<15>
VGATE<15,64>
CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>
+1.05VS
+1.35V_CPU_VDDQ
+3V_PCH
+3V_PCH
+VCCIO_OUT
+1.05VS
+3VS
+1.05VS
+1.05VS
+1.35V
+VCCIO_OUT
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (2/7) PM, XDP, CLK
Custom
6 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (2/7) PM, XDP, CLK
Custom
6 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (2/7) PM, XDP, CLK
Custom
6 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RC64
39_0402_5%
@RC64
39_0402_5%
@
1 2
RC46
0_0402_5%
RC46
0_0402_5%
1 2
RC30 0_0402_5%RC30 0_0402_5%
1 2
RC52 0_0402_5%RC52 0_0402_5%
12
G
D
S
QC1
SSM3K7002FU_SC70-3
@
G
D
S
QC1
SSM3K7002FU_SC70-3
@
2
13
RC43 0_0402_5%RC43 0_0402_5%
12
RC33 0_0402_5%RC33 0_0402_5%
1 2
RC55 75_0402_1%RC55 75_0402_1%
1 2
RC6 0_0402_5%@RC6 0_0402_5%@
1 2
RC40 51_0402_1%RC40 51_0402_1%
12
CC156
0.1U_0402_25V6K
@
CC156
0.1U_0402_25V6K
@
1 2
RC88 0_0402_5%
@
RC88 0_0402_5%
@
12
RC130
10K_0402_5%
RC130
10K_0402_5%
12
RC62
1K_0402_5%
@RC62
1K_0402_5%
@
12
RC27 51_0402_1%@RC27 51_0402_1%@12
RC42 0_0402_5%
@
RC42 0_0402_5%
@
1 2
RC38 0_0402_5%RC38 0_0402_5%
1 2
RC25
R_short 0_0402_5%
RC25
R_short 0_0402_5%
1 2
RC1547 0_0402_5%@RC1547 0_0402_5%@
12
RC89
100K_0402_5%
RC89
100K_0402_5%
12
RC49 100_0402_1%RC49 100_0402_1%
1 2
RC26 0_0402_5%RC26 0_0402_5%
12
RC31 0_0402_5%RC31 0_0402_5%
1 2
CC65
0.1U_0402_25V6K
@
CC65
0.1U_0402_25V6K
@
1
2
RC53 0_0402_5%RC53 0_0402_5%
1 2
RC60
0_0402_5%
RC60
0_0402_5%
1 2
RC81K_0402_1% RC81K_0402_1%
1 2
RC14
3.3K_0402_1%
RC14
3.3K_0402_1%
12
RC41 51_0402_1%RC41 51_0402_1%
12
RC1544
4.99K_0402_1% @
RC1544
4.99K_0402_1% @
1 2
RC1545
R_short 0_0402_5%
RC1545
R_short 0_0402_5%
1 2
RC29 51_0402_1%@RC29 51_0402_1%@12
RC19 1K_0402_1%RC19 1K_0402_1%
12
RC5 1K_0402_1%RC5 1K_0402_1%
1 2
RC35 51_0402_1%@RC35 51_0402_1%@12
RC23 0_0402_5%RC23 0_0402_5%
1 2
RC126
100_0402_1%
@RC126
100_0402_1%
@
1 2
RC24 0_0402_5%RC24 0_0402_5%
1 2
CC60
220P_0402_25V8J
@CC60
220P_0402_25V8J
@
1
2
RC28 0_0402_5%RC28 0_0402_5%
12
CC66
0.1U_0402_25V6K
@
CC66
0.1U_0402_25V6K
@
1
2
RC2010K_0402_5% @RC2010K_0402_5% @
1 2
RC84
200_0402_5%
RC84
200_0402_5%
12
RC34 0_0402_5%RC34 0_0402_5%
1 2
RC32 51_0402_1%@RC32 51_0402_1%@12
RC51 0_0402_5%RC51 0_0402_5%
12
G
D
S
QC3
BSS138_NL_SOT23-3
@
G
D
S
QC3
BSS138_NL_SOT23-3
@
2
13
RC54 0_0402_5%RC54 0_0402_5%
1 2
RC50 0_0402_5%RC50 0_0402_5%
1 2
RC48 0_0402_5%RC48 0_0402_5%
1 2
RC39 0_0402_5%RC39 0_0402_5%
1 2
RC128
49.9_0402_1%
@RC128
49.9_0402_1%
@
1 2
RC1543
0_0402_5%
RC1543
0_0402_5%
1 2
RC36 0_0402_5%RC36 0_0402_5%
1 2
CC61
220P_0402_25V8J
@CC61
220P_0402_25V8J
@
1
2
RC47 0_0402_5%RC47 0_0402_5%
1 2
JXDP
MOLEX 52435-2671
@JXDP
MOLEX 52435-2671
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CC50
0.047U_0402_16V4Z@
CC50
0.047U_0402_16V4Z@
1
2
RC16
1.8K_0402_1%
RC16
1.8K_0402_1%
12
T55PAD @T55PAD @
RC37 0_0402_5%RC37 0_0402_5%
1 2
UC4
74AHC1G09GW_TSSOP5
UC4
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O4
P5
RC1539
100_0402_1%
RC1539
100_0402_1%
1 2
RC22 0_0402_5%RC22 0_0402_5%
12
RC44
62_0402_5%
RC44
62_0402_5%
1 2
PWR
DDR3
MISC
THERMAL
CLOCK
JTAG
Haswell rPGA EDS
2 OF 9
JCPUB
INTEL_HASWELL_HASWELL
PWR
DDR3
MISC
THERMAL
CLOCK
JTAG
Haswell rPGA EDS
2 OF 9
JCPUB
INTEL_HASWELL_HASWELL
BPM_N_7 AP28
BPM_N_6 AP29
BPM_N_5 AN28
BPM_N_4 AP30
BPM_N_3 AP31
BPM_N_2 AN29
BPM_N_1 AN31
BPM_N_0 AR30
DBR AP33
TDO AL33
TDI AM31
TRST AM33
TMS AN33
TCK AM34
PREQ AT29
PRDY AR29
SM_DRAMRST AN3
SM_RCOMP_2 AP2
SM_RCOMP_1 AR3
SM_RCOMP_0 AP3
BCLKP
E26 BCLKN
D26 SSC_DPLL_REF_CLKP
E27 SSC_DPLL_REF_CLKN
F27 DPLL_REF_CLKP
H28 DPLL_REF_CLKN
G28
PWRGOOD
AL34 PM_SYNC
AT28
PROCHOT
AM30 RSVD
AK31 PECI
AR27 CATERR
AN32
SKTOCC
AP32
PLTRSTIN
AT26 SM_DRAMPWROK
AC10
THERMTRIP
AM35
RC57 56_0402_5%RC57 56_0402_5%
1 2
RC2110K_0402_5% @RC2110K_0402_5% @
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
DDRA_DQ63
DDRA_DQ62
DDRA_DQ8
DDRA_DQ3
DDRA_DQ4
DDRA_DQ7
DDRA_DQ5
DDRA_DQ6
DDRA_DQ59
DDRA_DQ58
DDRA_DQ57
DDRA_DQ56
DDRA_DQ47
DDRA_DQ46
DDRA_DQ42
DDRA_DQ43
DDRA_DQ34
DDRA_DQ39
DDRA_DQ44
DDRA_DQ45
DDRA_DQ35
DDRA_DQ41
DDRA_DQ40
DDRA_DQ38
DDRA_DQ36
DDRA_DQ37
DDRA_DQ32
DDRA_DQ33
DDRA_DQ61
DDRA_DQ60
DDRA_DQ2
DDRA_DQ1
DDRA_DQ0
DDRA_DQ55
DDRA_DQ54
DDRA_DQ51
DDRA_DQ48
DDRA_DQ50
DDRA_DQ49
DDRA_DQ52
DDRA_DQ53
DDRA_DQ31
DDRA_DQ14
DDRA_DQ15
DDRA_DQ25
DDRA_DQ24
DDRA_DQ26
DDRA_DQ27
DDRA_DQ30
DDRA_DQ9
DDRA_DQ13
DDRA_DQ12
DDRA_DQ10
DDRA_DQ11
DDRA_DQ29
DDRA_DQ28
DDRA_DQ19
DDRA_DQ20
DDRA_DQ16
DDRA_DQ21
DDRA_DQ17
DDRA_DQ22
DDRA_DQ18
DDRA_DQ23
DDRA_MA15
DDRA_MA0
DDRA_MA14
DDRA_MA5
DDRA_MA4
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA9
DDRA_MA7
DDRA_MA6
DDRA_MA12
DDRA_MA13
DDRA_MA8
DDRA_MA11
DDRA_MA10
DDRA_DQS#7
DDRA_DQS#0
DDRA_DQS#2
DDRA_DQS#5
DDRA_DQS#3
DDRA_DQS#1
DDRA_DQS#4
DDRA_DQS#6
DDRA_DQS0
DDRA_DQS2
DDRA_DQS1
DDRA_DQS6
DDRA_DQS5
DDRA_DQS4
DDRA_DQS3
DDRA_DQS7+VREF_CA_R
+V_DDR_REFA_R
+V_DDR_REFB_R
DRAMRST_CNTRL
+V_DDR_REFA_R
DRAMRST_CNTRL
+V_DDR_REFB_R
DDRB_DQ33
DDRB_DQ14
DDRB_DQ42
DDRB_DQ59
DDRB_DQ63
DDRB_DQ43
DDRB_DQ55
DDRB_DQ53
DDRB_DQ29
DDRB_DQ24
DDRB_DQ34
DDRB_DQ4
DDRB_DQ26
DDRB_DQ13
DDRB_DQ10
DDRB_DQ21
DDRB_DQ11
DDRB_DQ57
DDRB_DQ44
DDRB_DQ0
DDRB_DQ7
DDRB_DQ46
DDRB_DQ3
DDRB_DQ15
DDRB_DQ27
DDRB_DQ30
DDRB_DQ35
DDRB_DQ40
DDRB_DQ49
DDRB_DQ23
DDRB_DQ25
DDRB_DQ19
DDRB_DQ37
DDRB_DQ48
DDRB_DQ36
DDRB_DQ18
DDRB_DQ8
DDRB_DQ47
DDRB_DQ9
DDRB_DQ60
DDRB_DQ50
DDRB_DQ62
DDRB_DQ52
DDRB_DQ2
DDRB_DQ51
DDRB_DQ56
DDRB_DQ39
DDRB_DQ22
DDRB_DQ28
DDRB_DQ6
DDRB_DQ45
DDRB_DQ17
DDRB_DQ58
DDRB_DQ61
DDRB_DQ31
DDRB_DQ54
DDRB_DQ1
DDRB_DQ41
DDRB_DQ5
DDRB_DQ12
DDRB_DQ20
DDRB_DQ38
DDRB_DQ32
DDRB_DQ16
DDRB_MA15
DDRB_MA0
DDRB_MA9
DDRB_MA7
DDRB_MA13
DDRB_MA2
DDRB_MA4
DDRB_MA11
DDRB_MA3
DDRB_MA5
DDRB_MA6
DDRB_MA10
DDRB_MA8
DDRB_MA1
DDRB_MA12
DDRB_MA14
DDRB_DQS#1
DDRB_DQS#7
DDRB_DQS#5
DDRB_DQS#4
DDRB_DQS#0
DDRB_DQS#3
DDRB_DQS#6
DDRB_DQS#2
DDRB_DQS7
DDRB_DQS0
DDRB_DQS1
DDRB_DQS5
DDRB_DQS4
DDRB_DQS3
DDRB_DQS2
DDRB_DQS6
DDRB_BS0# <12>
DDRB_BS1# <12>
DDRB_BS2# <12>
DDRB_WE# <12>
DDRB_RAS# <12>
DDRB_CAS# <12>
DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>
DDRB_CLK1 <12>
DDRB_CKE1 <12>
DDRB_CLK1# <12>
DDRA_DQ[0..63]<11>
DDRA_MA[0..15] <11>
DDRA_DQS#[0..7] <11>
DDRA_DQS[0..7] <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDRA_BS0# <11>
DDRA_BS1# <11>
DDRA_BS2# <11>
DDRA_CAS# <11>
DDRA_WE# <11>
DDRA_RAS# <11>
DDRA_CS0# <11>
DDRA_CS1# <11>
DDRA_CKE0 <11>
DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>
DRAMRST_CNTRL<6>
DDRB_DQ[0..63]<12>
DDRB_MA[0..15] <12>
DDRB_DQS#[0..7] <12>
DDRB_DQS[0..7] <12>
DDRB_ODT1 <12>
DDRB_ODT0 <12>
DDRB_CS1# <12>
DDRB_CS0# <12>
+VREF_DQ_DIMMB_R
+VREF_DQ_DIMMA_R
+VREF_CA_R
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (3/7) DDRIII
Custom
7 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (3/7) DDRIII
Custom
7 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (3/7) DDRIII
Custom
7 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RC1548 0_0402_5%RC1548 0_0402_5%
1 2
RC92 0_0402_5%RC92 0_0402_5%
1 2
T63 PAD@T63 PAD@
Haswell rPGA EDS
3 OF 9
JCPUC
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
3 OF 9
JCPUC
INTEL_HASWELL_HASWELL
RSVD_AC7 AC7
SA_CK_N_0 U4
SA_CK_P_0 V4
SA_CKE_0 AD9
SA_CK_N_1 U3
SA_CK_P_1 V3
SA_CKE_1 AC9
SA_CK_N_2 U2
SA_CK_P_2 V2
SA_CKE_2 AD8
SA_CK_N_3 U1
SA_CK_P_3 V1
SA_CKE_3 AC8
SA_CS_N_0 M7
SA_CS_N_1 L9
SA_CS_N_2 M9
SA_CS_N_3 M10
SA_ODT_0 M8
SA_ODT_1 L7
SA_ODT_2 L8
SA_ODT_3 L10
SA_BS_0 V5
SA_BS_1 U5
SA_BS_2 AD1
RSVD_V10 V10
SA_RAS U6
SA_WE U7
SA_CAS U8
SA_MA_0 V8
SA_MA_1 AC6
SA_MA_10 V6
SA_MA_11 AC1
SA_MA_12 AD4
SA_MA_13 V7
SA_MA_14 AD3
SA_MA_15 AD2
SA_MA_2 V9
SA_MA_3 U9
SA_MA_4 AC5
SA_MA_5 AC4
SA_MA_6 AD6
SA_MA_7 AC3
SA_MA_8 AD5
SA_MA_9 AC2
SA_DQS_N_0 AP15
SA_DQS_N_1 AP8
SA_DQS_N_2 AJ8
SA_DQS_N_3 AF3
SA_DQS_N_4 J3
SA_DQS_N_5 E2
SA_DQS_N_6 C5
SA_DQS_N_7 C11
SA_DQS_P_0 AP14
SA_DQS_P_1 AP9
SA_DQS_P_2 AK8
SA_DQS_P_3 AG3
SA_DQS_P_4 H3
SA_DQS_P_5 E3
SA_DQS_P_6 C6
SA_DQS_P_7 C12
SA_DQ_0
AR15
SA_DQ_1
AT14
SA_DQ_2
AM14
SA_DQ_3
AN14
SA_DQ_4
AT15
SA_DQ_5
AR14
SA_DQ_6
AN15
SA_DQ_7
AM15
SA_DQ_8
AM9
SA_DQ_9
AN9
SA_DQ_10
AM8
SA_DQ_11
AN8
SA_DQ_12
AR9
SA_DQ_13
AT9
SA_DQ_14
AR8
SA_DQ_15
AT8
SA_DQ_16
AJ9
SA_DQ_17
AK9
SA_DQ_18
AJ6
SA_DQ_19
AK6
SA_DQ_20
AJ10
SA_DQ_21
AK10
SA_DQ_22
AJ7
SA_DQ_23
AK7
SA_DQ_24
AF4
SA_DQ_25
AF5
SA_DQ_26
AF1
SA_DQ_27
AF2
SA_DQ_28
AG4
SA_DQ_29
AG5
SA_DQ_30
AG1
SA_DQ_31
AG2
SA_DQ_32
J1
SA_DQ_33
J2
SA_DQ_34
J5
SA_DQ_35
H5
SA_DQ_36
H2
SA_DQ_37
H1
SA_DQ_38
J4
SA_DQ_39
H4
SA_DQ_40
F2
SA_DQ_41
F1
SA_DQ_42
D2
SA_DQ_43
D3
SA_DQ_44
D1
SA_DQ_45
F3
SA_DQ_46
C3
SA_DQ_47
B3
SA_DQ_48
B5
SA_DQ_49
E6
SA_DQ_50
A5
SA_DQ_51
D6
SA_DQ_52
D5
SA_DQ_53
E5
SA_DQ_54
B6
SA_DQ_55
A6
SA_DQ_56
E12
SA_DQ_57
D12
SA_DQ_58
B11
SA_DQ_59
A11
SA_DQ_60
E11
SA_DQ_61
D11
SA_DQ_62
B12
SA_DQ_63
A12
SM_VREF
AM3
SA_DIMM_VREFDQ
F16
SB_DIMM_VREFDQ
F13
G
D
S
QC11 BSS138_SOT23
@
G
D
S
QC11 BSS138_SOT23
@
2
1 3
T64 PAD@T64 PAD@
Haswell rPGA EDS
4 OF 9
JCPUD
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
4 OF 9
JCPUD
INTEL_HASWELL_HASWELL
RSVD AG8
SB_CKN0 Y4
SB_CK0 AA4
SB_CKE_0 AF10
SB_CKN1 Y3
SB_CK1 AA3
SB_CKE_1 AG10
SB_CKN2 Y2
SB_CK2 AA2
SB_CKE_2 AG9
SB_CKN3 Y1
SB_CK3 AA1
SB_CKE_3 AF9
SB_CS_N_0 P4
SB_CS_N_1 R2
SB_CS_N_2 P3
SB_CS_N_3 P1
SB_ODT_0 R4
SB_ODT_1 R3
SB_ODT_2 R1
SB_ODT_3 P2
SB_BS_0 R7
SB_BS_1 P8
SB_BS_2 AA9
RSVD R10
SB_RAS R6
SB_WE P6
SB_CAS P7
SB_MA_0 R8
SB_MA_1 Y5
SB_MA_2 Y10
SB_MA_3 AA5
SB_MA_4 Y7
SB_MA_5 AA6
SB_MA_6 Y6
SB_MA_7 AA7
SB_MA_8 Y8
SB_MA_9 AA10
SB_MA_10 R9
SB_MA_11 Y9
SB_MA_12 AF7
SB_MA_13 P9
SB_MA_14 AA8
SB_MA_15 AG7
SB_DQS_N_0 AP18
SB_DQS_N_1 AP11
SB_DQS_N_2 AP5
SB_DQS_N_3 AJ3
SB_DQS_N_4 L3
SB_DQS_N_5 H9
SB_DQS_N_6 C8
SB_DQS_N_7 C14
SB_DQS_P_0 AP17
SB_DQS_P_1 AP12
SB_DQS_P_2 AP6
SB_DQS_P_3 AK3
SB_DQS_P_4 M3
SB_DQS_P_5 H8
SB_DQS_P_6 C9
SB_DQS_P_7 C15
SB_DQ_0
AR18
SB_DQ_1
AT18
SB_DQ_2
AM17
SB_DQ_3
AM18
SB_DQ_4
AR17
SB_DQ_5
AT17
SB_DQ_6
AN17
SB_DQ_7
AN18
SB_DQ_8
AT12
SB_DQ_9
AR12
SB_DQ_10
AN12
SB_DQ_11
AM11
SB_DQ_12
AT11
SB_DQ_13
AR11
SB_DQ_14
AM12
SB_DQ_15
AN11
SB_DQ_16
AR5
SB_DQ_17
AR6
SB_DQ_18
AM5
SB_DQ_19
AM6
SB_DQ_20
AT5
SB_DQ_21
AT6
SB_DQ_22
AN5
SB_DQ_23
AN6
SB_DQ_24
AJ4
SB_DQ_25
AK4
SB_DQ_26
AJ1
SB_DQ_27
AJ2
SB_DQ_28
AM1
SB_DQ_29
AN1
SB_DQ_30
AK2
SB_DQ_31
AK1
SB_DQ_32
L2
SB_DQ_33
M2
SB_DQ_34
L4
SB_DQ_35
M4
SB_DQ_36
L1
SB_DQ_37
M1
SB_DQ_38
L5
SB_DQ_39
M5
SB_DQ_40
G7
SB_DQ_41
J8
SB_DQ_42
G8
SB_DQ_43
G9
SB_DQ_44
J7
SB_DQ_45
J9
SB_DQ_46
G10
SB_DQ_47
J10
SB_DQ_48
A8
SB_DQ_49
B8
SB_DQ_50
A9
SB_DQ_51
B9
SB_DQ_52
D8
SB_DQ_53
E8
SB_DQ_54
D9
SB_DQ_55
E9
SB_DQ_56
E15
SB_DQ_57
D15
SB_DQ_58
A15
SB_DQ_59
B15
SB_DQ_60
E14
SB_DQ_61
D14
SB_DQ_62
A14
SB_DQ_63
B14
RC143
1K_0402_1%
@RC143
1K_0402_1%
@
12
RC144
1K_0402_1%
@RC144
1K_0402_1%
@
12
G
D
S
QC9 BSS138_SOT23
@
G
D
S
QC9 BSS138_SOT23
@
2
1 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
COMPENSATION PU FOR eDP
HPD INVERSION FOR EDP
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Display Port Presence Strap
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
CFG[6:5]
PCIE Port Bifurcation Straps
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1: (Default) PEG Train immediately
following xxRESETB de assertion
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
CFG STRAPS for CPU
check CLK item
*
*
*
*
20120829 VA1
Add net for add HDMI MUX
CPU_EDP_AUX
CPU_EDP_AUX#
EDP_COMP
CPU_EDP_TX0-
CPU_EDP_TX0+
FDI_CTX_PRX_N0
EDP_HPD_IN#
FDI_CTX_PRX_N1
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
EDP_COMP
CFG7
CFG_RCOMP
H_CPU_RSVD
H_CPU_TESTLO
CFG4
CFG17
CFG19
CFG16
CFG18
CFG10
CFG11
CFG14
CFG15
CFG1
CFG2
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG12
CFG13
CFG6
CFG5
CFG_RCOMP
H_CPU_RSVD
H_CPU_TESTLO
CFG2
EDP_HPD_IN#
CPU_EDP_TX1+
CPU_EDP_TX1-
FDI_CTX_PRX_P0 <15>
FDI_CTX_PRX_N1 <15>
FDI_CTX_PRX_P1 <15>
FDI_CTX_PRX_N0 <15>
CPU_EDP_HPD<38>
CPU_HDMI_TX1+<37>
CPU_HDMI_TX1-<37>
CPU_HDMI_CLK+<37>
CPU_HDMI_TX0-<37>
CPU_HDMI_TX2+<37>
CPU_HDMI_TX2-<37>
CPU_HDMI_CLK-<37>
CPU_HDMI_TX0+<37>
CPU_EDP_TX0- <38>
CPU_EDP_TX0+ <38>
CPU_EDP_TX1+ <38>
CPU_EDP_TX1- <38>
CPU_EDP_AUX# <38>
CPU_EDP_AUX <38>
+VCCIOA_OUT
+VCCIO_OUT
+VCC_CORE
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (4/7) RSVD,CFG
Custom
8 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (4/7) RSVD,CFG
Custom
8 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (4/7) RSVD,CFG
Custom
8 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
T69PAD @T69PAD @
T117PAD@T117PAD@
T89PAD @T89PAD @
T130PAD@T130PAD@
T135PAD@T135PAD@
T134PAD@T134PAD@
T100PAD @T100PAD @
T80 PAD@T80 PAD@
RC45 49.9_0402_1%RC45 49.9_0402_1%
12
T93PAD @T93PAD @
T71 PAD@T71 PAD@
Haswell rPGA EDS
9 OF 9
JCPUI
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
9 OF 9
JCPUI
INTEL_HASWELL_HASWELL
RSVD_TP
AT1
RSVD_TP
AT2
RSVD
AD10
RSVD_TP
A34
RSVD_TP
A35
RSVD
W29
RSVD
W28
RSVD
G26
RSVD
W33
RSVD
AL30
RSVD
AL29
VCC
F25
RSVD_TP
C35
RSVD_TP
B35
RSVD_TP
AL25
RSVD
W30
RSVD
W31
TESTLO
W34
CFG_0
AT20
CFG_1
AR20
CFG_2
AP20
CFG_3
AP22
CFG_4
AT22
CFG_5
AN22
CFG_6
AT25
CFG_7
AN23
CFG_8
AR24
CFG_9
AT23
CFG_10
AN20
CFG_11
AP24
CFG_12
AP26
CFG_13
AN25
CFG_14
AN26
CFG_15
AP25
RSVD_TP C23
RSVD_TP B23
RSVD_TP D24
RSVD_TP D23
CFG_RCOMP AT31
CFG_16 AR21
CFG_18 AR23
CFG_17 AP21
CFG_19 AP23
RSVD AR33
RSVD G6
RSVD AM27
RSVD AM26
RSVD F5
RSVD AM2
RSVD K6
RSVD_TP AR1
RSVD E18
RSVD A2
RSVD_TP E21
RSVD_TP E20
RSVD AP27
RSVD AR26
RSVD AL31
RSVD AL32
NC B1
RSVD U10
RSVD P10
T83 PAD@T83 PAD@
T88PAD @T88PAD @
T104PAD @T104PAD @
T101PAD @T101PAD @
T98PAD @T98PAD @
T79 PAD@T79 PAD@
T77 PAD@T77 PAD@
T81 PAD@T81 PAD@
T132PAD@T132PAD@
T156PAD @T156PAD @
RC59 49.9_0402_1%RC59 49.9_0402_1%
12
T137PAD@T137PAD@
T72 PAD@T72 PAD@
T85 PAD@T85 PAD@
T164PAD @T164PAD @
T99PAD @T99PAD @
T82 PAD@T82 PAD@
RC86
1K_0402_1%
@RC86
1K_0402_1%
@
12
T165PAD @T165PAD @
Haswell rPGA EDS
eDP
DDI
8 OF 9
JCPUH
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
eDP
DDI
8 OF 9
JCPUH
INTEL_HASWELL_HASWELL
DDIB_TXBN_0
T28
DDIB_TXBP_0
U28
DDIB_TXBN_1
T30
DDIB_TXBP_1
U30
DDIB_TXBN_2
U29
DDIB_TXBP_2
V29
DDIB_TXBN_3
U31
DDIB_TXBP_3
V31
DDIC_TXCN_0
T34
DDIC_TXCP_0
U34
DDIC_TXCN_1
U35
DDIC_TXCP_1
V35
DDIC_TXCN_2
U32
DDIC_TXCP_2
T32
DDIC_TXCN_3
U33
DDIC_TXCP_3
V33
DDID_TXDN_0
P29
DDID_TXDP_0
R29
DDID_TXDN_1
N28
DDID_TXDP_1
P28
DDID_TXDN_2
P31
DDID_TXDP_2
R31
DDID_TXDN_3
N30
DDID_TXDP_3
P30
EDP_AUXN M27
EDP_AUXP N27
EDP_HPD P27
EDP_TXN_0 P35
EDP_TXN_1 N34
EDP_TXP_0 R35
EDP_TXP_1 P34
EDP_RCOMP E24
RSVD R27
FDI_TXN_0 P33
FDI_TXP_0 R33
FDI_TXN_1 N32
FDI_TXP_1 P32
T94 PAD@T94 PAD@
T91PAD @T91PAD @
RC83
1K_0402_1%
@RC83
1K_0402_1%
@
12
RC85
1K_0402_1%
RC85
1K_0402_1%
12
T70 PAD@T70 PAD@
T133PAD@T133PAD@
RC76
1K_0402_1%
@RC76
1K_0402_1%
@
12
T95PAD @T95PAD @
T129PAD@T129PAD@
T166PAD @T166PAD @
T136PAD@T136PAD@
RC124.9_0402_1% RC124.9_0402_1%
12
T102PAD @T102PAD @
RC77
1K_0402_1%
RC77
1K_0402_1%
12
T116PAD@T116PAD@
T96PAD @T96PAD @
T131PAD@T131PAD@
T97PAD @T97PAD @
T73 PAD@T73 PAD@
T78PAD @T78PAD @
T126PAD@T126PAD@
T92PAD @T92PAD @
T87PAD @T87PAD @
T143PAD@T143PAD@
T138PAD@T138PAD@
T173PAD@T173PAD@
T76 PAD@T76 PAD@
RC75
100K_0402_5%
RC75
100K_0402_5%
12
T142PAD@T142PAD@
T86PAD @T86PAD @
T84 PAD@T84 PAD@
RC65
10K_0402_5%
RC65
10K_0402_5%
1 2
G
D
S
QC6
BSS138_SOT23
G
D
S
QC6
BSS138_SOT23
2
13
RC58 49.9_0402_1%RC58 49.9_0402_1%
12
T90PAD @T90PAD @
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDDQ DECOUPLING
VCC_SENSE
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
need connect to power
Power
placement
need connect to power
CPU_PWR_DEBUG
VSSSENSE VSSSENSE_R
VCCSENSE VCCSENSE_R
VCCSENSE_R
VR_SVID_DAT
VR_SVID_CLK
VR_SVID_ALRT#_R
CPU_PWR_DEBUG
VCCSENSE<64>
VSSSENSE<64> VSSSENSE_R <10>
VR_SVID_CLK<64>
VR_SVID_ALRT#<64>
CPU_PWR_DEBUG <6>
VR_SVID_DAT<64>
+1.35V_CPU_VDDQ
+VCC_CORE
+VCC_CORE
+VCCIOA_OUT
+VCC_CORE
+1.35V
+1.05VS
+VCCIO_OUT
+VCC_CORE
+1.35V_CPU_VDDQ
+1.05VS
+1.05VS +VCCIO_OUT
+VCCIO_OUT
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (5/7) PWR, BYPASS
Custom
9 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (5/7) PWR, BYPASS
Custom
9 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (5/7) PWR, BYPASS
Custom
9 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CC168
10U_0603_6.3V6M
CC168
10U_0603_6.3V6M
1
2
T113 PAD@T113 PAD@
RC68
R_short 0_0402_5%
RC68
R_short 0_0402_5%
12
Haswell rPGA EDS
5 OF 9
JCPUE
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
5 OF 9
JCPUE
INTEL_HASWELL_HASWELL
RSVD
K27
RSVD
L27
RSVD
T27
RSVD
V27
VDDQ
AB11
VDDQ
AB2
VDDQ
AB5
VDDQ
AB8
VDDQ
AE11
VDDQ
AE2
VDDQ
AE5
VDDQ
AE8
VDDQ
AH11
VDDQ
K11
VDDQ
N11
VDDQ
N8
VDDQ
T11
VDDQ
T2
VDDQ
T5
VDDQ
T8
VDDQ
W11
VDDQ
W2
VDDQ
W5
VDDQ
W8
RSVD
N26
VCC
K26
RSVD
AL27
RSVD
AK27
VCC_SENSE
AL35
RSVD
E17
VCCIO_OUT
AN35
VCCIO2PCH
A23
VCCIOA_OUT
F22
RSVD
W32
RSVD
AL16
VSS
J27
RSVD
AL13
VIDALERT
AM28
VIDSCLK
AM29
VIDSOUT
AL28
VSS
AP35
PWR_DEBUG
H27
RSVD
AP34
RSVD
AT35
RSVD
AR35
RSVD
AR32
RSVD
AL26
RSVD
AT34
RSVD
AL22
RSVD
AT33
RSVD
AM21
RSVD
AM25
RSVD
AM22
RSVD
AM20
RSVD
AM24
RSVD
AL19
RSVD
AM23
RSVD
AT32
VCC AA26
VCC AA28
VCC AA34
VCC AA30
VCC AA32
VCC AB26
VCC AB29
VCC AB25
VCC AB27
VCC AB28
VCC AB30
VCC AB31
VCC AB33
VCC AB34
VCC AB32
VCC AC26
VCC AB35
VCC AC28
VCC AD25
VCC AC30
VCC AD28
VCC AC32
VCC AD31
VCC AC34
VCC AD34
VCC AD26
VCC AD27
VCC AD29
VCC AD30
VCC AD32
VCC AD33
VCC AD35
VCC AE26
VCC AE32
VCC AE28
VCC AE30
VCC AG28
VCC AG34
VCC AE34
VCC AF25
VCC AF26
VCC AF27
VCC AF28
VCC AF29
VCC AF30
VCC AF31
VCC AF32
VCC AF33
VCC AF34
VCC AF35
VCC AG26
VCC AH26
VCC AH29
VCC AG30
VCC AG32
VCC AH32
VCC AH35
VCC AH25
VCC AH27
VCC AH28
VCC AH30
VCC AH31
VCC AH33
VCC AH34
VCC AJ25
VCC AJ26
VCC AJ27
VCC AJ28
VCC AJ29
VCC AJ30
VCC AJ31
VCC AJ32
VCC AJ33
VCC AJ34
VCC AJ35
VCC G25
VCC H25
VCC J25
VCC K25
VCC L25
VCC M25
VCC N25
VCC P25
VCC R25
VCC T25
VCC U25
VCC U26
VCC V25
VCC V26
VCC W26
VCC W27
VCC
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
RC66
100_0402_1%
RC66
100_0402_1%
12
RC63
130_0402_1%
@
RC63
130_0402_1%
@
12
T157 PAD@T157 PAD@
CC37
22U_0805_6.3V6M
CC37
22U_0805_6.3V6M
1
2
CC33
22U_0805_6.3V6M
CC33
22U_0805_6.3V6M
1
2
CC152 0.1U_0402_25V6KCC152 0.1U_0402_25V6K
12
CC169
10U_0603_6.3V6M
CC169
10U_0603_6.3V6M
1
2
RC4
0_0603_5% @
RC4
0_0603_5% @
12
T162 PAD@T162 PAD@
CC41
22U_0805_6.3V6M
@
CC41
22U_0805_6.3V6M
@
1
2
T115 PAD@T115 PAD@
CC43
22U_0805_6.3V6M
CC43
22U_0805_6.3V6M
1
2
CC151 0.1U_0402_25V6KCC151 0.1U_0402_25V6K
12
T154 PAD@T154 PAD@
T160 PAD@T160 PAD@
CC161
10U_0603_6.3V6M
CC161
10U_0603_6.3V6M
1
2
CC164
10U_0603_6.3V6M
CC164
10U_0603_6.3V6M
1
2
RC69
150_0402_1%
@
RC69
150_0402_1%
@
12
RC70
100_0402_1%
RC70
100_0402_1%
12
T106 PAD@T106 PAD@
RC61 43_0402_5%RC61 43_0402_5%
1 2
CC166
10U_0603_6.3V6M
CC166
10U_0603_6.3V6M
1
2
T153 PAD@T153 PAD@
CC35
22U_0805_6.3V6M
@
CC35
22U_0805_6.3V6M
@
1
2
+
CC167
330U_D2_2VM_R6M
@
+
CC167
330U_D2_2VM_R6M
@
1
2
RC71
10K_0402_5%
@
RC71
10K_0402_5%
@
12
CC165
10U_0603_6.3V6M
CC165
10U_0603_6.3V6M
1
2
T163 PAD@T163 PAD@
T152 PAD@T152 PAD@
CC42
22U_0805_6.3V6M
CC42
22U_0805_6.3V6M
1
2
CC170
10U_0603_6.3V6M
CC170
10U_0603_6.3V6M
1
2
RC67
R_short 0_0402_5%
RC67
R_short 0_0402_5%
12
CC171
10U_0603_6.3V6M
CC171
10U_0603_6.3V6M
1
2
T112 PAD@T112 PAD@
CC162
10U_0603_6.3V6M
CC162
10U_0603_6.3V6M
1
2
CC36
22U_0805_6.3V6M
CC36
22U_0805_6.3V6M
1
2
T159 PAD@T159 PAD@
T151 PAD@T151 PAD@
CC39
22U_0805_6.3V6M
CC39
22U_0805_6.3V6M
1
2
+
CC172
330U_D2_2VM_R6M
@
+
CC172
330U_D2_2VM_R6M
@
1
2
CC38
22U_0805_6.3V6M
CC38
22U_0805_6.3V6M
1
2
CC34
22U_0805_6.3V6M
CC34
22U_0805_6.3V6M
1
2
CC40
22U_0805_6.3V6M
CC40
22U_0805_6.3V6M
1
2
T158 PAD@T158 PAD@
CC163
10U_0603_6.3V6M
CC163
10U_0603_6.3V6M
1
2
T107 PAD@T107 PAD@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For Deep S3
R56 need to check on SDV
AO4304L
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV00
+1.35V_CPU_VDDQ
SUSP
RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3#
CPU1.5V_S3_GATE<46>
SUSP<40,55,61>
RUN_ON_CPU1.5VS3# <6>
VSSSENSE_R <9>
+3VALW
+1.35V
+VSB
+1.35V_CPU_VDDQ
+1.35V_CPU_VDDQ+1.35V
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (6/7) PWR
Custom
10 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (6/7) PWR
Custom
10 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU (6/7) PWR
Custom
10 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CC286 0.1U_0402_10V6KCC286 0.1U_0402_10V6K
1 2
CC95 0.1U_0402_10V6KCC95 0.1U_0402_10V6K
1 2
UC3
AO4304L_SO8
@
UC3
AO4304L_SO8
@
6
2
4
1
3
5
7
8
CC287 0.1U_0402_10V6KCC287 0.1U_0402_10V6K
1 2
RC237 0_0402_5%RC237 0_0402_5%
1 2
J15
JUMP_43X79
@J15
JUMP_43X79
@
11
2
2
G
D
S
QC156
2N7002KW_SOT323-3
@
G
D
S
QC156
2N7002KW_SOT323-3
@
2
13
RC1487
470_0603_5%
@RC1487
470_0603_5%
@
12
T65PAD @T65PAD @
CC96 0.1U_0402_10V6KCC96 0.1U_0402_10V6K
1 2
RC238 0_0402_5%RC238 0_0402_5%
1 2
RC56
100K_0402_5%
@RC56
100K_0402_5%
@
12
RC1546
470K_0402_5%
@RC1546
470K_0402_5%
@
12
Haswell rPGA EDS
6 OF 9
JCPUF
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
6 OF 9
JCPUF
INTEL_HASWELL_HASWELL
VSS
A10
VSS
A13
VSS
A16
VSS
A19
VSS
A22
VSS
A25
VSS
A27
VSS
A29
VSS
A3
VSS
A31
VSS
A33
VSS
A4
VSS
A7
VSS
AA11
VSS
AA25
VSS
AA27
VSS
AA31
VSS
AA29
VSS
AB1
VSS
AB10
VSS
AA33
VSS
AA35
VSS
AB3
VSS
AC25
VSS
AC27
VSS
AB4
VSS
AB6
VSS
AB7
VSS
AB9
VSS
AC11
VSS
AD11
VSS
AC29
VSS
AC31
VSS
AC33
VSS
AC35
VSS
AD7
VSS
AE1
VSS
AE10
VSS
AE25
VSS
AE29
VSS
AE3
VSS
AE27
VSS
AE35
VSS
AE4
VSS
AE6
VSS
AE7
VSS
AE9
VSS
AF11
VSS
AF6
VSS
AF8
VSS
AG11
VSS
AG25
VSS
AE31
VSS
AG31
VSS
AE33
VSS
AG6
VSS
AH1
VSS
AH10
VSS
AH2
VSS
AG27
VSS
AG29
VSS
AH3
VSS
AG33
VSS
AG35
VSS
AH4
VSS
AH5
VSS
AH6
VSS
AH7
VSS
AH8
VSS
AH9
VSS
AJ11
VSS
AJ5
VSS
AK11
VSS
AK25
VSS
AK26
VSS
AK28
VSS
AK29
VSS
AK30
VSS
AK32
VSS
E19
VSS AK34
VSS AK5
VSS AL1
VSS AL10
VSS AL11
VSS AL12
VSS AL14
VSS AL15
VSS AL17
VSS AL18
VSS AL2
VSS AL20
VSS AL21
VSS AL23
VSS E22
VSS AL3
VSS AL4
VSS AL5
VSS AL6
VSS AL7
VSS AL8
VSS AL9
VSS AM10
VSS AM13
VSS AM16
VSS AM19
VSS E25
VSS AM32
VSS AM4
VSS AM7
VSS AN10
VSS AN13
VSS AN16
VSS AN19
VSS AN2
VSS AN21
VSS AN24
VSS AN27
VSS AN30
VSS AN34
VSS AN4
VSS AN7
VSS AP1
VSS AP10
VSS AP13
VSS AP16
VSS AP19
VSS AP4
VSS AP7
VSS W25
RSVD AR10
VSS AR13
VSS AR16
VSS AR19
VSS AR2
VSS AR22
VSS AR25
VSS AR28
VSS AR31
VSS AR34
VSS AR4
VSS AR7
VSS AT10
VSS AT13
VSS AT16
VSS AT19
VSS AT21
VSS AT24
VSS AT27
VSS AT3
VSS AT30
VSS AT4
VSS AT7
VSS B10
VSS B13
VSS B16
VSS B19
VSS B2
VSS B22
Haswell rPGA EDS
7 OF 9
JCPUG
INTEL_HASWELL_HASWELL
Haswell rPGA EDS
7 OF 9
JCPUG
INTEL_HASWELL_HASWELL
VSS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
RSVD
J28
VSS
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS K10
VSS K2
VSS K29
VSS K3
VSS K31
VSS K33
VSS K35
VSS K4
VSS K5
VSS K7
VSS K8
VSS K9
VSS L11
VSS L26
VSS L6
VSS M11
VSS M26
VSS M28
VSS M30
VSS M32
VSS M34
VSS M6
VSS N1
VSS N10
VSS N2
VSS N29
VSS N3
VSS N31
VSS N33
VSS N35
VSS N4
VSS N5
VSS N6
VSS N7
VSS N9
VSS P11
VSS P26
VSS P5
VSS R11
VSS R26
VSS R28
VSS R30
VSS R32
VSS R34
VSS R5
VSS T1
VSS T10
VSS T29
VSS T3
VSS T31
VSS T33
VSS T35
VSS T4
VSS T6
VSS T7
VSS T9
VSS U11
VSS U27
VSS V11
VSS V28
VSS V30
VSS V32
VSS V34
VSS W1
VSS W10
VSS W3
VSS W35
VSS W4
VSS W6
VSS W7
VSS W9
VSS Y11
RSVD H11
RSVD AL24
RSVD F19
RSVD T26
VSS_SENSE AK35
RSVD AK33
RC1349
470K_0402_5%
@RC1349
470K_0402_5%
@
1 2
G
D
S
QC5
2N7002KW_SOT323-3
@
G
D
S
QC5
2N7002KW_SOT323-3
@
2
13
RC1537
100K_0402_5%
@RC1537
100K_0402_5%
@
12
G
D
S
QC4
2N7002KW_SOT323-3
@
G
D
S
QC4
2N7002KW_SOT323-3
@
2
13
RC1538
0_0402_5%
@
RC1538
0_0402_5%
@
1 2
CC97
0.01U 50V K X7R 0603
@
CC97
0.01U 50V K X7R 0603
@1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
DDR_A_DM[0:7] connect to GND
Layout Note:
Place near DIMM (10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
3A@1.5V For RF request
DDR3 SO-DIMM A
20120727 VA
SWAP DQ for layout
20120727 VA
SWAP DQ for layout
20120727 VA
SWAP DQ for layout
20120727 VA
SWAP DQ for layout
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
SMB_CLK_S3
SMB_DATA_S3
+VREF_DQ_DIMMA
+VREF_CA
DDRA_MA15
DDRA_CKE0
DDRA_DQ59
DDRA_MA3
DDRA_CS1#
DDRA_BS1#
DDRA_DQS0
DDRA_WE#
DDRA_MA7
DDRA_MA0
DDRA_DQS7
DDRA_DQS#5
DDRA_DQS2
DDRA_RAS#
DDRA_DQ33
DDRA_DQ58
DDRA_MA8
DDRA_CS0#
DDRA_MA6
DDR3_DRAMRST#
DDRA_MA10
DDRA_DQS#7
DDRA_DQS#6
DDRA_DQ40
DDRA_MA9
DDRA_DQS#4
DDRA_DQS5
DDRA_DQ54
DDRA_BS2#
DDRA_MA1
DDRA_BS0#
DDRA_CAS# DDRA_ODT0
DDRA_MA5
DDRA_DQS#1
DDRA_MA14
DDRA_DQ55
DDRA_MA4
DDRA_DQ62
DDRA_ODT1
DDRA_CLK1
DDRA_CLK1#
DDRA_DQS#2
DDRA_CLK0
DDRA_CLK0#
DDRA_DQ32
DDRA_DQS1
DDRA_MA13
DDRA_MA11
DDRA_MA2
DDRA_DQ41
DDRA_DQ63
DDRA_DQS6
DDRA_MA12
DDRA_DQS#0
DDRA_DQS4
DDRA_DQ42
DDRA_CKE1
DDRA_DQ36
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ37 DDRA_DQ35
DDRA_DQ44
DDRA_DQ45
DDRA_DQ47
DDRA_DQ2DDRA_DQ1
DDRA_DQ46
DDRA_DQ43
DDRA_DQ49
DDRA_DQ53
DDRA_DQ52
DDRA_DQ48
DDRA_DQ51
DDRA_DQ50
DDRA_DQ60
DDRA_DQ56
DDRA_DQ61 DDRA_DQ57
DDRA_DQ6
DDRA_DQ3DDRA_DQ5
DDRA_DQ7
DDRA_DQ8
DDRA_DQ13 DDRA_DQ15
DDRA_DQ12
DDRA_DQ9
DDRA_DQ14
DDRA_DQ10
DDRA_DQ16
DDRA_DQ11
DDRA_DQ17
DDRA_DQ4
DDRA_DQ0
DDRA_DQ31
DDRA_DQ28
DDRA_DQ30
DDRA_DQS3
DDRA_DQ29
DDRA_DQ23
DDRA_DQS#3
DDRA_DQ22
DDRA_DQ19
DDRA_DQ24
DDRA_DQ18
DDRA_DQ25
DDRA_DQ20
DDRA_DQ21
DDRA_DQ27
DDRA_DQ26
+VREF_CA
DDRA_DQ[0..63] <7>
DDRA_DQS[0..7] <7>
DDRA_DQS#[0..7] <7>
DDRA_MA[0..15] <7>
DDRA_CKE0<7>
DDRA_BS2#<7>
DDRA_CLK0<7>
DDRA_CLK0#<7>
DDRA_BS0#<7>
DDRA_WE#<7>
DDRA_CAS#<7>
DDRA_CS1#<7>
DDRA_CKE1 <7>
DDRA_BS1# <7>
DDRA_RAS# <7>
DDRA_CS0# <7>
DDRA_ODT0 <7>
DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDRA_ODT1 <7>
DDR3_DRAMRST# <12,6>
SMB_CLK_S3 <12,17,40,47>
SMB_DATA_S3 <12,17,40,47>
+VREF_CA <12>
+0.675VS
+1.35V
+1.35V
+0.675VS
+3VS
+1.35V+1.35V
+VREF_CA_R+1.35V
+VREF_DQ_DIMMA_R
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM A
Custom
11 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM A
Custom
11 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM A
Custom
11 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CD180
0.1U_0402_10V6K
CD180
0.1U_0402_10V6K
1
2
RD81
1K_0402_1%
RD81
1K_0402_1%
12
CD179 0.1U_0402_10V6KCD179 0.1U_0402_10V6K
1
2
CD151
10U_0603_6.3V6M
CD151
10U_0603_6.3V6M
1
2
CD141
2.2U_0603_6.3V6K
CD141
2.2U_0603_6.3V6K
1
2
CD162
0.1U_0402_10V6K
CD162
0.1U_0402_10V6K
1
2
RD89
0_0402_5%
RD89
0_0402_5%
12
CD51
0.047U_0402_16V4Z
@
CD51
0.047U_0402_16V4Z
@
1
2
CD290
2.2U_0603_6.3V6K
CD290
2.2U_0603_6.3V6K
1
2
CD160
1U_0402_6.3V6K
CD160
1U_0402_6.3V6K
1
2
RD90
24.9_0402_1%
RD90
24.9_0402_1%
12
CD140
0.1U_0402_10V6K
CD140
0.1U_0402_10V6K
1
2
CD158
1U_0402_6.3V6K
CD158
1U_0402_6.3V6K
1
2
CD159
1U_0402_6.3V6K
CD159
1U_0402_6.3V6K
1
2
CD147
0.1U_0402_10V6K
CD147
0.1U_0402_10V6K
1
2
CD146
10U_0603_6.3V6M
CD146
10U_0603_6.3V6M
1
2
RD82
10K_0402_5%
RD82
10K_0402_5%
1 2
RD79
1K_0402_1%
RD79
1K_0402_1%
12
+
CD148
220U_6.3V_M
+
CD148
220U_6.3V_M
1
2
CD153
10U_0603_6.3V6M
CD153
10U_0603_6.3V6M
1
2
CD143
10U_0603_6.3V6M
CD143
10U_0603_6.3V6M
1
2
RD78
1K_0402_1%
RD78
1K_0402_1%
12
CD149
0.1U_0402_10V6K
CD149
0.1U_0402_10V6K
1
2
CD53
0.047U_0402_16V4Z
@
CD53
0.047U_0402_16V4Z
@
1
2
CD154
0.1U_0402_10V6K
CD154
0.1U_0402_10V6K
1
2
CD152
10U_0603_6.3V6M
CD152
10U_0603_6.3V6M
1
2
CD155
0.1U_0402_10V6K
CD155
0.1U_0402_10V6K
1
2
CD142
10U_0603_6.3V6M
CD142
10U_0603_6.3V6M
1
2
JDDRL1
LCN_DAN06-K4806-0102
ME@
JDDRL1
LCN_DAN06-K4806-0102
ME@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD52
0.047U_0402_16V4Z
@
CD52
0.047U_0402_16V4Z
@
1
2
CD150
2.2U_0603_6.3V6K
CD150
2.2U_0603_6.3V6K
1
2
CD144
10U_0603_6.3V6M
CD144
10U_0603_6.3V6M
1
2
RD91
0_0402_5%
RD91
0_0402_5%
1 2
CD288
1U_0402_6.3V6K
CD288
1U_0402_6.3V6K
1
2
CD145
10U_0603_6.3V6M
CD145
10U_0603_6.3V6M
1
2
CD156
0.1U_0402_10V6K
CD156
0.1U_0402_10V6K
1
2
RD80
1K_0402_1%
RD80
1K_0402_1%
12
RD88
24.9_0402_1%
RD88
24.9_0402_1%
12
RD83
10K_0402_5%
RD83
10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
Layout Note:
Place near DIMM
DDR_B_DM[0:7] connect to GND
For RF request
DDR3 SO-DIMM B
3A@1.5V
20120727 VA
SWAP DQ for layout
20120727 VA
SWAP DQ for layout
20120727 VA
SWAP DQ for layout
+VREF_DQ_DIMMB
+VREF_CA
DDRB_MA7
DDRB_BS1#
DDRB_MA15
DDRB_CS0#
DDRB_RAS#
DDRB_DQS#5
DDRB_DQS7
DDRB_MA0
DDRB_ODT0
DDRB_DQS5
DDRB_DQS#7
DDRB_MA6
DDRB_ODT1
DDRB_MA4
DDRB_MA14
SMB_CLK_S3
DDRB_MA2
DDRB_MA11
DDRB_DQ38
DDRB_CLK1#
DDRB_CLK1
DDRB_CKE0
DDRB_DQS4
DDRB_MA12
DDRB_DQS6
SMB_DATA_S3
DDRB_WE#
DDRB_CS1#
DDRB_MA3
DDRB_BS2#
DDRB_DQS#4
DDRB_MA9
DDRB_DQS#6
DDRB_MA10
DDRB_MA8
DDRB_MA5
DDRB_CAS#
DDRB_BS0#
DDRB_MA1
DDRB_MA13
DDRB_CLK0#
DDRB_CLK0
DDRB_DQS#0
DDRB_DQS0
DDR3_DRAMRST#
DDRB_DQS3
DDRB_CKE1
DDRB_DQS#3
DDRB_DQ26
DDRB_DQS2
DDRB_DQ27
DDRB_DQS#2
DDRB_DQS#1
DDRB_DQS1
DDRB_DQ33
DDRB_DQ32
DDRB_DQ39
DDRB_DQ36
DDRB_DQ37
DDRB_DQ34
DDRB_DQ35
DDRB_DQ44
DDRB_DQ41
DDRB_DQ40
DDRB_DQ45
DDRB_DQ46
DDRB_DQ52
DDRB_DQ47
DDRB_DQ53
DDRB_DQ42
DDRB_DQ49
DDRB_DQ43
DDRB_DQ48
DDRB_DQ51
DDRB_DQ57DDRB_DQ56
DDRB_DQ50
DDRB_DQ60
DDRB_DQ54
DDRB_DQ55
DDRB_DQ61
DDRB_DQ59
DDRB_DQ58
DDRB_DQ63
DDRB_DQ62
DDRB_DQ0
DDRB_DQ1DDRB_DQ5
DDRB_DQ4
DDRB_DQ2
DDRB_DQ3
DDRB_DQ9
DDRB_DQ8
DDRB_DQ6
DDRB_DQ12
DDRB_DQ13
DDRB_DQ7
DDRB_DQ16
DDRB_DQ10DDRB_DQ11
DDRB_DQ17
DDRB_DQ14
DDRB_DQ21
DDRB_DQ20
DDRB_DQ15
DDRB_DQ25
DDRB_DQ19
DDRB_DQ18
DDRB_DQ24
DDRB_DQ22
DDRB_DQ28
DDRB_DQ29
DDRB_DQ23
DDRB_DQ30
DDRB_DQ31
DDRB_DQ[0..63] <7>
DDRB_DQS[0..7] <7>
DDRB_DQS#[0..7] <7>
DDRB_MA[0..15] <7>
DDR3_DRAMRST# <11,6>
DDRB_CKE1 <7>
DDRB_CLK1 <7>
DDRB_BS1# <7>
DDRB_CLK1# <7>
DDRB_CS0# <7>
DDRB_RAS# <7>
DDRB_ODT0 <7>
SMB_DATA_S3 <11,17,40,47>
DDRB_ODT1 <7>
SMB_CLK_S3 <11,17,40,47>
DDRB_CKE0<7>
DDRB_BS2#<7>
DDRB_CLK0#<7>
DDRB_CLK0<7>
DDRB_BS0#<7>
DDRB_CAS#<7>
DDRB_WE#<7>
DDRB_CS1#<7>
+VREF_CA <11>
+0.675VS
+1.35V
+0.675VS
+1.35V +1.35V +1.35V
+3VS
+VREF_DQ_DIMMB_R
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM B
Custom
12 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM B
Custom
12 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DDRIII SO-DIMM B
Custom
12 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CD176
1U_0402_6.3V6K
CD176
1U_0402_6.3V6K
1
2
CD168
10U_0603_6.3V6M
CD168
10U_0603_6.3V6M
1
2
CD157
0.1U_0402_10V6K
CD157
0.1U_0402_10V6K
1
2
CD172
0.1U_0402_10V6K
CD172
0.1U_0402_10V6K
1
2
RD93
0_0402_5%
RD93
0_0402_5%
1 2
CD175
1U_0402_6.3V6K
CD175
1U_0402_6.3V6K
1
2
CD163
10U_0603_6.3V6M
CD163
10U_0603_6.3V6M
1
2
CD55
0.047U_0402_16V4Z
@
CD55
0.047U_0402_16V4Z
@
1
2
CD281
2.2U_0603_6.3V6K
CD281
2.2U_0603_6.3V6K
1
2
CD280
0.1U_0402_10V6K
CD280
0.1U_0402_10V6K
1
2
CD289
2.2U_0603_6.3V6K
CD289
2.2U_0603_6.3V6K
1
2
CD178
0.1U_0402_10V6K
CD178
0.1U_0402_10V6K
1
2
CD169
0.1U_0402_10V6K
CD169
0.1U_0402_10V6K
1
2
CD181
0.1U_0402_10V6K
CD181
0.1U_0402_10V6K
1
2
RD9710K_0402_5%RD9710K_0402_5%
1 2
CD164
10U_0603_6.3V6M
CD164
10U_0603_6.3V6M
1
2
CD166
10U_0603_6.3V6M
CD166
10U_0603_6.3V6M
1
2
CD170
0.1U_0402_10V6K
CD170
0.1U_0402_10V6K
1
2
CD165
10U_0603_6.3V6M
CD165
10U_0603_6.3V6M
1
2
RD84
1K_0402_1%
RD84
1K_0402_1%
12
RD95
10K_0402_5%
RD95
10K_0402_5%
1 2
CD171
0.1U_0402_10V6K
CD171
0.1U_0402_10V6K
1
2
CD54
0.047U_0402_16V4Z
@
CD54
0.047U_0402_16V4Z
@
1
2
CD56
0.047U_0402_16V4Z
@
CD56
0.047U_0402_16V4Z
@
1
2
JDDRL2
FOX_AS0A621-U4SG-7H
ME@
JDDRL2
FOX_AS0A621-U4SG-7H
ME@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD177
2.2U_0603_6.3V6K
CD177
2.2U_0603_6.3V6K
1
2
RD92
24.9_0402_1%
RD92
24.9_0402_1%
12
RD85
1K_0402_1%
RD85
1K_0402_1%
12
CD167
10U_0603_6.3V6M
CD167
10U_0603_6.3V6M
1
2
CD174
1U_0402_6.3V6K
CD174
1U_0402_6.3V6K
1
2
CD161
10U_0603_6.3V6M
CD161
10U_0603_6.3V6M
1
2
CD173
1U_0402_6.3V6K
CD173
1U_0402_6.3V6K
1
2
CD282
10U_0603_6.3V6M
CD282
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CMOS
HIntegrated VRM enable (Default)
L Integrated VRM disable
INTVRMEN
*
(INTVRMEN should always be pull high.)
HDA AUDIO
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high (Default)
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
*Low = Disabled (Default)
High = Enabled
[Flash Descriptor Security Overide]
ODD
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
SATA Impedance Compensation
W=20mils W=20mils
Place JUMPER under RAM door
<Intel update spec>
If RH1509 = stuff
RH1353 = @
QH10 = @
RH108 = @
SSD
HDD
PCH_TP25
+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TCK
PCH_RTCX1
PCH_RTCX2
PCH_RTCX2
PCH_RTCX1
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
PCH_INTVRMEN
SM_INTRUDER#
HDA_BIT_CLK
HDA_RST#
HDA_SDOUT
HDA_SYNC_R HDA_SYNC
HDA_BIT_CLK
HDA_SYNC
HDA_SYNC
HDA_SPKR
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
ME_FLASH HDA_SDOUT
PCH_GPIO13
PCH_GPIO33
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
SATA_COMP
SATA_COMP
HDD_LED#
PCH_GPIO21
SATA_DET#
SATA_IREF
CRT_SWITCH_1 PCH_GPIO33PCH_GPIO33
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
HDA_RST_AUDIO#<45>
HDA_SYNC_AUDIO<45>
HDA_SDOUT_AUDIO<45>
HDA_BITCLK_AUDIO<45>
HDA_SPKR<45>
HDA_SDIN0<45>
ME_FLASH<46>
SATA_PRX_DTX_P2 <44>
SATA_PRX_DTX_N2 <44>
SATA_PTX_C_DRX_N2 <44>
SATA_PTX_C_DRX_P2 <44>
HDD_LED# <51>
SATA_DET# <40>
CRT_SWITCH_1<37>
SATA_PRX_DTX_N0 <40>
SATA_PRX_DTX_P0 <40>
SATA_PTX_C_DRX_N0 <40>
SATA_PTX_C_DRX_P0 <40>
SATA_PRX_DTX_N1 <44>
SATA_PRX_DTX_P1 <44>
SATA_PTX_C_DRX_N1 <44>
SATA_PTX_C_DRX_P1 <44>
SATA_PTX_DRX_N0 <40>
SATA_PTX_DRX_P0 <40>
+3V_PCH
+RTCVCC
+RTCVCC
+5VS +3V_PCH
+3VS
+3V_PCH
+3V_PCH
+1.5VS
+3VS
+3VS
+3VS
+1.5VS
+RTCBATT +RTCVCC
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (1/9) SATA,HDA,SPI, LPC
Custom
13 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (1/9) SATA,HDA,SPI, LPC
Custom
13 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (1/9) SATA,HDA,SPI, LPC
Custom
13 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RH146 20K_0402_5%RH146 20K_0402_5%
1 2
RH46 210_0402_1%@RH46 210_0402_1%@
1 2
JME1
SHORT PADS
@JME1
SHORT PADS
@
12
T161PAD @T161PAD @
RH116
33_0402_5%
RH116
33_0402_5%
1 2
RH108 1K_0402_5%RH108 1K_0402_5%
12
RH288
0_0603_5%
@
RH288
0_0603_5%
@
12
RH148 20K_0402_5%RH148 20K_0402_5%
1 2
CH184 0.01U_0402_16V7K
@
CH184 0.01U_0402_16V7K
@
12
RH49
100_0402_1%
@
RH49
100_0402_1%
@
12
CH273 0.01U_0402_16V7KCH273 0.01U_0402_16V7K
12
RH110 0_0402_5%RH110 0_0402_5%
1 2
CH272 0.01U_0402_16V7KCH272 0.01U_0402_16V7K
12
RH317 10K_0402_5%@RH317 10K_0402_5%@12
T155PAD @T155PAD @
T108 PAD@T108 PAD@
RH105 1K_0402_5%@RH105 1K_0402_5%@
1 2
T109 PAD@T109 PAD@
RH119 10K_0402_5%RH119 10K_0402_5%
12
G
D
S
QH10
BSS138_NL_SOT23-3
G
D
S
QH10
BSS138_NL_SOT23-3
2
13
RH47
100_0402_1%
@
RH47
100_0402_1%
@
12
CH185 0.01U_0402_16V7K
@
CH185 0.01U_0402_16V7K
@
12
RH149 1M_0402_5%RH149 1M_0402_5%
1 2
JTAGRTC AZALIA
SATA
LPT_PCH_M_EDS
REV = 5
1 OF 11
UHA
LYNXPOINT_BGA695
JTAGRTC AZALIA
SATA
LPT_PCH_M_EDS
REV = 5
1 OF 11
UHA
LYNXPOINT_BGA695
TP20
AB6
TP25
F8
TP9 BA2
TP22
C26
RTCX1
B5
SATA_RXN_1 BC10
SATA_RXP_1 BE10
JTAG_TDI
AE2
JTAG_TDO
AD3
JTAG_TMS
AD1
JTAG_TCK
AB3
HDA_SDO
A24
HDA_SDI2
G22
HDA_SDI3
F22
HDA_SDI1
K22
HDA_SDI0
L22
RTCRST#
D9
INTRUDER#
A8
INTVRMEN
G10
SRTCRST#
B9
RTCX2
B4
SATA_IREF BD4
SATA0GP/GPIO21 AT1
SATA1GP/GPIO19 AU2
SATALED# AP3
SATA_RCOMP AY5
SATA_TXP5/PETP2 AR15
SATA_RXP5/PERP2 BE14
SATA_TXN5/PETN2 AP15
SATA_RXN5/PERN2 BC14
SATA_TXP4/PETP1 AW15
SATA_TXN4/PETN1 AV15
SATA_RXP4/PERP1 BB13
SATA_RXN4/PERN1 BD13
SATA_TXP_3 AT13
SATA_RXP_3 BE12
SATA_TXN_3 AR13
SATA_RXN_3 BC12
SATA_TXP_2 AW13
SATA_TXN_2 AY13
SATA_RXN_2 BB9
SATA_RXP_2 BD9
SATA_TXP_1 AW10
SATA_TXN_1 AV10
SATA_TXP_0 AY8
SATA_TXN_0 AW8
SATA_RXP_0 BE8
SATA_RXN_0 BC8
HDA_RST#
C24
SPKR
AL10
HDA_SYNC
A22
HDA_BCLK
B25
HDA_DOCK_RST#/GPIO13
C22
DOCKEN#/GPIO33
B17
TP8 BB2
RH316 10K_0402_5%RH316 10K_0402_5%
12
RH44 210_0402_1%@RH44 210_0402_1%@
1 2
RH1353
1M_0402_5%
RH1353
1M_0402_5%
12
CH188
18P_0402_50V8J
CH188
18P_0402_50V8J
1
2
RH407.5K_0402_1% RH407.5K_0402_1%
1 2
RH114
33_0402_5%
RH114
33_0402_5%
1 2
RH112
33_0402_5%
RH112
33_0402_5%
1 2
CH202
1U_0603_10V4Z
CH202
1U_0603_10V4Z
1
2
RH120 10K_0402_5%RH120 10K_0402_5%
12
RH1509 0_0402_5%
@
RH1509 0_0402_5%
@
1 2
RH109 R_short 0_0402_5%RH109 R_short 0_0402_5%
1 2
RH121
10K_0402_5%
@RH121
10K_0402_5%
@
1 2
Y3
32.768KHZ_12.5PF_CM31532768DZFT
Y3
32.768KHZ_12.5PF_CM31532768DZFT
1 2
CH189
18P_0402_50V8J
CH189
18P_0402_50V8J
1
2
CH229
1U_0603_10V4Z
CH229
1U_0603_10V4Z
1
2
RH1508 0_0402_5%
@
RH1508 0_0402_5%
@
1 2
RH99
1K_0402_5%
RH99
1K_0402_5%
12
RH106 1K_0402_5%@RH106 1K_0402_5%@12
RH107 1K_0402_1%@RH107 1K_0402_1%@
1 2
CH186 0.01U_0402_16V7KCH186 0.01U_0402_16V7K
12
RH118
33_0402_5%
RH118
33_0402_5%
1 2
RH410_0402_5% RH410_0402_5%
12
JCMOS2
SHORT PADS@
JCMOS2
SHORT PADS@
12
CH187 0.01U_0402_16V7KCH187 0.01U_0402_16V7K
12
RH59 51_0402_1%@RH59 51_0402_1%@12
CH179
1U_0603_10V4Z
CH179
1U_0603_10V4Z
1
2
RH45 210_0402_1%@RH45 210_0402_1%@
1 2
RH48
100_0402_1%
@
RH48
100_0402_1%
@
12
RH150 330K_0402_5%RH150 330K_0402_5%
1 2
RH145
10M_0402_5%
RH145
10M_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI
0 1 Reserved (NAND)
1 0
11 SPI
SATA_SLPD
(BBS_BIT0)
Boot BIOS Strap
BBS_BIT1
(GPIO51) Boot BIOS Location
*
00 LPC
*
Low = A16 swap
override/Top-Block
Swap Override enabled
**High=Default
PCI_GNT3#
A16 swap overide Strap/Top-Block
Swap Override jumper
PPT EDS DOC#474146
SWAP
For ESD
20120829 VA1
Add net for add CRT MUX
20120829 VA1
Add net for add HDMI MUX
CRT_IREF
PCH_ENBKL
PCH_ENVDD
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCH_GPIO51
PCH_WL_OFF#
PCH_GPIO2
ODD_DA#_R
PLT_RST#
PCH_GPIO51
PCH_WL_OFF#
DGPU_HOLD_RST#
PCH_WL_OFF#
DGPU_GC6_EN
PCH_GPIO51
PIRQH#
DGPU_GC6_EN
DGPU_HOLD_RST#
PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
PLT_RST#
PCH_CRT_R
PCH_CRT_B
PCH_CRT_G
PCH_CRT_HSYNC
PCH_CRT_VSYNC
PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
CRT_DET#CRT_DET#_R
PIRQH#
PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQB#
ODD_DA#_R
ODD_DA#_R
PCH_DGPU_HOLD_RST#
CRT_DET#_R
DGPU_PWR_EN DGPU_PWR_EN_R
DGPU_GC6_EN
NVDD_PWR_EN NVDD_PWR_EN_R
DDPB_DATA
DDPB_CLK
TMDS_B_HPD
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_EDP_PWM
PCI_PIRQC#
PCH_GPIO2
DGPU_PWR_EN
PCH_ENBKL<35>
PCH_ENVDD<35>
ODD_DA#_R <44>
PLT_RST# <23,32,40,41,46>
CRT_DET# <36>
DGPU_HOLD_RST#<23,54>
PCH_WL_OFF#<40>
DGPU_PWR_EN<23,54,55>
DGPU_GC6_EN<27,54>
NVDD_PWR_EN<54,63>
PCH_CRT_DDC_DAT<37>
PCH_CRT_DDC_CLK<37>
PCH_CRT_B<37>
PCH_CRT_G<37>
PCH_CRT_R<37>
PCH_CRT_HSYNC<37>
PCH_CRT_VSYNC<37>
DDPB_CLK <37>
DDPB_DATA <37>
TMDS_B_HPD <37>
PCH_EDP_PWM<35>
+3VS
+3VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (2/9) PCIE, SMBUS, CLK
Custom
14 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (2/9) PCIE, SMBUS, CLK
Custom
14 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (2/9) PCIE, SMBUS, CLK
Custom
14 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RH1519 0_0402_5%RH1519 0_0402_5%
1 2
RH301
100K_0402_5%
RH301
100K_0402_5%
12
RH310 8.2K_0402_5%
@
RH310 8.2K_0402_5%
@
1 2
RH302
649_0402_1%
RH302
649_0402_1%
12 RH325 10K_0402_5%RH325 10K_0402_5%
12
LPT_PCH_M_EV
DISPLAY
LVDSCRT
PCI
5 OF 11
REV = 5UHE
LYNXPOINT_BGA695
LPT_PCH_M_EV
DISPLAY
LVDSCRT
PCI
5 OF 11
REV = 5UHE
LYNXPOINT_BGA695
VGA_BLUE
T45
VGA_GREEN
U44
VGA_RED
V45
VGA_DDC_CLK
M43
DAC_IREF
U40
VGA_IRTN
U39
EDP_BKLTCTL
N36
EDP_BKLTEN
K36
EDP_VDDEN
G36
PIRQA#
H20
PIRQB#
L20
PIRQC#
K17
PIRQD#
M20
GPIO50
A12
GPIO52
B13
GPIO54
C12
GPIO51
C10
GPIO53
A10
GPIO55
AL6
DDPB_CTRLCLK R40
DDPB_CTRLDATA R39
DDPC_CTRLCLK R35
DDPC_CTRLDATA R36
DDPD_CTRLCLK N40
DDPD_CTRLDATA N38
DDPB_AUXN H45
DDPC_AUXN K43
DDPD_AUXN J42
DDPB_AUXP H43
DDPC_AUXP K45
DDPD_AUXP J44
DDPB_HPD K40
DDPC_HPD K38
DDPD_HPD H39
PIRQE#/GPIO2 G17
PIRQH#/GPIO5 M15
PME# AD10
PLTRST# Y11
PIRQG#/GPIO4 L15
PIRQF#/GPIO3 F17
VGA_VSYNC
N44
VGA_HSYNC
N42
VGA_DDC_DATA
M45
CC63
220P_0402_25V8J
@CC63
220P_0402_25V8J
@
1
2
RH339150_0402_1% RH339150_0402_1% 12
RH308 1K_0402_5%@RH308 1K_0402_5%@12
RH850 2.2K_0402_5%RH850 2.2K_0402_5%
1 2
RH320 8.2K_0402_5%RH320 8.2K_0402_5%
1 2
RH340150_0402_1% RH340150_0402_1% 12
RH312 8.2K_0402_5%RH312 8.2K_0402_5%
1 2
RH1522 0_0402_5%RH1522 0_0402_5%
1 2
RPH5
8.2K_0804_8P4R_5%
RPH5
8.2K_0804_8P4R_5%
18
27
36
45
RH341150_0402_1% RH341150_0402_1% 12
RH315 8.2K_0402_5%
@
RH315 8.2K_0402_5%
@
1 2
RH311 8.2K_0402_5%RH311 8.2K_0402_5%
1 2
RH851 2.2K_0402_5%RH851 2.2K_0402_5%
1 2
RH1526 0_0402_5%RH1526 0_0402_5%
1 2
RH314 8.2K_0402_5%@RH314 8.2K_0402_5%@
1 2
T114 PAD@T114 PAD@
RH323 8.2K_0402_5%RH323 8.2K_0402_5%
1 2
RH1525 0_0402_5%RH1525 0_0402_5%
1 2
RH318 8.2K_0402_5%@RH318 8.2K_0402_5%@
1 2
RH324 8.2K_0402_5%RH324 8.2K_0402_5%
1 2
RH307 1K_0402_5%@RH307 1K_0402_5%@
1 2
RH313 8.2K_0402_5%RH313 8.2K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Can be left NC when IAMT is not support on the platfrom
For Deep S3
Can be left NC if no use integrated LAN.
10/06 Test point request
For Deep S3
APWROK can be connect to
PWROK if iAMT disable
For Deep S3
*DSWODVREN - On Die DSW VR Enable
HEnable
LDisable
For Deep S3
note need connect to GPIO27
For Intel checklist V0.5
For Intel checklist V0.6
Add one to +3VALW next Rev.
PM_CLKRUN#
SUS_STAT#
SUSCLK
WAKE#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_SUS#_R
H_PM_SYNC
PCH_GPIO29
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N1
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N0
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_IREF
DMI_RCOMP
SUSACK#_R
SYS_RESET#
SYS_PWROK
VGATE
PCH_PWROK
APWROK
PWROK
PM_DRAM_PWRGD
SUSWARN#
SUSWARN#_R
PCH_RSMRST#_R
PCH_AC_PRESENT_R
PCH_AC_PRESENT_R
PCH_GPIO72
RI#
FDI_CTX_PRX_N1
FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_INT
FDI_CSYNC
FDI_IREF
FDI_RCOMP
DSWODVREN
DSWODVREN
PCH_DPWROK_R DPWROK_EC
PCIE_WAKE#WAKE#
PCH_RSMRST#_R
PCH_PWROK
PCH_DPWROK_R
PM_CLKRUN#
PM_SLP_S4# <46>
PM_SLP_S3# <46>
PM_SLP_SUS# <46,55>
H_PM_SYNC <6>
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P3<5>
DMI_CTX_PRX_P2<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P0<5>
SUSACK#<46>
SYS_PWROK <6>
VGATE<6,64>
PCH_PWROK<46>
PM_DRAM_PWRGD<6>
SUSWARN#<46>
EC_RSMRST#<46>
PBTN_OUT#<46>
AC_PRESENT<46>
DPWROK_EC <46>
PCIE_WAKE# <19,40,41>
FDI_CTX_PRX_N0 <8>
FDI_CTX_PRX_N1 <8>
FDI_CTX_PRX_P0 <8>
FDI_CTX_PRX_P1 <8>
FDI_CSYNC <5>
FDI_INT <5>
EDP_SEL<38>
SIO_PWRBTN#_R<6>
+3V_PCH
+1.5VS
+1.5VS
+3VS
+3VS
+3V_PCH
+3VALW
+3V_PCH
+1.5VS
+1.5VS
+RTCVCC
+3VS
+3VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) PCIE, SMBUS, CLK
Custom
15 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) PCIE, SMBUS, CLK
Custom
15 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) PCIE, SMBUS, CLK
Custom
15 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
T139 PAD@T139 PAD@
RH1489 R_short 0_0402_5%RH1489 R_short 0_0402_5%
1 2
CH1071
0.1U_0402_16V4Z
CH1071
0.1U_0402_16V4Z
1
2
T110PAD T110PAD
RH234 R_short 0_0402_5%RH234 R_short 0_0402_5%
1 2
RH202 10K_0402_5%RH202 10K_0402_5%
12
RH204 7.5K_0402_1%RH204 7.5K_0402_1%
1 2
T68PAD T68PAD
RH246 8.2K_0402_5%RH246 8.2K_0402_5%
1 2
RH294 R_short 0_0402_5%RH294 R_short 0_0402_5%
1 2
T145PAD @T145PAD @
T67PAD T67PAD
RH2067.5K_0402_1% RH2067.5K_0402_1%
12 RH1858.2K_0402_5% RH1858.2K_0402_5% 12
RH43 0_0402_5%RH43 0_0402_5%
12
RH1488 R_short 0_0402_5%RH1488 R_short 0_0402_5%
12
T148PAD @T148PAD @
T141PAD @T141PAD @
T140 PAD@T140 PAD@
RH1512 R_short 0_0402_5%RH1512 R_short 0_0402_5%
1 2
RH182
100K_0402_1%
@RH182
100K_0402_1%
@
12
RH184
100K_0402_1%
RH184
100K_0402_1%
12
UH7
MC74VHC1G08DFT2G SC70 5P
UH7
MC74VHC1G08DFT2G SC70 5P
B
2
A
1Y4
P5
G
3
T144PAD @T144PAD @
RH420_0402_5% RH420_0402_5%
12
RH187 10K_0402_5%RH187 10K_0402_5%
1 2
RH189
330K_0402_5%
RH189
330K_0402_5%
12
T66PAD T66PAD
RH222 200K_0402_5%RH222 200K_0402_5%
12
RH319 10K_0402_5%RH319 10K_0402_5%
12
RH292 R_short 0_0402_5%RH292 R_short 0_0402_5%
1 2
RH203
10K_0402_5%
RH203
10K_0402_5%
12
RH1456 R_short 0_0402_5%RH1456 R_short 0_0402_5%
12
RH291
330K_0402_5%@
RH291
330K_0402_5%@
12
T147PAD @T147PAD @
RH1510
R_short 0_0402_5%
RH1510
R_short 0_0402_5%
1 2
RH196
R_short 0_0402_5%
RH196
R_short 0_0402_5%
1 2
T111 PAD@T111 PAD@
T146PAD @T146PAD @
RH1511 R_short 0_0402_5%RH1511 R_short 0_0402_5%
1 2
RH188 10K_0402_5%RH188 10K_0402_5%
12
LPT_PCH_M_EDS
DMI
Management
FDI
System Power
REV = 5
4 OF 11
UHB
LYNXPOINT_BGA695
LPT_PCH_M_EDS
DMI
Management
FDI
System Power
REV = 5
4 OF 11
UHB
LYNXPOINT_BGA695
TP21
AB10
TP10 AW44
TP16 AV43
TP12
AW17
TP17 AU42
TP7
AV17
TP5 AY45
TP13 AU44
SUSWARN#/SUSPWRNACK/GPIO30
J4
DMI_IREF
BE16
DMI_RCOMP
AY17
FDI_RCOMP AR44
SLP_WLAN#/GPIO29
D2
DRAMPWROK
H3
APWROK
AB7
PWROK
F10
SYS_RESET#
AM1
DMI_RXP_2
AR17
DMI_RXP_3
AW20
DMI_TXN_0
BD21
DMI_TXN_1
BE20
SLP_LAN# G5
PMSYNCH AY3
SLP_SUS# F1
SLP_A# F3
SLP_S3# H1
SLP_S4# C6
SLP_S5#/GPIO63 Y7
SUSCLK/GPIO62 Y6
SUS_STAT#/GPIO61 U7
CLKRUN# AN7
WAKE# K3
DPWROK L13
FDI_IREF AT45
FDI_CSYNC AL39
FDI_RXP_1 AL36
FDI_RXP_0 AJ36
FDI_RXN_1 AL35
FDI_RXN_0 AJ35
ACPRESENT/GPIO31
E6
SYS_PWROK
AD7
SUSACK#
R6
DMI_TXP_2
BB17
DMI_TXP_0
BB21
DMI_RXP_1
AP20
DMI_RXN_2
AP17
DMI_TXP_3
BC18
DMI_TXP_1
BC20
DMI_TXN_3
BE18 DMI_TXN_2
BD17
DMI_RXP_0
AY22
DMI_RXN_3
AV20
PWRBTN#
K1
RI#
N4
BATLOW#/GPIO72
K7
RSMRST#
J2
FDI_INT AL40
DSWVRMEN C8
DMI_RXN_1
AR20 DMI_RXN_0
AW22
TP15 AV45
RH290 10K_0402_5%RH290 10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Change C196, C197 value of Cap
from 33pF to 10pF for TXC recommend
GPIO64, 65 that only for GC6
1. GPIO64 : S_DGPU_GC6_EN
2. GPIO65 : S_DGPU_PWROK
BIOS Request SKU ID
2nd VGA
Reserve for EMI please close to
PCH
LAN
WLAN
CLK_CPU_SSC_DPLL
CLK_CPU_SSC_DPLL#
CLK_CPU_DPLL
CLK_CPU_DPLL#
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_ICH_14M
CLK_PCI_LOOPBACK
PCI_LOOPBACKOUTCLK_PCI_LOOPBACK
XTAL25_OUT
XTAL25_IN
XTAL25_IN
XTAL25_OUT
CLK_BCLK_ITP
CLK_BCLK_ITP#
CLK_PCI_EC_R
CLK_PCI_DB_R
S_DGPU_RST_R
PCH_GPIO67
ICLK_IREF
PCH_CLK_BIASREF
PCH_GPIO18
CLKREQ_TV#_R
PCH_GPIO44
PCH_GPIO46
PCH_GPIO45
CLK_REQ_GPU#_R
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_2VGA#
CLK_PCIE_2VGA
CLK2_REQ_GPU#_R
CLK_CPU_DMI
CLK_CPU_DMI#
CLKREQ_TV#_R
CLK_PCI_LOOPBACK
PCH_GPIO73
WLAN_CLKREQ1#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#
PCH_GPIO18
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
CLKREQ_LAN#
WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
PCH_GPIO73
CLK_PCI_EC<46>
CLK_PCI_DB<40>
PCH_GPIO67 <19>
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23> CLK_REQ_GPU#_R <23>
CLK_PCIE_2VGA <32>
CLK_PCIE_2VGA# <32>
CLK2_REQ_GPU#_R <32>
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>
CLK_CPU_SSC_DPLL# <6>
CLK_CPU_SSC_DPLL <6>
CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>
S_DGPU_RST <32,54>
EDP_AUX_SEL <38>
S_DGPU_PWROK <32,54>
CLK_PCIE_WLAN<40>
CLK_PCIE_WLAN#<40>
WLAN_CLKREQ1#<40>
CLK_PCIE_LAN#<41>
CLK_PCIE_LAN<41>
CLKREQ_LAN#<41>
+3VS
+1.05V_+1.5V_RUN
+1.5VS
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) DMI, FDI, PM
Custom
16 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) DMI, FDI, PM
Custom
16 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (3/9) DMI, FDI, PM
Custom
16 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RH281 0_0402_5%RH281 0_0402_5%
12
RH162 10K_0402_5%RH162 10K_0402_5%
1 2
RH177 10K_0402_5%RH177 10K_0402_5%
12
RH1505 R_short 0_0402_5%
RH1505 R_short 0_0402_5%
1 2
CH199
22P_0402_50V8J
@CH199
22P_0402_50V8J
@
1 2
RH163 10K_0402_5%RH163 10K_0402_5%
1 2
RH152 10K_0402_5%RH152 10K_0402_5%
12
CH196
12P_0402_50V8F
CH196
12P_0402_50V8F
1
2
RH253 22_0402_5%RH253 22_0402_5%
1 2
CH197
12P_0402_50V8F
CH197
12P_0402_50V8F
1
2
RH1504 R_short 0_0402_5%
RH1504 R_short 0_0402_5%
1 2
RH165 10K_0402_5%RH165 10K_0402_5%
12
RPH1
10K_0804_8P4R_5%
RPH1
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
LPT_PCH_M_EDS
CLOCK SIGNAL
REV = 5
2 OF 11
UHC
LYNXPOINT_BGA695
LPT_PCH_M_EDS
CLOCK SIGNAL
REV = 5
2 OF 11
UHC
LYNXPOINT_BGA695
PCIECLKRQ4#/GPIO26
V3 CLKOUT_PCIE_P_4
AF45
CLKOUT_PCIE_P_5
AE42
PCIECLKRQ5#/GPIO44
AA2
CLKOUT_PCIE_N_6
AB40
CLKOUT_PCIE_P_6
AB39
PCIECLKRQ6#/GPIO45
AE4
CLKOUT_PCIE_N_7
AJ44
CLKOUT_PCIE_P_7
AJ42
CLKOUTFLEX2/GPIO66 F36
CLKIN_SATA BE6
CLKIN_GND AR24
CLKIN_DMI AY24
PCIECLKRQ1#/GPIO18
AF1
CLKOUT_DP AJ40
CLKOUT_DMI AF39
CLKOUT_PCIE_N_0
Y43
CLKOUT_PCIE_P_0
Y45
CLKOUT_PEG_B Y39
CLKOUT_PEG_A AB35
PCIECLKRQ0#/GPIO73
AB1
CLKOUT_PEG_A_P AB36
PEGA_CLKRQ#/GPIO47 AF6
CLKOUT_PEG_B_P Y38
PEGB_CLKRQ#/GPIO56 U4
CLKOUT_PCIE_P_1
AA42
CLKOUT_PCIE_N_2
AB43
CLKOUT_ITPXDP
AH43
XTAL25_IN AL44
XTAL25_OUT AM43
CLKOUTFLEX0/GPIO64 C40
CLKOUTFLEX1/GPIO65 F38
DIFFCLK_BIASREF AN44
ICLK_IREF AM45
CLKOUTFLEX3/GPIO67 F39
CLKIN_33MHZLOOPBACK D17
REFCLK14IN F45
CLKIN_SATA_P BC6
CLKIN_DOT96P G33
CLKIN_DOT96N H33
CLKIN_GND_P AT24
CLKIN_DMI_P AW24
CLKOUT_DP_P AJ39
CLKOUT_DMI_P AF40
CLKOUT_PCIE_N_1
AA44
PCIECLKRQ7#/GPIO46
Y3
CLKOUT_ITPXDP_P
AH45
CLKOUT_33MHZ1
E44
CLKOUT_33MHZ0
D44
CLKOUT_33MHZ2
B42
CLKOUT_33MHZ3
F41
CLKOUT_33MHZ4
A40
CLKOUT_PCIE_N_4
AF43
CLKOUT_PCIE_N_3
AD43
CLKOUT_PCIE_P_3
AD45
PCIECLKRQ3#/GPIO25
T3
CLKOUT_PCIE_N5
AE44
CLKOUT_DPNS_P AF36
CLKOUT_DPNS AF35
PCIECLKRQ2#/GPIO20/SMI#
AF3
CLKOUT_PCIE_P_2
AB45
TP19 AD39
TP18 AD38
RH168 10K_0402_5%RH168 10K_0402_5%
12
RH1514 22_0402_5%RH1514 22_0402_5%
12
RH183 10K_0402_5%RH183 10K_0402_5%
12
RH158 10K_0402_5%RH158 10K_0402_5%
12
RH172 10K_0402_5%RH172 10K_0402_5%
12
RH147 10K_0402_5%RH147 10K_0402_5%
12
RH1513 10K_0402_5%RH1513 10K_0402_5%
1 2
T149PAD @T149PAD @
RH174 22_0402_5%
@
RH174 22_0402_5%
@
12
RH164 10K_0402_5%RH164 10K_0402_5%
1 2
RH329 10K_0402_5%RH329 10K_0402_5%
12
RH176
33_0402_5%
@RH176
33_0402_5%
@
12
RH170 10K_0402_5%RH170 10K_0402_5%
1 2
RH280 0_0402_5%RH280 0_0402_5%
12
RH540_0402_5% RH540_0402_5%
1 2
RH166 10K_0402_5%RH166 10K_0402_5%
1 2
RH169
1M_0402_5%
RH169
1M_0402_5%
1 2
T150PAD @T150PAD @
Y2
25MHZ_10PF_7V25000014
Y2
25MHZ_10PF_7V25000014
GND
2
33
1
1
GND
4
RH2087.5K_0402_1% RH2087.5K_0402_1%
1 2
RH167 10K_0402_5%RH167 10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EC and Mini card debug port
VGA, EC, Thermal Sensor
DIMM1, DIMM2, Mini CARD, TP
2N7002KDWH
Vth= min 1V, max 2.5V
ESD 2KV
For EMI
32Mb Flash ROM16Mb Flash ROM
For EMI
LPC_AD2
LPC_AD0
LPC_AD3
LPC_AD1
LPC_FRAME#
SERIRQ
SPI_SB_CS0#_R
SPI_CS1#
SPI_CLK_PCH
SPI_CLK_PCH_0
SPI_CLK_PCH_1_R
SPI_SB_CS0#
SPI_CS1#_R
SPI_SO_L
SPI_SI_R
SPI_SI_R1 SPI_SI
SPI_SO_R
SPI_SO_L1
PCH_TD_IREF
PCH_GPIO11
DRAMRST_CNTRL_PCH
SML0CLK
SML0DATA
PCH_HOT#
PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA SMB_DATA_S3
SMB_CLK_S3
SML1CLK
SML1DATA
EC_SMB_CK2
EC_SMB_DA2
PCH_SMBCLK
PCH_SMBDATA
SML0CLK
SML0DATA
PCH_HOT#
SML1CLK
SML1DATA
SPI_WP#
SPI_HOLD#
SPI_WP#_1
SPI_HOLD#_1
SPI_SB_CS0#_R
SPI_SO_L
SPI_WP#
SPI_SI_R
SPI_CLK_PCH_0
SPI_HOLD#
SPI_WP#_1
SPI_CS1#_R
SPI_SO_L1 SPI_HOLD#_1
SPI_SI_R1
SPI_CLK_PCH_1_R
SPI_CLK_PCH_0 SPI_CLK_PCH_1_R
SPI_CS1#_R
SPI_SI_R1
SPI_SO_L1
SPI_CLK_PCH_1 SPI_CLK_PCH_1_R
LPC_AD0<40,46>
LPC_AD1<40,46>
LPC_AD2<40,46>
LPC_AD3<40,46>
LPC_FRAME#<40,46>
SERIRQ<46>
SMB_CLK_S3 <11,12,40,47>
SMB_DATA_S3 <11,12,40,47>
EC_SMB_CK2 <23,32,34,36,43,46>
EC_SMB_DA2 <23,32,34,36,43,46>
DRAMRST_CNTRL_PCH <6>
SPI_CS1#_R<46>
SPI_SI_R1<46>
SPI_SO_L1<46>
SPI_CLK_PCH_1<46>
+3VS
+3V_PCH
+3V_PCH
+3VS
+3V_PCH +3VS
+3VS
+3VS +3VS
+3VS +3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (4/9) LVDS, CRT,DP,HDMI
Custom
17 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (4/9) LVDS, CRT,DP,HDMI
Custom
17 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (4/9) LVDS, CRT,DP,HDMI
Custom
17 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RH142 2.2K_0402_5%
RH142 2.2K_0402_5%
1 2
RH333 R_short 0_0402_5%RH333 R_short 0_0402_5%
12
RH10410K_0402_5% RH10410K_0402_5%
1 2
RH337 10K_0402_5%
RH337 10K_0402_5%
1 2
T118PAD @T118PAD @
UH53
W25Q32FVSSIQ_SO8
UH53
W25Q32FVSSIQ_SO8
CLK 6
GND
4DIO 5
DO
2
/WP
3
VCC 8
/HOLD 7
/CS
1
RH322 8.2K_0402_1%RH322 8.2K_0402_1%
1 2
CH190
10P_0402_50V8J
@CH190
10P_0402_50V8J
@
1
2
RH138 2.2K_0402_5%
RH138 2.2K_0402_5%
12
RH133 33_0402_5%RH133 33_0402_5%
1 2
CH275
0.1U_0402_16V4Z
CH275
0.1U_0402_16V4Z
1
2
RH131 33_0402_5%RH131 33_0402_5%
12
RH335 10K_0402_5%RH335 10K_0402_5%
12
RH137 2.2K_0402_5%
RH137 2.2K_0402_5%
12
G
D
S
QH162A
2N7002KDWH_SOT363-6
G
D
S
QH162A
2N7002KDWH_SOT363-6
2
6 1
RH136 2.2K_0402_5%
RH136 2.2K_0402_5%
1 2
RH205 33_0402_5%RH205 33_0402_5%
1 2
CH191
0.1U_0402_16V4Z
CH191
0.1U_0402_16V4Z
1
2
RH130 R_short 0_0402_5%RH130 R_short 0_0402_5%
12
RH141 2.2K_0402_5%
RH141 2.2K_0402_5%
1 2
G
D
S
QH61B
2N7002KDWH_SOT363-6
G
D
S
QH61B
2N7002KDWH_SOT363-6
5
3 4
RH115 10_0402_5%
@
RH115 10_0402_5%
@
1 2
RH134 10K_0402_5%
RH134 10K_0402_5%
12
RH111 10_0402_5%
@
RH111 10_0402_5%
@
1 2
RH135 2.2K_0402_5%
RH135 2.2K_0402_5%
1 2
RH334 33_0402_5%RH334 33_0402_5%
12
RH257 3.3K_0402_5%RH257 3.3K_0402_5%
1 2
RH336 10K_0402_5%RH336 10K_0402_5%
1 2
RH140 10K_0402_5%
RH140 10K_0402_5%
12
T119PAD @T119PAD @
G
D
S
QH61A
2N7002KDWH_SOT363-6
G
D
S
QH61A
2N7002KDWH_SOT363-6
2
6 1
RH127 3.3K_0402_5%RH127 3.3K_0402_5%
1 2
RH332 33_0402_5%RH332 33_0402_5%
1 2
RH330 3.3K_0402_5%RH330 3.3K_0402_5%
1 2
T120PAD @T120PAD @
G
D
S
QH162B
2N7002KDWH_SOT363-6
G
D
S
QH162B
2N7002KDWH_SOT363-6
5
3 4
RH338 0_0402_5%
@
RH338 0_0402_5%
@
12
UH52
W25Q16DVSSIQ_SO8
UH52
W25Q16DVSSIQ_SO8
CS#
1
DO
2
WP#
3
GND
4
VCC 8
HOLD# 7
CLK 6
DI 5
RH129 3.3K_0402_5%RH129 3.3K_0402_5%
1 2
RH331 33_0402_5%RH331 33_0402_5%
1 2
T121PAD @T121PAD @
CH200
10P_0402_50V8J
@CH200
10P_0402_50V8J
@
1
2
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
SPILPC
3 OF 11 REV = 5
UHD
LYNXPOINT_BGA695
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
SPILPC
3 OF 11 REV = 5
UHD
LYNXPOINT_BGA695
SML1ALERT#/PCHHOT#/GPIO74 H6
SPI_IO3
AJ2
SPI_MISO
AH3
SPI_IO2
AJ4
SPI_MOSI
AH1
SPI_CS2#
AJ10
SPI_CS1#
AL7
SPI_CS0#
AJ7
SPI_CLK
AJ11
LDRQ1#/GPIO23
G20
SERIRQ
AL11
LDRQ0#
D21
LFRAME#
B21
LAD_3
C18
LAD_2
A18
LAD_1
C20
LAD_0
A20
TD_IREF AY43
CL_DATA AF10
CL_RST# AF7
CL_CLK AF11
SML1DATA/GPIO75 N11
SML1CLK/GPIO58 K6
SML0DATA R7
SML0CLK U8
SML0ALERT#/GPIO60 N8
SMBDATA U11
SMBCLK R10
SMBALERT#/GPIO11 N7
TP2 BC45
TP4 BE43
TP1 BA45
TP3 BE44
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LEFT USB
Within 500 mils
Camera
LEFT USB
RIGHT USB 1 (SUB/B)
Some PCH config not support USB port 6 & 7.
WLAN
Port1
Port2
Port5
Port6
USB3.0
LEFT USB
LEFT USB
Card reader
Card reader
Touch panel
Debug port, reserved test point
WLAN
LAN
USB30_RX_N2
USB30_TX_N2
USB30_RX_P2
USB30_TX_P2
USBRBIAS
USB_OC5#
USB_OC4#
USB_OC2#
USB_OC0#
USB_OC3#
USB_OC1#
USB_OC6#
USB_OC7#
USB_OC4#
USB_OC2#
USB_OC7#
USB_OC5#
USB_OC6#
USB_OC3#
USB_OC1#
USB_OC0#
PCH_PCIE_RCOMP
PCH_PCIE_IREF
USB20_N0
USB20_P0
USB20_N2
USB20_P2
USB20_P10
USB20_N10
USB20_P3
USB20_N3
USB20_N1
USB20_P1
USB20_P4
USB20_N4
USB20_N8
USB20_P8
PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N4
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P5
PCIE_PRX_DTX_N5
USB30_RX_N5
USB30_RX_P5
USB30_TX_N5
USB30_TX_P5
USB30_RX_P6
USB30_RX_N6
USB30_TX_N6
USB30_TX_P6
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
USB30_RX_N2 <49>
USB30_RX_P2 <49>
USB30_TX_N2 <49>
USB30_TX_P2 <49>
USB_OC1# <49>
USB20_N0 <35>
USB20_P0 <35>
USB20_N2 <49>
USB20_P2 <49>
USB20_N10 <40>
USB20_P10 <40>
USB20_P3 <49>
USB20_N3 <49>
USB20_P1 <50>
USB20_N1 <50>
USB20_P4 <48>
USB20_N4 <48>
USB20_P8 <50>
USB20_N8 <50>
USB_OC0# <50>
PCIE_PRX_DTX_N4<41>
PCIE_PTX_C_DRX_N4<41>
PCIE_PRX_DTX_P4<41>
PCIE_PTX_C_DRX_P4<41>
PCIE_PRX_DTX_N5<40>
PCIE_PRX_DTX_P5<40>
USB30_RX_N5<49>
USB30_RX_P5<49>
USB30_TX_P5<49>
USB30_TX_N5<49>
USB30_RX_P6<48>
USB30_RX_N6<48>
USB30_TX_P6<48>
USB30_TX_N6<48>
PCIE_PTX_C_DRX_N5<40>
PCIE_PTX_C_DRX_P5<40>
+3V_PCH
+1.5VS
+1.5VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (5/9) PCI, USB
Custom
18 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (5/9) PCI, USB
Custom
18 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (5/9) PCI, USB
Custom
18 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RPH4
10K_1206_8P4R_5%
RPH4
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
RPH3
10K_1206_8P4R_5%
RPH3
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
CH192 0.1U_0402_10V7KCH192 0.1U_0402_10V7K
1 2
T124 PAD@T124 PAD@
T125 PAD@T125 PAD@
LPT_PCH_M_EDS
USB
PCIe
9 OF 11 REV = 5
UHI
LYNXPOINT_BGA695
LPT_PCH_M_EDS
USB
PCIe
9 OF 11 REV = 5
UHI
LYNXPOINT_BGA695
USB3TP6 BE28
USB3TN6 BD27
USB3RP6 AP29
USB3RN6 AR29
USB3TP5 BC26
USB3TN5 BE26
USB3RP5 AV29
USB3RN5 AW29
PETP1/USB3TP3
BC32
PERP2/USB3RP4
AR31
PETP2/USB3TP4
BB33
USB3TP2 BC24
PETN2/USB3TN4
BD33
PERN2/USB3RN4
AT31
PETN1/USB3TN3
BE32
PERP1/USB3RP3
AY31 PERN1/USB3RN3
AW31
PERN_3
AW33
PERP_3
AY33
PETN_3
BE34
PETN_4
BE36
PERN_5
AW36
PERP_5
AV36
PETN_5
BD37
PERP_6
AW38
PETN_6
BC38
PERN_7
AT40
USB2N13 F24
USB2P13 G24
USB2N12 G26
USB2P12 F26
USB2P11 C28
USB2N11 A28
USB2P10 D29
USB2P9 C30
USB2N10 B29
USB2N9 A30
USB2P8 C32
USB2N8 A32
USB2N7 G29
USB2P7 H29
USB2P6 L31
USB2N6 K31
USB2P5 G31
USB2P4 D33
USB2N5 F31
USB2N4 B33
USB2P3 C34
USB2N3 A34
USB2P2 C36
USB2N2 A36
USB2P1 C38
USB2N1 A38
USB2P0 D37
USB2N0 B37
PETP_8
BD41
PCIE_IREF
BE30
PCIE_RCOMP
BD29
PETP_3
BC34
PERN_4
AT33
PERP_4
AR33
PETP_4
BC36
PETP_5
BB37
PERN_6
AY38
PETP_6
BE38
PERP_7
AT39
PETN_7
BE40
PETP_7
BC40
PERN_8
AN38
PERP_8
AN39
PETN_8
BD42
USB3RN1 AR26
USB3RP1 AP26
USB3TN1 BE24
USB3TP1 BD23
USB3RN2 AW26
USB3RP2 AV26
USB3TN2 BD25
USBRBIAS# K24
USBRBIAS K26
OC0#/GPIO59 P3
OC1#/GPIO40 V1
OC2#/GPIO41 U2
OC3#/GPIO42 P1
OC4#/GPIO43 M3
OC5#/GPIO9 T1
OC6#/GPIO10 N2
OC7#/GPIO14 M1
TP23 L33
TP6
BB29
TP11
BC30
TP24 M33 T122PAD @T122PAD @
RH210 7.5K_0402_1%RH210 7.5K_0402_1%
1 2
T181PAD @T181PAD @
T180PAD @T180PAD @
CH195 0.1U_0402_10V7KCH195 0.1U_0402_10V7K
1 2
RH218
22.6_0402_1%
RH218
22.6_0402_1%
1 2
T123PAD @T123PAD @
CH194 0.1U_0402_10V7KCH194 0.1U_0402_10V7K
1 2
RH51 0_0402_5%RH51 0_0402_5%
1 2
CH193 0.1U_0402_10V7KCH193 0.1U_0402_10V7K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO16,49
11
01USB X6,PCIEX8,SATAX4
Config
USB X4,PCIEX8,SATAX6
*
waiting check
waiting check
waiting check
waiting
check
Reseve for SKU ID
*PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
*
This signal has a weak internal pull up
On-Die PLL Voltage Regulator
L On-Die PLL Voltage Regulator disable
GPIO28
H On-Die voltage regulator enable
1 1
14"
15"
PCH_GPIO70
0
1
XX
X
X
PCH_GPIO38
X
X
Function
Reserve
X X
PCH_GPIO67
SKU ID
PCH_GPIO16
PCH_GPIO16
PCH_GPIO49
PCH_GPIO49 PCH_GPIO68
KBRST#
S_DGPU_PWR_EN
PCH_GPIO6
PCH_GPIO1
EC_SCI#
EC_SMI#
EC_LID_OUT#
PCH_GPIO12
PCH_GPIO16
PCH_DGPU_PWROK
PCH_BT_DISABLE#
ODD_EN
DS3_WAKE#_R
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO48
PCH_GPIO39
PCH_GPIO49
PCH_GPIO68
PCH_GPIO70
TP_VSS_NCTF
KBRST#
PCH_THRMTRIP#_R H_THRMTRIP#
CPU_PLTRST#
DS3_WAKE#_R
PCH_GPIO28
ODD_DETECT#
PCH_GPIO37
EC_SCI#
EC_SMI#
PCH_GPIO70
PCH_GPIO67
PCH_GPIO38
CMOS_ON# PCH_GPIO68
GC6_EVENT#_R
PCH_S_DGPU_PWR_EN
PCH_S_NVDD_PWR_EN
PCH_GPIO48
PCH_GPIO39
SLAVE_PRESENT#
SLAVE_PRESENT#
EC_SCI#<46>
EC_SMI#<46>
EC_LID_OUT#<46>
PCH_BT_DISABLE#<40>
ODD_EN<44>
PCIE_WAKE#<15,40,41>
PCH_BT_ON#<40>
ODD_DETECT#<44>
GATEA20 <46>
KBRST# <46>
H_CPUPWRGD <6>
H_THRMTRIP# <6>
PCH_THRMTRIP#_R <23,32>
CPU_PLTRST# <6>
PCH_GPIO67<16>
CMOS_ON#<35>
GC6_EVENT#<23,54>
S_DGPU_PWR_EN<32,54,55>
S_NVDD_PWR_EN<32,54>
DGPU_PWROK<27,54,62,63>
HDSW_DDC<37>
HDSW_MAIN<37>
SLAVE_PRESENT#<32>
+3VS
+3VS
+3VS
+3VS
+3VS
+3V_PCH
+3VS
+3VS
+3V_PCH
+3VS
+3VS
+3VS
+3VS
+3VALW
+3VS
+3VS
+3V_PCH
+3VS
+3V_PCH
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RH151710K_0402_5% RH151710K_0402_5% 12
RH240 1K_0402_5%@RH240 1K_0402_5%@
1 2
RH236 10K_0402_5%RH236 10K_0402_5%
1 2
RH154 0_0402_5%RH154 0_0402_5%
1 2
RH228 10K_0402_5%RH228 10K_0402_5%
1 2
RH207 10K_0402_5%
DS3@
RH207 10K_0402_5%
DS3@
12
RH25510K_0402_5% RH25510K_0402_5% 12
RH171
0_0402_5%
RH171
0_0402_5%
1 2
RH247 10K_0402_5%RH247 10K_0402_5%
1 2
RH2310_0402_5% RH2310_0402_5% 12
RH251 0_0402_5%RH251 0_0402_5%
12
RH2250_0402_5% @RH2250_0402_5% @12
RH233 10K_0402_5%RH233 10K_0402_5%
1 2
RH230 10K_0402_5%RH230 10K_0402_5%
1 2
RH161
0_0402_5%
RH161
0_0402_5%
1 2
RH268 10K_0402_5%@RH268 10K_0402_5%@
12
RH712
10K_0402_5%
@
RH712
10K_0402_5%
@
1 2
RH704
10K_0402_5%
RH704
10K_0402_5%
1 2
RH1493
10K_0402_5% RH1493
10K_0402_5% 12
RH243 10K_0402_5%
@
RH243 10K_0402_5%
@
1 2
RH266 10K_0402_5%RH266 10K_0402_5%
12
RH248 10K_0402_5%RH248 10K_0402_5%
1 2
RH242
10K_0402_5%
RH242
10K_0402_5%
1 2
RH709
10K_0402_5%
RH709
10K_0402_5%
1 2
RH711
10K_0402_5%
@
RH711
10K_0402_5%
@
1 2
RH156 0_0402_5%RH156 0_0402_5%
1 2
RH706
10K_0402_5%
@
RH706
10K_0402_5%
@
1 2
RH265 10K_0402_5%RH265 10K_0402_5%
12
RH239 390_0402_5%RH239 390_0402_5%
1 2
RH708
10K_0402_5%
@
RH708
10K_0402_5%
@
1 2
RH238 10K_0402_5%RH238 10K_0402_5%
1 2
LPT_PCH_M_EDS
NCTF
CPU/Misc
GPIO
6 OF 11 REV = 5
UHF
LYNXPOINT_BGA695
LPT_PCH_M_EDS
NCTF
CPU/Misc
GPIO
6 OF 11 REV = 5
UHF
LYNXPOINT_BGA695
TACH6/GPIO70
G13
TACH7/GPIO71
H15
VSS BA1
VSS BC1
VSS N10
VSS A2
VSS BD45
VSS BD2
VSS BD44
VSS BD1
VSS B45
VSS B2
VSS B1
VSS A44
VSS A41
LAN_PHY_PWR_CTRL/GPIO12
K13
GPIO15
AB11
VSS A43
VSS A4
VSS E45
VSS E1
VSS D1
VSS BE3
VSS BE2
TACH4/GPIO68
C16
GPIO57
U12
SDATAOUT1/GPIO48
AN4
GPIO35/NMI#
AP1
GPIO28
AD11
GPIO34
AN6
GPIO27
R11
GPIO24
Y10
SCLOCK/GPIO22
BB4
TACH3/GPIO7
G15
TACH1/GPIO1
F13
PLTRST_PROC# AU4
THRMTRIP# AV1
PROCPWRGD AV3
RCIN# AT6
PECI AY1
SATA5GP/GPIO49
AK3
VSS B44
TACH5/GPIO69
D13
SATA3GP/GPIO37
AK1
SATA2GP/GPIO36
AT3
VSS
A5 VSS
C45 VSS
BE5 VSS
BE41
SDATAOUT0/GPIO39
AM3
SLOAD/GPIO38
AT7
TACH0/GPIO17
C14
SATA4GP/GPIO16
AN2
GPIO8
Y1
TACH2/GPIO6
A14
BMBUSY#/GPIO0
AT8
TP14 AN10
RH229 10K_0402_5%@RH229 10K_0402_5%@
1 2
RH249 0_0402_5%RH249 0_0402_5%
12
RH250
200K_0402_5%
@
RH250
200K_0402_5%
@
1 2
RH232 10K_0402_1%@RH232 10K_0402_1%@
1 2
RH22610K_0402_5% RH22610K_0402_5% 12
RH252
10K_0402_5%
RH252
10K_0402_5%
1 2
RH241 10K_0402_5%RH241 10K_0402_5%
1 2
RH272 10K_0402_5%@RH272 10K_0402_5%@
1 2
RH259 10K_0402_5%RH259 10K_0402_5%
1 2
RH2240_0402_5% @RH2240_0402_5% @12
RH235 10K_0402_5%RH235 10K_0402_5%
12
RH227 10K_0402_5%RH227 10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.312 A
670mA
70mA
+PCH_USB_DCPSUS1
+3VPCH_PCH_VCCSUS3_3
+PCH_USB_DCPSUS1
+PCH_VCCDSW_R
+1.05VS_PCH_VCC
+VCCADAC
+PCH_VCCDSW
+PCH_USB_DCPSUS3
+PCH_USB_DCPSUS3
+3VS_PCH_VCC3_3
+PCH_VCCDSW
+1.05VS_PCH_VCCASW
+1.05VS_PCH_VCCIO
+1.5VS
+3VS
+1.05VS_PCH_VCCIO
+1.05VS_PCH_VCCIO
+1.05V_+1.5V_RUN
+1.05VS_PCH_VCCIO
+1.05VS
+1.05V_+1.5V_RUN
+1.05V_+1.5V_RUN
+1.05VS
+1.05V_+1.5V_RUN
+1.05VS
+3VPCH_PCH_VCCSUS3_3
+3VS_PCH_VCC3_3
+1.05VS_PCH_VCC
+1.05VS_PCH_VCCASW
+1.05VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (7/9) PWR
Custom
20 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (7/9) PWR
Custom
20 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (7/9) PWR
Custom
20 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CH34
1U_0402_6.3V6K
CH34
1U_0402_6.3V6K
1
2
CH82
10U_0603_6.3V6M
@CH82
10U_0603_6.3V6M
@
1
2
CH30
10U_0603_6.3V6M
CH30
10U_0603_6.3V6M
1
2
CH46
1U_0402_6.3V6K
CH46
1U_0402_6.3V6K
1
2
CH48
1U_0402_6.3V6K
CH48
1U_0402_6.3V6K
1
2
CH35
1U_0402_6.3V6K
CH35
1U_0402_6.3V6K
1
2
CH86
1U_0402_6.3V6K
CH86
1U_0402_6.3V6K
1
2
CH32
1U_0402_6.3V6K
CH32
1U_0402_6.3V6K
1
2
CH31
1U_0402_6.3V6K
CH31
1U_0402_6.3V6K
1
2
CH33
1U_0402_6.3V6K
CH33
1U_0402_6.3V6K
1
2
CH36
1U_0402_6.3V6K
CH36
1U_0402_6.3V6K
1
2
RH209
R_short 0_0603_5%
RH209
R_short 0_0603_5%
1 2
CH38
0.1U_0402_10V7K
CH38
0.1U_0402_10V7K
1
2
CH85
10U_0603_6.3V6M
@CH85
10U_0603_6.3V6M
@
1
2
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
USB3
HVCMOS
FDI
CRT DAC
SATA
7 OF 11 REV = 5
UHG
LYNXPOINT_BGA695
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
USB3
HVCMOS
FDI
CRT DAC
SATA
7 OF 11 REV = 5
UHG
LYNXPOINT_BGA695
VCCVRM AN11
VCC
AE18
VCC
AE22
VCCASW
U20
VCCASW
U22
VCCASW
U24
VCCASW
V22
VCCASW
V24
VCCASW
Y18
VCCASW
Y20
VCCASW
Y22
VCCADAC1_5 P45
VSS P43
VCCADACBG3_3 M31
VCCVRM BB44
VCCIO AN34
VCCIO AN35
VCC3_3_R30 R30
VCC3_3_R32 R32
DCPSUS1 Y12
VCCSUS3_3 AJ30
VCCSUS3_3 AJ32
DCPSUS3 AJ26
DCPSUS3 AJ28
VCCIO AK20
VCCVRM AK26
VCCVRM AK28
VCCIO AK18
VCCVRM BE22
VCCIO AM22
VCCIO AP22
VCCIO AR22
VCCIO AT22
VCCASW
V18
VCCASW
V20
VCCASW
U18 VCCASW
AA18 DCPSUSBYP
U14
VCC
Y26 VCC
AG24 VCC
AG22 VCC
AG20
VCC
AA24
VCC
AA26
VCC
AD20
VCC
AD24 VCC
AD22
VCC
AD26
VCC
AD28
VCCIO AK22
VCCIO AM20
VCCIO AM18
VCC
AG18 VCC
AE26 VCC
AE24
VCC
AE20
CH40
10U_0603_6.3V6M
@CH40
10U_0603_6.3V6M
@
1
2
CH83
10U_0603_6.3V6M
@CH83
10U_0603_6.3V6M
@
1
2
J1
JUMP_43X39
J1
JUMP_43X39
11
2
2
CH47
1U_0402_6.3V6K
CH47
1U_0402_6.3V6K
1
2
CH61
1U_0402_6.3V6K
@CH61
1U_0402_6.3V6K
@
1
2
RH1
1_0603_1%
RH1
1_0603_1%
12
RH37 5.11_0402_1%RH37 5.11_0402_1%
1 2
CH39
1U_0402_6.3V6K
@CH39
1U_0402_6.3V6K
@
1
2
RH1990_0603_5% @RH1990_0603_5% @
1 2
RH3600_0402_5% @RH3600_0402_5% @
12
CH44
10U_0603_6.3V6M
CH44
10U_0603_6.3V6M
1
2
CH64
22U_0805_6.3V6M
CH64
22U_0805_6.3V6M
1
2
CH45
1U_0402_6.3V6K
CH45
1U_0402_6.3V6K
1
2
CH80
0.1U_0402_10V7K
CH80
0.1U_0402_10V7K
1
2
CH57
0.01U_0402_16V7K
CH57
0.01U_0402_16V7K
1
2
CH56
10U_0603_6.3V6M
CH56
10U_0603_6.3V6M
1
2
CH81
10U_0603_6.3V6M
@CH81
10U_0603_6.3V6M
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
Place near pin AP45
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
306mA
55mA
3.629A
183mA
133mA
261mA
22mA
10mA
15mA
+PCH_USB_DCPSUS2
+PCH_USB_DCPSUS2
+PCH_VCCSST
+PCH_VCCCFUSE
+PCH_VPROC
+PCH_DCPRTC
+PCH_VCC
+PCH_VPROC
+PCH_VCCDSW3_3
+PCH_VCC
+PCH_VCCCFUSE
+3VPCH_PCH_VCCSUS3_3
+1.05VS
+1.05V_+1.5V_RUN
+3VS
+3V_PCH
+3VALW
+3VS_PCH_VCC3_3
+1.05VS_PCH_VCCIO
+3VPCH_VCCSUSHDA
+3VPCH_PCH_VCCSUS3_3
+1.05VS
+3VS
+1.05V_+1.5V_RUN
+1.05VS
+1.05VS +PCH_VCCCLK
+PCH_VCCCLK
+PCH_VCCCLK
+PCH_VCCCLK3_3
+PCH_VCCCLK3_3
+1.05VS
+3VS_PCH_VCC3_3
+1.05VS_PCH_VCCIO
+3VS_PCH_VCC3_3
+3VPCH_PCH_VCCSUS3_3
+1.05VS +1.05VS_PCH_VCCIO
+3V_PCH +3VPCH_PCH_VCCSUS3_3
+1.5VS +1.05V_+1.5V_RUN
+1.05VS
+3VS_PCH_VCC3_3+3VS
+1.05VS_PCH_VCCASW
+3VS +3VS_PCH_VCCSPI
+3VS_PCH_VCCSPI
+RTCVCC
+3V_PCH +3VPCH_VCCSUSHDA
+1.05VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (8/9) PWR
Custom
21 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (8/9) PWR
Custom
21 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (8/9) PWR
Custom
21 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CH77
1U_0402_6.3V6K
CH77
1U_0402_6.3V6K
1
2
RH361 0_0402_5%@RH361 0_0402_5%@
1 2
CH78
1U_0402_6.3V6K
CH78
1U_0402_6.3V6K
1
2
CH55
0.1U_0402_10V7K
CH55
0.1U_0402_10V7K
1
2
RH212
R_short 0_0805_5%
RH212
R_short 0_0805_5%
1 2
CH73
0.1U_0402_10V7K
CH73
0.1U_0402_10V7K
1
2
CH60
0.1U_0402_10V7K
CH60
0.1U_0402_10V7K
1
2
RH215
R_short 0_0603_5%
RH215
R_short 0_0603_5%
12
CH66
0.1U_0402_10V7K
CH66
0.1U_0402_10V7K
1
2
CH37
1U_0402_6.3V6K
CH37
1U_0402_6.3V6K
1
2
CH59
0.1U_0402_10V7K
CH59
0.1U_0402_10V7K
1
2
CH67
1U_0402_6.3V6K
CH67
1U_0402_6.3V6K
1
2
J2
JUMP_43X39
J2
JUMP_43X39
1
122
CH58
1U_0402_6.3V6K
CH58
1U_0402_6.3V6K
1
2
CH54
1U_0402_6.3V6K
CH54
1U_0402_6.3V6K
1
2
CH42
10U_0603_6.3V6M
CH42
10U_0603_6.3V6M
1
2
CH53
1U_0402_6.3V6K
CH53
1U_0402_6.3V6K
1
2
RH214
R_short 0_0603_5%
RH214
R_short 0_0603_5%
12
RH211
R_short 0_0603_5%
RH211
R_short 0_0603_5%
12
CH49
1U_0402_6.3V6K
CH49
1U_0402_6.3V6K
1
2
RH2010_0402_5% @RH2010_0402_5% @
12
CH51
1U_0402_6.3V6K
CH51
1U_0402_6.3V6K
1
2
CH68
0.1U_0402_10V7K
CH68
0.1U_0402_10V7K
1
2
CH62
0.1U_0402_10V7K
CH62
0.1U_0402_10V7K
1
2
RH200
R_short 0_0805_5%
RH200
R_short 0_0805_5%
1 2
CH79
1U_0402_6.3V6K
CH79
1U_0402_6.3V6K
1
2
CH50
1U_0402_6.3V6K
CH50
1U_0402_6.3V6K
1
2
CH63
0.1U_0402_10V7K
CH63
0.1U_0402_10V7K
1
2
RH219
R_short 0_0805_5%
RH219
R_short 0_0805_5%
12
CH52
1U_0402_6.3V6K
CH52
1U_0402_6.3V6K
1
2
CH76
0.1U_0402_10V7K
CH76
0.1U_0402_10V7K
1
2
RH213
R_short 0_0603_5%
RH213
R_short 0_0603_5%
12
CH75
1U_0402_6.3V6K
CH75
1U_0402_6.3V6K
1
2
RH1516
R_short 0_0603_5%
RH1516
R_short 0_0603_5%
1 2
CH72
0.1U_0402_10V7K
CH72
0.1U_0402_10V7K
1
2
CH84 0.1U_0402_10V7KCH84 0.1U_0402_10V7K
1 2
RH197
R_short 0_0603_5%
RH197
R_short 0_0603_5%
12
LH100
4.7UH_LQM18FN4R7M00D_20%
@
LH100
4.7UH_LQM18FN4R7M00D_20%
@
1 2
LPT_PCH_M_EDS
ICC
Thermal
Fuse
SPI
CPU
RTC
Azalia
GPIO/LPC
USB
8 OF 11 REV = 5
UHH
LYNXPOINT_BGA695
LPT_PCH_M_EDS
ICC
Thermal
Fuse
SPI
CPU
RTC
Azalia
GPIO/LPC
USB
8 OF 11 REV = 5
UHH
LYNXPOINT_BGA695
VCCSUS3_3
R26
VCCSUS3_3
R28
VCCSUS3_3
U26
VSS
M24
VCCUSBPLL
U35
VCC3_3
L24
VCCIO
U30
VCCIO
V30 VCCIO
V28
VCCCLK
Y32
VCCCLK3_3
M29
VCCCLK3_3
L29
VCCCLK3_3
L26
VCCCLK3_3
M26
VCCCLK3_3
U32
VCCCLK3_3
V32
VCCCLK
AD34
VCCCLK
AA30
VCCCLK
AA32
VCCCLK
AD35
VCCCLK
AG30
VCCCLK
AG32
VCCCLK
AD36
VCCCLK
AE30
VCCCLK
AE32
VCCSUS3_3 R20
VCCSUS3_3 R22
VCCDSW3_3 A16
DCPSST AA14
VCC3_3 AE14
VCC3_3 AF12
VCC3_3 AG14
VCCIO U36
VCCSUSHDA A26
VCCSUS3_3 K8
VCCRTC A6
DCPRTC P14
DCPRTC P16
V_PROC_IO AJ12
V_PROC_IO AJ14
VCCSPI AD12
VCC P18
VCC P20
VCCASW L17
VCCASW R18
VCCVRM AW40
VCC3_3 AK30
VCC3_3 AK32
VCC
AP45
VCCVRM
AF34
DCPSUS2
Y35
VCCIO
Y30
VCCSUS3_3
R24
RH1515R_short 0_0402_5% RH1515R_short 0_0402_5% 12
CH88
1U_0402_6.3V6K
CH88
1U_0402_6.3V6K
1
2
CH74
1U_0402_6.3V6K
CH74
1U_0402_6.3V6K
1
2
CH69
0.1U_0402_10V7K
CH69
0.1U_0402_10V7K
1
2
RH2200_0805_5%
@
RH2200_0805_5%
@
12
RH2210_0805_5% RH2210_0805_5%
12
CH71
1U_0402_6.3V6K
CH71
1U_0402_6.3V6K
1
2
CH70
0.1U_0402_10V7K
CH70
0.1U_0402_10V7K
1 2
CH65
0.1U_0402_10V7K
CH65
0.1U_0402_10V7K
1
2
RH198 0_0603_5%@RH198 0_0603_5%@
12
CH87
1U_0402_6.3V6K
@CH87
1U_0402_6.3V6K
@
1
2
CH43
10U_0603_6.3V6M
CH43
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (9/9) VSS
Custom
22 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (9/9) VSS
Custom
22 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PCH (9/9) VSS
Custom
22 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
LPT_PCH_M_EDS
REV = 511 OF 11
UHK
LYNXPOINT_BGA695
LPT_PCH_M_EDS
REV = 511 OF 11
UHK
LYNXPOINT_BGA695
VSS D4
VSS BC16
VSS G2
VSS G38
VSS G44
VSS G8
VSS H10
VSS H13
VSS
AB8
VSS BD31
VSS BD35
VSS BD39
VSS BD7
VSS AV7
VSS F20
VSS F33
VSS
AA16
VSS H36
VSS H26
VSS H17
VSS H22
VSS H24
VSS F29
VSS F15
VSS D25
VSS
AC2
VSS
AB38
VSS
AJ20 VSS
AJ18
VSS
AJ24 VSS
AJ22
VSS K33
VSS K29
VSS K20
VSS K15
VSS K10
VSS H7
VSS H40
VSS H31
VSS AT43
VSS AY36
VSS BD19
VSS BD15
VSS BD11
VSS BA40
VSS B7
VSS B39
VSS B35
VSS B31
VSS B27
VSS B23
VSS B19
VSS
AL2 VSS
AL12 VSS
AK45 VSS
AK43 VSS
AK24 VSS
AK14 VSS
AJ8 VSS
AJ6 VSS
AJ38 VSS
AJ34
VSS
AJ16
VSS
AG16 VSS
AF8 VSS
AF38 VSS
AE28 VSS
AE16 VSS
AD8
VSS
AD16 VSS
AD14 VSS
AC44
VSS
AB34 VSS
AB12 VSS
AA4 VSS
AA28 VSS
AA22 VSS
AA20
VSS
AG44 VSS
AG28 VSS
AG26 VSS
AG2
VSS
AD32 VSS
AD30 VSS
AD18
VSS
BB42 VSS
BC22
VSS BC28
VSS
AD6 VSS
AD40
LPT_PCH_M_EDS
REV = 510 OF 11
UHJ
LYNXPOINT_BGA695
LPT_PCH_M_EDS
REV = 510 OF 11
UHJ
LYNXPOINT_BGA695
VSS
AV31
VSS
BB25
VSS
AV40
VSS
AV33
VSS
AV13 VSS
D42
VSS
AT36
VSS
AT26 VSS
AT20 VSS
AT17
VSS
AT29
VSS
AV24
VSS N12
VSS N39
VSS N35
VSS N6
VSS P24
VSS P22
VSS P30
VSS P28
VSS P26
VSS P32
VSS R12
VSS R2
VSS R16
VSS R14
VSS R38
VSS R34
VSS R44
VSS T43
VSS R8
VSS U16
VSS U10
VSS U28
VSS U34
VSS U38
VSS U6
VSS U42
VSS V14
VSS V16
VSS V26
VSS W44
VSS W2
VSS V43
VSS Y16
VSS Y14
VSS Y24
VSS Y34
VSS Y28
VSS Y40
VSS Y36
VSS Y8
VSS
AT38
VSS
F43
VSS
AT15 VSS
AT10 VSS
AK16 VSS
AR2 VSS
AP43
VSS
AP24
VSS
AN40 VSS
AN36
VSS
AM30 VSS
AM28
VSS M22
VSS M17
VSS L44
VSS L2
VSS K39
VSS
B15 VSS
B11 VSS
AY7 VSS
AY29 VSS
AY26 VSS
AY20 VSS
AY15 VSS
AY10
VSS
AW2 VSS
AV6
VSS
AP31
VSS
AP13 VSS
AN8
VSS
AM32
VSS
AM26 VSS
AM24 VSS
AM14 VSS
AL8 VSS
AL38 VSS
AL34
VSS
AN42
VSS
AM16
VSS
AV22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
150mA
Under GPU(below 150mils)
180ohms (ESR=0.2) Bead
PU AT EC SIDE, +3VS AND 4.7K
60mA
45mA
45mA
Differential signal
Internal Thermal Sensor
Under GPU Near GPU
Close to GPU
220 ohms @100MHz (ESR=0.05)
Under GPU Near GPU
120mA
LVDS
CRT
GPIO 14 of GPU connect to PCH GPIO 0
2012-0418 --> Stuff QV7, RV208
2012-0429 --> Add QV5, C38 has abnormal shutdown issue
Vendor recommand reserve PU/PD resistor
For GC6
+SP_PLLVDD
PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
VGA_SMB_DA2
VGA_SMB_CK2
PCH_THRMTRIP#_R
I2CB_SCL
I2CB_SDA
VGA_CRT_DATA
VGA_CRT_CLK
CLK_PCIE_VGA
CLK_PCIE_VGA#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PLT_RST_VGA#
PEX_TERMP
VGA_SMB_DA2
VGA_SMB_CK2
XTALOUT
XTALSSIN
XTAL_IN
XTAL_OUT
+PLLVDD
+SP_PLLVDD
+PLLVDD
+DACA_VDD
VGA_BL_PWM
VGA_CRT_G
VGA_CRT_B
VGA_CRT_R
+DACA_VDD
OVERT#
VGA_AC_DET_R
VGA_CRT_DATA
VGA_CRT_CLK
I2CB_SCL
I2CB_SDA
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_G
VGA_CRT_R
VGA_CRT_B
+DACA_VREF
DACA_RSET
XTAL_IN
XTAL_OUT
CLK_REQ_GPU#
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N1
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_N0
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
CLK_REQ_GPU#
FB_CLAMP_TOGGLE_REQ#
DGPU_HOLD_RST#
PLT_RST_VGA#
PLT_RST#
DGPU_HDMI_HPD
VGA_ALERT#
OVERT#
FB_CLAMP_MON
FB_CLAMP_TOGGLE_REQ#
NVVDD PWM_VID
VGA_AC_DET_R
VGA_BL_PWM
VGA_ENBKL
VGA_ENVDD
VGA_EDP_HPD
PLT_RST_VGA#
OVERT#
VGA_ALERT#
VGA_AC_DET_R
I2CC_SDA
I2CC_SCL
I2CC_SDA
I2CC_SCL
FB_CLAMP_MON
PCIE_CTX_C_GRX_P[0..15]<32,5>
PCIE_CRX_GTX_N[0..15]<32,5>
PCIE_CRX_GTX_P[0..15]<32,5>
PCIE_CTX_C_GRX_N[0..15]<32,5>
EC_SMB_DA2 <17,32,34,36,43,46>
EC_SMB_CK2 <17,32,34,36,43,46>
PCH_THRMTRIP#_R <19,32>
CLK_PCIE_VGA<16>
CLK_PCIE_VGA#<16>
VGA_CRT_B <37>
VGA_CRT_HSYNC <37>
VGA_CRT_VSYNC <37>
VGA_CRT_G <37>
VGA_CRT_R <37>
VGA_CRT_CLK <37>
VGA_CRT_DATA <37>
CLK_REQ_GPU#_R<16>
DGPU_PWR_EN<14,23,54,55>
GC6_EVENT# <19,54>
DGPU_HOLD_RST#<14,54>
PLT_RST#<14,32,40,41,46>
MEM_VREF <28,29,30,31>
NVVDD PWM_VID <63>
DGPU_HDMI_HPD <37,39>
DPRSLPVR_VGA <63>
VGA_ENBKL <35>
VGA_ENVDD <35>
VGA_BL_PWM <35>
VGA_EDP_HPD <38>
VGA_AC_DET <46>
VGA_AC_DET_R <32>
DGPU_PWR_EN<14,23,54,55>
FB_CLAMP <23,27,54>
PLT_RST_VGA#
FB_CLAMP <23,27,54>
+1.05VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+1.05VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS
+3VS_VGA
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_PCIE/ DAC/ GPIO
Custom
23 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_PCIE/ DAC/ GPIO
Custom
23 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_PCIE/ DAC/ GPIO
Custom
23 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CV151
0.1U_0402_10V7K
@
CV151
0.1U_0402_10V7K
@1
2
RV230
10K_0402_5%
@
RV230
10K_0402_5%
@
1 2
RV25
2.2K_0402_5%
RV25
2.2K_0402_5%
1 2
CV148
0.1U_0402_10V7K
GC6@
CV148
0.1U_0402_10V7K
GC6@
1
2
LV1 BLM18PG181SN1D_2PLV1 BLM18PG181SN1D_2P
1 2
CV125
0.1U_0402_10V7K
@CV125
0.1U_0402_10V7K
@
1
2
RV2610K_0402_5% RV2610K_0402_5%
1 2
CV126
0.1U_0402_10V7K
@CV126
0.1U_0402_10V7K
@
1
2
RV237
10K_0402_5%
GC6@
RV237
10K_0402_5%
GC6@
12
CV40
22U_0805_6.3V6M
CV40
22U_0805_6.3V6M
1
2
CV41 0.22U_0402_10V6KCV41 0.22U_0402_10V6K
1 2
G
D
S
QV5
2N7002KW_SOT323-3
G
D
S
QV5
2N7002KW_SOT323-3
2
13
CV130
0.1U_0402_10V7K
CV130
0.1U_0402_10V7K
1
2
CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K
1 2
CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K
1 2
G
D
S
QV2
LP2301ALT1G_SOT-23
GC6@
G
D
S
QV2
LP2301ALT1G_SOT-23
GC6@
2
13
RV20 200_0402_1%
@
RV20 200_0402_1%
@
1 2
CV5
0.1U_0402_10V7K
CV5
0.1U_0402_10V7K
1
2
RV52
100K_0402_5%
RV52
100K_0402_5%
1 2
QV7A
DMN66D0LDW-7 2N_SOT363-6
@
QV7A
DMN66D0LDW-7 2N_SOT363-6
@
61
2
CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K
1 2
RV232
10K_0402_5%
@RV232
10K_0402_5%
@
1 2
CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K
1 2
CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K
1 2
RV112 0_0402_5%@RV112 0_0402_5%@
1 2
CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K
1 2
G
D
S
QV6
2N7002KW_SOT323-3
G
D
S
QV6
2N7002KW_SOT323-3
2
13
C1061
0.1U_0402_16V4Z
C1061
0.1U_0402_16V4Z
1
2
Crystal
YV1
27MHZ_10PF_7V27000050
Crystal
YV1
27MHZ_10PF_7V27000050
IN
1
OUT 3
GND 2
GND
4
UV1
N14P-GT-A2_FCBGA908
GT@
UV1
N14P-GT-A2_FCBGA908
GT@
CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K
1 2
CV112
22U_0805_6.3V6M
CV112
22U_0805_6.3V6M
1
2
CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K
1 2
RV23 10M_0402_5%RV23 10M_0402_5%
1 2
CV131
0.1U_0402_10V7K
CV131
0.1U_0402_10V7K
1
2
CV127
1U_0402_6.3V6K
CV127
1U_0402_6.3V6K
1
2
CV128
4.7U_0603_6.3V6K
CV128
4.7U_0603_6.3V6K
1
2
PCI EXPRESS
CLK
Part 1 of 7
DACs
I2C
GPIO
UV1A
N14P-GT1-A2_FCBGA908
GT1@
PCI EXPRESS
CLK
Part 1 of 7
DACs
I2C
GPIO
UV1A
N14P-GT1-A2_FCBGA908
GT1@
PEX_RX0
AN12
PEX_RX0_N
AM12
PEX_RX1
AN14
PEX_RX1_N
AM14
PEX_RX2
AP14
PEX_RX2_N
AP15
PEX_RX3
AN15
PEX_RX3_N
AM15
PEX_RX4
AN17
PEX_RX4_N
AM17
PEX_RX5
AP17
PEX_RX5_N
AP18
PEX_RX6
AN18
PEX_RX6_N
AM18
PEX_RX7
AN20
PEX_RX7_N
AM20
PEX_RX8
AP20
PEX_RX8_N
AP21
PEX_RX9
AN21
PEX_RX9_N
AM21
PEX_RX10
AN23
PEX_RX10_N
AM23
PEX_RX11
AP23
PEX_RX11_N
AP24
PEX_RX12
AN24
PEX_RX12_N
AM24
PEX_RX13
AN26
PEX_RX13_N
AM26
PEX_RX14
AP26
PEX_RX14_N
AP27
PEX_RX15
AN27
PEX_RX15_N
AM27
PEX_TX0
AK14
PEX_TX0_N
AJ14
PEX_TX1
AH14
PEX_TX1_N
AG14
PEX_TX2
AK15
PEX_TX2_N
AJ15
PEX_TX3
AL16
PEX_TX3_N
AK16
PEX_TX4
AK17
PEX_TX4_N
AJ17
PEX_TX5
AH17
PEX_TX5_N
AG17
PEX_TX6
AK18
PEX_TX6_N
AJ18
PEX_TX7
AL19
PEX_TX7_N
AK19
PEX_TX8
AK20
PEX_TX8_N
AJ20
PEX_TX9
AH20
PEX_TX9_N
AG20
PEX_TX10
AK21
PEX_TX10_N
AJ21
PEX_TX11
AL22
PEX_TX11_N
AK22
PEX_TX12
AK23
PEX_TX12_N
AJ23
PEX_TX13
AH23
PEX_TX13_N
AG23
PEX_TX14
AK24
PEX_TX14_N
AJ24
PEX_TX15
AL25
PEX_TX15_N
AK25
PEX_REFCLK
AL13
PEX_REFCLK_N
AK13
PEX_RST_N
AJ12
PEX_TSTCLK_OUT
AJ26
PEX_TSTCLK_OUT_N
AK26
PEX_TERMP
AP29
PEX_CLKREQ_N
AK12
PEX_WAKE_N
AJ11
GPIO0 P6
GPIO1 M3
GPIO2 L6
GPIO3 P5
GPIO4 P7
GPIO5 L7
GPIO6 M7
GPIO7 N8
GPIO8 M1
GPIO9 M2
GPIO10 L1
GPIO11 M5
GPIO12 N3
GPIO13 M4
GPIO14 N4
GPIO15 P2
GPIO16 R8
GPIO17 M6
GPIO18 R1
GPIO19 P3
GPIO20 P4
GPIO21 P1
I2CS_SCL T4
I2CS_SDA T3
I2CC_SCL R2
I2CC_SDA R3
I2CB_SCL R7
I2CB_SDA R6
I2CA_SCL R4
I2CA_SDA R5
DACA_HSYNC AM9
DACA_VSYNC AN9
DACA_RED AK9
DACA_GREEN AL10
DACA_BLUE AL9
DACA_VDD AG10
DACA_VREF AP9
DACA_RSET AP8
PLLVDD AD8
SP_PLLVDD AE8
VID_PLLVDD AD7
XTAL_SSIN H1
XTAL_IN H3
XTAL_OUTBUFF J4
XTAL_OUT H2
QV1B
2N7002DW-T/R7_SOT363-6
QV1B
2N7002DW-T/R7_SOT363-6
3
5
4
G
D
S
QV16
2N7002H 1N_SOT23-3
G
D
S
QV16
2N7002H 1N_SOT23-3
2
1 3
RV32
10K_0402_5%
RV32
10K_0402_5%
1 2
CV122
0.1U_0402_10V7K
CV122
0.1U_0402_10V7K
1
2
RV22 2.49K_0402_1%RV22 2.49K_0402_1%
1 2
CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K
1 2
LV5
BLM18PG181SN1D_0603
LV5
BLM18PG181SN1D_0603
12
CV38
10P_0402_50V8J
CV38
10P_0402_50V8J
1
2
RV238
0_0402_5%
GC6@
RV238
0_0402_5%
GC6@
1 2
RV11 2.2K_0402_5%RV11 2.2K_0402_5%
1 2
RV138 0_0402_5%
@
RV138 0_0402_5%
@
1 2
RV208
10K_0402_5%
RV208
10K_0402_5%
12
RV223
10K_0402_5%
RV223
10K_0402_5%
12
CV4
0.1U_0402_10V7K
CV4
0.1U_0402_10V7K
1
2
RV231
10K_0402_5%
RV231
10K_0402_5%
12
CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K
1 2
CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K
1 2
UV2
NC7SZ08P5X_NL_SC70-5
UV2
NC7SZ08P5X_NL_SC70-5
B
2
A
1Y4
P5
G
3
RV27
10K_0402_5%
RV27
10K_0402_5%
12
RV1 10K_0402_5%RV1 10K_0402_5%
1 2
CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K
1 2
RV111
10K_0402_5%
RV111
10K_0402_5%
1 2
RV17 2.2K_0402_5%RV17 2.2K_0402_5%
1 2
RV233 0_0402_5%
@
RV233 0_0402_5%
@
1 2
RV13 2.2K_0402_5%RV13 2.2K_0402_5%
1 2
RV235
10K_0402_5%
GC6@
RV235
10K_0402_5%
GC6@
12
CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K
1 2
RV107
124_0402_1%
RV107
124_0402_1%
12
G
D
S
QV3
2N7002KW_SOT323-3
GC6@
G
D
S
QV3
2N7002KW_SOT323-3
GC6@
2
13
RV65
10K_0402_5%
@
RV65
10K_0402_5%
@
1 2
RV109 150_0402_1%RV109 150_0402_1%
1 2
CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K
1 2
CV139
0.1U_0402_10V7K
CV139
0.1U_0402_10V7K
1
2
RV2 10K_0402_5%RV2 10K_0402_5%
1 2
CV37
10P_0402_50V8J
CV37
10P_0402_50V8J
1
2
RV16 100K_0402_5%RV16 100K_0402_5%
1 2
RV15 2.2K_0402_5%RV15 2.2K_0402_5%
1 2
LV7 0_0402_5%LV7 0_0402_5%
1 2
RV108 150_0402_1%RV108 150_0402_1%
1 2
RV106 150_0402_1%RV106 150_0402_1%
1 2
RV236
10K_0402_5%
GC6@
RV236
10K_0402_5%
GC6@
12
RV10 2.2K_0402_5%RV10 2.2K_0402_5%
1 2
QV7B
DMN66D0LDW-7 2N_SOT363-6
@
QV7B
DMN66D0LDW-7 2N_SOT363-6
@
3
5
4
CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K
1 2
QV1A
2N7002DW-T/R7_SOT363-6
QV1A
2N7002DW-T/R7_SOT363-6
61
2
RV24
2.2K_0402_5%
RV24
2.2K_0402_5%
1 2
RV12 2.2K_0402_5%RV12 2.2K_0402_5%
1 2
R1495 0_0402_5%
@
R1495 0_0402_5%
@
1 2
RV14 2.2K_0402_5%RV14 2.2K_0402_5%
1 2
DV2
RB751V-40_SOD323-2
DV2
RB751V-40_SOD323-2
12
CV113
4.7U_0402_6.3V6M
CV113
4.7U_0402_6.3V6M
1
2
RV239
1K_0402_5% GC6@
RV239
1K_0402_5% GC6@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
trace width: 16mils
differential voltage sensing.
differential signal routing.
for 15" dual channel
20mils
1MB SPI ROM FOR VBIOS ROM (SLI)
For EMI
SA00004EK0J(2012/0813)
20120829 VA1
Change net name for add HDMI MUX
20120829 VA1
Change net name for add HDMI MUX
HDMI
VSSSENSE_VGA
VCCSENSE_VGA
TESTMODE
STRAP0
STRAP2
STRAP1
STRAP3
STRAP4
GPU_HDMI_CLK
GPU_HDMI_DATA
ROM_SI
ROM_SO
ROM_SCLK
ROM_CS#
ROM_CS#
ROM_HOLD#ROM_SO_RROM_SO
ROM_SCLK
ROM_CS#_R
ROM_SCLK_R
ROM_SI_R ROM_SI
VGA_EDP_TX0-
VGA_EDP_TX0+
VGA_EDP_AUX#
VGA_EDP_AUX
VGA_EDP_TX1+
VGA_EDP_TX1-
ROM_SCLK_R
GPU_HDMI_TX1-
GPU_HDMI_TX1+
GPU_HDMI_TX2-
GPU_HDMI_TX2+
GPU_HDMI_CLK-
GPU_HDMI_TX0-
GPU_HDMI_TX0+
GPU_HDMI_CLK+
GPU_HDMI_DATA
GPU_HDMI_CLK
VGA_EDP_AUX
VGA_EDP_AUX#
VCCSENSE_VGA <63>
VSSSENSE_VGA <63>
STRAP0 <33>
STRAP1 <33>
STRAP2 <33>
STRAP3 <33>
STRAP4 <33>
ROM_SI <33>
ROM_SO <33>
ROM_SCLK <33>
GPU_HDMI_DATA<37>
GPU_HDMI_CLK<37>
GPU_HDMI_TX1+<37>
GPU_HDMI_TX0+<37>
GPU_HDMI_TX2-<37>
GPU_HDMI_TX2+<37>
GPU_HDMI_TX1-<37>
GPU_HDMI_CLK+<37>
GPU_HDMI_TX0-<37>
GPU_HDMI_CLK-<37>
VGA_EDP_TX0+<38>
VGA_EDP_TX0-<38>
VGA_EDP_TX1-<38>
VGA_EDP_TX1+<38>
VGA_EDP_AUX<38>
VGA_EDP_AUX#<38>
+3VS_VGA
+3VS_VGA
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_LVDS/ HDMI/ THERM
Custom
24 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_LVDS/ HDMI/ THERM
Custom
24 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_LVDS/ HDMI/ THERM
Custom
24 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RV228 0_0402_5%@
RV228 0_0402_5%@
1 2
RV114 47K_0402_5%RV114 47K_0402_5%
1 2
CV295
0.1U_0402_16V4Z @
CV295
0.1U_0402_16V4Z @
12
RV113 47K_0402_5%RV113 47K_0402_5%
1 2
RV33
10K_0402_5%
RV33
10K_0402_5%
12
RV224 0_0402_5%
@
RV224 0_0402_5%
@
1 2
RV227 0_0402_5%@
RV227 0_0402_5%@
1 2
TV4TV4
TV5TV5
RV38 40.2K_0402_1%RV38 40.2K_0402_1%
1 2
Part 4 of 7
LVDS/TMDS
NC
GENERAL
SERIAL
TEST
UV1D
N14P-GT-A2_FCBGA908
Part 4 of 7
LVDS/TMDS
NC
GENERAL
SERIAL
TEST
UV1D
N14P-GT-A2_FCBGA908
IFPA_TXC_N
AN6 IFPA_TXC
AM6
NC P8
NC AC6
NC AJ28
NC AJ4
NC AJ5
NC AL11
NC C15
NC D19
NC D20
NC D23
NC D26
NC H31
NC T8
IFPA_TXD0
AP3
IFPA_TXD0_N
AN3
IFPA_TXD1
AN5
IFPA_TXD1_N
AM5
IFPA_TXD2
AL6
IFPA_TXD2_N
AK6
IFPA_TXD3
AJ6
IFPA_TXD3_N
AH6
IFPB_TXC
AJ9
IFPB_TXC_N
AH9
IFPB_TXD4
AP6
IFPB_TXD4_N
AP5
IFPB_TXD5
AM7
IFPB_TXD5_N
AL7
IFPB_TXD6
AN8
IFPB_TXD6_N
AM8
IFPB_TXD7
AK8
IFPB_TXD7_N
AL8
IFPC_L0
AK1
IFPC_L0_N
AJ1
IFPC_L1
AJ3
IFPC_L1_N
AJ2
IFPC_L2
AH3
IFPC_L2_N
AH4
IFPC_L3
AG5
IFPC_L3_N
AG4
IFPD_L0
AM1
IFPD_L0_N
AM2
IFPD_L1
AM3
IFPD_L1_N
AM4
NC V32
IFPD_L2_N
AL4
IFPD_L3_N
AK5
IFPD_L2
AL3
IFPD_L3
AK4
IFPE_L0
AD2
IFPE_L0_N
AD3
IFPE_L1
AD1
IFPE_L1_N
AC1
IFPE_L2
AC2
IFPE_L2_N
AC3
IFPE_L3
AC4
IFPE_L3_N
AC5
IFPF_L0
AE3
IFPF_L0_N
AE4
IFPF_L1
AF4
IFPF_L1_N
AF5
IFPF_L2
AD4
IFPF_L2_N
AD5
IFPF_L3
AG1
IFPF_L3_N
AF1
STRAP0 J2
STRAP1 J7
STRAP2 J6
CEC L3
THERMDP K3
THERMDN K4
ROM_CS_N H6
ROM_SI H5
ROM_SO H7
ROM_SCLK H4
IFPF_AUX_I2CZ_SCL
AF3
IFPF_AUX_I2CZ_SDA_N
AF2
IFPE_AUX_I2CY_SCL
AB3
IFPE_AUX_I2CY_SDA_N
AB4
IFPD_AUX_I2CX_SCL
AK3
IFPD_AUX_I2CX_SDA_N
AK2
IFPC_AUX_I2CW_SCL
AG3
IFPC_AUX_I2CW_SDA_N
AG2
VDD_SENSE L4
GND_SENSE L5
BUFRST_N L2
MULTI_STRAP_REF0_GND J1
TESTMODE AK11
JTAG_TCK AM10
JTAG_TDI AM11
JTAG_TDO AP12
JTAG_TMS AP11
JTAG_TRST_N AN11
STRAP3 J5
STRAP4 J3
TV3TV3
RV30100K_0402_5% RV30100K_0402_5%
12
RV226 0_0402_5%
@
RV226 0_0402_5%
@
1 2
RV34 10K_0402_5%RV34 10K_0402_5%
1 2
RV35 10K_0402_5%RV35 10K_0402_5%
12
RV19100K_0402_5% RV19100K_0402_5%
12
RV229
10K_0402_5% @
RV229
10K_0402_5% @
12
RV225
10K_0402_5%
@RV225
10K_0402_5%
@
12
UV15
MX25L2006EMIT-12G SOP
@
UV15
MX25L2006EMIT-12G SOP
@
VCC 8
HOLD# 7
CLK 6
DIO 5
GND
4WP#
3DO
2CS#
1
CH201
10P_0402_50V8J
@CH201
10P_0402_50V8J
@
1
2
TV2TV2
RH123 10_0402_5%
@
RH123 10_0402_5%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Near GPU
2000mA
3.5A
Under GPU(below 150mils)
For GDDR5 setting. Near GPU
Under GPU(below 150mils)
Under GPU(below 150mils)
Place near balls Place near GPU
120mA
Place near balls
Place near balls
GDDR5
40.2Ohm
40.2Ohm
60.4Ohm
CALIBRATION PIN
FB_CAL_x_PD_VDDQ
FB_CAL_x_PU_GND
FB_CAL_xTERM_GND
Place near balls
220mA
300ohms @100MHz (ESR=0.25)
P/N: SM010031680
Place near balls
Place near balls
570mA
220ohms @100MHz (ESR=0.05)
180ohms @100MHz (ESR=0.2)
P/N: SM010030710
IFPA_IOVDD and
IFPB_IOVDD combined
200mA
120ohms @100MHz (ESR=0.18)
P/N:SM01000BZ00
Place near balls
IFPAB & IFPEF have to use
+PEX_PLLVDD
+IFPAB_PLLVDD
+IFPAB_IOVDD
+IFPE_IOVDD
+IFPC_PLLVDD
+IFPD_PLLVDD
+IFPC_IOVDD
+IFPD_IOVDD
+IFPEF_PLLVDD
+PEX_PLLVDD
+VDD33
FB_VDDQ_SENSE
FB_VSS_SENSE
+IFPEF_PLLVDD
+IFPE_IOVDD +IFPD_IOVDD
+IFPD_PLLVDD
VDDQ_SENSE<61>
+1.5VS_VGA
+1.5VS_VGA
+1.05VS_VGA
+1.05VS_VGA
+3VS_VGA
+3VS_VGA
+1.05VS_VGA
+1.5VS_VGA
+3VS_VGA
+1.05VS_VGA
+3VS_VGA
+1.05VS_VGA
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_Power
Custom
25 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_Power
Custom
25 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_Power
Custom
25 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CV74
4.7U_0603_6.3V6K
CV74
4.7U_0603_6.3V6K
1
2
CV149
4.7U_0603_6.3V6K
CV149
4.7U_0603_6.3V6K
1
2
CV43
1U_0402_6.3V6K
CV43
1U_0402_6.3V6K
1
2
RV4710K_0402_5%
@
RV4710K_0402_5%
@
1 2
CV172
1U_0402_6.3V6K
CV172
1U_0402_6.3V6K
1
2
CV287
0.1U_0402_10V7K
CV287
0.1U_0402_10V7K
1
2
RV4410K_0402_5%
@
RV4410K_0402_5%
@
1 2
CV173
0.1U_0402_10V7K
CV173
0.1U_0402_10V7K
1
2
CV281
1U_0402_6.3V6K
CV281
1U_0402_6.3V6K
1
2
CV152
4.7U_0603_6.3V6K
CV152
4.7U_0603_6.3V6K
1
2
RV6 40.2_0402_1%RV6 40.2_0402_1%
1 2
CV45
1U_0402_6.3V6K
CV45
1U_0402_6.3V6K
1
2
RV4510K_0402_5%
@
RV4510K_0402_5%
@
1 2
CV284
0.1U_0402_10V7K
CV284
0.1U_0402_10V7K
1
2
CV285
0.1U_0402_10V7K
CV285
0.1U_0402_10V7K
1
2
CV272
10U_0603_6.3V6M
CV272
10U_0603_6.3V6M
1
2
RV141 R_short 0_0402_5%RV141 R_short 0_0402_5%
1 2
RV431K_0402_1% @RV431K_0402_1% @
12
CV75
4.7U_0603_6.3V6K
CV75
4.7U_0603_6.3V6K
1
2
CV293
1U_0402_6.3V6K
CV293
1U_0402_6.3V6K
1
2
CV73
4.7U_0603_6.3V6K
CV73
4.7U_0603_6.3V6K
1
2
CV274
22U_0805_6.3V6M
CV274
22U_0805_6.3V6M
1
2
RV4210K_0402_5%
@
RV4210K_0402_5%
@
1 2
LV9
BLM18PG181SN1D_0603
LV9
BLM18PG181SN1D_0603
12
CV216
0.1U_0402_10V7K
CV216
0.1U_0402_10V7K
1
2
LV4
BLM18PG181SN1D_0603
LV4
BLM18PG181SN1D_0603
12
CV279
1U_0402_6.3V6K
CV279
1U_0402_6.3V6K
1
2
CV140
1U_0402_6.3V6K
CV140
1U_0402_6.3V6K
1
2
CV46
1U_0402_6.3V6K
CV46
1U_0402_6.3V6K
1
2
CV267
4.7U_0603_6.3V6K
CV267
4.7U_0603_6.3V6K
1
2
CV141
0.1U_0402_10V7K
CV141
0.1U_0402_10V7K
1
2
CV52
10U_0603_6.3V6M
CV52
10U_0603_6.3V6M
1
2
CV286
0.1U_0402_10V7K
CV286
0.1U_0402_10V7K
1
2
CV280
1U_0402_6.3V6K
CV280
1U_0402_6.3V6K
1
2
CV264
4.7U_0603_6.3V6K
CV264
4.7U_0603_6.3V6K
1
2
RV501K_0402_1% RV501K_0402_1%
12
CV56
22U_0805_6.3V6M
CV56
22U_0805_6.3V6M
1
2
CV111
0.1U_0402_10V7K
CV111
0.1U_0402_10V7K
1
2
CV54
22U_0805_6.3V6M
CV54
22U_0805_6.3V6M
1
2
CV176
1U_0402_6.3V6K
CV176
1U_0402_6.3V6K
1
2
CV270
10U_0603_6.3V6M
CV270
10U_0603_6.3V6M
1
2
CV265
4.7U_0603_6.3V6K
CV265
4.7U_0603_6.3V6K
1
2
CV50
10U_0603_6.3V6M
CV50
10U_0603_6.3V6M
1
2
CV277
1U_0402_6.3V6K
CV277
1U_0402_6.3V6K
1
2
RV8 40.2_0402_1%RV8 40.2_0402_1%
1 2
CV3
1U_0603_10V6K
CV3
1U_0603_10V6K
1
2
CV263
4.7U_0603_6.3V6K
CV263
4.7U_0603_6.3V6K
1
2
CV53
22U_0805_6.3V6M
CV53
22U_0805_6.3V6M
1
2
CV268
4.7U_0603_6.3V6K
CV268
4.7U_0603_6.3V6K
1
2
CV271
10U_0603_6.3V6M
CV271
10U_0603_6.3V6M
1
2
RV461K_0402_1% RV461K_0402_1%
12
CV109
0.1U_0402_10V7K
CV109
0.1U_0402_10V7K
1
2
CV55
22U_0805_6.3V6M
CV55
22U_0805_6.3V6M
1
2
CV269
10U_0603_6.3V6M
CV269
10U_0603_6.3V6M
1
2
CV276
22U_0805_6.3V6M
CV276
22U_0805_6.3V6M
1
2
CV70
0.1U_0402_10V7K
CV70
0.1U_0402_10V7K
1
2
CV292
0.1U_0402_10V7K
CV292
0.1U_0402_10V7K
1
2
RV142 R_short 0_0402_5%RV142 R_short 0_0402_5%
1 2
CV48
4.7U_0603_6.3V6K
CV48
4.7U_0603_6.3V6K
1
2
CV294
0.1U_0402_10V7K
CV294
0.1U_0402_10V7K
1
2
CV65
0.1U_0402_10V7K
CV65
0.1U_0402_10V7K
1
2
CV150
0.1U_0402_10V7K
CV150
0.1U_0402_10V7K
1
2
CV266
4.7U_0603_6.3V6K
CV266
4.7U_0603_6.3V6K
1
2
RV5
R_short 0_0603_5%
RV5
R_short 0_0603_5%
12
CV47
4.7U_0603_6.3V6K
CV47
4.7U_0603_6.3V6K
1
2
CV66
4.7U_0805_25V6-K
CV66
4.7U_0805_25V6-K
1
2
CV158
0.1U_0402_10V7K
CV158
0.1U_0402_10V7K
1
2
RV9 60.4_0402_1%RV9 60.4_0402_1%
1 2
CV171
0.1U_0402_10V7K
CV171
0.1U_0402_10V7K
1
2
CV147
1U_0402_6.3V6K
CV147
1U_0402_6.3V6K
1
2
RV401K_0402_1%
@
RV401K_0402_1%
@
12
Part 5 of 7
POWER
UV1E
N14P-GT-A2_FCBGA908
Part 5 of 7
POWER
UV1E
N14P-GT-A2_FCBGA908
PEX_IOVDDQ_0 AG13
PEX_IOVDDQ_1 AG15
PEX_IOVDDQ_2 AG16
PEX_IOVDDQ_3 AG18
PEX_IOVDDQ_4 AG25
PEX_IOVDDQ_5 AH15
PEX_IOVDDQ_6 AH18
PEX_IOVDDQ_7 AH26
PEX_IOVDDQ_8 AH27
PEX_IOVDDQ_9 AJ27
PEX_IOVDDQ_10 AK27
PEX_IOVDDQ_11 AL27
PEX_IOVDDQ_12 AM28
PEX_IOVDDQ_13 AN28
PEX_IOVDD_0 AG19
PEX_IOVDD_1 AG21
PEX_IOVDD_2 AG22
PEX_IOVDD_3 AG24
PEX_IOVDD_4 AH21
PEX_SVDD_3V3 AG12
VDD33_0 J8
VDD33_1 K8
VDD33_2 L8
VDD33_3 M8
PEX_PLL_HVDD AH12
FBVDDQ_0
AA27
FBVDDQ_1
AA30
FBVDDQ_2
AB27
FBVDDQ_3
AB33
FBVDDQ_4
AC27
FBVDDQ_5
AD27
FBVDDQ_6
AE27
FBVDDQ_7
AF27
FBVDDQ_8
AG27
FBVDDQ_9
B13
FBVDDQ_10
B16
FBVDDQ_11
B19
FBVDDQ_12
E13
FBVDDQ_13
E16
FBVDDQ_14
E19
FBVDDQ_15
H10
FBVDDQ_16
H11
FBVDDQ_17
H12
FBVDDQ_18
H13
FBVDDQ_19
H14
FBVDDQ_20
H15
FBVDDQ_21
H16
FBVDDQ_22
H18
FBVDDQ_23
H19
FBVDDQ_24
H20
FBVDDQ_25
H21
FBVDDQ_26
H22
FBVDDQ_27
H23
FBVDDQ_28
H24
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
M27
FBVDDQ_33
N27
FBVDDQ_34
P27
FBVDDQ_35
R27
FBVDDQ_36
T27
FBVDDQ_37
T30
FBVDDQ_38
T33
FBVDDQ_39
V27
FBVDDQ_40
W27
FBVDDQ_41
W30
FBVDDQ_42
W33
FBVDDQ_43
Y27
PEX_IOVDD_5 AH25
PEX_PLLVDD AG26
IFPA_IOVDD AG8
IFPB_IOVDD AG9
IFPAB_PLLVDD AH8
IFPAB_RSET AJ8
IFPC_IOVDD AF6
IFPC_PLLVDD AF7
IFPC_RSET AF8
IFPD_IOVDD AG6
IFPD_PLLVDD AG7
IFPD_RSET AN2
IFPE_IOVDD AC7
IFPEF_PLVDD AB8
IFPEF_RSET AD6
IFPF_IOVDD AC8
FB_VDDQ_SENSE
F1
FB_GND_SENSE
F2
FB_CAL_PD_VDDQ
J27
FB_CAL_PU_GND
H27
FB_CAL_TERM_GND
H25
CV49
10U_0603_6.3V6M
CV49
10U_0603_6.3V6M
1
2
CV197
0.1U_0402_10V7K
CV197
0.1U_0402_10V7K
1
2
LV6
BLM18PG181SN1D_0603
LV6
BLM18PG181SN1D_0603
12
CV273
22U_0805_6.3V6M
CV273
22U_0805_6.3V6M
1
2
CV146
4.7U_0603_6.3V6K
CV146
4.7U_0603_6.3V6K
1
2
LV10
BLM18PG181SN1D_0603
LV10
BLM18PG181SN1D_0603
12
CV51
10U_0603_6.3V6M
CV51
10U_0603_6.3V6M
1
2
CV153
0.1U_0402_10V7K
CV153
0.1U_0402_10V7K
1
2
CV282
1U_0402_6.3V6K
CV282
1U_0402_6.3V6K
1
2
CV44
1U_0402_6.3V6K
CV44
1U_0402_6.3V6K
1
2
CV156
4.7U_0603_6.3V6K
CV156
4.7U_0603_6.3V6K
1
2
CV275
22U_0805_6.3V6M
CV275
22U_0805_6.3V6M
1
2
RV4
0_0603_5%
RV4
0_0603_5%
12
CV278
1U_0402_6.3V6K
CV278
1U_0402_6.3V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VGA_CORE
+VGA_CORE
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_+VGA CORE, GND
Custom
26 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_+VGA CORE, GND
Custom
26 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_+VGA CORE, GND
Custom
26 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
GND
Part 6 of 7
UV1F
N13P-GT1-A2_FCBGA908
GND
Part 6 of 7
UV1F
N13P-GT1-A2_FCBGA908
GND_0
A2
GND_1
AA17
GND_2
AA18
GND_3
AA20
GND_4
AA22
GND_5
AB12
GND_6
AB14
GND_7
AB16
GND_8
AB19
GND_9
AB2
GND_10
AB21
GND_11
A33
GND_12
AB23
GND_13
AB28
GND_14
AB30
GND_15
AB32
GND_16
AB5
GND_17
AB7
GND_18
AC13
GND_19
AC15
GND_20
AC17
GND_21
AC18
GND_22
AA13
GND_23
AC20
GND_24
AC22
GND_25
AE2
GND_26
AE28
GND_27
AE30
GND_28
AE32
GND_29
AE33
GND_30
AE5
GND_31
AE7
GND_32
AH10
GND_33
AA15
GND_34
AH13
GND_35
AH16
GND_36
AH19
GND_37
AH2
GND_38
AH22
GND_39
AH24
GND_40
AH28
GND_41
AH29
GND_42
AH30
GND_43
AH32
GND_44
AH33
GND_45
AH5
GND_46
AH7
GND_47
AJ7
GND_48
AK10
GND_49
AK7
GND_50
AL12
GND_51
AL14
GND_52
AL15
GND_53
AL17
GND_54
AL18
GND_55
AL2
GND_56
AL20
GND_57
AL21
GND_58
AL23
GND_59
AL24
GND_60
AL26
GND_61
AL28
GND_62
AL30
GND_63
AL32
GND_64
AL33
GND_65
AL5
GND_66
AM13
GND_67
AM16
GND_68
AM19
GND_69
AM22
GND_70
AM25
GND_71
AN1
GND_72
AN10
GND_73
AN13
GND_74
AN16
GND_75
AN19
GND_76
AN22
GND_77
AN25
GND_78
AN30
GND_79
AN34
GND_80
AN4
GND_81
AN7
GND_82
AP2
GND_83
AP33
GND_84
B1
GND_85
B10
GND_86
B22
GND_87
B25
GND_88
B28
GND_89
B31
GND_90
B34
GND_91
B4
GND_92
B7
GND_93
C10
GND_94
C13
GND_95
C19
GND_96
C22
GND_97
C25
GND_98
C28
GND_99
C7
GND_100 D2
GND_101 D31
GND_102 D33
GND_103 E10
GND_104 E22
GND_105 E25
GND_106 E5
GND_107 E7
GND_108 F28
GND_109 F7
GND_110 G10
GND_111 G13
GND_112 G16
GND_113 G19
GND_114 G2
GND_115 G22
GND_116 G25
GND_117 G28
GND_118 G3
GND_119 G30
GND_120 G32
GND_121 G33
GND_122 G5
GND_123 G7
GND_124 K2
GND_125 K28
GND_126 K30
GND_127 K32
GND_128 K33
GND_129 K5
GND_130 K7
GND_131 M13
GND_132 M15
GND_133 M17
GND_134 M18
GND_135 M20
GND_136 M22
GND_137 N12
GND_138 N14
GND_139 N16
GND_140 N19
GND_141 N2
GND_142 N21
GND_143 N23
GND_144 N28
GND_145 N30
GND_146 N32
GND_147 N33
GND_148 N5
GND_149 N7
GND_150 P13
GND_151 P15
GND_152 P17
GND_153 P18
GND_154 P20
GND_155 P22
GND_156 R12
GND_157 R14
GND_158 R16
GND_159 R19
GND_160 R21
GND_161 R23
GND_162 T13
GND_163 T15
GND_164 T17
GND_165 T18
GND_166 T2
GND_167 T20
GND_168 T22
GND_169 AG11
GND_170 T28
GND_171 T32
GND_172 T5
GND_173 T7
GND_174 U12
GND_175 U14
GND_176 U16
GND_177 U19
GND_178 U21
GND_179 U23
GND_180 V12
GND_181 V14
GND_182 V16
GND_183 V19
GND_184 V21
GND_185 V23
GND_186 W13
GND_187 W15
GND_188 W17
GND_189 W18
GND_190 W20
GND_191 W22
GND_192 W28
GND_193 Y12
GND_194 Y14
GND_195 Y16
GND_196 Y19
GND_197 Y21
GND_198 Y23
GND_199 AH11
GND_OPT C16
GND_OPT W32
POWER
Part 7 of 7
UV1G
N13P-GT1-A2_FCBGA908
POWER
Part 7 of 7
UV1G
N13P-GT1-A2_FCBGA908
VDD_0
AA12
VDD_1
AA14
VDD_2
AA16
VDD_3
AA19
VDD_4
AA21
VDD_5
AA23
VDD_6
AB13
VDD_7
AB15
VDD_8
AB17
VDD_9
AB18
VDD_10
AB20
VDD_11
AB22
VDD_12
AC12
VDD_13
AC14
VDD_14
AC16
VDD_15
AC19
VDD_16
AC21
VDD_17
AC23
VDD_18
M12
VDD_19
M14
VDD_20
M16
VDD_21
M19
VDD_22
M21
VDD_23
M23
VDD_24
N13
VDD_25
N15
VDD_26
N17
VDD_27
N18
VDD_28
N20
VDD_29
N22
VDD_30
P12
VDD_31
P14
VDD_32
P16
VDD_33
P19
VDD_34
P21
VDD_35
P23
VDD_36
R13
VDD_37
R15
VDD_38
R17
VDD_39
R18
VDD_40
R20
VDD_41
R22
VDD_42
T12
VDD_43
T14
VDD_44
T16
VDD_45
T19
VDD_46
T21
VDD_47
T23
VDD_48
U13
VDD_49
U15
VDD_50
U17
VDD_51
U18
VDD_52
U20
VDD_53
U22
VDD_54
V13
VDD_55
V15
VDD_58 V20
VDD_59 V22
VDD_60 W12
VDD_61 W14
VDD_62 W16
VDD_63 W19
VDD_64 W21
VDD_65 W23
VDD_66 Y13
VDD_67 Y15
VDD_68 Y17
VDD_69 Y18
VDD_70 Y20
VDD_71 Y22
VDD_56 V17
VDD_57 V18
XVDD_1 U1
XVDD_2 U2
XVDD_3 U3
XVDD_4 U4
XVDD_5 U5
XVDD_6 U6
XVDD_7 U7
XVDD_8 U8
XVDD_9 V1
XVDD_10 V2
XVDD_11 V3
XVDD_12 V4
XVDD_13 V5
XVDD_14 V6
XVDD_15 V7
XVDD_16 V8
XVDD_17 W2
XVDD_18 W3
XVDD_19 W4
XVDD_20 W5
XVDD_21 W7
XVDD_22 W8
XVDD_23 Y1
XVDD_24 Y2
XVDD_25 Y3
XVDD_26 Y4
XVDD_27 Y5
XVDD_28 Y6
XVDD_29 Y7
XVDD_30 Y8
XVDD_31 AA1
XVDD_32 AA2
XVDD_33 AA3
XVDD_34 AA4
XVDD_35 AA5
XVDD_36 AA6
XVDD_37 AA7
XVDD_38 AA8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
30ohms (ESR=0.01) Bead
P/N;SM010007W00
200mA
Place close to ball
Place close to ball Place close to BGA
Place close to BGA
Place close to ball
PU for X16 modePU for X16 mode
FBx_CMD31
RST#
GDDR5
Mode H - Mirror Mode Mapping
DATA Bus
32..630..31
Address
FBx_CMD1
FBx_CMD0
FBx_CMD3
FBx_CMD4
FBx_CMD6
FBx_CMD2
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD5
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD11
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD15
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD30
FBx_CMD29
FBx_CMD28
FBx_CMD23
A4_BA2
ABI#
A6_A11
RST#
A5_BA1
A7_A8
A0_A10
A12_RFU
A3_BA3
A1_A9
CS#
A2_BA0
WE#
CAS#
CS#
ABI#
A1_A9
CKE#
A4_BA2
CAS#
A6_A11
A5_BA1
A0_A10
A7_A8
A12_RFU
WE#
CKE#
A3_BA3
RAS#
RAS#
A2_BA0
GC6 support on 15"
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D16
FBC_D18
FBC_D11
FBC_D7
FBC_D17
FBC_D1
FBC_D14
FBC_D3
FBC_D5
FBC_D15
FBC_D4
FBC_D2
FBC_D13
FBC_D6
FBC_D10
FBC_D9
FBC_D12
FBC_D8
FBC_D0
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D19
FBC_D57
FBC_D58
FBC_D20
FBC_D59
FBC_D21
FBC_D60
FBC_D22
FBC_D61
FBC_D23
FBC_D62
FBC_D63
FBC_D[0..63]
FBA_D16
FBA_D59
FBA_D50
FBA_D18
FBA_D40
FBA_D24
FBA_D22
FBA_D47
FBA_D17
FBA_D55
FBA_D46
FBA_D30
FBA_D7
FBA_D11
FBA_D14
FBA_D26
FBA_D53
FBA_D58
FBA_D1
FBA_D43
FBA_D21
FBA_D45
FBA_D52
FBA_D49
FBA_D60
FBA_D25
FBA_D15
FBA_D5
FBA_D3
FBA_D23
FBA_D56
FBA_D2
FBA_D4
FBA_D41
FBA_D61
FBA_D33
FBA_D44
FBA_D6
FBA_D13
FBA_D57
FBA_D10
FBA_D36
FBA_D27
FBA_D20
FBA_D32
FBA_D54
FBA_D48
FBA_D9
FBA_D38
FBA_D19
FBA_D51
FBA_D8
FBA_D62
FBA_D28
FBA_D34
FBA_D12
FBA_D0
FBA_D29
FBA_D35
FBA_D31
FBA_D63
FBA_D37
FBA_D39
FBA_D42
FBA_D[0..63]
FBA_MA6_MA11_L
FBA_MA2_BA0_L
FBA_MA1_MA9_L
FBA_CS#_L
FBA_WE#_L
FBA_ABI#_L
FBA_MA12_RFU_L
FBA_MA4_BA2_L
FBA_MA5_BA1_L
FBA_MA7_MA8_L
FBA_MA3_BA3_L
FBA_DBI4#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI6#
FBA_DBI5#
FBA_DBI7#
FBA_DBI0#
FBA_EDC1
FBA_EDC0
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK0
FBA_WCK3
FBA_WCK3_N
FBA_WCK0_N
FBA_CLK1
FBA_CLK1#
FBA_CLK0
FBA_CLK0#
FBC_DBI4#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
FBC_DBI0#
FBC_EDC1
FBC_EDC0
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK0
FBC_WCK3
FBC_WCK3_N
FBC_WCK0_N
FBC_CLK1
FBC_CLK1#
FBC_CLK0
FBC_CLK0#
FBC_MA6_MA11_L
FBC_MA2_BA0_L
FBC_MA1_MA9_L
FBC_CS#_L
FBC_WE#_L
FBC_ABI#_L
FBC_MA12_RFU_L
FBC_MA4_BA2_L
FBC_MA5_BA1_L
FBC_MA7_MA8_L
FBC_MA3_BA3_L
+FB_PLLAVDD
FBA_RST#_L
FBA_RST#_H
FBA_MA0_MA10_L
FBA_RAS#_L
FBA_CKE_L
FBA_RST#_L
FBA_MA7_MA8_H
FBA_MA4_BA2_H
FBA_CS#_H
FBA_MA0_MA10_H
FBA_MA1_MA9_H
FBA_MA6_MA11_H
FBA_MA5_BA1_H
FBA_MA3_BA3_H
FBA_RAS#_H
FBA_ABI#_H
FBA_WE#_H
FBA_MA2_BA0_H
FBA_RST#_H
FBA_MA12_RFU_H
FBA_CKE_H
FBA_CAS#_L
FBA_CAS#_H
FBC_RST#_L
FBC_RST#_H
FBC_MA0_MA10_L
FBC_RAS#_L
FBC_CAS#_L
FBC_CKE_L
FBC_CS#_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA4_BA2_H
FBC_MA5_BA1_H
FBC_WE#_H
FBC_MA7_MA8_H
FBC_MA6_MA11_H
FBC_ABI#_H
FBC_MA12_RFU_H
FBC_MA0_MA10_H
FBC_MA1_MA9_H
FBC_RAS#_H
FBC_RST#_L
FBC_RST#_H
FBC_CAS#_H
FBC_CKE_H
FB_CLAMP
FB_CLAMP GC6_EN
FBC_D[0..63]<30,31>
FBA_D[0..63]<28,29>
FBA_MA5_BA1_L <28>
FBA_WE#_L <28>
FBA_CS#_L <28>
FBA_MA7_MA8_L <28>
FBA_MA6_MA11_L <28>
FBA_ABI#_L <28>
FBA_MA12_RFU_L <28>
FBA_MA1_MA9_L <28>
FBA_MA3_BA3_L <28>
FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBA_DBI0#<28>
FBA_DBI1#<28>
FBA_DBI2#<28>
FBA_DBI3#<28>
FBA_DBI7#<29>
FBA_DBI4#<29>
FBA_DBI5#<29>
FBA_DBI6#<29>
FBA_WCK0_N <28>
FBA_WCK1_N <28>
FBA_WCK2_N <29>
FBA_WCK3_N <29>
FBA_WCK3 <29>
FBA_WCK0 <28>
FBA_WCK1 <28>
FBA_WCK2 <29>
FBA_CLK1 <29>
FBA_CLK1# <29>
FBA_CLK0# <28>
FBA_CLK0 <28>
FBC_DBI0#<30>
FBC_DBI1#<30>
FBC_DBI2#<30>
FBC_DBI3#<30>
FBC_DBI7#<31>
FBC_DBI4#<31>
FBC_DBI5#<31>
FBC_DBI6#<31>
FBC_EDC[3..0]<30>
FBC_EDC[7..4]<31>
FBC_WCK3_N <31>
FBC_WCK0_N <30>
FBC_WCK1_N <30>
FBC_WCK2_N <31>
FBC_WCK3 <31>
FBC_WCK0 <30>
FBC_WCK1 <30>
FBC_WCK2 <31>
FBC_CLK1# <31>
FBC_CLK1 <31>
FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_MA5_BA1_L <30>
FBC_WE#_L <30>
FBC_CS#_L <30>
FBC_MA7_MA8_L <30>
FBC_MA6_MA11_L <30>
FBC_ABI#_L <30>
FBC_MA12_RFU_L <30>
FBC_MA1_MA9_L <30>
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
FBC_MA4_BA2_L <30>
FBA_EDC[3..0]<28>
FBA_EDC[7..4]<29>
FBA_MA0_MA10_L <28>
FBA_RAS#_L <28>
FBA_RST#_L <28>
FBA_CKE_L <28>
FBA_MA7_MA8_H <29>
FBA_MA4_BA2_H <29>
FBA_CS#_H <29>
FBA_MA0_MA10_H <29>
FBA_MA1_MA9_H <29>
FBA_MA6_MA11_H <29>
FBA_MA5_BA1_H <29>
FBA_MA3_BA3_H <29>
FBA_RAS#_H <29>
FBA_ABI#_H <29>
FBA_WE#_H <29>
FBA_MA2_BA0_H <29>
FBA_RST#_H <29>
FBA_MA12_RFU_H <29>
FBA_CKE_H <29>
FBA_CAS#_L <28>
FBA_CAS#_H <29>
FBC_MA0_MA10_L <30>
FBC_RAS#_L <30>
FBC_CAS#_L <30>
FBC_CKE_L <30>
FBC_CS#_H <31>
FBC_MA3_BA3_H <31>
FBC_MA2_BA0_H <31>
FBC_MA4_BA2_H <31>
FBC_MA5_BA1_H <31>
FBC_WE#_H <31>
FBC_MA7_MA8_H <31>
FBC_MA6_MA11_H <31>
FBC_ABI#_H <31>
FBC_MA12_RFU_H <31>
FBC_MA0_MA10_H <31>
FBC_MA1_MA9_H <31>
FBC_RAS#_H <31>
FBC_RST#_L <30>
FBC_RST#_H <31>
FBC_CKE_H <31>
FBC_CAS#_H <31>
FB_CLAMP <23,54>
FBVDDQ_PWR_EN <61>
DGPU_PWROK<19,54,62,63>
DGPU_GC6_EN<14,54> S_GC6_EN <32,54>
+1.5VS_VGA
+1.05VS_VGA +FB_PLLAVDD
+FB_PLLAVDD
+FB_PLLAVDD
+FB_PLLAVDD
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_MEM Interface
Custom
27 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_MEM Interface
Custom
27 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_MEM Interface
Custom
27 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CV106 0.1U_0402_10V7KCV106 0.1U_0402_10V7K
1 2
RV74
10K_0402_5%
RV74
10K_0402_5%
12
CV39
22U_0805_6.3V6M
CV39
22U_0805_6.3V6M
1
2
CV110
1U_0402_6.3V6K
CV110
1U_0402_6.3V6K
1
2
RV29
200K_0402_5%
GC6@
RV29
200K_0402_5%
GC6@
12
RV18 0_0402_5%
GC6@
RV18 0_0402_5%
GC6@
1 2
LV3
FBMA-L11-160808300LMA25T_2P
LV3
FBMA-L11-160808300LMA25T_2P
1 2
CV108
0.1U_0402_10V7K
CV108
0.1U_0402_10V7K
1
2
RV172
0_0402_5%
@RV172
0_0402_5%
@
1 2
RV73
10K_0402_5%
RV73
10K_0402_5%
12
RV6160.4_0402_1%
@
RV6160.4_0402_1%
@
1 2
RV222
10K_0402_5%
RV222
10K_0402_5%
12
MEMORY INTERFACE B
Part 3 of 7
UV1C
N14P-GT-A2_FCBGA908
MEMORY INTERFACE B
Part 3 of 7
UV1C
N14P-GT-A2_FCBGA908
FBB_D0
G9
FBB_D1
E9
FBB_D2
G8
FBB_D3
F9
FBB_D4
F11
FBB_D5
G11
FBB_D6
F12
FBB_D7
G12
FBB_D8
G6
FBB_D9
F5
FBB_D10
E6
FBB_D11
F6
FBB_D12
F4
FBB_D13
G4
FBB_D14
E2
FBB_D15
F3
FBB_D16
C2
FBB_D17
D4
FBB_D18
D3
FBB_D19
C1
FBB_D20
B3
FBB_D21
C4
FBB_D22
B5
FBB_D23
C5
FBB_D24
A11
FBB_D25
C11
FBB_D26
D11
FBB_D27
B11
FBB_D28
D8
FBB_D29
A8
FBB_D30
C8
FBB_D31
B8
FBB_D32
F24
FBB_D33
G23
FBB_D34
E24
FBB_D35
G24
FBB_D36
D21
FBB_D37
E21
FBB_D38
G21
FBB_D39
F21
FBB_D40
G27
FBB_D41
D27
FBB_D42
G26
FBB_D43
E27
FBB_D44
E29
FBB_D45
F29
FBB_D46
E30
FBB_D47
D30
FBB_D48
A32
FBB_D49
C31
FBB_D50
C32
FBB_D51
B32
FBB_D52
D29
FBB_D53
A29
FBB_D54
C29
FBB_D55
B29
FBB_D56
B21
FBB_D57
C23
FBB_D58
A21
FBB_D59
C21
FBB_D60
B24
FBB_D61
C24
FBB_D62
B26
FBB_D63
C26
FBB_DQM0
E11
FBB_DQM1
E3
FBB_DQM2
A3
FBB_DQM3
C9
FBB_DQM4
F23
FBB_DQM5
F27
FBB_DQM6
C30
FBB_DQM7
A24
FBB_DQS_WP0
D10
FBB_DQS_WP1
D5
FBB_DQS_WP2
C3
FBB_DQS_WP3
B9
FBB_DQS_WP4
E23
FBB_DQS_WP5
E28
FBB_DQS_WP6
B30
FBB_DQS_WP7
A23
FBB_DQS_RN0
D9
FBB_DQS_RN1
E4
FBB_DQS_RN2
B2
FBB_DQS_RN3
A9
FBB_DQS_RN4
D22
FBB_DQS_RN5
D28
FBB_DQS_RN6
A30
FBB_DQS_RN7
B23
FBB_CMD0 D13
FBB_CMD1 E14
FBB_CMD2 F14
FBB_CMD3 A12
FBB_CMD4 B12
FBB_CMD5 C14
FBB_CMD6 B14
FBB_CMD7 G15
FBB_CMD8 F15
FBB_CMD9 E15
FBB_CMD10 D15
FBB_CMD11 A14
FBB_CMD12 D14
FBB_CMD13 A15
FBB_CMD14 B15
FBB_CMD15 C17
FBB_CMD16 D18
FBB_CMD17 E18
FBB_CMD18 F18
FBB_CMD19 A20
FBB_CMD20 B20
FBB_CMD21 C18
FBB_CMD22 B18
FBB_CMD23 G18
FBB_CMD24 G17
FBB_CMD25 F17
FBB_CMD26 D16
FBB_CMD27 A18
FBB_CMD28 D17
FBB_CMD29 A17
FBB_CMD30 B17
FBB_CMD31 E17
FBB_CMD_RFU0 C12
FBB_CMD_RFU1 C20
FBB_DEBUG0 G14
FBB_DEBUG1 G20
FBB_CLK0 D12
FBB_CLK0_N E12
FBB_CLK1 E20
FBB_CLK1_N F20
FBB_WCK01 F8
FBB_WCK01_N E8
FBB_WCK23 A5
FBB_WCK23_N A6
FBB_WCK45 D24
FBB_WCK45_N D25
FBB_WCK67 B27
FBB_WCK67_N C27
FBB_WCKB01 D6
FBB_WCKB01_N D7
FBB_WCKB23 C6
FBB_WCKB23_N B6
FBB_WCKB45 F26
FBB_WCKB45_N E26
FBB_WCKB67 A26
FBB_WCKB67_N A27
FBB_PLL_AVDD H17
RV210
10K_0402_5%
RV210
10K_0402_5%
12
RV156
0_0402_5%
NOGC6@
RV156
0_0402_5%
NOGC6@
1 2
RV5960.4_0402_1%
@
RV5960.4_0402_1%
@
1 2
RV71
10K_0402_5%
RV71
10K_0402_5%
12
DV3
DAN202UT106_SC70-3
GC6@
DV3
DAN202UT106_SC70-3
GC6@
2
3
1
RV66 10K_0402_5%NOGC6@RV66 10K_0402_5%NOGC6@
12
G
D
S
QV4
2N7002_SOT23
@
G
D
S
QV4
2N7002_SOT23
@
2
13
RV209
10K_0402_5%
RV209
10K_0402_5%
12
RV169
0_0402_5%
@
RV169
0_0402_5%
@
1 2
RV72
10K_0402_5%
RV72
10K_0402_5%
12
MEMORY INTERFACE
A
Part 2 of 7
UV1B
N14P-GT-A2_FCBGA908
MEMORY INTERFACE
A
Part 2 of 7
UV1B
N14P-GT-A2_FCBGA908
FBA_D0
L28
FBA_D1
M29
FBA_D2
L29
FBA_D3
M28
FBA_D4
N31
FBA_D5
P29
FBA_D6
R29
FBA_D7
P28
FBA_D8
J28
FBA_D9
H29
FBA_D10
J29
FBA_D11
H28
FBA_D12
G29
FBA_D13
E31
FBA_D14
E32
FBA_D15
F30
FBA_D16
C34
FBA_D17
D32
FBA_D18
B33
FBA_D19
C33
FBA_D20
F33
FBA_D21
F32
FBA_D22
H33
FBA_D23
H32
FBA_D24
P34
FBA_D25
P32
FBA_D26
P31
FBA_D27
P33
FBA_D28
L31
FBA_D29
L34
FBA_D30
L32
FBA_D31
L33
FBA_D32
AG28
FBA_D33
AF29
FBA_D34
AG29
FBA_D35
AF28
FBA_D36
AD30
FBA_D37
AD29
FBA_D38
AC29
FBA_D39
AD28
FBA_D40
AJ29
FBA_D41
AK29
FBA_D42
AJ30
FBA_D43
AK28
FBA_D44
AM29
FBA_D45
AM31
FBA_D46
AN29
FBA_D47
AM30
FBA_D48
AN31
FBA_D49
AN32
FBA_D50
AP30
FBA_D51
AP32
FBA_D52
AM33
FBA_D53
AL31
FBA_D54
AK33
FBA_D55
AK32
FBA_D56
AD34
FBA_D57
AD32
FBA_D58
AC30
FBA_D59
AD33
FBA_D60
AF31
FBA_D61
AG34
FBA_D62
AG32
FBA_D63
AG33
FBA_CMD3 R34
FBA_CMD8 V28
FBA_CMD2 U29
FBA_CMD21 AA32
FBA_CMD24 Y29
FBA_CMD23 Y28
FBA_CMD26 Y30
FBA_CMD7 U28
FBA_CMD15 Y32
FBA_CMD13 V34
FBA_CMD4 R33
FBA_CMD18 AA28
FBA_CMD29 Y34
FBA_CMD27 AA34
FBA_CMD6 U33
FBA_CMD17 AA29
FBA_CMD19 AC34
FBA_CMD22 AA33
FBA_CMD12 U31
FBA_CMD28 Y31
FBA_CMD10 V30
FBA_CMD25 W 31
FBA_CMD9 V29
FBA_CMD1 T31
FBA_CMD11 U34
FBA_CMD0 U30
FBA_CMD5 U32
FBA_DQM0
P30
FBA_DQM1
F31
FBA_DQM2
F34
FBA_DQM3
M32
FBA_DQM4
AD31
FBA_DQM5
AL29
FBA_DQM6
AM32
FBA_DQM7
AF34
FBA_DQS_RN0
M30
FBA_DQS_RN1
H30
FBA_DQS_RN2
E34
FBA_DQS_RN3
M34
FBA_DQS_RN4
AF30
FBA_DQS_RN5
AK31
FBA_DQS_RN6
AM34
FBA_DQS_RN7
AF32
FBA_DQS_WP0
M31
FBA_DQS_WP1
G31
FBA_DQS_WP2
E33
FBA_DQS_WP3
M33
FBA_DQS_WP4
AE31
FBA_DQS_WP5
AK30
FBA_DQS_WP6
AN33
FBA_DQS_WP7
AF33
FBA_CMD16 AA31
FBA_CMD20 AC33
FBA_CMD14 V33
FBA_CMD30 Y33
FBA_CMD31 V31
FBA_CLK0_N R31
FBA_WCK45_N AG31
FBA_CLK0 R30
FBA_WCK67 AJ34
FBA_WCK23 H34
FBA_WCK01_N L30
FBA_WCK01 K31
FBA_WCK67_N AK34
FBA_WCK23_N J34
FBA_CLK1_N AC31
FBA_WCK45 AG30
FBA_CLK1 AB31
FBA_WCKB01 J30
FBA_WCKB01_N J31
FBA_WCKB23 J32
FBA_WCKB23_N J33
FBA_WCKB45 AH31
FBA_WCKB45_N AJ31
FBA_WCKB67 AJ32
FBA_WCKB67_N AJ33
FBA_PLL_AVDD U27
FBA_CMD_RFU0 R32
FBA_CMD_RFU1 AC32
FB_VREF H26
FB_CLAMP E1
FB_DLL_AVDD K27
FBA_DEBUG0 R28
FBA_DEBUG1 AC28
RV5860.4_0402_1%
@
RV5860.4_0402_1%
@
1 2
RV6810K_0402_5% @RV6810K_0402_5% @
12
RV221
10K_0402_5%
RV221
10K_0402_5%
12
RV6060.4_0402_1%
@
RV6060.4_0402_1%
@
1 2
CV107
0.1U_0402_10V7K
CV107
0.1U_0402_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Memory - Lower 32 bits
UV3 SIDE
DATA Bus
GDDR5
Mode H - Mirror Mode Mapping
0..31 32..63
Address
FBx_CMD0
FBx_CMD1
FBx_CMD4
FBx_CMD3
FBx_CMD2
FBx_CMD6
FBx_CMD5
FBx_CMD10
FBx_CMD9
FBx_CMD8
FBx_CMD7
FBx_CMD14
FBx_CMD13
FBx_CMD12
FBx_CMD11
FBx_CMD19
FBx_CMD18
FBx_CMD17
FBx_CMD16
FBx_CMD15
FBx_CMD22
FBx_CMD21
FBx_CMD20
FBx_CMD27
FBx_CMD26
FBx_CMD25
FBx_CMD24
FBx_CMD23
FBx_CMD28
FBx_CMD29
FBx_CMD30
ABI#
A4_BA2
A0_A10
A7_A8
A5_BA1
RST#
A6_A11
A2_BA0
CS#
A1_A9
A3_BA3
A12_RFU
CKE#
A1_A9
ABI#
CS#
CAS#
WE#
A5_BA1
A6_A11
CAS#
A4_BA2
CKE#
WE#
A12_RFU
A7_A8
A0_A10
A2_BA0
RAS#
RAS#
A3_BA3
Follow DG
BYTE3
BYTE1
BYTE2
BYTE0
16 mil
UV4 SIDE
RST#
FBx_CMD31
FBA_CLK0
FBA_CLK0#
FBA_MA6_MA11_L
FBA_MA2_BA0_L
FBA_MA1_MA9_L
FBA_RAS#_L
FBA_WE#_L
FBA_MA0_MA10_L
FBA_MA12_RFU_L
FBA_MA5_BA1_L
FBA_MA7_MA8_L
FBA_MA3_BA3_L
FBA_RST#_L
+FBA_VREFC0
FBA_CAS#_L
FBA_CS#_L
FBA_MA4_BA2_L
FBA_ABI#_L
FBA_CKE_L
FBA_DBI2#
FBA_DBI0#
FBA_EDC0
FBA_EDC2
+FBA_VREFD_L
+FBA_VREFD_L
+FBA_VREFC0
FBA_CLK0
FBA_CLK0#
FBA_ABI#_L
FBA_CKE_L
+FBA_VREFD_L
+FBA_VREFC0
FBA_W CK0
FBA_W CK0_N
FBA_W CK1
FBA_W CK1_N
FBA_CLK0
FBA_CLK0#
FBA_EDC3
FBA_EDC1
FBA_DBI1#
FBA_DBI3#
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA3_BA3_L
FBA_MA4_BA2_L
FBA_MA6_MA11_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA12_RFU_L
FBA_MA7_MA8_L
FBA_CS#_L
FBA_WE#_L
FBA_CAS#_L
FBA_RAS#_L
FBA_W CK1
FBA_W CK1_N
FBA_W CK0
FBA_W CK0_N
FBA_D24
FBA_D30
FBA_D26
FBA_D25
FBA_D27
FBA_D28
FBA_D29
FBA_D31
FBA_D11
FBA_D14
FBA_D15
FBA_D13
FBA_D10
FBA_D8
FBA_D12
FBA_D9
FBA_D16
FBA_D18
FBA_D22
FBA_D21
FBA_D23
FBA_D17
FBA_D20
FBA_D19
FBA_D7
FBA_D1
FBA_D5
FBA_D3
FBA_D2
FBA_D4
FBA_D6
FBA_D0
FBA_RST#_L
FBA_CLK0#<27>
FBA_CLK0<27>
FBA_MA5_BA1_L<27>
FBA_W E#_L<27>
FBA_RAS#_L<27>
FBA_MA7_MA8_L<27>
FBA_MA6_MA11_L<27>
FBA_MA12_RFU_L<27>
FBA_MA1_MA9_L<27>
FBA_MA0_MA10_L<27>
FBA_MA3_BA3_L<27>
FBA_MA2_BA0_L<27>
FBA_RST#_L<27>
FBA_CAS#_L<27>
FBA_MA4_BA2_L<27>
FBA_CS#_L<27>
FBA_CKE_L<27>
FBA_ABI#_L<27>
FBA_D[0..31]<27>
FBA_EDC[3..0]<27>
FBA_DBI0#<27>
FBA_DBI2#<27> FBA_DBI1#<27>
FBA_DBI3#<27>
MEM_VREF<23,29,30,31>
FBA_W CK0_N<27>
FBA_W CK1_N<27>
FBA_W CK0<27>
FBA_W CK1<27>
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA +1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA+1.5VS_VGA
+1.5VS_VGA
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Lower
Custom
28 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Lower
Custom
28 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Lower
Custom
28 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV4
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV4
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
CV76
1U_0603_25V6
CV76
1U_0603_25V6
1
2
CV174
10U_0603_6.3V6M
CV174
10U_0603_6.3V6M
1
2
RV120
121_0402_1%
RV120
121_0402_1%
12
RV129
549_0402_1%
RV129
549_0402_1%
12
CV129
0.1U_0402_10V7K
CV129
0.1U_0402_10V7K
1
2
CV80
1U_0603_25V6
CV80
1U_0603_25V6
1
2
CV134
0.1U_0402_10V7K
CV134
0.1U_0402_10V7K
1
2
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV3
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV3
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
RV127
549_0402_1%
RV127
549_0402_1%
12
CV71
1U_0603_25V6
CV71
1U_0603_25V6
1
2
CV78
1U_0603_25V6
CV78
1U_0603_25V6
1
2
RV213
931_0402_1%
RV213
931_0402_1%
1 2
RV115
1K_0402_1%
RV115
1K_0402_1%
12
RV21 40.2_0402_1%RV21 40.2_0402_1%
1 2
RV28 40.2_0402_1%RV28 40.2_0402_1%
1 2
CV136
0.1U_0402_10V7K
CV136
0.1U_0402_10V7K
1
2
CV42
820P_0402_25V7
CV42
820P_0402_25V7
1
2
CV132
0.1U_0402_10V7K
CV132
0.1U_0402_10V7K
1
2
RV130
1.33K_0402_1%
RV130
1.33K_0402_1%
12
RV123
160_0402_1%
@
RV123
160_0402_1%
@
1 2
CV69
1U_0603_25V6
CV69
1U_0603_25V6
1
2
CV155
0.01U_0402_25V7K
CV155
0.01U_0402_25V7K
1
2
RV117
1K_0402_1%
RV117
1K_0402_1%
12
CV166
10U_0603_6.3V6M
CV166
10U_0603_6.3V6M
1
2
RV118
1K_0402_1%
RV118
1K_0402_1%
12
CV77
1U_0603_25V6
CV77
1U_0603_25V6
1
2
RV116
1K_0402_1%
RV116
1K_0402_1%
12
RV212
931_0402_1%
RV212
931_0402_1%
1 2
CV58
820P_0402_25V7
CV58
820P_0402_25V7
1
2
RV128
1.33K_0402_1%
RV128
1.33K_0402_1%
12
CV135
0.1U_0402_10V7K
CV135
0.1U_0402_10V7K
1
2
CV133
0.1U_0402_10V7K
CV133
0.1U_0402_10V7K
1
2
G
D
S
QV9
2N7002W -T/R7_SOT323-3
G
D
S
QV9
2N7002W -T/R7_SOT323-3
2
13
RV119
121_0402_1%
RV119
121_0402_1%
12
CV79
1U_0603_25V6
CV79
1U_0603_25V6
1
2
CV68
1U_0603_25V6
CV68
1U_0603_25V6
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Memory - Upper 32 bits
Follow DG
BYTE5
BYTE7
BYTE6
BYTE4
16 mil
UV5 SIDE
UV6 SIDE
FBx_CMD31
RST#
DATA Bus
0..31
GDDR5
Mode H - Mirror Mode Mapping
32..63
Address
FBx_CMD0
FBx_CMD1
FBx_CMD4
FBx_CMD3
FBx_CMD2
FBx_CMD6
FBx_CMD5
FBx_CMD10
FBx_CMD9
FBx_CMD8
FBx_CMD7
FBx_CMD14
FBx_CMD13
FBx_CMD12
FBx_CMD11
FBx_CMD19
FBx_CMD18
FBx_CMD17
FBx_CMD16
FBx_CMD15
FBx_CMD22
FBx_CMD21
FBx_CMD20
FBx_CMD27
FBx_CMD26
FBx_CMD25
FBx_CMD24
FBx_CMD23
FBx_CMD28
FBx_CMD29
FBx_CMD30
ABI#
A4_BA2
A0_A10
A7_A8
A5_BA1
RST#
A6_A11
A2_BA0
CS#
A1_A9
A3_BA3
A12_RFU
CKE#
A1_A9
ABI#
CS#
CAS#
WE#
A5_BA1
A6_A11
CAS#
A4_BA2
CKE#
WE#
A12_RFU
A7_A8
A0_A10
A2_BA0
RAS#
RAS#
A3_BA3
FBA_CLK1
FBA_CLK1#
FBA_RST#_H
FBA_ABI#_H
FBA_CKE_H
+FBA_VREFD_H
+FBA_VREFC1
FBA_CLK1
FBA_CLK1#
FBA_MA6_MA11_H
FBA_MA2_BA0_H
FBA_MA1_MA9_H
FBA_RAS#_H
FBA_WE#_H
FBA_MA0_MA10_H
FBA_MA12_RFU_H
FBA_MA5_BA1_H
FBA_MA7_MA8_H
FBA_MA3_BA3_H
+FBA_VREFC1
FBA_CAS#_H
FBA_CS#_H
FBA_MA4_BA2_H
FBA_ABI#_H
FBA_CKE_H
FBA_DBI6#
FBA_DBI4#
FBA_EDC4
FBA_EDC6
+FBA_VREFD_H
+FBA_VREFD_H
+FBA_VREFC1
FBA_CLK1
FBA_CLK1#
FBA_W CK2
FBA_W CK2_N
FBA_W CK3
FBA_W CK3_N
FBA_EDC5
FBA_EDC7
FBA_DBI5#
FBA_DBI7#
FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA3_BA3_H
FBA_MA4_BA2_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H
FBA_RAS#_H
FBA_WE#_H
FBA_CAS#_H
FBA_CS#_H
FBA_W CK3
FBA_W CK3_N
FBA_W CK2
FBA_W CK2_N
FBA_D40
FBA_D47
FBA_D46
FBA_D43
FBA_D45
FBA_D44
FBA_D42
FBA_D41
FBA_D59
FBA_D58
FBA_D60
FBA_D56
FBA_D61
FBA_D57
FBA_D62
FBA_D63
FBA_D50
FBA_D55
FBA_D53
FBA_D52
FBA_D49
FBA_D54
FBA_D48
FBA_D51
FBA_D33
FBA_D36
FBA_D32
FBA_D38
FBA_D34
FBA_D35
FBA_D37
FBA_D39
FBA_RST#_H
FBA_CLK1#<27>
FBA_CLK1<27>
FBA_MA5_BA1_H<27>
FBA_W E#_H<27>
FBA_RAS#_H<27>
FBA_MA7_MA8_H<27>
FBA_MA6_MA11_H<27>
FBA_MA12_RFU_H<27>
FBA_MA1_MA9_H<27>
FBA_MA0_MA10_H<27>
FBA_MA3_BA3_H<27>
FBA_MA2_BA0_H<27>
FBA_CAS#_H<27>
FBA_MA4_BA2_H<27>
FBA_CS#_H<27>
FBA_CKE_H<27>
FBA_ABI#_H<27>
FBA_EDC[7..4]<27>
FBA_D[63..32]<27>
FBA_DBI4#<27>
FBA_DBI6#<27>
FBA_DBI5#<27>
FBA_DBI7#<27>
MEM_VREF<23,28,30,31>
FBA_W CK2_N<27>
FBA_W CK3_N<27>
FBA_W CK2<27>
FBA_W CK3<27>
FBA_RST#_H<27>
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Upper
Custom
29 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Upper
Custom
29 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Num ber Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_A Upper
Custom
29 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RV134
1K_0402_1%
RV134
1K_0402_1%
12
CV60
820P_0402_25V7
CV60
820P_0402_25V7
1
2
CV83
1U_0603_25V6
CV83
1U_0603_25V6
1
2
RV31 40.2_0402_1%RV31 40.2_0402_1%
1 2
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV6
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV6
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
RV146
1.33K_0402_1%
RV146
1.33K_0402_1%
12
G
D
S
QV11
2N7002W -T/R7_SOT323-3
G
D
S
QV11
2N7002W -T/R7_SOT323-3
2
13
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV5
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV5
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
CV85
1U_0603_25V6
CV85
1U_0603_25V6
1
2
CV179
10U_0603_6.3V6M
CV179
10U_0603_6.3V6M
1
2
RV36 40.2_0402_1%RV36 40.2_0402_1%
1 2
CV137
0.1U_0402_10V7K
CV137
0.1U_0402_10V7K
1
2
RV214
931_0402_1%
RV214
931_0402_1%
1 2
CV145
0.1U_0402_10V7K
CV145
0.1U_0402_10V7K
1
2
CV81
1U_0603_25V6
CV81
1U_0603_25V6
1
2
RV143
549_0402_1%
RV143
549_0402_1%
12
RV135
121_0402_1%
RV135
121_0402_1%
12
RV215
931_0402_1%
RV215
931_0402_1%
1 2
RV139
160_0402_1%
@
RV139
160_0402_1%
@
1 2
CV86
1U_0603_25V6
CV86
1U_0603_25V6
1
2
CV142
0.1U_0402_10V7K
CV142
0.1U_0402_10V7K
1
2
CV187
10U_0603_6.3V6M
CV187
10U_0603_6.3V6M
1
2
CV59
820P_0402_25V7
CV59
820P_0402_25V7
1
2
RV144
1.33K_0402_1%
RV144
1.33K_0402_1%
12
CV88
1U_0603_25V6
CV88
1U_0603_25V6
1
2
CV84
1U_0603_25V6
CV84
1U_0603_25V6
1
2
RV133
1K_0402_1%
RV133
1K_0402_1%
12
CV144
0.1U_0402_10V7K
CV144
0.1U_0402_10V7K
1
2
CV82
1U_0603_25V6
CV82
1U_0603_25V6
1
2
RV132
1K_0402_1%
RV132
1K_0402_1%
12
CV87
1U_0603_25V6
CV87
1U_0603_25V6
1
2
RV136
121_0402_1%
RV136
121_0402_1%
12
CV175
0.01U_0402_25V7K
CV175
0.01U_0402_25V7K
1
2
CV143
0.1U_0402_10V7K
CV143
0.1U_0402_10V7K
1
2
RV131
1K_0402_1%
RV131
1K_0402_1%
12
RV145
549_0402_1%
RV145
549_0402_1%
12
CV138
0.1U_0402_10V7K
CV138
0.1U_0402_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Memory Partition C - Lower 32 bits
Follow DG
BYTE2
BYTE0 BYTE3
BYTE1
UV8 SIDE
UV7 SIDE
FBx_CMD31
RST#
DATA Bus
0..31
GDDR5
Mode H - Mirror Mode Mapping
32..63
Address
FBx_CMD0
FBx_CMD1
FBx_CMD4
FBx_CMD3
FBx_CMD2
FBx_CMD6
FBx_CMD5
FBx_CMD10
FBx_CMD9
FBx_CMD8
FBx_CMD7
FBx_CMD14
FBx_CMD13
FBx_CMD12
FBx_CMD11
FBx_CMD19
FBx_CMD18
FBx_CMD17
FBx_CMD16
FBx_CMD15
FBx_CMD22
FBx_CMD21
FBx_CMD20
FBx_CMD27
FBx_CMD26
FBx_CMD25
FBx_CMD24
FBx_CMD23
FBx_CMD28
FBx_CMD29
FBx_CMD30
ABI#
A4_BA2
A0_A10
A7_A8
A5_BA1
RST#
A6_A11
A2_BA0
CS#
A1_A9
A3_BA3
A12_RFU
CKE#
A1_A9
ABI#
CS#
CAS#
WE#
A5_BA1
A6_A11
CAS#
A4_BA2
CKE#
WE#
A12_RFU
A7_A8
A0_A10
A2_BA0
RAS#
RAS#
A3_BA3
FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
+FBC_VREFD_L
+FBC_VREFC0
FBC_D16
FBC_D18
FBC_D22
FBC_D21
FBC_D23
FBC_D17
FBC_D20
FBC_D19
FBC_CLK0
FBC_CLK0#
FBC_MA6_MA11_L
FBC_MA2_BA0_L
FBC_MA1_MA9_L
FBC_RAS#_L
FBC_WE#_L
FBC_MA0_MA10_L
FBC_MA12_RFU_L
FBC_MA5_BA1_L
FBC_MA7_MA8_L
FBC_MA3_BA3_L
FBC_RST#_L
+FBC_VREFC0
FBC_CAS#_L
FBC_CS#_L
FBC_MA4_BA2_L
FBC_ABI#_L
FBC_CKE_L
FBC_D7
FBC_D1
FBC_D5
FBC_D3
FBC_D2
FBC_D4
FBC_D6
FBC_D0
FBC_DBI2#
FBC_DBI0#
FBC_EDC0
FBC_EDC2
+FBC_VREFD_L
+FBC_VREFD_L
+FBC_VREFC0
FBC_CLK0
FBC_CLK0#
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA3_BA3_L
FBC_MA4_BA2_L
FBC_DBI3#
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
FBC_EDC1
FBC_EDC3
FBC_MA6_MA11_L
FBC_MA1_MA9_L
FBC_MA0_MA10_L
FBC_MA12_RFU_L
FBC_MA7_MA8_L
FBC_DBI1#
FBC_CS#_L
FBC_ABI#_L
FBC_WE#_L
FBC_WCK1
FBC_WCK1_N
FBC_CAS#_L
FBC_RAS#_L
FBC_WCK0
FBC_WCK0_N
FBC_D24
FBC_D30
FBC_D26
FBC_D25
FBC_D27
FBC_D28
FBC_D29
FBC_D31
FBC_D11
FBC_D14
FBC_D15
FBC_D13
FBC_D10
FBC_D8
FBC_D12
FBC_D9
FBC_RST#_L
FBC_CLK0#<27>
FBC_CLK0<27>
FBC_MA5_BA1_L<27>
FBC_WE#_L<27>
FBC_RAS#_L<27>
FBC_MA7_MA8_L<27>
FBC_MA6_MA11_L<27>
FBC_MA12_RFU_L<27>
FBC_MA1_MA9_L<27>
FBC_MA0_MA10_L<27>
FBC_MA3_BA3_L<27>
FBC_MA2_BA0_L<27>
FBC_RST#_L<27>
FBC_CAS#_L<27>
FBC_MA4_BA2_L<27>
FBC_CS#_L<27>
FBC_CKE_L<27>
FBC_ABI#_L<27>
FBC_EDC[3..0]<27>
FBC_D[0..31]<27>
FBC_DBI0#<27>
FBC_DBI2#<27>
MEM_VREF<23,28,29,31>
FBC_WCK0_N<27>
FBC_WCK1_N<27>
FBC_WCK0<27>
FBC_WCK1<27>
FBC_DBI3#<27>
FBC_DBI1#<27>
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Lower
Custom
30 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Lower
Custom
30 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Lower
Custom
30 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CV93
1U_0603_25V6
CV93
1U_0603_25V6
1
2
RV151
121_0402_1%
RV151
121_0402_1%
12
RV161
549_0402_1%
RV161
549_0402_1%
12
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV8
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV8
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
CV163
0.1U_0402_10V7K
CV163
0.1U_0402_10V7K
1
2
RV162
1.33K_0402_1%
RV162
1.33K_0402_1%
12
RV39 40.2_0402_1%RV39 40.2_0402_1%
1 2
RV159
549_0402_1%
RV159
549_0402_1%
12
CV94
1U_0603_25V6
CV94
1U_0603_25V6
1
2
CV157
0.1U_0402_10V7K
CV157
0.1U_0402_10V7K
1
2
CV92
1U_0603_25V6
CV92
1U_0603_25V6
1
2
CV61
820P_0402_25V7
CV61
820P_0402_25V7
1
2
CV89
1U_0603_25V6
CV89
1U_0603_25V6
1
2
RV37 40.2_0402_1%RV37 40.2_0402_1%
1 2
CV159
0.1U_0402_10V7K
CV159
0.1U_0402_10V7K
1
2
RV216
931_0402_1%
RV216
931_0402_1%
1 2
RV155
160_0402_1%
@
RV155
160_0402_1%
@
1 2
CV91
1U_0603_25V6
CV91
1U_0603_25V6
1
2
RV217
931_0402_1%
RV217
931_0402_1%
1 2
CV62
820P_0402_25V7
CV62
820P_0402_25V7
1
2
RV160
1.33K_0402_1%
RV160
1.33K_0402_1%
12
RV150
1K_0402_1%
RV150
1K_0402_1%
12
CV90
1U_0603_25V6
CV90
1U_0603_25V6
1
2
CV161
0.1U_0402_10V7K
CV161
0.1U_0402_10V7K
1
2
CV162
0.1U_0402_10V7K
CV162
0.1U_0402_10V7K
1
2
RV147
1K_0402_1%
RV147
1K_0402_1%
12
CV199
10U_0603_6.3V6M
CV199
10U_0603_6.3V6M
1
2
CV95
1U_0603_25V6
CV95
1U_0603_25V6
1
2
CV195
0.01U_0402_25V7K
CV195
0.01U_0402_25V7K
1
2
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV7
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV7
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
RV149
1K_0402_1%
RV149
1K_0402_1%
12
CV207
10U_0603_6.3V6M
CV207
10U_0603_6.3V6M
1
2
RV148
1K_0402_1%
RV148
1K_0402_1%
12
RV152
121_0402_1%
RV152
121_0402_1%
12
G
D
S
QV13
2N7002W-T/R7_SOT323-3
G
D
S
QV13
2N7002W-T/R7_SOT323-3
2
13
CV96
1U_0603_25V6
CV96
1U_0603_25V6
1
2
CV160
0.1U_0402_10V7K
CV160
0.1U_0402_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Memory Partition C - Upper 32 bits
Follow DG
BYTE6
BYTE4
BYTE7
BYTE5
UV10 SIDE
UV9 SIDE
FBx_CMD31
RST#
DATA Bus
0..31
GDDR5
Mode H - Mirror Mode Mapping
32..63
Address
FBx_CMD0
FBx_CMD1
FBx_CMD4
FBx_CMD3
FBx_CMD2
FBx_CMD6
FBx_CMD5
FBx_CMD10
FBx_CMD9
FBx_CMD8
FBx_CMD7
FBx_CMD14
FBx_CMD13
FBx_CMD12
FBx_CMD11
FBx_CMD19
FBx_CMD18
FBx_CMD17
FBx_CMD16
FBx_CMD15
FBx_CMD22
FBx_CMD21
FBx_CMD20
FBx_CMD27
FBx_CMD26
FBx_CMD25
FBx_CMD24
FBx_CMD23
FBx_CMD28
FBx_CMD29
FBx_CMD30
ABI#
A4_BA2
A0_A10
A7_A8
A5_BA1
RST#
A6_A11
A2_BA0
CS#
A1_A9
A3_BA3
A12_RFU
CKE#
A1_A9
ABI#
CS#
CAS#
WE#
A5_BA1
A6_A11
CAS#
A4_BA2
CKE#
WE#
A12_RFU
A7_A8
A0_A10
A2_BA0
RAS#
RAS#
A3_BA3
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N
+FBC_VREFD_H
+FBC_VREFC1
FBC_CLK1
FBC_CLK1#
FBC_MA6_MA11_H
FBC_MA2_BA0_H
FBC_MA1_MA9_H
FBC_RAS#_H
FBC_WE#_H
FBC_MA0_MA10_H
FBC_MA12_RFU_H
FBC_D50
FBC_D55
FBC_D53
FBC_D52
FBC_MA5_BA1_H
FBC_MA7_MA8_H
FBC_D49
FBC_D54
FBC_D48
FBC_D51
FBC_MA3_BA3_H
FBC_RST#_H
+FBC_VREFC1
FBC_CAS#_H
FBC_CS#_H
FBC_MA4_BA2_H
FBC_ABI#_H
FBC_CKE_H
FBC_DBI6#
FBC_DBI4#
FBC_EDC4
FBC_EDC6
+FBC_VREFD_H
+FBC_VREFD_H
+FBC_VREFC1
FBC_CLK1
FBC_CLK1#
FBC_D33
FBC_D36
FBC_D32
FBC_D38
FBC_D34
FBC_D35
FBC_D37
FBC_D39
FBC_CLK1
FBC_CLK1#
FBC_CKE_H
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA3_BA3_H
FBC_MA4_BA2_H
FBC_EDC5
FBC_MA12_RFU_H
FBC_MA7_MA8_H
FBC_DBI5#
FBC_EDC7
FBC_MA1_MA9_H
FBC_DBI7#
FBC_ABI#_H
FBC_WCK3
FBC_WCK3_N
FBC_WCK2
FBC_WCK2_N
FBC_RAS#_H
FBC_WE#_H
FBC_CAS#_H
FBC_CS#_H
FBC_D59
FBC_D58
FBC_D60
FBC_D56
FBC_D61
FBC_D57
FBC_D62
FBC_D63
FBC_D40
FBC_D47
FBC_D46
FBC_D43
FBC_D45
FBC_D44
FBC_D42
FBC_D41
FBC_RST#_H
FBC_CLK1#<27>
FBC_CLK1<27>
FBC_MA5_BA1_H<27>
FBC_WE#_H<27>
FBC_RAS#_H<27>
FBC_MA7_MA8_H<27>
FBC_MA6_MA11_H<27>
FBC_MA12_RFU_H<27>
FBC_MA1_MA9_H<27>
FBC_MA0_MA10_H<27>
FBC_MA3_BA3_H<27>
FBC_MA2_BA0_H<27>
FBC_RST#_H<27>
FBC_CAS#_H<27>
FBC_MA4_BA2_H<27>
FBC_CS#_H<27>
FBC_CKE_H<27>
FBC_ABI#_H<27>
FBC_EDC[7..4]<27>
FBC_DBI4#<27>
FBC_DBI6#<27>
FBC_DBI5#<27>
FBC_DBI7#<27>
FBC_D[63..32]<27>
MEM_VREF<23,28,29,30>
FBC_WCK2_N<27>
FBC_WCK3_N<27>
FBC_WCK2<27>
FBC_WCK3<27>
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Upper
Custom
31 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Upper
Custom
31 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
N13P_GDDR5_C Upper
Custom
31 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RV168
121_0402_1%
RV168
121_0402_1%
12
RV163
1K_0402_1%
RV163
1K_0402_1%
12
CV165
0.1U_0402_10V7K
CV165
0.1U_0402_10V7K
1
2
CV215
0.01U_0402_25V7K
CV215
0.01U_0402_25V7K
1
2
RV48 40.2_0402_1%RV48 40.2_0402_1%
1 2
RV178
1.33K_0402_1%
RV178
1.33K_0402_1%
12
CV101
1U_0603_25V6
CV101
1U_0603_25V6
1
2
CV167
0.1U_0402_10V7K
CV167
0.1U_0402_10V7K
1
2
CV64
820P_0402_25V7
CV64
820P_0402_25V7
1
2
RV171
160_0402_1%
@
RV171
160_0402_1%
@
1 2
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV10
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV10
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
CV227
10U_0603_6.3V6M
CV227
10U_0603_6.3V6M
1
2
RV177
549_0402_1%
RV177
549_0402_1%
12
RV41 40.2_0402_1%RV41 40.2_0402_1%
1 2
CV164
0.1U_0402_10V7K
CV164
0.1U_0402_10V7K
1
2
CV245
10U_0603_6.3V6M
CV245
10U_0603_6.3V6M
1
2
RV167
121_0402_1%
RV167
121_0402_1%
12
CV104
1U_0603_25V6
CV104
1U_0603_25V6
1
2
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV9
H5GQ1H24AFR-T2L_BGA170
X76@
170-BALL
SGRAM GDDR5
MF=0 MF=1 MF=0MF=1
UV9
H5GQ1H24AFR-T2L_BGA170
X76@
WE# CS#
L12
CS# WE#
G12
CAS# RAS#
L3
RAS# CAS#
G3
CKE#
J3
CK
J12
CK#
J11
VPP/NC
U5
EDC0 EDC3
C2
EDC1 EDC2
C13
DQ24 DQ0 A4
DQ25 DQ1 A2
DQ26 DQ2 B4
DQ27 DQ3 B2
DQ28 DQ4 E4
DQ29 DQ5 E2
DQ30 DQ6 F4
DQ31 DQ7 F2
VSSQ E1
VSS
T10
VSS
L10
VSS
P10
VREFD
A10
VDD
D11 VDD
R10
VDDQ B1
VDDQ D1
VDDQ F1
VDDQ M1
VREFD
U10
VDDQ T1
ZQ
J13
RESET#
J2
WCK01 WCK23
D4
WCK23# WCK01#
P5
WCK23 WCK01
P4
VSSQ A1
VSSQ C1
VSSQ N1
VSSQ R1
WCK01# WCK23#
D5
VSSQ U1
VPP/NC
A5
VDDQ G2
VSSQ H2
VSSQ K2
VDDQ L2
VDDQ B3
VSSQ A3
VSS
G10
VDD
C10
ABI#
J4
VDD
R5
VSS
D10
VDD
C5
DQ17 DQ9 A13
DQ18 DQ10 B11
DQ19 DQ11 B13
DQ20 DQ12 E11
DQ21 DQ13 E13
DQ22 DQ14 F11
DQ23 DQ15 F13
DQ16 DQ8 A11
EDC2 EDC1
R13
BA2/A4 BA0/A2
K11
VDD
L4 VDD
G4 VDD
L1 VDD
G1
VSS
B10 VSS
T5 VSS
L5 VSS
G5 VSS
B5 VSS
K1 VSS
H1
VDDQ P1
BA3/A3 BA1/A5
H10
BA0/A2 BA2/A4
H11
BA1/A5 BA3/A3
K10
VDDQ D3
VDDQ F3
VDDQ H3
VDDQ K3
VDDQ M3
VDDQ P3
VDDQ T3
VDDQ E5
VDDQ N5
VDDQ E10
VDDQ N10
VDDQ B12
VDDQ D12
VDDQ F12
VDDQ H12
VDDQ K12
VDDQ M12
VDDQ P12
VDDQ T12
VDDQ G13
VDDQ L13
VDDQ B14
VDDQ D14
VDDQ F14
VDDQ M14
VDDQ P14
VSSQ C3
VSSQ E3
VSSQ N3
VSSQ R3
VSSQ U3
VSSQ C4
VSSQ R4
VSSQ F5
VSSQ M5
VSSQ F10
VSSQ M10
VSSQ C11
VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
VSSQ H13
VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
VSSQ U14
VDDQ T14
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VSS
H14
VSS
K14
DQ8 DQ16 U11
DQ9 DQ17 U13
DQ10 DQ18 T11
DQ11 DQ19 T13
DQ12 DQ20 N11
DQ13 DQ21 N13
DQ14 DQ22 M11
DQ15 DQ23 M13
DQ0 DQ24 U4
DQ1 DQ25 U2
DQ2 DQ26 T4
DQ3 DQ27 T2
DQ4 DQ28 N4
DQ5 DQ29 N2
DQ6 DQ30 M4
DQ7 DQ31 M2
EDC3 EDC0
R2
DBI0# DBI3#
D2
DBI1# DBI2#
D13
DBI2# DBI1#
P13
DBI3# DBI0#
P2
VREFC
J14
SEN
J10 MF
J1
A8/A7 A10/A0
K4
A9/A1 A11/A6
H5
A10/A0 A8/A7
H4
A11/A6 A9/A1
K5
A12/RFU/NC
J5
RV175
549_0402_1%
RV175
549_0402_1%
12
RV166
1K_0402_1%
RV166
1K_0402_1%
12
G
D
S
QV15
2N7002W-T/R7_SOT323-3
G
D
S
QV15
2N7002W-T/R7_SOT323-3
2
13
CV97
1U_0603_25V6
CV97
1U_0603_25V6
1
2
CV98
1U_0603_25V6
CV98
1U_0603_25V6
1
2
RV164
1K_0402_1%
RV164
1K_0402_1%
12
RV219
931_0402_1%
RV219
931_0402_1%
1 2
RV218
931_0402_1%
RV218
931_0402_1%
1 2
CV170
0.1U_0402_10V7K
CV170
0.1U_0402_10V7K
1
2
CV103
1U_0603_25V6
CV103
1U_0603_25V6
1
2
CV169
0.1U_0402_10V7K
CV169
0.1U_0402_10V7K
1
2
CV63
820P_0402_25V7
CV63
820P_0402_25V7
1
2
CV102
1U_0603_25V6
CV102
1U_0603_25V6
1
2
RV165
1K_0402_1%
RV165
1K_0402_1%
12
CV168
0.1U_0402_10V7K
CV168
0.1U_0402_10V7K
1
2
CV99
1U_0603_25V6
CV99
1U_0603_25V6
1
2
CV100
1U_0603_25V6
CV100
1U_0603_25V6
1
2
RV176
1.33K_0402_1%
RV176
1.33K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
11/11 for 2nd VGA fan
need to notic EC
follow MXM 3.0 spec
PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
SLI_FAN_SPEED
SLI_FAN_PWM
PLT_RST#
CLK2_REQ_GPU#_R
S_DGPU_PWR_EN
GC6_EVENT_SLI#
S_DGPU_RST
CLK_PCIE_2VGA
CLK_PCIE_2VGA#
GC6_SLI_EN
S_DGPU_PWR_EN#
SLI_B+_ON#
SLI_5V_ON#
S_DGPU_PWROK
PCIE_CRX_C_GTX_N15
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P8
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N14
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
SUSP#
VGA_AC_DET_R
S_NVDD_PWR_EN
PCH_THRMTRIP#_R
EC_SMB_DA2
EC_SMB_CK2
PCIE_CTX_C_GRX_P[0..15]<23,5>
PCIE_CRX_GTX_N[0..15]<23,5>
PCIE_CRX_GTX_P[0..15]<23,5>
PCIE_CTX_C_GRX_N[0..15]<23,5>
S_GC6_EVENT# <54>
SLI_FAN_PWM <44,46>
SLI_FAN_SPEED <44,46>
S_NVDD_PWR_EN <19,54>
S_DGPU_PWR_EN <19,54,55>
EC_SMB_CK2 <17,23,34,36,43,46>
CLK_PCIE_2VGA# <16>
CLK_PCIE_2VGA <16>
S_GC6_EN <27,54>
S_DGPU_PWR_EN# <55>
SLI_B+_ON# <56>
SLI_5V_ON# <56>
SUSP# <46,55,60,61,62>
CLK2_REQ_GPU#_R <16>
S_DGPU_RST <16,54>
PCH_THRMTRIP#_R <19,23>
PLT_RST# <14,23,40,41,46>
EC_SMB_DA2 <17,23,34,36,43,46>
S_DGPU_PWROK <16,54>
VGA_AC_DET_R <23>
SLAVE_PRESENT# <19>
B+_SLI
+5VS_SLI
+3VS_SLI +3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA MXM
Custom
32 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA MXM
Custom
32 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
VGA MXM
Custom
32 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CV180.22U_0402_10V6K CV180.22U_0402_10V6K
12
CV90.22U_0402_10V6K CV90.22U_0402_10V6K
12
CV70.22U_0402_10V6K CV70.22U_0402_10V6K
12
CV60.22U_0402_10V6K CV60.22U_0402_10V6K
12
CV160.22U_0402_10V6K CV160.22U_0402_10V6K
12
CV190.22U_0402_10V6K CV190.22U_0402_10V6K
12
JSLI1
TE_2199022-1_118P-T ME@
JSLI1
TE_2199022-1_118P-T ME@
GND
1GND 2
NC
3GND 4
NC
5GND 6
NC
7GND 8
NC
9+19V 10
NC
11 +19V 12
NC
13
NC
15
GND
17
PEG_RX_N7
19
PEG_RX_P7
21
GND
23 +19V 24
PEG_RX_N6
25 GND 26
PEG_RX_P6
27 GND 28
GND
29 GND 30
GND
31 GND 32
PEG_RX_N5
33 GND 34
PEG_RX_P5
35 GND 36
GND
37 +5V 38
PEG_RX_N4
39 +5V 40
PEG_RX_P4
41 +5V 42
GND
43 +5V 44
PEG_RX_N3
45 +5V 46
PEG_RX_P3
47 GND 48
GND
49 GND 50
PEG_RX_N2
51 GND 52
PEG_RX_P2
53
NC 54
GND
55
+3V 56
PEG_RX_N1
57
+3V 58
PEG_RX_P1
59
NC 62
GND
61 GND 60
NC 64
PEG_RX_P0
65
NC 66
GND
67
NC 70
PEG_TX_N7
71
NC 72
PEG_TX_N5
83
PWR_GOOD 84
PEG_TX_P5
85
CLK_REQ# 88
PEG_TX_N4
89
RSVD 90
PEG_TX_P7
73
TH_PWN 76
PEG_TX_N6
77
NC 78
PEG_TX_P6
79
AC_DC 82
PEG_TX_P4
91
NC 94
PEG_TX_N3
95
TH_OVERT# 96
PEG_TX_P3
97
RSVD 100
PEG_TX_N2
101
SMB_DAT 102
PEG_TX_P2
103
WAKE# 106
PEG_TX_N1
107
RSVD 108
PEG_TX_P1
109
GND 112
PEG_TX_N0
113
CLK_PCIE_N 114
PEG_TX_P0
115
CLK_PCIE_P 116
GND
117
GND 118
+19V 14
+19V 16
+19V 18
+19V 20
+19V 22
PEG_RX_N0
63
GND
69
GND
75
GND
81
GND
87
GND
93
GND
99
GND
111
GND
105
GND
119 GND 120
NC 68
TH_TACH 74
PEX_STD_SW# 80
PWR_EN 86
RSVD 92
NC 98
SMB_CLK 104
RSVD 110
GND
121 GND 122
CV130.22U_0402_10V6K CV130.22U_0402_10V6K
12
CV100.22U_0402_10V6K CV100.22U_0402_10V6K
12
CV80.22U_0402_10V6K CV80.22U_0402_10V6K
12
CV110.22U_0402_10V6K CV110.22U_0402_10V6K
12
RV234 0_0402_5%
@
RV234 0_0402_5%
@
1 2
CV140.22U_0402_10V6K CV140.22U_0402_10V6K
12
RV173 0_0402_5%@RV173 0_0402_5%@
1 2
RV158 0_0402_5%@RV158 0_0402_5%@
1 2
CV200.22U_0402_10V6K CV200.22U_0402_10V6K
12
CV150.22U_0402_10V6K CV150.22U_0402_10V6K
12
CV120.22U_0402_10V6K CV120.22U_0402_10V6K
12
CV170.22U_0402_10V6K CV170.22U_0402_10V6K
12
CV220.22U_0402_10V6K CV220.22U_0402_10V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power Rail
+3VS_VGA
ROM_SCLK
Logical
Strapping Bit3
Logical
Strapping Bit2
SLOT_CLK_CFG
Logical
Strapping Bit0
SUB_VENDOR PEX_PLL_EN_TERM
RAM_CFG[0]
STRAP0
STRAP1
STRAP2
ROM_SI RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
VGA_DEVICESMB_ALT_ADDR
PCI_DEVID[4]
ROM_SO FB[0]
Logical
Strapping Bit1
Physical
Strapping pin
X76
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Resistor Values Pull-up to
+3VS_VGA
5K 1000
10K
15K
20K
25K
30K
35K
45K
Pull-down to Gnd
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
FB[1]
3GIO_PAD_CFG_ADR[0]
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP3
STRAP4
+3VS_VGA
+3VS_VGA
SOR3_EXPOSED
RESERVED PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED DP_PLL_VDD33V
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
XCLK_417
0
1
277MHz (Default)
Reserved
3GIO_PADCFG
3GIO_PADCFG[3:0]
0000 Notebook Default
SLOT_CLK_CFG
GPU and MCH don't share a common reference clock
GPU and MCH share a common reference clock (Default)
0
1
SMBUS_ALT_ADDR
0
1
0x9E (Default)
0x9C (Multi-GPU usage)
VGA_DEVICE
0
1
3D Device (Class Code 302h)
VGA Device (Default)
USER Straps
User[3:0]
1000-1100 Customer defined
0
1
Disable (Default)
Enable
PEX_PLL_EN_TERM
0
1
Limit to PCIE Gen1
PCIE Gen 2/3 Capable
PCIE_MAX_SPEED
SUB_VENDOR
0
1
No VBIOS ROM (Default)
BIOS ROM is present
FB_0_BAR_SIZE
0
1
256MB (Default)
Reserved
2
3
Reserved
Reserved
FB Memory (GDDR5)
K4G20325FD-FC04 2G 64Mx32
K4G10325FG-HC04 1G 32Mx32
H5GQ2H24MFR-T2C 2G 64Mx32
H5GQ1H24BFR-T2C 1G 32Mx32
GPU
N13P-GT1
28nm
Hynix
Samsung
ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
PD 30K
PD 45K
PD 25K
PD 20K
PU 10K
PD 15K
(ROM not present)
PD 35K
(ROM present)
PU 45K PD 5K PD 25K PU 5K PD 45K
X76
Samsung
X76
X76409JVL01 (2G 64Mx32) SA00005B70J
X76409JVL02 (2G 64Mx32)
VRAM P/N
SA00004GD0J
VRAM
2012-0418 --> Set BOM
structure as Stuff for ALL SKU
PD 25KH5GQ2H24AFR-T2C 2G 64Mx32
SA00004GD1JHynix X76409JVL02 (2G 64Mx32)
EOL
EOL
SA00003RS0JX76409JVL51 (1G 32Mx16)
X76409JVL52 (1G 32Mx16) SA00003WL1J
STRAP0
STRAP2
STRAP1
ROM_SI
ROM_SO
STRAP4
STRAP3
ROM_SCLK
STRAP0<24>
STRAP1<24>
STRAP2<24>
ROM_SI<24>
ROM_SO<24>
ROM_SCLK<24>
STRAP3<24>
STRAP4<24>
+3VS_VGA
+3VS_VGA
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_MISC
Custom
33 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_MISC
Custom
33 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
N13P_MISC
Custom
33 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RV96
4.99K_0402_1%
RV96
4.99K_0402_1%
1 2
RV95
45.3K_0402_1%
@RV95
45.3K_0402_1%
@
1 2
RV93
4.99K_0402_1%
@
RV93
4.99K_0402_1%
@
1 2
RV97
24.9K_0402_1%
GT@
RV97
24.9K_0402_1%
GT@
1 2
RV101
20K_0402_1%
X76@
RV101
20K_0402_1%
X76@
1 2
RV122
20K_0402_1%
@
RV122
20K_0402_1%
@
1 2
RV100
4.99K_0402_1%
@
RV100
4.99K_0402_1%
@
1 2
RV103
4.99K_0402_1%
GT1@
RV103
4.99K_0402_1%
GT1@
1 2
RV103
15K_0402_1%
GT@
RV103
15K_0402_1%
GT@
RV99
10K_0402_1%
RV99
10K_0402_1%
1 2
RV124
4.99K_0402_1%
@
RV124
4.99K_0402_1%
@
1 2
RV94
30K_0402_1%
GT1@
RV94
30K_0402_1%
GT1@
1 2
RV98
4.99K_0402_1%
@
RV98
4.99K_0402_1%
@
1 2
RV92
45.3K_0402_1%
RV92
45.3K_0402_1%
1 2
RV125
45.3K_0402_1%
RV125
45.3K_0402_1%
1 2
RV102
30K_0402_1%
@
RV102
30K_0402_1%
@
1 2
RV121
4.99K_0402_1%
RV121
4.99K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Noe:
LVDS output swing control
4.99K for default swing, change the value for
swing adjust
Initial Code EEPROM
I2C_CFG = "H"
EEPROM for Initial Code
I2C Address: 0xA0
Suggest minimum 8Kbit
Power On Configuration
I2C_ADDR: I2C Slave address selection, internal pull-down ~80KRLV_CFG: LVDS color depth and data
mapping selection, internal pull-down ~80K
1.2V
Default
L:8-bit VESA mapping
H:6-bit both VESA
and JEIDA mapping
RLV_CFG
M:8-bit JEIDA mapping
To LVDS
panel
Use BLM18KG331SN1 Use BLM18KG331SN1 Use BLM18KG331SN1
Use 2.2uH 800mA
Close Pin14
Close Pin6
Close Pin38,50
Close Pin19
Close Pin12,13 GND of 4.7uF capacitor
behind Inductor.
Default
L:0x10h~0x1Fh
H:0x90h~0x9Fh
ENPVCC_I2C_ADDR
*
RC
Stuff
NA
RA RB
RA
RB
Stuff
Stuff
NA
NANA
NA
GPIO0: LVDS single link or dual link selection, internal pull-down ~80K
RC RD
Close to UT3
Close to JLVDS1
*
Default
Daul channel
Single channel
GPIO0
*
RD
Stuff
NA
EDID_CLK_CON
EDID_DAT_CON
GPIO0
CSDA/MSDA
CSCL/MSCL
RLV_CFG
VDDIO_DTL
VDDIO_DTL
VDDRX_DTL
EN_BACKLIGHT
ENPVCC_I2C_ADDR
TL_INVPWM
VDD12_DTL
VDDIO_DTL
VDDIO_DTL
ENPVCC_I2C_ADDR
VDDIO_DTL
DTL_PD#
DTL_RST#
VDDIO_DTL
VDDIOX_DTL SW_OUT VDDRX_DTLVDD12_DTLVDDIO_DTL
CSDA/MSDA
CSCL/MSCL
VDDRX_DTL
VDDIOX_DTL
VDDIOX_DTL
VDD12_DTL
VDDIO_DTL
VDDIO_DTL
EDP_HPD
DTL_RST#
DTL_PD#
TL_INVPWM
ENPVCC_I2C_ADDR
GPIO0
RLV_CFG
EN_BACKLIGHT
REXT
RLV_AMP
SW_OUT
SW_OUT
LVDS_A0_NVS
LVDS_A0#_NVS
LVDS_A1_NVS
LVDS_A1#_NVS
LVDS_A2_NVS
LVDS_A2#_NVS
LVDS_B0_NVS
LVDS_B0#_NVS
LVDS_B1_NVS
LVDS_B1#_NVS
LVDS_B2_NVS
LVDS_B2#_NVS
LVDS_BCLK#_NVS
LVDS_BCLK_NVS
LVDS_ACLK#_NVS
LVDS_ACLK_NVS
CSCL/MSCL
EDID_DAT_CON
CSDA/MSDA
EDID_CLK_CON
INVT_PWM
EDP_TX0-_C
EDP_TX0+_C
EDP_TX1-_C
EDP_TX1+_C
EDP_AUX_C
EDP_AUX#_C
EDP_AUX
EDP_TX0-
EDP_TX0+
EDP_TX1+
EDP_TX1-
EDP_HPD_CONEDP_HPD
EDP_AUX#
EDP_AUX
EDP_TX0-
EDP_TX0+
EDP_TX1+
EDP_TX1-
EDP_AUX#
EC_SMB_CK2
EC_SMB_DA2
GPIO0
VDDIO_DTL
EDP_TX0-_CON
EDP_TX0+_CON
EDP_AUX#_CON
EDP_AUX_CON
EDP_TX0-_C
EDP_TX0+_C
EDP_AUX_C
EDP_AUX#_C
EDP_TX1+_C
EDP_TX1-_C
EDP_TX1+_CON
EDP_TX1-_CON
EDID_CLK_CON <35>
EDID_DAT_CON <35>
ENPVCC_I2C_ADDR <35>
EN_BACKLIGHT <35>
TL_INVPWM <35>
EDP_HPD<38>
LVDS_A0_NVS <35>
LVDS_A0#_NVS <35>
LVDS_A1_NVS <35>
LVDS_A1#_NVS <35>
LVDS_A2_NVS <35>
LVDS_A2#_NVS <35>
LVDS_B0_NVS <35>
LVDS_B0#_NVS <35>
LVDS_B1_NVS <35>
LVDS_B1#_NVS <35>
LVDS_B2_NVS <35>
LVDS_B2#_NVS <35>
LVDS_BCLK#_NVS <35>
LVDS_BCLK_NVS <35>
LVDS_ACLK#_NVS <35>
LVDS_ACLK_NVS <35>
INVT_PWM<35>
EDP_HPD_CON <35>
EDP_AUX#_C<38>
EDP_AUX_C<38>
EDP_TX0+_C<38>
EDP_TX0-_C<38>
EDP_TX1+_C<38>
EDP_TX1-_C<38>
EDP_TX0-_CON <35>
EDP_TX0+_CON <35>
EDP_AUX_CON <35>
EDP_AUX#_CON <35>
EDP_TX1-_CON <35>
EDP_TX1+_CON <35>
EC_SMB_CK2<17,23,32,36,43,46>
EC_SMB_DA2<17,23,32,36,43,46>
+3.3VS_DTL+3VS +3.3VS_DTL
+3.3VS_DTL
+3.3VS_DTL
+3.3VS_DTL
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
34 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
34 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
34 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CT9
1U_0402_6.3V6K
CT9
1U_0402_6.3V6K
1
2
CT17 0.1U_0402_10V7KCT17 0.1U_0402_10V7K
12
RT9 4.99K_0402_1%RT9 4.99K_0402_1%
12
CT8 0.1U_0402_10V7KCT8 0.1U_0402_10V7K
12
RT1270 0_0402_5%RT1270 0_0402_5%
12
CT15 0.1U_0402_10V7KCT15 0.1U_0402_10V7K
12
CT7 0.1U_0402_10V7KCT7 0.1U_0402_10V7K
12
RT6
4.7K_0402_5%
RT6
4.7K_0402_5%
12
LT1 BLM18PG331SN1D_2PLT1 BLM18PG331SN1D_2P
1 2
CT320.1U_0402_10V7K
EDP@
CT320.1U_0402_10V7K
EDP@
1 2
CT5
0.47U_0402_6.3V6K
CT5
0.47U_0402_6.3V6K
1
2
UT2
M24C08-WMN6TP_SO8
@UT2
M24C08-WMN6TP_SO8
@
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
PS8625
UT3
PS8625QFN56GTR-A0_QFN56_7X7
PS8625
UT3
PS8625QFN56GTR-A0_QFN56_7X7
NC
56
ENBLT
23
TESTMODE
20
TD0n 44
SW_OUT
15
TD0p 43
PD#
10
PWMO
12
VDDRX
6
GNDX 17
TCK0n 47
TCK0p 46
VDDIOX
13
TC0n 49
TC0p 48
GNDX 18
TB0n 52
TB0p 51
VDDIOX
14
TA0n 54
TA0p 53
GND 28
RLV_CFG
22
RLV_AMP
27 REXT
26
ENPVCC
33
RLV_LNK/GPIO0
21
GND 3
PWMI
45
VDD12
19
NC
55
SW_OUT
16
DAUXn
1
DAUXp
2
VDDIO
38
DRX0p
4
DRX0n
5
DRX1p
7
DRX1n
8
VDDIO
50
HPD
11
RST#
9
Epad 57
TA1p 41
TA1n 42
TB1p 39
TB1n 40
TC1p 36
TC1n 37
TCK1p 34
TCK1n 35
TD1p 31
TD1n 32
DDC_SDA 30
DDC_SCL 29
CSDA/MSDA 24
CSCL/MSCL 25
RT1 10K_0402_5%RT1 10K_0402_5%
1 2
RT1268 0_0402_5%
EDP@
RT1268 0_0402_5%
EDP@
1 2
CT10
0.47U_0402_6.3V6K
CT10
0.47U_0402_6.3V6K
1
2
CT16 0.1U_0402_10V7KCT16 0.1U_0402_10V7K
12
CT11 0.01U_0402_16V7KCT11 0.01U_0402_16V7K
12
CT3
1U_0402_6.3V6K
CT3
1U_0402_6.3V6K
12
CT13 0.01U_0402_16V7KCT13 0.01U_0402_16V7K
12
CT22 0.1U_0402_10V7KCT22 0.1U_0402_10V7K
12
CT2
4.7U_0603_6.3V6K
CT2
4.7U_0603_6.3V6K
1
2
CT6
1U_0402_6.3V6K
CT6
1U_0402_6.3V6K
1
2
CT4
4.7U_0603_6.3V6K
CT4
4.7U_0603_6.3V6K
1
2
RT13
2K_0402_5%
RT13
2K_0402_5%
12
CT1
2.2U_0402_6.3V6M
CT1
2.2U_0402_6.3V6M
12
RT3
4.7K_0402_5%
@RT3
4.7K_0402_5%
@
12
RT12
2K_0402_5%
RT12
2K_0402_5%
12
CT310.1U_0402_10V7K
EDP@
CT310.1U_0402_10V7K
EDP@
1 2
CT18 0.1U_0402_10V7KCT18 0.1U_0402_10V7K
12
CT12 0.1U_0402_10V7KCT12 0.1U_0402_10V7K
12
CT340.1U_0402_10V7K
EDP@
CT340.1U_0402_10V7K
EDP@
1 2
CT350.1U_0402_10V7K
EDP@
CT350.1U_0402_10V7K
EDP@
1 2
CT14 0.1U_0402_10V7KCT14 0.1U_0402_10V7K
12
RT10
4.7K_0402_5%
DAUL@ RT10
4.7K_0402_5%
DAUL@
12
RT8 4.7K_0402_5%@RT8 4.7K_0402_5%@
1 2
CT300.1U_0402_10V7K
EDP@
CT300.1U_0402_10V7K
EDP@
1 2
RT7 4.7K_0402_5%@RT7 4.7K_0402_5%@
1 2
RT2 10K_0402_5%RT2 10K_0402_5%
1 2
LT3 BLM18PG331SN1D_2PLT3 BLM18PG331SN1D_2P
1 2
CT330.1U_0402_10V7K
EDP@
CT330.1U_0402_10V7K
EDP@
1 2
RT1271 0_0402_5%RT1271 0_0402_5%
1 2
RT1272 0_0402_5%RT1272 0_0402_5%
1 2
LT2
2.2UH_HPC252012F-2R2M_1.3A_20%
LT2
2.2UH_HPC252012F-2R2M_1.3A_20%
1 2
RT14 4.99K_0402_1%RT14 4.99K_0402_1%
12
LT4 BLM18PG331SN1D_2PLT4 BLM18PG331SN1D_2P
1 2
CT19 0.1U_0402_10V7KCT19 0.1U_0402_10V7K
12
RT15
4.7K_0402_5%
@
RT15
4.7K_0402_5%
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
2A 80 mil 2A 80 mil
9/23 EMI Request
W=40mils
CMOS Camera
(40 MIL)
(60 MIL)
W=60mils
W=40mils
EMI request ESD request
LVDS LOAD SWITCH
1.9mS Typical Rise time ,Rds_on 80m ohm
LCDVDD
GPU
PCH
eDP to LVDS
+CMOS_PW_R
EDID_CLK_CON
EDID_DAT_CON
DISPOFF#
DMIC_CLK TL_INVPWM
DISPOFF#
DMIC_DATA
DMIC_CLK
EDP_AUX_CON
EDP_AUX#_CON
USB20_N0
USB20_P0 USB20_P0_CMOS
USB20_N0_CMOS
USB20_N0_CMOS
USB20_P0_CMOS
USB20_N0
USB20_P0 USB20_P0_CMOS
USB20_N0_CMOS
USB20_N0_CMOS
USB20_P0_CMOS
EDP_TX0+_CON
EDP_TX0-_CON
EDP_HPD_CON
EDP_TX1+_CON
EDP_TX1-_CON
INVT_PWM
TL_INVPWM
ENBKL
LVDS_BCLK#_NVS
LVDS_BCLK_NVS
LVDS_B2_NVS
LVDS_B2#_NVS
LVDS_B1_NVS
LVDS_B1#_NVS
LVDS_B0_NVS
LVDS_B0#_NVS
LVDS_ACLK_NVS
LVDS_ACLK#_NVS
LVDS_A2_NVS
LVDS_A2#_NVS
LVDS_A1_NVS
LVDS_A1#_NVS
LVDS_A0_NVS
LVDS_A0#_NVS
BKOFF#
CMOS_ON#<19>
EDID_CLK_CON<34>
EDID_DAT_CON<34>
BKOFF# <46>
EN_BACKLIGHT <34>
DMIC_CLK<45>
DMIC_DATA<45>
USB20_N0<18>
USB20_P0<18>
EDP_HPD_CON <34>
ENPVCC_I2C_ADDR<34>
PCH_ENVDD<14>
VGA_ENVDD<23>
TL_INVPWM<34>
VGA_BL_PWM<23>
PCH_EDP_PWM<14>
INVT_PWM <34>
VGA_ENBKL<23>
PCH_ENBKL<14>
ENBKL <46>
LVDS_BCLK#_NVS<34>
LVDS_BCLK_NVS<34>
LVDS_B2_NVS<34>
LVDS_B2#_NVS<34>
LVDS_B1_NVS<34>
LVDS_B1#_NVS<34> LVDS_B0_NVS<34>
LVDS_B0#_NVS<34>
LVDS_ACLK_NVS<34>
LVDS_ACLK#_NVS<34>
LVDS_A2_NVS<34>
LVDS_A2#_NVS<34>
LVDS_A1_NVS<34>
LVDS_A1#_NVS<34>
LVDS_A0_NVS<34> LVDS_A0#_NVS<34>
EDP_AUX#_CON <34>
EDP_AUX_CON <34>
EDP_TX0-_CON <34>
EDP_TX0+_CON <34>
EDP_TX1+_CON <34>
EDP_TX1-_CON <34>
B++LEDVDD
+3VS
+CMOS_PW
+LEDVDD
+LCDVDD_CON
+3VS
+3VS
+3VS
+CMOS_PW
+3VS
+3VS +LCDVDD_CON
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
35 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
35 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
35 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
R828
100K_0402_5%
R828
100K_0402_5%
1 2
C527
470P_0402_50V7K
@
C527
470P_0402_50V7K
@
1
2
R822 4.7K_0402_5%
@
R822 4.7K_0402_5%
@
12
R435
100K_0402_5%
CMOS@
R435
100K_0402_5%
CMOS@
1 2
R1166 0_0402_5%R1166 0_0402_5%
1 2
C519
10U_0603_6.3V6M
@
C519
10U_0603_6.3V6M
@
1
2
C525
470P_0402_50V7K
@
C525
470P_0402_50V7K
@
1
2
U76
NCT3521U
U76
NCT3521U
GND 2
EN 3
IN
5
DIS
4
VOUT 1
R8230_0402_5%
@
R8230_0402_5%
@
12
L74
WCM-2012-900T_4P
@
L74
WCM-2012-900T_4P
@
11
44
3
3
2
2
R432
0_0603_5%
CMOS@
R432
0_0603_5%
CMOS@
1 2
R813
R_short 0_0805_5%
R813
R_short 0_0805_5%
1 2
C520
0.1U_0402_16V4Z
CMOS@
C520
0.1U_0402_16V4Z
CMOS@
1
2
C934
100P_0402_50V8J
C934
100P_0402_50V8J
1
2
R834
0_0402_5%
R834
0_0402_5%
1 2
D60
DAN202UT106_SC70-3
D60
DAN202UT106_SC70-3
2
3
1
D61
DAN202UT106_SC70-3
@D61
DAN202UT106_SC70-3
@
2
3
1
C518
0.1U_0402_16V4Z
CMOS@
C518
0.1U_0402_16V4Z
CMOS@
1
2
JLVDS1
ACES_87142-4041-BS
ME@JLVDS1
ACES_87142-4041-BS
ME@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
GND1
41 GND2 42
CV283
4.7U_0603_6.3V6K
CV283
4.7U_0603_6.3V6K
1
2
R826
0_0402_5%
R826
0_0402_5%
1 2
D62
DAN202UT106_SC70-3
D62
DAN202UT106_SC70-3
2
3
1
C524
4.7U_0805_25V6-K
C524
4.7U_0805_25V6-K
1
2
R827
100K_0402_5%
R827
100K_0402_5%
1 2
G
D
S
Q94 AO3413_SOT23-3
CMOS@
G
D
S
Q94 AO3413_SOT23-3
CMOS@
2
13
R829
100K_0402_5%
R829
100K_0402_5%
1 2
C1052
0.01U_0402_16V7K
@C1052
0.01U_0402_16V7K
@
1
2
D59
AZC099-04S.R7G_SOT23-6
@D59
AZC099-04S.R7G_SOT23-6
@
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
R8910_0402_5% R8910_0402_5%
12
R1515
0_0402_5%
@
R1515
0_0402_5%
@
1 2
R818
150_0603_1%
R818
150_0603_1%
C529
680P_0402_50V7K
@
C529
680P_0402_50V7K
@
1
2
R1196 0_0402_5%
@
R1196 0_0402_5%
@
1 2
R1202 0_0402_5%R1202 0_0402_5%
1 2
JCMOS1
ME@
JCMOS1
ME@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
GND
9
GND
10
C523
470P_0603_50V8J
C523
470P_0603_50V8J
1
2
C1051
0.1U_0402_16V4Z
@C1051
0.1U_0402_16V4Z
@
1
2
C291
1U_0402_6.3V6K
C291
1U_0402_6.3V6K
1
2
R1212 0_0402_5%R1212 0_0402_5%
1 2
R1198 0_0402_5%
@
R1198 0_0402_5%
@
1 2
C58
0.047U_0402_16V4Z
@
C58
0.047U_0402_16V4Z
@
12
R1197
0_0402_5%
R1197
0_0402_5%
1 2
R1167 0_0402_5%R1167 0_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLOSE TO CONN
CRT Connector
W=40mils
From SW
From CRT SW
From CRT SW
CRT_DDC_DAT_CON
CRT_DDC_DAT_CON
CRT_DDC_CLK_CON
CRT_DDC_CLK_CON
CRT_R_CON
CRT_G_CON
HSYNC_CON
VSYNC_CON
CRT_B_CON
VSYNC_CON
HSYNC_CON
OE#
OE#
CRT_DDC_DAT_CON
HSYNC_CON
CRT_DDC_CLK_CON
VSYNC_CON
CRT_HSYNC_1
CRT_VSYNC_1
CRT_HSYNC_2
CRT_VSYNC_2
DDC_CLK_R
CRT_DDC_DATA_R DDC_DAT_R
CRT_DDC_CLK_R
CRT_DET#
+CRT_VCC_CON
EC_SMB_DA2
EC_SMB_CK2
CRT_R_CON CRT_G_CON
CRT_B_CONCRT_DET#
CRT_DDC_DATA_R<37>
CRT_DDC_CLK_R<37>
CRT_DET#<14>
DAC_BLU_1<37>
DAC_GRN_1<37>
DAC_RED_1<37>
VSYNC_G<37>
HSYNC_G<37>
EC_SMB_DA2<17,23,32,34,43,46>
EC_SMB_CK2<17,23,32,34,43,46>
+5VS
+CRT_VCC
+CRT_VCC
+CRT_VCC
+CRT_VCC
+3VS
+CRT_VCC_CON
+CRT_VCC_CON
+CRT_VCC_CON
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CRT Connector
Custom
36 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CRT Connector
Custom
36 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CRT Connector
Custom
36 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
C546
0.1U_0402_16V4Z
C546
0.1U_0402_16V4Z
1
2
C548
100P_0402_50V8J
@
C548
100P_0402_50V8J
@
1
2
L16 NBQ100505T-800Y_0402L16 NBQ100505T-800Y_0402
1 2
R837
2.2K_0402_5%
R837
2.2K_0402_5%
12
R838
2.2K_0402_5%
R838
2.2K_0402_5%
12
L20
NBQ100505T-800Y_0402
L20
NBQ100505T-800Y_0402
1 2
U25
SN74AHCT1G125DCKR_SC70-5
U25
SN74AHCT1G125DCKR_SC70-5
A
2Y4
OE# 1
G
3P5
R832
150_0402_1%
R832
150_0402_1%
12
G
D
S
Q73A
2N7002KDWH_SOT363-6
G
D
S
Q73A
2N7002KDWH_SOT363-6
2
61
G
G
JCRT1
SUYIN_070546HR015M22BZR
ME@
G
G
JCRT1
SUYIN_070546HR015M22BZR
ME@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
L19
NBQ100505T-800Y_0402
L19
NBQ100505T-800Y_0402
1 2
R839
33_0603_5%
R839
33_0603_5%
1 2
C545
10P_0402_50V8J
@
C545
10P_0402_50V8J
@
1
2
C541
10P_0402_50V8J
C541
10P_0402_50V8J
1
2
R1191 0_0402_5%
@
R1191 0_0402_5%
@
1 2
C539
10P_0402_50V8J
C539
10P_0402_50V8J
1
2
G
D
S
Q73B
2N7002KDWH_SOT363-6
G
D
S
Q73B
2N7002KDWH_SOT363-6
5
34
R1190 0_0402_5%R1190 0_0402_5%
1 2
R1192 0_0402_5%
@
R1192 0_0402_5%
@
1 2
D31
AZC099-04S.R7G_SOT23-6
@D31
AZC099-04S.R7G_SOT23-6
@
I/O4 6
VDD 5
I/O3 4
I/O2
3
GND
2
I/O1
1
C537
10P_0402_50V8J
C537
10P_0402_50V8J
1
2
C542
10P_0402_50V8J
C542
10P_0402_50V8J
1
2
R840
33_0603_5%
R840
33_0603_5%
1 2
D7
AZC099-04S.R7G_SOT23-6
@D7
AZC099-04S.R7G_SOT23-6
@
I/O4 6
VDD 5
I/O3 4
I/O2
3
GND
2
I/O1
1
C538
10P_0402_50V8J
C538
10P_0402_50V8J
1
2
C536
0.1U_0402_16V4Z
C536
0.1U_0402_16V4Z
1
2
D36
RB491D_SC59-3
D36
RB491D_SC59-3
2 1
F1
0.5A_8V_KMC3S050RY
F1
0.5A_8V_KMC3S050RY
21
R833
1K_0402_5%
R833
1K_0402_5%
1 2
U24
SN74AHCT1G125DCKR_SC70-5
U24
SN74AHCT1G125DCKR_SC70-5
A
2Y4
OE# 1
G
3P5
R1189 0_0402_5%R1189 0_0402_5%
1 2
L18 NBQ100505T-800Y_0402L18 NBQ100505T-800Y_0402
1 2
R831
150_0402_1%
R831
150_0402_1%
12
C540
10P_0402_50V8J
C540
10P_0402_50V8J
1
2
C547
10P_0402_50V8J
@C547
10P_0402_50V8J
@
1
2
C543
100P_0402_50V8J
C543
100P_0402_50V8J
1
2
L17 NBQ100505T-800Y_0402L17 NBQ100505T-800Y_0402
1 2
C544
0.1U_0402_16V4Z
C544
0.1U_0402_16V4Z
1
2
C549
68P_0402_50V8K
@
C549
68P_0402_50V8K
@
1
2
R830
150_0402_1%
R830
150_0402_1%
12
2
2
1
1
B B
A A
Channel A --> GPU
Channel B --> PCH
For reserved CRT SW
L
Input SELx
nB2---PCH
nB1--GPU
Input/Output An
H An=nB2
An=nB1
Function
SEL
L: No DDC active
buffer, passive
DDC level shifting
H:Active DDC buffer
enable, setting 1
DDC_BUF
*
M:Active DDC buffer
enable, setting 2
RA RB
RA RB
Stuff
Stuff
NA
NANA
NA
RC RD RFRE
RG RH RI RJ
RK RL
SEL
IN1_PEQ/IN2_PEQ: Rx Equalization Setting for
port1/port2.Internal pull-down ~500K ohm
*
IN1_PEQ/IN2_PEQ
H: High level receiving
equalization selection
L: Middle level
receiving equalization
selection
RDRC
M: Low level receiving
equalization selection NA
Stuff
Stuff
NA
NA NA
RFRE
NA
Stuff
Stuff
NANA
NA
PRE_EMI: TMDS output drive pre-emphasis and
EMI setting, Internal pull-down ~500K ohm
SEL
L: No pre-emphasis,
no EMI control
H: Pre-emphasis
added, no EMI control
PRE_EMI
*
M: No pre-emphasis,
EMI control selected
RG RH
Stuff
Stuff
NA
NANA
NA
CFG_HPD: HPD switching configuration.
Internal pull-down ~500K
L: IN1_HPD=OUT_HPD when SW_MAIN=L /
IN2_HPD=OUT_HPD when SW_MAIN=H
IN1_HPD=LOW otherwise /
IN2_HPD=LOW otherwise
SEL
M: IN1_HPD=OUT_HPD when SW_DDC=L or SW_MAIN=L /
IN2_HPD=OUT_HPD when SW_DDC=H or SW_MAIN=H
IN1_HPD=LOW otherwise / IN2_HPD=LOW otherwise
*
CFG_HPD
H: IN1_HPD=OUT_HPD SW_DDC=L/
IN2_HPD=OUT_HPD SW_DDC=H
IN1_HPD=LOW otherwise /
IN2_HPD=LOW otherwise
Stuff
RJRI
NA
NA NA
NA
Stuff
PWDN_ASQ: Power down control. Internal pull-down
~500K
L: Normal operation
SEL
*
PWDN_ASQ
H: power down Stuff
RHRG
NA
NA NA
For PS8271: R35/R36 NC
For PS8272: R35/R36 NC, pin21/pin22 NC or SW_MAIN/SW_DDC driven to LOW
For PS8273: R35/R36 stuff or SW_MAIN/SW_DDC driven to HIGH
DDCBUF DDC_BUF_EN = L: No DDC active
buffer, passive DDC level shifting
SW
SW_DDC IN1---CPU
IN2---GPU
SW_MAIN
Input Output
H=IN2
L=IN1
IN2---GPU
IN1---CPU
H=IN2
L=IN1
CRT_SWITCH_1
VGA_HDMI_CLK+
VGA_HDMI_TX1+
VGA_HDMI_TX0-
VGA_HDMI_TX0+
VGA_HDMI_TX2-
VGA_HDMI_TX2+
VGA_HDMI_CLK-
VGA_HDMI_TX1-
VGA_HDMI_DATA
VGA_HDMI_CLK
DDC_BUF
PRE_EMI
IN1_PEQ
IN2_PEQ
CFG_HPD
PWDN_ASQ
DDC_BUF IN1_PEQ IN2_PEQ
PRE_EMI CFG_HPD
PWDN_ASQ
HDMI_CONN_HPD
DDPB_DATA
DDPB_CLK
HDSW_DDC
HDSW_MAIN
HDSW_DDC
HDSW_MAIN
DDPB_CLK
DDPB_DATA
HDSW_MAIN HDSW_DDC
CRT_SWITCH_1
CPU_HDMI_TX0-_C
CPU_HDMI_TX0+_C
CPU_HDMI_TX1-_C
CPU_HDMI_TX1+_C
CPU_HDMI_TX2-_C
CPU_HDMI_TX2+_C
CPU_HDMI_CLK-_C
CPU_HDMI_CLK+_C
GPU_HDMI_TX0-_C
GPU_HDMI_TX0+_C
GPU_HDMI_TX1-_C
GPU_HDMI_TX1+_C
GPU_HDMI_TX2-_C
GPU_HDMI_TX2+_C
GPU_HDMI_CLK-_C
GPU_HDMI_CLK+_C
VGA_CRT_B<23>
VGA_CRT_G<23>
VGA_CRT_R<23>
VGA_CRT_VSYNC<23>
VGA_CRT_HSYNC<23>
VGA_CRT_DATA<23>
VGA_CRT_CLK<23>
PCH_CRT_B<14>
PCH_CRT_G<14>
PCH_CRT_R<14>
PCH_CRT_HSYNC<14>
PCH_CRT_DDC_DAT<14>
PCH_CRT_DDC_CLK<14>
DAC_GRN_1 <36>
DAC_RED_1 <36>
PCH_CRT_VSYNC<14>
CRT_DDC_DATA_R <36>
CRT_DDC_CLK_R <36>
DAC_BLU_1 <36>
CRT_SWITCH_1 <13>
VSYNC_G <36>
HSYNC_G <36>
VGA_HDMI_DATA <39>
VGA_HDMI_CLK <39>
GPU_HDMI_CLK<24>
GPU_HDMI_DATA<24>
HDMI_CONN_HPD <39>
DDPB_CLK<14>
DDPB_DATA<14>
HDSW_DDC<19>
HDSW_MAIN<19>
VGA_HDMI_TX2- <39>
VGA_HDMI_CLK+ <39>
VGA_HDMI_TX0+ <39>
VGA_HDMI_TX1- <39>
VGA_HDMI_TX1+ <39>
VGA_HDMI_CLK- <39>
VGA_HDMI_TX2+ <39>
VGA_HDMI_TX0- <39>
TMDS_B_HPD<14>
DGPU_HDMI_HPD<23,39>
CPU_HDMI_CLK+<8>
CPU_HDMI_TX1+<8>
CPU_HDMI_TX0+<8>
CPU_HDMI_TX0-<8>
CPU_HDMI_TX2+<8>
CPU_HDMI_TX2-<8>
CPU_HDMI_CLK-<8>
CPU_HDMI_TX1-<8>
GPU_HDMI_TX0-<24>
GPU_HDMI_TX0+<24>
GPU_HDMI_TX1+<24>
GPU_HDMI_CLK+<24>
GPU_HDMI_TX1-<24>
GPU_HDMI_CLK-<24>
GPU_HDMI_TX2-<24>
GPU_HDMI_TX2+<24>
+3VS
+3VS +3VS_HDSW +3VS_HDSW +3VS_HDSW +3VS_HDSW
+3VS_HDSW +3VS_HDSW
+3VS_HDSW
+3VS_HDSW
+3VS_HDSW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI and CRT SW
Custom
37 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI and CRT SW
Custom
37 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI and CRT SW
Custom
37 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CM15 0.1U_0402_10V6KCM15 0.1U_0402_10V6K
1 2
CM5 0.1U_0402_10V6KCM5 0.1U_0402_10V6K
1 2
CM4 0.1U_0402_10V6KCM4 0.1U_0402_10V6K
1 2
CM6 0.1U_0402_10V6KCM6 0.1U_0402_10V6K
1 2
RM18
4.7K_0402_5%
@RM18
4.7K_0402_5%
@
1 2
RM26
430_0402_1%
RM26
430_0402_1%
12
CM1
2.2U_0603_6.3V6K
CM1
2.2U_0603_6.3V6K
1
2
CM17 0.1U_0402_10V6KCM17 0.1U_0402_10V6K
1 2
RM19
4.7K_0402_5%
@RM19
4.7K_0402_5%
@
1 2
RM33 0_0402_5%RM33 0_0402_5%
1 2
RM14
4.7K_0402_5%
@RM14
4.7K_0402_5%
@
1 2
CM19 0.1U_0402_10V6KCM19 0.1U_0402_10V6K
1 2
CM13 0.1U_0402_10V6KCM13 0.1U_0402_10V6K
1 2
RM29 2.2K_0402_5%RM29 2.2K_0402_5%
1 2
CM7 0.1U_0402_10V6KCM7 0.1U_0402_10V6K
1 2
CM8 0.1U_0402_10V6KCM8 0.1U_0402_10V6K
1 2
CM16 0.1U_0402_10V6KCM16 0.1U_0402_10V6K
1 2
RM20
4.7K_0402_5%
@RM20
4.7K_0402_5%
@
1 2
UM1
PI3V712-AZLEX_TQFN32_6X3
UM1
PI3V712-AZLEX_TQFN32_6X3
A0 1
A1 2
GND 3
VDD
4
A2 5
A3 6
A4 7
4B2
17
4B1
18 3B1
20
3B2
19
0B2
26
0B1
27
1B1
25
1B2
24
GND 31
VDD
32
A5 9
SEL1 8
A6 10
GND 11
5B1
12
5B2
13
6B1
14
2B2
21
2B1
22
VDD
23
VDD
29
GND 28
SEL2 30
6B2
15
VDD
16
GPAD 33
CM11 0.1U_0402_10V6KCM11 0.1U_0402_10V6K
1 2
RM28 4.7K_0402_5%RM28 4.7K_0402_5%
1 2
CM12 0.1U_0402_10V6KCM12 0.1U_0402_10V6K
1 2
CM3 0.01U_0402_16V7KCM3 0.01U_0402_16V7K
1 2
RM27 4.7K_0402_5%RM27 4.7K_0402_5%
1 2
CM1183
1U_0603_10V6K
CM1183
1U_0603_10V6K
1
2
RM22
4.7K_0402_5%
@RM22
4.7K_0402_5%
@
1 2
RM23
4.7K_0402_5%
@RM23
4.7K_0402_5%
@
1 2
RM15
4.7K_0402_5%
@RM15
4.7K_0402_5%
@
1 2
RM1
0_0402_5%
RM1
0_0402_5%
12
RM21
4.7K_0402_5%
@RM21
4.7K_0402_5%
@
1 2
CM14 0.1U_0402_10V6KCM14 0.1U_0402_10V6K
1 2
RM25
0_0402_5%
RM25
0_0402_5%
12
CM2 4.7U_0603_6.3V6KCM2 4.7U_0603_6.3V6K
1 2
RM17
4.7K_0402_5%
@RM17
4.7K_0402_5%
@
1 2
CM18 0.1U_0402_10V6KCM18 0.1U_0402_10V6K
1 2
RM24
4.7K_0402_5%
@RM24
4.7K_0402_5%
@
1 2
RM16
4.7K_0402_5%
@RM16
4.7K_0402_5%
@
1 2
PS8271QFN48GTR-A1_QFN48_7X7
UHM1
PS8271QFN48GTR-A1_QFN48_7X7
UHM1
IN1_D3p
2
VDD 6
RTERM 7
IN2_D1n
8
IN2_D1p
9
IN2_HPD
10
IN2_D2p
12
IN1_D4p
5
IN1_D3n
1
GND
18
REXT
24
OUT_D4n 27
VDD 31
OUT_D1n 36
OUT_SDA 37
GND
43
IN2_D2n
11
IN2_PEQ
15
SW_MAIN
21
OUT_D4p 26
OUT_D2n 33
DDCBUF 40
IN1_HPD
46
IN1_D4n
4
IN1_PEQ
3
IN2_D3n
13
IN2_D3p
14
IN2_D4n
16
IN2_D4p
17
IN2_SCL
19
IN1_D2p
48 IN1_D2n
47 IN1_D1p
45 IN1_D1n
44
IN1_SDA
42 IN1_SCL
41
OUT_SCL 38
PWDN_ASQ 25
CFG_HPD 28
OUT_D3p 29
OUT_D3n 30
OUT_D2p 32
IN2_SDA
20
SW_DDC
22
CEXT
23
OUT_HPD 39
PRE_EMI 34
OUT_D1p 35
PAD
49
RM13
4.7K_0402_5%
@RM13
4.7K_0402_5%
@
1 2
CM9 0.1U_0402_10V6KCM9 0.1U_0402_10V6K
1 2
RM30 2.2K_0402_5%RM30 2.2K_0402_5%
1 2
CM10 0.1U_0402_10V6KCM10 0.1U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OE# SEL AUX_SEL FUNCTION
L L L PORT A
L L H PORT A-HS, PORT B-HPD/AUX
L H L PORT B-HS, PORT A-HPD/AUX
L
H
H
X
H
X
PORT B
IC POWER DOWN
CPU_EDP_TX0-
CPU_EDP_TX0+
CPU_EDP_AUX#
CPU_EDP_AUX
CPU_EDP_TX1+
CPU_EDP_TX1-
EDP_HPD <34>
EDP_TX0+_C <34>
EDP_TX0-_C <34>
EDP_SEL <15>
EDP_AUX_SEL <16>
EDP_AUX_C <34>
EDP_AUX#_C <34>
CPU_EDP_TX0+<8>
CPU_EDP_TX0-<8>
VGA_EDP_TX0+<24>
VGA_EDP_TX0-<24>
VGA_EDP_AUX<24>
VGA_EDP_AUX#<24>
CPU_EDP_HPD<8>
VGA_EDP_HPD<23>
EDP_TX1+_C <34>
EDP_TX1-_C <34>
CPU_EDP_TX1+<8>
CPU_EDP_TX1-<8>
VGA_EDP_TX1+<24>
VGA_EDP_TX1-<24>
CPU_EDP_AUX<8>
CPU_EDP_AUX#<8>
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
38 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
38 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LVDS/ CMOS/ USB-ReDriver
Custom
38 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RM2
0_0402_5%
RM2
0_0402_5%
12
U79
PI3VDP3212ZLEX_TQFN32_6X3
U79
PI3VDP3212ZLEX_TQFN32_6X3
VDD 3
VDD 9
VDD 12
VDD 16
VDD 20
VDD 29
AUX_SEL 32
D0+A
31
D0-A
30
D1-A
26 D1+A
27
D1+B
23
D1-B
22
D0-B
24 D0+B
25
GND
21
GND
28
D0- 2
D0+ 1
D1+ 4
D1- 5
AUX+ 6
AUX- 7
HPD 8
AUX+A
19
AUX-A
18
HPD_A
17
AUX-B
14 AUX+B
15
HPD_B
13
SEL 10
OE# 11
GPAD
33
CM1184
1U_0603_10V6K
CM1184
1U_0603_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
for NV recommend
SA00004ZB0J
20120829 VA1
Change net name for add HDMI MUX
Close to JHDMI1
VGA_HDMI_DATA
VGA_HDMI_CLK
HDMI_CLK-_CON
HDMI_CLK+_CON
HDMI_TX0-_CON
HDMI_TX0+_CON
HDMI_TX1-_CON
HDMI_TX1+_CON
HDMI_TX2-_CON
HDMI_TX2+_CON
HDMI_DET
HDMI_DET_R
HDMI_TX1-_CON
HDMI_TX2+_CON
HDMI_TX0+_CON
HDMI_TX0-_CON
HDMI_CLK+_CON
HDMI_TX1+_CON
HDMI_TX2-_CON
HDMI_CLK-_CON
VGA_HDMI_DATA
VGA_HDMI_CLK
+5VS_HDMI+CRT_VCC_CON
HDMI_CLK+_CON
HDMI_CLK-_CON
HDMI_TX0-_CON
HDMI_TX0+_CON
HDMI_CLK+_CON
HDMI_CLK-_CON
HDMI_TX0-_CON
HDMI_TX0+_CON
HDMI_TX2-_CON
HDMI_TX2+_CON
HDMI_TX1+_CON
HDMI_TX1-_CON
HDMI_TX2-_CON
HDMI_TX2+_CON
HDMI_TX1+_CON
HDMI_TX1-_CON
VGA_HDMI_CLK
VGA_HDMI_DATA
HDMI_DET
+5VS_HDMI
HDMI_TX1+_R
HDMI_TX2-_R
HDMI_TX1-_R
HDMI_CLK-_R
HDMI_TX2+_R
HDMI_TX0+_R
HDMI_TX0-_R
HDMI_CLK+_R
HDMI_TX1-_CON
HDMI_TX1+_CON
HDMI_TX0+_CON
HDMI_TX0-_CON
HDMI_CLK+_CON
HDMI_TX2-_CON
HDMI_CLK-_CON
HDMI_TX2+_CON
VGA_HDMI_CLK+ HDMI_CLK+_R
VGA_HDMI_TX1-
VGA_HDMI_TX1+
VGA_HDMI_TX2-
VGA_HDMI_TX2+
VGA_HDMI_TX0-
VGA_HDMI_TX0+
HDMI_CLK-_RVGA_HDMI_CLK-
HDMI_TX0-_R
HDMI_TX1-_R
HDMI_TX1+_R
HDMI_TX2-_R
HDMI_TX2+_R
HDMI_TX0+_R
DGPU_HDMI_HPD<23,37>
VGA_HDMI_DATA<37>
VGA_HDMI_CLK<37>
HDMI_CONN_HPD<37>
VGA_HDMI_CLK+<37>
VGA_HDMI_TX1+<37>
VGA_HDMI_TX1-<37>
VGA_HDMI_TX2+<37>
VGA_HDMI_TX2-<37>
VGA_HDMI_TX0+<37>
VGA_HDMI_TX0-<37>
VGA_HDMI_CLK-<37>
+5VS
+5VS
+3VS
+3VS
+CRT_VCC_CON
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI_CONN
Custom
39 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI_CONN
Custom
39 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDMI_CONN
Custom
39 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
R860
2.2K_0402_5%
R860
2.2K_0402_5%
1 2
R303 0_0402_5%R303 0_0402_5%
1 2
R300 0_0402_5%R300 0_0402_5%
1 2
L23
WCM2012F2SF-900T04_4P
L23
WCM2012F2SF-900T04_4P
1
1
4
433
22
R328 100K_0402_5%
@
R328 100K_0402_5%
@
1 2
G
D
S
Q85
2N7002_SOT23
G
D
S
Q85
2N7002_SOT23
2
13
L67
BLM18PG181SN1D_0603
@
L67
BLM18PG181SN1D_0603
@
12
R302 0_0402_5%R302 0_0402_5%
1 2
C659
2200P_0402_50V7K
C659
2200P_0402_50V7K
1
2
C1015 3.3P_0402_50V8C
@
C1015 3.3P_0402_50V8C
@
1 2
R868 0_0402_5%@R868 0_0402_5%@
1 2
R1486
0_0402_5%
R1486
0_0402_5%
1 2
L24
WCM2012F2SF-900T04_4P
L24
WCM2012F2SF-900T04_4P
1
1
4
433
22
C1020 3.3P_0402_50V8C
@
C1020 3.3P_0402_50V8C
@
1 2
D38
BAT54S-7-F_SOT23-3
@
D38
BAT54S-7-F_SOT23-3
@
2
3
1
R1505
0_0402_5%
@
R1505
0_0402_5%
@
12
APL3517AI-TRG_SOT23-3
U78
APL3517AI-TRG_SOT23-3
U78
GND
2
VOUT
3
VIN 1
C1016 3.3P_0402_50V8C
@
C1016 3.3P_0402_50V8C
@
1 2
R304 0_0402_5%R304 0_0402_5%
1 2
R862
1M_0402_5%
R862
1M_0402_5%
1 2
46@
HDMI+HDCP
46@
HDMI+HDCP
R320
499_0402_1%
@
R320
499_0402_1%
@
1 2
R866 0_0402_5%@R866 0_0402_5%@
1 2
R859
1K_0402_5%
@
R859
1K_0402_5%
@
12
D57
AZC099-04S.R7G_SOT23-6
@D57
AZC099-04S.R7G_SOT23-6
@
I/O4 6
VDD 5
I/O3 4
I/O2
3
GND
2
I/O1
1
R325 499_0402_1%@R325 499_0402_1%@
1 2
R327 499_0402_1%@R327 499_0402_1%@
1 2
R323 499_0402_1%@R323 499_0402_1%@
1 2
G
D
S
Q114
2N7002H 1N_SOT23-3
@
G
D
S
Q114
2N7002H 1N_SOT23-3
@
2
13
R305 0_0402_5%R305 0_0402_5%
1 2
C1019 3.3P_0402_50V8C
@
C1019 3.3P_0402_50V8C
@
1 2
R324 499_0402_1%@R324 499_0402_1%@
1 2
C561
0.1U_0402_16V4Z
C561
0.1U_0402_16V4Z
1
2
R885
20K_0402_5%
R885
20K_0402_5%
1 2
JHDMI1
TAITW_PDVBR0-19FLBS4NN4N0
ME@
JHDMI1
TAITW_PDVBR0-19FLBS4NN4N0
ME@
D2+
1D2_shield
2D2-
3D1+
4D1_shield
5D1-
6D0+
7D0_shield
8D0-
9CK+
10 CK_shield
11 CK-
12 CEC
13 Reserved
14 SCL
15 SDA
16 DDC/CEC_GND
17 +5V
18 HP_DET
19
GND 20
GND 21
GND 22
GND 23
8
7
65
4
3
2
1
9
10
D32
AZ1045-04F_DFN2510P10E-10-9
@
8
7
65
4
3
2
1
9
10
D32
AZ1045-04F_DFN2510P10E-10-9
@
4
5
1
6
2
7
3
9
8
R864
100K_0402_5%
@
R864
100K_0402_5%
@
12
C1018 3.3P_0402_50V8C
@
C1018 3.3P_0402_50V8C
@
1 2
L26
WCM2012F2SF-900T04_4P
L26
WCM2012F2SF-900T04_4P
1
1
4
433
22
R869 0_0402_5%@R869 0_0402_5%@
1 2
R326 499_0402_1%@R326 499_0402_1%@
1 2
R865 0_0402_5%@R865 0_0402_5%@
1 2
8
7
65
4
3
2
1
9
10
D33
AZ1045-04F_DFN2510P10E-10-9
@
8
7
65
4
3
2
1
9
10
D33
AZ1045-04F_DFN2510P10E-10-9
@
4
5
1
6
2
7
3
9
8
R870 0_0402_5%@R870 0_0402_5%@
1 2
R1499
0_0402_5%
@
R1499
0_0402_5%
@
1 2
R322 499_0402_1%
@
R322 499_0402_1%
@
1 2
R872 0_0402_5%@R872 0_0402_5%@
1 2
C562
0.1U_0402_16V4Z
C562
0.1U_0402_16V4Z
1
2
L27
WCM2012F2SF-900T04_4P
L27
WCM2012F2SF-900T04_4P
1
1
4
433
22
R307 0_0402_5%R307 0_0402_5%
1 2
R321 499_0402_1%
@
R321 499_0402_1%
@
1 2
R301 0_0402_5%R301 0_0402_5%
1 2
R861
2.2K_0402_5%
R861
2.2K_0402_5%
1 2
C1022 3.3P_0402_50V8C
@
C1022 3.3P_0402_50V8C
@
1 2
R306 0_0402_5%R306 0_0402_5%
1 2
C59
220P_0402_25V8J
@C59
220P_0402_25V8J
@
1
2
C1021 3.3P_0402_50V8C
@
C1021 3.3P_0402_50V8C
@
1 2
R867 0_0402_5%@R867 0_0402_5%@
1 2
C1017 3.3P_0402_50V8C
@
C1017 3.3P_0402_50V8C
@
1 2
R871 0_0402_5%@R871 0_0402_5%@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NGFF(SSD)
Mini-Express Card(WLAN/WiMAX) Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
For EC to detect
debug card insert.
For SSD use:
9/18 Increase for Intel AOAC function
9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function
softstart (RC) will check on EVT PCB
For RF request
For isolate Intel Rainbow Peak and
Compal debug card.
WLAN&BT Combo module circuits
BT on module
Enable
BT on module
Disable
BT_CRTL (GPIO22)
PCH_BT_ON#
H
L
L
H
*
SSD Active:4.5W(1.5A)
For EMI
WLAN_CLKREQ1#
+1.5VS_WLAN
PLT_RST#
SMB_CLK_S3_R
SMB_DATA_S3_R
EC_TX
EC_RX
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
PLT_RST#
CLK_PCI_DB
PCI_RST#_R
SATA_DET#
BT_CTRL_RBT_CTRL
BT_DISABLE#
BT_DISABLE#
BT_CTRL
WL_OFF#
PCIE_WAKE#
SATA_ITX_DRX_N0_R
SATA_ITX_DRX_P0_R
SATA_DTX_IRX_N0_R
SATA_DTX_IRX_P0_R
SATA_ITX_DRX_N0_R
SATA_ITX_DRX_P0_R
CLK_PCI_DB
SATA_DTX_IRX_N0_R
SATA_DTX_IRX_P0_R
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_P0 SATA_DTX_IRX_P0
SATA_DTX_IRX_N0SATA_PRX_DTX_N0
SATA_DTX_IRX_P0_C SATA_DTX_IRX_P0_R
SATA_ITX_DRX_N0_C SATA_ITX_DRX_N0_R
SATA_ITX_DRX_P0_C SATA_ITX_DRX_P0_R
SATA_DTX_IRX_N0_C SATA_DTX_IRX_N0_R
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PTX_C_DRX_P0_R
SATA_PTX_C_DRX_N0_R
SATA_PRX_DTX_P0_R
SATA_PRX_DTX_N0_R
PCIE_WAKE#<15,19,41>
WLAN_CLKREQ1#<16>
USB20_N10 <18>
USB20_P10 <18>
PCH_WL_OFF# <14>
EC_TX<46>
EC_RX<46>
SMB_CLK_S3 <11,12,17,47>
SMB_DATA_S3 <11,12,17,47>
PCIE_PTX_C_DRX_N5<18>
PCIE_PTX_C_DRX_P5<18>
PCIE_PRX_DTX_N5<18>
PCIE_PRX_DTX_P5<18>
LPC_AD2 <17,46>
LPC_AD1 <17,46>
LPC_AD3 <17,46>
LPC_AD0 <17,46>
LPC_FRAME# <17,46>
CLK_PCI_DB <16>
CLK_PCIE_WLAN<16>
SATA_DET#<13>
PLT_RST# <14,23,32,41,46>
AOAC_ON#<46>
PCH_BT_DISABLE#<19>
PCH_BT_ON#<19> SUSP <10,55,61>
LAN_WAKE#<41,46,55>
CLK_PCIE_WLAN#<16>
SATA_PRX_DTX_P0<13>
SATA_PRX_DTX_N0<13>
SATA_PTX_C_DRX_P0<13>
SATA_PTX_C_DRX_N0<13>
SATA_PTX_DRX_P0<13>
SATA_PTX_DRX_N0<13>
+3VS_WLAN
+3VS_WLAN
+3VALW
+3VS_SSD
+1.5VS
+1.5VS
+3VS_WLAN
+3VS
+3VALW
+3VS_WLAN
+3VS_SSD
+3VS
+3VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Mini-Card
C
40 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Mini-Card
C
40 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Mini-Card
C
40 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
J8
JUMP_43X79
@
J8
JUMP_43X79
@
1
122
C568
10U_0805_10V6K
C568
10U_0805_10V6K
1
2
CR2
0.01U_0402_16V7K
@
CR2
0.01U_0402_16V7K
@
1
2
C571 0.01U_0402_16V7KC571 0.01U_0402_16V7K
1 2
R907
0_0402_5%
@
R907
0_0402_5%
@
1 2
C199
10P_0402_50V8J
@C199
10P_0402_50V8J
@
1
2
CR6 0.01U_0402_16V7K
@
CR6 0.01U_0402_16V7K
@
1 2
C1048
0.01U_0402_25V7K
@
C1048
0.01U_0402_25V7K
@
1
2
C569
10U_0805_10V6K
@
C569
10U_0805_10V6K
@
1
2
R889
100K_0402_5%
R889
100K_0402_5%
1 2
G
D
S
Q157B
2N7002KDWH_SOT363-6
@
G
D
S
Q157B
2N7002KDWH_SOT363-6
@
5
34
J5
JUMP_43X79
@
J5
JUMP_43X79
@
1
122
R887
100_0402_1%
R887
100_0402_1%
1 2
JWLN1
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
JWLN1
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
WAKE#
1
NC
3
NC
5
CLKREQ#
7
GND
9
REFCLK-
11
REFCLK+
13
GND
15
NC
17
NC
19
GND
21
PERn0
23
PERp0
25
GND
27
GND
29
PETn0
31
PETp0
33
GND
35
NC
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
GND
53
3.3V 2
GND 4
1.5V 6
NC 8
NC 10
NC 12
NC 14
NC 16
GND 18
NC 20
PERST# 22
+3.3Vaux 24
GND 26
+1.5V 28
SMB_CLK 30
SMB_DATA 32
GND 34
USB_D- 36
USB_D+ 38
GND 40
LED_WWAN# 42
LED_WLAN# 44
LED_WPAN# 46
+1.5V 48
GND 50
+3.3V 52
GND 54
CR4 0.01U_0402_16V7K
@
CR4 0.01U_0402_16V7K
@
1 2
C567
0.1U_0402_16V4Z
C567
0.1U_0402_16V4Z
1
2
RR5
4.7K_0402_5%
@
RR5
4.7K_0402_5%
@
12
RR6
4.7K_0402_5%
@
RR6
4.7K_0402_5%
@
12
R880 0_0402_5%R880 0_0402_5%
1 2
R878 0_0402_5%@R878 0_0402_5%@
1 2
CR1
0.1U_0402_16V4Z
@
CR1
0.1U_0402_16V4Z
@
1
2
C574 0.01U_0402_16V7KC574 0.01U_0402_16V7K
1 2
R400
0_0603_5%
R400
0_0603_5%
12
RR3
4.7K_0402_5%
@
RR3
4.7K_0402_5%
@
12
R879 0_0402_5%@R879 0_0402_5%@
1 2
R873 0_0402_5%@R873 0_0402_5%@
1 2
R881 0_0402_5%@R881 0_0402_5%@
1 2
C570 0.01U_0402_16V7KC570 0.01U_0402_16V7K
1 2
R882 R_short 0_0402_5%R882 R_short 0_0402_5%
1 2
R125 10_0402_5%
@
R125 10_0402_5%
@
1 2
R1620 0_0402_5%@R1620 0_0402_5%@
1 2
R883 0_0402_5%@R883 0_0402_5%@
1 2
C526
0.1U_0402_16V4Z
@
C526
0.1U_0402_16V4Z
@
1
2
RR2
4.7K_0402_5%
@
RR2
4.7K_0402_5%
@
12
C572
0.01U_0402_16V7K
@C572
0.01U_0402_16V7K
@
12
CR3 0.01U_0402_16V7K
@
CR3 0.01U_0402_16V7K
@
1 2
C575 0.01U_0402_16V7KC575 0.01U_0402_16V7K
1 2
G
D
S
Q157A
2N7002KDWH_SOT363-6
@
G
D
S
Q157A
2N7002KDWH_SOT363-6
@
2
61
C573
0.01U_0402_16V7K
@
C573
0.01U_0402_16V7K
@
12
R898 0_0402_5%R898 0_0402_5%
1 2
CR5 0.01U_0402_16V7K
@
CR5 0.01U_0402_16V7K
@
1 2
UR1
PS8520CTQFN20GTR2A0_TQFN20_4X4
@UR1
PS8520CTQFN20GTR2A0_TQFN20_4X4
@
A_INp
1
A_INn
2
NC2 16
A_PRE1
19
B_OUTp
5
VDD1 10
B_PRE0 8
A_PRE0 9
NC1 6
TEST
18
GND2
13 B_INp 11
B_INn 12
B_PRE1
17
A_OUTn 14
A_OUTp 15
VDD2 20
GND1
3
B_OUTn
4
EPAD
21
EN
7
C57
0.047U_0402_16V4Z
@
C57
0.047U_0402_16V4Z
@
1
2
R903 0_0402_5%R903 0_0402_5%
1 2
R896 0_0402_5%
@
R896 0_0402_5%
@
1 2
G
D
S
Q104
AO3413_SOT23-3
AOAC@
G
D
S
Q104
AO3413_SOT23-3
AOAC@
2
13
R1556
1K_0402_5%
COMBT@
R1556
1K_0402_5%
COMBT@
1 2
C566
0.01U_0402_25V7K
C566
0.01U_0402_25V7K
1
2
R884 0_0402_5%@R884 0_0402_5%@
1 2
R875 0_0402_5%@R875 0_0402_5%@
1 2
R904 0_0402_5%R904 0_0402_5%
1 2
R876 0_0402_5%@R876 0_0402_5%@
1 2
13
15
17
19
12
14
16
18
NC
NC
NC
NC
NC
NC
NC
NC
JSSD1
TYCO_2199230-3
ME@
13
15
17
19
12
14
16
18
NC
NC
NC
NC
NC
NC
NC
NC
JSSD1
TYCO_2199230-3
ME@
CONFIG_3
1
GND1
3
GND2
5
USB_D+
7
USBD-
9
GND3
11
CONFIG_0
21
WAKE_ON_WW AN#
23
DPR
25
GND4
27
USB3.0-TX-(Device)
29
USB3.0-TX+(Device)
31
GND5
33
USB3.0-RX-(Device)
35
USB3.0-RX+(Device)
37
GND6
39
PERN0/SATA-B+
41
PERP0/SATA-B-
43
GND7
45
PETN0/SATA-A-
47
PETP0/SATA-A+
49
GND8
51
REFCLKN
53
REFCLKP
55
GND9
57
ANTCTL0
59
ANTCTL1
61
ANTCTL2
63
ANTCTL3
65
RESET#
67
CONFIG_1
69
GND10
71
GND11
73
CONFIG_2
75
3.3VAUX1 2
3.3VAUX2 4
FULL_CARD_POWER_OFF# 6
W_DISABLE#1 8
LED#1/DAS/DSS# 10
GPIO_5 20
GPIO_6 22
GPIO_7 24
W_DISABLE#2 26
UIM-RFU 28
UIM-RESET 30
UIM-CLK 32
UIM-DATA 34
UIM-PWR 36
DEVSLP 38
GPIO_0 40
GPIO_1 42
GPIO_2 44
GPIO_3 46
GPIO_4 48
PERST# 50
CLKREQ# 52
PEWAKE# 54
NC1 56
NC2 58
COEX3 60
COEX2 62
COEX1 64
SIM_DETECT 66
SUSCLK 68
3.3VAUX3 70
3.3VAUX4 72
3.3VAUX5 74
PEG1
76 PEG2 77
RR4
4.7K_0402_5%
@
RR4
4.7K_0402_5%
@
12
R1557
0_0402_5%
COMBT@R1557
0_0402_5%
COMBT@
1 2
C1055
0.1U_0402_16V4Z
C1055
0.1U_0402_16V4Z
1
2
R906
0_0402_5%
@
R906
0_0402_5%
@
12
R897 0_0402_5%
COMBT@
R897 0_0402_5%
COMBT@
1 2
R888
100_0402_1%
R888
100_0402_1%
1 2
R874 0_0402_5%@R874 0_0402_5%@
1 2
R899 0_0402_5%R899 0_0402_5%
1 2
RR1
4.7K_0402_5%
@
RR1
4.7K_0402_5%
@
12
C564
0.1U_0402_16V4Z
@
C564
0.1U_0402_16V4Z
@
1
2
C533
0.1U_0402_16V4Z
AOAC@
C533
0.1U_0402_16V4Z
AOAC@
1
2
R436
100K_0402_5%
AOAC@ R436
100K_0402_5%
AOAC@
1 2
C565
0.1U_0402_16V4Z
@
C565
0.1U_0402_16V4Z
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place Close to PIN1
Place Close to Chip
Vendor recommand reserve the
PU resistor close LAN chip
Near
Pin13
Near
Pin19
Near
Pin31
Close to
Pin40
Note: Place Close to LAN chip
LL1 DCR< 0.15 ohm
Rate current > 1A
Place close to Pin34
Close together
Near
Pin6
RL5
NC = 25MHz
Pull-Down = 48MHz
H --> Overclocking mode
L --> Not overclocking mode
Place Close to PIN10
Optional
Near
Pin37
Place close to Pin16
Near
Pin22
Near
Pin9
QCA8171
QCA8172
Pin17 Pin18 Pin19 Pin20 Pin21
NC NC NC NC NC
LAN_MDI2+ LAN_MDI2- LAN_MDI3+ LAN_MDI3-+1.1_AVDDL
QCA8171/72 Pin defination difference.
QCA8172-AL3A-R_QFN40_5X5
SH00000GT0J
SH00000JM0J
+3VALW_LAN
PLT_RST#
PCIE_WAKE#_R
LAN_XTALO
LAN_XTALI
PCIE_PRX_C_DTX_N4
PCIE_PRX_C_DTX_P4
PLT_RST#
LAN_PWR_ON#
LAN_XTALOLAN_XTALO
LAN_XTALI
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+LX+LX_R+1.1_DVDDL
+1.1_DVDDL+1.1_AVDDL_L +1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
LAN_MDI0-
LAN_MDI1+
LAN_MDI0+
LAN_MDI2-
LAN_MDI1-
LAN_MDI2+
LAN_MDI3-
LAN_MDI3+
LAN_CLK_SEL
LAN_LINK#
LAN_ACTIVITY#
LAN_RBIAS
+LX
+AVDD3.3
+AVDD3.3
DEBUGMODE
+1.1_DVDDL
+2.7_AVDDH
CLKREQ_LAN#<16>
PCIE_PTX_C_DRX_P4<18>
PCIE_PTX_C_DRX_N4<18>
PCIE_PRX_DTX_N4<18>
PCIE_PRX_DTX_P4<18>
CLK_PCIE_LAN#<16>
CLK_PCIE_LAN<16>
PCIE_WAKE#<15,19,40>
LAN_WAKE#<40,46,55>
PLT_RST#<14,23,32,40,46>
LAN_PWR_ON#<46>
LAN_MDI2+ <42>
LAN_MDI2- <42>
LAN_MDI1+ <42>
LAN_MDI3+ <42>
LAN_MDI1- <42>
LAN_MDI0+ <42>
LAN_MDI0- <42>
LAN_MDI3- <42>
LAN_ACTIVITY# <42>
LAN_LINK# <42>
+3VALW_LAN
+3VALW_LAN
+3VALW_LAN
+3VALW
+LX
+LX +3VS
+3VALW_LAN
+3VALW_LAN
+3VALW_LAN
+3VALW_LAN
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN_QCA8171
Custom
41 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN_QCA8171
Custom
41 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN_QCA8171
Custom
41 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CL52
0.1U_0402_16V4Z
CL52
0.1U_0402_16V4Z
1
2
CL49
10U_0805_10V4Z
@CL49
10U_0805_10V4Z
@
1
2
CL39
0.1U_0402_16V4Z
CL39
0.1U_0402_16V4Z
1
2
CL40
0.1U_0402_16V4Z
CL40
0.1U_0402_16V4Z
1
2
CL59
1U_0402_6.3V4Z
CL59
1U_0402_6.3V4Z
1
2
CL38
10U_0805_10V4Z
CL38
10U_0805_10V4Z
1
2
CL54
0.1U_0402_16V4Z
CL54
0.1U_0402_16V4Z
1
2
RL11 0_0603_5%RL11 0_0603_5%
1 2
G
D
S
QL1
LP2301ALT1G_SOT-23
G
D
S
QL1
LP2301ALT1G_SOT-23
2
13
RL7 0_0402_5%
@
RL7 0_0402_5%
@
1 2
CL41
1U_0402_6.3V4Z
CL41
1U_0402_6.3V4Z
1
2
CL63
15P_0402_50V8J
CL63
15P_0402_50V8J
1
2
CL50
0.1U_0402_16V4Z
CL50
0.1U_0402_16V4Z
1
2
RL6 0_0402_5%RL6 0_0402_5%
1 2
CL34
0.1U_0402_16V4Z
@
CL34
0.1U_0402_16V4Z
@1
2
CL58
0.1U_0402_16V4Z
CL58
0.1U_0402_16V4Z
1
2
RL9 30K_0402_5%
@
RL9 30K_0402_5%
@
1 2
RL2 0_0603_5%RL2 0_0603_5%
1 2
CL55
0.1U_0402_16V4Z
CL55
0.1U_0402_16V4Z
1
2
CL57
0.1U_0402_16V4Z
CL57
0.1U_0402_16V4Z
1
2
CL45
1000P_0402_50V7K
@
CL45
1000P_0402_50V7K
@
1 2
RL5 10K_0402_5%
@
RL5 10K_0402_5%
@
12
CL62
15P_0402_50V8J
CL62
15P_0402_50V8J
1
2
CL43 0.1U_0402_16V7KCL43 0.1U_0402_16V7K
1 2
CL53
1U_0402_6.3V4Z
CL53
1U_0402_6.3V4Z
1
2
RL10 30K_0402_5%RL10 30K_0402_5%
1 2
CL60
0.1U_0402_16V4Z
CL60
0.1U_0402_16V4Z
1
2
CL61
1U_0402_6.3V4Z
CL61
1U_0402_6.3V4Z
1
2
CL37
0.1U_0402_16V4Z
CL37
0.1U_0402_16V4Z
1
2
RL8 2.37K_0402_1%RL8 2.37K_0402_1%
1 2
CL56
1U_0402_6.3V4Z
CL56
1U_0402_6.3V4Z
1
2
J16
JUMP_43X79
@
J16
JUMP_43X79
@
1
122
Atheros
QCA8171
UL1
QCA8171-BL3A-R_QFN40_5X5
Atheros
QCA8171
UL1
QCA8171-BL3A-R_QFN40_5X5
35 RX_P
1
VDD33
30 TX_P
29 TX_N
36 RX_N
11
TRXP0
12
TRXN0
14
TRXP1
15
TRXN1
10
RBIAS
40
LX
38
LED_0 39
LED_1
28 NC
27 TESTMODE_2
25 TESTMODE_0
26 TESTMODE_1
3WAKE#
2PERST#
23
LED_2
33 REFCLK_P
32 REFCLK_N
31 AVDDL
34 AVDDL
6AVDDL_REG
22
AVDDH 9
AVDDH_REG
24
PPS 37
DVDDL_REG
5
DEBUGMODE
4CLKREQ#
41 GND
7XTLO
8XTLI
16
AVDD33
17
TRXP2
18
TRXN2
19 AVDDL
20
TRXP3
21
TRXN3
13 AVDDL
RL17 4.7K_0402_5%@RL17 4.7K_0402_5%@
1 2
RL16 4.7K_0402_5%
@
RL16 4.7K_0402_5%
@
1 2
LL1
4.7UH +-20% PCAA041B-4R7M 1.1A
LL1
4.7UH +-20% PCAA041B-4R7M 1.1A
1 2
CL46
0.1U_0402_16V4Z
CL46
0.1U_0402_16V4Z
1
2
LL2
FBMA-L11160808601LMA10T_2P
LL2
FBMA-L11160808601LMA10T_2P
1 2
YL7
25MHZ_10PF_7V25000014
YL7
25MHZ_10PF_7V25000014
GND
2
33
1
1
GND
4
RL4 4.7K_0402_5%
@
RL4 4.7K_0402_5%
@
1 2
CL35
0.01U_0402_25V7K
@
CL35
0.01U_0402_25V7K
@
1
2
CL51
0.1U_0402_16V4Z
CL51
0.1U_0402_16V4Z
1
2
CL36
1000P_0402_50V7K
@CL36
1000P_0402_50V7K
@
CL42
4.7U_0603_6.3V6K
CL42
4.7U_0603_6.3V6K
1
2
LL3
FBMA-L11160808601LMA10T_2P
LL3
FBMA-L11160808601LMA10T_2P
1 2
CL44 0.1U_0402_16V7KCL44 0.1U_0402_16V7K
1 2
CL48
10U_0805_10V4Z
CL48
10U_0805_10V4Z
1
2
RL3
100K_0402_5%
RL3
100K_0402_5%
12
CL47
1U_0402_6.3V4Z
CL47
1U_0402_6.3V4Z
1
2
UL1
SA00006540J
@
UL1
SA00006540J
@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place CL33 close to TL1CL69 reserved for EMI,
place close to TL1
350UH_NS892405
JP/N
placement
DL3, DL4 Reserve for Surge
Place Close to TL1
FL1 ~ FL4 Reserve for Serge Line to GND
FL3 change to BS4200N for ESD request
RJ45_MIDI0-
RJ45_MIDI0+
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI1-
RJ45_MIDI3+
RJ45_MIDI3-
RJ45_MIDI1+
LAN_LINK#
LAN_ACTIVITY#
MCT0
MCT1
MCT2
LAN_ACTIVITY#
LAN_LINK#
TCT
MCT3
MCT2
MCT1
MCT0
LAN_MDI0-
LAN_MDI0+ RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI3-
RJ45_MIDI3+
RJ45_MIDI2-
RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI1-
LAN_MDI1+
LAN_MDI3-
LAN_MDI3+
LAN_MDI2-
LAN_MDI2+
LAN_MDI1-
LAN_MDI0+
LAN_MDI0-
LAN_MDI1-
LAN_MDI1+
LAN_MDI2+
LAN_MDI2-
LAN_MDI3+
LAN_MDI3-
MCT3
LAN_ACTIVITY#<41>
LAN_LINK#<41>
LAN_MDI0+<41>
LAN_MDI0-<41>
LAN_MDI3+<41>
LAN_MDI3-<41>
LAN_MDI2+<41>
LAN_MDI2-<41>
LAN_MDI1+<41>
LAN_MDI1-<41>
+3VALW_LAN
+3VALW_LAN
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN Transformer
Custom
42 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN Transformer
Custom
42 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LAN Transformer
Custom
42 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CL75 0.1U_0402_16V4ZCL75 0.1U_0402_16V4Z
12
FL5
BS401N 1206
SURGE@
FL5
BS401N 1206
SURGE@
1 2
CL66
10P_1206_2KV7K
CL66
10P_1206_2KV7K
1
2
RL15
75_0402_1%
RL15
75_0402_1%
12
CL33
1U_0402_10V6K
CL33
1U_0402_10V6K
1
2
FL4
BS401N 1206
SURGE@
FL4
BS401N 1206
SURGE@
1 2
DL3
TCLAMP3302N.TCT_SLP2626P10-10
@
DL3
TCLAMP3302N.TCT_SLP2626P10-10
@
1
1
2
2
3
3
4
4
5
566
77
88
99
10 10
GND
11
FL2
BS401N 1206
SURGE@
FL2
BS401N 1206
SURGE@
1 2
DL4
TCLAMP3302N.TCT_SLP2626P10-10
@
DL4
TCLAMP3302N.TCT_SLP2626P10-10
@
1
1
2
2
3
3
4
4
5
566
77
88
99
10 10
GND
11
CL65
470P_0402_50V7K
@
CL65
470P_0402_50V7K
@1
2
RL18
R_short 0_0805_5%
RL18
R_short 0_0805_5%
1 2
CL64
470P_0402_50V7K
@
CL64
470P_0402_50V7K
@1
2
TL1
SP05000650J
@
TL1
SP05000650J
@
RL19
R_short 0_0805_5%
RL19
R_short 0_0805_5%
1 2
JRJ45
SANTA_130456-111
ME@
JRJ45
SANTA_130456-111
ME@
PR4+
7
PR4-
8
PR2-
6
PR3-
5
PR3+
4
PR2+
3
PR1-
2
PR1+
1
Green LED-
9
Green LED+
10
Yellow LED-
11
Yellow LED+
12
G1 13
G2 14
FL1
BS401N 1206
SURGE@
FL1
BS401N 1206
SURGE@
1 2
RL12
R_short 0_0805_5%
RL12
R_short 0_0805_5%
1 2
RL14 220_0402_5%RL14 220_0402_5%
1 2
FL3
BS4200N-C-LV_SMB-F2
FL3
BS4200N-C-LV_SMB-F2
1
122
CL73 0.1U_0402_16V4ZCL73 0.1U_0402_16V4Z
12
CL74 0.1U_0402_16V4ZCL74 0.1U_0402_16V4Z
12
1:1
1:1
1:1
1:1
TL1
350UH_NS892407
1:1
1:1
1:1
1:1
TL1
350UH_NS892407
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD2+
5
TD2-
6
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12 MX4- 13
MX3- 16
MCT3 18
MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
MX4+ 14
MCT4 15
MX3+ 17
RL20
R_short 0_0805_5%
RL20
R_short 0_0805_5%
1 2
CL69
0.1U_0402_16V4Z
@CL69
0.1U_0402_16V4Z
@1
2
RL13 220_0402_5%RL13 220_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close to SSD side
Under VRAM
FAN1 Conn
REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
SMSC thermal sensor
placed near by VRAM
internal pull up 1.2K to 1.5V
R for initial thermal
shutdown temp
FAN_PWM & TACH
for PWM FAN
Close U29
Address 1001_101xb
Remove +VDD netname
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
REMOTE1-
REMOTE1+
REMOTE2-
REMOTE2+
EC_SMB_DA2
REMOTE2+
REMOTE2-
REMOTE1+
REMOTE1-
EC_SMB_CK2 EC_SMB_CK2 <17,23,32,34,36,46>
EC_SMB_DA2 <17,23,32,34,36,46>
EC_FAN_PWM<46>
EC_FAN_SPEED<46>
+5VS
+3VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA Thermal sensor/FAN CONN
Custom
43 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA Thermal sensor/FAN CONN
Custom
43 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA Thermal sensor/FAN CONN
Custom
43 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
C986
10U_0805_10V6K
C986
10U_0805_10V6K
1
2
JFAN1
ACES_85205-04001
ME@
JFAN1
ACES_85205-04001
ME@
1
1
2
2
3
3
G5
5
G6
6
4
4
U29
EMC1403-2-AIZL-TR_MSOP10
U29
EMC1403-2-AIZL-TR_MSOP10
DN1
3
DP1
2
VDD
1
GND 6
ALERT# 8
DP2
4
DN2
5
THERM# 7
SMDATA 9
SMCLK 10
C984
100P_0402_50V8J
@
C984
100P_0402_50V8J
@
1
2
C49
0.1U_0402_10V7K
@C49
0.1U_0402_10V7K
@
1
2
C982
100P_0402_50V8J
@
C982
100P_0402_50V8J
@
1
2
R624
10K_0402_5%
@
R624
10K_0402_5%
@
12
E
B
C
Q137
MMST3904-7-F_SOT323-3
E
B
C
Q137
MMST3904-7-F_SOT323-3
2
3 1
C658
2200P_0402_50V7K
C658
2200P_0402_50V7K
1
2
C449
2200P_0402_50V7K
C449
2200P_0402_50V7K
1
2
E
B
C
Q138
MMST3904-7-F_SOT323-3
E
B
C
Q138
MMST3904-7-F_SOT323-3
2
3 1
C443
0.1U_0402_16V4Z
C443
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
SATA HDD Conn.
ODD Power Control
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
SATA ODD Conn.
+5VS_HDD
SATA_PRX_DTX_P1
SATA_PRX_C_DTX_N1SATA_PRX_DTX_N1
SATA_PRX_C_DTX_P1
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
ODD_EN#
ODD_EN#
ODD_DA#
HDD_PWR_DET#
HDD_PWR_DET#
ODD_EN<19>
ODD_DA#_R<14>
SATA_PTX_C_DRX_P1<13>
SATA_PRX_DTX_N1<13>
SATA_PRX_DTX_P1<13>
SATA_PTX_C_DRX_N1<13>
SATA_PTX_C_DRX_P2<13>
SATA_PTX_C_DRX_N2<13>
SATA_PRX_DTX_P2<13>
SATA_PRX_DTX_N2<13>
SLI_FAN_SPEED<32,46>
ODD_DETECT#<19>
SLI_FAN_PWM<32,46>
+5VS
+5VALW +5VS
+5VS
+5VS_ODD
+3VS
+5VS_ODD
+5VS_ODD
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDD/ODD CONN
Custom
44 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDD/ODD CONN
Custom
44 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HDD/ODD CONN
Custom
44 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
C637
0.1U_0402_16V4Z
C637
0.1U_0402_16V4Z
1
2
R1494 R_short 0_0402_5%R1494 R_short 0_0402_5%
1 2
G
D
S
Q88 AO3413_SOT23-3
G
D
S
Q88 AO3413_SOT23-3
2
13
C631
1000P_0402_50V7K
C631
1000P_0402_50V7K
1
2
R923
100K_0402_5% @
R923
100K_0402_5% @
12
R1504 0_0402_5%R1504 0_0402_5%
1 2
C632
0.1U_0402_16V4Z
C632
0.1U_0402_16V4Z
1
2
R1476 0_0402_5%@R1476 0_0402_5%@
1 2
C628 0.01U_0402_16V7KC628 0.01U_0402_16V7K
1 2
C639
10U_0603_6.3V6M
C639
10U_0603_6.3V6M
1
2
J12
JUMP_43X79
@J12
JUMP_43X79
@
1
122
C1049
0.1U_0402_16V4Z @
C1049
0.1U_0402_16V4Z @
1
2
R1497 0_0402_5%@R1497 0_0402_5%@
1 2
G
D
S
Q89
2N7002KW_SOT323-3
G
D
S
Q89
2N7002KW_SOT323-3
2
13
R1479 R_short 0_0402_5%R1479 R_short 0_0402_5%
1 2
R1478
100K_0402_5%
R1478
100K_0402_5%
12
C633
1U_0603_10V4Z
C633
1U_0603_10V4Z
1
2
JODD2
SANTA_202404-1
ME@JODD2
SANTA_202404-1
ME@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
DP
8
+5V
9
+5V
10
MD
11
GND
12
GND
13 GND 14
GND 15
C1057
0.01U_0402_16V7K
C1057
0.01U_0402_16V7K
1
2
C634
10U_0603_6.3V6M
C634
10U_0603_6.3V6M
1
2
G
D
S
Q90
2N7002KW_SOT323-3
@
G
D
S
Q90
2N7002KW_SOT323-3
@
2
13
JHDD1
SANTA_191201-1
ME@
JHDD1
SANTA_191201-1
ME@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
V33
8
V33
9
V33
10
GND
11
GND
12
GND
13
V5
14
V5
15
V5
16
GND
17
Reserved
18
GND
19
V12
20
V12
21
V12
22 GND 23
GND 24
C627 0.01U_0402_16V7KC627 0.01U_0402_16V7K
1 2
R1477
470_0603_5%
@R1477
470_0603_5%
@
12
R1110
100K_0402_5%
R1110
100K_0402_5%
12
C635
10U_0603_6.3V6M
C635
10U_0603_6.3V6M
1
2
C629 0.01U_0402_16V7KC629 0.01U_0402_16V7K
1 2
C638
0.01U_0402_16V7K@
C638
0.01U_0402_16V7K@
1
2
R1496
100K_0402_5%
R1496
100K_0402_5%
12
C630 0.01U_0402_16V7KC630 0.01U_0402_16V7K
1 2
R921 10K_0402_5%R921 10K_0402_5%
1 2
R710 0_0402_5%@R710 0_0402_5%@
1 2
J6
JUMP_43X79
@J6
JUMP_43X79
@
1
122
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPEAKER-OUT (pin-43/44/45/46_Port D)
Pin Assignment Function
Internal
External Line in LINE1 (pin-21/22_Port C)
Mic inMIC1 (pin-19/20_Port B) External
MIC2 (pin-17/18_Port F)
Location
ALC282 Configuation - example
4 external jacks: Line-in / Mic-in / Hp-out / SPDIF-OUT
Internal speaker
Internal Stereo DMIC
NC
Internal Speaker
Cap-Saving HP-OUT (pin-32/33_Port I) External Headphone out
AGND
DGND
Tied at one point only under
the codec or near the codec
InternalDMIC1/2 (pin-2/3) Internal Mic ( Digital MIC )
MONO-OUT (pin-16) NC
If AVDD2 is design to 1.5V, you will get better
power consumption.
Place close to pin 1
place close to pin 13
Place close to Pin 34/35/36
Place close to Pin 34/35/36
Place close
to pin 9
Place close to Pin 26
Place close to Pin 28
PCH Beep
PC Beep
EC Beep
10 mils
Ext. MIC
10 mils
10 mils
30 mils
30 mils
For EMI
Reserve for ESD request.
2009/11/02 Modify
P/N chang to 0 ohm to B phase
+3.3VD
+5VA
+5VD
+CPVDD
+AVDD2
+3.3VD
+CPVDD
+AVDD2
+5VA
+5VD
HDA_SDIN0_R
+5VD
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
PC_BEEPPC_BEEP1
PC_BEEP
HPOUTL_R HP_OUTL
HPOUTR_R HP_OUTR
SPDIF_OUT
HDA_SDIN0
DMIC_CLK_R
DMIC_DATA_RDMIC_DATA
DMIC_CLK
DMIC_CLK_R
DMIC_DATA_R
SPKOUT_R2-
SPK_R1SPKOUT_R1+
SPK_L2SPKOUT_L2-
SPK_L1SPKOUT_L1+
SPK_R2
SPKOUT_L1+
SPKOUT_L2-
SPKOUT_R2-
SPKOUT_R1+
C_MIC1_LMIC1_L
C_MIC1_RMIC1_R
HDA_SYNC_AUDIO_R
HDA_SDOUT_AUDIO_R
HDA_BITCLK_AUDIO_R
A_PDB
HDA_BITCLK_AUDIO_R
A_PDB
SPK_R1
SPK_R2
SPK_L1
SPK_L2
HDA_BITCLK_AUDIO<13>
HDA_SDOUT_AUDIO<13>
HDA_SYNC_AUDIO<13>
BEEP#<46>
HDA_SPKR<13>
HDA_RST_AUDIO#<13>
HP_OUTL <50>
HP_OUTR <50>
SPDIF_OUT <50>
MIC_JD<50>
PLUG_IN<50>
HDA_SDIN0<13>
DMIC_DATA<35>
DMIC_CLK<35>
MIC1_L<50>
MIC1_R<50>
EC_MUTE#<46>
+3VS
+5VS
+1.5VS
+3VS
+1.5VS
+3.3VD
+3.3VD
+MIC1_VREFO_L
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Audio Codec
C
45 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Audio Codec
C
45 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Audio Codec
C
45 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
CA1382
0.1U_0402_16V4Z
CA1382
0.1U_0402_16V4Z
1
2
CA1390
2.2U_0603_10V6K
CA1390
2.2U_0603_10V6K
1
2
RA165620K_0402_1% RA165620K_0402_1%
1 2
RA4
33_0402_5%
RA4
33_0402_5%
1 2
CA10 1000P_0402_50V7K~N@CA10 1000P_0402_50V7K~N@
1 2
CA1396
10P_0402_50V8J
@
CA1396
10P_0402_50V8J
@
1
2
CA12792.2U_0603_6.3V6K CA12792.2U_0603_6.3V6K
1 2
R956 0_0402_5%R956 0_0402_5%
1 2
LA63
FBMA-10-100505-301T_2P
LA63
FBMA-10-100505-301T_2P
1 2
CA23 0.1U_0402_16V4ZCA23 0.1U_0402_16V4Z
1 2
R126 10_0402_5%
@
R126 10_0402_5%
@
1 2
CA12802.2U_0603_6.3V6K CA12802.2U_0603_6.3V6K
1 2
CA9 1000P_0402_50V7K~N@CA9 1000P_0402_50V7K~N@
1 2
CA24 0.1U_0402_16V4ZCA24 0.1U_0402_16V4Z
1 2
RA1659 0_0402_5%
@
RA1659 0_0402_5%
@
1 2
CA1395
10U_0805_10V4Z
CA1395
10U_0805_10V4Z
1
2
RA1652
10_0402_5%
RA1652
10_0402_5%
1 2
DA2
AZ5125-02S.R7G_SOT23-3
@DA2
AZ5125-02S.R7G_SOT23-3
@
2
3
1
DA1
AZ5125-02S.R7G_SOT23-3
@DA1
AZ5125-02S.R7G_SOT23-3
@
2
3
1
RA1648 0_0402_5%
@
RA1648 0_0402_5%
@
1 2
CA1392 10U_0805_10V4ZCA1392 10U_0805_10V4Z
1 2
R438
100K_0402_5%
R438
100K_0402_5%
1 2
CA1387
0.1U_0402_16V4Z
CA1387
0.1U_0402_16V4Z
1
2
CA1381
10U_0603_6.3V6M
CA1381
10U_0603_6.3V6M
1
2
R957 0_0402_5%R957 0_0402_5%
1 2
CA11 1000P_0402_50V7K~N@CA11 1000P_0402_50V7K~N@
1 2
CA1386
10U_0805_10V4Z
CA1386
10U_0805_10V4Z
1
2
UA1
ALC282-CG_MQFN48_6X6
UA1
ALC282-CG_MQFN48_6X6
DVDD
1
GPIO0/DMIC-DATA
2
GPIO1/DMIC-CLK
3
DVSS 4
SDATA-OUT
5
BCLK
6
LDO3-CAP 7
SDATA-IN
8
DVDD-IO
9
SYNC
10
RESETB
11
PCBEEP
12
Sense A
13
Sense B
14
JDREF 15
MONO-OUT 16
MIC2-L(PORT-F-L)
17
MIC2-R(PORT-F-R)
18
MIC1-L(PORT-B-L)
19
MIC1-R(PORT-B-R)
20
LINE1-R(PORT-C-R)
21 LINE1-L(PORT-C-L)
22
LINE2-R(PORT-E-R)
23 LINE2-L(PORT-E-L)
24
AVSS1 25
AVDD1
26
LDO1-CAP 27
VREF 28
MIC2-VREFO 29
MIC1-VREFO-R 30
MIC1-VREFO-L 31
HPOUT-L(PORT-I-L) 32
HPOUT-R(PORT-I-R) 33
CPVEE 34
CBN 35
CPVDD
36
CBP 37
AVSS2 38
LDO2-CAP 39
AVDD2
40
PVDD1
41
SPK-OUT-L+ 42
SPK-OUT-L- 43
SPK-OUT-R- 44
SPK-OUT-R+ 45
PVDD2
46
PDB
47
SPDIF-OUT/GPIO2 48
Thermal Pad 49
CA1379
10U_0805_10V4Z
CA1379
10U_0805_10V4Z
1
2
RA56 0_0603_5%
RA56 0_0603_5%
1 2
CA1393 10U_0805_10V4ZCA1393 10U_0805_10V4Z
1 2
CA12 1000P_0402_50V7K~N@CA12 1000P_0402_50V7K~N@
1 2
CA1377
10U_0805_10V4Z
CA1377
10U_0805_10V4Z
1
2
R5 60.4_0402_1%R5 60.4_0402_1%
12
RA61 0_0603_5%
RA61 0_0603_5%
1 2
CA1383
10U_0805_10V4Z
CA1383
10U_0805_10V4Z
12
RA1653
10_0402_5%
RA1653
10_0402_5%
1 2
RA1660
0_0402_5%
RA1660
0_0402_5%
1 2
RA1658 0_0402_5%RA1658 0_0402_5%
1 2
JSPK1
ACES_85205-04001
ME@
JSPK1
ACES_85205-04001
ME@
1
1
2
2
3
3
G5
5
G6
6
4
4
LA62
FBMA-10-100505-301T_2P
LA62
FBMA-10-100505-301T_2P
1 2
R437
100K_0402_5%
@
R437
100K_0402_5%
@
12
RA1657
33_0402_5%
RA1657
33_0402_5%
12
CA1399
10P_0402_50V8J
CA1399
10P_0402_50V8J
1
2
LA65
FBMA-10-100505-301T_2P
LA65
FBMA-10-100505-301T_2P
1 2
RA1650 20K_0402_1%RA1650 20K_0402_1%
12
R10 60.4_0402_1%R10 60.4_0402_1%
12
R946
FBMA-10-100505-301T_2P
R946
FBMA-10-100505-301T_2P
1 2
CA1398
10P_0402_50V8J
CA1398
10P_0402_50V8J
1
2
CA1380
0.1U_0402_16V4Z
CA1380
0.1U_0402_16V4Z
1
2
RA1651
10_0402_5%
RA1651
10_0402_5%
1 2
LA64
FBMA-10-100505-301T_2P
LA64
FBMA-10-100505-301T_2P
1 2
RA3
10K_0402_5%
@RA3
10K_0402_5%
@
12
C200
10P_0402_50V8J
@C200
10P_0402_50V8J
@
1
2
LA66
FBMA-10-100505-301T_2P
LA66
FBMA-10-100505-301T_2P
1 2
CA1384
0.1U_0402_16V4Z
CA1384
0.1U_0402_16V4Z
1
2
CA1385
10U_0805_10V4Z
CA1385
10U_0805_10V4Z
1
2
CA1378
0.1U_0402_16V4Z
CA1378
0.1U_0402_16V4Z
1
2
CA1397
10P_0402_50V8J
CA1397
10P_0402_50V8J
1
2
CA1391 2.2U_0603_10V6KCA1391 2.2U_0603_10V6K
12
RA60 0_0603_5%
RA60 0_0603_5%
1 2
CA1388
0.1U_0402_16V4Z
CA1388
0.1U_0402_16V4Z
1
2
CA1394 10U_0805_10V4ZCA1394 10U_0805_10V4Z
1 2
RA58 0_0603_5%
RA58 0_0603_5%
1 2
RA1649
R_short 0_0402_5%
RA1649
R_short 0_0402_5%
1 2
RA165439.2K_0402_1% RA165439.2K_0402_1%
1 2
CA1389 2.2U_0603_10V6KCA1389 2.2U_0603_10V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close EC
minimum trace width 12 mil
All capacitors close to EC
EMC Request
Need to check which SMBus can be use for debug
20120730 VA
Reserved hardware
strapping for Auto load
code
For ESD For EMI
For factory EC flash
PLT_RST#
KBRST#
LPC_AD2
LPC_FRAME#
LPC_AD3
LPC_AD1
LPC_AD0
SERIRQ
CLK_PCI_EC
EC_SCI#
EC_SMI#
GATEA20
KSO2
KSO4
KSO3
KSO1
KSO0
KSO8
KSO7
KSO6
KSO5
KSO9
KSO10
KSO13
KSO12
KSO11
KSO14
KSO15
KSI0
KSI2
KSI5
KSI4
KSI1
KSI3
KSI6
KSI7
EC_SMB_DA1
EC_SMB_CK1
VCOREVCC
WRST#
SUSP#
BATT_TEMP
EC_LID_OUT#
SYSON
DPWROK_EC
SYSON
EC_AGND
+3VALW_R
PBTN_OUT#
BEEP#
TP_CLK
TP_DATA
PWR_LED#
BATT_CHG_LED#
BATT_LOW_LED#
BATT_TEMP
ADP_I
IMVP_IMON
EC_FAN_SPEED
EC_FAN_PWM
CAPS_LED#
AOAC_ON#
LED_KB_PWM
SLI_FAN_SPEED
EC_TX
EC_RX
PM_SLP_S3#
PM_SLP_S4#
USB_ON#
USB_CH
EC_RSMRST#
PCH_PWROK
ACPRN
LID_SW#
SUSACK#
PM_SLP_SUS#
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2
EC_SMB_CK2
SLI_FAN_PWM
TURBO_V
SUSWARN#
USB_ON#
TP_DATA
TP_CLK
USB_CH
LPC_FRAME#
EC_FAN_PWM
LAN_WAKE#
EC_FAN_SPEED
H_PROCHOT#_EC
BKOFF#
KSO[0..17]
KSI[0..7]
ACPRN
BATT_LEN#
AD_ID
PCH_PWR_EN
KSO16
KSO17
EC_SPI_SI
EC_SPI_SO_L
EC_SPI_CLK
EC_SPI_CS1#
ACPRN
ENBKL
VR_ON
AC_PRESENT_R
EC_GPO7
LAN_PWR_ON#
PECI_EC
EC_SMB_CK2
EC_SMB_DA2
VGA_AC_DET
AC_PRESENTAC_PRESENT_R
EC_GPO7
SUSP#
TP_LED#
NOVO#
SPI_SI_R1
SPI_CLK_PCH_1
SPI_SO_L1
EC_SPI_CS1#
EC_SPI_CLK
EC_SPI_SO_L
EC_SPI_SI
SPI_CS1#_R
PLT_RST#
CLK_PCI_EC
ON/OFF
BKOFF#
LID_SW#
ACPRN
DRAMRST_CNTRL_EC
NTC_V
VDDQ_PGOOD
H_PROCHOT#_EC
MAINPWON_EC
LAN_WAKE#
EC_GPO7
AC_PRESENT_R
EC_MUTE#
ENBKL
ACOFF
ME_FLASH
DRAMRST_CNTRL_EC
NUM_LED#
SYSON
EXIO_DATA
EXIO_CS
EXIO_CLK
SLI_FAN_SPEED
EC_ON
EC_GPO7 SUS_VCCP
EC_SMB_CK1
WRST#
EC_SMB_DA1
KSI7
KSI6
EXIO_CS
LPC_FRAME#<17,40>
LPC_AD2<17,40>
LPC_AD1<17,40>
LPC_AD3<17,40>
LPC_AD0<17,40>
SERIRQ<17>
CLK_PCI_EC<16>
PLT_RST#<14,23,32,40,41>
EC_SMB_CK1<57,58>
EC_SMB_DA1<57,58>
EC_LID_OUT#<19>
DPWROK_EC<15>
TP_CLK <47>
PWR_LED# <51,52>
BATT_CHG_LED# <51>
BATT_LOW_LED# <51>
BATT_TEMP <57>
IMVP_IMON <64>
EC_FAN_SPEED <43>
EC_FAN_PWM <43>
ADP_I <57,58>
TP_DATA <47>
PBTN_OUT# <15>
BEEP# <45>
CAPS_LED# <51>
AOAC_ON# <40>
LED_KB_PWM <47>
SLI_FAN_SPEED <32,44>
EC_TX<40>
EC_RX<40>
PM_SLP_S3# <15>
PM_SLP_S4# <15>
USB_ON#<49>
USB_CH <50>
EC_RSMRST#<15>
PCH_PWROK <15>
ACPRN <58>
LID_SW# <47>
ON/OFF<52>
SUSACK# <15>
SLI_FAN_PWM <32,44>
TURBO_V <57>
SUSWARN# <15>
LAN_WAKE# <40,41,55>
H_PROCHOT# <57,6>
BKOFF# <35>
KSO[0..17]<47>
KSI[0..7]<47>
EC_SMI#<19>
BATT_LEN# <57>
AD_ID <57>
PCH_PWR_EN <55,57>
PM_SLP_SUS# <15,55>
KBRST#<19>
GATEA20<19>
EC_SCI#<19>
VR_HOT#<64>
VR_ON<64>
EXIO_CLK <54>
EXIO_CS <54>
EXIO_DATA <54>
LAN_PWR_ON#<41>
H_PECI<6>
EC_SMB_CK2<17,23,32,34,36,43>
EC_SMB_DA2<17,23,32,34,36,43>
WRST#<54>
VGA_AC_DET <23>
AC_PRESENT <15>
CPU1.5V_S3_GATE <10>
SUSP# <32,55,60,61,62>
TP_LED# <51>
NOVO# <52>
SPI_CS1#_R <17>
SPI_SO_L1 <17>
SPI_SI_R1 <17>
SPI_CLK_PCH_1 <17>
NTC_V <57>
VDDQ_PGOOD <60>
PROCHOT# <57>
MAINPWON <57,59>
EC_MUTE# <45>
ENBKL <35>
ACOFF <58>
ME_FLASH <13>
DRAMRST_CNTRL_EC <6>
NUM_LED# <51>
SYSON <60>
EC_ON <52,59>
SUS_VCCP <62>
+3VALW_R
+3VS
+RTCBATT
+3VS +3VALW_EC
+3VALW_R
+3VALW
+3VALW_R +3VALW_EC
EC_AGND
+3VLP
+3VALW_R
+3VS
+3VS
+3VS
+3VS
+5VALW
+3VALW_R
+3VS
+3VLP
+3VS
+3VL
+3VL
+3VALW_R
+3VALW_R
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EC ITE8586LQFP
C
46 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EC ITE8586LQFP
C
46 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EC ITE8586LQFP
C
46 69
Wednesday, March 27, 2013
2012/05/02 2012/5/02
RE1524
0_0402_5%
@
RE1524
0_0402_5%
@
1 2
IT7PAD IT7PAD
CE17 100P_0402_50V8JCE17 100P_0402_50V8J
1 2
CE9
0.1U_0402_16V4Z
CE9
0.1U_0402_16V4Z
12
CE8
0.1U_0402_16V4Z
CE8
0.1U_0402_16V4Z
12
RE22
0_0603_5%
RE22
0_0603_5%
12
RE114.7K_0402_5% RE114.7K_0402_5%
1 2
IT1PAD IT1PAD
RE6
100K_0402_5%
RE6
100K_0402_5%
1 2
RE33 10K_0402_5%RE33 10K_0402_5%
1 2
RE38 0_0402_5%RE38 0_0402_5%
1 2
RE1 0_0603_5%@RE1 0_0603_5%@
1 2
RE2110K_0402_5% RE2110K_0402_5%
1 2
CE204
10P_0402_50V8J
@CE204
10P_0402_50V8J
@
1
2
RE41
R_short 0_0402_5%
RE41
R_short 0_0402_5%
1 2
CE11
1U_0402_6.3V6K
CE11
1U_0402_6.3V6K
1
2
RE44 0_0402_5%
@
RE44 0_0402_5%
@
12
CE10
0.1U_0402_16V4Z
CE10
0.1U_0402_16V4Z
12
CE3
0.1U_0402_16V4Z
CE3
0.1U_0402_16V4Z
12
CE16 100P_0402_50V8JCE16 100P_0402_50V8J
1 2
CE6
0.1U_0402_16V4Z
CE6
0.1U_0402_16V4Z
12
RE1910K_0402_5% RE1910K_0402_5%
1 2
CE1
.1U_0402_16V7K
CE1
.1U_0402_16V7K
12
RE34 0_0402_5%RE34 0_0402_5%
1 2
RE15 10K_0402_5%RE15 10K_0402_5%
1 2
IT5PAD IT5PAD
RE24 2.2K_0402_5%RE24 2.2K_0402_5%
1 2
CE63
220P_0402_25V8J
@CE63
220P_0402_25V8J
@
1
2
RE26
100K_0402_5%
RE26
100K_0402_5%
12
IT6PAD IT6PAD
RE1525
0_0402_5%
@
RE1525
0_0402_5%
@
1 2
RE910K_0402_5% RE910K_0402_5%
12
RE1526
0_0402_5%
@
RE1526
0_0402_5%
@
1 2
RE13 10K_0402_5%RE13 10K_0402_5%
1 2
RE1527
0_0402_5%
@
RE1527
0_0402_5%
@
1 2
CE14
47P_0402_50V8J
@
CE14
47P_0402_50V8J
@
12
RE10 10K_0402_5%@RE10 10K_0402_5%@
1 2
LE1
BLM18PG181SN1D_0603
LE1
BLM18PG181SN1D_0603
1 2
RE29 2.2K_0402_5%RE29 2.2K_0402_5%
1 2
RE30 2.2K_0402_5%RE30 2.2K_0402_5%
1 2
RE37 43_0402_5%RE37 43_0402_5%
1 2
RE14 10K_0402_5%@RE14 10K_0402_5%@
1 2
IT3PAD IT3PAD
CE15
0.1U_0402_10V6K
@
CE15
0.1U_0402_10V6K
@
1
2
LPC
Int. K/B
Matrix
SM Bus
GPIO
ADC
PWM
DAC
PS2
EXTERNAL SERIAL FLASH
SPI Flash ROM
UART
Clock
GPIO
WAKE UP
IT8586E/AX
LQFP-128L
UE1
IT8586E-FX_LQFP128_14X14
S IC IT8586E/EX LQFP 128P KB CONTROLLER
LPC
Int. K/B
Matrix
SM Bus
GPIO
ADC
PWM
DAC
PS2
EXTERNAL SERIAL FLASH
SPI Flash ROM
UART
Clock
GPIO
WAKE UP
IT8586E/AX
LQFP-128L
UE1
IT8586E-FX_LQFP128_14X14
S IC IT8586E/EX LQFP 128P KB CONTROLLER
LPCRST#/GPD2
22
CK32KE/GPJ7
2
KBRST#/GPB6
4
SERIRQ/GPM6
5
TACH1A/TMA1/GPD7 48
LAD3/GPM3
7
LAD2/GPM2
8
VCC 11
LAD0/GPM0
10
VSS
1
LFRAME#/GPM5
6
LAD1/GPM1
9
KSO11/ERR#
51
KSO12/SLCT
52
KSO13
53
KSO14
54
KSO15
55
KSO16/SMOSI/GPC3
56
WRST#
14
ADC1/GPI1 67
ADC2/GPI2 68
VSS
27
KSO17/SMISO/GPC5
57
ADC3/GPI3 69
ADC4/GPI4 70
KSI0/STB#
58
KSI1/AFD#
59
KSI2/INIT#
60
KSI3/SLIN#
61
KSI4
62
KSI5
63
KSI6
64
LPCCLK/GPM4
13
ECSMI#/GPD4
15
PWM0/GPA0 24
PWM1/GPA1 25
PWM2/GPA2 28
PWM3/GPA3 29
PWM4/GPA4 30
PWM5/GPA5 31
PWM6/SSCK/GPA6 32
GINT/CTS0#/GPD5
33
PWM7/RIG1#/GPA7 34
RTS1#/GPE5
35
KSO0/PD0
36
KSO1/PD1
37
KSO2/PD2
38
KSO3/PD3
39
KSO4/PD4
40
KSO5/PD5
41
PWUREQ#/BBO/SMCLK2ALT/GPC7
16
LPCPD#/GPE6
17
RI1#/GPD0 18
L80HLAT/BAO/GPE0 19
L80LLAT/GPE7 20
RI2#/GPD1 21
ECSCI#/GPD3
23
ADC5/DCD1#/GPI5 71
ADC6/DSR1#/GPI6 72
ADC7/CTS1#/GPI7 73
TACH2/GPJ0 76
AVCC 74
DAC3/TACH1B/GPJ3 79
AVSS
75
DAC4/DCD0#/GPJ4 80
DAC5/RIG0#/GPJ5 81
EGAD/GPE1 82
GPH5/ID5 98
GPH6/ID6 99
GPJ1 77
DAC2/TACH0B/GPJ2 78
KSO8/ACK#
44
KSO9/BUSY
45
KSO10/PE
46
TACH0A/GPD6 47
KSO6/PD6
42
KSO7/PD7
43
EGCS#/GPE2 83
EGCLK/GPE3 84
PS2CLK0/TMB0/CEC/GPF0 85
PS2DAT0/TMB1/GPF1 86
GPF2 87
GPF3 88
SSCE0#/GPG2 100
NC 101
NC 102
NC 103
DSR0#/GPG6 104
VSS
91
NC 105
VSTBY 50
PS2CLK2/GPF4 89
PS2DAT2/GPF5 90
AC_IN# 108
LID_SW# 109
PWRSW#
110
XLP_OUT
111
VSTBY0
112
SMCLK1/GPC1
115
SMDAT1/GPC2
116
SMCLK2/PECI/GPF6
117
SMDAT2/PECIRQT#/GPF7
118
CLKRUN#/GPH0/ID0
93
CRX0/GPC0 119
VSTBY 92
TMRI0/GPC4 120
VSS
113
CTX0/TMA0/GPB2 123
TMRI1/GPC6 124
GPE4
125
GA20/GPB5
126
CK32K/GPJ6
128
CTX1/SOUT1/GPH2/SMDAT3/ID2
95 SSCE1#/GPG0 106
KSI7
65
ADC0/GPI0 66
VSTBY 114
GPH3/ID3 96
DTR1#/SBUSY/GPG1/ID7 107
GPH4/ID4 97
VSS
49
VSS
122
VSTBY 26
VSTBY 121
VSTBY(PLL) 127
VCORE 12
VBAT 3
CRX1/SIN1/SMCLK3/GPH1/ID1
94
RE2 0_0402_5%@RE2 0_0402_5%@
1 2
RE1810K_0402_5% RE1810K_0402_5%
1 2
IT4PAD IT4PAD
RE23 2.2K_0402_5%RE23 2.2K_0402_5%
1 2
RE32
10K_0402_5%
RE32
10K_0402_5%
12
RE45 0_0402_5%RE45 0_0402_5%
12
RE25
100K_0402_5% @
RE25
100K_0402_5% @
12
CE2
0.1U_0402_16V4Z
CE2
0.1U_0402_16V4Z
12
RE40
0_0402_5%
@RE40
0_0402_5%
@
12
RE39 0_0402_5%RE39 0_0402_5%
1 2
LE2
BLM18PG181SN1D_0603
LE2
BLM18PG181SN1D_0603
1 2
RE27
100K_0402_5%
RE27
100K_0402_5%
12
RE7
100K_0402_5%
@
RE7
100K_0402_5%
@
1 2
RE1610K_0402_5% RE1610K_0402_5%
12
RE124.7K_0402_5% RE124.7K_0402_5%
1 2
IT0PAD IT0PAD
RE5 0_0603_5%RE5 0_0603_5%
1 2
RE3 R_short 0_0402_5%RE3 R_short 0_0402_5%
1 2
RE17 0_0402_5%RE17 0_0402_5%
1 2
RE31
100K_0402_5%
@
RE31
100K_0402_5%
@
12
RE4
10K_0402_5%
@
RE4
10K_0402_5%
@
12
RE125 10_0402_5%
@
RE125 10_0402_5%
@
1 2
RE8
10K_0402_5%
@
RE8
10K_0402_5%
@
12
IT2PAD IT2PAD
CE5
0.1U_0402_16V4Z
CE5
0.1U_0402_16V4Z
12
RE2010K_0402_5%
@
RE2010K_0402_5%
@
1 2
RE28 10K_0402_5%RE28 10K_0402_5%
1 2
G
D
S
QE1
2N7002H_SOT23-3
G
D
S
QE1
2N7002H_SOT23-3
2
13
RE43 0_0402_5%RE43 0_0402_5%
12
CE4
1000P_0402_50V7K
CE4
1000P_0402_50V7K
12
CE7
0.1U_0402_16V4Z
CE7
0.1U_0402_16V4Z
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To TP/B Conn.
Lid Switch
For ESD request
KB Lighting CONN.4pin
15" INT_KBD Conn.
CONN PIN define need double check
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
For ESD Request
TP_CLK
+VCC_LID
TP_DATA
SMB_CLK_S3
SMB_DATA_S3
KSO0
KSO12
KSO11
KSO1
KSI0
KSO7
KSO5
KSI5
KSO3
KSO16
KSO17
KSI6
KSO15
KSO4
KSI3
KSO14
KSI7
KSO2
KSI2
KSO13
KSI4
KSO6
KSO9
KSO8
KSO10
KSI1
KSO17
KSO16
KSI[0..7]
KSO[0..17]
KSO2
KSO15
KSO6
KSO8
KSO13
KSO12
KSO11
KSO10
KSO3
KSO4
KSI0
KSO0
KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
KBL_DET
KBL_DET#
KBL_DET#
LID_SW# <46>
TP_CLK<46>
TP_DATA<46>
SMB_DATA_S3<11,12,17,40>
SMB_CLK_S3<11,12,17,40>
KSI[0..7] <46>
KSO[0..17] <46>
LED_KB_PWM<46>
KBL_DET# <54>
+3VL
+3VS
+3VALW
+VCC_KB_LED
+VCC_KB_LED
+5VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
KB/ KB-LIGHT/ LID IC
Custom
47 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
KB/ KB-LIGHT/ LID IC
Custom
47 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
KB/ KB-LIGHT/ LID IC
Custom
47 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
C737 100P_0402_50V8J@C737 100P_0402_50V8J@
1 2
C756 100P_0402_50V8J@C756 100P_0402_50V8J@
1 2
C762
100P_0402_50V8J
@
C762
100P_0402_50V8J
@
1
2
C761
100P_0402_50V8J
@
C761
100P_0402_50V8J
@
1
2
C749 100P_0402_50V8J@C749 100P_0402_50V8J@
1 2
C907
0.01U_0402_16V7K
@C907
0.01U_0402_16V7K
@
1
2
R1002
R_short 0_0402_5%
R1002
R_short 0_0402_5%
1 2
C752 100P_0402_50V8J@C752 100P_0402_50V8J@
1 2
C748 100P_0402_50V8J@C748 100P_0402_50V8J@
1 2
C746 100P_0402_50V8J@C746 100P_0402_50V8J@
1 2
C741 100P_0402_50V8J@C741 100P_0402_50V8J@
1 2
C740 100P_0402_50V8J@C740 100P_0402_50V8J@
1 2
R1229
10K_0402_5%
KBL@
R1229
10K_0402_5%
KBL@
12
C755 100P_0402_50V8J@C755 100P_0402_50V8J@
1 2
R1230
10K_0402_5%
@
R1230
10K_0402_5%
@
1 2
C739 100P_0402_50V8J@C739 100P_0402_50V8J@
1 2
C758
0.1U_0402_16V4Z
C758
0.1U_0402_16V4Z
1
2
C744 100P_0402_50V8J@C744 100P_0402_50V8J@
1 2
C751 100P_0402_50V8J@C751 100P_0402_50V8J@
1 2
C759
10P_0402_50V8J
C759
10P_0402_50V8J
1
2
C736 100P_0402_50V8J@C736 100P_0402_50V8J@
1 2
C738 100P_0402_50V8J@C738 100P_0402_50V8J@
1 2
C743 100P_0402_50V8J@C743 100P_0402_50V8J@
1 2
C553
330P_0402_50V8J
C553
330P_0402_50V8J
12
JTP1
ACES_88514-00601-071
ME@JTP1
ACES_88514-00601-071
ME@
1
1
2
2
3
3
4
4
5
5
6
6
GND
8GND
7
C747 100P_0402_50V8J@C747 100P_0402_50V8J@
1 2
C753 100P_0402_50V8J@C753 100P_0402_50V8J@
1 2
U37
5711ACDL-M3T1S SOT-23
U37
5711ACDL-M3T1S SOT-23
GND
1
OUTPUT 3
VDD 2
C742 100P_0402_50V8J@C742 100P_0402_50V8J@
1 2
C794 100P_0402_50V8J@C794 100P_0402_50V8J@
1 2
C795 100P_0402_50V8J@C795 100P_0402_50V8J@
1 2
C735 100P_0402_50V8J@C735 100P_0402_50V8J@
1 2
R1231
10K_0402_5%
@
R1231
10K_0402_5%
@
1 2
C760
0.1U_0402_16V4Z
C760
0.1U_0402_16V4Z
C757 100P_0402_50V8J@C757 100P_0402_50V8J@
1 2
JKB1
ACES_85202-3005N
ME@
JKB1
ACES_85202-3005N
ME@
G1 31
G2 32
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
G
D
S
Q121 AO3413_SOT23-3
KBL@
G
D
S
Q121 AO3413_SOT23-3
KBL@
2
13
C734 100P_0402_50V8J@C734 100P_0402_50V8J@
1 2
G
D
S
Q163
2N7002KW_SOT323-3
G
D
S
Q163
2N7002KW_SOT323-3
2
13
C908
0.1U_0402_16V4Z
@
C908
0.1U_0402_16V4Z
@
1
2
R1232
0_0402_5%
R1232
0_0402_5%
1 2
C750 100P_0402_50V8J@C750 100P_0402_50V8J@
1 2
R1003 100K_0402_5%R1003 100K_0402_5%
1 2
C754 100P_0402_50V8J@C754 100P_0402_50V8J@
1 2
C745 100P_0402_50V8J@C745 100P_0402_50V8J@
1 2
C905
0.1U_0402_10V6K
@
C905
0.1U_0402_10V6K
@
1
2
JKBL1
E&T_6906-Q04N-00R
ME@
JKBL1
E&T_6906-Q04N-00R
ME@
1
1
2
2
3
3
4
4
G1
5
G2
6
D58
AZC099-04S.R7G_SOT23-6
@
D58
AZC099-04S.R7G_SOT23-6
@
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
R1480
100K_0402_5%
KBL@
R1480
100K_0402_5%
KBL@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(40mil)
(40mil)
(40mil)
800mA
< 4 in 1 Card Reader Connector >
Colse to Conn. Colse to Socket Pin11.
Colse to Conn.
For EMI
Close to chip
AC Coupling close to
pin1 and pin2 of Chip
1.2V Power Source Selection:
(Optional)
20 mils
All of cap. close to chip
40 mils40 mils
Close to Pin3 Close to Pin28
Close to Pin22 Close to Pin25 Close to Pin13
Close to Pin12
Vendor recommend to reserve
SD_CLK_MS_DATA0
SD_CLK_MS_DATA0
SD_CD#
SD_DATA2_MS_CLK
SD_MS_DATA3
SD_DATA0_MS_DATA1
MS_INS#
SD_DATA0_MS_DATA1
SD_DATA2_MS_CLK
SD_CMD_MS_DATA2
SD_CMD_MS_DATA2
SD_MS_DATA3
+CRD_POWER
SD_CLK_MS_DATA0 SD_DATA2_MS_CLK
SD_DATA2_MS_CLK SD_CLK_MS_DATA0
SD_DATA2_MS_CLK_R
SD_MS_DATA3_R
SD_CMD_MS_DATA2_R
SD_CLK_MS_DATA0_R
SD_DATA0_MS_DATA1_R
SD_DATA1_MS_BS_R
SD_DATA2_MS_CLK
SD_MS_DATA3
SD_CMD_MS_DATA2
SD_CLK_MS_DATA0
SD_DATA0_MS_DATA1
SD_DATA1_MS_BS
SD_WP
SD_CD#
MS_INS#
+3VS_CARD
SD_WP
SD_DATA1_MS_BS
SD_DATA1_MS_BS
USB30_RX_N6_C
USB30_RX_P6_C
USB30_TX_N6_C
USB30_TX_P6_C
USB30_RX_P6<18>
USB30_RX_N6<18>
USB20_P4<18>
USB20_N4<18>
USB30_TX_N6<18>
USB30_TX_P6<18>
+CRD_POWER
+3VS_CARD
+CRD_POWER+DV12
+3V3_AUX
+DV12
+3V3_AUX +3VS_CARD
+3VS_CARD+3VS
+3VS_CARD +3V3_AUX
+DV12
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Card reader GL3213
Custom
48 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Card reader GL3213
Custom
48 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Card reader GL3213
Custom
48 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
CW553
10P_0402_50V8J
@
CW553
10P_0402_50V8J
@
1
2
CW10
0.1U_0402_16V4Z
CW10
0.1U_0402_16V4Z
1
2
RW14
10_0402_5%
@
RW14
10_0402_5%
@
1 2
CW5
0.1U_0402_16V4Z
CW5
0.1U_0402_16V4Z
1 2
RW2
1M_0402_5%
RW2
1M_0402_5%
1 2
RW9
680_0402_1%
RW9
680_0402_1%
1 2
CW25
15P_0402_50V8J
CW25
15P_0402_50V8J
1
2
RW4 0_0402_5%RW4 0_0402_5%
1 2
CW3
4.7U_0603_10V6K
CW3
4.7U_0603_10V6K
1 2
CW6
0.1U_0402_16V4Z
CW6
0.1U_0402_16V4Z
1 2
CW26
15P_0402_50V8J
CW26
15P_0402_50V8J
1
2
CW20
1U_0402_10V6K
CW20
1U_0402_10V6K
1
2
RW10 R_short 0_0402_5%RW10 R_short 0_0402_5%
1 2
CW21
0.1U_0402_16V4Z
CW21
0.1U_0402_16V4Z
1
2
CW550
10P_0402_50V8J
@
CW550
10P_0402_50V8J
@
1
2
CW1
.1U_0402_16V7K
CW1
.1U_0402_16V7K
12
RW13
10_0402_5%
@
RW13
10_0402_5%
@
1 2
CW7
0.1U_0402_16V4Z
CW7
0.1U_0402_16V4Z
1
2
RW6 0_0402_5%RW6 0_0402_5%
1 2
RW11
10_0402_5%
@
RW11
10_0402_5%
@
1 2
CW552
10P_0402_50V8J
@
CW552
10P_0402_50V8J
@
1
2
RW5 0_0402_5%RW5 0_0402_5%
1 2
CW17
10U_0805_10V6K
CW17
10U_0805_10V6K
1
2
CW24
1U_0402_10V6K
CW24
1U_0402_10V6K
1
2
CW16
0.1U_0402_16V4Z
CW16
0.1U_0402_16V4Z
1
2
CW19
2.2U_0603_6.3V6K
CW19
2.2U_0603_6.3V6K
1
2
RW1
R_short 0_0603_5%
RW1
R_short 0_0603_5%
12
CW8
.1U_0402_16V7K
CW8
.1U_0402_16V7K
12
YW1
25MHZ_10PF_7V25000014
YW1
25MHZ_10PF_7V25000014
GND
2
33
1
1
GND
4
RW3 0_0402_5%RW3 0_0402_5%
1 2
RW7 0_0402_5%RW7 0_0402_5%
1 2
CW22
4.7U_0603_10V6K
CW22
4.7U_0603_10V6K
1
2
UW1
GL3213-OHY03_QFN28_5X5
UW1
GL3213-OHY03_QFN28_5X5
TXN
1
TXP
2
AVDD12
3
RXN
4
RXP
5
X1
6
X2
7
AVDD33
8
RTERM
9
SD_WP 10
SD_CDZ 11
DVDD12
12
V33IN
13
MS_INS 14
SB1 15
SB2 16
SB3 17
SB4 18
SB5 19
SB6 20
VUHSI 21
DVDD33 22
PMOS 23
RSTZ
24
AVDD33 25
DP
26
DM
27
AVDD12
28
G1 29
CW9
.1U_0402_16V7K
CW9
.1U_0402_16V7K
12
CW4
1U_0402_10V6K
CW4
1U_0402_10V6K
1 2
JREAD2
T-SOL_144-1313002600_40P_NR-T
ME@
JREAD2
T-SOL_144-1313002600_40P_NR-T
ME@
XD08-WP
32
XD14-D4
26
MS7-DATA3 15
MS4-DATA0 10
SD9-DAT2 21
SD7-DAT0 4
SD2-CMD 16
MS3-DATA1 8
XD16-D6
24 SD1-DAT3 19
SD8-DAT1 3
XD06-ALE
34
XD10-D0
30
SD5-CLK 9
XD12-D2
28
MS6-INS 14
MS5-DATA2 12
MS8-SCLK 17
XD03-RE
37
MS2-BS 7
XD15-D5
25
XD17-D7
23
XD11-D1
29
XD04-CE
36
XD02-R/B
38
XD13-D3
27
XD07-WE
33
MS9-VCC 18
XD GND
31
XD05-CLE
35
XD GND
40
SD4-VDD 11
XD-VCC
22
XD01-CD
39
SD-CD 1
SD-WP 2
SD CD/WP GND
41
SD CD/WP GND
42 MS10-VSS 20
MS1-VSS 5
SD3-VSS 13
SD6-VSS 6
CW18
0.1U_0402_16V4Z
CW18
0.1U_0402_16V4Z
1
2
CW23
2.2U_0603_6.3V6K
CW23
2.2U_0603_6.3V6K
1
2
CW551
10P_0402_50V8J
@
CW551
10P_0402_50V8J
@
1
2
CW15
0.1U_0402_16V4Z
@
CW15
0.1U_0402_16V4Z
@
1
2
RW12
10_0402_5%
@
RW12
10_0402_5%
@
1 2
CW2
.1U_0402_16V7K
CW2
.1U_0402_16V7K
12
RW8 0_0402_5%RW8 0_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Low Active 2A
For ESD request
For EMI request
LEFT SIDE USB3.0 PORT X1
For EMI request
USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
For ESD request
USB2.0 choke --> SM070001S0J
USB3.0 Choke --> SM070001S0J
For ESD request
For ESD request
USB_ON# USB_OC1#
USB30_RX_N2
USB30_RX_P2
USB30_TX_C_P2
USB30_TX_C_N2
USB30_TX_R_P2
USB30_RX_R_N2
USB30_RX_R_P2
USB30_TX_R_N2
USB20_N2_R
USB20_P2_R
USB20_N2
USB20_P2
USB30_TX_R_P2
USB30_RX_R_N2
USB30_RX_R_P2
USB30_TX_R_N2
USB30_TX_R_P2
USB30_RX_R_N2
USB30_RX_R_P2
USB30_TX_R_N2
USB20_N2_R
USB20_P2_R
USB30_TX_C_P2 USB30_TX_R_P2USB30_TX_P2
USB30_TX_N2 USB30_TX_C_N2 USB30_TX_R_N2
USB20_P2_RUSB20_P2
USB20_N2_RUSB20_N2
USB30_RX_P2 USB30_RX_R_P2
USB30_RX_R_N2USB30_RX_N2
USB30_TX_C_P5 USB30_TX_R_P5USB30_TX_P5
USB30_TX_C_N5 USB30_TX_R_N5USB30_TX_N5
USB20_P3_RUSB20_P3
USB20_N3_RUSB20_N3
USB30_RX_P5 USB30_RX_R_P5
USB30_RX_R_N5USB30_RX_N5
USB30_RX_N5
USB30_RX_P5
USB30_TX_R_P5
USB30_RX_R_N5
USB30_RX_R_P5
USB30_TX_R_N5
USB20_N3_R
USB20_P3_R
USB20_N3
USB20_P3
USB30_TX_C_P5
USB30_TX_C_N5
USB20_N3_R
USB30_TX_R_P5
USB30_RX_R_N5
USB30_RX_R_P5
USB30_TX_R_N5
USB20_P3_R
USB30_TX_R_P5
USB30_RX_R_N5
USB30_RX_R_P5
USB30_TX_R_N5
USB_OC1# <18>
USB_ON#<46>
USB30_TX_P2<18>
USB30_TX_N2<18>
USB20_P2<18>
USB20_N2<18>
USB30_RX_P2<18>
USB30_RX_N2<18>
USB30_TX_P5<18>
USB30_TX_N5<18>
USB20_P3<18>
USB20_N3<18>
USB30_RX_P5<18>
USB30_RX_N5<18>
+USB_VCCA+5VALW
+5VALW
+USB_VCCA
+USB_VCCA
+5VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
USB 3.0 PORT (LEFT)
Custom
49 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
USB 3.0 PORT (LEFT)
Custom
49 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
USB 3.0 PORT (LEFT)
Custom
49 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
D24
AZC099-04S.R7G_SOT23-6
@
D24
AZC099-04S.R7G_SOT23-6
@
I/O4 6
VDD 5
I/O3 4
I/O2
3
GND
2
I/O1
1
JUSB2
SANTA_370300-1
ME@
JUSB2
SANTA_370300-1
ME@
SSTX-
8
SSTX+
9
GND_6 13
GND_5 12
VBUS
1
D+
3D-
2
GND_1
4
SSRX-
5
SSRX+
6
GND_2
7
GND_4 11
GND_3 10
C817 470P_0402_50V7KC817 470P_0402_50V7K
1 2
U39
G547I2P81U_MSOP8
U39
G547I2P81U_MSOP8
FLG 5
VIN
3VOUT 6
GND
1
EN
4
VOUT 7
VIN
2VOUT 8
R1163 0_0402_5%
@
R1163 0_0402_5%
@
1 2
R1162 0_0402_5%
@
R1162 0_0402_5%
@
1 2
C299 0.1U_0402_10V6KC299 0.1U_0402_10V6K
1 2
L72
WCM-2012-900T_4P
L72
WCM-2012-900T_4P
11
44
3
3
2
2
L68
WCM-2012-900T_4P
L68
WCM-2012-900T_4P
11
44
3
3
2
2
R1156 0_0402_5%
@
R1156 0_0402_5%
@
1 2
R1154 0_0402_5%
@
R1154 0_0402_5%
@
1 2
L69
WCM-2012-900T_4P
L69
WCM-2012-900T_4P
11
44
3
3
2
2
L73
WCM-2012-900T_4P
L73
WCM-2012-900T_4P
11
44
3
3
2
2
C816 470P_0402_50V7KC816 470P_0402_50V7K
1 2
C302 0.1U_0402_10V6KC302 0.1U_0402_10V6K
1 2
C767 0.1U_0402_16V4ZC767 0.1U_0402_16V4Z
12
R1161 0_0402_5%@R1161 0_0402_5%@
1 2
8
7
6 5
4
3
2
1
9
10
D29
YSCLAMP0524P_SLP2510P8-10-9
@
8
7
6 5
4
3
2
1
9
10
D29
YSCLAMP0524P_SLP2510P8-10-9
@
4
5
1
6
2
7
3
9
8
C904
1000P_0402_50V7K@
C904
1000P_0402_50V7K@
1
2
JUSB1
SANTA_370300-1
ME@
JUSB1
SANTA_370300-1
ME@
SSTX-
8
SSTX+
9
GND_6 13
GND_5 12
VBUS
1
D+
3D-
2
GND_1
4
SSRX-
5
SSRX+
6
GND_2
7
GND_4 11
GND_3 10
C301 0.1U_0402_10V6KC301 0.1U_0402_10V6K
1 2
R1158 0_0402_5%
@
R1158 0_0402_5%
@
1 2
L71
WCM-2012-900T_4P
L71
WCM-2012-900T_4P
11
44
3
3
2
2
L70
WCM-2012-900T_4P
L70
WCM-2012-900T_4P
11
44
3
3
2
2
D25
AZC099-04S.R7G_SOT23-6
@
D25
AZC099-04S.R7G_SOT23-6
@
I/O4 6
VDD 5
I/O3 4
I/O2
3
GND
2
I/O1
1
+
C815 220U_6.3V_M
@
+
C815 220U_6.3V_M
@
1 2
R1165 0_0402_5%@R1165 0_0402_5%@
1 2
+
C814 220U_6.3V_M
+
C814 220U_6.3V_M
1 2
C819
0.1U_0402_16V4Z
C819
0.1U_0402_16V4Z
1 2
C818
0.1U_0402_16V4Z
C818
0.1U_0402_16V4Z
1 2
C300 0.1U_0402_10V6KC300 0.1U_0402_10V6K
1 2
R1157 0_0402_5%
@
R1157 0_0402_5%
@
1 2
R1159 0_0402_5%@R1159 0_0402_5%@
1 2
R1164 0_0402_5%
@
R1164 0_0402_5%
@
1 2
R1155 0_0402_5%
@
R1155 0_0402_5%
@
1 2
R1160 0_0402_5%
@
R1160 0_0402_5%
@
1 2
8
7
6 5
4
3
2
1
9
10
D27
YSCLAMP0524P_SLP2510P8-10-9
@
8
7
6 5
4
3
2
1
9
10
D27
YSCLAMP0524P_SLP2510P8-10-9
@
4
5
1
6
2
7
3
9
8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ext. MIC
Remove Diode (DA1, DA2)
Touch panel
Sleep & Charge
Right side USB Charger Port (USB_Port5, near JMIC1)
20120902 VA2
Change to OC0#
Genesys GL887
0
0
1
1
1
1
CHG_MOD1 CHG_MOD0
1
CHG_MOD2
0
0
1
1
0
0
1
1
0
1
CDP mode
DCP mode
Apple 1A mode
Charge Mode
Apple 2A mode
Auto mode (DCP and Apple 1A)
Auto mode (DCP and Apple 2A)
0 0
1
Charge Disable
0
DCP_Auto
DCP_Auto
11
OUT held low /Data lines disconnected
1 1 Data connected and Load detect active
Data connected
1
Data connected
1
1
1
1
00
CHG_MOD0
CHG_MOD1
1
CHG_MOD2
0
MODE
0
0
0X
Data connected
Stay in DCP BC1.2 Charging mode
01
TI TPS2543
Stay in DCP Divider1 Charging mode
0
ILIM_SEL2
Data disconnected and Load detect active
X
0
Data disconnected and Load detect active
0
1 1
01 1
001
X
X
X
X
XDCH
SDP1
CDP
SDP2
SDP1
DCP_Short
DCP_Divider
Genesys GL887T
X
0
1
1
1
0
CHG_MOD1 CHG_MOD0
1
CHG_MOD2
1
0
0
1
1
1
0
0
1
1
Auto 2A mode without wake up function
BC1.2 SDP mode
Auto 2A mode with wake up function
Charge Mode
BC1.2 DCP mode
Apple 2A mode
BC1.2 CDP mode with Smart CDP
0 0
0
Power down mode
0
*
*
*
*
*
*
Close to U8 Pin 1
50 mil 50 mil
Mode S0 S3
CHG_MOD 01
Close to U8
For ESD
For TI charger
EXT_MIC_R
EXT_MIC_L
EXT_MIC_R
HP_OUTL
HP_OUTR
MIC_JD
PLUG_IN
USB20_P8
USB20_N8
USB20_P8_THP
USB20_P8_THPUSB20_P8
USB20_N8
USB20_N8_THP
USB20_N8_THP
USB20_N8_THP
USB20_P8_THP
ILIM_SEL0
ILIM_SEL1
ILIM_SEL2
USB20_P1
USB20_N1
ILIM_SEL1
USB20_P1_C
USB20_N1_C
CHG_MOD1
USB_CH
CHG_MOD1
ILIM_SEL0
ILIM_SEL2
CHG_MOD2
CHG_MOD0
CHG_MOD2
USB20_P1_C
USB20_N1_C
EXT_MIC_L
SPDIF_OUT
MIC1_R<45>
MIC1_L<45>
PLUG_IN<45>
MIC_JD<45>
HP_OUTR<45>
HP_OUTL<45>
SPDIF_OUT<45>
USB20_N8<18>
USB20_P8<18>
USB20_P1<18>
USB20_N1<18>
USB_OC0# <18>
USB_CH<46>
CHG_MOD<54>
+MIC1_VREFO_L
+5VS
+5VALW
+5VALW
+5VALW +5V_CHGUSB
+5VALW
+5VALW
+5VS
+5V_CHGUSB
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
AUDIO-B CONN/ USB CHARGER
Custom
50 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
AUDIO-B CONN/ USB CHARGER
Custom
50 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
AUDIO-B CONN/ USB CHARGER
Custom
50 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
C1100
220P_0402_25V8J
C1100
220P_0402_25V8J
1
2
RA1623
2.2K_0402_5%
RA1623
2.2K_0402_5%
1 2
RA1634 1K_0402_5%RA1634 1K_0402_5%
12
R2 0_0603_5%R2 0_0603_5%
12
RA1622
2.2K_0402_5%
RA1622
2.2K_0402_5%
1 2
C1099
0.1U_0402_16V4Z
@C1099
0.1U_0402_16V4Z
@1
2
R1584
10K_0402_5%
@
R1584
10K_0402_5%
@
1 2
R1168 0_0402_5%R1168 0_0402_5%
1 2
C1098
0.1U_0402_16V4Z
C1098
0.1U_0402_16V4Z
1
2
U8
GL887-OCGC_QFN16_3X3
887T@U8
GL887-OCGC_QFN16_3X3
887T@
NC2
4
CHG_MOD0
8
DM_DOWN 11
BC_CON 9
ALARM 13
CHG_MOD2
6
CHG_MOD1
7
DM_UP
2
PSW_EN
5
DP_DOWN 10
VBUS_OUT 12
DP_UP
3
NC1
16
P5V
1
NC0
15 GND_PAD 17
GND 14
R1551
10K_0402_5%
TI@R1551
10K_0402_5%
TI@
1 2
R1561 10K_0402_5%
@
R1561 10K_0402_5%
@
1 2
U8
TPS2546RTER_QFN16_4X4
TI@
U8
TPS2546RTER_QFN16_4X4
TI@
JTHP
ACES_85205-06001
ME@JTHP
ACES_85205-06001
ME@
1
1
2
2
3
3
5
5
6
6
4
4
G7
7
G8
8
R1585
10K_0402_5%
@R1585
10K_0402_5%
@
1 2
T182PAD
@
T182PAD
@
C1096
10U_0603_6.3V6M
C1096
10U_0603_6.3V6M
1
2
G
D
S
Q122
2N7002KW_SOT323-3
@
G
D
S
Q122
2N7002KW_SOT323-3
@
2
13
R1586
10K_0402_5%
@R1586
10K_0402_5%
@
1 2
RA1633 1K_0402_5%RA1633 1K_0402_5%
12
JSB1
ACES_50505-0184N-001
ME@
JSB1
ACES_50505-0184N-001
ME@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18 G1 19
G2 20
R1559
10K_0402_5%
@
R1559
10K_0402_5%
@
1 2
R1558
0_0402_5%887@
R1558
0_0402_5%887@
12
R1552
20K_0402_5%
TI@
R1552
20K_0402_5%
TI@
1 2
R1553
10K_0402_5%
R1553
10K_0402_5%
1 2
R1560 0_0402_5%R1560 0_0402_5%
1 2
R1555
0_0402_5%
R1555
0_0402_5%
12
C1097
0.01U_0402_16V7K
C1097
0.01U_0402_16V7K
1
2
R1169 0_0402_5%R1169 0_0402_5%
1 2
L75
WCM-2012-900T_4P
@
L75
WCM-2012-900T_4P
@
11
44
3
3
2
2
R1554
20K_0402_5%
@R1554
20K_0402_5%
@
1 2
White
White
Amber
PWR LED HDD LED
BATT CHARGE/LOW LED
White
CapsLK LED
LED3 LED2 LED1 LED4
POWER BATTERY T/P CapsLK
PCB Fedical Mark PAD
TouchPad_LED 2012-0507 --> Change LED1 to T/P LED
MIN PCIE: H_3P3 X 1CPU and GPU: H_3P8X 6
ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
H_2P8X4P0NX1
E: H_3P3X 1
A: H_2P8X 8
E: H_3P3X 3 H_3P0X9
B: H_3P8X 3
GPUCPU
C: H_3P8X 3
Screw Hole
LION LED SC500007F0J
LION LED:SC500004Y0J
HDD_LED#_R
BATT_LOW_LED#
BATT_CHG_LED#
HDD_LED#_R
PWR_LED#<46,52>
CAPS_LED#<46>
HDD_LED#<13>
TP_LED#<46>
NUM_LED#<46>
BATT_CHG_LED#<46>
BATT_LOW_LED#<46>
+5VALW
+5VS
+5VALW
+5VS
+5VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LED
Custom
51 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LED
Custom
51 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
LED
Custom
51 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
H25
HOLEA
H25
HOLEA
1
R1014
470_0402_5%
R1014
470_0402_5%
12
R1013
300_0402_5%
R1013
300_0402_5%
12
H35
HOLEA
H35
HOLEA
1
R1621
0_0402_5%
R1621
0_0402_5%
1 2
H29
HOLEA
H29
HOLEA
1
H13
HOLEA
H13
HOLEA
1
R1323
300_0402_5%
R1323
300_0402_5%
12
H23
HOLEA
H23
HOLEA
1
FD1FD1
1
LED1
12-21SYGCS530-E1S155TR8_W
LED1
12-21SYGCS530-E1S155TR8_W
21
H36
HOLEA
H36
HOLEA
1
LED3
12-21SYGCS530-E1S155TR8_W
LED3
12-21SYGCS530-E1S155TR8_W
21
LED5
12-21SYGCS530-E1S155TR8_W
LED5
12-21SYGCS530-E1S155TR8_W
21
LED2
12-22-S2ST3D-C30-2C_WHI-ORG
LED2
12-22-S2ST3D-C30-2C_WHI-ORG
1
3
2
R1322
300_0402_5%
R1322
300_0402_5%
12
H10
HOLEA
H10
HOLEA
1
H33
HOLEA
H33
HOLEA
1
H31
HOLEA
H31
HOLEA
1
H26
HOLEA
H26
HOLEA
1
H16
HOLEA
H16
HOLEA
1
FD2FD2
1
H11
HOLEA
H11
HOLEA
1
R1622
0_0402_5%
@R1622
0_0402_5%
@
1 2
FD3FD3
1
LED4
12-21SYGCS530-E1S155TR8_W
LED4
12-21SYGCS530-E1S155TR8_W
21
H21
HOLEA
H21
HOLEA
1
R1563300_0402_5% R1563300_0402_5%
12
H14
HOLEA
H14
HOLEA
1
H37
HOLEA
H37
HOLEA
1
H12
HOLEA
H12
HOLEA
1
H30
HOLEA
H30
HOLEA
1
FD4FD4
1
H24
HOLEA
H24
HOLEA
1
H15
HOLEA
H15
HOLEA
1
H28
HOLEA
H28
HOLEA
1
H20
HOLEA
H20
HOLEA
1
R1012
470_0402_5%
R1012
470_0402_5%
12
H34
HOLEA
H34
HOLEA
1
H32
HOLEA
H32
HOLEA
1
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
For ESD Request
Power Button/B link
to Function/B Conn. 10pin
For S3.5
TOP Side
Bottom Side
ON/OFF switch
Power Button
For S3.5
For S3.5
NO51ON@ default reserved
ON/OFF
EC_ON
ON/OFFBTN#
NOVO#
51_ON#
51_ON#
ON/OFF
NOVO_BTN#
NOVO_BTN#
ON/OFFBTN#
NOVO#<46>
EC_ON<46,59>
51_ON# <56>
ON/OFF <46>
PWR_LED#<46,51>
+3VL+3VALW
+3VALW +3VL
+5VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
ONOFF SW/ PWR-B CONN/ ISPD
Custom
52 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
ONOFF SW/ PWR-B CONN/ ISPD
Custom
52 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
ONOFF SW/ PWR-B CONN/ ISPD
Custom
52 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
R1116
100K_0402_5%
NO51ON@
R1116
100K_0402_5%
NO51ON@
1 2
C551
100P_0402_50V8J@
C551
100P_0402_50V8J@
1
2
SW 2
SMT1-05_4P
@SW2
SMT1-05_4P
@
3
2
1
4
5
6
G
D
S
Q153
2N7002_SOT23-3
G
D
S
Q153
2N7002_SOT23-3
2
13
C552
330P_0402_50V8J
C552
330P_0402_50V8J
12
D72
DAN202UT106_SC70-3
NO51ON@D72
DAN202UT106_SC70-3
NO51ON@
2
3
1
R28 0_0402_5%R28 0_0402_5%
1 2
D56
DAN202UT106_SC70-3
D56
DAN202UT106_SC70-3
2
3
1
R1531 0_0603_5%R1531 0_0603_5%
1 2
J7
SHORT PADS
@
J7
SHORT PADS
@
1 2
R19 0_0402_5%
NO51ON@
R19 0_0402_5%
NO51ON@
1 2
JPW R1
ACES_88514-00601-071
ME@JPW R1
ACES_88514-00601-071
ME@
1
12
23
34
45
56
6
GND
8
GND
7
R1117
100K_0402_5%
R1117
100K_0402_5%
1 2
R1532 0_0603_5%
@
R1532 0_0603_5%
@
1 2
R1523
10K_0402_5%
R1523
10K_0402_5%
1 2
R1119
100K_0402_5%
R1119
100K_0402_5%
1 2
R1118
100K_0402_5%
NO51ON@ R1118
100K_0402_5%
NO51ON@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Y501 NM-A032
1.0
NVSR
C
53 69Wednesday, March 27, 2013
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Y501 NM-A032
1.0
NVSR
C
53 69Wednesday, March 27, 2013
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Y501 NM-A032
1.0
NVSR
C
53 69Wednesday, March 27, 2013
2011/07/21 2012/12/31
GPU_PWR_EN
GPU_PWR_GOOD
PEX REST
SLI_FB_Clamp
FB_clamp_req
DGPU_HOLD_RST#
For USB charge
WRST#
GC6_EVENT# S_GC6_EVENT#
KBL_DET# CHG_MOD
GC6_EVENT#
EXIO_CS
FB_CLAMP
EXIO_DATA
CHG_MOD
EXIO_CLK
EXIO_CLK<46>
EXIO_CS<46>
WRST#<46>
EXIO_DATA<46>
S_DGPU_PWROK <16,32>
S_DGPU_PWR_EN <19,32,55>
GC6_EVENT#<19,23,54>
DGPU_PWROK<19,27,62,63>
DGPU_GC6_EN<14,27>
S_GC6_EN <27,32>
S_GC6_EVENT# <32>
S_DGPU_RST <16,32>
DGPU_PWR_EN<14,23,55>
DGPU_HOLD_RST#<14,23>
NVDD_PWR_EN<14,63>
KBL_DET#<47>
S_NVDD_PWR_EN <19,32>
CHG_MOD <50,54>
GC6_EVENT#<19,23,54>
FB_CLAMP<23,27,54>
CHG_MOD<50,54>
FB_CLAMP<23,27,54>
+3VALW_R
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EX IO
Custom
54 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EX IO
Custom
54 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
EX IO
Custom
54 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
RXE2 0_0402_5%
GC6@
RXE2 0_0402_5%
GC6@ 12
RXE1 0_0603_5%
@
RXE1 0_0603_5%
@
1 2
RXE30_0402_5%
GC6@
RXE30_0402_5%
GC6@ 12
T178PAD @T178PAD @
U80
IT8302FN
IT7230BFN-BX-0001_QFN24_4X4
@
U80
IT8302FN
IT7230BFN-BX-0001_QFN24_4X4
@
VSS1 1
GPIO_DATA
2
CYCLE_START
3GPIO_CLK
4
RESET#
5
GPIO4
6
GPIO5
7
GPIO7
8
GPIO9
9
GPIO11
10
GPIO13
11
VSS2 12
VSTBY1 13
GPIO18
14
GPIO20
15 GPIO22 16
GPIO24 17
GPIO26 18
GPIO27 19
GPIO29 20
GPIO33 21
GPIO31 22
GPIO35 23
VSTBY2 24
GND
25
RE460_0402_5% RE460_0402_5%
12
RXE14 0_0402_5%
@
RXE14 0_0402_5%
@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+5VALW to +5VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+3VALW to +3VS
+3VALW to +3V_PCH
+3VS to +3VS_VGA
For Intel S3 Power Reduction.
+3VS to +3VS_SLI
2012-0419 --> modify +3VS_SLI BOM structure to "SLI@"
Power 58 ,
For ESD request
For ESD request
Id=3.2A
DGPU_PWR_EN#
SUSP
5VS_GATE5VS_GATE_R
SUSP
3VS_GATE3VS_GATE_R
PM_SLP_SUS#
PCH_PWR_EN
PCH_PWR_EN#
SUSP
SUSP
DGPU_PWR_EN#
PCH_PWR_EN#_R
S_DGPU_PWR_EN#
PCH_PWR_EN#_RPCH_PWR_EN#_R
PCH_PWR_EN#_RLAN_WAKE#
DGPU_PWR_EN<14,23,54>
PM_SLP_SUS#
<15,46>
PCH_PWR_EN<46,57>
SUSP<10,40,61>
SUSP#<32,46,60,61,62>
S_DGPU_PWR_EN#<32>
S_DGPU_PWR_EN<19,32,54>
LAN_WAKE#
<40,41,46>
+5VALW +5VS
+5VALW
+3VS
+5VALW
+VSB +VSB
+3VALW +3VS
+3VALW +3V_PCH
+3VS_VGA
+5VALW +0.675VS
+3VS
+5VALW
+3VS_SLI
+5VS +3VS
+5VALW +3VL+3VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DC V TO VS INTERFACE
Custom
55 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DC V TO VS INTERFACE
Custom
55 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
DC V TO VS INTERFACE
Custom
55 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
R60
100K_0402_5%
DS3@R60
100K_0402_5%
DS3@
1 2
C41
0.1U_0402_16V4Z
C41
0.1U_0402_16V4Z 1
2
R1450
470_0603_5%
@R1450
470_0603_5%
@
12
G
D
S
Q107B
2N7002KDWH_SOT363-6
G
D
S
Q107B
2N7002KDWH_SOT363-6
5
34
C838
1U_0603_10V4Z
C838
1U_0603_10V4Z
1
2
R1452
R_short 0_0402_5%
R1452
R_short 0_0402_5%
1 2
C841
1U_0603_10V4Z
C841
1U_0603_10V4Z
1
2
R1120
100K_0402_5% DS3@
R1120
100K_0402_5% DS3@
12
R1094
22_0603_5%
R1094
22_0603_5%
12
J11
JUMP_43X79
@J11
JUMP_43X79
@
1
122
C44
0.1U_0402_16V4Z
C44
0.1U_0402_16V4Z 1
2
C837
10U_0603_6.3V6M
C837
10U_0603_6.3V6M
1
2
C45
0.1U_0402_16V4Z
C45
0.1U_0402_16V4Z 1
2
G
D
S
Q151
2N7002KW_SOT323-3
@
G
D
S
Q151
2N7002KW_SOT323-3
@
2
13
R1513
10K_0402_5%
R1513
10K_0402_5%
1 2
C1011
0.1U_0402_10V7K
C1011
0.1U_0402_10V7K
1
2
R1474
470_0603_5% @
R1474
470_0603_5% @
12
C42
0.1U_0402_16V4Z
C42
0.1U_0402_16V4Z 1
2
R1500
470_0603_5%
@R1500
470_0603_5%
@
12
R1483
820K_0402_5% @
R1483
820K_0402_5% @
12
C843
0.01U_0402_25V7K
C843
0.01U_0402_25V7K
1
2
G
D
S
Q145
AO3413_SOT23
G
D
S
Q145
AO3413_SOT23
2
13
C1066
0.01U_0402_25V7K
@C1066
0.01U_0402_25V7K
@
1
2
R117
R_short 0_0402_5%
R117
R_short 0_0402_5%
1 2
C1012
0.1U_0402_10V7K
C1012
0.1U_0402_10V7K
1
2
G
D
S
Q147
AO3413_SOT23
G
D
S
Q147
AO3413_SOT23
2
13
R1484
820K_0402_5% @
R1484
820K_0402_5% @
12
G
D
S
Q99
2N7002KW_SOT323-3
G
D
S
Q99
2N7002KW_SOT323-3
2
13
R1449
47K_0402_5%
R1449
47K_0402_5%
12
G
D
S
Q107A
2N7002KDWH_SOT363-6
G
D
S
Q107A
2N7002KDWH_SOT363-6
2
61
C39
0.1U_0402_16V4Z
@C39
0.1U_0402_16V4Z
@
1
2
R1088
82K_0402_5%
R1088
82K_0402_5%
1 2
U47
AP4800BGM-HF
U47
AP4800BGM-HF
4
7
8
6
5
1
2
3
R1501
100K_0402_5%
R1501
100K_0402_5%
12
C48
10U_0603_6.3V6M
C48
10U_0603_6.3V6M
1
2
C1058
0.1U_0402_16V4Z @
C1058
0.1U_0402_16V4Z @
1
2
R1097
100K_0402_5%
R1097
100K_0402_5%
12
C43
0.1U_0402_16V4Z
C43
0.1U_0402_16V4Z 1
2
G
D
S
Q148
AO3413_SOT23
G
D
S
Q148
AO3413_SOT23
2
13
C46
0.1U_0402_16V4Z
C46
0.1U_0402_16V4Z
1
2
C840
10U_0603_6.3V6M
C840
10U_0603_6.3V6M
1
2
G
D
S
Q118
2N7002_SOT23
DS3@
G
D
S
Q118
2N7002_SOT23
DS3@
2
13
R1451
10K_0402_5%
R1451
10K_0402_5%
1 2
R1475
470_0603_5% @
R1475
470_0603_5% @
12
R1448
0_0402_5%
@R1448
0_0402_5%
@12
R1085
150K_0402_5%
R1085
150K_0402_5%
C1059
0.01U_0402_25V7K
@C1059
0.01U_0402_25V7K
@
1
2
R1454
100K_0402_5%
R1454
100K_0402_5%
12
R1089
R_short 0_0402_5%
R1089
R_short 0_0402_5%
1 2
C1065
0.1U_0402_16V4Z @
C1065
0.1U_0402_16V4Z @
1
2
G
D
S
Q150
2N7002KW_SOT323-3
G
D
S
Q150
2N7002KW_SOT323-3
2
13
G
D
S
Q102
2N7002KW_SOT323-3
@
G
D
S
Q102
2N7002KW_SOT323-3
@
2
13
C37
10U_0603_6.3V6M
C37
10U_0603_6.3V6M
1
2
R1086
470K_0402_5%
R1086
470K_0402_5%
12
U46
AP4800BGM-HF
U46
AP4800BGM-HF
4
7
8
6
5
1
2
3
G
D
S
Q149
2N7002KW_SOT323-3
@
G
D
S
Q149
2N7002KW_SOT323-3
@
2
13
C836
10U_0805_10V6K
@
C836
10U_0805_10V6K
@
1
2
G
D
S
Q101
2N7002KW_SOT323-3
@
G
D
S
Q101
2N7002KW_SOT323-3
@
2
13
C1063
0.01U_0402_25V7K
@
C1063
0.01U_0402_25V7K
@
1
2
G
D
S
Q100
2N7002KW_SOT323-3
G
D
S
Q100
2N7002KW_SOT323-3
2
13
R1121
100K_0402_5%
DS3@R1121
100K_0402_5%
DS3@
12
C842
0.01U_0402_25V7K
C842
0.01U_0402_25V7K
1
2
R1503
R_short 0_0402_5%
R1503
R_short 0_0402_5%
12
G
D
S
Q146
2N7002KW_SOT323-3
G
D
S
Q146
2N7002KW_SOT323-3
2
13
C40
0.1U_0402_16V4Z
C40
0.1U_0402_16V4Z 1
2
R1453
0_0402_5%
@
R1453
0_0402_5%
@12
R1502
47K_0402_5%
R1502
47K_0402_5%
12
C1062
0.1U_0402_16V4Z
@C1062
0.1U_0402_16V4Z
@1
2
C839
10U_0805_10V6K
@C839
10U_0805_10V6K
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DC030006J00
3.3V
- +
RTC Battery
+5VS to +5VS_SLI
APDIN1APDIN
51ON-3
51ON-1
51ON-2
CHGRTCIN
51_ON#<53>
SLI_B+_ON#<32> SLI_5V_ON#<32>
VIN
VIN
VS
BATT+
+CHGRTC
+3VLP
+RTCBATT
+CHGRTC
B+_SLIB+
+5VS +5VS_SLI
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Vin Detector
Custom
56 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Vin Detector
Custom
56 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Vin Detector
Custom
56 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC113
10U_0603_6.3V6M
SLI@
PC113
10U_0603_6.3V6M
SLI@
1
2
PJ102
JUMP_43X79
@
PJ102
JUMP_43X79
@
1
122
PR113
47K_0402_1%
SLI@
PR113
47K_0402_1%
SLI@
1 2
JRTC1
MAXEL_ML1220T10@
JRTC1
MAXEL_ML1220T10@
12
PC107
10U_0603_6.3V6M
@
PC107
10U_0603_6.3V6M
@
12
PC109
0.22U_0603_25V7K
SLI@
PC109
0.22U_0603_25V7K
SLI@
1 2
PC104
1000P_0402_50V7K
PC104
1000P_0402_50V7K
12
PL101
SMB3025500YA_2P
PL101
SMB3025500YA_2P
1 2
PR111
200K_0402_1%
SLI@
PR111
200K_0402_1%
SLI@
1 2
PR103
200_0402_1%
@PR103
200_0402_1%
@
1 2
PD104
RB751V-40_SOD323-2
PD104
RB751V-40_SOD323-2
1 2
PD101
LL4148_LL34-2
@
PD101
LL4148_LL34-2
@
1 2
PR102
68_1206_5%
@
PR102
68_1206_5%
@
12
PR108
0_0402_5%
PR108
0_0402_5%
1 2
PR105
22K_0402_1%
@PR105
22K_0402_1%
@
1 2
PR106
560_0603_5%
PR106
560_0603_5%
1 2
PF101
12A_65V_451012MRL
PF101
12A_65V_451012MRL
21
PR109
200_0603_5%@
PR109
200_0603_5%@
12
PU101
APL5156-33DI-TRL_SOT89-3
@PU101
APL5156-33DI-TRL_SOT89-3
@
VIN 2
GND
1
VOUT
3
PC110
0.1U_0603_25V7K
SLI@
PC110
0.1U_0603_25V7K
SLI@
12
S
G
D
PQ103 AO6409L_TSOP6
SLI@
S
G
D
PQ103 AO6409L_TSOP6
SLI@
3
6
2
5
1
4
PC101
1000P_0402_50V7K
PC101
1000P_0402_50V7K
12
PC105
0.22U_0603_25V7K
@
PC105
0.22U_0603_25V7K
@
1 2
PC111
0.1U_0402_16V4Z
SLI@
PC111
0.1U_0402_16V4Z
SLI@
1
2
PQ101
TP0610K-T1-E3_SOT23-3
@PQ101
TP0610K-T1-E3_SOT23-3
@
2
13
PR110
200K_0402_1%
SLI@
PR110
200K_0402_1%
SLI@
1 2
PQ102
AON7403L_DFN8-5
SLI@
PQ102
AON7403L_DFN8-5
SLI@
3
52
4
1
PD102
LL4148_LL34-2
@
PD102
LL4148_LL34-2
@
12
PR104
100K_0402_1%
@
PR104
100K_0402_1%
@
12
PR101
68_1206_5%
@
PR101
68_1206_5%
@
12
PJ101
JUMP_43X39@
PJ101
JUMP_43X39@
1
122
JDCIN1
4602-Q04C-09R 4P P2.5@
JDCIN1
4602-Q04C-09R 4P P2.5@
11
33
44
22
PC102
100P_0402_50V8J
PC102
100P_0402_50V8J
12
PC103
100P_0402_50V8J
PC103
100P_0402_50V8J
12
PR112
47K_0402_1%
SLI@PR112
47K_0402_1%
SLI@
1 2
PR107
560_0603_5%
PR107
560_0603_5%
1 2
PC106
0.1U_0603_25V7K
@
PC106
0.1U_0603_25V7K
@
12
PC112
0.01U_0402_16V7K
SLI@
PC112
0.01U_0402_16V7K
SLI@
1
2
PC108
1U_0805_25V6K
@
PC108
1U_0805_25V6K
@
12
PD103
RB751V-40_SOD323-2
PD103
RB751V-40_SOD323-2
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
PH1 under CPU botten side :
PR222
4.42K:90W
9.1K:120W
16.5K:170W
PR221
57.6K:90W
82.5K:120W
76.8K:170W
3V--- 90W
1.5V--- 120W
0V--- 170W
EC_SMDA
EC_SMCA
TURBO_V_1
ADP_OCP_1
ADP_OCP_2
OTP_N_003
NTC_V_1
OTP_N_002
BATT_OUT <59>
BATT_TEMP <47>
EC_SMB_DA1 < 34,47,51,59>
EC_SMB_CK1 < 34,47,51,59>
BATT_LEN#<47>
PROCHOT#<47> MAINPWON <47,60>
H_PROCHOT#<6,47>
ADP_I<47,59>
AD_ID <47>
NTC_V
<47>
TURBO_V
<47>
SPOK<60>
PCH_PWR_EN<47,56>
VMB2
+3VALW+3VALW
P2
BATT+
VMB
+3VALW
VMB2
+VSBP
B+
+VSBP +VSB
+3VLP
VL
+3VS
+CHGRTC
+3VALW
+3VALW
+3VL
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
BATTERY CONN/OTP
Custom
57 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
BATTERY CONN/OTP
Custom
57 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
BATTERY CONN/OTP
Custom
57 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PJ201
JUMP_43X39@
PJ201
JUMP_43X39@
1
122
PR227
100K_0402_5%
PR227
100K_0402_5%
12
PR230
0_0402_5%
PR230
0_0402_5%
1 2
PR207
10K_0402_1%
PR207
10K_0402_1%
12
PR222
4.42K_0402_1%
PR222
4.42K_0402_1%
1 2
PC205
0.22U_0603_25V7K
PC205
0.22U_0603_25V7K
12
PR223
10K_0402_1%
PR223
10K_0402_1%
1 2
PR231
0_0402_5%
PR231
0_0402_5%
1 2
PR229
10K_0402_1%
PR229
10K_0402_1%
1 2
PR213
10K_0402_1%
PR213
10K_0402_1%
12
PR221
57.6K_0402_1%@
PR221
57.6K_0402_1%@
1 2
G
D
S
PQ201
2N7002KW_SOT323-3
@
G
D
S
PQ201
2N7002KW_SOT323-3
@2
13
PR217
100K_0402_1%
PR217
100K_0402_1%
12
G
D
S
PQ203
2N7002KW_SOT323-3
G
D
S
PQ203
2N7002KW_SOT323-3
2
13
PU202A
AS393MTR-E1 SO 8P OP
PU202A
AS393MTR-E1 SO 8P OP
+
3
-
2O1
P8
G
4
PR212
100K_0402_1%
PR212
100K_0402_1%
1 2
PR206
150K_0402_1%
PR206
150K_0402_1%
1 2
PR215
0_0402_5%
@PR215
0_0402_5%
@
1 2
PL201
SMB3025500YA_2P
PL201
SMB3025500YA_2P
1 2
PR233
1K_0402_1%
PR233
1K_0402_1%
1 2
PC201
1000P_0402_50V7K
PC201
1000P_0402_50V7K
12
PR226
21.5K_0402_1%
@
PR226
21.5K_0402_1%
@
12
PH201
100K_0402_1%_NCP15WF104F03RC
PH201
100K_0402_1%_NCP15WF104F03RC
12
PF201
12A_65V_451012MRL
PF201
12A_65V_451012MRL
21
PR228
100K_0402_5%47W@
PR228
100K_0402_5%47W@
12
PR232
0_0402_5%
PR232
0_0402_5%
1 2
PQ202
TP0610K-T1-E3_SOT23-3
PQ202
TP0610K-T1-E3_SOT23-3
2
13
PR224
10K_0402_1%
@
PR224
10K_0402_1%
@
12
PC202
0.01U_0402_25V7K
PC202
0.01U_0402_25V7K
12
PR211
100K_0402_1%
PR211
100K_0402_1%
1 2
PC204
1U_0402_6.3V6K
PC204
1U_0402_6.3V6K
12
PR203
6.49K_0402_1%
PR203
6.49K_0402_1%
1 2
PR202
100_0402_1%
PR202
100_0402_1%
12
PR220
0_0402_5%
@
PR220
0_0402_5%
@
12
JBATT1
TYCO_1775789-1
@
JBATT1
TYCO_1775789-1
@
11
33
44
55
66
GND 8
GND 9
22
77
G
D
S
PQ204
2N7002KW_SOT323-3
G
D
S
PQ204
2N7002KW_SOT323-3
2
13
PC203
0.01U_0402_25V7K
PC203
0.01U_0402_25V7K
12
G
D
S
PQ205
2N7002KW_SOT323-3
G
D
S
PQ205
2N7002KW_SOT323-3
2
13
PR216
22K_0402_1%
PR216
22K_0402_1%
1 2
PR214
200K_0402_1%
@PR214
200K_0402_1%
@
1 2
PU201
G718TM1U_SOT23-8
@
PU201
G718TM1U_SOT23-8
@RHYST2 5
OT1
3
OT2
4
GND
2
VCC
1
TMSNS2 6
RHYST1 7
TMSNS1 8
PR210
100K_0402_1%
PR210
100K_0402_1%
1 2
PC207
0.1U_0603_25V7K
@
PC207
0.1U_0603_25V7K
@
12
PR219
0_0402_5%
@PR219
0_0402_5%
@
1 2
PC206
0.1U_0603_25V7K
PC206
0.1U_0603_25V7K
12
PR209
10M_0402_5%
PR209
10M_0402_5%
1 2
PR218
100K_0402_1%
@
PR218
100K_0402_1%
@
1 2
PR204
10K_0402_5%
PR204
10K_0402_5%
1 2
PR225
13.7K_0402_1%
PR225
13.7K_0402_1%
12
PR205
255K_0402_1%
PR205
255K_0402_1%
1 2
PR201
100_0402_1%
PR201
100_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For disable pre-charge circuit.
Charge Option() bit[8]=1
DISCHG_G
DL_CHG
P2-2
LX_CHG
ACOFF-1
PACIN
VIN
BST_CHG
ACOFF-1
DH_CHG
6251_SN
P2-1
CHGCHG
DISCHG_G-1
PACIN
BM#
ACPRN
BATT_OUT
PACIN
ACP ACN
ACOFF<47>
BATT_OUT <58>
EC_SMB_DA1
<41,47,51,58>
EC_SMB_CK1
<41,47,51,58>
ADP_I<47,59>
ACPRN
<60>
ACIN <47>
VIN
P2
P3
VIN
BATT+
B+
CHG_B+
+3VALW P
+3VALW P
P2
BQ24737_VDD
BQ24737_VDD
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CHARGER
Custom
58 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CHARGER
Custom
58 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CHARGER
Custom
58 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PR306
10K_0402_5%
PR306
10K_0402_5%
1 2
PC315
10U_0805_25V6K
PC315
10U_0805_25V6K
12
PQ302
AO4423L 1P SO8
PQ302
AO4423L 1P SO8
3 6
5
7
8
2
4
1
PQ311
AON7408L_DFN8-5
PQ311
AON7408L_DFN8-5
4
5
1
2
3
PL301
4.7UH_PCMB104E-4R7MS_10A_20%
PL301
4.7UH_PCMB104E-4R7MS_10A_20%
1 2
PR322
2.2_0603_5%
PR322
2.2_0603_5%
1 2
PR328
47K_0402_1%
PR328
47K_0402_1%
12
PC303
0.1U_0603_25V7K
@PC303
0.1U_0603_25V7K
@
1 2
PR313
100K_0402_1%
PR313
100K_0402_1%
12
PQ303
DTA144EUA_SC70-3
PQ303
DTA144EUA_SC70-3
2
1 3
PU301
BQ24737RGRR_VQFN20_3P5X3P5
PU301
BQ24737RGRR_VQFN20_3P5X3P5
ACOK 5
ACN 1
SDA
8
IOUT
7
PHASE 19
LODRV
15
SRN
12
BM
11
REGN 16
ACDET
6
ACP 2
CMPOUT 3
CMPIN 4
GND
14
SRP
13
BTST 17
HIDRV 18
VCC 20
TP 21
SCL
9
ILIM
10
PR309
64.9K_0603_1%
PR309
64.9K_0603_1%
1 2
PQ309
DTC115EUA_SC70-3
PQ309
DTC115EUA_SC70-3
2
13
PC317
0.1U_0603_25V7K
PC317
0.1U_0603_25V7K
12
PR3270.01_2512_1% PR3270.01_2512_1%
1
3
4
2
PR325
47K_0402_1%
PR325
47K_0402_1%
1 2
PR314
39.2K_0402_1%
@PR314
39.2K_0402_1%
@
12
PQ306
DTC115EUA_SC70-3
PQ306
DTC115EUA_SC70-3
2
13
PC318
2200P_0402_50V7K
PC318
2200P_0402_50V7K
1 2
PC311
0.1U_0603_25V7K
PC311
0.1U_0603_25V7K
12
PC319
4.7U_0805_25V6-K
PC319
4.7U_0805_25V6-K
1 2
PC323
10U_0805_25V6K@
PC323
10U_0805_25V6K@
1 2
PR316
4.7M_0603_1%
@PR316
4.7M_0603_1%
@
1 2
PR331
12K_0402_1%
PR331
12K_0402_1%
12
PQ307A
2N7002KDW -2N_SOT363-6
PQ307A
2N7002KDW -2N_SOT363-6
61
2
PR308
390K_0603_1%
PR308
390K_0603_1%
12
PC320
4.7U_0805_25V6-K
PC320
4.7U_0805_25V6-K
1 2
PQ301
AO4423L 1P SO8
PQ301
AO4423L 1P SO8
36
5
7
8
2
4
1
PD301
RB751V-40_SOD323-2
PD301
RB751V-40_SOD323-2
12
PC307
0.1U_0603_25V7K
PC307
0.1U_0603_25V7K
12
PC305
100P_0603_50V8
PC305
100P_0603_50V8
1 2
PR329
10K_0402_1%
PR329
10K_0402_1%
12
PC316
10U_0805_25V6K
PC316
10U_0805_25V6K
12
PC306
0.1U_0603_25V7K
PC306
0.1U_0603_25V7K
12
PR319
6.8_0603_5%
PR319
6.8_0603_5%
12
PC308
1U_0603_25V6
PC308
1U_0603_25V6
12
PR332
0.01_2512_1%
PR332
0.01_2512_1%
1
3
4
2
PC309
0.047U_0603_16V7K
PC309
0.047U_0603_16V7K
12
PC314
680P_0603_50V7K
PC314
680P_0603_50V7K
12
PR323
4.7_1206_5%
PR323
4.7_1206_5%
12
PR318
18K_0402_1%
PR318
18K_0402_1%
12
PC312
0.1U_0603_25V7K
PC312
0.1U_0603_25V7K
12
PQ307B
2N7002KDW -2N_SOT363-6
PQ307B
2N7002KDW -2N_SOT363-6
34
5
PR307
0_0402_5%
PR307
0_0402_5%
12
PQ310
AO4423L 1P SO8
PQ310
AO4423L 1P SO8
3 6
5
7
8
2
4
1
PR317
10K_0603_1%@
PR317
10K_0603_1%@
12
PQ305B
2N7002KDW-2N_SOT363-6
PQ305B
2N7002KDW-2N_SOT363-6
34
5
PQ312
AON7702L_DFN8-5
PQ312
AON7702L_DFN8-5
4
5
1
2
3
PC321
4.7U_0805_25V6-K
PC321
4.7U_0805_25V6-K
1 2
PD303
1SS355_SOD323-2
PD303
1SS355_SOD323-2
1 2
PR303
20K_0402_1%
PR303
20K_0402_1%
12
PC313
0.1U_0603_25V7K
PC313
0.1U_0603_25V7K
1 2
PC324
0.1U_0603_25V7K
@
PC324
0.1U_0603_25V7K
@
12
PR302
200K_0402_1%
PR302
200K_0402_1%
12
PR310
0_0402_5%
PR310
0_0402_5%
1 2
PL302
1UH_PCMB061H-1R0MS_7A_20%
PL302
1UH_PCMB061H-1R0MS_7A_20%
1 2
PQ308B
2N7002KDW-2N_SOT363-6
PQ308B
2N7002KDW-2N_SOT363-6
34
5
PC322
10U_0805_25V6K@
PC322
10U_0805_25V6K@
1 2
PR320
10_0603_5%
PR320
10_0603_5%
12
PD302
1SS355_SOD323-2
PD302
1SS355_SOD323-2
1 2
PC301
0.1U_0603_25V7K
PC301
0.1U_0603_25V7K
12
PR324
200K_0402_1%
PR324
200K_0402_1%
1 2
PR330
10K_0402_1%
PR330
10K_0402_1%
1 2
PR301
200K_0402_5%
PR301
200K_0402_5%
12
PQ308A
2N7002KDW -2N_SOT363-6
PQ308A
2N7002KDW -2N_SOT363-6
61
2
PC310
1U_0603_25V6
PC310
1U_0603_25V6
1 2
PR315
100K_0402_1%
@PR315
100K_0402_1%
@
1 2
PR326
10K_0402_1%
PR326
10K_0402_1%
1 2
PR321
10_1206_5%
PR321
10_1206_5%
1 2
PR312
147K_0402_1%
PR312
147K_0402_1%
1 2
PQ305A
2N7002KDW -2N_SOT363-6
PQ305A
2N7002KDW -2N_SOT363-6
61
2
PR305
47K_0402_1%
PR305
47K_0402_1%
1 2
PC302
2200P_0402_50V7K
PC302
2200P_0402_50V7K
1 2
PR311
0_0402_5%
PR311
0_0402_5%
1 2
PC304 .1U_0603_25V7KPC304 .1U_0603_25V7K
12
PR304
150K_0402_1%
PR304
150K_0402_1%
12
PQ304
DTC115EUA_SC70-3
PQ304
DTC115EUA_SC70-3
2
13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5VALWP
Imax=10A
OCP current 11.5~19.5A
TYP MAX
H/S Rds(on):22mohm , 30mohm
L/S Rds(on):10.8mohm , 13.6mohm
3VALWP
Imax=7.5A
OCP current 8.6A~13.92A
TYP MAX
H/S Rds(on): 22mohm , 30mohm
L/S Rds(on):10.8mohm ,13.6mohm
LG_3V
SW1_5V
FB_3V
UG_5V
BST_5V
LG_5V
SNUB_5V
5V_EN
BST_3V
UG_3V
SW2_3V
FB_5V
SNUB_3V
3V_EN
5V_EN
3V_EN
EC_ON
<47,53>
MAINPWON
<47,58>
SPOK
<58>
B++
+5VALWP
B++
B++
+3VALWP
B+
VL
+3VL
VS
VL
+3VALWP +3VALW
+5VALWP +5VALW
+3VLP
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
3VALWP/5VALWP
Custom
59 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
3VALWP/5VALWP
Custom
59 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
3VALWP/5VALWP
Custom
59 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC403
4.7U_0805_25V6-K
PC403
4.7U_0805_25V6-K
12
PC411
0.1U_0603_25V7K
PC411
0.1U_0603_25V7K
12
PR405
130K_0402_1%
PR405
130K_0402_1%
1 2
PC415
0.1U_0603_25V7K
PC415
0.1U_0603_25V7K
1 2
G
D
S
PQ405
2N7002KW_SOT323-3
@
G
D
S
PQ405
2N7002KW_SOT323-3
@
2
13
PC414
0.1U_0402_25V6
PC414
0.1U_0402_25V6
12
PR410
2.2_0603_5%
PR410
2.2_0603_5%
1 2
PR411
30K_0402_1%
PR411
30K_0402_1%
1 2
PQ401
AO4466L_SO8
PQ401
AO4466L_SO8
4
6
1
2
3
5
7
8
PC404
2200P_0402_50V7K
PC404
2200P_0402_50V7K
12
PR409
4.7_1206_5%
PR409
4.7_1206_5%
12
PJ402
JUMP_43X118@
PJ402
JUMP_43X118@
11
2
2
PC420
10U_0805_25V6K
PC420
10U_0805_25V6K
12
+
PC408
330U_D2E_6.3VM_R25M
+
PC408
330U_D2E_6.3VM_R25M
1
2
PC402
4.7U_0805_25V6-K
PC402
4.7U_0805_25V6-K
12
PR418
316K_0402_1%
@
PR418
316K_0402_1%
@
1 2
PR404
0_0603_5%~D
PR404
0_0603_5%~D
1 2
PJ401
JUMP_43X118@
PJ401
JUMP_43X118@
11
2
2
PL402
3.3UH +-20% PCMB063T-3R3MS 6.5A
PL402
3.3UH +-20% PCMB063T-3R3MS 6.5A
12
PC405
0.1U_0603_25V7K
PC405
0.1U_0603_25V7K
12
PC423
4.7U_0603_6.3V6K
PC423
4.7U_0603_6.3V6K
12
PC413
0.1U_0603_25V7K
PC413
0.1U_0603_25V7K
1 2
PC412
680P_0603_50V7K
PC412
680P_0603_50V7K
12
PC422
0.1U_0402_25V6
@
PC422
0.1U_0402_25V6
@
1 2
PD401
LL4148_LL34-2
PD401
LL4148_LL34-2
1 2
TPS51225CRUKR_QFN20_3X3
PU401
TPS51225CRUKR_QFN20_3X3
PU401
CS1 1
VFB1 2
VREG3 3
VFB2 4
CS2 5
EN2
6
PGOOD
7
SW2
8
VBST2
9
DRVH2
10
DRVL2
11
VIN
12
VREG5
13
VO1 14
DRVL1
15
DRVH1 16
VBST1 17
SW1 18
VCLK 19
EN1
20
PAD 21
PR417
402K_0402_1%
PR417
402K_0402_1%
12
PC418
1U_0603_10V6K
PC418
1U_0603_10V6K
12
PR407
56K_0402_1%
PR407
56K_0402_1%
1 2
PR413
2.2K_0402_5%
PR413
2.2K_0402_5%
1 2
PC416
680P_0603_50V7K
PC416
680P_0603_50V7K
12
+
PC409
330U_D2E_6.3VM_R25M
+
PC409
330U_D2E_6.3VM_R25M
1
2
PR414 0_0402_5%PR414 0_0402_5%
1 2
PC417
10U_0805_25V6K
@
PC417
10U_0805_25V6K
@
12
PR412
4.7_1206_5%
PR412
4.7_1206_5%
12
PR420
330_0402_5%
@PR420
330_0402_5%
@
1 2
PQ404
AO4456_SO8
PQ404
AO4456_SO8
4
7
8
6
5
1
2
3
PQ403
AO4712_SO8
PQ403
AO4712_SO8
3 6
5
7
8
2
4
1
PL401
4.7UH_VMPI1004AR-4R7M-Z01_10A_20%
PL401
4.7UH_VMPI1004AR-4R7M-Z01_10A_20%
1 2
PR419
100K_0402_5%
@PR419
100K_0402_5%
@
12
PC419
2200P_0402_50V7K
PC419
2200P_0402_50V7K
12
PC410
0.1U_0402_25V6
@
PC410
0.1U_0402_25V6
@
1 2
PQ402
AO4406AL_SO8
PQ402
AO4406AL_SO8
3 6
5
7
8
2
4
1
PC421
1U_0603_10V5K
PC421
1U_0603_10V5K
12
PD402
LL4148_LL34-2
@PD402
LL4148_LL34-2
@
12
PR408
20K_0402_1%
PR408
20K_0402_1%
1 2
PR416
1M_0402_1%
@PR416
1M_0402_1%
@
1 2
PJ403
JUMP_43X118@
PJ403
JUMP_43X118@
11
2
2
PR402
2.2_0603_5%
PR402
2.2_0603_5%
1 2
PR406
0_0603_5%~D
PR406
0_0603_5%~D
1 2
PR401
13K_0402_1%
PR401
13K_0402_1%
1 2
PR403
20K_0402_1%
PR403
20K_0402_1%
1 2
PC401
0.1U_0603_25V7K
PC401
0.1U_0603_25V7K
12
PR415 0_0402_5%PR415 0_0402_5%
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
B+_1.35V
SNB_1.35V
DH_1.35V
VIN_1.35V
VIN_0.675V
CS_1.35V
VDD_1.35V
S5_1.35V
VDDQ_1.35V
VTTSNS_0.675V
VDDP_1.35V
BST_1.35V
TON_1.35V
DL_1.35V
FB_1.35V
B+_1.35V
VTTREF_0.675V
S3_1.35V
LX_1.35V
SYSON
<47>
SUSP#<32,47,56,62,63>
VDDQ_PGOOD
<47>
SUSP#_PWR<61,62>
+1.35VP +1.35V
+0.675VSP +0.675VS
+1.35VP
B+
+1.35VP+5VALW
+0.675VSP
+1.35VP
+1.35VP
+5VALW
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
1.35VP/0.675VSP
Custom
60 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
1.35VP/0.675VSP
Custom
60 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
1.35VP/0.675VSP
Custom
60 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC509
1U_0603_10V6K
PC509
1U_0603_10V6K
12
PJ501
JUMP_43X118
PJ501
JUMP_43X118
12
PC503
2200P_0402_50V7K
PC503
2200P_0402_50V7K
12
PR532
10K_0402_5%
PR532
10K_0402_5%
12
PR502
5.1_0603_5%
PR502
5.1_0603_5%
1 2
PC508
1U_0603_10V6K
PC508
1U_0603_10V6K
12
PC514
10U_0805_6.3VAM
PC514
10U_0805_6.3VAM
1
2
PC504
10U_0805_25V6K
PC504
10U_0805_25V6K
12
PR510
10K_0402_1%
PR510
10K_0402_1%
12
PR505
0_0402_5%
PR505
0_0402_5%
1 2
PQ502
SISA12DN-T1-GE3
PQ502
SISA12DN-T1-GE3
3 5
2
4
1
PR519
0_0402_5%
PR519
0_0402_5%
12
PR504
2.2_0603_5%
PR504
2.2_0603_5%
1 2
PC513
0.033U_0402_16V7K
PC513
0.033U_0402_16V7K
12
PC510
0.22U_0402_10V6K
PC510
0.22U_0402_10V6K
1 2
PR501
4.7_1206_5%
PR501
4.7_1206_5%
12
PR540
0_0402_5%
@PR540
0_0402_5%
@
1 2
PC525
100P_0402_50V8J
PC525
100P_0402_50V8J
1 2
PR514
0_0402_5%
PR514
0_0402_5%
1 2
PR516
100K +-1% 0402
PR516
100K +-1% 0402
12
PC502
0.1U_0402_25V6
PC502
0.1U_0402_25V6
12
PQ501
SIS472DN-T1-GE3
PQ501
SIS472DN-T1-GE3
3 5
2
4
1
PR503
20.5K_0402_1%
PR503
20.5K_0402_1%
1 2
PR506
887K_0402_1%
PR506
887K_0402_1%
1 2
PC507
680P_0603_50V7K
PC507
680P_0603_50V7K
12
PU501
RT8207MZQW _WQFN20_3X3
PU501
RT8207MZQW _WQFN20_3X3
VTTSNS 2
FB
6
S5
8
PGOOD
10
VDDP
12
PHASE 16
BOOT 18
VTTREF 4
PGND
14
VTTGND 1
GND 3
VDDQ 5
S3
7
TON
9
VDD
11
CS
13
LGATE
15
UGATE 17
VTT 20
VLDOIN 19
PAD 21
PL502
2.2UH_VMPI0703AR-2R2M-Z01_8A_20%
PL502
2.2UH_VMPI0703AR-2R2M-Z01_8A_20%
1 2
PC501
68P_0402_50V8J
PC501
68P_0402_50V8J
12
PC517
0.1U_0402_10V7K
@PC517
0.1U_0402_10V7K
@
12
+
PC506
330U_D2_2.5VY_R15M
+
PC506
330U_D2_2.5VY_R15M
1
2
PR507
8.06K_0402_1%
PR507
8.06K_0402_1%
1 2
PC505
4.7U_0805_25V6-K
PC505
4.7U_0805_25V6-K
12
PC515
10U_0805_6.3VAM
PC515
10U_0805_6.3VAM
1
2
PC518
0.1U_0402_10V7K
@PC518
0.1U_0402_10V7K
@
12
PL501
HCB1608KF-121T30_0603
PL501
HCB1608KF-121T30_0603
1 2
PR531
0_0402_5%
PR531
0_0402_5%
12
PJ502
JUMP_43X39
PJ502
JUMP_43X39
11
2
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
VFB=0.8V
Vo=VFB*(1+PR522/PR539)
EN_1.5VSP
SUSP#_PWR
BST_1.5VSP_VGA-1
SNUB_1.5V
SUSP#
<32,47,56,61,62,63>
SUSP#<32,47,57,61,62,63>
FBVDDQ_PWR_EN<27>
VDDQ_SENSE <25>
SUSP<34>
SUSP#_PWR
<60,62>
SUSP#_PWR<60,61,62>
+1.5VS+1.5VSP
+5VS
+1.5VSP
+5VS
+3VALW
+1.5VSP_VGA +1.5VS_VGA
+1.5VSP_VGA
+3VL
B+
+5VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.5VS_VGA/+1.5VS
Custom
61 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.5VS_VGA/+1.5VS
Custom
61 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.5VS_VGA/+1.5VS
Custom
61 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PR518
11.5K_0402_1%
PR518
11.5K_0402_1%
1 2
PJ505
JUMP_43X118@
PJ505
JUMP_43X118@
11
2
2
PQ504
MDV1525URH_PDFN33-8-5
PQ504
MDV1525URH_PDFN33-8-5
4
5
1
2
3
G
D
S
PQ503
2N7002KW_SOT323-3
@
G
D
S
PQ503
2N7002KW_SOT323-3
@
2
13
PR538
0_0402_5%
@PR538
0_0402_5%
@
1 2
PL503
1UH_PCMB063T-1R0MS_12A_20%
PL503
1UH_PCMB063T-1R0MS_12A_20%
1 2
PU504
APL5912-KAC-TRL_SO8
PU504
APL5912-KAC-TRL_SO8
GND
1
VOUT 4
POK
7
EN
8
VCNTL 6
VIN 5
VOUT 3
FB 2
VIN 9
PR517
10K_0402_1%
PR517
10K_0402_1%
12
+
PC56
220U_B2_6.3VM_R15M
+
PC56
220U_B2_6.3VM_R15M
1
2
PR522
39.2K_0402_1%
PR522
39.2K_0402_1%
12
PD502
RB751V-40_SOD323-2
PD502
RB751V-40_SOD323-2
1 2
PC537
0.1U_0402_25V6
PC537
0.1U_0402_25V6
12
PR521
4.7_1206_5%
@
PR521
4.7_1206_5%
@
12
PC530
.1U_0402_16V7K
@
PC530
.1U_0402_16V7K
@
12
PR535
0_0402_5%
PR535
0_0402_5%
1 2
PC58
0.1U_0402_10V7K
PC58
0.1U_0402_10V7K
1 2
PC549
1U_0402_6.3V6K
PC549
1U_0402_6.3V6K
12
PC529
0.22U_0603_16V7K
PC529
0.22U_0603_16V7K
1 2
PR529
2.2_0603_5%
PR529
2.2_0603_5%
1 2
PJ503
JUMP_43X118
@
PJ503
JUMP_43X118
@
11
2
2
PC545
.1U_0603_25V7K
PC545
.1U_0603_25V7K
12
PC546
4.7U_0805_6.3V6K
PC546
4.7U_0805_6.3V6K
12
PJ508
JUMP_43X79
@
PJ508
JUMP_43X79
@
11
2
2
PR523
1M_0402_1%
@
PR523
1M_0402_1%
@
1 2
PU502
TPS51212DSCR_SON10_3X3
PU502
TPS51212DSCR_SON10_3X3
EN
3
TRIP
2
V5IN 7
DRVH 9
SW 8
DRVL 6
VBST 10
RF
5
VFB
4
PGOOD
1
TP 11
PC548
0.01U_0402_25V7K
PC548
0.01U_0402_25V7K
12
PR537
100K_0402_5%
@PR537
100K_0402_5%
@
12
PC542
1U_0603_10V6K
PC542
1U_0603_10V6K
12
PR534
0_0402_5%
PR534
0_0402_5%
12
PC538
2200P_0402_50V7K
PC538
2200P_0402_50V7K
12
PC547
22U_0805_6.3V6M
PC547
22U_0805_6.3V6M
12
PC526
680P_0603_50V7K
@
PC526
680P_0603_50V7K
@
12
PR526
75K_0402_1%
PR526
75K_0402_1%
12
PJ504
JUMP_43X118@
PJ504
JUMP_43X118@
11
2
2
PR539
44.2K_0402_1%
PR539
44.2K_0402_1%
12
PC536
10U_0805_25V6K
PC536
10U_0805_25V6K
12
PR536
0_0402_5%
@
PR536
0_0402_5%
@
12
PR525
0_0402_5%
PR525
0_0402_5%
1 2
PC539
470P_0603_50V7K
PC539
470P_0603_50V7K
12
PR524
0_0402_5%
@
PR524
0_0402_5%
@
1 2
PR533
0_0402_5%
PR533
0_0402_5%
1 2
PQ505
AON6504_POWERDFN56-8-5
PQ505
AON6504_POWERDFN56-8-5
4
5
1
2
3
PC528
10U_0805_25V6K
PC528
10U_0805_25V6K
12
PR520
20K_0402_1%
PR520
20K_0402_1%
1 2
PR527
470K_0402_1%
PR527
470K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VFB=0.6V
Vo=VFB*(1+PR706/PR705)
FB=0.6Volt
1.05VMP_FB
1.05VMP_LX
1.05VMP_VIN
EN_1.05VMP
SUSP#<32,47,56,61,62,63>
DGPU_PWROK<19,27,55,64>
SUSP#<32,47,56,61,62,63>
SUSP#_PWR<60,61>
SUS_VCCP<47>
+1.05VS+1.05VS_VCCPP
+1.05VS_VCCPP
+5VALW
+3VS
+1.05VS_VGA+1.05VSP_VGA
+3VALW +1.05VSP_VGA
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.05VS/+1.05VS_VGA
Custom
62 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.05VS/+1.05VS_VGA
Custom
62 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
+1.05VS/+1.05VS_VGA
Custom
62 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PJ703
JUMP_43X39
@
PJ703
JUMP_43X39
@
11
2
2
PC708
22U_0805_6.3V6M
PC708
22U_0805_6.3V6M
12
PU702
SY8032ABC_SOT23-6
PU702
SY8032ABC_SOT23-6
IN
4
PG
5
LX 3
FB
6EN 1
GND 2
PC706
22U_0805_6.3V6M
PC706
22U_0805_6.3V6M
12
PR712
0_0402_5%
@
PR712
0_0402_5%
@
1 2
PR701
0_0402_5%
@PR701
0_0402_5%
@
1 2
PC705
22U_0805_6.3V6M
PC705
22U_0805_6.3V6M
12
PR716
10_0402_5%
PR716
10_0402_5%
12
PR717
0_0402_5%
@PR717
0_0402_5%
@
1 2
PJ704
JUMP_43X79@
PJ704
JUMP_43X79@
11
2
2
PR710
1M_0402_5%
PR710
1M_0402_5%
1 2
PC704
680P_0603_50V7K
PC704
680P_0603_50V7K
12
PR713
10K_0402_5%
PR713
10K_0402_5%
1 2
PL701
S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
PL701
S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
1 2
PR706
75K_0402_1%
PR706
75K_0402_1%
12
PC711
68P_0402_50V8J
PC711
68P_0402_50V8J
12
PC701
.1U_0402_16V7K
@
PC701
.1U_0402_16V7K
@
12
PD701
RB751V-40_SOD323-2
PD701
RB751V-40_SOD323-2
1 2
PC714
22U_0805_6.3VAM
PC714
22U_0805_6.3VAM
12
PR709
0_0402_5%
PR709
0_0402_5%
1 2
PJ701
JUMP_43X118@
PJ701
JUMP_43X118@
11
2
2
PC707
22U_0805_6.3V6M
PC707
22U_0805_6.3V6M
12
PR714
0_0402_5%
PR714
0_0402_5%
12
PC716
22U_0805_6.3VAM
PC716
22U_0805_6.3VAM
12
PR702
47K_0402_5%
@PR702
47K_0402_5%
@
1 2
PC718
1U_0402_16V6K
PC718
1U_0402_16V6K
12
PR705
100K_0402_1%
PR705
100K_0402_1%
12
PC710
22U_0805_6.3VAM
PC710
22U_0805_6.3VAM
12
PC713
22U_0805_6.3VAM
PC713
22U_0805_6.3VAM
12
PC703
.1U_0402_16V7K
PC703
.1U_0402_16V7K
12
PR704
4.7_1206_5%
PR704
4.7_1206_5%
12
PC717
22U_0805_6.3V6M
PC717
22U_0805_6.3V6M
12
PC715
0.1U_0402_10V7K
@PC715
0.1U_0402_10V7K
@
12
PC702
22U_0805_6.3V6M
PC702
22U_0805_6.3V6M
12
PJ702
JUMP_43X118@
PJ702
JUMP_43X118@
1
122
PR708
75K_0402_1%
PR708
75K_0402_1%
12
PU701
SY8036LDBC_DFN10_3X3
PU701
SY8036LDBC_DFN10_3X3
EN
5
PG 4
LX 3
FB 6
SVIN
8
TP
11
LX 2
PVIN
10
SS
7
PVIN
9
LX
1
PR711
100K_0402_1%
PR711
100K_0402_1%
12
PR703
10K_0402_5%
PR703
10K_0402_5%
1 2
PR715
0_0402_5%
PR715
0_0402_5%
12
PR718
0_0402_5%
PR718
0_0402_5%
1 2
PL702
1UH_PH041H-1R0MS_3.8A_20%
PL702
1UH_PH041H-1R0MS_3.8A_20%
1 2
PC709
22P_0402_50V8J
PC709
22P_0402_50V8J
12
PC712
680P_0603_50V7K
PC712
680P_0603_50V7K
12
PR707
4.7_1206_5%
PR707
4.7_1206_5%
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
Near VGA Core
Under VGA Core
N14P-GT 35W
Ipeak=50A
Imax=35A
Iocp=64.8A
Fsw=450KHz
bulk cap 330uF 9m *5
GB4-128 package
Thermistor near MOSFET
trigger point 97 degree C.
N14P-GS 25W
Ipeak=36A
Imax=25A
Iocp=64.8A
Fsw=450KHz
bulk cap 330uF 9m *3
PR805 = 34K ==>Fsw = 450KHz
BOOT2_2_VGA
SNUB2_VGA
BOOT1_2_VGA
PHASE2_VGA
BOOT1_VGA
SNUB1_VGA
UGATE1_2_VGA
UGATE2_2_VGA
PHASE1_VGA
PVCC_VGA
UGATE1_VGA
BOOT2_VGA
UGATE2_VGA
VIDBUF
VREF
FS
FB2_VGA
COMP_VGAFB1_VGA
VSS_SEN
VREF
FB_VGA
PSI_VGA
GPU_VID
VCC_VGA
VCC_SEN
VREF
EN_VGA
LGATE1_VGA
LGATE2_VGA
VCCSENSE_VGA<24>
VSSSENSE_VGA<24>
DGPU_PWROK
<19,27,55,63>
DPRSLPVR_VGA
<23>
NVVDD PWM_VID
<23>
NVDD_PWR_EN <14>
+VGA_B+
B+
+VGA_B+
+5VS
+VGA_CORE
+VGA_CORE
+VGA_CORE
+VGA_CORE
+5VS
+3VS
+3VS_VGA
+3VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA_CORE
Custom
63 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA_CORE
Custom
63 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
VGA_CORE
Custom
63 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PR805
34K_0402_1%
PR805
34K_0402_1%
12
PC807
4.7U_0603_6.3V6M
PC807
4.7U_0603_6.3V6M
12
PU801
NCP81172MNTWG_QFN24_4X4
PU801
NCP81172MNTWG_QFN24_4X4
BST1 1
HG1 2
EN 3
PSI 4
VID 5
VIDBUF 6
REFIN
7
VREF
8
FS
9
FBRTN
10
FB
11
COMP
12
TSNS
13
TALERT#
14
VCC
15
PGOOD
16
HG2
17
BST2
18
PH2 19
LG2 20
PVCC 21
PGND 22
LG1 23
PH1 24
GND
25
PC811
4.7U_0603_6.3V6M
@
PC811
4.7U_0603_6.3V6M
@
12
PC824
4.7U_0603_6.3V6M
@
PC824
4.7U_0603_6.3V6M
@
12
PC839
4.7U_0603_10V6K
PC839
4.7U_0603_10V6K
1 2
PC802
4.7U_0603_6.3V6M
PC802
4.7U_0603_6.3V6M
12
PR825
0_0402_5%
PR825
0_0402_5%
12
PR806 0_0402_5%PR806 0_0402_5%
1 2
PC816
0.1U_0402_10V7K
PC816
0.1U_0402_10V7K
12
PC830
47U_0805_6.3V6M
PC830
47U_0805_6.3V6M
12
PQ801
FDMS7698
PQ801
FDMS7698
4
5
1
2
3
PC841
2200P_0402_50V7K
PC841
2200P_0402_50V7K
12
PR833
2.2_0402_5%
@PR833
2.2_0402_5%
@
12
PC834
10U_0805_25V6K
PC834
10U_0805_25V6K
12
PC843
10U_0805_25V6K
PC843
10U_0805_25V6K
12
PC844
680P_0402_50V7K@
PC844
680P_0402_50V7K@
12
PC826
4.7U_0603_6.3V6M
@
PC826
4.7U_0603_6.3V6M
@
12
PC847
0.22U_0603_10V7K
PC847
0.22U_0603_10V7K
1 2
PQ807
FDMC0310AS
PQ807
FDMC0310AS
4
5
1
2
3
PR802 0_0402_5%PR802 0_0402_5%
1 2
PC833
10U_0805_25V6K
PC833
10U_0805_25V6K
12
PR818
0_0402_5%
PR818
0_0402_5%
12
PC815
0.1U_0402_10V7K
PC815
0.1U_0402_10V7K
12
PC822
4.7U_0603_6.3V6M
PC822
4.7U_0603_6.3V6M
12
PR821
0_0603_5%
PR821
0_0603_5%
12
+
PC846
330U_D2_2V_Y
+
PC846
330U_D2_2V_Y
1
2
PR819
4.7_1206_5%
@
PR819
4.7_1206_5%
@
12
PC827
4.7U_0603_6.3V6M
@
PC827
4.7U_0603_6.3V6M
@
12
PQ803
FDMS7698
PQ803
FDMS7698
4
5
1
2
3
+
PC836
330U_D2_2V_Y
+
PC836
330U_D2_2V_Y
1
2
PR808
10K_0402_1%
<BOM Structure>
PR808
10K_0402_1%
<BOM Structure>
1 2
PR812 5.9K_0402_1%PR812 5.9K_0402_1%
12
PC838
0.22U_0603_10V7K
PC838
0.22U_0603_10V7K
1 2
PC850 10P_0402_50V8JPC850 10P_0402_50V8J
1 2
PC859
2700P_0402_50V7-K
@PC859
2700P_0402_50V7-K
@
12
PC804
4.7U_0603_6.3V6M
PC804
4.7U_0603_6.3V6M
12
PQ802
FDMC0310AS
PQ802
FDMC0310AS
4
5
1
2
3
PC858
10P_0402_50V8J
PC858
10P_0402_50V8J
12
PL804
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
PL804
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
1 2
PR814 0_0402_5%PR814 0_0402_5%
12
PR828
5.1K_0402_1%
PR828
5.1K_0402_1%
12
PC821
4.7U_0603_6.3V6M
PC821
4.7U_0603_6.3V6M
12
PQ806
FDMC0310AS
PQ806
FDMC0310AS
4
5
1
2
3
PC835
680P_0402_50V7K
@PC835
680P_0402_50V7K
@
12
PH801
100K_0402_1%_NCP15WF104F03RC
PH801
100K_0402_1%_NCP15WF104F03RC
12
PR810
82K_0402_1%
PR810
82K_0402_1%
1 2
PC810
4.7U_0603_6.3V6M
PC810
4.7U_0603_6.3V6M
12
PC817
0.1U_0402_10V7K
PC817
0.1U_0402_10V7K
12
PC813
4.7U_0603_6.3V6M
@
PC813
4.7U_0603_6.3V6M
@
12
PR803
30K_0402_1%
PR803
30K_0402_1%
1 2
PC853
1000P_0402_50V7K
PC853
1000P_0402_50V7K
12
PR811 0_0402_5%PR811 0_0402_5%
1 2
PR813 10K_0402_5%PR813 10K_0402_5%
12
PC801
4.7U_0603_6.3V6M
PC801
4.7U_0603_6.3V6M
12
PR827
100K_0402_1%
PR827
100K_0402_1%
12
PC803
4.7U_0603_6.3V6M
PC803
4.7U_0603_6.3V6M
12
PL801
HCB2012KF-121T50_0805
PL801
HCB2012KF-121T50_0805
1 2
PC849
.1U_0402_16V7K
PC849
.1U_0402_16V7K
12
PR829
2K_0402_1%
PR829
2K_0402_1%
12
PD801
RB751V-40_SOD323-2
PD801
RB751V-40_SOD323-2
12
PR826
18K_0402_1%
PR826
18K_0402_1%
12
PR834
2.2_0402_5%
@PR834
2.2_0402_5%
@
12
PC823
4.7U_0603_6.3V6M
PC823
4.7U_0603_6.3V6M
12
PR816 10K_0402_5%PR816 10K_0402_5%
12
PC818
0.1U_0402_10V7K
PC818
0.1U_0402_10V7K
12
PR804 10K_0402_5%PR804 10K_0402_5%
1 2
PC806
4.7U_0603_6.3V6M
PC806
4.7U_0603_6.3V6M
12
PC814
4.7U_0603_6.3V6M
@
PC814
4.7U_0603_6.3V6M
@
12
PC856
2200P_0402_50V7K
PC856
2200P_0402_50V7K
12
PL803
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
PL803
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
1 2
PQ804
FDMC0310AS
PQ804
FDMC0310AS
4
5
1
2
3
PC808
4.7U_0603_6.3V6M
PC808
4.7U_0603_6.3V6M
12
PC819
4.7U_0603_6.3V6M
PC819
4.7U_0603_6.3V6M
12
+
PC845
330U_D2_2V_Y
+
PC845
330U_D2_2V_Y
1
2
PC809
4.7U_0603_6.3V6M
PC809
4.7U_0603_6.3V6M
12
G
D
S
PQ805
2N7002KW_SOT323-3
@
G
D
S
PQ805
2N7002KW_SOT323-3
@
2
13
PR801 0_0402_5%PR801 0_0402_5%
1 2
PC852
47P_0402_50V8J
PC852
47P_0402_50V8J
1 2
PC825
4.7U_0603_6.3V6M
@
PC825
4.7U_0603_6.3V6M
@
12
PC820
4.7U_0603_6.3V6M
PC820
4.7U_0603_6.3V6M
12
PC842
10U_0805_25V6K
PC842
10U_0805_25V6K
12
PC851
100P_0402_50V8J
PC851
100P_0402_50V8J
1 2
PR817
0_0603_5%
PR817
0_0603_5%
12
+
PC837
330U_D2_2V_Y
+
PC837
330U_D2_2V_Y
1
2
PR820
4.7_1206_5%
@PR820
4.7_1206_5%
@
12
PC855
.1U_0402_16V7K
PC855
.1U_0402_16V7K
1 2
PR822
0_0402_5%
PR822
0_0402_5%
12
PL802
HCB2012KF-121T50_0805
PL802
HCB2012KF-121T50_0805
1 2
PC831
0.1U_0402_25V6
PC831
0.1U_0402_25V6
12
PR807 0_0402_5%PR807 0_0402_5%
1 2
PC832
2200P_0402_50V7K
PC832
2200P_0402_50V7K
12
PR831
10K_0402_5%
PR831
10K_0402_5%
1 2
PR824
20K_0402_1%
PR824
20K_0402_1%
12
PR830 0_0402_5%PR830 0_0402_5%
12
PR823
20K_0402_1%
PR823
20K_0402_1%
12
PC812
4.7U_0603_6.3V6M
@
PC812
4.7U_0603_6.3V6M
@
12
PC805
4.7U_0603_6.3V6M
PC805
4.7U_0603_6.3V6M
12
PC854
0.01U_0603_50V7K
PC854
0.01U_0603_50V7K
1 2
PR809
51_0402_1%
PR809
51_0402_1%
1 2
PC829
22U_0805_6.3V6M
PC829
22U_0805_6.3V6M
1
2
PC840
0.1U_0402_25V6
PC840
0.1U_0402_25V6
12
PR832
100K_0402_5%
@
PR832
100K_0402_5%
@
12
PC848
1U_0402_10V6K
PC848
1U_0402_10V6K
1 2
PC828
4.7U_0603_6.3V6M
@
PC828
4.7U_0603_6.3V6M
@
12
PR815 2.2_0402_5%PR815 2.2_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Mount for 37W
37W=10K
47W=15.4K
Place close to
phase 2 MOSFET
37W=43K
47W=66.5K
NA for 37W
NA for 37W
Place close to
phase 1 inductir
37W=10K
47W=7.5K
CSSUM
CSREF
VR_SVID_CLK_1
VR_SVID_ALRT#_1
VR_SVID_DAT_1
CSP3
CSP1
CSP2
VR_HOT#_1
CSCOMP
VR_SVID_DAT_1
VR_SVID_ALRT#_1
VR_SVID_CLK_1
VSP
TSENSE
TSENSE
SWN1
SWN2
SWN3
VSN_2VSN_1
CSP2
VR_RDY
CSP3
CSP2
CSREF
CSREF
CSP1
SWN3 <66>
SWN2 <66>
SWN1 <66>
CSREF <66>
DRON <66>
81103_PWM <66>
SW3 <66>
HG3 <66>
LG3 <66>
LG1 <66>
HG1 <66>
SW1 <66>
VR_ON<47>
VR_SVID_DAT
<9>
VR_SVID_ALRT#
<9>
VR_SVID_CLK
<9>
VCCSENSE<9>
VSSSENSE<9>
VGATE
<6,15>
IMVP_IMON
<47>
VR_HOT#
<47>
+VCCIO_OUT
+3VS
CPU_B+
+5VALW
+5VALW
+5VALW
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
CPU_CORE
Custom
64 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
CPU_CORE
Custom
64 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
1.0
CPU_CORE
Custom
64 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC911
470P_0402_50V8-J
PC911
470P_0402_50V8-J
12
PC909
0.22U_0402_10V6K
PC909
0.22U_0402_10V6K
1 2
PR923
0_0402_5%
PR923
0_0402_5%
1 2
PR904
121K +-1% 060347W@
PR904
121K +-1% 060347W@
1 2
PR931
0_0402_5%
PR931
0_0402_5%
12
PR911
5.76K_0402_1%
47W@
PR911
5.76K_0402_1%
47W@
12
PR918
1K_0402_1%
PR918
1K_0402_1%
1 2
PR934
130_0402_1%
PR934
130_0402_1%
1 2
PC907
0.22U_0402_10V6K
PC907
0.22U_0402_10V6K
1 2
PR924
1K_0402_5%
PR924
1K_0402_5%
1 2
PR927
0_0402_5%
PR927
0_0402_5%
1 2
PR919
10K_0402_1%
37W@
PR919
10K_0402_1%
37W@
PC913
10P_0402_50V8J
PC913
10P_0402_50V8J
1 2
PR938
13K_0402_1%
PR938
13K_0402_1%
1 2
PR935
0_0402_5%
PR935
0_0402_5%
1 2
PR916
2.2_0603_5%
PR916
2.2_0603_5%
1 2
PC917
2.2U_0603_10V7K
PC917
2.2U_0603_10V7K
1 2
PR937
0_0402_5%
PR937
0_0402_5%
1 2
PC905
0.047U_0402_16V7K
47W@
PC905
0.047U_0402_16V7K
47W@
12
PC912
0.01U_0402_25V7K
PC912
0.01U_0402_25V7K
12
PU901
NCP81103MNTWG_QFN36_5X5
PU901
NCP81103MNTWG_QFN36_5X5
EN
1
VRHOT#
2
SDIO
3
ALERT#
4
ROSC
7
SCLK
5
CSCOMP 27
CSP3 24
CSREF 25
CSSUM 26
PVCC 15
BST3 19
HG3 18
SW3 17
LG3 16
PGND 14
COMP
31
VSP
35
FB
32
DIFFOUT
33
CSP1 22
VRMP
30
VR_RDY
6
DRON 21
VSN
34 LG1 13
SW1 12
VCC
36
IOUT
29
HG1 11
CSP2 23
TSENSE
8
ILIM
28
PWM2/IMAX 20
BST1 10
INT_SEL
9
GND
37
PR933
75_0402_1%
PR933
75_0402_1%
1 2
PR926
0_0402_5%
PR926
0_0402_5%
1 2
PR903
121K +-1% 0603
PR903
121K +-1% 0603
1 2
PR928
45.3K_0402_1%
PR928
45.3K_0402_1%
1 2
PR917
15.4K_0402_1%
47W@
PR917
15.4K_0402_1%
47W@
1 2
PH901
220K_0402_5%_ERTJ0EV224J
PH901
220K_0402_5%_ERTJ0EV224J
12
PR951
0_0402_5%
PR951
0_0402_5%
1 2
PR906
66.5K_0402_1%
47W@
PR906
66.5K_0402_1%
47W@
1 2
PC904
0.047U_0402_16V7K
PC904
0.047U_0402_16V7K
12
PC918
.1U_0402_16V7K
PC918
.1U_0402_16V7K
1 2
PC903
1000P_0402_50V7K
PC903
1000P_0402_50V7K
1 2
PC914
390P_0402_50V7K
PC914
390P_0402_50V7K
1 2
PR936
0_0402_5%
PR936
0_0402_5%
1 2
PR930
1.91K +-1% 0402
PR930
1.91K +-1% 0402
12
PR919
7.5K_0402_1%
47W@
PR919
7.5K_0402_1%
47W@
1 2
PR913
5.76K_0402_1%
PR913
5.76K_0402_1%
12
PH902
100K_0402_1%_TSM0B104F4251RZ
PH902
100K_0402_1%_TSM0B104F4251RZ
1 2
PC906
0.047U_0402_16V7K
PC906
0.047U_0402_16V7K
12
PR922
0_0402_5%
PR922
0_0402_5%
1 2
PR915
2.2_0603_5%
PR915
2.2_0603_5%
1 2
PR917
10K_0402_1%
37W@
PR917
10K_0402_1%
37W@
PR907
20K_0402_1%
@PR907
20K_0402_1%
@
1 2
PR914
0_0402_5%
37W@
PR914
0_0402_5%
37W@
12
PR908
20K_0402_1%
@PR908
20K_0402_1%
@
1 2
PR925
2_0603_5%
PR925
2_0603_5%
1 2
PC916
2200P_0402_50V7K
PC916
2200P_0402_50V7K
1 2
PC901
1000P_0402_50V7K
PC901
1000P_0402_50V7K
1 2
PC908
2.2U_0603_10V7K
PC908
2.2U_0603_10V7K
1 2
PR902
165K_0402_1%
PR902
165K_0402_1%
1 2
PR920
49.9_0402_1%
PR920
49.9_0402_1%
1 2
PR905
121K +-1% 0603
PR905
121K +-1% 0603
1 2
PC910
.1U_0402_16V7K
PC910
.1U_0402_16V7K
1 2
PC902
680P_0402_50V7K
PC902
680P_0402_50V7K
1 2
PR929
34.8K_0402_1%
PR929
34.8K_0402_1%
1 2
PR901
75K_0402_1%
PR901
75K_0402_1%
1 2
PR912
24.3K_0402_1%
PR912
24.3K_0402_1%
1 2
PR906
43K_0402_1%
37W@
PR906
43K_0402_1%
37W@
PC915
1000P_0402_50V7K
PC915
1000P_0402_50V7K
12
PR909
20K_0402_1%
@PR909
20K_0402_1%
@
1 2
PR932
54.9_0402_1%
PR932
54.9_0402_1%
1 2
PR910
5.76K_0402_1%
PR910
5.76K_0402_1%
12
PR921
1K_0402_1%
PR921
1K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Mount for 47W
CSREF
V1N_CPU
V3N_CPU
SNUB_CPU3
SNUB_CPU1
V2N_CPU CSREF
SNUB_CPU2
SW2
BSTA2 BSTA2_1
EN_VCORE2
HG2
LG2
VCC_VCORE2
CPU_B+
CPU_B+
HG1<65>
SWN3 <65>
SW1<65>
LG1<65>
HG3<65>
SW3<65>
LG3<65>
CSREF <65>
SWN1 <65>
SWN2 <65>
81103_PWM<65>
DRON<65>
+VCC_CORE
+VCC_CORE
CPU_B+
+VCC_CORE
+5VALW
B+
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU_CORE
65 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU_CORE
65 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
CPU_CORE
65 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC921
10U_0805_25V6K
PC921
10U_0805_25V6K
12
PL904
0.22UH +-20% PCMB104T-R22MS 35A
47W@
PL904
0.22UH +-20% PCMB104T-R22MS 35A
47W@
1
3
4
2
PC939
10U_0805_25V6K
47W@
PC939
10U_0805_25V6K
47W@
12
PC919
680P_0402_50V7K
PC919
680P_0402_50V7K
12
PR950
10_0402_1%
47W@
PR950
10_0402_1%
47W@
12
PC943
2200P_0402_50V7K
47W@
PC943
2200P_0402_50V7K
47W@
12
+
PC934
68U_25V_M_R0.36
+
PC934
68U_25V_M_R0.36
1
2
PL902
0.22UH +-20% PCMB104T-R22MS 35A
PL902
0.22UH +-20% PCMB104T-R22MS 35A
1
3
4
2
PQ905
AON6428L_DFN8-5
47W@PQ905
AON6428L_DFN8-5
47W@
4
5
1
2
3
PC924
2200P_0402_50V7K
PC924
2200P_0402_50V7K
12
PL901
FBMA-L11-453215-800LMA90T_1812
PL901
FBMA-L11-453215-800LMA90T_1812
1 2
PQ901
AON6428L_DFN8-5
PQ901
AON6428L_DFN8-5
4
5
1
2
3
PC942
0.1U_0402_25V6K
47W@
PC942
0.1U_0402_25V6K
47W@
12
PC941
10U_0805_25V6K
47W@
PC941
10U_0805_25V6K
47W@
12
PR946
2.2_0603_5%
47W@PR946
2.2_0603_5%
47W@
1 2
PR942
2.2_0603_1%
PR942
2.2_0603_1%
12
PC927
10U_0805_25V6K
PC927
10U_0805_25V6K
12
PC920
10U_0805_25V6K
PC920
10U_0805_25V6K
12
+
PC933
68U_25V_M_R0.36
+
PC933
68U_25V_M_R0.36
1
2
PR939
2.2_0603_1%
PR939
2.2_0603_1%
12
PC923
0.1U_0402_25V6K
PC923
0.1U_0402_25V6K
12
PC931
2200P_0402_50V7K
PC931
2200P_0402_50V7K
12
PR949
4.7_1206_5%
47W@
PR949
4.7_1206_5%
47W@
12
PR941
10_0402_1%
PR941
10_0402_1%
12
PC928
10U_0805_25V6K
PC928
10U_0805_25V6K
12
PC935
680P_0402_50V7K
PC935
680P_0402_50V7K
12
PQ904
AON6504_POWERDFN56-8-5
PQ904
AON6504_POWERDFN56-8-5
4
5
1
2
3
PQ902
AON6504_POWERDFN56-8-5
PQ902
AON6504_POWERDFN56-8-5
4
5
1
2
3
PC936
0.22U_0402_10V6K
47W@PC936
0.22U_0402_10V6K
47W@
12
PR945
2K_0402_1%
47W@
PR945
2K_0402_1%
47W@
12
PQ903
AON6428L_DFN8-5
PQ903
AON6428L_DFN8-5
4
5
1
2
3
PC930
0.1U_0402_25V6K
PC930
0.1U_0402_25V6K
12
PR944
10_0402_1%
PR944
10_0402_1%
12
PC922
10U_0805_25V6K
PC922
10U_0805_25V6K
12
PC938
680P_0402_50V7K
47W@
PC938
680P_0402_50V7K
47W@
12
PR947
2.2_0603_1%
47W@ PR947
2.2_0603_1%
47W@
12
PR943
4.7_1206_5%
PR943
4.7_1206_5%
12
PQ906
AON6504_POWERDFN56-8-5
47W@ PQ906
AON6504_POWERDFN56-8-5
47W@
4
5
1
2
3
PL903
0.22UH +-20% PCMB104T-R22MS 35A
PL903
0.22UH +-20% PCMB104T-R22MS 35A
1
3
4
2
PR940
4.7_1206_5%
PR940
4.7_1206_5%
12
PC940
10U_0805_25V6K
47W@
PC940
10U_0805_25V6K
47W@
12
PC929
10U_0805_25V6K
PC929
10U_0805_25V6K
12
220P_0402_50V7K
PC925@
220P_0402_50V7K
PC925@
12
PR948
0_0402_5%
47W@ PR948
0_0402_5%
47W@
12
NCP81151MNTBG_DFN8_2X2
PU902
47W@
NCP81151MNTBG_DFN8_2X2
PU902
47W@
BST
1
PWM
2
EN
3
VCC
4
FLAG 9
DRVH 8
SW 7
GND 6
DRVL 5
PC937
2.2U_0603_10V7K
47W@PC937
2.2U_0603_10V7K
47W@
12
68P_0402_50V8J
PC926@
68P_0402_50V8J
PC926@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
+VCC_CORE
+VCC_CORE
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PROCESSOR DECOUPLING
Custom
66 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PROCESSOR DECOUPLING
Custom
66 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PROCESSOR DECOUPLING
Custom
66 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
PC1022
22U_0805_6.3VAM
PC1022
22U_0805_6.3VAM
1
2
PC1024
22U_0805_6.3VAM
PC1024
22U_0805_6.3VAM
1
2
PC1023
22U_0805_6.3VAM
PC1023
22U_0805_6.3VAM
1
2
+
PC1030
470U_D2_2VM_R4.5M~D
+
PC1030
470U_D2_2VM_R4.5M~D
1
2
PC1015
22U_0805_6.3VAM
PC1015
22U_0805_6.3VAM
1
2
PC1009
10U_0805_6.3VAM
PC1009
10U_0805_6.3VAM
1
2
PC1010
10U_0805_6.3VAM
PC1010
10U_0805_6.3VAM
1
2
PC1027
22U_0805_6.3VAM
PC1027
22U_0805_6.3VAM
1
2
PC1001
10U_0805_6.3VAM
PC1001
10U_0805_6.3VAM
1
2
PC1017
22U_0805_6.3VAM
PC1017
22U_0805_6.3VAM
1
2
PC1003
10U_0805_6.3VAM
PC1003
10U_0805_6.3VAM
1
2
PC1029
22U_0805_6.3VAM
PC1029
22U_0805_6.3VAM
1
2
PC1011
10U_0805_6.3VAM
PC1011
10U_0805_6.3VAM
1
2
PC1028
22U_0805_6.3VAM
PC1028
22U_0805_6.3VAM
1
2
+
PC1032
470U_D2_2VM_R4.5M~D
@
+
PC1032
470U_D2_2VM_R4.5M~D
@
1
2
PC1008
10U_0805_6.3VAM
PC1008
10U_0805_6.3VAM
1
2
+
PC1034
470U_D2_2VM_R4.5M~D
@
+
PC1034
470U_D2_2VM_R4.5M~D
@
1
2
PC1007
10U_0805_6.3VAM
PC1007
10U_0805_6.3VAM
1
2
PC1002
10U_0805_6.3VAM
PC1002
10U_0805_6.3VAM
1
2
PC1020
22U_0805_6.3VAM
PC1020
22U_0805_6.3VAM
1
2
PC1004
10U_0805_6.3VAM
PC1004
10U_0805_6.3VAM
1
2
PC1021
22U_0805_6.3VAM
PC1021
22U_0805_6.3VAM
1
2
PC1016
22U_0805_6.3VAM
PC1016
22U_0805_6.3VAM
1
2
+
PC1033
470U_D2_2VM_R4.5M~D
@
+
PC1033
470U_D2_2VM_R4.5M~D
@
1
2
PC1013
22U_0805_6.3VAM
PC1013
22U_0805_6.3VAM
1
2
PC1005
10U_0805_6.3VAM
PC1005
10U_0805_6.3VAM
1
2
PC1018
22U_0805_6.3VAM
PC1018
22U_0805_6.3VAM
1
2
PC1036
22U_0805_6.3VAM
PC1036
22U_0805_6.3VAM
1
2
PC1012
22U_0805_6.3VAM
PC1012
22U_0805_6.3VAM
1
2
PC1019
22U_0805_6.3VAM
PC1019
22U_0805_6.3VAM
1
2
PC1026
22U_0805_6.3VAM
PC1026
22U_0805_6.3VAM
1
2
+
PC1035
470U_D2_2VM_R4.5M~D
+
PC1035
470U_D2_2VM_R4.5M~D
1
2
PC1025
22U_0805_6.3VAM
PC1025
22U_0805_6.3VAM
1
2
PC1014
22U_0805_6.3VAM
PC1014
22U_0805_6.3VAM
1
2
+
PC1031
470U_D2_2VM_R4.5M~D
@
+
PC1031
470U_D2_2VM_R4.5M~D
@
1
2
PC1006
10U_0805_6.3VAM
PC1006
10U_0805_6.3VAM
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PU701
+1.05VS_VCCP
+1.05VS
V
A1
B1
A3
B4
A5
PCH
Q148,+3VALW_PCH
Q149,+5VALW_PCH
B3
51ON#
ON/OFFBTN#
ON/OFF
VS
EC_ON
VIN
BATT
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A# 6
PBTN_OUT#
4
V
VVV
V
VV
V
V
V
V
V
PCH_PWR_EN#
+3VALW_PCH
+5VALW_PCH
3
V
A5 B7
SYSON PU501
+1.35V, +0.675VS
A4 B6
SUSP#,SUSP 8
VV
U46
+5VS
U47
+3VS
PU504
+1.5VS
PU701
+1.05VS
V
V
V
VR_ON
11
VGATE
PM_DRAM_PWRGD_CPU
H_CPUPWRGD
PLT_RST#
B5
SYS_PWROK
B7 2
2
V
V
V
PCH_RSMRST#
5
7
V
PU901
+VCC_CORE
14
10-A
CPU
15
V
2-A
V
9
V
VV
PU401
EC
AC
MODE
BATT
MODE
PU301
A2 B+
B2
PQ101
8-A (DIS)
V
Q145, Q147
+3VS_VGA
+3VS_SLI
DGPU_PWR_EN (GPU)
NVDD_PWR_EN (PCH)
PU502, PU702
+1.5VS_VGA
+1.05VS_VGA
V
PU801
+VGA_CORE
+3VALW
V
2
PCH_DPWROK_R
SUSP#,SUSP
U3
+1.35V_CPU_VDDQ
V
V
DGPU_PWROK (PWR IC)
VDDQ_PWRGOOD
8-B
V
V
10
BATT+
(DIS)
V
V
PU503
+1.8VS
V
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Power Sequence
67 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Power Sequence
67 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
Power Sequence
67 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HW PIR (Product Improve Record)
QIQY5 LA-8691P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/03/09
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HW PIR
68 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HW PIR
68 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
HW PIR
68 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
13
Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change PG# Modify List Date PhaseItem
1
2
3
4
5
6
8
14
7
11
10
17
9
15
16
12
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PWR PIR
69 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PWR PIR
69 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
1.0
PWR PIR
69 69
Wednesday, March 27, 2013
2012/07/01 2014/07/01
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