Compal NM A032 Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal NM-A032 VIQY1 - Schematics. Free.
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A B C D E 1 1 VIQY1 (Y510) 2 2 NM_A032 Rev1.0 Schematic 3 Intel Haswell Processor with DDRIII + Lynx point PCH nVIDIA N14P GT + 2nd VGA N14P GT 3 2013-03-19 Rev1.0 4 4 Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. A B C D Cover Page Size Document Number Custom Date: Y510 NM-A032 Wednesday, March 27, 2013 Sheet E 1 of Rev 1.0 69 A B C D E PCI-Express 16X Gen3 1 2nd VGA, N14P-GT1 N14P-GT1 VRAM 64*32 GDDR5* 8 MUX BANK 0, 1, 2, 3 1.35V DDRIIIL 1066/1333/1600 MT/s 1 UP TO 16G Page 5,6,7,8,9,10 HDMI CRT Conn. Page 39 DDR3-SO-DIMM X2 Page 11,12 Page 23,24,25,26,27,28,29,30,31,33 Page 37 HDMI Conn. Memory BUS (DDRIII) Dual Channel rPGA946 37.5mm*37.5mm VRAM 64*32 GDDR5* 8 Page 32 Sub/B Intel CPU Haswell PEG 0~7 PEG 8~15 MUX Page 36 CRT Page 35 LVDS eDP to LVDS PS8625 MUX Page 34 2 RJ45 Conn. Page 42 DMI *4 5GT/s Page 37 HDMI1.4b LVDS Conn. FDI *2 2.7GT/s eDP eDP USB 2.0 Port1 5V 480MHz Page 38 Atheros QCA8171-BL3A-R Page 41 PCIe port 3 USB Charger IC USB Charger Conn. GL887T Page 50 Intel PCH Lynx point PCIe Gen1 1.5V 5GT/s 2 USB 2.0 5V 480MHz USB Left USB 2.0 Port 2 USB 3.0 Port 2 USB Left USB 2.0 Port 3 USB 3.0 Port 5 Page 49 SPI ROM (4MB+2MB) SATA Port 5 page 44 3.3V 33MHz USB 3.0 5V 5GT/s FCBGA 695Balls 20mm*20mm Card reader IC GL3213 Page 48 Page 48 Touch panel USB 2.0 Port 8 Page 50 SATA Gen3 Port 5 3V 6GHz(600MB/s) USB 2.0 5V 480MHz SATA Gen1 Port2 SATA Port 2 page 44 3V 3GHz(300MB/s) Card reader Conn. Int. Camera USB 2.0 Port 0 Page 35 SATA ODD 3 Page 49 SPI BUS Page 17 SATA HDD Page 50 Sub/B USB 3.0 Port6 5V 5GT/s USB 2.0 Port4 5V 480MHz PCIe Gen1 5V 480MHz SATA Gen3 5V 6GHz(600MB/s) PCIeMini Card WLAN NGFF SSD PCIe Port 4 page 40 SATA Port 4 page 40 PCIeMini Card WLAN 3 USB Port 10 page 40 Page 13,14,15,16,17,18,19,20,21,22 HD Audio 3.3V 24MHz LPC BUS 3.3V 33MHz EC ITE IT8586E-FX Debug Port Page 40 Codec ALC282CG Page 46 Power Circuit DC/DC SPK Conn. Page 45 Page 45 Page 56,57,58,59,60,61, 62,63,64,65,66 4 DC/DC Interface CKT. RTC CKT. POWER/B Conn. AUDIO, USB/B Conn. Page 55 Touch Pad Page 56 Int.KBD Page 47 Page 52 Page 47 Issued Date ODD/B Conn. page 44 A NOVO/B Conn. Page 35 Page 43 2012/07/01 2014/07/01 Deciphered Date Ext. MIC Conn. Sub/B Title LC Future Center Secret Data Security Classification Page 50 Int. MIC Conn. (JCMOS Conn.) Thermal Sensor EMC 1403 Page 50 4 HP Conn. Sub/B Page 50 Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 Page 52 B C D Sheet E 2 of Rev 1.0 69 A B Voltage Rails ( O --> Means ON C D E , X --> Means OFF ) +5VS Power Plane +VCCSA +V1.5S_VCCP +CPU_CORE +3VALW +VGA_CORE +1.5V B+ +GFX_CORE +5VALW SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +1.5VS 1 SIGNAL STATE +3VS +1.8VS Clock 1 +1.05VS State +0.75VS +3.3VS_VGA +1.5VS_VGA USB 2.0 USB 3.0 S0 O O O BOM Structure Table USB Port Table +1.05VS_VGA Port O 0 XHCI S3 O O O X O S5 S4 Battery only O O X X 3 5 6 X X 2 2 EHCI1 2 S5 S4/AC Only 1 4 5 6 7 8 9 10 11 12 13 X EHCI2 S5 S4 AC & Battery don't exist X X X X BOM Structure GT@ GT1@ CMOS@ SURGE@ X76@ GC6@ NOGC6@ AOAC@ KBL@ ME@ @ DS3@ daul@ 887T@ 887@ TI@ EDP@ SLI@ 47W@ 37W@ 4 External USB Port Camera USB Port (Right Side) USB Port (Left Side) USB Port (Left Side) Card Reader Touch panel Mini Card(WLAN) SMBUS Control Table SOURCE Main VGA 2nd VGA BATT IT8580E SODIMM WLAN WiMAX Thermal Sensor PCH PCIE PORT LIST TP Module Port BTO Item NV GT750M NV GT755M CMOS Camera part QCA8171 LAN surge part X76 Level part for VRAM NV CG6 support part 2 NV no CG6 support part AOAC support part K/B Light part ME part Unpop Deep S3 support part Support daul channel panel function GENESYS 887T USB charger solution GENESYS 887 USB charger solution TI USB charger solution Support EDP panel function For SLI function part For 47W CPU part For 37W CPU part Device 3 3 EC_SMB_CK1 IT8580E EC_SMB_DA1 +3VALW EC_SMB_CK2 IT8580E EC_SMB_DA2 +3VS +3VS +3VS SMB_CLK_S3 SMB_DATA_S3 PCH +3VS X X V X V X X X V X X X X X X X +3VALW V +3VS V +3VS X V +3VS X X X V X +3V_PCH V +3V_PCH 1 2 3 4 5 6 7 8 V LAN WLAN +3VS Address EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1 4 4 Device Device Smart Battery 0001 011X b Thermal Sensor EMC1403-2 Master VGA Slave VGA Address Device Address 1001_101xb DDR DIMM0 1001 000Xb 0x9E 0x9C DDR DIMM2 1001 010Xb Security Classification Issued Date DAZ0SF00100 Title LC Future Center Secret Data 2012/07/01 2014/07/01 Deciphered Date Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 A B C D Sheet E 3 of Rev 1.0 69 5 4 Hot plug detect for IFP link E VGA and GDDR5 Voltage Rails D ACTIVE 3 2 Performance Mode P0 TDP at Tj = 102 C* (GDDR5) (N14Px GPIO) Function Description GPU (4) Mem (1,5) NVCLK /MCLK Products (W) (W) (MHz) (V) (A) (W) (A) N14X 128bit 1GB GDDR5 TBD TBD TBD TBD TBD TBD TBD FBVDDQ (GPU+Mem) (1.35V) PCI Express I/O and (1.05V) PLLVDD (6) (1.8V) I/O and PLLVDD (1.05V) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD FBVDD (1.35V) NVVDD GPIO I/O GPIO0 IN - FB_CLAMP_MON GPIO1 OUT - NA GPIO2 OUT - VGA_BL_PWM GPIO3 OUT - VGA_ENVDD Physical Strapping pin ROM_SCLK +3VS_VGA GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA OUT - NA ROM_SO +3VS_VGA GPIO5 STRAP0 +3VS_VGA GPIO6 OUT - FB_CLAMP_TOGGLE_REQ# STRAP1 +3VS_VGA STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] GPIO7 OUT - NA STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED GPIO8 OUT - OVERT# STRAP4 +3VS_VGA PCIE_SPEED_ CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V GPIO9 OUT - VGA_ALERT# GPIO10 OUT - Memory VREF Control GPIO11 OUT - NVVDD PWM_VID GPIO12 IN - AC Power Detect Input GPIO13 OUT - DPRSLPVR_VGA GPIO14 OUT - NA GPIO15 IN - NA GPIO16 OUT - NA GPIO17 IN - VGA_EDP_HPD GPIO18 IN - DGPU_HDMI_HPD GPIO19 IN - NA Logical Strapping Bit1 Logical Strapping Bit0 PCI_DEVID[4] Logical Strapping Bit2 SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE USER[3] USER[2] USER[1] Logical Strapping Bit3 Power Rail RESERVED 0x0FCD setting SMB_ALT_ADDR (ROM_SO Bit 1) (10K pull High) N14P-GT 28nm +VGA_CORE tNVVDD >0 tPEX_VDD >0 1 0x9C C STRAP3 PU 10K PD 15K PU 45K PD 5K PD 25K PU 5K PD 45K Master PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave N14P-GT N14P-GT1 ROM_SI ROM_SI STRAP4 B K4G20325FD-FC03 H5GQ2H24AFR-R0C Samsung 2500MHz K4G20325FD-FC04 Hynix 2500MHz H5GQ2H24AFR-T2C PD 30K 64Mx32 +1.05VS_VGA 0x9E STRAP2 Hynix 3000MHz tFBVDDQ >0 I2C Slave addrees ID 0 STRAP1 64Mx32 +1.5VS_VGA PCI_DEVID[0] STRAP0 GPU Samsung 3000MHz 3GIO_PAD_CFG_ADR[0] ROM_SCLK ROM_SO FB Memory (GDDR5) +3VS_VGA (3.3V) USER[0] 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] Device ID N13P-GT (28nm) GPU Other D C B 1 64Mx32 PD 25K PD 30K 1. all power rail ramp up time should be larger than 40us 64Mx32 PD 25K Other Power rail +3VS_VGA A A Tpower-off <10ms Issued Date 1.all GPU power rails should be turned off within 10ms 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ 5 Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 4 3 2 VGA Notes List Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 4 of Rev 1.0 69 5 4 3 2 1 +VCCIOA_OUT D 2 PEG_COMP 24.9_0402_1% D 1 RC2 CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils. Haswell rPGA EDS JCPUA DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 D21 C21 B21 A21 <15> <15> <15> <15> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 D20 C20 B20 A20 <15> <15> <15> <15> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D18 C17 B17 A17 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D17 C18 B18 A18 <15> <15> <15> <15> FDI_CSYNC FDI_INT 2 RC3 2 RC87 1 1 0_0402_5% 0_0402_5% FDI_CSYNC_R FDI_INT_R DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 H29 J29 FDI_CSYNC FDI_INT FDI <15> <15> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 PEG DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI C <15> <15> <15> <15> B INTEL_HASWELL_HASWELL PEG_RCOMP PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8 PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15 PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15 PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8 PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15 PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15 E23 PEG_COMP M29PCIE_CRX_GTX_N0 K28PCIE_CRX_GTX_N1 M31PCIE_CRX_GTX_N2 L30 PCIE_CRX_GTX_N3 M33PCIE_CRX_GTX_N4 L32 PCIE_CRX_GTX_N5 M35PCIE_CRX_GTX_N6 L34 PCIE_CRX_GTX_N7 E29PCIE_CRX_GTX_N8 D28PCIE_CRX_GTX_N9 E31PCIE_CRX_GTX_N10 D30PCIE_CRX_GTX_N11 E35PCIE_CRX_GTX_N12 D34PCIE_CRX_GTX_N13 E33PCIE_CRX_GTX_N14 E32PCIE_CRX_GTX_N15 L29 PCIE_CRX_GTX_P0 L28 PCIE_CRX_GTX_P1 L31 PCIE_CRX_GTX_P2 K30PCIE_CRX_GTX_P3 L33 PCIE_CRX_GTX_P4 K32PCIE_CRX_GTX_P5 L35 PCIE_CRX_GTX_P6 K34PCIE_CRX_GTX_P7 F29PCIE_CRX_GTX_P8 E28PCIE_CRX_GTX_P9 F31PCIE_CRX_GTX_P10 E30PCIE_CRX_GTX_P11 F35PCIE_CRX_GTX_P12 E34PCIE_CRX_GTX_P13 F33PCIE_CRX_GTX_P14 D32PCIE_CRX_GTX_P15 H35PCIE_CTX_GRX_N0 H34PCIE_CTX_GRX_N1 J33 PCIE_CTX_GRX_N2 H32PCIE_CTX_GRX_N3 J31 PCIE_CTX_GRX_N4 G30PCIE_CTX_GRX_N5 C33PCIE_CTX_GRX_N6 B32PCIE_CTX_GRX_N7 B31PCIE_CTX_GRX_N8 A30PCIE_CTX_GRX_N9 B29PCIE_CTX_GRX_N10 A28PCIE_CTX_GRX_N11 B27PCIE_CTX_GRX_N12 A26PCIE_CTX_GRX_N13 B25PCIE_CTX_GRX_N14 A24PCIE_CTX_GRX_N15 J35 PCIE_CTX_GRX_P0 G34PCIE_CTX_GRX_P1 H33PCIE_CTX_GRX_P2 G32PCIE_CTX_GRX_P3 H31PCIE_CTX_GRX_P4 H30PCIE_CTX_GRX_P5 B33PCIE_CTX_GRX_P6 A32PCIE_CTX_GRX_P7 C31PCIE_CTX_GRX_P8 B30PCIE_CTX_GRX_P9 C29PCIE_CTX_GRX_P10 B28PCIE_CTX_GRX_P11 C27PCIE_CTX_GRX_P12 B26PCIE_CTX_GRX_P13 C25PCIE_CTX_GRX_P14 B24PCIE_CTX_GRX_P15 PCIE_CRX_GTX_N[0..15] <23,32> PEG Static Lane Reversal - CFG2 is for the 16x 1: Normal Operation; Lane # socket pin map definition CFG2 * definition matches 0:Lane Reversed C PCIE_CRX_GTX_P[0..15] CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15 CC16 CC20 CC23 CC25 CC30 CC18 CC22 CC28 CC32 CC19 CC24 CC29 CC17 CC21 CC27 CC26 CC31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 <23,32> 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N[0..15] <23,32> PCIE_CTX_C_GRX_P[0..15] <23,32> B 1 OF 9 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU (1/7) DMI, FDI, PEG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 20, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 5 of Rev 0.1 69 5 4 3 2 +1.35V 1 2 0_0402_5% 2 2 RC1543 1 2 0_0402_5% DDR3_DRAMRST# XDP_OBS0 XDP_OBS1 <11,12> XDP_OBS2 XDP_OBS3 2 G QC3 BSS138_NL_SOT23-3 RC5 need to close to JCPU1 H_CPUPWRGD 1 <15> <9> <17> 1 RC42 DRAMRST_CNTRL_PCH <7> <46> 2 DRAMRST_CNTRL 0_0402_5% @ 1 DRAMRST_CNTRL 1 DRAMRST_CNTRL_EC RC15452 @ 2 R_short 0_0402_5% SIO_PWRBTN#_R CPU_PWR_DEBUG 2 1K_0402_1% H_CPUPWRGD_XDP 2 0_0402_5% CFD_PWRBTN#_XDP @ CPU_PWR_DEBUG VGATE <15,64> VGATE CLK_CPU_ITP <16> CLK_CPU_ITP CLK_CPU_ITP# <16> CLK_CPU_ITP# RC5 RC6 +1.05VS CC50 0.047U_0402_16V4Z 1 1 BUF_CPU_RST# 1 1K_0402_1% 2 XDP_RST#_R XDP_DBRESET# RC8 XDP_TDO_R XDP_TRST#_R XDP_TDI_R XDP_TMS_R Reserve for Deep S3 XDP_TCK_R +1.05VS Place near JXDP1 1 @ 2 1 @ 2 CC66 0.1U_0402_25V6K DDR3_DRAMRST#_R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 XDP_PREQ#_R XDP_PRDY#_R CC65 0.1U_0402_25V6K D @ JXDP @ RC62 @ 1K_0402_5% 1 S 3 RC1544 4.99K_0402_1% @ D XDP Connector 1 RC60 H_DRAMRST# 1 D 27 28 MOLEX 52435-2671 20120806 VA change XDP connector to 28 pin PU/PD for JTAG signals DDR3 COMPENSATION SIGNALS +3VS C RC1539 SM_RCOMP0 1 SM_RCOMP1 RC55 1 2 75_0402_1% SM_RCOMP2 RC49 1 2 100_0402_1% C 2 100_0402_1% Haswell rPGA EDS 1 1K_0402_1% JCPUB @ RC32 2 1 51_0402_1% XDP_TDO @ RC35 2 1 51_0402_1% RC40 2 1 51_0402_1% <46,57> H_PROCHOT# <15> <19> XDP_TCLK XDP_TRST# RC41 2 H_PM_SYNC H_CPUPWRGD 1 RC25 AT28 H_PM_SYNC AL34 VCCPWRGOOD_0_R PM_DRAM_PWRGD_CPU AC10 AT26 BUF_CPU_RST# 2 R_short 0_0402_5% PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN PRDY PREQ TCK TMS TRST TDI TDO DBR BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7 1 51_0402_1% CLK_CPU_DPLL# CLK_CPU_DPLL CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL 2 1 RC51 2 1 RC52 2 1 RC43 2 1 RC22 <16> CLK_CPU_DMI# <16> CLK_CPU_DMI 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CLK_CPU_DMI# CLK_CPU_DMI G28 H28 F27 E27 D26 E26 DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP CLOCK <16> <16> <16> <16> INTEL_HASWELL_HASWELL AP3 AR3 AP2 AN3 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 H_DRAMRST# AR29 AT29 AM34 AN33 AM33 AM31 AL33 AP33 XDP_PRDY# RC47 1 XDP_PREQ# RC48 1 XDP_TCLK RC50 1 XDP_TMS RC53 1 XDP_TRST# RC54 1 XDP_TDI RC23 1 XDP_TDO RC24 1 XDP_DBRESET#_R RC26 2 AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R RC30 RC31 RC33 RC34 RC36 RC37 RC38 RC39 2 2 2 2 2 0_0402_5% XDP_PRDY#_R 0_0402_5% XDP_PREQ#_R XDP_TCK_R 0_0402_5% XDP_TMS_R 0_0402_5% 0_0402_5% XDP_TRST#_R 2 0_0402_5% XDP_TDI_R 2 0_0402_5% XDP_TDO_R 1 0_0402_5% XDP_DBRESET# 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% SM_DRAMPWROK with DDR Power Gating Topology VCCPWRGOOD_0_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 CAD Note: Avoid stub in the PWRGD path while placing resistors RC25 & RC130 2 OF 9 BUF_CPU_RST# CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil 1 1 51_0402_1% XDP_PREQ# SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST RC130 10K_0402_5% 1 51_0402_1% @ RC29 2 CATERR PECI RSVD PROCHOT THERMTRIP PWR @ RC27 2 XDP_TDI MISC SKTOCC AN32 AR27 AK31 AM30 AM35 THERMAL XDP_TMS H_CATERR# H_PECI <46> H_PECI PAD T55 @ 1 2 56_0402_5% H_PROCHOT#_R RC57 H_THRMTRIP# <19> H_THRMTRIP# 2 AP32 +1.05VS DDR3 RC19 2 JTAG XDP_DBRESET#_R VCCPWRGOOD_0_R B B 497750_497750_SHRKBY_MBL_SCH_CHKLST 0.5 page19 item 3.6 SM_DRAMPWROK For ESD 1 1 @ @ CC61 220P_0402_25V8J 2 2 CC60 220P_0402_25V8J +3V_PCH For ESD concern, please put near CPU 1 2 5 B O 2 UC4 74AHC1G09GW_TSSOP5 1 0_0402_5% 1 3 <10> A D S 2 G RUN_ON_CPU1.5VS3# @ QC1 SSM3K7002FU_SC70-3 1 @ 1 +1.05VS RC1261 @ RC1281 @ RC44 1 +VCCIO_OUT PM_DRAM_PWRGD_CPU 0_0402_5% RC14 3.3K_0402_1% 2 RC1547 Buffered Reset to CPU 2 RC28 @ RC64 39_0402_5% 3 A 4 RUNPWROK_AND 1 2 P 1 0_0402_5% 2 1 2 2 1 G RC88 RC16 1.8K_0402_1% 2 SYS_PWROK PM_DRAM_PWRGD +VCCIO_OUT CC156 1 2 @ 0.1U_0402_25V6K RC84 <15> <15> 200_0402_5% RC89 100K_0402_5% @ 1 +1.35V_CPU_VDDQ +3V_PCH 1 CPU_SSC_DPLL 10K_0402_5% CPU_SSC_DPLL# 1 10K_0402_5% 2 H_THRMTRIP# 100_0402_1% 2 H_CATERR# 49.9_0402_1% 2 H_PROCHOT# 62_0402_5% 2 RC20 @ 2 RC21 @ SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21 1.05V <19> 1 0_0402_5% RC46 CPU_PLTRST# 2 BUF_CPU_RST# A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU (2/7) PM, XDP, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 6 of Rev 1.0 69 5 4 3 2 1 Haswell rPGA EDS <12> JCPUD DDRB_DQ[0..63] DDRB_DQ0 AR18 DDRB_DQ1 AT18 DDRB_DQ2 AM17 DDRB_DQ3 AM18 DDRB_DQ4 AR17 DDRB_DQ5 AT17 DDRB_DQ6 AN17 DDRB_DQ7 AN18 DDRB_DQ8 AT12 DDRB_DQ9 AR12 DDRB_DQ10 AN12 DDRB_DQ11 AM11 DDRB_DQ12 AT11 DDRB_DQ13 AR11 DDRB_DQ14 AM12 DDRB_DQ15 AN11 DDRB_DQ16 AR5 DDRB_DQ17 AR6 DDRB_DQ18 AM5 DDRB_DQ19 AM6 DDRB_DQ20 AT5 DDRB_DQ21 AT6 DDRB_DQ22 AN5 DDRB_DQ23 AN6 DDRB_DQ24 AJ4 DDRB_DQ25 AK4 DDRB_DQ26 AJ1 DDRB_DQ27 AJ2 DDRB_DQ28 AM1 DDRB_DQ29 AN1 DDRB_DQ30 AK2 DDRB_DQ31 AK1 L2 DDRB_DQ32 M2 DDRB_DQ33 L4 DDRB_DQ34 M4 DDRB_DQ35 L1 DDRB_DQ36 M1 DDRB_DQ37 L5 DDRB_DQ38 M5 DDRB_DQ39 G7 DDRB_DQ40 J8 DDRB_DQ41 G8 DDRB_DQ42 G9 DDRB_DQ43 J7 DDRB_DQ44 J9 DDRB_DQ45 DDRB_DQ46 G10 DDRB_DQ47 J10 A8 DDRB_DQ48 B8 DDRB_DQ49 A9 DDRB_DQ50 B9 DDRB_DQ51 D8 DDRB_DQ52 E8 DDRB_DQ53 D9 DDRB_DQ54 E9 DDRB_DQ55 DDRB_DQ56 E15 DDRB_DQ57 D15 DDRB_DQ58 A15 DDRB_DQ59 B15 DDRB_DQ60 E14 DDRB_DQ61 D14 DDRB_DQ62 A14 DDRB_DQ63 B14 Haswell rPGA EDS <11> JCPUC DDRA_DQ[0..63] DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 +VREF_CA_R +V_DDR_REFA_R +V_DDR_REFB_R D C +VREF_CA_R AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15 AM9 AN9 AM8 AN8 AR9 AT9 AR8 AT8 AJ9 AK9 AJ6 AK6 AJ10 AK10 AJ7 AK7 AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2 J1 J2 J5 H5 H2 H1 J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6 E12 D12 B11 A11 E11 D11 B12 A12 AM3 F16 F13 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD_AC7 SA_CK_N_0 SA_CK_P_0 SA_CKE_0 SA_CK_N_1 SA_CK_P_1 SA_CKE_1 SA_CK_N_2 SA_CK_P_2 SA_CKE_2 SA_CK_N_3 SA_CK_P_3 SA_CKE_3 SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3 SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3 SA_BS_0 SA_BS_1 SA_BS_2 RSVD_V10 SA_RAS SA_WE SA_CAS SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15 SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7 AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8 @T64 @ T64 PAD DDRA_CLK0# DDRA_CLK0 DDRA_CKE0 DDRA_CLK1# DDRA_CLK1 DDRA_CKE1 M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1 <11> <11> <11> <11> <11> <11> DDRA_CS0# DDRA_CS1# <11> <11> DDRA_ODT0 DDRA_ODT1 <11> <11> DDRA_BS0# DDRA_BS1# DDRA_BS2# V10 U6 U7 U8 DDRA_RAS# DDRA_WE# DDRA_CAS# DDRA_MA[0..15] V8 DDRA_MA0 AC6DDRA_MA1 V9 DDRA_MA2 U9 DDRA_MA3 AC5DDRA_MA4 AC4DDRA_MA5 AD6DDRA_MA6 AC3DDRA_MA7 AD5DDRA_MA8 AC2DDRA_MA9 V6 DDRA_MA10 AC1DDRA_MA11 AD4DDRA_MA12 V7 DDRA_MA13 AD3DDRA_MA14 AD2DDRA_MA15 <11> <11> <11> <11> <11> <11> <11> DDRA_DQS#[0..7] AP15 DDRA_DQS#0 AP8DDRA_DQS#1 AJ8DDRA_DQS#2 AF3DDRA_DQS#3 J3 DDRA_DQS#4 E2 DDRA_DQS#5 C5 DDRA_DQS#6 C11DDRA_DQS#7 AP14 DDRA_DQS0 AP9DDRA_DQS1 AK8DDRA_DQS2 AG3DDRA_DQS3 H3 DDRA_DQS4 E3 DDRA_DQS5 C6 DDRA_DQS6 C12DDRA_DQS7 <11> DDRA_DQS[0..7] <11> SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 4 OF 9 RSVD SB_CKN0 SB_CK0 SB_CKE_0 SB_CKN1 SB_CK1 SB_CKE_1 SB_CKN2 SB_CK2 SB_CKE_2 SB_CKN3 SB_CK3 SB_CKE_3 SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3 SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3 SB_BS_0 SB_BS_1 SB_BS_2 RSVD SB_RAS SB_WE SB_CAS SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15 SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7 AG8 Y4 AA4 AF10 Y3 AA3 AG10 Y2 AA2 AG9 Y1 AA1 AF9 @ T63 P4 R2 P3 P1 R4 R3 R1 P2 R7 P8 AA9 PAD DDRB_CLK0# DDRB_CLK0 DDRB_CKE0 DDRB_CLK1# DDRB_CLK1 DDRB_CKE1 <12> <12> <12> <12> <12> <12> DDRB_CS0# DDRB_CS1# <12> <12> DDRB_ODT0 DDRB_ODT1 <12> <12> DDRB_BS0# DDRB_BS1# DDRB_BS2# R10 R6 P6 P7 <12> <12> <12> DDRB_RAS# DDRB_WE# DDRB_CAS# DDRB_MA[0..15] R8 DDRB_MA0 Y5 DDRB_MA1 Y10DDRB_MA2 AA5DDRB_MA3 Y7 DDRB_MA4 AA6DDRB_MA5 Y6 DDRB_MA6 AA7DDRB_MA7 Y8 DDRB_MA8 AA10 DDRB_MA9 R9 DDRB_MA10 Y9 DDRB_MA11 AF7DDRB_MA12 P9 DDRB_MA13 AA8DDRB_MA14 AG7DDRB_MA15 D <12> <12> <12> <12> C AP18 DDRB_DQS#0 AP11 DDRB_DQS#1 AP5DDRB_DQS#2 AJ3DDRB_DQS#3 L3 DDRB_DQS#4 H9 DDRB_DQS#5 C8 DDRB_DQS#6 C14DDRB_DQS#7 AP17 DDRB_DQS0 AP12 DDRB_DQS1 AP6DDRB_DQS2 AK3DDRB_DQS3 M3 DDRB_DQS4 H8 DDRB_DQS5 C9 DDRB_DQS6 C15DDRB_DQS7 DDRB_DQS#[0..7] DDRB_DQS[0..7] <12> <12> INTEL_HASWELL_HASWELL B B <6> INTEL_HASWELL_HASWELL DRAMRST_CNTRL DRAMRST_CNTRL 3 S BSS138_SOT23 1 D QC11 2 G 3 OF 9 @ 2 0_0402_5% 2 0_0402_5% 1 RC144 @ 1K_0402_1% @ RC143 1K_0402_1% 2 BSS138_SOT23 2 QC9 DRAMRST_CNTRL @ 3 S D 1 +V_DDR_REFA_R +V_DDR_REFB_R 1 RC1548 1 RC92 1 2 G +VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R A A 6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ) Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU (3/7) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 7 of Rev 1.0 69 5 4 3 2 1 CFG STRAPS for CPU 2 @ RC76 1K_0402_1% 1 CFG2 D D PEG Static Lane Reversal - CFG2 is for the 16x * 1:(Default) Normal Operation; Lane # definition matches socket pin map definition CFG2 0:Lane Reversed 20120829 VA1 Add net for add HDMI MUX T34 U34 U35 V35 U32 T32 U33 V33 COMPENSATION PU FOR eDP +VCCIOA_OUT 2 1 2 1 RC45 C RC58 1 2 RC1 RC59 P29 R29 N28 P28 P31 R31 N30 P30 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils. eDP EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1 DDIC_TXCN_0 DDIC_TXCP_0 DDIC_TXCN_1 DDIC_TXCP_1 DDIC_TXCN_2 DDIC_TXCP_2 DDIC_TXCN_3 DDIC_TXCP_3 DDID_TXDN_0 DDID_TXDP_0 DDID_TXDN_1 DDID_TXDP_1 DDID_TXDN_2 DDID_TXDP_2 DDID_TXDN_3 DDID_TXDP_3 M27 N27 P27 E24 R27 CPU_EDP_AUX# CPU_EDP_AUX EDP_HPD_IN# EDP_COMP P35 R35 N34 P34 P33 R33 N32 P32 CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+ FDI_CTX_PRX_N0 FDI_CTX_PRX_P0 FDI_CTX_PRX_N1 FDI_CTX_PRX_P1 CPU_EDP_AUX# CPU_EDP_AUX PAD <38> <38> T69 @ CFG4 1 EDP_AUXN EDP_AUXP EDP_HPD EDP_RCOMP RSVD CPU_EDP_TX0<38> CPU_EDP_TX0+ <38> CPU_EDP_TX1<38> CPU_EDP_TX1+ <38> FDI_CTX_PRX_N0 <15> FDI_CTX_PRX_P0 <15> FDI_CTX_PRX_N1 <15> FDI_CTX_PRX_P1 <15> CFG4 * INTEL_HASWELL_HASWELL 8 OF 9 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port CFG6 A34 A35 @ T76 PAD @ T80 PAD W29 W28 H_CPU_RSVD G26 W33 AL30 AL29 F25 @ T79 PAD @ T94 PAD +VCC_CORE @ T82 PAD @ T81 PAD C35 B35 @ T85 PAD AL25 @ T84 PAD @ T83 PAD W30 W31 W34 H_CPU_TESTLO A CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG0 AT20 AR20 AP20 AP22 AT22 AN22 AT25 AN23 AR24 AT23 AN20 AP24 AP26 AN25 AN26 AP25 RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD VCC CFG_RCOMP CFG_16 CFG_18 CFG_17 CFG_19 RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD_TP RSVD RSVD TESTLO RSVD CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 RSVD RSVD NC RSVD RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD INTEL_HASWELL_HASWELL C23 B23 D24 D23 AT31 AR21 AR23 AP21 AP23 PAD PAD PAD PAD CFG_RCOMP CFG16 CFG18 CFG17 CFG19 T86 @ T78 @ T87 @ T88 @ PAD T156 @ PAD T164 @ PAD T165 @ PAD T166 @ * CFG[6:5] AR33 G6 AM27 AM26 F5 AM2 K6 PAD PAD PAD PAD PAD PAD PAD T91 @ T90 @ T92 @ T89 @ T93 @ T95 @ T104 @ E18 PAD T96 @ U10 P10 PAD PAD T98 @ T97 @ B1 A2 AR1 PAD PAD T100 @ T99 @ E21 E20 PAD PAD T102 @ T101 @ PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B CFG7 AP27 AR26 * AL31 AL32 CFG7 @ RC86 1K_0402_1% @ T173PAD @ T116PAD @ T117PAD @ T126PAD @ T129PAD @ T130PAD @ T131PAD @ T132PAD @ T133PAD @ T134PAD @ T135PAD @ T136PAD @ T137PAD @ T138PAD @ T142PAD @ T143PAD RSVD_TP RSVD_TP RSVD_TP RSVD_TP 2 @ T73 PAD @ T77 PAD RSVD_TP RSVD_TP RSVD 1 1 2 RC75 100K_0402_5% B AT1 AT2 AD10 2 1 3 S 2 G CPU_EDP_HPD QC6 BSS138_SOT23 <38> @ T70 PAD @ T71 PAD @ T72 PAD RC85 1K_0402_1% JCPUI EDP_HPD_IN# D 1 Haswell rPGA EDS @RC83 @ RC83 1K_0402_1% 1 CFG5 RC65 10K_0402_5% 2 +VCCIO_OUT HPD INVERSION FOR EDP C Display Port Presence Strap DDI 1 2 JCPUH 2 EDP_COMP 24.9_0402_1% H_CPU_TESTLO 49.9_0402_1% CFG_RCOMP 49.9_0402_1% 1 H_CPU_RSVD 49.9_0402_1% DDIB_TXBN_0 DDIB_TXBP_0 DDIB_TXBN_1 DDIB_TXBP_1 DDIB_TXBN_2 DDIB_TXBP_2 DDIB_TXBN_3 DDIB_TXBP_3 RC77 1K_0402_1% check CLK item T28 U28 T30 U30 U29 V29 U31 V31 CPU_HDMI_TX2CPU_HDMI_TX2+ CPU_HDMI_TX1CPU_HDMI_TX1+ CPU_HDMI_TX0CPU_HDMI_TX0+ CPU_HDMI_CLKCPU_HDMI_CLK+ 2 Haswell rPGA EDS <37> <37> <37> <37> <37> <37> <37> <37> PEG DEFER TRAINING 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A 9 OF 9 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU (4/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 8 of Rev 1.0 69 5 4 3 2 1 +VCC_CORE Haswell rPGA EDS JCPUE @ T107 @ T106 @ T112 @ T113 D K27 L27 T27 V27 PAD PAD PAD PAD +1.35V_CPU_VDDQ +1.35V CC151 2 1 0.1U_0402_25V6K CC152 2 1 0.1U_0402_25V6K AB11 AB2 AB5 AB8 AE11 AE2 AE5 AE8 AH11 K11 N11 N8 T11 T2 T5 T8 W11 W2 W5 W8 placement @ T115 N26 K26 AL27 AK27 PAD +VCC_CORE @ T151 @ T152 +VCC_CORE C 1 2 RC66 100_0402_1% VCC_SENSE 2 +1.05VS <64> RC67 2 VCCSENSE VCCSENSE need connect to power 0_0603_5% 1 +VCCIO_OUT @ 1 VSSSENSE_R R_short 0_0402_5% VSSSENSE_R <10> <64> <64> <64> PAD PAD @ T154 PAD RC61 43_0402_5% 1 2 VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT 1 RC70 100_0402_1% 2 AL35 E17 AN35 A23 F22 W32 AL16 J27 AL13 PAD +VCCIO_OUT +1.05VS +VCCIOA_OUT @ T160 @ T159 AM28 AM29 AL28 AP35 H27 AP34 AT35 AR35 AR32 AL26 AT34 AL22 AT33 AM21 AM25 AM22 AM20 AM24 AL19 AM23 AT32 CPU_PWR_DEBUG RC63 130_0402_1% @ 2 VSSSENSE 1 <64> 1 VCCSENSE_R R_short 0_0402_5% CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU RC68 2 VSSSENSE PAD PAD VCCSENSE_R @ T153 RC4 CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD RSVD @ T157 @ T158 @ T162 @ T163 PAD PAD PAD PAD +VCCIO_OUT B VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RSVD VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIO2PCH VCCIOA_OUT RSVD RSVD VSS RSVD VIDALERT VIDSCLK VIDSOUT VSS PWR_DEBUG RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD +1.05VS Power 1 VDDQ DECOUPLING 2 1 2 1 2 1 2 @ 1 2 1 2 RC71 10K_0402_5% 2 CPU_PWR_DEBUG Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 <6> need connect to power VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC INTEL_HASWELL_HASWELL D C B U25 U26 V25 V26 W26 W27 5 OF 9 CC43 22U_0805_6.3V6M 1 CC42 22U_0805_6.3V6M 2 CC41 22U_0805_6.3V6M 1 CC40 22U_0805_6.3V6M 2 CC39 22U_0805_6.3V6M 1 CC38 22U_0805_6.3V6M 2 @ CC37 22U_0805_6.3V6M 1 CC36 22U_0805_6.3V6M 2 CC35 22U_0805_6.3V6M 1 CC34 22U_0805_6.3V6M 2 CC33 22U_0805_6.3V6M 1 A +VCC_CORE CPU_PWR_DEBUG 1 @ + @ 2 1 2 @ + CC172 330U_D2_2VM_R6M 2 1 CC167 330U_D2_2VM_R6M 2 1 CC166 10U_0603_6.3V6M 2 1 CC165 10U_0603_6.3V6M 2 1 CC164 10U_0603_6.3V6M 2 1 CC163 10U_0603_6.3V6M 2 1 CC162 10U_0603_6.3V6M 2 1 CC161 10U_0603_6.3V6M 2 1 CC168 10U_0603_6.3V6M 2 1 CC169 10U_0603_6.3V6M 1 CC170 10U_0603_6.3V6M 2 CC171 10U_0603_6.3V6M 1 2 @ RC69 150_0402_1% +1.35V_CPU_VDDQ AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU (5/7) PWR, BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 9 of Rev 1.0 69 5 4 C B JCPUF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22 +1.35V_CPU_VDDQ @ J15 2 +1.35V 2 1 1 +1.35V_CPU_VDDQ JUMP_43X79 +1.35V INTEL_HASWELL_HASWELL 6 OF 9 For Deep S3 1 2 0.1U_0402_10V6K CC286 1 2 0.1U_0402_10V6K CC96 1 2 0.1U_0402_10V6K CC95 1 2 0.1U_0402_10V6K @ RC56 100K_0402_5% 4 2 1 RC1349 2 @ S @ S AO4304L Vgs=10V,Id=18A, Rds<6.7m ohm P/N: SB00000RV00 @ CC97 0.01U 50V K X7R 0603 S D 1 1 D 2 G INTEL_HASWELL_HASWELL @ @ QC4 2N7002KW_SOT323-3 @ QC156 2N7002KW_SOT323-3 2 CPU1.5V_S3_GATE 3 0_0402_5% <46> 3 A SUSP 1 <40,55,61> C RC237 1 0_0402_5% 2 RC238 1 VSSSENSE_R PAD 0_0402_5% 2 B <9> T65 @ 7 OF 9 AO4304L_SO8 D@ 2 G D 1 2 3 470K_0402_5% RUN_ON_CPU1.5VS3# K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33 1 R56 need to check on SDV 8 7 6 5 RUN_ON_CPU1.5VS3 RC1538 1 @ 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD RSVD RSVD RSVD VSS_SENSE RSVD UC3 1 1 2 RC1537 @ 100K_0402_5% JCPUG VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS +1.35V_CPU_VDDQ CC287 +VSB +3VALW B34 B4 B7 C1 C10 C13 C16 C19 C2 C22 C24 C26 C28 C30 C32 C34 C4 C7 D10 D13 D16 D19 D22 D25 D27 D29 D31 D33 D35 D4 D7 E1 E10 E13 E16 E4 E7 F10 F11 F12 F14 F15 F17 F18 F20 F21 F23 F24 F26 F28 F30 F32 F34 F4 F6 F7 F8 F9 G1 G11 G2 G27 G29 G3 G31 G33 G35 G4 G5 H10 H26 H6 H7 J11 J26 J28 J30 J32 J34 J6 K1 1 RUN_ON_CPU1.5VS3# <6> RC1546 470K_0402_5% 1 2 RC1487 470_0603_5% 2 D 2 Haswell rPGA EDS 1 A10 A13 A16 A19 A22 A25 A27 A29 A3 A31 A33 A4 A7 AA11 AA25 AA27 AA31 AA29 AB1 AB10 AA33 AA35 AB3 AC25 AC27 AB4 AB6 AB7 AB9 AC11 AD11 AC29 AC31 AC33 AC35 AD7 AE1 AE10 AE25 AE29 AE3 AE27 AE35 AE4 AE6 AE7 AE9 AF11 AF6 AF8 AG11 AG25 AE31 AG31 AE33 AG6 AH1 AH10 AH2 AG27 AG29 AH3 AG33 AG35 AH4 AH5 AH6 AH7 AH8 AH9 AJ11 AJ5 AK11 AK25 AK26 AK28 AK29 AK30 AK32 E19 3 3 Haswell rPGA EDS QC5 @ 2 SUSP G 2N7002KW_SOT323-3 Title LC Future Center Secret Data Security Classification Issued Date A 2012/07/01 2014/07/01 Deciphered Date CPU (6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 10 of Rev 1.0 69 5 4 3 2 1 DDR3 SO-DIMM A +VREF_DQ_DIMMA_R +1.35V +1.35V 1 +1.35V 2 0.1U_0402_10V6K 1 CD140 DDRA_DQ4 DDRA_DQ0 DDRA_DQ1 DDRA_DQ5 DDRA_DQ13 DDRA_DQ12 2 24.9_0402_1% DDRA_DQS#1 DDRA_DQS1 DDRA_DQ9 DDRA_DQ8 20120727 VA SWAP DQ for layout DDRA_DQ20 DDRA_DQ21 DDRA_DQS#2 DDRA_DQS2 DDRA_DQ23 DDRA_DQ19 DDRA_DQ25 DDRA_DQ28 DDRA_DQ7 DDRA_DQ6 DDRA_DQS#0 DDRA_DQS0 1 CD51 @ 2 DDRA_DQ2 DDRA_DQ3 DDRA_DQ15 DDRA_DQ14 DDR3_DRAMRST# 1 CD52 @ 2 1 CD53 @ 2 DDR3_DRAMRST# <12,6> DDRA_DQ11 DDRA_DQ10 DDRA_DQ16 DDRA_DQ17 DDRA_DQ22 DDRA_DQ18 20120727 VA SWAP DQ for layout DDRA_DQ31 DDRA_DQ29 +1.35V DDRA_DQS#3 DDRA_DQS3 <7> <7> DDRA_WE# DDRA_CAS# <7> DDRA_CS1# DDRA_MA10 DDRA_BS0# DDRA_WE# DDRA_CAS# DDRA_MA13 DDRA_CS1# B DDRA_DQ37 DDRA_DQ36 DDRA_DQ40 DDRA_DQ41 20120727 VA SWAP DQ for layout DDRA_DQ42 DDRA_DQ44 DDRA_DQ52 DDRA_DQ53 DDRA_DQS#6 DDRA_DQS6 1 RD82 2 10K_0402_5% 1 +3VS 1 2 2 CD162 0.1U_0402_10V6K RD83 10K_0402_5% 2 CD290 2.2U_0603_6.3V6K 1 205 G1 G2 206 2 2 2 C + CD148 220U_6.3V_M 2 1 DDRA_BS1# DDRA_RAS# DDRA_CS0# DDRA_ODT0 DDRA_ODT1 DDRA_CLK1 DDRA_CLK1# <7> <7> DDRA_BS1# DDRA_RAS# <7> <7> DDRA_CS0# DDRA_ODT0 <7> <7> DDRA_ODT1 <7> DDRA_DQ39 DDRA_DQ35 1 CD149 2 1 CD150 2 2 +VREF_CA RD89 1 0_0402_5% 1 CD179 0.1U_0402_10V6K 2 RD81 1K_0402_1% +VREF_CA DDRA_DQ38 DDRA_DQ34 Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket RD80 1K_0402_1% +VREF_CA <12> RD88 B 24.9_0402_1% DDRA_DQ45 DDRA_DQ47 Layout Note: Place near DIMM Layout Note: Place near DIMM DDRA_DQS#5 DDRA_DQS5 DDRA_DQ43 DDRA_DQ46 DDRA_DQ49 DDRA_DQ51 +0.675VS 20120727 VA SWAP DQ for layout DDRA_DQ54 DDRA_DQ55 1 CD288 DDRA_DQ56 DDRA_DQ57 2 DDRA_DQS#7 DDRA_DQS7 DDR_A_DM[0:7] connect to GND 1 CD158 2 1 CD159 2 1 CD160 2 A DDRA_DQ62 DDRA_DQ63 SMB_DATA_S3 SMB_CLK_S3 0.65A@0.75V SMB_DATA_S3 SMB_CLK_S3 +0.675VS <12,17,40,47> <12,17,40,47> Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date DDRIII SO-DIMM A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 ME@ 5 DDRA_CLK1 DDRA_CLK1# Issued Date LCN_DAN06-K4806-0102 2 1 1U_0402_6.3V6K DDRA_DQ58 DDRA_DQ59 2 CD1561 +VREF_CA_R 1U_0402_6.3V6K A DDRA_MA2 DDRA_MA0 1U_0402_6.3V6K DDRA_DQ61 DDRA_DQ60 2 +1.35V DDRA_MA6 DDRA_MA4 1U_0402_6.3V6K DDRA_DQ48 DDRA_DQ50 2 2.2U_0603_6.3V6K DDRA_DQS#4 DDRA_DQS4 2 CD1471 DDRA_MA11 DDRA_MA7 0.1U_0402_10V6K DDRA_DQ32 DDRA_DQ33 2 CD1551 2 DDRA_BS0# 2 2 <7> DDRA_CLK0 DDRA_CLK0# DDRA_MA15 DDRA_MA14 2 1 DDRA_CLK0 DDRA_CLK0# <7> CD1541 0.1U_0402_10V6K <7> <7> DDRA_CKE1 CD1461 0.1U_0402_10V6K DDRA_MA3 DDRA_MA1 DDRA_CKE1 CD1531 0.1U_0402_10V6K DDRA_MA8 DDRA_MA5 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 CD1451 0.1U_0402_10V6K DDRA_MA12 DDRA_MA9 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 CD1441 10U_0603_6.3V6M DDRA_BS2# CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 CD1521 10U_0603_6.3V6M DDRA_BS2# 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CD1431 10U_0603_6.3V6M <7> DDRA_CKE0 CD1421 10U_0603_6.3V6M CD1511 10U_0603_6.3V6M DDRA_DQ24 DDRA_DQ30 10U_0603_6.3V6M DDRA_CKE0 OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) (10uF_0603_6.3V)*8 (0.1uF_402_10V)*4 Layout Note: Place near DIMM 2 <7> <7> D 10U_0603_6.3V6M VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 10U_0603_6.3V6M DDRA_DQ27 DDRA_DQ26 C VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 <7> DDRA_MA[0..15] 1 2 1 2 2.2U_0603_6.3V6K RD90 2 1K_0402_1% CD180 0.1U_0402_10V6K 1 2 1 CD141 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 0.047U_0402_16V4Z RD79 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 0.047U_0402_16V4Z D For RF request JDDRL1 +VREF_DQ_DIMMA <7> DDRA_DQS#[0..7] 3A@1.5V 0.047U_0402_16V4Z RD91 1 2 0_0402_5% <7> DDRA_DQS[0..7] 2 RD78 1K_0402_1% DDRA_DQ[0..63] 4 3 2 1 Sheet 11 of Rev 1.0 69 5 4 1 +1.35V +1.35V 1 0.1U_0402_10V6K 2 2.2U_0603_6.3V6K 2 1 2 1K_0402_1% 1 1 1 CD157 2 DDRB_DQ2 DDRB_DQ3 DDRB_DQ13 DDRB_DQ12 2 24.9_0402_1% DDRB_DQS#1 DDRB_DQS1 DDRB_DQ15 DDRB_DQ11 DDRB_DQ20 DDRB_DQ16 DDRB_DQS#2 DDRB_DQS2 DDRB_DQ22 DDRB_DQ23 DDRB_DQ28 DDRB_DQ29 DDRB_DQ26 DDRB_DQ27 C <7> DDRB_WE# DDRB_CAS# DDRB_MA13 DDRB_CS1# DDRB_CS1# DDRB_DQ32 DDRB_DQ36 DDRB_DQ44 DDRB_DQ45 DDRB_DQ40 DDRB_DQ42 DDRB_DQ53 DDRB_DQ55 DDRB_DQS#6 DDRB_DQS6 +3VS CD177 2.2U_0603_6.3V6K 1 1 2 2 205 CD178 0.1U_0402_10V6K G1 G2 FOX_AS0A621-U4SG-7H C 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 DDRB_CKE1 DDRB_CKE1 CD1611 <7> DDRB_MA15 DDRB_MA14 2 DDRB_MA11 DDRB_MA7 DDRB_MA6 DDRB_MA4 CD2821 2 CD1631 2 CD1641 2 CD1651 2 CD1661 2 CD1671 2 CD1681 2 CD1691 2 CD1701 2 CD1711 2 CD1721 2 20120727 VA SWAP DQ for layout DDRB_MA2 DDRB_MA0 DDRB_CLK1 DDRB_CLK1# DDRB_BS1# DDRB_RAS# DDRB_CS0# DDRB_ODT0 DDRB_ODT1 DDRB_CLK1 DDRB_CLK1# <7> <7> DDRB_BS1# DDRB_RAS# <7> <7> DDRB_CS0# DDRB_ODT0 <7> <7> DDRB_ODT1 <7> +VREF_CA DDRB_DQ35 DDRB_DQ37 DDRB_DQ38 DDRB_DQ34 1 CD280 2 1 CD281 2 +VREF_CA <11> B DDRB_DQ41 DDRB_DQ47 Layout Note: Place near DIMM DDRB_DQS#5 DDRB_DQS5 Layout Note: Place near DIMM DDRB_DQ43 DDRB_DQ46 +0.675VS DDRB_DQ54 DDRB_DQ52 DDR_B_DM[0:7] connect to GND 20120727 VA SWAP DQ for layout DDRB_DQ51 DDRB_DQ50 1 CD173 DDRB_DQ61 DDRB_DQ57 2 DDRB_DQS#7 DDRB_DQS7 1 CD174 2 1 CD175 2 1 CD176 2 1U_0402_6.3V6K 1 RD95 2 10K_0402_5% 1 2 RD9710K_0402_5% +1.35V 1U_0402_6.3V6K DDRB_DQ63 DDRB_DQ62 A DDRB_DQ25 DDRB_DQ24 1U_0402_6.3V6K DDRB_DQ56 DDRB_DQ60 20120727 VA SWAP DQ for layout 1U_0402_6.3V6K DDRB_DQ49 DDRB_DQ48 DDRB_DQS#3 DDRB_DQS3 (10uF_0603_6.3V)*8 (0.1uF_402_10V)*4 Layout Note: Place near DIMM DDRB_DQ30 DDRB_DQ31 2.2U_0603_6.3V6K DDRB_DQS#4 DDRB_DQS4 DDRB_DQ18 DDRB_DQ19 0.1U_0402_10V6K DDRB_DQ39 DDRB_DQ33 B DDRB_DQ17 DDRB_DQ21 0.1U_0402_10V6K DDRB_WE# DDRB_CAS# <11,6> 0.1U_0402_10V6K DDRB_BS0# <7> <7> DDR3_DRAMRST# DDRB_DQ14 DDRB_DQ10 0.1U_0402_10V6K <7> DDRB_MA10 DDRB_BS0# 2 D 0.1U_0402_10V6K DDRB_CLK0 DDRB_CLK0# DDR3_DRAMRST# 2 <7> <7> 10U_0603_6.3V6M <7> <7> DDRB_CLK0 DDRB_CLK0# <7> 10U_0603_6.3V6M DDRB_MA3 DDRB_MA1 DDRB_DQ8 DDRB_DQ9 1 CD56 @ 10U_0603_6.3V6M DDRB_MA8 DDRB_MA5 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 2 DDRB_DQ6 DDRB_DQ7 1 CD55 @ 10U_0603_6.3V6M DDRB_MA12 DDRB_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 1 CD54 @ DDRB_DQS#0 DDRB_DQS0 10U_0603_6.3V6M DDRB_BS2# <7> DDRB_DQS[0..7] DDRB_MA[0..15] 10U_0603_6.3V6M DDRB_BS2# DDRB_DQ0 DDRB_DQ1 10U_0603_6.3V6M DDRB_CKE0 <7> 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 DDRB_DQ[0..63] DDRB_DQS#[0..7] 10U_0603_6.3V6M <7> DDRB_CKE0 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 0.047U_0402_16V4Z CD289 DDRB_DQ5 DDRB_DQ4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 0.047U_0402_16V4Z RD85 RD92 For RF request JDDRL2 +VREF_DQ_DIMMB 1 CD181 0.1U_0402_10V6K 3A@1.5V 0.047U_0402_16V4Z RD93 1 2 0_0402_5% +1.35V RD84 1K_0402_1% 2 2 DDR3 SO-DIMM B +VREF_DQ_DIMMB_R D 3 DDRB_DQ59 DDRB_DQ58 A SMB_DATA_S3 SMB_CLK_S3 SMB_DATA_S3 SMB_CLK_S3 +0.675VS <11,17,40,47> <11,17,40,47> 0.65A@0.75V Issued Date Title LC Future Center Secret Data Security Classification ME@ 2012/07/01 2014/07/01 Deciphered Date DDRIII SO-DIMM B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 12 of Rev 1.0 69 4 3 Place JUMPER under RAM door @ 2 2 20K_0402_5% JME1 SHORT PADS PCH_RTCX1 B5 PCH_RTCX2 B4 PCH_SRTCRST# B9 D SM_INTRUDER#A8 G10 PCH_INTVRMEN 2 20K_0402_5% PCH_RTCRST# D9 1 1 CH229 1U_0603_10V4Z @ 2 <45> RH121 <45> +3VS 1 2 10K_0402_5% 1 2 0_0402_5% PCH_GPIO33 HDA_BIT_CLK B25 HDA_SPKR HDA_SDIN0 HDA_SYNC A22 HDA_SPKR AL10 HDA_RST# C24 HDA_SDIN0 L22 K22 G22 CRT_SWITCH_1 RH110 CRT_SWITCH_1 F22 <46> ME_FLASH RH109 1 ME_FLASH @ 2 1K_0402_1% PCH_GPIO33 B17 RH3172 @ 1 10K_0402_5% PCH_GPIO13 C22 SRTCRST# SATA_TXN_0 SATA_TXP_0 SATA_RXN_1 SATA_RXP_1 INTRUDER# INTVRMEN SATA_TXN_1 SATA_TXP_1 RTCRST# SATA_RXN_2 SATA_RXP_2 HDA_BCLK SATA_TXN_2 SATA_TXP_2 HDA_SYNC SPKR SATA_RXN_3 SATA_RXP_3 HDA_RST# HDA_SDI0 SATA_TXN_3 SATA_TXP_3 HDA_SDI1 SATA_RXN4/PERN1 SATA_RXP4/PERP1 HDA_SDI2 HDA_SDI3 SATA_TXN4/PETN1 SATA_TXP4/PETP1 HDA_SDO SATA_RXN5/PERN2 SATA_RXP5/PERP2 DOCKEN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_TXP5/PETP2 SATA_RCOMP SATALED# AB3 PCH_JTAG_TMS AD1 RH45 1 @ 2 210_0402_1% PCH_JTAG_TDI AE2 RH46 1 @ 2 210_0402_1% PCH_JTAG_TDO AD3 2 @ RH47 100_0402_1% @ RH49 100_0402_1% RH48 100_0402_1% @ 1 PCH_JTAG_TCK 2 210_0402_1% 1 RH59 2 @ 1 @ RH1508 2 F8 PCH_TP25 0_0402_5% C26 @ T108 PAD AB6 @ T109 PAD JTAG_TCK SATA0GP/GPIO21 JTAG_TMS SATA1GP/GPIO19 JTAG 1 51_0402_1% +3.3V_ALW_PCH_JTAG RH44 1 @ 1 2 @ HDA_SDOUT A24 RH1071 2 C +3V_PCH 2 R_short 0_0402_5% RTCX2 RH288 0_0603_5% 1 +3V_PCH 2 <37> SATA_RXN_0 SATA_RXP_0 AZALIA @ JCMOS2 SHORT PADS 2 RH1461 REV = 5 RTCX1 RTC RH1481 1 1 CH202 1U_0603_10V4Z 2 +RTCVCC 1 LPT_PCH_M_EDS UHA CMOS 2 SATA 5 JTAG_TDI SATA_IREF JTAG_TDO TP9 TP25 TP8 BC8 BE8 AW8 AY8 D BC10 BE10 AV10 AW10 BB9 SATA_PRX_DTX_N2 BD9 SATA_PRX_DTX_P2 ODD AY13 SATA_PTX_DRX_N2 AW13 SATA_PTX_DRX_P2 CH1862 CH1872 1 0.01U_0402_16V7K 1 0.01U_0402_16V7K SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_C_DRX_N2 SATA_PTX_C_DRX_P2 <44> <44> SATA_PTX_C_DRX_N2 SATA_PTX_C_DRX_P2 <44> <44> BC12 BE12 AR13 AT13 BD13 SATA_PRX_DTX_N0 BB13 SATA_PRX_DTX_P0 SSD @ CH1842 CH1852 @ AV15 SATA_PTX_DRX_N0 AW15 SATA_PTX_DRX_P0 1 0.01U_0402_16V7K 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 SATA_PTX_C_DRX_P0 BC14 SATA_PRX_DTX_N1 BE14 SATA_PRX_DTX_P1 AY5 CH2732 CH2722 1 0.01U_0402_16V7K 1 0.01U_0402_16V7K SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 <40> <40> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1 <40> <40> <44> <44> SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1 <44> <44> C SATA_COMP AP3 HDD_LED# RH1202 AT1 PCH_GPIO21 RH1192 1 10K_0402_5% 2 1 RH41 +3VS HDD_LED# RH3162 SATA_IREF 0_0402_5% 1 10K_0402_5% +3VS AU2 SATA_DET# BD4 <40> <40> SATA_PTX_C_DRX_N0 SATA_PTX_C_DRX_P0 HDD AP15 SATA_PTX_DRX_N1 AR15 SATA_PTX_DRX_P1 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 1 10K_0402_5% +1.5VS <51> +3VS SATA_DET# <40> BA2 PAD T161 @ PAD T155 @ BB2 TP22 W=20mils W=20mils TP20 +RTCBATT +RTCVCC 2 LYNXPOINT_BGA695 1 OF 11 RH99 1 1 1K_0402_5% CH179 1U_0603_10V4Z 2 PCH_RTCX1 1 RH145 2 PCH_RTCX2 +RTCVCC 10M_0402_5% B Y3 1 SATA Impedance Compensation B RH1491 2 1M_0402_5% SM_INTRUDER# RH1501 2 330K_0402_5% PCH_INTVRMEN +3VS 2 RH1051 32.768KHZ_12.5PF_CM31532768DZFT 1 1 CH189 18P_0402_50V8J INTVRMEN CH188 18P_0402_50V8J 2 +1.5VS * 2 H L ：：Integrated VRM enable (Default) Integrated VRM disable * @ 2 1K_0402_5% HDA_SPKR SATA_COMP 7.5K_0402_1% HIGH= Enable ( No Reboot ) LOW= Disable (Default) 1 2 RH40 CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. (INTVRMEN should always be pull high.)If RH1509 = stuff RH1353 = @ QH10 = @ RH108 = @ HDA AUDIO +5VS +3V_PCH 2 HDA_BIT_CLK <45> HDA_SYNC_AUDIO RH1141 33_0402_5% 2 HDA_SYNC_R <45> HDA_RST_AUDIO# RH1161 33_0402_5% 2 HDA_RST# <45> HDA_SDOUT_AUDIO RH1181 33_0402_5% 2 HDA_SDOUT 3 RH1082 QH10 BSS138_NL_SOT23-3 1 2 2 RH1509 0_0402_5% RH1353 1M_0402_5% HDA_SYNC RH1062 1 S 1 @ 1 1K_0402_5% @ 1 1K_0402_5% HDA_SDOUT This signal has a weak internal pull-down HDA_SYNC D RH1121 33_0402_5% G A HDA_BITCLK_AUDIO 2 +3V_PCH <45> * On Die PLL VR Select is supplied by 1.5V when smapled high (Default) 1.8V when sampled low Needs to be pulled High for Chief River platfrom * Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide] A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (1/9) SATA,HDA,SPI, LPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 13 of Rev 1.0 69 5 4 3 2 1 +3VS D RH8501 2 2.2K_0402_5% PCH_CRT_DDC_CLK RH8511 2 2.2K_0402_5% PCH_CRT_DDC_DAT 150_0402_1% 2 RH339 1 PCH_CRT_B 150_0402_1% 2 RH340 1 PCH_CRT_G 150_0402_1% 2 RH341 1 PCH_CRT_R D 20120829 VA1 Add net for add CRT MUX +3VS LPT_PCH_M_EV UHE PCH_CRT_B <37> PCH_CRT_G <37> PCH_CRT_R PCH_CRT_B T45 PCH_CRT_G U44 PCH_CRT_R V45 PCH_CRT_DDC_CLK PCH_CRT_DDC_CLK M43 <37> PCH_CRT_DDC_DAT PCH_CRT_DDC_DAT M45 PCH_CRT_HSYNC N42 PCH_CRT_VSYNC N44 <37> PCH_CRT_HSYNC <37> PCH_CRT_VSYNC 2 RH302 1 649_0402_1% U40 CRT_IREF U39 DDPB_CTRLCLK VGA_GREEN DDPB_CTRLDATA VGA_RED DDPC_CTRLCLK VGA_DDC_CLK VGA_DDC_DATA DDPC_CTRLDATA CRT <37> VGA_BLUE DDPD_CTRLCLK VGA_HSYNC DDPD_CTRLDATA VGA_VSYNC DDPB_AUXN DAC_IREF DDPC_AUXN DISPLAY <37> VGA_IRTN C <23,54> DGPU_HOLD_RST# <54,63> NVDD_PWR_EN <23,54,55> <27,54> DGPU_PWR_EN <35> PCH_ENBKL <35> PCH_ENVDD PCH_EDP_PWM N36 PCH_ENBKL K36 PCH_ENVDD G36 PCI_PIRQA# H20 PCI_PIRQB# L20 PCI_PIRQC# K17 PCI_PIRQD# M20 1 2 A12 PCH_DGPU_HOLD_RST# RH1519 0_0402_5% 1 2 NVDD_PWR_EN_R B13 NVDD_PWR_EN RH1526 0_0402_5% 2 DGPU_PWR_EN_R C12 DGPU_PWR_EN 1 RH1525 0_0402_5% C10 PCH_GPIO51 DGPU_GC6_EN <40> PCH_EDP_PWM PCH_WL_OFF# A10 DGPU_GC6_EN PCH_WL_OFF# AL6 EDP_BKLTCTL EDP_BKLTEN DDPD_AUXN DDPB_AUXP LVDS <35> DDPC_AUXP EDP_VDDEN DDPD_AUXP DDPB_HPD PIRQA# DDPC_HPD PIRQB# DDPD_HPD PPT EDS DOC#474146 RH314 1 @ 2 8.2K_0402_5% PCH_GPIO51 RH318 1 @ 2 8.2K_0402_5% DGPU_GC6_EN RH313 1 2 8.2K_0402_5% PIRQH# RH312 1 2 8.2K_0402_5% PCH_WL_OFF# RH320 1 2 8.2K_0402_5% CRT_DET#_R N40 RH311 1 2 8.2K_0402_5% DGPU_HOLD_RST# N38 RH323 1 2 8.2K_0402_5% PCI_PIRQC# RH324 1 2 8.2K_0402_5% PCH_GPIO2 RH325 2 1 10K_0402_5% DGPU_PWR_EN RH310 1 2 8.2K_0402_5% DGPU_GC6_EN RH315 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST# RH308 2 @ 1 1K_0402_5% PCH_WL_OFF# REV = 5 R40 DDPB_CLK R39 DDPB_DATA DDPB_CLK <37> DDPB_DATA <37> R35 20120829 VA1 Add net for add HDMI MUX R36 H45 K43 J42 C H43 @ K45 J44 K40 TMDS_B_HPD TMDS_B_HPD <37> K38 H39 PIRQC# PIRQD# PCI PIRQE#/GPIO2 GPIO50 PIRQF#/GPIO3 GPIO52 PIRQG#/GPIO4 GPIO54 PIRQH#/GPIO5 GPIO51 PME# GPIO53 PLTRST# G17 PCH_GPIO2 F17 ODD_DA#_R L15 1 CRT_DET#_R RH1522 PIRQH# M15 AD10 Y11 @ T114 ODD_DA#_R <44> 2 CRT_DET# 0_0402_5% CRT_DET# A16 swap overide Strap/Top-Block Swap Override jumper <36> PAD PLT_RST# PLT_RST# <23,32,40,41,46> LYNXPOINT_BGA695 Low = A16 swap override/Top-Block Swap Override enabled PCI_GNT3# GPIO55 5 OF 11 ***High=Default B B 1 PLT_RST# 2 RH301 100K_0402_5% PCH_GPIO51 RH307 1 2 1K_0402_5% @ +3VS RPH5 8 7 6 5 1 2 3 4 PCI_PIRQD# PCI_PIRQA# ODD_DA#_R PCI_PIRQB# Boot BIOS Strap BBS_BIT1 (GPIO51) SWAP 8.2K_0804_8P4R_5% SATA_SLPD (BBS_BIT0) 0 0 0 1 1 0 Boot BIOS Location LPC Reserved (NAND) ODD_DA#_R For ESD PCI 1 @ A 2 A CC63 220P_0402_25V8J * Issued Date 2012/07/01 2014/07/01 Deciphered Date 1 SPI Title LC Future Center Secret Data Security Classification 1 PCH (2/9) PCIE, SMBUS, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 14 of Rev 1.0 69 5 4 3 2 1 +3VS +RTCVCC +3V_PCH 1 1 CH1071 0.1U_0402_16V4Z RH189 330K_0402_5% D 2 1 10K_0402_5% RH222 2 1 200K_0402_5% PCH_AC_PRESENT_R 5 SUSWARN# B DSWODVREN Y A 4 SYS_PWROK <6> @ * RH182 100K_0402_1% 2 UH7 MC74VHC1G08DFT2G SC70 5P 1 1 @ RH291 330K_0402_5% 1 PCH_PWROK ： ： DSWODVREN - On Die DSW VR Enable H Enable L Disable 2 2 PCH_PWROK 1 VGATE P VGATE 3 <6,64> G +3VALW D 2 2 RH202 2 RH203 10K_0402_5% LPT_PCH_M_EDS DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 <5> <5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <5> <5> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 <5> <5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <5> <5> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 C <5> <5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <5> <5> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 <5> <5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 2 +1.5VS DMI_CTX_PRX_N2AP17 DMI_CTX_PRX_N3AV20 DMI_CTX_PRX_P0AY22 DMI_CTX_PRX_P1AP20 DMI_CTX_PRX_P2AR17 DMI_CTX_PRX_P3AW20 DMI_CRX_PTX_N0BD21 DMI_CRX_PTX_N1BE20 DMI_CRX_PTX_N2BD17 DMI_CRX_PTX_N3BE18 DMI_CRX_PTX_P0BB21 DMI_CRX_PTX_P1BC20 DMI_CRX_PTX_P2BB17 DMI_CRX_PTX_P3BC18 1 RH43 DMI_IREF 0_0402_5% BE16 AW17 @ T139 PAD AV17 @ T111 PAD 2 DMI_RCOMP 7.5K_0402_1% 1 RH204 +1.5VS AY17 REV = 5 DMI_RXN_0 DMI_RXN_1 FDI_RXN_0 DMI_RXN_2 DMI_RXN_3 FDI_RXN_1 DMI_RXP_0 DMI_RXP_1 FDI_RXP_0 FDI FDI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI TP16 DMI_TXN_0 DMI_TXN_1 TP5 TP15 DMI_TXN_2 DMI_TXN_3 TP10 DMI_TXP_0 DMI_TXP_1 FDI_CSYNC FDI_INT DMI_TXP_2 DMI_TXP_3 FDI_IREF DMI_IREF TP17 TP12 TP13 TP7 FDI_RCOMP AJ35 FDI_CTX_PRX_N0 AL35 FDI_CTX_PRX_N1 AJ36 FDI_CTX_PRX_P0 AL36 FDI_CTX_PRX_P1 AV43 PAD T144 @ AY45 PAD T141 @ AV45 PAD T147 @ PAD T148 @ FDI_CTX_PRX_N0 <8> FDI_CTX_PRX_N1 <8> FDI_CTX_PRX_P0 <8> FDI_CTX_PRX_P1 <8> C PCH_DPWROK_R 1 <5> <5> For Intel checklist V0.6 AW44 AL39 FDI_CSYNC AL40 FDI_INT AT45 FDI_IREF 0_0402_5% RH184 100K_0402_1% 2 UHB DMI_CTX_PRX_N0AW22 DMI_CTX_PRX_N1AR20 For Intel checklist V0.5 FDI_CSYNC FDI_INT AU42 PAD 1 RH42 T145 @ AU44 PAD T146 @ AR44 2 FDI_RCOMP 7.5K_0402_1% 2 1 RH206 <5> <5> +1.5VS +3VS PM_CLKRUN# 8.2K_0402_5% 2 RH185 1 +1.5VS DMI_RCOMP For Deep S3 <46> RH1488 2 SUSACK# RH188 +3VS 2 1 R_short 0_0402_5% SUSACK#_R 1 SYS_RESET# AM1 SYS_PWROK AD7 10K_0402_5% R6 B <46> RH196 PCH_PWROK 1 2 R_short 0_0402_5% 2 AB7 APWROK RH1510 1 R_short 0_0402_5% PM_DRAM_PWRGD H3 APWROK can be connect to PWROK if iAMT disable <6> <46> For Deep S3 <6> <46> SIO_PWRBTN#_R <46> <46> PM_DRAM_PWRGD EC_RSMRST# SUSWARN# RH1511 1 2 R_short 0_0402_5% PCH_RSMRST#_R J2 RH1489 1 2 SUSWARN#_R J4 RH1512 1 PBTN_OUT# F10 PWROK R_short 0_0402_5% 2 K1 R_short 0_0402_5% RH234 1 2R_short 0_0402_5%PCH_AC_PRESENT_R +3VALW RH246 1 2 8.2K_0402_5% PCH_GPIO72 K7 +3V_PCH RH290 2 1 10K_0402_5% RI# N4 AC_PRESENT @ T140 <38> PAD EDP_SEL E6 AB10 D2 SUSACK# DSWVRMEN System Power Management SYS_RESET# SYS_PWROK DPWROK WAKE# PWROK CLKRUN# APWROK SUS_STAT#/GPIO61 DRAMPWROK SUSCLK/GPIO62 RSMRST# SLP_S5#/GPIO63 SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PWRBTN# SLP_S3# ACPRESENT/GPIO31 SLP_A# BATLOW#/GPIO72 SLP_SUS# RI# PMSYNCH TP21 SLP_LAN# C8 DSWODVREN L13 PCH_DPWROK_R RH292 1 2 R_short 0_0402_5% DPWROK_EC K3 WAKE# RH294 1 2 R_short 0_0402_5% PCIE_WAKE# <46> PCIE_WAKE# <19,40,41> SUS_STAT# Y6 SUSCLK PAD T66 PAD T67 PAD T68 Y7 PM_SLP_S5# C6 PM_SLP_S4# H1 PM_SLP_S3# F3 Can be left NC when IAMT is not support on the platfrom F1 PM_SLP_SUS#_R PCH_GPIO29 <46> PM_SLP_S3# <46> RH1456 2 AY3 H_PM_SYNC G5 PM_SLP_S4# 1 R_short 0_0402_5% H_PM_SYNC PAD PM_SLP_SUS# <46,55> For Deep S3 <6> T110 Can be left NC if no use integrated LAN. 10/06 Test point request SLP_WLAN#/GPIO29 LYNXPOINT_BGA695 B note need connect to GPIO27 AN7 PM_CLKRUN# U7 For Deep S3 DPWROK_EC Add one to +3VALW next Rev. 4 OF 11 +3V_PCH WAKE# RH319 A 2 1 10K_0402_5% RH1871 2 10K_0402_5% PCH_RSMRST#_R A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (3/9) PCIE, SMBUS, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 15 of Rev 1.0 69 5 4 3 LPT_PCH_M_EDS UHC D Y43 Y45 PCH_GPIO73 AB1 AA44 AA42 PCH_GPIO18 AF1 AB43 AB45 CLKREQ_TV#_R AF3 LAN <41> <41> <41> <40> <40> <40> WLAN CLK_PCIE_LAN#AD43 CLK_PCIE_LAN AD45 T3 CLKREQ_LAN# CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN# CLK_PCIE_WLAN#AF43 CLK_PCIE_WLAN AF45 WLAN_CLKREQ1# V3 CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ1# PCH_GPIO44 AE44 AE42 AA2 AB40 AB39 PCH_GPIO45 AE4 C AJ44 AJ42 PCH_GPIO46 <6> CLK_CPU_ITP# <6> CLK_CPU_ITP RH280 RH281 2 1 0_0402_5% 2 Y3 CLK_BCLK_ITP#AH43 1 0_0402_5% CLK_BCLK_ITP AH45 D44 <46> <40> CLK_PCI_EC CLK_PCI_DB RH253 1 2 22_0402_5% CLK_PCI_EC_R E44 RH174 2 1 22_0402_5% CLK_PCI_DB_R B42 @ F41 CLK_PCI_LOOPBACK RH1514 2 1 22_0402_5% PCI_LOOPBACKOUT A40 CLKOUT_PCIE_N_0 CLKOUT_PEG_A_P PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 CLKOUT_PCIE_N_1 CLKOUT_PCIE_P_1 CLKOUT_PEG_B CLKOUT_PEG_B_P PCIECLKRQ1#/GPIO18 PEGB_CLKRQ#/GPIO56 CLKOUT_PCIE_N_2 CLKOUT_DMI CLKOUT_PCIE_P_2 CLKOUT_DMI_P PCIECLKRQ2#/GPIO20/SMI# CLKOUT_DP CLKOUT_DP_P CLKOUT_PCIE_N_3 CLKOUT_PCIE_P_3 PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLKOUT_DPNS_P CLKOUT_PCIE_N_4 CLKOUT_PCIE_P_4 PCIECLKRQ4#/GPIO26 CLKIN_DMI CLKIN_DMI_P CLKOUT_PCIE_N5 CLKOUT_PCIE_P_5 PCIECLKRQ5#/GPIO44 CLKIN_GND CLKIN_GND_P CLKIN_DOT96N CLKIN_DOT96P CLKOUT_PCIE_N_6 CLKOUT_PCIE_P_6 PCIECLKRQ6#/GPIO45 CLKIN_SATA CLKIN_SATA_P CLKOUT_PCIE_N_7 REFCLK14IN CLKIN_33MHZLOOPBACK CLKOUT_PCIE_P_7 PCIECLKRQ7#/GPIO46 XTAL25_IN XTAL25_OUT CLKOUT_ITPXDP CLKOUTFLEX0/GPIO64 CLKOUT_ITPXDP_P CLKOUTFLEX1/GPIO65 CLKOUT_33MHZ0 CLKOUTFLEX2/GPIO66 CLKOUT_33MHZ1 CLKOUTFLEX3/GPIO67 CLKOUT_33MHZ2 ICLK_IREF CLKOUT_33MHZ3 TP19 TP18 CLKOUT_33MHZ4 DIFFCLK_BIASREF CLOCK SIGNAL LYNXPOINT_BGA695 1 REV = 5 CLKOUT_PEG_A CLKOUT_PCIE_P_0 2 AB35 CLK_PCIE_VGA# AB36 CLK_PCIE_VGA AF6 Y39 U4 <23> CLK_PCIE_VGA <23> RH1513 1 CLK_REQ_GPU#_R CLK_PCIE_2VGA# Y38 CLK_PCIE_VGA# 2 10K_0402_5% CLK_PCIE_2VGA# CLK_PCIE_2VGA RH170 AF39 CLK_CPU_DMI# 1 2 10K_0402_5% CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL AF35 AF36 CLK_CPU_DPLL# CLK_CPU_DPLL AY24 AW24 CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI AR24 AT24 CLKIN_DMI2# CLKIN_DMI2 H33 G33 CLK_BUF_DREF_96M# CLK_BUF_DREF_96M RH1621 RH1631 2 2 10K_0402_5% 10K_0402_5% BE6 BC6 CLK_BUF_PCIE_SATA# RH1641 CLK_BUF_PCIE_SATA RH1661 2 2 10K_0402_5% 10K_0402_5% 2 10K_0402_5% CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL CLK_CPU_DPLL# CLK_CPU_DPLL RPH1 4 3 2 1 RH1671 5 6 7 8 10K_0804_8P4R_5% C EDP_AUX_SEL <38> S_DGPU_PWROK <32,54> F36 S_DGPU_RST_R F39 PCH_GPIO67 AN44 <6> <6> XTAL25_IN XTAL25_OUT F38 RH1505 1 AD39 AD38 <6> <6> CLKIN_DMI2# CLKIN_DMI2 CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI C40 AM45 <32> +3V_PCH <6> AJ40 AJ39 AL44 AM43 CLK2_REQ_GPU#_R <6> CLK_CPU_DMI F45 CLK_BUF_ICH_14M D17 CLK_PCI_LOOPBACK <23> 2nd VGA <32> CLK_CPU_DMI# AF40 CLK_CPU_DMI CLK_REQ_GPU#_R +3V_PCH <32> CLK_PCIE_2VGA CLK2_REQ_GPU#_R D 2 R_short 0_0402_5% ICLK_IREF 0_0402_5% RH1832 RH1504 1 PCH_GPIO67 1 2 RH54 PAD T149 @ PAD T150 @ 1 PCH_CLK_BIASREF 7.5K_0402_1% 2 RH208 1 +3VS 10K_0402_5% 2 R_short 0_0402_5% <19> S_DGPU_RST <32,54> BIOS Request SKU ID +1.5VS +1.05V_+1.5V_RUN GPIO64, 65 that only for GC6 1. GPIO64 : S_DGPU_GC6_EN 2. GPIO65 : S_DGPU_PWROK 2 OF 11 +3V_PCH B B RH1522 1 10K_0402_5% PCH_GPIO73 RH1682 1 10K_0402_5% CLKREQ_LAN# RH1652 1 10K_0402_5% WLAN_CLKREQ1# RH1472 1 10K_0402_5% PCH_GPIO44 RH1722 1 10K_0402_5% PCH_GPIO45 RH1772 1 10K_0402_5% PCH_GPIO46 Change C196, C197 value of Cap from 33pF to 10pF for TXC recommend XTAL25_IN 1 XTAL25_OUT Y2 Reserve for EMI please close to PCH +3VS 1 CH196 RH1582 1 10K_0402_5% PCH_GPIO18 RH3292 1 10K_0402_5% CLKREQ_TV#_R RH169 2 1M_0402_5% 12P_0402_50V8F CLK_PCI_LOOPBACK @RH176 @ RH176 33_0402_5% 2 1 1 2 3 GND 1 3 GND 2 4 25MHZ_10PF_7V25000014 1 2 CH197 12P_0402_50V8F @CH199 @ CH199 22P_0402_50V8J 1 2 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (3/9) DMI, FDI, PM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 16 of Rev 1.0 69 5 4 3 2 1 D D LPT_PCH_M_EDS UHD +3V_PCH EC and Mini card debug port LPC_AD0 <40,46> LPC_AD1 <40,46> LPC_AD2 <40,46> LPC_AD3 <40,46> A20 LPC_AD1 C20 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_FRAME# LAD_0 A18 LAD_2 C18 1 10K_0402_5% 2 RH104 2 33_0402_5% 2 33_0402_5% 2 RH333 SPI_CS1#_R 1 R_short 0_0402_5% 1 R_short 0_0402_5% SPI_CLK_PCH AJ11 SPI_SB_CS0# AJ7 LDRQ0# SML1ALERT#/PCHHOT#/GPIO74 SPI_SI_R SPI_SI_R1 RH1331 RH2051 2 33_0402_5% 2 33_0402_5% SPI_SO_L SPI_SO_L1 RH1312 RH3342 1 33_0402_5% 1 33_0402_5% SPI_SI AH1 SPI_SO_R AH3 10K_0402_5% SML0CLK 1 RH336 2 DRAMRST_CNTRL_PCH <6> 10K_0402_5% SML0DATA 1 RH337 2 10K_0402_5% PCH_HOT# 2 RH140 1 10K_0402_5% N11SML1DATA AF11 CL_CLK AF10 CL_DATA SPI_CS0# AF7 CL_RST# SPI_CS1# AJ10 C 2 RH335 1 K6 SML1CLK SML1CLK/GPIO58 SERIRQ AL7 SPI_CS1# 10K_0402_5% DRAMRST_CNTRL_PCH H6 PCH_HOT# LDRQ1#/GPIO23 C-Link RH134 1 R7 SML0DATA SML0DATA SPI_CLK 2 U8 SML0CLK SML1DATA/GPIO75 2 RH130 SPI_SB_CS0#_R N8 SML0ALERT#/GPIO60 SPI SPI_CLK_PCH_0 RH3311 SPI_CLK_PCH_1_R RH3321 SMBDATA LFRAME# AL11 SERIRQ PCH_GPIO11 U11PCH_SMBDATA SML0CLK B21 PCH_GPIO11 R10 PCH_SMBCLK SMBCLK LAD_3 G20 SERIRQ +3VS SMBus LAD_1 D21 <46> N7 SMBALERT#/GPIO11 LPC <40,46> LPC_AD0 SPI_CS2# TP1 SPI_MOSI TP2 Thermal SPI_MISO TP4 AJ4 SPI_IO2 TP3 AJ2 SPI_IO3 3 OF 11 PAD T118 @ BC45 PAD T119 @ BE43 PAD T120 @ BE44 PAD T121 @ AY43 TD_IREF LYNXPOINT_BGA695 BA45 1 PCH_TD_IREF RH322 C 2 8.2K_0402_1% REV = 5 +3VS +3VS <46> SPI_SI_R1 <46> SPI_SO_L1 <46> SPI_CLK_PCH_1 1 RH136 2 2.2K_0402_5% 1 RH135 2 2.2K_0402_5% SPI_CLK_PCH_1_R 2.2K_0402_5% 2 RH138 1 2.2K_0402_5% 3 PCH_SMBDATA D SPI_CLK_PCH_1_R RH115 1 @ 16Mb Flash ROM CH190 @ 32Mb Flash ROM +3VS 1 +3V_PCH CH200 2 S SMB_DATA_S3 QH162B 2N7002KDWH_SOT363-6 1 RH141 2 2.2K_0402_5% 1 RH142 2 2.2K_0402_5% 2 3.3K_0402_5% 2 3.3K_0402_5% SPI_WP#_1 SPI_HOLD#_1 10P_0402_50V8J 8 7 6 5 SPI_HOLD# SPI_CLK_PCH_0 SPI_SI_R 1 2 1 CH191 0.1U_0402_16V4Z SPI_CS1#_R 1 SPI_SO_L1 2 SPI_WP#_1 3 W25Q16DVSSIQ_SO8 4 /CS SML1DATA DO /WP GND VCC /HOLD CLK DIO 8 1 7 SPI_HOLD#_1 6 SPI_CLK_PCH_1_R 5 SPI_SI_R1 2 EC_SMB_CK2 EC_SMB_CK2 <23,32,34,36,43,46> EC_SMB_DA2 <23,32,34,36,43,46> QH61A 2N7002KDWH_SOT363-6 +3VS UH53 VCC HOLD# CLK DI 6 3 4 S +3VS UH52 CS# DO WP# GND 5 RH3301 RH2571 10P_0402_50V8J G SPI_WP# SPI_HOLD# B 2 D 2 3.3K_0402_5% 2 3.3K_0402_5% <11,12,40,47> +3VS SML1CLK RH1271 RH1291 SMB_DATA_S3 DIMM1, DIMM2, Mini CARD, TP 10_0402_5% 2 @ 1 4 2 For EMI 10_0402_5% 2 @ <11,12,40,47> G RH111 SPI_CLK_PCH_0 1 SMB_CLK_S3 QH162A 2N7002KDWH_SOT363-6 S 1 0_0402_5% For EMI 1 2 3 4 RH137 1 SMB_CLK_S3 D 2 1 G SPI_CLK_PCH_1 RH338 6 D 5 PCH_SMBCLK @ SPI_SB_CS0#_R SPI_SO_L SPI_WP# 2 SPI_SO_L1 B +3VS 2N7002KDWH Vth= min 1V, max 2.5V ESD 2KV 2 +3V_PCH SPI_SI_R1 G SPI_CS1#_R S <46> VGA, EC, Thermal Sensor SPI_CS1#_R EC_SMB_DA2 QH61B 2N7002KDWH_SOT363-6 CH275 0.1U_0402_16V4Z W25Q32FVSSIQ_SO8 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (4/9) LVDS, CRT,DP,HDMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 17 of Rev 1.0 69 5 4 3 2 1 D D LPT_PCH_M_EDS UHI USB30_RX_N5 USB30_RX_P5 <49> <49> USB30_TX_N5 USB30_TX_P5 <48> <48> USB30_RX_N6 USB30_RX_P6 <48> <48> USB30_TX_N6 USB30_TX_P6 AW31 AY31 USB30_TX_N5 USB30_TX_P5 BE32 BC32 USB30_RX_N6 USB30_RX_P6 AT31 AR31 USB30_TX_N6 USB30_TX_P6 BD33 BB33 AW33 AY33 BE34 BC34 <41> <41> C LAN PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 <40> <40> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 <40> <40> PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5 CH192 1 CH193 1 CH194 1 CH195 1 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 AT33 AR33 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 BE36 BC36 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 AW36 AV36 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 BD37 BB37 AY38 AW38 BC38 BE38 AT40 AT39 BE40 BC40 AN38 AN39 BD42 BD41 +1.5VS 1 2 PCH_PCIE_IREF 0_0402_5% RH51 BE30 @ T124 PAD BC30 @ T125 PAD BB29 B +1.5VS 1 RH210 2 PCH_PCIE_RCOMP BD29 7.5K_0402_1% USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9 USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13 PETN1/USB3TN3 PETP1/USB3TP3 PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4 PERN_3 PERP_3 PETN_3 PETP_3 PERN_4 PERP_4 PETN_4 PETP_4 PCIe WLAN <41> <41> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PERN1/USB3RN3 PERP1/USB3RP3 PERN_5 PERP_5 USB <49> <49> USB30_RX_N5 USB30_RX_P5 PETN_5 PETP_5 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 PERN_6 PERP_6 PETN_6 PETP_6 PERN_7 PERP_7 PETN_7 PETP_7 PERN_8 PERP_8 PETN_8 PETP_8 USBRBIAS# USBRBIAS PCIE_IREF TP24 TP23 TP11 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14 TP6 PCIE_RCOMP B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 <35> <35> <50> <50> <49> <49> <49> <49> <48> <48> Camera RIGHT USB 1 (SUB/B) LEFT USB LEFT USB Card reader Some PCH config not support USB port 6 & 7. USB20_N8 USB20_P8 USB20_N8 USB20_P8 USB20_N10 USB20_P10 AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28 K24 K26 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 Touch panel <50> <50> USB20_N10 USB20_P10 PAD PAD <40> <40> T180 @ T181 @ Debug port, reserved test point WLAN C USB3.0 USB30_RX_N2 USB30_RX_P2 USB30_TX_N2 USB30_TX_P2 USB30_RX_N2 USB30_RX_P2 USB30_TX_N2 USB30_TX_P2 <49> <49> <49> <49> 1 22.6_0402_1% PAD PAD Port2 LEFT USB Port5 LEFT USB Port6 Card reader RH218 2 USBRBIAS Within 500 mils M33 L33 Port1 +3V_PCH T122 @ T123 @ RPH3 P3 V1 U2 P1 M3 T1 N2 M1 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# USB_OC0# USB_OC1# 4 3 2 1 USB_OC5# USB_OC2# USB_OC7# USB_OC0# <50> <49> 5 6 7 8 B 10K_1206_8P4R_5% RPH4 LYNXPOINT_BGA695 9 OF 11 4 3 2 1 USB_OC6# USB_OC1# USB_OC4# USB_OC3# REV = 5 5 6 7 8 10K_1206_8P4R_5% A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (5/9) PCI, USB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 18 of Rev 1.0 69 5 4 <35> 1 CMOS_ON# RH156 CMOS_ON# 3 2 2 1 Function PCH_GPIO68 0_0402_5% PCH_GPIO38 PCH_GPIO67 PCH_GPIO70 X X 2 10K_0402_5% X LPT_PCH_M_EDS UHF 2 10K_0402_5% EC_LID_OUT# RH232 1 0_0402_5% 2 DGPU_PWROK RH238 2@ 10K_0402_1% 1 RH231 1 <15,40,41> 0_0402_5% PCIE_WAKE# +3V_PCH 2 10K_0402_5% PCH_BT_DISABLE# <40> Y10 R11 PCH_GPIO28 AD11 1 2 10K_0402_5% PCH_BT_ON# AN6 2 10K_0402_5% PCH_GPIO35 AP1 ODD_DETECT# AT3 RH242 RH243 1 @ <44> waiting check C DS3_WAKE#_R BB4 2 10K_0402_5% +3VS +3VS AN2 RH2411 PCH_BT_ON# waiting check ODD_EN <44> ODD_EN @ 1 RH224 2 AB11 PCH_DGPU_PWROK C14 PCH_BT_DISABLE# waiting check Y1 K13 ODD_DETECT# PCH_GPIO37 AK1 PCH_GPIO38 +3VS AT7 RH247 1 2 10K_0402_5% PCH_GPIO39 AM3 RH248 1 2 10K_0402_5% PCH_GPIO48 AN4 RH252 1 +3V_PCH 2 SLAVE_PRESENT# AK3 PCH_GPIO49 10K_0402_5% <32> SLAVE_PRESENT# SLAVE_PRESENT# U12 PCH_GPIO68 C16 <32,54,55> S_DGPU_PWR_EN <32,54> S_NVDD_PWR_EN RH249 RH251 2 2 1 0_0402_5% PCH_S_DGPU_PWR_EN D13 Reseve for SKU ID PCH_GPIO70 G13 1 0_0402_5% 1 RH154 PCH_S_NVDD_PWR_EN 2 TP_VSS_NCTF 0_0402_5% GPIO28 On-Die PLL Voltage Regulator This signal has a weak internal pull up * H L RH240 1 @ 2 1K_0402_5% PCH_GPIO28 BE41 BE5 C45 A5 <37> HDSW_DDC <37> HDSW_MAIN 0 X 1 TACH3/GPIO7 GPIO8 RH2361 LAN_PHY_PWR_CTRL/GPIO12 TP14 GPIO15 PECI SATA4GP/GPIO16 RCIN# GPIO TACH0/GPIO17 PROCPWRGD SCLOCK/GPIO22 THRMTRIP# GPIO24 PLTRST_PROC# GPIO27 VSS 2 10K_0402_5% AN10 +3VS GATEA20 <46> AY1 AT6 +3VS SKU ID KBRST# KBRST# AV3 <46> H_CPUPWRGD AV1PCH_THRMTRIP#_R 1 RH239 AU4 CPU_PLTRST# <6> 2 H_THRMTRIP# 390_0402_5% CPU_PLTRST# RH711 H_THRMTRIP# <6> PCH_THRMTRIP#_R <23,32> <6> N10 GPIO28 PCH_GPIO38 GPIO34 <16> RH704 @ PCH_GPIO70 SATA2GP/GPIO36 C SATA3GP/GPIO37 SLOAD/GPIO38 RH712 SDATAOUT0/GPIO39 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71 VSS VSS VSS VSS NCTF 0_0402_5% 1 2 RH161 0_0402_5% 1 2 RH171 6 OF 11 A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4 +3VS 1 RH1493EC_SCI# 10K_0402_5% 2 RH709 RH706 @ +3V_PCH RH235 2 1 10K_0402_5% EC_SMI# +3VS 2 RH265 2 RH266 1 1 +3VS PCH_GPIO16 10K_0402_5% PCH_GPIO49 10K_0402_5% REV = 5 1 @ RH272 2 @ RH268 2 1 10K_0402_5% 2 1 PCH_GPIO68 RH255 10K_0402_5% 2 1 RH226 KBRST# PCH_GPIO16 10K_0402_5% PCH_GPIO49 10K_0402_5% B PCH_GPIO39 PCH_GPIO48 Config +3VS GPIO16,49 10K_0402_5% * RH708 PCH_GPIO67 PCH_GPIO67 GPIO35/NMI# LYNXPOINT_BGA695 ：：On-Die voltage regulator enable On-Die PLL Voltage Regulator disable B H15 X X 2 PCH_GPIO12 X 15" 1 EC_SMI# D 10K_0402_5% 1 EC_SMI# 2 10K_0402_5% 14" 2 RH230 <46> @ CPU/Misc 1 1 TACH2/GPIO6 2 RH229 EC_SCI# TACH1/GPIO1 1 G15 10K_0402_5% A14 EC_SCI# 2 PCH_GPIO6 X BMBUSY#/GPIO0 1 2 10K_0402_5% PCH_GPIO16 +3VS <40> 1 EC_LID_OUT# +3VS waiting check <27,54,62,63> RH228 <46> F13 10K_0402_5% <46> PCH_GPIO1 @ 2 +3V_PCH 2 10K_0402_5% 1 1 +3VS 1 1 10K_0402_5% AT8 RH227 Reserve 2 D 10K_0402_5% +3VS 1 1 RH225 GC6_EVENT#_R @ RH233 @ 2 10K_0402_5% 0_0402_5% GC6_EVENT# 1 <23,54> * PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable USB X4,PCIEX8,SATAX6 11 USB X6,PCIEX8,SATAX4 01 2 1 RH1517 S_DGPU_PWR_EN +3VALW DS3@ RH207 2 1 10K_0402_5% DS3_WAKE#_R A A @ +3VS RH250 ODD_DETECT# 200K_0402_5% 1 2 1 2 10K_0402_5% RH259 PCH_GPIO37 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (6/9) GPIO, CPU, MISC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 19 of Rev 1.0 69 5 4 3 2 1 70mA UHG 2 +1.5VS +1.05V_+1.5V_RUN 2 VCCADAC1_5 1 1 2 +1.05VS 1 +1.05VS_PCH_VCCASW RH209 2 +1.05VS_PCH_VCCASW VCCVRM FDI VCCIO VCCIO VCC3_3_R30 VCC3_3_R32 HVCMOS DCPSUS1 VCCSUS3_3 VCCSUS3_3 DCPSUS3 DCPSUS3 VCCIO VCCVRM VCCVRM USB3 VCCVRM PCIe/DMI VCCIO VCCVRM SATA VCCIO +PCH_VCCDSW_R 2 AN35 R30 R32 Y12 1 2 +3VS_PCH_VCC3_3 +PCH_USB_DCPSUS1 1 +3VPCH_PCH_VCCSUS3_3 AJ30 AJ32 +3VPCH_PCH_VCCSUS3_3 AJ26 AJ28 AK20 AK26 AK28 +PCH_USB_DCPSUS3 2 C +1.05V_+1.5V_RUN +1.05VS_PCH_VCCIO +1.05V_+1.5V_RUN 1 BE22 AK18 +1.05V_+1.5V_RUN +1.05VS_PCH_VCCIO 1 AN11 AK22 1 +1.05VS_PCH_VCCIO AM18 AM20 AM22 AP22 AR22 AT22 2 1 2 REV = 5 1 2 1 2 1 2 1 2 CH44 10U_0603_6.3V6M 2 +3VS_PCH_VCC3_3 CH45 1U_0402_6.3V6K RH37 AN34 CH46 1U_0402_6.3V6K 1 B 7 OF 11 1 BB44 CH47 1U_0402_6.3V6K LYNXPOINT_BGA695 +3VS CH86 1U_0402_6.3V6K VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCMPHY +1.05VS_PCH_VCCIO M31 @ CH85 10U_0603_6.3V6M DCPSUSBYP VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW P43 2 2 @ CH82 10U_0603_6.3V6M 2 VCCADACBG3_3 @ CH83 10U_0603_6.3V6M 2 1 CH36 1U_0402_6.3V6K 2 1 CH35 1U_0402_6.3V6K 1 CH64 22U_0805_6.3V6M R_short 0_0603_5% +PCH_VCCDSW U14 AA18 U18 U20 U22 U24 V18 V20 V22 V24 Y18 Y20 Y22 VSS CRT DAC Core 670mA VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC CH48 1U_0402_6.3V6K 2 1 CH31 1U_0402_6.3V6K 1 CH33 1U_0402_6.3V6K 2 CH32 1U_0402_6.3V6K 2 1 CH38 0.1U_0402_10V7K AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24 Y26 +1.05VS_PCH_VCC 1 CH30 10U_0603_6.3V6M JUMP_43X39 P45 @ CH81 10U_0603_6.3V6M 2 D LPT_PCH_M_EDS +1.05VS_PCH_VCC J1 C 2 1 1_0603_1% CH56 10U_0603_6.3V6M 1.312 A +1.05VS 1 CH80 0.1U_0402_10V7K 2 CH57 0.01U_0402_16V7K 1 RH1 1 2 +VCCADAC D +PCH_VCCDSW 5.11_0402_1% B 2 CH34 1U_0402_6.3V6K 1 +1.05VS 1 2 2 1 RH360 @ @ CH61 1U_0402_6.3V6K +PCH_USB_DCPSUS1 0_0402_5% +1.05VS 2 A 2 2 RH199 @ A Title LC Future Center Secret Data Security Classification Issued Date 1 1 @CH39 @ CH39 1U_0402_6.3V6K 1 @CH40 @ CH40 10U_0603_6.3V6M +PCH_USB_DCPSUS3 0_0603_5% 2012/07/01 2014/07/01 Deciphered Date PCH (7/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 20 of Rev 1.0 69 5 4 3 2 1 +3VPCH_PCH_VCCSUS3_3 15mA 1 +1.05VS M24 U35 L24 AF34 L29 2 +PCH_USB_DCPSUS2 0_0402_5% AA30 AA32 AD35 AG30 AG32 AD36 +1.05VS AE30 AE32 @ RH215 1 10mA +3VS +3VPCH_VCCSUSHDA A26 1 VCCVRM VCC VCCSUS3_3 VCCCLK VCCRTC RTC VCCCLK3_3 DCPRTC DCPRTC +RTCVCC K8 P14 P16 +PCH_DCPRTC VCCCLK3_3 VCCCLK3_3 VCCCLK3_3 V_PROC_IO V_PROC_IO CPU VCCCLK3_3 VCCCLK3_3 VCCSPI SPI VCCCLK VCC VCC VCCCLK VCCCLK VCCASW Fuse VCCCLK VCCASW VCCCLK VCCCLK VCCVRM VCCCLK VCC3_3 Thermal VCCCLK VCCCLK VCC3_3 LYNXPOINT_BGA695 8 OF 11 CH70 1 2 1 0.1U_0402_10V7K +PCH_VPROC AJ12 AJ14 2 +3VS_PCH_VCCSPI AD12 P18 P20 1 +PCH_VCCCFUSE 2 L17 R18 AK30 1 2 C +1.05V_+1.5V_RUN AK32 REV = 5 1 2 Place near pin AD34 2 +3VS +1.05V_+1.5V_RUN RH220 RH221 +3VS +1.05VS B +PCH_VCCCLK3_3 1 Place near pin M29 Place near pin L29 1 2 1 2 Place near pin L26,M26 CH54 1U_0402_6.3V6K 2 CH53 1U_0402_6.3V6K +3VPCH_PCH_VCCSUS3_3 RH211 1 1 CH52 1U_0402_6.3V6K 2 CH51 1U_0402_6.3V6K +3V_PCH 2 1 0_0805_5% R_short 0_0805_5% 183mA 1 0_0603_5% A 2 2 1 2 RH212 2 1 2 2 1 2 0_0805_5% 55mA RH197 1 R_short 0_0603_5% @ RH198 2 R_short 0_0805_5% Place near pin AG30,AG32,AE30,AE32 +1.5VS 2 2 1 1 Place near pin AD35,AD36 JUMP_43X39 +1.05VS 1 CH88 1U_0402_6.3V6K Place near pin Y32,AA30,AA32 1 CH78 1U_0402_6.3V6K 2 CH77 1U_0402_6.3V6K 3.629A CH50 1U_0402_6.3V6K 2 1 CH79 1U_0402_6.3V6K R_short 0_0805_5% CH75 1U_0402_6.3V6K 1 +1.05VS_PCH_VCCIO 2 1 +PCH_VCCCFUSE RH200 2 J2 1 2 RH219 +PCH_VPROC @ 22mA 2 +1.05VS +3VS_PCH_VCC3_3 +PCH_VCCCLK 306mA 1 1 2 2 Place near pin AP45 1 +1.05VS 1 2 +1.05VS_PCH_VCCASW AW40 2 RH213 1 R_short 0_0603_5% 1 A6 +3VS_PCH_VCCSPI 2 2 +3VPCH_PCH_VCCSUS3_3 VCCSUSHDA 1 +1.05VS_PCH_VCCIO U36 1 +1.05VS B 2 0.1U_0402_10V7K CH71 1U_0402_6.3V6K 2 R_short 0_0603_5% 2 +PCH_VCCSST 1 CH84 CH72 0.1U_0402_10V7K 2 1 AA14 AE14 AF12 AG14 CH73 0.1U_0402_10V7K 1 D Azalia DCPSUS2 +3VALW +3VS_PCH_VCC3_3 CH76 0.1U_0402_10V7K 2 R_short 0_0603_5% +3VPCH_VCCSUSHDA +3V_PCH VCCIO CH49 1U_0402_6.3V6K 1RH1516 +PCH_VCC CH43 10U_0603_6.3V6M LH100 1 2 4.7UH_LQM18FN4R7M00D_20% VCCIO VCCIO VCCIO VCCIO +3V_PCH RH201 @ 1 RH1515 CH74 1U_0402_6.3V6K 2 AD34 +PCH_VCCCLK VCC3_3 VCC3_3 VCC3_3 VCC3_3 ICC 1 C U32 V32 DCPSST VCCUSBPLL +PCH_VCCDSW3_3 CH67 1U_0402_6.3V6K +PCH_VCCCLK3_3 L26 M26 @ CH87 1U_0402_6.3V6K 1 @ RH361 M29 VSS A16 CH68 0.1U_0402_10V7K +1.05VS Y32 +PCH_VCCCLK VCCDSW3_3 CH69 0.1U_0402_10V7K 2 AP45 +PCH_VCC 2 GPIO/LPC CH58 1U_0402_6.3V6K 1 CH42 10U_0603_6.3V6M 2 +PCH_USB_DCPSUS2 Y35 +1.05V_+1.5V_RUN CH37 1U_0402_6.3V6K 1 2 1 CH66 0.1U_0402_10V7K 2 U30 V28 V30 Y30 +1.05VS_PCH_VCCIO VCCSUS3_3 VCCSUS3_3 R20 R22 1 CH65 0.1U_0402_10V7K 1 CH63 0.1U_0402_10V7K 2 +3VS_PCH_VCC3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 USB 1 CH62 0.1U_0402_10V7K 2 CH59 0.1U_0402_10V7K D R24 R26 R28 U26 2 0_0402_5% R_short 0_0402_5% 2 CH55 0.1U_0402_10V7K 1 +3VPCH_PCH_VCCSUS3_3 CH60 0.1U_0402_10V7K LPT_PCH_M_EDS UHH Place near pin U32,V32 A 261mA R_short 0_0603_5% +3VS +3VS_PCH_VCC3_3 RH214 1 2 Issued Date R_short 0_0603_5% 5 Title LC Future Center Secret Data Security Classification 133mA 2012/07/01 2014/07/01 Deciphered Date PCH (8/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 4 3 2 1 Sheet 21 of Rev 1.0 69 5 4 3 2 1 D D UHJ AL34 AL38 AL8 AM14 AM24 AM26 AM28 AM30 AM32 AM16 AN36 AN40 AN42 AN8 AP13 AP24 AP31 AP43 AR2 AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38 D42 AV13 AV22 AV24 AV31 AV33 BB25 AV40 AV6 AW2 F43 AY10 AY15 AY20 AY26 AY29 AY7 B11 B15 C B LPT_PCH_M_EDS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS UHK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8 AA16 AA20 AA22 AA28 AA4 AB12 AB34 AB38 AB8 AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40 AD6 AD8 AE16 AE28 AF38 AF8 AG16 AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38 AJ6 AJ8 AK14 AK24 AK43 AK45 AL12 AL2 BC22 BB42 LPT_PCH_M_EDS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS LYNXPOINT_BGA695 LYNXPOINT_BGA695 10 OF 11 11 OF 11 B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28 C B REV = 5 REV = 5 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date PCH (9/9) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 22 of Rev 1.0 69 5 4 3 2 1 +3VS_VGA UV1A B UV2 4 Y PLT_RST_VGA# 3 A RV111 10K_0402_5% AJ11 1 NC7SZ08P5X_NL_SC70-5 <16> <16> R1495 @ 1 B CLK_PCIE_VGA CLK_PCIE_VGA# 1 2 @ RV20 200_0402_1% Differential signal 0_0402_5% CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU# AL13 AK13 AK12 PEX_TSTCLK_OUT PEX_TSTCLK_OUT# AJ26 AK26 PLT_RST_VGA# AJ12 AP29 2 1 RV22 2 PEX_TERMP 2.49K_0402_1% R4 R5 I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA R2 R3 I2CC_SCL I2CC_SDA AE8 SP_PLLVDD PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N PEX_RST_N PEX_TERMP AD7 VID_PLLVDD XTAL_IN XTAL_OUT XTAL_OUTBUFF XTAL_SSIN XTAL_IN XTAL_OUT XTALOUT XTALSSIN 1 10K_0402_5% 2 1 DGPU_PWR_EN XTAL_IN 1 2 1 4 N14P-GT-A2_FCBGA908 +3VS_VGA 1 2 10K_0402_5% 1 2 6 3 4 1 1 3 2 1 RV223 10K_0402_5% CV151 0.1U_0402_10V7K 2 2 2 2.2K_0402_5% 2 2.2K_0402_5% Under GPU 1 2 1 2 1 Near GPU 2 1 2 1 2 1 LV5 2 1 BLM18PG181SN1D_0603 +3VS_VGA 2 <23,27,54> 2 1 3 GND OUT IN GND 3XTAL_OUT 2 +PLLVDD 27MHZ_10PF_7V27000050 CV37 10P_0402_50V8J 1 2 CV38 10P_0402_50V8J 2N7002H 1N_SOT23-3 1 2 1 LV7 1 2 0_0402_5% +1.05VS_VGA 2 A CLK_REQ_GPU# Under GPU Near GPU 2 CLK_REQ_GPU#_R D <16> QV16 1 2 RV32 10K_0402_5% 2 G LP2301ALT1G_SOT-23 1 S 3 1 RV15 1 RV17 Crystal GT@ S FB_CLAMP I2CC_SDA 150_0402_1% 220 ohms @100MHz (ESR=0.05) 120mA +DACA_VDD @ RV232 @RV232 10K_0402_5% RV237 10K_0402_5% GC6@ @ 1 RV233 2 0_0402_5% Issued Date Title LC Future Center Secret Data Security Classification 1 S I2CC_SCL 150_0402_1% 2 2012/07/01 Deciphered Date 2014/07/01 N13P_PCIE/ DAC/ GPIO 2 QV3 2N7002KW_SOT323-3 GC6@ GC6@ CV148 150_0402_1% 2 B 2 RV26 2 2 1 2 G <14,23,54,55> For GC6 1 2 YV1 RV230 10K_0402_5% @ RV231 RV236 10K_0402_5% GC6@ QV2 100K_0402_5% 2 UV1 1 0.1U_0402_10V7K <14,23,54,55> DGPU_PWR_EN 3 A D 2 G GC6@ 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 1 2 RV23 10M_0402_5% 2 1 2 1 RV239 2 1 1K_0402_5% GC6@ D 1 RV106 1 RV108 1 RV109 VGA_CRT_B Internal Thermal Sensor 1 RV235 10K_0402_5% GC6@ 2 +SP_PLLVDD GT1@ +3VS_VGA RV16 1 C <19,54> +3VS_VGA 1 RV14 1 VGA_CRT_DATA RV10 1 VGA_CRT_CLK RV11 1 I2CB_SCL RV12 1 I2CB_SDA RV13 1 OVERT# RV1 1 VGA_AC_DET_R RV2 Close to GPU VGA_CRT_R VGA_CRT_G J4 H1 GC6_EVENT# VGA_ALERT# 2 0_0402_5% @ 45mA H3 H2 2 QV6 2N7002KW_SOT323-3 GPIO 14 of GPU connect to PCH GPIO 0 VGA_BL_PWM 1 RV112 1 1 LVDS RV27 10K_0402_5% N14P-GT1-A2_FCBGA908 RV238 0_0402_5% GC6@ 2 +PLLVDD 45mA 3 FB_CLAMP_TOGGLE_REQ# CRT VGA_SMB_CK2 VGA_SMB_DA2 60mA PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N <37> <37> 1 I2CC_SCL I2CC_SDA AD8 PLLVDD PEX_WAKE_N VGA_CRT_CLK VGA_CRT_DATA I2CB_SCL I2CB_SDA T4 T3 I2CS_SCL I2CS_SDA RV52 100K_0402_5% 1 VGA_CRT_CLK VGA_CRT_DATA R7 R6 @ <37> <37> RV107 124_0402_1% FB_CLAMP_MON +3VS RV65 10K_0402_5% 1 VGA_CRT_HSYNC VGA_CRT_VSYNC +3VS_VGA CV128 1 <37> <37> <37> CV127 2 2 PLT_RST# DGPU_HOLD_RST# PLT_RST# DGPU_HOLD_RST# G <14,32,40,41,46> <14,54> P 5 2 VGA_CRT_R VGA_CRT_G VGA_CRT_B 4.7U_0603_6.3V6K 1 +DACA_VDD +DACA_VREF DACA_RSET 2012-0418 --> Stuff QV7, RV208 2012-0429 --> Add QV5, C38 has abnormal shutdown issue 1U_0402_6.3V6K C1061 0.1U_0402_16V4Z AG10 AP9 AP8 QV5 2N7002KW_SOT323-3 D +3VS DACA_VDD DACA_VREF DACA_RSET VGA_CRT_HSYNC VGA_CRT_VSYNC S PLT_RST_VGA# VGA_CRT_R VGA_CRT_G VGA_CRT_B AM9 AN9 D S PU AT EC SIDE, +3VS AND 4.7K DACA_HSYNC DACA_VSYNC D @ G 2N7002DW-T/R7_SOT363-6 C PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N <46> CV122 <17,32,34,36,43,46> AK14 AJ14 AH14 AG14 AK15 AJ15 AL16 AK16 AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25 PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K AK9 AL10 AL9 DACA_RED DACA_GREEN DACA_BLUE 5 2 OVERT# <28,29,30,31> Vendor recommand reserve PU/PD resistor CV139 EC_SMB_DA2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VGA_AC_DET <19,32> @ QV7A DMN66D0LDW-7 2N_SOT363-6 PLT_RST_VGA# 2 G 0.1U_0402_10V7K 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DV2 RB751V-40_SOD323-2 2 1 PCH_THRMTRIP#_R QV7B DMN66D0LDW-7 2N_SOT363-6 CV40 VGA_SMB_DA2 CV24 CV26 CV21 CV23 CV25 CV27 CV29 CV31 CV33 CV28 CV30 CV32 CV36 CV41 CV34 CV35 VGA_AC_DET_R <38> <37,39> 0.1U_0402_10V7K 2 QV1A 1 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 VGA_EDP_HPD DGPU_HDMI_HPD @ CV126 <17,32,34,36,43,46> VGA_EDP_HPD DGPU_HDMI_HPD <63> <32> <63> @ CV125 EC_SMB_CK2 2N7002DW-T/R7_SOT363-6 NVVDD PWM_VID VGA_AC_DET_R DPRSLPVR_VGA 22U_0805_6.3V6M 4 VGA_SMB_CK2 MEM_VREF NVVDD PWM_VID VGA_AC_DET_R CV131 QV1B 3 RV208 10K_0402_5% @ OVERT# VGA_ALERT# 0.1U_0402_10V7K 1 1 5 RV25 2.2K_0402_5% FB_CLAMP_TOGGLE_REQ# 0.1U_0402_10V7K 2 <35> <35> <35> 0.1U_0402_10V7K 2 1 CV5 CV4 CV112 CV113 2 1 0.1U_0402_10V7K 2 1 PCH_THRMTRIP#_R <23,27,54> CV130 2 2 +3VS_VGA 1 0.1U_0402_10V7K +3VS_VGA +SP_PLLVDD 4.7U_0402_6.3V6M 180ohms (ESR=0.2) Bead RV24 2.2K_0402_5% 150mA BLM18PG181SN1D_2P 2 22U_0805_6.3V6M LV1 1 +1.05VS_VGA VGA_BL_PWM VGA_ENVDD VGA_ENBKL FB_CLAMP 1 Under GPU(below 150mils) D 2 0_0402_5% 2 PCIE_CRX_GTX_P[0..15] @ FB_CLAMP_MON 1 RV138 VGA_BL_PWM VGA_ENVDD VGA_ENBKL P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 0.1U_0402_10V7K PCIE_CRX_GTX_P[0..15] Part 1 of 7 1 <32,5> PCIE_CRX_GTX_N[0..15] PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N GPIO PCIE_CRX_GTX_N[0..15] AN12 AM12 AN14 AM14 AP14 AP15 AN15 AM15 AN17 AM17 AP17 AP18 AN18 AM18 AN20 AM20 AP20 AP21 AN21 AM21 AN23 AM23 AP23 AP24 AN24 AM24 AN26 AM26 AP26 AP27 AN27 AM27 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P[0..15] DACs <32,5> +3VS_VGA PCIE_CTX_C_GRX_N[0..15] I2C PCIE_CTX_C_GRX_P[0..15] PCI EXPRESS PCIE_CTX_C_GRX_N[0..15] <32,5> CLK <32,5> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 23 of Rev 1.0 69 5 4 3 2 1 UV1D Part 4 of 7 for 15" dual channel IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N VDD_SENSE <38> <38> <38> <38> VGA_EDP_TX0+ VGA_EDP_TX0VGA_EDP_TX1+ VGA_EDP_TX1- VGA_EDP_TX0+ VGA_EDP_TX0VGA_EDP_TX1+ VGA_EDP_TX1- C <37> <37> <37> <37> <37> <37> <37> <37> GPU_HDMI_TX2+ GPU_HDMI_TX2GPU_HDMI_TX1+ GPU_HDMI_TX1GPU_HDMI_TX0+ GPU_HDMI_TX0GPU_HDMI_CLK+ GPU_HDMI_CLK- GPU_HDMI_TX2+ GPU_HDMI_TX2GPU_HDMI_TX1+ GPU_HDMI_TX1GPU_HDMI_TX0+ GPU_HDMI_TX0GPU_HDMI_CLK+ GPU_HDMI_CLK- RV19 1 VGA_EDP_AUX 100K_0402_5% 2 RV30 1 VGA_EDP_AUX# AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5 AE3 AE4 AF4 AF5 AD4 AD5 AG1 AF1 20120829 VA1 Change net name for add HDMI MUX 100K_0402_5% 2 AM1 AM2 AM3 AM4 AL3 AL4 AK4 AK5 B <38> <38> RV113 1 47K_0402_5% 2 GPU_HDMI_CLK RV114 1 47K_0402_5% 2 GPU_HDMI_DATA IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N GND_SENSE VGA_EDP_AUX VGA_EDP_AUX# HDMI <37> <37> GPU_HDMI_CLK GPU_HDMI_DATA 20120829 VA1 Change net name for add HDMI MUX VGA_EDP_AUX VGA_EDP_AUX# AK3 AK2 GPU_HDMI_CLK GPU_HDMI_DATA AB3 AB4 AF3 AF2 D L4 VCCSENSE_VGA VCCSENSE_VGA <63> L5 VSSSENSE_VGA VSSSENSE_VGA <63> trace width: 16mils differential voltage sensing. differential signal routing. TEST TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N AK11 AM10 AM11 AP12 AP11 AN11 TESTMODE 1 RV34 TV2 TV3 TV4 TV5 10K_0402_5% RV33 2 10K_0402_5% C SERIAL ROM_CS_N ROM_SCLK ROM_SI ROM_SO H6 H4 H5 H7 GENERAL BUFRST_N CEC MULTI_STRAP_REF0_GND AG3 AG2 +3VS_VGA IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N LVDS/TMDS AK1 AJ1 AJ3 AJ2 AH3 AH4 AG5 AG4 P8 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32 1 AJ9 AH9 AP6 AP5 AM7 AL7 AN8 AM8 AK8 AL8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC 2 D IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N NC AM6 AN6 AP3 AN3 AN5 AM5 AL6 AK6 AJ6 AH6 IFPC_AUX_I2CW _SCL IFPC_AUX_I2CW _SDA_N STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N THERMDP THERMDN ROM_CS# ROM_SCLK ROM_SI ROM_SO RV35 L2 ROM_SCLK <33> ROM_SI <33> ROM_SO <33> 10K_0402_5% 1 2 L3 J1 J2 J7 J6 J5 J3 1 RV38 2 40.2K_0402_1% STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 <33> <33> <33> <33> <33> B K3 K4 For EMI ROM_SCLK_R IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N RH123 1 @ 10_0402_5% 2 1 @ CH201 2 1MB SPI ROM FOR VBIOS ROM (SLI) N14P-GT-A2_FCBGA908 20mils 2 RV229 @ 10K_0402_5% RV224 @0_0402_5% 2 ROM_CS#_R ROM_CS#1 2 ROM_SO 1 ROM_SO_R RV226 @0_0402_5% A @ SA00004EK0J(2012/0813) @ UV15 1 2 3 4 CS# DO W P# GND VCC HOLD# CLK DIO 8 7 6 5 MX25L2006EMIT-12G SOP Issued Date 2012/07/01 ROM_HOLD# A RV228 @ 0_0402_5% 2 ROM_SCLK_R1 ROM_SCLK 2 ROM_SI_R 1 ROM_SI RV227 @ 0_0402_5% Title LC Future Center Secret Data Security Classification RV225 10K_0402_5% 2 @ 1 1 1 2 0.1U_0402_16V4Z 10P_0402_50V8J +3VS_VGA CV295 2014/07/01 Deciphered Date N13P_LVDS/ HDMI/ THERM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 Sheet 1 24 of Rev 1.0 69 3 2 UV1E 2 R_short 0_0402_5% F1 CALIBRATION PIN F2 FB_CAL_x_PD_VDDQ 40.2Ohm RV8 FB_CAL_x_PU_GND 40.2Ohm RV9 FB_CAL_xTERM_GND 1 2 40.2_0402_1% J27 1 2 40.2_0402_1% H27 1 2 60.4_0402_1% H25 RV6 GDDR5 2 1 2 CV52 CV51 10U_0603_6.3V6M CV50 10U_0603_6.3V6M CV49 10U_0603_6.3V6M CV48 CV47 10U_0603_6.3V6M 1 2 1 +1.05VS_VGA 1 D CV55 CV56 22U_0805_6.3V6M CV53 22U_0805_6.3V6M 2 1 4.7U_0603_6.3V6K CV46 CV45 1U_0402_6.3V6K CV44 1U_0402_6.3V6K 1U_0402_6.3V6K CV43 2 1 1 2 2 +3VS_VGA AG26 +PEX_PLLVDD 1 2 1 2 1 CV73 AG12 CV74 AH12 2 IFPA_IOVDD IFPB_IOVDD J8 K8 L8 M8 Place near balls 2 AG8 +IFPAB_IOVDD 1 AG9 10K_0402_5% 1 2 1 2 1 2 1 RV5 1 R_short 0_0603_5% CV75 @ 2 1 RV45 2 1K_0402_1% RV40 2 @ @ RV47 CV111 AH8 +IFPAB_PLLVDD 1 AJ8 10K_0402_5% +3VS_VGA Place near GPU +VDD33 CV293 4.7U_0603_6.3V6K FB_VDDQ_SENSE FB_VSS_SENSE 1 2 2 Under GPU(below 150mils) IFPAB_PLLVDD IFPAB_RSET +1.5VS_VGA Under GPU(below 150mils) 2 1 1U_0402_6.3V6K RV142 1 2 1 CV109 0.1U_0402_10V7K 2 R_short 0_0402_5% PEX_PLLVDD 2 1 0.1U_0402_10V7K RV141 1 VDDQ_SENSE PEX_SVDD_3V3 VDD33_0 VDD33_1 VDD33_2 VDD33_3 C <61> PEX_PLL_HVDD 2 CV70 2 2 1 4.7U_0603_6.3V6K 2 1 CV286 CV285 1 0.1U_0402_10V7K 2 CV284 1 0.1U_0402_10V7K 2 0.1U_0402_10V7K 2 1 CV294 CV287 CV292 2 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 CV280 CV279 CV282 CV278 2 1 0.1U_0402_10V7K 2 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K CV281 CV277 1 1U_0402_6.3V6K 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1U_0402_6.3V6K Under GPU(below 150mils) +1.5VS_VGA AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28 1 0.1U_0402_10V7K D PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 CV54 CV276 2 1 22U_0805_6.3V6M 2 1 +1.05VS_VGA AG19 AG21 AG22 AG24 AH21 AH25 1U_0402_6.3V6K 2 1 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 22U_0805_6.3V6M 2 1 FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 POWER 1 1 CV275 22U_0805_6.3V6M 1 2 CV274 22U_0805_6.3V6M 1 2 CV273 22U_0805_6.3V6M 1 2 CV272 22U_0805_6.3V6M 2 2 AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27 1 Near GPU 2000mA Part 5 of 7 3.5A CV271 10U_0603_6.3V6M 2 1 CV269 10U_0603_6.3V6M 2 1 CV268 10U_0603_6.3V6M 2 1 Near GPU CV267 4.7U_0603_6.3V6K 1 CV266 4.7U_0603_6.3V6K 2 CV265 4.7U_0603_6.3V6K 2 1 CV264 4.7U_0603_6.3V6K 1 CV263 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K For GDDR5 setting. CV270 10U_0603_6.3V6M +1.5VS_VGA 4.7U_0603_6.3V6K 4 4.7U_0603_6.3V6K 5 C 2 FB_VDDQ_SENSE IFPC_PLLVDD IFPC_RSET FB_GND_SENSE IFPC_IOVDD FB_CAL_PD_VDDQ IFPD_PLLVDD IFPD_RSET FB_CAL_PU_GND IFPD_IOVDD 1 @ 2 AF7 +IFPC_PLLVDD AF8 1 10K_0402_5% RV42 2 1K_0402_1% @ RV43 AF6 +IFPC_IOVDD 1 @ 2 10K_0402_5% RV44 AG7 +IFPD_PLLVDD AN2 2 1K_0402_1% IFPAB & IFPEF have to use 1 RV46 AG6 +IFPD_IOVDD FB_CAL_TERM_GND IFPEF_PLVDD IFPEF_RSET 60.4Ohm IFPE_IOVDD IFPF_IOVDD Place near balls AB8 +IFPEF_PLLVDD AD6 2 1K_0402_1% 1 RV50 AC7 +IFPE_IOVDD AC8 +1.05VS_VGA LV6 2 1 BLM18PG181SN1D_0603 CV66 CV3 4.7U_0805_25V6-K CV65 0.1U_0402_10V7K 0_0603_5% 2 B Place near balls 2 1 2 1 2 Place near balls Place near balls 2 2 2 +IFPD_IOVDD 1 CV197 1 CV216 0.1U_0402_10V7K 2 1 CV176 1 CV156 CV158 CV172 LV4 2 1 BLM18PG181SN1D_0603 +IFPE_IOVDD 1 1U_0402_6.3V6K 2 CV153 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K +1.05VS_VGA 570mA 1 0.1U_0402_10V7K 2 2 1 CV141 1 4.7U_0603_6.3V6K A 1 1U_0402_6.3V6K 4.7U_0603_6.3V6K LV10 2 1 BLM18PG181SN1D_0603 1 1 180ohms @100MHz (ESR=0.2) P/N: SM010030710 220ohms @100MHz (ESR=0.05) CV152 +1.05VS_VGA 2 RV4 2 +IFPD_PLLVDD 2 Place near balls 200mA CV140 CV150 CV173 2 +3VS_VGA +IFPEF_PLLVDD 1 CV146 2 1 120ohms @100MHz (ESR=0.18) P/N:SM01000BZ00 4.7U_0603_6.3V6K 2 1 0.1U_0402_10V7K 0.1U_0402_10V7K 2 1 CV147 1U_0402_6.3V6K 1 CV149 4.7U_0603_6.3V6K LV9 2 1 BLM18PG181SN1D_0603 CV171 0.1U_0402_10V7K 220mA 1U_0402_6.3V6K +3VS_VGA 0.1U_0402_10V7K 300ohms @100MHz (ESR=0.25) P/N: SM010031680 B 1 1U_0603_10V6K 120mA +PEX_PLLVDD N14P-GT-A2_FCBGA908 IFPA_IOVDD and IFPB_IOVDD combined 2 A Place near balls Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date N13P_Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 25 of Rev 1.0 69 5 4 3 2 1 UV1F Part 6 of 7 C AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 POWER Part 7 of 7 D B VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22 U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 W2 W3 W4 W5 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 N13P-GT1-A2_FCBGA908 A Issued Date 2012/07/01 Deciphered Date 4 3 2 D C B A N13P-GT1-A2_FCBGA908 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199 GND_OPT GND_OPT Title LC Future Center Secret Data Security Classification GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND +VGA_CORE UV1G +VGA_CORE A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 N13P_+VGA CORE, GND Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 26 of Rev 1.0 69 5 <30,31> 30ohms (ESR=0.01) Bead P/N;SM010007W00 2 1 FBC_D[0..63] FBC_D[0..63] PU for X16 mode UV1B PU for X16 mode UV1C Part 2 of 7 FBA_EDC[7..4] FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7 M31 G31 E33 M33 AE31 AK30 AN33 AF33 M30 H30 E34 M34 AF30 AK31 AM34 AF32 +1.5VS_VGA FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N FBA_WCKB01 FBA_WCKB01_N FBA_WCKB23 FBA_WCKB23_N FBA_WCKB45 FBA_WCKB45_N FBA_WCKB67 FBA_WCKB67_N FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FB_CLAMP FB_DLL_AVDD R30 R31 AB31 AC31 K31 L30 H34 J34 AG30 AG31 AJ34 AK34 J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33 E1 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N <28> <28> <29> <29> FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N <28> <28> <28> <28> <29> <29> <29> <29> GC6 support on 15" FB_CLAMP FB_CLAMP <30> <30> <30> <30> <31> <31> <31> <31> <23,54> RV66 NOGC6@ 10K_0402_5% 2 1 FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7# +FB_PLLAVDD K27 CV106 1 0.1U_0402_10V7K 2 Place close to ball FBA_PLL_AVDD FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FB_VREF U27 H26 1 2 Place close to ball 1 2 +FB_PLLAVDD 1 <30> FBC_EDC[3..0] <31> FBC_EDC[7..4] 2 Place close to BGA D10 D5 C3 B9 E23 E28 B30 A23 D9 E4 B2 A9 D22 D28 A30 B23 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 FBC_CS#_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA4_BA2_L FBC_MA5_BA1_L FBC_WE#_L FBC_MA7_MA8_L FBC_MA6_MA11_L FBC_ABI#_L FBC_MA12_RFU_L FBC_MA0_MA10_L FBC_MA1_MA9_L FBC_RAS#_L FBC_RST#_L FBC_CKE_L FBC_CAS#_L FBC_CS#_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA4_BA2_H FBC_MA5_BA1_H FBC_WE#_H FBC_MA7_MA8_H FBC_MA6_MA11_H FBC_ABI#_H FBC_MA12_RFU_H FBC_MA0_MA10_H FBC_MA1_MA9_H FBC_RAS#_H FBC_RST#_H FBC_CKE_H FBC_CAS#_H FBC_CS#_L <30> FBC_MA3_BA3_L <30> FBC_MA2_BA0_L <30> FBC_MA4_BA2_L <30> FBC_MA5_BA1_L <30> +1.5VS_VGA FBC_WE#_L <30> FBC_MA7_MA8_L <30> FBC_MA6_MA11_L <30> FBC_ABI#_L <30> RV210 FBC_MA12_RFU_L <30> 10K_0402_5% FBC_MA0_MA10_L <30> FBC_MA1_MA9_L <30> FBC_RAS#_L <30> FBC_RST#_L <30> FBC_CKE_L <30> FBC_CAS#_L <30> FBC_CS#_H <31> FBC_MA3_BA3_H <31> FBC_MA2_BA0_H <31> FBC_MA4_BA2_H <31> FBC_MA5_BA1_H <31> +1.5VS_VGA FBC_WE#_H <31> FBC_MA7_MA8_H <31> FBC_MA6_MA11_H <31> FBC_ABI#_H <31> RV222 FBC_MA12_RFU_H <31> 10K_0402_5% FBC_MA0_MA10_H <31> FBC_MA1_MA9_H <31> FBC_RAS#_H <31> FBC_RST#_H <31> FBC_CKE_H <31> FBC_CAS#_H <31> GDDR5 Mode H - Mirror Mode Mapping C12 C20 @ FBB_DEBUG0 FBB_DEBUG1 G14 60.4_0402_1% 1 G20 60.4_0402_1% 1 2RV60 2RV61 +1.5VS_VGA @ FBB_CLK0 FBB_CLK0_N FBB_CLK1 FBB_CLK1_N FBB_WCK01 FBB_WCK01_N FBB_WCK23 FBB_WCK23_N FBB_WCK45 FBB_WCK45_N FBB_WCK67 FBB_WCK67_N FBB_WCKB01 FBB_WCKB01_N FBB_WCKB23 FBB_WCKB23_N FBB_WCKB45 FBB_WCKB45_N FBB_WCKB67 FBB_WCKB67_N FBB_PLL_AVDD D12 E12 E20 F20 FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1# F8 E8 A5 A6 D24 D25 B27 C27 FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1# FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N <30> <30> <31> <31> FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N <30> <30> <30> <30> <31> <31> <31> <31> D6 D7 C6 B6 F26 E26 A26 A27 H17 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 1 @ RV68 GC6@ FBVDDQ_PWR_EN 5 2 NOGC6@ 0_0402_5% A4_BA2 FBx_CMD4 A5_BA1 FBx_CMD5 WE# FBx_CMD6 A7_A8 FBx_CMD7 A6_A11 FBx_CMD8 ABI# FBx_CMD9 A12_RFU FBx_CMD10 A0_A10 FBx_CMD11 A1_A9 FBx_CMD12 RAS# FBx_CMD13 RST# FBx_CMD14 CKE# FBx_CMD15 CAS# C FBx_CMD16 CS# FBx_CMD17 A3_BA3 FBx_CMD18 A2_BA0 FBx_CMD19 A4_BA2 FBx_CMD20 A5_BA1 FBx_CMD21 WE# FBx_CMD22 A7_A8 FBx_CMD23 A6_A11 FBx_CMD24 ABI# FBx_CMD25 A12_RFU FBx_CMD26 A0_A10 FBx_CMD27 A1_A9 FBx_CMD28 RAS# FBx_CMD29 RST# FBx_CMD30 CKE# FBx_CMD31 CAS# B 1 RV74 RV73 10K_0402_5% 10K_0402_5% 2 A <61> Issued Date 1 Title LC Future Center Secret Data Security Classification RV29 200K_0402_5% 2 DGPU_PWROK A2_BA0 FBx_CMD3 RV71 RV72 10K_0402_5% 10K_0402_5% RV156 <19,54,62,63> A3_BA3 FBx_CMD2 1 0_0402_5% DV3 DAN202UT106_SC70-3 2 1 3 FBx_CMD1 32..63 FBC_RST#_L FBC_RST#_H FBA_RST#_L FBA_RST#_H <32,54> CS# 2 2 10K_0402_5% S_GC6_EN 1 1 FB_CLAMP RV172 @ 2 2 RV169 S @ 2 0_0402_5% 1 GC6@ 2 GC6_EN RV18 0_0402_5% 3 A 1 FBx_CMD0 Place close to ball N14P-GT-A2_FCBGA908 @ QV4 2N7002_SOT23 1 1 D 2 G 0..31 2 N14P-GT-A2_FCBGA908 DGPU_GC6_EN DATA Bus Address +FB_PLLAVDD 1 +3VS <14,54> D 1 FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 FBB_CMD_RFU0 FBB_CMD_RFU1 D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 2 E11 E3 A3 C9 F23 F27 C30 A24 FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 1 FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7# FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 2 1 2 1 2 2RV58 2RV59 @ <29> G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26 1 <29> P30 F31 F34 M32 AD31 AL29 AM32 AF34 R28 60.4_0402_1% 1 AC28 60.4_0402_1% 1 <28> FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 2 FBA_EDC[3..0] FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7# R32 AC32 @ FBA_DEBUG0 FBA_DEBUG1 Part 3 of 7 CV108 <28> FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7# FBA_CS#_L <28> FBA_MA3_BA3_L <28> FBA_MA2_BA0_L <28> FBA_MA4_BA2_L <28> FBA_MA5_BA1_L <28> +1.5VS_VGA FBA_WE#_L <28> FBA_MA7_MA8_L <28> FBA_MA6_MA11_L <28> FBA_ABI#_L <28> RV209 FBA_MA12_RFU_L <28> 10K_0402_5% FBA_MA0_MA10_L <28> FBA_MA1_MA9_L <28> FBA_RAS#_L <28> FBA_RST#_L <28> FBA_CKE_L FBA_CAS#_L <28> FBA_CS#_H <29> FBA_MA3_BA3_H <29> FBA_MA2_BA0_H <29> FBA_MA4_BA2_H <29> FBA_MA5_BA1_H <29> +1.5VS_VGA FBA_WE#_H <29> FBA_MA7_MA8_H <29> FBA_MA6_MA11_H <29> FBA_ABI#_H <29> RV221 FBA_MA12_RFU_H <29> 10K_0402_5% FBA_MA0_MA10_H <29> FBA_MA1_MA9_H <29> FBA_RAS#_H <29> FBA_RST#_H <29> FBA_CKE_H FBA_CAS#_H <29> 0.1U_0402_10V7K <28> <28> <28> <28> <29> <29> <29> <29> B FBA_CMD_RFU0 FBA_CMD_RFU1 FBA_CS#_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA4_BA2_L FBA_MA5_BA1_L FBA_WE#_L FBA_MA7_MA8_L FBA_MA6_MA11_L FBA_ABI#_L FBA_MA12_RFU_L FBA_MA0_MA10_L FBA_MA1_MA9_L FBA_RAS#_L FBA_RST#_L FBA_CKE_L FBA_CAS#_L FBA_CS#_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA4_BA2_H FBA_MA5_BA1_H FBA_WE#_H FBA_MA7_MA8_H FBA_MA6_MA11_H FBA_ABI#_H FBA_MA12_RFU_H FBA_MA0_MA10_H FBA_MA1_MA9_H FBA_RAS#_H FBA_RST#_H FBA_CKE_H FBA_CAS#_H MEMORY INTERFACE B C U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 CV39 Place close to BGA FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 CV110 LV3 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 22U_0805_6.3V6M 200mA FBMA-L11-160808300LMA25T_2P 1 2 +FB_PLLAVDD D L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33 CV107 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 1U_0402_6.3V6K +FB_PLLAVDD 0.1U_0402_10V7K +1.05VS_VGA 3 FBA_D[0..63] FBA_D[0..63] MEMORY INTERFACE A <28,29> 4 2012/07/01 Deciphered Date 2014/07/01 N13P_MEM Interface THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 GC6@ 4 3 2 1 Sheet 27 of Rev 1.0 69 5 4 Memory - Lower 32 bits FBA_EDC0 <27> FBA_EDC2 FBA_D[0..31] FBA_EDC[3..0] <27> FBA_DBI0# <27> FBA_DBI2# FBA_DBI0# FBA_DBI2# D <27> <27> <27> <27> <27> <27> <27> FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L <27> <27> <27> <27> <27> FBA_MA7_MA8_L FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L FBA_MA12_RFU_L C2 C13 R13 R2 D2 D13 P13 P2 FBA_CLK0 FBA_CLK0# FBA_CKE_L J12 J11 J3 FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L H11 K10 K11 H10 FBA_MA7_MA8_L FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L FBA_MA12_RFU_L K4 H5 H4 K5 J5 FBA_CLK0 FBA_CLK0# FBA_CKE_L A5 U5 2 RV115 1 1K_0402_1% J1 J10 J13 2 RV117 1 2 RV119 1 1K_0402_1% 121_0402_1% Follow DG 1 RV21 2 40.2_0402_1% J4 G3 G12 L3 L12 FBA_ABI#_L FBA_RAS#_L FBA_CS#_L FBA_CAS#_L FBA_WE#_L FBA_ABI#_L FBA_RAS#_L FBA_CS#_L FBA_CAS#_L FBA_WE#_L RV123 160_0402_1% @ 2 40.2_0402_1% 1 <27> <27> FBA_WCK0_N FBA_WCK0 <27> <27> FBA_WCK1_N FBA_WCK1 CV155 1 RV28 0.01U_0402_25V7K FBA_CLK0# 1 C FBA_WCK0_N FBA_WCK0 D5 D4 FBA_WCK1_N FBA_WCK1 P5 P4 +FBA_VREFD_L A10 U10 J14 +FBA_VREFC0 EDC0 EDC1 EDC2 EDC3 EDC3 EDC2 EDC1 EDC0 DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# MF=1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC J2 FBA_RST#_L FBA_RST#_L 1 RV127 549_0402_1% 2 RV212 1 2 RV128 1.33K_0402_1% B 1 CV42 +FBA_VREFC0 820P_0402_25V7 1 2 931_0402_1% 16 mil 2 +1.5VS_VGA G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 1 +1.5VS_VGA RV129 549_0402_1% ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC RESET# 1 RV130 1.33K_0402_1% 2 2 G QV9 2N7002W-T/R7_SOT323-3 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD CV58 S +FBA_VREFD_L 820P_0402_25V7 1 MEM_VREF 3 <23,29,30,31> D 2 RV213 1 2 931_0402_1% DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ +1.5VS_VGA H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 MF=0 MF=0 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_EDC3 BYTE0 FBA_EDC1 <27> FBA_DBI3# <27> FBA_DBI1# FBA_DBI3# FBA_DBI1# FBA_CLK0 FBA_CLK0# FBA_CKE_L FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 BYTE2 2 170-BALL SGRAM GDDR5 C2 C13 R13 R2 D2 D13 P13 P2 J12 J11 J3 FBA_MA4_BA2_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA5_BA1_L H11 K10 K11 H10 FBA_MA0_MA10_L FBA_MA6_MA11_L FBA_MA7_MA8_L FBA_MA1_MA9_L FBA_MA12_RFU_L K4 H5 H4 K5 J5 A5 U5 +1.5VS_VGA 2 RV116 1 1K_0402_1% +1.5VS_VGA MF SEN ZQ 2 <27> 2 RV118 1 2 RV120 1 1K_0402_1% 121_0402_1% B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 FBA_ABI#_L FBA_CAS#_L FBA_WE#_L FBA_RAS#_L FBA_CS#_L J4 G3 G12 L3 L12 D5 D4 FBA_WCK0_N FBA_WCK0 P5 P4 +FBA_VREFD_L +FBA_VREFC0 FBA_RST#_L A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 J1 J10 J13 FBA_WCK1_N FBA_WCK1 +1.5VS_VGA A10 U10 J14 J2 H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 MF=1 EDC0 EDC1 EDC2 EDC3 EDC3 EDC2 EDC1 EDC0 DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC RESET# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 170-BALL 2 2 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 BYTE3 D FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 GDDR5 Mode H - Mirror Mode Mapping BYTE1 DATA Bus VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ Address 0..31 FBx_CMD0 CS# FBx_CMD1 A3_BA3 FBx_CMD2 A2_BA0 FBx_CMD3 A4_BA2 FBx_CMD4 A5_BA1 FBx_CMD5 B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 WE# FBx_CMD6 A7_A8 FBx_CMD7 A6_A11 FBx_CMD8 ABI# FBx_CMD9 A12_RFU FBx_CMD10 A0_A10 FBx_CMD11 A1_A9 FBx_CMD12 RAS# FBx_CMD13 RST# FBx_CMD14 CKE# FBx_CMD15 CAS# C FBx_CMD16 CS# FBx_CMD17 A3_BA3 FBx_CMD18 A2_BA0 FBx_CMD19 A4_BA2 FBx_CMD20 A5_BA1 FBx_CMD21 WE# FBx_CMD22 A7_A8 FBx_CMD23 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 2 1 A6_A11 FBx_CMD24 ABI# FBx_CMD25 A12_RFU FBx_CMD26 A0_A10 FBx_CMD27 A1_A9 FBx_CMD28 RAS# FBx_CMD29 RST# FBx_CMD30 CKE# FBx_CMD31 CAS# B 2 A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 32..63 CV136 1 CV135 1 CV134 1 0.1U_0402_10V7K 2 CV80 1 0.1U_0402_10V7K 2 CV79 1 0.1U_0402_10V7K 2 1U_0603_25V6 1 CV76 1U_0603_25V6 1 CV71 2 1U_0603_25V6 2 CV174 CV133 1 1U_0603_25V6 2 CV132 1 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 H5GQ1H24AFR-T2L_BGA170 10U_0603_6.3V6M 2 CV129 1 0.1U_0402_10V7K 2 CV78 1 0.1U_0402_10V7K 2 CV77 1 0.1U_0402_10V7K 2 1U_0603_25V6 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UV4 SIDE +1.5VS_VGA CV69 1U_0603_25V6 2 CV68 1 1U_0603_25V6 CV166 1U_0603_25V6 10U_0603_6.3V6M A 1 MF=0 X76@ H5GQ1H24AFR-T2L_BGA170 2 MF=1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 +1.5VS_VGA MF SEN ZQ SGRAM GDDR5 X76@ UV3 SIDE +1.5VS_VGA 1 UV4 MF=1 2 FBA_CLK0 <27> <27> <27> <27> <27> 2 UV3 MF=0 <27> 3 4 3 2 N13P_GDDR5_A Lower Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 28 of Rev 1.0 69 5 4 3 2 Memory - Upper 32 bits 1 UV6 UV5 MF=0 MF=0 FBA_EDC4 <27> <27> FBA_EDC6 FBA_D[63..32] FBA_EDC[7..4] D <27> <27> <27> <27> <27> <27> <27> <27> FBA_DBI4# <27> FBA_DBI6# FBA_CLK1 FBA_CLK1# FBA_CKE_H FBA_DBI6# J12 J11 J3 FBA_MA2_BA0_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA3_BA3_H H11 K10 K11 H10 K4 H5 H4 K5 J5 FBA_MA7_MA8_H FBA_MA1_MA9_H FBA_MA0_MA10_H FBA_MA6_MA11_H FBA_MA12_RFU_H FBA_MA7_MA8_H FBA_MA1_MA9_H FBA_MA0_MA10_H FBA_MA6_MA11_H FBA_MA12_RFU_H D2 D13 P13 P2 FBA_CLK1 FBA_CLK1# FBA_CKE_H FBA_MA2_BA0_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA3_BA3_H <27> <27> <27> <27> <27> FBA_DBI4# C2 C13 R13 R2 A5 U5 2 RV131 1 1K_0402_1% 2 RV133 1 2 RV135 1 1K_0402_1% 121_0402_1% Follow DG 1 RV31 2 40.2_0402_1% J4 G3 G12 L3 L12 FBA_ABI#_H FBA_RAS#_H FBA_CS#_H FBA_CAS#_H FBA_WE#_H FBA_ABI#_H FBA_RAS#_H FBA_CS#_H FBA_CAS#_H FBA_WE#_H EDC0 EDC1 EDC2 EDC3 EDC3 EDC2 EDC1 EDC0 DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC RV139 160_0402_1% @ 1 RV36 <27> <27> 2 40.2_0402_1% 0.01U_0402_25V7K FBA_CLK1# 1 FBA_WCK2_N FBA_WCK2 D5 D4 FBA_WCK3_N FBA_WCK3 P5 P4 +FBA_VREFD_H A10 U10 J14 FBA_WCK2_N FBA_WCK2 <27> <27> FBA_WCK3_N FBA_WCK3 CV175 1 C ABI# RAS# CS# CAS# WE# +FBA_VREFC1 WCK01# WCK01 WCK23# WCK23 CAS# WE# RAS# CS# WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC 2 <27> FBA_RST#_H FBA_RST#_H H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 1 +1.5VS_VGA RV143 549_0402_1% 2 RV214 1 2 RV144 1.33K_0402_1% 1 CV59 +FBA_VREFC1 820P_0402_25V7 1 2 931_0402_1% J2 16 mil +1.5VS_VGA RESET# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B 1 +1.5VS_VGA RV145 549_0402_1% VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 2 RV215 2 G S QV11 2N7002W-T/R7_SOT323-3 1 CV60 1 RV146 1.33K_0402_1% 2 MEM_VREF 3 <23,28,30,31> +FBA_VREFD_H 820P_0402_25V7 1 1 2 931_0402_1% D 170-BALL 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SGRAM GDDR5 MF=1 MF=1 MF=0 MF=0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 MF=1 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_EDC7 FBA_EDC5 BYTE4 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 <27> FBA_DBI7# <27> FBA_DBI5# FBA_DBI7# FBA_DBI5# C2 C13 R13 R2 D2 D13 P13 P2 FBA_CLK1 FBA_CLK1# FBA_CKE_H J12 J11 J3 FBA_MA4_BA2_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA5_BA1_H H11 K10 K11 H10 FBA_MA0_MA10_H FBA_MA6_MA11_H FBA_MA7_MA8_H FBA_MA1_MA9_H FBA_MA12_RFU_H K4 H5 H4 K5 J5 BYTE6 A5 U5 +1.5VS_VGA 2 RV132 1 1K_0402_1% +1.5VS_VGA MF SEN ZQ 2 FBA_CLK1 <27> <27> <27> <27> <27> J1 J10 J13 MF=1 2 RV134 1 2 RV136 1 1K_0402_1% 121_0402_1% B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 FBA_ABI#_H FBA_CAS#_H FBA_WE#_H FBA_RAS#_H FBA_CS#_H J4 G3 G12 L3 L12 FBA_WCK3_N FBA_WCK3 D5 D4 FBA_WCK2_N FBA_WCK2 P5 P4 +FBA_VREFD_H A10 U10 J14 +FBA_VREFC1 FBA_RST#_H A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 J1 J10 J13 +1.5VS_VGA J2 H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 EDC0 EDC1 EDC2 EDC3 EDC3 EDC2 EDC1 EDC0 DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 BYTE7 D FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 BYTE5 GDDR5 Mode H - Mirror Mode Mapping DATA Bus +1.5VS_VGA MF SEN ZQ ABI# RAS# CS# CAS# WE# VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC RESET# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 170-BALL SGRAM GDDR5 B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 Address 0..31 FBx_CMD0 CS# FBx_CMD1 A3_BA3 FBx_CMD2 A2_BA0 FBx_CMD3 A4_BA2 FBx_CMD4 A5_BA1 32..63 FBx_CMD5 WE# FBx_CMD6 A7_A8 FBx_CMD7 A6_A11 FBx_CMD8 ABI# FBx_CMD9 A12_RFU FBx_CMD10 A0_A10 FBx_CMD11 A1_A9 FBx_CMD12 RAS# FBx_CMD13 RST# FBx_CMD14 CKE# FBx_CMD15 CAS# C FBx_CMD16 CS# FBx_CMD17 A3_BA3 FBx_CMD18 A2_BA0 FBx_CMD19 A4_BA2 FBx_CMD20 A5_BA1 FBx_CMD21 WE# FBx_CMD22 A7_A8 FBx_CMD23 A6_A11 FBx_CMD24 ABI# FBx_CMD25 A12_RFU FBx_CMD26 A0_A10 FBx_CMD27 A1_A9 FBx_CMD28 RAS# FBx_CMD29 RST# FBx_CMD30 CKE# FBx_CMD31 CAS# B X76@ X76@ UV5 SIDE H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170 2 2 1 2 1 CV144 1 CV143 1 0.1U_0402_10V7K 2 CV145 1 0.1U_0402_10V7K 2 CV86 1 0.1U_0402_10V7K 2 CV85 1 1U_0603_25V6 1 CV88 1U_0603_25V6 2 CV87 CV142 CV138 CV83 CV82 CV137 2 UV6 SIDE 1U_0603_25V6 2 1 CV187 2 1 10U_0603_6.3V6M 2 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 1U_0603_25V6 1 CV81 1U_0603_25V6 2 CV84 1 1U_0603_25V6 CV179 1 1U_0603_25V6 2 0.1U_0402_10V7K A 10U_0603_6.3V6M +1.5VS_VGA 1U_0603_25V6 +1.5VS_VGA A 2 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 2 N13P_GDDR5_A Upper Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 29 of Rev 1.0 69 5 4 3 2 1 Memory Partition C - Lower 32 bits UV7 UV8 FBC_MA7_MA8_L FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L FBC_MA12_RFU_L K4 H5 H4 K5 J5 A5 U5 2 RV147 1 1K_0402_1% 2 RV149 1 2 RV151 1 1K_0402_1% 121_0402_1% Follow DG 1 RV37 <27> <27> <27> <27> <27> 2 40.2_0402_1% FBC_ABI#_L FBC_RAS#_L FBC_CS#_L FBC_CAS#_L FBC_WE#_L FBC_ABI#_L FBC_RAS#_L FBC_CS#_L FBC_CAS#_L FBC_WE#_L J4 G3 G12 L3 L12 A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# C 1 RV39 2 40.2_0402_1% 0.01U_0402_25V7K FBC_CLK0# <27> <27> FBC_WCK0_N FBC_WCK0 <27> <27> FBC_WCK1_N FBC_WCK1 CV195 1 RV155 160_0402_1% @ 1 FBC_WCK0_N FBC_WCK0 D5 D4 WCK01# WCK01 WCK23# WCK23 FBC_WCK1_N FBC_WCK1 P5 P4 WCK23# WCK23 WCK01# WCK01 +FBC_VREFD_L +FBC_VREFC0 A10 U10 J14 VREFD VREFD VREFC 2 <27> FBC_RST#_L FBC_RST#_L J2 RESET# +1.5VS_VGA 1 H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 RV159 549_0402_1% 2 RV160 1.33K_0402_1% +FBC_VREFC0 1 CV61 1 820P_0402_25V7 2 RV216 1 2 931_0402_1% 2 +1.5VS_VGA G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 B 1 +1.5VS_VGA RV161 549_0402_1% 2 RV217 S 2 1 <23,28,29,31> D 3 RV162 1.33K_0402_1% 2 G MEM_VREF 1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD CV62 820P_0402_25V7 +FBC_VREFD_L 1 1 2 931_0402_1% VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 170-BALL SGRAM GDDR5 QV13 2N7002W-T/R7_SOT323-3 X76@ 2 2 1 CV159 CV157 CV160 CV90 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 CV89 1 1U_0603_25V6 2 H5GQ1H24AFR-T2L_BGA170 CV92 1U_0603_25V6 CV91 1 1U_0603_25V6 1 CV199 2 UV7 SIDE 1U_0603_25V6 A 10U_0603_6.3V6M +1.5VS_VGA A5 U5 +1.5VS_VGA 2 RV150 1 2 RV152 1 1K_0402_1% 121_0402_1% J1 J10 J13 FBC_WCK1_N FBC_WCK1 D5 D4 FBC_WCK0_N FBC_WCK0 P5 P4 A10 U10 J14 +FBC_VREFD_L +FBC_VREFC0 FBC_RST#_L DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# MF=1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 RESET# H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS +1.5VS_VGA G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 170-BALL SGRAM GDDR5 +1.5VS_VGA 2 1 UV8 SIDE 1 2 1 2 1 2 1 2 1 2 1 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREFD VREFD VREFC J2 MF=0 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 BYTE3 D GDDR5 Mode H - Mirror Mode Mapping DATA Bus BYTE1 +1.5VS_VGA MF SEN ZQ J4 G3 G12 L3 L12 FBC_ABI#_L FBC_CAS#_L FBC_WE#_L FBC_RAS#_L FBC_CS#_L EDC3 EDC2 EDC1 EDC0 VPP/NC VPP/NC 2 RV148 1 1K_0402_1% B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 K4 H5 H4 K5 J5 FBC_MA0_MA10_L FBC_MA6_MA11_L FBC_MA7_MA8_L FBC_MA1_MA9_L FBC_MA12_RFU_L MF=1 EDC0 EDC1 EDC2 EDC3 CK CK# CKE# H11 K10 K11 H10 FBC_MA4_BA2_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA5_BA1_L BYTE2 D2 D13 P13 P2 J12 J11 J3 FBC_CLK0 FBC_CLK0# FBC_CKE_L FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 +1.5VS_VGA MF SEN ZQ 2 FBC_CLK0 J1 J10 J13 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC FBC_DBI1# C2 C13 R13 R2 B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 Address 0..31 FBx_CMD0 CS# FBx_CMD1 A3_BA3 FBx_CMD2 A2_BA0 FBx_CMD3 A4_BA2 FBx_CMD4 A5_BA1 FBx_CMD5 WE# FBx_CMD6 A7_A8 FBx_CMD7 A6_A11 FBx_CMD8 ABI# FBx_CMD9 A12_RFU FBx_CMD10 A0_A10 FBx_CMD11 A1_A9 FBx_CMD12 RAS# FBx_CMD13 RST# FBx_CMD14 CKE# FBx_CMD15 CAS# 32..63 C FBx_CMD16 CS# FBx_CMD17 A3_BA3 FBx_CMD18 A2_BA0 FBx_CMD19 A4_BA2 FBx_CMD20 A5_BA1 FBx_CMD21 WE# FBx_CMD22 A7_A8 FBx_CMD23 A6_A11 FBx_CMD24 ABI# FBx_CMD25 A12_RFU FBx_CMD26 A0_A10 FBx_CMD27 A1_A9 FBx_CMD28 RAS# FBx_CMD29 RST# FBx_CMD30 CKE# FBx_CMD31 CAS# B X76@ 1 CV162 FBC_MA7_MA8_L FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L FBC_MA12_RFU_L BA2/A4 BA3/A3 BA0/A2 BA1/A5 FBC_DBI1# CV161 <27> <27> <27> <27> <27> BA0/A2 BA1/A5 BA2/A4 BA3/A3 <27> FBC_DBI3# 0.1U_0402_10V7K FBC_MA2_BA0_L FBC_MA5_BA1_L FBC_MA4_BA2_L FBC_MA3_BA3_L H11 K10 K11 H10 CK CK# CKE# FBC_DBI3# CV163 <27> <27> <27> <27> FBC_MA2_BA0_L FBC_MA5_BA1_L FBC_MA4_BA2_L FBC_MA3_BA3_L J12 J11 J3 <27> 0.1U_0402_10V7K FBC_CLK0 FBC_CLK0# FBC_CKE_L FBC_CLK0 FBC_CLK0# FBC_CKE_L DBI3# DBI2# DBI1# DBI0# FBC_EDC1 BYTE0 CV94 FBC_DBI2# DBI0# DBI1# DBI2# DBI3# FBC_EDC3 0.1U_0402_10V7K FBC_DBI2# D2 D13 P13 P2 FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 CV93 <27> FBC_DBI0# MF=0 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 1U_0603_25V6 FBC_DBI0# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CV96 1U_0603_25V6 <27> <27> <27> <27> DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CV95 FBC_EDC[3..0] D EDC3 EDC2 EDC1 EDC0 1U_0603_25V6 <27> FBC_EDC2 FBC_D[0..31] EDC0 EDC1 EDC2 EDC3 MF=0 CV207 <27> C2 C13 R13 R2 MF=1 1U_0603_25V6 FBC_EDC0 MF=1 10U_0603_6.3V6M MF=0 H5GQ1H24AFR-T2L_BGA170 2 A 2 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_C Lower THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 30 of Rev 1.0 69 5 4 3 2 1 Memory Partition C - Upper 32 bits UV9 FBC_MA7_MA8_H FBC_MA1_MA9_H FBC_MA0_MA10_H FBC_MA6_MA11_H FBC_MA12_RFU_H FBC_MA7_MA8_H FBC_MA1_MA9_H FBC_MA0_MA10_H FBC_MA6_MA11_H FBC_MA12_RFU_H H11 K10 K11 H10 K4 H5 H4 K5 J5 A5 U5 2 RV163 1 1K_0402_1% 2 RV165 1 2 RV167 1 1K_0402_1% 121_0402_1% Follow DG 1 RV41 2 40.2_0402_1% FBC_ABI#_H FBC_RAS#_H FBC_CS#_H FBC_CAS#_H FBC_WE#_H FBC_ABI#_H FBC_RAS#_H FBC_CS#_H FBC_CAS#_H FBC_WE#_H J4 G3 G12 L3 L12 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC RV171 160_0402_1% @ 1 RV48 2 40.2_0402_1% 0.01U_0402_25V7K FBC_CLK1# <27> <27> 1 FBC_WCK2_N FBC_WCK2 D5 D4 FBC_WCK3_N FBC_WCK3 P5 P4 +FBC_VREFD_H A10 U10 J14 FBC_WCK2_N FBC_WCK2 <27> <27> FBC_WCK3_N FBC_WCK3 CV215 1 C +FBC_VREFC1 ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC 2 <27> FBC_RST#_H FBC_RST#_H J2 RESET# +1.5VS_VGA 1 H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 RV175 549_0402_1% 2 RV176 1.33K_0402_1% +FBC_VREFC1 1 CV63 1 820P_0402_25V7 2 RV218 1 2 931_0402_1% 2 +1.5VS_VGA G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 B 1 +1.5VS_VGA RV177 549_0402_1% 2 RV219 S 2 1 <23,28,29,30> D 3 RV178 1.33K_0402_1% 2 G MEM_VREF 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD CV64 820P_0402_25V7 +FBC_VREFD_H 1 1 2 931_0402_1% 2 170-BALL QV15 2N7002W-T/R7_SOT323-3 SGRAM GDDR5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 2 J12 J11 J3 H11 K10 K11 H10 FBC_MA0_MA10_H FBC_MA6_MA11_H FBC_MA7_MA8_H FBC_MA1_MA9_H FBC_MA12_RFU_H K4 H5 H4 K5 J5 A5 U5 +1.5VS_VGA 2 RV164 1 1K_0402_1% B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 J1 J10 J13 2 RV166 1 2 RV168 1 1K_0402_1% 121_0402_1% J4 G3 G12 L3 L12 FBC_ABI#_H FBC_CAS#_H FBC_WE#_H FBC_RAS#_H FBC_CS#_H FBC_WCK3_N FBC_WCK3 D5 D4 FBC_WCK2_N FBC_WCK2 P5 P4 A10 U10 J14 +FBC_VREFD_H +FBC_VREFC1 J2 FBC_RST#_H H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 +1.5VS_VGA G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14 MF=1 EDC0 EDC1 EDC2 EDC3 EDC3 EDC2 EDC1 EDC0 DBI0# DBI1# DBI2# DBI3# DBI3# DBI2# DBI1# DBI0# CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3 BA2/A4 BA3/A3 BA0/A2 BA1/A5 A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC A10/A0 A11/A6 A8/A7 A9/A1 VPP/NC VPP/NC MF=1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 2 ABI# RAS# CS# CAS# WE# CAS# WE# RAS# CS# WCK01# WCK01 WCK23# WCK23 WCK23# WCK23 WCK01# WCK01 VREFD VREFD VREFC RESET# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 1 UV10 SIDE 1 2 1 2 1 2 1 2 1 2 1 2 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 170-BALL +1.5VS_VGA MF=0 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 BYTE7 GDDR5 Mode H - Mirror Mode Mapping BYTE5 B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14 Address 0..31 FBx_CMD0 CS# FBx_CMD1 A3_BA3 FBx_CMD2 A2_BA0 FBx_CMD3 A4_BA2 FBx_CMD4 A5_BA1 FBx_CMD5 WE# FBx_CMD6 A7_A8 FBx_CMD7 A6_A11 FBx_CMD8 ABI# FBx_CMD9 A12_RFU FBx_CMD10 A0_A10 FBx_CMD11 A1_A9 FBx_CMD12 RAS# FBx_CMD13 RST# FBx_CMD14 CKE# FBx_CMD15 CAS# 32..63 C FBx_CMD16 CS# FBx_CMD17 A3_BA3 FBx_CMD18 A2_BA0 FBx_CMD19 A4_BA2 FBx_CMD20 A5_BA1 FBx_CMD21 WE# FBx_CMD22 A7_A8 A6_A11 FBx_CMD23 A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14 FBx_CMD24 ABI# FBx_CMD25 A12_RFU FBx_CMD26 A0_A10 FBx_CMD27 A1_A9 FBx_CMD28 RAS# FBx_CMD29 RST# FBx_CMD30 CKE# FBx_CMD31 CAS# B X76@ H5GQ1H24AFR-T2L_BGA170 2 A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_C Upper THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 D DATA Bus FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 +1.5VS_VGA MF SEN ZQ SGRAM GDDR5 CV227 CV165 CV164 CV167 CV98 1 FBC_DBI5# D2 D13 P13 P2 FBC_MA4_BA2_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA5_BA1_H BYTE6 10U_0603_6.3V6M 2 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 0.1U_0402_10V7K 2 1 CV97 1 1U_0603_25V6 H5GQ1H24AFR-T2L_BGA170 CV100 1U_0603_25V6 2 CV99 CV245 1 1U_0603_25V6 1 UV9 SIDE 1U_0603_25V6 10U_0603_6.3V6M A 2 FBC_DBI5# FBC_DBI7# FBC_CLK1 FBC_CLK1# FBC_CKE_H FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 X76@ +1.5VS_VGA <27> +1.5VS_VGA MF SEN ZQ 2 FBC_CLK1 <27> <27> <27> <27> <27> J1 J10 J13 BA0/A2 BA1/A5 BA2/A4 BA3/A3 FBC_DBI7# C2 C13 R13 R2 CV169 <27> <27> <27> <27> <27> FBC_MA2_BA0_H FBC_MA5_BA1_H FBC_MA4_BA2_H FBC_MA3_BA3_H CK CK# CKE# <27> CV168 FBC_MA2_BA0_H FBC_MA5_BA1_H FBC_MA4_BA2_H FBC_MA3_BA3_H DBI3# DBI2# DBI1# DBI0# 0.1U_0402_10V7K <27> <27> <27> <27> J12 J11 J3 DBI0# DBI1# DBI2# DBI3# CV170 FBC_CLK1 FBC_CLK1# FBC_CKE_H FBC_CLK1 FBC_CLK1# FBC_CKE_H D2 D13 P13 P2 FBC_EDC5 CV102 <27> <27> <27> FBC_DBI6# MF=0 FBC_EDC7 BYTE4 0.1U_0402_10V7K FBC_DBI4# FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 CV101 FBC_DBI6# UV10 A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2 1U_0603_25V6 FBC_DBI4# <27> DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CV104 1U_0603_25V6 <27> EDC3 EDC2 EDC1 EDC0 MF=0 CV103 FBC_EDC[7..4] D EDC0 EDC1 EDC2 EDC3 MF=1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 1U_0603_25V6 <27> FBC_EDC6 FBC_D[63..32] MF=1 1U_0603_25V6 <27> C2 C13 R13 R2 0.1U_0402_10V7K MF=0 FBC_EDC4 2 1 Sheet 31 of Rev 1.0 69 5 4 3 2 1 B+_SLI follow MXM 3.0 spec JSLI1 D D PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P9 C PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P8 PCIE_CRX_GTX_N15 PCIE_CRX_GTX_P15 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV20 CV22 PCIE_CRX_C_GTX_N15 PCIE_CRX_C_GTX_P15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P14 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV16 CV18 PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P13 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV19 CV14 PCIE_CRX_C_GTX_N13 PCIE_CRX_C_GTX_P13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P12 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV15 CV17 PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P11 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV12 CV13 PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P10 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV10 CV11 PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P9 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV8 CV9 PCIE_CRX_C_GTX_N9 PCIE_CRX_C_GTX_P9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P8 0.22U_0402_10V6K 0.22U_0402_10V6K 2 2 1 1 CV6 CV7 PCIE_CRX_C_GTX_N8 PCIE_CRX_C_GTX_P8 B 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 GND NC NC NC NC NC NC NC GND PEG_RX_N7 PEG_RX_P7 GND GND GND GND +19V +19V +19V +19V +19V +19V +19V GND PEG_RX_N6 PEG_RX_P6 GND GND PEG_RX_N5 PEG_RX_P5 GND PEG_RX_N4 PEG_RX_P4 GND PEG_RX_N3 PEG_RX_P3 GND PEG_RX_N2 PEG_RX_P2 +19V GND GND GND GND GND GND +5V +5V +5V +5V +5V GND GND GND GND PEG_RX_N1 PEG_RX_P1 GND PEG_RX_N0 PEG_RX_P0 GND GND PEG_TX_N7 PEG_TX_P7 GND PEG_TX_N6 PEG_TX_P6 GND PEG_TX_N5 PEG_TX_P5 GND PEG_TX_N4 PEG_TX_P4 GND PEG_TX_N3 PEG_TX_P3 GND PEG_TX_N2 PEG_TX_P2 GND PEG_TX_N1 PEG_TX_P1 GND PEG_TX_N0 PEG_TX_P0 GND NC +3V +3V GND NC NC NC NC NC NC TH_TACH TH_PWN NC PEX_STD_SW# AC_DC PWR_GOOD PWR_EN CLK_REQ# RSVD RSVD NC TH_OVERT# NC RSVD SMB_DAT SMB_CLK WAKE# RSVD RSVD GND CLK_PCIE_N CLK_PCIE_P GND GND GND TE_2199022-1_118P-T 11/11 for 2nd VGA fan need to notic EC <23,5> PCIE_CTX_C_GRX_N[0..15] <23,5> PCIE_CTX_C_GRX_P[0..15] <23,5> PCIE_CRX_GTX_N[0..15] <23,5> PCIE_CRX_GTX_P[0..15] GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +5VS_SLI +3VS_SLI 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 +3VS C SLI_B+_ON# SLI_5V_ON# SUSP# SLI_B+_ON# <56> SLI_5V_ON# <56> SUSP# <46,55,60,61,62> SLI_FAN_SPEED SLI_FAN_PWM VGA_AC_DET_R S_DGPU_PWROK S_DGPU_PWR_EN# CLK2_REQ_GPU#_R S_NVDD_PWR_EN S_DGPU_RST PCH_THRMTRIP#_R PLT_RST# GC6_EVENT_SLI# EC_SMB_DA2 EC_SMB_CK2 GC6_SLI_EN S_DGPU_PWR_EN CLK_PCIE_2VGA# CLK_PCIE_2VGA SLI_FAN_SPEED SLI_FAN_PWM <44,46> <44,46> VGA_AC_DET_R <23> S_DGPU_PWROK <16,54> S_DGPU_PWR_EN# <55> CLK2_REQ_GPU#_R <16> S_NVDD_PWR_EN <19,54> S_DGPU_RST <16,54> SLAVE_PRESENT# PCH_THRMTRIP#_R <19,23> PLT_RST# <14,23,40,41,46> EC_SMB_DA2 EC_SMB_CK2 RV158 1 @ 2 0_0402_5% <19> S_GC6_EVENT# <54> <17,23,34,36,43,46> <17,23,34,36,43,46> S_DGPU_PWR_EN CLK_PCIE_2VGA# CLK_PCIE_2VGA <19,54,55> <16> <16> B 120 122 RV234 1 2 0_0402_5% RV173 1 @ 2 0_0402_5% S_GC6_EN @ <27,54> ME@ PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_P[0..15] PCIE_CRX_GTX_N[0..15] PCIE_CRX_GTX_P[0..15] A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 2 VGA MXM 2014/07/01 Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 32 of Rev 1.0 69 5 4 3 2 2 RV122 20K_0402_1% @ 1 1 RV121 4.99K_0402_1% 1 RV94 30K_0402_1% GT1@ RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE STRAP0 +3VS_VGA USER[3] USER[2] USER[1] STRAP1 +3VS_VGA STRAP2 +3VS_VGA PCI_DEVID[3] STRAP3 +3VS_VGA SOR3_EXPOSED STRAP4 +3VS_VGA Power Rail PCI_DEVID[2] RESERVED Pull-down to Gnd 10K 1001 0001 15K 1010 0010 20K 1011 0011 25K 1100 0100 30K 1101 0101 35K 1110 0110 45K 1111 0111 5K USER[0] 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] Pull-up to +3VS_VGA 1000 Resistor Values PCI_DEVID[1] 3GIO_PAD_CFG_ADR[0] D PCI_DEVID[0] SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED PCIE_SPEED_ CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V SLOT_CLK_CFG 0000 0 GPU and MCH don't share a common reference clock 1 GPU and MCH share a common reference clock (Default) SUB_VENDOR 0 No VBIOS ROM (Default) 1 BIOS ROM is present C 3GIO_PADCFG XCLK_417 USER Straps 3GIO_PADCFG[3:0] 0 277MHz (Default) User[3:0] 1 Reserved 1000-1100 @ 2012-0418 0000 --> Set BOM structure as Stuff for ALL SKU 2 2 1 RV103 RV103 4.99K_0402_1% 1 RV102 30K_0402_1% @ 1 PEX_PLL_EN_TERM PCI_DEVID[4] +3VS_VGA 1 RV100 4.99K_0402_1% 1 1 RV99 10K_0402_1% 2 RV101 20K_0402_1% X76@ X76 SLOT_CLK_CFG +3VS_VGA RV125 45.3K_0402_1% ROM_SI ROM_SO ROM_SCLK <24> ROM_SI <24> ROM_SO <24> ROM_SCLK Logical Strapping Bit0 2 2 2 1 RV98 4.99K_0402_1% @ 1 Logical Strapping Bit1 ROM_SI +3VS_VGA C Logical Strapping Bit3 Logical Strapping Bit2 SUB_VENDOR 2 2 @ RV124 4.99K_0402_1% 1 RV97 24.9K_0402_1% GT@ 1 RV96 4.99K_0402_1% 1 1 @ RV95 45.3K_0402_1% 2 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 2 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 2 <24> <24> <24> <24> <24> RV93 @ 4.99K_0402_1% 1 1 D 2 2 2 +3VS_VGA RV92 45.3K_0402_1% 2 Physical Strapping pin ROM_SCLK Notebook Default Customer defined PEX_PLL_EN_TERM PCIE_MAX_SPEED FB_0_BAR_SIZE 0 Disable (Default) 0 Limit to PCIE Gen1 0 Reserved 1 Enable 1 PCIE Gen 2/3 Capable 1 Reserved SMBUS_ALT_ADDR VGA_DEVICE 2 256MB (Default) 0 0x9E (Default) 0 3D Device (Class Code 302h) 3 Reserved 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) GT1@ GT@ 15K_0402_1% B B X76 GPU FB Memory (GDDR5) Samsung N13P-GT1 28nm Hynix A K4G20325FD-FC04 2G 64Mx32 ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM PD 30K K4G10325FG-HC04 1G 32Mx32 PD 45K EOL H5GQ2H24MFR-T2C 2G 64Mx32 PD 25K H5GQ1H24BFR-T2C 1G 32Mx32 PD 20K H5GQ2H24AFR-T2C 2G 64Mx32 PD 25K PU 10K PD 15K (ROM not present) PD 35K (ROM present) Samsung PU 45K PD 5K PD 25K PU 5K PD 45K Hynix Issued Date 2012/07/01 Deciphered Date X76409JVL01 (2G 64Mx32) SA00005B70J X76409JVL51 (1G 32Mx16) SA00003RS0J X76409JVL02 (2G 64Mx32) SA00004GD0J X76409JVL02 (2G 64Mx32) SA00004GD1J X76409JVL52 (1G 32Mx16) SA00003WL1J 2014/07/01 Y501 NM-A032 4 3 A N13P_MISC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: 5 EOL Title LC Future Center Secret Data Security Classification VRAM P/N X76 2 Sheet 1 33 of Rev 1.0 69 5 4 3 Use BLM18KG331SN1 Use BLM18KG331SN1 +3VS +3.3VS_DTL 1 0_0402_5% BLM18PG331SN1D_2P 1 2 LT1 BLM18PG331SN1D_2P 1 VDDIO_DTL 2 1 Use BLM18KG331SN1 Close Pin14 +3.3VS_DTL LT4 2 RT1270 2 LT3 LT2 VDDIOX_DTL 1 SW_OUT 2 BLM18PG331SN1D_2P VDD12_DTL1 2 VDDRX_DTL 1.2V 2.2UH_HPC252012F-2R2M_1.3A_20% 1 1 CT5 0.47U_0402_6.3V6K D 2 1 CT6 1U_0402_6.3V6K 2 2 1 CT10 0.47U_0402_6.3V6K 2 CT13 CT8 2 2 CT7 0.01U_0402_16V7K Close Pin6 0.1U_0402_10V7K 1 VDD12_DTL 1 Close Pin19 0.01U_0402_16V7K 0.1U_0402_10V7K 1 VDDIO_DTL 1 VDDIO_DTL <38> <35> EDP_HPD INVT_PWM Close Pin38,50 0.1U_0402_10V7K C RT2 CT3 2 1 1 10K_0402_5% 2 VDDIO_DTL DTL_PD# RT1 1 1 RT14 4.99K_0402_1% 2 1 2 1 10K_0402_5% 2 VDDIO_DTL DTL_RST# RT9 VDDRX_DTL VDDIOX_DTL VDDIOX_DTL VDD12_DTL 6 13 14 19 VDDIO_DTL VDDIO_DTL 38 50 EDP_AUX# EDP_AUX 1 2 EDP_TX0+ EDP_TX0- 4 5 EDP_TX1+ EDP_TX1- 7 8 EDP_HPD 11 INVT_PWM DTL_RST# DTL_PD# 45 9 10 TL_INVPWM ENPVCC_I2C_ADDR GPIO0 RLV_CFG EN_BACKLIGHT Noe: LVDS output swing control 4.99K for default swing, change the value for swing adjust 1U_0402_6.3V6K CT1 2 B EDP_AUX#_C <38> EDP_AUX_C <38> EDP_TX0+_C <38> EDP_TX0-_C <38> EDP_TX1+_C <38> EDP_TX1-_C VDDRX VDDIOX VDDIOX VDD12 26 27 20 SW_OUT SW_OUT 15 16 EDP_AUX#_C EDP_AUX# EDP_AUX_C CT18 2 0.1U_0402_10V7K 1 EDP_AUX EDP_TX0+_C CT19 2 0.1U_0402_10V7K 1 EDP_TX0+ TB0p TB0n TC0p TC0n TCK0p TCK0n TD0p TD0n DRX0p DRX0n TA1p TA1n DRX1p DRX1n TB1p TB1n HPD PWMI RST# PD# TC1p TC1n TCK1p TCK1n PWMO ENPVCC RLV_LNK/GPIO0 RLV_CFG ENBLT TD1p TD1n DDC_SDA DDC_SCL CSDA/MSDA CSCL/MSCL REXT RLV_AMP TESTMODE GNDX GNDX GND GND SW_OUT SW_OUT 55 56 0.1U_0402_10V7K 1 PS8625 DAUXn DAUXp 4.99K_0402_1% CT17 2 TA0p TA0n VDDIO VDDIO 12 33 21 22 23 REXT RLV_AMP 2.2U_0402_6.3V6M <38> CT9 1U_0402_6.3V6K D 53 54 LVDS_A0_NVS LVDS_A0#_NVS 51 52 LVDS_A1_NVS LVDS_A1#_NVS 48 49 LVDS_A2_NVS LVDS_A2#_NVS 46 47 LVDS_ACLK_NVS LVDS_ACLK#_NVS LVDS_A0_NVS LVDS_A0#_NVS <35> <35> LVDS_A1_NVS LVDS_A1#_NVS <35> <35> LVDS_A2_NVS LVDS_A2#_NVS <35> <35> LVDS_ACLK_NVS LVDS_ACLK#_NVS <35> <35> 43 44 41 42 LVDS_B0_NVS LVDS_B0#_NVS 39 40 LVDS_B1_NVS LVDS_B1#_NVS 36 37 LVDS_B2_NVS LVDS_B2#_NVS 34 35 LVDS_BCLK_NVS LVDS_BCLK#_NVS EDP_AUX#_C 0.1U_0402_10V7K CT30 1 2 EDP@ EDP_AUX#_CON EDP_AUX_C 0.1U_0402_10V7K CT31 1 2 EDP@ EDP_AUX_CON EDP_TX0+_C 0.1U_0402_10V7K CT32 1 2 EDP@ EDP_TX0+_CON <35> <35> EDP_TX0-_C 0.1U_0402_10V7K CT33 1 2 EDP@ EDP_TX0-_CON LVDS_B1_NVS LVDS_B1#_NVS <35> <35> EDP_TX1+_C 0.1U_0402_10V7K CT34 1 2 EDP@ EDP_TX1+_CON LVDS_B2_NVS LVDS_B2#_NVS <35> <35> 0.1U_0402_10V7K CT35 1 2 EDP@ EDP_TX1-_C EDP_TX1-_CON 30 29 24 25 EDP_TX0-_C EDP_TX1+_C 17 18 28 3 EDP_TX1-_C EDP_HPD RT1268 <35> EDP_TX1+_CON <35> EDP_TX1-_CON <35> C +3.3VS_DTL RT12 2K_0402_5% 57 RT13 2K_0402_5% EDID_DAT_CON EDID_CLK_CON EDP_TX0- <35> EDP_TX0-_CON EDID_DAT_CON EDID_CLK_CON CSDA/MSDA CSCL/MSCL EDID_DAT_CON EDID_CLK_CON ENPVCC_I2C_ADDR 0.1U_0402_10V7K 1 0.1U_0402_10V7K 1 0.1U_0402_10V7K 1 <35> EDP_TX0+_CON Close to JLVDS1 <35> <35> PS8625QFN56GTR-A0_QFN56_7X7 CT16 2 CT15 2 CT14 2 <35> 31 32 NC NC Epad EDP_AUX_CON LVDS_B0_NVS LVDS_B0#_NVS LVDS_BCLK_NVS LVDS_BCLK#_NVS EDP_AUX#_CON 1 2 VDDRX_DTL 1 1 CT22 2 2 2 CT11 1 CT2 4.7U_0603_6.3V6K UT3 0.1U_0402_10V7K 1 2 2 2 GND of 4.7uF capacitor behind Inductor. Close Pin12,13 CT12 2 1 Use 2.2uH 800mA CT4 4.7U_0603_6.3V6K 1 EDP@ 2 0_0402_5% EDP_HPD_CON EDP_HPD_CON EN_BACKLIGHT <35> EDP_TX1+ <35> <35> ENPVCC_I2C_ADDR EN_BACKLIGHT TL_INVPWM TL_INVPWM To LVDS panel <35> <35> <35> EDP_TX1B Close to UT3 Power On Configuration Initial Code EEPROM 1 VDDIO_DTL +3.3VS_DTL 1 RLV_CFG RC RT3 4.7K_0402_5% DAUL@ RT8 @ 1 4.7K_0402_5% 2 CSCL/MSCL RT10 4.7K_0402_5% RT7 @ 1 RD 4.7K_0402_5% 2 CSDA/MSDA RT15 4.7K_0402_5% @ ENPVCC_I2C_ADDR GPIO0 GPIO0: LVDS single link or dual link selection, internal pull-down ~80K 2 RB 2 2 1 2 @ VDDIO_DTL 1 VDDIO_DTL RT6 4.7K_0402_5% RA +3.3VS_DTL @ Default Default * RLV_CFG H:6-bit both VESA and JEIDA mapping M:8-bit JEIDA mapping RA Stuff NA NA L:8-bit VESA mapping A RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K RB NA * ENPVCC_I2C_ADDR H:0x90h~0x9Fh RC Stuff L:0x10h~0x1Fh NA Default * GPIO0 Single channel Daul channel RD NA <17,23,32,36,43,46> <17,23,32,36,43,46> Stuff EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2 RT1272 EC_SMB_DA2 RT1271 1 1 GPIO0 CSCL/MSCL CSDA/MSDA 2 0_0402_5% 2 0_0402_5% 8 7 6 5 VCC WP SCL SDA UT2 1 2 3 4 A0 A1 A2 GND M24C08-WMN6TP_SO8 Stuff I2C_CFG = "H" EEPROM for Initial Code I2C Address: 0xA0 Suggest minimum 8Kbit NA I2C_ADDR: I2C Slave address selection, internal pull-down ~80K Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date A LVDS/ CMOS/ USB-ReDriver THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 34 of Rev 1.0 69 5 4 3 2 1 JLVDS1 ME@ EDP_AUX#_CON EDP_AUX_CON +CMOS_PW CMOS Camera <34> <34> Q94 EDP_TX0+_CON EDP_TX0-_CON EDP_TX1+_CON EDP_TX1-_CON EDP_HPD_CON <34> <34> EDP_TX1+_CON EDP_TX1-_CON EDP_HPD_CON DISPOFF# +3VS +LEDVDD (60 MIL) ACES_87142-4041-BS 2 C529 @ 1 R432 0_0603_5% 1 2 CMOS@ 1 CMOS@ C518 0.1U_0402_16V4Z 2 +CMOS_PW_R CMOS@ 1 C1051 @ 0.1U_0402_16V4Z 1 4.7K_0402_5% 2 0_0402_5% 1 +3VS BKOFF# BKOFF# R891 <46> <19> 2 0_0402_5% 1 EN_BACKLIGHT R823 1 1 R813 2 1 R_short 0_0805_5% 2 2 C58 @ C524 4.7U_0805_25V6-K 2 1 USB20_N0_CMOS 1 2 3 4 5 6 7 8 4 USB20_P0_CMOS 9 10 2 0_0402_5% 2 0_0402_5% USB20_N0_CMOS USB20_P0_CMOS USB20_N0_CMOS USB20_P0_CMOS USB20_P0 3 +3VS DMIC_CLK DMIC_DATA <45> <45> L74 2 2 1 3 4 JCMOS1 W=40mils +CMOS_PW R1166 1 R1167 1 1 0.047U_0402_16V4Z 9/23 EMI Request USB20_N0 D B+ 2A 80 mil 2A 80 mil C523 470P_0603_50V8J USB20_N0 USB20_P0 @ C520 0.1U_0402_16V4Z 2 CMOS@ +LEDVDD USB20_N0 USB20_P0 2 0.01U_0402_16V7K 2 1 <34> @ <18> <18> W=40mils 1 CMOS@ 2 R435 1 CMOS_ON# 1 @ C1052 2 100K_0402_5% 680P_0402_50V7K +LCDVDD_CON 1 @ 3 +3VS <34> <34> <34> R822 2 W=60mils (40 MIL) AO3413_SOT23-3 2 EDP_TX0+_CON EDP_TX0-_CON C519 10U_0603_6.3V6M LVDS_ACLK_NVS LVDS_ACLK#_NVS LVDS_A2_NVS LVDS_A2#_NVS LVDS_A1_NVS LVDS_A1#_NVS LVDS_A0_NVS LVDS_A0#_NVS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND1GND2 EDP_AUX#_CON EDP_AUX_CON G LVDS_ACLK_NVS LVDS_ACLK#_NVS LVDS_A2_NVS LVDS_A2#_NVS LVDS_A1_NVS LVDS_A1#_NVS LVDS_A0_NVS LVDS_A0#_NVS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 D D <34> <34> <34> <34> <34> <34> <34> <34> LVDS_BCLK_NVS LVDS_BCLK#_NVS LVDS_B2_NVS LVDS_B2#_NVS LVDS_B1_NVS LVDS_B1#_NVS LVDS_B0_NVS LVDS_B0#_NVS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 S <34> EDID_CLK_CON <34> EDID_DAT_CON <34> TL_INVPWM <34> LVDS_BCLK_NVS <34> LVDS_BCLK#_NVS <34> LVDS_B2_NVS <34> LVDS_B2#_NVS <34> LVDS_B1_NVS <34> LVDS_B1#_NVS <34> LVDS_B0_NVS <34> LVDS_B0#_NVS EDID_CLK_CON EDID_DAT_CON 1 2 3 4 5 6 7 8 GND GND WCM-2012-900T_4P ME@ @ C C LCDVDD GND 4 DIS EN 1 2 R818 VOUT 3 NCT3521U 4.7U_0603_6.3V6K 2 IN 150_0603_1% 1 1U_0402_6.3V6K C291 +LCDVDD_CON U76 5 1 CV283 +3VS 2 eDP to LVDS <34> GPU <23> R1202 1 ENPVCC_I2C_ADDR R1198 1 VGA_ENVDD 2 0_0402_5% 2 0_0402_5% @ D61 @ 2 1 <14> PCH_ENVDD 2 0_0402_5% 3 @ 2 PCH R1196 1 DAN202UT106_SC70-3 R828 100K_0402_5% B 1 B R1515 1 TL_INVPWM 2 @ 0_0402_5% <23> VGA_BL_PWM 1 2 0_0402_5% R1197 1 2 0_0402_5% R826 D60 2 1 PCH_EDP_PWM INVT_PWM INVT_PWM <34> 2 <14> 3 DAN202UT106_SC70-3 1 R829 100K_0402_5% EMI request ESD request D59 1 2 0_0402_5% 1 D62 2 1 A PCH_ENBKL 2 0_0402_5% ENBKL ENBKL 3 2 2 1@ C527 +3VS @ I/O3 I/O1 VDD GND I/O4 I/O2 1 DMIC_DATA 5 2 A 2 USB20_N0_CMOS 2 DAN202UT106_SC70-3 <46> 4 USB20_P0_CMOS DISPOFF# 6 3 DMIC_CLK AZC099-04S.R7G_SOT23-6 R827 100K_0402_5% 1 <14> 1 R1212 C525 1@ 470P_0402_50V7K R834 470P_0402_50V7K VGA_ENBKL C934 <23> TL_INVPWM 100P_0402_50V8J DMIC_CLK Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS/ CMOS/ USB-ReDriver THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: LVDS LOAD SWITCH 1.9mS Typical Rise time ,Rds_on 80m ohm 5 Title LC Future Center Secret Data Security Classification Y501 NM-A032 4 3 2 1 Sheet 35 of Rev 1.0 69 A B C D E CRT Connector +CRT_VCC +5VS D36 2 +CRT_VCC_CON F1 1 1 RB491D_SC59-3 2 +CRT_VCC_CON 1 0.5A_8V_KMC3S050RY W=40mils 1 <14> C536 0.1U_0402_16V4Z 2 1 CRT_DET# JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_DET# <37> DAC_RED_1 <37> DAC_GRN_1 <37> DAC_BLU_1 1 1 R830 150_0402_1% R831 150_0402_1% 2 2 1 From CRT SW 2 1 R832 150_0402_1% 1 2 NBQ100505T-800Y_0402 CRT_R_CON L17 1 2 NBQ100505T-800Y_0402 CRT_DDC_DAT_CON CRT_G_CON L18 1 2 NBQ100505T-800Y_0402 HSYNC_CON CRT_B_CON 1 C537 1 C538 2 2 10P_0402_50V8J CLOSE TO CONN L16 2 1 C539 10P_0402_50V8J 10P_0402_50V8J 1 C540 2 VSYNC_CON 1 C542 2 2 C541 10P_0402_50V8J CRT_DDC_CLK_CON 1 10P_0402_50V8J10P_0402_50V8J 2 G G 16 17 C543 SUYIN_070546HR015M22BZR 100P_0402_50V8J ME@ 2 2 +CRT_VCC R833 1 2 1 OE# 1K_0402_5% C544 0.1U_0402_16V4Z 5 P A OE# 2 HSYNC_G R840 4 CRT_HSYNC_1 Y NBQ100505T-800Y_0402 1 2 CRT_HSYNC_2 1 3 2 1 2 +CRT_VCC From CRT SW HSYNC_CON L19 33_0603_5% U24 SN74AHCT1G125DCKR_SC70-5 G <37> 1 2 @ C545 10P_0402_50V8J D7 CRT_R_CON 3 2 1 CRT_DET# 5 P 2 A 3 +3VS R839 4 CRT_VSYNC_1 1 Y 2 CRT_VSYNC_2 1 1 2 2 2 0_0402_5% I/O3 5 +CRT_VCC_CON 4 DDC_DAT_R 3 4 CRT_B_CON 3 VSYNC_CON 3 @ C547 10P_0402_50V8J @ I/O2 I/O4 GND VDD I/O1 I/O3 6 HSYNC_CON 5 +CRT_VCC_CON 1 CRT_DDC_CLK_CON 1 R838 2.2K_0402_5% 2 R1189 1 R837 2.2K_0402_5% 2 1 5 G CRT_DDC_DATA_R I/O1 D31 1 2 4 CRT_DDC_DAT_CON AZC099-04S.R7G_SOT23-6 CRT_DDC_DAT_CON D G 2 S CRT_DDC_DATA_R VDD CRT_G_CON VSYNC_CON L20 +CRT_VCC <37> GND 6 AZC099-04S.R7G_SOT23-6 NBQ100505T-800Y_0402 33_0603_5% U25 SN74AHCT1G125DCKR_SC70-5 G VSYNC_G 1 2 OE# <37> I/O4 OE# C546 0.1U_0402_16V4Z 3 @ I/O2 From SW <37> CRT_DDC_CLK_R CRT_DDC_CLK_R R1190 1 2 0_0402_5% EC_SMB_DA2 EC_SMB_DA2 R1191 1 2 0_0402_5% DDC_CLK_R 1 6 <17,23,32,34,43,46> EC_SMB_CK2 4 @ EC_SMB_CK2 R1192 1 CRT_DDC_CLK_CON D S <17,23,32,34,43,46> Q73B 2N7002KDW H_SOT363-6 Q73A 2N7002KDW H_SOT363-6 @ C548 100P_0402_50V8J 2 0_0402_5% 1 1 2 2 @ C549 68P_0402_50V8K @ 4 Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. A B C CRT Connector 2014/07/01 D Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 Sheet E 36 of Rev 1.0 69 2 1 +3VS +3VS_HDSW 0_0402_5% 2 1 RM25 RA +3VS_HDSW CM2 1 4.7U_0603_6.3V6K 2 CM3 1 0.01U_0402_16V7K 2 1 RB RM13 @ 2 4.7K_0402_5% 1 1 4.7K_0402_5% SEL +3VS_HDSW VDD VDD <8> <8> <8> <8> <8> <8> <8> <8> CM4 CM5 CM6 CM7 CM8 CM9 CM10 CM11 CPU_HDMI_TX0CPU_HDMI_TX0+ CPU_HDMI_TX1CPU_HDMI_TX1+ CPU_HDMI_TX2CPU_HDMI_TX2+ CPU_HDMI_CLKCPU_HDMI_CLK+ 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 CPU_HDMI_TX0-_C CPU_HDMI_TX0+_C CPU_HDMI_TX1-_C CPU_HDMI_TX1+_C CPU_HDMI_TX2-_C CPU_HDMI_TX2+_C CPU_HDMI_CLK-_C CPU_HDMI_CLK+_C 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 44 45 47 48 1 2 4 5 PWDN_ASQ IN1_D1n IN1_D1p IN1_D2n IN1_D2p IN1_D3n IN1_D3p IN1_D4n IN1_D4p CFG_HPD DDCBUF PRE_EMI RTERM 6 31 25 PWDN_ASQ 28 CFG_HPD 40 34 7 DDC_BUF PRE_EMI * CM12 CM13 CM14 CM15 CM16 CM17 CM18 CM19 GPU_HDMI_TX0GPU_HDMI_TX0+ GPU_HDMI_TX1GPU_HDMI_TX1+ GPU_HDMI_TX2GPU_HDMI_TX2+ GPU_HDMI_CLKGPU_HDMI_CLK+ 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K <14> <23,39> TMDS_B_HPD DGPU_HDMI_HPD <14> DDPB_CLK <14> DDPB_DATA <24> GPU_HDMI_CLK <24> GPU_HDMI_DATA <19> <19> GPU_HDMI_TX0-_C GPU_HDMI_TX0+_C GPU_HDMI_TX1-_C GPU_HDMI_TX1+_C GPU_HDMI_TX2-_C GPU_HDMI_TX2+_C GPU_HDMI_CLK-_C GPU_HDMI_CLK+_C 46 10 41 42 19 20 DDPB_CLK DDPB_DATA HDSW_DDC HDSW_MAIN HDSW_DDC HDSW_MAIN IN1_PEQ IN2_PEQ 8 9 11 12 13 14 16 17 22 21 3 15 Stuff NA NA RG RH RM19 @ 1 2 RM20 @ 1 2 SEL OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p 36 35 33 32 30 29 27 26 VGA_HDMI_TX0VGA_HDMI_TX0+ VGA_HDMI_TX1VGA_HDMI_TX1+ VGA_HDMI_TX2VGA_HDMI_TX2+ VGA_HDMI_CLKVGA_HDMI_CLK+ VGA_HDMI_TX0VGA_HDMI_TX0+ VGA_HDMI_TX1VGA_HDMI_TX1+ VGA_HDMI_TX2VGA_HDMI_TX2+ VGA_HDMI_CLKVGA_HDMI_CLK+ 1 RM26 430_0402_1% 2 2 18 43 49 <39> <39> <39> <39> <39> <39> <39> * <39> 4.7K_0402_5% 2 HDSW_DDC RM28 1 4.7K_0402_5% 2 HDSW_MAIN RM29 1 2.2K_0402_5% 2 DDPB_CLK RM30 1 2.2K_0402_5% 2 DDPB_DATA SW Input OUT_HPD OUT_SCL OUT_SDA 39 38 37 HDMI_CONN_HPD VGA_HDMI_CLK VGA_HDMI_DATA HDMI_CONN_HPD VGA_HDMI_CLK VGA_HDMI_DATA IN1---CPU IN2---GPU L=IN1 H=IN2 RD RE RF NA Stuff NA NA Stuff NA Stuff NA NA NA NA IN1_PEQ/IN2_PEQ: Rx Equalization Setting for port1/port2.Internal pull-down ~500K ohm RI RJ RM21 @ 1 2 RM22 @ 1 2 +3VS_HDSW 4.7K_0402_5% B 4.7K_0402_5% CFG_HPD RG RH Stuff NA SEL M: No pre-emphasis, EMI control selected NA Stuff L: No pre-emphasis, no EMI control NA NA CFG_HPD H: IN1_HPD=OUT_HPD SW_DDC=L/ IN2_HPD=OUT_HPD SW_DDC=H IN1_HPD=LOW otherwise / IN2_HPD=LOW otherwise RJ NA NA Stuff NA NA L: IN1_HPD=OUT_HPD when SW_MAIN=L / IN2_HPD=OUT_HPD when SW_MAIN=H otherwise / otherwise * IN1_HPD=LOW IN2_HPD=LOW <39> <39> <39> +3VS_HDSW SEL +3VS GND GND PAD 1 RM33 RI Stuff M: IN1_HPD=OUT_HPD when SW_DDC=L or SW_MAIN=L / IN2_HPD=OUT_HPD when SW_DDC=H or SW_MAIN=H IN1_HPD=LOW otherwise / IN2_HPD=LOW otherwise RK RM23 @ 2 4.7K_0402_5% RM1 0_0402_5% RL 1 RM24 @ 2 4.7K_0402_5% PWDN_ASQ H: power down * Channel B --> PCH RG RH Stuff NA NA NA L: Normal operation PWDN_ASQ: Power down control. Internal pull-down ~500K 2 2 HDSW_DDC 0_0402_5% Output SW_MAIN 4.7K_0402_5% PWDN_ASQ CEXT REXT A L=IN1 H=IN2 L: Middle level receiving equalization selection IN1_PEQ IN2_PEQ Channel A --> GPU IN1---CPU IN2---GPU * 1 For PS8271: R35/R36 NC For PS8272: R35/R36 NC, pin21/pin22 NC or SW_MAIN/SW_DDC driven to LOW For PS8273: R35/R36 stuff or SW_MAIN/SW_DDC driven to HIGH SW_DDC RC IN1_PEQ/IN2_PEQ H: High level receiving equalization selection Stuff 4.7K_0402_5% PRE_EMI H: Pre-emphasis added, no EMI control 1 2 CM1183 RM27 1 4.7K_0402_5% RM17 @ 2 CFG_HPD: HPD switching configuration. Internal pull-down ~500K 1U_0603_10V6K HDSW_MAIN 1 IN2_PEQ M: Low level receiving equalization selection PRE_EMI: TMDS output drive pre-emphasis and EMI setting, Internal pull-down ~500K ohm PS8271QFN48GTR-A1_QFN48_7X7 +3VS_HDSW RF RM18 @ 2 1 CM1 2.2U_0603_6.3V6K 1 4.7K_0402_5% SEL NA RE +3VS_HDSW RM16 @ 2 PRE_EMI IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA SW_DDC SW_MAIN NA DDCBUF DDC_BUF_EN = L: No DDC active buffer, passive DDC level shifting 1 23 24 IN2_D1n IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p RB Stuff L: No DDC active buffer, passive DDC level shifting 4.7K_0402_5% <24> <24> <24> <24> <24> <24> <24> <24> RA M:Active DDC buffer enable, setting 2 B 1 IN1_PEQ DDC_BUF H:Active DDC buffer enable, setting 1 +3VS_HDSW RD RM15 @ 2 4.7K_0402_5% DDC_BUF UHM1 RC +3VS_HDSW RM14 @ 2 UM1 4 16 23 29 32 27 25 22 20 18 12 14 <23> VGA_CRT_R <23> VGA_CRT_G <23> VGA_CRT_B <23> VGA_CRT_CLK <23> VGA_CRT_DATA <23> VGA_CRT_HSYNC <23> VGA_CRT_VSYNC 26 24 21 19 17 13 15 <14> PCH_CRT_R <14> PCH_CRT_G <14> PCH_CRT_B <14> PCH_CRT_DDC_CLK <14> PCH_CRT_DDC_DAT <14> PCH_CRT_HSYNC <14> PCH_CRT_VSYNC VDD VDD VDD VDD VDD A0 A1 A2 A3 A4 0B1 1B1 2B1 3B1 4B1 5B1 6B1 0B2 1B2 2B2 3B2 4B2 5B2 6B2 SEL1 A5 A6 SEL2 GND GND GND GND GPAD 1 2 5 6 7 8 DAC_RED_1 <36> DAC_GRN_1 <36> DAC_BLU_1 <36> CRT_DDC_CLK_R <36> CRT_DDC_DATA_R <36> CRT_SWITCH_1 CRT_SWITCH_1 9 10 30 HSYNC_G VSYNC_G <13> <36> <36> CRT_SWITCH_1 For reserved CRT SW 3 11 28 31 33 A PI3V712-AZLEX_TQFN32_6X3 Input SELx Input/Output An Function L nB1--GPU An=nB1 H nB2---PCH An=nB2 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date HDMI and CRT SW 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 2 1 Sheet 37 of Rev 1.0 69 5 4 3 2 1 D D 1 +3VS 2 RM2 0_0402_5% <8> <8> <8> C CPU_EDP_AUX CPU_EDP_AUX# CPU_EDP_HPD <24> <24> <24> <24> VGA_EDP_TX0+ VGA_EDP_TX0VGA_EDP_TX1+ VGA_EDP_TX1- <24> <24> <23> VGA_EDP_AUX VGA_EDP_AUX# VGA_EDP_HPD CPU_EDP_TX0+ CPU_EDP_TX0CPU_EDP_TX1+ CPU_EDP_TX1- 31 30 27 26 CPU_EDP_AUX CPU_EDP_AUX# 19 18 17 25 24 23 22 15 14 13 21 28 33 D0+A D0-A D1+A D1-A VDD VDD VDD VDD VDD VDD AUX+A AUX-A HPD_A D0+ D0D1+ D1- D0+B D0-B D1+B D1-B AUX+ AUXHPD AUX+B AUX-B HPD_B GND GND GPAD SEL OE# AUX_SEL 3 9 12 16 20 29 1 2 CM1184 CPU_EDP_TX0+ CPU_EDP_TX0CPU_EDP_TX1+ CPU_EDP_TX1- 1U_0603_10V6K U79 <8> <8> <8> <8> 1 2 4 5 EDP_TX0+_C EDP_TX0-_C EDP_TX1+_C EDP_TX1-_C 6 7 8 C <34> <34> <34> <34> EDP_AUX_C <34> EDP_AUX#_C <34> EDP_HPD <34> 10 11 32 EDP_SEL <15> EDP_AUX_SEL <16> PI3VDP3212ZLEX_TQFN32_6X3 OE# L L L L H B SEL L L H H X AUX_SEL FUNCTION L PORT A H PORT A-HS, PORT B-HPD/AUX L PORT B-HS, PORT A-HPD/AUX H PORT B X IC POWER DOWN B A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date LVDS/ CMOS/ USB-ReDriver THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 38 of Rev 1.0 69 5 1 L23 2 2 1 HDMI_CLK-_CON C1015 1 2 3.3P_0402_50V8C 4 1 2 @ 2 3.3P_0402_50V8C @ L24 2 1 HDMI_TX1-_CON C1019 @ 2 3.3P_0402_50V8C C659 1 @ 2200P_0402_50V7K L27 4 1 2 4 3 2 3 1 HDMI_TX2+_CON C1022 HDMI_TX2-_CON 1 C1021 W CM2012F2SF-900T04_4P @ 2 3.3P_0402_50V8C R862 1M_0402_5% G 1 Q85 3 1 D 2 S HDMI_CONN_HPD R1486 1 0_0402_5% 2N7002_SOT23 20120829 VA1 Change net name for add HDMI MUX R885 20K_0402_5% C HDMI_TX1+_CON HDMI_TX1-_CON HDMI_TX2+_CON 2 G 2 2 Q114 2N7002H 1N_SOT23-3 3 +3VS 1 @ 2 R328 100K_0402_5% 2 @ 1 HDMI_DET_R 1 L67 BLM18PG181SN1D_0603 2 1 @ R860 2.2K_0402_5% 1K_0402_5% 1 C561 0.1U_0402_16V4Z 2 R861 2.2K_0402_5% 1 @ 2 C59 220P_0402_25V8J JHDMI1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_DET VGA_HDMI_DATA VGA_HDMI_CLK S@ B +5VS_HDMI 0_0402_5% @ for NV recommend R859 DGPU_HDMI_HPD 2 +CRT_VCC_CON 1 <23,37> 1 HDMI_TX2-_CON R1499 0_0402_5% R1505 1 HDMI_TX0-_CON 1 HDMI_TX0+_CON @ <37> VGA_HDMI_CLK- VGA_HDMI_CLK- R300 1 2 0_0402_5% HDMI_CLK-_R R866 1 @ 2 0_0402_5% HDMI_CLK-_CON <37> <37> VGA_HDMI_CLK+ VGA_HDMI_TX0- VGA_HDMI_CLK+ VGA_HDMI_TX0- R301 R302 1 1 2 0_0402_5% 2 0_0402_5% HDMI_CLK+_R R865 1 @ HDMI_TX0-_R R868 1 @ 2 2 0_0402_5% 0_0402_5% HDMI_CLK+_CON HDMI_TX0-_CON <37> <37> VGA_HDMI_TX0+ VGA_HDMI_TX1- VGA_HDMI_TX0+ VGA_HDMI_TX1- R303 R304 1 1 2 0_0402_5% 2 0_0402_5% HDMI_TX0+_R R867 1 @ HDMI_TX1-_R R870 1 @ 2 2 0_0402_5% 0_0402_5% HDMI_TX0+_CON HDMI_TX1-_CON <37> <37> VGA_HDMI_TX1+ VGA_HDMI_TX2- VGA_HDMI_TX1+ VGA_HDMI_TX2- R305 R306 1 1 2 0_0402_5% 2 0_0402_5% HDMI_TX1+_R R869 1 @ HDMI_TX2-_R R872 1 @ 2 2 0_0402_5% 0_0402_5% HDMI_TX1+_CON HDMI_TX2-_CON VGA_HDMI_TX2+ VGA_HDMI_TX2+ R307 1 2 0_0402_5% HDMI_TX2+_R R871 1 @ 2 0_0402_5% HDMI_TX2+_CON <37> SA00004ZB0J C +CRT_VCC_CON R864 100K_0402_5% HDMI_CLK-_CON @ HDMI_CLK+_CON U78 @ D38 BAT54S-7-F_SOT23-3 1 R320 499_0402_1% 1 2 @ 1 2 R321 @ 499_0402_1% 1 2 R322 @ 499_0402_1% 1 2 R323 @ 499_0402_1% 1 2 R324 @ 499_0402_1% 1 2 R325 @ 499_0402_1% 1 2 R326 @ 499_0402_1% 1 2 R327 @ 499_0402_1% D 2 +5VS 2 @ <37> 2 +3VS 2 3.3P_0402_50V8C VIN HDMI_TX2-_R 1 C562 2 HDMI_TX2+_R 1 1 2 3 1 L26 VGA_HDMI_DATA GND 1 <37> 2 3.3P_0402_50V8C 2 HDMI_TX1-_R @ W CM2012F2SF-900T04_4P 3 1 HDMI_TX1+_CON 4 3 C1020 VGA_HDMI_DATA 2 4 D 2 3.3P_0402_50V8C 2 HDMI_TX1+_R @ VGA_HDMI_CLK VGA_HDMI_CLK 2 HDMI_TX0-_CON 1 C1017 <37> 1 3 3 W CM2012F2SF-900T04_4P +5VS 2 3.3P_0402_50V8C 0.1U_0402_16V4Z 4 HDMI_TX0+_CON 1 C1018 3 4 HDMI_TX0-_R 2 2 1 D 1 2 1 HDMI_TX0+_R APL3517AI-TRG_SOT23-3 HDMI_CLK-_R W CM2012F2SF-900T04_4P 1 3 HDMI_CLK+_CON 3 C1016 4 3 VOUT HDMI_CLK+_R 4 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 B TAITW _PDVBR0-19FLBS4NN4N0 ME@ Close to JHDMI1 D57 VGA_HDMI_CLK 3 2 VGA_HDMI_DATA 1 I/O2 GND I/O1 @ I/O4 VDD I/O3 6 HDMI_DET 5 4 D32 HDMI_CLK+_CON 1 1 10 9HDMI_CLK+_CON D33 HDMI_TX2-_CON 1 1 HDMI_CLK-_CON 2 2 9 8HDMI_CLK-_CON HDMI_TX2+_CON 2 2 9 8HDMI_TX2+_CON HDMI_TX0-_CON 4 4 7 7HDMI_TX0-_CON HDMI_TX1+_CON 4 4 7 7HDMI_TX1+_CON HDMI_TX0+_CON 5 5 6 6HDMI_TX0+_CON HDMI_TX1-_CON 5 5 6 6HDMI_TX1-_CON +5VS_HDMI AZC099-04S.R7G_SOT23-6 A @ 3 3 3 3 8 8 AZ1045-04F_DFN2510P10E-10-9 @ 10 9HDMI_TX2-_CON Issued Date 2012/07/01 Deciphered Date 4 3 A Title HDMI_CONN 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 HDMI+HDCP AZ1045-04F_DFN2510P10E-10-9 LC Future Center Secret Data Security Classification 46@ 2 Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 Sheet 1 39 of Rev 1.0 69 B C 9/18 JP1 Pin2,24,52 E Reserve for SW mini-pcie debug card. Series resistors closed to KBC side. contact to +3VS_WLAN for AOAC function LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB COMBT@ BT_CTRL R897 1 2 <15,19,41> PCIE_WAKE# 2 BT_DISABLE# JWLN1 PCIE_WAKE# WLAN_CLKREQ1# WLAN_CLKREQ1# <16> <16> CLK_PCIE_WLAN# CLK_PCIE_WLAN PCI_RST#_R CLK_PCI_DB COMBT@ For isolate Intel Rainbow Peak and Compal debug card. <18> <18> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 +3VS_WLAN C199 2 <46> <46> 10P_0402_50V8J PCH_BT_DISABLE# 1 COMBT@ 2 100_0402_1% R887 2 2 R888 100_0402_1% BT_CTRL BT_DISABLE# 53 S 3 5 SUSP <10,55,61> @ 1 2 1 R880 2 0_0402_5% PLT_RST# 2 @ 0_0402_5% 2 R_short 0_0402_5% 1 R881 R882 1 SMB_CLK_S3_R SMB_DATA_S3_R 1 1 R883 R884 @ C564 0.1U_0402_16V4Z 2 1 2 @ 0_0402_5% 2 @ 0_0402_5% BT on module Enable <46> 2 2 0.01U_0402_25V7K 2 1 AOAC@ 1 1 1 C1048 @ 2 2 2 AOAC@ C533 0.1U_0402_16V4Z 0.01U_0402_25V7K 1 BT on module Disable 2 C1055 0.1U_0402_16V4Z softstart (RC) will check on EVT PCB H L PCH_BT_ON# L H 2 9/18 Increase for Intel AOAC function @ C568 2 AOAC@ 1 R436 AOAC_ON# 100K_0402_5% BT_CRTL (GPIO22) C574 <13> 1 1 @ SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 10U_0805_10V6K C567 Q104 AO3413_SOT23-3 <11,12,17,47> <11,12,17,47> <18> <18> 54 2 2 JUMP_43X79 +3VALW SMB_CLK_S3 SMB_DATA_S3 WLAN&BT Combo module circuits +3VS_SSD 1 1 +3VALW +3VS_WLAN SATA_PTX_DRX_P0 1 2 0.01U_0402_16V7K R898 1 SATA_PTX_C_DRX_P0_R 0_0402_5% 2 1 0.01U_0402_16V7K R899 2 1 SATA_PTX_C_DRX_N0_R 0_0402_5% 2 C575 C566 +3VS_WLAN 1 PCH_WL_OFF# <14> PLT_RST# <14,23,32,41,46> C526 0.1U_0402_16V4Z * <16> C565 0.1U_0402_16V4Z 3 USB20_N10 USB20_P10 <13> 1 CLK_PCI_DB J8 ME@ <17,46> <17,46> <17,46> <17,46> <17,46> +3VS WL_OFF# NGFF(SSD) 0.1U_0402_16V4Z LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 +1.5VS_WLAN LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R For EC to detect debug card insert. S LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 1 R400 0_0603_5% TAITW_PFPET0-AFGLBG1ZZ4N0 1 G 4 @ GND R889 100K_0402_5% D 2N7002KDWH_SOT363-6 Q157B 2 G PCH_BT_ON# 1 <19> D Q157A 2N7002KDWH_SOT363-6 6 0_0402_5% 2 GND 2 <19> R1557 EC_TX 1 EC_RX 1 EC_TX EC_RX 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 2 2 2 2 2 G @ WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V @ @ @ @ @ @ D PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5 10_0402_5% 2 @ 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 +1.5VS 1 1 1 1 1 1 R873 R874 R875 R876 R878 R879 S <18> <18> R125 1 CLK_PCI_DB 2 2 0_0402_5% @ BT_CTRL_R 0_0402_5% R1556 1K_0402_5% For EMI 1 +1.5VS 2 LAN_WAKE# <16> 1 R1620 <41,46,55> C57 0.047U_0402_16V4Z 1 @ 1 For RF request +3VS_WLAN @ Mini-Express Card(WLAN/WiMAX) D 2 A SATA_PTX_DRX_N0 SATA_PRX_DTX_P0 R903 1 0_0402_5% C571 2 1 SATA_PRX_DTX_P0_R 2 SATA_PRX_DTX_N0 R904 1 0_0402_5% C570 2 1 SATA_PRX_DTX_N0_R 2 SSD Active:4.5W(1.5A) @ C569 SATA_ITX_DRX_N0_R 0.01U_0402_16V7K SATA_DTX_IRX_P0_R 0.01U_0402_16V7K SATA_DTX_IRX_N0_R +3VS_SSD +3VS 2 SATA_ITX_DRX_P0_R J5 1 10U_0805_10V6K ME@ 1 2 2 JUMP_43X79 @ JSSD1 For SSD use: 2 SATA_DET# 1 R896 0_0402_5% @ 4 76 PEG1 UR1 <13> <13> <13> <13> SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 7 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 0.01U_0402_16V7K SATA_PRX_DTX_P0 2 @ C572 SATA_DTX_IRX_P0 @1 1 C573 SATA_DTX_IRX_N0 SATA_PRX_DTX_N0 2 @ 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 1 2 5 4 19 17 18 3 13 21 EN A_INp A_INn B_OUTp B_OUTn A_PRE1 B_PRE1 TEST GND1 GND2 EPAD @ VDD1 VDD2 NC1 NC2 A_PRE0 B_PRE0 A_OUTp A_OUTn B_INp B_INn 1 2 @ 10 20 6 16 @ 2 1 1 1 RR2 4.7K_0402_5% @ RR3 4.7K_0402_5% 2 RR1 4.7K_0402_5% 2 2 @ 2 1 RR5 @ 4.7K_0402_5% @ R907 1 2 0_0402_5% @ +3VS 1 1 RR4 4.7K_0402_5% 2 @ 0.01U_0402_16V7K SATA_DET# RR6 4.7K_0402_5% 0.1U_0402_16V4Z <13> 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 3 +3VS CR2 SATA_ITX_DRX_N0_R SATA_ITX_DRX_P0_R 2 4 6 8 10 CR1 SATA_DTX_IRX_P0_R SATA_DTX_IRX_N0_R 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 3.3VAUX1 3.3VAUX2 FULL_CARD_POWER_OFF# W_DISABLE#1 LED#1/DAS/DSS# NC NC NC NC GPIO_5 GPIO_6 GPIO_7 W_DISABLE#2 UIM-RFU UIM-RESET UIM-CLK UIM-DATA UIM-PWR DEVSLP GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 PERST# CLKREQ# PEWAKE# NC1 NC2 COEX3 COEX2 COEX1 SIM_DETECT SUSCLK 3.3VAUX3 3.3VAUX4 3.3VAUX5 1 @ 2 R906 1 0_0402_5% CONFIG_3 GND1 GND2 USB_D+ USBDGND3 NC NC NC NC CONFIG_0 WAKE_ON_WWAN# DPR GND4 USB3.0-TX-(Device) USB3.0-TX+(Device) GND5 USB3.0-RX-(Device) USB3.0-RX+(Device) GND6 PERN0/SATA-B+ PERP0/SATA-BGND7 PETN0/SATA-APETP0/SATA-A+ GND8 REFCLKN REFCLKP GND9 ANTCTL0 ANTCTL1 ANTCTL2 ANTCTL3 RESET# CONFIG_1 GND10 GND11 CONFIG_2 2 1 3 5 7 9 11 3 @ 9 8 15 14 SATA_ITX_DRX_P0_C SATA_ITX_DRX_N0_C CR3 CR4 11 12 SATA_DTX_IRX_P0_C SATA_DTX_IRX_N0_C CR5 CR6 1 1 @ 1 1 @ @ 2 2 @ 2 2 0.01U_0402_16V7K 0.01U_0402_16V7K SATA_ITX_DRX_P0_R SATA_ITX_DRX_N0_R 0.01U_0402_16V7K 0.01U_0402_16V7K SATA_DTX_IRX_P0_R SATA_DTX_IRX_N0_R PS8520CTQFN20GTR2A0_TQFN20_4X4 4 PEG2 77 TYCO_2199230-3 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date Mini-Card 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Size C Date: A B C D Document Number Y501 NM-A032 Wednesday, March 27, 2013 E Sheet 40 of Rev 1.0 69 5 4 +3VALW 3 2 1 +3VALW_LAN J16 +LX JUMP_43X79 2 2 D Note: Place Close to LAN chip LL1 DCR< 0.15 ohm Rate current > 1A LL2 LL3 FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P 1 2 2 +1.1_AVDDL 1 +1.1_DVDDL +1.1_AVDDL_L CL39 0.1U_0402_16V4Z 1 2 Close to Pin40 Vendor recommand reserve the PU resistor close LAN chip 1 2 CL42 2 1 CL40 1 1 1 2 4.7U_0603_6.3V6K 100K_0402_5% CL37 2 1 SH00000GT0J LL1 1 2 +LX SH00000JM0J 4.7UH +-20% PCAA041B-4R7M 1.1A +LX_R CL41 LAN_PWR_ON# 2 0_0603_5% 2 10U_0805_10V4Z <46> RL3 2 LAN_PWR_ON# RL2 +1.1_DVDDL 1 1 @ LP2301ALT1G_SOT-23 CL35 0.01U_0402_25V7K 2 0.1U_0402_16V4Z CL38 0.1U_0402_16V4Z G D 1 D 1 S @ CL34 @ CL36 1000P_0402_50V7K QL1 3 Close together 1U_0402_6.3V4Z 2 @ 1 2 0.1U_0402_16V4Z 1 Place close to Pin34 @ 2 4.7K_0402_5% PLT_RST# 3 25 26 27 @ 1 RL16 +3VALW_LAN 2 4.7K_0402_5% @ 28 +3VALW_LAN <16> 1 RL17 LAN_XTALO LAN_XTALI 2 4.7K_0402_5% @ 13 19 31 34 6 2 1 2 41 LAN_RBIAS TESTMODE_0 TESTMODE_1 TESTMODE_2 RBIAS 1 +3VALW_LAN VDD33 40 +LX 5 DEBUGMODE Near Pin19 Near Pin31 +3VALW_LAN Optional @ LX XTLO XTLI CLKREQ# PPS DVDDL_REG AVDDL AVDDL AVDDL AVDDL AVDDL_REG AVDD33 AVDDH AVDDH_REG 24 37 +LX 1 2 30K_0402_5% RL10 1 2 30K_0402_5% RL9 QCA8171-BL3A-R_QFN40_5X5 1 2 SA00006540J QCA8172-AL3A-R_QFN40_5X5 +3VALW_LAN @ 1 2 1 2 1 2 1 2 +AVDD3.3 +2.7_AVDDH B GND @ +3VS +1.1_DVDDL 16 22 9 1 2 1 2 Near Pin9 1 2 1 2 RL11 1 +AVDD3.3 Near Pin37 Near Pin6 LAN_XTALI Place Close to PIN1 2 2.37K_0402_1% NC UL1 Near Pin13 1 RL8 Place Close to PIN10 CL55 CL53 CL52 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z CL51 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z CL50 B 1U_0402_6.3V4Z CL54 +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL 10 WAKE# DEBUGMODE 4 CLKREQ_LAN# 1 7 8 PERST# RL5 NC = 25MHz Pull-Down = 48MHz 1 2 Near Pin22 CL61 2 <42> <42> <42> <42> <42> <42> <42> <42> 1 2 0_0603_5% 2 +3VALW_LAN 1U_0402_6.3V4Z PLT_RST# PCIE_WAKE#_R LAN_MDI0LAN_MDI0+ LAN_MDI1LAN_MDI1+ LAN_MDI2LAN_MDI2+ LAN_MDI3LAN_MDI3+ CL60 2 0_0402_5% 2 0_0402_5% LAN_MDI0LAN_MDI0+ LAN_MDI1LAN_MDI1+ LAN_MDI2LAN_MDI2+ LAN_MDI3LAN_MDI3+ 1 10K_0402_5% 0.1U_0402_16V4Z 1 1 RL6 RL7 PCIE_WAKE# LAN_WAKE# REFCLK_N REFCLK_P 12 11 15 14 18 17 21 20 2 @ @ CLK_PCIE_LAN# CLK_PCIE_LAN TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3 RX_P C LAN_ACTIVITY# <42> LAN_LINK# <42> RL5 CL49 32 33 RX_N LAN_ACTIVITY# LAN_LINK# LAN_CLK_SEL CL48 10U_0805_10V4Z <15,19,40> <40,46,55> 35 38 39 23 CL47 10U_0805_10V4Z <16> <16> 36 QCA8171 CL46 1U_0402_6.3V4Z PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 LED_0 LED_1 LED_2 Atheros TX_P CL45 0.1U_0402_16V4Z <18> <18> TX_N 1000P_0402_50V7K 1 2 PCIE_PRX_C_DTX_P4 30 1U_0402_6.3V4Z PCIE_PRX_C_DTX_N4 29 2 0.1U_0402_16V7K CL58 2 0.1U_0402_16V7K CL44 1 0.1U_0402_16V4Z CL59 CL43 1 PCIE_PRX_DTX_P4 CL57 PCIE_PRX_DTX_N4 <18> 0.1U_0402_16V4Z <18> CL56 C H --> Overclocking mode L --> Not overclocking mode UL1 Place Close to Chip 1U_0402_6.3V4Z PLT_RST# 0.1U_0402_16V4Z <14,23,32,40,46> 1 RL4 +3VALW_LAN Place close to Pin16 YL7 LAN_XTALO 1 1 3 GND 1 CL62 15P_0402_50V8J 2 QCA8171/72 Pin defination difference. 3 GND 2 4 25MHZ_10PF_7V25000014 1 Pin17 Pin18 Pin19 Pin20 Pin21 CL63 15P_0402_50V8J QCA8171 2 LAN_MDI2+ LAN_MDI2- +1.1_AVDDL LAN_MDI3+ LAN_MDI3- A A QCA8172 NC NC NC NC Title LC Future Center Secret Data Security Classification Issued Date NC 2012/07/01 2014/07/01 Deciphered Date LAN_QCA8171 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 Sheet 1 41 of Rev 1.0 69 5 4 3 2 1 LAN_LINK# <41> LAN_LINK# <41> LAN_ACTIVITY# LAN_ACTIVITY# JRJ45 CL73 2 0.1U_0402_16V4Z 1 TL1 1 TCT TCT1 D <41> <41> <41> <41> <41> 2 LAN_MDI0+ LAN_MDI0+ LAN_MDI0- LAN_MDI1+ LAN_MDI1- LAN_MDI2+ LAN_MDI0CL74 0.1U_0402_16V4Z 2 1 3 LAN_MDI1+ 5 TD1+ 6 LAN_MDI2+ 8 1:1 MX1+ TD1- 4 LAN_MDI1CL75 0.1U_0402_16V4Z 2 1 MCT1 MX1- TCT2 TD2+ MCT2 1:1 MX2+ TD2- 7 MX2- TCT3 TD3+ MCT3 1:1 MX3+ 24 23 MCT0 RJ45_MIDI0+ 1 RL12 9 LAN_LINK# 2 +3VALW_LAN R_short 0_0805_5% @ CL64 470P_0402_50V7K 22 21 20 19 18 17 10 MCT1 RJ45_MIDI1+ 1 RL18 2 R_short 0_0805_5% LAN_MDI3+ <41> LAN_MDI3- LAN_MDI3+ 11 LAN_MDI3- 12 MX3- TCT4 MCT4 TD4+ 1:1 MX4+ 16 15 MCT2 RJ45_MIDI2+ 1 RL19 MCT3 14 RJ45_MIDI3+ 13 RJ45_MIDI3- 1 RL20 RJ45_MIDI2- 5 RJ45_MIDI1- 6 RJ45_MIDI3+ 7 RJ45_MIDI3- 8 1 +3VALW_LAN RL14 1 2 220_0402_5% 12 PR1+ PR1PR2+ PR3+ PR3PR2PR4+ G2 PR4- G1 14 13 Yellow LEDYellow LED+ SANTA_130456-111 2 ME@ FL5 C 1 SURGE@ CL66 10P_1206_2KV7K JP/N 2 @ CL69 reserved for EMI, place close to TL1 2 RL15 75_0402_1% 2 2 4 D R_short 0_0805_5% TL1 1 CL33 1U_0402_10V6K RJ45_MIDI2+ placement Green LED+ 2 1 1 3 11 RJ45_MIDI2- 350UH_NS892407 @ CL69 0.1U_0402_16V4Z 2 LAN_ACTIVITY# R_short 0_0805_5% 2 MX4- RJ45_MIDI0RJ45_MIDI1+ 2 C TD4- 1 RJ45_MIDI1- 1 <41> TD3- 2 RJ45_MIDI0+ Green LED- BS401N 1206 9 LAN_MDI2- LAN_MDI2- 2 220_0402_5% 10 RJ45_MIDI0- @ CL65 470P_0402_50V7K <41> RL13 1 1 SP05000650J 350UH_NS892405 Place CL33 close to TL1 B B Place Close to TL1 MCT3 MCT2 TCLAMP3302N.TCT_SLP2626P10-10 SURGE@ 1 SURGE@ BS401N 1206 2 FL4 SURGE@ 1 2 2 LAN_MDI3- FL3 LAN_MDI3+ 1 10 9 8 7 6 2 10 9 8 7 6 BS401N 1206 1 2 3 4 5 1 TCLAMP3302N.TCT_SLP2626P10-10 1 2 3 4 5 FL2 LAN_MDI2+ LAN_MDI1- 1 LAN_MDI2LAN_MDI1+ 2 10 9 8 7 6 FL1 10 9 8 7 6 GND 1 2 3 4 5 @ 11 1 2 3 4 5 11 LAN_MDI0+ GND LAN_MDI0- DL4 @ BS401N 1206 MCT0 DL3 BS4200N-C-LV_SMB-F2 MCT1 A A FL1 ~ FL4 DL3, DL4 Reserve for Serge Line to GND Reserve for Surge FL3 change to BS4200N for ESD request Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date LAN Transformer THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 Sheet 1 42 of Rev 1.0 69 3 SMSC thermal sensor placed near by VRAM 1 +3VS 2 REMOTE1- 2 1 1 2 @ C982 100P_0402_50V8J Remove +VDD netname REMOTE2+ REMOTE2- C443 0.1U_0402_16V4Z REMOTE1+ 2 REMOTE1- 3 REMOTE2+ 4 REMOTE2- 5 VDD SMCLK DP1 SMDATA DN1 ALERT# DP2 THERM# DN2 GND 10 EC_SMB_CK2 9 EC_SMB_DA2 8 EC_SMB_CK2 <17,23,32,34,36,46> REMOTE1- EC_SMB_DA2 <17,23,32,34,36,46> 1 2 C 2 B Q137 MMST3904-7-F_SOT323-3 E R624 7 2 6 1 Close to SSD side +3VS REMOTE2+ 10K_0402_5% @ @ C984 100P_0402_50V8J EMC1403-2-AIZL-TR_MSOP10 FAN_PWM & TACH for PWM FAN Address 1001_101xb REMOTE2- 1 2 2 B C Q138 MMST3904-7-F_SOT323-3 E REMOTE2+/-: Trace width/space:10/10 mil Trace length:<8" internal pull up 1.2K to 1.5V R for initial thermal shutdown temp C Under VRAM REMOTE1+ U29 1 C658 2200P_0402_50V7K D 1 REMOTE1+ C449 2200P_0402_50V7K 1 3 Close U29 2 1 D 4 3 5 C B B FAN1 Conn +5VS JFAN1 2 C986 10U_0805_10V6K 1 1 C49 0.1U_0402_10V7K @ <46> <46> 1 2 3 4 5 6 EC_FAN_SPEED EC_FAN_PW M 2 1 2 3 4 G5 G6 ACES_85205-04001 ME@ A A Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 2 VGA Thermal sensor/FAN CONN Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 Sheet 1 43 of Rev 1.0 69 A B C D 1 E F G H SATA ODD Conn. SATA HDD Conn. JHDD1 <13> <13> <13> <13> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C627 1 C628 1 1 2 3 4 5 6 7 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 SATA_PRX_C_DTX_P1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 @J12 @ J12 1 +5VS 1 2 2 +5VS_HDD JUMP_43X79 +5VS 2 1 2 1 C631 1000P_0402_50V7K 2 1 C632 0.1U_0402_16V4Z 2 1 C633 1U_0603_10V4Z 2 <13> <13> <13> <13> SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 <32,46> <19> V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C629 1 C630 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K R1479 1 R1476 1 1 R710 SLI_FAN_SPEED ODD_DETECT# SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2 2 R_short 0_0402_5% @2 0_0402_5% @2 0_0402_5% +5VS_ODD R921 +3VS <14> <32,46> GND GND 1 R1497 1 R1494 1 ODD_DA#_R SLI_FAN_PWM 1 2 3 4 5 6 7 HDD_PWR_DET# SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 2 @ ODD_DA# 10K_0402_5% 8 9 10 11 12 13 2 0_0402_5% 2 R_short 0_0402_5% ME@ GND A+ AGND BB+ GND DP +5V +5V MD GND GND GND GND 15 14 SANTA_202404-1 24 23 2 1 C634 10U_0603_6.3V6M JODD2 GND A+ AGND BB+ GND 1 SANTA_191201-1 C635 10U_0603_6.3V6M ME@ 2 ODD Power Control @ 1 J6 1 2 2 JUMP_43X79 +5VALW +5VS +5VS_ODD 2 2 1 1 1 C639 10U_0603_6.3V6M 2 1 R1477 @ 470_0603_5% C637 0.1U_0402_16V4Z 3 2 1 2 ODD_EN# Q90 2 2 G 2N7002KW_SOT323-3 D S ODD_EN# C1057 0.01U_0402_16V7K 1 2N7002KW_SOT323-3 3 C638 0.01U_0402_16V7K 1 ODD_EN @ D 2 G 1 <19> 2 @ 3 2 R1110 1 2 C1049 0.1U_0402_16V4Z 100K_0402_5% Q89 1 1 1 2 R1496 100K_0402_5% G R923 100K_0402_5% @ 3 D 1 S 3 +5VS_ODD AO3413 VGS= -4.5V, Id=-3A, Rds<97m ohm Q88 AO3413_SOT23-3 @ S 2 R1478 100K_0402_5% HDD_PWR_DET# R1504 1 0_0402_5% 2 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 HDD/ODD CONN 2014/07/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 A B C D E F G Sheet 44 H of Rev 1.0 69 4 3 2 1 RA1648 RA1649 1 +5VA 1 2 CA1385 1 10U_0805_10V4Z 10U_0805_10V4Z 2 +5VD 2 1 CA1387 CA1386 <13> HDA_SDOUT_AUDIO <13> HDA_BITCLK_AUDIO 1 RA1651 2 2 10_0402_5% 2 10_0402_5% 2 10_0402_5% 1 RA1652 1 RA1653 <13> 1 HDA_SYNC_AUDIO 0.1U_0402_16V4Z CA1384 2 2 D UA1 1 9 2 26 40 1 CA1383 +AVDD2 10U_0805_10V4Z 41 46 +CPVDD 36 2 3 DMIC_DATA_R DMIC_CLK_R HDA_SDOUT_AUDIO_R 8 5 HDA_BITCLK_AUDIO_R 6 HDA_SDIN0_R 10 HDA_SYNC_AUDIO_R 12 PC_BEEP <50> <50> 1 39.2K_0402_1% 1 20K_0402_1% PLUG_IN MIC_JD 2 RA1654 2 RA1656 place close to pin 13 C 13 14 <50> <50> MIC1_L MIC1_R MIC1_L MIC1_R 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 1 1 2 CA1280 C_MIC1_L 2 CA1279 C_MIC1_R 19 20 17 18 22 21 24 23 1 P/N chang to 0 ohm to B phase 10 mils DMIC_CLK <35> DMIC_DATA DMIC_DATA 1 R956 2 0_0402_5% 1 R957 2 0_0402_5% RA1657 33_0402_5% DMIC_CLK_R <13> 2 <35> DMIC_CLK DMIC_DATA_R +3.3VD CA1378 2 Place close to pin 1 +3.3VD 1 1 CA1382 +1.5VS 11 HDA_RST_AUDIO# 47 A_PDB DVDD DVDD-IO MONO-OUT MIC2-VREFO MIC1-VREFO-R MIC1-VREFO-L AVDD1 AVDD2 JDREF PVDD1 PVDD2 CPVDD GPIO0/DMIC-DATA GPIO1/DMIC-CLK VREF HPOUT-L(PORT-I-L) HPOUT-R(PORT-I-R) CBN CBP SDATA-IN SDATA-OUT CPVEE BCLK LDO1-CAP LDO2-CAP LDO3-CAP SYNC PCBEEP SPK-OUT-LSPK-OUT-L+ SPK-OUT-RSPK-OUT-R+ Sense A Sense B MIC1-L(PORT-B-L) MIC1-R(PORT-B-R) MIC2-L(PORT-F-L) MIC2-R(PORT-F-R) SPDIF-OUT/GPIO2 DVSS AVSS1 AVSS2 Thermal Pad LINE1-L(PORT-C-L) LINE1-R(PORT-C-R) LINE2-L(PORT-E-L) LINE2-R(PORT-E-R) 16 29 30 31 15 Ext. MIC +MIC1_VREFO_L RA1650 2 10 mils 1 20K_0402_1% Place close to Pin 28 28 32 33 35 37 R5 2 R10 2 HPOUTL_R HPOUTR_R 1 60.4_0402_1% 1 60.4_0402_1% HP_OUTL HP_OUTR HP_OUTL HP_OUTR <50> <50> 1 CA1388 Place close to Pin 34/35/36 34 1 2.2U_0603_10V6K 1 2.2U_0603_10V6K CA1391 2 27 39 7 CA1392 1 CA1393 1 CA1394 1 43 42 44 45 2 CA1389 SPKOUT_L2SPKOUT_L1+ SPKOUT_R2SPKOUT_R1+ 0.1U_0402_16V4Z 2 10 mils 1 CA1390 2 2.2U_0603_10V6K 2 10U_0805_10V4Z 2 10U_0805_10V4Z 2 10U_0805_10V4Z 30 mils C 48 2 R946 1 FBMA-10-100505-301T_2P SPDIF_OUT SPDIF_OUT 4 25 38 49 <50> R438 <46> 1 EC_MUTE# 2 A_PDB 1 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z Place close to Pin 26 0.1U_0402_16V4Z 10U_0603_6.3V6M CA1381 10U_0805_10V4Z +5VD 2 1 CA1380 CA1379 1 2 R_short 0_0402_5% 0.1U_0402_16V4Z CA1377 Place close to pin 9 D 1 10U_0805_10V4Z 2 @ 2 0_0402_5% 1 100K_0402_5% R437 100K_0402_5% @ RESETB 2 5 PDB CA13951 <13> ALC282-CG_MQFN48_6X6 HDA_SDIN0 HDA_SDIN0 10U_0805_10V4Z 2 1 HDA_SDOUT_AUDIO @ CA1396 10P_0402_50V8J 2 Place close to Pin 34/35/36 HDA_BITCLK_AUDIO HDA_SYNC_AUDIO 2 2 PC Beep 10P_0402_50V8J PCH Beep <46> BEEP# 1 CA24 2 0.1U_0402_16V4Z <13> HDA_SPKR 1 CA23 2 0.1U_0402_16V4Z 1 +CPVDD @ CA11 1 2 1000P_0402_50V7K~N SPK_L2 @ CA12 1 2 1000P_0402_50V7K~N RA4 1 2 33_0402_5% PC_BEEP RA3 10K_0402_5% 30 mils 2 +3VS 1 +5VD +5VS 1 2 LA66 FBMA-10-100505-301T_2P 1 RA1660 1 RA1658 2 0_0402_5% +1.5VS 1 @ RA1659 2 0_0402_5% +3VS 4 external jacks: Line-in / Mic-in / Hp-out / SPDIF-OUT Internal speaker Internal Stereo DMIC DA1 @ AZ5125-02S.R7G_SOT23-3 For EMI HDA_BITCLK_AUDIO_R If AVDD2 is design to 1.5V, you will get better power consumption. AGND Tied at one point only under the codec or near the codec R126 1 @ 10_0402_5% 2 1 @ 10P_0402_50V8J 2 DGND Pin Assignment Location Function SPEAKER-OUT (pin-43/44/45/46_Port D) Internal Internal Speaker Cap-Saving HP-OUT (pin-32/33_Port I) External Headphone out LINE1 (pin-21/22_Port C) External Line in MIC1 (pin-19/20_Port B) External Mic in MONO-OUT (pin-16) NC Security Classification NC Issued Date MIC2 (pin-17/18_Port F) C200 Reserve for ESD request. LC Future Center Secret Data AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 4 3 2 A Title Audio Codec Size C Date: 5 DA2 @ AZ5125-02S.R7G_SOT23-3 2 2012/5/02 2012/05/02 Deciphered Date Internal Internal Mic ( Digital MIC ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL DMIC1/2 (pin-2/3) 1 2 3 4 G5 G6 ACES_85205-04001 ME@ ALC282 Configuation - example 0_0402_5% A JSPK1 1 2 3 4 5 6 SPK_L1 SPK_L2 SPK_R1 SPK_R2 2 LA65 FBMA-10-100505-301T_2P +AVDD2 2 0_0603_5% 2 0_0603_5% 2 0_0603_5% 2 0_0603_5% 1 1 1 1 3 FBMA-10-100505-301T_2P 1 2 LA64 RA56 RA58 RA60 RA61 SPKOUT_L1+ SPKOUT_L2SPKOUT_R1+ SPKOUT_R2- 2 LA63 FBMA-10-100505-301T_2P +5VA B 2009/11/02 Modify PC_BEEP1 @ FBMA-10-100505-301T_2P 1 2 LA62 +3.3VD 2 1000P_0402_50V7K~N SPK_L1 2 1 EC Beep +3.3VD 2 1000P_0402_50V7K~N 3 1 10P_0402_50V8J 1 1 @ CA10 1 1 10P_0402_50V8J @ CA9 SPK_R2 2 CA1399 SPK_R1 CA1398 1 B CA1397 1 2 Document Number Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 45 Rev 1.0 of 69 5 4 10_0402_5% 2 1 +3VALW 1 CE1 CE4 1000P_0402_50V7K 1 LE2 1 2 EC_AGND BLM18PG181SN1D_0603 1 1 +3VALW_R CE3 0.1U_0402_16V4Z RE4 10K_0402_5% @ 1 2 100K_0402_5% <19> EC_SMI# <40> EC_RX <40> EC_TX <14,23,32,40,41> PLT_RST# <19> EC_SCI# <19> GATEA20 1 CE11 1U_0402_6.3V6K 2 <47> KSI[0..7] C KSI[0..7] Need to check which SMBus can be use for debug +3VALW_R 1 EC_SMB_CK1 EC_SMB_DA1 PAD PAD PAD PAD PAD IT0 IT1 IT2 IT3 IT4 PAD PAD PAD IT5 IT6 IT7 2 RE22 0_0603_5% 1 RE23 1 RE24 2 2.2K_0402_5% EC_SMB_CK1 KSI7 KSI6 WRST# 2 2.2K_0402_5% EC_SMB_DA1 58 59 60 61 62 63 64 65 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 For factory EC flash KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 KSO0/PD0 Int. K/B KSO1/PD1 Matrix KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5 ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/GPI4 ADC5/DCD1#/GPI5 ADC6/DSR1#/GPI6 ADC7/CTS1#/GPI7 ADC IT8586E/AX LQFP-128L DAC DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3 DAC4/DCD0#/GPJ4 DAC5/RIG0#/GPJ5 PS2CLK0/TMB0/CEC/GPF0 PS2DAT0/TMB1/GPF1 GPF2 PS2 GPF3 PS2CLK2/GPF4 PS2DAT2/GPF5 EXTERNAL SERIAL FLASH GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6 NC NC NC NC SPI Flash ROM AC_IN# LID_SW# UART PWR_LED# BATT_CHG_LED# BATT_LOW_LED# LED_KB_PWM SLI_FAN_PWM EC_FAN_PWM BEEP# EC_GPO7 BATT_LEN# SUSP# 66 67 68 69 70 71 72 73 NTC_V TURBO_V BATT_TEMP IMVP_IMON EC_ON ADP_I AD_ID VDDQ_PGOOD 78 79 80 81 SUSWARN# MAINPWON_EC H_PROCHOT#_EC ENBKL 85 86 87 88 89 90 USB_CH PBTN_OUT# PM_SLP_SUS# SUSACK# TP_CLK TP_DATA 96 97 98 99 CAPS_LED# PCH_PWR_EN ACOFF PCH_PWROK 101 102 103 105 108 109 1 74 PWM LPC 24 25 28 29 30 31 32 34 120 124 VGA_AC_DET VGA_AC_DET RE32 10K_0402_5% <23> 2 VSTBY VSTBY VSTBY VSTBY VSTBY VSTBY(PLL) AVCC 26 50 92 114 121 127 12 11 KSO[0..17] <47> EC_GPO7 PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5 PWM6/SSCK/GPA6 PWM7/RIG1#/GPA7 TMRI0/GPC4 TMRI1/GPC6 0_0402_5% 1 0_0402_5% 1 @ 0_0402_5% 1 <40,41,55> SUS_VCCP SUS_VCCP <62> +3VALW_R PWR_LED# <51,52> BATT_CHG_LED# <51> BATT_LOW_LED# <51> LED_KB_PWM <47> SLI_FAN_PWM <32,44> EC_FAN_PWM <43> BEEP# <45> RE8 10K_0402_5% @ +3VS BATT_LEN# <57> SUSP# <32,55,60,61,62> 1 RE6 EC_GPO7 LAN_WAKE# <15> NTC_V <57> TURBO_V <57> BATT_TEMP <57> IMVP_IMON <64> EC_ON <52,59> ADP_I <57,58> AD_ID <57> VDDQ_PGOOD <60> RE39 1 RE17 1 DRAMRST_CNTRL_EC 2 +3VALW_R RE43 2 RE44 2 RE45 2 AC_PRESENT_R AC_PRESENT 1 WRST# KBRST#/GPB6 SERIRQ/GPM6 LFRAME#/GPM5 LAD3/GPM3 LAD2/GPM2 LAD1/GPM1 LAD0/GPM0 LPCCLK/GPM4 WRST# ECSMI#/GPD4 PWUREQ#/BBO/SMCLK2ALT/GPC7 LPCPD#/GPE6 LPCRST#/GPD2 ECSCI#/GPD3 GA20/GPB5 2 0_0402_5% AC_PRESENT 2 <54> 4 5 6 7 8 9 10 13 14 15 16 17 22 23 126 KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC WRST# EC_SMI# EC_RX EC_TX PLT_RST# EC_SCI# GATEA20 KSO[0..17] <19> KBRST# <17> SERIRQ <17,40> LPC_FRAME# <17,40> LPC_AD3 <17,40> LPC_AD2 <17,40> LPC_AD1 <17,40> LPC_AD0 <16> CLK_PCI_EC VCC VBAT UE1 VCORE 3 LAN_WAKE# RE38 1 AC_PRESENT_R minimum trace width 12 mil D 2 1 2 2 2 R_short 0_0402_5% CE5 0.1U_0402_16V4Z 1 CE6 0.1U_0402_16V4Z RE3 CE7 0.1U_0402_16V4Z 2 0_0402_5% @ LE1 1 2 BLM18PG181SN1D_0603 CE8 0.1U_0402_16V4Z 1 CE9 0.1U_0402_16V4Z RE2 CE10 0.1U_0402_16V4Z +3VALW_EC +3VS +RTCBATT D +3VALW_EC +3VALW_R All capacitors close to EC +3VALW_R 2 +3VALW_R .1U_0402_16V7K 2 VCOREVCC 1 10P_0402_50V8J 1 2 2 1 2 CE63 220P_0402_25V8J 2 0_0603_5% 2 2 +3VL 1 RE1 @ 1 @ Close EC CE204 2 0_0603_5% 1 @ 1 1 RE5 2 2 @ 1 RE125 1 CLK_PCI_EC 2 For EMI For ESD PLT_RST# 3 +3VS SUSWARN# <15> MAINPWON <57,59> PROCHOT# <57> ENBKL <35> 2 0_0402_5% 2 0_0402_5% CE2 0.1U_0402_16V4Z EC_FAN_SPEED 10K_0402_5% 2 1 RE9 SLI_FAN_SPEED 10K_0402_5% 2 1 RE16 C +3VS USB_CH <50> PBTN_OUT# <15> PM_SLP_SUS# <15,55> SUSACK# <15> TP_CLK <47> TP_DATA <47> TP_CLK 4.7K_0402_5% 1 2 RE11 TP_DATA 4.7K_0402_5% 1 2 RE12 +5VALW CAPS_LED# <51> PCH_PWR_EN <55,57> ACOFF <58> PCH_PWROK <15> 10K_0402_5% 1 RE18 2 USB_ON# 10K_0402_5% 1 RE19 2 EC_FAN_PWM10K_0402_5% 1 RE20 2 USB_CH EC_SPI_CS1# EC_SPI_SI EC_SPI_SO_L EC_SPI_CLK +3VS ACPRN LID_SW# ACPRN LID_SW# <58> <47> @ +3VS PECI_EC LAN_PWR_ON# EC_SMB_CK2 EC_SMB_DA2 EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3 Bus GPIO GPJ1 SSCE0#/GPG2 SSCE1#/GPG0 DSR0#/GPG6 DTR1#/SBUSY/GPG1/ID7 CRX0/GPC0 CTX0/TMA0/GPB2 RI1#/GPD0 RI2#/GPD1 TACH2/GPJ0 TACH1A/TMA1/GPD7 TACH0A/GPD6 L80HLAT/BAO/GPE0 L80LLAT/GPE7 +3VLP RE34 1 B <64> +3VS 1 RE29 2 2.2K_0402_5% EC_SMB_CK2 1 RE30 2 2.2K_0402_5% EC_SMB_DA2 <15> <15> 2 0_0402_5% 33 35 93 USB_ON# DPWROK_EC EC_RSMRST# <49> USB_ON# DPWROK_EC EC_RSMRST# <19> 112 125 VR_ON VR_ON 2 128 EC_LID_OUT# AC_PRESENT_R EC_LID_OUT# VSTBY0 GPE4 WAKE UP GINT/CTS0#/GPD5 RTS1#/GPE5 CLKRUN#/GPH0/ID0 CK32KE/GPJ7 CK32K/GPJ6 GPIO 77 100 106 104 107 119 123 18 21 76 48 47 19 20 EXIO_DATA <54> EXIO_CS EXIO_CLK EC_MUTE# LAN_WAKE# DRAMRST_CNTRL_EC ME_FLASH SYSON BKOFF# AOAC_ON# PM_SLP_S3# PM_SLP_S4# NOVO# SLI_FAN_SPEED EC_FAN_SPEED TP_LED# NUM_LED# EC_MUTE# <54> LPC_FRAME# 10K_0402_5% 1 RE21 <54> 2 <45> +3VLP DRAMRST_CNTRL_EC <6> ME_FLASH <13> SYSON <60> BKOFF# <35> AOAC_ON# <40> PM_SLP_S3# <15> PM_SLP_S4# <15> NOVO# <52> SLI_FAN_SPEED <32,44> EC_FAN_SPEED <43> TP_LED# <51> NUM_LED# <51> RE28 1 ACPRN 10K_0402_5% 2 B +3VS RE7 ENBKL 1 2 @ 100K_0402_5% 20120730 VA Reserved hardware strapping for Auto load code Clock <64> RE41 1 VR_HOT# 2 H_PROCHOT# VSS VSS VSS VSS VSS AVSS 75 1 27 49 91 113 122 VSS R_short 0_0402_5% H_PROCHOT#_EC S 2 G QE1 2N7002H_SOT23-3 IT8586E-FX_LQFP128_14X14 D <57,6> CE14 47P_0402_50V8J @ 1 2 43_0402_5% <41> LAN_PWR_ON# <17,23,32,34,36,43> EC_SMB_CK2 <17,23,32,34,36,43> EC_SMB_DA2 PWRSW# SM XLP_OUT SMCLK1/GPC1 SMDAT1/GPC2 SMCLK2/PECI/GPF6 SMDAT2/PECIRQT#/GPF7 CRX1/SIN1/SMCLK3/GPH1/ID1 CTX1/SOUT1/GPH2/SMDAT3/ID2 EXIO_DATA EXIO_CS EXIO_CLK 2 EC_SMB_CK1 EC_SMB_DA1 RE37 1 EC_SMB_CK1 EC_SMB_DA1 <6> H_PECI 82 83 84 1 <57,58> <57,58> 110 111 115 116 117 118 94 95 ON/OFF 3 <52> +3VL EC_AGND +3VALW_R RE25 RE15 1 10K_0402_5% 2 LID_SW# CPU1.5V_S3_GATE <10> CE16 1 2 100P_0402_50V8J ACPRN CE17 1 2 100P_0402_50V8J 100K_0402_5% EMC Request SYSON RE31 100K_0402_5% 1 1 RE40 0_0402_5% SYSON RE27 0.1U_0402_10V6K CE15 ACPRN @ 100K_0402_5% SUSP# 1 RE14 @ 10K_0402_5% 1 2 BATT_TEMP @ 2 EC_GPO7 @ @ 2 BKOFF# 10K_0402_5% 2 2 RE13 1 1 ON/OFF 1 S IC IT8586E/EX LQFP 128P KB CONTROLLER RE10 @ 10K_0402_5% 1 2 RE26 10K_0402_5% 2 EXIO_CS 100K_0402_5% @ EC_SPI_CS1# EC_SPI_SI EC_SPI_SO_L EC_SPI_CLK RE1524 1 2 0_0402_5% @ 2 RE1525 1 0_0402_5% @ 2 RE1526 1 0_0402_5% @ 2 RE1527 1 0_0402_5% SPI_CS1#_R SPI_SI_R1 SPI_SO_L1 SPI_CLK_PCH_1 SPI_CS1#_R 4 A 2 <17> SPI_SI_R1 <17> SPI_SO_L1 <17> Title LC Future Center Secret Data Security Classification Issued Date SPI_CLK_PCH_1 2012/05/02 Deciphered Date EC ITE8586LQFP 2012/5/02 <17> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Size C Date: 5 1 2 RE33 1 2 A 3 2 Document Number Y501 NM-A032 Wednesday, March 27, 2013 1 Sheet 46 Rev 1.0 of 69 5 4 3 2 1 15" INT_KBD Conn. <46> 2 @ 100P_0402_50V8J KSO17 C795 1 2 @ 100P_0402_50V8J KSO2 C734 1 2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 D JKBL1 +VCC_KB_LED 2 1 1 2 3 4 5 6 1 2 3 4 G1 G2 E&T_6906-Q04N-00R ME@ @ +5VS AO3413 VGS= -4.5V, Id=-3A, Rds<97m ohm +VCC_KB_LED G1 G2 31 32 Q121 AO3413_SOT23-3 3 1 KBL@ G R1229 10K_0402_5% KBL@ ACES_85202-3005N D C794 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 S KSO16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0.1U_0402_10V6K C905 D C KB Lighting CONN.4pin JKB1 <46> 2 2 KSO[0..17] 1 KSI[0..7] KSO[0..17] 2 KSI[0..7] ME@ CONN PIN define need double check R1232 1 2 1 Q163 2 3 1 C C907 0.01U_0402_16V7K S 2N7002KW_SOT323-3 +3VS R1230 2 R1480 100K_0402_5% KBL@ @ D 2 G LED_KB_PWM C908 0.1U_0402_16V4Z 1 0_0402_5% <46> 1 KBL_DET @ 1 2 @ KBL_DET# KBL_DET# <54> 10K_0402_5% To TP/B Conn. R1231 1 @ 2 KBL_DET# 10K_0402_5% JTP1 <11,12,17,40> <11,12,17,40> B <46> <46> TP_DATA TP_CLK 1 2 3 4 5 6 SMB_DATA_S3 SMB_CLK_S3 SMB_DATA_S3 SMB_CLK_S3 TP_DATA TP_CLK 1 2 @ C761 100P_0402_50V8J 1 +3VS @ C762 C760 100P_0402_50V8J 2 0.1U_0402_16V4Z 7 8 ME@ 1 2 3 4 5 6 Lid Switch B GND GND ACES_88514-00601-071 +3VL R1002 1 2 I/O4 I/O2 C758 0.1U_0402_16V4Z 2 2 OUTPUT 2 6 3 LID_SW# 2 U37 1 3 C759 10P_0402_50V8J <46> C553 1 GND 5711ACDL-M3T1S SOT-23 1 330P_0402_50V8J 2 VDD 1 1 5 I/O1 GND +3VALW I/O3 2 100K_0402_5% VDD D58 4 R1003 1 +VCC_LID R_short 0_0402_5% AZC099-04S.R7G_SOT23-6 @ For ESD request For ESD Request A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date KB/ KB-LIGHT/ LID IC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 5 4 3 2 1 Sheet 47 of Rev 1.0 69 5 4 3 2 1 CW3 1 2 UW1 RW1 2 +3VS 1 +3VS_CARD 12 +DV12 R_short 0_0603_5% +3V3_AUX RW10 1 2 R_short 0_0402_5% +3VS_CARD D 1.2V Power Source Selection: (Optional) <18> USB30_RX_N6 <18> USB30_RX_P6 <18> USB30_TX_N6 <18> USB30_TX_P6 13 +3V3_AUX AC Coupling close to pin1 and pin2 of Chip RW2 PMOS V33IN AVDD33 .1U_0402_16V7K 2 .1U_0402_16V7K 2 .1U_0402_16V7K 2 2 .1U_0402_16V7K 1 CW1 USB30_RX_N6_C 1 1 CW2 USB30_RX_P6_C 2 1 CW8 USB30_TX_N6_C 4 1 CW9 USB30_TX_P6_C 5 DVDD33 7 2 1 CW25 15P_0402_50V8J +DV12 1 3 GND 1 3 28 GND 1 2 4 25MHZ_10PF_7V25000014 2 3 2 <18> USB20_P4 <18> USB20_N4 CW5 1 2 +3VS_CARD 0.1U_0402_16V4Z 1 RW9 2 680_0402_1% Vendor recommend to reserve CW6 1 2 0.1U_0402_16V4Z 26 27 8 9 24 +3VS_CARD 22 D VUHSI CW4 1 2 21 Close to chip RXN 1U_0402_10V6K RXP X1 SB5 X2 SB4 SB3 AVDD12 SB2 AVDD12 SB1 CW26 15P_0402_50V8J +CRD_POWER 25 TXP 1M_0402_5% YW1 23 TXN SB6 6 1 4.7U_0603_10V6K DVDD12 20 SD_DATA2_MS_CLK_R RW3 1 2 0_0402_5% 19 SD_MS_DATA3_R RW4 1 2 0_0402_5% SD_CMD_MS_DATA2_R RW5 1 2 0_0402_5% 17 SD_CLK_MS_DATA0_R RW6 1 2 0_0402_5% SD_CLK_MS_DATA0 16 SD_DATA0_MS_DATA1_R RW7 1 2 0_0402_5% SD_DATA0_MS_DATA1 15 SD_DATA1_MS_BS_R RW8 1 2 0_0402_5% SD_DATA1_MS_BS 18 SD_DATA2_MS_CLK SD_MS_DATA3 SD_CMD_MS_DATA2 DP DM SD_WP SD_CDZ 10 SD_WP 11 SD_CD# 14 MS_INS# AVDD33 RTERM MS_INS RSTZ G1 29 C C GL3213-OHY03_QFN28_5X5 < 4 in 1 Card Reader Connector > +CRD_POWER (40mil) +CRD_POWER 800mA JREAD2 41 42 SD CD/WP GND SD CD/WP GND 2 Colse to Conn. 17 10 8 12 15 14 7 5 20 SD_DATA2_MS_CLK SD_CLK_MS_DATA0 SD_DATA0_MS_DATA1 SD_CMD_MS_DATA2 SD_MS_DATA3 MS_INS# SD_DATA1_MS_BS 2 1 2 Colse to Socket Pin11. SD_CLK_MS_DATA0 B SD_DATA2_MS_CLK 2 XD GND XD GND MS8-SCLK MS4-DATA0 MS3-DATA1 MS5-DATA2 MS7-DATA3 MS6-INS MS2-BS MS1-VSS MS10-VSS 6 13 1 RW11 10_0402_5% RW12 10_0402_5% @ @ 1 CW550 10P_0402_50V8J T-SOL_144-1313002600_40P_NR-T 1 ME@ 1 CW551 10P_0402_50V8J @ 2 @ 2 For EMI 2 SD_DATA2_MS_CLK SD_CLK_MS_DATA0 Close to Pin13 2 Close to Pin25 SD6-VSS SD3-VSS +3V3_AUX CW24 1U_0402_10V6K 2 2.2U_0603_6.3V6K 2 1 40 mils 31 40 XD07-WE XD08-WP XD06-ALE XD01-CD XD02-R/B XD03-RE XD04-CE XD05-CLE 1 2 Close to Pin22 1 CW23 2 CW10 0.1U_0402_16V4Z CW22 4.7U_0603_10V6K 1 +3VS_CARD 33 32 34 39 38 37 36 35 SD_CLK_MS_DATA0 SD_DATA0_MS_DATA1 SD_DATA1_MS_BS SD_DATA2_MS_CLK SD_MS_DATA3 SD_CMD_MS_DATA2 SD_CD# SD_WP 1 Colse to Conn. Close to Pin28 All of cap. close to chip 40 mils 2 9 4 3 21 19 16 1 2 (40mil) CW18 0.1U_0402_16V4Z 2 @ SD5-CLK SD7-DAT0 SD8-DAT1 SD9-DAT2 SD1-DAT3 SD2-CMD SD-CD SD-WP (40mil) 11 18 CW17 10U_0805_10V6K 1 SD4-VDD MS9-VCC XD10-D0 XD11-D1 XD12-D2 XD13-D3 XD14-D4 XD15-D5 XD16-D6 XD17-D7 2 Close to Pin12 Close to Pin3 CW15 0.1U_0402_16V4Z 2 CW21 0.1U_0402_16V4Z 2 1 1 XD-VCC 1 B 2 1 CW7 0.1U_0402_16V4Z CW19 1 CW20 1U_0402_10V6K 2.2U_0603_6.3V6K 20 mils 30 29 28 27 26 25 24 23 CW16 0.1U_0402_16V4Z 22 +DV12 RW13 10_0402_5% RW14 10_0402_5% CW552 10P_0402_50V8J A 1 @ 1 @ 1 2 Issued Date 2012/07/01 2014/07/01 Deciphered Date 2 Y501 NM-A032 4 3 2 @ Card reader GL3213 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: 5 1 Title LC Future Center Secret Data Security Classification CW553 10P_0402_50V8J @ 1 Sheet 48 of Rev 1.0 69 A A B C D E LEFT SIDE USB3.0 PORT X1 +5VALW +USB_VCCA U39 <46> USB_ON# USB_ON# GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 USB_OC1# G547I2P81U_MSOP8 1 1 Low Active 2A USB_OC1# +USB_VCCA C814 220U_6.3V_M 1 2 <18> + C767 0.1U_0402_16V4Z 2 1 1 2 3 4 1 2 C816 470P_0402_50V7K C904 @ 1000P_0402_50V7K 1 2 For EMI request 1 2 C819 For ESD request USB2.0 choke --> SM070001S0J 0.1U_0402_16V4Z USB3.0 Choke --> SM070001S0J JUSB1 <18> <18> L68 2 USB30_RX_N2 2 3 USB30_RX_P2 3 1 4 1 USB30_RX_R_N2 4 USB30_RX_R_P2 WCM-2012-900T_4P R1162 1 R1163 1 USB20_N2 USB20_P2 USB20_N2 USB20_P2 <18> <18> USB30_RX_N2 USB30_RX_P2 <18> <18> USB30_TX_N2 USB30_TX_P2 @ R1154 1 @ R1155 1 @ R1156 1 @ R1157 1 @ @ USB30_RX_N2 USB30_RX_P2 USB30_TX_N2 C300 1 USB30_TX_P2 C299 1 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K USB30_TX_C_N2 USB30_TX_C_P2 L70 USB30_TX_C_N2 2 USB30_TX_C_P2 3 2 1 3 4 1 USB30_TX_R_N2 4 USB30_TX_R_P2 2 0_0402_5% USB30_RX_R_N2 2 0_0402_5% USB30_RX_R_P2 2 0_0402_5% USB30_TX_R_N2 2 0_0402_5% USB30_TX_R_P2 1 2 3 4 5 6 7 8 9 VBUS DD+ GND_1 SSRXSSRX+ GND_2 SSTXSSTX+ 13 12 11 10 GND_6 GND_5 GND_4 GND_3 SANTA_370300-1 ME@ WCM-2012-900T_4P 2 2 L72 USB20_N2 2 USB20_P2 3 2 1 1 USB20_N2_R 4 USB20_P2_R For ESD request D24 @ 3 4 WCM-2012-900T_4P D27 USB20_N2_R USB30_RX_R_N2 9 10 1 1USB30_RX_R_N2 USB30_RX_R_P2 8 9 2 2 USB30_RX_R_P2 USB30_TX_R_N2 7 7 4 4 USB30_TX_R_N2 USB30_TX_R_P2 6 6 5 5 USB30_TX_R_P2 3 3 3 2 1 I/O4 GND VDD I/O1 I/O3 6 5 +5VALW 4 USB20_P2_R +USB_VCCA C815 220U_6.3V_M 1 2 @ For EMI request USB2.0 choke --> SM070000I00 + For ESD request @ @ I/O2 AZC099-04S.R7G_SOT23-6 8 YSCLAMP0524P_SLP2510P8-10-9 3 2 0_0402_5% USB20_N2_R 2 0_0402_5% USB20_P2_R D29 USB30_RX_R_N5 9 10 1 1USB30_RX_R_N5 USB30_RX_R_P5 8 9 2 2 USB30_RX_R_P5 USB30_TX_R_N5 7 7 4 4 USB30_TX_R_N5 USB30_TX_R_P5 6 6 5 5 USB30_TX_R_P5 1 2 C817 470P_0402_50V7K C818 1 USB3.0 Choke --> SM070001U00 For ESD request L69 0.1U_0402_16V4Z 3 3 2 USB30_RX_N5 2 USB30_RX_P5 3 JUSB2 <18> YSCLAMP0524P_SLP2510P8-10-9 <18> USB20_N3 USB20_P3 <18> <18> USB30_RX_N5 USB30_RX_P5 <18> <18> USB30_TX_N5 USB30_TX_P5 R1165 1 @ R1164 1 @ R1161 1 R1160 1 USB20_N3 USB20_P3 USB30_RX_N5 USB30_RX_P5 USB30_TX_N5 C302 1 USB30_TX_P5 C301 1 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K USB30_TX_C_N5 USB30_TX_C_P5 R1159 1 @ R1158 1 @ 2 0_0402_5% USB20_N3_R 2 0_0402_5% USB20_P3_R @ 2 2 @ 2 2 0_0402_5% USB30_RX_R_N5 0_0402_5% USB30_RX_R_P5 0_0402_5% USB30_TX_R_N5 0_0402_5% USB30_TX_R_P5 1 2 3 4 5 6 7 8 9 3 I/O2 VBUS DD+ GND_1 SSRXSSRX+ GND_2 SSTXSSTX+ 4 4 USB30_RX_R_P5 L71 USB30_TX_C_N5 2 GND_6 GND_5 GND_4 GND_3 13 12 11 10 USB30_TX_C_P5 3 2 1 3 4 1 USB30_TX_R_N5 4 USB30_TX_R_P5 1 USB20_N3_R 4 USB20_P3_R WCM-2012-900T_4P L73 USB20_N3 2 USB20_P3 3 ME@ @ I/O4 3 1 USB30_RX_R_N5 WCM-2012-900T_4P SANTA_370300-1 USB20_N3_R 1 3 8 D25 2 6 2 1 3 4 WCM-2012-900T_4P 2 GND VDD I/O1 I/O3 5 +5VALW 4 USB20_P3_R 4 4 1 Issued Date Title LC Future Center Secret Data Security Classification AZC099-04S.R7G_SOT23-6 2012/07/01 Deciphered Date USB 3.0 PORT (LEFT) 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 A B C D Sheet E 49 of Rev 1.0 69 5 4 3 2 1 +5VS +5V_CHGUSB JSB1 Touch panel JTHP R2 +5VS 2 1 0_0603_5% 1 2 3 4 5 6 7 8 USB20_N8_THP USB20_P8_THP <18> <18> D R1168 1 R1169 1 USB20_N8 USB20_P8 USB20_N8 USB20_P8 2 0_0402_5% 2 0_0402_5% USB20_N8_THP USB20_P8_THP L75 USB20_N8 2 USB20_P8 3 ME@ 1 2 3 4 5 6 G7 G8 USB20_P1_C USB20_N1_C 0.1U_0402_16V4Z 1 @ C1099 2 EXT_MIC_L EXT_MIC_R MIC_JD HP_OUTR HP_OUTL SPDIF_OUT PLUG_IN ACES_85205-06001 2 1 3 4 1 USB20_N8_THP 4 USB20_P8_THP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 <45> <45> <45> <45> <45> WCM-2012-900T_4P MIC_JD HP_OUTR HP_OUTL SPDIF_OUT PLUG_IN 2 ME@ D 19 20 ACES_50505-0184N-001 1 @ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 G1 18 G2 C1100 220P_0402_25V8J For ESD Sleep & Charge Right side USB Charger Port (USB_Port5, near JMIC1) +5VALW Genesys GL887 C1097 0.01U_0402_16V7K C1096 10U_0603_6.3V6M C 1 2 CHG_MOD2 1 Close to U8 Pin 1 2 +5VALW U8 2 50 mil R1553 10K_0402_5% <18> USB20_P1 <18> USB20_N1 1 USB20_P1 3 USB20_N1 2 887T@ 50 mil P5V VBUS_OUT DP_UP DP_DOWN DM_UP 1 DM_DOWN R1555 CHG_MOD1 2 For TI charger USB_CH CHG_MOD2 CHG_MOD1 CHG_MOD0 <46> USB_CH 1 0_0402_5% ILIM_SEL2 ILIM_SEL1 ILIM_SEL0 S3 1 0 R1559 10K_0402_5% @ PSW_EN CHG_MOD2 CHG_MOD1 CHG_MOD0 BC_CON ALARM 10 USB20_P1_C 11 USB20_N1_C @ PAD 9 * USB_OC0# R1560 1 2 0_0402_5% 1 R1561 1 CHG_MOD 210K_0402_5% 2 G 3 @ 4 16 15 NC2 NC1 NC0 GND GND_PAD CHG_MOD1 CHG_MOD0 Charge Mode C 0 0 Charge Disable 0 0 0 Power down mode 0 1 0 CDP mode 0 0 1 Auto 2A mode without wake up function 0 1 1 1 0 0 DCP mode 1 0 1 Apple 2A mode 1 1 0 Auto mode (DCP and Apple 1A) 1 1 1 Auto mode (DCP and Apple 2A) * Apple 1A mode TI TPS2543 CHG_MOD2 13 CHG_MOD2 0 20120902 VA2 Change to OC0# T182 Charge Mode CHG_MOD1 * CHG_MOD0 X 1 0 BC1.2 SDP mode 0 1 1 Auto 2A mode with wake up function 1 0 0 1 0 1 1 1 1 ILIM_SEL2 BC1.2 DCP mode Apple 2A mode BC1.2 CDP mode with Smart CDP MODE <18> * 14 17 DCH OUT held low /Data lines disconnected 0 0 0 X 1 1 1 1 CDP Data connected and Load detect active 1 1 1 0 SDP2 Data connected SDP1 Data connected 1 1 0 X 0 1 0 X SDP1 Data connected 1 0 0 X DCP_Short Stay in DCP BC1.2 Charging mode 1 0 1 X DCP_Divider Stay in DCP Divider1 Charging mode 0 1 1 X DCP_Auto Data disconnected and Load detect active 0 0 1 X DCP_Auto Data disconnected and Load detect active GL887-OCGC_QFN16_3X3 CHG_MOD2 B <54> 5 6 7 8 12 Genesys GL887T CHG_MOD0 +5VALW S0 1 CHG_MOD R1558 2 887@ 1 0_0402_5% 2 Mode * +5V_CHGUSB +5VALW CHG_MOD1 U8 D B 1 Q122 S 2N7002KW_SOT323-3 @ 2 C1098 0.1U_0402_16V4Z TI@ * TPS2546RTER_QFN16_4X4 Close to U8 @ +5VALW 1 R1551 10K_0402_5% TI@ 2 ILIM_SEL2 1 R1585 10K_0402_5% @ 2 ILIM_SEL1 1 R1586 10K_0402_5% @ 2 ILIM_SEL0 R1584 1 10K_0402_5% TI@ R1552 1 20K_0402_5% 2 R1554 1 @ 20K_0402_5% 2 2 Ext. MIC +MIC1_VREFO_L A A 2 2 Remove Diode (DA1, DA2) RA1623 2.2K_0402_5% <45> MIC1_R <45> MIC1_L 5 Issued Date RA1634 2 1 1K_0402_5% EXT_MIC_R RA1633 2 1 1K_0402_5% EXT_MIC_L 4 Title LC Future Center Secret Data Security Classification 1 1 RA1622 2.2K_0402_5% 2012/07/01 2014/07/01 Deciphered Date AUDIO-B CONN/ USB CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 3 2 1 Sheet 50 of Rev 1.0 69 BATT CHARGE/LOW LED White LED2 Amber <46> BATT_LOW_LED# <46> BATT_CHG_LED# 2 BATT_LOW_LED# R1012 1 3 470_0402_5% White 2 BATT_CHG_LED# 1 R1014 1 +5VALW 2 LION LED SC500007F0J 470_0402_5% 12-22-S2ST3D-C30-2C_WHI-ORG <46> White HDD LED CapsLK LED PWR LED NUM_LED# LION LED:SC500004Y0J LED5 1 2 2 300_0402_5% 1 R1563 +5VS 12-21SYGCS530-E1S155TR8_W LED3 <46,52> 1 PWR_LED# 2 2 12-21SYGCS530-E1S155TR8_W 2012-0507 --> Change LED1 to T/P LED TouchPad_LED R1621 1 0_0402_5% TP_LED# 2 LED1 1 HDD_LED#_R 2 2 12-21SYGCS530-E1S155TR8_W HDD_LED# @ 2 R1322 1 +5VS 300_0402_5% HDD_LED#_R LED4 <46> 1 CAPS_LED# 2 2 12-21SYGCS530-E1S155TR8_W R1323 1 +5VS 300_0402_5% LED3 POWER LED2 BATTERY LED1 LED4 T/P CapsLK Screw Hole CPU and GPU: H_3P8X 6 H12 HOLEA H11 H14 HOLEA HOLEA H15 HOLEA 1 1 1 H10 HOLEA 1 1 H13 HOLEA MIN PCIE: H_3P3 X 1 B: H_3P8X 3 1 C: H_3P8X 3 CPU E: H_3P3X 1 GPU ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1 A: H_2P8X 8 FD4 1 FD3 1 FD2 1 FD1 1 1 H29 HOLEA H34 HOLEA H35 HOLEA H36 HOLEA H37 HOLEA Issued Date 2012/07/01 1 1 1 1 1 1 1 H20 H21 HOLEAHOLEA 1 1 H_2P8X4P0NX1 Title LC Future Center Secret Data Security Classification 1 H28 HOLEA 1 H24 H25 HOLEAHOLEA H_3P0X9 1 1 PCB Fedical Mark PAD H26 HOLEA H33 H32 HOLEA HOLEA H23 HOLEA E: H_3P3X 3 H16 HOLEA H31 HOLEA 1 H30 HOLEA 1 <13> R1622 1 0_0402_5% +5VALW 1 <46> R1013 1 300_0402_5% Deciphered Date 2014/07/01 LED THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 Sheet 51 of Rev 1.0 69 ON/OFF switch SW 2 +3VALW @ 1 J7 R1117 100K_0402_5% 2 1 R1531 SHORT PADS @ 1 R1116 100K_0402_5% NO51ON@ SMT1-05_4P 1 2 4 6 5 2 Bottom Side +3VL 3 2 1 Power Button TOP Side Power Button/B link to Function/B Conn. 10pin 2 0_0603_5% D72 For S3.5 NO51ON@ 3 ON/OFF ON/OFF 1 ON/OFFBTN# 2 51_ON# JPW R1 8 7 GND GND <46> 51_ON# <56> +5VALW DAN202UT106_SC70-3 S Q153 2N7002_SOT23-3 <46,51> 2 G R1523 10K_0402_5% PW R_LED# ON/OFFBTN# For +3VL 2 1 C551 6 5 4 3 2 1 ACES_88514-00601-071 100P_0402_50V8J 2 ESD Request EMI REQUEST 1ST = SCA00000E00 2ST = SCA00000R00 R1119 100K_0402_5% R1118 100K_0402_5% 1 NO51ON@ 6 5 4 3 2 1 For S3.5 2 +3VALW 1 @ 2 C552 330P_0402_50V8J 1 1 3 EC_ON 2 EC_ON D 1 <46,59> NOVO_BTN# ME@ @ 1 R1532 2 0_0603_5% D56 <46> 51_ON# ON/OFF NOVO# R19 R28 NOVO# NO51ON@ 1 2 0_0402_5% 1 2 0_0402_5% 2 1 NOVO_BTN# 3 DAN202UT106_SC70-3 NO51ON@ default reserved For S3.5 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ONOFF SW/ PWR-B CONN/ ISPD Size Document Number Custom Date: Y501 NM-A032 Wednesday, March 27, 2013 Sheet 52 of Rev 1.0 69 5 4 3 2 1 D D C C B B A A Compal Secret Data Security Classification Issued Date 2011/07/21 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title NVSR Size C Date: 5 4 3 2 Document Number Rev 1.0 Y501 NM-A032 Wednesday, March 27, 2013 Sheet 1 53 of 69 1 @ RXE1 2 0_0402_5% FB_CLAMP2 GC6@ 1 0_0402_5% RXE3 1 RE46 EXIO_CLK EXIO_CS GC6_EVENT# 2 GC6@ 1 RXE2 0_0402_5% <23,27,54> FB_CLAMP <19,23,54> GC6_EVENT# <19,27,62,63> DGPU_PWROK <14,23,55> DGPU_PWR_EN <14,23> DGPU_HOLD_RST# <14,27> DGPU_GC6_EN <14,63> NVDD_PWR_EN <47> KBL_DET# U80 2 4 3 5 <46> WRST# WRST# KBL_DET# 1 12 FB_CLAMP +3VALW_R 6 7 8 9 10 11 14 15 @ VSS1 VSS2 <46> EXIO_CLK <46> EXIO_CS <19,23,54> GC6_EVENT# CHG_MOD GPIO_DATA GPIO_CLK CYCLE_START RESET# VSTBY2 VSTBY1 GPIO4 GPIO5 GPIO7 GPIO9 GPIO11 GPIO13 GPIO18 GPIO20 GPIO35 GPIO33 GPIO31 GPIO29 GPIO27 GPIO26 GPIO24 GPIO22 GND CHG_MOD EXIO_DATA 25 <50,54> <46> <23,27,54> 2 0_0603_5% EXIO_DATA 24 13 23 21 22 20 19 18 17 16 S_GC6_EN <27,32> S_GC6_EVENT# <32> S_DGPU_PWROK <16,32> S_DGPU_PWR_EN <19,32,55> S_DGPU_RST <16,32> CHG_MOD S_NVDD_PWR_EN CHG_MOD PAD T178 SLI_FB_Clamp FB_clamp_req GPU_PWR_GOOD GPU_PWR_EN PEX REST DGPU_HOLD_RST# @ <19,32> <50,54> For USB charge IT8302FN IT7230BFN-BX-0001_QFN24_4X4 GC6_EVENT# RXE141 2 0_0402_5% S_GC6_EVENT# @ Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 EX IO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 Sheet 54 of Rev 1.0 69 A B C +5VALW to +5VS +5VALW AP4800BGM VGS=10V, ID=9A, Rds=18m ohm VGS=+-25V +3VALW +5VS +3VS U47 1 1 1 2 AP4800BGM-HF 1 C840 10U_0603_6.3V6M 2 1 C841 1U_0603_10V4Z R1474 R1475 @ 470_0603_5% D DS3@ S R1097 100K_0402_5% SUSP SUSP Q148 AO3413_SOT23 3 DS3@ 1 2 C1065 0.1U_0402_16V4Z @ 1 2 2 <10,40,61> Q118 2N7002_SOT23 +0.675VS <32,46,60,61,62> 1 1 @ 2 2 Id=3.2A R1094 22_0603_5% D S S D 2 SUSP# 2 2 1 +5VALW JUMP_43X79 G R1121 100K_0402_5% Q102 2N7002KW_SOT323-3 3 1 @ 1 DS3@ 2 G 1 PM_SLP_SUS# R1448 2 0_0402_5% @ S D PM_SLP_SUS# D 2 G +3V_PCH J11 @ S <15,46> S 2 SUSP G Q100 2N7002KW_SOT323-3 5 G SUSP G Q107A 2N7002KDWH_SOT363-6 Q107B 2N7002KDWH_SOT363-6 4 2 R_short 0_0402_5% @ 1 1 R117 PCH_PWR_EN 1 PCH_PWR_EN PCH_PWR_EN# 1 2 3 <46,57> 1 DS3@ PCH_PWR_EN#_R R60 100K_0402_5% +3VALW 2 R1120 100K_0402_5% R1483 820K_0402_5% 2 +VSB D +3VALW to +3V_PCH +5VALW 2 C843 0.01U_0402_25V7K 1 470K_0402_5% 1 S Q101 2N7002KW_SOT323-3 2 G 2 R1086 3VS_GATE 2 2 3 S @ 2 3 2 SUSP G Q99 2N7002KW_SOT323-3 @ 1 D R_short 0_0402_5% 1 1 D 2 R1484 820K_0402_5% 2 3VS_GATE_R1 +VSB 150K_0402_5% 1 C842 0.01U_0402_25V7K R1089 R1085 5VS_GATE 82K_0402_5% 1 1 R1088 2 1 3 5VS_GATE_R @ 2 2 For ESD request 470_0603_5% 2 10U_0805_10V6K C839 2 10U_0805_10V6K 6 2 @ 1 C838 1U_0603_10V4Z 1 C837 10U_0603_6.3V6M 1 2 3 3 2 AP4800BGM-HF 4 2 1 8 7 6 5 4 1 1 2 3 1 8 7 6 5 1 U46 C836 @ E +3VALW to +3VS AP4800BGM VGS=10V, ID=9A, Rds=18m ohm VGS=+-25V 1 D C1066 0.01U_0402_25V7K For Intel S3 Power Reduction. PCH_PWR_EN#_R 1 PCH_PWR_EN#_R C39 @ 0.1U_0402_16V4Z +3VS +3VS_VGA 2 Q145 AO3413_SOT23 +5VALW 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C42 0.1U_0402_16V4Z 1 C45 +3VL 0.1U_0402_16V4Z 1 C40 R1449 47K_0402_5% C41 C46 1 2 0.1U_0402_16V4Z 1 R1451 DGPU_PWR_EN# 2 2 2 2 1 2 R1452 DGPU_PWR_EN 1 2 G R_short 0_0402_5% Q146 2N7002KW_SOT323-3 R1454 100K_0402_5% +3VS 2012-0419 --> modify +3VS_SLI BOM structure to "SLI@" A DGPU_PWR_EN# 2 S D S 2 G 2N7002KW_SOT323-3 @ Q149 1 1 2 2 C1012 0.1U_0402_10V7K @ 1 S_DGPU_PWR_EN# 2 1 S 1 3 2 R1500 470_0603_5% D 3 1 2 1 2 1 D @ C1063 0.01U_0402_25V7K 2 S 2 G 2N7002KW_SOT323-3 C48 10U_0603_6.3V6M 4 @ Q151 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date DC V TO VS INTERFACE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y501 NM-A032 2 3 2 G R_short 0_0402_5% Q150 2N7002KW_SOT323-3 R1501 100K_0402_5% G 1 R1513 1 C1011 0.1U_0402_10V7K C37 10U_0603_6.3V6M D 2 R1503 S_DGPU_PWR_EN 1 2 10K_0402_5% <19,32,54> 2 1 S 3 C1062 0.1U_0402_16V4Z S_DGPU_PWR_EN# @ +3VS_SLI 1 @ R1502 47K_0402_5% <32> 1 R1450 470_0603_5% Q147 AO3413_SOT23 +5VALW 4 2 2 For ESD request +3VS to +3VS_SLI D 2 1 <14,23,54> 3 2 C1059 0.01U_0402_25V7K @ 2 10K_0402_5% 2 1 @ 2 +3VS 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 C44 C43 +3VALW 2 3 +5VS C1058 0.1U_0402_16V4Z G +5VALW 1 1 +3VS to +3VS_VGA D 1 S 3 1 R1453 2 1 @ 0_0402_5% 通通Power 修修58頁, 反反 LAN_WAKE# 1 LAN_WAKE# 3 40,41,46> B C D E Sheet 55 of Rev 1.0 69 5 4 3 B+_SLI SLI@ 1 D @ 2 2 PQ103 AO6409L_TSOP6 SLI@ 6 4 5 2 1 PC112 0.01U_0402_16V7K 1 1 2 2 PC113 10U_0603_6.3V6M SLI@ SLI@ 2 2 1 2 SLI@ 3 2 1 PR111 200K_0402_1% SLI@ 0.1U_0402_16V4Z PC111 1 2 4 PC110 0.1U_0603_25V7K 2 1 PC109 0.22U_0603_25V7K 1 G SLI@ SLI@ +5VS_SLI PJ102 5 D PR110 200K_0402_1% JUMP_43X79 +5VS S 2 1 2 3 1 1 2 +5VS to +5VS_SLI SLI@ PQ102 AON7403L_DFN8-5 PC104 1000P_0402_50V7K 1 2 @ 4602-Q04C-09R 4P P2.5 JDCIN1 1 1 2 2 B+ PC103 100P_0402_50V8J 3 PC102 100P_0402_50V8J 1 PL101 SMB3025500YA_2P 1 2 1 D PF101 12A_65V_451012MRL 2 APDIN1 2 2 1 APDIN PC101 1000P_0402_50V7K 3 4 1 VIN DC030006J00 4 2 PR113 47K_0402_1% SLI@ 1 1 PR112 SLI@ 47K_0402_1% VIN PC105 0.22U_0603_25V7K 2 LL4148_LL34-2 @ 1 1 2 51ON-3 C @ - JRTC1 + @ PD103 2 1 +RTCBATT RB751V-40_SOD323-2 1 2 +CHGRTC RTC Battery 2 3 VOUT 1 2 PR107 560_0603_5% 1 2 PD104 RB751V-40_SOD323-2 PR109 200_0603_5% APL5156-33DI-TRL_SOT89-3 VIN 2 CHGRTCIN B 1 3.3V PR106 560_0603_5% 1 2 1 @ PU101 B 1 @ MAXEL_ML1220T10 GND PC107 10U_0603_6.3V6M @ 1 2 2 PR108 1 0_0402_5% 2 +CHGRTC SLI_5V_ON# @ PC106 0.1U_0603_25V7K 2 <32> VS @ 1 @ PR105 22K_0402_1% 1 2 2 +3VLP 51_ON# 100K_0402_1% 1 PR104 @ <53> 3 51ON-2 SLI_B+_ON# PR102 68_1206_5% @ PQ101 TP0610K-T1-E3_SOT23-3 PR103 @ 200_0402_1% 1 2 <32> 51ON-1 1 PJ101 @ JUMP_43X39 1 2 1 2 2 PD102 LL4148_LL34-2 2 1 2 BATT+ PR101 68_1206_5% 2 1 @ C 1 PD101 @ PC108 1U_0805_25V6K @ A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date Vin Detector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 5 4 3 2 1 Sheet 56 of Rev 1.0 69 5 4 VMB2 1 PL201 SMB3025500YA_2P 1 2 BATT+ 1 D PC202 0.01U_0402_25V7K 2 For KB930 --> Keep PU1 circuit (Vth = 0.825V) For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205,PR211,PQ201,PR208,PR212 PH1 under CPU botten side : CPU thermal protection at 92+-3 degree C Recovery at 56 +-3 degree C < 34,47,51,59> EC_SMB_DA1 < 34,47,51,59> VL PR227 2 1 PR219 @ 0_0402_5% 2 1 MAINPWON 100K_0402_5% 1 2 PR226 21.5K_0402_1% 1 @ <47,60> PR221 57.6K:90W 82.5K:120W 76.8K:170W <47> PR225 13.7K_0402_1% C 1 2 2 @ 1 2 ADP_OCP_2 1 PR221 @ 57.6K_0402_1% PR224 10K_0402_1% PR220 2 0_0402_5% AD_ID TURBO_V_1 2 6 @ 1 <47> PH201 100K_0402_1%_NCP15WF104F03RC PROCHOT# 2 NTC_V <47> NTC_V_1 OTP_N_002 1 OTP_N_003 3 S 3V--- 90W 1.5V--- 120W 0V--- 170W OT1 TMSNS2 7 4 5 @ OT2 RHYST2 G718TM1U_SOT23-8 2 ADP_OCP_1 G PQ201 @ 2N7002KW_SOT323-3 GND RHYST1 8 2 PR223 10K_0402_1% D 3 VCC TMSNS1 1 2 PR218 1 1 H_PROCHOT# 100K_0402_1% @ <6,47> 2 2 PU201 1 PR231 0_0402_5% +3VS +3VLP PR222 4.42K:90W 9.1K:120W 16.5K:170W 2 PR230 0_0402_5% @ C +3VALW ADP_I 1 BATT_TEMP <47> <47,59> 1 1 2 PR204 10K_0402_5% PC207 0.1U_0603_25V7K 2 1 +3VALW PR222 4.42K_0402_1% 1 2 PR203 6.49K_0402_1% EC_SMB_CK1 2 2 PC201 1000P_0402_50V7K TURBO_V TYCO_1775789-1 @ 2 1 PR202 100_0402_1% 1 EC_SMCA EC_SMDA 2 1 PR201 100_0402_1% D 1 2 3 4 5 6 7 8 9 2 VMB PF201 12A_65V_451012MRL 1 2 JBATT1 1 2 3 4 5 6 7 GND GND 3 <47> 1 PR228 47W@ 100K_0402_5% B B S A PR213 <47> BATT_LEN# 2 1 10K_0402_1% PQ205 D 2N7002KW_SOT323-3 S PC204 1U_0402_6.3V6K 1 D PQ204 2N7002KW_SOT323-3 2 G 3 PR232 0_0402_5% 1 2 PR233 1K_0402_1% 1 2 1 @PR215 @ PR215 0_0402_5% 1 2 +VSBP S PJ201 @ JUMP_43X39 1 2 1 2 +VSB 2 SPOK <47,56> PCH_PWR_EN 1 1 PR207 10K_0402_1% 3 PR212 2 +CHGRTC <60> 100K_0402_1% 1 1 2 1 2 PC206 0.1U_0603_25V7K @ PR214 200K_0402_1% +3VALW 1 PU202A AS393MTR-E1 SO 8P OP +VSBP 2 1 2 +3VL 2 G PC205 0.22U_0603_25V7K D PR216 22K_0402_1% 1 2 PR217 100K_0402_1% 2 1 BATT_OUT <59> 1 2 100K_0402_1% 2 PR211 1 1 - 1 1 PR210 2 P O 3 2 + 3 B+ PQ203 2N7002KW_SOT323-3 8 3 PR206 150K_0402_1% 2 PQ202 TP0610K-T1-E3_SOT23-3 +3VALW 100K_0402_1% PR209 10M_0402_5% 1 PR229 10K_0402_1% 1 2 G PR205 255K_0402_1% 4 2 1 2 2 VMB2 +3VALW PC203 0.01U_0402_25V7K 1 P2 A 2 G Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 5 4 3 2 1 Sheet 57 of Rev 1.0 69 5 4 3 2 1 Charge Option() bit[8]=1 B+ P3 P2 PQ302 AO4423L 1P SO8 PR317 2 1 @ 10K_0603_1% 1 2 3 ACN ACP 21 1 LX_CHG 18 ILIM BTST REGN 1 PR322 PC309 2.2_0603_5% 0.047U_0603_16V7K 1 2 2 1 BST_CHG PD301 RB751V-40_SOD323-2 2 1 17 16 PQ312 AON7702L_DFN8-5 4 2 2 DL_CHG PC324 0.1U_0603_25V7K 1 2 2 1 6 1 CHG 4 2 3 BATT+ B BQ24737_VDD @ ACIN PR329 10K_0402_1% 2 A 1 PR331 2 3 4 5 <47> PACIN 2N7002KDW-2N_SOT363-6 PQ308B 2 PR328 47K_0402_1% ACPRN PR330 10K_0402_1% 1 2 1 1 PC306 0.1U_0603_25V7K 2 1 3 2 1 1 15 14 PR320 10_0603_5% 13 1 2 BM# 11 2 6.8_0603_5% 1 12 PR319 BQ24737_VDD PC308 1U_0603_25V6 PC307 0.1U_0603_25V7K 2 1 2 5 DH_CHG 2 4 PQ307B 2N7002KDW -2N_SOT363-6 4 PL301 PR332 4.7UH_PCMB104E-4R7MS_10A_20% 0.01_2512_1% PC316 10U_0805_25V6K 2 1 1U_0603_25V6 19 SCL 3 5 BATT_OUT B 2ACOFF-1 2 PC315 10U_0805_25V6K 2 1 PHASE PU301 BQ24737RGRR_VQFN20_3P5X3P5 HIDRV PR318 18K_0402_1% 2 1 1SS355_SOD323-2 PD303 4 1 3 2 1 VCC PR313 100K_0402_1% C PACIN PC310 20 PR323 CMPIN CMPOUT TP 2 4.7_1206_5% 10 PR321 10_1206_5% 1 2 PQ308A 2N7002KDW -2N_SOT363-6 1 PQ311 AON7408L_DFN8-5 P2 16251_SN 2 PR312 1 2 147K_0402_1% 1 1 IOUT SDA PC317 0.1U_0603_25V7K 2 1 2 LODRV 9 PD302 1SS355_SOD323-2 2 PC311 GND 7 100P_0603_50V8 8 ACDET 1 3 PR315 @ 2 5 PC305 1 2 PR324 200K_0402_1% PC314 680P_0603_50V7K 2 1 390K_0603_1% ADP_I 6 2 3 PR307 0_0402_5% +3VALW P 2 0.1U_0603_25V7K SRP EC_SMB_CK1 <41,47,51,58> 1 PQ309 DTC115EUA_SC70-3 1 0.1U_0603_25V7K PR316 @ 1 2 4.7M_0603_1% BM 4 ACOFF EC_SMB_DA1 <41,47,51,58> PR306 1 2ACOFF-12 10K_0402_5% <47,59> .1U_0603_25V7K 1 PR310 0_0402_5% 1 2 PR311 0_0402_5% 1 2 1 <47> PC304 2 PC312 2 39.2K_0402_1% PR309 64.9K_0603_1% 1 2 1 PQ306 DTC115EUA_SC70-3 PR308 1 P2-2 3 PQ305B 5 2N7002KDW-2N_SOT363-6 PACIN PR314 @ 2 SRN 2 1 PR305 47K_0402_1% 1 2 <58> VIN 1 BATT_OUT 150K_0402_1% C ACOK 2 1 1 PR304 PQ307A 2N7002KDW -2N_SOT363-6 4 6 2 3 6 PQ305A 2N7002KDW -2N_SOT363-6 2 PC313 +3VALW P 1 2 <60> ACPRN PR303 20K_0402_1% 100K_0402_1% DTC115EUA_SC70-3 PR326 10K_0402_1% 5 1 PQ304 VIN 2 1DISCHG_G-1 1 2 D PR325 47K_0402_1% 1 2 ACN 0.1U_0603_25V7K P2-1 8 7 6 5 DISCHG_G 1 1 ACP 1 2 3 PC318 2200P_0402_50V7K PC303 @ 0.1U_0603_25V7K PC319 4.7U_0805_25V6-K 1 2 2 PC320 4.7U_0805_25V6-K 1 2 1 PQ310 AO4423L 1P SO8 2 3 1 2 CHG_B+ PL302 1UH_PCMB061H-1R0MS_7A_20% 1 2 PC321 4.7U_0805_25V6-K 1 2 PR302 200K_0402_1% 1 2 PC301 0.1U_0603_25V7K 2 1 2 2 3 1 DTA144EUA_SC70-3 4 PC302 2200P_0402_50V7K 1 2 PQ303 PR301 200K_0402_5% PR327 1 2 D 0.01_2512_1% 1 8 7 6 5 PC322 @ 10U_0805_25V6K 1 2 3 4 1 2 3 4 8 7 6 5 VIN PC323 @ 10U_0805_25V6K 1 2 PQ301 AO4423L 1P SO8 12K_0402_1% A For disable pre-charge circuit. Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 5 4 3 2 Sheet 1 58 of Rev 1.0 69 5 4 3 2 1 PJ401 PR401 13K_0402_1% 1 2 2 +3VALW P 2 1 1 +3VALW @ JUMP_43X118 @ +3VL PC410 0.1U_0402_25V6 @ 1 2 PC422 0.1U_0402_25V6 1 PR403 20K_0402_1% 1 2 2 PJ402 2 +5VALW P PC418 1U_0603_10V6K 2 1 PR406 0_0603_5%~D 1 2 D PR411 30K_0402_1% 1 2 @ 2 1 1 +5VALW D JUMP_43X118 PR408 20K_0402_1% 1 2 2 +3VLP B++ 2 PR405 130K_0402_1% VCLK 9 UG_5V VBST2 17 BST_5V 18 SW 1_5V DRVL1 SW1 PL401 4.7UH_VMPI1004AR-4R7M-Z01_10A_20% 1 2 LG_5V PQ404 3 2 1 PC421 1U_0603_10V5K 2 1 B++ AO4456_SO8 PC416 680P_0603_50V7K 2 1SNUB_5V 2 +5VALWP 15 EN1 5V_EN 20 VIN VREG5 13 11 1 PC417 10U_0805_25V6K 2 1 PC415 0.1U_0603_25V7K 1 2 3 2 1 PR410 2.2_0603_5% 1 2 4 3V_EN PC420 10U_0805_25V6K 2 1 4 4 PC411 0.1U_0603_25V7K 2 1 B LG_3V PQ403 AO4712_SO8 1 2 3 2 8 7 6 5 PC412 PR409 680P_0603_50V7K 4.7_1206_5% 2 1 SNUB_3V 2 1 PC409 330U_D2E_6.3VM_R25M + 12 SW2 PL402 3.3UH +-20% PCMB063T-3R3MS 6.5A 2 1 1 5 6 7 8 16 DRVL2 8 C TPS51225CRUKR_QFN20_3X3 DRVH2 DRVH1 VBST1 SW 2_3V 19 @ PC408 330U_D2E_6.3VM_R25M BST_3V 10 1 2 3 PR402 2.2_0603_5% 1 2 PQ402 AO4406AL_SO8 PR412 4.7_1206_5% 2 1 UG_3V PC413 0.1U_0603_25V7K 1 2 14 PC419 2200P_0402_50V7K 2 1 PGOOD 21 5 6 7 8 7 4 +3VALWP PAD PC414 0.1U_0402_25V6 2 1 1 CS1 2 VFB1 VREG3 3 4 CS2 EN2 VO1 <58> SPOK PQ401 AO4466L_SO8 6 VFB2 8 7 6 5 3V_EN PR404 0_0603_5%~D 1 2 C PC404 2200P_0402_50V7K 2 1 PU401 5 1 PC403 4.7U_0805_25V6-K 2 1 1 @ JUMP_43X118 PC402 4.7U_0805_25V6-K 2 1 2 PC401 0.1U_0603_25V7K 2 1 PC405 0.1U_0603_25V7K 2 1 2 FB_5V 1 FB_3V PJ403 B+ PR407 56K_0402_1% 1 B++ VL 1 + 2 B PR414 0_0402_5% 1 5V_EN 2 PR415 0_0402_5% PR413 2.2K_0402_5% 1 2 <47,53> EC_ON PD401 LL4148_LL34-2 1 2 VS 1 PR418 316K_0402_1% 1 2 @ 5 4 1 @ PR416 1M_0402_1% 1 2 PC423 4.7U_0603_6.3V6K @ PD402 LL4148_LL34-2 2 1 PQ405 @ 2N7002KW _SOT323-3 2 VL 3VALWP Imax=7.5A OCP current 8.6A~13.92A TYP MAX H/S Rds(on): 22mohm , 30mohm L/S Rds(on):10.8mohm ,13.6mohm 2 1 PR417 402K_0402_1% A S 1 2 @ PR420 330_0402_5% 2 G 2 PR419 @ 100K_0402_5% D 3 1 <47,58> MAINPW ON Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 3 5VALWP Imax=10A OCP current 11.5~19.5A TYP MAX H/S Rds(on):22mohm , 30mohm L/S Rds(on):10.8mohm , 13.6mohm 2 3VALWP/5VALWP Size Document Number Custom Date: Y510 NM-A032 Wednesday, March 27, 2013 Sheet 1 59 of Rev 1.0 69 A C VIN_0.675V 2 PU501 VTT VIN_1.35V 1 20 19 VLDOIN BST_1.35V 18 BOOT PHASE LGATE PAD VTTGND VDDP 21 1 2 PJ501 1 +1.35V JUMP_43X118 PJ502 1 2 1 2 +1.35VP 2 +0.675VSP 2 1 1 +0.675VS JUMP_43X39 VTTSNS_0.675V 3 VTTREF_0.675V VDDQ_1.35V +1.35VP 1 4 5 7 6 2 FB S3 S5 TON FB_1.35V +3VS PR531 0_0402_5% 2 1 PR532 10K_0402_5% 2 1 S3_1.35V <47> VDDQ_PGOOD 2 VDDQ 8 PC509 1U_0603_10V6K 10 PC508 1U_0603_10V6K VTTREF 9 VDD GND RT8207MZQW _W QFN20_3X3 S5_1.35V 11 1 1 PQ502 SISA12DN-T1-GE3 VDD_1.35V CS VTTSNS TON_1.35V VDDP_1.35V 12 PR502 5.1_0603_5% 1 2 2 1 2 3 +5VALW 13 PGND PGOOD +5VALW 2 2 1SNB_1.35V 2 2 PR503 20.5K_0402_1% 1 2 CS_1.35V 4 PC507 680P_0603_50V7K PC506 + 14 PR501 4.7_1206_5% 330U_D2_2.5VY_R15M 1 17 16 1 2 3 1 +1.35VP 15 +0.675VSP 2 5 1 DL_1.35V UGATE 5 4 PQ501 SIS472DN-T1-GE3 DH_1.35V +1.35VP LX_1.35V 1 2 PC505 4.7U_0805_25V6-K 1 PC504 10U_0805_25V6K 2 1 PC503 2200P_0402_50V7K 2 1 PC502 0.1U_0402_25V6 2 1 2 PR505 0_0402_5% 1 2 1 PL502 2.2UH_VMPI0703AR-2R2M-Z01_8A_20% D PR504 2.2_0603_5% 1 2 PC515 10U_0805_6.3VAM PC510 0.22U_0402_10V6K 1 2 B+_1.35V PC501 68P_0402_50V8J B+ B PC514 10U_0805_6.3VAM A PL501 HCB1608KF-121T30_0603 1 2 PC513 0.033U_0402_16V7K PR507 8.06K_0402_1% 1 2 PC525 100P_0402_50V8J 1 2 PR510 10K_0402_1% 1 2 <47> 3 @ PC518 <61,62> SUSP#_PWR 0.1U_0402_10V7K PR514 0_0402_5% 1 2 PR540 @ 0_0402_5% 1 2 1 SUSP# 2 2 <32,47,56,62,63> 2 PR519 0_0402_5% PR516 100K +-1% 0402 2 1 1 1 PR506 887K_0402_1% 2 B+_1.35V1 2 +1.35VP @ PC517 0.1U_0402_10V7K SYSON 3 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 1.35VP/0.675VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 A B C D Sheet 60 of Rev 1.0 69 A B C D RF DRVL 8 1 7 +5VALW 6 11 PC542 1U_0603_10V6K PQ505 TPS51212DSCR_SON10_3X3 4 1 1 3 2 1 AON6504_POW ERDFN56-8-5 1 PC539 470P_0603_50V7K 2 PC538 2 1 PC537 2 1 2 +1.5VSP_VGA 1 + 2 V5IN 2 1 SW VFB PL503 1UH_PCMB063T-1R0MS_12A_20% PC58 0.1U_0402_10V7K EN MDV1525URH_PDFN33-8-5 PC56 220U_B2_6.3VM_R15M DRVH 10 9 @ TRIP TP 470K_0402_1% 1 PR527 2 1 PR526 2 75K_0402_1% 5 PC530 @ .1U_0402_16V7K 2 1 4 VBST 1 @ 3 PGOOD PC526 PR521 680P_0603_50V7K 4.7_1206_5% 2 1SNUB_1.5V2 1 2 @ SUSP# PU502 1 PR524 0_0402_5% 1 2 PR523 1M_0402_1% 1 2 @ <32,47,57,61,62,63> PR529 PC529 2.2_0603_5% 0.22U_0603_16V7K 1 2BST_1.5VSP_VGA-1 1 2 B+ @ 3 2 1 PR533 0_0402_5% 1 2 2200P_0402_50V7K 4 5 FBVDDQ_PW R_EN 1 <27> 2 1 0.1U_0402_25V6 PQ504 PD502 RB751V-40_SOD323-2 1 2 PC536 10U_0805_25V6K 2 1 5 PC528 10U_0805_25V6K 2 1 PJ503 JUMP_43X118 2 1 2 1 PR525 0_0402_5% 1 2 2 PR518 11.5K_0402_1% <25> VDDQ_SENSE 2 2 PR517 10K_0402_1% +1.5VSP_VGA PJ504 2 2 @ +5VS 1 1 JUMP_43X118 +3VALW 1 JUMP_43X118 EN 1 FB VIN 2 2 PR522 39.2K_0402_1% 9 APL5912-KAC-TRL_SO8 VFB=0.8V Vo=VFB*(1+PR522/PR539) PC548 0.01U_0402_25V7K 22U_0805_6.3V6M 8 PR520 20K_0402_1% 1 PC545 .1U_0603_25V7K 2 1 2 EN_1.5VSP 1 +1.5VSP 3 1 2 0_0402_5% 4 PC547 2 1 VOUT 1 VIN VOUT 2 POK PR535 1 +1.5VS 1 PC546 4.7U_0805_6.3V6K 1 <32,47,56,61,62,63> SUSP# 1 1 7 0_0402_5% 5 2 2 @ 2 PR539 44.2K_0402_1% 2 SUSP#_PWR 2 PU504 <60,61,62> PJ505 2 PC549 1U_0402_6.3V6K PR536 0_0402_5% @ PR538 1 2 2 1 S 3 +1.5VSP 2 @ GND 3 PQ503 @ 2N7002KW _SOT323-3 PJ508 JUMP_43X79 2 +5VS VCNTL <60,62> SUSP#_PW R D 2 G <34> SUSP @ 1 1 SUSP#_PW R PR534 0_0402_5% 6 2 PR537 @ 100K_0402_5% 3 1 1 +3VL 2 +1.5VS_VGA 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. A B C +1.5VS_VGA/+1.5VS Size Document Number Custom Date: Y510 NM-A032 Wednesday, March 27, 2013 D Sheet 61 of Rev 1.0 69 5 4 3 2 1 2 +3VS 1 PR703 10K_0402_5% PR715 0_0402_5% 2 1 4 PC703 .1U_0402_16V7K 1 2 PC708 22U_0805_6.3V6M 1 2 PC707 22U_0805_6.3V6M 1 2 +1.05VS_VCCPP PJ701 2 @ 2 +1.05VS 1 1 JUMP_43X118 PR706 2 1 1 VFB=0.6V Vo=VFB*(1+PR706/PR705) PC706 22U_0805_6.3V6M 2 1 1 7 11 SY8036LDBC_DFN10_3X3 2 2 PC701 .1U_0402_16V7K 6 2 FB 1 SVIN EN +1.05VS_VCCPP 3 PC705 22U_0805_6.3V6M LX 1 PVIN 2 PR704 4.7_1206_5% LX 1 1 @ 1 PR702 @ 47K_0402_5% PL701 S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A 1 2 PC704 680P_0603_50V7K SUS_VCCP 5 PC718 1U_0402_16V6K PR718 0_0402_5% 1 2 8 PVIN 2 @ PR717 0_0402_5% 1 2 1 PR716 10_0402_5% 2 SUSP# <60,61> SUSP#_PWR <47> 2 @ PR701 0_0402_5% 1 2 1 <32,47,56,61,62,63> 2 2 9 LX 10 PG 2 SS 2 TP 1 PU701 2 1 +5VALW D PC702 PC717 22U_0805_6.3V6M 22U_0805_6.3V6M 1 PJ702 @ JUMP_43X118 1 D 75K_0402_1% PR705 100K_0402_1% 2 1 C 2 C PC709 22P_0402_50V8J 2 +3VS SY8032ABC_SOT23-6 FB=0.6Volt 2 PD701 RB751V-40_SOD323-2 1 2 PR709 EN_1.05VMP 2 2 1 1 +1.05VS_VGA @ JUMP_43X79 PR711 100K_0402_1% 2 2 2 0_0402_5% PC715 @ 0.1U_0402_10V7K 1 @ SUSP# +1.05VSP_VGA 1.05VMP_FB PR710 1M_0402_5% PR712 <32,47,56,61,62,63> B PJ704 1 2 0_0402_5% 1 1 2 DGPU_PW ROK 1 <19,27,55,64> PR708 75K_0402_1% PC714 22U_0805_6.3VAM 1 1 EN +1.05VSP_VGA 2 FB 2 1 GND PL702 1UH_PH041H-1R0MS_3.8A_20% 1 2 1.05VMP_LX 2 PG 3 PC713 22U_0805_6.3VAM 6 LX 1 5 PC710 22U_0805_6.3VAM IN PC711 68P_0402_50V8J 2 1 2 1 JUMP_43X39 @ PC716 22U_0805_6.3VAM B 4 1.05VMP_VIN 1 1 1 2 1 1 2 2 2 2 PU702 PJ703 +3VALW PC712 PR707 680P_0603_50V7K 4.7_1206_5% PR714 0_0402_5% 2 1 1 PR713 10K_0402_5% A A Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 2 +1.05VS/+1.05VS_VGA Size Document Number Custom Date: Y510 NM-A032 Wednesday, March 27, 2013 Sheet 1 62 of Rev 1.0 69 A PC814 4.7U_0603_6.3V6M 2 1 PC834 10U_0805_25V6K 1 PC833 10U_0805_25V6K 2 1 + 2 PC837 330U_D2_2V_Y + 2 @ PC835 680P_0402_50V7K 2 1 PVCC_VGA 2 1 PR811 2 0_0402_5% +5VS 20 +VGA_B+ PC847 0.22U_0603_10V7K 2 BOOT2_2_VGA 1 1 PC843 10U_0805_25V6K 2 PC842 10U_0805_25V6K 1 2 1 PC841 2200P_0402_50V7K 4 2 1 UGATE2_2_VGA 3 2 1 PR817 0_0603_5% 2 1 2 PR818 0_0402_5% 2 1 PC840 0.1U_0402_25V6 5 BST2 19 3 PQ803 FDMS7698 2.2_0402_5% +5VS 1 PL804 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 2 3 2 1 PQ804 FDMC0310AS PQ807 FDMC0310AS 2 10K_0402_5% +3VS 1 3 2 1 PR833 @ 2.2_0402_5% + 2 1 + 2 PC844 680P_0402_50V7K 2 @ 1 PC846 330U_D2_2V_Y 0_0402_5% 1 4 1SNUB2_VGA 2 @ PR819 4.7_1206_5% 4 LGATE2_VGA PC845 330U_D2_2V_Y 1 5 +VGA_CORE 5 PHASE2_VGA PR813 2 1 PC836 330U_D2_2V_Y 1SNUB1_VGA 2 PQ806 FDMC0310AS 1 2 1 1 5 3 2 1 PQ802 FDMC0310AS 18 17 16 VCC_VGA 5.9K_0402_1% 1 PR812 2 N14P-GS 25W Ipeak=36A Imax=25A Iocp=64.8A Fsw=450KHz bulk cap 330uF 9m *3 2 2 1 22 21 BOOT2_VGA PR814 2 +VGA_CORE PC839 4.7U_0603_10V6K 23 PR816 10K_0402_5% +3VS 2 1 VREF 1 2 PH801 100K_0402_1%_NCP15WF104F03RC 2 1 Thermistor near MOSFET trigger point 97 degree C. 2 1 PC831 0.1U_0402_25V6 5 3 2 1 5 3 2 1 1 4 2 PHASE1_VGA HG1 PQ801 FDMS7698 24 UGATE2_VGA <19,27,55,63> DGPU_PWROK PR815 2 1 @ PR820 4.7_1206_5% BST1 EN HG2 2 PH2 PC832 2200P_0402_50V7K 2 1 2 BOOT1_VGA 2 2 0_0402_5% EN_VGA 1 PR802 3 2 10K_0402_5% 1 PR804 PSI_VGA 5 LG2 COMP PR810 82K_0402_1% PC849 .1U_0402_16V7K PSI VID VIDBUF FB 3 4 4 2 0_0402_5% 1 PR801 6 PVCC PGOOD 12 FBRTN PC848 1U_0402_10V6K 2FB2_VGA1 PC851 100P_0402_50V8J 11 LG1 B+ PL803 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 2 PR834 @ 2.2_0402_5% NCP81172MNTWG_QFN24_4X4 PGND FS VCC 9 15 1 FB_VGA 10P_0402_50V8J 1 2 COMP_VGA PL801 HCB2012KF-121T50_0805 1 2 PL802 HCB2012KF-121T50_0805 1 2 UGATE1_2_VGA 4 UGATE1_VGA PH1 TALERT# FS 4 PR821 PC838 0_0603_5% 0.22U_0603_10V7K 2 1BOOT1_2_VGA 1 2 PR822 0_0402_5% 2 1 LGATE1_VGA PU801 VREF <14> PR832 100K_0402_5% @ PC855 .1U_0402_16V7K 1 2 REFIN 14 PC850 NVDD_PWR_EN 1 DPRSLPVR_VGA NVVDD PWM_VID 8 10 PC852 PR809 47P_0402_50V8J 51_0402_1% 1 2FB1_VGA1 2 PR808 10K_0402_1% 1 2 VCC_SEN N14P-GT 35W Ipeak=50A Imax=35A Iocp=64.8A Fsw=450KHz bulk cap 330uF 9m *5 PR803 30K_0402_1% 1 2 2 2 1 34K_0402_1% VSS_SEN 0_0402_5% 7 TSNS 2 1 PC856 2200P_0402_50V7K VREF PR805 GND 1 PR807 PC854 2 0.01U_0603_50V7K 25 1 2 PC853 1000P_0402_50V7K PR829 2K_0402_1% 2 1 PR826 18K_0402_1% 2 1 13 1 0_0402_5% 2 PD801 RB751V-40_SOD323-2 2 1 1 PC813 4.7U_0603_6.3V6M 2 1 VREF PR828 @ PC859 5.1K_0402_1% 2 1 2700P_0402_50V7-K PR823 GPU_VID 20K_0402_1% 2 1VIDBUF D S PR806 1 PR831 10K_0402_5% <23> 1 PR824 20K_0402_1% 2 1 2 PR805 = 34K ==>Fsw = 450KHz @ 1 2 1 @ PC858 10P_0402_50V8J 2 1 PR825 0_0402_5% 2 VCCSENSE_VGA @ PC828 4.7U_0603_6.3V6M @ PC827 4.7U_0603_6.3V6M 2 1 @ PC826 4.7U_0603_6.3V6M 2 1 PC825 4.7U_0603_6.3V6M 2 1 PC824 4.7U_0603_6.3V6M 2 1 PC823 4.7U_0603_6.3V6M 2 1 @ G PQ805 2N7002KW_SOT323-3 3 @ <24> @ +3VS_VGA PC822 4.7U_0603_6.3V6M 2 1 PC821 4.7U_0603_6.3V6M 2 1 PC820 4.7U_0603_6.3V6M 2 1 2 VSSSENSE_VGA @ <23> PR830 0_0402_5% 2 1 PR827 100K_0402_1% 2 1 <24> PC812 4.7U_0603_6.3V6M 2 1 PC811 4.7U_0603_6.3V6M 2 1 PC810 4.7U_0603_6.3V6M 2 1 PC809 4.7U_0603_6.3V6M 2 1 PC808 4.7U_0603_6.3V6M 2 1 PC807 4.7U_0603_6.3V6M 2 1 PC806 4.7U_0603_6.3V6M 2 1 PC805 4.7U_0603_6.3V6M 2 1 PC804 4.7U_0603_6.3V6M 2 1 @ +VGA_B+ PC818 0.1U_0402_10V7K PC802 4.7U_0603_6.3V6M 2 1 PC803 4.7U_0603_6.3V6M 2 1 PC817 0.1U_0402_10V7K 2 1 1 PC819 4.7U_0603_6.3V6M 2 1 2 2 D +3VS Near VGA Core PC830 47U_0805_6.3V6M 1 PC829 22U_0805_6.3V6M 2 1 +VGA_CORE C GB4-128 package Under VGA Core PC816 0.1U_0402_10V7K 2 1 1 2 1 2 PC815 0.1U_0402_10V7K 2 1 1 PC801 4.7U_0603_6.3V6M 2 1 +VGA_CORE B 4 Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 A B C D Sheet 63 of Rev 1.0 69 5 4 3 2 1 D D 1 2 47W@ CSREF <66> CSP2 2 @ PR907 20K_0402_1% 1 PR910 5.76K_0402_1% 2 1 PR911 5.76K_0402_1% 2 1 2 1 2 PR919 7.5K_0402_1% 28 29 30 31 32 33 34 35 36 VSN_2 37 PC916 2200P_0402_50V7K VSP 1 2 3 4 5 6 7 8 9 PR923 0_0402_5% 2 <47> <47> VR_ON VR_HOT# PR926 0_0402_5% 1 2 1 2 PR927 0_0402_5% 2 CSP2 18 17 16 15 14 13 12 11 10 HG3 SW3 LG3 PVCC PGND LG1 SW1 HG1 BST1 HG3 Mount for 37W <66> LG3 <66> LG1 <66> HG1 <66> SW3 PC908 1 2 <66> PR951 0_0402_5% 1 2 2.2U_0603_10V7K SW1 +5VALW <66> B PR916 PC909 2.2_0603_5% 0.22U_0402_10V6K 1 2 1 2 PR928 45.3K_0402_1% 1 2 TSENSE PC910 .1U_0402_16V7K A <9> VR_SVID_ALRT# VR_SVID_CLK 1 2 PR935 0_0402_5% 1 2 PR936 0_0402_5% 1 2 PR937 0_0402_5% 2 1 1 1 2 2 Place close to phase 2 MOSFET A VR_SVID_DAT_1 VR_SVID_ALRT#_1 VR_SVID_CLK_1 +3VS <9> VR_SVID_DAT VGATE <9> PC918 .1U_0402_16V7K PR930 1.91K +-1% 0402 PR931 0_0402_5% 1 1 2 PR932 54.9_0402_1% 1 2 PR933 75_0402_1% 2 1 PR934 130_0402_1% 1 2 2 +VCCIO_OUT PR938 13K_0402_1% 1 PR929 34.8K_0402_1% PH902 100K_0402_1%_TSM0B104F4251RZ 2 PR925 2_0603_5% PC917 2.2U_0603_10V7K 1 2 1 +5VALW 1 1 27 26 25 24 23 22 21 20 19 GND TSENSE 2 <66> +5VALW <66> PR915 PC907 2.2_0603_5% 0.22U_0402_10V6K 1 2 1 2 2 1 2 PR924 1K_0402_5% 1 2 PC915 1000P_0402_50V7K PR913 5.76K_0402_1% 2 1 37W=43K 47W=66.5K PU901 NCP81103MNTWG_QFN36_5X5 1 VCCSENSE 1 VSN_1 ILIM IOUT VRMP COMP FB DIFFOUT VSN VSP VCC VR_HOT#_1 VR_SVID_DAT_1 VR_SVID_ALRT#_1 VR_SVID_CLK_1 VR_RDY <9> 2 PR922 0_0402_5% 1 VSSSENSE 2 1 <9> SWN1 C NA for 37W 2 PC911 470P_0402_50V8-J 2 1 47W@ B <66> 37W@ CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 DRON PWM2/IMAX BST3 2 PR921 1K_0402_1% PR917 15.4K_0402_1% 47W@ PR912 24.3K_0402_1% 1 2 EN VRHOT# SDIO ALERT# SCLK VR_RDY ROSC TSENSE INT_SEL 1 CSP1 81103_PWM 1 37W=10K 47W=7.5K SWN2 2 1 PC913 10P_0402_50V8J 1 2 43K_0402_1% 37W@ 37W=10K 47W=15.4K 10K_0402_1% 37W@ PC912 0.01U_0402_25V7K 2 1 PC914 390P_0402_50V7K 2 1 2 PR920 49.9_0402_1% <66> PR906 66.5K_0402_1% 1 2 47W@ CSCOMP PR918 1K_0402_1% 10K_0402_1% 37W@ DRON 2 PR917 1 CSSUM IMVP_IMON CPU_B+ PR919 @ PR909 20K_0402_1% CSREF CSP1 1 PR906 CSP2 <47> <66> 47W@ PC906 0.047U_0402_16V7K CSP3 SWN3 PR914 0_0402_5% C CSREF 2 1 2 PC903 1000P_0402_50V7K 1 2 CSP3 @ PR908 20K_0402_1% CSREF 1 PC902 680P_0402_50V7K 1 2 NA for 37W PR905 121K +-1% 0603 1 2 SWN1 PC905 0.047U_0402_16V7K PR904 47W@ 121K +-1% 0603 1 2 SWN2 PC901 1000P_0402_50V7K 1 2 Place close to phase 1 inductir PR901 75K_0402_1% 1 2 PH901 220K_0402_5%_ERTJ0EV224J 2 1 PR902 165K_0402_1% 1 2 PC904 0.047U_0402_16V7K PR903 121K +-1% 0603 1 2 SWN3 <6,15> Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 2014/07/01 Deciphered Date CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Wednesday, March 27, 2013 Date: Y510 NM-A032 5 4 3 2 1 Sheet 64 of Rev 1.0 69 5 4 3 2 1 D D 2 + 2 +VCC_CORE <65> HG3 4 PC931 2200P_0402_50V7K PR942 2.2_0603_1% 2 1 <65> PC930 0.1U_0402_25V6K 2 1 SWN1 PC929 10U_0805_25V6K 2 1 PR941 10_0402_1% PC928 10U_0805_25V6K 2 1 1 1 2 CPU_B+ 2 <65> PC927 10U_0805_25V6K 2 1 CSREF 5 1 @ PC925 220P_0402_50V7K 1 2 2 C <65> SW3 <65> LG3 PQ903 AON6428L_DFN8-5 SNUB_CPU3 2 1 3 2 1 PR943 4.7_1206_5% 2 3 PR944 V3N_CPU 2 1 CSREF 10_0402_1% SWN3 <65> PC935 680P_0402_50V7K 2 5 4 PQ904 AON6504_POWERDFN56-8-5 +VCC_CORE PL903 0.22UH +-20% PCMB104T-R22MS 35A 1 4 1 2 C V1N_CPU 3 2 1 3 2 1 PQ902 AON6504_POWERDFN56-8-5 PR940 4.7_1206_5% 2 1SNUB_CPU1 4 3 PC919 680P_0402_50V7K 5 1 PL902 0.22UH +-20% PCMB104T-R22MS 35A 1 4 2 B+ 1 PC934 68U_25V_M_R0.36 + PC933 68U_25V_M_R0.36 2 1 @ PC926 68P_0402_50V8J LG1 PC924 2200P_0402_50V7K <65> PC923 0.1U_0402_25V6K 2 1 SW1 PQ901 AON6428L_DFN8-5 4 PC922 10U_0805_25V6K 2 1 <65> PR939 2.2_0603_1% 2 1 PL901 FBMA-L11-453215-800LMA90T_1812 1 2 PC921 10U_0805_25V6K 2 1 1 HG1 3 2 1 <65> PC920 10U_0805_25V6K 2 1 5 CPU_B+ PQ905 47W@ AON6428L_DFN8-5 47W@ 47W@ 47W@ PC943 2200P_0402_50V7K PC942 0.1U_0402_25V6K 2 1 PC941 10U_0805_25V6K 2 1 47W@ B 47W@ 4 2 1 PC936 47W@ 0.22U_0402_10V6K PC940 10U_0805_25V6K 2 1 1 BSTA2_1 5 BSTA2 2 B PC939 10U_0805_25V6K 2 1 CPU_B+ PR946 47W@ 2.2_0603_5% 1 2 Mount for 47W 47W@ 2 PR945 1EN_VCORE2 3 2K_0402_1% VCC_VCORE2 4 DRON 1 PWM EN VCC DRVH SW GND 2 47W@ PR948 0_0402_5% 1 DRVL PC937 47W@ 2.2U_0603_10V7K 9 HG2 7 SW2 1 6 5 LG2 PU902 NCP81151MNTBG_DFN8_2X2 +VCC_CORE PL904 0.22UH +-20% PCMB104T-R22MS 35A 3 2 1 47W@ PR947 2.2_0603_1% 2 1 8 1 2 FLAG 2 81103_PWM <65> BST 4 2 PR949 4.7_1206_5% 47W@ 3 47W@ 4 47W@ 2 1 3 2 1 47W@ PQ906 AON6504_POWERDFN56-8-5 SNUB_CPU2 <65> +5VALW 2 5 1 PR950 10_0402_1% 1 V2N_CPU 2 CSREF 47W@ PC938 680P_0402_50V7K 47W@ SWN2 <65> A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU_CORE Size Date: 5 4 3 2 Document Number Y510 NM-A032 Wednesday, March 27, 2013 1 Sheet 65 of Rev 1.0 69 5 4 3 2 1 Based on PDDG rev 0.7 Table 5-1. +VCC_CORE 1 +VCC_CORE 1 + + PC1030 1 + PC1031 1 + PC1032 PC1033 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 2 2 2 2 D 1 2 1 PC1001 10U_0805_6.3VAM 2 PC1002 10U_0805_6.3VAM 1 2 PC1003 10U_0805_6.3VAM 1 2 PC1004 10U_0805_6.3VAM 1 2 @ PC1005 1 + 2 1 PC1011 10U_0805_6.3VAM 2 PC1010 10U_0805_6.3VAM 1 2 PC1009 10U_0805_6.3VAM 1 2 PC1008 10U_0805_6.3VAM 1 2 D @ 10U_0805_6.3VAM 1 1 @ 470U_D2_2VM_R4.5M~D PC1007 10U_0805_6.3VAM 1 2 PC1006 2 + PC1034 470U_D2_2VM_R4.5M~D PC1035 470U_D2_2VM_R4.5M~D 2 10U_0805_6.3VAM @ +VCC_CORE 1 2 C 1 PC1016 22U_0805_6.3VAM 2 1 2 1 PC1017 22U_0805_6.3VAM 2 1 2 2 2 2 2 2 2 2 2 PC1012 22U_0805_6.3VAM C 1 PC1020 22U_0805_6.3VAM 1 PC1024 22U_0805_6.3VAM 1 PC1028 22U_0805_6.3VAM 2 1 PC1013 22U_0805_6.3VAM 1 PC1019 22U_0805_6.3VAM 1 PC1025 22U_0805_6.3VAM 1 PC1027 22U_0805_6.3VAM 2 1 PC1014 22U_0805_6.3VAM 1 PC1018 22U_0805_6.3VAM 1 PC1026 22U_0805_6.3VAM 1 2 1 PC1015 22U_0805_6.3VAM 2 PC1021 22U_0805_6.3VAM 1 PC1023 22U_0805_6.3VAM 2 PC1022 22U_0805_6.3VAM 1 PC1029 22U_0805_6.3VAM 2 PC1036 22U_0805_6.3VAM B B A A Title LC Future Center Secret Data Security Classification Issued Date 2012/07/01 Deciphered Date 2014/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 2 PROCESSOR DECOUPLING Size Document Number Custom Date: Y510 NM-A032 Wednesday, March 27, 2013 Sheet 1 66 of Rev 1.0 69 4 3 D V 2 B7 V PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A# 15 CPU C 6 7 DGPU_PWR_EN (GPU) NVDD_PWR_EN (PCH) (DIS) 8 SUSP#,SUSP V 8-A U3 +1.35V_CPU_VDDQ U46 +5VS U47 +3VS V B VR_ON V 10 11 VGATE PU502, PU702 +1.5VS_VGA +1.05VS_VGA PU503 +1.8VS PU504 +1.5VS Q145, Q147 +3VS_VGA +3VS_SLI B 8-B (DIS) DGPU_PWROK (PWR IC) PU801 +VGA_CORE PU701 +1.05VS VDDQ_PWRGOOD V V V SUSP#,SUSP PU701 +1.05VS_VCCP +1.05VS PU501 +1.35V, +0.675VS 9 V PU901 +VCC_CORE V SYSON V V V PLT_RST# 14 V ON/OFFBTN# ON/OFF B6 H_CPUPWRGD V V EC_ON A4 PCH 5 PBTN_OUT# C PM_DRAM_PWRGD_CPU V A5 SYS_PWROK 10-A 4 PCH_RSMRST# V 51ON# V V B3 V EC V 2 PCH_DPWROK_R V V B4 V PQ101 +3VALW_PCH +5VALW_PCH 3 2 V B7 V VS BATT+ A5 V +3VALW VV B2 B5 V PU401 Q148,+3VALW_PCH Q149,+5VALW_PCH V B1 A3 V V V BATT B+ D V A2 PU301 V BATT MODE A1 VIN 1 2-A PCH_PWR_EN# AC MODE 2 V 5 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 Power Sequence 2014/07/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Y510 NM-A032 Wednesday, March 27, 2013 1 Sheet 67 of Rev 1.0 69 5 4 3 2 1 HW PIR (Product Improve Record) QIQY5 LA-8691P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.2 GERBER-OUT DATE: 2012/03/09 D NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" D For Deep S3 Function C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 HW PIR 2014/07/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Y510 NM-A032 Wednesday, March 27, 2013 1 Sheet 68 of Rev 1.0 69 5 4 3 2 Version change list (P.I.R. List) Item 1 Page 1 of 1 for PWR Reason for change PG# Modify List Date Phase 1 D D 2 3 4 5 6 7 8 C C 9 10 11 12 13 14 B B 15 16 17 A A Issued Date Title LC Future Center Secret Data Security Classification 2012/07/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5 4 3 PWR PIR 2014/07/01 Deciphered Date 2 Size Date: Document Number Y510 NM-A032 Wednesday, March 27, 2013 Sheet 1 69 of Rev 1.0 69 www.s-manuals.com
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