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User Manual: Motherboard Compal NM-A311 ACLU9 - Schematics. Free.
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A
B
C
D
E
1
1
LCFC Confidential
ACLU9 M/B Schematics Document
Intel BayTrail M-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU
2
2
2013-12-22
REV:0.2
3
3
4
4
Title
LC Future Center Secret Data
Security Classification
Issued Date
2013/08/08
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
Cover Page
2013/08/05
D
Size Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
E
1
of
59
A
B
C
D
E
File Name : ACLU9
LCFC confidential
NV (N15V-GM/N15S-GT)
GB2B-64 Package
Page 18~28
Memory BUS (DDR3L)
Dual Channel
PCI-Express
2x Gen2
PCIe Port5
DDR3L-SO-DIMM
Page 14
1.35V DDR3L 1333 MT/s
VRAM 256/128*16
DDR3L*8 4GB/2GB/1GB
UP TO 8G
Page 19~28
1
1
USB 3.0 1x
HDMI
HDMI Conn.
USB 2.0 1x
Page 34
CRT
VGA Conn.
Baytrail M (4.5W)
Page 36
USB 2.0 1x
Page 41
USB Left 2.0 Conn
Page 41
USB 2.0 Port3
eDP Conn
to USB Port
USB Left 3.0 Conn
USB 3.0 Port0
USB 2.0 Port0
USB 2.0 1x
Int. Camera
USB2.0 Port2
to Camera
eDP x2 Lane
USB Right
Int. MIC Conn.
USB2.0 1x
USB2.0 Hub Port1
Page 33
2
2
USB 2.0 1x
SATA HDD
Page 42
SATA Gen2
SATA Port0
SATA ODD
Page 42
BGA-1170
25mm*27mm
SATA Gen1
USB2.0 1x
RTL8111GUL (1G)
RTL8106EUL (10M/100M)
Page 37
Page 16
SD/MMC Conn.
USB Board
Touch Screen
reserved
Page 33
USB 2.0 Port2
USB2.0 1x
NGFF Card
WLAN&BT
PCIe 1x
LAN Realtek
Page 38
Cardreader Realtek
RTS5170USB2.0 Hub Port3
SATA Port1
USB 2.0 Port1
RJ45 Conn.
USB2.0 1x
USB Hub
PCIe 1x
Page 40
PCIe Port0
USB2.0 Hub Port4
PCIe Port1
HD Audio
SPI BUS
Page 4~12
SPI ROM
8MB Page 07
Sub-board ( for 14")
POWER BOARD
3
Codec
Conexant CX20752
Page 43
3
SPK Conn.
Page 43
USB Board
EC
ITE IT8586E-LQFP
Page 44
Sub-board ( for 15")
HP&Mic Combo Conn.
POWER BOARD
USB Board
Touch Pad
Page 45
Int.KBD
Page 45
Thermal Sensor
NCT7718W
Page 39
USB Board
ODD Board
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
A
B
C
D
E
Sheet
2
of
59
A
B
C
D
+5VS
+3VS
Power Plane
B+ +3VALW
+3VL +5VALW
1
2
+3VALW_SOC
+1.0VALW
+1.8VALW
+0.68VS
CPU_CORE
GFX_CORE
S0
O
O
O
O
O
S3
O
O
O
O
X
O
O
O
X
X
S5 S4
Battery only
S5 S4
AC & Battery
don't exist
SIGNAL
STATE
O
X
X
X
X
X
SLP_S1# SLP_S3# SLP_S4#
Full ON
HIGH
HIGH
X
+VALW +VALW_PCH
ON
HIGH
ON
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
USB Port Table
USB 2.0 USB 3.0
X
X
XHCI
+VS
ON
ON
HIGH
ON
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
ON
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
ON
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
ON
OFF
OFF
OFF
EC_SMB_DA1
IT8586E
+3VALW
EC_SMB_CK2
IT8586E
V
EC_SMB_DA2
+3VS
X
BATT
IT8586E
V
Camera
Cardreader
BT(WLAN)
TOUCH PANEL
1
2
3
4
USB HUB
V
X
X
V
+3VS
+3VS
X
X
X
X
V
V
V
+3VS
+3VS
X
X
X
V
EC SM Bus2 address
Device
need to update
Thermal Sensor EMC1403-2
Address
X
+3VALW_PCH
ON
1
2
3
4
5
6
7
8
BOM Structure
AOAC@
OPT@
UMA@
14@
15@
100M@
N15SGT@
N15VGM@
GIGA@
GC6@
TS@
RANKA@
RANKB@
ME@
CD@
@
1
BTO Item
AOAC support part
GPU Part
UMA SKU ID part
For 14" part
For 15" part
100M LAN part
2
N15SGT Part
N15GSM Part
GIGA LAN Part
GPU GC6 Part
Touch Screen part
GPU VRAM RANKA PART
GPU VRAM RANKB PART
Connector
COST DOWN
Not stuff
Hynix VRAM Part
H4T@
M4T@
S4T@@
Device
charger
X
X
0001 011X b
PCH
Port
X
X
Charger
TP
Module
X
+3VGS
Smart Battery
Thermal
Sensor
X
+3VALW
Device
SODIMM
WLAN
WiMAX
X
V
EC SM Bus1 address
4
USB Port (Left Side)
USB HUB
PCIE PORT LIST
VGA
PCH_SMB_CLK
PCH
PCH_SMB_DATA +3VALW_PCH
USB Port (Right Side)
2
SMBUS Control Table
EC_SMB_CK1
USB Port (Left Side)
1
ON
HIGH
SOURCE
0
Clock
LOW
3
1
3
S1(Power On Suspend)
Clock
BOM Structure Table
3 External
USB Port
Port
EHCI1
X
+V
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Full ON
+1.05VS
+1.35V
SIGNAL
STATE
+1.5VS
State
S5 S4/AC Only
E
, X --> Means OFF )
Voltage Rails ( O --> Means ON
Micron VRAM Part
Samsung VRAM Part
3
Discrete GPU
Discrete GPU
WLAN
LAN
PCH SM Bus address
Device
Address
DDR DIMMA
1001 000Xb
Rsvd
4
1001_100xb
VGA
0x9E
Wlan
PCH
0x96
TP
need to update
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
A
B
C
D
E
Sheet
3
of
59
5
4
3
2
1
Port
Port 0 DDI PROCESSOR Pin Names HDMI* Mapping
DDI0_TXP_0
HDMI_TX2+
DDI0_TXN_0
HDMI_TX2DDI0_TXP_1
HDMI_TX1+
DDI0_TXN_1
HDMI_TX1DDI0_TXP_2
HDMI_TX0+
DDI0_TXN_2
HDMI_TX0DDI0_TXP_3
HDMI_CLK+
DDI0_TXP_3
HDMI_CLKDDI0_HPD
HDMI_HPD
DDI0_DDCDATA
DDPB_DAT
DDI0_DDCCLK
DDPB_CLK
UC1C
{34}
{34}
{34}
{34}
{34}
{34}
{34}
{34}
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
HDMI_TX2+
HDMI_TX2HDMI_TX1+
HDMI_TX1HDMI_TX0+
HDMI_TX0HDMI_CLK+
HDMI_CLK-
HDMI_TX2+
HDMI_TX2HDMI_TX1+
HDMI_TX1HDMI_TX0+
HDMI_TX0HDMI_CLK+
HDMI_CLK-
AV3
AV2
AT2
AT3
AR3
AR1
AP3
AP2
AL3
AL1
{34}
D27
HDMI_HPD
C26
C28
{34} DDPB_DATA
{34} DDPB_CLK
B28
C27
B26
D
V1P0Sx
V1P0Sx
V1P0Sx
V1P0Sx
V1P0Sx
V1P0Sx
V1P0Sx
V1P0Sx
DDI0_AUXP V1P0Sx
DDI0_AUXN V1P0Sx
V1P0Sx DDI1_AUXP
V1P0Sx DDI1_AUXN
DDI0_HPD
DDI0_DDCDATA V1P8S
DDI0_DDCCLK V1P8S
DDI0_VDDEN
DDI0_BKLTEN
DDI0_BKLTCTL
2
RC1
402_0402_1%
DDI0_RCOMP_N
DDI0_RCOMP_P
DDI0_RCOMP_P
AK13
AK12
AM14
AM13
AM3
AM2
DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3
V1P8S DDI1_HPD
V1P8S
1
DDI0_RCOMP_N
DDI0_TXP_0 V1P0Sx
DDI0_TXN_0 V1P0Sx
DDI0_TXP_1 V1P0Sx
DDI0_TXN_1 V1P0Sx
DDI0_TXP_2 V1P0Sx
DDI0_TXN_2 V1P0Sx
DDI0_TXP_3 V1P0Sx
DDI0_TXN_3 V1P0Sx
V1P8S
V1P8S
DDI1_DDCDATA
DDI1_DDCCLK
DDI1_VDDEN
V1P8S
V1P8S DDI1_BKLTEN
V1P8S DDI1_BKLTCTL
V1P8S
V1P8S
V1P8S
DDI0_RCOMP
V1P0Sx
DDI0_RCOMP_P V1P0Sx
RESERVED_AM14
RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13
VSS_AH3
RESERVED_VSS2
VSS_AH2
RESERVED_VSS3
RESERVED_AM13
VSS_AM3
RESERVED_VSS0
VSS_AM2
RESERVED_VSS1
VGA_RED
VGA_BLUE
VGA_GREEN
VGA_IREF
VGA_IRTN
C
{12}
GPIO_NC13
change dual mos to one mos
GPIO_NC13
T2
T3
AB3
AB2
Y3
Y2
W3
W1
V2
V3
R3
R1
AD6
AD4
AB9
AB7
Y4
Y6
V4
V6
A29
C29
AB14
B30
C30
RESERVED_T2
RESERVED_T3
RESERVED_AB3
RESERVED_AB2
RESERVED_Y3
RESERVED_Y2
RESERVED_W3
RESERVED_W1
RESERVED_V2
RESERVED_V3
RESERVED_R3
RESERVED_R1
RESERVED_AD6
RESERVED_AD4
RESERVED_AB9
RESERVED_AB7
RESERVED_Y4
RESERVED_Y6
RESERVED_V4
RESERVED_V6
GPIO_S0_NC13
RESERVED_A29
GPIO_S0_NC14_C29 RESERVED_C29
RESERVED_AB14
GPIO_S0_NC12
V1P8S
RESERVED_C30
VVGA_GPIO
VVGA_GPIO
VGA_HSYNC
VGA_VSYNC
VVGA_GPIO
VVGA_GPIO
VGA_DDCCLK
VGA_DDCDATA
RESERVED_T7
RESERVED_T9
RESERVED_AB13
RESERVED_AB12
RESERVED_Y12
RESERVED_Y13
RESERVED_V10
RESERVED_V9
RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14
RESERVED_T13
RESERVED_T6
RESERVED_T4
RESERVED_P14
BAY-TRAIL-M-SOC_FCBGA1170 3 OF 13
V1P8S
RESERVED_D32
RESERVED_N32
RESERVED_J34
RESERVED_K28
RESERVED_F28
RESERVED_F32
RESERVED_D34
RESERVED_J28
RESERVED_D28
RESERVED_M32
RESERVED_F34
REV = 1.15
RESERVED_K34
GPIO_S0_NC26
GPIO_S0_NC25
GPIO_S0_NC24
GPIO_S0_NC23
GPIO_S0_NC22
GPIO_S0_NC21
GPIO_S0_NC20
GPIO_S0_NC18
GPIO_S0_NC17
GPIO_S0_NC16
GPIO_S0_NC15
AG3
AG1
AF3
AF2
AD3
AD2
AC3
AC1
CPU_EDP_TX0+
CPU_EDP_TX0CPU_EDP_TX1+
CPU_EDP_TX1-
AK3
AK2
CPU_EDP_AUX
CPU_EDP_AUX#
K30
P30
G30
N30
J30
M30
CPU_EDP_TX0+ {33}
CPU_EDP_TX0- {33}
CPU_EDP_TX1+ {33}
CPU_EDP_TX1- {33}
EDP
CPU_EDP_AUX {33}
CPU_EDP_AUX# {33}
EDP_HPD
DDI1_DDCDATA
1 @
TP11
DDI1_DDCDATA
Port
Port 1 DDI PROCESSOR Pin Names EDP* Mapping
CPU_EDP_TX0+
DDI1_TXP_0
DDI1_TXN_0
CPU_EDP_TX0DDI1_TXP_1
CPU_EDP_TX1+
CPU_EDP_TX1DDI1_TXN_1
DDI1_AUXP
CPU_EDP_AUX
DDI1_AUXN
CPU_EDP_AUX#
DDI1_HPD
EDP_HPD
{12}
PCH_LCD_VDDEN_Q
PCH_BKLT_EN_Q
PCH_BKLT_CTRL_Q
AH14
AH13
AF14
AF13
AH3
AH2
BA3
AY2
BA1
AW1
AY3
CRT_R
CRT_B
CRT_G
CRT_IREF
BD2
BF2
VGA_HS
VGA_VS
BC1
BC2
VGA_DDC_CLK
VGA_DDC_DAT
CRT_R
CRT_B
CRT_G
D
{36}
{36}
{36}
VGA_HS
VGA_VS
{36}
{36}
VGA_DDC_CLK
VGA_DDC_DAT
+3VS
{36}
{36}
T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6
T4
P14
RPC16
3
4
2
1
2.2K_0404_4P2R_5%
CRT_R
RC5
2
CRT_B
VGA_DDC_CLK
VGA_DDC_DAT
1
150_0402_1%
RC6
2
1
150_0402_1%
CRT_G
RC7
2
1
150_0402_1%
CRT_IREF
RC4
1
2
357_0402_1%
need to change 357 1%
K34
D32
N32
J34
K28
F28
F32
D34
J28
D28
M32
F34
C
XDP
?
@
R4602 change from 10K to 1K,
as Vienna
+1.8VS
+3VS
2
+3VALW
3
4
R4602
1K_0402_1%
2
1
1
RPC24
10K_0404_4P2R_5%
1
D
2
4 S2
QC3
CPU_EDP_HPD
G
QC1A
PJT138K_SOT363-6
S 2N7002KW_SOT323-3
{33}
1
G1
QC1B
PJT138K_SOT363-6
3
2
EDP_HPD
{33}
R4603
100K_0402_5%
0604
2
1 S1
PCH_LCD_VDDEN_Q
D1 6
5 G2
D2 3
PCH_ENVDD
B
B
EDP_HPD
+3VALW
4
3
+3VS
RC972
RPC25
10K_0404_4P2R_5%
2
2
1
2
QC2B
PJT138K_SOT363-6
QC2A
PJT138K_SOT363-6
2
G1
{33}
4 S2
QC198B
PJT138K_SOT363-6
QC198A
PJT138K_SOT363-6
1 S1
PCH_BKLT_CTRL_Q
D1 6
5 G2
D2 3
PCH_EDP_PWM
4 S2
D2 3
{33}
1 S1
G1
D1 6
5 G2
2
RC973
10K_0402_5%
10K_0402_5%
PCH_ENBKL
PCH_BKLT_EN_Q
+3VS
1
1
+1.8VALW
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/03/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
SOC (DDI,EDP)
2013/02/01
Deciphered Date
2
Size Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
4
of
59
5
4
3
DDRA_DQ[63:0]
DDRA_MA[15:0]
{14}
DDRA_DQS[7:0]
{14}
DDRA_DQS#[7:0]
DDRA_DM[7:0]
2
1
{14}
{14}
{14}
UC1A
UC1B
D
Swap Group 2 to Group 3
Swap Group to 6\7\5
{14}
{14}
{14}
C
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15
K45
H47
L41
H44
H50
G53
H49
D50
G52
E52
K48
E51
F47
J51
B49
B50
DDRA_DM0
DDRA_DM1
DDRA_DM3
DDRA_DM2
DDRA_DM4
DDRA_DM6
DDRA_DM7
DDRA_DM5
G36
B36
F38
B42
P51
V42
Y50
Y52
M45
M44
H51
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
{14}
{14}
{14}
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
{14}
DDRA_CS0#
{14}
DDRA_CS1#
{14}
DDRA_CKE0
{14}
DDRA_CKE1
{14}
DDRA_ODT0
K47
K44
D52
P44
P45
C47
D48
F44
E46
T41
P42
DDRA_ODT1
{14}
M50
M48
{14} DDRA_CLK0
{14} DDRA_CLK0#
P50
P48
{14} DDRA_CLK1
{14} DDRA_CLK1#
{14}
P41
DDRA_DRAMRST#
100K_0402_1% 2 RC19
100K_0402_1% 2 RC20
1
1
DRAM_VREF
AF44
ICLK_DRAM_TERMN_0
ICLK_DRAM_TERMN_1
AH42
AF42
AD42
DDR_PWROK
DDR_CORE_PWROK AB42
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
AD44
AF45
AD45
AF40
AF41
AD40
AD41
B
DRAM0_MA_00
DRAM0_MA_11
DRAM0_MA_22
DRAM0_MA_33
DRAM0_MA_44
DRAM0_MA_55
DRAM0_MA_66
DRAM0_MA_77
DRAM0_MA_88
DRAM0_MA_99
DRAM0_MA_1010
DRAM0_MA_1111
DRAM0_MA_1212
DRAM0_MA_1313
DRAM0_MA_1414
DRAM0_MA_1515
DRAM0_DQ_00
DRAM0_DQ_11
DRAM0_DQ_22
DRAM0_DQ_33
DRAM0_DQ_44
DRAM0_DQ_55
DRAM0_DQ_66
DRAM0_DQ_77
DRAM0_DQ_88
DRAM0_DQ09_C32
DRAM0_DQ_1010
DRAM0_DQ_1111
DRAM0_DQ_1212
DRAM0_DQ_1313
DRAM0_DQ_1414
DRAM0_DQ_1515
DRAM0_DQ_1616
DRAM0_DQ_1717
DRAM0_DQ_1818
DRAM0_DQ_1919
DRAM0_DQ_2020
DRAM0_DQ_2121
DRAM0_DQ_2222
DRAM0_DQ_2323
DRAM0_DQ_2424
DRAM0_DQ_2525
DRAM0_DQ_2626
DRAM0_DQ_2727
DRAM0_DQ_2828
DRAM0_DQ_2929
DRAM0_DQ_3030
DRAM0_DQ_3131
DRAM0_DQ_3232
DRAM0_DQ_3333
DRAM0_DQ_3434
DRAM0_DQ_3535
DRAM0_DQ_3636
DRAM0_DQ_3737
DRAM0_DQ_3838
DRAM0_DQ_3939
DRAM0_DQ_4040
DRAM0_DQ_4141
DRAM0_DQ_4242
DRAM0_DQ_4343
DRAM0_DQ_4444
DRAM0_DQ_4545
DRAM0_DQ_4646
DRAM0_DQ_4747
DRAM0_DQ_4848
DRAM0_DQ_4949
DRAM0_DQ_5050
DRAM0_DQ_5151
DRAM0_DQ_5252
DRAM0_DQ_5353
DRAM0_DQ_5454
DRAM0_DQ_5555
DRAM0_DQ_5656
DRAM0_DQ_5757
DRAM0_DQ_5858
DRAM0_DQ_5959
DRAM0_DQ_6060
DRAM0_DQ_6161
DRAM0_DQ_6262
DRAM0_DQ_6363
DRAM0_DM_00
DRAM0_DM_11
DRAM0_DM_22
DRAM0_DM_33
DRAM0_DM_44
DRAM0_DM_55
DRAM0_DM_66
DRAM0_DM_77
DRAM0_RAS
DRAM0_CAS
DRAM0_WE
DRAM0_BS_00
DRAM0_BS_11
DRAM0_BS_22
DRAM0_CS_0
DRAM0_CS_2
DRAM0_CKE_00
RESERVED_D48
DRAM0_CKE_22
RESERVED_E46
DRAM0_ODT_0
DRAM0_ODT_2
DRAM0_CKP_0
DRAM0_CKN_0
DRAM0_CKP_2
DRAM0_CKN_2
DRAM0_DRAMRST
DRAM_VREF
DRAM0_DQSP_00
DRAM0_DQSN_00
DRAM0_DQSP_11
DRAM0_DQSN_11
DRAM0_DQSP_22
DRAM0_DQSN_22
DRAM0_DQSP_33
DRAM0_DQSN_33
DRAM0_DQSP_44
DRAM0_DQSN_44
DRAM0_DQSP_55
DRAM0_DQSN_55
DRAM0_DQSP_66
DRAM0_DQSN_66
DRAM0_DQSP_77
DRAM0_DQSN_77
ICLK_DRAM_TERM_1
ICLK_DRAM_TERMN
ICLK_DRAM_TERMN_AF42
DRAM_VDD_S4_PWROK
DRAM_CORE_PWROK
DRAM_RCOMP_00
DRAM_RCOMP_11
DRAM_RCOMP_22
RESERVED_AF40
RESERVED_AF41
RESERVED_AD40
RESERVED_AD41
M36
J36
P40
M40
P36
N36
K40
K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51
L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51
DDRA_DQS0
DDRA_DQS#0
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7
DDRA_DQS5
DDRA_DQS#5
AY45
BB47
AW41
BB44
BB50
BC53
BB49
BF50
BC52
BE52
AY48
BE51
BD47
BA51
BH49
BH50
Group 0
Group 1
BD38
BH36
BC36
BH42
AT51
AM42
AK50
AK52
Group 3
Swap Group 2 to Group 3
AV45
AV44
BB51
Group 2
AY47
AY44
BF52
AT44
Group 4
AT45
BG47
BE46
BD44
BF48
Group 6
AP41
AT42
Swap Group to 6\7\5
AV50
AV48
Group 7
AT50
AT48
AT41
Group 5
DRAM1_MA_00
DRAM1_MA_11
DRAM1_MA_22
DRAM1_MA_33
DRAM1_MA_44
DRAM1_MA_55
DRAM1_MA_66
DRAM1_MA_77
DRAM1_MA_88
DRAM1_MA_99
DRAM1_MA_1010
DRAM1_MA_1111
DRAM1_MA_1212
DRAM1_MA_1313
DRAM1_MA_1414
DRAM1_MA_1515
DRAM1_DQ_00
DRAM1_DQ_11
DRAM1_DQ_22
DRAM1_DQ_33
DRAM1_DQ_44
DRAM1_DQ_55
DRAM1_DQ_66
DRAM1_DQ_77
DRAM1_DQ_88
DRAM1_DQ_99
DRAM1_DQ_1010
DRAM1_DQ_1111
DRAM1_DQ_1212
DRAM1_DQ_1313
DRAM1_DQ_1414
DRAM1_DQ_1515
DRAM1_DQ_1616
DRAM1_DQ_1717
DRAM1_DQ_1818
DRAM1_DQ_1919
DRAM1_DQ_2020
DRAM1_DQ_2121
DRAM1_DQ_2222
DRAM1_DQ_2323
DRAM1_DQ_2424
DRAM1_DQ_2525
DRAM1_DQ_2626
DRAM1_DQ_2727
DRAM1_DQ_2828
DRAM1_DQ_2929
DRAM1_DQ_3030
DRAM1_DQ_3131
DRAM1_DQ_3232
DRAM1_DQ_3333
DRAM1_DQ_3434
DRAM1_DQ_3535
DRAM1_DQ_3636
DRAM1_DQ_3737
DRAM1_DQ_3838
DRAM1_DQ_3939
DRAM1_DQ_4040
DRAM1_DQ_4141
DRAM1_DQ_4242
DRAM1_DQ_4343
DRAM1_DQ_4444
DRAM1_DQ_4545
DRAM1_DQ_4646
DRAM1_DQ_4747
DRAM1_DQ_4848
DRAM1_DQ_4949
DRAM1_DQ_5050
DRAM1_DQ_5151
DRAM1_DQ_5252
DRAM1_DQ_5353
DRAM1_DQ_5454
DRAM1_DQ_5555
DRAM1_DQ_5656
DRAM1_DQ_5757
DRAM1_DQ_5858
DRAM1_DQ_5959
DRAM1_DQ_6060
DRAM1_DQ_6161
DRAM1_DQ_6262
DRAM1_DQ_6363
DRAM1_DM_00
DRAM1_DM_11
DRAM1_DM_22
DRAM1_DM_33
DRAM1_DM_44
DRAM1_DM_55
DRAM1_DM_66
DRAM1_DM_77
DRAM1_RAS
DRAM1_CAS
DRAM1_WE
DRAM1_BS_00
DRAM1_BS_11
DRAM1_BS_22
DRAM1_CS_0
DRAM1_CS_2
DRAM1_CKE_00
RESERVED_BE46
DRAM1_CKE_22
RESERVED_BF48
DRAM1_ODT_0
DRAM1_ODT_2
DRAM1_CKP_0
DRAM1_CKN_0
DRAM1_CKP_2
DRAM1_CKN_2
DRAM1_DRAMRST
DRAM1_DQSP_00
DRAM1_DQSN_00
DRAM1_DQSP_11
DRAM1_DQSN_11
DRAM1_DQSP_22
DRAM1_DQSN_22
DRAM1_DQSP_33
DRAM1_DQSN_33
DRAM1_DQSP_44
DRAM1_DQSN_44
DRAM1_DQSP_55
DRAM1_DQSN_55
DRAM1_DQSP_66
DRAM1_DQSN_66
DRAM1_DQSP_77
DRAM1_DQSN_77
Swap Group 2 to Group 3
Swap Group to 6\7\5
BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44
BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53
AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51
D
C
BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51
B
1 OF 13
REV = 1.15
2 OF 13
?
BAY-TRAIL-M-SOC_FCBGA1170
+3VALW
+1.35V
REV = 1.15
?
@
4
3
BAY-TRAIL-M-SOC_FCBGA1170
@
RPC13
10K_0404_4P2R_5%
+3VALW
4
3
1
2
+1.35V
+1.35V
0_0402_5%
2
1
2
D
2
5
D
CC18
.1U_0402_10V6-K
G
2N7002KDWH_SOT363-6
S
1
QC16A
{7,44}
CC3
.1U_0402_10V6-K
4
S
D
2
SYS_PWROK
G
1
2
2N7002KDWH_SOT363-6
CC19
.1U_0402_10V6-K
S
A
1
1
2
2
3
4
6
QC5A
QC16B
2
G
VDDQ_PGOOD
1
CC2
.1U_0402_10V6-K
DDR_CORE_PWROK
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
RC29
4.7K_0402_1%
2
0_0402_5%
S
{44,55}
A
RC103
1
CC1
.1U_0402_10V6-K
6
2
2
RC27
162_0402_1%
1
DRAM_VREF
1
2 0_0402_5%
RC26
29.4_0402_1%
1
RC25
23.2_0402_1%
D
5
G
2
2
QC5B
RC28
1
RPC14
10K_0404_4P2R_5%
DDR_PWROK
1
SM_RCOMP_0
RC24
4.7K_0402_1%
2
1
2
1
SM_RCOMP_1
3
1
RC23
SM_RCOMP_2
DDR3 Compensation Signal
WIDTH:20MIL
SPACING: 25MIL
Length: 500Mil
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/03/26
Deciphered Date
SOC (DDR3L)
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
5
of
59
5
4
3
2
1
+1.8VS
MMC1_D0
MMC1_D1
MMC1_D2
MMC1_D3
MMC1_D4
MMC1_D5
MMC1_D6
MMC1_D7
MMC1_RCOMP
BA18
AY20
BD20
BA20
BD18
BC18
1
RC30
402_0402_1%
2
MMC1_CMD
MMC1_RST
SD2_CLK
SD2_D0
SD2_D1
SD2_D2
SD2_D3_CD
SD2_CMD
SATA_RCOMP_DN
AY26
AT28
BD26
AU28
BA26
BC24
AV28
BF22
BD22
RC43 1
2 49.9_0402_1%
SD3_CLK
SD3_D0
SD3_D1
SD3_D2
SD3_D3
SD3_CD#
SD3_CMD
SD3_1P8EN
SD3_PWREN
SDMMC3_RCOMP BF26
RESERVED_VSS7
RESERVED_VSS6
V1P8S
V1P8S
V1P8S
V1P8S
VSS_BB7
VSS_BB5
PCIE_CLKREQ_0
PCIE_CLKREQ_1
PCIE_CLKREQ_2
PCIE_CLKREQ_3
SD3_WP_BD5
PCIE_RCOMP_P_AP14_AP14
PCIE_RCOMP_N_AP13_AP13
RESERVED_BB4
RESERVED_BB3
RESERVED_AV10
RESERVED_AV9
HDA_LPE_RCOMP
VAUD
HDA_RST
VAUD
HDA_SYNC
VAUD
HDA_CLK
VAUD
HDA_SDO
VAUD
HDA_SDI0
VAUD
HDA_SDI1
VAUD
GPIO_S0_SC_14 HDA_DOCKRST
HDA_DOCKEN
GPIO_S0_SC_15
LPE_I2S2_CLK
LPE_I2S2_FRM
LPE_I2S2_DATAOUT
LPE_I2S2_DATAIN
RESERVED_P34
RESERVED_N34
SD3_RCOMP
RESERVED_AK9
RESERVED_AK7
V1P0_S3
BAY-TRAIL-M-SOC_FCBGA1170
@
PROCHOT
AT7
AT6
PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N4
AP12
AP10
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
AP6
AP4
PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3
AP9
AP7
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
2
2
OPT@
1 CC6
1 CC7
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
OPT@
.1U_0402_10V6-K
.1U_0402_10V6-K
2
2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
1 CC104
1 CC103
PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
.1U_0402_10V6-K
.1U_0402_10V6-K
2
2
1 CC105
1 CC106
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
dGPU
+3VS
{19}
{19}
LAN_CLKREQ# RC968
WLAN_CLKREQ#RC969
GPU_CLKREQ#_Q
PCIE_CLKREQ_2#
WLAN_CLKREQ#_Q
LAN_CLKREQ#_Q
AP14
AP13
PCIE_RCOMP_DP
PCIE_RCOMP_DN
BF28
BA30
BC30
BD28
1 10K_0402_5%
1 10K_0402_5%
{40}
{40}
{37}
{37}
{37}
{37}
+1.8VS
LAN
RC958
2.2K_0402_5%
PCIE_RCOMP_DP
PCIE_RCOMP_DN
1
LAN_CLKREQ#_Q
RC31
402_0402_1%
BB4
BB3
AV10
AV9
BF20
BG22
BH20
BJ21
BG20
BG19
BG21
BH18
BG18
2
2
WLAN
BB7
BB5
BG3
BD7
BG5
BE3
BD5
D
10K_0804_8P4R_5%
{19}
{19}
{40}
{40}
8
7
6
5
2 2
B
MMC1_CLK
SDMMC1_RCOMP AY18
SATA_RCOMP_DP
PCIE_TXP_3
PCIE_TXN_3
PCIE_RXP_3
PCIE_RXN_3
AV26
BA24
C
PCIE_RXP_2
PCIE_RXN_2
V1P8S
V1P8S
V1P8S
SATA_RCOMP_P_AU18
SATA_RCOMP_N_AT18
AT22
2 49.9_0402_1%
PCIE_TXP_2
PCIE_TXN_2
SATA_GP0
SATA_GP1
SATA_LED
AU18
AT18
AV20
AU22
AV22
AT20
AY24
AU26
AT26
AU20
RC35 1
ICLK_SATA_TERMP RESERVED_VSS4
ICLK_SATA_TERMN RESERVED_VSS5
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
.1U_0402_10V6-K
.1U_0402_10V6-K
{19}
{19}
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
1
LAN_CLKREQ#_Q
GPU_CLKREQ#_Q 2
3
PCIE_CLKREQ_2#
WLAN_CLKREQ#_Q 4
3
E
SATA_RCOMP_DP
SATA_RCOMP_DN
BA12
AY14
AY12
AT10
AT9
OPT@
{19}
{19}
LAN_CLKREQ#
{37}
QC6
MMBT3904WH_SOT323-3
+1.8VS
0607
HDA_RCOMP
HDA_RST_AUDIO#_R
HDA_SYNC_AUDIO_R
HDA_BITCLK_AUDIO_R
HDA_SDOUT_AUDIO_R
1
1
1
1
1
RC36
RC37
RC38
RC39
RC40
2
2
2
2
2
C
RC959
2.2K_0402_5%
49.9_0402_1%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
{43}
HDA_RST_AUDIO#
HDA_SYNC_AUDIO
{43}
{43}
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
{43}
HDA_SDIN0
{43}
1
WLAN_CLKREQ#_Q
3
WLAN_CLKREQ#
{40}
QC7
MMBT3904WH_SOT323-3
I2S_2_FS
I2S_2_TXD
I2S_2_FS {12}
I2S_2_TXD {12}
+1.8VS
+1.0VS
P34
N34
RC42
73.2_0402_1%
@
AK9
AK7
C24 CPU_PROCHOT#_R 1 RC44
2 0_0402_5%
RC960
2.2K_0402_5%
OPT@
H_PROCHOT#
{44,51,52}
1
GPU_CLKREQ#_Q
4 OF 13 REV = 1.15 ?
3
E
2 0_0402_5%
ODD_DETECT#_SOC
ODD_DA#_SOC
PCIE_RXP_1
PCIE_RXN_1
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
RPC1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
C
BB10
BC10
CRB USE SATA_GP0
1
SOC_SCI#
RC32
need check with BIOS
only GPIO_S0_SC[0..7] can make SCI
SATA_RXP_1
SATA_RXN_1
AV6
AV4
OPT@
1 CC4
1 CC5
1
AY16
BA16
PCIE_TXP_1
PCIE_TXN_1
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
2
2
2 2
B
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_TXP1
SATA_TXN_1
AT14
AT13
.1U_0402_10V6-K
.1U_0402_10V6-K
E
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
BD10
BF10
PCIE_RXP_0
PCIE_RXN_0
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
C
{42}
{42}
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_RXP_0
SATA_RXN_0
AY7
AY6
1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
AU16
AV16
PCIE_TXP_0
PCIE_TXN_0
2 2
B
{42}
{42}
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_TXP_0
SATA_TXN_0
C
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
BF6
BG7
2
{42}
{42}
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
1
ODD
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
2
D
{42}
{42}
ACLU1
1
HDD
Net name changed to same as
1
?
VLV_M_D
UC1D
QC199
MMBT3904WH_SOT323-3
GPU_CLKREQ#
OPT@
{19}
change mos to 3904
B
B
+1.8VS
+3VALW_R
+1.8VS
1
2
+1.8VS
D2 3
2
1
ODD_DA#
{42}
1
EC_SCI#
{44}
QC13
PJA138K_SOT23-3
@
QC17B
PJT138K_SOT363-6
G1
2
1
3
SOC_SCI#
S
4 S2
D
G2 5
2
G
ODD_DA#_SOC
RC95
10K_0402_5%
@
2
3
4
RC967
2.2K_0402_5%
RPC9
2.2K_0404_4P2R_5%
ODD_DETECT#_SOC
A
1 S1
D1 6
ODD_DETECT#
{42}
@
A
QC17A
PJT138K_SOT363-6
+3VS
@
RC957
RC965
1
1
2
2
10K_0402_5%
10K_0402_5%
ODD_DETECT#
ODD_DA#
Issued Date
Title
LC Future Center Secret Data
Security Classification
@
2013/03/26
Deciphered Date
2013/02/01
SOC (PCIE&HDA&SATA&STRAPS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
6
of
59
3
CC13
CC14
10P_0402_50V8-J
2
25MHZ_10PF_7V25000014
10P_0402_50V8-J
1
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
{37}
{37}
CLK_PCIE_LAN#
CLK_PCIE_LAN
AF9
AF7
PCIE_CLKN_11
PCIE_CLKP_11
AK4
AK6
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
PCIE_CLKN_22
PCIE_CLKP_22
AM4
AM6
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_CLKN_33
PCIE_CLKP_33
AM10
AM9
+1.8VALW_SPI
V1P8A PMC_SUSPWRDNACK
V1P8A PMC_SUSCLK0_G24
PMC_SLP_S0IX
V1P8A
PMC_SLP_S4
V1P8A
PMC_SLP_S3
V1P8A
GPIO_S514_J20
GPIO_S5_14 V1P8A
PMC_ACPRESENT
V1P8A
PMC_WAKE_PCIE_0
V1P8A
PMC_BATLOW
V1P8A
PMC_PWRBTN
V1P8A
PMC_RSTBTN
Internal 20K(H) V1P8S
PMC_PLTRST
V1P8A
GPIO_S517_J24
GPIO_S5_17 V1P8A
PMC_SUS_STAT
V1P8A
RESERVED_AM10
RESERVED_AM9
+1.8VALW_SPI
PMC_SUSCLK
@
+3VALW_R
D26
G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18
SUSPWRDNACK
PMC_SUSCLK
PMC_SLP_S0IX#
PMC_SLP_S4#
PMC_SLP_S3#
GPIO_S514_J20
PMC_ACIN
PMC_PCIE_WAKE#
PMC_BATLOW#
PMC_PWRBTN#
PMC_RSTBTN#
PMC_PLTRST#
C11
RTC_RST#
B10
B7
EC_RSMRST#
SYS_PWROK
C9
A9
B8
RTC_X1
RTC_X2
BVCCRTC_EXTPAD CC17 1
+1.8VALW
1
TP4
RC60
10K_0402_5%
@
0604
@
1 RC71
2 10K_0402_5%
+1.8VALW
PMC_ACIN
EC_RSMRST#
1 RC72
2 10K_0402_5%
+1.8VALW
2 10K_0402_5%
1
CC113
@
1 100K_0402_5%
20.01U_0402_25V7K
D
RC61
2.2K_0402_5%
for ACINneed check with power team
RC69 1
@
2
0_0402_5%
{44}
AC_PRESENT
@
RC63
10K_0402_5%
@
1 @ TP5
1 RC83
2 RC930
EC_RSMRST#
D
2 0_0402_5%
{40}
{40}
PCIE_CLKN_00
PCIE_CLKP_00
BF34
BD34
BD32
BF32
S
1
CLK_PCIE_GPU#
CLK_PCIE_GPU
2
+1.8VALW
RC82
{19}
{19}
AF6
AF4
CLK_PCIE_GPU#
CLK_PCIE_GPU
SIO_UART2_RXD
SIO_UART2_TXD
SIO_UART2_RTS
SIO_UART2_CTS
RESERVED_AD10
RESERVED_AD12
2 10K_0402_5%
G
1,Space 15MIL
2,No trace under crystal
3,place on oppsosit side of MCP for temp influence
CRYSTAL
ICLK_ICOMP
ICLK_RCOMP
1 RC73
2
OSC2
AD14
AD13
AD10
AD12
1
1
GND1
2 4.02K_0402_1% ICLK_ICOMP
2 47.5_0402_1% ICLK_RCOMP
4
3
1
2
1
CC12
18P_0402_50V8J
GND2
PMC_RSTBTN#
2
D
OSC1
TP9
TP10
TP1
TP3
1
1
2
1 @
1 @
1 @
1 @
AU34
AV34
BA34
AY34
QC203
PJA138K_SOT23-3
1
2
SIO_UART1_RXD
SIO_UART1_TXD
SIO_UART1_RTS
SIO_UART1_CTS
RESERVED_AD9
2
RC70 1
RC62 1
YC2
1
YC1
32.768KHZ_12.5PF_200458-PG14
CC11
18P_0402_50V8J
+1.8VS
ICLK_OSCIN
ICLK_OSCOUT
AD9
2
?
VLV_M_D
UC1E
AH12
AH10
XTAL25_IN
XTAL25_OUT
2 1M_0402_5%
1
1
XTAL25_OUT
XTAL25_IN
1
RC93
2
2
2 10M_0402_5%
3
D
QC9
2
1
RC92 1
4
RTC_X2
RTC_X1
5
0605
ACIN#
G
{44,53}
RPC15
RC85
2
22_0402_5%
PCH_SPI_CS0#
PCH_SPI_SO
SPI_WP#
1
2
3
4
CS#
SO(IO1)
WP#(IO2)
VSS
SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
1
2
C
D14
G12
F14
F12
G16
D18
F16
AT34
50mA
8
7
6
5
VCC
HOLD#(IO3)
SCLK
SI(IO0)
CC8
.1U_0402_10V6-K
XDP
GD25LQ64CVIGR_TSOP8
0605
SPI ROM
PCH_SPI_CS0# RC81 1
PCH_SPI_SI
PCH_SPI_CLK
VCCRTC
SRTC_RST#
RTC_RST#
RC89 1
2 20K_0402_1%
RC90 1
2 20K_0402_1%
RC84 1
RC88 1
2 22_0402_5%PCH_SPI_CS0#_R
B18
B16
C18
A17
C17
C16
B14
C15
SOC_KBRST#
2
2
1
2
CC10
1
1U_0402_6.3V6K
CC9
2
1U_0402_6.3V6K
1
1
SOC_LID_OUT#
JME1
SHORT PADS
@
TAP_TCK
TAP_TRST
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY
TAP_PREQ
RESERVED
C23
C21
B22
A21
C22
PCH_SPI_SO_R
2 22_0402_5%PCH_SPI_SI_R
2 22_0402_5%PCH_SPI_CLK_R
SOC_SMI#
JCMOS1
SHORT PADS
@
C13
A13
C19
JCMOS/JCMOS1
Place under Bottom
RTCRST#
Space 15Mil
RC91 1
2 49.9_0402_1%
GPIO_RCOMP18
ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_EXTPAD
N26
V1P0S
V1P0S
V1P0S
PCU_SPI_CS_00
PCU_SPI_CS_11
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
GPIO_S5_0
GPIO_S5_1
GPIO_S5_2
GPIO_S5_3
GPIO_S5_4
GPIO_S5_5
GPIO_S5_6
GPIO_S5_7
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
GPIO_S5_8
GPIO_S5_9
GPIO_S5_10
V1P8A
V1P8A
V1P8A
SIO_PWM_00
SIO_PWM_11
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
BAY-TRAIL-M-SOC_FCBGA1170
5 OF 13
REV = 1.15
B24 CPU_SVID_ALRT#_R
A25 CPU_SVID_DAT_R
C25 CPU_SVID_CLK_R
AU32
AT32
{44}
{5,44}
2 .1U_0402_10V6-K
1 RC78
1 RC79
1 RC80
2 20_0402_1%
2 16.9_0402_1%
2 0_0402_5%
{59}
CPU_SVID_ALERT#
{59}
CPU_SVID_DAT
{59}
CPU_SVID_CLK
C
need check power part if RES is staffed
K24
N24
M20
J18
M18
K18
K20
M22
M24
+1.8VALW
AV32
BA28
AY28
AY30
RC927
10K_0402_5%
?
RC793
10K_0402_5%
PMC_PCIE_WAKE#
S
PCIE_WAKE#
D
The ALT_GPIO_SMI.CORE_GPIO_SMI_STS@ [31:24] & ALT_GPIO_SMI.CORE_GPIO_SMI _EN[15:8] register bits correspond
to GPIO_S0_SC[7:0]. ALT_GPIO_SMI.SUS_GPIO_SMI_STS[23:16] & ALT_GPIO_SMI.SUS_GPIO_SMI_EN[7:0] correspond
to GPIO_S5[7:0].
+3VS
+3VALW
G
+3VALW
GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30
SIO_SPI_CS
V1P8S
V1P8S SIO_SPI_MISO
V1P8S SIO_SPI_MOSI
SIO_SPI_CLK
V1P8S
GPIO_RCOMP
RTC RST#
SVID_ALERT
SVID_DATA
SVID_CLK
EC_RSMRST#
SYS_PWROK
1
UC2
PCH_SPI_SO_R 1
PMC_RSMRST
PMC_CORE_PWROK
VRTC
VRTC
2
+1.8VALW_SPI
1
SRTC_RST#
PMC_PLT_CLK_00
PMC_PLT_CLK_11
PMC_PLT_CLK_22
PMC_PLT_CLK_33
PMC_PLT_CLK_44
PMC_PLT_CLK_55
ILB_RTC_RST
2
to 2.2K 4R8P
3
2.2K_0804_8P4R_5%
change 3.3K
ILB_RTC_TEST
BH7
BH5
BH4
BH8
BH6
BJ9
C12
2N7002KW_SOT323-3
2
SPI_WP#
SPI_HOLD#
PCH_SPI_CS0#
1
8
7
6
5
3
S
1
2
3
4
{37,40,44}
3
4
QC168
PJA138K_SOT23-3
RPC17
10K_0404_4P2R_5%
B
B
+1.8VALW
2
1
+3VALW_R
2
2
1
1
1
3
1
D2 3
RC74
10K_0402_5%
SUSWARN#
D
4 S2
SUSPWRDNACK
S
{44}
@
QC15A
PJT138K_SOT363-6
QC10
PJA138K_SOT23-3
1 S1
2 G1
RC75
10K_0402_5%
RC104
100K_0402_5%
G
PMC_PLTRST#
D1 6
5 G2
2
{19,37,40,44}
2
PLT_RST#
QC15B
PJT138K_SOT363-6
+1.8VALW
+1.8VALW
+1.8VALW
+1.8VALW
+1.8VALW
+3VALW_R
+3VALW
+3VALW_R
4 S2
D2 3
G2 5
QC14A
PJT138K_SOT363-6
EC_LID_OUT#
{44}
PMC_PWRBTN#
4 S2
3
4
PM_SLP_S3#
KBRST#
1
QC12A
PJT138K_SOT363-6
PMC_SLP_S4#
D2 3
PBTN_OUT#
QC12B
PJT138K_SOT363-6
4
{40}
2
SUSCLK
4 S2
QC11B
D2 3
PM_SLP_S4#
Bay trail plaform susclk is 1.8VSA level, NGFF card need 3.3V
{44}
PJT138K_SOT363-6
{44}
Issued Date
3
A
QC200
PJA138K_SOT23-3
Title
LC Future Center Secret Data
2013/03/26
Deciphered Date
2
SOC (RTC&SPI&PM)
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
1
PMC_SUSCLK
PJT138K_SOT363-6
{44}
Security Classification
QC14B
PJT138K_SOT363-6
{44}
3
D1 6
2
2
1
G1
1 S1
@
@
D1 6
G2 5
1 S1
SOC_KBRST#
{44}
RC933
10K_0402_5%
RC932
2.2K_0402_5%
@
2
1
G1
2
1
EC_SMI#
2
2
1
PMC_SLP_S3#
2
1
G1
G2 5
0801 EC_INT_SERIRQ need change to level shift
D1 6
RPC3
10K_0404_4P2R_5%
QC11A
D
2
1
RPC5
10K_0404_4P2R_5%
2
RPC4
10K_0404_4P2R_5%
S
1 S1
SOC_SMI#
SOC_LID_OUT#
3
4
3
4
RPC7
10K_0404_4P2R_5%
2
RPC6
2.2K_0404_4P2R_5%
G
A
RPC2
10K_0404_4P2R_5%
@
3
4
3
4
0605
0603
2
+3VALW_R
3
4
+1.8VALW
1
+1.8VALW
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Thursday, December 26, 2013
1
0801 EC_INT_SERIRQ need change to level shift
Sheet
7
of
59
4
3
E2
D2
{44} LPC_AD0
{44} LPC_AD1
{44} LPC_AD2
{44} LPC_AD3
{44} LPC_FRAME#
{44} CLK_PCI_EC
RC114
1
2 45.3_0402_1% USB_HSIC_RCOMP
RC117
1
2 49.9_0402_1% RCOMP_LPC_HVT
RC118
SOC_SERIRQ
RC119
1
2 22_0402_5%
1
2 0_0402_5%
PCH_PCI_CLK_R
A7
BF18
BH16
BJ17
BJ13
BG14
BG17
BG15
BH14
BG16
BG13
BG12
BH10
BG11
PCH_SMB_DATA
PCH_SMB_CLK
PCH_SMB_ALERT#
V1P8A
V1P8A
USB_PLL_MON
V1P8S
V1P8S
V1P8S
V1P8S
V1P8S
V1P8S
V1P8S
GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61
V1P8S
ILB_8254_SPKR
BD12
BC12
BD14
BC14
BF14
BD16
BC16
PXS_RST#_SOC
GPIO_S0_SC_56
VGA_PWRGD_SOC
GPIO52_SOC
GPIO53_SOC
PXS_PWREN_SOC
GPIO_S0_SC_56
BH12
USB_HSIC1_DATA
USB_HSIC1_STROBE
USB_HSIC_RCOMP
VLPC
VLPC
VLPC
VLPC
VLPC
VLPC
VLPC
VLPC
VLPC
V1P8S
V1P8S
V1P8S
SIO_I2C0_DATA
SIO_I2C0_CLK
V1P8S
V1P8S
SIO_I2C1_DATA
SIO_I2C1_CLK
V1P8S
V1P8S
SIO_I2C2_DATA
SIO_I2C2_CLK
V1P8S
V1P8S
SIO_I2C3_DATA
SIO_I2C3_CLK
V1P8S
V1P8S
SIO_I2C4_DATA
SIO_I2C4_CLK
V1P8S
V1P8S
SIO_I2C5_DATA
SIO_I2C5_CLK
V1P8S
V1P8S
SIO_I2C6_DATA
SIO_I2C6_CLK
1
RC116
10K_0402_5%
PCH_BEEP
PCH_WLAN_OFF#
2 G1
RC112
10K_0402_5%
@
{40}
PCH_BT_OFF#
QC19A
5 G2
PCH_BT_OFF#_Q
{40}
CMOS_ON#
PJT138K_SOT363-6
1
D
C
G
S
@
3
PJA138K_SOT23-3
BG24
BH24
BG25
BJ25
BG26
BH26
+1.8VS
+1.8VS
+1.8VS
PCU_SMB_DATA V1P8S
PCU_SMB_CLK
V1P8S
PCU_SMB_ALERT V1P8S
BF27
BG27
BH28
BG28
RC966
2.2K_0402_5%
@
BJ29
BG29
VGA_PWRGD_SOC
PCH_WLAN_OFF#_Q
PCH_BT_OFF#_Q
D1 6
GPIO52
{19}
GPIO53
{19}
{22,44}
QC204
PJA138K_SOT23-3
@
Description
1 S1
GPIO52_SOC
VGA_PWRGD
D
BH30
GPIO_S0_SC_092 BG30
GPIO_S0_SC_093 ?
V1P8S
V1P8S
RPC8
2.2K_0404_4P2R_5%
GC6@
4 S2
GPIO53_SOC
QC21A
PJT138K_SOT363-6
GC6@
B
D2 3
Reserve for GPU
QC21B
PJT138K_SOT363-6
GC6@
0
Reserve
Reserve
UMA SKU
1
Reserve
Reserve
GPU SKU
0
Reserve
Reserve
14’ panel
1
Reserve
Reserve
15’ panel
PCH_SMB_ALERT#
RPC18
1
USB_OC0#
2
USB_OC1#
10K_0404_4P2R_5%
2
10K_0402_5%
ODD_EN
@
1
+1.8VALW
4
3
1 RPC19
2
10K_0404_4P2R_5%
+1.8VS
+1.8VS
GPIO52
GPIO53
PCH_PCI_CLK_R
CC108
1
2
10P_0402_50V8-J
@
RPC22
2.2K_0404_4P2R_5%
RPC23
2.2K_0404_4P2R_5%
10K_0402_5%
GPIO52
RC955
1
@
2
10K_0402_5%
GPIO53
RC17
2
@
1
100K_0402_5%
PXS_PWREN
RC18
1
@
2
10K_0402_5%
PXS_RST#
14@
@
3
SOC_SERIRQ
@
1
CC15
.1U_0402_10V6-K
VCCB
GND
EO
A4
B4
6
PCH_SMB_DATA
4
SERIRQ
1
G2129TL1U_SC70-6
2
2
D2 3
SMB_DATA_S3
A
{14,40}
EMC
CC16
.1U_0402_10V6-K
SERIRQ level shift need IC, not MOS for frequence
4
4 S2
QC20B
PJT138K_SOT363-6
{44}
Issued Date
5
{14,40}
5
3
Title
LC Future Center Secret Data
Security Classification
PCB ID
2
1
G1
RC98
10K_0402_5%
G2 5
UC3
SMB_CLK_S3
QC20A
PJT138K_SOT363-6
1
1
UMA@
RC947
2.2K_0402_5%
1
2
2
RC946
2.2K_0402_5%
1
2
@
RC56
2.2K_0402_5%
1
2
1
RC97
0_0402_5%
VCCA
D1 6
2
2
2
RC96
0_0402_5%
1
RC57
2.2K_0402_5%
1
2
0610
RC954
1 S1
PCH_SMB_CLK
2
Reserve for NV GPU
+1.8VS
@
PCB_ID0
PCB_ID1
PCB_ID2
PCB_ID3
A
+3VS
2
1
+1.8VS
1
@
@
RC945
2.2K_0402_5%
1
2
2 1K_0402_1% ICLK_USB_TERMN_0
2 1K_0402_1% ICLK_USB_TERMN_1
2 0_0402_5%
USB_PLL_MON
15@
RC944
2.2K_0402_5%
1
2
1
1
1
OPT@
RC55
2.2K_0402_5%
1
2
RC105
RC106
RC108
RC54
2.2K_0402_5%
1
2
2
GC6@
+3VS
3
4
RC964
3
4
4
3
+3VS
2
PCH_CMOS_ON#_Q
BH22
BG23
S
+1.8VALW
{33}
QC18
QC19B
PJT138K_SOT363-6
{43}
G
210K_0402_5%
1
3
1
3
+3VS
{12}
PCH_WLAN_OFF#_Q
USB_HSIC0_DATA
USB_HSIC0_STROBE
PCB_ID3
+3VS
RC115
10K_0402_5%
USB_RCOMPO
USB_RCOMPI
LPC_RCOMP
ILB_LPC_AD_00
ILB_LPC_AD_11
ILB_LPC_AD_22
ILB_LPC_AD_33
ILB_LPC_FRAME
ILB_LPC_CLK_00
ILB_LPC_CLK_11
ILB_LPC_CLKRUN
ILB_LPC_SERIRQ
+3VS
2
H5
H4
RESERVED_H5
RESERVED_H4
ICLK_USB_TERM_1
1
USB_OC_00
USB_OC_11
2
ICLK_USB_TERMN_D10
ICLK_USB_TERMN
+1.8VS
RC120 1
2
2
1
2
2
1
H8
H7
RESERVED_H8
RESERVED_H7
@
PCB_ID2
PCB_ID1
1
2
2
1
USB_DP3
USB_DN3
6 OF 13
PCB_ID0
2
USB_DP2
USB_DN2
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
B
S
2
B4
B5
C
QC201
2N7002KW_SOT323-3
@
G1
M13
USB_PLL_MON
D
2
G
1
CC107
.1U_0402_10V6-K
@
G2 5
2 45.3_0402_1%
2
@
RC170 1
0_0402_5%
VGA_GATE#
3
4
1
{44}
2
1
RC113
D
1
D6
C7
USBRBIAS
{41}
{41}
USB_DP1
USB_DN1
D2 3
USB_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil
C20
B20
USB_OC0#
USB_OC1#
USB_OC0#
USB_OC1#
USB30_TX_P1
USB30_TX_N1
{21,58}
OPT@
QC4
PJA138K_SOT23-3
OPT@
LEFT USB (3.0)
4 S2
ICLK_USB_TERMN_0 D10
ICLK_USB_TERMN_1 F10
{41}
{45}
USB30_TX_P1
USB30_TX_N1
{41}
{41}
PXS_PWREN
QC8
PJA138K_SOT23-3
{19}
1
USB Hub
K10
H10
K6
K7
USB3_TXP0
USB3_TXN0
USB30_RX_P1
USB30_RX_N1
PXS_RST#
2
K12
J12
USB20_P3
USB20_N3
PXS_RST#_SOC
USB30_RX_P1
USB30_RX_N1
PXS_PWREN_SOC
1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
RC948
10K_0402_5%
OPT@
D1 6
USB20_P2
USB20_N2
{16}
{16}
D4
E3
USB3_RXP0
USB3_RXN0
USB_DP0
USB_DN0
2 1.24K_0402_1%
M4
M6
RESERVED_M4
RESERVED_M6
V1P8A
V1P8A
V1P8A
V1P8A
1 RC110
USB3_P1_REXT
P10
P12
1 S1
{41}
{41}
RESERVED_M7
USB3_REXT0
RESERVED_P10
RESERVED_P12
RC971
2.2K_0402_5%
OPT@
RC956
10K_0402_5%
OPT@
RC970
2.2K_0402_5%
OPT@
2
LEFT USB (2.0)
RIGHT USB (2.0)
M7
M12
3
J14
G14
GPIO_S5_40
GPIO_S5_41
GPIO_S5_42
GPIO_S5_43
+1.8VS
P7
P6
D
M16
K16
USB20_P0
USB20_N0
RESERVED_P7
RESERVED_P6
S
USB20_P1
USB20_N1
USB20_P0
USB20_N0
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
V1P8A
+3VS
D
USB20_P1
USB20_N1
{45}
{45}
GPIO_S5_32
GPIO_S5_33
GPIO_S5_34
GPIO_S5_35
GPIO_S5_36
GPIO_S5_37
GPIO_S5_38
GPIO_S5_39
M10
M9
S
{41}
{41}
LEFT USB (3.0)
RESERVED_M10
RESERVED_M9
G
J3
P3
H3
B12
PCB_ID0
PCB_ID1
PCB_ID2
PCB_ID3
D
V1P8A
G
M3
L1
K2
K3
M2
N3
P2
L3
PCH_CMOS_ON#_Q
ODD_EN
ODD_EN
+3VS
GPIO_S5_31
1
{42}
1
+1.8VS
2
G2
2
?
VLV_M_D
UC1F
3
5
2013/03/26
Deciphered Date
2
SOC (USB&LPC&SMB)
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
8
of
59
5
4
3
2
?
VLV_M_D
UC1G
1
+1.35V
+CPU_CORE
2 RC131 1 100_0402_1%
{59}
{59}
{59}
VCC_SENSE
+GFX_CORE
D
VCC_AXG_SENSE
2
VSS_SENSE
RC132 1 100_0402_1%
P28
BB8
N28
DRAM_VDD_S4_CLK
AD38
AF38
A48
AK38
AM38
AV41
AV42
BB46
VCC_SENSE
VCC_AXG_SENSE
VSS_SENSE
+1.35V
2 RC130 1 100_0402_1%
VCC_SENSE
VCC_AXG_SENSE
VSS_SENSE
CORE_VCC_SENSE_P28
UNCORE_VNN_SENSE
CORE_VSS_SENSE_N28
DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51
DRAM_VDD_S4_BJ48
DRAM_VDD_S4_C51
DRAM_VDD_S4_D44
DRAM_VDD_S4_F49
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42
DRAM_VDD_S4_V38
DRAM_VDD_S4_Y38
+1.35V
1 RC129 2
0_0603_5%
DRAM_VDD_S4_AD38
DRAM_VDD_S4_AF38
DRAM_VDD_S4
DRAM_VDD_S4_AK38
DRAM_VDD_S4_AM38
DRAM_VDD_S4_AV41
DRAM_VDD_S4_AV42
DRAM_VDD_S4_BB46
+CPU_CORE
AA27
AA29
AA30
AC27
AC29
AC30
AD27
AD29
AD30
AF27
AF29
AG27
AG29
AG30
P26
P27
U27
U29
V27
V29
V30
Y27
Y29
Y30
AF30
CORE_VCC_S0IX_AA27
CORE_VCC_S0IX_AA29
CORE_VCC_S0IX_AA30
CORE_VCC_S0IX_AC27
CORE_VCC_S0IX_AC29
CORE_VCC_S0IX_AC30
CORE_VCC_S0IX_AD27
CORE_VCC_S0IX_AD29
CORE_VCC_S0IX_AD30
CORE_VCC_S0IX_AF27
CORE_VCC_S0IX_AF29
CORE_VCC_S0IX_AG27
CORE_VCC_S0IX_AG29
CORE_VCC_S0IX_AG30
CORE_VCC_S0IX_P26
CORE_VCC_S0IX_P27
CORE_VCC_S0IX_U27
CORE_VCC_S0IX_U29
CORE_VCC_S0IX_V27
CORE_VCC_S0IX_V29
CORE_VCC_S0IX_V30
CORE_VCC_S0IX_Y27
CORE_VCC_S0IX_Y29
CORE_VCC_S0IX_Y30
0402
0402
0402
0402
+CPU_CORE
12 A
1
TP_CORE_V1P05_S4
TP2_CORE_VCC_S0IX
10uF SE00000UD8J
4.7uF SE00000SO0J
2.2uF SE00000888J
1uF
SE000000K0J
7 OF 13
1
1
1
1
AA22
C
CAD NOTE:FOR PIN AD38 AND AF38
DRAM_VDD_S4_CLK
1
Vienna is 0402 1uF
AA24
AC22
AC24
AD22
AD24
AF22
AF24
AG22
AG24
AJ22
AJ24
AK22
AK24
AK25
AK27
AK29
AK30
AK32
AM22
?
2
CC22
10U_0603_6.3V6M
D
+GFX_CORE
UNCORE_VNN_S3_AA24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AD24
UNCORE_VNN_S3_AF22
UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AG24
UNCORE_VNN_S3_AJ22
UNCORE_VNN_S3_AJ24
UNCORE_VNN_S3_AK22
UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK27
UNCORE_VNN_S3_AK29
UNCORE_VNN_S3_AK30
UNCORE_VNN_S3_AK32
UNCORE_VNN_S3_AM22
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
@
C
BD49
BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38
CC20
.1U_0402_10V6-K
CD@
1
CC21
1U_0402_6.3V6K
2
SE000000K0J
CC23
CC24
CC25
CC26
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 CD@
2
2
2
2
+1.35V
1.25 A
+CPU_CORE
1
1
2
1
CC35
22U_0805_6.3V6M
CD@
CC36
22U_0805_6.3V6M
2
1
2
1
CC37
22U_0805_6.3V6M
CD@
2
2
CC109
33P_0402_50V8J
B
@ For
1
CC27
2.2U_0402_6.3V6M
2
1
CC28
2.2U_0402_6.3V6M
2
1
CC32
2.2U_0402_6.3V6M
CC29
2.2U_0402_6.3V6M
2
CD@
1
2
CC31
33P_0402_50V8J
@
1
CC30
.1U_0402_10V6-K
2
1
CC33
.1U_0402_10V6-K
2
1
2
For RF
CC34
33P_0402_50V8J
@
B
For RF
RF request
+GFX_CORE
CC40
1U_0402_6.3V6K
2
1
2
CC39
1U_0402_6.3V6K
CD@
1
CC110
1U_0402_6.3V6K
2
1
2
CC38
33P_0402_50V8J
1
@
For RF request
+GFX_CORE
14 A
2
A
CC41
10U_0603_6.3V6M
1
Vienna is 0402 10uF
1
2
CC42
1U_0402_6.3V6K
CD@
2
CC43
10U_0603_6.3V6M
A
1
SE00000UD8J
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/03/26
Deciphered Date
SOC (Power)
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
9
of
59
5
4
3
+1.0VS_SOC
2
1
+1.35VS_SOC
D
+1.0VS_SOC
+1.0VS_SOC
+1.05VS
+1.0VS_SOC
+1.0VS_SOC
+1.0VS_SOC
+1.0VALW_UNCORE_G3
实际是1.05VS
+1.05VS_CORE_S3
+1.05VS_CORE_S3
+1.35VS_SOC
SVID_V1P0_S3_V32
VGA_V1P0_S3_BJ6
DRAM_V1P0_S0IX_AD35
DRAM_V1P0_S0IX_AF35
DRAM_V1P0_S0IX_AF36
DRAM_V1P0_S0IX_AA36
DRAM_V1P0_S0IX_AJ36
DRAM_V1P0_S0IX_AK35
DRAM_V1P0_S0IX_AK36
DRAM_V1P0_S0IX_Y35
DRAM_V1P0_S0IX_Y36
DDI_V1P0_S0IX_AK19
DDI_V1P0_S0IX_AK21
DDI_V1P0_S0IX_AJ18
DDI_V1P0_S0IX_AM16
+1.0VALW_UNCORE_G3
UNCORE_V1P0_G3_U22 +1.0VALW_UNCORE_G3
UNCORE_V1P0_G3_V22
UNCORE_V1P0_S0IX_AN30
VIS_V1P0_S0IX_AN29
UNCORE_V1P0_S0IX_AN29
VIS_V1P0_S0IX_AN30
UNCORE_V1P0_S3_AF16
UNCORE_V1P0_S3_AF18
UNCORE_V1P0_S3_Y18
UNCORE_V1P0_S3_G1
PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21
AN18
AN19
AA33
AF21
AG21
V24
Y22
Y24
M14
U18
U19
AN25
Y19
C3
C5
B6
AC32
Y32
U36
AA25
AG32
V36
BD1
AF19
AG19
AJ19
+1.05VS_CORE_S3
VGA_V1P35_S3
PCIE_GBE_SATA_V1P0_S3_AN18
SATA_V1P0_S3_AN19
CORE_V1P05_S3_AA33
UNCORE_V1P0_S0IX_AF21
UNCORE_V1P0_S0IX_AG21 UNCORE_V1P0_S0IX_V24
VIS_V1P0_S0IX_V24
UNCORE_V1P0_S0IX_Y22
VIS_V1P0_S0IX_Y22
UNCORE_V1P0_S0IX_Y24
VIS_V1P0_S0IX_Y24
USB_V1P0_S3_M14
USB_V1P0_S3_U18
USB_V1P0_S3_U19
GPIO_V1P0_S3_AN25 +1.0VALW_UNCORE_G3
USB3_V1P0_G3_Y19 +1.0VALW_UNCORE_G3
USB3_V1P0_G3_C3
UNCORE_V1P0_G3_C5
UNCORE_V1P0_G3_B6 CORE_V1P05_S3_AC32
CORE_V1P0_S3_AC32 CORE_V1P05_S3_Y32
CORE_V1P0_S3_Y32
UNCORE_V1P35_S0IX_F4_U36
UNCORE_V1P35_S0IX_F5_AA25
UNCORE_V1P35_S0IX_F2_AG32
UNCORE_V1P35_S0IX_F3_V36
VGA_V1P35_S3_F1_BD1
UNCORE_V1P35_S0IX_F6
UNCORE_V1P35_S0IX_F1_AG19
ICLK_V1P35_S3_F1_AJ19
AG18
AN16
U16
+1.8VS_UNCORE_S3
DRAM_V1P35_S0IX_F1_AD36
HDA_LPE_V1P5V1P8_S3_AM32
UNCORE_V1P8_S3_AM30
UNCORE_V1P8_S3_AN32
LPC_V1P8V3P3_S3_AM27
UNCORE_V1P8_G3_U24
USB_V3P3_G3_N18
USB_V3P3_G3_P18
UNCORE_V1P8_S3_U38
VGA_V3P3_S3_AN24
PCU_V1P8_G3_V25
PCU_V3P3_G3_N22
SD3_V1P8V3P3_S3_AN27
VSS_AD16
VSS_AD18
USB_HSIC_V1P2_G3_V18
UNCORE_V1P8_G3_AA18
RTC_VCC_P22
USB_V1P8_G3_N20
PMU_V1P8_G3_U25
CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35
CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33
VSS_A3_A3
VSS_A49_A49
VSS_A5_A5
VSS_A51_A51
VSS_A52_A52
VSS_A6_A6
VSS_B2_B2
VSS_B52_B52
VSS_B53_B53
VSS_BE1_BE1
VSS_BE53_BE53
VSS_BG1_BG1
VSS_BG53_BG53
VSS_BH1_BH1
VSS_BH2_BH2
VSS_BH52_BH52
VSS_BH53_BH53
VSS_BJ2_BJ2
VSS_BJ3_BJ3
VSS_BJ5_BJ5
VSS_BJ49_BJ49
VSS_BJ51_BJ51
VSS_BJ52_BJ52
VSS_C1_C1
VSS_C53_C53
VSS_E1_E1
VSS_E53_E53
RESERVED_F1
PCIE_V1P0_S3_AK18
PCIE_V1P0_S3_AM18
ICLK_V1P35_S3
ICLK_V1P35_S3
+1.5VS_HDA_S3
?
VLV_M_D
UC1H
V32
BJ6
AD35
AF35
AF36
AA36
AJ36
AK35
AK36
Y35
Y36
AK19
AK21
AJ18
AM16
U22
V22
AN29
AN30
AF16
AF18
Y18
G1
AM21
AN21
VGA_V1P0_S3
ICLK_V1P35_S3_F2
VSSA_AN16
USB_VSSA_U16
8 OF 13
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
AD36
AM32
AM30
AN32
AM27
U24
N18
P18
U38
AN24
V25
N22
AN27
AD16
AD18
V18
AA18
P22
N20
U25
AF33
AG33
AG35
U33
U35
V33
A3
A49
A5
A51
A52
A6
B2
B52
B53
BE1
BE53
BG1
BG53
BH1
BH2
BH52
BH53
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52
C1
C53
E1
E53
F1
AK18
AM18
+3.3VS_SOC
+1.8VALW_SOC
+3.3VALW_USB/PCU_G3
VSS_AD
+1.0VALW_UNCORE_G3
VSS_AD
VSS_AD
+1.0VALW_UNCORE_G3
0531 Change to UNCORE_V1P0_G3
VCCRTC
D
+1.05VS
+1.0VS_SOC
?
@
+1.0VS_SOC
C
1.9 A+850 mA
1U_0402_6.3V6K
PJ1
PJ_43x79_6
1
2
CC46
CD@
1
+1.0VS_SOC
CC47
2
CAD NOTE:FOR
PIN AD35 AF35
CAD NOTE:FOR
PIN AF36
1
1
2
CC49
1U_0402_6.3V6K
CD@
CC50
1U_0402_6.3V6K
2
CAD NOTE:FOR
PINS AJ36 AK35
AK36
1
CC51
1U_0402_6.3V6K
CAD NOTE:FOR
PINS AA36 Y35
Y36
1
CC52
1U_0402_6.3V6K
CAD NOTE:FOR
PINS AK21
2
2
2
1
+1.05VS
RC300 1
2 0_0402_5%
CC53
1U_0402_6.3V6K
@
1.0 A
VGA_V1P0_S3
1U_0402_6.3V6K
+1.0VS
1U_0402_6.3V6K
C
1
CAD NOTE:FOR
CC48 PIN BJ6
1
CC114
10U_0603_6.3V6M
1
2
2
1
CC54
1U_0402_6.3V6K
2
CC55
1U_0402_6.3V6K
2
+1.35VS_SOC
0603
@
2
CC61
CD@
2
1
1
CC62
2
CC63
2
1
CC64
+1.35VS_SOC_VGA
CC60
.1U_0402_10V6-K
RC974 1
2
2 0_0603_5%
CC115
1
2
2
@
VGA_V1P35_S3
CC101
1
1
1U_0402_6.3V6K
CC59
CD@
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
2
1
CC58
2 0_0603_5%
@
CAD NOTE:FOR
PIN BD1
CAD NOTE:FOR
CAD NOTE:FOR
CAD NOTE:FOR
PIN U18 U19
PINS AF21 AND AG21
PINS V24 Y22 Y24
1
2
@
+1.5VS
10U_0603_6.3V6M
@
CC57
22U_0805_6.3V6M
2
1
22U_0805_6.3V6M
CC56
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@
1
22U_0805_6.3V6M
RC301 1
CAD NOTE:FOR CAD NOTE:FOR
CAD NOTE:FOR
PINS AM16
PINS AK19 PINS AJ18
+3VS
+1.5VS_HDA_S3
RC136 1
+3.3VS_SOC
8 mA+25 mA
RC135 1
10 mA
2 0_0603_5%
2 0_0603_5%
CAD NOTE:FOR
1 PIN AM27
CC116
CC66
10U_0603_6.3V6M
1U_0402_6.3V6K
CD@
2
2
1
1
CC65
1U_0402_6.3V6K
2
CC70
2
@
2
CC71
CD@
1
CAD NOTE:FOR
CAD NOTE:FOR
PIN AN18
PIN V23
1U_0402_6.3V6K
1
CC69
CAD NOTE:FOR
PIN Y18 G1
1U_0402_6.3V6K
2
1
0.01U_0402_25V7K
CC68
CAD NOTE:FOR
PIN AF16 AF18
1U_0402_6.3V6K
2
@
1
1U_0402_6.3V6K
CC67
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
CAD NOTE:FOR
PIN AM16
CAD NOTE:FOR
PIN AN25
1
CC72
2
1
1
CC73
2
CC74
1U_0402_6.3V6K
2
1
2
CAD NOTE:FOR
PIN AK18 AM18
CC75
1U_0402_6.3V6K
CD@
+1.8VS
@
+1.8VS_UNCORE_S3
RC137 1
+1.35VS_SOC
10 mA
2 0_0603_5%
ICLK_V1P35_S3
RC302 1
2 0_0402_5%
CAD NOTE:FOR
PIN AG18
CAD NOTE:FOR
CAD NOTE:FOR
CAD NOTE:FOR
CAD NOTE:FOR
1 PIN U38
1 PIN AM30 AN32 1 PIN AM30 AN32 1 PIN AM30 AN32
CC76
CC77
CC78
CC79
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
@
@
2
2
2
2
ICLK_V1P35_S3
1
CC111
1U_0402_6.3V6K
2
B
B
+1.8VALW
RC138
+1.8VALW_SOC
1
65 mA
2 0_0603_5%
CAD NOTE:FOR
1
+1.0VALW
+1.0VALW_UNCORE_G3
1 RC139
2
325 mA
CC80
1U_0402_6.3V6K
CD@
1 PIN AA18
CC81
1U_0402_6.3V6K
2
+1.0VALW_UNCORE_G3
2 0_0603_5%
CAD NOTE:FOR
1
CC82
1U_0402_6.3V6K
2
1
2
1
CC83
1U_0402_6.3V6K
CD@
1
CC84
1U_0402_6.3V6K
2
2
CC85
1U_0402_6.3V6K
CD@
2
1
CAD NOTE:FOR
PINS Y19 AND C3
CC87
0.01U_0402_25V7K
CD@
1 PIN V18
CC86
1U_0402_6.3V6K
VSS_AD
2
0531 删除1.2VS预留
BAY TRAIL no use
VCCRTC
0603
1
CC112
.1U_0402_10V6-K
2
+1.35VS
+1.35VS_SOC
1 RC140
375 mA+45 mA
2 0_0603_5%
CAD NOTE:FOR
CAD NOTE:FOR CAD NOTE:FOR
CAD NOTE:FOR
PIN
AJ19
1 PIN V36
1 PIN AD36
1
1 PIN AA25
CC89
CC90
CC91
CC92
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
0611
2
2
2
2
CAD NOTE:FOR
PIN AD36
1
2
CAD NOTE:FOR
CAD NOTE:FOR
1 PIN AG19
1 PIN AF19
CC102
CC94
CC95
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
CD@
CD@
2
2
+3VALW_SOC
RC141
+3.3VALW_USB/PCU_G3
1
50 mA
2 0_0603_5%
1
A
1
2
CC98
10U_0603_6.3V6M
1
2
CC99
22U_0805_6.3V6M
CD@
CAD NOTE:FOR
PIN AA25
1
CC100
1U_0402_6.3V6K
CD@
2
CAD NOTE:FOR
PIN U36
1
CC88
1U_0402_6.3V6K
2 CD@
2
CAD NOTE:FOR
PIN AG32
1
CC93
1U_0402_6.3V6K
CD@
2
CC96
1U_0402_6.3V6K
CD@
1
CAD NOTE:FOR
PIN N18 P18
CC97
.1U_0402_10V6-K
A
2
Security Classification
Issued Date
Title
LC Future Center Secret Data
2013/03/26
Deciphered Date
2013/02/01
SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Document Number
4
3
2
Rev
0.2
ACLU9
Monday, December 23, 2013
Date:
5
1
Sheet
10
of
59
5
4
?
VLV_M_D
UC1I
A11
A15
A19
A23
A27
A31
A35
A39
A43
A47
AA1
AA16
AA19
AA21
AA3
AA32
AA35
AA38
AA53
AB10
AB4
AB41
AB45
AB47
AB48
AB50
AB51
AB6
AC16
AC18
AC19
AC21
AC25
AC33
AC35
D
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40
AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36
C
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
?
VLV_M_D
UC1K
AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1
AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19
AT24
AT27
AT30
AT35
AT38
AT4
AT47
AT52
AU1
AU24
AU3
AU30
AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51
AV7
AW13
AW19
AW27
AW3
AW35
AY10
AY22
AY32
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
10 OF 13 ?
@
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27
BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38
D
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
11 OF 13 ?
@
E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27
H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
12 OF 13
@
B
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
1
?
VLV_M_D
UC1L
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
2
?
VLV_M_D
UC1J
AG38
AH4
AH41
AH45
AH7
AH9
AJ1
AJ16
AJ21
AJ25
AJ27
AJ29
AJ3
AJ30
AJ32
AJ33
AJ35
AJ38
AJ53
AK10
AK14
AK16
AK33
AK41
AK44
AM12
AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40
M28
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
9 OF 13 ?
@
BF30
BF36
BF4
BG31
BG34
BG39
BG42
BG45
BG49
BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47
BJ7
C14
C31
C34
C39
C42
C45
C49
D12
D16
D24
D30
D36
D38
E19
E35
3
?
VLV_M_D
UC1M
K9
L13
L19
L27
L35
M19
M26
M27
M34
M35
M38
M47
M51
N1
N16
N38
N51
P13
P16
P19
P20
P24
P32
P35
P38
P4
P47
P52
P9
T40
U1
U11
U12
U14
U21
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
U3
U30
U32
U40
U42
U43
U45
U46
U48
U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9
C
?
BAY-TRAIL-M-SOC_FCBGA1170
REV = 1.15
13 OF 13
@
B
?
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/03/26
Deciphered Date
SOC (VSS)
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
11
of
59
5
4
3
2
1
D
D
Hardware STRAPS
(Follow up CRB& VIENNA)
MDSI_DDCDATA(Checklist repuest 10K pull down)
GPIO_S0_SC_56(Internal Pull-up)
GPIO_S0_SC[063] (Internal Pull-up)
GPIO_S0_SC[065](Internal Pull-up)
DDI1_DDCDATA
DDI0_DDCDATA
GPIO_S0_SC_56:
A16 Top Swap
0=Top address bit is unchanged
1=Top address bit is inverted
GPIO_S0_SC[063]
Multiplexed with Hardware Straps Pin LPE_I2S2_FRM
BIOS Boot selection
0=LPC
1=SPI
GPIO_S0_SC[065]
Multiplexed with LPE_I2S2_DATAOUT
Security Flash Descriptors
0=Override
1=Normal Operation
DDI0_DDCDATA:
DDI0 strap
0=DDI0 not detected
1=DDI0 detected
DDI1_DDCDATA:
DDI1 strap
0=DDI1 not detected
1=DDI1 detected
2
2
RC46
10K_0402_1%
@
@
RC47
10K_0402_1%
@
1
RC45
10K_0402_1%
1
@
1
1
RC938
10K_0402_1%
1
RC936
2.2K_0402_5%
2
2
2
+1.8VS
GPIO_NC13
GPIO_S0_SC_56
I2S_2_FS
I2S_2_TXD
PCH_HDMI_DDC_DAT
DDI0_DDCDATA
C
GPIO_NC13
GPIO_S0_SC_56
GPIO_S0_SC_56
I2S_2_FS
I2S_2_FS
I2S_2_TXD
I2S_2_TXD
1
1
1
RC941
10K_0402_1%
@
{8}
{6}
{6}
{4}
2
DDI1_DDCDATA
RC943
2.2K_0402_5%
@
RC942
10K_0402_1%
1
2
2
2
DDI1_DDCDATA
RC963
10K_0402_1%
@
{4}
GPIO_NC13
B
I2S_2_TXD
2
0606
C
B
@
1
ME2
1
1
1
RC961
4.7K_0402_5%
QC202
2
G
RC962
1
2
PCH_ME_PROTECT
{44}
0_0402_5%
S
3
2
2
D
JUMP_43X39
2N7002KW_SOT323-3
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
SOC (STRAPS & OTHERS)
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
12
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
MCP (OTHER)
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
13
of
59
5
4
DDRA_DQ[0..63]
{5}
DDRA_DQS[0..7]
{5}
{5}
DDRA_DQS#[0..7]
3A@1.5V
DDRA_DQS#1
DDRA_DQS1
DDRA_DQ10
DDRA_DQ11
DDRA_DQ16
DDRA_DQ17
DDRA_DQS#2
DDRA_DQS2
DDRA_DQ18
DDRA_DQ19
DDRA_DQ28
DDRA_DQ25
DDRA_DM3
@
1
2
DDRA_DQ7
DDRA_DQ2
@
1
2
@
1
2
DDRA_DQ12
DDRA_DQ8
DDRA_DM1
DDRA_DRAMRST#
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
{5}
DDRA_DQ15
DDRA_DQ14
DDRA_DQ20
DDRA_DQ21
Layout Note:
Place near DIMM
DDRA_DQ23
DDRA_DQ22
DDRA_DQ24
DDRA_DQ29
+1.35V
DDRA_DQS#3
DDRA_DQS3
{5}
DDRA_DQS#4
DDRA_DQS4
DDRA_DQ40
DDRA_DQ45
DDRA_DM5
DDRA_DQ42
DDRA_DQ43
DDRA_DQ48
DDRA_DQ49
2
2
CD28
.1U_0402_10V6-K
205
207
GND1
BOSS1
GND2
BOSS2
LCN_DAN06-K4406-0103
ME@
5
4
206
208
@
C
CD19
220U_6.3V_M
2
+1.35V
+1.35V
DDRA_CLK1
DDRA_CLK1#
DDRA_BS1#
DDRA_RAS#
DDRA_CS0#
DDRA_ODT0
DDRA_ODT1
DDRA_CLK1
DDRA_CLK1#
{5}
{5}
DDRA_BS1#
DDRA_RAS#
{5}
{5}
DDRA_CS0#
DDRA_ODT0
{5}
{5}
DDRA_ODT1
{5}
RD1
4.7K_0402_1%
RD5
1
DDRA_DM4
DDRA_DQ38
DDRA_DQ39
2
RD6
1
2
1
DDR_DQ
0_0402_5%
DDR_CA
DDRA_DQ37
DDRA_DQ33
RD3
4.7K_0402_1%
2
DDR_CA
0_0402_5%
RD2
4.7K_0402_1%
B
RD4
4.7K_0402_1%
DDRA_DQ44
DDRA_DQ41
DDRA_DQS#5
DDRA_DQS5
Layout Note:
Place near DIMM
DDRA_DQ47
DDRA_DQ46
+1.35V
DDRA_DQ52
DDRA_DQ53
+0.675VS
DDRA_DM6
5V
0
@0.
.65A
7
CD68
DDRA_DQ55
DDRA_DQ54
1
2
DDRA_DQ60
DDRA_DQ57
CD69
@
DDRA_DQS#7
DDRA_DQS7
1
2
@
CD66
1
2
@
CD67
1
2
1
@
CD24 1
CD23
1U_0402_6.3V6K
2
2
@
DDRA_DQ63
DDRA_DQ62
CD25
1
2
CD26
2
@
cost down bom to change 0.1uF
SMB_DATA_S3 {8,40}
SMB_CLK_S3 {8,40}
+0.675VS
Issued Date
2013/08/08
2013/08/05
Deciphered Date
@
1
2
1
1
2
2
@
DDRIII SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
3
2
A
@
For RF request
Title
LC Future Center Secret Data
Security Classification
1
CD70
33P_0402_50V8J
@
1
+
10U_0603_6.3V6M
SA1
1
CD27
2.2U_0603_6.3V6K
2
1
CD65
+3VS
1
CD64
SA0
2
CD18
.1U_0402_10V6-K
DDRA_DQ58
DDRA_DQ59
1
10U_0603_6.3V6M
A
2
CD17
.1U_0402_10V6-K
DDRA_DM7
1
.1U_0402_10V6-K
DDRA_DQ56
DDRA_DQ61
2
CD16
@
.1U_0402_10V6-K
DDRA_DQ50
DDRA_DQ51
1
DDRA_MA2
DDRA_MA0
.1U_0402_10V6-K
SA0
SA1
DDRA_MA6
DDRA_MA4
.1U_0402_10V6-K
2 0_0402_5%
2 0_0402_5%
2
CD15
DDRA_MA11
DDRA_MA7
.1U_0402_10V6-K
DDRA_DQS#6
DDRA_DQS6
2
@
CD21
.1U_0402_10V6-K
DDRA_DQ32
DDRA_DQ36
2
1
DDRA_CS1#
DDRA_MA13
DDRA_CS1#
2
2
DDRA_WE#
DDRA_CAS#
2
1
1
DDRA_WE#
DDRA_CAS#
2
DDRA_MA15
DDRA_MA14
CD14
.1U_0402_10V6-K
DDRA_BS0#
{5}
{5}
2
1
.1U_0402_10V6-K
{5}
DDRA_MA10
DDRA_BS0#
{5}
CD13
.1U_0402_10V6-K
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE1
1
.1U_0402_10V6-K
DDRA_CLK0
DDRA_CLK0#
{5}
{5}
DDRA_CKE1
CD12
10U_0603_6.3V6M
DDRA_MA3
DDRA_MA1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
10U_0603_6.3V6M
DDRA_MA8
DDRA_MA5
CKE1
VDD_2
A15
A14
VDD_4
A11
A7
VDD_6
A6
A4
VDD_8
A2
A0
VDD_10
CK1
CK1#
VDD_12
BA1
RAS#
VDD_14
S0#
ODT0
VDD_16
ODT1
NC_2
VDD_18
VREF_CA
VSS_28
DQ36
DQ37
VSS_30
DM4
VSS_32
DQ38
DQ39
VSS_34
DQ44
DQ45
VSS_35
DQS5#
DQS5
VSS_38
DQ46
DQ47
VSS_40
DQ52
DQ53
VSS_42
DM6
VSS_44
DQ54
DQ55
VSS_46
DQ60
DQ61
VSS_48
DQS7#
DQS7
VSS_50
DQ62
DQ63
VSS_52
EVENT#
SDA
SCL
VTT_2
CD11
10U_0603_6.3V6M
DDRA_MA12
DDRA_MA9
CKE0
VDD_1
NC_1
BA2
VDD_3
A12/BC#
A9
VDD_5
A8
A5
VDD_7
A3
A1
VDD_9
CK0
CK0#
VDD_11
A10/AP
BA0
VDD_13
WE#
CAS#
VDD_15
A13
S1#
VDD_17
TEST
VSS_27
DQ32
DQ33
VSS_29
DQS4#
DQS4
VSS_31
DQ34
DQ35
VSS_33
DQ40
DQ41
VSS_36
DM5
VSS_37
DQ42
DQ43
VSS_39
DQ48
DQ49
VSS_41
DQS6#
DQS6
VSS_43
DQ50
DQ51
VSS_45
DQ56
DQ57
VSS_47
DM7
VSS_49
DQ58
DQ59
VSS_51
SA0
VDDSPD
SA1
VTT_1
1
10U_0603_6.3V6M
DDRA_BS2#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CD10
10U_0603_6.3V6M
DDRA_BS2#
{5}
DDRA_CKE0
CD9 1
10U_0603_6.3V6M
DDRA_CKE0
CD8 1
10U_0603_6.3V6M
CD7 1
DDRA_DQ30
DDRA_DQ31
2
{5}
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
DDRA_DM2
10U_0603_6.3V6M
DDRA_DQ26
DDRA_DQ27
DDRA_DQS#0
DDRA_DQS0
1
DDRA_DQ9
DDRA_DQ13
{5}
D
DDRA_DQ4
DDRA_DQ5
2
DDRA_DQ6
DDRA_DQ3
DDRA_DM[7:0]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
DDRA_DM0
VSS_2
DQ4
DQ5
VSS_4
DQS0#
DQS0
VSS_6
DQ6
DQ7
VSS_8
DQ12
DQ13
VSS_10
DM1
RESET#
VSS_12
DQ14
DQ15
VSS_14
DQ20
DQ21
VSS_16
DM2
VSS_18
DQ22
DQ23
VSS_20
DQ28
DQ29
VSS_22
DQS3#
DQS3
VSS_24
DQ30
DQ31
VSS_26
2
2
VREF_DQ
VSS_1
DQ0
DQ1
VSS_3
DM0
VSS_5
DQ2
DQ3
VSS_7
DQ8
DQ9
VSS_9
DQS1#
DQS1
VSS_11
DQ10
DQ11
VSS_13
DQ16
DQ17
VSS_15
DQS2#
DQS2
VSS_17
DQ18
DQ19
VSS_19
DQ24
DQ25
VSS_21
DM3
VSS_23
DQ26
DQ27
VSS_25
{5}
CD6
33P_0402_50V8J
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CD5
33P_0402_50V8J
CD3
DDRA_DQ0
DDRA_DQ1
DDRA_MA[0..15]
For RF request
JDDR1
DDR_DQ
DDRA_DQ35
DDRA_DQ34
RD10 1
RD11 1
+1.35V
CD4
33P_0402_50V8J
B
+1.35V
.1U_0402_10V6-K
C
1
2
D
2
DDR3 SO-DIMM A
DDR Mapping table
DDRA_DQ0---DQ0
DDRA_DQ1---DQ1
DDRA_DQ6---DQ2
DDRA_DQ3---DQ3
DDRA_DQ4---DQ4
DDRA_DQ5---DQ5
DDRA_DQ7---DQ6
DDRA_DQ2---DQ7
DDRA_DQ9----DQ8
DDRA_DQ13---DQ9
DDRA_DQ10---DQ10
DDRA_DQ11---DQ11
DDRA_DQ12---DQ12
DDRA_DQ8----DQ13
DDRA_DQ15---DQ14
DDRA_DQ14---DQ15
DDRA_DQ16---DQ16
DDRA_DQ17---DQ17
DDRA_DQ18---DQ18
DDRA_DQ19---DQ19
DDRA_DQ20---DQ20
DDRA_DQ21---DQ21
DDRA_DQ23---DQ22
DDRA_DQ22---DQ23
DDRA_DQ28---DQ24
DDRA_DQ25---DQ25
DDRA_DQ26---DQ26
DDRA_DQ27---DQ27
DDRA_DQ24---DQ28
DDRA_DQ29---DQ29
DDRA_DQ30---DQ30
DDRA_DQ31---DQ31
DDRA_DQ32---DQ32
DDRA_DQ36---DQ33
DDRA_DQ35---DQ34
DDRA_DQ34---DQ35
DDRA_DQ37---DQ36
DDRA_DQ33---DQ37
DDRA_DQ38---DQ38
DDRA_DQ39---DQ39
DDRA_DQ40---DQ40
DDRA_DQ45---DQ41
DDRA_DQ42---DQ42
DDRA_DQ43---DQ43
DDRA_DQ44---DQ44
DDRA_DQ41---DQ45
DDRA_DQ47---DQ46
DDRA_DQ46---DQ47
DDRA_DQ48---DQ48
DDRA_DQ49---DQ49
DDRA_DQ50---DQ50
DDRA_DQ51---DQ51
DDRA_DQ52---DQ52
DDRA_DQ53---DQ53
DDRA_DQ55---DQ54
DDRA_DQ54---DQ55
DDRA_DQ56---DQ56
DDRA_DQ61---DQ57
DDRA_DQ58---DQ58
DDRA_DQ59---DQ59
DDRA_DQ60---DQ60
DDRA_DQ57---DQ61
DDRA_DQ63---DQ62
DDRA_DQ62---DQ63
3
1
Sheet
14
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
15
of
59
5
4
3
2
1
+3VS
1
RH20
U1
2
0_0603_5%
+5VALW
+3VALW_SOC
+VDD
0604
29
DM0
DP0
DM1
DP1
AVDD
DM2
DP2
RREF
AVDD1
X1
X2
DM3
DP3
AVDD2
GL850G
QFN28
V33
V5
PWREN1#/SDA
OVCUR1#/SMC
OVCUR2#/SMD
PGANG
PSELF
DVDD
OVCUR3#
OVCUR4#
TEST/SCL
RESET#
DP4
DM4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+VDD
V5
SDA_HUB
HUB_USB_OC1#
1
RH1
@
1 TP6
1
RH2
2
0_0603_5%
2
V5
0_0603_5%
@
@
** External regulator mode：RH1上件，RH2不上件
Internal regulator mode：RH1不上件，RH2上件
PGANG
PSELF
D
LB1
1
2+VDD
UPB100505T-121Y-N_2P
1 TP7
TEST/SCL
RESET#
HUB_USB20_P4
HUB_USB20_N4
@
1
CH1
.1U_0402_10V6-K
2
+VDD
2 RH3
1 @
10M_0402_5%
YH1
1
2
GND2
4
12MHZ_10PF_7V12000008
1
2
1
CH2
CH3
10U_0603_6.3V6M .1U_0402_10V6-K
2
2
2
CH10
20P_0402_50V8
2
1
2
1
2
1
2
As close to GL850G
CH2 close to PIN28
CH3 PIN5
C
1
.1U_0402_10V6-K
CH8
CH9
20P_0402_50V8
GND1
1
2
UPB100505T-121Y-N_2P
1
1
1U_0402_6.3V6K
CH7
0805 change
OSC2
0604
1U_0402_6.3V6K
CH6
2
GL850G-OHY31_QFN28_5X5
OSC1
3
+AVDD
.1U_0402_10V6-K
CH5
1
+AVDD
LB2
.1U_0402_10V6-K
CH4
PAD
XTAL12_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XTAL12_IN
D
HUB_USB20_N0
HUB_USB20_P0
HUB_USB20_N1
HUB_USB20_P1
+AVDD
HUB_USB20_N2
HUB_USB20_P2
RREF_HUB
+AVDD
XTAL12_IN
XTAL12_OUT
HUB_USB20_N3
HUB_USB20_P3
+AVDD
CH4/CH5 PIN9
CH6/CH15 PIN14
As close to GL850G
1
RH4
+VDD
USB20_N3
1
2
HUB_USB20_N0
{8}
USB20_P3
USB20_P3
4
3
HUB_USB20_P0
RH6
10K_0402_5%
@
Vienna change to 619 ohm for Eye Diagram test
RH9
2
DLP11SN900HL2L_4P
1
2
0_0402_5%
RH8
RH7
10K_0402_5%
2
USB20_N3
1
@
{8}
1
CM1
+5VALW
2
0_0402_5%
C
RREF_HUB
1
2
RESET#
2
47K_0402_5%
RH10
2
1U_0402_6.3V6K
CH11
1
B
1
680_0402_1%
B
PGANG
0605
@
1 RH11
2
100K_0402_5%
Individual Mode
+VDD
HUB_USB20_N1
HUB_USB20_P1
{33}
{33}
Camera
HUB_USB20_N2
HUB_USB20_P2
{45}
{45}
Card reader
HUB_USB20_N3
HUB_USB20_P3
{40}
{40}
BT
HUB_USB20_N4
HUB_USB20_P4
{33}
{33}
Touch panel
PSELF
1
RH12 2
10K_0402_5%
Self-power
+VDD
RH628
2
HUB_USB_OC1# 1
@ 10K_0402_5%
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/03/26
Deciphered Date
USB Hub GL850G-OHY31
2013/02/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
16
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
5
4
3
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
17
of
59
5
4
3
2
1
N15x GPIO
D
ACTIVE
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO
I/O
Function Description
GPIO0
OUT
-
GPIO1
OUT
N/A
GPIO2
OUT
N/A
GPIO3
OUT
N/A
GPIO4
OUT
N/A
GPIO5
OUT
N/A
GPU power sequencing---3V3_MAIN_EN
GPIO6
IN
-
GPU wake signal for GC6 2.0
GPIO7
OUT
N/A
GPIO8
I/O
-
System side PCIe reset Monitor
GPIO9
I/O
N/A
2.2K Pull-up
GPIO10
OUT
N/A
GPIO11
OUT
-
GPIO12
IN
GPIO13
OUT
IN
N/A
GPIO15
IN
N/A
GPIO16
GPIO17
IN
N/A
GPIO19
IN
N/A
GPIO20
(W)
(W)
(MHz)
(V)
(A)
(W)
(A)
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(3.3V)
(10K pull High)
Physical
Strapping pin
ROM_SCLK
Phase Shedding
N/A
GPIO18
Products
N14X
128bit
2GB
DDR3
NVVDD
GPU Core VDD PWM control signal
N/A
IN
Other
NVCLK
/MCLK
N15x Multi-level Straps
C
GPIO14
I/O and
PLLVDD
(1.05V)
Mem
(1,5)
D
AC Power Detect Input
-
FBVDD
(1.35V)
FBVDDQ
PCI Express
(GPU+Mem) (1.05V)
(1.35V)
(6)
GPU
(4)
FB Enable for GC6 2.0
N/A
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
+3VGS
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
ROM_SI
+3VGS
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
+3VGS
DEVID_SEL
PCIE_CFG
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
+3VGS
STRAP1
+3VGS
STRAP2
+3VGS
Power Rail
C
Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3
+3VGS
STRAP4
+3VGS
SMBUS_ALT_ADDR
GPIO21
OUT
GPU PCIe self-reset control
0
0x9E (Default)
OVERT
OUT
Active Low Thermal Catastrophic Over Temperature
1
0x9C (Multi-GPU usage)
N15V-GM Power Sequence
N15x Binary Straps
B
Other Power rail
+3VG_AON
B
+VGA_CORE
+3VG_AON
Physical
Strapping pin
ROM_SCLK
tNVVDD >0
+1.35VGS
Tpower-off <10ms
tFBVDDQ >0
+1.05VS_VGA
tPEX_VDD >0
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
1. all power rail ramp up time should be larger than 40us
Power Rail
Strap Mapping
+3VGS
SMB_ALT_ADDR
ROM_SI
+3VGS
SUB_VENDOR
ROM_SO
+3VGS
VGA_DEVICE
STRAP0
+3VGS
RAM_CFG[0]
STRAP1
+3VGS
STRAP2
+3VGS
RAM_CFG[2]
STRAP3
+3VGS
RAM_CFG[3]
STRAP4
+3VGS
PCIE_MAX_SPEED
RAM_CFG[1]
N15S-GT Power Sequence
+3VG_AON
+VGA_CORE
A
A
tNVVDD >0
+1.05VS_VGA
+1.35VGS
tPEX_VDD >0
Issued Date
Title
LC Future Center Secret Data
Security Classification
1. all power rail ramp up time should be larger than 40us
2013/08/08
Deciphered Date
2013/08/05
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
18
of
59
5
4
{8}
GPIO53
{6}
PCIE_CRX_GTX_N[0..1]
{6}
PCIE_CRX_GTX_P[0..1]
{6}
PCIE_CTX_C_GRX_N[0..1]
{6}
PCIE_CTX_C_GRX_P[0..1]
RV1
1 GC6@
2 0_0402_5%
FB_GC6_EN_R
RV2
1 GC6@
2 0_0402_5%
GPU_EVENT#
3
2
1
UV1A
+3VGS
1 RV175
@
Part 1 of 6
1 0_0402_5%
@
+3VG_AON
OPT@1 0_0402_5%
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
2
2
2
2
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
C
1
5
B
UV2
4
Y
SYS_PEX_RST_MON#
RV14
10K_0402_5%
OPT@
3
A
2
1
P
2
PXS_RST#
G
PLT_RST#
1
74LVC1G08GW_SOT353-1-5
OPT@
2 RV16
0_0402_5%
1
@
NC100
NC101
NC102
NC103
NC104
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
1
RV180
10K_0402_5%
GC6@
3
RV37
10K_0402_5%
@
1
1
2
SYS_PEX_RST_MON#
1
DV6
GPU_PEX_RST_HOLD#
@
2
2
Differential signal
B
1
CLK_PCIE_GPU
CLK_PCIE_GPU#
CLK_REQ_GPU#
{7} CLK_PCIE_GPU
{7} CLK_PCIE_GPU#
AE8
AD8
AC6
2 RV32
PEX_TSTCLK_OUT
200_0402_1% PEX_TSTCLK_OUT#
AF22
AE22
PLT_RST_VGA#
2 RV35
PEX_TERMP
OPT@ 2.49K_0402_1%
AC7
AF25
1
2
2 0_0402_5%
OPT@
AE3
AE4
3
OVERT#
1
1
2
CORE_PLLVDD
SP_PLLVDD
@
3
1
QV3
2N7002KW_SOT323-3
@
S
B7
A7
VGA_CRT_CLK
VGA_CRT_DATA
C9
C8
I2CB_SCL
I2CB_SDA
A9
B9
I2CC_SCL
I2CC_SDA
D9
D8
@
2
+3VG_AON
RV13
10K_0402_5%
@
I2C,if not use, can be soft grounded
and delete pull up resistor
3
1
1
---colin
VGA_CRT_DATA
RV17 1
VGA_CRT_CLK
RV19 1
I2CB_SCL
RV22 1
OPT@
+PLLVDD
OPT@
2 RV24
0_0402_5%
@
OPT@
+SP_PLLVDD
I2CB_SDA
RV25 1
I2CC_SCL
RV28 1
OPT@
RV30 1
OPT@
RV33 1
XTALOUT
XTAL_SSIN
XTAL_OUTBUFF
C11
B10
@
XTAL_IN
XTAL_OUT
A10 XTALSSIN
C10 XTALOUT
GPU_EVENT#
2 RV15
GC6@ 0_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
+3VG_AON
3VGS_PWR_EN
RV18 2
OPT@
OVERT#
RV20 1
VGA_ALERT#
RV23 1
VGA_AC_DET_R
RV26 1
PSI_VGA
RV29 1
OPT@
OPT@
OPT@
OPT@
GPU_PEX_RST_HOLD# RV31 1
OPT@
1
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
B
1 OPT@
1 OPT@
2 RV34 10K_0402_5%
2 RV36 10K_0402_5%
Under GPU(below 150mils)
180ohms (ESR=0.2) Bead
1
+SP_PLLVDD
OPT@
150mA
BAT54AWT1G_SOT323-3
GC6@
1
2 RV39
N15VGM@ 0_0402_5%
1
change to BAT54A for cost down
CV12
@
Connect to CPU GPIO
I2CC_SDA
XTAL_IN
XTAL_OUT
2
Internal Thermal Sensor
1
45mA
C
1
+3VG_AON
VGA_SMB_CK2
VGA_SMB_DA2
45mA
CV2
@
QV4
2N7002KW_SOT323-3
@
L6
M6
N6
2
CV3
{44}
OPT@
PEX_RST_N
PEX_TERMP
1
+3VG_AON
WRST#
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_TSTCLK
PEX_TSTCLK_N
D
2
G
CV218
QV23
2N7002KW_SOT323-3
OPT@
W5
AE2
AF2
3
1
2 0_0402_5%
.1U_0402_10V6-K
1 RV174
N15S-GT-S-A2_FCBGA595
PLT_RST_VGA#
1 RV8
@
GPU_PEX_RST_HOLD#
AG3
AF4
AF3
4
6
1
{58}
OVERT#
60mA
CLK
+3VG_AON
PSI_VGA
GPU_EVENT#_R
I2CA_SCL
I2CA_SDA
VID_PLLVDD
+3VGS
2 RV6
PSI_VGA
0_0402_5%
PLT_RST_VGA#
A6
AB6
S
D
{8}
1
N15SGT@
D
QV2A
2N7002KDWH_SOT363-6
@
S
S
{7,37,40,44}
PLT_RST#
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
NC89
NC90
NC91
NC92
NC93
NC94
NC95
NC96
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
{44}
G
2
CV11
.1U_0402_10V6-K
OPT@
AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25
VGA_AC_DET
D
2
G
OVERT#
1
RB751V-40_SOD323-2
D
2
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
2
S
RV12
CV10
CV13
CV8
CV9
DV1
{58}
OPT@
.1U_0402_10V6-K
2
NVVDD PWM_VID
H_THRMTRIP#
QV2B
2N7002KDWH_SOT363-6
@
2
RV10
NVVDD PWM_VID
VGA_AC_DET_R
PSI_VGA_R
2
D
CV1
@
5
G
A6 Symbol update to OVER
G
+3VGARST
SYS_PEX_RST_MON#
VGA_ALERT#
PLT_RST_VGA#
NC97
NC98
NC99
{21,58}
3VGS_PWR_EN
GPU_EVENT#_R
1
CV15
2
OPT@
1
CV16
2
OPT@
1
CV17
2
OPT@
22U_0805_6.3V6M
+3VS
3VGS_PWR_EN
2
PU AT EC SIDE, +3VS AND 4.7K
OVERT
NC33
2 0_0402_5%
1
RV4
10K_0402_5%
@
1
RV9
QV1A
2N7002KDWH_SOT363-6
OPT@
@
2
1 0_0402_5%
{39,44}
{23}
4.7U_0402_6.3V6M
D
EC_SMB_DA2
FB_GC6_EN
0.1U_0402_10V7K
S
6
FB_GC6_EN
0.1U_0402_10V7K
2
G
1
VGA_SMB_DA2
{39,44}
C6
B2
D6
C7
F9
A3
A4
B6
E9
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
.1U_0402_10V6-K
D
EC_SMB_CK2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
2
S
3
QV1B
2N7002KDWH_SOT363-6
OPT@
RV7
2
1 0_0402_5%
@
GPIO
4
VGA_SMB_CK2
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
NC81
NC82
NC83
NC84
NC85
NC86
NC87
NC88
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
DACs
5
1
1
RV5
2.2K_0402_5%
OPT@
G
RV3
2.2K_0402_5%
OPT@
AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
PCI EXPRESS
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
+3VG_AON
2
2
+3VG_AON
I2C
D
.1U_0402_10V6-K
GPIO52
.1U_0402_10V6-K
{8}
1
2 LV1
+1.05VGS
PBY160808T-181Y-N_2P
OPT@
CV18
2
OPT@
2 RV38
OPT@ 10M_0402_5%
YV1
+3VG_AON
+3VG_AON
XTAL_IN
1
2
1
1
RV41
10K_0402_5%
@
RV46
10K_0402_5%
@
OSC2
Under GPU
4
Near GPU
30ohms (ESR=0.05) Bead
1
+PLLVDD
3
27MHZ_10PF_7V27000050
OPT@
2 LV2
+1.05VGS
XTAL_OUT
1
1
CV20
OPT@
CV21
0.1U_0402_10V7K
2
OPT@
2
PBY160808T-300Y-N_2P
OPT@
1
2
CV22
22U_0805_6.3V6M
OPT@
2
2
RV45
10K_0402_5%
@
3
2
QV6
2N7002KW_SOT323-3
@
RV47
10K_0402_5%
GC6@
Connect to CPU GPIO
1
A
FB_GC6_EN
S
1
1
G
2
FB_GC6_EN_R
2 RV49
GC6@ 0_0402_5%
Issued Date
Title
LC Future Center Secret Data
Security Classification
1
2 RV48
OPT@
0_0402_5%
CV24
@
D
1
CLK_REQ_GPU#
2
QV5
2N7002KW_SOT323-3
@
1
.1U_0402_10V6-K
RV44
10K_0402_5%
OPT@
3
1
GPU_CLKREQ#
2
2
1
D
{6}
2
G
A
2
CV19
OPT@
GND2
GND1
+3VG_AON
1
S
.1U_0402_10V6-K
+3VG_AON
CV23
@
1
OSC1
10P_0402_50V8J
RV40
10K_0402_5%
@
1
10P_0402_50V8J
2
2
Deciphered Date
2013/08/08
2013/08/05
N15X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
19
of
59
5
4
3
2
1
D
D
UV1C
Part 3 of 6
AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5
NC105
NC106
NC107
NC108
NC109
NC110
NC111
NC112
NC113
NC114
FERMI_RSVD1
FERMI_RSVD2
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC
AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5
NC50
NC51
NC52
NC115
NC116
NC117
NC118
NC119
NC120
NC121
NC122
NC123
NC124
NC125
NC126
NC127
NC128
NC129
NC130
NC131
NC132
C
V3
V4
U3
U4
T4
T5
R4
R5
N1
M1
M2
M3
K2
K3
K1
J1
M4
M5
L3
L4
K4
K5
J4
J5
N4
N5
P3
P4
B
J2
J3
H3
H4
NC133
NC134
NC135
NC136
NC137
NC138
NC139
NC140
PGOOD
GENERAL
LVDS/TMDS
BUFRST_N
T2
T3
T1
R1
R2
R3
N2
N3
NC71
NC72
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC73
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GNDMLS_REF1
MULTI_STRAP_REF2_GND
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
THERMDP
THERMDN
NC42
NC43
NC44
NC45
NC46
VDD_SENSE
F11
AD10
AD7
B19 Symbol update to FBA_CMD32
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
D11
2
@
1 RV50
10K_0402_5%
D10
E10
F10
Symbol update to GPIO8
D1
D2
E4
E3
D3
C1
F6
F4
F5
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
{28}
{28}
{28}
{28}
{28}
C
1
2 RV51
N15SGT@ 40.2K_0402_1%
F12
E12
F2
VCCSENSE_VGA
VCCSENSE_VGA
{58}
trace width: 16mils
differential voltage sensing.
differential signal routing.
NC47
NC48
GND_SENSE
NC49
NC141
NC142
F1
VSSSENSE_VGA
AD9
AE5
AE6
AF6
AD6
AG4
TESTMODE
@
@
@
@
VSSSENSE_VGA
{58}
TEST
NC143
NC144
NC145
NC146
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
NC147
NC148
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
1 OPT@
1
1
1
1
TV1
TV2
TV3
1TV4
OPT@
D12
B12
A12
C12
@ 1
ROM_SI
ROM_SO
ROM_SCLK
2 RV52
10K_0402_5%
B
2 RV53
10K_0402_5%
TV5
ROM_SI {28}
ROM_SO {28}
ROM_SCLK {28}
N15S-GT-S-A2_FCBGA595
OPT@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
N15X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
20
of
59
4
3
2
UV1D
+1.05VGS
G10
G12
CV48
1
2
OPT@
4.7U_0603_6.3V6K
2
OPT@
1U_0402_6.3V6K
1
+3VG_AON
Near
1
CV49
Under
CV47
2
CV215
2
@
2
OPT@
N15V-GM
D
N15S-GT
1.0uF
4
1
4.7uF
2
1
10uF
4
1
22uF
4
1
Place near GPU
+3VGS
RV54
FB_CAL_TERM
G8
G9
1
D22
1
C24
1
B25
1
OPT@
2 RV55
40.2_0402_1%
OPT@
2 RV56
42.2_0402_1%
OPT@
2 RV57
51.1_0402_1%
2
OPT@
1
2
OPT@
1
2
OPT@
1
CV53
1
CV52
+1.35VGS
4.7U_0603_6.3V6K
+VDD33
CV51
3V3_MAIN_1
3V3_MAIN_2
2
0_0603_5%
Change RV9 to 0ohm jump
2
OPT@
CALIBRATION PIN
DDR3
FB_CAL_x_PD_VDDQ
40.2Ohm
FB_CAL_x_PU_GND
42.2Ohm
FB_CAL_xTERM_GND
51.1Ohm
Place near balls
C
+3VG_AON
2
OPT@
1
CV57
1
2
OPT@
120ohm (ESR=0.18) Bead
2
OPT@
1
CV60
1
CV59
CV58
1U_0603_25V6M
2
OPT@
4.7U_0805_25V6-K
N15S-GT-S-A2_FCBGA595
OPT@
1
+1.05VGS
2
1 LV3
@
HCB1608KF-121T30_0603
+PEX_PLLVDD
.1U_0402_10V6-K
PEX_PLLVDD_1
PEX_PLLVDD_2
AA14
AA15
2
OPT@
4.7U_0603_6.3V6K
120mA
NC76
NC77
NC78
NC79
NC80
1
CV56
AA8
AA9
AB8
4.7U_0603_6.3V6K
PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
CV55
Under GPU(below 150mils)
PEX_SVDD_3V3
J7
K7
K6
H6
J6
1
PEX_IOVVDD/Q Decouling
Place near balls(Under GPU)
.1U_0402_10V6-K
NC158
NC159
NC160
NC161
1
MLCC
C
T7
R7
U6
R6
2
For RF
33P_0402_50V8J
1
N15VGM@CV42
1
2
N15VGM@CV41
2
10U_0603_6.3V6M
N15VGM@CV40
10U_0603_6.3V6M
CV39
1
OPT@
10U_0603_6.3V6M
N15VGM@CV38
10U_0603_6.3V6M
CV37
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
2
+1.05VGS
1
N15VGM@CV46
22U_0805_6.3V6M
2
N15VGM@CV45
N15VGM@CV44
2
1
.1U_0402_10V6-K
1U_0402_6.3V6K
N15VGM@CV36
1U_0402_6.3V6K
N15VGM@CV35
N15VGM@CV34
1U_0402_6.3V6K
1U_0402_6.3V6K
CV33
2
OPT@
1
1
+3VG_AON
3V3_AON_1
3V3_AON_2
FB_CAL_VDDQ
NC154
NC155
NC156
NC157
AA22
AB23
AC24
AD25
AE26
AE27
1
2
OPT@
Symbol update to 3V3_AON
FB_CAL_GND
M7
N7
T6
P6
2
Under GPU(below 150mils)
1
1U_0402_6.3V6K
NC150
NC151
NC152
NC153
2
1
CV50
W7
AA6
W6
Y6
NC149
2
1
.1U_0402_10V6-K
V7
FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4
2
OPT@
1
.1U_0402_10V6-K
H24
H26
J21
K21
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
1
22U_0805_6.3V6M
Symbol update to FBVDDQ_AON
H24/H26/J21/K21
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
22U_0805_6.3V6M
D
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
CV43
2
OPT@
Near GPU
2000mA
FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
POWER
2
OPT@
1
1
Part 4 of 6
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
L22
L24
L26
M21
N21
R21
T21
V21
W21
CV32
CV31
CV30
2
OPT@
1
0.1U_0402_10V7K
2
OPT@
1
3.5A
0.1U_0402_10V7K
CV29
CV28
2
OPT@
1
1U_0603_25V6M
2
OPT@
1
1U_0603_25V6M
1
OPT@
1
CV27
4.7U_0603_6.3V6K
2
OPT@
2
Under GPU(below 150mils)
CV26
CV25
1
10U_0603_6.3V6M
22U_0805_6.3V6M
Near GPU
4.7U_0603_6.3V6K
+1.35VGS
22U_0805_6.3V6M
5
2
2
1 RV62
OPT@ 0_0603_5%
OPT@
Place near balls
+3.3VS TO +3VG_AON
+3VS
+3VG_AON
+5VALW
1
B
+1.35V
+1.35V TO +1.35VGS
+1.35VGS
AON6414AL_DFN8-5
1
2
3
D
CV65
1
2
G
S 2N7002KW_SOT323-3
@
S 2N7002KW_SOT323-3
2
RV66 OPT@
100K_0402_5%
2
CV66
1
QV14
CV67
1
OPT@
4
QV13
PXS_PWREN#
2
2
CV68
1
2
CV69
1
2
CV70
1
RV67
470_0603_5%
@
2
1
+20VSB
+
1
5
OPT@
CV64
.1U_0402_10V6-K
2
CV63
10U_0603_6.3V6M
OPT@
.1U_0402_10V6-K
OPT@
2
10U_0603_6.3V6M
@
2
1
10U_0603_6.3V6M
OPT@
RV64
470_0603_5%
@
220U_B2_2.5VM_R15M
@
CV62
0.01U_0402_25V7K
@
10U_0603_6.3V6M
OPT@
3
2
10U_0603_6.3V6M
OPT@
2
1
1
1
OPT@
1
LP2301ALT1G_SOT23-3
2
3
1
2
G
PXS_PWREN
2 RV65
10K_0402_5%
OPT@
1
2
1
2
1
D
G
@
CV61
.1U_0402_10V6-K
PXS_PWREN#
{8,58}
OPT@
QV11
OPT@
RV63
47K_0402_5%
QV12
D
1
S
3
B
+5VALW
1
OPT@2 RV68
100K_0402_5%
2
FBVDDQ_PWR_EN#
2
1
N15VGM@
+5VALW
1
GC6@
2
QV20
DGPU_PWR_EN#
2
2
CV71
0.01U_0402_25V7K
OPT@
RV70
124K_0402_1%
OPT@
S
QV18
2N7002KW_SOT323-3
OPT@
3
FBVDDQ_PWR_EN
QV17
2N7002KW_SOT323-3
OPT@
S
CV74
10U_0603_6.3V6M
GC6@
A
D
2
G
@
S 2N7002KW_SOT323-3
Issued Date
Title
LC Future Center Secret Data
Security Classification
S 2N7002KW_SOT323-3
RV74 GC6@
100K_0402_5%
2013/08/08
Deciphered Date
2013/08/05
N15X_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
S
D
2
G
1
GC6@
CV75
.1U_0402_10V6-K
2
2
RV72
470_0603_5%
@
3
3
1
3VGS_PWR_EN
D
2
CV73
0.01U_0402_25V7K
@
1
2
{19,58}
1
QV19
2
G
LP2301ALT1G_SOT23-3
1
1 RV73
2
10K_0402_5%
GC6@
DGPU_PWR_EN#
1
2
1
2
@
CV72
.1U_0402_10V6-K
1
GC6@
G
A
1
{23}
D
S
3
QV16
GC6@
RV71
47K_0402_5%
D
2
G
3
47K_0402_5%
OPT@
1
3
1
1
RV171 1
0_0603_5%
QV15
2N7002KW_SOT323-3
@
G
1
RV69
+3.3VS TO +3VGS
D
2
2
+3VGS
+3VG_AON
FBVDDQ_PWR_EN#
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
21
of
59
5
4
3
2
1
D
D
UV1E
UV1F
GND_113
GND_114
+VGA_CORE
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
+VGA_CORE
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
+VGA_CORE
2
OPT@
2
OPT@
1
2
OPT@
OPT@
OPT@
OPT@
OPT@
2
@
2
@
1
CV88
1
CV87
1
4.7U_0603_6.3V6K
2
CV86
1
4.7U_0603_6.3V6K
2
CV85
1
4.7U_0603_6.3V6K
2
CV84
CV83
1
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K
CV82
1
4.7U_0603_6.3V6K
CV81
CV80
4.7U_0603_6.3V6K
2
2
@
1
CV213
For RF
33P_0402_50V8J
VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021
2
@
2
@
N15S-GT-S-A2_FCBGA595
OPT@
1
CV102
CV101
CV100
2
@
1
4.7U_0603_6.3V6K
2
@
1
4.7U_0603_6.3V6K
2
@
1
CV99
CV98
CV97
2
OPT@
1
4.7U_0603_6.3V6K
C
4.7U_0603_6.3V6K
2
OPT@
1
1
OPT@
4.7U_0603_6.3V6K
1
4.7U_0603_6.3V6K
CV79
2
OPT@
CV96
CV78
4.7U_0603_6.3V6K
OPT@
CV92
1
2
4.7U_0603_6.3V6K
1U_0402_6.3V6K
CV91
2
OPT@
OPT@
1
VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14
2
@
For RF
CV214
1
CV95
2
OPT@
2
4.7U_0603_6.3V6K
1
1
CV105
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV77
2
1U_0402_6.3V6K
CV90
CV94
1
OPT@
22U_0805_6.3V6M
1
2
OPT@
2
33P_0402_50V8J
2
OPT@
1
1
OPT@
4.7U_0603_6.3V6K
1
1U_0402_6.3V6K
2
OPT@
2
OPT@
4.7U_0603_6.3V6K
CV89
1
CV93
1U_0402_6.3V6K
OPT@
1
CV104
2
22U_0805_6.3V6M
CV76
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU
POWER
Part 6 of 6
4.7U_0603_6.3V6K
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
CV103
Part 5 of 6
22U_0805_6.3V6M
C
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
1
2
@
Near GPU
AA7
AB7
N15S-GT-S-A2_FCBGA595
OPT@
B
B
2
+3VGS
1
RV176
10K_0402_5%
OPT@
+VGA_CORE
DV5
+3VG_AON
+5VALW
1
{57}
2
1 2
{8,44}
2
47K_0402_5%
OPT@
1
QV25
2N7002KW_SOT323-3
OPT@
S
S
2N7002KW_SOT323-3
+1.35VGS
1
@
RV177
C
2
B
CV219
1
OPT@2
2.2K_0402_5%
1
A
2
@
.1U_0402_10V6-K
S
2N7002KW_SOT323-3
QV24
MMBT3904WH_SOT323-3
E
3
QV21
@
VGA_PWRGD
BAT54AWT1G_SOT323-3
OPT@
D
D
G
3
2
1
QV22
10K_0402_5%
OPT@
2
G
3
2
1
1
EN_VGA
3
{57,58}
RV179
RV178
D
2
G
1
3
+5VALW
RV173
470_0603_5%
@
RV172
47K_0402_5%
@
2
+1.05VGS_PWRGD
1
OPT@
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
N15X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
22
of
59
5
{24,25,26,27}
4
3
2
1
FBA_D[0..63]
FBA_D[0..63]
{24,25,26,27} FBA_DQM[7..0]
{24,25,26,27} FBA_DQS[7..0]
{24,25,26,27} FBA_DQS#[7..0]
{24,25,26,27}
FBA_CMD[30..0]
UV1B
D
Only Dual Rank need Termination
D
CMD mapping mod Mode E
Part 2 of 6
OPT@
Place close to BGA
2
OPT@
2
OPT@
1
CV113
CV112
1
0.1U_0402_10V7K
1
CV111
22U_0805_6.3V6M
+FB_PLLAVDD
Place close to ball
1U_0402_6.3V6K
Place close to BGA
2
OPT@
F16
P22
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FB_PLLAVDD_1
FB_PLLAVDD_2
D23
+FB_PLLAVDD
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_CLK1
FBA_CLK1_N
FB_VREF
Place close to ball
B
FB_GC6_EN
1
2
OPT@
2
RV119 1
@
RV120 1 OPT@
H22
CV115
0.1U_0402_10V7K
FB_CLAMP F3
0_0402_5%
2 10K_0402_5%
FBA_CLK0
FBA_CLK0_N
FB_DLLAVDD
FB_CLAMP
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_RAS#
FBA_CMD12
2
2
@
FBA_CMD13
1 60.4_0402_1%
1 60.4_0402_1%
FBA_CMD14
@
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_CAS#
FBA_CMD21
FBA_CMD22
F19
C14
A16
A22
P25
W22
AB27
T27
FBA_DQS#0
FBA_DQS#1
FBA_DQS#2
FBA_DQS#3
FBA_DQS#4
FBA_DQS#5
FBA_DQS#6
FBA_DQS#7
E19
C15
B16
B22
R25
W23
AB26
T26
FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
D24
D25
FBA_CLK0
FBA_CLK0#
N22
M22
FBA_CLK1
FBA_CLK1#
FBA_CLK0 {24,26}
FBA_CLK0# {24,26}
FBA_CMD29
FBA_CLK1 {25,27}
FBA_CLK1# {25,27}
FBA_CMD30
D18
C18
D17
D16
T24
U24
V24
V25
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
0..31
ODT_L
32..63
0..31
32..63
ODT_L
CS1#_L
FBx_CMD2
CS0#_L
FBx_CMD3
CKE_L
2
FBx_CMD4
A9
A9
A11
A11
@
FBx_CMD5
A6
A6
A7
A7
FBx_CMD6
A3
A3
BA1
BA1
FBx_CMD7
A0
A0
A12
A12
FBx_CMD8
A8
A8
A8
A8
2
FBx_CMD9
A12
A12
A0
A0
@
FBx_CMD10
A1
A1
A2
A2
FBx_CMD11
RAS#
RAS#
RAS#
RAS#
FBx_CMD12
A13
A13
A14
A14
FBx_CMD13
BA1
BA1
A3
A3
FBx_CMD14
A14
A14
A13
A13
2
FBx_CMD15
CAS#
CAS#
CAS#
CAS#
@
FBx_CMD16
1
1
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
Address
FBx_CMD0
FBx_CMD1
CV106
0.1U_0402_10V7K
2 100_0402_5%
2 100_0402_5%
CV107
FBA_CMD7
FBA_CAS# {24,25,26,27}
FBA_ODT_H {25,27}
FBA_CS1#_H {27}
FBA_CS0#_H {25}
FBA_CKE_H {25,27}
FBA_RST# {24,25,26,27}
2 100_0402_5%
2 100_0402_5%
0.1U_0402_10V7K
FBA_CMD6
OPT@
RV77 1 OPT@
RV78 1
OPT@
RV79 1 OPT@
RV80 1
OPT@
1
RV81
OPT@
RV82 1
OPT@
RV83 1 OPT@
RV84 1
OPT@
RV85 1 OPT@
RV86 1
OPT@
RV87 1 OPT@
RV88 1
OPT@
RV89 1 OPT@
RV90 1
OPT@
RV91 1 OPT@
RV92 1
OPT@
RV93 1 OPT@
RV94 1
OPT@
RV95 1 OPT@
RV96 1
OPT@
RV97 1 OPT@
RV98 1
OPT@
RV99 1 OPT@
RV100 1
OPT@
RV101 1 OPT@
RV102 1
OPT@
RV103 1 OPT@
RV104 1
OPT@
RV105 1 OPT@
RV106 1
OPT@
RV107 1 OPT@
RV108 1
OPT@
RV109 1 OPT@
RV110 1
OPT@
RV111 1 OPT@
RV112 1
OPT@
RV113 1 OPT@
RV114 1
OPT@
RV115 1 OPT@
RV116 1
OPT@
RV117 1 OPT@
RV118 1
OPT@
OPT@
1
CV108
{24,25,26,27}
FBA_RAS#
RV75 1
RV76 1
0.1U_0402_10V7K
FBA_CMD5
2 100_0402_5%
2 100_0402_5%
CKE_L
ODT_H
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
CS1#_H
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
CKE_H
FBx_CMD20
RST
RST
RST
RST
FBx_CMD21
A7
A7
A6
A6
@
FBx_CMD22
A4
A4
A5
A5
FBx_CMD23
A11
A11
A9
A9
FBx_CMD24
A2
A2
A1
A1
FBx_CMD25
A10
A10
WE#
WE#
FBx_CMD26
A5
A5
A4
A4
2
FBx_CMD27
BA2
BA2
@
FBx_CMD28
WE#
WE#
A10
A10
FBx_CMD29
BA0
BA0
BA0
BA0
BA2
BA2
1
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
CKE_H
FBx_CMD19
2
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
2 100_0402_5%
CS0#_H
FBx_CMD18
1
FBx_CMD30
1
C
ODT_H
FBx_CMD17
2 100_0402_5%
2 100_0402_5%
CV109
FBA_CMD4
Symbol update to +1.35VGS
FBA_CMD34/35
F22 RV121
J22 RV122
D19
D14
C17
C22
P24
W24
AA25
U25
+1.35VGS
FBA_ODT_L {24,26}
FBA_CS1#_L {26}
FBA_CS0#_L {24}
FBA_CKE_L {24,26}
0.1U_0402_10V7K
2 LV4
HCB1608KF-300T60_2P
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_ODT_L
FBA_CS1#_L
FBA_CS0#_L
FBA_CKE_L
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_RAS#
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CAS#
FBA_ODT_H
FBA_CS1#_H
FBA_CS0#_H
FBA_CKE_H
FBA_RST#
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
CV110
+FB_PLLAVDD
200mA
1
FBA_CMD34
FBA_CMD35
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
B19
0.1U_0402_10V7K
+1.05VGS
FBA_CMD00
FBA_CMD01
FBA_CMD02
FBA_CMD03
FBA_CMD04
FBA_CMD05
FBA_CMD06
FBA_CMD07
FBA_CMD08
FBA_CMD09
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
Rank1
CV114
30ohms (ESR=0.01) Bead
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
0.1U_0402_10V7K
C
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
MEMORY
INTERFACE A
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
Rank0
2
B
@
N15S-GT-S-A2_FCBGA595
OPT@
DV4 GC6@
FB_GC6_ENRV123 1
FB_GC6_EN
2 0_0402_5%
GC6_EN 2
1
+3VGS
{57,58}
DGPU_PWROK
A
RV124
1
2
10K_0402_5%
OPT@
FBVDDQ_PWR_EN
BAV70W-7-F_SOT323-3
1
{21}
1
3
2 RV126
0_0402_5%
N15VGM@
RV125
200K_0402_5%
GC6@
2
{19}
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
N15X_MEM Interface
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
23
of
59
5
4
3
2
1
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
FBA_D[0..63]
{23,25,26,27}
+1.35VGS
FBA_CMD[30..0]
{23,25,26,27}
FBA_DQM[7..0]
{23,25,26,27}
FBA_DQS[7..0]
{23,25,26,27}
FBA_DQS#[7..0]
{23,25,26,27}
D
1
D
RANKA@
RV128
1.33K_0402_1%
2
UV6
+FBA_VREFCA0
+FBA_VREFCA0
+FBA_VREFDQ0
{26}
1
+FBA_VREFCA0
2
RANKA@
RV127
1.33K_0402_1%
1
2
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
CV116
.01U_0402_16V7-K
RANKA@
1
+1.35VGS
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
+FBA_VREFDQ0
2
RANKA@
RV168
1.33K_0402_1%
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
UV5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D5
FBA_D1
FBA_D7
FBA_D0
FBA_D4
FBA_D3
FBA_D6
FBA_D2
M8
H1
+FBA_VREFCA0
+FBA_VREFDQ0
Group0
FBA_D31
FBA_D25
FBA_D30
FBA_D24
FBA_D29
FBA_D27
FBA_D28
FBA_D26
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
Group3
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D11
FBA_D13
FBA_D8
FBA_D15
FBA_D10
FBA_D14
FBA_D9
FBA_D12
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D17
FBA_D22
FBA_D16
FBA_D23
FBA_D19
FBA_D21
FBA_D18
FBA_D20
+1.35VGS
+FBA_VREFDQ0
FBA_CMD29
FBA_CMD13
FBA_CMD27
{26}
1
2
RANKA@
RV167
1.33K_0402_1%
VREFCA
VREFDQ
1
2
CV216
.01U_0402_16V7-K
RANKA@
{23,26}
{23,26}
{23,26}
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
M2
N8
M3
J7
K7
K9
BA0
BA1
BA2
CK
CK
CKE
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
Group1
Rank0
M2
N8
M3
FBA_CMD29
FBA_CMD13
FBA_CMD27
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
J7
K7
K9
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
Address
0..31
FBx_CMD0
ODT_L
Rank1
32..63
B2
D9
G7
K2
K8
N1
N9
R1
R9
0..31
32..63
ODT_L
FBx_CMD1
Group2
+1.35VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMD mapping mod Mode E
CS1#_L
FBx_CMD2
CS0#_L
FBx_CMD3
CKE_L
FBx_CMD4
A9
A9
A11
A11
FBx_CMD5
A6
A6
A7
A7
FBx_CMD6
A3
A3
BA1
BA1
FBx_CMD7
A0
A0
A12
A12
FBx_CMD8
A8
A8
A8
A8
FBx_CMD9
A12
A12
A0
A0
FBx_CMD10
A1
A1
A2
A2
FBx_CMD11
RAS#
RAS#
RAS#
RAS#
FBx_CMD12
A13
A13
A14
A14
FBx_CMD13
BA1
BA1
A3
A3
FBx_CMD14
A14
A14
A13
A13
FBx_CMD15
CAS#
CAS#
CAS#
CAS#
CKE_L
C
C
K1
L2
J3
K3
L3
FBA_DQS0
FBA_DQS3
F3
C7
FBA_DQM0
FBA_DQM3
RV129
162_0402_1%
RANKA@
E7
D3
2
FBA_DQS#0 G3
FBA_DQS#3 B7
FBA_CLK0#
{23,25,26,27}
FBA_RST#
1
1
RV131
10K_0402_5%
RANKA@
1
1
FBA_CKE_L
2
RV134
10K_0402_5%
RANKA@
+1.35VGS
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_CMD28
K1
L2
J3
K3
L3
FBA_DQS1
FBA_DQS2
F3
C7
E7
D3
FBA_DQM1
FBA_DQM2
FBA_DQS#1 G3
FBA_DQS#2 B7
T2
FBA_RST#
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV132
243_0402_1%
RANKA@
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
2
RV133
10K_0402_5%
RANKA@
B
L8
2 RV130
243_0402_1%
RANKA@
J1
L1
J9
L9
M7
2
FBA_ODT_L
T2
FBA_RST#
ODT
CS
RAS
CAS
WE
1
1
FBA_CLK0
FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_CMD28
2
{23,26} FBA_ODT_L
{23} FBA_CS0#_L
{23,25,26,27} FBA_RAS#
{23,25,26,27} FBA_CAS#
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBx_CMD16
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
+1.35VGS
ODT_H
ODT_H
FBx_CMD17
CS1#_H
FBx_CMD18
CS0#_H
FBx_CMD19
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
+1.35VGS
UV6 SIDE
ODT
CS
RAS
CAS
WE
CKE_H
CKE_H
FBx_CMD20
RST
RST
RST
RST
FBx_CMD21
A7
A7
A6
A6
FBx_CMD22
A4
A4
A5
A5
FBx_CMD23
A11
A11
A9
A9
FBx_CMD24
A2
A2
A1
A1
FBx_CMD25
A10
A10
WE#
WE#
FBx_CMD26
A5
A5
A4
A4
FBx_CMD27
BA2
BA2
FBx_CMD28
WE#
WE#
A10
A10
FBx_CMD29
BA0
BA0
BA0
BA0
BA2
BA2
FBx_CMD30
B
+1.35VGS
UV5 SIDE
RANKA@
RANKA@
RANKA@
RANKA@
RANKA@
@
RANKA@
RANKA@
RANKA@
RANKA@
2
RANKA@
2
RANKA@
1
CV139
1
CV134
1
33P_0402_50V8J
2
CV133
1
1U_0603_25V6M
2
CV132
1
1U_0603_25V6M
2
CV131
1
1U_0603_25V6M
2
CV130
CV129
1
1U_0603_25V6M
2
0.1U_0402_10V7K
For RF
RANKA@
1
0.1U_0402_10V7K
2
CV127
CV122
1
33P_0402_50V8J
2
CV121
1
1U_0603_25V6M
2
CV120
1
1U_0603_25V6M
2
CV119
1
1U_0603_25V6M
2
CV118
1
1U_0603_25V6M
2
0.1U_0402_10V7K
1
CV117
0.1U_0402_10V7K
For RF
2
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
DDR3 VRAM Rank0_L
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
24
of
59
5
4
3
2
1
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
1
+1.35VGS
D
FBA_D[0..63]
RANKA@
RV135
1.33K_0402_1%
+FBA_VREFCA1
+FBA_VREFCA1
{27}
+FBA_VREFCA1
+FBA_VREFDQ1
1
1
2
CV141
.01U_0402_16V7-K
RANKA@
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
1
+1.35VGS
RANKA@
RV169
1.33K_0402_1%
2
+FBA_VREFDQ1
{27}
1
2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
1
2
FBA_CMD29
FBA_CMD13
FBA_CMD27
M2
N8
M3
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
J7
K7
K9
CV217
.01U_0402_16V7-K
RANKA@
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
{23,27}
{23,27}
{23,27}
C
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
{23,27}
{23}
{23,24,26,27}
{23,24,26,27}
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_CMD28
K1
L2
J3
K3
L3
FBA_DQS4
FBA_DQS7
F3
C7
1
FBA_CLK1
RV137
162_0402_1%
2
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D34
FBA_D38
FBA_D35
FBA_D39
FBA_D32
FBA_D36
FBA_D33
FBA_D37
FBA_D59
FBA_D62
FBA_D58
FBA_D63
FBA_D57
FBA_D60
FBA_D56
FBA_D61
M8
H1
+FBA_VREFCA1
+FBA_VREFDQ1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
Group4
Group7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D44
FBA_D43
FBA_D45
FBA_D40
FBA_D47
FBA_D42
FBA_D46
FBA_D41
D7
C3
C8
C2
A7
A2
B8
A3
FBA_DQM4
FBA_DQM7
RANKA@
E7
D3
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
FBA_CLK1#
FBA_DQS#4 G3
FBA_DQS#7 B7
{23,24,26,27}
FBA_RST#
FBA_RST#
T2
L8
FBA_CKE_H
1
J1
L1
J9
L9
M7
RV140
243_0402_1%
RANKA@
2
1
1
FBA_ODT_H
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
M2
N8
M3
FBA_CMD29
FBA_CMD13
FBA_CMD27
J7
FBA_CLK1
FBA_CLK1# K7
FBA_CKE_H K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_CMD28
K1
L2
J3
K3
L3
FBA_DQS5
FBA_DQS6
F3
C7
E7
D3
FBA_DQM5
FBA_DQM6
FBA_DQS#5 G3
FBA_DQS#6 B7
T2
FBA_RST#
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV141
243_0402_1%
RANKA@
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
FBA_DQM[7..0]
{23,24,26,27}
FBA_DQS[7..0]
{23,24,26,27}
FBA_DQS#[7..0]
{23,24,26,27}
CMD mapping mod Mode E
Rank0
Group6
Address
0..31
FBx_CMD0
ODT_L
Rank1
32..63
0..31
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
32..63
ODT_L
CS1#_L
FBx_CMD1
+1.35VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9
D
{23,24,26,27}
FBx_CMD2
CS0#_L
FBx_CMD3
CKE_L
FBx_CMD4
A9
A9
A11
A11
FBx_CMD5
A6
A6
A7
A7
FBx_CMD6
A3
A3
BA1
BA1
FBx_CMD7
A0
A0
A12
A12
FBx_CMD8
A8
A8
A8
A8
FBx_CMD9
A12
A12
A0
A0
FBx_CMD10
A1
A1
A2
A2
FBx_CMD11
RAS#
RAS#
RAS#
RAS#
FBx_CMD12
A13
A13
A14
A14
FBx_CMD13
BA1
BA1
A3
A3
FBx_CMD14
A14
A14
A13
A13
FBx_CMD15
CAS#
CAS#
CAS#
CAS#
CKE_L
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
ODT_H
ODT_H
FBx_CMD16
CS1#_H
FBx_CMD17
B1
B9
D1
D8
E2
E8
F9
G1
G9
FBx_CMD18
CS0#_H
FBx_CMD19
CKE_H
CKE_H
FBx_CMD20
RST
RST
RST
RST
FBx_CMD21
A7
A7
A6
A6
FBx_CMD22
A4
A4
A5
A5
FBx_CMD23
A11
A11
A9
A9
FBx_CMD24
A2
A2
A1
A1
FBx_CMD25
A10
A10
WE#
WE#
FBx_CMD26
A5
A5
A4
A4
FBx_CMD27
BA2
BA2
FBx_CMD28
WE#
WE#
A10
A10
FBx_CMD29
BA0
BA0
BA0
BA0
BA2
BA2
2
2
RV138
RV139
10K_0402_5% 10K_0402_5%
RANKA@
RANKA@
DQSL
DQSU
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
Group5
FBA_D52
FBA_D50
FBA_D55
FBA_D51
FBA_D53
FBA_D48
FBA_D54
FBA_D49
+1.35VGS
+FBA_VREFDQ1
RANKA@
RV170
1.33K_0402_1%
M8
H1
1
2
RANKA@
RV136
1.33K_0402_1%
{23,24,26,27}
FBA_CMD[30..0]
UV7
2
2
UV8
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
B
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
FBx_CMD30
RANKA@
RANKA@
RANKA@
RANKA@
2
RANKA@
2
RANKA@
2
RANKA@
@
1
CV164
1
CV159
1
CV158
1
1U_0603_25V6M
2
CV157
1
1U_0603_25V6M
2
CV156
1
1U_0603_25V6M
2
CV155
1
1U_0603_25V6M
2
CV154
1
CV152
CV147
2
For RF
33P_0402_50V8J
RANKA@
1
+1.35VGS
UV7 SIDE
0.1U_0402_10V7K
2
CV146
CV145
RANKA@
1
1U_0603_25V6M
2
+1.35VGS
0.1U_0402_10V7K
RANKA@
1
1U_0603_25V6M
2
CV144
CV143
RANKA@
1
1U_0603_25V6M
2
For RF
33P_0402_50V8J
RANKA@
1
1U_0603_25V6M
2
CV142
1
+1.35VGS
UV8 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.35VGS
B
2
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
DDR3 VRAM Rank0_H
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
25
of
59
5
4
3
2
1
FBA_D[0..63]
D
UV9
{24}
{24}
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
+FBA_VREFCA0
+FBA_VREFDQ0
+FBA_VREFCA0
+FBA_VREFDQ0
M8
H1
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
FBA_CMD29
FBA_CMD6
FBA_CMD30
M2
N8
M3
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D1
FBA_D5
FBA_D0
FBA_D7
FBA_D2
FBA_D6
FBA_D3
FBA_D4
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D25
FBA_D31
FBA_D24
FBA_D30
FBA_D26
FBA_D28
FBA_D27
FBA_D29
M8
H1
+FBA_VREFCA0
+FBA_VREFDQ0
Group0
Group3
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
FBA_CMD29
FBA_CMD6
FBA_CMD30
M2
N8
M3
FBA_ODT_L
FBA_CS1#_L
FBA_RAS#
FBA_CAS#
FBA_CMD25
K1
L2
J3
K3
L3
FBA_DQS0
FBA_DQS3
F3
C7
FBA_DQM0
FBA_DQM3
E7
D3
FBA_DQS#0 G3
FBA_DQS#3 B7
{23,24,25,27}
FBA_RST#
FBA_RST#
1
T2
L8
2 RV142
243_0402_1%
RANKB@
J1
L1
J9
L9
M7
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
J7
K7
K9
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_ODT_L
FBA_CS1#_L
FBA_RAS#
FBA_CAS#
FBA_CMD25
K1
L2
J3
K3
L3
FBA_DQS1
FBA_DQS2
F3
C7
E7
D3
FBA_DQM1
FBA_DQM2
FBA_DQS#1 G3
FBA_DQS#2 B7
T2
FBA_RST#
L8
1
{23,24} FBA_ODT_L
{23} FBA_CS1#_L
{23,24,25,27} FBA_RAS#
{23,24,25,27} FBA_CAS#
J7
K7
K9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV143
243_0402_1%
RANKB@
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
B
{23,24,25,27}
FBA_DQS[7..0]
{23,24,25,27}
FBA_DQS#[7..0]
{23,24,25,27}
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D13
FBA_D11
FBA_D15
FBA_D8
FBA_D12
FBA_D9
FBA_D14
FBA_D10
Group1
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D22
FBA_D17
FBA_D23
FBA_D16
FBA_D20
FBA_D18
FBA_D21
FBA_D19
Group2
CMD mapping mod Mode E
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
Rank0
B2
D9
G7
K2
K8
N1
N9
R1
R9
Address
0..31
FBx_CMD0
ODT_L
Rank1
32..63
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
CS1#_L
CS0#_L
FBx_CMD3
CKE_L
FBx_CMD4
A9
A9
A11
A11
FBx_CMD5
A6
A6
A7
A7
FBx_CMD6
A3
A3
BA1
BA1
FBx_CMD7
A0
A0
A12
A12
CKE_L
FBx_CMD8
A8
A8
A8
A8
FBx_CMD9
A12
A12
A0
A0
FBx_CMD10
A1
A1
A2
A2
FBx_CMD11
RAS#
RAS#
RAS#
RAS#
FBx_CMD12
A13
A13
A14
A14
FBx_CMD13
BA1
BA1
A3
A3
FBx_CMD14
A14
A14
A13
A13
FBx_CMD15
CAS#
CAS#
CAS#
CAS#
CS1#_H
FBx_CMD18
CS0#_H
FBx_CMD19
RANKB@
RANKB@
RANKB@
RANKB@
RANKB@
RST
RST
RST
RST
FBx_CMD21
A7
A7
A6
A6
FBx_CMD22
A4
A4
A5
A5
FBx_CMD23
A11
A11
A9
A9
FBx_CMD24
A2
A2
A1
A1
@
A10
A10
WE#
WE#
A5
A5
A4
A4
FBx_CMD27
BA2
BA2
FBx_CMD28
WE#
WE#
A10
A10
FBx_CMD29
BA0
BA0
BA0
BA0
BA2
BA2
RANKB@
RANKB@
RANKB@
2
RANKB@
2
RANKB@
2
RANKB@
1
CV188
1
CV183
1
CV182
CV181
1
1U_0603_25V6M
2
CV180
1
1U_0603_25V6M
2
CV179
1
For RF
33P_0402_50V8J
+1.35VGS
1U_0603_25V6M
2
CV178
1
1U_0603_25V6M
2
B
FBx_CMD26
UV3 SIDE
0.1U_0402_10V7K
1
0.1U_0402_10V7K
2
+1.35VGS
CV176
CV171
1
33P_0402_50V8J
2
CV170
1
1U_0603_25V6M
2
CV169
1
1U_0603_25V6M
2
CV168
1
1U_0603_25V6M
2
CV167
CV166
RANKB@
1
1U_0603_25V6M
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
+1.35VGS
CKE_H
CKE_H
FBx_CMD20
FBx_CMD30
For RF
C
ODT_H
ODT_H
FBx_CMD17
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
UV4 SIDE
32..63
FBx_CMD2
FBx_CMD16
B1
B9
D1
D8
E2
E8
F9
G1
G9
0..31
ODT_L
FBx_CMD1
FBx_CMD25
+1.35VGS
D
+1.35VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9
2
C
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
{23,24}
{23,24}
{23,24}
{23,24,25,27}
FBA_DQM[7..0]
UV10
+1.35VGS
BA0
BA1
BA2
{23,24,25,27}
FBA_CMD[30..0]
2
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
DDR3 VRAM Rank1_L
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
26
of
59
5
4
3
2
1
FBA_D[0..63]
{23,24,25,26}
FBA_CMD[30..0]
{23,24,25,26}
FBA_DQM[7..0]
{23,24,25,26}
FBA_DQS[7..0]
{23,24,25,26}
FBA_DQS#[7..0]
{23,24,25,26}
D
D
UV11
{25}
{25}
M8
H1
+FBA_VREFCA1
+FBA_VREFDQ1
+FBA_VREFCA1
+FBA_VREFDQ1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D38
FBA_D34
FBA_D39
FBA_D35
FBA_D37
FBA_D33
FBA_D36
FBA_D32
FBA_D62
FBA_D59
FBA_D63
FBA_D58
FBA_D61
FBA_D56
FBA_D60
FBA_D57
+FBA_VREFCA1
+FBA_VREFDQ1
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
Group4
Group7
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D43
FBA_D44
FBA_D40
FBA_D45
FBA_D41
FBA_D46
FBA_D42
FBA_D47
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D50
FBA_D52
FBA_D51
FBA_D55
FBA_D49
FBA_D54
FBA_D48
FBA_D53
+1.35VGS
FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
J7
K7
K9
FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#
FBA_CMD25
K1
L2
J3
K3
L3
FBA_DQS4
FBA_DQS7
F3
C7
E7
D3
FBA_DQM4
FBA_DQM7
FBA_DQS#4 G3
FBA_DQS#7 B7
{23,24,25,26}
T2
FBA_RST#
FBA_RST#
L8
1
J1
L1
J9
L9
M7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
2
RV144
243_0402_1%
RANKB@
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
FBA_CMD29
FBA_CMD6
FBA_CMD30
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#
FBA_CMD25
K1
L2
J3
K3
L3
FBA_DQS5
FBA_DQS6
F3
C7
FBA_DQM5
FBA_DQM6
E7
D3
FBA_DQS#5 G3
FBA_DQS#6 B7
FBA_RST#
T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
RV145
243_0402_1%
RANKB@
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
B
M2
N8
M3
J7
FBA_CLK1
FBA_CLK1# K7
FBA_CKE_H K9
1
{23,25}
{23}
{23,24,25,26}
{23,24,25,26}
C
M2
N8
M3
Group6
CMD mapping mod Mode E
Rank0
+1.35VGS
2
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
{23,25}
{23,25}
{23,25}
FBA_CMD29
FBA_CMD6
FBA_CMD30
Group5
J1
L1
J9
L9
M7
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
Address
0..31
FBx_CMD0
ODT_L
Rank1
32..63
0..31
FBx_CMD1
FBx_CMD2
A1
A8
C1
C9
D2
E9
F1
H2
H9
CS1#_L
CS0#_L
FBx_CMD3
CKE_L
FBx_CMD4
A9
A9
A11
A11
FBx_CMD5
A6
A6
A7
A7
FBx_CMD6
A3
A3
BA1
BA1
FBx_CMD7
A0
A0
A12
A12
CKE_L
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBx_CMD8
A8
A8
A8
A8
FBx_CMD9
A12
A12
A0
A0
FBx_CMD10
A1
A1
A2
A2
FBx_CMD11
RAS#
RAS#
RAS#
RAS#
FBx_CMD12
A13
A13
A14
A14
FBx_CMD13
BA1
BA1
A3
A3
FBx_CMD14
A14
A14
A13
A13
FBx_CMD15
CAS#
CAS#
CAS#
CAS#
ODT_H
ODT_H
FBx_CMD16
CS1#_H
FBx_CMD17
B1
B9
D1
D8
E2
E8
F9
G1
G9
FBx_CMD18
CS0#_H
96-BALL
SDRAM DDR3
K4W4G1646B-HC11_FBGA96
@
CKE_H
CKE_H
FBx_CMD19
FBx_CMD20
RST
RST
RST
RST
FBx_CMD21
A7
A7
A6
A6
FBx_CMD22
A4
A4
A5
A5
FBx_CMD23
A11
A11
A9
A9
FBx_CMD24
A2
A2
A1
A1
FBx_CMD25
A10
A10
WE#
WE#
FBx_CMD26
A5
A5
A4
A4
FBx_CMD27
BA2
BA2
FBx_CMD28
WE#
WE#
A10
A10
FBx_CMD29
BA0
BA0
BA0
BA0
BA2
BA2
FBx_CMD30
+1.35VGS
+1.35VGS
UV6 SIDE
+1.35VGS
RANKB@
RANKB@
RANKB@
RANKB@
RANKB@
2
RANKB@
2
RANKB@
1
CV207
1
CV206
1
33P_0402_50V8J
2
CV205
1
1U_0603_25V6M
2
CV204
1
1U_0603_25V6M
2
CV203
1
1U_0603_25V6M
2
CV202
1
1U_0603_25V6M
2
CV200
CV195
1
33P_0402_50V8J
2
CV194
CV193
RANKB@
1
1U_0603_25V6M
2
0.1U_0402_10V7K
RANKB@
1
1U_0603_25V6M
2
CV192
CV191
RANKB@
1
1U_0603_25V6M
2
For RF
0.1U_0402_10V7K
RANKB@
1
1U_0603_25V6M
CV190
0.1U_0402_10V7K
0.1U_0402_10V7K
2
B
+1.35VGS
UV5 SIDE
For RF
1
32..63
ODT_L
2
1
CV212
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
UV12
2
RANKB@
@
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
DDR3 VRAM Rank1_H
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
27
of
59
5
4
3
Physical
Strapping pin
ROM_SCLK
+3VG_AON
2
RV150
45.3K_0402_1%
@
1
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
+3VGS
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
ROM_SI
+3VGS
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
+3VGS
DEVID_SEL
PCIE_CFG
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
+3VGS
STRAP1
+3VGS
STRAP2
+3VGS
STRAP3
+3VGS
STRAP4
+3VGS
Power Rail
D
Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
1
RV149
4.99K_0402_1%
@
1
RV148
24.9K_0402_1%
@
1
RV147
4.99K_0402_1%
@
1
1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
RV155
10K_0402_1%
OPT@
1
RV154
4.99K_0402_1%
@
1
RV153
15K_0402_1%
@
1
RV152
4.99K_0402_1%
@
1
1
RV151
45.3K_0402_1%
@
2
2
Reserved(keep pull-up and pull-down footprint and not stuff by default)
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
{20}
{20}
{20}
{20}
{20}
2
2
2
2
D
RV146
49.9K_0402_1%
N15SGT@
2
+3VGS
C
DEVID_SEL
Pull-up to
+3VGS
1000
Pull-down to Gnd
1001
0001
15K
1010
0010
20K
1011
0011
24.9K
SD03424928J
30.1K
SD03430128J
34.8K
SD03434828J
45.3K
SD03445328J
1100
0100
1101
0101
1110
0110
1111
0111
Resistor Values
4.99K
SD03449918J
10K
0
(Default)
0000
1
PCIE_CFG
0
(Default)
1
C
Physical
Strapping pin
ROM_SCLK
2
2
RV161
10K_0402_1%
OPT@
1
1
RV160
10K_0402_1%
OPT@
1
RV159
10K_0402_1%
OPT@
X76
Power Rail
0
0x9E (Default)
1
0x9C (Multi-GPU usage)
Strap Mapping
+3VGS
SMB_ALT_ADDR
ROM_SI
+3VGS
SUB_VENDOR
ROM_SO
+3VGS
VGA_DEVICE
VGA_DEVICE
STRAP0
+3VGS
RAM_CFG[0]
0
3D Device (Class Code 302h)
STRAP1
+3VGS
RAM_CFG[1]
1
VGA Device (Default)
1
RV158
4.99K_0402_1%
@
ROM_SI
ROM_SO
ROM_SCLK
2
{20} ROM_SI
{20} ROM_SO
{20} ROM_SCLK
RV157
4.99K_0402_1%
@
1
1
RV156
4.99K_0402_1%
@
2
2
2
SMBUS_ALT_ADDR
STRAP2
+3VGS
RAM_CFG[2]
STRAP3
+3VGS
RAM_CFG[3]
STRAP4
+3VGS
PCIE_MAX_SPEED
X76
GPU
B
FB Memory (DDR3)
Hynix
900MHz
N15S-GT
Micron
900MHz
Samsung
900MHz
GPU
ROM_SI
H5TC4G63AFR-11C
0x3
256M x 16
PD 20K
MT41J256M16HA-093G:E
0x4
256M x 16
PD 24.9K
K4W4G1646D-BC1A
0x5
256M x 16
PD 30.1K
FB Memory (DDR3)
ROM_SO
ROM_SCLK
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
B
PD 4.99K
PD 4.99K
PU 49.9K
Un-stuff
Un-stuff
Un-stuff
STRAP3
STRAP2
STRAP1
STRAP0
STRAP4
ROM_SI
ROM_SO
PD 10K
PU 10K
PD 10K
PD 10K
Un-stuff
ROM_SCLK
VRAM
H5TC4G63AFR-11C
Hynix
900MHz
N15V-GM
Micron
900MHz
256M x 16
0x4
MT41J256M16HA-093G:E
256M x 16
Samsung
PU 10K
PU 10K
PD 10K
PU 10K
A
Micron
900MHz
128M x 16
PU 10K
PU 10K
PD 10K
PD 10K
0xC
MT41J128M16JT-093G
128M x 16
PD 10K
PD 10K
PD 10K
PU 10K
VRAM P/N
SA00005SH40
X7604012002
SA00005M120
X7604012001
SA00005VS00
0xD
H5TC2G63FFR-11C
Hynix
900MHz
X76
X7604112001
PD 10K
PD 10K
PD 10K
PD 10K
Micron
A
0x1
Hynix
K4W2G1646Q-BC1A
Samsung
900MHz
128M x 16
0xE
PU 10K
PU 10K
PU 10K
PD 10K
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
N15X_MISC
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
28
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
Blank
2013/08/05
Deciphered Date
2
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
29
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
5
4
3
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
30
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
5
4
3
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
31
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
5
4
3
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
32
of
59
5
4
3
2
1
LCD POWER CIRCUIT
CMOS Camera
+3VS
Need short
+3VS
W=60mils
J1
1
1
1
R1
130_0603_1%
1
2
R2
100K_0402_5%
3
S
G
2
C5
.1U_0402_10V6-K
@
4
1
1
S
1
2 0_0402_5%
D
2
1
G
S
1
2N7002KDWH_SOT363-6
2
1
2
1
{8}
1
2
@2
@
D
1
C3
.1U_0402_10V6-K
2
2
C4
10U_0603_6.3V6M
@
2
R5 1
@
100K_0402_5%
CMOS_ON#
1
C9
0.01U_0402_25V7K
@
2
1
W=40mils
2
R3 1
0_0603_5%
1
1
For EMI
Close to R5
2
2
C10
.1U_0402_10V6-K
@
@
2
R7
100K_0402_5%
1
33P_0402_50V8J
@
C43
R6
PCH_ENVDD
W=60mils
1
0_0805_5%
.1U_0402_10V6-K
C8
Q8A
{4}
L1
2
2
4.7U_0603_6.3V6K
C7
6
C2
.1U_0402_10V6-K
1
@
+LCDVDD_CON
+LCDVDD
G
2N7002KDWH_SOT363-6
Q7 3
LP2301ALT1G_SOT23-3
D
1
2
220K_0402_1%
G
+3VS_CMOS
LP2301ALT1G_SOT23-3
W=40 mils
.01U_0402_16V7-K
5
D
JUMP_43X39
C1
4.7U_0603_6.3V6K
@
D
Q8B
D
Q9
R4
2
2
S
3
2
2
+3VS_CMOS_R
@
1
C6
+5VALW
2
+LCDVDD
+3VS
1
2 0_0402_5%
ENBKL
2A 80 mil
2
R17 1
0_0805_5%
{44}
1
C
R16
100K_0402_5%
AO3401A_SOT23-3
2
D
S
3
Q33
1 @
2
2
@
R179 1
100K_0402_5%
Q34
1
PCH_ENVDD
2
R181 1
@
0_0402_5%
@
1
{4}
{4}
CPU_EDP_TX0+
CPU_EDP_TX0-
{4}
{4}
CPU_EDP_TX1+
CPU_EDP_TX1-
{4}
{4}
CPU_EDP_AUX
CPU_EDP_AUX#
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_TX0+
EDP_TX0-
CPU_EDP_TX1+
CPU_EDP_TX1-
C17
C18
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_TX1+
EDP_TX1-
CPU_EDP_AUX
CPU_EDP_AUX#
C20
C21
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_AUX
EDP_AUX#
+3VS
2
R21
C22
680P_0402_50V7K
@
{4}
1
2
@
0_0402_5%
W=60mils
CPU_EDP_HPD
+LCDVDD_CON
+3VS
{43} DMIC_DATA
{43} DMIC_CLK
2
{16}
{16}
B
R182 1
R183 1
+3VS_CMOS
HUB_USB20_P1
HUB_USB20_N1
R22
.1U_0402_10V6-K
2 TS@
C23 1
1 TS@
2
100K_0402_5%
+3VS_TS_R
C24
0.047U_0402_16V7K
@
LP2301ALT1G_SOT23-3
1
C25
.1U_0402_10V6-K
@
2 {16}
{16}
HUB_USB20_N4
HUB_USB20_P4
R28
2
R23
R24
1 TS@
1 TS@
1 10K_0402_5% TS_RS
2 0_0402_5%
2 0_0402_5%
USB20_N4_CONN
USB20_P4_CONN
USB20_P4_CONN
+3VS_TS
2 0_0402_5%
1
2
3
4
5
6
1
2
3
4
5
6
USB20_N4_CONN
+3VALW
GND1
GND2
2 0_0402_5%
For EMI
Touch Screen
HUB_USB20_N1 4
D2
For EMI
1
2
4
3
2
USB20_P4_CONN
3
USB20_N4_CONN
L12
@
1
2
4
3
2
HUSB20_P1_R
3
HUSB20_N1_R
CMM21T-900M-N_4P
D1
AZC199-02S.R7G_SOT23-3
@
2
1
@
2
HUB_USB20_P4
A
L13
1
@
1
@
1
1
C13
7
8
HUB_USB20_P1
R27
1
ACES_87213-00601-P01
ME@
3
@
@
2
2
1
B
ACES_50406-03071-001
ME@
W=40mils
EMI request
+3VS_TS
R26
31
32
33
34
35
JTS1
TS@
G
2 0_0402_5%
G1
G2
G3
G4
G5
1
+3VS_TS_R
1 TS@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D
S
3
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+3VS_TS
Q11
R25
2 0_0402_5% HUSB20_P1_R
2 0_0402_5% HUSB20_N1_R
2
Touch Screen
C12
C19
C16
INVT_PWM
S
2N7002KW_SOT323-3
1
EC_TS_ON#
CPU_EDP_TX0+
CPU_EDP_TX0-
DISPOFF#
@
2
@
JEDP1
G
C132
.1U_0402_10V6-K
@
1
C
+LEDVDD
D
Reserve for power consumption test
{44}
C11
1
@
@
2
2
R20
100K_0402_5%
R15
100K_0402_1%
2
EMI Request
1
INVT_PWM
1 2
2 0_0402_5%
3
1
R19
PCH_EDP_PWM
@
R13
100K_0402_1%
1
2
R180
100K_0402_5%
@
1
R18
1K_0402_5%
@
{4}
2
C15
1
INVT_PWM
LEDVDD_EN#
2
B+
C14
1
1
2
@
G
+3VS
EDP_AUX
EDP_AUX#
+LEDVDD
2A 80 mil
ENBKL
DISPOFF#
470P_0402_50V7K
R14
B+
@
DMIC_CLK
2
DISPOFF#
@
1
2 0_0402_5%
R9
100K_0402_1%
2
1
470P_0402_50V7K
PCH_ENBKL
R12
4.7U_0805_25V6-K
{4}
BKOFF#
1
{44}
R8
100K_0402_1%
100P_0402_50V8J
1
1
1
2
@
0_0402_5%
R11
EMI request
2
2
2
PCH_ENBKL
R10
4.7K_0402_5%
@
470P_0402_50V7K
For RF
+3VS
A
For EMI
CMM21T-900M-N_4P
1
AZ5215-01F_DFN1006P2E2
HUB_USB20_N4 4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
33
of
59
5
4
L2
1
HDMI_CLK-_C
3
2
1
@
1
2
2
1
HDMI_CLK-_CON
2
3.3P_0402_50V8-C
C26
@
4
3
3
1
HDMI_CLK+_CON
2
3.3P_0402_50V8-C
C27
HDMI2012F2SF-900T04_4P
D
1
2
1
HDMI_TX0-_CON
C28
D
2
3.3P_0402_50V8-C
3
3
1
HDMI_TX0+_CON
C29
2
3.3P_0402_50V8-C
3
4
4
2
3.3P_0402_50V8-C
2
1
4
+5VS_HDMI
@
2
@
HDMI_TX0+_C
+1.8VS
+1.8VS
L3
1
HDMI_TX0-_C
RP9
2.2K_0404_4P2R_5%
3
4
4
HDMI_CLK+_C
RP10
2.2K_0404_4P2R_5%
@
1
2
4
3
2
1
HDMI_TX1-_CON
C30
{4}
@
3
1
HDMI_TX1+_CON
DDPB_CLK
2
3.3P_0402_50V8-C
C31
L5
HDMI_TX2-_C
1
HDMI_TX2+_C
4
G1
HDMI2012F2SF-900T04_4P
@
1
2
2
1
HDMI_TX2-_CON
2
3.3P_0402_50V8-C
C32
{4}
1 S1
DDPB_DATA
D2 3
HDMICLK_R
Q3401B
PJT138K_SOT363-6
2
4
HDMI_TX1+_C
4 S2
2
1
L4
1
HDMI_TX1-_C
G2 5
HDMI2012F2SF-900T04_4P
D1 6
HDMI_DET
D3
1 1
10 9
HDMI_DET
HDMIDAT_R
2 2
9 8
HDMIDAT_R
HDMICLK_R
4 4
7 7
HDMICLK_R
+5VS_HDMI
5 5
6 6
+5VS_HDMI
3 3
HDMIDAT_R
8
@
3 HDMI_TX2+_CON
1
4
3
C33
HDMI2012F2SF-900T04_4P
2
3.3P_0402_50V8-C
Q3401A
PJT138K_SOT363-6
AZ1045-04F_DFN2510P10E-10-9
@
For EMC
For EMC
+1.8VS
C
C
R31 1
2 619_0402_1%
HDMI_TX0+_C
R32 1
2 619_0402_1%
HDMI_TX1-_C
R33 1
2 619_0402_1%
HDMI_TX1+_C
R34 1
2 619_0402_1%
HDMI_TX2-_C
R37 1
2 619_0402_1%
HDMI_TX2+_C
R38 1
2 619_0402_1%
+5VS
R3405
1K_0402_1%
D4
+5VS_HDMI_F
{4}
D5
F1
1
3
RB491D_SOT23-3
@
HDMI_HPD
D4
0.5A_8V_KMC3S050RY
LP2301ALT1G_SOT23-3
1
3
1
Q32
2
G
3
S
R41
100K_0402_5%
S
2
{46}
SUSP
JHDMI1
HDMI_DET
100K_0402_5%
HDMIDAT_R
HDMICLK_R
HDMI_CLK-
C35
2
1 .1U_0402_10V6-K
HDMI_CLK-_C
R43 2
@
1 0_0402_5%
HDMI_CLK-_CON
{4} HDMI_CLK+
{4} HDMI_TX0-
HDMI_CLK+
HDMI_TX0-
C36
C37
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_CLK+_C R44 2
HDMI_TX0-_C R45 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_CLK+_CON
HDMI_TX0-_CON
{4}
{4}
HDMI_TX0+
HDMI_TX1-
HDMI_TX0+
HDMI_TX1-
C38
C39
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_TX0+_C
HDMI_TX1-_C
R46 2
R47 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_TX0+_CON
HDMI_TX1-_CON
{4}
{4}
HDMI_TX1+
HDMI_TX2-
HDMI_TX1+
HDMI_TX2-
C40
C41
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_TX1+_C
HDMI_TX2-_C
R48 2
R49 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_TX1+_CON
HDMI_TX2-_CON
HDMI_TX2+
HDMI_TX2+
C42
2
1 .1U_0402_10V6-K
HDMI_TX2+_C
R50 2
@
1 0_0402_5%
HDMI_TX2+_CON
{4}
B
{4}
C34
.1U_0402_10V6-K
2
2
Q13
G
1
@
2
Q12
2N7002KW_SOT323-3
2N7002KW_SOT323-3
3
1
2
BAT54S-7-F_SOT23-3
1
1
D
G
R42
1
D
2
+3VS
+5VS_HDMI
@
2
S
HDMI_TX0-_C
+5VS
D
2 619_0402_1%
2
R30 1
3
HDMI_CLK+_C
R4602 change from 10K to 1K,
as Vienna
1
2 619_0402_1%
2
R29 1
1
HDMI_CLK-_C
HDMI_CLK-
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND1
CK_shield
GND2
CK+
D0GND3
D0_shield
GND4
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
B
22
23
FOX_QJ111A1-RC0AH1-8H
ME@
Close to JHDMI1
A
HDMI_CLK+_CON
D6
1 1
10 9
HDMI_CLK+_CON
HDMI_TX1-_CON
D7
1 1
10 9
HDMI_TX1-_CON
HDMI_CLK-_CON
2 2
9 8
HDMI_CLK-_CON
HDMI_TX1+_CON
2 2
9 8
HDMI_TX1+_CON
HDMI_TX0+_CON
4 4
7 7
HDMI_TX0+_CON
HDMI_TX2-_CON
4 4
7 7
HDMI_TX2-_CON
HDMI_TX0-_CON
5 5
6 6
HDMI_TX0-_CON
HDMI_TX2+_CON
5 5
6 6
HDMI_TX2+_CON
3 3
3 3
8
8
AZ1045-04F_DFN2510P10E-10-9
@
For EMC
AZ1045-04F_DFN2510P10E-10-9
@
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
34
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
DP to CRT Converter(PS8613)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
35
of
59
5
4
3
2
1
+3VS
CRT Connector
+CRT_VCC_CON
+5VS_HDMI
+5VS
RVG39
1
VGA_DDC_CLK
6
CRT_DDC_CLK
5
2
G
4
3
RB491D_SOT23-3
3
S
VGA_DDC_DAT
1
2 @
2
0_0603_5%
+CRT_VCC_CON
0.5A_8V_KMC3S050RY
W=40mils
CRT_DDC_DAT
1
D
CVG34
.1U_0402_10V6-K
@
2
D
VGA_DDC_DAT
@
FVG1
@
1
Q31A
2N7002KDWH_SOT363-6
D
2N7002KDWH_SOT363-6
Q31B
@
1
2
1
C50
@
100P_0402_50V8J
C485
@
68P_0402_50V8J
2
JCRT1
2
1
{4}
CRT_R
LVG6 1
2
BLM18BB470SN1D_2P~D
LVG11 1
2 0_0603_5%
CRT_DET#
CRT_R_CON
{4}
CRT_G
LVG7 1
2
BLM18BB470SN1D_2P~D
LVG12 1
2 0_0603_5%
CRT_DDC_DAT
CRT_G_CON
{4}
CRT_B
2
LVG8 1
BLM18BB470SN1D_2P~D
LVG13 1
2 0_0603_5%
HSYNC_CON
CRT_B_CON
1
1
2
1
2
1
2
2
2
1
1
2
1
2
TVG3
10P_0402_50V8J
CVG40
2
1
10P_0402_50V8J
CVG39
@
1
10P_0402_50V8J
CVG38
@
CVG53
22P_0402_50V8-J
2
CVG52
22P_0402_50V8-J
2
1
CVG51
22P_0402_50V8-J
2
1
10P_0402_50V8J
CVG37
1
RVG27
150_0402_1%
10P_0402_50V8J
CVG36
RVG26
150_0402_1%
10P_0402_50V8J
CVG35
2
@ PAD
RVG25
150_0402_1%
DVG2
AZ5425-01F_DFN1006P2E2
2
{4}
1
DVG1
D
VGA_DDC_CLK
S
{4}
2
1
+CRT_VCC
1
G
RPC10
2.2K_0404_4P2R_5%
1
2
3
4
+CRT_VCC_CON
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
VSYNC_CON
CRT_DDC_CLK
CVG41
100P_0402_50V8J
@
@
CLOSE TO CONN
1
For EMC
G
G
16
17
SUYIN_070546HR015M25KZR
ME@
2
C
C
RVG21
1
+3VS
2 0_0402_5%
1
+5VS
2
VGA_HS
VGA_HS
A
3
G
{4}
OE#
P
RVG40
1K_0402_1%
@
2
5
RVG37
1
2
@
1K_0402_5%
1
CVG49
1
2 @
.1U_0402_10V6-K
4
CRT_HSYNC
Y
UVG3
74AHCT1G125GW_SOT353-5
@
RVG32
1
2 15_0402_5%
CRT_HSYNC_R
1
LVG9
2 0_0402_5%
HSYNC_CON
1
LVG9/LVG10
SM01000LO00 Change to 0 ohm
@
RVG22
1
CVG42
150P_0402_50V8-J
2
+3VS
2 0_0402_5%
B
B
1
+5VS
2
RVG41
1K_0402_1%
@
2
5
P
VGA_VS
A
3
G
{4}
VGA_VS
OE#
.1U_0402_10V6-K
RVG38
1
2
@
1K_0402_5%
1
CVG50
1
2 @
4
CRT_VSYNC
Y
UVG4
74AHCT1G125GW_SOT353-5
@
RVG33
1
2 15_0402_5%
CRT_VSYNC_R
LVG10
1
2 0_0402_5%
VSYNC_CON
1
@
CRT_B_CON
DVG3
1 1
10 9
CRT_B_CON
VSYNC_CON
DVG4
1 1
10 9
VSYNC_CON
CRT_G_CON
2 2
9 8
CRT_G_CON
HSYNC_CON
2 2
9 8
HSYNC_CON
CRT_R_CON
4 4
7 7
CRT_R_CON
CRT_DDC_CLK
4 4
7 7
CRT_DDC_CLK
CRT_DET#
5 5
6 6
CRT_DET#
CRT_DDC_DAT
5 5
6 6
CRT_DDC_DAT
A
3 3
3 3
8
8
AZ1045-04F_DFN2510P10E-10-9
@
CVG45
150P_0402_50V8-J
2
A
AZ1045-04F_DFN2510P10E-10-9
@
For EMC
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
CRT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
36
of
59
5
4
3
2
1
+3VALW TO +3VALW_LAN
Need short
1
JL1
1
+3VALW_LAN
+LAN_VDDREG
width : 40 mils
2 @
2
+3VALW_LAN rising time (10%~90%):
0.5ms
spec
100ms
+3VALW_LAN
RL1
1
0_0603_5%
JUMP_43X79
2
@
2
@
@
2
CL5
@
Close to Pin11
1
2
Close to Pin32
CL6
1
2
1
CL7
2
Close to Pin11
.1U_0402_10V6-K
CL4
1
.1U_0402_10V6-K
1
CL9
.01U_0402_16V7-K
1 @
2
.1U_0402_10V6-K
1
2
CL8
G
1
2
@
47K_0402_5%
3
Q14
1
D
RL3
LAN_PWR_ON#
S
RL2
100K_0402_5%
@
{44}
1
LP2301ALT1G_SOT23-3
4.7U_0603_6.3V6K
+3VALW
4.7U_0603_6.3V6K
D
@
2
1
CL1
4.7U_0603_6.3V6K
2
D
CL2
.1U_0402_10V6-K
2
Close to Pin32
+3VALW_LAN
+3VS
2
2
+3VALW_LAN
QL1
1
UL1
G
2
RL4
10K_0402_5%
@
RL5
10K_0402_5%
@
1
1
D
LAN_CLKREQ#_R
{7,40,44}
{40,44}
RL7 1
RL6 1
PCIE_WAKE#
LAN_WAKE#
@
2 0_0402_5%
2 0_0402_5%
1
2
2.49K_0402_1%
+3VS
+3VALW_LAN
RSET
+LAN_VDD10
LAN_XTALO
LAN_XTALI
TL3 @ 1
1
LAN_PWR_ON#
2
RL121
@
0_0402_5%
LAN_DISABLE#
TL4 @ 1
2
RL9
1K_0402_1%
@
2
{7,19,40,44} PLT_RST#
{6} PCIE_PRX_DTX_N3
{6} PCIE_PRX_DTX_P3
LAN_PWR_ON#
{6}
CL10 1
CL11 1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
+LAN_REGOUT
+LAN_VDDREG
+LAN_VDD10
PCIE_WAKE#_R
ISOLATE#
PLT_RST#
PCIE_PRX_C_DTX_N3
PCIE_PRX_C_DTX_P3
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
AVDD33_2
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPIO
LED2
REGOUT
VDDREG
DVDD10
LANWAKEB
ISOLATEB
PERSTB
HSON
HSOP
REFCLK_N
REFCLK_P
HSIN
HSIP
CLKREQB
AVDD33_1
MDIN3
MDIP3
AVDD10_2
MDIN2
MDIP2
MDIN1
MDIP1
AVDD10_1
MDIN0
MDIP0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_CLKREQ#_R
+3VALW_LAN
LAN_MDI3LAN_MDI3+
+LAN_VDD10
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
+LAN_VDD10
LAN_MDI0LAN_MDI0+
CLK_PCIE_LAN#
{7}
{7}
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_MDI3LAN_MDI3+
{38}
{38}
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
{38}
{38}
{38}
{38}
LAN_MDI0LAN_MDI0+
{38}
{38}
2
0_0402_5%
1
RL18
C
{6}
{6}
CL10 close to Pin18
CL11 close to Pin17
0_0402_5%
1
LAN_CLKREQ#
PCIE_WAKE#_R
RL8
RL10 1
@
2N7002KW_SOT323-3
C
ISOLATE#
3
S
+3VALW
2
RL11
15K_0402_5%
@
RTL8111GUL-CG_QFN32_4X4
GIGA@
B
B
For RTL8111GUL/ RTL8106EUL (SWR mode)
LAN_XTALI
+LAN_VDD10
YL1
1
2
CL12
10P_0402_50V8J
LAN_XTALO
OSC1
GND2
GND1
OSC2
4
+LAN_REGOUT
3
1
25MHZ_10PF_7V25000014
2
1
2
LL1
2.2UH_NLC252018T-2R2J-N_5%
1
1
CL13
10P_0402_50V8J
CL15
4.7U_0603_6.3V6K
2
2
1
@
2
1
CL16
.1U_0402_10V6-K
2
1
CL17
.1U_0402_10V6-K
2
1
CL18
.1U_0402_10V6-K
2
1
CL19
.1U_0402_10V6-K
2
1
CL20
.1U_0402_10V6-K
Close to Pin3, 8, 22, 30
2
1
CL21
1U_0402_6.3V6K
@
2
CL22
.1U_0402_10V6-K
@
Close to Pin22(Reserved)
Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
＜＜
4
3
2
LAN_RTL8111GUL/RTL8106EUL
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
37
of
59
5
4
3
2
1
DL1/DL2
1'S PN:SC300003M00
6
7
LAN_MDI2-
NC2
VDD
GND
NC3
NC4
I/O3
I/O1
3
LAN_MDI3+
11
8
1
+3VALW_LAN
6
LAN_MDI1-
7
NC5
NC2
VDD
GND
NC3
NC4
I/O3
I/O1
3
LAN_MDI0+
10
11
8
1
1
CL24
4
5
{37}
LAN_MDI1-
{37}
LAN_MDI1+
{37}
LAN_MDI2+
{37}
LAN_MDI2-
LAN_MDI1-
20
LAN_MDI1+
19
LAN_MDI2+
17
LAN_MDI2-
16
15
68P_0402_50V8J
C
I/O2
22
18
DL2
I/O4
NC1
LAN_MDI0+
LAN_MDI3-
Place Close to TL1
9
2
LAN_MDI0+
21
AZ3033-04F_DFN2525P10E10
GIGA@
LAN_MDI1+
{37}
10
{37}
LAN_MDI3+
{37}
LAN_MDI3-
LAN_MDI3+
LAN_MDI3-
14
13
TD1+
MX1-
TD1-
MCT2
TCT2
MX2+
TD2+
MX2-
TD2-
MCT3
TCT3
MX3+
TD3+
MX3-
TD3-
MCT4
TCT4
MX4+
TD4+
MX4-
TD4-
1
MCT
2
LAN_MDO0-
3
LAN_MDO0+
4
MCT
5
LAN_MDO1-
6
LAN_MDO1+
7
MCT
8
LAN_MDO2+
9
LAN_MDO2-
10
MCT
11
LAN_MDO3+
D
12
RL17
20_0603_5%
1
I/O2
NC5
TCT1
MX1+
1
4
5
+3VALW_LAN
I/O4
NC1
23
DL3
BS4200N-C-LV_SMB-F2
2
9
2
LAN_MDI0-
2
LAN_MDI2+
LAN_MDI0-
1
DL1
{37}
GIGA@
MCT1
2
TL1
24
D
CL32
0.022U_0603_50V7K
LAN_MDO3-
1
1
2
2
CL25
1000P_1206_2KV7-K
@
C
BOTHHAND GST5009 LF LAN
2
LAN_MDI0CHASSIS1_GND
AZ3033-04F_DFN2525P10E10
Place Close to TL2
ME@
JRJ1
GND_4
GND_3
LAN_MDO0+
1
LAN_MDO0-
2
LAN_MDO1+
3
LAN_MDO2+
4
LAN_MDO2-
5
LAN_MDO1-
6
LAN_MDO3+
7
LAN_MDO3-
8
B
CL27 1
2 0_0603_5%
CL28 1
2 0_0603_5%
CL29 1
2 0_0603_5%
CHASSIS1_GND
Reserve for EMI go rural solution
GND_2
PR1+
GND_1
12
11
10
9
B
PR1PR2+
CHASSIS1_GND
PR3+
PR3PR2PR4+
PR4SANTA_130460-3
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
LAN_Transformer
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
38
of
59
5
4
3
2
1
D
D
SMSC thermal sensor
placed near DIMM
+3VS
2
REMOTE-_R
U3901
1
1
C47
.1U_0402_10V6-K
@
2
+3VS
R51
REMOTE+_R
2
REMOTE-_R
3
2
1
@
10K_0402_5%
4
SCL
D+
SDA
D-
ALERT#
T_CRIT#
GND
8
EC_SMB_CK2
7
EC_SMB_DA2
EC_SMB_CK2
{19,44}
EC_SMB_DA2
{19,44}
C
1
2 0_0402_5%
REMOTE+_R
REMOTE2- R177
1
2 0_0402_5%
REMOTE-_R
R178 1 @
1
Q15
MMBT3904W H_SOT323-3
@
5
Near CPU core
REMOTE2+
C46
100P_0402_50V8J
@
2
B
2
C
Q16
MMBT3904W H_SOT323-3
E
REMOTE2-
2 0_0402_5%
REMOTE2+ R176
REMOTE1-
E
6
Address 1001_100xb
R175 1 @
C
2
B
2
REMOTE1-
VDD
NCT7718W _MSOP8
REMOTE1+
1
1
C45
100P_0402_50V8J
@
3
C44
2200P_0402_50V7K
Near GPU&VRAM
REMOTE1+
1
REMOTE+_R
1
3
Close to U3901
Baytrail SOC use thermal sensor to read the thermal,
Baytrail don't has PECI signal
C
2 0_0402_5%
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
FAN Conn
B
B
+5VS
JFAN1
R52
1
C49
10U_0805_10V6K
@
2
1
2
0_0603_5%
C3901
.1U_0402_10V6-K
@
1
2
3
4
5
6
+5VS_FAN
1
{44}
{44}
EC_FAN_SPEED
EC_FAN_PW M
2
1
2
3
4
GND1
GND2
ACES_85205-04001
ME@
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2013/08/08
Deciphered Date
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Thermal sensor/FAN CONN
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
39
of
59
A
B
C
D
Mini-Express Card(WLAN/WiMAX)
Need short
+3VS
+3VS_WLAN
JWLAN1
@
J2
1
1
2
2
{16}
{16}
JUMP_43X79
+3VALW
D
C52
@
2
2
2
R54 1 AOAC@ 2
1
100K_0402_5%
2
1
.01U_0402_16V7-K
AOAC_ON#
1 AOAC@
1
G
{44}
3
S
Q17
C51
.1U_0402_10V6-K
@
1
3
5
7
HUB_USB20_P3
HUB_USB20_N3
LP2301ALT1G_SOT23-3
1
1
2
C53
.1U_0402_10V6-K
AOAC@
C54
.1U_0402_10V6-K
AOAC@
{6}
{6}
PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4
{6}
{6}
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
{7}
{7}
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
WLAN_CLKREQ_Q#
{7,37,44}
{37,44}
PCIE_WAKE#
R57
LAN_WAKE#
+3VS
2
2
+3VS_WLAN
1
1
2 0_0402_5%
PEG2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
1
@
T2
1
@
T3
1
EC_TX_RSVD
EC_RX_RSVD
R62
R63
1
1
@
@
2 0_0402_5%
2 0_0402_5%
Bay trail plaform susclk is 1.8V level, NGFF card need check whether OK
SUSCLK_R
PLT_RST#
BT_OFF#
WLAN_OFF#
SMB_DATA_S3_R
SMB_CLK_S3_R
1
@ T4
EC_TX_R
R55
1
2 0_0402_5%
R53
R56
R58
R59
1
1
1
1
2 1K_0402_1%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
@
@
1
SUSCLK {7}
PLT_RST# {7,19,37,44}
PCH_BT_OFF# {8}
{8}
PCH_WLAN_OFF#
SMB_DATA_S3 {8,14}
SMB_CLK_S3 {8,14}
+3VS_WLAN
77
EC_TX_R
R184
1
2 100_0402_1%
BT_OFF#
R185
1
2 100_0402_1%
EC_TX
{44}
EC_RX
{44}
R186
100K_0402_5%
WLAN_CLKREQ_Q#
2
2
2N7002KW_SOT323-3
R61
EC_TX_R
BT_OFF#
D
AOAC@ 3
WLAN_CLKREQ#
S
{6}
@
3.3VAUX1
3.3VAUX2
LED#1
NC
NC
NC
NC
LED#2
GND16
DP_AUXN
DP_AUXP
GND13
DP_ML1N
DP_ML1P
GND14
DP_ML0N
DP_ML0P
GND15
RESERVED1
RESERVED2
RESERVED3
COEX3
COEX2
COEX1
SUSCLK
PERST0#
RESERVED/W_DISABLE#2
W_DISABLE#1
I2C_DATA
I2C_CLK
I2C_ALERT#
RESERVED4
PERST1#
CLKREQ1#
PEWAKE1#
3.3VAUX4
3.3VAUX5
1
G
2
1
GND1
USB_D+
USB_DGND2
9
NC
11
NC
13
NC
15
NC
17
19 MLDIR_SENSE
21 DP_ML3N
23 DP_ML3P
GND3
25
27 DP_ML2N
29 DP_ML2P
31 GND4
33 DP_HPD
35 GND5
37 PETP0
39 PETN0
41 GND6
43 PERP0
45 PERN0
47 GND7
49 REFCLKP0
51 REFCLKN0
53 GND8
55 CLKREQ0#
57 PEWAKE0#
59 GND9
61 PETP1
63 PETN1
65 GND10
67 PERP1
69 PERN1
71 GND11
73 REFCLKP1
75 REFCLKN1
GND12
76
PEG1
JAE_SM3ZS067U410BAR1000
ME@
R60
10K_0402_5%
AOAC@
Q18
E
+3VS_WLAN
2 0_0402_5%
If support AOAC, NC R61;
if not support AOAC, stuff R61.
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
A
B
C
D
E
Sheet
40
of
59
A
B
C
D
E
U2
+5VALW
1
1
2
2.2U_0603_6.3V6K
2
C58 1
{44,45}
3
USB_ON#
USB_ON#
4
GND
VOUT3
VIN1
VOUT2
VIN2
VOUT1
EN/EN
FLAG
1
C55
+USB_VCCA
+
+USB_VCCA
LEFT SIDE USB3.0 PORT X2
C56
@
1
C57
@
1
2
220U_6.3V_M
2
1U_0603_25V6M
8
7
2
470P_0402_50V7K
1
6
ME@
JUSB1
5
USB_OC0#
AP2820CMMTR-G1_MSOP8
Low Active 2A
1
2
USB_OC0#
{8}
{8}
{8}
C61
1000P_0402_50V7K
@
USB20_N2
USB20_P2
USB20_N2
USB20_P2
R65
R64
1
1
@
@
2 0_0402_5%
2 0_0402_5%
1
2
3
4
USB20_N2_R
USB20_P2_R
VBUS
DD+
GND
GND1
GND2
GND3
GND4
5
6
7
8
C-K_20267-5K11-02
USB20_P2_R
+USB_VCCA
@
1
1
D11
2
2
@
2
AZ5425-01F_DFN1006P2E2
1
1
D10
2
2
@
AZ5425-01F_DFN1006P2E2
1
1
D9
2
2
2
AZ5425-01F_DFN1006P2E2
USB20_N2_R
USB20_P1_R
7
4
4 USB30_TX_R_N1
USB30_TX_R_P1 6
6
5
5 USB30_TX_R_P1
3
3
USB20_N2_R
CMM21T-900M-N_4P
8
AZ1045-04F_DFN2510P10E-10-9
3
L9
USB30_RX_N1
3
USB30_RX_P1
2
3
4
2
1
D13
@
1
USB30_TX_R_N1 7
USB20_N1_R
D14
1
2 USB30_RX_R_P1
2
2
2
9
1
3
USB30_RX_R_P1 8
AZ5425-01F_DFN1006P2E2
3
@
1 1USB30_RX_R_N1
1
4
2
D12
USB30_RX_R_N1 9 10
USB20_P2_R
2
4
1
2
2
USB20_N2
1
AZ5425-01F_DFN1006P2E2
L8
USB20_P2
@
3
For EMC
4 USB30_RX_R_N1
1 USB30_RX_R_P1
+USB_VCCA
DLW 21SN900HQ2L_4P
C62
@
1
2
1U_0603_25V6M
C63
@
1
2
470P_0402_50V7K
L10
USB30_TX_C_N1 3
USB30_TX_C_P1 2
3
4
2
1
4
USB30_TX_R_N1
1
USB30_TX_R_P1
{8}
L11
USB20_N1
1
USB20_P1
4
1
2
4
3
ME@
JUSB2
DLW 21SN900HQ2L_4P
2
USB20_N1_R
3
USB20_P1_R
{8}
USB30_TX_P1
USB30_TX_N1
{8} USB20_P1
{8} USB20_N1
{8} USB30_RX_P1
CMM21T-900M-N_4P
{8}
USB30_RX_N1
USB30_TX_P1 C64
1
2 .1U_0402_10V6-K USB30_TX_C_P1 R68
1
@
2 0_0402_5%
USB30_TX_R_P1
USB30_TX_N1 C65
USB20_P1
1
2 .1U_0402_10V6-K USB30_TX_C_N1 R69
R70
1
1
@
@
2 0_0402_5%
2 0_0402_5%
USB30_TX_R_N1
USB20_P1_R
USB20_N1
USB30_RX_P1
R71
R72
1
1
@
@
2 0_0402_5%
2 0_0402_5%
USB20_N1_R
USB30_RX_R_P1
USB30_RX_N1
R73
1
@
2 0_0402_5%
USB30_RX_R_N1
9
1
8
3
7
2
6
4
5
StdA_SSTX+
VBUS
StdA_SSTXD+
GND_DRAIN
DStdA_SSRX+
GND_5
StdA_SSRX-
GND_1
GND_2
GND_3
GND_4
10
11
12
13
SUYIN_020053GR009M2736L
4
4
For EMC
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
USB2.0/USB3.0 PORT (LEFT)
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
D
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
E
41
of
59
A
B
C
D
E
F
G
H
SATA HDD Conn.
{6}
{6}
1
{6}
{6}
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
C66
C67
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C68
C69
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+5VS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+5VS_HDD
Need short
@
J3
1
1
2
3
4
5
6
7
1
2
2
JUMP_43X79
+5VS_HDD
1
@
1
C74
1000P_0402_50V7K
2
1
C75
.1U_0402_10V6-K
2
@
2
1
C76
1U_0402_6.3V6K
1
C77
10U_0805_10V6K
2
2
FOR 14"
SATA ODD Conn.
ME@
JHDD1
GND_1
A+
AGND_2
BB+
GND_3
1
JODD1
{6}
{6}
V33_1
V33_2
V33_3
GND_4
GND_5
GND_6
V5_1
V5_2
V5_3
GND_7
DAS/DSS
GND_8
V12_1
V12_2
V12_3
{6}
{6}
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
14@ C70
14@ C71
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_P1_14
SATA_PTX_C_DRX_N1_14
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
14@ C72
14@ C73
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_N1_14
SATA_PRX_C_DTX_P1_14
ODD_DETECT#_R
+5V_ODD
ODD_DA#_R
1
2
3
4
5
6
7
GND_1
RX+
RXGND_2
TXTX+
GND_3
8
9
10
11
12
13
DP
+5V_1
+5V_2
MD
GND_4
GND_5
GND1
GND2
14
15
SUYIN_127382FB013S255ZL
ME@
SUYIN_127043HR022M32QZR
C78
10U_0805_10V6K
@
FOR 15"
2
SATA ODD FFC Conn
For EMC
2
JODD2
15@ C79
15@ C80
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_P1_15
SATA_PTX_C_DRX_N1_15
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
15@ C81
15@ C82
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_N1_15
SATA_PRX_C_DTX_P1_15
1
R74
ODD_DETECT#
2 0_0402_5%
ODD_DETECT#_R
2
{6}
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
Need Short
1
2
2
11
12
1
J4
1
+5V_ODD
ODD_DA#_R
R92
0_0402_5%
@
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GND_1
GND_2
ACES_51524-01001-003
ME@
JUMP_43X79
+5VALW
+5VS
+5V_ODD
LP2301ALT1G_SOT23-3
D
2
1
2
{6}
2
{44}
D
2
ODD_EN#
ODD_DA#
ODD_DA_EC#
R80
1
@
2 0_0402_5%
R86
1
@
2 0_0402_5%
ODD_DA#_R
Q21
PJA138K_SOT23-3
G
S
S
3
R81
100K_0402_5%
R77
10K_0402_5%
@
R79
470_0603_5%
@
2
@
C87
.01U_0402_16V7-K
1
Q20
PJA138K_SOT23-3
G
2
2
+3VS
1
2
C86
C84
C83
2
1
@
1
ODD_EN
@2
1
.1U_0402_10V6-K
1
2 R78
100K_0402_5%
@
1
10U_0805_10V6K
ODD_EN#
1
C85
2
@2
@
{8}
1
.1U_0402_10V6-K
1
1
2
R76
10K_0402_5%
1 Q19
G
R75
10K_0402_5%
@
3
D
S
3
.01U_0402_16V7-K
3
@
3
1
@
@
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
D
E
HDD/ODD CONN
2013/08/05
Deciphered Date
F
Size Document Number
Custom
G
Rev
0.2
ACLU9
Monday, December 23, 2013
Date:
Sheet
42
H
of
59
5
4
3
2
1
+1.5VS
+3VS
+3VS
RA8
2 0_0603_5%
1
2 0_0402_5%
+3VS
+3.3VD
RA11 1
2 0_0402_5%
DVDD_IO
@
+5VS
CA1
1
RA7
2 0_0603_5%
+5VA
D
RA10 1
2 0_0603_5%
RA3
1
@
2 0_0603_5%
RA5
1
@
2 0_0603_5%
RA43
1
RA1
1
2 0_0402_5%
RA4
1
2 0_0402_5%
RA6
1
@
2 0_0402_5%
RA9
1
@
2 0_0402_5%
RA12
1
@
2 0_0402_5%
RA13
1
@
2 0_0402_5%
+3VALW
+5VD
Same as Vienna
AVDD_HP
+3VL
.1U_0402_10V6-K
1
RA2
2
2 0_0603_5%
1
D
Close to Pin7
2
+3VS
RA14
10K_0402_5%
.1U_0402_10V6-K
1
2
CA13
100P_0402_50V8J
CA19
.1U_0402_10V6-K
CA18
.1U_0402_10V6-K
CA16
4.7U_0603_6.3V6K
CA15
4.7U_0603_6.3V6K
2
2
2
1
1
CA51
1
2
@
CA52
CA14 1
DMIC_CLK_R
CA17 1
19
20
2 1U_0402_6.3V6K
21
2 2.2U_0603_6.3V6K
1
41
PORTD_A_MIC
PORTD_B_MIC
LPWR_5.0
RPWR_5.0
HGNDA
HGNDB
FLY_P
FLY_N
AVDD_HP
AVEE
PORTA_R
PORTA_L
GND
2
30
31
PORTD_A_MIC
PORTD_B_MIC
25
26
RING2_CONN
RING3_CONN
24
AVDD_HP
23
22
HPOUT_R
HPOUT_L
B
Close to Pin11,13,16
1
1
2
2.2U_0603_6.3V6K
CA6
1U_0402_6.3V6K
CA10
CA5
.1U_0402_10V6-K
CA35
4.7U_0603_6.3V6K
2
C
+5VA
AVDD_HP
2
Close to Pin29
RA39
100_0402_1%
Reserve DA2 to prevent
cross-talk between
HPOUT_R/L, if stuff DA2,
RA37/RA38 need change to
3K.
CX20752-21Z_QFN40_5X5
@
LINE_B_R
LINE_B_L
RA38
3K_0402_1%
1
13
16
DMIC_DATA_R
CLASS-D_REF
MICBIASB
33
32
RA41
0_0402_5%
@
RA37
2
11
RA42
0_0402_5%
@
3K_0402_1%
+5VD
100P_0402_50V8J
+5VD
PORTB_R_LINE
PORTB_L_LINE
SPK_R+
SPK_R-
35
34
2
1
RA40
100_0402_1%
2
1
.1U_0402_10V6-K
CA12
DMIC_CLK_R
DMIC_DATA_R
MICBIASC
MICBIASB
17
15
DA2
BAT54AWT1G_SOT323-3
1
1
.1U_0402_10V6-K
CA11
2
2
MUSIC_REQ/GPIO0/PORTC_L_MIC
DMIC_CLK/MUSIC_REQ/GPIO0
DMIC_DAT/GPIO1
SPK_L+
SPK_L-
1LINE_B_L
33_0402_5% 1 RA18
0_0402_5% 1 RA19
RIGHT+
RIGHT-
12
14
1LINE_B_R
DMIC_CLK
DMIC_DATA
JSENSE
GPIO1/PORTC_R_MIC
LEFT+
LEFT-
2
2
{33}
{33}
36
40
1
CX20751-11Z
MICBIASB
2
38
37
PC_BEEP
SPKR_MUTE#
AVDD_3.3
VREF_1.65V
AVDD_5V
+3.3VD
1
JSENSE
SDATA_IN
SDATA_OUT
2
2
10
39
SYNC
AVDD_3.3
VREF_1.65V
+5VA
1
1
Close to Pin27
1
PC_BEEP
SPKR_MUTE#
1
2
20K_0402_1%
RA36
1
6
4
SDATA_IN
27
29
28
2
CD@
2
JSENSE
2
FILT_1.8V
DVDD_IO
3
{6}
{6} HDA_SDIN0
HDA_SDOUT_AUDIO
BIT_CLK
3
7
2
18
1
1
2
39.2K_0402_1%
RA17
PLUG_IN
HDA_SYNC_AUDIO
FILT_1.8V
VDD_IO
VDDO_3.3
DVDD_3.3
1
{45}
{6}
8
HDA_SYNC_AUDIO
RA16
1
33_0402_5%
HDA_SDOUT_AUDIO
RESET#
2
2
1
RA15
5.11K_0402_1%
5
HDA_BITCLK_AUDIO
HDA_BITCLK_AUDIO
2
{6}
C
9
HDA_RST_AUDIO#
HDA_RST_AUDIO#
1
CA16 close to Pin18
CA17 close to Pin2
2
+3.3VD
UA1
{6}
1
CA9
.1U_0402_10V6-K
3
0608
2
1U_0402_6.3V6K
CA8
QA1
MMBT3904WH_SOT323-3
E
CA7
.1U_0402_10V6-K
C
2
B
CA4
4.7U_0603_6.3V6K
2 RA289 1
4.7K_0402_5%
PCH_BEEP
1
{8}
CA2
2
PC_BEEP
.1U_0402_10V6-K
2
1
.1U_0402_10V6-K
CA3
2 RA288 1
10K_0402_5%
BEEP#
1
{44}
GNDA
GND
Close to Pin3
1
0606
1
1
2
2
Close to Pin28 Close to Pin24
CA36
4.7U_0603_6.3V6K
RA20 1
RA21 1
2 82.5_0402_1%
2 82.5_0402_1%
CA20 1
CA21 1
2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K
HP_OUTR
HP_OUTL
{45}
{45}
RA22
1
1
PORTD_A_MIC
PORTD_B_MIC
2 100_0402_1%
2 100_0402_1%
RING3_CONN
RING2_CONN
{45}
{45}
B
RA23
+3VS
2
2
For EMI
+1.5VS
HDA_RST_AUDIO#
HDA_SYNC_AUDIO
RA826
10K_0402_5%
HDA_SDOUT_AUDIO
@
1
JSPK1
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
HDA_BITCLK_AUDIO
HDA_SDIN0
1
1
1
1
@
@
@
@
2
2
2
2
RA25
RA29
RA32
RA33
SPK_R+
SPK_RSPK_L+
SPK_L-
RA26
RA31
RA30
RA34
1
1
1
1
2
2
2
2
BLM18PG221SN1D_2P
BLM18PG221SN1D_2P
BLM18PG221SN1D_2P
BLM18PG221SN1D_2P
1
2
3
4
SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN
1
2
3
4
A
@
@
@
2
CA34
1
1
2
1000P_0402_50V7K
2
CA33
1
1000P_0402_50V7K
2
CA32
CA31
1
1
1000P_0402_50V7K
1
2
1000P_0402_50V7K
1
2
220P_0402_50V7K
CA30
1
2
220P_0402_50V7K
CA29
2
2
220P_0402_50V7K
CA28
CA26
220P_0402_50V7K
CA27
@
2
1
@
CA25
1
33P_0402_50V8J
CA24
2
@
@
2
1
33P_0402_50V8J
CA23
1
22P_0402_50V8-J
2
@
+3.3VD
1
1
2
@
RA24 1
0_0402_5%
22P_0402_50V8-J
D
S
QA198
PJA138K_SOT23-3
@
0610
CA22
PCH_HDA_RST#_Q
22P_0402_50V8-J
3
@
HDA_RST_AUDIO#
2
RA27 1
@
27_0402_5%
1
G
1
2
RA825
10K_0402_5%
5
6
GND1
GND2
ACES_88231-04001
ME@
@
A
RA28
47K_0402_5%
EC_MUTE#
RB751V-40_SOD323-2
2 @
DA4 1
For EMI
2
PCH_HDA_RST#_Q
RB751V-40_SOD323-2
2 @
DA3 1
SPKR_MUTE#
{44}
EC_MUTE#
Issued Date
2013/08/08
2013/08/05
Deciphered Date
Codec_CX20751
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
2
RA35 1
0_0402_5%
5
Title
LC Future Center Secret Data
Security Classification
Rev
0.2
ACLU9
4
3
2
1
Sheet
43
of
59
5
4
For EMI
Close EC
+3VL
2
2 0_0402_5%
2 0_0402_5%
2
CE6
1
CE7
2
1
1
2 HCB1608KF-181T20_2P
+3VALW_R
CE8
2
1
CE9
2
1
CE10
2
1
1
CE11
LE2
2
2
2 HCB1608KF-181T20_2P
1
1
CE4
.1U_0402_10V6-K
CE5
1000P_0402_50V7K
EC_AGND 2
RE5
10K_0402_5%
@
EC_AGND
D
RB751V-40_SOD323-2
{8}
2 100K_0402_5%
1
CE12
1U_0402_6.3V6K
2
{7} EC_SMI#
{40} EC_RX
{40} EC_TX
{7,19,37,40} PLT_RST#
{6} EC_SCI#
@
IT1
1 PAD
KSO[0..17]
KSO[0..17]
+3VALW_R
RPE1
2
1
3
4
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA1
PAD
PAD
PAD
PAD
PAD
2.2K_0404_4P2R_5%
+3VS
KSI7
KSI6
WRST#
RPE2
3
4
PAD
PAD
PAD
@
IT2
@
IT3
@
IT4
@
IT5
@
IT6
1
1
1
@
IT7
@
IT8
@
IT9
EC_SMB_CK2
EC_SMB_DA2
For factory EC flash
2.2K_0404_4P2R_5%
to charge ,battery
to thermal sensor
+3VL
{52,53}
{52,53}
EC_SMB_CK1
EC_SMB_DA1
{37} LAN_PWR_ON#
{19,39} EC_SMB_CK2
{19,39} EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA2
RE27
Change RE24 to 0ohm jump
B
{59}
EC_VR_ON
{41,45}
USB_ON#
{7}
{7}
{7}
+3VL
2 10K_0402_5% ON/OFF
RE36 1
@
2 10K_0402_5% BKOFF#
2 0_0402_5%
112
125
33
35
93
USB_ON#
2
128
EC_LID_OUT#
AC_PRESENT
RE33 1
74
26
50
92
114
121
127
AVCC
11
VCC
EXTERNAL SERIAL FLASH
GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6
NC1
NC2
NC3
NC4
SPI Flash ROM
AC_IN#
LID_SW#
UART
EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3
Bus
GPIO
GPJ1
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
DTR1#/SBUSY/GPG1/ID7
CRX0/GPC0
CTX0/TMA0/GPB2
RI1#/GPD0
RI2#/GPD1
TACH2/GPJ0
TACH1A/TMA1/GPD7
TACH0A/GPD6
L80HLAT/BAO/GPE0
L80LLAT/GPE7
WAKE UP
GPIO
PWR_LED# {45}
BATT_CHG_LED# {45}
BATT_LOW_LED# {45}
BATT_LEN# {52}
SYS_PWROK {5,7}
EC_FAN_PWM {39}
BEEP# {43}
EC_FAN_PWM
ACLU9 NC
LAN_WAKE#
SUSP#
66
67
68
69
70
71
72
73
SUSWARN#
MAINPWON
ENBKL
VR_+1.0VALW_PWRGD
ACLU9 NC
ACIN#
LID_SW#
82
83
84
VGA_GATE#
{7}
{52}
{33}
1
2 0_0402_5%
PROCHOT#
LID_SW#
{45}
VGA_GATE# {8}
VDDQ_PGOOD {5,55}
{53}
ADAPTER_ID_ON#
EC_MUTE#
SYSON
BKOFF#
{43}
SUSP#
RE18 1
SUSP#
RE19 1
2 100K_0402_5%
SYSON
RE21 1
2 100K_0402_5%
EC_3VSPWREN
RE23 1
2 100K_0402_5%
SYS_PWROK
RE12 1
2 10K_0402_5%
1 0_0402_5%
RE24 2
1 0_0402_5%
EC_ADAPTER
PM_SLP_S3# {7}
2 0_0402_5%
RE29 1
PM_SLP_S4# {7}
NOVO# {45}
EC_TS_ON# {33}
{39}
EC_FAN_SPEED
2 0_0402_5%
VGA_AC_DET
RE30 1
SYSON
{12}
PCIE_WAKE#
EMC Request
{40}
{7,37,40}
RE34
VR_HOT#
1
2 0_0402_5%
QE1
2
H_PROCHOT#
D
2
1
G
VGA_AC_DET
{19}
ODD_DA_EC#
{42}
3
S
2
{6,51,52}
RE37 1
RE39 1
1 10K_0402_5%
C48
CE20
.1U_0402_10V6-K
1
@2
2
2
@ CE18
1
2 1U_0402_6.3V6K
{7,53}
1
2
Issued Date
1
2
ACIN#
ACIN#
D
QE2
2
G
Deciphered Date
EC ITE8586LQFP
2013/08/05
Date:
3
A
{53}
Title
LC Future Center Secret Data
2013/08/08
ACIN
2N7002KW_SOT323-3 S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
ACES_85205-04001
ME@
1
2 100P_0402_50V8J
1
2
3
4
GND1
GND2
2
2 100P_0402_50V8J
1
@ CE17
Security Classification
5
1
2
3
4
5
6
RE42
10K_0402_5%
1
1
ACIN#
ON/OFF
+3VL
1
BATT_TEMP @ CE16
J80P1
2 0_0402_5%
EC_TX
EC_RX
3
NOVO#
2 0_0402_5%
@
RE41
100K_0402_5%
CE19 .1U_0402_10V6-K
RE46 2
when mirror, GPG2 pull high
when no mirror, GPG2 pull low
B
CE13
.1U_0402_10V6-K
+5VS +3VS
CE14
47P_0402_50V8J
@
+3VL
CE21 .1U_0402_10V6-K
1 10K_0402_5%
1
@
{45}
NUM_LED#
H_PROCHOT#_EC
.01U_0402_16V7-K
1 10K_0402_5%
@
2 100K_0402_5%
{51}
PCH_ME_PROTECT
SYSON {55}
BKOFF# {33}
EC_FAN_SPEED
@
Change RE30 to 0ohm jump
+3VALW_R
@
2 100K_0402_5%
Need confirm later
RE26 2
AOAC_ON#
{59}
+3VL
RE44 2
RE15 1
USB_ON#
+3VS
GPG2
C
{52}
+3VALW_R
for EC version update to EX, manual modify PN to FX
RE43 2
3
4
{57}
EC_AGND
GPG2
RE51
0_0402_5%
+5VALW
RE14
2 10K_0402_5% BKOFF#
GPG2
+3VS
2.2K_0404_4P2R_5%
Change RE14 to 0ohm jump
2N7002KW_SOT323-3
A
2 100K_0402_5%
RPE3
CAPS_LED# {45}
PCH_PWR_EN {46,52,56,57}
ACOFF {53}
VR_+1.5VS_PWRGD
{46,56}
GPG2
2 0_0402_5%
@
2 10K_0402_5% LID_SW#
RE40 1
2 10K_0402_5%
@
2
1
TP_CLK
TP_DATA
Bay trail Platform SPI is 1.8V level, for mirror, need to check whether ok with ITE
108
109
77
100
106
104
107
119
123
18
21
76
48
47
19
20
1
TP_CLK {45}
TP_DATA {45}
VR_+1.5VS_PWRGD
101
102
103
105
1
RE9
+5VS
VGA_PWRGD {8,22}
PBTN_OUT# {7}
VR_+1.0VALW_PWRGD
TP_CLK
TP_DATA
96
97
98
99
RE7
ENBKL
10K_0402_5%
2 10K_0402_5%
{46,55,56,57}
SUSP#
H_PROCHOT#_EC
85
86
87
88
89
90
LPC_FRAME#
2
@
RE52
0_0402_5%
@
NTC_V {52}
TURBO_V {52}
BATT_TEMP {52,53}
VR_IMVP_IMON {59}
{59}
VR_CPU_PWROK
ADP_I {52,53}
ADAPTER_ID {51,53}
EC_3VSPWREN {46}
BATT_TEMP
78
79
80
81
RE11 1
Clock
IT8586E-AX_LQFP128_14X14
RE38 1
DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5
PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
GPF2
PS2
GPF3
PS2CLK2/GPF4
PS2DAT2/GPF5
GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0
CK32KE/GPJ7
CK32K/GPJ6
ADC
DAC
PWRSW#
SM
XLP_OUT
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/GPH2/SMDAT3/ID2
VSTBY0
GPE4
ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
IT8586E/AX
LQFP-128L
VSS1
@
1
EC_RSMRST#
VGA_AC_DET
RE35 1
110
111
115
116
117
118
94
95
ON/OFF
{45} ON/OFF
{54} EC_ON
EC_SMB_CK1
EC_SMB_DA1
KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
Int. K/B
KSO1/PD1
KSO2/PD2
Matrix
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5
LPC
24
25
28
29
30
31
32
34
120
124
RE10 1
EC_FAN_PWM
1
2
1
1
1
1
1
1
58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
PWM
AVSS
{45}
CLK_PCI
EC_RX
EC_TX
PLT_RST#
KSI[0..7]
KSI[0..7]
{45}
C
2 0_0402_5%
WRST#
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/GPC4
TMRI1/GPC6
75
1
KBRST#/GPB6
SERIRQ/GPM6
LFRAME#/GPM5
LAD3/GPM3
LAD2/GPM2
LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
PWUREQ#/BBO/SMCLK2ALT/GPC7
LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5
VSS2
VSS3
VSS4
VSS5
VSS6
RE8
4
5
6
7
8
9
10
13
14
15
16
17
22
23
126
LPC_FRAME#
EC_FAN_SPEED
2
@
{7} KBRST#
{8} SERIRQ
{8} LPC_FRAME#
{8} LPC_AD3
{8} LPC_AD2
{8} LPC_AD1
{8} LPC_AD0 1
RE53
CLK_PCI_EC
27
49
91
113
122
2
1
DE1
1
{37,40}
+3VS
1
+3VALW_R
LAN_WAKE#
minimum trace width 12 mil
1
WRST#
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
3
VBAT
{19}
VCORE
UE1
12
LAN_WAKE#
Change RE6 to 0ohm jump
2
@
1
1
LE1
1
RE4 1
RE6
All capacitors close to EC
+3VALW_R
+3VALW_EC
+3VS
VCCRTC
+3VALW_EC
+3VALW_R
VCOREVCC
.1U_0402_10V6-K
D
+3VALW
+3VALW_R
CE3
1
2
0_0603_5%
1
CE2
10P_0402_50V8J
@
2
2
CE1
220P_0402_50V7K
RE3 1
.1U_0402_10V6-K
1
2
1
2 10_0402_5%
@
.1U_0402_10V6-K
1
.1U_0402_10V6-K
RE2
2
.1U_0402_10V6-K
CLK_PCI
1
.1U_0402_10V6-K
PLT_RST#
2 0_0603_5%
@
.1U_0402_10V6-K
For ESD
3
1
RE1
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
44
of
49
5
4
3
2
1
ON/OFF switch
+3VL
K/B Connector
+3VALW
15"
14"
+3VS
KSO0_15
KSO[0..17]
{44}
D15
{44}
1
2 @
100P_0402_50V8J
PWR_NUM_LED
C134
1
2 @
100P_0402_50V8J
KSO16
C91
1
2 @
100P_0402_50V8J
JKB2
2
NOVO#
NOVO#
PWR_CAPS_LED C133
1
CAPS_LED# C117
1
R85
1
2 0_0402_5%
100P_0402_50V8J
{44}
NOVO_BTN#
@
ON/OFF
2 @
NUM_LED#
C118
1
2 @
100P_0402_50V8J
KSO17
C88
1
2 @
100P_0402_50V8J
KSO2
C89
1
2 @
100P_0402_50V8J
KSO1
C90
1
2 @
100P_0402_50V8J
KSO15
C92
1
2 @
100P_0402_50V8J
KSO7
C93
1
2 @
100P_0402_50V8J
KSO6
C94
1
2 @
100P_0402_50V8J
KSI2
C95
1
2 @
100P_0402_50V8J
KSO8
C96
1
2 @
100P_0402_50V8J
KSO5
C97
1
2 @
100P_0402_50V8J
KSO13
C98
1
2 @
100P_0402_50V8J
KSI3
C99
1
2 @
100P_0402_50V8J
KSO12
C100
1
2 @
100P_0402_50V8J
KSO14
C101
1
2 @
100P_0402_50V8J
CAPS_LED#
PWR_CAPS_LED
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
CAPS_LED#
3
D
BAT54CW_SOT323-3
2
+3VL
2
+3VALW
@
R119 1
ON/OFFBTN#
J5 1
R114
100K_0402_5%
1
1
R111
100K_0402_5%
@
2 0_0402_5%
ON/OFF
{44}
ON/OFF
KSO11
C102
1
2 @
100P_0402_50V8J
KSI7
C103
1
2 @
100P_0402_50V8J
KSO10
C104
1
2 @
100P_0402_50V8J
KSI6
C105
1
2 @
100P_0402_50V8J
KSO3
C106
1
2 @
100P_0402_50V8J
KSI5
C107
1
2 @
100P_0402_50V8J
KSO4
C108
1
2 @
100P_0402_50V8J
KSI4
C109
1
2 @
100P_0402_50V8J
KSI0
C110
1
2 @
100P_0402_50V8J
KSO9
C111
1
2 @
100P_0402_50V8J
2
SHORT PADS
J6 1
2
KSO0
1
C112
2 @
100P_0402_50V8J
KSI1
C113
1
2 @
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
100P_0402_50V8J
SHORT PADS
TP_PWR
3
@1
C116
2
100P_0402_50V8J
C115
2
100P_0402_50V8J
@1
2
1
2
3
4
5
6
GND1
GND2
+3VL
AZC199-02S.R7G_SOT23-3
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NUM_LED#
PWR_NUM_LED
CAPS_LED#
PWR_CAPS_LED
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
2.2U_0603_6.3V6K
2
C119 1
3
GND1
GND2
7
8
ACES_50503-0060N-001
ME@
{41,44}
USB_ON#
USB_ON#
4
GND
30 GND1
29 GND2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
KSO5_15
KB_5 KSI4_14
KSO1_15
KB_6 KSI5_14
KSI0_15
KB_7 KSO0_14
KSO2_15
KB_8 KSI2_14
KSO4_15
KB_9 KSI3_14
KSO7_15
KB_10 KSO5_14
KSO8_15
KB_11 KSO1_14
KSO6_15
KB_12 KSI0_14
KSO3_15
D
KB_13 KSO2_14
KSO12_15
KB_14 KSO4_14
KSO13_15
KB_15 KSO7_14
KSO14_15
KB_16 KSO8_14
KSO11_14
KB_17 KSO6_14
KSO10_15
KB_18 KSO3_14
KSO15_15
KB_19 KSO12_14
KSO16_15
KB_20 KSO13_14
KSO17_15
KB_21 KSO14_14
KB_LED_PWR_15
KB_22 KSO11_14
CAPS_LED#_15
KB_23 KSO10_14
VDD_15
KB_24 KSO15_14
NUM_LED#_15
C
VIN1
VOUT2
VIN2
VOUT1
EN/EN
+USB_VCCB
7
6
5
FLAG
{8}
{8}
USB_OC1#
1
AP2820CMMTR-G1_MSOP8
2
USB_OC1#
R67
R66
USB20_P0
USB20_N0
1
1
2 0_0402_5% USB20_P0_CONN
2 0_0402_5% USB20_N0_CONN
{8}
{16}
{16}
C120
1000P_0402_50V7K
@
HUB_USB20_P2
HUB_USB20_N2
{43}
{43}
@
HP_OUTR
HP_OUTL
{44}
LID_SW#
JUSB3
+3VS
8
VOUT3
Low Active 2A
2
2
2
@
For EMC
{43}
RING2_CONN
{43}
RING3_CONN
{43} PLUG_IN
HP_OUTR
HP_OUTL
RING2_CONN
RING3_CONN
PLUG_IN
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18 G2
17 G1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
19
ACES_50505-0184N-P01
ME@
TP_P6
1
B
1
L14
USB20_P0
1
USB20_N0
4
2
D19
2
2
2
1
1
ON/OFFBTN#
AZ5215-01F_DFN1006P2E2
@
AZ5215-01F_DFN1006P2E2
1
1
D18
DT5
2
2
2
5
EVQPLHA15_4P
A
GND1
A1
B1
B
GND2
1
For 14"
1
2
3
4
5
6
1
1
AZ5215-01F_DFN1006P2E2
1
1
EVQPLHA15_4P
2
2
2
5
1
A
GND1
A1
B1
B
3
4
6
GND2
1
1
2
2
5
A1
GND1
GND2
B1
EVQPLHA15_4P
6
Change to same as ACLUA
15@
@
6
A
B
3
14@
4
TP-R
3
6
1
TP-R
SW4
DT4
1
6
SW3
2
TP-L
D17
DT3
TP_RIGHT Button
TP_P6
2
GND
5
5
4
TP-L
A1
GND
5
@
TP_P5
NOVO_BTN#
GND1
4
15@
TP_RIGHT Button
GND2
DAT
B1
3
EVQPLHA15_4P
DAT
6
3
2
CLK
1
2
4
CLK
SW2
DT2
1
2
3
4
5
6
NOVO_BTN#
ON/OFFBTN#
LID_SW#
TP_LEFT Button
TP_P5
AZ5215-01F_DFN1006P2E2
2
AZ5215-01F_DFN1006P2E2
B
2
1
A
3
14@
4
VDD
B
For 15"
1
NUM_LED#
+USB_VCCB
U3
1
JPWRB1
AZ5215-01F_DFN1006P2E2
VDD
1
+5VALW
For EMC
AZ5215-01F_DFN1006P2E2
For 14"
{44}
Right Side USB2.0 Port X 1 (USB/B)
@
TP_P4
SW1
KSI3_15
USB I/O Connector
7
8
ACES_50503-0060N-001
ME@
TP_LEFT Button
KSI2_15
KB_3 KSI6_14
KB_4 KSO9_14
DT1
1
TP_CLK
TP_DATA
TP_P4
TP_P5
TP_P6
TP_CLK
TP_DATA
C114
.1U_0402_10V6-K
1
1
2
3
4
5
6
KB_2 KSI7_14
JKB1
PWR/B Connector
JTP1
{44}
{44}
R90
300_0402_5%
15@
ACES_50504-3041-001
ME@
TP_CLK
TP_DATA
2
@
R160 1
0_0402_5%
2
R141 1
0_0402_5%
R84
300_0402_5%
27
28
For EMC
2
+5VS
+3VS
GND1
GND2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15"
ACES_88514-02601-071
ME@
TP/B Connector
C
1
KSO[0..17]
14"
{44}
2
KSI[0..7]
1
1
@
R83
100K_0402_5%
2
2
2
KB_1 KSI1_14
KSI[0..7]
R82
100K_0402_5%
@
@
1
2
4
3
2
USB20_P0_CONN
3
USB20_N0_CONN
CMM21T-900M-N_4P
For 15"
LED
{44}
PWR_LED#
PWR_LED#
LED1
1
2 14@
R142 1
2 1.5K_0402_5%
+5VALW
R143 1
2 470_0402_5%
+3VALW
LTW-C193TS5
LED4
1
2 15@
LTW-C193TS5
{44}
BATT_LOW_LED#
BATT_LOW_LED#
LED2
1
2 14@
LTST-C193KFKT-LC
A
A
LED5
1
2 15@
LTST-C193KFKT-LC
{44}
BATT_CHG_LED#
BATT_CHG_LED#
LED3
1
2 14@
R144 1
2 1.5K_0402_5%
+5VALW
LTW-C193TS5
1
Issued Date
2 15@
Title
LC Future Center Secret Data
Security Classification
LED6
2013/08/08
Deciphered Date
2013/08/05
KBD/PWR/IO/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
LTW-C193TS5
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
45
of
59
A
B
C
+3VALW to +3VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
D
E
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+3VALW
+5VALW
+3VALW
+5VS
+1.35VS_SOC_VGA
Q4607
+3VS
Q4602
3
2
3VS_GATE
C4605
0.01U_0402_25V7K
S 2N7002KW_SOT323-3
1
1
D
Q25
2N7002KDWH_SOT363-6
@
S 2N7002KW_SOT323-3
+5VLP
2
AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max
1
{44,55,56,57}
SUSP#
3
6
Q10A
C4602
0.01U_0402_25V7K
@
D
D
Q10B
5
G
2
5VS_GATE
2
SUSP
R269
1
C4603
.1U_0402_10V6-K
@
+1.8VALW
1
2
1
0601 ADD
Q170B
2N7002KDWH_SOT363-6
D
5
G
D
4
2
Q170A
R899
330K_0402_5%
2N7002KDWH_SOT363-6
G
S
2
1
2
C4608
1
2
C216
.1U_0402_10V6-K
1
0_0402_5%
1
{44,56}
+1.8VS_PWREN#
S
2
+1.8VS_PWREN
R266
VR_+1.5VS_PWRGD
6
{56}
1
1
VR_+1.05VS_PWRGD
4
2
6
G
S
@
2
1000P_0402_50V7K
C444
Q163B
2N7002KDWH_SOT363-6
3
5
2
1
1
2
3
5
R898
100K_0402_5%
4
2
D
0_0402_5%
1000P_0402_50V7K
C484
Q163A
2N7002KDWH_SOT363-6
0601 ADD
2
@
R895
100K_0402_5%
R894
100K_0402_5%
3
1
1
R897
330K_0402_5%
Q30
AON6414AL_DFN8-5
1
1
0601 ADD
2
@
R893
100K_0402_5%
R892
100K_0402_5%
4
R289
1
C214
.1U_0402_10V6-K
2
2
2
+1.35VS_PWREN
S
2
+1.8VS_PWREN#
D
2
G
@
+5VLP
+20VSB
+1.35VS_PWREN#
1
0601 ADD
+1.35VS_PWREN#
1
1
2
3
5
R896
100K_0402_5%
2
1
+5VALW
Q28
AON6414AL_DFN8-5
+1.8VS
+5VLP
1
+5VALW
+20VSB
AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max
+1.35VS
2
AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max
1
0_0402_5%
S 2N7002KDWH_SOT363-6
S
2
+1.35V
2
1
G
2N7002KDWH_SOT363-6
2
2
for 8s reset SOC off power
C219
.1U_0402_10V6-K
@
4
2
2
1
1
2
PCH_PWR_EN#_R
1
1
1
2
3
5
1000P_0402_50V7K
C446
1
1
C4601
.1U_0402_10V6-K
@
S 2N7002KW_SOT323-3
G
3
G
R159
47_0603_5%
@
SUSP
SUSP
2
R166
100K_0402_5%
+1.0VS
Q4606
AON6414AL_DFN8-5
2
3
2
2
2
Q26
D
{34}
Id=3.2A
+0.675VS
D
1
R163
100K_0402_5%
@
JUMP_43X79
S
Q27
.1U_0402_10V6-K
C4607
@
1
R162
100K_0402_5%
2 100K_0402_5% PCH_PWR_EN#
PCH_PWR_EN
CC117
2
1
1
1
2
LP2301ALT1G_SOT23-3
PCH_PWR_EN
1
@
2N7002KDWH_SOT363-6
4
R161
100K_0402_5%
{44,52,56,57}
16.5K_0402_1%
R4607
24K_0402_1%
{44}
EC_3VSPWREN
+5VALW
1
@
J7
1
R164 1
5
+3VALW_SOC
1
+3VALW
FB
2
0_0402_5%
5
G
G
S
S
1
Q24B
D
D
2
+1.0VALW
+5VALW
PCH_PWR_EN#_R
2
+20VSB
+3VS_PWREN#
G
2
2
1
Q24A
2
R4601
820K_0402_5%
@
EN
R4606
.1U_0402_10V6-K
VR_+1.05VS_PWRGD
2
470K_0402_5%
1
@
GND
SY8089AAAC_SOT23-5
2
1 R156
0_0402_5%
G
4
R4608
R158
3VS_GATE_R
D
2
SUSP
2N7002KW_SOT323-3
3
1
+20VSB
Q23
2
G
1
IN
Vout=0.8(1+R4606/R4607)
+3VS_PWREN#
4
1
2
150K_0402_5%
S
@
R4604
100K_0402_5%
R4605
100K_0402_5%
LX
1
R152 @
470_0603_5%
1
2
1
@
2
2
C130
1U_0603_25V6M
2
2
@
6
1
D Q22
R165
820K_0402_5%
@
2
AP4800BGM-HF_SO-8
1
2 R155
5VS_GATE
1
2
3
1
82K_0402_1%
1
C131
0.01U_0402_25V7K
C127
10U_0603_6.3V6M
2
2
R154
5VS_GATE_R
1
1
C129
10U_0805_25V6K
@
R151
470_0603_5%
@
+5VLP
2
C126
1U_0603_25V6M
1
2
+5VALW
1
1
@
1
3
2
@
1
AP4800BGM-HF_SO-8
1
2
3
4
2
8
7
6
5
1
C125
10U_0805_25V6K
4
1
C128
10U_0805_25V6K
@
1
C4606
4.7U_0603_6.3V6K
3
1
2
3
2
Q4601
8
7
6
5
4.7U_0603_6.3V6K
+5VALW to +5VS
2
3
3
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
DC V TO VS INTERFACE
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
46
59
of
4
4
A
B
C
D
E
4
3
V
B+
BATT
B5
D
Q26,+3VALW_SOC
3
VR_+1.0VALW_PWRGD
2
+3VALW
+3VALW_SOC
V
V V V
BATT
MODE
A4
PU401
V
PU301
A2
1
PCH_PWR_EN#
V
V V
VIN
B1
4
PCH_RSMRST#
EC
5
PBTN_OUT#
SOC
EC_ON
other Device
B4
V
PM_SLP_S3#
PM_SLP_S4#
14
6
PLTRST#
DDR_CORE_PWROK
C
13
SYS_PWROK
V
B3
ON/OFF
15
V V
A3
1
V
A1
V
AC
MODE
A2
+3VLP
2
V
B2
D
V
5
C
V
NOVO
SYSON
7
V
VR_REDY
(DIS)
V
Vb
11
+1.35V
PU501
+VGA_CORE
PU909
V
PXS_PWREN
DGPU_PWROK
V
V
+1.05VGS
PU702
V
+3VG_AON
QV11
V
VR_+1.05VS_PWRGD
PU501
+0.675V
V
B
VGA
VR_+1.5VS_PWRGD
V
12
V
EC_3VSPWREN
PU602
+1.5VS
V
PU603
+1.05VS
Q28
+1.35VS
+1.35VGS
QV14
V
9
V
Q4606
+1.0VS
Va (DIS)
V
SUSP#
Q4601
+5VS
V
B
V
V
VR_ON
V
10
PU901
+CPU_CORE
V
PXS_PWREN
Q4602
+3VS
Q30
+1.8VS
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
47
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
Virtual symbol
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
48
of
59
5
4
1
H6
HOLEA
H7
HOLEA
H8
HOLEA
PAD_SHAPET5P0X6P0B7P0D2P3
pad_SHT7P0X7P05BR10P65X10P3D2P8
Pad_ct8p0b9p0d2p8
H9
HOLEA
H11
HOLEA
H10
HOLEA
Pad_ct8p0b9p0d2p8 pad_shapet8p8x8p0cb9p0d2p8
H12
HOLEA
1
1
1
1
H5
HOLEA
1
H4
HOLEA
1
1
D
1
H3
HOLEA
1
pad_c2p3d2p3n
1
H2
HOLEA
pad_o2p3x2p8d2p3x2p8n
1
H1
HOLEA
1
pad_o2p3x2p8d2p3x2p8n
1
pad_c2p3d2p3n
2
NH5
HOLEA
1
D
NH4
HOLEA
1
NH3
HOLEA
1
NH1
HOLEA
3
pad_shapet8p8x8p0cb9p0d2p8
pad_ct6p0d4p3
PAD_CT6P5B5P0D4P0
PAD_CT6P5B5P0D4P0
PAD_CT6P5B5P0D4P0
Pad_ct6p0b8p0d4p6
PAD_CT6P5B5P0D4P0
H22
HOLEA
H23
HOLEA
H21
HOLEA
1
H20
HOLEA
1
H19
HOLEA
1
H18
HOLEA
1
H17
HOLEA
1
H16
HOLEA
1
1
H15
HOLEA
1
H14
HOLEA
1
H13
HOLEA
1
C
1
C
CHASSIS1_GND
pad_cb8p0d7p0
pad_ct6p0shapeb8p0x6p75d2p3
PAD_CT6P0shapeb10p04x10p0d2p8
pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5
PAD_ShapeT5P0X6P0-D PAD_shapeT5P0X6P0-U
pad_ct5p5b6p0d3p3 pad_ct3p8b6p0d3p3
pad_ct5p5b6p0d3p3
pad_ct5p5b8p0d2p5
B+
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GP8
PAD_RT2P65X2P2
@
@
1
2
@
1
2
@
@
1
2
1
2
@
1
B
+3VS
+3VALW
+5VALW
+3VALW
C137
1
FFC CONN GROUND PAD
1
1
1
GP12
PAD_RT2P45X2P5
@
1
GP11
PAD_RT2P45X2P5
@
1
1
1
GP10
PAD_RT2P21X2P99
@
2
@
+VGA_CORE
GP9
PAD_RT2P21X2P99
@
1
0.1U_0402_25V6
GP7
PAD_RT2P65X2P2
@
C4906
0.1U_0402_25V6
GP6
PAD_RT2P65X2P2
@
C4905
0.1U_0402_25V6
GP5
PAD_RT2P65X2P2
@
C4904
0.1U_0402_25V6
GP4
PAD_RT2P65X2P2
@
C4903
0.1U_0402_25V6
GP3
PAD_RT2P65X2P2
@
C4902
0.1U_0402_25V6
B
GP2
PAD_RT2P65X2P2
@
C4901
GP1
PAD_RT2P65X2P2
@
2
C135
.1U_0402_10V6-K
@
1
C136
1
+3VS
1
@
2 .1U_0402_10V6-K
+GFX_CORE
C138
.1U_0402_10V6-K
@
2
2
.1U_0402_10V6-K
C251
1
@
2 .1U_0402_10V6-K
+3VS
C252
PCB Fedical Mark PAD
FD1
FD2
FD3
FD4
For EMC
FD5
1
1
1
1
1
Issued Date
2 .1U_0402_10V6-K
A
Title
LC Future Center Secret Data
2013/08/08
Deciphered Date
Hole
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
1
@
FD6
Security Classification
1
A
+1.35V
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
Sheet
1
49
of
59
5
4
B+
Silergy
SY8208CQNC
Converter
FOR SYSTEM
D
Adaptor
EC_ON
3
EN
Silergy
SY8032LDBC
DFN10_3X3
Switch Mode
+5VALW/6A
PGOOD
ALW_PWRGD
+3VLP/ 100mA
ANPEC
APL5930AQBI-TRG
TDFN10_3X3
Switch Mode
+3VALW/ 5A
PGOOD
ALW_PWRGD
SYSON
S5
SUSP#
S3
TI
TPS51716RUKR
WQFN20_3X3
Switch Mode
FOR DDR
PGOOD
EN
+1.35V/10A
Silergy
SY8032ABC
SOT23-6
Switch Mode
+0.675VS/2A
PGOOD
C
+1.05VSP_VGA/2A
FOR VDDR
PGOOD
EN
PAGE 46
VR_ON
SMBus
+1.5VSP/1A
FOR VDDR
SUSP#
TI
BQ24737RGRR
Battery Charger
Switch Mode
+1.0VALW/2.5A
PGOOD
EN
PAGE 39
C
D
FOR VDDR
SUSP#
Silergy
SY8206BQNC
Converter
FOR SYSTEM
EN
1
+5VLP/ 100mA
PAGE 39
EC_ON
2
EN
Onsemi
NCP6132AMNR2G
QFN60_7X7
Switch Mode
FOR CPU Core PGOOD
PGOOD_NB
CPU Core/12A
Silergy
SY8089AAC
SOT23-5
Switch Mode
GFX Core/14A
VGATE
+1.8VALW/1A
FOR VDDR
PGOOD
EN
B
Battery
Li-ion
4S1P/41WH
VIDs
NVDD_PWR_EN
EN
Onsemi
NCP81172MNTWG
QFN24_4X4
Switch Mode
FOR GPU VDDC
PGOOD
Silergy
SY8032ABC
SOT23-6
Switch Mode
+VGA_CORE/31A
B
+1.05VS/2A
FOR VDDR
EN
VGA_PWRGD
PGOOD
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
50
of
59
5
4
3
2
1
+3VL
VCCRTC
2
VIN
RTC_VCC
PD101
RB751V-40_SOD323-2
PJ101
ACES_50299-00501-003
ME@
@
1
@
1
1
JUMP_43X118
1
1
{44,53}
PC102
2
1
7A_24VDC_429007.WRML
ADAPTER_ID
2
2
2
APDIN1
PC104
1000P_0402_50V7K
2
PC103
2
1
1
470P_0402_50V7K
APDIN
2
D
PF101
1
2
3
4
5
PC101
1000P_0402_50V7K
1
2
3
4
5
470P_0402_50V7K
JDCIN1
JRTC1
PR101
2
1
1
PD102
2
BAT_D
2
1K_0603_5%
@
change to 1K
FDK_ML1220-TT28
D
1
RB751V-40_SOD323-2
SD01310018J
@
RTC_VCC 20MIL
+3VALW 20MIL
VCCRTC 20MIL
BAT_D 20MIL
{53}
737_ACP
737_ACN
{53}
@
PC105
2
1
+1.05VS
+1.05VS
PC109 @
2
1
EN
TMER
1
2
1
2
2
1
PR108
6
1
5
1
375K for
124K for
15uS
5uS
@
PR106
7
@
RT9553AGQW_WDFN10_3X3
PR114
124K_0402_1%
@
+3VALW
H_PROCHOT#
@
8
2
1
1
2
1
PQ101
4
PR113
10K_0402_5%
@
PR112
10K_0402_1%
@
0.1U_0402_25V6
UVSET
1
0_0402_5%
+3VALW
2
24K_0402_1% @
PR110
10K_0402_1%
@
2
+3VALW
2.94K_0402_1%
PR109
10K_0402_1%
@
set OVP
UVP 9V
2
35.7K_0402_1%
ILIM
PR104
2
@
1
3
2
OVSET
11
1
RESET
VCC
H_PROCHOT#
2
2
+3VALW
CSP
9
PR103
10K_0402_5%
2
2
PR102
10K_0402_5%
@{6,44,52}
CSN PROCHOT#
GND
@
@
PR111
30K_0402_1%
D
2
G
2N7002KW_SOT323-3
B
3
EC_ADAPTER
1
PR107
@
{44}
1
PU101
1
@
PC108
0.1U_0402_25V6
PC106
0.1U_0402_25V6
@
10
0.1U_0402_25V6
@
PR105
0_0402_5%
1
2
PC107
2
1
1
0.1U_0402_25V6
+5VALW
1
C
2
C
S
45W current limit 2.8A
65W current limit 3.6A
B
@
New solution need verify in SDV
This solution will reverse in next phase
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
2013/08/05
Deciphered Date
DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
5
4
3
2
1
Sheet
51
of
59
5
4
3
2
VMB2
VMB
JBATT1
PL201
C8BBPH403025-1TAPING_2P
1
2
BATT+
1
PC201
1000P_0402_50V7K
PC202
0.01U_0402_25V7K
2
2
For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212
PH201 under CPU botten side :
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
+5VLP
+3VL
@
4
{44,53}
A/D
G
S
@ PR214
1
1
1
5
ADP_OCP_2 1
MAINPWON
2
PR207
10K_0402_1%
2
PH201
@
PR209
57.6K_0402_1%
@
2
1
1
Turbo_V_1
1
BATT_TEMP
OTP_N_003
2ADP_OCP_1
PQ201
2N7002KW_SOT323-3
PR213
2
10K_0402_5%
6
G718TM1U_SOT23-8
3
1
BATT_TEMP_IN
OT2 RHYST2
2
OTP_N_002
@
100K_0402_1%_NCP15WF104F03RC
2
@
D
NTC_V_1
7
2
PR212
0_0402_5%
+3VALW
OT1 TMSNS2
8
1
2
100K_0402_1%
1
1
3
PR206
100K_0402_1%
@
H_PROCHOT#
1
{6,44,51}
GND RHYST1
2
{44,53}
PR208
VCC TMSNS1
1
2
EC_SMB_DA1
2
PR211
10K_0402_1%
1
PR205
21.5K_0402_1%
@
2
PU201
{44,53}
PR204
13.7K_0402_1%
1
1
PR203
4.42K_0402_1%
@
+3VS
EC_SMB_CK1
D
ADP_I
2
2
{44,53}
PC203
0.1U_0402_25V6
@
2
PR210
0_0402_5%
SUYIN_200082GR007G232ZR
PR202
100_0402_1%
1
1
EC_SMCA
EC_SMDA
2
D
PF201
8A_24V_F1206HI8000V024T
1
2
1
2
3
4
5
6
7
8
9
PR201
100_0402_1%
2
1
1
2
3
4
5
6
7
GND1
GND2
1
@
{44}
{44}
2
3
0_0402_5% @
C
NTC_V
2
PROCHOT#
{44}
Turbo_V
0_0402_5%
PR215
1
{44}
C
+3VALW
VMB2
+5VALW
+3VALW
1
UVP_1
2
3
1
1
4
1
3
1
PR352
1M_0402_5%
P
8
2N7002KDWH_SOT363-6
2
PR232
1
VSBP_2
2
@
PJ201
JUMP_43X39
2
1
2
+20VSB
1
PC208
0.1U_0402_25V6
2
PC207
2
1
0.22U_0603_25V7K
{53}
1
1
2
3
VSBP_3
22K_0402_1%
@
ALW_PWRGD
{44,46,56,57}
PCH_PWR_EN
6
1
2N7002KDWH_SOT363-6
S
4
1
PR234
0_0402_5%
2
PQ204
D
2
VSBP_1
G
1
{54}
1
4
PR236
100K_0402_1%
1
2
2
BATT_LEN#
S
B
PQ203B
2N7002KDWH_SOT363-6
PR238
PQ203A
10K_0402_1%
D
1
2 2
G
1
{44}
PQ205
2N7002KW_SOT323-3
G
S
AS393MTR-G1_SO8
100K_0402_1%
PR235
1
+3VL
2
@
@
G
-_1
4
D
BATT_OUT
Use BATT_TEMP to implement BATT_OUT function,
New solution need verify in SDV,maybe can reverse in next phase
5
S
AS393MTR-G1_SO8
2
PR353
1M_0402_5%
B+
2
PR239
100K_0402_1%
-_2
1
VIN
PR228
100K_0402_1%
2
1
2
5
2
2
G
D
@
+3VALW
A
7
PR237
1
2
1K_0402_1%
S 2N7002KW_SOT323-3
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
PC210
1U_0402_6.3V6K
@
3
O1
D
2
O2
2
+_1
PR224
430K_0402_1%
2
1
@
PC205
220P_0402_50V7K
2
1
1
PR223
180K_0402_1%
2
1
2
@
PU202B
+_2
@
PR225
1
2
0_0603_5%
+VSBP
@
PQ210
TP0610K-T1-E3_SOT23-3
100K_0402_1%
PR227
1
3
8
1
1
PR233
49.9K_0402_1%
PU202A
P
3
2
G
2
PR231
10K_0402_1%
1
2
6
@
PQ202A
+3VALW
PR226
100K_0402_1%
1
2
1
2
1
@
PR230
10M_0402_5%
1
2
PR229
280K_0402_1%
@
PC209
0.1U_0402_25V6
+3VALW
5
2
20K_0402_1%
B
+5VALW
G
S
1 PR222
@
PQ202B
2N7002KDWH_SOT363-6
@
D
5
1.78M_0402_1%
12.5V
@
PC204
0.1U_0402_25V6
H_PROCHOT#
2
G
2
2
@
PR221
1
6
@
AZ5215-01F_DFN1006P2E2
PC206
0.01U_0402_25V7K
@
PR219
430K_0402_1%
1
PD202
SUYIN_200082GR007G232ZR
VMB2
@
PR217
221K_0402_1%
1
1
Reverse PD305 For EMI request
PR220
499K_0402_1%
2
1
1
VMB2
2
EC_SMCA
EC_SMDA
BATT_TEMP_IN
+5VALW
@
PR216
10K_0402_1%
PD201
AZC199-02S.R7G_SOT23-3
4
1
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
GND1
GND2
2
JBATT2
@
PR218
0_0402_5%
2
1
2013/08/08
2013/08/05
Deciphered Date
BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 23, 2013
Date:
Rev
0.2
ACLU9
3
2
1
Sheet
52
of
59
5
4
3
B+
2
PC311
1
3
PC310
2
1
P2
2
2
1SS355_SOD323-2
PD302
2
PACIN_P
1
2
59K_0402_1%
PC317
1
2
737_ACDET
6
6
D
2
PACIN
G
S
PQ307A
2N7002KDWH_SOT363-6
5
6
7
8
AO4466L_SO8
14
3
PQ311
GND
1
ACN
ACDET
CMPOUT
PR313
4
ACP
1
S
2
20
PR312
390K_0402_1%
VCC
PQ306B
2N7002KDWH_SOT363-6
2
PD303
RB751V-40_SOD323-2
2
1
PC315
0.1U_0402_25V6
1
PC314
1U_0603_25V6M
2
1
1
1
0.1U_0402_25V6
737_VCC
2
D
G
PACIN_G
47K_0402_1%
PR314
BTST
17
BST_CHG 1
2
2.2_0603_5%
PC316
2
1
C
4
0.047U_0603_16V7K
5
ACPRN
ACOK
REGN
16
ACOFF
D
0_0402_5%
PR315
2
737_SCL
0_0402_5%
PR317
1
2
737_SDA
{44,52}
EC_SMB_DA1
PU301
9
SCL
HIDRV
18
DH_CHG
PR318
0.01_1206_1%
BQ24737RGRR_VQFN20_3P5X3P5
8
SDA
1
PR326
316K_0402_1%
2
1
1
@
2
4
DL_CHG
3
2
1
SRP_1 13
PC321
680P_0402_50V7K
@
2
1
4
PR320
4.7_1206_5%
AO4466L_SO8
1
4
737_ILIM
2
1
100K_0402_1%
3
PQ312
21
2 CHG
1
5
6
7
8
15
2
2
2N7002KDWH_SOT363-6 S
PR325
0_0402_5%
@
4
4.7UH_PCMB063T-4R7MS_5.5A_20% 2
1 6251_SN
SRP
SRN
PAD
PR324
10_0603_5%
PR322
2
10K_0402_5%
1
2
PR323
6.8_0603_5%
1
+3VS
LODRV
SRN_1 12
10
11
PQ308B D
5
G
BM#
2
3
PR321 @
BATT_OUT
ILIM
BM#
2
IOUT
CMPIN
7
ADP_I
PC318
100P_0402_50V8J
1
LX_CHG
1
1
{44,52}
2N7002KDWH_SOT363-6
PR319
1M_0402_5%
2
0_0402_5%
ADP_I
PC323
1
2
PC322
0.1U_0402_25V6
@
737_SRP
0.1U_0402_25V6
+3VALW
2
B
BATT_TEMP
B
737_SRN
PC324
0.1U_0402_25V6
1
{44,52}
BATT+
PL301
PHASE
19
1
S
0.1U_0402_25V6
1
EC_SMB_CK1
{44,52}
PC320
10U_0805_25V6K
2
1
{44}
PQ309A
2
G
2 ACOFF-1
PC319
10U_0805_25V6K
2
1
PR316
1
6
3
2
1
C
5
1
1SS355_SOD323-2
S
2
1
2
BQ24737_VDD
VIN
P2-2
PR311
1
PC312
2
1
PR310
1M_0402_5%
BATT_OUT
PR309
2
1
10_1206_5%
{52}
PC313
1U_0603_25V6M
2
1
4
6
1
PQ308A
2
G
2
D
S 2N7002KDWH_SOT363-6
PACIN
5 PACIN_N
0.1U_0402_25V6
G
PR308
68K_0402_1%
3
6
1
S
PR306
200K_0402_1%
PQ307B
2N7002KDWH_SOT363-6
D
0.1U_0402_25V6
2N7002KDWH_SOT363-6
PQ306A D
2
G
PD301
1
PR307
20K_0402_1%
3
P2_G1
PQ305
LTC015EUBFS8TL_UMT3F-3
PR305
10K_0402_1%
1
1
2
VIN
2
47K_0402_1%
1
DISCHG_G-1
1
P2-1
D
4
PR304
1
@
737_ACN
2ACOFF-1
{51}
737_ACP
BATT+
8
7
6
5
DISCHG_G
2
{51}
PC309
2200P_0402_50V7K
@
PC308
4.7U_0805_25V6-K
1
2
PC304
10U_0805_25V6K
@
2
PC303
10U_0805_25V6K
@
1
PR303
200K_0402_1%
PQ303
AO4407AL_SO8
1
2
3
PC306
4.7U_0805_25V6-K
1
2
100P_0402_50V8J
2
3
PC305
4.7U_0805_25V6-K
1
2
2
1
3
1 P2_G2
2
PC307
0.1U_0402_25V6
2
1
1
2
2
PC301
1
2
PQ304
LTA044EUBFS8TL_UMT3F-3
PR302
200K_0402_5%
4
1
D
@
PJ301
JUMP_43X118
1
2
1
2
PR301
0.01_1206_1%
1
PC302
0.1U_0402_25V6
1
2
4
1
2
3
2
PQ302
SI4483ADY-T1-GE3_SO8
1
8
2
7
3
6
5
4
8
7
6
5
VIN
1
P3
PQ301
AO4407AL_SO8
1
P2
2
Charge Option() bit[8]=1
+3VALW
VIN
1
PR328
1M_0402_5%
1
1
1
BQ24737_VDD
1
2
2
2
PR329
47K_0402_1%
PR330
10K_0402_1%
PR331
2
ACIN
{44}
10K_0402_1%
2
PR327
750_0603_1%
D PQ310A
G
2N7002KDWH_SOT363-6 S
3
{44,51}
1
4
S 2N7002KDWH_SOT363-6
1
D
1
5
G
S
ADAPTER_ID_ON#
{44}
PQ310B
2N7002KDWH_SOT363-6
A
2
2
2
1
PR334
1M_0402_5%
PD304
AZ5425-01F_DFN1006P2E2
4
1
D
5
ACPRN
G
ADAPTER_ID
PC326
0.1U_0402_25V6
2
1
PC325
680P_0402_50V7K
2
1
@
ADAPTER_ID_ON#_G
PR332
12K_0402_1%
2
2
PR333
0_0402_5%
@
A
3
6
2
1
PACIN
PQ309B
ACPRN
PR335
0_0402_5%
1
2
@
ACIN#
{7,44}
Title
LC Future Center Secret Data
Security Classification
Issued Date
ACIN#
2013/08/08
Deciphered Date
2013/08/05
CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
53
of
59
5
4
3
2
1
D
D
PU401
5
PTP401
PAD
2
+3VALW_P
PR403
4.7_1206_5%
@
100mA +3VLP
2
@
PJ402
PL401
1
2
2.2UH_PCMB063T-2R2MS_8A_20%
1
+3VALW_P
@
2
+3VALW
PC403
2
PC407
22U_0805_6.3V6M
LDO
4
1
FB
+3VLX
PR404
1M_0402_5%
2
@ PC408
0.1U_0402_25V6
3
LX
OUT
10
1
1
+3VALW_FB
1
0.1U_0603_25V7-M
PC406
22U_0805_6.3V6M
2
1
0_0402_5%
+3VBS
PC405
22U_0805_6.3V6M
2
1
EN1
+3V_PWRGD
2
1
2
6
PC404
22U_0805_6.3V6M
2
1
+3VALW_EN
BS
1
GND
3V_GND
2
EC_ON
PG
1 2
IN
2
9
EN2
1
8
PC409
4.7U_0603_6.3V6K
2
7
+3V_VIN
PR401
1M_0402_5%
1
2
1
2
PR402
1
{44}
1
1.5A
1
1
PC401
0.1U_0402_25V6
2
JUMP_43X79
SY8206BQNC_QFN10_3X3
@
PJ401
2
PC402
10U_0805_25V6K
B+
2
4A
1
1
JUMP_43X79
PC410
1000P_0402_50V9-J
@
3V_GND
3V_GND
3V_GND
PC411
1
1
PR405
2
1K_0402_1%
+3VL
+3VLP
JUMPER
@
C
2
0.01U_0402_25V7K
PJ403
1
2
change 470P to 10nf for soft start time 2ms
@
PJ404
2
3V_GND
2
1
C
1
JUMP_43X39
2
+3VALW
PR406
100K_0402_5%
{52}
LX
OUT
4
PR413
2 +5VALW_P
+5VALW_OUT1
0_0402_5%
LDO
7
PR410
4.7_1206_5%
@
100mA
+5VLP
2
+5VALW
@
3.3UH_PCMB063T-3R3MS_6.5A_20%
PL402
1
2
0.1U_0603_25V7-M
5A
PJ406
2
+5VALW_P
PC420
22U_0805_6.3V6M
FB
+5VLX
2
0_0402_5%
PC415
1
2
PC419
22U_0805_6.3V6M
2
1
3
10
1
PR411
1M_0402_5%
2
1
2
1
+5VFB
+5VBS
PC418
22U_0805_6.3V6M
2
1
0_0402_5%
@ PC421
0.1U_0402_25V6
ALW_PWRGD
PC417
22U_0805_6.3V6M
2
1
EN
+5V_PWRGD
1
VCC
1
2
6
2
1
BS
1
1U_0603_25V6M
+5VALW_EN
5V_GND
PG
2
5
GND
1
PC416
1
2 +5VVCC
IN
2
9
PC422
4.7U_0603_6.3V6K
PC414
10U_0805_25V6K
1
2
8
SY8208CQNC_QFN10_3X3
B
1
+5V_VIN
2
2
PR409
EC_ON
1
1
2
1
1
2
JUMP_43X79
@
PR408
2.5A
PC412
0.1U_0402_25V6
2
2
0_0402_5% @
PU402
@
PJ405
PC413
10U_0805_25V6K
B+
1
1
PR407
+3V_PWRGD
2
1
1
JUMP_43X79
B
@
PC423
1000P_0402_50V9-J
@
5V_GND
5V_GND
5V_GND
PC424
1
2
6800P_0402_25V7-K
1
PR412
2
1K_0402_1%
PJ407
1
2
JUMPER
@
6800pf soft start 2ms
47nf soft start 7ms
5V_GND
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
PWR_3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
54
of
59
A
B
C
D
1k for 500K
12k for 670K
1
@
PC501
0.1U_0402_10V7K
2
1
1
1.35V_GND
SUSP# {44,46,56,57}
0.1U_0402_10V7K
@
S5
5
16
17
TRIP
S3
18
19
20
VTTSNS
VBST
15
PR507
PC506
0_0603_5% 0.1U_0603_25V7-M
1
2 2
1
BST_1.35V
V5IN
2
1
0_0402_5%
13
PL501
1
LX_1.35V
12
2
11
+5VALW
PQ502
4
1
JUMP_43X79
1
PR509
4.7_1206_5%
@
2
1.35V_L
2
1
+
2
1
1
DIS ------10A
UMA-----6A
+1.35V
JUMP_43X118
@
PC509
330U_2.5V_M
2
1
10
9
6
7
2
PR510
10K_0402_1%
3
2
1
2
REFIN
2
PC513
0.1U_0402_25V6
1
PJ503
2
0.68UH_PCMC063T-R68MN_15.5A_20%
AON7506_DFN
PC510
1U_0603_25V6M
LG_1.35V
2
JUMP_43X118
UG_1.35V
3
2
1
14
2
GND
VREF
DRVL
PGND
VDDQSNS
VTTREF
1
1
2
1.35V_SN
2
+0.675VS
@
PJ502
1
SW
TPS51716RUKR_WQFN20_3X3
VTTGND
REFIN
5
1.35V_GND
1
B+
JUMP_43X79
PQ501
2
VTT
DRVH
DDR_VREF
@
PJ504
2
1
AON7408L_DFN8-5
1
4
VLDOIN
+VTT_REFP
+0.675VSP
1
4
5
2
3
PC511
1U_0402_6.3V6K
2
PR508
1
@
PAD
8
PC507
22U_0805_6.3V6M
2
1
2A
+0.675VSP
2A
+1.35V
PC508
22U_0805_6.3V6M
2
1
2
MODE
1
PGOOD
21
PC505
10U_0805_25V6K
1
PC502
10U_0805_25V6K
2
1
PC503
2
1
SYSON {44}
0.1U_0402_25V6
PC504
2
1
S3_1.35V
2
2
1.35V_B+
@
PU501
@
PJ501
2A
PR504 0_0402_5%
2
1
S5_1.35V
1
VDDQ_PGOOD
2
{5,44}
PR505
1K_0402_1%
0_0402_5%
2
PR501
1
1.35V_GND
PR506
2
1
133K_0402_1%
PR503
2
1
100K_0402_1%
+3VALW
PC512
1000P_0402_50V9-J
@
1.35V_GND
1
1
1.35V_GND
2
2
0.01U_0402_25V7K
3
+1.35VP
Vout=1.367V
Iocp min=23A
PR511
30.9K_0402_1%
PC514
1.35V_GND
3
1.35V_GND
PJ4
1
2
JUMPER
@
1.35V_GND
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
1.35VS/+0.675VS
Size
Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
D
Sheet
55
of
59
A
B
C
D
+1.8VALW _L
2A
PU601
1
2
2
PC605
22U_0805_6.3V6M
1
PC604
22U_0805_6.3V6M
1
2
1
1
1
PR604
1M_0402_5%
PR605
10K_0402_1%
PC607
.1U_0402_10V6-K
2
2
PR606
2
1
0_0402_5%
PCH_PW R_EN
1
+1.8VALW _FB
EN_+1.8VALW
2
{44,46,52,57}
@
PR603
2
1
47K_0402_5%
SUSP#
SUSP#
@
PC606
680P_0402_50V7K
@
1
{44,46,55,57}
PR602
19.6K_0402_1%
2
JUMP_43X79
@
PC603
68P_0402_50V8J
1
SY8089AAAC_SOT23-5
FB=0.6Volt
1
1
EN
PJ602
2
2
FB
1
2
GND
5
+1.8VALW
1UH_PH041H-1R0MS_3.8A_20%
PL601
1
2
+1.8VALW _LX
PR601
4.7_1206_5%
3
LX
2
2
IN
2
1
JUMP_43X79
@
1
PC602
22U_0805_6.3V6M
1
4
+1.8VALW _VIN
PC601
22U_0805_6.3V6M
2
1
2
1A
1
1
PJ601
2
+3VALW
+5VALW
1
+1.5VSP
500mA
1
PC610
220P_0402_50V7K
1
@
PC611
10U_0603_6.3V6M
@
PR609
24K_0402_1%
2
2
2
APL5930KAI-TRG_SO8
1
PR608
21.5K_0402_1%
VR_+1.5VS_PW RGD
{44,46}
+3VS
2
+3VALW
1
1
2
1
1
FB
PR610
100K_0402_5%
@
PR617
100K_0402_5%
2
JUMP_43X39
EN
POK
1
.1U_0402_10V6-K
PC612
@
2
2
8
7
3
4
2
2EN_1_5VSP
0_0402_5%
VOUT1
VOUT2
1
1
VR_+1.05VS_PW RGD 1
1
@
2
JUMP_43X39
PR607
PJ604
VCNTL
VIN1
VIN2
GND
6
5
9
1
2
1
PC609
4.7U_0603_6.3V6K
2
2
PU602
PJ603
2
+3VALW
+1.5VS
500mA
2
PC608
1U_0603_25V6M
2
+3VALW
1
VFB=0.8V
PR616
100K_0402_5%
+1.05VS_L
3
3
2
2A
PU603
EN_1.05VMP
1
2
1
1.05VMP_FB
4
2
@
2
1
PR615
100K_0402_1%
PC619
.1U_0402_10V6-K
2
PR614
1M_0402_5%
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
+1.05VS
1
PR613
2
1
47K_0402_5%
@
PC618
680P_0402_50V7K
@
1
SUSP#
1
PC617
22U_0805_6.3V6M
1
FB=0.6Volt
1
@
PR612
75K_0402_1%
2
1
PC616
22U_0805_6.3V6M
EN
2
JUMP_43X79
PC615
68P_0402_50V8J
FB
SY8032ABC_SOT23-6
PJ606
2
1
GND
PL602
1
2
1UH_PH041H-1R0MS_3.8A_20%
1.05VMP_LX
2
2
PG
3
1
LX
2
6
IN
2
2
@
5
1
4
1.05VMP_VIN
PR611
4.7_1206_5%
1A
PC614
22U_0805_6.3V6M
1
2
1
JUMP_43X79
1
2
PC613
22U_0805_6.3V6M
2
1
PJ605
+3VALW
VR_+1.05VS_PW RGD
2
{46}
B
C
+1.05VS/+1.5VS
Document Number
Size
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
D
Sheet
56
of
59
5
4
3
2
1
2
+3VALW
1
PR701
100K_0402_5%
{44}
VR_+1.0VALW_PWRGD
2
1
1
D
@
1
2
PC706
22U_0805_6.3V6M
1SNB_+1.0VALW
2
1
PC709
.1U_0402_10V6-K
1
PR702
4.7_1206_5%
@
2
1
JUMP_43X79
2
1
1
@
2
+1.0VALW_L
PC705
22U_0805_6.3V6M
EN
+1.0VALW_LX
2
1
FB
3
+1.0VALW
@
PJ702
1
GND
2
2
0_0402_5%
PR705
1
PCH_PWR_EN
6
LX
PG
SY8032ABC_SOT23-6
PR704
{44,46,52,56}
IN
5
1UH_PH041H-1R0MS_3.8A_20%
PL701
1
2
+1.0VALW_EN
2
@ PR703
1
2
0_0402_5%
{44,46,55,56} SUSP#
4
+1.0VALW_PVIN
2
@
2
1
1
47K_0402_5%
2
JUMP_43X79
PC702
2
1
2
0.1U_0402_25V6
+5VALW
D
PU701
PC704
22U_0805_6.3V6M
PC701
22U_0805_6.3V6M
2.5A
@
PJ701
@
PC711
680P_0402_50V7K
@
VFB=0.6V
68.1K_0402_1%
PR706
1
2
1
+1.0VALW_FB
PR707
100K_0402_1%
2
2
1 PC712
220P_0402_50V7K
C
C
2
+3VS
PR708
10K_0402_5%
OPT@
1
+1.05VSP_VGA
2
1.05VGS_EN
1
1
+1.05VGS
1
2
PC717
22U_0805_6.3V6M
PC716
22U_0805_6.3V6M
1
2
PC715
68P_0402_50V8J
1
2
2
PC718
680P_0402_50V7K
@
2
JUMP_43X79
B
1.05VGS_FB
OPT@
1
1
PR713
1M_0402_5%
OPT@
OPT@
PR714
100K_0402_1%
OPT@
PC719
.1U_0402_10V6-K
@
2
1
0_0402_5%
N15SGT@
@
2
OPT@
1
1
PR710
4.7_1206_5%
EN
SY8032ABC_SOT23-6
FB=0.6Volt
OPT@
2
PR715
1.05VGS_EN
FB
2
1.05VGS_EN
4.7K_0402_5%
N15VGM@
2
{22,58} EN_VGA
GND
@
PJ709
PL702
1
2
1UH_PH041H-1R0MS_3.8A_20%
OPT@
1.05VGS_LX
OPT@
1
PR172
PG
3
PD701
2 N15VGM@
1
B
6
LX
OPT@
PR711
75K_0402_1%
2
1
OPT@
5
IN
1
2
1
JUMP_43X79
{23,58} DGPU_PWROK
PU702
4
1.05VGS_VIN
2
+1.05VGS_PWRGD
1
1
1
PC714
22U_0805_6.3V6M
2
PC713
22U_0805_6.3V6M
2
1
2
2
{22}
@
PJ703
+3VALW
2.5A
{21}
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2013/08/08
Deciphered Date
2013/08/05
+1.05VS/+1.05VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
57
of
59
5
4
3
2
1
2
+3VGS
1
PD705
RB751V-40_SOD323-2
OPT@
2
EN_VGA
1
1
PR9443
PR9444
1
2
100K_0402_5%
@
OPT@
10K_0402_1%
EN_VGA
{22,57}
D
PC1303
.1U_0402_10V6-K
OPT@
2
2
1
N15SGT@
PR9445
0_0402_5%
3VGS_PWR_EN
2
D
{19,21}
PR9442
10K_0402_5%
@
N15VGM@
2
1
PR9446
0_0402_5%
PXS_PWREN
1
{8,21}
+VGA_B+
NVVDD PWM_VID
20
2
1
PC1298
10U_0805_25V6K
2
1
PC1295
10U_0805_25V6K
2
1
PC1255
0.1U_0402_25V6
3
2
1
OPT@ PC1297
330U_D2_2V_Y
OPT@ PC1293
330U_D2_2V_Y
1
1SNUB1_VGA 2
PC1296
680P_0402_50V7K
@
+VGA_B+
4
1
2
1
1
OPT@
B
OPT@
OPT@
PL706
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2
OPT@
PHASE2_VGA
Deciphered Date
2
PC1292
22U_0805_6.3V6M
OPT@
A
OPT@
Title
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
OPT@
PC1291
22U_0805_6.3V6M
2
1
1
1
2
1
2
2
OPT@
PC1290
22U_0805_6.3V6M
2
1
@
LC Future Center Secret Data
2013/08/08
+
2
PC1282
680P_0402_50V7K
@
@
Security Classification
1
PC1281
330U_D2_2V_Y
OPT@
+
2
2
OPT@
+3VS
Issued Date
1
PC1280
330U_D2_2V_Y
@
1
PR9428
4.7_1206_5%
@
PC1288
22U_0805_6.3V6M
4
PR9432
0_0402_5% @
2
1
1SNUB2_VGA 2
LGATE2_VGA
AON6554_DFN
PC1279
1U_0402_6.3V6K
OPT@
+VGA_CORE
PQ994
PC1287
22U_0805_6.3V6M
PR9424
PC1278
0_0603_5%
0.22U_0603_16V7K
2
1OPT@ BOOT2_2_VGA 1
2
OPT@
PC1276
10U_0805_25V6K
UGATE2_2_VGA
OPT@
2
PR9423
0_0402_5%
2
1
PC1275
10U_0805_25V6K
OPT@
A
4
C
2 0_0402_5%
+5VS
@
PR9433 OPT@
10K_0402_5%
5
+
2
2OPT@
1
PR9418
NCP81172MNTWG_QFN24_4X4
+5VS
2
1
OPT@
PR9427
2.2_0402_5%
1
1
19
@
2
2
2
1
PVCC_VGA
BOOT2_VGA
VCC_VGA
3
2
1
1
21
3
2
1
1
PC1299
.1U_0402_10V6-K
OPT@
+
PC1301
4.7U_0603_6.3V6K
23
22
UGATE2_VGA
2
2
OPT@
B
1
24
DGPU_PWROK
PR9425
10K_0402_5%
+3VS
2
1
1
2
100_0402_5%
+VGA_CORE
reserve for future tune
5
GND
25
PH2
OPT@
2
LG2
OPT@
PR9435
4.7_1206_5%
@
PC1273
0.1U_0402_25V6
FB
B+
OPT@
OPT@ PQ993
AON6414AL_DFN8-5
PVCC
PH903
100K_0402_1%_NCP15WF104F03RC
2
1
OPT@
PR9426
1
VREFOPT@ 2
5.9K_0402_1%
1
PQ991
AON6414AL_DFN8-5
5
FBRTN
PR9448
+VGA_CORE
5
BOOT1_VGA
PGND
COMP
PR9438
5.1K_0402_1%
@
PHASE1_VGA
EN_VGA
1
BST1
HG1
PSI_VGA
2
5
VID
6
LG1
FS
2
1
11
PC1270
FB_VGA
PC1269
PR9419
47P_0402_50V8J
OPT@ PC1271
1
2FB1_VGA1
2
1
2
COMP_VGA 12
1000P_0402_50V7K
PR9420
OPT@
51_0402_1%
10P_0402_50V8J
PR9421
PC1272
0_0402_5%
OPT@
OPT@
1 VCC_SEN
1
2
1
2FB2_VGA1 PR9422 2
VCCSENSE_VGA OPT@ 2
OPT@
10K_0402_1%
100P_0402_50V8J
82K_0402_1% OPT@
OPT@
PH1
VREF
1
1
PL705
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2
3
2
1
10
VSS_SEN
REFIN
BST2
9
18
8
FS
HG2
VREF
TALERT#
7
2N15VGM@
5600P_0402_25V7-K
PR9439
2
1OPT@
39K_0402_1%
VIDBUF
1
PC1277
14
VSSSENSE_VGA
PC1294
0.01U_0603_50V7K
2
OPT@ 1
PR9449
0_0402_5%
1
OPT@ 2
TSNS
1
100_0402_5%
OPT@
PU909
13
2
N15VGM@
PR9437
6.2K_0402_1%
1
2
2
PR9431
1.74K_0402_1%
N15VGM@
1
2
PR9447
PR9436
0_0402_5%
N15VGM@
UGATE1_VGA
OPT@
2
JUMP_43X79
@
PQ992
4
LGATE1_VGA
OPT@
OPT@
GPU_VID
reserve follow
NV suggestion
7.5K_0402_1%
PR9440
27K_0402_1%
PR9434
1
2
2
1VIDBUF
VREF
N15VGM@
N15VGM@
3
PC1262
2700P_0402_50V7-K
1
2
4
@
OPT@
EN
reserve
PGOOD
27
7.5
0
6.2
1.74
5.6
PC1261
10P_0402_50V8J
2
1
20
20
2
18
0
2.7
1
C
PR9440
PR9434
PR9436
PR9437
PR9431
PC1277
PR9430
0_0402_5%
AON6554_DFN
R1
R2
R3
R4
R5
C(nF)
2
B
D
N15S-GT N15V-GM
4
PR9429
PC1300
0_0603_5%
0.22U_0603_16V7K
2
1BOOT1_2_VGA 1
2
PR9441
OPT@
OPT@
0_0402_5%
2
1 UGATE1_2_VGA
OPT@
5
N15S-GT use config-B
N15V-GM use config-D
2
DGPU_PWROK
17
VCCSENSE_VGA
DGPU_PWROK
PSI
VCCSENSE_VGA
VCC
{20}
16
VSSSENSE_VGA
15
{20}
VSSSENSE_VGA
{23,57}
PJ710
2
PSI_VGA
NVVDD PWM_VID
{19}
PSI_VGA
PC1289
22U_0805_6.3V6M
2
1
NVVDD PWM_VID
1
{19}
PWR-VGA_CORE
Size Document Number
Custom
Date:
Rev
0.2
ACLU9
Monday, December 23, 2013
1
Sheet
58
of
59
5
4
3
2
B+
+3VALW
+3VALW
1
1
1
CPU_GFX_VIN
PJ_43x79_6
PJ901
3A
+1.0VS
1
1
@
PR903
10K_0402_5%
PR904
1
2
PC911
PR913
CORE_GND 133K_0402_1%
GFX_RDYA
PR922
2
1 PR925 2
CORE_GND 68K_0402_1%
1 PR926 2
B+
1K_0402_1%
PC927
0.01U_0402_25V7K
1
VR_HOT#
CPU_RDY
PC933
0.1U_0402_25V6
CORE_GND
PC919
330U_D2_2V_Y
2
1
PC918
22U_0805_6.3V6M
PC917
22U_0805_6.3V6M
2
1
CPU_GFX_VIN
5
@
CORE_GND
PR949
CPU_CSCOMP
1
PC950
2
910_0402_1%
CPU_DROOP
1
2
+CPU_CORE
1000P_0402_50V9-J
CORE_GND
2
4
1 2
CPU_LG
1
2
1
2
2
0.47UH_PCMB063T-R47MS_18A_20%
@PR946
@PR946
2.2_0603_5%
PQ904
2
J901
2
JUMPER
CPU_TSENSE
PH902
Thinking_ERTSM0B224J
CLOSE to GFX inductor
1
B
TSENSEA
AON7506_DFN
@PC951
@PC951
0.47U_0402_25V6K
1
+
2
1
PC948
330U_D2_2V_Y
2
165K_0402_1%
12A
PL902
1
CPU_PH
1
1
75K_0402_1%
1
+CPU_CORE
AON7408L_DFN8-5
PR944
2
3
2
1
CORE_GND
4
2
PC943
0.1U_0402_25V6
1
2
2
PR945
41.2K_0402_1%
CPU_HG
2 CPU_PH
133K_0402_1%
1
1
3
2
1
PR943
1
VR_IMVP_IMON
1
{44}
2200P_0402_50V7K
2
1 PC942
680P_0402_50V7K
10_0402_1% 330P_0402_50V8J 5.9K_0402_1%
PQ903
PR942
2
5
PC941
1
2
2
PR948
8.25K_0402_1%
2
1
1
PH904
100K_0402_1%_NCP15WF104F03RC
2
1
PC940
1
2
PH959
100K_0402_1%_NCP15WF104F03RC
2
1
2
PC937
1200P_0402_50V7-K
PR947
8.25K_0402_1%
2
1
1
10P_0402_50V8J
PR941
PC939
1
2
CPU_CSCOMP
PC938
1
2
2
1K_0402_1%
PR940
PC936
0.1U_0402_25V6
PR939
1
PC935
10U_0805_25V6K
+ PC934
2
10U_0805_25V6K
2
1
PC932
1000P_0402_50V9-J
CORE_GND CPU_CSSUM
PC947
22U_0805_6.3V6M
2
11.8K
PC946
22U_0805_6.3V6M
PC931
1000P_0402_50V7K
2
0_0402_5%
1
0_0402_5%
PR938
1
2
VCC_SENSE
CPU_GFX_VIN
1.5A
1
{9}
+5VALW
CORE_GND
CORE_GND
0.1U_0402_25V6
1
2 CPU_PH
2.94K_0402_1%
PR935
PC930
0.047U_0402_25V7K
+CPU_CORE
2
VSS_SENSE
2
20_0402_1%
2
PC945
22U_0805_6.3V6M
2
1
{9}
C
0.22U_0603_25V7K
1
PR934
1 PR936
PC928
1
2
2
2
CPU_SVID_CLK
+5VALW
1
{7}
PC916
22U_0805_6.3V6M
2
1
1
2
16.9_0402_1%
1
1 PR929
2
0_0402_5%
PC944
22U_0805_6.3V6M
2
0_0402_5%
CPU_LG
CPU_PH
CPU_HG
2.2_0603_5%
1
1
PR933
1
PC920
330U_2.5V_M
PR923
1
PC926
2.2U_0603_6.3V6K
1
2
PR931
13K_0402_1%
1
2
PC929
1
CPU_TSENSE 2
PR937
2
1
14.3K_0402_1% CPU_DROOP
CPU_SVID_ALERT#
1
CPU_SVID_DAT
{7}
+
2
CORE_GND
68U_25V_M
PR932
{7}
+
2
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CORE_GND
2
2
CORE_GND
@PC921
@PC921
0.47U_0402_25V6K
1
PC924
0.22U_0603_25V7K
1
2
PR921
1
2
2.2_0603_5%
GFX_HG
GFX_PH
GFX_LG
4
1
2
PR928
PR930
69.8_0402_1% 69.8_0402_1%
VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK
1 PR924 2
30K_0402_1%
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
NCP6132AMNR2G_QFN60_7X7
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
2
+1.0VS CORE_GND
1
1
1
PR927
69.8_0402_1%
+1.0VS
CORE_GND
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
2
1
@
PC952
1U_0402_6.3V6K
C
2
+1.0VS
PC925 @
0.1U_0402_25V6
1
2
0_0402_5%
2
1
1
EC_VR_ON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
CORE_GND
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PU901
5
PR920
14.7K_0402_1%
1
2
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
2
2.2_0603_5%
PC923
2.2U_0603_6.3V6K
1
2
2
0.47UH_PCMB063T-R47MS_18A_20%
1
3
2
1
1
2
0.1U_0402_25V6
PR919
1
+5VALW
PQ902
GFX_LG
2
CORE_GND
1
GFX_PH
AON7506_DFN @PR916
@PR916
2.2_0603_5%
1
GFX_DROOPA
GFX_CSCOMPA
GFX_CSSUMA
+GFX_CORE
2
0_0402_5%
+GFX_CORE
14A
PL901
PC914
0.047U_0402_25V7K
PR918
1
2
GFX_PH
2.94K_0402_1%
PC922
1
2
CORE_GND
+5VALW
2
PR917
AON7408L_DFN8-5
3
2
1
PC913
1000P_0402_50V7K
4
PC912
1000P_0402_50V7K
CSP1A
TSENSEA
0_0402_5%
1
GFX_HG
1
2
2
PR915
1
VCC_AXG_SENSE
PQ901
2200P_0402_50V7K
PR914
6.8K_0402_1%
2
1
16.5K_0402_1%
1K_0402_1%
1
1
2
2
2
1
PR908
1
PH901
1
2
PR910
1
165K_0402_1%
2 GFX_PH
1 PR911
PC908
2
2
1
PC903
PC915
22U_0805_6.3V6M
2
1
1
2
2
CLOSE to GFX inductor
5
@
10P_0402_50V8J
PR912
1
PC907
D
Thinking_ERTSM0B224J
10_0402_1% 330P_0402_50V8J
75K_0402_1%
2
2
41.2K_0402_1%
PC910
1
2
2
PR907
1
CORE_GND
PC909
1
2
0.1U_0402_25V6
GFX_RDYA
10U_0805_25V6K
CPU_RDY
1 PR906 2
0_0402_5%
1 PR909
{44}
CPU_GFX_VIN
1.5A
1000P_0402_50V9-J
10U_0805_25V6K
1 PR905 2
0_0402_5%
{9}
2
+GFX_CORE
CPU_GFX_VIN
680P_0402_50V7K
PC906
VR_CPU_PWROK
GFX_DROOPA 1
806_0402_1%
PC905
2
1
{44}
D
PC902
0.1U_0402_25V6
1
2
CORE_GND
VR_HOT#
1200P_0402_50V7-K
VR_HOT#
{44}
2
2
2
2
GFX_CSCOMPA
PC901
2
PR902
10K_0402_5%
68U_25V_M
+ PC904
PR901
69.8_0402_1%
+
PC949
330U_2.5V_M
2
B
A
A
Security Classification
Issued Date
Title
LC Future Center Secret Data
2012/09/03
Deciphered Date
2012/09/03
PWR_CPU_CORE/GFX_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Document Number
4
3
2
Rev
0.2
ACLU9
Monday, December 23, 2013
Date:
5
1
Sheet
59
of
59
www.s-manuals.com
Source Exif Data:
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