Cortex A5 Technical Reference Manual
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- Cortex-A5 Technical Reference Manual
- Contents
- List of Tables
- List of Figures
- Preface
- 1: Introduction
- 2: Functional Description
- 3: Programmers Model
- 4: System Control
- 4.1 About system control
- 4.1.1 System control functional groups
- 4.1.2 System control and configuration
- 4.1.3 MMU control and configuration
- 4.1.4 Cache control and configuration
- 4.1.5 Cache Operations Registers
- 4.1.6 System performance monitor registers
- 4.1.7 System feature registers
- 4.1.8 c0, Instruction set attributes registers
- 4.1.9 c7, VA to PA operations
- 4.1.10 c8, TLB maintenance operations
- 4.1.11 c10, Memory region remap
- 4.1.12 c13, Software Thread ID Registers
- 4.1.13 c15, TLB access and attributes
- 4.2 Register summary
- 4.2.1 Virtualization
- 4.2.2 c0 summary table
- 4.2.3 c1 summary table
- 4.2.4 c2 summary table
- 4.2.5 c3 summary table
- 4.2.6 c4 summary table
- 4.2.7 c5 summary table
- 4.2.8 c6 summary table
- 4.2.9 c7 summary table
- 4.2.10 c8 summary table
- 4.2.11 c9 summary table
- 4.2.12 c10 summary table
- 4.2.13 c11 summary table
- 4.2.14 c12 summary table
- 4.2.15 c13 summary table
- 4.2.16 c14 summary table
- 4.2.17 c15 summary table
- 4.3 Register descriptions
- 4.3.1 Main ID Register
- 4.3.2 Cache Type Register
- 4.3.3 TCM Type Register
- 4.3.4 TLB Type Register
- 4.3.5 Multiprocessor Affinity Register
- 4.3.6 Processor Feature Register 0
- 4.3.7 Processor Feature Register 1
- 4.3.8 Debug Feature Register 0
- 4.3.9 Auxiliary Feature Register 0
- 4.3.10 Memory Model Features Register 0
- 4.3.11 Memory Model Features Register 1
- 4.3.12 Memory Model Features Register 2
- 4.3.13 Memory Model Features Register 3
- 4.3.14 Instruction Set Attributes Register 0
- 4.3.15 Instruction Set Attributes Register 1
- 4.3.16 Instruction Set Attributes Register 2
- 4.3.17 Instruction Set Attributes Register 3
- 4.3.18 Instruction Set Attributes Register 4
- 4.3.19 Instruction Set Attributes Register 5
- 4.3.20 Instruction Set Attributes Registers 6-7
- 4.3.21 Cache Size Identification Register
- 4.3.22 Cache Level ID Register
- 4.3.23 Auxiliary ID Register
- 4.3.24 Cache Size Selection Register
- 4.3.25 System Control Register
- 4.3.26 Auxiliary Control Register
- 4.3.27 Coprocessor Access Control Register
- 4.3.28 Secure Configuration Register
- 4.3.29 Secure Debug Enable Register
- 4.3.30 Non-secure Access Control Register
- 4.3.31 Virtualization Control Register
- 4.3.32 Translation Table Base Register 0
- 4.3.33 Translation Table Base Register 1
- 4.3.34 Translation Table Base Control Register
- 4.3.35 Domain Access Control Register
- 4.3.36 Data Fault Status Register
- 4.3.37 Instruction Fault Status Register
- 4.3.38 Auxiliary Data Fault Status Register
- 4.3.39 Auxiliary Instruction Fault Status Register
- 4.3.40 Data Fault Address Register
- 4.3.41 Instruction Fault Address Register
- 4.3.42 NOP Register
- 4.3.43 Physical Address Register
- 4.3.44 Instruction Synchronization Barrier
- 4.3.45 Data Synchronization Barrier
- 4.3.46 Data Memory Barrier
- 4.3.47 Vector Base Address Register
- 4.3.48 Monitor Vector Base Address Register
- 4.3.49 Interrupt Status Register
- 4.3.50 Virtualization Interrupt Register
- 4.3.51 Context ID Register
- 4.3.52 Configuration Base Address Register
- 4.1 About system control
- 5: Non-debug Use of CP14
- 6: Memory Management Unit
- 7: Level 1 Memory System
- 8: Level 2 Memory Interface
- 9: Debug
- 9.1 About debug
- 9.2 Debugging modes
- 9.3 Debug interface
- 9.4 Debug register summary
- 9.5 Debug register descriptions
- 9.5.1 Debug Identification Register
- 9.5.2 Debug Status and Control Register
- 9.5.3 Program Counter Sampling Register
- 9.5.4 Debug State Cache Control Register
- 9.5.5 Event Catch Register
- 9.5.6 Debug State MMU Control Register
- 9.5.7 Operating System Lock and Save/Restore Registers
- 9.5.8 Debug Run Control Register
- 9.5.9 Breakpoint Value Registers
- 9.5.10 Breakpoint Control Registers
- 9.5.11 Watchpoint Value Register
- 9.5.12 Watchpoint Control Register
- 9.5.13 Device Power-down and Reset Control Register
- 9.5.14 Device Power-down and Reset Status Register
- 9.6 Management registers
- 9.7 Integration test registers
- 9.8 External debug interface
- 9.9 Miscellaneous debug signals
- 10: Performance Monitoring Unit
- 10.1 About the Performance Monitoring Unit
- 10.2 Performance monitoring register descriptions
- 10.2.1 Performance Monitor Control Register
- 10.2.2 Count Enable Set Register
- 10.2.3 Count Enable Clear Register
- 10.2.4 Overflow Flag Status Register
- 10.2.5 Software Increment Register
- 10.2.6 Event Counter Selection Register
- 10.2.7 Common Event Identification Registers
- 10.2.8 Cycle Count Register
- 10.2.9 Event Type Select Register
- 10.2.10 Cycle Count Filter Control Register
- 10.2.11 Event Count Registers
- 10.2.12 User Enable Register
- 10.2.13 Interrupt Enable Set Register
- 10.2.14 Interrupt Enable Clear Register
- 10.2.15 Configuration Register
- 10.2.16 Lock Access Register
- 10.2.17 Lock Status Register
- 10.2.18 Authentication Status Register
- 10.2.19 Device Type Register
- 10.2.20 Identification Registers
- A: Signal Descriptions
- A.1 Signal descriptions
- A.1.1 Clock and reset signals
- A.1.2 Interrupt signals
- A.1.3 Configuration signals
- A.1.4 Standby and wait for event signals
- A.1.5 Power management signals
- A.1.6 AXI interfaces
- A.1.7 Performance monitoring signals
- A.1.8 MBIST interface
- A.1.9 Scan test signals
- A.1.10 External debug interface
- A.1.11 Trace interface signals
- A.1 Signal descriptions
- B: Revisions
- Glossary