Intel® PXA27x Processor Family Developer’s Manual Developer's
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- Intel® PXA27x Processor Family Developer's Manual
- Contents :
- Figures:
- Tables:
- Revision History
- Introduction 1
- 1.1 About This Manual
- 1.2 Product Overview
- 1.2.1 Intel XScale® Technology
- 1.2.2 Power Management
- 1.2.3 Internal Memory
- 1.2.4 Interrupt Controller
- 1.2.5 Operating-System Timers
- 1.2.6 Pulse-Width Modulation Unit (PWM)
- 1.2.7 Real-Time Clock (RTC)
- 1.2.8 General-Purpose I/O (GPIO)
- 1.2.9 Memory Controller
- 1.2.10 DMA Controller
- 1.2.11 Serial Ports
- 1.2.12 LCD Panel Controller
- 1.2.13 MultiMediaCard, SD Memory Card, and SDIO Card Controller
- 1.2.14 Memory Stick Host Controller
- 1.2.15 Mobile Scalable Link (MSL) Interface
- 1.2.16 Keypad Interface
- 1.2.17 Universal Subscriber Identity Module (USIM) Interface
- 1.2.18 Quick Capture Camera Interface
- 1.2.19 Test Interface
- 1.3 Intel XScale® Microarchitecture Compatibility
- System Architecture 2
- 2.1 Overview
- 2.2 Intel XScale® Technology Implementation Options
- 2.3 Endianness
- 2.4 I/O Ordering
- 2.5 Semaphores
- 2.6 Interrupts
- 2.7 Reset
- 2.8 Internal Registers
- 2.9 Selecting Peripherals or General-Purpose I/O
- 2.10 Power-On Reset and Boot Operation
- 2.11 Power Management
- 2.12 Signal Descriptions
- Clocks and Power Manager 3
- 3.1 Overview
- 3.2 Features
- 3.3 Signal Descriptions
- 3.3.1 Hardware Reset (nRESET)
- 3.3.2 Internal Reset (nRESET_OUT)
- 3.3.3 GPIO Wake-Up Sources
- 3.3.4 GPIO Reset (nRESET_GPIO/GPIO<1>)
- 3.3.5 Processor Oscillator Input (PXTAL_IN)
- 3.3.6 Processor Oscillator Output (PXTAL_OUT)
- 3.3.7 Processor Clock Input/Output (CLK_PIO/GPIO<9>)
- 3.3.8 Timekeeping Oscillator Input (TXTAL_IN)
- 3.3.9 Timekeeping Oscillator Output (TXTAL_OUT)
- 3.3.10 Timekeeping Clock Output (CLK_TOUT/GPIO<10>)
- 3.3.11 Clock Request (CLK_REQ)
- 3.3.12 External Clock (CLK_EXT)
- 3.3.13 Battery Fault and VDD Fault (nBATT_FAULT, nVDD_FAULT)
- 3.3.14 Power Enable (PWR_EN)
- 3.3.15 System Power Enable (SYS_EN)
- 3.3.16 Power Manager I2C Clock (PWR_SCL/GPIO<3>)
- 3.3.17 Power Manager I2C Data (PWR_SDA/GPIO<4>)
- 3.3.18 Power Manager Capacitor Pins (PWR_CAP<3:0>)
- 3.3.19 Power Manager Supply Output (PWR_OUT)
- 3.3.20 48-MHz Output Clock (48_MHz)
- 3.4 Reset Manager Operation
- 3.5 Clocks Manager Operation
- 3.5.1 External Clock Source Selection (CLK_REQ)
- 3.5.2 13MHz Processor Oscillator
- 3.5.3 32.768kHz Timekeeping Oscillator
- 3.5.4 Peripheral Phase-Locked Loop (312 MHz)
- 3.5.5 Core Phase-Locked Loop (Programmable)
- 3.5.6 Functional-Unit Clock Gating
- 3.5.7 Modifying Clock Frequencies
- 3.5.8 Summary of Clock Modes
- 3.6 Power Manager Operation
- 3.6.1 Power Domains
- 3.6.2 Internal Voltage Regulators
- 3.6.3 Power Manager I2C Interface
- 3.6.4 Power Faults and Imprecise-Data Abort
- 3.6.5 Modifying Power Modes
- 3.6.6 Idle Mode
- 3.6.7 Deep-Idle Mode
- 3.6.8 Standby Mode
- 3.6.9 Sleep Mode
- 3.6.10 Deep-Sleep Mode
- 3.6.11 Initial Power-On and Deep-Sleep Exit Sequence
- 3.6.12 Summary of Power Modes
- 3.7 Voltage Manager Operation
- 3.8 Register Descriptions
- 3.8.1 Power Manager Registers
- 3.8.1.1 Power Manager Control Register (PMCR)
- 3.8.1.2 Power Manager Sleep Status Register (PSSR)
- 3.8.1.3 Power Manager Scratch-Pad Register (PSPR)
- 3.8.1.4 Power Manager Wake-Up Enable Register (PWER)
- 3.8.1.5 Power Manager Rising-Edge Detect Enable Register (PRER)
- 3.8.1.6 Power Manager Falling-Edge Detect Enable Register (PFER)
- 3.8.1.7 Power Manager Edge-Detect Status Register (PEDR)
- 3.8.1.8 Power Manager General Configuration Register (PCFR)
- 3.8.1.9 Power Manager GPIO Sleep-State Registers (PGSRx)
- 3.8.1.10 Reset Controller Status Register (RCSR)
- 3.8.1.11 Power Manager Sleep Configuration Register (PSLR)
- 3.8.1.12 Power Manager Standby Configuration Register (PSTR)
- 3.8.1.13 Power Manager Voltage Change Control Register (PVCR)
- 3.8.1.14 Power Manager USIM Card Control/Status Register (PUCR)
- 3.8.1.15 Power Manager Keyboard Wake-Up Enable Register (PKWR)
- 3.8.1.16 Power Manager Keyboard Level-Detect Status Register (PKSR)
- 3.8.1.17 Power Manager I2C Command Register File (PCMDx)
- 3.8.2 Clocks Manager Registers
- 3.8.3 Coprocessor 14: Clock and Power Management
- 3.8.1 Power Manager Registers
- 3.9 Register Summary
- Internal Memory 4
- DMA Controller 5
- 5.1 Overview
- 5.2 Features
- 5.3 Signal Descriptions
- 5.4 Operation
- 5.4.1 DMA Channels
- 5.4.2 DMA Descriptors
- 5.4.3 Transferring Data
- 5.4.4 Programming Tips
- 5.4.5 Fly-By Transfers
- 5.4.6 How DMA Handles Trailing Bytes
- 5.4.7 Quick Reference to DMA Programming
- 5.4.8 Programming Examples
- 5.5 Register Descriptions
- 5.5.1 DMA Request to Channel Map Register (DRCMRx)
- 5.5.2 DMA Descriptor Address Registers (DDADRx)
- 5.5.3 DMA Source Address Register (DSADRx)
- 5.5.4 DMA Target Address Registers (DTADRx)
- 5.5.5 DMA Command Registers (DCMDx)
- 5.5.6 DMA Fly-By Configuration Register (FLYCNFG)
- 5.5.7 DREQ<2:0> Status Register (DRQSR0/1/2)
- 5.5.8 DMA Channel Control/Status Registers (DCSRx)
- 5.5.9 DMA Interrupt Register (DINT)
- 5.5.10 DMA Alignment Register (DALGN)
- 5.5.11 DMA Programmed I/O Control Status Register (DPCSR)
- 5.6 Register Summary
- Memory Controller 6
- 6.1 Overview
- 6.2 Features
- 6.3 Signal Descriptions
- 6.4 Operation
- 6.4.1 Stacked SDRAM and Flash Memory
- 6.4.2 Synchronous Dynamic Memory (SDRAM) Interface
- 6.4.3 Synchronous, Static, and Variable-Latency I/O (VLIO) Interfaces
- 6.4.4 PC Card and CompactFlash Interface
- 6.4.5 Types and Sizes of Memory Accesses
- 6.4.6 Alternate Bus Master Mode
- 6.4.7 Alternate Booting
- 6.4.8 Memory System Examples
- 6.4.9 Memory Interface Reset and Initialization
- 6.4.10 Hardware, Watchdog, or Sleep/Deep-Sleep/Standby Reset Operation
- 6.4.11 GPIO Reset Procedure
- 6.5 Register Descriptions
- 6.5.1 Synchronous Dynamic Memory Registers
- 6.5.2 Synchronous Static Memory Registers
- 6.5.3 Asynchronous Static Memory Registers
- 6.5.4 Boot Time Default Configuration Register (BOOT_DEF)
- 6.5.5 Expansion Memory Timing Configuration Registers (MCMEMx, MCATTx, MCIOx)
- 6.5.6 Expansion Memory Configuration Register (MECR)
- 6.5.7 Programmable Output Buffer Strength Registers
- 6.6 Register Summary
- LCD Controller 7
- 7.1 Overview
- 7.2 Features
- 7.3 Signal Descriptions
- 7.4 Operation
- 7.4.1 Block Diagram
- 7.4.2 Bandwidth Calculations
- 7.4.3 Pixel Clock Frequency Calculation
- 7.4.4 Multiple Panel Considerations
- 7.4.5 Graphical Overlays
- 7.4.6 Pixel Formats
- 7.4.7 Base Frame
- 7.4.8 Overlay 1 Window
- 7.4.9 Overlay 2 Window
- 7.4.10 Interfacing with LCD Smart Panels
- 7.4.11 Hardware Cursor
- 7.4.11.1 32x32x2bpp and 64x64x2bpp 2-Color and Transparency Modes
- 7.4.11.2 32x32x2bpp and 64x64x2bpp 4-Color Modes
- 7.4.11.3 32x32x2bpp and 64x64x2bpp 3-Color and Transparency Modes
- 7.4.11.4 128x128x1bpp 2-Color Mode
- 7.4.11.5 128x128x1bpp 1-Color and Transparency Mode
- 7.4.11.6 Cursor Positioning
- 7.4.11.7 Cursor Color Map
- 7.4.12 External Palette Buffer
- 7.4.13 Frame Buffer
- 7.4.13.1 Memory Organization for Pixel Depth of 2 bpp
- 7.4.13.2 Memory Organization for Pixel Depth of 4 bpp
- 7.4.13.3 Memory Organization for Pixel Depth of 8 bpp
- 7.4.13.4 Memory Organization for Pixel Depth of 16 bpp
- 7.4.13.5 Memory Organization for Pixel Depth of 18 bpp
- 7.4.13.6 Memory Organization for Pixel Depth of 19 bpp
- 7.4.13.7 Memory Organization for Pixel Depth of 24 bpp
- 7.4.13.8 Memory Organization for Pixel Depth of 25 bpp
- 7.4.13.9 Memory Organization for 4:4:4 YCbCr Packed Format
- 7.4.14 Dual-Scan Mode
- 7.4.15 Functional Timing
- 7.4.16 Using the LCD Controller Data Pins
- 7.4.16.1 Single-Scan/Dual-Scan Select
- 7.4.16.2 Output Pin Drive Format for Passive Single Scan
- 7.4.16.3 8-Bit Interface for Active Monochrome Single Scan
- 7.4.16.4 16-Bit Interface for Active Single Scan
- 7.4.16.5 18-Bit Interface for Active Single Scan
- 7.4.16.6 Summary of Pin Assignments in Active Mode
- 7.4.16.7 8-Bit Interface for Smart Panels
- 7.5 Register Descriptions
- 7.5.1 Using LCD Control Registers
- 7.5.2 LCD Controller Control Register 0 (LCCR0)
- 7.5.3 LCD Controller Control Register 1 (LCCR1)
- 7.5.4 LCD Controller Control Register 2 (LCCR2)
- 7.5.5 LCD Controller Control Register 3 (LCCR3)
- 7.5.6 LCD Controller Control Register 4 (LCCR4)
- 7.5.7 LCD Controller Control Register 5 (LCCR5)
- 7.5.8 Overlay 1 Control Register 1 (OVL1C1)
- 7.5.9 Overlay 1 Control Register 2 (OVL1C2)
- 7.5.10 Overlay 2 Control Register 1 (OVL2C1)
- 7.5.11 Overlay 2 Control Register 2 (OVL2C2)
- 7.5.12 Cursor Control Register (CCR)
- 7.5.13 Command Control Register (CMDCR)
- 7.5.14 TMED RGB Seed Register (TRGBR)
- 7.5.15 TMED Control Register (TCR)
- 7.5.16 DMA Frame Descriptor Address Registers (FDADRx)
- 7.5.17 DMA Frame Branch Registers (FBRx)
- 7.5.18 LCD Buffer Strength Control Register (LCDBSCNTR)
- 7.5.19 Panel Read Status Register (PRSR)
- 7.5.20 LCD Controller Status Register 0 (LCSR0)
- 7.5.21 LCD Controller Status Register 1 (LCSR1)
- 7.5.22 LCD Controller Interrupt ID Register (LIIDR)
- 7.5.23 DMA Frame Source Address Registers (FSADRx)
- 7.5.24 DMA Frame ID Registers (FIDRx)
- 7.5.25 LCD DMA Command Register (LDCMDx)
- 7.6 Register Summary
- SSP Serial Ports 8
- 8.1 Overview
- 8.2 Features
- 8.3 Signal Descriptions
- 8.4 Operation
- 8.4.1 Processor and DMA FIFO Access
- 8.4.2 Trailing Bytes in the Receive FIFO
- 8.4.3 Frame Counter
- 8.4.4 Data Formats
- 8.4.5 High Impedance on SSPTXDx
- 8.4.6 Network Mode
- 8.4.7 Parallel Data Formats for FIFO Storage
- 8.4.8 Continuous Serial Clock Operation
- 8.4.9 FIFO Operation
- 8.4.10 Baud-Rate Generation
- 8.4.11 32-Bit I2S Emulation using SSP
- 8.5 Register Descriptions
- 8.5.1 SSP Control Register 0 (SSCR0_x)
- 8.5.2 SSP Control Register 1 (SSCR1_x)
- 8.5.3 SSP Programmable Serial Protocol Register (SSPSP_x)
- 8.5.4 SSP Time-Out Register (SSTO_x)
- 8.5.5 SSP Interrupt Test Register (SSITR_x)
- 8.5.6 SSP Status Register (SSSR_x)
- 8.5.7 SSP Data Register (SSDR_x)
- 8.5.8 SSP TX Time Slot Active Register (SSTSA_x)
- 8.5.9 SSP RX Time Slot Active Register (SSRSA_x)
- 8.5.10 SSP Time Slot Status Register (SSTSS_x)
- 8.5.11 SSP Audio Clock Divider Register (SSACD_x)
- 8.6 Register Summary
- I2C Bus Interface Unit 9
- 9.1 Overview
- 9.2 Features
- 9.3 Signal Descriptions
- 9.4 Operation
- 9.4.1 Operational Blocks
- 9.4.2 I2C Bus Interface Modes
- 9.4.3 START and STOP Bus States
- 9.4.4 Data Transfer Sequence
- 9.4.5 Data and Addressing Management
- 9.4.6 I2C ACKNOWLEDGE
- 9.4.7 Arbitration
- 9.4.8 Master Operations
- 9.4.9 Master Mode Programming Examples
- 9.4.10 Slave Operations
- 9.4.11 Slave Mode Programming Examples
- 9.4.12 General Call Address
- 9.4.13 Reset Conditions
- 9.5 Register Descriptions
- 9.6 Register Summary
- UARTs 10
- 10.1 Overview
- 10.2 Features
- 10.3 Signal Descriptions
- 10.4 Operation
- 10.4.1 Reset
- 10.4.2 FIFO Operation
- 10.4.3 Auto-Flow Control
- 10.4.4 Auto-Baud-Rate Detection
- 10.4.5 32-Bit Peripheral Bus
- 10.4.6 Slow Infrared Asynchronous Interface
- 10.4.7 Programmable Baud-Rate Generator
- 10.5 Register Descriptions
- 10.5.1 Receive Buffer Register (RBR)
- 10.5.2 Transmit Holding Register (THR)
- 10.5.3 Divisor Latch Registers, Low and High (DLL, DLH)
- 10.5.4 Interrupt Enable Register (IER)
- 10.5.5 Interrupt Identification Register (IIR)
- 10.5.6 FIFO Control Register (FCR)
- 10.5.7 Receive FIFO Occupancy Register (FOR)
- 10.5.8 Auto-Baud Control Register (ABR)
- 10.5.9 Auto-Baud Count Register (ACR)
- 10.5.10 Line Control Register (LCR)
- 10.5.11 Line Status Register (LSR)
- 10.5.12 Modem Control Register (MCR)
- 10.5.13 Modem Status Register (MSR)
- 10.5.14 Scratchpad Register (SCR)
- 10.5.15 Infrared Selection Register (ISR)
- 10.6 Register Summary
- Fast Infrared Communications Port 11
- 11.1 Overview
- 11.2 Signal Descriptions
- 11.3 Operation
- 11.3.1 4PPM Modulation
- 11.3.2 Frame Format
- 11.3.3 Address Field
- 11.3.4 Control Field
- 11.3.5 Data Field
- 11.3.6 CRC Field
- 11.3.7 Baud Rate Generation
- 11.3.8 Receive Operation
- 11.3.9 Transmit Operation
- 11.3.10 Transmit and Receive FIFOs
- 11.3.11 Removing Trailing Bytes in Receive FIFO
- 11.3.12 32-Bit Peripheral Bus
- 11.4 Register Descriptions
- 11.5 Register Summary
- USB Client Controller 12
- 12.1 Overview
- 12.2 Features
- 12.3 Signal Descriptions
- 12.4 Operation
- 12.5 USB On-The-Go Operation
- 12.6 Register Descriptions
- 12.6.1 UDC Control Register (UDCCR)
- 12.6.2 UDC Interrupt Control Registers (UDCICR0, UDCICR1, and UDCOTGICR)
- 12.6.3 USB Port 2 Output Control Register (UP2OCR)
- 12.6.3.1 USB Host Controller Single-Ended Output Select
- 12.6.3.2 USB Host Port 2 Transceiver Output Enable
- 12.6.3.3 USB Host Port 2 Transceiver Output Select
- 12.6.3.4 OTG ID Output Enable
- 12.6.3.5 External Transceiver Suspend Enable
- 12.6.3.6 External Transceiver Speed Control
- 12.6.3.7 Host Port 2 D- Pull-Up Bypass Enable
- 12.6.3.8 Host Port 2 D- Pull-Up Enable
- 12.6.3.9 Host Port 2 D+ Pull-Up Enable
- 12.6.3.10 Host Port 2 Pull D- Down Enable
- 12.6.3.11 Host Port 2 Pull D+ Down Enable
- 12.6.3.12 Charge Pump Vbus Pulse Enable
- 12.6.3.13 Charge Pump Vbus Enable
- 12.6.4 USB Port 3 Output Control Register (UP3OCR)
- 12.6.5 UDC Interrupt Status Registers (UDCISR0, UDCISR1, and UDCOTGISR)
- 12.6.6 UDC Frame Number Register (UDCFNR)
- 12.6.7 UDC Endpoint 0 Control/Status Register (UDCCSR0)
- 12.6.8 UDC Endpoints A-X Control Status Registers (UDCCRSA- UDCCRSX)
- 12.6.9 UDC Byte Count Registers (UDCBCR0 and UDCBCRA- UDCBCRX)
- 12.6.10 UDC Data Registers (UDCDR0 and UDCDRA--UDCDRX)
- 12.6.11 UDC Endpoint A-X Configuration Registers (UDCCRA- UDCCRX)
- 12.7 Register Summary
- AC ‘97 Controller 13
- 13.1 Overview
- 13.2 Features
- 13.3 Signal Descriptions
- 13.4 AC-Link Digital Serial Interface Protocol
- 13.4.1 AC-Link Audio Output Frame (AC97_SDATA_OUT)
- 13.4.2 AC-Link Audio Input Frame (AC97_SDATA_IN)
- 13.4.2.1 Slot 0: Tag Phase
- 13.4.2.2 Slot 1: Status Address Port/SLOTREQ Bits
- 13.4.2.3 Slot 2: Status Data Port
- 13.4.2.4 Slot 3: PCM Record Left Channel
- 13.4.2.5 Slot 4: PCM Record Right Channel
- 13.4.2.6 Slot 5: Optional Modem Line Codec
- 13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
- 13.4.2.8 Slots 7-11: Reserved
- 13.4.2.9 Slot 12: I/O Status
- 13.5 AC-Link Low-Power Modes
- 13.6 Operation
- 13.7 Register Descriptions
- 13.7.1 Global Control Register (GCR)
- 13.7.2 Global Status Register (GSR)
- 13.7.3 PCM Out Control Register (POCR)
- 13.7.4 PCM In Control Register (PCMICR)
- 13.7.5 PCM Out Status Register (POSR)
- 13.7.6 PCM In Status Register (PCMISR)
- 13.7.7 Codec Access Register (CAR)
- 13.7.8 PCM Data Register (PCDR)
- 13.7.9 Microphone In Control Register (MCCR)
- 13.7.10 Microphone In Status Register (MCSR)
- 13.7.11 Microphone In Data Register (MCDR)
- 13.7.12 Modem Out Control Register (MOCR)
- 13.7.13 Modem In Control Register (MICR)
- 13.7.14 Modem Out Status Register (MOSR)
- 13.7.15 Modem In Status Register (MISR)
- 13.7.16 Modem Data Register (MODR)
- 13.7.17 Accessing Codec Registers
- 13.8 Register Summary
- Inter-IC Sound (I2S) Controller 14
- 14.1 Overview
- 14.2 Features
- 14.3 Signal Descriptions
- 14.4 Operation
- 14.5 Register Descriptions
- 14.5.1 Serial Audio Controller Global Control Register (SACR0)
- 14.5.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)
- 14.5.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
- 14.5.4 Serial Audio Clock Divider Register (SADIV)
- 14.5.5 Serial Audio Interrupt Clear Register (SAICR)
- 14.5.6 Serial Audio Interrupt Mask Register (SAIMR)
- 14.5.7 Serial Audio Data Register (SADR)
- 14.6 Register Summary
- MultiMediaCard/SD/SDIO Controller 15
- 15.1 Overview
- 15.2 Features
- 15.3 Signal Descriptions
- 15.4 Operation
- 15.5 Interrupts
- 15.6 Clock Control
- 15.7 Data FIFOs
- 15.8 MMC/SD Card Communications Protocol
- 15.8.1 Start and Stop Clock
- 15.8.2 Enabling SPI Mode
- 15.8.3 Basic, No Data, and Command-Response Sequence
- 15.8.4 Data Transfer
- 15.8.5 Busy Sequence
- 15.8.6 SPI Functionality
- 15.8.7 SDIO Card Communications Protocol
- 15.8.8 Basic, No Data, Command-Response Sequence
- 15.8.9 Data Transfer
- 15.8.10 Overlapping a Command with a Data Transfer
- 15.8.11 Busy Sequence
- 15.8.12 SPI Functionality
- 15.8.13 SDIO Interrupts
- 15.8.14 SDIO Suspend/Resume
- 15.8.15 SDIO Read Wait
- 15.9 Register Descriptions
- 15.9.1 MMC Clock Start/Stop Register (MMC_STRPCL)
- 15.9.2 MMC Status Register (MMC_STAT)
- 15.9.3 MMC Clock Rate Register (MMC_CLKRT)
- 15.9.4 MMC SPI Mode Register (MMC_SPI)
- 15.9.5 MMC Command/Data Register (MMC_CMDAT)
- 15.9.6 MMC Response Time-Out Register (MMC_RESTO)
- 15.9.7 MMC Read Time-Out Register (MMC_RDTO)
- 15.9.8 MMC Block Length Register (MMC_BLKLEN)
- 15.9.9 MMC Number of Blocks Register (MMC_NUMBLK)
- 15.9.10 MMC Buffer Partly Full Register (MMC_PRTBUF)
- 15.9.11 MMC Interrupt Mask Register (MMC_I_MASK)
- 15.9.12 MMC Interrupt Request Register (MMC_I_REG)
- 15.9.13 MMC Command Register (MMC_CMD)
- 15.9.14 MMC Argument High Register (MMC_ARGH)
- 15.9.15 MMC Argument Low Register (MMC_ARGL)
- 15.9.16 MMC Response FIFO (Read-Only) (MMC_RES)
- 15.9.17 MMC Receive FIFO (Read-Only) (MMC_RXFIFO)
- 15.9.18 MMC Transmit FIFO (MMC_TXFIFO)
- 15.9.19 MMC RD_WAIT Register (MMC_RDWAIT)
- 15.9.20 MMC Blocks Remaining Register (MMC_BLKS_REM)
- 15.10 Register Summary
- Mobile Scalable Link (MSL) Interface 16
- 16.1 Overview
- 16.2 Features
- 16.3 Signal Descriptions
- 16.4 Operation
- 16.5 Register Descriptions
- 16.5.1 MSL FIFO Registers (BBFIFOx)
- 16.5.2 MSL Channel Configuration Registers (BBCFGx)
- 16.5.3 MSL Channel Status Registers (BBSTATx)
- 16.5.4 MSL Channel EOM Registers (BBEOMx)
- 16.5.5 MSL Interrupt ID Register (BBIID)
- 16.5.6 MSL Transmit Frequency Select Register (BBFREQ)
- 16.5.7 MSL Wait Count Register (BBWAIT)
- 16.5.8 MSL Clock Stop Time Register (BBCST)
- 16.5.9 MSL Wake-Up Register (BBWAKE)
- 16.5.10 MSL Interface Width Register (BBITFC)
- 16.6 Register Summary
- Memory Stick Host Controller 17
- 17.1 Overview
- 17.2 Features
- 17.3 Signal Descriptions
- 17.4 Operation
- 17.5 Register Descriptions
- 17.5.1 MSHC Command Register (MSCMR)
- 17.5.2 MSHC Control and Status Register (MSCRSR)
- 17.5.3 MSHC Interrupt and Status Register (MSINT)
- 17.5.4 MSHC Interrupt Enable Register (MSINTEN)
- 17.5.5 MSHC Control Register 2 (MSCR2)
- 17.5.6 MSHC ACD Command Register (MSACD)
- 17.5.7 MSHC Receive FIFO Register (MSRXFIFO)
- 17.5.8 MSHC Transmit FIFO Register (MSTXFIFO)
- 17.6 Register Summary
- Keypad Interface 18
- 18.1 Overview
- 18.2 Features
- 18.3 Signal Descriptions
- 18.4 Operation
- 18.5 Register Descriptions
- 18.5.1 Keypad Interface Control Register (KPC)
- 18.5.2 Keypad Interface Direct Key Register (KPDK)
- 18.5.3 Keypad Interface Rotary Encoder Count Register (KPREC)
- 18.5.4 Keypad Interface Matrix Key Register (KPMK)
- 18.5.5 Keypad Interface Automatic Scan Register (KPAS)
- 18.5.6 Keypad Interface Automatic Scan Multiple Keypress Registers 0-3 (KPASMKPx)
- 18.5.7 Keypad Interface Key Debounce Interval Register (KPKDI)
- 18.6 Register Summary
- Universal Subscriber ID Interface 19
- 19.1 Overview
- 19.2 Features
- 19.3 Signal Descriptions
- 19.4 Operation
- 19.5 Register Descriptions
- 19.5.1 USIM Receive Buffer Register (RBR)
- 19.5.2 USIM Transmit Holding Register (THR)
- 19.5.3 USIM Interrupt Enable Register (IER)
- 19.5.4 USIM Interrupt Identification Register (IIR)
- 19.5.5 USIM FIFO Control Register (FCR)
- 19.5.6 USIM FIFO Status Register (FSR)
- 19.5.7 USIM Error Control Register (ECR)
- 19.5.8 USIM Line Control Register (LCR)
- 19.5.9 USIM Card Control Register (USCCR)
- 19.5.10 USIM Line Status Register (LSR)
- 19.5.11 USIM Extra Guard Time Register (EGTR)
- 19.5.12 USIM Block Guard Time Register (BGTR)
- 19.5.13 USIM Time-Out Register (TOR)
- 19.5.14 USIM Clock Register (CLKR)
- 19.5.15 USIM Divisor Latch Register (DLR)
- 19.5.16 USIM Factor Latch Register (FLR)
- 19.5.17 USIM Character Waiting Time Register (CWTR)
- 19.5.18 USIM Block Waiting Time Register (BWTR)
- 19.6 Register Summary
- USB Host Controller 20
- 20.1 Overview
- 20.2 Features
- 20.3 Signal Descriptions
- 20.4 Operation
- 20.5 Interrupts
- 20.6 Programming Considerations
- 20.7 Power Management
- 20.8 Register Descriptions
- 20.8.1 UHC HCI Spec Revision Register (UHCREV)
- 20.8.2 UHC Host Control Register (UHCHCON)
- 20.8.3 UHC Command Status Register (UHCCOMS)
- 20.8.4 UHC Interrupt Status Register (UHCINTS)
- 20.8.5 UHC Interrupt Enable Register (UHCINTE)
- 20.8.6 UHC Interrupt Disable Register (UHCINTD)
- 20.8.7 UHC Host Controller Communication Area (UHCHCCA)
- 20.8.8 UHC Period Current Endpoint Descriptor (UHCPCED)
- 20.8.9 UHC Control Head Endpoint Descriptor (UHCCHED)
- 20.8.10 UHC Control Current Endpoint Descriptor (UHCCCED)
- 20.8.11 UHC Bulk Head Endpoint Descriptor (UHCBHED)
- 20.8.12 UHC Bulk Current Endpoint Descriptor (UHCBCED)
- 20.8.13 UHC Done Head Register (UHCDHEAD)
- 20.8.14 UHC Frame Interval Register (UHCFMI)
- 20.8.15 UHC Frame Remaining Register (UHCFMR)
- 20.8.16 UHC Frame Number Register (UHCFMN)
- 20.8.17 UHC Periodic Start Register (UHCPERS)
- 20.8.18 UHC Low-Speed Threshold Register (UHCLST)
- 20.8.19 UHC Root Hub Descriptor A Register (UHCRHDA)
- 20.8.20 UHC Root Hub Descriptor B Register (UHCRHDB)
- 20.8.21 UHC Root Hub Status Register (UHCRHS)
- 20.8.22 UHC Root Hub Port Status 1/2/3 Registers (UHCRHPS1, UHCRHPS2, and UHCRHPS3)
- 20.8.23 UHC Status Register (UHCSTAT)
- 20.8.24 UHC Reset Register (UHCHR)
- 20.8.25 UHC Interrupt Enable Register (UHCHIE)
- 20.8.26 UHC Interrupt Test Register (UHCHIT)
- 20.9 Register Summary
- Real-Time Clock (RTC) 21
- 21.1 Overview
- 21.2 Features
- 21.3 Signal Descriptions
- 21.4 Operation
- 21.5 Register Descriptions
- 21.5.1 RTC Trim Register (RTTR)
- 21.5.2 RTC Status Register (RTSR)
- 21.5.3 RTC Alarm Register (RTAR)
- 21.5.4 RTC Wristwatch Day Alarm Registers (RDARx)
- 21.5.5 RTC Wristwatch Year Alarm Registers (RYARx)
- 21.5.6 RTC Stopwatch Alarm Registers (SWARx)
- 21.5.7 RTC Periodic Interrupt Alarm Register (PIAR)
- 21.5.8 RTC Counter Register (RCNR)
- 21.5.9 RTC Day Counter Register (RDCR)
- 21.5.10 RTC Year Counter Register (RYCR)
- 21.5.11 RTC Stopwatch Counter Register (SWCR)
- 21.5.12 RTC Periodic Interrupt Counter Register (RTCPICR)
- 21.6 Register Summary
- Operating System Timers 22
- 22.1 Overview
- 22.2 Features
- 22.3 Signal Descriptions
- 22.4 Operation
- 22.5 Register Descriptions
- 22.5.1 OS Match Control Registers (OMCRx)
- 22.5.2 OS Timer Match Registers (OSMRx)
- 22.5.3 OS Timer Watchdog Match Enable Register (OWER)
- 22.5.4 OS Timer Interrupt Enable Register (OIER)
- 22.5.5 OS Timer Count Register 0 (OSCR0)
- 22.5.6 OS Timer Count Registers (OSCR4-11)
- 22.5.7 OS Timer Status Register (OSSR)
- 22.5.8 OS Timer Snapshot Register (OSNR)
- 22.6 Register Summary
- Pulse Width Modulator Controller 23
- General-Purpose I/O Controller 24
- 24.1 Overview
- 24.2 Features
- 24.3 Signal Descriptions
- 24.4 Operation
- 24.5 Register Descriptions
- 24.5.1 GPIO Pin-Direction Registers (GPDR)
- 24.5.2 GPIO Pin-Output Set Registers (GPSR) and GPIO Pin- Output Clear Registers (GPCR)
- 24.5.3 GPIO Rising-Edge Detect Enable Registers (GRER0/1/2/3) and Falling-Edge Detect Enable Registers (GFER0/1/2/3)
- 24.5.4 GPIO Alternate Function Register (GAFR)
- 24.5.5 GPIO Pin-Level Registers (GPLRx)
- 24.5.6 GPIO Edge Detect Status Register (GEDR)
- 24.6 Register Summary
- Interrupt Controller 25
- 25.1 Overview
- 25.2 Features
- 25.3 Signal Descriptions
- 25.4 Operation
- 25.5 Register Descriptions
- 25.5.1 Interrupt Controller Pending Registers (ICPR and ICPR2)
- 25.5.2 Interrupt Controller IRQ Pending Registers (ICIP and ICIP2)
- 25.5.3 Interrupt Controller FIQ Pending Registers (ICFP and ICFP2)
- 25.5.4 Interrupt Controller Mask Registers (ICMR and ICMR2)
- 25.5.5 Interrupt Controller Level Registers (ICLR and ICLR2)
- 25.5.6 Interrupt Controller Control Register (ICCR)
- 25.5.7 Interrupt Priority Registers 0-39 (IPRx)
- 25.5.8 Interrupt Control Highest Priority Register (ICHP)
- 25.6 Register Summary
- Software Debug 26
- 26.1 Overview
- 26.2 Features
- 26.3 Signal Descriptions
- 26.4 Operation
- 26.4.1 Debug Exceptions
- 26.4.2 Hardware Breakpoint Resources
- 26.4.3 Software Breakpoints
- 26.4.4 Normal RX Handshaking versus High-Speed Download
- 26.4.5 Executing Conditionally Using TXRXCTRL
- 26.4.6 Debug JTAG Access
- 26.4.7 Trace Buffer
- 26.4.8 Halt Mode Software Protocol
- 26.4.9 Software Debug Notes
- 26.5 Register Descriptions
- 26.5.1 Transmit/Receive Control Register (TXRXCTRL)
- 26.5.2 Debug Control and Status Register (DCSR)
- 26.5.3 Data Breakpoint Controls Register (DBCON)
- 26.5.4 Instruction Breakpoint Address and Control Register (IBCRx)
- 26.5.5 Data Breakpoint Register (DBRx)
- 26.5.6 Transmit Register (TX)
- 26.5.7 Receive Register (RX)
- 26.5.8 Checkpoint Registers (CHKPTx)
- 26.5.9 Trace Buffer Register (TBREG)
- 26.6 Register Summary
- Quick Capture Interface 27
- 27.1 Overview
- 27.2 Features
- 27.3 Signal Descriptions
- 27.4 Operation
- 27.4.1 Operating Modes
- 27.4.2 Clock (CICLK and MCLK) Generation
- 27.4.3 Serial-to-Parallel Conversion
- 27.4.4 FIFO Operation
- 27.4.5 Pixel Formats
- 27.4.6 Functional Timing
- 27.5 Register Descriptions
- 27.5.1 Quick Capture Interface Control Register 0 (CICR0)
- 27.5.2 Quick Capture Interface Control Register 1 (CICR1)
- 27.5.3 Quick Capture Interface Control Register 2 (CICR2)
- 27.5.4 Quick Capture Interface Control Register 3 (CICR3)
- 27.5.5 Quick Capture Interface Control Register 4 (CICR4)
- 27.5.6 Quick Capture Interface Time-Out Register (CITOR)
- 27.5.7 Quick Capture Interface Status Register (CISR)
- 27.5.8 Quick Capture Interface FIFO Control Register (CIFR)
- 27.5.9 Quick Capture Interface Receive Buffer Registers (CIBRx)
- 27.6 Register Summary
- Memory Map and Registers 28
- System Bus Arbiter 29
- Glossary
- Index