E200z4 Power Architecture ™ Core Reference ManuaL

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e200z4 Power Architecture™ Core Reference Manual
Contents
Figures
Tables
About This Book
- Audience
- Organization
- Suggested Reading
  - General Information
- Acronyms and Abbreviations
  - Table i. Acronyms and Abbreviated Terms
- Terminology Conventions
  - Table ii. Terminology Conventions
  - Table iii. Instruction Field Conventions
Chapter 1 e200z4 Core Complex Overview
- 1.1 Overview
  - Figure 1-1. e200z446n3 Block Diagram
- 1.2 Features
- 1.3 Programming Model
- 1.4 Microarchitecture Summary
Chapter 2 Register Model
- Figure 2-1. e200z446n3 Supervisor Mode Programmer’s Model SPRs
- Figure 2-2. e200z446n3 User-Mode Programmer’s Model SPRs
- 2.1 Power ISA Embedded Category Registers
  - 2.1.1 User-level Registers
  - 2.1.2 Supervisor-level Registers
- 2.2 e200-Specific Special Purpose Registers
  - 2.2.1 User-Level Registers
  - 2.2.2 Supervisor-Level Registers
- 2.3 e200-Specific Device Control Registers
- 2.4 Special Purpose Register Descriptions
- 2.5 SPR Register Access
- 2.6 Reset Settings
  - Table 2-16. Reset Settings for e200 Resources
Chapter 3 Instruction Model
- 3.1 Unsupported Instructions and Instruction Forms
  - Table 3-1. List of Unsupported Instructions
- 3.2 Optionally Supported Instructions and Instruction Forms
  - Table 3-2. List of Optionally Supported Instructions
- 3.3 Implementation Specific Instructions
  - Table 3-3. Implementation-specific Instruction Summary
- 3.4 Power ISA Instruction Extensions
- 3.5 Memory Access Alignment Support
- 3.6 Memory Synchronization and Reservation Instructions
- 3.7 Branch Prediction
- 3.8 Interruption of Instructions by Interrupt Requests
- 3.9 New e200z4 Categories
- 3.10 ISEL Instruction
- 3.11 Enhanced Debug
  - 3.11.1 Debug Notify Halt Instructions
- 3.12 Machine Check
- 3.13 WAIT Instruction
- 3.14 Enhanced Reservations
- 3.15 Volatile Context Save/Restore
  - Table 3-4. Volatile Context Save/Restore Instruction Set
- 3.16 Unimplemented SPRs and Read-Only SPRs
- 3.17 Invalid Forms of Instructions
- 3.18 Instruction Summary
  - 3.18.1 Instruction Index Sorted by Mnemonic
    - Table 3-5. Instructions Sorted by Mnemonic
  - 3.18.2 Instruction Index Sorted by Opcode
    - Table 3-6. Instructions Sorted by Opcode
Chapter 4 Instruction Pipeline and Execution Timing
- 4.1 Overview of Operation
  - Figure 4-1. e200z4 Block Diagram
  - Table 4-1. Concurrent Instruction Issue Capabilities
- 4.2 Core Subsystems
- 4.3 Execution Units
- 4.4 Instruction Pipeline
- 4.5 Control Hazards
- 4.6 Instruction Serialization
- 4.7 Interrupt Recognition and Exception Processing
- 4.8 Concurrent Instruction Execution
- 4.9 Instruction Timings
  - Table 4-3. Instruction Class Cycle Counts
  - Table 4-4. Instruction Timing by Mnemonic
- 4.10 Operand Placement On Performance
  - Table 4-5. Performance Effects of Storage Operand Placement
Chapter 5 Interrupts and Exceptions
- 5.1 Interrupts
  - 5.1.1 Interrupt Classes
  - 5.1.2 Interrupt Types
- 5.2 Exception Syndrome Register
  - Figure 5-1. Exception Syndrome Register (ESR)
  - Table 5-4. ESR Bit Settings
- 5.3 Machine State Register
  - Figure 5-2. Machine State Register (MSR)
  - Table 5-5. MSR Bit Settings
- 5.4 Machine Check Syndrome Register (MCSR)
  - Figure 5-3. Machine Check Syndrome Register (MCSR)
  - Table 5-6. Machine Check Syndrome Register (MCSR)
- 5.5 Interrupt Vector Prefix Registers (IVPR)
  - Figure 5-4. e200 Interrupt Vector Prefix Register (IVPR)
  - Table 5-7. IVPR Register Fields
- 5.6 Interrupt Vector Offset Registers (IVORxx)
  - Figure 5-5. e200 Interrupt Vector Offset Register (IVOR)
  - Table 5-8. IVOR Register Fields
- 5.7 Interrupt Definitions
- 5.8 Exception Recognition and Priorities
  - 5.8.1 Exception Priorities
    - Table 5-34. e200 Exception Priorities
- 5.9 Interrupt Processing
- 5.10 Process Switching
Chapter 6 Embedded Floating-Point Unit, Version 2
- 6.1 Nomenclature and Conventions
- 6.2 EFPU Programming Model
- 6.3 Embedded Floating-Point Unit Operations
- 6.4 Embedded Floating-point Results Summary
- 6.5 EFPU Instruction Timing
  - 6.5.1 EFPU Single-Precision Vector Floating-Point Instruction Timing
    - Table 6-13. EFPU Vector Floating-Point Instruction Timing
  - 6.5.2 EFPU Single-Precision Scalar Floating-Point Instruction Timing
    - Table 6-14. EFPU Scalar Floating-Point Instruction Timing
- 6.6 Instruction Forms and Opcodes
Chapter 7 Signal Processing Extension Unit
- 7.1 Nomenclature and Conventions
- 7.2 SPE Programming Model
- 7.3 Integer SPE Simple Instructions
- 7.4 Integer SPE Multiply, Multiply-Accumulate, and Operation to Accumulator Instructions (Complex Integer Instructions)
- 7.5 SPE Vector Load/Store Instructions
- 7.6 SPE Instruction Timing
- 7.7 Instruction Forms and Opcodes
Chapter 8 Power Management
- 8.1 Active State
- 8.2 Waiting State
- 8.3 Halted State
- 8.4 Stopped State
  - Figure 8-1. Power Management State Diagram
- 8.5 Power Management Pins
  - Table 8-1. Power Management Pins
- 8.6 Power Management Control Bits
- 8.7 Software Considerations for Power Management using Wait Instructions
- 8.8 Software Considerations for Power Management using Doze, Nap or Sleep
- 8.9 Debug Considerations for Power Management
Chapter 9 L1 Cache
- 9.1 Overview
- 9.2 4 Kbyte ICache Organization
  - Figure 9-1. e200z446n3 ICache Block Diagram
  - Figure 9-2. Cache Organization and Line Format
- 9.3 Cache Lookup
  - Figure 9-3. ICache Lookup Flow
- 9.4 Cache Control
- 9.5 Cache Organization Control
- 9.6 Cache Operation
- 9.7 Cache Parity and EDC Protection
- 9.8 Cache Management Instructions
- 9.9 Touch Instructions
- 9.10 Cache Line Locking/Unlocking
- 9.11 Cache Instructions and Exceptions
  - 9.11.1 Exception Conditions for Cache Instructions
    - Table 9-7. Special Case Handling
  - 9.11.2 Transfer Type Encodings for Cache Management Instructions
    - Table 9-8. Transfer Type Encoding
- 9.12 Self-Modifying Code Requirements
- 9.13 Page Table Control Bits
  - 9.13.1 Cache-Inhibited Accesses
- 9.14 Effect of Hardware Debug on Cache Operation
- 9.15 Cache Memory Access For Debug/Error Handling
- 9.16 Hardware Debug (Cache) Control Register 0
  - Figure 9-11. Hardware Debug Control Register 0 (HDBCR0)
  - Table 9-11. HDBCR0 Field Descriptions
Chapter 10 Memory Management Unit
- 10.1 Overview
- 10.2 Effective to Real Address Translation
- 10.3 Translation Lookaside Buffer
  - Table 10-2. TLB Entry Bit Definitions
- 10.4 Configuration Information
- 10.5 Software Interface and TLB Instructions
- 10.6 TLB Operations
- 10.7 MMU Control Registers
- 10.8 TLB Coherency Control
- 10.9 Core Interface Operation for MMU Control Instructions
  - 10.9.1 Transfer Type Encodings for MMU Control Instructions
    - Table 10-16. Transfer Type Encoding
- 10.10 Effect of Hardware Debug on MMU Operation
- 10.11 External Translation Alterations for Real-time Systems
  - Figure 10-16. External Translation Alteration TLB Entry Compare Process
Chapter 11 Debug Support
- 11.1 Overview
- 11.2 Software Debug Events and Exceptions
- 11.3 Debug Registers
- 11.4 External Debug Support
- 11.5 Watchpoint Support
  - Table 11-27. Watchpoint Output Signal Assignments
- 11.6 MMU and Cache Operation During Debug
- 11.7 Cache Array Access During Debug
- 11.8 Basic Steps for Enabling, Using, and Exiting External Debug Mode
- 11.9 Parallel Signature Unit
Chapter 12 Nexus 3+ Module
- 12.1 Introduction
  - 12.1.1 Terms and Definitions
    - Table 12-1. Terms and Definitions
  - 12.1.2 Feature List
  - 12.1.3 Functional Block Diagram
    - Figure 12-1. Nexus 3+ Functional Block Diagram
- 12.2 Enabling Nexus 3+ Operation
- 12.3 TCODEs Supported
  - Table 12-2. Supported TCODEs
  - Table 12-3. Error Code Encoding (TCODE = 8)
  - Table 12-4. Error Type Encoding (TCODE = 8)
  - Table 12-5. RCODE values (TCODE = 27)
  - Table 12-6. Event Code Encoding (TCODE = 33)
  - Table 12-7. Data Trace Size Encodings (TCODE = 5,6,13,14)
- 12.4 Nexus 3+ Programmer’s Model
  - Table 12-8. Nexus 3+ Register Map
  - 12.4.1 Client Select Control (CSC)-reference only
    - Figure 12-2. Client Select Control Register
    - Table 12-9. Client Select Control Register Fields
  - 12.4.2 Port Configuration Register (PCR)-reference only
    - Figure 12-3. Port Configuration Register
    - Table 12-10. Port Configuration Register Fields
  - 12.4.3 Nexus Development Control Register 1 (DC1)
    - Figure 12-4. Development Control Register 1
    - Table 12-11. Development Control Register 1 Fields
  - 12.4.4 Nexus Development Control Registers 2 and 3 (DC2, DC3)
  - 12.4.5 Nexus Development Control Register 4 (DC4)
    - Figure 12-7. Development Control Register 4
    - Table 12-14. Development Control Register 4 Fields
  - 12.4.6 Development Status Register (DS)
    - Figure 12-8. Development Status Register
    - Table 12-15. Development Status Register Fields
  - 12.4.7 Watchpoint Trigger Registers (WT, PTSTC, PTETC, DTSTC, DTETC)
  - 12.4.8 Nexus Watchpoint Mask Register (WMSK)
    - Figure 12-14. Watchpoint Mask Register
    - Table 12-21. Watchpoint Mask Register Fields
  - 12.4.9 Nexus Overrun Control Register (OVCR)
    - Figure 12-15. Nexus Overrun Control Register
    - Table 12-22. Nexus Overrun Control Register Fields
  - 12.4.10 Data Trace Control Register (DTC)
    - Figure 12-16. Data Trace Control Register
    - Table 12-23. Data Trace Control Register Fields
  - 12.4.11 Data Trace Start Address Registers (DTSA1-4)
  - 12.4.12 Data Trace End Address Registers (DTEA1-4)
  - 12.4.13 Read/Write Access Control/Status (RWCS)
  - 12.4.14 Read/Write Access Data (RWD)
  - 12.4.15 Read/Write Access Address (RWA)
    - Figure 12-27. Read/Write Access Address Register
- 12.5 Nexus 3+ Register Access via JTAG/OnCE
- 12.6 Nexus Message Fields
  - 12.6.1 TCODE Field
  - 12.6.2 Source ID Field (SRC)
  - 12.6.3 Relative Address Field (U-ADDR)
    - Figure 12-28. Relative Address Generation and Recreation
  - 12.6.4 Full Address Field (F-ADDR)
  - 12.6.5 Address Space Indication Field (MAP)
- 12.7 Nexus Message Queues
  - 12.7.1 Message Queue Overrun
  - 12.7.2 CPU Stall
  - 12.7.3 Message Suppression
  - 12.7.4 Nexus Message Priority
    - Table 12-29. Message Type Priority and Message Dropped Responses
  - 12.7.5 Data Acquisition Message Priority Loss Response
  - 12.7.6 Ownership Trace Message Priority Loss Response
  - 12.7.7 Program Trace Message Priority Loss Response
  - 12.7.8 Data Trace Message Priority Loss Response
- 12.8 Debug Status Messages
  - Figure 12-29. Debug Status Message Format
- 12.9 Error Messages
  - Figure 12-30. Error Message Format
- 12.10 Ownership Trace
  - 12.10.1 Overview
  - 12.10.2 Ownership Trace Messaging (OTM)
    - Figure 12-31. Ownership Trace Message Format
- 12.11 Program Trace
  - 12.11.1 Branch Trace Messaging Types
  - 12.11.2 BTM Message Formats
  - 12.11.3 Program Trace Message Fields
  - 12.11.4 Resource Full Messages
    - Figure 12-35. Resource Full Message Format
    - Table 12-33. RCODE Encoding
  - 12.11.5 Program Correlation Messages
  - 12.11.6 Program Trace Overflow Error Messages
  - 12.11.7 Program Trace Synchronization Messages
  - 12.11.8 Enabling Program Trace
  - 12.11.9 Program Trace Timing Diagrams (2 MDO/1 MSEO configuration)
- 12.12 Data Trace
  - 12.12.1 Data Trace Messaging (DTM)
  - 12.12.2 DTM Message Formats
  - 12.12.3 DTM Operation
  - 12.12.4 Data Trace Timing Diagrams(8 MDO/2 MSEO configuration)
    - Figure 12-46. Data Trace-Data Write Message
    - Figure 12-47. Data Trace-Data Read with Sync Message
- 12.13 Data Acquisition Messaging
  - 12.13.1 Data Acquisition ID Tag Field
  - 12.13.2 Data Acquisition Data Field
  - 12.13.3 Data Acquisition Trace Event
    - Figure 12-48. Data Acquisition Message Format
- 12.14 Watchpoint Trace Messaging
  - Figure 12-49. Watchpoint Message Format.
  - Table 12-37. Watchpoint Source Encoding
  - 12.14.1 Watchpoint Timing Diagram (2 MDO/1 MSEO configuration)
    - Figure 12-50. Watchpoint Message and Watchpoint Error Message
- 12.15 Nexus 3+ Read/Write Access to Memory-Mapped Resources
  - 12.15.1 Single Write Access
  - 12.15.2 Block Write Access
  - 12.15.3 Single Read Access
  - 12.15.4 Block Read Access
  - 12.15.5 Error Handling
    - Figure 12-51. Error Message Format
- 12.16 Nexus 3+ Pin Interface
  - 12.16.1 Pins Implemented
  - 12.16.2 Pin Protocol
- 12.17 Rules for Output Messages
- 12.18 Auxiliary Port Arbitration
  - Table 12-42. MDO Request Encodings
- 12.19 Examples
  - Table 12-43. Indirect Branch Message Example (2 MDO/1 MSEO)
  - Table 12-44. Indirect Branch Message Example (8 MDO/2 MSEO)
  - Table 12-45. Direct Branch Message Example (2 MDO / 1 MSEO)
  - Table 12-46. Direct Branch Message Example (8 MDO / 2 MSEO)
  - Table 12-47. Data Write Message Example (8 MDO / 1 MSEO)
  - Table 12-48. Data Write Message Example (8 MDO / 2 MSEO)
- 12.20 Electrical Characteristics
- 12.21 IEEE 1149.1 (JTAG) RD/WR Sequences
  - 12.21.1 JTAG Sequence for Accessing Internal Nexus Registers
    - Table 12-49. Accessing Internal Nexus 3+ Registers through JTAG/OnCE
  - 12.21.2 JTAG Sequence for Read Access of Memory-Mapped Resources
    - Table 12-50. Accessing Memory-Mapped Resources (Reads)
  - 12.21.3 JTAG Sequence for Write Access of Memory-Mapped Resources
    - Table 12-51. Accessing Memory-Mapped Resources (Writes)
Chapter 13 External Core Complex Interfaces
- 13.1 Overview
- 13.2 Signal Index
  - Figure 13-1. e200 Signal Groups
  - Table 13-1. Interface Signal Definitions
- 13.3 Signal Descriptions
- 13.4 Timing Diagrams
Appendix A Register Summary
- Figure A-1. e200z446n3 Supervisor Mode Programmer’s Model SPRs
- Figure A-2. e200z4463 User Mode Programmer’s Model SPRs
- Figure A-3. Machine State Register (MSR)
- Figure A-4. Processor ID Register (PIR)
- Figure A-5. Processor Version Register (PVR)
- Figure A-6. System Version Register (SVR)
- Figure A-7. Integer Exception Register (XER)
- Figure A-8. Exception Syndrome Register (ESR)
- Figure A-9. Machine Check Syndrome Register (MCSR)
- Figure A-10. Timer Control Register (TCR)
- Figure A-11. Timer Status Register (TSR)
- Figure A-12. Hardware Implementation Dependent Register 0 (HID0)
- Figure A-13. Hardware Implementation Dependent Register 1 (HID1)
- Figure A-14. Branch Unit Control and Status Register (BUCSR)
- Figure A-15. e200 Interrupt Vector Offset Register (IVOR)
- Figure A-16. DBCNT Register
- Figure A-17. DBCR0 Register
- Figure A-18. DBCR1 Register
- Figure A-19. DBCR2 Register
- Figure A-20. DBCR3 Register
- Figure A-21. DBCR4 Register
- Figure A-22. DBCR5 Register
- Figure A-23. DBCR6 Register
- Figure A-24. DBSR Register
- Figure A-25. DBERC0 Register
- Figure A-26. OnCE Status Register
- Figure A-27. OnCE Command Register
- Figure A-28. OnCE Control Register
- Figure A-29. CPU Scan Chain Register (CPUSCR)
- Figure A-30. Control State Register (CTL)
- Figure A-31. SPE Status and Control Register (SPEFSCR)
- Figure A-32. L1 Cache Control and Status Register 0 (L1CSR0)
- Figure A-33. L1 Cache Control and Status Register 1 (L1CSR1)
- Figure A-34. L1 Cache Configuration Register 0 (L1CFG0)
- Figure A-35. L1 Cache Configuration Register 1 (L1CFG1)
- Figure A-36. L1 Flush/Invalidate Register (L1FINV1)
- Figure A-37. MMU Configuration Register (MMUCFG)
- Figure A-38. TLB Configuration Register (TLB0CFG, TLB1CFG)
- Figure A-39. MMU Control and Status Register 0 (MMUCSR0)
- Figure A-40. MMU Assist Registers Summary
- Figure A-41. Parallel Signature Control Register (PSCR)
- Figure A-42. Parallel Signature Status Register (PSSR)
- Figure A-43. Parallel Signature High Register (PSHR)
- Figure A-44. Parallel Signature Low Register (PSLR)
- Figure A-45. Parallel Signature Counter Register (PSCTR)
- Figure A-46. Parallel Signature Update High Register (PSUHR)
- Figure A-47. Parallel Signature Update Low Register (PSULR)
Appendix B Revision History

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