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Arm® Compiler
Version 6.10

Errors and Warnings Reference Guide

Arm® Compiler

Arm® Compiler
Errors and Warnings Reference Guide
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.
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Confidentiality Change

14 March 2014

Non-Confidential Arm Compiler v6.00 Release

15 December 2014 Non-Confidential Arm Compiler v6.01 Release

30 June 2015

18 November 2015 Non-Confidential Arm Compiler v6.3 Release

24 February 2016

Non-Confidential Arm Compiler v6.4 Release

29 June 2016

Non-Confidential Arm Compiler v6.5 Release

04 November 2016 Non-Confidential Arm Compiler v6.6 Release

Non-Confidential Arm Compiler v6.02 Release

0607-00 05 April 2017

Non-Confidential Arm Compiler v6.7 Release. Document numbering scheme has
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0608-00 30 July 2017

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100074_0610_00_en

Contents
Arm® Compiler Errors and Warnings Reference
Guide

Preface
About this book ...................................................... ...................................................... 6

Chapter 1

Licensing Errors and Warnings
1.1

Chapter 2

Assembler Errors and Warnings
2.1

Chapter 3

List of the armar error and warning messages ........................................................ 5-92

Other Errors and Warnings
6.1
6.2

100074_0610_00_en

List of the fromelf error and warning messages ........................... ........................... 4-89

Librarian Errors and Warnings
5.1

Chapter 6

Suppressing armlink error and warning messages ........................ ........................ 3-44
List of the armlink error and warning messages ...................................................... 3-45

ELF Image Converter Errors and Warnings
4.1

Chapter 5

List of the armasm error and warning messages .......................... .......................... 2-13

Linker Errors and Warnings
3.1
3.2

Chapter 4

List of the licensing error and warning messages .......................... .......................... 1-9

Internal faults and other unexpected failures ............................. ............................. 6-94
List of other error and warning messages ............................... ............................... 6-95

Preface

This preface introduces the Arm® Compiler Errors and Warnings Reference Guide.
It contains the following:
• About this book on page 6.

100074_0610_00_en

Preface
About this book

About this book
The Arm® Compiler Errors and Warnings Reference Guide provides lists of the errors and warnings that
each of the compilation tools can generate. It does not include errors and warnings produced by
armclang.
Using this book
This book is organized into the following chapters:
Chapter 1 Licensing Errors and Warnings
Describes license-related error and warning messages that might be displayed by the assembler,
the linker, or the ELF image converter.
Chapter 2 Assembler Errors and Warnings
Describes the error and warning messages for the assembler, armasm.
Chapter 3 Linker Errors and Warnings
Describes the error and warning messages for the linker, armlink.
Chapter 4 ELF Image Converter Errors and Warnings
Describes the error and warning messages for the ELF image converter, fromelf.
Chapter 5 Librarian Errors and Warnings
Describes the error and warning messages for the Arm librarian, armar.
Chapter 6 Other Errors and Warnings
Describes error and warning messages that might be displayed by any of the tools.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
See the Arm® Glossary for more information.
Typographic conventions
italic
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instead of the full command or option name.
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monospace bold

Denotes language keywords when used outside example code.

100074_0610_00_en

Preface
About this book

Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, , , ,
SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in the
Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
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100074_0610_00_en

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Technical Support.
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Chapter 1
Licensing Errors and Warnings

Describes license-related error and warning messages that might be displayed by the assembler, the
linker, or the ELF image converter.
It contains the following section:
• 1.1 List of the licensing error and warning messages on page 1-9.

100074_0610_00_en

1-8

1 Licensing Errors and Warnings
1.1 List of the licensing error and warning messages

1.1

List of the licensing error and warning messages
A list of the error and warning messages that are caused by license-related issues.
The license error codes have three components; a prefix letter, an error number, and a suffix letter:
LNNNND

The prefix letter L indicates the tool that generated the error:
•
•
•

For the assembler, armasm, the error code starts with A.
For the linker, armlink, the error code starts with L.
For the ELF image converter, fromelf, the error code starts with Q.

The error numbers, NNNN, are identical for each tool.
The suffix letter, D, indicates the severity of the error:
• W means warning.
• E means error.
• F means fatal.
Note
For the compiler, armclang, error messages are still generated, but with no error code.
[A9503E|L9503E|Q9503E]: Keys for back-end could not be found in product
definition.
[A9506E|L9506E|Q9506E]: Message received by back-end is not valid.
[A9507E|L9507E|Q9507E]: back-end returned status= with invalid
version number ().
[A9511E|L9511E|Q9511E]: Unable to determine the current toolkit. Ensure that
ARM_TOOL_VARIANT is set correctly.

[A9515E|L9515E|Q9515E]: There is at least one feature CheckedOut for module
. Unregister is not allowed until you CheckedIn all the features.
[A9517E|L9517E|Q9517E]: Parsing error: (:).
[A9518W|L9518W|Q9518W]: Parsing warning: (:).
[A9519E|L9519E|Q9519E]: Your installation appears to be corrupt.
This may be subsumed into a common code for these errors, where the problem is that there is
something wrong with one or more of the mapping files.
[A9520E|L9520E|Q9520E]: Product definition string is empty. Set command will be
ignored.
[A9521E|L9521E|Q9521E]: File I/O error when determining the current toolkit. Ensure
that ARM_TOOL_VARIANT is set correctly, and you have read permissions for the
complete toolchain installation.
[A9526W|L9526W|Q9526W]: Failed to write to license cache file . Error
: .

[A9527W|L9527W|Q9527W]: Failed to calculate license cache file contents .
[A9528W|L9528W|Q9528W]: Failed to close license cache file . Error
: .
[A9529W|L9529W|Q9529W]: Failed to move or copy license cache file from
to . Error : .

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1-9

1 Licensing Errors and Warnings
1.1 List of the licensing error and warning messages

[A9530W|L9530W|Q9530W]: Failed to remove license cache file . Error
: .
[A9531W|L9531W|Q9531W]: Failed to read license cache file . Error
: .
[A9533W|L9533W|Q9533W]: License cache file invalid .
[A9534E|L9534E|Q9534E]: Failed to create hash of cache file.
[A9535F|L9535F|Q9535F]: Dynamic library: error while finding address of
function in library .
[A9536F|L9536F|Q9536F]: Dynamic library: error while loading library .
[A9539F|L9539F|Q9539F]: Dynamic library: failed to create checking module in library
.
[A9540F|L9540F|Q9540F]: Could not call DoCommand of external library, as the pointer to
it is NULL.

[A9542F|L9542F|Q9542F]: Could not allocate memory for encryption key.
[A9544E|L9544E|Q9544E]: Cannot check in feature with version
because it has not been checked out.
[A9545E|L9545E|Q9545E]: Info key could not be found in product definition
.

[A9546E|L9546E|Q9546E]: Your license has expired (expiry date: ).
[A9547E|L9547E|Q9547E]: No license checking back-end registered with id for
feature .
[A9549E|L9549E|Q9549E]: The feature is not available with your current
toolkit and license. Ensure that ARM_TOOL_VARIANT is set correctly for your toolkit.

[A9550E|L9550E|Q9550E]: The feature is not available with your current
toolkit and license. Ensure that ARM_TOOL_VARIANT is set correctly for your toolkit.
[A9552E|L9552E|Q9552E]: The feature is not available with your current
toolkit and license. Ensure that ARM_TOOL_VARIANT is set correctly for your toolkit.
[A9554E|L9554E|Q9554E]: Invalid data returned from back-end for feature
.

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1-10

1 Licensing Errors and Warnings
1.1 List of the licensing error and warning messages

[A9555E|L9555E|Q9555E]: Unable to checkout a license.
See the following table for more specific replacements per Flex error code:
Flex error
number

Message

-1

Unable to check out a license. The license file could not be found. Check that
ARMLMD_LICENSE_FILE is set to the correct path.

-4

Maximum number of license seats reached.

-5

The provided license does not enable these tools.

-9

This host does not match the host ID in the license.

-10

The license has expired.

-14

Unable to resolve the license server’s IP address. Check that ARMLMD_LICENSE_FILE
is set correctly.

-15

Unable to connect to the license server. Check that ARMLMD_LICENSE_FILE is set
correctly and the license server is available.

-30

Cannot read license file.

-34

System date/time is not the same as the license server.

-88

The system clock has been set back.

-96

Unable to connect to the license server. Check that ARMLMD_LICENSE_FILE is set
correctly and the license server is available.

-97

Unable to connect to the license server. Check that ARMLMD_LICENSE_FILE is set
correctly and the license server is available.

[A9558E|L9558E|Q9558E]: System clock tampering detected. License checkout will fail.
[A9559E|L9559E|Q9559E]: License information retrieval for feature with
version was cancelled because no back-end is associated with it.
[A9561E|L9561E|Q9561E]: No generation date specified, but relative expiry dates
present.
[A9580E|L9580E|Q9580E]: is not available with your current toolkit and
license. Ensure that ARM_TOOL_VARIANT is set correctly for your toolkit.

100074_0610_00_en

1-11

Chapter 2
Assembler Errors and Warnings

Describes the error and warning messages for the assembler, armasm.
It contains the following section:
• 2.1 List of the armasm error and warning messages on page 2-13.

100074_0610_00_en

2-12

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

2.1

List of the armasm error and warning messages
A list of the error and warning messages that armasm produces.
Note
License-related error messages can be found in the 1.1 List of the licensing error and warning messages
on page 1-9 section.
A1017E: :INDEX: cannot be used on a pc-relative expression

The :INDEX: expression operator has been applied to a PC-relative expression, most likely a
program label. :INDEX: returns the offset from the base register in a register-relative expression.
If you require the offset of a label called within an area called , use
- .

See the following in the armasm User Guide:
Unary operators.
A1020E: Bad predefine:

The operand to the --predefine or --pd command-line option was not recognized. The
directive must be enclosed in quotes if it contains spaces, for example on Windows:
--predefine "versionnum SETA 5"

If the SETS directive is used, the argument to the directive must also be enclosed in quotes,
which might require escaping, depending on the operating system and shell. For example:
--predefine "versionstr SETS \"5A\""

A1021U: No input file

No input file was specified on the command line. This might be because there was no
terminating quote on a quoted argument.
A1023E: File "" could not be opened:
A1024E: File "" could not all be loaded:
A1042E: Unrecognized APCS qualifier ''

There is an error in the argument given to the --apcs command line option. Check the spelling
of .
A1051E: Cannot open --depend file '':
A1055E: Cannot open --errors file '':
A1056E: Target cpu '' not recognized

The name given in the --cpu command line option is not a recognized processor name. Check
the spelling of the argument.
Use --cpu=list to list the supported processors and architectures.
A1067E: Output file specified as '', but it has already been specified as
''

More than one output file, -o filename, has been specified on the command line. Misspelling a
command line option can cause this.

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2-13

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1071E: Cannot open listing file '':
The file given in the --list command-line option could not be opened. This could

be for any of the following reasons:
• The given name is not valid.
• There is no space.
• A read-only file with the same name already exists.
• The file is in use by another process.
Check you have specified the correct path for the file.
A1072E: The specified listing file '' must not be a .s or .o file

The filename argument to the --list command line option has an extension that indicates it is a
source or object file. This might be because the filename argument was accidentally omitted
from the command line. Check that the correct argument is given to the --list command line
option.
A1073E: The specified output file '' must not be a source file

The object file specified on the command line has a filename extension that indicates it is a
source file. This might be because the object filename was accidentally omitted from the
command line.
A1074E: The specified depend file '' must not be a source file

The filename argument to the --depend command line option has an extension that indicates it
is a source (.s) file. This might be because the filename argument was accidentally omitted
from the command line. Check that the correct arguments are given.
A1075E: The specified errors file '' must not be a source file

The filename argument to the --errors command line option has an extension that indicates it
is a source (.s) file. This might be because the filename argument was accidentally omitted
from the command line. Check that the correct arguments are given.
A1085W: Forced user-mode LDM/STM must not be followed by use of banked R8-R14

The Arm architecture does not permit you to access banked registers in the instruction
immediately following a User registers LDM or STM. Adding a NOP immediately after the LDM or
STM is one way to avoid this.
For example:
stmib sp, {r0-r14}^ ; Return a pointer to the frame in a1.
mov r0, sp

change to:
stmib sp, {r0-r14}^ ; Return a pointer to the frame in a1.
nop
mov r0, sp

A1088W: Faking declaration of area AREA |$$$$$$$|

This is reported when no AREA directive is specified. See also message number A1105E.
A1099E: Structure stack overflow max stack size
A1100E: Structure stack underflow
A1105E: Area directive missing

This is reported when no AREA directive is specified. See also message number A1088W.
A1106E:
A1107E:
A1108E:
A1109E:

100074_0610_00_en

Missing comma
Bad symbol type, expect label
Multiply defined symbol ''
Bad expression type

2-14

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1110E: Expected constant expression

A constant expression was expected after, for example, SETA.
See the following in the armasm User Guide:
Numeric expressions.
A1111E: Expected constant or address expression
A1112E: Expected address expression
A1113E: Expected string expression

A string expression was expected after, for example, SETS.
See the following in the armasm User Guide:
String expressions.
A1114E:
A1116E:
A1117E:
A1118E:
A1119E:

Expected register relative expression
String operands can only be specified for DCB
Register symbol '' already defined
No current macro expansion
MEND not allowed within conditionals
MEND means END of Macro (not the English word mend).

See the following in the armasm User Guide:
About macros.
A1120E:
A1121E:
A1122E:
A1123E:
A1125E:
A1126E:
A1127E:
A1128E:
A1129E:
A1130E:
A1131E:
A1132E:
A1133E:
A1134E:
(symbol
A1135E:

Bad global name
Global name '' already exists
Locals not allowed outside macros
Bad local name
Unknown or wrong type of global/local symbol ''
Bad alignment boundary, must be a multiple of 2
Bad IMPORT/EXTERN name
Common name '' already exists
Imported name '' already exists
Bad exported name
Bad symbol type for exported symbol ''
REQUIRE directive not supported for format output
Bad required symbol name
Bad required symbol type, expect (symbol is either external or label) and
is relocatable and absolute)
Area name missing

AREA names starting with any non-alphabetic character must be enclosed in bars, for example
change:
AREA 1_DataArea, CODE, READONLY

to:
AREA |1_DataArea|, CODE, READONLY

A1136E: Entry address already set

100074_0610_00_en

2-15

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1137E: Unexpected characters at end of line

This is given when extra characters that are not part of an instruction are found on an instruction
line.
For example:
ADD r0, r0, r1 comment

You could change this to:
ADD r0, r0, r1 ; comment

A1138E:
A1139E:
A1140E:
A1141E:
A1142E:

String "" too short for operation, length must be >
String overflow, string exceeds characters
Bad operand type
Relocated expressions may only be added or subtracted
Subtractive relocations not supported for format output

This can occur when subtracting symbols that are in different areas, for example:
IMPORT sym1
IMPORT sym2
DCD (sym2 - sym1)

A1143E:
A1144E:
A1145E:
A1146E:
A1147E:
A1148E:
A1150E:

COMMON directive not supported for %s format output
DCDO directive not supported for %s format output
Undefined exported symbol ''
Unable to open output file :
Bad shift name
Unknown shift name , expected one of LSL, LSR, ASR, ROR, RRX
Bad symbol, not defined or external

This typically occurs in the following cases:
• When the current file requires an INCLUDE of another file to define some symbols, for
example:
"init.s", line 2: Error: A1150E: Bad symbol
2 00000000 DCD EBI_CSR_0

In this case, the solution is to include the required definitions file. For example:
INCLUDE targets/eb40.inc

•

When the current file requires IMPORT for some symbols, for example:
"init.s", line 4: Error: A1150E: Bad symbol
4 00000000 LDR r0, =||Image$$RAM$$ZI$$Limit||

In this case, the solution is to import the required symbol, for example:
IMPORT ||Image$$RAM$$ZI$$Limit||

A1151E: Bad register name symbol

Example:
MCR p14, 3, R0, Cr1, Cr2

The coprocessor registers CR must be labeled as a lowercase c for the code to build. The register
can be r or R:
MCR p14, 3, r0, c1, c2

or
MCR p14, 3, R0, c1, c2

A1152E: Unexpected operator

100074_0610_00_en

2-16

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1153E:
A1154E:
A1155E:
A1156E:
A1157E:
A1158E:

Undefined symbol
Unexpected operand, operator expected
Unexpected unary operator equal to or equivalent to
Missing open bracket
Syntax error following directive
Illegal line start, should be blank

Some directives, for example, ENTRY, IMPORT, EXPORT, and GET must be on a line without a label
at the start of the line. This error is given if a label is present.
A1159E: Label missing from line start

Some directives, for example, FUNCTION or SETS, require a label at the start of the line, for
example:
my_func FUNCTION

or
label SETS

This error is given if the label is missing.
A1160E: Bad local label number

A numeric local label is a number in the range 0-99, optionally followed by a name.
See the following in the armasm User Guide:
Numeric local labels.
A1161E: Syntax error following local label definition
A1162E: Incorrect routine name ''
A1163E: Unknown opcode , expecting opcode or Macro

The most common reasons for this are:
• Forgetting to put white space in the left hand margin, before the instruction. For example,
change the following:
MOV PC,LR

to:
MOV PC,LR

•

Use of a hardware floating point instruction without using the --fpu switch. For example:
FMXR FPEXC, r1 ;

•

must be assembled with armasm --fpu=vfp
Mis-typing the opcode:
ADDD

instead of:
ADD

A1164E: Opcode not supported on selected processor

The processor selected on the armasm command line does not support this instruction.
See the following:
Arm® Architecture Reference Manual.
A1165E: Too many actual parameters, expecting parameters
A1166E: Syntax error following label
A1167E: Invalid line start
100074_0610_00_en

2-17

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1168E: Translate not allowed in pre-indexed form
A1169E: Missing close square bracket
A1170E: Immediate 0x out of range for this operation, must be below (0x)

This error is given when a DCB, DCW or DCWU directive is used with an immediate that is too large.
See the following in the armasm User Guide:
• DCB.
• DCW and DCWU.
A1171E: Missing close bracket
A1172E: Bad rotator , must be even and between 0 and 30
A1173E: ADR/L cannot be used on external symbols

The ADR and ADRL pseudo-instructions can only be used with labels within the same code
area. To load an out-of-area address into a register, use LDR instead.
A1174E: Data transfer offset 0x out of range. Permitted values are 0x to
0x
A1175E: Bad register range
A1176E: Branch offset 0x out of range. Permitted values are 0x to 0x

Branches are PC-relative, and have a limited range. If you are using numeric local labels, you
can use the ROUT directive to limit their scope. This helps to avoid referring to the wrong label
by accident.
See the following in the armasm User Guide:
Numeric local labels.
A1179E:
A1180E:
A1181E:
A1182E:
A1183E:
A1184E:
A1185E:
A1186E:

Bad hexadecimal number
Missing close quote
Bad operator
Bad based number
Numeric overflow
Externals not valid in expressions
Symbol missing
Code generated in data area

An instruction has been assembled into a data area. This can happen if you have omitted the
CODE attribute on the AREA directive.

See the following in the armasm User Guide:
AREA.
A1187E:
A1188E:
A1189E:
A1190E:
A1191E:
A1192E:
A1193E:
A1194E:
A1195W:
A1196E:

100074_0610_00_en

Error in macro parameters
Register value out of range. Permitted values are to
Missing '#'
Unexpected ''
Floating point register number out of range 0 to
Coprocessor register number out of range 0 to 15
Coprocessor number out of range 0 to 15
Bad floating-point number
Small floating point value converted to 0.0
Too late to ban floating point

2-18

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1198E: Unknown operand

This can occur when an operand is accidentally mistyped.
For example:
armasm --cpu=8-A.64 init.s -g -PD "ROM_RAM_REMAP SETL {FALS}"

must be:
armasm --cpu=8-A.64 init.s -g -PD "ROM_RAM_REMAP SETL {FALSE}"

See the following in the armasm User Guide:
Assembly time substitution of variables.
A1199E:
A1200E:
A1201E:
A1202E:

Coprocessor operation out of range 0 to
Structure mismatch expect While/Wend
Substituted line too long, maximum length
No pre-declaration of substituted symbol ''

See the following in the armasm User Guide:
Assembly time substitution of variables.
A1203E:
A1204E:
A1205E:
A1206E:

Illegal label parameter start in macro prototype
Bad macro parameter default value
Register occurs multiply in list
Registers should be listed in increasing register number order

This warning is given if registers in, for example, LDM or STM instructions are not specified in
increasing order and the --checkreglist option is used.
A1207E: Bad or unknown attribute

This error is given when an invalid attribute is given in the AREA directive. For example:
AREA test,CODE,READONLY,HALFWORD

HALFWORD is invalid, so remove it.

See the following in the armasm User Guide:
AREA.
A1209E:
A1210E:
A1211E:
A1212E:
A1213E:
A1214E:
A1215E:
A1216E:
A1217E:
A1219E:

ADRL cannot be used with PC as destination
Non-zero data within uninitialized area ''
Missing open square bracket
Division by zero
Attribute cannot be used with attribute
Too late to define symbol '' as register list
Bad register list symbol
Bad string escape sequence
Error writing to code file :
Bad APSR, CPSR or SPSR designator

For example:
MRS r0, PSR

It is necessary to specify which status register to use (CPSR or SPSR), such as, for example:
MRS r0, CPSR

A1220E: BLX must be unconditional
A1221E: Area attribute '' not supported for object file format
A1223E: Comdat Symbol '' is not defined
100074_0610_00_en

2-19

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1224E:
A1225E:
A1226E:
A1227E:
A1228E:
A1229E:
A1230E:
A1234E:
A1237E:
A1238E:
A1240E:
A1241E:
A1242E:
A1243E:
A1244E:
A1245E:
A1246E:
A1247E:

format does not allow PC-relative data transfers between areas
ASSOC attribute is not allowed in non-comdat areas
SELECTION attribute is not allowed in non-comdat areas
Comdat Associated area '' undefined at this point in the file
Comdat Associated area '' is not an area name
Missing COMDAT symbol
Missing '}' after COMDAT symbol
Undefined or Unexported Weak Alias for symbol ''
Invalid register or register combination for this operation
Immediate value must be word aligned when used in this operation
Immediate value cannot be used with this operation
Must have immediate value with this operation
Offset must be word aligned when used with this operation
Offset must be halfword aligned with this operation
Missing '!'
B or BL from Thumb code to ARM code
B or BL from ARM code to Thumb code
BLX from ARM code to ARM code, use BL

This occurs when there is a BLX label branch from A32 code to A32 code within this
assembler file. This is not permitted because BLX label always results in a change of
instruction set state. The usual solution is to use BL instead.
A1248E: BLX from Thumb code to Thumb code, use BL

This occurs when there is a BLX label branch from T32 code to T32 code within this assembler
file. This is not permitted because BLX label always results in a change of instruction set state.
The usual solution is to use BL instead.
A1249E:
A1250E:
A1253E:

A1254E:

Post indexed addressing mode not available
Pre indexed addressing mode not available for this instruction, use [Rn, Rm]
Thumb branch to external symbol cannot be relocated: not representable in
Halfword literal values not supported

In the following example, change the LDRH into LDR, which is the standard way of loading
constants into registers:
LDRH R3, =constant

A1256E:
A1259E:
SPSR
A1260E:
A1261E:

DATA directive can only be used in CODE areas
Invalid PSR field specifier, syntax is _ where is either CPSR or
PSR field '' specified more than once
MRS cannot select fields, use APSR, CPSR or SPSR directly

This is caused by an attempt to use fields for CPSR or SPSR with an MRS instruction. For
example:
MRS r0, CPSR_c

A1262U:
A1265U:
A1267E:
A1268E:
A1269U:
A1270E:
A1271E:
A1272E:
A1273E:
A1274W:
100074_0610_00_en

Expression storage allocator failed
Structure mismatch: IF or WHILE unmatched at end of INCLUDE file
Bad GET or INCLUDE for file
Unmatched conditional or macro
unexpected GET on structure stack
File "" not found
Line too long, maximum line length is
End of input file
'\\' should not be used to split strings
'\\' at end of comment
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-20

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1283E: Literal pool too distant, use LTORG to assemble it within 1KB

For T32 code, a literal pool must be within 1KB of an LDR instruction that is trying to access it.
See also messages A1284E and A1471W.
A1284E: Literal pool too distant, use LTORG to assemble it within 4KB

For A32 code, a literal pool must be within 4KB of an LDR instruction that is trying to access it.
To solve this, add an LTORG directive into your assembly source code at a convenient place.
See the following in the armasm User Guide:
• Load addresses to a register using LDR Rd, =label.
• LTORG.
A1285E:
A1286E:
A1287E:
A1288E:
A1289E:
A1290E:
A1291E:
A1310W:
A1311U:
A1312E:
A1313W:

Bad macro name
Macro already exists
Illegal parameter start in macro prototype
Illegal parameter in macro prototype
Invalid parameter separator in macro prototype
Macro definition too big, maximum length
Macro definitions cannot be nested
Symbol attribute not recognized
macro definition attempted within expansion
Assertion failed
Missing END directive at end of file

The assembler requires an END directive to know when the code in the file terminates. You can
add comments or other such information in free format after this directive.
A1314W: Reserved instruction (using NV condition)
A1315E: NV condition not supported on targeted CPU
A1316E: Shifted register operand to MSR has undefined effect
A1319E: Undefined effect (using PC as Rs)
A1320E: Undefined effect (using PC as Rn or Rm in register specified shift)
A1321E: Undefined effect (using PC as offset register)
A1322E: Unaligned transfer of PC, destination address must be 4 byte aligned,
otherwise result is UNPREDICTABLE

This error is reported when you try to use an LDR instruction to load the PC from a non wordaligned address. For example:
AREA Example, CODE
LDR pc, [pc, #6] ; Error – offset must be a multiple of 4
END

This code gives an UNPREDICTABLE result.
A1323E: Reserved instruction (Rm = Rn with post-indexing)
A1324E: Undefined effect (PC + writeback)
A1327E: Non portable instruction (LDM with writeback and base in register list, final
value of base unpredictable)

In the LDM instruction, if the base register is specified in , and base register
writeback is specified, the final value of is UNKNOWN.
A1328E: Non portable instruction (STM with writeback and base not first in register
list, stored value of base unpredictable)
In the STM instruction, if is specified in and base register writeback is

specified:
• If is the lowest-numbered register specified in , the original value of
is stored.
• Otherwise, the stored value of is UNKNOWN.

100074_0610_00_en

2-21

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1329E: Unpredictable instruction (forced user mode transfer with write-back to base)

This is caused by an instruction such as PUSH {r0}^ where the ^ indicates access to user
registers. Writeback to the base register is not available with this instruction. Instead, the base
register must be updated separately. For example:
SUB sp, sp,#4
STMID sp, {r0}^

Another example is replacing STMFD R0!, {r13, r14}^ with:
SUB r0, r0,#8
STM r0, {r13, r14}^

See also message A1085W.
A1331E: Unpredictable instruction (PC as source or destination)
A1332E: Unpredictable effect (PC-relative SWP)
A1334E: Undefined effect (use of PC/PSR)
A1335E: Useless instruction (PC cannot be written back)
A1337E: Useless instruction (PC is destination)
A1338E: Dubious instruction (PC used as an operand)
A1339E: Unpredictable if RdLo and RdHi are the same register
A1341E: Branch to unaligned destination, expect destination to be byte aligned
A1342W: of symbol in another AREA will cause link-time failure if symbol is
not close enough to this instruction
A1344I: host error: out of memory
A1355U: A Label was found which was in no AREA

This can occur if no white space precedes an assembler directive. Assembler directives must be
indented. For example use:
IF :DEF: FOO
; code
ENDIF

instead of:
IF :DEF: FOO
; code
ENDIF

Symbols beginning in the first column are assumed to be labels.
A1356E: Instruction not supported on targeted CPU

This occurs if you try to use an instruction that is not supported by the selected architecture or
processor.
For example:
SMULBB r0,r0,r1 ;

This can be assembled with:
armasm --cpu 5TE

See the following:
Arm® Architecture Reference Manual.
A1406E:
A1407E:
A1408E:
A1409W:
A1411E:
A1412E:
100074_0610_00_en

Bad decimal number
Overlarge floating point value
Overlarge (single precision) floating point value
Small (single precision) floating value converted to 0.0
Closing '>' missing from vector specifier
Bad vector length, should be between and
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-22

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1413E: Bad vector stride, should be between and
A1414E: Vector wraps round over itself, length * stride should not be greater than

A1415E: VFPASSERT must be followed by 'VECTOR' or 'SCALAR'
A1416E: Vector length does not match current vector length
A1417E: Vector stride does not match current vector stride
A1418E: Register has incorrect type '' for instruction, expect floating point/
double register type
A1419E: Scalar operand not in a scalar bank
A1420E: Lengths of vector operands are different
A1421E: Strides of vector operands are different
A1422E: This combination of vector and scalar operands is not allowed
A1423E: This operation is not vectorizable
A1424E: Vector specifiers not allowed in operands to this instruction
A1425E: Destination vector must not be in a scalar bank
A1426E: Source vector must not be in a scalar bank
A1427E: Operands have a partial overlap
A1428E: Register list contains registers of varying types
A1429E: Expected register list

The assembler reports this when FRAME SAVE and FRAME RESTORE directives are not given
register lists.
See the following in the armasm User Guide:
• FRAME RESTORE.
• FRAME SAVE.
A1430E: Unknown frame directive
A1431E: Frame directives are not accepted outside of PROCs/FUNCTIONs

See the following in the armasm User Guide:
Frame directives.
A1432E: Floating-point register type not consistent with selected floating-point
architecture
A1433E: Only the writeback form of this instruction exists

The addressing mode specified for the instruction did not include the writeback specifier (that is,
a '!' after the base register), but the instruction set only supports the writeback form of the
instruction. Either use the writeback form, or replace with instructions that have the required
behavior.
A1434E: Architecture attributes '' and '' conflict
A1435E: {PCSTOREOFFSET} is not defined when assembling for an architecture
{PCSTOREOFFSET} is only defined when assembling for a processor, not for an architecture.
A1437E: {ARCHITECTURE} is undefined
{ARCHITECTURE} is only defined when assembling for an architecture, not for a processor.

100074_0610_00_en

2-23

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1446E: Bad or unknown attribute ''. Use --apcs /interwork instead

For example:
AREA test1, CODE, READONLY
AREA test, CODE, READONLY, INTERWORK

This code might have originally been intended to work with the legacy Arm Software
Development Toolkit (SDT). The INTERWORK area attribute is obsolete. To eliminate the error, do
the following:
• Remove the ", INTERWORK" from the AREA line.
• Assemble with armasm --apcs /interwork foo.s instead.
A1447W: Missing END directive at end of file, but found a label named END

This is caused by the END directive not being indented.
A1448E: Deprecated form of PSR field specifier used (use _f)
A1449E: Deprecated form of PSR field specifier used (use _c)
A1450E: Deprecated form of PSR field specifier used (use _cxsf for future
compatibility)
armasm supports the full range of MRS and MSR instructions, in the following forms:
MRS(cond)
MRS(cond)
MSR(cond)
MSR(cond)
MSR(cond)
MSR(cond)

Rd, CPSR
Rd, SPSR
CPSR_fields,
SPSR_fields,
CPSR_fields,
SPSR_fields,

Rm
Rm
#immediate
#immediate

where fields can be any combination of cxsf.
Legacy versions of the assembler permitted other forms of the MSR instruction to modify the
control field and flags field:
•
•
•

cpsr or cpsr_all, control and flags field
cpsr_flg, flags field only
cpsr_ctl, control field only.

Similar control and flag settings apply for SPSR.
These forms are deprecated and must not be used. If your legacy code contains them, the
assembler reports:
Deprecated form of PSR field specifier used (use _cxsf)

To avoid the warning, in most cases you can modify your code to use _c, _f, _cf or _cxsf
instead.
See the following in the armasm User Guide:
• Conditional execution in A32 state.
• Conditional execution in T32 state.
• General-purpose registers in AArch32 state.
• Access to the inline barrel shifter in AArch32 state.
A1454E: FRAME STATE RESTORE directive without a corresponding FRAME STATE REMEMBER

See the following in the armasm User Guide:
• Frame directives.
• FRAME STATE REMEMBER.
• FRAME STATE RESTORE.

100074_0610_00_en

2-24

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1456W: INTERWORK area directive is obsolete. Continuing as if --apcs /inter selected

For example, the following code generates this warning:
AREA test, CODE, READONLY, INTERWORK

This code might have originally been intended to work with the legacy Arm Software
Development Toolkit (SDT). The INTERWORK area attribute is obsolete. To eliminate the
warning, do the following:
1. Remove the ", INTERWORK" from the AREA line.
2. Assemble with armasm --apcs /interwork foo.s instead.
See also message A1446E.
A1457E: Cannot mix INTERWORK and NOINTERWORK code areas in same file
INTERWORK and (default) NOINTERWORK code areas cannot be mixed in the same file. This code
might have originally been intended to work with the Arm Software Development Toolkit
(SDT). The INTERWORK AREA attribute is obsolete in the Arm Compiler toolchain.

For example:
AREA test1, CODE, READONLY
…
AREA test2, CODE, READONLY, INTERWORK

To eliminate the error, carry out the following steps:
1. Move the two AREAs into separate assembly files, for example, test1.s and test2.s.
2. Remove , INTERWORK from the AREA line in test2.s.
3. Assemble test1.s with armasm --apcs /nointerwork.
4. Assemble test2.s with armasm --apcs /interwork.
5. At link time, the linker adds any necessary interworking veneers.
See also message A1446E.
A1458E: DCFD or DCFDU not allowed when fpu is None
A1459E: Cannot B or BL to a register

This form of the instruction is not permitted. See the following for the permitted forms:
Arm® Architecture Reference Manual.
A1461E: Specified processor or architecture does not support Thumb instructions

It is likely that you are specifying an architecture or processor using the --cpu option and
incorporating T32 code in the AREA that is generating this error.
For example, in the following command line, code.s contains T32 code but the --arm_only
option forces only A32 code to be generated.
armasm --arm_only --cpu=7-A code.s
A1462E:
A1463E:
A1464W:
A1466W:

Specified memory attributes do not support this instruction
SPACE directive too big to fit in area, area size limit 2^32
ENDP/ENDFUNC without corresponding PROC/FUNC
Operator precedence means that expression would evaluate differently in C
armasm has always evaluated certain expressions in a different order to C. This warning might

help C programmers from being caught out when writing in assembly language.
To avoid the warning, do either of the following:
• Modify the code to make the evaluation order explicit, by adding brackets.
• Suppress the warning with the --unsafe switch.
See the following in the armasm User Guide:
Operator precedence.
100074_0610_00_en

2-25

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1467W: FRAME ADDRESS with negative offset is not recommended
A1468W: FRAME SAVE saving registers above the canonical frame address is not
recommended
A1469E: FRAME STATE REMEMBER directive without a corresponding FRAME STATE RESTORE

See the following in the armasm User Guide:
• Frame directives.
• FRAME STATE REMEMBER.
• FRAME STATE RESTORE.
A1471W: Directive may be in an executable position

This can occur with, for example, the LTORG directive (see messages A1283E and A1284E).
LTORG instructs the assembler to dump literal pool DCD data at this position.
To prevent this warning, the data must be placed where the processor cannot execute them as
instructions. A good place for an LTORG is immediately after an unconditional branch, or after
the return instruction at the end of a subroutine.
As a last resort, you could add a branch over the LTORG to avoid the data being executed. For
example:
B unique_label
LTORG
unique_label

A1475E: At least one register must be transferred, otherwise result is UNPREDICTABLE
A1476E: BX r15 at non word-aligned address is UNPREDICTABLE
A1477E: This register combination results in UNPREDICTABLE behavior

This error is generated when you are assembling an instruction that has UNPREDICTABLE results on
execution. You must rewrite your code to avoid this UNPREDICTABLE behavior. For example, the
following instructions all cause this error when assembling to T32, and the target architecture is
Armv6T2 or later:
ADD sp, r0, #100 ; error - UNPREDICTABLE use of SP
CMP pc, #1 ; error - UNPREDICTABLE use of PC
PUSH
{r0, pc} ; error - use of an UNPREDICTABLE register combination

100074_0610_00_en

2-26

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1479W: Requested alignment is greater than area alignment , which
has been increased

This is warning about an ALIGN directive that has a coarser alignment boundary than its
containing AREA. This is not permitted. To compensate, the assembler automatically increases
the alignment of the containing AREA for you. A simple test case that gives the warning is:
AREA test, CODE, ALIGN=3
ALIGN 16
mov pc, lr
END

In this example, the alignment of the AREA (ALIGN=3) is 2^3=8 byte boundary, but the mov
pc,lr instruction is on a 16-byte boundary, causing the error.
Note
The two alignment types are specified in different ways.
This warning can also occur when using AREA ... ALIGN=0 to align a code section on a byte
boundary. This is not possible. Code sections can only be aligned on:
•
•

a four-byte boundary for A32 code, so use "ALIGN=2"
a two-byte boundary for T32 code, so use "ALIGN=1".

See the following in the armasm User Guide:
• ALIGN.
• AREA.
A1480W:
A1481E:
A1482E:
A1484W:

Macro cannot have same name as a directive or instruction
Object file format does not support this area alignment
Shift option out of range, allowable values are from to
Obsolete shift name 'ASL', use LSL instead

The Arm architecture does not have an ASL shift operation. The AArch32 barrel shifter only has
the following shift types:
•
•
•
•

ROR.
ASR.
LSR.
LSL.

An arithmetic (that is, signed) shift left is the same as a logical shift left, because the sign bit
always gets shifted out.
If the name ASL is used, the assembler reports this warning and converts the ASL to LSL.
See the following in the armasm User Guide:
• --unsafe.
• ASR.
A1485E: LDM/STM instruction exceeds maximum register count allowed with
--split_ldm
A1486E: ADR/ADRL of a symbol in another AREA is not supported in ELF

The ADR and ADRL pseudo-instructions can only be used with labels within the same code
section. To load an out-of-area address into a register, use LDR instead.
A1487W: Obsolete instruction name 'ASL', use LSL instead

This warning is given when the ASL instruction is used in pre-UAL T32 code, that is, when you
assemble using the --16 command-line option, or you use the CODE16 directive. See the
corresponding A32 ASL message A1484W.

100074_0610_00_en

2-27

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1488W: PROC/FUNC at line in '' without matching ENDP/ENDFUNC
A1489E: is undefined
A1490E: is undefined

{CPU} is only defined by assembling for a processor and not an architecture.
A1491W: Internal error: Found relocation at offset with incorrect alignment

This might indicate an assembler fault. Contact your supplier.
A1492E:
0x
A1493E:
A1495W:

Immediate 0x out of range for this operation. Permitted values are
to 0x
REQUIRE must be in an AREA
Target of branch is a data address
armasm determines the type of a symbol and detects branches to data. To suppress this warning,
specify --diag-suppress 1495.

A1496W: Absolute relocation of ROPI address with respect to symbol '' at
offset may cause link failure

For example, when assembling the following code with --apcs /ropi, this warning is given.
This is because it generates an absolute relocation (R_ARM_ABS32) to a PI code symbol.
AREA code, CODE
codeaddr DCD codeaddr
END

A1497W: Absolute relocation of RWPI address with respect to symbol '' at
offset may cause link failure

For example, when assembling the following code with --apcs /rwpi, this warning is given.
This is because it generates an absolute relocation (R_ARM_ABS32) to a PI data symbol.
AREA data, DATA
dataaddr DCD dataaddr
END

A1498E: Unexpected characters following Thumb instruction

For example, the following instruction is valid in both UAL and pre-UAL code:
ADD r0, r0, r1

However, the following instruction is invalid in pre-UAL T32 code. The unexpected characters
are , ASR #1.
ADD r0, r0, r1, ASR #1

A1499E: Register pair is not a valid contiguous pair
A1500E: Unexpected characters when expecting ''
A1501E: Shift option out of range, allowable values are 0, 8, 16 or 24
A1502W: Register is a caller-save register, not valid for this operation
A1505E: Bad expression type, expect logical expression
A1506E: Accumulator should be in form accx where x ranges from 0 to
A1507E: Second parameter of register list must be greater than or equal to the first
A1508E: Structure mismatch expect Conditional
A1509E: Bad symbol type, expect label, or weak external symbol
A1510E: Immediate 0x cannot be represented by 0-255 and a rotation
A1511E: Immediate cannot be represented by combination of two data processing
instructions
A1512E: Immediate 0x out of range for this operation. Permitted values are
to
A1513E: Symbol not found or incompatible Symbol type for ''
A1514E: Bad global name ''

100074_0610_00_en

2-28

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1515E:
A1516E:
A1517E:
A1539E:
A1540E:
A1541E:
A1542E:
A1543W:
A1544E:
A1545U:
A1546W:

Bad local name ''
Bad symbol '', not defined or external
Unexpected operator equal to or equivalent to
Link Order dependency '' not an area
Cannot have a link order dependency on self
is not a valid condition code
Macro names and [parameter] conflict
Empty macro parameter default value
Invalid empty PSR field specifier, field must contain at least one of c,x,s,f
Too many sections for one file
Stack pointer update potentially breaks 8 byte stack alignment

The stack must be eight-byte aligned on an external boundary so pushing an odd number of
registers causes this warning. For example:
PUSH {r0}

This warning is suppressed by default. To enable it, use --diag_warning 1546.
See the following in the armasm User Guide:
--diag_warning=tag{, tag}.
A1547W: PRESERVE8 directive has automatically been set

Example:
PUSH {r0,r1}

This warning is given because you have not explicitly set the PRESERVE8 directive, but the
assembler has set it automatically. This warning is suppressed by default. To enable it, use
--diag_warning 1547.
See the following in the armasm User Guide:
• --diag_warning=tag{, tag}.
• REQUIRE8 and PRESERVE8.
A1548W: Code contains LDRD/STRD indexed/offset from SP but REQUIRE8 is not set

This warning is given when the REQUIRE8 directive is not set when required. For example:
PRESERVE8
STRD r0,[sp,#8]

See the following in the armasm User Guide:
REQUIRE8 and PRESERVE8.
A1549W: Setting of REQUIRE8 but not PRESERVE8 is unusual

Example:
PRESERVE8 {FALSE}
REQUIRE8
STRD r0,[sp,#8]

A1550U:
A1551E:
A1560E:
A1561E:
A1562E:

100074_0610_00_en

Input and output filenames are the same
Cannot add Comdef area to non-comdat group
Non-constant byte literal values not supported
MERGE and STRING sections must be data sections
Entry size for Merge section must be greater than 0

2-29

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1563W: Instruction stalls CPU for cycle(s)

The assembler can give information about possible interlocks in your code caused by the
pipeline of the processor chosen by the --cpu option. To do this, assemble with
armasm --diag_warning 1563.
Note
If the --cpu option specifies a multi-issue processor such as Cortex®‑A8, the interlock warnings
are unreliable.
See also warning A1746W.
A1572E:
A1573E:
A1574E:
A1575E:
A1576E:
A1577E:
A1578E:
A1581W:

Operator SB_OFFSET_11_0 only allowed on LDR/STR instructions
Operator SB_OFFSET_19_12 only allowed on Data Processing instructions
Expected one or more flag characters from ""
BLX with bit[0] equal to 1 is architecturally UNDEFINED
Bad coprocessor register name symbol
Bad coprocessor name symbol
Bad floating point register name symbol ''
Added bytes of padding at address

By default, the assembler warns when it adds padding bytes to the generated code. This occurs
whenever an instruction or directive is used at an address that requires a higher alignment, for
example, to ensure A32 instructions start on a four-byte boundary after some T32 instructions,
or where there is a DCB followed by a DCD.
For example:
AREA Test, CODE, READONLY
THUMB
ThumbCode
MOVS r0, #1
ADR r1, ARMProg
BX r1
; ALIGN ; <<< uncomment to avoid the first warning
ARM
ARMProg
ADD r0,r0,#1
BX LR
DCB 0xFF
DCD 0x1234
END

This code results in the following warnings:
A1581W: Added 2 bytes of padding at address 0x6
8 00000008 ARM
A1581W: Added 3 bytes of padding at address 0x11
13 00000014 DCD 0x1234

The warning can also occur when using ADR in T32-only code. The ADR T32 pseudo-instruction
can only load addresses that are word aligned, but a label within T32 code might not be word
aligned. Use ALIGN to ensure four-byte alignment of an address within T32 code.
See the following in the armasm User Guide:
• ADR (PC-relative).
• ADR (register-relative).
• ALIGN.
• DCB.
• DCD and DCDU.
A1582E:
A1583E:
A1584E:
A1585E:
A1586E:
100074_0610_00_en

Link Order area '' undefined
Group symbol '' undefined
Mode not allowed for this instruction
Bad operand type () for operator
Bad operand types (, ) for operator
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-30

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1587E: Too many registers in register list, maximum of
A1588E: Align only available on VLD and VST instructions
A1589E: Element index must remain constant across all registers
A1590E: Mix of subscript and non-subscript elements not allowed
A1593E: Bad Alignment, must match transfer size UIMM *
A1595E: Bad Alignment, must match *
, or 64 when is 4
A1596E: Invalid alignment for dt st combination
A1597E: Register increment of 2 not allowed when dt is 8
A1598E: Bad Register list length
A1599E: Out of range subscript, must be between 0 and
A1600E: Section type must be within range SHT_LOOS and SHT_HIUSER
A1601E: Immediate cannot be represented
A1603E: This instruction inside IT block has UNPREDICTABLE results
A1604W: Thumb Branch to destination without alignment to bytes
A1606E: Symbol attribute cannot be used with attribute
A1607E: Thumb-2 wide branch instruction used, but offset could fit in Thumb-1 narrow
branch instruction
A1608W: MOV pc, instruction used, but BX is preferred
A1609W: MOV ,pc instruction does not set bit zero, so does not create a return
address

This warning is caused when the current value of the PC is copied into a register while
executing in T32 state. An attempt to create a return address in this fashion fails because bit[0]
is not set. Attempting to branch with BX to this instruction causes a state change to A32.
To create a return address, you can use:
MOV r0, pc
ADDS r0, #1

You can then safely suppress this warning with:
--diag_suppress 1609

A1611E: Register list increment of 2 not allowed for this instruction
A1612E: addressing not allowed for
A1613E: Invalid register or register combination for this operation, ,
expected one of
A1614E: Scalar access not allowed when dt is 64
A1615E: Store of a single element or structure to all lanes is UNDEFINED
A1616E: Instruction, offset, immediate or register combination is not supported by
the current instruction set

This error can be caused by attempting to use an invalid combination of operands. For example,
in T32:
MOV r0, #1 ; /* Not permitted */
MOVS r0, #1 ; /* Ok */

See the following in the armasm User Guide:
A32 and T32 Instructions.
A1617E:
A1618E:
A1619E:
A1620E:
A1621E:
A1622E:
A1623E:
A1624W:
A1625W:
100074_0610_00_en

Specified width is not supported by the current instruction set
Specified instruction is not supported by the current instruction set
Specified condition is not consistent with previous IT
Error writing to file '':
CBZ or CBNZ from Thumb code to ARM code
Negative register offsets are not supported by the current instruction set
Offset not supported by the current instruction set
Branch from Thumb code to ARM code
Branch from ARM code to Thumb code
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-31

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1626W: BL from Thumb code to ARM code
A1627W: BL from ARM code to Thumb code

This occurs when there is a branch from A32 code to T32 code (or from T32 code to A32 code)
within this file. The usual solution is to move the T32 code into a separate assembler file. Then,
at link-time, the linker adds any necessary interworking veneers.
A1630E: Specified processor or architecture does not support ARM instructions

Arm M-profile processors, for example Cortex‑M3 and Cortex‑M1, implement only the T32
instruction set, not the A32 instruction set. It is likely that the assembly file contains some A32specific instructions and is being built for one of these processors.
A1631E:
A1632E:
A1633E:
A1634E:
A1635E:
A1636E:
A1637E:
A1638E:
A1639E:
A1640E:
A1641E:
A1642W:
A1643E:
values.
A1644E:
A1645W:

Only left shifts of 1, 2 and 3 are allowed on load/stores
Else forbidden in IT AL blocks
LDR rx,= pseudo instruction only allowed in load word form
LDRD/STRD has no register offset addressing mode in Thumb
CBZ/CBNZ can not be made conditional
Flag setting MLA is not supported in Thumb
Error reading line:
Writeback not allowed on register offset loads or stores in Thumb
Conditional DCI only allowed in Thumb mode
Offset must be a multiple of four
Forced user-mode LDM/STM not supported in Thumb
Relocated narrow branch is not recommended
Cannot determine whether instruction is working on single or double precision
Cannot use single precision registers with FLDMX/LSTMX
Substituted with
armasm can be configured to issue a warning in cases where it chooses to substitute an

instruction. For example:
• ADD negative_number is the same as SUB positive_number
• MOV negative_number is the same as MVN positive_number
• CMP negative_number is the same as CMN positive_number.
For the T32 instruction set, UNPREDICTABLE single register LDMs are transformed into LDRs.
This warning is suppressed by default, but can be enabled with --diag_warning 1645.
For example, when the following code is assembled with --diag_warning 1645:
AREA foo, CODE
ADD r0, #-1
MOV r0, #-1
CMP r0, #-1

the assembler reports:
Warning: A1645W: Substituted ADD with SUB
3 00000000 ADD r0, #-1
Warning: A1645W: Substituted MOV with MVN
4 00000004 MOV r0, #-1
Warning: A1645W: Substituted CMP with CMN
5 00000008 CMP r0, #-1

and the resulting code generated is:
foo
0x00000000: e2400001 ..@. SUB r0,r0,#1
0x00000004: e3e00000 .... MVN r0,#0
0x00000008: e3700001 ..p. CMN r0,#1

A1647E: Bad register name symbol, expected Integer register

An integer (core) register is expected at this point in the syntax.

100074_0610_00_en

2-32

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1648E: Bad register name symbol, expected Wireless MMX SIMD register
A1649E: Bad register name symbol, expected Wireless MMX Status/Control or General
Purpose register
A1650E: Bad register name symbol, expected any Wireless MMX register
A1651E: TANDC, TEXTRC and TORC instructions with destination register other than R15
is undefined
A1652W: FLDMX/FSTMX instructions are deprecated in ARMv6. Please use FLDMD/FSTMD
instructions to save and restore unknown precision values.
A1653E: Shift instruction using a status or control register is undefined
A1654E: Cannot access external symbols when loading/storing bytes or halfwords
A1655E: Instruction is UNPREDICTABLE if halfword/word/doubleword is unaligned
A1656E: Target must be at least word-aligned when used with this instruction
A1657E: Cannot load a byte/halfword literal using WLDRB/WLDRH =constant
A1658W: Support for is deprecated

An option passed to armasm is deprecated.
See the following in the armasm User Guide:
Assembler command-line options.
A1659E: Cannot B/BL/BLX between ARM/Thumb and Thumb-2EE
A1660E: Cannot specify scalar index on this register type
A1661E: Cannot specify alignment on this register
A1662E: Cannot specify a data type on this register type
A1663E: A data type has already been specified on this register
A1664E: Data type specifier not recognized
A1665E: Data type size must be one of 8, 16, 32 or 64
A1666E: Data type size for floating-point must be 32 or 64
A1667E: Data type size for polynomial must be 8 or 16
A1668E: Too many data types specified on instruction
A1669E: Data type specifier not allowed on this instruction
A1670E: Expected 64-bit doubleword register expression
A1671E: Expected 128-bit quadword register expression
A1672E: Expected either 64-bit or 128-bit register expression
A1673E: Both source data types must be same type and size
A1674E: Source operand 1 should have integer type and be double the size of source
operand 2
A1675E: Data types and sizes for destination must be same as source
A1676E: Destination type must be integer and be double the size of source
A1677E: Destination type must be same as source, but half the size
A1678E: Destination must be untyped and same size as source
A1679E: Destination type must be same as source, but double the size
A1680E: Destination must be unsigned and half the size of signed source
A1681E: Destination must be unsigned and have same size as signed source
A1682E: Destination must be un/signed and source floating, or destination floating
and source un/signed, and size of both must be 32-bits
A1683E: Data type specifiers do not match a valid encoding of this instruction
A1684E: Source operand type should be signed or unsigned with size between and

A1685E: Source operand type should be signed, unsigned or floating point with size
between and
A1686E: Source operand type should be signed or floating point with size between
and
A1687E: Source operand type should be integer or floating point with size between
and
A1688E: Source operand type should be untyped with size between and
A1689E: Source operand type should be -bit floating point
100074_0610_00_en

2-33

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1690E: Source operand type should be signed with size between and
A1691E: Source operand type should be integer, floating point or polynomial with size
between and
A1692E: Source operand type should be signed, unsigned or polynomial with size
between and
A1693E: Source operand type should be unsigned or floating point with size between
and
A1694E: Instruction cannot be conditional in the current instruction set

Conditional instructions are not permitted in the specified instruction set. The instruction MOVEQ,
for example, is permitted in A32 code, and in T32 code in architectures in which the IT
instruction is available.
A1695E: Scalar index not allowed on this instruction
A1696E: Expected either 32-bit, 64-bit or 128-bit register expression
A1697E: Expected either 32-bit or 64-bit VFP register expression
A1698E: Expected 32-bit VFP register expression
A1699E: 64-bit data type cannot be used with these registers
A1700E: Source operand type should be integer with size between and
A1701E: 16-bit polynomial type cannot be used for source operand
A1702E: Register Dm can not be scalar for this instruction
A1704E: Register Dm must be in the range D0-D for this data type
A1705W: Assembler converted Qm register to D[]
A1706E: Register Dm must be scalar
A1708E: 3rd operand to this instruction must be a constant expression
A1709E: Expected ARM or scalar register expression
A1710E: Difference between current and previous register should be
A1711E: Scalar registers cannot be used in register list for this instruction
A1712E: This combination of LSB and WIDTH results in UNPREDICTABLE behavior
A1713E: Invalid field specifiers for APSR: must be APSR_ followed by at least one of
n, z, c, v, q or g
A1714E: Invalid combination of field specifiers for APSR
A1715E: PSR not defined on target architecture
A1716E: Destination for VMOV instruction must be ARM integer, 32-bit singleprecision, 64-bit doubleword register or 64-bit doubleword scalar register
A1717E: Source register must be an ARM integer, 32-bit single-precision or 64-bit
doubleword scalar register
A1718E: Source register must be an ARM integer register or same as the destination
register
A1719W: This PSR name is deprecated and may be removed in a future release
A1720E: Source register must be a 64-bit doubleword scalar register
A1721E: Destination register may not have all-lanes specifier
A1722E: Labels not allowed inside IT blocks
A1723W: __RELOC is deprecated, please use the new RELOC directive
A1724E: RELOC may only be used immediately after an instruction or data generating
directive
A1725W: 'armasm inputfile outputfile' form of command-line is deprecated
A1726W: Decreasing --max_cache below 8MB is not recommended
A1727W: Immediate could have been generated using the 16-bit Thumb MOVS instruction
A1728E: Source register must be same type as destination register
A1729E: Register list may only contain 32-bit single-precision or 64-bit doubleword
registers
A1730E: Only IA or DB addressing modes may be used with these instructions
A1731E: Register list increment of 2 or more is not allowed for quadword registers
A1732E: Register list must contain between 1 and 4 contiguous doubleword registers
A1733E: Register list must contain 2 or 4 doubleword registers, and increment 2 is
only allowed for 2 registers
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2-34

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1734E: Register list must contain doubleword registers with increment 1 or 2
A1735E: Post-indexed offset must equal the number of bytes loaded/stored ()
A1736E: Number of registers in list must equal number of elements
A1737E: PC or SP can not be used as the offset register
A1738E: Immediate too large for this operation
A1739W: Constant generated using single VMOV instruction; second instruction is a NOP
A1740E: Number of bytes in FRAME PUSH or FRAME POP directive must not be less than
zero
A1741E: Instruction cannot be conditional
A1742E: Expected LSL #Imm
A1744E: Alignment on register must be a multiple of 2 in the range 16 to 256
A1745W: This register combination is DEPRECATED and may not work in future
architecture revisions

This warning is generated when all of the following conditions are satisfied:
• You are using a deprecated register combination, for example:
PUSH

•
•
•
•

{r0, pc}

You are assembling for a target architecture that supports 32-bit T32 instructions, in other
words Armv6T2 or later.
You are assembling to A32 code.
Note
When assembling to T32, rather than A32 code, and the target architecture is Armv6T2 or
later, the assembler generates error A1477E instead.
When assembling for an architecture or processor that does not support 32-bit T32
instructions, in other words Arm architectures before Armv6T2, by default no diagnostic is
emitted.

A1746W: Instruction stall diagnostics may be unreliable for this CPU

This warning is shown when you enable message A1563W for a processor that is not modeled
accurately by the assembler. It indicates that you cannot rely on the output of A1563W when
improving your code.
See also warning A1563W.
A1753E: Unrecognized memory barrier option
A1754E: Cannot change the type of a scalar register
A1755E: Scalar index has already been specified on this register
A1756E: Data type must be specified on all registers
A1757W: Symbol attributes must be within square brackets; Any other syntax is
deprecated
A1758W: Exporting multiple symbols with this directive is deprecated
A1759E: Specified processor or architecture does not support Thumb-2EE instructions
A1760W: Build Attribute is ''
A1761W: Difference in build attribute from '' in
A1762E: Branch offset 0x out of range of 16-bit Thumb branch, but offset
encodable in 32-bit Thumb branch

This is caused when assembling for T32 if an offset to a branch instruction is too large to fit in a
16-bit branch. The .W suffix can be added to the instruction to instruct the assembler to generate
a 32-bit branch.

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2-35

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1763W: Inserted an IT block for this instruction

This indicates that the assembler has inserted an IT block to permit a number of conditional
instructions in T32 code. For example:
MOVEQ r0,r1

This warning is off by default. It can be enabled using --diag_warning A1763.
A1764W: instructions are deprecated in architecture and above
A1765E: Size of padding value on ALIGN must be 1, 2 or 4 bytes

This is caused when the optional padsize attribute is used with an ALIGN directive, but has an
incorrect size. It does not refer to the parameter to align to. The parameter can be any power of 2
from 2^0 to 2^31.
A1766W: Size of padding value for code must be a minimum of bytes; treating as
data
A1767E: Unexpected characters following attribute
A1768E: Missing '='
A1769E: Bad NEON or VFP system register name symbol
A1771E: Bad floating-point bitpattern when expecting -bit bitpattern
A1772E: Destination type must be signed or unsigned integer, and source type must be
32-bit or 64-bit floating-point
A1773E: Floating-point conversion only possible between 32-bit single-precision and
64-bit double-precision types
A1774E: Fixed-point conversion only possible for 16-bit or 32-bit signed or unsigned
types
A1775E: Conversion between these types is not possible
A1776E: This operation is not available for 32-bit single-precision floating point
types
A1777E: is out of range for symbol type; value must be between and
A1778E: is out of range for symbol binding; value must be between and
A1779E: DCDO cannot be used on READONLY symbol ''
A1780E: Unknown ATTR directive
A1781E: Tag # cannot be set by using ATTR
A1782E: Tag # should be set with ATTR
A1783E: Attribute scope must be a label or section name
A1784W: Reference to weak definition '' not relocated
A1785E: Macro '' not found, but '' exists

100074_0610_00_en

2-36

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1786W: This instruction using SP is deprecated and may not work in future
architecture revisions

This warning is generated when all of the following conditions are satisfied:
•

You explicitly use the SP in a deprecated way, for example:
ADD sp, r0, #100

•
•

You are assembling for a target architecture that supports 32-bit T32 instructions, in other
words Armv6T2 or later.
You are assembling to A32 code.

Arm deprecates the explicit use of the SP in A32 instructions in any way that is not possible in
the corresponding T32 instruction. Such deprecated register uses are still possible in A32
instructions for backwards compatibility and you can suppress this warning by using the
assembler’s command line option --diag_suppress=1786. However, Arm recommends you
modify your code, because it might not work in future architecture revisions.
You can replace the deprecated use of the SP shown in the example with a sequence like:
ADD r1, r0, #100
MOV sp, r1

•
•

Note
When assembling to T32, rather than A32 code, and the target architecture is Armv6T2 or
later, the assembler generates error A1477E instead.
When assembling for an architecture or processor that does not support 32-bit T32
instructions, in other words Arm architectures before Armv6T2, by default no diagnostic is
emitted.

A1787W: Use of VFP Vector Mode is deprecated in ARMv7
A1788W: Explicit use of PC in this instruction is deprecated and may not work in
future architecture revisions

This warning is generated when all of the following conditions are satisfied:
•

You explicitly use the PC in a deprecated way, for example:
CMP pc, #1

•
•

You are assembling for a target architecture that supports 32-bit T32 instructions, in other
words Armv6T2 or later.
You are assembling to A32 code.

When assembling to T32, rather than A32 code, and the target architecture is Armv6T2 or
later, the assembler generates error A1477E instead.
When assembling for an architecture or processor that does not support 32-bit T32
instructions, in other words Arm architectures before Armv6T2, by default no diagnostic is
emitted.

A1789W: Explicit use of PC in this instruction is deprecated and and may not work in
future architecture revisions, except as destination register

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2-37

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1790W: Writeback ignored in Thumb LDM loading the base register

This is caused by incorrectly adding an exclamation mark to indicate base register writeback.
For example:
LDM r0!, {r0-r4}

is not a legal instruction because r0 is the base register and is also in the destination register list.
In this case, the assembler ignores the writeback and generates:
LDM r0, {r0-r4}

A1791W:
A1792E:
A1793E:
A1794E:
A1795E:
A1796E:
A1797E:
A1798W:
A1799W:
A1800W:
A1801E:
A1803E:
A1804E:
A1805E:
A1806E:
A1807W:
A1808E:
A1809W:
aligned

Previous value of tag # will be overridden
Undefined build attributes tag
Conversion only possible between 16-bit and 32-bit floating point
Conversion operations require two data types
Source and destination vector must contain elements
Register type not consistent with data type
Specified FPU is not compatible with CPU architecture
Output is not WYSIWYG ()
Output has not been checked for WYSIWYG property
No output for line
Instruction is UNPREDICTABLE in current instruction set
Bad system instruction name
Bad CP14 or CP15 register name for instruction
Register is Read-Only
Register is Write-Only
Instruction executes as NOP on target CPU
Generated object file may be corrupt ()
Instruction aligns PC before using it; section ought to be at least 4 byte

This warning is generated when all the following conditions apply:
• You are using a PC-relative offset in a T32 instruction that requires the PC to be wordaligned.
• The code section containing this instruction has less than 4-byte alignment.
• The instruction is not relocated at link time (because of a relocation emitted by the
assembler).
If these conditions are all met, and the code section containing this instruction is not placed at a
4-byte aligned address when linking, the instruction might operate on or with the wrong address
at runtime. This is because the instruction aligns the PC to a 4-byte address before using it.
The following example shows an LDR instruction in T32 that is diagnosed by this warning
because the section has an alignment of 2 bytes:
AREA ||.text||, CODE, READONLY, ALIGN=1
THUMB
LDR r0, [pc, #8] ; gives warning A1809W

A1810E:
A1811E:
A1812W:
A1813W:
A1814E:
A1815E:
A1816E:
A1817W:
A1818W:
A1819W:
A1820E:
100074_0610_00_en

Base register writeback value unclear; use '[rn,#n]!' or '[rn],#n' syntax
Size of fill value must be 1, 2 or 4 bytes and a factor of fill size
Instruction cannot be assembled in the opposite instruction set
32-bit instruction used where 16-bit could have been used
No output file
SHT_ARM_EXIDX sections require a link order dependency to be set
Unknown opcode '' in CODE16, but exists in THUMB
ATTR tag # setting ignored in
ATTR COMPAT flag and vendor '' setting ignored in
ATTR compatible with tag # setting ignored in
Register and processor mode not valid for instruction
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-38

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1821E: Expected constant or register expression
A1822E: Expected list of 32-bit extension registers
A1823E: Expected list of 64-bit extension registers
A1824E: Expected core register or 32-bit, 64-bit or 128-bit extension register
A1825E: Expected constant or 32-bit extension register
A1826E: Expected constant or 64-bit extension register
A1827E: Expected constant or 128-bit extension register
A1828E: Expected core register or 32-bit extension register
A1829E: Expected core register or 64-bit extension register
A1830E: Expected core register or 128-bit extension register
A1831E: Expected constant, floating-point constant, core register or 64-bit extension
register
A1832E: Expected floating-point constant, core register or 32-bit extension register
A1833E: Expected constant or '{option}', where option is a constant from 0 to 255
A1834E: Expected register or address expression
A1835E: Too few data types specified on instruction
A1836E: Expected '
' data type for destination
A1837E: Expected '
' data type for first source
A1838E: Unexpected characters when expecting '' or ''
A1839E: Destination register must be scalar
A1840E: First source register must be scalar
A1841E: Alignment specified on base register not valid for instruction
A1842E: Syntax not allowed for a pseudo-instruction
A1843E: Literal load not supported for instruction
A1844E: Literal type not supported
A1845E: Register type not available in current instruction set
A1846E: Invalid field specifiers for CPSR or SPSR: must be followed by at least one
of c, x, s or f
A1847E: Expression requiring more than one relocation not allowed

This can occur during the assembly of A32 instructions when trying to access data in another
area. For example, using:
LDR r0, [pc, #label - . - 8]

or its equivalent:
LDR r0, [pc, #label-{PC}-8]

where label is defined in a different AREA.
Change your code to use the simpler, equivalent syntax:
LDR r0, label

This works if label is either in the same area or in a different area.
A1848W:
A1849E:
A1850E:
A1851E:
A1852E:
A1853E:
A1854E:
A1856E:
A1857E:
A1858E:
A1859E:
A1860E:
A1861E:
100074_0610_00_en

State change in IT block
Scalar index on operand out of range for data type
Width must be before any data type qualifiers
Invalid line start - local label not supported on this directive
Use of VFP Vector Mode is not supported on target FPU
Alignment of instruction or target must be at least -byte aligned
Unknown opcode '', maybe wrong target CPU?
Shifted register operand not allowed
Specified shift not allowed
Flag setting form of this instruction not available
Flag preserving form of this instruction not available
Register operands must be from R0 to R7 in this instruction
Option '' is obsolete.
Copyright © 2014–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

2-39

2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1862E: Data type size for floating-point must be 16 or 32
A1863E: Data type size for floating-point must be 32
A1864E: Data type size for floating-point must be 16, 32 or 64
A1865W: '#' not seen before constant expression
A1866E: Wireless MMX Control register not defined on target CPU
A1867E: Immediate 0x out of range for this operation. Permitted values are
multiples of from 0x to 0x
A1868E: Bitfield LSB out of range. Permitted values are 0 to
A1869E: Register must not be PC
A1870W: Area '' has incorrect attributes, expect ''
A1871E: Immediate 0x cannot be represented by 0-255 shifted left by 0-23 or
duplicated in all, odd or even bytes

This error occurs when armasm cannot encode the instruction with the specified immediate.
For example, in Arm Compiler 4.1 and above, the following instruction causes this error in T32
state:
ADDS

r0, r1, #-20

A workaround is to use the equivalent SUBS instruction instead:
SUBS

A1872E:
A1873E:
A1874E:
A1875E:

r0, r1, #20

Shift by register not allowed
Only the non-writeback form of this instruction exists
Specified register list cannot be loaded or stored in target instruction set
Register Rn must be from R0 to R7 in this instruction

Change the specified register to be in the range R0 to R7.
A1876W: Use of '|' as a synonym for the :OR: operator is deprecated.
A1877E: Specified register for not allowed in current instruction set
A1878E: Offset must be -byte aligned when used with this operation
A1879E: Specified addressing mode not available
A1880E: Data transfer size not available
A1881E: load/store mode is not permitted
A1882E: Destination and first source register must be same
A1883E: Destination and second source register must be same
A1884E: Specified AIF bits not available on target CPU
A1885E: Cannot change processor mode in current instruction set
A1886E: Invalid operand size for add with carry-in: must be 16 or 32
A1887E: Specified source data type not allowed; must be one of:
A1888E: Specified destination data type not allowed; must be one of:
A1889E: Specified register type not available on target architecture
A1890E: Specified shift results in UNPREDICTABLE behaviour
A1891E: With this register combination, writeback results in UNPREDICTABLE behaviour
A1892W: Writeback with this register combination is deprecated and may not work in
future architecture revisions
A1893E: The specified flags result in UNPREDICTABLE behaviour
A1894E: The specified immediate results in UNPREDICTABLE behaviour
A1895E: The specified condition results in UNPREDICTABLE behaviour
A1896E: Specified alignment not supported on this instruction
A1897E: Bitfield width out of range. Permitted values are 1 to
A1898E: Target cannot be relocated. No suitable relocation exists for this
instruction
A1899E: Specified operator is only allowed on the following instructions:
A1900W: Deprecated system instruction name
A1901E: Specified system instruction not supported on target architecture

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2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1902E: Specified special register not supported on target architecture
A1903E: Line not seen in first pass; cannot be assembled

This occurs if an instruction or directive does not appear in pass 1 but appears in pass 2 of the
assembler.
The following example shows when a line is not seen in pass 1:
AREA x,CODE
[ :DEF: foo
num EQU 42 ; Assembler does not see this line during pass 1 because
; foo is not defined at this point during pass 1
]
foo DCD num
END

A1905U: Pre-processor step failed for ''
A1906W: Unfinished IT block
A1907W: Test for this symbol has been seen and may cause failure in the second pass.

This diagnostic is suppressed by default. Enable it to identify situations that might result in
errors A1903E, A1908E, or A1909E.
A1908E: Label '' value inconsistent: in pass 1 it was ; in pass 2 it was

The following example generates this error because in pass 1 the value of x is 0x0004+r9, and in
pass 2 the value of x is 0x0000+r0:
map 0, r0
if :lnot: :def: sym
map 0, r9
field 4
endif
x
field 4
sym LDR r0, x

A1909E: Line not seen in second pass; cannot be assembled

This occurs if an instruction or directive appears in pass 1 but does not appear in pass 2 of the
assembler.
The following example shows when a line is not seen in pass 2:
AREA x,CODE
[ :LNOT: :DEF: foo
MOV r1, r2 ; Assembler does not see this line during pass 2 because
; foo is already defined
]
foo MOV r3, r4
END

A1911E: Immediate 0x out of range for this operation. Immediate value must be 0
A1912E: In this instruction, register must not be PC when flag-setting is
specified
A1913E: Specified operand type not allowed in this position
A1914E: Expected expression
A1915W: Relocation is not recommended on this instruction or directive
A1916E: Unknown built-in variable ''
A1917E: Expected vector register expression
A1921E: Expected 8-bit byte register expression
A1922E: Expected 16-bit halfword register expression
A1923E: Expected list of vector registers
A1925E: Coprocessor number must be 14 or 15 on this architecture
A1927E: Expected core register, 64-bit extension register or vector register
A1931W: This instruction inside IT block is deprecated
A1932E: Register type not allowed on this architecture
A1933E: Option '' not supported on target architecture

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2 Assembler Errors and Warnings
2.1 List of the armasm error and warning messages

A1934E:
A1936E:
A1937E:
A1938E:
A1939W:
A1940E:
A1941E:
A1942E:
A1943E:
A1944E:
A1992E:
A1993E:
A1994E:
A1995E:
A1996E:
A1997E:
A1998E:
A1999E:

100074_0610_00_en

Shift by not allowed. Permitted values are
Literal pool too distant, use LTORG to assemble it within
Conversions to fixed point only support rounding mode Z
Coprocessor number must be 14 on this architecture
This mnemonic is deprecated
Execute only is not compatible with

Arm® Compiler Errors And Warnings Reference Guide 100074 0610 00 En

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