FAN6749 — Highly Integrated Ultra Green Mode PWM Controller Fairchild

User Manual: Marking of electronic components, SMD Codes 67, 67**, 6721, 6741, 6741A, 6742HL, 6742HR, 6742ML, 6742MR, 6747, 6749ML. Datasheets BAS40-07V, FAN6747, FAN6749MLM, IRF6721SPbF, NUP4302MR6, SG6741A, SG6741SY, SG6742HL, SG6742HR, SG6742ML, SG6742MR, STP3467.

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FAN6749
Highly Integrated Ultra Green-Mode PWM Controller
Features

Description



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


High-Voltage Startup





Two-Level OCP, 56 ms Delay for Super Peak Load

The FAN6749 highly integrated PWM controller
enhances the performance of flyback converters. To
minimize standby power consumption, a proprietary
Green-Mode function continuously decreases the
switching frequency under light-load conditions. Under
zero-load conditions, the power supply enters Burst
Mode and completely shuts off PWM output. Green
Mode helps power supplies meet international power
conservation requirements.

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


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HV Pin Brown-in/out Protection with Hysteresis

Low Operating Current: 1.8 mA
Linearly Decreasing PWM Frequency to 24 kHz
Proprietary Frequency Hopping to Reduce EMI
Two-Level Over-Current Protection (OCP),
1400 ms Delay for Normal Peak Load
Output Short-Circuit Protection (SCP)
Peak-Current Mode Operation with Cycle-by-Cycle
Current Limiting
Constant Power Limit by HV Sampling
Internal FB Open-Loop Protection (OLP)
GATE Output Maximum Voltage Clamp: 14.5V
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Integrated 6ms Soft-Start Function
Internal Latch Circuit (OVP, OTP, OCP, OLP, SCP)
Internal OTP Sensor with Hysteresis

Applications
General-Purpose Switched-Mode Power Supplies and
Flyback Power Converters, including:




Power Adapters
Open-Frame SMPS; Specifically for SMPS with
Surge-Current Output, such as for Printer, Scanner,
Motor Drivers

The FAN6749 is designed for SMPS with surge-current
output and incorporates a two-level Over-Current
Protection (OCP) function. Besides the cycle-by-cycle
current limiting, two-level OCP can handle peak loading
within a specified delay time.
FAN6749 also integrates a frequency-hopping function
that helps reduce EMI emission of a power supply with
minimum line filters. Built-in synchronized slope
compensation helps achieve stable peak-current control.
To keep constant output power limit over universal AC
input range, the current limit and OCP threshold voltage
are adjusted according to AC line voltage detected by
the HV pin. Gate output is clamped at 14.5 V to protect
the external MOSFET from over-voltage damage.

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

October 2012

Other protection functions include: AC input brownout
protection with hysteresis, Short-Circuit Protection
(SCP) for output-short condition, and VDD Over-Voltage
Protection (OVP). For over-temperature protection, an
external NTC thermistor can be applied to sense the
ambient temperature. When OLP, OCP, SCP, VDD OVP,
or OTP is activated, an internal latch circuit latches off
the controller. The latch resets when VDD is removed.
OVP

OCP

OLP

OTP

SCP

Latch

There are three differences from FAN6748 to FAN6749:
 Over-current protection debounce time is extended
to 1400 ms.
 Brown-out debounce time is extended to 100 ms.
 No SENSE short-circuit protection function.

Ordering Information
Part Number

Operating Temperature Range

Package

Packing
Method

FAN6749MLM

-40 to +105°C

8-Pin Small Outline Package (SOP)

Reel & Tape

www.fairchildsemi.com

Figure 1. Typical Application

Internal Block Diagram

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Application Diagram

Figure 2. Functional Block Diagram
© 2012 Fairchild Semiconductor Corporation
FAN6749 • Rev. 1.0.3

www.fairchildsemi.com
2

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Marking Information
F - Fairchild Logo
Z - Plant Code
X - 1-Digit Year Code
Y - 1-Digit Week Code
TT - 2-Digit Die Run Code
T - Package Type (M=SOP)
M - Manufacture Flow Code

ZXYTT
6749ML
TM

Figure 3. Top Mark

Pin Configuration
GND

GATE

VDD

SENSE

Figure 4. Pin Configuration (Top View)

Pin Definitions
Pin #

Name

GND

Feedback Pin. The output voltage feedback information from the external compensation circuit is
fed into this pin. The PWM duty cycle is determined by comparing the FB signal with currentsense signal from the SENSE pin.

No Connection

High-Voltage Startup. The HV pin is typically connected to the AC line input through an external
diode and a resistor (RHV). This pin is used not only to charge VDD capacitor during startup, but
also to sense the line voltage. The line voltage information is used for brown-out protection and
power limit line compensation.

Over-Temperature Protection. An external NTC thermistor is connected from this pin to the
GND pin. Once the voltage of the RT pin drops below the threshold voltage, the controller latches
off the PWM. The RT pin also provides external latch protection. If the RT pin is not connected to
an NTC resistor for over-temperature protection, place a 100 kΩ resistor to ground to prevent
noise interference.

SENSE

VDD

Power Supply of IC. A holdup capacitor typically connects from this pin to ground. A rectifier
diode in series with the transformer auxiliary winding connects to this pin to supply bias during
normal operation.

GATE

Gate Drive Output. The totem-pole output driver for the power MOSFET; internally limited to
VGATE-CLAMP.

Description
Ground Pin. A 0.1 µF decoupling capacitor between VDD and GND is recommended.

Current Sense. The sensed voltage is used for peak-current-mode control, over-current
protection, short-circuit protection, and cycle-by-cycle current limiting.

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3

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

(1,2)

Max.

Unit

VDD

DC Supply Voltage

VFB

FB Pin Input Voltage

-0.3

7.0

SENSE Pin Input Voltage

-0.3

7.0

RT Pin Input Voltage

-0.3

7.0

VSENSE
VRT
VHV

Continuous Input Voltage

500

(3)

Pulse Input Voltage

640

Power Dissipation (TA＜50°C)

400

JA

Thermal Resistance (Junction-to-Air)

150

C/W

Operating Junction Temperature

-40

+125

C

Storage Temperature Range

-55

+150

C

+260

C

All Pins Except HV Pin

TSTG
TL

Lead Temperature (Wave Soldering or IR, 10 Seconds)
(4)

ESD

Human Body Model , JEDEC:JESD22-A114
(4)

Charged Device Model , JEDEC:JESD22-C101

Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. Duration of pulse input voltage is less than or equal to ≤ 1 second.
4. ESD with the HV pin CDM=1000 V and HBM=500 V.

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Absolute Maximum Ratings

Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol
RHV

Parameter
HV Startup Resistor

Min.

Typ.

Max.

Unit

150

200

250

kΩ

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4

VDD=15 V and TA=25C unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VDD Section
Continuously Operating Voltage

Limited by VDD OVP

VDD-ON

VOP

Threshold Voltage to Startup

VDD Rising

VDD-OFF

Threshold Voltage to Stop
Switching in Protection Mode

VDD Falling

VDD-OLP

Threshold Voltage to Turn On HV
Startup in Protection Mode

VDD Falling

6.5

7.5

8.5

Threshold Voltage to Stop
Switching in Normal Mode

VDD Falling

6.0

6.5

7.0

VDD Falling

4.5

5.0

5.5

VDD Falling

3.5

4.0

4.5

VUVLO
+2.5

VUVLO +3

VUVLO +3.5

VDD-OFF
+1.0

VDD-OFF
+1.5

VDD-OFF +2.0

µA

VUVLO

Threshold Voltage to Enable HV
VRESTART Startup to Charge VDD in Normal
Mode

VDD-LH

Threshold Voltage to Release
Latch Mode

VDD-AC

Threshold Voltage on VDD Pin for
Disable Brown-in to Avoid Startup
Failure

VDD-SCP

Threshold Voltage on VDD Pin for
Short-Circuit Protection (SCP)

VFB > VFB-OLP

tD-SCP

Debounce Time for SCP

VFB>VFB-OLP
& VDD< VDD-SCP

IDD-ST

Startup Current

VDD-ON – 0.16 V

IDD-OP1

VDD=20 V, VFB = 3 V
Supply Current in PWM Operation
Gate Open

1.8

2.4

IDD-OP2

Supply Current when PWM Stops

VDD=15 V, VFB < 1.4 V

1.0

1.9

ILH

Operating Current when VDD VFB-N

170

200

230

VFB < VFB-G

400

520

640

VFB > VFB-N

VFB = VFB-G

100

130

IHV-LC

tS-CYCLE

Line Voltage Sample Cycle(7)

tH-TIME

Line Voltage Hold Period(7)

tUPDATE

Peak Line Voltage Data
Update Cycle for High / Low
Line Compensation(7)

tD-AC-OFF

Debounce Time for Brownout

DC Source Series R=200 kΩ to HV Pin

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Electrical Characteristics (Continued)

µs
µs
ms
ms

Oscillator Section
fOSC

Switching Frequency when VFB>VFB-N

tHOP

Hopping Period

Center Frequency
Hopping Range
Center Frequency

fOSC-G

Switching Frequency When VFBVOCP

1000

1400

1800

tSS
tD-OCP

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Electrical Characteristics (Continued)

Continued on the following page…
PWM Frequency

fOSC

fOSC-G

VFB-ZDC VFB-ZDCR VFB-G

VFB-N

VFB

Figure 7. VFB vs. PWM Frequency
© 2012 Fairchild Semiconductor Corporation
FAN6749 • Rev. 1.0.3

www.fairchildsemi.com
7

VDD=15 V and TA=25C unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

1.5

GATE Section
DMAX

Maximum Duty Cycle

VGATE-L

Gate Low Voltage

VDD=15 V, IO=50 mA

VGATE-H

Gate High Voltage

VDD=12 V, IO=50 mA

Gate Rising Time (20-80%)

VDD=15 V, CL=1 nF

Gate Falling Time (80-20%)

VDD=15 V, CL=1 nF

VDD=15 V

300

VDD=15 V, GATE=6 V

250

VDD=22 V

11.0

14.5

18.0

100

110

µA

1.015

1.050

1.085

0.65

0.70

0.75

9.66

10.50

11.34

kΩ

(7)

IGATE-SINK Gate Sink Current

IGATE-SOURCE Gate Sourcing Current

(7)

VGATE-CLAMP Gate Output Clamping Voltage

RT Section
IRT

Output Current of RT Pin

VRTTH1

Threshold Voltage for Over-Temperature 0.7 V ＜ VRT ＜ 1.05 V,
Protection
After 14 ms Latch Off

VRTTH2

Threshold Voltage for Latch Triggering

ROTP

VRT ＜ 0.7 V, After 165 µs
Latch Off

Maximum External Resistance of RT Pin
to Trigger Latch Protection

tD-OTP1

Debounce Time for Over-Temperature
Protection Triggering

VRTTH2 ＜ VRT ＜ VRTTH1

tD-OTP2

Debounce Time for Latch Triggering

VRT < VRTTH2

165

240

µs

Over-Temperature Protection Section (OTP)
TOTP
TRestart

Protection Junction Temperature(5,7)
(6,7)

Restart Junction Temperature

+135

°C

TOTP25

°C

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Electrical Characteristics (Continued)

Notes:
5. When activated, the output is disabled and the latch is turned off.
6. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated.
7. Guaranteed by design.

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8

Figure 8. Startup Current (IDD-ST) vs. Temperature

Figure 9. Operation Supply Current (IDD-OP1)
vs. Temperature

Figure 10. Start Threshold Voltage (VDD-ON)
vs. Temperature

Figure 11. Minimum Operating Voltage (VDD-OFF)
vs. Temperature

Figure 12. Supply Current Drawn from HV Pin (IHV)
vs. Temperature

Figure 13. HV Pin Leakage Current After Startup (IHV-LC)
vs. Temperature

Figure 14. Frequency in Normal Mode (fOSC) vs.
Temperature

Figure 15. Maximum Duty Cycle (DCYMAX) vs.
Temperature

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Typical Performance Characteristics

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9

Figure 16. FB Open-Loop Trigger Level (VFB-OLP) vs.
Temperature

Figure 18.

Figure 20.

Figure 17. Delay of FB Pin Open-Loop Protection (tD-OLP)
vs. Temperature

VDD Over-Voltage Protection (VDD-OVP)
vs. Temperature

Figure 19.

Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature

Figure 22.

Figure 21. Over-Temperature Protection Threshold
Voltage (VRTTH2) vs. Temperature

Brown-in (VAC-ON) vs. Temperature

Output Current from RT Pin (IRT)
vs. Temperature

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Typical Performance Characteristics

Figure 23. Brown-out (VAC-OFF) vs. Temperature

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Current Mode Control

fOSC

FAN6749 employs peak current mode control, as shown
in Figure 24. An opto-coupler (such as the H11A817A)
and a shunt regulator (such as the KA431) are typically
used to implement the feedback network. Comparing the
feedback voltage with the voltage across the Rsense
resistor makes it possible to control the switching duty
cycle. The built-in slope compensation stabilizes the
current loop and prevents sub-harmonic oscillation.

fOSC-G

VFB-ZDC VFB-ZDCR VFB-G

VFB-N

VFB

Figure 25. VFB vs. PWM Frequency

Figure 24. Current Mode Control Circuit Diagram

Green-Mode Operation
FAN6749 modulates the PWM frequency as a function
of the FB voltage to improve the medium- and light-load
efficiency, as shown in Figure 25. Since the output
power is proportional to the FB voltage in current mode
control, the switching frequency decreases as load
decreases. In heavy-load conditions, the switching
frequency is fixed at 65 kHz. Once VFB decreases below
VFB-N (2.7 V), the PWM frequency starts linearly
decreasing from 65 kHz to 24 kHz to reduce switching
losses. As VFB drops to VFB-G (2.25 V), where switching
frequency is decreased to 24 kHz, the switching
frequency is fixed to avoid acoustic noise.

Figure 26. Burst Switching in Green Mode

Operating Current
In normal condition, operating current is around 1.8 mA
(IDD-OP1); when VFB<1.4 V, operating current is further
reduced to 1 mA (IDD-OP2) by disabling several blocks of
FAN6749. The low operating current improves light-load
efficiency and reduces the requirement of VDD hold-up
capacitance.

High-Voltage Startup and Line Sensing

When VFB falls below VFB-ZDC (2.0 V) as load decreases
further, FAN6749 enters Burst Mode, where PWM
switching is disabled. Then the output voltage starts to
drop, causing the feedback voltage to rise. Once VFB
rises above VFB-ZDCR (2.1 V), switching resumes. Burst
Mode alternately enables and disables switching,
thereby reducing switching loss for lower power
consumption, as shown in Figure 26

The HV pin is typically connected to the AC line input
through an external diode and a resistor (RHV), as shown
in Figure 27. When AC line voltage is applied, the VDD
hold-up capacitor is charged by the line voltage through
the diodes and resistor. After VDD voltage reaches the
turn-on threshold voltage (VDD-ON), the startup circuit
charging VDD capacitor is switched off and VDD is
supplied by the auxiliary winding of the transformer.
Once FAN6749 starts up, it continues operation until
VDD drops below 6.5 V (VUVLO). The IC startup time with
a given AC line input voltage is given as:

tSTARTUP  RHV  CDD  ln

VAC IN 
VAC IN 

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Functional Description



(1)

 VDD ON

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11

Figure 28.

Cycle-by-Cycle Current-Limit Circuit

The HV pin detects the AC line voltage using a switched
voltage divider that consists of external resistor (RHV)
and internal resistor (RLS), as shown in Figure 27. The
internal line-sensing circuit detects line voltage using a
sampling circuit and a peak-detection circuit. Since the
voltage divider causes power consumption when it is
switched on, the switching is driven by a signal with a
very narrow pulse width to minimize power loss. The
sampling frequency is adaptively changed according to
the load condition to minimize the power consumption in
the light-load condition.
Based on the detected line voltage, brown-in and brownout thresholds are determined as:

V BROWN - IN (RMS) 
V BROWN-OUT (RMS) 

R HV V AC ON

200k



R HV V AC OFF

200k



(2)
(3)

Figure 29. Current Limit vs. Line Voltage

Two-Level Over-Current Protection (OCP)

Since the internal resistor (RLS=1.62 kΩ) of the voltage
divider is much smaller than RHV, the thresholds are
given as s function of RHV.

Other than cycle-by-cycle current limiting, FAN6749
applies another threshold voltage, VOCP, for current
sense. As shown in Figure 28, when peak of VSENSE
exceeds VOCP at each pulse for a period of time, tD-OCP;
over-current protection (OCP) is triggered. This
protection is designed for applications with surge-current
outputs. If a peak load is present for less than tD-OCP, the
controller operates as usual. If the peak load continues
longer than tD-OCP, GATE output is stopped to protect the
converter from overload condition.

Note that VDD must be larger than VDD-AC to start up,
even though sensed line voltage satisfies Equation 2.

High/Low Line Compensation for Constant
Power Limit
FAN6749 has cycle-by-cycle current limit, as shown in
Figure 28, which limits the maximum input power with a
given input voltage. If the output consumes beyond this
maximum power, the dropping output voltage triggers
the overload protection.

Like VLIMIT, the VOCP is adjusted by high/low line
compensation block to maintain a constant over-current
protection level, regardless of line voltage. Figure 31
shows how VOCP changes with the line voltage with
different RHV resistors.

As shown in Figure 28, the high/low line compensation
block adjusts the current limit level, VLIMIT, based on the
line voltage. Figure 29 shows how the cycle-by-cycle
current-limit level changes with the line voltage for
different RHV resistors. To maintain the constant output
power limit regardless of line voltage, the cycle-by-cycle
current limit level, VLIMIT, decreases as line voltage
increases. The current-limit level is also proportional to
the RHV resistor value and power limit level can be tuned
using different RHV resistors.
© 2012 Fairchild Semiconductor Corporation
FAN6749 • Rev. 1.0.3

FAN6749 — Highly Integrated Ultra Green-Mode PWM Controller

Figure 27. Startup Circuit

When OCP is triggered, it is recommended to have
VFB>VFB-N for whole AC input range. VFB>VFB-N ensures
switching frequency is fixed at 65 kHz. If OCP is
triggered in the frequency-reduction region (VFB
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