Intel 815E Schematics. Www.s Manuals.com. R1.05 Schematics

User Manual: Motherboard Intel 815E - Schematics. Free.

Open the PDF directly: View PDF .
Page Count: 34

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Revision 1.05 - Fab C

**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

PAGETITLE

2

3,4

5

6

7,8

10

11

12,13

9

18

19

20

21

22

23

24

25

1COVER SHEET

BLOCK DIAGRAM

PGA370 PART 1 & 2

AGTL TERMINATION

CLOCK GENERATOR

GMCH PART 1 & 2

DIMM 1 & 2

17

15

16

26

INTERNAL DEBUG HEADERS

DECOUPLING CAPACITORS

PU/PDR & UNUSED GATES

AGP

ICH PART 1 & 2

PCI 1 & 2

AUDIO I/O

AC97 CODEC

VIDEO BUS & CONNECTOR

LPC I/O CONTROLLER & FDCL

KB, MS, GAME & IR

ATX POWER & H/W MONITOR

DIMM 3

27

28

PCI 3

14

FRONT PANEL & CNR

29

30

VREGS: DUALS, 3.3SB, 2.5, VCMOS

WOR, WOL & 2S1P

USB 0-3

31

FWH & UDMA100 IDE 1-2

Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset

Universal Socket 370 Platform

Customer Reference Board Schematics

32

SYSTEM CONFIGURATION

VREGS: VCCVID, V1_8SB

VREGS: VDDQ, VCC1_8, AND VTT

THERMTRIP 33

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions

of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating

to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,

or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,

life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."

Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising

from future changes to them.

The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product

order.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was

developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips

Electronics N.V. and North American Philips Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel®, Pentium®, Pentium® III, Celeron™, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in

the United States and other countries.

*Other brands and names may be claimed as the property of others.

Copyright© 2001, Intel Corporation

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Title Page

133

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VRM

CTRL

ADDR

DATA

ADDR

CLOCK

DATA

CTRL

USB

IDE Primary

IDE Secondary

370-PIN SOCKET PROCESSOR

GMCH

ICH2

3 DIMM

Modules

AGP

Connector

Digital Video

Out Connector

PCI CONN 1

PCI CONN3

BLOCK DIAGRAM

FirmWare Hub

SIO

CNR

PCI CNTRL

PCI ADDR/DATA

AC’97 LINK

Keyboard

Mouse

Floppy Game Port Serial 1

GTL BUS

Audio

Codec

Connector

ParallelSerial 2

USB PORT 1-4

UDMA/100

PCI CONN 2

Note: PCI3

Connector is

not populated

on the board

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Block Diagram

233

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

370 - Pin Socket Part 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

370-pin Socket Part 1

333

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

HA#[3..31]

HD#[0..63]

HA#3

HD#55

HD#52

HD#41

HD#34

HD#33

HD#32

HD#25

HD#22

HD#12

HD#2

HA#27

HA#18

HA#11

HD#35

HD#10

HD#6

HA#16

HD#43

HD#31

HD#24

HA#12

HD#42

HD#20

HD#30

HD#29

HD#5

HD#3

HA#20

HD#60

HD#58

HD#48

HD#45

HD#40

HD#39

HD#28

HD#56

HD#36

HD#27

HD#21

HD#15

HA#29

HA#25

HA#22

HA#14

HA#9

HD#38

HD#1

HD#0

HA#13

HA#6

HA#5

HD#23

HD#4

HA#21

HA#19

HA#10

HA#8

HA#4

HD#50

HD#47

HD#44

HA#31

HA#28

HA#23

HD#62

HD#61

HD#57

HD#18

HD#16

HD#7

HD#59

HD#54

HD#53

HD#49

HD#37

HD#8

HA#30

HA#26

HD#63

HD#51

HD#46

HD#26

HD#11

HD#9

HA#17

HA#7

HA#24

HA#15

HD#19

HD#17

HD#14

HD#13

CPU_VID0

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

RS#17RS#27

RS#07

HA#[3..31] 7

HD#[0..63] 7

HREQ#1 7

HREQ#2 7

HREQ#3 7

HREQ#4 7

HREQ#0 7

JPR_VID0 29,32

JPR_VID4 29,32

JPR_VID2 29,32

JPR_VID3 29,32

JPR_VID1 29,32

VCCVID

VCC3_3

VTT

VTT

RP4

1K/8P4R

1

3

5

7 8

6

4

2

R372 1k

RP3

10K/8P4R

1

3

5

7 8

6

4

2

R371

10K

U3A

Socket 370_9

W1

T4

N1

M6

U1

S3

T6

J1

S1

P6

Q3

M4

Q1

L1

N3

U3

H4

R4

P4

H6

L3

G1

F8

G3

K6

E3

E1

F12

A5

A3

J3

C5

F6

C1

C7

B2

C9

A9

D8

D10

C15

D14

D12

A7

A11

C11

A21

A15

A17

C13

C25

A13

D16

A23

C21

C19

C27

A19

C23

C17

A25

A27

E25

F16

AH26

AH22

AK28

AM34

AH2

AD2

Z2

V2

M2

D18

H2

D2

AL3

AG5

AC5

Y5

U5

Q5

L5

G5

D4

B4

AM6

AJ7

E7

B8

AM10

AJ11

E11

B12

AM14

AJ15

E15

B16

AM18

AJ19

E19

F20

B20

AM22

AJ23

D22

F24

B24

AM26

AJ27

D26

F28

B28

AM30

D30

AF32

AB32

X32

T32

P32

F32

B32

AH34

AD34

Z34

V34

R34

M34

H34

D34

AK36

X36

T36

P36

K36

F36

A37

AC33

Y37

AK8

AH12

AH8

AN9

AL15

AH10

AL9

AH6

AK10

AN5

AL7

AK14

AL5

AN7

AE1

Z6

AG3

AC3

AJ1

AE3

AB6

AB4

AF6

Y3

AA1

AK6

Z4

AA3

AD4

X6

AC1

W3

AF4

AL35

AM36

AL37

AJ37

AK18

AH16

AH18

AL19

AL17

C33

C31

A33

A31

E31

C29

E29

A29

AH20

AK16

AL21

AN11

AN15

G35

AL13

U37

U35

S37

S33

E23

AN21

AA35

AA33

B26

C3

AK2

AF2

AB2

T2

P2

K2

F4

E5

AM4

AE5

AA5

W5

S5

N5

J5

F2

D6

B6

AM8

AJ9

E9

B10

AM12

AJ13

E13

B14

AM16

AJ5

AJ17

E17

B18

AM20

AJ21

D20

F22

AM24

AJ25

D24

F26

AM28

AJ29

D28

AK34

F30

B30

AM32

AH32

Z32

V32

R32

M32

H32

AF34

AB34

X34

T34

P34

K34

F34

B34

AH36

B22

V36

R36

H36

D36

D32

AD32

AH24

F14

K32

AA37

Y35

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#12

HD#13

HD#14

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#62

HD#63

RS#0

RS#1

RS#2

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND/VID4

GND

GND

GND

GND

GND

GND

GND

GND

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#10

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#29

HA#30

HA#31

HA#32

HA#33

HA#34

HA#35

VID0

VID1

VID2

VID3

REQ#0

REQ#1

REQ#2

REQ#3

REQ#4

DEP0#

DEP1#

DEP2#

DEP3#

DEP4#

DEP5#

DEP6#

DEP7#

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VTT1_5

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GTLREF Inputs ( 1 cap for every 2 inputs )

GTLREF Generation Circuit

Use 0603 Packages and distribute

370 - Pin Socket

within 500 mils of processor

Part2

Place Site w/in 0.5"

Do Not stuff C

of clock pin (W37)

Rds_on approx. 100

mOhm @5Vgs

CMOSREF generation circuitPlace near AB36

GTLREFA to CPU.

GTLREF to GMCH.

Debug only!

Debug only! Do NOT place

jumper before removing

R375

66M

10

100M

BSEL#1

0

BSEL#0

rsvd

FSB

0

1

1

1 133M

0

Debug sites only.

Do not stuff R330

Stuff resistor

only on non-UMB

platforms.

Tu

a

No-stuff R199 - see p.33.

Stuff either R5 or R415. See p33.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

370-pin Socket Part 2

433

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

GTLREFA

PLL2

SLEWCNTR

FLUSH#

RTTCNTR

PLL1

ITP_VTT

ITP_DBRESET

ITP_CPURESET

AG1_VTT/NC

GTLREFA

CMOSREF

TUALDET

NCHCTRLP

DYN_OE

RESET2#

A20M# 12

VTIN2 21,25

BPRI# 7

HITM# 7

BR0# 5

THRMDN 21,25

BNR# 7

FERR# 12

STPCLK# 12

INTR 12

HLOCK# 7

HTRDY# 7

IGNNE# 12

CPUSLP# 12

HIT# 7

NMI 12

DRDY# 7

BSEL#1 29,32

DEFER# 7

INIT# 12,17

HADS# 7

BSEL#0 29,32

SMI# 12

DBSY# 7

APICD112

CPUHCLK6APICCLK_CPU6

CPU_PWGD12,33

ITPRDY#5

ITPCLK6

GTLREF 7,32

VTTPWRGD26

APICD012

TUAL56,7,26

TUAL5#

TUAL5 6,7

CPURST#7,33

CMOSREF

GTLREFA 32

DBRESET#25

THERMTRIP# 33

N639540333

VCC2_5

VTT

VTT

V3SB

VCCVID

V3SB

VTT VCC2_5

VTT

VTT

VTT

VCC5

VCC5

VTT

VTT

VCMOS

Q27

FDN335N

Q26

2N3904

R344

1k

R338

75 1%

R406

1k

R339

150 1%

BC228

0.1uF

R343

2.2k

Q25

2N7002

R341

2.2k

R340

1k

R330 X0

R373330

FB30BEAD

1 2

R346

1k

PR7

75,1%

R8

330

PR1

56,%1

R33

90.9,1%

BC12

0.1UF

BC18

0.1UF

R199

1.8k R4

1K

C12

10PF

R5

39 R3

1K

R6

39

R7

150 R2

150

MC7

4.7UF

R13

330

BC1

0.1UF

R275

22

+

C6

33uF (C size)

BC16

0.1UF

BC7

0.1UF

R345 1k

R14

150

PR8

150,1%

PR5

110,%1

R1

150

PR6

150,1%

BC17

0.1UF

R15

150

PR4

150,1%

L2

4.7UH/SMD-0805

C3

X18PF

R315 0

R319

243,1%

J2

XHEADER_15X2

2 1

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

21

43

65

87

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

R9

680

R316 0

R317 0

R318 243,1%

R342 1k

R314

1K

U3B

Socket 370_9

X2

AG1

C37 E21

AJ33

AJ31

AN29

AL29

AL31

AH28

S35

W33

U33

E27

AN35

AN37

AN33

AL33

AK32

J37

A35

G33

E37

C35

E35

N33

N35

N37

Q33

Q35

Q37

AK30

AM2

F10

W35

Y1

R2

G37

L33

J35

L35

J33

W37

Y33

AK26

AH4

X4

AB36

AD36

Z36

E33

F18

K4

R6

V6

AD6

AK12

AK22

AH14

AN17

AN25

AN19

AK20

AN27

AL23

AL25

AL27

AN31

AE37

AE33

AG35

AH30

AJ35

M36

L37

AG33

AC35

AG37

AE35

AC37

AL11

AN13

AN23

B36

AK24

V4

AN3

AK4

AJ3 AF36

AL1

RESVD21(BR1#)

EDGCTRL/VRSEL

CPUPRES# VCOREDET

BSEL0#

BSEL1#

BR0#

THRMDN

THRMDP

THERMTRIP#

RTTCNTR

PLL1

PLL2

SLEWCNTR

TDI

TDO

TRST#

TCK

TMS

PREQ#

PRDY#

BP2#

BP3#

BPM0#

BPM1#

RSRVD6

RSRVD7

RSRVD8

RSRVD9

RSRVD10

RSRVD11

RSRVD12/JBSEL1#

RSRVD13

RSRVD15

RSRVD16

RSRVD17

RSRVD18

RSRVD19

RSRVD20

PICD0

PICD1

PICCLK

BCLK

CLKREF

PWRGOOD

RESET#

RESET2#

V_CMOS

V1_5

V2_5

VREF0

VREF1

VREF2

VREF3

VREF4

VREF5

VREF6

VREF7

BNR#

BPRI#

TRDY#

DEFER#

LOCK#

DRDY#

HITM#

HIT#

DBSY#

ADS#

FLUSH#

A20M#

STPCLK#

SLP#

SMI#

LINT0/INTR

LINT1/NMI

INIT#

FERR#

IGNNE#

IERR#

RSP#

AP0#

AP1#

RP#

BINIT#

AERR#

BERR#

DYN_OE

VTTPWRGD

RSVD - NC TUALDET

RSRVD21

R374

14

R375 0

JP6

JUMPER

C163

0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTT Decoupling

Debug cap sites - place near processor

Do not populate in assembly - debug sites only.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VTT Decoupling

533

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

ITPRDY# 4

BR0# 4

VTT

VTT

VTT

R12 150

R23 56

MC23

4.7UF

MC22

4.7UF

BC34

0.1UF

BC35

0.1UF

BC36

0.1UF

BC37

0.1UF

BC38

0.1UF

BC24

0.1UF

BC23

0.1UF

BC5

0.1UF

BC14

0.1UF

BC22

0.1UF

BC9

0.1UF

BC15

0.1UF

BC2

0.1UF

BC13

0.1UF

BC3

0.1UF

C164

820uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Clock power gate

Rds_on = 100 mOhm.

Ensure that the buffer used will disable

its PLL and tristate outputs when no

refclk is present; otherwise, must gate

power here, too.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Clock Generator

633

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

MEMV3PCIV3

L_VCC2_5

AV3 USBV3

PCLK_REF

MEMCLK4

MEMCLK1 MEMCLK8

MEMCLK5

MEMCLK11

MEMCLK6

MEMCLK0

MEMCLK11

MEMCLK7

MEMCLK10

MEMCLK[0..7]

MEMCLK9

MEMCLK8

MEMCLK4

MEMCLK3

MEMCLK2

MEMCLK1

MEMCLK0

MEMCLK2

MEMCLK10

MEMCLK5

MEMCLK6

MEMCLK3 MEMCLK7

MEMCLK9

MEMCLK[8..11]

AGPCLK_CONN11

ICH_3V6613 GMCH_3V668

SLP_S3#13,21,28

R_SMBDATA32 R_SMBCLK32

ICH_CLK1413

FMOD129

PCLK_0/ICH12

FMOD029

GMCHHCLK 7

SIO_CLK24 21

APICCLK_CPU 4

MEMCLK[8..11] 10

APICCLK_ICH 12

MEMCLK[0..7] 9

DCLK_WR 7

USBCLK 13

DOTCLK 8

PCLK_8 17

PCLK_2 14

PCLK_7 21

PCLK_3 15

PCLK_1 14

VTTPWRGD1226

TUAL5 4,7,26

ITPCLK 4

CPUHCLK 4

VCC2_5

VCC3_3

VCC_CLOCK

VCC_CLOCK

VCC_CLOCK

VCC_CLOCK

VCC3_3

VCC_CLOCK

BC227

0.1UF

BC226

0.01UF

MC18

4.7UF

PFB2

BEAD

1 2

BC31

0.1UF

BC32

0.01UF

BC56

0.1UF

BC55

0.01UF

PFB4

BEAD

1 2

BC59

0.01UF

BC57

0.01UF

BC58

0.1UF

BC62

0.01UF

BC61

0.1UF

MC29

4.7UF

MC28

4.7UF

PFB5

BEAD

1 2

R347

0

BC60

0.1UF

R348

130 Q28

2N7002

BC26

0.01UF

BC25

0.1UF

MC21

4.7UF

C33

18PF

C35

18PF

R58 33

R45 33

R46 33

RN19 22/8P4R

1

3

5

7

2

4

6

8

R57 33

R320 33

RN20 22/8P4R

1

3

5

7

2

4

6

8

R50 22

R62 22

R63 22

Y3

14.318MHZ

R44 22

R51 22

C19

X10PF

C21

X10PF

C20

X10PF

R277 33

CN4

X10P/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

CN5

X10P/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

C34

X10PF

C31

X10PF

C23

X10PF

C22

X10PF

CN6

X10P/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

C120

X10PF

C41

X10PF

C42

X10PF

C40

X10PF

C39

X10PF

U6

ICS9250-28

54

53

1

51

50

47

46

45

42

41

38

37

36

33

32

26

27

3

55

8

13

17

19

24

30

34

39

2

5

9

14

20

25

31

35

6

7

4

56

10

11

12

15

16

21

22

23

29

18

28

40

44

49

43

48

52

CPUCLK_0

CPUCLK_1

IOAPIC

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM7

SDRAM8

SDRAM9

SDRAM10

SDRAM11

48MHZ_0

48MHZ_1

GNDL

GNDL

GND

GND

GND

GND

GND

GND

GND

GND

VDDL

VDD

VDD

VDD

VDDA

VDD

VDD

VDD

X1

X2

REF0

VDDL

3V66-0

3V66-1

3V66-2

PCICLK0

PCICLK1

PD#

SCLK

SDATA

SDRAM12

FS0

FS1

VDD

VDD

VDD

GND

GND

GND

C29

X10PF

R64 33

R290 33

R67 33

R65 33

R66 33

R49 33

R47 33

RN34

33/8P4R

1

3

5

7

2

4

6

8

R48 33

C25

X10PF

C24

X10PF

C28

X10PF

C30

X10PF

C133

X10PF

Q29

FDN359AN

R72 10

PFB11

BEAD

1 2

R249 8.2K

U29

ICS9112B-17

1 6

7

10

11

16

12

5

4

13 2

3

14

15

9

8

REF CLKB1

CLKB2

CLKB3

CLKB4

CLKOUT

GND

GND

VDD

VDD CLKA1

CLKA2

CLKA3

CLKA4

FS1

FS2

R312 X33

C132

X18PF

R303

10K

R302

10K

PFB12

BEAD

1 2

BC222

0.01UF

BC221

0.1UF

MC66

4.7UF

R60 10

BC28

0.01UF

BC27

0.1UF

BC29

0.01UF

BC30

0.1UF

MC20

4.7UF

MC19

4.7UF

PFB1

BEAD

1 2

BC33

0.01UF

BC21

0.1UF

BC63

0.01UF

BC64

0.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Host Interface

SM_WE#

SM_MAA9

SM_CAS#

SBA7

SM_BS0

SM_BS1

SM_MAA10

SM_MAA11

SM_MAA12

SM_RAS#

Host Freq : HI=100 LO=66

FSB P-MOS Kicker : HI=NON-Cu LO=Cu

Host Freq : HI=133 LO=100/66

LM FREQ : HI=133 LO=100

SM/LM muxing strap , active low

IOQ depth : HI=4 LO=1

ALLZ : LO=ALLZ HI=Normal

XOR chain : LO=XOR HI=Normal

SYSTEM MEMORY

Do Not Stuff C

Place Site w/in

0.5" of clock

ball(v6)

Place close

to GMCH

Backside decouping , should be

placed under chipset memory signal

field

Backside decouping , should be

placed under chipset AGP signal

field

Debug sites only.

Place

near GMCH

LO = Future 0.13u Socket 370 processors

HI = Pentium(R) III Processor or Intel(R)

Celeron(tm) Processor w/CPUID = 068Xh

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

GMCH Part 1

733

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

HD#[0..63]

HA#[3..31]

HREQ#1

HD#61

HD#25

HREQ#0

HD#58

HD#57

HD#51

HD#33

HD#24

HD#13

HD#49

HD#32

HD#29

HA#31

HD#62

HD#48

HD#30

HD#9

HD#0

HA#30

HD#39

HD#10

HD#5

HD#4

RS#0

HD#53

HD#42

HD#28

HD#63

HD#55

HD#40

HD#26

HD#16

HD#8

HD#3

HD#38

HD#37

HD#1

HD#47

HD#43

HD#11

HD#56

HD#54

HD#44

HD#41

HD#27

HD#19

HA#29

HD#22

HREQ#4

HD#45

HD#23

HD#17

HD#14

HD#52

HD#46

HD#34

HD#20

HD#18

HD#2

HREQ#3

HD#60

HD#35

HD#31

HD#15

HD#7

HREQ#2

HD#59

HD#6

HD#50

HD#36

HD#21

HD#12

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#16

HA#12

HA#13

HA#11

HA#14

HA#10

HA#15

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#26

HA#27

HA#25

HA#28

HA#24

RS#2

RS#1

SM_MAA4

SM_MAA5

SM_MAA6

SM_MAA7

SM_MD28

SM_MD9

SM_MD6

SM_CKE1

SM_MAA11

SM_MAA3

SM_MD50

SM_MD42

SM_MD32

SM_MD7

SM_CSA#2

SM_MD54

SM_MD45

SM_MD15

SM_CSB#1

SM_MD61

SM_MD48

SM_MD16

SM_MD0

SM_CSA#0

SM_MAA0

SM_DQM5

SM_MD63

SM_MD36

SM_MD24

SM_MD19

SM_CSB#0

SM_MD41

SM_MD33

SM_MD21

SM_MD3

SM_CKE0

SM_CSB#3

SM_MAA8

SM_MD51

SM_MD35

SM_MD29

SM_MD13

SM_MD10

SM_CSA#1

SM_MAA12

SM_MAA2

SM_MD55

SM_MD53

SM_MD43

SM_MD12

SM_CKE3

SM_CSA#3

SM_MAA9

SM_DQM2

SM_MD59

SM_MD58

SM_MD56

SM_MD46

SM_MD2

SM_DQM4

SM_MD62

SM_MD37

SM_MD17

SM_MAA1

SM_DQM0

SM_MD39

SM_MD22

SM_DQM7

SM_MD34

SM_MD26

SM_MD1

SM_MD52

SM_MD40

SM_MD31

SM_MD30

SM_MD11

SM_MD8

SM_MD5

SM_CKE2

SM_CSB#2

SM_DQM1

SM_MD49

SM_MD44

SM_MD14

SM_MD4

SM_DQM3

SM_MD60

SM_MD57

SM_MD47

SM_MD23

SM_MD38

SM_MD27

SM_MD20

SM_MD18

SM_DQM6

SM_MD25

SM_MAA10

SM_MD[0..63]

SM_MAA[0..12]

SM_DQM[0..7]

SM_WE#

SM_MAB#[4..7]

SM_CKE[0..3]

SM_MAC#[4..7]

SM_MAC#7

SM_MAC#6

SM_MAB#5

SM_MAB#6

SM_MAC#4

SM_MAB#4

SM_MAB#7

SM_MAC#5

SM_CSA#4

SM_CSA#5

SM_CSB#5

SM_CSB#4

SM_CKE4

SM_CKE5

SM_CKE[4..5]

SM_CSA#[0..3]

SM_CSA#[4..5]

SM_CSB#[0..3]

SM_CSB#[4..5]

SM_MAA9

SM_CAS#

SM_MAA10

SM_RAS#

SM_MAA12

HD#[0..63] 3

CPURST#4,33 HLOCK#4DEFER#4

HADS# BNR#4 BPRI#4 DBSY#4 DRDY#4 HIT#4 HITM#4 HTRDY#4

HA#[3..31]3 SM_BS09,10 SM_BS19,10

SM_RAS#9,10 SM_CAS#9,10 SM_WE#9,10

DCLK_WR6

PCIRST#16,17,21,30

GMCHHCLK6

SM_MAA[0..12]9,10

SM_DQM[0..7]9,10

SM_MD[0..63] 9,10SM_MAB#[4..7]9

SM_CKE[0..3]9

SM_MAC#[4..7]10

SM_CKE[4..5]10

SM_CSA#[4..5]10

SM_CSA#[0..3]9

SM_CSB#[4..5]10

SM_CSB#[0..3]9

R_BSEL#0 29

R_REFCLK 29

HREQ#03 HREQ#13 HREQ#23 HREQ#33 HREQ#43

RS#03 RS#13 RS#23

GTLREF

3

2

TUAL54,6,26

VTT

VCC3SBY

VCC3SBY

VDDQ

VTT

VTT

BC72

0.1UF

BC73

0.1UF

C38

X18PF

RN37

10/8P4R

1

3

5

7

2

4

6

8

C36

22PF

PR9 40.2,1%

RN36 10/8P4R

1

3

5

7

2

4

6

8

RN38 10/8P4R

1

3

5

7

2

4

6

8

R68 X10K

R77 X10K

BC188

X0.1UF

BC190

X0.1UF

BC191

X0.1UF

BC189

X0.1UF

BC192

X0.1UF

BC193

X0.1UF

BC194

X0.1UF

BC195

X0.1UF

U7A

U6

AA10

AA7

H3

AA5

L4

M3

G1

N4

M5

J3

J1

K1

L3

K3

R4

P1

T2

R3

N5

P5

R1

U1

P2

T1

T3

P3

T5

R5

V5

Y2

V3

W1

U4

V2

W3

W4

U5

Y5

Y3

U3

Y1

W5

V1

M1

N1

M2

L5

N3

K2

L1

H1

AA1

AB2

AF2

AD4

AB1

AB3

AA3

AC4

AC1

AF3

AD1

AE3

AD2

AD3

AF1

AA4

AD6

AC3

AE1

AB6

AF4

AE5

AC8

AB5

AF5

AC6

AF6

AD11

AF8

AD8

AD5

AB7

AF7

AD7

AB8

AE7

AE9

AB9

AF9

AD10

AF12

AB11

AB10

AD9

AC10

AF10

AD14

AD12

AB12

AE11

AE15

AF11

AF13

AB14

AF14

AB13

AB15

AE13

AC14

AD13

AD15

AF16

AF15

AC12

GTLREFA

GTLREFB

HCLK

RESET#

CPURST#

HLOCK#

DEFER#

ADS#

BNR#

BPRI#

DBSY#

DRDY#

HIT#

HITM#

HTRDY#

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#10

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#29

HA#30

HA#31

HREQ#0

HREQ#1

HREQ#2

HREQ#3

HREQ#4

RS#0

RS#1

RS#2

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#12

HD#13

HD#14

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#62

HD#63

U7B

82815 GMCH

B13

D11

G7

D13

B16

F12

A16

B12

A12

C11

A11

D12

C13

E11

A13

B7

B15

A15

C14

A14

B10

A10

C10

A9

D15

A17

D14

E14

E13

B17

F9

F8

D10

D9

B9

A8

C16

D18

E16

D8

E8

E9

D7

C8

C7

F7

G10

D16

F15

A7

A6

A18

C17

B6

A5

D23

C23

D22

F21

E21

G20

F20

D20

F19

E19

D19

E18

B18

F18

G18

D17

A3

A1

C1

F2

G3

D6

C5

B4

D4

C2

D3

E4

F5

G4

J6

K5

A26

A25

B24

A24

B23

A23

C22

A22

D21

B21

A21

C20

B20

A20

C19

A19

A4

A2

B1

E1

G2

E6

D5

C4

B3

D2

E3

F4

F6

G5

H4

J4

SBS0

SBS1

SRCOMP

SMAA0

SMAA1

SMAA2

SMAA3

SMAA4

SMAA5

SMAA6

SMAA7

SMAA8

SMAA9

SMAA10

SMAA11

SMAA12

SMAB#4

SMAB#5

SMAB#6

SMAB#7

SMAC4

SMAC5

SMAC6

SMAC7

SCSA#0

SCSA#1

SCSA#2

SCSA#3

SCSA#4

SCSA#5

SCSB#0

SCSB#1

SCSB#2

SCSB#3

SCSB#4

SCSB#5

SRAS#

SCAS#

SWE#

SCKE0

SCKE1

SCKE2

SCKE3

SCKE4

SCKE5

SCLK

RESVD

SDQM0

SDQM1

SDQM2

SDQM3

SDQM4

SDQM5

SDQM6

SDQM7

SMD0

SMD1

SMD2

SMD3

SMD4

SMD5

SMD6

SMD7

SMD8

SMD9

SMD10

SMD11

SMD12

SMD13

SMD14

SMD15

SMD16

SMD17

SMD18

SMD19

SMD20

SMD21

SMD22

SMD23

SMD24

SMD25

SMD26

SMD27

SMD28

SMD29

SMD30

SMD31

SMD32

SMD33

SMD34

SMD35

SMD36

SMD37

SMD38

SMD39

SMD40

SMD41

SMD42

SMD43

SMD44

SMD45

SMD46

SMD47

SMD48

SMD49

SMD50

SMD51

SMD52

SMD53

SMD54

SMD55

SMD56

SMD57

SMD58

SMD59

SMD60

SMD61

SMD62

SMD63

R90 8.2K

R89 8.2K

R88 10K

FB31BEAD

1 2

PR42

63.4 1%

PR43

150,1%

R349

10k

Q30

2N7002

R407

56

C168

0.1uF R61

90.9,1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power and Ground

Display Cache, Video, and

HUB Interface

of clock ball(AA21)

Do Not Stuff C

Place as close as

Possible to GMCH

and via straight

to VSS plane

Place R as

Close as

possible to

GMCH

Place Site w/in 0.5"

OCLK = 0.5"

RCLK = 1.5"

NOTE :

Place as close as

Possible to GMCH

and via straight

to VSS plane

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

GMCH Part 2

833

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

GAD13

GAD15

GAD7

GAD26

GAD2

GAD5

GAD25

GAD21

GAD0

GAD23

GAD28

GAD22

GAD10

GAD24

GAD31

GAD20

GAD19

GAD18

GAD30

GAD16

GAD1

GAD3

GAD8

GAD29

GAD9

GAD17

GAD12

GAD14

GAD27

GAD6

GAD11

GAD4

GAD[0..31]

OCLK

RCLK

FTD7

FTD6

FTD11

FTD3

FTD2

HL7

HL9

FTD1

FTD5

HL5

HCOMP

HL4

HL10

HL2

FTD10

FTD9

FTD4

HL3

FTD8

HL0

HL6

SBA[0..7]

HL1

HL[0..10]

FTD[0..11]

FTD0

HL8

GRCOMP

HUBREF_GMCH

GAD[0..31]11

GCBE#011 GCBE#111 GCBE#211 GCBE#311

GDEVSEL#11 GFRAME#11

GIRDY#11 GTRDY#11 GSTOP#11 GPAR11 GREQ#11 GGNT#11 PIPE#11

ADSTB011 ADSTB0#11 ADSTB111 ADSTB1#11 SBSTB11 SBSTB#11

ST011 ST111 ST211

RBF#11 WBF#11

GMCH_AGPREF 11

FTCLK0 16

FTHSYNC 16

3VFTSCL 16

3VDDCCL 16

FTD[0..11] 16

VID_BLUE 16

VID_RED 16

CRT_HSYNC 16

HL[0..10] 12

SBA[0..7] 11

SL_STALL 16

HLSTB 12

FTBLNK# 16

FTVSYNC 16

CRT_VSYNC 16

HLSTB# 12

VID_GREEN 16

FTCLK1 16

3VFTSDA 16

3VDDCDA 16

GMCH_3V66 6

DOTCLK 6

CONN_AGPREF11,32

SBA0 11

SBA1 11

SBA2 11

SBA3 11

SBA4 11

SBA5 11

SBA6 11

SBA7 11

VDDQ

VCC1_8VCC3SBYVDDQ

VCC1_8

VCC1_8

VCC1_8

PR15

40.2,1%

PR14 15.1%

C61

15PF/5%,MPO

PR13

174,1%

PR23

1K,1%

PR21

82,1%

PR24

82,1%

PR22

1K,1%

C69

560PF

C72

560PF

PR16

301,1%

PR18

40.2,1%

C58

10PF

BC89

0.1UF

PR17

301,1%

BC90

0.1UF

U7D

82815 GMCH

AF24

AE25

W6

Y9

Y18

AA6

AA8

AA11

AA13

AA15

AA17

AA19

AB16

AB20

AC22

AD19

C25

E24

F23

G22

J7

K6

M6

P6

T6

V7

G26

AA21

Y7

E23

AF26

AF25

B2

B5

B8

B11

B14

B19

B22

B25

E2

F10

F14

F17

G6

G8

G19

H2

H5

H7

K20

Y24

L21

M23

U25

N25

R21

U20

U23

W20

AB4

E7

AC2

AC5

AC7

AC9

AC11

AC13

AC15

AC17

AC19

AC21

AC25

AE2

AE4

AE6

AE8

AE10

AE12

AE14

AE16

AE18

AE20

B26

C3

C6

C9

C12

C15

C18

C21

C24

D1

E5

E10

E12

E15

E17

E20

E22

F1

F3

F11

F13

T21

U2

U7

K24

V4

V6

V20

V22

W2

W7

W23

W25

Y4

Y6

Y8

Y10

Y17

Y19

AA2

AA9

AA12

AA14

AA16

GND

GND

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC_1.8

VCC1_8

VCC1_8

VCC1_8

VCC1_8

VCC1_8

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

U7E

Solano

P11

P12

P13

P14

P15

P16

R2

R6

R11

R12

R13

R14

R15

R16

R23

R25

T4

T11

T12

T13

T14

T15

T16

L15

L16

L22

M4

M11

M12

M13

M14

M15

M16

L25

N2

N6

N11

N12

N13

N14

N15

N16

N23

AA23

F16

F25

G9

G17

G21

G23

P24

H6

H22

J2

J5

J23

J25

K4

K7

K21

L2

L6

L11

L12

L13

L14

AA25

P4

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

R251 22

U7C

82815 GMCH

K26

J22

K25

J21

L24

J20

L26

K23

K22

M25

M24

M26

M21

N24

N22

N26

T26

T22

U24

T23

U26

T24

V24

U21

V25

V21

V26

W21

W24

W22

W26

Y21

H23

N21

T25

Y26

R26

P26

P23

P21

P25

R24

AE26

AD25

AC26

M22

L23

U22

V23

Y23

AA24

AD24

AC24

AC23

AD26

AB24

J24

J26

R22

P22

AD16

AF17

AE17

AD17

AF18

AD18

AF20

AD20

AC20

AF21

AE21

AD21

AB19

AC18

AE19

AF19

AC16

AB17

AB21

AA20

AA18

AB18

AE24

Y20

AD23

AF22

AF23

AD22

AE22

AE23

F22

H24

H26

H25

G24

F24

E26

E25

D26

D25

D24

C26

H21

G25

F26

H20

AB22

AB25

AB23

AB26

AA22

AA26

Y22

Y25

GAD0/LDQM0

GAD1/LMD4

GAD2/LMD7

GAD3/LMD3

GAD4/LMD6

GAD5/LMD2

GAD6/LMD5

GAD7/LMD1

GAD8/LMD0

GAD9/LMA4

GAD10/LDQM1

GAD11/LMA2

GAD12/LMD8

GAD13/LMA5

GAD14/LMD9

GAD15/LMA1

GAD/16/LMA8

GAD17/LMD14

GAD18/LMA11

GAD19/LMD15

GAD20/LMA9

GAD21/LMD16

GAD22/LCS#

GAD23/LMD17

GAD24/LCKE

GAD25/LMD18

GAD26/LCAS#

GAD27/LMD19

GAD28/LTCLK1

GAD29/LMD20

GAD30/LTCLK0

GAD31/LMD21

GCBE#0/LMA3

GCBE#1/LMD10

GCBE#2/LMD13

GCBE#3/LRDS#

GFRAME#/LMA10

GDEVSEL#/LMD11

GIRDY#/LMD12

GTRDY#/LMA7

GSTOP#/LMA0

GPAR/LMA6

GREQ#/LMD27

GGNT#

PIPE#/LMD24

ADSTB0

ADSTB0#

ADSTB1

ADSTB1#

SBSTB

SBSTB#

ST0/LMD28

ST1/LDQM3

ST2/LMD29

RBF#/LMD30

WBF#

AGPREF

GRCOMP

OCLOCK

RCLOCK

LTVDATA0

LTVDATA1

LTVDATA2

LTVDATA3

LTVDATA4

LTVDATA5

LTVDATA6

LTVDATA7

LTVDATA8

LTVDATA9

LTVDATA10

LTVDATA11

BLANK#

TVCLKIN/SL_STALL

CLKOUT0

CLKOUT1

TVVSYNC

TVHSYNC

LTVCK

LTVDA

DDDA

DDCK

DCLKREF

IWASTE

IREF

VSYNC

HSYNC

RED

GREEN

BLUE

HCLK

HL0

HL1

HL2

HL3

HL4

HL5

HL6

HL7

HL8

HL9

HL10

HUBREF

HLSTB

HLSTB#

HCOMP

SBA0/LMD31

SBA1/LMD25

SBA2/LDQM2

SBA3/LMD26

SBA4/LMD23

SBA5/LWE#

SBA6/LMD22

SBA7/LGM_FREQ_SEL

L6 22nH

C169

33uF

C170

0.1uF

C171

0.01uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CH6-12

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

DIMMs 1 and 2

933

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

SM_CKE0

SM_MAA2 SM_MAA2

SM_DQM7

SM_MD48

SM_MD29

SM_BS0

SM_DQM5

SM_MD55

SM_MD2

SM_MAA0

SM_CKE2

SM_MD44

SM_MD39

SM_MD41

SM_MD57

SM_MD34

SM_MD40

SM_MD56

SM_MD21

MEMCLK6

SM_MD8

SM_MD4

SM_CKE3

MEMCLK1

SM_DQM2

SM_MD37

SM_MD32

SM_MD17

SM_MD36

SM_MD15

SM_MAB#6

SM_MD52

SM_CSA#0

SM_MD12

SM_MD24

SM_MD19

SM_MD3

SM_MD60

SM_MAA11

SM_MD27

SM_CSA#2

SM_MD31

SM_CAS#

SM_MAA10

SM_MD54

SM_MD16

SM_MAB#4

SM_MAA3

SM_MD44

MEMCLK0

SM_MD49

SM_DQM4

SM_CSB#2

SM_MD51

SMBDATA

SM_MD46

SM_RAS#

SM_MD15

SM_MD20

SM_MD61

SM_MD20

SM_MD63

SM_CSB#1

SM_DQM1

SM_MD51

SM_MD32

SM_MD58

MEMCLK4

SM_MD18

SM_MD57

SM_MD9

SM_MAA1

SM_MAB#5

SM_MD10

SM_MD27

SM_MD18

SM_DQM6

SM_MD23

SM_MD17

SM_MD5

SM_MD24

SM_MD42

SM_MD34

SM_MD62

SM_MD11 SM_MD43

SM_MD25

SM_MD59

SM_MAA9

SM_CSA#1

SM_MD8

SM_MD1

SM_MD5

SM_MD26

SM_MAA8

SM_MD21

SM_MD42

SM_MD6

SM_MD12 SM_MD45

SM_MD54

SM_CSB#3

SM_MD3

SM_MD14

SM_DQM5

SM_CSB#0

SM_MD56

SM_WE#

SM_MAA8

SM_MD35

SM_DQM4

SM_MD60

SM_MD45

SM_MD26

SM_MD48

SM_MAA12

SM_MD25

SM_MD61

SM_MAA7

SM_MD10

SM_MD40

SM_WE#

SM_MD41

SM_MD22

SM_BS0

MEMCLK7MEMCLK3

SM_MD55

SM_MAA1

SM_MD35

SM_DQM7

SM_MD38

SM_MD39

SM_MD19

SM_MAA9

SM_MD7

SM_CSA#3

SM_MD47

SM_RAS#

SMBDATA

SM_MD62

SM_MAA12

MEMCLK2

SM_MD53

SM_MAA10

SM_MD7

SM_MD0

SM_CAS#

SM_MAA4

SM_CKE1

SM_MD2

SM_MD14

SM_MD22

SM_MAA11

SM_MD13

SM_MD23

SM_MAA6

SM_MD28

SM_MD58

SM_MD50

SM_MD4

SM_MAA0

SM_DQM6

MEMCLK5

SM_DQM3

SM_MAA3

SM_MD30

SM_MAA5

SM_MD47

SM_MD46

SM_MD50

SM_MD0

SM_MD63

SM_MD6

SM_MD36

SM_BS1

SM_DQM0

SM_MD43

SM_MD28

SMBCLK

SM_MD13

SMBCLK

SM_MD33

SM_MAB#7

SM_MD30

SM_MD16

SM_MD38

SM_MD52

SM_DQM3

SM_MD49

SM_MD9

SM_DQM2

SM_DQM1

SM_MD29

SM_MD37

SM_MD31

SM_MD59

SM_MD11

SM_MD53

SM_BS1

SM_DQM0

SM_MD1SM_MD33

MEMCLK[0..7]

SM_CKE[0..3]

SM_CSA#[0..3]

SM_CSB#[0..3]

SM_DQM[0..7]

SM_MAB#[4..7]

SM_MD[0..63]

SM_MAA[0..12]

SM_WE#

SM_RAS#

SM_CAS#

SM_BS0

SM_BS1

SMBDATA

SMBCLK

DM_SA_PU 10

SM_MAA[0..12] 7,10

SM_MD[0..63] 7,10

SM_MAB#[4..7] 7

SM_DQM[0..7] 7,10

MEMCLK[0..7] 6

SM_CKE[0..3] 7

SM_CSA#[0..3] 7

SM_CSB#[0..3] 7

SM_WE# 7,10

SM_RAS# 7,10

SM_CAS# 7,10

SM_BS0 7,10

SM_BS1 7,10

SMBDATA 10,13,21,24,30,32

SMBCLK 10,13,21,24,30,32

VCC3SBY

VCC3SBY VCC3SBYVCC3SBYVCC3SBY

R28 2.2K

DIMM2

DIMM168

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

108

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VDD

DQ14

DQ15

CB0

CB1

VSS

CB8

CB9

VDD

WE#/WE0#

DQM0

DQM1

CS0#

DU/OE0#

VSS

A0

A2

A4

A6

A8

A10/AP

BA1/A12

VDD

VDD

CLK0/DU

VSS

DU/OE2#

CS2#

DQM2

DQM3

DU/WE2#

VDD

CB10

CB11

CB2

CB3

VSS

DQ16

DQ17

DQ18

DQ19

VDD

DQ20

NC

VREF/DU

CKE1

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VDD

DQ28

DQ29

DQ30

DQ31

VSS

CLK2/NC

NC

WP

SDA

SCL

VDD

VSS

DQ32

DQ33

DQ34

DQ35

VDD

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VDD

DQ46

DQ47

CB4

CB5

VSS

CB13

VDD

CAS#/DU

DQM4

DQM5

CS1#

RAS#/DU

VSS

A1

A3

A5

A7

A9

BA0/A11

A11/A13

VDD

CLK1/DU

A12/DU

VSS

CKE0/DU

CS3#

DQM6

DQM7

A13/DU

VDD

CB14

CB15

CB6

CB7

VSS

DQ48

DQ49

DQ50

DQ51

VDD

DQ52

NC

VREF/DU

REGE

VSS

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

VDD

DQ60

DQ61

DQ62

DQ63

VSS

CLK3/NC

NC

SA0

SA1

SA2

VDD

CB12

DIMM1

DIMM168

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

108

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VDD

DQ14

DQ15

CB0

CB1

VSS

CB8

CB9

VDD

WE#/WE0#

DQM0

DQM1

CS0#

DU/OE0#

VSS

A0

A2

A4

A6

A8

A10/AP

BA1/A12

VDD

VDD

CLK0/DU

VSS

DU/OE2#

CS2#

DQM2

DQM3

DU/WE2#

VDD

CB10

CB11

CB2

CB3

VSS

DQ16

DQ17

DQ18

DQ19

VDD

DQ20

NC

VREF/DU

CKE1

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VDD

DQ28

DQ29

DQ30

DQ31

VSS

CLK2/NC

NC

WP

SDA

SCL

VDD

VSS

DQ32

DQ33

DQ34

DQ35

VDD

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VDD

DQ46

DQ47

CB4

CB5

VSS

CB13

VDD

CAS#/DU

DQM4

DQM5

CS1#

RAS#/DU

VSS

A1

A3

A5

A7

A9

BA0/A11

A11/A13

VDD

CLK1/DU

A12/DU

VSS

CKE0/DU

CS3#

DQM6

DQM7

A13/DU

VDD

CB14

CB15

CB6

CB7

VSS

DQ48

DQ49

DQ50

DQ51

VDD

DQ52

NC

VREF/DU

REGE

VSS

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

VDD

DQ60

DQ61

DQ62

DQ63

VSS

CLK3/NC

NC

SA0

SA1

SA2

VDD

CB12

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

DIMM 3

10 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

SM_MD[0..63]

SM_CSB#[4..5]

SM_MAA[0..12]

SM_CKE[4..5]

SM_CSA#[4..5]

SM_DQM[0..7]

SM_MAC#[4..7]

SM_CSA#4

SM_MD56

SM_MAA11

SM_MD49

SM_MD61

SM_MD38

SM_MD19

SM_MAA10 SM_MAA9

SMBDATA

SM_MD12

SM_MD10

SM_MD34

SM_MD46

SM_MD35

SM_MD45

SM_MD18

SM_DQM5

SM_BS1

SM_DQM2

SM_MD39

SM_MD44

SM_MD55

SM_MD43

SM_MD53

SM_MD8

SM_MAA2

SM_MD6

SM_MD5

SM_MD7

SM_MD15

SM_MD29

SM_CSB#4

SM_DQM7

SM_MAC#4

SM_MD4

SM_MAC#5

SM_MD13

SM_MD36

SM_CSB#5

SM_MD21

SM_MD11

SM_CKE4

SM_MD63

SM_DQM4

MEMCLK9

SM_MD16

SM_MD28

SM_MD27

SM_DQM3

SM_MAA0 SM_MAA3

SM_MD40

MEMCLK8

SM_MAC#6

SM_DQM0

SM_MD60

SM_MD22

MEMCLK10

SM_MD20

SM_MAA1

SM_MD23

SM_MD0

SM_MD1

SM_WE#

SM_BS0

SM_MD54

SM_MD59

SM_MD32

SM_MD58

SM_MD42

SM_MD31

SM_MAC#7

SM_MD62

SM_MD9

SM_MD51

SM_MD2

SM_CSA#5

SM_MD30

SM_MAA8

SM_MD41

SM_MD52

SM_DQM1

SM_MD26

SM_MD17

SM_MD47

MEMCLK11

SM_MD14

SM_MD48

SMBCLK

SM_CKE5

SM_MD25

SM_MD50

SM_MAA12

SM_MD57

SM_MD37

SM_MD3

SM_MD24

SM_DQM6

SM_MD33

SMBDATA

SM_RAS#

SM_CAS#

SM_BS1

SMBCLK

SM_WE#

SM_BS0

MEMCLK[8..11]

SM_CAS#

SM_RAS#

SM_BS07,9

SM_BS17,9

SM_CAS#7,9

SM_CSB#[4..5]7

SM_WE#7,9

SM_CSA#[4..5]7

SM_MD[0..63]7,9

SM_MAC#[4..7]7

SM_DQM[0..7]7,9

SM_RAS#7,9

SM_MAA[0..12]7,9

SMBCLK9,13,21,24,30,32 SMBDATA9,13,21,24,30,32

DM_SA_PU9

MEMCLK[8..11]6

SM_CKE[4..5]7

VCC3SBY VCC3SBY

DIMM3

DIMM168

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

108

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VDD

DQ14

DQ15

CB0

CB1

VSS

CB8

CB9

VDD

WE#/WE0#

DQM0

DQM1

CS0#

DU/OE0#

VSS

A0

A2

A4

A6

A8

A10/AP

BA1/A12

VDD

VDD

CLK0/DU

VSS

DU/OE2#

CS2#

DQM2

DQM3

DU/WE2#

VDD

CB10

CB11

CB2

CB3

VSS

DQ16

DQ17

DQ18

DQ19

VDD

DQ20

NC

VREF/DU

CKE1

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VDD

DQ28

DQ29

DQ30

DQ31

VSS

CLK2/NC

NC

WP

SDA

SCL

VDD

VSS

DQ32

DQ33

DQ34

DQ35

VDD

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VDD

DQ46

DQ47

CB4

CB5

VSS

CB13

VDD

CAS#/DU

DQM4

DQM5

CS1#

RAS#/DU

VSS

A1

A3

A5

A7

A9

BA0/A11

A11/A13

VDD

CLK1/DU

A12/DU

VSS

CKE0/DU

CS3#

DQM6

DQM7

A13/DU

VDD

CB14

CB15

CB6

CB7

VSS

DQ48

DQ49

DQ50

DQ51

VDD

DQ52

NC

VREF/DU

REGE

VSS

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

VDD

DQ60

DQ61

DQ62

DQ63

VSS

CLK3/NC

NC

SA0

SA1

SA2

VDD

CB12

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CH6-18

Place close

to GMCH

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

AGP

11 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

GREQ# GGNT#

ST0 ST1

ST2 PIPE#

WBF#

SBA0 SBA1

SBA2 SBA3

SBSTB SBSTB1#

SBA4 SBA5

SBA6 SBA7

ADSTB1 ADSTB1#

GIRDY# GFRAME#

GDEVSEL# GTRDY#

GSTOP#

GPERR#

GSERR# GPAR

ADSTB0 ADSTB0#

GFRAME#

GPERR#

PIPE#

WBF#

ADSTB1

ADSTB1#

ADSTB0

GAD[0..31]

GAD2

GAD25

GAD23

GAD19

GAD12

GAD5

GAD21

GAD18

GAD13

GAD9

GAD1

GAD22

GAD20

GAD11

GAD4

GAD16

GAD7

GAD8

GAD27

GAD31

GAD29

GAD0

SBA[0..7]

GAD6

GAD17

GAD3

GAD14

GAD15

GAD10

GAD30

GAD28

GAD26

GAD24

SBA0

SBA1

SBA2

SBA3

ADSTB0#

GSERR#

GDEVSEL#

GPAR

GTRDY#

GIRDY#

GSTOP#

ST0

GREQ#

ST1

GGNT#

ST2

SBA7

SBA6

SBSTB

SBSTB#

SBA4

SBA5

RBF#

RBF#

CON_AGPREF

AGPUSBN 18

PIRQ#A 14,15,30

GGNT# 8

ST1 8

PIPE# 8

TYPEDET# 26

PCI_RST# 14,15,30

GFRAME# 8

GTRDY# 8

GSTOP# 8

PCI_PME# 12,14,15,22

GPAR 8

GCBE#0 8

ADSTB0# 8

ADSTB1# 8

WBF# 8

SBSTB# 8

GCBE#3 8

AGP_OC#18

AGPUSBP18

PIRQ#B14,15,30

AGPCLK_CONN6GREQ#8

ST08ST28

RBF#8

SBSTB8

ADSTB18

GCBE#28

GIRDY#8

GDEVSEL#8

GCBE#18

ADSTB08

GMCH_AGPREF8

GAD[0..31]8

SBA[0..7]8

CONN_AGPREF 8,32

VDDQ

V3SB

VCC3_3

VCC5 VCC12

VDDQ

VCC12

VDDQ

R3358.2K

R3328.2K R3338.2K R3348.2K

PR20

301,1%

Q13

2N7002

AGP1

AGP4XU_20

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

OVRCNT#

5V_A

5V_B

USB+

GND_K

INTB#

CLK

REQ#/DQ27

VCC3.3_F

ST0/DQ28

ST2/DQ29

RBF#/DQ30

GND_L

RESV_H

SBA0/DQ31

VCC3.3_G

SBA2/DQM2

SB_STB

GND_M

SBA4/DQ23

SBA6/DQ22

RESV

GND_N

3.3VAUX1

VCC3.3_H

AD31/DQ21

AD29/DQ20

VCC3.3_I

AD27/DQ19

AD25/DQ18

GND_O

AD_STB1

AD23/DQ17

VDDQ_F

AD21/DQ16

AD19/DQ15

GND_P

AD17/DQ14

C/BE2#/DQ13

VDDQ_G

IRDY#/DQ12

3.3VAUX2

GND_Q

RESV_K

VCC3.3_J

DEVSEL#/DQ11

VDDQ_H

PERR#

GND_R

SERR#

C/BE1#/DQ10

VDDQ_I

AD14/DQ9

AD12/DQ8

GND_S

AD10/DQM1

AD8/DQ0

VDDQ_J

AD_STB0

AD7/DQ1

GND_T

AD5/DQ2

AD3/DQ3

VDDQ_K

AD1/DQ4

VREF_CG

12V

TYPEDET#

RESV_A

USB-

GND_A

INTA#

RST#

GNT#

VCC3.3_A

DQM3/ST1

RESV_B

DQ24/PIPE#

GND_B

WBF#

DQ25/SBA1

VCC3.3_B

DQ26/SBA3

SB_STB#

GND_C

WE#/SBA5

M_FREQ_SEL/SBA7

RESV_C

GND_D

RESV_D

VCC3.3_C

TCLK0/AD30

TCLK1/AD28

VCC3.3_D

CAS#/AD26

AD24

GND_E

AD_STB1#

RAS#/C/BE3#

VDDQ_A

A0/AD22

A9/AD20

GND_F

A11/AD18

A8/AD16

VDDQ_B

A10/FRAME#

RESV_E

GND_G

RESV_F

VCC3.3_E

A7/TRDY#

CS#/STOP#

PME#

GND_H

A6/PAR

A1/AD15

VDDQ_C

A5/AD13

A2/AD11

GND_I

A4/AD9

A3/C/BE0#

VDDQ_D

AD_STB0#

DQ5/AD6

GND_J

DQ6/AD4

DQ7/AD2

VDDQ_E

DQM0/AD0

VREF_GC

PR19

200,1%

RN49

8.2K/8P4R

1

3

5

7

2

4

6

8

RN48

8.2K/8P4R

1

3

5

7

2

4

6

8

RN43

8.2K/8P4R

1

3

5

7

2

4

6

8

RN44

8.2K/8P4R

1

3

5

7

2

4

6

8

RN46

8.2K/8P4R

1

3

5

7

2

4

6

8

RN45

8.2K/8P4R

1

3

5

7

2

4

6

8

R106

2.2K

RN42

8.2K/8P4R

1

3

5

7

2

4

6

8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NPOP

Place R as

Close as

possible to

ICH

Place as close as

Possible to ICH

and via straight

to VSS plane

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ICH2 Part 1

12 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

AD[0..31]

HL[0..10]

HL10

HL4

HL9

HUBREF_ICH

HL2

HL1

HL8

HL0

HL5

HL7

HL3

HL6

AD24

AD23

AD20

AD17

AD9

AD22

AD10

AD12

AD26

AD25

AD1

AD4

AD28

AD3

AD2

AD27

AD19

AD8

AD31

AD11

AD30

AD15

AD0

AD13

AD14

AD6

AD29

AD16

AD21

AD18

AD7

AD5

U12_RN69-1

U12_RN69-7

U12_RN69-3

U12_RN69-5

AD[0..31]14,15

IGNNE# 4

A20M# 4

STPCLK# 4

SMI# 4

KBRST# 21,30

CPUSLP# 4

NMI 4

INIT# 4,17

INTR 4

FERR# 4

ICH_IRQ#D 30

ICH_IRQ#B 30

ICH_IRQ#C 30

CPU_PWGD 4,33

HLSTB# 8

IRQ15 17

IRQ14 17

SERIRQ 21,30

PREQ#5 30

PGNT#1 14

APICD1 4

PGNT#2 15

PREQ#0 14,30

HLSTB 8

PREQ#4 30

APICD0 4

PREQ#2 15,30

PREQ#1 14,30

PREQ#3 30

APICCLK_ICH 6

PGNT#0 14

HL[0..10] 8

ICH_IRQ#A 30

PCLK_0/ICH6

PCI_PME#11,14,15,22

C_BE#014,15

ICH_IRQ#F30

C_BE#114,15

IRDY#14,15,30

PAR14,15

ICH_IRQ#H30

FRAME#14,15,30

GPIO2730

TRDY#14,15,30

PERR#14,15,30

DEVSEL#14,15,30

PLOCK#14,15,30 ICHRST#30

ICH_IRQ#G30

C_BE#214,15

STOP#14,15,30

ICH_IRQ#E30

SERR#14,15,30

C_BE#314,15

PCI_REQ#A30

P66DET17

GPIO2317

LAN_RXD0 24

LAN_RXD1 24

LAN_RXD2 24

LAN_TXD0 24

LAN_CLK 24

LAN_RSTSYNC 24

LPC_PME#21,30 EXTSMI#24 GPI830 S66DET17

LAN_TXD2 24

PRI_DWN#24,29

HUBREF_ICH 32

LAN_TXD1 24

A20GATE 21,30

VCC1_8

VCC1_8

V1_8SBV3SB V3SBVCC1_8 V3SBVCC3_3 V1_8SBVCC1_8

U12A

82801BA ICH2

AA4

AB4

Y4

W5

W4

Y5

AB3

AA5

AB5

Y3

W6

W3

Y6

Y2

AA6

Y1

V2

AA8

V1

AB8

U4

W9

U3

Y9

U2

AB9

U1

W10

T4

Y10

T3

AA10

AA3

AB6

Y8

AA9

W11

V3

AB7

W8

V4

W1

AA15

AA7

W2

W7

Y15

M3

L2

E14

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18

R5

T5

U5

V5

D11

A12

R22

A11

C12

C11

B11

B12

C10

B13

C13

A4

B5

A5

B6

B7

A8

B8

A9

C8

C6

C7

A6

A7

A3

B4

P1

P2

P3

N4

F21

C16

N20

N19

P22

N21

R2

R3

T1

AB10

M2

M1

R4

T2

D10

E5

K19

L19

P5

V9

D2

Y7

N3

N2

N1

AA11

Y14

W14

AB15

A15

D14

C14

L1

B14

A14

AB14

AA14

A13

C5

M4

P4

L3

R1

L4

A1

A10

A2

A21

A22

AA1

AA2

AA21

AA22

AB1

AB2

AB21

AB22

B1

B10

B2

B21

B22

B3

B9

C2

C3

C4

C9

D3

D5

D6

D7

D8

D9

E6

E7

E8

E9

J10

J11

J12

J13

J14

J9

K1

K10

K11

K12

K13

K14

K9

L10

L11

L12

L13

L14

L9

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P9

P10

P11

P12

P13

P14

G2

G1

H1

F3

F2

F1

G3

H2

V6

V7

V8

U18

T18

F5

G5

V17

V18

V14

V15

V16

H5

J5

Y11

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

C_BE#0

C_BE#1

C_BE#2

C_BE#3

PCICLK

FRAME#

DEVSEL#

IRDY#

TRDY#

STOP#

PCIRST#

PLOCK#

PAR

SERR#

PCI_PME#

REQ#A/GPI0

GNT#A/GPO16

VCC3_3_2

VCC3_3_3

VCC3_3_4

VCC3_3_5

VCC3_3_6

VCC3_3_7

VCC3_3_8

VCC3_3_10

VCC3_3_11

VCC3_3_12

VCC3_3_13

VCC3_3_14

VCC3_3_15

VCC3_3_16

VCC3_3_17

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

HL0

HL1

HL2

HL3

HL4

HL5

HL6

HL7

HL8

HL9

HL10

HLSTB

HLSTB#

HCOMP

HUBREF

PIRQ#A

PIRQ#B

PIRQ#C

PIRQ#D

IRQ14

IRQ15

APICCLK

APICD1

APICD0

SERIRQ

REQ#0

REQ#1

REQ#2

REQ#3

GNT#0

GNT#1

GNT#2

GNT#3

VCC1_8_1

VCC1_8_2

VCC1_8_3

VCC1_8_4

VCC1_8_5

VCC1_8_6

VCCA

PERR#

PIRQ#E/GPI2

PIRQ#F/GPI3

PIRQ#G/GPI4

GPI7

GPI8

GPI12

GPI13

GPO18

GPO19

GPO20

GPO21

GPOD22

GPO23

GPIOD27

GPIOD28

CPUPWRGOD

HL11

PIRQ#H/GPI5

REQ#4

REQ#B/GPI1/REQ#5

GNT#4

GNT#B/GPO17/GNT#5

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

LAN_RXD0

LAN_RXD1

LAN_RXD2

LAN_TXD0

LAN_TXD1

LAN_TXD2

LAN_CLK

LAN_RSTSYNC

VCC3_3_18

VCC3_3_19

VCC3_3_20

VCCPS1

VCCPS2

VCCPX1

VCCPX2

VCCUSB1

VCCUSB2

VCCCS1

VCCCS2

VCCCS3

VCCAX1

VCCAX2

GPI6

C101

10PF

PR25

301,1%

PR26

301,1%

PR27

40.2,1%

BC119

0.01UF

RN69 22/8P4R

1

3

5

7

2

4

6

8

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Target 20ms after

VCC_CLOCK is

powered

Debug only - do

not stuff

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ICH2 Part 2

13 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

PDA0

SDA0

PDD5

PDD6

SDD1

SDD0

SDD4

PDD1

PDD7

PDD11

SDD10

SDD14

PDD2

SDD7

PDA2

SDD12

SDD2

SDD5

PDD4

SDA2

PDD8

PDD12

PDA1

SDA1

PDD13

SDD3

SDD13

PDD14

PDD15

SDD11

SDD15

PDD9

PDD10

SDD8

SDD6

SDD9

PDD0

PDD3

SDD[0..15]

PDD[0..15]

RTCX1

VBIAS

RTCX2

RTCRST#

PDA[0..2]

SDA[0..2]

R174_JP1

ICH_PWROK SDCS#1 17

AC_RST#24,29

SDCS#3 17

PDIOR# 17

PDIOW# 17

AC_SDIN124,30

SDDACK# 17

SDIOW# 17

PDREQ 17

SDIOR# 17

PIORDY 17

PDCS#1 17

AC_SDIN019,24,30

AC_BITCLK19,24

PDCS#3 17

SIORDY 17

PDDACK# 17

SDREQ 17

USBCLK6ICH_3V666

ICH_SPKR19,24,29

AC_SYNC19,24

SDD[0..15] 17

PDD[0..15] 17

ICH_RI#22,30

SLP_S3#6,21,28

PWRBTN#21,33

OVT#21,30

SLP_S5#28

RSMRST#21

LAD317,21 LAD217,21

LDRQ#021

LFRAME#17,21

LAD117,21 LAD017,21

SMBALERT#30

SMBDATA9,10,21,24,30,32 SMBCLK9,10,21,24,30,32

SUSCLK21

USBP1P18 USBP1N18

USBP0N18

USBP2P18

USBP3P18 USBP3N18

USBP2N18

EE_CS24

EE_SHCLK24 SMLINK1 15,30

SMLINK0 15,30

USBP0P18

USBOC#0-118

AC_SDOUT19,24,29

ICH_CLK146

PDA[0..2] 17

SDA[0..2] 17

USBOC#2-318

CASEOPEN#21,25

GPIO2530

EE_DOUT24 EE_DIN24

PWROK21,25

VRM_PWRGD 27

VCC5

VCC3_3

VCC5

VCCRTC VCC5SBY

V3SB

V3SB

VCC3_3

VCC_CLOCK

VCC3_3 VCMOS

VCC3_3

BC197

0.1UF

R325 1K

D19

BAT54C

1

2

3

1

2

3

R324 1K

D18

SS12/SMD

R403

1K

BC125

0.1UF

C91

1.0UF

CP2

47PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

RN70 15/8P4R

1

3

5

7

2

4

6

8

R129 1K

CP1

47PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

RN71 15/8P4R

1

3

5

7

2

4

6

8

C88

X18PF

C113

1.0UF

BAT1

BATTERY

C103

18PF

C104

1.0UF

R149 10M

C110

0.047UF

R181 1K

Y2

32.768KHZ

R162

10M

C102

18PF

R187

1K

R174 15K JP1

CCM0S

1

3

2

Q16

2N7002

U33

741G08 AND

1

2

3

4

5

A

B

GND

Y

Vcc

R141 10 C96

X10P

R134 1K

D8 SS12/SMD

D12

SS12/SMD

R164

560K

R271

560K

U12B

82801BA ICH2

AA13

W16

AB18

R20

W21

AA17

R21

Y17

AA16

AB16

AB17

T19

M19

P20

D4

T21

U22

T22

T20

V22

P19

R19

P21

Y22

W22

N22

Y12

W12

AB13

AB12

AB11

Y13

W13

AB19

AA19

W17

Y18

Y20

W19

E21

C15

E19

D15

F20

F19

E22

A16

D16

B16

G22

B18

F22

B17

G19

D17

G21

C17

G20

A17

H19

H22

J19

J22

K21

L20

M21

M22

L22

L21

K22

K20

J21

J20

H21

H20

D18

B19

D19

A20

C20

C21

D22

E20

D21

C22

D20

B20

C19

A19

C18

A18

U21

M20

K2

V19

D13

D12

W15

V21

Y16

W18

Y19

AB20

AA20

Y21

W20

K4

K3

J4

J3 U19

V20

B15

U20

AA18

AA12

THRM#

SLP_S3#

SLP_S5#

PWROK

PWRBTN#

RI#

RSMRST#

SUS_STAT#

SMBDATA

SMBCLK

SMBALTER#/GPI11

INTRUDER#

CLK14

CLK48

CLK66

VBIAS

RTCX1

RTCX2

RTCRST#

AC_RST#

AC_SYNC

AC_BITCLK

AC_SDOUT

AC_SDIN0

AC_SDIN1

SPKR

LAD0/FWH0

LAD1/FWH1

LAD2/FWH2

LAD3/FWH3

LFRAME#/FWH4

LDRQ#0

LDRQ#1

USBP1P

USBP1N

USBP0P

USBP0N

OC#1

OC#0

PDCS#1

SDCS#1

PDSC#3

SDCS#3

PDA0

PDA1

PDA2

SDA0

SDA1

SDA2

PDDREQ

SDDREQ

PDDACK#

SDDACK#

PDIOR#

SDIOR#

PDIOW#

SDIOW#

PIORDY

SIORDY

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD7

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9

SDD10

SDD11

SDD12

SDD13

SDD14

SDD15

VCCRTC

V5R1

V5R2

V5R_SUS

VCPU2

VCPU1

GPIO25

GPIO24

RSM_PWROK

USBP2P

USBP2N

USBP3P

USBP3N

OC#2

OC#3

EE_CS

EE_DIN

EE_DOUT

EE_SHCLK SMLINK0

SMLINK1

VRMPWRGD

TP0

SUSCLK

FS0

R376 43k

C172

1.0uF

R377 0

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PCI 1 and 2

14 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

AD30

AD28

AD26

AD24

AD22

AD20

AD18

AD16

AD15

AD13

AD11

AD9

AD6

AD4

AD2

AD0

AD31

AD29

AD27

AD25

AD23

AD21

AD19

AD17

PERR#

AD14

AD12

AD10

AD8

AD7

AD5

AD3

AD1

ACK64#

PIRQ#B

PIRQ#D

PCI_RST#

PCI_PME#

AD30

AD28

AD26

AD24

R_AD17

AD22

AD20

AD18

AD16

FRAME#

TRDY#

STOP#

PAR

AD15

AD13

AD11

AD9

C_BE#0

AD6

AD4

AD2

AD0

PIRQ#C

PIRQ#A

AD31

AD29

AD27

AD25

C_BE#3

AD23

AD21

AD19

AD17

C_BE#2

IRDY#

DEVSEL#

PLOCK#

PERR#

SERR#

C_BE#1

AD14

AD12

AD10

AD8

AD7

AD5

AD3

AD1

ACK64#

AD17R_AD16 AD16

AD[0..31]

C_BE#[0..3]

C_BE#3

C_BE#2

C_BE#1

C_BE#0

PIRQ#B11,15,30 PIRQ#D15,30

PCLK_16

PREQ#012,30

IRDY#12,15,30

DEVSEL#12,15,30

PLOCK#12,15,30

SERR#12,15,30

AD[0..31]12,15

C_BE#[0..3]12,15

PIRQ#A 11,15,30

PIRQ#C 15,30

PGNT#0 12

PCI_PME# 11,12,15,22

FRAME# 12,15,30

TRDY# 12,15,30

STOP# 12,15,30

PAR 12,15

ACK64#15,30

PGNT#1 12

PREQ#112,30

PCLK_26

PCI_RST# 11,15,30

PERR#12,15,30

REQ64#1 30 REQ64#2 30

VCC3_3

VCC5

VCC12VCC12-

VCC5

VCC3_3 VCC3_3

VCC5

VCC12

VCC12-

VCC5

VCC3_3

V3SB V3SB

R133

100 R142

100

PCI1

PCI_CON_32BIT

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

TRST#

+12V

TMS

TDI

+5V

INTA#

INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND

GND

RESERVED

RST#

+5V(I/O)

GNT

GND

PME#

AD30

+3.3V

AD28

AD26

GND

AD24

IDSEL

+3.3

AD22

AD20

GND

AD18

AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13

AD11

GND

AD9

C/BE#0

+3.3V

AD6

AD4

GND

AD2

AD0

+5V(I/O)

REQ64#

+5V

+5V

-12V

TCK

GND

TDO

+5V

+5V

INTB#

INTD#

PRSNT#1

RESERVED

PRSNT#2

GND

GND

RESERVED

GND

CLK

GND

REQ#

+5V(I/O)

AD31

AD29

GND

AD27

AD25

+3.3V

C/BE#3

AD23

GND

AD21

AD19

+3.3V

AD17

C/BE#2

GND

IRDY#

+3.3V

DEVSEL#

GND

LOCK#

PERR#

+3.3V

SERR#

+3.3V

C/BE#1

AD14

GND

AD12

AD10

GND

AD8

AD7

+3.3V

AD5

AD3

GND

AD1

+5V(I/O)

ACK64#

+5V

+5V

PCI2

PCI_CON_32BIT

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

TRST#

+12V

TMS

TDI

+5V

INTA#

INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND

GND

RESERVED

RST#

+5V(I/O)

GNT

GND

PME#

AD30

+3.3V

AD28

AD26

GND

AD24

IDSEL

+3.3

AD22

AD20

GND

AD18

AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13

AD11

GND

AD9

C/BE#0

+3.3V

AD6

AD4

GND

AD2

AD0

+5V(I/O)

REQ64#

+5V

+5V

-12V

TCK

GND

TDO

+5V

+5V

INTB#

INTD#

PRSNT#1

RESERVED

PRSNT#2

GND

GND

RESERVED

GND

CLK

GND

REQ#

+5V(I/O)

AD31

AD29

GND

AD27

AD25

+3.3V

C/BE#3

AD23

GND

AD21

AD19

+3.3V

AD17

C/BE#2

GND

IRDY#

+3.3V

DEVSEL#

GND

LOCK#

PERR#

+3.3V

SERR#

+3.3V

C/BE#1

AD14

GND

AD12

AD10

GND

AD8

AD7

+3.3V

AD5

AD3

GND

AD1

+5V(I/O)

ACK64#

+5V

+5V

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PCI 3

15 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

AD22

AD20

AD18

AD16

AD15

AD9

AD6

AD4

AD2

AD0

AD31

AD29

AD27

AD25

AD23

AD21

AD19

AD17

PERR#

AD14

AD12

AD10

AD8

AD7

AD5

AD3

AD1

ACK64#

C_BE#3

C_BE#2

C_BE#1

AD18

C_BE#0

AD30

R_AD18

AD24

AD11

AD13

AD28

AD26

AD[0..31]

C_BE#[0..3]

PIRQ#B11,14,30

PCLK_36

IRDY#12,14,30

DEVSEL#12,14,30

SERR#12,14,30

AD[0..31]12,14

C_BE#[0..3]12,14

PIRQ#C 14,30

PIRQ#A 11,14,30

PGNT#2 12

PCI_PME# 11,12,14,22

FRAME# 12,14,30

TRDY# 12,14,30

STOP# 12,14,30

PAR 12,14

ACK64#14,30

PCI_RST# 11,14,30

PREQ#212,30

PIRQ#D14,30

PERR#12,14,30 PLOCK#12,14,30

REQ64#3 30

SMLINK1 13,30

SMLINK0 13,30

VCC3_3

VCC5

VCC12VCC12-

VCC5

VCC3_3 V3SB

R148

100

PCI3

PCI_CON_32BIT

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

TRST#

+12V

TMS

TDI

+5V

INTA#

INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND

GND

RESERVED

RST#

+5V(I/O)

GNT

GND

PME#

AD30

+3.3V

AD28

AD26

GND

AD24

IDSEL

+3.3

AD22

AD20

GND

AD18

AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13

AD11

GND

AD9

C/BE#0

+3.3V

AD6

AD4

GND

AD2

AD0

+5V(I/O)

REQ64#

+5V

+5V

-12V

TCK

GND

TDO

+5V

+5V

INTB#

INTD#

PRSNT#1

RESERVED

PRSNT#2

GND

GND

RESERVED

GND

CLK

GND

REQ#

+5V(I/O)

AD31

AD29

GND

AD27

AD25

+3.3V

C/BE#3

AD23

GND

AD21

AD19

+3.3V

AD17

C/BE#2

GND

IRDY#

+3.3V

DEVSEL#

GND

LOCK#

PERR#

+3.3V

SERR#

+3.3V

C/BE#1

AD14

GND

AD12

AD10

GND

AD8

AD7

+3.3V

AD5

AD3

GND

AD1

+5V(I/O)

ACK64#

+5V

+5V

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Place 100pF cap

near DVO pin 40

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VGA Header and DVO Debug Header

16 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

DDCCL

DDCDA

HS

VS

BV

GV

RV

MONOPU

MON2PU

F5_FB11

FTD[0..11]

5VHSYNC

5VVSYNC

5VDDCDA

5VFTSDA

5VDDCCL

U8_VCC

5VFTSCL

FTD5

FTD3

FTD11

FTD1

FTD8

FTD6

FTD4

FTD7

FTD2

FTD9

FTD10

FTD0

FTVREF

3VDDCDA8

SL_STALL 8

3VDDCCL8

CRT_VSYNC8

FTVSYNC 8

3VFTSCL8

FTCLK1 8

CRT_HSYNC8

FTHSYNC 8

FTCLK0 8

VID_RED8

VID_GREEN8

VID_BLUE8

FTD[0..11]8

PCIRST#7,17,21,30

FTBLNK# 8

3VFTSDA8 VCC3SBY VCC1_8

VCC5

VCC5 VCC1_8

VCC5

VCC5

VCC1_8

VCC5 VCC3_3 VCC1_8

C138

1.0uF

C139

1.0uF

C140

1.0uF

C143

1.0uF

C141

2.2uF

C142

1.0uF

C144

2.2uF

R329 2.2K

R328 2.2K

C135

100PF

U8

QST3384

3

4

7

8

11

14

17

18

21

22

24

2

5

6

9

10

15

16

19

20

23

12

1

13

1A1

1A2

1A3

1A4

1A5

2A1

2A2

2A3

2A4

2A5

VCC

1B1

1B2

1B3

1B4

1B5

2B1

2B2

2B3

2B4

2B5

GND

BEA#

BEB#

D11

G1

D10

G2

D9

G3

D8

G4

D7

D6

G5

ST#

STB G6

D5 G7

D4 G8

D3

D2 G9

D1 G10

D0 G11

D/B G12

Y

C

CVBS

SP0

SP1

SP2

SP3

5V1

5V2

3V1

3V2

3V3

3V4

VDD1

VDD2

VDD3

VDD4

VREF

PD#

RST#

SDA5

SCL5

SDA

SCL

I/C

HS

VS

J3

DVO CONNECTOR

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

51 52

53 54

55 56

57 58

59 60

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

R85 33

C55

22PF

U28

PAC-VGA201/QSOP

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

VCC3

VCC1

VIDEO_1

VIDEO_2

VIDEO_3

GND

POWER_UP

VCC2 DDC_OUT1

DDC_OUT2

SYNC_IN1

SYNC_OUT1

SYNC_IN2

SYNC_OUT2

SD1

SD2

PR12

75,1%

C50

3.3PF

C49

X10PF

BC68

0.22UF

C47

3.3PF

C43

3.3PF

PR11

75,1%

PR10

75,1%

C53

10PF

C54

10PF

R87 33

C57

22PF

C56

10PF

C48

10PF

R84

1K

R322 10

R321 10

BC223

0.22UF

C134

100PF

VFB1

BEAD

1 2

FB11

BEAD

1 2

VGA1

VGA_CONN

6

1

11

7

2

12

8

3

13

9

4

14

10

5

15

R73

1K

F5

FUSE_1.0A

R350

1k

R97

4.7K

R96

4.7K

VFB2

BEAD

1 2

R351

1k

VFB3

BEAD

1 2

C46

X10PF

R326 22

C45

X10PF

R327 22

BC225

0.22UF

BC224

0.22UF

RN41 2.2K/8P4R

1

3

5

7

2

4

6

8

D4

1N4148

BC86

0.1UF

R95

4.7K

C136

0.01uF

C137

100pF

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDE

FWH

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

FWH and UDMA100 IDE

17 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

IDERST_IDE1_PIN1 PDD8

PDD6 PDD9

PDD5 PDD10

PDD4 PDD11

PDD3 PDD12

PDD2 PDD13

PDD1 PDD14

PDD0 PDD15

PDA1

PDA0

IDERST_IDE2_PIN1

SDD6

SDD5

SDD4

SDD3

SDD2

SDD1

SDD0

SDA1

SDA0

SDA2

IDERST#

FPGI4

SDD11

SDD13

SDD9

SDD10

SDD8

SDD15

SDD14

SDD12

IDERST# SDD7

SDD[0..15]

SDA[0..2]

PDD7

PDA2

PDD[0..15]

PDA[0..2]

PDREQ13

PDIOR#13 PDIOW#13

PIORDY13 PDDACK#13 IRQ1412

PDCS#3 13

SDD[0..15]13

SDCS#113

SDA[0..2]13

SDIOW#13

SIORDY13 SDDACK#13 IRQ1512

SDCS#3 13

SDIOR#13

IDEACTS#24

IDEACTP#24 PDCS#113

SDREQ13

PCIRST#7,16,21,30

INIT# 4,12

LAD3 13,21

PCLK_8 6

GPIO2312

LAD013,21 LAD113,21 LAD213,21

LFRAME# 13,21

IDERST#30

PDD[0..15]13

PDA[0..2]13

S66DET 12

P66DET 12

VCC3_3

VCC3_3

VCC3_3

VCC3_3VCC3_3

VCC3_3

R79

4.7K

R112 33

R76

4.7K

R75 8.2K

R113 33

R83 8.2K

IDE2

PIN_2X20

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31

33

35

37

39

32

34

36

38

40

BC175

0.1UF

BC177

0.1UF

BC178

0.1UF

BC173

0.1UF

R211 8.2K

C51

47PF

C44

47PF

R207

0

R80

10K

IDE1

PIN_2X20

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31

33

35

37

39

32

34

36

38

40

R70

10K

U23

FWH32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

VPP

RST#

FGPI3

FGPI2

FGPI1

FGPI0

WP#

TBL#

ID3

ID2

ID1

ID0

FWH0

FWH1

FWH2

GND FWH3

RFU

RFU

RFU

RFU

RFU

FWH4

INIT#

VCC

GND

VCCA

GNDA

IC

FGPI4

CLK

VCC

R206 8.2K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JP4 Pin 3 near USB2 Pin 5

JP4 Pin 4 near USB2 Pin 7

JP5 Pin 3 near USB2 Pin 6

JP5 Pin 4 near USB2 Pin 8

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

USB

18 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

USBP0P13 USBP1N13 USBP1P13

USBP0N13

USBOC#0-113

AGPUSBN11 AGPUSBP11

USBP3N13 USBP2P13

CNRUSBN24

USBOC#2-313

USBP3P13

CNRUSBP24

AGP_OC#11

CNR_OC#24

USBP2N13

VCC5DUAL

VCC5DUAL

V3SB

JP4

HEADER5

1

3

2

4

5

JP5

HEADER5

1

3

2

4

5

USB2

HEADER5X2

12

34

56

78

910

FB28 BEAD

1 2

BC4

470PF

+

EC18

100UF

RN72

15K/8P4R

1

3

5

7

2

4

6

8

FB24 BEAD

1 2 FB23 BEAD

1 2 FB22 BEAD

1 2

CP3

47PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

F4 FUSE_1.0A

FB21 BEAD

1 2

FB8 BEAD

1 2

CP4

47PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

FB26 BEAD

1 2

FB27 BEAD

1 2

USB1

USB_CON2

1

2

3

4

5

6

7

8

VCC0

DATA0-

DATA0+

GND0

VCC1

DATA1-

DATA1+

GND1

R268 X0

FB29 BEAD

1 2

RN73

15K/8P4R

1

3

5

7

2

4

6

8

+

EC39

100UF

R269 X0 F7 FUSE_1.0A

FB25 BEAD

1 2

R266

330K

C122

470PF

R267

330K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AC’97

CODEC

"SINGLE POINT CONNECTION"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

AC’97 Codec

19 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

CX3D

MONO_OUT

VREF

RX3D

FILT_R

FILT_L

AFILT2

AFILT1

XTAL_OUT

XTAL_IN

R154_MC58

VREFOUT

PC_BEEPR336_MC56

AC97SPKR24 EAPD 20

AUD_VREFOUT 20

AC_SYNC 13,24

AC_BITCLK 13,24

AC_SDIN0 13,24,30

PRI_DWN_RST# 29

AC_SDOUT 13,24,29

LINE_IN_L20

LNLVL_OUT_R20

CD_R20

CD_REF20

MIC_IN20

LINE_IN_R20

CD_L20

LNLVL_OUT_L20

AUX_R20 AUX_L20

ICH_SPKR13,24,29

VCC3_3 VCC5 VCC5_AUDIO

MC53

1UF

C97

22PF

C98

22PF

BC129

0.1UF

BC139

0.1UF

BC140

0.1UF

C99

X10PF

MC48

2.2UF

MC46

4.7UF

C95

2700PF

C94

2700PF

MC54

1UF

MC51

0.1uF NPOP

MC52

1UF

MC55

0.1UF

MC56 1UF

MC58 1UF

U15

CS4299

4

1

7

9

38

42

25

26

40

44

43

12

24

23

21

22

20

18

19

17

16

14

15

13

37

36

35

41

39

29

30

32

31

33

34

27

28

3

2

11

5

8

10

6

46

45

48

47

DVSS1

DVDD1

DVSS2

DVDD2

AVDD2

AVSS2

AVDD1

AVSS1

NC40

NC44

NC43

PC_BEEP

LINE_IN_R

LINE_IN_L

MIC1

MIC2

CD_R

CD_L

CD_REF

VIDEO_R

VIDEO_L

AUX_L

AUX_R

PHONE

MONO_OUT

LINE_OUT_R

LINE_OUT_L

LNLVL_OUT_R

LNLVL_OUT_L

AFILT1

AFILT2

FILT_L

FILT_R

RX3D

CX3D

VREF

VREFOUT

XTL_OUT

XTL_IN

RESET#

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CS1

CS0

CHAIN_CLK

EAPD

BC136

0.1UF

R337

220K

R154 100

PFB6

BEAD

12

R254

1K

R252

1K

R253 X0

Y1

24.576MHZ

R336 1K

R155

220K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CD Analog Input

Line_In Analog Input

Microphone Input

Stereo HP/Spkr out

"SINGLE POINT CONNECTION"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Audio I/O

20 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

R119_FB15

R120_MC41 JK3_MICIN

CD_ING

JK2_LINE_IN_R

JK2_LINE_IN_L

AUX_INL

AUX_INR

R122_FB17MC44_R122

R121_FB16MC42_R121

CD_INR CDIN_R

CD_INL CDIN_L

C87_C77

U11_BYPASS U11_OUTB

U11_OUTA

SPKROUT_R

U11_INB

MC47_R132

SPKROUT_L

CDIN_REF

C74_JK1

MC45_R127 U11_INA

LNLVL_OUT_R19

AUD_VREFOUT19

LINE_IN_R19

LINE_IN_L19

CD_R 19

CD_L 19

CD_REF 19

MIC_IN19

AUX_L 19

AUX_R 19

LNLVL_OUT_L19

EAPD19

VCC5_AUDIO

C90

100PF

R128

20K

BC123

0.1UF

R126 20K

C87 100PF

R127

20K

+

C78

100UF

R119

2.2K

R120

1K

C80

100PF

C75

100PF

MC42

1UF

R125

220K R124

220K

R115

1K

R117

1K

R116

1K

AUX1

2.54_WAFER_4

1

3

2

4

C85

0.01UF

CD2

2.54_WAFER_4

1

3

2

4

CD1

2mm_WAFER_4

1

3

2

4

JK2

PHONEJACK

JK3

PHONEJACK

JK1

PHONEJACK

R122

1K

R121

1K

C86

100PF

MC41

1UF C76

100PF

MC43

1UF

MC39

1UF

MC37

1UF

MC38

1UF

C81

100PF

C79

100PF

C83

100PF

C84

100PF

MC36

1UF

MC44

1UF

MC45

1UF

U11

LM4880

1

2

3

4

8

7

6

5

OUTA

INA

BYPASS

GND

VDD

OUTB

INB

SHUTDN

+

C77

100UF

R104

22

R105

22

C74

100PF

R132

20K

MC47

1UF

FB13

BEAD

1 2

FB14

BEAD

1 2

FB17

BEAD

1 2

FB16

BEAD

1 2

FB15

BEAD

1 2

R118

220K C82

100PF

MC40

1UF

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

W83627HF

FDD Signals Trace 8 or 10 mil

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Super I/O and FDC

21 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

WD#

DIR#

DS1#

WE#

MOA#

HEAD#

STEP#

DSB#

DSA#

MOB#

RWC#

IOAVCC

SUSLED 24

KDAT 23

KCLK 23

KEYLOCK# 24

RI#0 22

DCD#0 22

RXD0 22

DTR#0 22

RTS#0 22

DSR#0 22

CTS#0 22

STB# 22

AFD# 22

ERR# 22

SLIN# 22

ACK# 22

BUSY 22

PE 22

VTIN24,25 VTIN125

FANIO325 FANIO225 FANIO125

FANPWM225 FANPWM125

BEEP24

MCLK 23

MDAT 23

PS_ON 25

IRRX 23

IRTX 23

RI#1 22

DCD#1 22

RXD1 22

DTR#1 22

RTS#1 22

DSR#1 22

CTS#1 22

CASEOPEN# 13,25

SUSCLK 13

TXD1 22

KBRST# 12,30

PAR_INIT# 22

MIDI_IN23

J1BUTTON223 J2BUTTON223

J2BUTTON123 J1BUTTON123

JOY1Y23 JOY2Y23

MIDI_OUT23

JOY2X23 JOY1X23

SMBDATA9,10,13,24,30,32

SLP_S3# 6,13,28

A20GATE 12,30

PWROK 13,25

SLCT 22

PCIRST# 7,16,17,30

HM_VREF25 VTIN325

THRMDN4,25

SMBCLK9,10,13,24,30,32

OVT#13,30

PWRBTN# 13,33

TXD0 22

RSMRST# 13

PDR0 22

PDR1 22

PDR2 22

PDR3 22

PDR4 22

PDR5 22

PDR6 22

PDR7 22

LAD213,17 LAD313,17

LAD113,17 LAD013,17

SIO_CLK246LPC_PME#12,30 PCLK_76

LDRQ#013

VID027,29,32 VID127,29,32 VID227,29,32

-5VIN25 -12VIN25 +12VIN25 +3.3VIN25

VCORE25

LFRAME#13,17

VID327,29,32

SERIRQ12,30

PANSWIN 24,32

VTT_SENSE25

VCC5

VCC5

VCC5SBY

VCC3_3

VCC5

VCC5

VCCRTC

VCC5SBY

V3SB

R166

0

R185

300

R193

300

R157

10K

BC155

.1U

BC162

.1U

BC154

0.1UF

BC161

0.1UF

BC172

0.1UF

FB19

BEAD

1 2

FDC1

HEADER_17X2

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31

33 32

34

BC151

0.1UF

FB20

BEAD

1 2

R167

10K

U17

W83627HF

1

2

3

4

5

6

7

9

10

11

12

13

14

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

8

15

DRVDEN0

DRVDEN1

INDEX#

MOA#

DSB#

DSA#

MOB#

STEP#

WD#

WE#

VCC

TRAK0#

WP#

HEAD#

DSKCHG#

CLKIN

PME#

VSS

PCICLK

LDRQ#

SERIRQ

LAD3

LAD2

LAD1

LAD0

VCC3V

LFRAME#

LRESET#

SLCT

PE

BUSY

ACK#

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

SLIN#

INIT#

ERR#

AFD#

STB#

VCC

CTSA#

DSRA#

RTSA#

DTRA#

SINA

SOUTA

VSS

DCDA#

RIA#

KBLOCK#

GA20M

KBRST

VSB

KCLK

KDAT

SUSLED/GP35

MCLK

MDAT

PSOUT#

PSIN#

CIRRX/GP34

RSMRST#/GP33

PWROK/GP32

PWRCTL#/GP31

SUSCIN/GP30

VBAT

SUSCLKIN

CASEOPEN#

VCC

CTSB#

DSRB#

RTSB#

DTRB#

SINB

SOUTB

DCDB#

RIB#

VSS

IRTX/GP26

IRRX/GP25

WDTO/GP24

PLED/GP23

SDA/GP22

SCL/GP21

AGND

-5VIN

-12VIN

+12VIN

AVCC

+3.3VIN

VCOREB

VCOREA

VREF

VTIN3

VTIN2

VTIN1

OVT#

VID4

VID3

VID2

VID1

VID0

FANIO3

FANIO2

FANIO1

VCC

FANPWM2

FANPWM1

VSS

BEEP

MSI/GP20

MSO/IRQIN0

GPSA2/GP17

GPSB2/GP16

GPY1/GP15

GPY2/P16/GP14

GPX2/P15/GP13

GPX1/P14/GP12

GPSB1/P13/GP11

GPSA1/P12/GP10

DIR#

RDATA#

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Parallel Port

WAKE ON MODEM

COM1

COM2

WAKE ON LAN

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Serial, Parallel, WOL, and WOR

22 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

RI0

RI1

DCD0

DTR0

CTS0

TXDD0

RTS0

RXDD0

DSR0

RI0

DCD1

DTR1

CTS1

TXDD1

RTS1

RXDD1

DSR1

RI1

DSR0

RXDD0

RXDD1

TXDD1

DCD1

RTS1

DTR1

DTR0

TXDD0

RTS0

CTS0

DCD0

RI1

RI0

CTS1

DSR1

DCD#021 DTR#021 CTS#021 TXD021 RTS#021

DSR#021 RI#021

DCD#121 DTR#121 CTS#121 TXD121 RTS#121

DSR#121 RI#121

RXD021

RXD121

PDR721

PDR121

STB#21

PDR021

PDR321

PDR421

PDR521

PAR_INIT#21

SLIN#21

ACK#21

BUSY21

PE21

SLCT21

ERR#21

PDR221

PDR621

AFD#21

PCI_PME#11,12,14,15

ICH_RI#13,30

VCC5

VCC12- VCC12 VCC5

VCC5SBY

U5

PAC-S1284

1

2

3 26

4

5

6

7

8

9

10

11

12

13

14

28

27

15

25

24

23

22

21

20

19

18

17

16

P1

P2

SI1 SO1

SI2

SI3

SI4

SI5

P3

SI6

P4

SI7

P5

SI8

SI9

P8

P7

P6

SO2

SO3

SO4

GND

SO5

VCC

SO6

SO7

SO8

SO9

R107

10K

R109

10K

U10

GD75232

2

3

4

5

6

7

8

1

19

18

17

16

15

14

13 9

10

11

12

20

RA1

RA2

RA3

DY1

DY2

RA4

DY3

12V

RY1

RY2

RY3

DA1

DA2

RY4

DA3 RA5

-12V

GND

RY5

5V

CN2

100PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

CN3

100PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

CN9

100PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

CN11

100PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

COM2

HEADER_5X2

1

3

5

7

9

2

4

6

8

10

COM1

CONNECTOR_DB9

5

9

4

8

3

7

2

6

1

BC99

.1U

BC54

.1U

U9

GD75232

2

3

4

5

6

7

8

1

19

18

17

16

15

14

13 9

10

11

12

20

RA1

RA2

RA3

DY1

DY2

RA4

DY3

12V

RY1

RY2

RY3

DA1

DA2

RY4

DA3 RA5

-12V

GND

RY5

5V

R110

2.2K

BC49

.1U

R108

2.2K

R229

4.7K

R230

100

LPT1

LPT

13

25

12

24

11

23

10

22

9

21

8

20

7

19

6

18

5

17

4

16

3

15

2

14

1

D2

SS12/SMD

D6

SS12/SMD

D7

SS12/SMD

Q14

2N3904

Q15

2N3904

Q21

2N3904

WOL1

HEADER_3*1(2MM)

1

3

2

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Game Port

Keyboard

Mouse

IR

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PS/2, Game, and IR

23 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

MIDI_OUTPUT

JOY_1Y

J2BUT2

JOY_2Y

CN1_U1

MIDI_INPUT

J1BUT2

JOY_2X

JOY_1X

J2BUT1

J1BUT1

JOY2X21

J2BUTTON221

MIDI_OUT21

J1BUTTON121

J1BUTTON221

JOY1X21

JOY1Y21 JOY2Y21

J2BUTTON121

MIDI_IN21

KDAT21

KCLK21

MDAT21

MCLK21

IRRX21

IRTX21

VCC5VCC5 VCC5VCC5 VCC5VCC5 VCC5

VCC5

VCC5DUAL

R93

4.7K

R92

4.7K

R99

4.7K

C68

22PF

C73

470PF

C64

1000PF

F6 XFUSE_1.0A

C62

470PF

R98 47

C59

470PF

C63

22PF

C71

1000PF

R103 0

C67

1000PF

R102

4.7K

C65

22PF

C66

22PF

C60

1000PF

CN10

470PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

R94

4.7K C70

470PF J1

GAME_PORT

8

15

7

14

6

13

5

12

4

11

3

10

2

9

1

CN8

470PF/8P4C

1

3

5

7 8

2

4

6

1

3

5

78

2

4

6

R101

4.7K

FB12

BEAD

1 2

R91 47

R18 0

R17 0

CN1

470PF8P4C

1

3

5

78

2

4

6

1

3

5

78

2

4

6

IR1

HEADER_1X5

1

3

2

4

5

FB1

BEAD

1 2

FB3

BEAD

1 2

FB5

BEAD

1 2

FB2

BEAD

1 2

FB4

BEAD

1 2

FB6

BEAD

1 2

F1 XFUSE_1.0A

F2 XFUSE_1.0A U1

KB/MOUSE

1

2

3

4

5

6

13

14

15

16

17

7

8

9

10

11

12

C1

2.2UF

C2

2.2UF

RN4 4.7K/8P4R

1

3

5

7

2

4

6

8

RN40 1K/8P4R

1

3

5

7

2

4

6

8

RN39 1K/8P4R

1

3

5

7

2

4

6

8

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDD LED

PWR_SW

KEYLOCK

SMI_SW

SPEAKER

RESET

GREEN LED

RESERVE

PC_BEEP SELECTION

3-4 ON

1-2 ON CONTROLLED by AC97 CODEC

JP2 TRADITIONAL

Reset

Switch

Power

Switch

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Front Panel Headers and CNR

24 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

R237_2

R243_PN1

R240_PN1

R238_PN1

R237_PN2

R242_PN1

SMBDATA

D15_PN1

SMBCLK

IDEACTS#17

BEEP21

KEYLOCK#21

PANSWIN21,32

IDEACTP#17

HWRST#25,32

SUSLED21

EXTSMI#12

ICH_SPKR13,19,29

AC97SPKR19

AC_SDIN1 13,30

AC_SDIN0 13,19,30

AC_RST# 13,29

CNR_OC#18

AC_SDOUT13,19,29 AC_SYNC13,19

AC_BITCLK13,19

PRI_DWN#12,29 SMBCLK9,10,13,21,30,32 SMBDATA 9,10,13,21,30,32

CNRUSBN 18

CNRUSBP 18

EE_CS 13

LAN_TXD0 12

LAN_TXD2 12

LAN_CLK 12

LAN_RXD1 12

LAN_RXD012

LAN_TXD112LAN_RSTSYNC12

LAN_RXD212

EE_SHCLK13 EE_DOUT 13EE_DIN13

VCC5

VCC5SBY VCC5

VCC5

V3SB

VCC5

VCC12VCC5SBYVCC12- VCC5V3SB

VCC5SBY

VCC3_3

VCC5SBY

VCC5VCC5

VCC5

BC184

0.1UF

R236

33

SP1

BUZZER

R244

10K R238

220

R240

0

BC185

0.1UF

R243

150

R242

220

PN1

HEADER_14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

R233

10K

PN2

HEADER_14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

R234

150

R235

10K

R232 68

R231 68

R237

0

C119

0.1UF

R247

20K

JP2

XHEADER 2X2

12

34

R255

10K

R223

10K

R256 0

R226 2.2K

R272

15K

C125

47PF

R273

15K

C126

47PF

SMB2

SMBCON

1

3

2

4

5

R239 330

SMB1

SMBCON

1

3

2

4

5

R241

10K

CNRSLOT1

CNR

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

RESERVED

RESERVED

RESERVED

GND

RESERVED

RESERVED

GND

LAN_TXD1

LAN_RSTSYNC

GND

LAN_RXD2

LAN_RXD0

GND

RESERVED

+5VDUAL

USB_OC#

GND

-12V

+3.3VD

GND

EE_DOUT

EE_SHCLK

GND

SMB_A0

SMB_SCL

PRIMARY_DN#

GND

AC97_SYNC

AC97_SD_OUT

AC97_BITCLK

RESERVED

RESERVED

GND

RESERVED

RESERVED

GND

LAN_TXD2

LAN_TXD0

GND

LAN_CLK

LAN_RXD1

RESERVED

USB+

GND

USB-

+12V

GND

+3.3VDUAL

+5VD

GND

EE_DIN

EE_CS

SMB_A1

SMB_A2

SMB_SDA

AC97_RESET#

RESERVED

AC97_SD_IN1

AC97_SD_IN0

GND

R246

2.2K

D15 1N4148

D14 1N4148

D16

LED

Q19

2N3904

Q20

2N3904

Q22

2N3904

SW2

SW_4

1 2

3 4

12

34

SW3

SW_4

1 2

3 4

12

34

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CPU FAN

CHASSIS FAN

PWR FAN

Temperature Sensing

If case is opened,

this switch should be closed.

Voltage Sensing

"power use"

"system use"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ATX Power and HW Monitor

25 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

+12CHFAN

+12CPUFAN

ATXPWROK

FANIO1 21

FANPWM121

FANIO2 21

FANIO3 21

HM_VREF21

THRMDN4,21

VTIN121

VTIN24,21

+3.3VIN 21

-5VIN 21

+12VIN 21

VCORE 21

-12VIN 21

VTIN321

PWROK 13,21

CASEOPEN#13,21

HWRST#24,32

PS_ON21

DBRESET#4

FANPWM221

VTT_SENSE 21

VCC12-

VCC_5-

VCC5 VCC5SBY

VCC12

VCC12

VCCVID

VCC12-

VCC_5-

VTT

VCC12

VCC3_3

VCC12

VCC12

VCC5

VCC5

VCC5

VCCRTC

VCC3_3 VCC5VCC5SBY V3SB

VCC5SBY

VCC5SBY

VCC5SBY

V3SB VCC5SBY

V3SBV3SB U19E

74LVC06A

11 10

R189

4.7K

ATXPR1

ATX_PWCON

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

3.3V

GND

+5V

GND

+5V

GND

PWROK

AUX5V

+12V

3.3V

-12V

GND

PS_ON

GND

GND

GND

-5V

+5V

+5V

3.3V

R218

4.7K

R217 1K

R216 510

+

EC38

22UF

FAN3

HEADER_3

1

3

2

R11

4.7K

R10 1K

R16 510

FAN1

HEADER_3

1

3

2

Q17

2N7002

Q1

2N7002

+

EC3

22UF

R210

30K

FAN2

HEADER_3

1

3

2

R100

1K

+

EC35

22UF

C118

3300PF

PR37

28K,1%

PR32

120K,1%

PR34

232K,1%

R214

10K

PR35

56K,1%

R208

10K

R209

10K

PR33

56K,1%

S1

HEADER_2PIN

R245 100

R213 10M

R19

1K

R212

1K

PR39

10K,1%

PR36

10K,1%

t

RT1

10K_1%-THRM/0603

U20F

74LVC14A

1213

U19F

74LVC06A

13 12

R190

15K

U19A

74LVC06A

1 2

714

BC164

.1U

U20C

74LVC14A

65

C115

2.2UF

R192

33K

t

RT2

X10K_1%-THRM/0603

JP3

HEADER_2

1

2

U20D

74LVC14A

89

PR38

10K,1%

D13

1N4148

D1

1N4148

D5

1N4148

D10

1N4148

Q18

2N2907

Q2

2N2907

U19B

74LVC06A

3 4

U20A

74LVC14A

7

14 21

R323

1K BC165

.1U

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Target is

really 1.85V

2.0ms delay

nominal

ASSERTED LOW!

Empty for ADM1051AJR

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: Vddq, Vcc1_8, and Vtt

26 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

VR1_FB

U32-2

U31_FORCE2

U31_SENSE1

U31_SENSE2

U31_SHDN1#

R355_C147

U31_SHDN2#

D24_U32

U31_FORCE1

Q49_B

Q48_B

TUAL5

4

,6,

7

VTTPWRGD12 6

VTTPWRGD 4

VTTPWRGD5# 27

TYPEDET#11

VCC3_3

VCC3_3

VCC3_3

VCC5

V1_8SB

VCC5

V1_8SB

VCC12

VTT

VCC12VCC5SBY

VCC5

VCC5

VCC5

VTT

VCC1_8

VDDQ

VCC3_3

VCC3_3

D23 BAT54C

1

2

3

1

2

3

R366

732 1%

R368

1k 1%

Q49

NPN

Q48

PNP

Q43

2N7002

Q44

2N7002

R378

2.2k

R379

1k

C174

10 uF

U32B

LM393 Ch2

5

67

IN+ 2

IN- 2

OUT 2

R380

20k

C173

0.1 uF

C150

100uF

C151

100uF

C152

4.7uF

C153

4.7uF

C149

0.1uF

C156

100uF

C157

100uF

C158

4.7uF

C159

4.7uF

C155

0.1uF

ADM1051A

U31

8

4

5

3

7

1

6

2

VCC

GND

SHDN1#

SHDN2#

FORCE 1

FORCE 2

SENSE 1

SENSE 2

Q39

PHD55N03LT

Q40

MTD3055VLT4

R354

3.3k

C148

0.1uF

R356

3.3k

R359

10k

R364

49.9 1%

R357

0

R358

1M - NPOP

R367

10 1%

Q41

FDN335N

R355

0

C147

1.0uF

R402

470

R360

100 1%

R361

5620 1%

R401

220

R400

220

C160

22uF Tantalum

D24

BAT54C

1

2

3

1

2

3

C162

0.1uF

R381

1k

U32A

LM393 Ch1

21

8

4

3

IN- 1 OUT 1

VCC

GND

IN+ 1

VR1

LT1587-ADJ

32

1

VINVOUT

ADJ

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

New V1_SB Circuitry

This takes the place of

the old V1_8SB circuit.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: VCCVID, V1_8SB

27 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

Q45_L7

Q46_R386

Q45_L8

U34_C188

VID0

VID2

VID3

U34_C182

R382_U34

U34_R384

VCCVID_FB

VID1

VID4 U34-17

U34_R391

U34-18

U34_1415

VID[0:4]

2

9,3

2

VRM_PWRGD 13

VTTPWRGD5#26

VCC12

VCC5

VCC5

VCCVID

V1_8SB

V3SB

R404

32.4 1%

R405

38.3 1%

C183

0.1uF C184

4.7uF

C194

0.1uF

R392 0

U34

ADP3170

16

1

4

3

2

5

18

17

9

6

20

14

15

13

8

12

11

10

19

7

VCC

VID3

VID0

VID1

VID2

VID25

DRVH

DRVL

FB

PWRGD

GND

LRDRV

LRFB

COMP

SD

CT

CS+

CS-

PGND

REF

R382 10 (805)

C197

C188

100pF

R390

25.5k 1% R391 0

R393

154k 1%

C193

0.001uF

C175

10uF C177

3300uF C178

3300uF C179

0.1uF C180

4.7uF

C176

0.1uF C181

4.7uF

L7 1.7uH

Q45

SUD50N03-07

Q46

SUD50N03-07

R385 4.7 (805)

R386 2.2 (805)

R388

2.2 (805)

C189

4700pF

L8 1.2uH

R389 2 mOhm (2512)

R383

220 R384

220

C182 0.001uF

C185

820uF

C190

820uF

C186

820uF

C191

820uF C192

1000uF

C187

1000uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Stuff this box

Do not stuff this box.

Debug note:

Stuff only one box.

1206 pack

1210 pack

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: Duals, 3.3SB, 2.5, VCMOS

28 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

U2_R20

U2_C4

U2_Q5

U2_Q8

U2_Q7

U2_Q4

Q3_Feedback

Q42_Feedback

SLP_S5#13 SLP_S3#6,13,21

VCC3_3VCC12VCC5SBY

VCC3SBY

V3SB VCC5SBY

VCC5DUAL

VCC5SBY

VCC5 VCC2_5

VCC3_3

VCC5

VCMOSVCC3_3

VCC1_8

R369

1.13 1%

R370

9.31 1%

C5

1UF

C18

1UF R20

10K

C4

0.1UF

C8

1UF

+

EC6

10UF

PR3

100,1%

PR2

100,1%

+

EC5

100UF

C7

0.1UF

U2

RT9641

14

1

3

4

9

6

7

5

2

13

15

16

11

10

12

812V

5VSB

3V3DLSB

3V3DL

FAULT/MSET

S3

S5

EN5VDL

EN3VDL

SS

DRV2

VSEN2

5VDLSB

DLA

5VDL

GND

Q3

LM1117ADJ

3

1

2

VIN

ADJ

VOUT

Q5

NDS356AP/SOT23

+

EC17

100UF

+

EC11

10UF

+

EC14

1500UF

+

EC20

10UF

+

EC19

100UF

+

EC10

100UF

+

EC15

100UF

+

EC22

100UF

Q8

FDS8936 / SI9936

1

2

3

4 5

6

7

8

S1

G1

S2

G2 D2

D2

D1

D1

Q7

HUF76121D3S/TO252

Q4

NZT651/SOT223

PR44

49.9 1%

+

EC43

10UF

Q42

LT1117ADJ

3

1

2

VIN

ADJ

VOUT

PR45

10 1%

+

EC42

10UF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SW 5

OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111)

USE CPU FREQ STRAP IN ICH REGISTER

AC_SDOUT

ON

STRAP(SPKR)

OFF REBOOT ON 2ND WATCHDOG TIMEOUT

SW 6 NO REBOOT ON 2ND WATCHDOG TIMEOUTON

ON

SW 7

OFF ON BOARD AC97 CODEC

PRIMARY CODEC

DISABLE

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

System Config DIP Switches

29 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

SW1_R262

SW1_R263 ICH_SPKR 13,19,24

AC_RST#13,24

PRI_DWN#12,24 PRI_DWN_RST# 19

JPR_VID03,32

JPR_VID13,32

JPR_VID33,32

JPR_VID43,32

JPR_VID23,32

VID221,27,32 VID321,27,32 VID427,32

VID021,27,32 VID121,27,32

BSEL#14,32

BSEL#04,32

R_BSEL#07R_REFCLK7 FMOD1 6

FMOD0 6

AC_SDOUT 13,19,24

VCC3_3

VCC5SBY

VCC3_3 V3SB

V3SB

RP5

1K/8P4R

1

3

5

7 8

6

4

2

RP6

1K/8P4R

1

3

5

7 8

6

4

2

R153

10K

U19C

74LVC06A

5 6

R394 8.2k

R395 8.2k

R262 8.2K

R263 8.2K

SW1 DIPSW-8

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RN59

2.2K/8P4R

1

3

5

7

2

4

6

8

D17

1N4148

1

23

19 20 21

456

789

10 11 12

13 14 15

16 17 18

J5

7x3 JPR HDR

23

45 6

78 9

1011 12

1314 15

1617 18

1920 21

1

23

45 6

78 9

1011 12

1314 15

1617 18

1920 21

1

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PCI ICH2

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Pullup/Pulldown Rs and Unused Gates

30 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

R188_U18

SERR#12,14,15 PLOCK#12,14,15 STOP#12,14,15 DEVSEL#12,14,15

IRDY#12,14,15 FRAME#12,14,15

PERR#12,14,15

TRDY#12,14,15

PREQ#112,14 PREQ#012,14

PREQ#212,15

ACK64#14,15

SMBALERT#13

KBRST#12,21 A20GATE12,21

PCI_REQ#A12 OVT#13,21

AC_SDIN113,24

AC_SDIN013,19,24

ICH_IRQ#C12

ICH_IRQ#G12

ICH_IRQ#D12

ICH_IRQ#F12

ICH_IRQ#A12 ICH_IRQ#B12

ICH_IRQ#H12

ICH_IRQ#E12

PIRQ#C14,15 PIRQ#B11,14,15

PIRQ#D14,15

PIRQ#A11,14,15

SMLINK113,15 SMLINK013,15

SERIRQ12,21

GPIO2712 GPIO2513

ICH_RI#13,22

REQ64#114 REQ64#214 REQ64#315

ICHRST#12 PCIRST# 7,16,17,21

PCI_RST# 11,14,15

IDERST# 17

PREQ#412 PREQ#512 PREQ#312

SMBDATA9,10,13,21,24,32

LPC_PME#12,21

SMBCLK9,10,13,21,24,32

GPI812

VCC5 V3SB

VCC3_3

V3SB

VCC3_3

VCC3_3

V3SB

VCC3_3

VCC3_3

VCC3_3

VCC3_3 VCC3_3

VCC3_3 VCC5

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC5SBY

RP2

2.7K/10P8R

1

2

3

4

6

7

8

9

10

5

R1

R2

R3

R4

R5

R6

R7

R8

C

C

RN55

8.2K/8P4R

1

3

5

7

2

4

6

8

RN54

8.2K/8P4R

1

3

5

7

2

4

6

8

RN60

4.7K/8P4R

1

3

5

7

2

4

6

8

RN51

8.2K/8P4R

1

3

5

7

2

4

6

8

RN66

2.7K/8P4R

1

3

5

7

2

4

6

8

RN64

2.7K/8P4R

1

3

5

7

2

4

6

8

RN58

2.7K/8P4R

1

3

5

7

2

4

6

8

RN77

8.2K/8P4R

1

3

5

7

2

4

6

8

R152 10K

R147 10K

RN74

0/8P4R

1

3

5

7

2

4

6

8

RN76

X0/8P4R

1

3

5

7

2

4

6

8

RN75

8.2K/8P4R

1

3

5

7

2

4

6

8

R276 8.2K

U18A

74LVC07A

1 2

147

BC163

.1U

R188

1K R198

1K

R197

1K

U18B

74LVC07A

3 4

147

R196

1K

U18C

74LVC07A

5 6

147

U20B

74LVC14A

43

U18E

74LVC07A

11 10

147

U18F

74LVC07A

13 12

147

U18D

74LVC07A

9 8

147

U19D

74LVC06A

9 8

U20E

74LVC14A

1011

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

" GMCH : 0.1U//0.01U at each conner and each side-center "

" GMCH : Near Display Cache Quadrant "

" Display Cache : Near the Power Pins "

" GMCH : Near System Mem Quadrant "

" DIMM0 : Near Power Pins "

" DIMM1 : Near Power Pins "

" ICH : 0.1U//0.01U at each conner " " ICH : Near Power Pins "" ICH : Near Power Pins "

" misc. "

" ATX POWER " " ATX POWER " " ATX POWER " " ATX POWER "" ATX POWER "

" ICH : Near Power Pins "

" Within 70 mils of GMCH "

" DIMM2 : Near Power Pins "

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Decoupling Caps

31 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

VCC1_8

VCC3SBY

VCC3SBY

VCC3SBY

VCC1_8V3SBVCC3_3

VCC3_3

VCC3_3 VCC5 VCC_5- VCC12-VCC12

VCCVID

V1_8SB

VCC3SBY

VDDQ

VDDQ

H3 HOLE A

1

2

3

4 5

6

7

8H4 HOLE A

1

2

3

4 5

6

7

8

MC5

4.7UF/X7R

MC6

4.7UF/X7R

MC8

4.7UF/X7R

MC3

4.7UF/X7R

MC9

4.7UF/X7R

MC4

4.7UF/X7R

MC10

4.7UF/X7R

MC2

4.7UF/X7R

MC13

4.7UF/X7R

MC1

4.7UF/X7R

MC14

4.7UF/X7R

MC24

4.7UF

MC15

4.7UF/X7R

BC78

0.1UF

H5 HOLE A

1

2

3

4 5

6

7

8

MC49

4.7UF/X7R

BC71

0.1UF

H6 HOLE A

1

2

3

4 5

6

7

8

MC50

4.7UF/X7R

BC43

0.1UF

MC64

4.7UF/X7R

BC44

0.1UF

MC65

4.7UF/X7R

BC42

0.1UF

BC50

0.1UF

BC81

0.1UF

BC45

0.1UF

BC75

0.01UF

BC105

0.01UF

BC95

0.01UF

BC96

0.01UF

BC114

0.01UF

BC79

0.01UF

BC46

0.01UF

BC47

0.01UF

BC101

0.1UF

BC102

0.1UF

MC33

4.7UF

MC32

4.7UF

MC35

4.7UF

MC34

4.7UF

BC103

0.1UF

BC104

0.1UF

BC112

0.1UF

BC111

0.1UF

BC110

0.1UF

BC108

0.1UF

BC87

0.01UF

BC82

0.01UF

BC80

0.01UF

BC74

0.01UF

BC88

0.01UF

BC51

0.01UF

BC52

0.01UF

BC65

0.01UF

BC48

0.01UF

BC76

0.1UF

BC66

0.1UF

MC16

4.7UF

MC11

4.7UF

MC31

4.7UF

MC30

4.7UF

BC19

0.1UF

BC39

0.1UF

BC10

0.1UF

BC8

0.1UF

MC27

4.7UF

MC17

4.7UF

H7 HOLE A

1

2

3

4 5

6

7

8

MC12

4.7UF

BC40

0.1UF

BC67

0.1UF

BC11

0.1UF

BC77

0.1UF

BC20

0.1UF

MC25

4.7UF

BC84

0.1UF

BC121

0.1UF

BC138

0.1UF

BC132

0.1UF

BC131

0.1UF

BC149

0.01UF

BC124

0.01UF

BC147

0.01UF

BC150

0.01UF

BC116

0.1UF

BC113

0.1UF

BC115

0.1UF

MC57

2.2UF

BC122

0.1UF

BC106

0.1UF

BC109

0.1UF

BC107

0.1UF

BC100

0.1UF

BC128

0.1UF

BC158

0.01UF

BC160

0.01UF

BC159

0.01UF

BC144

0.01UF

BC145

0.1UF

BC146

0.1UF

BC169

0.01UF

BC171

0.01UF

BC183

0.01UF

BC170

0.01UF

BC182

0.01UF

BC186

0.01UF

BC187

0.01UF

BC181

0.01UF

EC33

22UF

BC85

0.1UF

BC83

0.1UF

EC27

22UF

BC41

0.1UF

BC53

0.1UF

BC69

0.1UF

BC70

0.1UF

EC28

22UF

BC156

0.1UF

BC142

0.1UF

EC36

22UF

BC168

0.1UF

BC180

0.1UF

EC26

22UF

BC167

0.1UF

BC179

0.1UF

BC143

0.1UF

BC157

0.1UF

BC91

0.01UF

BC93

0.01UF

BC98

0.01UF

BC97

0.01UF

BC92

0.01UF

BC208

0.1UF

BC212

0.1UF

BC211

0.1UF

BC210

0.1UF

BC209

0.1UF

MC59

2.2UF

BC207

0.1UF

H1 HOLE A

1

2

3

4 5

6

7

8

BC206

0.1UF

BC205

0.1UF

BC204

0.1UF

MC60

4.7UF

MC26

4.7UF

BC94

0.01UF

BC216

0.1UF

BC213

0.1UF

BC214

0.1UF

BC215

0.1UF

BC217

0.1UF

BC218

0.1UF

MC61

4.7UF

MC62

4.7UF

MC63

4.7UF

H8 HOLE A

1

2

3

4 5

6

7

8H9 HOLE A

1

2

3

4 5

6

7

8

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Internal Debug headers

32 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

R_SMBCLK

JPR_VID0

JPR_VID2

VID3

JPR_VID4

VID1

VID4

VID2

VID0

R_SMBDATA

JPR_VID1

JPR_VID3

VID[4:0]21,27,29

R_SMBCLK 6

GTLREF 4,7 GTLREFA 4 HUBREF_ICH 12 CONN_AGPREF 8,11

JPR_VID[4:0]3,29

BSEL#1 4,29

BSEL#0 4,29 R_SMBDATA 6

PANSWIN21,24

HWRST#24,25 SMBDATA 9,10,13,21,24,30

SMBCLK 9,10,13,21,24,30

VTT VTT VCC1_8 VCC3SBY VDDQ

J4

2x15 HDR

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

12

34

56

78

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

J6

HEADER_3

1

3

2

J7

HEADER_3

1

3

2

J8

HEADER_3

1

3

2

J9

HEADER_3

1

3

2

J10

HEADER_3

1

3

2

R396 0

R397 0

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

No-stuff C198 - debug site only

Stuff either R5 or R415. See p4.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Thermtrip

33 33

Thursday, November 29, 2001

Thursday, November 29, 2001

Document:

Page Name:

Revision:

Platform Applications Engineering

1900 Prairie City Road

Folsom, CA 95630

Last Revised:

Page No:

of

Page:

Doc:

Q52_R416

N6395404

Q51_Q52

THERMTRIP#4

PWRBTN# 13,21

CPURST#4,7

CPU_PWGD4,12

N6395403 4

VCC1_8 VCC1_8 V3SB

R412 1K

R413

510

R414

1.3k C198

X0.01uF

R415 0

Q52

2N3904

R416

2.2k

Q50

2N3904

Q51

2N3904

R408

0

R409

4.7k

R410

1K

R411

20k

www.s-manuals.com