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Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset
Universal Socket 370 Platform
Customer Reference Board Schematics
Revision 1.05 - Fab C
TITLE

3

C

4

PAGE

COVER SHEET

1

BLOCK DIAGRAM

2

PGA370 PART 1 & 2

3,4

AGTL TERMINATION

5

CLOCK GENERATOR

6

GMCH PART 1 & 2

7,8

DIMM 1 & 2

9

DIMM 3

10

AGP

11

ICH PART 1 & 2

12,13

PCI 1 & 2

14

PCI 3

15

VIDEO BUS & CONNECTOR

16

FWH & UDMA100 IDE 1-2

17

USB 0-3

18

AC97 CODEC

19

AUDIO I/O
LPC I/O CONTROLLER & FDCL

20

WOR, WOL & 2S1P

22

KB, MS, GAME & IR
FRONT PANEL & CNR

23

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
from future changes to them.
The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was
developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips
Electronics N.V. and North American Philips Corporation.

21

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

24

ATX POWER & H/W MONITOR

25

VREGS: VDDQ, VCC1_8, AND VTT
VREGS: VCCVID, V1_8SB

26

VREGS: DUALS, 3.3SB, 2.5, VCMOS

28
29

DECOUPLING CAPACITORS
INTERNAL DEBUG HEADERS

31

THERMTRIP

33

*Other brands and names may be claimed as the property of others.

30

Copyright© 2001, Intel Corporation

32

**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
Document:

1

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Title Page
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
1

A

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2

Intel®, Pentium®, Pentium® III, Celeron™, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in
the United States and other countries.

27

SYSTEM CONFIGURATION
PU/PDR & UNUSED GATES

3

C

D

E

of 33

1

A

B

C

D

E

BLOCK DIAGRAM
VRM

4

370-PIN SOCKET PROCESSOR

CLOCK

4

DATA

CTRL

ADDR

GTL BUS
DATA

CTRL

ADDR

AGP
Connector
3 DIMM
Modules

GMCH
Digital Video
3

3

Out Connector

IDE Secondary
PCI ADDR/DATA

ICH2
USB PORT 1-4

2

PCI CONN3

UDMA/100

PCI CONN 2

PCI CONN 1

PCI CNTRL

IDE Primary

USB

Note: PCI3
Connector is
not populated
on the board

FirmWare Hub

AC’97 LINK

2

CNR
Connector

Audio
Codec

SIO

Document:

1

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Block Diagram
Last Revised:

Floppy

Game Port

Keyboard

Serial 1

Serial 2

Parallel

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Mouse

Revision:
1.05
Page No:
2

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D

E

of 33

1

5

4

3

2

VTT

1

VCCVID
HA#[3..31]

7
7
7

AH26
AH22
AK28

RS#0
RS#1
RS#2

RS#0
RS#1
RS#2

Socket 370_9

370 - Pin Socket Part 1

7

HD#[0..63]

7

VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5

D

VCC3_3

RP3
R371

10K/8P4R

10K

C

R372

AL35 CPU_VID0
AM36CPU_VID1
AL37 CPU_VID2
AJ37 CPU_VID3
AK36CPU_VID4
AK18
AH16
AH18
AL19
AL17
C33
C31
A33
A31
E31
C29
VTT
E29
A29

1k

RP4
1
3
5
7
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

JPR_VID0
JPR_VID1
JPR_VID2
JPR_VID3
JPR_VID4

2
4
6
8

7
7
7
7
7

1K/8P4R

B

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: 370-pin Socket Part 1
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
3

5

4

3

2

29,32
29,32
29,32
29,32
29,32

AH20
AK16
AL21
AN11
AN15
G35
AL13
U37
U35
S37
S33
E23
AN21
AA35
AA33

Document:

A

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

2
4
6
8

AK8
AH12
AH8
AN9
AL15
AH10
AL9
AH6
AK10
AN5
AL7
AK14
AL5
AN7
AE1
Z6
AG3
AC3
AJ1
AE3
AB6
AB4
AF6
Y3
AA1
AK6
Z4
AA3
AD4
X6
AC1
W3
AF4

1
3
5
7

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
VID0
VID1
VID2
VID3
GND/VID4
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#

X36
GND
T36
GND
P36
GND
K36
GND
F36
GND
A37
GND
AC33
GND
Y37
GND

B

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AG5
GND
AC5
GND
Y5
GND
U5
GND
Q5
GND
L5
GND
G5
GND
D4
GND
B4
GND
AM6
GND
AJ7
GND
E7
GND
B8
GND
AM10
GND
AJ11
GND
E11
GND
B12
GND
AM14
GND
AJ15
GND
E15
GND
B16
GND
AM18
GND
AJ19
GND
E19
GND
F20
GND
B20
GND
AM22
GND
AJ23
GND
D22
GND
F24
GND
B24
GND
AM26
GND
AJ27
GND
D26
GND
F28
GND
B28
GND
AM30
GND
D30
GND
AF32
GND
AB32
GND
X32
GND
T32
GND
P32
GND
F32
GND
B32
GND
AH34
GND
AD34
GND
Z34
GND
V34
GND
R34
GND
M34
GND
H34
GND
D34
GND

C

W1
T4
N1
M6
U1
S3
T6
J1
S1
P6
Q3
M4
Q1
L1
N3
U3
H4
R4
P4
H6
L3
G1
F8
G3
K6
E3
E1
F12
A5
A3
J3
C5
F6
C1
C7
B2
C9
A9
D8
D10
C15
D14
D12
A7
A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16

AM34
GND
AH2
GND
AD2
GND
Z2
GND
V2
GND
M2
GND
D18
GND
H2
GND
D2
GND
AL3
GND

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID

U3A
D

HA#[3..31]

B26
C3
AK2
AF2
AB2
T2
P2
K2
F4
E5
AM4
AE5
AA5
W5
S5
N5
J5
F2
D6
B6
AM8
AJ9
E9
B10
AM12
AJ13
E13
B14
AM16
AJ5
AJ17
E17
B18
AM20
AJ21
D20
F22
AM24
AJ25
D24
F26
AM28
AJ29
D28
AK34
F30
B30
AM32
AH32
Z32
V32
R32
M32
H32
AF34
AB34
X34
T34
P34
K34
F34
B34
AH36
B22
V36
R36
H36
D36
D32
AD32
AH24
F14
K32
AA37
Y35

HD#[0..63]

1

of 33

A

5

4

3

2

1

BSEL#1
0
0
1
1

No-stuff R199 - see p.33.
VTT

Stuff either R5 or R415. See p33.

VCC2_5

R314

330 R373

R199 R15

R14

R13

R6

R5

R7

FSB
66M
100M
rsvd
133M
VCMOS

Place near AB36
D

BSEL#0
0
1
0
1

R9

R338

V3SB V3SB

R8

CMOSREF generation circuit
D

75 1%

BC1

CMOSREF
1K

1.8k

150

150

330

39

39

150

VTT

330
680

6

ITPCLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

U3B

R316
R317
0
R318

0

243,1%
VTT
R374

C

XHEADER_15X2

TDI
TDO
TRST#
TCK
TMS

J37
A35

PREQ#
PRDY#

G33
E37
C35
E35

BP2#
BP3#
BPM0#
BPM1#

14

33 N6395403
5

AN35
AN37
AN33
AL33
AK32

ITPRDY#

N33
N35
NCHCTRLP N37
Q33
Q35
Q37

RSRVD6
RSRVD7
RSRVD8
RSRVD9
RSRVD10
RSRVD11

AM2
F10
W35
Y1
R2
G37
L33
AL1

RSRVD13
RSRVD15
RSRVD16
RSRVD17
RSRVD18
RSRVD19
RSRVD20
RSRVD21

ITP_CPURESET
VTT
R319

VTT
R33
R340

243,1%
R342
26

X2
1k
DYN_OE

VTTPWRGD

12
APICD0
12
APICD1
6 APICCLK_CPU
6
CPUHCLK
12,33 CPU_PWGD
7,33
CPURST#

RESET2#
R345

1k
AG1_VTT/NC

R406

VTT

AN3
AK4
J35
L35
J33
W37
Y33
AK26
AH4
X4
AJ3
AG1

VCC2_5
C37

1k

Stuff resistor
only on non-UMB
platforms.

150,1%

Q27
FDN335N

PR6

R275

MC7

BC7

4.7UF

0.1UF

Do Not stuff C

Part2

RESVD21(BR1#)
DYN_OE
VTTPWRGD
PICD0
PICD1
PICCLK
BCLK
CLKREF
PWRGOOD
RESET#
RESET2#
RSVD - NC
EDGCTRL/VRSEL
CPUPRES#

150,1%

1K

R339

Debug sites only.

C12

0.1uF

BNR#
BPRI#
HTRDY#
DEFER#
HLOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#

7
7
7
7
7
7
7
7
7
7

BSEL0#
BSEL1#
RSRVD12/JBSEL1#

AJ33
AJ31
AK30

BSEL#0
BSEL#1

29,32
29,32

BR0#
THRMDP
THRMDN
THERMTRIP#

AN29
AL31
AL29
AH28

BR0#
VTIN2
THRMDN
THERMTRIP#

5
21,25
21,25
33

A20M#
STPCLK#
SLP#
SMI#
LINT0/INTR
LINT1/NMI
INIT#
FERR#
IGNNE#
IERR#

AE33
AG35
AH30
AJ35
M36
L37
AG33
AC35
AG37
AE35

A20M#
STPCLK#
CPUSLP#
SMI#
INTR
NMI
INIT#
FERR#
IGNNE#

12
12
12
12
12
12
12,17
12
12

PLL1
PLL2

W33
U33

RSP#
AP0#
AP1#
RP#

AC37
AL11
AN13
AN23

BINIT#
AERR#
BERR#
TUALDET
SLEWCNTR
RTTCNTR
VCOREDET

B36
AK24
V4
AF36
E27
S35
E21

PLL1
PLL2

C

Tua

VCC5
R341
2.2k

VCCVID

L2

33uF (C size)
C6

TUAL5

VCC5
Q25
2N7002

4.7UH/SMD-0805
VTT

6,7
B

R343
2.2k
R344
TUAL5#

Debug only!
R375
0

Q26
2N3904

1k

TUALDET
SLEWCNTR
RTTCNTR

Debug only! Do NOT place
jumper before removing
R375

PR1

PR5

JP6

56,%1

110,%1

JUMPER

GTLREF Generation Circuit
Use 0603 Packages and distribute
GTLREF Inputs ( 1 cap for every 2 inputs )
within 500 mils of processor

FB30BEAD
VTT
1
2

X18PF

BC228

150 1%

Socket 370_9

Place Site w/in 0.5"
of clock pin (W37)
C3
22

6,7,26 TUAL5

R4

1K

AH14
AN17
AN25
AN19
AK20
AN27
AL23
AL25
AL27
AN31
AE37FLUSH#

BNR#
BPRI#
TRDY#
DEFER#
LOCK#
DRDY#
HITM#
HIT#
DBSY#
ADS#
FLUSH#

370 - Pin Socket

PR4
Rds_on approx. 100
mOhm @5Vgs

R3

150

+

B

90.9,1%

1k

E33
F18
K4
R6
V6
AD6
AK12
AK22

0 ITP_DBRESET

R1

150
CMOSREF

VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7

R315

DBRESET#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

R2
GTLREFA

J2
AB36
AD36
Z36

25

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

0.1UF

V_CMOS
V1_5
V2_5

ITP_VTT

C163
R346

10PF

PR7
0.1uF

1k

GTLREFA

32

Document:

75,1%

A

GTLREFA
PR8
150,1%

BC18

BC17

BC16

0.1UF

0.1UF

0.1UF

GTLREF

7,32

R330
X0
Do not stuff R330
GTLREFA to CPU.
BC12
GTLREF to GMCH.
0.1UF

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: 370-pin Socket Part 2
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
4

5

4

3

2

1

of 33

A

5

4

3

2

1

D

D

VTT
R23

56

BR0#

4
R12

150

ITPRDY#

4

C

C

VTT

MC23
4.7UF

MC22
4.7UF

BC34

BC35

BC36

BC37

BC38

BC24

BC23

BC5

BC14

BC22

BC9

BC15

BC2

BC13

BC3

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

VTT

Do not populate in assembly - debug sites only.
Debug cap sites - place near processor
C164
820uF

B

B

VTT Decoupling

Document:

A

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: VTT Decoupling
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
5

5

4

3

2

1

of 33

A

A

B

VCC_CLOCK

1

C

PFB4
2

D

AV3

E

1

PFB2
2

MC18

BEAD

USBV3

VCC_CLOCK
BEAD

VCC_CLOCK

BC56

BC55

0.1UF

0.01UF

BC32 BC31
R249

PFB5
2

1

4

0.01UF

8.2K

PCIV3
MC28

BEAD

4.7UF

0.01UF

0.1UF

0.01UF

0.1UF

0.01UF

4.7UF

1

PFB1
2

MC19

BEAD

MEMV3

MC29 BC62 BC61 BC57 BC58 BC59 BC60
4.7UF

0.1UF

BC226 BC227 BC28 BC27 BC29 BC30 BC33 BC21 BC63 BC64

0.1UF

0.01UF

0.1UF

0.01UF

0.1UF

0.01UF

0.1UF

0.01UF

0.1UF

0.01UF

0.1UF

MC20
4.7UF

4.7UF

VCC_CLOCK
4

R347
0

1

VCC2_5

PFB11
2

R348
C35

U6

VDDL
VDDL

18PF

Y3
6

X1

7
4

X2
REF0

14.318MHZ

29 FMOD1
C33
R60

13 ICH_CLK14
13 ICH_3V66
8 GMCH_3V66
11 AGPCLK_CONN

18PF

10

12 PCLK_0/ICH

R64
R65
R66

33
33
33

10
11
12

3V66-0
3V66-1
3V66-2

R67
R290

33
33

15
16

PCICLK0
PCICLK1

18
28

FS0
FS1

21
22
23

PD#
SCLK
SDATA

29 FMOD0
13,21,28 SLP_S3#
32 R_SMBCLK
32 R_SMBDATA

R72

C39

C40

C41

C42

X10PF

X10PF

X10PF

X10PF

X10PF

GNDL
GNDL

C29

10

3
55

VCC3_3
Q29
FDN359AN

26 VTTPWRGD12

TUAL5

4,7,26

130

5
9
14
20
25
31
35
40
44
49

0.01UF

VDD
VDD
VDD
VDDA
VDD
VDD
VDD
VDD
VDD
VDD

0.1UF

2N7002

37
36
33
32

R320
R46
R45
R57
R58
8
6
4
2
RN19
8
6
4
2
RN20
R50
R51
R62
R63

33
33
33
33
33
7
5
3
1
22/8P4R
7
5
3
1
22/8P4R
22
22
22
22

SDRAM12

29

R44

22

48MHZ_0
48MHZ_1

26
27

R48
R49

33
33

R47

33

CPUCLK_0
CPUCLK_1
IOAPIC

54
53
1

SDRAM0
SDRAM1
SDRAM2
SDRAM3

51
50
47
46

SDRAM4
SDRAM5
SDRAM6
SDRAM7

45
42
41
38

SDRAM8
SDRAM9
SDRAM10
SDRAM11

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

4.7UF

Q28
2
56

MC21 BC25 BC26

ICS9250-28

ITPCLK
CPUHCLK
GMCHHCLK
MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3

4
4
7

APICCLK_ICH 12

MEMCLK4
MEMCLK5
MEMCLK6
MEMCLK7

3

MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11

MEMCLK[0..7]

8
13
17
19
24
30
34
39
43
48
52

BEAD

3

APICCLK_CPU 4

L_VCC2_5

C19

C21

C20

C133 C25

C24

C28

C30

X10PF

X10PF

X10PF

X10PF

X10PF

X10PF

X10PF

MEMCLK[8..11]
X10PF

DCLK_WR

7

USBCLK
DOTCLK

13
8

SIO_CLK24

21

MEMCLK[0..7] 9
MEMCLK[8..11] 10

VCC_CLOCK

2

PFB12
2
U29

MC66 BC221 BC222
4.7UF

0.1UF

R302

R303

10K

10K

0.01UF

PCLK_REF
MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3

MEMCLK4
MEMCLK5
MEMCLK6
MEMCLK7

4
13
9
8

FS1
FS2

1

REF

MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11

2
4
6
8

2
3
14
15

7
5
3
1

CLKB1
CLKB2
CLKB3
CLKB4

6
7
10
11

R277

8
6
4
2

33

CLKOUT

16

R312

X33

GND
GND
ICS9112B-17

C120

Document:

X10PF

Page Name: Clock Generator

X10P/8P4C
C34

C31

C23

C22

X10PF

X10PF

X10PF

X10PF

1
3
5
7

X10P/8P4C

PCLK_1
PCLK_2
PCLK_3
PCLK_7

14
14
15
21

PCLK_8

17

33/8P4R

CN5

1
3
5
7

1
3
5
7

1
3
5
7

X10P/8P4C

RN34
CLKA1
CLKA2
CLKA3
CLKA4

CN6

2
4
6
8
CN4

2
4
6
8

2
4
6
8

5
12

1

VDD
VDD

2
4
6
8

BEAD

Rds_on = 100 mOhm.

2
4
6
8

1

Ensure that the buffer used will disable
its PLL and tristate outputs when no
refclk is present; otherwise, must gate
power here, too.

1
3
5
7

VCC3_3

Clock power gate

C132

Last Revised:
1
3
5
7

2

X18PF

Intel(R) 815E Chipset Universal Socket 370 CRB
Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
6

A

B

C

D

E

of 33

1

5

VTT

4

Debug sites only.
1
2

VTT

FB31BEAD C168

9 SM_MAB#[4..7]

PR42
R61

0.1uF

32

U7A

63.4 1%
Place close
to GMCH
90.9,1%

GTLREF
PR43

D

150,1%

BC72

BC73

0.1UF

0.1UF

U6
AA10
AA7
H3
AA5
L4
M3
G1
N4
M5
J3
J1
K1
L3
K3

6
GMCHHCLK
16,17,21,30 PCIRST#
4,33
CPURST#
4
HLOCK#
4
DEFER#
HADS#

R407
56

4
4
4
4
4
4
4

Place
near GMCH

VTT
3

3

10 SM_MAC#[4..7]

HA#[3..31]

BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#
HA#[3..31]

C

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

R4
P1
T2
R3
N5
P5
R1
U1
P2
T1
T3
P3
T5
R5
V5
Y2
V3
W1
U4
V2
W3
W4
U5
Y5
Y3
U3
Y1
W5
V1

B

3
3
3
3
3

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

3 RS#0
3 RS#1
3 RS#2

GTLREFA
GTLREFB
HCLK
RESET#
CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

M1
N1
M2
L5
N3

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

K2
L1
H1

RS#0
RS#1
RS#2

Do Not Stuff C
Place Site w/in
0.5" of clock
ball(v6)

C38
X18PF

HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AA1
AB2
AF2
AD4
AB1
AB3
AA3
AC4
AC1
AF3
AD1
AE3
AD2
AD3
AF1
AA4
AD6
AC3
AE1
AB6
AF4
AE5
AC8
AB5
AF5
AC6
AF6
AD11
AF8
AD8
AD5
AB7
AF7
AD7
AB8
AE7
AE9
AB9
AF9
AD10
AF12
AB11
AB10
AD9
AC10
AF10
AD14
AD12
AB12
AE11
AE15
AF11
AF13
AB14
AF14
AB13
AB15
AE13
AC14
AD13
AD15
AF16
AF15
AC12

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#[0..63]

3

9,10 SM_MAA[0..12]

2

SM_MAB#[4..7]

9,10
9,10
9,10

SM_MD[0..63]

SM_MAA[0..12]

1
3
5
7

SM_MAB#4
SM_MAB#5
SM_MAB#6
SM_MAB#7

RN38
1
3
5
7

D13
B16
F12
A16
2
B12
4
A12
6
C11
8
A11
D12
C13
10/8P4R E11
A13
B7
10/8P4R
2
B15
4
A15
6
C14
8
A14
RN37

1
3
5
7
RN36

2
B10
4
A10
6
C10
8
A9
10/8P4R
B13
D11

SM_BS0
SM_BS1

SMAC4
SMAC5
SMAC6
SMAC7
SBS0
SBS1
SCSA#0
SCSA#1
SCSA#2
SCSA#3
SCSA#4
SCSA#5

SM_CSB#0
SM_CSB#1
SM_CSB#2
SM_CSB#3
SM_CSB#4
SM_CSB#5

F9
F8
D10
D9
B9
A8

SCSB#0
SCSB#1
SCSB#2
SCSB#3
SCSB#4
SCSB#5

C16
D18
E16

SRAS#
SCAS#
SWE#

D8
E8
E9
D7
C8
C7

SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5

F7
G10

DCLK_WR

VCC3SBY

SMAB#4
SMAB#5
SMAB#6
SMAB#7

D15
A17
D14
E14
E13
B17

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CKE4
SM_CKE5
6

SMAA0
SMAA1
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAA10
SMAA11
SMAA12

SM_CSA#0
SM_CSA#1
SM_CSA#2
SM_CSA#3
SM_CSA#4
SM_CSA#5

SM_RAS#
SM_CAS#
SM_WE#

9,10 SM_DQM[0..7]

SM_DQM[0..7]
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
PR9

D16
F15
A7
A6
A18
C17
B6
A5

40.2,1%

Host Interface

VCC3SBY

SM_MD[0..63] 9,10

U7B

SM_MAA0
SM_MAA1
SM_MAA2
SM_MAA3
SM_MAA4
SM_MAA5
SM_MAA6
SM_MAA7
SM_MAA8
SM_MAA9
SM_MAA10
SM_MAA11
SM_MAA12

SM_MAC#4
SM_MAC#5
SM_MAC#6
SM_MAC#7
9,10
9,10

1

SM_MAC#[4..7]

G7
C36

SCLK
RESVD
SDQM0
SDQM1
SDQM2
SDQM3
SDQM4
SDQM5
SDQM6
SDQM7

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8
SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63

D23
C23
D22
F21
E21
G20
F20
D20
F19
E19
D19
E18
B18
F18
G18
D17
A3
A1
C1
F2
G3
D6
C5
B4
D4
C2
D3
E4
F5
G4
J6
K5
A26
A25
B24
A24
B23
A23
C22
A22
D21
B21
A21
C20
B20
A20
C19
A19
A4
A2
B1
E1
G2
E6
D5
C4
B3
D2
E3
F4
F6
G5
H4
J4

SRCOMP
82815 GMCH

SYSTEM MEMORY
22PF

SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63

A

10 SM_CKE[4..5]
9 SM_CSA#[0..3]
10 SM_CSA#[4..5]
9 SM_CSB#[0..3]
10 SM_CSB#[4..5]

BC190

BC191

BC189

X0.1UF

X0.1UF

X0.1UF

X0.1UF
D

Backside decouping , should be
placed under chipset memory signal
field

VDDQ

BC192

BC193

BC194

BC195

X0.1UF

X0.1UF

X0.1UF

X0.1UF

C

Backside decouping , should be
placed under chipset AGP signal
field

SM_MAA12
R349
10k

4,6,26

SM_WE#
SM_MAA9
SM_CAS#
SBA7
SM_BS0
SM_BS1
SM_MAA10
SM_MAA11
SM_MAA12

Q30
2N7002

TUAL5

SM_WE#

R90

8.2K

SM_CAS#

R89

8.2K

R88

10K

SM_MAA9

SM_RAS#
9 SM_CKE[0..3]

BC188

R68

X10K

SM_MAA10

R77

X10K

SM_RAS#

Host Freq
FSB P-MOS
Host Freq
LM FREQ :

R_BSEL#0

29

R_REFCLK

29

: HI=100 LO=66
Kicker : HI=NON-Cu LO=Cu
: HI=133 LO=100/66
HI=133 LO=100

SM/LM muxing strap , active low
ALLZ : LO=ALLZ HI=Normal
IOQ depth : HI=4 LO=1
LO = Future 0.13u Socket 370 processors
HI = Pentium(R) III Processor or Intel(R)
Celeron(tm) Processor w/CPUID = 068Xh
XOR chain : LO=XOR HI=Normal

SM_CKE[0..3]

Document:

SM_CKE[4..5]

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: GMCH Part 1

SM_CSA#[0..3]

Last Revised:

SM_CSA#[4..5]
SM_CSB#[0..3]

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

SM_CSB#[4..5]

Revision:
1.05
Page No:
7

5

4

B

3

2

1

of 33

A

5

4

3

SBA[0..7]
HL[0..10]
FTD[0..11]
11

GAD[0..31]

GAD[0..31]

D

B

GAD0/LDQM0
GAD1/LMD4
GAD2/LMD7
GAD3/LMD3
GAD4/LMD6
GAD5/LMD2
GAD6/LMD5
GAD7/LMD1
GAD8/LMD0
GAD9/LMA4
GAD10/LDQM1
GAD11/LMA2
GAD12/LMD8
GAD13/LMA5
GAD14/LMD9
GAD15/LMA1
GAD/16/LMA8
GAD17/LMD14
GAD18/LMA11
GAD19/LMD15
GAD20/LMA9
GAD21/LMD16
GAD22/LCS#
GAD23/LMD17
GAD24/LCKE
GAD25/LMD18
GAD26/LCAS#
GAD27/LMD19
GAD28/LTCLK1
GAD29/LMD20
GAD30/LTCLK0
GAD31/LMD21

GCBE#0
GCBE#1
GCBE#2
GCBE#3

H23
N21
T25
Y26

GCBE#0/LMA3
GCBE#1/LMD10
GCBE#2/LMD13
GCBE#3/LRDS#

11
11
11
11
11
11
11
11
11

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

R26
P26
P23
P21
P25
R24
AE26
AD25
AC26

GFRAME#/LMA10
GDEVSEL#/LMD11
GIRDY#/LMD12
GTRDY#/LMA7
GSTOP#/LMA0
GPAR/LMA6
GREQ#/LMD27
GGNT#
PIPE#/LMD24

11
11
11
11
11
11

ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBSTB
SBSTB#

M22
L23
U22
V23
Y23
AA24

ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBSTB
SBSTB#

11
11
11

ST0
ST1
ST2

AD24
AC24
AC23

ST0/LMD28
ST1/LDQM3
ST2/LMD29

11
RBF#
11
WBF#
11,32 CONN_AGPREF
PR14

12

FTD[0..11]

16

AD26
AB24
J24
GRCOMP J26
OCLK R22
15.1%
RCLK P22

PR15

RBF#/LMD30
WBF#
AGPREF
GRCOMP
OCLOCK
RCLOCK

VDDQ VCC3SBY VCC1_8

LTVDATA0
LTVDATA1
LTVDATA2
LTVDATA3
LTVDATA4
LTVDATA5
LTVDATA6
LTVDATA7
LTVDATA8
LTVDATA9
LTVDATA10
LTVDATA11
BLANK#
TVCLKIN/SL_STALL
CLKOUT0
CLKOUT1
TVVSYNC
TVHSYNC

AD16
AF17
AE17
AD17
AF18
AD18
AF20
AD20
AC20
AF21
AE21
AD21
AB19
AC18
AE19
AF19
AC16
AB17

LTVCK
LTVDA

FTD0
FTD1
FTD2
FTD3
FTD4
FTD5
FTD6
FTD7
FTD8
FTD9
FTD10
FTD11

VCC1_8
L6

22nH
C169
33uF

FTBLNK#
SL_STALL
FTCLK0
FTCLK1
FTVSYNC
FTHSYNC

16
16
16
16
16
16

AB21
AA20

3VFTSCL
3VFTSDA

16
16

DDDA
DDCK

AA18
AB18

3VDDCDA
3VDDCCL

16
16

DCLKREF
IWASTE
IREF

AE24
Y20
AD23

DOTCLK

6

VSYNC
HSYNC
RED
GREEN
BLUE

AF22
AF23
AD22
AE22
AE23

CRT_VSYNC
CRT_HSYNC
VID_RED
VID_GREEN
VID_BLUE

16
16
16
16
16

HCLK
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HUBREF
HLSTB
HLSTB#
HCOMP

SBA0/LMD31
SBA1/LMD25
SBA2/LDQM2
SBA3/LMD26
SBA4/LMD23
SBA5/LWE#
SBA6/LMD22
SBA7/LGM_FREQ_SEL

R251

22

C170
0.1uF

C171
0.01uF

C58
10PF

F22
H24
H26
H25
G24
F24
E26
E25
D26
D25
D24
C26
H21
G25
F26
H20

GMCH_3V66
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HUBREF_GMCH
HCOMP

HLSTB
HLSTB#

Do Not Stuff C
Place Site w/in 0.5"
of clock ball(AA21)

6
VCC1_8
PR18

40.2,1%

Place R as
Close as
possible to
GMCH

12
12
VCC1_8

AB22
AB25
AB23
AB26
AA22
AA26
Y22
Y25

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

11
11
11
11
11
11
11
11

PR16
301,1%

C61

0.1UF

15PF/5%,MPO

PR13

BC90

PR17

174,1%

0.1UF

301,1%

AA21
Y7
E23
AF26
AF25

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

B2
B5
B8
B11
B14
B19
B22
B25
E2
F10
F14
F17
G6
G8
G19
H2
H5
H7

VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY

K20
Y24
L21
M23
U25
N25
R21
U20
U23
W20

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND

Power and Ground
Place as close as
Possible to GMCH
and via straight
to VSS plane

OCLK = 0.5"
RCLK = 1.5"

U7E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AB4
E7
AC2
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC25
AE2
AE4
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
B26
C3
C6
C9
C12
C15
C18
C21
C24
D1
E5
E10
E12
E15
E17
E20
E22
F1
F3
F11
F13
T21
U2
U7
K24
V4
V6
V20
V22
W2
W7
W23
W25
Y4
Y6
Y8
Y10
Y17
Y19
AA2
AA9
AA12
AA14
AA16

P11
P12
P13
P14
P15
P16
R2
R6
R11
R12
R13
R14
R15
R16
R23
R25
T4
T11
T12
T13
T14
T15
T16
L15
L16
L22
M4
M11
M12
M13
M14
M15
M16
L25

D

N2
N6
N11
N12
N13
N14
N15
N16
N23
AA23
F16
F25
G9
G17
G21
G23
P24
H6
H22
J2
J5
J23
J25
K4
K7
K21
L2
L6
L11
L12
L13
L14
AA25
P4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C

Solano

VDDQ
C69
B

560PF
PR21

PR23

82,1%

1K,1%

PR24

PR22

GMCH_AGPREF 11

82,1%

1K,1%
C72
560PF

82815 GMCH

Display Cache, Video, and
HUB Interface
NOTE :

VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8

AF24
AE25

40.2,1%

A

W6
Y9
Y18
AA6
AA8
AA11
AA13
AA15
AA17
AA19
AB16
AB20
AC22
AD19
C25
E24
F23
G22
J7
K6
M6
P6
T6
V7
G26

82815 GMCH

BC89

1

U7D

K26
J22
K25
J21
L24
J20
L26
K23
K22
M25
M24
M26
M21
N24
N22
N26
T26
T22
U24
T23
U26
T24
V24
U21
V25
V21
V26
W21
W24
W22
W26
Y21

11
11
11
11

11

HL[0..10]

U7C

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

C

SBA[0..7]

2

Place as close as
Possible to GMCH
and via straight
to VSS plane

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: GMCH Part 2
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
8

5

4

3

2

1

of 33

A

A

B

VCC3SBY

C

VCC3SBY

SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8

4

SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#0
3

SM_MAA0
SM_MAA2
SM_MAA4
SM_MAA6
SM_MAA8
SM_MAA10
SM_BS1
MEMCLK0
SM_CSB#0
SM_DQM2
SM_DQM3

SM_MD16
SM_MD17
SM_MD18
SM_MD19

2

SM_MD20
SM_CKE1
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
MEMCLK2
1

SMBDATA
SMBCLK

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

E

VCC3SBY
DIMM2

DIMM1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

SM_MD0
SM_MD1
SM_MD2
SM_MD3

D

VCC3SBY

VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
VSS
A1
A3
A5
A7
A9
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
VSS
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
VREF/DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3/NC
NC
SA0
SA1
SA2
VDD

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

SM_MD32
SM_MD33
SM_MD34
SM_MD35

SM_MD0
SM_MD1
SM_MD2
SM_MD3

SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40

SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8

SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45

SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13

SM_MD46
SM_MD47

SM_MD14
SM_MD15

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#1
SM_RAS#

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#2

SM_MAA1
SM_MAA3
SM_MAA5
SM_MAA7
SM_MAA9
SM_BS0
SM_MAA11

SM_MAA0
SM_MAA2
SM_MAB#4
SM_MAB#6
SM_MAA8
SM_MAA10
SM_BS1

MEMCLK1
SM_MAA12

MEMCLK4

SM_CKE0
SM_CSB#1
SM_DQM6
SM_DQM7

SM_CSB#2
SM_DQM2
SM_DQM3

SM_MD48
SM_MD49
SM_MD50
SM_MD51

SM_MD16
SM_MD17
SM_MD18
SM_MD19

SM_MD52

SM_MD20

SM_MD53
SM_MD54
SM_MD55

SM_MD21
SM_MD22
SM_MD23

SM_MD56
SM_MD57
SM_MD58
SM_MD59

SM_MD24
SM_MD25
SM_MD26
SM_MD27

SM_MD60
SM_MD61
SM_MD62
SM_MD63

SM_MD28
SM_MD29
SM_MD30
SM_MD31

SM_CKE3

MEMCLK3

MEMCLK6
SMBDATA
SMBCLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
VSS
A1
A3
A5
A7
A9
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
VSS
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
VREF/DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3/NC
NC
SA0
SA1
SA2
VDD

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#3
SM_RAS#

SM_MAA[0..12] 7,10

SM_MD[0..63]

SM_MD[0..63] 7,10

SM_MAB#[4..7]

SM_MAB#[4..7] 7

SM_DQM[0..7]

SM_DQM[0..7] 7,10

MEMCLK[0..7]

MEMCLK[0..7] 6

SM_CKE[0..3]

SM_CKE[0..3] 7

SM_CSA#[0..3]

SM_CSA#[0..3] 7

SM_CSB#[0..3]

SM_CSB#[0..3] 7

SM_WE#

SM_WE#

7,10

SM_RAS#

SM_RAS#

7,10

SM_CAS#

SM_CAS#

7,10

SM_BS0

SM_BS0

7,10

SM_BS1

SM_BS1

7,10

SMBDATA
SMBCLK

SMBDATA
SMBCLK

10,13,21,24,30,32
10,13,21,24,30,32

4

3

SM_MAA1
SM_MAA3
SM_MAB#5
SM_MAB#7
SM_MAA9
SM_BS0
SM_MAA11
MEMCLK5
SM_MAA12
SM_CKE2
SM_CSB#3
SM_DQM6
SM_DQM7
VCC3SBY
R28
2.2K
SM_MD48
SM_MD49
SM_MD50
SM_MD51

2

DM_SA_PU

10

SM_MD52

SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
MEMCLK7

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: DIMMs 1 and 2
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

DIMM168

DIMM168

SM_MAA[0..12]

Revision:
1.05
Page No:
9

A

CH6-12

B

C

D

E

of 33

1

A

B

C

VCC3SBY

D

E

VCC3SBY
DIMM3

7,9 SM_MAA[0..12]
7,9 SM_MD[0..63]
7

SM_MAC#[4..7]

7,9 SM_DQM[0..7]

4

6

MEMCLK[8..11]

7

SM_CKE[4..5]

7 SM_CSA#[4..5]
7 SM_CSB#[4..5]
7,9

SM_WE#

7,9

SM_RAS#

7,9

SM_CAS#

7,9

SM_BS0

7,9

SM_BS1

9,13,21,24,30,32 SMBDATA
9,13,21,24,30,32 SMBCLK
3

SM_MAA[0..12]
SM_MD[0..63]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

SM_MD0
SM_MD1
SM_MD2
SM_MD3

SM_MAC#[4..7]
SM_DQM[0..7]
MEMCLK[8..11]
SM_CKE[4..5]
SM_CSA#[4..5]
SM_CSB#[4..5]
SM_WE#

SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15

SM_RAS#
SM_CAS#
SM_BS0
SM_BS1
SMBDATA
SMBCLK

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#4
SM_MAA0
SM_MAA2
SM_MAC#4
SM_MAC#6
SM_MAA8
SM_MAA10
SM_BS1
MEMCLK8
SM_CSB#4
SM_DQM2
SM_DQM3

SM_MD16
SM_MD17
SM_MD18
SM_MD19

2

SM_MD20
SM_CKE5
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
MEMCLK10
1

9

DM_SA_PU
SMBDATA
SMBCLK

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
VSS
A1
A3
A5
A7
A9
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
VSS
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
VREF/DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3/NC
NC
SA0
SA1
SA2
VDD

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40

4

SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#5
SM_RAS#
3

SM_MAA1
SM_MAA3
SM_MAC#5
SM_MAC#7
SM_MAA9
SM_BS0
SM_MAA11
MEMCLK9
SM_MAA12
SM_CKE4
SM_CSB#5
SM_DQM6
SM_DQM7

SM_MD48
SM_MD49
SM_MD50
SM_MD51

2

SM_MD52

SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
MEMCLK11

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: DIMM 3
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

DIMM168

Revision:
1.05
Page No:
10

A

B

C

D

E

of 33

1

A

B

C

D

VCC3_3
VCC5

E

VCC12
VCC12
VDDQ

R106
2.2K
4

4

VDDQ
18

GSERR#
GPAR
GPERR#
GDEVSEL#

1
3
5
7

RN49
2
4
6
8

GFRAME#
GIRDY#
GTRDY#
GSTOP#

1
3
5
7

8.2K/8P4R
RN48
2
4
6
8

1
3
5
7

8.2K/8P4R
RN42
2
4
6
8

GREQ#
GGNT#
ST0
ST1

SBA0
SBA1
SBA2
SBA3

SBA7
SBA6

18

AGP_OC#

AGPUSBP

14,15,30 PIRQ#B
6 AGPCLK_CONN
8
GREQ#
8
8
8

GREQ#
ST0
ST2
RBF#

ST0
ST2
RBF#

SBA0

8

SBA2
SBSTB

SBSTB

SBA4
SBA6
V3SB

8.2K/8P4R
RN43
2
4
6
8

3

ST2
RBF#
PIPE#
WBF#

AGP1

1
3
5
7

1
3
5
7

1
3
5
7

8.2K/8P4R
RN44
2
4
6
8
8.2K/8P4R
RN46
2
4
6
8

GAD31
GAD29
GAD27
GAD25
8

ADSTB1
GAD23

ADSTB1

GAD21
GAD19
GAD17
8

GCBE#2

8

GIRDY#

GIRDY#

8.2K/8P4R

2

ADSTB0
ADSTB0#
ADSTB1
ADSTB1#

8.2K
8.2K
8.2K
8.2K

SBSTB#
SBSTB
SBA5
SBA4

1
3
5
7

R332
R333
R334
R335

GDEVSEL#

8 GDEVSEL#

GPERR#
GSERR#

RN45
2
4
6
8

8

GCBE#1
GAD14
GAD12
GAD10
GAD8

8.2K/8P4R
8

ADSTB0
GAD7

ADSTB0

GAD5
GAD3
GAD1
8 GMCH_AGPREF

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66

OVRCNT#
5V_A
5V_B
USB+
GND_K
INTB#
CLK
REQ#/DQ27
VCC3.3_F
ST0/DQ28
ST2/DQ29
RBF#/DQ30
GND_L
RESV_H
SBA0/DQ31
VCC3.3_G
SBA2/DQM2
SB_STB
GND_M
SBA4/DQ23
SBA6/DQ22
RESV
GND_N
3.3VAUX1
VCC3.3_H
AD31/DQ21
AD29/DQ20
VCC3.3_I
AD27/DQ19
AD25/DQ18
GND_O
AD_STB1
AD23/DQ17
VDDQ_F
AD21/DQ16
AD19/DQ15
GND_P
AD17/DQ14
C/BE2#/DQ13
VDDQ_G
IRDY#/DQ12
3.3VAUX2
GND_Q
RESV_K
VCC3.3_J
DEVSEL#/DQ11
VDDQ_H
PERR#
GND_R
SERR#
C/BE1#/DQ10
VDDQ_I
AD14/DQ9
AD12/DQ8
GND_S
AD10/DQM1
AD8/DQ0
VDDQ_J
AD_STB0
AD7/DQ1
GND_T
AD5/DQ2
AD3/DQ3
VDDQ_K
AD1/DQ4
VREF_CG

12V
TYPEDET#
RESV_A
USBGND_A
INTA#
RST#
GNT#
VCC3.3_A
DQM3/ST1
RESV_B
DQ24/PIPE#
GND_B
WBF#
DQ25/SBA1
VCC3.3_B
DQ26/SBA3
SB_STB#
GND_C
WE#/SBA5
M_FREQ_SEL/SBA7
RESV_C
GND_D
RESV_D
VCC3.3_C
TCLK0/AD30
TCLK1/AD28
VCC3.3_D
CAS#/AD26
AD24
GND_E
AD_STB1#
RAS#/C/BE3#
VDDQ_A
A0/AD22
A9/AD20
GND_F
A11/AD18
A8/AD16
VDDQ_B
A10/FRAME#
RESV_E
GND_G
RESV_F
VCC3.3_E
A7/TRDY#
CS#/STOP#
PME#
GND_H
A6/PAR
A1/AD15
VDDQ_C
A5/AD13
A2/AD11
GND_I
A4/AD9
A3/C/BE0#
VDDQ_D
AD_STB0#
DQ5/AD6
GND_J
DQ6/AD4
DQ7/AD2
VDDQ_E
DQM0/AD0
VREF_GC

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

TYPEDET#

GGNT#
ST1
PIPE#
WBF#
SBA1
SBA3
SBSTB1#

26

AGPUSBN

18

PIRQ#A
PCI_RST#
GGNT#

14,15,30
14,15,30
8

ST1

8

PIPE#

8

WBF#

8

SBSTB#

8

SBA5
SBA7
3

GAD30
GAD28
GAD26
GAD24
ADSTB1#

ADSTB1#
GCBE#3

8
8

GFRAME#

8

GTRDY#
GSTOP#
PCI_PME#

8
8
12,14,15,22

GPAR

8

GAD22
GAD20
GAD18
GAD16
GFRAME#

GTRDY#
GSTOP#
GPAR
GAD15

VDDQ

GAD13
GAD11

2

PR20

Place close
to GMCH

301,1%

CON_AGPREF

GAD9
ADSTB0#
GAD6

GCBE#0

8

ADSTB0#

8

PR19
200,1%

GAD4
GAD2
Q13
2N7002

GAD0
CONN_AGPREF 8,32

AGP4XU_20

Document:

1

8

GAD[0..31]

8

SBA[0..7]

GAD[0..31]

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: AGP
Last Revised:

SBA[0..7]

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
11

A

CH6-18

B

C

D

E

of 33

1

C

C_BE#0
C_BE#1
C_BE#2
C_BE#3

AA3
AB6
Y8
AA9

PCLK_0/ICH
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
ICHRST#
PLOCK#
PAR
SERR#
PERR#
PCI_PME#

W11
V3
AB7
W8
V4
W1
AA15
AA7
W2
W7
Y7
Y15

30

PCI_REQ#A

M3
L2

30
30
30
30
17
17
30
24
21,30

ICH_IRQ#E
ICH_IRQ#F
ICH_IRQ#G
ICH_IRQ#H
P66DET
S66DET
GPI8
EXTSMI#
LPC_PME#

N3
N2
N1
M4
Y11
AA11
Y14
W14
AB15
A15
D14
C14
L1
B14
A14
AB14
AA14

14,15
14,15
14,15
14,15
6
14,15,30
C101
14,15,30
14,15,30
10PF
14,15,30
NPOP
14,15,30
30
14,15,30
14,15
14,15,30
14,15,30
11,14,15,22

VCCCS1
VCCCS2
VCCCS3

C_BE#0
C_BE#1
C_BE#2
C_BE#3
PCICLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PCIRST#
PLOCK#
PAR
SERR#
PERR#
PCI_PME#

A

1

H5
J5
VCCAX1
VCCAX2

V17
V18
VCCUSB1
VCCUSB2

F5
G5
VCCPX1
VCCPX2

U18
T18

D2

D10
E5
K19
L19
P5
V9

H18
J18
P18
R18
R5
T5
U5
V5
V6
V7
V8

E14
E15
E16
E17
E18
F18
G18

2

V1_8SB V1_8SB

HL[0..10]
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGOD

PIRQ#E/GPI2
PIRQ#F/GPI3
PIRQ#G/GPI4
PIRQ#H/GPI5
GPI6
GPI7
GPI8
GPI12
GPI13
GPO18
GPO19
GPO20
GPO21
GPOD22
GPO23
GPIOD27
GPIOD28

HL[0..10]

8

A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
KBRST#
A20GATE
CPU_PWGD

4
4
4
4
4,17
4
4
4
4
21,30
21,30
4,33

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HLSTB
HLSTB#
HCOMP
HUBREF

A4
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3
B4

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D

P1
P2
P3
N4

ICH_IRQ#A
ICH_IRQ#B
ICH_IRQ#C
ICH_IRQ#D

30
30
30
30

IRQ14
IRQ15
APICCLK
APICD1
APICD0
SERIRQ

F21
C16
N20
N19
P22
N21

IRQ14
IRQ15
APICCLK_ICH
APICD1
APICD0
SERIRQ

17
17
6
4
4
21,30

R2
R3
T1
AB10
P4
L3

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

14,30
14,30
15,30
30
30
30

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4
GNT#B/GPO17/GNT#5

M2
M1
R4
T2
R1
L4

PGNT#0
PGNT#1
PGNT#2

14
14
15

LAN_RXD0
LAN_RXD1
LAN_RXD2

G2
G1
H1

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

F3
F2
F1

24
24
24
RN69
1
3
5
7

LAN_RSTSYNC
LAN_CLK

H2
G3

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
REQ#B/GPI1/REQ#5

REQ#A/GPI0
GNT#A/GPO16

D11
A12
R22
A11
C12
C11
B11
B12
C10
B13
C13
A13

A1
VSS0
A10
VSS1
A2
VSS2
A21
VSS3
A22
VSS4
AA1
VSS5
AA2
VSS6
AA21
VSS7
AA22
VSS8
AB1
VSS9
AB2
VSS10
AB21
VSS11
AB22
VSS12
B1
VSS13
B10
VSS14
B2
VSS15
B21
VSS16
B22
VSS17
B3
VSS18
B9
VSS19
C2
VSS20
C3
VSS21
C4
VSS22
C9
VSS23
D3
VSS24
D5
VSS25
D6
VSS26
D7
VSS27
D8
VSS28
D9
VSS29
E6
VSS30
E7
VSS31
E8
VSS32
E9
VSS33
J10
VSS34
J11
VSS35
J12
VSS36
J13
VSS37
J14
VSS38
J9
VSS39
K1
VSS40
K10
VSS41
K11
VSS42
K12
VSS43
K13
VSS44
K14
VSS45
K9
VSS46
L10
VSS47
L11
VSS48
L12
VSS49
L13
VSS50
L14
VSS51
L9
VSS52
M9
VSS53
M10
VSS54
M11
VSS55
M12
VSS56
M13
VSS57
M14
VSS58
N9
VSS59
N10
VSS60
N11
VSS61
N12
VSS62
N13
VSS63
N14
VSS64
P9
VSS65
P10
VSS66
P11
VSS67
P12
VSS68
P13
VSS69
P14
VSS70

17
GPIO23
30
GPIO27
24,29 PRI_DWN#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VCCPS1
VCCPS2

AA4
AB4
Y4
W5
W4
Y5
AB3
AA5
AB5
Y3
W6
W3
Y6
Y2
AA6
Y1
V2
AA8
V1
AB8
U4
W9
U3
Y9
U2
AB9
U1
W10
T4
Y10
T3
AA10

VCC1_8 V3SB V3SB V3SB

VCCA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

D

B

U12A
82801BA ICH2
AD[0..31]

VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20

AD[0..31]

VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8

14,15

3

VCC1_8

V14
V15
V16

4

VCC3_3

VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6

5

D

VCC1_8

HLSTB
HLSTB#

PR27 Place R as
Close as
40.2,1%possible to
ICH

8
8

HUBREF_ICH

U12_RN69-1
U12_RN69-3
U12_RN69-5
U12_RN69-7

HUBREF_ICH 32
VCC1_8

PR25
301,1%

BC119

PR26

0.01UF

301,1%

B

Place as close as
Possible to ICH
and via straight
to VSS plane

22/8P4R
2
4
6
8

LAN_TXD0
LAN_TXD2
LAN_TXD1

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: ICH2 Part 1
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:
1.05
Page No:
12

4

3

2

24
24
24

LAN_RSTSYNC 24
LAN_CLK
24

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
5

C

1

of 33

A

A

B

C

VCC3_3

V3SB
6

ICH_CLK14

R141

3
3

D19

R134

VCC5

VCCRTC

E

VCC5SBY

VCMOS

10

Q16
2N7002

C96

BC197
D18

X10P

1K

0.1UF
SS12/SMD

BAT54C

R129

1

2

D

R325

1K

VCC5

1K

4

4

A

C172
2
1.0uF

B

Y

ICH_PWROK

4
R174

JP1
1
2
3

R174_JP1

15K

741G08 AND
3

C113
1.0UF

D12

21,33 PWRBTN#
22,30 ICH_RI#
21
RSMRST#
21
SUSCLK
9,10,21,24,30,32 SMBDATA
9,10,21,24,30,32 SMBCLK
30
SMBALERT#
21,25 CASEOPEN#

CCM0S
R187

21,25 PWROK

1K

SS12/SMD
R181

1K

R377 0

3

C110
Debug only - do
not stuff

6
6

0.047UF

M19
P20
D4

CLK14
CLK48
CLK66

VBIAS
RTCX1
RTCX2
RTCRST#

T21
U22
T22
T20

VBIAS
RTCX1
RTCX2
RTCRST#

AC_RST#
AC_SYNC
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
ICH_SPKR

V22
P19
R19
P21
Y22
W22
N22

USBCLK
ICH_3V66

BAT1
BATTERY
R162
24,29
19,24
19,24
19,24,29
X18PF
19,24,30
24,30
19,24,29
C88

10M
R149

10M
Y2

32.768KHZ
C103

C102

18PF

18PF

2

USBOC#2-3

24
24
24
24

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4
LDRQ#0
LDRQ#1

W17
Y18
AB19
AA19
W18
Y19
AB20
AA20

USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N

W19
Y20
Y21
W20
K4
K3
J4
J3

R271

R164

560K

560K 47PF/8P4C

CP1

1

OC#0
OC#1
OC#2
OC#3
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

2
4
6
8

USBOC#0-1

18

LDRQ#0

Y12
W12
AB13
AB12
AB11
Y13
W13

M20
K2

V19

1.0UF

PDCS#1
SDCS#1
PDSC#3
SDCS#3

E21
C15
E19
D15

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

F20
F19
E22
A16
D16
B16

PDDREQ
SDDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY

G22
B18
F22
B17
G19
D17
G21
C17
G20
A17

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

SMLINK0
SMLINK1
VRMPWRGD
TP0
FS0

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDD[0..15]
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDD[0..15]

U19
V20
B15
U20
AA12

SS12/SMD

PDCS#1
SDCS#1
PDCS#3
SDCS#3
PDA[0..2]

17
17
17
17
17

SDA[0..2]
PDREQ
SDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY

17
17
17
17
17
17
17
17
17
17
17

PDD[0..15]

17

3

2

VCC3_3

R403
V3SB

1K
SDD[0..15]
SMLINK0
SMLINK1

17
15,30
15,30
VRM_PWRGD 27

Document:

R324

1K

Intel(R) 815E Chipset Universal Socket 370 CRB

1
3
5
7

47PF/8P4C

Page Name: ICH2 Part 2
82801BA ICH2

Last Revised:

1
3
5
7

1
3
5
7

D8

0.1UF

PDA[0..2]
PDA0
PDA1
PDA2
SDA0
SDA1
SDA2
SDA[0..2]

CP2

1
3
5
7

BC125

2
4
6
8

18

RN71 15/8P4R
1
2
3
4
5
6
7
8

21

RN70 15/8P4R
1
2
3
4
5
6
7
8

2
4
6
8

USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N

LAD0
LAD1
LAD2
LAD3
LFRAME#

2
4
6
8

18
18
18
18
18
18
18
18

17,21
17,21
17,21
17,21
17,21

AC_RST#
AC_SYNC
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
SPKR

C91

V5R1
V5R2

21,30 OVT#
6,21,28 SLP_S3#
28
SLP_S5#

U33

GPIO25
GPIO24
THRM#
SLP_S3#
SLP_S5#
PWROK
RSM_PWROK
PWRBTN#
RI#
RSMRST#
SUS_STAT#
SUSCLK
SMBDATA
SMBCLK
SMBALTER#/GPI11
INTRUDER#

V5R_SUS

5
1

GND Vcc

R376 43k

W15
V21
AA13
W16
AB18
R20
Y16
W21
AA17
R21
Y17
AA18
AA16
AB16
AB17
T19

GPIO25

D12
D13

U12B
30

VCCRTC

Target 20ms after
VCC_CLOCK is
powered

U21

1.0UF

VCC_CLOCK

VCPU1
VCPU2

1

2

VCC3_3
C104
VCC3_3

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
13

A

B

C

D

E

of 33

1

A

B

C

D

E

V3SB
V3SB
VCC3_3

VCC3_3

VCC5
VCC3_3

VCC5

VCC3_3

VCC5

VCC12-

VCC5
VCC12-

VCC12

VCC12

4

4

PCI1

11,15,30 PIRQ#B
15,30
PIRQ#D

6
12,30

PCLK_1
PREQ#0
AD31
AD29

3

AD27
AD25
C_BE#3
AD23
AD21
AD19
AD17
C_BE#2
12,15,30

IRDY#

12,15,30 DEVSEL#
12,15,30 PLOCK#
12,15,30 PERR#
12,15,30

PERR#

SERR#
C_BE#1
AD14

2

AD12
AD10

AD8
AD7
AD5
AD3
AD1
ACK64#

15,30 ACK64#

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

PCI2
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+5V(I/O)
RESERVED
GND
GND
RESERVED
RST#
+5V(I/O)
GNT
GND
PME#
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

C/BE#0
+3.3V
AD6
AD4
GND
AD2
AD0
+5V(I/O)
REQ64#
+5V
+5V

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PIRQ#A
PIRQ#C

AD30

11,15,30
15,30

PCI_RST#

11,15,30

PGNT#0

12

PCI_PME#

11,12,15,22

AD28
AD26

PIRQ#C
PIRQ#A

6

PCLK_2

12,30

PREQ#1
AD31
AD29
AD27
AD25

AD24
R_AD16

R133
100

AD16

AD22
AD20

C_BE#3
AD23
AD21
AD19

AD18
AD16

AD17
C_BE#2
FRAME#

12,15,30

TRDY#

12,15,30

STOP#

12,15,30

PAR

12,15

IRDY#
DEVSEL#
PLOCK#
PERR#
SERR#

AD15
AD13
AD11

C_BE#1
AD14
AD12
AD10

AD9
C_BE#0

AD8
AD7

AD6
AD4

AD5
AD3

AD2
AD0

AD1
REQ64#1

ACK64#

30

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

PCI_CON_32BIT

12,15

AD[0..31]

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

C/BE#0
+3.3V
AD6
AD4
GND
AD2
AD0
+5V(I/O)
REQ64#
+5V
+5V

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PIRQ#B
PIRQ#D

PCI_RST#
PGNT#1

12

PCI_PME#
AD30
AD28
AD26

3

AD24
R_AD17

R142 AD17
100

AD22
AD20
AD18
AD16
FRAME#
TRDY#
STOP#

PAR
AD15
AD13
AD11

2

AD9
C_BE#0
AD6
AD4
AD2
AD0
REQ64#2

30

PCI_CON_32BIT

AD[0..31]

Document:

1

12,15 C_BE#[0..3]

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+5V(I/O)
RESERVED
GND
GND
RESERVED
RST#
+5V(I/O)
GNT
GND
PME#
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9

C_BE#[0..3]

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: PCI 1 and 2
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
14

A

B

C

D

E

of 33

1

A

B

C

D

E

V3SB
VCC3_3

VCC3_3
VCC5

VCC5

VCC12-

VCC12

4

4

PCI3

14,30
PIRQ#D
11,14,30 PIRQ#B

6

PCLK_3

12,30

PREQ#2
AD31
AD29

3

AD27
AD25
C_BE#3
AD23
AD21
AD19
AD17
C_BE#2
12,14,30

IRDY#

12,14,30 DEVSEL#
12,14,30 PLOCK#
12,14,30 PERR#
12,14,30

PERR#

SERR#
C_BE#1
AD14

2

AD12
AD10

AD8
AD7
AD5
AD3
AD1
ACK64#

14,30 ACK64#

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+5V(I/O)
RESERVED
GND
GND
RESERVED
RST#
+5V(I/O)
GNT
GND
PME#
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

C/BE#0
+3.3V
AD6
AD4
GND
AD2
AD0
+5V(I/O)
REQ64#
+5V
+5V

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PIRQ#C
PIRQ#A

AD30

14,30
11,14,30

PCI_RST#

11,14,30

PGNT#2

12

PCI_PME#

11,12,14,22

AD28
AD26

3

AD24
R_AD18

R148
100

AD18

AD22
AD20
AD18
AD16

AD15

FRAME#

12,14,30

TRDY#

12,14,30

STOP#

12,14,30

SMLINK0
SMLINK1

13,30
13,30

PAR

12,14

AD13
AD11

2

AD9
C_BE#0
AD6
AD4
AD2
AD0
REQ64#3

30

PCI_CON_32BIT

1

12,14

Document:

AD[0..31]

AD[0..31]

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: PCI 3
C_BE#[0..3]

12,14 C_BE#[0..3]

Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
15

A

B

C

D

E

of 33

1

A

B

C

D

E

VCC5
VCC5 VCC1_8

F5

BC68

FUSE_1.0A

0.22UF

BC223
0.22UF
4

4

VFB3
VID_RED

1

F5_FB11

2

R73
1K

BEAD
C49

C50

75,1%

3.3PF

VID_GREEN

1

2
BEAD

PR11
75,1%

3

VID_BLUE

VCC3

SD2

16

2

VCC1

SD1

15

1

RV
MONOPU
GV
DDCDA

3

VIDEO_1

SYNC_OUT2

14

4

VIDEO_2

SYNC_IN2

13

5

VIDEO_3

SYNC_OUT1

12

6

GND

SYNC_IN1

11

7

POWER_UP

DDC_OUT2

10

R321

10

8

VCC2

DDC_OUT1

9

R322

10

R87

33

X10PF

3.3PF
VFB1

8

VGA1

1

C46

C47

2

BV
HS
MON2PU
VS

R85
BEAD
PR10

C43

C45

BC224 BC225

75,1%

3.3PF

X10PF

0.22UF0.22UF

PAC-VGA201/QSOP

33

DDCCL

3VDDCDA
3VDDCCL
CRT_HSYNC
CRT_VSYNC

8
8

3VFTSDA
3VFTSCL

3
4
7
8
11
14
17
18
21
22
1
13

2

VCC
1B1
1A1
1B2
1A2
1B3
1A3
1B4
1A4
1B5
1A5
2B1
2A1
2B2
2A2
2B3
2A3
2B4
2A4
2B5
2A5
BEA#
BEB# GND

3

C55

C54

C57

C56

C48

C53

22PF

10PF

22PF

10PF

10PF 10PF

D4
U8_VCC

24
2
5
6
9
10
15
16
19
20
23

5VDDCDA
5VDDCCL
5VHSYNC
5VVSYNC

R326

1
3
5
7

22
R327

22

VCC3SBY VCC1_8

5VFTSDA
5VFTSCL

VCC5

2
4
6
8

1N4148
R95

BC86

4.7K

0.1UF

RN41 2.2K/8P4R

C134 C135
100PF 100PF

R97

R96

4.7K

4.7K

R328
R329

12

2.2K
2.2K

VCC1_8
2

R350
1k
FTVREF
VCC5

FTVSYNC
FTHSYNC
SL_STALL

C141

C142

C143

C144

1.0uF

2.2uF

1.0uF

1.0uF

2.2uF

1

FTD[0..11]

FTD[0..11]

D4 G8

G7
D5

STB G6

ST# G5

D6

D7 G4

D8

G3

R351
1k

C136

C137

0.01uF

100pF

58
60
HS

VS

54
56
I/C

50
52
SCL

46
48
SCL5

SDA

42
44
PD#

RST#

SDA5

38
40
VREF

34
36
VDD3

VDD4

30
32
VDD1

VDD2

26
28
3V4

3V3

18
20

22
24
3V2

3V1

5V2

14
16
SP2

SP3

5V1

10
12
SP1

6
8

SP0
G2
D9

D10 G1

8
8
8

Place 100pF cap
near DVO pin 40

J3
DVO CONNECTOR

41 D3
43
G9
45 D2 G9
47
G10
49 D1 G10
51
G11
53 D0 G11
55
G12
G12
57 D/B
59

C140

1.0uF

21
23
G5
25
27
G6
29
31
G7
33
35
G8
37
39

C139

1.0uF

1
3
G1
5
7
G2
9
11
G3
13
15
G4
17
19

C138

8

CVBS

Y

VCC1_8
D11

VCC3_3

C

2
4

7,17,21,30 PCIRST#

VCC5

6
1
11
7
2
12
8
3
13
9
4
14
10
5
15
VGA_CONN

U8
QST3384
8
8
8
8

1K

BEAD

X10PF

VFB2
8

FB11

U28
1

PR12

R84

2

8

FTD11
FTD10
FTD9
FTD8
FTD7
FTD6
FTD5
FTD4
FTD3
FTD2
FTD1
FTD0

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: VGA Header and DVO Debug Header
FTCLK0
FTCLK1
FTBLNK#

8
8
8

Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
16

A

B

C

D

E

of 33

1

8

7

6

5

4

3

VCC3_3

VCC3_3

13

PDD[0..15]

13

PDA[0..2]

30
BC173
R207

BC175

BC177

BC178

0.1UF

0.1UF

0.1UF

IDERST#

PDD[0..15]
PDA[0..2]
IDERST#

IDE1

R113

33 IDERST_IDE1_PIN1 1
PDD7
3
PDD6
5
PDD5
7
PDD4
9
PDD3
11
PDD2
13
PDD1
15
PDD0
17
19
21
23
25
27
29
31
PDA1
33
PDA0
35
37
39

VCC3_3

0.1UF
0

R79
4.7K
U23
7,16,21,30 PCIRST#

12

R206

8.2K

GPIO23

13,21
13,21
13,21

LAD0
LAD1
LAD2

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

VPP
RST#
FGPI3
FGPI2
FGPI1
FGPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0
FWH1
FWH2
GND

1

IDE

FWH
D

2

VCC
CLK
FGPI4
IC
GNDA
VCCA
GND
VCC
INIT#
FWH4
RFU
RFU
RFU
RFU
RFU
FWH3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FPGI4

R211

8.2K

PCLK_8

6

INIT#
LFRAME#

4,12
13,21

13
13
13
13
13
12

PDREQ
PDIOW#
PDIOR#
PIORDY
PDDACK#
IRQ14

13
24

PDCS#1
IDEACTP#

VCC3_3

R83

8.2K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

D

P66DET

12

PDCS#3

13

PIN_2X20
PDA2

R80

C51
LAD3

10K

47PF

13,21

C

FWH32

13

SDD[0..15]

13

SDA[0..2]

SDD[0..15]
SDA[0..2]
IDERST#

IDE2

R112

33

VCC3_3

R76
4.7K
13
13
13
13
13
12

B

SDREQ
SDIOW#
SDIOR#
SIORDY
SDDACK#
IRQ15
VCC3_3

13
24

R75

IDERST_IDE2_PIN1
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

SDA1
SDA0

8.2K

SDCS#1
IDEACTS#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

B

S66DET

12

SDCS#3

13

R70

PIN_2X20
SDA2

10K

C44
47PF

Document:

A

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: FWH and UDMA100 IDE
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

1.05
Page No:
17

8

7

6

5

4

3

2

1

of 33

A

8

7

6

5

4

3

2

1

VCC5DUAL
F4
13

FUSE_1.0A

USBOC#0-1

USB1
1
FB8
+ EC18

D

2
BC4
470PF

100UF

1
1
13
13
13
13

1
2
3
4
5
6
7
8

BEAD

2 FB21

2
BEAD

VCC0
DATA0DATA0+
GND0
VCC1
DATA1DATA1+
GND1

D

USB_CON2

USBP0N
USBP0P
USBP1N
USBP1P

2 FB22

1
2 FB23

1

BEAD

BEAD

2
4
6
8

1
3
5
7

2
4
6
8

FB24

BEAD

CP3

2
4
6
8

1
3
5
7

RN72
15K/8P4R

47PF/8P4C

1
3
5
7

V3SB

R266 R267
330K 330K

C

C

24

CNR_OC#

R268

X0

VCC5DUAL

11

AGP_OC#

R269

X0

F7

13

USBOC#2-3

FUSE_1.0A

1

2
USB2

FB25

BEAD
1

+ EC39

C122

100UF

470PF

1
1
1
FB29

USBP2N
USBP2P
USBP3N
USBP3P

2 FB26

BEAD

HEADER5X2

BEAD

BEAD

BEAD
2
4
6
8

B

CP4
47PF/8P4C

1
3
5
7

2
4
6
8

1
3
5
7

RN73
15K/8P4R

24
24

1
2
3
4
5

CNRUSBN
CNRUSBP

11
11

2
4
6
8
10

2
4
6
8

13
13
13
13

FB27

1
3
5
7

B

FB28

2

2

1
3
5
7
9

2

JP4
HEADER5
1
2
3
4
5

AGPUSBN
AGPUSBP

JP4
JP4

Pin 3 near USB2 Pin 5
Pin 4 near USB2 Pin 7

JP5
JP5

Pin 3 near USB2 Pin 6
Pin 4 near USB2 Pin 8

JP5

HEADER5

Document:

A

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: USB
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

1.05
Page No:
18

8

7

6

5

4

3

2

1

of 33

A

8

7

6

5

4

3

VCC5

1

VCC5_AUDIO

1

VCC3_3

2

PFB6

2

BEAD
D

D

40
44
43
NC40
NC44
NC43

AVDD1

26

25

42
AVSS2

AVDD2

DVSS2

AVSS1

CS1
CS0
CHAIN_CLK
EAPD

46
45
48
47

PRI_DWN_RST# 29
AC_SDOUT
13,24,29
AC_SDIN0
13,24,30
AC_SYNC
13,24
AC_BITCLK
13,24

EAPD

C

20

C99

30

32

31

FILT_L

FILT_R

XTL_OUT

R252
CS4299
1K

2

29

AFILT2

MC51

XTL_IN

X10PF

AFILT1

B

11
5
8
10
6

3

MONO_OUT

U15

RESET#
SDATA_OUT
SDATA_IN
SYNC
BIT_CLK

R253
XTAL_OUT

1UF

VREFOUT

MC58

VREFOUT 28

R154_MC58

VREF

100

27

R154

AFILT1

24 AC97SPKR
20 LNLVL_OUT_R
20 LNLVL_OUT_L

VREF

20 AUX_L
20 AUX_R

AC’97
CODEC

CX3D

20 CD_R
20 CD_L
20 CD_REF

PC_BEEP
LINE_IN_R
LINE_IN_L
MIC1
MIC2
CD_R
CD_L
CD_REF
VIDEO_R
VIDEO_L
AUX_L
AUX_R
PHONE
MONO_OUT
LINE_OUT_R
LINE_OUT_L
LNLVL_OUT_R
LNLVL_OUT_L

RX3D

12
24
23
21
22
20
18
19
17
16
14
15
13
37
36
35
41
39

34

PC_BEEP

33

1UF

CX3D

MC56

RX3D

R336_MC56

FILT_R

1K

DVDD2

DVDD1

DVSS1
R336

FILT_L

C

ICH_SPKR
LINE_IN_R
LINE_IN_L
MIC_IN

AFILT2

13,24,29
20
20
20

38

0.1UF

9

BC129

0.1UF

7

BC136

0.1UF

1

BC139

0.1UF

4

BC140

0.1uF NPOP

X0

AUD_VREFOUT 20

B

XTAL_IN
R254

Y1

1K
24.576MHZ

R337
220K

C95

R155
220K

C94

MC53

2700PF 2700PF 1UF

MC54

MC52

MC55

MC46

MC48

C98

C97

1UF

1UF

0.1UF

4.7UF

2.2UF

22PF

22PF

"SINGLE POINT CONNECTION"

Document:

A

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: AC’97 Codec
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

1.05
Page No:
19

8

7

6

5

4

3

2

1

of 33

A

8

7

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4

3

2

1

Stereo HP/Spkr out
R104

+

C77
C87_C77

1

FB13
2

SPKROUT_R
JK1

22

C78

R105

BEAD

+

100UF

1

D

22

100UF
MC47

FB14
2

SPKROUT_L
D

BEAD
PHONEJACK

R132
MC47_R132

19 LNLVL_OUT_L

C75

1UF

C74

100PF

20K
C87

100PF

100PF
C74_JK1

R126

MC45

R127
MC45_R127

19 LNLVL_OUT_R

20K

U11_INA
U11_BYPASS

1UF

20K

U11_OUTA
U11
1 OUTA
2 INA
3 BYPASS
4 GND

VCC5_AUDIO
8
7
6
5

VDD
OUTB
INB
SHUTDN

R128
20K

U11_OUTB
U11_INB

C90
100PF

LM4880
MC40
1UF

BC123

C

C

0.1UF
19 EAPD

Line_In Analog Input
MC44
19

MC44_R122

LINE_IN_R

R122
1K

FB17
2

R122_FB17 1

JK2

1UF
MC42_R121

LINE_IN_L

R121
1K

FB16
2

R121_FB16 1

CD_INR

1
2
3
4

BEAD

MC42
19

CD Analog Input
CD2

JK2_LINE_IN_R

CD_ING
CD_INL

JK2_LINE_IN_L
2.54_WAFER_4

1UF
C86

100PF

100PF

CDIN_R

1K
R117

CDIN_L

CDIN_REF
1K

CD1

B

19

CD_L

19

CD_REF

19

1UF
MC38

R116

PHONEJACK

CD_R
1UF
MC39

1K

BEAD
C80

MC43

R115

1UF
B

R125
220K

1
2
3
4

C81

R118
220K

100PF

C79

R124
220K

C82

100PF

100PF

2mm_WAFER_4

Microphone Input

R119
R119_FB15

19 AUD_VREFOUT

JK3

2.2K
MC41
19

R120_MC41

MIC_IN

R120

1

1K

1UF

FB15
2 JK3_MICIN

C85
0.01UF

MC36
AUX_INL
1UF

AUX_L

19

AUX_R

19

MC37

AUX_INR

2.54_WAFER_4

BEAD
C76

AUX1
1
2
3
4

1UF

PHONEJACK

100PF

Document:

A

"SINGLE POINT CONNECTION"

C83

C84

100PF

100PF

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Audio I/O
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

1.05
Page No:
20

8

7

6

5

4

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8

7

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6

5

4

3

2

IRRX
IRTX
RI#1
DCD#1
TXD1
RXD1
DTR#1
RTS#1
DSR#1
CTS#1

VTT_SENSE

9,10,13,24,30,32 SMBDATA

R185
300
R193
300

9,10,13,24,30,32 SMBCLK
25
25
25
25

-5VIN
-12VIN
+12VIN
+3.3VIN

25
25
25

VCORE
HM_VREF
VTIN3

D

VCC5

1
1

FB19
2

FB20
2

IOAVCC

4,25

R166
0

R157
10K

VCC5SBY

R167
10K

V3SB

BEAD
BC172
0.1UF

BEAD
THRMDN
VCCRTC

0.1UF

4,25 VTIN2
25
VTIN1
13,30 OVT#

C

27,29,32
27,29,32
27,29,32
27,29,32
25
25
25

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

VID3
VID2
VID1
VID0
FANIO3
FANIO2
FANIO1
FANPWM2
FANPWM1

24
23
23
23
23
23
23
23
23
23
23

BEEP
MIDI_IN
MIDI_OUT
J1BUTTON2
J2BUTTON2
JOY1Y
JOY2Y
JOY2X
JOY1X
J2BUTTON1
J1BUTTON1

W83627HF

23
23
22
22
22
22
22
22
22
22

CASEOPEN#

13,25

SUSCLK

13

SLP_S3#

6,13,28

PS_ON

25

PWROK

13,25

RSMRST#

13

PANSWIN

24,32

PWRBTN#

13,33

MDAT
MCLK

23
23

SUSLED
KDAT
KCLK

24
23
23

KBRST#
A20GATE
KEYLOCK#
RI#0
DCD#0

12,30
12,30
24
22
22

TXD0
RXD0
DTR#0
RTS#0
DSR#0
CTS#0

22
22
22
22
22
22

STB#
AFD#
ERR#
PAR_INIT#
SLIN#

22
22
22
22
22

D

U17

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

SUSLED/GP35
KDAT
KCLK
VSB
KBRST
GA20M
KBLOCK#
RIA#
DCDA#
VSS
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3

C

VCC5SBY

VCC5

BC151
0.1UF

DRVDEN0
DRVDEN1
INDEX#
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE#
VCC
TRAK0#
WP#
RDATA#
HEAD#
DSKCHG#
CLKIN
PME#
VSS
PCICLK
LDRQ#
SERIRQ
LAD3
LAD2
LAD1
LAD0
VCC3V
LFRAME#
LRESET#
SLCT
PE
BUSY
ACK#
PD7
PD6
PD5
PD4

25
25

VTIN2
VTIN1
OVT#
VID4
VID3
VID2
VID1
VID0
FANIO3
FANIO2
FANIO1
VCC
FANPWM2
FANPWM1
VSS
BEEP
MSI/GP20
MSO/IRQIN0
GPSA2/GP17
GPSB2/GP16
GPY1/GP15
GPY2/P16/GP14
GPX2/P15/GP13
GPX1/P14/GP12
GPSB1/P13/GP11
GPSA1/P12/GP10

VTIN3
VREF
VCOREA
VCOREB
+3.3VIN
AVCC
+12VIN
-12VIN
-5VIN
AGND
SCL/GP21
SDA/GP22
PLED/GP23
WDTO/GP24
IRRX/GP25
IRTX/GP26
VSS
RIB#
DCDB#
SOUTB
SINB
DTRB#
RTSB#
DSRB#
CTSB#
VCC
CASEOPEN#
SUSCLKIN
VBAT
SUSCIN/GP30
PWRCTL#/GP31
PWROK/GP32
RSMRST#/GP33
CIRRX/GP34
PSIN#
PSOUT#
MDAT
MCLK

BC161

0.1UF

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

VCC5
BC154

1

B

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

FDC1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

FDD Signals Trace 8 or 10 mil

B

W83627HF

RWC#
DS1#
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE#

PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
ACK#
BUSY
PE
SLCT

22
22
22
22
22
22
22
22
22
22
22
22

PCIRST#

7,16,17,30

VCC5
VCC3_3
BC162
.1U

HEAD#

BC155
.1U

HEADER_17X2
6
SIO_CLK24
12,30 LPC_PME#
6
PCLK_7

A

A

13
LDRQ#0
12,30 SERIRQ
13,17
13,17
13,17
13,17
13,17

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Super I/O and FDC

LAD3
LAD2
LAD1
LAD0
LFRAME#

Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Revision:

Platform Applications Engineering

1.05

1900 Prairie City Road
Folsom, CA 95630

Page No:
21

8

7

6

5

4

3

2

1

of 33

A

B

C

D

VCC12-

WAKE ON LAN

VCC12

E

VCC5

COM1

VCC5SBY

COM1

D7

Q21

3
2
1

R230
100

2N3904

HEADER_3*1(2MM)
R229
4.7K

21
21
21
21
21
21
21
21

DCD#0
DTR#0
CTS#0
TXD0
RTS#0
RXD0
DSR#0
RI#0

10
11

-12V
GND

12V
5V

1
20

12
13
14
15
16
17
18
19

RY5
DA3
RY4
DA2
DA1
RY3
RY2
RY1

RA5
DY3
RA4
DY2
DY1
RA3
RA2
RA1

9
8
7
6
5
4
3
2

DCD0
DTR0
CTS0
TXDD0
RTS0
RXDD0
DSR0
RI0

1
6
2
7
3
8
4
9
5

CN3

2
4
6
8

WOL1

11,12,14,15 PCI_PME#

DCD0
DSR0
RXDD0
RTS0
TXDD0
BC99 CTS0
.1U
DTR0
RI0

2
4
6
8

4

SS12/SMD

2
4
6
8

U9
SS12/SMD

2
4
6
8

D6

4

CONNECTOR_DB9
CN2

1
3
5
7

100PF/8P4C

1
3
5
7

1
3
5
7

100PF/8P4C

1
3
5
7

GD75232

WAKE ON MODEM
ICH_RI#

COM2

U10

R109
RI1

Q15
2N3904
10K

R110
2.2K

DCD#1
DTR#1
CTS#1
TXD1
RTS#1
RXD1
DSR#1
RI#1

12
13
14
15
16
17
18
19

RY5
DA3
RY4
DA2
DA1
RY3
RY2
RY1

RA5
DY3
RA4
DY2
DY1
RA3
RA2
RA1

9
8
7
6
5
4
3
2

CTS1
DSR1
DTR1
BC54 RXDD1
.1U
DCD1
TXDD1

DCD1
DTR1
CTS1
TXDD1
RTS1
RXDD1
DSR1
RI1

1
3
5
7
9

RTS1
RI1

21

ERR#

Parallel Port

100PF/8P4C
VCC5

D2

1
3
5
7

AFD#

2
4
6
8
10

HEADER_5X2

GD75232
CN11

21

3

COM2

2
4
6
8

21
21
21
21
21
21
21
21

1
20

2
4
6
8

R108
2.2K

12V
5V

1
3
5
7

10K

3

-12V
GND

CN9
100PF/8P4C

1
3
5
7

Q14
2N3904

2
4
6
8

RI0

10
11

2
4
6
8

R107

1
3
5
7

13,30

U5
SS12/SMD

2

1

21

PAR_INIT#

1

21

SLIN#

2

21

STB#

3

21

PDR0

21

PDR1

21

P8

28

P2

P7

27

SI1

SO1

26

4

SI2

SO2

25

5

SI3

SO3

24

PDR2

6

SI4

SO4

23

21

PDR3

7

SI5

GND

22

21

SLCT

8

P3

SO5

21

21

PDR4

9

SI6

VCC

20

21

PE

10

P4

SO6

19

21

PDR5

11

SI7

SO7

18

21

BUSY

12

P5

SO8

17

21

PDR6

13

SI8

SO9

16

21

PDR7

14

SI9

P6

15

P1

BC49
.1U

2

LPT1
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

Document:
Last Revised:

PAC-S1284
21

ACK#

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Serial, Parallel, WOL, and WOR
Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

LPT

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
22

A

B

C

D

E

of 33

1

A

B

C

VCC5 VCC5

VCC5

VCC5

VCC5

VCC5

D

E

VCC5
R103

XFUSE_1.0A

2

F6

0

FB12
R99

4.7K

4.7K

R94
4.7K

4

R93
4.7K

R102
4.7K

BEAD

R101
4.7K

C70

4

1

R92

470PF
J1

RN39
8
6
4
2
47

R91
C60
1000PF

C66
22PF

C64
1000PF

C68
22PF

C63
22PF

C67
1000PF

C65
22PF

C71
1000PF

MIDI_OUTPUT

47
1K/8P4R
7
5
3
1

JOY_2Y
JOY_1Y
J2BUT2
J1BUT2
MIDI_INPUT

C59

CN8

470PF

470PF
470PF/8P4C

VCC5DUAL

GAME_PORT
C73
CN10

3

7
5
3
1

470PF

7
5
3
1

3

C62

8
6
4
2

R98

1
9
2
10
3
11
4
12
5
13
6
14
7
15
8

8
6
4
2

JOY2Y
JOY1Y
J2BUTTON2
J1BUTTON2
MIDI_IN

R17

7
5
3
1

MIDI_OUT

21
21
21
21
21

470PF/8P4C

7
5
3
1

21

J1BUT1
J2BUT1
JOY_1X
JOY_2X

8
6
4
2

J1BUTTON1
J2BUTTON1
JOY1X
JOY2X

1K/8P4R
7
5
3
1

8
6
4
2

21
21
21
21

RN40
8
6
4
2

Game Port

0
FB1

F1
R18

XFUSE_1.0A

1

F2

2
BEAD

0
XFUSE_1.0A

FB3
21

KDAT

2

1

BEAD
FB5
2

2

21

KCLK

U1

1

CN1_U1

BEAD
RN4
8
6
4
2

21

4.7K/8P4R
7
5
3
1

MDAT

21

MCLK

2

1

BEAD
FB4
2

1

BEAD
FB6
2

2

13
14
15

FB2
1

1
2
3
4
5
6

16
17
7
8
9
10
11
12

BEAD

KB/MOUSE
IR1
VCC5

1

21

IRRX

21

IRTX

CN1

1
2
3
4
5

8
6
4
2

8
6
4
2

7
5
3
1

470PF8P4C
HEADER_1X5

7
5
3
1

C1

C2

2.2UF

2.2UF

Keyboard
Mouse

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: PS/2, Game, and IR
Last Revised:

IR

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
23

A

B

C

D

E

of 33

1

8

7

Power
Switch

6

V3SB

5

VCC5SBY

4

VCC5

3

VCC3_3 VCC12-VCC5SBY

1

1

2

2

3

3

4

4

R233
10K

R242 R244
220
10K

R243
150

R246
2.2K

R238
220

SW_4
12
LAN_TXD1
12 LAN_RSTSYNC

PN1
R238_PN1

21

KEYLOCK#
EXTSMI#
R243_PN1
D15_PN1
R242_PN1

21,32

PANSWIN
R241
10K

BC185
R240
0

0.1UF

R240_PN1

C119

1
2
3
4
5
6
7
8
9
10
11
12
13
14

17

17

12
12

LAN_RXD2
LAN_RXD0

18

CNR_OC#

KEYLOCK

HDD LED

VCC12V3SB VCC5

13
13

SMI_SW

EE_DIN
EE_SHCLK

HEADER_14
9,10,13,21,30,32 SMBCLK
12,29 PRI_DWN#
D15

1N4148

D14

1N4148

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19

RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
LAN_TXD1
LAN_RSTSYNC
GND
LAN_RXD2
LAN_RXD0
GND
RESERVED
+5VDUAL
USB_OC#
GND
-12V
+3.3VD

RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
LAN_TXD2
LAN_TXD0
GND
LAN_CLK
LAN_RXD1
RESERVED
USB+
GND
USB+12V
GND
+3.3VDUAL
+5VD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

GND
EE_DOUT
EE_SHCLK
GND
SMB_A0
SMB_SCL
PRIMARY_DN#
GND
AC97_SYNC
AC97_SD_OUT
AC97_BITCLK

GND
EE_DIN
EE_CS
SMB_A1
SMB_A2
SMB_SDA
AC97_RESET#
RESERVED
AC97_SD_IN1
AC97_SD_IN0
GND

A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30

LAN_TXD2
LAN_TXD0

12
12

LAN_CLK
LAN_RXD1

12
12

CNRUSBP

18

CNRUSBN

18

D

R272 C125 R273 C126
15K
15K
47PF
47PF

PWR_SW

0.1UF

C

1

CNRSLOT1

SW2

D

12

2

13,19 AC_SYNC
13,19,29 AC_SDOUT
13,19 AC_BITCLK

IDEACTP#

13
13

SMBDATA
AC_RST#

9,10,13,21,30,32
13,29

AC_SDIN1
AC_SDIN0

13,30
13,19,30

C

CNR

R247
20K

IDEACTS#

EE_DOUT
EE_CS

SW3
VCC5

1

1

2

2

3

3

4

4

VCC5SBY
R255
10K

VCC5
VCC5

VCC5

SW_4
SMBCLK
Reset
Switch

R235
10K

R234
150

SMBDATA
PN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14

25,32 HWRST#

B

R237_PN2

21

SUSLED

Q22
2N3904

R237
0
R237_2

VCC5

R223
10K
21

BEEP
R256

Q19
2N3904

0

R232

68

R231

68

RESET

SMB2

SMB1

1
2
3
4
5

SPEAKER

1
2
3
4
5
SMBCON

B

SMBCON

GREEN LED
D16
RESERVE

VCC5SBY

R239

330
LED

HEADER_14
VCC5
SP1
R236
33

BUZZER

JP2
13,19,29 ICH_SPKR
A

1
3

2
4

R226

2.2K

Q20
2N3904

Document:

BC184
0.1UF

XHEADER 2X2

Last Revised:
19

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Front Panel Headers and CNR
Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

AC97SPKR

JP2
PC_BEEP SELECTION
1-2 ON TRADITIONAL
3-4 ON CONTROLLED by AC97 CODEC

Revision:

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

1.05
Page No:
24

8

7

6

5

4

3

2

1

of 33

A

A

B

C

VCC3_3

D

VCC5SBY

E

VCC5

V3SB

ATXPR1

PS_ON

VCC_54

VCC5

1
2
3
4
5
6
7
8
9
10

3.3V
3.3V
GND
+5V
GND
+5V
GND
PWROK
AUX5V
+12V

BC164
.1U

D10
1N4148

R190
15K

VCC5SBY
14

21

3.3V
-12V
GND
PS_ON
GND
GND
GND
-5V
+5V
+5V

U20C
ATXPWROK

5

VCC5SBY
VCC12

6

4.7K

1

2

4

R192
33K

C115

74LVC14A
74LVC06A

ATX_PWCON

R189

U19A

2.2UF

7

11
12
13
14
15
16
17
18
19
20

VCC12-

VCC5SBY
U20F
R245

24,32 HWRST#

100

13

U19F
12

13

VCC5SBY

12
U20D

74LVC14A
V3SB

V3SB

U19E

74LVC06A
9

8

11

10

PWROK

13,21

74LVC14A
R323
1K

BC165
.1U

V3SB

VCC5SBY

U20A
14
1
7

4 DBRESET#

74LVC06A

U19B
2

3

4

74LVC14A

3

74LVC06A

1
2
21

VTIN1

4,21

VTIN2

PR38
VCC12

VCC5

10K,1%

R218
4.7K
R217

CHASSIS FAN

Q18
2N2907
+12CHFAN

1K

D13
1N4148

Q17
2N7002
21

FANPWM1

R216

EC38

+

22UF

510

1K

C118
FANIO1

21
4,21

VCC12

PR37
28K,1%

D1

R19

1N4148
Q1
2N7002
21

FANPWM2

R16

510

EC3

+

22UF

FANIO2

Voltage Sensing

10K
PR34

D5

+

1N4148

56K,1%

2

+12VIN

21

VCORE

21

VTT_SENSE

21

+3.3VIN

21

VCC12-

232K,1%

VCC5

22UF

HEADER_2PIN

10K
R214

PR33

EC35

S1

VCC3_3

56K,1%

PWR FAN

13,21 CASEOPEN#

10K
R208

21

10M

If case is opened,
this switch should be closed.

VTT

PR35

VCC12
R213

R209

1K

FAN1
3
2
1
HEADER_3

VCCRTC

PR36
10K,1%

VCCVID

CPU FAN

Q2
2N2907
+12CPUFAN

1K

10K_1%-THRM/0603

VCC5

R11

R10

RT1

THRMDN

2

4.7K

PR39
10K,1%

3300PF

HEADER_3

1

30K

"power use"

FAN3
3
2
1

VCC12

X10K_1%-THRM/0603

"system use"
R210

R212

RT2

t

VTIN3
HM_VREF

HEADER_2

t

21
21

3

JP3

Temperature Sensing

PR32

-12VIN

21

-5VIN

21

VCC_5-

120K,1%

R100

Document:

1K

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: ATX Power and HW Monitor

FAN2
3
2
1

FANIO3

21

Last Revised:

HEADER_3

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
25

A

B

C

D

E

of 33

1

A

B

C

D

Q39
PHD55N03LT

U31_FORCE1

R354
3.3k

C155

C156

C157

C158

C159

0.1uF

100uF

100uF

4.7uF

4.7uF

R357
3

4

VDDQ

1

2

2

VCC5

VCC3_3

1

VCC5SBY VCC12

D23

4

0
U31_SENSE1

BAT54C

3

R356
3.3k

R355_C147
C147

R358

R401

TYPEDET#

C148
R355
0
U31_SHDN1#

R359
10k

220
Q48_B

1.0uF

0.1uF

VCC3_3

R400

220

VCC3_3

1M - NPOP
11

E

8
5
3
4

U31_SHDN2#

Q49_B

U31
VCC
SHDN1#
SHDN2#
GND

FORCE 1
SENSE 1
FORCE 2
SENSE 2

7
6
1
2

Q48
PNP

Q49
NPN

R402
VCC3_3

470
Empty for ADM1051AJR

ADM1051A
3

3

Q40
MTD3055VLT4

U31_FORCE2
U31_SENSE2
VCC5

C151

C152

C153

C149

100uF

100uF

4.7uF

4.7uF

0.1uF

R360

3

100 1%

Target is
really 1.85V

R378
2.2k

VTT
VCC3_3

VCC5

VR1
3

VOUT
VIN

2

ADJ

1

C160
R364

C174 LT1587-ADJ
10 uF

VR1_FB
C162

22uF Tantalum

2
4

1

R380
20k

VCC
IN+ 1

C173
0.1 uF

6

LM393 Ch1

2.0ms delay
nominal

R366
732 1%
Q41
FDN335N

Document:

U32-2

R367

4,6,7 TUAL5
10 1%

R381
1k

IN+ 2
OUT 2
IN- 2

VTTPWRGD

VTTPWRGD5# 27

Intel(R) 815E Chipset Universal Socket 370 CRB

Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

1

Revision:

Platform Applications Engineering

1.05

1900 Prairie City Road
Folsom, CA 95630

Page No:
26

A

B

4

Q44
2N7002

7

LM393 Ch2

2

Page Name: VRegs: Vddq, Vcc1_8, and Vtt

R368
1k 1%

1

U32B

IN- 1
GND

V1_8SB

49.9 1%
0.1uF

V1_8SB
5

OUT 1

R379
1k

ASSERTED LOW!

D24_U32

1

VTT

VCC5

U32A
8
3

VTTPWRGD12 6

VCC5

1

2

2

Q43
2N7002

2

VCC1_8

VCC12

R361
5620 1%

3

D24
BAT54C

C150

C

D

E

of 33

A

B

VCC5

L7

C

D

E

1.7uH
Q45_L7

C175
10uF
4

C176
0.1uF

C177
3300uF

C178
3300uF

C179
0.1uF

C180
4.7uF

C181
4.7uF
U34_R384

VCC12

4

C182 0.001uF
U34
R382

10 (805)
C183
0.1uF

29,32 VID[0:4]
26 VTTPWRGD5#
VCC5

R382_U34

16
1
C184
2
4.7uF
3
4
5
8
7
U34_R391
13
U34_C18812
C188
20
VID3
VID2
VID1
VID0
VID4

VCC
CS+
VID3
CSVID2
PGND
VID1
DRVH
VID0
DRVL
VID25
FB
SD
PWRGD
REF
COMP LRDRV
CT
LRFB
GND
ADP3170

U34_C182
11
10
19
18
17
9
6
14
15

Q45
SUD50N03-07
U34-18 R385
4.7 (805)
2.2 (805)
U34-17 R386
VCCVID_FB

R383
220
L8

VCCVID

1.2uH

Q45_L8
R389 2 mOhm (2512)

VRM_PWRGD 13

R388

C185
820uF

Q46_R386
U34_1415

C186
820uF

C187
1000uF

2.2 (805)
Q46
SUD50N03-07

C189
4700pF

100pF

R390

R384
220

C190
820uF

C191
820uF

C192
1000uF

R391 0
3

25.5k 1%

3

R393

R392 0

C193
0.001uF

C194
0.1uF

154k 1%

V3SB
New V1_SB Circuitry

R404

V1_8SB

This takes the place of
the old V1_8SB circuit.

32.4 1%

2

2

C197
R405
38.3 1%

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: VRegs: VCCVID, V1_8SB
Last Revised:

1

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

1

Revision:

Platform Applications Engineering

1.05

1900 Prairie City Road
Folsom, CA 95630

Page No:
27

A

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C

D

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A

B

C

VCC5SBY

VCC12

D

VCC3_3

E

VCC5

VCC2_5

4

EC11
+

100UF

0.1UF

3

EC19
+

10UF

VIN

VOUT

100UF

4

U2_Q4

3

NZT651/SOT223
V3SB

4
9

U2_R20
C18

10UF

1UF

DRV2

15

VSEN2

16

100,1%
Q3_Feedback

100UF

HUF76121D3S/TO252
PR2

3V3DL
FAULT/MSET

VCC3SBY
EC14
+

C5

100,1%

VCC5SBY

1500UF

1UF

R20
10K

EC10
+

6,13,21 SLP_S3#
13
SLP_S5#
VCC5SBY
U2_C4

3

+ EC5

Q7
U2_Q7

3V3DLSB

6
7
5
2
13

S3
S5
EN5VDL
EN3VDL
SS

5VDLSB

11

5VDL

12

DLA

10

GND

EC20
+

PR3

10UF

U2

12V

5VSB

1

14

+ EC6

Q4

2

LM1117ADJ
1

EC17
+

C7

ADJ

Q3

U2_Q5

100UF
Q5
NDS356AP/SOT23
VCC5DUAL
3

C8

RT9641
1UF

8

C4
0.1UF

U2_Q8

Q8

VCC3_3

4

G2

D2

5

3

S2

D2

6

2

G1

D1

7

1

S1

D1

8

Do not stuff this box.
VCC5

VCC1_8

Stuff this box
VCC3_3

EC22
+

EC15
+

100UF

100UF

VCMOS

FDS8936 / SI9936

Q42
3

VIN

ADJ

2

VOUT

Debug note:
Stuff only one box.

R369
1.13 1%
1206 pack

2

2

LT1117ADJ
+ EC43

1

+ EC42

PR44
10UF

10UF
49.9 1%

R370
9.31 1%
1210 pack

Q42_Feedback
PR45
10 1%

Document:

1

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: VRegs: Duals, 3.3SB, 2.5, VCMOS
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
28

A

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C

D

E

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1

A

B

C

D

E

2
4
6
8

V3SB

1
3
5
7

RN59
2.2K/8P4R

4

VCC3_3

SW1
1
2
3
4
5
6
7
8

4

DIPSW-8
16
15
14
13
12
11
10
9

SW1_R262
SW1_R263

R262
R263

8.2K
8.2K

AC_SDOUT
ICH_SPKR

13,19,24
13,19,24

D17
13,24 AC_RST#
1N4148
VCC5SBY
3

3

U19C
12,24 PRI_DWN#

5

6

R153

PRI_DWN_RST# 19

74LVC06A

10K

VCC3_3

SW 7
OFF
ON

ON BOARD AC97 CODEC
PRIMARY CODEC
DISABLE

SW 5
ON
OFF

AC_SDOUT
USE CPU FREQ STRAP IN ICH REGISTER
FORCE CPU FREQ STRAP TO SAFE MODE(1111)

SW 6
ON
OFF

STRAP(SPKR)
NO REBOOT ON 2ND WATCHDOG TIMEOUT
REBOOT ON 2ND WATCHDOG TIMEOUT

V3SB

J5
3,32 JPR_VID0

2

3,32 JPR_VID1

2

2

5

5

8

8

3,32 JPR_VID3

11

11

3,32 JPR_VID4

14

14

4,32 BSEL#1

17

17

20

20

3,32 JPR_VID2

4,32 BSEL#0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

1
3
4
6
7
9
10
12
13
15
16
18
19
21

1
3
4
6
7
9
10
12
13
15
16
18
19
21

2

2
4
6
8

2
4
6
8

7x3 JPR HDR

1
3
5
7

1

RP6
1K/8P4R

Document:

1
3
5
7

RP5
1K/8P4R

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: System Config DIP Switches
21,27,32
21,27,32
21,27,32
21,27,32
27,32
7
7

VID0
VID1
VID2
VID3
VID4
R_REFCLK
R_BSEL#0

Last Revised:
R394 8.2k
FMOD1
FMOD0

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

6
6

R395 8.2k

Revision:
1.05
Page No:
29

A

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C

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E

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1

C

ICH2

VCC5

R1
R2
R3
R4
R5
R6
R7
R8

1
3
5
7

2.7K/10P8R
RN58
2
4
6
8

1
3
5
7

2.7K/8P4R
RN64
2
4
6
8

1
3
5
7

2.7K/8P4R
RN66
2
4
6
8

4

12,15 PREQ#2
12,14 PREQ#1
12,14 PREQ#0

12
12
12

14,15
14
14
15

PREQ#3
PREQ#5
PREQ#4

ACK64#
REQ64#1
REQ64#2
REQ64#3

C

5

C

10

13
13,22
9,10,13,21,24,32
9,10,13,21,24,32

SMBALERT#
ICH_RI#
SMBCLK
SMBDATA

12,21 LPC_PME#
13,15 SMLINK0
13,15 SMLINK1

12
13
12

12
13,21
12,21
12,21

GPI8
GPIO25
GPIO27

PCI_REQ#A
OVT#
KBRST#
A20GATE

1
3
5
7

RN55
2
4
6
8
8.2K/8P4R
RN60
2
4
6
8

V3SB

1
3
5
7

4.7K/8P4R
RN54
2
4
6
8

V3SB

1
3
5
7

VCC3_3

1
3
5
7

8.2K/8P4R
RN51
2
4
6
8

BC163
.1U

R276

8.2K

R147

10K

13,24 AC_SDIN1

R152

10K

VCC3_3
VCC3_3

VCC3_3

RN74
2
4
6
8

1
3
5
7

RN75
2
4
6
8

1
3
5
7

0/8P4R
RN76
2
4
6
8

1
3
5
7

8.2K/8P4R
RN77
2
4
6
8

R188
1K

14
ICHRST#

U18D
8

9

R188_U18

12
12
12
12

ICH_IRQ#E
ICH_IRQ#F
ICH_IRQ#G
ICH_IRQ#H

7,16,17,21

R198
1K
3

U18C
6

5

7

7

74LVC07A

VCC3_3

8.2K/8P4R
VCC5SBY

U18E
10

11

74LVC07A

U19D
9

U20B
3

4

74LVC14A
U20E
11

7

2

ICH_IRQ#A
ICH_IRQ#B
ICH_IRQ#C
ICH_IRQ#D

PCIRST#

VCC3_3

14

X0/8P4R
12
12
12
12

11,14,15

VCC3_3

VCC3_3

74LVC07A

1
3
5
7

PCI_RST#

74LVC07A

VCC3_3
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D

R197
1K
U18B
4

3

12

11,14,15
11,14,15
14,15
14,15

17
4

2.7K/8P4R
3

IDERST#

74LVC07A

VCC3_3
12,21 SERIRQ

R196
1K
U18A
2

1

8.2K/8P4R

13,19,24 AC_SDIN0

VCC5

7

1
2
3
4
6
7
8
9

VCC3_3

14

PERR#
SERR#
PLOCK#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#

E

VCC3_3

7

RP2
12,14,15
12,14,15
12,14,15
12,14,15
12,14,15
12,14,15
12,14,15
12,14,15

D

V3SB

14

B

PCI

14

A

2

10

74LVC14A

8
VCC3_3

14

74LVC06A

U18F
12

13

7

74LVC07A

Document:

1

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Pullup/Pulldown Rs and Unused Gates
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
30

A

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C

D

E

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1

A

B

C

" ATX POWER "

VCC12
VCC3_3 " ATX POWER "

" ATX POWER "

VCC5

BC85

BC83

EC27

BC41

BC53

EC28

BC69

0.1UF

0.1UF

0.1UF

22UF

VCC12- " ATX POWER "

0.1UF

0.1UF

22UF

BC168

BC180

BC143

BC157

EC36

BC142

BC156

BC167

BC179

0.1UF

0.1UF

0.1UF

0.1UF

22UF

0.1UF

0.1UF

0.1UF

0.1UF

BC70
22UF

22UF

E

VCC_5- " ATX POWER "
EC26

EC33

D

0.1UF

4

4

VCCVID

MC3

MC4

4.7UF/X7R

MC2

4.7UF/X7R

MC1

4.7UF/X7R

MC5

4.7UF/X7R

MC6

4.7UF/X7R

MC8

4.7UF/X7R

MC9

4.7UF/X7R

VCC3SBY " DIMM0 : Near Power Pins "

MC31
4.7UF

3

VCC1_8

MC26
4.7UF

MC30
4.7UF

MC11
4.7UF

MC16
4.7UF

4.7UF/X7R

BC66

BC39

BC19

BC8

BC10

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

MC13

MC14

MC15

MC49

MC50

MC64

MC65

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

" Display Cache : Near the Power Pins "

VDDQ

BC76

MC10
4.7UF/X7R

MC35

MC34

4.7UF

4.7UF

MC33
4.7UF

MC32
4.7UF

BC101

BC102

BC103

BC104

BC112

BC111

BC110

BC108

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

3

" GMCH : 0.1U//0.01U at each conner and each side-center "

MC24
4.7UF

BC78

BC71

BC50

BC42

BC43

BC44

BC45

BC81

BC75

BC114

BC105

BC95

BC96

BC79

BC46

BC47

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

VCC3SBY " GMCH : Near System Mem Quadrant "

" GMCH : Near Display Cache Quadrant "
" Within 70 mils of GMCH "

VDDQ

VCC3SBY " DIMM1 : Near Power Pins "

BC87

BC82

BC80

BC74

BC88

BC65

BC48

BC51

BC52

BC94

BC91

BC97

BC92

BC93

BC98

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

VCC3_3

" ICH : 0.1U//0.01U at each conner "

V3SB " ICH : Near Power Pins "

MC12
4.7UF

MC17
4.7UF

MC27
4.7UF

MC25
4.7UF

VCC1_8 " ICH : Near Power Pins "

BC11

BC20

BC40

BC67

BC77

BC84

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

V1_8SB

" ICH : Near Power Pins "

2

2

BC131

BC132

BC138

BC121

BC150

BC149

BC147

BC124

0.1UF

0.1UF

0.1UF

0.1UF

0.01UF

0.01UF

0.01UF

0.01UF

VCC3_3

1

MC57
2.2UF

MC59
2.2UF

BC204

BC205

BC206

BC207

BC115

BC113

BC116

BC208

BC209

BC210

BC211

BC212

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

" misc. "

VCC3SBY " DIMM2 : Near Power Pins "

BC100

BC107

BC106

BC109

BC122

BC128

BC145

BC146

BC144

BC158

BC159

BC160

BC169

BC170

BC171

BC183

BC182

BC181

BC187

BC186

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

H1
1
2
3
4

HOLE A
8
7
6
5

H3
1
2
3
4

HOLE A
8
7
6
5

H4
1
2
3
4

HOLE A
8
7
6
5

H5
1
2
3
4

HOLE A

H6
1
2
3
4

8
7
6
5

HOLE A
8
7
6
5

H7
1
2
3
4

HOLE A
8
7
6
5

H8
1
2
3
4

HOLE A
8
7
6
5

H9
1
2
3
4

MC60
4.7UF

MC61
4.7UF

MC62
4.7UF

MC63
4.7UF

BC213

BC214

BC215

BC216

BC217

BC218

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

HOLE A

Document:

8
7
6
5

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Decoupling Caps
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
31

A

B

C

D

E

of 33

1

A

B

C

21,27,29 VID[4:0]

4

D

E

J4
VID0
VID2
VID4

3,29 JPR_VID[4:0]

21,24 PANSWIN

JPR_VID1
JPR_VID3

24,25 HWRST#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

VID1
VID3

BSEL#1
BSEL#0

R_SMBDATA
R_SMBCLK
JPR_VID0
JPR_VID2
JPR_VID4

4,29
4,29
R_SMBDATA 6
R_SMBCLK
6
R396

0
SMBDATA
SMBCLK

2x15 HDR

3

R397

VTT

VTT

J6

VCC1_8

J7
3
2
1

HEADER_3

GTLREF

J8
3
2
1

4,7

VCC3SBY

HEADER_3

GTLREFA

4

HUBREF_ICH

12

HEADER_3

J10
3
2
1

3
2
1
HEADER_3

3

0

VDDQ

J9
3
2
1

9,10,13,21,24,30
9,10,13,21,24,30

CONN_AGPREF 8,11

HEADER_3

2

2

Document:

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Internal Debug headers
Last Revised:

1

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

1

Revision:

Platform Applications Engineering

1.05

1900 Prairie City Road
Folsom, CA 95630

Page No:
32

A

B

C

D

E

of 33

A

B

C

D

E

4

4

VCC1_8

VCC1_8

R409
4.7k

V3SB

R410

R411

1K

20k

PWRBTN#
R412

13,21

1K
Q51
2N3904
Q51_Q52

R408
4

Q50
2N3904

THERMTRIP#

R416

0
3

Q52_R416

4,7 CPURST#

Q52
2N3904

3

2.2k

2

2

Stuff either R5 or R415. See p4.

4,12 CPU_PWGD
R413
510

R415 0
N6395404
R414
1.3k

N6395403

4

C198
X0.01uF

Document:

1

No-stuff C198 - debug site only

Intel(R) 815E Chipset Universal Socket 370 CRB

Page Name: Thermtrip
Last Revised:

Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001

Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630

Revision:
1.05
Page No:
33

A

B

C

D

E

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1

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2001:12:04 14:12:29Z
Creator Tool                    : Windows NT 4.0
Modify Date                     : 2013:11:29 19:18:42+02:00
Metadata Date                   : 2013:11:29 19:18:42+02:00
Producer                        : Acrobat Distiller 3.01 for Windows
Format                          : application/pdf
Title                           : Intel 815E - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Intel 815E - Schematics. www.s-manuals.com.
Document ID                     : uuid:ff4f01cf-1e25-42ea-b361-bfd910c5028e
Instance ID                     : uuid:47843505-d2c8-49a5-b818-206c6c60e600
Page Count                      : 34
Keywords                        : Intel, 815E, -, Schematics., www.s-manuals.com.

EXIF Metadata provided by EXIF.tools