Inventec Dakar 10F/FG Schematics. Www.s Manuals.com. 10f, 10fg Rx01 Schematics 1
User Manual: Motherboard Inventec Dakar 10F, FG, R, RG 6050A2491301 - Schematics. Free.
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7 8 6 5 4 3 2 1 THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED. HSF Property:ROHS or Halogen-Free(5L3?) F F E E DAKAR10F/FG D D 2011.09.02 C C B B A A EE DATE POWER DATE INVENTEC DRAWER DESIGN CHECK TITLE RESPONSIBLE Everest Main Board SIZE= 21-OCT-2002 VER: FILE NAME: DATE REV CHANGE NO. 8 7 P/N 6 5 4 3 MODEL,PROJECT,FUNCTION 1310xxxxx-0-0 XXX 2 SIZE C CODE DOC.NUMBER REV X01 CS SHEET 1 1 of 68 8 7 6 4 5 3 2 1 TABLE OF CONTENTS D D PAGE C B PAGE PAGE 1. COVER PAGE 2. INDEX 3. BLOCK DIAGRAM 4. POWER MAP 5. POWER CHARGER 6. POWER +V3LA/+V3A/+5A 7. POWER +V1.5/+V0.75 8. POWER +V1.8S 9. POWER VCCIO 10. POWER VCCSA 11. POWER VCORE 12. POWER VGFX 13. POWER VCORE_DGPU 14. ENABLE PIN 15. LOAD SWITCH-1 16. LOAD SWITCH-2 17. PCB SCREW 18. HALL SENSOR 19. LED 20. K/B & TP/B CONN 21. EC 22. LAN 23. RJ45 & TRANSFORMER 24. AUDIO CODEC 25. SPEAKER/HP JACK/MIC JACK 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. CARDREADER MINI1 WLAN/DEBUG CARD MINI2 3G/LTE SATA HDD/ODD CONN USB 2.0 CONN USB 3.0 CONTROLLER USB 3.0 CONN W/ S&C USB 3.0 CONN LCM CONN CRT CONN HDMI CONN HDMI CEC DDR3 DIMM0 DDR3 DIMM1 FAN & THERMAL SENSOR CPU 1 CPU 2 CPU 3 DRAM CPU 4 POWER CPU 5 POWER CPU 6 GND PCH 1 PCH 2 PCH 3 PCH 4 AXG PCH 5 USB PCH 6 MISC PCH 7 POWER PCH 8 POWER PCH 9 GND VGA 1 VGA 2 VGA 3 VGA 4 VGA 5 VGA 6 VRAM 1 VRAM 2 VRAM 3 VRAM 4 POWER BUTTON BOARD EMI C B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 2 REV X01 68 of 1 8 7 6 AMD 4 5 3 (1333/1600 MHZ) DDR3 INTERFACE DC 35W W/ POWER EXPRESS 1 DDR3@1.5/0.75V IVY BRIDGE PEG 2 204-PIN SODIMM0 SOCKET-RPGA989 THAMES DDR3 INTERFACE 37.5 X 37.5 X 5 mm 29X 29 MM DDR3@1.5/0.75V (1333/1600 MHZ) D D 204-PIN SODIMM1 FDI DMI 2.0 INTERNAL MIC IN AUDIO CODEC REA_ALC269Q_VB6 HDA HDMI C EXT MIC IN C HEADPHONE PCH USB_0: USB CONN USB2.0 CRT PANTHER POINT USB_2: USB CONN USB_8: CARD READER 25 X 25 X 2.3 mm LVDS USB_9: MINICARD WLAN LCM USB_10:WEBCAM SLEEP & CHARGE B B PCIE_1:LAN RJ45 USB_1: USB3.0 CONN USB3.0 PCIE ATHEROS_AR8161/8162 PCIE_2:WLAN PCIE_3:USB3.0 A ENE-P2809A THERMAL SENSOR PCIE USB_8: CARD READER USB2.0 REA_RTS5129 PCIE EC WINDBOND SATA SATA0:ESATA SPI SATA1: HDD SATA6: ODD A SPI FLASH 8MB SPI NPCE885LA0DX MXIC_MX25L3206EM2I BATTERY CHARGER & DC/DC & IMVP 7 KEYBOARD INVENTEC TOUCH PAD LI-ION BATTERY 6-Cell TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 3 REV X01 68 of 1 8 7 6 ADAPTOR 4 5 +VBAT 2 +V5A_+-5% BQ24725RGRR FUSE 3 1 +V5S TPS51123 AO6402L CHARGER 65W-75W 8A 6036A0003401 90W 10A 6036A0002901 120W 12A 6036A0006001 EC_SMB2 POWER BUDGET 12.139 A POWER BUDGET 4.711AINRUSH 0.9A CHG_EN F 300K PEAK2.592A 100.82UF_0.842M£[ BATT_IN OCP 10.4A ACPRES PEAK 7.283A +V0.85S_+-0.5% R=120K AVG 2.363A TSP51461 220UF_25M£[ // 53.92UF_1.529M£[ D D POWER BUDGET 6A F 340K OCP 6A BATTERY PACK PEAK 6A +V3LA_+-5% +VCORE_+-0.5% +V3_LAN +V3A +VCORE1_+-0.5% TPS51123 TI_TPS61640 AO6402L AM2321P POWER BUDGET 9.429 A INRUSH 0.9A POWER BUDGET 4.711A POWER BUDGET 4.711A INRUSH 0.9A 100.82UF_0.842M£[ PEAK2.592A PEAK2.592A F 280K F 375K OCP 10.7A OCP 53A PEAK 5.695A POWER BUDGET C AVG 1.262A PEAK 53A 53A +V3S R=130K +V1.8S AVG1.048 A AO6402L 220UF_25M£[ //10.6UF_5.924M£[ AVG 28.822A 100.82UF_0.842M£[ C GMT_AT1530F11U 1880UF_1.1M£[ // 2276UF_0.203M£[ VDD_CORE POWER BUDGET 4.711A INRUSH 0.9A TPS51217 POWER BUDGET V1.5_+-5% 20.070A POWER BUDGET 4.711A INRUSH 0.9A 100.82UF_0.842M£[ PEAK2.592A PEAK2.592A 100.82UF_0.842M£[ +V0.75S F 340K OCP 29.1A R=75K PEAK 20.070A AVG 11.531A TPS51216 TPS51216 560UF_25M£[ // 80UF_0.93M£[ POWER BUDGET 13.7 A +V1.5S F 340K OCP 10.1A R=115K PEAK 17.107A B AVG4.835 A 560UF_25M£[ // 1274.8UF_0.214M£[ AON7410 B +V1.5_CPU AON7410 +VTT_+-5% TPS51216 POWER BUDGET 13.7 A A CHANGING POINTS~~ F 340K TPS51218 SAME AS 2009 PROJECT OCP 10.1A TPS51217 SAME AS 2010 PROJECT +V1.8S IS NEW IC GMT_AT1530F11U PEAK 17.107A R=115K A AVG4.835 A 560UF_25M£[ // 1274.8UF_0.214M£[ CHARGE IS NEW IC BQ24725 VCC CORE IS NEW IC TPS51640 VTT IS NEW IC TPS51219 V0.85 IS NEW IC TPS 51641 INVENTEC V3_V5 IS NEW IC TPS51123 POWER BUDGET ~~IC SPEC (MAX CURRENT ) PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION AVG CURRENT ~~TEST RESULT(MAX CURRENT) TITLE MODEL,PROJECT,FUNCTION Block Diagram INRUSH ~~L/S TURN NO SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 4 REV X01 68 of 1 8 7 6 4 5 FUSE6000 65W-75W 8A(6036A0003401) 90W 10A(6036A0002901) 120W 12A(6036A0006001) 3 FUSE6050 PVBAT P3V3AL 1 2 1M_5%_2 10PF_50V_2 1 OUT 1 R6802 21E8 TP30 TP30 TP30 D6701 2 1 R6014 BATT+ 2 BATT+ 3 ID 4 B-I 5 TS 6 SMD G G1 7 SMC G G2 8 GND G G3 9 GND G G4 D SYN_200045GR009G18TZR_9P D6703 EZJZ0V500AA_DY 1 EZJZ0V500AA_DY 2 PVBAT RSC_0603_DY Q6010 Q6011 8 2 7 3 4 7 2 3 6 6 3 3 4 4 G S D 0.01_1%_6 NMOS_4D3S 2 0.1UF_25V_3 4 G 1 2 TPCA8065_H C6031 1 2200PF_50V_2 2 0.1UF_16V_2 PAD6000 2 0.1UF_25V_3 POWERPAD_2_0610 PVADPTR 1 2 1 C6030 1 NMOS_4D3S C6020 AM4410NC AM4410NC S 5 5 G D 1 2 6 NMOS_4D3S 1 2 7 5 C6033 Q6012 1 1 S PVPACK R6000 8 1 D 1 D6702 EZJZ0V500AA_DY 4.7K_5%_3 CSC0805_DY 33_5%_2 R6051 PVADPTR 1 2 1 1 R6015 1 RSC_0603_DY 2 0.1UF_16V_2_DY NEAR EC 33_5%_2 2 R6050 1 BI BI EC_SMB1_DATA EC_SMB1_CLK 21D2 21D3 R6801 C6800 1 CN6050 1K_5%_2 2 R6052 1 OUT BATT_IN 2 TP6005 21E6 21D2 21D3 D 1000PF_50V_2 220K_1%_2 2 1 TP6004 1 2 2 2 2 HW_V_ADC 33K_5%_2_DY TP6003 1 R6053 1 1 C7601 1000PF_50V_2 ACES_50315_0047N_002_4P 2 2 R6800 RSC_0603_DY C7602 R6054 2 8A_125V 1 1 4 LITTLEFUSE_R451015_15A_65V C6050 2 2 3 4 2 1 3 6 1 3 5 G2 2 4 2 G1 1 1 1 NFE31PT222Z1E9L 1 1 2 8 1 L7600 FUSE6000 C6014 1 PVPACK PVADPTR CN6000 2 2 R6005 4.3K_5%_2 2 2 A2 0.1UF_25V_3 2 R6004 4.3K_5%_2 A1 C6022 C 2 C6021 BAT54C_30V_0.2A 0.1UF_25V_3 1 2 2 2 2 1 2 3 4 B 1 1 CSC0805_DY 2 C6013 1 4.7UF_25V_5 C6012 2 4.7UF_25V_5 1 2 0.1UF_25V_3 2 C6025 2 CSC0402_DY 0.1UF_25V_3 C7600 C6024 1 1 0.1UF_16V_2 C6011 1 1 2 2 4.7UF_25V_5 SBR3U40P1_DY C6023 1 VRCHARGER_LG 2 C6010 2 1 2 1 RSC_0603_DY 1 R6016 1 EC_SMB2_DATA 1 R7600 2 BI 1 1 1 8 7 2 2 4 2 2 R6007 3 2 S BAT54C_30V_0.2A G 2 2 D6700 A2 D6001 C6028 2 3 4 3 1 A1 15 14 13 12 11 1 1 2 Q6001 1 110K_5%_2 21D2 R6001 2 0.01_1%_6 0.047UF_16V_2 D 2 16 2 NMOS_4D3S 1 REGN 1 1UF_10V_2 CSC0402_DY 37C3 56C8 21D3 CSC0805_DY ETQP3W4R7WFN AON7410 GND 2 17 C6027 LODRV SRP SRN 1 BTST ILIM CSC0603_DY C6035 C6004 4.7UF_25V_5 L6000 CSC0402_DY C6029 3.32K_1%_3 HIDRV NEAR IC C6034 C6003 4.7UF_25V_5 1 8 SCL 18 7 9 PHASE VRCHARGER_PH 6 SDA 19 5 8 BATDRV R6003 20 C 1 1 IOUT P3V3AL NEAR EC VCC 2 C6002 S 7 100PF_50V_2 100PF_50V_2 21 G ACDET C6036 C6037 TML C6001 470PF_50V_2 VRCHARGER_HG 6 10 ACN HW_I_ADC ACP B OUT CMSRC 21E6 ACDRV ACOK TI_BQ24725RGRR_QFN_20P 1 1 2 3 5 4 1 C6026 1UF_25V_3 1 D OUT NMOS_4D3S 10_5%_5 U6000 21E8 Q6000 R6012 AON7410 ACPRES 6 2 R6013 10K_5%_3 21E6 5 1 1 1 3 2 20.5K_1%_2 1 DIODES_BAV99 P3V3AL R6002 D6000 D6002 2 2 2 RSC_0603_DY 1 3 2 2 1 1 R6006 RSC_1206_DY 1 R6019 2 R6018 2 RSC_1206_DY C 1 C SHORT_0402 R6017 56D8 21D3 37C6 21D2 BI EC_SMB2_CLK 1 2 SHORT_0402 R6011 A SHORT_0402 C6032 0.1UF_16V_2 R6008 R6010 2 30K_5%_2 1 6.98_1%_2 2 1 A 2 1 2 1 1 R6009 2 4.3K_5%_2 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 5 REV X01 68 of 1 8 7 6 4 5 14D7 3 2 1 EN_5V 2 D 120K_1%_2 R6160 1 IN D PVBAT 14C7 2VREF EN_3V VRP5V0A_PH OUT OUT 6D3 1 1 IN 5V_PG OUT R6110 130K_1%_2 POWERPAD_2_0610 2 2 1 PAD6110 2 VBATP OUT 6C3 14C8 6C6 VBATP IN 1 1 7 8 2 1 3 4 2 1 1 7 8 R6150 1 15.4K_1%_2 1 330UF_6.3V 2 14D6 + 2 1 2 C6150 CSC0402_DY 2 1 OUT R6151 R6113 2 2 2 RSC_0402_DY 2 1 B C6120 10UF_6.3V_3 2 C6122 C6121 1UF_6.3V_2 1UF_25V_3 1 1 10K_1%_2 2 14D6 14C8 14D4 10K_1%_2 1 B 6 5 VRP5V0A_LDO IN 2 4 3 2 1 1 VRP5V0A_VIN ETQP3W3R3WFN C7615 3 EN_3V_5V IN 2 2 14C7 R6101 2 2 18 17 16 13 IN OUT RSC_0603_DY 4 G SKIP_3V_5V VRP5V0A 2 R7615 S S TI_TPS51123RGER_QFN_24P G AON7702A D 21 VRP3V3A_LDO OUT 14C7 L6150 1 Q6151 CSC0402_DY 330UF_6.3V 2 0.1UF_16V_2 D 1 C6155 1 2 AON7702A + R6155 2.2_5%_3 VRP5V0A_HG 20 VRP5V0A_PH 19 VRP5V0A_LG ENC VIN C7610 1 DRVL1 VREG5 C6100 3 LL1 DRVL2 GND 6.8K_1%_2 2 LL2 EN0 RSC_0603_DY R6100 14C6 14C8 4 5 25 DRVH1 U6100 DRVH2 5 6 22 1 21 15 4 3 2 1 1 7 VBST1 14 NMOS_4D3S G S AON7410 D 2 2 8 VBST2 SKIPSEL 1 9 Q6101 R7610 2 23 C 4.7UF_25V_5 S 0.1UF_16V_2 ETQP3W3R3WFN 24 PGOOD D OUT 2 VO1 VREG3 C6161 4.7UF_25V_5 G 14D6 1 VO2 8 C6160 NMOS_4D3S L6100 VRP3V3A 7 VRP3V3A_HG10 VRP3V3A_PH11 VRP3V3A_LG12 Q6150 0.22UF_6.3V_2 TRIP1 2 VFB1 21 VREF 1 TONSEL R6114 2.2_5%_3 C6115 VFB2 4.7UF_25V_5 TRIP2 4.7UF_25V_5 TML C6110 6 C6123 Q6100 C6111 AON7410 C 6 5 5 6 7 1 1 8 1 14C8 VO=(( R6150/R6151)+1)*2 VOUT=((R6100/R6101)+1)*2 VRP5V0A_LG OUT 6B3 14D5 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 6 REV X01 68 of 1 8 7 6 4 5 3 2 1 2 2 D 1 PAD6210 P5V0A D 4.7UF_25V_5 1 2 C6212 1 4.7UF_25V_5 2 C6211 4.7UF_25V_5 2 C6210 1 8 7 5 6 S 2 1 DRVH 14 VRP1V5_HG 2.2_5%_3 1 4 2 15 2 C6215 1 VBST 3 2 D G R6215 V5IN NMOS_4D3S FDMC8884 U6200 12 Q6200 C6216 2.2UF_6.3V_3 1 1 P0V75S POWERPAD_2_0610 PVBAT 0.1UF_16V_2 L6200 3 VTTSNS 1 14C2 OUT + C6200 560UF_2.5V 1 C 2 2 PAD6220 2 PCMC104T_1R0MN POWERPAD1X1M VRP1V5 1 4 GND 1 MODE VTTGND 4 18 TRIP VTTREF 5 0.22UF_6.3V_2 2 TI_TPS51216RUKR_QFN_20P C6221 C6220 75K_1%_2 1 21 1 2 19 TML 1 R6202 1 R6203 2 100K_5%_2 C6218 2 2 3 1 2 VTT CSC0402_DY RSC_0603_DY 2 1 P0V75M_VREF 0.1UF_16V_2 1 0.01UF_50V_2 2 C6217 2 52.3K_1%_2 R6201 1 B VLDOIN S 7 REFIN 9 G 8 VDDQSNS R7620 20 11 PGOOD C7620 VREF 2 6 4 2 10K_1%_2 2 1 10UF_6.3V_3 DDR3L_SEL 1 10 R6200 IN D PGND VRP1V5_LG Q6201 11 FDMS0310AS DRVL 8 S5 5 IN C 16 7 EN_1V5 SW VRP1V5_PH 6 14D1 S3 13 2 IN 17 3 14D1 EN_0V75 1V5_PG OUT B 14C2 VOUT=REFIN=1.8*(R6201/(R6200+R6201)) MODE=100KOHM:TRACKING DISCHARGE A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 7 REV X01 68 of 1 8 7 6 4 5 3 2 1 D D P5V0A P3V3S 1 C6971 GMT_AT1530F11U_SOP8_8P U6970 VOUT=((13K+10K)+1)*0.8 9 TML OCP=4.5AMP L6970 8 VIN LX 7 VRP1V8S_PH 1 VRP1V8S 2 OUT 14A2 PAN_ELL5PR2R2N 1 22UF_6.3V_5 C6970 1 2 10K_1%_2 2 R6972 1 0.1UF_16V_2 2 C6973 GND 3 PGND 2 2 CSC0402_DY REF C6974 4 13K_1%_2 EN FB 2 5 6 0.1UF_16V_2 1 C6972 2 B IN VCC 1 EN_1V8 14B1 1 R6973 1 2 10_5%_2 R6970 2 10UF_6.3V_3 C 1 C B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 8 REV X01 68 of 1 8 7 6 4 5 3 2 1 D D 1 C6312 2 C6311 2 C6310 1 1 1 1 2 2 3 3 4 4 VRP1V05S OUT 14A8 1 + 560UF_2.5V C6300 1 CYN_PCMB063T_R68MS_4P 2 2 R7630 1 1 CSC0402_DY RSC_0603_DY 2 2 4 C6316 8 2.2UF_6.3V_3 1 PGND GND TRIP 7 86.6K_1%_2 2 6 R6302 5 1 VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND S B 1 G 0.01UF_50V_2 D TI_TPS51219RTER_QFN_16P C6319 8 2 4 L6300 P5V0A C7630 9 8 V5 1 VSNS 7 4 6 VCC_SENSE_VCCIO 5 DL C6301 VRP1V0_VCCP_LG GSNS 2 VRP1VO_VCCP_HG 22UF_6.3V_5 11 2 2 2 DH 10 7 1 REFIN 3 4.7UF_25V_5 2 2 IN 2 COMP 44A3 IN 1 VSS_SENSE_VCCIO 0_5%_2_DY Q6301 2.2UF_6.3V_3 44A3 VCCIO_SEL IN FDMS0310AS 2 C6318 1 46B4 4.7UF_25V_5 VRP1VO_VCCP_PH 1 12 2 SW 3 BST EN MODE PGOOD VREF S 1 R6307 3 13 14 15 16 17 2 10K_5%_2 G PWPD 1 D R6306 Q6300 0.1UF_16V_2 U6300 C 2 NMOS_4D3S 2.2_5%_3 1 FDMC8884 P3V3A C6315 2 6 R6315 1 5 VCCP_PG OUT 1 PAD6310 1 14A8 100K_5%_2 R6303 2 14B6 C POWERPAD_2_0610 PVBAT EN_VCCP IN 4.7UF_25V_5 14B7 B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 9 REV X01 68 of 1 8 7 6 4 5 3 2 1 D 1 D C6522 C6520 1 2 2 2 1 0.01UF_50V_2 R6520 5.11K_1%_2 1 3300PF_50V_2 VCCSA_SENSE C6521 0.22UF_6.3V_2 2 1 5 4 3 2 6 MODE VOUT SLEW COMP 1 GND C TI_TPS51461RGER_QFN_24P 25 TML 24 VIN SW 7 23 VIN SW 8 22 VIN SW 9 21 PGND SW 10 C6511 20 PGND SW 0.1UF_16V_2 19 PGND L6500 1 2 2 3 3 4 4 VRPVCCSA 14A6 1 1 C6501 C6502 C6503 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY 2 2 C6500 2 1 0.1UF_16V_2 RSC_0603_DY EN_SA IN 14B5 IN 45A2 IN 45A2 1 2 13 14 15 17 18 OUT 2 R7650 16 1 C6515 1 EN VID0 VID1 PGOOD 1 CYN_PCMB063T_R33MS_4P 11 12 BST V5FILT 2 VRPVSA_PH 2 U6500 V5DRV 1 1 2 22UF_6.3V_5 VREF C C6510 2 RSC_0402_DY 1 P5V0A 45A2 IN R6521 R6524 1 2 VCCSA_VID0 C7650 CSC0402_DY SHORT_0402 1 C6524 2 2 VCCSA_VID1 B SHORT_0402 2 1UF_6.3V_2 2 C6523 B 1UF_6.3V_2 1 R6525 1 SA_PG OUT 14A6 21B6 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 10 REV X01 68 of 1 4 5 3 PVBAT 2 1 100PF_50V_2 15.4K_1%_2 IN PVBAT_CPU 2 10_5%_3 C6630 2.2UF_10V_3 1 4.7UF_10V_3 R6627 2.2UF_6.3V_3 44C2 11A3 IN PVCORE_PG 17 CPGOOD VR_SVID_CLK 18 VCLK 1 2 C6617 4.7UF_25V_5 1 2 C6616 1 C6615 2 4.7UF_25V_5 28.7K_1%_2 1 CSW1 45 2.2_5%_3 CDL1 44 V5DRV 43 1 2 0.1UF_16V_2 1 8 2 L6610 R7661 C6600 470UF_2V 470UF_2V C7661 C CSC0402_DY 2 U6600 C6601 1 RSC_0603_DY + C6622 4 1 11D5 OUT 11D5 OUT 3 OUT PVCORE 2 2 11A4 VR_ON 100K_5%_NTC 3 1 40B4 2 49B7 C6633 16 1 2 1 11D5 IN 2 46 CBST1 VR_ON R6604 1 2 IN 162K_1%_2 S 11A7 V3R3 2 R6603 2 1 V5_CPU 4 1 1 15 2.2UF_6.3V_3 2 CDH1 47 G C6634 1 48 R6601 C 1 VREF V5 2 OUT GOCP-R 14 2 4 GND D VREF_CPU R6605 1 PAN_ETQP4LR36ZFC_4P 5 2 13 11D7 2 11D1 R6602 Q6611 IN 11D6 11D4 11B3 1 49 FDMS0306AS VREF_CPU 11C8 11B7 11A4 11A7 1 S CTHERM COCP-R CF-IMAX CCSP1 CCSN1 CCSN2 CCSP2 CCSP3 CCSN3 CCOMP CVFB CGFB P3V3A IN 17.8K_1%_2 G 56K_1%_2 7 2 3 C6629 CPU_CSP1 OUT 11D7 8 R6617 1 7 V5_CPU 6 OUT 11D6 0.033UF_16V_2 P5V0A 5 4 CPU_CSP1 CPU_CSN1 5 6 CPU_CSN2 11C4 11C8 + IN IN IN 7 CPU_CSP2 8 9 0 IN DNP 10 R6723 11 VCCSENSE 0 IN DNP 12 VSSSENSE R6719 R6626 3.3K_1%_2 2 0 1 DNP 11B7 D R6716 11A7 Q6610 0 11A4 IN NMOS_4D3S DNP 2 VREF_CPU FDMS7692 R6714 D C6623 R6619 1 3 11C3 100K_5%_NTC 21 8.45K_1%_2 DNP CPU_CSN1 OUT 2 30K 11D5 0.1UF_16V_2_DY 2 R6712 2 11D3 1 11D3 200K DNP R6618 P3V3A 11C3 44B3 R6625 R6711 44B3 C6631 DNP 1 D C6614 2 3 56K VREF_CPU IN 6 R6627 11A4 11C8 3 3.3K DNP 11A7 11D4 11D3 1 R6626 C6632 11B7 11D6 4.7UF_25V_5 2+0 11B3 1 2+1 4.7UF_25V_5 2 24K_1%_2 2 68UF_25V C6610 90.9K_1%_2 C6000 2 2 1 1 OUT + 2 PVBAT_CPU 2 2 1 1 1 R6623 R6621 1 1 POWERPAD_2_0610 1 39K_1%_2 4.7UF_25V_5 R6622 1 C6613 2 43K_1%_2 2 R6620 1 1 VREF_CPU IN 4.7UF_25V_5 11A4 C6612 11A7 2 11B7 4.7UF_25V_5 11C8 1 11D4 C6611 11D7 2 PAD6610 2 6 1 7 4.7UF_25V_5 8 CPU_CSN2 P5V0A R6628 R6711 44C2 0_5%_2_DY 2 2 200K_1%_2 44C2 11A3 OUT BI VR_SVID_ALERT#19 ALERT# VR_SVID_DATA 20 VDIO CPU_PROCHOT# 21 VR_HOT# TI_TPS51650RSLR_QFN_48P PGND 42 CDL2 41 CSW2 40 C6625 CPU_CSP2 1 2 0.033UF_16V_2 PVBAT_CPU GPGOOD 38 2.2_5%_3 CDH2 VBAT 37 1 2 0.1UF_16V_2 R6616 2 10K_5%_3 R6610 11D3 1 1 R6608 2 1 1 8 B R7662 4.12K_1%_2 P3V3A 1 + + 3 2 1 2 3 R6731 1 2 VREF_CPU IN 11A7 OUT 12C8 11B7 11C8 11D4 11D6 11D7 RSC_0402_DY 1 P3V3A 0.1UF_16V_2_DY 40B4 11C7 OUT 11B7 OUT PVCORE_PG 11C7 44C2 IN 1 1 2 C6635 130_1%_2 R6633 VR_SVID_CLK INVENTEC TITLE 2 2 49B7 0.1UF_16V_2 C6727 100K_5%_NTC 2 12C5 R6729 1 1 2 15.4K_1%_2 54.9_1%_2 1 2 VREF_CPU R6632 IN 2K_5%_2 11A4 R6732 11B7 1 11C8 12C5 11D4 1 11D6 2 2 R6728 11D7 A P1V05S 2 IN R6631 8.66K_1%_2 R6730 100K_5%_2 2K_5%_2 11C7 1 OUT 1 VR_ON R6634 A GSKIP# 2 2 20K_5%_2 R6720 GPU_CSP1 R6630 IN 2 R6724 2 GPU_CSN1 1 1 EN_PVCORE 0_5%_2 2 470UF_2V 2 0_5%_2_DY R6723 470UF_2V CSC0402_DY 2 2 4 R6718 1 2 C6603 C6602 C7662 12B8 1 1 RSC_0603_DY 21 7 2 3 2 3 4 OUT 4 1 L6620 S OUT 0_5%_2_DY R6719 6 5 CPWM336 GPWM235 GPWM134 33 32 31 30 29 2 OUT 1 100PF_50V_2 0_5%_2_DY 2 2 1 1 1 1 VREF_CPU D C6726 IN R6716 0_5%_2_DY IN P3V3A G R6714 21D3 PVCORE 2 28.7K_1%_2 3 PVBAT Q6621 0_5%_2 R6715 11D7 11D6 11C8 11A4 11A7 11D4 28 2 0_5%_2 2 2 IN 27 0_5%_2 GFX_VCC_SENSE R6713 1 26 2 25 IN 1 FDMS0306AS 45C3 1 PAN_ETQP4LR36ZFC_4P GFX_VSS_SENSE R6712 30K_1%_2 R6609 2 S 45C3 1 100K_5%_NTC 20K_1%_2 B 2 162K_1%_2 R6607 17.8K_1%_2 G 1 CPWM3 GPWM2 GPWM1 GSKIP# GCSN2 GCSP2 GCSP1 GCSN1 GCOMP GVFB R6629 GTHERM GF_IMAX GGFB 1 24 D 23 1 11D1 Q6620 PVAXG_PG CBST2 C6624 2 NMOS_4D3S OUT 1 FDMS7692 11A4 SLEW 39 IN 8 R6606 22 7 OUT 6 21C3 5 41D6 PVAXG_PG 44C2 11C7 BI MODEL,PROJECT,FUNCTION VR_SVID_DATA Block Diagram R6638 SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 11 REV X01 68 of 1 8 7 6 4 5 3 2 1 D D 11A6 OUT 11A6 OUT GPU_CSN1 C6722 GPU_CSP1 1 2 0.033UF_16V_2 8 1 PVBAT R6704 2 100K_5%_NTC 1 1 PVAXG 2 28.7K_1%_2 1 2 2 OUT 12C5 4 1 4.7UF_25V_5 C6713 2 4.7UF_25V_5 1 C6712 2 4.7UF_25V_5 1 C6711 2 4.7UF_25V_5 2 2 2 2 3 C6702 560UF_2.5V_DY C6710 + + CSC0402_DY 3 C7671 1 1 1 C6701 470UF_2V_DY 2 1 C6700 + 1UF_6.3V_2 RSC_0603_DY S C6721 PVBAT_AXG R7671 470UF_2V G 2 D Q6711 P5V0A TI_TPS51601DRBR_SON_8P PAD6710 POWERPAD_2_0610 2 L6710 21 DRVL 5 4 1 8 6 1 2 3 4 3 7 FDMS0306AS GND R6703 2 1 4 SW VDD 7 PWM R6702 1 PAN_ETQP4LR36WFC_4P 6 SKIP# 3 8 5 2 PAD DRVH 2 GSKIP# GPWM1 C 162K_1%_2 17.8K_1%_2 3 IN IN 2 S 11B5 BST 9 G 11A4 1 1 1 U6710 R6705 12B1 1 0.1UF_16V_2 D 2 NMOS_4D3S 2.2_5%_3 1 IN Q6710 C6720 2 FDMS7692 R6701 1 7 5 C 6 PVBAT_AXG B B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 12 REV X01 68 of 1 8 7 6 4 5 3 2 1 R7016 16A1 13B2 16A8 16C4 1 DGPU_PWR_EN IN EN_DGPU 2 OUT 13C8 10K_5%_2 PVBAT 4.7UF_25V_5 C6762 2 4.7UF_25V_5 2 4.7UF_25V_5 C6760 2 C6761 1 0.1UF_16V_2 8 2 2 1 1 2 2 1 + 2K_1%_2 3 2 1 1 + 3 470UF_2V 2 470UF_2V C C6752 P3V3S_DGPU 1 2 + R6750 2 R7675 1 1 8 7 2 3 R6754 1 21K_1%_2 VOUT 1 C6751 470UF_2V 2 C6750 8.66K_1%_2 D0 R6753 6 1 1 5 R6751 D1 56F7 56D5 13C2 2 R7017 REA_RT8208BGQW_WQFN_16P 10K_5%_2 GND 1 POWERPAD_2_0610 OUT 16.2K_1%_2 17 EN_DEM IN VRPVCORE_DGPU 4 2 15 C7010 2 1 14 PWRCNTL_0 3 RSC_0603_DY CSC0402_DY G1 56F7 2 2 EN_DGPU IN 7 1 3 56C5 S FB 9.53K_1%_2 13D1 IN 2 PWRCNTL_1 1 7 C7675 G0 6 VRPVCORE_DGPU_LG 8 G R6758 VRPVCORE_DGPU1 IN POWERPAD_2_0610 PAN_ETQP4LR36WFC_4P 1 2 VRPVCORE_DGPU_PH PGOOD CS PAD6750 13C3 L6750 1 10 D PVCORE_DGPU 1 1 C 2 11 3 PHASE VRPVCORE_DGPU_HG 4 12 5 VDD 0_5%_2_DY PAD6751 UGATE 2 4 2 D DGPU_PWRGD 1 Q6751 OUT 2 FDMS0308AS 13B2 0.1UF_16V_2 1 VDDP LGATE 52C6 13 4 1UF_6.3V_2 1 C6757 1UF_6.3V_2 2 1 C6754 2 2 2 S 9 2.2_5%_3 BOOT G 10_5%_2 TON D 16 2 Q6750 U6750 R6756 C6753 NMOS_4D3S R6752 FDMS7692 240K_5%_2 1 6 2 3 1 5 R6755 P5V0A SLP_S3#_3R1 IN 1 1 2 2 D R7020 21D6 13A2 14B8 49A1 POWERPAD_2_0610 PAD6760 1 45D3 14A6 14D2 DGPU_PWRGD 52C6 13C8 IN OUT P.S. R6750(R1) R6751(R2) R6753(R3) R6754(R4) B B P1V5S_DGPU P1V5S_DGPU 1 R7018 2 49A1 21D6 14B8 13D2 14A6 14D2 45D3 IN DGPU_PWR_EN 1 R7019 EN_VPCIE 2 13A6 1 R7030 SLP_S3#_3R1 2 0_5%_2_DY 1UF_10V_5 1 C6951 2 22UF_6.3V_5 1 2 OUT 1K_5%_2 1UF_6.3V_2 13A2 IN 2 2.7K_1%_2 C6950 1 10K_1%_2 1 2 2 GMT_G9731AF11U_SOP_8P OUT 1 R6950 2 3 R6951 1UF_10V_5 1 C6954 TML 2 4 VEN GND 9 POK 8 VPP EN_VPCIE ADJ IN VO_1 7 13B1 A VIN 6 VO_2 5 C6952 U6950 68PF_50V_2 1 VRPVPCIE 13D2 16A8 C7011 16A1 16C4 2 2 P5V0A 22UF_6.3V_5 C6955 1 100K_5%_2_DY PVPCIE A PAD6950 13A3 IN VRPVPCIE 1 1 2 2 POWERPAD_2_0610 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 13 REV X01 68 of 1 8 7 6 4 5 3 2 DDR_P1V5 OUT 6D6 1 2 2 SSM3K7002BFU 6C1 VRP5V0A IN 14C8 6C1 VRP5V0A IN 1 1 2 2 2 D7001 C7001 1 DIODES_BAV99 21D3 49B3 1 2 2 2 0.1UF_16V_2 13 P3V3S 2 VRP5V0A_LG IN P5V0AL 6B4 VRP5V0A_LDO1 A2 IN 1 2 2 1 2 P15V0A R7013 1 BAT54C_30V_0.2A_DY RSC_0402_DY R7000 OUT POWERPAD1X1M 6D6 2 7B3 14C2 1UF_25V_3 IN 1V5_PG 1V5_PG P3V3_LDO RSC_0402_DY 14D4 14D6 6C1 VRP5V0A IN 1 R7001 P1V5 SKIP_3V_5V 2 OUT 6B5 14C8 6B6 1 VRP3V3A_LDO IN 1 PAD6200 2 2 1 1 10K_5%_2 PAD6121 6C6 6C3 C VBATP IN 1 R7002 VRP5V0A_VIN 2 OUT POWERPAD1X1M 6B5 P5VAUXON IN 1 EN_3V_5V 2 OUT VRP1V5 IN 1 1 2 2 C POWERPAD_2_0610 6B4 0_5%_2 P1V8S DGPU VCCSA VCCIO R7040 R7021 SLP_S3#_3R 1 EN_VCCP 2 OUT 9C6 IN VCCP_PG 1 EN_SA 2 9D6 OUT 10B4 1 IN 14A8 0_5%_2 P3V3S C7040 CSC0402_DY R7050 EN_1V8 2 OUT 2 1 8B6 10K_5%_2 B 1 2 B 0.1UF_16V_2 1 47K_5%_2 C7020 21D6 14A6 13A2 13D2 14D2 49A1 45D3 2 PAD6201 7C1 R7003 2 POWERPAD_2_0610 0_5%_3 21F6 14D8 15D6 OUT 2 2 EN_3V C7004 1 PAD6120 1 D CSC0402_DY C7003 C7002 C VRP3V3A_LDO EN_1V5 2 0_5%_2 C7006 D7002 IN R7012 2 A1 POWERPAD_2_0610 D7000 1 2 IN 1 SLP_S5#_3R IN 1 1 6C8 VRP3V3A DIODES_BAV99 6B6 7C7 13 0.1UF_16V_2 6B3 14C6 OUT 2 POWERPAD_2_0610 0.1UF_16V_2 3 7C7 C7005 PAD6100 P5VAUXON OUT 0.1UF_16V_2 D IN EN_0V75 2 47K_5%_2 2 14D4 P3V3AL 21F6 14C8 15D6 1 1 G 14C8 R7010 SLP_S3#_3R IN PAD6150 0.047UF_16V_2 EC_PW_ON# 1 S IN C7000 D Q7000 14D6 P5V0A 3 EN_5V 21D6 14A6 13A2 13D2 14B8 49A1 45D3 1 3V & 5V 15D4 21C3 1 C7050 0.01UF_50V_2 1 2 P3V3S P3V3S R7041 VCCP_PG IN 14A6 10A5 IN 2 SA_PG SA_PG OUT 2 21B6 D7040 VCCP_PG OUT P1V8S NC 14B6 14A8 9C6 10K_5%_2 1 R7022 2 10K_5%_2 14B8 49A1 45D3 13D2 21D6 13A2 14D2 IN SLP_S3#_3R 3 1 PAD6900 DIODE-BAT54-TAP-PHP 8C2 A IN VRP1V8S 1 1 2 2 A POWERPAD_2_0610 P1V05S PAD6300 1 1 2 PVSA 2 POWERPAD_2_0610 PAD6500 10C1 PAD6301 9B1 IN VRP1V05S 1 1 2 IN VRPVCCSA 1 1 2 2 INVENTEC POWERPAD_2_0610 2 POWERPAD_2_0610 TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 14 REV X01 68 of 1 8 7 6 4 5 3 2 P15V0A 1 P3V3AL P3V3A P3V3AL 1 1 D S 4 1 1 2 2 2 R7105 P3V3_LDO POWERPAD_2_0610 5 100K_5%_2 R7104 6 G 3 NMOS_4D1S 100K_5%_2_DY 1 2 PVBAT PAD7100 Q7102 1 3 2 AO6402AL 1 R7106 21C3 14D8 SENSE 1 S 2200PF_50V_2 RESET# 3 OUT 21F6 14C8 14D8 2 D 2 P5VAUXON SSM3K7002BFU 3 5 C7100 G R7100 Q7103 D 1 1 1 2 THRM_SHUTDWN#3 1 OUT IN VDD 2 NC D7490 40B1 40A8 56D6 EC_PW_ON# 2 U7490 510K_1%_2 D 200_5%_2 D 4 Q7101 R7491 10K_5%_2 120K_1%_2 1 2 G S GND R7492 GND DIODE-BAT54-TAP-PHP SSM3K7002BFU 2 2 1 2 TI_TPS3801_01_SC70_5P P3V3AL P15V0A P3V3S C C PAD7101 POWERPAD_2_0610 Q7105 D S 4 G 3 2 2 1 1 200_5%_2 32 Q7106 15B8 15A4 15B4 49B1 16A7 SLP_S3_3R IN 1 G SSM3K7002BFU 2 2 2 SSM3K7002BFU 680PF_50V_2 G C7102 1 0_5%_2 2 SLP_S3_3R C7101 IN S 49B1 16A7 15A4 15B4 D Q7104 2200PF_50V_2 1 3 1 2 2 D AO6402AL R7108 S NMOS_4D1S 1 22UF_6.3V_5 6 C7103 5 R7109 1 1 2 470K_5%_2 2 R7107 1 1 P5V0S P5V0A PAD7102 POWERPAD_2_0610 Q7107 1 D S 4 G 3 2 1 2 B 1 2 3 2 Q7108 15B8 15A4 15B4 49B1 16A7 IN SLP_S3_3R 1 G SSM3K7002BFU 2 2 C7104 0_5%_2 CSC0402_DY 1 2 D AO6402AL R7110 1 S NMOS_4D1S 22UF_6.3V_5 6 C7105 1 5 R7111 2 200_5%_2 1 B P1V5S P1V5 PAD7103 POWERPAD_2_0610 Q7109 1 2 R7113 3 2 6 3 5 4 G IN NMOS_4D3S 1 1 G 2 SSM3K7002BFU AON7410 R7112 SLP_S3_3R 200_5%_2 7 Q7110 15B4 49B1 16A7 15B8 1 1 3 2 S 2 D A P0V75S R7114 Q7112 23 C7107 AON7410 D 4 S G NMOS_4D3S 22UF_6.3V_5 5 8 2 2 6 A 1 1 200_5%_2 S 1 D 7 1 8 2 INVENTEC D G TITLE S 1 MODEL,PROJECT,FUNCTION SSM3K7002BFU Block Diagram 2 2 C7106 CSC0402_DY 1 Q7111 0_5%_2 SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 15 REV X01 68 of 1 8 7 6 4 5 P1V5 3 2 1 P1V5S_DGPU Q7113 8 D S 1 2 7 POWER EXPRESS 3 6 5 G 4 S 1 NMOS_4D3S AON7410 Q7114 8 D D 7 2 6 3 5 G DURING RESET AFTER RESET 4 HIGH DGPU_PWR_EN# NMOS_4D3S D 0 : DGPU POWER SWITCH TURNED ON HIGH AON7410 1 1 : POWER SWITCH TURNED OFF R7116 16A5 IN 1 2 R7115 0 : DGPU POWER IS NOT STABLE 1 16B7 DGPU_PWR_EN_15R 200_5%_2 220K_5%_2 DGPU_PWRGD 1 : DGPU POWER IS STABLE 2 C7108 2 680PF_50V_2 3 0 : KEEP DGPU IN RESET LOW LOW DGPU_HOLD_RST# 1 : RESET IS RELEASED D Q7115 SSM3K7002FU S G P3V3S P3V3S_DGPU 2 0_5%_2_DY R7042 1 DIODES_DMP2305U_SOT23_3P Q7003 P3V3S S 4 G 3 16A1 13D2 IN DGPU_PWR_EN1 R7039 1 2 2 2 1 200_5%_2 220K_5%_2 G G 1 G S 1 C7021 R7119 1 2 1 R7120 DGPU_PWR_EN_15R IN 13B2 0_5%_2 AO6402AL 16A5 C7023 D 16A8 NMOS_4D1S CSC0402_DY 6 2 5 16D7 C 2 Q7002 SSM3K7002BFU D CSC0402_DY D 2 2 R7031 Q7118 1 2 3 0_5%_6_DY 2 R7038 1 10K_5%_2 P1V8S_DGPU S S 1 C P1V8S 2 1 1 CSC0402_DY DGPU_PWR_EN_3R IN C7024 16A6 D 16B7 C7110 2 3 680PF_50V_2 B B D Q7119 16A6 DGPU_PWR_EN_3R IN 1 SSM3K7002FU G S 16C7 1 2 P3V3S R7121 D IN DGPU_PWR_EN#1 G SSM3K7002BFU DGPU_PWR_EN_15R OUT 16B7 16D7 D DGPU_PWR_EN_3R 1 G A R7047 IN SLP_S3_3R 1 2 0_5%_2_DY INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 16C4 S 51B6 S G S 1 2 51C7 2 1 16A8 SSM3K7002BFU D 1R7035 2 0_5%_2 13D2 2 DGPU_PWR_EN CSC0402_DY IN C7022 13B2 16A1 13B2 2 R7034 Q7019 IN 16C7 SSM3K7002BFU 13D2 16C4 3 2 1 Q7018 10K_5%_2 R7033 2 3 A 16B7 OUT Q7120 1M_5%_2 1 P15V0A P3V3_LDO DGPU_PWR_EN 3 2 10K_5%_2 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 16 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 0~49(PCB SCREW) D D BOUNDARY SCAN TEST POINT FIX1 1 FIX_MASK 1 FIX5 PVCORE FIX_MASK 1 FIX2 1 FIX_MASK FIX3 1 1 TP30 FIX_MASK FIX8 1 FIX_MASK 1 TP30 TP5 1 TP30 PVAXG TP2 1 FIX4 TP4 1 TP30 PVCORE_DGPU FIX7 FIX_MASK TP3 1 FIX6 FIX_MASK 1 PVBAT TP1 TP6 1 TP30 1 TP30 PVADPTR TP7 TP30 FIX_MASK TP8 1 TP30 1 TP9 TP10 1 TP30 TP30 C C CPU PCB 1 1 1 1 S1 SCREW300_1000_1P S2 SCREW300_1000_1P S3 SCREW300_1000_1P GPU S10 1 SCREW330_600_1P 1 S11 1 SCREW300_1000_1P 1 STD16 STDPAD_1.15_6-TOP 1.6MM S15 SCREW330_600_1P SCREW330_600_1P 1 WLAN S14 SCREW330_600_1P 1 S12 S23 SCREW330_600_1P SCREW330_600_1P S13 S5 B 1 1 1 STD17 STDPAD_1.15_6-TOP S24 1.6MM SCREW330_600_1P SCREW330_600_1P 3G 1 1 STD18 B STDPAD_1.15_6-TOP 1 1 1 S6 1.6MM SCREW300_1000_1P S7 SCREW300_1000_1P S8 SCREW300_1000_1P FAN 1 1 1 S18 SCREW220_700_1P S21 SCREW120_0_600_1P S20 SCREW540_1000_NP_1P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 17 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 50-99(HALL SENSOR) D D P3V3AL C 1 C R50 VDD 1 OUT 2 2 100K_5%_2 U50 GND LID_SW#_3 OUT 21D3 1 1 3 D50 MAG_MH248BESO_SOT23_3P C50 VARISTOR_DY 2 2 1000PF_50V_2 B B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 18 REV X01 68 of 1 8 7 6 5 4 3 2 1 REFERENCE 100~199(LED) SUSPEND LED D P3V3A D D154 21B6 IN PWR_OLED# TP100 1 R160 1 2 1 2 TP30 150_5%_2 HT_191UY P5V0S POWER ON LED C C D159 21D6 IN PWR_WLED# TP101 1 R150 1 2 1 2 TP30 19_217_T1D_CP1Q2QY_3T 220_5%_2 P3V3S WIFI/WIMAX/3G/LTE LED D156 21D6 IN WL_OLED# 1 R155 TP104 1 2 1 2 TP30 HT_191UY 150_5%_2 DC IN / BATTERY CHARGE LED D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED B B D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER BLINK:LOW BATTERY P5V0A D152 21B6 IN DCIN_WLED# 1 R152 TP102 1 2 1 2 TP30 19_217_T1D_CP1Q2QY_3T 220_5%_2 P3V3AL D155 A BAT_OLED# 21B6 IN 1 TP103 A R154 1 2 1 2 TP30 HT_191UY 150_5%_2 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 19 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 200~249(POWER CONN) R253 REFERENCE 250~299(KB/TP CONN) 1 2 0_5%_2_DY CN250 P3V3S SCAN_OUT<17..0> 21B3 OUT 16 SCAN_OUT<16> G2 30 30 G1 G1 29 28 28 27 27 SCAN_OUT<13> SCAN_OUT<15> SCAN_OUT<1> SCAN_OUT<0> 26 26 25 25 24 24 23 23 SCAN_OUT<11> SCAN_OUT<9> SCAN_OUT<5> SCAN_OUT<6> 22 22 21 21 0 11 9 5 6 10 14 8 12 7 3 2 G2 29 1 7 31 SCAN_OUT<4> SCAN_OUT<2> 15 SCAN_IN<7..0> 32 31 4 13 IN 33 32 SCAN_OUT<17> 2 20D3 34 33 17 D 21B3 34 SCAN_OUT<10> SCAN_OUT<14> SCAN_OUT<8> SCAN_OUT<12> SCAN_IN<7..0> 20 20 19 19 18 18 17 17 16 16 15 15 SCAN_OUT<7> SCAN_OUT<3> SCAN_IN<7> SCAN_IN<2> 14 D 21B3 20C6 IN 0 SCAN_IN<0> D250 1 2 VARISTOR_DY 1 SCAN_IN<1> D251 1 2 VARISTOR_DY 2 SCAN_IN<2> D252 1 2 VARISTOR_DY 3 SCAN_IN<3> D253 1 2 VARISTOR_DY 4 SCAN_IN<4> D254 1 2 VARISTOR_DY 5 SCAN_IN<5> D255 1 2 VARISTOR_DY 6 SCAN_IN<6> D256 1 2 VARISTOR_DY 7 SCAN_IN<7> D257 1 2 VARISTOR_DY 14 13 13 12 12 11 11 SCAN_IN<3> SCAN_IN<4> SCAN_IN<0> SCAN_IN<5> 10 10 SCAN_IN<6> SCAN_IN<1> C C 3 4 0 5 6 1 21B6 IN 21D6 IN IN 21D6 9 9 8 8 7 7 6 6 5 5 4 4 CAPS_LED#_3 R250 1 2 200_5%_2 3 3 SCROLL_LED#_3 NUM_LED#_3 R251 1 2 2 1 2 200_5%_2 200_5%_2 2 R252 1 1 D258 D259 D260 VARISTOR_DY 1 VARISTOR_DY 1 1 VARISTOR_DY KEYBOARD CONN 2 2 2 PTWO_AFF340_A2G1V_P _34P B B P5V0S CN200 CN280 21D2 21D3 BI BI 1 1 IM_CLK_5 2 2 IM_DAT_5 3 3 4 4 21D3 G G1 G G2 1 1 G 3 2 2 G 4 ACES_50224_0020N_001_2P ACES_50503_0044N_001_4P D200 VARISTOR_DY 1 1 2 PWR_SWIN#_3 OUT 2 21D2 21D3 A A D280 3 PHP_PESD5V2S2UT_SOT23_3P_DY POWER CONN TOUCHPAD CONN INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 20 REV X01 68 of 1 8 7 6 5 4 3 2 1 REFERENCE 300~389(KBC) P3V3AL P3V3AL_R P3V3S F F P3V3AL CLOSE PIN4 R318 1 R320 2 0.1UF_16V_2 100K_5%_2 D300 15D6 14C8 14D8 P5VAUXON IN 2 NC C306 2 10UF_6.3V_5_DY 1 2 C312 1 C304 2 0.1UF_16V_2 1 0.1UF_16V_2 C303 2 0.1UF_16V_2 1 2 C302 1 0.1UF_16V_2 2 C301 1 0.1UF_16V_2 2 FOR ESD PROTECT 2 C313 2.2_5%_3 C300 1 1 2 4.7UF_6.3V_3 1 3 1 VCC_POR# OUT 21B6 DIODE-BAT54-TAP-PHP 0_5%_1 R301 1 1 5D3 4 102 115 88 76 46 VDD AVCC 2 VCC5 2 0.1UF_16V_2 1 LPC_3S_AD<3> LAD2/GPIOF3 128 LPC_3S_AD<2> IN LPC_3S_AD<1> 1 100 GPIO93/AD3 LAD1/GPIOF2 127 TP30 108 GPIO05/AD4 LAD0/GPIOF1 126 LPC_3S_AD<0> SERIRQ/GPIOF0 125 PCI_3S_SERIRQ TP311 EC_BKLTEN OUT IN IN LCM_BKLTEN 96 GPIO04/AD5 ACPRES 95 GPIO03/AD6 94 GPIO07/AD7 1 2 GPIO11/CLKRUN# 14D2 14A6 14B8 1 13D2 36B2 0.1UF_16V_2 C315 2 2 C317 0.1UF_16V_2 1 45D3 49A1 13A2 37B1 1 101 TP314 SLP_S3#_3R 1 TP30 105 GPIO95/DA1 TP30 106 GPIO96/DA2 107 GPIO97/DA3 HDMI_HPD_EC GPIO94/DA0 TP324TP30 RUNSCI0#_3 ECSCI#/GPIO54 29 GPIO10/LPCPD# 124 TP30 1 GPIO85/GA20 121 EC_3S_A20GATE KBRST#/GPIO86 122 KBRST# 20B7 P3V3AL R346 2 49A6 1 49A5 49B8 100K_5%_2 49A8 19B4 32A6 32C1 33C6 24A2 D 22D7 EC_SMB2 1 TP315 SCROLL_LED#_3 OUT 1 TP316 NUM_LED#_3 OUT IN IN OUT OUT OUT OUT OUT 79 114 TP30 6 109 TP30 ACPRESENT EC_PWRSW# R300 GPIO52/PSDAT3/RDY# 27 GPIO16 GPIO50/PSCLK3/TDO 25 GPIO24 GPIO27/PSDAT2 11 GPIO30/F_WP# GPIO26/PSCLK2 10 USB_OC#_2 GPIO34/CIRRXL GPIO35/PSDAT1 71 IM_DAT_5 15 GPIO36 GPIO37/PSCLK1 72 IM_CLK_5 TP30 80 GPIO41/F_WP# 26 GPIO51/N2TCK WL_OLED# USB_OC#_1 123 1.CHARGE 31D4 31A5 32A8 32A8 19C7 EC_SMB1_CLK GPIO22/SDA1/N2TMS EC_MUTE# 73 GPIO70 69 EC_SMB1_DATA WOL_AUX_ON# 74 GPIO71 GPIO73/SCL2 67 EC_SMB2_CLK GPIO72 GPIO74/SDA2 68 1 TP317 OUT OUT OUT OUT 75 21C8 47A6 21C7 47A6 21C7 OUT OUT GPIO23/SCL3A 119 AOAC_ON# 33_5%_2 21C8 OUT IN EC_SPI_SI 33_5%_2 R341 EC_SPI_SO R340 1 1 112 GP(I)O84/IOX_SCLK/XORTR# GPIO53/SDA4A 28 LID_SW#_3 EC_CTL2 110 GPO82/IOX_LDSH/TEST# GPIO42/SCL3B/TCK 17 TP30 TP326 1 GPIO06/IOX_DOUT GPIO43/SDA3B/TMS 20 TP30 TP303 1 SLP_S5#_3R GPIO44/SCL4B/TDI 21 TP30 TP304 1 H_PROCHOT_EC 23 TP30 TP305 1 SB_USB_2 1 91 GPIO81/F_WP# 90 F_CS0# 2 EC_SPI_CLK_R 92 F_SCK 2 EC_SPI_SI_R 86 F_SDI_F_SDIO1 2 EC_SPI_SO_R 87 F_SDIO_F_SDIO0 44 VCORF 47A6 21D6 21C6 47A6 21C7 C 2 2 1 47K_5%_2 1 47K_5%_2 5D3 5D3 37C6 56D8 21D3 5A7 37C3 56C8 21D3 5A7 27B2 21D2 21D3 21D3 47B7 47B8 21D3 27C2 21D3 27B2 EC_SMB1_CLK EC_SMB1_DATA EC_SMB2_CLK EC_SMB2_DATA AOAC_ON# WLON# BI BI BI BI BI BI R322 R321 R317 R316 2 R334 2 R335 2 1 2 1 3.3K_5%_2 2 1 1.8K_5%_2 2 1 1.8K_5%_2 3.3K_5%_2 D 1 1.8K_5%_2 1 1.8K_5%_2 18C4 14D2 IN OUT OUT 49B3 21B1 30B6 21D3 OUT 49B7 49C2 82 EC_PW_ON# GPIO77/SPI_DI 84 SB_USB_1 GPIO76/SPI_DO 83 EC_CTL1 15D4 14D8 R333 32C3 32A8 33D8 10K_5%_2 32A8 1 OUT OUT OUT AGND GND6 GND5 GND4 GND3 GND2 GND1 R336 10K_5%_2_DY 2 89 5 2 1 1 C 2 SO_SIO1 3 WP#_ACC 4 GND VCC AGND_KBC 8 R319 3.3K_5%_2_DY 2 HOLD# 7 1 SCLK 6 EC_SPI_CLK 5 EC_SPI_SI SI_SIO0 IN IN 21C7 21D6 47A6 21C6 21C7 47A6 41D6 11B7 OUT CPU_PROCHOT# 3 MXIC_MX25L3206EM2I_12G_SOP_8P_DY 0.1UF_16V_2_DY CS# 2 1 1 EC_SPI_SO 2 EC_SPI_CS1# C318 IN OUT R311 10K_5%_2_DY U302 21C6 R308 P3V3AL R315 47A6 IM_DAT_5 IM_CLK_5 BI BI POWERPAD1X1M P3V3AL 47A6 21C8 20A8 PAD319 2 MXIC_MX25L3206EM2I_12G_SOP_8P 1 20A8 21D3 103 21C7 116 IN IN 78 EC_SPI_SI 21D3 WINB_NPCE885LA0DX_LQFP_128P 1UF_6.3V_2 45 EC_SPI_CLK 5 21D2 RSMRST# 18 6 P5V0S 56C8 27C2 21D2 EC_ILIM_SEL 1 SCLK SI_SIO0 21D2 FLASH_OVERRIDE TP30 49C2 2 GND 7 1 R314 23.3K_5%_2 5D3 WLON# 93 49B7 56D8 24 C310 8 21D2 120 EC_SPI_CS0# EC_SPI_CLK R342 1 BI BI BI BI BI BI OUT IN 5D3 GPIO31/SDA3A 0.1UF_16V_2 WP#_ACC 4 52C2 11A8 21D2 GPIO47/SCL4A PWR_WLED# 21D1 30A3 20A8 20A8 GPIO20/TA2/IOX_DIN_DIO 1 3 VCC HOLD# 2 SO_SIO1 C309 CS# 2 52C2 20A4 OUT OUT OUT IN 117 U300 1 OUT OUT RSMRST# EC_SMB2_DATA P3V3AL EC_SPI_SO 52D6 USB30_PWR_EN 10K_5%_2 EC_SPI_CS0# 49B3 2 P3V3AL IN OUT 47C2 49A5 P3V3AL 70 33_5%_2 21C6 47C3 27B7 1 47A6 47A6 21D6 47C3 27C3 BI BI GPIO17/SCL1/N2TCK GPIO75/SPI_SCK 47A6 21C8 47C3 27C3 TP325 1 GPIO67/N2TMS GPIO46/SDA4B/CIRRXM/TRST# 47A6 47C3 27C3 PWR_SWIN#_3 TP306 EN_PVCORE 14 TP318 2 47C3 27C3 1 TP30 1 TP307 LOW_BAT#_3 GPIO02 TP30 3.CEC 1 51C7 27C3 P3V3AL 2 EC_SMB3 2.GPU THERMAL R313 OUT E 57A6 10K_5%_2 20B7 1.BATTERY IN OUT TP313 91 GPIO65/SMI# 10K_5%_2 PCI_3S_CLKRUN# 8 51A8 1 LAD3/GPIOF4 GPIO92/AD2 28C3 27C7 51A7 10K_5%_2 GPIO91/AD1 99 27C3 R326 LFRAME#/GPIOF6 98 IN BI BI BI BI BI BI BI OUT 1 GPIO90/AD0 1 TP30 TP310 BATT_IN LPC_3S_FRAME# 2 21E6 IN CLK_KBPCI 3 10K_5%_2 5D3 HW_I_ADC EC_SMB1 2 R312 5B7 21E8 BUF_PLT_RST# 7 LRESET#/GPIOF7 2 21E8 BATT_IN OUT VREF 97 HW_I_ADC R303 21E6 P3V3S LCLK/GPIOF5 5B8 IN U301 P3V3AL_EC_VREF104 AGND_KBC 5B7 R323 4.7K_5%_2 VCC4 R332 10K_5%_2 34B5 21E6 P3V3S VCC3 10K_5%_2_DY 100K_5%_2 1 C305 2 10UF_6.3V_5_DY 1 C314 2 R345 2 E R344 19 PM: 10K 2 P3V3AL_EC P3V3AL_EC 2 L300 FBM_11_160808_121T P3V3S 1 GM: 100K 1 P3V3AL_R 2 1 PCH_LCM_BKLTEN 21E6 VCC2 IN 50D7 P3V3AL_EC OUT 0_5%_1 R302 P3V3AL LCM_BKLTEN 2 VCC1 VGA_LCM_BKLTEN 1 IN 1 56D6 U301 14A6 21B6 10A5 IN IN FAN_TACH1 1 31 GPIO56/TA1 KBSOUT0/GPOB0/JENK# 53 TP30 63 GPIO14/TB1 KBSOUT1/GPIOB1/TCK 52 64 GPIO01/TB2 KBSOUT2/GPIOB2/TMS 51 32 GPIO15/A_PWM SA_PG C311 680PF_50V_2 49B7 49A6 2 19A7 19A7 40C6 B 20C7 19D7 OUT OUT OUT OUT OUT OUT TP320 PCH_PWROK 1 118 22B5 21F4 IN OUT IN 41D5 BI H_PECI 49 GPIO21/B_PWM KBSOUT5/GPIOB5/TDO 48 62 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# 47 DCIN_WLED# 65 GPIO32/D_PWM KBSOUT7/GPIOB7 43 1 22 GPIO45/E_PWM KBSOUT8/GPIOC0 42 TP30 81 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# 41 CAPS_LED#_3 66 GPIO33/H_PWM KBSOUT10_P80_CLK/GPIOC2 40 PWR_OLED# 16 KBSOUT11_P80_DAT/GPIOC3 39 TP321 FAN1_PWM TP30 GPIO40/F_PWM TP322 1 111 GP(I)O83/SOUT_CR/TRIST# TP323 TP30 1 113 GPIO87/CIRRXM/SIN_CR EC_32KHZ 77 LAN_RST# 30 85 VCC_POR# 1 2 EC_PECI 13 12 43_5%_2 P1V05S KBSOUT12/GPIO64 38 KBSOUT13/GPIO63 37 KBSOUT14/GPIO62 36 35 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 34 GPIO57/KBSOUT17 33 0 G 1 H_PROCHOT_EC 1 2 3 SSM3K7002BFU 4 IN 21D3 R324 100K_5%_2 5 6 7 8 9 10 B 11 12 13 14 15 16 17 GPIO00/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO VCC_POR# R339 52C2 50 BAT_OLED# TP30 49B3 KBSOUT3/GPIOB3/TDI KBSOUT4/GPOB4/JEN0# SCAN_OUT<0> SCAN_OUT<1> SCAN_OUT<2> SCAN_OUT<3> SCAN_OUT<4> SCAN_OUT<5> SCAN_OUT<6> SCAN_OUT<7> SCAN_OUT<8> SCAN_OUT<9> SCAN_OUT<10> SCAN_OUT<11> SCAN_OUT<12> SCAN_OUT<13> SCAN_OUT<14> SCAN_OUT<15> SCAN_OUT<16> SCAN_OUT<17> 1 40C8 40C8 2 21B6 S 1 IN 20D6 2 TP319 FAN_TACH1 OUT D Q300 SCAN_OUT<17..0> PECI VTT KBSIN0/GPIOA0/N2TCK 54 KBSIN1/GPIOA1/N2TMS 55 KBSIN2/GPIOA2 56 KBSIN3/GPIOA3 57 KBSIN4/GPIOA4 58 KBSIN5/GPIOA5 59 KBSIN6/GPIOA6 60 KBSIN7/GPIOA7 61 SCAN_IN<0> SCAN_IN<1> SCAN_IN<2> SCAN_IN<3> SCAN_IN<4> SCAN_IN<5> SCAN_IN<6> SCAN_IN<7> 0 1 SCAN_IN<7..0> 20C6 IN 20D3 2 3 4 5 6 7 WINB_NPCE885LA0DX_LQFP_128P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 21 1 REV X01 of 68 8 7 6 4 5 3 2 1 REFERENCE 400~499(LAN) Q400 P3V3A_LAN D 1 1 C425 0.1UF_16V_2 1 C405 2 C424 2 2 1 1 0.1UF_16V_2 C402 2 1UF_10V_2_DY 2 100K_5%_2 10UF_6.3V_5_DY R400 1 C404 1 1 2 G C401 G POWERPAD_2_0610 2 2 0.047UF_16V_2 WOL_AUX_ON# 1 2 C403 CSC0402_DY 2 C400 1 S IN D 21D6 1 1UF_6.3V_2 D 1 S PAVDDVCO_LAN PAD400 DIODES_DMP2305U_SOT23_3P 2 P3V3A 4.7UF_6.3V_3 D R402 0_5%_3 1 C423 PVLX_LAN 0.1UF_16V_2 2 C FOR LDO MODE R403 2 1 10K_5%_2 R404 2 7 23B7 23C6 23B7 23B7 23B7 23B7 31 32 34 33 AVDDL REFCLK_N REFCLK_P SMCLK XTLO XTLI 9 AVDDH_REG PPS LED_2 AVDDH RBIAS 29 PCIE_LAN_RX_C_DP PCIE_LAN_RX_C_DN 1 2 C422 1 2 0.1UF_16V_2 0.1UF_16V_2 PCIE_LAN_RX_DP PCIE_LAN_RX_DN OUT OUT 48D8 48D8 24 23 22 21 C420 B 0.1UF_16V_2 ATHEROS_AR8161_AL3A_R_QFN_40P C419 1 1 C417 0.1UF_16V_2 2 C416 22B5 2 22B5 1 2 0.1UF_16V_2 2 2 1 C421 P3V3A_LAN 0.1UF_16V_2 X400 1 48C7 25 C418 OUT OUT 48C7 PAVDDH_LAN 26 1UF_10V_2_DY LAN_X2 48D8 27 PAVDDL_LAN LAN_X1 48D8 28 2 AVDDL TRXP2 30 TRXP3 20 19 18 TRXN1 15 AVDDL TRXN0 TRXP1 14 LAN_TRD0_DP LAN_TRD0_DN LAN_TRD1_DP LAN_TRD1_DN LAN_TRD2_DP LAN_TRD2_DN LAN_TRD3_DP LAN_TRD3_DN TRXN2 TRXN3 13 BI BI BI BI BI BI BI BI AVDDL SMDATA 2.37K_1%_2 23B7 23C6 35 36 37 38 TESTMODE 8 10 TX_N NC AVDD33 2 RX_P AVDDL_REG RX_N ISOLATN 6 DVDDL_REG 5 LED_0 CLKREQN LED_1 4 TX_P 1 23B7 23C6 R405 WAKEN TRXP0 0.1UF_16V_2 23B7 23C6 1 VDD33 PERSTN 3 17 IN IN 1 2 C415 1UF_6.3V_2 2 C414 1 22A5 LAN_X1 LAN_X2 1 2 16 1 PAVDDH_LAN C413 22A5 2 RSC_0603_DY 1UF_6.3V_2 C412 1 2 2 1 2 C408 1 C407 1000PF_50V_2_DY FOR SW MODE 0.1UF_16V_2_DY 2 B 2 1 C406 LQM21PN2R2MC0D_DY 10UF_6.3V_5_DY 1 1 R406 2 LAN_RST# PCIE_WAKE# 11 PDVDDL_LAN IN OUT LX GND 2 PAVDDL_LAN L400 1 30K_5%_2 0.1UF_16V_2 PVLX_LAN 49B3 49A5 27C7 31C6 R401 IN IN IN IN U400 P3V3S 21B6 39 P3V3A_LAN 40 41 10K_5%_2_DY CLKREQ_LAN# OUT 48C7 12 48D7 PCIE_LAN_TX_DN PCIE_LAN_TX_DP CLK_PCIE_LAN_DP CLK_PCIE_LAN_DN 1 1 48D8 1 C426 2 0.1UF_16V_2 1UF_6.3V_2 1 1 C427 2 C 2 PAVDDL_LAN PDVDDL_LAN 33PF_50V_2 C410 2 2 A 33PF_50V_2 C409 25MHZ A C417:8161 STUFF 8162 OPEN INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 22 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 400~499(LAN) 23C3 23B3 23C3 23B3 23C3 23B3 23C2 D 23B3 23C2 23B3 23C3 23B3 23C2 23B3 23C2 23B3 LAN_TD_DP LAN_TD_DN LAN_RD_DP LAN_C_DP LAN_C_DN LAN_RD_DN LAN_D_DP LAN_D_DN IN IN IN IN IN IN IN IN JACK470 1 TX+ 2 TX- 3 RX+ G G1 4 P4 G G2 5 P5 6 RX- 7 P7 8 P8 D SANTA_13045_8P U471 RCT RCT 10 8 RD- RX- 9 6 RD+ RX+ 11 4 NC 0.1UF_16V_2 NC NC 12 NC 13 BOTH_TS21C_HF_SOP_16P 2 C479 2 2 C478 0.1UF_16V_2 5 LAN_TD_DN LAN_TD_DP 1 16 R475 IN IN TX+ LAN_RD_DN LAN_RD_DP 75_5%_3 22B5 14 TD+ 7 2 23B7 LAN_TRD1_DN LAN_TRD1_DP 15 TX- 1 22B5 TCT TD- 1 R474 23B7 TCT 3 75_5%_3 C 22B5 LAN_TRD0_DN LAN_TRD0_DP IN IN 1 23B7 22B5 1 23B7 2 OUT OUT 23B3 23D5 23B3 23D5 OUT OUT 23B3 23D5 2 23B3 23D5 R476 2 2 R477 6 TD2- MX2- 19 5 TD2+ MX2+ 20 7 TCT3 MCT3 18 9 TD3- MX3- 16 8 TD3+ MX3+ 17 TCT4 MCT4 15 12 TD4- MX4- 13 11 TD4+ MX4+ 14 1 1UF_6.3V_2 C474 2 0.1UF_16V_2 1 C473 2 CSC0402_DY 1 2 C483 1 0.1UF_16V_2 C472 2 1 CSC0402_DY 2 C482 1 0.1UF_16V_2 C471 2 CSC0402_DY 1 C481 2 0.1UF_16V_2 1 C470 2 1 C480 2 CSC0402_DY BOTH_GST5009_RA_SOP_24P LAN_RD_DN LAN_RD_DP LAN_C_DN LAN_C_DP LAN_D_DN LAN_D_DP 1 21 R473 IN IN OUT 23B3 23D5 LAN_D_DN R479 OUT 23B3 23D5 1 LAN_D_DP OUT 23B3 23D5 OUT OUT 23C3 23D5 23C3 23D5 OUT OUT 23C3 23D5 23C3 23D5 OUT OUT 23C2 23D5 23C2 23D5 OUT OUT 23C2 23D5 23C2 23D5 B 75_5%_3 MCT2 2 TCT2 1 4 LAN_TD_DN LAN_TD_DP R472 23 75_5%_3 MX1+ 2 TD1+ 10 LAN_TRD3_DN LAN_TRD3_DP LAN_C_DP 1 22B5 22 2 1 22B5 B IN IN 24 MX1- R471 22B5 LAN_TRD2_DN LAN_TRD2_DP MCT1 TD1- 75_5%_3 22B5 LAN_TRD1_DN LAN_TRD1_DP IN IN TCT1 3 2 22B5 1 1 22B5 23C6 1 1 2 R470 23C6 R478 RSC_0402_DY 75_5%_3 22B5 23D5 RSC_0603_DY 2 23C6 LAN_TRD0_DN LAN_TRD0_DP IN IN 23B3 RSC_0402_DY U470 22B5 OUT RSC_0603_DY PAVDDL_LAN 23C6 C LAN_C_DN 1 C475 1 2 CSC0402_DY C477 100PF_50V_2 2 C476 1 2 1000PF_2000V_6 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 23 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 500~549(AUDIO CODEC) P5V0S 1 C519 1 1 1 CLOSE TO PIN27 P5V0S_AUDIO_AVDD C513 R515 1 C512 C503 0_5%_3 2 2 10UF_6.3V_3 BLM18PG121SN1(6014B0041601_0603) 2 2 2.2UF_6.3V_3 AGND_AUDIO 2 0.1UF_16V_2 2.2UF_6.3V_3 AGND_AUDIO BLM18PG121SN1(6014B0041601_0603) MIC_REF_L 2 MIC_REF_R C OUT 25B8 OUT 25B3 OUT 25A3 OUT 25D3 OUT 25D3 D P5V0S_AUDIO_AVDD PVDD1 SPK_OUT_L_P R512 1 2 0_5%_3 40 SPK-L+ SPK_OUT_L_N R511 1 2 0_5%_3 41 SPK-L- 42 PVSS1 ANALOG DIGITAL LINE1-R 24 LINE1-L 23 MIC1-R 22 MIC_R MIC1-L 21 MIC_L MONO-OUT 20 JDREF 19 1 18 20K_1%_2 BI 25C2 BI 25C2 4.7UF_6.3V_3 C504 2 C501 2 AVDD1 AVSS1 VREF LDO-CAP HP-OUT-L HP-OUT-R MIC2-VREFO AVDD2 39 MIC1-VREFO-R 38 MIC1-VREFO-L AVSS2 CPVEE CBP 37 0.1UF_16V_2 1 1 25 27 26 28 29 30 31 32 33 34 35 36 0.1UF_16V_2 U500 AGND_AUDIO 25B8 OUT 1 2 C500 4.7UF_6.3V_3 1 0.1UF_16V_2 C507 2 4.7UF_6.3V_3 1 2 C505 0.1UF_16V_2_DY 1 C506 2 10UF_6.3V_3_DY C532 1 0_5%_3 2 2 1 1 2.2UF_6.3V_3 P5V0S_PVDD CBN R516 2 HP_L C502 C536 P5V0S HP_R 1 P5V0S_AUDIO_AVDD D AGND_AUDIO C R514 RESERVE FOR EMI 43 25B8 OUT SPK_OUT_R_P PVSS2 Sense-B R510 1 2 0_5%_3 44 SPK-R- MIC2-R 17 R509 1 2 0_5%_3 45 SPK-R+ MIC2-L 16 46 PVDD2 LINE2-R 15 47 EAPD LINE2-L 14 48 SPDIFO Sense A 13 2 AGND_AUDIO OUT CLOSE TO PIN13 R500 1 2 MICS IN 25C5 IN 25B2 49 PCBEEP SYNC DVDD-IO RESET# GND SDATA-IN DVSS2 BIT-CLK SDATA-OUT 20K_1%_2 PD# GPIO1/DMIC-CLK GPIO0/DMIC-DATA DVDD1 0.1UF_16V_2 1 C531 2 4.7UF_6.3V_3 2 C529 1 25B8 SPK_OUT_R_N (THERMAL PAD 4X4 VIAS) 1 R501 2 HPS 39.2K_1%_2 REA_ALC269Q_VB6_CGT_QFN_48P B 2 1 12 10 1 1 11 9 8 7 6 5 4 3 2 1 C514 2 B C520 P3V3S R507 PCSPKR_PCH_3 2 47K_1%_2 C516 2 1 C509 1 R506 2 4.7K_1%_2 HDA_3S_RST# HDA_3S_SYNC 1 HDA_R_SDIN0 1000PF_50V_2 1 R502 2 HDA_3S_SDIN0 2 HDA_3S_BITCLK IN 47C7 IN 47C7 IN 47B7 IN 47C7 IN 47B7 IN 21D6 22_5%_2 C517 2 1 100PF_50V_2 0.1UF_16V_2 2 1000PF_50V_2 2 1 1UF_6.3V_2 1 C508 C515 47C8 C521 2 0.1UF_16V_2 1000PF_50V_2 2 IN HDA_R_BITCLK 1 1 R503 0_5%_2 1000PF_50V_2 TIED UNDER OR NEAR CODEC 34B3 BI HDA_3S_SDOUT MIC_IN_DATA EC_MUTE# R505 PAD500 AGND_AUDIO 1 1 2 34B3 2 BI MIC_IN_CLK 1 2 MIC_IN_CLK_R P3V3A 100_5%_2 POWERPAD1X1M 1UF_6.3V_2 1 2 C522 1 2 0.1UF_16V_2 C510 C518 2 AGND_AUDIO 22PF_50V_2_DY A 1 A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 24 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERCE 600~649(JACK/MIC/SPEAKER) AUDIO JACKS D MIC_REF_L 2 MICPHONE R605 MICS 1 2 1 11 G1 TP30 1 1 2 1 2 1 1 21K_5%_2 2 MIC_R 2 MIC_L TP605 1 TP30 TP604 TP30 R607 1 2 R603 1K_5%_2 BI 24C2 BI 24C2 2.2UF_6.3V_3 C607 0_5%_3 G2 TP606 SINGA_2SJ_T351_019_6P RESERVE FOR EMI C600 C601 CSC0402_DY 2 CSC0402_DY C 2 AGND_AUDIO C 2.2UF_6.3V_3 C606 R602 24B2 D 1 6 OUT 24D3 2.2K_5%_2 1 3 0_5%_3 IN R604 2.2K_5%_2 R606 5 TP607 14 24D3 1 TP30 JACK600 IN 2 MIC_REF_R RESERVE FOR EMI AGND_AUDIO D600 2 3 B B 1 PHP_PESD5V2S2UT_SOT23_3P_DY INTERNAL SPEAKERS NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH 3 3 2 2 1 1 JACK601 G2 G1 R601 G2 75_5%_2 G1 24D3 24D3 IN IN HP_R 1 HP_L 1 2 OUT 1 TP601 1 5 4 3 6 TP600 1 2 2 1TP30 R608 TP602 0_5%_3 1 G1 G2 SINGA_2SJ_T351_019_6P 1 C611 2 1 24B2 2 470PF_50V_2_DY C609 2 1 470PF_50V_2_DY C608 1 TP30 R600 75_5%_2 2 1 470PF_50V_2_DY C605 2 1 470PF_50V_2_DY C604 2 1 470PF_50V_2_DY C603 2 1 470PF_50V_2_DY C602 0_5%_3 2 TP603 1TP30 HPS TP30 ACES_50224_0040N_001_4P 2 R609 A 470PF_50V_2_DY 24C7 4 1 24C7 4 C610 24C7 CN600 SPK_OUT_L_P SPK_OUT_L_N SPK_OUT_R_N SPK_OUT_R_P 2 IN IN IN IN 470PF_50V_2_DY 24C7 HEADPHONE AGND_AUDIO AGND_AUDIO A RESERVE FOR EMI RESERVE FOR EMI AGND_AUDIO INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 25 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERNCE 900~999(CARDREADER) D D SD_CMD SD_R_CLK 1 R901 BI SD_CLK 2 BI 26B3 26B3 0_5%_2 RESERVE FOR EMI SD_CD# 26B3 13 14 15 17 16 18 BI P3V3S_CR C C 1 1 SP6 SP7 SP8 SP9 GPIO0 SP10 U900 C905 SP11 SP5 C906 12 2.2UF_6.3V_3 BI 26B3 BI SD_D320 SP12 SP4 11 SD_D0 SD_D221 SP13 SP3 10 SD_D1 22 SP14 SP2 9 23 XD_D7 SP1 8 BI 26B3 BI 26B3 0.1UF_16V_2 2 26B3 2 19 CN900 26C7 26D5 24 BI 7 26C5 26C5 26C5 26C7 REA_RTS5129_QFN_24P 2 26C5 6 1 5 4 3 2 1 26B5 B SD_D3 SD_CMD 26B3 SDREG 3V3_IN 1UF_6.3V_2 DP TML DM 25 RREF C901 CARD_3V3 XD_CD# 1 V18 SD_WP BI BI BI BI BI BI BI BI SD_CLK SD_D0 SD_D1 SD_D2 SD_CD# SD_WP C904 1 CD-DAT3 2 CMD 3 VSS1 4 VDD 5 CLK 6 VSS2 7 DAT0 8 DAT1 9 DAT2 10 CARD_DETECT 11 WRIT_PROTECT G1 G1 G2 G2 B TAI_PSDAT0_09GLBS1ZZ4H1_11P 1UF_6.3V_2 R900 2 CARD_REF 2 1 6.2K_1%_2 P3V3S_CR BI 51B2 BI USB_CR_DN 1 51B2 USB_CR_DP C902 2 0.1UF_16V_2 P3V3S PAD900 A 1 2 2 P3V3S_CARD A 1 POWERPAD_2_0610 1 1 C900 C903 4.7UF_6.3V_3 2 2 0.1UF_16V_2 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 26 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 1300~1349(WLAN) D D SUPPORT AOAC:OPEN SUPPORT AOAC:STUFF P3V3S 1 P3V3S P3V3A P1V5S R1304 1 C1304 S 4 G 3 1 5 6 0.1UF_16V_2 10UF_6.3V_3 D 2 2 1 1 C1302 Q1300 0_5%_5 C1306 10UF_6.3V_3 2 CSC0402_DY 2 2 C1301 CSC0402_DY 2 C1305 0.1UF_16V_2 C1307 AM3423P_DY 1 1 1 2 2 PMOS_4D1S AOAC_ON# 22B5 52B6 27B7 48D7 48B7 48B7 48B7 57A6 51A8 28C3 27C3 21E3 51A7 48D8 48D8 48D8 48D8 BI BI IN IN IN IN IN OUT OUT IN IN PCIE_WAKE# BTIFON# 1 1 R1301 2 0_5%_2 CLKREQ_WLAN# WAKE# 3 CH_DATA 5 CH_CLK 7 CLKREQ# 9 GND LPC_AD3 10 LPC_3S_AD<3> 47C2 21E3 BI IN GND 4 1.5V 6 LPC_FRAME# 8 LPC_3S_FRAME# 11 REFCLK- LPC_AD2 12 LPC_3S_AD<2> CLK_PCIE_WLAN_DP 13 REFCLK+ LPC_AD1 14 LPC_3S_AD<1> LPC_AD0 16 LPC_3S_AD<0> 15 GND BUF_PLT_RST# 17 LPC_DEBUG_RST# CLK_PCI_DEBUG 19 LPC_PCI_CLK 21 GND PCIE_WLAN_RX_DN 23 PERN0 PCIE_WLAN_RX_DP 25 PERP0 27 GND GND 18 PERST# 22 BUF_PLT_RST# 24 +3.3VAUX GND SMB_CLK 30 PCH_3A_ALERT_CLK SMB_DATA 32 PCH_3A_ALERT_DAT GND PETN0 PCIE_WLAN_TX_DP 33 PETP0 35 GND USB_D- 36 USB_WLAN_DN 37 Reserved USB_D+ 38 USB_WLAN_DP 39 Reserved 41 Reserved PCI_3S_SERIRQ 1 R1302 R1303 2 2 0_5%_2 0_5%_2_DY GND GND 40 LED_WWAN# 42 Reserved LED_WLAN# 45 +V3AL LED_WPAN# 46 47 PWR_LED# 1.5V 48 49 NUM_LED# 51 CAPS_LED# G 47C3 47C3 21E3 47C3 21E3 47C3 21E3 47C3 21E3 28C3 57A6 27C7 51A8 GND Q1301 G 34 44 G1 21E3 21E3 28 1.5V 29 1 IN 26 31 BTIFON# IN IN IN IN IN 20 W_DISABLE# PCIE_WLAN_TX_DN B 27C7 2 3.3V CLK_PCIE_WLAN_DN 43 52B6 C 1 3 48D8 31C6 D 49A5 21D2 21D3 IN CN1300 BI BI 48D2 48D3 48D2 48D3 BI BI 51B2 1 WLON# IN 21D2 21D3 S 49B3 2 0_5%_2 SSM3K7002BFU 2 R1300 C 51B2 B 50 52 3.3V G G2 BELLW_80003_4021_52P A A MINI CARD 1(WLAN) INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 27 REV X01 68 of 1 7 6 4 5 3 REFERENCE 1400~1499(3G) 2 1 22UF_6.3V_5 1 C1412 2 0.1UF_16V_2 C1411 2 2 0.1UF_16V_2 C1410 1 P1V5S 1 8 P3V3S D 1 1 1 D C1402 C1401 C1400 CN1400 47B3 47B3 C BI BI SATA_MINICARD_RX_DP SATA_MINICARD_RX_DN SATA_MINICARD_TX_DN SATA_MINICARD_TX_DP C1405 1 0.01UF_50V_2 2 0.01UF_50V_2 SATA_MINICARD_C_RX_DP SATA_MINICARD_C_RX_DN 2 0.01UF_50V_2 0.01UF_50V_2 C1408 1 2 SATA_MINICARD_C_TX_DN SATA_MINICARD_C_TX_DP 2 C1406 C1407 1 1 1 TP24 TP1402 LPC_FRAME# 8 LPC_AD3 10 REFCLK- LPC_AD2 12 REFCLK+ LPC_AD1 14 GND LPC_AD0 16 11 13 15 17 LPC_DEBUG_RST# 19 LPC_PCI_CLK 21 GND 23 PERN0 25 PERP0 27 GND 29 GND 31 PETN0 33 PETP0 35 GND USB_D- 36 37 Reserved USB_D+ 38 GND UIM_PWR UIM_DATA UIM_CLK UIM_RST OUT BI BI OUT 28A4 PERST# 28A4 28A4 18 22 3G_OFF# BUF_PLT_RST# IN 24 +3.3VAUX GND 26 21E3 27C7 57A6 28 1.5V SMB_CLK 30 SMB_DATA 32 GND 34 39 Reserved 41 Reserved LED_WWAN# 42 43 Reserved LED_WLAN# 44 45 +V3AL LED_WPAN# 46 47 PWR_LED# 1.5V 48 49 NUM_LED# 51 CAPS_LED# G1 G GND GND 28B6 28A6 20 W_DISABLE# 22UF_6.3V_5 2 GND 6 0.1UF_16V_2 0.1UF_16V_2 4 2 CLKREQ# 9 GND 1.5V 2 7 3.3V TP24 TP24 27C3 51A8 3 BI BI CH_CLK 1 1 TP1400 Q1400 D 47B3 CH_DATA 5 TP1401 G USB_3G_DN USB_3G_DP BI BI 40 1 3G_ON# 51B2 51B2 IN 52D6 C S 47B3 WAKE# 3 2 SSM3K7002BFU 2 CLOSE TO CONN SIDE 1 50 52 3.3V G G2 BELLW_80003_4021_52P B B P3V3S U1400 28D3 28A4 IN UIM_PWR 1 VIO 2 GND 3 VIO VIO VBUS VIO 6 5 4 NXP_IP4223CZ6_SOT457_6P_DY CN1401 28D3 BI UIM_DATA P5 GND VCC P1 P6 VPP RST P2 P7 I_O CLK P3 G2 G G UIM_PWR UIM_RST UIM_CLK IN IN BI 28B6 28D3 28C3 28C3 G1 1 A 4.7UF_6.3V_3 C1404 2 2 C1403 A 0.1UF_16V_2 1 TAI_PMPAT5_06GLBS7NI4H1_6P INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 28 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 1700~1749(HDD) REFERENCE 1750~1799(ODD) SATA HDD D 1 47C3 IN IN 47C3 47C3 OUT OUT 47C3 SATA_HDD_TX_DP SATA_HDD_TX_DN C1704 SATA_HDD_RX_DN SATA_HDD_RX_DP C1700 C1705 C1701 1 2 0.01UF_50V_2 1 2 0.01UF_50V_2 1 2 0.01UF_50V_2 1 2 0.01UF_50V_2 SATA_HDD_TX_C_DP SATA_HDD_TX_C_DN SATA_HDD_RX_C_DN SATA_HDD_RX_C_DP PLACE CLOSE TO CONNECTOR(<100MILS) P5V0S 1 0.1UF_16V_2 2 C1702 1 22UF_6.3V_5 C1703 2 22UF_6.3V_5 2 C1706 1 40MIL CN1700 GND 2 A+ 3 A- 4 GND 5 B- 6 B+ 7 GND 8 V3.3 9 V3.3 D 10 V3.3 11 GND 12 GND 13 GND 14 V5 15 V5 16 V5 17 GND 18 RESERVED 19 GND 20 V12 21 V12 G1 G1 22 V12 G2 G2 SANTA_194911_1_22P C C 1 1 P5V0S Q1751 3 2 100K_5%_2_DY 1 R1754 0_5%_6 TPC6111_DY 2 2 D 10K_5%_2_DY 2 2 1 PMOS_4D1S R1751 R1750 S CSC0402_DY G 1 3 C1754 R1752 1M_5%_2_DY 4 P3V3S 52D2 IN 1 2 B G C1758 S B 1 5 D 6 Q1750 SATA_ODD_PWREN 2 1 1 0.1UF_16V_2 2 C1755 1 22UF_6.3V_5 C1756 2 2 C1757 CSC0402_DY 22UF_6.3V_5 1 2 SSM3K7002BFU_DY P6 51C7 52D7 51B6 52B6 A 47B3 47B3 47B3 47B3 OUT OUT IN IN SATA_ODD_RX_DP SATA_ODD_RX_DN SATA_ODD_TX_DN SATA_ODD_TX_DP C1750 1 C1753 2 C1751 1 1 2 C1752 1 OUT OUT SATA_ODD_DA# SATA_ODD_PRSNT# 0.01UF_50V_2 2 0.01UF_50V_2 SATA_ODD_RX_C_DP SATA_ODD_RX_C_DN 0.01UF_50V_2 2 0.01UF_50V_2 SATA_ODD_TX_C_DN SATA_ODD_TX_C_DP CN1750 GND P5 GND P4 MD P3 +5V P2 +5V P1 DP S7 GND S6 B+ S5 B- S4 GND S3 A- S2 A+ G G1 S1 GND G G2 SATA ODD A SYN_127382FR013G212ZR_13P PLACE CLOSE TO CONNECTOR(<100MILS) INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 29 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 2000~2099(USB) D D P5V0A_USB3 CN2002 66C6 51C2 66C6 51C2 BI BI USB_P2_DN USB_P2_DP 1 1 2 2 3 3 G1 G1 4 4 G2 G2 ACES_50224_0040N_001_4P C C P5V0A 2 2 P5V0A_USB_PW1 POWERPAD_2_0610 1 1 1 PAD2000 1 C2000 C2001 1UF_6.3V_2 2 2 22UF_6.3V_5_DY B B P5V0A_USB3 7 VIN VOUT 6 4 EN_EN# FLG# 5 RICH_RT9711APF_MSOP_8P R2000 C2003 C2002 22UF_6.3V_5 1 8 VOUT 1 VOUT VIN 3 0.1UF_16V_2 RSC_0402_DY 2 2 IN 1 21D3 GND 2 2 SB_USB_2 1 1 U2000 C2004 CSC0402_DY 1 2 P3V3AL R2001 2 10K_5%_2 USB_OC#_2 OUT 21D3 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 30 REV X01 68 of 1 8 7 6 4 5 3 REFERENCE 2400~2499(USB3.0) 2 P3V3A 1 P3V3_USB3 Q2403 DIODES_DMP2305U_SOT23_3P 1 C2471 2 10UF_6.3V_3 1 0.01UF_50V_2 2 C2470 1 0.01UF_50V_2 2 C2405 1 0.01UF_50V_2 C2404 2 0.01UF_50V_2 1 2 C2403 1 D 3 220K_5%_2 0.01UF_50V_2 2 C2402 1 0.1UF_16V_2 C2401 2 0.1UF_16V_2 1 C2400 2 2 CSC0402_DY 1 C2473 G G 1 2 2 1 2 C2425 0.1UF_16V_2 1 2 C2424 0.1UF_16V_2 1 0.1UF_16V_2 C2423 2 31A5 21D6 USB30_PWR_EN IN 1 Q2402 G SSM3K7002BFU S 2 C2422 0.01UF_50V_2 1 1 C2421 2 0.01UF_50V_2 1 0.01UF_50V_2 2 C2420 1 0.01UF_50V_2 C2419 2 0.01UF_50V_2 1 C2418 2 0.01UF_50V_2 1 C2417 2 D R2427 2 1 CSC0402_DY C2472 R2424 10K_5%_2 D S 1 S D P1V05_USB3 2 D 25 U2400 AVDD33 51A7 CLKREQ_USB3# 1 31B8 IN 48B7 49B3 10K_5%_2 49A5 44 U3RXDP2 40 USB2_IC_TX2_DP USB3_IC_RX2_DP U3RXDN2 41 USB3_IC_RX2_DN 27C7 PLT_RST# IN PCIE_WAKE# OUT CLKREQ_IC_USB3# IN 41C7 36B2 22B5 31B6 47 PERSTB 48 PEWAKEB 10 PECREQB USB3_SMI# 2 33C5 BI 33B5 33B5 1 C2416 1 C P3V3_USB3 OCI2B 17 R2415 1 OCI1B 19 R2416 1 PPON2 18 PPON1 20 2 10K_5%_2 2 10K_5%_2 31C6 51B6 IN 31C7 10K_5%_2 BI BI 0.01UF_50V_2 U2DP2 PERXN 33B5 2 PERXP 8 R4955 1 33C5 0.01UF_50V_2 7 C 2 R4754 BI BI 0.1UF_16V_2 C2415 USB3_IC_TX2_DN USB2_IC_TX2_DN 45 2 38 U2DM2 0.1UF_16V_2 U3TXDN2 PETXN 2 1 PETXP 5 33B5 2 4 BI C2414 USB3_IC_TX2_DP 0.1UF_16V_2 37 1 AVDD33 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD33 VDD33 U3TXDP2 C2408 2 PCIE_USB3_TX_DP PCIE_USB3_TX_DN IN IN 48D8 PECLKN 2 48D8 PCIE_USB3_RX_C_DP PCIE_USB3_RX_C_DN 2 1 C2410 P3V3_USB3 2 BLM21PG600SN1D_3A 0.1UF_16V_2 C2409 1 PCIE_USB3_RX_DP PCIE_USB3_RX_DN OUT OUT 48D8 PECLKP 2 48B7 48D8 1 L2400 1 1 CLK_PCIE_USB3_DP CLK_PCIE_USB3_DN IN IN P3V3_USB30_AVDD C2406 48B7 VDD33 VDD33 P3V3_USB3 10UF_6.3V_3 3 42 39 33 P3V3_USB30_AVDD 30 21 9 6 P1V05_USB3 43 34 22 12 P3V3_USB3 P3V3_USB3 51B6 OUT USB3_SMI# 46 SMIB 11 PONRSTB R2406 1 2 U3TXDP1 28 USB3_IC_TX1_DP U3TXDN1 29 USB3_IC_TX1_DN USB2_IC_TX1_DN BI 2 10K_5%_2 NC 31A6 31A8 1 31A6 31A8 1 3 D2400 USB3_SCLK USB3_CS# USB3_SI USB3_SO OUT OUT OUT IN 15 SPISCK 14 SPICSB 16 SPISI 13 SPISO U2DM1 36 U2DP1 35 U3RXDP1 31 USB2_IC_TX1_DP USB3_IC_RX1_DP U3RXDN1 32 USB3_IC_RX1_DN BI BI BI BI 32D7 32D7 32B8 32B8 32A8 32D7 DIODE-BAT54-TAP-PHP C2411 USB3_XT1 USB3_XT2 1UF_6.3V_2 X2400 XT1 23 XT2 27 IC(L) 32D7 R2400 C2413 B 1.6K_1%_2 24MHZ RREF 26 1 2 C2412 12PF_50V_2 12PF_50V_2 2 2 BI GND 1 2 1 2 1 B 24 49 RENESAS_UPD720202K8_BAA_A_QFN_48P 31C7 OUT CLKREQ_USB3# 1 R2405 2 CLKREQ_IC_USB3# IN 31C6 0_5%_2 48B7 P1V5 P5V0A P1V05_USB3 U2403 P3V3_USB3 31D4 IN R2481 VIN 8 EN 7 POK 6 VCNTL 5 C2480 2 VOUT 3 VOUT 4 TRACE WIDTH>20MILS1 VIN ANPEC_APL5930KAI_TRG_SOP_8P 1 1 0.1UF_16V_2 2 PAD2400 1 2 2 10K_1%_2 CS# USB3_SO 2 SO 3 WP# SCLK 6 USB3_SCLK 4 GND SI 5 USB3_SI VCC 8 NC 7 22UF_6.3V_5 1UF_6.3V_2 C2434 2 2 1 A POWERPAD1X1M 2 1 C2438 USB3_CS# R2422 1 C2435 C2433 22UF_6.3V_5 150PF_50V_2 2 2 OUT FB 2 2 R2423 IN 31B6 IN 31B6 31.6K_1%_2 INVENTEC 2 31B6 IN 1 1 U2480 31B6 GND 1 47K_5%_2 10K_5%_2 A 21D6 9 1 1 R2480 1 P3V3_USB3 USB30_PWR_EN TITLE MAC_MX25L5121EMC_20G_SOP_8P MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 31 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 2400~2499(USB3.0) 31B2 USB3.0 FROM CONTROLLLER BI BI 31B2 USB3.0 FROM PCH 51C6 31B2 D R2431 1 C2447 USB3_SSRX1_DN USB3_SSRX1_DP 2 0_5%_2 2 0_5%_2 R2432 1 R2433 1 USB3_IC_TX1_DN USB3_IC_TX1_DP BI BI 31B2 R2430 1 USB3_PCH_RX1_DN USB3_PCH_RX1_DP BI BI 51C6 USB3.0 FROM CONTROLLLER USB3_IC_RX1_DN USB3_IC_RX1_DP 2 1 USB3_SSTX1_DN USB3_SSTX1_DP 2 0.1UF_16V_2 2 0.1UF_16V_2 1 32C7 32C7 0_5%_2 0_5%_2 2 C2448 BI BI 32B7 BI BI 32B7 D 51C6 USB3.0 FROM PCH USB3_PCH_TX1_DN USB3_PCH_TX1_DP BI BI 51C6 C2440 1 2 0.1UF_16V_2 2 0.1UF_16V_2 1 C2441 P5V0A_USB1 USB3.0 1 P5V0A_USB1 + P5V0A CURRENT LIMIT 2.5A 2 100UF_6.3V 1 1 1 33D8 32A8 21C3 2 0_5%_2 2 0_5%_2 1 BI BI R2446 C2427 R2447 32B8 51C2 USB_P0_DN USB_P0_DP R2455 1 USB_P0_R_DN USB_P0_R_DP 2 1 2 R2454 1 2 4 3 0_5%_2 32D5 32D5 32B8 31B2 32A8 31B2 USB2_IC_TX1_DN1 USB2_IC_TX1_DP1 BI BI R2503 1 WCM_2012_900T 0_5%_2 2 0_5%_2 2 0_5%_2 32D5 32D5 USB_P0_L_DN USB_P0_L_DP USB3_SSRX1_DN USB3_SSRX1_DP BI BI USB3_SSTX1_DN USB3_SSTX1_DP BI BI 7 3 IN OUT 6 4 EN OC# 5 DD+ 4 PGND 5 SSRX- 6 SSRX+ G G1 7 GND G G2 8 SSTX- G G3 9 SSTX+ G G4 R2408 47UF_6.3V_5 1000PF_50V_2 C 10K_5%_2 USB_OC#_1 VBUS 3 P3V3AL GMT_G547E1P81U_MSOP_8P 2 2 8 OUT C2428 CN2401 2 R2504 OUT IN 2 0.1UF_16V_2 2 L2404 BI BI SB_USB_1 C2432 C2426 22UF_6.3V_5 51C2 32B8 IN GND 2 2 32A8 1 1 C USB_IC_DP USB_IC_DN 1 1 U2402 32A8 C2429 OUT 33C6 21D6 32A6 USB 3.0 CONNECTOR LOTES_AUSB0026_P001_9P B B 51C2 32C8 51C2 32C8 BI BI USB_P0_DN 1 USB_P0_DP 1 R2456 2 0_5%_2 2 0_5%_2 P5V0A R2457 BI 32B8 31B2 BI 21D6 USB2_IC_TX1_DN 1 32B8 31B2 USB2_IC_TX1_DP IN EC_ILIM_SEL C2442 2 1 U2401 8 CTL3 16 ILIM1 15 GND FAULT# P5V0A BI USB_OC#_1 OUT P3V3AL R2434 2 12 P5V0A_USB1 1 2 33C6 21D6 32C1 R2435 R2436 20K_5%_2 0_5%_2_DY A 2 10K_5%_2 100K_5%_2_DY BI 11 9 10 R2458 32C8 13 TI_TPS2540A_QFN_16P 1 32C8 14 OUT NC A 17 1 CTL2 PWPD ILIM0 2 7 IN CTL1 DM_IN EN DP_IN 5 6 ILIM_SEL 21D6 SB_USB_1 EC_CTL1 EC_CTL2 EC_CTL3 DM_OUT 21C3 IN IN IN IN DP_OUT 21C3 33D8 32C3 1 2 4 3 0.1UF_16V_2 USB_IC_DP USB_IC_DN INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 32 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 2400~2499(USB3.0) 1 P5V0A_USB2 + P5V0A CURRENT LIMIT 2.5A GND OUT 8 2 IN OUT 7 3 IN OUT 6 4 EN OC# 5 P5V0A_USB2 1 SB_USB_1 1 P3V3AL R2410 GMT_G547E1P81U_MSOP_8P 1 1 1 10K_5%_2 C2454 2 2 47UF_6.3V_5 USB_OC#_1 C2452 OUT C2453 C2451 21D6 32A6 32C1 0.1UF_16V_2 1000PF_50V_2 2 22UF_6.3V_5_DY 2 IN 1 21C3 32C3 32A8 100UF_6.3V 2 U2404 D USB 3.0 CONNECTOR C2449 2 D 31C2 USB2.0 FROM PCONTROLLER USB2_IC_TX2_DN USB2_IC_TX2_DP BI BI R2453 1 2 R2452 1 2 R2450 1 R2451 1 2 0_5%_2 2 0_5%_2 0_5%_2 0_5%_2 C 1 L2405 USB2.0 FROM PCH 51C2 USB_P1_DN USB_P1_DP BI BI USB_P1_R_DN USB_P1_R_DP 1 2 4 3 USB_P1_L_DN USB_P1_L_DP WCM_2012_900T 33B3 USB3_SSRX2_DN USB3_SSRX2_DP BI BI 33B3 33B2 USB3_SSTX2_DN USB3_SSTX2_DP BI BI 33B2 CN2402 C VBUS 2 D- 3 D+ 4 PGND 5 SSRX- 6 SSRX+ G G1 7 GND G G2 8 SSTX- G G3 9 SSTX+ G G4 LOTES_AUSB0026_P001_9P BI BI USB3.0 FROM CONTROLLLER USB3.0 FROM PCH 51C6 BI BI 51C6 B BI BI USB3.0 FROM CONTROLLLER USB3.0 FROM PCH 51C6 BI BI 51C6 USB3_IC_RX2_DN USB3_IC_RX2_DP USB3_PCH_RX2_DN USB3_PCH_RX2_DP R2437 1 R2438 1 2 0_5%_2 2 0_5%_2 R2439 1 R2440 1 2 2 USB3_SSRX2_DN USB3_SSRX2_DP BI BI 33C3 33C3 0_5%_2 0_5%_2 B USB3_IC_TX2_DN USB3_IC_TX2_DP USB3_PCH_TX2_DN USB3_PCH_TX2_DP C2443 1 C2444 2 0.1UF_16V_2 2 0.1UF_16V_2 1 1 C2445 C2446 1 USB3_SSTX2_DN USB3_SSTX2_DP BI BI 33C3 33C3 2 0.1UF_16V_2 2 0.1UF_16V_2 USB3.0 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 33 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFFERENCE 3000~3049(LCM) P3V3S S 1 1 2 2 2 C3001 10UF_6.3V_3 C3002 G 100_5%_2 D Q3002 G P3V3S G S SSM3K7002BFU P3V3S GM:2.2K 2 PM:4.7K SSM3K7002BFU R3005 R3002 2 2.2K_5%_2 1 1 2.2K_5%_2 (60130B4720ZT) BI BI 56D6 50D7 C BI BI 50C7 VGA_LVDS_DDCCLK VGA_LVDS_DDCDATA 1 R3015 1 R3016 PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA 1 R3017 1 R3018 2 0_5%_1 2 0_5%_1 LVDS_DDCCLK LVDS_DDCDATA 2 0_5%_1 2 0_5%_1 34A6 34A6 34A6 34A6 34A6 34A6 34A6 VGA_INV_PWM_3 0_5%_1 2 100_5%_2 PCH_INV_PWM_3 EC_BKLTEN 1R3014 0_5%_1 2 1 2 1 2 1 1 100_5%_2 50C6 50C6 50C6 IN IN PM: 10K 2 0_5%_1 1000PF_50V_2 10K_5%_2 CSC0402_DY 51B2 100K_5%_2 C3006 R3035 24A6 PCH_LVDS_TXDL1_DN PCH_LVDS_TXDL1_DP 1 R3021 1 R3022 2 0_5%_1 2 0_5%_1 PCH_LVDS_TXDL2_DN PCH_LVDS_TXDL2_DP 1 R3023 1 R3024 2 0_5%_1 2 0_5%_1 PCH_LVDS_TXCL_DN PCH_LVDS_TXCL_DP 1 R3025 1 R3026 2 0_5%_1 2 0_5%_1 MIC_IN_CLK MIC_IN_DATA BI BI 24A6 USB_CAM_DN USB_CAM_DP BI BI 51B2 2 IN IN R3006 2 50C6 IN IN C3007 2 B 2 0_5%_1 LVDS_TXCL_DN LVDS_TXCL_DP 2 GM:OPEN 1 R3019 1 R3020 IN IN INV_PWM_3_R EC_BKLTEN_R R3003 PCH_LVDS_TXDL0_DN PCH_LVDS_TXDL0_DP LVDS_TXDL2_DN LVDS_TXDL2_DP 1 21E6 IN IN LVDS_TXDL1_DN LVDS_TXDL1_DP IN IN 1 50D7 IN LVDS_TXDL0_DN LVDS_TXDL0_DP IN IN R3009 1R3013 CN3000 1 34A6 57B6 2 2 56D6 1 1 0.1UF_16V_2 1 C3004 LCM_VDDEN 2 0_5%_1 2 D IN D R3004 PCH_LCM_VDDEN# S 50D7 1 680PF_50V_2 470K_5%_2 Q3001 R3012 PCH_LCM_VDDEN 1 2 1 3 VGA_LCM_VDDEN 1 G 1 IN 2 P3V3S_LCM 2 2 C3003 DIODES_DMP2305U_SOT23_3P 3 57B6 1 0_5%_1 2 1 POWERPAD_2_0610 0.01UF_50V_2 2 47K_5%_2 C3000 1 R3000 2 R3001 R3011 PAD3003 1 D D P3V3S_MOS_LCM D 0.1UF_16V_2 Q3000 S 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 G G1 28 28 G G2 29 29 MIC_IN_DATA_R30 2 C B 30 R3010 ACES_50203_03001_001_30P 100_5%_2 50C6 50C6 50C6 50C6 IN IN IN IN P3V3S 57A6 57A6 IN IN 1 R3031 1 R3032 2 0_5%_1 2 0_5%_1 LVDS_TXDL2_DN LVDS_TXDL2_DP VGA_LVDS_TXCL_DN VGA_LVDS_TXCL_DP 1 R3033 1 R3034 2 0_5%_1 2 0_5%_1 LVDS_TXCL_DN LVDS_TXCL_DP OUT OUT 34C3 OUT OUT 34B3 PAD3001 1 34C3 1 2 2 POWERPAD_2_0610 34C3 34B3 0.1UF_16V_2 VGA_LVDS_TXDL2_DN VGA_LVDS_TXDL2_DP OUT OUT 34C3 1 LVDS_TXDL1_DN LVDS_TXDL1_DP C3011 2 0_5%_1 2 0_5%_1 34C3 2 1 R3029 1 R3030 34C3 1 VGA_LVDS_TXDL1_DN VGA_LVDS_TXDL1_DP OUT OUT 0.1UF_25V_3 A IN IN LVDS_TXDL0_DN LVDS_TXDL0_DP C3010 57A6 2 0_5%_1 2 0_5%_1 2 57A6 IN IN 1 R3027 1 R3028 1 57A6 VGA_LVDS_TXDL0_DN VGA_LVDS_TXDL0_DP 4.7UF_25V_5 57A6 IN IN C3009 57A6 PVBAT_LCD 2 57A6 PVBAT A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 34 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 3050~3099(CRT) 2 P5V0S D3050 56D3 50B7 56E2 56D3 50B7 D 56E2 56D3 50B7 IN IN IN IN IN IN VGA_CRTR R3064 1 0_5%_1 2 PCH_CRTR R3065 1 0_5%_1 2 VGA_CRTG R3066 1 0_5%_1 2 PCH_CRTG R3067 1 2 0_5%_1 VGA_CRTB R3068 1 0_5%_1 2 PCH_CRTB R3069 1 0_5%_1 2 L3052 CRTR 1 2 120NH,5% CRTR_L 35A7 OUT 35C3 P5V0S_CRT1 L3051 CRTG 1 2 CRTG_L 120NH,5% OUT 35A7 35C3 OUT 35A7 35C3 2 56E2 1 SBR3U40P1 L3050 CRTB D FUSE3050 CRTB_L 2 120NH,5% 1 1 C3052 2 15PF_50V_2 1 15PF_50V_2 C3051 2 2 15PF_50V_2 C3050 1 150_1%_2 2 R3056 1 150_1%_2 R3055 2 R3054 2 150_1%_2 1 1 1 SMD1812P110TF P5V0S_CRT2 CN3051 P5V0S_CRTVDD 35D4 35A7 35D4 35A7 35D4 35A7 IN IN IN CRTR_L CRTG_L CRTB_L 1 GM:2.2K PM:2K (60130B2020ZT) 1 TP3050 R3050 R3051 2.2K_5%_2 C CRT_DDCDATA_OUT BI 2 2.2K_5%_2 2 35A3 1 R3053 CRT_DDCCLK_OUT BI 1 R3052 TP3051 35A3 IN IN 35A3 2 1TP24 CRT_DDCDATA_R_OUT CRT_HSYNC_R_OUT CRT_VSYNC_R_OUT CRT_DDCCLK_R_OUT 2 100_5%_2 35A3 1 TP24 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 G1 G1 13 13 G2 G2 14 14 15 C 15 SUYIN_070546HR015M25KZR_15P 1 1 100_5%_2 C3053 C3054 0.1UF_16V_2_DY 2 2 0.1UF_16V_2_DY RESERVE CAP FOR EMI B 35A4 35A4 OUT CRT_VSYNC CRT_HSYNC P3V3S 1 P5V0S OUT 0.22UF_6.3V_2 R3060 VGA_CRT_VSYNC 0_5%_1 2 PCH_CRT_VSYNC R3072 1 0_5%_1 2 VGA_CRT_HSYNC R3073 1 2 0_5%_1 PCH_CRT_HSYNC R3074 1 0_5%_1 2 VGA_CRT_DDCDATA R3075 1 0_5%_1 2 PCH_CRT_DDCDATA R3076 1 0_5%_1 2 VGA_CRT_DDCCLK R3077 1 0_5%_1 2 PCH_CRT_DDCCLK R3061 2.2K_5%_2 2 IN 56D3 56F7 IN 50A6 IN 56D3 56F7 IN 50A6 IN 56A3 IN 50A6 IN 56A3 IN 50A6 B 35A4 OUT CRT_DDCCLK 2 2.2K_5%_2 2 OUT CRT_DDCDATA 0_5%_1 2 R3071 1 1 GM:2.2K PM:10K (60130B1030ZT) C3056 1 35A4 R3070 1 P3V3S 1 2 1 A C3055 35D4 35C3 35D4 35C3 P5V0S_CRTVDD IN IN IN VCC-SYNC SYNC_OUT2 16 VCC-VIDEO SYNC_IN2 15 3 VIDEO_1 SYNC_OUT1 14 4 VIDEO_2 SYNC_IN1 13 5 VIDEO_3 DCC_OUT2 12 6 GND DDC_IN2 11 7 VCC-DCC DDC_IN1 10 8 1 2 0.22UF_6.3V_2 35C3 35D4 CRTR_L CRTG_L CRTB_L U3050 BYP DDC_OUT1 CRT_VSYNC_OUT CRT_VSYNC CRT_HSYNC_OUT CRT_HSYNC CRT_DDCDATA CRT_DDCCLK 9 IN 35B4 IN 35B4 IN IN 1 R3062 2 30_5%_2 CRT_VSYNC_R_OUT 1 R3063 2 30_5%_2 CRT_HSYNC_R_OUT CRT_DDCDATA_OUT OUT 35C3 OUT 35C3 OUT 35C5 OUT 35C5 A 35A4 35A4 CRT_DDCCLK_OUT TI_TPD7S019_15DBQR_SSOP_16P C3057 0.22UF_6.3V_2 2 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 35 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 3150~3199(HDMI) PLACE CLOSE TO CONNECTOR 50B3 BI 50B3 BI PCH_HDMI_DDCDATA 1 R3174 2 0_5%_1 PCH_HDMI_DDCCLK 1 R3175 2 0_5%_1 36A7 36A2 IN HDMI_TX2_C_DP 1 R3166 2 HDMI_TX2_R_DP 0_5%_2 P5V0AL 36A2 IN HDMI_TX2_C_DN 1 R3167 2 HDMI_TX2_R_DN 1 36A7 0_5%_2 56B3 BI BI VGA_HDMI_DDCDATA 1 R3176 2 0_5%_1 HDMI_DDCDATA VGA_HDMI_DDCCLK 1 R3177 2 0_5%_1 HDMI_DDCCLK BI 36C8 BI 36C8 2 36A7 36A2 IN HDMI_TX1_C_DP 1 R3168 D3150 NC 56B3 2 HDMI_TX1_R_DP DIODE-BAT54-TAP-PHP D 3 0_5%_2 IN HDMI_TX1_C_DN 1 R3169 2 HDMI_TX1_R_DN D 1 36A2 1 36A7 R3152 0_5%_2 2.2K_5%_2 36A7 36A2 IN 2.2K_5%_2 2 R3170 2 HDMI_TX0_C_DP 1 GM: 2.2K PM:10K (60130B1030ZT) R3153 2 HDMI_TX0_R_DP 0_5%_2 36B7 P3V3S 36A2 IN HDMI_TX0_C_DN 1 R3171 2 HDMI_TX0_R_DN P3V3S 1 1 36B7 2.2K_5%_2 2 2 Q3151 36B7 HDMI_DDCDATA S 36A2 IN HDMI_TXC_C_DN1 G BI HDMI_TXC_C_DP 1 R3172 2 HDMI_TXC_R_DP 0_5%_2 SSM3K17FU S R3173 2 HDMI_TXC_R_DN 0_5%_2 HDMI_CN_DDCDATA D D 36C3 BI 37C3 37D6 G C IN R3179 2.2K_5%_2 36D6 36A2 G GM: 2.2K PM:10K R3178 (60130B1030ZT) P5V0AL Q3150 G D3155 SSM3K17FU 36D6 BI HDMI_DDCCLK S S D D 40MIL HDMI_CN_DDCCLK 36C3 BI CN3150 1 0_5%_2 2 36C6 37C3 36C6 TP24 1 HDMI_CN_DDCCLK BI BI FUSE3150 1 2 P5V0AL_HDMI_VDD1 1 37D3 HDMI_CEC BI TP3151 HDMI_CN_DDCDATA P5V0AL_HDMI_VDD2 37D3 TMDS Data2+ 2 TMDS Data2 Shield 3 TMDS Data2- 4 TMDS Data1+ 5 TMDS Data1 Shield 6 TMDS Data1- 7 TMDS Data0+ 8 TMDS Data0 Shield 9 TMDS Data0- 10 TMDS Clock+ 11 TMDS Clock Shield 12 TMDS Clock- 13 CEC G1 G1 14 Reserved G2 G2 15 DDC Clock G3 G3 16 DDC Data G4 G4 17 DDC/CEC GND 18 +5V Power 19 SMD1812P110TF OUT P3V3S Hot Plug Detect R3154 HPDET_IC 1 C3150 SYN_100042GR019M26DZL_19P 2 1 37C1 1 1 SBR3U40P1 C 1K_5%_2 R3150 C3151 100PF_50V_2 22PF_50V_2_DY 2 2 1 2 470K_5%_2 CLOSE TO CONNECTOR GM:680_5% R3165 PM:499_5% 100K_5%_2 1 R3164 B 2 36C5 36A2 IN 2 R3180 50B3 680_5%_2 HDMI_TXC_C_DN 3 1 VGA_HPDET 1 SSM3K7002BFU 2 0_5%_1 U3150 R3181 R3163 1 OUT PCH_HPDET 5 HDMI_TXC_C_DP + IN D 36A2 S 36C5 P3V3S G Q3152 B 2 1 (6013A0076801) 56C5 2 OUT HPDET 2 0_5%_1 IN 1 IN 21D6 37B1 IN 31C6 41C7 51A7 3 HDMI_TX0_C_DN PLT_RST# TC7SZ08FU R3162 36A2 HDMI_HPD_EC 2 - 680_5%_2 36D5 1 4 2 680_5%_2 R3161 36D5 36A2 IN HDMI_TX0_C_DP 1 2 680_5%_2 R3160 36D5 36A2 IN HDMI_TX1_C_DN 1 2 680_5%_2 56F3 R3159 36D5 36A2 IN HDMI_TX1_C_DP 1 56F3 2 56F3 56F3 680_5%_2 A 56F3 R3158 36D5 36A2 IN HDMI_TX2_C_DN 1 56F3 2 56F3 56F3 680_5%_2 IN IN IN IN IN IN IN IN VGA_HDMI_TX2_DN VGA_HDMI_TX2_DP VGA_HDMI_TX1_DN VGA_HDMI_TX1_DP VGA_HDMI_TX0_DN VGA_HDMI_TX0_DP VGA_HDMI_TXC_DN VGA_HDMI_TXC_DP C3152 1 2 0.1UF_6.3V_1 C3154 1 C3153 1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 C3156 1 C3155 1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 C3158 1 C3157 1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 C3159 1 2 0.1UF_6.3V_1 A R3157 36D5 36A2 IN HDMI_TX2_C_DP 1 2 680_5%_2 50B3 50B3 50B3 50B3 50B3 50B3 50B3 50B3 IN IN IN IN IN IN IN IN PCH_HDMI_TX2_DN PCH_HDMI_TX2_DP PCH_HDMI_TX1_DN PCH_HDMI_TX1_DP PCH_HDMI_TX0_DN PCH_HDMI_TX0_DP PCH_HDMI_TXC_DN PCH_HDMI_TXC_DP C3160 1 C3162 1 C3164 1 C3166 1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 2 0.1UF_6.3V_1 C3161 1 2 0.1UF_6.3V_1 C3163 1 2 0.1UF_6.3V_1 C3165 1 2 0.1UF_6.3V_1 C3167 1 HDMI_TX2_C_DN HDMI_TX2_C_DP HDMI_TX1_C_DN HDMI_TX1_C_DP HDMI_TX0_C_DN HDMI_TX0_C_DP HDMI_TXC_C_DN HDMI_TXC_C_DP 2 0.1UF_6.3V_1 OUT OUT OUT OUT OUT OUT OUT OUT 36A7 36D5 36A7 36D5 36A7 36D5 36A7 36D5 36B7 36D5 INVENTEC 36A7 36D5 36B7 36C5 TITLE 36B7 36C5 MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 36 REV X01 68 of 1 8 7 6 4 5 3 2 1 P3V3AL 1 1 P3V3AL D3200 R3201 NC DIODE-BAT54-TAP-PHP Q3201 G 2 SSM3K17FU 4.02K_1%_2 2 G 3 D P3V3AL HDMI_DDCCLK_CEC BI S S DHDMI_CN_DDCCLK D 36C3 BI D 36C6 1 37B3 P3V3AL R3204 37B6 IN 2 + U3203 24 HDMI_CEC 2 1 R3214 CEC_IN1 1 NC 5 27K_5%_2 BI 36C3 Q3200 3 4.02K_1%_2 SSM3K17FU G D R3206 1 1 2 CEC_OUT OUT 37B6 37B3 HDMI_DDCDATA_CEC BI S S DHDMI_CN_DDCDATA D 36C3 BI 36C6 1 G P3V3AL 22K_5%_2 SSM3K7002BFU 2 S 2 Q3203 3 74LVC1G14GV G R3200 - 68_5%_2 C3200 2 P3V3AL P3V3AL 37A6 37D8 37C6 OUT IN IN OUT CEC_XOUT CEC_XIN CEC_IN CEC_OUT P3_5-SSCK-SCL-CMP1_2 2 P3_7-CNTR0#-SSO-TXD1 3 RESET# 4 XOUT-P4_7 5 VSS-AVSS 6 XIN-P4_6 7 VCC-AVCC 8 MODE 9 P4_5-INT0#-RXD1 10 P3_4-SCS#-SDA-CMP1_1 P3_3-TCIN-INT3#-SSI00-CMP1_0 EC_SMB2_DATA 19 P1_0-KI0#-AN8-CMP0_0 18 HDMI_DDCDATA_CEC P1_1-KI1#-AN9-CMP0_1 17 HDMI_DDCCLK_CEC P4_2-VREF 16 P1_2-KI2#-AN10-CMP0_2 15 P1_3-KI3#-AN11-TZOUT 14 P1_4-TXD0 P1_5-RXD0-CNTR01-INT11# P1_7-CNTR00-INT10# 20 P1_6-CLK0-SSI01 2 5 NC U3200 R3227 1 1 1 5A7 21D3 56C8 21D2 BI + 1 4.7K_5%_2 EC_SMB2_CLK C 2 4 2 HPDET_IC 36C4 IN 37C5 BI BI 37D5 - 33_5%_2 PHP_74LVC1G17_SOT753_5P 3 37A8 BI 2 2 2 U3202 5A7 21D3 56D8 21D2 R3208 4.7K_5%_2 2 R3210 4.7K_5%_2 4.7K_5%_2 R3213 R3209 1 1 1 C 0.1UF_16V_2 1 R3205 100K_5%_2 13 12 11 HDMI_HPD_EC RSC_0402_DY 1 2 1UF_6.3V_2 1 2 C3205 0.1UF_16V_2 1 C3202 2 R3202 P3V3AL B 36B2 21D6 OUT RENESAS_R5F211B4D61SP_LSSOP_20P B 37B6 OUT 47K_5%_2 1 R3212 2 47K_5%_2 2 R3211 1 P3V3AL CEC_XOUT CEC_XIN IN 37B6 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 37 REV X01 68 of 1 8 7 6 4 5 REFERENCE 4100~4299(DDR) BI BI DQ14 78 A15 DQ15 DQ16 43C5 43C5 43D4 43D4 43D4 43D4 43D4 43D4 43A8 43A8 43A8 38A6 38A6 48A8 39C8 48A8 39C8 BA0 DQ17 108 BA1 DQ18 BA2 DQ19 114 S0# DQ20 121 S1# DQ21 101 CK0 DQ22 103 CK0# DQ23 102 CK1 DQ24 104 CK1# DQ25 73 CKE0 DQ26 74 CKE1 DQ27 115 CAS# DQ28 110 RAS# DQ29 113 WE# DQ30 197 SA0 DQ31 201 SA1 DQ32 202 SCL DQ33 200 SDA DQ34 116 ODT0 79 DQ35 43C5 43C5 IN IN M_ODT0 M_ODT1 120 DQ36 DQ37 ODT1 DQ38 11 DM0 DQ39 28 DM1 DQ40 46 DM2 DQ41 63 DM3 DQ42 136 DM4 DQ43 153 DM5 DQ44 170 DM6 DQ45 187 DM7 DQ46 DQ47 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN M_A_DQS0_DP M_A_DQS1_DP M_A_DQS2_DP M_A_DQS3_DP M_A_DQS4_DP M_A_DQS5_DP M_A_DQS6_DP M_A_DQS7_DP M_A_DQS0_DN M_A_DQS1_DN M_A_DQS2_DN M_A_DQS3_DN M_A_DQS4_DN M_A_DQS5_DN M_A_DQS6_DN M_A_DQS7_DN 12 DQS0 DQ48 29 DQS1 DQ49 47 DQS2 DQ50 64 DQS3 DQ51 DQS4 DQ52 DQS5 DQ53 137 154 171 DQS6 DQ54 188 DQS7 DQ55 10 DQS0# DQ56 27 DQS1# DQ57 45 DQS2# DQ58 62 DQS3# DQ59 135 DQS4# DQ60 152 DQS5# DQ61 169 DQS6# DQ62 186 DQS7# DQ63 14 C4101 C4100 C4102 C4103 VDD3 VSS18 49 82 VDD4 VSS19 54 87 VDD5 VSS20 55 88 VDD6 VSS21 60 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 VDD7 VSS22 61 94 VDD8 VSS23 65 99 C4104 C4105 1 C4106 C4107 15 16 330UF_2.5V_DY 17 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 18 19 NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S 20 21 C4110 P3V3S 22 C4109 C4108 23 24 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 25 26 27 28 C4114 VDD9 VSS24 66 100 VDD10 VSS25 71 105 VDD11 VSS26 72 106 VDD12 VSS27 127 111 VDD13 VSS28 128 112 VDD14 VSS29 133 117 VDD15 VSS30 134 118 VDD16 VSS31 138 123 VDD17 VSS32 139 124 VDD18 VSS33 144 VSS34 145 VSS35 150 VSS36 151 NC1 VSS37 155 122 NC2 VSS38 156 125 NCTEST VSS39 161 VSS40 162 C4115 29 199 30 31 VDDSPD 0.1UF_16V_2 2.2UF_6.3V_3 77 32 33 34 35 36 37 P0V75M_VREF 38 39C3 38B5 41A5 39C3 PM_EXTTS#1_R DDR3_DRAMRST# OUT OUT 198 30 VSS41 167 EVENT# VSS42 168 RESET# VSS43 172 VSS44 173 VSS45 178 VREF_DQ VSS46 179 VREF_CA VSS47 184 VSS48 185 VSS49 189 VSS50 190 39 40 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 41 42 1 126 43 C4150 44 C4116 2 45 0.1UF_16V_2 2.2UF_6.3V_3 46 47 P0V75M_VREF 48 49 50 51 52 C4117 53 C4118 54 55 0.1UF_16V_2 2.2UF_6.3V_3 P3V3S 56 57 58 59 VSS1 3 VSS2 VSS51 195 8 VSS3 VSS52 196 9 VSS4 13 VSS5 14 VSS6 19 VSS7 20 VSS8 25 VSS9 VTT1 203 26 VSS10 VTT2 204 31 VSS11 32 VSS12 G1 G1 37 VSS13 G2 G2 38 VSS14 43 VSS15 C P0V75S 1.5A B 60 R4104 61 BELLW_80001_1021_204P 10K_5%_2 62 63 PM_EXTTS#1_R 39C3 38C3 IN PLACE THESE CAPS CLOSE TO VTT1 AND VTT2 1 BELLW_80001_1021_204P C4119 C4120 C4121 C4122 1 1 P3V3S 1 43A8 IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT IN IN 109 81 13 D 1 43A8 M_A_BS0 M_A_BS1 M_A_BS2 M_CS#0 M_CS#1 M_CLK_DDR0_DP M_CLK_DDR0_DN M_CLK_DDR1_DP M_CLK_DDR1_DN M_CKE0 M_CKE1 M_A_CAS# M_A_RAS# M_A_WE# SA0_DIM0 SA1_DIM0 PCH_3S_SMCLK PCH_3S_SMDATA 48 1 43A8 44 VSS17 2 DQ13 A14 VSS16 VDD2 1 A13 80 VDD1 76 2 119 12 1 DQ12 2 A12/BC# 1 83 CN4100 75 LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 11 2 DQ11 1 A11 2 84 P1V5 9 1 DQ10 2 A10/AP 8 10 1 DQ9 2 A9 107 7 1 DQ8 2 A8 85 1 89 6 2 DQ7 1 A7 5 2 86 4 1 DQ6 2 DQ5 A6 1 15 A5 90 3 2 14 DQ4 1 13 A4 91 2 2 12 DQ3 1 11 A3 92 2 10 95 1 1 9 D DQ2 2 8 DQ1 A2 1 7 A1 96 2 6 97 43D8 1 5 DQ0 0 2 4 A0 M_A_DQ<0> 7 M_A_DQ<1> 15 M_A_DQ<2> 17 M_A_DQ<3> 4 M_A_DQ<4> 6 M_A_DQ<5> 16 M_A_DQ<6> 18 M_A_DQ<7> 21 M_A_DQ<8> 23 M_A_DQ<9> 33 M_A_DQ<10> 35 M_A_DQ<11> 22 M_A_DQ<12> 24 M_A_DQ<13> 34 M_A_DQ<14> 36 M_A_DQ<15> 39 M_A_DQ<16> 41 M_A_DQ<17> 51 M_A_DQ<18> 53 M_A_DQ<19> 40 M_A_DQ<20> 42 M_A_DQ<21> 50 M_A_DQ<22> 52 M_A_DQ<23> 57 M_A_DQ<24> 59 M_A_DQ<25> 67 M_A_DQ<26> 69 M_A_DQ<27> 56 M_A_DQ<28> 58 M_A_DQ<29> 68 M_A_DQ<30> 70 M_A_DQ<31> 129M_A_DQ<32> 131M_A_DQ<33> 141M_A_DQ<34> 143M_A_DQ<35> 130M_A_DQ<36> 132M_A_DQ<37> 140M_A_DQ<38> 142M_A_DQ<39> 147M_A_DQ<40> 149M_A_DQ<41> 157M_A_DQ<42> 159M_A_DQ<43> 146M_A_DQ<44> 148M_A_DQ<45> 158M_A_DQ<46> 160M_A_DQ<47> 163M_A_DQ<48> 165M_A_DQ<49> 175M_A_DQ<50> 177M_A_DQ<51> 164M_A_DQ<52> 166M_A_DQ<53> 174M_A_DQ<54> 176M_A_DQ<55> 181M_A_DQ<56> 183M_A_DQ<57> 191M_A_DQ<58> 193M_A_DQ<59> 180M_A_DQ<60> 182M_A_DQ<61> 192M_A_DQ<62> 194M_A_DQ<63> 5 1 3 98 + 2 M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15> 2 1 B 1 M_A_DQ<63..0> CN4100 0 C 2 CHA M_A_A<15..0> 43A4 3 R4100 10K_5%_2_DY 2 10K_5%_2_DY 2 SO-DIMMA SPD ADDRESS IS 0XA2 2 R4101 A 2 IF SA0_DIM0=1 , SA1_DIM0=0 A 2 2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 NOTE: SA0_DIM0 SO-DIMMA TS ADDRESS IS 0X32 1 1 SA1_DIM0 IN 38C8 IN 38C8 IF SA0_DIM0=0 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA0 R4102 R4103 10K_5%_2 INVENTEC 2 10K_5%_2 2 SO-DIMMA TS ADDRESS IS 0X30 TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 38 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4100~4299(DDR) CHB M_B_A<15..0> BI M_B_DQ<63..0> DQ13 80 A14 DQ14 78 A15 DQ15 DQ16 43A4 43A4 43A4 43C1 43C1 43D1 43D1 43D1 43D1 43D1 43D1 43A4 43A4 C 43A4 39A7 39A6 OUT OUT SA0_DIM1 SA1_DIM1 48A8 38C8 48A8 38C8 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN M_B_BS0 M_B_BS1 M_B_BS2 M_CS#2 M_CS#3 M_CLK_DDR2_DP M_CLK_DDR2_DN M_CLK_DDR3_DP M_CLK_DDR3_DN M_CKE2 M_CKE3 M_B_CAS# M_B_RAS# M_B_WE# 109 BA0 DQ17 108 BA1 DQ18 BA2 DQ19 114 S0# DQ20 121 S1# DQ21 101 CK0 DQ22 103 CK0# DQ23 102 CK1 DQ24 104 CK1# DQ25 73 CKE0 DQ26 74 CKE1 DQ27 115 CAS# DQ28 110 RAS# DQ29 113 WE# DQ30 197 SA0 DQ31 201 SA1 DQ32 202 SCL DQ33 200 SDA DQ34 79 PCH_3S_SMCLK PCH_3S_SMDATA DQ35 43C1 43C1 IN IN M_ODT2 M_ODT3 116 ODT0 DQ36 120 ODT1 DQ37 DQ38 11 DM0 DQ39 28 DM1 DQ40 46 DM2 DQ41 63 DM3 DQ42 136 DM4 DQ43 153 DM5 DQ44 170 DM6 DQ45 187 DQ46 DM7 DQ47 43B1 43B1 43B1 43B1 43B1 B 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN M_B_DQS0_DP M_B_DQS1_DP M_B_DQS2_DP M_B_DQS3_DP M_B_DQS4_DP M_B_DQS5_DP M_B_DQS6_DP M_B_DQS7_DP M_B_DQS0_DN M_B_DQS1_DN M_B_DQS2_DN M_B_DQS3_DN M_B_DQS4_DN M_B_DQS5_DN M_B_DQS6_DN M_B_DQS7_DN 12 DQS0 DQ48 29 DQS1 DQ49 47 DQS2 DQ50 64 DQS3 DQ51 137 DQS4 DQ52 154 DQS5 DQ53 171 DQS6 DQ54 188 DQS7 DQ55 10 DQS#0 DQ56 27 DQS#1 DQ57 45 DQS#2 DQ58 62 DQS#3 DQ59 135 DQS#4 DQ60 152 DQS#5 DQ61 169 DQS#6 DQ62 186 DQS#7 DQ63 1 A13 119 13 C4124 14 C4125 C4126 C4127 C4128 C4129 C4130 15 16 1UF_6.3V_2 17 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 VSS19 54 87 VDD5 VSS20 55 60 VDD7 VSS22 61 VDD8 VSS23 65 99 VDD9 VSS24 66 100 VDD10 VSS25 71 105 VDD11 VSS26 72 106 VDD12 VSS27 127 111 VDD13 VSS28 128 112 VDD14 VSS29 133 117 VDD15 VSS30 134 118 VDD16 VSS31 138 123 VDD17 VSS32 139 124 VDD18 VSS33 144 VSS34 145 VSS35 150 VSS36 151 VSS37 155 C4132 C4131 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 27 C4138 49 VDD4 94 23 28 VSS18 93 P3V3S 26 48 VDD3 82 VSS21 C4133 25 44 VSS17 VDD6 21 24 VSS16 VDD2 81 88 19 22 VDD1 76 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 18 20 CN4101 75 LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 11 12 2 DQ12 1 DQ11 A12 2 A11 83 P1V5 C4137 29 199 30 2.2UF_6.3V_3 31 VDDSPD 0.1UF_16V_2 77 32 33 34 35 36 P0V75M_VREF 37 38C3 38B5 41A5 38C3 PM_EXTTS#1_R DDR3_DRAMRST# OUT OUT NC1 122 NC2 VSS38 156 125 NCTEST VSS39 161 VSS40 162 EVENT# VSS41 167 RESET# VSS42 168 VSS43 172 VSS44 173 VREF_DQ VSS45 178 VREF_CA VSS46 179 VSS47 184 VSS48 185 198 30 38 39 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 40 1 126 41 42 43 C4151 44 C4139 45 46 47 P0V75M_VREF 0.1UF_16V_2 2.2UF_6.3V_3 48 49 50 51 1 84 D 9 10 52 C4140 53 C4141 54 0.1UF_16V_2 2.2UF_6.3V_3 55 56 2 DQ10 1 A10_AP 2 107 7 1 DQ9 2 DQ8 A9 1 A8 85 6 8 2 DQ7 1 A7 89 5 2 DQ6 1 A6 86 1 15 90 4 2 14 DQ5 2 13 A5 3 1 12 91 2 2 11 DQ4 1 10 DQ3 A4 2 9 A3 92 1 1 8 DQ2 2 7 D DQ1 A2 95 1 6 A1 96 0 2 5 97 M_B_DQ<0> 7 M_B_DQ<1> 15 M_B_DQ<2> 17 M_B_DQ<3> 4 M_B_DQ<4> 6 M_B_DQ<5> 16 M_B_DQ<6> 18 M_B_DQ<7> 21 M_B_DQ<8> 23 M_B_DQ<9> 33 M_B_DQ<10> 35 M_B_DQ<11> 22 M_B_DQ<12> 24 M_B_DQ<13> 34 M_B_DQ<14> 36 M_B_DQ<15> 39 M_B_DQ<16> 41 M_B_DQ<17> 51 M_B_DQ<18> 53 M_B_DQ<19> 40 M_B_DQ<20> 42 M_B_DQ<21> 50 M_B_DQ<22> 52 M_B_DQ<23> 57 M_B_DQ<24> 59 M_B_DQ<25> 67 M_B_DQ<26> 69 M_B_DQ<27> 56 M_B_DQ<28> 58 M_B_DQ<29> 68 M_B_DQ<30> 70 M_B_DQ<31> 129M_B_DQ<32> 131M_B_DQ<33> 141M_B_DQ<34> 143M_B_DQ<35> 130M_B_DQ<36> 132M_B_DQ<37> 140M_B_DQ<38> 142M_B_DQ<39> 147M_B_DQ<40> 149M_B_DQ<41> 157M_B_DQ<42> 159M_B_DQ<43> 146M_B_DQ<44> 148M_B_DQ<45> 158M_B_DQ<46> 160M_B_DQ<47> 163M_B_DQ<48> 165M_B_DQ<49> 175M_B_DQ<50> 177M_B_DQ<51> 164M_B_DQ<52> 166M_B_DQ<53> 174M_B_DQ<54> 176M_B_DQ<55> 181M_B_DQ<56> 183M_B_DQ<57> 191M_B_DQ<58> 193M_B_DQ<59> 180M_B_DQ<60> 182M_B_DQ<61> 192M_B_DQ<62> 194M_B_DQ<63> 5 1 4 DQ0 2 3 43D4 BI A0 1 2 98 2 1 M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15> 1 0 CN4101 2 43A1 57 58 2 VSS1 VSS49 189 3 VSS2 VSS50 190 8 VSS3 VSS51 195 9 VSS4 VSS52 196 13 VSS5 14 VSS6 19 VSS7 20 VSS8 25 VSS9 26 VSS10 VTT1 203 31 VSS11 VTT2 204 32 VSS12 37 VSS13 G1 G1 38 VSS14 G2 G2 43 VSS15 C P0V75S 1.5A B BELLW_80001_5021_204P 59 60 61 62 63 BELLW_80001_5021_204P NOTE: P3V3S C4142 C4143 1 1 1 1 PLACE THESE CAPS CLOSE TO VTT1 AND VTT2 C4144 C4145 1 SO-DIMMB TS ADDRESS IS 0X34 1 SO-DIMMB SPD ADDRESS IS 0XA4 A 2 A 10K_5%_2 2 2 SA1_DIM1 R4107 IN 39C8 1 SA0_DIM1 1 IN 2 R4106 10K_5%_2_DY 39C8 2 2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 R4105 R4108 INVENTEC 2 10K_5%_2_DY 2 10K_5%_2 TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 39 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4300~4349(FAN) P5V0S REFERENCE 4411~4449(THERMAL ) PAD4300 1 1 P5V0S_FAN 2 2 POWERPAD_2_0610 L4300 2 C4302 0.1UF_16V_2 1 1 C4301 4.7UF_6.3V_3 D 10K_5%_2 2 R4300 1 P3V3S 2 C4307 D 2 KC_FBM_11_160808_101_T_2P_DY 22UF_6.3V_5_DY 2 1 1 CN4300 21B6 FAN_TACH1 IN 1 TP4300 TP30 1 1 2 2 3 3 G G1 4 4 G G2 1 2 R4306 FAN1_PWM 21B6 IN 1 C 10K_5%_2 1 2 C4305 CSC0402_DY C 220pF_50V_2 2 C4300 1 ACES_50273_0047N_001_4P P3V3S FAN CN TP4301 B CSC0402_DY 2 C4306 1 TP30 B P5V0AL RHYST1 71 3 OT1 TMSNS2 6 4 OT2 RHYST2 5 1 3 C S G 41D5 IN PM_THRMTRIP# 1 330_5%_2 2 B B SSM3K7002BFU 2 Q4412 R4413 52C1 C4412 MMBT4401 CSC0402_DY ENE_P2809A2_SOT23_8P 1 R4441 13.3K_1%_2 2 A 2 100K_1%_NTC 2 2 THRM_SHUTDWN# 1 OUT R4447 15D8 2 D 2 13.3K_1%_2 56D6 40B1 56D6 40A8 E GND 15D8 Q4411 1 C 2 R4443 P5V0AL 1 8 OUT R4414 E TMSNS1 IN PVCORE_PG 2M_5%_2 26.7K_1%_2 VCC 2 U4441 11A4 1 2 1 1 11C7 THRM_SHUTDWN# R4446 2 2 R4444 R4445 100K_5%_2 0.1UF_16V_2 C4441 1 1 P5V0AL 100K_1%_NTC 26.7K_1%_2 R4442 1 49B7 A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 40 REV X01 68 of 1 8 7 6 4 5 REFERENCE 4500~4699(CPU) 3 2 CN4500 R4500 1 PROC_SELECT# AN34 1 NV_CLE 2 OUT 1 AL33 CATERR# AN33 PECI 1 1K_5%_2 52C2 21A6 OUT H_PECI R4503 62_5%_2 11B7 CPU_PROCHOT# 1 1 OUT 2 21C3 PROCESS STRAP SETTING A27 CLK_DMI_PCH_DN R4504 2 CPU_PROCHOT#_R AL32 PROCHOT# 56_5%_2 A16 R4510 1 DPLL_REF_CLK# A15 R4511 1 STUFF R4502 CSC0402_DY STUFF R4500/R4501 40A4 52C1 OUT PM_THRMTRIP# AN32 D SM_DRAMRST# R8 CPU_DRAMRST# SM_RCOMP[0] AK1SM_RCOMP0 140_1%_2 A5 SM_RCOMP1 R4512 1 R4513 1 2 SM_RCOMP[1] 2 25.5_1%_2 SM_RCOMP[2] A4 SM_RCOMP2 R4514 1 2 200_1%_2 OUT 41A5 THERMTRIP# BI H_PM_SYNC AM34 PM_SYNC R4505 200_5%_2 SET TOVCC WHEN HIGH 2 52C2 IN H_CPUPWRGD AP33 UNCOREPWRGOOD R4506 49B7 PM_DRAM_PWRGD IN 1 PM_DRAM_PWRGD_R 2 V8 JTAG & BPM 1 SET TOVSS WHEN LOW(DEFAULT) 49A3 PWR MANAGEMENT LOW IN C6/C7 PRDY# AP29 PREQ# AP27 TCK AR26 TMS AR27 PLT_RST# IN 1 AR33 2 RESET# 1 1 1.5K_5%_2 R4509 R4508 1 TP4502 1 TP4503 1 TP4504 1 TP4505 1 TP4506 1 TP4507 1 TP4508 TRST# AP30 TDI AR28 TP30 TDO AP26 AL35 DBR# TP30 TP30 1 TP4509 H_PRDY# H_PREQ# OUT IN H_TCK H_TMS H_TRST# H_TDI H_TDO SYS_RESET# 41B2 IN IN IN 41B2 IN OUT 41B2 OUT 49B8 41B2 41B2 C SM_DRAMPWROK R4507 31C6 TP30 TP30 TP30 TP30 TP30 130_1%_2 51A7 36B2 2 1K_5%_2 2 1K_5%_2 C4500 DMI&FDI TERMINATIONVOLTAGE NV_CLE 48B3 P1V05S DPLL_REF_CLK P1V5S C 48B3 IN IN 2 SANDY BRIDGE/IVY BRIDGE A28 CLK_DMI_PCH_DP TP24 52B2 MISC DDR3 1 TP4501 P1V05S THERMAL 2 R4501 BCLK BCLK# SKTOCC# TP24 PLACE CLOSE TO CPT AND NVRAM CONNECTOR SANDY BRIDGE ONLY CLOCKS TP4500 C26 2.2K_5%_2_DY H_SNB_IVB# OUT H_SNB_IVB# R4502 2.2K_5%_2 D OUT 2 1 41D8 MISC P1V8S 41D5 1 BPM#[0] AT28 BPM#[1] AR29 CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT BPM#[2] AR30 - MAX LENGTH = 500 MILS BPM#[3] AT30 - TRACE WIDTH = 15MILS AND BPM#[4] AP32 - MB TRACE IMPEDANCE < 68 MOHMS BPM#[5] AR31 (WORST CASE RESISTANCE) BPM#[6] AT31 BPM#[7] AR32 10K_5%_2 P1V05S 2 2 750_1%_2 LOTES_ACA_ZIF_069_P01_989P 41C1 IN 41C1 IN 41C1 IN H_TMS R4516 1 2 51_5%_2 H_TDI R4517 1 2 51_5%_2 H_PREQ# R1418 1 2 51_5%_2_DY B B S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3 IN H_TCK R4519 1 2 51_5%_2 H_TRST# R4520 1 2 51_5%_2 1 R4602 R4601 1K_5%_2 2 2 1K_5%_2 1 DRAMRST_CNTRL OUT R4603 2 DDR3_DRAMRST# OUT 38C3 IN 41D2 39C3 1K_5%_2 3 45D6 45D8 IN 41C1 P1V5 1 P3V3A 41C1 R4600 1 1 2 G S IN D Q4600 DRAMRST_CNTRL_PCH 0_5%_2 A 1 2 1 A CPU_DRAMRST# SSM3K7002BFU C4620 R4604 0.047UF_16V_2 2 4.99K_1%_2 2 48D3 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 41 REV X01 68 of 1 8 7 6 4 5 3 2 1 P1V05S REFERENCE 4500~4699(CPU) CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS 1 SHOULD BE SHORTED AND ROUTED WITH - MAX LENGTH = 500 MILS R4522 24.9_1%_2 - TYPICAL IMPEDANCE = 43 MOHMS CN4500 49C6 D 49C6 49C6 49C6 49C6 49D6 49D6 49D6 49D6 49D6 49D6 49D6 49D6 49D3 49D3 49D3 49D3 49D3 49D3 C 49D3 49D3 1 IN IN PEG_RX#[4] J32 PEG_RX#[5] H34 PEG_RX#[6] H31 PEG_RX#[7] G33 DMI_TX0_DP B28 DMI_RX[0] DMI_TX1_DP B26 DMI_RX[1] DMI_TX2_DP A24 DMI_RX[2] DMI_TX3_DP B23 DMI_RX[3] DMI_RX0_DN G21 DMI_TX#[0] DMI_RX1_DN E22 DMI_TX#[1] PEG_RX#[8] G30 DMI_RX2_DN F21 DMI_TX#[2] PEG_RX#[9] F35 DMI_RX3_DN D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_RX#[11] E32 DMI_RX0_DP G22 DMI_TX[0] PEG_RX#[12] D33 DMI_RX1_DP D22 DMI_TX[1] PEG_RX#[13] D31 DMI_RX2_DP F20 DMI_TX[2] PEG_RX#[14] B33 DMI_RX3_DP C21 DMI_TX[3] PEG_RX#[15] C32 FDI_TX0_DN A21 FDI0_TX#[0] FDI_TX1_DN H19 FDI0_TX#[1] FDI_TX2_DN E19 FDI0_TX#[2] FDI_TX3_DN F18 FDI0_TX#[3] FDI_TX4_DN B21 FDI1_TX#[0] FDI_TX5_DN C20 FDI1_TX#[1] FDI_TX6_DN D18 FDI1_TX#[2] FDI_TX7_DN E17 FDI1_TX#[3] - TYPICAL IMPEDANCE = 14.5 MOHMS PEG_RX[0] J33 PEG_RX[1] L35 PEG_RX[2] K34 PEG_RX[3] H35 PEG_RX[4] H32 PEG_RX[5] G34 PEG_RX[6] G31 PEG_RX[7] F33 PEG_RX[8] F30 PEG_RX[9] E35 PEG_RX[10] E33 PEG_RX[11] F32 PEG_RX[12] D34 PEG_RX[13] E31 FDI0_TX[1] PEG_RX[14] C33 FDI0_TX[2] PEG_RX[15] B32 G18 FDI0_TX[3] FDI_TX4_DP B20 FDI1_TX[0] PEG_TX#[0] M29 FDI_TX5_DP C19 FDI1_TX[1] PEG_TX#[1] M32 FDI_TX6_DP D19 FDI1_TX[2] PEG_TX#[2] M31 FDI_TX7_DP F17 FDI1_TX[3] PEG_TX#[3] L32 PEG_TX#[4] L29 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 PEG_TX#[7] J30 FDI_INT H20 FDI_INT PEG_TX#[8] J28 OUT OUT OUT OUT OUT OUT OUT OUT PEG_TX#[9] FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 PEG_TX#[12] F27 PEG_TX#[13] D28 PEG_TX#[14] F26 PEG_TX#[15] E25 24.9_1%_2 2 B CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS A18 eDP_COMPIO A17 eDP_ICOMPO PEG_TX[0] M28 B16 eDP_HPD PEG_TX[1] M33 PEG_TX[2] M30 PEG_TX[3] L31 PEG_TX[4] L28 PEG_TX[5] K30 PEG_TX[6] K27 eDP_AUX D15 eDP_AUX# eDP SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH C15 PEG_TX[7] J29 C17 eDP_TX[0] PEG_TX[8] J27 F16 eDP_TX[1] PEG_TX[9] H28 C16 eDP_TX[2] PEG_TX[10] G28 G15 eDP_TX[3] PEG_TX[11] E28 PEG_TX[12] F28 C18 eDP_TX#[0] PEG_TX[13] D27 E16 eDP_TX#[1] PEG_TX[14] E26 D16 eDP_TX#[2] PEG_TX[15] D25 F15 PEG_C_RX15_DN PEG_C_RX14_DN PEG_C_RX13_DN PEG_C_RX12_DN PEG_C_RX11_DN PEG_C_RX10_DN PEG_C_RX9_DN PEG_C_RX8_DN PEG_C_RX7_DN PEG_C_RX6_DN PEG_C_RX5_DN PEG_C_RX4_DN PEG_C_RX3_DN PEG_C_RX2_DN PEG_C_RX1_DN PEG_C_RX0_DN PEG_C_RX15_DP PEG_C_RX14_DP PEG_C_RX13_DP PEG_C_RX12_DP PEG_C_RX11_DP PEG_C_RX10_DP PEG_C_RX9_DP PEG_C_RX8_DP PEG_C_RX7_DP PEG_C_RX6_DP PEG_C_RX5_DP PEG_C_RX4_DP PEG_C_RX3_DP PEG_C_RX2_DP PEG_C_RX1_DP PEG_C_RX0_DP IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 57B1 57B1 57B1 D 57B1 57B1 57C1 CLOSE TO CPU 57C1 57C1 57C1 57C1 42B4 IN 42B4 IN PEG_TX15_DN PEG_TX14_DN PEG_TX13_DN PEG_TX12_DN PEG_TX11_DN PEG_TX10_DN PEG_TX9_DN PEG_TX8_DN PEG_TX7_DN PEG_TX6_DN PEG_TX5_DN PEG_TX4_DN PEG_TX3_DN PEG_TX2_DN PEG_TX1_DN PEG_TX0_DN PEG_TX15_DP PEG_TX14_DP PEG_TX13_DP PEG_TX12_DP PEG_TX11_DP PEG_TX10_DP PEG_TX9_DP PEG_TX8_DP PEG_TX7_DP PEG_TX6_DP PEG_TX5_DP PEG_TX4_DP PEG_TX3_DP PEG_TX2_DP PEG_TX1_DP PEG_TX0_DP 57D1 C4580 1 2 0.22UF_6.3V_1 PEG_C_TX0_DN PEG_TX1_DN C4581 1 2 0.22UF_6.3V_1 PEG_C_TX1_DN 2 0.22UF_6.3V_1 PEG_C_TX2_DN 0.22UF_6.3V_1 PEG_C_TX3_DN OUT 57D6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57B6 OUT 57B6 OUT 57B6 OUT 57B6 OUT 57B6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57D6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57C6 OUT 57B6 OUT 57B6 OUT 57B6 OUT 57B6 OUT 57B6 57D1 57D1 42B4 IN PEG_TX2_DN C4582 1 PEG_TX3_DN C4583 1 2 PEG_TX4_DN C4584 1 2 0.22UF_6.3V_1 PEG_C_TX4_DN PEG_TX5_DN C4585 1 2 0.22UF_6.3V_1 PEG_C_TX5_DN PEG_TX6_DN 57D1 57D1 42B4 42B4 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 57B1 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 42B3 42D3 42A4 IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 42A3 42A4 IN IN 57B1 57B1 42B4 IN 42B4 IN 57B1 57B1 C4586 1 2 0.22UF_6.3V_1 PEG_C_TX6_DN PEG_TX7_DN C4587 1 2 0.22UF_6.3V_1 PEG_C_TX7_DN PEG_TX8_DN C4588 1 2 0.22UF_6.3V_1 PEG_C_TX8_DN PEG_TX9_DN C4589 1 2 0.22UF_6.3V_1 PEG_C_TX9_DN PEG_TX10_DN C4590 1 2 0.22UF_6.3V_1 PEG_C_TX10_DN PEG_TX11_DN 57C1 57C1 42B4 IN 57C1 57C1 42B4 IN 57C1 57D1 42B4 IN 42B4 IN 42B4 IN 57D1 57D1 57D1 C4591 1 2 0.22UF_6.3V_1 PEG_C_TX11_DN PEG_TX12_DN C4592 1 2 0.22UF_6.3V_1 PEG_C_TX12_DN PEG_TX13_DN C4593 1 2 0.22UF_6.3V_1 PEG_C_TX13_DN PEG_TX14_DN C4594 1 2 0.22UF_6.3V_1 PEG_C_TX14_DN PEG_TX15_DN C4595 1 2 0.22UF_6.3V_1 PEG_C_TX15_DN PEG_TX0_DP 57D1 42B3 42C4 IN IN 42C3 42C3 42C4 IN 42C3 42C3 42C4 IN 42A4 IN 42C3 42C3 C4596 1 2 0.22UF_6.3V_1 PEG_C_TX0_DP PEG_TX1_DP C4597 1 2 0.22UF_6.3V_1 PEG_C_TX1_DP PEG_TX2_DP C4598 1 2 0.22UF_6.3V_1 PEG_C_TX2_DP PEG_TX3_DP C4599 1 2 0.22UF_6.3V_1 PEG_C_TX3_DP PEG_TX4_DP C4600 1 2 0.22UF_6.3V_1 PEG_C_TX4_DP PEG_TX5_DP 42C3 42C3 42A4 IN 42C3 42C3 42A4 IN 42C3 42D3 42A4 IN B 42D3 C4601 1 2 0.22UF_6.3V_1 PEG_C_TX5_DP PEG_TX6_DP C4602 1 2 0.22UF_6.3V_1 PEG_C_TX6_DP PEG_TX7_DP C4603 1 2 0.22UF_6.3V_1 PEG_C_TX7_DP PEG_TX8_DP C4604 1 2 0.22UF_6.3V_1 PEG_C_TX8_DP PEG_TX9_DP C4605 1 2 0.22UF_6.3V_1 PEG_C_TX9_DP PEG_TX10_DP 42A3 42A3 42A4 IN 42A3 42A3 42B4 IN 42A3 42B3 42B4 IN 42B3 42B3 42B4 IN 42B4 IN 42B3 42B3 C4606 1 2 0.22UF_6.3V_1 PEG_C_TX10_DP PEG_TX11_DP C4607 1 2 0.22UF_6.3V_1 PEG_C_TX11_DP PEG_TX12_DP C4608 1 2 0.22UF_6.3V_1 PEG_C_TX12_DP PEG_TX13_DP C4609 1 2 0.22UF_6.3V_1 PEG_C_TX13_DP PEG_TX14_DP C4610 1 2 0.22UF_6.3V_1 PEG_C_TX14_DP PEG_TX15_DP C4611 1 2 0.22UF_6.3V_1 PEG_C_TX15_DP 42B3 42B3 42B4 IN 42B3 42B3 42B4 IN 42B3 IN 42B4 IN 42B4 IN LOTES_ACA_ZIF_069_P01_989P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 C 57D1 42B4 eDP_TX#[3] PEG_TX0_DN 57C1 42B4 H29 P1V0S_VCCP_EDP_COMPIO 2 PEG_RX#[3] J35 DMI_RX#[3] R4521 - TYPICAL IMPEDANCE < 25 MOHMS L34 B24 E20 49C3 49C3 M35 PEG_RX#[2] DMI_TX3_DN G19 49C3 49C3 PEG_RX#[1] DMI_RX#[2] FDI_TX3_DP 49C3 IN K33 DMI_RX#[1] A25 FDI_TX2_DP 49C3 49C3 PEG_RX#[0] B25 DMI_TX2_DN FDI_TX1_DP 49D3 P1V05S OUT OUT OUT OUT OUT OUT OUT OUT - MAX LENGTH = 500 MILS DMI_TX1_DN FDI0_TX[0] 49D3 IN IN OUT OUT OUT OUT H22 A22 49D3 49C3 OUT OUT OUT OUT PEG_RCOMPO DMI_RX#[0] FDI_TX0_DP 49D3 49C3 OUT OUT OUT OUT J21 PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH PEG_ICOMPO B27 PCI EXPRESS* - GRAPHICS 49D6 J22 DMI_TX0_DN DMI 49D6 OUT OUT OUT OUT Intel(R) FDI 49D6 P1V0S_VCCP_PEG_ICOMPI PEG_ICOMPI 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 42 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4500~4699(CPU) SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR CN4500 CN4500 BI 39D5 M_A_DQ<63..0> SA_CLK[0] SA_CLK#[0] D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 B 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 38D8 38D8 38D8 A 38C8 38C8 38C8 OUT OUT OUT OUT OUT OUT M_A_DQ<0> M_A_DQ<1> M_A_DQ<2> M_A_DQ<3> M_A_DQ<4> M_A_DQ<5> M_A_DQ<6> M_A_DQ<7> M_A_DQ<8> M_A_DQ<9> M_A_DQ<10> M_A_DQ<11> M_A_DQ<12> M_A_DQ<13> M_A_DQ<14> M_A_DQ<15> M_A_DQ<16> M_A_DQ<17> M_A_DQ<18> M_A_DQ<19> M_A_DQ<20> M_A_DQ<21> M_A_DQ<22> M_A_DQ<23> M_A_DQ<24> M_A_DQ<25> M_A_DQ<26> M_A_DQ<27> M_A_DQ<28> M_A_DQ<29> M_A_DQ<30> M_A_DQ<31> M_A_DQ<32> M_A_DQ<33> M_A_DQ<34> M_A_DQ<35> M_A_DQ<36> M_A_DQ<37> M_A_DQ<38> M_A_DQ<39> M_A_DQ<40> M_A_DQ<41> M_A_DQ<42> M_A_DQ<43> M_A_DQ<44> M_A_DQ<45> M_A_DQ<46> M_A_DQ<47> M_A_DQ<48> M_A_DQ<49> M_A_DQ<50> M_A_DQ<51> M_A_DQ<52> M_A_DQ<53> M_A_DQ<54> M_A_DQ<55> M_A_DQ<56> M_A_DQ<57> M_A_DQ<58> M_A_DQ<59> M_A_DQ<60> M_A_DQ<61> M_A_DQ<62> M_A_DQ<63> M_A_BS0 M_A_BS1 M_A_BS2 AA6 V9 OUT OUT OUT 38C8 0 38C8 1 C5 SA_DQ[0] D5 SA_DQ[1] D3 3 SA_DQ[2] D2 4 SA_DQ[3] 5 SA_CKE[0] D6 SA_DQ[4] SA_CLK[1] AA5 C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR1_DP M_CLK_DDR1_DN M_CKE1 V10 OUT OUT OUT 38C8 2 38C8 6 38C8 7 C2 SA_DQ[6] C3 SA_DQ[7] 9 SA_DQ[8] 10 F10 F8 G10 G9 SA_CKE[1] 38C8 8 SA_DQ[9] SA_DQ[10] RSVD_TP[1] AB4 SA_DQ[11] RSVD_TP[2] AA4 RSVD_TP[3] W9 11 12 13 F9 SA_DQ[12] F7 SA_DQ[13] G8 15 SA_DQ[14] G7 16 SA_DQ[15] K4 SA_DQ[16] RSVD_TP[4] AB3 14 17 18 K5 SA_DQ[17] RSVD_TP[5] AA3 K1 SA_DQ[18] RSVD_TP[6] W10 J1 SA_DQ[19] J5 21 SA_DQ[20] J4 22 SA_DQ[21] 23 J2 K2 M8 N10 SA_CS#[0] SA_DQ[22] SA_CS#[1] SA_DQ[23] 19 20 M_CS#0 M_CS#1 AK3 AL3 SA_DQ[24] RSVD_TP[7] AG1 SA_DQ[25] RSVD_TP[8] AH1 OUT OUT 38D8 24 38C8 25 26 27 N8 SA_DQ[26] N7 28 SA_DQ[27] M10 29 SA_DQ[28] 30 M9 SA_DQ[29] SA_ODT[0] AH3 N9 SA_DQ[30] SA_ODT[1] AG3 M7 SA_DQ[31] RSVD_TP[9] AG2 AG6 SA_DQ[32] RSVD_TP[10] AH2 AG5 SA_DQ[33] AK6 SA_DQ[34] AK5 SA_DQ[35] AH5 SA_DQ[36] AH6 AJ5 SA_DQ[37] SA_DQ[38] AJ6 SA_DQ[39] AJ8 SA_DQ[40] AK8 SA_DQ[41] AJ9 SA_DQ[42] AK9 SA_DQ[43] DDR SYSTEM MEMORY A 0 M_CLK_DDR0_DP M_CLK_DDR0_DN M_CKE0 AB6 M_B_DQ<63..0> BI M_ODT0 M_ODT1 OUT OUT 38C8 31 38C8 32 33 34 35 36 37 SA_DQS#[0] SA_DQS#[1] C4 G6 M_A_DQS0_DN OUT OUT OUT OUT OUT OUT OUT OUT M_A_DQS1_DN SA_DQS#[2] J3 M_A_DQS2_DN SA_DQS#[3] M6 M_A_DQS3_DN SA_DQS#[4] AL6 M_A_DQS4_DN SA_DQS#[5] AM8 M_A_DQS5_DN SA_DQS#[6] 38 AR12M_A_DQS6_DN AM15M_A_DQS7_DN 38B8 39 38B8 40 38B8 41 38B8 42 38B8 43 38B8 44 38B8 45 AH8 SA_DQ[44] AH9 SA_DQ[45] AL9 47 SA_DQ[46] AL8 48 SA_DQ[47] AP11 49 SA_DQ[48] 50 SA_DQS#[7] AN11 SA_DQ[49] SA_DQS[0] D4 M_A_DQS0_DP AL12 SA_DQ[50] SA_DQS[1] F6 M_A_DQS1_DP M_A_DQS2_DP M_A_DQS3_DP AM12 SA_DQ[51] SA_DQS[2] K3 AM11 SA_DQ[52] SA_DQS[3] N6 AL11 SA_DQS[4] SA_DQ[53] OUT OUT OUT OUT OUT OUT OUT OUT AL5 M_A_DQS4_DP 38B8 46 38B8 51 38B8 52 38B8 53 38B8 54 38B8 55 AP12 SA_DQ[54] SA_DQS[5] AM9 M_A_DQS5_DP AN12 SA_DQ[55] SA_DQS[6] AR11M_A_DQS6_DP AJ14 SA_DQ[56] SA_DQS[7] AM14M_A_DQS7_DP AH14 SA_DQ[57] AL15 59 SA_DQ[58] AK15 60 SA_DQ[59] AL14 SA_DQ[60] SA_DQ[61] SA_MA[0] AD10 AJ15 SA_DQ[62] SA_MA[1] W1 AH15 SA_DQ[63] SA_MA[2] W2 SA_MA[3] W7 SA_MA[4] V3 SA_MA[5] V2 SA_MA[6] W3 AE10 SA_BS[0] SA_MA[7] W6 AF10 SA_BS[1] SA_MA[8] V1 SA_BS[2] SA_MA[9] W5 M_A_CAS# M_A_RAS# M_A_WE# SA_MA[10] AD8 SA_MA[11] V4 SA_MA[12] W4 SA_CAS# SA_MA[13] AF8 AD9 SA_RAS# SA_MA[14] V5 AF9 SA_WE# SA_MA[15] V7 AE8 M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15> 56 38B8 57 38B8 M_A_A<15..0> OUT AK14 V6 38B8 58 61 38D8 62 0 M_B_DQ<0> C9 M_B_DQ<1> A7 M_B_DQ<2> D10 M_B_DQ<3> C8 M_B_DQ<4> A9 M_B_DQ<5> A8 M_B_DQ<6> D9 M_B_DQ<7> D8 M_B_DQ<8> G4 M_B_DQ<9> F4 M_B_DQ<10> F1 M_B_DQ<11> G1 M_B_DQ<12> G5 M_B_DQ<13> F5 M_B_DQ<14> F2 G2 M_B_DQ<15> J7 M_B_DQ<16> J8 M_B_DQ<17> M_B_DQ<18> K10 K9 M_B_DQ<19> J9 M_B_DQ<20> M_B_DQ<21> J10 K8 M_B_DQ<22> K7 M_B_DQ<23> M5 M_B_DQ<24> N4 M_B_DQ<25> M_B_DQ<26> N2 M_B_DQ<27> N1 M_B_DQ<28> M4 M_B_DQ<29> N5 M_B_DQ<30> M2 M_B_DQ<31> M1 M_B_DQ<32> AM5 M_B_DQ<33> AM6 M_B_DQ<34> AR3 M_B_DQ<35> AP3 M_B_DQ<36> AN3 M_B_DQ<37> AN2 M_B_DQ<38> AN1 M_B_DQ<39> AP2 M_B_DQ<40> AP5 M_B_DQ<41> AN9 M_B_DQ<42> AT5 M_B_DQ<43> AT6 M_B_DQ<44> AP6 M_B_DQ<45> AN8 M_B_DQ<46> AR6 M_B_DQ<47> AR5 M_B_DQ<48> AR9 M_B_DQ<49>AJ11 M_B_DQ<50> AT8 M_B_DQ<51> AT9 M_B_DQ<52>AH11 M_B_DQ<53> AR8 M_B_DQ<54>AJ12 M_B_DQ<55>AH12 M_B_DQ<56>AT11 M_B_DQ<57>AN14 M_B_DQ<58>AR14 M_B_DQ<59>AT14 M_B_DQ<60>AT12 M_B_DQ<61>AN15 M_B_DQ<62>AR15 M_B_DQ<63>AT15 SB_CLK[0] AE2 SB_CLK#[0] AD2 SB_CKE[0] R9 SB_DQ[4] SB_CLK[1] AE1 SB_DQ[5] SB_CLK#[1] AD1 SB_DQ[0] R10 SB_CKE[1] SB_DQ[6] SB_DQ[10] RSVD_TP[11] AB2 SB_DQ[11] RSVD_TP[12] AA2 SB_DQ[12] RSVD_TP[13] T9 SB_DQ[16] RSVD_TP[14] AA1 SB_DQ[17] RSVD_TP[15] AB1 SB_DQ[18] RSVD_TP[16] T10 SB_DQ[14] SB_DQ[15] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_CS#[0] AD3 SB_DQ[23] SB_CS#[1] AE3 SB_DQ[24] RSVD_TP[17] AD6 SB_DQ[25] RSVD_TP[18] AE6 SB_DQ[29] SB_ODT[0] AE4 SB_DQ[30] SB_ODT[1] AD4 SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] RSVD_TP[19] AD5 RSVD_TP[20] AE5 D7 M_B_DQS0_DN F3 M_B_DQS1_DN SB_DQS#[2] K6 M_B_DQS2_DN SB_DQS#[3] N3 M_B_DQS3_DN SB_DQS#[4] AN5 M_B_DQS4_DN SB_DQS#[5] AP9 M_B_DQS5_DN SB_DQ[43] SB_DQS#[6] AK12 M_B_DQS6_DN SB_DQ[44] SB_DQS#[7] AP15 M_B_DQS7_DN SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] 13 14 39C8 39C8 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 39B8 OUT OUT OUT OUT OUT OUT OUT OUT 39B8 39B8 39B8 39B8 39B8 39B8 39B8 39B8 B SB_DQ[48] SB_DQ[49] SB_DQS[0] C7 M_B_DQS0_DP SB_DQ[50] SB_DQS[1] G3 M_B_DQS1_DP SB_DQ[51] SB_DQS[2] J6 M_B_DQS2_DP SB_DQ[52] SB_DQS[3] M3 M_B_DQS3_DP SB_DQ[53] SB_DQS[4] AN6 M_B_DQS4_DP SB_DQ[54] SB_DQS[5] AP8 M_B_DQS5_DP SB_DQ[55] SB_DQS[6] AK11 M_B_DQS6_DP SB_DQ[56] SB_DQS[7] AP14 M_B_DQS7_DP 39B8 39B8 39B8 39B8 39B8 39B8 39B8 SB_DQ[57] SB_DQ[58] SB_DQ[59] M_B_A<15..0> SB_DQ[60] SB_MA[0] AA8 SB_DQ[62] SB_MA[1] T7 SB_DQ[63] SB_DQ[61] SB_BS[0] SB_MA[7] R2 AA7 SB_BS[1] SB_MA[8] T5 R6 SB_BS[2] SB_MA[9] R3 10 12 39C8 SB_DQ[47] AA9 SB_MA[10] AB7 SB_MA[11] R1 SB_MA[12] T1 SB_CAS# SB_MA[13] AB10 AB8 SB_RAS# SB_MA[14] R5 AB9 SB_WE# SB_MA[15] R4 AA10 39C8 SB_DQ[46] 9 M_B_CAS# M_B_RAS# M_B_WE# OUT OUT SB_DQ[45] SB_MA[6] 39C8 M_ODT2 M_ODT3 SB_DQS#[1] SB_DQ[38] T3 11 39C8 C SB_DQS#[0] SB_DQ[37] T4 39C8 39C8 SB_DQ[28] SB_MA[5] 8 OUT OUT SB_DQ[27] 4 7 M_CS#2 M_CS#3 SB_DQ[26] T2 OUT OUT OUT 39C8 SB_DQ[13] SB_MA[4] 39D8 39C8 SB_DQ[9] 3 39D8 M_CLK_DDR3_DP M_CLK_DDR3_DN M_CKE3 SB_DQ[8] T6 6 39C8 39C8 SB_DQ[7] R7 M_B_BS0 M_B_BS1 M_B_BS2 OUT OUT OUT 39C8 D SB_MA[3] 5 39C8 SB_DQ[3] SB_MA[2] 63 OUT OUT OUT SB_DQ[2] 2 1 M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2 SB_DQ[1] DDR SYSTEM MEMORY B 38D5 M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15> 0 OUT 1 2 3 4 5 6 7 8 9 10 11 A 12 13 14 15 15 INVENTEC LOTES_ACA_ZIF_069_P01_989P LOTES_ACA_ZIF_069_P01_989P TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 43 REV X01 68 of 1 8 7 6 5 4 3 2 1 F F POWER CN4500 REFERENCE 4500~4699(CPU) PVCORE F14 VCC21 VCCIO20 F13 AD34 VCC22 VCCIO21 F12 AD33 VCC23 VCCIO22 F11 AD32 VCC24 VCCIO23 E14 AD31 VCC25 VCCIO24 E12 AD30 VCC26 AD29 VCC27 VCCIO25 E11 AD28 VCC28 VCCIO26 D14 AD27 VCC29 VCCIO27 D13 AD26 VCC30 VCCIO28 D12 AC35 VCC31 VCCIO29 D11 AC34 VCC32 VCCIO30 C14 AC33 VCC33 VCCIO31 C13 AC32 VCC34 VCCIO32 C12 AC31 VCC35 VCCIO33 C11 AC30 VCC36 VCCIO34 B14 AC29 VCC37 VCCIO35 B12 AC28 VCC38 VCCIO36 A14 AC27 VCC39 VCCIO37 A13 AC26 VCC40 VCCIO38 A12 AA35 VCC41 VCCIO39 A11 AA34 VCC42 AA33 VCC43 VCCIO40 J23 AA32 VCC44 AA31 VCC45 AA30 VCC46 AA29 VCC47 AA28 VCC48 AA27 VCC49 AA26 VCC50 Y35 VCC51 Y34 VCC52 Y33 VCC53 Y32 VCC54 Y31 VCC55 Y30 VCC56 Y29 VCC57 Y28 VCC58 Y27 VCC59 Y26 VCC60 V35 VCC61 V34 VCC62 V33 VCC63 V32 VCC64 V31 VCC65 V30 VCC66 V29 VCC67 V28 VCC68 V27 VCC69 V26 VCC70 U35 VCC71 U34 VCC72 U33 VCC73 U32 VCC74 U31 VCC75 U30 VCC76 U29 VCC77 U28 VCC78 U27 VCC79 U26 VCC80 R35 VCC81 R34 VCC82 R33 VCC83 R32 VCC84 R31 VCC85 R30 VCC86 R29 VCC87 R28 VCC88 R27 VCC89 R26 VCC90 P35 VCC91 P34 VCC92 P33 VCC93 P32 VCC94 P31 VCC95 P30 VCC96 P29 VCC97 P28 VCC98 P27 VCC99 P26 VCC100 1 VCCIO19 22UF_6.3V_5 VCC20 AD35 C4540 G12 AF26 2 VCCIO18 1 VCC19 22UF_6.3V_5 G13 AF27 C4541 VCCIO17 2 VCC18 1 G14 AF28 22UF_6.3V_5 H11 VCCIO16 C4542 VCCIO15 VCC17 2 H12 VCC16 AF29 22UF_6.3V_5 VCCIO14 1 VCC15 AF30 C4537 H14 AF31 2 VCCIO13 1 VCC14 22UF_6.3V_5 J11 AF32 C4536 VCCIO12 2 VCC13 1 J12 AF33 22UF_6.3V_5 J13 VCCIO11 C4535 VCCIO10 VCC12 2 J14 VCC11 AF34 1 VCCIO9 22UF_6.3V_5 VCC10 AF35 C4534 L10 AG26 2 VCCIO8 22UF_6.3V_5 VCC9 1 P10 AG27 C4533 VCCIO7 2 VCC8 1 U10 AG28 22UF_6.3V_5 Y10 VCCIO6 C4532 VCCIO5 VCC7 2 AC10 VCC6 AG29 1 VCCIO4 C4531 VCC5 AG30 2 AG10 AG31 22UF_6.3V_5 VCCIO3 D P1V05S 1 1 PLACE CLOSE TO CPU C 2 R4527 75_5%_2 2 R4528 130_1%_2 SVID SIGNAL TO VR VIDALERT# AJ29 VIDSCLK AJ30 VIDSOUT AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT R4529 1 243_5%_2 R4530 1 R4531 1 2 0_5%_2 2 0_5%_2 VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA OUT OUT OUT 11C7 11A3 11C7 11A3 11C7 1 PVCORE R4532 100_1%_2 2 VCCSENSE VSSSENSE OUT OUT 11D6 11D6 R4533 100_1%_2 B 1 P1V05S VCC_SENSE AJ35 VSS_SENSE AJ34 R4534 2 10_1%_2 VCCIO_SENSE B10 VSSIO_SENSE A10 VCC_SENSE_VCCIO VSS_SENSE_VCCIO 1 1 2 1 VCC4 OUT OUT 9B7 9B7 R4535 10_1%_2 2 B AH10 AG32 1 C 2 22UF_6.3V_5 2 22UF_6.3V_5 2 22UF_6.3V_5 C4525 AH13 VCCIO2 2 C4524 VCCIO1 VCC3 PEG AND DDR 2 1 22UF_6.3V_5 2 2 C4523 2 C4521 22UF_6.3V_5 1 1 C4522 22UF_6.3V_5 C4520 22UF_6.3V_5 2 22UF_6.3V_5 C4519 1 C4518 1 1 D VCC2 AG33 SVID 1 2 1 22UF_6.3V_5 22UF_6.3V_5 2 22UF_6.3V_5 C4517 VCC1 AG34 SENSE LINES C4516 2 C4515 2 22UF_6.3V_5 1 2 22UF_6.3V_5 1 2 1 C4514 C4513 E P1V05S AG35 CORE SUPPLY C4512 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 1 C4511 2 C4510 1 1 E A A INVENTEC LOTES_ACA_ZIF_069_P01_989P TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 44 1 REV X01 of 68 8 7 6 4 5 3 2 1 PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT: ROUTE WITH MIN. TRACE WIDTH OF 10 MILS P0V75M_VREF P0V75M_VREF P0V75M_VREF_H P0V75M_VREF IN CPUDDR_WR_VREF2 2 3 S 46C4 3 2 2 3 D D S G AM2302N Q4500 45D8 45D6 41A8 IN DRAMRST_CNTRL IN DRAMRST_CNTRL AM2302N R4541 100K_5%_2 2 D 41A8 1 1 1 G Q4501 AM2302N 1 Q4502 G CPUDDR_WR_VREF1 D IN S 46C4 D R4538 49A1 21D6 14D2 IN SLP_S3#_3R 1 2 1 1 POWER 0_5%_2 14A6 13A2 13D2 14B8 PVAXG PVAXG R4539 CN4500 VAXG28 AM18 VAXG29 AM17 VAXG30 AL24 VAXG31 AL23 VAXG32 AL21 AL20 AL18 B VDDQ3 AF1 VDDQ4 AC7 VDDQ5 AC4 VDDQ6 AC1 VDDQ7 Y7 VDDQ8 Y4 VAXG33 VDDQ9 Y1 VAXG34 VDDQ10 U7 VAXG35 VDDQ11 U4 AL17 VAXG36 VDDQ12 U1 AK24 VAXG37 VDDQ13 P7 AK23 VAXG38 VDDQ14 P4 AK21 VAXG39 VDDQ15 P1 AK20 VAXG40 AK18 VAXG41 AK17 VAXG42 AJ24 VAXG43 AJ23 VAXG44 AJ21 VAXG45 AJ20 VAXG46 AJ18 VAXG47 AJ17 VAXG48 AH24 VAXG49 AH23 VAXG50 AH21 VAXG51 AH20 VAXG52 AH18 VAXG53 AH17 VAXG54 DDR3 -1.5V RAILS AF4 2 5A 1 VAXG27 AM20 AF7 VDDQ2 + AM21 VDDQ1 C4567 C4568 C4569 10UF_6.3V_3 10UF_6.3V_3 C4570 10UF_6.3V_3 C4571 10UF_6.3V_3 10UF_6.3V_3 C4572 C4573 220UF_2.5V 10UF_6.3V_3 2 VAXG26 1 VAXG25 AM23 2 VAXG24 AM24 P1V5S 1 VAXG23 AN17 2 AN18 NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE B PVSA VCCSA1 M27 VCCSA2 M26 VCCSA3 L26 VCCSA4 J26 VCCSA5 J25 VCCSA6 J24 VCCSA7 H26 VCCSA8 H25 1 VAXG22 + VAXG21 AN20 C4574 PVSA C4575 C4577 C4576 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 100UF_6.3V 2 VAXG20 AN21 1 VAXG19 AN23 2 VAXG18 AN24 1 VAXG17 AP17 2 VAXG16 AP18 1 VAXG15 AP20 C AL1 2 AP21 SM_VREF 1 VAXG14 2 VAXG13 AP23 1 VAXG12 AP24 P0V75M_VREF_H 2 AR17 C 2 VAXG11 1 VAXG10 AR18 2 VAXG9 AR20 R4540 1 VAXG8 AR21 11B8 2 22UF_6.3V_5 22UF_6.3V_5 AR23 470PF_50V_2 10_1%_2 SA RAIL 22UF_6.3V_5 C4550 AK34 GFX_VSS_SENSE 1 VAXG7 C4549 VSSAXG_SENSE C4578 11B8 OUT OUT 2 VAXG6 AR24 C4548 AK35 GFX_VCC_SENSE 1 VAXG5 AT17 SENSE LINES VAXG4 AT18 VAXG_SENSE VREF VAXG3 AT20 GRAPHICS VAXG2 AT21 1 AT23 2 22UF_6.3V_5 VAXG1 2 22UF_6.3V_5 AT24 1 1 C4547 2 22UF_6.3V_5 2 2 22UF_6.3V_5 C4546 2 C4545 2 C4651 1 1 1 1 10_1%_2 A A VCCPLL2 A2 VCCPLL3 VCCSA_SENSE H23 VCCSA_SENSE FC_C22 C22 VCCSA_VID0 VCCSA_VID1 VCCSA_VID1 C24 1 22UF_6.3V_5 OUT 10C4 OUT OUT 10B4 INVENTEC 10B4 1 1 1UF_6.3V_2 VCCPLL1 A6 C4565 C4564 2 10UF_6.3V_3 1UF_6.3V_2 B6 2 C4563 2 2 C4562 1 1 1 MPZ1608S221AT P1V8S_VCCPLL 2 1.2A 2 100_5%_2 MISC L4500 1 1.8V RAIL R4544 P1V8S R4556 R4547 1K_5%_2 1K_5%_2 R4547 TITLE 2 2 LOTES_ACA_ZIF_069_P01_989P MODEL,PROJECT,FUNCTION SNB:0 OHM Block Diagram IVB:1K OHM SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 45 REV X01 68 of 1 8 7 6 4 5 3 CN4500 2 1 CN4500 CN4500 AT35 VSS1 VSS81 AJ22 T35 VSS161 VSS234 F22 AT32 VSS2 VSS82 AJ19 T34 VSS162 VSS235 F19 AT29 VSS3 VSS83 AJ16 T33 VSS163 VSS236 E30 AT27 VSS4 VSS84 AJ13 T32 VSS164 VSS237 E27 VSS85 AJ10 T31 VSS238 E24 T30 46A6 AT25 VSS5 VSS6 VSS86 AJ7 VSS166 VSS239 E21 AT19 VSS7 VSS87 AJ4 T29 VSS167 VSS240 E18 46A6 AT16 VSS8 VSS88 AJ3 T28 VSS168 VSS241 E15 46A6 AT13 VSS9 VSS89 AJ2 T27 VSS169 VSS242 E13 46A6 VSS90 AJ1 T26 VSS243 E10 P9 VSS10 VSS11 VSS91 AH35 VSS171 VSS244 E9 AT4 VSS12 VSS92 AH34 P8 VSS172 VSS245 E8 AT3 VSS13 VSS93 AH32 P6 VSS173 VSS246 E7 AR25 VSS14 VSS94 AH30 P5 VSS174 VSS247 E6 VSS95 AH29 P3 VSS248 E5 P2 VSS176 VSS249 E4 AR22 VSS15 VSS175 AR19 VSS16 VSS96 AH28 AR16 VSS17 VSS97 AH26 N35 VSS177 VSS250 E3 AR13 VSS18 VSS98 AH25 N34 VSS178 VSS251 E2 AR10 VSS19 VSS99 AH22 N33 VSS179 VSS252 E1 N32 CFG<0> CFG<1> CFG<2> CFG<3> CFG<4> CFG<5> CFG<6> CFG<7> CFG<8> CFG<9> CFG<10> CFG<11> CFG<12> CFG<13> CFG<14> CFG<15> CFG<16> CFG<17> L7 RSVD29 AG7 AK28 CFG[0] RSVD30 AE7 AK29 CFG[1] RSVD31 AK2 AL26 CFG[2] RSVD32 W8 AL27 CFG[3] AK26 CFG[4] AL29 CFG[5] RSVD33 AT26 AL30 CFG[6] RSVD34 AM33 AM31 CFG[7] RSVD35 AJ27 AM32 CFG[8] AM30 CFG[9] AM28 CFG[10] AM26 CFG[11] AN28 CFG[12] AN31 CFG[13] RSVD37 T8 AN26 CFG[14] RSVD38 J16 AM27 CFG[15] RSVD39 H16 AK31 CFG[16] RSVD40 G16 AN29 CFG[17] VSS20 VSS100 AH19 VSS180 VSS253 D35 AR4 VSS21 VSS101 AH16 N31 VSS181 VSS254 D32 AR2 VSS22 VSS102 AH7 N30 VSS182 VSS255 D29 AP34 VSS23 VSS103 AH4 N29 VSS183 VSS256 D26 RSVD41 AR35 AP31 VSS24 VSS104 AG9 N28 VSS184 VSS257 D20 AJ31 VAXG_VAL_SENSE RSVD42 AT34 VSS105 AG8 N27 VSS258 D17 AH31 VSSAXG_VAL_SENSE RSVD43 AT33 N26 VSS186 VSS259 C34 AJ33 VCC_VAL_SENSE RSVD44 AP35 AH33 VSS_VAL_SENSE RSVD45 AR34 AJ26 RSVD5 RSVD46 B34 RSVD47 A33 RSVD48 A34 RSVD49 B35 RSVD50 C35 VSS25 VSS185 AP25 VSS26 VSS106 AG4 AP22 VSS27 VSS107 AF6 M34 VSS187 VSS260 C31 AP19 VSS28 VSS108 AF5 L33 VSS188 VSS261 C28 AP16 VSS29 VSS109 AF3 L30 VSS189 VSS262 C27 AP13 VSS30 VSS110 AF2 L27 VSS190 VSS263 C25 VSS31 VSS111 AE35 L9 VSS191 VSS264 C23 AP7 VSS32 VSS112 AE34 L8 VSS192 VSS265 C10 AP4 VSS33 VSS113 AE33 L6 VSS193 VSS266 C1 AP1 VSS34 VSS114 AE32 L5 VSS194 VSS267 B22 VSS115 AE31 L4 VSS268 B19 VSS116 AE30 L3 VSS196 VSS269 B17 VSS117 AE29 L2 VSS197 VSS270 B15 AN30 VSS35 VSS_1 VSS195 45D8 45D6 CPUDDR_WR_VREF1 CPUDDR_WR_VREF2 IN IN B4 RSVD6 D1 RSVD7 AN27 VSS36 AN25 VSS37 AN22 VSS38 VSS118 AE28 L1 VSS198 VSS271 B13 AN19 VSS39 VSS119 AE27 K35 VSS199 VSS272 B11 F25 RSVD8 K32 F24 RSVD9 VSS RESERVED AR7 AP10 VSS40 VSS120 AE26 VSS200 VSS273 B9 AN13 VSS41 VSS121 AE9 K29 VSS201 VSS274 B8 F23 RSVD10 AN10 VSS42 VSS122 AD7 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32 AN7 VSS43 VSS123 AC9 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32 AN4 VSS44 VSS124 AC8 J31 VSS204 VSS277 B3 G24 RSVD13 H33 E23 RSVD14 AM29 VSS45 VSS125 AC6 VSS205 VSS278 B2 AM25 VSS46 VSS126 AC5 H30 VSS206 VSS279 A35 D23 RSVD15 AM22 VSS47 VSS127 AC3 H27 VSS207 VSS280 A32 C30 RSVD16 AM19 VSS48 VSS128 AC2 H24 VSS208 VSS281 A29 A31 RSVD17 AM16 VSS49 VSS129 AB35 H21 VSS209 VSS282 A26 B30 RSVD18 AM13 VSS50 VSS130 AB34 H18 VSS210 VSS283 A23 B29 RSVD19 VSS51 VSS131 AB33 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 AM7 VSS52 VSS132 AB32 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD55 AM35 AM4 VSS53 VSS133 AB31 H10 VSS213 A30 RSVD22 AM3 VSS54 VSS134 AB30 H9 VSS214 C29 RSVD23 AM2 VSS55 VSS135 AB29 H8 VSS215 AM1 VSS56 VSS136 AB28 H7 VSS216 AL34 VSS57 VSS137 AB27 H6 VSS217 J20 RSVD24 AL31 VSS58 VSS138 AB26 H5 VSS218 B18 RSVD25 RSVD56 AT2 AL28 VSS59 VSS139 Y9 H4 VSS219 A19 VCCIO_SEL RSVD57 AT1 VSS140 Y8 H3 VSS220 RSVD58 AR1 H2 VSS221 AL19 VSS62 VSS142 Y5 H1 VSS222 AL16 VSS63 VSS143 Y3 G35 VSS223 AL13 VSS64 VSS144 Y2 G32 VSS224 VSS145 W35 G29 VSS225 G26 VSS226 AL10 VSS65 AL7 VSS66 VSS146 W34 AL4 VSS67 VSS147 W33 G23 VSS227 AL2 VSS68 VSS148 W32 G20 VSS228 AK33 VSS69 VSS149 W31 G17 VSS229 VSS150 W30 G11 VSS230 F34 VSS231 AK30 VSS70 AK27 VSS71 VSS151 W29 AK25 VSS72 VSS152 W28 F31 VSS232 AK22 VSS73 VSS153 W27 F29 VSS233 AK19 VSS74 VSS154 W26 AK16 VSS75 VSS155 U9 AK13 VSS76 VSS156 U8 AK10 VSS77 VSS157 U6 AK7 VSS78 VSS158 U5 AK4 VSS79 VSS159 U3 VSS80 VSS160 U2 AJ25 10K_5%_2_DY VSS141 2 VSS61 Y6 VCCIO_SEL OUT J15 R4555 VSS60 AL22 9C7 1 AL25 D C AN16 AM10 B VSS170 AT7 AP28 C 46A6 AT22 AT10 D VSS165 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT RSVD28 AH27 VCC_DIE_SENSE REMOVE CLK_XDP_CLKGEN_DP CLK_XDP_CLKGEN_DN B RSVD27 B1 KEY LOTES_ACA_ZIF_069_P01_989P PEG STATIC LANE REVERSAL CFG(2) 1 : (DEFAULT) NORMAL OPERATION 0 : LANE REVERSED LOW EDP ENABLE LOTES_ACA_ZIF_069_P01_989P A A 1 : (DEFAULT) EDP DISABLED LOTES_ACA_ZIF_069_P01_989P IN PEG STATIC LAN REVERSAL LOW EDP ENABLE CFG<2> 1 R4550 2 1K_1%_2 46D4 IN CFG<4> 1 R4551 46D4 IN CFG<5> 1 IN PCIE PORT BIFURCATION PEG DEFER TRAINING 1 R4553 2 1K_1%_2_DY 46D4 IN CFG<7> 1 R4554 1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION CFG(7) 0 : PEG WAIT FOR BIOS FOR TRAINING 2 1K_1%_2_DY CFG<6> 0 : EDP ENABLED PEG DEFER TRAINING 2 1K_1%_2_DY R4552 CFG(4) 2 1K_1%_2_DY PCIE PORT BIFURCATION STRAPS INVENTEC 11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED 10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED CHANGE by 7 6 MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 STRAP PIN 8 TITLE CFG[6:5] 01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED) 00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 46 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4700~4949(PCH) P3V3A P3V3AL 1 R4736 2 2 0_5%_2_DY 1 P3V3_RTC 2 2 1 RTCRST# G22 SRTCRST# 2 2 K22 INTRUDER# C17 INTVRMEN BI BI HDA_3S_BITCLK 1 HDA_3S_SYNC 1 R4711 R4709 2 HDA_3S_BITCLK_R N34 33_5%_2 HDA_3S_SYNC_R 2 L34 T10 PCSPKR_PCH_3(NO REBOOT) 1 : NO REBOOT ENABLED 0 : (DEFAULT) NO REBOOT DISABLED 24B2 HDA_SYNC HDA_3S_RST# OUT 1 R4712 2 HDA_3S_RST#_R K34 STRAPPING SPKR HDA_RST# HDA_3S_SDIN0 IN STRAP 1:ENABLE 0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)P3V3A HDA_SDIN1 C34 47B8 IN 21D3 HDA_SDIN0 G34 FLASH_OVERRIDE R4715 1 A34 2 HDA_SDIN2 HDA_SDIN3 1K_5%_2 24A2 OUT B HDA_3S_SDOUT R4716 1 A36 2 33_5%_2 HDA_SDO SATA FLASH OVERRIDE FLASH DESCRIPTOR SECURITY OVERIDE E34 IHDA 33_5%_2 24A2 STRAPPING 2 C36 HDA_DOCK_EN#/GPIO33 N32 HDA_DOCK_RST#/GPIO13 10K_5%_2_DY IN EC_SMI R4718 1 2 2 RSC_0402_DY 1K_5%_2 47D3 HDA_3S_SYNC_R(PLL ODVR VOLTAGE) 1 : VCC VRM = 1.6V 0 : VCC VRM = 1.8V(DEFAULT) OUT OUT 47D3 OUT 47D3 OUT TP4720 1 PCH_TCK J3 TP4721 PCH_TMS H7 JTAG_TMS TP4722 PCH_TDI K5 JTAG_TDI TP4723 PCH_TDO H1 JTAG_TDO JTAG_TCK TP30 1 TP30 1 JTAG OUT 1 FWH4/LFRAME# D36 LPC_3S_FRAME# SERIRQ HDA_BCLK 33_5%_2 HDA_3S_SYNC_R FWH3/LAD3 C37 LPC_3S_AD<0> LPC_3S_AD<1> LPC_3S_AD<2> LPC_3S_AD<3> BI BI BI BI 21E3 27C3 21E3 27C3 21E3 27C3 21E3 27C3 P3V3S 21E3 OUT 27C3 E36 R4744 K36 10K_5%_2 2 24A2 PCSPKR_PCH_3 R4714 FWH2/LAD2 B37 PCI_3S_SERIRQ V5 21E3 BI 27B7 C STRAPPING 24B2 1 R4720 A38 LDRQ1#/GPIO23 SATA 6G INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE 1:ENABLE INTERNAL VRS 0:ENABLE EXTERNAL VRS OUT 1 2 D20 C38 FWH1/LAD1 2 C FLASH_OVERRIDE 2 RTCX2 FWH0/LAD0 LDRQ0# 0_5%_2_DY 1 R4743 RSC_0402_DY 1 RTCX1 RTC C4702 1 R4705 C20 R4707 R4706 R4741 RSC_0402_DY RSC_0402_DY U4700 A20 330K_5%_3 21D3 47B7 2 18PF_50V_2 2 1 1 2 2 P3V3_RTC 2 - CN4700 LOTES_AAA_BAT_063_P02_A_2P 1M_5%_2 1 C4700 + 1 TP30 1UF_6.3V_2 2 1 2 C4704 RTCX1 R4739 TP4705 1UF_6.3V_2 1K_5%_2 D 1 1UF_6.3V_2 1 2 47A6 2 20K_1%_2 1 R4700 47B6 R4742 RSC_0402_DY 1 32.768KHZ R4740 RSC_0402_DY RSC_0402_DY PCH_TDI PCH_TMS PCH_TDO OUT OUT OUT 2 1 10M_5%_2 C4701 R4704 47A6 LPC C A1 X4700 2 R4738 R4708 1 2 1 1 4 1 3 R4703 20K_1%_2 1 OUT 2 18PF_50V_2 BAT54C_30V_0.2A 24B1 1 1 P3V3_RTC D4700 D 2 RSC_0402_DY C4703 RTCX2 3 R4737 1 A2 P1V05S SATA0RXN AM3 SATA0RXP AM1 SATA0TXN AP7 SATA0TXP AP5 SATA1RXN AM10 SATA1RXP AM8 SATA1TXN AP11 SATA1TXP AP10 SATA2RXN AD7 SATA2RXP AD5 SATA2TXN AH5 SATA2TXP AH4 SATA3RXN AB8 SATA3RXP AB10 SATA3TXN AF3 SATA3TXP AF1 SATA4RXN Y7 SATA4RXP Y5 SATA4TXN AD3 SATA4TXP AD1 SATA5RXN Y3 SATA5RXP Y1 SATA5TXN AB3 SATA5TXP AB1 SATAICOMPO Y11 SATAICOMPI Y10 SATA_HDD_RX_DN SATA_HDD_RX_DP SATA_HDD_TX_DN SATA_HDD_TX_DP IN IN OUT OUT SATA_MINICARD_RX_DN SATA_MINICARD_RX_DP SATA_MINICARD_TX_DN SATA_MINICARD_TX_DP IN IN OUT OUT 29D5 29D5 29D5 28C7 28C7 28C7 28C7 B SATA_ODD_RX_DN SATA_ODD_RX_DP SATA_ODD_TX_DN SATA_ODD_TX_DP 29A7 IN IN OUT OUT 29A7 29A7 29A7 P1V05S R4747 P1V05S_SATARCOMPO 1 TP30 1 29D5 2 37.4_1%_2 TP30 SATA3RCOMPO AB12 SATA3COMPI AB13 SATA3RBIAS AH1 1 P1V05S P1V05S_SATA3RCOMPO 1 R4748 P3V3S 2 21C8 OUT A SPI_CLK EC_SPI_CS0# Y14 SPI_CS0# EC_SPI_CS1# T1 SPI_CS1# SATALED# 21C7 21C6 OUT OUT EC_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 EC_SPI_SO U3 SPI_MISO SATA1GP/GPIO19 STRAPPING 2 21C8 21C6 R4750 R4751 750_1%_2 10K_5%_2 R4752 10K_5%_2 10K_5%_2 2 OUT OUT 2 2 21C8 R4749 2 21C7 21D6 SPI 21D6 T3 1 1 1 49.9_1%_2 EC_SPI_CLK A P3 V14 P1 ITL_PANTHERPOINT_FCBGA_989P R4734 RSC_0402_DY 1 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 47 REV X01 68 of 1 6 4 5 3 2 SMB_ALERT# REFERENCE 4700~4949(PCH) C4724 2 0.1UF_16V_2 27B7 27B7 PCIE_WLAN_RX_DN PCIE_WLAN_RX_DP PCIE_WLAN_TX_DN PCIE_WLAN_TX_DP IN IN OUT OUT 0.1UF_16V_2 2 0.1UF_16V_2 31C7 31C7 31C7 D 31C7 PCIE_USB3_RX_DN PCIE_USB3_RX_DP PCIE_USB3_TX_DN PCIE_USB3_TX_DP IN IN OUT OUT 2 CLKREQ_LAN# 1 R4775 2 2 0.1UF_16V_2 P3V3A OUT BB32 PETN2 AY32 PETP2 CLKREQ_LAN# 1 R4773 BG36 PERN3 BJ36 PERP3 AV34 PETN3 AU34 PETP3 BF36 PERN4 BE36 PERP4 AY34 PETN4 BB34 PETP4 2 PERN5 BH37 PERP5 AY36 PETN5 BB36 PETP5 BJ38 PERN6 BG38 PERP6 AU36 PETN6 CLOCK TERMINATION FOR FICM AV36 PETP6 STUFF FOR INTEGRATED CLK BG40 PERN7 BJ40 PERP7 AY40 PETN7 BB40 PETP7 CLKREQ_WLAN# 1 R4776 10K_5%_2 P3V3S 2 48D8 27C7 48B7 10K_5%_2_DY OUT CLKREQ_WLAN# 1 R4772 2 2 2 10K_5%_2 IN CLKIN_BUF_DOT96_DN 1 22C2 22C2 48D8 22C5 48D7 R4780 48B3 IN CLKIN_BUF_DOT96_DP A12 DRAMRST_CNTRL_PCH SML0CLK C8 PCH_3A_ALERT_CLK SML0DATA G12 PCH_3A_ALERT_DAT OUT 41A8 OUT 27B3 48D3 27B3 48D2 27B3 OUT 1 2 CLK_PCIE_LAN_DN CLK_PCIE_LAN_DP OUT OUT CLKREQ_LAN# IN PCH_3A_ALERT_CLK IN R4799 1 48D2 48D3 27B3 PCH_3A_ALERT_DAT IN R4800 1 C13 SML1ALERT# SML1CLK/GPIO58 E14 SML1_CLK SML1DATA/GPIO75 M16 SML1ALERT#/PCHHOT#/GPIO74 IN 48D2 OUT 48D2 OUT 48C2 48D3 SML1_CLK BI P3V3A SML1_DATA CL_CLK1 M7 CL_DATA1 T11 PERN8 BC38 PERP8 AW38 PETN8 AY38 PETP8 Y40 CLKOUT_PCIE0N Y39 CLKOUT_PCIE0P SSM3K7002FU_DY EC_SMB3_CLK SML1_DATA BI Q4703 CL_RST1# P10 P3V3A R4753 48C3 CLKREQ_GPU# OUT 1 2 SSM3K7002FU_DY EC_SMB3_DATA BI 10K_5%_2 M10 CLKREQ_GPU# PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_N AB37 CLKOUT_PEG_A_P AB38 CLK_PEG_REF_DN CLK_PEG_REF_DP OUT 48C3 OUT OUT 57B6 C 57B6 XTAL25_OUT CLKREQ_WLAN# IN AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 M1 CLKIN_SATA1_DP 1 2 31C7 10K_5%_2 R4783 48B3 IN CLKIN_SATA1_DN 1 2 31C7 OUT OUT 31B8 31C7 IN CLK_PCIE_USB3_DN CLK_PCIE_USB3_DP CLKREQ_USB3# AA48 CLKOUT_PCIE2N AA47 CLKOUT_PCIE2P V10 PCIECLKRQ2#/GPIO20 10K_5%_2 B TP4703 P3V3A TP4704 TP24 1 TP24 1 Y37 CLKOUT_PCIE3N Y36 CLKOUT_PCIE3P CLKOUT_DP_N AM12 CLKOUT_DP_P AM13 CLKIN_DMI_N BF18 CLKIN_DMI_P BE18 Y43 CLKOUT_PCIE4N Y45 CLKOUT_PCIE4P 1 R4785 R4787 2.2K_5%_2 CLKIN_GND1_N BJ30 CLKIN_GND1_P BG30 1 PCIECLKRQ4#/GPIO26 V45 CLKOUT_PCIE5N V46 CLKOUT_PCIE5P L14 2 Q4700 CLKIN_DOT_96N G24 CLKIN_DOT_96P E24 CLKIN_SATA_N AK7 CLKIN_SATA_P AK5 REFCLK14IN CLKIN_BUF_DOT96_DN CLKIN_BUF_DOT96_DP CLKIN_SATA1_DN CLKIN_SATA1_DP K45 CLKIN_PCH14 CLKIN_PCILOOPBACK H45 CLKIN_PCI_FB CLKOUT_PEG_B_N XTAL25_IN V47 AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 XTAL25_IN XTAL25_OUT XCLK_RCOMP D 1 SSM3K7002BFU 2 V40 CLKOUT_PCIE6N V42 CLKOUT_PCIE6P Y47 48B8 48B8 IN 48B8 IN 51A7 OUT OUT 48B1 IN SMB_ALERT# 1 B500 2 PASSWORD_0805 1 V38 CLKOUT_PCIE7N V37 CLKOUT_PCIE7P FLEX CLOCKS D 1 K12 2 PCIECLKRQ7#/GPIO46 S 10K_5%_2_DY PCH_3S_SMDATA 2 A PCIECLKRQ6#/GPIO45 R4794 1 48C1 CLOSE TO PCH T13 2 3 PCH_3A_SMDATA G SSM3K7002BFU AK14 CLKOUT_ITPXDP_N AK13 CLKOUT_ITPXDP_P CLKOUTFLEX0/GPIO64 K43 1 CLKOUTFLEX1/GPIO65 F47 1 CLKOUTFLEX2/GPIO66 H47 1 CLKOUTFLEX3/GPIO67 K49 TP24 TP4700 TP24 TP4701 TP24 INVENTEC TP4702 2 BI IN IN 48C8 90.9_1%_2 R4793 1 Q4701 38C8 39C8 48C8 R4802 10K_5%_2_DY BI IN IN P1V05S PEG_B_CLKRQ#/GPIO56 10K_5%_2_DY PCH_3A_SMCLK BI PCIECLKRQ5#/GPIO44 AB42 E6 2 S G 48D3 B 18PF_50V_2 2 R4792 1 A 48D3 C4729 18PF_50V_2 C4728 48D3 2 2 PCH_3S_SMCLK 3 BI 2 2 38C8 39C8 48C8 10K_5%_2_DY 2.2K_5%_2 R4786 2.2K_5%_2 48C8 R4791 2.2K_5%_2 R4784 IN IN 10K_5%_2_DY 1 1 1 1 P5V0S L12 2 25MHZ CLKIN_DMI_PCH_DN CLKIN_DMI_PCH_DP XTAL25_IN 2 PCIECLKRQ3#/GPIO25 R4790 1 P3V3A 1 X4701 R4837 10K_5%_2_DY P3V3S 48A3 R4801 10K_5%_2 A8 2 41D2 1 R4789 1 OUT 41D2 1M_5%_2 CLOCKS IN OUT OUT PCIECLKRQ1#/GPIO18 R4782 48B3 CLK_DMI_PCH_DN CLK_DMI_PCH_DP 2 48D8 27C7 48D7 10K_5%_2 CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP OUT OUT 1 27C7 2 2 1 48A3 1 CLKIN_PCH14 OUT 2 27C7 R4781 IN D 2 Q4702 10K_5%_2 48A3 2 2.2K_5%_2 BI BE38 J2 2 2.2K_5%_2 2.2K_5%_2 PEG_A_CLKRQ#/GPIO47 2 10K_5%_2 R4798 1 R4779 48B3 2 2.2K_5%_2 3 1 R4797 1 D CLKIN_DMI_PCH_DP 2 10K_5%_2 S IN 48A8 R4796 1 2 1 R4778 48B3 BI SML1ALERT# IN 48D3 10K_5%_2 C PCH_3A_SMDATA 48D3 3 CLKIN_DMI_PCH_DN C9 48A8 10K_5%_2 R4777 IN SMBDATA BI D BG37 OUT 48B3 PERP2 SMBCLK PCH_3A_SMCLK S 48D8 22C5 48C7 10K_5%_2_DY PCIE_USB3_TX_C_DN PCIE_USB3_TX_C_DP C4794 1 PERN2 BF34 1 H14 10K_5%_2 PETP1 BE34 E12 SMBALERT#/GPIO11 SML0ALERT#/GPIO60 C4793 1 PETN1 P3V3A R4795 2 2 48D7 27C7 48B7 OUT 2 0.1UF_16V_2 0.1UF_16V_2 48D7 22C5 48C7 PCIE_WLAN_TX_C_DN PCIE_WLAN_TX_C_DP C4727 1 PERP1 AV32 AU32 C4726 1 BJ34 Link 27B7 2 Controller 27B7 PCIE_LAN_TX_C_DN PCIE_LAN_TX_C_DP C4725 1 PCI-E* 1 PERN1 SMBUS BG34 G 22C2 PCIE_LAN_RX_DN PCIE_LAN_RX_DP PCIE_LAN_TX_DN PCIE_LAN_TX_DP 1 22B1 22C2 IN IN OUT OUT 48B2 OUT P3V3A U4700 22B1 1 G 7 1 8 TITLE MODEL,PROJECT,FUNCTION ITL_PANTHERPOINT_FCBGA_989P Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 48 REV X01 68 of 1 8 7 6 4 5 3 2 1 DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE U4700 42C7 42C7 42D7 OUT OUT OUT OUT 42D7 42D7 P1V05S 42D7 1 42D7 OUT OUT OUT OUT 42D7 42D7 R4812 DMI_RX0_DP DMI_RX1_DP DMI_RX2_DP DMI_RX3_DP IN IN IN IN 42D7 42D7 DMI_TX0_DN DMI_TX1_DN DMI_TX2_DN DMI_TX3_DN BE20 DMI1RXN FDI_RXN1 AY14 BG18 DMI2RXN FDI_RXN2 BE14 BG20 DMI3RXN FDI_RXN3 BH13 FDI_RXN4 BC12 BE24 DMI0RXP FDI_RXN5 BJ12 BC20 DMI1RXP FDI_RXN6 BG10 BJ18 DMI2RXP FDI_RXN7 BG9 BJ20 DMI3RXP FDI_RXP0 BG14 FDI_RXP1 BB14 FDI_RXP2 BF14 FDI_RXP3 BG13 FDI_RXP4 BE12 FDI_RXP5 BG12 FDI_RXP6 BJ10 FDI_RXP7 BH9 FDI_TX0_DP FDI_TX1_DP FDI_TX2_DP FDI_TX3_DP FDI_TX4_DP FDI_TX5_DP FDI_TX6_DP FDI_TX7_DP AW16 FDI_INT AW24 DMI0TXN AW20 DMI_TX0_DP DMI_TX1_DP DMI_TX2_DP DMI_TX3_DP DMI1TXN BB18 DMI2TXN AV18 DMI3TXN AY24 DMI0TXP AY20 DMI1TXP AY18 DMI2TXP AU18 DMI3TXP 49.9_1%_2 FDI_INT 2 FDI_TX0_DN FDI_TX1_DN FDI_TX2_DN FDI_TX3_DN FDI_TX4_DN FDI_TX5_DN FDI_TX6_DN FDI_TX7_DN BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 FDI_LSYNC1 BB10 FDI_LSYNC1 IN IN IN IN IN IN IN IN 42C7 IN IN IN IN IN IN IN IN 42C7 42C7 OUT 42B7 OUT 42B7 OUT 42B7 OUT 42B7 OUT 42B7 LOW-DISABLED 42C7 D 42C7 42C7 42C7 P3V3_RTC 42C7 42C7 42C7 1 42D7 BJ14 STRAPPING 42C7 R4829 330K_5%_2 42C7 42C7 2 42D7 FDI_RXN0 42C7 42C7 42B7 1 42D7 DMI0RXN R4830 330K_5%_2_DY 2 IN IN IN IN 42D7 HIGH-ENABLED(DEFAULT) BC24 FDI D DMI_RX0_DN DMI_RX1_DN DMI_RX2_DN DMI_RX3_DN DMI 42D7 R4814 C 1 2 750_1%_2 P3V3S C 1 P3V3A 1 DSWVRMEN A18 R4832 STRAPPING R4816 1 2 C12 SUSACK# DPWROK E22 1 2 SYS_RESET# IN RSMRST# 2 IN 21D1 21D3 1K_5%_2_DY 49B7 0_5%_2 0_5%_2_DY 41C1 R4831 K3 SYS_RESET# WAKE# B9 PCIE_WAKE# N3 PCI_3S_CLKRUN# IN 22B5 27C7 IN 21E3 49A5 31C6 49A5 40B4 APWROK P3V3A 41C7 B13 DRAMPWROK 1 OUT PM_DRAM_PWRGD 49C2 21D1 21D3 R4820 IN 10K_5%_2_DY C21 2 SUS_PWR_ACK 2 49A5 OUT RSMRST# K16 SUSWARN#/SUSPWRDNACK/GPIO30 E20 PWRBTN# INT. PU 20K H20 ACPRESENT/GPIO31 INT. PD 20K E10 BATLOW#/GPIO72 A10 RI# NC D4706 RSMRST# 21D6 IN EC_PWRSW# 3 1 G8 R4883 10K_5%_2_DY SUSCLK/GPIO62 SLP_S5#/GPIO63 N14 D10 EC_32KHZ OUT SLP_S5#_3R OUT P3V3_LDO 21B6 14D2 SLP_S5_3R 21D3 B OUT Q4713 SLP_S4# 1 H4 R4834 G 10K_5%_2 SLP_S3# F4 SLP_S3#_IC_3R SSM3K7002FU_DY 2 L10 B SUS_STAT#/GPIO61 SLP_A# G10 D4707 IN ACPRESENT SLP_SUS# G16 SLP_SUS# AP14 H_PM_SYNC 15B4 49A5 1 BAT54_30V_0.2A 49A5 IN PM_RI# P3V3A INT. PU 20K PMSYNCH SLP_LAN#/GPIO29 BI 2 SSM3K7002BFU 3 41C5 P3V3A K14 5 IN LOW_BAT#_3 15B8 16A7 G OUT NC 21D6 15A4 S 2 21D6 OUT Q4714 1 BAT54_30V_0.2A SLP_S3_3R 3 PWROK 1 L22 D IN P3V3_LDO 2 PCH_PWROK 21B6 49A6 CLKRUN#/GPIO32 3 SYS_PWROK D P12 S PVCORE_PG 2 IN 11C7 System Power Management 11A4 1 IN SUSACK# 2 R4815 10K_5%_2 ITL_PANTHERPOINT_FCBGA_989P P3V3A 2 1 A SLP_S3#_3R IN 49B7 IN 49A6 IN 31C6 22B5 IN 49B3 27C7 ACPRESENT R4824 1 2 10K_5%_2 SUS_PWR_ACK R4825 1 2 10K_5%_2 PM_RI# R4826 1 2 10K_5%_2 PCIE_WAKE# R4827 1 2 10K_5%_2 2 13A2 14B8 OUT 13D2 14D2 14A6 21D6 45D3 - 8.2K_5%_2 21D6 2 4 49A6 21B6 IN PCH_PWROK 1 49B7 R4710 TC7SZ08FU 100K_5%_2 1 1 3 A + U4704 R4822 R4823 INVENTEC 2 10K_5%_2 P3V3S TITLE 49B3 21E3 IN PCI_3S_CLKRUN# 1 R4828 2 MODEL,PROJECT,FUNCTION 8.2K_5%_2 Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 49 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4700~4949(PCH) 1 P3V3S D R4855 D U4700 1 1 2 100K_5%_2 21E7 R4856 R4857 OUT OUT 34B5 OUT PCH_LCM_BKLTEN PCH_LCM_VDDEN J47 L_BKLTEN SDVO_TVCLKINN AP43 M45 L_VDD_EN SDVO_TVCLKINP AP45 PCH_INV_PWM_3 P45 L_BKLTCTL PCH_LVDS_DDCDATA - LVDS DETECT 1 L_DDC_CLK K47 L_DDC_DATA T45 L_CTRL_CLK P39 L_CTRL_DATA 2 HIGH-LVDS ENABLED LOW-LVDS DISABLED (DEFAULT) 34B8 34B8 34B8 34B8 34B8 34B8 34B8 34B8 OUT OUT OUT OUT OUT OUT OUT OUT 35D8 35D8 2 35A2 35A2 150_1%_2 OUT OUT AP39 SDVO_INTP AP40 LVD_IBG SDVO_CTRLCLK P38 AF36 LVD_VBG SDVO_CTRLDATA M39 AE48 LVD_VREFH AE47 LVD_VREFL DDPB_AUXN AT49 DDPB_AUXP AT47 DDPB_HPD AT40 DDPB_0N AV42 LVDSA_CLK# AK40 LVDSA_CLK DDPB_0P AV40 PCH_LVDS_TXDL0_DN PCH_LVDS_TXDL1_DN PCH_LVDS_TXDL2_DN AN48 LVDSA_DATA#0 DDPB_1N AV45 AM47 LVDSA_DATA#1 DDPB_1P AV46 AK47 LVDSA_DATA#2 DDPB_2N AU48 AJ48 LVDSA_DATA#3 DDPB_2P AU47 DDPB_3N AV47 DDPB_3P AV49 PCH_LVDS_TXDL0_DP PCH_LVDS_TXDL1_DP PCH_LVDS_TXDL2_DP AN47 LVDSA_DATA0 AM49 LVDSA_DATA1 AK49 LVDSA_DATA2 AJ47 LVDSA_DATA3 AF40 LVDSB_CLK# AF39 LVDSB_CLK AH45 LVDSB_DATA#0 AH47 LVDSB_DATA#1 AF49 LVDSB_DATA#2 AF45 LVDSB_DATA#3 DDPC_CTRLCLK P46 DDPC_CTRLDATA P42 AP47 AP49 DDPC_HPD AT38 PCH_HPDET DDPC_0N AY47 DDPC_0P AY49 DDPC_1N AY43 DDPC_1P AY45 DDPC_2N BA47 PCH_HDMI_TX2_DN PCH_HDMI_TX2_DP PCH_HDMI_TX1_DN PCH_HDMI_TX1_DP PCH_HDMI_TX0_DN PCH_HDMI_TX0_DP PCH_HDMI_TXC_DN PCH_HDMI_TXC_DP LVDSB_DATA0 LVDSB_DATA1 AF47 LVDSB_DATA2 DDPC_2P BA48 AF43 LVDSB_DATA3 DDPC_3N BB47 DDPC_3P BB49 CRT_BLUE P49 CRT_GREEN T49 CRT_RED DDPD_CTRLCLK M43 DDPD_CTRLDATA M36 DDPD_AUXN AT45 CRT_DDC_CLK DDPD_AUXP AT43 M40 CRT_DDC_DATA DDPD_HPD BH41 DDPD_0N BB43 M47 CRT_HSYNC DDPD_0P BB45 M49 CRT_VSYNC DDPD_1N BF44 DDPD_1P BE44 DDPD_2N BF42 PCH_CRT_DDCCLK PCH_CRT_DDCDATA T39 PCH_CRT_HSYNC PCH_CRT_VSYNC R4860 1 2 35B2 35B2 150_1%_2 OUT OUT R4861 1 2 PCH_HDMI_DDCCLK PCH_HDMI_DDCDATA DDPC_AUXP AH49 N48 C DDPC_AUXN AH43 R4859 1 SDVO_INTN AK39 PCH_CRTB PCH_CRTG PCH_CRTR OUT OUT OUT AM40 PCH_LVDS_TXCL_DN PCH_LVDS_TXCL_DP B 35D8 AM42 SDVO_STALLP AF37 2.37K_1%_2 C SDVO_STALLN WHEN ¡¥1¡¦- LVDS IS DETECTED R4858 Digital Display Interface 34C5 OUT OUT T40 LVDS 34C5 PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA CRT 2 2.2K_5%_2 2 2.2K_5%_2 34D7 T43 DAC_IREF DDPD_2P BE42 T42 CRT_IRTN DDPD_3N BJ42 DDPD_3P BG42 IN OUT OUT OUT OUT OUT OUT OUT OUT 36D8 36D8 36B5 36A5 36A5 36A5 B 36A5 36A5 36A5 36A5 36A5 1 150_1%_2 BI BI A A ITL_PANTHERPOINT_FCBGA_989P R4862 2 1K_1%_2 CLOSE TO PCH INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 50 REV X01 68 of 1 8 7 6 4 5 REFERENCE 4700~4949(PCH) D BOOT BIOS BBS_BIT0 0 1 1 0 1 1 0 DESTINATION AU3 BJ26 TP2 RSVD4 BG4 BH25 TP3 BJ16 TP4 RSVD5 AT10 BG16 TP5 RSVD6 BC8 AH38 TP6 AH37 TP7 RSVD7 AU2 AK43 TP8 RSVD8 AT4 AK45 TP9 RSVD9 AT3 C18 TP10 RSVD10 AT1 N30 TP11 RSVD11 AY3 TP12 RSVD12 AT5 TP13 RSVD13 AV3 RSVD14 AV1 RSVD15 BB1 RSVD16 BA3 RSVD17 BB5 RSVD18 BB3 RSVD19 BB7 RSVD20 BE8 RSVD21 BD4 RSVD22 BF6 RSVD23 AV5 RSVD24 AV10 RSVD25 AT8 H3 AH12 LPC AM4 TP14 AM5 TP15 Y13 TP16 K24 TP17 L24 TP18 AB46 TP19 AB45 TP20 P3V3S R4874 1 2 8.2K_5%_2 PCI_3S_INTA# R4875 1 2 8.2K_5%_2 PCI_3S_INTB# R4876 1 2 8.2K_5%_2 PCI_3S_INTC# R4877 1 2 8.2K_5%_2 PCI_3S_INTD# BI 51B6 BI 51B6 BI 51B6 BI 51B6 ROUTE WITH 90 OHMS IMPEDANCE 1 2 32D7 RUNSCI0#_3 8.2K_5%_2 33B5 R4880 1 2 10K_5%_2 DGPU_HOLD_RST# R4881 1 2 10K_5%_2 PCI_3S_REQ2# R4882 1 2 10K_5%_2 DGPU_PWR_EN# IN 51B6 IN 16A3 51B6 32D7 32D7 33B5 R4838 2 10K_5%_2 SATA_ODD_DA# R4956 1 2 10K_5%_2 PCI_3S_PIRQG# R4879 1 2 10K_5%_2 PCI_3S_PIRQH# USB3_PCH_RX1_DP USB3_PCH_RX2_DP BI BI 51B6 57A6 IN 33B5 1 USB3_PCH_RX1_DN USB3_PCH_RX2_DN BI BI 21E3 52D6 IN 32D7 C B21 TP21 M20 TP22 AY16 TP23 BG46 TP24 IN 29A5 51B6 IN 51B6 USB3_PCH_TX1_DN USB3_PCH_TX2_DN BI BI USB3_PCH_TX1_DP USB3_PCH_TX2_DP BI BI BE28 USB3RN1 RSVD26 AY5 BC30 USB3RN2 RSVD27 BA2 BE32 USB3RN3 BJ32 USB3RN4 RSVD28 AT12 BC28 USB3RP1 RSVD29 BF3 BE30 USB3RP2 BF32 USB3RP3 BG32 USB3RP4 AV26 USB3TN1 BB26 AU28 USBP0N C24 USBP0P A24 USB3TN2 USBP1N C25 USB3TN3 USBP1P B25 AY30 USB3TN4 USBP2N C26 AU26 USB3TP1 USBP2P A26 AY26 USB3TP2 USBP3N K28 DEBUG PORT AV28 USB3TP3 USBP3P H28 AW30 USB3TP4 USBP4N E28 USBP4P D28 USBP5N C28 USBP5P A28 USBP6N C29 USBP6P B29 51B6 IN BBS STRAPING 51C7 STP_A16OVR 2 2 51C7 51C7 57A6 R4885 B R4886 1K_5%_2_DY 51C7 16A3 1 1 31C7 31C6 29A5 51C7 51C7 TOP-BLOCK SWAP OVERRIDE HIGH=DEFAULT 51B7 P3V3A 1 P3V3A R4887 USB3_SMI# SATA_ODD_DA# PCI_3S_PIRQG# PCI_3S_PIRQH# BI BI BI BI 48A3 OUT OUT CLK_KBPCI CLKIN_PCI_FB R4889 1 R4890 1 CLK_KBPCI_R CLK_PCI_FB_R 2 22_5%_2 2 22_5%_2 5 + 27C7 BI BUF_PLT_RST# M28 PIRQC# USBP8N L30 G38 PIRQD# USBP8P K30 USBP9N G30 REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 OUT CLK_PCI_DEBUGR4891 1 2 USBP9P E30 USBP10N C30 USBP10P A30 USBP11N L32 D47 GNT1#/GPIO51 USBP11P K32 E42 GNT2#/GPIO53 USBP12N G32 F46 GNT3#/GPIO55 USBP12P E32 USBP13N C32 USBP13P A32 G42 PIRQE#/GPIO2 G40 PIRQF#/GPIO3 C42 PIRQG#/GPIO4 D44 PIRQH#/GPIO5 K10 PME# NOTE: USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2 USB_P0_DN USB_P0_DP USB_P1_DN USB_P1_DP USB_P2_DN USB_P2_DP BI BI BI BI BI BI USB_CR_DN USB_CR_DP USB_WLAN_DN USB_WLAN_DP USB_CAM_DN USB_CAM_DP BI BI BI BI BI BI USB_3G_DN USB_3G_DP BI BI C 32C8 32B8 P0.P1 RESERVER FOR USB3.0 32C8 32B8 33C5 33C5 30C5 66C6 66C6 30C5 26A8 26A8 27B3 27B3 34B3 34B3 CARD READER WLAN WEBCAM B 28C3 28C3 3G R4835 USBRBIAS# C33 USBRBIAS B33 1 2 1 TP4717 22_5%_2 CLOSE TO PCH INT. PU 20K PLTRST# OC0#/GPIO59 A14 OC1#/GPIO40 K20 OC2#/GPIO41 B17 H49 CLKOUT_PCI0 OC3#/GPIO42 C16 H43 CLKOUT_PCI1 OC4#/GPIO43 L16 J48 CLKOUT_PCI2 OC5#/GPIO9 A16 K42 CLKOUT_PCI3 OC6#/GPIO10 D14 H40 CLKOUT_PCI4 OC7#/GPIO14 C14 MACHINE_ID0 MACHINE_ID1 MACHINE_ID2 MACHINE_ID3 MACHINE_ID4 MACHINE_ID5 MACHINE_ID6 MACHINE_ID1_DB CLK_PCI_DEBUG_R 4 ITL_PANTHERPOINT_FCBGA_989P IN IN IN IN IN IN IN IN 51A4 51A5 51A4 51A5 51A4 51A5 51A4 51A5 51A4 51A5 51A4 51A5 51A4 51A5 51A4 51A5 TO BE USED AS GPIO 2 A - 21E3 57A6 2 TC7SZ08FU R4888 3 27C3 27C7 USBP7P 100K_5%_2 P3V3A 1 28C3 A 1 PIRQB# H38 C6 TP24 U4705 D 22.6_1%_3 P3V3A_PME# 2 10K_5%_2_DY PLT_RST# 21E3 N28 K38 USED AS GPIO ONLY. INT. PU 20K STP_A16OVR BI USBP7N 1K_5%_2_DY LOW=A16 SWAP OVERRIDE 31C6 36B2 PIRQA# DGPU_HOLD_RST# C46 C44 PCI_3S_REQ2# DGPU_PWR_EN# E40 OUT OUT OUT 51C7 K40 USB 51C7 BBS_BIT1 PCI_3S_INTA# PCI_3S_INTB# PCI_3S_INTC# PCI_3S_INTD# BI BI BI BI PCI 51D7 41C7 1 TOTAL LENGTH NO LONGER THAN 11 INCHES 33B5 R4878 AV7 RSVD3 ------ 0 AY7 RSVD2 TP1 RESERVED(NAND) SPI (DEFAULT) RSVD1 BG26 NVRAM BBS_BIT1 GPIO19 2 U4700 RSVD GPIO51 3 51A4 51A2 51A4 51A2 51A4 51A2 51A4 51A2 51A4 51A2 51A4 51A2 51A4 51A2 51A4 51A2 OUT OUT OUT OUT OUT OUT OUT OUT MACHINE_ID0 MACHINE_ID1 MACHINE_ID2 MACHINE_ID3 MACHINE_ID4 MACHINE_ID5 MACHINE_ID6 MACHINE_ID1_DB R4892 1 R4893 1 R4894 1 R4895 1 R4896 1 R4897 1 R4898 1 R4899 1 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 51A5 51A2 51A5 51A2 51A2 51A5 51A5 51A2 51A2 51A5 OUT OUT OUT OUT OUT OUT OUT OUT MACHINE_ID0 R4900 MACHINE_ID1 R4901 MACHINE_ID2 R4902 MACHINE_ID3 R4903 MACHINE_ID4 R4904 MACHINE_ID5 R4905 MACHINE_ID6 R4906 MACHINE_ID1_DB R4907 1 1 1 1 1 1 1 1 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY 2 10K_5%_2_DY INVENTEC 2 10K_5%_2_DY 2 10K_5%_2_DY TITLE MODEL,PROJECT,FUNCTION Block Diagram NOTE:10K_5%(60130B1030ZT) NOTE:10K_5%(60130B1030ZT) SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 51 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4700~4949(PCH) P3V3A R4927 1 2 10K_5%_2_DY PCH_GPIO6 R4908 1 2 1K_5%_2_DY PCH_GPIO15 R4909 1 1 R4910 PCH_GPIO8 2 10K_5%_2 PCH_GPIO12 2 10K_5%_2_DY OUT 52D6 OUT 52C6 OUT 52D6 OUT 52C6 P3V3S R4721 1 D 2 33K_5%_2_DY U4700 MSATA_DET IN 1 2 10K_5%_2_DY PCH_GPIO22 R4917 1 2 10K_5%_2_DY PCH_GPIO38 1 R4915 2 R4919 1 PCH_GPIO16 10K_5%_2_DY 2 10K_5%_2 SATA_ODD_PRSNT# OUT 52C6 OUT 52B6 OUT 52C6 OUT 29A5 52C7 51C7 52B6 28C2 IN 52D7 IN 21E3 IN 52D7 OUT 52D7 OUT 52D7 OUT BMBUSY#/GPIO0 TACH4/GPIO68 C40 TACH1/GPIO1 TACH5/GPIO69 B41 R4724 1 2 10K_5%_2_DY PCH_GPIO6 H36 TACH2/GPIO6 TACH6/GPIO70 C41 R4725 1 2 10K_5%_2_DY RUNSCI0#_3 E38 TACH3/GPIO7 TACH7/GPIO71 A40 R4726 1 2 10K_5%_2_DY PCH_GPIO8 C10 INT. PU 20K INT. PU 20K GPIO8 PCH_GPIO12 C4 LAN_PHY_PWR_CTRL/GPIO12 PCH_GPIO15 G2 GPIO15 INT. PD 20K A20GATE 52C6 OUT PCH_GPIO16 U2 13B2 13C8 52D7 C IN 52C7 OUT OUT R4928 P3V3S 52A7 1 T5 SCLOCK/GPIO22 KBLED_ID E8 GPIO24 2 OUT TACH0/GPIO17 PCH_GPIO22 10K_5%_2_DY PLL_ODVR_EN E16 STRAPPING P8 GPIO27 INT.PD 20K GPIO28 INT. PU 20K R4929 1 2 10K_5%_2_DY K1 STP_PCI#/GPIO34 R4930 1 2 10K_5%_2_DY K4 GPIO35 R4932 1 2 10K_5%_2_DY V8 OUT 52D7 OUT 52B7 OUT PROCPWRGD H_CPUPWRGD THRMTRIP# AY10 INIT3_3V# T14 210K_5%_2_DY R4926 1 2100K_5%_2 PCH_GPIO39 52B6 OUT SATA3GP/GPIO37 PCH_GPIO38 SLOAD/GPIO38 AY1 TS_VSS1 AH8 TS_VSS2 AK11 TS_VSS3 AH10 TS_VSS4 AK10 29A5 27C7 OUT 27B7 1 2 1K_5%_2_DY 1 2100K_5%_2 PCH_GPIO37 52B6 OUT OUT 41C5 C P1V05S R4944 R4941 56_5%_2 R4943 1 2 2 PM_THRMTRIP# IN 40A4 41D5 0_5%_2_DY NV_CLE FOLLOW EDS1.0 BG2 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 BG48 41D6 OUT D6 GPIO57 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 VSS_NCTF_1 VSS_NCTF_19 BJ4 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 A46 VSS_NCTF_4 VSS_NCTF_22 BJ46 VSS_NCTF_23 BJ5 VSS_NCTF_24 BJ6 B OUT BTIFON# A5 VSS_NCTF_5 A6 VSS_NCTF_6 B3 NCTF R4935 21D2 SDATAOUT0/GPIO39 VSS_NCTF_15 SATA_ODD_PRSNT# LOW- TX,RXTERMINATED TO SAME VOLTAGE R4934 IN 41D5 P37 V3 V13 A4 P3V3S 21A6 56_5%_2 390_5%_2 FDI_OVRVLTG(GPIO37) (DC COUPLING MODE) DEFAULT OUT BOTH THESE SHOULD BE CLOSE TO PCH STRAPPING SDATAOUT1/GPIO48 TP24 1 52D7 N2 PCH_GPIO39STRAPPING M3 TP4907 B 21E2 P1V05S STRAPPING DF_TVS NC_1 R4920 1 IN THRMTRIP#_R 1 INT. PD 20K P3V3S KBRST# AY11 SATA2GP/GPIO36 PCH_GPIO37STRAPPING M5 H_PECI R4942 INTERNAL GFX :100K PD 52B7 2 P5 RCIN# GFX_CRB_DET(GPIO39) EXTERNAL GFX :10K PU R4940 1 0_5%_2_DY INT. PU 20K D40 PCH_PECI SATA4GP/GPIO16 52D7 DGPU_PWRGD AU16 1 OUT EC_3S_A20GATE 1 PCH_GPIO22 P4 STRAPPING CPU/MISC 2 10K_5%_2_DY OUT A42 GPIO 1 R4727 29B8 3G_ON# PECI 52D7 D P3V3S SATA_ODD_PWREN 2 R4916 T7 2 P3V3S VSS_NCTF_7 VSS_NCTF_25 C2 B47 VSS_NCTF_8 VSS_NCTF_26 C48 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 VSS_NCTF_14 VSS_NCTF_32 F49 PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28) A HIGH-ENABLED (DEFAULT) A LOW-DISABLED P3V3A 1 R4950 2 PLL_ODVR_EN IN BF49 52C6 10K_5%_2 R4936 1 2 ITL_PANTHERPOINT_FCBGA_989P INVENTEC 10K_5%_2_DY TITLE STRAP MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 52 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 4700~4949(PCH) P1V05S P3V3S VCCCORE[10] AG27 VCCCORE[11] AG29 VCCCORE[12] AJ23 VCCCORE[13] AJ26 VCCCORE[14] AJ27 VCCCORE[15] AJ29 VCCCORE[16] AJ31 VCCCORE[17] P1V05S AN19 VCCIO[28] BJ22 VCCAPLLEXP 1 1 1 D P1V05S 20MIL 2 VCCCORE[9] AG26 VCCALVDS AK36 VSSALVDS AK37 VCCTX_LVDS[1] AM37 VCCTX_LVDS[2] AM38 VCCTX_LVDS[3] AP36 VCCTX_LVDS[4] AP37 15MIL P1V8S L4701 15MIL P1V8S_VCCTX_LVDS 1 2 1 VCCCORE[8] AG24 0.1UF_16V_2 0.01UF_50V_2 10UF_6.3V_3 P3V3S C4785 C4786 0.01UF_50V_2 0.01UF_50V_2 FBM_11_160808_121T C4787 22UF_6.3V_5 2 VCCCORE[7] AG23 C4783 2 FBM_11_160808_121T 2 VCCCORE[6] AG21 1 C4784 U47 1 AF23 C4782 VSSADAC 2 VCCCORE[5] P3V3S_VCCADAC 15MIL U48 2 VCCCORE[4] AF21 VCCADAC 1 VCCCORE[3] AD23 POWER CRT VCCCORE[2] AD21 2 1UF_6.3V_2 VCCCORE[1] AC23 LVDS 1 C4775 AA23 VCC CORE 2 1UF_6.3V_2 2 1UF_6.3V_2 10UF_6.3V_3 D C4774 L4700 U4700 2 C4773 2 C4772 1 1 1 1.3A R4945 AN17 VCCIO[16] AN21 VCCIO[17] AN26 VCCIO[18] AN27 VCCIO[19] AP21 VCCIO[20] AP23 VCCIO[21] 1UF_6.3V_2 15MIL HVCMOS VCCIO[15] C4780 VCC3_3[6] V33 C4788 1 VCC3_3[7] V34 2 0.1UF_16V_2 C P1V5S_VCCAFDI_VRM 2 2 1UF_6.3V_2 2 1UF_6.3V_2 C4779 AN16 1 1 1 C4778 2 1UF_6.3V_2 2 10UF_6.3V_3 1 1 C4777 C4776 P3V3S 0_5%_2_DY 3A C 2 P1V05S_VCCAPLLEXP 1 P1V05S AP24 VCCIO[22] AP26 VCCIO[23] DMI VCCIO VCCVRM[3] VCCDMI[1] AT20 15MIL P1V05S 15MIL P1V05S VCCCLKDMI P3V3S AT16 AB36 15MIL VCCIO[24] AN33 VCCIO[25] AN34 VCCIO[26] BH29 VCC3_3[3] 2 1UF_6.3V_2 C4790 1 AT24 C4789 1 2 P1V8S 1 1UF_6.3V_2_DY VCCDFTERM[1] AG16 15MIL VCCDFTERM[2] AG17 VCCDFTERM[3] AJ16 VCCDFTERM[4] AJ17 1 C4781 B 15MIL B C4791 2 0.1UF_16V_2 R4946 P1V05S_VCCAFDIPLL 2 BG6 VccAFDIPLL P1V05S 0_5%_2_DY P1V05S 20MIL AP17 15MIL AU20 VCCIO[27] FDI 1 0.1UF_16V_2 2 2 P3V3A R4947 R4948 0_5%_2 0_5%_2_DY V1 15MIL 1 VCCSPI 1 VCCVRM[2] 2 AP16 P3V3AL 1 15MIL P1V05S NAND / SPI P1V5S_VCCAFDI_VRM VCCDMI[2] C4792 ITL_PANTHERPOINT_FCBGA_989P 2 1UF_6.3V_2 A A P1V5S_VCCAFDI_VRM P1V5S R4949 1 40MIL 2 INVENTEC 0_5%_3 TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 53 REV X01 68 of 1 7 6 4 5 3 2 P1V05S P1V05S 2 P1V05S_VCCACLKAD49 0_5%_2_DY C4803 1 0.1UF_16V_2 VCCIO[30] P26 VCCIO[31] P28 VCCIO[32] T27 VCCIO[33] T29 C4829 1 V12 DCPSUSBYP T38 VCC3_3[5] 2 P1V05S_VCCAPLLDMI2 BH23 VCCAPLLDMI2 AL29 VCCIO[14] USB R4867 2 0_5%_2_DY 20MIL D C4805 1 2 AL24 DCPSUS[3] C4807 22UF_6.3V_5 VCCASW[2] AA24 VCCASW[3] AA26 VCCASW[4] VCCASW[5] C4809 1UF_6.3V_2 VCCASW[7] AC26 VCCASW[8] AC27 VCCASW[9] AC29 VCCASW[10] P1V05S AC31 VCCASW[11] AD29 VCCASW[12] AD31 VCCASW[13] L4706 C4813 1UF_6.3V_2 1 2 2 2 VCCASW[14] W23 VCCASW[15] T26 V5REF_SUS M26 DCPSUS[4] AN23 D 10MIL 20MIL 20.1UF_16V_2 1 P1V05S 2 0.1UF_16V_2 10MIL V5REF_SUS P3V3S D4709 3 2 1BAT54_30V_0.2A P3V3A 1 P5V0S AN24 VCCSUS3_3[1] 1UF_6.3V_2_DY 10MIL R4870 P34 V5REF VCCSUS3_3[2] N20 VCCSUS3_3[3] N22 VCCSUS3_3[4] P20 VCCSUS3_3[5] P22 2 10_5%_5 1 C4834 10MIL V5REF 1 2 1UF_6.3V_2 P3V3A C 10MIL C4835 1 2 1UF_6.3V_2 P3V3S VCC3_3[1] AA16 VCC3_3[8] W16 VCC3_3[4] T34 20MIL C4836 2 0.1UF_16V_2 1 W24 P3V3S VCCASW[16] W26 VCCASW[17] W29 VCCASW[18] W31 VCCASW[19] W33 VCCASW[20] 1 2 0.1UF_16V_2 P3V3S 2 20MIL AJ2 VCCIO[5] AF13 VCCIO[12] AH13 VCCIO[13] AH14 1 C4838 2 0.1UF_16V_2 1 1 1 VCCIO[34] 210_5%_5 1 C4833 VCC3_3[2] P1V05S_VCCADPLLB FBM_11_160808_121T C4815 R4869 P3V3A C4837 L4707 2 P24 0.1UF_16V_2 10UF_6.3V_3 C4811 1 VCCSUS3_3[10] V24 P5V0A 2 C4814 0.1UF_16V_2 B W21 1 1 1 P1V05S_VCCADPLLA 22UF_6.3V_5_DY V23 C4830 1 C4832 PCI/GPIO/LPC 1UF_6.3V_2 2 2 VCCASW[6] AA31 C4810 2 1UF_6.3V_2 AA29 1 1 1 C4808 C4812 VCCSUS3_3[9] 1 2 AA21 AA27 FBM_11_160808_121T T24 BAT54_30V_0.2A 3 1 2 2 22UF_6.3V_5 VCCASW[1] P1V05S 2 VCCSUS3_3[8] 10MIL C4831 AA19 Clock and Miscellaneous 1 1 C4806 1 T23 VCCSUS3_3[6] 1.1A C VCCSUS3_3[7] 1UF_6.3V_2_DY P1V05S P3V3A P3V3A D4708 P1V05S 1 1UF_6.3V_2 C4804 20MIL P1V05S REFERENCE 4700~4949(PCH) 3A VCCDSW3_3 0.1UF_16V_2_DY 10UF_6.3V_3 2 2T16 0_5%_2 2 C4802 R4866 N26 2 0.1UF_16V_2 1 VCCIO[29] NC 1 1 2 C4801 POWER VCCACLK 1 15MIL U4700 R4865 1 2 P3V3A P3V3S 1 NC 8 C4816 N16 P1V5S_VCCAFDI_VRM C4817 P1V05S B DCPRTC 20MIL C4839 15MIL Y49 VCCVRM[4] 2 2 10UF_6.3V_3 SATA 1UF_6.3V_2 2 22UF_6.3V_5_DY 15MIL BD47 VCCADPLLA BF47 2 1UF_6.3V_2 AF14 VCCIO[6] P1V05S L4708 AK1 VCCAPLLSATA 15MIL 1 P1V05S_VCCAPLLSATA 1 VCCADPLLB C4818 2 1UF_6.3V_2 C4819 2 1UF_6.3V_2 C4820 2 1UF_6.3V_2 15MIL 1 VCCDIFFCLKN[1] AF34 VCCDIFFCLKN[2] AG34 VCCDIFFCLKN[3] VCCSSC V16 DCPSST T17 DCPSUS[1] V19 DCPSUS[2] CPU BJ8 V_PROC_IO VCCASW[22] T21 VCCASW[23] V21 VCCASW[21] T19 VCCRTC C4827 C4828 A 20MIL P3V3A HDA RTC 1 1 1 A22 2 C4826 2 P1V05S P3V3_RTC 0.1UF_16V_2 2 2 1 AD17 P32 VCCSUSHDA 10MIL INVENTEC 1 2 C4825 0.1UF_16V_2 20MIL 1 1 1 1 C4841 ITL_PANTHERPOINT_FCBGA_989P TITLE 0.1UF_16V_2 1UF_6.3V_2 0.1UF_16V_2 MODEL,PROJECT,FUNCTION 0.1UF_16V_2 2 2 2 Block Diagram 2 4.7UF_6.3V_3 AC17 1UF_6.3V_2 10MIL C4824 VCCIO[3] VCCIO[4] 1UF_6.3V_2_DY C4823 AC16 1 C4822 1 P1V05S VCCIO[2] 10MIL C4840 MISC A AF11 P1V05S 1 0.1UF_16V_2 2 VCCVRM[1] VCCIO[7] AF33 15MIL AG33 C4821 P1V5S_VCCAFDI_VRM 0603_DY P1V05S 20MIL AF17 2 SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 54 REV X01 68 of 1 8 7 6 5 4 3 REFERENCE 4700~4949(PCH) U4700 VSS[80] AK38 AA2 VSS[2] VSS[81] AK4 AA3 VSS[3] VSS[82] AK42 AA33 VSS[4] VSS[83] AK46 AA34 VSS[5] VSS[84] AK8 AB11 VSS[6] VSS[85] AL16 AB14 VSS[7] VSS[86] AL17 AB39 VSS[8] VSS[87] AL19 VSS[9] VSS[88] AL2 VSS[10] VSS[89] AL21 AB5 VSS[11] VSS[90] AL23 AB7 VSS[12] VSS[91] AL26 AC19 VSS[13] VSS[92] AL27 VSS[14] VSS[93] AL31 AC21 VSS[15] VSS[94] AL33 AC24 VSS[16] VSS[95] AL34 AC33 VSS[17] VSS[96] AL48 AC34 VSS[18] VSS[97] AM11 AC48 VSS[19] VSS[98] AM14 AD10 VSS[20] VSS[99] AM36 AD11 VSS[21] VSS[100] AM39 AD12 VSS[22] VSS[101] AM43 AD13 VSS[23] VSS[102] AM45 AD19 VSS[24] VSS[103] AM46 AD24 VSS[25] VSS[104] AM7 AD26 VSS[26] VSS[105] AN2 AD27 VSS[27] VSS[106] AN29 AD33 VSS[28] VSS[107] AN3 AD34 VSS[29] VSS[108] AN31 AD36 VSS[30] VSS[109] AP12 AD37 VSS[31] VSS[110] AP19 AD38 VSS[32] VSS[111] AP28 AD39 VSS[33] VSS[112] AP30 VSS[34] VSS[113] AP32 AD40 VSS[35] VSS[114] AP38 AD42 VSS[36] VSS[115] AP4 AD43 VSS[37] VSS[116] AP42 AD45 VSS[38] VSS[117] AP46 AB4 AB43 D AC2 AD4 C AD46 VSS[39] VSS[118] AP8 AD8 VSS[40] VSS[119] AR2 AE2 VSS[41] VSS[120] AR48 AE3 VSS[42] VSS[121] AT11 AF10 VSS[43] VSS[122] AT13 AF12 VSS[44] VSS[123] AT18 AD14 VSS[45] VSS[124] AT22 AD16 VSS[46] VSS[125] AT26 AF16 VSS[47] VSS[126] AT28 AF19 VSS[48] VSS[127] AT30 AF24 VSS[49] VSS[128] AT32 AF26 VSS[50] VSS[129] AT34 AF27 VSS[51] VSS[130] AT39 AF29 VSS[52] VSS[131] AT42 AF31 VSS[53] VSS[132] AT46 AF38 VSS[54] VSS[133] AT7 VSS[55] VSS[134] AU24 AF42 VSS[56] VSS[135] AU30 AF46 VSS[57] VSS[136] AV16 AF5 VSS[58] VSS[137] AV20 AF7 VSS[59] VSS[138] AV24 AF8 VSS[60] VSS[139] AV30 AG19 VSS[61] VSS[140] AV38 VSS[62] VSS[141] AV4 AG31 VSS[63] VSS[142] AV43 AG48 VSS[64] VSS[143] AV8 AH11 VSS[65] VSS[144] AW14 VSS[66] VSS[145] AW18 AH36 VSS[67] VSS[146] AW2 AH39 VSS[68] VSS[147] AW22 AH40 VSS[69] VSS[148] AW26 AH42 VSS[70] VSS[149] AW28 AH46 VSS[71] VSS[150] AW32 VSS[72] VSS[151] AW34 AJ19 VSS[73] VSS[152] AW36 AJ21 VSS[74] VSS[153] AW40 AJ24 VSS[75] VSS[154] AW48 AJ33 VSS[76] VSS[155] AV11 AJ34 VSS[77] VSS[156] AY12 AK12 VSS[78] VSS[157] AY22 VSS[79] VSS[158] AY28 AF4 B AG2 AH3 AH7 AK3 A VSS[0] VSS[1] AA17 1 U4700 VSS[159] VSS[259] H46 AY42 VSS[160] VSS[260] K18 AY46 VSS[161] VSS[261] K26 AY8 VSS[162] VSS[262] K39 B11 VSS[163] VSS[263] K46 B15 VSS[164] VSS[264] K7 B19 VSS[165] VSS[265] L18 B23 VSS[166] VSS[266] L2 B27 VSS[167] VSS[267] L20 B31 VSS[168] VSS[268] L26 B35 VSS[169] VSS[269] L28 B39 VSS[170] VSS[270] L36 VSS[171] VSS[271] L48 F45 VSS[172] VSS[272] M12 BB12 VSS[173] VSS[273] P16 BB16 VSS[174] VSS[274] M18 BB20 VSS[175] VSS[275] M22 BB22 VSS[176] VSS[276] M24 BB24 VSS[177] VSS[277] M30 BB28 VSS[178] VSS[278] M32 BB30 VSS[179] VSS[279] M34 BB38 VSS[180] VSS[280] M38 VSS[181] VSS[281] M4 BB46 VSS[182] VSS[282] M42 BC14 VSS[183] VSS[283] M46 BC18 VSS[184] VSS[284] M8 VSS[185] VSS[285] N18 BC22 VSS[186] VSS[286] P30 BC26 VSS[187] VSS[287] N47 BC32 VSS[188] VSS[288] P11 BC34 VSS[189] VSS[289] P18 BC36 VSS[190] VSS[290] T33 BC40 VSS[191] VSS[291] P40 BC42 VSS[192] VSS[292] P43 BC48 VSS[193] VSS[293] P47 BD46 VSS[194] VSS[294] P7 VSS[195] VSS[295] R2 BE22 VSS[196] VSS[296] R48 BE26 VSS[197] VSS[297] T12 BE40 VSS[198] VSS[298] T31 AY4 H5 2 B7 BB4 BC2 BD5 BF10 VSS[199] VSS[299] T37 BF12 VSS[200] VSS[300] T4 BF16 VSS[201] VSS[301] W34 BF20 VSS[202] VSS[302] T46 BF22 VSS[203] VSS[303] T47 BF24 VSS[204] VSS[304] T8 BF26 VSS[205] VSS[305] V11 BF28 VSS[206] VSS[306] V17 VSS[207] VSS[307] V26 BF30 VSS[208] VSS[308] V27 BF38 VSS[209] VSS[309] V29 BF40 VSS[210] VSS[310] V31 BF8 VSS[211] VSS[311] V36 BG17 VSS[212] VSS[312] V39 BG21 VSS[213] VSS[313] V43 BG33 VSS[214] VSS[314] V7 BG44 VSS[215] VSS[315] W17 VSS[216] VSS[316] W19 BH11 VSS[217] VSS[317] W2 BH15 VSS[218] VSS[318] W27 BH17 VSS[219] VSS[319] W48 BH19 VSS[220] VSS[320] Y12 H10 VSS[221] VSS[321] Y38 BH27 VSS[222] VSS[322] Y4 BH31 VSS[223] VSS[323] Y42 BH33 VSS[224] VSS[324] Y46 BH35 VSS[225] VSS[325] Y8 BH39 VSS[226] VSS[328] BG29 BH43 VSS[227] VSS[329] N24 BH7 VSS[228] VSS[330] AJ3 D3 BD3 BG8 VSS[229] VSS[331] AD47 D12 VSS[230] VSS[333] B43 D16 VSS[231] VSS[334] BE10 D18 VSS[232] VSS[335] BG41 D22 VSS[233] VSS[337] G14 D24 VSS[234] VSS[338] H16 D26 VSS[235] VSS[340] T36 D30 VSS[236] VSS[342] BG22 D32 VSS[237] VSS[343] BG24 D34 VSS[238] VSS[344] C22 D38 VSS[239] VSS[345] AP13 D42 VSS[240] VSS[346] M14 VSS[241] VSS[347] AP3 E18 VSS[242] VSS[348] AP1 E26 VSS[243] VSS[349] BE16 G18 VSS[244] VSS[350] BC16 G20 VSS[245] VSS[351] BG28 G26 VSS[246] VSS[352] BJ28 G28 VSS[247] G36 VSS[248] G48 VSS[249] H12 VSS[250] H18 VSS[251] H22 VSS[252] H24 VSS[253] H26 VSS[254] H30 VSS[255] H32 VSS[256] H34 VSS[257] F3 VSS[258] D8 ITL_PANTHERPOINT_FCBGA_989P D C B A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram ITL_PANTHERPOINT_FCBGA_989P SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 55 REV X01 68 of 1 8 7 6 5 4 3 2 1 P3V3S_DGPU VGA_CRT_VSYNC R5027 2 1 10K_5%_2_DY GPIO22 PWRCNTL_0 R5017 1 210K_5%_2 PWRCNTL_1 OUT 35B2 56D3 OUT 56C5 OUT 13C6 56D5 OUT 13C6 56C5 0 HYNIX 0 0 SAMSUNG 1 R5006 1 TRANSMITTER POWER SAVING ENABLE 0 : 50% TX OUTPUT SWING (DEFAULT) 1 : FULL TX OUTPUT SWING GPIO_1 PCIE TRANSMITTER DE-EMPHASIS GPIO_2 GPIO_8 GPIO_21 MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 0 : GEN1 (DEFAULT) 1 : GEN2 LEFT UNCONNECTED MUST BE LOW DURING RESET E GPIO_9 0 : ENABLE (DEFAULT) 1 : DISABLE VGA DISABLE GPIO_[11:13] GPIO_13 GPIO_12 GPIO_11 MEMORY APERTURE SIZE MEMORY APERTURE SIZE 0 0 0 0 0 1 0 0 1 128M 256M 64M 0 1 1 AU24 TXCAM_DPA3N AV23 TX0P_DPA2P AT25 TX0M_DPA2N AR24 TX1P_DPA1P AU26 TX1M_DPA1N AV25 AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 AP8 DVPCNTL_0 AW8 DVPCNTL_1 TXCBP_DPB3P AR30 AR3 DVPCNTL_2 TXCBM_DPB3N AT29 AR1 0 : DE-EMPHASIS DISABLED (DEFAULT) 1 : DE-EMPHASIS ENABLED GEN1/GEN2 ENABLE TXCAP_DPA3P MUTI GFX DPA PIN BASE STRAPS GPIO_0 0 1 P1V8S_DGPU 2 R5056 1 210K_5%_2 35B2 56D3 0 0 TX3P_DPB2P AV31 TX3M_DPB2N AU30 DVPDATA_3 TX4P_DPB1P AR32 AW5 DVPDATA_4 TX4M_DPB1N AT31 AU5 DVPDATA_5 AR6 DVPDATA_6 TX5P_DPB0P AT33 AW6 DVPDATA_7 TX5M_DPB0N AU32 AU6 DVPDATA_8 AT7 DVPDATA_9 TXCCP_DPC3P AU14 AV7 DVPDATA_10 TXCCM_DPC3N AV13 AN7 DVPDATA_11 AV9 DVPDATA_12 TX0P_DPC2P AT15 AT9 DVPDATA_13 TX0M_DPC2N AR14 AR10 DVPDATA_14 AU1 DVPDATA_0 AU3 DVPDATA_1 AW3 DVPDATA_2 AP6 DPB DPC AW10 DVPDATA_15 TX1P_DPC1P AU16 AU10 DVPDATA_16 TX1M_DPC1N AV15 AP10 DVPDATA_17 AV11 DVPDATA_18 TX2P_DPC0P AT17 AT11 DVPDATA_19 TX2M_DPC0N AR16 AR12 DVPDATA_20 AW12 DVPDATA_21 TXCDP_DPD3P AU20 AU12 DVPDATA_22 TXCDM_DPD3N AT19 AP12 DVPDATA_23 TX3P_DPD2P AT21 TX3M_DPD2N AR20 TX4P_DPD1P AU22 TX4M_DPD1N AV21 TX5P_DPD0P AT23 TX5M_DPD0N AR22 AJ21 SWAPLOCKA AK21 SWAPLOCKB 34C5 BI BI 34C5 10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED 56F7 11 : AUDIO FOR BOTH DP AND HDMI 56F7 IN IN IN BI BI IN 56C7 D 56F7 21E7 P3V3S_DGPU 40B1 40A8 OUT 56F7 56F7 SSM3K7002BFU EC_SMB2_DATA 3 C 2 AH23 GPIO_3_SMBDATA AJ23 GPIO_4_SMBCLK AH17 GPIO_5_AC_BATT AJ17 GPIO_6 AK17 PWRCNTL_0 2 1 10K_5%_2 13C6 56F7 PWRCNTL_1 OUT 56F7 GPIO22 IN 1 1 TP15 TP30 1 TP30 1 2 GPU_SID GPIO_7_BLON HSYNC AC36 AJ13 GPIO_8_ROMSO VSYNC AC38 AH15 GPIO_9_ROMSI AJ16 GPIO_10_ROMSCK AK16 GPIO_11 AL16 GPIO_12 AM16 GPIO_13 AM14 GPIO_14_HPD2 AM13 GPIO_15_PWRCNTL_0 AK14 GPIO_16 VDD1DI AC33 AG30 GPIO_17_THERMAL_INT VSS1DI AC34 AN14 GPIO_18_HPD3 AM17 GPIO_19_CTF AL13 GPIO_20_PWRCNTL_1 R2/NC AC30 AJ14 GPIO_21_BB_EN R2B/NC AC31 AK13 GPIO_22_ROMCSB AN13 GPIO_23_CLKREQB G2/NC AD30 RSET 2 36B5 I=75MA TRACE WIDTH>=15MIL AE34 G2B/NC AD31 B2/NC AF30 TP30 AL24 JTAG_TMS B2B/NC AF31 AM24 JTAG_TDO AJ19 GENERICA AK19 GENERICB C/NC AC32 AJ20 GENERICC Y/NC AD32 AK20 GENERICD COMP/NC AF32 AJ24 GENERICE_HPD4 AH26 GENERICF_HPD5 AH24 GENERICG_HPD6 H2SYNC/GENLK_CLK AD29 V2SYNC/GENLK_VSYNC AC29 0.1UF_16V_2 AH13 VDD2DI/NC AG31 VSS2DI/NC AG32 A2VDD/NC AG33 A2VDDQ/NC AD33 A2VSSQ/TSVSSQ DPLL_PVDD AN32 DPLL_PVSS AN31 DPLL_VDDC C5016 AV33 XTALIN AU34 XTALOUT DDC/AUX 2 2 PLL/CLOCK B R4 1 2 AM26 AN26 AUX1P AM27 AUX1N AL27 X5000 12PF_50V_2 C5212 2 12PF_50V_2 C5211 27MHZ 2 AW34 XO_IN AW35 XO_IN2 1 1 2 TP5000 56E2 OUT 35D8 56E2 OUT OUT 56F7 35B2 VGA_CRTB 150_1%_2 2 D P1V8S_DGPU VGA_CRT_HSYNC VGA_CRT_VSYNC 1 L5000 I=70MA TRACE WIDTH>=15MIL 35B2 56F7 P1V8S_AVDD 2 1 FBM_11_160808_121T 2 C5001 C5000 0.1UF_16V_2 C5005 1UF_6.3V_2 10UF_6.3V_3 I=100MA TRACE WIDTH>=15MIL L5001 C5003 2 C5002 0.1UF_16V_2 1 FBM_11_160808_121T C5004 1UF_6.3V_2 10UF_6.3V_3 C AN20 AUX2N AM20 DDCDATA_AUX3N DDCCLK_AUX4P 1 AF29 DPLUS AG29 DMINUS AK32 TS_FDO AL31 TS_A/NC L5006 I=20MA TRACE WIDTH>=15MIL 1 P1V8S_TSVDD AJ32 TSVDD AJ33 TSVSS VGA_HDMI_DDCCLK VGA_HDMI_DDCDATA BI BI 36D8 36D8 THERMAL AL19 AL30 AM30 AL29 DDCDATA_AUX4N AM29 DDCCLK_AUX5P AN21 DDCDATA_AUX5N AM21 DDC6CLK AJ30 DDC6DATA AJ31 P1V8S_DGPU 1 35D8 150_1%_2 2 R5074 1 AM19 AUX2P DDCCLK_AUX3P TP30 1 OUT VGA_CRTG B DDC2DATA 1 2 56E2 150_1%_2 2 R5073 1 AA29 DDC1CLK DDC2CLK 1M_5%_2 1 VGA_CRTB 35D8 IN R5072 1 AF33 DDC1DATA 0.1UF_16V_2 1UF_6.3V_2 10UF_6.3V_3 2 AM32 C5015 C5014 VGA_CRTG OUT 35D8 IN VGA_CRTR VREFG 1 1 FBM_11_160808_121T VGA_CRTR 35D8 IN HPD1 1 C5010 249_1%_2 I=125MA TRACE WIDTH>=15MIL 1 PVPCIE_DPLL_VDDC 2 56D3 35D8 DAC2 R2SET/NC L5005 56D3 P1V8S_VDD1DI JTAG_TCK PVPCIE 1 PLACE CLOSE TO ASIC P0V6S_VREFG 21 R5003 1 C5012 0.1UF_16V_2 2 2 10UF_6.3V_3 2 C5011 C5013 1UF_6.3V_2 1 1 FBM_11_160808_121T E 499_1%_2 1 P1V8S_DPLL_PVDD 2 2 L5004 AD34 JTAG_TDI AK24 36A5 P1V8S_DGPU R5004 1 AVDD AVSSQ JTAG_TRSTB VGA_HPDET IN 36A5 499_1%_2 P1V8S_DGPU P1V8S_DGPU AB34 AK23 10K_5%_2 OUT OUT 36A5 R5000 AN23 1 SSM3K7002BFU AE38 AM23 2 Q5002 AF37 TP11 R5060 10K_5%_2_DY B BB TP14 TP12 36A5 36A5 DAC1 TP30 TP30 R5005 56D5 BI 1 TP16 1 R5095 2 BI AD35 GPU_SIC S OUT 1 10K_5%_2 1 G 5A7 D 21D2 S 21D3 37C3 AE36 GB GPU_SID 2 R5015 10K_5%_2 2 1 P3V3S_DGPU 1 R5061 Q5001 SSM3K7002BFU R5063 2 BI G GPIO_2 GPIO5 56D5 10K_5%_2 GPU_SIC 2 GPIO_1 GPIO_0 AN16 GPIO11 IN 1 G AD37 AH18 D Q5000 AD39 AH20 GPIO9 IN 1 R5094 2 P3V3S_DGPU R RB GPIO0 GPIO1 GPIO2 VGA_LCM_BKLTEN OUT THRM_SHUTDWN# 3 15D8 10K_5%_2 1 G 3 D BI EC_SMB2_CLK S 5A7 SDA GENERAL PURPOSE I/O 56D7 21D2 SCL AJ26 56F7 OUT OUT F 2 01 : AUDIO FOR DP ONLY 21D3 37C6 AK26 00 : NO AUDIO FUNCTION AUDIO[1:0] VGA_HDMI_TX2_DP VGA_HDMI_TX2_DN OUT OUT 36A5 36A5 2 HSYNC[1] VSYNC[0] VGA_HDMI_TX1_DP VGA_HDMI_TX1_DN 36A5 56D3 DPD I2C VGA_LVDS_DDCCLK VGA_LVDS_DDCDATA VGA_HDMI_TX0_DP VGA_HDMI_TX0_DN OUT OUT DVPCLK 32M ENABLE EXTERNAL BIOS ROM DEVICE 0 : DISABLE (DEFAULT) 1 : ENABLE GPIO_22 VGA_HDMI_TXC_DP VGA_HDMI_TXC_DN 1 210K_5%_2 OUT 0 2 R5031 1 OUT GPIO11:MEMORY APERTURE SIZE 256M 1 VGA_CRT_HSYNC 56D5 2 210K_5%_2 56D5 1 R5030 1 OUT MEM_ID1 1 GPIO9 GPIO11 THAMES (6019B0917601) U5001 MEM_ID0 MEM_ID2 2 10K_5%_2 MEM_ID3 1 RSC_0402_DY 2 56D5 2 2 1 56D5 OUT 1 1 R5014 OUT 10K_5%_2_DY R5037 GPIO5 2 RSC_0402_DY R5009 2 1 1 10K_5%_2_DY R5028 56D5 2 2 R5008 GPIO2 1 56D5 OUT 1 10K_5%_2 R5011 OUT 10K_5%_2_DY GPIO1 2 GPIO0 2 10K_5%_2 R5007 2 10K_5%_2 R5010 1 10K_5%_2_DY F R5016 1 DDCCLK_AUX7P AK30 DDCDATA_AUX7N AK29 VGA_CRT_DDCCLK VGA_CRT_DDCDATA BI BI 35A2 35B2 FBM_11_160808_121T C5019 C5017 C5018 1UF_6.3V_2 0.1UF_16V_2 AMD_216_0833002_FCBGA_962P 2 2 2 10UF_6.3V_3 A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 56 1 REV X01 of 68 8 7 6 4 5 3 2 1 U5001 42B1 42D1 42B1 42D1 42B1 42D1 D BI BI BI BI BI BI PEG_C_TX0_DP PEG_C_TX0_DN AA38 PCIE_RX0P PCIE_TX0P Y33 Y37 PCIE_RX0N PCIE_TX0N Y32 PEG_C_TX1_DP PEG_C_TX1_DN Y35 PCIE_RX1P PCIE_TX1P W33 W36 PCIE_RX1N PCIE_TX1N W32 PEG_C_TX2_DP PEG_C_TX2_DN W38 PCIE_RX2P PCIE_TX2P U33 V37 PCIE_RX2N PCIE_TX2N U32 PEG_C_TX3_DP PEG_C_TX3_DN V35 PCIE_RX3P PCIE_TX3P U30 U36 PCIE_RX3N PCIE_TX3N U29 PEG_C_TX4_DP PEG_C_TX4_DN U38 PCIE_RX4P PCIE_TX4P T33 T37 PCIE_RX4N PCIE_TX4N T32 PEG_C_TX5_DP PEG_C_TX5_DN T35 PCIE_RX5P PCIE_TX5P T30 R36 PCIE_RX5N PCIE_TX5N T29 PEG_C_TX6_DP PEG_C_TX6_DN R38 PCIE_RX6P PCIE_TX6P P33 P37 PCIE_RX6N PCIE_TX6N P32 PEG_C_TX7_DP PEG_C_TX7_DN P35 PCIE_RX7P PCIE_TX7P P30 N36 PCIE_RX7N PCIE_TX7N P29 PEG_C_TX8_DP PEG_C_TX8_DN N38 PCIE_RX8P PCIE_TX8P N33 M37 PCIE_RX8N PCIE_TX8N N32 PEG_C_TX9_DP PEG_C_TX9_DN M35 PCIE_RX9P PCIE_TX9P N30 L36 PCIE_RX9N PCIE_TX9N N29 PEG_C_TX10_DP PEG_C_TX10_DN L38 PCIE_RX10P K37 PCIE_RX10N PEG_C_TX11_DP PEG_C_TX11_DN K35 PCIE_RX11P J36 PCIE_RX11N PEG_C_TX12_DP PEG_C_TX12_DN J38 H37 PEG_C_TX13_DP PEG_C_TX13_DN PEG_RX0_DP PEG_RX0_DN C5022 1 2 0.1UF_6.3V_1 C5023 1 2 0.1UF_6.3V_1 PEG_RX1_DP PEG_RX1_DN C5024 1 2 0.1UF_6.3V_1 C5025 1 2 0.1UF_6.3V_1 PEG_RX2_DP PEG_RX2_DN C5026 1 2 0.1UF_6.3V_1 C5027 1 2 0.1UF_6.3V_1 PEG_RX3_DP PEG_RX3_DN C5028 1 2 0.1UF_6.3V_1 C5029 1 2 0.1UF_6.3V_1 PEG_RX4_DP PEG_RX4_DN C5030 1 2 0.1UF_6.3V_1 C5031 1 2 0.1UF_6.3V_1 PEG_RX5_DP PEG_RX5_DN C5032 1 2 0.1UF_6.3V_1 C5033 1 2 0.1UF_6.3V_1 PEG_RX6_DP PEG_RX6_DN C5034 1 2 0.1UF_6.3V_1 C5035 1 2 0.1UF_6.3V_1 C5036 1 2 0.1UF_6.3V_1 C5037 1 2 0.1UF_6.3V_1 C5038 1 2 0.1UF_6.3V_1 C5039 1 2 0.1UF_6.3V_1 C5040 1 2 0.1UF_6.3V_1 C5041 1 2 0.1UF_6.3V_1 PEG_RX10_DP PEG_RX10_DN C5042 1 2 0.1UF_6.3V_1 C5043 1 2 0.1UF_6.3V_1 PEG_RX11_DP PEG_RX11_DN C5044 1 2 0.1UF_6.3V_1 C5045 1 2 0.1UF_6.3V_1 PEG_RX12_DP PEG_RX12_DN C5046 1 2 0.1UF_6.3V_1 C5047 1 2 0.1UF_6.3V_1 PEG_RX13_DP PEG_RX13_DN C5048 1 2 0.1UF_6.3V_1 C5049 1 2 0.1UF_6.3V_1 PEG_RX14_DP PEG_RX14_DN C5050 1 2 0.1UF_6.3V_1 C5051 1 2 0.1UF_6.3V_1 PEG_RX15_DP PEG_RX15_DN C5052 1 2 0.1UF_6.3V_1 C5053 1 2 0.1UF_6.3V_1 PEG_C_RX0_DP PEG_C_RX0_DN PEG_C_RX1_DP PEG_C_RX1_DN PEG_C_RX2_DP PEG_C_RX2_DN BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 BI BI 42C4 42C4 42C4 42D4 D 42B1 42C1 42B1 42C1 42B1 42C1 42B1 42C1 42B1 42C1 42B1 C 42C1 42C1 42A1 42C1 42A1 42C1 42A1 42C1 U5001 42A1 LVDS CONTROL VARY_BL DIGON VGA_INV_PWM_3 VGA_LCM_VDDEN AK27 AJ27 OUT OUT 42A1 R5071 42B1 2 R5070 AK35 TXCLK_UN_DPF3N AL36 42A1 1 10K_5%_2 TXOUT_U0P_DPF2P AJ38 TXOUT_U0N_DPF2N AK37 TXOUT_U1P_DPF1P AH35 TXOUT_U1N_DPF1N AJ36 TXOUT_U2P_DPF0P AG38 TXOUT_U2N_DPF0N AH37 10K_5%_2 42B1 1 TXCLK_UP_DPF3P BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI PCIE_TX10P L33 PCIE_TX10N L32 PCIE_TX11P L30 PCIE_TX11N L29 PCIE_RX12P PCIE_TX12P K33 PCIE_RX12N PCIE_TX12N K32 H35 PCIE_RX13P PCIE_TX13P J33 G36 PCIE_RX13N PCIE_TX13N J32 PEG_C_TX14_DP PEG_C_TX14_DN G38 PCIE_RX14P PCIE_TX14P K30 F37 PCIE_RX14N PCIE_TX14N K29 PEG_C_TX15_DP PEG_C_TX15_DN F35 PCIE_RX15P PCIE_TX15P H33 E37 PCIE_RX15N PCIE_TX15N H32 PEG_RX7_DP PEG_RX7_DN PEG_RX8_DP PEG_RX8_DN PEG_RX9_DP PEG_RX9_DN PEG_C_RX3_DP PEG_C_RX3_DN PEG_C_RX4_DP PEG_C_RX4_DN PEG_C_RX5_DP PEG_C_RX5_DN PEG_C_RX6_DP PEG_C_RX6_DN PEG_C_RX7_DP PEG_C_RX7_DN PEG_C_RX8_DP PEG_C_RX8_DN PEG_C_RX9_DP PEG_C_RX9_DN PEG_C_RX10_DP PEG_C_RX10_DN PEG_C_RX11_DP PEG_C_RX11_DN PEG_C_RX12_DP PEG_C_RX12_DN PEG_C_RX13_DP PEG_C_RX13_DN 42D4 42D4 42D4 42D4 42D4 C 42D4 42D4 42D4 42D4 42D4 42D4 34D7 2 B 42C1 34B5 BI BI PCI EXPRESS INTERFACE 42B1 BI BI BI BI BI BI PEG_C_RX14_DP PEG_C_RX14_DN PEG_C_RX15_DP PEG_C_RX15_DN B 42D4 42D4 CLOCK 48C3 48C3 TXOUT_U3P AF35 TXOUT_U3N AG36 BI BI CLK_PEG_REF_DP CLK_PEG_REF_DN AB35 PCIE_REFCLKP AA36 PCIE_REFCLKN PVPCIE CALIBRATION 1 R5039 2 AH16 PWRGOOD AA30 PERSTB PCIE_CALRP Y30 GPU_PCIE_CALRP R5035 1 2 1.27K_1%_2 PCIE_CALRN Y29 GPU_PCIE_CALRN R5034 1 2 2K_1%_2 1K_5%_2 LVTMDP AR34 A TXOUT_L0N_DPE2N AU35 TXOUT_L1P_DPE1P AR37 TXOUT_L1N_DPE1N AU39 TXOUT_L2P_DPE0P AP35 TXOUT_L2N_DPE0N AR35 TXOUT_L3P AN36 TXOUT_L3N AP37 VGA_LVDS_TXDL0_DP VGA_LVDS_TXDL0_DN VGA_LVDS_TXDL1_DP VGA_LVDS_TXDL1_DN VGA_LVDS_TXDL2_DP VGA_LVDS_TXDL2_DN BI BI BI BI 34A8 BI BI 34A8 BI BI 34A8 2 34A8 A AMD_216_0833002_FCBGA_962P P3V3S_DGPU 34A8 34A8 U5005 27C3 21E3 27C7 51A8 28C3 IN 51B6 51C7 IN 34A8 BUF_PLT_RST# 1 4 DGPU_PERST DGPU_HOLD_RST#2 TC7SZ08FU INVENTEC 3 TXOUT_L0P_DPE2P AW37 0_5%_2_DY R5013 1 34A8 5 TXCLK_LN_DPE3N VGA_LVDS_TXCL_DP VGA_LVDS_TXCL_DN + AP34 - TXCLK_LP_DPE3P TITLE MODEL,PROJECT,FUNCTION Block Diagram AMD_216_0833002_FCBGA_962P SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 57 REV X01 68 of 1 7 6 4 5 3 U5001 30 31 32 33 C 34 35 36 37 38 39 40 41 42 43 44 P1V5S_DGPU 45 46 48 40.2_1%_2 49 50 51 52 53 55 0.1UF_16V_2 C5204 2 100_1%_2 R5045 40.2_1%_2 2 R5053 2 1 B P1V5S_DGPU 1 54 1 2 R5052 1 47 56 57 58 59 60 61 62 63 P1V05_REFDA_GPU P1V05_REFSA_GPU DQA0_14/DQA_14 E28 DQA0_15/DQA_15 D27 DQA0_16/DQA_16 F26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 A32 DQMA<0> C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 DQMA<1> A26 DQA0_19/DQA_19 WCKA0_1/DQMA_2 D23 DQMA<2> WCKA0B_1/DQMA_3 E22 DQMA<3> F24 H16 MAA1_6/MAA_14_BA0 J17 MAA1_7/MAA_A15_BA1 DQA0_20/DQA_20 H17 C24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 C14 DQMA<4> A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 DQMA<5> E24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 E10 DQMA<6> C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 A22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 D9 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 C34 DQSA0_DP D21 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D29 DQSA1_DP A20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 D25 DQSA2_DP F20 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E20 DQSA3_DP EDCA1_0/QSA_4/RDQSA_4 E16 DQSA4_DP DQA0_30/DQA_30 E18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 E12 DQSA5_DP C18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 J10 DQSA6_DP A18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 D7 F18 DQA1_2/DQA_34 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 A34 DQSA0_DN A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 DQSA1_DN F16 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 E26 DQSA2_DN D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 DQSA3_DN E14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C16 DQSA4_DN DDBIA1_1/QSA_5B/WDQSA_5 C12 DQSA5_DN DQA1_8/DQA_40 D13 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 J11 DQSA6_DN F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 A12 DQA1_11/DQA_43 D11 DQA1_12/DQA_44 ADBIA0/ODTA0 J21 F10 DQA1_13/DQA_45 ADBIA1/ODTA1 G19 A10 DQA1_14/DQA_46 C10 DQA1_15/DQA_47 CLKA0 H27 G13 DQA1_16/DQA_48 CLKA0B G27 H13 DQA1_17/DQA_49 J13 DQA1_18/DQA_50 CLKA1 H11 DQA1_19/DQA_51 CLKA1B G10 DQA1_20/DQA_52 J14 H14 G8 DQA1_21/DQA_53 RASA0B K23 K9 DQA1_22/DQA_54 RASA1B K19 K10 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI DQSA7_DP D17 F14 OUT OUT OUT DQMA<7> F22 D19 12 12 MAA_BA<2> MAA_BA<0> MAA_BA<1> BI BI BI BI BI BI BI BI DQSA7_DN ODTA0 ODTA1 BI BI CLKA0_DP CLKA0_DN OUT OUT CLKA1_DP CLKA1_DN OUT OUT RASA0# RASA1# OUT OUT G9 DQA1_24/DQA_56 CASA0B K20 A8 DQA1_25/DQA_57 CASA1B K17 C8 DQA1_26/DQA_58 E8 DQA1_27/DQA_59 CSA0B_0 K24 A6 DQA1_28/DQA_60 CSA0B_1 K27 C6 DQA1_29/DQA_61 E6 DQA1_30/DQA_62 CSA1B_0 M13 A5 DQA1_31/DQA_63 CSA1B_1 K16 L18 MVREFDA CKEA0 K21 L20 MVREFSA CKEA1 J20 R5050 1 2 N12 RSC_0402_DY 2240_1%_2 AG12 2 M12 RSC_0402_DY 2240_1%_2 M27 2240_1%_2 AH12 63D8 13 62D4 62D7 63D4 63D8 14 62D4 62D7 63D4 63D8 15 16 62C7 17 62C7 18 62C4 19 62C4 20 63C4 21 63C4 22 63C8 23 63C8 24 25 62C7 26 62C7 27 62C4 28 62C4 29 63C4 30 63C4 31 63C8 32 63C8 33 34 62C7 35 62C7 36 62C4 37 62C4 38 63C4 39 63C4 40 63C8 41 63C8 42 43 62C4 62C7 44 63C4 63C8 45 46 62B3 62D4 62B5 62C7 62C4 47 62D7 CASA0# CASA1# OUT OUT CSA0#_0 OUT 49 63B4 63D4 63D8 63B5 63C8 63D4 62C4 62C7 63C4 63C8 62C4 62C7 63C4 63C8 62C4 62C7 P1V5S_DGPU CSA1#_0 OUT CKEA0 CKEA1 OUT OUT MEM_CALRN0 WEA0B K26 MEM_CALRN1 WEA1B L15 WEA0# WEA1# MAA0_8 H23 MAA<13> MAA1_8 J19 63C4 63C8 62C4 62C7 63C4 63C8 OUT OUT 62C4 62C7 63C4 63C8 OUT 62D4 63D4 62D8 63D8 MEM_CALRN2 MEM_CALRP1 MEM_CALRP0 MEM_CALRP2 48 P1V5S_DGPU 50 51 52 53 54 55 57 58 59 60 61 62 63 P1V05_REFDB_GPU P1V05_REFSB_GPU MAB0_3/MAB_3 F1 DQB0_4/DQB_4 MAB0_4/MAB_4 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 F5 DQB0_6/DQB_6 G4 DQB0_7/DQB_7 H5 DQB0_8/DQB_8 H6 DQB0_9/DQB_9 J4 DQB0_10/DQB_10 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 K6 DQB0_11/DQB_11 K5 DQB0_12/DQB_12 L4 DQB0_13/DQB_13 M6 DQB0_14/DQB_14 M1 DQB0_15/DQB_15 M3 DQB0_16/DQB_16 M5 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H3 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1 P6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T3 WCKB0B_1/DQMB_3 T5 P5 MAB1_3/MAB_11 MAB1_4/MAB_12 DQB0_20/DQB_20 MAB1_5/BA2 AA8 MAB1_6/BA0 Y8 MAB1_7/BA1 AA9 R4 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AE4 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5 T1 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK6 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5 V6 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 V1 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 Y6 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 Y1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 Y3 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AA4 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AB1 DQB1_2/DQB_34 R5012 1 1 2 5.11K_1%_2_DY R5022 OPEN R5048 OPEN SEYMOUR TP13 TP30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AD5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AF1 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AG4 DQB1_11/DQB_43 AH5 DQB1_12/DQB_44 ADBIB0/ODTB0 T7 AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7 AJ4 DQB1_14/DQB_46 AK3 DQB1_15/DQB_47 CLKB0 L9 AF8 DQB1_16/DQB_48 CLKB0B L8 AF9 DQB1_17/DQB_49 CLKB1 DQB1_19/DQB_51 CLKB1B AD7 DQB1_20/DQB_52 AL7 DQB1_21/DQB_53 RASB0B T10 AM8 DQB1_22/DQB_54 RASB1B Y10 AM7 DQB1_23/DQB_55 11 D 12 DQB1_24/DQB_56 CASB0B W10 AL4 DQB1_25/DQB_57 CASB1B AA10 AM6 DQB1_26/DQB_58 AM1 DQB1_27/DQB_59 CSB0B_0 P10 AN4 DQB1_28/DQB_60 CSB0B_1 L10 AP3 DQB1_29/DQB_61 AP1 DQB1_30/DQB_62 CSB1B_0 AD10 AP5 DQB1_31/DQB_63 CSB1B_1 AC10 Y12 MVREFDB AA12 MVREFSB U10 CKEB1 AA11 WEB0B N10 WEB1B AB11 MAB0_8 T8 MAB1_8 W8 DRAM_RST AMD_216_0833002_FCBGA_962P CLKB1_DP CLKB1_DN CASB0# CASB1# CSB0#_0 CKEB0 CSB1#_0 CKEB0 CKEB1 WEB0# WEB1# MAB<13> AH11 1R5029 OUT OUT OUT 64D7 65D4 BI BI BI BI BI BI BI BI 64C7 BI BI BI BI BI BI BI BI 64C7 BI BI BI BI BI BI BI BI 64C7 65D8 64C4 64C4 64C7 65C4 65C4 65C8 65C8 64C4 64C4 64C7 65C4 65C4 65C8 65C8 C 64C4 64C4 64C7 65C4 65C4 65C8 65C8 64C4 65C4 64C7 65C8 OUT OUT 64B3 64D4 64D7 64B5 64C4 64C7 OUT OUT 65B4 65D4 65D8 65B5 65C8 65D4 OUT OUT 64C4 64C7 65C4 65C8 OUT OUT 64C4 64C7 65C4 65C8 OUT 64C4 64C7 OUT 65C4 65C8 OUT OUT 64C4 64C7 65C4 65C8 OUT OUT 64C4 64C7 65C4 65C8 OUT 64D4 64D7 1R5032 2 10_5%_2 64D4 64D7 65D4 65D8 64D4 64D7 65D4 65D8 64D4 BI BI RASB0# RASB1# AK1 AMD_216_0833002_FCBGA_962P R5022 STUFF 9 10 CLKB0_DP CLKB0_DN DQB1_18/DQB_50 CLKTESTB 8 ODTB0 ODTB1 AK9 CLKTESTA 7 G7 AG7 AL10 6 DQMB<0> DQMB<1> DQMB<2> DQMB<3> DQMB<4> DQMB<5> DQMB<6> DQMB<7> AD8 AK10 5 MAB_BA<2> MAB_BA<0> MAB_BA<1> AG8 TESTEN 4 DQSB0_DN K1 DQSB1_DN P1 DQSB2_DN W4 DQSB3_DN AC4 DQSB4_DN AH3 DQSB5_DN AJ8 DQSB6_DN AM3 DQSB7_DN DDBIB0_0/QSB_0B/WDQSB_0 AD28 3 DQSB0_DP K3 DQSB1_DP P3 DQSB2_DP V5 DQSB3_DP AB5 DQSB4_DP AH1 DQSB5_DP AJ9 DQSB6_DP AM5 DQSB7_DP DQB1_3/DQB_35 65D4 64D4 64D7 65D8 OUT 2 F6 AB3 P3V3S_DGPU THAMES A 56 2 R5024 R5048 1 R5047 1 L27 GDDR5 0.1UF_16V_2 1 C5205 2 100_1%_2 1 R5023 2 R5058 1 2240_1%_2 63D4 DQA1_23/DQA_55 P1V5S_DGPU R5033 1 R5022 1 62D7 62D4 MAB0_2/MAB_2 DQB0_3/DQB_3 MAB<12..0> B 65D4 2 VM_RESET 65D8 OUT 51_5%_2 120PF_50V_2 29 A28 MAA1_5/MAA_13_BA2 11 DQB0_2/DQB_2 E1 1 28 DQA0_13/DQA_13 10 11 E3 C5200 27 J16 DQA0_12/DQA_12 C28 10 1 2 26 MAA1_4/MAA_12 DQA0_11/DQA_11 F28 9 0 T9 1 25 MAA1_3/MAA_11 G16 9 P8 MAB0_1/MAB_1 2 R5025 24 MAA1_2/MAA_10 A30 8 MAB0_0/MAB_0 DQB0_1/DQB_1 5.1K_1%_2 23 DQA0_10/DQA_10 L13 8 MAB<0> MAB<1> MAB<2> P9 MAB<3> N7 MAB<4> N8 MAB<5> N9 MAB<6> U9 MAB<7> U8 MAB<8> Y9 MAB<9> W9 AC8 MAB<10> AC9 MAB<11> AA7 MAB<12> DQB0_0/DQB_0 C3 GDDR5 22 H20 DQA0_9/DQA_9 C30 7 1 21 MAA1_1/MAA_9 F30 7 DDR2 GDDR5/GDDR3 DDR3 C5 1K_5%_2 20 H19 DQA0_8/DQA_8 6 1 19 MAA1_0/MAA_8 D31 5 6 2 18 G21 DQA0_7/DQA_7 5 0.1UF_16V_2 17 MAA0_7/MAA_7 DQA0_6/DQA_6 E32 4 40.2_1%_2 16 MAA0_6/MAA_6 H21 DQA0_5/DQA_5 F32 4 C5201 15 MAA0_5/MAA_5 J26 100_1%_2 14 H26 1 13 MAA0_4/MAA_4 3 0.1UF_16V_2 12 DQA0_4/DQA_4 D33 2 3 R5001 11 G32 2 1 2 10 D J24 R5002 9 H24 MAA0_3/MAA_3 0 1 2 8 MAA0_2/MAA_2 DQA0_3/DQA_3 BI DQB<0> DQB<1> DQB<2> DQB<3> DQB<4> DQB<5> DQB<6> DQB<7> DQB<8> DQB<9> DQB<10> DQB<11> DQB<12> DQB<13> DQB<14> DQB<15> DQB<16> DQB<17> DQB<18> DQB<19> DQB<20> DQB<21> DQB<22> DQB<23> DQB<24> DQB<25> DQB<26> DQB<27> DQB<28> DQB<29> DQB<30> DQB<31> DQB<32> DQB<33> DQB<34> DQB<35> DQB<36> DQB<37> DQB<38> DQB<39> DQB<40> DQB<41> DQB<42> DQB<43> DQB<44> DQB<45> DQB<46> DQB<47> DQB<48> DQB<49> DQB<50> DQB<51> DQB<52> DQB<53> DQB<54> DQB<55> DQB<56> DQB<57> DQB<58> DQB<59> DQB<60> DQB<61> DQB<62> DQB<63> 1 7 DQA0_2/DQA_2 E34 OUT 1 2 6 A35 0 40.2_1%_2 5 J23 C5202 4 MAA0_1/MAA_1 100_1%_2 3 MAA0_0/MAA_0 DQA0_1/DQA_1 DQB<63..0> 1 2 DQA0_0/DQA_0 C35 MAA<12..0> R5020 1 MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> 1 2 0 G24 R5021 BI DDR2 GDDR3/GDDR5 DDR3 C37 2 62D1 63D1 DDR2 GDDR5/GDDR3 DDR3 MEMORY INTERFACE A 62D5 63D5 DQA<0> DQA<1> DQA<2> DQA<3> DQA<4> DQA<5> DQA<6> DQA<7> DQA<8> DQA<9> DQA<10> DQA<11> DQA<12> DQA<13> DQA<14> DQA<15> DQA<16> DQA<17> DQA<18> DQA<19> DQA<20> DQA<21> DQA<22> DQA<23> DQA<24> DQA<25> DQA<26> DQA<27> DQA<28> DQA<29> DQA<30> DQA<31> DQA<32> DQA<33> DQA<34> DQA<35> DQA<36> DQA<37> DQA<38> DQA<39> DQA<40> DQA<41> DQA<42> DQA<43> DQA<44> DQA<45> DQA<46> DQA<47> DQA<48> DQA<49> DQA<50> DQA<51> DQA<52> DQA<53> DQA<54> DQA<55> DQA<56> DQA<57> DQA<58> DQA<59> DQA<60> DQA<61> DQA<62> DQA<63> 1 U5001 DDR2 GDDR3/GDDR5 DDR3 DQA<63..0> 2 MEMORY INTERFACE B 8 A R5048 STUFF INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 58 REV X01 68 of 1 8 7 6 5 4 3 2 1 F F U5001 P1V5S_DGPU MEM I/O P1V8S_DGPU PCIE PCIE_VDDC#10 R28 VDDR1#21 PCIE_VDDC#11 T28 L16 VDDR1#22 PCIE_VDDC#12 U28 L21 VDDR1#23 L23 VDDR1#24 L26 VDDR1#25 VDDR4#6 VDDC#39 T20 VDDC#40 T22 VDDC#41 T24 U18 M21 NC_VSSRHA VDDC#45 U21 VDDC#46 U23 VDDC#47 U26 V12 NC_VDDRHB VDDC#48 V17 U12 NC_VSSRHB VDDC#49 V20 VDDC#50 V22 VDDC#51 V24 VDDC#52 V27 VDDC#53 Y16 VDDC#54 Y18 VDDC#55 Y21 VDDC#56 Y23 P1V8S_SPV18 0.1UF_16V_2 1 2 C5208 1 2 1UF_6.3V_2 C5207 1 2 C5206 10UF_6.3V_3 FBM_11_160808_121T PLL H7 MPV18#1 VDDC#57 Y26 H8 MPV18#2 VDDC#58 Y28 10UF_6.3V_3 1 2 C5115 1UF_6.3V_2 1 2 C5114 1UF_6.3V_2 1 2 C5113 1UF_6.3V_2 1 10UF_6.3V_3 1 1 1 C5136 2 2 1UF_6.3V_2 1 1 1UF_6.3V_2 C5135 1UF_6.3V_2 2 C5134 1UF_6.3V_2 1 1 1 2 C5133 1UF_6.3V_2 1 C5132 2 1UF_6.3V_2 1UF_6.3V_2 1 2 C5154 1UF_6.3V_2 1 1 2 C5146 1UF_6.3V_2 1 C 1 2 VDDC#44 2 1 NC_VDDRHA C5166 0.1UF_16V_2 L5015 U16 M20 1UF_6.3V_2 P1V8S_DGPU 1 2 C5107 1UF_6.3V_2 1 C5105 2 10UF_6.3V_3 2 C5104 C 1 FBM_11_160808_121T VDDC#43 2 T27 VDDC/BIF_VDDC#42 10UF_6.3V_3 T17 AG11 1 R26 VDDC#38 10UF_6.3V_3 VDDC#37 VDDR4#3 1 R23 VDDR4#2 AF12 C5159 VDDC#36 10UF_6.3V_3 R21 VDDR4#1 P1V8S_MPV 2 R18 VDDC#35 AF11 L5014 1 VDDC#34 AD12 P1V8S_DGPU PVDDCORE_DGPU N27 C5153 N24 VDDC/BIF_VDDC#33 2 VDDC#32 VDDR4#8 1 M26 VDDR4#7 AG15 C5165 VDDC#31 2 VDDR4#5 AG13 1UF_6.3V_2 AH28 AF15 10UF_6.3V_3 VDDC#30 1 0.1UF_16V_2 1 2 C5108 0.1UF_16V_2 1 2 C5103 1UF_6.3V_2 1 C5102 2 2 C5106 1 FBM_11_160808_121T VDDR4#4 2 AH27 AF13 2 P1V8S_VDDR4 2 1UF_6.3V_2 1 1 AH22 VDDC#29 L5010 C5164 AG21 VDDC#28 2 VDDC#27 C5152 AG18 VDDR3#4 1UF_6.3V_2 VDDC#26 10UF_6.3V_3 VDDR3#3 AG24 1 AG16 AG23 2 VDDC#25 D 1 VDDR3#2 C5163 AF22 AF24 2 VDDC#24 C5266 0.1UF_16V_2 1UF_6.3V_2 P1V8S_DGPU VDDR3#1 C5151 AF20 AF23 2 AF17 VDDC#23 1UF_6.3V_2 AD26 VDDC#22 I/O 10UF_6.3V_3 AD23 VDDC#21 C5145 VDDC#20 1 VDD_CT#4 C5150 AG27 2 AD21 1 VDDC#19 C5161 VDD_CT#3 2 AD18 AG26 1 2 C5101 1UF_6.3V_2 2 C5100 1UF_6.3V_2 1 1 2 C5099 10UF_6.3V_3 2 C5098 AC27 VDDC#18 POWER 1 P3V3S_DGPU VDDC#17 VDD_CT#2 1UF_6.3V_2 AC24 VDD_CT#1 AF27 1UF_6.3V_2 AC22 VDDC#16 AF26 1UF_6.3V_2 AC20 VDDC#15 LEVEL TRANSLATION 10UF_6.3V_3 AC17 VDDC#14 1 AB28 VDDC#13 C5130 AB26 VDDC#12 2 AB23 VDDC#11 1 VDDC#10 C5144 AB21 VDDR1#34 2 VDDC#9 1 AB18 VDDR1#33 C5148 AB16 VDDC#8 2 VDDC#7 VDDR1#32 C5160 AA27 VDDR1#31 2 VDDC#6 1UF_6.3V_2 VDDR1#30 U11 1UF_6.3V_2 AA24 R11 1UF_6.3V_2 VDDC#5 1 VDDR1#29 C5129 AA22 P7 2 VDDC#4 1 VDDR1#28 C5143 AA20 N11 2 AA17 VDDC#3 CORE 1 VDDC#2 VDDR1#27 C5147 AA15 VDDR1#26 2 VDDC#1 L7 Y7 E PVCORE_DGPU M11 U7 C5126 N28 VDDR1#20 L12 2 PCIE_VDDC#9 BLM18PG221SN1D 1UF_6.3V_2 VDDR1#19 2 M28 K13 C5125 L28 PCIE_VDDC#8 1UF_6.3V_2 PCIE_VDDC#7 VDDR1#18 2 VDDR1#17 C5124 PCIE_VDDC#6 J9 K11 1UF_6.3V_2 VDDR1#16 J30 1 J29 C5123 PCIE_VDDC#5 2 VDDR1#15 J7 1UF_6.3V_2 H30 H10 1 PCIE_VDDC#4 2 PVPCIE 1 VDDR1#14 C5120 H29 G29 2 G31 PCIE_VDDC#3 0.1UF_16V_2 PCIE_VDDC#2 VDDR1#13 1 VDDR1#12 G26 C5119 PCIE_VDDC#1 G23 2 VDDR1#11 G30 Y11 D AB37 2 VDDR1#10 G20 C5112 G17 PCIE_VDDR/PCIE_PVDD 2 VDDR1#9 C5122 Y31 G14 0.1UF_16V_2 PCIE_VDDR#8 1UF_6.3V_2 VDDR1#8 1 W30 G11 C5111 W29 PCIE_VDDR#7 2 V28 PCIE_VDDR#6 VDDR1#7 1 PCIE_VDDR#5 VDDR1#6 AL9 C5121 VDDR1#5 AK8 2 AJ7 0.01UF_50V_2 AA34 0.1UF_16V_2 PCIE_VDDR#4 1 VDDR1#4 C5110 AA33 AG10 1 2 AA32 PCIE_VDDR#3 1 1UF_6.3V_2 PCIE_VDDR#2 VDDR1#3 1UF_6.3V_2 1 2 C5097 1UF_6.3V_2 C5096 2 1UF_6.3V_2 1 1 2 C5095 1UF_6.3V_2 1 2 C5094 10UF_6.3V_3 2 C5093 FBM_11_160808_121T PCIE_VDDR#1 VDDR1#2 AF7 C5265 P1V8S_VDDCT 2 1 1 VDDR1#1 AD11 L5013 P1V8S_PCIE_VDDR 2 1.8V_110MA 1.8V_504MA AA31 K8 P1V8S_DGPU L5009 C5086 1 10UF_6.3V_3 1 C5092 2 10UF_6.3V_3 1 2 C5091 10UF_6.3V_3 1 C5090 2 10UF_6.3V_3 1 2 C5089 10UF_6.3V_3 1 C5088 2 10UF_6.3V_3 2 C5087 1 E 2 1UF_6.3V_2 1 C5085 2 1UF_6.3V_2 1 2 C5084 1UF_6.3V_2 1 2 C5083 1UF_6.3V_2 1 2 C5082 1UF_6.3V_2 1 2 C5081 1UF_6.3V_2 1 2 C5080 1UF_6.3V_2 1 2 C5079 1UF_6.3V_2 1 C5078 2 2 C5077 1UF_6.3V_2 1 AC7 FB_GND N15 VDDCI#13 N17 VDDCI#14 N20 VDDCI#15 N22 VDDCI#16 R12 VDDCI#17 R13 VDDCI#18 R16 VDDCI#19 T12 VDDCI#20 T15 VDDCI#21 V15 VDDCI#22 Y13 1UF_6.3V_2 1 2 C5197 1 2 1UF_6.3V_2 C5195 1UF_6.3V_2 1 2 C5193 1UF_6.3V_2 2 C5192 1UF_6.3V_2 1 1 2 C5191 1UF_6.3V_2 1 C5190 2 1UF_6.3V_2 1 C5189 B 1 N13 2 M23 VDDCI#11 VDDCI#12 1 M18 VDDCI#10 1UF_6.3V_2 M16 VDDCI#9 10UF_6.3V_3 AH29 M15 VDDCI#8 C5169 ISOLATED CORE I/O AD16 VDDCI#7 2 FB_VDDCI AD13 VDDCI#6 10UF_6.3V_3 AG28 AC15 VDDCI#5 C5168 FB_VDDC AC12 VDDCI#4 2 AF28 AB13 VDDCI#3 10UF_6.3V_3 VOLTAGE SENESE AA13 VDDCI#2 C5188 1 2 0.1UF_16V_2 C5213 1UF_6.3V_2 1 C5210 2 2 10UF_6.3V_3 1 C5209 SPVSS VDDCI#1 2 SPV10 AN10 FBM_11_160808_121T B AN9 1 PVPCIE_SPV10 C5167 2 SPV18 2 L5016 1 AM10 1 PVCORE_DGPU PVPCIE AMD_216_0833002_FCBGA_962P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 59 1 REV X01 of 68 8 7 6 4 5 3 2 1 U5001 P1V8S_DGPU DP C/D POWER P1V8S_DGPU DP A/B POWER L5019 L5017 60C6 60B3 AP32 AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27 AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27 AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28 AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24 AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25 AP23 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 AP26 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33 AP15 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 AP33 AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29 AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29 AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30 0.1UF_16V_2 C5220 0.1UF_16V_2 C5228 2 1UF_6.3V_2 DPCD_VDD18 IN DPAB_VDD18 2 FBM_11_160808_121T 10UF_6.3V_3 AP31 DPAB/DPA_VDD10#2 1 DPAB/DPA_VDD10#1 DPCD/DPC_VDD10#2 C5222 DPCD/DPC_VDD10#1 AT13 1 2 AP13 DPAB_VDD18 1UF_6.3V_2 AP24 1 AN24 DPAB/DPA_VDD18#2 C5221 DPAB/DPA_VDD18#1 DPCD/DPC_VDD18#2 2 DPCD/DPC_VDD18#1 AP21 1 1 C5227 2 10UF_6.3V_3 1 C5226 2 D AP20 1 DPCD_VDD18 2 2 1 FBM_11_160808_121T D 60C3 60B3 IN PVPCIE PVPCIE L5020 L5018 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30 AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32 AW18 DPCD_CALR DP E/F POWER DPEF_VDD18 2 DPAB_CALR AW28 1 10UF_6.3V_3 2 C5225 1UF_6.3V_2 1 1 C5224 2 2 AH34 DPEF/DPE_VDD18#1 AJ34 DPEF/DPE_VDD18#2 AL33 DPEF/DPE_VDD10#1 AM33 DPEF/DPE_VDD10#2 AN34 AP39 AR39 DP/DPE_VSSR#3 AU37 DP/DPE_VSSR#4 DP PLL POWER DPAB_VDD18/DPA_PVDD DP_VSSR/DPA_PVSS AU28 DPAB_VDD18 AV27 IN 60C3 IN 60C6 0.1UF_16V_2 1 2 C5234 1UF_6.3V_2 1 2 C5233 10UF_6.3V_3 2 C5232 1 FBM_11_160808_121T B 60B3 60B6 C 150_1%_2 L5021 1 2 FBM_11_160808_121T R5040 2 150_1%_2 P1V8S_DGPU 1 1 C5223 R5041 1 0.1UF_16V_2 AW20 DPAB_VDD10 2 0.1UF_16V_2 1 2 C5231 1UF_6.3V_2 2 2 C5230 1 C5229 C 1 DPCD_VDD10 2 10UF_6.3V_3 1 FBM_11_160808_121T DPEF_VDD18 IN DPAB_VDD18/DPB_PVDD AV29 DP_VSSR/DPB_PVSS AR28 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AU18 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AV17 DPCD_VDD18/DPD_PVDD AV19 DP_VSSR/DPD_PVSS AR18 AF34 DPEF/DPF_VDD18#1 AG34 DPEF/DPF_VDD18#2 PVPCIE DPEF_VDD18/DPE_PVDD DP_VSSR/DPE_PVSS AM37 DPCD_VDD18 B DPEF_VDD18 AN38 IN 60B6 L5022 0.1UF_16V_2 2 C5237 1UF_6.3V_2 1 2 C5236 1 2 C5235 1 DPEF_VDD10 2 10UF_6.3V_3 1 FBM_11_160808_121T AK33 DPEF/DPF_VDD10#1 AK34 DPEF/DPF_VDD10#2 DPEF_VDD18/DPF_PVDD DP_VSSR/DPF_PVSS AF39 DP/DPF_VSSR#1 AH39 DP/DPF_VSSR#2 AK39 DP/DPF_VSSR#3 AL34 DP/DPF_VSSR#4 AM34 DP/DPF_VSSR#5 AM39 DPEF_CALR AL38 AM35 R5042 A 1 2 A 150_1%_2 AMD_216_0833002_FCBGA_962P INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 60 REV X01 68 of 1 8 7 6 5 4 3 2 1 F F U5001 E AB39 PCIE_VSS#1 GND#1 A3 E39 PCIE_VSS#2 GND#2 A37 F34 PCIE_VSS#3 GND#3 AA16 F39 PCIE_VSS#4 GND#4 AA18 G33 PCIE_VSS#5 GND#5 AA2 G34 PCIE_VSS#6 GND#6 AA21 H31 PCIE_VSS#7 GND#7 AA23 H34 PCIE_VSS#8 GND#8 AA26 H39 PCIE_VSS#9 GND#9 AA28 J31 PCIE_VSS#10 GND#10 J34 PCIE_VSS#11 GND#11 K31 PCIE_VSS#12 GND#12 AB15 PCIE_VSS#13 GND#13 AB17 K39 PCIE_VSS#14 GND#14 AB20 L31 PCIE_VSS#15 GND#15 AB22 L34 PCIE_VSS#16 GND#16 AB24 M34 PCIE_VSS#17 GND#17 AB27 M39 PCIE_VSS#18 GND#18 AC11 N31 PCIE_VSS#19 GND#19 AC13 N34 PCIE_VSS#20 GND#20 AC16 P31 PCIE_VSS#21 GND#21 AC18 P34 PCIE_VSS#22 GND#22 AC2 P39 PCIE_VSS#23 GND#23 AC21 R34 PCIE_VSS#24 GND#24 AC23 T31 PCIE_VSS#25 GND#25 AC26 T34 PCIE_VSS#26 GND#26 AC28 T39 PCIE_VSS#27 GND#27 AC6 U31 PCIE_VSS#28 GND#28 AD15 U34 PCIE_VSS#29 GND#29 AD17 V34 PCIE_VSS#30 GND#30 AD20 V39 PCIE_VSS#31 GND#31 AD22 W31 PCIE_VSS#32 GND#32 AD24 W34 PCIE_VSS#33 GND#33 AD27 Y34 PCIE_VSS#34 GND#34 AD9 Y39 PCIE_VSS#35 GND#35 AE2 GND#36 AE6 GND#37 AF10 GND#38 AF16 GND#39 AF18 GND#40 AF21 GND#41 AG17 F15 GND#100 GND#42 AG2 F17 GND#101 GND#43 AG20 F19 GND#102 GND#44 AG22 F21 GND#103 GND#45 AG6 F23 GND#104 GND#46 AG9 F25 GND#105 GND#47 AH21 F27 GND#106 GND#48 AJ10 F29 GND#107 GND#49 AJ11 F31 GND#108 GND#50 AJ2 F33 GND#109 GND#51 AJ28 F7 GND#110 GND#52 AJ6 F9 GND#111 GND#53 AK11 G2 GND#112 GND#54 AK31 G6 GND#113 GND#55 AK7 H9 GND#114 GND#56 AL11 J2 GND#115 GND#57 AL14 GND#116 GND#58 AL17 J6 GND#117 GND#59 AL2 J8 GND#118 GND#60 AL20 K14 GND#119 J27 GND#121 GND#63 AL26 GND#122 GND#64 AL32 GND#123 GND#65 AL6 L22 GND#124 GND#66 AL8 L24 L17 GND#120 GND#125 GND#67 AM11 L6 GND#126 GND#68 AM31 M17 GND#127 GND#69 AM9 M22 GND#128 GND#70 AN11 M24 GND#129 GND#71 AN2 N16 GND#130 GND#72 AN30 N18 GND#131 GND#73 AN6 GND#132 GND#74 AN8 N21 GND#133 GND#75 AP11 N23 GND#134 GND#76 AP7 N26 GND#135 GND#77 AP9 N2 GND#136 GND#78 AR5 R15 GND#137 GND#79 B11 R17 GND#138 GND#80 B13 GND#139 GND#81 B15 R20 GND#140 GND#82 B17 R22 GND#141 GND#83 B19 R24 GND#142 GND#84 B21 R27 GND#143 GND#85 B23 GND#144 GND#86 B25 T11 GND#145 GND#87 B27 T13 GND#146 GND#88 B29 T16 GND#147 GND#89 B31 T18 GND#148 GND#90 B33 T21 GND#149 GND#91 B7 T23 GND#150 GND#92 B9 T26 GND#151 GND#93 C1 U15 GND#153 GND#94 C39 U17 GND#154 GND#95 E35 GND#155 GND#96 E5 U20 GND#156 GND#97 F11 U22 GND#157 GND#98 F13 U24 GND#158 U27 GND#159 N6 R2 R6 U2 U6 E D PX_EN AL21 AL23 L11 L2 B GND/PX_EN#61 GND#62 K7 C AB12 K34 GND D AA6 IN C B GND#160 V11 GND#161 V16 GND#163 V18 GND#164 V21 GND#165 V23 GND#166 V26 GND#167 W2 GND#168 W6 GND#169 Y15 GND#170 Y17 GND#171 Y20 GND#172 Y22 GND#173 VSS_MECH#1 A39 Y24 GND#174 VSS_MECH#2 AW1 Y27 GND#175 VSS_MECH#3 AW39 U13 GND#152 V13 GND#162 AMD_216_0833002_FCBGA_962P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 61 1 REV X01 of 68 7 IN IN 62A7 63D8 63D4 62D4 58D4 58A5 BI MAA<13..0> 0 1 2 3 4 5 6 7 8 9 10 11 12 D 13 63D8 63D4 62D4 58D5 63D8 63D4 62D4 58D5 63D8 63D4 62D4 62D4 58D5 62B3 62C4 58B5 62B5 58B5 62C4 58B5 62C4 58C5 62C4 58B5 62C4 58B5 62C4 58B5 62C4 58A5 U5500 VRAM_VREFC_A<0> VRAM_VREFD_A<3> M9 H2 MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13> IN IN IN DQL1 F8 DQL2 A0 DQL3 F9 P8 A1 DQL4 H4 P4 A2 DQL5 H9 DQL6 G3 DQL7 H8 A3 58C5 C 58D5 58D5 58C5 58C5 BI BI BI BI 65C4 64C7 64C4 63C8 63C4 62C4 58A1 58D4 58A5 BI MAA<13..0> 0 58D8 1 58D8 2 58D8 3 58D8 4 R3 A7 DQU0 D8 T9 A8 DQU1 C4 R4 A9 DQU2 C9 L8 A10_AP DQU3 C3 R8 A11 DQU4 A8 N8 A12 DQU5 A3 DQU6 B9 DQU7 A4 A13 T8 A14 M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 BA2 CK CK DQA<12> DQA<13> DQA<9> DQA<15> DQA<8> DQA<14> DQA<10> DQA<11> BI BI BI BI BI BI BI BI 58D8 7 58D8 8 58D8 9 58D8 10 58D8 11 58D8 12 58D8 13 63D8 63D4 62D7 58D5 D10 63D8 63D4 62D7 58D5 VDD#G8 VDD#K3 K3 VDD#K9 K9 VDD#N2 N2 63D8 63D4 N10 VDD#N10 62D7 62D7 R2 VDD#R2 62C7 P1V5S_DGPU 58D5 62B3 58B5 62B5 58B5 62C7 58B5 CKE_CKE0 VDD#R10 R10 K2 ODT VDDQ#A2 A2 62C7 58C5 L3 CS VDDQ#A9 A9 62C7 58B5 C2 62C7 58B5 C10 62C7 58B5 D3 62C7 58A5 J4 RAS VDDQ#C2 K4 CAS VDDQ#C10 L4 WE VDDQ#D3 E10 DQSL DQSU VDDQ#F2 F2 VDDQ#H3 H3 E8 DML D4 DMU G4 DQSL B8 DQSU T3 RESET R5509 ZQ_ZQ0 58C5 58C5 58D5 A10 58D5 VSS#B4 B4 VSS#E2 E2 VSS#G9 G9 58C5 VSS#J3 J3 58C5 VSS#J9 J9 VSS#M2 M2 E4 DQL1 F8 DQL2 F3 N4 A0 DQL3 F9 P8 A1 DQL4 H4 P4 A2 DQL5 H9 DQL6 G3 DQL7 H8 A3 P9 A4 P3 A5 R9 A6 R3 A7 DQU0 D8 T9 A8 DQU1 C4 R4 A9 DQU2 C9 L8 A10_AP DQU3 C3 R8 A11 DQU4 A8 N8 A12 DQU5 A3 DQU6 B9 DQU7 A4 A13 T8 A14 M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 M4 BA2 65C8 65C4 64C7 64C4 63C8 63C4 62C7 58A1 P10 N2 BI BI VDD#N10 CK VDD#R2 VDD#R10 R10 ODT VDDQ#A2 A2 CS VDDQ#A9 A9 J4 RAS VDDQ#C2 C2 K4 CAS VDDQ#C10 L4 WE DQSA3_DP DQSA2_DP F4 DQSL VDDQ#F2 F2 C8 DQSU VDDQ#H3 H3 DQSA3_DN DQSA2_DN BI BI E8 DML D4 DMU G4 DQSL B8 DQSU VM_RESET IN T3 RESET R5508 1 L9 ZQ_ZQ0 B2 B10 J2 NC_ODT VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 NC_CE1 L10 NC_ZQ1 G2 VSSQ#G2 G10 A11 NC NC T1 NC NC T11 R5540 R5541 2 1 56_5%_2 F10 VSSQ#F10 VSSQ#G10 A1 IN 1 2 CLKA0_DP 58B5 62D7 IN 56_5%_2 2 J10 B H10 VSS#A10 A10 VSS#B4 VSS#E2 E2 VSS#G9 G9 VSS#J3 J3 VSS#J9 J9 VSS#M2 M2 58D8 58D8 58D8 58D8 P1V5S_DGPU 58D8 P10 T2 VSS#T2 VSS#T10 T10 VSSQ#B2 B2 B10 VSSQ#D2 D2 VSSQ#D9 D9 NC_ODT VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 J10 NC_CE1 L10 NC_ZQ1 F10 VSSQ#F10 VSSQ#G2 G2 G10 NC NC T1 NC NC T11 B P1V5S_DGPU R5506 4.99K_1%_2 2 1 1 IN R5507 1 C5503 2 4.99K_1%_2 0.1uF_16V_2 1 VRAM_VREFD_A<1> 62D4 A 1 1 1 1 C5533 C5534 INVENTEC 10UF_6.3V_3 2 2 10UF_6.3V_3 2 1UF_6.3V_2 C5532 1UF_6.3V_2 C5531 2 1UF_6.3V_2 C5530 2 2 C5529 1UF_6.3V_2 2 1UF_6.3V_2 10UF_6.3V_3 2 10UF_6.3V_3 1 1 C5528 1 1 C5527 2 2.2UF_6.3V_2 1 2 C5525 1 1UF_6.3V_2 2 C5524 1UF_6.3V_2 1 C5523 2 1UF_6.3V_2 1 2 C5522 1 1UF_6.3V_2 C5521 1 2 C5526 1 P1V5S_DGPU TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 D P2 2 R5505 1 4.99K_1%_2 R5503 1 0.1uF_16V_2 2 C5501 1 2 2 C5502 1 IN 0.1uF_16V_2 4.99K_1%_2 2 VRAM_VREFD_A<3> 4.99K_1%_2 R5501 1 1 R5502 4.99K_1%_2 R5500 1 2 1 0.1uF_16V_2 C5500 2 58D8 M10 VSS#P2 2 R5504 2 VRAM_VREFC_A<2> 62D4 P1V5S_DGPU 1UF_6.3V_2 58D8 P1V5S_DGPU P1V5S_DGPU SAM_K4B1G1646D_HCF7_FBGA_100P IN A C5520 58D8 C B4 J2 A11 P1V5S_DGPU 2 58D8 D3 VDDQ#H10 VSSQ#B10 62D4 A1 P1V5S_DGPU 62D7 58D8 E10 VSSQ#G10 SAM_K4B1G1646D_HCF7_FBGA_100P VRAM_VREFC_A<0> 58D8 2 VSSQ#D9 D9 CLKA0_DN 1 D2 58B5 62C7 C5516 VSSQ#D2 62C4 0.01UF_50V_2 VSSQ#B2 VSSQ#B10 IN 58D8 243_1%_2 243_1%_2 62D7 58D8 58D8 C10 VDDQ#D3 VSS#P10 2 BI BI BI BI BI BI BI BI 58D8 R2 CKE_CKE0 L3 DQMA<3> DQMA<2> BI BI 58D8 N10 CK T10 VSS#T10 K9 VDD#N2 K2 T2 VSS#T2 K3 VDD#K9 VSS#M10 P2 VSS#P2 G8 VDD#K3 ODTA0 CSA0#_0 RASA0# CASA0# WEA0# IN IN IN IN IN DQA<19> DQA<18> DQA<21> DQA<16> DQA<23> DQA<17> DQA<22> DQA<20> BI BI BI BI BI BI BI BI D10 K8 K10 DQA<26> DQA<31> DQA<29> DQA<25> DQA<24> DQA<28> DQA<27> DQA<30> B3 VDD#G8 J8 M10 VSS#P10 L9 DQL0 VREFDQ T4 CLKA0_DP CLKA0_DN CKEA0 IN IN IN VREFCA H2 N3 MAA_BA<0> MAA_BA<1> MAA_BA<2> BI BI BI M9 VDDQ#E10 H10 VSS#A10 MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13> 58D8 P1V5S_DGPU B3 G8 VDDQ#H10 2 62D8 6 C8 1 63D4 A6 F4 VM_RESET IN 63D8 58D8 R9 VSS#M10 65C8 58D8 1 U5501 VRAM_VREFC_A<2> VRAM_VREFD_A<1> 5 K10 DQSA0_DN DQSA1_DN 62B2 58D8 IN IN A5 K8 DQMA<0> DQMA<1> BI BI 62B4 58D8 A4 VDDQ#E10 58C5 BI BI BI BI BI BI BI BI 2 P3 J8 DQSA0_DP DQSA1_DP DQA<3> DQA<0> DQA<4> DQA<2> DQA<6> DQA<1> DQA<5> DQA<7> 3 P9 M4 ODTA0 CSA0#_0 RASA0# CASA0# WEA0# IN IN IN IN IN E4 N4 T4 CLKA0_DP CLKA0_DN CKEA0 VREFDQ DQL0 F3 N3 MAA_BA<0> MAA_BA<1> MAA_BA<2> BI BI BI VREFCA 4 5 4.99K_1%_2 62A8 6 4.99K_1%_2 8 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 62 REV X01 68 of 1 62D8 62D4 58D4 58A5 MAA<13..0> BI 0 1 2 3 4 5 6 7 8 9 10 11 12 D 13 63D4 62D7 62D4 58D5 63D4 62D7 62D4 58D5 63D4 62D7 63D4 63D4 62D4 63B4 58B5 63B5 58B5 63C4 58B5 63C4 58B5 63C4 58B5 63C4 58B5 63C4 58B5 63C4 58A5 H2 VREFDQ DQL1 F8 DQA<51> DQL2 F3 DQA<53> DQL3 F9 DQA<49> A0 P8 A1 DQL4 H4 DQA<52> P4 A2 DQL5 H9 DQA<50> N3 A3 DQL6 G3DQA<55> P9 A4 DQL7 H8 DQA<48> A6 A7 DQU0 D8 DQA<62> T9 A8 DQU1 C4 DQA<60> R4 A9 DQU2 C9 DQA<58> DQU3 C3 DQA<61> A10_AP R8 A11 DQU4 A8 DQA<59> N8 A12 DQU5 A3 DQA<57> T4 A13 DQU6 B9 DQA<56> T8 A14 DQU7 A4 DQA<63> M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 J8 K8 K10 58C5 C DQSA6_DP DQSA7_DP BI BI 58C5 BI BI 58C5 58C5 BI BI 58C5 64C4 63C4 62C7 62C4 65C8 58A1 65C4 IN BA2 CK 2 3 58D8 4 58D8 5 8 58D8 9 58D8 10 58D8 11 58D8 12 58D8 13 P1V5S_DGPU 58D8 62D7 62D4 58D5 62D4 58D5 63D8 VDD#G8 G8 VDD#K3 63D8 R2 63C8 P1V5S_DGPU 63B4 58B5 63B5 58B5 63C8 58B5 58B5 C10 63C8 58B5 D3 63C8 58A5 RAS VDDQ#C2 K4 CAS VDDQ#C10 L4 WE VDDQ#D3 58C5 58C5 VDDQ#H3 H3 E2 G9 58C5 VSS#G9 J3 58C5 VSS#J3 VSS#J9 VSS#M2 DQL6 G3DQA<34> DQL7 H8 DQA<36> A3 P9 A4 P3 A5 R9 A6 R3 A7 DQU0 D8 DQA<44> T9 A8 DQU1 C4 DQA<43> R4 A9 DQU2 C9 DQA<47> L8 A10_AP DQU3 C3 DQA<42> R8 A11 DQU4 A8 DQA<46> N8 A12 DQU5 A3 DQA<40> T4 A13 DQU6 B9 DQA<45> DQU7 A4 DQA<41> T8 A14 M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 M4 BA2 VDD#R10 R10 ODTA1 CSA1#_0 RASA1# CASA1# WEA1# K2 ODT VDDQ#A2 A2 L3 CS VDDQ#A9 A9 J4 RAS VDDQ#C2 C2 K4 CAS VDDQ#C10 L4 WE DQSA4_DP DQSA5_DP F4 DQSL VDDQ#F2 F2 C8 DQSU VDDQ#H3 H3 DQMA<4> DQMA<5> BI BI E8 DML D4 DMU VDDQ#H10 H10 VSS#A10 A10 VSS#B4 B4 J9 VSS#M2 M2 65C4 64C7 64C4 63C8 62C7 62C4 58A1 VM_RESET IN T3 RESET R5518 P10 1 T2 L9 ZQ_ZQ0 63C8 58B5 63D4 NC_ODT VSSQ#E3 L2 NC_CSI VSSQ#E9 E9 1 R5542 R5543 2 1 56_5%_2 2 CLKA1_DP 58B5 63D8 IN 56_5%_2 C5517 D9 CLKA1_DN IN 63D4 F10 2 G2 G10 T10 VSSQ#B2 B2 D2 VSSQ#D9 D9 NC_ODT VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 J10 NC_CE1 L10 NC_ZQ1 C F10 VSSQ#F10 G2 VSSQ#G2 G10 B A11 T11 NC NC T1 NC NC T11 SAM_K4B1G1646D_HCF7_FBGA_100P R5516 4.99K_1%_2 C5507 0.1uF_16V_2 1 IN 2 1 VRAM_VREFD_A<5> 63D4 2 2 1 R5515 1 2 4.99K_1%_2 P1V5S_DGPU 0.1uF_16V_2 C5506 1 IN 2 2 P1V5S_DGPU 4.99K_1%_2 4.99K_1%_2 VRAM_VREFC_A<6> 63D4 2 R5513 1 C5505 2 4.99K_1%_2 0.1uF_16V_2 1 IN 1 VRAM_VREFD_A<7> R5514 2 R5512 4.99K_1%_2 2 R5510 1 D 58D8 P1V5S_DGPU B10 VSSQ#D2 J2 A1 T1 2 1 R5511 0.1uF_16V_2 1 C5504 2 P1V5S_DGPU 58D8 58D8 T2 VSS#T10 VSSQ#G10 P1V5S_DGPU 63D8 58D8 P10 VSS#T2 VSSQ#B10 1 B10 P1V5S_DGPU IN 58D8 58D8 P1V5S_DGPU P1V5S_DGPU 63D8 58D8 243_1%_2 SAM_K4B1G1646D_HCF7_FBGA_100P VRAM_VREFC_A<4> 58D8 P2 VSS#P2 VSS#P10 2 58D8 M10 VSS#M10 65C8 58D8 E10 M2 P2 58D8 D3 J3 M10 58D8 C10 VDDQ#D3 VSS#J9 DQSA4_DN DQSA5_DN BI BI 58D8 58D8 R2 CKE_CKE0 J9 VSSQ#D9 NC K10 BI BI BI BI BI BI BI BI 58D8 N10 G9 D2 NC VDD#R2 VSS#J3 VSSQ#D2 NC CK DQSU B2 NC VDD#N10 B8 VSSQ#B2 VSSQ#G10 CK K8 58D8 D10 E2 T10 VSSQ#G2 J8 BI BI BI BI BI BI BI BI B3 VSS#G9 E3 A11 H9 DQA<39> VSS#E2 J2 B DQL5 DQSL 243_1%_2 NC_ZQ1 A2 G4 VSS#T10 VSSQ#F10 BI BI 58C5 A10 VSS#E2 VSSQ#B10 IN IN IN IN IN 58D5 VSS#B4 VSS#T2 IN IN IN H10 B4 VSS#P10 L10 P4 VDDQ#E10 F2 VSS#P2 CLKA1_DP CLKA1_DN CKEA1 E10 VDDQ#F2 VSS#A10 NC_CE1 H4 DQA<32> N2 N10 63C8 J10 DQL4 K9 C2 ZQ_ZQ0 A1 VDD#N2 J4 RESET P8 N2 58B5 DQSU F9 DQA<37> VDD#N2 58B5 B8 DQL3 K3 63C8 DQSL A0 VDD#K9 63C8 G4 N4 K9 A9 DMU DQL2 F3 DQA<33> VDD#K9 A2 D4 F8 DQA<38> G8 VDDQ#A9 DML E4 DQA<35> DQL1 VDD#K3 58D5 VDDQ#A2 E8 DQL0 VREFDQ K3 62D4 CS DQSU VREFCA H2 VDD#G8 62D7 ODT DQSL MAA_BA<0> MAA_BA<1> MAA_BA<2> BI BI BI 1 M9 N3 58D8 62D7 VDD#R2 CK 7 58D8 BI BI BI BI BI BI BI BI L3 A1 1 58D8 K2 L9 MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13> 0 58D8 63D8 VDD#N10 R5519 2 MAA<13..0> BI R10 T3 1 58A5 63D8 VDDQ#H10 VM_RESET 58D4 D10 VSS#M10 64C7 58D8 62D4 VDD#R10 C8 DQSA6_DN DQSA7_DN 62D8 63D8 CKE_CKE0 F4 DQMA<6> DQMA<7> 58D8 B3 VDDQ#E10 58C5 63A3 58D8 U5503 VRAM_VREFC_A<6> VRAM_VREFD_A<5> IN IN 6 R3 M4 63A4 58D8 BI BI BI BI BI BI BI BI A5 R9 L8 ODTA1 CSA1#_0 RASA1# CASA1# WEA1# IN IN IN IN IN E4 DQA<54> P3 CLKA1_DP CLKA1_DN CKEA1 IN IN IN DQL0 N4 MAA_BA<0> MAA_BA<1> MAA_BA<2> BI BI BI 58D5 MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13> VREFCA 2 4.99K_1%_2 63D4 M9 3 4.99K_1%_2 63A6 U5502 VRAM_VREFC_A<4> VRAM_VREFD_A<7> IN IN 4 5 R5517 63A8 6 1 7 0.01UF_50V_2 8 1 C5549 10UF_6.3V_3 2 2 1UF_6.3V_2 1 1 C5547 C5548 10UF_6.3V_3 2 C5546 2 1UF_6.3V_2 1 1 2 1UF_6.3V_2 C5545 1UF_6.3V_2 C5544 2 2 C5542 1UF_6.3V_2 C5543 1 1 10UF_6.3V_3 2 2 1 2.2UF_6.3V_2 2 C5540 1UF_6.3V_2 1 2 C5539 1 1UF_6.3V_2 C5538 2 1UF_6.3V_2 1 2 C5537 1 1UF_6.3V_2 2 C5536 1 1UF_6.3V_2 C5535 2 C5541 10UF_6.3V_3 1 A 1 A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 63 REV X01 68 of 1 7 IN IN 64A7 65D8 65D4 64D4 58D1 58A1 BI MAB<13..0> 0 1 2 3 4 5 6 7 8 9 10 11 12 D 13 65D8 65D4 64D4 58D1 65D8 65D4 64D4 58D1 65D8 65D4 64D4 64D4 58D1 64B3 64C4 58B1 64B5 58B1 64C4 58B1 64C4 58C1 64C4 58B1 64C4 58B1 64C4 58B1 64C4 58A1 U5504 VRAM_VREFC_B<0> VRAM_VREFD_B<3> M9 H2 MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13> IN IN IN IN IN IN IN IN E4 DQB<31> DQL1 F8 DQB<27> DQL2 N4 A0 DQL3 F9 DQB<25> P8 A1 DQL4 H4DQB<30> P4 A2 DQL5 H9 DQB<24> DQL6 G3DQB<28> DQL7 H8DQB<26> A3 58C1 C 58D1 58D1 58C1 58C1 BI BI 65C4 64C4 63C8 63C4 62C7 62C4 58A1 64B2 58D4 58D4 65D8 65D4 64D7 58D1 58A1 MAB<13..0> BI 58D4 1 58D4 2 58D4 3 58D4 4 R9 A6 6 R3 A7 DQU0 D8 DQB<6> T9 A8 DQU1 C4 DQB<3> R4 A9 DQU2 C9DQB<2> L8 A10_AP DQU3 C3DQB<7> R8 A11 DQU4 A8 DQB<1> N8 A12 DQU5 A3 DQB<4> T4 A13 DQU6 B9 DQB<0> T8 A14 DQU7 A4 DQB<5> M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 K10 BA2 CK 58D4 7 58D4 8 58D4 9 58D4 10 58D4 11 58D4 12 58D4 13 65D8 65D4 64D7 58D1 D10 65D8 65D4 64D7 58D1 VDD#G8 VDD#K3 K3 VDD#K9 K9 VDD#N2 N2 65D8 65D4 N10 CKE_CKE0 VDD#R10 R10 64D7 64D7 R2 VDD#R2 64C7 P1V5S_DGPU 58D1 64B3 58B1 64B5 58B1 64C7 58B1 ODT VDDQ#A2 A2 64C7 58C1 L3 CS VDDQ#A9 A9 64C7 58B1 C2 64C7 58B1 C10 64C7 58B1 D3 64C7 58A1 DQSB3_DP DQSB0_DP F4 RAS VDDQ#C2 K4 CAS VDDQ#C10 L4 WE VDDQ#D3 E10 C8 DQSL DQSU VDDQ#F2 F2 VDDQ#H3 H3 E8 DML D4 DMU G4 DQSL B8 DQSU VM_RESET T3 RESET R5529 1 L9 DQL0 E4 DQB<13> VREFDQ DQL1 F8 DQB<10> DQL2 F3 DQB<9> N4 A0 DQL3 F9 DQB<15> P8 A1 DQL4 H4 DQB<12> P4 A2 DQL5 H9 DQB<14> DQL6 G3DQB<8> DQL7 H8 DQB<11> A3 P9 A4 P3 A5 R9 A6 R3 A7 DQU0 D8 DQB<20> T9 A8 DQU1 C4 DQB<19> R4 A9 DQU2 C9 DQB<23> L8 A10_AP DQU3 C3 DQB<16> R8 A11 DQU4 A8 DQB<21> N8 A12 DQU5 A3 DQB<17> T4 A13 DQU6 B9 DQB<22> T8 A14 DQU7 A4 DQB<18> M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 M4 BA2 VSS#B4 VSS#E2 E2 VSS#G9 G9 58C1 VSS#J3 J3 58C1 VSS#J9 J9 VSS#M2 M2 K9 VDD#N2 N2 CK VDD#R2 VDD#R10 R10 ODTB0 CSB0#_0 RASB0# CASB0# WEB0# K2 ODT VDDQ#A2 A2 L3 CS VDDQ#A9 A9 J4 RAS VDDQ#C2 C2 K4 CAS VDDQ#C10 L4 WE DQSB1_DP DQSB2_DP F4 DQSL VDDQ#F2 F2 C8 DQSU VDDQ#H3 H3 DQSB1_DN DQSB2_DN BI BI DML D4 DMU G4 DQSL B8 DQSU 65C8 65C4 64C7 63C8 63C4 62C7 62C4 58A1 P10 VM_RESET IN T3 1 T2 2 L9 B10 H10 VSS#A10 A10 NC_ODT VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 L10 NC_ZQ1 A11 58B1 64C7 IN 1 R5544 56_5%_2 F10 VSSQ#F10 G2 VSSQ#G2 G10 NC NC T1 NC NC T11 R5545 2 1 2 CLKB0_DP 58B1 64D7 IN 56_5%_2 C5518 NC_CE1 64C4 CLKB0_DN 2 J10 A1 64D4 VSS#B4 VSS#E2 E2 VSS#G9 G9 VSS#J3 J3 VSS#J9 J9 VSS#M2 M2 P1V5S_DGPU T2 VSS#T10 T10 VSSQ#B2 B2 B10 VSSQ#D2 D2 VSSQ#D9 D9 VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 J10 NC_CE1 L10 NC_ZQ1 F10 VSSQ#F10 G2 VSSQ#G2 G10 NC NC T1 NC NC T11 B SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU R5526 4.99K_1%_2 R5527 1 C5511 2 4.99K_1%_2 R5525 2 1 1 IN 0.1uF_16V_2 1 4.99K_1%_2 R5523 1 1 2 2 1 0.1uF_16V_2 C5509 2 A VRAM_VREFD_B<1> 64D4 2 1 IN C5510 1 64D4 0.1uF_16V_2 4.99K_1%_2 2 VRAM_VREFC_B<2> R5522 4.99K_1%_2 VRAM_VREFD_B<3> IN 4.99K_1%_2 R5521 1 D P1V5S_DGPU P1V5S_DGPU 2 R5524 2 R5520 1 2 1 0.1uF_16V_2 C5508 2 58D4 P10 VSS#T2 NC_ODT A11 P1V5S_DGPU A 1 1 1 1 C5563 C5564 INVENTEC 10UF_6.3V_3 2 2 10UF_6.3V_3 2 1UF_6.3V_2 C5562 1UF_6.3V_2 C5561 2 1UF_6.3V_2 C5560 2 2 C5559 1UF_6.3V_2 2 1UF_6.3V_2 10UF_6.3V_3 2 10UF_6.3V_3 1 1 C5558 1 1 C5557 2 2.2UF_6.3V_2 2 C5555 1 1 1UF_6.3V_2 C5554 2 1UF_6.3V_2 1 2 C5553 1 1UF_6.3V_2 2 C5552 1 1UF_6.3V_2 C5551 1 2 C5556 1 P1V5S_DGPU P1V5S_DGPU 1UF_6.3V_2 58D4 58D4 P2 J2 A1 P1V5S_DGPU C5550 58D4 58D4 M10 VSS#P2 VSSQ#G10 SAM_K4B1G1646D_HCF7_FBGA_100P 2 58D4 2 VSSQ#D9 D9 1 D2 VSSQ#G10 64D7 58D4 C B4 VSSQ#B10 0.01UF_50V_2 VSSQ#D2 J2 B VRAM_VREFC_B<0> 58D4 E10 VDDQ#H10 ZQ_ZQ0 B2 VSSQ#B2 VSSQ#B10 IN 58D4 243_1%_2 243_1%_2 64D7 58D4 D3 VSS#P10 T10 58D4 C10 VDDQ#D3 RESET R5528 58D4 58D4 R2 CKE_CKE0 E8 BI BI BI BI BI BI BI BI 58D4 N10 VSS#M10 P2 VSS#T10 K3 VDD#K9 VDD#N10 M10 VSS#T2 G8 CK 58D4 D10 VDD#K3 K8 BI BI BI BI BI BI BI BI B3 VDD#G8 J8 K10 DQMB<1> DQMB<2> BI BI 58D1 B4 VSS#P2 ZQ_ZQ0 IN IN IN IN IN BI BI 58C1 A10 VSS#P10 2 58C1 58D1 VSS#A10 IN IN IN VREFCA H2 VDDQ#E10 H10 VDDQ#H10 CLKB0_DP CLKB0_DN CKEB0 1 M9 N3 MAB_BA<0> MAB_BA<1> MAB_BA<2> BI BI BI K2 J4 MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13> 58D4 P1V5S_DGPU B3 G8 VDD#N10 CK BI BI BI BI BI BI BI BI ODTB0 CSB0#_0 RASB0# CASB0# WEB0# IN 0 5 VSS#M10 65C8 58D4 U5505 VRAM_VREFC_B<2> VRAM_VREFD_B<1> IN IN A5 K8 DQSB3_DN DQSB0_DN BI BI 64B4 A4 J8 DQMB<3> DQMB<0> BI BI 58D4 2 P3 VDDQ#E10 58C1 BI BI BI BI BI BI BI BI 3 P9 M4 CLKB0_DP CLKB0_DN CKEB0 VREFDQ DQL0 F3 DQB<29> N3 MAB_BA<0> MAB_BA<1> MAB_BA<2> BI BI BI VREFCA 4 5 4.99K_1%_2 64A8 6 4.99K_1%_2 8 TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 64 REV X01 68 of 1 M9 VREFCA DQL0 H2 VREFDQ DQL1 DQL2 65D4 64D7 64D4 58D1 58A1 MAB<13..0> BI 0 1 2 3 4 5 6 7 8 9 10 11 12 D 13 65D4 64D7 64D4 58D1 65D4 64D7 64D4 58D1 65D4 64D7 65D4 65D4 64D4 65B4 58B1 65B5 58B1 65C4 58B1 65C4 58B1 65C4 58B1 65C4 58B1 65C4 58B1 65C4 58A1 N4 DQL4 P4 A2 DQL5 N3 A3 DQL6 P9 A4 DQL7 A6 A7 DQU0 D8 T9 A8 DQU1 C4 R4 A9 DQU2 C9 A10_AP DQU3 A11 DQU4 A8 N8 A12 DQU5 A3 T4 A13 DQU6 B9 T8 A14 DQU7 A4 M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 K10 58C1 C DQSB6_DP DQSB7_DP BI BI 58C1 BI BI 58C1 58C1 BI BI 58C1 63C8 63C4 62C7 62C4 65C4 58A1 64C7 IN BA2 CK 2 58D4 3 58D4 4 58D4 5 58D4 BI BI BI BI BI BI BI BI 8 58D4 9 58D4 10 58D4 11 58D4 12 58D4 13 64D4 58D1 64D7 64D4 58D1 65D8 VDD#G8 G8 VDD#K3 65D8 R2 65C8 P1V5S_DGPU 65B4 58B1 65B5 58B1 65C8 58B1 65C8 58B1 C10 65C8 58B1 D3 65C8 58A1 RAS VDDQ#C2 K4 CAS VDDQ#C10 L4 WE VDDQ#D3 58C1 58C1 VDDQ#H3 H3 IN IN IN IN IN BI BI 58D1 VSS#E2 E2 G9 58C1 VSS#G9 J3 58C1 VSS#J3 VSS#J9 VSS#M2 A4 P3 A5 R9 A6 R3 A7 DQU0 D8 DQB<41> T9 A8 DQU1 C4 DQB<44> R4 A9 DQU2 C9 DQB<42> L8 A10_AP DQU3 C3 DQB<45> R8 A11 DQU4 A8 DQB<40> N8 A12 DQU5 A3 DQB<47> DQU6 B9 DQB<43> DQU7 A4 DQB<46> A13 T8 A14 M8 A15_BA3 M3 BA0 VDD#B3 N9 BA1 VDD#D10 M4 BA2 K2 ODT VDDQ#A2 A2 L3 CS VDDQ#A9 A9 J4 RAS VDDQ#C2 C2 K4 CAS VDDQ#C10 L4 WE DQSB4_DP DQSB5_DP F4 DQSL VDDQ#F2 F2 C8 DQSU VDDQ#H3 H3 D4 DMU VDDQ#H10 H10 VSS#A10 A10 VSS#B4 B4 J9 M2 VSS#M2 M2 65C8 64C7 64C4 63C8 63C4 62C7 62C4 58A1 VM_RESET IN T3 RESET R5538 P10 1 T2 L9 ZQ_ZQ0 B10 VSSQ#E9 E9 CLKB1_DN IN 1 2 1 R5547 2 CLKB1_DP 58B1 65D8 IN 56_5%_2 1 56_5%_2 65D4 F10 G2 2 G10 T1 T10 VSSQ#B2 B2 D2 VSSQ#D9 D9 NC_ODT VSSQ#E3 E3 L2 NC_CSI VSSQ#E9 E9 J10 NC_CE1 L10 NC_ZQ1 D 58D4 P1V5S_DGPU C F10 VSSQ#F10 G2 VSSQ#G2 G10 NC NC T1 NC NC T11 SAM_K4B1G1646D_HCF7_FBGA_100P 2 R5536 C5515 0.1UF_16V_2 1 IN 2 1 VRAM_VREFD_B<5> 65D4 2 2 1 R5535 1 2 4.99K_1%_2 P1V5S_DGPU 0.1UF_16V_2 C5514 1 IN 4.99K_1%_2 2 P1V5S_DGPU 4.99K_1%_2 4.99K_1%_2 VRAM_VREFC_B<6> 65D4 2 R5533 1 C5513 2 4.99K_1%_2 0.1UF_16V_2 1 IN 1 VRAM_VREFD_B<7> R5534 2 R5532 4.99K_1%_2 58D4 B A1 T11 2 R5530 1 58D4 B10 VSSQ#D2 J2 A11 2 1 R5531 0.1UF_16V_2 1 C5512 2 P1V5S_DGPU 58D4 T2 VSS#T10 VSSQ#G10 P1V5S_DGPU 65D8 58D4 P10 VSS#T2 VSSQ#B10 0.01UF_50V_2 VSSQ#E3 NC_CSI 58B1 65D4 R5546 C5519 NC_ODT L2 65C8 P1V5S_DGPU IN 58D4 P1V5S_DGPU P1V5S_DGPU 65D8 58D4 243_1%_2 SAM_K4B1G1646D_HCF7_FBGA_100P VRAM_VREFC_B<4> 58D4 P2 VSS#P2 VSS#P10 2 58D4 M10 VSS#M10 P2 58D4 E10 J3 M10 58D4 D3 VSS#J9 DQSB4_DN DQSB5_DN BI BI 58D4 C10 VDDQ#D3 J9 D9 NC R10 G9 VSSQ#D9 NC VDD#R10 DML 58D4 58D4 R2 CKE_CKE0 E8 BI BI BI BI BI BI BI BI 58D4 N10 VSS#J3 D2 NC VDD#R2 DQSU VSSQ#D2 NC CK B8 B2 VSSQ#G10 VDD#N10 E2 VSSQ#B2 VSSQ#G2 CK K8 58D4 D10 VSS#G9 T10 VSSQ#F10 J8 BI BI BI BI BI BI BI BI B3 VSS#E2 E3 A11 DQL7 H8 DQB<38> A3 P9 DQSL J2 A1 DQL6 G3 DQB<33> G4 VSS#T10 VSSQ#B10 B H9 DQB<34> ODTB1 CSB1#_0 RASB1# CASB1# WEB1# 243_1%_2 NC_ZQ1 DQL5 K10 DQMB<4> DQMB<5> BI BI 58C1 A10 VSS#B4 VSS#T2 IN IN IN H10 B4 VSS#P10 L10 A2 VDDQ#E10 F2 VSS#P2 CLKB1_DP CLKB1_DN CKEB1 E10 VDDQ#F2 VSS#A10 NC_CE1 P4 N2 N10 C2 J10 H4 DQB<32> K9 J4 ZQ_ZQ0 DQL4 VDD#N2 58B1 RESET A1 N2 58B1 DQSU P8 VDD#N2 65C8 B8 F9 DQB<37> K3 65C8 DQSL DQL3 VDD#K9 A9 G4 A0 K9 A2 DMU N4 VDD#K9 VDDQ#A9 D4 DQL2 F3 DQB<36> G8 VDDQ#A2 DML F8 DQB<35> VDD#K3 58D1 CS E8 E4 DQB<39> DQL1 K3 64D4 ODT DQSU DQL0 VREFDQ VDD#G8 64D7 L3 DQSL MAB_BA<0> MAB_BA<1> MAB_BA<2> BI BI BI VREFCA H2 T4 58D4 P1V5S_DGPU M9 N3 58D4 64D7 VDD#R2 CK 7 DQB<59> DQB<63> DQB<62> DQB<58> DQB<60> DQB<56> DQB<61> DQB<57> K2 L9 1 1 U5507 MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13> 0 58D4 65D8 VDD#N10 R5539 2 MAB<13..0> BI R10 T3 1 58A1 65D8 VDDQ#H10 VM_RESET 58D1 D10 VSS#M10 64C4 58D4 64D4 VDD#R10 C8 DQSB6_DN DQSB7_DN 64D7 65D8 CKE_CKE0 F4 DQMB<6> DQMB<7> 58D4 B3 VDDQ#E10 58C1 C3 R8 K8 65A3 58D4 2 VRAM_VREFC_B<6> VRAM_VREFD_B<5> IN IN 6 R3 J8 65A4 58D4 BI BI BI BI BI BI BI BI A5 R9 M4 ODTB1 CSB1#_0 RASB1# CASB1# WEB1# IN IN IN IN IN DQL3 A1 L8 CLKB1_DP CLKB1_DN CKEB1 IN IN IN A0 P8 P3 MAB_BA<0> MAB_BA<1> MAB_BA<2> BI BI BI 58D1 MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13> DQB<55> F8 DQB<52> F3 DQB<51> F9 DQB<54> H4 DQB<48> H9 DQB<50> G3 DQB<49> H8 DQB<53> E4 3 4.99K_1%_2 65A6 U5506 VRAM_VREFC_B<4> VRAM_VREFD_B<7> IN IN 4 5 4.99K_1%_2 65A8 6 R5537 7 1 8 C5579 C5578 10UF_6.3V_3 2 2 10UF_6.3V_3 2 1 1 1UF_6.3V_2 1 C5577 1 C5576 2 1UF_6.3V_2 1 2 1UF_6.3V_2 C5575 1UF_6.3V_2 C5574 2 2 C5572 1UF_6.3V_2 C5573 1 1 2 10UF_6.3V_3 2 1 2.2UF_6.3V_2 2 C5570 1UF_6.3V_2 1 2 C5569 1 1UF_6.3V_2 C5568 2 1UF_6.3V_2 1 2 C5567 1 1UF_6.3V_2 2 C5566 1 1UF_6.3V_2 C5565 2 C5571 10UF_6.3V_3 1 A 1 A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 65 REV X01 68 of 1 8 7 6 4 5 3 2 1 D D C C P5V0A_USB3 CN2001 51C2 30C5 51C2 30C5 USB_P2_DN USB_P2_DP BI BI 1 4 L2001 USB_L_P2_DN USB_L_P2_DP 2 3 WCM_2012_900T 1 VCC G1 G1 2 DATA- G2 G2 3 DATA+ G3 G3 4 GND G4 G4 SUYIN_020173GR004M555ZL_4P B B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 66 REV X01 68 of 1 8 7 6 4 5 3 2 1 REFERENCE 9000~9999(SMALL BOARD) D D POWER BUTTON 6 1 1 1 B 2 A 5 1 SW9000 4 2 C 3 D PAD9000 SMDPAD_1P_40X120 C9000 MISAKI_NTC017_DA1G_E160T_6P 1 2 3 1000PF_50V_2_DY PAD9001 SMDPAD_1P_40X120 D9000 DGND_PWRSW_DB C C PHP_PESD5V2S2UT_SOT23_3P_DY B B FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX9005 1 FIX9004 1 FIX9003 1 FIX9002 1 FIX9001 1 1 FIX9000 FIX_MASK S9000 1 SCREW540_700_NP_1P 1 S9001 SCREW540_700_NP_1P A A DGND_PWRSW_DB INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 67 REV X01 68 of 1 8 7 6 5 4 3 2 1 D D C C B B A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block Diagram SIZE A3 CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS DOC.NUMBER 1310xxxxx-0-0 SHEET 68 REV X01 68 of 1 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Modify Date : 2015:08:24 20:21:43+03:00 Create Date : 2011:09:06 10:06:16+08:00 Metadata Date : 2015:08:24 20:21:43+03:00 Creator Tool : Allegro Design Publisher Document ID : uuid:753fa9cb-7781-4899-883d-dcb847d55051 Instance ID : uuid:44e3e349-c01e-438d-ad42-9303a9316599 Format : application/pdf Title : Inventec Dakar 10F/FG - Schematics. www.s-manuals.com. Creator : Subject : Inventec Dakar 10F/FG - Schematics. www.s-manuals.com. Producer : Adobe PDF Library 8.0 Page Count : 69 Keywords : Inventec, Dakar, 10F/FG, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools