Inventec Dakar 10F/FG Schematics. Www.s manuals.com. 10f, 10fg Rx01 Schematics 1

DAKAR10F/FG

681

21-OCT-2002

1310xxxxx-0-0

XXX

X01

MODEL,PROJECT,FUNCTION

2011.09.02

Everest Main Board

CS

C

REV

DATE CHANGE NO.

E

D

C

B

A

7654321

76543

E

D

C

B

A

8

FF

P/N

VER:

DATEDATEEE

DESIGN

DRAWER

CHECK

8

INVENTEC

TITLE

SIZE CODE

SHEET

of

DOC.NUMBER REV

1

POWER

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR

IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT

HSF Property:ROHS or Halogen-Free(5L3?)

RESPONSIBLE

SIZE=

FILE NAME:

2

9. POWER VCCIO

10. POWER VCCSA

11. POWER VCORE

13. POWER VCORE_DGPU

37. HDMI CEC

PAGE

TABLE OF CONTENTS

PAGE

52. PCH 6 MISC

53. PCH 7 POWER

54. PCH 8 POWER

55. PCH 9 GND

56. VGA 1

57. VGA 2

58. VGA 3

59. VGA 4

51. PCH 5 USB

19. LED

12. POWER VGFX

24. AUDIO CODEC

21. EC

22. LAN

39. DDR3 DIMM1

41. CPU 1

43. CPU 3 DRAM

42. CPU 2

40. FAN & THERMAL SENSOR

6. POWER +V3LA/+V3A/+5A

44. CPU 4 POWER

45. CPU 5 POWER

46. CPU 6 GND

47. PCH 1

48. PCH 2

49. PCH 3

8. POWER +V1.8S

7. POWER +V1.5/+V0.75

3. BLOCK DIAGRAM

4. POWER MAP

23. RJ45 & TRANSFORMER

5. POWER CHARGER 30. USB 2.0 CONN

38. DDR3 DIMM0

50. PCH 4 AXG

34. LCM CONN

26. CARDREADER

27. MINI1 WLAN/DEBUG CARD

28. MINI2 3G/LTE

29. SATA HDD/ODD CONN

31. USB 3.0 CONTROLLER

32. USB 3.0 CONN W/ S&C

33. USB 3.0 CONN 60. VGA 5

64. VRAM 3

65. VRAM 4

66. POWER BUTTON BOARD

67. EMI

2. INDEX

35. CRT CONN

36. HDMI CONN 63. VRAM 2

62. VRAM 1

PAGE

1. COVER PAGE

61. VGA 6

25. SPEAKER/HP JACK/MIC JACK

20. K/B & TP/B CONN

18. HALL SENSOR

17. PCB SCREW

16. LOAD SWITCH-2

15. LOAD SWITCH-1

14. ENABLE PIN

682

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

A3 CS

Block Diagram

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

PCIE_3:USB3.0 PCIE

PCIE_2:WLAN PCIE

SATA

SLEEP & CHARGE

204-PIN SODIMM1

(1333/1600 MHZ)

DDR3@1.5/0.75V

204-PIN SODIMM0

(1333/1600 MHZ)

DDR3@1.5/0.75V

DMI 2.0

37.5 X 37.5 X 5 mm

SOCKET-RPGA989

DC 35W

IVY BRIDGE

RJ45

ENE-P2809A

THERMAL SENSOR

PCH

AUDIO CODEC

USB2.0

SATA1: HDD

SATA6: ODD

SATA0:ESATA

NPCE885LA0DX

EC WINDBOND

USB2.0

25 X 25 X 2.3 mm

PANTHER POINT

BATTERY CHARGER &

DC/DC & IMVP 7

6-Cell

LI-ION BATTERY

FDI

SPI

DDR3 INTERFACE

TOUCH PAD

KEYBOARD

SPI

PCIE

USB_8:

HDA REA_ALC269Q_VB6

USB_10:WEBCAM

USB_1: USB3.0 CONN

REA_RTS5129

CARD READER

INTERNAL MIC IN

EXT MIC IN

HEADPHONE

USB_0: USB CONN

USB_2: USB CONN

USB_8: CARD READER

USB_9: MINICARD WLAN

USB3.0

SPI FLASH 8MB

MXIC_MX25L3206EM2I

LCM

HDMI

W/ POWER EXPRESS

AMD

THAMES

29X 29 MM

PEG

ATHEROS_AR8161/8162

PCIE_1:LAN

LVDS

CRT

683

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

A3 CS

Block Diagram

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

AO6402L

POWER BUDGET 4.711A

+V0.75S

INRUSH 0.9A

VDD_CORE

+VCORE1_+-0.5%

+VCORE_+-0.5%

F 340K

OCP 29.1A R=75K

TPS51217

OCP 53A

F 280K

TI_TPS61640

POWER BUDGET 53A

PEAK 53A AVG 28.822A

1880UF_1.1M£[ // 2276UF_0.203M£[

POWER BUDGET 20.070A

560UF_25M£[ // 80UF_0.93M£[

PEAK 20.070A AVG 11.531A

65W-75W 8A 6036A0003401

90W 10A 6036A0002901

120W 12A 6036A0006001

FUSE

CHG_EN

BATT_IN

EC_SMB2

CHARGER

ACPRES

BQ24725RGRR

BATTERY PACK

+VBAT

TPS51123

POWER BUDGET 12.139 A

220UF_25M£[ // 53.92UF_1.529M£[

PEAK 7.283A AVG 2.363A

OCP 10.4A R=120K

F 300K

560UF_25M£[ // 1274.8UF_0.214M£[

PEAK 5.695A AVG1.048 A

TPS51216

OCP 10.7A R=130K

220UF_25M£[ //10.6UF_5.924M£[

POWER BUDGET 9.429 A

TPS51123

F 375K

POWER BUDGET 13.7 A

PEAK 17.107A AVG4.835 A

OCP 10.1A R=115K

F 340K

POWER BUDGET 13.7 A

TPS51216

+VTT_+-5%

AON7410

V1.5_+-5%

+V3LA_+-5%

PEAK2.592A

AON7410

PEAK2.592A

AO6402L

+V3S

+V3A

POWER BUDGET 4.711A

100.82UF_0.842M£[

INRUSH 0.9A

TPS51216

+V1.5_CPU

PEAK2.592A

+V1.5S

PEAK2.592A

POWER BUDGET 4.711A

GMT_AT1530F11U

100.82UF_0.842M£[

AM2321P

INRUSH 0.9A

+V1.8S

+V3_LAN

INRUSH 0.9A

+V5A_+-5%

OCP 6A

F 340K

PEAK2.592A

AO6402L

TSP51461

POWER BUDGET 6A

INRUSH 0.9A

100.82UF_0.842M£[

POWER BUDGET 4.711A

PEAK 6A AVG 1.262A

+V5S

+V0.85S_+-0.5%

ADAPTOR

V3_V5 IS NEW IC TPS51123

V0.85 IS NEW IC TPS 51641

VTT IS NEW IC TPS51219

VCC CORE IS NEW IC TPS51640

CHARGE IS NEW IC BQ24725

+V1.8S IS NEW IC GMT_AT1530F11U

TPS51217 SAME AS 2010 PROJECT

TPS51218 SAME AS 2009 PROJECT OCP 10.1A R=115K

PEAK 17.107A AVG4.835 A

F 340K

560UF_25M£[ // 1274.8UF_0.214M£[

POWER BUDGET ~~IC SPEC (MAX CURRENT )

PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION

AVG CURRENT ~~TEST RESULT(MAX CURRENT)

INRUSH ~~L/S TURN NO

CHANGING POINTS~~

684

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

Block Diagram

CS

A3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

NEAR EC

FUSE6000

65W-75W 8A(6036A0003401)

90W 10A(6036A0002901)

120W 12A(6036A0006001)

NEAR IC

685

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

CSC0402_DY

SYN_200045GR009G18TZR_9P

LITTLEFUSE_R451015_15A_65V

1000PF_50V_2

P3V3AL

RSC_0603_DY

33K_5%_2_DY

220K_1%_2

PVPACK

EZJZ0V500AA_DY

10PF_50V_2

1000PF_50V_2

0.1UF_25V_3

RSC_1206_DY

AON7410

PVADPTR

0.1UF_16V_2

PVADPTR

NFE31PT222Z1E9L

Block Diagram

CS

A3

TP30

0.1UF_16V_2_DY

ACES_50315_0047N_002_4P

TP30

PVADPTR 4.7K_5%_3

SHORT_0402

POWERPAD_2_0610

0.1UF_25V_3

PVBAT

3.32K_1%_3

100PF_50V_2

20.5K_1%_2

10K_5%_3

ETQP3W4R7WFN

4.7UF_25V_5

SBR3U40P1_DY

10_5%_5

470PF_50V_2 4.7UF_25V_5

BAT54C_30V_0.2A

TPCA8065_H

EZJZ0V500AA_DY

8A_125V

TP30

RSC_0603_DY

CSC0603_DY

110K_5%_2

1UF_10V_2

30K_5%_2

AM4410NC

2200PF_50V_2

P3V3AL

100PF_50V_2

4.3K_5%_24.3K_5%_2

RSC_0603_DY

0.1UF_25V_3

33_5%_2

1M_5%_2

PVBAT

RSC_0603_DY

PVPACK

CSC0805_DY

0.01_1%_6

CSC0805_DY

4.7UF_25V_5

0.1UF_25V_3

0.1UF_16V_2

0.1UF_25V_3

RSC_0603_DY

CSC0402_DY

1UF_25V_3

0.047UF_16V_2

BAT54C_30V_0.2A

SHORT_0402

6.98_1%_2

4.3K_5%_2

0.01_1%_6

0.1UF_25V_3

DIODES_BAV99

SHORT_0402

AM4410NC

CSC0805_DY

RSC_1206_DY

AON7410

TI_BQ24725RGRR_QFN_20P

EZJZ0V500AA_DY

1K_5%_2

P3V3AL

0.1UF_16V_2

CSC0402_DY

CN6050

CN6000

R6003

L6000

TP6003 TP6004 TP6005

C7602

R6019

R6018 C6014

R6015

R6017

R6016

R6009

R6010

R6011

C6004

C6050

R6052

R6054 R6053

R6051

R6050

D6703D6702D6701

FUSE6050

PAD6000

C6013

C6012

C6011

C6010

C7600

C6027

C6026

C6028

C6023

C6025

C6024

C6020

C6022C6021

C6032

C6034

C6035

C6036

C6037

C6029

C6031C6030

C6001 C6002 C6003

C6033

R6802

C6800

C7601

L7600

FUSE6000

R6801

R6800

R7600

R6012

R6008

R6007

R6005R6004

R6006

R6013

R6014

R6002

R6001

R6000

D6700

D6001

D6000

D6002

Q6001

Q6000

Q6012

Q6011Q6010

U6000

37C3 21D2

21E8

56C8

56D8

21E6

21D3

21D3 21D2

21E6

21D2

21E8 21E6

37C6

21D3

21D3 EC_SMB1_CLK

EC_SMB1_DATA

BATT_IN

VRCHARGER_PH

ACPRES

HW_I_ADC

HW_V_ADC

EC_SMB2_DATA

EC_SMB2_CLK

VRCHARGER_HG

VRCHARGER_LG

G4

G3

G2

G1

9

8

7

6

5

4

3

2

1

G2

G1

4

3

2

1

21

1 1 1

2 1

2 1 2 1

21

2 1

21

2 1

21

21 21

21

2 1

21

2 1

21

2 1

21

2 1

2121

2 1

21

2 1

4

3

2121

21 21

21

21 21

21

43

21

43

21

2 1

3

21

3

21

3

2 1

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

45

6

7

8

3

2

1

4 5

6

7

8

3

2

1

45

6

7

8

20

21

13

12

8

9

16

19

15

7

10

18

14

3

17

11

2

5

1

4

6

BI

C

A2A1

BI

OUT

12

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

OUT

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

G

GND

SMC

SMD

TS

B-I

ID

BATT+

6

5

4

3

2

1

BI

OUT

C

A2A1

VCC

TML

SRP

SRN

SDA

SCL

REGN

PHASE

LODRV

IOUT

ILIM

HIDRV

GND

CMSRC

BTST

BATDRV

ACP

ACOK

ACN

ACDRV

ACDET

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

VOUT=((R6100/R6101)+1)*2

VO=(( R6150/R6151)+1)*2

686

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

TI_TPS51123RGER_QFN_24P

0.1UF_16V_2

10K_1%_2

RSC_0603_DY

AON7702A

CSC0402_DY

1UF_6.3V_2

330UF_6.3V

RSC_0402_DY

6.8K_1%_2

PVBAT

0.1UF_16V_2

2.2_5%_3

POWERPAD_2_0610

15.4K_1%_2

10K_1%_2

330UF_6.3V

Block Diagram

CS

A3

0.22UF_6.3V_2

10UF_6.3V_3

1UF_25V_3

120K_1%_2

4.7UF_25V_5

4.7UF_25V_5 4.7UF_25V_5

ETQP3W3R3WFN

CSC0402_DY

AON7410

ETQP3W3R3WFN

RSC_0603_DY

4.7UF_25V_5

AON7702A

2.2_5%_3

130K_1%_2

Q6151

Q6101

L6100 L6150

C6110

R6150

R6151

C6150

C6161C6160

R7615

Q6150

C6155R6155

C6123

C7615

C6120

C6122

R6160

R6110

U6100

R6114

C6115

Q6100

C6111

R7610

R6113

C6121

C7610

PAD6110

R6100

C6100

R6101

14C7

14C8

14C6

14D4

14C8

14D6

6C6 14C8

6D3

14D6

6B3 14D5

14D7

14C7

6C3 14C8

14D6 VRP3V3A_LG

VRP3V3A_PH

VRP3V3A_HG

VRP3V3A_LDO

VRP5V0A_LG

VRP5V0A_PH

VRP5V0A_HG

VRP5V0A_VIN

SKIP_3V_5V

VRP3V3A

VRP5V0A_PH2VREF

VBATP

5V_PG

VRP5V0A_LDO

VRP5V0A_LG

EN_5V

EN_3V

VBATP

EN_3V_5V

VRP5V0A

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

21 21

2 1

2 12 1

2 1

2 12 1

3

2

1

4 5

6

7

8

2121

2 1

2 12 1

17

8

3

7 24

16

5

2

9 22

1

4

25

14

23

11 20

15

6

18

13

12 19

10 21

2121

3

2

1

4 5

6

7

8

2 1

12

OUT

S

G

D

S

G

D

OUT

+

OUT

IN

NMOS_4D3S

D

G

S

OUT

+

OUT

IN

VFB1

VFB2

GND

SKIPSEL

VREG5

ENC

TML

TONSEL

VIN

TRIP2

TRIP1

EN0

VREF

DRVL2

VBST2

VREG3

VO2 VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

LL2

DRVH2

OUT

NMOS_4D3S

D

G

S

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

MODE=100KOHM:TRACKING DISCHARGE

VOUT=REFIN=1.8*(R6201/(R6200+R6201))

687

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P0V75M_VREF

4.7UF_25V_5

PCMC104T_1R0MN

0.22UF_6.3V_2

FDMS0310AS

RSC_0603_DY

TI_TPS51216RUKR_QFN_20P

10UF_6.3V_3

POWERPAD1X1M

560UF_2.5V

2.2_5%_3

PVBAT

POWERPAD_2_0610

Block Diagram

CS

A3

CSC0402_DY

FDMC8884

0.1UF_16V_2

P0V75S

P5V0A

2.2UF_6.3V_3

100K_5%_2

75K_1%_2

10K_1%_2

0.1UF_16V_2

0.01UF_50V_2

52.3K_1%_2

L6200

C6220

Q6201Q6200

U6200

PAD6220

PAD6210

C6200

C6212

C6211

C6210

R7620

C7620

C6215R6215

C6216

C6221

R6202

C6218

R6200

C6217

R6201

R6203

14C2

14D1

VRP1V5_LG

VRP1V5_PH

VRP1V5_HG

VRP1V5

1V5_PG

EN_0V75

EN_1V5

DDR3L_SEL

43

21

2 1

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

21

2 1

212 1

2121

2 1

21

2 1

21

2 1

21

2 1

IN

S

G

D

NMOS_4D3S

D

G

S

IN

VTTSNS

VTTREF

VTTGND

VTT

VREF

VLDOIN

VDDQSNS

VBSTV5IN

TRIP

TML

SW

S5

S3

REFIN

PGOOD

PGND

MODE

GND

DRVL

DRVH

1 2

OUT

1 2

+

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

VOUT=((13K+10K)+1)*0.8

OCP=4.5AMP

688

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

22UF_6.3V_5

CSC0402_DY

13K_1%_210K_1%_2

10UF_6.3V_3

PAN_ELL5PR2R2N

Block Diagram

CS

A3

GMT_AT1530F11U_SOP8_8P

0.1UF_16V_2

P3V3SP5V0A

10_5%_2

0.1UF_16V_2

C6970

U6970

C6973

C6974

R6973R6972

L6970

C6971

R6970C6972

14A2

14B1

VRP1V8S

VRP1V8S_PH

EN_1V8

2 1

8

1

9

2

6

7

3

4

5

2 1

2 12 1

21

2 1

2 12 1

IN

VIN

VCC

TML

REF

PGND

LX

GND

FB

EN

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND

689

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

22UF_6.3V_5

4.7UF_25V_5

0_5%_2_DY

10K_5%_2

100K_5%_2

P3V3A

FDMS0310AS

0.1UF_16V_2

4.7UF_25V_5

2.2UF_6.3V_3

86.6K_1%_2

0.01UF_50V_2

TI_TPS51219RTER_QFN_16P

2.2_5%_3

2.2UF_6.3V_3

P5V0A

POWERPAD_2_0610

CYN_PCMB063T_R68MS_4P

A3 CS

Block Diagram

560UF_2.5V

PVBAT

RSC_0603_DY

CSC0402_DY

FDMC8884

R6307

Q6301Q6300

U6300

C6301

C6300

PAD6310

C6312

L6300

C6311

C6310

R7630

C6315

C6316

C7630

R6303

R6315

C6319

R6306

R6302

C6318

44A3

46B4

44A3

14A8 14B6

14B7

14A8

VRP1V05S

VRP1VO_VCCP_HG

VRP1V0_VCCP_LG

VSS_SENSE_VCCIO

VCCIO_SEL

VCCP_PG

VCC_SENSE_VCCIO

EN_VCCP

VRP1VO_VCCP_PH

21

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

4

1

9

6

12

2

17

16

8

15

3

7

14

10

11

5

13

2 1

212 1

43

21

2 1

21

2 1

21

2 1

21

2 1

IN

S

G

D

IN

NMOS_4D3S

D

G

S

VSNS

VREF

V5

TRIP

SW

REFIN

PWPD

PGOOD

PGND

MODE

GSNS

GND

EN

DL

DH

COMP

BST

OUT

+

1 2

IN

43

21

IN

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6810

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

22UF_6.3V_5

CSC0402_DY

RSC_0603_DY

CYN_PCMB063T_R33MS_4P

0.1UF_16V_2

TI_TPS51461RGER_QFN_24P

1UF_6.3V_2

P5V0A

0.01UF_50V_2

22UF_6.3V_5_DY22UF_6.3V_5

Block Diagram

CS

A3

22UF_6.3V_5

SHORT_0402

RSC_0402_DY

5.11K_1%_2

0.22UF_6.3V_2

3300PF_50V_2

0.1UF_16V_2

1UF_6.3V_2

22UF_6.3V_5

R6525

R6524

L6500

C6522

C6503C6502C6501C6500

R7650

C6515

C7650

R6521

R6520

C6521

C6520

U6500

C6524

C6523

C6511C6510

14A6

45A2

14B5

45A2

14A6 21B6

VRPVCCSA

VCCSA_SENSE

EN_SA

VCCSA_VID0

VCCSA_VID1

VRPVSA_PH

SA_PG

21

43

21

2 1

21

2 1

21

2 1

21

2

5

24

23

22

15

14

17

18

25

9

8

7

11

10

4

16

21

20

19

6

1

13

3

12

2 1

43

21

OUT

IN

VREF

VOUT

VID1

VID0

V5FILT

V5DRV

TML

SLEW

PGOOD

MODE

GND

EN

COMP

BST

SW

SWVIN

VIN

PGND

SW

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

R6627

DNP

R6638

R6723 DNP 0

R6719

R6711

R6714

R6716

R6712

R6626

200K

30K

DNP

DNP 0

0

DNP

DNP56K

3.3K

2+1 2+0

6811

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

2.2UF_10V_3

2.2_5%_3

P5V0A

0.1UF_16V_2

10_5%_3

P3V3A

4.7UF_10V_3

FDMS7692

P5V0A

100K_5%_NTC

15.4K_1%_2

FDMS0306AS

0.1UF_16V_2

TI_TPS51650RSLR_QFN_48P

0.033UF_16V_2

162K_1%_2

PVCORE

PVBAT

P3V3A

PVBAT

P3V3A P1V05S

P3V3A

28.7K_1%_2

PAN_ETQP4LR36ZFC_4P

28.7K_1%_2

CSC0402_DY

3.3K_1%_2

CSC0402_DY

15.4K_1%_2

100K_5%_NTC

8.66K_1%_2

20K_5%_2

0_5%_2_DY

30K_1%_2

200K_1%_2

20K_1%_2

0_5%_2_DY

56K_1%_2

4.12K_1%_2

100PF_50V_2

8.45K_1%_2

100PF_50V_2

43K_1%_2

24K_1%_2

39K_1%_2

FDMS7692

RSC_0603_DY

A3 CS

Block Diagram

470UF_2V

100K_5%_NTC

162K_1%_2

470UF_2V

0.1UF_16V_2_DY

POWERPAD_2_0610

68UF_25V

4.7UF_25V_5

0.033UF_16V_2

470UF_2V

0.1UF_16V_2_DY

RSC_0603_DY

FDMS0306AS

100K_5%_2

0_5%_2

90.9K_1%_2

0_5%_2

0_5%_2_DY

0.1UF_16V_2

130_1%_2

54.9_1%_2

2K_5%_2

RSC_0402_DY

0_5%_2

2.2UF_6.3V_3

PAN_ETQP4LR36ZFC_4P

100K_5%_NTC17.8K_1%_2

17.8K_1%_2

2.2_5%_3

10K_5%_3

P3V3A

C6629

C6622

C6630

R6617

R6601

R6618

U6600

R6602

R6607

C6635

R6729

Q6621Q6611 Q6620Q6610

C6603

C6617

C6623

R6605

C6616

C6615

C6614

C6613

C6612

C6611

C6610

C6000

PAD6610

R6619

C6631

C6601C6600

R6604

L6610

R6603

C6625

R6610

R6609

L6620

R6608

C6602

R6633

R6632

R7661

C7661

C6624R6606

R6616

R7662

C7662

R6732

R6634

R6622R6620

R6623

R6621

C6632

R6625

R6626

R6731

R6730

C6727

R6719

R6723

R6724

R6720

C6726

R6718

R6728

R6627

C6634

R6713

C6633

R6628

R6629

R6711

R6712

R6715

R6716R6714

R6630

R6631

11C4

11D5

11C3

11D3

11C3

40B4 11A4

11D1 11D3

11D5

11D6 11D4

11D5

11A3

40B4

41D6 21C3

11A3

21D3

11C7

11D7 11D6

11D4 11C8

11B7

11A7

11A4

45C3

11A4

11A7

11D7 11D6 11D4 11C8 11B7 11A4

12C5

11D7

11D6

11D4

11C8

11A7

11A4

12C5

44B3

11C8

11B7 11A7 11A4

11D7 11D4 11C8 11B7 11A7 11A4

11D6 11D4 11C8 11B7 11A7

11B7

49B7 11C7

44C2 11C7

44C2

11D7 11D6 11C8 11B7 11A7 11A4

11D1 11B3

11D5

11D3 11B3

12B8

11D7

11C7

12C8

44C2

49B7

44C2

CPU_CSN2

CPU_CSN1

CPU_CSP1

V5_CPU

EN_PVCORE

CPU_CSP2

PVCORE_PG

PVBAT_CPU

CPU_CSN2

CPU_CSP2

VR_SVID_ALERT#

VR_SVID_CLK

VR_ON

VREF_CPU

GFX_VSS_SENSE

GFX_VCC_SENSE

VREF_CPU

VR_ON

VREF_CPU

GPU_CSN1

VREF_CPU

GPU_CSP1

VSSSENSE

VCCSENSE

VREF_CPU

PVAXG_PG

PVCORE_PG

VR_SVID_DATA

PVBAT_CPU

CPU_CSP1

CPU_CSN1

PVBAT_CPU

CPWM3

GSKIP#

VR_SVID_CLK

VREF_CPU

GPWM1

GPWM2

PVAXG_PG

CPU_PROCHOT#

VR_SVID_DATA

49

48

44

4

1 2

2

47

1

5

7

6

21

2 1

1

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

4

8

3

2

1

13

15

20

19

17

36

43

14

41

42

23

31

32

33

34

21

30

24

22

28

27

29

26

25

10

1

39

45

35

16

2

11

12

40

37

7

6

3

8

5

9

38

46

18

2 1

21

2 1

21

2 1

3

2

1

3

2

1

21

43

21

43

21

3

2

1

2 1

2 12 1

212

2121

21

2 12 1

2 1

2121

21

2 1

21

2 1

21

2 1

21

2 1

21

2 1

2 12 1

21

2 1

2 12 1

IN

BIOUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

S

G

DS

G

D

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

+

IN

V3R3

VDIO

GOCP-R

ALERT#

CPGOOD

CPWM3

V5DRV

V5

VREF

CDL2

PGND

GPGOOD

GCSN2

GTHERM

GSKIP#

GPWM1

VR_HOT#

GCSP2

GND

GF_IMAX

SLEW

GCSN1

GCOMP

GCSP1

GVFB

GGFB

CCOMP

CTHERM

CBST2

CSW1

GPWM2

VR_ON

COCP-R

CVFB

CGFB

CSW2

CDL1

VBAT

CDH1

CCSP2

CCSN2

CF-IMAX

CCSP3

CCSN1

CCSP1

CCSN3

CDH2

CBST1

VCLK

OUT

IN

+

1 2

IN

+

++

OUT

IN

OUT

IN

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6812

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

PAN_ETQP4LR36WFC_4P

28.7K_1%_217.8K_1%_2

TI_TPS51601DRBR_SON_8P

0.1UF_16V_2

CSC0402_DY

RSC_0603_DY

560UF_2.5V_DY

470UF_2V_DY

162K_1%_2

100K_5%_NTC

470UF_2V

FDMS7692

2.2_5%_3

PVAXG

0.033UF_16V_2

4.7UF_25V_5

1UF_6.3V_2

P5V0A

FDMS0306AS

A3 CS

Block Diagram

POWERPAD_2_0610

4.7UF_25V_5

PVBAT

R6702

C6702

L6710

C6701

Q6711Q6710

U6710

C6713

C6712

C6711

PAD6710

C6710

C6700

C6722

R6705

R6704R6703

R7671

C7671

C6721

C6720R6701

11A6

11B5

11A4

12C5

12B1

PVBAT_AXG

GSKIP#

GPWM1

GPU_CSP1

GPU_CSN1

PVBAT_AXG

21

2 1

43

21

3

2

1

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

6

72

3

9

4 5

81

2 1

2 12 1

3

2

1

21

2121

2 12 1

2 1

2121

+

S

G

D

NMOS_4D3S

D

G

S

VDD

SWSKIP#

PWM

PAD

GND DRVL

DRVHBST

OUT

12

+

IN

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4)

6813

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P3V3S_DGPU

P1V5S_DGPU

16.2K_1%_2

470UF_2V

10K_5%_2

P5V0A

PVBAT

PVCORE_DGPU

68PF_50V_2

CSC0402_DY

1UF_6.3V_2

21K_1%_2

8.66K_1%_2

240K_5%_2

9.53K_1%_2

1UF_10V_5

REA_RT8208BGQW_WQFN_16P

10K_1%_2 2.7K_1%_2

22UF_6.3V_5

1UF_10V_5

CS

A3

Block Diagram

10K_5%_2

POWERPAD_2_0610

0.1UF_16V_2

10_5%_2

0_5%_2_DY

P5V0A

POWERPAD_2_0610

2.2_5%_3 0.1UF_16V_2

FDMS0308AS

4.7UF_25V_5

FDMS7692

470UF_2V

RSC_0603_DY

PAN_ETQP4LR36WFC_4P

2K_1%_2

POWERPAD_2_0610

GMT_G9731AF11U_SOP_8P

0_5%_2_DY

22UF_6.3V_5

100K_5%_2_DY

1K_5%_2

P1V5S_DGPU

1UF_6.3V_2

PVPCIE

POWERPAD_2_0610

C6752

Q6751Q6750

C6751

C6750

R7030

C7010

R7020

R7016

PAD6751

PAD6750

C6762

C6761

R6750R6751

L6750

R7017

R7018

R7019

C7011

PAD6950

C6951

C6950

R6950

C6952

R6951

PAD6760

C6760

C6753

R7675

C7675

R6752

R6755

R6753

R6754

U6750

R6758

R6756

C6757

C6754

C6955

U6950

C6954

56F7

13C2

13D1

13B1

13B2 52C6

13A2

52C6

13A3

13A6

13C8

13B2 16A1 16A8

13D2

49A1

45D3 21D6

14D2 14B8

14A6 13A2

16C4

49A1

45D3

56D5

56C5 56F7

13C3

14D2

14A6

13D2

14B8

21D6

16A8

16A1

VRPVCORE_DGPU

DGPU_PWRGD

PWRCNTL_1

PWRCNTL_0

EN_VPCIE

DGPU_PWRGD

EN_DGPU

SLP_S3#_3R

DGPU_PWR_EN

EN_VPCIE

SLP_S3#_3R

VRPVPCIE

VRPVCORE_DGPU_PH

VRPVCORE_DGPU_LG

VRPVCORE_DGPU_HG

DGPU_PWR_EN

VRPVPCIE

3

2

1

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

3

2

1

21

2 1

21

2 1

2 12 1

43

21

2 1

2

1

21

2 1

21

2 1

21

2 12 1

21

1

9

2

12

16

11

4

8

17

14

7

3

15 5

6

10

13

2 1

21

2 1

6

5

8

9

7

1

2

4

3

2 1

+

S

G

D

NMOS_4D3S

D

G

S

+

IN

OUTIN

1 2

IN

OUT

VPP

VIN

VEN

TML

POK

GND

ADJ

VO_2

VO_1

OUT

1 2

IN

OUT

12

IN

VOUT

VDDP

VDD

UGATE

TON

PHASE

PGOOD

LGATE

GND

G1

G0

FB

EN_DEM D1

D0

CS

BOOT

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

DGPU

VCCSA

3V & 5V DDR_P1V5

P1V8S

VCCIO

6814

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P3V3_LDO

RSC_0402_DY

POWERPAD_2_0610

DIODE-BAT54-TAP-PHP

POWERPAD_2_0610

P3V3S

CSC0402_DY

47K_5%_2

0_5%_2

BAT54C_30V_0.2A_DY

0.047UF_16V_2

SSM3K7002BFU

POWERPAD_2_0610

RSC_0402_DY

0_5%_3

10K_5%_2

0_5%_2

P1V05S

PVSA

A3 CS

Block Diagram

P1V8S

47K_5%_2

DIODES_BAV99

0.1UF_16V_2

POWERPAD_2_0610

DIODES_BAV99

P3V3S

1UF_25V_3

10K_5%_2

P3V3S

10K_5%_2

0_5%_2

P3V3S

10K_5%_2

P1V5

CSC0402_DY

0.1UF_16V_2

0.01UF_50V_2

0.1UF_16V_2

P15V0A

POWERPAD1X1M

P5V0A

POWERPAD_2_0610

P3V3AL

P5V0AL

POWERPAD1X1M

POWERPAD_2_0610

PAD6121

R7000

Q7000

C7006

C7005

C7020

R7021

R7010

D7000

R7012

C7003

C7001 D7001

C7002

R7013

PAD6200

PAD6201

R7050

C7050

PAD6900

C7040

C7004

D7002

R7040

R7041

D7040

PAD6500

PAD6150

PAD6100

C7000

PAD6120

R7002

R7001

R7003

R7022

PAD6300

PAD6301

49A1

6B4

6B5

14C8

10B4

6B4

14C6 6B6

14D6

6C6 6C3

6B3

6B5

15D6

6D6

7C1

14D2

13A2

14A8 9C6

14D4 6C1

14B6

14A8

9C6

9B1

45D3

21D6

14D2

14A6

13D2

13A2

21B6 14A6 10A5

14D6 14C8 6C1

8C2

21F6

15D6

14D8

21F6

14C8

6D6

9D6

14D4 6C1

14C2

7B3

45D3

21D6

14B8

14A6

13D2

13A2 7C7

10C1

49B3

21D3

45D3 21D6

14B8 13D2

7C7

8B6

15D4 21C3

6C8

6B6

14C8

VRP1V5

VRP1V8S

VRPVCCSA

EN_3V

SLP_S3#_3R

EN_3V_5V

VRP5V0A_VIN

VRP3V3A_LDO

VRP5V0A SKIP_3V_5V

EN_SA

EC_PW_ON#

VCCP_PG

VRP1V05S

VCCP_PG

1V5_PG

VBATP

VCCP_PG

SLP_S3#_3R

SA_PGSA_PG

VRP5V0A

P5VAUXON

EN_5V

EN_VCCP

VRP5V0A_LG

1V5_PG

SLP_S3#_3R EN_0V75

SLP_S5#_3R EN_1V5

EN_1V8

VRP3V3A_LDO

P5VAUXON

VRP5V0A_LDO

VRP5V0A

VRP3V3A

21

2

1

3

2 1 2 1

2 1

21

3

2 1

21

2 1

2 13

21

2 1

21

2 1

21

2 1

3

21

2 1

2

13

21

2 1

21

IN

OUT

1 2

IN

1 2

IN

OUTIN

OUT

NC

IN

1 2

IN

1 2

IN

OUT

IN

1 2

IN

1 2

OUT

IN

1 2

IN

G

DS

IN

C

A2A1

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6815

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

POWERPAD_2_0610

SSM3K7002BFU

P5V0S

POWERPAD_2_0610

TI_TPS3801_01_SC70_5P

SSM3K7002BFU

200_5%_2

P0V75S

22UF_6.3V_5 22UF_6.3V_5

SSM3K7002BFU

200_5%_2

SSM3K7002BFU

22UF_6.3V_5

2200PF_50V_2

SSM3K7002BFU

P5V0A

0_5%_2

CSC0402_DY

470K_5%_2

P1V5

2200PF_50V_2

0_5%_2

680PF_50V_2

10K_5%_2

P3V3AL

100K_5%_2

100K_5%_2_DY

P3V3AL

200_5%_2

AO6402AL

P15V0A

AO6402AL

P1V5S

DIODE-BAT54-TAP-PHP

510K_1%_2

120K_1%_2

PVBAT P3V3_LDO

P15V0A

AO6402AL

POWERPAD_2_0610

200_5%_2

A3 CS

Block Diagram

200_5%_2

P3V3A

P3V3AL

0_5%_2

CSC0402_DY

AON7410

P3V3S

Q7104

Q7111

Q7110

Q7108

Q7106

Q7103

Q7101

C7101

C7100

R7104

R7100

Q7102

D7490

R7492

U7490

Q7112

Q7105

R7108

Q7107

R7106

PAD7100

R7105

R7109R7111

R7114

R7113

R7491

PAD7101

C7103

C7102

PAD7102

C7105

C7104

PAD7103

C7107

C7106

Q7109

R7110

R7112

R7107

49B1

15B8

56D6

16A7

15B4

15B8

16A7

15B4

15B8

15A4

15B4

16A7

15B4

15A4

21C3

14C8

14D8

21F6

40A8 40B1

15A4 SLP_S3_3R

SLP_S3_3R

P5VAUXON

EC_PW_ON#

THRM_SHUTDWN#

2

1

3

2

1

3

2

1

3 2

1

3 2

1

3

2

1

3

2

1

3

2 1

2 12 1

4

36

5

2

1

2

13

2 1

4

5 3

2

1

3

2

1

45

6

7

8

4

36

5

2

1

21

4

36

5

2

1

2 1

21

2 1

2 12 1

2 1

21

2 1

3

2

1

45

6

7

8

21

2 1

VDD

SENSE RESET#

GND

NMOS_4D3S

D

G

S

D

G

S

NMOS_4D1S

D

G

S

NMOS_4D1S

1 2

IN

OUT

12

1 2

NMOS_4D3S

D

G

S

G

DS

G

DS

G

DS

G

DS

G

DS

G

DS

G

DS

D

G

S

NMOS_4D1S

OUT

NC

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

POWER EXPRESS

DGPU_PWR_EN#

DGPU_PWRGD

DGPU_HOLD_RST#

AFTER RESET

HIGH

DURING RESET

HIGH

LOW

0 : DGPU POWER SWITCH TURNED ON

0 : DGPU POWER IS NOT STABLE

1 : DGPU POWER IS STABLE

0 : KEEP DGPU IN RESET

LOW

1 : POWER SWITCH TURNED OFF

1 : RESET IS RELEASED

6816

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

680PF_50V_2

SSM3K7002BFU

0_5%_2

CSC0402_DY

0_5%_2_DY

SSM3K7002FU

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

0_5%_2_DY

P1V8S

0_5%_6_DY

AO6402AL

10K_5%_2

CSC0402_DY

SSM3K7002BFU

SSM3K7002FU

Block Diagram

CS

A3

200_5%_2

0_5%_2

P3V3S

SSM3K7002BFU

10K_5%_2

CSC0402_DY

AON7410

220K_5%_2

P3V3S

P3V3S P3V3S_DGPU

200_5%_2

AON7410

P1V8S_DGPU

P1V5 P1V5S_DGPU

680PF_50V_2

220K_5%_2

1M_5%_2

P15V0A

P3V3_LDO

10K_5%_2

SSM3K7002BFU

R7047

R7038

R7042

R7121

C7024

C7023

Q7018

R7034

Q7019

R7033

C7022

R7035

Q7002

Q7003

R7031

R7039

C7021

Q7120

Q7113

Q7114

R7115

Q7115

C7108

Q7118

R7119

Q7119

C7110

R7120

R7116

16C7 16A6

16B7 16A6

13D2

13B2

51C7

16A1 16C4 13B2

16A8 16A1 13D2 13B2

16D7

13D2 16A8 16C4

51B6

16A5 16B7

16A5

16D7 16B7

16B7

16C7

SLP_S3_3R

DGPU_PWR_EN_3R

DGPU_PWR_EN

DGPU_PWR_EN_15R

DGPU_PWR_EN#

DGPU_PWR_EN_15R

DGPU_PWR_EN_3R

DGPU_PWR_EN_15R

DGPU_PWR_EN_3R

21

2 1

2

1

3

2 12

1

3

2 1

21

2

1

3

S

G

D

2 1

21

2 1

2

1

3

2

1

45

6

7

8

3

2

1

45

6

7

8

2 12

1

3

2 1

4

36

5

2

1

2 12

1

3

2 1

21

IN

G

DS

OUT

G

DS

IN

G

DS

G

SD

IN

G

DS

OUT

IN

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

IN

G

DS

D

G

S

NMOS_4D1S

G

DS

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 0~49(PCB SCREW)

PCB

BOUNDARY SCAN TEST POINT

3G

CPU WLANGPU

FAN

6817

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SCREW220_700_1P

SCREW300_1000_1P

SCREW540_1000_NP_1P

SCREW300_1000_1P

SCREW330_600_1P

SCREW300_1000_1P

FIX_MASK

SCREW300_1000_1P

PVCORE_DGPU

PVADPTR

SCREW330_600_1P

Block Diagram

1.6MM

STDPAD_1.15_6-TOP

SCREW120_0_600_1P

TP30

TP30 TP30TP30

FIX_MASK

TP30

FIX_MASK

TP30

PVCORE

TP30

PVBAT

PVAXG

TP30

CS

A3

FIX_MASK

SCREW330_600_1P

STDPAD_1.15_6-TOP

1.6MM

STDPAD_1.15_6-TOP

SCREW330_600_1P

S18

S20

S8

S7

S6

S5

S3

S2

S1

S23

S24

STD18

STD17

STD16

TP9TP8 TP10

TP1

TP6

TP5

TP7

TP4TP3

TP2

S21

S15

S14

S13

S10

S11

S12

FIX5

FIX6

FIX7

FIX1

FIX2

FIX3

FIX8FIX4

1

11 1

1

11

1

11

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 50-99(HALL SENSOR)

6818

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

100K_5%_2

VARISTOR_DY

P3V3AL

1000PF_50V_2

MAG_MH248BESO_SOT23_3P

Block Diagram

CS

A3

R50

D50

C50

U50

21D3

LID_SW#_3

2 1

1

2

3

OUT

GND

OUT

VDD

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

WIFI/WIMAX/3G/LTE LED

POWER ON LED

SUSPEND LED

REFERENCE 100~199(LED)

BLINK:LOW BATTERY

D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED

DC IN / BATTERY CHARGE LED

6819

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

TP30

150_5%_2

19_217_T1D_CP1Q2QY_3T

19_217_T1D_CP1Q2QY_3T 220_5%_2

150_5%_2

Block Diagram

CS

A3

HT_191UY

P3V3A

TP30

HT_191UY

P5V0S

HT_191UY

P3V3AL

150_5%_2

TP30

P5V0A

220_5%_2

TP30

P3V3S

TP104

TP103

TP102

TP101

TP100

D155

R154

D156

R155

D152

R152

D159

R150

D154

R160

21B6

21D6

21B6

21D6

WL_OLED#

PWR_WLED#

PWR_OLED#

BAT_OLED#

DCIN_WLED#

1

21 21

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

KEYBOARD CONN

TOUCHPAD CONN

REFERENCE 250~299(KB/TP CONN)

REFERENCE 200~249(POWER CONN)

POWER CONN

6820

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

200_5%_2

ACES_50224_0020N_001_2P

Block Diagram

CS

A3

0

1

VARISTOR_DY

1

6

5

0

4

3

7

0_5%_2_DY

P3V3S

3

12

8

14

10

6

9

5

11

0

1

15

13

2

4

17

16

2

7

PTWO_AFF340_A2G1V_P _34P

2

3

6

7

VARISTOR_DY

5

4

VARISTOR_DY VARISTOR_DY

VARISTOR_DY

P5V0S

ACES_50503_0044N_001_4P

PHP_PESD5V2S2UT_SOT23_3P_DY

CN200

D257

D256

D255

D254

D253

D252

D251

D250

CN250

CN280

D280

D200

D260D259D258

R252

R251

R250

R253

21D2

21B3 20C6

21D6

21B6

21B3

21B3 20D3

21D3

21D2

PWR_SWIN#_3

IM_DAT_5

SCAN_IN<7..0>

NUM_LED#_3

SCROLL_LED#_3

CAPS_LED#_3

SCAN_OUT<17..0>

SCAN_IN<7..0>

SCAN_IN<1>

SCAN_IN<6>

SCAN_IN<5>

SCAN_IN<0>

SCAN_IN<3>

SCAN_IN<2>

SCAN_IN<7>

SCAN_OUT<3>

SCAN_OUT<7>

SCAN_OUT<12>

SCAN_OUT<8>

SCAN_OUT<14>

SCAN_OUT<10>

SCAN_OUT<6>

SCAN_OUT<5>

SCAN_OUT<0>

SCAN_OUT<1>

SCAN_OUT<15>

SCAN_OUT<13>

SCAN_OUT<2>

SCAN_OUT<4>

SCAN_OUT<17>

SCAN_OUT<16>

SCAN_OUT<11>

SCAN_OUT<9> SCAN_IN<0>

SCAN_IN<2>

SCAN_IN<3>

SCAN_IN<4>

SCAN_IN<7>

SCAN_IN<6>

SCAN_IN<5>

SCAN_IN<1>

SCAN_IN<4>

IM_CLK_5 4

3

2

1

21

G2

G1

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

G2

G1

4

3

2

1

3

2

1

21

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

G1

G2

G

4

3

2

1

IN

OUT

BI

IN

OUT

G

2

1

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

1.CHARGE

2.GPU THERMAL

1.BATTERY

EC_SMB1

3.CEC

FOR ESD PROTECT

CLOSE PIN4

REFERENCE 300~389(KBC)

EC_SMB2 EC_SMB3

PM: 10K

GM: 100K

21 68

MODEL,PROJECT,FUNCTION

X01

XXX 21-OCT-2002

1310xxxxx-0-0

10K_5%_2

TP30

WINB_NPCE885LA0DX_LQFP_128P

POWERPAD1X1M

TP30

P3V3AL

TP30

AGND_KBC

4.7K_5%_2

10K_5%_2

10K_5%_2_DY

0_5%_1

TP30

10K_5%_2

TP30

100K_5%_2

TP30

P3V3S

TP30

1.8K_5%_2

10K_5%_2

47K_5%_2

TP30

33_5%_2

P3V3AL

0.1UF_16V_2_DY 0.1UF_16V_2

P3V3AL

4.7UF_6.3V_3

680PF_50V_2

0.1UF_16V_2

10K_5%_2

100K_5%_2

7

6

3

4

5

2

1

0

17

15

16

14

12

13

10

11

9

7

8

5

4

6

2

3

0

1

WINB_NPCE885LA0DX_LQFP_128P

100K_5%_2

DIODE-BAT54-TAP-PHP

2.2_5%_3

CSC

Block Diagram

10K_5%_2

3.3K_5%_2

P3V3S

P3V3AL

P3V3AL_R

P3V3AL

P3V3AL P3V3AL_R

P5V0S

SSM3K7002BFU

0.1UF_16V_2

10UF_6.3V_5_DY

0.1UF_16V_2

1UF_6.3V_2

P3V3AL

3.3K_5%_2

10K_5%_2

P3V3AL

3.3K_5%_2_DY

MXIC_MX25L3206EM2I_12G_SOP_8P_DY

MXIC_MX25L3206EM2I_12G_SOP_8P

P3V3AL_EC

AGND_KBC

0.1UF_16V_2

33_5%_2

47K_5%_2

FBM_11_160808_121T

P3V3AL

10K_5%_2_DY

TP30

P3V3AL_EC

P3V3S

0.1UF_16V_2

10UF_6.3V_5_DY

P3V3AL_EC

100K_5%_2

0_5%_1

P1V05S

43_5%_2

R303

TP326

TP325

TP324

TP323

TP322

TP321

TP320

TP319

TP318

TP317

TP316

TP315

TP314

TP313

TP311

TP310

R335

R334

U302

C318

R319

R315

R345R344

R302

R301

Q300

R339

U301

R300

R346

R326

R312

R324

TP307

TP306

TP305

TP304

TP303

R333

C311

R320

D300

C309

R314

R313

U300

C317

C315

L300

C314

C305

C306

C312

C304

C303

C302

C301

C300

C313

R318

R311

R308

R321

R322

R317

R316

R336

R332 R323

PAD319

C310

R342

R341

R340

5B8

20B7

49A5

49B8

49A8

20B7

37B1

13A2

21E6

21F4

22B5

49B3

19C7

47A6

45D3

40C8

18C4

47B7

27B2

52D6 51C7

20A4

40C6

49B7 49A6

21B6

32A8

21C8

32C1

19B4

14A6

34B5

21E8

21E8 5B7

5D3

49C2

20A8 21D2

11A8

21D1

30A3

20A8

20D3

19D7

20C7

31A5

32A8

31D4

36B2

22D7

49A6

37C6 56D8

56C8

21D3 27B2

21D3

21D3 5D3

5D3

21D3

5A7

51A8 57A6

10A5

14D2

21C7

21C6

21C7

21D6

14D8

21C8

21C7

27C2

5A7

49B7

20A8

20D6

5D3

21D2

52C2

21D3

14D8

21D2

5D3

47C2 27B7

47C3 27C3

51A7

27C7 27C3

21D2

21E6 5B7

21E6 5D3

21B6

49A5 49B3

49B7 49C2 21D3

28C3

52C2

20A8

27C2

21D2

15D4

21D2

56D8

56C8 37C3

49B3

11B7 41D6

21B6

47A6

14C8 15D6

21C6

47A6

21C7

21C6

21C8

47A6 21D6

21C6

21C7

21D6

47A6

32C3

32A8

21B1

30B6

14D2

32A8

32A6

13D2

24A2

40C8

14A6

19A7

47B8

14B8

21D3

49A1

33C6

33D8

21E6 56D6

50D7

20C6

41D5 52C2

SLP_S3#_3R

HDMI_HPD_EC

SCROLL_LED#_3

NUM_LED#_3

ACPRESENT

EC_PWRSW#

LOW_BAT#_3

WL_OLED#

USB_OC#_1

EC_MUTE#

WOL_AUX_ON#

LCM_BKLTEN

ACPRES

SLP_S5#_3R

H_PROCHOT_EC

SB_USB_2

RSMRST#

PWR_SWIN#_3

EC_BKLTEN

EC_SPI_SO_R

EC_SPI_SI_R

USB30_PWR_EN

EC_ILIM_SEL

EC_CTL2

PWR_WLED#

SB_USB_1

EC_CTL1

EC_PW_ON#

LID_SW#_3

FLASH_OVERRIDE

EN_PVCORE

IM_DAT_5

USB_OC#_2

IM_CLK_5

BATT_IN

HW_I_ADC

P3V3AL_EC_VREF

EC_SPI_CS0#

EC_SPI_CLK_R

WLON#

EC_SMB2_DATA

EC_SMB1_DATA

AOAC_ON#

EC_SMB2_CLK

EC_SMB1_CLK

RUNSCI0#_3

KBRST#

EC_3S_A20GATE

PCI_3S_SERIRQ

BUF_PLT_RST#

CLK_KBPCI

LPC_3S_FRAME#

LPC_3S_AD<0>

LPC_3S_AD<1>

LPC_3S_AD<2>

LPC_3S_AD<3>

PCI_3S_CLKRUN#

EC_PECI

VCC_POR#

EC_32KHZ

LAN_RST#

CPU_PROCHOT#

FAN1_PWM

DCIN_WLED#

CAPS_LED#_3

PWR_OLED#

FAN_TACH1

PCH_PWROK

BAT_OLED#

EC_SPI_SO

EC_SPI_SI

EC_SPI_CLK

AOAC_ON#

WLON#

SCAN_OUT<8>

SCAN_OUT<5>

SA_PG

EC_SPI_SI

FAN_TACH1

RSMRST#

SCAN_OUT<14>

SCAN_OUT<13>

SCAN_OUT<17..0>

SCAN_OUT<7>

SCAN_OUT<6>

SCAN_IN<7>

SCAN_IN<6>

SCAN_IN<3>

SCAN_IN<4>

SCAN_IN<5>

SCAN_IN<2>

SCAN_IN<1>

SCAN_IN<0>

SCAN_OUT<17>

SCAN_OUT<15>

SCAN_OUT<16>

SCAN_OUT<12>

SCAN_OUT<10>

SCAN_OUT<11>

SCAN_OUT<9>

SCAN_OUT<4>

SCAN_OUT<2>

SCAN_OUT<3>

SCAN_OUT<0>

SCAN_OUT<1>

P5VAUXON VCC_POR#

IM_CLK_5

H_PROCHOT_EC

EC_SPI_CLK

EC_SPI_SI

EC_SPI_CLK

EC_SPI_SO

EC_SPI_CS0#

EC_SPI_SO

HW_I_ADC

IM_DAT_5

EC_SMB1_CLK

EC_SMB1_DATA

EC_SMB2_CLK

EC_SMB2_DATA

EC_SPI_CS1#

BATT_IN

VGA_LCM_BKLTEN

PCH_LCM_BKLTEN

LCM_BKLTEN

SCAN_IN<7..0>

H_PECI

21

1

2 1

3

8

2

5

6

7

4

1

2 1

21

2 1

21

2

1

3

21

12

85

13

41

42

43

47

48

49

50

51

35

36

37

38

39

40

52

53

61

60

59

58

57

56

55

54

111

113

81

34

33

31

30

22

16

66

65

118

32

63

62

64

77

104

4

44

115

88

76

46

19

125

7

3

2

1

128

127

126

122

112

110

107

106

105

101

100

99

98

97

121

91

84

83

82

68

67

75

74

73

123

9

28

27

26

25

24

23

21

20

17

80

7215

7114

120

109

11

10

6

119

69

117

70

114

8

124

94

93

108

96

95

79

5

116

89

78

45

18

87

86

92

90

29

102

103

2 1

1

2 1

2

13

2 1

21

3

8

2

5

6

7

4

1

2 1

21

2 1

21

2 1

21

2 1

21

IN

12

OUT

BI

IN

OUT

IN

BI

OUT

IN

OUT

IN

WP#_ACC

VCC

SO_SIO1

SI_SIO0

SCLK

HOLD#

GND

CS#

OUT

IN

OUT

IN

OUTIN

OUT

G

DS

OUT

BI

KBSOUT11_P80_DAT/GPIOC3

KBSOUT10_P80_CLK/GPIOC2

GPIO55/CLKOUT/IOX_DIN_DIO

VTT

PECI

GPIO87/CIRRXM/SIN_CR

GP(I)O83/SOUT_CR/TRIST#

GPIO00/EXTCLK

VCC_POR#

GPIO40/F_PWM

GPIO45/E_PWM

GPIO33/H_PWM

GPIO66/G_PWM

GPIO32/D_PWM

GPIO13/C_PWM

GPIO21/B_PWM

GPIO15/A_PWM

GPIO01/TB2

GPIO14/TB1

GPIO56/TA1

KBSIN7/GPIOA7

KBSIN6/GPIOA6

KBSIN5/GPIOA5

KBSIN4/GPIOA4

KBSIN3/GPIOA3

KBSIN2/GPIOA2

KBSIN1/GPIOA1/N2TMS

KBSIN0/GPIOA0/N2TCK

GPIO57/KBSOUT17

GPIO60/KBSOUT16

KBSOUT15/GPIO61/XOR_OUT

KBSOUT14/GPIO62

KBSOUT13/GPIO63

KBSOUT12/GPIO64

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT8/GPIOC0

KBSOUT7/GPIOB7

KBSOUT6/GPIOB6/RDY#

KBSOUT5/GPIOB5/TDO

KBSOUT4/GPOB4/JEN0#

KBSOUT3/GPIOB3/TDI

KBSOUT2/GPIOB2/TMS

KBSOUT1/GPIOB1/TCK

KBSOUT0/GPOB0/JENK#

F_SDIO_F_SDIO0

F_SDI_F_SDIO1

GPIO51/N2TCK

GPIO36

GPIO20/TA2/IOX_DIN_DIO

GPIO34/CIRRXL

GPIO02

VCORF

GPIO16

GP(I)O84/IOX_SCLK/XORTR#

GPO82/IOX_LDSH/TEST#

GPIO30/F_WP#

GPIO05/AD4

GPIO97/DA3

GPIO04/AD5

GPIO03/AD6

GPIO07/AD7

GPIO06/IOX_DOUT

GPIO81/F_WP#

GPIO77/SPI_DI

GPIO76/SPI_DO

GPIO75/SPI_SCK

GPIO41/F_WP#

GPIO72

GPIO71

GPIO70

GPIO53/SDA4A

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO47/SCL4A

GPIO46/SDA4B/CIRRXM/TRST#

GPIO44/SCL4B/TDI

GPIO43/SDA3B/TMS

GPIO42/SCL3B/TCK

GPIO24 GPIO27/PSDAT2

GPIO35/PSDAT1

GPIO26/PSCLK2

GPIO37/PSCLK1

GPIO96/DA2

GPIO95/DA1

GPIO94/DA0

GPIO93/AD3

GPIO92/AD2

GPIO91/AD1

GPIO90/AD0

VREF

F_CS0#

F_SCK

GPIO31/SDA3A

GPIO74/SDA2

GPIO22/SDA1/N2TMS

GPIO23/SCL3A

GPIO73/SCL2

GPIO17/SCL1/N2TCKGPIO67/N2TMS

GPIO10/LPCPD#

GPIO65/SMI#

ECSCI#/GPIO54

KBRST#/GPIO86

GPIO85/GA20

SERIRQ/GPIOF0

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD0/GPIOF1

LAD1/GPIOF2

LAD2/GPIOF3

LAD3/GPIOF4

GPIO11/CLKRUN#

AGND

GND6

GND5

GND4

GND3

GND2

GND1

VDD

AVCC

VCC5

VCC4

VCC3

VCC2

VCC1

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

OUT

IN

OUT

BI

OUT

BI

IN

BI

OUT

IN

OUT

OUTIN

NC

OUT

IN

OUT

IN

OUT

WP#_ACC

VCC

SO_SIO1

SI_SIO0

SCLK

HOLD#

GND

CS#

OUT

IN

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7654321

76543

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

FOR LDO MODE

REFERENCE 400~499(LAN)

FOR SW MODE

C417:8161 STUFF 8162 OPEN

6822

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

P3V3A

1UF_6.3V_2

0.1UF_16V_2

10K_5%_2_DY

10K_5%_2

PAVDDH_LAN

0.1UF_16V_2

RSC_0603_DY

1000PF_50V_2_DY

10UF_6.3V_5_DY

PDVDDL_LAN

1UF_6.3V_2

0.1UF_16V_2_DY

P3V3A_LAN

PDVDDL_LAN

1UF_6.3V_2

30K_5%_2

P3V3S

PAVDDL_LAN

10UF_6.3V_5_DY

1UF_6.3V_2

4.7UF_6.3V_3

P3V3A_LAN

0.1UF_16V_2

PVLX_LAN

100K_5%_2

ATHEROS_AR8161_AL3A_R_QFN_40P

0.1UF_16V_21UF_10V_2_DY

0.1UF_16V_2

1UF_10V_2_DY

PAVDDL_LAN

PAVDDH_LAN

0.047UF_16V_2

0.1UF_16V_2

2.37K_1%_2

0.1UF_16V_2 0.1UF_16V_2

33PF_50V_2

LQM21PN2R2MC0D_DY

PAVDDVCO_LAN

P3V3A_LAN

PAVDDL_LAN

POWERPAD_2_0610

PVLX_LAN

25MHZ

33PF_50V_2

Block Diagram

CS

A3

0.1UF_16V_2

0_5%_3

0.1UF_16V_2

Q400

R404

C427

C414

C412

C403

U400

R402

R406L400

C424

C405

C418

C407

C406

R403

C408

C402

R401 C421

C422

C420

C425

C423

C419

C417

C416

C404

PAD400

C401

R400

C400

C426

R405

C415

C413

C410

X400

C409

22A5

31C6

27C7

49A5

49B3

22A5

48C7

21B6

48C7

23B7

48D8

22B5

48D7

48D8

23B7

23C6

22B5

23C6

23B7

21D6

23C6

23B7

48C7

48D8

LAN_X1

LAN_X2

CLKREQ_LAN#

PCIE_LAN_RX_C_DP

PCIE_LAN_RX_C_DN

PCIE_LAN_TX_DP

CLK_PCIE_LAN_DN

CLK_PCIE_LAN_DP

PCIE_LAN_TX_DN

LAN_TRD0_DP

PCIE_LAN_RX_DP

PCIE_LAN_RX_DN

LAN_X2

LAN_RST#

PCIE_WAKE#

LAN_TRD3_DN

LAN_X1

LAN_TRD0_DN

LAN_TRD1_DN

WOL_AUX_ON#

LAN_TRD1_DP

LAN_TRD2_DP

LAN_TRD2_DN

LAN_TRD3_DP

S

G

D

2 1

7

8

3

130

29

14

11

15

12

27

26

25

35

36

33

32

10

24

2

28

40

23

39

38

5

41

37

4

6

13

9

16

34

31

22

21

20

19

18

17

2 1

2121

2 1

21

2 1

2 12 1

2 1

21

2 1

21

2 1

21

2 1

21

2 1

1 2

G

SD

TX_P

TX_N

TESTMODE

SMDATA

SMCLK

PPS

NC

LED_2

AVDDH

TRXN3

XTLO

XTLI

WAKEN

VDD33

TRXP1

TRXP0

TRXN1

TRXN0

RX_P

RX_N

REFCLK_P

REFCLK_N

RBIAS

PERSTN

LX

LED_1

LED_0

ISOLATN

GND

DVDDL_REG

CLKREQN

AVDDL_REG

AVDDL

AVDDH_REG

AVDD33

AVDDL

AVDDLTRXP3

AVDDL

TRXN2

TRXP2

OUT

IN

OUT

BI

IN

OUT

IN

OUT

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 400~499(LAN)

6823

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SANTA_13045_8P

BOTH_TS21C_HF_SOP_16P

CSC0402_DY

PAVDDL_LAN

CSC0402_DY

BOTH_GST5009_RA_SOP_24P

1UF_6.3V_2

1000PF_2000V_6

0.1UF_16V_2

CSC0402_DY

0.1UF_16V_2

100PF_50V_2

CSC0402_DY

75_5%_3

RSC_0603_DY

RSC_0402_DY

RSC_0603_DY

75_5%_3

Block Diagram

CS

A3

JACK470

U470

R470

C475

R476

R478

R479

R477

R475

R474

R473

R472

R471

C477

C476

U471

C479

C478

C474

C473

C483

C472

C482

C471

C481

C470

C480

23C3

23B3

22B5

23C6 22B5

23B7 22B5

23C2 23B3

23C3 23B3

23C2 23B3

23C3

23C3 23B3

23D5 23C2

23D5 23B3

23D5 23C2

23D5 23C3

23D5 23B3

LAN_TRD0_DP

LAN_TD_DP

LAN_C_DP

LAN_C_DN

LAN_D_DN

LAN_D_DP

LAN_RD_DN

LAN_RD_DP

LAN_TD_DN

LAN_D_DP

LAN_C_DP

LAN_RD_DP

LAN_TD_DP

LAN_D_DN

LAN_C_DN

LAN_RD_DN

LAN_TD_DN

LAN_TRD3_DP

LAN_TRD2_DP

LAN_TRD1_DP

LAN_TRD3_DN

LAN_TRD2_DN

LAN_TRD1_DN

LAN_TRD0_DN

LAN_TRD1_DP

LAN_TRD1_DN

LAN_TRD0_DP

LAN_TRD0_DN

LAN_RD_DN

LAN_RD_DP

LAN_TD_DP

LAN_D_DN

LAN_C_DN

LAN_D_DP

LAN_C_DP

G2

G1

8

7

6

5

4

3

2

1

12

11

9

8

6

5

3

2

10

7

4

1

13

14

16

17

19

20

22

23

15

18

21

24

2 1

14

16

3

1

9

11

8

6

7

5

4

2 15

13

12

10

2 1

IN

G

P8

P7

RX-

P5

P4

RX+

TX-

TX+

MX4+

MX3+

MX2+

MX1+

MX4-

MX3-

MX2-

MX1-

MCT4

MCT3

MCT2

MCT1

TD4+

TD3+

TD2+

TD1+

TD4-

TD3-

TD2-

TD1-

TCT4

TCT3

TCT2

TCT1

OUT

IN

OUT

IN

OUT

IN

TX-

TX+

TD-

TD+

RX-

RX+

RD-

RD+

RCT

NC

TCT TCT

NC

RCT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

(THERMAL PAD 4X4 VIAS)RESERVE FOR EMI

DIGITAL

ANALOG

BLM18PG121SN1(6014B0041601_0603)

CLOSE TO PIN13

BLM18PG121SN1(6014B0041601_0603)

REFERENCE 500~549(AUDIO CODEC)

TIED UNDER OR NEAR CODEC

CLOSE TO PIN27

6824

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P5V0S_AUDIO_AVDD

P5V0S P5V0S_AUDIO_AVDD

P3V3A

P3V3S

AGND_AUDIO

P5V0S

P5V0S_AUDIO_AVDD

AGND_AUDIO

2.2UF_6.3V_3 10UF_6.3V_3

REA_ALC269Q_VB6_CGT_QFN_48P

4.7K_1%_2

100PF_50V_2

47K_1%_2

0.1UF_16V_2

0_5%_3

0.1UF_16V_2

100_5%_2

22PF_50V_2_DY

0.1UF_16V_2

1UF_6.3V_2

0.1UF_16V_2

22_5%_2

0_5%_2

39.2K_1%_2

20K_1%_2

10UF_6.3V_3_DY

0.1UF_16V_2_DY

0_5%_3

4.7UF_6.3V_3

0.1UF_16V_2 4.7UF_6.3V_3

0.1UF_16V_2

0_5%_3

4.7UF_6.3V_3

2.2UF_6.3V_3

0.1UF_16V_2

4.7UF_6.3V_3

Block Diagram

CS

A3

2.2UF_6.3V_3 0.1UF_16V_2

1000PF_50V_2

POWERPAD1X1M

1000PF_50V_2

C512

U500

R505

R516

R515

PAD500

C517

C516

C515

C514

C518

C510

C522

C508

C509

C529

C531

R510

R509

R511

R512

C532

C506

C507

C505

C500

C536

R503

R502

R506

C521

R507

C520

R501

R500

R514

C504

C501

C513C519

C502

C503

25D3

21D6

47B7

47C7

47B7

47C8

34B3

25B2

25C5

25C2

25C2 25B8

25B8

25B3

25D3

25A3

HDA_R_BITCLK

HP_R

HP_L

MIC_REF_L

MIC_REF_R

MIC_R

MIC_L

HDA_3S_RST#

HDA_3S_SYNC

HDA_R_SDIN0

HDA_3S_SDOUT

EC_MUTE#

MIC_IN_CLK_R

MIC_IN_DATA

MIC_IN_CLK

HDA_3S_SDIN0

HDA_3S_BITCLK

PCSPKR_PCH_3

HPS

MICS

SPK_OUT_R_N

SPK_OUT_R_P

SPK_OUT_L_P

SPK_OUT_L_N

P5V0S_PVDD

2 1

2710

44

45

41

40

48

18

13

5

8

11

43

42

46

39

4

12

20

29

17

16

30

31

22

21

15

14

24

23

28

19

33

32

3

2

49

47

7

1

9

34

36

35

6

37

26

38

25

21

2 1

21

2 1

21

2 1

2121

21

2 1

IN

BI

GND

SPDIFO

EAPD

PVDD2

SPK-R+

SPK-R-

PVSS2

PVSS1

SPK-L-

SPK-L+

PVDD1

AVDD2

AVSS2

CBP

CBN

CPVEE

HP-OUT-R

HP-OUT-L

MIC1-VREFO-L

MIC1-VREFO-R

MIC2-VREFO

LDO-CAP

VREF

AVSS1

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

PCBEEP

RESET#

SYNC

DVDD-IO

SDATA-IN

DVSS2

BIT-CLK

SDATA-OUT

PD#

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

DVDD1

BI

OUT

1 2

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH

RESERVE FOR EMI

MICPHONE

RESERVE FOR EMI

REFERCE 600~649(JACK/MIC/SPEAKER)

RESERVE FOR EMI

AUDIO JACKS

HEADPHONE

INTERNAL SPEAKERS

6825

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

470PF_50V_2_DY

SINGA_2SJ_T351_019_6P

TP30

AGND_AUDIO

A3 CS

Block Diagram

75_5%_2

0_5%_3

1K_5%_2

2.2K_5%_2 2.2K_5%_2

CSC0402_DY

2.2UF_6.3V_3

470PF_50V_2_DY

PHP_PESD5V2S2UT_SOT23_3P_DY

CSC0402_DY

470PF_50V_2_DY

ACES_50224_0040N_001_4P TP30

470PF_50V_2_DY

0_5%_3

75_5%_2

0_5%_3

TP30

AGND_AUDIO

470PF_50V_2_DY

0_5%_3

SINGA_2SJ_T351_019_6P

TP30

AGND_AUDIO

470PF_50V_2_DY

JACK601

JACK600 TP607

TP606

TP605

TP604

TP603

TP602

TP601

TP600

C607

C606

C605

C602

C603

C604

C609

C608

C611

C610

CN600

D600

R600

R601 R609

R608

R607

R606

C601C600

R604R605

R603

R602

24D3

24C7

24C2

24D3

24B2

24C7

24B2

SPK_OUT_L_N

SPK_OUT_R_N

SPK_OUT_R_P

HPS

HP_L

MIC_REF_L

MIC_REF_R

MIC_L

MIC_R

HP_R

SPK_OUT_L_P

MICS

G2

G1

6

5

4

3

2

1

G2

G1

6

5

4

3

2

1

21

2 1

G2

G1

4

3

2

1

3

2

1

21

21 21

21

2 1

21

IN

OUT

IN

G1

1

2

3

4 G2

IN

BI

IN

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERNCE 900~999(CARDREADER)

RESERVE FOR EMI

6826

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

REA_RTS5129_QFN_24P

1UF_6.3V_2

0.1UF_16V_2

2.2UF_6.3V_3

P3V3S_CR

A3 CS

Block Diagram

P3V3S

POWERPAD_2_0610

4.7UF_6.3V_3 0.1UF_16V_2

6.2K_1%_2

1UF_6.3V_2

0.1UF_16V_2

P3V3S_CR

0_5%_2

TAI_PSDAT0_09GLBS1ZZ4H1_11P

CN900

C901

U900

C905 C906

R901

C904

C902

C903

C900

PAD900

R900

26C5

26C7

26C5

26B5

26C7

26C5

26B3

51B2

26B3

26D5

P3V3S_CARD

CARD_REF

SD_D2

SD_D3

SD_CMD

SD_CD#

SD_R_CLK SD_CLK

SD_D0

USB_CR_DN

USB_CR_DP

SD_WP

SD_D1

SD_D3

SD_CD#

SD_CMD

SD_D0

SD_D1

SD_D2

SD_WP

SD_CLK

11

6

3

4

G2

G1

9

8

7

2

5

1

10

2 1

23

724

25

16

15

14

13

12

11

10

922

21

20

19

18

8

6

1

17

3

2

5

4

2 1

21

2 1

21

BI

WRIT_PROTECT

VSS2

VSS1

VDD

G2

G1

DAT2

DAT1

DAT0

CMD

CLK

CD-DAT3

CARD_DETECT

BI

XD_D7

XD_CD#V18

TML

SP9

SP8

SP7

SP6

SP5

SP4

SP3

SP2SP14

SP13

SP12

SP11

SP10

SP1

SDREG

RREF

GPIO0

DP

DM

CARD_3V3

3V3_IN

BI

BIBI

1 2

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

SUPPORT AOAC:OPEN

MINI CARD 1(WLAN)

SUPPORT AOAC:STUFF

REFERENCE 1300~1349(WLAN)

6827

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

0_5%_5

AM3423P_DY

BELLW_80003_4021_52P

0_5%_2_DY

0_5%_2

SSM3K7002BFU

P3V3S

CSC0402_DY

10UF_6.3V_3

0.1UF_16V_2

P1V5S

10UF_6.3V_3

0.1UF_16V_2

P3V3A

P3V3S

Block Diagram

CS

A3

0_5%_2

CN1300

Q1301

Q1300

C1306

C1307

R1304

C1302

C1301

R1300

C1304

C1305

R1302

R1303

R1301

48D8

27C7

47C3 21E3

21E3

47C3 21E3

51A8 28C3

47C3 21E3

48D2 48D8

21D2

47C3

21E3 47C3

21E3

57A6

51B2

48D3

48D2

48D3

48B7 48D7 48D8

51B2

21D2

48B7

48D8

51A7

21E3 27C3 28C3 51A8 57A6

48B7

48D8

27C7 52B6

21E3

27B7 52B6

22B5 31C6 49A5 49B3

21D3

47C2

AOAC_ON#

LPC_3S_AD<0>

PCH_3A_ALERT_CLK

PCH_3A_ALERT_DAT

CLK_PCIE_WLAN_DN

CLK_PCI_DEBUG

BUF_PLT_RST#

CLKREQ_WLAN#

BUF_PLT_RST#

LPC_3S_FRAME#

LPC_3S_AD<3>

LPC_3S_AD<2>

LPC_3S_AD<1>

PCI_3S_SERIRQ

BTIFON#

WLON#

CLK_PCIE_WLAN_DP

PCIE_WLAN_RX_DN

PCIE_WLAN_RX_DP

BTIFON#

PCIE_WLAN_TX_DN

PCIE_WLAN_TX_DP

PCIE_WAKE#

USB_WLAN_DN

USB_WLAN_DP

1

20

36

38

32

30

11

13

47

33

31

22

25

23

49

19

8

17

10

12

14

16

42

46

44

G2G1

7

3

5

51

9

6

52

50

48

43

41

40

4

39

37

35

34

29

2827

26

21

2

18

15

45

24

2

1

3

4

36

5

2

1

2 1

21

2 1

21

IN

W_DISABLE#

WAKE#

USB_D-

USB_D+

SMB_DATA

SMB_CLK

REFCLK-

REFCLK+

PWR_LED#

PETP0

PETN0

PERP0

PERN0

PERST#

NUM_LED#

LPC_PCI_CLK

LPC_FRAME#

LPC_DEBUG_RST#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LED_WWAN#

LED_WPAN#

LED_WLAN#

GG

CLKREQ#

CH_DATA

CH_CLK

CAPS_LED#

GND

1.5V

3.3V

GND

1.5V

Reserved

GND

Reserved

GND

1.5VGND

GND

3.3V

GND

+V3AL

+3.3VAUX

G

DS

IN

S

PMOS_4D1S

G

D

IN

BI

IN

BI

IN

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 1400~1499(3G)

CLOSE TO CONN SIDE

6828

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

BELLW_80003_4021_52P

P3V3S

0.01UF_50V_2

0.01UF_50V_2 TP24

SSM3K7002BFU

NXP_IP4223CZ6_SOT457_6P_DY

P1V5S

22UF_6.3V_5

0.1UF_16V_2

22UF_6.3V_5

0.1UF_16V_2

TP24

P3V3S

0.1UF_16V_2

4.7UF_6.3V_3

TAI_PMPAT5_06GLBS7NI4H1_6P

Block Diagram

CS

A3

TP24

CN1400

C1407

C1408

C1406

C1405

Q1400

C1412

C1411

C1410

TP1402

TP1401

TP1400

C1404

C1403

U1400

CN1401

C1400C1401C1402

47B3

51B2

57A6

52D6

21E3 27C3

27C7 51A8

28A4

28A6

28A4 28B6

51B2

28D3

28A4 28D3

28B6 28D3

28C3

SATA_MINICARD_C_TX_DP

SATA_MINICARD_C_TX_DN

3G_OFF#

USB_3G_DN

USB_3G_DP

BUF_PLT_RST#

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RST

SATA_MINICARD_C_RX_DN

SATA_MINICARD_C_RX_DP

UIM_CLK

UIM_RST

UIM_PWR

SATA_MINICARD_TX_DN

SATA_MINICARD_TX_DP 3G_ON#

UIM_DATA

UIM_PWR

SATA_MINICARD_RX_DN

SATA_MINICARD_RX_DP

1

20

36

38

32

30

11

13

47

33

31

22

25

23

49

19

8

17

10

12

14

16

42

46

44

G2G1

7

3

5

51

9

6

52

50

48

43

41

40

4

39

37

35

34

29

2827

26

21

2

18

15

45

24

21

2

1

3

2 1

1

2 1

4

6

3

1

52

P6

P1

P2

P7

P5

G2 G1

P3

2 1

OUT

W_DISABLE#

WAKE#

USB_D-

USB_D+

SMB_DATA

SMB_CLK

REFCLK-

REFCLK+

PWR_LED#

PETP0

PETN0

PERP0

PERN0

PERST#

NUM_LED#

LPC_PCI_CLK

LPC_FRAME#

LPC_DEBUG_RST#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LED_WWAN#

LED_WPAN#

LED_WLAN#

GG

CLKREQ#

CH_DATA

CH_CLK

CAPS_LED#

GND

1.5V

3.3V

GND

1.5V

Reserved

GND

Reserved

GND

1.5VGND

GND

3.3V

GND

+V3AL

+3.3VAUX

BI

OUT

BI

G

DS

IN

VIO

VBUSGND

VIO

VIO VIO

BI BI

IN

G

I_O

VPP

VCC

RST

CLK

G

GND

IN

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

PLACE CLOSE TO CONNECTOR(<100MILS)

REFERENCE 1750~1799(ODD)

SATA HDD

REFERENCE 1700~1749(HDD)

40MIL

PLACE CLOSE TO CONNECTOR(<100MILS)

SATA ODD

6829

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SSM3K7002BFU_DY

10K_5%_2_DY

0.01UF_50V_2

SANTA_194911_1_22P

22UF_6.3V_5

0.1UF_16V_2

P5V0S

22UF_6.3V_5

A3 CS

Block Diagram

0.1UF_16V_2

0.01UF_50V_2

SYN_127382FR013G212ZR_13P

P5V0S

TPC6111_DY

0_5%_6

22UF_6.3V_5

CSC0402_DY

P3V3S

100K_5%_2_DY

1M_5%_2_DY

R1750

Q1750

R1752

R1751

C1758

R1754

Q1751

CN1750

CN1700

C1754

C1702

C1755

C1703

C1706

C1756

C1757

C1753

C1752

C1751

C1750

C1701

C1700

C1705

C1704

47C3

52D2

47B3

52B6 52D7

51C7

47B3

51B6

SATA_ODD_PWREN

SATA_HDD_RX_C_DP

SATA_HDD_RX_C_DN

SATA_HDD_TX_C_DN

SATA_HDD_TX_C_DP

SATA_HDD_RX_DP

SATA_HDD_RX_DN

SATA_HDD_TX_DN

SATA_HDD_TX_DP

SATA_ODD_TX_DP

SATA_ODD_DA#

SATA_ODD_PRSNT#

SATA_ODD_RX_C_DP

SATA_ODD_RX_C_DN

SATA_ODD_TX_C_DN

SATA_ODD_TX_C_DP

SATA_ODD_TX_DN

SATA_ODD_RX_DN

SATA_ODD_RX_DP

2 1

2

1

3 2 1

21

2 1

4

36

5

2

1

S7

S6

S5

S4

S3

S2

S1

P6

P5

P4

P3

P2

P1

G2

G1

G2

G1

9

8

7

6

5

4

3

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

2 1

21

OUT

G

DS

S

PMOS_4D1S

G

D

GND

A+

A-

GND

B-

B+

GND

DP

+5V

MD

GND

G

G2

G1

V12

GND

RESERVED

GND

V5

GND

V3.3

GND

B+

B-

GND

A-

A+

GND

OUT

IN

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 2000~2099(USB)

6830

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

POWERPAD_2_0610

1UF_6.3V_2

P5V0A_USB3

ACES_50224_0040N_001_4P

22UF_6.3V_5

RSC_0402_DY

RICH_RT9711APF_MSOP_8P

P5V0A

22UF_6.3V_5_DY

CSC0402_DY P3V3AL

A3 CS

Block Diagram

10K_5%_2

P5V0A_USB3

0.1UF_16V_2

CN2002

C2002

PAD2000

R2001

R2000

C2003

C2000 C2001

C2004

U2000

51C2 66C6

21D3

P5V0A_USB_PW1

USB_P2_DP

USB_P2_DN

USB_OC#_2

SB_USB_2

G2

G1

4

3

2

1

2 1

21

2 1

8

7

6

54

3

2

1

BI

G1

1

2

3

4 G2

VOUT

FLG#

EN_EN#

VIN

GND

OUT

IN

1 2

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 2400~2499(USB3.0)

TRACE WIDTH>20MILS

6831

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P1V05_USB3 P3V3_USB30_AVDD

0.1UF_16V_2

P3V3_USB3

0.1UF_16V_2

0.01UF_50V_2

10UF_6.3V_3

0.1UF_16V_2

SSM3K7002BFU

220K_5%_2

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

P3V3A

10K_5%_2

CSC0402_DY

0.1UF_16V_2

P3V3_USB3

Block Diagram

CS

A3

12PF_50V_2

ANPEC_APL5930KAI_TRG_SOP_8P 10K_1%_2

31.6K_1%_2

P3V3_USB3

10K_5%_2

DIODE-BAT54-TAP-PHP

0.1UF_16V_2

P3V3_USB3

10K_5%_2

0.1UF_16V_2

0.01UF_50V_2

P3V3_USB30_AVDD

0.1UF_16V_2

10UF_6.3V_3

BLM21PG600SN1D_3A

47K_5%_2

MAC_MX25L5121EMC_20G_SOP_8P

P3V3_USB3

P5V0A

22UF_6.3V_5

RENESAS_UPD720202K8_BAA_A_QFN_48P

1.6K_1%_2

1UF_6.3V_2

P3V3_USB3

10K_5%_2

P3V3_USB3

10K_5%_2

12PF_50V_2

24MHZ

0.01UF_50V_2

P1V05_USB3

0.01UF_50V_2

150PF_50V_2

22UF_6.3V_5

POWERPAD1X1M

P1V05_USB3

0.01UF_50V_2

P1V5

0_5%_2

10K_5%_2

C2471

C2473

C2472

Q2402

Q2403

R4955

C2425

C2424

C2423

C2410

C2409

C2414

C2408

C2401

C2400

C2480

C2435

C2406

R2405

U2400

R4754

C2416

C2415

C2470

C2405

C2404

C2403

C2402

R2416

R2415

PAD2400

U2403

C2438

R2423

C2433

R2422

C2434

R2424

R2480 R2481

U2480

C2417

C2422

C2421

C2420

C2418

C2419

C2411

D2400

R2406

X2400

C2412C2413

L2400

R2400

R2427

21D6 31A5

32B8

48B7

31B8 48B7 22B5 27C7 49A5 49B3

48D8

51B6 31C6

48D8

41C7 51A7

31B6

31C7

51B6

48B7

31B6

31C6

31D4 21D6

33B5

33C5

31A6

33B5

31B6

48D8

31B6

32A8

32D7

32B8

32D7

31A6

31A8

36B2

31A8

48B7

31C7

33C5

USB2_IC_TX2_DN

USB30_PWR_EN

USB2_IC_TX2_DP

USB30_PWR_EN

USB3_SMI#

CLKREQ_USB3#

PCIE_USB3_TX_DP

PLT_RST#

PCIE_WAKE#

CLKREQ_IC_USB3#

CLK_PCIE_USB3_DN

PCIE_USB3_RX_DP

PCIE_USB3_RX_DN

PCIE_USB3_TX_DN

PCIE_USB3_RX_C_DP

USB3_SMI#

PCIE_USB3_RX_C_DN

USB3_SCLK

USB3_SI

USB3_IC_TX2_DP

USB3_IC_RX2_DN

USB3_IC_RX1_DN

USB2_IC_TX1_DN

USB2_IC_TX1_DP

USB3_IC_RX1_DP

USB3_IC_TX1_DP

USB3_CS#

USB3_XT1

USB3_IC_TX1_DN

USB3_SO

USB3_SI

USB3_CS#

USB3_IC_TX2_DN

CLKREQ_IC_USB3#

CLK_PCIE_USB3_DP

USB3_SCLK

CLKREQ_USB3#

USB3_SO

USB3_XT2

USB3_IC_RX2_DP

2 1

2

1

3

S

G

D

21

2 1

21

2 1

21

23

24

34

43

12

22

42

6

9

21

30

33

39

37

28

38

29

40

31

41

32

44

35

45

36

13

16

15

14

46

26

18

20

11

48

4

5

7

8

47

10

1

2

17

19

27

49

3

25

2 1

21

4

3

9

5

6

7

1

2

8

2 1

21

2 1

3

8

2

5

6

7

4

1

2 1

2

13

21

2 1

21

BI

NC

IN

OUT

IN

OUT

IN

BI

OUT

IN

G

DS

G

SD

OUT

IN

PERXN

PETXP

XT2

XT1

PONRSTB

PERSTB

PEWAKEB

PECREQB

AVDD33

PECLKP

PECLKN

PETXN

PERXP

SPISCK

SPICSB

IC(L)

VDD33

VDD10

VDD33

GND

SPISI

SPISO

VDD10

SMIB

RREF

U3TXDP2

U3TXDN2

U3RXDP2

U3RXDN2

U2DP1

U2DM1

U3TXDP1

U3TXDN1

U3RXDP1

U3RXDN1

U2DP2

U2DM2

OCI2B

OCI1B

PPON2

PPON1

OUT

BI

1 2

VIN

VCNTL

POK

EN

VIN

VOUT

FB

GND

IN

BI

OUT

IN

WP#

VCC

SO

SI

SCLK

NC

GND

CS#

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

USB3.0

USB3.0 FROM PCH

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

CURRENT LIMIT 2.5A

REFERENCE 2400~2499(USB3.0)

USB 3.0 CONNECTOR

6832

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

LOTES_AUSB0026_P001_9P

WCM_2012_900T

10K_5%_2

P5V0A_USB1

100K_5%_2_DY

0_5%_2

47UF_6.3V_5

20K_5%_2 0_5%_2_DY

P3V3AL

TI_TPS2540A_QFN_16P

1000PF_50V_2

P5V0A

0_5%_2

GMT_G547E1P81U_MSOP_8P

P5V0A_USB1

0_5%_2

0.1UF_16V_2

0_5%_2

0.1UF_16V_2

0_5%_2

22UF_6.3V_5

100UF_6.3V

P3V3AL

10K_5%_2

Block Diagram

CS

A3

0_5%_2

P5V0A_USB1

0.1UF_16V_2

P5V0A

0_5%_2

CN2401

R2436R2435

U2401

R2458

R2504

R2503

C2447

C2448

C2441

C2440

C2427

C2426

C2429

R2456

R2457

R2454

R2455

R2408

R2447

R2446

R2433

R2432

R2431

R2430

L2404

C2442

R2434

C2432 C2428

U2402

31B2

32D5

51C2

21C3

21D6

32C8

51C2

31B2

32C8

31B2 32A8

32B8

51C2

21D6

21C3

32C8

51C2

32A8

32B8

32C7

31B2

51C6

31B2

32B7

31B2

51C6

21D6

32D5

32C8

32A6

32A8

32C1

32C3

33C6

33D8

33C6

33D8

21D6

USB3_SSTX1_DP

USB3_SSTX1_DN

USB3_SSRX1_DP

USB3_SSRX1_DN

USB_P0_L_DP

USB_P0_L_DN

USB_P0_R_DP

USB_P0_R_DN

USB_IC_DN

USB2_IC_TX1_DP

USB_IC_DP

USB_OC#_1

SB_USB_1

USB2_IC_TX1_DN

USB_P0_DP

USB_IC_DN

USB_IC_DP

USB3_PCH_TX1_DP

USB3_PCH_TX1_DN

USB3_IC_TX1_DP

USB3_IC_TX1_DN USB3_SSTX1_DN

USB3_SSRX1_DN

USB3_SSRX1_DP

USB3_PCH_RX1_DN

USB3_PCH_RX1_DP

USB3_SSTX1_DP

USB3_IC_RX1_DP

USB3_IC_RX1_DN

SB_USB_1

EC_CTL1

EC_CTL2

EC_CTL3

EC_ILIM_SEL

USB2_IC_TX1_DP

USB_P0_DN

USB2_IC_TX1_DN

USB_P0_DN

G4

G3

G2

G1

9

8

7

6

5

4

3

2

1

2 1

17

12

9

1

4

15

16

14

13

5

310

211

8

7

6

21

2 1

21

2 1

21

34

2 1

21

2 1

6

7

8

5

3

2

1

4

IN

BI

OUT

IN

EN

OC#

OUT

IN

GND

G

SSTX+

SSTX-

GND

SSRX+

SSRX-

PGND

D+

D-

VBUS

PWPD

OUT

NC

IN

ILIM_SEL

ILIM1

ILIM0

GND

FAULT#

EN

DP_OUT DP_IN

DM_OUT DM_IN

CTL3

CTL2

CTL1

BI

+

BI

OUT

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CURRENT LIMIT 2.5A

REFERENCE 2400~2499(USB3.0)

USB 3.0 CONNECTOR

USB3.0

USB3.0 FROM PCH

USB3.0 FROM CONTROLLLER

USB2.0 FROM PCONTROLLER

USB2.0 FROM PCH

USB3.0 FROM PCH

USB3.0 FROM CONTROLLLER

6833

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

LOTES_AUSB0026_P001_9P

0_5%_2

22UF_6.3V_5_DY 0.1UF_16V_2 1000PF_50V_2

0_5%_2

A3 CS

Block Diagram

0_5%_2

WCM_2012_900T

P5V0A_USB2

P5V0A

GMT_G547E1P81U_MSOP_8P

100UF_6.3V

P5V0A_USB2

P3V3AL

10K_5%_2

47UF_6.3V_5

0.1UF_16V_2

CN2402

U2404

R2410

C2449

C2454

C2445

C2446

C2444

C2443

C2452

R2453

R2452

R2451

R2450

L2405

C2453

C2451

R2437

R2438

R2440

R2439

51C6

51C2

31C2

33C3

33B3

33B2

33B3

33B2

51C6

21C3

21D6

33C3

32C1 32A6

32C3 32A8

USB_P1_L_DN

USB_P1_L_DP

USB3_SSRX2_DN

USB3_SSRX2_DP

USB3_SSTX2_DN

USB3_SSTX2_DP

USB_P1_DP

USB_P1_DN

USB2_IC_TX2_DP

USB2_IC_TX2_DN

USB3_IC_TX2_DN

USB3_SSRX2_DP

USB3_SSRX2_DN

USB3_IC_TX2_DP USB3_SSTX2_DP

USB3_SSTX2_DN

USB3_PCH_RX2_DP

USB3_PCH_RX2_DN

USB3_IC_RX2_DP

USB3_IC_RX2_DN

USB_P1_R_DP

USB_P1_R_DN

USB_OC#_1

SB_USB_1

USB3_PCH_TX2_DN

USB3_PCH_TX2_DP

G4

G3

G2

G1

9

8

7

6

5

4

3

2

1

6

7

8

5

3

2

1

4

2 1

21

2 1

21

21 21

34

2 1

21

BI

G

SSTX+

SSTX-

GND

SSRX+

SSRX-

PGND

D+

D-

VBUS

EN

OC#

OUT

IN

GND

OUT

+

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFFERENCE 3000~3049(LCM)

PM:4.7K

GM:2.2K

(60130B4720ZT)

PM: 10K

GM:OPEN

6834

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

PVBAT_LCD

100_5%_2

10K_5%_2

100_5%_2

1000PF_50V_2

680PF_50V_2

10UF_6.3V_3

POWERPAD_2_0610

100_5%_2

2.2K_5%_2

0_5%_1

100_5%_2

100K_5%_2 CSC0402_DY

4.7UF_25V_5

0.1UF_16V_2

Block Diagram

CS

A3

ACES_50203_03001_001_30P

PVBAT

POWERPAD_2_0610

0.1UF_25V_3

0.1UF_16V_2

P3V3S

47K_5%_2

0.01UF_50V_2

0.1UF_16V_2

P3V3S

SSM3K7002BFU

470K_5%_2

P3V3S

2.2K_5%_2

SSM3K7002BFU

0_5%_1

P3V3S

DIODES_DMP2305U_SOT23_3P

C3002

R3018

R3017

R3016

R3015

R3014

R3034

R3033

R3032

R3031

R3030

R3029

R3028

R3027

R3026

R3025

R3024

R3023

R3021

R3022

R3020

R3019

R3013

R3012

R3011

R3035

Q3002

Q3001

Q3000

R3006

CN3000

C3006

R3001

R3000

C3000

C3003

R3004

C3001

PAD3003

R3002

R3005

C3004

C3007

R3003

R3009

R3010

C3011

C3010

C3009

PAD3001

24A6

34B3

34C3

50D7

34C3

34C3 57A6

57A6

50C6

34A6

50C6

51B2

50C6

57A6

57B6

50C7

50D7

56D6

50D7

21E6

57B6

MIC_IN_CLK

MIC_IN_DATA

USB_CAM_DN

MIC_IN_DATA_R

P3V3S_MOS_LCM P3V3S_LCM

LCM_VDDEN

LVDS_DDCCLKPCH_LVDS_DDCCLK

PCH_LVDS_DDCDATA

VGA_LVDS_DDCDATA

VGA_LVDS_DDCCLK

VGA_LVDS_TXDL1_DP

VGA_LVDS_TXDL0_DP

PCH_LVDS_TXCL_DP

VGA_LVDS_TXDL0_DN

PCH_LVDS_TXDL1_DN

PCH_LVDS_TXDL0_DP

PCH_LVDS_TXCL_DN

PCH_LVDS_TXDL2_DN

PCH_LVDS_TXDL2_DP

PCH_LVDS_TXDL1_DP

PCH_LVDS_TXDL0_DN

LVDS_TXCL_DP

LVDS_TXCL_DN

LVDS_TXDL2_DP

LVDS_TXDL2_DN

LVDS_TXDL1_DP

LVDS_TXDL1_DN

PCH_LCM_VDDEN

VGA_LCM_VDDEN

LVDS_TXDL0_DP

LVDS_TXDL0_DN

LVDS_TXDL0_DP

LVDS_TXDL1_DP

LVDS_TXDL2_DN

LVDS_TXCL_DN

LVDS_TXDL1_DN

LVDS_TXCL_DP

LVDS_TXDL2_DP

INV_PWM_3_R

EC_BKLTEN_R

USB_CAM_DP

LVDS_DDCDATA

EC_BKLTEN

PCH_INV_PWM_3

VGA_INV_PWM_3

VGA_LVDS_TXCL_DP

VGA_LVDS_TXCL_DN

VGA_LVDS_TXDL2_DP

VGA_LVDS_TXDL2_DN

PCH_LCM_VDDEN#

VGA_LVDS_TXDL1_DN

2 1

21

2 1

2

1

3

2

1

3

S

G

D

2 1

G2

G1

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

2 1

21

2 1

21

2 1

21

2 1

21

2 1

21

IN

BI

IN

G

DS

G

DS

G

SD

BI

1 2

G

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

1 2

IN

BI

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

(60130B2020ZT)

GM:2.2K

(60130B1030ZT)

PM:10K

GM:2.2K

PM:2K

REFERENCE 3050~3099(CRT)

RESERVE CAP FOR EMI

6835

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SUYIN_070546HR015M25KZR_15P

P5V0S_CRTVDD

0.22UF_6.3V_2

P5V0S_CRTVDD

2.2K_5%_2

0_5%_1

P3V3S

30_5%_2

2.2K_5%_2

P3V3S

0_5%_1

0.22UF_6.3V_2

P5V0S

0.1UF_16V_2_DY

A3 CS

Block Diagram

TP24

0.1UF_16V_2_DY

100_5%_2

2.2K_5%_2

P5V0S

SBR3U40P1

SMD1812P110TF

TI_TPD7S019_15DBQR_SSOP_16P

15PF_50V_2

120NH,5%

150_1%_2

15PF_50V_2

2.2K_5%_2

CN3051

R3077

R3076

R3070

R3071

R3072

R3073

R3074

R3075

R3069

R3068

R3065

R3064

R3066

R3067

FUSE3050

D3050

C3052

C3054C3053

R3050 R3051

R3052

R3053 TP3051

TP3050

R3063

R3062

R3061R3060

C3057

C3055

C3056

U3050

C3051

C3050

R3056

R3055

R3054

L3050

L3051

L3052

35D4 35A7

35D4

56D3 56F7

35D4

35A3

56A3

50A6

56A3

35A4

50A6

35A4

56D3 56E2

50B7

35C3

35B4

35A4

35C3

35D4

35C3

35C5

35C3

35A3

35C3

35D4 35A7

35A7

35A3

35C3

35A7

CRTB_L

CRTG_L

CRT_DDCCLK_R_OUT

CRT_DDCDATA_R_OUT

CRTR_L

VGA_CRT_VSYNC

PCH_CRT_VSYNC

CRT_DDCDATA_OUT

CRT_HSYNC_R_OUT

CRT_VSYNC_R_OUT

CRT_HSYNC

CRT_VSYNC

CRTB

CRTG

CRTR

PCH_CRTB

CRT_DDCCLK_OUT

VGA_CRT_DDCCLK

VGA_CRT_HSYNC

PCH_CRT_DDCCLK

PCH_CRT_DDCDATA

VGA_CRT_DDCDATA

PCH_CRT_HSYNC

CRT_DDCCLK

CRT_DDCDATA

CRT_VSYNC

CRT_HSYNC

CRT_DDCDATA

CRT_DDCCLK

CRT_HSYNC_OUT

CRT_VSYNC_OUT

CRTG_L

CRTB_L

CRTR_L

CRT_VSYNC_R_OUT

CRT_HSYNC_R_OUT

P5V0S_CRT2

P5V0S_CRT1

CRTR_L

CRTG_L

CRTB_L

VGA_CRTR

VGA_CRTG

VGA_CRTB

PCH_CRTR

PCH_CRTG

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

G2

G1

9

8

7

6

5

4

3

2

15

14

13

12

11

10

1

21

21 21

2 1

21

1

21

2 1

1 16

15

98

7

6

5

4

3

2

14

13

12

11

10

2 1

21

IN

BI

IN

VCC-SYNC SYNC_OUT2

SYNC_IN2

DDC_OUT1BYP

VCC-DCC

GND

VIDEO_3

VIDEO_2

VIDEO_1

VCC-VIDEO

SYNC_OUT1

SYNC_IN1

DCC_OUT2

DDC_IN2

DDC_IN1

OUT

G2

G1

9

8

7

6

5

4

3

2

15

14

13

12

11

10

1

IN

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

(60130B1030ZT)

REFERENCE 3150~3199(HDMI)

GM: 2.2K

PM:10K

40MIL

CLOSE TO CONNECTOR

PLACE CLOSE TO CONNECTOR

(60130B1030ZT)

PM:10K

GM: 2.2K

PM:499_5%

GM:680_5%

(6013A0076801)

6836

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

680_5%_2

0.1UF_6.3V_1

SYN_100042GR019M26DZL_19P

SMD1812P110TF

2.2K_5%_2

0_5%_2

0_5%_1

SSM3K17FU

P3V3S

0_5%_2

P5V0AL

SBR3U40P1

0_5%_2

1K_5%_2

470K_5%_2 22PF_50V_2_DY

TP24

0_5%_2

Block Diagram

CS

A3

680_5%_2

2.2K_5%_2

DIODE-BAT54-TAP-PHP

680_5%_2

P3V3S

TC7SZ08FU

P3V3S

SSM3K17FU

2.2K_5%_2

100K_5%_2

P3V3S

0.1UF_6.3V_1

100PF_50V_2

0_5%_1

680_5%_2

SSM3K7002BFU

2.2K_5%_2

CN3150

R3180

R3181

C3156

C3154

C3152

C3157

C3155

C3153

C3159

C3158

R3177

R3176

R3175

R3174

R3179R3178

C3161

C3160

C3163

C3165

C3167

C3164

C3162

C3166

Q3152

D3150

C3151

TP3151

R3169

R3168

R3167

R3166

R3173

R3172

R3171

R3170

R3152 R3153

Q3150

Q3151

R3159

R3157

R3158

R3160

R3161

R3162

R3163

R3164

R3165

U3150

C3150

D3155

FUSE3150

R3154

R3150

36A2

56F3

37D6

56B3

50B3

36D6

37C3 36C3

36C3 37D3

36A2 36D5

36C6 37D3

36C6 37C3

36A2 36A7

36B7

36A2

37C1

36A2 36A7

36A2

36D5

36A2 36A7

36A2 36C5

36A2 36D5

37B1 21D6

31C6 41C7 51A7

36D5

36C5

36A7

36B7

36A7

36B7

36A7

36C8

56F3

50B3

56C5

36A2 36B7

36B7

36A2

36C5

HDMI_TX1_C_DN

PCH_HDMI_TX2_DN

P5V0AL_HDMI_VDD2

HDMI_CEC

HPDET_IC

HDMI_TX1_R_DN

HDMI_TX0_R_DP

VGA_HDMI_DDCCLK

VGA_HDMI_DDCDATA

PCH_HDMI_DDCCLK

PCH_HDMI_DDCDATA

HDMI_DDCCLK

HDMI_DDCDATA

HDMI_CN_DDCCLK

HDMI_CN_DDCDATA

HDMI_CN_DDCCLK

P5V0AL_HDMI_VDD1

HDMI_CN_DDCDATA

HDMI_TXC_R_DN

HDMI_TX1_C_DP

HDMI_TXC_R_DP

HDMI_TX0_R_DN

HDMI_TX1_C_DN

HDMI_TX2_R_DP

HDMI_TX2_R_DN

HDMI_TX1_R_DP

HDMI_TX2_C_DP

HDMI_TX2_C_DN

HDMI_TX1_C_DP

HDMI_TX2_C_DN

HDMI_TXC_C_DP

HDMI_TX2_C_DP

HPDET

HDMI_HPD_EC

PLT_RST#

HDMI_TX0_C_DP

HDMI_TXC_C_DP

HDMI_TX2_C_DN

HDMI_TX1_C_DP

HDMI_TX1_C_DN

HDMI_TX2_C_DP

VGA_HDMI_TX1_DN

VGA_HDMI_TX2_DP

VGA_HDMI_TX2_DN

HDMI_TX0_C_DN

HDMI_TXC_C_DN

PCH_HDMI_TX2_DP

PCH_HDMI_TX1_DN

PCH_HDMI_TX1_DP

VGA_HDMI_TXC_DP

HDMI_TX0_C_DP

VGA_HDMI_TXC_DN

VGA_HDMI_TX0_DP

VGA_HDMI_TX0_DN

VGA_HDMI_TX1_DP

PCH_HDMI_TX0_DN

PCH_HDMI_TX0_DP

PCH_HDMI_TXC_DN

PCH_HDMI_TXC_DP

PCH_HPDET

HDMI_TX0_C_DP

HDMI_TXC_C_DP

HDMI_TX0_C_DN

HDMI_TXC_C_DN

VGA_HPDET

HDMI_DDCDATA

HDMI_DDCCLK

HDMI_TXC_C_DN

HDMI_TX0_C_DN

G4

G3

G2

G1

9

8

7

6

5

4

3

2

19

18

17

16

15

14

13

12

11

10

1

21

2 1

21

2

1

3

2

13

2 1

1

21

2 1

S

G

D

S

G

D

21

2 1

5

4

3

2

1

2 1

2 1 21

21

2 1

IN

IN OUT

OUT

G

DS

IN

NC

BI

IN

BI

BI BI

G

DS

G

DS

IN

OUT

IN

+-

G4

G3

G2

G1

TMDS Data0-

TMDS Data0 Shield

TMDS Data0+

TMDS Data1-

TMDS Data1 Shield

TMDS Data1+

TMDS Data2-

TMDS Data2 Shield

Hot Plug Detect

+5V Power

DDC/CEC GND

DDC Data

DDC Clock

Reserved

CEC

TMDS Clock-

TMDS Clock Shield

TMDS Clock+

TMDS Data2+

IN

OUT

IN

OUT

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6837

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SSM3K17FU

P3V3AL

SSM3K17FU

4.02K_1%_2

SSM3K7002BFU

74LVC1G14GV

22K_5%_2

P3V3AL

A3 CS

Block Diagram

P3V3AL

RSC_0402_DY

P3V3AL

4.02K_1%_2

68_5%_2

P3V3AL

DIODE-BAT54-TAP-PHP

27K_5%_2

100K_5%_2

4.7K_5%_2

RENESAS_R5F211B4D61SP_LSSOP_20P

47K_5%_2

P3V3AL

33_5%_2

1UF_6.3V_2

0.1UF_16V_2

PHP_74LVC1G17_SOT753_5P

0.1UF_16V_2

Q3203

C3202

C3200

U3203

R3212

R3211

R3205

R3206

D3200

R3204

R3214

R3213 R3210

R3202

U3200

R3227

C3205

R3208

R3209

R3200 Q3200

R3201 Q3201

U3202

36C3

56D8 56C8

37B3 37B6

36C6 36C3 37B3

36C4

21D6

37B6

21D2

5A7

37A8

37C5

21D2

5A7

37D5

36C6 36C3

37C6

37D8

37A6

37B6 37B6

21D3 21D3

36B2

HDMI_CN_DDCCLK

HDMI_CN_DDCDATA

HDMI_CEC

CEC_OUT

HDMI_DDCCLK_CEC

HPDET_IC

HDMI_HPD_EC

CEC_IN

CEC_XOUT

HDMI_DDCDATA_CEC

HDMI_DDCCLK_CEC

CEC_OUT

CEC_IN

CEC_XIN

CEC_XOUT CEC_XIN

HDMI_DDCDATA_CEC

EC_SMB2_CLK EC_SMB2_DATA

2

1

3

2 1

5

4

1

2

3

2 1

21

2

132 1

21

2 1

2 1 5

4

1

2

3

21

2 1

S

G

D

2 1

S

G

D

4

6

5

7

3

9

16

2

1 20

19

10 11

12

13

14

15

17

18

8

INOUT

OUT

IN

BI

IN

OUT

BI

OUT

IN

G

DS

NC

+

-

NC

-

NC

+

G

DS

G

DS

XOUT-P4_7

XIN-P4_6

VSS-AVSS

VCC-AVCC

RESET#

P4_5-INT0#-RXD1

P4_2-VREF

P3_7-CNTR0#-SSO-TXD1

P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1

P3_3-TCIN-INT3#-SSI00-CMP1_0

P1_7-CNTR00-INT10# P1_6-CLK0-SSI01

P1_5-RXD0-CNTR01-INT11#

P1_4-TXD0

P1_3-KI3#-AN11-TZOUT

P1_2-KI2#-AN10-CMP0_2

P1_1-KI1#-AN9-CMP0_1

P1_0-KI0#-AN8-CMP0_0

MODE

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

CHA

IF SA0_DIM0=0 , SA1_DIM0=0

SO-DIMMA TS ADDRESS IS 0X30

SO-DIMMA SPD ADDRESS IS 0XA0

NOTE:

1.5A

NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

SO-DIMMA TS ADDRESS IS 0X32

SO-DIMMA SPD ADDRESS IS 0XA2

IF SA0_DIM0=1 , SA1_DIM0=0

REFERENCE 4100~4299(DDR)

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

6838

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

BELLW_80001_1021_204P

Block Diagram

CS

A3

P3V3S

0.1UF_16V_2

0

1

3

2

4

6

5

7

8

9

11

10

12

15

18

19

20

21

22

23

24

25

26

27

28

29

32

34

33

35

36

37

38

39

40

42

44

43

46

45

47

48

49

50

52

51

53

54

57

56

58

59

62

63

10K_5%_2_DY

10K_5%_2

10K_5%_2_DY

10K_5%_2

13

14

1UF_6.3V_2

10K_5%_2

55

P3V3S

10UF_6.3V_3 10UF_6.3V_3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3

1UF_6.3V_21UF_6.3V_21UF_6.3V_21UF_6.3V_2

P0V75S

0.1UF_16V_2

30

10UF_6.3V_3

60

61

P0V75M_VREF

2.2UF_6.3V_3 0.1UF_16V_2

2.2UF_6.3V_3

P3V3S

41

P1V5

330UF_2.5V_DY

16

31

17

CN4100

C4100

R4103

R4101

R4102

R4100

R4104

C4119 C4120 C4121 C4122

C4117 C4118

C4150 C4116

C4114 C4115

C4102C4101 C4103 C4104

C4110 C4108C4109

C4105 C4107C4106

43D8

38C8

43B5

43A4

43A8

43C5

43A8

43D4

43A8

43B5

43D4

43A8

48A8 39C8

38A6

43C5

48A8 39C8

43C5

41A5 39C3

39C3 38B5

43B5

39C3 38C3

43C5

DDR3_DRAMRST#

PM_EXTTS#1_R

M_A_A<3>

M_A_A<2>

M_A_A<1>

M_A_A<0>

M_A_A<15..0>

M_A_DQ<63>

M_A_DQ<62>

M_A_DQS7_DN

M_A_DQS6_DN

M_A_DQS5_DN

M_A_DQS4_DN

M_A_DQS3_DN

M_A_DQS2_DN

M_A_DQS0_DN

M_A_DQS0_DP

M_ODT1

M_ODT0

PCH_3S_SMCLK

SA1_DIM0

SA0_DIM0

M_A_WE#

M_A_RAS#

M_A_CAS#

M_CKE1

M_CKE0

M_CLK_DDR1_DN

M_CLK_DDR0_DP

M_CS#1

M_CS#0

M_A_BS2

M_A_BS1

M_A_BS0

M_A_A<15>

M_A_A<14>

M_A_A<13>

M_A_A<12>

M_A_A<11>

M_A_A<10>

M_A_A<9>

M_A_A<8>

M_A_A<7>

M_A_A<6>

M_A_A<5>

M_A_A<4>

M_A_DQ<61>

M_A_DQ<60>

M_A_DQ<59>

M_A_DQ<58>

M_A_DQ<57>

M_A_DQ<56>

M_A_DQ<55>

M_A_DQ<54>

M_A_DQ<53>

M_A_DQ<52>

M_A_DQ<51>

M_A_DQ<50>

M_A_DQ<49>

M_A_DQ<48>

M_A_DQ<47>

M_A_DQ<46>

M_A_DQ<45>

M_A_DQ<44>

M_A_DQ<43>

M_A_DQ<42>

M_A_DQ<41>

M_A_DQ<40>

M_A_DQ<39>

M_A_DQ<38>

M_A_DQ<37>

M_A_DQ<36>

M_A_DQ<35>

M_A_DQ<34>

M_A_DQ<33>

M_A_DQ<32>

M_A_DQ<31>

M_A_DQ<30>

M_A_DQ<29>

M_A_DQ<28>

M_A_DQ<27>

M_A_DQ<26>

M_A_DQ<25>

M_A_DQ<24>

M_A_DQ<23>

M_A_DQ<22>

M_A_DQ<21>

M_A_DQ<20>

M_A_DQ<19>

M_A_DQ<18>

M_A_DQ<17>

M_A_DQ<16>

M_A_DQ<15>

M_A_DQ<14>

M_A_DQ<13>

M_A_DQ<12>

M_A_DQ<11>

M_A_DQ<10>

M_A_DQ<9>

M_A_DQ<8>

M_A_DQ<7>

M_A_DQ<6>

M_A_DQ<5>

M_A_DQ<4>

M_A_DQ<3>

M_A_DQ<2>

M_A_DQ<1>

M_A_DQ<0>

M_A_DQ<63..0>

SA0_DIM0

SA1_DIM0

M_A_DQS1_DP

M_A_DQS5_DP

M_A_DQS4_DP

M_A_DQS3_DP

M_A_DQS2_DP

M_A_DQS6_DP

M_A_DQS1_DN

M_A_DQS7_DP

M_CLK_DDR0_DN

M_CLK_DDR1_DP

PCH_3S_SMDATA

PM_EXTTS#1_R

204

20325

20

19

14

196

195

190

13

189

185

184

179

178

173

172

168

167

162

9

161

156

155

151

150

145

144

139

138

134

8

133

128

127

72

71

66

65

61

60

55

3

54

49

48

44

43

38

37

32

31

26

2

1

126

199

99

94

93

88

87

82

81

76

124

123

118

117

112

111

106

105

100

75

30

125

122

77

G2

G1

198

113

200

202

201

197

121

114

110

120

116

186

188

169

171

152

154

135

137

62

64

45

47

27

29

10

12

23

21

18

194

192

182

180

16

193

191

183

181

176

174

166

164

177

175

6

165

163

160

158

148

146

159

157

149

147

4

142

140

132

130

143

141

131

129

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

187

170

153

136

63

46

28

11

74

73

104

102

103

101

115

79

108

109

85

89

86

90

91

92

95

96

78

80

119

83

84

107

97

98

2 1

2 1 2 1

2 1

IN

OUT

IN

OUT

G2

G1

VTT2

VTT1

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VREF_CA

VREF_DQ

RESET#

EVENT#

NCTEST

NC2

NC1

VDDSPD

VDD18

VDD17

VDD16

VDD15

VDD14

VDD13

VDD12

VDD11

VDD10

VDD9

VDD8

VDD7

VDD6

VDD5

VDD4

VDD3

VDD2

VDD1

DQS7#

DQS6#

DQS5#

DQS4#

DQS3#

DQS2#

DQS1#

DQS0#

DQS7

DQS6

DQS5

DQS4

DQS3

DQS2

DQS1

DQS0

DM7

DM6

DM5

DM4

DM3

DM2

DM1

DM0

ODT1

ODT0

SDA

SCL

SA1

SA0

WE#

RAS#

CAS#

CKE1

CKE0

CK1#

CK1

CK0#

CK0

S1#

S0#

BA2

BA1

BA0

A15

A14

A13

A12/BC#

A11

A10/AP

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

IN

+

IN

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

SO-DIMMB SPD ADDRESS IS 0XA4

SO-DIMMB TS ADDRESS IS 0X34

CHB

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

NOTE:

1.5A

REFERENCE 4100~4299(DDR)

6839

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

10K_5%_2_DY

63

10K_5%_2

61

60

59

58

57

56

55

53

54

52

51

49

50

47

46

45

43

44

42

41

40

39

38

34

33

32

31

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

13

14

11

12

10

8

9

7

6

5

3

4

2

1

0

11

10

9

7

6

5

3

2

1

0

0.1UF_16V_2

10UF_6.3V_3

0.1UF_16V_2

10UF_6.3V_3

A3

1UF_6.3V_2

CS

Block Diagram

1UF_6.3V_2

P0V75S

10UF_6.3V_3

35

36

37

4

P3V3S

62

30

1UF_6.3V_2 1UF_6.3V_2

10UF_6.3V_3

48

2.2UF_6.3V_3

P0V75M_VREF

P3V3S

1UF_6.3V_2

10K_5%_2_DY

2.2UF_6.3V_3

1UF_6.3V_2 1UF_6.3V_2

8

12

15

14

13

10UF_6.3V_3

0.1UF_16V_2

10K_5%_2

BELLW_80001_5021_204P

2.2UF_6.3V_3

P1V5

1UF_6.3V_2

BELLW_80001_5021_204P

CN4101

R4108

R4106R4105

R4107

C4145C4144C4143C4142

C4130

C4131

C4129

C4132

C4128

C4133

C4141C4140

C4127C4126C4125

C4137

C4139C4151

C4124

C4138

43B1

43D1

43A1

43B1

48A8 38C8

39C8 39C8

43A4

43D1

43B1

43C1

39A7

39A6

48A8 38C8

43A4

43D4

43B1

41A5 38C3

38C3 38B5

43A4

M_B_DQ<54>

M_B_DQ<53>

M_B_DQ<52>

M_B_DQ<51>

M_B_DQ<50>

M_B_DQ<49>

M_B_DQ<63>

M_B_DQ<62>

M_B_DQ<61>

M_B_DQ<60>

M_B_DQ<59>

M_B_DQ<58>

M_B_DQ<48>

M_B_DQ<46>

M_B_DQ<45>

M_B_DQ<43>

M_B_DQS1_DN

M_B_DQS7_DP

M_B_DQS3_DP

M_CLK_DDR3_DP

M_CLK_DDR2_DN

M_B_A<15..0>

M_B_DQS2_DP

M_B_DQS1_DP

PCH_3S_SMDATA

M_B_DQ<63..0>

M_B_DQS6_DP

M_B_DQS5_DP

M_B_DQS4_DP

SA1_DIM1SA0_DIM1

M_B_A<1>

M_B_A<15>

M_B_A<2>

M_B_A<3>

M_B_A<4>

M_B_A<5>

M_B_A<6>

M_B_BS0

M_B_BS1

M_B_BS2

M_B_CAS#

M_CLK_DDR2_DP

M_CLK_DDR3_DN

M_CKE2

M_CKE3

M_B_DQ<0>

M_B_DQ<1>

M_B_DQ<10>

M_B_DQ<11>

M_B_DQ<12>

M_B_DQ<13>

M_B_DQ<16>

M_B_DQ<17>

M_B_DQ<2>

M_B_DQ<23>

M_B_DQ<24>

M_B_DQ<25>

M_B_DQ<27>

M_B_DQ<28>

M_B_DQ<29>

M_B_DQ<3>

M_B_DQ<30>

M_B_DQ<35>

M_B_DQ<36>

M_B_DQ<37>

M_B_DQ<38>

M_B_DQ<39>

M_B_DQ<4>

M_B_DQ<40>

M_B_DQ<41>

M_B_DQ<42>

M_B_DQ<44>

M_B_DQ<47>

M_B_DQ<5>

M_B_DQ<55>

M_B_DQ<56>

M_B_DQ<57>

M_B_DQ<6>

M_B_DQ<7>

M_B_DQ<8>

M_B_DQ<9>

M_B_DQS0_DN

M_B_DQS3_DN

M_B_DQS4_DN

M_B_DQS5_DN

M_B_DQS6_DN

M_B_DQS7_DN

M_B_DQS0_DP

M_ODT2

M_ODT3

M_B_RAS#

M_CS#2

M_CS#3

SA0_DIM1

SA1_DIM1

PCH_3S_SMCLK

M_B_WE#

M_B_A<0>

M_B_DQ<14>

M_B_DQ<15>

M_B_A<7>

M_B_A<8>

M_B_A<9>

M_B_A<10>

M_B_A<11>

M_B_A<12>

M_B_A<13>

M_B_A<14>

M_B_DQS2_DN

M_B_DQ<34>

M_B_DQ<33>

M_B_DQ<32>

M_B_DQ<31>

M_B_DQ<26>

M_B_DQ<18>

M_B_DQ<19>

M_B_DQ<20>

M_B_DQ<21>

M_B_DQ<22>

PM_EXTTS#1_R

DDR3_DRAMRST#

204

203

25

20

19

14

196

195

190

13

189

185

184

179

178

173

172

168

167

162

9

161

156

155

151

150

145

144

139

138

134

8

133

128

127

72

71

66

65

61

60

55

3

54

49

48

44

43

38

37

32

31

26

2

1

126

199

99

94

93

88

87

82

81

76

124

123

118

117

112

111

106

105

100

75

30

125

122

77

G2

G1

198

113

200

202

201

197

121

114

110

120

116

188

171

154

137

64

47

29

12

186

169

152

135

62

45

27

10

23

21

18

194

192

182

180

16

193

191

183

181

176

174

166

164

177

175

6

165

163

160

158

148

146

159

157

149

147

4

142

140

132

130

143

141

131

129

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

187

170

153

136

63

46

28

11

74

73

104

102

103

101

115

79

108

109

85

89

86

90

91

92

95

96

78

80

119

83

84

107

97

98

2 1 2 1

2 12 1

2 1

2 12 1

2 1

IN

VTT2

VTT1

VSS9

VSS8

VSS7

VSS6

VSS52

VSS51

VSS50

VSS5

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS4

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS3

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS2

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS1

VREF_DQ

VREF_CA

VDDSPD

VDD9

VDD8

VDD7

VDD6

VDD5

VDD4

VDD3

VDD2

VDD18

VDD17

VDD16

VDD15

VDD14

VDD13

VDD12

VDD11

VDD10

VDD1

RESET#

NCTEST

NC2

NC1

G2

G1

EVENT#

WE#

SDA

SCL

SA1

SA0

S1#

S0#

RAS#

ODT1

ODT0

DQS7

DQS6

DQS5

DQS4

DQS3

DQS2

DQS1

DQS0

DQS#7

DQS#6

DQS#5

DQS#4

DQS#3

DQS#2

DQS#1

DQS#0

DQ9

DQ8

DQ7

DQ63

DQ62

DQ61

DQ60

DQ6

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ5

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ4

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ1

DQ0

DM7

DM6

DM5

DM4

DM3

DM2

DM1

DM0

CKE1

CKE0

CK1#

CK1

CK0#

CK0

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12

A11

A10_AP

A1

A0

IN

OUT

IN

BI

IN

OUT

BI

OUT

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

FAN CN

REFERENCE 4300~4349(FAN)

REFERENCE 4411~4449(THERMAL )

6840

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

ENE_P2809A2_SOT23_8P

13.3K_1%_2

100K_1%_NTC 26.7K_1%_2

P5V0AL

100K_1%_NTC 26.7K_1%_2

P5V0AL

ACES_50273_0047N_001_4P

4.7UF_6.3V_3

10K_5%_2

CSC0402_DY

SSM3K7002BFU

CSC0402_DY

100K_5%_2

P5V0AL

0.1UF_16V_2

10K_5%_2

TP30

220pF_50V_2

CSC0402_DY

P5V0S

KC_FBM_11_160808_101_T_2P_DY

POWERPAD_2_0610

0.1UF_16V_2

330_5%_2 MMBT4401

2M_5%_2

A3 CS

Block Diagram

22UF_6.3V_5_DY

P3V3S

R4441

R4447 R4446

CN4300

Q4411R4445

TP4301

TP4300

R4413

R4306

R4300

C4305

C4300

C4441

R4442

U4441

R4444

R4443

C4302

C4412

R4414

Q4412

C4301

C4307

PAD4300

L4300

C4306

56D6

21B6

40B1 15D8

11A4 11C7 49B7

41D5 52C1

15D8 40A8

21B6

THRM_SHUTDWN#

PVCORE_PG

FAN1_PWM

PM_THRMTRIP#

THRM_SHUTDWN#

P5V0S_FAN

FAN_TACH1

21

2 1 2 1

G2

G1

4

3

2

1

2

1

3

2 1

1

21

2 1

1

6

8

5

7

4

3

2

2 1

21

2 1

2 1E C

B

2 1

21

2 1

G

4

3

2

1

G

DS

VCC

TMSNS2

TMSNS1

RHYST2

RHYST1

OT2

OT1

GND

OUT

IN

B

C E

IN

1 2

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT

- TRACE WIDTH = 15MILS AND

LOW IN C6/C7

- MAX LENGTH = 500 MILS

(WORST CASE RESISTANCE)

- MB TRACE IMPEDANCE < 68 MOHMS

REFERENCE 4500~4699(CPU)

PLACE CLOSE TO CPT AND NVRAM CONNECTOR

STUFF R4500/R4501

(DEFAULT)NV_CLE

SANDY BRIDGE ONLY

SET TOVCC WHEN HIGH

SET TOVSS WHEN LOW

SANDY BRIDGE/IVY BRIDGE

STUFF R4502

PROCESS STRAP SETTING

DMI&FDI TERMINATIONVOLTAGE

S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3

6841

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

TP30

LOTES_ACA_ZIF_069_P01_989P

0.047UF_16V_2

51_5%_2

1K_5%_2

56_5%_2

1K_5%_2

1.5K_5%_2

130_1%_2

200_5%_2

P1V5S

1K_5%_2

SSM3K7002BFU

750_1%_2

4.99K_1%_2

0_5%_2

62_5%_2

Block Diagram

CS

A3

2.2K_5%_2

P1V8S

P1V05S

140_1%_2

25.5_1%_2

200_1%_2

1K_5%_2

P1V05S

51_5%_2_DY

51_5%_2

TP30

TP24

P1V05S

2.2K_5%_2_DY

10K_5%_2

CSC0402_DY

1K_5%_2

P1V5P3V3A

CN4500

Q4600

C4620

R4601

R4604

R4602

R4603

R4600

R1418

R4520

R4519

R4517

R4516

TP4509

TP4506

TP4507

TP4508

TP4505

TP4504

TP4503

TP4502

R4514

R4513

R4512

R4510

R4511

R4505

R4506

R4508

R4507

C4500

R4503

R4504

TP4501

TP4500

R4509

R4501

R4502R4500

38C3

52C1

41D8

40A4

52C2

51A7

45D6

45D8

48D3

11B7 21C3

49B7

41D5

48B3

41A5

41B2

49B8

41B2

41C1

21A6 52C2

52B2

49A3

31C6 36B2

39C3

41D2

SM_RCOMP2

SM_RCOMP1

SM_RCOMP0

PM_DRAM_PWRGD_R

H_SNB_IVB#

H_PM_SYNC

PM_THRMTRIP#

CPU_PROCHOT#_R

H_PECI

CLK_DMI_PCH_DP

CLK_DMI_PCH_DN

CPU_DRAMRST#

H_CPUPWRGD

CPU_PROCHOT#

DRAMRST_CNTRL_PCH

DRAMRST_CNTRL

PM_DRAM_PWRGD

H_SNB_IVB#

H_PRDY#

H_PREQ#

H_TCK

H_TMS

H_TRST#

SYS_RESET#

H_TDI

H_TDO

H_TMS

H_TCK

H_TDI

H_PREQ#

H_TRST#

NV_CLE

PLT_RST#

DDR3_DRAMRST#

CPU_DRAMRST#

AP33

AP30

AR27

AN32

AP26

AR28

AR26

A4

A5

AK1

R8

V8

AN34

AR33

AL32

C26

AP27

AP29

AM34

AN33

A15

A16

AL35

AL33

AR32

AT31

AR31

AP32

AT30

AR30

AR29

AT28

A27

A28

2

1

3

2 1 2 1

21

1

21

2 1

21

2 1

21

2 1 2 1

21

1

2 1

21

2 1

JTAG & BPM MISCDDR3

PWR MANAGEMENT THERMAL

MISC

CLOCKS

UNCOREPWRGOOD

PROC_SELECT#

SKTOCC#

PM_SYNC

BPM#[7]

BPM#[6]

BPM#[5]

BPM#[4]

BPM#[3]

BPM#[2]

BPM#[1]

BPM#[0]

DBR#

TDO

TDI

TRST#

TMS

TCK

PREQ#

PRDY#

RESET#

SM_DRAMPWROK

THERMTRIP#

PROCHOT#

PECI

CATERR#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK

BCLK#

SM_RCOMP[0]

SM_DRAMRST#

SM_RCOMP[2]

SM_RCOMP[1]

G

DS

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH

- TYPICAL IMPEDANCE < 25 MOHMS

CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS

- TYPICAL IMPEDANCE = 43 MOHMS

REFERENCE 4500~4699(CPU)

- TYPICAL IMPEDANCE = 14.5 MOHMS

- MAX LENGTH = 500 MILS

PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH

- MAX LENGTH = 500 MILS

SHOULD BE SHORTED AND ROUTED WITH

CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS

CLOSE TO CPU

6842

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

LOTES_ACA_ZIF_069_P01_989P

0.22UF_6.3V_1

P1V05S

24.9_1%_2

Block Diagram

CS

A3

P1V05S

24.9_1%_2

CN4500

C4604

C4605

C4606

C4607

C4608

C4609

C4610

C4611

C4596

C4597

C4598

C4599

C4600

C4601

C4602

C4603

C4595

C4594

C4593

C4592

C4591

C4590

C4589

C4588

C4584

C4585

C4586

C4587

C4583

C4582

C4581

C4580

R4522

R4521

49C6

57B1

42C4

42B4

42C4

42A4

42B4

42C4

42B4

57C6

57D6

42B4

57B1

57C1

57D1

57C1

57D1

42D3

42A3

57B6

42B4 57B6

42B4

42B4 57C6

42A4 57C6

42A4 57D6

57D6

57C6

57B6

57C6

57D6

42B4

42B3

42C3

49D3

49C3

57B1

57C1

42A4

57D1

57B1

57D1

57B1

57C1

57D1

42C3

42A3

42B3

42A3

42B3

49D6

49C6

49D6

49D3

49D6

49D3

49C3

P1V0S_VCCP_PEG_ICOMPI

DMI_RX3_DP

P1V0S_VCCP_EDP_COMPIO

DMI_TX2_DN

PEG_TX0_DP

PEG_TX1_DP

PEG_TX2_DP

PEG_TX3_DP

PEG_TX4_DP

PEG_TX5_DP

PEG_TX6_DP

PEG_TX7_DP

PEG_TX8_DP

PEG_TX9_DP

PEG_TX10_DP

PEG_TX11_DP

PEG_TX12_DP

PEG_TX13_DP

PEG_TX14_DP

PEG_TX15_DP

PEG_TX0_DN

PEG_TX1_DN

PEG_TX2_DN

PEG_TX3_DN

PEG_TX4_DN

PEG_TX5_DN

PEG_TX6_DN

PEG_TX7_DN

PEG_TX8_DN

PEG_TX9_DN

PEG_TX10_DN

PEG_TX11_DN

PEG_TX12_DN

PEG_TX13_DN

PEG_TX14_DN

PEG_TX15_DN

PEG_C_RX0_DP

PEG_C_RX1_DP

PEG_C_RX2_DP

PEG_C_RX3_DP

PEG_C_RX4_DP

PEG_C_RX5_DP

PEG_C_RX6_DP

PEG_C_RX7_DP

PEG_C_RX8_DP

PEG_C_RX9_DP

PEG_C_RX10_DP

PEG_C_RX11_DP

PEG_C_RX12_DP

PEG_C_RX13_DP

PEG_C_RX14_DP

PEG_C_RX15_DP

PEG_C_RX0_DN

PEG_C_RX1_DN

PEG_C_RX2_DN

PEG_C_RX3_DN

PEG_C_RX4_DN

PEG_C_RX5_DN

PEG_C_RX6_DN

PEG_C_RX7_DN

PEG_C_RX8_DN

PEG_C_RX9_DN

PEG_C_RX10_DN

PEG_C_RX11_DN

PEG_C_RX12_DN

PEG_C_RX13_DN

PEG_C_RX14_DN

PEG_C_RX15_DN

FDI_LSYNC1

FDI_LSYNC0

FDI_INT

FDI_FSYNC1

FDI_FSYNC0

FDI_TX7_DP

FDI_TX6_DP

FDI_TX5_DP

FDI_TX4_DP

FDI_TX3_DP

FDI_TX2_DP

FDI_TX1_DP

FDI_TX0_DP

FDI_TX7_DN

FDI_TX6_DN

FDI_TX5_DN

FDI_TX4_DN

FDI_TX3_DN

FDI_TX2_DN

FDI_TX1_DN

FDI_TX0_DN

DMI_RX2_DP

DMI_RX1_DP

DMI_RX0_DP

DMI_RX3_DN

DMI_RX2_DN

DMI_RX1_DN

DMI_RX0_DN

DMI_TX3_DP

DMI_TX2_DP

DMI_TX1_DP

DMI_TX0_DP

DMI_TX3_DN

DMI_TX1_DN

DMI_TX0_DN

PEG_TX13_DN

PEG_TX12_DN

PEG_TX14_DN

PEG_TX0_DP

PEG_TX15_DP

PEG_TX15_DN

PEG_TX4_DN

PEG_TX11_DN

PEG_TX10_DN

PEG_TX9_DN

PEG_TX8_DN

PEG_TX7_DN

PEG_TX6_DN

PEG_TX5_DN

PEG_TX3_DN

PEG_C_TX10_DP

PEG_C_TX0_DN

PEG_TX1_DN

PEG_TX2_DN

PEG_C_TX15_DP

PEG_TX14_DP PEG_C_TX14_DP

PEG_TX13_DP PEG_C_TX13_DP

PEG_TX12_DP PEG_C_TX12_DP

PEG_TX11_DP PEG_C_TX11_DP

PEG_TX10_DP

PEG_TX9_DP PEG_C_TX9_DP

PEG_TX8_DP PEG_C_TX8_DP

PEG_TX7_DP PEG_C_TX7_DP

PEG_TX6_DP PEG_C_TX6_DP

PEG_TX5_DP PEG_C_TX5_DP

PEG_TX4_DP PEG_C_TX4_DP

PEG_TX3_DP PEG_C_TX3_DP

PEG_TX2_DP PEG_C_TX2_DP

PEG_C_TX1_DP

PEG_C_TX0_DP

PEG_C_TX8_DN

PEG_C_TX9_DN

PEG_C_TX10_DN

PEG_C_TX11_DN

PEG_C_TX12_DN

PEG_C_TX13_DN

PEG_C_TX14_DN

PEG_C_TX15_DN

PEG_C_TX7_DN

PEG_C_TX6_DN

PEG_C_TX5_DN

PEG_C_TX4_DN

PEG_C_TX3_DN

PEG_C_TX2_DN

PEG_C_TX1_DN

PEG_TX0_DN

PEG_TX1_DP

E25

F26

D28

F27

E29

G27

H29

J28

J30

K28

K31

L29

L32

M31

M32

M29

D25

E26

D27

F28

E28

G28

H28

J27

J29

K27

K30

L28

L31

M30

M33

M28

C32

B33

D31

D33

E32

E34

F35

G30

G33

H31

H34

J32

J35

L34

M35

K33

B32

C33

E31

D34

F32

E33

E35

F30

F33

G31

G34

H32

H35

K34

L35

J33

H22

J21

J22

H20

E17

D18

C20

B21

F17

D19

C19

B20

H17

J17

F18

E19

H19

A21

G18

E20

G19

A22

J19

J18

F15

D16

E16

C18

G15

C16

F16

C17

A17

B16

A18

D15

C15

D21

F21

E22

G21

C21

F20

D22

G22

B24

A25

B25

B27

B23

A24

B26

B28

21

2 1

OUT

IN

OUT

eDP

Intel(R) FDI

DMI

PCI EXPRESS* - GRAPHICS

eDP_ICOMPO

eDP_HPD

eDP_COMPIO

eDP_TX#[3]

eDP_TX#[2]

eDP_TX#[1]

eDP_TX#[0]

eDP_TX[3]

eDP_TX[2]

eDP_TX[1]

eDP_TX[0]

eDP_AUX#

eDP_AUX

PEG_TX[15]

PEG_TX[14]

PEG_TX[13]

PEG_TX[12]

PEG_TX[11]

PEG_TX[10]

PEG_TX[9]

PEG_TX[8]

PEG_TX[7]

PEG_TX[6]

PEG_TX[5]

PEG_TX[4]

PEG_TX[3]

PEG_TX[2]

PEG_TX[1]

PEG_TX[0]

PEG_TX#[15]

PEG_TX#[14]

PEG_TX#[13]

PEG_TX#[12]

PEG_TX#[11]

PEG_TX#[10]

PEG_TX#[9]

PEG_TX#[8]

PEG_TX#[7]

PEG_TX#[6]

PEG_TX#[5]

PEG_TX#[4]

PEG_TX#[3]

PEG_TX#[2]

PEG_TX#[1]

PEG_TX#[0]

PEG_RX[15]

PEG_RX[14]

PEG_RX[13]

PEG_RX[12]

PEG_RX[11]

PEG_RX[10]

PEG_RX[9]

PEG_RX[8]

PEG_RX[7]

PEG_RX[6]

PEG_RX[5]

PEG_RX[4]

PEG_RX[3]

PEG_RX[2]

PEG_RX[1]

PEG_RX[0]

PEG_RX#[15]

PEG_RX#[14]

PEG_RX#[13]

PEG_RX#[12]

PEG_RX#[11]

PEG_RX#[10]

PEG_RX#[9]

PEG_RX#[8]

PEG_RX#[7]

PEG_RX#[6]

PEG_RX#[5]

PEG_RX#[4]

PEG_RX#[3]

PEG_RX#[2]

PEG_RX#[1]

PEG_RX#[0]

PEG_RCOMPO

PEG_ICOMPO

PEG_ICOMPI

FDI1_LSYNC

FDI0_LSYNC

FDI_INT

FDI1_FSYNC

FDI0_FSYNC

FDI1_TX[3]

FDI1_TX[2]

FDI1_TX[1]

FDI1_TX[0]

FDI0_TX[3]

FDI0_TX[2]

FDI0_TX[1]

FDI0_TX[0]

FDI1_TX#[3]

FDI1_TX#[2]

FDI1_TX#[1]

FDI1_TX#[0]

FDI0_TX#[3]

FDI0_TX#[2]

FDI0_TX#[1]

FDI0_TX#[0]

DMI_TX[2]

DMI_TX[3]

DMI_TX[1]

DMI_TX[0]

DMI_TX#[3]

DMI_TX#[2]

DMI_TX#[1]

DMI_TX#[0]

DMI_RX[3]

DMI_RX[2]

DMI_RX[1]

DMI_RX[0]

DMI_RX#[3]

DMI_RX#[2]

DMI_RX#[1]

DMI_RX#[0]

OUT

IN

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4500~4699(CPU)

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

6843

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

LOTES_ACA_ZIF_069_P01_989P

15

14

13

12

11

10

9

8

7

6

5

4

3

2

163

62

61

45

43

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

14

13

11

A3 CS

Block Diagram

10

9

8

7

6

2

5

44

42

12

57

58

59

56

52

53

54

55

51

47

48

49

50

46

60

18

17

16

15

4

3

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

19

0

15

13

14

12

10

11

9

2

3

0

1

8

7

6

5

4

LOTES_ACA_ZIF_069_P01_989P

CN4500

39B8

38D8

38B8

38C8

38D8

38C8

39C8

38B8

38C8

39D8

38B8

38C8

38D5

38D8

38C8

39D5

39C8

39B8

39C8

39B8

39C8

39B8

M_A_DQ<6>

M_B_DQS4_DN

M_B_DQS5_DN

M_B_DQS6_DN

M_B_DQS3_DN

M_B_DQS2_DN

M_B_DQS1_DN

M_B_DQS7_DN

M_B_DQS0_DP

M_B_DQ<27>

M_B_DQ<26>

M_B_DQ<31>

M_B_DQ<32>

M_B_DQ<30>

M_B_DQ<29>

M_B_DQ<28>

M_B_DQ<55>

M_B_DQ<54>

M_B_DQ<53>

M_B_DQ<51>

M_B_A<1>

M_B_DQ<56>

M_A_DQ<63>

M_A_DQ<62>

M_A_DQ<61>

M_A_DQ<60>

M_A_DQ<59>

M_A_DQ<58>

M_A_DQ<57>

M_A_DQ<56>

M_A_DQ<55>

M_A_DQ<54>

M_A_DQ<53>

M_A_DQ<52>

M_A_DQ<51>

M_A_DQ<50>

M_A_DQ<49>

M_A_DQ<48>

M_A_DQ<47>

M_A_DQ<46>

M_A_DQ<45>

M_A_DQ<44>

M_A_DQ<43>

M_A_DQ<42>

M_A_DQ<41>

M_A_DQ<40>

M_A_DQ<39>

M_A_DQ<38>

M_A_DQ<37>

M_A_DQ<36>

M_A_DQ<35>

M_A_DQ<34>

M_A_DQ<33>

M_A_DQ<32>

M_A_DQ<31>

M_A_DQ<30>

M_A_DQ<29>

M_A_DQ<28>

M_A_DQ<27>

M_A_DQ<26>

M_A_DQ<25>

M_A_DQ<24>

M_A_DQ<23>

M_A_DQ<22>

M_A_DQ<21>

M_A_DQ<20>

M_A_DQ<19>

M_A_DQ<18>

M_A_DQ<17>

M_A_DQ<16>

M_A_DQ<15>

M_A_DQ<14>

M_A_DQ<13>

M_A_DQ<12>

M_A_DQ<11>

M_A_DQ<10>

M_A_DQ<9>

M_A_DQ<8>

M_A_DQ<7>

M_A_DQ<5>

M_A_DQ<4>

M_A_DQ<3>

M_A_DQ<2>

M_A_DQ<1>

M_A_DQ<0>

M_A_A<15>

M_A_A<14>

M_A_A<13>

M_A_A<12>

M_A_A<11>

M_A_A<10>

M_A_A<9>

M_A_A<8>

M_A_A<7>

M_A_A<6>

M_A_A<5>

M_A_A<4>

M_A_A<3>

M_A_A<2>

M_A_A<1>

M_A_A<0>

M_A_DQS7_DN

M_A_DQS7_DP

M_A_DQS6_DN

M_A_DQS6_DP

M_A_DQS5_DN

M_A_DQS5_DP

M_A_DQS4_DN

M_A_DQS4_DP

M_A_DQS3_DN

M_A_DQS3_DP

M_A_DQS2_DN

M_A_DQS2_DP

M_A_DQS1_DN

M_A_DQS1_DP

M_A_DQS0_DN

M_A_DQS0_DP

M_ODT1

M_ODT0

M_CS#1

M_CS#0

M_CKE1

M_CKE0

M_CLK_DDR1_DN

M_CLK_DDR0_DN

M_CLK_DDR1_DP

M_CLK_DDR0_DP

M_A_WE#

M_A_RAS#

M_A_CAS#

M_A_BS2

M_A_BS1

M_A_BS0

M_A_A<15..0>

M_B_DQ<63..0>

M_B_A<15..0>

M_B_BS0

M_B_BS1

M_B_BS2

M_B_CAS#

M_B_RAS#

M_B_WE#

M_B_DQ<0>

M_B_DQ<1>

M_B_DQ<2>

M_B_DQ<3>

M_B_DQ<4>

M_B_DQ<5>

M_B_DQ<6>

M_B_DQ<7>

M_B_DQ<8>

M_B_DQ<9>

M_B_DQ<10>

M_B_DQ<11>

M_B_DQ<12>

M_B_DQ<13>

M_B_DQ<14>

M_B_DQ<15>

M_B_DQ<16>

M_B_DQ<17>

M_B_DQ<18>

M_B_DQ<19>

M_B_DQ<20>

M_B_DQ<21>

M_B_DQ<22>

M_B_DQ<23>

M_B_DQ<24>

M_B_DQ<25>

M_B_DQ<33>

M_B_DQ<34>

M_B_DQ<35>

M_B_DQ<36>

M_B_DQ<37>

M_B_DQ<38>

M_B_DQ<39>

M_B_DQ<40>

M_B_DQ<41>

M_B_DQ<42>

M_B_DQ<43>

M_B_DQ<44>

M_B_DQ<45>

M_B_DQ<46>

M_B_DQ<47>

M_B_DQ<48>

M_B_DQ<49>

M_B_DQ<50>

M_B_DQ<52>

M_B_DQ<57>

M_B_DQ<58>

M_B_DQ<59>

M_B_DQ<60>

M_B_DQ<61>

M_B_DQ<62>

M_B_DQ<63>

M_CLK_DDR2_DP

M_CLK_DDR3_DP

M_CLK_DDR2_DN

M_CLK_DDR3_DN

M_CKE2

M_CKE3

M_ODT2

M_ODT3

M_B_DQS4_DP

M_B_DQS5_DP

M_B_DQS6_DP

M_B_DQS7_DP

M_B_DQS0_DN

M_B_DQS1_DP

M_B_DQS2_DP

M_B_DQS3_DP

M_B_A<0>

M_B_A<2>

M_B_A<3>

M_B_A<4>

M_B_A<5>

M_B_A<6>

M_B_A<7>

M_B_A<8>

M_B_A<9>

M_B_A<10>

M_B_A<11>

M_B_A<12>

M_B_A<13>

M_B_A<14>

M_B_A<15>

M_CS#2

M_CS#3

M_A_DQ<63..0>

AF9

AD9

AG3

AH3

V7

V5

AF8

W4

V4

AD8

W5

V1

W6

W3

V2

V3

W7

W2

W1

AD10

AM15

AR12

AM8

AL6

M6

J3

G6

C4

AM14

AR11

AM9

AL5

N6

K3

F6

D4

AH15

AJ15

AK14

AL14

AK15

AL15

AH14

AJ14

AN12

AP12

AL11

AM11

AM12

AL12

AN11

AP11

AL8

AL9

AH9

AH8

AK9

AJ9

AK8

AJ8

AJ6

AJ5

AH6

AH5

AK5

AK6

AG5

AG6

M7

N9

M9

M10

N7

N8

N10

M8

K2

J2

J4

J5

J1

K1

K5

K4

G7

G8

F7

F9

G9

G10

F8

F10

C3

C2

C6

D6

D2

D3

D5

C5

AL3

AK3

AB5

AA6

AA5

AB6

V10

V9

AE8

V6

AF10

AE10

AH2

AG2

AH1

AG1

W10

AA3

AB3

W9

AA4

AB4

AB9

AB8

AD4

AE4

R4

R5

AB10

T1

R1

AB7

R3

T5

R2

T3

T4

T2

T6

R7

T7

AA8

AP15

AK12

AP9

AN5

N3

K6

F3

D7

AP14

AK11

AP8

AN6

M3

J6

G3

C7

AT15

AR15

AN15

AT12

AT14

AR14

AN14

AT11

AH12

AJ12

AR8

AH11

AT9

AT8

AJ11

AR9

AR5

AR6

AN8

AP6

AT6

AT5

AN9

AP5

AP2

AN1

AN2

AN3

AP3

AR3

AM6

AM5

M1

M2

N5

M4

N1

N2

N4

M5

K7

K8

J10

J9

K9

K10

J8

J7

G2

F2

F5

G5

G1

F1

F4

G4

D8

D9

A8

A9

C8

D10

A7

C9

AE3

AD3

AD1

AD2

AE1

AE2

R10

R9

AA10

R6

AA7

AA9

AE5

AD5

AE6

AD6

T10

AB1

AA1

T9

AA2

AB2

BI

DDR SYSTEM MEMORY A

RSVD_TP[10]

RSVD_TP[9]

RSVD_TP[8]

RSVD_TP[7]

RSVD_TP[6]

RSVD_TP[3]

RSVD_TP[5]

RSVD_TP[4]

RSVD_TP[2]

RSVD_TP[1]

SA_DQ[63]

SA_DQ[62]

SA_DQ[61]

SA_DQ[60]

SA_DQ[59]

SA_DQ[58]

SA_DQ[57]

SA_DQ[56]

SA_DQ[55]

SA_DQ[54]

SA_DQ[53]

SA_DQ[52]

SA_DQ[51]

SA_DQ[50]

SA_DQ[49]

SA_DQ[48]

SA_DQ[47]

SA_DQ[46]

SA_DQ[45]

SA_DQ[44]

SA_DQ[43]

SA_DQ[42]

SA_DQ[41]

SA_DQ[40]

SA_DQ[39]

SA_DQ[38]

SA_DQ[37]

SA_DQ[36]

SA_DQ[35]

SA_DQ[34]

SA_DQ[33]

SA_DQ[32]

SA_DQ[31]

SA_DQ[30]

SA_DQ[29]

SA_DQ[28]

SA_DQ[27]

SA_DQ[26]

SA_DQ[25]

SA_DQ[24]

SA_DQ[23]

SA_DQ[22]

SA_DQ[21]

SA_DQ[20]

SA_DQ[19]

SA_DQ[18]

SA_DQ[17]

SA_DQ[16]

SA_DQ[15]

SA_DQ[14]

SA_DQ[13]

SA_DQ[12]

SA_DQ[11]

SA_DQ[10]

SA_DQ[9]

SA_DQ[8]

SA_DQ[7]

SA_DQ[6]

SA_DQ[5]

SA_DQ[4]

SA_DQ[3]

SA_DQ[2]

SA_DQ[1]

SA_DQ[0]

SA_MA[15]

SA_MA[14]

SA_MA[13]

SA_MA[12]

SA_MA[11]

SA_MA[10]

SA_MA[9]

SA_MA[8]

SA_MA[7]

SA_MA[6]

SA_MA[5]

SA_MA[4]

SA_MA[3]

SA_MA[2]

SA_MA[1]

SA_MA[0]

SA_DQS#[7]

SA_DQS[7]

SA_DQS#[6]

SA_DQS[6]

SA_DQS#[5]

SA_DQS[5]

SA_DQS#[4]

SA_DQS[4]

SA_DQS#[3]

SA_DQS[3]

SA_DQS#[2]

SA_DQS[2]

SA_DQS#[1]

SA_DQS[1]

SA_DQS#[0]

SA_DQS[0]

SA_ODT[1]

SA_ODT[0]

SA_CS#[1]

SA_CS#[0]

SA_CKE[1]

SA_CKE[0]

SA_CLK#[1]

SA_CLK#[0]

SA_CLK[1]

SA_CLK[0]

SA_WE#

SA_RAS#

SA_CAS#

SA_BS[2]

SA_BS[1]

SA_BS[0]

DDR SYSTEM MEMORY B

RSVD_TP[20]

RSVD_TP[19]

RSVD_TP[18]

RSVD_TP[17]

SB_CS#[1]

SB_CS#[0]

RSVD_TP[16]

RSVD_TP[15]

RSVD_TP[14]

RSVD_TP[13]

RSVD_TP[12]

RSVD_TP[11]

SB_DQ[63]

SB_DQ[62]

SB_DQ[61]

SB_DQ[60]

SB_DQ[59]

SB_DQ[58]

SB_DQ[57]

SB_DQ[56]

SB_DQ[55]

SB_DQ[54]

SB_DQ[53]

SB_DQ[52]

SB_DQ[51]

SB_DQ[50]

SB_DQ[49]

SB_DQ[48]

SB_DQ[47]

SB_DQ[46]

SB_DQ[45]

SB_DQ[44]

SB_DQ[43]

SB_DQ[42]

SB_DQ[41]

SB_DQ[40]

SB_DQ[39]

SB_DQ[38]

SB_DQ[37]

SB_DQ[36]

SB_DQ[35]

SB_DQ[34]

SB_DQ[33]

SB_DQ[32]

SB_DQ[31]

SB_DQ[30]

SB_DQ[29]

SB_DQ[28]

SB_DQ[27]

SB_DQ[26]

SB_DQ[25]

SB_DQ[24]

SB_DQ[23]

SB_DQ[22]

SB_DQ[21]

SB_DQ[20]

SB_DQ[19]

SB_DQ[18]

SB_DQ[17]

SB_DQ[16]

SB_DQ[15]

SB_DQ[14]

SB_DQ[13]

SB_DQ[12]

SB_DQ[11]

SB_DQ[10]

SB_DQ[9]

SB_DQ[8]

SB_DQ[7]

SB_DQ[6]

SB_DQ[5]

SB_DQ[4]

SB_DQ[3]

SB_DQ[2]

SB_DQ[1]

SB_DQ[0]

SB_MA[15]

SB_MA[14]

SB_MA[13]

SB_MA[12]

SB_MA[11]

SB_MA[10]

SB_MA[9]

SB_MA[8]

SB_MA[7]

SB_MA[6]

SB_MA[5]

SB_MA[4]

SB_MA[3]

SB_MA[2]

SB_MA[1]

SB_MA[0]

SB_DQS#[3]

SB_DQS[3]

SB_DQS#[2]

SB_DQS[2]

SB_DQS#[1]

SB_DQS[1]

SB_DQS#[0]

SB_DQS[0]

SB_DQS#[7]

SB_DQS[7]

SB_DQS#[6]

SB_DQS[6]

SB_DQS#[5]

SB_DQS[5]

SB_DQS#[4]

SB_DQS[4]

SB_ODT[1]

SB_ODT[0]

SB_CKE[1]

SB_CKE[0]

SB_CLK#[1]

SB_CLK#[0]

SB_CLK[1]

SB_CLK[0]

SB_WE#

SB_RAS#

SB_CAS#

SB_BS[2]

SB_BS[1]

SB_BS[0]

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4500~4699(CPU)

SVID SIGNAL TO VR

PLACE CLOSE TO CPU

44

MODEL,PROJECT,FUNCTION

X01

68

XXX 21-OCT-2002

1310xxxxx-0-0

LOTES_ACA_ZIF_069_P01_989P

100_1%_2

0_5%_2

43_5%_2

P1V05S

75_5%_2130_1%_2

PVCORE

P1V05S

10_1%_2

100_1%_2

0_5%_2

22UF_6.3V_5

P1V05S

22UF_6.3V_5

CSC

Block Diagram

22UF_6.3V_5 22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5 22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5 22UF_6.3V_5

PVCORE

22UF_6.3V_5 22UF_6.3V_5

CN4500

R4535

R4534

R4533

R4532

R4527R4528

R4531

R4530

R4529

C4542

C4541

C4540

C4535

C4536

C4537

C4533

C4534

C4531

C4532

C4522 C4523 C4524 C4525

C4518 C4519 C4520 C4521

C4514 C4515 C4516 C4517

C4513C4512C4511C4510

11D6

11A3 11C7

11C7

9B7

11A3 11C7

VCCSENSE

H_CPU_SVIDDAT

H_CPU_SVIDCLK

H_CPU_SVIDALRT#

VR_SVID_DATA

VR_SVID_CLK

VR_SVID_ALERT#

VCC_SENSE_VCCIO

VSS_SENSE_VCCIO

VSSSENSE

A10

AJ34

AJ28

AJ30

AJ29

B10

J14

L10

P10

U10

Y10

J23

AC10

A11

A12

A13

A14

B12

B14

C11

C12

C13

C14

AG10

D11

D12

D13

D14

E11

E12

E14

F11

F12

F13

AH10

F14

G12

G13

G14

H11

H12

H14

J11

J12

J13

AH13

AJ35

P27

P28

P29

P30

P31

P32

P33

P34

P35

R26

AG27

R27

R28

R29

R30

R31

R32

R33

R34

R35

U26

AG28

U27

U28

U29

U30

U31

U32

U33

U34

U35

V26

AG29

V27

V28

V29

V30

V31

V32

V33

V34

V35

Y26

AG30

Y27

Y28

Y29

Y30

Y31

Y32

Y33

Y34

Y35

AA26

AG31

AA27

AA28

AA29

AA30

AA31

AA32

AA33

AA34

AA35

AC26

AG32

AC27

AC28

AC29

AC30

AC31

AC32

AC33

AC34

AC35

AD26

AG33

AD27

AD28

AD29

AD30

AD31

AD32

AD33

AD34

AD35

AF26

AG34

AF27

AF28

AF29

AF30

AF31

AF32

AF33

AF34

AF35

P26

AG26

AG35

2 1 2 1

2 1

21

2 1

2 1 2 1

2 1

SVID

SENSE LINES

PEG AND DDR

CORE SUPPLY

POWER

VCCIO40

VCCIO_SENSE

VCCIO31

VCCIO30

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO25

VCCIO17

VCCIO16

VCCIO15

VCCIO14

VCCIO13

VCCIO11

VCCIO10

VCCIO9

VCCIO8

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO24

VCCIO23

VCCIO22

VCCIO21

VCCIO20

VCCIO19

VCCIO18

VCCIO12

VCCIO1

VCC100

VCC99

VCC98

VCC97

VCC96

VCC95

VCC94

VCC93

VCC92

VCC91

VCC90

VCC89

VCC88

VCC87

VCC86

VCC85

VCC84

VCC83

VCC82

VCC81

VCC80

VCC79

VCC78

VCC77

VCC76

VCC75

VCC74

VCC73

VCC72

VCC71

VCC70

VCC69

VCC68

VCC67

VCC66

VCC65

VCC64

VCC63

VCC62

VCC61

VCC60

VCC59

VCC58

VCC57

VCC56

VCC55

VCC54

VCC53

VCC52

VCC51

VCC50

VCC49

VCC48

VCC47

VCC46

VCC45

VCC44

VCC43

VCC42

VCC41

VCC40

VCC39

VCC38

VCC37

VCC36

VCC35

VCC34

VCC33

VCC32

VCC31

VCC30

VCC29

VCC28

VCC27

VCC26

VCC25

VCC24

VCC23

VCC22

VCC21

VCC20

VCC19

VCC18

VCC17

VCC16

VCC15

VCC14

VCC13

VCC12

VCC11

VCC10

VCC9

VCC8

VCC7

VCC6

VCC5

VCC4

VCC3

VCC2

VCC1

VSSIO_SENSE

VIDSOUT

VIDSCLK

VIDALERT#

VSS_SENSE

VCC_SENSE

OUT

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7654321

76543

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

ROUTE WITH MIN. TRACE WIDTH OF 10 MILS

PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:

5A

1.2A

IVB:1K OHM

SNB:0 OHM

R4547

NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE

6845

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

1UF_6.3V_2

10UF_6.3V_3

100UF_6.3V

1UF_6.3V_2

22UF_6.3V_5

AM2302N

PVSA

10UF_6.3V_3

A3 CS

Block Diagram

10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3

470PF_50V_2

220UF_2.5V

AM2302N

PVAXG

0_5%_2

AM2302N

P0V75M_VREF P0V75M_VREF_H

P1V5S

100K_5%_2

PVAXG

22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5

MPZ1608S221AT

P1V8S

P0V75M_VREF_H

22UF_6.3V_5 22UF_6.3V_5

P0V75M_VREF

PVSA

10UF_6.3V_3

10UF_6.3V_310UF_6.3V_3

10_1%_2

10UF_6.3V_3 10UF_6.3V_3

100_5%_2

1K_5%_2 1K_5%_2

22UF_6.3V_5

LOTES_ACA_ZIF_069_P01_989P

CN4500

R4547R4556

R4540

R4539

C4577

R4544

C4578

R4541

R4538

Q4500

Q4502

Q4501

L4500

C4573

C4576C4575C4574

C4572C4571C4570C4569C4568C4567

C4562 C4563 C4564 C4565

C4651 C4545 C4550C4546 C4547 C4548 C4549

21D6 14D2 14B8

46C4

45D6 41A8

46C4

11B8

45D8 41A8

14A6

13A2

13D2

10B4

10C4

49A1 SLP_S3#_3R

CPUDDR_WR_VREF1

DRAMRST_CNTRL

CPUDDR_WR_VREF2

DRAMRST_CNTRL

GFX_VSS_SENSE

GFX_VCC_SENSE

VCCSA_SENSE

VCCSA_VID1

VCCSA_VID0

P1V8S_VCCPLL

AK34

Y1

Y4

Y7

AC1

AC4

AC7

AF1

AF4

P1

P4

P7

U1

U4

U7

AF7

C24

H23

H25

H26

J24

J25

J26

L26

M26

M27

A2

A6

B6

AK35

AR21

AR23

AR24

AT17

AH17

AH18

AH20

AH21

AH23

AT18

AH24

AJ17

AJ18

AJ20

AJ21

AJ23

AJ24

AK17

AK18

AK20

AT20

AK21

AK23

AK24

AL17

AL18

AL20

AL21

AL23

AL24

AM17

AT21

AM18

AM20

AM21

AM23

AM24

AN17

AN18

AN20

AN21

AN23

AT23

AN24

AP17

AP18

AP20

AP21

AP23

AP24

AR17

AR18

AR20

AT24

AL1

C22

2 1

2 1 2 1

2 1

21

2

1

3

2

1

3

2

1

3

21

2 1

OUT

IN

G

DS

G

D S

G

D S

+

MISC VREF

SA RAIL

1.8V RAIL

LINES

SENSE

DDR3 -1.5V RAILS

GRAPHICS

POWER

FC_C22

VCCPLL3

VCCSA_VID1

VCCSA_SENSE

VCCSA8

VCCSA7

VCCSA6

VCCSA5

VCCSA4

VCCSA3

VCCSA2

VCCSA1

VCCPLL2

VCCPLL1

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

VDDQ1

VDDQ15

VDDQ14

VDDQ13

VDDQ12

VDDQ11

VAXG54

VAXG53

VAXG52

VAXG51

VAXG50

VAXG49

VAXG48

VAXG47

VAXG46

VAXG45

VAXG44

VAXG43

VAXG42

VAXG41

VAXG40

VAXG39

VAXG38

VAXG37

VAXG36

VAXG35

VAXG34

VAXG33

VAXG32

VAXG31

VAXG30

VAXG29

VAXG28

VAXG27

VAXG26

VAXG25

VAXG24

VAXG23

VAXG22

VAXG21

VAXG20

VAXG19

VAXG18

VAXG17

VAXG16

VAXG15

VAXG14

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VAXG3

VAXG2

VAXG1 VAXG_SENSE

VSSAXG_SENSE

SM_VREF

+

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

0 : EDP ENABLED

0 : LANE REVERSED

CFG(2)

CFG(7)

LOW EDP ENABLE

CFG(4)

PEG DEFER TRAINING

STRAP PIN

PEG STATIC LAN REVERSAL

LOW EDP ENABLE

PCIE PORT BIFURCATION

PEG DEFER TRAINING CFG[6:5]

PEG STATIC LANE REVERSAL

CLK_XDP_CLKGEN_DP

CLK_XDP_CLKGEN_DN

00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED

01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED)

10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED

11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED

PCIE PORT BIFURCATION STRAPS

0 : PEG WAIT FOR BIOS FOR TRAINING

1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION

1 : (DEFAULT) EDP DISABLED

1 : (DEFAULT) NORMAL OPERATION

REMOVE

6846

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

LOTES_ACA_ZIF_069_P01_989P

1K_1%_2_DY

1K_1%_2

1K_1%_2_DY

A3 CS

Block Diagram

LOTES_ACA_ZIF_069_P01_989P

10K_5%_2_DY

R4555

CN4500CN4500

CN4500

R4553

R4554

R4552

R4551

R4550

45D8

45D6

46D4

46A6

9C7

CFG<7>

CFG<2>

CFG<5>

CFG<4>

CFG<6>

CFG<0>

CFG<1>

CFG<2>

CFG<3>

CFG<4>

CFG<5>

CFG<6>

CFG<7>

CFG<8>

CFG<9>

CFG<10>

CFG<12>

CFG<13>

CFG<14>

CFG<15>

CFG<17>

CFG<11>

CFG<16>

VCCIO_SEL

CPUDDR_WR_VREF1

CPUDDR_WR_VREF2

21

AH31

AH33

A19

AJ33

AH27

AJ31

F24

F25

D1

B4

AR1

AT1

AT2

AM35

AN35

AK32

AJ32

C35

AJ26

B35

A34

A33

B34

AR34

AP35

AT33

AT34

AR35

G16

H16

J16

T8

AJ27

AM33

AT26

W8

AK2

AE7

AG7

L7

J15

B18

J20

C29

A30

B31

D30

B29

B30

A31

C30

D23

E23

G24

G25

D24

F23

B1

AN29

AK31

AM27

AN26

AN31

AN28

AM26

AM28

AM30

AM32

AM31

AL30

AL29

AK26

AL27

AL26

AK29

AK28

A3

A20

A23

A26

A29

A32

A35

B2

B3

B5

B7

B8

B9

B11

B13

B15

B17

B19

B22

C1

C10

C23

C25

C27

C28

C31

C34

D17

D20

D26

D29

D32

D35

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E13

E15

E18

E21

E24

E27

E30

F19

F22

F29

F31

F34

G11

G17

G20

G23

G26

G29

G32

G35

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H13

H15

H18

H21

H24

H27

H30

H33

J31

J34

K26

K29

K32

K35

L1

L2

L3

L4

L5

L6

L8

L9

L27

L30

L33

M34

N26

N27

N28

N29

N30

N31

N32

N33

N34

N35

P2

P3

P5

P6

P8

P9

T26

T27

T28

T29

T30

T31

T32

T33

T34

T35

AH22

AH25

AH26

AH28

AH29

AH30

AH32

AH34

AH35

AJ1

AT13 AJ2

AJ3

AJ4

AJ7

AJ10

AJ13

AJ16

AJ19

AJ22

AJ25

AT16

AK4

AK7

AK10

AK13

AK16

AK19

AK22

AK25

AK27

AK30

AT19

AK33

AL2

AL4

AL7

AL10

AL13

AL16

AL19

AL22

AL25

AT22

AL28

AL31

AL34

AM1

AM2

AM3

AM4

AM7

AM10

AM13

AT25

AM16

AM19

AM22

AM25

AM29

AN4

AN7

AN10

AN13

AN16

AT27

AN19

AN22

AN25

AN27

AN30

AP1

AP4

AP7

AP10

AP13

AT29

AP16

AP19

AP22

AP25

AP28

AP31

AP34

AR2

AR4

AR7

AT32

AR10

AR13

AR16

U2

AR19

U3

U5

U6

U8

U9

W26

W27

W28

W29

W30

AR22

W31

W32

W33

W34

W35

Y2

Y3

Y5

Y6

Y8

AR25

Y9

AB26

AB27

AB28

AB29

AB30

AB31

AB32

AB33

AB34

AT3

AB35

AC2

AC3

AC5

AC6

AC8

AC9

AD7

AE9

AE26

AT4

AE27

AE28

AE29

AE30

AE31

AE32

AE33

AE34

AE35

AF2

AT7

AF3

AF5

AF6

AG4

AG8

AG9

AH4

AH7

AH16

AH19

AT10

AT35

21

IN

OUT

RESERVED

RSVD55

RSVD54

VCCIO_SEL

VCC_DIE_SENSE

KEY

VSS_VAL_SENSE

VCC_VAL_SENSE

VSSAXG_VAL_SENSE

VAXG_VAL_SENSE

RSVD5

RSVD10

RSVD44

RSVD25

RSVD33

RSVD32

RSVD14

RSVD13

RSVD12

RSVD11

RSVD9

RSVD8

RSVD7

RSVD6

RSVD37

RSVD24

RSVD23

RSVD21

RSVD22

RSVD19

RSVD20

RSVD18

RSVD17

RSVD15

RSVD16

RSVD27

RSVD29

RSVD28

RSVD31

RSVD30

RSVD52

RSVD51

RSVD50

RSVD49

RSVD48

RSVD47

RSVD46

RSVD58

RSVD57

RSVD56

RSVD45

RSVD43

RSVD41

RSVD40

RSVD39

RSVD42

RSVD38

RSVD35

RSVD34

CFG[17]

CFG[16]

CFG[15]

CFG[14]

CFG[13]

CFG[12]

CFG[11]

CFG[10]

CFG[9]

CFG[8]

CFG[7]

CFG[6]

CFG[5]

CFG[4]

CFG[3]

CFG[2]

CFG[1]

CFG[0]

VSS_1

VSS285

VSS284

VSS283

VSS282

VSS281

VSS280

VSS279

VSS278

VSS277

VSS276

VSS275

VSS274

VSS273

VSS272

VSS271

VSS270

VSS269

VSS268

VSS267

VSS266

VSS265

VSS264

VSS263

VSS262

VSS261

VSS260

VSS259

VSS258

VSS257

VSS256

VSS255

VSS254

VSS253

VSS252

VSS251

VSS250

VSS249

VSS248

VSS247

VSS246

VSS245

VSS244

VSS243

VSS242

VSS241

VSS240

VSS239

VSS238

VSS237

VSS236

VSS235

VSS234

VSS233

VSS232

VSS231

VSS230

VSS229

VSS228

VSS227

VSS226

VSS225

VSS224

VSS223

VSS222

VSS221

VSS220

VSS219

VSS218

VSS217

VSS216

VSS215

VSS214

VSS213

VSS212

VSS211

VSS210

VSS209

VSS208

VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS130

VSS129

VSS128

VSS127

VSS126

VSS125

VSS124

VSS123

VSS122

VSS121

VSS120

VSS119

VSS118

VSS117

VSS116

VSS115

VSS114

VSS113

VSS112

VSS111

VSS110

VSS109

VSS108

VSS107

VSS106

VSS105

VSS104

VSS103

VSS102

VSS101

VSS100

VSS99

VSS98

VSS97

VSS96

VSS95

VSS94

VSS93

VSS92

VSS91

VSS90

VSS89

VSS88

VSS87

VSS86

VSS85

VSS84

VSS83

VSS82

VSS81

VSS80

VSS79

VSS78

VSS77

VSS76

VSS75

VSS74

VSS73

VSS72

VSS71

VSS70

VSS69

VSS68

VSS67

VSS66

VSS65

VSS64

VSS63

VSS62

VSS61

VSS60

VSS59

VSS58

VSS57

VSS56

VSS55

VSS54

VSS53

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

IN

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

STRAPPING

HDA_3S_SYNC_R(PLL ODVR VOLTAGE)

1 : VCC VRM = 1.6V

0 : VCC VRM = 1.8V(DEFAULT)

0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)

FLASH DESCRIPTOR SECURITY OVERIDE

0:ENABLE EXTERNAL VRS

STRAP

STRAPPING

0 : (DEFAULT) NO REBOOT DISABLED

1 : NO REBOOT ENABLED

PCSPKR_PCH_3(NO REBOOT)

1:ENABLE

FLASH OVERRIDE

REFERENCE 4700~4949(PCH)

STRAPPING

INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE

1:ENABLE INTERNAL VRS

6847

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

TP30

1K_5%_2

33_5%_2

Block Diagram

CS

A3

LOTES_AAA_BAT_063_P02_A_2P

BAT54C_30V_0.2A

1K_5%_2

0_5%_2_DY

1UF_6.3V_2

20K_1%_2

P3V3_RTC

330K_5%_3

10K_5%_2_DY

TP30

32.768KHZ

10M_5%_2

18PF_50V_2

P3V3_RTC

1UF_6.3V_2

1M_5%_2

P1V05S

37.4_1%_2

TP30

RSC_0402_DY

1UF_6.3V_2

18PF_50V_2

P1V05S

P3V3AL

P3V3A

RSC_0402_DY

0_5%_2_DY

RSC_0402_DY

P3V3A

10K_5%_2

P3V3S

49.9_1%_2

20K_1%_2

TP30

1K_5%_2

10K_5%_210K_5%_2

P3V3S

750_1%_2

P3V3_RTC

ITL_PANTHERPOINT_FCBGA_989P

RSC_0402_DY

33_5%_2

CN4700

R4700

X4700

TP4705

R4750

D4700

R4718

R4743R4741R4739

TP4723

TP4722

TP4721

TP4720

C4701

C4702

C4700

C4704

C4703

R4708

R4707

R4705

R4704

R4703

R4714

R4720

R4734

R4706

R4711

R4709

R4712

R4715

R4716

R4736

R4737

R4742R4740R4738

R4749

R4748

R4747

R4744

R4752R4751

U4700

28C7

29D5

47D3

24B2

24B1

21C8

21C7

21C8

21C7 21C6

21D6

24A2

47D3

21C6

29A7

27C3 21E3

24A2

47B6

47A6

47B7

21D3

29A7

27B7 21E3

21D3

47B8

24B2

21C8

24A2

SATA_HDD_TX_DN

SATA_HDD_TX_DP

SATA_MINICARD_RX_DN

SATA_MINICARD_TX_DP

SATA_MINICARD_TX_DN

SATA_MINICARD_RX_DP

SATA_HDD_RX_DP

SATA_HDD_RX_DN

HDA_3S_SDOUT

HDA_3S_RST#

HDA_3S_SDIN0

HDA_3S_RST#_R

HDA_3S_SYNC_R

HDA_3S_BITCLK_R

HDA_3S_SYNC

FLASH_OVERRIDE

HDA_3S_BITCLK

PCSPKR_PCH_3

EC_SPI_SI

EC_SPI_CS1#

RTCX2

RTCX1

PCH_TMS

PCH_TDI

PCH_TDO

FLASH_OVERRIDE

HDA_3S_SYNC_R

PCH_TDO

PCH_TDI

PCH_TMS

PCH_TCK

EC_SPI_CS0#

EC_SPI_CLK

SATA_ODD_TX_DP

SATA_ODD_TX_DN

SATA_ODD_RX_DP

SATA_ODD_RX_DN

EC_SMI

LPC_3S_FRAME#

LPC_3S_AD<3>

LPC_3S_AD<2>

LPC_3S_AD<1>

LPC_3S_AD<0>

P1V05S_SATARCOMPO

PCI_3S_SERIRQ

P1V05S_SATA3RCOMPO

EC_SPI_SO

2 1 2 1

4

32

1

2 1

3

21

2 1

1

2 1

21

2 1

21

2 1

21

2 1

G22

T10

V4

U3

T1

Y14

T3

V5

P3

Y11

Y10

AB1

AB3

Y1

Y3

AD1

AD3

Y5

Y7

AF1

AF3

AB10

AB8

AB12

AH1

AB13

AH4

AH5

AD5

AD7

AP10

AP11

AM8

AM10

P1

AP5

AP7

AM1

AM3

V14

C20

A20

D20

K36

E36

H7

H1

K5

J3

C17

K22

L34

A36

A34

C34

G34

E34

K34

N32

C36

N34

D36

C37

B37

A38

C38

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

- +

OUT

IN

C

A2A1

SATA 6G

JTAG

SPI

LPC

SATA

IHDA RTC

SATA3RBIAS

SATA3RCOMPO

SATA3COMPI

SATAICOMPO

SPKR

SERIRQ

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

SATA1GP/GPIO19

SATA0GP/GPIO21

SPI_MISO

SPI_MOSI

SPI_CS1#

SPI_CS0#

SPI_CLK

SATAICOMPI

SATA5TXP

SATA5TXN

SATA5RXP

SATA5RXN

SATA4TXP

SATA4TXN

SATA4RXP

SATA4RXN

SATA3TXP

SATA3TXN

SATA3RXP

SATA3RXN

SATA2TXP

SATA2TXN

SATA2RXP

SATA2RXN

SATA1TXP

SATA1TXN

SATA1RXP

SATA1RXN

SATA0TXP

SATA0TXN

SATA0RXP

SATA0RXN

SRTCRST#

HDA_DOCK_RST#/GPIO13

HDA_DOCK_EN#/GPIO33

HDA_SDIN3

RTCRST#

LDRQ0#

FWH4/LFRAME#

LDRQ1#/GPIO23

FWH3/LAD3

FWH2/LAD2

FWH1/LAD1

FWH0/LAD0

SATALED#

HDA_SDO

HDA_SDIN2

HDA_SDIN1

HDA_SDIN0

HDA_RST#

HDA_SYNC

HDA_BCLK

INTRUDER#

INTVRMEN

RTCX2

RTCX1

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CLOSE TO PCH

CLOCK TERMINATION FOR FICM

REFERENCE 4700~4949(PCH)

STUFF FOR INTEGRATED CLK

6848

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P3V3A

0.1UF_16V_2

10K_5%_2

P3V3A

P1V05S

10K_5%_2

0.1UF_16V_2

10K_5%_2

P3V3A

10K_5%_2

2.2K_5%_2

1M_5%_2

25MHZ

Block Diagram

CS

A3

ITL_PANTHERPOINT_FCBGA_989P

P5V0S

10K_5%_2

2.2K_5%_2

10K_5%_2

0.1UF_16V_2

10K_5%_2_DY

TP24

P3V3A

2.2K_5%_2

P3V3S

PASSWORD_0805

18PF_50V_2

10K_5%_2_DY

2.2K_5%_2

P3V3A

SSM3K7002FU_DY

P3V3S

90.9_1%_2

TP24

10K_5%_2_DY

P3V3A

10K_5%_2

10K_5%_2_DY

0.1UF_16V_2

10K_5%_2

SSM3K7002BFU

10K_5%_2

10K_5%_2_DY

P3V3A

10K_5%_2_DY

10K_5%_2

Q4700

Q4701

TP4701

R4753

TP4702

TP4700

R4794

R4793

R4792

R4791

R4790

R4789

C4793

C4794

TP4703

TP4704

R4800

R4799

R4798

R4797

R4796

Q4703

Q4702

R4801

C4729

C4728

X4701

B500

R4802

R4837

R4784 R4785

R4786

R4787

R4783

R4782

R4781

R4780

R4779

R4778

R4777

R4772

R4773

R4776

R4775

R4795

C4727

C4726

C4725

C4724

U4700

48D7

48C7

22C5 48D8

22C5

48C3

41D2

48C8

48B3

22C2

31C7

22C2

48B3

48D3

48B2

48A8

41A8

48A3

22B1

48B3

48A3

39C8

38C8

48D3

39C8

38C8

48B3

41D2

57B6

27B7

31C7

48D7

48B7

27C7

31C7

31B8

48A3

48D3

48D2 27B3

48D3

27C7

31C7

48D8

48D7

27C7

48D8

48D7

22C5

22C2

48C8

48B8

51A7

48C1

48B1

48C7

48D2

48C2

48D3

27B3

48D3

27B3

48D3

57B6

48B8

22B1

48B7

27C7

48D8

48C8

48C3

CLKREQ_LAN#

PCIE_USB3_TX_C_DN

CLKREQ_GPU#

SML1_CLK

SML1ALERT#

CLKIN_DMI_PCH_DN

PCIE_LAN_TX_DP

PCIE_WLAN_TX_C_DP

PCIE_WLAN_TX_C_DN

PCIE_LAN_TX_C_DP

PCIE_LAN_TX_C_DN

PCIE_USB3_TX_DN

PCIE_LAN_TX_DN

CLKIN_SATA1_DP

SML1ALERT#

PCH_3A_ALERT_CLK

PCH_3A_ALERT_DAT

PCH_3A_SMCLK

PCH_3A_SMDATA

XTAL25_OUT

PCIE_LAN_RX_DN

PCIE_LAN_RX_DP

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_PCH14

PCH_3A_SMDATA

CLKIN_SATA1_DN

PCIE_USB3_TX_DP

CLKREQ_WLAN#

XTAL25_IN

SMB_ALERT#

SML1_CLK

EC_SMB3_CLK

EC_SMB3_DATA

SML1_DATA

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_SATA1_DN

CLKIN_SATA1_DP

CLKIN_PCH14

XTAL25_OUT

XTAL25_IN

PCH_3A_ALERT_DAT

SMB_ALERT#

DRAMRST_CNTRL_PCH

PCH_3A_ALERT_CLK

CLKIN_PCI_FB

CLKREQ_USB3#

CLK_PCIE_USB3_DP

CLK_PCIE_USB3_DN

CLK_PCIE_LAN_DP

PCIE_USB3_RX_DP

PCIE_USB3_RX_DN

PCIE_WLAN_TX_DP

PCIE_WLAN_TX_DN

PCIE_WLAN_RX_DP

PCIE_WLAN_RX_DN

CLKREQ_WLAN#

CLK_PCIE_WLAN_DP

CLK_PCIE_WLAN_DN

CLKREQ_LAN#

CLK_PCIE_LAN_DN

CLKREQ_LAN#

PCH_3A_SMCLK

PCH_3S_SMCLK

PCH_3S_SMDATA

CLKREQ_WLAN#

PCIE_USB3_TX_C_DP

SML1_DATA

CLKIN_DMI_PCH_DP

CLKIN_DMI_PCH_DN

CLK_DMI_PCH_DP

CLK_DMI_PCH_DN

CLK_PEG_REF_DP

CLK_PEG_REF_DN

CLKREQ_GPU#

2

1

32

1

3

1

21

1

21

1

21

2

1

32

1

3

2 12 1

2 1

21

2 1

21

V49

V47

Y47

M16

E14

C13

G12

C8

A12

C9

H14

E12

K45

AY38

BB40

AV36

BB36

BB34

AU34

AY32

AU32

AW38

AY40

AU36

AY36

AY34

AV34

BB32

AV32

BC38

BJ40

BG38

BH37

BE36

BJ36

BF34

BJ34

BE38

BG40

BJ38

BG37

BF36

BG36

BE34

BG34

E6

M10

K12

T13

L14

L12

A8

V10

M1

J2

K49

H47

F47

K43

AB40

AB42

AB38

AB37

V37

V38

V42

V40

V46

V45

Y45

Y43

Y36

Y37

AA47

AA48

AB47

AB49

Y39

Y40

AK13

AK14

AM13

AM12

AU22

AV22

AK5

AK7

H45

BG30

BJ30

E24

G24

BE18

BF18

P10

T11

M7

OUT

BI

OUT

IN

G

DS

G

DS

OUT

BI

OUT

Link

Controller

SMBUS

FLEX CLOCKS

CLOCKS

PCI-E*

PCIECLKRQ6#/GPIO45

CL_RST1#

CL_DATA1

CL_CLK1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT#/PCHHOT#/GPIO74

SML0DATA

SML0CLK

SML0ALERT#/GPIO60

SMBDATA

SMBCLK

SMBALERT#/GPIO11

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

PCIECLKRQ7#/GPIO46

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_DP_N

CLKOUT_DP_P

XCLK_RCOMP

CLKOUT_PEG_B_N

CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

PCIECLKRQ5#/GPIO44

PCIECLKRQ4#/GPIO26

PCIECLKRQ3#/GPIO25

PCIECLKRQ2#/GPIO20

PCIECLKRQ1#/GPIO18

PCIECLKRQ0#/GPIO73

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKIN_PCILOOPBACK

REFCLK14IN

XTAL25_OUT

XTAL25_IN

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

CLKIN_GND1_P

CLKIN_GND1_N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

PETP8

PETN8

PETP7

PETN7

PETP6

PETN6

PETP5

PETN5

PETP4

PETN4

PETP3

PETN3

PETP2

PETN2

PETP1

PETN1

PERP8

PERN8

PERP7

PERN7

PERP6

PERN6

PERP5

PERN5

PERP4

PERN4

PERP3

PERN3

PERP2

PERN2

PERP1

PERN1

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

BI

G

DS

G

DS

OUT

BI

OUT

IN

OUT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

INT. PU 20K

STRAPPING

INT. PU 20K

INT. PD 20K

DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE

STRAPPING

LOW-DISABLED

HIGH-ENABLED(DEFAULT)

6849

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

330K_5%_2_DY

1K_5%_2_DY

100K_5%_2

750_1%_2

P3V3A

10K_5%_2

P3V3S

P3V3A

BAT54_30V_0.2A

10K_5%_2

P3V3_LDO

P3V3A

8.2K_5%_2

10K_5%_2_DY

P3V3A

10K_5%_2

8.2K_5%_2

10K_5%_2

A3 CS

Block Diagram

P3V3A

49.9_1%_2

0_5%_2

ITL_PANTHERPOINT_FCBGA_989P

0_5%_2_DY

P1V05S

P3V3_LDO

P3V3_RTC

330K_5%_2

P3V3S

10K_5%_2

10K_5%_2_DY

TC7SZ08FU

SSM3K7002BFU

SSM3K7002FU_DY

BAT54_30V_0.2A

U4704

R4710

Q4714

R4883

Q4713

R4832

R4830

R4827

R4826

R4825

R4824

R4823

R4822

D4707

D4706

R4820

R4815 R4816

R4812

R4814

R4828

R4834

R4831

R4829

U4700

42B7

42D7

15B8

15A4

42C7

42B7

42C7

21D6

41C1

49A5

41C7

49C2

21D3

21D1

21D6

49A6

42D7

42C7

42D7

49B3 21E3

42B7

42C7

21B6

42C7

49A5 31C6 27C7 22B5

42C7

49A5

49B7

42D7 42C7

42C7

42B7

49B7

21D6 49A6

27C7

22B5 31C6

49B3

49B7

21B6

49A5

49A6

21B6

11C7

11A4

40B4

14D2 21D3

21D3 21D1

21E3

15B4

41C5

14D2 14B8

13A2 45D3 21D6

14A6 13D2

16A7

SLP_S3#_3R

RSMRST#

FDI_TX6_DN

SUS_PWR_ACK

PM_DRAM_PWRGD

RSMRST#

PM_RI#

ACPRESENT

PCIE_WAKE#

ACPRESENT

DMI_TX2_DP

DMI_TX3_DP

DMI_RX0_DP

DMI_RX1_DP

DMI_RX3_DN

DMI_RX2_DN

DMI_RX1_DN

DMI_RX0_DN

PCI_3S_CLKRUN#

SUS_PWR_ACK

FDI_INT

FDI_TX7_DP

FDI_TX5_DP

FDI_TX4_DP

FDI_TX3_DP

FDI_TX1_DP

EC_32KHZ

FDI_TX0_DP

FDI_TX7_DN

FDI_TX4_DN

FDI_TX5_DN

FDI_TX2_DN

FDI_TX3_DN

FDI_TX0_DN

FDI_TX1_DN

PCIE_WAKE#

PCH_PWROK

SUSACK#

PVCORE_PG PCI_3S_CLKRUN#

FDI_TX2_DP

FDI_FSYNC0

DMI_TX1_DP

DMI_TX0_DP

DMI_TX2_DN

DMI_TX1_DN

DMI_RX2_DP

DMI_RX3_DP

DMI_TX0_DN

DMI_TX3_DN

FDI_TX6_DP

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PM_RI#

PCH_PWROK

SLP_S5#_3R

SLP_S5_3R

SLP_S3_3R

H_PM_SYNC

SLP_SUS#

SLP_S3#_IC_3R

SYS_RESET#

LOW_BAT#_3

EC_PWRSW#

5

4

3

2

1

21

2

1

3

2 12

1

3

2 1

21

2 1

21

2

13

2

13

2 1

21

2 1

21

2 1

21

2 1

B9K3

P12

K16

N14

C12

G8

G16

D10

H4

F4

K14

G10

C21

A10

L22

E20

AP14

BH9

BJ10

BG12

BE12

BG13

BF14

BB14

BG14

BG9

BG10

BJ12

BC12

BH13

BE14

AY14

BJ14

BB10

AV14

AW16

BC10

AV12

A18

B13

E22

BJ24

BG25

AU18

AV18

BJ20

BG20

AY18

BB18

BJ18

BG18

BH21

AY20

AW20

BC20

BE20

AY24

AW24

BE24

BC24

N3

E10

L10

H20

IN

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

+-

G

DS

OUT

G

DS

IN

OUT

IN

OUT

System Power Management

FDI

DMI

SUSACK#

DSWVRMEN

SLP_A#

DMI2RBIAS

DPWROK

APWROK

SLP_LAN#/GPIO29

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

CLKRUN#/GPIO32

PWROK

BATLOW#/GPIO72

ACPRESENT/GPIO31

SUSCLK/GPIO62

SUS_STAT#/GPIO61

WAKE#

RI#

PWRBTN#

SYS_PWROK

SYS_RESET#

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_SUS#

PMSYNCH

FDI_INT

FDI_LSYNC1

FDI_LSYNC0

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

FDI_RXN0

DMI_IRCOMP

DMI_ZCOMP

DMI3TXP

DMI2TXP

DMI1TXP

DMI0TXP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

DMI3RXN

DMI2RXN

DMI1RXN

DMI0RXN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CLOSE TO PCH

REFERENCE 4700~4949(PCH)

WHEN ¡¥1¡¦- LVDS IS DETECTED

HIGH-LVDS ENABLED

PCH_LVDS_DDCDATA - LVDS DETECT

LOW-LVDS DISABLED (DEFAULT)

6850

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

150_1%_2

ITL_PANTHERPOINT_FCBGA_989P

2.37K_1%_2

1K_1%_2

Block Diagram

CS

A3

100K_5%_2

P3V3S

2.2K_5%_22.2K_5%_2

150_1%_2

R4857R4856

R4858

R4855

R4861

R4860

R4859

R4862

U4700

35D8

35B2

35D8

35A2

36B5

36A5

34D7

34B5

21E7

34B8

34C5

34B8

34C5

34B8

36A5

36D8

PCH_CRT_VSYNC

PCH_CRT_HSYNC

PCH_CRT_DDCCLK

PCH_CRT_DDCDATA

PCH_CRTR

PCH_CRTG

PCH_CRTB

PCH_HDMI_DDCDATA

PCH_LVDS_DDCCLK

PCH_LVDS_DDCDATA

PCH_LVDS_TXCL_DN

PCH_LVDS_TXCL_DP

PCH_LVDS_TXDL0_DN

PCH_LVDS_TXDL0_DP

PCH_LVDS_TXDL1_DP

PCH_LVDS_TXDL2_DP

PCH_LCM_VDDEN

PCH_INV_PWM_3

PCH_LCM_BKLTEN

PCH_LVDS_TXDL1_DN

PCH_LVDS_TXDL2_DN

PCH_HDMI_DDCCLK

PCH_HPDET

PCH_HDMI_TX2_DP

PCH_HDMI_TX1_DN

PCH_HDMI_TX1_DP

PCH_HDMI_TX0_DN

PCH_HDMI_TX0_DP

PCH_HDMI_TXC_DN

PCH_HDMI_TXC_DP

PCH_HDMI_TX2_DN

2 1

21

2 1

21

2 1

AP45

AP43

AM40

AM42

AP40

AP39

M39

P38

AF43

AF47

AH49

AH43

AF45

AF49

AH47

AH45

AF40

AF39

AJ47

AK49

AM49

AN47

AJ48

AK47

AM47

AN48

AK39

AK40

AE47

AE48

AF36

AF37

M45

K47

T40

P39

T45

J47

P45

BH41

M36

M43

AT43

AT45

BG42

BJ42

BE42

BF42

BE44

BF44

BB45

BB43

AT38

P42

P46

AP49

AP47

BB49

BB47

BA48

BA47

AY45

AY43

AY49

AY47

AT40

AT47

AT49

AV49

AV47

AU47

AU48

AV46

AV45

AV40

AV42

T43

M49

T49

T42

M47

P49

M40

T39

N48

OUT

IN

OUT

BI

OUT

BI

OUT

CRT

Digital Display Interface

LVDS

SDVO_INTN

SDVO_INTP

SDVO_STALLN

SDVO_STALLP

SDVO_TVCLKINN

SDVO_TVCLKINP

DDPD_HPD

DDPC_HPD

DDPB_HPD

DDPD_AUXP

DDPC_AUXP

DDPB_AUXP

DDPD_AUXN

DDPC_AUXN

DDPB_AUXN

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_CTRLDATA

DDPC_CTRLCLK

SDVO_CTRLDATA

SDVO_CTRLCLK

DAC_IREF

CRT_VSYNC

CRT_RED

CRT_IRTN

CRT_HSYNC

CRT_GREEN

CRT_DDC_DATA

CRT_DDC_CLK

CRT_BLUE

DDPD_1P

DDPD_0P

DDPC_3P

DDPC_2P

DDPC_0P

DDPC_1P

LVD_VBG

LVD_IBG

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

DDPB_3P

DDPB_2P

DDPD_3P

DDPD_2P

DDPB_1P

DDPB_0P

DDPD_1N

DDPD_0N

DDPC_3N

DDPC_2N

DDPC_1N

DDPC_0N

DDPB_3N

DDPB_2N

DDPD_3N

DDPD_2N

LVD_VREFL

LVD_VREFH

DDPB_1N

DDPB_0N

LVDSB_DATA0

LVDSB_DATA#3

LVDSB_DATA#2

LVDSB_DATA#1

LVDSB_DATA#0

LVDSB_CLK

LVDSB_CLK#

LVDSA_DATA3

LVDSA_DATA2

LVDSA_DATA1

LVDSA_DATA0

LVDSA_DATA#3

LVDSA_DATA#2

LVDSA_DATA#1

LVDSA_DATA#0

LVDSA_CLK

LVDSA_CLK#

L_VDD_EN

L_DDC_DATA

L_DDC_CLK

L_CTRL_DATA

L_CTRL_CLK

L_BKLTEN

L_BKLTCTL

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

TOP-BLOCK SWAP OVERRIDE

LOW=A16 SWAP OVERRIDE

STP_A16OVR

USED AS GPIO ONLY.

INT. PU 20K

TO BE USED AS GPIO

HIGH=DEFAULT

BBS STRAPING

WEBCAM

P0.P1 RESERVER FOR USB3.0

USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2

DEBUG PORT

NOTE:10K_5%(60130B1030ZT)

------

BOOT BIOS

DESTINATION

LPC

1

1 0

00

RESERVED(NAND)

BBS_BIT0

GPIO19

0

BBS_BIT1

GPIO51

REFERENCE 4700~4949(PCH)

1 1 SPI (DEFAULT)

ROUTE WITH 90 OHMS IMPEDANCE

TOTAL LENGTH NO LONGER THAN 11 INCHES

NOTE:

3G

CLOSE TO PCH

CARD READER

WLAN

6851

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

ITL_PANTHERPOINT_FCBGA_989P

100K_5%_2

22_5%_2

22.6_1%_3

P3V3A

P3V3S

TC7SZ08FU

10K_5%_2

TP24

10K_5%_2_DY

1K_5%_2_DY

8.2K_5%_2

10K_5%_2_DY

1K_5%_2_DY

10K_5%_2_DY

A3 CS

Block Diagram

10K_5%_2

8.2K_5%_2

10K_5%_2

8.2K_5%_2

10K_5%_2

P3V3A

10K_5%_2

R4838

R4882

R4881

R4880

R4879

R4956

R4897

R4896

R4895

R4894

R4893

R4892

R4899

R4898

TP4717

U4705

R4887

R4888

R4891

R4890

R4889

R4885 R4886

R4878

R4877

R4876

R4875

R4874

R4907

R4906

R4905

R4904

R4903

R4902

R4901

R4900

R4835

U4700

66C6

57A6

34B3

27B3

26A8

28C3

51A2

31C6

32D7

51B6

36B2

21E3 28C3

27C7

51B7

51B6

52D6

21E3

16A3

51C7

51A5

32B8

33C5

32D7

51B6

51C7

51B6

51C7

32D7

51A5

51A2

51D7

32C8

27C7

28C3

33C5

30C5

51A4

33B5

32D7

48A3

21E3

51A2 51A4

51A4

51A2

51A5

51A2

51A5

51A2

51A5

51A2

51A5

30C5

51A4

51A4 51A5

51A4

31C6

41C7

31C7

51C7

51B6

29A5

51C7

16A3

51C7

57A6

27C3

29A5

33B5

51B6

MACHINE_ID2

CLK_PCI_DEBUG_R

USB_CAM_DN

USB_CAM_DP

USB_CR_DN

USB_CR_DP

USB_WLAN_DN

USB_WLAN_DP

USB_P2_DP

USB_P2_DN

USB_3G_DP

USB3_SMI#

BUF_PLT_RST#

MACHINE_ID0

MACHINE_ID1

MACHINE_ID2

MACHINE_ID6

MACHINE_ID5

MACHINE_ID4

MACHINE_ID3

CLK_KBPCI

CLKIN_PCI_FB

CLK_PCI_DEBUG

SATA_ODD_DA#

CLK_PCI_FB_R

P3V3A_PME#

PLT_RST#

CLK_KBPCI_R

MACHINE_ID4

MACHINE_ID3

SATA_ODD_DA#

USB_P0_DN

USB3_PCH_RX1_DN

USB3_PCH_RX2_DN

USB3_PCH_RX2_DP

USB3_PCH_TX2_DP

USB3_PCH_RX1_DP

USB_P1_DP

MACHINE_ID0

BBS_BIT1

USB_P0_DP

USB_P1_DN

RUNSCI0#_3

PCI_3S_INTD#

PCI_3S_INTC#

PCI_3S_INTB#

PCI_3S_INTA#

MACHINE_ID1_DB

MACHINE_ID0

MACHINE_ID4

MACHINE_ID5

MACHINE_ID6

MACHINE_ID1_DB

MACHINE_ID1

MACHINE_ID2

MACHINE_ID3

MACHINE_ID1_DB

MACHINE_ID6

MACHINE_ID5

MACHINE_ID1

USB_3G_DN

PCI_3S_REQ2#

DGPU_PWR_EN#

PCI_3S_PIRQG#

STP_A16OVR

PCI_3S_PIRQH#

USB3_PCH_TX1_DP

USB3_PCH_TX1_DN

USB3_PCH_TX2_DN

DGPU_HOLD_RST#

PCI_3S_INTA#

PCI_3S_INTB#

PCI_3S_INTC#

PCI_3S_INTD#

DGPU_HOLD_RST#

PCI_3S_REQ2#

DGPU_PWR_EN#

PCI_3S_PIRQH#

PCI_3S_PIRQG#

21

1

5

4

3

2

1

21

21C33

B33

E30

G30

K30

L30

M28

N28

B29

C29

A28

C28

D28

E28

H28

K28

A26

C26

B25

C25

A32

C32

E32

G32

K32

L32

A30

C30

A24

C24

AK45

AK43

AH37

AH38

BG16

AW30

BJ16

AV28

AY26

AU26

AY30

AU28

BB26

AV26

BG32

BF32

BE30

BH25

BC28

BJ32

BE32

BC30

BE28

BG46

AY16

M20

B21

AB45

BJ26

AB46

L24

K24

Y13

AM5

AM4

AH12

H3

N30

C18

BG26

AT3

AT4

AU2

BC8

AT10

BG4

AU3

BF3

AT12

BA2

AY5

AT8

AV10

AV5

BF6

BD4

BE8

AV7

BB7

BB3

BB5

BA3

BB1

AV1

AV3

AT5

AY3

AT1

AY7

E40

C44

C46

K10

C6

D44

C42

G40

G42

G38

H38

K38

K40

C14

D14

A16

L16

C16

B17

K20

A14

F46

E42

D47

H40

K42

J48

H43

H49

IN

BI

OUT

BI

OUT

BI

OUT

BI

OUT

IN

BI

IN

BI

IN

BI

+-

OUT

BI

USB

PCI

NVRAM

RSVD

TP24

TP10

TP11

TP12

TP13

TP14

TP15

TP5

TP4

USB3TP4

USB3TP3

USB3TP2

USB3TP1

USB3TN4

USB3TN3

USB3TN2

USB3TN1

USB3RP4

USB3RP3

USB3RP2

USB3RP1

USB3RN4

USB3RN3

USB3RN2

USB3RN1

TP23

TP22

TP21

TP20

TP19

TP18

TP17

TP16

TP9

TP8

TP7

TP6

TP3

TP2

TP1

PLTRST#

CLKOUT_PCI3

CLKOUT_PCI4 OC7#/GPIO14

OC6#/GPIO10

OC5#/GPIO9

OC4#/GPIO43

OC3#/GPIO42

OC2#/GPIO41

OC1#/GPIO40

OC0#/GPIO59

USBRBIAS

USBRBIAS#

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI0

PME#

USBP13P

USBP13N

USBP12P

USBP12N

USBP11P

USBP11N

USBP10P

USBP10N

USBP9P

USBP9N

USBP8P

USBP8N

USBP7P

USBP7N

USBP6P

USBP6N

USBP5P

USBP5N

USBP4P

USBP4N

USBP3P

USBP3N

USBP2P

USBP2N

USBP1P

USBP1N

USBP0P

USBP0N

PIRQH#/GPIO5

PIRQG#/GPIO4

PIRQF#/GPIO3

PIRQE#/GPIO2

GNT3#/GPIO55

GNT2#/GPIO53

GNT1#/GPIO51

REQ3#/GPIO54

REQ2#/GPIO52

REQ1#/GPIO50

PIRQD#

PIRQC#

PIRQB#

PIRQA#

RSVD29

RSVD28

RSVD27

RSVD26

RSVD24

RSVD25

RSVD16

RSVD15

RSVD14

RSVD13

RSVD12

RSVD11

RSVD10

RSVD9

RSVD22

RSVD21

RSVD20

RSVD19

RSVD18

RSVD17

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD23

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

FDI_OVRVLTG(GPIO37)

LOW- TX,RXTERMINATED TO SAME VOLTAGE

GFX_CRB_DET(GPIO39)

STRAPPING

INTERNAL GFX :100K PD

EXTERNAL GFX :10K PU

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)

(DC COUPLING MODE) DEFAULT

STRAP

BOTH THESE SHOULD BE CLOSE TO PCH

STRAPPING

INT. PU 20K

INT. PD 20K

LOW-DISABLED

HIGH-ENABLED (DEFAULT)

STRAPPING

FOLLOW EDS1.0

STRAPPING

INT.PD 20K

INT. PD 20K

STRAPPING

REFERENCE 4700~4949(PCH)

6852

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

10K_5%_2_DY

P3V3S

10K_5%_2_DY

10K_5%_2

10K_5%_2_DY

1K_5%_2_DY

10K_5%_2

P3V3A

10K_5%_2_DY

100K_5%_2

56_5%_2

0_5%_2_DY

10K_5%_2_DY

TP24

P1V05S

ITL_PANTHERPOINT_FCBGA_989P

P3V3S

P1V05S

56_5%_2

0_5%_2_DY

390_5%_2

Block Diagram

CS

A3

10K_5%_2_DY

100K_5%_2

P3V3S

10K_5%_2

P3V3A

1K_5%_2_DY

P3V3S

10K_5%_2_DY

P3V3S

33K_5%_2_DY

10K_5%_2_DY

P3V3S

R4909

R4721

R4919

R4727

R4726

R4725

R4724

R4917

R4929

R4927

R4916

R4915

R4908

R4935

R4950

R4932

TP4907

R4936

R4934

R4926

R4920

R4910

R4944

R4943

R4942

R4941

R4940

R4930

R4928

U4700

52C6

29A5

52B6

52C6

52B6

52C7

13B2

52D7

52C6

51C7

52D7

52C7

52D7

52A7

52D7

52C6

52D6

52C6

13C8

52D7

52D7 29A5

27B7

28C2

52B6

52C6

52B6

29B8

21E2

41D5

40A4

41D5 21A6

21D2

41C5

41D6

52B7

27C7

52D7

21E3

PCH_GPIO37

SATA_ODD_PRSNT#

PCH_GPIO16

PCH_GPIO38

PCH_GPIO22

KBLED_ID

DGPU_PWRGD

PCH_GPIO16

PCH_GPIO15

PCH_GPIO12

PCH_GPIO8

RUNSCI0#_3

PCH_GPIO6

3G_ON#

MSATA_DET

PLL_ODVR_EN

PCH_GPIO39

PCH_GPIO8

PCH_GPIO15

PCH_GPIO12

PCH_GPIO6

PCH_GPIO22

SATA_ODD_PRSNT#

BTIFON#

NV_CLE

H_CPUPWRGD

KBRST#

H_PECI

EC_3S_A20GATE

PCH_GPIO38

PCH_PECI

THRMTRIP#_R

SATA_ODD_PWREN

PM_THRMTRIP#

PCH_GPIO39

PCH_GPIO37

PLL_ODVR_EN

21

1

21

2 1

21

2 1

21

BD1

B47

B3

A6

A5

A46

F49

F1

E49

A45

E1

D49

D1

C48

C2

BJ6

BJ5

BJ46

BJ45

BJ44A44

BJ4

BH47

BH3

BG48

BG2

BF49

BF1

BE49

BE1

BD49

A4

AK10

AH10

AK11

AH8

AY10

A40

C41

B41

C40

E38

H36

A42

D40

K1

N2

V13

M3

T5

V3

U2

M5

V8

P5

AY11

AU16

AY1

P37

C4

T14

C10

D6

K4

P8

E16

E8

G2

T7

P4

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GPIO

NCTF

CPU/MISC

DF_TVS

VSS_NCTF_16

VSS_NCTF_15

VSS_NCTF_14

VSS_NCTF_13

NC_1

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_31

VSS_NCTF_30

VSS_NCTF_29

VSS_NCTF_28

VSS_NCTF_27

VSS_NCTF_26

VSS_NCTF_25

VSS_NCTF_24

VSS_NCTF_23

VSS_NCTF_22

VSS_NCTF_21

VSS_NCTF_20

VSS_NCTF_19

VSS_NCTF_18

VSS_NCTF_17

TACH5/GPIO69

TACH7/GPIO71

TACH6/GPIO70

TACH4/GPIO68

A20GATE

VSS_NCTF_32

SATA4GP/GPIO16

GPIO35

STP_PCI#/GPIO34

INIT3_3V#

SATA2GP/GPIO36

TACH1/GPIO1

GPIO15

BMBUSY#/GPIO0

GPIO8

THRMTRIP#

PECI

RCIN#

PROCPWRGD

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SLOAD/GPIO38

SCLOCK/GPIO22

SATA5GP/GPIO49/TEMP_ALERT#

SATA3GP/GPIO37

TACH3/GPIO7

TACH0/GPIO17

TACH2/GPIO6

VSS_NCTF_12

VSS_NCTF_11

VSS_NCTF_10

VSS_NCTF_9

VSS_NCTF_8

VSS_NCTF_7

VSS_NCTF_6

VSS_NCTF_5

VSS_NCTF_4

VSS_NCTF_3

VSS_NCTF_2

VSS_NCTF_1

LAN_PHY_PWR_CTRL/GPIO12

GPIO57

GPIO24

GPIO28

GPIO27

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

3A

20MIL

15MIL

40MIL

1.3A

REFERENCE 4700~4949(PCH)

15MIL

20MIL

15MIL

6853

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

P3V3S

P1V8S

P3V3S

P1V05S

P1V8S

P1V5S_VCCAFDI_VRM

P1V05S

P3V3AP3V3AL

P1V5SP1V5S_VCCAFDI_VRM

P1V05S

P1V5S_VCCAFDI_VRM

P3V3S

P1V05S

FBM_11_160808_121T

0.1UF_16V_2

0.01UF_50V_2

10UF_6.3V_3

FBM_11_160808_121T

22UF_6.3V_5

1UF_6.3V_2

Block Diagram

CS

0.1UF_16V_2

0_5%_2

A3

0.01UF_50V_20.01UF_50V_2

0.1UF_16V_2

1UF_6.3V_2

1UF_6.3V_2_DY

0_5%_2_DY

0_5%_3

ITL_PANTHERPOINT_FCBGA_989P

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

10UF_6.3V_3

0_5%_2_DY

1UF_6.3V_2

0_5%_2_DY

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

0.1UF_16V_2

10UF_6.3V_3

R4949

C4792

R4948

R4947

C4791

C4790

C4789

C4788

C4785 C4786 C4787

L4701

C4782 C4783 C4784

L4700

R4946

C4781

C4780

C4776 C4777 C4778 C4779

R4945

C4775C4774C4773C4772

U4700

P1V05S_VCCAPLLEXP

P1V8S_VCCTX_LVDS

P3V3S_VCCADAC

P1V05S_VCCAFDIPLL

21

2 1

21

2 1

21

2 1

21

2 1

21

2 1

21

2 1

AK37

U47

AT16

AP16

AP37

AP36

AM38

AM37

V1

AN19

AP17

AN34

AN33

AT24

AP26

AP24

AP23

AP21

AN27

AN26

AN21

AN17

AN16

AU20

AT20

AJ17

AJ16

AG17

AG16

AG24

AG23

AG21

AF23

AF21

AD23

AD21

AC23

AJ31

AJ29

AJ27

AJ26

AJ23

AG29

AG27

AG26

AA23

AB36

BJ22

AK36

BG6

U48

V34

V33

BH29

LVDS

FDI

POWER

VCC CORE

CRT

DMI HVCMOS

VCCIO

NAND / SPI

VCCCORE[12]

VCCCORE[13]

VCCCORE[14]

VCCCORE[15]

VCCIO[28]

VCCIO[15]

VCCCORE[17]

VCCCORE[16]

VCCCORE[11]

VCCCORE[10]

VCCCORE[9]

VCCCORE[8]

VCCCORE[7]

VCCCORE[6]

VCCCORE[5]

VCCCORE[4]

VCCCORE[2]

VCCCORE[1]

VCCCORE[3]

VCCSPI

VCCVRM[2]

VccAFDIPLL

VCCDFTERM[4]

VCCDFTERM[3]

VCCADAC

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCALVDS

VCCVRM[3]

VCCAPLLEXP

VCCTX_LVDS[4]

VCCTX_LVDS[3]

VSSADAC

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCC3_3[3] VCCDFTERM[2]

VCCDFTERM[1]

VCCDMI[1]

VCCCLKDMI

VCCDMI[2]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCCIO[27]

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

20MIL

10MIL

20MIL

10MIL

20MIL

10MIL

15MIL

1.1A

15MIL

20MIL

15MIL

20MIL

REFERENCE 4700~4949(PCH)

3A

10MIL

20MIL

10MIL

15MIL

10MIL

20MIL

10MIL

6854

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

0.1UF_16V_2

10_5%_5

P3V3A

1UF_6.3V_21UF_6.3V_2

P1V05S

1UF_6.3V_2_DY

0_5%_2_DY

22UF_6.3V_5

1UF_6.3V_2

BAT54_30V_0.2A

1UF_6.3V_2

P3V3S

1UF_6.3V_2

P1V05S

P3V3A

1UF_6.3V_2

P3V3A

P1V05S

1UF_6.3V_2

0.1UF_16V_2

P1V05S

4.7UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2

1UF_6.3V_2_DY

P1V05S

10UF_6.3V_3

22UF_6.3V_5_DY 1UF_6.3V_2

P1V05S

FBM_11_160808_121T

22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3

P1V05S

0.1UF_16V_2

P3V3_RTC

22UF_6.3V_5

1UF_6.3V_2 0.1UF_16V_2

0.1UF_16V_2

1UF_6.3V_2

P1V5S_VCCAFDI_VRM

0.1UF_16V_2

P3V3S

10UF_6.3V_3

P1V05S

0.1UF_16V_2

0.1UF_16V_2_DY

P1V05S

0_5%_2_DY

0_5%_2

ITL_PANTHERPOINT_FCBGA_989P

P3V3A

0.1UF_16V_2

P1V05S

1UF_6.3V_2

0603_DY

1UF_6.3V_2_DY

P3V3A

A3

P1V05S

P1V5S_VCCAFDI_VRM

CS

Block Diagram

P1V05S

P5V0S

P3V3S

0.1UF_16V_2

10_5%_5

P3V3A

P5V0A

P3V3A

C4835

C4834

C4829

C4841

C4840

L4708

C4839

C4838

C4837

C4836

R4870

D4709

C4832

C4833

R4869

D4708

C4831

C4830

C4827C4826 C4828

C4825C4824C4823

C4822

C4821

C4820

C4819

C4818

C4812

C4815

L4707

C4816 C4817

C4814C4813

L4706

C4811

C4810C4809C4808

C4807C4806

C4805

R4867

C4802C4801

R4866

C4803

C4804

R4865 U4700

P1V05S_VCCAPLLDMI2

V5REF_SUS

V5REF

P1V05S_VCCADPLLB

P1V05S_VCCADPLLA

P1V05S_VCCACLK

P1V05S_VCCAPLLSATA

21

2 1

21

2

13

2 1

21

2

13

21

2 1

21

2 1

2 12 1

21

2 1

2 1 2 1

2 1

21

2 1

21

2 1

212 1

2 1

21

Y49

AF11

P32

V23

T24

T23

P24

P22

P20

N22

N20

V24

AN24

AG33

A22

AF17

AF14

AF13

AD17

T26

T29

T27

P28

P26

AC17

N26

AC16

AL29

AH14

AH13

T16

AG34

AF34

AF33

AC27

AC26

AA31

AA29

AA27

AA26

AA24

V21

T21

T19

W33

AA21

W31

W29

W26

W24

W23

W21

AD31

AD29

AC31

AC29

AA19

AK1

BH23

BF47

BD47

AD49

W16

T38

T34

AJ2

AA16

BJ8

M26

P34

V12

AN23

AL24

V19

T17

V16

N16

NC NC

HDA

CPU

RTC

PCI/GPIO/LPCMISC

POWER

USB

Clock and Miscellaneous

SATA

VCCVRM[4]

DCPRTC

VCCASW[20]

VCC3_3[2]

VCCASW[18]

VCCASW[15]

VCCASW[19]

VCCIO[5]

VCCASW[17]

VCCASW[16]

VCCASW[1]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCASW[2]

VCCIO[29]

VCCAPLLDMI2

VCCASW[4]

DCPSUSBYP

VCCASW[3]

VCCASW[5]

VCCASW[6]

VCCSUSHDA

VCCSUS3_3[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

V5REF

VCC3_3[4]

VCCRTC

VCCSUS3_3[10]

VCCSUS3_3[9]

VCCSUS3_3[8]

VCCSUS3_3[7]

VCCADPLLB

VCCDIFFCLKN[1]

DCPSUS[1]

VCCSSC

VCCADPLLA

VCCACLK

VCCDIFFCLKN[2]

DCPSST

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCC3_3[1]

VCC3_3[8]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

V_PROC_IO

VCCDIFFCLKN[3]

VCCASW[13]

VCCASW[14]

VCCVRM[1]

VCCAPLLSATA

DCPSUS[3]

DCPSUS[2]

VCCDSW3_3

VCC3_3[5]

VCCIO[14]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCIO[7]

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

6855

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

Block Diagram

CS

A3

ITL_PANTHERPOINT_FCBGA_989P

U4700

BJ28

BG28

BC16

BE16

AP1

AP3

M14

AP13

C22

BG24

BG22

T36

H16

G14

BG41

BE10

B43

AD47

AJ3

N24

BG29

Y8

Y46

Y42

Y4

Y38

Y12

W48

W27

W2

W19

W17

V7

V43

V39

V36

V31

V29

V27

V26

V17

V11

T8

T47

T46

W34

T4

T37

T31

T12

R48

R2

P7

P47

P43

P40

T33

P18

P11

N47

P30

N18

M8

M46

M42

M4

M38

M34

M32

M30

M24

M22

M18

P16

M12

L48

L36

L28

L26

L20

L2

L18

K7

K46

K39

K26

K18

H46

F3

H34

H32

H30

H26

H24

H22

H18

H12

G48

G36

G28

G26

G20

G18

E26

E18

D8

D42

D38

D34

D32

D30

D26

D24

D22

D18

D16

D12

D3

BH7

BH43

BH39

BH35

BH33

BH31

BH27

H10

BH19

BH17

BH15

BH11

BG8

BG44

BG33

BG21

BG17

BF8

BF40

BF38

BF30

BD3

BF28

BF26

BF24

BF22

BF20

BF16

BF12

BF10

BE40

BE26

BE22

BD5

BD46

BC48

BC42

BC40

BC36

BC34

BC32

BC26

BC22

BC2

BC18

BC14

BB46

BB4

BB38

BB30

BB28

BB24

BB22

BB20

BB16

BB12

F45

B7

B39

B35

B31

B27

B23

B19

B15

B11

AY8

AY46

AY42

AY4

AM36

AM14

AM11

AL48

AL34

AL33

AL31

AL27

AL26

AL23

AB4

AL21

AL2

AL19

AL17

AL16

AK8

AK46

AK42

AK4

AK38

AB39

AK3

AK12

AJ34

AJ33

AJ24

AJ21

AJ19

AH7

AH46

AH42

AB14

AH40

AH39

AH36

AH3

AH11

AG48

AG31

AG2

AG19

AF8

AB11

AF7

AF5

AF46

AF42

AF4

AF38

AF31

AF29

AF27

AF26

AA34

AF24

AF19

AF16

AD16

AD14

AF12

AF10

AE3

AE2

AD8

AA33

AD46

AD45

AD43

AD42

AD40

AD4

AD39

AD38

AD37

AD36

AA3

AD34

AD33

AD27

AD26

AD24

AD19

AD13

AD12

AD11

AD10

AA2

AC48

AC34

AC33

AC24

AY28

AY22

AY12

AV11

AW48

AW40

AW36

AW34

AW32

AC21

AW28

AW26

AW22

AW2

AW18

AW14

AV8

AV43

AV4

AV38

AC2

AV30

AV24

AV20

AV16

AU30

AU24

AT7

AT46

AT42

AT39

AC19

AT34

AT32

AT30

AT28

AT26

AT22

AT18

AT13

AT11

AR48

AB7

AR2

AP8

AP46

AP42

AP4

AP38

AP32

AP30

AP28

AP19

AB5

AP12

AN31

AN3

AN29

AN2

AM7

AM46

AM45

AM43

AM39

AB43

AA17

H5

VSS[352]

VSS[351]

VSS[350]

VSS[349]

VSS[348]

VSS[347]

VSS[346]

VSS[345]

VSS[344]

VSS[343]

VSS[342]

VSS[340]

VSS[338]

VSS[337]

VSS[335]

VSS[334]

VSS[333]

VSS[331]

VSS[330]

VSS[329]

VSS[328]

VSS[325]

VSS[324]

VSS[323]

VSS[322]

VSS[321]

VSS[320]

VSS[319]

VSS[318]

VSS[317]

VSS[316]

VSS[315]

VSS[314]

VSS[313]

VSS[312]

VSS[311]

VSS[310]

VSS[309]

VSS[308]

VSS[307]

VSS[306]

VSS[305]

VSS[304]

VSS[303]

VSS[302]

VSS[301]

VSS[300]

VSS[299]

VSS[298]

VSS[297]

VSS[296]

VSS[295]

VSS[294]

VSS[293]

VSS[292]

VSS[291]

VSS[290]

VSS[289]

VSS[288]

VSS[287]

VSS[286]

VSS[285]

VSS[284]

VSS[283]

VSS[282]

VSS[281]

VSS[280]

VSS[279]

VSS[278]

VSS[277]

VSS[276]

VSS[275]

VSS[274]

VSS[273]

VSS[272]

VSS[271]

VSS[270]

VSS[269]

VSS[268]

VSS[267]

VSS[266]

VSS[265]

VSS[264]

VSS[263]

VSS[262]

VSS[261]

VSS[260]

VSS[259]

VSS[258]

VSS[257]

VSS[256]

VSS[255]

VSS[254]

VSS[253]

VSS[252]

VSS[251]

VSS[250]

VSS[249]

VSS[248]

VSS[247]

VSS[246]

VSS[245]

VSS[244]

VSS[243]

VSS[242]

VSS[241]

VSS[240]

VSS[239]

VSS[238]

VSS[237]

VSS[236]

VSS[235]

VSS[234]

VSS[233]

VSS[232]

VSS[231]

VSS[230]

VSS[229]

VSS[228]

VSS[227]

VSS[226]

VSS[225]

VSS[224]

VSS[223]

VSS[222]

VSS[221]

VSS[220]

VSS[219]

VSS[218]

VSS[217]

VSS[216]

VSS[215]

VSS[214]

VSS[213]

VSS[212]

VSS[211]

VSS[210]

VSS[209]

VSS[208]

VSS[207]

VSS[206]

VSS[205]

VSS[204]

VSS[203]

VSS[202]

VSS[201]

VSS[200]

VSS[199]

VSS[198]

VSS[197]

VSS[196]

VSS[195]

VSS[194]

VSS[193]

VSS[192]

VSS[191]

VSS[190]

VSS[189]

VSS[188]

VSS[187]

VSS[186]

VSS[185]

VSS[184]

VSS[183]

VSS[182]

VSS[181]

VSS[180]

VSS[179]

VSS[178]

VSS[177]

VSS[176]

VSS[175]

VSS[174]

VSS[173]

VSS[172]

VSS[171]

VSS[170]

VSS[169]

VSS[168]

VSS[167]

VSS[166]

VSS[165]

VSS[164]

VSS[163]

VSS[162]

VSS[161]

VSS[160]

VSS[159]

VSS[158]

VSS[157]

VSS[156]

VSS[155]

VSS[154]

VSS[153]

VSS[152]

VSS[151]

VSS[150]

VSS[149]

VSS[148]

VSS[147]

VSS[146]

VSS[145]

VSS[144]

VSS[143]

VSS[142]

VSS[141]

VSS[140]

VSS[139]

VSS[138]

VSS[137]

VSS[136]

VSS[135]

VSS[134]

VSS[133]

VSS[132]

VSS[131]

VSS[130]

VSS[129]

VSS[128]

VSS[127]

VSS[126]

VSS[125]

VSS[124]

VSS[123]

VSS[122]

VSS[121]

VSS[120]

VSS[119]

VSS[118]

VSS[117]

VSS[116]

VSS[115]

VSS[114]

VSS[113]

VSS[112]

VSS[111]

VSS[110]

VSS[109]

VSS[108]

VSS[107]

VSS[106]

VSS[105]

VSS[104]

VSS[103]

VSS[102]

VSS[101]

VSS[100]

VSS[99]

VSS[98]

VSS[97]

VSS[96]

VSS[95]

VSS[94]

VSS[93]

VSS[92]

VSS[91]

VSS[90]

VSS[89]

VSS[88]

VSS[87]

VSS[86]

VSS[85]

VSS[84]

VSS[83]

VSS[82]

VSS[81]

VSS[80]

VSS[79]

VSS[78]

VSS[77]

VSS[76]

VSS[75]

VSS[74]

VSS[73]

VSS[72]

VSS[71]

VSS[70]

VSS[69]

VSS[68]

VSS[67]

VSS[66]

VSS[65]

VSS[64]

VSS[63]

VSS[62]

VSS[61]

VSS[60]

VSS[59]

VSS[58]

VSS[57]

VSS[56]

VSS[55]

VSS[54]

VSS[53]

VSS[52]

VSS[51]

VSS[50]

VSS[49]

VSS[48]

VSS[47]

VSS[46]

VSS[45]

VSS[44]

VSS[43]

VSS[42]

VSS[41]

VSS[40]

VSS[39]

VSS[38]

VSS[37]

VSS[36]

VSS[35]

VSS[34]

VSS[33]

VSS[32]

VSS[31]

VSS[30]

VSS[29]

VSS[28]

VSS[27]

VSS[26]

VSS[25]

VSS[24]

VSS[23]

VSS[22]

VSS[21]

VSS[20]

VSS[19]

VSS[18]

VSS[17]

VSS[16]

VSS[15]

VSS[14]

VSS[13]

VSS[12]

VSS[11]

VSS[10]

VSS[9]

VSS[8]

VSS[7]

VSS[6]

VSS[5]

VSS[4]

VSS[3]

VSS[2]

VSS[1]

VSS[0]

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

I=125MA TRACE WIDTH>=15MIL

I=70MA TRACE WIDTH>=15MIL

PIN BASE STRAPS

TRANSMITTER POWER SAVING ENABLEGPIO_0

0

MEM_ID0

10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED

MEMORY APERTURE SIZE

0

0 : 50% TX OUTPUT SWING (DEFAULT)

1 : FULL TX OUTPUT SWING

11 : AUDIO FOR BOTH DP AND HDMI

0 : DISABLE (DEFAULT)

ENABLE EXTERNAL BIOS ROM DEVICE 1 : ENABLE

00 : NO AUDIO FUNCTION

01 : AUDIO FOR DP ONLY

1

0

MEMORY APERTURE SIZE

GPIO_9

GPIO_8

GPIO_21

VGA DISABLE

1

GPIO_12

GPIO_13

0

1

GPIO_[11:13]

I=20MA TRACE WIDTH>=15MIL

32M

128M

256M

64M

I=75MA TRACE WIDTH>=15MIL

GPIO_1 PCIE TRANSMITTER DE-EMPHASIS 0 : DE-EMPHASIS DISABLED (DEFAULT)

1 : DE-EMPHASIS ENABLED

GPIO_11

0

MUST BE LOW DURING RESET

GEN1/GEN2 ENABLE

LEFT UNCONNECTED

GPIO_2

0 : ENABLE (DEFAULT)

AUDIO[1:0]

VSYNC[0]

HSYNC[1]

GPIO_22

1 : DISABLE

0 : GEN1 (DEFAULT)

1 : GEN2

GPIO11:MEMORY APERTURE SIZE 256M 0

MEM_ID3

0

SAMSUNG

HYNIX0

MEM_ID1

1

0

MEM_ID2

PLACE CLOSE TO ASIC

I=100MA TRACE WIDTH>=15MIL

THAMES (6019B0917601)

56 68

MODEL,PROJECT,FUNCTION

X01

XXX 21-OCT-2002

1310xxxxx-0-0

P1V8S_DGPU

FBM_11_160808_121T

150_1%_2

10UF_6.3V_3

AMD_216_0833002_FCBGA_962P

10K_5%_2

P3V3S_DGPU

10K_5%_2_DY

249_1%_2

12PF_50V_2

10K_5%_2_DY

10K_5%_2

SSM3K7002BFU

P1V8S_DGPU

1UF_6.3V_2

499_1%_2

P1V8S_DGPU

10K_5%_2

FBM_11_160808_121T

P1V8S_DGPU

FBM_11_160808_121T

10UF_6.3V_3

P1V8S_DGPU

10UF_6.3V_3

FBM_11_160808_121T

1UF_6.3V_2

10K_5%_2_DY

0.1UF_16V_2

499_1%_2

FBM_11_160808_121T

1UF_6.3V_2

0.1UF_16V_2

10K_5%_2

TP30

10UF_6.3V_3

PVPCIE

10UF_6.3V_3

TP30

C CS

10K_5%_2

27MHZ

TP30

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

0.1UF_16V_2

SSM3K7002BFU

Block Diagram

P3V3S_DGPU

SSM3K7002BFU

12PF_50V_2

1M_5%_2

10K_5%_2

TP30

0.1UF_16V_2

P3V3S_DGPU

10K_5%_2

RSC_0402_DY

10K_5%_2

RSC_0402_DY

10K_5%_2_DY

10K_5%_2

R5031

R5030

R5010

R5016

R5074

R5073

R5072

U5001

R5017

R5056

L5000

R5000

C5005C5000C5001

L5001

C5004C5002C5003

R5009

R5008

R5007

R5006

C5212

TP12

TP14

TP11

TP15

TP16

R5060

Q5000

R5015

R5063

R5005

C5010

R5004

R5003

R5061

C5012

C5011

R4

X5000

TP5000

C5211

C5018

C5015

C5017

C5019

R5011

R5028

R5037

R5014

R5027

R5094

Q5001

R5095

Q5002

L5004

C5013

L5005

C5014

C5016

L5006

56F7

56D5

56C5

34C5

56F7

21D3 21D2 5A7 37C3 56D5

21D3 21D2 5A7 37C6 56D5

15D8

35B2

56C5

13C6

56D5

56D3

56D3 35B2

13C6

56D5

36B5

35D8

56F7

35D8

56E2

35B2

36A5

56D7

36D8

35B2

35A2

21E7

34C5

36A5

35D8

56D3

35D8 56D3

36D8

56F7

40B1

13C6

56F7

35B2

56F7

56C7

56F7

40A8

VGA_CRTR

VGA_CRTG

VGA_CRTB

GPIO9

GPU_SIC

GPIO2

VGA_LVDS_DDCCLK

PWRCNTL_1

PWRCNTL_0

EC_SMB2_DATA GPU_SID

EC_SMB2_CLK GPU_SIC

VGA_CRT_VSYNC

VGA_CRT_HSYNC

GPIO11

GPIO22

GPIO9

GPIO2

GPIO5

GPIO11

VGA_LCM_BKLTEN

PVPCIE_DPLL_VDDC

PWRCNTL_1

GPIO22

MEM_ID3

MEM_ID2

MEM_ID1

MEM_ID0

VGA_LVDS_DDCDATA

VGA_CRT_HSYNC

VGA_CRTB

VGA_CRTG

VGA_CRT_VSYNC

VGA_HDMI_TX1_DN

VGA_HDMI_TX1_DP

VGA_HDMI_TX0_DN

VGA_HDMI_TX0_DP

VGA_HDMI_TXC_DN

VGA_HDMI_TXC_DP

P0V6S_VREFG

VGA_HDMI_TX2_DN

VGA_HDMI_TX2_DP

PWRCNTL_0

GPIO5

GPU_SID

GPIO1

GPIO0

P1V8S_VDD1DI

P1V8S_DPLL_PVDD

VGA_CRTR

P1V8S_AVDD

THRM_SHUTDWN#

P1V8S_TSVDD

GPIO0

GPIO1

VGA_HPDET

VGA_HDMI_DDCCLK

VGA_HDMI_DDCDATA

VGA_CRT_DDCCLK

VGA_CRT_DDCDATA

21

AD32

AU34

AV33

AW35

AW34

AC38

AG32

AC34

AH13

AG31

AC33

AC29

AU20

AT19

AU14

AV13

AR30

AT29

AU24

AV23

AT23

AT33

AR22

AU32

AU22

AR32

AV21

AT31

AT21

AV31

AR20

AU30

AT17

AT27

AR16

AR26

AU16

AU26

AV15

AV25

AT15

AT25

AR14

AR24

AJ33

AJ32

AK32

AL31

AK21

AJ21

AJ26

AK26

AB34

AD37

AA29

AC31

AC30

AD39

AM23

AL24

AM24

AN23

AK23

AC36

AK24

AD29

AH15

AJ13

AK17

AJ17

AH17

AJ23

AH23

AN13

AK13

AJ14

AL13

AN16

AM17

AN14

AG30

AK14

AM13

AM14

AM16

AL16

AK16

AJ16

AH18

AH20

AH24

AH26

AJ24

AK20

AJ20

AK19

AJ19

AD35

AD31

AD30

AE36

AT7

AU6

AW6

AR6

AU5

AW5

AP6

AP12

AU12

AW12

AR12

AW3

AT11

AV11

AP10

AU10

AW10

AR10

AT9

AV9

AN7

AV7

AU3

AU1

AU8

AR8

AR3

AW8

AP8

AR1

AF29

AN31

AN32

AM32

AG29

AK29

AM21

AM29

AM30

AK30

AN21

AL29

AL30

AJ31

AJ30

AL19

AM19

AN26

AM26

AF32

AC32

AE38

AF31

AF30

AF37

AE34

AD34

AN20

AM20

AM27

AL27

AF33

AD33

AG33

21

2 1

21

2 1

21

2 1

1

21

2

1

3

2 1

21

2 1

2121

21

2 1

21

1

2 1

21

2 1

2

1

3

2 1

2

1

3

21

2 1

21

2 1

21

BI

OUT

IN

G

DS

BI

IN

OUT

IN

OUT

BI

OUT

PLL/CLOCK

THERMAL

DDC/AUX

DAC2

DAC1

GENERAL PURPOSE I/O

I2C

MUTI GFX

DPD

DPC

DPB

DPA

SWAPLOCKB

SWAPLOCKA

XO_IN2

XO_IN

TS_A/NC

Y/NC

VSYNC

VDD2DI/NC

VDD1DI

V2SYNC/GENLK_VSYNC

TXCDP_DPD3P

TXCDM_DPD3N

TXCCP_DPC3P

TXCCM_DPC3N

TXCBP_DPB3P

TXCBM_DPB3N

TXCAP_DPA3P

TXCAM_DPA3N

TX5P_DPD0P

TX5P_DPB0P

TX5M_DPD0N

TX5M_DPB0N

TX4P_DPD1P

TX4P_DPB1P

TX4M_DPD1N

TX4M_DPB1N

TX3P_DPD2P

TX3P_DPB2P

TX3M_DPD2N

TX3M_DPB2N

TX2P_DPC0P

TX2P_DPA0P

TX2M_DPC0N

TX2M_DPA0N

TX1P_DPC1P

TX1P_DPA1P

TX1M_DPC1N

TX1M_DPA1N

TX0P_DPC2P

TX0P_DPA2P

TX0M_DPC2N

TX0M_DPA2N

SDA

SCL

RSET

RB

R2SET/NC

R2B/NC

R2/NC

R

GB

G2B/NC

G2/NC

G

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDC6DATA

DDC6CLK

DDC2DATA

DDC2CLK

DDC1DATA

DDC1CLK

COMP/NC

C/NC

BB

B2B/NC

B2/NC

B

AVSSQ

AVDD

AUX2P

AUX2N

AUX1P

AUX1N

A2VSSQ/TSVSSQ

A2VDDQ/NC

A2VDD/NC

XTALOUT

XTALIN

VSS2DI/NC

VSS1DI

VREFG

TSVSS

TSVDD

TS_FDO

DDCCLK_AUX7P

DDCDATA_AUX7N

JTAG_TRSTB

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

HSYNC

HPD1

H2SYNC/GENLK_CLK

GPIO_9_ROMSI

GPIO_8_ROMSO

GPIO_7_BLON

GPIO_6

GPIO_5_AC_BATT

GPIO_4_SMBCLK

GPIO_3_SMBDATA

GPIO_23_CLKREQB

GPIO_22_ROMCSB

GPIO_21_BB_EN

GPIO_20_PWRCNTL_1

GPIO_2

GPIO_19_CTF

GPIO_18_HPD3

GPIO_17_THERMAL_INT

GPIO_16

GPIO_15_PWRCNTL_0

GPIO_14_HPD2

GPIO_13

GPIO_12

GPIO_11

GPIO_10_ROMSCK

GPIO_1

GPIO_0

GENERICG_HPD6

GENERICF_HPD5

GENERICE_HPD4

GENERICD

GENERICC

GENERICB

GENERICA

DVPDATA_9

DVPDATA_8

DVPDATA_7

DVPDATA_6

DVPDATA_5

DVPDATA_4

DVPDATA_3

DVPDATA_23

DVPDATA_22

DVPDATA_21

DVPDATA_20

DVPDATA_2

DVPDATA_19

DVPDATA_18

DVPDATA_17

DVPDATA_16

DVPDATA_15

DVPDATA_14

DVPDATA_13

DVPDATA_12

DVPDATA_11

DVPDATA_10

DVPDATA_1

DVPDATA_0

DVPCNTL_MVP_1

DVPCNTL_MVP_0

DVPCNTL_2

DVPCNTL_1

DVPCNTL_0

DVPCLK

DPLUS

DPLL_VDDC

DPLL_PVSS

DPLL_PVDD

DMINUS

OUT

BI

G

DS

IN

G

DS

IN

BI

IN

OUT

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7654321

76543

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

6857

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

TC7SZ08FU

P3V3S_DGPU

0_5%_2_DY

AMD_216_0833002_FCBGA_962P

A3 CS

Block Diagram

0.1UF_6.3V_1

PVPCIE

0.1UF_6.3V_1

1.27K_1%_2

2K_1%_2

10K_5%_210K_5%_2

AMD_216_0833002_FCBGA_962P

1K_5%_2

R5013

U5005

R5071R5070

U5001

C5052

C5053

C5050

C5051

C5048

C5049

C5046

C5047

C5044

C5045

C5042

C5043

C5040

C5041

C5038

C5039

C5036

C5037

C5034

C5035

C5032

C5033

C5030

C5031

C5028

C5029

C5026

C5027

C5024

C5025

C5023

C5022

R5034

R5035

R5039

34A8

42A1

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42C4

42D4

42B1

42D1

42B1

42D1

42B1

42C1

42B1

42C1

42B1

42C1

42B1

42C1

42B1

42C1

42B1

42C1

42A1

42C1

42A1

42C1

42B1

42A1

48C3

42C1

48C3

42C4

42D4

42C4

42A1

34D7

34B5

34A8

21E3

51A8 27C7

34A8

51B6

27C3

51C7

28C3

34A8

VGA_LVDS_TXCL_DP

BUF_PLT_RST#

DGPU_HOLD_RST#

DGPU_PERST

PEG_C_TX10_DP

PEG_RX15_DP

PEG_C_RX0_DPPEG_RX0_DP

PEG_C_RX0_DNPEG_RX0_DN

PEG_C_RX1_DPPEG_RX1_DP

PEG_C_RX1_DNPEG_RX1_DN

PEG_C_RX2_DPPEG_RX2_DP

PEG_C_RX2_DNPEG_RX2_DN

PEG_C_RX3_DPPEG_RX3_DP

PEG_C_RX3_DNPEG_RX3_DN

PEG_C_RX4_DPPEG_RX4_DP

PEG_C_RX4_DNPEG_RX4_DN

PEG_C_RX5_DPPEG_RX5_DP

PEG_C_RX5_DNPEG_RX5_DN

PEG_C_RX6_DPPEG_RX6_DP

PEG_C_RX6_DNPEG_RX6_DN

PEG_C_RX7_DPPEG_RX7_DP

PEG_C_RX7_DNPEG_RX7_DN

PEG_C_RX8_DNPEG_RX8_DN

PEG_C_RX8_DPPEG_RX8_DP

PEG_C_RX9_DPPEG_RX9_DP

PEG_C_RX9_DNPEG_RX9_DN

PEG_C_RX10_DPPEG_RX10_DP

PEG_C_RX10_DNPEG_RX10_DN

PEG_C_RX11_DPPEG_RX11_DP

PEG_C_RX11_DNPEG_RX11_DN

PEG_C_RX12_DPPEG_RX12_DP

PEG_C_RX12_DNPEG_RX12_DN

PEG_C_RX13_DPPEG_RX13_DP

PEG_C_RX13_DNPEG_RX13_DN

PEG_RX14_DP

PEG_RX14_DN

PEG_RX15_DN

GPU_PCIE_CALRP

GPU_PCIE_CALRN

PEG_C_TX0_DP

PEG_C_TX0_DN

PEG_C_TX1_DN

PEG_C_TX1_DP

PEG_C_TX2_DN

PEG_C_TX2_DP

PEG_C_TX3_DP

PEG_C_TX3_DN

PEG_C_TX4_DP

PEG_C_TX4_DN

PEG_C_TX5_DP

PEG_C_TX5_DN

PEG_C_TX6_DP

PEG_C_TX6_DN

PEG_C_TX7_DN

PEG_C_TX7_DP

PEG_C_TX8_DP

PEG_C_TX8_DN

PEG_C_TX9_DP

PEG_C_TX9_DN

PEG_C_TX10_DN

PEG_C_TX11_DP

PEG_C_TX11_DN

PEG_C_TX13_DP

PEG_C_TX13_DN

PEG_C_TX14_DN

PEG_C_TX15_DN

PEG_C_TX15_DP

CLK_PEG_REF_DN

PEG_C_RX15_DN

PEG_C_RX15_DP

PEG_C_RX14_DN

PEG_C_RX14_DP

PEG_C_TX12_DN

PEG_C_TX12_DP

PEG_C_TX14_DP

VGA_LCM_VDDEN

VGA_INV_PWM_3

VGA_LVDS_TXDL1_DN

VGA_LVDS_TXCL_DN

VGA_LVDS_TXDL2_DP

VGA_LVDS_TXDL2_DN

VGA_LVDS_TXDL0_DN

VGA_LVDS_TXDL1_DP

CLK_PEG_REF_DP

VGA_LVDS_TXDL0_DP

21

5

4

3

2

1

21

AK27

AF35

AG36

AG38

AH37

AH35

AJ36

AJ38

AK37

AN36

AP37

AP35

AR35

AR37

AU39

AW37

AU35

AK35

AL36

AP34

AR34

AJ27

AH16

AA30

N30

N29

N33

N32

P30

P29

P33

P32

T30

T29

T33

T32

U30

U29

U33

U32

W33

W32

H33

H32

K30

K29

J33

J32

K33

K32

L30

L29

L33

L32

Y33

Y32

M35

L36

N38

M37

P35

N36

R38

P37

T35

R36

U38

T37

V35

U36

W38

V37

Y35

W36

F35

E37

G38

F37

H35

G36

J38

H37

K35

J36

L38

K37

AA38

Y37

AB35

AA36

Y30

Y29

21

BI

IN

+-

OUT

BI

LVDS CONTROL

LVTMDP

VARY_BL

TXOUT_U3P

TXOUT_U3N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_L3P

TXOUT_L3N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

DIGON

CALIBRATION

CLOCK

PCI EXPRESS INTERFACE

PCIE_TX9P

PCIE_TX9N

PCIE_TX8P

PCIE_TX8N

PCIE_TX7P

PCIE_TX7N

PCIE_TX6P

PCIE_TX6N

PCIE_TX5P

PCIE_TX5N

PCIE_TX4P

PCIE_TX4N

PCIE_TX3P

PCIE_TX3N

PCIE_TX2P

PCIE_TX2N

PCIE_TX1P

PCIE_TX1N

PCIE_TX15P

PCIE_TX15N

PCIE_TX14P

PCIE_TX14N

PCIE_TX13P

PCIE_TX13N

PCIE_TX12P

PCIE_TX12N

PCIE_TX11P

PCIE_TX11N

PCIE_TX10P

PCIE_TX10N

PCIE_TX0P

PCIE_TX0N

PERSTB

PCIE_RX9P

PCIE_RX9N

PCIE_RX8P

PCIE_RX8N

PCIE_RX7P

PCIE_RX7N

PCIE_RX6P

PCIE_RX6N

PCIE_RX5P

PCIE_RX5N

PCIE_RX4P

PCIE_RX4N

PCIE_RX3P

PCIE_RX3N

PCIE_RX2P

PCIE_RX2N

PCIE_RX1P

PCIE_RX1N

PCIE_RX15P

PCIE_RX15N

PCIE_RX14P

PCIE_RX14N

PCIE_RX13P

PCIE_RX13N

PCIE_RX12P

PCIE_RX12N

PCIE_RX11P

PCIE_RX11N

PCIE_RX10P

PCIE_RX10N

PCIE_RX0P

PCIE_RX0N

PCIE_REFCLKP

PCIE_REFCLKN

PCIE_CALRP

PCIE_CALRNPWRGOOD

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

R5022 OPEN

R5048 OPEN

SEYMOUR

THAMES

R5048 STUFF

R5022 STUFF

6858

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

240_1%_2

RSC_0402_DY

240_1%_2

RSC_0402_DY

0.1UF_16V_2

100_1%_2

62

63

P1V5S_DGPU

40.2_1%_2

1K_5%_2

5.11K_1%_2_DY

P3V3S_DGPU

AMD_216_0833002_FCBGA_962P

26

1

12

0.1UF_16V_2

100_1%_2

TP30

100_1%_2

0.1UF_16V_2

61

40.2_1%_2

P1V5S_DGPU

55

54 54

P1V5S_DGPU

120PF_50V_2

0.1UF_16V_2

0

1

2

3

4

5

6

7

8

10

9

11

12

1

0

2

4

3

5

7

6

8

10

9

11

13

15

14

17

16

18

51_5%_2

Block Diagram

CS

10_5%_2

5.1K_1%_2

A3

20

19

22

21

23

25

24

27

28

30

29

31

33

32

35

34

36

38

37

40

39

41

43

42

45

44

46

48

47

49

51

50

53

52

56

55

58

57

40.2_1%_2

59

60

63

62

0

2

3

4

5

6

7

8

10

9

12

11

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

56

57

58

40.2_1%_2

59

100_1%_2

60

61

U5001U5001

R5012

R5029

C5200

R5032

R5025

R5001

C5201

TP13

R5002

R5020

C5202

R5021

R5024

R5052

R5022

R5033

R5058

R5048

R5047

R5050

C5204

R5045

C5205

R5053R5023

63C8

63D1

64D4 64D7 65D4

64D4

65D4

62C4

63C8

62C7

62D1

62D4 62D8

63D8

63C8

62D4 62D7

63D8

62C4

63C8

64D7

65D8

64D4

64D7 65D4 65D8

64D4 64D7

65D4 65D8

65D8

64C7

64C4

64C7

64C4

65C4

65C8

64C4

64C7

65C4

64C4

64C7

65C4

65C8

64C7

64C4

64C7

65C4

65C8

65C4 65C8

64C4 64C7

64B3 64D4 64D7

64B5 64C4 64C7

65B4 65D4 65D8

65B5 65C8 65D4

64C4 64C7

65C4 65C8

64C4 64C7

65C4 65C8

64C4 64C7

65C4 65C8

64D4 64D7 65D4 65D8

62D4 62D7 63D4

63D4 63D8

62C7

62D5

63D5

62C7

62C4

63C4

63C8

62C4

63C4

63C8

62C7

62C4

63C4

63C8

62B3 62D4 62D7

62B5 62C4

62C7

63B5 63C8 63D4

63B4 63D4 63D8

62C4 62C7

63C4 63C8

62C7

63C4

62C4 62C7

63C4 63C8

63D4

62C4 62C7

63C4 63C8

62C4 62C7

63C4

P1V05_REFSA_GPU

P1V05_REFDA_GPU

DQA<63>

DQA<62>

DQA<61>

DQA<47>

DQA<36>

DQA<24>

DQA<25>

DQA<26>

DQMA<6>

DQB<27>

DQB<18>

DQB<17>

MAA<1>

DQB<5>

MAB<13>

WEB1#

WEB0#

DQSB7_DN

DQSB6_DN

DQSB5_DN

DQSB4_DN

DQSB3_DN

DQSB2_DN

DQSB1_DN

DQSB0_DN

DQSB7_DP

DQSB6_DP

DQSB5_DP

DQSB4_DP

DQSB3_DP

DQSB2_DP

DQSB1_DP

DQSB0_DP

RASB1#

RASB0#

ODTB1

ODTB0

MAB<9>

MAB<8>

MAB<7>

MAB<6>

MAB<5>

MAB<4>

MAB<3>

MAB<2>

MAB_BA<1>

MAB_BA<0>

MAB_BA<2>

MAB<12>

MAB<11>

MAB<10>

MAB<1>

MAB<0>

DQMB<7>

DQMB<6>

DQMB<5>

DQMB<4>

DQMB<3>

DQMB<2>

DQMB<1>

DQMB<0>

CSB1#_0

CSB0#_0

CLKB1_DN

CLKB1_DP

CLKB0_DN

CLKB0_DP

CKEB1

CKEB0

CASB1#

CASB0#

P1V05_REFSB_GPU

DQB<9>

DQB<8>

DQB<7>

DQB<63>

DQB<62>

DQB<61>

DQB<60>

DQB<6>

DQB<59>

DQB<58>

DQB<57>

DQB<56>

DQB<55>

DQB<54>

DQB<53>

DQB<52>

DQB<51>

DQB<50>

DQB<49>

DQB<48>

DQB<47>

DQB<46>

DQB<45>

DQB<44>

DQB<43>

DQB<42>

DQB<41>

DQB<40>

DQB<4>

DQB<39>

DQB<38>

DQB<37>

DQB<36>

DQB<35>

DQB<34>

DQB<33>

DQB<32>

DQB<31>

DQB<30>

DQB<3>

DQB<29>

DQB<28>

DQB<26>

DQB<25>

DQB<24>

DQB<23>

DQB<22>

DQB<21>

DQB<20>

DQB<2>

DQB<19>

DQB<16>

DQB<15>

DQB<14>

DQB<13>

DQB<12>

DQB<11>

DQB<10>

DQB<1>

DQB<0>

DQA<52>

WEA1#

WEA0#

DQSA7_DN

DQSA6_DN

DQSA5_DN

DQSA4_DN

DQSA3_DN

DQSA2_DN

DQSA1_DN

DQSA0_DN

MAA<13>

DQSA7_DP

DQSA6_DP

DQSA5_DP

DQSA4_DP

DQSA3_DP

DQSA2_DP

DQSA1_DP

DQSA0_DP

RASA1#

RASA0#

ODTA1

ODTA0

MAA<9>

MAA<8>

MAA<7>

MAA<6>

MAA<5>

MAA<4>

MAA<3>

MAA<2>

MAA_BA<1>

MAA_BA<0>

MAA_BA<2>

MAA<12>

MAA<11>

MAA<10>

MAA<0>

DQMA<7>

DQMA<5>

DQMA<4>

DQMA<3>

DQMA<2>

DQMA<1>

DQMA<0>

CSA1#_0

CSA0#_0

CLKA1_DN

CLKA1_DP

CLKA0_DN

CLKA0_DP

CKEA1

CKEA0

CASA1#

CASA0#

DQA<9>

DQA<8>

DQA<7>

DQA<60>

DQA<6>

DQA<59>

DQA<58>

DQA<57>

DQA<56>

DQA<55>

DQA<54>

DQA<53>

DQA<51>

DQA<50>

DQA<5>

DQA<49>

DQA<48>

DQA<46>

DQA<45>

DQA<44>

DQA<43>

DQA<42>

DQA<41>

DQA<40>

DQA<4>

DQA<39>

DQA<38>

DQA<37>

DQA<35>

DQA<34>

DQA<33>

DQA<32>

DQA<31>

DQA<30>

DQA<3>

DQA<29>

DQA<28>

DQA<27>

DQA<23>

DQA<22>

DQA<21>

DQA<20>

DQA<2>

DQA<19>

DQA<18>

DQA<17>

DQA<16>

DQA<15>

DQA<14>

DQA<13>

DQA<12>

DQA<11>

DQA<10>

DQA<1>

DQA<0>

P1V05_REFDB_GPU

MAB<12..0>DQB<63..0>

VM_RESET

MAA<12..0>DQA<63..0>

AB11

N10

AK5

AF5

AK6

AE4

T5

H1

T3

H3

AD28

Y10

T10

AA12

Y12

W8

AA9

Y8

AA8

AA7

AC9

AC8

W9

Y9

T8

U8

U9

N9

N8

N7

P9

T9

P8

AM5

AJ9

AH1

AB5

V5

P3

K3

F6

AH11

AF3

AF1

AD5

AD3

AD1

AD6

AP5

AP1

AB3

AP3

AN4

AM1

AM6

AL4

AK1

AM7

AM8

AL7

AK9

AB1

AG7

AG8

AF9

AF8

AK3

AJ4

AH6

AH5

AG4

AF6

AB6

AA4

H6

H5

G4

F5

F3

F1

Y5

Y3

E1

Y1

Y6

V3

V1

V6

U4

T1

T6

R4

P5

E3

P6

N4

M5

M3

M1

M6

L4

K5

K6

J4

C3

C5

AM3

AJ8

AH3

AC4

W4

P1

K1

G7

AC10

AD10

L10

P10

AL10

AK10

AD7

AD8

L8

L9

AA11

U10

AA10

W10

W7

T7

L15

K26

D9

A14

E10

C14

E22

C32

D23

A32

K19

K23

L20

L18

AH12

M12

M27

AG12

N12

L27

J19

H17

J17

H16

J16

G16

L13

H20

H19

H23

G21

H21

J26

H26

J24

H24

J23

G24

D7

J10

E12

E16

E20

D25

D29

C34

D13

F14

E14

D15

F16

A16

A5

E6

D17

C6

A6

E8

C8

A8

G9

K10

K9

G8

G10

F18

H11

J13

H13

G13

C10

A10

F10

D11

A12

F12

A18

C18

F30

D31

E32

F32

D33

G32

E18

D19

E34

F20

A20

D21

F22

A22

C22

E24

A24

C24

F24

A35

A26

C26

F26

D27

E28

A28

C28

F28

A30

C30

C35

C37

F8

J11

C12

C16

C20

E26

E30

A34

K16

M13

K27

K24

H14

J14

G27

H27

J20

K21

K17

K20

G19

J21

21

2 1

21

2 1

1

2 1

21

2 1

2 12 1

BI

OUT

GDDR5/DDR2/GDDR3

GDDR5

DDR3

GDDR3/GDDR5

DDR2

DDR3

GDDR5/GDDR3

DDR2

MEMORY INTERFACE B

MAB1_8

MAB0_8

WEB1B

WEB0B

DDBIB1_3/QSB_7B/WDQSB_7

DDBIB1_2/QSB_6B/WDQSB_6

DDBIB1_1/QSB_5B/WDQSB_5

DDBIB1_0/QSB_4B/WDQSB_4

DDBIB0_3/QSB_3B/WDQSB_3

DDBIB0_2/QSB_2B/WDQSB_2

DDBIB0_1/QSB_1B/WDQSB_1

DDBIB0_0/QSB_0B/WDQSB_0

EDCB1_3/QSB_7/RDQSB_7

EDCB1_2/QSB_6/RDQSB_6

EDCB1_1/QSB_5/RDQSB_5

EDCB1_0/QSB_4/RDQSB_4

EDCB0_3/QSB_3/RDQSB_3

EDCB0_2/QSB_2/RDQSB_2

EDCB0_1/QSB_1/RDQSB_1

EDCB0_0/QSB_0/RDQSB_0

RASB1B

RASB0B

ADBIB1/ODTB1

ADBIB0/ODTB0

MAB1_1/MAB_9

MAB1_0/MAB_8

MAB0_7/MAB_7

MAB0_6/MAB_6

MAB0_5/MAB_5

MAB0_4/MAB_4

MAB0_3/MAB_3

MAB0_2/MAB_2

MAB1_7/BA1

MAB1_6/BA0

MAB1_5/BA2

MAB1_4/MAB_12

MAB1_3/MAB_11

MAB1_2/MAB_10

MAB0_1/MAB_1

MAB0_0/MAB_0

DRAM_RST

WCKB1B_1/DQMB_7

WCKB1_1/DQMB_6

WCKB1B_0/DQMB_5

WCKB1_0/DQMB_4

WCKB0B_1/DQMB_3

WCKB0_1/DQMB_2

WCKB0B_0/DQMB_1

WCKB0_0/DQMB_0

CSB1B_1

CSB1B_0

CSB0B_1

CSB0B_0

CLKTESTB

CLKTESTA

CLKB1B

CLKB1

CLKB0B

CLKB0

CKEB1

CKEB0

CASB1B

CASB0B

TESTEN

MVREFSB

MVREFDB

DQB0_9/DQB_9

DQB0_8/DQB_8

DQB0_7/DQB_7

DQB1_31/DQB_63

DQB1_30/DQB_62

DQB1_29/DQB_61

DQB1_28/DQB_60

DQB0_6/DQB_6

DQB1_27/DQB_59

DQB1_26/DQB_58

DQB1_25/DQB_57

DQB1_24/DQB_56

DQB1_23/DQB_55

DQB1_22/DQB_54

DQB1_21/DQB_53

DQB1_20/DQB_52

DQB1_19/DQB_51

DQB1_18/DQB_50

DQB0_5/DQB_5

DQB1_17/DQB_49

DQB1_16/DQB_48

DQB1_15/DQB_47

DQB1_14/DQB_46

DQB1_13/DQB_45

DQB1_12/DQB_44

DQB1_11/DQB_43

DQB1_10/DQB_42

DQB1_9/DQB_41

DQB1_8/DQB_40

DQB0_4/DQB_4

DQB1_7/DQB_39

DQB1_6/DQB_38

DQB1_5/DQB_37

DQB1_4/DQB_36

DQB1_3/DQB_35

DQB1_2/DQB_34

DQB1_1/DQB_33

DQB1_0/DQB_32

DQB0_31/DQB_31

DQB0_30/DQB_30

DQB0_3/DQB_3

DQB0_29/DQB_29

DQB0_28/DQB_28

DQB0_27/DQB_27

DQB0_26/DQB_26

DQB0_25/DQB_25

DQB0_24/DQB_24

DQB0_23/DQB_23

DQB0_22/DQB_22

DQB0_21/DQB_21

DQB0_20/DQB_20

DQB0_2/DQB_2

DQB0_19/DQB_19

DQB0_18/DQB_18

DQB0_17/DQB_17

DQB0_16/DQB_16

DQB0_15/DQB_15

DQB0_14/DQB_14

DQB0_13/DQB_13

DQB0_12/DQB_12

DQB0_11/DQB_11

DQB0_10/DQB_10

DQB0_1/DQB_1

DQB0_0/DQB_0

GDDR5

DDR3

GDDR5/GDDR3

DDR2

GDDR5/DDR2/GDDR3

DDR3

GDDR3/GDDR5

DDR2

MEMORY INTERFACE A

WEA1B

WEA0B

DDBIA1_3/QSA_7B/WDQSA_7

DDBIA1_2/QSA_6B/WDQSA_6

DDBIA1_1/QSA_5B/WDQSA_5

DDBIA1_0/QSA_4B/WDQSA_4

DDBIA0_3/QSA_3B/WDQSA_3

DDBIA0_2/QSA_2B/WDQSA_2

DDBIA0_1/QSA_1B/WDQSA_1

DDBIA0_0/QSA_0B/WDQSA_0

MAA1_8

MAA0_8

EDCA1_3/QSA_7/RDQSA_7

EDCA1_2/QSA_6/RDQSA_6

EDCA1_1/QSA_5/RDQSA_5

EDCA1_0/QSA_4/RDQSA_4

EDCA0_3/QSA_3/RDQSA_3

EDCA0_2/QSA_2/RDQSA_2

EDCA0_1/QSA_1/RDQSA_1

EDCA0_0/QSA_0/RDQSA_0

RASA1B

RASA0B

ADBIA1/ODTA1

ADBIA0/ODTA0

MAA1_1/MAA_9

MAA1_0/MAA_8

MAA0_7/MAA_7

MAA0_6/MAA_6

MAA0_5/MAA_5

MAA0_4/MAA_4

MAA0_3/MAA_3

MAA0_2/MAA_2

MAA1_7/MAA_A15_BA1

MAA1_6/MAA_14_BA0

MAA1_5/MAA_13_BA2

MAA1_4/MAA_12

MAA1_3/MAA_11

MAA1_2/MAA_10

MAA0_1/MAA_1

MAA0_0/MAA_0

WCKA1B_1/DQMA_7

WCKA1_1/DQMA_6

WCKA1B_0/DQMA_5

WCKA1_0/DQMA_4

WCKA0B_1/DQMA_3

WCKA0_1/DQMA_2

WCKA0B_0/DQMA_1

WCKA0_0/DQMA_0

CSA1B_1

CSA1B_0

CSA0B_1

CSA0B_0

CLKA1B

CLKA1

CLKA0B

CLKA0

CKEA1

CKEA0

CASA1B

CASA0B

MEM_CALRP2

MEM_CALRP0

MEM_CALRN2

MEM_CALRN1

MEM_CALRN0

MVREFSA

MVREFDA

MEM_CALRP1

DQA0_9/DQA_9

DQA0_8/DQA_8

DQA0_7/DQA_7

DQA1_31/DQA_63

DQA1_30/DQA_62

DQA1_29/DQA_61

DQA1_28/DQA_60

DQA0_6/DQA_6

DQA1_27/DQA_59

DQA1_26/DQA_58

DQA1_25/DQA_57

DQA1_24/DQA_56

DQA1_23/DQA_55

DQA1_22/DQA_54

DQA1_21/DQA_53

DQA1_20/DQA_52

DQA1_19/DQA_51

DQA1_18/DQA_50

DQA0_5/DQA_5

DQA1_17/DQA_49

DQA1_16/DQA_48

DQA1_15/DQA_47

DQA1_14/DQA_46

DQA1_13/DQA_45

DQA1_12/DQA_44

DQA1_11/DQA_43

DQA1_10/DQA_42

DQA1_9/DQA_41

DQA1_8/DQA_40

DQA0_4/DQA_4

DQA1_7/DQA_39

DQA1_6/DQA_38

DQA1_5/DQA_37

DQA1_4/DQA_36

DQA1_3/DQA_35

DQA1_2/DQA_34

DQA1_1/DQA_33

DQA1_0/DQA_32

DQA0_31/DQA_31

DQA0_30/DQA_30

DQA0_3/DQA_3

DQA0_29/DQA_29

DQA0_28/DQA_28

DQA0_27/DQA_27

DQA0_26/DQA_26

DQA0_25/DQA_25

DQA0_24/DQA_24

DQA0_23/DQA_23

DQA0_22/DQA_22

DQA0_21/DQA_21

DQA0_20/DQA_20

DQA0_2/DQA_2

DQA0_19/DQA_19

DQA0_18/DQA_18

DQA0_17/DQA_17

DQA0_16/DQA_16

DQA0_15/DQA_15

DQA0_14/DQA_14

DQA0_13/DQA_13

DQA0_12/DQA_12

DQA0_11/DQA_11

DQA0_10/DQA_10

DQA0_1/DQA_1

DQA0_0/DQA_0

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

1.8V_504MA

1.8V_110MA

59 68

MODEL,PROJECT,FUNCTION

X01

XXX 21-OCT-2002

1310xxxxx-0-0

P1V8S_DGPU

AMD_216_0833002_FCBGA_962P

1UF_6.3V_2

FBM_11_160808_121T

0.1UF_16V_2

P1V8S_DGPU

FBM_11_160808_121T

1UF_6.3V_2

10UF_6.3V_3

BLM18PG221SN1D

P1V8S_DGPU

0.01UF_50V_2

1UF_6.3V_2

0.1UF_16V_2

10UF_6.3V_3

1UF_6.3V_2

0.1UF_16V_2

10UF_6.3V_3

1UF_6.3V_2

PVCORE_DGPU

PVPCIE

PVCORE_DGPU

PVDDCORE_DGPU

P3V3S_DGPU

P1V5S_DGPU

PVPCIE

0.1UF_16V_2

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

1UF_6.3V_21UF_6.3V_2

1UF_6.3V_2

0.1UF_16V_21UF_6.3V_2

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

Block Diagram

CSC

10UF_6.3V_3

FBM_11_160808_121T

10UF_6.3V_3

FBM_11_160808_121T

10UF_6.3V_3

FBM_11_160808_121T

10UF_6.3V_3

U5001

L5013

C5115

C5114

C5113

C5112

C5111

C5110

C5126

C5136

C5135

C5125

C5124

C5134

C5146 C5133

C5123

C5122

C5132

C5130

C5121

C5120

C5129

C5145

C5144

C5143

C5154

C5153

C5152

C5165

C5164

C5197

C5195

C5193

C5192

C5151

C5150

C5148

C5163

C5161

C5160

C5147C5159

C5191

C5190

C5166

C5189

C5188

C5169

C5168

C5167

C5119

C5086

C5085

C5084

C5083

C5082

C5081

C5080

C5092

C5091

C5090

C5089

C5097

C5096

C5101

C5100

C5095

C5094

C5099

C5098

C5266

C5265

C5108

C5208 C5103

C5102

C5106

L5010

L5015

C5207

C5206

C5213

C5210

C5209

C5079

C5078

C5077

C5088

C5087

L5009

C5093

C5107

C5105

C5104

L5016

L5014

P1V8S_PCIE_VDDR

PVPCIE_SPV10

P1V8S_VDDCT

P1V8S_VDDR4

P1V8S_SPV18

P1V8S_MPV

AG15

AG13

AG11

AF15

AF13

AF12

AF11

AD12

AG24

AG23

AF24

AF23

G14

G11

AL9

AK8

AJ7

AG10

Y7

Y11

U7

U11

R11

AF7

P7

N11

M11

L7

L26

L23

L21

L16

L12

K8

AD11

K13

K11

J9

J7

H10

G29

G26

G23

G20

G17

AC7

M18

M16

M15

AD16

AD13

AC15

AC12

Y13

V15

T15

AB13

T12

R16

R13

R12

N22

N20

N17

N15

N13

M23

AA13

T27

N27

AB21

AB18

AB16

AA27

Y28

Y26

Y23

Y21

Y18

Y16

V27

V24

V22

AA24

V20

V17

U26

U23

U21

U18

U16

T24

T22

AA22

T20

T17

R26

R23

R21

R18

N24

M26

AH28

AA20

AH27

AH22

AG21

AG18

AG16

AF22

AF20

AF17

AD26

AD23

AA17

AD21

AD18

AC27

AC24

AC22

AC20

AC17

AB28

AB26

AB23

AA15

AG27

AG26

AF27

AF26

AN10

AM10

AN9

AB37

Y31

W30

W29

V28

AA34

AA33

AA32

AA31

N28

M28

L28

J30

J29

H30

H29

G31

U28

T28

R28

G30

U12

M21

V12

M20

H8

H7

AG28

AF28

AH29

21

2 1

2 1 2 1

2 1

2 12 1

2 1

2 1 2 1

2 1

21

2 1

21

2 1

21

SENESE

VOLTAGE

CORE I/O

ISOLATED

TRANSLATION

LEVEL

I/O

MEM I/O

CORE

PCIE

PLL

POWER

FB_GND

FB_VDDCI

FB_VDDC

VDDC#30

VDDC#29

VDDCI#22

VDDCI#1

VDDCI#19

VDDCI#16

VDDCI#11

VDDCI#7

VDDC#8

VDDC#7

VDDC#58

VDDC#57

VDDC#56

VDDCI#2

VDDC#55

VDDC#54

VDDC#53

VDDC#52

VDDC#51

VDDC#50

VDDC#49

VDDC#48

VDDCI#21

VDDC#47

VDDC#6

VDDC#46

VDDC#45

VDDC#44

VDDC#43

VDDC/BIF_VDDC#42

VDDC#41

VDDC#40

VDDC#39

VDDC#38

VDDCI#20

VDDC#5

VDDC#37

VDDC#36

VDDC#35

VDDC#34

VDDCI#18

VDDCI#17

VDDC/BIF_VDDC#33

VDDC#32

VDDCI#15

VDDCI#14

VDDC#4

VDDCI#13

VDDCI#12

VDDC#31

VDDCI#10

VDDCI#9

VDDCI#8

VDDC#28

VDDC#27

VDDC#26

VDDC#25

VDDC#3

VDDC#24

VDDC#23

VDDC#22

VDDC#21

VDDC#20

VDDC#19

VDDC#18

VDDCI#6

VDDCI#5

VDDC#17

VDDC#2

VDDC#16

VDDC#15

VDDC#14

VDDC#13

VDDCI#4

VDDCI#3

VDDC#12

VDDC#11

VDDC#10

VDDC#9

VDDC#1

VDD_CT#4

VDD_CT#3

VDD_CT#2

VDD_CT#1

NC_VSSRHB

NC_VSSRHA

NC_VDDRHB

NC_VDDRHA

VDDR4#6

VDDR4#3

VDDR4#2

VDDR4#1

VDDR4#8

VDDR4#7

VDDR4#5

VDDR4#4

VDDR3#4

VDDR3#3

VDDR3#2

VDDR3#1

VDDR1#9

VDDR1#8

VDDR1#7

VDDR1#6

VDDR1#5

VDDR1#4

VDDR1#34

VDDR1#33

VDDR1#32

VDDR1#31

VDDR1#30

VDDR1#3

VDDR1#29

VDDR1#28

VDDR1#27

VDDR1#26

VDDR1#25

VDDR1#24

VDDR1#23

VDDR1#22

VDDR1#21

VDDR1#20

VDDR1#2

VDDR1#19

VDDR1#18

VDDR1#17

VDDR1#16

VDDR1#15

VDDR1#14

VDDR1#13

VDDR1#12

VDDR1#11

VDDR1#10

VDDR1#1

SPVSS

SPV10

PCIE_VDDR#8

PCIE_VDDR#7

PCIE_VDDR#6

PCIE_VDDR#5

PCIE_VDDR#4

PCIE_VDDR#3

PCIE_VDDR#2

PCIE_VDDR#1

PCIE_VDDC#9

PCIE_VDDC#8

PCIE_VDDC#7

PCIE_VDDC#6

PCIE_VDDC#5

PCIE_VDDC#4

PCIE_VDDC#3

PCIE_VDDC#2

PCIE_VDDC#12

PCIE_VDDC#11

PCIE_VDDC#10

PCIE_VDDC#1

SPV18

MPV18#2

MPV18#1

PCIE_VDDR/PCIE_PVDD

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7654321

76543

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

6860

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

150_1%_2

AMD_216_0833002_FCBGA_962P

150_1%_2

1UF_6.3V_2

0.1UF_16V_2

150_1%_2

0.1UF_16V_2

1UF_6.3V_2 0.1UF_16V_2

1UF_6.3V_2

10UF_6.3V_3

P1V8S_DGPU

FBM_11_160808_121T

P1V8S_DGPU

PVPCIE

10UF_6.3V_3

1UF_6.3V_2

FBM_11_160808_121T

1UF_6.3V_2

FBM_11_160808_121T

Block Diagram

CS

A3

0.1UF_16V_2

10UF_6.3V_3

1UF_6.3V_2

PVPCIE

10UF_6.3V_3

FBM_11_160808_121T

10UF_6.3V_3

FBM_11_160808_121T

10UF_6.3V_3

0.1UF_16V_2

L5022

C5235

C5236

C5237

L5021

C5232

C5233

C5234

L5020

C5229

C5230

C5231

C5227

C5226

L5019

C5228

C5223

C5225

L5018

C5224

L5017

C5220

C5221

C5222

U5001

R5040R5041

R5042

60C6

60B6

60B3

60C3

60B3

60B6

60B3 60C3

DPAB_VDD10

DPAB_VDD18

DPEF_VDD18

DPCD_VDD18

DPEF_VDD18

DPCD_VDD10

DPCD_VDD18

DPEF_VDD10

DPCD_VDD18

DPEF_VDD18

DPAB_VDD18

21

2 1

21

2 1

21

2 1

21

2 1

21

2 1

21

2 1

AL38

AM37

AM39

AG34

AF34

AK34

AK33

AJ34

AH34

AM33

AL33

AV19

AU18

AW18

AP23

AP22

AP15

AP14

AP21

AP20

AT13

AP13

AV29

AU28

AW28

AP26

AP25

AP33

AN33

AP24

AN24

AP32

AP31

AM35

AN38

AR18

AV17

AR28

AV27

AM34

AL34

AK39

AH39

AF39

AU37

AR39

AP39

AN34

AW22

AW20

AP19

AP18

AN19

AW16

AW14

AP17

AP16

AN17

AW32

AW30

AP30

AP29

AN29

AW26

AW24

AP28

AP27

AN27

2121

21

IN

DP E/F POWER

DP C/D POWER DP A/B POWER

DP PLL POWER

DP/DPF_VSSR#5

DP/DPF_VSSR#4

DP/DPF_VSSR#3

DP/DPF_VSSR#2

DP/DPF_VSSR#1

DPEF/DPF_VDD18#2

DPEF/DPF_VDD18#1

DPEF/DPF_VDD10#2

DPEF/DPF_VDD10#1

DP_VSSR/DPF_PVSS

DPEF_VDD18/DPF_PVDD

DPEF_CALR

DP/DPE_VSSR#4

DP/DPE_VSSR#3

DP/DPE_VSSR#2

DP/DPE_VSSR#1

DPEF/DPE_VDD18#2

DPEF/DPE_VDD18#1

DPEF/DPE_VDD10#2

DPEF/DPE_VDD10#1

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPE_PVDD

DP/DPD_VSSR#5

DP/DPD_VSSR#4

DP/DPD_VSSR#3

DP/DPD_VSSR#2

DP/DPD_VSSR#1

DPCD/DPD_VDD18#2

DPCD/DPD_VDD18#1

DPCD/DPD_VDD10#2

DPCD/DPD_VDD10#1

DP_VSSR/DPD_PVSS

DPCD_VDD18/DPD_PVDD

DPCD_CALR

DP/DPC_VSSR#5

DP/DPC_VSSR#4

DP/DPC_VSSR#3

DP/DPC_VSSR#2

DP/DPC_VSSR#1

DPCD/DPC_VDD18#2

DPCD/DPC_VDD18#1

DPCD/DPC_VDD10#2

DPCD/DPC_VDD10#1

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPC_PVDD

DP/DPB_VSSR#5

DP/DPB_VSSR#4

DP/DPB_VSSR#3

DP/DPB_VSSR#2

DP/DPB_VSSR#1

DPAB/DPB_VDD18#2

DPAB/DPB_VDD18#1

DPAB/DPB_VDD10#2

DPAB/DPB_VDD10#1

DP_VSSR/DPB_PVSS

DPAB_VDD18/DPB_PVDD

DPAB_CALR

DP/DPA_VSSR#5

DP/DPA_VSSR#4

DP/DPA_VSSR#3

DP/DPA_VSSR#2

DP/DPA_VSSR#1

DPAB/DPA_VDD18#2

DPAB/DPA_VDD18#1

DPAB/DPA_VDD10#2

DPAB/DPA_VDD10#1

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPA_PVDD

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

61 68

MODEL,PROJECT,FUNCTION

X01

XXX 21-OCT-2002

1310xxxxx-0-0

AMD_216_0833002_FCBGA_962P

C CS

Block Diagram

U5001

PX_EN

AW39

AW1

A39

H39

H34

H31

G34

G33

F39

Y39

Y34

W34

W31

V39

V34

F34

U34

U31

T39

T34

T31

R34

P39

P34

P31

N34

E39

N31

M39

M34

L34

L31

K39

K34

K31

J34

J31

AB39

AL21

F13

F11

E5

E35

C39

C1

B9

B7

B33

AA28

B31

B29

B27

B25

B23

B21

B19

B17

B15

B13

AA26

B11

AR5

AP9

AP7

AP11

AN8

AN6

AN30

AN2

AN11

AA23

AM9

AM31

AM11

AL8

AL6

AL32

AL26

AL23

AL20

AA21

AL2

AL17

AL14

AL11

AK7

AK31

AK11

AJ6

AJ28

AJ2

AA2

AJ11

AJ10

AH21

AG9

AG6

AG22

AG20

AG2

AG17

AF21

AA18

AF18

AF16

AF10

AE6

AE2

AD9

AD27

AD24

AD22

AD20

AA16

AD17

AD15

AC6

AC28

AC26

AC23

AC21

AC2

AC18

AC16

A37

AC13

AC11

Y27

Y24

Y22

Y20

Y17

Y15

AB27

W6

W2

V26

V23

V21

V18

V16

V13

V11

U6

AB24

U27

U24

U22

U20

U2

U17

U15

U13

T26

T23

AB22

T21

T18

T16

T13

T11

R6

R27

R24

R22

R20

AB20

R2

R17

R15

N6

N26

N23

N21

N2

N18

N16

AB17

M24

M22

M17

L6

L24

L22

L2

L17

L11

K7

AB15

K14

J8

J6

J27

J2

H9

G6

G2

F9

F7

AB12

F33

F31

F29

F27

F25

F23

F21

F19

F17

F15

AA6

A3

GND

GND#162

GND#152

GND#97

GND#96

GND#95

GND#94

GND#93

GND#92

GND#91

GND#90

GND#89

GND#88

GND#9

GND#87

GND#86

GND#85

GND#84

GND#83

GND#82

GND#81

GND#80

GND#79

GND#8

GND#78

GND#77

GND#76

GND#75

GND#74

GND#73

GND#72

GND#71

GND#70

GND#69

GND#7

GND#68

GND#67

GND#66

GND#65

GND#64

GND#63

GND#62

GND/PX_EN#61

GND#60

GND#59

GND#6

GND#58

GND#57

GND#56

GND#55

GND#54

GND#53

GND#52

GND#51

GND#50

GND#49

GND#5

GND#48

GND#47

GND#46

GND#45

GND#44

GND#43

GND#42

GND#41

GND#40

GND#4

GND#39

GND#38

GND#37

GND#36

GND#35

GND#34

GND#33

GND#32

GND#31

GND#30

GND#3

GND#29

GND#28

GND#27

GND#26

GND#25

GND#24

GND#23

GND#22

GND#21

GND#20

GND#2

GND#19

GND#18

GND#175

GND#174

GND#173

GND#172

GND#171

GND#17

GND#170

GND#169

GND#168

GND#167

GND#166

GND#165

GND#164

GND#163

GND#161

GND#160

GND#16

GND#159

GND#158

GND#157

GND#156

GND#155

GND#154

GND#153

GND#151

GND#150

GND#149

GND#15

GND#148

GND#147

GND#146

GND#145

GND#144

GND#143

GND#142

GND#141

GND#140

GND#139

GND#14

GND#138

GND#137

GND#136

GND#135

GND#134

GND#133

GND#132

GND#131

GND#130

GND#129

GND#13

GND#128

GND#127

GND#126

GND#125

GND#124

GND#123

GND#122

GND#121

GND#120

GND#119

GND#12

GND#118

GND#117

GND#116

GND#115

GND#114

GND#113

GND#112

GND#111

GND#110

GND#109

GND#11

GND#108

GND#107

GND#106

GND#105

GND#104

GND#103

GND#102

GND#101

GND#100

GND#98

GND#10

GND#1

VSS_MECH#3

VSS_MECH#2

VSS_MECH#1

PCIE_VSS#9

PCIE_VSS#8

PCIE_VSS#7

PCIE_VSS#6

PCIE_VSS#5

PCIE_VSS#4

PCIE_VSS#35

PCIE_VSS#34

PCIE_VSS#33

PCIE_VSS#32

PCIE_VSS#31

PCIE_VSS#30

PCIE_VSS#3

PCIE_VSS#29

PCIE_VSS#28

PCIE_VSS#27

PCIE_VSS#26

PCIE_VSS#25

PCIE_VSS#24

PCIE_VSS#23

PCIE_VSS#22

PCIE_VSS#21

PCIE_VSS#20

PCIE_VSS#2

PCIE_VSS#19

PCIE_VSS#18

PCIE_VSS#17

PCIE_VSS#16

PCIE_VSS#15

PCIE_VSS#14

PCIE_VSS#13

PCIE_VSS#12

PCIE_VSS#11

PCIE_VSS#10

PCIE_VSS#1

IN

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7654321

76543

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

6862

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SAM_K4B1G1646D_HCF7_FBGA_100P

13

P1V5S_DGPU

1

A3 CS

Block Diagram

P1V5S_DGPU

0

1UF_6.3V_2

4.99K_1%_2

P1V5S_DGPU

243_1%_2

13

8

1UF_6.3V_2

P1V5S_DGPU

0.1uF_16V_2

0.01UF_50V_2

0.1uF_16V_2

2.2UF_6.3V_2

0.1uF_16V_2

2

3

4

5

6

7

8

9

10

11

12

4.99K_1%_24.99K_1%_2

10UF_6.3V_310UF_6.3V_3

243_1%_2

56_5%_256_5%_2

4.99K_1%_24.99K_1%_2

0

1

2

3

4

5

7

6

9

10

11

12

4.99K_1%_24.99K_1%_2

10UF_6.3V_3

SAM_K4B1G1646D_HCF7_FBGA_100P

10UF_6.3V_3

4.99K_1%_2

U5501U5500

R5506R5507

C5503

C5534C5533

R5508

R5541

C5516

R5540

R5504R5505

C5502

C5532

C5531

C5530

C5529

C5528

R5509

R5502R5503

C5527

C5501

C5526

C5525

C5524

R5500R5501

C5500

C5523

C5522

C5521

C5520

58D8

58D8 58D8

58D8

58B5 62C7

58C5 62C7

58C5

58D5

58C5

58D5

58C5

58D5

58B5 62C7

58B5 62B5 62C7

58B5 62B3 62D7

58A5 62C4

58B5 62C4

58C5

58D5 62D4 63D4 63D8

58B5 62D4

62D7

58C5

58A5 62C7

58B5 62C7

58C5

58D5

58A5 58D4 62D8 63D4 63D8

58B5 62C4

62D7

58C5 62C4

58B5 62C4

58B5 62B5 62C4

58B5 62B3 62D4

58A1 62C4 63C4 63C8 64C4 64C7 65C4 65C8

62B2

62B4

62D4

58A1 62C7 63C4 63C8 64C4 64C7 65C4 65C8

62D4

58B5 62C4 62C7

62A7

62A8

58A5 58D4 62D4 63D4 63D8

62D7

58D5 62D7 63D4 63D8

CLKA0_DP

CLKA0_DN

DQA<27>

DQA<30>

DQA<28>

DQA<24>

MAA<0>

VRAM_VREFD_A<1>

VRAM_VREFC_A<2>

VM_RESET

DQMA<2>

DQSA3_DN

CKEA0

ODTA0

CSA0#_0

DQA<23>

RASA0#

MAA<1>

MAA<2>

MAA<3>

MAA<4>

MAA<5>

MAA<6>

MAA<7>

MAA<8>

MAA<9>

MAA<10>

MAA<11>

MAA<12>

MAA<13>

MAA_BA<0>

MAA_BA<1>

MAA_BA<2>

CASA0#

WEA0#

DQSA3_DP

DQSA2_DP

DQMA<3>

DQSA2_DN

DQA<26>

DQA<31>

DQA<29>

DQA<25>

DQA<19>

DQA<18>

DQA<21>

DQA<16>

DQA<17>

DQA<22>

DQA<20>DQA<11>

DQA<10>

DQA<14>

DQA<12>

DQA<13>

DQA<9>

DQA<8>

DQA<15>

DQA<7>

DQA<5>

DQA<6>

DQA<4>

DQA<1>

DQA<3>

DQA<2>

DQA<0>

DQSA0_DP

DQSA1_DP

DQMA<0>

DQSA0_DN

DQMA<1>

WEA0#

CASA0#

DQSA1_DN

MAA_BA<0>

MAA_BA<1>

MAA_BA<2>

CLKA0_DP

MAA<13..0>

RASA0#

CSA0#_0

VRAM_VREFC_A<0>

MAA<13>

MAA<11>

ODTA0

CKEA0

CLKA0_DN

CLKA0_DP

MAA<5>

VM_RESET

MAA<6>

MAA<7>

MAA<3>

MAA<2>

VRAM_VREFD_A<1>VRAM_VREFC_A<2>

CLKA0_DN

VRAM_VREFD_A<3>

VRAM_VREFC_A<0>

MAA<0>

MAA<1>

MAA<4>

MAA<8>

MAA<9>

MAA<10>

MAA<12>

MAA<13..0>

VRAM_VREFD_A<3>

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

2121

2 1

21

2 1

21

2121

2 1

21

2121

2 1

2121

2 1

IN

BI

BI BI

BI

IN

BI

IN

BI

IN

IN IN

BI

BIBI

IN

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6863

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

1UF_6.3V_2

12

243_1%_2

6

7

4.99K_1%_2 4.99K_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

10UF_6.3V_3 10UF_6.3V_3

4.99K_1%_2 4.99K_1%_2

13

12

11

10

9

8

6

7

5

3

4

1

2

0

56_5%_2

4.99K_1%_2 4.99K_1%_2

56_5%_2

243_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

10UF_6.3V_3

A3

4.99K_1%_2 4.99K_1%_2

10UF_6.3V_3

CS

Block Diagram

13

11

9

8

10

5

4

3

2

1

0

0.1uF_16V_2

2.2UF_6.3V_2

0.1uF_16V_2

0.01UF_50V_2

0.1uF_16V_2

P1V5S_DGPU

P1V5S_DGPU P1V5S_DGPU

P1V5S_DGPU

P1V5S_DGPU P1V5S_DGPU

P1V5S_DGPU

1UF_6.3V_2

P1V5S_DGPU P1V5S_DGPU

U5503

U5502

R5517

C5549

R5516

C5548

C5507

C5547

C5546

R5518

R5543R5542

C5517

R5514R5515

C5506

C5545

C5544

C5543

C5542

R5519

R5512R5513

C5505

C5541

C5540

C5539

C5538

R5510R5511

C5504

C5537

C5536

C5535

58D8

63D8

58D8

58D8 58D8

58D8

58C5

58D8

58A5 63C4

58B5 63C4

58D8

58A5 63C8

63A4

58D8

58D5 62D4 62D7 63D8

63A3

63D8

58A1 62C4 62C7 63C4 64C4 64C7 65C4 65C8

58B5 63C4

63D8

58A5 58D4 62D4 62D8 63D4

63A6

63A8

63D4

58B5 63D4

63D8

58A1 62C4 62C7 63C8 64C4 64C7 65C4 65C8

58C5

58D5

58C5

63D4

58A5 58D4 62D4 62D8

58D5 62D4 62D7 63D8

58B5 63C8 63D4

58B5 63C4

58D5 62D4 62D7 63D4

58B5 63B4 63D4

58B5 63B5 63D4

58B5 63C8

58C5

58B5 63C8

58B5 63B4 63D8

58D8

58B5 63C8

58B5 63B5 63C8

58D8

DQA<50>

DQA<49>

DQA<52>

DQA<55>

DQA<48>

DQA<53>

DQA<47>

DQA<45>

DQA<41>

DQA<40>

DQA<46>

DQA<42>

DQA<44>

MAA<5>

DQA<59>

DQA<57>

DQA<56>

VM_RESET

MAA<12>

MAA<11>

DQA<60>

MAA<7>

DQA<43>

MAA<11>

MAA<12>

MAA<4>

DQA<63>

DQMA<6>

DQMA<7>

DQSA6_DN

DQSA7_DN

DQSA7_DP

DQSA6_DP

DQA<61>

DQA<58>

DQA<62>

WEA1#

CASA1#

RASA1#

DQA<51>

WEA1#

MAA<0>

VRAM_VREFC_A<6>

MAA<0>

MAA<1>

MAA_BA<0>

VRAM_VREFD_A<5>

VRAM_VREFC_A<4>

ODTA1

CKEA1

VRAM_VREFD_A<7>

MAA<13>

MAA<10>

MAA<9>

MAA<8>

MAA<7>

MAA<6>

MAA<5>

MAA<4>

MAA<3>

MAA<2>

MAA<1>

MAA<13..0>

VRAM_VREFD_A<7>

VRAM_VREFC_A<4>

VRAM_VREFC_A<6>

CLKA1_DP

VM_RESET

DQMA<5>

DQSA4_DN

DQSA5_DP

DQMA<4>

DQSA5_DN

VRAM_VREFD_A<5>

MAA<13..0>

MAA_BA<2>

MAA_BA<1>

MAA<13>

MAA<10>

MAA<9>

MAA<8>

MAA<6>

MAA<3>

MAA<2>

CLKA1_DN

CSA1#_0

MAA_BA<0>

MAA_BA<1>

MAA_BA<2>

CLKA1_DP

CLKA1_DN

RASA1#

DQSA4_DP

CASA1#

CSA1#_0

CLKA1_DP

DQA<35>

DQA<38>

DQA<33>

DQA<37>

DQA<32>

DQA<36>

DQA<34>

DQA<39>

ODTA1

CKEA1

CLKA1_DN

DQA<54>

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

21

2 1

21

2 1 2 1

2 1

21

2121

2 1

2121

2 1

21

2121

2 1

2121

2 1

IN

BI

IN

BI

IN

BI

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

BI

IN

BI

IN

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6864

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SAM_K4B1G1646D_HCF7_FBGA_100P

12

P1V5S_DGPU

10

9

4.99K_1%_2

243_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

4.99K_1%_2 4.99K_1%_2

13

12

11

10

9

8

6

7

5

3

4

1

2

0

4.99K_1%_2 4.99K_1%_2

56_5%_2 56_5%_2

243_1%_2

10UF_6.3V_3

A3 CS

Block Diagram

4.99K_1%_2 4.99K_1%_2

13

11

8

7

6

5

4

2

1

0

0.1uF_16V_2

0.01UF_50V_2

0.1uF_16V_2

4.99K_1%_2

10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3

1UF_6.3V_2

2.2UF_6.3V_2

1UF_6.3V_2

3

C5558

C5559

C5560

C5561

C5562

C5554

C5552

C5553

C5551

C5550

U5504

R5526R5527

C5511

U5505

C5564C5563

R5528

R5545

C5518

R5544

R5524R5525

C5510

R5529

R5522R5523

C5557

C5509

C5556

C5555

R5520R5521

C5508

58D4

58D1

58B1

58C1

58B1

58A1

58D4

58C1

58D1

58C1

58D1

64C4

58B1 64C4

64C4

64B3 64D4

58B1 64B5 64C4

58B1 64C4

64C4

58A1 62C4 62C7 63C4 63C8 64C4 65C4 65C8

64D7

58A1 58D1 64D4 65D4 65D8

64D4 65D4 65D8

64A7

64A8

58B1 64C4 64C7

64D4

58B1 64D4

64D7

58A1 62C4 62C7 63C4 63C8 64C7 65C4 65C8

58C1

58D1

58C1

58A1 64C7

58B1 64C7

58B1 64B5 64C7

58B1 64B3 64D7

58B1 64C7

58C1 64C7

58B1 64C7

58C1

58D1

64D4

58D1 64D7 65D4 65D8

58A1 58D1 64D7 65D4 65D8

64B4

64B2

64D7

58D4

DQB<9>

DQB<12>

DQB<14>

DQB<8>

DQB<15>

DQB<11>

DQB<20>

MAB<0>

VRAM_VREFD_B<1>

VRAM_VREFC_B<2>

VM_RESET

DQMB<2>

DQSB1_DN

CKEB0

ODTB0

CSB0#_0

CLKB0_DP

CLKB0_DN

DQB<21>

RASB0#

MAB<1>

MAB<2>

MAB<3>

MAB<4>

MAB<5>

MAB<6>

MAB<7>

MAB<8>

MAB<9>

MAB<10>

MAB<11>

MAB<12>

MAB<13>

MAB_BA<0>

MAB_BA<1>

MAB_BA<2>

CASB0#

WEB0#

DQSB1_DP

DQSB2_DP

DQMB<1>

DQSB2_DN

DQB<13>

DQB<10>

DQB<19>

DQB<23>

DQB<16>

DQB<17>

DQB<22>

DQB<18>

DQB<25>

DQB<24>

DQB<28>

DQB<1>

MAB<13>

DQB<6>

DQB<3>

DQB<29>

DQB<27>

DQB<31>

DQSB0_DN

DQMB<0>

DQSB3_DN

DQSB3_DP

DQSB0_DP

DQMB<3>

WEB0#

CKEB0

ODTB0

CSB0#_0

CLKB0_DP

CLKB0_DN

RASB0#

CASB0#

VM_RESET

VRAM_VREFD_B<3>

MAB<13..0>

MAB_BA<1>

MAB_BA<2>

MAB_BA<0>

MAB<12>

MAB<11>

MAB<10>

MAB<9>

MAB<8>

MAB<7>

MAB<6>

MAB<5>

MAB<4>

MAB<3>

MAB<2>

MAB<1>

MAB<0>

VRAM_VREFD_B<3>

VRAM_VREFC_B<0>

CLKB0_DN

VRAM_VREFC_B<2>

CLKB0_DP

VRAM_VREFD_B<1>

MAB<13..0>

VRAM_VREFC_B<0>

DQB<30>

DQB<5>

DQB<26>

DQB<0>

DQB<4>

DQB<7>

DQB<2>

2 1

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

2121

2 1

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

2 1

21

2 1

21

2121

2 1

21

2121

2 1

2121

2 1

IN

BI

IN

BI

IN

BI

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

BI

IN

BI

IN

BI

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

IN

BI

IN

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6865

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

6

P1V5S_DGPU

P1V5S_DGPU P1V5S_DGPU

P1V5S_DGPU

P1V5S_DGPU P1V5S_DGPU

P1V5S_DGPU

A3 CS

Block Diagram

2.2UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

0.1UF_16V_2

0.01UF_50V_2

0.1UF_16V_2

56_5%_2

0

2

1

3

4

5

7

10

8

9

11

12

13

10UF_6.3V_3

4.99K_1%_24.99K_1%_2

10UF_6.3V_3

243_1%_2

56_5%_2

4.99K_1%_24.99K_1%_2

0

2

1

4

3

5

7

6

8

9

10

11

12

13

4.99K_1%_24.99K_1%_2

10UF_6.3V_3

SAM_K4B1G1646D_HCF7_FBGA_100P

243_1%_2

4.99K_1%_24.99K_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

C5573

C5574

C5575

C5576

C5577

C5569

C5568

C5567

C5566

C5565

U5506

R5536R5537

C5579

C5515

U5507

C5578

R5538

R5547

C5519

R5546

R5534R5535

C5514

R5532R5533

C5513

C5572C5571

C5570

R5539

R5530R5531

C5512

58D4

64D7

58D4

58B1 65D4

65D8

58B1 65C8 65D4

58A1 58D1 64D4 65D8

65D4 65D4

65A6

65A8

58A1 58D1 64D4 64D7 65D4

58D1 64D4 64D7 65D4

65D8

58C1

58B1 65C4

58B1 65B4 65D4

58B1 65B5 65D4

58B1 65C4

58A1 65C4

58C1

58A1 62C4 62C7 63C4 63C8 64C4 64C7 65C4

65D8

65A4

58A1 62C4 62C7 63C4 63C8 64C4 64C7 65C8

58C1

58B1 65C8

58B1 65B4 65D8

58B1 65B5 65C8

58B1 65C8

58D1 64D4 64D7 65D8

58B1 65C8

58A1 65C8

58C1

58D1

58C1

58D4

65A3

DQB<62>

DQB<63>

DQB<58>

DQB<60>

DQB<57>

DQB<55>

DQB<54>

DQB<48>

DQB<50>

DQB<53>

DQB<49>

DQB<52>

DQB<51>

DQB<39>

DQB<37>

DQB<36>

DQB<34>

DQB<33>

DQB<32>

MAB<6>

DQB<59>

DQB<56>

DQB<61>

CLKB1_DPCLKB1_DN

MAB<13..0>

VRAM_VREFD_B<5>VRAM_VREFC_B<6>

VRAM_VREFD_B<7>

VRAM_VREFC_B<4>

MAB<0>

MAB<13..0>

MAB<1>

MAB<2>

MAB<3>

MAB<4>

MAB<5>

MAB<6>

MAB<7>

MAB<8>

MAB<9>

MAB<10>

MAB<13>

MAB<12>

MAB<11>

MAB_BA<1>

MAB_BA<2>

MAB_BA<0>

VRAM_VREFD_B<7>

DQMB<7>

DQSB6_DN

CKEB1

ODTB1

CSB1#_0

CLKB1_DP

CLKB1_DN

RASB1#

CASB1#

WEB1#

DQSB6_DP

DQSB7_DP

DQMB<6>

DQSB7_DN

VM_RESET

VRAM_VREFC_B<4>

MAB<0>

VRAM_VREFC_B<6>

VM_RESET

DQMB<5>

DQSB4_DN

CKEB1

ODTB1

CSB1#_0

CLKB1_DP

CLKB1_DN

RASB1#

MAB<1>

MAB<2>

MAB<3>

MAB<4>

MAB<5>

MAB<7>

MAB<8>

MAB<9>

MAB<10>

MAB<11>

MAB<12>

MAB<13>

MAB_BA<0>

MAB_BA<1>

MAB_BA<2>

CASB1#

WEB1#

DQSB4_DP

DQSB5_DP

DQMB<4>

DQSB5_DN

DQB<35>

DQB<46>

DQB<43>

DQB<47>

DQB<40>

DQB<45>

DQB<42>

DQB<44>

DQB<41>

DQB<38>

VRAM_VREFD_B<5>

2 1

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

2121

2 1

L9

L4

G2

G10

F10

E9

E3

D9

D2

B2

B10

T2

T10

P2

P10

M2

M10

J9

J3

G9

E2

B4

A10

H2

M9

H3

H10

F2

E10

D3

C2

C10

A9

A2

R2

R10

N2

N10

K9

K3

G8

D10

B3

T3

J4

K2

L10

J2

L2

J10

T11

T1

A11

A1

A4

B9

A3

A8

C3

C9

C4

D8

B8

C8

G4

F4

H8

G3

H9

H4

F9

F3

F8

E4

D4

E8

L3

K10

K8

J8

K4

M4

N9

M3

R4

T9

R3

R9

P3

P9

N3

P4

M8

T8

T4

N8

R8

L8

P8

N4

2 1

21

2 1

21

2121

2 1

2121

2 1

21

2121

2 1

IN

BI

IN

BI

IN

ININ

IN

BI

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

BI

IN

BI

NC

NC_CE1

NC_ZQ1

A0

VREFDQ

VREFCA

VSSQ#G10

VSSQ#E3

VSSQ#G2

VSSQ#F10

VSSQ#E9

NC_ODT

NC_CSI

RESET

DMU

DQSL

CKE_CKE0

ODT

CS

CK

DQU4

VDD#K9

VDD#R10

VDD#R2

VDD#N10

VDD#N2

RAS

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11

A12

A13

A14

A15_BA3

BA0

BA1

BA2

CAS

WE

DQSL

DQSU

DML

DQSU

ZQ_ZQ0

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU5

DQU6

DQU7

VDD#B3

VDD#D10

VDD#G8

VDD#K3

VDDQ#A2

VDDQ#A9

VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4

VSS#E2

VSS#G9

VSS#J3

VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2

VSSQ#D9

IN

BI

IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6866

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

WCM_2012_900T

SUYIN_020173GR004M555ZL_4P

P5V0A_USB3

Block Diagram

CS

A3

CN2001

L2001

30C5 51C2

USB_P2_DN

USB_P2_DP

USB_L_P2_DN

USB_L_P2_DP

1

4 G4

G3

G2

G1

2

3

21

34

VCC

GND G4

G3

G2

G1

DATA-

DATA+

BI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 9000~9999(SMALL BOARD)

POWER BUTTON

6867

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

SMDPAD_1P_40X120

PHP_PESD5V2S2UT_SOT23_3P_DY

DGND_PWRSW_DB

1000PF_50V_2_DY

FIX_MASK

SCREW540_700_NP_1P

MISAKI_NTC017_DA1G_E160T_6P

A3 CS

Block Diagram

FIX_MASK FIX_MASKFIX_MASKFIX_MASKFIX_MASK

DGND_PWRSW_DB

PAD9001

PAD9000

D9000

C9000

SW9000

S9001

S9000

FIX9005FIX9004FIX9003FIX9002FIX9001FIX9000

1

3

2

1

2 1

6

5

4

3

2

1

A B

DC

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

6868

X011310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002XXX

Block Diagram

CS

A3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

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Inventec Dakar 10F/FG Schematics. Www.s Manuals.com. 10f, 10fg Rx01 Schematics 1

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