Inventec Everest M Schematics. Www.s Manuals.com. Ra01 Schematics
User Manual: Motherboard Inventec Everest-M 6050A2447101 - Schematics. Free.
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8 7 6 5 4 3 2 1 D D C C EVEREST-M WS BULID B B 2010.01.04 A A INVENTEC TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 11:08:28 2011 EVEREST-M COVER PAGE CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 1 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D TABLE C B A PAGE 1. COVER PAGE 2. INDEX 3. BLOCK DIAGRAM 4. SMB DIAGRAM 5. POWER SEQUENCE BLOCK 6. POWER FLOW 7. PCB SCREW 8. POWER CHARGER 9. POWER BATTERY 10. POWER +3A/+5A 11. POWER +V1.5/+V0.75S 12. POWER VCCP/+V1.05_LAN_M 13. POWER +V0.85S/+V1.8S 14. POWER VCORE 15. POWER VCORE 16. POWER GPU NVVDD 17. POWER +V3S/+V5S/+V1.5S 18. POWER SEQ 19. POWER SEQ 20. CPU 1 21. CPU 2 22. CPU 3 DRAM 23. CPU 4 POWER 24. CPU 5 POWER 25. CPU 6 GND 26. DDR3 DIMM0 27. DDR3 DIMM1 OF CONTENTS PAGE 55. MINI1 WLAN/Debug Card 56. MINI2 3G 57. HALL SENSOR 58. LED 59. CLOCK GENERATOR 60. XDP 61. ME JTAG 62. PICK BUTTON BOARD 63. TOUCH PAD SW BOARD 64. POWER BUTTON BOARD 65. CARDREADER & USB BOARD 66. EMI 67. GPU SW/POWER 68. GPU-1 69. GPU-2 70. GPU-3 71. GPU-4 72. GPU-5 73. VRAM 74. VRAM 75. VRAM 76. VRAM PAGE 28. PCH 1 29. PCH 2 30. PCH 3 31. PCH 4 AXG 32. PCH 5 USB 33. PCH 6 MISC 34. PCH 7 POWER 35. PCH 8 POWER 36. PCH 9 GND 37. EC 38. FAN & THERMAL 39. LAN 40. RJ45 & TRANSFORMER 41. AUDIO CODEC 42. AUDIO AMP 43. TPM 44. LCM CONN 45. CRT CONN 46. HDMI CONN 47. DP CONN 48. eDP CONN 49. DB CONN USB & CARDREADER 50. SATA HDD/SSD & ODD CONN 51. E-SATA CONN 52. USB CONN 53. K/B & TP/B CONN 54. BLUETOOTH CONN INVENTEC SIZE C CHANGE 7 6 5 4 B A EVEREST-M INDEX TITLE 8 C 3 by Frank Hu DATE Mon Dec 27 16:49:48 2 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 2 97 of 1 REV A01 8 7 6 5 4 IVY EDP MUX 3D PANEL 15.6 eDP PERICOM WXGA LED BRIDGE 204-PIN X 37.5 HDMI HDR HDMI 1.4 ATI WHISTLER X 5 mm 60-PIN R CPU XDP (TEST PEGX16 FDI DMI JTAG XT 60-PIN PCH XDP (TEST RGB JTAG C HDR(DONGLE) HDMI INTERNAL (TEST 1.1 DP PCH LVDS LVDS (TEST Gbe RJ45 AUDIO ONLY) HDR (100/1000) LEWISVILLE INTEL PCIE_3: PCIE_4: CARD CONNECTOR 25 X 25 X 2.3 SPI mm FLASH 8MB USB_0 USB_2 USB_1 USB_5 USB_10 USB_12 USB_13 USB 2.0 PCIE LPC TPM V1.2 SLB9635TT1.2_FW3.17 CARD READER RESERVE FOR USB3.0 RESERVE FOR USB3.0 eSATA PORT Minicard WLAN Webcam Bluetooth Minicard 3G SATA3_0: SATA3_1: SATA2_2: SATA2_3: SATA2_4: SATA USB3.0 CONN B IN WINB_W25Q64BVSSIG TI_TUSB7320 CONN A C HEADPHONE/LINEOUT PCIE_6 PCIE_1 USB 3.0 EXT MIC ALC269Q_VC SPI TDP 3.9W 82579LM_BAM271 WIFI 3G/mSATA IN COUGAR POINT ONLY) Phy MIC CODEC REALTEK HDA B SIM ONLY) RGB HDR DISPLAYPORT 1.4 ONLY) HDR RJ-11ME JTAG LS (TEST R D ONLY) 2.0 35W 29MM X 29MM HDR VGA SODIMM X2 MAX MEMORY 8GB X2 JTAG AMD GDDR5 (1600MHZ) VT & TXT 37.5 1 DDR3@1.5/0.75V DUAL CHANNEL QC 45W OR DC 35W VRAM*4(64Mb*32) TOTAL:1GB 2 SOCKET-RPGA989 eDP D 3 B SSD HDD ZERO POWER ODD eSATA mSATA PCIE_2 RTS5209 A EC WINDBOND BATTERY CHARGER & DC/DC & IMVP A SPI SPI Flash 1MB WINB_W25Q80BVSSIG NPCE791LA0DX 7 LI-ION BATTERY 6-Cell KEYBOARD INVENTEC TOUCH PAD TITLE EVEREST-M BLOCK DIAGRAM SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Dec 27 16:50:03 2 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 3 97 of 1 REV A01 8 7 6 5 +V3A 4 3 2 +V3S PCIE +V5S RES 2.2K RES 2.2K RES 2.2K RES 2.2K CK505 D SMB_CLK SMB_CLK SMB_DATA SMB_CLK_S2 SSM3K7002 SMB_DATA 1 SO-DIMM SMB_DATA_S2 SSM3K7002 0 SO-DIMM 1 SATA 1 USB3.0_TUSB7320 0 SSD 2 CardReader_RTS5209 1 HDD 3 WLAN 2 ODD 4 MINICARD3G 3 eSATA 5 NC 4 mSATA 6 LAN 5 NC 7 NC 8 NC D XDP SMB_CLK_S3 USB PEG SMB_DATA_S3 0 Reserve eSATA for USB3.0 1 MINICARD 2 Reserve for USB3.0 WIFI 3 NC 4 NC 5 MINICARD 6 NC 7 NC 8 NC 9 NC C PCH SMB_CLK_A1 +V3A RES 2.2K SMB_DATA_A1 MINICAR +V3LA 3G RES 2.2K RES 3.3K RES 3.3K 10 SML0CLK B SML0DATA SCL1 SML0_CLK LEWISVILLE SML0_DATA SDA1 EC_SMB1_CLK 11 NC 12 BLUE TOOTH 13 MINICARD 3G BATTERY EC_SMB1_DATA B +V3LA EC RES 2.2K RES 2.2K +V3A RES 2.2K +V3LA RES 2.2K RES 1.8K SML1DATA WEBCAM LAN PHY +V3A SML1CLK C WLAN RES 1.8K CHARGE IC SML1_CLK SSM3K7002 EC_SMB3_CLK SSM3K7002 EC_SMB3_DATA SML1_DATA EC_SMB2_CLK THERMAL IC SCL2 A SDA2 A EC_SMB2_DATA GPU THERMAL INVENTEC EVEREST-M SMB DIAGRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Dec 27 16:50:16 2 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 4 97 of 1 REV A01 8 7 6 5 4 3 2 +V3LA 1 +V3S SLP_S3#_5R PC6014 AM4825P D ADAPTER +V5A 5/3.3V PMOS 0.01 OHM ADP_PRES +V5S (TPS51125) AM4825P PMOS D PC6014 KBC_PW_ON SLP_S3#_5R SLP_S3#_5R +V1.5 +VPACK VO 0.01 OHM G2997 +V1.5S TPS51218 CHARGER EN_PSV PC6014 C BATT_CLK BATT_DATA +V0.75S SLP_S5#_5R C SCL SDA ACIN# ACOK +V1.05S VO TPS51218 GFX_VDD_PG B PGOOD EN EN_PSV +V1.05_VCCP +GFX_VDD TPS51217 B VO TPS51218 VTT_SELECT D0 EN_PSV +VCC_CORE VCCSA_PG H_PROCHOT# +V0.85S VR_HOT# D0 A VCCDRE_EN EN_PSV VOUT VR_ON VR_SVID_DATA VDIO VR_SVID_CLK VCLK VR_SVID_ALRT# ALERT# +VGFX VR_PWRGD A +GFX_PWRGD MAX17039 VO INVENTEC EVEREST-M TITLE POWER SEQUENCE BLOCK SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Dec 27 16:50:27 2 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 5 97 of 1 REV A01 8 7 6 5 4 3 2 1 EVEREST PWROWSEQUENCE VBAT VADPTR (-7START) VPACK VBAT V5LA VCC VSEN V3LA (-5) V02 EN2 VCC V5A MAX_MAX17435ETG VBAT GMT_G686LT11U (-6) (-3) (-1) V01 D V5LA ACIN ACOK# MINICARD TI_TPS51125 (-4) +V5AUXON RESET# EN1 ACPRES LAN XDP VGA RST# RST# TPM (-5) RST# VREG5 RST# X2 D RST# VCORE NMOS BUFFER PLT_RST# (21) EC_PWRSW# (2) LRESET# CPU RSTIN# BUF_PLT_RST# PLERST# PM_DRAM_PWRGD (20) SM_DRAMPWROK SVID DRAMPWROK V5LA (17) SVID PWRBTN# GPIO36 H_CPUPWRGD (16) SM_DRAMPWROK PROCPWRGD (1) GPIO50_TD0 ACPRES RSMRST# RSMRST# SLP_S5#_3R GPIO43_TMS SLP_S4#_3R GPIO03 C GPIO32_D_PWM SLP_S4# SLP_LAN#_3R (5) SLP_S3#_3R (5B) PWRGD EN SLP_A_3R V5A VBAT VIN VCC (4) INVERTER SLP_S3_5R V1.5 VIN V5A TPS51218DSCR SLP_LAN#_3R GPIO75 EC AND GATE IMVP7 (6) (3A) V3A(-1) PM_APWROK SLP_S3# 99ms B SVID (12) MAIN_PWRGD GPIO02 C VCORE_PWRGOOD (18) SYS_PWROK APWROK DA2_GPIO96 (19) SLP_A# DAO_GPIO94 EC_PW_ON (-2) ALLSYS_PWROK VCORE SLP_LAN# SLP_A_3R (15) PWROK (4) PSDAT2_GPIO27 NMOS EC_PCH_PWROK PCH SLP_S5# (3) EN (3B) M_VREF CLK V0.75S GMT_G2997F6U V1.5_PG PGD VCC EN V3A EN V3A V1.05_LAN_M (4A) VIN VIN (4A) V3.3M V1.05M INVERTER AO4406 VCC VIN G5694F11U B AM3423P (5A) EN EN EN EN AM3423E V1.05S_VCCP PGD V0.85S (7) V1.05S VIN V5A V3LA VIN VIN PGD AO4406 EN TI (11) TPS51218DSCR VDDR_PWRGD EN (0) PWR_SWIN#_3 (7) V5S AM3423P GPIO01 AM3423P EN GPO82_TEEST# GPO84_XORTR# (11) VIN (7) V3S V1.05S_VCCP GMT G5694F11U V1.05_LAN_VR_PWRGD EN (7) V1.8S AND GATE PGD EN TI TPS51218DSCR EN SLP_S3#_5R V1.5 V1.5 (8) V1.5S (10) V3.3M (4A) +V1.05S_VCCP_EN (9) VIN A VIN AO4406 EC_DGPU_PWR_EN# (13) (8) V1.5_CPU AO4406 EN SLP_A_3R VIN AND GATE AND GATE VCC PGD (5M) PM_APWROK (5B) V1.5 VBAT (14) GPU_VDD V1.05S (14) GPU_1.5S VIN SEMTECH SC475A EN (14) GPU_V3S VIN AM4430N EN SLP_S3#3R V3S (14) GPU_1.5S VIN AM4430N EN INVENTEC AM3423P EN EVEREST-M POWER FLOW TITLE (15) EC_PCH_PWROK SIZE C CHANGE 8 7 A AND GATE (5A) EN V5A AND GATE 6 5 4 3 by Frank Hu DATE Mon Dec 27 16:50:39 2 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 6 97 of 1 REV A01 8 7 1 6 FIX1 1 FIX2 FIX_MASK FIX_MASK 1 FIX3 1 FIX4 FIX_MASK FIX_MASK 5 1 FIX5 1 FIX_MASK 4 FIX6 1 FIX_MASK FIX7 FIX_MASK 1 3 2 1 FIX8 FIX_MASK D D SCREW330_600_800_1P 1 SCREW330_600_800_1P S4 SCREW300_700_1P SCREW300_1000_1P 1 S22 SCREW330_600_800_1P 1 SCREW330_600_800_1P CPU 1 S24 1 1 S18 S10 S1 S23 S25 S26 SCREW300_1000_1P SCREW300_1000_1P SCREW300_1000_1P SCREW300_1000_1P SCREW500_1000_1P SCREW300_1000_1P C 1 1 1 1 S20 1 S12 1 C MB S3 S14 MINI 1 SCREW120_500_0_1P S16 SCREW120_0_500_1P SCREW120_0_500_1P 1 1 S7 S27 SCREW120_0_500_1P SCREW120_0_500_1P 1 PCH S19 S33 SCREW320_500_400_1P SCREW320_500_400_1P SCREW320_500_400_1P 1 S11 1 S9 SCREW320_500_400_1P 1 1 FAN B S17 1 B CARD GPU A A INVENTEC EVEREST-M PCB SCREW TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:56 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 7 97 of 1 REV A01 8 7 6 5 4 3 2 1 1 1 1 2 3 4 D 1 2 3 4 1 R6017 RSC_0603_DY 2 C6035 1 C6033 1 2 10PF_50V_2 R6019 2 2 1 G1 G2 8A_125V FUSE6000 CN6000 G1 2 1000PF_50V_2 RSC_0402_DY G2 R6018 RSC_0603_DY 1 C6003 CSC0402_DY 2 D 2 ACES_91302_0047L_1_4P NEAR EC 3A R6005 4.7K_5%_3 2 2 1 2 R6010 1K_1%_2 Q6004 1 IN 1 1 ACIN BST 1 LX C 2 2 A1 A2 2 1 ACOK PGND-PAD 4 LDO CSIP OUT 1 1 2 2 C6021 1UF_10V_2 2 1UF_10V_2 C6001 2 0.1UF_25V_3 2 4.7UF_25V_5 4.7UF_25V_5 CSIN 21 VAA 23 GND BATT CC 12 11 13 17 2 0.1UF_25V_2_DY 2 C6813 0.01UF_50V_2 ITHR 6 20 2 C6817 2 4.7UF_25V_5 2 CHG_CHG_SEN_P 4.7UF_25V_5 CHG_CHG_SEN_N 2 ADAPTLIM EN SDA 1 C6016 B R6004 4.7_5%_3 2 D6003 SBR3U40P1 CSC0402_DY 1 1 1 1 FDMC8884 1 2 4 0.02_1%_6 Q6001 4 3 2 18 R6001 1 3 2 5 6 7 8 C6007 SCL 4.7UF_25V_5_DY L6000 VCC 1 2 C6000 2 1 C6814 IINP 22 1 PCMC063T_3R3MN S C6025 C6005 4 3 2 1 G 1 R6014 10_5%_2 2 7 9 CHG_HG 8 CHG_SW 5 CHG_LG 25 2 10K_5%_2 D6001 BAT54C_30V_0.2A 17435_LDO R6007 1 0.1UF_25V_3 1 D C6028 0.1UF_25V_3 8> DLO 10 2 C6002 2 NMOS_4D3S B 1 C6006 R6000 1 1 S 1 5 6 7 8 Q6000 FDMC8884 4.7_5%_3 DHI R6013 4.3K_1%_3 2 1UF_25V_3 19 3 1 2 1UF_25V_3 D 2 (1.68V) C6029 G BAV99 R6008 10K_5%_2 RSC_0603_DY 2 C6023 NMOS_4D3S 2 3 SSM3K7002BFU R6006 2 P_GATE D6000 1 2 0_5%_2_DY C6009 D 1 S G 2A 20_5%_2 R6045 1 1 2 10_5%_5 3 2 1R6044 1 1 R6016 R6012 45.3K_1%_2 C CHG_VBAT_SEN_P NEAR IC 0_5%_2 1 TPC8121 PAD6000 POWERPAD_2_0610 1 2 0_5%_2_DY 0.01UF_25V_2_DY 0.1UF_25V_2 2 R6043 1 2 2 R6036 150_5%_3 R60422 1 C6812 1 G 8 7 6 5 1 1 2200PF_50V_2 0.1UF_25V_2 CHG_VBAT_SEN_N 1 AM4410NC AM4410NC D PMOS_4D3S NMOS_4D3S C6030 RSC_0402_DY 0.01_1%_6 S 2 C6811 2 4 R6020 2 1 3 2 23.106V) : G NMOS_4D3S 1 Q6005 1 2 3 4 R6046 1 2 3 4 1 24.67V) MIN S 3 14 16 15 MAX : (OVP D 2 (OVP G 8 7 6 5 8 7 6 5 DCIN PDSL CSSP CSSN 2 C DIODES_SMAJ20A_13_F_2P D6004 3 4 L6001 D 1 2 1 1 S 1 1 2 3 4 NFE31PT222Z1E9L Q6002 1 Q6003 24 U6000 MAX_MAX17435ETG+_TQFN_24P C6022 1UF_10V_2 1 P3V3_AL 2 1 1 0X15 A 8.4V : R6003 10K_5%_2 0X14 40D0H 512MA : 1.5A : 12.6V : 3140H 16.8V : 41A0H 3A : R6002 10K_5%_2 2 1 C6008 2 0.1UF_16V_2 C6026 0.1UF_16V_2 1 2 NEAR EC 2 A 0200H_512MA 0600H_1.54A 0C00H_3.07A 1 TP6002 17435_LDO INVENTEC 8> 1 OUT EVEREST-M POWER CHARGER TITLE TP6000 SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 10:52:57 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 8 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D FUSE6100 LITTLEFUSE_R451015_15A_65V 1 1 C6106 2 1000PF_50V_2 2 CN6100 SYN_200045GR009G15JZR_9P R6110 1 2 1 R6109 102K_1%_3 715K_1%_2 2 1 2 360K_1%_2 R6100 R6101 R6102 1 1 1 2 3 4 5 6 7 8 9 R6108 1 2 1K_5%_2 2 33_5%_2 2 33_5%_2 1 2 BATT+ ID B-I TS SMD G SMC G GND G GND G G1 G2 G3 G4 1 1 D6100 EZJZ0V500AA C BATT+ D6099 EZJZ0V500AA_DY D6101 EZJZ0V500AA C 2 2 B B 1 R6105 10K_5%_2 2 D6102 NC 2 1 3 1 R6104 510K_1%_2 U6100 1 2 3 BAT54_30V_0.2A_DY RESET MR 5 VSEN 4 GND VCC 2 R6039 1 2 0_5%_2 1 GMT_G686LT11U_SOT23_5P 1 C6107 2 0.1UF_16V_2 R6103 100K_1%_2 2 A A INVENTEC EVEREST-M POWER BATTERY TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 10:53:36 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 9 97 of 1 REV A01 7 6 5 4 Q6200 8 7 6 5 1 R6201 G 1 1 2 2 1 POWERPAD_2_0610 R6202 200_5%_2 1 2 2 3 0_5%_2 1 C6211 2 2200PF_50V_2 3 D 1 C6215 G 2 CSC0402_DY VCLK IN 10< 37> EC_PW_ON# 1 IN G S S 1 10> Q6805 D Q6202 2 AON7410 R6200 2 SSM3K7002BFU 2 SSM3K7002BFU 1 C6216 3 1 R6210 120K_1%_2 G 2 SSM3K7002BFU 2 D6202 P5V_A BAV99 2 S IN 3 EC_PW_ON# 37> 0.1UF_25V_2 2 1 D Q6203 D 1 C6217 2 0.1UF_25V_2 10< 1 D 100K_5%_2 1 2 3 4 S NMOS_4D3S 100K_5%_2 2 PAD6205 D 1 R6212 3 2 1 1 2 D6203 BAV99 1 2 C6218 C6219 0.1UF_25V_2 3 8 1 0.1UF_25V_2 C6220 2 1UF_25V_3 1 2 1 C A1 C 3 D6201 C BAT54C_30V_0.2A 1 A2 >>VRE3 OR VRE5=OOA >>VREF=ASKIP >>GND=PWM 2 1 1 SKIPSEL 1 2 PAD6202 POWERPAD_2_0610 1 R6209 130K_1%_2 2 2 2 PAD6203 >>VRE5=365/460 >>VRE3=300/375 >>VREF=245/305 >>GND=200/250 2 POWERPAD_2_0610 TONSEL B 2 1 PGOOD VBST1 DRVH2 DRVH1 LL1 LL2 DRVL2 DRVL1 24 23 C6213 22 21 VR5A_HG1 20 VR5A_PH 19 VR5A_LG 5 6 7 8 0.1UF_25V_3 7A 1 L6200 PCMC063T_3R3MN 1 13 14 15 16 17 18 + 1 G POWERPAD_2_0610 2 1 R6206 10K_1%_2 2 2 RSC_0603_DY 2 1 2 3 4 2 A 2 4 3 2 1 PAD6204 POWERPAD1X1M + R6037 2 15.4K_1%_2 S 1 G C6202 330UF_6.3V 10< 1 R6205 Q6207 C6200 330UF_6.3V VCLK S PAD6201 1 2 1 OUT 2 4.7UF_25V_5 2 R6208 10K_1%_2 2 2 TPC8A05_H 1 1 2 C6214 5 6 7 8 8 7 6 5 TPC8A05_H 1 1 4.7UF_25V_5 4 3 2 1 2 C6201 D Q6205 2 1 2 4.7UF_25V_5 D R6207 6.8K_1%_2 A VO1 VBST2 U6200 TI_TPS51125_QFN_24P 1 AON7410 VREG3 1 PCMC063T_3R3MN Q6206 6 5 4 3 2 1 25 NMOS_4D3S G S 2 3.8A C6203 S 2 2 L6201 1 G C6212 VO2 VCLK VREG5 VIN GND SKIPSEL EN0 7 8 9 VR3AL_HG 10 VR3AL_PH 11 VR3AL_LG 12 0.1UF_25V_3 1 0.22UF_6.3V_2 NMOS_4D3S AON7410 ENTRIP1 VFB1 VREF TONSEL VFB2 ENTRIP2 TML Q6204 1 2 3 4 POWERPAD_2_0610 2 8 7 6 5 D 4.7UF_25V_5 2 4.7UF_25V_5 2 C6204 10A 1 C6209 D C6205 PAD6200 1 1 1 4A 1 2 C6206 1 CSC0805_DY C6210 2 R6204 RSC_0402_DY 1 2 1UF_6.3V_2 1 C6208 1 2 2.2UF_25V_5 2 C6207 INVENTEC 10UF_6.3V_3 EVEREST-M POWER +3A/+5A TITLE SIZE C CHANGE 8 7 B 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 10:54:36 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 10 97 of 1 REV A01 7 6 5 4 3 2 1 1 1 8 2 PAD6301 POWERPAD_2_0610 D 22A 2 D 3.7A Q6300 TPCA8065_H 2 37< 11< 30> SLP_S4# V1.5_PG 1 IN U6302 TI_TPS51218DSCR_SON_10P 1 2 3 4 5 OUT 2 PAD6303 R6301 2.2_5%_3 1 2 2 PGOOD VBST TRIP DRVH EN SW VFB V5IN DRVL 1 2 1 2 5 6 7 8 1 3 PAD6302 L6300 2 4 1 1 2 2 C POWERPAD_2_0610 R6047 PCMC104T_1R0MN D RF 10 9 VR15_HG 8 VR15_PH 7 6 VR15_LG C6305 0.1uF_25V_3 1 4.7_5%_3 2 1 2 95.3K_1%_2 2 G C6302 2.2uF_6.3V_3 4 3 2 1 S R6310 200K_1%_2 R6311 Q6301 TPCA8A02_H 1 R6304 C6815 11.5K_1%_2 2 2200PF_50V_2 1 + 2 2 1 1 1 11 C6301 CSC0402_DY 2 POWERPAD_2_0610 R6302 0_5%_2 C C6309 4.7uF_25V_5 1 2 18< 2 1 C6300 4.7uF_25V_5 4 3 2 1 R6314 RSC_0402_DY GND 2 1 C6303 4.7uF_25V_5 S G 1 1 NMOS_4D3S P3V3_S 5 6 7 8 D 3.7A C6304 560uF_2.5V 2 1 R6303 10K_1%_2 2 B B 37< 37< 18< 17< 30> SLP_S3# IN 11< 1 SLP_S4# 30> R6307 IN P3V3_A P1V5 2 +V1.5S_CPUDDR_PG IN 1 R6306 11 10 9 8 7 6 2 0_5%_2 20/20 mil C6312 1000PF_50V_2_DY A 1.5A U6300 0_5%_2_DY TML VDDQSNS VIN VLDOIN S5 GND S3 VTT PGND VTTSNS 1 2 3 4 5 PAD6300 1 2 1 C6311 0.1UF_16V_2 POWERPAD_2_0610 1 1 C6308 2 2 1.5A 2 2 VTTREF GMT_G2997F6U_MSOP10_10P 1 1 2 1 C6307 22uF_6.3V_5 C6306 2 22uF_6.3V_5 A 1uF_10V_2 INVENTEC EVEREST-M POWER +V1.5/+V0.75S TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:25:55 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 11 97 of 1 REV A01 7 6 5 4 3 2 1 1 8 2 VBST TRIP DRVH EN SW V5IN VFB RF DRVL 10 9 VRVCCP_HG 8 VRVCCP_PH 7 6 VRVCCP_LG 1 2 1 2.2_5%_3 C6406 2 4.7UF_25V_5 1 C6401 2 4.7UF_25V_5 L6403 1 3 1 1 2 2 POWERPAD_2_0610 PAN_ETQP4LR36WFC_4P 2 2.2UF_6.3V_3 2 + 560UF_2.5V TPCA8057_H G 2 C6407 Q6400 2 C6411 S 1 4 3 2 1 1 11 470K_1%_2 44.2K_1%_2 28A 5 6 7 8 1 2 R6411 R6405 2 2 PAD6401 2 4 D CSC0402_DY 1 1 1 POWERPAD_2_0610 2 NMOS_4D3S 1 C6413 D PAD6402 1 4 3 2 1 0.22UF_25V_3 C6410 2 1 1 0_5%_2 PGOOD GND 1 2 3 4 5 OUT 2 R6403 C6403 4.7UF_25V_5 S U6400 VTT_PG Q6401 1 TPCA8065_H G TI_TPS51218DSCR_SON_10P R6402 POWERPAD_2_0610 2 D NMOS_4D3S 3.3A R6400 10K_5%_2 1 2 5 6 7 8 1 13< 1 P3V3_S D PAD6403 R6410 C6415 0.1UF_10V_2_DY RSC_0402_DY C 2 2 C 1 R6417 2 IN VCC_SENSE_VTT 23> 1 1 200_1%_2 R6413 C6414 9.53K_1%_2 2 2 1000PF_50V_2_DY 1 R6414 20K_1%_2 R6415 1 IN VSS_SENSE_VTT 2 1 23> 2 0_5%_2 R6416 100_5%_2 B 2 B P3V3_A 0.5A +V1.05_LAN_M 1 1 C6452 2 10UF_6.3V_3 1.5A U6401 GMT_G5694F11U_SOP_8P R6452 10_5%_3 8 2 TML VIN LX 9 7 PAD6400 L6450 1 2 1 1 2 2 LTF5022T_2R2N3R2_LC POWERPAD_2_0610 30> SLP_LAN# 1 IN 5 2 A 1 C6453 2 0.1UF_16V_2 EN 6 0_5%_2 GND 19< FB PGND R6454 37< VCC 3 1 REF 1 4 R6450 3.09K_1%_2 2 2 1 C6454 2 0.1UF_16V_2 1 C6451 2 CSC0402_DY 1 C6450 2 22UF_6.3V_5 A 1 R6451 10K_1%_2 2 INVENTEC EVEREST-M TITLE POWER VCCP/+V1.05_LAN_M SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:26:41 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 12 97 of 1 REV A01 8 7 6 5 4 3 2 1 1 PVBAT 2 POWERPAD_2_0610 2 1 PAD6500 P3V3_A 5 6 7 8 D 1 Q6500 U6500 AON7410 TI_TPS51217DSCR_SON_10P 2 VBST 10 R6500 1 C6503 2 2 TRIP 3 EN 4 VFB 5 TRAN DRVH 9 VR85_HG SW 8 VR85_PH 1 2 GND 1 PAD6503 1 2 1 2 2 POWERPAD_2_0610 Q6501 TPC8A05_H 1 C6504 2 2.2UF_6.3V_3 1 2 330UF_2V_9MR_PANA_-35% C6508 S 2 D VR85_LG G CSC0402_DY R6508 78.7K_1%_2 6 2 PCMC063T_3R3MN 5 6 7 8 11 C6505 DRVL C6500 4.7UF_25V_5 L6500 1 D 1 7 2 1 4 3 2 1 2 0_5%_2 V5IN C6502 4.7UF_25V_5 4 3 2 1 1 R6502 2 0.22UF_25V_3 1 0_5%_3 2 1 S PGOOD C6501 4.7UF_25V_5 6A G 1 1 + R6501 10K_5%_2 1 NMOS_4D3S D 1 R6509 1K_1%_2 C6507 R6503 RSC_0402_DY 2 0.1UF_10V_2_DY 2 2 C 1 1 C6510 2 47PF_50V_2 R6506 C 2 1 200_1%_2 1 C6506 P5V_A R6504 6.49K_1%_2 1000PF_50V_2_DY 2 2 1 1 R6510 20K_1%_2 1 R6507 40.2K_1%_2 2 R6505 20K_1%_2 2 3 2 1 B Q6502 LMBT3904LT1G 1 Q6503 G SSM3K7002BFU S 200_1%_2 3 1 D R6511 E 2 IN VCCSA_SEL C 24> 2 2 B B LOW HIGH 0.9V - 0.8V 1.6A 1 1 C6514 10UF_6.3V_3 10K_5%_2 2 3A U6502 GMT_G5694F11U_SOP_8P R6516 R6517 10_5%_3 2 1 2 8 9 7 TML VIN LX PAD6501 L6502 1 2 1 1 2 2 LTF5022T_2R2N3R2_LC 1 C6515 2 0.1UF_16V_2 GND PGND EN 1 C6513 2 CSC0402_DY R6514 13K_1%_2 2 REF POWERPAD_2_0610 1 4 FB 6 5 VCC 2 3 1 A 1 C6511 2 0.1UF_16V_2 A 1 C6512 2 22UF_6.3V_5 1 R6515 10K_1%_2 2 INVENTEC EVEREST-M TITLE POWER +V0.85S/+V1.8S SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:27:17 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 13 97 of 1 REV A01 8 7 6 5 4 3 2 1 +VBAT_CPU PVBAT PAD6600 10A 1 1 2 2 POWERPAD_2_0610 P5V_A U6602 MAX_MAX8791GTA+_TQFN_8P 14< 14< +VBAT_CPU 1 DL 1 C6619 2 1UF_6.3V_2 GND IN IN IN IN VRCPU_HG3 CPU_BST3 VRCPU_PH3 VRCPU_LG3 15< 15< 15< 15< 1 C6601 2 1 C6600 2 4.7UF_25V_5 1 C6602 4.7UF_25V_5 4.7UF_25V_5 1 C6603 1 C6604 1 C6605 C6606 2 2 2 2 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 2 1 C6607 2 4.7UF_25V_5 D PVAXG R6624 4.87K_1%_2 0_5%_2 2 2 2 2 LX 1 8 1 7 4 3 1 R6620 R6622 178K_1%_2 VDD P5V_A P3V3_A 1 DH BST PAD D 10RG PW M SKIP 9 FOLLOW BERLIN 2 6 5 IN IN PH3_PWM PH3_SKIP# CCVA 14< IN VBOOTA 14< IN SRA 14< 14< 1 C6618 2 2.2UF_6.3V_2 P3V3_S 470PF_50V_2 2 R6619 0_5%_2 1 R6618 115K_1%_2 2 1 R6610 2K_5%_2 2 2 15< VRCPU_PH2 IN 14< P5V_A 14< B IMAXA IMAXB 14< 1 2 R6623 10K_5%_2 1 2 R6038 2 C6608 0_5%_2 IN IN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10RG P3V3_A P5V_A 1000PF_50V_2 R6602 2 100_1%_2 LXA2 VBOOTB C VRA_READY VBOOTA VRB_READY CCI2 CSPA1 CCI1 CSNA1 SRA CSNA2 SRB CSPA2 THERMA U6600 CSPA3 CSNA3 THERMB N.C. MAX_MAX17039GTN+_TQFN_56P IMAXA FBB IMAXB GNDSB TMAX IMONB VR_HOT# AGND CCVB LXB GND C6610 470PF_50V_2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 57 IN IN VBOOTB 14< VBOOTA IN IN IN IN SRA 14< SRB 14< THERMA 14< THERMB 14< IN IN IN IN IN FBB 14> GNDSB 14> IMONB 14< CCVB 14< VRAXG_PH1 1 2 1 2 IN VCCSENSE 23> 14< C6611 470PF_50V_2 1 TP6600 B 15< C6614 2 1 R6608 IN IMAXB 14< IN IMONB 14< IN CCVB 14< IN VBOOTB 14< IN SRB 14< IN THERMB 14< TONA TONB TONB 14< P5V_A 14< 14< FBA IN GNDSA IN 1 R6614 10_1%_2 2 1 2 1 2 R6612 10_1%_2 C6613 P5V_A 1000PF_50V_2 A 1 2 1 1 1 1 TP6601 TP24 1 1 A IN 1 R6616 5.1K_1%_2 14< 14< 2 2 R6625 4.87K_1%_2 1000PF_50V_2 IN IN IN IN IN 0_5%_2 15< VRAXG_LG1 15< GPU_BST1 15< VRAXG_HG1 R6617 178K_1%_2 2 CATCH R 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FOLLOW BERLIN +VBAT_CPU OUT R6626 100K_5%_2 1 VSSSENSE 23> 2 2 2 R6611 2K_5%_2 IN 1 CATCH R 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 1 2 R6601 10_1%_2 DHA2 BSTA2 DLA2 VDDA DLA1 BSTA1 DHA1 LXA1 PWM_OUT DRSKIP CCVA IMONA GNDSA FBA R6621 20.5K_1%_2 1 C6615 GNDSB ALERT# VDIO VCLK VCC TONA TONB CSPB CSNB VR_ENABLE DLG VDDB DLB BSTB DHB 1 R6605 1 OUT 100_1%_2 R6603 10_1%_2 9.53K_1%_2 THERMA 14< IN FBB 1 1 IN 14< VRCPU_LG1 15< CPU_BST1 15< VRCPU_HG1 15< VRCPU_PH1 15< PH3_PWM 14< 14< PH3_SKIP# CCVA 14< 14< IMONA GNDSA 14< FBA 14< 14< VRCPU_HG2 15< CPU_BST2 15< VRCPU_LG2 15< 14< IMONA IN IN IN IN IN IN IN IN IN IN IMAXA IN IN IN IN IN R6604 2 1 TONA 14< IN C 1000PF_50V_2 2 C6609 P5V_A C6612 R6609 R6606 115K_1%_2 R6627 100K_5%_2 C6616 2 2 2.2UF_6.3V_2 2 2 R6607 0_5%_2 470PF_50V_2 2 20.5K_1%_2 1 1 C6617 2 2 2.2UF_6.3V_2 INVENTEC EVEREST-M POWER VCORE TITLE IN 8 7 VSSAXG_SENSE 24> SIZE C 14< CHANGE 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:28:44 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 14 97 of 1 REV A01 8 7 6 5 4 3 2 1 PVCORE +VBAT_CPU 1 1 2 +VBAT_CPU 1 VRCPU_PH2 1 2 Q6705 TPCA8057_H 3 4.7_5%_3 1 2 IN 1 1 3300PF_50V_2 2 1 C6709 4 3 2 1 R6708 2 3.6K_1%_2 10K_5%_NTC R6709 2.37K_1%_2 1 2 3300PF_50V_2 R6712 1 R6713 1 2.37K_1%_2 2 2 R6707 S R6706 2 4 PAN_ETQP4LR36ZFC_4P R6711 D VRCPU_LG2 G S G C6706 2 1 5 6 7 8 14< 4 3 2 1 L6702 1 3 PAN_ETQP4LR36ZFC_4P 4.7_5%_3 D 4 3 2 1 IN IN C6708 R6714 1 2 3.6K_1%_2 1 2 1 2 10K_5%_NTC R6715 2 RSC_0402_DY RSC_0402_DY C 2 VRCPU_HG2 14< NMOS_4D3S Q6703 TPCA8057_H 2 4 14< 0.22UF_25V_3 Q6704 TPCA8065_H R6705 D IN NMOS_4D3S VRCPU_LG1 L6701 C6711 3 60A 1 3 5 6 7 8 14< 2 1 4 3 2 1 IN IN 470UF_2V S VRCPU_PH1 2 G 14< VRCPU_HG1 R6716 1 2.2_5%_3 G 14< 1 IN Q6702 TPCA8065_H S C6707 0.22UF_25V_3 + + 2 CPU_BST2 D 2.2_5%_3 D 14< NMOS_4D3S IN 2 D CPU_BST1 5 6 7 8 5 6 7 8 R6710 NMOS_4D3S 14< 1 C6704 C6701 1500UF_2V 1 2 C6710 C 2 0.47UF_6.3V_2 0.47UF_6.3V_2 +VBAT_CPU +VBAT_CPU 5 6 7 8 1 0.22UF_25V_3 L6700 1 3 5 6 7 8 2 4 VRAXG_HG1 VRAXG_PH1 5 6 7 8 D 4.7_5%_3 VRAXG_LG1 IN Q6707 TPCA8057_H 12 14< S G 2 R6701 2.37K_1%_2 1 1 R6702 2 1 R6703 2 PAN_ETQP4LR36ZFC_4P R6718 S 2 4 3 2 1 C6713 2 3.6K_1%_2 10K_5%_NTC R6704 1 2 4 4.7_5%_3 G C6700 3300PF_50V_2 1 1 R6720 2 1 R6721 2 3.6K_1%_2 10K_5%_NTC R6722 2.37K_1%_2 3300PF_50V_2 2 R6719 1 RSC_0402_DY 1 B L6703 1 3 R6700 4 3 2 1 33A IN IN NMOS_4D3S Q6701 TPCA8057_H Q6706 TPCA8065_H 4 3 2 1 PAN_ETQP4LR36ZFC_4P 1 D IN NMOS_4D3S 14< VRCPU_LG3 C6714 S 14< VRCPU_PH3 2 G B 2.2_5%_3 4 3 2 1 IN IN IN 2 S 14< VRCPU_HG3 1 Q6700 TPCA8065_H G 0.22UF_25V_3 2 1 R6723 D C6712 5 6 7 8 14< GPU_BST1 NMOS_4D3S 2.2_5%_3 1 2 1 2 R6717 2 1 NMOS_4D3S IN D 14< CPU_BST3 2 RSC_0402_DY C6703 2 14< GPU_CSP1 0.47UF_6.3V_2 1 IN C6715 2 0.47UF_6.3V_2 A 14< GPU_CSN1 A IN INVENTEC EVEREST-M POWER VCORE TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:29:38 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 15 97 of 1 REV A01 7 6 5 4 3 2 1 1 8 1 2 PAD6801 2 POWERPAD_2_0610 5 6 7 8 D D 3.5A 1 NMOS_4D3S 2 TRIP 3 EN 4 VFB C6807 2 4.7UF_25V_5 30A D 4.7UF_25V_5 10 VBST PAD6800 1 C6804 1 R6804 0_5%_3 2 1 C6805 2 S G PGOOD 4.7UF_25V_5 4 3 2 1 U6800 TI_TPS51217DSCR_SON_10P 1 1 C6803 Q6800 TPCA8065_H DRVH 9 VRGPU_HG SW 8 VRGPU_PH 2 1 1 2 2 2 POWERPAD_2_0610 0.1UF_25V_2 PAD6803 C6800 Q6801 TPCA8A02_H 2.2UF_6.3V_3 2 C6802 CSC0402_DY 2 1 + FOR OPTIMUS SHUTDOWN SOLUTION 2 1 1 R6809 10.2K_1%_2 2 2 C6809 47PF_50V_2 1 R6803 1 R6808 OUT 68> +GPU_NVVDD_L 1 2 100PF_50V_2 2 R6807 40.2K_1%_2 2 2 0_5%_2 28.7K_1%_2 C6816 1 B B CONNECT TO GPU 3 1 D Q6803 R6040 C 4 3 2 1 4 3 2 1 S 2 G S G R6806 1K_1%_2 1 C6810 470UF_2V SBR3U40P1_DY 1 C + 2 Q6802 TPCA8A02_H 470UF_2V 2 2 C6806 470UF_2V 2 11 86.6K_1%_2 R6810 100_5%_2 D6800 1 POWERPAD_2_0610 C6808 2 GND TRAN 2 2 + 1 1 D R6805 VRGPU_LG D 5 1 1 1 1 PAN_ETQP4LR36WFC_4P 5 6 7 8 DRVL 6 5 6 7 8 7 2 4 1 V5IN L6800 1 3 2 1 G S 0_5%_2 SSM3K7002BFU 2 2 NVVDD R6048 VOLTAGE LEVEL VID0 VID1 0 0 0 1 1V 1 0 0.975V 1 33.2K_1%_2 3 A 1 R6041 A D Q6804 2 1 0.825V G S 0_5%_2 2 SSM3K7002BFU INVENTEC EVEREST-M POWER GPU NVVDD TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 00:17:23 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 16 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_S P3V3_AL P15V_A G 3 D 2 2 AO6402AL PAD7001 4 NMOS_4D1S R7036 100K_5%_2 P5V_AL S POWERPAD_2_0610 1 D D 1 1 2 5 6 1 Q7005 WS 2 1 R7035 R7039 1 2 2 1 10K_5%_2 0_5%_2 2 R7033 200_5%_3 C7030 3 CSC0402_DY C7029 22UF_6.3V_5 2 2 1 C7026 2 22UF_6.3V_5 1 D Q7090 1 1 OUT 37< 1 IN Q7001 3 D S G SSM3K7002BFU 2 G 1 OUT SLP_S3_5R 17> 17< 19< OUT 17< SLP_S3#_15R 18< 19< 24< 2 SSM3K7002BFU S SLP_S3# 18< 30> 11< D Q7088 G 3 S SLP_S3_5R SSM3K7002BFU 2 C C P1V5 P1V5_S P5V_S Q7002 PAD7000 D S G 1 2 3 4 1 1 2 2 POWERPAD_2_0610 1 NMOS_4D3S AON7410 11.5A 2 PAD7002 1 24< 19< 18< 17< 17> SLP_S3#_15R 1 IN 2 POWERPAD_2_0610 1 8 7 6 5 R7037 R7038 200_5%_2 1 C7028 2 680PF_50V_2 2 2 750K_1%_2 Q7003 3 D B 19< 17> SLP_S3_5R IN B G S P5V_A 1 SSM3K7002BFU 1 2 5 6 2 P0V75_S Q7004 S 4 G 3 D 1 NMOS_4D1S R7032 22_5%_2 AO6402AL 2 1 IN 0_5%_2 2 1 D SLP_S3#_15R R7034 19< 17< 17> SLP_S3_5R 1 OUT G 3 Q7000 SSM3K7002BFU S C7027 2 CSC0402_DY 2 A A INVENTEC EVEREST-M TITLE POWER +V3S/+V5S/+V1.5S SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:26 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 17 97 of 1 REV A01 7 6 5 4 3 2 1 2 8 37< 19< 18< SLP_A# 30> IN NC D7001 R7029 1 3 2 1 0_5%_2 18> IN +V1.05_LAN_PG OUT BAT54_30V_0.2A PM_APWROK 30< P3V3_A P3V3_A P3V3_A R7028 IN P3V3_A 2 10K_5%_2 1 1 SLP_A# 37< 18< 30> 19< 1 C7011 1 C7012 2 0.1UF_16V_2 2 0.1UF_16V_2 C7010 D 1 1 C7025 0.1UF_16V_2 0.1UF_16V_2 D 2 2 C7009 2 5 5 1 2 TC7SZ08FU R7004 2 1 1 TC7SZ08FU C7000 4 0_5%_2 3 OUT 2 TC7SZ08FU 0.1UF_16V_2 2 U7003 1 C7001 2 0.1UF_10V_2_DY +V1.05S_VCCP_EN 12< - 3 5 4 - 3 U7002 + 1 + + 2 3.3K_5%_2 2 100K_5%_2 1 R7001 2 4 2 U7001 4 R7005 1 1 U7000 + 5 1 - 1UF_6.3V_2 +V3M 3 TC7SZ08FU 1 P3V3_A R7002 2 10K_5%_2_DY C 11> VCCSA_PG 1 IN R7006 37< 1 IN V1.5_PG R7003 OUT 60> 14< 37< 30> IN SLP_S3# C P3V3_A P3V3_A 1 C7013 2 0.1UF_16V_2 59< 1 10K_5%_2 MAIN_PWRGD 11< 2 0_5%_2 2 17< IN +V1.5S_CPUDDR_PG 20< C7002 R7000 2 5 1 1 C7003 2 0.1UF_16V_2 14> VR_PWRGD IN 1 37> EC_PCH_PWROK IN 2 38< 30< P3V3_A 4 OUT ALLSYS_PWROK - 2 1M_1%_2 + U7004 0.1UF_16V_2 1 3 TC7SZ08FU +V1.05_LAN_M R7007 1 R7010 10K_1%_2 309K_1%_2 2 B R7009 2 110K_1%_2 5 1 + 3 - OUT 2 1 C7004 1 2 0.1UF_10V_2_DY 2 + 1 B 2 - U7005 4 OUT +V1.05_LAN_PG WS 18< AZV331KTR_E1 1 C7005 OUT R7008 100K_1%_2 1000PF_50V_2 2 P1V5 P3V3_A 1 1 R7013 R7015 P3V3_A 1K_5%_2 1K_5%_2 P3V3_S DRAMRST_CNTRL_CPU 2 2 R7027 1 R7016 1 D7000 10K_5%_2 2 D 1 Q7064 OUT 1 3 G BSH111 20< 18< 2 C7006 2 1000PF_50V_2 1 OUT R7014 4.99K_1%_2 470PF_50V_2 INVENTEC 2 2 LMBT3904LT1G EVEREST-M POWER SEQ TITLE 2 2 CHANGE 6 5 4 CPU_DRAMRST# 20> 1 C7008 2 2 0_5%_2 SIZE C 7 26> 27> R7031 330_5%_2 8 DDR3_DRAMRST# A 1 1 E 1 R7023 OUT G S SSM3K7002BFU B +V1.5S_CPUDDR_PG 11< C P1V5_CPUDDRS 1 2 0_5%_2 1 3 3 IN 2 2 NC SLP_S3#_15R IN R7026 3 0_5%_2 R7030 1 Q7065 19< 17> 17< 24< DRAMRST_CNTRL_PCH 1 2 1K_5%_2 D R7025 BAT54_30V_0.2A Q7053 0_5%_2_DY R7024 10K_5%_2 2 IN 2 S 1 A DRAMRST_CNTRL_EC 1 3 by Frank Hu DATE Fri Dec 2 31 10:16:27 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 18 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_A +V1.05_LAN_M P5V_A P3V3_A +V3M P1V05_VCCPS +V1.05M +V1.05S P5V_A 2 R7019 47K_5%_2 D PAD7003 1 2 1 R7022 10K_1%_2 220K_5%_2 R7020 8 7 6 5 Q7062 D S G 1 2 1 2 3 4 1 Q7006 4 1 1 NMOS_4D3S 2 C7019 C7018 2 AON7410 1 2 5 6 D 2 2 1 C7014 2 0.01UF_50V_2 3 POWERPAD_2_0610 1 S 1 10UF_6.3V_3 R7018 G PMOS_4D1S C7017 2 10UF_6.3V_3 AM3423P C7015 2 1 10UF_6.3V_3 D 1 100K_5%_2 2 330PF_50V_2_DY C7024 2 1 D 0.1UF_10V_2_DY 2 3 1 Q7061 SSM3K7002BFU G S 1 2 2 R7017 200_5%_3 C7016 1 680PF_50V_2 1 R7021 200_5%_2 D 2 1 3 G Q7058 D S SSM3K7002BFU 2 3 C 3 Q7060 SSM3K7002BFU G 37< 2 12< 30> SLP_LAN# 1 IN Q7059 G SSM3K7002BFU S S 1 D C D 2 18< 30> SLP_A# 1 IN Q7063 G SSM3K7002BFU S 37< 3 2 P1V5_CPUDDRS B B P1V5 Q7052 8 7 6 5 D S G P1V5_CPUDDRS 1 2 3 4 NMOS_4D3S AON7410 1 24< 18< 17< 17> SLP_S3#_15R 1 IN R7011 1 C7007 2 470PF_50V_2 C7023 1 R7012 200_5%_2 2 0.1UF_16V_2 1 2 C7022 1 0.1UF_16V_2 2 C7021 1 0.1UF_16V_2 2 C7020 P1V5 0.1UF_16V_2 2 2 0_5%_2 Q7051 3 D 17< SLP_S3_5R 1 IN G A S A 17> SSM3K7002BFU 2 INVENTEC EVEREST-M POWER SEQ TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:27 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 19 97 of 1 REV A01 8 7 6 5 4 3 2 1 REMOVE CLKOUT_DMI_CLKGEN_DP CLKOUT_DMI_CLKGEN_DN WS CN4500 H_SNB_IVB# OUT TP4500 AN34 1 1 to CPT and NVRAM connector 1 H_SNB_IVB# OUT NV_CLE OUT 32> 37<> 33> H_PECI 1 OUT R4516 2 H_PECI_R AN33 PECI 2 H_PROCHOT#_R AL32 PROCHOT# 2 0_5%_2 2 0_5%_2 IN IN CLK_DMI_PCH_DP CLK_DMI_PCH_DN 2 0_5%_2 2 0_5%_2 IN IN CLK_DP_PCH_CPU_DP CLK_DP_PCH_CPU_DN 29> 29> SM_DRAMRST# 1 1 R4531 R4530 A16 A15 CLK_DP_PCH_CPU_R_DN R8 CPU_DRAMRST# OUT 29> 29> 18> R4536 TerminationVoltage 14> Set toVss when LOW Set toVcc when HIGH (Default) 1 H_PROCHOT# OUT SM_RCOMP[0] 1 NV_CLE CATERR# 43_5%_2 2 DMI&FDI AL33 0_5%_2_DY R4510 62_5%_2 4.7K_5%_2 H_CATERR#_R 2 1 1 CLK_DP_PCH_CPU_R_DP DPLL_REF_CLK 1 20> 2 R4542 R4541 A28 A27 CLKOUT_DMI_PCH_R_DN MISC DDR3 close 1 R4538 BCLK# DPLL_REF_CLK# R4517 D CLKOUT_DMI_PCH_R_DP BCLK SKTOCC# THERMAL Place PROC_SELECT# P1V05_VCCPS R4537 2.2K_5%_2 2 MISC 20> P1V8_S C26 CLOCKS D 56_5%_2 C4504 2 47PF_50V_2 C SM_RCOMP[1] 33< 1 PM_THRMTRIP# OUT R4535 SM_RCOMP[2] 2 AN32 PM_THRMTRIP#_R AK1 A5 A4 R4507 R4506 R4505 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 1 1 1 140_1%_2 25.5_1%_2 200_1%_2 2 2 2 C THERMTRIP# P1V5_CPUDDRS P3V3_A LOW IN 1 100K_5%_2_DY 2 1 R4532 1 C4570 R4511 200_5%_2 2 U4502 H_PM_SYNC BI 1 60> 33> 2 0.1UF_16V_2 200_5%_2 R4534 2 H_PM_SYNC_R AM34 2 H_CPUPWRGD_R AP33 PM_SYNC 0_5%_2 1 R4512 30<> C6/C7 H_CPUPWRGD IN 1 R4533 AP29 AP27 OUT IN AR26 AR27 AP30 IN IN IN TDO AR28 AP26 IN OUT DBR# AL35 PRDY# PREQ# JTAG & BPM P3V3_A PWR MANAGEMENT 0_5%_2 TCK TMS TRST# TDI UNCOREPWRGOOD 0_5%_2 R4529 2 18> 30> 18< PM_DRAM_PWRGD +V1.5S_CPUDDR_PG IN IN 1 2 B VCC A Y 3 GND 5 4 R4500 1 PM_DRAM_PWRGD_R 2 V8 130_1%_2 1 BPM#[0] BPM#[1] NXP_74AHC1G09GV_SOT753_5P 20> 39_5%_2 AR33 IN BUF_PLT_RST#_CPU 2 0_5%_2 1 SYS_RESET#_R BPM#[2] BPM#[3] RESET# BPM#[4] 2 BPM#[5] 3 BPM#[6] BPM#[7] AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 OUT OUT OUT OUT OUT OUT OUT OUT H_BPM0_XDP# H_BPM1_XDP# H_BPM2_XDP# H_BPM3_XDP# H_BPM4_XDP# H_BPM5_XDP# H_BPM6_XDP# H_BPM7_XDP# 30< 60< 60< 60< 60< 60< 60< 60< 60< B D Q4500 60> SYS_RESET# OUT SM_DRAMPWROK R4513 B H_PRDY# 60< H_PREQ# 60> 20< H_TCK 60<> 60> 20< H_TMS 60<> 60> 20< H_TRST# 60> 20< H_TDI 60> 20< H_TDO 60<> 60< 1 IN G S SLP_S3_5R FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER SSM3K7002BFU 2 P1V05_VCCPS P3V3_S 20< 1 P1V05_VCCPS 20< C4559 20< IN IN IN H_TCK H_TRST# IN IN 1 1 R4555 2 51_5%_2 2 51_5%_2 1 R4552 2 51_5%_2_DY 1 R4554 1 2 51_5%_2 2 2 1 0.1UF_16V_2 60> R4556 H_TMS 60> H_TDI H_PREQ# 60<> 60> R4558 20< 75_5%_2 A 60<> 60> 1 1 2 56< R4557 10K_5%_2 BUF_PLT_RST# 55< 32<> 43< IN U4501 NC 2 IN-A 3 GND VCC A 51_5%_2 5 1 OUT-Y 4 20< R4509 2 OUT BUF_PLT_RST#_CPU 43_5%_2 1 TSB_TC7SZ07FU_SSOP_5P INVENTEC R4508 0_5%_2_DY 2 CHANGE 7 6 5 4 EVEREST-M CPU 1 TITLE SIZE C 8 R4553 2 H_CPUPWRGD_R IN 60> 20< 3 by Frank Hu DATE Fri Dec 2 31 10:16:28 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 20 97 of 1 REV A01 8 7 6 5 4 3 2 1 P1V05_VCCPS CLOSE to 1 R4545 D DMI_TX_DN<3..0> 2 CN4500 IN PEG_ICOMPI PEG_ICOMPO OUT DMI_RX_DP<3..0> 0 1 2 3 30> 30> 30> 30> 1 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] A22 G19 E20 G18 B20 C19 D19 F17 FDI_TX_DP<0> FDI_TX_DP<1> FDI_TX_DP<2> FDI_TX_DP<3> FDI_TX_DP<4> FDI_TX_DP<5> FDI_TX_DP<6> FDI_TX_DP<7> 0 1 2 3 4 5 6 7 FDI_FSYNC0 FDI_FSYNC1 30> FDI_INT J18 J17 IN IN PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] FDI0_TX#[0] PEG_RX[3] FDI0_TX#[1] PEG_RX[4] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] Intel(R) A21 H19 E19 F18 B21 C20 D18 E17 FDI_TX_DN<0> FDI_TX_DN<1> FDI_TX_DN<2> FDI_TX_DN<3> FDI_TX_DN<4> FDI_TX_DN<5> FDI_TX_DN<6> FDI_TX_DN<7> PEG_RX#[1] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] FDI1_TX[2] PEG_TX#[2] FDI1_TX[3] PEG_TX#[3] PCI OUT FDI_TX_DP<7..0> R4544 24.9_1%_2 PEG_RX#[0] DMI_RX#[3] OUT FDI_TX_DN<7..0> P1V05_VCCPS G22 D22 F20 C21 DMI_RX_DP<0> DMI_RX_DP<1> DMI_RX_DP<2> DMI_RX_DP<3> 0 1 2 3 0 1 2 3 4 5 6 7 B G21 E22 F21 D21 DMI_RX_DN<0> DMI_RX_DN<1> DMI_RX_DN<2> DMI_RX_DN<3> DMI_RX#[2] FDI0_FSYNC FDI1_FSYNC PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] IN H20 FDI_INT IN IN J19 H17 FDI0_LSYNC PEG_TX#[10] FDI1_LSYNC PEG_TX#[11] PEG_TX#[8] PEG_TX#[9] FDI_LSYNC0 FDI_LSYNC1 PEG_TX#[12] PEG_TX#[13] 2 +V1.05S_VCCP_eDP_COMPIO 48> 48<> 48<> EDP_HPD# PEG_TX#[14] A18 A17 B16 IN PEG_TX#[15] eDP_COMPIO PEG_TX[0] eDP_HDP# PEG_TX[1] BI BI C15 D15 OUT C17 F16 C16 G15 EDP_AUX_DP EDP_AUX_DN eDP_AUX eDP_AUX# PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] 48> EDP_TX0_DP eDP_TX[0] PEG_TX[7] eDP_TX[1] PEG_TX[8] eDP_TX[2] PEG_TX[9] eDP_TX[3] PEG_TX[10] PEG_TX[11] A EDP_TX0_DN 48> C18 E16 D16 F15 OUT K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT eDP_ICOMPO eDP C B28 B26 A24 B23 DMI_TX_DP<0> DMI_TX_DP<1> DMI_TX_DP<2> DMI_TX_DP<3> PEG_TX15_C_DN PEG_TX14_C_DN PEG_TX13_C_DN PEG_TX12_C_DN PEG_TX11_C_DN PEG_TX10_C_DN PEG_TX9_C_DN PEG_TX8_C_DN PEG_TX7_C_DN PEG_TX6_C_DN PEG_TX5_C_DN PEG_TX4_C_DN PEG_TX3_C_DN PEG_TX2_C_DN PEG_TX1_C_DN PEG_TX0_C_DN DMI_RX#[1] - GRAPHICS OUT DMI_RX_DN<3..0> DMI_TX_DN<2> DMI_TX_DN<3> PEG_RCOMPO EXPRESS* 0 1 2 3 DMI_TX_DN<1> DMI_RX#[0] DMI IN B27 B25 A25 B24 DMI_TX_DN<0> FDI DMI_TX_DP<3..0> 0 1 2 3 J22 J21 H22 24.9_1%_2 +V1.05S_VCCP_PEG_ICOMPI eDP_TX#[0] PEG_TX[12] eDP_TX#[1] PEG_TX[13] eDP_TX#[2] PEG_TX[14] eDP_TX#[3] PEG_TX[15] PEG_RX15_DN 68> PEG_RX14_DN 68> PEG_RX13_DN 68> PEG_RX12_DN 68> PEG_RX11_DN 68> PEG_RX10_DN 68> 68> PEG_RX9_DN PEG_RX8_DN 68> PEG_RX7_DN 68> PEG_RX6_DN 68> PEG_RX5_DN 68> PEG_RX4_DN 68> PEG_RX3_DN 68> PEG_RX2_DN 68> PEG_RX1_DN 68> PEG_RX0_DN 68> PEG_RX15_DP 68> PEG_RX14_DP 68> PEG_RX13_DP 68> 68> PEG_RX12_DP 68> PEG_RX11_DP 68> PEG_RX10_DP 68> PEG_RX9_DP 68> PEG_RX8_DP 68> PEG_RX7_DP 68> PEG_RX6_DP 68> PEG_RX5_DP 68> PEG_RX4_DP 68> PEG_RX3_DP 68> PEG_RX2_DP 68> PEG_RX1_DP 68> PEG_RX0_DP PEG_TX15_C_DN 21< PEG_TX14_C_DN 21< PEG_TX13_C_DN 21< PEG_TX12_C_DN 21< PEG_TX11_C_DN 21< 21< PEG_TX10_C_DN 21< PEG_TX9_C_DN 21< PEG_TX8_C_DN 21< PEG_TX7_C_DN 21< PEG_TX6_C_DN 21< PEG_TX5_C_DN 21< PEG_TX4_C_DN 21< PEG_TX3_C_DN 21< PEG_TX2_C_DN 21< PEG_TX1_C_DN 21< PEG_TX0_C_DN PEG_TX15_C_DP 21< PEG_TX14_C_DP 21< PEG_TX13_C_DP 21< PEG_TX12_C_DP 21< PEG_TX11_C_DP 21< 21< PEG_TX10_C_DP 21< PEG_TX9_C_DP 21< PEG_TX8_C_DP 21< PEG_TX7_C_DP 21< PEG_TX6_C_DP 21< PEG_TX5_C_DP 21< PEG_TX4_C_DP 21< PEG_TX3_C_DP 21< PEG_TX2_C_DP 21< PEG_TX1_C_DP 21< PEG_TX0_C_DP IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN C4546 C4545 C4544 C4543 C4542 C4541 C4540 C4539 C4538 C4537 C4536 C4535 C4534 C4533 C4532 C4531 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CPU 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PEG_TX15_DN PEG_TX14_DN PEG_TX13_DN PEG_TX12_DN PEG_TX11_DN PEG_TX10_DN PEG_TX9_DN PEG_TX8_DN PEG_TX7_DN PEG_TX6_DN PEG_TX5_DN PEG_TX4_DN PEG_TX3_DN PEG_TX2_DN PEG_TX1_DN PEG_TX0_DN 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< 68< C PEG_TX15_C_DP PEG_TX14_C_DP PEG_TX13_C_DP PEG_TX12_C_DP PEG_TX11_C_DP PEG_TX10_C_DP PEG_TX9_C_DP PEG_TX8_C_DP PEG_TX7_C_DP PEG_TX6_C_DP PEG_TX5_C_DP PEG_TX4_C_DP PEG_TX3_C_DP PEG_TX2_C_DP PEG_TX1_C_DP PEG_TX0_C_DP IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN C4530 C4529 C4528 C4527 C4526 C4525 C4524 C4523 C4522 C4521 C4520 C4519 C4518 C4517 C4516 C4515 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 0.1UF_6.3V_1 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PEG_TX15_DP 68< PEG_TX14_DP 68< PEG_TX13_DP 68< PEG_TX12_DP 68< PEG_TX11_DP 68< PEG_TX10_DP 68< PEG_TX9_DP 68< PEG_TX8_DP 68< PEG_TX7_DP 68< PEG_TX6_DP 68< PEG_TX5_DP 68< PEG_TX4_DP 68< PEG_TX3_DP 68< PEG_TX2_DP 68< PEG_TX1_DP 68< PEG_TX0_DP 68< INVENTEC EVEREST-M CPU 2 TITLE SIZE C CHANGE 7 6 5 B A FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER 8 D 68< 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:57 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 21 97 of 1 REV A01 8 7 6 5 SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR 27<> 4 M_B_DQ<63..0> 3 2 1 BI CN4500 CN4500 BI SA_CLK[0] D C B C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_CKE[0] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_CLK[1] SA_CLK#[1] SA_CKE[1] RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] SA_DQS#[0] SA_DQ[38] SA_DQS#[1] SA_DQ[39] SA_DQS#[2] SA_DQ[40] SA_DQS#[3] SA_DQ[41] SA_DQS#[4] SA_DQ[42] SA_DQS#[5] SA_DQ[43] SA_DQS#[6] SA_DQS#[7] SA_DQ[44] AB3 AA3 W10 AK3 AL3 AG1 AH1 OUT OUT AH3 AG3 AG2 AH2 OUT OUT M_CS#0 M_CS#1 M_ODT0 M_ODT1 C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQS_DN<0> M_A_DQS_DN<1> M_A_DQS_DN<2> M_A_DQS_DN<3> M_A_DQS_DN<4> M_A_DQS_DN<5> M_A_DQS_DN<6> M_A_DQS_DN<7> 26< 26< 26< 26< M_A_DQS_DN<7..0> 0 1 2 3 4 5 6 7 BI SA_DQ[49] SA_DQS[0] SA_DQ[50] SA_DQS[1] SA_DQ[51] SA_DQS[2] SA_DQ[52] SA_DQS[3] SA_DQ[53] SA_DQS[4] SA_DQ[54] SA_DQS[5] SA_DQ[55] SA_DQS[6] SA_DQ[56] SA_DQS[7] M_A_DQS_DP<7..0> D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQS_DP<0> M_A_DQS_DP<1> M_A_DQS_DP<2> M_A_DQS_DP<3> M_A_DQS_DP<4> M_A_DQS_DP<5> M_A_DQS_DP<6> M_A_DQS_DP<7> 0 1 2 3 4 5 6 7 SA_DQ[57] SA_DQ[58] OUT M_A_A<15..0> SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_MA[0] SA_DQ[62] SA_MA[1] SA_DQ[63] SA_MA[2] SA_BS[0] SA_MA[7] SA_BS[1] SA_MA[8] SA_BS[2] SA_MA[9] SA_MA[12] OUT OUT OUT AB4 AA4 W9 SA_DQ[48] SA_MA[11] M_A_CAS# M_A_RAS# M_A_WE# OUT OUT OUT SA_DQ[47] SA_MA[10] AE8 AD9 AF9 26< 26< 26< SA_DQ[46] A 26< 26< 26< M_CLK_DDR1_DP M_CLK_DDR1_DN M_CKE1 SB_CLK[0] SB_CLK#[0] SA_DQ[45] SA_MA[6] OUT OUT OUT AA5 AB5 V10 BI SA_MA[5] M_A_BS0 M_A_BS1 M_A_BS2 26< 26< 26< SA_DQ[3] SA_MA[4] 26< 26< 26< M_CLK_DDR0_DP M_CLK_DDR0_DN M_CKE0 SA_DQ[2] SA_MA[3] AE10 AF10 V6 OUT OUT OUT SA_DQ[1] DDR SYSTEM MEMORY A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 SA_CLK#[0] M_A_DQ<0> M_A_DQ<1> M_A_DQ<2> M_A_DQ<3> M_A_DQ<4> M_A_DQ<5> M_A_DQ<6> M_A_DQ<7> M_A_DQ<8> M_A_DQ<9> M_A_DQ<10> M_A_DQ<11> M_A_DQ<12> M_A_DQ<13> M_A_DQ<14> M_A_DQ<15> M_A_DQ<16> M_A_DQ<17> M_A_DQ<18> M_A_DQ<19> M_A_DQ<20> M_A_DQ<21> M_A_DQ<22> M_A_DQ<23> M_A_DQ<24> M_A_DQ<25> M_A_DQ<26> M_A_DQ<27> M_A_DQ<28> M_A_DQ<29> M_A_DQ<30> M_A_DQ<31> M_A_DQ<32> M_A_DQ<33> M_A_DQ<34> M_A_DQ<35> M_A_DQ<36> M_A_DQ<37> M_A_DQ<38> M_A_DQ<39> M_A_DQ<40> M_A_DQ<41> M_A_DQ<42> M_A_DQ<43> M_A_DQ<44> M_A_DQ<45> M_A_DQ<46> M_A_DQ<47> M_A_DQ<48> M_A_DQ<49> M_A_DQ<50> M_A_DQ<51> M_A_DQ<52> M_A_DQ<53> M_A_DQ<54> M_A_DQ<55> M_A_DQ<56> M_A_DQ<57> M_A_DQ<58> M_A_DQ<59> M_A_DQ<60> M_A_DQ<61> M_A_DQ<62> M_A_DQ<63> AB6 AA6 V9 SA_CAS# SA_MA[13] SA_RAS# SA_MA[14] SA_WE# SA_MA[15] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26<> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 M_B_DQ<0> M_B_DQ<1> M_B_DQ<2> M_B_DQ<3> M_B_DQ<4> M_B_DQ<5> M_B_DQ<6> M_B_DQ<7> M_B_DQ<8> M_B_DQ<9> M_B_DQ<10> M_B_DQ<11> M_B_DQ<12> M_B_DQ<13> M_B_DQ<14> M_B_DQ<15> M_B_DQ<16> M_B_DQ<17> M_B_DQ<18> M_B_DQ<19> M_B_DQ<20> M_B_DQ<21> M_B_DQ<22> M_B_DQ<23> M_B_DQ<24> M_B_DQ<25> M_B_DQ<26> M_B_DQ<27> M_B_DQ<28> M_B_DQ<29> M_B_DQ<30> M_B_DQ<31> M_B_DQ<32> M_B_DQ<33> M_B_DQ<34> M_B_DQ<35> M_B_DQ<36> M_B_DQ<37> M_B_DQ<38> M_B_DQ<39> M_B_DQ<40> M_B_DQ<41> M_B_DQ<42> M_B_DQ<43> M_B_DQ<44> M_B_DQ<45> M_B_DQ<46> M_B_DQ<47> M_B_DQ<48> M_B_DQ<49> M_B_DQ<50> M_B_DQ<51> M_B_DQ<52> M_B_DQ<53> M_B_DQ<54> M_B_DQ<55> M_B_DQ<56> M_B_DQ<57> M_B_DQ<58> M_B_DQ<59> M_B_DQ<60> M_B_DQ<61> M_B_DQ<62> M_B_DQ<63> C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 SB_DQ[0] SB_CKE[0] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_CLK[1] SB_CLK#[1] SB_CKE[1] RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] SB_DQ[37] SB_DQS#[0] SB_DQ[38] SB_DQS#[1] SB_DQ[39] SB_DQS#[2] SB_DQ[40] SB_DQS#[3] SB_DQ[41] SB_DQS#[4] SB_DQ[42] SB_DQS#[5] SB_DQ[43] SB_DQS#[6] SB_DQ[44] SB_DQS#[7] SB_DQS[0] SB_DQ[49] SB_DQ[50] SB_DQS[1] SB_DQ[51] SB_DQS[2] SB_DQ[52] SB_DQS[3] SB_DQ[53] SB_DQS[4] SB_DQ[54] SB_DQS[5] SB_DQ[55] SB_DQS[6] SB_DQ[56] SB_DQS[7] OUT OUT OUT 27< 27< AD3 AE3 AD6 AE6 OUT OUT M_CS#2 M_CS#3 AE4 AD4 AD5 AE5 OUT OUT D AB2 AA2 T9 AA1 AB1 T10 27< 27< C D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_ODT2 M_ODT3 27< 27< BI M_B_DQS_DN<7..0> BI M_B_DQS_DP<7..0> 0 1 2 3 4 5 6 7 M_B_DQS_DN<0> M_B_DQS_DN<1> M_B_DQS_DN<2> M_B_DQS_DN<3> M_B_DQS_DN<4> M_B_DQS_DN<5> M_B_DQS_DN<6> M_B_DQS_DN<7> C7 G3 J6 M3 AN6 AP8 AK11 AP14 B 0 1 2 3 4 5 6 7 M_B_DQS_DP<0> M_B_DQS_DP<1> M_B_DQS_DP<2> M_B_DQS_DP<3> M_B_DQS_DP<4> M_B_DQS_DP<5> M_B_DQS_DP<6> M_B_DQS_DP<7> SB_DQ[57] SB_DQ[58] M_B_A<15..0> OUT SB_DQ[59] 27<> SB_DQ[60] SB_DQ[61] SB_MA[0] SB_DQ[62] SB_MA[1] SB_DQ[63] SB_MA[2] SB_BS[0] SB_MA[7] SB_BS[1] SB_MA[8] SB_BS[2] SB_MA[9] SB_MA[12] M_B_CAS# M_B_RAS# M_B_WE# M_CLK_DDR3_DP M_CLK_DDR3_DN M_CKE3 27< SB_DQ[48] SB_MA[10] AA10 AB8 AB9 OUT OUT OUT SB_DQ[47] SB_MA[11] 27< 27< 27< AE1 AD1 R10 SB_DQ[46] SB_MA[6] OUT OUT OUT 27< 27< SB_DQ[45] SB_MA[5] M_B_BS0 M_B_BS1 M_B_BS2 M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2 27< SB_DQ[3] SB_MA[4] 27< 27< 27< OUT OUT OUT SB_DQ[2] SB_MA[3] AA9 AA7 R6 AE2 AD2 R9 SB_DQ[1] DDR SYSTEM MEMORY B M_A_DQ<63..0> SB_CAS# SB_MA[13] SB_RAS# SB_MA[14] SB_WE# SB_MA[15] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER INVENTEC EVEREST-M CPU 3 DRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:57 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 22 97 of 1 REV A01 7 6 PVCORE 2 2 10uF_6.3V_3 D 1 1 1 C4584 1 C4583 2 2 2 10uF_6.3V_3 2 10uF_6.3V_3 1 1 10uF_6.3V_3 1 C4586 2 C4594 2 C4585 2 10uF_6.3V_3 10uF_6.3V_3 10uF_6.3V_3 1 C4587 2 C4581 C4582 10uF_6.3V_3 10uF_6.3V_3 C 1 1 1 C4578 C4577 2 C4593 2 2 22uF_6.3V_5 B 1 2 22uF_6.3V_5 1 1 C4590 2 1 2 22uF_6.3V_5 C4588 2 22uF_6.3V_5 1 22uF_6.3V_5 1 C4574 C4573 2 1 C4589 2 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 1 C4591 C4592 1 C4571 C4572 2 2 22uF_6.3V_5 22uF_6.3V_5 2 22uF_6.3V_5 22uF_6.3V_5 A 1 1 C4564 1 C4565 2 2 2 22uF_6.3V_5 1 C4576 22uF_6.3V_5 C4575 2 22uF_6.3V_5 22uF_6.3V_5 VCC3 VCCIO1 VCCIO2 VCC4 VCCIO3 VCC5 VCCIO4 VCC6 VCCIO5 VCC7 VCCIO6 VCC8 VCCIO7 VCC9 VCCIO8 VCC10 VCCIO9 VCC11 VCCIO10 VCC12 VCCIO11 VCC13 VCCIO12 VCC14 VCCIO13 VCC15 VCCIO14 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCC22 VCCIO21 VCC23 VCCIO22 VCC24 VCCIO23 VCC25 VCCIO24 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 1 1 + 10uF_6.3V_3 POWER VCC2 PEG AND DDR C4579 3 2 1 P1V05_VCCPS VCC1 2 3 1 VCC27 VCCIO25 VCC28 VCCIO26 VCC29 VCCIO27 VCC30 VCCIO28 VCC31 VCCIO29 VCC32 VCCIO30 VCC33 VCCIO31 VCC34 VCCIO32 VCC35 VCCIO33 VCC36 VCCIO34 VCC37 VCCIO35 VCC38 VCCIO36 VCC39 VCCIO37 VCC40 VCCIO38 VCC41 VCCIO39 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 VCCIO40 J23 VCC42 VCC43 VCC44 1 C4599 C4569 2 470UF_2V 22uF_6.3V_5 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 1 C4598 2 22uF_6.3V_5 1 C4557 2 22uF_6.3V_5 1 C4597 2 2 2 22uF_6.3V_5 C4558 C4503 22uF_6.3V_5 2 22uF_6.3V_5 22uF_6.3V_5 D 1 1 22uF_6.3V_5 1 C4560 C4563 C4561 C4566 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 2 1 1 C4562 2 2 2 2 P1V05_VCCPS +V1.05S_VCCP_VCCIO40 1 R4528 C 2 0_5%_2 20mil VCC45 1 C4596 VCC26 P1V05_VCCPS CLOSE TO POWER IC 1 1 VCC55 54.9_1%_2 130_1%_2 2 VCC56 1 1 R4548 R4525 VCC54 2 2 R4546 130_1%_2 R4547 75_1%_2 2 VCC57 VCC58 VCC59 SVID C4580 4 CN4500 AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 VCC60 VCC61 VIDALERT# VCC62 VIDSCLK VCC63 VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT 1 1 1 R4551 R4549 R4550 2 2 2 43_1%_2 0_5%_2 0_5%_2 OUT OUT OUT VCC64 VCC65 VR_SVID_ALRT# VR_SVID_CLK 14< 14<> VR_SVID_DATA VCC67 VCC68 VCC69 1 VCC70 R4504 100_1%_2 VCC71 VCC72 2 VCC73 VCC74 VCC75 R4527 R4526 VCC76 VCC77 1 1 2 2 0_5%_2 0_5%_2 OUT OUT 1 VCC78 VCCSENSE VSSSENSE 14< 14< R4503 100_1%_2 VCC79 VCC80 2 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC_SENSE VSS_SENSE VCCSENSE_R VSSSENSE_R 1 2 VCC92 VCCIO_SENSE VSS_SENSE_VCCIO VCC94 WS R4502 10_1%_2 VCC91 VCC93 A P1V05_VCCPS AJ35 AJ34 B10 A10 OUT VCC_SENSE_VTT OUT VSS_SENSE_VTT VCC95 1 VCC96 INVENTEC R4501 10_1%_2 VCC97 VCC98 2 VCC99 EVEREST-M CPU 4 POWER TITLE VCC100 FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER SIZE C CHANGE 8 7 B PVCORE VCC66 SENSE LINES 1 1 5 CORE SUPPLY 8 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:58 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 23 97 of 1 REV A01 8 7 WS 5 xxVccSA_Select[0] [[ CPU PIN# C22 VID1 of VR ]] xxVccSA_Select[1] [[ CPU PIN# C24 VID0 of VR ]] Function D 6 4 2 1 P0V75_VREF_M_H P0V75_VREF_M VCCSA VR Vout SNB HIGH 0 0 0.90V IVB HIGH SNB LOW 0 1 0.725V 1 0 0.80V IVB 1 1 0.675V LOW 3 20/20 Q4501 mil 1 2 5 6 D S 4 G 3 20/20 1 NMOS_4D1S SLP_S3#_15R 1 IN R4523 100K_5%_2 1 AO6402AL 2 R4524 mil 2 C4595 470pF_50V_2 D 2 0_5%_2 PVAXG CN4500 2 2 22uF_6.3V_5 22uF_6.3V_5 2 22uF_6.3V_5 1 1 2 C4605 2 22uF_6.3V_5_DY C4604 22uF_6.3V_5_DY 1 C4603 1 C4507 C4508 2 22uF_6.3V_5 22uF_6.3V_5 WS B 2 + 1 + 1 3 C4506 2 470UF_2V 3 C4505 470UF_2V CPU_CHB_VREFDQ SENSE VAXG11 WS VAXG12 VAXG13 SM_VREF AL1 VAXG14 VAXG15 VAXG16 SA_DIMM_VREFDQ VAXG17 SB_DIMM_VREFDQ C B4 D1 P1V5_CPUDDRS VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VAXG34 VDDQ10 VAXG35 VDDQ11 VAXG36 VDDQ12 VAXG37 VDDQ13 VAXG38 VDDQ14 VAXG39 VDDQ15 6A AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 1 1 C4554 C4556 2 2 1 C4553 1 2 10uF_6.3V_3 10uF_6.3V_3 1 C4555 2 1 C4552 2 10uF_6.3V_3 10uF_6.3V_3 C4551 2 10uF_6.3V_3 10uF_6.3V_3 220UF_2.5V 1 VAXG10 B VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 P0V85_S VAXG50 VAXG51 VCCSA8 M27 M26 L26 J26 J25 J24 H26 H25 VCCSA_SENSE H23 OUT C22 C24 A19 OUT VCCSA_SEL VCCSA1 VAXG52 VCCSA2 VAXG53 VCCSA3 VAXG54 VCCSA4 VCCSA5 VCCSA6 VCCSA7 2 1 C4502 10uF_6.3V_3 2 1 C4501 C4500 2 10uF_6.3V_3 10uF_6.3V_3 RAIL P1V8_S 1 220UF_2.5V 2 22uF_6.3V_5 C4602 1 VAXG9 mil CPU_CHA_VREFDQ 1 C4601 1 P0V75_VREF_M_H VAXG8 + 2 C4600 VAXG7 + 1 20/20 VAXG6 C4568 C VAXG5 2 22uF_6.3V_5 14< 1 22uF_6.3V_5 VAXG4 VAXG_SENSE 14< VSSAXG_SENSE C4567 22uF_6.3V_5 2 OUT OUT 2 22uF_6.3V_5 2 C4514 AK35 AK34 VREF 22uF_6.3V_5 2 1 C4513 RAILS 22uF_6.3V_5 2 1 C4512 VAXG3 DDR3 -1.5V 2 1 C4511 VAXG_SENSE VSSAXG_SENSE SA RAIL 2 1 C4510 VAXG2 LINES 1 C4509 POWER VAXG1 GRAPHICS 1 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 L4500 A 1.1A 1 VCCPLL FBM_11_160808_181A15T 1 1 C4547 2 C4549 2 C4548 2 1uF_6.3V_2 22uF_6.3V_5 1 1 B6 A6 A2 VCCPLL1 VCCPLL2 VCCSA_SENSE WS VCCPLL3 C4550 VCCSA_VID[0] 2 1uF_6.3V_2 MISC 2 1.8V A VCCSA_VID[1] 10uF_6.3V_3 VCCIO_SEL 1 2 R4559 0_5%_2_DY 2 10K_5%_2 1 R4543 13< WS INVENTEC FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER EVEREST-M CPU 5 POWER TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Mon Jan 2 03 17:28:06 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 24 97 of 1 REV A01 7 6 CN4500 D C B AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 5 4 VSS81 VSS2 VSS82 VSS3 VSS83 VSS4 VSS84 VSS5 VSS85 VSS6 VSS86 VSS7 VSS87 VSS8 VSS88 VSS9 VSS89 VSS10 VSS90 VSS11 VSS91 VSS12 VSS92 VSS13 VSS93 VSS14 VSS94 VSS15 VSS95 VSS96 VSS16 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 VSS17 VSS18 VSS98 VSS19 VSS99 VSS20 VSS100 VSS21 VSS101 VSS22 VSS102 VSS23 VSS103 VSS24 VSS104 VSS25 VSS105 VSS26 VSS106 VSS27 VSS107 VSS28 VSS108 VSS29 VSS109 VSS30 VSS110 VSS31 VSS111 VSS32 VSS112 VSS33 VSS113 VSS34 VSS114 VSS VSS35 VSS36 VSS115 VSS116 VSS117 VSS37 VSS38 VSS118 VSS39 VSS119 VSS40 VSS120 VSS41 VSS121 VSS42 VSS122 VSS43 VSS123 VSS44 VSS124 VSS45 VSS125 VSS46 VSS126 VSS47 VSS127 VSS48 VSS128 VSS49 VSS129 VSS50 VSS130 VSS51 VSS131 VSS52 VSS132 VSS53 VSS133 VSS54 VSS134 VSS55 VSS135 VSS56 VSS136 VSS57 VSS137 VSS58 VSS138 VSS59 VSS139 VSS60 VSS140 VSS61 VSS141 VSS62 VSS142 VSS63 VSS143 VSS64 VSS144 VSS65 VSS145 VSS66 VSS146 VSS67 VSS147 VSS68 VSS148 VSS69 VSS149 VSS70 VSS150 VSS71 VSS151 VSS72 VSS152 VSS73 VSS153 VSS74 VSS154 VSS75 VSS155 VSS76 VSS156 VSS77 VSS157 VSS78 VSS158 VSS79 VSS159 VSS80 VSS160 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 VSS161 VSS234 VSS162 VSS235 VSS163 VSS236 VSS164 VSS237 VSS238 VSS165 VSS166 VSS239 VSS167 VSS240 VSS168 VSS241 VSS169 VSS242 VSS170 VSS243 VSS171 VSS244 VSS172 VSS245 VSS173 VSS246 VSS174 VSS247 VSS175 VSS248 VSS176 VSS249 VSS177 VSS250 VSS178 VSS251 VSS179 VSS252 VSS180 VSS253 VSS181 VSS254 VSS182 VSS255 VSS183 VSS256 VSS184 VSS257 VSS185 VSS258 VSS186 VSS259 VSS187 VSS260 VSS188 VSS261 VSS189 VSS262 VSS190 VSS263 VSS191 VSS264 VSS192 VSS265 VSS VSS193 VSS194 VSS266 VSS267 VSS268 VSS195 VSS196 VSS269 VSS197 VSS270 VSS198 VSS271 VSS199 VSS272 VSS200 VSS273 VSS201 VSS274 VSS202 VSS275 VSS203 VSS276 VSS204 VSS277 VSS205 VSS278 VSS206 VSS279 VSS207 VSS280 VSS208 VSS281 VSS209 VSS282 VSS210 VSS283 VSS211 VSS284 VSS212 VSS285 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 RSVD29 60< 60< 60< 60< 60< 60< AJ31 AH31 AJ33 AH33 AJ26 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 VSS217 J20 B18 VSS218 VSS219 J15 VSS223 CFG[9] VCC_DIE_SENSE CFG[10] VSS_DIE_SENSE CFG[12] CFG[13] RSVD37 CFG[14] RSVD38 CFG[15] RSVD39 CFG[16] RSVD40 D VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD5 AR35 AT34 AT33 AP35 AR34 RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 B34 A33 A34 B35 C35 RSVD_NCTF6 C RSVD8 RSVD9 RSVD10 RSVD11 RSVD51 RSVD12 RSVD52 AJ32 AK32 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 BCLK_ITP RSVD21 BCLK_ITP# AN35 AM35 IN IN RSVD22 CLK_XDP_CLKGEN_DP CLK_XDP_CLKGEN_DN RSVD23 RSVD24 RSVD25 AT2 AT1 AR1 RSVD_NCTF11 B RSVD27 KEY B1 VSS227 FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER VSS228 VSS229 VSS230 PEG Static VSS231 Lane Reversal VSS232 VSS233 1: 0: 2 1K_1%_2_DY IN R4519 1 2 1K_1%_2_DY IN R4518 1 2 1K_1%_2_DY (Default) Normal Lane Reversed operation LOW eDP ENABLE 2 1K_1%_2 1 1 1: (Default) 0: eDP Enabled CFG(7) PCIE Port CFG[6:5] eDP Disabled Training 1: (Default) 0: PEG Wait A PEG Train for Bifurcation BIOS immediately for following xxRESETB de assertion training Straps 11: (Default) 10: x8, x8 01: Reserved 00: x8, x4, x16 - - Device x4 Device (Device - 1 function 1 function Device 1 and 1 enabled 1 function 1 function ; 1 disabled 1 and INVENTEC 2 disabled function ; 2 disabled function 2 enabled SIZE C 6 5 4 3 by Frank Hu DATE Fri Dec 2 EVEREST-M CPU 6 GND TITLE 2 enabled CHANGE 7 T8 J16 H16 G16 CFG[17] VSS226 STRAP PIN 8 AH27 AH26 CFG[11] VSS225 R4520 CFG<7> RSVD35 CFG[8] VSS224 IN Training CFG[7] AT26 AM33 AJ27 RSVD_NCTF13 VSS222 CFG<5> PEG Defer RSVD34 VSS221 2 1K_1%_2 CFG<6> RSVD33 CFG[6] RSVD_NCTF12 1 Bifurcation CFG[5] VSS220 R4521 Port CFG[4] VSS216 IN 25> RSVD32 CFG[3] RSVD_NCTF9 VSS215 LOW eDP ENABLE CFG<4> 60< RSVD31 CFG[2] RSVD_NCTF10 VSS214 FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER R4522 RSVD30 CFG[1] RSVD_NCTF8 CFG(2) IN CFG[0] RSVD_NCTF7 PEG Defer CFG<2> AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT VSS213 A Reversal CFG<0> CFG<1> CFG<2> CFG<3> CFG<4> CFG<5> CFG<6> CFG<7> CFG<8> CFG<9> CFG<10> CFG<11> CFG<12> CFG<13> CFG<14> CFG<15> CFG<16> CFG<17> 60< 60< 25< 60< 25< 25< 25< 25< 60< 60< 60< 60< 60< FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER Lan 1 L7 AG7 AE7 AK2 W8 RSVD28 CFG(4) PEG Static 2 CN4500 CN4500 VSS1 PCIE 3 RESERVED 8 31 10:16:59 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 25 97 of 1 REV A01 8 7 6 5 4 3 2 1 CHA C 26< 26< SA0_DIM0 SA1_DIM0 60< OUT OUT 59<> 27< 29<> PCH_3S_SMCLK PCH_3S_SMDATA 22> 22> M_ODT0 M_ODT1 IN IN M_A_DQS_DP<7..0> IN B 22<> M_A_DQS_DN<7..0> IN 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 M_A_DQS_DP<0> 7 M_A_DQS_DN<7> M_A_DQS_DP<1> M_A_DQS_DP<2> M_A_DQS_DP<3> M_A_DQS_DP<4> M_A_DQS_DP<5> M_A_DQS_DP<6> M_A_DQS_DP<7> M_A_DQS_DN<0> M_A_DQS_DN<1> M_A_DQS_DN<2> M_A_DQS_DN<3> M_A_DQS_DN<4> M_A_DQS_DN<5> M_A_DQS_DN<6> A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 DQ9 A10_AP DQ10 A11 DQ11 A12 DQ12 A13 DQ13 A14 DQ14 A15 DQ15 BA0 DQ17 BA1 DQ18 BA2 DQ19 S0# DQ20 S1# DQ21 CK0 DQ22 CK0# DQ23 CK1 DQ24 CK1# DQ25 CKE0 DQ26 CKE1 DQ27 CAS# DQ28 RAS# DQ29 W E# DQ30 SA0 DQ31 SA1 DQ32 SCL DQ33 DQ34 DQ35 ODT0 DQ36 ODT1 DQ37 DQ38 DM0 DQ39 DM1 DQ40 DM2 DQ41 DM3 DQ42 DM4 DQ43 DM5 DQ44 DM6 DQ45 DM7 DQ46 DQ47 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQ48 DQS1 DQ49 DQS2 DQ50 DQS3 DQ51 DQS4 DQ52 DQS5 DQ53 DQS6 DQ54 DQS7 DQ55 DQS#0 DQ56 DQS#1 DQ57 DQS#2 DQ58 DQS#3 DQ59 DQS#4 DQ60 DQS#5 DQ61 DQS#6 DQ62 DQS#7 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_A_DQ<0> M_A_DQ<1> M_A_DQ<2> M_A_DQ<3> M_A_DQ<4> M_A_DQ<5> M_A_DQ<6> M_A_DQ<7> M_A_DQ<8> M_A_DQ<9> M_A_DQ<10> M_A_DQ<11> M_A_DQ<12> M_A_DQ<13> M_A_DQ<14> M_A_DQ<15> M_A_DQ<16> M_A_DQ<17> M_A_DQ<18> M_A_DQ<19> M_A_DQ<20> M_A_DQ<21> M_A_DQ<22> M_A_DQ<23> M_A_DQ<24> M_A_DQ<25> M_A_DQ<26> M_A_DQ<27> M_A_DQ<28> M_A_DQ<29> M_A_DQ<30> M_A_DQ<31> M_A_DQ<32> M_A_DQ<33> M_A_DQ<34> M_A_DQ<35> M_A_DQ<36> M_A_DQ<37> M_A_DQ<38> M_A_DQ<39> M_A_DQ<40> M_A_DQ<41> M_A_DQ<42> M_A_DQ<43> M_A_DQ<44> M_A_DQ<45> M_A_DQ<46> M_A_DQ<47> M_A_DQ<48> M_A_DQ<49> M_A_DQ<50> M_A_DQ<51> M_A_DQ<52> M_A_DQ<53> M_A_DQ<54> M_A_DQ<55> M_A_DQ<56> M_A_DQ<57> M_A_DQ<58> M_A_DQ<59> M_A_DQ<60> M_A_DQ<61> M_A_DQ<62> M_A_DQ<63> 22<> M_A_DQ<63..0> 0 1 2 3 4 5 LAYOUT NOTE: PLACE THESE CAPS NEAR SO-DIMM0 POWER PIN P1V5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 C4122 C4125 1 C4124 1 2 2 1UF_6.3V_2 1 2 1UF_6.3V_2 C4140 C4123 1 2 1UF_6.3V_2 C4139 1 C4138 1 2 2 10UF_6.3V_3 1UF_6.3V_2 C4137 1 2 10UF_6.3V_3 10UF_6.3V_3 C4136 10UF_6.3V_3 CN4101 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 1 DQ1 SDA 11 28 46 63 136 153 170 187 22<> A1 DQ16 116 120 IN IN DQ0 A9 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 IN IN IN IN IN IN IN IN IN IN IN IN IN IN A0 1 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 C4135 10UF_6.3V_3 10UF_6.3V_3 2 22> M_A_BS0 22> M_A_BS1 22> M_A_BS2 22> M_CS#0 22> M_CS#1 M_CLK_DDR0_DP M_CLK_DDR0_DN M_CLK_DDR1_DP M_CLK_DDR1_DN 22> M_CKE0 M_CKE1 22> 22> M_A_CAS# 22> M_A_RAS# 22> M_A_WE# M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15> 2 D 22> 22> 22> 22> BI CN4101 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 BI M_A_A<15..0> 2 22> P3V3_S 1 1 2 2 2.2UF_6.3V_2 VSS17 VDD3 VSS18 VDD4 VSS19 VDD5 VSS20 VDD6 VSS21 VDD7 VSS22 VDD8 VSS23 VDD9 VSS24 VDD10 VSS25 VDD11 VSS26 VDD12 VSS27 VDD13 VSS28 VDD14 VSS29 VDD15 VSS30 VDD16 VSS31 VDD17 VSS32 VDD18 VSS33 VDDSPD VSS35 NC1 VSS37 NC2 VSS38 NCTEST VSS39 0.1UF_16V_2 26< 27> PM_EXTTS#1_R 18> DDR3_DRAMRST# 27> DIMM0_VREF_DQ OUT OUT 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 VSS36 77 122 125 C4127 VSS16 VDD2 VSS34 199 C4126 VDD1 VSS40 198 30 EVENT# VSS41 RESET# VSS42 1 126 VREF_DQ VSS45 VREF_CA VSS46 VSS43 20/20 MIL VSS44 VSS47 C4119 1 20/20 MIL 2 0.1UF_16V_2 DIMM0_VREF_CA C4120 47 48 49 50 51 52 53 C4121 1 1 2 2 2.2UF_6.3V_2 0.1UF_16V_2 54 55 56 57 58 59 60 61 62 63 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 VSS48 VSS1 VSS49 VSS2 VSS50 VSS3 VSS51 VSS4 VSS52 D C P0V75_S VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VTT1 VSS11 VTT2 VSS12 VSS13 G1 VSS14 G2 1.5A 203 204 G1 G2 B VSS15 BELLW_80001_6021_204P NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S PLACE THESE CAPS CLOSE TO VTT1 AND VTT2 C4110 C4100 1 BELLW_80001_6021_204P C4109 1 2 2 1UF_6.3V_2 C4128 1 1 2 1UF_6.3V_2 2 1UF_6.3V_2 1UF_6.3V_2 P3V3_S WS REMOVE NOTE: 1 A IF SA0_DIM0=0 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA0 SO-DIMMA TS ADDRESS IS 0X30 1 R4102 1UF CAP 1PCS R4125 10K_5%_2_DY 10K_5%_2_DY 2 A P3V3_S 2 IN SA0_DIM0 26> IN SA1_DIM0 26> 1 IF SA0_DIM0=1 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA2 SO-DIMMA TS ADDRESS IS 0X32 1 R4126 10K_5%_2 1 R4100 2 R4101 10K_5%_2 10K_5%_2 2 27> 2 26> PM_EXTTS#1_R IN R4127 1 2 OUT PM_EXTTS#1 0_5%_2 INVENTEC EVEREST-M DDR3 DIMM0 TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:00 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 26 97 of 1 REV A01 8 7 6 5 4 3 CHB 22> BI M_B_A<15..0> D C 27< 27< SA0_DIM1 SA1_DIM1 60< 26< 22> M_B_BS0 22> M_B_BS1 22> M_B_BS2 22> M_CS#2 22> M_CS#3 M_CLK_DDR2_DP M_CLK_DDR2_DN M_CLK_DDR3_DP M_CLK_DDR3_DN 22> M_CKE2 22> M_CKE3 22> M_B_CAS# 22> M_B_RAS# 22> M_B_WE# OUT OUT 59<> 29<> PCH_3S_SMCLK PCH_3S_SMDATA 22> 22> M_ODT2 M_ODT3 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 22> 22> 22> 22> IN IN 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 IN IN 116 120 IN IN IN IN IN IN IN IN IN IN IN IN IN IN M_B_DQS_DP<7..0> IN 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 B 22<> M_B_DQS_DN<7..0> IN M_B_DQS_DP<0> M_B_DQS_DP<1> M_B_DQS_DP<2> M_B_DQS_DP<3> M_B_DQS_DP<4> M_B_DQS_DP<5> M_B_DQS_DP<6> M_B_DQS_DP<7> M_B_DQS_DN<0> M_B_DQS_DN<1> M_B_DQS_DN<2> M_B_DQS_DN<3> M_B_DQS_DN<4> M_B_DQS_DN<5> M_B_DQS_DN<6> M_B_DQS_DN<7> A0 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10_AP DQ10 A11 DQ11 A12 DQ12 A13 DQ13 DQ14 A14 DQ15 A15 DQ16 DQ17 BA0 DQ18 BA1 BA2 DQ19 S0# DQ20 S1# DQ21 CK0 DQ22 CK0# DQ23 CK1 DQ24 CK1# DQ25 CKE0 DQ26 CKE1 DQ27 CAS# DQ28 RAS# DQ29 W E# DQ30 SA0 DQ31 SA1 DQ32 SCL DQ33 SDA DQ34 DQ35 DQ36 ODT0 ODT1 DQ37 DQ38 11 28 46 63 136 153 170 187 22<> BI CN4100 DM0 DQ39 DM1 DQ40 DM2 DQ41 DM3 DQ42 DM4 DQ43 DM5 DQ44 DM6 DQ45 DM7 DQ46 DQ47 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQ48 DQS1 DQ49 DQS2 DQ50 DQS3 DQ51 DQS4 DQ52 DQS5 DQ53 DQS6 DQ54 DQS7 DQ55 DQS#0 DQ56 DQS#1 DQ57 DQS#2 DQ58 DQS#3 DQ59 DQS#4 DQ60 DQS#5 DQ61 DQS#6 DQ62 DQS#7 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 M_B_DQ<0> M_B_DQ<1> M_B_DQ<2> M_B_DQ<3> M_B_DQ<4> M_B_DQ<5> M_B_DQ<6> M_B_DQ<7> M_B_DQ<8> M_B_DQ<9> M_B_DQ<10> M_B_DQ<11> M_B_DQ<12> M_B_DQ<13> M_B_DQ<14> M_B_DQ<15> M_B_DQ<16> M_B_DQ<17> M_B_DQ<18> M_B_DQ<19> M_B_DQ<20> M_B_DQ<21> M_B_DQ<22> M_B_DQ<23> M_B_DQ<24> M_B_DQ<25> M_B_DQ<26> M_B_DQ<27> M_B_DQ<28> M_B_DQ<29> M_B_DQ<30> M_B_DQ<31> M_B_DQ<32> M_B_DQ<33> M_B_DQ<34> M_B_DQ<35> M_B_DQ<36> M_B_DQ<37> M_B_DQ<38> M_B_DQ<39> M_B_DQ<40> M_B_DQ<41> M_B_DQ<42> M_B_DQ<43> M_B_DQ<44> M_B_DQ<45> M_B_DQ<46> M_B_DQ<47> M_B_DQ<48> M_B_DQ<49> M_B_DQ<50> M_B_DQ<51> M_B_DQ<52> M_B_DQ<53> M_B_DQ<54> M_B_DQ<55> M_B_DQ<56> M_B_DQ<57> M_B_DQ<58> M_B_DQ<59> M_B_DQ<60> M_B_DQ<61> M_B_DQ<62> M_B_DQ<63> LAYOUT NOTE: P1V5 C4112 SO-DIMM0 C4115 1 C4114 1 2 PLACE 2 1UF_6.3V_2 1 2 1UF_6.3V_2 POWER PIN C4134 C4113 1 2 1UF_6.3V_2 C4133 1 1UF_6.3V_2 2 10UF_6.3V_3 1 2 2 10UF_6.3V_3 C4130 1 10UF_6.3V_3 10UF_6.3V_3 C4129 1 2 CN4100 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 C4132 1 C4131 1 2 2 10UF_6.3V_3 10UF_6.3V_3 P3V3_S C4116 1 WS 1 2 2 2.2UF_6.3V_2 REMOVE CPU_CHB_VREFDQ DIMM1_VREF_DQ OUT OUT C4104 0.1UF_16V_2 20/20 1 DIMM1_VREF_CA 1 1 1 2 2 2.2UF_6.3V_2 C4106 0.1UF_16V_2 2 IN VSS21 VDD7 VSS22 VDD8 VSS23 VDD9 VSS24 VDD10 VSS25 VDD11 VSS26 VDD12 VSS27 VDD13 VSS28 VDD14 VSS29 VDD15 VSS30 VDD16 VSS31 VDD17 VSS32 VDD18 VSS33 VSS35 NC1 VSS37 NC2 VSS38 NCTEST VSS39 EVENT# VSS41 RESET# VSS42 VSS43 VSS44 VREF_DQ VSS45 VREF_CA VSS46 VSS47 VSS48 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 10K_5%_2_DY IN VSS20 VDD6 MIL R4124 2 VSS19 VDD5 VSS40 1 126 2 C4105 10K_5%_2 VSS18 VDD4 MIL P3V3_S R4104 VDD3 SA0_DIM1 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 VSS36 198 30 20/20 1 VSS17 0.1UF_16V_2 PM_EXTTS#1_R DDR3_DRAMRST# NOTE: SO-DIMMB SPD ADDRESS IS 0XA4 SO-DIMMB TS ADDRESS IS 0X34 VSS16 VDD2 VDDSPD 77 122 125 C4117 VDD1 VSS34 199 SA1_DIM1 27> 1 THESE CAPS NEAR 22<> M_B_DQ<63..0> 2 27> VSS1 VSS49 VSS2 VSS50 VSS3 VSS51 VSS4 VSS52 D PLACE THESE CAPS CLOSE TO VTT1 AND VTT2 P0V75_S VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VTT1 VSS11 VTT2 2031.5A 204 VSS12 VSS13 G1 VSS14 G2 G1 G2 VSS15 BELLW_80001_2021_204P 1 1 R4103 R4123 10K_5%_2 10K_5%_2_DY 2 2 C4108 PLACE THESE CAPS CLOSE TO VTT1 AND VTT2 C4107 1 C4102 1 2 2 1UF_6.3V_2 20/20 1UF_6.3V_2 P1V5 1 R4114 S D 1 3 R4128 G 1 2 5 6 1 R4115 0_5%_2 2 1 2 2 R4111 R4130 1K_5%_2_DY 2 R4129 1K_5%_2_DY 1 1 R4122 1K_1%_2 2 2 1 C4103 1 1 R4117 1K_1%_2 AO6402AL 2 0.1UF_16V_2 2 0.1UF_16V_2 2 2 1 R4110 1 IN 1 2 5 6 D 1 1 3 1 R4131 1K_5%_2_DY AO6402AL 1 R4133 1K_5%_2_DY 2 2 R4134 1K_5%_2_DY 2 4 1 G 1 1 R4137 0_5%_2 2 S P1V5 R4136 0_5%_2 2 R4132 1K_5%_2_DY NMOS_4D1S R4141 0_5%_2_DY 2 2 R4138 R4139 2 1 0_5%_2 1 2 0_5%_2 R4140 R4112 2 0_5%_2 1 2 0_5%_2_DY 2 A 1 1 R4135 1K_5%_2_DY C4141 0.1UF_16V_2 1 1 2 2 R4105 0_5%_2_DY 2 C4142 2 0.1UF_16V_2_DY R4116 0_5%_2_DY R4143 R4142 1 2 0_5%_2 P1V5 2 Q4101 1 R4121 1K_1%_2 C4118 R4119 0_5%_2 1 R4120 0_5%_2_DY 2 DRAMRST_CNTRL_CPU CPU_CHB_VREFDQ 1 2 0_5%_2 NMOS_4D1S 1K_5%_2_DY 1 R4118 1K_1%_2 Q4100 4 P1V5 DIMM1_VREF_DQ 1 2 0_5%_2_DY A 1 DIMM0_VREF_DQ 2 1 2 IN INVENTEC DRAMRST_CNTRL_CPU 0_5%_2_DY 0_5%_2_DY R4144 1 TITLE 2 0_5%_2_DY SIZE C CHANGE 8 7 6 5 4 1UF_6.3V_2 WS DIMM1_VREF_CA DIMM0_VREF_CA 2 MIL P0V75_VREF_M P1V5_CPUDDRS B C4101 1 1 2 1UF_6.3V_2 BELLW_80001_2021_204P CPU_CHA_VREFDQ C 3 by Frank Hu DATE Fri Dec 2 31 10:16:30 2010 EVEREST-M DDR3 DIMM1 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 27 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_A +V3M P3V3_AL 2 3 4 2 R4761 1uF_6.3V_2 1M_5%_2 2 2 1uF_6.3V_2 2 A20 RTCX2 C20 RTCX2 D20 RTCRST# +V_RTC_SRTCRST# WS P3V3_S +V_RTC_INTRUDER# P5V_S RTCX1 G22 SRTCRST# K22 INTRUDER# 1 R4813 2 0_5%_2_DY C17 FWH3/LAD3 FWH4/LFRAME# D36 OUT LDRQ0# LDRQ1#/GPIO23 INTVRMEN SERIRQ HDA_3S_RST# LPC_3S_AD<0> LPC_3S_AD<1> LPC_3S_AD<2> LPC_3S_AD<3> LPC_3S_FRAME# E36 K36 1 R4758 V5 BI P3V3_A R4851 STRAP Flash Disable Enable R4770 1 2 33_1%_2 HDA_3S_SYNC_R R4769 1 2 33_1%_2 HDA_3S_RST#_R OUT L34 HDA_SYNC T10 SPKR K34 HDA_RST# 2 HDA_3S_SDIN0 IN 1 WS 10K_5%_2_DY Override - (Default)Internal - pull-up P5V_S pull-down E34 HDA_SDIN0 G34 HDA_SDIN1 HDA_3S_SDOUT 2 OUT 1 37> STRAP PIN HIGH - ENABLE LOW - Internal R4785 EC_SMI C34 HDA_SDIN2 A34 HDA_SDIN3 SATA3RXP IN R4773 A36 HDA_SDO HDA_3S_SDOUT_R dgnd C36 HDA_DOCK_EN#/GPIO33 N32 HDA_DOCK_RST#/GPIO13 SATA4RXN SATA4RXP SATA4TXN SATA4TXP 1 SATA5RXN SATA5RXP SATA5TXN 2 51_5%_2 1 PCH_TCK OUT WS OVERIDE 3 D SATA3TXP PCH_TMS J3 JTAG_TCK OUT H7 JTAG_TMS JTAG_TDI JTAG_TDO 61> 60<> 60> 28> PCH_TDI OUT K5 61< 60<> 60> 28> PCH_TDO OUT H1 SATA5TXP HIGH:ENABLE HDA_3S_SDOUT_R LOW:DISABLE 2 OUT 0_5%_2 3 D P3V3_A 2 2 R4892 PCH_SPI_CS1# 1 28<> CN4701 BI BI A +V3M_SPI 1 R4755 BI 2 33_5%_2 PCH_SPI_CLK_R 1 2 0_5%_2 PCH_SPI_CS0#_R R4764 3.3K_5%_2 CE# SO 8 7 6 5 VDD HOLD# WP# SCK VSS SI PCH_SPI_SI PCH_SPI_SO BI BI R4756 1 2 33_5%_2 R4754 1 2 33_5%_2 2 BI BI Y14 SPI_CLK SPI_CS0# PCH_SPI_MOSI_R BI BI PCH_SPI_CLK PCH_SPI_SI 28<> 28<> EC_SPI_CLK OUT EC_SPI_CS0# OUT 37> R4765 DO_IO1 /WP_IO2 GND 37< VCC /HOLD_IO3 CLK DIO_ID0 8 7 6 5 37> R4766 BI BI 1 2 3.3K_5%_2 37< PCH_SPI_CLK 28<>1 PCH_SPI_SI 28<> WINB_W25Q64BVSSIG_SOIC_8P AM10 AM8 AP11 AP10 IN IN OUT OUT 37<> 37<> 37<> 43< 43< 43< R4701 100_1%_2 100_1%_2 2 55< 37<> 43< 55< 55< 55< P3V3_S 2 AD7 AD5 AH5 AH4 1 6 43< 55< IN IN OUT OUT SATA ODD AB8 AB10 AF3 AF1 IN IN OUT OUT SATA_ESATA_RX_DN SATA_ESATA_RX_DP SATA_ESATA_TX_DN SATA_ESATA_TX_DP eSATA Y7 Y5 AD3 AD1 IN IN OUT OUT SATA_mSATA_RX_DN SATA_mSATA_RX_DP SATA_mSATA_TX_DN SATA_mSATA_TX_DP Y3 Y1 AB3 AB1 Y11 SATAICOMPI Y10 +V1.05S_SATAICOMPO C Distance cap +V1.05S R4757 1 2 B 37.4_1%_2 +V1.05S SATA3RCOMPO AB12 SATA3COMPI AB13 SATA3RBIAS AH1 1 R4891 +V1.05S_SATA3RCOMPO 2 P3V3_S 49.9_1%_2 1 V14 PCH_XDPFN10 SPI_MISO SATA1GP/GPIO19 P1 PCH_XDPFN11 1 R4799 2 33_5%_2_DY 1 R4850 EC_SPI_SI OUT 1 R4798 2 33_5%_2_DY 37> EC_SPI_SO IN 1 R4797 2 0_5%_2_DY BI PCH_SPI_CLK BI PCH_SPI_CS0# 0_5%_2_DY 1 R4803 1 R4801 5 R4771 10K_5%_2 OUT PCH_XDPFN10 OUT PCH_XDPFN11 2 2 0_5%_2_DY 28> R4823 2 28<> 0_5%_2_DY A 28<> BI PCH_SPI_SI OUT 1 R4763 2 RSC_0402_DY 28<> INVENTEC EVEREST-M PCH 1 TITLE BI PCH_SPI_SO 28<> SIZE C CLOSED TO PCH 4 58< 28> 1 1 2 PCH_SPI_CS1# 0_5%_2_DY 1 2 STRAP PIN 2 0_5%_2_DY R4802 2 OUT LED_3S_SATA# 1K_5%_2_DY 2 1 P3 R4804 2 1 R4852 10K_5%_2 SATA0GP/GPIO21 R4800 2 750_1%_2 3 Frank Hu DATE Sun Jan 2 02 19:22:09 on between the "P" the signal identical distance PCH and cap on the for same pair mSATA WS SPI_MOSI 33_5%_2_DY C4764 2 0.1UF_16V_2 37<> PCI_3S_SERIRQ HDD CHANGE by 7 R4702 R4703 2 SATA V4 CLOSED TO EC 8 1 SSD SPI_CS1# U3 37< +V3M_SPI /CS 1 SATA T1 1 10K_5%_2 1 2 3 4 1 SATA_SSD_RX_DN SATA_SSD_RX_DP SATA_SSD_TX_DN SATA_SSD_TX_DP SATA_HDD_RX_DN SATA_HDD_RX_DP SATA_HDD_TX_DN SATA_HDD_TX_DP SATA_ODD_RX_DN SATA_ODD_RX_DP SATA_ODD_TX_DN SATA_ODD_TX_DP ITL_PANTHERPOINT_FCBGA_989P U4702 PCH_SPI_CS0# PCH_SPI_SO T3 OUT ACES_91960_0084L_8P 2 28<> IN IN OUT OUT SATAICOMPO SATALED# 28<> 1 2 3 4 2 210_1%_2 R4890 1 +V3M_SPI 1K_5%_2_DY PCH_SPI_CS0# PCH_SPI_SO R4812 BI PCH_SPI_CS0# 28<> G PCH_SPI_CLK 28<> HDA_3S_SDOUT_R S 1 Q4705 AM2321P_DY 28<> AM3 AM1 AP7 AP5 SPI R4893 1 28<> 28<> SATA1TXP SATA2TXP TP4713 60<> 60> 61> SECURITY 1 R4768 2 33_1%_2 2 ANTITHEFT 2 BI S 12pF_50V_2 10K_5%_2_DY IN SATA1TXN SATA3TXN SSM3K7002FU C4779 1 FLASH_OVERRIDE SATA1RXP SATA2TXN SATA 1 P3V3_S FLASH DESCRIPTOR SATA1RXN SATA2RXP JTAG 2 OUT PCH_SPI_SI SATA0TXP SATA2RXN G WS 1K_5%_2 B SATA0TXN SATA3RXN 1 Q4704 R4783 HDA_3S_SYNC_R SATA0RXP disabled OUT HDA_3S_SDOUT 3 HDA_BCLK IHDA enabled No Reboot D N34 SATA 6G G C S SATA0RXN HDA_3S_BITCLK_R 2 33_1%_2 SSM3K7002FU OUT PCSPKR_PCH_3 No Reboot 1: No Reboot 0: (Default) 2 1 R4767 BI HDA_3S_BITCLK 2 BI HDA_3S_SYNC 1 Q4703 2 210_1%_2 10K_5%_2 STRAP R4782 2 210_1%_2 D 1 1K_5%_2_DY H-VCC VRM=1.5V L- (Default) VCC VRM=1.8V R4704 2 BI BI BI BI FWH2/LAD2 1 R4706 100_1%_2 C38 A38 B37 C37 FWH0/LAD0 FWH1/LAD1 +V_RTC_RTCRST# MAXELL_ML1220_T10_2P U4700 RTCX1 LPC 1.2K_1%_3 C4761 OUT PCH_TDI PCH_TMS OUT PCH_TDO OUT note 1 1 VRM Enable INTVRMEN- 1.05V highEnable Internal VRs low-Enable External VRs 1 20K_1%_2 1 Placememt R4705 2 RTC 1 C4762 2 1 18pF_50V_2 R4760 1 C4765 2 1 NC 2 330K_5%_3 2 R4778 1 SIG442 2 X4701 32.768KHZ 2 10M_5%_2 150_1%_3 2 60> 28> 61> 60<> 60> 28> 60<> 61> 60> 28> 60<> 61< R4707 0_5%_2 1 R4708 2 RSC_0402_DY R4786 1 0_5%_3 1 R4759 1uF_6.3V_2 1 18pF_50V_2 R4772 C4763 +V_RTC 1 D - 1 1 R4777 RTC BATTERY + 2 20K_1%_2 BAT54_30V_0.2A U4703 R4762 1 D4704 3 1 2 +V_RTC +V_RTC 2 +V1.05S C4766 1 2 1 +V3M_SPI 2011 CODE CS SHEET DOC.NUMBER REV CS_1310AXXXXXX-MTR 28 97 of 1 A01 PCH and should between the "N" signal be 8 7 5 P3V3_S CLKREQ_USB3# R4894 1 IN USB3.0 10K_5%_2 CLKREQ_CR# 1 IN 2 3 CARD READER 10K_5%_2 PCIE_USB3_RX_DN PCIE_USB3_RX_DP PCIE_USB3_TX_DN PCIE_USB3_TX_DP IN IN OUT OUT BG34 BJ34 AV32 AU32 0.1UF_16V_2 C4780 C4781 PCIE_USB3_TX_C_DN 1 1 2 2 PCIE_USB3_TX_C_DP 0.1UF_16V_2 PCIE_CR_RX_DN PCIE_CR_RX_DP PCIE_CR_TX_DN PCIE_CR_TX_DP IN IN OUT OUT BE34 BF34 BB32 AY32 0.1UF_16V_2 C4782 C4783 PCIE_CR_TX_C_DN 1 1 2 2 PCIE_CR_TX_C_DP PERN1 PERP1 SMBALERT#/GPIO11 PETP1 PERN2 PERP2 PETN2 PETP2 2 10K_5%_2 R4730 1 3G 2 C4758 C4757 PCIE_WLAN_TX_C_DN 1 1 2 PCIE_WLAN_TX_C_DP 2 0.1UF_16V_2 IN IN OUT OUT PCIE_3G_RX_DN PCIE_3G_RX_DP PCIE_3G_TX_DN PCIE_3G_TX_DP 0.1UF_16V_2 C4784 C4785 PCIE_3G_TX_C_DN 1 1 2 2 PCIE_3G_TX_C_DP 0.1UF_16V_2 10K_5%_2_DY H14 29<> SMBDATA PERN3 BF36 BE36 AY34 BB34 PERN4 C9 BI PCH_3A_SMDATA 10K_5%_2 1 R4752 2 A12 IN DRAMRST_CNTRL_PCH 1 R4751 SML0CLK C8 OUT SML0_CLK SML0DATA G12 OUT SML0_DATA PETN3 PETP3 PETN4 PETP4 BG37 BH37 AY36 BB36 PERN5 BJ38 BG38 AU36 AV36 PERN6 BG40 BJ40 AY40 BB40 PERN7 BE38 BC38 AW38 AY38 PERN8 1 R4741 PCH_3A_SMCLK 29<> SML1ALERT# 55<> IN 2 2.2K_5%_2 PERP3 PERP4 55<> BI 39<> 29< 39<> 39<> 29> 29< SML0_CLK 39<> IN SML1CLK/GPIO58 E14 OUT SML1_CLK PERP5 SML1DATA/GPIO75 M16 OUT SML1_DATA IN 29> SML0_DATA 29< C13 SML1ALERT#/PCHHOT#/GPIO74 1 IN 2.2K_5%_2 R4749 2 D 2.2K_5%_2 SML1ALERT# PETN5 2 2.2K_5%_2 1 R4750 2 29> 29<> SML1_CLK P3V3_A 2 BI SSM3K7002BFU 29<> S WS BG36 BJ36 AV34 AU34 PCI-E* 1 CLKREQ_WLAN# IN WLAN SMBCLK SML0ALERT#/GPIO60 0.1UF_16V_2 P3V3_A 2 1 G D R4731 IN IN OUT OUT PCIE_WLAN_RX_DN PCIE_WLAN_RX_DP PCIE_WLAN_TX_DN PCIE_WLAN_TX_DP E12 1 1 P3V3_A PETN1 0.1UF_16V_2 P3V3_A 2 R4753 10K_5%_2 U4700 2 R4895 4 SMBUS WS 6 PETP5 D LAN 10K_5%_2_DY IN IN OUT OUT 0.1UF_16V_2 C4760 C4759 1 1 2 2 PCIE_LAN_TX_C_DN PCIE_LAN_TX_C_DP 0.1UF_16V_2 FOR INTEGRATED C IN CLKIN_DMI_PCH_DP CLKIN_BUF_DOT96_DN IN CLKIN_BUF_DOT96_DP IN CLKIN_SATA1_DN 10K_5%_2 2 10K_5%_2 R4794 1 2 10K_5%_2 R4793 1 2 10K_5%_2 R47921 2 10K_5%_2 R47881 IN CLKIN_SATA1_DP 2 R4795 1 IN CLKIN_PCH14 CLK R4796 1 IN CLKIN_DMI_PCH_DN 2 R47871 IN 2 TP4712 P3V3_A 1 WS TP4711 R4740 CLKREQ_USB3# CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP 1 1 P3V3_A R4744 2.2K_5%_2 1 CLKREQ_WLAN# WS P3V3_A CLK_PCIE_3G_DN CLK_PCIE_3G_DP R4742 2.2K_5%_2 2 27< 59<> 26< 60< P5V_S 1 2.2K_5%_2 R4743 2 2.2K_5%_2 OUT CL_CLK CL_DATA1 T11 OUT CL_DATA 55> PETN7 PETP7 CL_RST1# P10 OUT CL_RST# 55> PERP8 CLKREQ_3G# 2 2 J2 1 R4814 OUT OUT AA48 AA47 IN V10 OUT OUT Y37 Y36 A8 IN Y43 Y45 IN L12 V45 V46 2 10K_5%_2 L14 M10 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_PCIE1P CLKOUT_DMI_P AB37 AB38 CLK_PEG_GPU_REF_DN CLK_PEG_GPU_REF_DP AV22 AU22 OUT OUT CLK_DMI_PCH_DN CLK_DMI_PCH_DP AM12 AM13 OUT OUT CLK_DP_PCH_CPU_DN CLK_DP_PCH_CPU_DP BF18 BE18 IN IN G D AB42 AB40 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_DMI_N CLKIN_DMI_P CLKIN_GND1_N CLKIN_GND1_P CLKOUT_PCIE5N REFCLK14IN CLKIN_PCILOOPBACK PCIECLKRQ5#/GPIO44 1 CLK_PCIE_LAN_DP Q4702 2 10K_5%_2 R4816 1 R4815 1 E6 2 0_5%_2 CLK_PCIE_LAN_R_DN 2 0_5%_2 CLK_PCIE_LAN_R_DP IN CLKREQ_LAN# TP4706 1 TP4705 1 R4889 60< CLK_XDP_DN OUT CLK_XDP_DP OUT V40 V42 T13 SSM3K7002BFU 60< 2 2 AK7 AK5 29> OUT XTAL25_IN C4776 18pF_50V_2 CLKIN_BUF_CPYCLK_DN CLKIN_BUF_CPYCLK_DP IN IN CLKIN_SATA1_DN CLKIN_SATA1_DP K45 IN CLKIN_PCH14 H45 IN CLKIN_PCI_FB V47 V49 OUT OUT 2 R4854 R4855 10K_5%_2 10K_5%_2 B 2 59> 29< 59> 29< CLKOUT_PEG_B_N XTAL25_IN CLKOUT_PEG_B_P XTAL25_OUT R4859 R4858 1 1 1 2 10K_5%_2 2 0_5%_2 2 0_5%_2 V38 V37 K12 CLKOUT_ITPXDP_DN CLKOUT_ITPXDP_DP AK14 AK13 29> XTAL25_IN XTAL25_OUT 29> +V1.05S PEG_B_CLKRQ#/GPIO56 Y47 CLKOUT_PCIE6N R4747 1 2 90.9_1%_2 CLKOUT_PCIE6P A CLOSE TO PCH PCIECLKRQ6#/GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUTFLEX0/GPIO64 K43 CLKOUTFLEX1/GPIO65 F47 1 R4700 2 OUT CLK_GPU_27M_SS_R CLKOUTFLEX2/GPIO66 H47 CLKOUTFLEX3/GPIO67 K49 CLK_GPU_27M 22_5%_2 OUT DGPU_PRSNT# 67< INVENTEC ITL_PANTHERPOINT_FCBGA_989P WS REMOVE CLK_XDP_CLKGEN_DN REMOVE CLK_XDP_CLKGEN_DP CHANGE 7 6 EVEREST-M PCH 2 TITLE SIZE C 8 2 1 1 CLKIN_BUF_DOT96_DN CLKIN_BUF_DOT96_DP CLKOUT_PCIE5P FLEX CLOCKS D 2 IN IN CLKOUT_PCIE4P CLKIN_SATA_P 25MHz 1 IN IN CLKOUT_PCIE4N PCIECLKRQ4#/GPIO26 1 BJ30 BG30 G24 E24 2 CLKIN_DMI_PCH_DN CLKIN_DMI_PCH_DP PCIECLKRQ3#/GPIO25 XCLK_RCOMP OUT OUT CLK_PCIE_LAN_DN S BI PCH_3S_SMDATA 1 3 G C4777 18pF_50V_2 CLKOUT_PCIE2N CLKOUT_PCIE2P 1 1 R4774 A R4849 1M_5%_2 X4700 20< PCIECLKRQ1#/GPIO18 PCIECLKRQ2#/GPIO20 C 1 OUT OUT S 55<> BI BI Q4700 3 BI CLKOUT_PCIE0P SSM3K7002BFU PCH_3A_SMCLK PCH_3A_SMDATA EC_SMB3_DATA CLKREQ_GPU_PEG# IN CLKOUT_PCIE0N CLKIN_SATA_N 1 37<> 29> CLKIN_DOT_96P OUT OUT 1 OUT XTAL25_OUT CLKIN_DOT_96N 3Q4703 29<> SSM3K7002BFU PETP8 CLKOUT_DP_N BI 2 55> 2 PETN8 CLKOUT_PEG_A_N M1 IN PERP7 PEG_A_CLKRQ#/GPIO47 Y40 Y39 AB49 AB47 OUT OUT TP4704 TP4703 1 PCH_3S_SMCLK CL_CLK1 Q4701 3 BI BI PETP6 CLKOUT_DP_P CLK_PCIE_CR_DN CLK_PCIE_CR_DP B R4745 PETN6 10K_5%_2 CLKREQ_CR# P3V3_S 1 1 2 10K_5%_2 CLK_PCIE_USB3_DN CLK_PCIE_USB3_DP 10K_5%_2 EC_SMB3_CLK 29> SML1_DATA M7 D STUFF 37<> PERP6 S PCIE_LAN_RX_DN PCIE_LAN_RX_DP PCIE_LAN_TX_DN PCIE_LAN_TX_DP Controller Link 2 CLOCKS R4748 1 IN G CLKREQ_LAN# 5 4 3 by Frank Hu DATE Sun Jan 2 02 15:32:31 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 29 97 of 1 REV A01 8 7 6 5 4 3 DSWVRMEN - 2 Deep S4/S5 Well On-Die 1 Voltage Regulator Enable high-Enabled(Default) low-Disabled U4700 +V1.05S 21< 21< 21< 21< 1 R4739 21< 21< 21< 21< 49.9_1%_2 2 IN IN IN IN DMI_RX_DP<0> DMI_RX_DP<1> DMI_RX_DP<2> DMI_RX_DP<3> DMI_TX_DN<0> DMI_TX_DN<1> DMI_TX_DN<2> DMI_TX_DN<3> IN IN IN IN BE24 BC20 BJ18 BJ20 OUT OUT OUT OUT AW24 AW20 BB18 AV18 OUT OUT OUT OUT AY24 AY20 AY18 AU18 DMI0RXN FDI_RXN0 DMI1RXN FDI_RXN1 DMI2RXN FDI_RXN2 DMI3RXN FDI_RXN3 FDI_RXN4 DMI0RXP FDI_RXN5 DMI1RXP FDI_RXN6 DMI2RXP FDI_RXN7 DMI0TXP FDI_RXP6 DMI1TXP FDI_RXP7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_INT AW16 FDI_RXP0 DMI0TXN FDI_RXP1 DMI1TXN DMI2TXN DMI3TXN FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 DMI_TX_DP<0> DMI_TX_DP<1> DMI_TX_DP<2> DMI_TX_DP<3> R4888 1 2 STRAP PIN BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 IN IN IN IN IN IN IN IN DMI3RXP FDI 21> 21> 21> 21> D DMI_RX_DN<0> DMI_RX_DN<1> DMI_RX_DN<2> DMI_RX_DN<3> DMI 21> 21> 21> 21> BC24 BE20 BG18 BG20 IN IN IN IN IN IN IN IN DMI2TXP EC OUT FDI_INT OUT FDI_FSYNC0 21< BG25 DMI_IRCOMP FDI_FSYNC1 BC10 OUT FDI_FSYNC1 21< FDI_LSYNC0 AV14 OUT FDI_LSYNC0 21< FDI_LSYNC1 BB10 OUT FDI_LSYNC1 21< 1 SUSACK#_R 2 C12 SUSACK# Management IN 0_5%_2_DY K3 SYS_RESET# P12 SYS_PWROK L22 PWROK L10 APWROK 0.1UF_10V_2_DY B13 DRAMPWROK 1 R4886 RSMRST#_R C21 RSMRST# SUS_PWR_ACK_R K16 SUSWARN#/SUSPWRDNACK/GPIO30 E20 PWRBTN# H20 ACPRESENT/GPIO31 E10 BATLOW#/GPIO72 A10 RI# IN R4847 1 2 ALLSYS_PWROK OUT IN SUSACK#_R 0_5%_2 EC_PCH_PWROK IN 18> P3V3_A PM_APWROK IN PM_DRAM_PWRGD OUT B 1 37> 2 R4738 EC_PWRSW# IN NC D4702 37> 3 10K_5%_2 2 1 1 SUS_PWR_ACK OUT R4846 1 0.1UF_10V_2_DY C4769 2 1 0.1UF_10V_2_DY C4768 2 2 1 0_5%_2 1 R4848 2 0_5%_2 2 0_5%_2 BAT54_30V_0.2A R4884 330K_5%_2_DY A18 DPWROK E22 37< 30< ACPRESENT IN XDP_PWRSW# IN 1 R4883 2 IN 0_5%_2 WAKE# CLKRUN#/GPIO32 SUS_STAT#/GPIO61 SUSCLK/GPIO62 SLP_S5#/GPIO63 C4767 RSMRST#_R 2 B9 N3 IN PCIE_WAKE# BI PCI_3S_CLKRUN# G8 OUT SUS_STAT# N14 OUT FM_32KHZ OUT SLP_S5# 37> D10 55<> 30< OUT SLP_S4# 11< 37< SLP_S3# F4 OUT SLP_S3# 11< 17< OUT SLP_A# OUT SLP_SUS# SLP_SUS# G16 PMSYNCH AP14 BI 37<> 30< 43< 37< H4 G10 CLOSE TO IC 37> SLP_S4# SLP_A# 1 0.1UF_10V_2_DY 18< B 18< 19< 37< 37< 37< H_PM_SYNC 20<> 2 60> RSMRST# IN 2 C4778 Power CLOSE TO IC IN DSWVRMEN R4887 SUSACK#_EC 2 10K_5%_2 SUS_PWR_ACK_R 1 2 AV12 System R4734 SYS_RESET# 330K_5%_2 C 1 20> 2 21< FDI_FSYNC0 DMI2RBIAS D 1 21> 21> 21> 21> 21> 21> 21> 21> DMI_ZCOMP BH21 +V_RTC R4885 BJ24 P3V3_S 60> 21> 21> 21> 21> 21> 21> 21> 21> DMI3TXP 750_1%_2 C FDI_TX_DN<0> FDI_TX_DN<1> FDI_TX_DN<2> FDI_TX_DN<3> FDI_TX_DN<4> FDI_TX_DN<5> FDI_TX_DN<6> FDI_TX_DN<7> FDI_TX_DP<0> FDI_TX_DP<1> FDI_TX_DP<2> FDI_TX_DP<3> FDI_TX_DP<4> FDI_TX_DP<5> FDI_TX_DP<6> FDI_TX_DP<7> D4703 LOW_BAT#_3 IN 30< NC 3 1 PM_RI# IN SLP_LAN#/GPIO29 K14 OUT SLP_LAN# 30> 12< 19< 37< ITL_PANTHERPOINT_FCBGA_989P P3V3_A BAT54_30V_0.2A P3V3_A 37< 30< A 1 R4732 8.2K_5%_2 ACPRESENT IN SUS_PWR_ACK IN R4776 1 2 10K_5%_2 R4735 1 2 10K_5%_2 R4736 1 2 10K_5%_2 R4775 1 2 10K_5%_2 1 2 10K_5%_2_DY A 2 ISOLATION PM_RI# IN PCIE_WAKE# IN 30< 37< 30< 55<> 19< 12< 30> SLP_LAN# OUT R4824 INVENTEC P3V3_S EVEREST-M PCH 3 TITLE PCI_3S_CLKRUN# IN R4733 1 2 8.2K_5%_2 SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Sun Jan 2 02 18:04:44 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 30 97 of 1 REV A01 8 7 6 5 1 3 2 1 1 R4845 100K_5%_2 P3V3_S 4 R4844 100K_5%_2 2 2 D D 1 R4842 2.2K_5%_2 2 U4700 1 R4841 2.2K_5%_2 67< 48< PCH_LCM_BKLTEN 67< 48< PCH_LCM_VDDEN OUT OUT R4843 2 67< 48< PCH_LCM_INVPWM 1 OUT PCH_LCM_INVPWM_R 2 J47 M45 L_BKLTEN SDVO_TVCLKINN L_VDD_EN SDVO_TVCLKINP P45 L_BKLTCTL SDVO_STALLN SDVO_STALLP 0_5%_2 67< PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA T40 K47 OUT OUT SDVO_INTN 2 67< 67< C PCH_LVDS_DDCDATA - 67< 67< 67< LVDS DETECT PCH_LVDS_TXCL_DN PCH_LVDS_TXCL_DP PCH_LVDS_TXDL0_DN PCH_LVDS_TXDL1_DN PCH_LVDS_TXDL2_DN AF37 AF36 LVD_IBG SDVO_CTRLCLK LVD_VBG SDVO_CTRLDATA AE48 AE47 LVD_VREFH AK39 AK40 OUT OUT AN48 AM47 AK47 AJ48 OUT OUT OUT L_CTRL_CLK LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 DDPB_AUXN DDPB_AUXP Interface 1 2.37K_1%_2 LVDSA_DATA#3 DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N LOW-LVDS ENABLED DISABLED 67< 67< 67< (DEFAULT) PCH_LVDS_TXDL0_DP PCH_LVDS_TXDL1_DP PCH_LVDS_TXDL2_DP AN47 AM49 AK49 AJ47 OUT OUT OUT AF40 AF39 LVDSA_DATA0 DDPB_3P Display HIGH-LVDS LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP AH43 AH49 AF47 AF43 B LVDSB_DATA#0 DDPC_HPD LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N LVDSB_DATA2 DDPC_2P LVDSB_DATA3 DDPC_3N DDPC_3P N48 P49 T49 OUT OUT OUT 1 1 R4791 150_1%_2 R4790 2 45< PCH_CRT_DDCCLK 45< PCH_CRT_DDCDATA T39 M40 OUT OUT M47 M49 CRT_GREEN CRT_RED DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN CRT_DDC_CLK DDPD_AUXP CRT_DDC_DATA DDPD_HPD 2 DDPD_0N 150_1%_2 R4789 1 OUT OUT CRT_BLUE CRT 45< PCH_CRT_BLUE 45< PCH_CRT_GREEN 45< PCH_CRT_RED 45< 45< 2 PCH_CRT_HSYNC PCH_CRT_VSYNC CRT_HSYNC DDPD_0P CRT_VSYNC DDPD_1N DDPD_1P 150_1%_2 DDPD_2N T43 T42 DAC_IREF DDPD_2P CRT_IRTN DDPD_3N 1 DDPD_3P R4729 1K_1%_2 P38 M39 AT49 AT47 AT40 PCH_DUAL_DDCDATA - AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 HIGH-DP DP DETECTED C ENABLED LOW-DP DISABLED (DEFAULT) P46 P42 BI BI AP47 AP49 AT38 BI BI IN PCH_DUAL_DDCCLK 47<> PCH_DUAL_DDCDATA 47<> PCH_DP_AUX_DN PCH_DP_AUX_DP PCH_DP_HPD 47> 47<> 47<> LVDSB_DATA#1 Digital AH45 AH47 AF49 AF45 AP39 AP40 L_CTRL_DATA LVDS R4882 AM42 AM40 L_DDC_CLK L_DDC_DATA SDVO_INTP T45 P39 AP43 AP45 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 OUT OUT OUT OUT OUT OUT OUT OUT PCH_DP_LANE0_DN PCH_DP_LANE0_DP PCH_DP_LANE1_DN PCH_DP_LANE1_DP PCH_DP_LANE2_DN PCH_DP_LANE2_DP PCH_DP_LANE3_DN PCH_DP_LANE3_DP 47< 47< 47< 47< 47< 47< 47< 47< B M43 M36 AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 ITL_PANTHERPOINT_FCBGA_989P 2 CLOSE TO PCH A A INVENTEC EVEREST-M PCH 4 AXG TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Sat Jan 2 01 18:30:03 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 31 97 of 1 REV A01 6 GPIO51 GPIO19 BOOT BIOS BBS_BIT1 BBS_BIT0 DESTINATION RSVD1 RESERVED(NAND) 1 0 - 1 1 0 0 BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 (DEFAULT) LPC P3V3_S 1 2 8.2K_5%_2 R4725 1 2 8.2K_5%_2 BI BI BI BI IN R4724 1 2 8.2K_5%_2 R4723 1 2 8.2K_5%_2 R4722 1 2 10K_5%_2_DY R4721 1 2 10K_5%_2_DY R4720 1 2 10K_5%_2_DY R4719 1 2 10K_5%_2 R4718 1 2 10K_5%_2_DY R4717 1 2 10K_5%_2 R4818 1 2 10K_5%_2 R4780 1 2 10K_5%_2 BI BI IN IN IN IN IN PCI_3S_INTA# 32<> PCI_3S_INTB# 32<> PCI_3S_INTC# 32<> PCI_3S_INTD# 32<> RUNSCI0# 3 RSVD2 1 R4711 4 U4700 0 SPI 5 TP1 RSVD3 TP2 RSVD4 TP4 RSVD5 TP5 RSVD6 TP7 RSVD7 TP8 RSVD8 RSVD9 TP9 TP10 RSVD10 TP11 RSVD11 TP12 RSVD12 TP13 RSVD13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 37> RSVD22 PCI_3S_INTG# 32<> PCI_3S_INTH# 32<> DGPU_HOLD_RST# 32> EC_DGPU_PWR_EN# 37> DGPU_SELECT# 32> SATA_ODD_DA# 32<> DGPU_PWR_EN# 32> Routed Total 37> 67< with length WS 67< 90 ohms impedance no longer than B21 M20 AY16 BG46 11 BI USB3_P1_RX_DN 50> 37< C USB3_P3_RX_DN BI USB3_P1_RX_DP BI USB3_P3_RX_DP BI USB3_P1_TX_DN BI BI USB3_P3_TX_DN BI USB3_P1_TX_DP P3V3_S BI USB3_P3_TX_DP TP21 TP24 AV5 RSVD24 AV10 RSVD25 AT8 USB3RN1 RSVD26 USB3RN2 RSVD27 USB3RN4 RSVD28 USB3RP1 RSVD29 USB3RP3 USB3RP4 DEBUG PORT USB3TN1 USBP0N USBP0P USB3TN2 USBP1N USB3TN3 USBP1P USB3TN4 USBP2N USB3TP1 USBP2P USB3TP2 USBP3N USB3TP3 USBP3P USB3TP4 USBP4N USBP6N USBP6P 1 R4728 1K_5%_2_DY 1 R4716 1K_5%_2_DY R4877 1K_5%_2_DY B 1 32< 67< 2 2 2 37> DGPU_HOLD_RST# 32< DGPU_SELECT# 37< 32< DGPU_PWR_EN# K40 K38 H38 G38 OUT OUT OUT C46 C44 E40 PIRQA# USBP7N PIRQB# USBP7P USBP8N PIRQC# PIRQD# REQ1#/GPIO50 DEBUG PORT USB BI BTMDL# BI BI BI BI PCI 54> 32<> PCI_3S_INTA# PCI_3S_INTB# PCI_3S_INTC# PCI_3S_INTD# REQ2#/GPIO52 REQ3#/GPIO54 USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N DGPU_PWM_SELECT# OUT R4821 1 2 0_5%_2 DGPU_PWM_SELECT#_R D47 E42 F46 GNT1#/GPIO51 USBP11P GNT2#/GPIO53 USBP12N GNT3#/GPIO55 USBP12P USBP13N STP_A16OVR TOP-BLOCK SWAP OVERRIDE LOW=A16 USBP13P SWAP OVERRIDE HIGH=DEFAULT P3V3_A 54> 32<> BTMDL# 32< 50> SATA_ODD_DA# 32<> PCI_3S_INTG# 32<> PCI_3S_INTH# 1 R4714 G42 G40 C42 D44 BI BI BI BI +V3A_PME# 10K_5%_2_DY 68< 60< 39< 37< PLT_RST# K10 C6 BI P3V3_A PIRQG#/GPIO4 USBRBIAS# 1 A R4881 OUT OUT OUT R4879 R4880 TP4702 2 55< 0.1UF_16V_2 CLK_PCI_DEBUG OUT 1 R4715 1 1 1 1 2 2 2 2 22_5%_2 22_5%_2 22_5%_2 CLK_PCI_EC_R CLK_PCI_TPM_R CLK_PCI_FB_R 22_5%_2 H49 H43 J48 K42 H40 BI BI BI BI BI BI USB_P0_DN USB_P0_DP USB_P1_DN USB_P1_DP USB_P2_DN USB_P2_DP RESERVE FOR USB3.0 BI BI USB_P5_DN USB_P5_DP WLAN BI BI USB_P10_DN USB_P10_DP WEBCAM BI BI BI BI USB_P12_DN USB_P12_DP USB_P13_DN USB_P13_DP BT 3G 1 C33 1 R4726 2 CLOSE TO PCH B33 PLTRST# OC0#/GPIO59 CLKOUT_PCI0 OC3#/GPIO42 CLKOUT_PCI1 OC4#/GPIO43 CLKOUT_PCI2 OC5#/GPIO9 CLKOUT_PCI3 OC6#/GPIO10 2 CLKOUT_PCI4 OC7#/GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 R4839 R4840 R4838 R4837 R4836 R4835 R4834 R4833 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_5%_2 0_5%_2 10K_5%_2 10K_5%_2 R4896 P3V3_A 1 3 1 2 R4832 10K_5%_2 2 OUT CHANGE 7 6 5 P3V3_A IN IN IN USB_OC#_0 RESERVE FOR USB3.0 USB_OC#_1 FOR eSATA USB_OC#_2 RESERVE FOR USB3.0 IN SMC_WAKE_SCI# 10K_5%_2 10K_5%_2 0_5%_2 IN IN PCH_XDPFN0 IN PCH_XDPFN2 IN PCH_XDPFN3 IN PCH_XDPFN4 IN PCH_XDPFN5 IN IN PCH_XDPFN6 4 3 by Frank Hu A PCH_XDPFN1 PCH_XDPFN7 INVENTEC DATE Sun Jan 2 02 17:15:21 EVEREST-M PCH 5 USB TITLE SIZE C 8 1 10K_5%_2 CLK_PCI_DEBUG_R SMC_WAKE_SCI# WS 1 10K_5%_2_DY PME# TC7SZ08FU R4817 10K_5%_2_DY 2 1 R4727 100K_5%_2 P3V3_A 22.6_1%_3 5 + BUF_PLT_RST# B 2 4 BI RESERVE FOR USB3.0 TP4715 ITL_PANTHERPOINT_FCBGA_989P U4701 eSATA TP4714 PIRQH#/GPIO5 OC2#/GPIO41 37<> CLK_PCI_EC 43< CLK_PCI_TPM 29< CLKIN_PCI_FB 1 PIRQF#/GPIO3 OC1#/GPIO40 C4772 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 PIRQE#/GPIO2 USBRBIAS 2 C WS USB3RP2 USBP5P 32<> 32<> 32<> 32<> AY5 BA2 AT12 BF3 USBP5N STP_A16OVR D USB3RN3 BBS_BIT1 2 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 RSVD23 USBP4P R4878 10K_5%_2 AT10 BC8 TP23 BBS STRAP 1 AY7 AV7 AU3 BG4 TP22 inches BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 1 TP6 RSVD21 33> 2 TP3 NVRAM D 7 RSVD 8 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 32 97 of 1 REV A01 8 7 6 5 4 3 2 1 STRAP PIN P3V3_A 1 R4831 2 1K_5%_2 OUT HOST_ALERT#1 - LOW - INTEL HIGH - HOST_ALERT#1 (DEFAULT) INTEL TLS CONFIDENTIALITY ME CRYPTO TRANSPORT LAYER SECURITY(TLS) ME CRYPTO TLS CIPHER SUITE CIPHER SUITE WITH NO CONFIDENTIALITY WITH CONFIDENTIALITY P3V3_A STRAP PIN INTEGRATED 1 CLOCKING R4779 D D 10K_5%_2_DY P3V3_S 2 1K_5%_2 LOW - (DEFAULT) HIGH - DISABLE OUT 33> 59< ICC_EN# ENABLE INTEGRATED INTEGRATED CLK CLK P3V3_S 32< 37> 59< R4870 1 2 10K_5%_2 R4864 1 2 10K_5%_2 R4862 1 2 10K_5%_2_DY R4830 1 2 200K_1%_2 R4826 1 2 10K_5%_2_DY OUT GFX_CRB_DET R4825 1 2 10K_5%_2 OUT CRIT_TEMP_REP# OUT BIOS_REC 33> 33< OUT MFG_MODE 33> 33< 33> 33< IN TEST_DET OUT C 33> 39<> OUT ICC_EN# OUT LAN_PHY_PWR P3V3_S 33> RUNSCI0# HOST_ALERT#1 2 10K_5%_2 R4872 1 2 10K_5%_2 R4871 1 2 10K_5%_2 PCH_XDPFN17 DGPU_HPD_INTR#_R R4819 1 2 0_5%_2 ICC_EN#_R R4875 1 2 0_5%_2 PCH_XDPFN16 OUT OUT T7 U4700 1 R4874 67< 33> 37> TACH4/GPIO68 BMBUSY#/GPIO0 A42 TACH1/GPIO1 TACH5/GPIO69 H36 TACH2/GPIO6 TACH6/GPIO70 E38 TACH3/GPIO7 TACH7/GPIO71 C10 GPIO8 C4 LAN_PHY_PWR_CTRL/GPIO12 G2 GPIO15 A20GATE PECI P3V3_A 33> 1 2 10K_5%_2 PCH_XDPFN14 U2 SATA4GP/GPIO16 50> 33> SATA_ODD_PRSNT# R4876 16> DGPU_PWROK 33> 33< 1:DEFAULT/0:ENABLE BIOS_REC D40 BI OUT P3V3_S TACH0/GPIO17 T5 SCLOCK/GPIO22 R4869 1 2 10K_5%_2 E8 GPIO24 R4784 1 2 10K_5%_2 E16 GPIO27 CPU/MISC 2 GPIO 1 R4820 RCIN# PROCPWRGD THRMTRIP# INIT3_3V# PCH_XDPFN8 OUT P8 GPIO28 K1 STP_PCI#/GPIO34 TS_VSS1 1 R4861 R4865 R4873 2 1 2 1 2 10K_5%_2 10K_5%_2_DY 10K_5%_2_DY 33> IN TEST_DET IN MFG_MODE 33> IN BIOS_REC R4811 1 2 10K_5%_2 R4868 1 2 10K_5%_2 PCH_XDPFN9 K4 GPIO35 OUT R4867 1 2 0_5%_2 PCH_XDPFN12 V8 SATA2GP/GPIO36 OUT R4866 1 2 0_5%_2 PCH_XDPFN13 M5 SATA3GP/GPIO37 OUT N2 SLOAD/GPIO38 OUT M3 SDATAOUT0/GPIO39 TS_VSS2 33< TS_VSS3 50> 33> SATA_ODD_PRSNT# TS_VSS4 33> 33> FDI_OVRVLTG NC_1 33< R4827 1 2 100K_5%_2 OUT GFX_CRB_DET 33> 33> 33> MFG_MODE GFX_CRB_DET B V13 37> 33> CRIT_TEMP_REP# 33< TEST_DET OUT 1 R4863 OUT 2 0_5%_2 PCH_XDPFN15 SDATAOUT1/GPIO48 VSS_NCTF_15 V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 D6 GPIO57 VSS_NCTF_17 1 R4828 2 2 1 R4829 1K_5%_2_DY OUT FDI_OVRVLTG 33> 10K_5%_2 LOW- TX,RXTERMINATED TO SAME VOLTAGE A4 VSS_NCTF_1 VSS_NCTF_19 A44 VSS_NCTF_2 VSS_NCTF_20 A45 VSS_NCTF_3 VSS_NCTF_21 A46 VSS_NCTF_4 VSS_NCTF_22 A5 VSS_NCTF_5 A6 VSS_NCTF_6 B3 VSS_NCTF_7 VSS_NCTF_25 B47 VSS_NCTF_8 VSS_NCTF_26 BD1 VSS_NCTF_9 VSS_NCTF_27 BD49 VSS_NCTF_10 VSS_NCTF_28 BE1 VSS_NCTF_11 VSS_NCTF_29 BE49 VSS_NCTF_12 VSS_NCTF_30 BF1 VSS_NCTF_13 VSS_NCTF_31 BF49 VSS_NCTF_14 VSS_NCTF_32 NCTF STRAP PIN VSS_NCTF_23 VSS_NCTF_24 FDI_OVRVLTG (DC COUPLING MODE) DEFAULT A R4781 1 2 10K_5%_2_DY IN PCH_XDPFN8 33> STRAP PCH_XDPFN8 HIGH-ENABLED - ON DIE PLL VOLTAGE REGULATOR R4860 1 21.5K_1%_1/16W R4853 1 2 A40 P4 AU16 IN PCH_PECI 0_5%_2_DY AY11 AY10 OUT H_PECI IN KBRST# 37> OUT THRMTRIP#_R AY1 2 R4712 1 AK11 2 IN 4 3 PM_THRMTRIP# 20> 38< 390_5%_2 AH10 BOTH THESE SHOULD BE AK10 CLOSE TO PCH P37 OUT NV_CLE WS 20> FOLLOW EDS1.0 B BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 A D1 D49 E1 E49 F1 F49 CHANGE 5 20< R4713 56_5%_2_DY AH8 INVENTEC SIZE C 6 C H_CPUPWRGD 60> P1V05_VCCPS EVEREST-M PCH 6 MISC LOW-DISABLED 7 37<> T14 TITLE 8 37< EC_3S_A20GATE 20> P5 ITL_PANTHERPOINT_FCBGA_989P (DEFAULT) SATA_ODD_PWREN 50< C41 WS VSS_NCTF_18 P3V3_S OUT B41 1 DF_TVS 33< C40 by Frank Hu DATE Sun Jan 2 02 17:58:29 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 33 97 of 1 REV A01 8 7 6 5 4 3 2 1 +V1.05S VCCCORE[5] VCCCORE[6] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] AN16 VCCIO[15] AN17 VCCIO[16] AK37 C4709 10uF_6.3V_3 0.01UF_50V_2 0.1UF_16V_2 D 15mil P1V8_S VCCTX_LVDS[1] AM37 VCCTX_LVDS[2] AM38 VCCTX_LVDS[3] AP36 VCCTX_LVDS[4] AP37 15mil 1 L4700 2 FBM_11_160808_121T C4708 C4707 C4706 0.01UF_50V_2 0.01UF_50V_2 22uF_6.3V_5 2 VCCAPLLEXP VSSALVDS C4748 2 BJ22 AK36 2 +V1.05S_VCCAPLLEXP +V1.05S VCCALVDS FBM_11_160808_121T C4756 1 VCCCORE[17] VCCIO[28] P3V3_S 2 1 VCCCORE[16] AN19 U47 1 VCCCORE[15] 20mil VSSADAC 1 2 VCCCORE[7] LVDS VCCCORE[4] CRT VCCCORE[3] P3V3_S L4701 15mil 1 2 2 2 2 +V1.05S POWER U48 2 1uF_6.3V_2 1uF_6.3V_2 VCCCORE[2] VCCADAC 2 1uF_6.3V_2 VCCCORE[1] 1 1 C4710 C4711 U4700 1 1 1 1 C4755 C4746 D 10uF_6.3V_3 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 VCC CORE 1.3A 1 0_5%_2_DY 3A C4751 C4752 1uF_6.3V_2 1uF_6.3V_2 C4750 1uF_6.3V_2 1uF_6.3V_2 2 2 2 2 2 10uF_6.3V_3 1 C4753 C4754 1 1 1 1 C 2 HVCMOS R4810 +V1.05S AN21 VCCIO[17] AN26 VCCIO[18] AN27 VCCIO[19] AP21 VCCIO[20] AP23 VCCIO[21] AP24 VCCIO[22] VCC3_3[6] V33 VCC3_3[7] V34 15mil AT16 1 VCCIO[23] AT24 VCCIO[24] DMI VCCIO 15mil AT20 VCCDMI[1] +V1.05S 15mil AB36 VCCIO[25] AN34 VCCIO[26] 1 VCC3_3[3] 2 15mil AP16 VCCVRM[2] R4809 2 +V1.05S_VccAFDIPLL 20mil P1V05_VCCPS BG6 AP17 VccAFDIPLL VCCIO[27] FDI 1 0_5%_2_DY NAND / +VCCAFDI_VRM +V1.05S VCCDFTERM[1] AG16 VCCDFTERM[2] AG17 VCCDFTERM[3] AJ16 VCCDFTERM[4] AJ17 15mil B C4745 0.1UF_16V_2 +V3M VCCSPI V1 15mil 1 15mil P1V8_S 2 SPI BH29 2 1 2 15mil C4732 1uF_6.3V_2 1UF_6.3V_2_DY AN33 1 C4775 0.1UF_16V_2 +V1.05S 0.1UF_16V_2 15mil C4749 B 2 P1V05_VCCPS VCCCLKDMI AP26 C C4747 1 +VCCAFDI_VRM VCCVRM[3] P3V3_S P3V3_S AU20 VCCDMI[2] C4744 ITL_PANTHERPOINT_FCBGA_989P 1uF_6.3V_2 2 A A P1V5_S +VCCAFDI_VRM R4808 1 2 INVENTEC 0_5%_3 40mil SIZE C CHANGE 8 7 6 5 4 EVEREST-M PCH 7 POWER TITLE 3 by Frank Hu DATE Sat Jan 2 01 18:30:57 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 34 97 of 1 REV A01 7 6 VCCACLK C4717 2 1 +V1.05S DCPSUSBYP T38 VCC3_3[5] 0_5%_2_DY 1 C4771 1uF_6.3V_2_DY 2 VCCAPLLDMI2 AL29 VCCIO[14] AL24 DCPSUS[3] +V1.05M C4714 22uF_6.3V_5 2 2 22uF_6.3V_5 +V1.05M 2 1uF_6.3V_2 2 1uF_6.3V_2 AA21 VCCASW[2] AA24 VCCASW[3] AA26 VCCASW[4] AA27 VCCASW[5] AA29 VCCASW[6] AA31 VCCASW[7] AC26 VCCASW[8] AC27 VCCASW[9] AC29 VCCASW[10] +V1.05S 2 VCCASW[11] AD29 VCCASW[12] C4727 0.1UF_16V_2 2 10uF_6.3V_3 2 2 1uF_6.3V_2 VCCASW[13] W21 VCCASW[14] W23 VCCASW[15] W24 VCCASW[16] W26 VCCASW[17] W29 VCCASW[18] W31 VCCASW[19] W33 VCCASW[20] 1 C4729 1 1 C4725 10uF_6.3V_3 VCCADPLLA VCCADPLLB +V1.05S C4723 +V1.05_LAN_M 1 2 2 15mil 15mil 1 1uF_6.3V_2 C4722 2 1 1uF_6.3V_2 C4721 2 1 15mil 15mil 2 1UF_6.3V_2_DY VCCVRM[4] BF47 VCCADPLLB T24 VCCSUS3_3[9] V23 1 VCCSUS3_3[10] V24 0.1UF_16V_2 VCCSUS3_3[6] P24 VCCIO[34] T26 V5REF_SUS M26 AN23 AN24 P34 VCCSUS3_3[2] N20 VCCSUS3_3[3] N22 VCCSUS3_3[4] P20 VCCSUS3_3[5] P22 10mil P3V3_A C4740 2 D4701 2 0.1UF_16V_2 1 P3V3_A 1uF_6.3V_2_DY VCC3_3[1] VCC3_3[8] W16 VCC3_3[4] T34 10mil V5REF 1 2 0.1UF_16V_2 3 P3V3_S BAT54_30V_0.2A 1 R4709 1 2 10_5%_5 C4737 1 2 1uF_10V_2 C 10mil C4736 2 P3V3_S 20mil C4773 1 2 0.1UF_16V_2 1 2 0.1UF_16V_2 P3V3_S 20mil AJ2 VCCIO[5] AF13 C4701 VCCIO[12] AH13 20mil VCCIO[13] AH14 VCCIO[6] AF14 AK1 1 2 0.1UF_16V_2 VCCVRM[1] AF11 VCCIO[2] AC16 VCCIO[3] AC17 VCCIO[4] AD17 B +V1.05S C4734 1 2 1uF_6.3V_2 +V1.05S 1 +V1.05S_VCCAPLLSATA L4702 2 +VCCAFDI_VRM 10mil +V1.05S VCCDIFFCLKN[3] DCPSST C4739 P3V3_A 0603_DY VCCDIFFCLKN[2] V16 10_5%_5 P5V_S VCCDIFFCLKN[1] VCCSSC 2 D4700 VCCIO[7] AG33 1 10mil 1uF_10V_2 AA16 R4710 10mil 1 +V1.05_LAN_M_DCPSUS<1> DCPSUS[1] DCPSUS[2] V_PROC_IO A22 0.1UF_16V_2 20mil 1 C4700 2 VCCRTC T21 VCCASW[22] +V1.05M V21 VCCASW[23] 20mil T19 VCCASW[21] P3V3_A VCCSUSHDA P32 ITL_PANTHERPOINT_FCBGA_989P 2 0.1UF_16V_2 C4733 0.1UF_16V_2 SIZE C CHANGE 7 6 5 EVEREST-M PCH 8 POWER TITLE 2 2 2 1uF_6.3V_2 INVENTEC 10mil 1 C4742 1 C4702 1 1 2 2 2 C4741 RTC CPU BJ8 +V_RTC 0.1UF_16V_2 8 D +V1.05S VSREF_SUS 2 1 P5V_A 20mil C4770 3 BAT54_30V_0.2A P3V3_A 10mil 1 VCCAPLLSATA 1 1 1 C4718 0.1UF_16V_2 VCCSUS3_3[8] DCPRTC VCCADPLLA T17 V19 10mil 4.7uF_6.3V_3 T23 A 1 C4719 VCCSUS3_3[7] P3V3_A P3V3_S P1V05_VCCPS C4743 T29 1uF_10V_2 1uF_6.3V_2 0.1UF_16V_2 0_5%_2_DY C4720 VCCIO[33] VCC3_3[2] BD47 AF17 AF33 AF34 AG34 1 1uF_6.3V_2 2 T27 C4716 C4735 MISC R4805 Y49 20mil C4724 A N16 15mil 2 2 1uF_6.3V_2 1 1 2 22UF_6.3V_5_DY C4726 VCCIO[32] V5REF SATA +VCCAFDI_VRM 1 C4712 P28 VCCSUS3_3[1] 2 FBM_11_160808_121T VCCIO[31] C4738 HDA 1 2 22UF_6.3V_5_DY B C4728 1 C4713 P26 DCPSUS[4] AC31 AD31 FBM_11_160808_121T VCCIO[30] 1 C4731 C4730 1 2 1uF_6.3V_2 C 1 C4703 VCCASW[1] 1 1 C4715 1.1A AA19 PCI/GPIO/LPC 20mil BH23 Miscellaneous +V1.05S_VCCAPLLDMI2 and 2 Clock 1 USB R4806 +V1.05S N26 VCCDSW3_3 V12 2 2 0.1UF_10V_2_DY VCCIO[29] 2 10uF_6.3V_3 T16 1 0.1UF_16V_2 2 POWER 2 AD49 +V1.05S_VCCACLK 3A 1 1 1 C4774 D 1 NC 2 U4700 0_5%_2_DY 20mil L4703 2 2 1 15mil C4704 C4705 L4704 3 +V1.05S R4807 P3V3_A 1 4 +V1.05S P3V3_S 0.1UF_16V_2 5 NC 8 4 3 by Frank Hu DATE Sat Jan 2 01 18:31:14 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 35 97 of 1 REV A01 8 7 H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 D C B 6 5 4 3 AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 U4700 VSS[0] VSS[1] VSS[80] VSS[2] VSS[81] VSS[3] VSS[82] VSS[4] VSS[83] VSS[5] VSS[84] VSS[6] VSS[85] VSS[7] VSS[86] VSS[8] VSS[87] VSS[9] VSS[88] VSS[10] VSS[89] VSS[11] VSS[90] VSS[12] VSS[91] VSS[13] VSS[92] VSS[14] VSS[93] VSS[15] VSS[94] VSS[16] VSS[95] VSS[17] VSS[96] VSS[18] VSS[97] VSS[19] VSS[98] VSS[20] VSS[99] VSS[21] VSS[100] VSS[22] VSS[101] VSS[23] VSS[102] VSS[24] VSS[103] VSS[25] VSS[104] VSS[26] VSS[105] VSS[27] VSS[106] VSS[28] VSS[107] VSS[29] VSS[108] VSS[30] VSS[109] VSS[31] VSS[110] VSS[32] VSS[111] VSS[33] VSS[112] VSS[34] VSS[113] VSS[35] VSS[114] VSS[36] VSS[115] VSS[37] VSS[116] VSS[38] VSS[117] VSS[39] VSS[118] VSS[40] VSS[119] VSS[41] VSS[120] VSS[42] VSS[121] VSS[43] VSS[122] VSS[44] VSS[123] VSS[45] VSS[124] VSS[46] VSS[125] VSS[47] VSS[126] VSS[48] VSS[127] VSS[49] VSS[128] VSS[50] VSS[129] VSS[51] VSS[130] VSS[52] VSS[131] VSS[53] VSS[132] VSS[54] VSS[133] VSS[55] VSS[134] VSS[56] VSS[135] VSS[57] VSS[136] VSS[58] VSS[137] VSS[59] VSS[138] VSS[60] VSS[139] VSS[61] VSS[140] VSS[62] VSS[141] VSS[63] VSS[142] VSS[64] VSS[143] VSS[65] VSS[144] VSS[66] VSS[145] VSS[67] VSS[146] VSS[68] VSS[147] VSS[69] VSS[148] VSS[70] VSS[149] VSS[71] VSS[150] VSS[72] VSS[151] VSS[73] VSS[152] VSS[74] VSS[153] VSS[75] VSS[154] VSS[76] VSS[155] VSS[77] VSS[156] VSS[78] VSS[157] VSS[79] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 ITL_PANTHERPOINT_FCBGA_989P A 2 U4700 VSS[159] VSS[259] VSS[160] VSS[260] VSS[161] VSS[261] VSS[162] VSS[262] VSS[163] VSS[263] VSS[164] VSS[264] VSS[165] VSS[265] VSS[166] VSS[266] VSS[167] VSS[267] VSS[168] VSS[268] VSS[169] VSS[269] VSS[170] VSS[270] VSS[171] VSS[271] VSS[172] VSS[272] VSS[173] VSS[273] VSS[174] VSS[274] VSS[175] VSS[275] VSS[176] VSS[276] VSS[177] VSS[277] VSS[178] VSS[278] VSS[179] VSS[279] VSS[180] VSS[280] VSS[181] VSS[281] VSS[182] VSS[282] VSS[183] VSS[283] VSS[184] VSS[284] VSS[185] VSS[285] VSS[186] VSS[286] VSS[187] VSS[287] VSS[188] VSS[288] VSS[189] VSS[289] VSS[190] VSS[290] VSS[191] VSS[291] VSS[192] VSS[292] VSS[193] VSS[293] VSS[194] VSS[294] VSS[195] VSS[295] VSS[196] VSS[296] VSS[197] VSS[297] VSS[198] VSS[298] VSS[199] VSS[299] VSS[200] VSS[300] VSS[201] VSS[301] VSS[202] VSS[302] VSS[203] VSS[303] VSS[204] VSS[304] VSS[205] VSS[305] VSS[206] VSS[306] VSS[207] VSS[307] VSS[208] VSS[308] VSS[209] VSS[309] VSS[210] VSS[310] VSS[211] VSS[311] VSS[212] VSS[312] VSS[213] VSS[313] VSS[214] VSS[314] VSS[215] VSS[315] VSS[216] VSS[316] VSS[217] VSS[317] VSS[218] VSS[318] VSS[219] VSS[319] VSS[220] VSS[320] VSS[221] VSS[321] VSS[222] VSS[322] VSS[223] VSS[323] VSS[224] VSS[324] VSS[225] VSS[325] VSS[226] VSS[328] VSS[227] VSS[329] VSS[228] VSS[330] VSS[229] VSS[331] VSS[230] VSS[333] VSS[231] VSS[334] VSS[232] VSS[335] VSS[233] VSS[337] VSS[234] VSS[338] VSS[235] VSS[340] VSS[236] VSS[342] VSS[237] VSS[343] VSS[238] VSS[344] VSS[239] VSS[345] VSS[240] VSS[346] VSS[241] VSS[347] VSS[242] VSS[348] VSS[243] VSS[349] VSS[244] VSS[350] VSS[245] VSS[351] VSS[246] VSS[352] 1 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B A VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] INVENTEC VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] ITL_PANTHERPOINT_FCBGA_989P SIZE C CHANGE 8 7 6 5 4 EVEREST-M PCH 9 GND TITLE 3 by Frank Hu DATE Sun Jan 2 02 18:04:06 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 36 97 of 1 REV A01 8 7 6 5 4 P3V3_AL 102 4 AVCC VDD 1 1 1 R352 R302 R353 2 2 IN WLON# OUT 1 R331 2 10K_5%_2_DY Enable shared BIOS 37<> 55> 100K_5%_2 Memory OUT 84 83 82 112 110 73 6 IN BI OUT OUT BOARDID1 R300 - NUM_LED#_3 64 95 93 94 119 109 120 USB1_PWREN OUT EC_PW_ON# OUT C GPO76_SHBM IN OUT IN 1 0_5%_2 2 AD1_GPIO91 LCLK NEED 0.1UF AD2_GPIO92 LFRAME# AD3_GPIO93 LAD0 GPIO05 LAD1 GPIO04 LAD2 LAD3 DA0_GPIO94 SERIRQ DA1_GPIO95 GPIO11_CLKRUN# DA2_GPIO96 GPIO97 KBRST#_GPIO86 GPIO85_GA20 GPIO66_G_PWM ECSCI#_GPIO54 GPIO65_SMI# GPIO01 GPIO67_PWUREQ# GPIO03 GPIO71 GPIO06 GPIO72 GPIO07 GPO83_SOUT_CR_TRIST# GPIO23_SCL3 SDA4_GPIO53 GPIO30 GPIO36 GPIO31_SDA3 GPIO51 SCL4_GPIO47 GPIO77 GPIO87_SIN_CR GPO76_SHBM GPIO75 VTT ECSTRAP110 EC_MUTE# 54<> BTIFON# PECI GPO82_TEST# GPIO45_E_PWM GPIO70 GPIO40_F_PWM GPIO24 2 10K_5%_2_DY OUT SCROLL_LED#_3 30> FM_32KHZ IN MAIN_PWRGD IN 37<> STRAP PIN HIGH - (Default) LOW - TEST MODE NORMAL MODE P3V3_AL P3V3_AL Close R321 1 R319 1 2 2 1 R314 R301 R375 EC R303 R341 1 1 2 62 118 32 63 31 117 0_5%_2 0_5%_2 0_5%_2 TP_ON# OUT 58< WL_OLED# OUT CAPS_LED#_3 OUT EC_SMB2_DATA EC_SMB2_CLK 8> 8> BI BI 65 66 68 67 69 70 BI BI P5V_S R322 R323 53<> 53<> H_PROCHOT# OUT 1 1 2 47K_5%_2 2 47K_5%_2 IM_DAT_5 IM_CLK_5 12< 19< 30> 30> BI BI 90 91 92 2 2 11 10 71 72 0_5%_2 0_5%_2 44 GPIO46_TRST# GPIO00_EXTCLK GPIO52_PSDAT3_RDY# CLKOUT_GPIO55 VCC_POR# C_PWM_GPIO13 KBSIN0 B_PWM_GPIO21 KBSIN1 A_PWM_GPIO15 KBSIN2 TB1_GPIO14 KBSIN3 TA1_GPIO56 KBSIN4 TA2_GPIO20 KBSIN5 KBSIN6 GPIO32_D_PWM KBSIN7 GPIO33_H_PWM KBSOUT0_JENK# KBSOUT1_TCK GPIO74_SDA2 KBSOUT2_TMS GPIO73_SCL2 KBSOUT3_TDI GPIO22_SDA1 KBSOUT4_JEN0# GPIO17_SCL1 KBSOUT5_TDO KBSOUT6_RDY# F_SDIO1 KBSOUT7 F_SDIO0 KBSOUT8 KBSOUT9_SDP_VIS# F_CS0# KBSOUT10_P80_CLK GPIO81 KBSOUT11_P80_DAT F_SCK KBSOUT12_GPIO64 KBSOUT13_GPIO63 PSDAT2_GPIO27 KBSOUT14_GPIO62 PSCLK2_GPIO26 KBSOUT15_GPIO61_XOR_OUT GPIO35_PSDAT1 KBSOUT16_GPIO60 GPIO37_PSCLK1 KBSOUT17_GPIO57 VCORF C301 PECI 1 2 54 55 56 57 58 59 60 61 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 R366 2 2 1 1 2 2 1 1 R364 R363 R311 R310 R309 R308 R307 R306 R305 R304 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_5%_2 0_5%_2 0_5%_2 0_5%_2 220_5%_2 220_5%_2 220_5%_2 220_5%_2 220_5%_2 220_5%_2 220_5%_2 220_5%_2 1 H_PROCHOT#_EC 1uF_6.3V_2 2 IN S 1 SSM3K7002BFU FAN_TACH CRIT_TEMP_REP# SLP_S5# USB0_PWREN 52< DRAMRST_CNTRL_EC RSMRST# WS EC_EDP_MUX_IC_SEL VCC_POR# IN SCAN_IN<0> SCAN_IN<7..0> 0 1 SCAN_IN<1> 2 SCAN_IN<2> 3 SCAN_IN<3> 4 SCAN_IN<4> 5 SCAN_IN<5> 6 SCAN_IN<6> 7 SCAN_IN<7> SCAN_OUT<0> SCAN_OUT<1> SCAN_OUT<2> SCAN_OUT<3> SCAN_OUT<4> SCAN_OUT<5> SCAN_OUT<6> SCAN_OUT<7> SCAN_OUT<8> SCAN_OUT<9> SCAN_OUT<10> SCAN_OUT<11> SCAN_OUT<12> SCAN_OUT<13> SCAN_OUT<14> SCAN_OUT<15> SCAN_OUT<16> SCAN_OUT<17> WINB_NPCE791LA0DX_LQFP_128P PAD300 1 1 2 P3V3_S CLOSE IC EC 37< 8> 37< 8> HW_I_ADC HW_V_ADC BATT_IN IN IN OUT R357 Thermal R380 BOARDID0 Thermal BOARDID1 IN 0: 1: 2 1.5K_1%_2_DY 2 10K_5%_2 R379 1 21.5K_1%_1/16W R361 1 2 P3V3_AL R333 1 2 10K_5%_2 R376 R336 1 1 2 0_5%_2 2 33_5%_2 1 2 3 4 U300 CS# DO VCC HOLD# W P# CLK GND DI 8 7 6 5 R330 1 R334 1 R335 1 2 3.3K_5%_2 2 33_5%_2 2 33_5%_2 IN IN EC_SPI_CLK 28> 37> 37> EC_SPI_SI 28> C307 WINB_W25Q80BVSSIG_SOIC_8P 0.1UF_16V_2 10K_5%_2_DY SIZE C CHANGE 8 7 6 5 37> 53> 4 3 by Frank Hu DATE Tue Jan 2 04 11:09:01 A JTAG select (Default) INVENTEC EVEREST-M EC TITLE 2 IN R362 1 1 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 STRAP PIN 1 2.GPU 1.CPU IN OUT 2 2 2 OUT SCAN_OUT<0> 10K_5%_2_DY EC_SPI_CS0# EC_SPI_SO 1 1 1 C317 C316 C315 1 1.Charge 1.Battery EC_SMB3 PIN GND_KBC_ALG CLOSE TO EC 2 EC_SMB2 B 2 2 P3V3_AL EC_SMB1 2 4.7uF_6.3V_3 CLOSE IC GND_KBC_ALG 680pF_50V_2 P3V3_A P3V3_AL L300 FBM_11_160808_121T C312 C310 GND_KBC_ALG C314 PIN 1 0.1UF_16V_2 C 2 0.1UF_16V_2 2 4.7uF_6.3V_3 +V3LA_EC OUT SCAN_OUT<17..0> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN 4.7uF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 2 2 2 2 2 2 1 1 C313 C306 POWERPAD1x1m 100K_5%_2 Close 58< 58< OUT OUT OUT OUT OUT OUT IN IN 2 A 37< 38> 1 2 R356 CLOSE IC 1 1 1 1 1 1 C308 C305 C311 C300 C304 C303 2 G P3V3_AL 33> BAT_OLED# SUS_OLED# OUT IN R365 20> H_PECI BI 22 16 17 20 21 23 25 27 85 KBRST# 33< EC_3S_A20GATE RUNSCI0# EC_SMI 28< OUT IN OUT OUT DGPU_PWR_EN# 32< EC_PWRSW# WS FLASH_OVERRIDE P1V05_VCCPS 3G_ON# 26> PM_EXTTS#1 IN OUT OUT OUT IN 0_5%_2 R378 D BOARDID0 0_5%_2 D Q300 PSCLK3_GPIO50_TDO GPIO02 1 3 R367 1 1 10K_5%_2_DY 10K_5%_2 2 IN EC_SPI_SO OUT EC_SPI_SI EC_SPI_CS0# OUT SMC_WAKE_SCI# OUT OUT EC_SPI_CLK 1 R359 IN SLP_LAN# 1 R358 IN SLP_SUS# 86 87 2 2 10K_5%_2 R329 EC_DGPU_PWR_EN# DGPU_HOLD_RST# CHG_EN OUT OUT IN OUT R368 R360 R345 2 28< 37> 28> 37< IN BI BI BI BI BI BI BI BI 1 72<> 72<> 2 2.2K_1%_2 2 2.2K_1%_2 1 1 77 79 30 1 0_5%_2 53< 2 3.3K_5%_2 2 3.3K_5%_2 EC_SMB1_DATA EC_SMB1_CLK OUT OUT OUT IN IN 2 ACPRESENT 30< 30> SUS_STAT# 32<> R354 39< PLT_RST# 68< 32> 60< CLK_PCI_EC LPC_3S_FRAME# 28<>10K_5%_2 43< LPC_3S_AD<0> 55< LPC_3S_AD<1> 28<> 43< 55< LPC_3S_AD<2> 28<> 43< 55< LPC_3S_AD<3> 43< 28<> PCI_3S_SERIRQ 55< PCI_3S_CLKRUN# 30<> 30< 43< IN 1 OUT 1 B BAT_BLED1# DCIN_BLED# FAN_PWMA FAN_TACH SLP_S4# 58< 72<> 38> 37< 38> 11< 30> R370 GND6 GND1 GND2 GND3 GND4 GND5 ECSTRAP110 BI 5 18 45 78 89 116 2 GPIO44_TDI GPIO16 AGND R377 GPIO43_TMS 103 1 114 0_5%_2 43_1%_2 GPO84_XORTR# GPIO42_TCK low-Enabled 12 13 R369 2 P3V3_A P3V3_A 1 LRESET# P3V3_S 2 GPIO34 GPIO10_LPCPD# AD0_GPIO90 P3V3_S 2 VREF 1 10< ACPRES# PWR_BLED# LID_SW#_3 8> 58< 57> BI 55< 1 0_5%_2 2 0_5%_2_DY 1 0_5%_2 1 0_5%_2 81 R372 BI EC_SMB3_CLK EC_SMB3_DATA R374 2 R355 1 R373 2 R371 2 EC_LCM_INVPWM OUT 2 10K_5%_2 1.8K_5%_2 PWR_SWIN#_3 29<> SLP_S3# IN EC_PCH_PWROK OUT 18< 17< 11< 30> 97 98 99 100 108 96 101 105 106 107 14 124 7 2 3 126 127 128 1 125 8 122 121 29 9 123 74 75 111 28 15 26 24 113 1 P3V3_AL 8> 8> 9> 104 1 HW_I_ADC IN HW_V_ADC IN BATT_IN OUT H_PROCHOT#_EC OUT 48< 44< EC_BKLTEN OUT SW_LCM_BKLTEN IN IN SLP_A# D +V3LA_EC_VREF 2 4.7K_5%_2 1 2 R339 U301 1 +V3LA_EC GPIO41 37< 2 VCC_POR# OUT 37< 37< 37> 29<> 80 19 46 76 88 115 VCC1 VCC2 VCC3 VCC4 VCC5 2 NC 1 BAT54_30V_0.2A 1.8K_5%_2 10K_5%_2 100K_5%_2 30< EC_LCM_INVPWM RSMRST# 37> 30< 2 10K_5%_2 1 3 +V5AUXON OUT OUT LOW_BAT#_3 R313 1 2 9> R312 2 R340 100K_5%_2 P3V3_S +V3LA_EC OUT OUT 1 P3V3_S 1 P3V3_AL 1 10< 2 20mil R316 D302 3 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 37 97 of 1 REV A01 8 7 6 5 4 3 2 1 P5V_S D 30mil P3V3_S R4304 4.7K_5%_2 2 CN4300 1 2 3 4 1 37< FAN_TACH D OUT 1 2 3 G 4 G 2 2 C4303 1 0.1UF_16V_2 C4304 4.7UF_10V_3 1 G1 G2 1 C4302 1000PF_50V_2_DY ACES_50273_0047N_001_4P 2 P3V3_S C R4305 C 2 4.7K_5%_2 1 37> FAN_PWMA OUT 18< 14> OUT THRM_SHUTDWN# VR_PWRGD IN 1 P5V_AL 2M_5%_2 SET GND OT R4302 1 2 32.4K_1%_2 PM_THRMTRIP# OUT THRM_SHUTDWN# 1 IN R4301 330_5%_2 GMT_G708T1U_SOT23_5P Q4301 2 1 B 2 SSM3K7002BFU B E HYST 1 2 3 C 1 VCC S 5 4 C4301 G 3 +THM_VDD 2 150_5%_2 0.1UF_16V_2 1 U4411 1 LMBT3904LT1G 2 1 R4303 3 Q4300 D 2 10mil B R4300 C4300 CSC0402_DY 2 2 GM Thermal shutdown at 80.8℃ PM Thermal shutdown at 86℃ RSET=0.0012*T2-0.9308*T+96.147 Hysteresis is 30C +/-3℃ +/-3℃ from from 60℃ 60℃ to to 100℃ 100℃ A A INVENTEC EVEREST-M FAN & THERMAL TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:37 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 38 97 of 1 REV A01 8 7 6 5 4 3 2 1 30MIL +V3M +V3M_LAN D D R415 2 1 0_5%_5 C416 0.1UF_16V_2 1 1 2 2 C414 C415 22UF_6.3V_5 0.1UF_16V_2 1 C413 1 2 0.1UF_16V_2 2 P3V3_A 0805 1 R411 10K_5%_2 2 U400 68< 60< 37< 29> 29> 2 R417 1 BI LAN_JTAG_TMS 39<> BI LAN_JTAG_TCK 39<> CLKREQ_LAN# 32<> PLT_RST# OUT IN R410 R418 1 1 2 2 CLKREQ_LAN#_R 0_5%_2 PLT_RST#_R 0_5%_2 IN IN CLK_PCIE_LAN_DP CLK_PCIE_LAN_DN 29< 29< PCIE_LAN_RX_DP PCIE_LAN_RX_DN OUT OUT 29> 29> PCIE_LAN_TX_DP PCIE_LAN_TX_DN IN IN 1 1 C404 C403 2 2 PCIE_LAN_RX_C_DP PCIE_LAN_RX_C_DN 0.1UF_16V_2 0.1UF_16V_2 48 36 CLK_REQ_N 44 45 PE_CLKP MDI_PLUS1 PE_CLKN MDI_MINUS1 38 39 PETp MDI_PLUS2 PETn MDI_MINUS2 41 42 PERp MDI_PLUS3 PERn MDI_MINUS3 28 31 SMB_CLK MDI_PLUS0 PE_RST_N MDI_MINUS0 MDI +V3M_LAN PCIE 29< C 13 14 BI BI LAN_TRD0_DP LAN_TRD0_DN 40< 40< 17 18 BI BI LAN_TRD1_DP LAN_TRD1_DN 40< 40< 20 21 BI BI LAN_TRD2_DP LAN_TRD2_DN 40< 40< 23 24 BI BI LAN_TRD3_DP LAN_TRD3_DN 40< 40< C +V3M_LAN 10K_5%_2_DY R416 1 29< 29> SML0_CLK 29< 29> SML0_DATA R408 BI BI R409 1 1 2 2 SMB_CLK_LAN SMB_DATA_LAN 0_5%_2 0_5%_2 6 +V3M_LAN_RSVD_NC +V3M_LAN_RSVD_VCC3P3_1 +V3M_LAN_RSVD_VCC3P3_2 VDD3P3_IN 1 2 5 VDD3P3_OUT 4 RSVD_NC SMBUS 2 SMB_DATA RSVD_VCC3P3_1 10K_5%_2_DY RSVD_VCC3P3_2 LAN_ENABLE 1 40< R407 10K_5%_2 B 1 BI 1 1 1 R406 39<> 39<> 0_5%_2_DY 2 OUT LAN_X1 VDD3P3_19 VDD3P3_29 39< LAN_JTAG_TMS LAN_JTAG_TCK 39> 39> 0_5%_2 LAN_X1 LAN_X2 32 34 33 35 TP402 TP401 BI BI 9 10 IN IN JTAG_TDI JTAG_TDO JTAG_TMS XTAL_IN 43 VDD1P0_11 11 15MIL 40 22 16 8 15MIL VDD1P0_22 2 1 OUT LAN_X2 39< 25MHZ 1 C411 33PF_50V_2 1 2 C412 33PF_50V_2 R404 1K_5%_2 1 2 VDD1P0_8 30 TEST_EN 12 RBIAS 2 2 0_5%_2_DY 1 1 2 2 4.7K_5%_2 4.7K_5%_2 1 C400 2 B 1UF_10V_2 15MIL +V1.05_LAN_M +V1.05_LAN R402 1 CTRL_1P0 7 VSS_EPAD 49 2 15MIL 0_5%_5 +V1.05_LAN_CTRL_1P0 1 R403 3.01K_1%_2 2 +V1.05_LAN VDD1P0_43 VDD1P0_40 R400 2 0_5%_2 VDD1P0_37 JTAG_TCK XTAL_OUT R413 47 46 37 VDD1P0_46 VDD1P0_16 X400 1 LED2 VDD1P0_47 2 1 TP400 LED1 R401 1 15MIL 15 19 29 VDD3P3_15 LED0 2 0_5%_2 R412 1 26 27 25 JTAG LAN_PHY_PWR BI BI LAN_DISABLE_N 2 R405 33> LED_R3S_LANACT# LED_R3S_LANLINK# 3 LED +V3M_LAN R414 L400 1 2 0603_DY 4.7UH ITL_LEWISVILLE_PQFN_48P C401 22UF_6.3V_5 1 1 2 2 C402 0.1UF_16V_2 A A INVENTEC EVEREST-M LAN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:38 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 39 97 of 1 REV A01 8 7 LED_R3S_LANACT# 6 R477 1 IN 5 4 3 2 1 2 RSC_0603_DY +V3M_LAN WS D 1 R478 2 RSC_0603_DY 1 R476 2 LED_R3S_LANLINK# IN JACK470 LAN_TRD3_CN_DP LAN_TRD3_CN_DN LAN_TRD2_CN_DP LAN_TRD1_CN_DP LAN_TRD1_CN_DN LAN_TRD2_CN_DN LAN_TRD0_CN_DP LAN_TRD0_CN_DN RSC_0603_DY 1 2 3 4 5 6 7 8 IN IN IN IN IN IN IN IN TX+ D TXRX+ G P4 G P5 G RX- G G1 G2 G3 G4 P7 P8 SYN_100073HR008G13CZL_8P 1 R475 2 RSC_0603_DY +V3M_LAN C C 1 R472 0_5%_2_DY 2 WS B +V3M_LAN_TRANSFORMER LAN_TRD3_DN LAN_TRD3_DP LAN_TRD2_DN LAN_TRD2_DP LAN_TRD1_DN LAN_TRD1_DP IN IN LAN_TRD0_DN LAN_TRD0_DP IN IN IN IN IN IN U470 1 3 2 4 6 5 7 9 8 10 12 11 TCT1 MCT1 TD1- MX1- TD1+ MX1+ TCT2 MCT2 TD2- MX2- TD2+ MX2+ TCT3 MCT3 TD3- MX3- TD3+ MX3+ TCT4 MCT4 TD4- MX4- TD4+ MX4+ 24 22 23 21 19 20 18 16 17 15 13 14 OUT OUT LAN_TRD0_CN_DN LAN_TRD0_CN_DP 40< 40< OUT OUT LAN_TRD1_CN_DN LAN_TRD1_CN_DP 40< 40< OUT OUT LAN_TRD2_CN_DN LAN_TRD2_CN_DP 40< 40< OUT OUT LAN_TRD3_CN_DN LAN_TRD3_CN_DP 40< 40< B BOTH_GST5009_SOP_24P 1 2 1 C409 0.1UF_16V_2 2 1 C408 0.1UF_16V_2 2 C407 0.1UF_16V_2 1 2 1 C406 0.1UF_16V_2 2 C405 1UF_6.3V_2 1 1 R473 8152 1 R474 1 R470 R471 75_5%_3 75_5%_3 75_5%_3 75_5%_3 2 2 2 2 OPEN A 1 2 A C410 1000PF_2000V_6 INVENTEC EVEREST-M RJ45 & TRANSFORMER TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 00:15:14 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 40 97 of 1 REV A01 8 7 6 5 4 3 2 1 1 R511 5.11K_1%_2 2 R508 1 2 39.2K_1%_2 R507 1 D 2 10K_1%_2 D P3V3_A 10 MIL OUT C509 1 1 2 2 42< C_BIAS C510 LDO_OUT_3.3V 10UF_6.3V_5 0.1UF_16V_2 10 MIL 1 R512 100_5%_2 NEAR CODEC 1 C518 1 C519 2 10UF_6.3V_5 2 0.1UF_16V_2 R501 ONLY NEEDED FOR -11Z AND IF SUPPLY TO VAUX_3.3 IS REMOVED DURING SYSTEM RE-START. 11/16 MODIFY FOR VENDOR COMMAND 1 1 1 C507 40 39 38 37 36 35 34 33 32 31 2 C508 2 2 0.1UF_16V_2 2 C R513 R500 1 1 2 2 0_5%_2 33_5%_2 HDA_3S_SDIN0_R C504 1 2 33_5%_2 2 0.1UF_16V_2 C506 1 1 2 CSC0402_DY CSC0402_DY RESERVE FOR EMI 1 PCSPKR_PCH_3_R 1 C532 CSC0402_DY 2 (10-22PF) C533 DMIC1-2 VAUX_3.3 FILT_1.8 AVEE 30 29 28 27 26 25 24 23 22 21 GND 41 PORTC_L FILT_1.65 SDATA_OUT AVDD_5V AVDD_3.3 BIT_CLK AVDD_HP U500 SDATA_IN NC VDD_IO NC SYNC PORTA_R RESET# PORTA_L PC_BEEP 1 C516 2 1 C530 2 10UF_6.3V_5 1 C531 2 0.1UF_16V_2 1UF_6.3V_2 1 C517 P3V3_A HEADPHONE JACK INTERNAL PORT C: MICROPHONE JACK MIC P3V3_S 10 MIL MIL 1 10 PORT A: PORT B: 0.1UF_16V_2 2 CONEX_CX20671_21Z_QFN_40P 2 C PORT CONFIGURATION 11 12 13 14 15 16 17 18 19 20 R502 1 2 3 4 5 6 7 8 9 10 LEFT+ LPWR_5.0 LEFTRIGHTRPWR_5.0 RIGHT+ CLASS-D_REF DVDD_3.3 FLY_P FLY_N 10UF_6.3V_5 DMIC_CLK SPDIF GPIO0-EAPD# GPIO1-SPK_MUTE# SENSE_A PORTB_R PORTB_L B_BIAS C_BIAS PORTC_R R501 10K_5%_2_DY C511 B 1 C512 2 0.1UF_16V_2 2 C522 1 1UF_6.3V_2 B 2 1UF_6.3V_2 1 C529 2 0.1UF_16V_2 0OHM_5% 1206 R509 2 1 R506 SPK_OUT_L+_R 0_5%_2 2 1 R505 SPK_OUT_L-_R 0_5%_2 2 0_5%_2 0_5%_2 C534 CSC0402_DY A 2 1 1 2 C526 1 0.1UF_16V_2 1 C514 1 C513 2 0.1UF_16V_2 2 0.1UF_16V_2 2 10UF_6.3V_5 1A 0_5%_6 1 SPK_OUT_R+_R R503 2 2 1 C515 PAD +V5S_LPWR_5.0 SPK_OUT_R-_R R504 1 1 2 C527 0.1UF_16V_2 1 C528 2 10UF_6.3V_5 1 C520 10UF_6.3V_5 1 C521 2 0.1UF_16V_2 C525 2 10UF_6.3V_3 1 PLACE BYPASS CAPS CLOSE TO DEVICE. 2 C535 CSC0402_DY A 1 2 C536 CSC0402_DY 1 1 2 C537 CSC0402_DY RESERVE FOR EMI, 2 120 CLOSE TO CODEC OHMS@100MHZ INVENTEC EVEREST-M AUDIO CODEC TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Sun Jan 2 02 13:16:19 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 41 97 of 1 REV A01 8 7 6 5 4 AUDIO 3 2 1 JACKS PORT C EXTENAL 41> C_BIAS MICROPHONE IN D D 1 1 R601 3.3K_5%_2 R600 3.3K_5%_2 2 JACK600 5 4 3 6 2 1 G1 G2 Recommended R605 R604 1 C608 CSC0402_DY 1 C609 CSC0402_DY 2 CN600 1 1 2 100_5%_2 C602 2 2.2UF_6.3V_2 2 D602 VARISTOR_DY VARISTOR_DY 2 2 2 C G1 close 1 C606 C605 CSC0402_DY CSC0402_DY CSC0402_DY 2 to 2 G1 PHP_PESD5V2S2UT_SOT23_3P D600 2 3 PORT A HEADPHONE 2 4 3 G2 1 ACES_50224_0040N_001_4P C604 CSC0402_DY 2 B connector 1 R602 2 5.1_5%_2 2 5.1_5%_2 1 1 R603 JACK601 G2 G1 1 2 6 3 4 5 1 place 1 C607 2 EMI, 1 1 D601 1 1 G2 for 2.2UF_6.3V_2 SPEAKERS 1 2 3 4 Reserve 2 protection C603 1 C B 1 for 100_5%_2 1 SINGA_2SJ_T351_019_6P INTERNAL 2 SINGA_2SJ_T351_019_6P D604 1 D603 VARISTOR_DY 2 CSC0402_DY 2 C601 CSC0402_DY 2 2 VARISTOR_DY 1 C600 A A INVENTEC EVEREST-M AUDIO AMP TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Sun Jan 2 02 13:17:10 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 42 97 of 1 REV A01 8 7 6 5 4 3 D 2 P3V3_A 15mil 1 2 D R3500 NC FOR SUPPORT VPRO STUFF FOR FW1.2 C3502 0.1UF_16V_2 P3V3_S P3V3_S C 56< 55< 37<> 55< 20< LCLK 28> LPC_3S_FRAME# IN 22 LFRAME# 32<> BUF_PLT_RST# IN 16 LRESET# 28 LPCPD# 1 1 R3501 P3V3_S 55< 37<> 28<> PCI_3S_SERIRQ 37<> 30<> PCI_3S_CLKRUN# 30< R3502 2 NC LAD3 VDD VDD GND GND GND GND 10 19 24 1 R3500 2 C3505 0_5%_2_DY 4 11 18 25 C3504 0.1UF_16V_2 C3503 0.1UF_16V_2 0.1UF_16V_2 2 21 LAD2 5 1 IN VSB LAD1 2 CLK_PCI_TPM LAD0 C 0_5%_2 2 4.7K_5%_2 27 15 IN IN PP NC SERIRQ NC CLKRUN# NC 7 1 3 12 C3501 9 TESTBI_BADD 8 TESTI XTALI_32K_IN XTALO GPIO GPIO2 13 14 6 2 TPM_XTALI TPM_XTALO 1 4 3 LPCPD# SHOULD BE CONNECT TO VDD 26 23 20 17 1 2 10PF_50V_2 X3500 R3503 10M_5%_2 INFINEON_SLB9635TT1.2_FW3.16_TSSOP_28P 2 32.768KHZ C3500 1 2 32> U3500 IN IN IN IN LPC_3S_AD<0> LPC_3S_AD<1> LPC_3S_AD<2> LPC_3S_AD<3> 1 28<> 28<> 28<> 28<> 2 37<> 37<> 37<> 37<> 1 15mil 55< 55< 55< 55< 1 1 2 10PF_50V_2 TPM1.2 B B P/N FW VERSION A 1.02 6019B0101801 3.16 6019B0761601 (SUPPORT A VPRO) INVENTEC EVEREST-M TPM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:39 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 43 97 of 1 REV A01 8 R? 1 IN IN IN PCH_LVDS_TXDL0_DN PCH_LVDS_TXDL1_DN PCH_LVDS_TXDL0_DP PCH_LVDS_TXDL2_DP PCH_LVDS_TXCL_DP IN IN IN IN IN EDP_TX1_DN IN PCH_LVDS_TXDL1_DP PCH_LVDS_TXDL2_DN PCH_LVDS_TXCL_DN EDP_TX0_DN IN EDP_TX1_DP IN R? 1 2 0_5%_2_DY R? 1 IN 2 0_5%_2_DY R? 1 2 0_5%_2_DY R? 1 2 0_5%_2_DY 1 2 2 3 3 2 0_5%_2 4 4 1 2 0_5%_2 5 5 1 2 0_5%_2 6 6 7 7 8 8 9 9 R? R? 2 P3V3_S P3V3_S 10 1 2 47K_5%_2 1 Place 0.01UF_50V_2 2 3 D 4 S C3008 D 470K_5%_2 as possible 30mil 6 5 2 1 to connector +V3S_PCH_LCM_VDDEN C3003 S AM3423P 0.1UF_16V_2 11 12 13 13 14 14 17 18 18 19 19 20 20 23 +VBAT_LVDS 24 24 1 30mil 25 25 G G1 26 26 G G2 27 27 28 28 29 29 30 30 1 R3000 0.1uF_25V_3 2 2 LED panel +VBAT_LVDS 44< 44< 32<> 32<> USB_P10_DN USB_P10_DP IN IN 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 IN IN SW_LVDS_DDCCLK SW_LVDS_TXDL0_DN SW_LVDS_TXDL0_DP SW_LVDS_TXDL2_DN SW_LVDS_TXDL2_DP GPU_LVDS2_TXDL0_DN GPU_LVDS2_TXDL0_DP IN IN GPU_LVDS2_TXDL2_DN GPU_LVDS2_TXDL2_DP BI IN IN IN IN R3003 2 R3001 1 MIC_IN_CLK MIC_IN_DATA IN IN 1 2 33_5%_2 41> C 100_5%_2 44< G2 ACES_88242_4600_46P IN SW_LCM_INVPWM P3V3_S IN B R3008 10K_5%_2_DY 1 IN P3V3_S B 2 PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA R3007 ACES_50252_03001_002_30P CPT PANEL 10K_5%_2 P5V_S 2 P3V3_S 1 LOW:DISABLE 2 1 VIO VIO 6 2 GND VBUS 5 VIO USB_P10_DP 4 IN IN 32<> 32<> 44< 44< 41> IN 44< 41> IN MIC_IN_DATA MIC_IN_CLK 1 VIO USB_P10_DN 1 3 A 5 HI:ENABLE U3001 2 C3000 0.1UF_16V_2 0.1UF_16V_2 1 C3005 44< D3000 D3001 VARISTOR_DY VARISTOR_DY A EC_BKLTEN IN 2 1 4 NXP_IP4223CZ6_SOT457_6P_DY R3005 2 2 37> 1 2 48< IN 100_5%_2 - EC_EDP_MUX_IC_SEL + U3000 TC7SZ08FU 1 1 3 2 for IN 2 1 4.7uF_25V_5 2.2K_5%_2 S C3009 2 40mil SSM3K7002BFU IN IN G1 1 C3010 2.2K_5%_2 2 KC_FBM_11_160808_101A20T_2P C3007 22 2 R3002 1 3 D 1 G IN IN G1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 G2 2 Q3002 IN IN 0.1UF_16V_2 21 C3001 1 2 20mil 23 IN 1000PF_50V_2 L3001 67> 67> P3V3_S 22 2 PCH_LCM_INVPWM PVBAT BI IN IN GPU_LVDS2_TXDL1_DN GPU_LVDS2_TXDL1_DP GPU_LVDS2_TXCL_DN GPU_LVDS2_TXCL_DP C 21 100_5%_2 67> 67> 1 16 17 1 R3006 1 SW_LVDS_DDCDATA SW_LVDS_TXDL1_DN SW_LVDS_TXDL1_DP SW_LVDS_TXCL_DN SW_LVDS_TXCL_DP 15 16 2 2 2 10uF_6.3V_3 2 SSM3K7002BFU CN3000 10 12 C3004 G 680pF_50V_2 1 D 11 15 1 1 IN G 3 1 PCH_LCM_VDDEN close 1 Q3001 2 PMOS_4D1S 1 as Q3000 R3009 2 D C3006 R3010 3 CN? 1 0_5%_2 1 4 P3V3_S 2 0_5%_2_DY R? 1 R? 5 2 0_5%_2_DY 2 0_5%_2_DY 1 6 2 0_5%_2_DY R? 1 R? 1 R? 7 R3004 C3002 100K_5%_2 INVENTEC CSC0402_DY 2 2 EVEREST-M LCM CONN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 11:07:56 2011 CODE CS SHEET DOC.NUMBER REV CS_1310AXXXXXX-MTR 44 97 of 1 A01 8 7 31> 31> 31> PCH_CRT_RED IN PCH_CRT_GREEN IN R3076 PCH_CRT_BLUE IN R3075 D 1 R3077 6 0_5%_2 2 OUT 5 CRT_R 45< 1 2 0_5%_2 OUT CRT_G 45< 1 2 0_5%_2 OUT CRT_B 45< 45> 4 CRT_R 45> CRT_G 31> PCH_CRT_VSYNC 31> PCH_CRT_HSYNC IN R3074 1 2 0_5%_2 OUT CRT_VSYNC 45< IN R3073 1 2 0_5%_2 OUT CRT_HSYNC 45< 45> CRT_B 31> PCH_CRT_DDCDATA 31> PCH_CRT_DDCCLK IN R3072 1 2 0_5%_2 OUT CRT_DDCDATA IN R3071 1 2 0_5%_2 OUT CRT_DDCCLK 45< 1 2 IN R3070 71> GPU_CRT_G IN R3069 71> GPU_CRT_B IN R3068 1 2 0_5%_2_DY 71> GPU_CRT_VSYNC IN R3067 1 2 0_5%_2_DY 71> GPU_CRT_HSYNC IN R3066 1 2 0_5%_2_DY 71> GPU_CRT_DDCDATA IN R3065 1 2 0_5%_2_DY 71> GPU_CRT_DDCCLK IN R3064 1 2 0_5%_2_DY C 1 L3052 1 IN 2 CRT_R_L 2 R3052 1 LOW18ANR12G00BD L3051 1 IN L3050 1 IN 1 2 OUT CRT_R_CN 45< 2 OUT CRT_G_CN 45< 2 OUT CRT_B_CN 45< 0_5%_2 CRT_G_L 2 R3053 1 LOW18ANR12G00BD D 0_5%_2 CRT_B_L 2 R3054 1 LOW18ANR12G00BD 0_5%_2 45< 1 1 1 R3061 150_1%_2 R3060 150_1%_2 R3059 150_1%_2 2 2 2 71> GPU_CRT_R 3 1 2 1 C3065 10PF_50V_2 2 1 C3064 10PF_50V_2 2 C3063 1 C3052 1 C3051 1 C3050 10PF_50V_2 2 22PF_50V_2 2 22PF_50V_2 2 22PF_50V_2 1 C3062 1 C3061 2 10PF_50V_2 2 10PF_50V_2 1 C3060 10PF_50V_2 2 0_5%_2_DY 2 0_5%_2_DY C FOLLOW INTEL DESIGN GUIDE CO-LAYOUT P3V3_S P3V3_S P5V_S P5V_S 2 P5V_S B 1 R3063 2.2K_5%_2 B 1 R3062 2.2K_5%_2 2 2 45< 45> CRT_R_CN 45< 45> CRT_G_CN 45> CRT_B_CN 45< 1 2 3 4 5 6 7 8 IN IN IN VCC-SYNC SYNC_OUT2 VCC-VIDEO SYNC_IN2 VIDEO_1 SYNC_OUT1 VIDEO_2 SYNC_IN1 VIDEO_3 DCC_OUT2 GND DDC_IN2 VCC-DCC DDC_IN1 BYP DDC_OUT1 16 15 14 13 12 11 10 9 CRT_VSYNC_R R3051 1 2 33_5%_2 CRT_HSYNC_R R3050 1 2 33_5%_2 IN OUT IN IN OUT CRT_VSYNC_CN 45< CRT_VSYNC 45> CRT_HSYNC_CN 45< 45> CRT_HSYNC CRT_DDCDATA_R 45<> CRT_DDCDATA 45> CRT_DDCCLK 45> CRT_DDCCLK_R 45<> OUT IN OUT TI_TPD7S019_15DBQR_SSOP_16P 1 2 2 0.22UF_6.3V_2 1 2 P5V_S FUSE3050 1 R3058 2.2K_5%_2 45> CRT_DDCDATA_R CRT_DDCCLK_R +V5S_CRTCONNPWR_FUSE 2 R3056 33_5%_2 R3055 2 CRT_DDCDATA_CN 45> 45> 2 CRT_HSYNC_CN CRT_VSYNC_CN IN IN 1 2 3 4 5 6 7 8 9 10 11 12 G1 13 G2 G1 G2 14 15 CRT_DDCCLK_CN 33_5%_2 1 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IN IN IN R3057 2.2K_5%_2 1 BI CN3050 CRT_R_CN CRT_G_CN CRT_B_CN 1A_32V_0467001 1 BI 45< 45> 45> 45> 2 +V5S_CRTCONNPWR_D 1 0.22UF_6.3V_2 45> 45< 45< 1 2 C3053 MILS) C3056 C3057 C3059 0.1UF_10V_2_DY 12PF_50V_2_DY 2 12PF_50V_2_DY A SYN_070546FR015S251ZR_15P 1 0.22UF_6.3V_2 1 C3054 (40 1 1 2 2 C3058 0.1UF_10V_2_DY 2 C3055 SBR3U40P1 1 D3050 U3050 INVENTEC EVEREST-M CRT CONN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:01 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 45 97 of 1 REV A01 8 7 6 1 P3V3_GPUS R3165 1 G 2 S 1 2 499_1%_2 R3172 1 2 499_1%_2 R3171 1 2 499_1%_2 4 D R3170 1 2 499_1%_2 R3169 1 2 499_1%_2 R3168 1 2 499_1%_2 R3167 1 2 499_1%_2 R3166 1 2 499_1%_2 LINE4 NC LINE3 NC 71> 71> 71> C 71> GPU_HDMI_TX2_DN GPU_HDMI_TX1_DP GPU_HDMI_TX1_DN GPU_HDMI_TX0_DP 71> GPU_HDMI_TX0_DN 1 VCC GND LINE2 NC LINE1 NC 6 7 8 9 10 D CLOSE TO CONNECTOR Q3152 SSM3K7002BFU GPU_HDMI_TX2_DP 2 SEM_0544M_MSOP_10P_DY 5 4 3 2 1 3 2 71> 3 D3154 1M_5%_2 D R3173 5 0.1UF_16V_2 C3153 IN 1 2 1 2 1 2 1 2 1 2 IN 1 GPU_HDMI_TX2_R_DP 2 GPU_HDMI_TX2_R_DN 2 GPU_HDMI_TX1_R_DP 2 GPU_HDMI_TX1_R_DN 2 GPU_HDMI_TX0_R_DP 2 GPU_HDMI_TX0_R_DN R3155 1 0_5%_2 GPU_HDMI_TX1_C_DN R3154 1 0_5%_2 R3153 GPU_HDMI_TX0_C_DP 1 C 0_5%_2 0.1UF_16V_2 C3156 R3156 1 GPU_HDMI_TX1_C_DP 0.1UF_16V_2 C3157 IN 2 0_5%_2 0.1UF_16V_2 C3154 IN GPU_HDMI_TX2_C_DN 0.1UF_16V_2 C3155 IN R3157 1 0_5%_2 0.1UF_16V_2 C3152 IN GPU_HDMI_TX2_C_DP GPU_HDMI_TX0_C_DN R3152 1 2 0_5%_2 CN3150 71> GPU_HDMI_TXC_DN IN 1 2 GPU_HDMI_TXC_R_DP 2 GPU_HDMI_TXC_R_DN 0_5%_2 0.1UF_16V_2 1 R3151 1 2 C3158 IN GPU_HDMI_TXC_C_DP GPU_HDMI_TXC_C_DN R3150 1 2 0_5%_2 P5V_S +V5S_HDMI TP3150 D3155 10 9 8 7 6 B NC LINE1 NC LINE2 VCC GND NC LINE3 NC LINE4 TP35 1 1 2 3 4 5 D3153 2 46<> 46<> HDMI_CN_DDCCLK HDMI_CN_DDCDATA FUSE3150 1 40MIL 1 1 C3150 2 100PF_50V_2 71< GPU_HDMI_HPDET 2 +V5LA_HDMI_CONNPWR TMDS-DATA2-SHIELD TMDS-DATA2TMDS-DATA1+ TMDS-DATA1-SHIELD TMDS-DATA1TMDS-DATA0+ TMDS-DATA0-SHIELD TMDS-DATA0TMDS-CLOCK+ TMDS-CLOCK-SHIELD TMDS-CLOCKCEC G1 RESERVED G2 DDC-CLOCK G3 DDC-DATA G4 G1 G2 G3 G4 DDC-CEC-GND B +5V-POWER HOT-PLUG-DETECT 1A_32V_0467001 SBR3U40P1 SEM_0544M_MSOP_10P_DY R3158 1 OUT SYN_100042MR019M153ZL_19P 2 1K_5%_2 CLOSE TO CONNECTOR +V5S_HDMI BI BI TMDS-DATA2+ 2 1 C3151 D3151 D3152 R3163 100K_5%_2 2 D3150 22PF_50V_2_DY 2 2 2 2 1 1 1 1 71> GPU_HDMI_TXC_DP 0.1UF_16V_2 C3159 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 D3156 2 1 1 R3159 A R3174 4.7K_5%_2 4.7K_5%_2 2 2 2 4.7K_5%_2 G 4.7K_5%_2 2 R3161 1 R3175 1 0_5%_2_DY P3V3_GPUS 1 VARISTOR_DY SBR3U40P1 R3162 A VARISTOR_DY VARISTOR_DY G 71<> GPU_HDMI_DDCCLK 1 BI R3160 2 S 33_5%_2 S D D BI HDMI_CN_DDCCLK BI HDMI_CN_DDCDATA 46<> G Q3151 SSM3K17FU G 71<> GPU_HDMI_DDCDATA BI 1 R3164 2 S 33_5%_2 S D D INVENTEC 46<> Q3150 SSM3K17FU SIZE C CHANGE 8 7 EVEREST-M HDMI CONN TITLE 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:40 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 46 97 of 1 REV A01 8 7 IN PCH_DP_LANE0_DN IN PCH_DP_LANE1_DP IN PCH_DP_LANE1_DN IN PCH_DP_LANE2_DN 1 2 1 2 1 1 IN 2 1 PCH_DP_LANE3_DN IN 2 PCH_DP_LANE3_C_DP 0.1UF_16V_2 2 1 PCH_DP_LANE3_C_DN 0.1UF_16V_2 C3302 IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PCH_DP_LANE2_C_DN 0.1UF_16V_2 C3303 PCH_DP_LANE3_DP PCH_DP_LANE2_C_DP 0.1UF_16V_2 C3304 D CN3300 2 C3305 1 PCH_DP_LANE1_C_DN 0.1UF_16V_2 C3306 2 PCH_DP_LANE1_C_DP 0.1UF_16V_2 1 3 PCH_DP_LANE0_C_DN 2 C3307 4 PCH_DP_LANE0_C_DP 0.1UF_16V_2 C3308 IN 5 0.1UF_16V_2 C3309 PCH_DP_LANE0_DP PCH_DP_LANE2_DP 6 1 2 DDC_AUX_EN# OUT DDCCLK_AUXP_CN P3V3_S P5V_S DDCDATA_AUXN_CN BI D3300 PCH_DP_HPD_CN OUT 1 1 2 +V3S_DPCONNPWR_FUSE 2 40mil G BI SBR3U40P1 FUSE3300 1A_32V_0467001 1 +V3S_DPCONNPWR_D SSM3K17FU 1 G 1 R3300 1M_5%_2 R3307 31< S PCH_DP_HPD OUT D S C IN D PCH_DP_HPD_CN 100K_5%_2 2 3 4 5 D 6 7 8 9 10 11 12 13 14 15 16 17 G1 18 G2 19 G3 20 G4 G1 G2 G3 G4 MLX_105020_6001_20P 1 R3308 5.1M_5%_2 1 2 R3309 0_5%_2 2 2 2 Q3300 C PIN 14 :DDC buffer ID distinguish from HDMI &DVI Adapter PCH_DP_AUX_C_DP D G 2 PCH_DP_AUX_M_DP Q3307 S SSM3K17FU G D G S S 1 Q3301 D S BI 0.1UF_16V_2 D PCH_DP_AUX_DP C3301 G SSM3K17FU PCH_DP_AUX_C_DN S Q3306 S G SSM3K17FU G D B G D P3V3_S PCH_DP_AUX_M_DN S 2 1 B Q3310 D S BI 0.1UF_16V_2 D PCH_DP_AUX_DN C3300 G SSM3K17FU 1 R3301 2.2K_5%_2 D PCH_DUAL_DDCCLK_M Q3305 D D Q3309 D S 2 S BI S DDCCLK_AUXP_CN BI S PCH_DUAL_DDCCLK 47<> G G 1 G G SSM3K17FU SSM3K17FU 2 P3V3_S 1 R3302 100K_5%_2 Q3308 D PCH_DUAL_DDCDATA_M Q3304 D D D S 1 2 S DDCDATA_AUXN_CN BI S 2 BI P5V_S P3V3_S 1 R3304 2.2K_5%_2 S PCH_DUAL_DDCDATA R3303 100K_5%_2 47<> 1 R3306 R3305 10K_5%_2 SSM3K17FU G G SSM3K17FU 2 Q3302 3 Q3303 D 3 A 2 D G A G 10K_5%_2 1 G 1 DDC_AUX_EN# IN S 2 SSM3K7002BFU INVENTEC 2 SSM3K7002BFU SIZE C CHANGE 7 EVEREST-M DP CONN TITLE PCH Dual-mode 8 6 5 4 47> S G 3 by Frank Hu DATE Fri Dec 2 31 10:16:41 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 47 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_S P3V3_S 1 R3354 47K_5%_2 D C3358 2 2 D 1 0.01UF_50V_2 Q3350 2 3 G 1 PMOS_4D1S R3353 470K_5%_2 S 2 IN G D Q3352 C3359 4 S 1 PCH_LCM_VDDEN 1 2 D SSM3K7002BFU +V3S_eDPCONNPWR 6 5 2 1 1 2 AM3423P 680pF_50V_2 1 C3357 C3352 2 10uF_6.3V_3 40mil 0.1UF_16V_2 3 1 R3350 2 D SSM3K7002BFU C 100_5%_2 3 C 1 S G Q3351 P3V3_S 2 1 C3350 0.1UF_16V_2 2 CN3350 21> 21> 5 37> EC_BKLTEN 1 IN 2 C3354 2 0.1UF_16V_2 1 2 1 0.1UF_16V_2 C3351 EDP_HPD#_CN R3352 4 1 EDP_TX0_C_DN EDP_TX0_C_DP OUT 2 100_5%_2 - 44< IN OUT OUT U3350 + PCH_LCM_BKLTEN EDP_TX0_DN EDP_TX0_DP G1 1 3 5 7 9 11 13 15 17 19 21 23 G2 1 3 TC7SZ08FU B 1 C3356 R3351 100K_5%_2 2 2 G1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 4 6 8 10 12 14 16 18 20 22 24 EDP_AUX_C_DP EDP_AUX_C_DN OUT OUT IN PCH_LCM_INVPWM ACES_87216_2406_24P 1 R3358 R3360 2 OUT PVBAT 21< 3 Q3353 100K_5%_2_DY EDP_HPD# D 100K_5%_2_DY R3355 1K_5%_2 2 40mil 1 2 B P1V05_VCCPS G2 CSC0402_DY P3V3_S 1 48< 48< EDP_AUX_DP BI 1 C3361 2 IN EDP_AUX_C_DP 21<> EDP_AUX_DN BI 1 L3350 2 +VBAT_eDP KC_FBM_11_160808_101A20T_2P 0.1UF_16V_2 C3360 1 48> C3355 2 IN EDP_AUX_C_DN EDP_HPD#_CN 1 IN G S 21<> 4.7uF_25V_5 48> 1 2 1 2 SSM3K7002BFU 1 C3353 2 R3356 0.1uF_25V_3 2 100K_5%_2 0.1UF_16V_2 1 1 R3359 A R3357 A 2 2 100K_5%_2_DY 100K_5%_2_DY INVENTEC EVEREST-M EDP CONN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 11:08:43 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 48 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D CARDREADER/USB CONNECTOR P3V3_S C C P5V_A 30mil 1.5A ACES_50503_0184N_001_18P 32<> 32<> 32<> 32<> 32<> 32<> B 32< 58< USB1_PWREN USB_P1_DP USB_P1_DN USB_P2_DP USB_P2_DN IN IN IN USB_P8_DP USB_P8_DN IN IN USB_OC#_1 LED_3IN1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 IN IN IN OUT 18 17 G2 16 G1 G2 G1 15 14 13 12 11 10 9 8 7 B 6 5 4 3 2 1 CN255 A A INVENTEC EVEREST-M TITLE DB CONN USB & CARDREADER SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:02 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 49 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_S 1 R1700 RSC_0603_DY CLOSE TO SATA CONN CN1700 2 28> 28> D 28< 28< IN IN SATA_HDD_TX_DP SATA_HDD_TX_DN 1 2 2 C1702 OUT OUT SATA_HDD_RX_DN SATA_HDD_RX_DP 1 0.01UF_50V_2 C1705 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SATA_HDD_TX_C_DP SATA_HDD_TX_C_DN 0.01UF_50V_2 C1704 C1703 1 0.01UF_50V_2 1 0.01UF_50V_2 SATA_HDD_RX_C_DN SATA_HDD_RX_C_DP 2 2 1 D1701 VARISTOR_DY 1 D1702 +V3S_SATAHDDCONN 1 1 D1703 VARISTOR_DY VARISTOR_DY 2 D1700 VARISTOR_DY 2 2 2 P5V_S 40MILS 1 C1706 1 C1701 1 C1700 2 22UF_6.3V_5 2 22UF_6.3V_5 2 0.1UF_16V_2 GND A+ AGND D BB+ GND V3.3 V3.3 V3.3 GND GND GND V5 V5 V5 GND RESERVED GND V12 V12 G1 V12 G2 G1 G2 SYN_127043HR022M22SZR_22P SATA HDD C P5V_S P3V3_S C 1 R1900 RSC_0603_DY 1 1 R1751 1M_5%_2 CN1900 2 2 P3V3_S 1 1 2 C1753 R1752 PMOS_4D1S D 3 G SSM3K7002BFU 28< 28< SATA_SSD_RX_DN SATA_SSD_RX_DP OUT OUT C1904 C1903 2 0.01UF_50V_2 1 0.01UF_50V_2 1 2 1 2 C1906 0.01UF_50V_2 1 SATA_SSD_TX_C_DP SATA_SSD_TX_C_DN 2 C1905 0.01UF_50V_2 SATA_SSD_RX_C_DN SATA_SSD_RX_C_DP 2 AM3423P Q1750 P5V_S +V3S_SATASSDCONN 1.1A D S B 1 IN IN 4 G 3 2 IN SATA_SSD_TX_DP SATA_SSD_TX_DN S R1753 10K_5%_2 SATA_ODD_PWREN 28> 28> 2 1M_5%_2 Q1751 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1000PF_50V_2 6 5 2 1 +V5S_SATAODDCONN_MOS 1 2 3 4 5 6 7 8 9 10 11 12 B 13 14 15 G 16 G G1 G2 ACES_88501_1601_16P C1900 C1750 C1751 C1752 1 1 1 2 2 2 10UF_6.3V_3 1UF_6.3V_2 1 2 1 2 1 C1902 2 22UF_6.3V_5 22UF_6.3V_5 1UF_6.3V_2 C1901 0.1UF_16V_2 SATA SSD CN1750 P6 P5 P4 P3 P2 P1 S7 S6 S5 S4 S3 S2 S1 R1750 32< 32<> SATA_ODD_DA# OUT 1 33> 28< 28< SATA_ODD_RX_DP SATA_ODD_RX_DN OUT OUT 28> 28> SATA_ODD_TX_DN SATA_ODD_TX_DP IN IN C1754 C1755 1 1 0.01UF_50V_2 1 SATA_ODD_PRSNT# OUT SATA_ODD_RX_C_DP SATA_ODD_RX_C_DN 0.01UF_50V_2 2 2 C1757 C1756 SATA_ODD_R_DA# 0_5%_2 CLOSE TO SATA CONN A 2 1 0.01UF_50V_2 SATA_ODD_TX_C_DN SATA_ODD_TX_C_DP 0.01UF_50V_2 2 2 1 1 D1751 VARISTOR_DY 2 1 D1753 VARISTOR_DY 2 2 GND MD +5V +5V DP GND A B+ BGND AA+ G1 GND G2 G1 G2 SYN_127382FR013G503ZR_13P 1 D1750 VARISTOR_DY GND D1752 VARISTOR_DY INVENTEC 2 SATA ODD SATA HDD/SSD SIZE C CHANGE 8 7 6 5 EVEREST-M TITLE 4 3 by Frank Hu DATE Sun Jan 2 02 18:54:06 2011 CODE CS SHEET & ODD CONN DOC.NUMBER CS_1310AXXXXXX-MTR 50 97 of 1 REV A01 8 7 6 5 4 3 2 1 E-SATA D C1811 28> 2 IN SATA_ESATA_TX_DN SATA_ESATA_TX_C_DN 1 SATA_ESATA_RX_C_DN 0.01UF_50V_2 C1810 28> 2 IN SATA_ESATA_TX_DP C1803 2 1 SATA_ESATA_TX_C_DP 1 SATA_ESATA_RX_C_DP 0.01UF_50V_2 1 C1807 1 1 1 1 2 2 2 0.1UF_16V_2 VCC VCC GND EN GND U1800 D1 GND D0 VCC VCC 2 6 7 8 9 10 28< EN D0 D1 FUNCTION 0 X X STANDBY 2 IN 1 R1801 4.7K_5%_2 R1800 RSC_0402_DY 15 14 13 12 11 IN OUT REDRIVER_ESATA_TX_DN 2 2 OUT R1802 4.7K_5%_2_DY C TI_SN75LVCP412RTJR_QFN_20P REDRIVER_ESATA_TX_DP 1 R1803 4.7K_5%_2 1 TX_0P TX_0N GND RX_1N RX_1P 0.1UF_16V_2 TML 1 R1804 4.7K_5%_2 RX_0P RX_0N GND TX_1N TX_1P 21 20 19 18 17 16 C1806 1 1UF_6.3V_2 SATA_ESATA_RX_DP PINS 2 1UF_6.3V_2 OUT D P3V3_S 1 2 3 4 5 C C1808 28< 0.01UF_50V_2 P3V3_S C1809 SATA_ESATA_RX_DN C1802 2 P3V3_S CLOSE TO IC OUT 0.01UF_50V_2 REDRIVER_ESATA_RX_DP 51> REDRIVER_ESATA_RX_DN 51> 1 0 0 DEFAULT 1 1 0 CH0->5DB 1 0 1 CH1->5DB 1 1 1 CH0,1->5DB 2 B B +USB_VCC0 40MIL CN1800 32<> 32<> USB_P0_DN USB_P0_DP BI BI 4 1 L1800 3 2 WCM_2012_900T USB_P0_L_DN USB_P0_L_DP 1 VCC GND 5 2 USB_N TXP 6 REDRIVER_ESATA_TX_C_DP C1805 REDRIVER_ESATA_TX_C_DN C1804 3 USB_P TXN 7 4 GND GND 8 G1 RXN 9 REDRIVER_ESATA_RX_C_DN RXP 10 REDRIVER_ESATA_RX_C_DP GND 11 G1 G2 G3 G4 G2 G3 G4 1 TWIN_EU103_117CRL_TW_11P 2 2 C1801 2 C1800 2 1 D1801 VARISTOR_DY A 2 1 D1803 VARISTOR_DY 2 1 1 1 0.01UF_50V_2 IN REDRIVER_ESATA_TX_DP 51> IN REDRIVER_ESATA_TX_DN 51> OUT REDRIVER_ESATA_RX_DN 51< OUT REDRIVER_ESATA_RX_DP 51< 0.01UF_50V_2 0.01UF_50V_2 0.01UF_50V_2 1 D1802 VARISTOR_DY 2 1 D1800 VARISTOR_DY A 2 INVENTEC EVEREST-M E-SATA CONN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:42 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 51 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D ESATA POWER P5V_A PAD1800 1 1 2 2 +V5A_ESATAPWR_IN 40MIL POWERPAD1X1M C 1 C1815 2 0.01UF_50V_2 +USB_VCC0 U1801 37> USB0_PWREN 1 2 3 4 IN GND OUT IN OUT IN OUT EN OC# 8 7 6 5 40MIL 1 1 C1813 1 C1812 2 22UF_6.3V_5 2 0.1UF_16V_2 R1805 RSC_0402_DY 2 GMT_G547G1P81U_MSOP_8P 1 C1814 2 0.1UF_16V_2 C CLOSE TO ESATA CONNECTOR P3V3_AL 1 B B R1806 10K_5%_2 2 OUT USB_OC#_1 A A INVENTEC EVEREST-M USB CONN TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Sun Jan 2 02 18:04:58 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 52 97 of 1 REV A01 8 7 14" 6 5 4 3 1 P3V3_S KEYBOARD PTWO_AFF340_A2G1V_P SCAN_OUT<17..0> OUT 16 34 33 32 31 SCAN_OUT<16> R254 17 0_5%_2 1 SCAN_OUT<17> 2 D 4 2 SCAN_OUT<2> SCAN_OUT<15> SCAN_OUT<1> SCAN_OUT<0> 11 9 5 6 SCAN_OUT<5> SCAN_OUT<6> 10 14 8 12 SCAN_OUT<14> SCAN_OUT<8> SCAN_OUT<12> C 53< 53< 37< 37< SCAN_IN<7> SCAN_IN<2> IN IN 53< 53< 53< 53< 37< 37< 37< 37< SCAN_IN<3> SCAN_IN<4> SCAN_IN<0> SCAN_IN<5> IN IN IN IN 10 9 8 7 53< 53< 37< 37< SCAN_IN<6> SCAN_IN<1> IN IN OUT R251 1 2 200_5%_2 6 5 4 3 OUT OUT R252 1 R253 1 2 2 200_5%_2 200_5%_2 2 1 D260 EZJZ0V120JA_DY D259 EZJZ0V120JA_DY 2 G2 30 G1 G1 IN D262 2 D EZJZ0V120JA_DY D250 27 1 26 25 53< 24 2 EZJZ0V120JA_DY 37< SCAN_IN<1> IN 37< SCAN_IN<0> IN 23 53< 22 21 D251 20 1 19 2 EZJZ0V120JA_DY D252 18 17 1 16 15 2 EZJZ0V120JA_DY 14 53< 37< SCAN_IN<3> IN 53< 37< SCAN_IN<5> IN 13 12 11 C 10 1 9 D253 2 8 EZJZ0V120JA_DY D254 7 1 6 5 2 EZJZ0V120JA_DY 4 53< 3 37< SCAN_IN<6> IN 37< SCAN_IN<4> IN 2 1 53< CN251 D258 EZJZ0V120JA_DY 2 SCAN_IN<2> 1 1 1 1 G2 28 14 13 12 11 SCAN_OUT<7> SCAN_OUT<3> 31 37< 29 18 17 16 15 SCAN_OUT<10> 7 3 32 22 21 20 19 SCAN_OUT<11> SCAN_OUT<9> 53< 33 26 25 24 23 SCAN_OUT<13> _34P 34 30 29 28 27 SCAN_OUT<4> 13 15 1 0 CAPS_LED#_3 SCROLL_LED#_3 NUM_LED#_3 2 D255 1 2 2 EZJZ0V120JA_DY D256 1 2 EZJZ0V120JA_DY B 53< 37< SCAN_IN<7> B IN CN200 G1 P5V_S 14" TOUCH PAD G1 1 2 1 2 G2 OUT CN250 G1 1 2 3 4 5 G2 37< 1 D200 VARISTOR_DY 2 G A 53> G2 ENTERY_3703_Q02N_03R_2P 25mil PWR_SWIN#_3 6 1 2 3 4 5 6 BI BI IN TP_ON# IM_CLK_5 IM_DAT_5 37<> 37<> A 37> SW200 4 5 6 G ACES_88502_060N_6P 1 1 C250 2 CSC0402_DY C252 2 A B C D 1 2 3 OUT PWR_SWIN#_3 MISAKI_NTC017_DA1G_E160T_6P CSC0402_DY INVENTEC PUT ON BOTTOM SIDE EVEREST-M K/B & TP/B TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:43 2010 CODE CS SHEET CONN DOC.NUMBER CS_1310AXXXXXX-MTR 53 97 of 1 REV A01 8 7 6 5 4 3 2 1 BLUETOOTH D D P3V3_S P3V3_S 20MIL C2104 1 ALWAYS STUFF C2100 1 R2105 100K_5%_2 1 2 2 22UF_6.3V_5 2 0.1UF_16V_2 ACES_87213_0600N_6P BI BI BI OUT G2 C 1 2 3 4 5 6 32<> USB_P12_DP 32<> USB_P12_DN 55> 37> BTIFON# 32<> BTMDL# G 6 5 4 3 2 1 C G1 G CN2100 B B USB_P 1 2 GND USB_N 3 4 CH_CLK BTMDL 5 6 RST# VCC 7 8 CH_DATA# 9 10 GND DISABLE A A INVENTEC TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:02 2010 EVEREST-M BLUETOOTH CONN CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 54 97 of 1 REV A01 8 7 6 & Debug 4 3 card 2 WXMIT_OFF# 1 OUT 3 Q1300 D Wireless 5 1 IN WLON# 37> S G 2 SSM3K7002BFU D D P1V5_S 25mil 1 2 1 C1302 22uF_6.3V_5 2 1 C1306 2 0.1UF_16V_2 1 C1305 1 C1304 2 0.1UF_16V_2 0.1UF_16V_2 2 1 C1303 2 0.1UF_16V_2 C1301 22uF_6.3V_5 SUPPORT IAMT NEED +V3A P3V3_S 2.7A CN1300 30< C 54<> 37> BTIFON# OUT 1 R1301 PCIE_WAKE# 1 2 0_5%_2 2 CLKREQ_WLAN# OUT 0_5%_2 55< 3 D Q1301 G 43< CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP 20< 32<> BUF_PLT_RST# 56< CLK_PCI_DEBUG IN IN IN IN PCIE_WLAN_RX_DN PCIE_WLAN_RX_DP OUT OUT PCIE_WLAN_TX_DN PCIE_WLAN_TX_DP IN IN S 1 R1300 BI SSM3K7002FU_DY 2 CL_CLK 29> CL_DATA 29> CL_RST# PCI_3S_SERIRQ 29> B OUT OUT OUT IN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G1 WAKE# RESERVED RESERVED 3.3V GND 1.5V CLKREQ# RESERVED GND RESERVED REFCLK- RESERVED REFCLK+ RESERVED GND RESERVED RESERVED GND RESERVED RESERVED GND PERN0 PERP0 GND GND PERST# +3.3VAUX GND 1.5V SMB_CLK PETN0 SMB_DATA PETP0 GND GND USB_D- RESERVED USB_D+ RESERVED GND RESERVED LED_WWAN# RESERVED LED_WLAN# RESERVED LED_WPAN# RESERVED RESERVED RESERVED 1.5V GND 3.3V G G 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 C LPC_3S_FRAME# LPC_3S_AD<3> LPC_3S_AD<2> LPC_3S_AD<1> LPC_3S_AD<0> WXMIT_OFF# 55> BUF_PLT_RST# IN IN IN IN IN IN IN R1303 R1302 2 0_5%_2 2 0_5%_2 1 1 BI BI OUT 28> 28<> 28<> 28<> 28<> 32<> 56< 37<> 37<> 37<> 37<> 37<> 20< 43< 43< 43< 43< 43< 43< 55< PCH_3A_SMCLK 29<> PCH_3A_SMDATA 29<> BI BI USB_P5_DN USB_P5_DP 32<> 32<> WIMAX_LED# B G2 BELLW_80051_1021_52P Note: A MINI CARD 1 3.3V Peak(max)mA 2,750mA 1.5V 500mA Normal(max)mA 1,100mA A 375mA INVENTEC EVEREST-M TITLE MINI1 SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:43 2010 WLAN/DEBUG CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 55 97 of 1 CARD REV A01 8 7 6 5 4 3 2 3G/GPS 1 OUT 3G_OFF# 56< 3 D Q1401 D 3G_ON# 1 IN G D S 37> SSM3K7002BFU 2 P1V5_S P3V3_S 25mil 1A 1 C1400 0.1UF_16V_2 2 1 1 C1401 2 0.1UF_16V_2 2 1 C1402 22uF_6.3V_5 P3V3_S C1407 1 22uF_6.3V_5 2 1 C1406 0.1UF_16V_2 2 CLOSE TO SIM C1405 CONNECTOR 0.1UF_16V_2 2 C C U1402 CN1401 B 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G1 WAKE# RESERVED RESERVED 3.3V GND 1.5V CLKREQ# RESERVED GND RESERVED REFCLK- RESERVED REFCLK+ RESERVED GND RESERVED RESERVED GND RESERVED RESERVED GND PERN0 PERP0 GND GND PERST# +3.3VAUX GND 1.5V SMB_CLK PETN0 SMB_DATA PETP0 GND GND USB_D- RESERVED USB_D+ RESERVED GND RESERVED LED_WWAN# RESERVED LED_WLAN# RESERVED LED_WPAN# RESERVED RESERVED RESERVED 1.5V GND 3.3V G G 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 BI BI BI BI UIM_PWR 56<> UIM_DATA 56<> UIM_CLK 56<>56<> UIM_RST IN IN 3G_OFF# 56> BUF_PLT_RST# 1 VIO VIO 6 2 GND VBUS 5 3 VIO VIO 4 NXP_IP4223CZ6_SOT457_6P_DY 32<> 20< 43< 55< CN1400 56<> BI BI USB_P13_DN USB_P13_DP 32<> 32<> UIM_DATA BI P5 P6 P7 G2 GND VCC VPP RST I_O CLK P1 P2 P3 G G1 G UIM_PWR UIM_RST UIM_CLK BI BI BI 56<> 56<> 56<> B TAI_PMPAT5_06GLBS7N14_6P 1 2 1 C1403 4.7uF_6.3V_3 2 C1404 0.1UF_16V_2 G2 BELLW_80051_1021_52P A A MINI CARD 2 INVENTEC EVEREST-M MINI2 3G TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:03 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 56 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D HALL SENSOR P3V3_AL C C 15mil R52 100K_5%_2 U50 3 VDD 1 OUT 2 GND 1 MAG_MH248BESO_SOT23_3P 2 OUT LID_SW#_3 37< 1 1 L50 C50 VARISTOR_DY 2 1000PF_50V_2 2 B B A A INVENTEC EVEREST-M HALL SENSOR TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:03 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 57 97 of 1 REV A01 8 7 6 5 4 3 2 1 P5V_A D151 BAT_BLED1# 1 IN 2 1 2 220_5%_2 19_217_T1D_CP1Q2QY_3T 1 R153 C151 D P3V3_AL CSC0402_DY 2 D D155 P3V3_A 37> D154 37< SUS_OLED# 1 IN 2 1 R160 1 BAT_OLED# 1 IN 2 R154 2 150_5%_2 HT_191UY C150 C159 2 1 1 150_5%_2 HT_191UY 2 CSC0402_DY 2 CSC0402_DY Suspend BATTERY LED LED C C P3V3_S P5V_S D159 37> PWR_BLED# 1 IN 1 2 D156 R155 2 37> 220_5%_2 19_217_T1D_CP1Q2QY_3T 1 R150 WL_OLED# 1 IN 2 2 1 150_5%_2 HT_191UY C154 1 CSC0402_DY 2 C155 2 POWER LED CSC0402_DY Wireless & BT LED WIMAX LED P5V_S B B P5V_S 5 1 IN D150 + LED_3S_SATA# U150 4 1 2 1 P5V_S R151 2 2 TC7SZ08FU 19_217_T1D_CP1Q2QY_3T 1 1 220_5%_2 - 3 C149 C153 2 CSC0402_DY P5V_S HDD LED 5 49> LED_3IN1 1 IN U191 D153 + 2 0.1UF_16V_2 1 4 2 R156 1 2 2 - 220_5%_2 P5V_A 3 TC7SZ08FU 19_217_T1D_CP1Q2QY_3T 1 C156 D152 A 72<> 37> DCIN_BLED# 1 IN 2 1 2 A 2 CARD READER LED 220_5%_2 19_217_T1D_CP1Q2QY_3T 1 R152 CSC0402_DY C152 2 CSC0402_DY DC-IN INVENTEC LED EVEREST-M LED TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:44 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 58 97 of 1 REV A01 8 7 6 5 4 3 2 1 +V3S_CLK_VDD P3V3_S Layout D note: All decoupling 0.1uF disperse closed to pin D 15mil 1 L4001 2 FBM_11_160808_121T 1 C4006 2 1 1 C4005 2 10uF_6.3V_3 1 C4007 2 1 C4008 2 0.1UF_16V_2 2 0.1UF_16V_2 0.1UF_16V_2 1 C4009 C4010 2 0.1UF_16V_2 0.1UF_16V_2 P3V3_S 1 R4002 C U4000 CLKIN_BUF_DOT96_DP CLKIN_BUF_DOT96_DN R4013 R4012 OUT OUT 1 1 2 33_5%_2_DY 2 33_5%_2_DY CLK_BUF_DOT96_R_DP CLK_BUF_DOT96_R_DN P3V3_S 1 R4001 10K_5%_2 2 CLKIN_SATA1_DP CLKIN_SATA1_DN CLKIN_DMI_PCH_DP CLKIN_DMI_PCH_DN OUT OUT R4011 R4010 1 1 2 33_5%_2_DY 2 33_5%_2_DY OUT OUT R4009 R4008 1 1 2 33_5%_2_DY 2 33_5%_2_DY CLK_SATA1_R_DP CLK_SATA1_R_DN CLKIN_DMI_PCH_R_DP CLKIN_DMI_PCH_R_DN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND VDDDOT96MHz_3.3 SCLK_3.3 GNDDOT96MHz DOT96T_LPR SDATA_3.3 REF_3L-FSLC_3.3 DOT96C_LPR VDDREF_3.3 VDD_27MHz X1 27MHz_nonSS X2 27MHz_SS GND27MHz GNDREF CLKPWRGD-PD#_3.3 GNDSATA VDDCPU_3.3 SATAT_LPR CPUT0_LPR SATAC_LPR CPUC0_LPR GNDSRC GNDCPU SRCT1_LPR CPUT1_LPR SRCC1_LPR CPUC1_LPR VDDSRC_IO VDDCPU_IO CPU_STOP# VDDSRC_3.3 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C 10K_5%_2_DY 2 R4000 CLK_R3S_PCH14_R 1 2 BI BI OUT 33_5%_2_DY PCH_3S_SMCLK PCH_3S_SMDATA CLKIN_PCH14 X4000 CKG_X1 CKG_X2 1 R4007 1 2 0_5%_2 CLKOUT_DMI_CLKGEN_R_DP CLKOUT_DMI_CLKGEN_R_DN R4006 R4005 1 1 2 33_5%_2_DY 2 33_5%_2_DY CLK_BUF_CPYCLK_R_DP CLK_BUF_CPYCLK_R_DN R4017 R4016 1 1 R4015 R4014 CLKPWRGD_R IDT_ICS9LRS3197AKLFT_MLF_32P OUT CLKPWRGD 59> OUT OUT CLKOUT_DMI_CLKGEN_DP CLKOUT_DMI_CLKGEN_DN 1 2 0_5%_2_DY 2 0_5%_2_DY OUT OUT CLKIN_BUF_CPYCLK_DP CLKIN_BUF_CPYCLK_DN 2 1 2 0_5%_2_DY OUT 1 2 0_5%_2_DY 1 1 15mil 2 14.31818MHz Please +V1.05S_VCCP_VDD L4000 R4004 2 30PPM 1 C4004 C4003 2 33pF_50V_2 33pF_50V_2 CLK_XDP_CLKGEN_DP OUT CLK_XDP_CLKGEN_DN B P1V05_VCCPS 27< 29<> 26< 60< place close to CLKGEN within B 500mils 2 0_5%_2_DY P3V3_A FBM_11_160808_121T 1 C4002 2 1 1 C4000 2 10uF_6.3V_3 C4001 2 0.1UF_16V_2 CLOSE TO IC 0.1UF_16V_2 1 C4011 2 0.1UF_16V_2 PIN15,18 5 33> A ICC_EN# IN 2 U4001 + IN 4 OUT CLKPWRGD 59> A - MAIN_PWRGD 1 3 TC7SZ08FU 1 R4003 2 1K_5%_2_DY INVENTEC EVEREST-M CLOCK GENERATOR TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Tue Jan 2 04 00:18:17 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 59 97 of 1 REV A01 8 7 6 5 4 3 2 1 CN8000 20< 20> D H_PREQ# OUT H_PRDY# IN H_BPM0_XDP# H_BPM1_XDP# H_BPM2_XDP# H_BPM3_XDP# IN IN CFG<10> CFG<11> H_BPM4_XDP# H_BPM5_XDP# H_BPM6_XDP# H_BPM7_XDP# IN IN 25> 25> P1V05_VCCPS P3V3_S 1 R8013 1 R8012 2 0_5%_2_DY 2 0_5%_2_DY 10mil 27< 26< 59<> 29<> 60<> IN IN IN IN IN IN R8053 R8001 H_CPUPWRGD OUT XDP_PWRSW# OUT 60< 25> CFG<0> IN ALLSYS_PWROK OUT PCH_3S_SMDATA IN PCH_3S_SMCLK IN H_TCK1 OUT 20< 60<> H_TCK OUT 1 1 2 1K_5%_2_DY 2 0_5%_2_DY H_CPUPWRGD_XDP XDP_PWRSW#_R +V1.05S_VCC_OBS_AB R8014 1 Close R8052 1 Close 2 0_5%_2_DY to CPU 2 0_5%_2_DY to TCK_XDP CPU 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATD_A0 OBSDATA_C0 OBSDATD_A1 OBSDATA_C1 GND4 GND5 OBSDATD_A2 OBSDATA_C2 OBSDATD_A4 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD_HOOK0 ITPCLK_HOOK4 ITPCLK#_HOOK5 HOOK1 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#_HOOK6 HOOK3 DBR#_HOOK7 GND14 GND15 SDA TDO TRSTn SCL TCK1 TDI TCK0 TMS GND16 GND17 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 IN IN CFG<16> CFG<17> IN IN CFG<0> CFG<1> CFG<2> CFG<3> 60< 25> 25> 25< 25> 25> IN IN CFG<8> CFG<9> CFG<4> CFG<5> CFG<6> CFG<7> IN IN IN IN CLK_XDP_R_DN R8003 R8002 D 1 R8055 1 R8011 25> 25< 25> 25< 2 2 0_5%_2_DY 2 0_5%_2_DY IN IN CLK_XDP_DP CLK_XDP_DN 1 2 1K_5%_2_DY IN PLT_RST# 2 2 2 1 0_5%_2_DY 1 0_5%_2_DY 1 0_5%_2_DY XDP_DBRESET# P1V05_VCCPS P3V3_S 25> 25< 25> 25< 1 1 +V1.05S_VCCP_VCC_OBS_CD R8054 25> 25> 25> IN IN CLK_XDP_R_DP 25> 29> 2 1K_5%_2 32<> 68< 1 R8000 1 2 51_1%_2_DY 10K_5%_2_DY 1K_5%_2 R8056 2 10mil 37< 39< TDO_R TRST#_R TDI_R TMS_R R8050 R8049 R8048 Close to OUT H_TRST# OUT H_TDI 20< OUT H_TMS 60<> 20< 2 R8051 1 H_TDO IN 20> 60<> 0_5%_2_DY Close 20< CPU 2 SAMTEC_BSH_030_01_L_D_A_TR_60P R8009 1 0_5%_2_DY OUT SYS_RESET# to CPU 20> 30< C C XDP CONNECTOR SERIES B 60< 20> 20< 60> 60> 20< H_TDO H_TCK H_TCK1 60> H_TMS 60< TDO_R BI BI BI BI BI R8008 1 2 0_5%_2_DY R8007 1 R8006 1 2 0_5%_2_DY 2 0_5%_2 R8005 1 2 0_5%_2_DY R8004 1 2 0_5%_2_DY PCH_TDI PCH_TCK PCH_TCK PCH_TMS PCH_TDO BI BI BI BI BI B 61> 60> 28> 61> 28> +V1.05S 28> 61> 28> 61< 1 R8010 2 10K_5%_2_DY IN CLK_XDP_R_DP PCH ONLY 61> 60> 28> 60<> 60<> 60> 60<> 60> A 60> TCK_XDP TDO_R TRST#_R TDI_R TMS_R IN IN IN IN IN R8047 1 R8046 1 2 0_5%_2_DY 2 0_5%_2 R8045 1 R8044 1 2 0_5%_2 2 0_5%_2 R8043 1 2 0_5%_2 OUT OUT OUT OUT OUT 28> PCH_TCK 60<> PCH_TDO PCH_TRST# 28> PCH_TDI 60<> PCH_TMS 28> Close 61> 61> 61> 60<> H_CPUPWRGD_XDP IN R8015 1 to CPU A 2 0_5%_2_DY OUT MAIN_PWRGD 18> 14< 37< 59< 61> INVENTEC EVEREST-M XDP TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:45 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 60 97 of 1 REV A01 8 7 6 5 4 3 2 1 +V3M +V3M 15MIL 1 1 +V3M R8037 10K_5%_2 R8040 2.37K_1%_2 2 2 1 D 1 C8003 2 0.1UF_16V_2 1 1 R8039 806_1%_2 R8034 10K_5%_2_DY 2 1 C8004 1 R8035 10K_5%_2 1 R8042 301_1%_2 R8036 10K_5%_2_DY 2 0.1UF_16V_2 2 D 2 1 2 1 R8033 10K_5%_2 2 R8032 10K_5%_2_DY OUT PCH_TCK_R 2 2 1 R8041 U8001 60<> 28> PCH_TDI 60> 28> PCH_TCK 60> 60<> 60<> 28> PCH_TMS 60> PCH_TRST# C 1 DIR 619_1%_2 VCC 14 OUT R8027 1 2 0_5%_2_DY PCH_TDI_R 2 A0 B0 13 OUT ME_TDI OUT R8026 1 2 0_5%_2_DY PCH_TCK_R 3 A1 B1 12 OUT ME_TCK 61< 4 GTLREF GND2 2 61< 11 OUT R8025 1 2 0_5%_2_DY PCH_TMS_R 5 A2 B2 10 OUT ME_TMS 61< OUT R8024 1 2 0_5%_2_DY PCH_TRST#_R 6 A3 B3 9 OUT ME_TRST# 7 GND1 GND3 8 61< C PHP_GTL2005_TSSOP_14P 1 1 R8030 10K_5%_2_DY 2 R8028 10K_5%_2_DY 2 1 1 R8031 10K_5%_2 +V3M 2 +V3M 1 1 B R8029 10K_5%_2 2 B R8022 R8038 3.24K_1%_2 10K_5%_2_DY 2 2 1 1 15MIL JACK8000 1 R8021 1K_5%_2 C8002 2 0.1UF_16V_2 2 1 R8023 10K_5%_2 61> ME_TCK 61> ME_TMS 61> ME_TDI 61> ME_TDO 61> ME_TRST# C8001 1 2 0.1UF_16V_2 2 R8016 10K_5%_2 IN IN IN IN IN 1 2 3 4 5 6 1 2 3 4 2 5 G1 6 G2 G1 G2 MLX_85510_5019_6P U8000 60<> 60> 28> PCH_TDO IN A 1 DIR 2 A0 3 A1 4 GTLREF 5 VCC 14 B0 13 12 B1 GND2 11 B2 10 A2 1 R8017 2 OUT ME_TDO 61< 22_5%_2 C8000 1 A 2 220PF_50V_2 6 1 1 R8020 1K_5%_2 2 1 R8019 1K_5%_2 2 7 R8018 1K_5%_2 B3 9 GND3 8 A3 GND1 PHP_GTL2005_TSSOP_14P 2 INVENTEC EVEREST-M ME JTAG TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:46 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 61 97 of 1 REV A01 8 7 6 5 4 PICK (FOR - TOUCHPAD MODULE, 3 2 1 BUTTON BOARD TOUCHPAD SWITCH BOARD, FINGERPRINT MODULE) D D CONNECT TO TOUCHPAD MODULE CONNECT TO MAINBOARD'S +TP_5S TP CONNECTOR +TP_5S CN9021 62<> 62<> TP_IM_CLK_5 TP_IM_DAT_5 LEFT_TP RIGHT_TP 62> BI BI IN IN 1 2 3 4 5 6 G1 G1 CN9022 1 6 5 4 3 2 1 2 62<> 62<> 3 4 5 6 G2 TP_IM_CLK_5 TP_IM_DAT_5 DB_TP_ON# G2 BI BI 62> IN G2 G2 G1 G1 6 5 4 3 2 1 ACES_88766_060N_6P ACES_88766_060N_6P C C GND_TP GND_TP CONNECT TO TOUCHPAD SWITCH BOARD CN9020 62< DB_TP_ON# OUT 1 2 G1 SW9021 2 G2 B G1 1 4 5 6 G2 ENTERY_3703_Q02N_03R_2P A B C D 1 2 3 OUT RIGHT_TP 62< B MISAKI_NTC017_DA1G_E160T_6P SW9020 GND_TP A B C D 1 2 3 OUT FIX_MASK 1 FIX9301 FIX_MASK 1 FIX9302 FIX_MASK FIX9303 1 1 FIX_MASK D9041 S9020 SCREW300_800_1P PHP_PESD5V2S2UT_SOT23_3P FIX9304 GND_TP 1 FIX_MASK 1 S9021 SCREW220_800_1P FIX9904 62< 3 FIX9300 1 2 MISAKI_NTC017_DA1G_E160T_6P LEFT_TP 1 4 5 6 GND_TP 1 FIX_MASK A A GND_TP INVENTEC EVEREST-M PICK BUTTON BOARD TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:03 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 62 97 of 1 REV A01 8 7 6 D 5 4 3 2 1 TOUCHPAD SWITCH BOARD R9040 SW9040 C A B C D 1 2 3 2 PAD9041 1 1 SMDPAD_1P_40X120 33_5%_2 C D9040 MISAKI_NTC017_DA1G_E160T_6P 1 4 5 6 D 2 C9040 3 1 0.01UF_50V_2 2 PHP_PESD5V2S2UT_SOT23_3P_DY PAD9040 1 GND_PB SMDPAD_1P_40X120 GND_PB GND_PB B B 1 FIX9040 FIX_MASK FIX9041 1 FIX_MASK FIX9042 FIX9043 1 1 FIX_MASK 1 S9040 SCREW230_700_1P FIX_MASK S9041 1 SCREW230_700_1P GND_PB A A INVENTEC EVEREST-M TOUCH PAD SW BOARD TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:46 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 63 97 of 1 REV A01 8 7 6 5 4 3 2 1 POWER BUTTON D D SW9000 1 G1 2 3 G2 4 PAD9000 1 1 FOX_1BT002_0021L_4P SMDPAD_1P_40X120 C9000 C C 1000PF_50V_2 1 2 2 PAD9001 1 SMDPAD_1P_40X120 D9000 PHP_PESD5V2S2UT_SOT23_3P_DY 3 GND_BTN GND_BTN GND_BTN B B S9001 S9000 FIX9000 FIX9001 1 1 FIX_MASK 1 FIX_MASK FIX_MASK 1 FIX_MASK SCREW540_700_NP_1P 1 SCREW540_700_NP_1P 1 FIX9002 FIX9003 FIX9004 1 FIX_MASK FIX9005 1 FIX_MASK GND_BTN A A INVENTEC EVEREST-M POWER BUTTON BOARD TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:46 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 64 97 of 1 REV A01 7 6 5 4 +V5A_DB PAD9150 1 CARD READER & USB BOARD 1 L9100 1 1 1 2 2 USB 2 +USB_VCC1 U9150 BLM18PG600SN1D 1 +V5A_DB 1 C9114 C9113 65< 2 D 2 10UF_6.3V_3 0.1UF_16V_2 GND_CARD IN SB_USB_1_DB 1 2 3 4 GND OUT IN OUT IN OUT EN OC# 8 7 6 5 1 2 65< IN SB_USB_1_DB 65<> IN USB_DB_P1_DP 65<> USB_DB_P1_DN IN 65<> USB_DB_P2_DP IN IN USB_DB_P2_DN 65<> 65< USB_DB_3IN1_DP IN IN 65< USB_DB_3IN1_DN 65> OUT USB_OC#_1_DB 65< OUT LED_3IN1_DB C 1 C9152 330UF_6.3V 2 0.1UF_16V_2 C9151 2 0.1UF_16V_2 2 D OUT GND_CARD USB_OC#_1_DB 3 +USB_VCC1 GND_CARD 4 65<> 6 USB_DB_P1_L_DN BI 65<> USB_DB_P1_L_DP 7 8 9 65< 10 4 1 BI BI USB_DB_P1_DP 65< 11 USB_DB_P1_DN L9151 3 2 BI USB_DB_P1_L_DN BI BI XTIL0 65< 14 65< 15 16 G1 17 G2 G1 G2 4 1 BI USB_DB_P2_DN BI USB_DB_P2_DP 65< +VBUS USB_DB_P1_L_DP L9150 3 2 BI 1 GND_CARD R9101 0_5%_2 2 1 C9102 2 47PF_50V_2_DY 2 270K_5%_2 BI GND_CARD 1 C9100 1 C9101 2 20PF_50V_2 2 20PF_50V_2 65<> +USB_VCC1 USB_DB_P2_L_DN BI 65<> USB_DB_P2_L_DP 1 C9104 1 C9108 0.1UF_16V_2 65> XTIL0 IN 65> XTIL1 IN 1 R9103 1 2 3 4 5 6 7 8 9 10 11 12 2 6.2K_1%_2 2 1UF_6.3V_2 2 65< 65< USB_DB_3IN1_DN USB_DB_3IN1_DP IN IN GND_CARD GND_CARD 65< 1 C9103 2 1UF_6.3V_2 BI C9109 +VBUS +CARD_3V3 1 C9111 OUT SD_D2 65> OUT SD_D3 65> 2 0.1UF_16V_2 GND_CARD 1 C9110 2 0.1UF_16V_2 G D+ G G G G1 G2 G3 G4 C RREF SP12 NC SP11 DM D3V3 GND GND SP10 U9100 NC NC 3V3_IN SP9 CARD_3V3 SP8 VREG SP7 D3V3 SP6 GND 36 35 34 33 32 31 30 29 28 27 26 25 SD_CMD DP GND_CARD 65> LED_3IN1_DB GND_CARD CN9101 1 C9106 1 C9105 2 2.2UF_6.3V_2 2 1UF_6.3V_2 SP5 BI 1 R9151 65<> SD_CMD 2 BI 65<> GND_CARD SD_CLK_MS_CLK 0_5%_2 BI MS_D3 1 C9107 2 1UF_6.3V_2 17 4 2 9 16 CLOSE TO CN BI SD_D1 65<> SD_D0_MS_D0 SD_CLK_MS_CLK BI 65<> SD_D2 BI BI OUT 65<> MS_INS# MS_D2 65<> BI SD_D0_MS_D0 65<> BI MS_D1 65<> MS_BS 65<> BI BI BI SD-VSS MS-VCC MS-VSS MS-DATA1 SD-VSS MS-DATA0 MS-VSS MS-DATA2 SD-WP MS-DATA3 SD-DAT1 MS-SCLK SD-DAT0 SD-CLK GND SD-DAT3 GND 65<> BI MS_BS BI SD_D0_MS_D0 BI 65<> 65<> BI MS_D2 65<> 65<> MS_INS# MS_D3 65<> BI 65<> SD_CLK_MS_CLK BI SD_CD# BI BI 20 G1 G2 SD-CD SD-CMD B 15 13 12 10 8 7 5 MS-BS MS-INS 22 19 18 14 6 3 1 21 11 BI SD_WP 65<> SD_CMD 65> SD_D3 OUT 65> MS_D1 65<> SD-DAT2 SD-CD-WP SD-VDD TAIT_R009_040_LM_22P +VBUS GND_CARD S9101 IN SD_D1 BI BI SD_CD# 65<> FIX9100 FIX9101 FIX9102 FIX9103 FIX9104 FIX9105 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 1 1 1 1 1 1 SD_WP SCREW300_900_1P 0.1UF_16V_2 S9102 GND_CARD R9151 1 A R9152 65<> BI GND_CARD GND_CARD 1 C9112 SCREW480_800_700_1P 2 1UF_6.3V_2 G D- +CARD_3V3 REA_RTS5159_VDD_GR_LQFP_48P 13 14 15 16 17 18 19 20 21 22 23 24 2 A VCC GND_CARD 1 1 IN VREG AV_PLL MS_D5 SP4 MS_D4 SP3 SP2 SP1 EEDI EESK EECS EEDO GPIO0 XTAL_CTR +VBUS CN9152 1 2 3 4 GND_CARD IN GND_CARD G SYN_020133GR004M52CZL_4P SP13 SP14 SP15 SP16 SP17 SP18 SP19 RST# MODE_SEL GND XTL0 XTLI 65< VREG G G GND_CARD 65<> USB_DB_P2_L_DP WCM_2012_900T 48 47 46 45 44 43 42 41 40 39 38 37 B D+ G1 G2 G3 G4 65<> 65<> USB_DB_P2_L_DN 1 GND_CARD R9100 G SYN_020133GR004M52CZL_4P 65<> 18 2 12MHZ G D- 13 1 X9100 1 VCC WCM_2012_900T 12 GND_CARD OUT CN9151 1 2 3 4 5 2 XTIL1 65> GND_CARD R9102 100K_5%_2 OUT R9150 RSC_0402_DY GND_CARD 1 2 ACES_50503_0184N_001_18P 65< 1 C9153 GMT_G547G1P81U_MSOP_8P 1 CN9100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 C9154 0.01UF_50V_2 C9150 22UF_6.3V_5_DY +VBUS 2 2 +V5A_DB_USB_IN 2 POWERPAD_2_0610 +V3S_CARD +V3S_CARD 3 + 8 GND_CARD CLOSE TO RTS5159 GND_CARD 65<> INVENTEC EVEREST-M TITLE CARDREADER & USB BOARD SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:47 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 65 97 of 1 REV A01 8 7 6 5 4 3 2 1 D D EMI P1V5 C7507 C7511 C 1 2 0.1UF_16V_2 C7510 1 C7509 0.1UF_16V_2 1 2 C7508 0.1UF_16V_2 1 2 2 0.1UF_16V_2 1 C 2 0.1UF_16V_2 1 2 0.1UF_16V_2 C7501 C7504 0.1UF_16V_2 1 C7502 2 C7505 0.1UF_16V_2 1 C7503 2 C7506 2 0.1UF_16V_2 1 1 2 0.1UF_16V_2 1 2 0.1UF_16V_2 C7500 1 2 0.1UF_16V_2 B B A A INVENTEC EVEREST-M EMI TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:04 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 66 97 of 1 REV A01 6 P5V_S 8 7 6 5 1 0_5%_2 G + P3V3_S C S 2 3 1 3 2 1 B0 VDD B1 VDD B2 VDD B3 VDD B4 VDD SSM3K7002BFU D 67< 33<> 1 DGPU_PWROK IN G Q7403 3 S 16> G 2 D 1 IN 1 DGPU_PWROK# IN SSM3K7002BFU G 2 S SSM3K7002BFU SSM3K7002BFU DGPU_PWROK# OUT DGPU_PWROK_5R OUT 2 VDD 38 37 36 35 29 28 27 26 IN IN IN IN IN IN IN IN PCH_LVDS_TXDL0_DN PCH_LVDS_TXDL0_DP PCH_LVDS_TXDL1_DN PCH_LVDS_TXDL1_DP PCH_LVDS_TXDL2_DN PCH_LVDS_TXDL2_DP PCH_LVDS_TXCL_DN PCH_LVDS_TXCL_DP 2.5A P3V3_S P3V3_GPUS C B5 B6 Q7407 B7 P5V_S 4 S 3 G 1 2 5 6 D 1 C2 A4 C3 A5 C4 A6 C5 A7 C6 C7400 B GND GND GND 3 D R7400 1 1 G 200_5%_3 S 3 Q7401 SSM3K7002BFU 1 EC_DGPU_PWR_EN# IN G SSM3K7002BFU 1 Q7410 67< 1 EC_DGPU_PWR_EN# IN B G SSM3K7002BFU 2 2 TML 2 330PF_50V_2 100K_5%_2 S GND 10K_5%_2 1 2 2 GND Q7402 2 D GND 1 4 10 14 17 19 21 41 39 43 C7401 R7411 1 S GND AM3423P 750K_1%_2 2 R7403 GND CSC0402_DY P3V3_S C7 GND PMOS_4D1S R7404 3 A3 SW_LVDS_TXDL0_DN SW_LVDS_TXDL0_DP SW_LVDS_TXDL1_DN SW_LVDS_TXDL1_DP SW_LVDS_TXDL2_DN SW_LVDS_TXDL2_DP SW_LVDS_TXCL_DN SW_LVDS_TXCL_DP D C1 OUT OUT OUT OUT OUT OUT OUT OUT 2 A2 2 GPU_LVDS1_TXDL0_DN GPU_LVDS1_TXDL0_DP GPU_LVDS1_TXDL1_DN GPU_LVDS1_TXDL1_DP GPU_LVDS1_TXDL2_DN GPU_LVDS1_TXDL2_DP GPU_LVDS1_TXCL_DN GPU_LVDS1_TXCL_DP A1 C0 2 3 6 7 11 12 15 16 1 A0 34 33 32 31 25 24 23 22 IN IN IN IN IN IN IN IN 200_5%_2 2 VDD DGPU_PWROK# 5 8 13 18 20 30 40 42 1 VDD R7406 G 2 2 U3005 1 1 C7405 Q7408 20mil 1 Q7400 680PF_50V_2 P1V8_S C7402 0.1UF_25V_2 2 220K_5%_2 HI: B2 LOW: B1 D 1 200_5%_2 1 G NMOS_4D3S Q7405 10K_5%_2 IN 1 1 2 3 4 S AM4430N R7412 R7413 DGPU_PWROK_5R 750K_1%_2 D R7402 330uF_2V_15mR_Pana_-35% 2 8 7 6 5 2 AM4430N R7414 10K_5%_2_DY S NMOS_4D3S G SSM3K7002BFU 67< 1 2 3 4 2 1 C7404 Q7404 2 R7407 D D Q7406 DGPU_PWROK IN P1V05_GPUS Q7409 OUT CLKREQ_GPU_PEG# 3 D 3.55A P1V05_VCCPS 2 P1V5_GPUS P1V5 D R7408 1 1 10.72A OUT CLKREQ_GPU_PEG#_MOS 0_5%_2 10K_5%_2 2 S R7405 3 D 1 R74012 4 S 1 2 P3V3_A 5 3 7 2 8 9 DGPU_SELECT IN SEL PER_PI2PCIE2412ZHE_TQFN_42P EC_DGPU_PWR_EN IN P3V3_S 1 C7403 67< NC 1 5 2 0.1UF_16V_2 U3004 + DGPU_SELECT# IN 2 4 - OUT DGPU_SELECT P5V_S DURING U3002 32< 32> DGPU_SELECT# IN GPU_LVDS_DDCCLK IN PCH_LVDS_DDCCLK IN SW_LVDS_DDCCLK OUT GPU_LVDS_DDCDATA IN PCH_LVDS_DDCDATA IN SW_LVDS_DDCDATA OUT TC7SH14F 1 2 3 4 5 6 7 8 S VCC OE 1B1 1B2 4B1 1A 4B2 2B1 4A 2B2 3B1 2A 3B2 GND 3A 16 15 14 13 12 11 10 9 IN IN OUT IN IN OUT GPU_LCM_BKLTEN PCH_LCM_BKLTEN 44< SW_LCM_BKLTEN GPU_LCM_VDDEN PCH_LCM_VDDEN 44< SW_LCM_VDDEN DGPU_PRSNT# IN DGPU_PWR_EN# 0 : 1 : ADDIN ADDIN 0 : DGPU POWER SWITCH 1 : POWER SWITCH 0 : DGPU POWER IS NOT STABLE. 1 : DGPU POWER IS STABLE LOW LOW 0 : 1 : KEEP DGPU IN RESET RESET IS RELEASED HIGH HIGH 0 : 1 : DISPLAY DISPLAY 0 : 1 : PWM SIGNAL PWM SIGNAL HIGH HIGH DGPU_PWROK DGPU_HOLD_RST# 1 2 10K_5%_2_DY 1 2 10K_5%_2 P5V_S DGPU_SELECT# U3003 P3V3_S R7409 AFTER RESET PHP_CBT3257DS_QSOP_16P 20mil R7410 RESET DGPU_PRSNT# 3 A 20mil HI: B2 LOW: B1 IN EC_LCM_INVPWM 1 R3021 2 0_5%_2_DY IN GPU_LCM_INVPWM 1 R3020 DGPU_PWM_SELECT# PCH_LCM_INVPWM SW_LCM_INVPWM 2 0_5%_2 31> 48< IN IN OUT 1 2 3 4 5 6 7 8 S 1B1 VCC OE 1B2 4B1 1A 4B2 2B1 4A 2B2 3B1 2A 3B2 GND 3A 16 15 14 13 12 11 10 9 DGPU_PWM_SELECT# 6 5 4 A FROM EC FROM PCH INVENTEC SIZE C CHANGE 7 TURNED ON TURNED OFF SWITCH ENABLED FOR DGPU SWITCH ENABLED FOR IGPU EVEREST-M GPU SW / POWER TITLE PHP_CBT3257DS_QSOP_16P 8 CARD PRESENT CARD NOT PLUGGED IN 3 by Frank Hu DATE Fri Dec 2 31 10:16:48 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 67 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_GPUS P1V05_GPUS 1 2 PEX_IOVDDQ_11 PEX_IOVDDQ_12 1 C5018 C5017 1 1 2 2 0.1uF_6.3V_1 0.1uF_6.3V_1 NC_23 AL23 AM23 PEX_TX6 NC_25 PEX_TX6* NC_26 PEG_RX7_C_DP PEG_RX7_C_DN PEG_RX8_C_DP PEG_RX8_C_DN PEG_RX9_C_DP PEG_RX9_C_DN PEG_TX12_DP PEG_TX12_DN IN IN PEG_RX13_DP PEG_RX13_DN PEG_TX13_DP PEG_TX13_DN PEG_RX14_DP PEG_RX14_DN OUT OUT OUT OUT PEG_TX14_DP PEG_TX14_DN IN IN C5012 C5011 C5010 C5009 1 1 1 1 2 2 1 1 2 2 2 2 2 2 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 PEG_RX10_C_DP PEG_RX10_C_DN PEG_RX11_C_DP PEG_RX11_C_DN PEG_RX12_C_DP PEG_RX12_C_DN PEG_RX13_C_DP PEG_RX13_C_DN IN IN OUT OUT PEX_RX6 VDD33_1 PEX_RX6* VDD33_2 AM24 AM25 PEX_TX7 VDD33_4 PEX_TX7* VDD33_5 AN25 AP25 PEX_RX7 AL25 AK25 PEX_TX8 AR25 AR26 PEX_RX8 AL26 AM26 PEX_TX9 VDD_SENSE_2 PEX_TX9* VDD_SENSE_3 C5008 C5007 C5006 C5005 1 1 1 1 2 2 2 2 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 0.1uF_6.3V_1 IN IN PEG_RX14_C_DP PEG_RX14_C_DN PEG_RX15_C_DP PEG_RX15_C_DN VDD33_3 1 2 2 2 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 1 2 2 10K_5%_2 B1 XTAL_IN XTAL_OUTBUFF D1 XTAL_OUT B2 NVIDIA_N12P_GS_BGA_973P XTAL27_OUT XTAL27_IN X5000 P3V3_GPUS 1 2 27MHz 15mil J10 J11 J12 J13 J9 R5073 C5068 C5069 10K_5%_2 18PF_50V_2 18PF_50V_2 C5153 C5150 C5146 C5134 C5001 0.1uF_16V_2 0.1uF_16V_2 1uF_6.3V_2 4.7uF_6.3V_3 0.1uF_16V_2 PEX_RX7* C PEX_TX8* CLK_GPU_27M IN PEX_RX8* VDD_SENSE_1 PEX_RX9 GND_SENSE_1 PEX_RX9* GND_SENSE_3 GND_SENSE_2 AM27 AM28 PEX_TX10 AN28 AP28 PEX_RX10 AL28 AK28 PEX_TX11 AR28 AR29 PEX_RX11 AK29 AL29 PEX_TX12 AP29 AN29 PEX_RX12 AM29 AM30 PEX_TX13 AN31 AP31 PEX_RX13 AM31 AM32 PEX_TX14 AR31 AR32 PEX_RX14 D35 P7 AD20 AD19 R7 E35 +GPU_NVVDD_L_R R5026 GND_SENSE_R PEX_TX10* 1 R5027 2 1 0_5%_2 2 OUT +GPU_NVVDD_L 15mil 100_1%_2 CLOSE TO POWER IC P1V05_GPUS PEX_RX10* PEX_TX11* PEX_PLLVDD AG14 15mil +GPU_V1.05S_PEX_PLLVDD PEX_RX11* C5003 1uF_6.3V_2 PEX_TX12* L5009 1 C5002 C5004 1uF_6.3V_2 0.1UF_16V_2 C5145 1uF_6.3V_2 2 HK1005R10J_T_200mA C5142 C5139 4.7uF_6.3V_3 4.7uF_6.3V_3 B 2 OUT OUT AP23 AN23 R5003 0_5%_2_DY XTAL_SSIN 1 PEG_RX12_DP PEG_RX12_DN C5014 C5013 1 1 NC_24 1 R5074 D2 1 PEX_RX5* 0.1UF_16V_2 2 NC_22 NC_21 D C5136 C5138 1 NC_20 PEX_RX5 SP_PLLVDD 2 PEX_TX5* AR22 AR23 XTAL_PLL VID_PLLVDD 1 NC_19 NC_18 14/16 PLLVDD 2 NC_17 PEX_TX5 +GPU_V1.05S_SP_PLLVDD 1 NC_16 PEX_RX4* 10mil 2 PEX_RX4 AP26 AN26 C5016 C5015 NC_15 PEG_RX5_C_DP AL22 PEG_RX5_C_DN AK22 IN IN OUT OUT NC_14 AN22 AP22 IN IN OUT OUT NC_13 PEX_TX4* 2 0.1UF_16V_2 1 0.1uF_6.3V_1 0.1uF_6.3V_1 NC_12 PEX_TX4 L5006 KC_HLM_160808_R10J 2 2 2 NC_9 U5000 AE9 AD9 AF9 1 NC_11 0.1UF_16V_2 2 NC_8 PEX_RX3* NC_7 C5063 C5135 0.1UF_16V_2 4700PF_50V_2 10UF_6.3V_3 1 1 21> 21> 1 1 NC_6 C5137 C5157 C5158 4.7uF_6.3V_3 2 C5020 C5019 NC_5 NC_3 NC_10 IN IN OUT OUT NC_4 PEX_RX2* 4.7UF_6.3V_3 2 0.1uF_6.3V_1 0.1uF_6.3V_1 NC_2 PEX_RX2 +GPU_V1.05S_PLLVDD 1 2 2 PEX_TX2* AR19 AR20 C5149 0.1UF_16V_2 A2 A7 AA4 AB4 AB7 AC5 AD6 AF6 AG6 AJ5 AK15 AL7 B7 C7 D5 D6 D7 E5 E7 F4 G5 H32 P6 U7 V6 Y4 10mil 2 2 1 1 NC_1 L5007 1 C5022 C5021 PEX_TX2 1 KC_HLM_160808_R10J PEX_RX1* PEX_TX3* IN IN OUT OUT AL19 AK19 2 0_5%_2_DY C5154 PEX_RX1 PEX_TX3 PEG_RX6_C_DP PEG_RX6_C_DN 2 0.1uF_6.3V_1 0.1uF_6.3V_1 E 2 2 2 1 1 1 1 2 C5024 C5023 OUT OUT 22UF_6.3V_5 2 21> 21> 0.1uF_6.3V_1 0.1uF_6.3V_1 15mil AG19 F7 PEX_SVDD_3V3 PEX_RX3 IN IN IN PEG_TX10_DP IN PEG_TX10_DN OUT PEG_RX11_DP PEG_RX11_DN OUT IN PEG_TX11_DP IN PEG_TX11_DN PEG_RX15_DP PEG_RX15_DN PEG_TX15_DP PEG_TX15_DN 2 2 GT21X AN19 AP19 AM21 AM22 1 OUT OUT 1 1 PEX_SVDD_3V3_NC GF108 AP20 AN20 IN IN C5026 C5025 PEX_SVDD_3V3 PEX_TX1* PEG_RX3_C_DP AL20 PEG_RX3_C_DN AM20 PEG_RX4_C_DP PEG_RX4_C_DN 0.1uF_16V_2 P1V05_GPUS 1 21< 21< 0.1uF_6.3V_1 0.1uF_6.3V_1 C5064 4.7uF_6.3V_3 2 21> 21> 2 2 C5159 10uF_6.3V_3 1 21< 21< 1 1 PEX_TX1 P1V05_GPUS 2 21> 21> C5028 C5027 OUT OUT C5132 R5002 1 21< 21< 0.1uF_6.3V_1 0.1uF_6.3V_1 AM18 AM19 P3V3_GPUS PEX_RX0* 2 21> 21> 2 2 PEX_RX0 2 B 21< 21< 1 1 AP17 AN17 PEX_IOVDDQ_25 C5140 PEX_TX0* 1 21> 21> C5030 C5029 PEX_TX0 1 21< 21< IN IN PEX_IOVDDQ_24 AL17 AM17 PEX_IOVDDQ_22 2 21< 21< PEG_RX9_DP PEG_RX9_DN PEG_TX9_DP PEG_TX9_DN PEG_RX10_DP PEG_RX10_DN PEG_RX2_C_DP PEG_RX2_C_DN PEX_IOVDDQ_23 PEX_REFCLK* 1 21< 21< 0.1uF_6.3V_1 0.1uF_6.3V_1 2 2 PEX_REFCLK 2 PEG_TX8_DP PEG_TX8_DN 1 1 AR16 AR17 1 PEG_TX7_DP PEG_TX7_DN PEG_RX8_DP 21< PEG_RX8_DN 21< C IN IN IN IN PEG_TX6_DP PEG_TX6_DN PEG_RX7_DP PEG_RX7_DN PEG_RX1_C_DP PEG_RX1_C_DN PEX_IOVDDQ_21 1uF_6.3V_2 2 PEG_TX5_DP PEG_TX5_DN PEG_RX6_DP 21< PEG_RX6_DN 21< 0.1uF_6.3V_1 0.1uF_6.3V_1 2 2 PEX_IOVDDQ_20 PEX_TSTCLK_OUT* 1uF_6.3V_2 0.1uF_16V_2 0.1uF_16V_2 C5143 C5147 C5151 2 PEG_TX4_DP PEG_TX4_DN PEG_RX5_DP PEG_RX5_DN 1 1 PEX_TSTCLK_OUT 0.1UF_16V_2_DY 2 PEG_RX4_DP PEG_RX4_DN IN IN OUT OUT PEG_TX3_DP PEG_TX3_DN PEG_RX0_C_DP PEG_RX0_C_DN AJ17 AJ18 C5155 2 PEG_RX3_DP PEG_RX3_DN D 21> 21> BI BI 0.1uF_6.3V_1 0.1uF_6.3V_1 2 2 200_1%_2 C5042 1UF_6.3V_2_DY 20mil 1 PEG_TX2_DP PEG_TX2_DN 1 1 1 PEX_IOVDDQ_19 C5043 1 PEX_IOVDDQ_16 C5044 1UF_6.3V_2_DY 1 PEX_IOVDDQ_15 C5045 P1V05_GPUS AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 2 CLK_PEG_GPU_REF_DP CLK_PEG_GPU_REF_DN C5032 C5031 22UF_6.3V_5 4.7UF_6.3V_3_DY 1 PEX_IOVDDQ_14 10UF_6.3V_3_DY 1 2 R5076 OUT OUT 0.1uF_16V_2 1 G PEX_IOVDDQ_13 SSM3K7002BFU E PEG_TX1_DP PEG_TX1_DN PEG_RX2_DP 21< PEG_RX2_DN 21< C5065 1 PEX_CLKREQ* PEX_IOVDDQ_18 21> 21> C5000 10uF_6.3V_3 2 AR13 PEX_IOVDDQ_17 C5034 C5033 C5133 4.7uF_6.3V_3 1 PEX_IOVDDQ_10 Q5001 OUT OUT C5141 1uF_6.3V_2 2 PEX_IOVDDQ_9 PEX_RST* C5046 C5047 22UF_6.3V_5_DY 2 1 D OUT 2 AM16 AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 2 PEX_IOVDDQ_4 PEX_IOVDDQ_5 S 3 P3V3_GPUS 21> 21> C5144 1uF_6.3V_2 2 PEX_IOVDDQ_3 PEX_IOVDDQ_8 C5036 C5035 C5148 2 5 + - 3 PEX_IOVDDQ_2 100K_5%_2 PEX_IOVDDQ_7 OUT OUT 0.1uF_16V_2 2 PEX_IOVDDQ_1 PEX_IOVDDQ_6 PEG_RX0_DP PEG_RX0_DN PEG_TX0_DP PEG_TX0_DN PEG_RX1_DP 21< PEG_RX1_DN 21< 1 R5000 TC7SZ08FU CLKREQ_GPU_PEG#_MOS C5152 0.1uF_16V_2 2 4 C5156 2 2 1 IN PEX_IOVDD_5 2 EC_PEG_RST# PEX_IOVDD_4 1 PEX_IOVDD_3 2 1 2 PLT_RST# IN 1 PEX_IOVDD_2 U5001 1 PEX_IOVDD_1 PCI_EXPRESS AK16 AK17 AK21 AK24 AK27 1 1/16 0.1uF_16V_2 60< 39< 32<> 37< F 20mil U5000 2 C5039 1 F PEX_RX12* PEX_TX13* PEX_RX13* PEX_TX14* GT21X RFU GF108 PEX_PLL_HVDD_NC PEX_TERMP AN32 AP32 PEX_TX15 AR34 AP34 PEX_RX15 AG20 R5075 PEX_RX14* AG21 1 2 2.49K_1%_2 PEX_TX15* TESTMODE PEX_RX15* NVIDIA_N12P_GS_BGA_973P AP35 1 R5017 2 10K_5%_2 A A INVENTEC TITLE SIZE C CHANGE by 8 7 6 5 4 3 Frank Hu DATE Fri Dec 31 10:16:49 2 2010 EVEREST GPU-1 CODE ES SHEET DOC.NUMBER REV CS_1310AXXXXXX-MTR 68 of 1 A01 97 8 7 6 5 4 3 2 1 P1V5_GPUS FBVDDQ_11 FBA_D10 FBVDDQ_12 FBA_D11 FBVDDQ_13 FBA_D12 FBVDDQ_14 FBA_D13 FBVDDQ_15 FBA_D14 FBVDDQ_16 FBA_D15 FBVDDQ_17 FBA_D16 FBVDDQ_18 FBA_D17 FBVDDQ_19 FBA_D18 FBVDDQ_20 FBA_D19 FBVDDQ_21 FBA_D20 FBVDDQ_22 FBA_D21 FBVDDQ_23 FBA_D22 FBVDDQ_24 FBA_D23 FBVDDQ_25 FBA_D24 FBVDDQ_26 FBA_D25 FBVDDQ_27 FBA_D26 FBA_DQM<0> FBA_DQM<1> FBA_DQM<2> FBA_DQM<3> FBA_DQM<4> FBA_DQM<5> FBA_DQM<6> FBA_DQM<7> P32 H34 J30 P30 AF32 AL32 AL34 AF35 BI C FBA_DQS_DN<7..0> 0 1 2 3 4 5 6 7 L34 H35 J32 N31 AE31 AJ32 AJ34 AC33 FBA_DQS_DN<0> FBA_DQS_DN<1> FBA_DQS_DN<2> FBA_DQS_DN<3> FBA_DQS_DN<4> FBA_DQS_DN<5> FBA_DQS_DN<6> FBA_DQS_DN<7> L35 G35 H31 N32 AD32 AJ31 AJ35 AC34 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 OUT FBA_D48 FBA_D49 GT21X FBA_D50 FBA_CMD25 FBA_CMD0 FBA_D52 FBA_CMD23 FBA_CMD1 FBA_D53 FBA_CMD2 FBA_CMD2 FBA_D54 FBA_CMD0 FBA_CMD3 FBA_D55 FBA_CMD10 FBA_CMD4 FBA_D56 FBA_CMD26 FBA_CMD5 FBA_CMD14 FBA_CMD6 FBA_D58 FBA_CMD7 FBA_CMD7 FBA_D59 FBA_CMD1 FBA_CMD8 FBA_D60 FBA_CMD22 FBA_CMD9 FBA_D61 FBA_CMD20 FBA_CMD10 FBA_D62 FBA_CMD24 FBA_CMD11 FBA_CMD18 FBA_CMD12 FBA_D63 FBA_CMD29 FBA_DQM0 FBA_CMD8 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQS_WP0 FBA_CMD17 FBA_CMD11 FBA_CMD18 FBA_CMD16 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD5 FBA_CMD23 FBA_CMD4 FBA_CMD24 FBA_CMD6 FBA_DQS_WP2 FBA_CMD15 FBA_CMD15 FBA_CMD21 FBA_DQS_WP1 FBA_CMD14 FBA_CMD16 FBA_CMD3 FBA_DQM7 FBA_CMD13 FBA_CMD27 FBA_CMD28 FBA_DQM6 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_DQS_WP3 FBA_CMD13 FBA_DQS_WP4 FBA_CMD19 FBA_CMD28 FBA_CMD12 FBA_CMD29 FBA_CMD30 N/A FBA_CMD30 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CMD31 FBA_CLK0* FBA_DQS_RN0 FBA_CLK1 FBA_DQS_RN1 FBA_CLK1* FBA_DQS_RN2 74<> 73< 74< GF108 FBA_D51 FBA_D57 73<> FBA_CMD<30..0> FBA_CMD<25> U30 V30 U31 V32 T35 U33 W32 W33 W31 W34 U34 U35 U32 T34 T33 W30 AB30 AA30 AB31 AA32 AB33 Y32 Y33 AB34 AB35 Y35 W35 Y34 Y31 Y30 W29 Y29 25 FBA_CMD<2> FBA_CMD<0> FBA_CMD<10> FBA_CMD<26> FBA_CMD<14> FBA_CMD<7> FBA_CMD<1> FBA_CMD<22> FBA_CMD<20> FBA_CMD<24> FBA_CMD<18> FBA_CMD<9> FBA_CMD<29> FBA_CMD<8> FBA_CMD<27> 2 0 10 26 14 7 1 22 20 24 18 9 29 8 27 FBA_CMD<11> FBA_CMD<16> FBA_CMD<28> FBA_CMD<3> FBA_CMD<17> FBA_CMD<5> FBA_CMD<4> FBA_CMD<21> FBA_CMD<6> FBA_CMD<13> FBA_CMD<19> FBA_CMD<12> FBA_CMD<30> T32 T31 AC31 AC30 FBC_DQM<7..0> 11 16 28 3 17 5 4 21 6 13 19 12 30 OUT OUT OUT OUT FBVDDQ_35 FBVDDQ_36 FBB_D8 FBVDDQ_37 FBB_D9 FBVDDQ_38 FBB_D10 FBC_DQM<0> FBC_DQM<1> FBC_DQM<2> FBC_DQM<3> FBC_DQM<4> FBC_DQM<5> FBC_DQM<6> FBC_DQM<7> 0 1 2 3 4 5 6 7 A16 D10 F11 D15 D27 D34 A34 D28 FBA_CLK0_DP FBA_CLK0_DN FBA_CLK1_DP FBA_CLK1_DN OUT 73< 74< 74< IN FBC_DQS_DN<7..0> 0 1 2 3 4 5 6 7 FBA_DQS_RN3 P1V5_GPUS FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 R5041 FBA_DQS_RN7 FBC_DQS_DP<0> FBC_DQS_DP<1> FBC_DQS_DP<2> FBC_DQS_DP<3> FBC_DQS_DP<4> FBC_DQS_DP<5> FBC_DQS_DP<6> FBC_DQS_DP<7> 0 1 2 3 4 5 6 7 FBC_DQS_DN<0> FBC_DQS_DN<1> FBC_DQS_DN<2> FBC_DQS_DN<3> FBC_DQS_DN<4> FBC_DQS_DN<5> FBC_DQS_DN<6> FBC_DQS_DN<7> 1 2 C5072 C5056 C5073 0.1UF_16V_2 FBB_D15 1UF_6.3V_2 FBB_D16 FBB_D17 0.1UF_16V_2 0.1UF_16V_2 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 E FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBC_CMD<30..0> FBB_D47 FBB_D48 FBB_D49 FBB_D51 FBB_CMD1 FBB_CMD2 FBB_CMD2 FBB_D54 FBB_CMD0 FBB_CMD3 FBB_D56 FBB_D57 FBB_CMD10 FBB_CMD4 FBB_CMD26 FBB_CMD5 FBB_CMD14 FBB_CMD6 FBB_D58 FBB_CMD7 FBB_D59 FBB_CMD1 FBB_CMD7 FBB_CMD8 FBB_D60 FBB_CMD22 FBB_CMD9 FBB_D61 FBB_CMD20 FBB_CMD10 FBB_D62 FBB_CMD24 FBB_CMD11 FBB_CMD18 FBB_CMD12 FBB_D63 FBB_CMD13 FBB_CMD14 FBB_CMD29 FBB_DQM0 FBB_CMD15 FBB_CMD8 FBB_DQM1 FBB_CMD27 FBB_CMD16 FBB_DQM3 FBB_CMD15 FBB_CMD17 FBB_DQM4 FBB_CMD11 FBB_CMD18 FBB_CMD16 FBB_CMD19 FBB_CMD28 FBB_CMD20 FBB_DQM2 FBB_DQM5 FBB_DQM6 FBB_CMD21 FBB_CMD3 FBB_DQM7 FBB_DQS_WP0 B26 FBB_DQS_WP7 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 F18 E19 D18 C17 F19 C19 B17 E20 B19 D20 A19 D19 C20 F20 B20 G21 F22 F24 F23 C25 C23 F21 E22 D21 A23 D22 B23 C22 B22 A22 A20 G20 FBB_CMD0 FBB_CMD23 FBB_D53 FBB_D55 76<> 75< 76< GF108 FBB_CMD25 FBB_D52 75<> OUT GT21X FBB_D50 FBB_CMD22 FBB_CMD5 FBB_CMD23 FBB_CMD4 FBB_CMD24 FBB_CMD25 FBB_CMD21 FBB_CMD26 FBB_CMD6 FBB_CMD13 FBB_CMD27 FBB_CMD19 FBB_CMD28 FBB_CMD12 FBB_CMD29 FBB_CMD30 N/A FBB_CMD30 FBB_CMD31 FBC_CMD<25> 25 FBC_CMD<2> FBC_CMD<0> FBC_CMD<10> FBC_CMD<26> FBC_CMD<14> FBC_CMD<7> FBC_CMD<1> FBC_CMD<22> FBC_CMD<20> FBC_CMD<24> FBC_CMD<18> FBC_CMD<9> FBC_CMD<29> FBC_CMD<8> FBC_CMD<27> 2 0 10 26 14 7 1 22 20 24 18 9 29 8 27 FBC_CMD<11> FBC_CMD<16> FBC_CMD<28> FBC_CMD<3> FBC_CMD<17> FBC_CMD<5> FBC_CMD<4> FBC_CMD<21> FBC_CMD<6> FBC_CMD<13> FBC_CMD<19> FBC_CMD<12> FBC_CMD<30> 11 16 28 3 17 5 4 21 6 13 19 12 30 D C FBB_DQS_RN0 FBB_DQS_RN1 E17 D17 D23 E23 FBB_CLK0 FBB_DQS_RN2 FBB_CLK0* FBB_DQS_RN3 FBB_CLK1 FBB_DQS_RN4 FBB_CLK1* FBB_DQS_RN5 OUT OUT OUT OUT P1V5_GPUS 75< FBC_CLK0_DP FBC_CLK0_DN FBC_CLK1_DP FBC_CLK1_DN 75< 76< 76< R5037 FBB_DQS_RN6 FBB_DQS_RN7 FBA_WCK0 FBA_DEBUG0_CAS2 FBA_WCK1 FBA_DEBUG1 FBA_WCK1* 60.4_1%_2 60.4_1%_2 +GPU_V1.5S_FBA_DEBUG 2 10K_5%_2 R50161 T30 T29 2 FBA_WCK0* FBA_WCK2 P1V05_GPUS FBA_WCK2* FBA_WCK3 FBA_WCK3* 16mil 1 1 C5075 C5060 0.1UF_16V_2 FBB_WCK1* FBB_WCK2 FBB_WCK2* FBB_WCK3 FBB_WCK3* B P1V5_GPUS C5077 10UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 FBM_10_160808_301A05T_500mA 1UF_6.3V_2 4.7uF_6.3V_3 2 J19 J18 FBB_WCK1 10mil 2 2 FB_PLLAVDD_2 FBB_DEBUG1 FBB_WCK0* 2 C5074 C5059 2 FB_DLLAVDD_2 RFU 2 RFU FBB_WCK0 K27 FB_CAL_PD_VDDQ GF108 FB_VREF_NC +GPU_V1.5S_FBC_DEBUG 1 R5077 2 10K_5%_2 1 C5076 GF108 2 GT21X L5000 G14 G15 G11 G12 G27 G28 G24 G25 G19 G16 FBB_DEBUG0_CAS2 1 1 FB_PLLAVDD_1 1 B +GPU_V1.05S_FB_DLLAVDD0 AG27 AF27 1 FB_DLLAVDD_1 J27 C5071 FBB_D14 C14 A10 E10 D14 E26 D32 A32 B14 B10 D9 E14 F26 D31 A31 A26 1 C5057 FBB_D13 FBB_CMD17 FBC_DQS_DP<7..0> 1 FBB_D12 FBB_CMD9 OUT 1 FBB_D11 2 FBVDDQ_34 FBB_D6 FBB_D7 C5070 0.1UF_16V_2 4.7UF_6.3V_3 0.1UF_16V_2 4.7UF_6.3V_3 2 FBVDDQ_33 FBB_D5 C5079 C5078 2 1 1 FBA_D31 FBVDDQ_32 FBB_D4 2 P29 R29 L29 M29 AG29 AH29 AD29 AE29 1 FBA_D30 1 0 1 2 3 4 5 6 7 1uF_6.3V_2 0.1UF_16V_2 FBA_D29 FBA_CLK0 BI 0.1UF_16V_2 FBVDDQ_31 FBB_D3 1 FBA_DQS_DP<0> FBA_DQS_DP<1> FBA_DQS_DP<2> FBA_DQS_DP<3> FBA_DQS_DP<4> FBA_DQS_DP<5> FBA_DQS_DP<6> FBA_DQS_DP<7> C5085 FBA_D28 FBA_CMD17 FBA_DQS_DP<7..0> C5062 FBA_D27 FBA_CMD9 0 1 2 3 4 5 6 7 C5084 FBB_D2 1 FBVDDQ_10 FBA_D9 FBVDDQ_30 2 FBVDDQ_9 FBA_D8 FBVDDQ_29 FBB_D1 1 FBVDDQ_8 FBA_D7 4.7UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 4.7UF_6.3V_3 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 FBVDDQ_28 FBB_D0 2 FBA_D6 C5082 C5081 C5080 B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25 FBB 1 FBVDDQ_7 FBC_D<0> FBC_D<1> FBC_D<2> FBC_D<3> FBC_D<4> FBC_D<5> FBC_D<6> FBC_D<7> FBC_D<8> FBC_D<9> FBC_D<10> FBC_D<11> FBC_D<12> FBC_D<13> FBC_D<14> FBC_D<15> FBC_D<16> FBC_D<17> FBC_D<18> FBC_D<19> FBC_D<20> FBC_D<21> FBC_D<22> FBC_D<23> FBC_D<24> FBC_D<25> FBC_D<26> FBC_D<27> FBC_D<28> FBC_D<29> FBC_D<30> FBC_D<31> FBC_D<32> FBC_D<33> FBC_D<34> FBC_D<35> FBC_D<36> FBC_D<37> FBC_D<38> FBC_D<39> FBC_D<40> FBC_D<41> FBC_D<42> FBC_D<43> FBC_D<44> FBC_D<45> FBC_D<46> FBC_D<47> FBC_D<48> FBC_D<49> FBC_D<50> FBC_D<51> FBC_D<52> FBC_D<53> FBC_D<54> FBC_D<55> FBC_D<56> FBC_D<57> FBC_D<58> FBC_D<59> FBC_D<60> FBC_D<61> FBC_D<62> FBC_D<63> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 C5083 2 FBVDDQ_6 FBA_D5 2 FBVDDQ_5 FBA_D4 2 FBVDDQ_4 FBA_D3 3/16 1 FBVDDQ_3 FBA_D2 P1V5_GPUS U5000 2 OUT FBVDDQ_2 FBA_D1 F BI 1 FBA_DQM<7..0> FBA_D0 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 J23 J24 J29 2 D FBVDDQ_1 FBC_D<63..0> 75<> 76<> FBA 1 E L32 N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30 AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33 AL31 AM33 AL33 AK30 AK32 AJ30 AH30 AH33 AH35 AH34 AH32 AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35 2 2/16 FBA_D<0> 0 FBA_D<1> 1 FBA_D<2> 2 3 FBA_D<3> FBA_D<4> 4 5 FBA_D<5> 6 FBA_D<6> FBA_D<7> 7 FBA_D<8> 8 FBA_D<9> 9 10 FBA_D<10> 11 FBA_D<11> 12 FBA_D<12> 13 FBA_D<13> 14 FBA_D<14> 15 FBA_D<15> 16 FBA_D<16> 17 FBA_D<17> 18 FBA_D<18> 19 FBA_D<19> 20 FBA_D<20> 21 FBA_D<21> 22 FBA_D<22> 23 FBA_D<23> 24 FBA_D<24> 25 FBA_D<25> 26 FBA_D<26> 27 FBA_D<27> 28 FBA_D<28> 29 FBA_D<29> 30 FBA_D<30> 31 FBA_D<31> 32 FBA_D<32> 33 FBA_D<33> 34 FBA_D<34> 35 FBA_D<35> 36 FBA_D<36> 37 FBA_D<37> 38 FBA_D<38> 39 FBA_D<39> 40 FBA_D<40> 41 FBA_D<41> 42 FBA_D<42> 43 FBA_D<43> 44 FBA_D<44> 45 FBA_D<45> 46 FBA_D<46> 47 FBA_D<47> 48 FBA_D<48> 49 FBA_D<49> 50 FBA_D<50> 51 FBA_D<51> 52 FBA_D<52> 53 FBA_D<53> 54 FBA_D<54> 55 FBA_D<55> 56 FBA_D<56> 57 FBA_D<57> 58 FBA_D<58> 59 FBA_D<59> 60 FBA_D<60> 61 FBA_D<61> 62 FBA_D<62> 63 FBA_D<63> 1 BI 2 FBA_D<63..0> 1 73<> 2 74<> 2 U5000 F +GPU_V1.5S_FBCAL_PD_VDDQ GT21X L27 FB_CAL_PU_GND FB_VREF P1V05_GPUS 1 1 R5040 R5039 NVIDIA_N12P_GS_BGA_973P 1 60.4_1%_2 2 FBM_10_160808_301A05T_500mA 1 C5067 C5061 10UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 40.2_1%_2 1 2 1 2 C5037 C5066 0.1UF_16V_2 2 2 C5038 L5002 2 M27 FB_CAL_TERM_GND NVIDIA_N12P_GS_BGA_973P 1 R5038 1 40.2_1%_2 C5058 4.7uF_6.3V_3 2 2 2 1 1 2 1UF_6.3V_2 A A INVENTEC TITLE SIZE C CHANGE by 8 7 6 5 4 3 Frank Hu DATE Fri Dec 31 10:16:50 2 2010 EVEREST GPU-2 CODE ES SHEET DOC.NUMBER REV CS_1310AXXXXXX-MTR 69 of 1 A01 97 8 7 6 5 4 3 2 1 U5000 GND_126 GND_32 GND_127 GND_33 GND_128 GND_34 GND_129 GND_35 GND_130 GND_36 GND_131 GND_37 GND_132 GND_38 GND_133 GND_39 GND_134 GND_40 GND_135 GND_41 GND_136 GND_42 GND_137 GND_43 GND_138 GND_44 GND_139 GND_45 GND_140 GND_46 GND_141 GND_47 GND_142 GND_48 GND_143 GND_49 GND_144 GND_50 GND_145 GND_51 GND_146 GND_52 GND_147 GND_53 GND_148 GND_54 GND_149 GND_55 GND_150 GND_56 GND_151 GND_57 GND_152 GND_58 GND_153 GND_59 GND_154 GND_60 GND_155 GND_61 GND_156 GND_62 GND_157 GND_63 GND_158 GND_64 GND_159 GND_65 GND_160 GND_66 GND_161 GND_67 GND_162 GND_68 GND_163 GND_69 GND_164 GND_70 GND_165 GND_71 GND_166 GND_72 GND_167 GND_73 GND_168 GND_74 GND_169 GND_75 GND_170 GND_76 GND_171 GND_77 GND_172 GND_78 GND_173 GND_79 GND_174 GND_80 GND_175 GND_081 GND_176 GND_082 GND_177 GND_083 GND_178 GND_084 GND_179 GND_085 GND_180 GND_086 GND_181 GND_087 GND_182 GND_088 GND_183 GND_089 GND_184 GND_090 GND_185 GND_091 GND_186 GND_092 GND_187 GND_093 GND_188 GND_094 GND_189 GND_095 GND_190 GND_191 VDD_079 VDD_024 VDD_080 VDD_025 VDD_081 VDD_026 VDD_082 VDD_027 VDD_083 VDD_028 VDD_084 VDD_029 VDD_085 VDD_030 VDD_086 VDD_031 VDD_087 VDD_032 VDD_088 VDD_033 VDD_089 VDD_034 VDD_090 VDD_035 VDD_091 VDD_036 VDD_092 VDD_037 VDD_093 VDD_038 VDD_094 VDD_039 VDD_095 VDD_040 VDD_096 VDD_041 VDD_097 VDD_042 VDD_098 VDD_043 VDD_099 VDD_044 VDD_100 VDD_045 VDD_101 VDD_046 VDD_102 VDD_047 VDD_103 VDD_048 VDD_104 VDD_049 VDD_105 VDD_050 VDD_106 VDD_051 VDD_107 VDD_052 VDD_108 VDD_053 VDD_109 VDD_054 VDD_110 VDD_055 VDD_111 C5120 C5121 C5122 C5123 C5124 C5125 0.015UF_10V_2 0.015UF_10V_2 0.022uF_16V_2 0.022uF_16V_2 0.022uF_16V_2 0.047UF_16V_2 C5115 C5119 C5118 C5117 C5116 0.047UF_16V_2 0.047UF_16V_2 1uF_6.3V_2 0.1UF_16V_2 C5054 C5053 0.1UF_16V_2 C5052 0.22UF_6.3V_2 0.22UF_6.3V_2 0.22UF_6.3V_2 C5114 C5113 C5112 C5055 4.7uF_6.3V_3 10uF_6.3V_3 10uF_6.3V_3 22UF_6.3V_5 B VDD_056 NVIDIA_N12P_GS_BGA_973P A INVENTEC EVEREST-M GPU-3 TITLE NVIDIA_N12P_GS_BGA_973P SIZE C CHANGE 8 C 1 GND_31 VDD_078 VDD_023 6800PF_25V_2 2 GND_125 VDD_077 VDD_022 0.01UF_50V_2 1 GND_30 VDD_076 VDD_021 0.01UF_50V_2 2 GND_124 VDD_075 VDD_020 0.01UF_50V_2 1 GND_123 GND_29 VDD_019 0.01UF_50V_2 2 GND_28 VDD_074 C5126 1 GND_122 VDD_018 4700PF_50V_2 C5127 2 GND_121 GND_27 VDD_073 C5128 1 GND_120 GND_26 VDD_072 VDD_017 C5129 2 GND_25 VDD_016 C5130 2 GND_119 C5131 1 GND_118 GND_24 VDD_071 2 GND_117 GND_23 VDD_070 VDD_015 1 GND_22 VDD_069 VDD_014 2 GND_116 VDD_068 VDD_013 1 GND_21 VDD_012 D 2 GND_115 VDD_067 1 GND_114 GND_20 VDD_066 VDD_011 2 GND_113 GND_19 VDD_065 VDD_010 1 GND_18 VDD_009 2 GND_112 PVCORE_GPU 1 GND_111 GND_17 VDD_064 2 GND_110 GND_16 VDD_063 1 GND_15 VDD_062 VDD_008 2 GND_109 VDD_007 1 GND_14 VDD_061 VDD_006 2 GND_108 VDD_060 VDD_005 1 GND_13 VDD_059 VDD_004 2 GND_107 VDD_003 P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 1 GND_12 VDD_058 2 GND_106 VDD_057 1 GND_105 NVVDD VDD_002 2 GND_104 GND_11 16/16 VDD_001 1 GND_9 GND_10 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 1 GND_103 2 GND_102 GND_8 1 GND_7 U5000 2 GND_101 1 GND_100 GND_6 2 GND_099 GND_5 PVCORE_GPU 1 GND_4 PVCORE_GPU 2 GND_098 1 GND_3 E15 E18 E24 E27 E30 E6 E9 F2 F31 F34 F5 J2 J31 J34 J5 L9 M11 M13 M15 M17 M19 M2 M21 M23 M25 M31 M34 M5 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R31 R34 R5 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V12 V14 V16 V18 V2 V20 V22 V24 V31 V5 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 2 A GND_097 1 B GND_096 2 C GND GND_2 2 D 15/16 GND_1 1 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AA5 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD11 AD13 AD15 AD17 AD2 AD21 AD23 AD25 AD31 AD34 AD5 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG31 AG34 AG5 AK2 AK31 AK34 AK5 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AL6 AL9 AN2 AN34 AP12 AP15 AP18 AP21 AP24 AP27 AP3 AP30 AP33 AP6 AP9 B12 B15 B21 B24 B27 B3 B30 B33 B6 B9 C2 C34 E12 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:17:04 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 70 97 of 1 REV A01 8 7 6 5 4 3 2 1 U5000 7/16 U5000 IFPAB 5/16 DVI-DL LVDS IFPAB_TXD0* IFPAB_TXD0 IFPA_TXD0* IFPA_TXD0 AL8 AM8 GPU_LVDS1_TXDL0_DN GPU_LVDS1_TXDL0_DP 20mil L5001 2 1 MMZ1608S181AT AJ11 C5094 C5093 C5092 IFPAB_TXD2* IFPAB_PLLVDD IFPAB_TXD2 IFPA_TXD1 IFPA_TXD2* IFPA_TXD2 AM9 AM10 OUT OUT GPU_LVDS1_TXDL1_DN GPU_LVDS1_TXDL1_DP AL10 AK10 OUT OUT GPU_LVDS1_TXDL2_DN GPU_LVDS1_TXDL2_DP 2 R5035 R5070 IFPA_TXD3 10K_5%_2 1 IFPAB_TXC* IFPA_TXC* 2 2 2 2 IFPAB_TXC AL11 AK11 IFPAB_TXD3 IFPA_TXC AM12 AM11 OUT GPU_LVDS1_TXCL_DN OUT GPU_LVDS1_TXCL_DP IFPB_TXD4* IFPB_TXD4 IFPA_IOVDD AG10 IFPB_IOVDD C5095 C5097 C5098 C5099 4.7uF_6.3V_3 1uF_6.3V_2 0.1UF_16V_2 0.1UF_16V_2 IFPAB_TXD4* IFPAB_TXD4 IFPAB_TXD5* IFPB_TXD5* IFPB_TXD5 IFPB_TXD6* IFPB_TXD6 2 2 IFPD_IOVDD IFPB_TXD7 U5000 IFPB_TXC* IFPB_TXC IFPEF IFPD GPU_LVDS2_TXDL1_DN GPU_LVDS2_TXDL1_DP AR10 AR11 OUT OUT GPU_LVDS2_TXDL2_DN GPU_LVDS2_TXDL2_DP TXC TXD0 TXD0 TXD0 TXD0 TXD1 TXD1 TXD1 TXD1 IFPE_AUX IFPE_L3* IFPE_L3 IFPE_L2* IFPE_L2 AD4 AE4 IFPAB AE5 AE6 GPIO0 TXD2 HPDE HPDE GPU_LVDS2_TXCL_DN GPU_LVDS2_TXCL_DP NVIDIA_N12P_GS_BGA_973P AF5 AF4 IFPE_L1* IFPE_L1 IFPE_L0* IFPE_L0 GPIO15 AG4 AH4 L5008 1 20mil 8/16 2 AJ9 FBM_10_160808_301A05T_500mA AH5 AH6 C5106 4.7uF_6.3V_3 L1 C5111 C5050 C5110 4.7UF_6.3V_3 0.1UF_16V_2 C5049 IFPF_AUX* IFPF_AUX AF2 AF3 P1V05_GPUS IFPC_RSET R5071 TXD4 TXD1 TXD5 TXD2 TXD5 TXD2 IFPF_L1* IFPF_L1 IFPF_L0* IFPF_L0 GPIO21 C5107 1uF_6.3V_2 1 0.1UF_16V_2 0.1UF_16V_2 DACB_GREEN AL4 DACB_BLUE AJ4 C5101 C5100 C5041 C5104 4/16 IFPC_L2 IFPC_L1* IFPC_L1 TXD2 IFPC_IOVDD IFPC_L0* TXD2 IFPC_L0 GPIO1 I2CA_SCL I2CA_SDA OUT GPU_HDMI_TXC_DN OUT GPU_HDMI_TXC_DP AM4 AM3 OUT GPU_HDMI_TX0_DN OUT GPU_HDMI_TX0_DP AM5 AL5 OUT GPU_HDMI_TX1_DN OUT GPU_HDMI_TX1_DP AM6 AM7 OUT GPU_HDMI_TX2_DN OUT GPU_HDMI_TX2_DP DACA_VREF AK13 DACA_RSET K2 AM13 AL13 DACA_RED AM15 OUT GPU_CRT_R 45< DACA_GREEN AM14 OUT GPU_CRT_G 45< DACA_BLUE AL14 OUT GPU_CRT_B 45< 1 0.1UF_16V_2 0.1UF_16V_2_DY 2 124_1%_2 2 2 GPU_CRT_HSYNC GPU_CRT_VSYNC OUT OUT 150_1%_2 INVENTEC R5066 R5065 150_1%_2 150_1%_2 2 2 2 CHANGE 5 4 3 by Frank Hu EVEREST-M GPU-4 TITLE SIZE C 6 A 1 1 1 R5067 7 GPU_HDMI_HPDET IN DACA_VSYNC DACA_HSYNC NVIDIA_N12P_GS_BGA_973P 8 B G1 G4 1 C5051 2 AR2 AP1 HPDC DACA AK12 R5068 1uF_6.3V_2 AN3 AP2 0.1UF_6.3V_1 1 1 2 2 0.1UF_16V_2 C5040 C5102 C NVIDIA_N12P_GS_BGA_973P DACA_VDD 0.1UF_16V_2_DY 4.7uF_6.3V_3 2 4.7uF_6.3V_3 IFPC_L2* IFPC AJ12 1 1 K6 20mil +GPU_V3S_DACA_VDD 2 2 NVIDIA_N12P_GS_BGA_973P AK4 IFPC_L3 TXD0 U5000 C5103 A C5109 1 HPDF C5108 P3V3_GPUS L5003 IFPC_L3* TXD0 AJ8 AJ2 AJ3 FBM_10_160808_301A05T_500mA IFPEF C5105 4.7uF_6.3V_3 AL3 AL2 TXC 2 TXD1 IFPF_L2 AH1 AJ1 2 2 TXD4 DACB_RED 1 TXD0 IFPF_L2* 20mil 2 BLM15AG221SN1D_300mA IFPC_AUX TXC 2 TXD3 AM1 AM2 IFPC_AUX* SCL TXD1 2 TXD0 DACB_VSYNC DACB_HSYNC DP SDA TXD1 1 IFPF_L3 L5004 1 AH3 AH2 1 10K_5%_2 TXD3 DACB_RSET I2CB_SDA DVI/HDMI IFPCD_IOVDD 1 IFPF_L3* 1 R5028 AH7 G3 G2 I2CB_SCL IFPC IFPC_PLLVDD AK7 C5048 1UF_6.3V_2_DY 0.1UF_16V_2_DY 0.1UF_16V_2_DY 1 TXC DACB_VREF 2.2K_1%_2 U5000 IFPCD_PLLVDD P3V3_GPUS IFPF_IOVDD TXC DACB_VDD AK6 R5022 1 SCL AD7 L7 NVIDIA_N12P_GS_BGA_973P 2 SDA AG7 2 10K_5%_2_DY 2 IFPE_IOVDD 2.2K_1%_2 DACB R5024 1 K1 2 TXD2 TXD2 OUT OUT 1K_1%_2 AE7 D 1 2 2 B TXD2 2 6/16 HPDAB 1 1K_1%_2_DY AN13 AP13 2 R5069 1 10K_5%_2 1 TXC TXC AP11 AN11 1 TXC U5000 R5064 2 IFPEF_RSET AR7 AR8 NVIDIA_N12P_GS_BGA_973P R5023 1 IFPEF_PLLVDD SCL 1 1 10K_5%_2 OUT OUT GPIO19 DP IFPE_AUX* SCL R5029 AN10 AP10 2 SDA AL1 GPU_LVDS2_TXDL0_DN GPU_LVDS2_TXDL0_DP 1 DVI-SL HDMI DVI-DL AJ6 IFPD_L0 HPDD OUT OUT 2 9/16 IFPD_L0* TXD2 AN7 AP7 R5034 AP8 AN8 1 2 2 2 IFPB_TXD7* C IFPD_L1 AP5 AN5 1 1 AG9 IFPAB_TXD5 4.7uF_6.3V_3 IFPD_L1* AR4 AR5 2 2 1 1 1 1 C5096 AN4 AP4 P3V3_GPUS 1 MMZ1608S181AT IFPD_L2 TXD2 AK8 20mil +GPU_V3S_IFPA_IOVDD 2 IFPD_L2* TXD1 2 L5005 IFPD_L3 TXD0 1 IFPAB_TXD3* 1 IFPD_L3* TXD0 10K_5%_2 P3V3_GPUS TXC 1K_1%_2_DY 2 1K_1%_2 0.1UF_16V_2 IFPD_AUX TXD1 IFPA_TXD3* R5072 2 1uF_6.3V_2 SCL TXC 4.7uF_6.3V_3 4.7uF_6.3V_3 IFPD_AUX* IFPAB_RSET 1 1 1 1 C5091 D AK9 +GPU_V1.05S_IFPAB_PLLVDD IFPA_TXD1* IFPD_RSET SDA 2 1 IFPAB_TXD1 DP IFPD_PLLVDD AB6 P1V05_GPUS IFPAB_TXD1* DVI/HDMI AC6 1 OUT OUT IFPD DATE Tue Jan 2 04 00:15:45 2011 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 71 97 of 1 REV A01 8 7 6 5 4 3 2 1 P3V3_GPUS P3V3_GPUS 1 1 1 1 34.8K_1%_2 1 1 72> IN MIOA_D1_NC MIOA_VDDQ_NC_3 MIOA_D2_NC MIOA_VDDQ_NC_4 MIOA_D3_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC 0.1UF_16V_2 2 10K_1%_2 15K_1%_2 U5 MIOA_CAL_PD_VDDQ_NC T5 MIOA_CAL_PU_GND_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC 2 2 2 10K_5%_2_DY MIOA_D9_NC MIOA_D14_NC N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 MIOB MIOB_VDDQ_NC_1 MIOB_D0_NC MIOB_VDDQ_NC_2 MIOB_D1_NC MIOB_VDDQ_NC_3 MIOB_D2_NC MIOB_VDDQ_NC_4 MIOB_D3_NC Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 MIOB_D4_NC MIOB_D5_NC MIOB_D6_NC C5086 MIOB_D7_NC MIOB_D8_NC 0.1UF_16V_2 MIOB_D9_NC AA7 MIOB_CAL_PD_VDDQ_NC AA6 MIOB_CAL_PU_GND_NC MIOB_D10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC FOR NVIDIA_N12P_GS_BGA_973P N5 11/16 AA9 AB9 W9 Y9 2 2 R5015 R5014 R5013 2 MIOA_VDDQ_NC_2 MIOA_D8_NC 24.9K_1%_2 2 24.9K_1% MIOA_D0_NC C5087 1 R5009 10K_5%_2_DY 10K_5%_2_DY IN 1 R5007 72> MIOA_VDDQ_NC_1 MIOA_D4_NC 1 R5008 IN ROM_SO ROM_SCLK 1 IN 20mil 1 IN 72> MIOA 1 ROM_SI 15K_1%_2 2 10K_5%_2_DY 10K_5%_2_DY IN 10/16 P9 R9 T9 U9 10K_5%_2_DY 2 72< D R5010 R5011 2 72< STRAP0 STRAP1 STRAP2 2 2 2 72< 20mil 1 R5012 45.3K_1%_2 U5000 U5000 R5004 R5005 1 R5006 P3V3_GPUS P3V3_GPUS AF1 MIOA_VREF_NC MIOB_VREF_NC P3V3_GPUS MIOA_CTL3_NC MIOA_HSYNC_NC 1 MIOA_VSYNC_NC MIOA_DE_NC C5090 0.1UF_16V_2_DY 2 MIOA_CLKOUT_NC C5089 C MIOA_CLKOUT_NC* 2 1 1 2 3 4 2200PF_50V_2_DY THRM_GPU_DP IN THRM_GPU_DN IN THRM_SHUTDWN# OUT 72> 72> MIOA_CLKIN_NC U4412 VCC SMBCLK DXP SMBDATA DXN ALERT# THERM# GND R5054 R5053 8 7 6 5 1 1 2 0_5%_2 2 0_5%_2 EC_SMB2_CLK 8> EC_SMB2_DATA 8> BI BI P5 N3 L3 N2 MIOB_VSYNC_NC MIOB_DE_NC V4 W4 R5047 AE1 1 MIOB_CLKOUT_NC 1 R5048 MIOB_CLKOUT_NC* 2 MIOB_CLKIN_NC 10K_5%_2 37<> 37<> W3 W1 W2 Y5 MIOB_CTL3_NC MIOB_HSYNC_NC R4 T4 N4 D NVIDIA_N12P_GS_BGA_973P NVIDIA_N12P_GS_BGA_973P C 2 10K_5%_2 GMT_G784_MSOP_8P__DY 1 1 P3V3_GPUS R5055 0_5%_2 0_5%_2 1 1 R5056 R5020 2 2 R5001 U5000 72< THRM_GPU_DN OUT THERMDN I2CS_SCL I2CS_SDA I2CC_SCL I2CC_SDA B GPIO5 1 1 GPIO6 R5031 GPIO7 GPIO8 GPIO13 GPIO14 R5059 ALERT# 1 2 0_5%_2_DY P3V3_GPUS 1 R5042 2 0_5%_2 1 U5000 13/16 J26 J25 MISC2 ROM_CS* BBIASN_NC BBIASP_NC ROM_SI ROM_SO 1 R5052 1 R5051 10K_5%_2 10K_5%_2 2 GPU_LCM_INVPWM GPU_LCM_VDDEN GPU_LCM_BKLTEN GPU_VID0 16< GPU_VID1 OUT OUT OUT OUT OUT OUT THRM_SHUTDWN# ROM_SCLK R5050 STRAP0 10K_5%_2 STRAP1 2 STRAP2 2 10K_5%_2 C3 D3 C4 D4 OUT ROM_SI 72< OUT ROM_SO 72< OUT ROM_SCLK 72< W5 W7 V7 IN IN IN STRAP0 STRAP1 STRAP2 GPIO20 PUT TOGETHER GPIO22 GPIO23 GPIO24 R5049 1 2.2K_1%_2 2 100K_5%_2 P3V3_GPUS L5 L6 M6 M7 R5063 1 R50211 2 2 AB5 F6 I2CH_SDA G6 SPDIF_NC A5 1 A4 C5 3 36K_5%_2 Q5000 BUFRST* D NVIDIA_N12P_GS_BGA_973P 1 BI DCIN_BLED# 37> R5062 R5061 58< S G 1 1 2 40.2K_1%_2 2 40.2K_1%_2 PGOOD_OUT* N9 M9 R5036 2 MULTI_STRAP_REF1_GND SSM3K7002BFU GND_H AK14 K9 INVENTEC CHANGE 6 5 4 3 by Frank Hu EVEREST-M GPU-5 TITLE SIZE C 7 0.1uF_16V_2 A NVIDIA_N12P_GS_BGA_973P 8 2.2K_1%_2 MULTI_STRAP_REF0_GND GND_F 2 C5088 CEC 10K_5%_2 0_5%_2_DY I2CH_SCL R5057 2 GPIO18 2 2 10K_5%_2 L2 L4 M4 72< 72< R5058 72< 2 GPIO16 P3V3_GPUS 2 R5043 GPIO17 10K_5%_2 A R5060 1 JTAG_TRST* GPIO12 10K_5%_2 1 JTAG_TDO GPIO11 R5044 10K_5%_2 1 1 R5033 JTAG_TDI GPIO10 B 1 0_5%_2_DY JTAG_TMS GPU_LVDS_DDCDATA 2 2 JTAG_TCK GPU_LVDS_DDCCLK BI 1 R5030 2 2 1 GPIO9 10K_5%_2 BI 2 GPIO4 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 R5045 2 GPIO3 2 GPIO2 AP14 AR14 AN14 AN16 AP16 2 0_5%_2 1 R5025 2 10K_5%_2 10K_5%_2 R50191 1 R5046 10K_5%_2 R5032 2 P3V3_GPUS THERMDP P3V3_GPUS 0_5%_2 R5018 1 E3 E4 1 B5 THRM_GPU_DP OUT E2 E1 1 72< 2.2K_1%_2 2.2K_1%_2 MISC1 2 2 12/16 B4 DATE Fri Dec 2 31 10:16:52 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 72 97 of 1 REV A01 8 7 6 5 4 3 2 1 U5501 FBA_VREF0 73< FBA_CMD<30..0> U5500 VREFDQ DQL0 VREFCA DQL1 DQL2 BI D FBA_CMD<7> FBA_CMD<20> FBA_CMD<4> FBA_CMD<14> FBA_CMD<17> FBA_CMD<6> FBA_CMD<26> FBA_CMD<3> FBA_CMD<1> FBA_CMD<10> FBA_CMD<21> FBA_CMD<5> FBA_CMD<22> FBA_CMD<18> FBA_CMD<29> FBA_CMD<30> N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 DQL4 A1 DQL5 A2 DQL6 DQL7 A3 M2 N8 M3 FBA_CMD<12> FBA_CMD<9> FBA_CMD<13> 73< 69> C 0 FBA_CMD<0> 25 2 24 8 19 FBA_CMD<25> FBA_CMD<2> FBA_CMD<24> FBA_CMD<8> FBA_CMD<19> J7 K7 K9 IN IN FBA_CLK0_DP FBA_CLK0_DN K1 L2 J3 K3 L3 A5 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#F1 BI BI F3 C7 DQSL BI BI E7 D3 DML VSS#A9 DMU VSS#B3 G3 B7 BI BI VDDQ#H2 VDDQ#H9 DQSU VSS#G8 DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 VSS#M9 T2 IN L8 VSS#P9 RESET# VSS#T1 ZQ VSS#T9 FBA_CMD<12> FBA_CMD<9> FBA_CMD<13> M2 N8 M3 P1V5_GPUS B2 D9 G7 K2 K8 N1 N9 R1 R9 0 25 2 24 8 19 1.5A VSSQ#B1 2 VSSQ#B9 243_1%_2 VSSQ#D1 2 VSSQ#D8 J1 L1 J9 L9 VSSQ#E2 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 DQL3 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 K1 L2 J3 K3 L3 FBA_CMD<25> FBA_CMD<2> FBA_CMD<24> FBA_CMD<8> FBA_CMD<19> A5 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 FBA_DQS_DP<2> FBA_DQS_DP<1> FBA_DQM<2> FBA_DQM<1> DQU7 A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#F1 BI BI F3 C7 DQSL VDDQ#H2 DQSU VDDQ#H9 BI BI E7 D3 DML VSS#A9 DMU VSS#B3 BI BI G3 B7 DQSL# VSS#J2 DQSU# VSS#J8 VSS#E1 69<> 69<> A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBA_DQS_DN<2> FBA_DQS_DN<1> VSS#G8 VSS#M1 VSS#M9 74< 73< 74<> 73<> 69> FBA_CMD<28> IN FBA_D<21> FBA_D<16> FBA_D<23> FBA_D<18> FBA_D<22> FBA_D<17> FBA_D<20> FBA_D<19> 21 16 23 18 22 17 20 19 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D<14> FBA_D<11> FBA_D<15> FBA_D<10> FBA_D<12> FBA_D<8> FBA_D<13> FBA_D<9> 14 11 15 10 12 8 13 9 BI FBA_D<16..23> BI FBA_D<8..15> 69<> VSS#P1 T2 RESET# L8 ZQ VSS#P9 VSS#T1 VSS#T9 69<> D P1V5_GPUS A14 VDDQ#E9 69<> 69<> A1 A8 C1 C9 D2 E9 F1 H2 H9 E3 F7 F2 F8 H3 H8 G2 H7 A4 P1V5_GPUS B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5A P1V5_GPUS A1 A8 C1 C9 D2 E9 F1 H2 H9 C A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 R5529 VSSQ#B1 VSSQ#B9 243_1%_2 VSSQ#D1 73< 69> FBA_CLK0_DP VSSQ#D8 J1 L1 J9 L9 IN B1 B9 D1 D8 E2 E8 F9 G1 G9 73< 69> 74<> FBA_CLK0_DN 73<> 69> IN FBA_CMD<25> IN VSSQ#E2 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 B 160_1%_2 1 R5525 HYNIX_H5TQ1G63DFR_11C_FBGA_96P 2 10K_5%_2 74<> 73<> 69> FBA_CMD<27> IN 1 R5526 2 10K_5%_2 HYNIX_H5TQ1G63DFR_11C_FBGA_96P P1V5_GPUS 0.1UF_16V_2 1 C5546 1uF_6.3V_2 1 C5547 1 1 1 0.1UF_16V_2 C5548 1uF_6.3V_2 2 0.1UF_16V_2 C5549 2 0.1UF_16V_2 C5550 2 0.1UF_16V_2 C5551 2 1uF_6.3V_2 C5552 2 C5553 2 2 1uF_6.3V_2 1 C5554 1 0.1UF_16V_2 2 A C5556 1 0.1UF_16V_2 2 0.1UF_16V_2 C5555 1 C5557 2 2 2 0.1UF_16V_2 1 C5558 1 P1V5_GPUS 1 1 0.1UF_16V_2 IN IN 69> FBA_CLK0_DP FBA_CLK0_DN 1 10K_5%_2 C5559 FBA_CMD<0> J7 K7 K9 R5524 R5528 DQL1 VDD#B2 1 R5527 B VSS#P1 1 FBA_CMD<28> 12 9 13 2 74< 73< 74<> 73<> 69> 6 3 7 0 4 2 5 1 73< A15 VSS#E1 FBA_DQS_DN<3> FBA_DQS_DN<0> FBA_D<6> FBA_D<3> FBA_D<7> FBA_D<0> FBA_D<4> FBA_D<2> FBA_D<5> FBA_D<1> 69<> 1 69<> 69<> FBA_DQS_DP<3> FBA_DQS_DP<0> FBA_DQM<3> FBA_DQM<0> D7 C3 C8 C2 A7 A2 B8 A3 FBA_D<0..7> BI A14 VDDQ#E9 69<> 69<> 26 27 24 30 28 31 25 29 A4 VDD#B2 12 9 13 FBA_D<26> FBA_D<27> FBA_D<24> FBA_D<30> FBA_D<28> FBA_D<31> FBA_D<25> FBA_D<29> N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 1 7 20 4 14 17 6 26 3 1 10 21 5 22 18 29 30 DQL3 E3 F7 F2 F8 H3 H8 G2 H7 VREFCA 2 H1 M8 IN 69<> FBA_CMD<7> FBA_CMD<20> FBA_CMD<4> FBA_CMD<14> FBA_CMD<17> FBA_CMD<6> FBA_CMD<26> FBA_CMD<3> FBA_CMD<1> FBA_CMD<10> FBA_CMD<21> FBA_CMD<5> FBA_CMD<22> FBA_CMD<18> FBA_CMD<29> FBA_CMD<30> 2 FBA_CMD<30..0> FBA_VREF0 DQL0 DQL2 7 20 4 14 17 6 26 3 1 10 21 5 22 18 29 30 2 73< VREFDQ BI FBA_D<24..31> BI H1 M8 IN A P1V5_GPUS P1V5_GPUS 1 1 R5505 74< FBA_VREF1 1.1K_1%_2 IN R5500 C5503 INVENTEC 2 0.01UF_50V_2 1.1K_1%_2 0.01UF_50V_2 2 2 1.1K_1%_2 1 C5501 1 1 R5504 2 IN 2 1 FBA_VREF0 2 R5501 1.1K_1%_2 EVEREST-M VRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:52 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 73 97 of 1 REV A01 8 7 6 5 4 3 2 1 U5503 74< FBA_CMD<30..0> U5502 H1 M8 IN VREFDQ DQL0 VREFCA DQL1 DQL2 BI 22 4 20 9 6 17 3 26 1 5 19 10 7 29 18 13 FBA_CMD<22> FBA_CMD<4> FBA_CMD<20> FBA_CMD<9> FBA_CMD<6> FBA_CMD<17> FBA_CMD<3> FBA_CMD<26> FBA_CMD<1> FBA_CMD<5> FBA_CMD<19> FBA_CMD<10> FBA_CMD<7> FBA_CMD<29> FBA_CMD<18> FBA_CMD<13> DQL3 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 FBA_CMD<12> FBA_CMD<14> FBA_CMD<30> C 74< 74< A5 27 FBA_CMD<27> 16 11 24 8 21 FBA_CMD<16> FBA_CMD<11> FBA_CMD<24> FBA_CMD<8> FBA_CMD<21> FBA_CLK1_DP FBA_CLK1_DN IN IN A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 J7 K7 K9 K1 L2 J3 K3 L3 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#E9 69<> 69<> FBA_DQS_DP<5> FBA_DQS_DP<7> FBA_DQM<5> FBA_DQM<7> 69<> 69<> FBA_DQS_DN<5> FBA_DQS_DN<7> VDDQ#F1 BI BI F3 C7 DQSL VDDQ#H2 DQSU VDDQ#H9 BI BI E7 D3 DML VSS#A9 DMU VSS#B3 VSS#E1 VSS#G8 G3 B7 BI BI DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 VSS#M9 B 74< 73< 74<> 73<> 69> FBA_CMD<28> VSS#P1 T2 IN 44 43 46 45 41 42 47 40 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D<58> FBA_D<59> FBA_D<56> FBA_D<62> FBA_D<57> FBA_D<60> FBA_D<61> FBA_D<63> 58 59 56 62 57 60 61 63 VSS#P9 RESET# VSS#T1 L8 VSS#T9 1 ZQ 69<> FBA_D<56..63> BI P1V5_GPUS B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5A 2 VSSQ#D1 VSSQ#D8 VSSQ#E2 J1 L1 J9 L9 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 VREFCA DQL1 DQL3 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 M2 N8 M3 69> 27 FBA_CMD<27> 16 11 24 8 21 FBA_CMD<16> FBA_CMD<11> FBA_CMD<24> FBA_CMD<8> FBA_CMD<21> IN IN FBA_CLK1_DP FBA_CLK1_DN J7 K7 K9 K1 L2 J3 K3 L3 69<> 69<> A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_DQS_DP<4> FBA_DQS_DP<6> FBA_DQM<4> FBA_DQM<6> 69<> 69<> A5 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#F1 F3 C7 DQSL VDDQ#H2 DQSU VDDQ#H9 BI BI E7 D3 DML VSS#A9 DMU VSS#B3 BI BI G3 B7 DQSL# VSS#J2 DQSU# VSS#J8 VSS#E1 VSS#G8 VSS#M1 VSS#M9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 74< 73< 74<> 73<> 69> FBA_CMD<28> IN FBA_D<35> FBA_D<36> FBA_D<32> FBA_D<38> FBA_D<33> FBA_D<39> FBA_D<34> FBA_D<37> 35 36 32 38 33 39 34 37 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D<51> FBA_D<52> FBA_D<48> FBA_D<54> FBA_D<50> FBA_D<55> FBA_D<49> FBA_D<53> 51 52 48 54 50 55 49 53 BI FBA_D<32..39> 69<> BI FBA_D<48..55> 69<> D P1V5_GPUS A14 BI BI FBA_DQS_DN<4> FBA_DQS_DN<6> E3 F7 F2 F8 H3 H8 G2 H7 A4 VDDQ#E9 P1V5_GPUS VSS#P1 T2 RESET# L8 ZQ VSS#P9 VSS#T1 VSS#T9 B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5A P1V5_GPUS A1 A8 C1 C9 D2 E9 F1 H2 H9 C A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 R5523 VSSQ#B1 VSSQ#B9 243_1%_2 VSSQ#D1 74< FBA_CLK1_DP 69> B1 B9 D1 D8 E2 E8 F9 G1 G9 74< 69> FBA_CLK1_DN 74<> 74<> 73<> 73<> 69> 69> VSSQ#D8 IN 2 VSSQ#B9 243_1%_2 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBA_CMD<12> FBA_CMD<14> FBA_CMD<30> 74< R5522 VSSQ#B1 DQL0 VDD#B2 12 14 30 A14 M2 N8 M3 69> 69> FBA_D<44> FBA_D<43> FBA_D<46> FBA_D<45> FBA_D<41> FBA_D<42> FBA_D<47> FBA_D<40> A4 VDD#B2 12 14 30 E3 F7 F2 F8 H3 H8 G2 H7 69<> FBA_CMD<22> FBA_CMD<4> FBA_CMD<20> FBA_CMD<9> FBA_CMD<6> FBA_CMD<17> FBA_CMD<3> FBA_CMD<26> FBA_CMD<1> FBA_CMD<5> FBA_CMD<19> FBA_CMD<10> FBA_CMD<7> FBA_CMD<29> FBA_CMD<18> FBA_CMD<13> 1 FBA_CMD<30..0> FBA_VREF1 VREFDQ 2 D 73< IN DQL2 22 4 20 9 6 17 3 26 1 5 19 10 7 29 18 13 1 74< FBA_VREF1 H1 M8 BI FBA_D<40..47> BI 73< IN FBA_CMD<0> IN FBA_CMD<16> IN J1 L1 J9 L9 R5519 160_1%_2 1 R5521 VSSQ#E2 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 B HYNIX_H5TQ1G63DFR_11C_FBGA_96P 2 10K_5%_2 1 R5520 2 10K_5%_2 HYNIX_H5TQ1G63DFR_11C_FBGA_96P 1 1uF_6.3V_2 A 2 1 1uF_6.3V_2 C5532 2 0.1UF_16V_2 C5533 1 1 C5534 2 0.1UF_16V_2 2 0.1UF_16V_2 C5535 1 1 C5536 2 0.1UF_16V_2 2 0.1UF_16V_2 C5537 1 C5538 2 1uF_6.3V_2 1 C5539 2 1uF_6.3V_2 1 C5540 2 0.1UF_16V_2 1 1 C5541 2 0.1UF_16V_2 2 0.1UF_16V_2 C5542 2 0.1UF_16V_2 C5543 1 C5544 1 P1V5_GPUS 2 0.1UF_16V_2 2 C5545 A 1 P1V5_GPUS INVENTEC EVEREST-M VRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:53 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 74 97 of 1 REV A01 8 7 6 5 4 3 2 1 U5505 FBC_VREF0 75< FBC_CMD<30..0> U5504 VREFCA DQL1 DQL2 BI D N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL3 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 75< 75< C M2 N8 M3 FBC_CMD<12> FBC_CMD<9> FBC_CMD<13> 69> 69> 0 FBC_CMD<0> 25 2 24 8 19 FBC_CMD<25> FBC_CMD<2> FBC_CMD<24> FBC_CMD<8> FBC_CMD<19> IN IN FBC_CLK0_DP FBC_CLK0_DN J7 K7 K9 K1 L2 J3 K3 L3 A5 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 FBC_DQM<0> FBC_DQM<3> A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#F1 BI BI F3 C7 DQSL VDDQ#H2 DQSU VDDQ#H9 BI BI E7 D3 DML VSS#A9 DMU VSS#B3 VSS#E1 FBC_DQS_DN<0> FBC_DQS_DN<3> G3 B7 BI BI VSS#G8 DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 VSS#M9 1 IN B FBC_D<24> FBC_D<27> FBC_D<31> FBC_D<28> FBC_D<29> FBC_D<26> FBC_D<30> FBC_D<25> VSS#P1 T2 RESET# L8 ZQ VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 243_1%_2 VSSQ#D1 2 2 10K_5%_2 VSSQ#D8 J1 L1 J9 L9 VSSQ#E2 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 DQL1 FBC_D<0..7> 69<> FBC_D<24..31> 69<> FBC_CMD<7> FBC_CMD<20> FBC_CMD<4> FBC_CMD<14> FBC_CMD<17> FBC_CMD<6> FBC_CMD<26> FBC_CMD<3> FBC_CMD<1> FBC_CMD<10> FBC_CMD<21> FBC_CMD<5> FBC_CMD<22> FBC_CMD<18> FBC_CMD<29> FBC_CMD<30> DQL3 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 12 FBC_CMD<12> 9 FBC_CMD<9> 13 FBC_CMD<13> P1V5_GPUS 75< 75< 1.5A P1V5_GPUS 69> 69> A5 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 A15 0 FBC_CMD<0> 25 2 24 8 19 FBC_CMD<25> FBC_CMD<2> FBC_CMD<24> FBC_CMD<8> FBC_CMD<19> VDD#D9 FBC_CLK0_DN BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 J7 K7 K9 IN IN K1 L2 J3 K3 L3 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#E9 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBC_DQS(2) FBC_DQS(1) BI BI F3 C7 FBC_DQM(2) FBC_DQM(1) BI BI E7 D3 FBC_DQSN(2) FBC_DQSN(1) BI BI VDDQ#F1 DQSL VDDQ#H2 DQSU VDDQ#H9 DML VSS#A9 DMU VSS#B3 VSS#E1 VSS#G8 G3 B7 DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 VSS#M9 IN FBC_CMD<28> FBC_D<18> FBC_D<16> FBC_D<20> FBC_D<17> FBC_D<23> FBC_D<19> FBC_D<22> FBC_D<21> 18 16 20 17 23 19 22 21 D7 C3 C8 C2 A7 A2 B8 A3 FBC_D<13> FBC_D<11> FBC_D<14> FBC_D<8> FBC_D<12> FBC_D<10> FBC_D<15> FBC_D<9> 13 11 14 8 12 10 15 9 BI FBC_D<16..23> BI FBC_D<8..15> VSS#P1 T2 RESET# L8 ZQ VSS#P9 VSS#T1 VSS#T9 69<> 69<> D P1V5_GPUS A14 M2 N8 M3 FBC_CLK0_DP E3 F7 F2 F8 H3 H8 G2 H7 A4 VDD#B2 B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5A P1V5_GPUS A1 A8 C1 C9 D2 E9 F1 H2 H9 C A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 R5518 VSSQ#B1 VSSQ#B9 243_1%_2 VSSQ#D1 75< 69> R5517 R5515 24 27 31 28 29 26 30 25 B2 D9 G7 K2 K8 N1 N9 R1 R9 1 FBC_CMD<28> 76< 75< 76<> 75<> 69> D7 C3 C8 C2 A7 A2 B8 A3 BI A14 VDDQ#E9 FBC_DQS_DP<0> FBC_DQS(3) BI 3 6 0 7 1 4 2 5 A4 VDD#B2 12 9 13 FBC_D<3> FBC_D<6> FBC_D<0> FBC_D<7> FBC_D<1> FBC_D<4> FBC_D<2> FBC_D<5> 7 20 4 14 17 6 26 3 1 10 21 5 22 18 29 30 1 FBC_CMD<7> FBC_CMD<20> FBC_CMD<4> FBC_CMD<14> FBC_CMD<17> FBC_CMD<6> FBC_CMD<26> FBC_CMD<3> FBC_CMD<1> FBC_CMD<10> FBC_CMD<21> FBC_CMD<5> FBC_CMD<22> FBC_CMD<18> FBC_CMD<29> FBC_CMD<30> 7 20 4 14 17 6 26 3 1 10 21 5 22 18 29 30 E3 F7 F2 F8 H3 H8 G2 H7 VREFCA 2 IN DQL0 DQL0 DQL2 B1 B9 D1 D8 E2 E8 F9 G1 G9 FBC_CLK0_DP 75< 69> VSSQ#D8 IN 1 FBC_CMD<30..0> FBC_VREF0 VREFDQ VREFDQ BI 2 75< H1 M8 H1 M8 IN FBC_CLK0_DN 160_1%_2 IN R5516 76<> 75<> 69> VSSQ#E2 J1 L1 J9 L9 R5514 FBC_CMD<25> 1 IN NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 B HYNIX_H5TQ1G63DFR_11C_FBGA_96P 2 10K_5%_2 HYNIX_H5TQ1G63DFR_11C_FBGA_96P P1V5_GPUS A C5518 1 1uF_6.3V_2 2 1uF_6.3V_2 1 1 C5519 2 0.1UF_16V_2 2 0.1UF_16V_2 C5520 1 C5521 2 0.1UF_16V_2 1 C5522 2 0.1UF_16V_2 1 1 1 1 0.1UF_16V_2 C5523 2 1uF_6.3V_2 2 1uF_6.3V_2 2 0.1UF_16V_2 C5525 C5524 2 C5526 1 C5527 2 0.1UF_16V_2 1 C5528 2 0.1UF_16V_2 1 C5529 2 0.1UF_16V_2 1 C5530 2 0.1UF_16V_2 2 C5531 1 P1V5_GPUS A P1V5_GPUS R5506 1.1K_1%_2 C5502 0.01UF_50V_2 1 R5507 INVENTEC 2 1.1K_1%_2 IN 1 FBC_VREF1 2 0.01UF_50V_2 76< 1 C5500 2 1.1K_1%_2 2 R5502 1 IN 2 2 1.1K_1%_2 FBC_VREF0 1 R5503 1 P1V5_GPUS EVEREST-M VRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:54 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 75 97 of 1 REV A01 8 7 FUSE6000 65W-75W 8A(6036A0003401) 90W 10A(6036A0002901) 120W 12A(6036A0006001) 6 5 4 3 2 PVADPTR PVBAT 2 2 3 4 R6017 1 R6019 2 R6018 0.1uF_16V_2_DY C6003 2 33K_5%_2_DY D R6000 2 RSC_0603_DY 1 OUT 1 HW_V_ADC 1 C6033 8A_125V 10PF_50V_2 ACES_91302_0047L_1_4P 1 2 2 G2 1000PF_50V_2 4 C6035 3 1 1 2 3 4 1 G2 FUSE6000 2 1 G1 1 CN6000 G1 NFE31PT222Z1E9L RSC_0603_DY L6001 2 1 1 D 2 4.7K_5%_3 R6005 1 2 RSC_0603_DY D6000 2 1M_5%_3 2 1 2 0.1uF_25V_3 1 NMOS_4D3S 1 TPCA8065_H PAD6000 2 POWERPAD_2_0610 D6001 1 A1 2 A2 C BAT54C_30V_0.2A C6012 2 1 20.5K_1%_2 0.1UF_16V_2 1 0.047uF_16V_2 1 2 C6000 4.7UF_25V_5 CSC0805_DY 1 3 B 2 4 PCMC063T_4R7MN 2 1 4.7UF_25V_5 C6023 2 C6019 2 C6004 2 2 C6021 2 0.1UF_25V_3 0.1UF_25V_3 4.7UF_25V_5 1 C6016 1 1 2 C6020 4.7UF_25V_5 1 1 1 0.1UF_16V_2 CSC0805_DY 2.2_5%_3 1 1 2 110K_1%_2 VRCHARGER_LG C6022 2 0.0015uF_50V_2 R6004 SBR3U40P1_DY D6003 2 4 3 2 1 2 1UF_10V_2 C6017 1 BAT54C_30V_0.2A 1 A2 Q6001 C6009 5 6 7 8 A1 2 1 R6014 2 R6001 2 0.01_1%_6 11 12 13 14 15 1 3 1 2 1 SSM3K7002FU_DY 1 2 A 10_1%_2 0.1UF_16V_2 High 2 G C6011 1 30.1K_1%_2 D 2 Q6004 R6011 Active IN 1 1 R6009 S CHG_EN 10K_5%_3_DY 2 R6021 1 WS C6001 L6000 1 S A 2 C6006 2 D6002 P3V3_AL P3V3_AL 4.7UF_25V_5 2 C6005 470pF_50V_2 1 C6002 2 1 5 6 7 8 4 3 2 1 VRCHARGER_PH 3 CSC0402_DY 1 2 C6027 1 2 CSC0402_DY C6029 1 100pF_50V_2 C6008 2 1 CSC0402_DY C6026 2 CSC0603_DY 1 C6028 2 REGN VRCHARGER_HG D 3.3K_1%_3 BTST ILIM 1 G OUT HIDRV SCL 20 19 18 17 16 1UF_25V_3 NMOS_4D3S EC_SMB2_CLK PHASE SDA 2 AON7410 OUT VCC IOUT LODRV GND SRP SRN BATDRV EC_SMB2_DATA ACDET 21 C OUT B 1 10_5%_5 2 R6015 1 5 4 3 2 1 HW_I_ADC 6 7 8 9 10 S ACN ACP CMSRC ACDRV ACOK C6015 TML R6013 D Low G Active NMOS_4D3S OUT U6000 ACPRES# TI_BQ24725RGRR_QFN_20P 2 Q6000 1 1 2 R6007 4.02K_1%_3 4.02K_1%_3 AON7410 WS 10K_5%_3 R6006 R6008 2 R6012 1 2 P3V3_AL 2 G C6024 1 2 3 4 C R6023 1 S 3 RSC_1206_DY 3 2 0.1UF_25V_3 D 2 2 DIODES_BAV99 1 PVADPTR 2 1 2 1 2 2200pF_50V_2 R6003 2 1 2 RSC_1206_DY C 2 1 C6007 C6010 1 0.1UF_25V_3 0.1UF_25V_3 AM4410NC AM4410NC CSC0805_DY C6014 NMOS_4D3S 68UF_25V G NMOS_4D3S Q6005 8 7 6 5 1 D + G S 10.01_1%_6 2 3 4 8 7 6 5 C6018 S 1 2 3 4 1 D C6025 R6020 Q6002 1 2 3 4 1 Q6003 8 7 6 5 C6013 PVADPTR R6002 PVPACK PVBAT R6010 1 2 6.98_1%_2 2 R6016 1 4.02K_1%_3 INVENTEC TITLE MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 76 97 of 1 REV X01 8 7 6 5 4 3 PVPACK 2 1 FUSE6100 LITTLEFUSE_R451015_15A_65V 1 2 P5V_AL C6106 D R6110 1 R6109 2 715K_1%_2 D CN6100 1 2 3 4 5 6 7 8 9 2 360K_1%_2 102K_1%_3 R6100 1 R6101 1 33_5%_2 2 1 2 R6102 2 1 1 PHP_PESD5V0S1BB_SOD523_2P D6103 2 2 1 2 D6104 2 PHP_PESD5V0S1BB_SOD523_2P 1 2 D6106 2 C 1 1 1 D6101 EZJZ0V500AA D6100 EZJZ0V500AA 33_5%_2 PHP_PESD5V0S1BB_SOD523_2P 1K_5%_2 2 BI 1 1 BI EC_SMB1_DATA EC_SMB1_CLK OUT 2 2 BATT_IN R6108 1 2 1000PF_50V_2 1 BATT+ BATT+ ID B-I TS SMD G SMC G GND G GND G G1 G2 G3 G4 SYN_200045GR009G15JZR_9P C REMOVE ? P5V_AL P5V_AL P3V3_AL 2 1 PVBAT R6105 10K_5%_2 A2 BAT54C_30V_0.2A B 1 2 R6104 3 U6100 5 VSEN 4 510K_1%_2 IN VCC THRM_SHUTDWN# 1 R6103 100K_1%_2 2 2 D6102 1 2 1K_5%_2 GMT_G686LT11U_SOT23_5P EZJZ0V120JA_DY 1 0.1uF_16V_2 1 C6107 11 R6106 + MR GND 2 - RESET A1 D6105 1 2 3 OUT 2 C +V5AUXON CN6101 2 B PVRTC LOTES_AAA_BAT_059_P03_2P A A INVENTEC TITLE MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 77 97 of 1 REV X01 6 5 2 G 1 1 2 3 4 1 2 FDMC8884 R5 2 3 S 2 Q6202 SSM3K7002FU 1 1 2 1 3 Q6201 1 G S EC_PW_ON OUT 2 NC D1 3 SSM3K7002FU D 1 R3 2 CHECK G S 2 10K_5%_2 2 1 IN D 2 G 2200pF_50V_2 D 1 0_5%_2 1 20K_5%_2_DY +V5AUXON 2 2 POWERPAD_2_0610 Q1 R2 1 3 R6201 1 S C6211 100K_5%_2_DY R4 2 PAD6205 D NMOS_4D3S 1 2 0_5%_2_DY 1 R6202 1 IN 8 7 6 5 200_5%_2 EC_PW_ON# D 2 P3V3_A Q6200 WS R1 3 P3V3_AL R6200 CHECK 4 P15V_A P3V3_AL 10K_5%_2 1 P5V_AL 100K_5%_2 7 D 8 SSM3K7002FU C6218 2 1 2 2 SSM3K7002FU 0.047uF_16V_2 S G 2 D 1 R6210 120K_1%_2 Q6203 1 3 DIODE-BAT54-TAP-PHP C C PVBAT D6201 3 1 1 1 POWERPAD_2_0610 2 2 PAD6203 PAD6202 2 IN 1 1 +V5AUXON R6209 130K_1%_3 C A2 2 A1 1 BAT54C_30V_0.2A PVBAT 2 POWERPAD_2_0610 4.7UF_25V_5 1 C6214 2 4.7UF_25V_5 C6201 2 4.7UF_25V_5 2 1 1 C6203 5 6 7 8 C6206 1 1 2 1 + 330UF_6.3V 21 R6204 2 4 3 2 1 1 C6220 5 6 7 8 13 14 15 16 17 18 2 R6216 1 1 2 A P15V_A 2.2uF_25V_5 DIODES_BAV99 0_5%_3 D6202 2 1 2 2 C6224 1UF_25V_3 1 31 C6222 0.1UF_25V_2 1 C6223 0.1uF_16V_2 2 2 0_5%_3 2 R6211 2 0.1uF_16V_2 1 10UF_6.3V_3 IN 1 C6215 1 +V5AUXON C6207 2 1 DIODES_BAV99 2 2 2 2 R6213 1UF_6.3V_2 POWERPAD1X1M D6203 1 1 1 2 RSC_0402_DY 3 AON7702L G 2 PAD6204 1 1 2 3 4 8 7 6 5 Q6205 S D C6208 1 2 3 4 + 330UF_6.3V 1 2 C6202 2 2 10K_1%_2 1 10K_5%_2 P5V_AL 2 2 R6206 1 2 R6212 +V3LDO PCMC063T_3R3MN 1 POWERPAD_2_0610 R6205 1 S 10K_1%_2 TI_TPS51123RGER_QFN_24P R6215 RSC_0402_DY G R6208 A P5V_A D R6207 6.8K_1%_2 1 V5A_LG AON7702L PCMC063T_3R3MN 2 C6200 DRVL1 PAD6200 L6200 1 V5A_SW 2 DRVL2 1 2 2200pF_50V_24.7_5%_3 G S AON7410 NMOS_4D3S D LL1 1 V5A_HG Q6207 POWERPAD_2_0610 2 6 5 4 3 2 1 25 8 7 6 5 2 2 Q6204 1 1 LL2 1 2 2 DRVH1 7A P5V_A 15.4K_1%_2 1 L6201 2 VBST1 U6200 DRVH2 ENC VREG5 VIN GND SKIPSEL EN0 1 PGOOD VBST2 C6213 0.1UF_25V_3 B S PAD6201 VREG3 D 1 V3LA_HG V3LA_SW V3LA_LG 24 23 22 21 20 19 Q6206 2 VO1 G 0.1UF_25V_3 VO2 NMOS_4D3S P3V3_AL 7 8 9 10 11 12 C6212 AON7410 10A TRIP1 VFB1 VREF TONSEL VFB2 ENTRIP2 4.7UF_25V_5 4.7UF_25V_5 TML C6204 C6205 3.8A 4 3 2 1 4A B 0.22UF_6.3V_2 C6209 1 2 P2V INVENTEC TITLE MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 78 97 of 1 REV X01 8 7 6 5 4 3 2 1 PVBAT 1 22A PAD6300 P1V5 1 P5V_A 2 P0V75_S POWERPAD_2_0610 6 2 VREF DRVL 10 PGOOD 20 VLDOIN 2 1 1 2200pF_50V_2 VTT 3 VTTSNS 1 C6310 19 MODE VTTGND 4 18 TRIP VTTREF 5 1 0.22uF_6.3V_2 2 VOUT=(1.8*R2)/(R1+R2) C6304 TI_TPS51216RUKR_QFN_20P 2 75K_1%_2 21 TML 1 100K_5%_2 R6305 2 2 R6304 1 C P0V75_VREF_M 1 2 2 2 52.3K_1%_2 C6302 GND 10uF_6.3V_3 C6301 7 C6303 1 1 0.1uF_10V_2 0.01uF_50V_2 R6302 C 560UF_2.5V 2 1 REFIN + 8 2 2 C6306 2 9 1 POWERPAD_2_0610 PCMC104T_1R0MN R6307 PAD6302 1 S VDDQSNS 2 4 4.7_5%_3 G 10K_1%_2 L6300 1 3 1 Q6301 TPCA8A02_H VR15_LG PGND 2 4 3 2 1 0.1UF_25V_3 S5 11 D POWERPAD_2_0610 1 1 R6303 2.2_5%_3 VR15_HG VR15_PH 16 0_5%_2 2 2 21 2 13 1 2 5 6 7 8 1 R6301 IN SW S3 C6305 1 4 3 2 1 2 14 2 D 1 DRVH R6306 1 2 1 1 2 IN 17 15 PAD6301 1 4.7UF_25V_5 4.7UF_25V_5 S 0_5%_2 R6300 VBST C6309 C6308 4.7UF_25V_5 G CHECK V5IN D U6300 12 C6307 NMOS_4D3S POWERPAD_2_0610 2.2uF_6.3V_3 D Q6300 TPCA8065_H 2 C6300 1 2 3.7A 5 6 7 8 PAD6310 2 1 2 3.7A 1 PVBAT B B P3V3_S 1 VCC FB 4 5 EN REF 2 L6340 1 2 2 13K_1%_2 GND 3 1 PGND 6 R6342 C6343 5.1K_1%_2 2 2 C6344 22UF_6.3V_5 10K_1%_2 2 R6343 1 2 C6342 0.1UF_16V_2 R1 C6345 2 C6341 1 1 1 2 PAN_ELL5PR2R2N 1 A 1 AON7702L 2 1 1 1 VR18_PH 2 LX TML 1 VIN PAD6340 POWERPAD_2_0610 CSC0402_DY 8 9 7 2 2 10UF_6.3V_3 2 1 1 4.7UF_25V_5 2 U6340 1 2200pF_50V_2 4 3 2 1 C6357 + 2 2 2 GMT_G5694F11U_SOP_8P CSC0402_DY C6353 1uF_10V_2 1 POWERPAD_2_0610 R6355 21 11 C6351 200K_1%_2 1 4.7_5%_3 1 1 2 2 PCMC063T_3R3MN S 2 R6352 PAD6351 L6350 2 R6354 Q6351 G CSC0402_DY 110K_1%_2 1 1 C6350 R6351 2 1 TI_TPS51218DSCR_SON_10P A 1 1 2 4 3 2 1 VRVCCP_HG VRVCCP_PH VRVCCP_LG P1V8_S AON7410 2 0.1UF_16V_2 DRVL 2 1 D RF V5IN 2.2_5%_3 2 SW VFB 1 C6340 P1V05_VCCPS 1 EN 10 9 8 7 6 5 6 7 8 DRVH GND 0_5%_2 2 R6350 1 VBST TRIP C6356 R6340 S PGOOD 0.1UF_25V_3 G 1 2 3 4 5 C6352 R6353 C6355 4.7UF_25V_5 D NMOS_4D3S P5V_A U6350 C6354 4.7UF_25V_5 Q6350 1 5 6 7 8 IN 10_5%_3 R6341 2 +V1.05S_VCCP_EN 10K_5%_2 PAD6350 POWERPAD_2_0610 2 2 1 P5V_A R6356 INVENTEC 2 2 330UF_6.3V R2 VOUT=(1+R1/R2)*0.7 10K_1%_2 TITLE 1 MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 79 97 of 1 REV X01 8 1 IN 4 3 2 1 PVBAT 2 1 R6400 0_5%_2 R6401 5 PAD6400 2 1 100K_5%_2_DY 2 2 C6400 P3V3_S R6403 1K_5%_2 POWERPAD_2_0610 16 15 14 13 PGOOD MODE EN BST REFIN DH 11 VRVCCIO_HG 3 GSNS DL 10 VRVCCIO_LG 4 VSNS V5 9 1 NEW PVCCIO TPCA8065_H 4 3 2 1 2 C6407 4.7UF_25V_5 1 3 5 6 7 8 VRVCCIO_PH L6400 PAD6401 1 2 4 1 2 2 POWERPAD_2_0610 ETQP4LR36AFM 2 Q6401 R6408 P5V_A PGND GND 2 TRIP COMP C6402 1 4 3 2 1 1 560UF_2.5V 22UF_6.3V_5 2 1 1 2 2 2 1UF_10V_2 86.6K_1%_2 C6410 C6409 CSC0402_DY + 1 1 8 5 2 C6408 TPCA8A02_H C6403 R6406 C S 0.01UF_50V_2 2 2 POWERPAD_2_0610 11 1 G 2 PAD6402 1 RSC_0603_DY 7 1 R6405 0_5%_2_DY C 12 6 1 2 IN VCCIO_SEL SW C6406 4.7UF_25V_5 D IN VREF C6405 4.7UF_25V_5 S VCCIO_SENSE 1 D IN 10K_5%_2 Q6400 G 2.2UF_10V_3 VSS_SENSE_VCCIO 2 1 NMOS_4D3S C6401 1 R6404 2 0.1UF_25V_3 0_5%_3 TI_TPS51219RTER_QFN_16P U6400 P3V3_A 2 2 17 PWPD 1 VTT_PG OUT C6404 R6407 1 5 6 7 8 10K_5%_2 2 1 R6402 D 1 1 2 2 100PF_50V_2_DY 2 D 2 SLP_S3#_5R 1 IN 6 1 1.5S_CPU_PG 7 1 C6433 2 C6434 R6430 1 2 0.01UF_50V_2 5.11K_1%_2 1 2 3300PF_50V_2 B C6435 IN 1 R6431 2 P0V85_S RSC_0402_DY SW PGND BST 1 1 R6433 18 17 16 15 14 13 1 1 C6437 R6434 2 0_5%_2 2 IN R6437 VTT_PG 2 2 1 C6442 C6443 C6444 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY RSC_0603_DY C6438 CSC0402_DY C6440 A CSC0402_DY 1UF_10V_2 2 1UF_10V_2 1 POWERPAD_2_0610 C6441 1 2 2 POWERPAD1X1M C6436 A 1 2 C6439 2 0.1UF_25V_3 0_5%_2 1 1 1 2 0_5%_3 1 2 PAD6430 R6432 1 PCMC063T_R33MN 2 SW PGND PAD6431 1 2 PGND 2 4 1 SW L6430 2 SW U6430 VIN 1 3 1 0.1UF_16V_2 VIN VRVCCSA_PH 7 8 9 10 11 12 2 10UF_10V_5 SW 1 10UF_10V_5 VIN 12 C6432 TI_TPS51461RGER_QFN_24P TML V5DRV V5FILT PGOOD VID1 VID0 EN C6431 2 C6430 2 25 24 23 22 21 20 19 1 1 1 GND VREF COMP SLEW VOUT MODE 2 P5V_A B WS WS 1 2 3 4 5 6 0.22UF_6.3V_2 VCCSA_SENSE IN 2 2 2 R6435 0_5%_2_DY IN VCCSA_VID1 VCCSA_VID0 P3V3_S 1 INVENTEC 2 R6436 10K_5%_2 TITLE OUT MODEL,PROJECT,FUNCTION VCCSA_PG Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 80 97 of 1 REV X01 8 7 6 5 4 3 2 1 1 VREF R6511 2 C6500 0.1UF_16V_2_DY PVBAT 1 R6512 2 2 C6505 1 33PF_50V_2 1 R6510 2 1 D PAD6500 POWERPAD_2_0610 VREF P5V_A CPGOOD CSW 1 45 2.2_5%_3 VCLK CDL1 44 V5DRV 43 N_C 42 PGND 41 1 CDH2 37 2.2_5%_3 2 1 2 4.7UF_25V_5 1 1 4.7UF_25V_5 1 2 4.7UF_25V_5 C6520 2 4.7UF_25V_5 C6519 1 1 2 1 R6543 2 2 L6501 5 6 7 8 R6536 1 21 560UF_2.5V C6521 2 CSC0402_DY 1 IN 2 4 3 2 1 C6534 470UF_2V + + C6533 R6528 2 2 INVENTEC 1 56K_1%_2 2 C6508 R6529 0.1UF_16V_2_DY TITLE MODEL,PROJECT,FUNCTION Block 2 1 2 100K_1%_NTC SIZE C CHANGE 7 PVCORE 2 28.7K_1%_2 100K_1%_NTC A 2 1 15.4K_1%_2 8.66K_1%_2 8 R6544 1 30K_5%_2 GPU_CSN2 IN GPU_CSP2 IN 17.8K_1%_3 2 VREF R6525 R6527 R6542 1 4 3 2 1 GPWM1 OUT GPWM2 OUT CPWM3 OUT 0_5%_2 2 0_5%_2 0_5%_2 2 2 GPU_CSN1 12 VR_ON 1 2 OUT GPU_CSP1 IN 1 1 100K_1%_2 20K_5%_2 1 S R6526 2 RSC_0603_DY G R6524 1 162K_1%_2 1 TPCA8057_H R6530 A B 0.033UF_16V_2 R6541 PAN_ETQP4LR36ZFC_4P 3 4 Q6503 OUT GSKIP VREF 2 2 1 R6523 0_5%_2_DY C6522 1 D 1 1 R6518 1 R6520 1 R6522 1 0_5%_2_DY OUT TPCA8065_H NMOS_4D3S 2 R6517 0_5%_2_DY 2 R6521 0_5%_2 1 R6516 2 1 R6519 0_5%_2_DY CPU_CSP2 S 2 G P3V3_A 2 4.7UF_25V_5 C6518 36 35 34 33 32 31 30 29 28 2 4.12K_1%_2 IN R6531 2 10K_5%_2 33PF_50V_2 R6515 2 1 MAIN_PWRGD 27 26 25 2 2 1 1 Q6502 D C6503 OUT POWERPAD_2_0610 NMOS_4D3S VREF 1 0.1UF_25V_2 PVBAT 0_5%_2_DY 0_5%_2_DY 1 VBAT CPWM3 GPWM2 GPWM1 GCSN2 GCSP2 R6509 2 CPU_CSN2 1 GGFB 38 C6510 2 24 GSKIP# CBST2 GTHERM GVFB GOCP_R 23 PAD6501 R6533 3 39 1 CSW2 1 GF_IMAX GCSP1 2 40 GCSN1 R6508 CDL2 GCOMP 30K_1%_2 GPGOOD 22 PVBAT 2 0_5%_2 2 1 1 R6507 1 VSSAXG_SENSE IN 21 TI_TPS51650RSLR_QFN_48P 2 R6506 1 VAXG_SENSE IN 1 R6505 B 0_5%_2 2 VR_HOT 5 6 7 8 +VGFX_PWRGD OUT R6504 1 200K_1%_2 2 VDIO VRCPU_LG2 VREF 19 20 P5V_A CSC0402_DY TPCA8057_H VRCPU_PH1 VRCPU_LG1 VRCPU_PH2 2 BI VR_SVID_DATA H_PROCHOT# OUT C6515 0.1UF_25V_2 VRCPU_HG2 1 2 U6500 2 + 16 1 C6509 1 3 2 R6532 6 C 470UF_2V 2 46 470UF_2V C6532 + CBST1 C6531 RSC_0603_DY 3 VR_ON VRCPU_HG1 2 15 ALERT# 1 1 47 18 2 21 CDH1 PVCORE 2 V3R3 IN 2 4 3 2 1 14 R6540 2 1 28.7K_1%_2 L6500 5 6 7 8 48 VR_SVID_ALRT# R6539 2 1 100K_1%_NTC S V5 17 2 D VREF IN R6538 1 17.8K_1%_3 R6535 Q6501 P5V_CPU 13 VR_SVID_CLK 2 1 4 3 2 1 49 G VR_PWRGD OUT 2.2UF_6.3V_3 2.2UF_6.3V_3 IN 1 162K_1%_2 2 2 GND 2 0.033UF_16V_2 R6537 PAN_ETQP4LR36ZFC_4P 3 4 NMOS_4D3S VR_ON C6502 C6501 C6511 1 1 2 3 4 5 6 7 8 9 10 11 12 2 CTHERM COCR-1 CCSP1 CCSN1 CCSN2 CCSP2 CCSP3 CCSN3 CCOMP CVFB C CGFB CF-IMAX P3V3_A C6516 1 S 24K_1%_2 4.7UF_10V_3 TPCA8065_H 2.2UF_10V_3 G R6503 VREF C6507 C6506 1 42.2K_1%_2 1 IN 10_5%_3 IN IN IN IN IN IN 1 IN D Q6500 2 2 NMOS_4D3S R6502 2 OUT 4.7UF_25V_5 C6514 R6534 1 2 15.4K_1%_2 CPU_CSP1 4.7UF_25V_5 C6513 1 P5V_CPU 4.7UF_25V_5 C6512 R6514 2 1 OUT 2 1 CPU_CSP1 CPU_CSN1 CPU_CSN2 CPU_CSP3 CPU_CSP2 VREF CPU_CSN3 VSSSENSE VCCSENSE 100K_1%_NTC C6517 1 8.45K_1%_2 CPU_CSN1 1 2 1 0.1UF_16V_2_DY R6513 2 75K_1%_2 5 6 7 8 C6504 1 2 VREF 2 R6501 1 130_1%_2 100K_1%_2 2 IN BI 2 D VR_SVID_CLK VR_SVID_DATA R6500 1 54.9_1%_2 1 PVTT 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 81 97 of 1 REV X01 8 7 6 5 4 3 2 1 1 PVBAT CPU_CSN3 OUT PW M VDD GND DRVL 1 1 4.7UF_25V_5 1 2 2 4.7UF_25V_5 R6548 2 1 17.8K_1%_3 R6549 2 R6550 2 1 28.7K_1%_2 100K_1%_NTC PVCORE 1 1 4 3 2 1 VRCPU_HG3 VRCPU_PH3 VRCPU_LG3 1 D C6524 Q6506 NMOS_4D3S P5V_A RSC_0603_DY C6529 S G CSC0402_DY 2 2 4 3 2 1 1UF_10V_2 C 2 L6502 R6546 21 SW SKIP# 4.7UF_25V_5 D 162K_1%_2 5 6 7 8 DRVH BST C6528 PAN_ETQP4LR36ZFC_4P 3 4 TPCA8057_H 1 2 3 4 CPWM3 IN 9 8 7 6 5 PAD C6527 2 0.033UF_16V_2 1 R6547 2 S U6501 4.7UF_25V_5 G P5V_CPU C6526 C6525 C6530 1 OUT CPU_CSP3 2 0.1UF_25V_2 2.2_5%_3 TI_TPS51601DRBR_SON_8P Q6505 2 2 D C6523 1 NMOS_4D3S 2 TPCA8065_H R6545 1 1 52 6 7 8 D POWERPAD_2_0610 1 2 1 PAD6503 C 1 PVBAT GPU_CSN1 OUT PAD6600 1 2 VDD GND DRVL VRAXG_LG1 1 C6601 1 1 1 2 17.8K_1%_3 2 2 2 2 R6603 1 4.7UF_25V_5 4.7UF_25V_5 4 3 2 1 3 1 Q6601 NMOS_4D3S P5V_A B 4.7UF_25V_5 162K_1%_2 1 R6604 2 1 R6605 2 28.7K_1%_2 100K_1%_NTC PVAXG 4 2 L6600 C6606 D PW M VRAXG_HG1 VRAXG_PH1 4.7UF_25V_5 R6602 2 1 C6605 C6604 B CSC0402_DY 21 SW C6603 PAN_ETQP4LR36ZFC_4P 5 6 7 8 DRVH SKIP# C6602 S BST R6601 S G TPCA8057_H 1 2 3 4 GSKIP# IN GPWM1 IN 9 8 7 6 5 G PAD U6600 2 0.033UF_16V_2 1 TI_TPS51601DRBR_SON_8P 1 52 6 7 8 2 0.1UF_25V_2 D 2 1 2.2_5%_3 Q6600 NMOS_4D3S 1 C6600 TPCA8065_H R6600 C6607 1 GPU_CSP1 OUT POWERPAD_2_0610 1UF_10V_2 2 2 4 3 2 1 RSC_0603_DY POWERPAD_2_0610 TI_TPS51601DRBR_SON_8P VDD GND DRVL VRAXG_LG2 1 1 2 1 1 2 1 2 100K_1%_NTC 1 2 A PVAXG 28.7K_1%_2 2 L6601 C6614 D 1 2 1 Q6603 NMOS_4D3S C6609 R6609 2 PAN_ETQP4LR36ZFC_4P 3 4 VRAXG_HG2 VRAXG_PH2 P5V_A 1 1 SW PW M 9 8 7 6 5 4.7UF_25V_5 4.7UF_25V_5 17.8K_1%_3 5 6 7 8 SKIP# DRVH 1 R6608 162K_1%_2 R6610 R6611 S BST CSC0402_DY INVENTEC R6607 S G TPCA8057_H GSKIP# IN GPWM2 IN 1 2 3 4 0.033UF_16V_2 C6613 C6612 4.7UF_25V_5 4.7UF_25V_5 G PAD U6601 C6611 C6610 2 0.1UF_25V_2 A Q6602 2 2 2 21 C6608 NMOS_4D3S 2.2_5%_3 1 D 2 C6615 1 GPU_CSP2 OUT 4 3 2 1 R6606 TPCA8065_H 1 GPU_CSN2 OUT PAD6601 52 6 7 8 2 1 1 PVBAT TITLE 1UF_10V_2 RSC_0603_DY Block 2 2 4 3 2 1 MODEL,PROJECT,FUNCTION SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 82 97 of 1 REV X01 8 7 6 5 4 3 2 1 1 PVBAT PAD6702 1 2 D D POWERPAD_2_0610 2 Sch 4 VFB 5 TRAN C6705 1 C6708 2 1 1 C C6707 + + 2 470UF_2V SBR3U40P1 2 R6702 10.2K_1%_2 2 47pF_50V_2 1 1 C6703 1 C6709 2 4 3 2 1 2 C6706 CSC0402_DY 11 1 2 2 D6700 S 1 D 2 1 470UF_2V 4 VRGPU_LG Q6702 1 2 3 4 1 2 3 75K_1%_2 PAD6701 POWERPAD_2_0610 PAN_ETQP4LR36WFC_4P G R6704 1K_1%_2 S 2 I80 G 1uF_10V_2 Q6701 D 2 C6701 1 1 6 2 4 2 DRVL L6700 5 6 7 8 7 4 3 2 1 V5IN 1 3 2 VRGPU_SW 4 3 2 1 VRGPU_HG 8 2 2 B 1 B R6706 20K_1%_2 2 R6701 68K_1%_2 R6708 2 3 1 10K_5%_2 WS 2 1 1 CHECK 2 P3V3_S R7 C1 D Q2 100PF_50V_2 G CHECK A SSM3K7002FU 1 WS VID1 2 P3V3_S 40.2K_1%_2 2 1 IN S POW_SW0 R6 2 3 10K_5%_2 WS VID0 +VDDC_GPU POW_SW1 POW_SW0 PCORE_GPU 1 1 9 SW R6703 1UF_6.3V_2 CSC0402_DY DRVH EN 1 8 7 6 5 1 C6801 TRIP 3 PAD6700 POWERPAD_2_0610 8 7 6 5 C C6702 1 5 6 7 8 0_5%_2 2 1 10K_5%_2 VBST 2 IN 2 2 R6801 10K_5%_2 1 EC_DGPU_PWR_EN 2 4.7UF_25V_5 2 PGOOD GND R6705 2 4.7UF_25V_5 0.1UF_25V_3 21 10 TSB_TPCA8057_H_8P 0 0 1.05V 0 1 1.00V 1 0 0.90V A For XT For PRO D Q3 POW_SW1 1 IN G VID1 S 1 R6802 2.2_5%_3 1 TSB_TPCA8057_H_8P IN 1 OUT C6700 R6700 1 4.7UF_25V_5 PVCORE_GPU S VDDC_GPU_PG WS SLP_S3#_3R U6700 TI_TPS51217DSCR_SON_10P TPCA8065_H 2 D 1 G 10K_5%_2 P5V_A NMOS_4D3S R6707 C6704 Q6700 CHECK 2 5 6 7 8 P3V3_S P5V_A 1 3.5A 1 30A WS SSM3K7002FU VID0 +VDDC_GPU POW_SW1 POW_SW0 PCORE_GPU 2 Original 0 1 1.00V 1 0 0.90V INVENTEC TITLE MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by 8 7 6 5 4 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 83 97 of 1 REV X01 8 7 6 CONFIGURATION STRAPS STRAPS: PIN DESCRIPTION TX_PWRS_ENB GPIO_0 TX_DEEMPH_EN GPIO_1 Tx Tx RESERVED GPIO_2 RESERVED GPIO_8 RESERVED GPIO_21 BIF_VGA DIS Pin-Based De-emphasis De-emphasis VGA controller VGA controller GPIO_9 swing=1 swing=0 enabled=1 disabled=0 Disable Enable CONFIG[2] CONFIG[1] CONFIG[0] GPIO_13 GPIO_12 GPIO_11 If GPIO_22 = 0, memory-aperture AUD[0] HSYNC AUD[1] VSYNC AUD 0 0 0 1 1 0 1 1 the the enabled=0 disabled=1 BIOS BIOS then size. during is left D ROM device=0 ROM device=1 CONFIG [2:0] Default is (Default) defines 0 0 1 the primary C HDMI, if dongle is and HDMI. (Default detected is 1 1) reset unconnected (7A) P1V8_GPUS P15V_A P1V5_GPUS P1V5 1 P1V8_S on=0 on=1 (Default) (2.012A) P3V3_A 1 Whistler (Default) [1:0]: = No audio function = Audio for DisplayPort only = Audio for DisplayPort and = Audio for both DisplayPort Must be low PCB default GENLK_CLK external external 2 GPU (Default) capacity capacity GPIO_22 C 3 Straps Advertises the PCIe device as 2.5 GT/s capable at power Advertises the PCIe device as 5.0 GT/s capable at power (ASIC Internal pull down, and PCB Default is 0) Must be low during reset PCB default is left unconnected Must be low during reset (PCB default is 0) Voltage control signal for the memory-voltage regulator. BIOS_ROM_EN RESERVED 4 OF DEFAULT SETTINGS Full Tx output 50% Tx output D 5 560K_1%_2 R5516 G 1 3 NMOS_4D1S 2 S D G NMOS_4D3S 0_5%_2_DY 3 8 7 6 5 B C5118 2.2uF_6.3V_3 FDMC7692 P3V3_S P3V3_GPUS G Q5112 SSM3K7002FU 2 C5116 0.01uF_50V_2 2 2 3 C5120 P3V3_A 2 2 P15V_A 1 R5115 1 DGPU_PWR_EN# IN 560K_1%_2 200_5%_2 D 3 1 2 Q5122 G 10K_5%_2 SSM3K7002FU 2 2 100K_5%_2 1 R5111 2 2 A 68pF_50V_2 C5108 1 R5119 R5123 S SSM3K7002FU 1 2 Q5105 0.1uF_16V_2 G AM2321P G 1 D 1 S VDDC_GPU_PG IN 3 Q5121 1 S 1 1 D AM3402N 1 2 3 4 1 Q5117 R5114 2 2.2uF_6.3V_3 4 2 1 C5107 2 1 100K_5%_2 2 R5106 68pF_50V_2 C5104 2 S S B D D 1 Q5110 1 2 5 6 1 R5517 A 2 0_5%_2 D 3 3 1 Q5109 S PX_MODE IN G G Q5113 S D 1 SSM3K7002FU SSM3K7002FU INVENTEC 2 2 BACO MODE TITLE MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 84 97 of 1 REV X01 8 7 WHISTLER WHISTLER 6 XT PRO TDP: 30~35 W TDP: 20~25 W PEG_TX0_DP PEG_TX0_DN BI BI AA38 Y37 PEG_TX1_DP PEG_TX1_DN BI BI PEG_TX2_DP PEG_TX2_DN 5 4 1 CLOSE TO GPU PCIE_RX0P PCIE_TX0P PCIE_RX0N PCIE_TX0N Y35 W36 PCIE_RX1P PCIE_TX1P PCIE_RX1N PCIE_TX1N BI BI W38 V37 PCIE_RX2P PCIE_TX2P PCIE_RX2N PCIE_TX2N PEG_TX3_DP PEG_TX3_DN BI BI V35 U36 PCIE_RX3P PCIE_TX3P PCIE_RX3N PCIE_TX3N PEG_TX4_DP PEG_TX4_DN BI BI U38 T37 PCIE_RX4P PCIE_TX4P PCIE_RX4N PCIE_TX4N PEG_TX5_DP PEG_TX5_DN BI BI T35 R36 PCIE_RX5P PCIE_TX5P PCIE_RX5N PCIE_TX5N PEG_TX6_DP PEG_TX6_DN BI BI R38 P37 PCIE_RX6P PCIE_TX6P PCIE_RX6N PCIE_TX6N PEG_TX7_DP PEG_TX7_DN BI BI P35 N36 PCIE_RX7P PCIE_TX7P PCIE_RX7N PCIE_TX7N PEG_TX8_DP PEG_TX8_DN BI BI N38 M37 PCIE_RX8P PCIE_TX8P PCIE_RX8N PCIE_TX8N PEG_TX9_DP PEG_TX9_DN BI BI M35 L36 PCIE_RX9P PEG_TX10_DP PEG_TX10_DN BI BI L38 K37 PCIE_RX10P PEG_TX11_DP PEG_TX11_DN BI BI K35 J36 PCIE_RX11P PEG_TX12_DP PEG_TX12_DN BI BI J38 H37 PCIE_RX12P PCIE_TX12P PCIE_RX12N PCIE_TX12N PEG_TX13_DP PEG_TX13_DN BI BI H35 G36 PCIE_RX13P PCIE_TX13P PCIE_RX13N PCIE_TX13N PEG_TX14_DP PEG_TX14_DN BI BI G38 F37 PCIE_RX14P PCIE_TX14P PCIE_RX14N PCIE_TX14N PEG_TX15_DP PEG_TX15_DN BI BI F35 E37 PCIE_RX15P PCIE_TX15P PCIE_RX15N PCIE_TX15N BI BI AB35 AA36 PCIE_RX9N PCIE_RX10N PCIE_RX11N PCI EXPRESS INTERFACE B 2 U5124 Y33 Y32 PEG_RX0_C_DP PEG_RX0_C_DN C5128 1 C5129 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX0_DP PEG_RX0_DN W33 W32 PEG_RX1_C_DP PEG_RX1_C_DN C5130 1 C5131 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX1_DP PEG_RX1_DN U33 U32 PEG_RX2_C_DP PEG_RX2_C_DN C5132 1 C5133 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX2_DP PEG_RX2_DN U30 U29 PEG_RX3_C_DP PEG_RX3_C_DN C5134 1 C5135 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX3_DP PEG_RX3_DN T33 T32 PEG_RX4_C_DP PEG_RX4_C_DN C5136 1 C5137 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX4_DP PEG_RX4_DN T30 T29 PEG_RX5_C_DP PEG_RX5_C_DN C5138 1 C5139 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX5_DP PEG_RX5_DN P33 P32 PEG_RX6_C_DP PEG_RX6_C_DN C5140 1 C5141 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX6_DP PEG_RX6_DN P30 P29 PEG_RX7_C_DP PEG_RX7_C_DN C5142 1 C5143 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX7_DP PEG_RX7_DN N33 N32 PEG_RX8_C_DP PEG_RX8_C_DN C5144 1 C5145 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX8_DP PEG_RX8_DN N30 N29 PEG_RX9_C_DP PEG_RX9_C_DN C5146 1 C5147 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX9_DP PEG_RX9_DN L33 L32 PEG_RX10_C_DP PEG_RX10_C_DN C5148 1 C5149 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX10_DP PEG_RX10_DN L30 L29 PEG_RX11_C_DP PEG_RX11_C_DN C5150 1 C5151 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX11_DP PEG_RX11_DN K33 K32 PEG_RX12_C_DP PEG_RX12_C_DN C5004 1 C5005 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX12_DP PEG_RX12_DN J33 J32 PEG_RX13_C_DP PEG_RX13_C_DN C5152 1 C5153 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX13_DP PEG_RX13_DN K30 K29 PEG_RX14_C_DP PEG_RX14_C_DN C5154 1 C5155 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX14_DP PEG_RX14_DN H33 H32 PEG_RX15_C_DP PEG_RX15_C_DN C5156 1 C5157 1 2 2 0.1UF_16V_2 0.1UF_16V_2 BI BI PEG_RX15_DP PEG_RX15_DN D C 3 PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N D C B CLOCK CLK_PEG_GPU_REF_DP CLK_PEG_GPU_REF_DN P1V0_GPU PCIE_REFCLKP PCIE_REFCLKN R5126 1.27K_1%_2 CALIBRATION P3V3_S R5003 2 AH16 PWRGOOD PCIE_CALRP Y30 1 2 PCIE_CALRN Y29 1 2 10K_5%_2 C5000 2 1 2K_1%_2 AA30 1 A R5127 PERSTB A 0.1UF_16V_2 AMD_216_0810_001_FCBGA_962P 5 IN 4 PEG_PLT_RST# 2 INVENTEC TC7SZ08FU R5125 100K_5%_2 GEN2: 2 3 1 - PLT_RST# 1 + DGPU_HOLD_RST# IN U5001 R5002 1 TITLE PCI EXPRESS BUS:TRANSMITTED/RECEIVER UP TO 5.0-GT/S BIT RATE. 2 0_5%_2_DY CHANGE 8 7 6 5 4 by 3 XXX DATE 21-OCT-2002 2 MODEL,PROJECT,FUNCTION Block SIZE C CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 SHEET 85 97 of 1 REV X01 7 6 DVPDATA_11 DVPDATA_12 TX0P_DPC2P DVPDATA_13 TX0M_DPC2N DVPDATA_14 DPC DVPDATA_15 TX1P_DPC1P TX1M_DPC1N DVPDATA_16 DVPDATA_17 DVPDATA_18 TX2P_DPC0P DVPDATA_19 TX2M_DPC0N DVPDATA_20 DVPDATA_21 TXCDP_DPD3P DVPDATA_22 TXCDM_DPD3N DVPDATA_23 TX3P_DPD2P TX3M_DPD2N SWAPLOCKA SWAPLOCKB DPD TX4P_DPD1P TX4M_DPD1N I2C R TML 11 SWING: 3.3V TP24 AN31 1 0.1UF_16V_2 C5027 1 1UF_6.3V_2 C5026 2 TP24 TP5031 THRM_GPU_DP IN THRM_GPU_DN IN THRM_SHUTDWN# OUT AV33 AU34 AVSSQ GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 VDD1DI GPIO_17_THERMAL_INT VSS1DI GPIO_19_CTF R2/NC GPIO_20_PWRCNTL_1 R2B/NC GPIO_21_BB_EN GPIO_22_ROMCSB G2/NC GPIO_23_CLKREQB JTAG_TRSTB G2B/NC JTAG_TDI JTAG_TCK B2/NC JTAG_TMS B2B/NC GENERICA C/NC GENERICB Y/NC GENERICC COMP/NC GENERICD GENERICE_HPD4 AW35 IN ASIC THRM_GPU_DP OUT THRM_GPU_DN OUT R5021 2 SMBCLK DXP SMBDATA DXN ALERT# GND 8 7 6 5 AF29 AG29 GPU_TS_FDO P1V8_GPUS 1 GPU_THM_CLK BI GPU_THM_DAT BI BI EC_SMB2_CLK EC_SMB2_DATA C5200 GPU_PS1 OUT L5186 2 I=0.005A OUT C5199 R5038 2 1 AG31 AG32 AG33 A2VDDQ/NC AD33 A2VSSQ/TSVSSQ AF33 R2SET/NC AA29 TSVDD AJ32 AJ33 FBM_11_160808_121T DDC1CLK DDC1DATA AUX1P XTALIN AUX1N XTALOUT DDC2DATA XO_IN AUX2P AUX2N XO_IN2 DDCCLK_AUX4P THERMAL DDCDATA_AUX4N 1 DDCDATA_AUX5N DDC6CLK DDC6DATA DDCCLK_AUX7P DDCDATA_AUX7N TSVDD C5205 1UF_6.3V_2 OUT 1 R5039 2 1 R5040 2 GPU_PS2 P3V3_GPUS 3.3V,0.13A GPU_PS1 IN GPU_PS2 IN GPU_PS3 IN 0_5%_3_DY OUT GPU_PS3 1 R5041 2 AM26 AN26 BI BI from noisy GND area. GPU_HDMI_DDCCLK GPU_HDMI_DDCDATA AM27 AL27 AM19 AL19 B AN20 AM20 BI BI GPU_EDP_AUX_DP GPU_EDP_AUX_DN BI BI GPU_CRT_DDCCLK GPU_CRT_DDCDATA FUTURE GPU Multi ASIC Level Straps feature AL29 AM29 AN21 AM21 AJ30 AJ31 AK30 AK29 TSVSS AMD_216_0810_001_FCBGA_962P A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by XXX BEN LEE 7 Pin AL30 AM30 GMT_G784_MSOP_8P 8 2 P1V8_GPUS Away PLL/CLOCK DPLL_VDDC TS_A/NC GND area. P1V8_GPUS 1 C5201 715_1%_2_DY DPLL_PVSS AL31 noisy FBM_11_160808_121T 0.1UF_16V_2 10UF_6.3V_3 AD29 AC29 DPLL_PVDD TS_FDO from L5207 AC32 AD32 AF32 A2VDD/NC VREFG AK32 Away 1 1.8V,0.1A HPD1 DMINUS 1UF_6.3V_2 I=0.045A VDD1D1 R5037 2 0_5%_2_DY C5204 0.1UF_16V_2 C H2SYNC/GENLK_CLK GENERICG_HPD6 DPLUS 2 DAC2 GENERICF_HPD5 DDCCLK_AUX5P BI C5198 AC30 AC31 AF30 AF31 1 FBM_11_160808_121T 10UF_6.3V_3 AD30 AD31 P1V8_GPUS L5042 I=0.07A 1 R5020 2 GND area. AVDD AC33 AC34 0_5%_2_DY DDCDATA_AUX3N future noisy AD34 AE34 JTAG_TDO DDCCLK_AUX3P GPU_TS_FDO MLPS option for from 2 GPIO_18_HPD3 DDC2CLK AW34 IN GPU_XOIN_27M_R GPU_XOIN2_100M_R 2 VCC THERM# AVDD GPIO_13 D OUT OUT 1 GPIO_12 TP24 U5018 1 2 3 4 1 1 TP5032 0_5%_2_DY 1 AM32 AN32 0.1UF_16V_2 2 AB34 GPU_CRT_HSYNC GPU_CRT_VSYNC Away R5195 499_1%_2 CRT 1 1 C5028 2 0.1UF_16V_2 1 1UF_6.3V_2 DPLL_PVDD C5188 1 0.1UF_16V_2 2200PF_50V_3 RSET GPIO_11 CLOSE TO GPU 249_1%_2 0_5%_2_DY 1 C5014 AC36 AC38 GPIO_10_ROMSCK AH13 2 C5193 1 10K_5%_2_DY 1 R5025 2 R5008 MODE C5013 A VSYNC IN P3V3_GPUS 2 GPIO_8_ROMSO 0_5%_2_DY DPLL_VDDC 2 1 GPU_JTAG_TCK 10UF_6.3V_3 C5182 OUT 10K_5%_2_DY GPU_JTAG_TMS 2 GPU_JTAG_TRSTB OUT R5024 1 P1V8_GPUS OUT JTAG HSYNC DDC/AUX I=0.125A 2 1 FBM_11_160808_121T GPU_JTAG_TDI GPIO_7_BLON 2 0.1UF_16V_2 R5034 2 1 C5183 1 1 10K_5%_2_DY 2 R5164 1 10K_5%_2_DY 2 1 R5162 2 R5160 1 L5180 TP5165 1 10K_5%_2_DY 2 P1V0_GPU 10K_5%_2 2 1 I=0.075A 2 FBM_11_160808_121T KHZ SPREAD SPECTRUM MODULATION OUT GPU_CRT_B GPIO_9_ROMSI AK24 IN OUT C5033 L5181 GPU_JTAG_TDO BB DAC1 GPIO_6 VDD2DI/NC IDT_6V40088_DFN_10P OUT GPIO_5_AC_BATT VSS2DI/NC P3V3_GPUS B GPU_HDMI_HPD1 P1V8_GPUS 1 32 B V2SYNC/GENLK_VSYNC 2 GND_27M GPU_XOIN_27M_R OUT 33_5%_2 GND_PLL GPU_XOIN2_100M_R OUT 1 R50232 TP24 GPIO_4_SMBCLK GPU_CRT_G AF37 AE38 1 27M 9 GPU_XOIN_27M TP24 1UF_6.3V_2 S1 5 GPU_XOIN2_100M 1 TP5036 OUT OUT IN IN IN IN IN IN IN IN 1 100M TP5035 P1V8_GPUS 1 R50222 33_5%_2 2 0_5%_2 6 2 VDD_27M 10 C5192 S0 X2 2 7 3 1 1 0_5%_2 R5012 R5010 2 1 C5163 2 0.1UF_16V_2 1 0.1UF_16V_2 C5161 2 2 10UF_6.3V_3 C5006 1 C VDD_100M R5185 L5007 U5017 X1_ICLK 4 8 1 3.3V,0.05A 2 2 1M_5%_2 2 R5016 1 10UF_6.3V_3 XTAL_4PIN OUT GPU_GPIO19 POW_SW1 GPU_GPIO21 GPU_GPIO22 GPU_GPIO23 GPU_JTAG_TRSTB GPU_JTAG_TDI GPU_JTAG_TCK GPU_JTAG_TMS GPU_JTAG_TDO 1 2 1 2 27MHZ_12PF 1 FBM_11_160808_121T 3 1 1 15PF_50V_2 C5011 2 P3V3_GPUS 1 4 499_1%_2 2 0_5%_2_DY 10UF_6.3V_3 C5184 1 IN 2 CLK_GPU_27M GPU_THERM_INT# X5015 R5009 C5166 1.8V 15PF_50V_2 SWING: IN IN IN IN OUT GB GPIO_3_SMBDATA GPU_CRT_R OUT 0.1UF_16V_2_DY GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 GPU_EDP_HPD POW_SW0 GPIO_2 OUT AE36 AD35 C5213 IN G 2 GPU_GPIO9 GPIO_1 AD39 AD37 1 OUT RB GPIO_0 2 D AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 OUT OUT OUT BI BI IN AT23 AR22 SDA GENERAL PURPOSE I/O GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 GPU_THM_DAT GPU_THM_CLK GPU_GPIO5 GPU_LCM_BKLTEN AU22 AV21 SCL TP24 10K_5%_2 CLOSE TO GPU AT21 AR20 1 TP5190 TX5P_DPD0P TX5M_DPD0N AK26 AJ26 1 AU20 AT19 R5211 POW_SW1 1 E AT17 AR16 10K_5%_2_DY TP24 TP5189 AU16 AV15 2 GPU_GPIO21 OUT AT15 AR14 1 2 DUAL CHANNEL FOR 3D FUNCTION AU14 AV13 2 IN TXCCM_DPC3N 10K_5%_2_DY 2 TXCCP_DPC3P DVPDATA_10 EDP 1 1 1 DVPDATA_9 R5179 10K_5%_2_DY GPU_EDP_TX0_DP GPU_EDP_TX0_DN 0.1UF_16V_2_DY R5212 POW_SW0 DVPDATA_8 AJ21 AK21 GPU_CRT_VSYNC OUT BI BI C5210 IN 10K_5%_2 R5163 2 10K_5%_2 TX5M_DPB0N 2 1 R51612 Audio DVPDATA_7 1 10K_5%_2 HDMI&DP R5178 GPU_EDP_TX1_DP GPU_EDP_TX1_DN R5208 GPU_LCM_BKLTEN IN GPU_CRT_HSYNC BI BI AT33 AU32 0_5%_3_DY 10K_5%_2 2 1 2 TX5P_DPB0P 2 R5159 1 OUT R5177 DVPDATA_6 1 1 GPU_GPIO5 AR32 AT31 2 10K_5%_2_DY GPU_GPIO19 IN 10K_5%_2 OUT TX4M_DPB1N DVPDATA_5 10K_5%_2_DY 2 2 TX4P_DPB1P DVPDATA_4 0.1UF_16V_2_DY R5209 1 R5176 DVPDATA_3 AV31 AU30 1 1 R5158 GPU_GPIO9 OUT 10K_5%_2_DY E TX3M_DPB2N DPB DVPDATA_2 2 2 TX3P_DPB2P DVPDATA_1 1 1 R5175 TXCBM_DPB3N DVPCLK DVPDATA_0 2 0.90V GPU_GPIO23 OUT 10K_5%_2_DY DVPCNTL_2 1 2 GPU_HDMI_TX2_DP GPU_HDMI_TX2_DN AR30 AT29 C5206 R5174 TXCBP_DPB3P 2 PRO GPU_GPIO13 OUT DVPCNTL_1 1 For 1.00V 0 2 DVPCNTL_0 10K_5%_2_DY 1 R5173 TX2M_DPA0N DVPCNTL_MVP_1 10K_5%_2_DY 1 1 GPU_GPIO12 OUT BI BI HDMI R5202 0 2 GPU_HDMI_TX1_DP GPU_HDMI_TX1_DN 2 +VDDC_GPU MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 R5172 10K_5%_2_DY POW_SW1 POW_SW0 PCORE_GPU GPU_GPIO11 OUT BI BI AT27 AR26 R5203 VID0 2 10K_5%_2_DY 1 VID1 R5171 TX2P_DPA0P DVPCNTL_MVP_0 2 1 GPU_GPIO22 OUT AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 1 0.90V 2 AU26 AV25 F 2 0 R5170 GPU_HDMI_TX0_DP GPU_HDMI_TX0_DN 1 1 XT TX1P_DPA1P TX1M_DPA1N 10K_5%_2 For [ALERT] BI BI 2 1.00V GPU_THERM_INT# IN AT25 AR24 1 1 2 GPU_HDMI_TXC_DP GPU_HDMI_TXC_DN 2 0 1 TX0M_DPA2N BI BI 2 1.05V TX0P_DPA2P GFX AU24 AV23 R5197 0 MUTI DPA 10K_5%_2_DY POW_SW1 POW_SW0 PCORE_GPU 0 P1V8_GPUS R5169 10K_5%_2 +VDDC_GPU TXCAM_DPA3N 1 1 1 VID0 VID1 TXCAP_DPA3P 150_1%_2 MB GPU_GPIO2 2 32 OUT R5196 1 2 1 1 R5019 10K_5%_2_DY 150_1%_2 0 GPU_GPIO1 2 MB OUT R5194 64 2 1 0 1 U5124 150_1%_2 1 SAMSUNG (1GB) 2 2 0 HYNIX 1 3 R5168 10K_5%_2 1 1 1 MB 1 0 10K_5%_2 128 (1GB) 0 0 2 0 (GDDR5) 0 R5187 0 Vendor 0 1 0 MEM_ID0 10K_5%_2 R5191 1 GPU_GPIO0 OUT 2 0 2 R5030 1 256 MB (DEFAULT) 0 R5167 10K_5%_2 1 1 MEMORY APERTURE SIZE 10K_5%_2_DY GPU_ GPIO11 4 MEM_ID1 2 F GPU_ GPIO12 MEM_ID2 1 GPU_ GPIO13 MEM_ID3 R5029 IF GPU_GPIO22 = 0, THEN GPIO[13:11] DEFINES THE PRIMARY MEMORY APERTURE SIZE 5 P3V3_GPUS 10K_5%_2_DY 8 6 5 4 3 DATE February 21-OCT-2002 2 22, 2010 CODE CS SHEET Diagram DOC.NUMBER CS_1310AXXXXXX-MTR 1310xxxxx-0-0 86 1 97 of 1 1 REV A01 X01 8 7 6 5 4 CHANNEL A 3 BI 1 VM_A1_ADA<31..0> 40.2_1%_2 MVREFDA_GPU C5216 0.1UF_16V_2 2 100_1%_2 2 R5214 1 1 2 R5043 R & CAPS CLOSE TO GPU B 1 P1V5_GPUS 40.2_1%_2 MVREFSA_GPU C5217 L18 L20 0.1UF_16V_2 P1V5_GPUS 2 100_1%_2 2 R5215 1 1 2 R5044 1 1 R & CAPS CLOSE TO GPU R5045 2 243_1%_2 R5218 2 243_1%_2 1 A R5219 2 L27 N12 AG12 M12 M27 AH12 DQA0_0/DQA_0 MAA0_0/MAA_0 DQA0_1/DQA_1 MAA0_1/MAA_1 DQA0_2/DQA_2 MAA0_2/MAA_2 DQA0_3/DQA_3 MAA0_3/MAA_3 A C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0 MAA1_7/MAA_A15_BA1 DQA0_16/DQA_16 DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 DQA0_21/DQA_21 WCKA1_0/DQMA_4 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 DQA1_2/DQA_34 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 DQA1_11/DQA_43 DQA1_12/DQA_44 ADBIA0/ODTA0 DQA1_13/DQA_45 ADBIA1/ODTA1 DQA1_14/DQA_46 DQA1_15/DQA_47 CLKA0 DQA1_16/DQA_48 CLKA0B DQA1_17/DQA_49 DQA1_18/DQA_50 CLKA1 DQA1_19/DQA_51 CLKA1B DQA1_20/DQA_52 DQA1_21/DQA_53 RASA0B DQA1_22/DQA_54 RASA1B DQA1_23/DQA_55 DQA1_24/DQA_56 CASA0B DQA1_25/DQA_57 CASA1B DQA1_26/DQA_58 DQA1_27/DQA_59 CSA0B_0 DQA1_28/DQA_60 CSA0B_1 DQA1_29/DQA_61 DQA1_30/DQA_62 CSA1B_0 DQA1_31/DQA_63 CSA1B_1 MVREFDA CKEA0 MVREFSA CKEA1 MEM_CALRN0 WEA0B MEM_CALRN1 WEA1B G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17 VM_A0_AA<0> VM_A0_AA<1> VM_A0_AA<2> VM_A0_AA<3> VM_A0_AA<4> VM_A0_AA<5> VM_A0_AA<6> VM_A0_AA<7> VM_A1_AA<0> VM_A1_AA<1> VM_A1_AA<2> VM_A1_AA<3> VM_A1_AA<4> VM_A1_AA<5> VM_A1_AA<6> VM_A1_AA<7> A32 C32 D23 E22 C14 A14 E10 D9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 BI VM_A0_AA<7..0> BI VM_A1_AA<7..0> D BI BI BI BI BI BI BI BI C34 D29 D25 E20 E16 E12 J10 D7 VM_WCKA0_0_DP VM_WCKA0_0_DN VM_WCKA0_1_DP VM_WCKA0_1_DN VM_WCKA1_0_DP VM_WCKA1_0_DN VM_WCKA1_1_DP VM_WCKA1_1_DN BI BI BI BI BI BI BI BI A34 E30 E26 C20 C16 C12 J11 F8 BI BI BI BI BI BI BI BI VM_EDCA0_0 VM_EDCA0_1 VM_EDCA0_2 VM_EDCA0_3 VM_EDCA1_0 VM_EDCA1_1 VM_EDCA1_2 VM_EDCA1_3 C VM_DDBIA0_0 VM_DDBIA0_1 VM_DDBIA0_2 VM_DDBIA0_3 VM_DDBIA1_0 VM_DDBIA1_1 VM_DDBIA1_2 VM_DDBIA1_3 J21 G19 BI BI H27 G27 OUT OUT DDR_A_CLKA0_DP DDR_A_CLKA0_DN J14 H14 OUT OUT DDR_A_CLKA1_DP DDR_A_CLKA1_DN K23 K19 OUT OUT DDR_A_RASA0# DDR_A_RASA1# K20 K17 OUT OUT DDR_A_CASA0# DDR_A_CASA1# K24 K27 OUT DDR_A_CSA0#_0 M13 K16 OUT DDR_A_CSA1#_0 K21 J20 OUT OUT DDR_A_CKEA0 DDR_A_CKEA1 K26 L15 OUT OUT DDR_A_WEA0# DDR_A_WEA1# H23 J19 BI BI VM_ADBIA0 VM_ADBIA1 B MEM_CALRN2 GDDR5 C VM_A0_ADA<0> VM_A0_ADA<1> VM_A0_ADA<2> VM_A0_ADA<3> VM_A0_ADA<4> VM_A0_ADA<5> VM_A0_ADA<6> VM_A0_ADA<7> VM_A0_ADA<8> VM_A0_ADA<9> VM_A0_ADA<10> VM_A0_ADA<11> VM_A0_ADA<12> VM_A0_ADA<13> VM_A0_ADA<14> VM_A0_ADA<15> VM_A0_ADA<16> VM_A0_ADA<17> VM_A0_ADA<18> VM_A0_ADA<19> VM_A0_ADA<20> VM_A0_ADA<21> VM_A0_ADA<22> VM_A0_ADA<23> VM_A0_ADA<24> VM_A0_ADA<25> VM_A0_ADA<26> VM_A0_ADA<27> VM_A0_ADA<28> VM_A0_ADA<29> VM_A0_ADA<30> VM_A0_ADA<31> VM_A1_ADA<0> VM_A1_ADA<1> VM_A1_ADA<2> VM_A1_ADA<3> VM_A1_ADA<4> VM_A1_ADA<5> VM_A1_ADA<6> VM_A1_ADA<7> VM_A1_ADA<8> VM_A1_ADA<9> VM_A1_ADA<10> VM_A1_ADA<11> VM_A1_ADA<12> VM_A1_ADA<13> VM_A1_ADA<14> VM_A1_ADA<15> VM_A1_ADA<16> VM_A1_ADA<17> VM_A1_ADA<18> VM_A1_ADA<19> VM_A1_ADA<20> VM_A1_ADA<21> VM_A1_ADA<22> VM_A1_ADA<23> VM_A1_ADA<24> VM_A1_ADA<25> VM_A1_ADA<26> VM_A1_ADA<27> VM_A1_ADA<28> VM_A1_ADA<29> VM_A1_ADA<30> VM_A1_ADA<31> DDR2 GDDR5/GDDR3 DDR3 MEMORY INTERFACE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BI D P1V5_GPUS 1 U5124 DDR2 GDDR3/GDDR5 DDR3 VM_A0_ADA<31..0> 2 MEM_CALRP1 MEM_CALRP0 MEM_CALRP2 MAA0_8 MAA1_8 VM_A0_AA<8> VM_A1_AA<8> A 243_1%_2 1 R5220 2 243_1%_2 1 R5221 2 AMD_216_0810_001_FCBGA_962P 243_1%_2 1 R5222 2 INVENTEC 243_1%_2 TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 87 1 of 97 1 REV X01 A01 7 6 5 4 CHANNEL B 3 D P1V5_GPUS VM_B1_ADA<31..0> 1 BI 40.2_1%_2 1 0.1UF_16V_2 2 2 C5225 R & CAPS CLOSE TO GPU B 1 P1V5_GPUS 40.2_1%_2 2 R5047 1 1 MVREFSB_GPU 100_1%_2 0.1UF_16V_2 Y12 AA12 2 C5226 2 R5224 C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 DQB0_0/DQB_0 MAB0_0/MAB_0 DQB0_1/DQB_1 MAB0_1/MAB_1 DQB0_2/DQB_2 MAB0_2/MAB_2 DQB0_3/DQB_3 MAB0_3/MAB_3 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB0_5/MAB_5 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1 DQB0_16/DQB_16 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 DQB0_21/DQB_21 WCKB1_0/DQMB_4 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 DQB1_11/DQB_43 DQB1_12/DQB_44 ADBIB0/ODTB0 DQB1_13/DQB_45 ADBIB1/ODTB1 DQB1_14/DQB_46 DQB1_15/DQB_47 CLKB0 DQB1_16/DQB_48 CLKB0B DQB1_17/DQB_49 DQB1_18/DQB_50 CLKB1 DQB1_19/DQB_51 CLKB1B DQB1_20/DQB_52 DQB1_21/DQB_53 RASB0B DQB1_22/DQB_54 RASB1B DQB1_23/DQB_55 DQB1_24/DQB_56 CASB0B DQB1_25/DQB_57 CASB1B DQB1_26/DQB_58 DQB1_27/DQB_59 CSB0B_0 DQB1_28/DQB_60 CSB0B_1 DQB1_29/DQB_61 DQB1_30/DQB_62 CSB1B_0 DQB1_31/DQB_63 CSB1B_1 CKEB0 MVREFDB CKEB1 MVREFSB WEB0B WEB1B GPU_TESTEN P3V3_GPUS AD28 TESTEN AK10 AL10 CLKTESTA GDDR5 R & CAPS CLOSE TO GPU CLKTESTB MAB0_8 MAB1_8 DRAM_RST P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 VM_B0_AA<0> VM_B0_AA<1> VM_B0_AA<2> VM_B0_AA<3> VM_B0_AA<4> VM_B0_AA<5> VM_B0_AA<6> VM_B0_AA<7> VM_B1_AA<0> VM_B1_AA<1> VM_B1_AA<2> VM_B1_AA<3> VM_B1_AA<4> VM_B1_AA<5> VM_B1_AA<6> VM_B1_AA<7> 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 H3 H1 T3 T5 AE4 AF5 AK6 AK5 VM_B0_AA<7..0> BI VM_B1_AA<7..0> D VM_WCKB0_0_DP VM_WCKB0_0_DN VM_WCKB0_1_DP VM_WCKB0_1_DN VM_WCKB1_0_DP VM_WCKB1_0_DN VM_WCKB1_1_DP VM_WCKB1_1_DN BI BI BI BI BI BI BI BI F6 K3 P3 V5 AB5 AH1 AJ9 AM5 VM_EDCB0_0 VM_EDCB0_1 VM_EDCB0_2 VM_EDCB0_3 VM_EDCB1_0 VM_EDCB1_1 VM_EDCB1_2 VM_EDCB1_3 BI BI BI BI BI BI BI BI G7 K1 P1 W4 AC4 AH3 AJ8 AM3 T7 W7 BI BI L9 L8 OUT OUT DDR_B_CLKB0_DP DDR_B_CLKB0_DN AD8 AD7 OUT OUT DDR_B_CLKB1_DP DDR_B_CLKB1_DN T10 Y10 OUT OUT DDR_B_RASB0# DDR_B_RASB1# W10 AA10 OUT OUT DDR_B_CASB0# DDR_B_CASB1# P10 L10 OUT DDR_B_CSB0#_0 AD10 AC10 OUT DDR_B_CSB1#_0 U10 AA11 OUT OUT DDR_B_CKEB0 DDR_B_CKEB1 N10 AB11 OUT OUT BI BI DDR_B_WEB0# DDR_B_WEB1# VM_B0_AA<8> VM_B1_AA<8> T8 W8 AH11 VM_RESET_R1 R5053 1 2 VM_ADBIB0 VM_ADBIB1 VM_RESET_R2 C5228 0.1UF_16V_2_DY 5K_1%_2 2 GPU_TESTEN 0 5.11K_1%_2 51_1%_2_DY R5050 51_1%_2_DY R5051 2 R5049 2 SIGNALS 1 INVENTEC PLACE ALL THESE COMPONENTS VERY CLOSE TO GPU (WITHIN 25MM) AND KEEP ALL COMPONENT CLOSE TO EACH OTHER. (WITHIN 5MM) EXCEPT RSER2 TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block DEBUG ONLY SIZE C CHANGE 8 7 A 120PF_50V_2 1 STUFF OPTION NORMAL JTAG MODE MODE 2 JTAG SIGNAL OUT VM_RESET 51_1%_2 2 AMD_216_0810_001_FCBGA_962P B R5055 1 1 1 2 2 0.1UF_16V_2_DY 2 C5227 1 R5052 1 1 1 10_1%_2 10K_5%_2_DY C VM_DDBIB0_0 VM_DDBIB0_1 VM_DDBIB0_2 VM_DDBIB0_3 VM_DDBIB1_0 VM_DDBIB1_1 VM_DDBIB1_2 VM_DDBIB1_3 BI BI BI BI BI BI BI BI A R5048 BI 1 100_1%_2 R5223 VM_B0_ADA<0> VM_B0_ADA<1> VM_B0_ADA<2> VM_B0_ADA<3> VM_B0_ADA<4> VM_B0_ADA<5> VM_B0_ADA<6> VM_B0_ADA<7> VM_B0_ADA<8> VM_B0_ADA<9> VM_B0_ADA<10> VM_B0_ADA<11> VM_B0_ADA<12> VM_B0_ADA<13> VM_B0_ADA<14> VM_B0_ADA<15> VM_B0_ADA<16> VM_B0_ADA<17> VM_B0_ADA<18> VM_B0_ADA<19> VM_B0_ADA<20> VM_B0_ADA<21> VM_B0_ADA<22> VM_B0_ADA<23> VM_B0_ADA<24> VM_B0_ADA<25> VM_B0_ADA<26> VM_B0_ADA<27> VM_B0_ADA<28> VM_B0_ADA<29> VM_B0_ADA<30> VM_B0_ADA<31> VM_B1_ADA<0> VM_B1_ADA<1> VM_B1_ADA<2> VM_B1_ADA<3> VM_B1_ADA<4> VM_B1_ADA<5> VM_B1_ADA<6> VM_B1_ADA<7> VM_B1_ADA<8> VM_B1_ADA<9> VM_B1_ADA<10> VM_B1_ADA<11> VM_B1_ADA<12> VM_B1_ADA<13> VM_B1_ADA<14> VM_B1_ADA<15> VM_B1_ADA<16> VM_B1_ADA<17> VM_B1_ADA<18> VM_B1_ADA<19> VM_B1_ADA<20> VM_B1_ADA<21> VM_B1_ADA<22> VM_B1_ADA<23> VM_B1_ADA<24> VM_B1_ADA<25> VM_B1_ADA<26> VM_B1_ADA<27> VM_B1_ADA<28> VM_B1_ADA<29> VM_B1_ADA<30> VM_B1_ADA<31> C5054 1 2 MVREFDB_GPU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B BI DDR2 GDDR5/GDDR3 DDR3 MEMORY INTERFACE VM_B0_ADA<31..0> R5046 1 U5124 DDR2 GDDR3/GDDR5 DDR3 C 2 2 8 6 5 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 88 1 of 97 1 REV X01 A01 5 V12 U12 NC_VDDRHB VDDC#48 NC_VSSRHB VDDC#49 VDDC#47 1 2 C5276 0.1UF_16V_2 H7 H8 VDDC#56 MPV18#1 VDDC#57 MPV18#2 VDDC#58 AM10 SPV18 AN9 SPV10 AN10 0.1UF_16V_2 1 2 VDDC#54 VDDC#55 SPV10 C5275 1UF_6.3V_2 VDDC#53 PLL SPV18 1 C5267 2 2 C5260 1 FBM_11_160808_121T 0.1UF_16V_2 1 C5060 2 1UF_6.3V_2 1 C5264 2 1UF_6.3V_2 1.0V,0.1A VDDC#51 VDDC#52 VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 SPVSS VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 VOLTAGE SENESE VDDCI#9 VDDCI#10 VDDCI#11 AF28 FB_VDDC AG28 FB_VDDCI VDDCI#12 VDDCI#13 VOLTAGE WAITING SENESE POWER DESIGN VDDCI#14 VDDCI#15 ISOLATED CORE I/O AH29 FB_GND VDDCI#16 VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22 2 2 2 2 2 1 1 1 1 1 1 2 1 2 1 2 1UF_6.3V_2 1 2 2 1UF_6.3V_2 1 1UF_6.3V_2 1 2 1UF_6.3V_2 1 1UF_6.3V_2 2 1UF_6.3V_2 1UF_6.3V_2 C5338 1 1 1UF_6.3V_2 1 C5337 2 2 1 1UF_6.3V_2 2 C5339 1UF_6.3V_2 2 1UF_6.3V_2 1 C5330 2 1 C5331 2 C5332 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 C5324 1 1 C5325 2 1 2 C5326 2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 C5319 1 1 C5320 2 1 2 C5321 2 1UF_6.3V_2 1UF_6.3V_2 1 2 1UF_6.3V_2 C5312 1 1 C5313 C5314 2 1UF_6.3V_2 1UF_6.3V_2 2 1UF_6.3V_2 1 C5305 2 1 C5306 2 1 1UF_6.3V_2 C5307 2 C5301 C5302 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1 C5293 2 1 C5294 1 2 C5295 2 2 1 2 1UF_6.3V_2 1 C5288 1 1UF_6.3V_2 E 2 2 1 C5333 1 C5327 1 C5322 1 1 2 1 10UF_6.3V_3 VDDC#45 10UF_6.3V_3 10UF_6.3V_3 VDDC#44 NC_VSSRHA C5335 10UF_6.3V_3 NC_VDDRHA C5328 10UF_6.3V_3 VDDC#43 M20 M21 10UF_6.3V_3 VDDC#41 C5315 VDDC#40 C5318 2 VDDC#39 VDDC/BIF_VDDC#42 10UF_6.3V_3 VDDR4#6 C5310 D C5308 VDDC#38 2 VDDC#37 VDDR4#3 10UF_6.3V_3 VDDC#36 VDDR4#2 BIF_VDDC BIF_VDDC IS SEPARATE CORE POWER FOR THE PCIE BUS LOGIC. AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13 2 1UF_6.3V_2 VDDC#35 VDDR4#1 10UF_6.3V_3 VDDC#34 AD12 AF11 AF12 AG11 1 VDDC#32 VDDC/BIF_VDDC#33 VDDR4#8 C5296 VDDC#31 VDDR4#7 2 VDDR4#5 1UF_6.3V_2 VDDC#30 VDDR4#4 1UF_6.3V_2 VDDC#27 VDDC#29 10UF_6.3V_3 VDDC#26 VDDR3#4 P1V0_GPU C 1UF_6.3V_2 VDDC#25 VDDR3#3 C5289 VDDC#24 VDDR3#2 1 VDDR3#1 C5290 VDDC#21 VDDC#23 C5287 1UF_6.3V_2 VDDC#20 VDDC#22 2 VDDC#19 1 VDDC#18 VDD_CT#4 C5291 VDDC#17 VDD_CT#3 2 VDDC#16 VDD_CT#2 1UF_6.3V_2 1UF_6.3V_2 VDDC#15 VDD_CT#1 F 10UF_6.3V_3 1 VDDC#10 1UF_6.3V_2 VDDC#9 VDDR1#34 1UF_6.3V_2 VDDC#8 VDDR1#33 10UF_6.3V_3 VDDR1#32 C5282 VDDC#7 2 VDDC#6 VDDR1#31 1 VDDC#5 VDDR1#30 C5283 VDDC#4 VDDR1#29 2 VDDR1#28 AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 1 VDDC#3 C5284 VDDC#1 VDDC#2 VDDR1#27 2 CORE VDDR1#26 C5334 1UF_6.3V_2 PVCORE_GPU 1 VDDR1#25 C5066 1UF_6.3V_2 VDDC+VDDCI=43.3A(PEAK) C5061 VDDR1#24 1 PCIE_VDDC#12 VDDR1#23 C5300 VDDR1#22 2 PCIE_VDDC#11 1 VDDR1#21 2 PCIE_VDDC#10 C5304 1 PCIE_VDDC#9 VDDR1#20 C5298 2 PCIE_VDDC#8 VDDR1#19 C5064 1 VDDR1#18 C5062 C5303 PCIE_VDDC#7 1 PCIE_VDDC#6 VDDR1#17 2 PCIE_VDDC#5 VDDR1#16 1UF_6.3V_2 PCIE_VDDC#4 VDDR1#15 C5316 1UF_6.3V_2 2 1.0V,1.1A G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 1 VDDR1#14 PCIE_PVDD 2 PCIE_VDDC#3 C5065 0.1UF_16V_2 L5336 1 BLM18PG600SN1D 1.8V,0.04A 1UF_6.3V_2 PCIE_VDDC#2 VDDR1#13 VDDC#28 AF13 AF15 AG13 AG15 1 2 C5274 1UF_6.3V_2 1 2 C5269 10UF_6.3V_3 1 1 C5058 2 2 C5257 0.1UF_16V_2 2 PCIE_VDDC#1 VDDR1#12 VDDC#50 10UF_6.3V_3 L5243 VDDR1#11 1 2 1 2 C5273 1UF_6.3V_2 1 2 C5268 1UF_6.3V_2 1 2 C5262 10UF_6.3V_3 C5263 2 2 L5057 1 C5245 2 1UF_6.3V_2 1 C5242 2 10UF_6.3V_3 1 C5238 2 1 PCIE_VDDR/PCIE_PVDD VDDR1#10 VDDC#12 AF23 AF24 AG23 AG24 MVP18 P1V0_GPU C VDDR1#9 VDDC#46 10UF_6.3V_3 1 PCIE_VDDR#8 VDDR4 1.8V,0.15A FBM_11_160808_121T 1 2 PCIE_VDDR#7 VDDR1#8 I/O 1.8V,0.17A 2 GDDR3 ORB FBM_11_160808_121T PCIE_VDDR#6 VDDR1#7 C5297 0.1UF_16V_2 2 0.1UF_16V_2 1.8V,0.05A VDDR1#6 C5063 1 1 2 C5056 1UF_6.3V_2 1 2 C5235 10UF_6.3V_3 1 L5233 PCIE_VDDR#5 VDDC#11 AF26 AF27 AG26 AG27 P1V8_GPUS P1V8_GPUS VDDR1#5 LEVEL TRANSLATION FBM_11_160808_121T Follow PCIE_VDDR#4 VDDC#14 C5272 0.1UF_16V_2 1 2 C5059 1UF_6.3V_2 1 2 C5261 10UF_6.3V_3 1 C5255 2 1 C5256 2 1 L5230 2 FBM_11_160808_121T 1 C5231 2 1 PCIE_VDDR#3 VDDR1#4 POWER D P1V8_GPUS L5250 PCIE_VDDR#2 VDDR1#3 VDD_CT 3.3V,0.06A 1.8V,0.04A VDDR1#2 VDDC#13 P3V3_GPUS PCIE_PVDD PCIE_VDDR#1 C5281 1.8V,0.017A 2 VDDR1#1 2 10UF_6.3V_3 P1V8_GPUS L5249 PCIE_VDDR 1.8V,0.44A AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37 C5340 1 C5270 2 1 2 C5271 10UF_6.3V_3 E 1 1 PCIE AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 STITCHING CAPS OPTION FOR MEM SIGNALS THAT HAVE A CHANGE OF REFERENCE PLANE VOLTAGE.ADD STITCHING CAPS WHEN REQUIRED, ONE CAP PER THREE SIGNALS FBM_11_160808_121T 2 P1V8_GPUS MEM I/O 1UF_6.3V_2 1 C5265 2 1 2 C5266 10UF_6.3V_3 C5259 2 1UF_6.3V_2 1 C5258 1 2 1UF_6.3V_2 1 1UF_6.3V_2 2 C5254 10UF_6.3V_3 1 2 C5253 1 1UF_6.3V_2 2 C5252 10UF_6.3V_3 1 2 C5251 1UF_6.3V_2 1 C5248 2 10UF_6.3V_3 1 2 C5247 1 1UF_6.3V_2 0.1UF_16V_2 C5244 2 0.1UF_16V_2 1 2 C5246 1 1UF_6.3V_2 C5240 2 1 C5241 2 C5239 0.1UF_16V_2 1 2 C5237 1UF_6.3V_2 1 2 0.1UF_16V_2 1 2 C5236 1 0.1UF_16V_2 2 C5232 1 0.1UF_16V_2 C5229 2 2 C5234 1UF_6.3V_2 1 GDDR5 900MHZ,1.5V,2.3A(PEAK) P1V8_GPUS 3 GPU U5124 POWER P1V5_GPUS F 4 2 6 2 7 8 PVCORE_GPU VDDC+VDDCI=43.3A(PEAK) 1UF_6.3V_2 2 1 C5329 1UF_6.3V_2 2 1 C5323 1UF_6.3V_2 1 C5317 2 1UF_6.3V_2 C5311 1 2 1UF_6.3V_2 1 C5309 2 1UF_6.3V_2 2 1 C5299 1UF_6.3V_2 1 2 C5292 B 10UF_6.3V_3 2 1 1UF_6.3V_2 1 C5285 C5286 2 1 2 1UF_6.3V_2 10UF_6.3V_3 1 C5279 C5280 2 1UF_6.3V_2 10UF_6.3V_3 2 C5278 1 2 B 1 C5277 AMD_216_0810_001_FCBGA_962P A A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by XXX BEN LEE 8 7 6 5 4 3 DATE February 21-OCT-2002 2 22, 2010 CODE CS SHEET Diagram DOC.NUMBER CS_1310AXXXXXX-MTR 1310xxxxx-0-0 89 1 97 of 1 1 REV A01 X01 7 8 6 5 4 3 2 1 F F U5124 GND#24 PCIE_VSS#25 GND#25 PCIE_VSS#26 GND#26 PCIE_VSS#27 GND#27 PCIE_VSS#28 GND#28 PCIE_VSS#29 GND#29 PCIE_VSS#30 GND#30 PCIE_VSS#31 GND#31 PCIE_VSS#32 GND#32 PCIE_VSS#33 GND#33 PCIE_VSS#34 GND#34 PCIE_VSS#35 GND#35 GND#36 GND#37 GND#38 GND#39 GND GND#44 GND#103 GND#45 GND#104 GND#46 GND#105 GND#47 GND#106 GND#48 GND#107 GND#49 GND#108 GND#50 GND#109 GND#51 GND#110 GND#52 GND#111 GND#53 GND#112 GND#54 GND#113 GND#55 GND#114 GND#56 GND#115 GND#57 GND#116 GND#58 GND#117 GND#59 GND#60 GND#118 GND#119 GND/PX_EN#61 GND#120 GND#62 GND#121 GND#63 GND#122 GND#64 GND#123 GND#65 GND#124 GND#66 GND#125 GND#67 GND#126 GND#68 GND#127 GND#69 GND#128 GND#70 GND#129 GND#71 GND#130 GND#72 GND#131 GND#73 GND#132 GND#74 GND#133 GND#75 GND#134 GND#76 GND#135 GND#77 GND#136 GND#78 GND#137 GND#79 GND#138 GND#80 GND#139 GND#81 GND#140 GND#82 GND#141 GND#83 GND#142 GND#84 GND#143 GND#85 GND#144 GND#86 GND#145 GND#87 GND#146 GND#88 GND#147 GND#89 GND#148 GND#90 GND#149 GND#91 GND#150 GND#92 GND#151 GND#93 GND#153 GND#94 GND#154 GND#95 GND#155 GND#96 GND#156 GND#97 GND#157 GND#98 P5V_S C5345 C5348 0.1UF_16V_2 0.1UF_16V_2 R5352 R5353 1K_5%_2 1K_5%_2 R5342 10K_5%_2 OUT VDDC_ON OUT VPCIE_ON DGPU_PWROK OUT R5071 PX_EN# 5 1 VDDC_GPU_PG U5067 0_5%_2 1 IN 5 2 1 PX_MODE 4 4 PX_EN 1 3 Q5351 G 2 2 P3V3_GPUS 3 U5349 3 3 TC7SZ08FU TC7SZ08FU 1 D G Q5072 SSM3K7002BFU SSM3K7002BFU 2 2 3 Q5341 1 G SSM3K7002BFU 2 10K_5%_2 OUT 1 R5068 0_5%_2_DY 3 DGPU_PWR_EN# IN 1 G PX_MODE 2 PX_MODE=0, PX_MODE=1, Q5343 FOR BACO MODE FOR NORMAL MODE SSM3K7002BFU 2 C P1V0_GPU Q5070 VPCIE_ON 1 IN 2 C5346 4.7UF_6.3V_3 BIF_VDDC PVCORE_GPU G AM2302N 3 GND#158 GND#159 GND#160 GND#161 1 GND#163 R5350 2 B GND#164 0_5%_3_DY GND#165 GND#166 GND#167 GND#168 GND#169 Q5069 GND#170 D D GND#171 1 B GND#43 GND#102 P3V3_S GND#172 GND#173 VSS_MECH#1 GND#174 VSS_MECH#2 GND#175 VSS_MECH#3 VDDC_ON A39 AW1 AW39 G IN G G C5347 ALPHA_AO3416_SOT23_3P GND#152 S S GND#162 AMD_216_0810_001_FCBGA_962P 4.7UF_6.3V_3 2 C GND#42 GND#101 P3V3_S D D GND#41 GND#100 P3V3_S S F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13 GND#40 E 1 GND#23 PCIE_VSS#24 2 PCIE_VSS#23 BACO D GND#22 S GND#21 PCIE_VSS#22 1 GND#20 PCIE_VSS#21 2 GND#19 PCIE_VSS#20 D GND#18 PCIE_VSS#19 S GND#17 PCIE_VSS#18 + GND#16 PCIE_VSS#17 - GND#15 PCIE_VSS#16 1 GND#14 PCIE_VSS#15 2 GND#13 PCIE_VSS#14 2 GND#12 PCIE_VSS#13 1 PCIE_VSS#12 S GND#11 D PCIE_VSS#11 + GND#10 - GND#9 PCIE_VSS#10 1 GND#8 PCIE_VSS#9 2 GND#7 PCIE_VSS#8 1 GND#6 PCIE_VSS#7 R5344 GND#5 PCIE_VSS#6 2 GND#4 PCIE_VSS#5 D PCIE_VSS#4 A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 S GND#3 1 GND#2 PCIE_VSS#3 2 GND#1 PCIE_VSS#2 D E PCIE_VSS#1 S AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 PVCORE_GPU A A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by XXX BEN LEE 8 7 6 5 4 3 DATE February 21-OCT-2002 2 22, 2010 CODE CS SHEET Diagram DOC.NUMBER CS_1310AXXXXXX-MTR 1310xxxxx-0-0 90 1 97 of 1 1 REV A01 X01 8 7 6 5 4 U5124 LVDS CONTROL DPCD_VDD10 3 DIGON DP C/D AP20 AP21 AK35 AL36 TXCLK_UN_DPF3N TXOUT_U0N_DPF2N D AN17 AP16 AP17 AW14 AW16 AJ38 AK37 TXOUT_U0P_DPF2P AH35 AJ36 TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N DPCD_VDD10 DPCD_VDD18 TXOUT_U2N_DPF0N AP22 AP23 AF35 AG36 TXOUT_U3P TXOUT_U3N AP14 AP15 AN19 AP18 AP19 AW20 AW22 AW37 AU35 TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N AR37 AU39 TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N AP35 AR35 TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N DPEF_VDD10 DPEF_VDD18 AN36 AP37 TXOUT_L3P TXOUT_L3N 1 R5382 2 AW18 P1V8_GPUS DPAB_VDD18 1.0V,0.33A DP/DPC_VSSR#3 DP/DPA_VSSR#3 DP/DPC_VSSR#4 DP/DPA_VSSR#4 DP/DPC_VSSR#5 DP/DPA_VSSR#5 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 D AP25 AP26 AN33 AP33 1 0.1UF_16V_2 C5379 2 DP/DPB_VSSR#2 DP/DPD_VSSR#3 DP/DPB_VSSR#3 DP/DPD_VSSR#4 DP/DPB_VSSR#4 DP/DPD_VSSR#5 DP/DPB_VSSR#5 DP E/F POWER 1 AL33 AM33 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS R5383 2 DPAB_VDD18 C DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AU28 AV27 DPAB_VDD18 AV29 AR28 DPCD_VDD18 AU18 AV17 DPCD_VDD18 AV19 AR18 DPEF_VDD18 DP/DPE_VSSR#3 DP/DPE_VSSR#4 DPCD_VDD18/DPD_PVDD DPEF/DPF_VDD18#1 B DPEF/DPF_VDD18#2 AM37 AN38 DPEF_VDD18 DPEF/DPF_VDD10#1 DPEF/DPF_VDD10#2 AL38 AM35 DP/DPF_VSSR#1 DP/DPF_VSSR#2 DP/DPF_VSSR#3 DP/DPF_VSSR#4 DP/DPF_VSSR#5 AM39 DPEF_CALR 1 1 0.1UF_16V_2 C5380 AMD_216_0810_001_FCBGA_962P A P1V8_GPUS PS_0: BALL AM34 ADD THESE BOM OPTIONS TO SUPPORT FUTURE GPU MULTI LEVEL PIN STRAPS FEATURE. 1 FUTURE ASIC INVENTEC 1 1 2 10K_5%_2_DY C5076 10K_5%_2_DY 0.1UF_16V_2_DY 2 2 0.1UF_16V_2 C5381 R5075 2 1UF_6.3V_2 1 C5378 2 10UF_6.3V_3 1 C5375 0.1UF_16V_2 1 C5367 2 1UF_6.3V_2 1 C5364 2 10UF_6.3V_3 1 C5361 2 POWER DP_VSSR/DPA_PVSS R5074 5 R5384 0_5%_2 DPEF_VDD10 2 6 DP PLL DPAB_VDD18/DPA_PVDD TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 7 AW28 1 DPAB_CALR DPEF/DPE_VDD18#2 AF39 AH39 AK39 AL34 AM34 1.0V,0.22A 40MILL AN29 AP29 AP30 AW30 AW32 150_1%_2 2 1UF_6.3V_2 1 C5377 2 10UF_6.3V_3 1 C5374 2 0_1%_3 2 R5372 DP/DPB_VSSR#1 DP/DPD_VSSR#2 DP_VSSR/DPE_PVSS 1 1 0_1%_3 2 R5370 0.1UF_16V_2 1 C5366 2 1UF_6.3V_2 1 C5363 2 10UF_6.3V_3 1 DPEF_VDD18 DP/DPD_VSSR#1 DPEF/DPE_VDD18#1 AK33 AK34 DPAB_VDD10 1.8V,0.33A 8 AN27 AP27 AP28 AW24 AW26 DPEF_VDD18/DPE_PVDD 1.0V,0.33A 1 C5360 2 0_1%_3 2 R5358 DP/DPA_VSSR#2 AH34 AJ34 AF34 AG34 2 0_1%_3 DP/DPA_VSSR#1 DP/DPC_VSSR#2 DP_VSSR/DPF_PVSS 1.8V,0.33A 2 DP/DPC_VSSR#1 AP31 AP32 DPEF_VDD18/DPF_PVDD DPCD_VDD18 R5356 DPAB/DPA_VDD10#2 DPEF_VDD18 R5073 1 DPAB/DPA_VDD10#1 DPCD/DPC_VDD10#2 DP_VSSR/DPD_PVSS 2 1UF_6.3V_2 1 C5376 2 10UF_6.3V_3 1 C5373 2 BLM18PG181SN1D_DY 1 2 BLM18PG181SN1D_DY L5371 2 L5369 1 2 L5368 1 BLM18PG181SN1D 0.1UF_16V_2 1 C5365 2 1UF_6.3V_2 1 2 C5362 1 10UF_6.3V_3 C5359 2 BLM18PG181SN1D_DY 1 2 BLM18PG181SN1D_DY L5357 2 L5355 1 2 BLM18PG181SN1D DPCD/DPC_VDD10#1 DPCD_CALR AN34 AP39 AR39 AU37 DPEF_VDD10 40MILL AN24 AP24 150_1%_2 DPCD_VDD10 P1V0_GPU 1.8V,0.33A L5354 DPAB/DPA_VDD18#2 150_1%_2 AMD_216_0810_001_FCBGA_962P 1 DPAB/DPA_VDD18#1 DPCD/DPC_VDD18#2 1 TXCLK_LN_DPE3N A DPCD/DPC_VDD18#1 AP34 AR34 TXCLK_LP_DPE3P B POWER DPAB_VDD10 LVTMDP C DPAB_VDD18 DP A/B DPAB_VDD18 AG38 AH37 TXOUT_U2P_DPF0P POWER DPAB_VDD10 AP13 AT13 TXCLK_UP_DPF3P 1 U5124 DPCD_VDD18 AK27 AJ27 VARY_BL 2 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 91 1 of 97 1 REV X01 A01 7 6 5 U5089 VDDQ-B3 DQ29|DQ5 VDDQ-B12 DQ28|DQ4 VDDQ-B14 VDDQ-D1 DQ26|DQ2 VDDQ-D3 DQ25|DQ1 VDDQ-D12 DQ24|DQ0 VDDQ-D14 DQ23|DQ15 VDDQ-E5 DQ22|DQ14 VDDQ-E10 DQ21|DQ13 VDDQ-F1 DQ20|DQ12 VDDQ-F3 DQ19|DQ11 VDDQ-F12 DQ18|DQ10 VDDQ-F14 DQ17|DQ9 VDDQ-G2 DQ16|DQ8 VDDQ-G13 DQ15|DQ23 VDDQ-H3 DQ14|DQ22 VDDQ-H12 DQ13|DQ21 VDDQ-K3 DQ12|DQ20 VDDQ-K12 DQ11|DQ19 VDDQ-L2 DQ10|DQ18 VDDQ-L13 VDDQ-M1 DQ8|DQ16 VDDQ-M3 DQ7|DQ31 VDDQ-M12 DQ6|DQ30 VDDQ-M14 DQ5|DQ29 VDDQ-N5 DQ4|DQ28 VDDQ-N10 DQ3|DQ27 VDDQ-P1 DQ2|DQ26 VDDQ-P3 DQ1|DQ25 VDDQ-P12 DQ0|DQ24 VDDQ-P14 VDDQ-T1 VDDQ-T3 VDDQ-T12 VDDQ-T14 RFU/A12/NC A7/A8|A0/A10 VDD-C5 A6/A11|A1/A9 VDD-C10 A5/BA1|A3/BA3 VDD-D11 VDD-G4 VDD-L1 VDD-L4 VDD-L11 VSSQ-E3 VSSQ-E14 VSSQ-F5 VSSQ-F10 VSSQ-H13 VSSQ-K2 VSSQ-K13 VSSQ-M5 VSSQ-N3 VSSQ-N12 VSSQ-N14 ZQ VSSQ-R1 SEN VSSQ-R3 VSSQ-R4 VSSQ-R12 MF VSSQ-R14 VSSQ-V1 VSSQ-V3 P1V5_GPUS VSSQ-V12 VSSQ-V14 VSS-L5 VSS-P10 VSS-T5 VSS-T10 VDD-G14 VDD-L1 VDD-L14 WCK01|WCK23 WCK23|WCK01 VDD-P11 WCK01#|WCK23# VDD-R5 VDD-R10 WCK23#|WCK01# A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14 VSSQ-A1 EDC3|EDC0 VSSQ-A3 EDC2|EDC1 VSSQ-A12 EDC1|EDC2 VSSQ-A14 EDC0|EDC3 VSSQ-C1 VSSQ-C3 VSSQ-C4 DBI3#|DBI0# DBI2#|DBI1# VSSQ-C11 DBI1#|DBI2# VSSQ-C12 DBI0#|DBI3# VSSQ-C14 VSSQ-E12 RAS#|CAS# VSSQ-E14 VSSQ-F5 CAS#|RAS# VSSQ-H2 VSSQ-H13 CKE# CK# VSSQ-K2 CK VSSQ-K13 VSSQ-M10 CS#|WE# VSSQ-N1 VSSQ-N3 WE#|CS# VSSQ-N14 J13 J10 1 ZQ VSSQ-R1 SEN VSSQ-R3 VSSQ-R11 J2 J1 BI RESET# VSSQ-R12 MF VSSQ-R14 VSSQ-V14 1 C5496 1 Vpp,NC1 VSS-B10 VREFD2 VSS-D10 VSS-G5 VSS-G10 VSS-H1 VSS-H14 VSS-K1 J14 VREFC VM_ADBIA1 VSS-K14 VSS-L5 VSS-P10 J4 BI VSS-T5 ABI# C B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10 VSS-B5 VREFD1 2 2 2.37K_1%_2 R5494 1 Vpp,NC 1UF_6.3V_2_DY VM_REFD1_A1 VM_REFD2_A1 VM_REFDC_A1 D VSS-T10 HYNIX_H5GQ2H24MFR_T2C_BGA_170P C5500 2 1 0.1UF_16V_2 1 B 1 0.1UF_16V_2 1UF_6.3V_2 1 2 C5498 1 1UF_6.3V_2 C5493 2 1UF_6.3V_2 1 C5490 2 1UF_6.3V_2 1 2 C5486 1UF_6.3V_2 1 2 C5482 1 1UF_6.3V_2 2 C5480 1 1UF_6.3V_2 2 C5479 1 1UF_6.3V_2 C5478 2 1 10UF_6.3V_3 2 C5477 1 0.1UF_16V_2 2 C5476 1 C5475 2 0.1UF_16V_2 1 0.1UF_16V_2 2 C5474 1 0.1UF_16V_2 2 C5473 1 0.1UF_16V_2 2 C5472 1 0.1UF_16V_2 C5471 2 2 C5470 0.1UF_16V_2 1 P1V5_GPUS 1 0.1UF_16V_2 2 C5469 1 1UF_6.3V_2 2 C5468 1 1UF_6.3V_2 2 C5467 1 1UF_6.3V_2 2 C5466 1 2 1UF_6.3V_2 C5465 1UF_6.3V_2 1 2 C5463 1UF_6.3V_2 1 2 C5462 1UF_6.3V_2 1 2 C5459 1UF_6.3V_2 1 C5454 2 1 C5453 VDD-G4 VDD-G11 A1/A9|A6/A11 E C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10 VDD-G1 A2/BA0|A4/BA2 A0/A10|A7/A8 A10 V10 P1V5_GPUS 2 VDD-D11 VSS-L10 HYNIX_H5GQ2H24MFR_T2C_BGA_170P B 10UF_6.3V_3 1 C5499 ABI# VDD-C10 A5/BA1|A3/BA3 VSSQ-N12 0_5%_2 2 1UF_6.3V_2 1 C5086 2 5.49K_1%_2 1 R5085 2 1UF_6.3V_2 1 2 C5461 1 R5458 2 5.49K_1%_2 1UF_6.3V_2 1 C5082 2 R5080 2 5.49K_1%_2 1 VSS-L10 J4 VDD-C5 A6/A11|A1/A9 VSSQ-V12 1UF_6.3V_2 VSS-K14 A7/A8|A0/A10 120_1%_2 1 VREFC VDDQ-P14 A3/BA3|A5/BA1 A5 V5 C5497 J14 DQ0|DQ24 P1V5_GPUS 2 VSS-K1 VDDQ-P12 VSSQ-V1 P1V5_GPUS 5.49K_1%_2 VSS-H14 VDDQ-P3 DQ1|DQ25 VSSQ-R4 1 VSS-H1 VDDQ-P1 DQ2|DQ26 VSSQ-V3 P1V5_GPUS R5495 VSS-D10 VDDQ-N10 A4/BA2|A2/BA0 G12 L12 BI BI VM_RESET 2 VREFD2 VDDQ-N5 DQ4|DQ28 RFU/A12/NC J3 J11 J12 BI 2 1 2 VSS-B10 VSS-G5 BI 2 B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10 VSS-B5 VREFD1 DQ5|DQ29 DQ3|DQ27 G3 L3 BI BI 2 0_5%_2_DY 1UF_6.3V_2_DY Vpp,NC1 VSS-G10 VM_ADBIA0 P2 P13 D13 D2 Vpp,NC A10 V10 VM_REFD1_A0 VM_REFD2_A0 VM_REFDC_A0 BI BI BI BI R5093 R5091 1 1 1UF_6.3V_2_DY 2 C5464 1 2 2.37K_1%_2 R5084 1 1UF_6.3V_2_DY 2 C5460 1 2 R5457 2.37K_1%_2 1 2 C5081 1 2 R5079 2.37K_1%_2 1UF_6.3V_2_DY A5 V5 R2 R13 C13 C2 R5092 2 P1V5_GPUS BI BI BI BI DDR_A_WEA1# DDR_A_CSA1#_0 1UF_6.3V_2 P1V5_GPUS C VDDQ-M14 1 RESET# VDDQ-M12 DQ6|DQ30 VSSQ-M5 P1V5_GPUS C5491 BI VDDQ-M3 DQ7|DQ31 0.1UF_16V_2 J2 J1 DQ8|DQ16 VSSQ-F10 C5492 VM_RESET VSSQ-R11 VDDQ-M1 C5506 1 VDDQ-L13 2 J13 J10 0_5%_2 VM_EDCA1_0 VM_EDCA1_1 VM_EDCA1_3 VM_EDCA1_2 DDR_A_CASA1# DDR_A_RASA1# 1 1 P4 P5 DDR_A_CKEA1 2 1 2 VDDQ-L2 DQ10|DQ18 1 WE#|CS# 120_1%_2 2 R5088 0_5%_2_DY 2 VSSQ-N1 CS#|WE# BI BI BI BI 2.37K_1%_2 R5087 R5083 VSSQ-M10 G12 L12 BI BI DQ11|DQ19 VSSQ-E3 1 DDR_A_CSA0#_0 DDR_A_WEA0# DDR_A_CLK1_DN DDR_A_CLK1_DP 2 P1V5_GPUS VDDQ-K12 0.1UF_16V_2 CK VDDQ-K3 DQ12|DQ20 C5505 CK# VDDQ-H12 DQ13|DQ21 2 CKE# VDDQ-H3 DQ14|DQ22 1 J3 J11 J12 BI VM_WCKA1_0_DP VM_WCKA1_0_DN VM_DDBIA1_0 VM_DDBIA1_1 VM_DDBIA1_3 VM_DDBIA1_2 5.49K_1%_2 DDR_A_CKEA0 BI BI VSSQ-H2 VDDQ-G13 DQ15|DQ23 F 0.1UF_16V_2 CAS#|RAS# R5487 BI BI RAS#|CAS# VDDQ-G2 DQ16|DQ8 C5504 G3 L3 VDDQ-F14 DQ17|DQ9 VSSQ-E1 R5488 DDR_A_RASA0# DDR_A_CASA0# VSSQ-E12 VDDQ-F12 DQ18|DQ10 2 VSSQ-C14 DQ19|DQ11 1 DBI0#|DBI3# VDDQ-F3 0.1UF_16V_2 VSSQ-C12 BI BI 1 DBI1#|DBI2# R5489 VSSQ-C11 2 DBI2#|DBI1# VM_WCKA1_1_DP VM_WCKA1_1_DN D4 D5 60.4_1%_2 VSSQ-C4 1 VSSQ-C3 DBI3#|DBI0# VDDQ-F1 DQ20|DQ12 DQ9|DQ17 J5 K4 K5 K10 K11 H10 H11 H5 H4 VM_A1_AA<0> VM_A1_AA<1> VM_A1_AA<3> VM_A1_AA<2> VM_A1_AA<5> VM_A1_AA<4> VM_A1_AA<6> VM_A1_AA<7> 0 1 3 2 5 4 6 7 P1V5_GPUS R5485 VSSQ-C1 2 VSSQ-A14 EDC0|EDC3 60.4_1%_2 VSSQ-A12 EDC1|EDC2 1 1 R5456 2 EDC2|EDC1 VSSQ-E1 60.4_1%_2 1 60.4_1%_2 R5455 2 DDR_A_CLK0_DN DDR_A_CLK0_DP VSSQ-A3 1UF_6.3V_2_DY P2 P13 D13 D2 A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14 VSSQ-A1 EDC3|EDC0 1UF_6.3V_2 BI BI BI BI VM_DDBIA0_3 VM_DDBIA0_2 VM_DDBIA0_0 VM_DDBIA0_1 WCK23#|WCK01# C5483 R2 R13 C13 C2 2 BI BI BI BI BI BI WCK23|WCK01 1 VM_EDCA0_3 VM_EDCA0_2 VM_EDCA0_0 VM_EDCA0_1 VDD-R5 VDD-R10 VDDQ-E10 DQ21|DQ13 VDD-L4 C5484 P4 P5 VDD-P11 WCK01#|WCK23# VDDQ-E5 DQ22|DQ14 VDD-L11 2 BI BI WCK01|WCK23 VM_A1_AA<8> VM_A1_AA<7..0> 1 VM_WCKA0_1_DP VM_WCKA0_1_DN P1V5_GPUS D D4 D5 BI BI DQ23|DQ15 VDDQ-T3 2 VM_WCKA0_0_DP VM_WCKA0_0_DN VDD-L14 VDDQ-D14 C5503 A0/A10|A7/A8 VDDQ-D12 DQ24|DQ0 2 VDD-G14 VDDQ-D3 DQ25|DQ1 1 A1/A9|A6/A11 VDDQ-D1 DQ26|DQ2 0.1UF_16V_2 VDD-G11 DQ27|DQ3 C5502 A2/BA0|A4/BA2 VDDQ-B14 VDDQ-T14 C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10 VDD-G1 A3/BA3|A5/BA1 VDDQ-B12 DQ28|DQ4 2 A4/BA2|A2/BA0 VDDQ-B3 DQ29|DQ5 0.1UF_16V_2 J5 K4 K5 K10 K11 H10 H11 H5 H4 VM_A0_AA<7> VM_A0_AA<6> VM_A0_AA<5> VM_A0_AA<4> VM_A0_AA<3> VM_A0_AA<2> VM_A0_AA<1> VM_A0_AA<0> 7 6 5 4 3 2 1 0 VDDQ-B1 DQ30|DQ6 VDDQ-T1 2.37K_1%_2 BI BI DQ31|DQ7 B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14 VDDQ-T12 R5090 VM_A0_AA<8> VM_A0_AA<7..0> GDDR5 CHANNEL A MEMORY 1 E BI U5094 M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4 VM_A1_ADA<5> VM_A1_ADA<6> VM_A1_ADA<4> VM_A1_ADA<7> VM_A1_ADA<3> VM_A1_ADA<2> VM_A1_ADA<1> VM_A1_ADA<0> VM_A1_ADA<11> VM_A1_ADA<10> VM_A1_ADA<8> VM_A1_ADA<9> VM_A1_ADA<12> VM_A1_ADA<14> VM_A1_ADA<13> VM_A1_ADA<15> VM_A1_ADA<31> VM_A1_ADA<24> VM_A1_ADA<30> VM_A1_ADA<26> VM_A1_ADA<29> VM_A1_ADA<25> VM_A1_ADA<28> VM_A1_ADA<27> VM_A1_ADA<18> VM_A1_ADA<21> VM_A1_ADA<17> VM_A1_ADA<22> VM_A1_ADA<19> VM_A1_ADA<23> VM_A1_ADA<16> VM_A1_ADA<20> 5 6 4 7 3 2 1 0 11 10 8 9 12 14 13 15 31 24 30 26 29 25 28 27 18 21 17 22 19 23 16 20 C5501 DQ9|DQ17 VM_A1_ADA<31..0> B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14 VDDQ-B1 DQ30|DQ6 DQ27|DQ3 1 2 DQ31|DQ7 2 P1V5_GPUS R5481 F M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4 VM_A0_ADA<30> VM_A0_ADA<26> VM_A0_ADA<29> VM_A0_ADA<27> VM_A0_ADA<31> VM_A0_ADA<25> VM_A0_ADA<28> VM_A0_ADA<24> VM_A0_ADA<16> VM_A0_ADA<20> VM_A0_ADA<17> VM_A0_ADA<21> VM_A0_ADA<18> VM_A0_ADA<22> VM_A0_ADA<19> VM_A0_ADA<23> VM_A0_ADA<5> VM_A0_ADA<6> VM_A0_ADA<3> VM_A0_ADA<7> VM_A0_ADA<4> VM_A0_ADA<2> VM_A0_ADA<1> VM_A0_ADA<0> VM_A0_ADA<11> VM_A0_ADA<10> VM_A0_ADA<8> VM_A0_ADA<9> VM_A0_ADA<12> VM_A0_ADA<14> VM_A0_ADA<13> VM_A0_ADA<15> 30 26 29 27 31 25 28 24 16 20 17 21 18 22 19 23 5 6 3 7 4 2 1 0 11 10 8 9 12 14 13 15 BI 3 2 VM_A0_ADA<31..0> 4 P1V5_GPUS 5.49K_1%_2 8 A A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by XXX BEN LEE 8 7 6 5 4 3 DATE February 21-OCT-2002 2 22, 2010 CODE CS SHEET Diagram DOC.NUMBER CS_1310AXXXXXX-MTR 1310xxxxx-0-0 92 1 97 of 1 1 REV A01 X01 7 6 5 4 3 2 1 P1V5_GPUS P1V5_GPUS U5078 U5077 VDDQ-B3 DQ29|DQ5 VDDQ-B12 DQ28|DQ4 VDDQ-B14 DQ27|DQ3 VDDQ-D1 DQ26|DQ2 VDDQ-D3 DQ25|DQ1 VDDQ-D12 DQ24|DQ0 VDDQ-D14 DQ23|DQ15 VDDQ-E5 DQ22|DQ14 VDDQ-E10 DQ21|DQ13 VDDQ-F1 DQ20|DQ12 VDDQ-F3 DQ19|DQ11 VDDQ-F12 DQ18|DQ10 VDDQ-F14 DQ17|DQ9 VDDQ-G2 DQ16|DQ8 VDDQ-G13 DQ15|DQ23 VDDQ-H3 DQ14|DQ22 VDDQ-H12 DQ13|DQ21 VDDQ-K3 DQ12|DQ20 VDDQ-K12 DQ11|DQ19 VDDQ-L2 DQ10|DQ18 VDDQ-L13 VDDQ-M1 DQ8|DQ16 VDDQ-M3 DQ7|DQ31 VDDQ-M12 DQ6|DQ30 VDDQ-M14 DQ5|DQ29 VDDQ-N5 DQ4|DQ28 VDDQ-N10 DQ3|DQ27 VDDQ-P1 DQ2|DQ26 VDDQ-P3 DQ1|DQ25 VDDQ-P12 DQ0|DQ24 VDDQ-P14 VDDQ-T1 VDDQ-T3 VDDQ-T12 VDDQ-T14 RFU/A12/NC A7/A8|A0/A10 VDD-C5 A6/A11|A1/A9 VDD-C10 A5/BA1|A3/BA3 VDD-D11 VDD-G4 VDD-L1 VDD-L4 VDD-L11 VSSQ-E3 VSSQ-E14 VSSQ-F5 VSSQ-F10 VSSQ-H13 VSSQ-K2 VSSQ-K13 VSSQ-M5 VSSQ-N14 ZQ VSSQ-R1 SEN VSSQ-R3 VSSQ-R4 RESET# VSSQ-R12 MF VSSQ-R14 VSSQ-V1 VSSQ-V3 P1V5_GPUS VSSQ-V12 VSSQ-V14 VSS-L5 VSS-T5 VSS-T10 VDD-G1 VDD-G4 A2/BA0|A4/BA2 VDD-G11 A1/A9|A6/A11 VDD-G14 WCK01|WCK23 VDD-L1 WCK23|WCK01 VDD-P11 WCK01#|WCK23# VDD-R5 VDD-R10 WCK23#|WCK01# A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14 VSSQ-A1 EDC3|EDC0 VSSQ-A3 EDC2|EDC1 VSSQ-A12 EDC1|EDC2 VSSQ-A14 EDC0|EDC3 VSSQ-C1 VSSQ-C3 VSSQ-C4 DBI3#|DBI0# DBI2#|DBI1# VSSQ-C11 DBI1#|DBI2# VSSQ-C12 DBI0#|DBI3# VSSQ-C14 VSSQ-E12 RAS#|CAS# VSSQ-E14 VSSQ-F5 CAS#|RAS# VSSQ-H2 VSSQ-H13 CKE# CK# VSSQ-K2 CK VSSQ-K13 R5444 VSSQ-M10 CS#|WE# VSSQ-N1 VSSQ-N3 WE#|CS# VSSQ-N12 120_1%_2 1 R5445 VSSQ-N14 J13 J10 0_5%_2 1 ZQ VSSQ-R1 SEN VSSQ-R3 VSSQ-R11 J2 J1 BI RESET# VSSQ-R12 MF VSSQ-R14 VSSQ-V14 1 C5440 1 VSS-B10 VREFD2 VSS-D10 VSS-G5 VSS-G10 VSS-K1 J14 VREFC VSS-K14 VSS-L5 VSS-P10 J4 BI VSS-T5 ABI# C B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10 VSS-B5 VREFD1 2 2 R5438 1 Vpp,NC1 VSS-H1 VM_ADBIB1 D Vpp,NC VSS-H14 VM_REFD1_B1 VM_REFD2_B1 VM_REFDC_B1 E C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10 VSS-T10 HYNIX_H5GQ2H24MFR_T2C_BGA_170P C5446 2 1 0.1UF_16V_2 1 B 1 0.1UF_16V_2 1UF_6.3V_2 1 2 C5442 1 1UF_6.3V_2 C5437 2 1UF_6.3V_2 1 2 C5433 1UF_6.3V_2 1 2 C5429 1UF_6.3V_2 1 2 C5425 1 1UF_6.3V_2 2 C5422 1 1UF_6.3V_2 2 C5421 1 1UF_6.3V_2 C5420 2 1 10UF_6.3V_3 2 C5419 1 0.1UF_16V_2 2 C5418 1 C5417 2 0.1UF_16V_2 1 0.1UF_16V_2 2 C5416 1 0.1UF_16V_2 2 C5415 1 0.1UF_16V_2 2 C5414 1 0.1UF_16V_2 C5413 2 2 C5412 0.1UF_16V_2 1 P1V5_GPUS 1 0.1UF_16V_2 2 C5411 1 1UF_6.3V_2 2 C5410 1 1UF_6.3V_2 2 C5409 1 1UF_6.3V_2 2 C5408 1 2 1UF_6.3V_2 C5405 1UF_6.3V_2 1 C5402 2 1UF_6.3V_2 1 2 C5399 1UF_6.3V_2 1 2 C5395 1UF_6.3V_2 1 C5390 2 1 C5385 2 VDD-D11 VDD-L14 A10 V10 P1V5_GPUS 10UF_6.3V_3 VDD-C10 A5/BA1|A3/BA3 VSS-L10 HYNIX_H5GQ2H24MFR_T2C_BGA_170P B VDD-C5 A6/A11|A1/A9 A0/A10|A7/A8 G12 L12 BI BI C5443 ABI# A7/A8|A0/A10 A3/BA3|A5/BA1 J3 J11 J12 BI 2 1UF_6.3V_2 1 2 C5404 1 2 R5401 5.49K_1%_2 1UF_6.3V_2 1 2 C5397 1 R5394 2 5.49K_1%_2 1UF_6.3V_2 1 2 C5389 1 2 R5387 VSS-P10 J4 VDDQ-P14 VSSQ-V12 1UF_6.3V_2 VSS-K14 DQ0|DQ24 A4/BA2|A2/BA0 G3 L3 BI BI 1 VREFC VDDQ-P12 1UF_6.3V_2_DY C5441 J14 VDDQ-P3 DQ1|DQ25 VSSQ-R4 2 VSS-K1 VDDQ-P1 DQ2|DQ26 RFU/A12/NC A5 V5 2.37K_1%_2 VSS-H14 VSS-L10 5.49K_1%_2 2 1 VSS-H1 VDDQ-N10 DQ3|DQ27 P1V5_GPUS 2 VSS-D10 VDDQ-N5 DQ4|DQ28 VSSQ-V1 P1V5_GPUS R5439 VREFD2 DQ5|DQ29 1 5.49K_1%_2 VSS-B10 VDDQ-M14 VSSQ-V3 P1V5_GPUS B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10 VSS-B5 VREFD1 VSS-G5 BI P2 P13 D13 D2 VM_RESET 2 Vpp,NC1 VSS-G10 VM_ADBIB0 BI BI BI BI Vpp,NC A10 V10 VM_REFD1_B0 VM_REFD2_B0 VM_REFDC_B0 2 1UF_6.3V_2_DY 1 1UF_6.3V_2_DY 2 C5403 1 2 R5400 2.37K_1%_2 1 1UF_6.3V_2_DY 2 C5396 1 2 R5393 2.37K_1%_2 1 2 C5388 1 2 R5386 2.37K_1%_2 1UF_6.3V_2_DY A5 V5 R2 R13 C13 C2 0_5%_2_DY 1 P1V5_GPUS BI BI BI BI 2 R5436 2 P1V5_GPUS C VDDQ-M12 DQ6|DQ30 VSSQ-M5 1UF_6.3V_2 BI VDDQ-M3 DQ7|DQ31 1 J2 J1 VM_EDCB1_0 VM_EDCB1_1 VM_EDCB1_3 VM_EDCB1_2 DDR_B_WEB1# DDR_B_CSB1#_0 C5434 VM_RESET VSSQ-R11 DQ8|DQ16 0.1UF_16V_2 1 VDDQ-M1 C5452 J13 J10 0_5%_2 1 P4 P5 DDR_B_CASB1# DDR_B_RASB1# C5435 1 VDDQ-L13 2 120_1%_2 VDDQ-L2 DQ10|DQ18 VSSQ-E1 1 R5407 VSSQ-N12 DQ11|DQ19 VSSQ-E3 P1V5_GPUS 2 R5406 VSSQ-N3 WE#|CS# BI BI DDR_B_CKEB1 R5430 2 2 0_5%_2_DY VSSQ-N1 CS#|WE# VM_WCKB1_0_DP VM_WCKB1_0_DN BI BI 2.37K_1%_2 2 R5398 VSSQ-M10 G12 L12 BI BI BI BI VM_DDBIB1_0 VM_DDBIB1_1 VM_DDBIB1_3 VM_DDBIB1_2 1 DDR_B_CSB0#_0 DDR_B_WEB0# DDR_B_CLK1_DN DDR_B_CLK1_DP 2 P1V5_GPUS VDDQ-K12 1 CK VDDQ-K3 DQ12|DQ20 C5451 CK# VDDQ-H12 DQ13|DQ21 2 CKE# VDDQ-H3 DQ14|DQ22 1 J3 J11 J12 BI VDDQ-G13 DQ15|DQ23 VSSQ-F10 R5431 DDR_A_CKEB0 BI BI VSSQ-H2 VDDQ-G2 DQ16|DQ8 F 0.1UF_16V_2 CAS#|RAS# 5.49K_1%_2 BI BI RAS#|CAS# VDDQ-F14 DQ17|DQ9 C5450 G3 L3 1 DDR_B_RASB0# DDR_B_CASB0# VSSQ-E12 VDDQ-F12 DQ18|DQ10 2 VSSQ-C14 DQ19|DQ11 1 DBI0#|DBI3# VDDQ-F3 0.1UF_16V_2 VSSQ-C12 2 DBI1#|DBI2# R5432 VSSQ-C11 VM_WCKB1_1_DP VM_WCKB1_1_DN D4 D5 60.4_1%_2 DBI2#|DBI1# 1 VSSQ-C4 2 VSSQ-C3 DBI3#|DBI0# VDDQ-F1 DQ20|DQ12 DQ9|DQ17 J5 K4 K5 K10 K11 H10 H11 H5 H4 VM_B1_AA<0> VM_B1_AA<1> VM_B1_AA<3> VM_B1_AA<2> VM_B1_AA<5> VM_B1_AA<4> VM_B1_AA<6> VM_B1_AA<7> 0 1 3 2 5 4 6 7 P1V5_GPUS R5428 VSSQ-C1 60.4_1%_2 VSSQ-A14 EDC0|EDC3 1 VSSQ-A12 EDC1|EDC2 1UF_6.3V_2_DY 2 R5392 1 EDC2|EDC1 VSSQ-E1 60.4_1%_2 2 60.4_1%_2 R5391 1 DDR_B_CLK0_DN DDR_B_CLK0_DP VSSQ-A3 1UF_6.3V_2 P2 P13 D13 D2 A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14 VSSQ-A1 EDC3|EDC0 C5426 BI BI BI BI VM_DDBIB0_3 VM_DDBIB0_2 VM_DDBIB0_0 VM_DDBIB0_1 WCK23#|WCK01# 2 R2 R13 C13 C2 1 BI BI BI BI BI BI WCK23|WCK01 C5427 VM_EDCB0_3 VM_EDCB0_2 VM_EDCB0_0 VM_EDCB0_1 VDD-R5 VDD-R10 2 P4 P5 VDD-P11 WCK01#|WCK23# VDDQ-E10 DQ21|DQ13 VDD-L4 1 BI BI WCK01|WCK23 VDDQ-E5 DQ22|DQ14 VDD-L11 2 VM_WCKB0_1_DP VM_WCKB0_1_DN P1V5_GPUS D D4 D5 BI BI VM_B1_AA<8> VM_B1_AA<7..0> R5423 VM_WCKB0_0_DP VM_WCKB0_0_DN VDD-L14 DQ23|DQ15 C5449 A0/A10|A7/A8 VDDQ-D14 2 VDD-G14 VDDQ-D12 DQ24|DQ0 1 A1/A9|A6/A11 VDDQ-D3 DQ25|DQ1 0.1UF_16V_2 VDD-G11 VDDQ-D1 DQ26|DQ2 C5448 A2/BA0|A4/BA2 DQ27|DQ3 VDDQ-T3 C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10 VDD-G1 A3/BA3|A5/BA1 VDDQ-B14 2 A4/BA2|A2/BA0 VDDQ-B12 DQ28|DQ4 0.1UF_16V_2 J5 K4 K5 K10 K11 H10 H11 H5 H4 VM_B0_AA<7> VM_B0_AA<6> VM_B0_AA<5> VM_B0_AA<4> VM_B0_AA<3> VM_B0_AA<2> VM_B0_AA<1> VM_B0_AA<0> 7 6 5 4 3 2 1 0 VDDQ-B3 DQ29|DQ5 VDDQ-T14 2.37K_1%_2 BI BI VDDQ-B1 DQ30|DQ6 VDDQ-T1 1 VM_B0_AA<8> VM_B0_AA<7..0> DQ31|DQ7 B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14 VDDQ-T12 2 E GDDR5 CHANNEL B MEMORY BI C5447 DQ9|DQ17 VM_B1_ADA<31..0> B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14 VDDQ-B1 DQ30|DQ6 2 DQ31|DQ7 R5424 F M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4 VM_B0_ADA<30> VM_B0_ADA<31> VM_B0_ADA<29> VM_B0_ADA<28> VM_B0_ADA<24> VM_B0_ADA<26> VM_B0_ADA<27> VM_B0_ADA<25> VM_B0_ADA<17> VM_B0_ADA<22> VM_B0_ADA<16> VM_B0_ADA<23> VM_B0_ADA<18> VM_B0_ADA<21> VM_B0_ADA<19> VM_B0_ADA<20> VM_B0_ADA<5> VM_B0_ADA<6> VM_B0_ADA<4> VM_B0_ADA<7> VM_B0_ADA<3> VM_B0_ADA<2> VM_B0_ADA<1> VM_B0_ADA<0> VM_B0_ADA<11> VM_B0_ADA<10> VM_B0_ADA<8> VM_B0_ADA<9> VM_B0_ADA<12> VM_B0_ADA<14> VM_B0_ADA<13> VM_B0_ADA<15> 30 31 29 28 24 26 27 25 17 22 16 23 18 21 19 20 5 6 4 7 3 2 1 0 11 10 8 9 12 14 13 15 BI 5.49K_1%_2 VM_B0_ADA<31..0> M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4 VM_B1_ADA<5> VM_B1_ADA<6> VM_B1_ADA<4> VM_B1_ADA<7> VM_B1_ADA<3> VM_B1_ADA<2> VM_B1_ADA<1> VM_B1_ADA<0> VM_B1_ADA<11> VM_B1_ADA<10> VM_B1_ADA<8> VM_B1_ADA<9> VM_B1_ADA<12> VM_B1_ADA<14> VM_B1_ADA<13> VM_B1_ADA<15> VM_B1_ADA<31> VM_B1_ADA<24> VM_B1_ADA<29> VM_B1_ADA<27> VM_B1_ADA<28> VM_B1_ADA<25> VM_B1_ADA<30> VM_B1_ADA<26> VM_B1_ADA<17> VM_B1_ADA<23> VM_B1_ADA<16> VM_B1_ADA<21> VM_B1_ADA<18> VM_B1_ADA<22> VM_B1_ADA<19> VM_B1_ADA<20> 5 6 4 7 3 2 1 0 11 10 8 9 12 14 13 15 31 24 29 27 28 25 30 26 17 23 16 21 18 22 19 20 0.1UF_16V_2 8 A A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE by XXX BEN LEE 8 7 6 5 4 3 DATE February 21-OCT-2002 2 22, 2010 CODE CS SHEET Diagram DOC.NUMBER CS_1310AXXXXXX-MTR 1310xxxxx-0-0 93 1 97 of 1 1 REV A01 X01 6 5 U5101 27 D1-A VDD 26 D0+B 25 EDP_MUX_IC_SEL BI BI BI BI BI BI BI CPU_EDP_TX1_DP CPU_EDP_TX1_DN GPU_EDP_TX0_DP GPU_EDP_TX0_DN GPU_EDP_TX1_DP GPU_EDP_TX1_DN 4 D1+ D0-B 24 5 D1- D1+B 23 6 AUX+ D1-B 22 7 AUX- GND 21 8 HPD VDD 20 9 VDD AUX+A 19 BI BI CPU_EDP_AUX_DP CPU_EDP_AUX_DN 10 SEL AUX-A 18 11 HPD_SEL HPD_A 17 12 13 14 15 16 D P3V3_S 0.12A PER_PI3VEDP212ZLEX_TQFN_32P 0.1UF_16V_2 2 P3V3_S 0.1UF_16V_2 0.1UF_16V_2 GPU_EDP_AUX_DP GPU_EDP_AUX_DN 1 BI BI 1 D1+A C5515 D0- 2 D0+ 3 1 1 2 C5513 BI BI BI BI EDP_MUX_IC_SEL CPU_EDP_TX0_DP CPU_EDP_TX0_DN 1 2 EDP_TX1_DP EDP_TX1_DN EDP_AUX_DP EDP_AUX_DN BI BI BI 2 1 BI BI 1 0.1UF_16V_2 C5508 2 2 C5507 0.1UF_16V_2 1 0.12A EDP_TX0_DP EDP_TX0_DN 3 33 32 31 30 29 28 VDD HPD_B AUX-B AUX+B VDD P3V3_S D 4 C5102 7 GND AUX_SEL D0+A D0-A VDD GND 8 R5509 2 10K_5%_2 NEED A GPIO C PIN C 3 D Q5098 EC_EDP_MUX_IC_SEL 1 IN G S SSM3K7002BFU 2 TRUTH TABLE (SEL SEL /HPD_SEL/AUX_SEL ACTIVE L (CPU) PORT B IS ACTIVE H (GPU) H36 (TACH2/GPIO6) 3 OUT 2 Pin B H36 (TACH2/GPIO6) 3 OUT Q5103 SSM3K7002BFU Plug 1 E MMBT3904 GPU_EDP_HPD OUT 1 R5099 2 IN H Cable 3 Q5512 EDP_HPD#_CN MMBT3904 150K_5%_2 2 2R5095 Unplug Q5097 L Cable C 3 2 R5510 GPU_HDMI_HPD1 OUT Unplug Cable GPU_HDMI_HPDET IN 150K_5%_2 1 1 R5096 10K_5%_2 Plug Unplug L Cable Cable EDP_HPD#_CN H L GPU_HDMI_HPDET GPU_HDMI_HPD1 Plug Cable R5511 10K_5%_2 H 2 Cable R5514 2 0_5%_2 2 Plug GPU_EDP_HPD H 1 1 0_5%_2 A 1 2 1 1 E H Cable C Unplug P3V3_GPUS DGPU_HPD_INTR#_R L Cable B Plug 1 B P3V3_GPUS DGPU_HPD_INTR#_R 2 SSM3K7002BFU G Q5100 PCH-COUGARPOINT: DGPU_HPD_INTR#_R G Pin D PCH-COUGARPOINT: DGPU_HPD_INTR#_R S B D PORT A IS S FUNCTION CONTROL) Unplug Cable Plug Unplug L A H Cable L Cable INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 94 1 of 97 1 REV X01 A01 6 5 4 OUT HP_R OUT HP_L 1 1 C502 2 D TO CODEC PIN39 dgnd 2 2 C516 0.1UF_16V_2 C515 2.2UF_10V_3 25 27 1 CLOSE R504 2.2K_1%_2 0.1UF_16V_2 1 10UF_6.3V_3 C503 2 1 1 0.1UF_16V_2 1 TO CODEC R503 2.2K_1%_2 26 C512 2 28 29 30 31 CLOSE +PVDD2 dgnd 2 POWER L503 23 MONO-OUT 20 JDREF 19 SENSE-B 18 MIC2-R 17 MIC2-L 16 LINE2-R 15 LINE2-L 14 SENSE-A 13 C518 1 CLOSE CLOSE PCBEEP C CLOSE TO CODEC R512 20K_1%_2 1 2 39.2K_1%_2 R513 1 POWER IN IN 2 MICS HPS D501 NC 2 C523 10UF_6.3V_3 dgnd 12 C519 11 +PWR_AUD FBMA_11_160808_151A20T L502 1 2 2 RESET# SYNC TO CODEC PIN46 P5V_S 49 1 0.1UF_16V_2 2 R514 1 1 2 2 dgnd 0.1UF_16V_2 47K_5%_2 1 PCSPKR_PCH_3 IN 2 dgnd R515 4.7K_5%_2 B CLOSE TO CODEC PIN12 P3V3_S IN IN HDA_3S_RST# HDA_3S_SYNC 1 IN 2 HDA_3S_SDIN0 HDA_3S_BITCLK 1 C520 22PF_50V_2 2 0.1UF_16V_2 22_5%_2 1 10UF_6.3V_3 C522 2 1 OUT R505 1 22_5%_2 1 C521 dgnd R509 2 R508 2 0_5%_2 2 1 10UF_6.3V_3 C509 2 1 MIC_L TO CODEC PIN19 dgnd C508 IN dgnd C520 0.01UF_50V_2 2 MIC_R 1 R511 2 20K_1%_2 2 0_5%_2 IN BAT54_30V_0.2A 10 1 2 P3V3_S GND 1K_1%_2 2 1K_1%_2 2 1 DVDD1 SPDIFO DVDD-IO 48 9 EAPD SDATA-IN 47 8 PVDD2 1 R502 1 3 46 DVSS2 SPK-R+ 7 45 BIT-CLK OUT 6 SPK_OUT_R+ SDATA-OUT SPK-R- PD# PVSS2 5 43 44 B 21 REA_ALC269Q_VB6_GR_QFN_48P 4 PVSS1 GPIO1-DMIC-CLK SPK-L- 42 3 41 OUT R510 MIC1-L R501 4.7UF_6.3V_3 2 4.7UF_6.3V_3 2 C517 SPK-L+ SPK_OUT_R- 1 22 0.1UF_16V_2 LINE1-L FBMA_11_160808_151A20T TO CODEC 1 24 C504 1 2 10UF_6.3V_3 C505 2 1 AVDD1 VREF AVSS1 LDO-CAP CPVEE CBN CLOSE LINE1-R 1 GIO0-DMIC-DATA OUT dgnd POWER 2 2 10UF_6.3V_3 1 40 OUT C +PVDD2 C513 0.1UF_16V_2 2 MIC1-R 10UF_6.3V_3 SPK_OUT_L- MIC2-VREFO PVDD1 MIC1-VREFO-R 39 MIC1-VREFO-L AVDD2 HP-OUT-L AVSS2 38 HP-OUT-R 37 POWER SPK_OUT_L+ IN IN POWER 0.1UF_16V_2 C507 1 2 +PVDD1 32 1 35 2.2UF_10V_3 C511 34 2 1 2.2UF_10V_3 33 C510 2 TO CODEC C506 2 1 POWER FBMA_11_160808_151A20T L501 1 2 1 2 CBP CLOSE 36 U500 +PVDD1 P5V_S MIC1_VREFO_L MIC1_VREFO_R 1 +PWR_AUD 1 POWER C514 10UF_6.3V_3 D 2 +PWR_AUD MIC1_VREFO_L MIC1_VREFO_R OUT OUT 3 10UF_6.3V_3 C501 2 1 7 C500 8 CLOSE TO CODEC dgnd dgnd 2 A EC_MUTE# IN R506 1 2 1K_5%_2 NC D505 3 1 OUT AMP_PD# 1 2 1 2 3 IN MIC_IN_CLK MIC_IN_DATA A D503 VARISTOR_DY 2 NC R507 AMP_PD# 1 D502 VARISTOR_DY D504 IN HDA_3S_SDOUT IN IN BAT54_30V_0.2A HDA_3S_RST# IN INVENTEC 2 1 0_5%_2 TITLE BAT54_30V_0.2A Everest Main Board MODEL,PROJECT,FUNCTION Block dgnd SIZE C CHANGE 8 7 6 5 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 95 1 of 97 1 REV X01 A01 1 3 2 1 JACK600 G2 G1 1 2 6 3 4 5 SINGA_2SJ_T351_019_6P 100PF_50V_2 C604 2 1 100PF_50V_2 D601 2 C603 2 600OHM_25% 2 OUT OUT 2 600OHM_25% 1 L602 1 MIC_R MICS 1 L601 1 D OUT 4 VARISTOR_DY MIC_L 5 D602 6 2 7 VARISTOR_DY 8 D D600 PHP_PESD5V2S2UT_SOT23_3P 2 3 1 C L603 600OHM_25% 100PF_50V_2_DY 1 C607 2 100PF_50V_2 D603 2 C605 2 1 100PF_50V_2 C606 2 1 2 VARISTOR_DY 1 600OHM_25% 2 1 75_5%_2 L604 D605 1 2 75_5%_2 1 HP_R IN HPS OUT R603 1 2 R604 1 2 VARISTOR_DY IN VARISTOR_DY D604 2 1 HP_L C JACK601 G2 G1 1 2 6 3 4 5 SINGA_2SJ_T351_019_6P B B CN600 SPK_OUT_L+_R SPK_OUT_L-_R SPK_OUT_R-_R SPK_OUT_R+_R 1000PF_50V_2_DY C608 2 A 1 2 3 4 1000PF_50V_2_DY C611 2 1 0_5%_3 0_5%_3 0_5%_3 0_5%_3 1000PF_50V_2_DY C610 2 1 R605 R606 R607 R608 1 SPK_OUT_RSPK_OUT_R+ IN IN IN IN 1000PF_50V_2_DY C609 2 1 SPK_OUT_L+ SPK_OUT_L- G1 G1 G2 G2 1 2 3 4 ACES_50224_0040N_001_4P A INVENTEC TITLE Everest Main Board MODEL,PROJECT,FUNCTION Block SIZE C CHANGE 8 7 6 5 4 by 3 XXX BEN LEE DATE February 22, 21-OCT-2002 2 2010 CODE CS Diagram DOC.NUMBER 1310xxxxx-0-0 CS_1310AXXXXXX-MTR SHEET 1 96 1 of 97 1 REV X01 A01 8 7 6 5 4 3 2 1 U5507 76< IN VREFDQ DQL0 VREFCA DQL1 DQL2 BI FBC_CMD<22> FBC_CMD<4> FBC_CMD<20> FBC_CMD<9> FBC_CMD<6> FBC_CMD<17> FBC_CMD<3> FBC_CMD<26> FBC_CMD<1> FBC_CMD<5> FBC_CMD<19> FBC_CMD<10> FBC_CMD<7> FBC_CMD<29> FBC_CMD<18> FBC_CMD<13> N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 DQL4 A1 DQL5 A2 DQL6 A3 DQL7 A6 DQU0 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 FBC_CMD<12> FBC_CMD<14> FBC_CMD<30> 76< 69> 76< 69> 27 FBC_CMD<27> 16 11 24 8 21 FBC_CMD<16> FBC_CMD<11> FBC_CMD<24> FBC_CMD<8> FBC_CMD<21> J7 K7 K9 IN IN FBC_CLK1_DP FBC_CLK1_DN K1 L2 J3 K3 L3 A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#E9 VDDQ#F1 FBC_DQS_DP<7> FBC_DQS_DP<5> BI BI F3 C7 DQSL FBC_DQM<7> FBC_DQM<5> BI BI E7 D3 DML VSS#A9 DMU VSS#B3 BI BI VDDQ#H9 DQSU VSS#G8 DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 VSS#M9 T2 IN VSS#T1 ZQ VSS#T9 P1V5_GPUS 76< 76< B2 D9 G7 K2 K8 N1 N9 R1 R9 69> 69> 27 FBC_CMD<27> 16 11 24 8 21 1.5A VSSQ#B1 VSSQ#B9 243_1%_2 2 VSSQ#D1 VSSQ#D8 J1 L1 J9 L9 VSSQ#E2 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 IN IN FBC_CLK1_DP FBC_CLK1_DN FBC_CMD<16> FBC_CMD<11> FBC_CMD<24> FBC_CMD<8> FBC_CMD<21> FBC_DQS_DN<4> FBC_DQS_DN<6> A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 J7 K7 K9 K1 L2 J3 K3 L3 A7 DQU1 A8 DQU2 A9 DQU3 A10_AP DQU4 A11 DQU5 A12_BC# DQU6 A13 DQU7 A15 VDD#D9 BA0 VDD#G7 BA1 VDD#K2 BA2 VDD#K8 VDD#N1 CK VDD#N9 CK# VDD#R1 CKE VDD#R9 ODT VDDQ#A1 CS# VDDQ#A8 RAS# VDDQ#C1 CAS# VDDQ#C9 W E# VDDQ#D2 VDDQ#F1 BI BI F3 C7 DQSL VDDQ#H2 DQSU VDDQ#H9 BI BI E7 D3 DML VSS#A9 DMU VSS#B3 BI BI G3 B7 VSS#G8 DQSL# VSS#J2 DQSU# VSS#J8 VSS#M1 IN FBC_CMD<28> FBC_D<49> FBC_D<53> FBC_D<50> FBC_D<54> FBC_D<51> FBC_D<55> FBC_D<48> FBC_D<52> 49 53 50 54 51 55 48 52 69<> BI FBC_D<48..55> 69<> D P1V5_GPUS A14 VSS#E1 69< 69< D7 C3 C8 C2 A7 A2 B8 A3 FBC_D<32..39> VSS#P1 T2 RESET# L8 ZQ VSS#P9 VSS#T1 VSS#T9 B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5A P1V5_GPUS A1 A8 C1 C9 D2 E9 F1 H2 H9 C A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 R5512 VSSQ#B1 VSSQ#B9 243_1%_2 76< 69> FBC_CLK1_DP VSSQ#D1 IN VSSQ#D8 R5511 J1 L1 J9 L9 B1 B9 D1 D8 E2 E8 F9 G1 G9 76< 69> FBC_CLK1_DN 76<> 75<> 69> 76<> 75<> 69> IN FBC_CMD<27> IN FBC_CMD<0> IN FBC_CMD<16> IN 76<> 75<> 69> 160_1%_2 1 R5508 VSSQ#E8 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 B 2 HYNIX_H5TQ1G63DFR_11C_FBGA_96P 10K_5%_2 1 VSSQ#E2 NC#J1 B1 B9 D1 D8 E2 E8 F9 G1 G9 R5509 2 10K_5%_2 1 R5510 2 10K_5%_2 0.1UF_16V_2 0.1UF_16V_2 1uF_6.3V_2 C5517 1 C5516 1 C5515 1uF_6.3V_2 2 0.1UF_16V_2 C5514 2 0.1UF_16V_2 C5513 1 C5512 2 0.1UF_16V_2 1 1 A C5511 2 1uF_6.3V_2 2 1uF_6.3V_2 C5510 1 C5509 2 0.1UF_16V_2 1 1 1 0.1UF_16V_2 C5508 2 0.1UF_16V_2 C5507 2 0.1UF_16V_2 C5506 2 C5505 1 P1V5_GPUS 2 1 2 0.1UF_16V_2 DQU0 VSS#M9 P1V5_GPUS C5504 A6 VDDQ#E9 FBC_DQS_DP<4> FBC_DQS_DP<6> FBC_DQM<4> 69> FBC_DQM<6> 69> A1 A8 C1 C9 D2 E9 F1 H2 H9 HYNIX_H5TQ1G63DFR_11C_FBGA_96P A A5 P1V5_GPUS 2 R5513 DQL7 BI A4 VDD#B2 1 L8 VSS#P9 RESET# DQL6 A3 1 FBC_CMD<28> M2 N8 M3 DQL5 A2 35 39 34 38 32 37 33 36 2 76< 75< 76<> 75<> 69> VSS#P1 12 FBC_CMD<12> 14 FBC_CMD<14> 30 FBC_CMD<30> DQL4 A1 FBC_D<35> FBC_D<39> FBC_D<34> FBC_D<38> FBC_D<32> FBC_D<37> FBC_D<33> FBC_D<36> 1 B 46 43 40 45 44 41 42 47 69<> DQL3 A0 E3 F7 F2 F8 H3 H8 G2 H7 2 FBC_DQS_DN<7> FBC_DQS_DN<5> VDDQ#H2 VSS#E1 G3 B7 FBC_D<46> FBC_D(43) FBC_D<40> FBC_D<45> FBC_D<44> FBC_D<41> FBC_D<42> FBC_D<47> DQL1 1 C M2 N8 M3 D7 C3 C8 C2 A7 A2 B8 A3 FBC_D<40..47> BI A14 VDD#B2 12 14 30 63 56 61 57 62 59 60 58 A4 A5 VREFCA 2 22 4 20 9 6 17 3 26 1 5 19 10 7 29 18 13 DQL3 22 4 20 9 6 17 3 26 1 5 19 10 7 29 18 13 69<> FBC_D<56..63> BI N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 1 FBC_CMD<30..0> FBC_VREF1 FBC_D<63> FBC_D<56> FBC_D<61> FBC_D<57> FBC_D<62> FBC_D<59> FBC_D<60> FBC_D<58> DQL0 2 D 75< E3 F7 F2 F8 H3 H8 G2 H7 VREFDQ DQL2 FBC_CMD<22> FBC_CMD<4> FBC_CMD<20> FBC_CMD<9> FBC_CMD<6> FBC_CMD<17> FBC_CMD<3> FBC_CMD<26> FBC_CMD<1> FBC_CMD<5> FBC_CMD<19> FBC_CMD<10> FBC_CMD<7> FBC_CMD<29> FBC_CMD<18> FBC_CMD<13> 1 76< H1 M8 H1 M8 IN BI FBC_CMD<30..0> U5506 FBC_VREF1 75< INVENTEC EVEREST-M VRAM TITLE SIZE C CHANGE 8 7 6 5 4 3 by Frank Hu DATE Fri Dec 2 31 10:16:55 2010 CODE CS SHEET DOC.NUMBER CS_1310AXXXXXX-MTR 97 97 of 1 REV A01 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : GPL Ghostscript 8.64 Modify Date : 2014:04:11 17:29:36+03:00 Create Date : 2011:01:04 11:09:37+08:00 Creator Tool : PDFCreator Version 0.9.8 Metadata Date : 2014:04:11 17:29:36+03:00 Document ID : b41b9cb2-1a0b-11e0-0000-9753751e89e4 Instance ID : uuid:75bd8cea-80b5-4f1e-b1c4-255c6fb2e34a Format : application/pdf Title : Inventec Everest-M - Schematics. www.s-manuals.com. Creator : Description : Description (x-repair) : Subject : Inventec Everest-M - Schematics. www.s-manuals.com. Has XFA : No Page Count : 98 Keywords : Inventec, Everest-M, -, Schematics., www.s-manuals.com.EXIF Metadata provided by EXIF.tools