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User Manual: Motherboard Inventec Everest-M 6050A2447101 - Schematics. Free.

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COVER PAGE
WS BULID
EVEREST-M
2010.01.04
EVEREST-M
97
Tue Jan 04 11:08:28 2011
Frank Hu
1
A01
CS_1310AXXXXXX-MTR
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
INDEX
75. VRAM
67. GPU SW/POWER
65. CARDREADER & USB BOARD
55. MINI1 WLAN/Debug Card
56. MINI2 3G
57. HALL SENSOR
59. CLOCK GENERATOR
61. ME JTAG
73. VRAM
72. GPU-5
71. GPU-4
70. GPU-3
69. GPU-2
68. GPU-1
62. PICK BUTTON BOARD
63. TOUCH PAD SW BOARD
64. POWER BUTTON BOARD
74. VRAM
76. VRAM
PAGE
58. LED
60. XDP
66. EMI
50. SATA HDD/SSD & ODD CONN
41. AUDIO CODEC
40. RJ45 & TRANSFORMER
38. FAN & THERMAL
TABLE OF CONTENTS
34. PCH 7 POWER
35. PCH 8 POWER
54. BLUETOOTH CONN
32. PCH 5 USB
31. PCH 4 AXG
28. PCH 1
29. PCH 2
30. PCH 3
39. LAN
37. EC
PAGE
36. PCH 9 GND
33. PCH 6 MISC
42. AUDIO AMP
43. TPM
52. USB CONN
47. DP CONN
48. eDP CONN
17. POWER +V3S/+V5S/+V1.5S
5. POWER SEQUENCE BLOCK
6. POWER FLOW
4. SMB DIAGRAM
3. BLOCK DIAGRAM
2. INDEX
1. COVER PAGE
14. POWER VCORE
PAGE
7. PCB SCREW
16. POWER GPU NVVDD
20. CPU 1
22. CPU 3 DRAM
25. CPU 6 GND
27. DDR3 DIMM1
26. DDR3 DIMM0
24. CPU 5 POWER
23. CPU 4 POWER
21. CPU 2
18. POWER SEQ
19. POWER SEQ
53. K/B & TP/B CONN
51. E-SATA CONN
49. DB CONN USB & CARDREADER
15. POWER VCORE
46. HDMI CONN
45. CRT CONN
44. LCM CONN
13. POWER +V0.85S/+V1.8S
12. POWER VCCP/+V1.05_LAN_M
11. POWER +V1.5/+V0.75S
10. POWER +3A/+5A
9. POWER BATTERY
8. POWER CHARGER
97
2
Frank Hu
Mon Dec 27 16:49:48 2010
EVEREST-M
CS_1310AXXXXXX-MTR
A01
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
6-Cell
TOUCH PADKEYBOARD
CONN A
DC/DC & IMVP 7
LI-ION BATTERY
SIM CARD
CONNECTOR
HDR(DONGLE)
HDMI 1.4
HDMI 1.4
RJ45
VGA
HDR
HDR
R
R
RGB
HDMI
RGB
PCIE_2
PCIE
PCIE_1
HDR
HDR
35W
ATI WHISTLER XT
AMD
29MM X 29MM
PEGX16
PCIE_6
LVDS
DP
FDI
3D PANEL
15.6 WXGA LED
VRAM*4(64Mb*32)
EDP
PERICOM
eDP
MUX
eDP
VT & TXT
DMI 2.0
QC 45W OR DC 35W
SOCKET-RPGA989
IVY BRIDGE
37.5 X 37.5 X 5 mm
TDP 3.9W
25 X 25 X 2.3 mm
EC WINDBOND
NPCE791LA0DX
PCH
SPI
SATA
TPM V1.2
SPI Flash 1MB
WINB_W25Q80BVSSIG
HDA
JTAG
JTAG
AUDIO CODEC
LS
REALTEK
ALC269Q_VC
USB_13 Minicard 3G
USB_12 Bluetooth
SATA3_1: HDD
SATA3_0: SSD
SATA2_4: mSATA
SATA2_3: eSATA
EXT MIC IN
(TEST ONLY)
HDR
(TEST ONLY)
(TEST ONLY)
INTERNAL MIC IN
60-PIN PCH XDP
RJ-11ME JTAG
60-PIN CPU XDP
JTAG
DUAL CHANNEL
(1600MHZ)
204-PIN SODIMM X2
DDR3@1.5/0.75V
MAX MEMORY 8GB X2
USB 2.0
HEADPHONE/LINEOUT
TOTAL:1GB GDDR5
USB_1 eSATA PORT
USB_0 RESERVE FOR USB3.0
USB_2 RESERVE FOR USB3.0
SATA2_2: ZERO POWER ODD
SLB9635TT1.2_FW3.17
LPC
(TEST ONLY)
Gbe Phy
LEWISVILLE
INTEL 82579LM_BAM271
(100/1000)
LVDS
DISPLAYPORT 1.1
(TEST ONLY)
PCIE_3: WIFI
PCIE_4: 3G/mSATA
CARD READER
RTS5209
TI_TUSB7320
BATTERY CHARGER &
CONN B
USB 3.0
USB3.0
USB_10 Webcam
USB_5 Minicard WLAN
WINB_W25Q64BVSSIG
SPI FLASH 8MB
SPI
COUGAR POINT
Frank Hu
97
3
Mon Dec 27 16:50:03 2010
A01
CS_1310AXXXXXX-MTR
C
CS
CODE
of
2
SHEET
1
REV
A A
B B
C C
DD
1
2
3
34
45
56
67
78
8
DATE
CHANGE by
SIZE
DOC.NUMBER
INVENTEC
TITLE
BLOCK DIAGRAM
EVEREST-M
SML1DATA
SML1CLK
SML0DATA
SML1_CLK
SML1_DATA
RES 2.2K
+V3A
SML0_DATA
SML0CLK
RES 2.2K
SMB_DATA
+V3A
RES 2.2K
SSM3K7002
SSM3K7002
+V3A
LAN PHY
RES 2.2K
+V3LA
RES 2.2K
RES 2.2K
LEWISVILLE
SMB_DATA
SMB_CLK
RES 2.2K
+V3A
RES 2.2K
SMB_CLK
+V5S
RES 2.2K
+V3S
RES 2.2K
SMB_DATA_S2
SMB_DATA_S3
SMB_CLK_S3
SMB_CLK_S2
SCL2
SDA2
EC
+V3LA
RES 1.8K
3G
PEG
EC_SMB1_CLK
EC_SMB1_DATA
RES 1.8K
THERMAL IC
CHARGE IC
GPU THERMAL
BATTERY
CK505
SO-DIMM 0 SO-DIMM 1
EC_SMB2_CLK
SDA1
SCL1
MINICAR
SMB_DATA_A1
SMB_CLK_A1
XDP
PCH
WLAN
MINICARD3G
NC
SATA
0
1
SSD
HDD
2
ODD
mSATA
eSATA
5
4
3
PCIE
CardReader_RTS5209
USB3.0_TUSB7320
NC
LAN
NC
1
3
2
6
5
4
7
NC
MINICARD
WIFI
SSM3K7002
SSM3K7002
EC_SMB3_CLK
EC_SMB3_DATA
EC_SMB2_DATA
SMB DIAGRAM
8
USB
MINICARD 3G
BLUE TOOTH
NC
WEBCAM
NC
NC
NC
NC
MINICARD WLAN
NC
NC
eSATA
Reserve for USB3.0
Reserve for USB3.0
1
0
2
4
3
5
6
7
9
8
11
10
12
13
SML0_CLK
RES 3.3K RES 3.3K
+V3LA
97
Mon Dec 27 16:50:16 2010
4
EVEREST-M
Frank Hu
CS_1310AXXXXXX-MTR
CS A01
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
+V0.85S
VCCSA_PG
D0
EN_PSV
+GFX_VDD
BATT_CLK
BATT_DATA
SCL
SDA
CHARGER
GFX_VDD_PG
ACOK
PGOOD
ACIN#
TPS51217
VR_SVID_CLK
VR_SVID_ALRT#
VCLK
VDIO
EN
0.01 OHM
+VPACK
ADAPTER
AM4825P
PMOS
AM4825P
ADP_PRES
KBC_PW_ON
VR_ON
VTT_SELECT
ALERT#
D0
VO
VR_HOT#
VO
VOUT
H_PROCHOT#
TPS51218
VO
EN_PSV
VO
+V1.5
+GFX_PWRGD
VR_PWRGD
+VCC_CORE
+VGFX
PC6014
SLP_S3#_5R
SLP_S5#_5R
SLP_S3#_5R
+V0.75S
+V1.5S
+V5A
+V3LA
PC6014
PC6014
SLP_S3#_5R
+V5S
+V3S
POWER SEQUENCE BLOCK
+V1.05_VCCP
G2997
(TPS51125)
5/3.3V
VCCDRE_EN
VR_SVID_DATA
MAX17039
EN_PSV
TPS51218
EN_PSV
0.01 OHM
PMOS
TPS51218
+V1.05S
EVEREST-M
Frank Hu
Mon Dec 27 16:50:27 2010
97
5
CS_1310AXXXXXX-MTR
A01
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
RST#
TPM
MINICARD X2
RST#
V5LA (-5)
V5A (-1)
V3LA (-3)
V02
V01
VGA
(17)
VCORE
SVID
SVID
AND
GATE
CLK
CPU
SM_DRAMPWROK
SM_DRAMPWROK
RSTIN#
VCORE_PWRGOOD (18)
SVID
PWRGD
EN
IMVP7
EN
(4A)
V3.3M
EN
(10)
(11)
EN
PGD
TPS51218DSCR
TPS51218DSCR
TI
TI
PGD
V0.85S
V1.05S_VCCP
+V1.05S_VCCP_EN
AND GATE
(9)
AND GATE
SLP_S3#3R
V1.8S
(7)
AND GATE
PM_APWROK (5B)
ALLSYS_PWROK (19)
VCORE
EC_PCH_PWROK (15)
H_CPUPWRGD (16)
PM_DRAM_PWRGD (20)
PWROK
V3A
VIN
M_VREF
APWROK
(3B)
V0.75S
V1.05M
DRAMPWROK
PROCPWRGD
BUF_PLT_RST#
SYS_PWROK
GMT_G2997F6U
BUFFER
RST#
VCC
VIN
EN
VIN
V5A
AM3423PAO4406
EN
GMT
G5694F11U
V1.05S
(7)
(5A)
(11)
EN
VIN
AND GATE
(5A)
(14)
GPU_V3S
AND GATE
AM3423P
V1.05_LAN_VR_PWRGD
EN
VIN
EN
V1.05S_VCCP
AO4406
V3S
(7)
(8)
V1.5S V3.3M (4A)
V3S
VIN
EN
GPU_1.5S
(14)
V1.05_LAN_M (4A)
AM4430N
TI_TPS51125
VREG5
V1.5
V1.5_PG
VBAT
EN2
EN1
XDPLAN
(-4)
V5LA (-5)
+V5AUXON
VCC
RESET#
GMT_G686LT11U
EVEREST PWROWSEQUENCE
VBAT
VSEN
VBAT (-6)
VPACK
MAX_MAX17435ETG
ACIN
VCC
VADPTR (-7START)
RST#RST#
PLERST#
SLP_S5#
SLP_S4#
SLP_LAN#
VBAT
(3A)
VCC
PGD
V3A
TPS51218DSCR
SLP_A#
SLP_S3#
V5A
EN
VIN
SLP_S5#_3R
SLP_S4#_3R (3)
(12)
SLP_LAN#_3R (4)
SLP_S3_5R
MAIN_PWRGD
INVERTER
SLP_S3#_3R (6)
SLP_A_3R
GPIO02
V3LA
VCC
PGD
AM3423P
VIN
V1.5
G5694F11U
EN
EN
VIN
(7)
V5S
SLP_S3#_5R
PGD
V1.05S
AO4406
VIN
EN
VIN
EN
(14)
GPU_1.5S
SLP_A_3R (5M)
V1.5_CPU
(8)
AM4430N
AM3423P
V5A
VIN
EN
V1.5
INVERTER
V1.5
AO4406
VIN
EN
VIN
EN
(14)
GPU_VDD
VBAT
VCC
SC475A
SEMTECH
EC_DGPU_PWR_EN#
GPO82_TEEST#
DAO_GPIO94
DA2_GPIO96
PSDAT2_GPIO27
GPIO43_TMS
GPIO50_TD0
NMOS
GPIO03
EC
99ms
GPIO75
EC_PW_ON
V3A(-1)
ACPRES
ACPRES
V5LA
(-2)
NMOS
GPO84_XORTR#
GPIO01
V5A
(13)
VIN
EN
(15)
(0)
PWR_SWIN#_3
EC_PCH_PWROK
AM3423E
EN
POWER FLOW
VDDR_PWRGD
PM_APWROK (5B)
PWRBTN#
EC_PWRSW# (2)
LRESET# PLT_RST# (21)
GPIO36
SLP_LAN#_3R (4)
RSMRST#
(1)
RSMRST#
PCH
SLP_A_3R (5)
GPIO32_D_PWM
ACOK#
6
97
Mon Dec 27 16:50:39 2010
EVEREST-M
Frank Hu
CS_1310AXXXXXX-MTR
A01
C
CS
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
FAN
MB
CPU
PCH
PCB SCREW
GPU
MINI CARD
EVEREST-M
Fri Dec 31 10:16:56 2010
97
7
Frank Hu
1
S33
1
S19
1
S11
1
S9
1
S27
1
S17
1
S16
1
S7
1
S14
1
S26
1
S25
1
S23
1
S20
1
S12
1
S3
1
S4
1
S24
1
S22
1
S18
1
S10
1
S1
1
FIX8
1
FIX7
1
FIX6
1
FIX5
1
FIX4
1
FIX3
1
FIX2
1
FIX1
SCREW120_500_0_1P
CS_1310AXXXXXX-MTR
A01
SCREW120_0_500_1P
SCREW320_500_400_1P
SCREW300_1000_1P
SCREW330_600_800_1P
SCREW320_500_400_1P SCREW320_500_400_1P
SCREW120_0_500_1P
SCREW120_0_500_1P SCREW120_0_500_1P
SCREW300_1000_1P
SCREW300_700_1P
SCREW300_1000_1P
SCREW300_1000_1P
SCREW320_500_400_1P
SCREW300_1000_1P
FIX_MASK
SCREW330_600_800_1P SCREW330_600_800_1P
FIX_MASK FIX_MASK
SCREW330_600_800_1P
FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK
SCREW500_1000_1P SCREW300_1000_1P
C
CS
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
NEAR EC
3A : 0C00H_3.07A
512MA : 0200H_512MA
12.6V : 3140H
16.8V : 41A0H
8.4V : 40D0H
0X15
POWER CHARGER
1.5A : 0600H_1.54A
0X14
3A
2A
NEAR IC
NEAR EC
(1.68V)
(OVP MIN : 23.106V)
(OVP MAX : 24.67V)
EVEREST-M
Frank Hu
8
97
Mon Jan 03 10:52:57 2011
R6042
DIODES_SMAJ20A_13_F_2P
0_5%_2
2
1
G2
2
1
C6035
8A_125V
10PF_50V_2
ACES_91302_0047L_1_4P
MAX_MAX17435ETG+_TQFN_24P
0.1UF_25V_2_DY
2200PF_50V_2
CHG_CHG_SEN_N
PAD6000
C6812
1
NFE31PT222Z1E9L
R6001
RSC_0603_DY
4
1
2
0.1UF_25V_2
2
R6016
10_5%_5
Q6004
1
SSM3K7002BFU
C6021
1UF_10V_2
P3V3_AL
1
1
0.01UF_25V_2_DY
0.01_1%_6
CHG_VBAT_SEN_P
2
3
R6007
10K_5%_2
12
0.1UF_25V_3
1
2
1
C6023
R6020
4.7K_5%_3
R6005
1
CN6000
FUSE6000
1
C6033
2
POWERPAD_2_0610
CHG_VBAT_SEN_N
2
RSC_0402_DY
R6046
RSC_0603_DY
2
1
1
RSC_0402_DY
C6003
20
0.1UF_16V_2
0.1UF_16V_2
2
10K_5%_2
17435_LDO
TP6002
1
1
1UF_10V_2
C6022
17435_LDO
BAT54C_30V_0.2A
D6001
10K_5%_2
0_5%_2_DY
P_GATE
C6006
FDMC8884
Q6002
C6029
1UF_25V_3
R6000
1
7
2
1
C6811
1
2
1
2
R6044
2
1
R6045
2
1 1
R6043
2
1
C6814
2
1
C6813
2
1
C6817
2
1
3
2
1
1
D6004
1
2
2
2
1
2
1
R6019
R6018
R6017
G1
4
3
2
1
2
R6008
2
1
C6028
2
1
R6013
2
1
R6012
3
2
1
D6000
2
2
R6036
2
1
2
1
C6030
2
1
R6006
3
2
5
6
7
8
Q6005
2
1
4
3
2
1
L6001
3
2
4 5
6
7
8
Q6003
3
2
1
45
6
7
8
2
43
1
2
1
R6010
2
1
C6016
43 2
1
2
1
C6000
2
1
C6001
2
1
C6005
2
1
C6002
2
1
2
2
1
L6000
2
1
C6009
2
1
R6004
2
1
D6003
3 2
1
4
5678
Q6000
3 2
1
4
5678
Q6001
2
1
C6007
2
1
C6026
2
1
C6008
1
R6002
2
1
R6014
2
1
C6025
2
1
2
1
TP6000
2
1
R6003
22
21
2
1
25
14
8
4
18
23
24
5
9
3
16
15
11
17
13
6
10
19
U6000
A01
10K_5%_2
0.1UF_25V_3
CSC0402_DY
FDMC8884
4.7_5%_3 4.7UF_25V_5
4.7UF_25V_5_DY4.7UF_25V_5
0.1UF_25V_2
0_5%_2_DY
CS_1310AXXXXXX-MTR
CHG_HG
CHG_SW
CHG_LG
CHG_CHG_SEN_P
RSC_0603_DY
CSC0402_DY
4.7UF_25V_5
TPC8121
0.02_1%_6
PCMC063T_3R3MN
0_5%_2
4.7UF_25V_5
SBR3U40P1
1000PF_50V_2
0.1UF_25V_3
1K_1%_2
4.7_5%_3
1UF_25V_3
BAV99
0.01UF_50V_2
8>
AM4410NC
150_5%_3
AM4410NC
45.3K_1%_2
4.3K_1%_3
1UF_10V_2
10_5%_2
8>
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
1
2
C
A2
A1
1
G1
2
3
4
G2
IN
G
DS
S
PMOS_4D3S
G
D
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
OUT
OUT
ACIN
ACOK
LDO
VAA
GND
VCC
SCL
SDA
EN
DCIN
PDSL
CSSP
CSSN
BST
DHI
LX
DLO
PGND-PAD
CSIP
CSIN
BATT
CC
IINP
ADAPTLIM
ITHR
POWER BATTERY
EVEREST-M
9
97
Mon Jan 03 10:53:36 2011
Frank Hu
715K_1%_2
D6101
EZJZ0V500AA
D6102
2
1
GMT_G686LT11U_SOT23_5P
10K_5%_2
R6105
1
2
C6107
BAT54_30V_0.2A_DY
1
1
4
R6039
1
2
0_5%_2
U6100
360K_1%_2
R6108
1
2
R6109
2
1
R6101
1
1000PF_50V_2
1
1
EZJZ0V500AA_DY
2
FUSE6100
3
2
2
1
R6103
2
1
R6104
2
3
5
2
1
D6099
2
1
2
1
D6100
2
1
R6102
2
1
R6110
2
2
1
R6100
2
1
C6106
5
6
7
3
9
8
G4
G3
G2
G1
2
4
CN6100
EZJZ0V500AA
33_5%_2
33_5%_2
102K_1%_3
1K_5%_2
0.1UF_16V_2
SYN_200045GR009G15JZR_9P
100K_1%_2
510K_1%_2
LITTLEFUSE_R451015_15A_65V
C
CS_1310AXXXXXX-MTR
CS A01
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
NC
RESET
GND
VCC
MR
VSEN
G
G
G
G
GND
GND
SMC
SMD
TS
B-I
ID
BATT+
BATT+
10A
POWER +3A/+5A
TONSEL
7A
4A
SKIPSEL
>>GND=200/250
>>VREF=245/305
>>VRE3=300/375
>>VRE5=365/460
>>GND=PWM
>>VREF=ASKIP
>>VRE3 OR VRE5=OOA
3.8A
Mon Jan 03 10:54:36 2011
10
Frank Hu
97
EVEREST-M
RSC_0603_DY
U6200
C6212
R6210
Q6203
2
C6209
0.22UF_6.3V_2
C6213
22
17
14
13
TI_TPS51125_QFN_24P
16
18
1
CSC0805_DY
1
0.1UF_25V_3
7
1
2
SSM3K7002BFU
P5V_A
EC_PW_ON#
AON7410
24
23
C6208
VCLK
1
VR5A_HG
PAD6204
10<
POWERPAD1X1M
0.1UF_25V_3
VR3AL_PH
Q6206
4.7UF_25V_5
1
100K_5%_2
2
1
R6200 AON7410
Q6805
7
C6215
0_5%_2
C6211
VCLK
0.1UF_25V_2
19
VR3AL_LG
CSC0402_DY
37>
10<
1
C6214
4.7UF_25V_5
PAD6202
1
POWERPAD_2_0610
4.7UF_25V_5 4.7UF_25V_5
2
120K_1%_2
2200PF_50V_2
2
3
2
2
1
C6216
D6203
BAV99
3
D6202
2
1UF_25V_3
1
R6205
15.4K_1%_2
8
2
3 2
1
4
567
0.1UF_25V_2
BAV99
1
C6218
0.1UF_25V_2
L6200
1
VR5A_LG
11
1
R6204
C6206
1
Q6207
TPC8A05_H
2
1
C6200
R6037
2
1
0.1UF_25V_2
2
C6217
200_5%_2
10>
AON7410
1
1
SSM3K7002BFU
2
100K_5%_2
EC_PW_ON#
37>
10<
2
PAD6203
2
130K_1%_2
C6205
SSM3K7002BFU
2
2
R6212
1
3
1
R6201
Q6202
1
2
8
Q6200
1
PAD6205
3
C6219
R6202
3 2
1
4
5678
32
1
4
5678
Q6205
2
1
1
3
2
32
1
4
56
78
Q6204
2
1
45
6
1
2
1
2
1
C6220
2
1
2
1
1
2
3
2
D6201
2
1
1
1
3
1
R6209
2
C6204
2
1
2
1
R6208
2
1
R6207
2
1
C6202
2
1
PAD6200
2
1
L6201
2
2
1
1
C6201
2
1
C6203
2
1
R6206
2
2
1
2
2
1
PAD6201
1
2
1
2
C6210
22
C6207
2
8
3
5
2
9
4
25
20
15
6
12
10 21
CS
C
POWERPAD_2_0610
POWERPAD_2_0610
10K_1%_2
POWERPAD_2_0610
BAT54C_30V_0.2A
10UF_6.3V_3
2.2UF_25V_5
RSC_0402_DY
1UF_6.3V_2
4.7UF_25V_5
PCMC063T_3R3MN
POWERPAD_2_0610
330UF_6.3V
10K_1%_2
VR3AL_HG
VR5A_PH
TPC8A05_H 330UF_6.3V
PCMC063T_3R3MN
A01
CS_1310AXXXXXX-MTR
6.8K_1%_2
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
OUT
IN
G
DS
IN
C
A2
A1
1
2
G
DS
G
DS
1
2
1
2
+
1
2
1
2
+
1
2
S
G
D
S
G
D
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
DRVL1
LL1
DRVH1
VBST1
PGOOD
VO1
EN0
SKIPSEL
GND
VIN
VREG5
VCLK
DRVL2
LL2
DRVH2
VBST2
VREG3
VO2
TML
ENTRIP2
VFB2
TONSEL
VREF
VFB1
ENTRIP1
22A
3.7A
POWER +V1.5/+V0.75S
1.5A
3.7A
1.5A
20/20 mil
Mon Jan 03 17:25:55 2011
97
11
Frank Hu
EVEREST-M
0_5%_2
P3V3_A
RSC_0402_DY
R6314
P3V3_S
TI_TPS51218DSCR_SON_10P 2.2_5%_3
VR15_PH
1
0.1uF_25V_3
2
R6302
V1.5_PG
SLP_S4#
SLP_S3#
0_5%_2_DY
R6307
R6306
+V1.5S_CPUDDR_PG
C6312
1000PF_50V_2_DY
10
1
1uF_10V_2
22uF_6.3V_5
C6306
POWERPAD_2_0610
PCMC104T_1R0MN
5
4
3
2
1
11
200K_1%_2
R6311
CSC0402_DY
C6301
95.3K_1%_2
2
VR15_LG
R6301
4.7uF_25V_5
1
C6305
2
U6302
2
2.2uF_6.3V_3
C6303
4.7uF_25V_5
TPCA8065_H
1
2
10
2
SLP_S4#
6
PAD6300
2
POWERPAD_2_0610
3
U6300
Q6301
TPCA8A02_H
C6815
1
560uF_2.5V
11.5K_1%_2
2200PF_50V_2
2
C6304
2
1
2
C6302
C6309
1
P1V5
4.7uF_25V_5
4
2
VR15_HG
POWERPAD_2_0610
CS
C
POWERPAD_2_0610
10K_1%_2
22uF_6.3V_5
18<
0_5%_2
30>
11<
37<
11<
37<
30>
17<18<37<
CS_1310AXXXXXX-MTR
0.1UF_16V_2
A01
4.7_5%_3
GMT_G2997F6U_MSOP10_10P
30>
9
6
8
7
Q6300
8765
4 3
8765
4
1
23
PAD6301
1
2
PAD6303
1
2
PAD6302
2
1
2
1
2
1
R6310
1 1
2
1
2
C6300
1
2
1
2
R6304
1
R6303
1
8 4
7
9
11
2
5
C6307
1
2
1
C6308
1
2
C6311
1
2
2
L6300
1
2
3
1
1
2
1
2
R6047
1
2
1
2
1
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
+
IN
IN
IN
1
2
TML
VTTREF
S3
GND
S5
VIN
VTTSNS
PGND
VTT
VLDOIN
VDDQSNS
OUT
1
2
1
2
1
2
S
G
D
NMOS_4D3S
D
G
S
DRVL
V5IN
SW
DRVH
VBST
GND
RF
VFB
EN
TRIP
PGOOD
1.5A
28A
POWER VCCP/+V1.05_LAN_M
3.3A
0.5A
EVEREST-M
12
97
Mon Jan 03 17:26:41 2011
Frank Hu
POWERPAD_2_0610
2
R6403
2.2UF_6.3V_3
2
P3V3_A
U6401
GMT_G5694F11U_SOP_8P
8
2
SLP_LAN#
R6452
1
1
20K_1%_2
1
2
RSC_0402_DY
PAN_ETQP4LR36WFC_4P
0.22UF_25V_3
1
VSS_SENSE_VTT
2
0_5%_2
9.53K_1%_2
R6413
0.1UF_10V_2_DY
C6415
7
3
VRVCCP_PH
3
2
0_5%_2
13<
VTT_PG
1
1
C6410
1
PAD6403
PAD6401
2
POWERPAD_2_0610
4.7UF_25V_5
2
4.7UF_25V_5
2
Q6401
TI_TPS51218DSCR_SON_10P
U6400
R6411
4
VRVCCP_LG
1
10K_5%_2
2
1
PAD6400
2
1
C6450
2
1
C6451
2
1
R6451
2
1
R6450
2
1
R6454
2
1
C6453
2
C6452
2
1
C6454
2
1
L6450
1
9
2
6
7
3
4
5
2
1
R6415
1
R6416
2
R6414
2
1
R6417
1
2
1
R6410
2
1
C6414
2
1
2
1
C6407
1
2
1
PAD6402
2
2
1
C6401
1
C6406
1
C6403
2
4
2
1
L6403
3 2
1
4
5 6 8
Q6400
3 2
1
4
5 6 7 8
2
1
2
1
R6402
1
C6411
2
R6400
2
1
R6405
2
1
C6413
10
7
8
5
11
6
9
+V1.05_LAN_M
44.2K_1%_2
POWERPAD_2_0610
TPCA8065_H
22UF_6.3V_5
CS_1310AXXXXXX-MTR
A01
POWERPAD_2_0610
VRVCCP_HG
VCC_SENSE_VTT
CSC0402_DY
37< 19<
30>
0_5%_2
0.1UF_16V_2
10_5%_3
10UF_6.3V_3
470K_1%_2
P3V3_S
2.2_5%_3
0.1UF_16V_2
LTF5022T_2R2N3R2_LC
10K_1%_2
3.09K_1%_2 CSC0402_DY
23>
TPCA8057_H
1000PF_50V_2_DY
100_5%_2
200_1%_2
23>
560UF_2.5V
4.7UF_25V_5
C
CS
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
1
2
IN
OUT
REF
FB
LX
TML
GND
PGND
EN
VCC
VIN
IN
IN
+
1
2
1
2
1
2
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
DRVL
V5IN
SW
DRVH
VBST
GND
RF
VFB
EN
TRIP
PGOOD
POWER +V0.85S/+V1.8S
3A
1.6A
6A
LOW - 0.9V
HIGH - 0.8V
EVEREST-M
97
13
Frank Hu
Mon Jan 03 17:27:17 2011
PCMC063T_3R3MN
2
POWERPAD_2_0610
C6508
0.1UF_10V_2_DY
1
PAD6503
330UF_2V_9MR_PANA_-35%
200_1%_2
R6506
6.49K_1%_2
2
1000PF_50V_2_DY
200_1%_2
1
TI_TPS51217DSCR_SON_10P
2
AON7410
Q6500
11
R6509
CSC0402_DY
2
78.7K_1%_2
LMBT3904LT1G
U6500
6
2.2UF_6.3V_3
1
1
5
4.7UF_25V_5
VR85_PH
7
6
1
RSC_0402_DY
Q6501
1
1
R6510
VCCSA_SEL
24>
1
VR85_LG
C6504
P3V3_A
1
0_5%_3
VR85_HG
1
2
10K_5%_2
R6501
10
4
1
C6507
40.2K_1%_2
2
1
R6500
9
1
2
0_5%_2
3
1
2
PVBAT
TPC8A05_H
2
R6511
C6505
47PF_50V_2
0.22UF_25V_3
4.7UF_25V_5
L6500
C6514
10UF_6.3V_3
0.1UF_16V_2
GMT_G5694F11U_SOP_8P
9
LTF5022T_2R2N3R2_LC
13K_1%_2
POWERPAD_2_0610
PAD6501
1
U6502
8
3 2
5 7 8
3 2
1
4
678
4
2
5
8
2
1
R6517
2
1
R6516
2
1
2
1
C6512
2
1
R6515
2
1
R6514
2
1
C6515
2
1
C6511
2
1
2
C6506
2
1
2
1
R6505
R6504
2
1
R6503
2
2
1
2
1
C6501
2
1
C6500
2
1
C6502
C6503
1
2
2 3
Q6502
2
1
3
Q6503
R6507
2
1
C6510
2
1
2
1
R6508
1
R6502
2
2
1
PAD6500
2
2
1
C6513
2
1
L6502
1
2
6
7
3
4
5
CS_1310AXXXXXX-MTR
22UF_6.3V_5
CSC0402_DY
10_5%_3
0.1UF_16V_2
20K_1%_2
P5V_A
1K_1%_2
10K_5%_2
SSM3K7002BFU
10K_1%_2
20K_1%_2
4.7UF_25V_5
POWERPAD_2_0610
CS A01
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
+
IN
B
C E
G
DS
1
2
1
2
1
2
REF
FB
LX
TML
GND
PGND
EN
VCC
VIN
S
G
D
NMOS_4D3S
D
G
S
VFB
VBST
V5IN
TRIP
TRAN
SW
PGOOD
GND
EN
DRVL
DRVH
CATCH R
POWER VCORE
10A
FOLLOW BERLIN 10RG
FOLLOW BERLIN 10RG
CATCH R
Mon Jan 03 17:28:44 2011
Frank Hu
97
14
EVEREST-M
1
470PF_50V_2
20.5K_1%_2
IMAXA
14<
10_1%_2
1
C6608
14<
14<
14<
15<
15<
15<
15<
VRCPU_HG2
2.2UF_6.3V_2
IMONA
14<
53
VRCPU_HG3
CPU_BST3
VRCPU_PH3
VRCPU_LG3
12
10
VRAXG_LG1
GPU_BST1
VRAXG_HG1
14<
14<
IMAXA
51
50
49
R6602
1
100_1%_2
U6600
54
56
52
MAX_MAX17039GTN+_TQFN_56P
0_5%_2
15<
VRCPU_PH2
8
TONA
9
VRAXG_PH1
CCVB
IMONB
FBB
THERMA
THERMB
470PF_50V_2
C6610
TP6600
13
14<
24
25
26
27
28
1
5.1K_1%_2
14>
14>
VBOOTB
SRB
14<
14<
22
40
41
42
15<
14<
SRA
VBOOTA
14
IMAXB
14<
CS
CS_1310AXXXXXX-MTR
C
14<
24>
20.5K_1%_2
23>
14<
0_5%_2 115K_1%_2
470PF_50V_2
0_5%_2 115K_1%_2 100K_5%_2
4.87K_1%_2
14<
14<
14<
14<
14<
P5V_A
14<
14<
14<
14<
14<
P3V3_S
178K_1%_2
+VBAT_CPU
4.87K_1%_2
14<
P5V_A
14<
2.2UF_6.3V_2
TP24
2.2UF_6.3V_2
15<
15<
P5V_A
14<
15<
15<
15<
14<
14<
14<
14<
14<
14<
14<
14<
1000PF_50V_2
1000PF_50V_2
1000PF_50V_2
10_1%_2
10_1%_2
23>
14<
10_1%_2
15<
15<
15<
15<
PVBAT
POWERPAD_2_0610
4.7UF_25V_5
1000PF_50V_2
4.7UF_25V_5 4.7UF_25V_5
PVAXG
4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5
+VBAT_CPU
4.7UF_25V_5
VSSAXG_SENSE
VSSSENSE
THERMB
SRB
VBOOTB
IMAXB
TONB
THERMA
SRA
VBOOTA
CCVA
TONA
PH3_PWM
GNDSA
CPU_BST2
VRCPU_LG1
VRCPU_LG2
VRCPU_HG1
CPU_BST1
PH3_SKIP#
PH3_PWM
VRCPU_PH1
CCVA
IMONA
GNDSA
FBA
GNDSB
GNDSB
FBB
A01
FBA
14<
P5V_A
178K_1%_2
+VBAT_CPU
P3V3_A
0_5%_2
P5V_A
1UF_6.3V_2
P5V_A
470PF_50V_2
100_1%_2
VCCSENSE
P5V_A
14<
CCVB
P3V3_A
100K_5%_2
1
37
16
48
46
7
36
38
29
19
57
30
18
17
35
43
15
20
34
23
21
5
6
4
3
39
11
2
55
44
45
C6618
1
2
R6623
2
R6611
1
1
2
C6611
1
2
C6617
1
2
C6616
1
2
TP6601
1
R6616
2
R6614
1
2
R6612
1
2
C6614
1
2
C6613
1
2
R6603
1
2
C6609
1
2
R6601
1
2
2
U6602
1
8
4
3
7
9
2
6
5
C6619
1
2
PAD6600
1
2
C6601
1
2
C6600
1
2
C6602
1
2
C6603
1
2
C6604
1
2
C6605
1
2
C6606
1
2
C6607
1
2
R6622
1
2
R6620
1
2
R6624
1
2
R6626
1
2
R6618
1
2
R6619
1
2
C6615
1
2
R6621
1
2
R6606
1
2
R6625
1
2
R6608
1
2
R6627
1
2
R6607
1
2
1
2
R6609
1
2
R6617
1
2
R6604
1
22
1
14<
PH3_SKIP#
33
31
32
9.53K_1%_2
R6605
2
MAX_MAX8791GTA+_TQFN_8P
0_5%_2
C6612
IMONB
14<
TONB
2K_5%_2
1
10K_5%_2
2
R6610
2K_5%_2
15<
47
1
R6038
1
2 2
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
LX
PWM
SKIP
VDD
PAD
DH
BST
DL
GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
2
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
N.C.
IMONA
CCVA
DRSKIP
PWM_OUT
BSTA1
DHA1
DLA2
CSNA3
LXA2
VRA_READY
VRB_READY
CSPA1
CSNA1
CSNA2
CSPA2
CSPA3
IMAXA
IMAXB
TMAX
VR_HOT#
AGND
ALERT#
VDIO
VCLK
VCC
TONA
TONB
CSPB
CSNB
VR_ENABLE
DLG
VDDB
DLB
BSTB
DHB
VBOOTB
VBOOTA
CCI2
CCI1
SRA
SRB
THERMA
THERMB
FBB
GNDSB
IMONB
CCVB
LXB
GND
DHA2
BSTA2
VDDA
DLA1
LXA1
GNDSA
FBA
POWER VCORE
33A
60A
Mon Jan 03 17:29:38 2011
15
97
Frank Hu
EVEREST-M
2
14<
4.7_5%_3
R6718
1
+VBAT_CPU
0.22UF_25V_3
2.2_5%_3
R6716
2.2_5%_3
0.22UF_25V_3
R6723
L6700
2
VRAXG_PH1
1
2
L6703
0.47UF_6.3V_2
2
C6710
RSC_0402_DY
2
3.6K_1%_2
R6714
2
VRCPU_HG2
14<
L6701
TPCA8065_H
CS
C
14<
14<
14<
14<
14<
14<
14<
+VBAT_CPU
2.37K_1%_2
0.47UF_6.3V_2
RSC_0402_DY
10K_5%_NTC
PAN_ETQP4LR36ZFC_4P
4.7_5%_3
14<
14<
TPCA8065_H
14<
14<
TPCA8065_H
PAN_ETQP4LR36ZFC_4P
RSC_0402_DY
PAN_ETQP4LR36ZFC_4P
14<
+VBAT_CPU
1500UF_2V
PVCORE
470UF_2V
VRCPU_LG3
VRCPU_PH3
VRCPU_HG3
VRCPU_LG1
VRCPU_HG1
VRCPU_PH1
CPU_BST3
CPU_BST1
VRAXG_LG1
VRAXG_HG1
GPU_BST1
VRCPU_LG2
CPU_BST2
A01
CS_1310AXXXXXX-MTR
GPU_CSP1
3.6K_1%_2
10K_5%_NTC
2.37K_1%_2
0.47UF_6.3V_2
3300PF_50V_2
TPCA8057_H
3.6K_1%_2
3300PF_50V_2
4.7_5%_3
TPCA8057_H
TPCA8065_H
2.2_5%_3
0.22UF_25V_3
TPCA8057_H
PAN_ETQP4LR36ZFC_4P
4.7_5%_3
2.37K_1%_2
14<
VRCPU_PH2
2.2_5%_3
14<
GPU_CSN1
8765
4
1
23
Q6703
8765
4
1
23
C6707
1
2
R6705
1
2
C6706
1
2
Q6705
8765
4
1
23
1
2
L6702
1
3 4
R6711
1
2
C6709
1
Q6704
8765
4
1
23
C6711
1
2
C6712
1
2
Q6701
8765
4
1
23
Q6700
8765
1
23
C6700
1
2
R6700
1
2
1
3 4
R6717
1
2
C6714
1
2
Q6707
8765
4
1
23
Q6706
8765
4 23
C6713
1
2
1
2
3 4
1
2
C6701
2
1
3
C6704
1
2
3
1
2
3 4
R6706
1
2
R6708
1
2
R6709
2
C6708
1
2
R6701
1
2
R6703
1
2
R6704
1
2
C6703
1
2
R6719
1
2
R6721
1
2
R6722
1
2
C6715
1
2
1
2
1
2
R6715
1
R6707
1
22
R6720
1
2
R6702
1
2
3300PF_50V_2
0.47UF_6.3V_2
1
RSC_0402_DY
TPCA8057_H
2.37K_1%_2 10K_5%_NTC 3.6K_1%_2
3300PF_50V_2
1
R6713
10K_5%_NTC
1
R6712
0.22UF_25V_3
4
1
R6710
2
+VBAT_CPU
Q6702
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
+
IN
IN
IN
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
IN
IN
IN
IN
NMOS_4D3S
D
G
S
NMOS_4D3S
D
G
S
IN
IN
IN
NMOS_4D3S
D
G
S
IN
IN
IN
NMOS_4D3S
D
G
S
IN
NMOS_4D3S
D
G
S
IN
IN
IN
IN
+
NMOS_4D3S
D
G
S
3.5A
POWER GPU NVVDD
1
0
1
0
VID1
VOLTAGE LEVEL
NVVDD
1V
0.975V
0.825V
30A
CONNECT TO GPU
FOR OPTIMUS SHUTDOWN SOLUTION
VID0
0
0
16
97
Tue Jan 04 00:17:23 2011
EVEREST-M
Frank Hu
TI_TPS51217DSCR_SON_10P
C6800
47PF_50V_2
2
5
11
1
R6805
U6800
8
VRGPU_HG
2
C6803
TPCA8065_H
SSM3K7002BFU
40.2K_1%_2
3
3
10
4.7UF_25V_5
L6800
2
2
470UF_2V
100_5%_2
R6810
2
PAD6801
1
0_5%_3
0.1UF_25V_2
1
PAD6800
POWERPAD_2_0610
2
1
C6810
2
1
R6048
2
1
C6816
2
1
R6808
2
2
1
3
Q6804
2
1
D6800
1
2
1
R6803
2
1
C6807
2
1
C6805
1
3 2
1
4
5 6 7 8
Q6800
2
1
C6809
2
1
R6806
2
1
R6041
2
1
R6040
2
1
R6807
2
1
Q6803
2
1
C6802
2
1
R6809
2
1
C6806
1
C6808
2
1
PAD6803
2
2
1
2
1
43
1
3
2
1
4 5
6
7
8
Q6802
3
2
1
4 5
6
7
8
Q6801
2
1
C6804
2
R6804
4 7
1
6
9
A01
TPCA8A02_H
POWERPAD_2_0610
POWERPAD_2_0610
470UF_2V470UF_2V
0_5%_2
28.7K_1%_2
SBR3U40P1_DY
VRGPU_LG
86.6K_1%_2
CS_1310AXXXXXX-MTR
CS
C
100PF_50V_2
33.2K_1%_2
+GPU_NVVDD_L
VRGPU_PH
68>
4.7UF_25V_5
10.2K_1%_2
CSC0402_DY
4.7UF_25V_5
PAN_ETQP4LR36WFC_4P
TPCA8A02_H
2.2UF_6.3V_3
SSM3K7002BFU
1K_1%_2
0_5%_2
0_5%_2
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
+
G
DS
OUT
NMOS_4D3S
D
G
S
G
DS
+
+
1
2
1
2
1
2
S
G
D
S
G
D
VFB
VBST
V5IN
TRIP
TRAN
SW
PGOOD
GND
EN
DRVL
DRVH
POWER +V3S/+V5S/+V1.5S
WS
11.5A
EVEREST-M
Frank Hu
Fri Dec 31 10:16:26 2010
97
17
2
1
R7036
3
2
1
45
6
7
8
Q7002
4
36
5
2
1
Q7004
4
36
5
2
1
Q7005
2
1
R7034
2
1
C7027
2
1
R7035
2
1
3
Q7088
2
1
3
Q7090
2
1
R7039
2
1
C7030
2
1
PAD7002
2
1
R7032
2
1
3
Q7000
2
1
3
Q7001
2
1
R7033
2
1
C7026
2
1
C7029
2
1
PAD7001
2
1
3
Q7003
2
1
R7038
2
1
PAD7000
2
1
C7028
2
1
R7037
P1V5
POWERPAD_2_0610
100K_5%_2
SLP_S3#_15R
SLP_S3_5R
CS_1310AXXXXXX-MTR
200_5%_3
17>
SLP_S3#_15R
22_5%_2
POWERPAD_2_0610
SSM3K7002BFU
P15V_A
17<
CS
SLP_S3_5R
SLP_S3_5R
SLP_S3_5R
SLP_S3#_15R
SLP_S3#
P3V3_S
17> 17< 19<
SSM3K7002BFU
P1V5_S
200_5%_2
POWERPAD_2_0610
680PF_50V_2
22UF_6.3V_5
22UF_6.3V_5
CSC0402_DY
17>19<
AON7410
750K_1%_2
19< 18<
24<
SSM3K7002BFU
P0V75_S
SSM3K7002BFU
19< 17< 17>
P3V3_AL
AO6402AL
P5V_AL
0_5%_2
24<
19<18<17<
SSM3K7002BFU
P5V_S
CSC0402_DY
0_5%_2
10K_5%_2
37<
18<
11<
30>
AO6402AL
P5V_A
A01
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
1
2
NMOS_4D3S
D
G
S
D
G
S
NMOS_4D1S
D
G
S
NMOS_4D1S
IN
OUT
IN
G
DS
G
DS
OUT
1
2
OUT
IN
G
DS
OUT
G
DS
IN
1
2
G
DS
POWER SEQ
WS
Frank Hu
EVEREST-M
Fri Dec 31 10:16:27 2010
18
97
2
1
C7000
2 3
1
Q7064
2
1
R7000
2
1
R7009
2
1
R7030
2
1
C7002
2
1
R7029
2
1
3
D7001
2
1
R7001
2
1
C7025
2
1
R7028
2
1
3
Q7053
2
1
C7008
2
1
R7010
2
1
C7003
2
1
R7007
2
1
R7008
2
1
C7005
5
2
4
3
1
U7005
2
1
R7031
2
1
R7027
2
1
R7016
2
1
R7026
2
1
R7014
2
1
R7015
2
1
R7013
2
1
C7013
5
4
3
2
1
U7004
2
1
R7023
2
1
3
D7000
2
1
R7024
2
1
R7025
2
1
3
Q7065
2
1
C7006
2
1
C7004
2
1
R7006
2
1
C7012
5
4
3
2
1
U7003
2
1
R7002
2
1
R7003
2
1
C7001
2
1
R7004
2
1
C7011
5
4
3
2
1
U7002
2
1
C7010
5
4
3
2
1
U7001
2
1
C7009
2
1
R7005
5
4
3
2
1
U7000
P3V3_A
+V1.05_LAN_PG
1K_5%_2
TC7SZ08FU
DRAMRST_CNTRL_CPU
DDR3_DRAMRST#
26>
BSH111
4.99K_1%_2
CPU_DRAMRST#
1K_5%_2
P1V5
27>
20>
0_5%_2
A01
CS_1310AXXXXXX-MTR
CS
C
0_5%_2
EC_PCH_PWROK
38<
0.1UF_16V_2
P3V3_A
59<
11>
+V1.5S_CPUDDR_PG
P3V3_A
SLP_S3#
0_5%_2
+V1.05_LAN_PG
37<
18<
10K_5%_2
TC7SZ08FU
3.3K_5%_2
0.1UF_16V_2
309K_1%_2
10K_5%_2
+V1.05_LAN_M
110K_1%_2
LMBT3904LT1G
0_5%_2
1000PF_50V_2
+V1.5S_CPUDDR_PG
470PF_50V_2
+V1.05S_VCCP_EN
PM_APWROK
ALLSYS_PWROK
VR_PWRGD
DRAMRST_CNTRL_PCH
DRAMRST_CNTRL_EC
SLP_A#
SLP_A#
V1.5_PG
MAIN_PWRGD
VCCSA_PG
SLP_S3#_15R
12<
0.1UF_16V_2
P3V3_A
0_5%_2
0.1UF_16V_2
P3V3_A
30<
P3V3_A
0.1UF_16V_2
TC7SZ08FU
0.1UF_10V_2_DY
37<
17< 11<
30>
14>
37>30<
18<
TC7SZ08FU
P3V3_A
P3V3_A
10K_1%_2
0.1UF_16V_2
1K_5%_2
0_5%_2_DY
BAT54_30V_0.2A
18<19<
37< 30>
0.1UF_16V_2
18>
P3V3_A
0.1UF_16V_2
1UF_6.3V_2
19< 30>
+V3M
100K_5%_2
10K_5%_2_DY
0_5%_2
20<
1M_1%_2
TC7SZ08FU
60> 37<
14<
AZV331KTR_E1
100K_1%_2
1000PF_50V_2
11<
20<
18<
0.1UF_10V_2_DY
P3V3_SP3V3_A
10K_5%_2
SSM3K7002BFU
10K_5%_2
BAT54_30V_0.2A
330_5%_2
19<
17>
24<
17<
P1V5_CPUDDRS
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
IN
+
-
OUT
OUT
IN
IN
IN
OUT
+
-
IN
NC
G
DS
OUT
OUT
IN
IN
OUT
+
-
IN
IN
OUT
+
-
IN
OUT
B
C E
IN
NC
G
DS
OUT
+
+
-
-
OUT
+
-
POWER SEQ
EVEREST-M
19
97
Fri Dec 31 10:16:27 2010
Frank Hu
3
2
1
45
6
7
8
Q7052
3
2
1
45
6
7
8
Q7062
2
1
C7024
2
1
C7023
2
1
C7022
2
1
C7021
2
1
C7020
2
1
C7007
2
1
R7012
2
1
R7011
2
1
R7017
2
1
C7017
2
1
C7015
2
1
C7014
2
1
R7018
2
1
R7019
2
1
C7019
2
1
R7021
2
1
C7018
2
1
C7016
2
1
R7020
2
1
R7022
2
1
PAD7003
4
3 6
5
2
1
Q7006
2
1
3
Q7051
2
1
3
Q7058
2
1
3
Q7059
2
1
3
Q7060
2
1
3
Q7061
2
1
3
Q7063
A01
P3V3_A
AON7410
0.1UF_10V_2_DY
200_5%_2
CS_1310AXXXXXX-MTR
SLP_S3#_15R
SLP_A#
SLP_S3_5R
SLP_LAN#
17<
24<
18< 17>
37<
18< 30>
SSM3K7002BFU
P1V5
SSM3K7002BFU
0_5%_2
AON7410
17>17<
470PF_50V_2
SSM3K7002BFU
200_5%_2
680PF_50V_2
SSM3K7002BFU
P1V5_CPUDDRS
10K_1%_2
P5V_A
220K_5%_2
P5V_A
+V1.05_LAN_M
10UF_6.3V_3
+V1.05M
P1V05_VCCPS
0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2
12<
30>37<
SSM3K7002BFU
0.1UF_16V_2
P1V5
P1V5_CPUDDRS
SSM3K7002BFU
200_5%_3
POWERPAD_2_0610
10UF_6.3V_3
+V1.05S
47K_5%_2
P3V3_A
100K_5%_2
0.01UF_50V_2
330PF_50V_2_DY
AM3423P
10UF_6.3V_3
+V3M
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
S
PMOS_4D1S
G
D
NMOS_4D3S
D
G
S
G
DS
NMOS_4D3S
D
G
S
G
DS
IN
IN
G
DS
G
DS
G
DS
IN
1
2
IN
G
DS
(Default)
Place close to CPT and NVRAM connector
DMI&FDI TerminationVoltage
Set toVss when LOW
Set toVcc when HIGH
NV_CLE
CPU 1
LOW IN C6/C7
CLKOUT_DMI_CLKGEN_DN
WS
REMOVE CLKOUT_DMI_CLKGEN_DP
Frank Hu
EVEREST-M
Fri Dec 31 10:16:28 2010
97
20
2
1
R4513
2
1
3
Q4500
2
1
R4512
2
1
R4511
2
1
C4559
5
4
1
2
3
U4501
4
5
3
1
2
U4502
2
1
R4508
2
1
R4509
2
1
R4558
2
1
R4532
2
1
R4500
2
1
C4504
2
1
R4510
2
1
R4536
2
1
R4516
2
1
R4506
2
1
R4538
2
1
R4537
2
1
R4557
2
1
C4570
2
1
R4552
2
1
R4555
2
1
R4553
2
1
R4554
2
1
R4556
2
1
R4529
2
1
R4505
2
1
R4507
2
1
R4531
2
1
R4530
2
1
R4541
2
1
R4542
2
1
R4533
2
1
R4534
2
1
R4535
2
1
R4517
1
TP4500
AP33
AP30
AR27
AN32
AP26
AR28
AR26
A4
A5
AK1
R8
V8
AN34
AR33
AL32
C26
AP27
AP29
AM34
AN33
A15
A16
AL35
AL33
AR32
AT31
AR31
AP32
AT30
AR30
AR29
AT28
A27
A28
CN4500
0_5%_2
H_SNB_IVB#
H_CATERR#_R
43_5%_2
56_5%_2
0_5%_2
PM_THRMTRIP#_R
SM_RCOMP2
CLK_DP_PCH_CPU_R_DN
CLK_DP_PCH_CPU_R_DP
CLKOUT_DMI_PCH_R_DN
CLKOUT_DMI_PCH_R_DP
CLK_DMI_PCH_DN
0_5%_2
0_5%_2
CLK_DMI_PCH_DP
CLK_DP_PCH_CPU_DP
20>
H_PECI
PM_THRMTRIP#
H_PECI_R
PM_DRAM_PWRGD_R
0_5%_2
H_PM_SYNC
H_CPUPWRGD
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
P3V3_S
H_CPUPWRGD_R
H_PM_SYNC_R
SM_RCOMP1
SYS_RESET#_R
H_TDO
75_5%_2
BUF_PLT_RST# BUF_PLT_RST#_CPU
32<>
43<
56< 55<
43_5%_2
0.1UF_16V_2
P1V05_VCCPS
0_5%_2_DY
20<
TSB_TC7SZ07FU_SSOP_5P
P1V05_VCCPS
37<>
33<
200_5%_2
P1V5_CPUDDRS
H_BPM7_XDP#
H_BPM6_XDP#
H_BPM5_XDP#
H_BPM4_XDP#
H_BPM3_XDP#
H_BPM2_XDP#
H_BPM1_XDP#
H_BPM0_XDP#
H_TDI
H_TRST#
H_TMS
H_TCK
H_PREQ#
H_PRDY#
BUF_PLT_RST#_CPU
H_PROCHOT#_R SM_RCOMP0
CPU_DRAMRST#
H_PROCHOT#
33>
39_5%_2
0.1UF_16V_2
4.7K_5%_2
NV_CLE
130_1%_2
P1V8_S
2.2K_5%_2
14>
30<>
P3V3_A
60>
NXP_74AHC1G09GV_SOT753_5P
SLP_S3_5R
PM_DRAM_PWRGD
P3V3_A
200_5%_2
H_CPUPWRGD_R
+V1.5S_CPUDDR_PG
H_SNB_IVB#
H_TDI
H_PREQ#
H_TRST#
H_TCK
H_TMS
SYS_RESET#
CLK_DP_PCH_CPU_DN
10K_5%_2
18<
18>
30>
20>
100K_5%_2_DY
32>
SSM3K7002BFU
47PF_50V_2
62_5%_2
0_5%_2_DY
20>
33>
0_5%_2
20< 60>
60>20<
20< 60>
20< 60>
60<>
60<>
60>20<
51_5%_2
51_5%_2
51_5%_2_DY
51_5%_2
60<
51_5%_2
P1V05_VCCPS
60<
60<
60<
60<
60<
60<
60<
60<
60<>
20<60>
60> 20<
20<60>
60<>
20<60>
60<>
0_5%_2
60> 30<
20<60>
60<
200_1%_2
25.5_1%_2
140_1%_2
18>
0_5%_2
29>
29>
29>
29>
CS_1310AXXXXXX-MTR
CS A01
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
OUT
IN
OUT OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
IN
BI
OUT
IN
G
DS
IN
VCC
OUT-Y
NC
IN-A
GND
Y
VCC
GND
B
A
JTAG & BPM
MISCDDR3
PWR MANAGEMENT
THERMAL MISC
CLOCKS
UNCOREPWRGOOD
PROC_SELECT#
SKTOCC#
PM_SYNC
BPM#[7]
BPM#[6]
BPM#[5]
BPM#[4]
BPM#[3]
BPM#[2]
BPM#[1]
BPM#[0]
DBR#
TDO
TDI
TRST#
TMS
TCK
PREQ#
PRDY#
RESET#
SM_DRAMPWROK
THERMTRIP#
PROCHOT#
PECI
CATERR#
DPLL_REF_CLK
DPLL_REF_CLK#
BCLK
BCLK#
SM_RCOMP[0]
SM_DRAMRST#
SM_RCOMP[2]
SM_RCOMP[1]
CPU 2
CLOSE to CPU
21
97
Fri Dec 31 10:16:57 2010
EVEREST-M
Frank Hu
2
1
C4516
2
1
C4515
2
1
C4520
2
1
C4519
2
1
C4518
2
1
C4517
2
1
C4524
2
1
C4523
2
1
C4522
2
1
C4521
2
1
C4526
2
1
C4525
2
1
C4527
2
1
C4528
2
1
C4530
2
1
C4529
2
1
C4531
2
1
C4532
2
1
C4533
2
1
C4534
2
1
C4535
2
1
C4536
2
1
C4537
2
1
C4538
2
1
C4539
2
1
C4540
2
1
C4542
2
1
C4541
2
1
C4543
2
1
C4544
2
1
C4545
2
1
C4546
2
1
R4544
2
1
R4545
H28
J27
J29
K27
K30
L28
L31
M30
D25
E26
D27
F28
E28
G28
M33
M28
H29
J28
J30
K28
K31
L29
L32
M31
E25
F26
D28
F27
E29
G27
M32
M29
E35
F30
F33
G31
G34
H32
H35
K34
B32
C33
E31
D34
F32
E33
L35
J33
F35
G30
G33
H31
H34
J32
J35
L34
C32
B33
D31
D33
E32
E34
M35
K33
H22
J21
J22
H20
F17
D19
C19
B20
E17
D18
C20
B21
H17
J17
G18
E20
G19
A22
F18
E19
H19
A21
J19
J18
G15
C16
F16
C17
F15
D16
E16
C18
A17
B16
A18
D15
C15
C21
F20
D22
G22
D21
F21
E22
G21
B23
A24
B26
B28
B24
A25
B25
B27
CN4500
PEG_RX6_DN
PEG_RX5_DN
PEG_RX4_DN
68>
PEG_TX0_C_DN
PEG_TX1_C_DN
68>
PEG_TX2_C_DN
68>
68>
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
PEG_TX2_DN
PEG_TX3_DN
68<
PEG_TX4_DN
0.1UF_6.3V_1
0.1UF_6.3V_1
PEG_TX7_DN
PEG_TX8_DN
PEG_TX9_DN
PEG_TX6_DN
PEG_TX5_DN
PEG_TX0_DN
0.1UF_6.3V_1
PEG_TX10_C_DP
PEG_TX9_C_DP
21<
21<
21<
21<
PEG_TX10_C_DN
PEG_TX9_C_DN
PEG_TX1_C_DN
PEG_TX0_C_DN
PEG_TX15_C_DP
PEG_TX14_C_DP
PEG_TX13_C_DP
PEG_TX12_C_DP
PEG_TX11_C_DP
PEG_TX10_C_DP
PEG_TX9_C_DP
PEG_TX4_C_DP
PEG_TX5_C_DP
PEG_TX6_C_DP
PEG_TX7_C_DP
PEG_TX8_C_DP
PEG_TX2_C_DN
PEG_TX4_C_DN
PEG_TX6_C_DN
PEG_TX7_C_DN
PEG_TX11_C_DN
PEG_TX12_C_DN
PEG_TX13_C_DN
PEG_RX4_DP
PEG_RX5_DP
PEG_RX6_DP
PEG_RX7_DP
PEG_RX12_DP
PEG_RX13_DP
PEG_RX14_DP
PEG_RX15_DP
PEG_RX0_DN
PEG_RX1_DN
+V1.05S_VCCP_PEG_ICOMPI
FDI_TX_DN<5>
FDI_TX_DP<7..0>
FDI_TX_DN<7..0>
DMI_RX_DP<3..0>
DMI_RX_DN<3..0>
2
DMI_TX_DP<3..0>
3
0
1
DMI_TX_DP<2>
DMI_TX_DP<3>
DMI_TX_DP<0>
DMI_TX_DP<1>
DMI_TX_DN<3..0>
DMI_TX_DN<2>
DMI_TX_DN<3>
DMI_TX_DN<0>
PEG_RX9_DN
DMI_RX_DN<2>
DMI_RX_DN<0>
EDP_TX0_DN
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
PEG_TX0_C_DP
PEG_TX1_C_DP
PEG_TX2_C_DP
PEG_TX4_C_DP
PEG_TX7_C_DP
PEG_TX11_C_DP
PEG_TX14_C_DP
PEG_TX15_C_DP
PEG_RX0_DP
24.9_1%_2
P1V05_VCCPS
PEG_RX15_DN
21<
21<
PEG_TX1_C_DP
PEG_TX0_C_DP
PEG_TX2_C_DP
PEG_TX3_C_DP
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
PEG_TX3_C_DN
PEG_TX8_C_DN
PEG_TX14_C_DN
PEG_TX15_C_DN
PEG_TX5_C_DN
21<
21<
21<
21<
21<
21<
21<
21<
21<
21<
68>
PEG_RX1_DP
PEG_RX2_DP
PEG_RX3_DP
PEG_RX9_DP
PEG_RX10_DP
PEG_RX11_DP
PEG_RX8_DP
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
68>
PEG_RX7_DN
PEG_RX8_DN
PEG_RX2_DN
PEG_RX3_DN
PEG_RX10_DN
PEG_RX12_DN
PEG_RX13_DN
PEG_RX11_DN
PEG_RX14_DN
68>
68>
68>
68>
68>
68>
68>
68>
68>
PEG_TX6_C_DP
PEG_TX8_C_DP
PEG_TX13_C_DP
PEG_TX14_C_DN
FDI_TX_DN<6>
FDI_TX_DN<4>
FDI_TX_DN<3>
FDI_TX_DN<2>
FDI_TX_DN<1>
FDI_TX_DN<0>
DMI_RX_DP<2>
DMI_RX_DP<1>
DMI_RX_DN<3>
DMI_TX_DN<1>
EDP_TX0_DP
48>
EDP_AUX_DN
EDP_AUX_DP
48>
48<>
48<>
EDP_HPD#
P1V05_VCCPS
48>
24.9_1%_2
+V1.05S_VCCP_eDP_COMPIO
CS_1310AXXXXXX-MTR
A01
C
CS
FDI_LSYNC1
FDI_LSYNC0
FDI_INT
FDI_FSYNC1
FDI_FSYNC0
FDI_TX_DP<7>
FDI_TX_DP<6>
FDI_TX_DP<5>
FDI_TX_DP<4>
FDI_TX_DP<3>
FDI_TX_DP<2>
FDI_TX_DP<1>
FDI_TX_DP<0>
FDI_TX_DN<7>
DMI_RX_DP<3>
DMI_RX_DP<0>
DMI_RX_DN<1>
3
2
PEG_TX3_C_DP
PEG_TX5_C_DP
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
PEG_TX9_C_DN
PEG_TX10_C_DN
PEG_TX11_C_DN
PEG_TX12_C_DP
PEG_TX0_DP
PEG_TX2_DP
PEG_TX1_DP
PEG_TX3_DP
PEG_TX4_DP
PEG_TX6_DP
PEG_TX5_DP
PEG_TX7_DP
PEG_TX8_DP
PEG_TX10_DP
PEG_TX9_DP
PEG_TX11_DP
PEG_TX12_DP
PEG_TX3_C_DN
PEG_TX4_C_DN
PEG_TX5_C_DN
PEG_TX6_C_DN
PEG_TX7_C_DN
PEG_TX8_C_DN
PEG_TX13_DP
PEG_TX14_DP
PEG_TX15_DP
PEG_TX1_DN
PEG_TX12_C_DN
PEG_TX13_C_DN
PEG_TX15_C_DN
PEG_TX10_DN
PEG_TX11_DN
PEG_TX12_DN
PEG_TX13_DN
PEG_TX14_DN
PEG_TX15_DN
30>
7
6
5
4
3
2
1
0
7
6
5
4
1
0
3
2
1
0
3
2
1
0
30>
30>
30>
30>
3
2
1
0
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
68<
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
0.1UF_6.3V_1
68<
68<
68<
68<
68<
68<
68<
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
OUT
IN
IN
OUT
OUT
BI
BI
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
OUT
IN
IN
eDP
Intel(R) FDI
DMI
PCI EXPRESS* - GRAPHICS
eDP_ICOMPO
eDP_HDP#
eDP_COMPIO
eDP_TX#[3]
eDP_TX#[2]
eDP_TX#[1]
eDP_TX#[0]
eDP_TX[3]
eDP_TX[2]
eDP_TX[1]
eDP_TX[0]
eDP_AUX#
eDP_AUX
PEG_TX[15]
PEG_TX[14]
PEG_TX[13]
PEG_TX[12]
PEG_TX[11]
PEG_TX[10]
PEG_TX[9]
PEG_TX[8]
PEG_TX[7]
PEG_TX[6]
PEG_TX[5]
PEG_TX[4]
PEG_TX[3]
PEG_TX[2]
PEG_TX[1]
PEG_TX[0]
PEG_TX#[15]
PEG_TX#[14]
PEG_TX#[13]
PEG_TX#[12]
PEG_TX#[11]
PEG_TX#[10]
PEG_TX#[9]
PEG_TX#[8]
PEG_TX#[7]
PEG_TX#[6]
PEG_TX#[5]
PEG_TX#[4]
PEG_TX#[3]
PEG_TX#[2]
PEG_TX#[1]
PEG_TX#[0]
PEG_RX[15]
PEG_RX[14]
PEG_RX[13]
PEG_RX[12]
PEG_RX[11]
PEG_RX[10]
PEG_RX[9]
PEG_RX[8]
PEG_RX[7]
PEG_RX[6]
PEG_RX[5]
PEG_RX[4]
PEG_RX[3]
PEG_RX[2]
PEG_RX[1]
PEG_RX[0]
PEG_RX#[15]
PEG_RX#[14]
PEG_RX#[13]
PEG_RX#[12]
PEG_RX#[11]
PEG_RX#[10]
PEG_RX#[9]
PEG_RX#[8]
PEG_RX#[7]
PEG_RX#[6]
PEG_RX#[5]
PEG_RX#[4]
PEG_RX#[3]
PEG_RX#[2]
PEG_RX#[1]
PEG_RX#[0]
PEG_RCOMPO
PEG_ICOMPO
PEG_ICOMPI
FDI1_LSYNC
FDI0_LSYNC
FDI_INT
FDI1_FSYNC
FDI0_FSYNC
FDI1_TX[3]
FDI1_TX[2]
FDI1_TX[1]
FDI1_TX[0]
FDI0_TX[3]
FDI0_TX[2]
FDI0_TX[1]
FDI0_TX[0]
FDI1_TX#[3]
FDI1_TX#[2]
FDI1_TX#[1]
FDI1_TX#[0]
FDI0_TX#[3]
FDI0_TX#[2]
FDI0_TX#[1]
FDI0_TX#[0]
DMI_TX[2]
DMI_TX[3]
DMI_TX[1]
DMI_TX[0]
DMI_TX#[3]
DMI_TX#[2]
DMI_TX#[1]
DMI_TX#[0]
DMI_RX[3]
DMI_RX[2]
DMI_RX[1]
DMI_RX[0]
DMI_RX#[3]
DMI_RX#[2]
DMI_RX#[1]
DMI_RX#[0]
CPU 3 DRAM
Fri Dec 31 10:16:57 2010
97
22
Frank Hu
EVEREST-M
AB9
AB8
AD4
AE4
R4
R5
AB10
T1
R1
AB7
R3
T5
R2
T3
T4
T2
T6
R7
T7
AA8
AP15
AK12
AP9
AN5
N3
K6
F3
D7
AP14
AK11
AP8
AN6
M3
J6
G3
C7
AT15
AR15
AN15
AT12
AT14
AR14
AN14
AT11
AH12
AJ12
AR8
AH11
AT9
AT8
AJ11
AR9
AR5
AR6
AN8
AP6
AT6
AT5
AN9
AP5
AP2
AN1
AN2
AN3
AP3
AR3
AM6
AM5
M1
M2
N5
M4
N1
N2
N4
M5
K7
K8
J10
J9
K9
K10
J8
J7
G2
F2
F5
G5
G1
F1
F4
G4
D8
D9
A8
A9
C8
D10
A7
C9
AE3
AD3
AD1
AD2
AE1
AE2
R10
R9
AA10
R6
AA7
AA9
AE5
AD5
AE6
AD6
T10
AB1
AA1
T9
AA2
AB2
CN4500
AF9
AD9
AG3
AH3
V7
V5
AF8
W4
V4
AD8
W5
V1
W6
W3
V2
V3
W7
W2
W1
AD10
AM15
AR12
AM8
AL6
M6
J3
G6
C4
AM14
AR11
AM9
AL5
N6
K3
F6
D4
AH15
AJ15
AK14
AL14
AK15
AL15
AH14
AJ14
AN12
AP12
AL11
AM11
AM12
AL12
AN11
AP11
AL8
AL9
AH9
AH8
AK9
AJ9
AK8
AJ8
AJ6
AJ5
AH6
AH5
AK5
AK6
AG5
AG6
M7
N9
M9
M10
N7
N8
N10
M8
K2
J2
J4
J5
J1
K1
K5
K4
G7
G8
F7
F9
G9
G10
F8
F10
C3
C2
C6
D6
D2
D3
D5
C5
AL3
AK3
AB5
AA6
AA5
AB6
V10
V9
AE8
V6
AF10
AE10
AH2
AG2
AH1
AG1
W10
AA3
AB3
W9
AA4
AB4
CN4500
M_A_DQ<10>
M_A_DQ<9>
M_A_DQ<8>
M_A_DQ<7>
M_A_DQ<6>
M_A_DQ<5>
M_CLK_DDR1_DN
M_CKE1
M_B_DQ<36>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<20>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<63>
63
62
1
M_A_A<2>
M_A_A<3>
M_A_DQ<11>
M_A_DQ<0>
22
M_B_DQ<30>
M_B_DQ<32>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<39>
M_B_DQ<41>
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
M_B_DQS_DN<6>
M_B_DQS_DN<3>
M_B_DQS_DN<2>
M_B_DQS_DN<0>
M_B_DQS_DN<1>
M_B_DQS_DP<0>
M_B_A<4>
M_B_A<5>
6
27<
M_CS#0
M_CS#1
M_A_DQS_DN<7..0>
40
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<47>
47
M_A_DQS_DP<7..0>
M_B_DQ<46>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<0>
M_B_DQ<62>
M_B_DQ<61>
M_B_DQ<60>
M_B_DQ<59>
M_B_DQ<58>
M_B_DQ<57>
M_B_DQ<56>
M_B_DQ<55>
M_B_DQ<54>
M_B_DQ<53>
M_B_DQ<52>
M_B_DQ<51>
M_B_DQ<50>
M_B_DQ<45>
M_B_DQ<40>
M_B_DQ<33>
M_B_DQ<31>
M_B_DQ<29>
M_B_DQ<28>
M_B_DQ<27>
M_B_DQ<26>
M_B_DQ<25>
M_B_DQ<24>
M_B_DQ<23>
M_B_DQ<22>
M_B_DQ<21>
M_B_DQ<19>
M_B_DQ<18>
M_B_DQ<17>
M_B_DQ<16>
M_B_DQ<15>
M_B_DQ<14>
M_B_DQ<13>
M_B_DQ<12>
M_B_DQ<11>
M_B_DQ<10>
M_B_DQ<9>
M_B_DQ<8>
M_B_DQ<7>
M_B_DQ<3>
M_B_DQ<2>
M_B_DQ<1>
M_B_WE#
M_B_RAS#
M_B_CAS#
M_B_BS2
M_B_BS1
M_B_BS0
M_CS#3
M_CS#2
M_B_A<15>
M_B_A<14>
M_B_A<13>
M_B_A<12>
M_B_A<11>
M_B_A<10>
M_B_A<9>
M_B_A<8>
M_B_A<7>
M_B_A<6>
M_B_A<3>
M_B_A<2>
M_B_A<1>
M_B_A<0>
M_B_DQS_DP<3>
M_B_DQS_DP<2>
M_B_DQS_DP<1>
M_B_DQS_DN<7>
M_B_DQS_DP<7>
M_B_DQS_DP<6>
M_B_DQS_DN<5>
M_B_DQS_DP<5>
M_B_DQS_DN<4>
M_B_DQS_DP<4>
M_ODT3
M_ODT2
M_CKE3
M_CKE2
M_CLK_DDR3_DN
M_CLK_DDR2_DN
M_CLK_DDR3_DP
M_CLK_DDR2_DP
3
9
0
1
2
4
5
6
7
8
27<>
10
11
12
13
14
16
15
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
48
49
50
51
52
53
54
55
56
57
58
59
60
61
27<
27<
27<
27<
27<
M_B_DQ<63..0>
26<>
26<
M_CLK_DDR1_DP
M_ODT1
63
M_A_BS0
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<12>
12
14
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR
M_A_DQ<63>
M_A_DQ<62>
M_A_DQ<61>
M_A_DQ<60>
M_A_DQ<59>
M_A_DQ<58>
M_A_DQ<57>
M_A_DQ<56>
M_A_DQ<55>
M_A_DQ<54>
M_A_DQ<53>
M_A_DQ<52>
M_A_DQ<51>
M_A_DQ<50>
M_A_DQ<49>
M_A_DQ<48>
M_A_DQ<47>
M_A_DQ<46>
M_A_DQ<45>
M_A_DQ<44>
M_A_DQ<43>
M_A_DQ<42>
M_A_DQ<41>
M_A_DQ<40>
M_A_DQ<39>
M_A_DQ<38>
M_A_DQ<37>
M_A_DQ<36>
M_A_DQ<35>
M_A_DQ<34>
M_A_DQ<33>
M_A_DQ<32>
M_A_DQ<31>
M_A_DQ<30>
M_A_DQ<29>
M_A_DQ<28>
M_A_DQ<27>
M_A_DQ<26>
M_A_DQ<25>
M_A_DQ<24>
M_A_DQ<23>
M_A_DQ<20>
M_A_DQ<19>
M_A_DQ<14>
M_A_DQ<13>
M_A_DQ<4>
M_A_DQ<3>
M_A_DQ<2>
M_A_DQ<1>
M_A_WE#
M_A_RAS#
M_A_CAS#
M_A_BS2
M_A_BS1
M_A_A<15>
M_A_A<14>
M_A_A<13>
M_A_A<12>
M_A_A<11>
M_A_A<10>
M_A_A<9>
M_A_A<8>
M_A_A<7>
M_A_A<6>
M_A_A<5>
M_A_A<4>
M_A_A<1>
M_A_A<0>
M_A_DQS_DN<7>
M_A_DQS_DP<7>
M_A_DQS_DN<6>
M_A_DQS_DP<6>
M_A_DQS_DN<5>
M_A_DQS_DP<5>
M_A_DQS_DN<4>
M_A_DQS_DP<4>
M_A_DQS_DN<3>
M_A_DQS_DP<3>
M_A_DQS_DN<2>
M_A_DQS_DP<2>
M_A_DQS_DN<1>
M_A_DQS_DP<1>
M_A_DQS_DN<0>
M_A_DQS_DP<0>
M_ODT0
M_CKE0
M_CLK_DDR0_DN
M_CLK_DDR0_DP
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
A01
M_A_A<15..0>
M_A_DQ<63..0>
M_B_A<15..0>
M_B_DQS_DP<7..0>
M_B_DQS_DN<7..0>
26<
26<
26<
62
26<
26<
26<
60
61
58
59
57
55
56
53
54
52
50
51
49
48
47
45
46
44
43
42
14
15
12
13
11
10
9
7
8
6
5
4
2
3
0
6
7
4
5
3
1
2
0
7
6
5
40
41
39
37
38
35
36
34
32
33
31
30
29
27
28
26
25
24
22
23
21
19
20
17
18
16
15
13
11
9
10
8
7
6
4
5
3
2
1
0
4
3
2
0
1
26<
26<
26<
26<
26<
26<
26<
26<
26<
14
15
12
13
11
10
9
7
8
5
4
2
3
1
0
6
7
4
5
3
27<>
1
2
0
7
6
5
4
3
2
0
1
27<
27<
27<
27<
27<
27<
27<
27<
27<
27<
CS_1310AXXXXXX-MTR
CS
C
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
DDR SYSTEM MEMORY B
SB_DQ[0]
SB_DQ[63]
RSVD_TP[20]
RSVD_TP[19]
RSVD_TP[18]
RSVD_TP[17]
SB_CS#[1]
SB_CS#[0]
RSVD_TP[16]
RSVD_TP[15]
RSVD_TP[14]
RSVD_TP[13]
RSVD_TP[12]
RSVD_TP[11]
SB_DQ[62]
SB_DQ[61]
SB_DQ[60]
SB_DQ[59]
SB_DQ[58]
SB_DQ[57]
SB_DQ[56]
SB_DQ[55]
SB_DQ[54]
SB_DQ[53]
SB_DQ[52]
SB_DQ[51]
SB_DQ[50]
SB_DQ[49]
SB_DQ[48]
SB_DQ[47]
SB_DQ[46]
SB_DQ[45]
SB_DQ[44]
SB_DQ[43]
SB_DQ[42]
SB_DQ[41]
SB_DQ[40]
SB_DQ[39]
SB_DQ[38]
SB_DQ[37]
SB_DQ[36]
SB_DQ[35]
SB_DQ[34]
SB_DQ[33]
SB_DQ[32]
SB_DQ[31]
SB_DQ[30]
SB_DQ[29]
SB_DQ[28]
SB_DQ[27]
SB_DQ[26]
SB_DQ[25]
SB_DQ[24]
SB_DQ[23]
SB_DQ[22]
SB_DQ[21]
SB_DQ[20]
SB_DQ[19]
SB_DQ[18]
SB_DQ[17]
SB_DQ[16]
SB_DQ[15]
SB_DQ[14]
SB_DQ[13]
SB_DQ[12]
SB_DQ[11]
SB_DQ[10]
SB_DQ[9]
SB_DQ[8]
SB_DQ[7]
SB_DQ[6]
SB_DQ[5]
SB_DQ[4]
SB_DQ[3]
SB_DQ[2]
SB_DQ[1]
SB_MA[15]
SB_MA[14]
SB_MA[13]
SB_MA[12]
SB_MA[11]
SB_MA[10]
SB_MA[9]
SB_MA[8]
SB_MA[7]
SB_MA[6]
SB_MA[5]
SB_MA[4]
SB_MA[3]
SB_MA[2]
SB_MA[1]
SB_MA[0]
SB_DQS#[3]
SB_DQS[3]
SB_DQS#[2]
SB_DQS[2]
SB_DQS#[1]
SB_DQS[1]
SB_DQS#[0]
SB_DQS[0]
SB_DQS#[7]
SB_DQS[7]
SB_DQS#[6]
SB_DQS[6]
SB_DQS#[5]
SB_DQS[5]
SB_DQS#[4]
SB_DQS[4]
SB_ODT[1]
SB_ODT[0]
SB_CKE[1]
SB_CKE[0]
SB_CLK#[1]
SB_CLK#[0]
SB_CLK[1]
SB_CLK[0]
SB_WE#
SB_RAS#
SB_CAS#
SB_BS[2]
SB_BS[1]
SB_BS[0]
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
DDR SYSTEM MEMORY A
RSVD_TP[10]
RSVD_TP[9]
RSVD_TP[8]
RSVD_TP[7]
RSVD_TP[6]
RSVD_TP[3]
RSVD_TP[5]
RSVD_TP[4]
RSVD_TP[2]
RSVD_TP[1]
SA_DQ[63]
SA_DQ[62]
SA_DQ[61]
SA_DQ[60]
SA_DQ[59]
SA_DQ[58]
SA_DQ[57]
SA_DQ[56]
SA_DQ[55]
SA_DQ[54]
SA_DQ[53]
SA_DQ[52]
SA_DQ[51]
SA_DQ[50]
SA_DQ[49]
SA_DQ[48]
SA_DQ[47]
SA_DQ[46]
SA_DQ[45]
SA_DQ[44]
SA_DQ[43]
SA_DQ[42]
SA_DQ[41]
SA_DQ[40]
SA_DQ[39]
SA_DQ[38]
SA_DQ[37]
SA_DQ[36]
SA_DQ[35]
SA_DQ[34]
SA_DQ[33]
SA_DQ[32]
SA_DQ[31]
SA_DQ[30]
SA_DQ[29]
SA_DQ[28]
SA_DQ[27]
SA_DQ[26]
SA_DQ[25]
SA_DQ[24]
SA_DQ[23]
SA_DQ[22]
SA_DQ[21]
SA_DQ[20]
SA_DQ[19]
SA_DQ[18]
SA_DQ[17]
SA_DQ[16]
SA_DQ[15]
SA_DQ[14]
SA_DQ[13]
SA_DQ[12]
SA_DQ[11]
SA_DQ[10]
SA_DQ[9]
SA_DQ[8]
SA_DQ[7]
SA_DQ[6]
SA_DQ[5]
SA_DQ[4]
SA_DQ[3]
SA_DQ[2]
SA_DQ[1]
SA_DQ[0]
SA_MA[15]
SA_MA[14]
SA_MA[13]
SA_MA[12]
SA_MA[11]
SA_MA[10]
SA_MA[9]
SA_MA[8]
SA_MA[7]
SA_MA[6]
SA_MA[5]
SA_MA[4]
SA_MA[3]
SA_MA[2]
SA_MA[1]
SA_MA[0]
SA_DQS#[7]
SA_DQS[7]
SA_DQS#[6]
SA_DQS[6]
SA_DQS#[5]
SA_DQS[5]
SA_DQS#[4]
SA_DQS[4]
SA_DQS#[3]
SA_DQS[3]
SA_DQS#[2]
SA_DQS[2]
SA_DQS#[1]
SA_DQS[1]
SA_DQS#[0]
SA_DQS[0]
SA_ODT[1]
SA_ODT[0]
SA_CS#[1]
SA_CS#[0]
SA_CKE[1]
SA_CKE[0]
SA_CLK#[1]
SA_CLK#[0]
SA_CLK[1]
SA_CLK[0]
SA_WE#
SA_RAS#
SA_CAS#
SA_BS[2]
SA_BS[1]
SA_BS[0]
20mil
CPU 4 POWER
CLOSE TO POWER IC
WS
EVEREST-M
Frank Hu
23
97
Fri Dec 31 10:16:58 2010
2
1
R4501
2
1
R4502
2
1
C4563
2
1
C4560
2
1
C4562
2
1
C4561
2
1
C4566
2
1
C4564
2
1
C4565
2
1
R4503
2
1
R4504
2
1
R4526
2
1
R4527
2
1
R4546
2
1
R4547
2
1
R4548
2
1
R4525
2
1
R4550
2
1
R4549
2
1
R4551
2
1
R4528
3
2
1
C4569
2
1
C4599
2
1
C4596
2
1
C4598
2
1
C4597
2
1
C4557
2
1
C4503
2
1
C4558
2
1
C4576
2
1
C4575
2
1
C4574
2
1
C4573
2
1
C4572
2
1
C4571
2
1
C4588
2
1
C4589
2
1
C4590
2
1
C4591
2
1
C4592
2
1
C4593
2
1
C4577
2
1
C4578
2
1
C4581
2
1
C4582
2
1
C4583
2
1
C4584
2
1
C4585
2
1
C4586
2
1
C4587
2
1
C4594
2
1
C4580
2
1
C4579
A10
AJ34
AJ28
AJ30
AJ29
B10
J14
L10
P10
U10
Y10
J23
AC10
A11
A12
A13
A14
B12
B14
C11
C12
C13
C14
AG10
D11
D12
D13
D14
E11
E12
E14
F11
F12
F13
AH10
F14
G12
G13
G14
H11
H12
H14
J11
J12
J13
AH13
AJ35
P27
P28
P29
P30
P31
P32
P33
P34
P35
R26
AG27
R27
R28
R29
R30
R31
R32
R33
R34
R35
U26
AG28
U27
U28
U29
U30
U31
U32
U33
U34
U35
V26
AG29
V27
V28
V29
V30
V31
V32
V33
V34
V35
Y26
AG30
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
AA26
AG31
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AC26
AG32
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AD26
AG33
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AF26
AG34
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
P26
AG26
AG35
CN4500
+V1.05S_VCCP_VCCIO40
54.9_1%_2
43_1%_2
PVCORE
0_5%_2
P1V05_VCCPS
10_1%_2
VCC_SENSE_VTT
10_1%_2
VSS_SENSE_VTT
100_1%_2
VSSSENSE
VCCSENSE
75_1%_2
0_5%_2
22uF_6.3V_5 22uF_6.3V_5
10uF_6.3V_3 10uF_6.3V_3
22uF_6.3V_5
22uF_6.3V_5
H_CPU_SVIDALRT#
P1V05_VCCPS
PVCORE
22uF_6.3V_5
470UF_2V
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
VCCSENSE_R
VSSSENSE_R
0_5%_2
100_1%_2
14<
14<
H_CPU_SVIDCLK
VR_SVID_DATA
VR_SVID_CLK
VR_SVID_ALRT#
H_CPU_SVIDDAT
130_1%_2
0_5%_2
0_5%_2
P1V05_VCCPS
130_1%_2
14<>
14<
P1V05_VCCPS
22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5
10uF_6.3V_310uF_6.3V_3
10uF_6.3V_3
22uF_6.3V_5
A01
22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5
22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5 22uF_6.3V_5
10uF_6.3V_3
10uF_6.3V_3 10uF_6.3V_3
10uF_6.3V_3 10uF_6.3V_3
C
CS_1310AXXXXXX-MTR
CS
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
+
SVID
SENSE LINES
PEG AND DDR
CORE SUPPLY
POWER
VCCIO40
VCCIO_SENSE
VCCIO31
VCCIO30
VCCIO29
VCCIO28
VCCIO27
VCCIO26
VCCIO39
VCCIO38
VCCIO37
VCCIO36
VCCIO35
VCCIO34
VCCIO33
VCCIO32
VCCIO25
VCCIO17
VCCIO16
VCCIO15
VCCIO14
VCCIO13
VCCIO11
VCCIO10
VCCIO9
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO24
VCCIO23
VCCIO22
VCCIO21
VCCIO20
VCCIO19
VCCIO18
VCCIO12
VCCIO1
VCC100
VCC99
VCC98
VCC97
VCC96
VCC95
VCC94
VCC93
VCC92
VCC91
VCC90
VCC89
VCC88
VCC87
VCC86
VCC85
VCC84
VCC83
VCC82
VCC81
VCC80
VCC79
VCC78
VCC77
VCC76
VCC75
VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
VCC56
VCC55
VCC54
VCC53
VCC52
VCC51
VCC50
VCC49
VCC48
VCC47
VCC46
VCC45
VCC44
VCC43
VCC42
VCC41
VCC40
VCC39
VCC38
VCC37
VCC36
VCC35
VCC34
VCC33
VCC32
VCC31
VCC30
VCC29
VCC28
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VSS_SENSE_VCCIO
VIDSOUT
VIDSCLK
VIDALERT#
VSS_SENSE
VCC_SENSE
WS
SNB HIGH
IVB HIGH
WS
WS
20/20 mil
6A
IVB LOW
0.675V
20/20 mil
CPU 5 POWER
1.1A
20/20 mil
0.90V
[[ CPU PIN# C22
xxVccSA_Select[0]
VID1 of VR ]]
0
0
1
VID0 of VR ]]
[[ CPU PIN# C24
xxVccSA_Select[1]
1
1
0
0
SNB LOW
Function
0.725V
VCCSA VR Vout
1
0.80V
WS
WS
24
97
EVEREST-M
Frank Hu
Mon Jan 03 17:28:06 2011
10uF_6.3V_3
VCCSA_SENSE
2
1
R4559
2
1
C4605
2
1
C4604
2
1
C4603
2
1
C4602
2
1
C4601
2
1
C4600
2
1
C4568
2
1
C4567
4
36
5
2
1
Q4501
2
1
R4523
2
1
C4595
2
1
R4524
2
1
R4543
2
1
C4502
2
1
C4501
2
1
C4500
2
1
C4553
2
1
C4552
2
1
C4551
2
1
C4555
2
1
C4556
2
1
C4554
2
1
L4500
2
1
C4547
2
1
C4549
2
1
C4548
2
1
C4550
32
1
C4505
32
1
C4506
2
1
C4507
2
1
C4508
2
1
C4510
2
1
C4509
2
1
C4511
2
1
C4512
2
1
C4513
2
1
C4514
AK34
Y1
Y4
Y7
AC1
AC4
AC7
AF1
AF4
P1
P4
P7
U1
U4
U7
AF7
C24
C22
H23
H25
H26
J24
J25
J26
L26
M26
M27
A2
A6
B6
A19
AK35
AR21
AR23
AR24
AT17
AH17
AH18
AH20
AH21
AH23
AT18
AH24
AJ17
AJ18
AJ20
AJ21
AJ23
AJ24
AK17
AK18
AK20
AT20
AK21
AK23
AK24
AL17
AL18
AL20
AL21
AL23
AL24
AM17
AT21
AM18
AM20
AM21
AM23
AM24
AN17
AN18
AN20
AN21
AN23
AT23
AN24
AP17
AP18
AP20
AP21
AP23
AP24
AR17
AR18
AR20
AT24
AL1
D1
B4
CN4500
22uF_6.3V_5
10uF_6.3V_3
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
0_5%_2_DY
VCCSA_SEL
CPU_CHB_VREFDQ
CPU_CHA_VREFDQ
470UF_2V
22uF_6.3V_5_DY
22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5
22uF_6.3V_5_DY
14<
14<
VSSAXG_SENSE
0_5%_2
10uF_6.3V_3
10uF_6.3V_3
13<
22uF_6.3V_5
P0V75_VREF_M
22uF_6.3V_522uF_6.3V_5 22uF_6.3V_522uF_6.3V_5
22uF_6.3V_5
P0V75_VREF_M_H
470pF_50V_2
AO6402AL
PVAXG
C
A01
CS
CS_1310AXXXXXX-MTR
SLP_S3#_15R
VAXG_SENSE
10uF_6.3V_3
220UF_2.5V
220UF_2.5V
10uF_6.3V_3
1uF_6.3V_2 1uF_6.3V_2
22uF_6.3V_5
10K_5%_2
P0V85_S
10uF_6.3V_3 10uF_6.3V_3
P1V5_CPUDDRS
100K_5%_2
P0V75_VREF_M_H
10uF_6.3V_3
10uF_6.3V_3
22uF_6.3V_5
470UF_2V
P1V8_S
FBM_11_160808_181A15T
22uF_6.3V_5
VCCPLL
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
+
+
D
G
S
NMOS_4D1S
IN
OUT
OUT
OUT
OUT
+
+
MISC VREFSA RAIL
1.8V RAIL
LINES
SENSE
DDR3 -1.5V RAILS
GRAPHICS
POWER
VCCIO_SEL
SB_DIMM_VREFDQ
SA_DIMM_VREFDQ
VCCSA_VID[0]
VCCPLL3
VCCSA_VID[1]
VCCSA_SENSE
VCCSA8
VCCSA7
VCCSA6
VCCSA5
VCCSA4
VCCSA3
VCCSA2
VCCSA1
VCCPLL2
VCCPLL1
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VDDQ15
VDDQ14
VDDQ13
VDDQ12
VDDQ11
VAXG54
VAXG53
VAXG52
VAXG51
VAXG50
VAXG49
VAXG48
VAXG47
VAXG46
VAXG45
VAXG44
VAXG43
VAXG42
VAXG41
VAXG40
VAXG39
VAXG38
VAXG37
VAXG36
VAXG35
VAXG34
VAXG33
VAXG32
VAXG31
VAXG30
VAXG29
VAXG28
VAXG27
VAXG26
VAXG25
VAXG24
VAXG23
VAXG22
VAXG21
VAXG20
VAXG19
VAXG18
VAXG17
VAXG16
VAXG15
VAXG14
VAXG13
VAXG12
VAXG11
VAXG10
VAXG9
VAXG8
VAXG7
VAXG6
VAXG5
VAXG4
VAXG3
VAXG2
VAXG1
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
PEG Defer Training
PCIE Port Bifurcation
LOW eDP ENABLE
STRAP PIN
CPU 6 GND
PEG Static Lan Reversal
0: eDP Enabled
LOW eDP ENABLE
PEG Defer Training
CFG(4)
PCIE Port Bifurcation Straps
00: x8, x4, x4 - Device 1 function 1 and 2 enabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled
11: (Default) x16 - Device 1 function 1 and 2 disabled
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG(7)
CFG(2)
1: (Default) Normal operation
PEG Static Lane Reversal
0: Lane Reversed
1: (Default) eDP Disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
EVEREST-M
Frank Hu
97
25
Fri Dec 31 10:16:59 2010
2
1
R4518
2
1
R4519
2
1
R4520
2
1
R4521
2
1
R4522
AH31
AH33
AH26
AJ33
AH27
AJ31
B35
A34
A33
B34
AR34
AP35
AT33
AT34
AR1
AT1
AT2
C35
AR35
F24
F25
AM35
AK32
AJ32
AJ26
G16
H16
J16
T8
AJ27
AM33
AT26
W8
AK2
AE7
AG7
L7
J15
B18
J20
C29
A30
B31
D30
B29
B30
A31
C30
D23
E23
G24
G25
D24
F23
B1
AM30
AM32
AM31
AL30
AL29
AK26
AL27
AL26
AN29
AK31
AM27
AN26
AN31
AN28
AM26
AM28
AK29
AK28
AN35
CN4500
A3
A20
A23
A26
A29
A32
A35
B2
B3
B5
B7
B8
B9
B11
B13
B15
B17
B19
B22
C1
C10
C23
C25
C27
C28
C31
C34
D17
D20
D26
D29
D32
D35
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E13
E15
E18
E21
E24
E27
E30
F19
F22
F29
F31
F34
G11
G17
G20
G23
G26
G29
G32
G35
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H13
H15
H18
H21
H24
H27
H30
H33
J31
J34
K26
K29
K32
K35
L1
L2
L3
L4
L5
L6
L8
L9
L27
L30
L33
M34
N26
N27
N28
N29
N30
N31
N32
N33
N34
N35
P2
P3
P5
P6
P8
P9
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
CN4500
AH22
AH25
AH28
AH29
AH30
AH32
AH34
AH35
AJ1
AT13
AJ2
AJ3
AJ4
AJ7
AJ10
AJ13
AJ16
AJ19
AJ22
AJ25
AT16
AK4
AK7
AK10
AK13
AK16
AK19
AK22
AK25
AK27
AK30
AT19
AK33
AL2
AL4
AL7
AL10
AL13
AL16
AL19
AL22
AL25
AT22
AL28
AL31
AL34
AM1
AM2
AM3
AM4
AM7
AM10
AM13
AT25
AM16
AM19
AM22
AM25
AM29
AN4
AN7
AN10
AN13
AN16
AT27
AN19
AN22
AN25
AN27
AN30
AP1
AP4
AP7
AP10
AP13
AT29
AP16
AP19
AP22
AP25
AP28
AP31
AP34
AR2
AR4
AR7
AT32
AR10
AR13
AR16
U2
AR19
U3
U5
U6
U8
U9
W26
W27
W28
W29
W30
AR22
W31
W32
W33
W34
W35
Y2
Y3
Y5
Y6
Y8
AR25
Y9
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AT3
AB35
AC2
AC3
AC5
AC6
AC8
AC9
AD7
AE9
AE26
AT4
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AF2
AT7
AF3
AF5
AF6
AG4
AG8
AG9
AH4
AH7
AH16
AH19
AT10
AT35
CN4500
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
CFG<16>
CFG<15>
CFG<13>
CFG<12>
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
CFG<5>
CFG<6>
25<
60<
60<
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
CFG<4>
CFG<5>
CFG<2>
CS_1310AXXXXXX-MTR
CS A01
C
CFG<17>
CFG<0>
CFG<14>
CFG<11>
CFG<10>
CFG<9>
CFG<8>
CFG<7>
CFG<4>
CFG<3>
CFG<2>
CFG<1>
CLK_XDP_CLKGEN_DN
CLK_XDP_CLKGEN_DP
25<
60<
60<
60<
60<
25<
60<
25<
60<
60<
60<
60<
60<
1K_1%_2_DY
1K_1%_2_DY
1K_1%_2
1K_1%_2
1K_1%_2_DY
25>60<
CFG<7>
CFG<6>
60<
25<
60<
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
RESERVED
VSS_DIE_SENSE
VCC_DIE_SENSE
BCLK_ITP#
BCLK_ITP
KEY
VSS_VAL_SENSE
VCC_VAL_SENSE
VSSAXG_VAL_SENSE
VAXG_VAL_SENSE
RSVD5
RSVD10
RSVD_NCTF4
RSVD25
RSVD33
RSVD32
RSVD14
RSVD13
RSVD12
RSVD11
RSVD9
RSVD8
RSVD37
RSVD24
RSVD23
RSVD21
RSVD22
RSVD19
RSVD20
RSVD18
RSVD17
RSVD15
RSVD16
RSVD27
RSVD29
RSVD28
RSVD31
RSVD30
RSVD52
RSVD51
RSVD_NCTF10
RSVD_NCTF9
RSVD_NCTF8
RSVD_NCTF7
RSVD_NCTF6
RSVD_NCTF13
RSVD_NCTF12
RSVD_NCTF11
RSVD_NCTF5
RSVD_NCTF3
RSVD_NCTF1
RSVD40
RSVD39
RSVD_NCTF2
RSVD38
RSVD35
RSVD34
CFG[17]
CFG[16]
CFG[15]
CFG[14]
CFG[13]
CFG[12]
CFG[11]
CFG[10]
CFG[9]
CFG[8]
CFG[7]
CFG[6]
CFG[5]
CFG[4]
CFG[3]
CFG[2]
CFG[1]
CFG[0]
VSS
VSS285
VSS284
VSS283
VSS282
VSS281
VSS280
VSS279
VSS278
VSS277
VSS276
VSS275
VSS274
VSS273
VSS272
VSS271
VSS270
VSS269
VSS268
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
DDR3 DIMM0
NOTE:
1.5A
NOTE:PLACE C4100
ON COMMON PATH
THESE CAPS NEAR
LAYOUT NOTE: PLACE
SO-DIMM0 POWER PIN
IF SA0_DIM0=1 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32
SO-DIMMA TS ADDRESS IS 0X30
SO-DIMMA SPD ADDRESS IS 0XA0
IF SA0_DIM0=0 , SA1_DIM0=0
FOR BOTH DIMM'S
VTT2
CHA
20/20 MIL
20/20 MIL
CLOSE TO VTT1 AND
PLACE THESE CAPS
WS
REMOVE 1UF CAP 1PCS
Fri Dec 31 10:17:00 2010
EVEREST-M
Frank Hu
97
26
2
1
R4127
2
1
R4126
2
1
R4101
2
1
R4100
2
1
R4125
2
1
R4102
2
1
C4110
2
1
C4100
2
1
C4109
2
1
C4128
2
1
C4120
2
1
C4121
2
1
C4119
2
1
C4126
2
1
C4127
2
1
C4122
2
1
C4125
2
1
C4124
2
1
C4123
2
1
C4137
2
1
C4136
2
1
C4135
2
1
C4140
2
1
C4139
2
1
C4138
204
203
25
20
19
14
196
195
190
13
189
185
184
179
178
173
172
168
167
162
9
161
156
155
151
150
145
144
139
138
134
8
133
128
127
72
71
66
65
61
60
55
3
54
49
48
44
43
38
37
32
31
26
2
1
126
199
99
94
93
88
87
82
81
76
124
123
118
117
112
111
106
105
100
75
30
125
122
77
G2
G1
198
CN4101
113
200
202
201
197
121
114
110
120
116
188
171
154
137
64
47
29
12
186
169
152
135
62
45
27
10
23
21
18
194
192
182
180
16
193
191
183
181
176
174
166
164
177
175
6
165
163
160
158
148
146
159
157
149
147
4
142
140
132
130
143
141
131
129
70
68
17
58
56
69
67
59
57
52
50
42
40
15
53
51
41
39
36
34
24
22
35
33
7
5
187
170
153
136
63
46
28
11
74
73
104
102
103
101
115
79
108
109
85
89
86
90
91
92
95
96
78
80
119
83
84
107
97
98
CN4101
M_A_DQS_DN<7..0>
M_A_DQS_DP<7..0>
M_A_DQ<38>
1UF_6.3V_2
BELLW_80001_6021_204P
M_A_DQ<2>
M_A_A<11>
M_A_A<4>
M_A_DQ<10>
P3V3_S
DIMM0_VREF_DQ
0.1UF_16V_2
1UF_6.3V_2
SA1_DIM0
P3V3_S
BELLW_80001_6021_204P
M_A_A<13>
M_A_A<12>
M_A_A<0>
0
M_A_A<6>
8
6
M_A_A<7>
M_A_DQ<24>
M_A_DQ<26>
32
M_A_DQ<31>
M_A_DQ<29>
M_A_DQ<25>
M_A_DQ<27>
M_A_DQ<8>
M_A_DQ<6>
M_A_DQ<19>
16
17
22<>
M_A_DQ<63..0>
P3V3_S
DIMM0_VREF_CA
DDR3_DRAMRST#
PM_EXTTS#1_R
M_A_DQ<4>
M_A_DQ<3>
M_A_A<15..0>
10K_5%_2 10K_5%_2
10K_5%_2_DY
26>
26>
10K_5%_2_DY
SA0_DIM0
10K_5%_2
0_5%_2
26>27>
PM_EXTTS#1
PM_EXTTS#1_R
1UF_6.3V_2
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_310UF_6.3V_3
10UF_6.3V_310UF_6.3V_3
1UF_6.3V_21UF_6.3V_21UF_6.3V_2
18>
26< 27>
P0V75_S
1UF_6.3V_21UF_6.3V_2
P1V5
CS
CS_1310AXXXXXX-MTR
A01
C
22>
0
1
2
4
3
5
6
7
8
9
10
11
12
14
15
13
20
18
19
22>
1
2
3
4
5
7
9
10
11
12
13
14
15
22>
22>
22>
21
22
23
24
25
26
27
28
30
29
33
31
35
34
38
36
37
40
39
43
41
42
44
45
46
47
48
49
50
51
52
53
55
54
56
57
58
60
59
61
63
62
22>
22>
22>
22>
22>
22>
22>
22>
22>
60< 27<
59<> 29<>
22>
22>
0
1
2
22<>
3
4
5
6
7
0
1
2
3
4
5
22<>
26<
26<
6
7
M_CS#1
M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<5>
M_A_DQ<7>
M_A_DQ<9>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<13>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<20>
M_A_DQ<18>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<5>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<14>
M_A_A<15>
M_A_BS2
M_A_BS1
M_A_BS0
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<28>
M_A_DQ<30>
M_A_DQ<33>
M_A_DQ<32>
M_A_DQ<35>
M_A_DQ<34>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<40>
M_A_DQ<43>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<55>
M_A_DQ<54>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<60>
M_A_DQ<59>
M_A_DQ<61>
M_A_DQ<63>
M_A_DQ<62>
M_CS#0
M_CLK_DDR1_DP
M_CLK_DDR0_DN
M_CLK_DDR0_DP
M_CLK_DDR1_DN
M_CKE0
M_A_WE#
M_A_RAS#
M_A_CAS#
M_CKE1
PCH_3S_SMCLK
PCH_3S_SMDATA
M_ODT0
M_ODT1
M_A_DQS_DP<0>
M_A_DQS_DP<1>
M_A_DQS_DP<2>
M_A_DQS_DP<3>
M_A_DQS_DP<4>
M_A_DQS_DP<5>
M_A_DQS_DP<6>
M_A_DQS_DP<7>
M_A_DQS_DN<0>
M_A_DQS_DN<1>
M_A_DQS_DN<2>
M_A_DQS_DN<3>
M_A_DQS_DN<4>
M_A_DQS_DN<5>
SA0_DIM0
SA1_DIM0
M_A_DQS_DN<6>
M_A_DQS_DN<7>
M_A_DQ<47>
27>
2.2UF_6.3V_2
0.1UF_16V_2
2.2UF_6.3V_2 0.1UF_16V_2
M_A_DQ<39>
22>
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
IN
BI
OUT
BI
G2
G1
VTT2
VTT1
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VREF_CA
VREF_DQ
RESET#
EVENT#
NCTEST
NC2
NC1
VDDSPD
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQS#7
DQS#6
DQS#5
DQS#4
DQS#3
DQS#2
DQS#1
DQS#0
DQS7
DQS6
DQS5
DQS4
DQS3
DQS2
DQS1
DQS0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
ODT1
ODT0
SDA
SCL
SA1
SA0
WE#
RAS#
CAS#
CKE1
CKE0
CK1#
CK1
CK0#
CK0
S1#
S0#
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10_AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
20/20 MIL
PLACE THESE CAPS
DDR3 DIMM1
SO-DIMM0 POWER PIN
PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2
1.5A
20/20 MIL
CHB
VTT2
CLOSE TO VTT1 AND
WS
NOTE:
LAYOUT NOTE: PLACE
THESE CAPS NEAR
SO-DIMMB TS ADDRESS IS 0X34
REMOVE CPU_CHB_VREFDQ
SO-DIMMB SPD ADDRESS IS 0XA4
20/20 MIL
WS
Fri Dec 31 10:16:30 2010
27
97
EVEREST-M
Frank Hu
2
1
R4139
2
1
R4138
2
1
R4137
2
1
R4136
2
1
R4144
2
1
R4143
2
1
R4142
2
1
R4141
2
1
C4142
2
1
R4140
2
1
C4141
2
1
R4135
2
1
R4134
2
1
R4133
2
1
R4132
2
1
R4131
2
1
R4130
2
1
R4129
2
1
R4128
4
36
5
2
1
Q4101
4
3 6
5
2
1
Q4100
2
1
R4122
2
1
R4117
2
1
R4118
2
1
C4118
2
1
R4110
2
1
R4111
2
1
R4121
2
1
C4103
2
1
R4112
2
1
R4105
204
203
25
20
19
14
196
195
190
13
189
185
184
179
178
173
172
168
167
162
9
161
156
155
151
150
145
144
139
138
134
8
133
128
127
72
71
66
65
61
60
55
3
54
49
48
44
43
38
37
32
31
26
2
1
126
199
99
94
93
88
87
82
81
76
124
123
118
117
112
111
106
105
100
75
30
125
122
77
G2
G1
198
CN4100
113
200
202
201
197
121
114
110
120
116
188
171
154
137
64
47
29
12
186
169
152
135
62
45
27
10
23
21
18
194
192
182
180
16
193
191
183
181
176
174
166
164
177
175
6
165
163
160
158
148
146
159
157
149
147
4
142
140
132
130
143
141
131
129
70
68
17
58
56
69
67
59
57
52
50
42
40
15
53
51
41
39
36
34
24
22
35
33
7
5
187
170
153
136
63
46
28
11
74
73
104
102
103
101
115
79
108
109
85
89
86
90
91
92
95
96
78
80
119
83
84
107
97
98
CN4100
2
1
R4119
2
1
R4120
2
1
R4115
2
1
R4116
2
1
R4114
2
1
R4123
2
1
R4124
2
1
R4103
2
1
R4104
2
1
C4101
2
1
C4102
2
1
C4107
2
1
C4132
2
1
C4133
2
1
C4134
2
1
C4129
2
1
C4130
2
1
C4131
2
1
C4108
2
1
C4106
2
1
C4105
2
1
C4113
2
1
C4114
2
1
C4115
2
1
C4117
2
1
C4112
2
1
C4116
2
1
C4104
SA0_DIM1
27>
P3V3_S
M_B_DQ<2>
M_B_DQ<1>
M_B_A<3>
M_B_DQ<17>
33
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<24>
M_B_DQ<27>
M_B_BS2
M_B_A<6>
DIMM0_VREF_CA
1UF_6.3V_2
17
M_B_DQ<16>
M_B_DQ<18>
M_B_DQ<19>
20
19
18
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
22
21
26
DIMM1_VREF_DQ
0.1UF_16V_22.2UF_6.3V_2
PM_EXTTS#1_R
DDR3_DRAMRST#
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
10UF_6.3V_3
P3V3_S
DIMM1_VREF_CA
0_5%_2
0_5%_2
0.1UF_16V_2
M_B_DQ<59>
1K_5%_2_DY
DRAMRST_CNTRL_CPU
0_5%_20_5%_2
1K_5%_2_DY
AO6402AL
0_5%_2_DY
1K_1%_2
P1V5
0_5%_2_DY
DIMM1_VREF_DQ
0_5%_2_DY
0_5%_2_DY
DIMM0_VREF_DQ
P1V5
P1V5_CPUDDRS
CPU_CHB_VREFDQ
1K_5%_2_DY
0_5%_2_DY
0_5%_2
AO6402AL
CPU_CHA_VREFDQ
1K_1%_2
1K_5%_2_DY
1K_5%_2_DY
62
M_B_DQ<63>
M_B_DQS_DN<1>
DRAMRST_CNTRL_CPU
P1V5
0.1UF_16V_2
P1V5
0_5%_2
0.1UF_16V_2_DY
0_5%_2_DY
C
M_B_DQS_DP<7>
M_B_DQ<56>
P0V75_VREF_M
1K_5%_2_DY
0.1UF_16V_2
0_5%_2_DY
0_5%_2
1K_1%_2
10K_5%_2_DY
0_5%_2
0_5%_2
0_5%_2_DY
0_5%_2_DY
M_B_DQ<62>
PCH_3S_SMDATA
SA0_DIM1
SA1_DIM1
63
61
60
59
58
57
56
55
54
53
52
51
M_B_DQ<50>
M_B_DQ<61>
M_B_DQ<60>
M_B_DQ<58>
M_B_DQ<57>
M_B_DQ<55>
M_B_DQ<53>
M_B_DQ<52>
M_B_DQ<51>
50
M_B_DQ<49>
49
M_B_DQS_DN<7>
M_B_DQS_DN<6>
M_B_DQS_DN<0>
M_B_DQ<38>
M_B_DQ<36>
M_B_DQ<43>
CS_1310AXXXXXX-MTR
M_B_DQS_DN<5>
M_B_DQS_DN<4>
M_B_DQS_DN<3>
M_B_DQS_DN<2>
M_B_DQ<48>
M_B_DQ<47>
M_B_DQ<46>
M_B_DQ<45>
M_B_DQ<42>
M_B_DQ<41>
M_B_DQ<40>
M_B_DQ<39>
M_B_DQ<37>
M_B_DQ<35>
M_B_DQ<32>
M_B_DQ<31>
M_B_DQ<30>
M_B_DQ<29>
M_B_DQ<28>
M_B_DQ<26>
M_B_DQ<25>
M_B_DQ<9>
M_B_DQ<8>
M_B_DQ<7>
M_B_DQ<6>
M_B_DQ<5>
M_B_DQ<4>
M_B_DQ<3>
M_B_DQ<0>
M_B_DQS_DP<6>
M_B_DQS_DP<5>
M_B_DQS_DP<4>
M_B_DQS_DP<3>
M_B_DQS_DP<2>
M_ODT3
M_ODT2
PCH_3S_SMCLK
M_B_WE#
M_B_RAS#
M_B_CAS#
M_CKE3
M_CKE2
M_CLK_DDR3_DN
M_CLK_DDR3_DP
M_CLK_DDR2_DN
M_CLK_DDR2_DP
M_CS#3
M_CS#2
M_B_BS1
M_B_BS0
M_B_A<15>
M_B_A<14>
M_B_A<13>
M_B_A<12>
M_B_A<11>
M_B_A<10>
M_B_A<9>
M_B_A<8>
M_B_A<7>
M_B_A<5>
M_B_A<4>
M_B_A<2>
M_B_A<1>
M_B_A<0>
M_B_DQS_DN<7..0>
M_B_A<15..0>
M_B_DQ<63..0>
7
6
5
4
3
2
1
22<>
27<
27<
0
7
6
5
4
3
2
1
0
22>
22>
29<>
60<
59<>
22>
22>
22>
22>
22>
22>
22>
22>
22>
22>
22>
22>
22>
22>
48
47
45
46
44
43
42
40
41
39
38
37
35
36
34
32
30
29
31
28
27
25
24
23
16
22>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
11
12
10
9
7
6
8
4
5
2
1
3
0
22<>
1UF_6.3V_2
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
BELLW_80001_2021_204P
P0V75_S
1UF_6.3V_2
P1V5
1UF_6.3V_2
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3 10UF_6.3V_3
10UF_6.3V_3
A01
CS
0.1UF_16V_2
M_B_DQ<44>
27>
10K_5%_2
10K_5%_2
SA1_DIM1
10K_5%_2_DY
1K_5%_2_DY
1K_5%_2_DY
M_B_DQS_DP<0>
M_B_DQS_DP<7..0>
M_B_DQS_DP<1>
M_B_DQ<54>
0.1UF_16V_2
2.2UF_6.3V_2
DIMM1_VREF_CA
BELLW_80001_2021_204P
22<>
26<
1K_1%_2
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
D
G
S
NMOS_4D1S
D
G
S
NMOS_4D1S
IN
G2
G1
VTT2
VTT1
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VREF_CA
VREF_DQ
RESET#
EVENT#
NCTEST
NC2
NC1
VDDSPD
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQS#7
DQS#6
DQS#5
DQS#4
DQS#3
DQS#2
DQS#1
DQS#0
DQS7
DQS6
DQS5
DQS4
DQS3
DQS2
DQS1
DQS0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
ODT1
ODT0
SDA
SCL
SA1
SA0
WE#
RAS#
CAS#
CKE1
CKE0
CK1#
CK1
CK0#
CK0
S1#
S0#
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10_AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
IN
IN
OUT
OUT
BI
HDA_3S_SDOUT_R HIGH:ENABLE
WS
LOW:DISABLE
FLASH DESCRIPTOR SECURITY OVERIDE
WS
Disable - (Default)Internal pull-down
1.05V VRM Enable
high- Enable Internal VRs
STRAP
Enable - pull-up
Flash Override
low-Enable External VRs
INTVRMEN-
SATA SSD
CLOSED TO EC
L- (Default) VCC VRM=1.8V
1: No Reboot enabled
H-VCC VRM=1.5V
No Reboot
Placememt note
PCH 1
CLOSED TO PCH
RTC BATTERY
0: (Default) No Reboot disabled
WS
STRAP
STRAP PIN
LOW - Internal
WS
cap on the "P" signal should be
Distance between the PCH and
identical distance between the
PCH and cap on the "N" signal
for same pair
HIGH - ENABLE ANTITHEFT
STRAP PIN
SATA HDD
SATA ODD
eSATA
WS
mSATA
Sun Jan 02 19:22:09 2011
EVEREST-M
Frank Hu
28
97
AD3
SATA_mSATA_TX_DN
SATA_mSATA_TX_DP
SATA_mSATA_RX_DP
SATA_mSATA_RX_DN
SATA_ESATA_TX_DP
SATA_ESATA_TX_DN
SATA_ESATA_RX_DP
SATA_ESATA_RX_DN
+V1.05S_SATAICOMPO
Y11
PCH_TDI
PCH_TDO
PCH_SPI_CLK
HDA_3S_SDOUT_R
FLASH_OVERRIDE
R4773
1
60>
PCH_TCK
PCH_SPI_CS0#
PCH_SPI_SO
PCH_SPI_SI
28>
PCH_TMS
AF3
AB8
AH4
SATA_ODD_TX_DP
Y5
Y3
HDA_3S_SDOUT
0_5%_3
60> 28>
PCH_TDI
PCH_TMS
PCH_TDO
LPC_3S_AD<0>
37<>
37<>
55<
37<>
55<
210_1%_2
61>
60<>
61>
60>
60<>
28>
60>
60<>
28>
61<
1
210_1%_2
1
R4703
100_1%_2
SATA_SSD_TX_DP
AM2321P_DY
CN4701
+V3M_SPI
1K_5%_2
HDA_3S_SDOUT
28>
60<>
51_5%_2
61>
3
P3V3_A
28<>
1
TP4713
dgnd
SSM3K7002FU
P5V_S
HDA_3S_RST#_R
HDA_3S_SYNC_R
SATA_ODD_RX_DP
R4757
37.4_1%_2
HDA_3S_SDOUT_R
61>
10K_5%_2_DY
28<>
28<>
3.3K_5%_2
28<>
28<>
P3V3_AL
0.1UF_16V_2
28<>
28<>
28<>
33_5%_2
37>
37<
28<>
0_5%_2_DY 0_5%_2_DY
37<
60>
28<>
28<>
1uF_6.3V_2
20K_1%_2
+V_RTC
20K_1%_2
1uF_6.3V_2 10M_5%_2
+V_RTC
18pF_50V_2
28>
58<
+V1.05S
43<
37<>
43<
55<43<
43< 55<
55<
+V1.05S
RSC_0402_DY
P3V3_A
100_1%_2 100_1%_2
210_1%_2
PCH_SPI_CS0#
PCH_SPI_SO
EC_SPI_SO PCH_SPI_SO
1.2K_1%_3
330K_5%_3
750_1%_2
R4758
1
2
R4706
1
2
R4708
2
R4704
1
2
R4702
1
2
R4705
2
1
2
2
1
2
R4890
1
2
1
2
1
2
1
2
R4850
1
R4800
1
2
R4804
1
1
22
2
1
2
1
2
R4797
1
2
R4772
1
2
C4766
1
2
1
2
1
2
R4762
1
2
R4760
1
2
1
2
C4762
1
2
R4761
2
1
1
2
2
R4756
1
2
R4812
1
2
1
2
3
1
2
1
2
R4778
1
2
1
2
R4766
1
2
1
2
R4764
1
2
1
7
6
5
2
4
3
1
1
2 3
4
6
1
5
2
4
7
8
3
WINB_W25Q64BVSSIG_SOIC_8P
R4701
2
PCH_XDPFN11
SATA_ODD_TX_DN
SATA_ODD_RX_DN
SATA_HDD_TX_DP
SATA_HDD_TX_DN
SATA_HDD_RX_DP
SATA_SSD_TX_DN
SATA_SSD_RX_DP
SATA_SSD_RX_DN
LPC_3S_FRAME#
LPC_3S_AD<3>
LPC_3S_AD<2>
LPC_3S_AD<1>
RTCX2
+V_RTC_RTCRST#
+V_RTC_SRTCRST#
PCH_XDPFN10
LED_3S_SATA#
A20
C20
D20
G22
K34
E34
G34
N32
J3
H7
K5
H1
T3
T1
V4
Y14
V14
P3
AH1
AB13
AB12
Y10
AB1
AB3
Y1
AD1
Y7
AF1
AB10
AH5
AD5
AD7
AP10
AP11
AM8
AM10
AP5
AP7
AM1
AM3
V5
K36
E36
C37
B37
C38
2
33_1%_2
+V_RTC_INTRUDER#
K22
C17
N34
L34
U4703
1
C4763
R4759
2
C4761
2
33_1%_2
1
T10
SIG442
2
R4769
HDA_3S_SYNC
PCSPKR_PCH_3
CS A01
C
CS_1310AXXXXXX-MTR
RTCX1
10K_5%_2
PCI_3S_SERIRQ
37<>
+V1.05S_SATA3RCOMPO
2
R4755
PCH_SPI_MOSI_R
2
28>
R4823
0_5%_2_DY
R4891
1
SATA_HDD_RX_DN
2
R4813
3
P5V_S
R4754
1
C36
1
A34
C34
R4768
1
2
2
PCH_SPI_CLK_R
PCH_SPI_CS0#_R
60>
R4801
R4786
1
2
+V3M_SPI
+V3M
18pF_50V_2
C4765
X4701
32.768KHZ
U4700
1
R4767
2
ITL_PANTHERPOINT_FCBGA_989P
1uF_6.3V_2
150_1%_3
R4777
D4704
BAT54_30V_0.2A
+V_RTC
2
33_5%_2
0_5%_2
1
R4765
2
1
P3V3_S
+V1.05S
P3V3_S
R4771
10K_5%_2
P1
U3
33_5%_2
10K_5%_2
R4852
49.9_1%_2
43<
D36
PCH_SPI_CLK
28<>
PCH_SPI_SI
37>
33_5%_2_DY 0_5%_2_DY
RSC_0402_DY
2
C4764
EC_SPI_SI
1
R4798 R4802
33_5%_2_DY
1K_5%_2_DY
PCH_XDPFN10
A36
12pF_50V_2
1
2
1
2
PCH_SPI_SI
1
Q4703
1
2
1K_5%_2_DY
A38
1
2
1
R4707
0_5%_2
+V3M_SPI
ACES_91960_0084L_8P
EC_SMI
P3V3_S
R4783
10K_5%_2_DY
PCH_SPI_SO
PCH_SPI_CS0#
61<
60<>
1
2
Q4705
2
1
60<>
0_5%_2
1
R4893
37>
Q4704
33_1%_2
C4779
R4785
HDA_3S_SYNC_R
1
3
1M_5%_2
MAXELL_ML1220_T10_2P
P3V3_S
0_5%_2_DY
HDA_3S_BITCLK_R
33_1%_2
R4770
R4782
2
R4851
SSM3K7002FU
HDA_3S_SDIN0
HDA_3S_RST#
HDA_3S_BITCLK
28<>
PCH_SPI_CS1#
28<>
8
2
1K_5%_2_DY
R4892
28<>
PCH_SPI_CLK
PCH_SPI_SI
+V3M_SPI
PCH_XDPFN11
0_5%_2_DY
1
R4799
EC_SPI_CS0#
3.3K_5%_2
PCH_SPI_CLK
PCH_SPI_SI
U4702
10K_5%_2
28<>
37>
EC_SPI_CLK
33_5%_2_DY
R4803
R4763
1
PCH_SPI_CS1#
PCH_SPI_CS0#
0_5%_2_DY
37<
P3V3_A
SIZE
CHANGE by
DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
BI IN
OUT
BIIN
BI
IN
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
IN
OUT
IN
BI
OUT
OUT
IN
OUT
IN
IN
OUT
IN
G
DS
G
S D
BI
OUT
G
DS
OUT
DIO_ID0
CLK
/HOLD_IO3
VCC
GND
/WP_IO2
DO_IO1
/CS
BI
IN
OUT
BI
BI
BI
BI
OUT
SI
SCK
HOLD#
VDD
VSS
WP#
SO
CE#
BI
BI
IN
BI
BI
OUT
-
+
OUT
NC
BI
OUT
BI
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
SATA 6G
JTAG
SPI
LPC
SATA
IHDA RTC
SATA3RBIAS
SATA3RCOMPO
SATA3COMPI
SATAICOMPO
SPKR
SERIRQ
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
SATA1GP/GPIO19
SATA0GP/GPIO21
SPI_MISO
SPI_MOSI
SPI_CS1#
SPI_CS0#
SPI_CLK
SATAICOMPI
SATA5TXP
SATA5TXN
SATA5RXP
SATA5RXN
SATA4TXP
SATA4TXN
SATA4RXP
SATA4RXN
SATA3TXP
SATA3TXN
SATA3RXP
SATA3RXN
SATA2TXP
SATA2TXN
SATA2RXP
SATA2RXN
SATA1TXP
SATA1TXN
SATA1RXP
SATA1RXN
SATA0TXP
SATA0TXN
SATA0RXP
SATA0RXN
SRTCRST#
HDA_DOCK_RST#/GPIO13
HDA_DOCK_EN#/GPIO33
HDA_SDIN3
RTCRST#
LDRQ0#
FWH4/LFRAME#
LDRQ1#/GPIO23
FWH3/LAD3
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
SATALED#
HDA_SDO
HDA_SDIN2
HDA_SDIN1
HDA_SDIN0
HDA_RST#
HDA_SYNC
HDA_BCLK
INTRUDER#
INTVRMEN
RTCX2
RTCX1
CLOSE TO PCH
PCH 2
USB3.0
WS
WS
REMOVE CLK_XDP_CLKGEN_DP
REMOVE CLK_XDP_CLKGEN_DN
LAN
WS
WS
WLAN
3G
WS
CARD READER
STUFF FOR INTEGRATED CLK
Frank Hu
97
29
EVEREST-M
Sun Jan 02 15:32:31 2011
2
10K_5%_2
P3V3_A
P3V3_S
2
R4894
PCIE_LAN_RX_DN
PCIE_LAN_RX_DP
PCIE_LAN_TX_DN
PCIE_LAN_TX_DP
CLK_PCIE_WLAN_DP
CLK_PCIE_WLAN_DN
AA47
AA48
AB49
10K_5%_2
TP4711
PCIE_CR_TX_DP
0.1UF_16V_2
0.1UF_16V_2
PCIE_CR_TX_C_DP
2
1
PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP
PCIE_CR_TX_DN
PCIE_CR_RX_DP
PCIE_CR_RX_DN
PCIE_USB3_TX_DP
PCIE_USB3_TX_DN
PCIE_USB3_RX_DP
PCIE_USB3_RX_DN
CLKREQ_USB3#
R4895
2
2
R4748
CLKREQ_LAN#
1
10K_5%_2_DY
CLKREQ_WLAN#
10K_5%_2_DY
R4730
1
2
10K_5%_2
R4731
1
2
10K_5%_2
1
10K_5%_2
CLKREQ_CR#
1
CLKREQ_CR#
CLKREQ_USB3#
CLK_PCIE_CR_DP
CLK_PCIE_CR_DN
P3V3_S
P3V3_A
CLK_PCIE_3G_DP
CLK_PCIE_3G_DN
CLKREQ_WLAN#
CLK_PCIE_USB3_DP
CLK_PCIE_USB3_DN
R4740
P3V3_A
10K_5%_2
PCIE_3G_TX_DP
1
R4889
R4859
CLK_XDP_DN
P5V_S
CLK_PCIE_LAN_DN
CLK_PCIE_LAN_DP
CLKREQ_LAN#
ITL_PANTHERPOINT_FCBGA_989P
CLKOUT_ITPXDP_DN
CLK_XDP_DP
A01
C
CS_1310AXXXXXX-MTR
CS
10K_5%_2
R4793
CLKIN_SATA1_DN
CLKIN_PCH14
CLKIN_SATA1_DP
CLKIN_BUF_DOT96_DN
CLKIN_BUF_DOT96_DP
CLKIN_DMI_PCH_DP
CLKIN_DMI_PCH_DN
10K_5%_2
R4787
1
2
10K_5%_2
1
2
R4792
R4788
1
2
10K_5%_2
R4794
1
2
10K_5%_2
1
2
R4796
1
R4795
1
2
TP4703
TP4704
CLKREQ_3G#
Y37
Y36
PCIE_3G_TX_DN
PCIE_3G_RX_DP
PCIE_3G_RX_DN
PCIE_WLAN_TX_DP
PCIE_WLAN_TX_DN
Y45
C4760
A8
1
2
BC38
BE38
AY40
BJ40
BG40
BG38
BJ38
AY36
BH37
BB34
AY34
BE36
BF36
AU34
AV34
BJ36
BG36
AY32
BB32
BF34
BE34
PCIE_CR_TX_C_DN
P3V3_A
P3V3_A
10K_5%_2
2.2K_5%_2
2.2K_5%_2
2.2K_5%_2
29>
39<>
P3V3_A
2.2K_5%_2
SSM3K7002BFU
SSM3K7002BFU
29>
39<>
29>
37<>
29>
37<>
29>
1M_5%_2
29>
18pF_50V_2
25MHz
18pF_50V_2
10K_5%_2
+V1.05S
10K_5%_2
29<>
29<>
39<>
29<
39<>
29<
29<
29<>
29<>
55>
55>
55>
20<
59> 29<
29<59>
29>
29>
10K_5%_2
10K_5%_2
0_5%_2
0_5%_2
0_5%_2
0_5%_2
60<
60<
P3V3_A
2.2K_5%_2
2.2K_5%_2
2.2K_5%_2
2.2K_5%_2
27<
60<
26<
59<>
SSM3K7002BFU
SSM3K7002BFU
55<>
29<>
SML1ALERT#
SML0_CLK
SML0_DATA
SML1_CLK
EC_SMB3_CLK
SML1_DATA
EC_SMB3_DATA
XTAL25_OUT
XTAL25_IN
CLKIN_BUF_CPYCLK_DN
CLKIN_BUF_CPYCLK_DP
PCH_3S_SMCLK
PCH_3A_SMCLK
PCH_3A_SMDATA
PCH_3S_SMDATA
22_5%_2
67<
CLK_GPU_27M
90.9_1%_2
55<>
55<>
10K_5%_2
R4753
2
R4854
1
2
R4855
1
2
R4747
1
2
R4700
1
2
X4700
1
2
C4777
1
2
C4776
1
2
R4849
1
2
R4752
1
2
R4741
1
2
R4751
1
2
R4750
1
2
R4749
1
2
Q4701
3
1
2
Q4700
3
1
2
TP4705
1
R4814
1
2
R4774
1
2
2
R4816
1
2
R4815
1
2
1
2
R4858
1
2
Q4703
3
1
2
Q4702
3
1
2
R4745
1
2
R4744
1
2
R4743
1
2
R4742
1
2
U4700
CLKIN_DMI_PCH_DN
CLKIN_DMI_PCH_DP
CLKIN_BUF_DOT96_DN
CLKIN_BUF_DOT96_DP
CLKIN_SATA1_DN
CLKIN_SATA1_DP
XTAL25_IN
XTAL25_OUT
CLKIN_PCH14
CLKIN_PCI_FB
CLK_PEG_GPU_REF_DN
CLK_PEG_GPU_REF_DP
CLKREQ_GPU_PEG#
DGPU_PRSNT#
CLK_DMI_PCH_DN
CLK_DMI_PCH_DP
CLK_DP_PCH_CPU_DP
CLK_DP_PCH_CPU_DN
CLK_PCIE_LAN_R_DP
PCH_3A_SMCLK
PCH_3A_SMDATA
DRAMRST_CNTRL_PCH
SML0_CLK
SML0_DATA
SML1ALERT#
SML1_CLK
SML1_DATA
CL_CLK
CL_DATA
CL_RST#
TP4712
CLK_PCIE_LAN_R_DN
CLKOUT_ITPXDP_DP
BG37
BB36
BB40
Y43
V45
L12
L14
V46
E6
TP4706
1
AK13
AK14
K12
V37
V38
T13
V42
V40
1
AB40
AB42
11
V10
M1
AB47
J2
1
Y39
Y40
AY38
AW38
AV36
10K_5%_2
1
CLK_GPU_27M_SS_R
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
M10
AB38
AU22
AB37
AV22
AM12
AM13
BF18
BE18
BJ30
G24
AK7
E24
AK5
K45
V49
V47
H45
Y47
K43
F47
K49
H47
T11
P10
BG30
2
1
C4781
2
1
1
PCIE_LAN_TX_C_DN
1
1
2
2
0.1UF_16V_2
C4759
2
1
C4780
AV32
AU32
BJ34
0.1UF_16V_2
PCIE_USB3_TX_C_DP
PCIE_USB3_TX_C_DN
BG34
0.1UF_16V_2
C4757
C4758
1
2
C4783
C4782
0.1UF_16V_2
PCIE_LAN_TX_C_DP
0.1UF_16V_2
AU36
1
C4785
C4784
PCIE_3G_TX_C_DP
PCIE_3G_TX_C_DN
2
PCIE_WLAN_TX_C_DP
PCIE_WLAN_TX_C_DN
0.1UF_16V_2
0.1UF_16V_2
2
1
2
0.1UF_16V_2
SIZE
CHANGE by DATE
8
8 7
7 6
6 5
5 4
4 3
3
2
1
D
D
CC
BB
AA
REV
1
SHEET
2
DOC.NUMBER
of
CODE
INVENTEC
TITLE
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
BI
BI
G
DS
BI
BI
IN
G
DS
IN
IN
IN
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
BI
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
BI
BI
BI
BI
G
DS
G
DS
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
Link
Controller
SMBUS
FLEX CLOCKS
CLOCKS
PCI-E*
PCIECLKRQ6#/GPIO45
CL_RST1#
CL_DATA1
CL_CLK1
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT#/PCHHOT#/GPIO74
SML0DATA
SML0CLK
SML0ALERT#/GPIO60
SMBDATA
SMBCLK
SMBALERT#/GPIO11
CLKOUT_ITPXDP_P
CLKOUT_ITPXDP_N
CLKOUT_PCIE7P
CLKOUT_PCIE7N
PCIECLKRQ7#/GPIO46
CLKOUT_PCIE6P
CLKOUT_PCIE6N
CLKOUT_DP_N
CLKOUT_DP_P
XCLK_RCOMP
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
PCIECLKRQ5#/GPIO44
PCIECLKRQ4#/GPIO26
PCIECLKRQ3#/GPIO25
PCIECLKRQ2#/GPIO20
PCIECLKRQ1#/GPIO18
PCIECLKRQ0#/GPIO73
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_P
CLKOUT_PEG_A_N
CLKIN_PCILOOPBACK
REFCLK14IN
XTAL25_OUT
XTAL25_IN
CLKIN_SATA_P
CLKIN_SATA_N
CLKIN_DOT_96P
CLKIN_DOT_96N
CLKIN_DMI_P
CLKIN_DMI_N
CLKIN_GND1_P
CLKIN_GND1_N
CLKOUT_PCIE5P
CLKOUT_PCIE5N
CLKOUT_PCIE4P
CLKOUT_PCIE4N
CLKOUT_PCIE3P
CLKOUT_PCIE3N
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1P
CLKOUT_PCIE1N
CLKOUT_PCIE0P
CLKOUT_PCIE0N
PETP8
PETN8
PETP7
PETN7
PETP6
PETN6
PETP5
PETN5
PETP4
PETN4
PETP3
PETN3
PETP2
PETN2
PETP1
PETN1
PERP8
PERN8
PERP7
PERN7
PERP6
PERN6
PERP5
PERN5
PERP4
PERN4
PERP3
PERN3
PERP2
PERN2
PERP1
PERN1
STRAP PIN
PCH 3
ISOLATION
low-Disabled
DSWVRMEN - Deep S4/S5 Well On-Die Voltage Regulator Enable
high-Enabled(Default)
CLOSE TO IC
EC
CLOSE TO IC
Frank Hu
EVEREST-M
Sun Jan 02 18:04:44 2011
97
30
SUS_PWR_ACK
L10
0.1UF_10V_2_DY
PM_DRAM_PWRGD
B13
0.1UF_10V_2_DY
C4768
2
1
RSMRST#_R
SUS_PWR_ACK_R
30<
55<>
PCIE_WAKE#
R4775
2
R4735
ITL_PANTHERPOINT_FCBGA_989P
P12
1
10K_5%_2
ALLSYS_PWROK
EC_PCH_PWROK
R4886
1
PM_APWROK
SUSACK#_EC
49.9_1%_2
10K_5%_2
10K_5%_2
P3V3_A
K14
AP14
0_5%_2
R4883
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BH9
BJ10
BG12
AW16