Inventec Everest M Schematics. Www.s manuals.com. Ra01 Schematics

COVER PAGE

WS BULID

EVEREST-M

2010.01.04

EVEREST-M

97

Tue Jan 04 11:08:28 2011

Frank Hu

1

A01

CS_1310AXXXXXX-MTR

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

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2

DOC.NUMBER

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CODE

INVENTEC

TITLE

INDEX

75. VRAM

67. GPU SW/POWER

65. CARDREADER & USB BOARD

55. MINI1 WLAN/Debug Card

56. MINI2 3G

57. HALL SENSOR

59. CLOCK GENERATOR

61. ME JTAG

73. VRAM

72. GPU-5

71. GPU-4

70. GPU-3

69. GPU-2

68. GPU-1

62. PICK BUTTON BOARD

63. TOUCH PAD SW BOARD

64. POWER BUTTON BOARD

74. VRAM

76. VRAM

PAGE

58. LED

60. XDP

66. EMI

50. SATA HDD/SSD & ODD CONN

41. AUDIO CODEC

40. RJ45 & TRANSFORMER

38. FAN & THERMAL

TABLE OF CONTENTS

34. PCH 7 POWER

35. PCH 8 POWER

54. BLUETOOTH CONN

32. PCH 5 USB

31. PCH 4 AXG

28. PCH 1

29. PCH 2

30. PCH 3

39. LAN

37. EC

PAGE

36. PCH 9 GND

33. PCH 6 MISC

42. AUDIO AMP

43. TPM

52. USB CONN

47. DP CONN

48. eDP CONN

17. POWER +V3S/+V5S/+V1.5S

5. POWER SEQUENCE BLOCK

6. POWER FLOW

4. SMB DIAGRAM

3. BLOCK DIAGRAM

2. INDEX

1. COVER PAGE

14. POWER VCORE

PAGE

7. PCB SCREW

16. POWER GPU NVVDD

20. CPU 1

22. CPU 3 DRAM

25. CPU 6 GND

27. DDR3 DIMM1

26. DDR3 DIMM0

24. CPU 5 POWER

23. CPU 4 POWER

21. CPU 2

18. POWER SEQ

19. POWER SEQ

53. K/B & TP/B CONN

51. E-SATA CONN

49. DB CONN USB & CARDREADER

15. POWER VCORE

46. HDMI CONN

45. CRT CONN

44. LCM CONN

13. POWER +V0.85S/+V1.8S

12. POWER VCCP/+V1.05_LAN_M

11. POWER +V1.5/+V0.75S

10. POWER +3A/+5A

9. POWER BATTERY

8. POWER CHARGER

97

2

Frank Hu

Mon Dec 27 16:49:48 2010

EVEREST-M

CS_1310AXXXXXX-MTR

A01

CS

C

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8 7

7 6

6 5

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3

2

1

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AA

REV

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INVENTEC

TITLE

6-Cell

TOUCH PADKEYBOARD

CONN A

DC/DC & IMVP 7

LI-ION BATTERY

SIM CARD

CONNECTOR

HDR(DONGLE)

HDMI 1.4

RJ45

VGA

HDR

R

RGB

HDMI

RGB

PCIE_2

PCIE

PCIE_1

HDR

35W

ATI WHISTLER XT

AMD

29MM X 29MM

PEGX16

PCIE_6

LVDS

DP

FDI

3D PANEL

15.6 WXGA LED

VRAM*4(64Mb*32)

EDP

PERICOM

eDP

MUX

eDP

VT & TXT

DMI 2.0

QC 45W OR DC 35W

SOCKET-RPGA989

IVY BRIDGE

37.5 X 37.5 X 5 mm

TDP 3.9W

25 X 25 X 2.3 mm

EC WINDBOND

NPCE791LA0DX

PCH

SPI

SATA

TPM V1.2

SPI Flash 1MB

WINB_W25Q80BVSSIG

HDA

JTAG

AUDIO CODEC

LS

REALTEK

ALC269Q_VC

USB_13 Minicard 3G

USB_12 Bluetooth

SATA3_1: HDD

SATA3_0: SSD

SATA2_4: mSATA

SATA2_3: eSATA

EXT MIC IN

(TEST ONLY)

HDR

(TEST ONLY)

INTERNAL MIC IN

60-PIN PCH XDP

RJ-11ME JTAG

60-PIN CPU XDP

JTAG

DUAL CHANNEL

(1600MHZ)

204-PIN SODIMM X2

DDR3@1.5/0.75V

MAX MEMORY 8GB X2

USB 2.0

HEADPHONE/LINEOUT

TOTAL:1GB GDDR5

USB_1 eSATA PORT

USB_0 RESERVE FOR USB3.0

USB_2 RESERVE FOR USB3.0

SATA2_2: ZERO POWER ODD

SLB9635TT1.2_FW3.17

LPC

(TEST ONLY)

Gbe Phy

LEWISVILLE

INTEL 82579LM_BAM271

(100/1000)

LVDS

DISPLAYPORT 1.1

(TEST ONLY)

PCIE_3: WIFI

PCIE_4: 3G/mSATA

CARD READER

RTS5209

TI_TUSB7320

BATTERY CHARGER &

CONN B

USB 3.0

USB3.0

USB_10 Webcam

USB_5 Minicard WLAN

WINB_W25Q64BVSSIG

SPI FLASH 8MB

SPI

COUGAR POINT

Frank Hu

97

3

Mon Dec 27 16:50:03 2010

A01

CS_1310AXXXXXX-MTR

C

CS

CODE

of

2

SHEET

1

REV

A A

B B

C C

DD

1

2

3

34

45

56

67

78

8

DATE

CHANGE by

SIZE

DOC.NUMBER

INVENTEC

TITLE

BLOCK DIAGRAM

EVEREST-M

SML1DATA

SML1CLK

SML0DATA

SML1_CLK

SML1_DATA

RES 2.2K

+V3A

SML0_DATA

SML0CLK

RES 2.2K

SMB_DATA

+V3A

RES 2.2K

SSM3K7002

+V3A

LAN PHY

RES 2.2K

+V3LA

RES 2.2K

LEWISVILLE

SMB_DATA

SMB_CLK

RES 2.2K

+V3A

RES 2.2K

SMB_CLK

+V5S

RES 2.2K

+V3S

RES 2.2K

SMB_DATA_S2

SMB_DATA_S3

SMB_CLK_S3

SMB_CLK_S2

SCL2

SDA2

EC

+V3LA

RES 1.8K

3G

PEG

EC_SMB1_CLK

EC_SMB1_DATA

RES 1.8K

THERMAL IC

CHARGE IC

GPU THERMAL

BATTERY

CK505

SO-DIMM 0 SO-DIMM 1

EC_SMB2_CLK

SDA1

SCL1

MINICAR

SMB_DATA_A1

SMB_CLK_A1

XDP

PCH

WLAN

MINICARD3G

NC

SATA

0

1

SSD

HDD

2

ODD

mSATA

eSATA

5

4

3

PCIE

CardReader_RTS5209

USB3.0_TUSB7320

NC

LAN

NC

1

3

2

6

5

4

7

NC

MINICARD

WIFI

SSM3K7002

EC_SMB3_CLK

EC_SMB3_DATA

EC_SMB2_DATA

SMB DIAGRAM

8

USB

MINICARD 3G

BLUE TOOTH

NC

WEBCAM

NC

MINICARD WLAN

NC

eSATA

Reserve for USB3.0

1

0

2

4

3

5

6

7

9

8

11

10

12

13

SML0_CLK

RES 3.3K RES 3.3K

+V3LA

97

Mon Dec 27 16:50:16 2010

4

EVEREST-M

Frank Hu

CS_1310AXXXXXX-MTR

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

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INVENTEC

TITLE

+V0.85S

VCCSA_PG

D0

EN_PSV

+GFX_VDD

BATT_CLK

BATT_DATA

SCL

SDA

CHARGER

GFX_VDD_PG

ACOK

PGOOD

ACIN#

TPS51217

VR_SVID_CLK

VR_SVID_ALRT#

VCLK

VDIO

EN

0.01 OHM

+VPACK

ADAPTER

AM4825P

PMOS

AM4825P

ADP_PRES

KBC_PW_ON

VR_ON

VTT_SELECT

ALERT#

D0

VO

VR_HOT#

VO

VOUT

H_PROCHOT#

TPS51218

VO

EN_PSV

VO

+V1.5

+GFX_PWRGD

VR_PWRGD

+VCC_CORE

+VGFX

PC6014

SLP_S3#_5R

SLP_S5#_5R

SLP_S3#_5R

+V0.75S

+V1.5S

+V5A

+V3LA

PC6014

SLP_S3#_5R

+V5S

+V3S

POWER SEQUENCE BLOCK

+V1.05_VCCP

G2997

(TPS51125)

5/3.3V

VCCDRE_EN

VR_SVID_DATA

MAX17039

EN_PSV

TPS51218

EN_PSV

0.01 OHM

PMOS

TPS51218

+V1.05S

EVEREST-M

Frank Hu

Mon Dec 27 16:50:27 2010

97

5

CS_1310AXXXXXX-MTR

A01

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

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CODE

INVENTEC

TITLE

RST#

TPM

MINICARD X2

RST#

V5LA (-5)

V5A (-1)

V3LA (-3)

V02

V01

VGA

(17)

VCORE

SVID

AND

GATE

CLK

CPU

SM_DRAMPWROK

RSTIN#

VCORE_PWRGOOD (18)

SVID

PWRGD

EN

IMVP7

EN

(4A)

V3.3M

EN

(10)

(11)

EN

PGD

TPS51218DSCR

TI

PGD

V0.85S

V1.05S_VCCP

+V1.05S_VCCP_EN

AND GATE

(9)

AND GATE

SLP_S3#3R

V1.8S

(7)

AND GATE

PM_APWROK (5B)

ALLSYS_PWROK (19)

VCORE

EC_PCH_PWROK (15)

H_CPUPWRGD (16)

PM_DRAM_PWRGD (20)

PWROK

V3A

VIN

M_VREF

APWROK

(3B)

V0.75S

V1.05M

DRAMPWROK

PROCPWRGD

BUF_PLT_RST#

SYS_PWROK

GMT_G2997F6U

BUFFER

RST#

VCC

VIN

EN

VIN

V5A

AM3423PAO4406

EN

GMT

G5694F11U

V1.05S

(7)

(5A)

(11)

EN

VIN

AND GATE

(5A)

(14)

GPU_V3S

AND GATE

AM3423P

V1.05_LAN_VR_PWRGD

EN

VIN

EN

V1.05S_VCCP

AO4406

V3S

(7)

(8)

V1.5S V3.3M (4A)

V3S

VIN

EN

GPU_1.5S

(14)

V1.05_LAN_M (4A)

AM4430N

TI_TPS51125

VREG5

V1.5

V1.5_PG

VBAT

EN2

EN1

XDPLAN

(-4)

V5LA (-5)

+V5AUXON

VCC

RESET#

GMT_G686LT11U

EVEREST PWROWSEQUENCE

VBAT

VSEN

VBAT (-6)

VPACK

MAX_MAX17435ETG

ACIN

VCC

VADPTR (-7START)

RST#RST#

PLERST#

SLP_S5#

SLP_S4#

SLP_LAN#

VBAT

(3A)

VCC

PGD

V3A

TPS51218DSCR

SLP_A#

SLP_S3#

V5A

EN

VIN

SLP_S5#_3R

SLP_S4#_3R (3)

(12)

SLP_LAN#_3R (4)

SLP_S3_5R

MAIN_PWRGD

INVERTER

SLP_S3#_3R (6)

SLP_A_3R

GPIO02

V3LA

VCC

PGD

AM3423P

VIN

V1.5

G5694F11U

EN

VIN

(7)

V5S

SLP_S3#_5R

PGD

V1.05S

AO4406

VIN

EN

VIN

EN

(14)

GPU_1.5S

SLP_A_3R (5M)

V1.5_CPU

(8)

AM4430N

AM3423P

V5A

VIN

EN

V1.5

INVERTER

V1.5

AO4406

VIN

EN

VIN

EN

(14)

GPU_VDD

VBAT

VCC

SC475A

SEMTECH

EC_DGPU_PWR_EN#

GPO82_TEEST#

DAO_GPIO94

DA2_GPIO96

PSDAT2_GPIO27

GPIO43_TMS

GPIO50_TD0

NMOS

GPIO03

EC

99ms

GPIO75

EC_PW_ON

V3A(-1)

ACPRES

V5LA

(-2)

NMOS

GPO84_XORTR#

GPIO01

V5A

(13)

VIN

EN

(15)

(0)

PWR_SWIN#_3

EC_PCH_PWROK

AM3423E

EN

POWER FLOW

VDDR_PWRGD

PM_APWROK (5B)

PWRBTN#

EC_PWRSW# (2)

LRESET# PLT_RST# (21)

GPIO36

SLP_LAN#_3R (4)

RSMRST#

(1)

RSMRST#

PCH

SLP_A_3R (5)

GPIO32_D_PWM

ACOK#

6

97

Mon Dec 27 16:50:39 2010

EVEREST-M

Frank Hu

CS_1310AXXXXXX-MTR

A01

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

FAN

MB

CPU

PCH

PCB SCREW

GPU

MINI CARD

EVEREST-M

Fri Dec 31 10:16:56 2010

97

7

Frank Hu

1

S33

1

S19

1

S11

1

S9

1

S27

1

S17

1

S16

1

S7

1

S14

1

S26

1

S25

1

S23

1

S20

1

S12

1

S3

1

S4

1

S24

1

S22

1

S18

1

S10

1

S1

1

FIX8

1

FIX7

1

FIX6

1

FIX5

1

FIX4

1

FIX3

1

FIX2

1

FIX1

SCREW120_500_0_1P

CS_1310AXXXXXX-MTR

A01

SCREW120_0_500_1P

SCREW320_500_400_1P

SCREW300_1000_1P

SCREW330_600_800_1P

SCREW320_500_400_1P SCREW320_500_400_1P

SCREW120_0_500_1P

SCREW120_0_500_1P SCREW120_0_500_1P

SCREW300_1000_1P

SCREW300_700_1P

SCREW300_1000_1P

SCREW320_500_400_1P

SCREW300_1000_1P

FIX_MASK

SCREW330_600_800_1P SCREW330_600_800_1P

FIX_MASK FIX_MASK

SCREW330_600_800_1P

FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK

SCREW500_1000_1P SCREW300_1000_1P

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

NEAR EC

3A : 0C00H_3.07A

512MA : 0200H_512MA

12.6V : 3140H

16.8V : 41A0H

8.4V : 40D0H

0X15

POWER CHARGER

1.5A : 0600H_1.54A

0X14

3A

2A

NEAR IC

NEAR EC

(1.68V)

(OVP MIN : 23.106V)

(OVP MAX : 24.67V)

EVEREST-M

Frank Hu

8

97

Mon Jan 03 10:52:57 2011

R6042

DIODES_SMAJ20A_13_F_2P

0_5%_2

2

1

G2

2

1

C6035

8A_125V

10PF_50V_2

ACES_91302_0047L_1_4P

MAX_MAX17435ETG+_TQFN_24P

0.1UF_25V_2_DY

2200PF_50V_2

CHG_CHG_SEN_N

PAD6000

C6812

1

NFE31PT222Z1E9L

R6001

RSC_0603_DY

4

1

2

0.1UF_25V_2

2

R6016

10_5%_5

Q6004

1

SSM3K7002BFU

C6021

1UF_10V_2

P3V3_AL

1

0.01UF_25V_2_DY

0.01_1%_6

CHG_VBAT_SEN_P

2

3

R6007

10K_5%_2

12

0.1UF_25V_3

1

2

1

C6023

R6020

4.7K_5%_3

R6005

1

CN6000

FUSE6000

1

C6033

2

POWERPAD_2_0610

CHG_VBAT_SEN_N

2

RSC_0402_DY

R6046

RSC_0603_DY

2

1

RSC_0402_DY

C6003

20

0.1UF_16V_2

2

10K_5%_2

17435_LDO

TP6002

1

1UF_10V_2

C6022

17435_LDO

BAT54C_30V_0.2A

D6001

10K_5%_2

0_5%_2_DY

P_GATE

C6006

FDMC8884

Q6002

C6029

1UF_25V_3

R6000

1

7

2

1

C6811

1

2

1

2

R6044

2

1

R6045

2

1 1

R6043

2

1

C6814

2

1

C6813

2

1

C6817

2

1

3

2

1

D6004

1

2

1

2

1

R6019

R6018

R6017

G1

4

3

2

1

2

R6008

2

1

C6028

2

1

R6013

2

1

R6012

3

2

1

D6000

2

R6036

2

1

2

1

C6030

2

1

R6006

3

2

5

6

7

8

Q6005

2

1

4

3

2

1

L6001

3

2

4 5

6

7

8

Q6003

3

2

1

45

6

7

8

2

43

1

2

1

R6010

2

1

C6016

43 2

1

2

1

C6000

2

1

C6001

2

1

C6005

2

1

C6002

2

1

2

1

L6000

2

1

C6009

2

1

R6004

2

1

D6003

3 2

1

4

5678

Q6000

3 2

1

4

5678

Q6001

2

1

C6007

2

1

C6026

2

1

C6008

1

R6002

2

1

R6014

2

1

C6025

2

1

2

1

TP6000

2

1

R6003

22

21

2

1

25

14

8

4

18

23

24

5

9

3

16

15

11

17

13

6

10

19

U6000

A01

10K_5%_2

0.1UF_25V_3

CSC0402_DY

FDMC8884

4.7_5%_3 4.7UF_25V_5

4.7UF_25V_5_DY4.7UF_25V_5

0.1UF_25V_2

0_5%_2_DY

CS_1310AXXXXXX-MTR

CHG_HG

CHG_SW

CHG_LG

CHG_CHG_SEN_P

RSC_0603_DY

CSC0402_DY

4.7UF_25V_5

TPC8121

0.02_1%_6

PCMC063T_3R3MN

0_5%_2

4.7UF_25V_5

SBR3U40P1

1000PF_50V_2

0.1UF_25V_3

1K_1%_2

4.7_5%_3

1UF_25V_3

BAV99

0.01UF_50V_2

8>

AM4410NC

150_5%_3

AM4410NC

45.3K_1%_2

4.3K_1%_3

1UF_10V_2

10_5%_2

8>

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

1

2

C

A2

A1

1

G1

2

3

4

G2

IN

G

DS

S

PMOS_4D3S

G

D

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

OUT

ACIN

ACOK

LDO

VAA

GND

VCC

SCL

SDA

EN

DCIN

PDSL

CSSP

CSSN

BST

DHI

LX

DLO

PGND-PAD

CSIP

CSIN

BATT

CC

IINP

ADAPTLIM

ITHR

POWER BATTERY

EVEREST-M

9

97

Mon Jan 03 10:53:36 2011

Frank Hu

715K_1%_2

D6101

EZJZ0V500AA

D6102

2

1

GMT_G686LT11U_SOT23_5P

10K_5%_2

R6105

1

2

C6107

BAT54_30V_0.2A_DY

1

4

R6039

1

2

0_5%_2

U6100

360K_1%_2

R6108

1

2

R6109

2

1

R6101

1

1000PF_50V_2

1

EZJZ0V500AA_DY

2

FUSE6100

3

2

1

R6103

2

1

R6104

2

3

5

2

1

D6099

2

1

2

1

D6100

2

1

R6102

2

1

R6110

2

1

R6100

2

1

C6106

5

6

7

3

9

8

G4

G3

G2

G1

2

4

CN6100

EZJZ0V500AA

33_5%_2

102K_1%_3

1K_5%_2

0.1UF_16V_2

SYN_200045GR009G15JZR_9P

100K_1%_2

510K_1%_2

LITTLEFUSE_R451015_15A_65V

C

CS_1310AXXXXXX-MTR

CS A01

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

NC

RESET

GND

VCC

MR

VSEN

G

GND

SMC

SMD

TS

B-I

ID

BATT+

10A

POWER +3A/+5A

TONSEL

7A

4A

SKIPSEL

>>GND=200/250

>>VREF=245/305

>>VRE3=300/375

>>VRE5=365/460

>>GND=PWM

>>VREF=ASKIP

>>VRE3 OR VRE5=OOA

3.8A

Mon Jan 03 10:54:36 2011

10

Frank Hu

97

EVEREST-M

RSC_0603_DY

U6200

C6212

R6210

Q6203

2

C6209

0.22UF_6.3V_2

C6213

22

17

14

13

TI_TPS51125_QFN_24P

16

18

1

CSC0805_DY

1

0.1UF_25V_3

7

1

2

SSM3K7002BFU

P5V_A

EC_PW_ON#

AON7410

24

23

C6208

VCLK

1

VR5A_HG

PAD6204

10<

POWERPAD1X1M

0.1UF_25V_3

VR3AL_PH

Q6206

4.7UF_25V_5

1

100K_5%_2

2

1

R6200 AON7410

Q6805

7

C6215

0_5%_2

C6211

VCLK

0.1UF_25V_2

19

VR3AL_LG

CSC0402_DY

37>

10<

1

C6214

4.7UF_25V_5

PAD6202

1

POWERPAD_2_0610

4.7UF_25V_5 4.7UF_25V_5

2

120K_1%_2

2200PF_50V_2

2

3

2

1

C6216

D6203

BAV99

3

D6202

2

1UF_25V_3

1

R6205

15.4K_1%_2

8

2

3 2

1

4

567

0.1UF_25V_2

BAV99

1

C6218

0.1UF_25V_2

L6200

1

VR5A_LG

11

1

R6204

C6206

1

Q6207

TPC8A05_H

2

1

C6200

R6037

2

1

0.1UF_25V_2

2

C6217

200_5%_2

10>

AON7410

1

SSM3K7002BFU

2

100K_5%_2

EC_PW_ON#

37>

10<

2

PAD6203

2

130K_1%_2

C6205

SSM3K7002BFU

2

R6212

1

3

1

R6201

Q6202

1

2

8

Q6200

1

PAD6205

3

C6219

R6202

3 2

1

4

5678

32

1

4

5678

Q6205

2

1

3

2

32

1

4

56

78

Q6204

2

1

45

6

1

2

1

2

1

C6220

2

1

2

1

2

3

2

D6201

2

1

3

1

R6209

2

C6204

2

1

2

1

R6208

2

1

R6207

2

1

C6202

2

1

PAD6200

2

1

L6201

2

1

C6201

2

1

C6203

2

1

R6206

2

1

2

1

PAD6201

1

2

1

2

C6210

22

C6207

2

8

3

5

2

9

4

25

20

15

6

12

10 21

CS

C

POWERPAD_2_0610

10K_1%_2

POWERPAD_2_0610

BAT54C_30V_0.2A

10UF_6.3V_3

2.2UF_25V_5

RSC_0402_DY

1UF_6.3V_2

4.7UF_25V_5

PCMC063T_3R3MN

POWERPAD_2_0610

330UF_6.3V

10K_1%_2

VR3AL_HG

VR5A_PH

TPC8A05_H 330UF_6.3V

PCMC063T_3R3MN

A01

CS_1310AXXXXXX-MTR

6.8K_1%_2

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

G

DS

IN

C

A2

A1

1

2

G

DS

G

DS

1

2

1

2

+

1

2

1

2

+

1

2

S

G

D

S

G

D

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

DRVL1

LL1

DRVH1

VBST1

PGOOD

VO1

EN0

SKIPSEL

GND

VIN

VREG5

VCLK

DRVL2

LL2

DRVH2

VBST2

VREG3

VO2

TML

ENTRIP2

VFB2

TONSEL

VREF

VFB1

ENTRIP1

22A

3.7A

POWER +V1.5/+V0.75S

1.5A

3.7A

1.5A

20/20 mil

Mon Jan 03 17:25:55 2011

97

11

Frank Hu

EVEREST-M

0_5%_2

P3V3_A

RSC_0402_DY

R6314

P3V3_S

TI_TPS51218DSCR_SON_10P 2.2_5%_3

VR15_PH

1

0.1uF_25V_3

2

R6302

V1.5_PG

SLP_S4#

SLP_S3#

0_5%_2_DY

R6307

R6306

+V1.5S_CPUDDR_PG

C6312

1000PF_50V_2_DY

10

1

1uF_10V_2

22uF_6.3V_5

C6306

POWERPAD_2_0610

PCMC104T_1R0MN

5

4

3

2

1

11

200K_1%_2

R6311

CSC0402_DY

C6301

95.3K_1%_2

2

VR15_LG

R6301

4.7uF_25V_5

1

C6305

2

U6302

2

2.2uF_6.3V_3

C6303

4.7uF_25V_5

TPCA8065_H

1

2

10

2

SLP_S4#

6

PAD6300

2

POWERPAD_2_0610

3

U6300

Q6301

TPCA8A02_H

C6815

1

560uF_2.5V

11.5K_1%_2

2200PF_50V_2

2

C6304

2

1

2

C6302

C6309

1

P1V5

4.7uF_25V_5

4

2

VR15_HG

POWERPAD_2_0610

CS

C

POWERPAD_2_0610

10K_1%_2

22uF_6.3V_5

18<

0_5%_2

30>

11<

37<

11<

37<

30>

17<18<37<

CS_1310AXXXXXX-MTR

0.1UF_16V_2

A01

4.7_5%_3

GMT_G2997F6U_MSOP10_10P

30>

9

6

8

7

Q6300

8765

4 3

8765

4

1

23

PAD6301

1

2

PAD6303

1

2

PAD6302

2

1

2

1

2

1

R6310

1 1

2

1

2

C6300

1

2

1

2

R6304

1

R6303

1

8 4

7

9

11

2

5

C6307

1

2

1

C6308

1

2

C6311

1

2

L6300

1

2

3

1

2

1

2

R6047

1

2

1

2

1

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

+

IN

1

2

TML

VTTREF

S3

GND

S5

VIN

VTTSNS

PGND

VTT

VLDOIN

VDDQSNS

OUT

1

2

1

2

1

2

S

G

D

NMOS_4D3S

D

G

S

DRVL

V5IN

SW

DRVH

VBST

GND

RF

VFB

EN

TRIP

PGOOD

1.5A

28A

POWER VCCP/+V1.05_LAN_M

3.3A

0.5A

EVEREST-M

12

97

Mon Jan 03 17:26:41 2011

Frank Hu

POWERPAD_2_0610

2

R6403

2.2UF_6.3V_3

2

P3V3_A

U6401

GMT_G5694F11U_SOP_8P

8

2

SLP_LAN#

R6452

1

20K_1%_2

1

2

RSC_0402_DY

PAN_ETQP4LR36WFC_4P

0.22UF_25V_3

1

VSS_SENSE_VTT

2

0_5%_2

9.53K_1%_2

R6413

0.1UF_10V_2_DY

C6415

7

3

VRVCCP_PH

3

2

0_5%_2

13<

VTT_PG

1

C6410

1

PAD6403

PAD6401

2

POWERPAD_2_0610

4.7UF_25V_5

2

4.7UF_25V_5

2

Q6401

TI_TPS51218DSCR_SON_10P

U6400

R6411

4

VRVCCP_LG

1

10K_5%_2

2

1

PAD6400

2

1

C6450

2

1

C6451

2

1

R6451

2

1

R6450

2

1

R6454

2

1

C6453

2

C6452

2

1

C6454

2

1

L6450

1

9

2

6

7

3

4

5

2

1

R6415

1

R6416

2

R6414

2

1

R6417

1

2

1

R6410

2

1

C6414

2

1

2

1

C6407

1

2

1

PAD6402

2

1

C6401

1

C6406

1

C6403

2

4

2

1

L6403

3 2

1

4

5 6 8

Q6400

3 2

1

4

5 6 7 8

2

1

2

1

R6402

1

C6411

2

R6400

2

1

R6405

2

1

C6413

10

7

8

5

11

6

9

+V1.05_LAN_M

44.2K_1%_2

POWERPAD_2_0610

TPCA8065_H

22UF_6.3V_5

CS_1310AXXXXXX-MTR

A01

POWERPAD_2_0610

VRVCCP_HG

VCC_SENSE_VTT

CSC0402_DY

37< 19<

30>

0_5%_2

0.1UF_16V_2

10_5%_3

10UF_6.3V_3

470K_1%_2

P3V3_S

2.2_5%_3

0.1UF_16V_2

LTF5022T_2R2N3R2_LC

10K_1%_2

3.09K_1%_2 CSC0402_DY

23>

TPCA8057_H

1000PF_50V_2_DY

100_5%_2

200_1%_2

23>

560UF_2.5V

4.7UF_25V_5

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

1

2

IN

OUT

REF

FB

LX

TML

GND

PGND

EN

VCC

VIN

IN

+

1

2

1

2

1

2

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

DRVL

V5IN

SW

DRVH

VBST

GND

RF

VFB

EN

TRIP

PGOOD

POWER +V0.85S/+V1.8S

3A

1.6A

6A

LOW - 0.9V

HIGH - 0.8V

EVEREST-M

97

13

Frank Hu

Mon Jan 03 17:27:17 2011

PCMC063T_3R3MN

2

POWERPAD_2_0610

C6508

0.1UF_10V_2_DY

1

PAD6503

330UF_2V_9MR_PANA_-35%

200_1%_2

R6506

6.49K_1%_2

2

1000PF_50V_2_DY

200_1%_2

1

TI_TPS51217DSCR_SON_10P

2

AON7410

Q6500

11

R6509

CSC0402_DY

2

78.7K_1%_2

LMBT3904LT1G

U6500

6

2.2UF_6.3V_3

1

5

4.7UF_25V_5

VR85_PH

7

6

1

RSC_0402_DY

Q6501

1

R6510

VCCSA_SEL

24>

1

VR85_LG

C6504

P3V3_A

1

0_5%_3

VR85_HG

1

2

10K_5%_2

R6501

10

4

1

C6507

40.2K_1%_2

2

1

R6500

9

1

2

0_5%_2

3

1

2

PVBAT

TPC8A05_H

2

R6511

C6505

47PF_50V_2

0.22UF_25V_3

4.7UF_25V_5

L6500

C6514

10UF_6.3V_3

0.1UF_16V_2

GMT_G5694F11U_SOP_8P

9

LTF5022T_2R2N3R2_LC

13K_1%_2

POWERPAD_2_0610

PAD6501

1

U6502

8

3 2

5 7 8

3 2

1

4

678

4

2

5

8

2

1

R6517

2

1

R6516

2

1

2

1

C6512

2

1

R6515

2

1

R6514

2

1

C6515

2

1

C6511

2

1

2

C6506

2

1

2

1

R6505

R6504

2

1

R6503

2

1

2

1

C6501

2

1

C6500

2

1

C6502

C6503

1

2

2 3

Q6502

2

1

3

Q6503

R6507

2

1

C6510

2

1

2

1

R6508

1

R6502

2

1

PAD6500

2

1

C6513

2

1

L6502

1

2

6

7

3

4

5

CS_1310AXXXXXX-MTR

22UF_6.3V_5

CSC0402_DY

10_5%_3

0.1UF_16V_2

20K_1%_2

P5V_A

1K_1%_2

10K_5%_2

SSM3K7002BFU

10K_1%_2

20K_1%_2

4.7UF_25V_5

POWERPAD_2_0610

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

+

IN

B

C E

G

DS

1

2

1

2

1

2

REF

FB

LX

TML

GND

PGND

EN

VCC

VIN

S

G

D

NMOS_4D3S

D

G

S

VFB

VBST

V5IN

TRIP

TRAN

SW

PGOOD

GND

EN

DRVL

DRVH

CATCH R

POWER VCORE

10A

FOLLOW BERLIN 10RG

CATCH R

Mon Jan 03 17:28:44 2011

Frank Hu

97

14

EVEREST-M

1

470PF_50V_2

20.5K_1%_2

IMAXA

14<

10_1%_2

1

C6608

14<

15<

VRCPU_HG2

2.2UF_6.3V_2

IMONA

14<

53

VRCPU_HG3

CPU_BST3

VRCPU_PH3

VRCPU_LG3

12

10

VRAXG_LG1

GPU_BST1

VRAXG_HG1

14<

IMAXA

51

50

49

R6602

1

100_1%_2

U6600

54

56

52

MAX_MAX17039GTN+_TQFN_56P

0_5%_2

15<

VRCPU_PH2

8

TONA

9

VRAXG_PH1

CCVB

IMONB

FBB

THERMA

THERMB

470PF_50V_2

C6610

TP6600

13

14<

24

25

26

27

28

1

5.1K_1%_2

14>

VBOOTB

SRB

14<

22

40

41

42

15<

14<

SRA

VBOOTA

14

IMAXB

14<

CS

CS_1310AXXXXXX-MTR

C

14<

24>

20.5K_1%_2

23>

14<

0_5%_2 115K_1%_2

470PF_50V_2

0_5%_2 115K_1%_2 100K_5%_2

4.87K_1%_2

14<

P5V_A

14<

P3V3_S

178K_1%_2

+VBAT_CPU

4.87K_1%_2

14<

P5V_A

14<

2.2UF_6.3V_2

TP24

2.2UF_6.3V_2

15<

P5V_A

14<

15<

14<

1000PF_50V_2

10_1%_2

23>

14<

10_1%_2

15<

PVBAT

POWERPAD_2_0610

4.7UF_25V_5

1000PF_50V_2

4.7UF_25V_5 4.7UF_25V_5

PVAXG

4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5

+VBAT_CPU

4.7UF_25V_5

VSSAXG_SENSE

VSSSENSE

THERMB

SRB

VBOOTB

IMAXB

TONB

THERMA

SRA

VBOOTA

CCVA

TONA

PH3_PWM

GNDSA

CPU_BST2

VRCPU_LG1

VRCPU_LG2

VRCPU_HG1

CPU_BST1

PH3_SKIP#

PH3_PWM

VRCPU_PH1

CCVA

IMONA

GNDSA

FBA

GNDSB

FBB

A01

FBA

14<

P5V_A

178K_1%_2

+VBAT_CPU

P3V3_A

0_5%_2

P5V_A

1UF_6.3V_2

P5V_A

470PF_50V_2

100_1%_2

VCCSENSE

P5V_A

14<

CCVB

P3V3_A

100K_5%_2

1

37

16

48

46

7

36

38

29

19

57

30

18

17

35

43

15

20

34

23

21

5

6

4

3

39

11

2

55

44

45

C6618

1

2

R6623

2

R6611

1

2

C6611

1

2

C6617

1

2

C6616

1

2

TP6601

1

R6616

2

R6614

1

2

R6612

1

2

C6614

1

2

C6613

1

2

R6603

1

2

C6609

1

2

R6601

1

2

U6602

1

8

4

3

7

9

2

6

5

C6619

1

2

PAD6600

1

2

C6601

1

2

C6600

1

2

C6602

1

2

C6603

1

2

C6604

1

2

C6605

1

2

C6606

1

2

C6607

1

2

R6622

1

2

R6620

1

2

R6624

1

2

R6626

1

2

R6618

1

2

R6619

1

2

C6615

1

2

R6621

1

2

R6606

1

2

R6625

1

2

R6608

1

2

R6627

1

2

R6607

1

2

1

2

R6609

1

2

R6617

1

2

R6604

1

22

1

14<

PH3_SKIP#

33

31

32

9.53K_1%_2

R6605

2

MAX_MAX8791GTA+_TQFN_8P

0_5%_2

C6612

IMONB

14<

TONB

2K_5%_2

1

10K_5%_2

2

R6610

2K_5%_2

15<

47

1

R6038

1

2 2

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

LX

PWM

SKIP

VDD

PAD

DH

BST

DL

GND

IN

1

2

IN

OUT

IN

N.C.

IMONA

CCVA

DRSKIP

PWM_OUT

BSTA1

DHA1

DLA2

CSNA3

LXA2

VRA_READY

VRB_READY

CSPA1

CSNA1

CSNA2

CSPA2

CSPA3

IMAXA

IMAXB

TMAX

VR_HOT#

AGND

ALERT#

VDIO

VCLK

VCC

TONA

TONB

CSPB

CSNB

VR_ENABLE

DLG

VDDB

DLB

BSTB

DHB

VBOOTB

VBOOTA

CCI2

CCI1

SRA

SRB

THERMA

THERMB

FBB

GNDSB

IMONB

CCVB

LXB

GND

DHA2

BSTA2

VDDA

DLA1

LXA1

GNDSA

FBA

POWER VCORE

33A

60A

Mon Jan 03 17:29:38 2011

15

97

Frank Hu

EVEREST-M

2

14<

4.7_5%_3

R6718

1

+VBAT_CPU

0.22UF_25V_3

2.2_5%_3

R6716

2.2_5%_3

0.22UF_25V_3

R6723

L6700

2

VRAXG_PH1

1

2

L6703

0.47UF_6.3V_2

2

C6710

RSC_0402_DY

2

3.6K_1%_2

R6714

2

VRCPU_HG2

14<

L6701

TPCA8065_H

CS

C

14<

+VBAT_CPU

2.37K_1%_2

0.47UF_6.3V_2

RSC_0402_DY

10K_5%_NTC

PAN_ETQP4LR36ZFC_4P

4.7_5%_3

14<

TPCA8065_H

14<

TPCA8065_H

PAN_ETQP4LR36ZFC_4P

RSC_0402_DY

PAN_ETQP4LR36ZFC_4P

14<

+VBAT_CPU

1500UF_2V

PVCORE

470UF_2V

VRCPU_LG3

VRCPU_PH3

VRCPU_HG3

VRCPU_LG1

VRCPU_HG1

VRCPU_PH1

CPU_BST3

CPU_BST1

VRAXG_LG1

VRAXG_HG1

GPU_BST1

VRCPU_LG2

CPU_BST2

A01

CS_1310AXXXXXX-MTR

GPU_CSP1

3.6K_1%_2

10K_5%_NTC

2.37K_1%_2

0.47UF_6.3V_2

3300PF_50V_2

TPCA8057_H

3.6K_1%_2

3300PF_50V_2

4.7_5%_3

TPCA8057_H

TPCA8065_H

2.2_5%_3

0.22UF_25V_3

TPCA8057_H

PAN_ETQP4LR36ZFC_4P

4.7_5%_3

2.37K_1%_2

14<

VRCPU_PH2

2.2_5%_3

14<

GPU_CSN1

8765

4

1

23

Q6703

8765

4

1

23

C6707

1

2

R6705

1

2

C6706

1

2

Q6705

8765

4

1

23

1

2

L6702

1

3 4

R6711

1

2

C6709

1

Q6704

8765

4

1

23

C6711

1

2

C6712

1

2

Q6701

8765

4

1

23

Q6700

8765

1

23

C6700

1

2

R6700

1

2

1

3 4

R6717

1

2

C6714

1

2

Q6707

8765

4

1

23

Q6706

8765

4 23

C6713

1

2

1

2

3 4

1

2

C6701

2

1

3

C6704

1

2

3

1

2

3 4

R6706

1

2

R6708

1

2

R6709

2

C6708

1

2

R6701

1

2

R6703

1

2

R6704

1

2

C6703

1

2

R6719

1

2

R6721

1

2

R6722

1

2

C6715

1

2

1

2

1

2

R6715

1

R6707

1

22

R6720

1

2

R6702

1

2

3300PF_50V_2

0.47UF_6.3V_2

1

RSC_0402_DY

TPCA8057_H

2.37K_1%_2 10K_5%_NTC 3.6K_1%_2

3300PF_50V_2

1

R6713

10K_5%_NTC

1

R6712

0.22UF_25V_3

4

1

R6710

2

+VBAT_CPU

Q6702

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

+

IN

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

IN

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

IN

NMOS_4D3S

D

G

S

IN

NMOS_4D3S

D

G

S

IN

NMOS_4D3S

D

G

S

IN

+

NMOS_4D3S

D

G

S

3.5A

POWER GPU NVVDD

1

0

1

0

VID1

VOLTAGE LEVEL

NVVDD

1V

0.975V

0.825V

30A

CONNECT TO GPU

FOR OPTIMUS SHUTDOWN SOLUTION

VID0

0

16

97

Tue Jan 04 00:17:23 2011

EVEREST-M

Frank Hu

TI_TPS51217DSCR_SON_10P

C6800

47PF_50V_2

2

5

11

1

R6805

U6800

8

VRGPU_HG

2

C6803

TPCA8065_H

SSM3K7002BFU

40.2K_1%_2

3

10

4.7UF_25V_5

L6800

2

470UF_2V

100_5%_2

R6810

2

PAD6801

1

0_5%_3

0.1UF_25V_2

1

PAD6800

POWERPAD_2_0610

2

1

C6810

2

1

R6048

2

1

C6816

2

1

R6808

2

1

3

Q6804

2

1

D6800

1

2

1

R6803

2

1

C6807

2

1

C6805

1

3 2

1

4

5 6 7 8

Q6800

2

1

C6809

2

1

R6806

2

1

R6041

2

1

R6040

2

1

R6807

2

1

Q6803

2

1

C6802

2

1

R6809

2

1

C6806

1

C6808

2

1

PAD6803

2

1

2

1

43

1

3

2

1

4 5

6

7

8

Q6802

3

2

1

4 5

6

7

8

Q6801

2

1

C6804

2

R6804

4 7

1

6

9

A01

TPCA8A02_H

POWERPAD_2_0610

470UF_2V470UF_2V

0_5%_2

28.7K_1%_2

SBR3U40P1_DY

VRGPU_LG

86.6K_1%_2

CS_1310AXXXXXX-MTR

CS

C

100PF_50V_2

33.2K_1%_2

+GPU_NVVDD_L

VRGPU_PH

68>

4.7UF_25V_5

10.2K_1%_2

CSC0402_DY

4.7UF_25V_5

PAN_ETQP4LR36WFC_4P

TPCA8A02_H

2.2UF_6.3V_3

SSM3K7002BFU

1K_1%_2

0_5%_2

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

+

G

DS

OUT

NMOS_4D3S

D

G

S

G

DS

+

1

2

1

2

1

2

S

G

D

S

G

D

VFB

VBST

V5IN

TRIP

TRAN

SW

PGOOD

GND

EN

DRVL

DRVH

POWER +V3S/+V5S/+V1.5S

WS

11.5A

EVEREST-M

Frank Hu

Fri Dec 31 10:16:26 2010

97

17

2

1

R7036

3

2

1

45

6

7

8

Q7002

4

36

5

2

1

Q7004

4

36

5

2

1

Q7005

2

1

R7034

2

1

C7027

2

1

R7035

2

1

3

Q7088

2

1

3

Q7090

2

1

R7039

2

1

C7030

2

1

PAD7002

2

1

R7032

2

1

3

Q7000

2

1

3

Q7001

2

1

R7033

2

1

C7026

2

1

C7029

2

1

PAD7001

2

1

3

Q7003

2

1

R7038

2

1

PAD7000

2

1

C7028

2

1

R7037

P1V5

POWERPAD_2_0610

100K_5%_2

SLP_S3#_15R

SLP_S3_5R

CS_1310AXXXXXX-MTR

200_5%_3

17>

SLP_S3#_15R

22_5%_2

POWERPAD_2_0610

SSM3K7002BFU

P15V_A

17<

CS

SLP_S3_5R

SLP_S3#_15R

SLP_S3#

P3V3_S

17> 17< 19<

SSM3K7002BFU

P1V5_S

200_5%_2

POWERPAD_2_0610

680PF_50V_2

22UF_6.3V_5

CSC0402_DY

17>19<

AON7410

750K_1%_2

19< 18<

24<

SSM3K7002BFU

P0V75_S

SSM3K7002BFU

19< 17< 17>

P3V3_AL

AO6402AL

P5V_AL

0_5%_2

24<

19<18<17<

SSM3K7002BFU

P5V_S

CSC0402_DY

0_5%_2

10K_5%_2

37<

18<

11<

30>

AO6402AL

P5V_A

A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

1

2

NMOS_4D3S

D

G

S

D

G

S

NMOS_4D1S

D

G

S

NMOS_4D1S

IN

OUT

IN

G

DS

G

DS

OUT

1

2

OUT

IN

G

DS

OUT

G

DS

IN

1

2

G

DS

POWER SEQ

WS

Frank Hu

EVEREST-M

Fri Dec 31 10:16:27 2010

18

97

2

1

C7000

2 3

1

Q7064

2

1

R7000

2

1

R7009

2

1

R7030

2

1

C7002

2

1

R7029

2

1

3

D7001

2

1

R7001

2

1

C7025

2

1

R7028

2

1

3

Q7053

2

1

C7008

2

1

R7010

2

1

C7003

2

1

R7007

2

1

R7008

2

1

C7005

5

2

4

3

1

U7005

2

1

R7031

2

1

R7027

2

1

R7016

2

1

R7026

2

1

R7014

2

1

R7015

2

1

R7013

2

1

C7013

5

4

3

2

1

U7004

2

1

R7023

2

1

3

D7000

2

1

R7024

2

1

R7025

2

1

3

Q7065

2

1

C7006

2

1

C7004

2

1

R7006

2

1

C7012

5

4

3

2

1

U7003

2

1

R7002

2

1

R7003

2

1

C7001

2

1

R7004

2

1

C7011

5

4

3

2

1

U7002

2

1

C7010

5

4

3

2

1

U7001

2

1

C7009

2

1

R7005

5

4

3

2

1

U7000

P3V3_A

+V1.05_LAN_PG

1K_5%_2

TC7SZ08FU

DRAMRST_CNTRL_CPU

DDR3_DRAMRST#

26>

BSH111

4.99K_1%_2

CPU_DRAMRST#

1K_5%_2

P1V5

27>

20>

0_5%_2

A01

CS_1310AXXXXXX-MTR

CS

C

0_5%_2

EC_PCH_PWROK

38<

0.1UF_16V_2

P3V3_A

59<

11>

+V1.5S_CPUDDR_PG

P3V3_A

SLP_S3#

0_5%_2

+V1.05_LAN_PG

37<

18<

10K_5%_2

TC7SZ08FU

3.3K_5%_2

0.1UF_16V_2

309K_1%_2

10K_5%_2

+V1.05_LAN_M

110K_1%_2

LMBT3904LT1G

0_5%_2

1000PF_50V_2

+V1.5S_CPUDDR_PG

470PF_50V_2

+V1.05S_VCCP_EN

PM_APWROK

ALLSYS_PWROK

VR_PWRGD

DRAMRST_CNTRL_PCH

DRAMRST_CNTRL_EC

SLP_A#

V1.5_PG

MAIN_PWRGD

VCCSA_PG

SLP_S3#_15R

12<

0.1UF_16V_2

P3V3_A

0_5%_2

0.1UF_16V_2

P3V3_A

30<

P3V3_A

0.1UF_16V_2

TC7SZ08FU

0.1UF_10V_2_DY

37<

17< 11<

30>

14>

37>30<

18<

TC7SZ08FU

P3V3_A

10K_1%_2

0.1UF_16V_2

1K_5%_2

0_5%_2_DY

BAT54_30V_0.2A

18<19<

37< 30>

0.1UF_16V_2

18>

P3V3_A

0.1UF_16V_2

1UF_6.3V_2

19< 30>

+V3M

100K_5%_2

10K_5%_2_DY

0_5%_2

20<

1M_1%_2

TC7SZ08FU

60> 37<

14<

AZV331KTR_E1

100K_1%_2

1000PF_50V_2

11<

20<

18<

0.1UF_10V_2_DY

P3V3_SP3V3_A

10K_5%_2

SSM3K7002BFU

10K_5%_2

BAT54_30V_0.2A

330_5%_2

19<

17>

24<

17<

P1V5_CPUDDRS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

+

-

OUT

IN

OUT

+

-

IN

NC

G

DS

OUT

IN

OUT

+

-

IN

OUT

+

-

IN

OUT

B

C E

IN

NC

G

DS

OUT

+

-

OUT

+

-

POWER SEQ

EVEREST-M

19

97

Fri Dec 31 10:16:27 2010

Frank Hu

3

2

1

45

6

7

8

Q7052

3

2

1

45

6

7

8

Q7062

2

1

C7024

2

1

C7023

2

1

C7022

2

1

C7021

2

1

C7020

2

1

C7007

2

1

R7012

2

1

R7011

2

1

R7017

2

1

C7017

2

1

C7015

2

1

C7014

2

1

R7018

2

1

R7019

2

1

C7019

2

1

R7021

2

1

C7018

2

1

C7016

2

1

R7020

2

1

R7022

2

1

PAD7003

4

3 6

5

2

1

Q7006

2

1

3

Q7051

2

1

3

Q7058

2

1

3

Q7059

2

1

3

Q7060

2

1

3

Q7061

2

1

3

Q7063

A01

P3V3_A

AON7410

0.1UF_10V_2_DY

200_5%_2

CS_1310AXXXXXX-MTR

SLP_S3#_15R

SLP_A#

SLP_S3_5R

SLP_LAN#

17<

24<

18< 17>

37<

18< 30>

SSM3K7002BFU

P1V5

SSM3K7002BFU

0_5%_2

AON7410

17>17<

470PF_50V_2

SSM3K7002BFU

200_5%_2

680PF_50V_2

SSM3K7002BFU

P1V5_CPUDDRS

10K_1%_2

P5V_A

220K_5%_2

P5V_A

+V1.05_LAN_M

10UF_6.3V_3

+V1.05M

P1V05_VCCPS

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

12<

30>37<

SSM3K7002BFU

0.1UF_16V_2

P1V5

P1V5_CPUDDRS

SSM3K7002BFU

200_5%_3

POWERPAD_2_0610

10UF_6.3V_3

+V1.05S

47K_5%_2

P3V3_A

100K_5%_2

0.01UF_50V_2

330PF_50V_2_DY

AM3423P

10UF_6.3V_3

+V3M

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

S

PMOS_4D1S

G

D

NMOS_4D3S

D

G

S

G

DS

NMOS_4D3S

D

G

S

G

DS

IN

G

DS

G

DS

G

DS

IN

1

2

IN

G

DS

(Default)

Place close to CPT and NVRAM connector

DMI&FDI TerminationVoltage

Set toVss when LOW

Set toVcc when HIGH

NV_CLE

CPU 1

LOW IN C6/C7

CLKOUT_DMI_CLKGEN_DN

WS

REMOVE CLKOUT_DMI_CLKGEN_DP

Frank Hu

EVEREST-M

Fri Dec 31 10:16:28 2010

97

20

2

1

R4513

2

1

3

Q4500

2

1

R4512

2

1

R4511

2

1

C4559

5

4

1

2

3

U4501

4

5

3

1

2

U4502

2

1

R4508

2

1

R4509

2

1

R4558

2

1

R4532

2

1

R4500

2

1

C4504

2

1

R4510

2

1

R4536

2

1

R4516

2

1

R4506

2

1

R4538

2

1

R4537

2

1

R4557

2

1

C4570

2

1

R4552

2

1

R4555

2

1

R4553

2

1

R4554

2

1

R4556

2

1

R4529

2

1

R4505

2

1

R4507

2

1

R4531

2

1

R4530

2

1

R4541

2

1

R4542

2

1

R4533

2

1

R4534

2

1

R4535

2

1

R4517

1

TP4500

AP33

AP30

AR27

AN32

AP26

AR28

AR26

A4

A5

AK1

R8

V8

AN34

AR33

AL32

C26

AP27

AP29

AM34

AN33

A15

A16

AL35

AL33

AR32

AT31

AR31

AP32

AT30

AR30

AR29

AT28

A27

A28

CN4500

0_5%_2

H_SNB_IVB#

H_CATERR#_R

43_5%_2

56_5%_2

0_5%_2

PM_THRMTRIP#_R

SM_RCOMP2

CLK_DP_PCH_CPU_R_DN

CLK_DP_PCH_CPU_R_DP

CLKOUT_DMI_PCH_R_DN

CLKOUT_DMI_PCH_R_DP

CLK_DMI_PCH_DN

0_5%_2

CLK_DMI_PCH_DP

CLK_DP_PCH_CPU_DP

20>

H_PECI

PM_THRMTRIP#

H_PECI_R

PM_DRAM_PWRGD_R

0_5%_2

H_PM_SYNC

H_CPUPWRGD

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

P3V3_S

H_CPUPWRGD_R

H_PM_SYNC_R

SM_RCOMP1

SYS_RESET#_R

H_TDO

75_5%_2

BUF_PLT_RST# BUF_PLT_RST#_CPU

32<>

43<

56< 55<

43_5%_2

0.1UF_16V_2

P1V05_VCCPS

0_5%_2_DY

20<

TSB_TC7SZ07FU_SSOP_5P

P1V05_VCCPS

37<>

33<

200_5%_2

P1V5_CPUDDRS

H_BPM7_XDP#

H_BPM6_XDP#

H_BPM5_XDP#

H_BPM4_XDP#

H_BPM3_XDP#

H_BPM2_XDP#

H_BPM1_XDP#

H_BPM0_XDP#

H_TDI

H_TRST#

H_TMS

H_TCK

H_PREQ#

H_PRDY#

BUF_PLT_RST#_CPU

H_PROCHOT#_R SM_RCOMP0

CPU_DRAMRST#

H_PROCHOT#

33>

39_5%_2

0.1UF_16V_2

4.7K_5%_2

NV_CLE

130_1%_2

P1V8_S

2.2K_5%_2

14>

30<>

P3V3_A

60>

NXP_74AHC1G09GV_SOT753_5P

SLP_S3_5R

PM_DRAM_PWRGD

P3V3_A

200_5%_2

H_CPUPWRGD_R

+V1.5S_CPUDDR_PG

H_SNB_IVB#

H_TDI

H_PREQ#

H_TRST#

H_TCK

H_TMS

SYS_RESET#

CLK_DP_PCH_CPU_DN

10K_5%_2

18<

18>

30>

20>

100K_5%_2_DY

32>

SSM3K7002BFU

47PF_50V_2

62_5%_2

0_5%_2_DY

20>

33>

0_5%_2

20< 60>

60>20<

20< 60>

60<>

60>20<

51_5%_2

51_5%_2_DY

51_5%_2

60<

51_5%_2

P1V05_VCCPS

60<

60<>

20<60>

60> 20<

20<60>

60<>

20<60>

60<>

0_5%_2

60> 30<

20<60>

60<

200_1%_2

25.5_1%_2

140_1%_2

18>

0_5%_2

29>

CS_1310AXXXXXX-MTR

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

OUT OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

G

DS

IN

VCC

OUT-Y

NC

IN-A

GND

Y

VCC

GND

B

A

JTAG & BPM

MISCDDR3

PWR MANAGEMENT

THERMAL MISC

CLOCKS

UNCOREPWRGOOD

PROC_SELECT#

SKTOCC#

PM_SYNC

BPM#[7]

BPM#[6]

BPM#[5]

BPM#[4]

BPM#[3]

BPM#[2]

BPM#[1]

BPM#[0]

DBR#

TDO

TDI

TRST#

TMS

TCK

PREQ#

PRDY#

RESET#

SM_DRAMPWROK

THERMTRIP#

PROCHOT#

PECI

CATERR#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK

BCLK#

SM_RCOMP[0]

SM_DRAMRST#

SM_RCOMP[2]

SM_RCOMP[1]

CPU 2

CLOSE to CPU

21

97

Fri Dec 31 10:16:57 2010

EVEREST-M

Frank Hu

2

1

C4516

2

1

C4515

2

1

C4520

2

1

C4519

2

1

C4518

2

1

C4517

2

1

C4524

2

1

C4523

2

1

C4522

2

1

C4521

2

1

C4526

2

1

C4525

2

1

C4527

2

1

C4528

2

1

C4530

2

1

C4529

2

1

C4531

2

1

C4532

2

1

C4533

2

1

C4534

2

1

C4535

2

1

C4536

2

1

C4537

2

1

C4538

2

1

C4539

2

1

C4540

2

1

C4542

2

1

C4541

2

1

C4543

2

1

C4544

2

1

C4545

2

1

C4546

2

1

R4544

2

1

R4545

H28

J27

J29

K27

K30

L28

L31

M30

D25

E26

D27

F28

E28

G28

M33

M28

H29

J28

J30

K28

K31

L29

L32

M31

E25

F26

D28

F27

E29

G27

M32

M29

E35

F30

F33

G31

G34

H32

H35

K34

B32

C33

E31

D34

F32

E33

L35

J33

F35

G30

G33

H31

H34

J32

J35

L34

C32

B33

D31

D33

E32

E34

M35

K33

H22

J21

J22

H20

F17

D19

C19

B20

E17

D18

C20

B21

H17

J17

G18

E20

G19

A22

F18

E19

H19

A21

J19

J18

G15

C16

F16

C17

F15

D16

E16

C18

A17

B16

A18

D15

C15

C21

F20

D22

G22

D21

F21

E22

G21

B23

A24

B26

B28

B24

A25

B25

B27

CN4500

PEG_RX6_DN

PEG_RX5_DN

PEG_RX4_DN

68>

PEG_TX0_C_DN

PEG_TX1_C_DN

68>

PEG_TX2_C_DN

68>

0.1UF_6.3V_1

PEG_TX2_DN

PEG_TX3_DN

68<

PEG_TX4_DN

0.1UF_6.3V_1

PEG_TX7_DN

PEG_TX8_DN

PEG_TX9_DN

PEG_TX6_DN

PEG_TX5_DN

PEG_TX0_DN

0.1UF_6.3V_1

PEG_TX10_C_DP

PEG_TX9_C_DP

21<

PEG_TX10_C_DN

PEG_TX9_C_DN

PEG_TX1_C_DN

PEG_TX0_C_DN

PEG_TX15_C_DP

PEG_TX14_C_DP

PEG_TX13_C_DP

PEG_TX12_C_DP

PEG_TX11_C_DP

PEG_TX10_C_DP

PEG_TX9_C_DP

PEG_TX4_C_DP

PEG_TX5_C_DP

PEG_TX6_C_DP

PEG_TX7_C_DP

PEG_TX8_C_DP

PEG_TX2_C_DN

PEG_TX4_C_DN

PEG_TX6_C_DN

PEG_TX7_C_DN

PEG_TX11_C_DN

PEG_TX12_C_DN

PEG_TX13_C_DN

PEG_RX4_DP

PEG_RX5_DP

PEG_RX6_DP

PEG_RX7_DP

PEG_RX12_DP

PEG_RX13_DP

PEG_RX14_DP

PEG_RX15_DP

PEG_RX0_DN

PEG_RX1_DN

+V1.05S_VCCP_PEG_ICOMPI

FDI_TX_DN<5>

FDI_TX_DP<7..0>

FDI_TX_DN<7..0>

DMI_RX_DP<3..0>

DMI_RX_DN<3..0>

2

DMI_TX_DP<3..0>

3

0

1

DMI_TX_DP<2>

DMI_TX_DP<3>

DMI_TX_DP<0>

DMI_TX_DP<1>

DMI_TX_DN<3..0>

DMI_TX_DN<2>

DMI_TX_DN<3>

DMI_TX_DN<0>

PEG_RX9_DN

DMI_RX_DN<2>

DMI_RX_DN<0>

EDP_TX0_DN

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

PEG_TX0_C_DP

PEG_TX1_C_DP

PEG_TX2_C_DP

PEG_TX4_C_DP

PEG_TX7_C_DP

PEG_TX11_C_DP

PEG_TX14_C_DP

PEG_TX15_C_DP

PEG_RX0_DP

24.9_1%_2

P1V05_VCCPS

PEG_RX15_DN

21<

PEG_TX1_C_DP

PEG_TX0_C_DP

PEG_TX2_C_DP

PEG_TX3_C_DP

21<

PEG_TX3_C_DN

PEG_TX8_C_DN

PEG_TX14_C_DN

PEG_TX15_C_DN

PEG_TX5_C_DN

21<

68>

PEG_RX1_DP

PEG_RX2_DP

PEG_RX3_DP

PEG_RX9_DP

PEG_RX10_DP

PEG_RX11_DP

PEG_RX8_DP

68>

PEG_RX7_DN

PEG_RX8_DN

PEG_RX2_DN

PEG_RX3_DN

PEG_RX10_DN

PEG_RX12_DN

PEG_RX13_DN

PEG_RX11_DN

PEG_RX14_DN

68>

PEG_TX6_C_DP

PEG_TX8_C_DP

PEG_TX13_C_DP

PEG_TX14_C_DN

FDI_TX_DN<6>

FDI_TX_DN<4>

FDI_TX_DN<3>

FDI_TX_DN<2>

FDI_TX_DN<1>

FDI_TX_DN<0>

DMI_RX_DP<2>

DMI_RX_DP<1>

DMI_RX_DN<3>

DMI_TX_DN<1>

EDP_TX0_DP

48>

EDP_AUX_DN

EDP_AUX_DP

48>

48<>

EDP_HPD#

P1V05_VCCPS

48>

24.9_1%_2

+V1.05S_VCCP_eDP_COMPIO

CS_1310AXXXXXX-MTR

A01

C

CS

FDI_LSYNC1

FDI_LSYNC0

FDI_INT

FDI_FSYNC1

FDI_FSYNC0

FDI_TX_DP<7>

FDI_TX_DP<6>

FDI_TX_DP<5>

FDI_TX_DP<4>

FDI_TX_DP<3>

FDI_TX_DP<2>

FDI_TX_DP<1>

FDI_TX_DP<0>

FDI_TX_DN<7>

DMI_RX_DP<3>

DMI_RX_DP<0>

DMI_RX_DN<1>

3

2

PEG_TX3_C_DP

PEG_TX5_C_DP

0.1UF_6.3V_1

PEG_TX9_C_DN

PEG_TX10_C_DN

PEG_TX11_C_DN

PEG_TX12_C_DP

PEG_TX0_DP

PEG_TX2_DP

PEG_TX1_DP

PEG_TX3_DP

PEG_TX4_DP

PEG_TX6_DP

PEG_TX5_DP

PEG_TX7_DP

PEG_TX8_DP

PEG_TX10_DP

PEG_TX9_DP

PEG_TX11_DP

PEG_TX12_DP

PEG_TX3_C_DN

PEG_TX4_C_DN

PEG_TX5_C_DN

PEG_TX6_C_DN

PEG_TX7_C_DN

PEG_TX8_C_DN

PEG_TX13_DP

PEG_TX14_DP

PEG_TX15_DP

PEG_TX1_DN

PEG_TX12_C_DN

PEG_TX13_C_DN

PEG_TX15_C_DN

PEG_TX10_DN

PEG_TX11_DN

PEG_TX12_DN

PEG_TX13_DN

PEG_TX14_DN

PEG_TX15_DN

30>

7

6

5

4

3

2

1

0

7

6

5

4

1

0

3

2

1

0

3

2

1

0

30>

3

2

1

0

0.1UF_6.3V_1

68<

0.1UF_6.3V_1

68<

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

eDP

Intel(R) FDI

DMI

PCI EXPRESS* - GRAPHICS

eDP_ICOMPO

eDP_HDP#

eDP_COMPIO

eDP_TX#[3]

eDP_TX#[2]

eDP_TX#[1]

eDP_TX#[0]

eDP_TX[3]

eDP_TX[2]

eDP_TX[1]

eDP_TX[0]

eDP_AUX#

eDP_AUX

PEG_TX[15]

PEG_TX[14]

PEG_TX[13]

PEG_TX[12]

PEG_TX[11]

PEG_TX[10]

PEG_TX[9]

PEG_TX[8]

PEG_TX[7]

PEG_TX[6]

PEG_TX[5]

PEG_TX[4]

PEG_TX[3]

PEG_TX[2]

PEG_TX[1]

PEG_TX[0]

PEG_TX#[15]

PEG_TX#[14]

PEG_TX#[13]

PEG_TX#[12]

PEG_TX#[11]

PEG_TX#[10]

PEG_TX#[9]

PEG_TX#[8]

PEG_TX#[7]

PEG_TX#[6]

PEG_TX#[5]

PEG_TX#[4]

PEG_TX#[3]

PEG_TX#[2]

PEG_TX#[1]

PEG_TX#[0]

PEG_RX[15]

PEG_RX[14]

PEG_RX[13]

PEG_RX[12]

PEG_RX[11]

PEG_RX[10]

PEG_RX[9]

PEG_RX[8]

PEG_RX[7]

PEG_RX[6]

PEG_RX[5]

PEG_RX[4]

PEG_RX[3]

PEG_RX[2]

PEG_RX[1]

PEG_RX[0]

PEG_RX#[15]

PEG_RX#[14]

PEG_RX#[13]

PEG_RX#[12]

PEG_RX#[11]

PEG_RX#[10]

PEG_RX#[9]

PEG_RX#[8]

PEG_RX#[7]

PEG_RX#[6]

PEG_RX#[5]

PEG_RX#[4]

PEG_RX#[3]

PEG_RX#[2]

PEG_RX#[1]

PEG_RX#[0]

PEG_RCOMPO

PEG_ICOMPO

PEG_ICOMPI

FDI1_LSYNC

FDI0_LSYNC

FDI_INT

FDI1_FSYNC

FDI0_FSYNC

FDI1_TX[3]

FDI1_TX[2]

FDI1_TX[1]

FDI1_TX[0]

FDI0_TX[3]

FDI0_TX[2]

FDI0_TX[1]

FDI0_TX[0]

FDI1_TX#[3]

FDI1_TX#[2]

FDI1_TX#[1]

FDI1_TX#[0]

FDI0_TX#[3]

FDI0_TX#[2]

FDI0_TX#[1]

FDI0_TX#[0]

DMI_TX[2]

DMI_TX[3]

DMI_TX[1]

DMI_TX[0]

DMI_TX#[3]

DMI_TX#[2]

DMI_TX#[1]

DMI_TX#[0]

DMI_RX[3]

DMI_RX[2]

DMI_RX[1]

DMI_RX[0]

DMI_RX#[3]

DMI_RX#[2]

DMI_RX#[1]

DMI_RX#[0]

CPU 3 DRAM

Fri Dec 31 10:16:57 2010

97

22

Frank Hu

EVEREST-M

AB9

AB8

AD4

AE4

R4

R5

AB10

T1

R1

AB7

R3

T5

R2

T3

T4

T2

T6

R7

T7

AA8

AP15

AK12

AP9

AN5

N3

K6

F3

D7

AP14

AK11

AP8

AN6

M3

J6

G3

C7

AT15

AR15

AN15

AT12

AT14

AR14

AN14

AT11

AH12

AJ12

AR8

AH11

AT9

AT8

AJ11

AR9

AR5

AR6

AN8

AP6

AT6

AT5

AN9

AP5

AP2

AN1

AN2

AN3

AP3

AR3

AM6

AM5

M1

M2

N5

M4

N1

N2

N4

M5

K7

K8

J10

J9

K9

K10

J8

J7

G2

F2

F5

G5

G1

F1

F4

G4

D8

D9

A8

A9

C8

D10

A7

C9

AE3

AD3

AD1

AD2

AE1

AE2

R10

R9

AA10

R6

AA7

AA9

AE5

AD5

AE6

AD6

T10

AB1

AA1

T9

AA2

AB2

CN4500

AF9

AD9

AG3

AH3

V7

V5

AF8

W4

V4

AD8

W5

V1

W6

W3

V2

V3

W7

W2

W1

AD10

AM15

AR12

AM8

AL6

M6

J3

G6

C4

AM14

AR11

AM9

AL5

N6

K3

F6

D4

AH15

AJ15

AK14

AL14

AK15

AL15

AH14

AJ14

AN12

AP12

AL11

AM11

AM12

AL12

AN11

AP11

AL8

AL9

AH9

AH8

AK9

AJ9

AK8

AJ8

AJ6

AJ5

AH6

AH5

AK5

AK6

AG5

AG6

M7

N9

M9

M10

N7

N8

N10

M8

K2

J2

J4

J5

J1

K1

K5

K4

G7

G8

F7

F9

G9

G10

F8

F10

C3

C2

C6

D6

D2

D3

D5

C5

AL3

AK3

AB5

AA6

AA5

AB6

V10

V9

AE8

V6

AF10

AE10

AH2

AG2

AH1

AG1

W10

AA3

AB3

W9

AA4

AB4

CN4500

M_A_DQ<10>

M_A_DQ<9>

M_A_DQ<8>

M_A_DQ<7>

M_A_DQ<6>

M_A_DQ<5>

M_CLK_DDR1_DN

M_CKE1

M_B_DQ<36>

M_B_DQ<4>

M_B_DQ<5>

M_B_DQ<6>

M_B_DQ<20>

M_B_DQ<37>

M_B_DQ<38>

M_B_DQ<63>

63

62

1

M_A_A<2>

M_A_A<3>

M_A_DQ<11>

M_A_DQ<0>

22

M_B_DQ<30>

M_B_DQ<32>

M_B_DQ<34>

M_B_DQ<35>

M_B_DQ<39>

M_B_DQ<41>

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

M_B_DQS_DN<6>

M_B_DQS_DN<3>

M_B_DQS_DN<2>

M_B_DQS_DN<0>

M_B_DQS_DN<1>

M_B_DQS_DP<0>

M_B_A<4>

M_B_A<5>

6

27<

M_CS#0

M_CS#1

M_A_DQS_DN<7..0>

40

M_B_DQ<42>

M_B_DQ<43>

M_B_DQ<44>

M_B_DQ<47>

47

M_A_DQS_DP<7..0>

M_B_DQ<46>

M_B_DQ<48>

M_B_DQ<49>

M_B_DQ<0>

M_B_DQ<62>

M_B_DQ<61>

M_B_DQ<60>

M_B_DQ<59>

M_B_DQ<58>

M_B_DQ<57>

M_B_DQ<56>

M_B_DQ<55>

M_B_DQ<54>

M_B_DQ<53>

M_B_DQ<52>

M_B_DQ<51>

M_B_DQ<50>

M_B_DQ<45>

M_B_DQ<40>

M_B_DQ<33>

M_B_DQ<31>

M_B_DQ<29>

M_B_DQ<28>

M_B_DQ<27>

M_B_DQ<26>

M_B_DQ<25>

M_B_DQ<24>

M_B_DQ<23>

M_B_DQ<22>

M_B_DQ<21>

M_B_DQ<19>

M_B_DQ<18>

M_B_DQ<17>

M_B_DQ<16>

M_B_DQ<15>

M_B_DQ<14>

M_B_DQ<13>

M_B_DQ<12>

M_B_DQ<11>

M_B_DQ<10>

M_B_DQ<9>

M_B_DQ<8>

M_B_DQ<7>

M_B_DQ<3>

M_B_DQ<2>

M_B_DQ<1>

M_B_WE#

M_B_RAS#

M_B_CAS#

M_B_BS2

M_B_BS1

M_B_BS0

M_CS#3

M_CS#2

M_B_A<15>

M_B_A<14>

M_B_A<13>

M_B_A<12>

M_B_A<11>

M_B_A<10>

M_B_A<9>

M_B_A<8>

M_B_A<7>

M_B_A<6>

M_B_A<3>

M_B_A<2>

M_B_A<1>

M_B_A<0>

M_B_DQS_DP<3>

M_B_DQS_DP<2>

M_B_DQS_DP<1>

M_B_DQS_DN<7>

M_B_DQS_DP<7>

M_B_DQS_DP<6>

M_B_DQS_DN<5>

M_B_DQS_DP<5>

M_B_DQS_DN<4>

M_B_DQS_DP<4>

M_ODT3

M_ODT2

M_CKE3

M_CKE2

M_CLK_DDR3_DN

M_CLK_DDR2_DN

M_CLK_DDR3_DP

M_CLK_DDR2_DP

3

9

0

1

2

4

5

6

7

8

27<>

10

11

12

13

14

16

15

17

18

19

20

21

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

41

42

43

44

45

46

48

49

50

51

52

53

54

55

56

57

58

59

60

61

27<

M_B_DQ<63..0>

26<>

26<

M_CLK_DDR1_DP

M_ODT1

63

M_A_BS0

M_A_DQ<21>

M_A_DQ<22>

M_A_DQ<12>

12

14

M_A_DQ<15>

M_A_DQ<16>

M_A_DQ<17>

M_A_DQ<18>

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

M_A_DQ<63>

M_A_DQ<62>

M_A_DQ<61>

M_A_DQ<60>

M_A_DQ<59>

M_A_DQ<58>

M_A_DQ<57>

M_A_DQ<56>

M_A_DQ<55>

M_A_DQ<54>

M_A_DQ<53>

M_A_DQ<52>

M_A_DQ<51>

M_A_DQ<50>

M_A_DQ<49>

M_A_DQ<48>

M_A_DQ<47>

M_A_DQ<46>

M_A_DQ<45>

M_A_DQ<44>

M_A_DQ<43>

M_A_DQ<42>

M_A_DQ<41>

M_A_DQ<40>

M_A_DQ<39>

M_A_DQ<38>

M_A_DQ<37>

M_A_DQ<36>

M_A_DQ<35>

M_A_DQ<34>

M_A_DQ<33>

M_A_DQ<32>

M_A_DQ<31>

M_A_DQ<30>

M_A_DQ<29>

M_A_DQ<28>

M_A_DQ<27>

M_A_DQ<26>

M_A_DQ<25>

M_A_DQ<24>

M_A_DQ<23>

M_A_DQ<20>

M_A_DQ<19>

M_A_DQ<14>

M_A_DQ<13>

M_A_DQ<4>

M_A_DQ<3>

M_A_DQ<2>

M_A_DQ<1>

M_A_WE#

M_A_RAS#

M_A_CAS#

M_A_BS2

M_A_BS1

M_A_A<15>

M_A_A<14>

M_A_A<13>

M_A_A<12>

M_A_A<11>

M_A_A<10>

M_A_A<9>

M_A_A<8>

M_A_A<7>

M_A_A<6>

M_A_A<5>

M_A_A<4>

M_A_A<1>

M_A_A<0>

M_A_DQS_DN<7>

M_A_DQS_DP<7>

M_A_DQS_DN<6>

M_A_DQS_DP<6>

M_A_DQS_DN<5>

M_A_DQS_DP<5>

M_A_DQS_DN<4>

M_A_DQS_DP<4>

M_A_DQS_DN<3>

M_A_DQS_DP<3>

M_A_DQS_DN<2>

M_A_DQS_DP<2>

M_A_DQS_DN<1>

M_A_DQS_DP<1>

M_A_DQS_DN<0>

M_A_DQS_DP<0>

M_ODT0

M_CKE0

M_CLK_DDR0_DN

M_CLK_DDR0_DP

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

A01

M_A_A<15..0>

M_A_DQ<63..0>

M_B_A<15..0>

M_B_DQS_DP<7..0>

M_B_DQS_DN<7..0>

26<

62

26<

60

61

58

59

57

55

56

53

54

52

50

51

49

48

47

45

46

44

43

42

14

15

12

13

11

10

9

7

8

6

5

4

2

3

0

6

7

4

5

3

1

2

0

7

6

5

40

41

39

37

38

35

36

34

32

33

31

30

29

27

28

26

25

24

22

23

21

19

20

17

18

16

15

13

11

9

10

8

7

6

4

5

3

2

1

0

4

3

2

0

1

26<

14

15

12

13

11

10

9

7

8

5

4

2

3

1

0

6

7

4

5

3

27<>

1

2

0

7

6

5

4

3

2

0

1

27<

CS_1310AXXXXXX-MTR

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

OUT

BI

OUT

BI

DDR SYSTEM MEMORY B

SB_DQ[0]

SB_DQ[63]

RSVD_TP[20]

RSVD_TP[19]

RSVD_TP[18]

RSVD_TP[17]

SB_CS#[1]

SB_CS#[0]

RSVD_TP[16]

RSVD_TP[15]

RSVD_TP[14]

RSVD_TP[13]

RSVD_TP[12]

RSVD_TP[11]

SB_DQ[62]

SB_DQ[61]

SB_DQ[60]

SB_DQ[59]

SB_DQ[58]

SB_DQ[57]

SB_DQ[56]

SB_DQ[55]

SB_DQ[54]

SB_DQ[53]

SB_DQ[52]

SB_DQ[51]

SB_DQ[50]

SB_DQ[49]

SB_DQ[48]

SB_DQ[47]

SB_DQ[46]

SB_DQ[45]

SB_DQ[44]

SB_DQ[43]

SB_DQ[42]

SB_DQ[41]

SB_DQ[40]

SB_DQ[39]

SB_DQ[38]

SB_DQ[37]

SB_DQ[36]

SB_DQ[35]

SB_DQ[34]

SB_DQ[33]

SB_DQ[32]

SB_DQ[31]

SB_DQ[30]

SB_DQ[29]

SB_DQ[28]

SB_DQ[27]

SB_DQ[26]

SB_DQ[25]

SB_DQ[24]

SB_DQ[23]

SB_DQ[22]

SB_DQ[21]

SB_DQ[20]

SB_DQ[19]

SB_DQ[18]

SB_DQ[17]

SB_DQ[16]

SB_DQ[15]

SB_DQ[14]

SB_DQ[13]

SB_DQ[12]

SB_DQ[11]

SB_DQ[10]

SB_DQ[9]

SB_DQ[8]

SB_DQ[7]

SB_DQ[6]

SB_DQ[5]

SB_DQ[4]

SB_DQ[3]

SB_DQ[2]

SB_DQ[1]

SB_MA[15]

SB_MA[14]

SB_MA[13]

SB_MA[12]

SB_MA[11]

SB_MA[10]

SB_MA[9]

SB_MA[8]

SB_MA[7]

SB_MA[6]

SB_MA[5]

SB_MA[4]

SB_MA[3]

SB_MA[2]

SB_MA[1]

SB_MA[0]

SB_DQS#[3]

SB_DQS[3]

SB_DQS#[2]

SB_DQS[2]

SB_DQS#[1]

SB_DQS[1]

SB_DQS#[0]

SB_DQS[0]

SB_DQS#[7]

SB_DQS[7]

SB_DQS#[6]

SB_DQS[6]

SB_DQS#[5]

SB_DQS[5]

SB_DQS#[4]

SB_DQS[4]

SB_ODT[1]

SB_ODT[0]

SB_CKE[1]

SB_CKE[0]

SB_CLK#[1]

SB_CLK#[0]

SB_CLK[1]

SB_CLK[0]

SB_WE#

SB_RAS#

SB_CAS#

SB_BS[2]

SB_BS[1]

SB_BS[0]

BI

OUT

BI

OUT

DDR SYSTEM MEMORY A

RSVD_TP[10]

RSVD_TP[9]

RSVD_TP[8]

RSVD_TP[7]

RSVD_TP[6]

RSVD_TP[3]

RSVD_TP[5]

RSVD_TP[4]

RSVD_TP[2]

RSVD_TP[1]

SA_DQ[63]

SA_DQ[62]

SA_DQ[61]

SA_DQ[60]

SA_DQ[59]

SA_DQ[58]

SA_DQ[57]

SA_DQ[56]

SA_DQ[55]

SA_DQ[54]

SA_DQ[53]

SA_DQ[52]

SA_DQ[51]

SA_DQ[50]

SA_DQ[49]

SA_DQ[48]

SA_DQ[47]

SA_DQ[46]

SA_DQ[45]

SA_DQ[44]

SA_DQ[43]

SA_DQ[42]

SA_DQ[41]

SA_DQ[40]

SA_DQ[39]

SA_DQ[38]

SA_DQ[37]

SA_DQ[36]

SA_DQ[35]

SA_DQ[34]

SA_DQ[33]

SA_DQ[32]

SA_DQ[31]

SA_DQ[30]

SA_DQ[29]

SA_DQ[28]

SA_DQ[27]

SA_DQ[26]

SA_DQ[25]

SA_DQ[24]

SA_DQ[23]

SA_DQ[22]

SA_DQ[21]

SA_DQ[20]

SA_DQ[19]

SA_DQ[18]

SA_DQ[17]

SA_DQ[16]

SA_DQ[15]

SA_DQ[14]

SA_DQ[13]

SA_DQ[12]

SA_DQ[11]

SA_DQ[10]

SA_DQ[9]

SA_DQ[8]

SA_DQ[7]

SA_DQ[6]

SA_DQ[5]

SA_DQ[4]

SA_DQ[3]

SA_DQ[2]

SA_DQ[1]

SA_DQ[0]

SA_MA[15]

SA_MA[14]

SA_MA[13]

SA_MA[12]

SA_MA[11]

SA_MA[10]

SA_MA[9]

SA_MA[8]

SA_MA[7]

SA_MA[6]

SA_MA[5]

SA_MA[4]

SA_MA[3]

SA_MA[2]

SA_MA[1]

SA_MA[0]

SA_DQS#[7]

SA_DQS[7]

SA_DQS#[6]

SA_DQS[6]

SA_DQS#[5]

SA_DQS[5]

SA_DQS#[4]

SA_DQS[4]

SA_DQS#[3]

SA_DQS[3]

SA_DQS#[2]

SA_DQS[2]

SA_DQS#[1]

SA_DQS[1]

SA_DQS#[0]

SA_DQS[0]

SA_ODT[1]

SA_ODT[0]

SA_CS#[1]

SA_CS#[0]

SA_CKE[1]

SA_CKE[0]

SA_CLK#[1]

SA_CLK#[0]

SA_CLK[1]

SA_CLK[0]

SA_WE#

SA_RAS#

SA_CAS#

SA_BS[2]

SA_BS[1]

SA_BS[0]

20mil

CPU 4 POWER

CLOSE TO POWER IC

WS

EVEREST-M

Frank Hu

23

97

Fri Dec 31 10:16:58 2010

2

1

R4501

2

1

R4502

2

1

C4563

2

1

C4560

2

1

C4562

2

1

C4561

2

1

C4566

2

1

C4564

2

1

C4565

2

1

R4503

2

1

R4504

2

1

R4526

2

1

R4527

2

1

R4546

2

1

R4547

2

1

R4548

2

1

R4525

2

1

R4550

2

1

R4549

2

1

R4551

2

1

R4528

3

2

1

C4569

2

1

C4599

2

1

C4596

2

1

C4598

2

1

C4597

2

1

C4557

2

1

C4503

2

1

C4558

2

1

C4576

2

1

C4575

2

1

C4574

2

1

C4573

2

1

C4572

2

1

C4571

2

1

C4588

2

1

C4589

2

1

C4590

2

1

C4591

2

1

C4592

2

1

C4593

2

1

C4577

2

1

C4578

2

1

C4581

2

1

C4582

2

1

C4583

2

1

C4584

2

1

C4585

2

1

C4586

2

1

C4587

2

1

C4594

2

1

C4580

2

1

C4579

A10

AJ34

AJ28

AJ30

AJ29

B10

J14

L10

P10

U10

Y10

J23

AC10

A11

A12

A13

A14

B12

B14

C11

C12

C13

C14

AG10

D11

D12

D13

D14

E11

E12

E14

F11

F12

F13

AH10

F14

G12

G13

G14

H11

H12

H14

J11

J12

J13

AH13

AJ35

P27

P28

P29

P30

P31

P32

P33

P34

P35

R26

AG27

R27

R28

R29

R30

R31

R32

R33

R34

R35

U26

AG28

U27

U28

U29

U30

U31

U32

U33

U34

U35

V26

AG29

V27

V28

V29

V30

V31

V32

V33

V34

V35

Y26

AG30

Y27

Y28

Y29

Y30

Y31

Y32

Y33

Y34

Y35

AA26

AG31

AA27

AA28

AA29

AA30

AA31

AA32

AA33

AA34

AA35

AC26

AG32

AC27

AC28

AC29

AC30

AC31

AC32

AC33

AC34

AC35

AD26

AG33

AD27

AD28

AD29

AD30

AD31

AD32

AD33

AD34

AD35

AF26

AG34

AF27

AF28

AF29

AF30

AF31

AF32

AF33

AF34

AF35

P26

AG26

AG35

CN4500

+V1.05S_VCCP_VCCIO40

54.9_1%_2

43_1%_2

PVCORE

0_5%_2

P1V05_VCCPS

10_1%_2

VCC_SENSE_VTT

10_1%_2

VSS_SENSE_VTT

100_1%_2

VSSSENSE

VCCSENSE

75_1%_2

0_5%_2

22uF_6.3V_5 22uF_6.3V_5

10uF_6.3V_3 10uF_6.3V_3

22uF_6.3V_5

H_CPU_SVIDALRT#

P1V05_VCCPS

PVCORE

22uF_6.3V_5

470UF_2V

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

VCCSENSE_R

VSSSENSE_R

0_5%_2

100_1%_2

14<

H_CPU_SVIDCLK

VR_SVID_DATA

VR_SVID_CLK

VR_SVID_ALRT#

H_CPU_SVIDDAT

130_1%_2

0_5%_2

P1V05_VCCPS

130_1%_2

14<>

14<

P1V05_VCCPS

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

10uF_6.3V_310uF_6.3V_3

10uF_6.3V_3

22uF_6.3V_5

A01

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

22uF_6.3V_5 22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5 22uF_6.3V_5

10uF_6.3V_3

10uF_6.3V_3 10uF_6.3V_3

C

CS_1310AXXXXXX-MTR

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

+

SVID

SENSE LINES

PEG AND DDR

CORE SUPPLY

POWER

VCCIO40

VCCIO_SENSE

VCCIO31

VCCIO30

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO25

VCCIO17

VCCIO16

VCCIO15

VCCIO14

VCCIO13

VCCIO11

VCCIO10

VCCIO9

VCCIO8

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO24

VCCIO23

VCCIO22

VCCIO21

VCCIO20

VCCIO19

VCCIO18

VCCIO12

VCCIO1

VCC100

VCC99

VCC98

VCC97

VCC96

VCC95

VCC94

VCC93

VCC92

VCC91

VCC90

VCC89

VCC88

VCC87

VCC86

VCC85

VCC84

VCC83

VCC82

VCC81

VCC80

VCC79

VCC78

VCC77

VCC76

VCC75

VCC74

VCC73

VCC72

VCC71

VCC70

VCC69

VCC68

VCC67

VCC66

VCC65

VCC64

VCC63

VCC62

VCC61

VCC60

VCC59

VCC58

VCC57

VCC56

VCC55

VCC54

VCC53

VCC52

VCC51

VCC50

VCC49

VCC48

VCC47

VCC46

VCC45

VCC44

VCC43

VCC42

VCC41

VCC40

VCC39

VCC38

VCC37

VCC36

VCC35

VCC34

VCC33

VCC32

VCC31

VCC30

VCC29

VCC28

VCC27

VCC26

VCC25

VCC24

VCC23

VCC22

VCC21

VCC20

VCC19

VCC18

VCC17

VCC16

VCC15

VCC14

VCC13

VCC12

VCC11

VCC10

VCC9

VCC8

VCC7

VCC6

VCC5

VCC4

VCC3

VCC2

VCC1

VSS_SENSE_VCCIO

VIDSOUT

VIDSCLK

VIDALERT#

VSS_SENSE

VCC_SENSE

WS

SNB HIGH

IVB HIGH

WS

20/20 mil

6A

IVB LOW

0.675V

20/20 mil

CPU 5 POWER

1.1A

20/20 mil

0.90V

[[ CPU PIN# C22

xxVccSA_Select[0]

VID1 of VR ]]

0

1

VID0 of VR ]]

[[ CPU PIN# C24

xxVccSA_Select[1]

1

0

SNB LOW

Function

0.725V

VCCSA VR Vout

1

0.80V

WS

24

97

EVEREST-M

Frank Hu

Mon Jan 03 17:28:06 2011

10uF_6.3V_3

VCCSA_SENSE

2

1

R4559

2

1

C4605

2

1

C4604

2

1

C4603

2

1

C4602

2

1

C4601

2

1

C4600

2

1

C4568

2

1

C4567

4

36

5

2

1

Q4501

2

1

R4523

2

1

C4595

2

1

R4524

2

1

R4543

2

1

C4502

2

1

C4501

2

1

C4500

2

1

C4553

2

1

C4552

2

1

C4551

2

1

C4555

2

1

C4556

2

1

C4554

2

1

L4500

2

1

C4547

2

1

C4549

2

1

C4548

2

1

C4550

32

1

C4505

32

1

C4506

2

1

C4507

2

1

C4508

2

1

C4510

2

1

C4509

2

1

C4511

2

1

C4512

2

1

C4513

2

1

C4514

AK34

Y1

Y4

Y7

AC1

AC4

AC7

AF1

AF4

P1

P4

P7

U1

U4

U7

AF7

C24

C22

H23

H25

H26

J24

J25

J26

L26

M26

M27

A2

A6

B6

A19

AK35

AR21

AR23

AR24

AT17

AH17

AH18

AH20

AH21

AH23

AT18

AH24

AJ17

AJ18

AJ20

AJ21

AJ23

AJ24

AK17

AK18

AK20

AT20

AK21

AK23

AK24

AL17

AL18

AL20

AL21

AL23

AL24

AM17

AT21

AM18

AM20

AM21

AM23

AM24

AN17

AN18

AN20

AN21

AN23

AT23

AN24

AP17

AP18

AP20

AP21

AP23

AP24

AR17

AR18

AR20

AT24

AL1

D1

B4

CN4500

22uF_6.3V_5

10uF_6.3V_3

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

0_5%_2_DY

VCCSA_SEL

CPU_CHB_VREFDQ

CPU_CHA_VREFDQ

470UF_2V

22uF_6.3V_5_DY

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

22uF_6.3V_5_DY

14<

VSSAXG_SENSE

0_5%_2

10uF_6.3V_3

13<

22uF_6.3V_5

P0V75_VREF_M

22uF_6.3V_522uF_6.3V_5 22uF_6.3V_522uF_6.3V_5

22uF_6.3V_5

P0V75_VREF_M_H

470pF_50V_2

AO6402AL

PVAXG

C

A01

CS

CS_1310AXXXXXX-MTR

SLP_S3#_15R

VAXG_SENSE

10uF_6.3V_3

220UF_2.5V

10uF_6.3V_3

1uF_6.3V_2 1uF_6.3V_2

22uF_6.3V_5

10K_5%_2

P0V85_S

10uF_6.3V_3 10uF_6.3V_3

P1V5_CPUDDRS

100K_5%_2

P0V75_VREF_M_H

10uF_6.3V_3

22uF_6.3V_5

470UF_2V

P1V8_S

FBM_11_160808_181A15T

22uF_6.3V_5

VCCPLL

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

+

D

G

S

NMOS_4D1S

IN

OUT

+

MISC VREFSA RAIL

1.8V RAIL

LINES

SENSE

DDR3 -1.5V RAILS

GRAPHICS

POWER

VCCIO_SEL

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

VCCSA_VID[0]

VCCPLL3

VCCSA_VID[1]

VCCSA_SENSE

VCCSA8

VCCSA7

VCCSA6

VCCSA5

VCCSA4

VCCSA3

VCCSA2

VCCSA1

VCCPLL2

VCCPLL1

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

VDDQ1

VDDQ15

VDDQ14

VDDQ13

VDDQ12

VDDQ11

VAXG54

VAXG53

VAXG52

VAXG51

VAXG50

VAXG49

VAXG48

VAXG47

VAXG46

VAXG45

VAXG44

VAXG43

VAXG42

VAXG41

VAXG40

VAXG39

VAXG38

VAXG37

VAXG36

VAXG35

VAXG34

VAXG33

VAXG32

VAXG31

VAXG30

VAXG29

VAXG28

VAXG27

VAXG26

VAXG25

VAXG24

VAXG23

VAXG22

VAXG21

VAXG20

VAXG19

VAXG18

VAXG17

VAXG16

VAXG15

VAXG14

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VAXG3

VAXG2

VAXG1

VAXG_SENSE

VSSAXG_SENSE

SM_VREF

PEG Defer Training

PCIE Port Bifurcation

LOW eDP ENABLE

STRAP PIN

CPU 6 GND

PEG Static Lan Reversal

0: eDP Enabled

LOW eDP ENABLE

PEG Defer Training

CFG(4)

PCIE Port Bifurcation Straps

00: x8, x4, x4 - Device 1 function 1 and 2 enabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled

11: (Default) x16 - Device 1 function 1 and 2 disabled

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

CFG(7)

CFG(2)

1: (Default) Normal operation

PEG Static Lane Reversal

0: Lane Reversed

1: (Default) eDP Disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

CFG[6:5]

EVEREST-M

Frank Hu

97

25

Fri Dec 31 10:16:59 2010

2

1

R4518

2

1

R4519

2

1

R4520

2

1

R4521

2

1

R4522

AH31

AH33

AH26

AJ33

AH27

AJ31

B35

A34

A33

B34

AR34

AP35

AT33

AT34

AR1

AT1

AT2

C35

AR35

F24

F25

AM35

AK32

AJ32

AJ26

G16

H16

J16

T8

AJ27

AM33

AT26

W8

AK2

AE7

AG7

L7

J15

B18

J20

C29

A30

B31

D30

B29

B30

A31

C30

D23

E23

G24

G25

D24

F23

B1

AM30

AM32

AM31

AL30

AL29

AK26

AL27

AL26

AN29

AK31

AM27

AN26

AN31

AN28

AM26

AM28

AK29

AK28

AN35

CN4500

A3

A20

A23

A26

A29

A32

A35

B2

B3

B5

B7

B8

B9

B11

B13

B15

B17

B19

B22

C1

C10

C23

C25

C27

C28

C31

C34

D17

D20

D26

D29

D32

D35

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E13

E15

E18

E21

E24

E27

E30

F19

F22

F29

F31

F34

G11

G17

G20

G23

G26

G29

G32

G35

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H13

H15

H18

H21

H24

H27

H30

H33

J31

J34

K26

K29

K32

K35

L1

L2

L3

L4

L5

L6

L8

L9

L27

L30

L33

M34

N26

N27

N28

N29

N30

N31

N32

N33

N34

N35

P2

P3

P5

P6

P8

P9

T26

T27

T28

T29

T30

T31

T32

T33

T34

T35

CN4500

AH22

AH25

AH28

AH29

AH30

AH32

AH34

AH35

AJ1

AT13

AJ2

AJ3

AJ4

AJ7

AJ10

AJ13

AJ16

AJ19

AJ22

AJ25

AT16

AK4

AK7

AK10

AK13

AK16

AK19

AK22

AK25

AK27

AK30

AT19

AK33

AL2

AL4

AL7

AL10

AL13

AL16

AL19

AL22

AL25

AT22

AL28

AL31

AL34

AM1

AM2

AM3

AM4

AM7

AM10

AM13

AT25

AM16

AM19

AM22

AM25

AM29

AN4

AN7

AN10

AN13

AN16

AT27

AN19

AN22

AN25

AN27

AN30

AP1

AP4

AP7

AP10

AP13

AT29

AP16

AP19

AP22

AP25

AP28

AP31

AP34

AR2

AR4

AR7

AT32

AR10

AR13

AR16

U2

AR19

U3

U5

U6

U8

U9

W26

W27

W28

W29

W30

AR22

W31

W32

W33

W34

W35

Y2

Y3

Y5

Y6

Y8

AR25

Y9

AB26

AB27

AB28

AB29

AB30

AB31

AB32

AB33

AB34

AT3

AB35

AC2

AC3

AC5

AC6

AC8

AC9

AD7

AE9

AE26

AT4

AE27

AE28

AE29

AE30

AE31

AE32

AE33

AE34

AE35

AF2

AT7

AF3

AF5

AF6

AG4

AG8

AG9

AH4

AH7

AH16

AH19

AT10

AT35

CN4500

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

CFG<16>

CFG<15>

CFG<13>

CFG<12>

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

CFG<5>

CFG<6>

25<

60<

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

CFG<4>

CFG<5>

CFG<2>

CS_1310AXXXXXX-MTR

CS A01

C

CFG<17>

CFG<0>

CFG<14>

CFG<11>

CFG<10>

CFG<9>

CFG<8>

CFG<7>

CFG<4>

CFG<3>

CFG<2>

CFG<1>

CLK_XDP_CLKGEN_DN

CLK_XDP_CLKGEN_DP

25<

60<

25<

60<

25<

60<

1K_1%_2_DY

1K_1%_2

1K_1%_2_DY

25>60<

CFG<7>

CFG<6>

60<

25<

60<

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

RESERVED

VSS_DIE_SENSE

VCC_DIE_SENSE

BCLK_ITP#

BCLK_ITP

KEY

VSS_VAL_SENSE

VCC_VAL_SENSE

VSSAXG_VAL_SENSE

VAXG_VAL_SENSE

RSVD5

RSVD10

RSVD_NCTF4

RSVD25

RSVD33

RSVD32

RSVD14

RSVD13

RSVD12

RSVD11

RSVD9

RSVD8

RSVD37

RSVD24

RSVD23

RSVD21

RSVD22

RSVD19

RSVD20

RSVD18

RSVD17

RSVD15

RSVD16

RSVD27

RSVD29

RSVD28

RSVD31

RSVD30

RSVD52

RSVD51

RSVD_NCTF10

RSVD_NCTF9

RSVD_NCTF8

RSVD_NCTF7

RSVD_NCTF6

RSVD_NCTF13

RSVD_NCTF12

RSVD_NCTF11

RSVD_NCTF5

RSVD_NCTF3

RSVD_NCTF1

RSVD40

RSVD39

RSVD_NCTF2

RSVD38

RSVD35

RSVD34

CFG[17]

CFG[16]

CFG[15]

CFG[14]

CFG[13]

CFG[12]

CFG[11]

CFG[10]

CFG[9]

CFG[8]

CFG[7]

CFG[6]

CFG[5]

CFG[4]

CFG[3]

CFG[2]

CFG[1]

CFG[0]

VSS

VSS285

VSS284

VSS283

VSS282

VSS281

VSS280

VSS279

VSS278

VSS277

VSS276

VSS275

VSS274

VSS273

VSS272

VSS271

VSS270

VSS269

VSS268

VSS267

VSS266

VSS265

VSS264

VSS263

VSS262

VSS261

VSS260

VSS259

VSS258

VSS257

VSS256

VSS255

VSS254

VSS253

VSS252

VSS251

VSS250

VSS249

VSS248

VSS247

VSS246

VSS245

VSS244

VSS243

VSS242

VSS241

VSS240

VSS239

VSS238

VSS237

VSS236

VSS235

VSS234

VSS233

VSS232

VSS231

VSS230

VSS229

VSS228

VSS227

VSS226

VSS225

VSS224

VSS223

VSS222

VSS221

VSS220

VSS219

VSS218

VSS217

VSS216

VSS215

VSS214

VSS213

VSS212

VSS211

VSS210

VSS209

VSS208

VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS130

VSS129

VSS128

VSS127

VSS126

VSS125

VSS124

VSS123

VSS122

VSS121

VSS120

VSS119

VSS118

VSS117

VSS116

VSS115

VSS114

VSS113

VSS112

VSS111

VSS110

VSS109

VSS108

VSS107

VSS106

VSS105

VSS104

VSS103

VSS102

VSS101

VSS100

VSS99

VSS98

VSS96

VSS95

VSS94

VSS93

VSS92

VSS91

VSS90

VSS89

VSS88

VSS87

VSS86

VSS85

VSS84

VSS83

VSS82

VSS81

VSS80

VSS79

VSS78

VSS77

VSS76

VSS75

VSS74

VSS73

VSS72

VSS71

VSS70

VSS69

VSS68

VSS67

VSS66

VSS65

VSS64

VSS63

VSS62

VSS61

VSS60

VSS59

VSS58

VSS57

VSS56

VSS55

VSS54

VSS53

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

DDR3 DIMM0

NOTE:

1.5A

NOTE:PLACE C4100

ON COMMON PATH

THESE CAPS NEAR

LAYOUT NOTE: PLACE

SO-DIMM0 POWER PIN

IF SA0_DIM0=1 , SA1_DIM0=0

SO-DIMMA SPD ADDRESS IS 0XA2

SO-DIMMA TS ADDRESS IS 0X32

SO-DIMMA TS ADDRESS IS 0X30

SO-DIMMA SPD ADDRESS IS 0XA0

IF SA0_DIM0=0 , SA1_DIM0=0

FOR BOTH DIMM'S

VTT2

CHA

20/20 MIL

CLOSE TO VTT1 AND

PLACE THESE CAPS

WS

REMOVE 1UF CAP 1PCS

Fri Dec 31 10:17:00 2010

EVEREST-M

Frank Hu

97

26

2

1

R4127

2

1

R4126

2

1

R4101

2

1

R4100

2

1

R4125

2

1

R4102

2

1

C4110

2

1

C4100

2

1

C4109

2

1

C4128

2

1

C4120

2

1

C4121

2

1

C4119

2

1

C4126

2

1

C4127

2

1

C4122

2

1

C4125

2

1

C4124

2

1

C4123

2

1

C4137

2

1

C4136

2

1

C4135

2

1

C4140

2

1

C4139

2

1

C4138

204

203

25

20

19

14

196

195

190

13

189

185

184

179

178

173

172

168

167

162

9

161

156

155

151

150

145

144

139

138

134

8

133

128

127

72

71

66

65

61

60

55

3

54

49

48

44

43

38

37

32

31

26

2

1

126

199

99

94

93

88

87

82

81

76

124

123

118

117

112

111

106

105

100

75

30

125

122

77

G2

G1

198

CN4101

113

200

202

201

197

121

114

110

120

116

188

171

154

137

64

47

29

12

186

169

152

135

62

45

27

10

23

21

18

194

192

182

180

16

193

191

183

181

176

174

166

164

177

175

6

165

163

160

158

148

146

159

157

149

147

4

142

140

132

130

143

141

131

129

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

187

170

153

136

63

46

28

11

74

73

104

102

103

101

115

79

108

109

85

89

86

90

91

92

95

96

78

80

119

83

84

107

97

98

CN4101

M_A_DQS_DN<7..0>

M_A_DQS_DP<7..0>

M_A_DQ<38>

1UF_6.3V_2

BELLW_80001_6021_204P

M_A_DQ<2>

M_A_A<11>

M_A_A<4>

M_A_DQ<10>

P3V3_S

DIMM0_VREF_DQ

0.1UF_16V_2

1UF_6.3V_2

SA1_DIM0

P3V3_S

BELLW_80001_6021_204P

M_A_A<13>

M_A_A<12>

M_A_A<0>

0

M_A_A<6>

8

6

M_A_A<7>

M_A_DQ<24>

M_A_DQ<26>

32

M_A_DQ<31>

M_A_DQ<29>

M_A_DQ<25>

M_A_DQ<27>

M_A_DQ<8>

M_A_DQ<6>

M_A_DQ<19>

16

17

22<>

M_A_DQ<63..0>

P3V3_S

DIMM0_VREF_CA

DDR3_DRAMRST#

PM_EXTTS#1_R

M_A_DQ<4>

M_A_DQ<3>

M_A_A<15..0>

10K_5%_2 10K_5%_2

10K_5%_2_DY

26>

10K_5%_2_DY

SA0_DIM0

10K_5%_2

0_5%_2

26>27>

PM_EXTTS#1

PM_EXTTS#1_R

1UF_6.3V_2

10UF_6.3V_3

10UF_6.3V_310UF_6.3V_3

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

18>

26< 27>

P0V75_S

1UF_6.3V_21UF_6.3V_2

P1V5

CS

CS_1310AXXXXXX-MTR

A01

C

22>

0

1

2

4

3

5

6

7

8

9

10

11

12

14

15

13

20

18

19

22>

1

2

3

4

5

7

9

10

11

12

13

14

15

22>

21

22

23

24

25

26

27

28

30

29

33

31

35

34

38

36

37

40

39

43

41

42

44

45

46

47

48

49

50

51

52

53

55

54

56

57

58

60

59

61

63

62

22>

60< 27<

59<> 29<>

22>

0

1

2

22<>

3

4

5

6

7

0

1

2

3

4

5

22<>

26<

6

7

M_CS#1

M_A_DQ<0>

M_A_DQ<1>

M_A_DQ<5>

M_A_DQ<7>

M_A_DQ<9>

M_A_DQ<11>

M_A_DQ<12>

M_A_DQ<14>

M_A_DQ<15>

M_A_DQ<13>

M_A_DQ<16>

M_A_DQ<17>

M_A_DQ<20>

M_A_DQ<18>

M_A_A<1>

M_A_A<2>

M_A_A<3>

M_A_A<5>

M_A_A<8>

M_A_A<9>

M_A_A<10>

M_A_A<14>

M_A_A<15>

M_A_BS2

M_A_BS1

M_A_BS0

M_A_DQ<21>

M_A_DQ<22>

M_A_DQ<23>

M_A_DQ<28>

M_A_DQ<30>

M_A_DQ<33>

M_A_DQ<32>

M_A_DQ<35>

M_A_DQ<34>

M_A_DQ<36>

M_A_DQ<37>

M_A_DQ<40>

M_A_DQ<43>

M_A_DQ<41>

M_A_DQ<42>

M_A_DQ<44>

M_A_DQ<45>

M_A_DQ<46>

M_A_DQ<48>

M_A_DQ<49>

M_A_DQ<50>

M_A_DQ<51>

M_A_DQ<52>

M_A_DQ<53>

M_A_DQ<55>

M_A_DQ<54>

M_A_DQ<56>

M_A_DQ<57>

M_A_DQ<58>

M_A_DQ<60>

M_A_DQ<59>

M_A_DQ<61>

M_A_DQ<63>

M_A_DQ<62>

M_CS#0

M_CLK_DDR1_DP

M_CLK_DDR0_DN

M_CLK_DDR0_DP

M_CLK_DDR1_DN

M_CKE0

M_A_WE#

M_A_RAS#

M_A_CAS#

M_CKE1

PCH_3S_SMCLK

PCH_3S_SMDATA

M_ODT0

M_ODT1

M_A_DQS_DP<0>

M_A_DQS_DP<1>

M_A_DQS_DP<2>

M_A_DQS_DP<3>

M_A_DQS_DP<4>

M_A_DQS_DP<5>

M_A_DQS_DP<6>

M_A_DQS_DP<7>

M_A_DQS_DN<0>

M_A_DQS_DN<1>

M_A_DQS_DN<2>

M_A_DQS_DN<3>

M_A_DQS_DN<4>

M_A_DQS_DN<5>

SA0_DIM0

SA1_DIM0

M_A_DQS_DN<6>

M_A_DQS_DN<7>

M_A_DQ<47>

27>

2.2UF_6.3V_2

0.1UF_16V_2

2.2UF_6.3V_2 0.1UF_16V_2

M_A_DQ<39>

22>

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

BI

OUT

BI

G2

G1

VTT2

VTT1

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VREF_CA

VREF_DQ

RESET#

EVENT#

NCTEST

NC2

NC1

VDDSPD

VDD18

VDD17

VDD16

VDD15

VDD14

VDD13

VDD12

VDD11

VDD10

VDD9

VDD8

VDD7

VDD6

VDD5

VDD4

VDD3

VDD2

VDD1

IN

OUT

IN

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

DQS#7

DQS#6

DQS#5

DQS#4

DQS#3

DQS#2

DQS#1

DQS#0

DQS7

DQS6

DQS5

DQS4

DQS3

DQS2

DQS1

DQS0

DM7

DM6

DM5

DM4

DM3

DM2

DM1

DM0

ODT1

ODT0

SDA

SCL

SA1

SA0

WE#

RAS#

CAS#

CKE1

CKE0

CK1#

CK1

CK0#

CK0

S1#

S0#

BA2

BA1

BA0

A15

A14

A13

A12

A11

A10_AP

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

20/20 MIL

PLACE THESE CAPS

DDR3 DIMM1

SO-DIMM0 POWER PIN

PLACE THESE CAPS

CLOSE TO VTT1 AND

VTT2

1.5A

20/20 MIL

CHB

VTT2

CLOSE TO VTT1 AND

WS

NOTE:

LAYOUT NOTE: PLACE

THESE CAPS NEAR

SO-DIMMB TS ADDRESS IS 0X34

REMOVE CPU_CHB_VREFDQ

SO-DIMMB SPD ADDRESS IS 0XA4

20/20 MIL

WS

Fri Dec 31 10:16:30 2010

27

97

EVEREST-M

Frank Hu

2

1

R4139

2

1

R4138

2

1

R4137

2

1

R4136

2

1

R4144

2

1

R4143

2

1

R4142

2

1

R4141

2

1

C4142

2

1

R4140

2

1

C4141

2

1

R4135

2

1

R4134

2

1

R4133

2

1

R4132

2

1

R4131

2

1

R4130

2

1

R4129

2

1

R4128

4

36

5

2

1

Q4101

4

3 6

5

2

1

Q4100

2

1

R4122

2

1

R4117

2

1

R4118

2

1

C4118

2

1

R4110

2

1

R4111

2

1

R4121

2

1

C4103

2

1

R4112

2

1

R4105

204

203

25

20

19

14

196

195

190

13

189

185

184

179

178

173

172

168

167

162

9

161

156

155

151

150

145

144

139

138

134

8

133

128

127

72

71

66

65

61

60

55

3

54

49

48

44

43

38

37

32

31

26

2

1

126

199

99

94

93

88

87

82

81

76

124

123

118

117

112

111

106

105

100

75

30

125

122

77

G2

G1

198

CN4100

113

200

202

201

197

121

114

110

120

116

188

171

154

137

64

47

29

12

186

169

152

135

62

45

27

10

23

21

18

194

192

182

180

16

193

191

183

181

176

174

166

164

177

175

6

165

163

160

158

148

146

159

157

149

147

4

142

140

132

130

143

141

131

129

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

187

170

153

136

63

46

28

11

74

73

104

102

103

101

115

79

108

109

85

89

86

90

91

92

95

96

78

80

119

83

84

107

97

98

CN4100

2

1

R4119

2

1

R4120

2

1

R4115

2

1

R4116

2

1

R4114

2

1

R4123

2

1

R4124

2

1

R4103

2

1

R4104

2

1

C4101

2

1

C4102

2

1

C4107

2

1

C4132

2

1

C4133

2

1

C4134

2

1

C4129

2

1

C4130

2

1

C4131

2

1

C4108

2

1

C4106

2

1

C4105

2

1

C4113

2

1

C4114

2

1

C4115

2

1

C4117

2

1

C4112

2

1

C4116

2

1

C4104

SA0_DIM1

27>

P3V3_S

M_B_DQ<2>

M_B_DQ<1>

M_B_A<3>

M_B_DQ<17>

33

M_B_DQ<33>

M_B_DQ<34>

M_B_DQ<24>

M_B_DQ<27>

M_B_BS2

M_B_A<6>

DIMM0_VREF_CA

1UF_6.3V_2

17

M_B_DQ<16>

M_B_DQ<18>

M_B_DQ<19>

20

19

18

M_B_DQ<20>

M_B_DQ<21>

M_B_DQ<22>

M_B_DQ<23>

22

21

26

DIMM1_VREF_DQ

0.1UF_16V_22.2UF_6.3V_2

PM_EXTTS#1_R

DDR3_DRAMRST#

M_B_DQ<10>

M_B_DQ<11>

M_B_DQ<12>

M_B_DQ<13>

M_B_DQ<14>

M_B_DQ<15>

10UF_6.3V_3

P3V3_S

DIMM1_VREF_CA

0_5%_2

0.1UF_16V_2

M_B_DQ<59>

1K_5%_2_DY

DRAMRST_CNTRL_CPU

0_5%_20_5%_2

1K_5%_2_DY

AO6402AL

0_5%_2_DY

1K_1%_2

P1V5

0_5%_2_DY

DIMM1_VREF_DQ

0_5%_2_DY

DIMM0_VREF_DQ

P1V5

P1V5_CPUDDRS

CPU_CHB_VREFDQ

1K_5%_2_DY

0_5%_2_DY

0_5%_2

AO6402AL

CPU_CHA_VREFDQ

1K_1%_2

1K_5%_2_DY

62

M_B_DQ<63>

M_B_DQS_DN<1>

DRAMRST_CNTRL_CPU

P1V5

0.1UF_16V_2

P1V5

0_5%_2

0.1UF_16V_2_DY

0_5%_2_DY

C

M_B_DQS_DP<7>

M_B_DQ<56>

P0V75_VREF_M

1K_5%_2_DY

0.1UF_16V_2

0_5%_2_DY

0_5%_2

1K_1%_2

10K_5%_2_DY

0_5%_2

0_5%_2_DY

M_B_DQ<62>

PCH_3S_SMDATA

SA0_DIM1

SA1_DIM1

63

61

60

59

58

57

56

55

54

53

52

51

M_B_DQ<50>

M_B_DQ<61>

M_B_DQ<60>

M_B_DQ<58>

M_B_DQ<57>

M_B_DQ<55>

M_B_DQ<53>

M_B_DQ<52>

M_B_DQ<51>

50

M_B_DQ<49>

49

M_B_DQS_DN<7>

M_B_DQS_DN<6>

M_B_DQS_DN<0>

M_B_DQ<38>

M_B_DQ<36>

M_B_DQ<43>

CS_1310AXXXXXX-MTR

M_B_DQS_DN<5>

M_B_DQS_DN<4>

M_B_DQS_DN<3>

M_B_DQS_DN<2>

M_B_DQ<48>

M_B_DQ<47>

M_B_DQ<46>

M_B_DQ<45>

M_B_DQ<42>

M_B_DQ<41>

M_B_DQ<40>

M_B_DQ<39>

M_B_DQ<37>

M_B_DQ<35>

M_B_DQ<32>

M_B_DQ<31>

M_B_DQ<30>

M_B_DQ<29>

M_B_DQ<28>

M_B_DQ<26>

M_B_DQ<25>

M_B_DQ<9>

M_B_DQ<8>

M_B_DQ<7>

M_B_DQ<6>

M_B_DQ<5>

M_B_DQ<4>

M_B_DQ<3>

M_B_DQ<0>

M_B_DQS_DP<6>

M_B_DQS_DP<5>

M_B_DQS_DP<4>

M_B_DQS_DP<3>

M_B_DQS_DP<2>

M_ODT3

M_ODT2

PCH_3S_SMCLK

M_B_WE#

M_B_RAS#

M_B_CAS#

M_CKE3

M_CKE2

M_CLK_DDR3_DN

M_CLK_DDR3_DP

M_CLK_DDR2_DN

M_CLK_DDR2_DP

M_CS#3

M_CS#2

M_B_BS1

M_B_BS0

M_B_A<15>

M_B_A<14>

M_B_A<13>

M_B_A<12>

M_B_A<11>

M_B_A<10>

M_B_A<9>

M_B_A<8>

M_B_A<7>

M_B_A<5>

M_B_A<4>

M_B_A<2>

M_B_A<1>

M_B_A<0>

M_B_DQS_DN<7..0>

M_B_A<15..0>

M_B_DQ<63..0>

7

6

5

4

3

2

1

22<>

27<

0

7

6

5

4

3

2

1

0

22>

29<>

60<

59<>

22>

48

47

45

46

44

43

42

40

41

39

38

37

35

36

34

32

30

29

31

28

27

25

24

23

16

22>

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

11

12

10

9

7

6

8

4

5

2

1

3

0

22<>

1UF_6.3V_2

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

BELLW_80001_2021_204P

P0V75_S

1UF_6.3V_2

P1V5

1UF_6.3V_2

10UF_6.3V_3

10UF_6.3V_3 10UF_6.3V_3

10UF_6.3V_3

A01

CS

0.1UF_16V_2

M_B_DQ<44>

27>

10K_5%_2

SA1_DIM1

10K_5%_2_DY

1K_5%_2_DY

M_B_DQS_DP<0>

M_B_DQS_DP<7..0>

M_B_DQS_DP<1>

M_B_DQ<54>

0.1UF_16V_2

2.2UF_6.3V_2

DIMM1_VREF_CA

BELLW_80001_2021_204P

22<>

26<

1K_1%_2

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

OUT

IN

BI

IN

D

G

S

NMOS_4D1S

D

G

S

NMOS_4D1S

IN

G2

G1

VTT2

VTT1

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VREF_CA

VREF_DQ

RESET#

EVENT#

NCTEST

NC2

NC1

VDDSPD

VDD18

VDD17

VDD16

VDD15

VDD14

VDD13

VDD12

VDD11

VDD10

VDD9

VDD8

VDD7

VDD6

VDD5

VDD4

VDD3

VDD2

VDD1

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

DQS#7

DQS#6

DQS#5

DQS#4

DQS#3

DQS#2

DQS#1

DQS#0

DQS7

DQS6

DQS5

DQS4

DQS3

DQS2

DQS1

DQS0

DM7

DM6

DM5

DM4

DM3

DM2

DM1

DM0

ODT1

ODT0

SDA

SCL

SA1

SA0

WE#

RAS#

CAS#

CKE1

CKE0

CK1#

CK1

CK0#

CK0

S1#

S0#

BA2

BA1

BA0

A15

A14

A13

A12

A11

A10_AP

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

IN

OUT

BI

HDA_3S_SDOUT_R HIGH:ENABLE

WS

LOW:DISABLE

FLASH DESCRIPTOR SECURITY OVERIDE

WS

Disable - (Default)Internal pull-down

1.05V VRM Enable

high- Enable Internal VRs

STRAP

Enable - pull-up

Flash Override

low-Enable External VRs

INTVRMEN-

SATA SSD

CLOSED TO EC

L- (Default) VCC VRM=1.8V

1: No Reboot enabled

H-VCC VRM=1.5V

No Reboot

Placememt note

PCH 1

CLOSED TO PCH

RTC BATTERY

0: (Default) No Reboot disabled

WS

STRAP

STRAP PIN

LOW - Internal

WS

cap on the "P" signal should be

Distance between the PCH and

identical distance between the

PCH and cap on the "N" signal

for same pair

HIGH - ENABLE ANTITHEFT

STRAP PIN

SATA HDD

SATA ODD

eSATA

WS

mSATA

Sun Jan 02 19:22:09 2011

EVEREST-M

Frank Hu

28

97

AD3

SATA_mSATA_TX_DN

SATA_mSATA_TX_DP

SATA_mSATA_RX_DP

SATA_mSATA_RX_DN

SATA_ESATA_TX_DP

SATA_ESATA_TX_DN

SATA_ESATA_RX_DP

SATA_ESATA_RX_DN

+V1.05S_SATAICOMPO

Y11

PCH_TDI

PCH_TDO

PCH_SPI_CLK

HDA_3S_SDOUT_R

FLASH_OVERRIDE

R4773

1

60>

PCH_TCK

PCH_SPI_CS0#

PCH_SPI_SO

PCH_SPI_SI

28>

PCH_TMS

AF3

AB8

AH4

SATA_ODD_TX_DP

Y5

Y3

HDA_3S_SDOUT

0_5%_3

60> 28>

PCH_TDI

PCH_TMS

PCH_TDO

LPC_3S_AD<0>

37<>

55<

37<>

55<

210_1%_2

61>

60<>

61>

60>

60<>

28>

60>

60<>

28>

61<

1

210_1%_2

1

R4703

100_1%_2

SATA_SSD_TX_DP

AM2321P_DY

CN4701

+V3M_SPI

1K_5%_2

HDA_3S_SDOUT

28>

60<>

51_5%_2

61>

3

P3V3_A

28<>

1

TP4713

dgnd

SSM3K7002FU

P5V_S

HDA_3S_RST#_R

HDA_3S_SYNC_R

SATA_ODD_RX_DP

R4757

37.4_1%_2

HDA_3S_SDOUT_R

61>

10K_5%_2_DY

28<>

3.3K_5%_2

28<>

P3V3_AL

0.1UF_16V_2

28<>

33_5%_2

37>

37<

28<>

0_5%_2_DY 0_5%_2_DY

37<

60>

28<>

1uF_6.3V_2

20K_1%_2

+V_RTC

20K_1%_2

1uF_6.3V_2 10M_5%_2

+V_RTC

18pF_50V_2

28>

58<

+V1.05S

43<

37<>

43<

55<43<

43< 55<

55<

+V1.05S

RSC_0402_DY

P3V3_A

100_1%_2 100_1%_2

210_1%_2

PCH_SPI_CS0#

PCH_SPI_SO

EC_SPI_SO PCH_SPI_SO

1.2K_1%_3

330K_5%_3

750_1%_2

R4758

1

2

R4706

1

2

R4708

2

R4704

1

2

R4702

1

2

R4705

2

1

2

1

2

R4890

1

2

1

2

1

2

1

2

R4850

1

R4800

1

2

R4804

1

22

2

1

2

1

2

R4797

1

2

R4772

1

2

C4766

1

2

1

2

1

2

R4762

1

2

R4760

1

2

1

2

C4762

1

2

R4761

2

1

2

R4756

1

2

R4812

1

2

1

2

3

1

2

1

2

R4778

1

2

1

2

R4766

1

2

1

2

R4764

1

2

1

7

6

5

2

4

3

1

2 3

4

6

1

5

2

4

7

8

3

WINB_W25Q64BVSSIG_SOIC_8P

R4701

2

PCH_XDPFN11

SATA_ODD_TX_DN

SATA_ODD_RX_DN

SATA_HDD_TX_DP

SATA_HDD_TX_DN

SATA_HDD_RX_DP

SATA_SSD_TX_DN

SATA_SSD_RX_DP

SATA_SSD_RX_DN

LPC_3S_FRAME#

LPC_3S_AD<3>

LPC_3S_AD<2>

LPC_3S_AD<1>

RTCX2

+V_RTC_RTCRST#

+V_RTC_SRTCRST#

PCH_XDPFN10

LED_3S_SATA#

A20

C20

D20

G22

K34

E34

G34

N32

J3

H7

K5

H1

T3

T1

V4

Y14

V14

P3

AH1

AB13

AB12

Y10

AB1

AB3

Y1

AD1

Y7

AF1

AB10

AH5

AD5

AD7

AP10

AP11

AM8

AM10

AP5

AP7

AM1

AM3

V5

K36

E36

C37

B37

C38

2

33_1%_2

+V_RTC_INTRUDER#

K22

C17

N34

L34

U4703

1

C4763

R4759

2

C4761

2

33_1%_2

1

T10

SIG442

2

R4769

HDA_3S_SYNC

PCSPKR_PCH_3

CS A01

C

CS_1310AXXXXXX-MTR

RTCX1

10K_5%_2

PCI_3S_SERIRQ

37<>

+V1.05S_SATA3RCOMPO

2

R4755

PCH_SPI_MOSI_R

2

28>

R4823

0_5%_2_DY

R4891

1

SATA_HDD_RX_DN

2

R4813

3

P5V_S

R4754

1

C36

1

A34

C34

R4768

1

2

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

60>

R4801

R4786

1

2

+V3M_SPI

+V3M

18pF_50V_2

C4765

X4701

32.768KHZ

U4700

1

R4767

2

ITL_PANTHERPOINT_FCBGA_989P

1uF_6.3V_2

150_1%_3

R4777

D4704

BAT54_30V_0.2A

+V_RTC

2

33_5%_2

0_5%_2

1

R4765

2

1

P3V3_S

+V1.05S

P3V3_S

R4771

10K_5%_2

P1

U3

33_5%_2

10K_5%_2

R4852

49.9_1%_2

43<

D36

PCH_SPI_CLK

28<>

PCH_SPI_SI

37>

33_5%_2_DY 0_5%_2_DY

RSC_0402_DY

2

C4764

EC_SPI_SI

1

R4798 R4802

33_5%_2_DY

1K_5%_2_DY

PCH_XDPFN10

A36

12pF_50V_2

1

2

1

2

PCH_SPI_SI

1

Q4703

1

2

1K_5%_2_DY

A38

1

2

1

R4707

0_5%_2

+V3M_SPI

ACES_91960_0084L_8P

EC_SMI

P3V3_S

R4783

10K_5%_2_DY

PCH_SPI_SO

PCH_SPI_CS0#

61<

60<>

1

2

Q4705

2

1

60<>

0_5%_2

1

R4893

37>

Q4704

33_1%_2

C4779

R4785

HDA_3S_SYNC_R

1

3

1M_5%_2

MAXELL_ML1220_T10_2P

P3V3_S

0_5%_2_DY

HDA_3S_BITCLK_R

33_1%_2

R4770

R4782

2

R4851

SSM3K7002FU

HDA_3S_SDIN0

HDA_3S_RST#

HDA_3S_BITCLK

28<>

PCH_SPI_CS1#

28<>

8

2

1K_5%_2_DY

R4892

28<>

PCH_SPI_CLK

PCH_SPI_SI

+V3M_SPI

PCH_XDPFN11

0_5%_2_DY

1

R4799

EC_SPI_CS0#

3.3K_5%_2

PCH_SPI_CLK

PCH_SPI_SI

U4702

10K_5%_2

28<>

37>

EC_SPI_CLK

33_5%_2_DY

R4803

R4763

1

PCH_SPI_CS1#

PCH_SPI_CS0#

0_5%_2_DY

37<

P3V3_A

SIZE

CHANGE by

DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI IN

OUT

BIIN

BI

IN

OUT

BI

OUT

BI

OUT

BI

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

G

DS

G

S D

BI

OUT

G

DS

OUT

DIO_ID0

CLK

/HOLD_IO3

VCC

GND

/WP_IO2

DO_IO1

/CS

BI

IN

OUT

BI

OUT

SI

SCK

HOLD#

VDD

VSS

WP#

SO

CE#

BI

IN

BI

OUT

-

+

OUT

NC

BI

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

SATA 6G

JTAG

SPI

LPC

SATA

IHDA RTC

SATA3RBIAS

SATA3RCOMPO

SATA3COMPI

SATAICOMPO

SPKR

SERIRQ

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

SATA1GP/GPIO19

SATA0GP/GPIO21

SPI_MISO

SPI_MOSI

SPI_CS1#

SPI_CS0#

SPI_CLK

SATAICOMPI

SATA5TXP

SATA5TXN

SATA5RXP

SATA5RXN

SATA4TXP

SATA4TXN

SATA4RXP

SATA4RXN

SATA3TXP

SATA3TXN

SATA3RXP

SATA3RXN

SATA2TXP

SATA2TXN

SATA2RXP

SATA2RXN

SATA1TXP

SATA1TXN

SATA1RXP

SATA1RXN

SATA0TXP

SATA0TXN

SATA0RXP

SATA0RXN

SRTCRST#

HDA_DOCK_RST#/GPIO13

HDA_DOCK_EN#/GPIO33

HDA_SDIN3

RTCRST#

LDRQ0#

FWH4/LFRAME#

LDRQ1#/GPIO23

FWH3/LAD3

FWH2/LAD2

FWH1/LAD1

FWH0/LAD0

SATALED#

HDA_SDO

HDA_SDIN2

HDA_SDIN1

HDA_SDIN0

HDA_RST#

HDA_SYNC

HDA_BCLK

INTRUDER#

INTVRMEN

RTCX2

RTCX1

CLOSE TO PCH

PCH 2

USB3.0

WS

REMOVE CLK_XDP_CLKGEN_DP

REMOVE CLK_XDP_CLKGEN_DN

LAN

WS

WLAN

3G

WS

CARD READER

STUFF FOR INTEGRATED CLK

Frank Hu

97

29

EVEREST-M

Sun Jan 02 15:32:31 2011

2

10K_5%_2

P3V3_A

P3V3_S

2

R4894

PCIE_LAN_RX_DN

PCIE_LAN_RX_DP

PCIE_LAN_TX_DN

PCIE_LAN_TX_DP

CLK_PCIE_WLAN_DP

CLK_PCIE_WLAN_DN

AA47

AA48

AB49

10K_5%_2

TP4711

PCIE_CR_TX_DP

0.1UF_16V_2

PCIE_CR_TX_C_DP

2

1

PCIE_WLAN_RX_DN

PCIE_WLAN_RX_DP

PCIE_CR_TX_DN

PCIE_CR_RX_DP

PCIE_CR_RX_DN

PCIE_USB3_TX_DP

PCIE_USB3_TX_DN

PCIE_USB3_RX_DP

PCIE_USB3_RX_DN

CLKREQ_USB3#

R4895

2

R4748

CLKREQ_LAN#

1

10K_5%_2_DY

CLKREQ_WLAN#

10K_5%_2_DY

R4730

1

2

10K_5%_2

R4731

1

2

10K_5%_2

1

10K_5%_2

CLKREQ_CR#

1

CLKREQ_CR#

CLKREQ_USB3#

CLK_PCIE_CR_DP

CLK_PCIE_CR_DN

P3V3_S

P3V3_A

CLK_PCIE_3G_DP

CLK_PCIE_3G_DN

CLKREQ_WLAN#

CLK_PCIE_USB3_DP

CLK_PCIE_USB3_DN

R4740

P3V3_A

10K_5%_2

PCIE_3G_TX_DP

1

R4889

R4859

CLK_XDP_DN

P5V_S

CLK_PCIE_LAN_DN

CLK_PCIE_LAN_DP

CLKREQ_LAN#

ITL_PANTHERPOINT_FCBGA_989P

CLKOUT_ITPXDP_DN

CLK_XDP_DP

A01

C

CS_1310AXXXXXX-MTR

CS

10K_5%_2

R4793

CLKIN_SATA1_DN

CLKIN_PCH14

CLKIN_SATA1_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_DMI_PCH_DP

CLKIN_DMI_PCH_DN

10K_5%_2

R4787

1

2

10K_5%_2

1

2

R4792

R4788

1

2

10K_5%_2

R4794

1

2

10K_5%_2

1

2

R4796

1

R4795

1

2

TP4703

TP4704

CLKREQ_3G#

Y37

Y36

PCIE_3G_TX_DN

PCIE_3G_RX_DP

PCIE_3G_RX_DN

PCIE_WLAN_TX_DP

PCIE_WLAN_TX_DN

Y45

C4760

A8

1

2

BC38

BE38

AY40

BJ40

BG40

BG38

BJ38

AY36

BH37

BB34

AY34

BE36

BF36

AU34

AV34

BJ36

BG36

AY32

BB32

BF34

BE34

PCIE_CR_TX_C_DN

P3V3_A

10K_5%_2

2.2K_5%_2

29>

39<>

P3V3_A

2.2K_5%_2

SSM3K7002BFU

29>

39<>

29>

37<>

29>

37<>

29>

1M_5%_2

29>

18pF_50V_2

25MHz

18pF_50V_2

10K_5%_2

+V1.05S

10K_5%_2

29<>

39<>

29<

39<>

29<

29<>

55>

20<

59> 29<

29<59>

29>

10K_5%_2

0_5%_2

60<

P3V3_A

2.2K_5%_2

27<

60<

26<

59<>

SSM3K7002BFU

55<>

29<>

SML1ALERT#

SML0_CLK

SML0_DATA

SML1_CLK

EC_SMB3_CLK

SML1_DATA

EC_SMB3_DATA

XTAL25_OUT

XTAL25_IN

CLKIN_BUF_CPYCLK_DN

CLKIN_BUF_CPYCLK_DP

PCH_3S_SMCLK

PCH_3A_SMCLK

PCH_3A_SMDATA

PCH_3S_SMDATA

22_5%_2

67<

CLK_GPU_27M

90.9_1%_2

55<>

10K_5%_2

R4753

2

R4854

1

2

R4855

1

2

R4747

1

2

R4700

1

2

X4700

1

2

C4777

1

2

C4776

1

2

R4849

1

2

R4752

1

2

R4741

1

2

R4751

1

2

R4750

1

2

R4749

1

2

Q4701

3

1

2

Q4700

3

1

2

TP4705

1

R4814

1

2

R4774

1

2

R4816

1

2

R4815

1

2

1

2

R4858

1

2

Q4703

3

1

2

Q4702

3

1

2

R4745

1

2

R4744

1

2

R4743

1

2

R4742

1

2

U4700

CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_SATA1_DN

CLKIN_SATA1_DP

XTAL25_IN

XTAL25_OUT

CLKIN_PCH14

CLKIN_PCI_FB

CLK_PEG_GPU_REF_DN

CLK_PEG_GPU_REF_DP

CLKREQ_GPU_PEG#

DGPU_PRSNT#

CLK_DMI_PCH_DN

CLK_DMI_PCH_DP

CLK_DP_PCH_CPU_DP

CLK_DP_PCH_CPU_DN

CLK_PCIE_LAN_R_DP

PCH_3A_SMCLK

PCH_3A_SMDATA

DRAMRST_CNTRL_PCH

SML0_CLK

SML0_DATA

SML1ALERT#

SML1_CLK

SML1_DATA

CL_CLK

CL_DATA

CL_RST#

TP4712

CLK_PCIE_LAN_R_DN

CLKOUT_ITPXDP_DP

BG37

BB36

BB40

Y43

V45

L12

L14

V46

E6

TP4706

1

AK13

AK14

K12

V37

V38

T13

V42

V40

1

AB40

AB42

11

V10

M1

AB47

J2

1

Y39

Y40

AY38

AW38

AV36

10K_5%_2

1

CLK_GPU_27M_SS_R

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

M10

AB38

AU22

AB37

AV22

AM12

AM13

BF18

BE18

BJ30

G24

AK7

E24

AK5

K45

V49

V47

H45

Y47

K43

F47

K49

H47

T11

P10

BG30

2

1

C4781

2

1

PCIE_LAN_TX_C_DN

1

2

0.1UF_16V_2

C4759

2

1

C4780

AV32

AU32

BJ34

0.1UF_16V_2

PCIE_USB3_TX_C_DP

PCIE_USB3_TX_C_DN

BG34

0.1UF_16V_2

C4757

C4758

1

2

C4783

C4782

0.1UF_16V_2

PCIE_LAN_TX_C_DP

0.1UF_16V_2

AU36

1

C4785

C4784

PCIE_3G_TX_C_DP

PCIE_3G_TX_C_DN

2

PCIE_WLAN_TX_C_DP

PCIE_WLAN_TX_C_DN

0.1UF_16V_2

2

1

2

0.1UF_16V_2

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

OUT

IN

OUT

IN

BI

G

DS

BI

IN

G

DS

IN

BI

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

G

DS

G

DS

IN

OUT

IN

OUT

IN

OUT

IN

OUT

Link

Controller

SMBUS

FLEX CLOCKS

CLOCKS

PCI-E*

PCIECLKRQ6#/GPIO45

CL_RST1#

CL_DATA1

CL_CLK1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT#/PCHHOT#/GPIO74

SML0DATA

SML0CLK

SML0ALERT#/GPIO60

SMBDATA

SMBCLK

SMBALERT#/GPIO11

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

PCIECLKRQ7#/GPIO46

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_DP_N

CLKOUT_DP_P

XCLK_RCOMP

CLKOUT_PEG_B_N

CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

PCIECLKRQ5#/GPIO44

PCIECLKRQ4#/GPIO26

PCIECLKRQ3#/GPIO25

PCIECLKRQ2#/GPIO20

PCIECLKRQ1#/GPIO18

PCIECLKRQ0#/GPIO73

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKIN_PCILOOPBACK

REFCLK14IN

XTAL25_OUT

XTAL25_IN

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

CLKIN_GND1_P

CLKIN_GND1_N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

PETP8

PETN8

PETP7

PETN7

PETP6

PETN6

PETP5

PETN5

PETP4

PETN4

PETP3

PETN3

PETP2

PETN2

PETP1

PETN1

PERP8

PERN8

PERP7

PERN7

PERP6

PERN6

PERP5

PERN5

PERP4

PERN4

PERP3

PERN3

PERP2

PERN2

PERP1

PERN1

STRAP PIN

PCH 3

ISOLATION

low-Disabled

DSWVRMEN - Deep S4/S5 Well On-Die Voltage Regulator Enable

high-Enabled(Default)

CLOSE TO IC

EC

CLOSE TO IC

Frank Hu

EVEREST-M

Sun Jan 02 18:04:44 2011

97

30

SUS_PWR_ACK

L10

0.1UF_10V_2_DY

PM_DRAM_PWRGD

B13

0.1UF_10V_2_DY

C4768

2

1

RSMRST#_R

SUS_PWR_ACK_R

30<

55<>

PCIE_WAKE#

R4775

2

R4735

ITL_PANTHERPOINT_FCBGA_989P

P12

1

10K_5%_2

ALLSYS_PWROK

EC_PCH_PWROK

R4886

1

PM_APWROK

SUSACK#_EC

49.9_1%_2

10K_5%_2

P3V3_A

K14

AP14

0_5%_2

R4883

BJ14

AY14

BE14

BH13

BC12

BJ12

BG10

BG9

BG14

BB14

BF14

BG13

BE12

BH9

BJ10

BG12

AW16

AV12

BC10

AV14

BB10

B9

E22

A18

N3

G8

N14

D10

H4

F4

G10

G16

E10

A10

H20

E20

K16

C21

L22

K3

C12

BH21

BG25

BJ24

AV18

AY24

AU18

AY18

AY20

BB18

AW20

AW24

BE24

BC20

BJ18

BJ20

BG20

BG18

BE20

BC24

2

SUSACK#_R

SLP_A#

SLP_LAN#

PCI_3S_CLKRUN#

ACPRESENT

FM_32KHZ

SUS_STAT#

PCIE_WAKE#

PM_RI#

SLP_S5#

SLP_S4#

SLP_S3#

SLP_SUS#

H_PM_SYNC

FDI_INT

FDI_LSYNC1

FDI_LSYNC0

FDI_FSYNC1

FDI_FSYNC0

FDI_TX_DP<7>

FDI_TX_DP<6>

FDI_TX_DP<5>

FDI_TX_DP<4>

FDI_TX_DP<3>

FDI_TX_DP<2>

FDI_TX_DP<1>

FDI_TX_DP<0>

FDI_TX_DN<7>

FDI_TX_DN<6>

FDI_TX_DN<5>

FDI_TX_DN<4>

FDI_TX_DN<3>

FDI_TX_DN<2>

FDI_TX_DN<1>

FDI_TX_DN<0>

DMI_TX_DP<3>

DMI_TX_DP<2>

DMI_TX_DP<1>

DMI_TX_DP<0>

DMI_TX_DN<3>

DMI_TX_DN<2>

DMI_TX_DN<1>

DMI_TX_DN<0>

DMI_RX_DP<3>

DMI_RX_DP<2>

DMI_RX_DP<1>

DMI_RX_DP<0>

DMI_RX_DN<3>

DMI_RX_DN<2>

DMI_RX_DN<1>

DMI_RX_DN<0>

U4700

750_1%_2

0_5%_2_DY

2

1

C4767

2

C4778

2

1

C4769

2

1

R4824

2

1

R4847

2

1

R4733

2

1

R4736

2

1

2

1

R4776

2

1

R4732

2

1

3

D4703

2

1

3

D4702

2

1

R4738

2

1

R4846

2

1

R4848

2

1

R4734

2

1

R4887

2

1

R4888

2

1

R4739

2

1

R4884

2

1

R4885

2

1

43<

0.1UF_10V_2_DY

21>

0.1UF_10V_2_DY

37>

P3V3_A

10K_5%_2

0_5%_2

37<

10K_5%_2_DY

P3V3_S

10K_5%_2

XDP_PWRSW#

LOW_BAT#_3

EC_PWRSW#

SUS_PWR_ACK_R

SYS_RESET#

SUSACK#_R

PCI_3S_CLKRUN#

SLP_LAN#

RSMRST#

PM_RI#

ACPRESENT

SUS_PWR_ACK

RSMRST#_R

P3V3_A

60>

37>

BAT54_30V_0.2A

8.2K_5%_2

BAT54_30V_0.2A

60>

20>

0_5%_2

P3V3_S

+V1.05S

19< 12<

30>37<

30<

18>

30<

0_5%_2

30<

30<37<

8.2K_5%_2

10K_5%_2

20<>

19<12<

37<30>

37<

18<

37<

19<

37<

17<11< 18<

37<

11<

37>

37<

21<

21>

30<

37<>

30<

55<>

21<

21>

330K_5%_2_DY

330K_5%_2

+V_RTC

CS_1310AXXXXXX-MTR

A01

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

NC

IN

NC

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

OUT

IN

OUT

System Power Management

FDI

DMI

SUSACK#

DSWVRMEN

SLP_A#

DMI2RBIAS

DPWROK

APWROK

SLP_LAN#/GPIO29

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

CLKRUN#/GPIO32

PWROK

BATLOW#/GPIO72

ACPRESENT/GPIO31

SUSCLK/GPIO62

SUS_STAT#/GPIO61

WAKE#

RI#

PWRBTN#

SYS_PWROK

SYS_RESET#

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_SUS#

PMSYNCH

FDI_INT

FDI_LSYNC1

FDI_LSYNC0

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

FDI_RXN0

DMI_IRCOMP

DMI_ZCOMP

DMI3TXP

DMI2TXP

DMI1TXP

DMI0TXP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

DMI3RXN

DMI2RXN

DMI1RXN

DMI0RXN

PCH_DUAL_DDCDATA - DP DETECTED

PCH_LVDS_DDCDATA - LVDS DETECT

HIGH-LVDS ENABLED

LOW-LVDS DISABLED (DEFAULT)

CLOSE TO PCH

PCH 4 AXG

LOW-DP DISABLED (DEFAULT)

HIGH-DP ENABLED

EVEREST-M

Frank Hu

Sat Jan 01 18:30:03 2011

97

31

R4882

PCH_CRT_BLUE

PCH_CRT_GREEN

PCH_CRT_RED

R4791

BA48

BB47

BB49

M43

M36

BB45

BF44

BF42

AT45

BH41

M45

PCH_LCM_INVPWM_R

AE48

AH43

AF37

AK39

AH49

AF43

N48

T39

M40

P49

M47

T42

T49

M49

T43

AV42

AV40

AV45

AV46

AU48

AU47

AV47

AV49

AT49

AT47

AT40

AY47

AY49

AY43

AY45

BA47

AP47

AP49

P46

P42

AT38

BB43

BE44

BE42

BJ42

BG42

AT43

P45

J47

T45

P39

T40

K47

AF36

AE47

AK40

AN48

AM47

AK47

AJ48

AN47

AM49

AK49

AJ47

AF39

AF40

AH45

AH47

AF49

AF45

AF47

P38

M39

AP39

AP40

AM42

AM40

AP43

AP45

U4700

ITL_PANTHERPOINT_FCBGA_989P

PCH_DP_HPD

PCH_DP_AUX_DP

PCH_DP_AUX_DN

PCH_DUAL_DDCDATA

PCH_DUAL_DDCCLK

PCH_CRT_VSYNC

PCH_CRT_HSYNC

PCH_CRT_DDCDATA

PCH_CRT_DDCCLK

PCH_DP_LANE3_DP

PCH_DP_LANE2_DP

PCH_DP_LANE0_DP

PCH_DP_LANE1_DP

PCH_DP_LANE3_DN

PCH_DP_LANE2_DN

PCH_DP_LANE1_DN

PCH_DP_LANE0_DN

PCH_LVDS_TXDL2_DP

PCH_LVDS_TXDL1_DP

PCH_LVDS_TXDL0_DP

PCH_LVDS_TXDL2_DN

PCH_LVDS_TXDL1_DN

PCH_LVDS_TXDL0_DN

PCH_LVDS_TXCL_DP

PCH_LVDS_TXCL_DN

PCH_LVDS_DDCDATA

PCH_LVDS_DDCCLK

2

1

R4729

2

1

R4789

2

1

R4790

2

1

2

1

2

1

R4843

2

1

R4842

2

1

R4841

2

1

R4845

2

1

R4844

PCH_LCM_BKLTEN

PCH_LCM_VDDEN

48<

45<

1K_1%_2

A01

PCH_LCM_INVPWM

47<>

47>

47<

100K_5%_2100K_5%_2

0_5%_2

67<

2.37K_1%_2

67<

48<

48<67<

67<

45<

150_1%_2

P3V3_S

2.2K_5%_22.2K_5%_2

CS_1310AXXXXXX-MTR

CS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

BI

OUT

CRT

Digital Display Interface

LVDS

SDVO_INTN

SDVO_INTP

SDVO_STALLN

SDVO_STALLP

SDVO_TVCLKINN

SDVO_TVCLKINP

DDPD_HPD

DDPC_HPD

DDPB_HPD

DDPD_AUXP

DDPC_AUXP

DDPB_AUXP

DDPD_AUXN

DDPC_AUXN

DDPB_AUXN

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_CTRLDATA

DDPC_CTRLCLK

SDVO_CTRLDATA

SDVO_CTRLCLK

DAC_IREF

CRT_VSYNC

CRT_RED

CRT_IRTN

CRT_HSYNC

CRT_GREEN

CRT_DDC_DATA

CRT_DDC_CLK

CRT_BLUE

DDPD_1P

DDPD_0P

DDPC_3P

DDPC_2P

DDPC_0P

DDPC_1P

LVD_VBG

LVD_IBG

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

DDPB_3P

DDPB_2P

DDPD_3P

DDPD_2P

DDPB_1P

DDPB_0P

DDPD_1N

DDPD_0N

DDPC_3N

DDPC_2N

DDPC_1N

DDPC_0N

DDPB_3N

DDPB_2N

DDPD_3N

DDPD_2N

LVD_VREFL

LVD_VREFH

DDPB_1N

DDPB_0N

LVDSB_DATA0

LVDSB_DATA#3

LVDSB_DATA#2

LVDSB_DATA#1

LVDSB_DATA#0

LVDSB_CLK

LVDSB_CLK#

LVDSA_DATA3

LVDSA_DATA2

LVDSA_DATA1

LVDSA_DATA0

LVDSA_DATA#3

LVDSA_DATA#2

LVDSA_DATA#1

LVDSA_DATA#0

LVDSA_CLK

LVDSA_CLK#

L_VDD_EN

L_DDC_DATA

L_DDC_CLK

L_CTRL_DATA

L_CTRL_CLK

L_BKLTEN

L_BKLTCTL

STP_A16OVR

PCH 5 USB

LOW=A16 SWAP OVERRIDE

HIGH=DEFAULT

TOP-BLOCK SWAP OVERRIDE

BBS_BIT1

1

0

1

0

11

00

GPIO51

GPIO19

BBS_BIT0

-

SPI (DEFAULT)

LPC

BOOT BIOS

DESTINATION

RESERVED(NAND)

Routed with 90 ohms impedance

Total length no longer than 11 inches

BBS STRAP

WS

DEBUG PORT

RESERVE FOR USB3.0

WS

RESERVE FOR USB3.0

eSATA

WLAN

WEBCAM

BT

3G

WS

RESERVE FOR USB3.0

FOR eSATA

RESERVE FOR USB3.0

CLOSE TO PCH

Sun Jan 02 17:15:21 2011

EVEREST-M

97

32

Frank Hu

10K_5%_2_DY

1

2

22_5%_2

SMC_WAKE_SCI#

2

PCH_XDPFN4

PCH_XDPFN2

PCH_XDPFN3

PCH_XDPFN5

PCH_XDPFN1

PCH_XDPFN0

2

1

A14

10K_5%_2_DY

1

P3V3_A

0_5%_2

R4817

1

USB_OC#_0

USB_OC#_1

USB_OC#_2

P3V3_A

USB_P13_DP

USB_P13_DN

2

USB_P12_DP

10K_5%_2_DY

R4896

2

USB_P12_DN

USB_P10_DP

USB_P2_DP

USB_P2_DN

USB_P1_DP

USB_P1_DN

2

1

R4837

2

10K_5%_2

SMC_WAKE_SCI#

10K_5%_2

2

R4838

B17

1

2

0_5%_2

10K_5%_2

1

R4840

2

0_5%_2

R4835

R4839

R4836

1

2

10K_5%_2

USB_P0_DP

USB_P0_DN

BB7

10K_5%_2

L30

TP4714

1

C30

A30

TP4715

1

E30

G30

TP4702

1

R4715

R4880

M28

USB_P10_DN

K30

L32

E28

H28

C26

B25

A26

K28

USB_P5_DN

AT12

USB_P5_DP

A24

C24

C25

R4726

22.6_1%_3

L16

CLK_PCI_DEBUG_R

1

R4879

32<>

USB3_P1_RX_DN

BC28

BE30

USB3_P3_TX_DN

USB3_P3_RX_DN

BE28

USB3_P3_TX_DP

USB3_P1_TX_DP

USB3_P1_TX_DN

USB3_P3_RX_DP

USB3_P1_RX_DP

BC30

AU28

AB45

CLKIN_PCI_FB

29<

P3V3_A

32<

1K_5%_2_DY

BUF_PLT_RST#

PLT_RST#

BTMDL#

CLK_PCI_TPM

CLK_PCI_EC

DGPU_PWM_SELECT#

BBS_BIT1

37<39<60<68<

100K_5%_2

TC7SZ08FU

0.1UF_16V_2

32<>

54>

1K_5%_2_DY

10K_5%_2

P3V3_S

1K_5%_2_DY

43<

37<>

P3V3_A

22_5%_2

54>

32<>

50>

10K_5%_2

37>

0_5%_2

PCH_XDPFN7

PCH_XDPFN6

CLK_PCI_DEBUG

55<

1

R4832

1

R4716

1

2

R4728

1

2

R4821

1

2

R4878

1

2

R4877

1

2

R4714

1

2

R4881

2

1

2

C4772

1

2

U4701

1

2

3

4

5

R4727

1

2

STP_A16OVR

U4700

DGPU_HOLD_RST#

DGPU_SELECT#

DGPU_PWM_SELECT#_R

BTMDL#

SATA_ODD_DA#

PCI_3S_INTG#

PCI_3S_INTH#

+V3A_PME#

CLK_PCI_EC_R

CLK_PCI_TPM_R

67<

37< 32<

DGPU_PWR_EN#

1

2

1

R4834

1

R4833

P3V3_A

AV28

BG32

BG46

AY16

M20

B21

AB46

AM5

L24

K24

Y13

C18

AM4

AK43

BG16

AH37

AH38

BJ16

BH25

BG26

AW30

CLK_PCI_FB_R

H43

H49

K42

J48

C6

K10

D44

C42

G40

G42

F46

E42

D47

E40

C44

C46

G38

H38

K38

K40

H40

ITL_PANTHERPOINT_FCBGA_989P

C14

D14

A16

C16

K20

B33

C33

A32

C32

E32

G32

K32

N28

C28

A28

C29

B29

D28

BF3

BA2

AY5

AT8

AV10

AV5

BD4

BE8

BA3

BB1

AV1

AV3

AT5

AY3

AT1

AT3

BB3

BB5

AT4

AU2

BC8

AY7

AV7

AU3

BG4

AT10

BF6

32<

N30

AK45

H3

AH12

C

A01

CS

CS_1310AXXXXXX-MTR

BJ26

32<>

2

1

R4780 10K_5%_2

2

1

R4818 10K_5%_2

2

1

R4717 10K_5%_2

2

1

R4718

10K_5%_2_DY

2

1

R4721

10K_5%_2_DY

2

1

R4720

10K_5%_2_DY

2

1

R4719 10K_5%_2

2

1

R4724

8.2K_5%_2

2

1

R4723

8.2K_5%_2

2

1

R4722

10K_5%_2_DY

2

1

R4725

8.2K_5%_2

2

1

R4711

8.2K_5%_2

37<32>

50>

32<>

67<32>

67<

37>

32<>

37>32>

32<>

37>

33>

P3V3_S

32<>

PCI_3S_INTA#

DGPU_PWR_EN#

SATA_ODD_DA#

DGPU_SELECT#

EC_DGPU_PWR_EN#

PCI_3S_INTH#

DGPU_HOLD_RST#

PCI_3S_INTG#

RUNSCI0#

PCI_3S_INTD#

PCI_3S_INTC#

PCI_3S_INTB#

32<>

PCI_3S_INTC#

PCI_3S_INTA#

PCI_3S_INTB#

PCI_3S_INTD#

BE32

BF32

AY26

BJ32

BB26

AV26

AY30

AU26

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

IN

BI

IN

BI

OUT

BI

OUT

BI

OUT

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

+

-

BI

OUT

BI

USB

PCI

NVRAM

RSVD

TP24

TP10

TP11

TP12

TP13

TP14

TP15

TP5

TP4

USB3TP4

USB3TP3

USB3TP2

USB3TP1

USB3TN4

USB3TN3

USB3TN2

USB3TN1

USB3RP4

USB3RP3

USB3RP2

USB3RP1

USB3RN4

USB3RN3

USB3RN2

USB3RN1

TP23

TP22

TP21

TP20

TP19

TP18

TP17

TP16

TP9

TP8

TP7

TP6

TP3

TP2

TP1

PLTRST#

CLKOUT_PCI3

CLKOUT_PCI4 OC7#/GPIO14

OC6#/GPIO10

OC5#/GPIO9

OC4#/GPIO43

OC3#/GPIO42

OC2#/GPIO41

OC1#/GPIO40

OC0#/GPIO59

USBRBIAS

USBRBIAS#

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI0

PME#

USBP13P

USBP13N

USBP12P

USBP12N

USBP11P

USBP11N

USBP10P

USBP10N

USBP9P

USBP9N

USBP8P

USBP8N

USBP7P

USBP7N

USBP6P

USBP6N

USBP5P

USBP5N

USBP4P

USBP4N

USBP3P

USBP3N

USBP2P

USBP2N

USBP1P

USBP1N

USBP0P

USBP0N

PIRQH#/GPIO5

PIRQG#/GPIO4

PIRQF#/GPIO3

PIRQE#/GPIO2

GNT3#/GPIO55

GNT2#/GPIO53

GNT1#/GPIO51

REQ3#/GPIO54

REQ2#/GPIO52

REQ1#/GPIO50

PIRQD#

PIRQC#

PIRQB#

PIRQA#

RSVD29

RSVD28

RSVD27

RSVD26

RSVD24

RSVD25

RSVD16

RSVD15

RSVD14

RSVD13

RSVD12

RSVD11

RSVD10

RSVD9

RSVD22

RSVD21

RSVD20

RSVD19

RSVD18

RSVD17

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD23

PCH 6 MISC

HIGH - INTEL ME CRYPTO TLS CIPHER SUITE WITH CONFIDENTIALITY

STRAP PIN

HOST_ALERT#1 - TLS CONFIDENTIALITY

STRAP PIN

INTEGRATED CLOCKING

1:DEFAULT/0:ENABLE

LOW- TX,RXTERMINATED TO SAME VOLTAGE

(DC COUPLING MODE) DEFAULT

HIGH-ENABLED (DEFAULT)

PCH_XDPFN8 - ON DIE PLL VOLTAGE REGULATOR

LOW-DISABLED

STRAP

FDI_OVRVLTG

LOW - (DEFAULT) ENABLE INTEGRATED CLK

STRAP PIN

LOW - (DEFAULT) INTEL ME CRYPTO TRANSPORT LAYER SECURITY(TLS) CIPHER SUITE WITH NO CONFIDENTIALITY

HIGH - DISABLE INTEGRATED CLK

CLOSE TO PCH

BOTH THESE SHOULD BE

FOLLOW EDS1.0

WS

Sun Jan 02 17:58:29 2011

Frank Hu

EVEREST-M

33

97

BJ6

BG2

BG48

P37

390_5%_2

1

R4712

2

AH8

AH10

AK11

T14

V8

2

1

R4867

AK10

AY1

PCH_PECI

PCH_XDPFN16

HOST_ALERT#1

33>

P3V3_A

33>

GFX_CRB_DET

P3V3_S

2

10K_5%_2

33> 33<

R4870

MFG_MODE

P3V3_S

LAN_PHY_PWR

33>

37>

DGPU_PWROK

P3V3_S

33>

GFX_CRB_DET

1

DGPU_HPD_INTR#_R

H36

E38

E8

T5

20>

PM_THRMTRIP#

38<

AY10

NV_CLE

THRMTRIP#_R

56_5%_2_DY

R4713

1

2

P1V05_VCCPS

20>

R4860

PCH_XDPFN13

E16

P4

AU16

E1

F49

F1

E49

D49

D1

C48

C2

BJ5

BJ46

BJ45

BJ44

BJ4

BH47

BH3

AY11

P5

A40

C41

B41

C40

K4

PCH_XDPFN12

R4866

M5

BF1

BF49

BE49

BE1

BD49

BD1

B47

B3

A6

A5

A46

A45

A44

A4

D6

V3

V13

M3

N2

K1

P8

D40

U2

G2

C4

C10

A42

T7

C

A01

CS

50<

37<

20>

37<>

37>

60> 20<

0_5%_2_DY

10K_5%_2

P3V3_S

P3V3_A

59<

33>

1K_5%_2

P3V3_A

1K_5%_2

10K_5%_2

0_5%_2

10K_5%_2

0_5%_2

32<

39<>

33>

67<

16>

10K_5%_2

0_5%_2

50> 33>

33>

33>33<

33>

0_5%_2

33>37>

33<

33> 33<

50>

33>

37>

33>

10K_5%_2

200K_1%_2

10K_5%_2_DY

10K_5%_2

100K_5%_2

33>

1K_5%_2_DY

P3V3_S

10K_5%_2

10K_5%_2_DY

H_PECI

HOST_ALERT#1

ICC_EN#

SATA_ODD_PRSNT#

FDI_OVRVLTG

BIOS_REC

SATA_ODD_PRSNT#

TEST_DET

BIOS_REC

FDI_OVRVLTG

PCH_XDPFN8

CRIT_TEMP_REP#

33<

33>

TEST_DET

MFG_MODE

10K_5%_2_DY

10K_5%_2

10K_5%_2_DY

CRIT_TEMP_REP#

33<

ICC_EN#

10K_5%_2_DY

1.5K_1%_1/16W

CS_1310AXXXXXX-MTR

R4876

1

2

R4872

1

2

R4871

1

2

R4819

1

2

R4875

1

2

R4874

1

2

R4869

1

2

R4784

1

2

R4811

1

2

R4868

1

2

R4863

1

2

R4831

1

2

R4820

1

2

1

2

R4864

1

R4825

1

2

R4862

1

2

R4830

1

2

R4826

1

2

R4865

1

2

R4873

1

2

R4827

1

2

R4828

2

R4829

1

2

R4781

1

2

R4853

1

2

R4779

1

2

R4861

1

2

33<

PCH_XDPFN8

TEST_DET

RUNSCI0#

PCH_XDPFN15

BIOS_REC

MFG_MODE

GFX_CRB_DET

H_CPUPWRGD

KBRST#

ICC_EN#_R

PCH_XDPFN17

PCH_XDPFN9

PCH_XDPFN14

EC_3S_A20GATE

SATA_ODD_PWREN

ITL_PANTHERPOINT_FCBGA_989P

10K_5%_2

59<

1

U4700

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

GPIO

NCTF

CPU/MISC

DF_TVS

VSS_NCTF_16

VSS_NCTF_15

VSS_NCTF_14

VSS_NCTF_13

NC_1

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_31

VSS_NCTF_30

VSS_NCTF_29

VSS_NCTF_28

VSS_NCTF_27

VSS_NCTF_26

VSS_NCTF_25

VSS_NCTF_24

VSS_NCTF_23

VSS_NCTF_22

VSS_NCTF_21

VSS_NCTF_20

VSS_NCTF_19

VSS_NCTF_18

VSS_NCTF_17

TACH5/GPIO69

TACH7/GPIO71

TACH6/GPIO70

TACH4/GPIO68

A20GATE

VSS_NCTF_32

SATA4GP/GPIO16

GPIO35

STP_PCI#/GPIO34

INIT3_3V#

SATA2GP/GPIO36

TACH1/GPIO1

GPIO15

BMBUSY#/GPIO0

GPIO8

THRMTRIP#

PECI

RCIN#

PROCPWRGD

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SLOAD/GPIO38

SCLOCK/GPIO22

SATA5GP/GPIO49/TEMP_ALERT#

SATA3GP/GPIO37

TACH3/GPIO7

TACH0/GPIO17

TACH2/GPIO6

VSS_NCTF_12

VSS_NCTF_11

VSS_NCTF_10

VSS_NCTF_9

VSS_NCTF_8

VSS_NCTF_7

VSS_NCTF_6

VSS_NCTF_5

VSS_NCTF_4

VSS_NCTF_3

VSS_NCTF_2

VSS_NCTF_1

LAN_PHY_PWR_CTRL/GPIO12

GPIO57

GPIO24

GPIO28

GPIO27

15mil

40mil

3A

15mil

1.3A

15mil

PCH 7 POWER

15mil

20mil

15mil

20mil

Frank Hu

EVEREST-M

Sat Jan 01 18:30:57 2011

97

34

ITL_PANTHERPOINT_FCBGA_989P

AJ17

AB36

AT20

AK36

AK37

U47

U48

AM37

AM38

AP36

AP37

V33

V34

AT16

AJ16

AG17

AG16

V1

AP17

AU20

BG6

AP16

BH29

AN34

AN33

AT24

AP26

AP24

AP23

AP21

AN27

AN26

AN21

AN17

AN16

BJ22

AN19

+V1.05S_VCCAPLLEXP

AJ31

AJ29

AJ27

AJ26

AJ23

AG29

AG27

AG26

AG24

AG23

AG21

AF23

AF21

AD23

AD21

AC23

AA23

+V1.05S_VccAFDIPLL

U4700

C4750

1uF_6.3V_2

R4810

2

1

R4808

2

1

C4744

2

1

C4745

2

1

C4732

2

1

C4775

2

1

C4747

2

1

L4700

2

1

C4706

2

1

C4707

2

1

C4708

2

1

L4701

2

1

C4709

2

1

C4748

2

1

C4756

2

1

C4749

2

1

R4809

2

1

2

1

C4752

2

1

C4753

2

1

C4751

2

1

C4754

2

1

2

1

C4710

2

1

C4711

2

1

C4755

2

1

C4746

0_5%_2_DY

+VCCAFDI_VRM

P3V3_S

1uF_6.3V_2

1UF_6.3V_2_DY

CS

P1V05_VCCPS

+V1.05S

10uF_6.3V_3

0.1UF_16V_2

1uF_6.3V_2 1uF_6.3V_2 1uF_6.3V_2

+V1.05S

0_5%_2_DY

+V1.05S

10uF_6.3V_3

+V1.05S

1uF_6.3V_2 1uF_6.3V_2

+VCCAFDI_VRM

0_5%_3

P1V5_S

1uF_6.3V_2

+V3M

+VCCAFDI_VRM

0.01UF_50V_2

0.1UF_16V_2

0.01UF_50V_2

0.1UF_16V_2

P1V8_S

+V1.05S

1uF_6.3V_2

22uF_6.3V_5

P1V05_VCCPS

P3V3_S

10uF_6.3V_3 0.01UF_50V_2 0.1UF_16V_2

FBM_11_160808_121T

P1V8_S

P3V3_S

A01

CS_1310AXXXXXX-MTR

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

LVDS

FDI

POWER

VCC CORE

CRT

DMI

HVCMOS

VCCIO

NAND / SPI

VCCCORE[12]

VCCCORE[13]

VCCCORE[14]

VCCCORE[15]

VCCIO[28]

VCCIO[15]

VCCCORE[17]

VCCCORE[16]

VCCCORE[11]

VCCCORE[10]

VCCCORE[9]

VCCCORE[8]

VCCCORE[7]

VCCCORE[6]

VCCCORE[5]

VCCCORE[4]

VCCCORE[2]

VCCCORE[1]

VCCCORE[3]

VCCSPI

VCCVRM[2]

VccAFDIPLL

VCCDFTERM[4]

VCCDFTERM[3]

VCCADAC

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCALVDS

VCCVRM[3]

VCCAPLLEXP

VCCTX_LVDS[4]

VCCTX_LVDS[3]

VSSADAC

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCC3_3[3] VCCDFTERM[2]

VCCDFTERM[1]

VCCDMI[1]

VCCCLKDMI

VCCDMI[2]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCCIO[27]

PCH 8 POWER

10mil

15mil

20mil

15mil

20mil

15mil

10mil

15mil

20mil

10mil

20mil

10mil

3A

10mil

20mil

10mil

1.1A

20mil

EVEREST-M

Sat Jan 01 18:31:14 2011

Frank Hu

35

97

+V1.05S

AA26

22uF_6.3V_5

1

V21

T21

T19

P32

AC16

AC17

AD17

AF11

AK1

AF14

AH14

AH13

AF13

AJ2

T34

W16

AA16

P22

P20

N22

N20

P34

AN24

AN23

M26

T26

P24

V24

V23

T24

T23

T29

T27

P28

P26

N26

V5REF

C4738

0.1UF_16V_2

A22

BJ8

V19

T17

V16

AG33

AG34

AF34

AF33

AF17

BF47

BD47

Y49

N16

W33

W31

W29

W26

W24

W23

W21

AD31

AD29

AC31

AC29

AC27

AC26

AA31

AA29

AA27

AA24

AA21

AA19

AL24

AL29

BH23

T38

V12

T16

AD49

+V1.05S_VCCAPLLSATA

P3V3_S

0.1UF_16V_2

C4701

1

2

C4735

1

VSREF_SUS

2

C4773

1uF_6.3V_2

ITL_PANTHERPOINT_FCBGA_989P

1uF_6.3V_2

0.1UF_16V_2

1

22UF_6.3V_5_DY

FBM_11_160808_121T

U4700

+V1.05S_VCCAPLLDMI2

VCCADPLLB

VCCADPLLA

+V1.05S_VCCACLK

2

1

C4712

2

1

C4713

2

1

C4733

2

1

C4700

2

1

L4702

2

1

C4734

2

1

2

1

2

1

C4736

2

1

C4737

2

1

R4709

2

1

3

D4700

1

C4770

2

1

C4739

2

1

R4710

2

1

3

D4701

2

1

2

C4740

2

1

C4716

2

1

C4702

2

1

C4742

2

1

C4741

2

1

C4743

2

1

C4719

2

1

C4718

2

1

R4805

2

1

C4720

2

1

C4721

2

1

C4722

2

1

C4723

2

1

C4724

2

1

L4703

2

1

L4704

2

1

C4725

2

C4726

2

1

C4728

2

1

C4727

2

1

C4729

2

1

C4730

2

1

C4731

2

1

C4703

2

C4715

2

1

C4714

2

1

C4771

2

1

R4806

2

1

C4705

2

1

C4704

2

1

C4717

2

1

C4774

2

1

R4807

1uF_6.3V_2

+V_RTC

0_5%_2_DY

1uF_6.3V_2

10uF_6.3V_3

22UF_6.3V_5_DY

1uF_6.3V_2

22uF_6.3V_5

0_5%_2_DY

0.1UF_10V_2_DY

0.1UF_16V_2

1uF_6.3V_2_DY

P3V3_S

0.1UF_16V_2

1uF_6.3V_2

+V1.05M

P3V3_A

0.1UF_16V_2

CS_1310AXXXXXX-MTR

+V1.05_LAN_M_DCPSUS<1>

4.7uF_6.3V_3 0.1UF_16V_2

FBM_11_160808_121T

P1V05_VCCPS

+V1.05_LAN_M

1UF_6.3V_2_DY

+V1.05S

1uF_6.3V_2

+V1.05S

+V1.05M

0.1UF_16V_2

P3V3_S

10uF_6.3V_3

P3V3_A

0.1UF_16V_2

0.1UF_16V_2 0.1UF_16V_2

0.1UF_16V_2

1uF_6.3V_2

10uF_6.3V_3

+VCCAFDI_VRM

1uF_6.3V_2

0.1UF_16V_2

1uF_6.3V_2

1uF_6.3V_2_DY

+V1.05S

0.1UF_16V_2

0_5%_2_DY

1uF_10V_2

0603_DY

+V1.05S

+VCCAFDI_VRM

P3V3_A

P3V3_S

P3V3_A

+V1.05S

P3V3_A

10_5%_5

1uF_10V_2

BAT54_30V_0.2A

0.1UF_16V_2

BAT54_30V_0.2A

10_5%_5

P3V3_A

+V1.05S

P5V_S

P3V3_S

P5V_A

P3V3_A

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

NC

HDA

CPU

RTC

PCI/GPIO/LPC

MISC

POWER

USB

Clock and Miscellaneous

SATA

VCCVRM[4]

DCPRTC

VCCASW[20]

VCC3_3[2]

VCCASW[18]

VCCASW[15]

VCCASW[19]

VCCIO[5]

VCCASW[17]

VCCASW[16]

VCCASW[1]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCASW[2]

VCCIO[29]

VCCAPLLDMI2

VCCASW[4]

DCPSUSBYP

VCCASW[3]

VCCASW[5]

VCCASW[6]

VCCSUSHDA

VCCSUS3_3[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

V5REF

VCC3_3[4]

VCCRTC

VCCSUS3_3[10]

VCCSUS3_3[9]

VCCSUS3_3[8]

VCCSUS3_3[7]

VCCADPLLB

VCCDIFFCLKN[1]

DCPSUS[1]

VCCSSC

VCCADPLLA

VCCACLK

VCCDIFFCLKN[2]

DCPSST

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCC3_3[1]

VCC3_3[8]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

V_PROC_IO

VCCDIFFCLKN[3]

VCCASW[13]

VCCASW[14]

VCCVRM[1]

VCCAPLLSATA

DCPSUS[3]

DCPSUS[2]

VCCDSW3_3

VCC3_3[5]

VCCIO[14]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCIO[7]

PCH 9 GND

Sun Jan 02 18:04:06 2011

Frank Hu

EVEREST-M

97

36

AB11

AA34

AA33

AA3

AA2

AK46

D42

ITL_PANTHERPOINT_FCBGA_989P

BB38

M24

BB12

F45

G48

H26

AY4

AY42

AY46

AY8

B11

B15

B19

B23

B27

B31

B35

B39

B7

BB16

BB20

BB22

BB24

BB28

BB30

BB4

BB46

BC14

BC18

BC2

BC22

BC26

BC32

BC34

BC36

BC40

BC42

BC48

BD46

BD5

BE22

BE26

BE40

BF10

BF12

BF16

BF20

BF22

BF24

BF26

BF28

BD3

BF30

BF38

BF40

BF8

BG17

BG21

BG33

BG44

BG8

BH11

BH15

BH17

BH19

H10

BH27

BH31

BH33

BH35

BH39

BH43

BH7

D3

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D8

E18

E26

G18

G20

G26

G28

G36

H12

H18

H22

H24

H30

H32

H34

F3

H46

K18

K26

K39

K46

K7

L18

L2

L20

L26

L28

L36

L48

M12

P16

M18

M22

M30

M32

M34

M38

M4

M42

M46

M8

N18

P30

N47

P11

P18

T33

P40

P43

P47

P7

R2

R48

T12

T31

T37

T4

W34

T46

T47

T8

V11

V17

V26

V27

V29

V31

V36

V39

V43

V7

W17

W19

W2

W27

W48

Y12

Y38

Y4

Y42

Y46

Y8

BG29

N24

AJ3

AD47

B43

BE10

BG41

G14

H16

T36

BG22

BG24

C22

AP13

M14

AP3

AP1

BE16

BC16

BG28

BJ28

U4700

AW36

ITL_PANTHERPOINT_FCBGA_989P

AF12

AD16

AM36

AP8

H5

AA17

AB43

AM39

AM43

AM45

AM46

AM7

AN2

AN29

AN3

AN31

AP12

AB5

AP19

AP28

AP30

AP32

AP38

AP4

AP42

AP46

AR2

AB7

AR48

AT11

AT13

AT18

AT22

AT26

AT28

AT30

AT32

AT34

AC19

AT39

AT42

AT46

AT7

AU24

AU30

AV16

AV20

AV24

AV30

AC2

AV38

AV4

AV43

AV8

AW14

AW18

AW2

AW22

AW26

AW28

AC21

AW32

AW34

AW40

AW48

AV11

AY12

AY22

AY28

AC24

AC33

AC34

AC48

AD10

AD11

AD12

AD13

AD19

AD24

AD26

AD27

AD33

AD34

AD36

AD37

AD38

AD39

AD4

AD40

AD42

AD43

AD45

AD46

AD8

AE2

AE3

AF10

AD14

AF16

AF19

AF24

AF26

AF27

AF29

AF31

AF38

AF4

AF42

AF46

AF5

AF7

AF8

AG19

AG2

AG31

AG48

AH11

AH3

AH36

AH39

AH40

AB14

AH42

AH46

AH7

AJ19

AJ21

AJ24

AJ33

AJ34

AK12

AK3

AB39

AK38

AK4

AK42

AK8

AL16

AL17

AL19

AL2

AL21

AB4

AL23

AL26

AL27

AL31

AL33

AL34

AL48

AM11

AM14

U4700

CS_1310AXXXXXX-MTR

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

VSS[352]

VSS[351]

VSS[350]

VSS[349]

VSS[348]

VSS[347]

VSS[346]

VSS[345]

VSS[344]

VSS[343]

VSS[342]

VSS[340]

VSS[338]

VSS[337]

VSS[335]

VSS[334]

VSS[333]

VSS[331]

VSS[330]

VSS[329]

VSS[328]

VSS[325]

VSS[324]

VSS[323]

VSS[322]

VSS[321]

VSS[320]

VSS[319]

VSS[318]

VSS[317]

VSS[316]

VSS[315]

VSS[314]

VSS[313]

VSS[312]

VSS[311]

VSS[310]

VSS[309]

VSS[308]

VSS[307]

VSS[306]

VSS[305]

VSS[304]

VSS[303]

VSS[302]

VSS[301]

VSS[300]

VSS[299]

VSS[298]

VSS[297]

VSS[296]

VSS[295]

VSS[294]

VSS[293]

VSS[292]

VSS[291]

VSS[290]

VSS[289]

VSS[288]

VSS[287]

VSS[286]

VSS[285]

VSS[284]

VSS[283]

VSS[282]

VSS[281]

VSS[280]

VSS[279]

VSS[278]

VSS[277]

VSS[276]

VSS[275]

VSS[274]

VSS[273]

VSS[272]

VSS[271]

VSS[270]

VSS[269]

VSS[268]

VSS[267]

VSS[266]

VSS[265]

VSS[264]

VSS[263]

VSS[262]

VSS[261]

VSS[260]

VSS[259]

VSS[258]

VSS[257]

VSS[256]

VSS[255]

VSS[254]

VSS[253]

VSS[252]

VSS[251]

VSS[250]

VSS[249]

VSS[248]

VSS[247]

VSS[246]

VSS[245]

VSS[244]

VSS[243]

VSS[242]

VSS[241]

VSS[240]

VSS[239]

VSS[238]

VSS[237]

VSS[236]

VSS[235]

VSS[234]

VSS[233]

VSS[232]

VSS[231]

VSS[230]

VSS[229]

VSS[228]

VSS[227]

VSS[226]

VSS[225]

VSS[224]

VSS[223]

VSS[222]

VSS[221]

VSS[220]

VSS[219]

VSS[218]

VSS[217]

VSS[216]

VSS[215]

VSS[214]

VSS[213]

VSS[212]

VSS[211]

VSS[210]

VSS[209]

VSS[208]

VSS[207]

VSS[206]

VSS[205]

VSS[204]

VSS[203]

VSS[202]

VSS[201]

VSS[200]

VSS[199]

VSS[198]

VSS[197]

VSS[196]

VSS[195]

VSS[194]

VSS[193]

VSS[192]

VSS[191]

VSS[190]

VSS[189]

VSS[188]

VSS[187]

VSS[186]

VSS[185]

VSS[184]

VSS[183]

VSS[182]

VSS[181]

VSS[180]

VSS[179]

VSS[178]

VSS[177]

VSS[176]

VSS[175]

VSS[174]

VSS[173]

VSS[172]

VSS[171]

VSS[170]

VSS[169]

VSS[168]

VSS[167]

VSS[166]

VSS[165]

VSS[164]

VSS[163]

VSS[162]

VSS[161]

VSS[160]

VSS[159]

VSS[158]

VSS[157]

VSS[156]

VSS[155]

VSS[154]

VSS[153]

VSS[152]

VSS[151]

VSS[150]

VSS[149]

VSS[148]

VSS[147]

VSS[146]

VSS[145]

VSS[144]

VSS[143]

VSS[142]

VSS[141]

VSS[140]

VSS[139]

VSS[138]

VSS[137]

VSS[136]

VSS[135]

VSS[134]

VSS[133]

VSS[132]

VSS[131]

VSS[130]

VSS[129]

VSS[128]

VSS[127]

VSS[126]

VSS[125]

VSS[124]

VSS[123]

VSS[122]

VSS[121]

VSS[120]

VSS[119]

VSS[118]

VSS[117]

VSS[116]

VSS[115]

VSS[114]

VSS[113]

VSS[112]

VSS[111]

VSS[110]

VSS[109]

VSS[108]

VSS[107]

VSS[106]

VSS[105]

VSS[104]

VSS[103]

VSS[102]

VSS[101]

VSS[100]

VSS[99]

VSS[98]

VSS[97]

VSS[96]

VSS[95]

VSS[94]

VSS[93]

VSS[92]

VSS[91]

VSS[90]

VSS[89]

VSS[88]

VSS[87]

VSS[86]

VSS[85]

VSS[84]

VSS[83]

VSS[82]

VSS[81]

VSS[80]

VSS[79]

VSS[78]

VSS[77]

VSS[76]

VSS[75]

VSS[74]

VSS[73]

VSS[72]

VSS[71]

VSS[70]

VSS[69]

VSS[68]

VSS[67]

VSS[66]

VSS[65]

VSS[64]

VSS[63]

VSS[62]

VSS[61]

VSS[60]

VSS[59]

VSS[58]

VSS[57]

VSS[56]

VSS[55]

VSS[54]

VSS[53]

VSS[52]

VSS[51]

VSS[50]

VSS[49]

VSS[48]

VSS[47]

VSS[46]

VSS[45]

VSS[44]

VSS[43]

VSS[42]

VSS[41]

VSS[40]

VSS[39]

VSS[38]

VSS[37]

VSS[36]

VSS[35]

VSS[34]

VSS[33]

VSS[32]

VSS[31]

VSS[30]

VSS[29]

VSS[28]

VSS[27]

VSS[26]

VSS[25]

VSS[24]

VSS[23]

VSS[22]

VSS[21]

VSS[20]

VSS[19]

VSS[18]

VSS[17]

VSS[16]

VSS[15]

VSS[14]

VSS[13]

VSS[12]

VSS[11]

VSS[10]

VSS[9]

VSS[8]

VSS[7]

VSS[6]

VSS[5]

VSS[4]

VSS[3]

VSS[2]

VSS[1]

VSS[0]

WS

1.Battery

EC_SMB1

EC_SMB2

1.Charge

2.GPU Thermal

EC_SMB3

1.CPU Thermal

Close EC

HIGH - (Default) NORMAL MODE

STRAP PIN

Close EC

low-Enabled

GPO76_SHBM - Enable shared BIOS Memory

LOW - TEST MODE

CLOSE TO EC

EC

STRAP PIN

0: JTAG select

1: (Default)

CLOSE IC PIN

20mil

NEED 0.1UF

WS

37

97

Tue Jan 04 11:09:01 2011

EVEREST-M

Frank Hu

EC_EDP_MUX_IC_SEL

RSMRST#

DRAMRST_CNTRL_EC

0_5%_2

1

52<

USB0_PWREN

SCAN_IN<0>

220_5%_2

0_5%_2

R365

SCAN_OUT<2>

SLP_S5#

CRIT_TEMP_REP#

SUS_OLED#

BAT_OLED#

H_PECI

58<

33>

20>

PM_EXTTS#1

3G_ON#

DGPU_HOLD_RST#

29

PWR_BLED#

EC_SMB3_CLK

58<

119

LID_SW#_3

PWR_SWIN#_3

WLON#

10K_5%_2_DY

FAN_TACH

SLP_S4#

TP_ON#

WL_OLED#

58

R309

1

P1V05_VCCPS

C308

1

EC_DGPU_PWR_EN#

CHG_EN

R368

1

0_5%_2

BOARDID0

DGPU_PWR_EN#

0_5%_2

FLASH_OVERRIDE

26>

32<

EC_PWRSW#

28

R366

123

74

75

2

R367

15

26

R378

43_1%_2

1

86

28>

EC_SPI_SO

SCAN_IN<1>

SCAN_IN<2>

VCC_POR#

2

59

0_5%_2

FAN_TACH

2

1

R361

2

1

R379

2

1

R362

2

1

R380

2

1

R355

2

1

R330

2

1

R357

2

1

PAD300

2

1

C307

2

1

R334

2

1

R335

2

1

R333

2

1

R376

2

1

R336

3

8

7

4

2

5

1

6

U300

2

1

R377

2

1

C314

2

1

C315

2

1

C316

2

1

C317

2

1

R356

2

1

3

Q300

2

1

C310

2

1

C312

2

1

L300

2

1

C306

2

1

C313

2

1

C303

2

1

C304

2

1

C300

2

1

C311

2

1

C305

2

1

2

1

R316

2

1

3

D302

2

1

R313

2

1

R312

2

1

R340

2

1

R339

2

1

R374

2

1

R373

2

1

R371

2

1

R302

2

1

R353

2

1

R352

2

1

R372

2

1

R331

2

1

R300

2

1

R370

2

1

R314

2

1

R301

2

1

R375

2

1

R341

2

1

R303

2

1

R321

2

1

R319

2

1

R322

2

1

R323

2

1

R358

2

1

R359

2

1

C301

2

1

R304

2

1

R305

2

1

R306

2

1

R307

2

1

R308

2

1

2

R310

R311

2

1

R363

2

R364

2

1

2

1

2

1

2

1

R360

2

1

R345

2

1

R329

2

1

R354

2

1

R369

104

4

44

85

115

88

76

46

19

63

117

31

125

12

13

11

10

7

3

2

128

127

126

41

42

43

47

48

49

50

51

52

33

34

35

36

37

38

39

40

53

61

60

57

56

55

54

122

112

111

110

83

113

121

91

84

82

68

67

73

81

9

27

25

24

23

22

21

20

17

80

16

72

71

14

66

65

120

109

6

69

70

114

8

124

94

93

108

96

95

79

64

77

107

5

116

89

78

45

18

87

92

90

106

105

101

30

118

62

102

103

100

99

98

97

32

U301

A01

3.3K_5%_2

10K_5%_2

33_5%_2

WINB_W25Q80BVSSIG_SOIC_8P

BOARDID0

EC_SPI_SO

C

CS_1310AXXXXXX-MTR

CS

P3V3_A

H_PROCHOT#_EC

47K_5%_2

SMC_WAKE_SCI#

EC_SPI_SI

EC_SMB2_DATA

EC_SMB2_CLK

ECSTRAP110

37<>

55>

54<>

EC_MUTE#

ECSTRAP110

BOARDID1

10<

100K_5%_2

EC_PW_ON#

10K_5%_2

VCC_POR#

37<

HW_I_ADC

HW_V_ADC

+V3LA_EC

ACPRESENT

30<

10K_5%_2

0

SCAN_IN<7..0>

SCAN_OUT<17..0>

10K_5%_2_DY

H_PROCHOT#

IM_CLK_5

IM_DAT_5

EC_SMB1_DATA

EC_SMB1_CLK

EC_SMB3_DATA

BOARDID1

SLP_LAN#

SLP_SUS#

EC_SPI_CS0#

EC_SPI_CLK

EC_SPI_CS0#

PECI

PCI_3S_CLKRUN#

PCI_3S_SERIRQ

LPC_3S_AD<3>

LPC_3S_AD<2>

LPC_3S_AD<1>

LPC_3S_AD<0>

LPC_3S_FRAME#

CLK_PCI_EC

PLT_RST#

CAPS_LED#_3

DCIN_BLED#

BAT_BLED1#

FM_32KHZ

SCROLL_LED#_3

BTIFON#

USB1_PWREN

NUM_LED#_3

ACPRES#

EC_LCM_INVPWM

SW_LCM_BKLTEN

H_PROCHOT#_EC

BATT_IN

+V3LA_EC_VREF

FAN_PWMA

MAIN_PWRGD

+V5AUXON

SLP_S3#

SLP_A#

EC_BKLTEN

EC_PCH_PWROK

EC_SPI_SI

EC_SPI_CLK

SCAN_IN<7>

SCAN_IN<6>

SCAN_IN<5>

SCAN_IN<4>

SCAN_IN<3>

SCAN_OUT<17>

SCAN_OUT<16>

SCAN_OUT<15>

SCAN_OUT<14>

SCAN_OUT<11>

SCAN_OUT<12>

SCAN_OUT<13>

SCAN_OUT<10>

SCAN_OUT<9>

SCAN_OUT<7>

SCAN_OUT<6>

SCAN_OUT<8>

HW_V_ADC

BATT_IN

SCAN_OUT<0>

HW_I_ADC

SCAN_OUT<5>

SCAN_OUT<4>

SCAN_OUT<3>

SCAN_OUT<1>

SCAN_OUT<0>

EC_SMI

EC_3S_A20GATE

RUNSCI0#

LOW_BAT#_3

SUS_STAT#

RSMRST#

EC_LCM_INVPWM

KBRST#

SSM3K7002BFU 100K_5%_2

P5V_S

47K_5%_2

53<>

P3V3_AL

10K_5%_2_DY

3.3K_5%_2

29<>

P3V3_AL

2.2K_1%_2

55<

1.8K_5%_2 1.8K_5%_2

72<>

8>

72<>

8>

10K_5%_2_DY

1.5K_1%_1/16W

10K_5%_2

1.5K_1%_2_DY

680pF_50V_2

37< 38>

19<

12<

30>

0_5%_2

37<

37>

28<

1uF_6.3V_2 WINB_NPCE791LA0DX_LQFP_128P

GND_KBC_ALG

30>

11<

38>37<

38>

58<

72<>

30>

37<>

8>

57>

58<

0_5%_2

53<

0_5%_2

9>

10<

P3V3_AL

BAT54_30V_0.2A

100K_5%_2

P3V3_AL

+V3LA_EC

8>

37<

30>

17< 11<

18<

44<48<

9>

37>

8>

37<

4.7K_5%_2

0_5%_2_DY

0_5%_2

10K_5%_2

P3V3_S P3V3_AL

P3V3_AL

0_5%_2

33_5%_2

37>28>

P3V3_AL

GND_KBC_ALG

POWERPAD1x1m

220_5%_2

7

6

4

5

2

3

1

0.1UF_16V_2

17

16

15

14

11

12

13

10

9

7

6

8

37<

8>

53>37>

37<

8>

0.1UF_16V_2

GND_KBC_ALG

0.1UF_16V_2 4.7uF_6.3V_3

5

4

3

2

1

0

P3V3_S

P3V3_AL

+V3LA_EC

0.1UF_16V_2

4.7uF_6.3V_3

FBM_11_160808_121T

P3V3_AL

0.1UF_16V_2

4.7uF_6.3V_3

0.1UF_16V_2

28<

P3V3_S

30<

0_5%_2

30<>

30< 43<

55<

43<

28<>

55<43<

28<>

55<43<

28<>

55<

28<>

43<

32>

39<

32<>

60< 68<

30>

100K_5%_2

10K_5%_2

P3V3_S

10K_5%_2

P3V3_S P3V3_A

37>

30<

P3V3_A

33<

10K_5%_2_DY

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

BI

OUT

BI

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

1

2

IN

OUT

DI

HOLD#

WP#

CS#

CLK

VCC

GND

DO

BI

IN

OUT

IN

OUT

G

DS

OUT

IN

OUTOUT

NC

OUT

IN

OUT

IN

OUTOUT

OUT

IN IN

OUT

IN

BI

OUT

BI

OUT

BI

OUT

IN

BI

OUT

IN

OUT

BI

OUT

BI

IN

OUT

BI

KBSOUT11_P80_DAT

KBSOUT10_P80_CLK

KBSOUT17_GPIO57

KBSOUT16_GPIO60

KBSOUT15_GPIO61_XOR_OUT

KBSOUT14_GPIO62

KBSOUT13_GPIO63

KBSOUT12_GPIO64

KBSOUT9_SDP_VIS#

KBSOUT8

KBSOUT7

KBSOUT6_RDY#

KBSOUT5_TDO

KBSOUT4_JEN0#

KBSOUT3_TDI

KBSOUT2_TMS

KBSOUT1_TCK

KBSOUT0_JENK#

KBSIN7

KBSIN6

KBSIN5

KBSIN4

KBSIN3

KBSIN2

KBSIN1

KBSIN0

VCC_POR#

GPIO52_PSDAT3_RDY#

PSCLK3_GPIO50_TDO

GPIO46_TRST#

GPIO44_TDI

GPIO43_TMS

GPIO42_TCK

GPIO40_F_PWM

GPIO45_E_PWM

PECI

VTT

GPIO87_SIN_CR

SCL4_GPIO47

GPIO51

GPIO36

SDA4_GPIO53

GPO83_SOUT_CR_TRIST#

GPIO72

GPIO71

GPIO67_PWUREQ#

GPIO65_SMI#

ECSCI#_GPIO54

GPIO85_GA20

KBRST#_GPIO86

GPIO11_CLKRUN#

SERIRQ

LAD3

LAD2

LAD1

LAD0

LFRAME#

LCLK

LRESET#

GPIO10_LPCPD#

GPIO34

GPIO41

VDD

AVCC

VCC5

VCC4

VCC3

VCC2

VCC1

GND6

GND5

GND4

GND3

GND2

GND1

AGND

VCORF

GPIO37_PSCLK1

GPIO35_PSDAT1

PSCLK2_GPIO26

PSDAT2_GPIO27

F_SCK

GPIO81

F_CS0#

F_SDIO0

F_SDIO1

GPIO17_SCL1

GPIO22_SDA1

GPIO73_SCL2

GPIO74_SDA2

GPIO33_H_PWM

GPIO32_D_PWM

TA2_GPIO20

TA1_GPIO56

TB1_GPIO14

A_PWM_GPIO15

B_PWM_GPIO21

C_PWM_GPIO13

CLKOUT_GPIO55

GPIO02

GPIO00_EXTCLK

GPIO16

GPIO24

GPIO70

GPO82_TEST#

GPO84_XORTR#

GPIO75

GPO76_SHBM

GPIO77

GPIO31_SDA3

GPIO30

GPIO23_SCL3

GPIO07

GPIO06

GPIO03

GPIO01

GPIO66_G_PWM

GPIO97

DA2_GPIO96

DA1_GPIO95

DA0_GPIO94

GPIO04

GPIO05

AD3_GPIO93

AD2_GPIO92

AD1_GPIO91

AD0_GPIO90

VREF

30mil

RSET=0.0012*T2-0.9308*T+96.147

10mil

Hysteresis is 30C

FAN & THERMAL

GM Thermal shutdown at 80.8℃+/-3℃from 60℃to 100℃

PM Thermal shutdown at 86℃+/-3℃from 60℃to 100℃

38

97

Fri Dec 31 10:16:37 2010

EVEREST-M

Frank Hu

2 3

1

Q4301

G2

G1

4

3

2

1

CN4300

2

1

C4304

2

1

C4302

2

1

R4304

2

1

R4305

2

1

C4300

2

1

R4301

2

1

R4300

2

1

3

Q4300

2

1

R4302

2

1

C4301

2

1

R4303

5

1

34 2

U4411

2

1

C4303

LMBT3904LT1G

THRM_SHUTDWN#

4.7K_5%_2

1000PF_50V_2_DY

ACES_50273_0047N_001_4P

4.7UF_10V_3

CSC0402_DY

CS_1310AXXXXXX-MTR

+THM_VDD

FAN_PWMA

FAN_TACH

PM_THRMTRIP#

VR_PWRGD

THRM_SHUTDWN#

0.1UF_16V_2

P5V_AL

150_5%_2

GMT_G708T1U_SOT23_5P

32.4K_1%_2

37>

P3V3_S

37<

4.7K_5%_2

P3V3_S

P5V_S

330_5%_2

14>18<

2M_5%_2

SSM3K7002BFU

0.1UF_16V_2

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

B

C E

G

4

3

2

1

OUT

IN

OUT

G

DS

OUT

VCC SET

GND

OT

HYST

15MIL

30MIL

15MIL

LAN

0805

4.7UH

EVEREST-M

39

97

Fri Dec 31 10:16:38 2010

Frank Hu

2

1

C401

2

1

R412

2

1

R416

2

1

R417

2

1

C415

2

1

C402

2

1

L400

2

1

R402

2

1

C400

2

1

R413

2

1

R400

2

1

R401

2

1

R414

2

1

C413

2

1

C414

2

1

C416

2

1

R415

2

1

C412

2

1

C411

2

1

X400

2

1

R403

2

1

R404

2

1

R405

2

1

R406

2

1

R407

1

TP401

1

TP402

1

TP400

2

1

C403

2

1

C404

2

1

R418

2

1

R409

2

1

R408

2

1

R410

2

1

R411

9

10

49

4

5

29

19

15

8

47

46

43

40

37

22

16

11

30

31

28

2

1

6

12

38

39

41

42

36

44

45

23

20

17

13

24

21

18

14

25

27

26

3

33

34

32

35

7

48

U400

+V3M_LAN

22UF_6.3V_5

A01

CS_1310AXXXXXX-MTR

0.1UF_16V_2

0603_DY

SMB_DATA_LAN

SMB_CLK_LAN

0.1UF_16V_2

22UF_6.3V_5

68<

29>

CLK_PCIE_LAN_DN

PCIE_LAN_RX_DP

PCIE_LAN_RX_DN

CS

60< 37<

CLK_PCIE_LAN_DP

LED_R3S_LANACT#

LED_R3S_LANLINK#

+V1.05_LAN_CTRL_1P0

LAN_X2

40<

0_5%_2

0.1UF_16V_2

0_5%_5

0_5%_2

CLKREQ_LAN#_R

+V1.05_LAN

0_5%_5

LAN_JTAG_TCK

LAN_X1

LAN_JTAG_TMS

LAN_PHY_PWR

SML0_DATA

SML0_CLK

LAN_X2

LAN_X1

PCIE_LAN_TX_DN

PCIE_LAN_TX_DP

PCIE_LAN_RX_C_DN

PCIE_LAN_RX_C_DP

PLT_RST#_R

LAN_JTAG_TCK

LAN_JTAG_TMS

LAN_TRD3_DN

LAN_TRD3_DP

LAN_TRD2_DN

LAN_TRD2_DP

LAN_TRD1_DN

LAN_TRD1_DP

LAN_TRD0_DN

LAN_TRD0_DP

+V3M_LAN_RSVD_NC

LAN_ENABLE

+V3M_LAN_RSVD_VCC3P3_2

+V3M_LAN_RSVD_VCC3P3_1

PLT_RST#

CLKREQ_LAN#

33PF_50V_2

25MHZ

10K_5%_2_DY

33PF_50V_2

0_5%_2

39<

39<>

+V3M_LAN

10K_5%_2_DY

0.1UF_16V_2

+V3M

39<>

33>

0_5%_2_DY

10K_5%_2

29>29<

29>

29<

0_5%_2

1K_5%_2

39>

3.01K_1%_2

ITL_LEWISVILLE_PQFN_48P

39<>

0.1UF_16V_2

+V3M_LAN

29>

29<

29>

29<

32<>

29<

0.1UF_16V_2

0_5%_2

10K_5%_2

P3V3_A

0_5%_2

1UF_10V_2

0_5%_2_DY

4.7K_5%_2

+V1.05_LAN_M

40<

+V3M_LAN

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

OUT

BI

IN

BI

OUT

IN

LED

JTAG

SMBUS

MDI

PCIE

VSS_EPAD

CLK_REQ_N

VDD1P0_47

VDD1P0_46

PE_CLKN

PE_CLKP

VDD1P0_43

PERn

PERp

VDD1P0_40

PETn

PETp

VDD1P0_37

PE_RST_N

JTAG_TCK

JTAG_TDO

JTAG_TMS

JTAG_TDI

SMB_DATA

TEST_EN

VDD3P3_29

SMB_CLK

LED1

LED0

LED2

MDI_MINUS3

MDI_PLUS3

VDD1P0_22

MDI_MINUS2

MDI_PLUS2

VDD3P3_19

MDI_MINUS1

MDI_PLUS1

VDD1P0_16

VDD3P3_15

MDI_MINUS0

MDI_PLUS0

RBIAS

VDD1P0_11

XTAL_IN

XTAL_OUT

VDD1P0_8

CTRL_1P0

RSVD_NC

VDD3P3_IN

VDD3P3_OUT

LAN_DISABLE_N

RSVD_VCC3P3_2

RSVD_VCC3P3_1

RJ45 & TRANSFORMER

8152 OPEN

WS

97

EVEREST-M

40

Tue Jan 04 00:15:14 2011

Frank Hu

+V3M_LAN_TRANSFORMER

+V3M_LAN

LAN_TRD0_CN_DN

LAN_TRD0_CN_DP

LAN_TRD2_CN_DN

LAN_TRD1_CN_DN

LAN_TRD1_CN_DP

LAN_TRD2_CN_DP

LAN_TRD3_CN_DN

LAN_TRD3_CN_DP

JACK470

RSC_0603_DY

LAN_TRD3_DN

LAN_TRD3_DP

LAN_TRD2_DN

LAN_TRD2_DP

LAN_TRD1_DN

LAN_TRD1_DP

LAN_TRD0_DP

0.1UF_16V_2

C408

RSC_0603_DY

2

SYN_100073HR008G13CZL_8P

G1

G2

G3

G4

4

5

7

8

3

6

1

2

13

17

16

18

20

23

19

21

0.1UF_16V_2

C409

1

LAN_TRD0_DN

12

11

9

8

6

5

3

2

10

7

4

1

14

22

15

24

U470

BOTH_GST5009_SOP_24P

LAN_TRD0_CN_DN

LAN_TRD1_CN_DN

LAN_TRD2_CN_DN

LAN_TRD3_CN_DN

LAN_TRD0_CN_DP

LAN_TRD1_CN_DP

LAN_TRD2_CN_DP

LAN_TRD3_CN_DP

C406

2

0.1UF_16V_2

2

1

R472

1

R475

2

1

R476

2

1

R478

2

1

R477

2 2

1

2

1

C407

2

1

C405

1

2

1

C410

2

1

R471

2

1

R470

2

1

R474

2

1

R473

0_5%_2_DY

LED_R3S_LANLINK#

A01

LED_R3S_LANACT#

0.1UF_16V_2 1UF_6.3V_2

+V3M_LAN

RSC_0603_DY

75_5%_3 75_5%_3

1000PF_2000V_6

75_5%_3 75_5%_3

40<

C

CS

CS_1310AXXXXXX-MTR

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

MX4+

MX3+

MX2+

MX1+

MX4-

MX3-

MX2-

MX1-

MCT4

MCT3

MCT2

MCT1

TD4+

TD3+

TD2+

TD1+

TD4-

TD3-

TD2-

TD1-

TCT4

TCT3

TCT2

TCT1

IN

G

TX+

TX-

RX+

P4

P5

P7

P8

RX-

IN

OUT

11/16 MODIFY FOR VENDOR COMMAND

R501 ONLY NEEDED FOR -11Z

PORT C: MICROPHONE JACK

PORT B: INTERNAL MIC

PORT CONFIGURATION

PORT A: HEADPHONE JACK

AUDIO CODEC

10 MIL

NEAR CODEC

RESERVE FOR EMI, CLOSE TO CODEC

120 OHMS@100MHZ

0OHM_5% 1206 PAD

RESERVE FOR EMI (10-22PF)

10 MIL

IS REMOVED DURING SYSTEM RE-START.

AND IF SUPPLY TO VAUX_3.3

10 MIL

PLACE BYPASS CAPS CLOSE TO DEVICE.

1A

Sun Jan 02 13:16:19 2011

Frank Hu

EVEREST-M

41

97

C514

1UF_6.3V_2

C516

2

42<

C_BIAS

1

2

10K_1%_2

P3V3_A

100_5%_2

35

34

33

27

25

CONEX_CX20671_21Z_QFN_40P

0.1UF_16V_2

C511

0.1UF_16V_2

R507

0.1UF_16V_2

C510

1

2

1

R512

4

8

C

A01

P3V3_S

10UF_6.3V_5

LDO_OUT_3.3V

0.1UF_16V_2

10UF_6.3V_3

10UF_6.3V_5

5.11K_1%_2

39.2K_1%_2

0.1UF_16V_2

CSC0402_DY

0.1UF_16V_2

0_5%_2

CSC0402_DY

+V5S_LPWR_5.0

SPK_OUT_R+_R

SPK_OUT_R-_R

SPK_OUT_L-_R

SPK_OUT_L+_R

HDA_3S_SDIN0_R

CS

10UF_6.3V_5

0_5%_6

0.1UF_16V_2

10K_5%_2_DY

CS_1310AXXXXXX-MTR

28

26

21

40

18

29

3

19

41

38

37

11

13

12

24

39

10

22

23

30

9

14

15

6

36

2

1

2

C517

1

2

C513

1

2

1

2

C515

1

2

1

2

C526

1

2

C527

1

2

C528

1

2

C520

1

2

C521

1

2

C518

1

C519

1

2

R511

R508

1

2

1

2

C508

2

C507

1

2

1

C504

1

2

1

2

1

2

C533

1

2

1

2

C506

1

2

R506

1

2

R505

1

2

R504

1

2

R503

1

2

1

C535

1

2

C536

1

2

C537

1

2

1

R509

1

2

C525

1

2

R501

1

2

C529

1UF_6.3V_2

P3V3_A

R513

2

R502 33_5%_2

33_5%_2

2

1

R500

C522

17

16

1

0_5%_2

C532

CSC0402_DY

2

CSC0402_DY

C534

CSC0402_DY

2

0.1UF_16V_2

10UF_6.3V_5

1

C531

C530

2

5

C512

1UF_6.3V_2

1

7

1

0.1UF_16V_2

10UF_6.3V_5

31

32

1

U500

20

0.1UF_16V_2

PCSPKR_PCH_3_R

10UF_6.3V_5

C509

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

PORTC_R

C_BIAS

B_BIAS

PORTB_L

PORTB_R

SENSE_A

GPIO1-SPK_MUTE#

GPIO0-EAPD#

SPDIF

DMIC_CLK

GND

AVEE

PORTA_L

PORTA_R

NC

AVDD_HP

AVDD_3.3

AVDD_5V

FILT_1.65

PORTC_L

FLY_N

FLY_P

DVDD_3.3

CLASS-D_REF

RIGHT+

RPWR_5.0

RIGHT-

LEFT-

LPWR_5.0

LEFT+

PC_BEEP

RESET#

SYNC

VDD_IO

SDATA_IN

BIT_CLK

SDATA_OUT

FILT_1.8

VAUX_3.3

DMIC1-2

AUDIO AMP

INTERNAL SPEAKERS

AUDIO JACKS

Recommended for protection

PORT A

HEADPHONE

PORT C

EXTENAL MICROPHONE

Reserve for EMI, place close to connector

EVEREST-M

97

42

Sun Jan 02 13:17:10 2011

Frank Hu

SINGA_2SJ_T351_019_6P

1

R602

R603

2

5.1_5%_2

PHP_PESD5V2S2UT_SOT23_3P

CSC0402_DY

1

2.2UF_6.3V_2

D602

1

2

CN600

ACES_50224_0040N_001_4P

C604

CSC0402_DY

C607 C605

CSC0402_DY

1

VARISTOR_DY

2

1

D604

2

1

D603

2

1

2

1

D601

2

1

R601

2

1

R600

G2

G1

4

3

2

1

2

C600

2

1

C601

2

1

3

2

1

D600

2

1

C609

C608

2

1

C602

2

1

C603

2

1

R604

2

1

R605

G2

G1

6

5

4

3

2

1

JACK601

G2

G1

6

5

4

3

2

JACK600

2

1

2

1

2

1

C606

2

1

CS_1310AXXXXXX-MTR

VARISTOR_DY

3.3K_5%_2

100_5%_2

VARISTOR_DY

C_BIAS

CSC0402_DY CSC0402_DY

5.1_5%_2

CSC0402_DY

SINGA_2SJ_T351_019_6P

100_5%_2

41>

3.3K_5%_2

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

G1

1

2

3

4

G2

IN

R3500

TPM

6019B0101801

6019B0761601

P/N

(SUPPORT VPRO)

FW VERSION

1.02

15mil

STUFF FOR FW1.2

NC FOR SUPPORT VPRO

TPM1.2

LPCPD# SHOULD BE CONNECT TO VDD

3.16

EVEREST-M

Frank Hu

Fri Dec 31 10:16:39 2010

97

43

2

1

R3500

14

13

5

8

9

27

7

16

28

22

21

17

20

23

26

2

6

15

4

3

25

24

19

18

12

11

10

1

U3500

4

32

1

X3500

2

1

C3500

2

1

C3501

2

1

R3503

2

1

C3503

2

1

C3504

2

1

C3505

2

1

C3502

2

1

R3501

2

1

R3502

A01

P3V3_S

56< 55<

20<

32<>

55<

28<>

30<>

PCI_3S_CLKRUN#

TPM_XTALO

TPM_XTALI

10PF_50V_2

0.1UF_16V_2

10PF_50V_2

32.768KHZ

10M_5%_2

0_5%_2_DY

0.1UF_16V_2

LPC_3S_AD<1>

LPC_3S_AD<0>

37<>

55<

28<>

55<

37<>

LPC_3S_AD<3>

LPC_3S_AD<2>

55<

37<> 28<>

28<>37<>

55<

CLK_PCI_TPM

32>

BUF_PLT_RST#

LPC_3S_FRAME#

28>

37<>

55<

0_5%_2

INFINEON_SLB9635TT1.2_FW3.16_TSSOP_28P

PCI_3S_SERIRQ

37<>

4.7K_5%_2

37<>

P3V3_S

P3V3_A

P3V3_S

0.1UF_16V_2

30<

C

CS_1310AXXXXXX-MTR

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

XTALO

XTALI_32K_IN

VSB

TESTI

TESTBI_BADD

SERIRQ

PP

LRESET#

LPCPD#

LFRAME#

LCLK

LAD3

LAD2

LAD1

LAD0

GPIO2

GPIO

CLKRUN#

GND

NC

GND

VDD

GND

NC

GND

NC

IN

20mil

CPT PANEL

LOW:DISABLE

HI:ENABLE

LCM CONN

40mil

30mil

Place as close as possible to connector

for LED panel

Tue Jan 04 11:07:56 2011

44

EVEREST-M

Frank Hu

97

PCH_LVDS_TXDL2_DP

PCH_LVDS_TXCL_DP

EDP_TX1_DP

R?

1

2

0_5%_2

EDP_TX0_DN

EDP_TX1_DN

R?

1

2

0_5%_2

0_5%_2_DY

2

R?

PCH_LVDS_TXCL_DN

PCH_LVDS_TXDL2_DN

2

1

0_5%_2

R?

1

0_5%_2

2

0_5%_2_DY

3

4

5

6

P3V3_S

2.2K_5%_2

1

R3002

2

PCH_LVDS_DDCCLK

PCH_LVDS_DDCDATA

PCH_LCM_INVPWM

1000PF_50V_2

C3009

0.1uF_25V_3

P3V3_S

2

1

C3005

0.1UF_16V_2

EC_EDP_MUX_IC_SEL

1

EC_BKLTEN

2

3 5

+V3S_PCH_LCM_VDDEN

0.01UF_50V_2

470K_5%_2

SSM3K7002BFU

R3010

1

680pF_50V_2

C3006

KC_FBM_11_160808_101A20T_2P

4.7uF_25V_5

U3000

TC7SZ08FU

+VBAT_LVDS

23

25

26 G2

G1

9

8

7

30

29

28

27

24

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

CN?

ACES_50252_03001_002_30P

2.2K_5%_2

1

C3001

R3000

2

C3010

1

2

AM3423P

4

2

R3009

1

3

Q3001

R3006

1

PCH_LCM_VDDEN

2

1

2

47K_5%_2

P3V3_S

2

1

C3008

2

1

P3V3_S

2

100_5%_2

2

1

C3003

0.1UF_16V_2

2

1

C3004

10uF_6.3V_3

3

3 6

5

2

1

Q3000

2

1

Q3002

SSM3K7002BFU

37>48<

R3005

1

100_5%_2

PCH_LVDS_TXDL0_DP

PCH_LVDS_TXDL1_DP

PCH_LVDS_TXDL1_DN

PCH_LVDS_TXDL0_DN

100K_5%_2

R3004

1

2

CSC0402_DY

C3002

1

2

PVBAT

L3001

1

2

1

2

4 2

0.1UF_16V_2

2

1

C3000

1

2

R?

1

2

R?

0_5%_2_DY

1

R?

2

0_5%_2_DY

1

2

R?

1

2

R?

1

2

0_5%_2_DY

R?

1

0_5%_2_DY

2

R?

P3V3_S

USB_P10_DN

G2

SW_LCM_INVPWM

33_5%_2

R3001

R3003

GPU_LVDS2_TXDL2_DP

2

26

30

GPU_LVDS2_TXCL_DN

1

2

4344

USB_P10_DP

GPU_LVDS2_TXCL_DP

GPU_LVDS2_TXDL1_DP

GPU_LVDS2_TXDL1_DN

SW_LVDS_TXCL_DP

SW_LVDS_TXCL_DN

SW_LVDS_TXDL1_DN

SW_LVDS_DDCDATA

SW_LVDS_TXDL1_DP

67>

+VBAT_LVDS

32<>

ACES_88242_4600_46P

SW_LVDS_DDCCLK

SW_LVDS_TXDL0_DN

40

38

31

0.1UF_16V_2

MIC_IN_DATA

P3V3_S

10K_5%_2_DY

R3008

1

2

10K_5%_2

R3007

1

2

MIC_IN_CLK

44<41>

P3V3_S

CN3000

1

3

USB_P10_DP

USB_P10_DN

5

VARISTOR_DY

MIC_IN_CLK

41>44<

20

C3007

1

44<

G1

9

8 7

6 5

46 45

42

41

4

39

37

36 35

34 33

32

3

29

28 27

25

24 23

22

21

2

19

18 17

16 15

12 11

10

67>

P5V_S

NXP_IP4223CZ6_SOT457_6P_DY

2

1

D3001

2

1

D3000

2

1

4

6

1

2

U3001

CS_1310AXXXXXX-MTR

MIC_IN_DATA

VARISTOR_DY

41>44<

44<

32<>

44<

32<>

C

A01

CS

SW_LVDS_TXDL2_DN

SW_LVDS_TXDL2_DP

GPU_LVDS2_TXDL0_DN

GPU_LVDS2_TXDL0_DP

GPU_LVDS2_TXDL2_DN

100_5%_2

SW_LVDS_TXDL0_DP

1314

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

G

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

IN

IN IN

IN

BI

IN

+

-

IN

G

DS

G

DS

S

PMOS_4D1S

G

D

VIO

VBUSGND

VIO

IN

3

44

23

19

17

15

11

1

G1

14

4

2

36

5

7

9

13

21

25

27

29

31

33

35

37

39

41

43

45

6

8

10

12

16

18

20

22

24

26

28

30

32

34

38

40

42

46

G2

CRT CONN

(40 MILS)

CO-LAYOUT

FOLLOW INTEL DESIGN GUIDE

Frank Hu

EVEREST-M

Fri Dec 31 10:17:01 2010

97

45

2

1

C3056

2

1

C3057

2

1

C3060

2

1

C3061

2

1

C3062

2

1

C3050

2

1

C3051

2

1

C3052

2

1

C3063

2

1

C3064

2

1

C3065

2

1

R3059

2

1

R3060

2

1

R3061

2

1

R3054

2

1

R3053

2

1

R3052

2

1

L3050

2

1

L3051

2

1

L3052

2

1

R3071

2

1

R3072

2

1

R3075

2

1

R3073

2

1

R3074

2

1

R3076

2

1

R3077

2

1

R3064

2

1

R3065

2

1

R3066

2

1

R3067

2

1

R3068

2

1

R3069

2

1

R3070

2

1

FUSE3050

2

1

C3053

2

1

C3054

2

1

C3055

2

1

R3062

2

1

R3063

2

1

R3050

2

1

R3051

1

16

15

98

7

6

5

4

3

2

14

13

12

11

10

U3050

2

1

D3050

2

1

R3058

2

1

R3057

2

1

R3055

2

1

R3056

2

1

C3058

2

1

C3059

G2

G1

9

8

7

6

5

4

3

2

15

14

13

12

11

10

1

CN3050

A01

CS_1310AXXXXXX-MTR

SYN_070546FR015S251ZR_15P

22PF_50V_2

LOW18ANR12G00BD

45>

10PF_50V_2

CRT_DDCCLK_R

CRT_DDCDATA_R

CRT_HSYNC_CN

45<

P5V_S

45<

CRT_R_CN

CRT_G_CN

CRT_B_CN

+V5S_CRTCONNPWR_FUSE

CRT_VSYNC_CN

CRT_HSYNC_CN

45>

33_5%_2

12PF_50V_2_DY 12PF_50V_2_DY

CRT_R_CN

CRT_G_CN

CRT_B_CN

CRT_VSYNC_R

CRT_VSYNC

CRT_DDCCLK_R

CRT_HSYNC_R

CRT_HSYNC

CRT_DDCDATA_R

GPU_CRT_DDCCLK

GPU_CRT_DDCDATA

GPU_CRT_HSYNC

GPU_CRT_VSYNC

GPU_CRT_R

GPU_CRT_G

GPU_CRT_B

PCH_CRT_DDCDATA

PCH_CRT_DDCCLK

CRT_DDCCLK

CRT_DDCDATA

CRT_VSYNC_CN

CRT_DDCCLK

CRT_DDCDATA

PCH_CRT_BLUE

PCH_CRT_HSYNC

PCH_CRT_VSYNC

PCH_CRT_GREEN

PCH_CRT_RED

CRT_HSYNC

CRT_VSYNC

CRT_B

CRT_G

CRT_R

CRT_B

CRT_G

CRT_R

+V5S_CRTCONNPWR_D

CRT_DDCCLK_CN

CRT_DDCDATA_CN

CRT_G_L

CRT_R_L

CRT_B_L

CRT_G_CN

CRT_B_CN

CRT_R_CN

0.22UF_6.3V_2 0.22UF_6.3V_2 0.22UF_6.3V_2

45>

45<

45< 45>

45>

45<

TI_TPD7S019_15DBQR_SSOP_16P

P5V_S

P3V3_S

P5V_S

71>

0_5%_2_DY

71>

31>

0_5%_2_DY

0_5%_2

45<>

2.2K_5%_2 2.2K_5%_2

33_5%_2

45>

45<>

45>

33_5%_2

45<

45>

45<

P3V3_S

150_1%_2

31>

0_5%_2

45<

45>

2.2K_5%_2 2.2K_5%_2

P5V_S

SBR3U40P1

1A_32V_0467001

150_1%_2 150_1%_2

10PF_50V_2

10PF_50V_2 22PF_50V_2

0.1UF_10V_2_DY 0.1UF_10V_2_DY

45>

45>45<

45>

22PF_50V_2

10PF_50V_2 10PF_50V_2 10PF_50V_2

LOW18ANR12G00BD

0_5%_2

45<

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

BI

OUT

IN

OUT

IN

OUT

VCC-SYNC SYNC_OUT2

SYNC_IN2

DDC_OUT1

BYP

VCC-DCC

GND

VIDEO_3

VIDEO_2

VIDEO_1

VCC-VIDEO

SYNC_OUT1

SYNC_IN1

DCC_OUT2

DDC_IN2

DDC_IN1

IN

G2

G1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CLOSE TO CONNECTOR

HDMI CONN

40MIL

CLOSE TO CONNECTOR

Fri Dec 31 10:16:40 2010

Frank Hu

EVEREST-M

97

46

2

1

D3156

2

1

C3151

2

1

R3164

2

1

R3160

1

TP3150

2

1

R3175

2

1

R3174

2

1

R3159

2

1

R3161

2

1

R3162

S

G

D

Q3150

S

G

D

Q3151

8

6

7

9

10

5

4

2

1

3

D3155

8

6

7

9

10

5

4

2

1

3

D3154

2

1

R3173

2

1

R3172

2

1

R3171

2

1

R3170

2

1

R3169

2

1

R3168

2

1

R3167

2

1

R3165

2

1

3

Q3152

2

1

R3166

2

1

R3151

2

1

C3158

2

1

C3159

2

1

C3156

2

1

C3157

2

1

C3154

2

1

C3155

2

1

C3152

2

1

C3153

2

1

R3157

2

1

R3156

2

1

R3155

2

1

R3154

2

1

R3153

2

1

R3152

2

1

R3150

2

1

C3150

2

1

R3163

2

1

D3152

2

1

D3151

2

1

D3150

2

1

D3153

2

1

R3158

2

1

FUSE3150

2

3

1

5

6

4

8

9

7

11

12

10

14

19

G4

G3

G2

G1

16

15

17

13

18

CN3150

HDMI_CN_DDCCLK

4.7K_5%_2

GPU_HDMI_TX0_R_DN

GPU_HDMI_TX0_R_DP

P3V3_GPUS

1M_5%_2

499_1%_2

0_5%_2

4.7K_5%_2

33_5%_2

SBR3U40P1

1K_5%_2

VARISTOR_DY

22PF_50V_2_DY

CS_1310AXXXXXX-MTR

GPU_HDMI_DDCDATA

GPU_HDMI_DDCCLK

GPU_HDMI_TXC_DP

GPU_HDMI_TXC_DN

GPU_HDMI_TX0_DN

GPU_HDMI_TX0_DP

GPU_HDMI_TX1_DN

GPU_HDMI_TX1_DP

GPU_HDMI_TX2_DN

HDMI_CN_DDCDATA

GPU_HDMI_TX2_DP

GPU_HDMI_HPDET

GPU_HDMI_TXC_R_DN

GPU_HDMI_TXC_R_DP

GPU_HDMI_TX1_R_DN

GPU_HDMI_TX1_R_DP

GPU_HDMI_TX2_R_DN

HDMI_CN_DDCDATA

HDMI_CN_DDCCLK

+V5LA_HDMI_CONNPWR

GPU_HDMI_TX2_R_DP

GPU_HDMI_TXC_C_DN

GPU_HDMI_TXC_C_DP

GPU_HDMI_TX1_C_DN

GPU_HDMI_TX1_C_DP

GPU_HDMI_TX2_C_DN

GPU_HDMI_TX0_C_DP

GPU_HDMI_TX0_C_DN

GPU_HDMI_TX2_C_DP

71<>

33_5%_2

71<>

4.7K_5%_2

71>

0.1UF_16V_2

SSM3K17FU

4.7K_5%_2

SSM3K17FU

P3V3_GPUS

46<>

0_5%_2_DY

+V5S_HDMI

SEM_0544M_MSOP_10P_DY

P5V_S

71>

SSM3K7002BFU

0.1UF_16V_2

499_1%_2

SEM_0544M_MSOP_10P_DY

100PF_50V_2

71<

100K_5%_2

VARISTOR_DY

SBR3U40P1

+V5S_HDMI

0_5%_2

46<>

VARISTOR_DY

1A_32V_0467001

TP35

SYN_100042MR019M153ZL_19P

0_5%_2

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

BI

G

DS

G

DS

NC

VCC

NC

LINE4

LINE3

GND

LINE2

LINE1

NC

VCC

NC

LINE4

LINE3

GND

LINE2

LINE1

BI

G

DS

IN

BI

IN

G4

G3

G2

G1

HOT-PLUG-DETECT

+5V-POWER

DDC-CEC-GND

DDC-DATA

DDC-CLOCK

RESERVED

CEC

TMDS-CLOCK-

TMDS-CLOCK-SHIELD

TMDS-CLOCK+

TMDS-DATA0-

TMDS-DATA0-SHIELD

TMDS-DATA0+

TMDS-DATA1-

TMDS-DATA1-SHIELD

TMDS-DATA1+

TMDS-DATA2-

TMDS-DATA2-SHIELD

TMDS-DATA2+

PCH Dual-mode

40mil

DP CONN

PIN 14 :DDC buffer ID

distinguish from HDMI &DVI Adapter

EVEREST-M

47

97

Fri Dec 31 10:16:41 2010

Frank Hu

G4

G3

G2

G1

9

8

7

6

5

4

3

20

2

19

18

17

16

15

14

13

12

11

10

1

CN3300

2

1

D3300

S

G

D

Q3300

2

1

3

Q3302

2

1

R3305

2

1

3

Q3303

2

1

R3306

2

1

R3302

2

1

R3304

S

G

D

Q3304

S

G

D

Q3308

2

1

R3303

2

1

R3301

S

G

D

Q3305

S

G

D

Q3309

2

1

C3300

S

G

D

Q3306

S

G

D

Q3310

2

1

C3301

S

G

D

Q3307

S

G

D

Q3301

2

1

C3309

2

1

C3308

2

1

C3307

2

1

C3306

2

1

C3305

2

1

C3304

2

1

C3303

2

1

C3302

2

1

R3307

2

1

FUSE3300

2

1

R3300

2

1

R3308

2

1

R3309

DDCDATA_AUXN_CN

PCH_DUAL_DDCDATA_M

PCH_DUAL_DDCCLK_M

PCH_DP_AUX_M_DP

PCH_DP_HPD_CN

P3V3_S

DDCCLK_AUXP_CN

DDCDATA_AUXN_CN

PCH_DP_HPD_CN

1A_32V_0467001

100K_5%_2

P3V3_S

SSM3K17FU

10K_5%_2

CS_1310AXXXXXX-MTR

+V3S_DPCONNPWR_FUSE

DDC_AUX_EN#

+V3S_DPCONNPWR_D

DDCCLK_AUXP_CN

PCH_DP_LANE1_DP PCH_DP_LANE1_C_DP

PCH_DP_LANE0_DN PCH_DP_LANE0_C_DN

PCH_DP_LANE0_DP PCH_DP_LANE0_C_DP

PCH_DP_LANE1_DN PCH_DP_LANE1_C_DN

PCH_DP_LANE2_DP PCH_DP_LANE2_C_DP

PCH_DP_LANE3_DP PCH_DP_LANE3_C_DP

PCH_DP_LANE2_DN PCH_DP_LANE2_C_DN

PCH_DP_LANE3_DN PCH_DP_LANE3_C_DN

PCH_DP_AUX_M_DN

PCH_DP_HPD

PCH_DP_AUX_C_DP

PCH_DP_AUX_C_DN

PCH_DP_AUX_DP

PCH_DP_AUX_DN

PCH_DUAL_DDCCLK

PCH_DUAL_DDCDATA

MLX_105020_6001_20P

0_5%_2

5.1M_5%_2

47>

1M_5%_2

DDC_AUX_EN#

SBR3U40P1

P5V_S

10K_5%_2

SSM3K7002BFU

47<>

100K_5%_2

0.1UF_16V_2

SSM3K17FU

P5V_S

SSM3K17FU

31<

0.1UF_16V_2

P3V3_S

0.1UF_16V_2

2.2K_5%_2

P3V3_S

2.2K_5%_2

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

G4

G3

G2

G1

9

8

7

6

5

4

3

20

2

19

18

17

16

15

14

13

12

11

10

1

OUT

IN

G

DS

IN

G

DS

G

DS

BI

G

DS

G

D S

BIBI

G

DS

G

D S

BI

G

D S

G

DS

BI

G

D S

G

DS

IN

OUT

BI

OUT

40mil

EDP CONN

40mil

EVEREST-M

Frank Hu

Tue Jan 04 11:08:43 2011

97

48

R3360

100K_5%_2_DY

R3359

100K_5%_2_DY

0.1UF_16V_2

C3360

0.1UF_16V_2

C3361

1

2

R3357

C3350

1

TC7SZ08FU

100_5%_2

21>

EC_BKLTEN

PCH_LCM_BKLTEN

15

17

23

ACES_87216_2406_24P

10

12

1

EDP_TX0_C_DN

EDP_TX0_C_DP

32

0.1UF_16V_2

Q3351

+V3S_eDPCONNPWR

100_5%_2

P3V3_S

0.1UF_16V_2

14

EDP_HPD#_CN

EDP_TX0_DP

U3350

5

2

R3350

680pF_50V_2

EDP_TX0_DN

0.1UF_16V_2

AM3423P

2

1

C3359

2

1

R3356

2

1

R3355

2

1

3

Q3353

2

1

2

1

2

1

R3358

2

1

2

1

3

2

1

3

Q3352

2

1

R3354

2

1

C3358

2

1

R3353

4

3 6

5

2

1

Q3350

1

2

1

L3350

2

1

C3355

2

1

C3353

1

4

3

2

1

2

R3351

2

1

C3356

2

1

R3352

2

1

C3357

2

1

C3352

1

C3351

2

1

C3354

G2

G1

987 65 4

24

22

21

20

19 18

16

13

11

CN3350

100K_5%_2

PCH_LCM_INVPWM

EDP_AUX_C_DN

0.01UF_50V_2

SSM3K7002BFU

P3V3_S

EDP_HPD#_CN

A01

EDP_AUX_DN

EDP_AUX_DP

PCH_LCM_VDDEN

EDP_AUX_C_DN

EDP_AUX_C_DP

EDP_HPD#

+VBAT_eDP

21<>

SSM3K7002BFU

100K_5%_2_DY

48>

100K_5%_2_DY

PVBAT

KC_FBM_11_160808_101A20T_2P

37>44<

100K_5%_2

21>

47K_5%_2

P3V3_S

470K_5%_2

P3V3_S

4.7uF_25V_5 0.1uF_25V_3

CSC0402_DY

10uF_6.3V_3 0.1UF_16V_2

SSM3K7002BFU

1K_5%_2

21<

48<

P1V05_VCCPS

CS

CS_1310AXXXXXX-MTR

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

OUT

G

DS

BI

IN

OUT

IN

BI

IN

G

DS

G

D S

S

PMOS_4D1S

G

D

OUT

IN

+

-

OUT

G2

24

22

20

19

18

17

16

14

12

11

10

9

87

5

3

2

1

23

21

4

6

G1

15

13

CARDREADER/USB CONNECTOR

30mil

DB CONN USB & CARDREADER

1.5A

EVEREST-M

49

97

Fri Dec 31 10:17:02 2010

Frank Hu

G2

G1

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

CN255

CS_1310AXXXXXX-MTR

ACES_50503_0184N_001_18P

P5V_A

A01

LED_3IN1

USB_OC#_1

USB_P8_DN

USB_P8_DP

USB_P2_DN

USB_P2_DP

USB_P1_DN

USB_P1_DP

USB1_PWREN

58<

32<

32<>

P3V3_S

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

18

17

16

15

14

13

12

11

G2

10

9

8

7

6

5

4

3

2

1

G1

CLOSE TO SATA CONN

40MILS

SATA HDD

SATA SSD

SATA HDD/SSD & ODD CONN

CLOSE TO SATA CONN

1.1A

SATA ODD

EVEREST-M

50

Frank Hu

97

Sun Jan 02 18:54:06 2011

2

1

R1750

2

1

C1756

2

1

C1757

2

1

C1755

2

1

C1754

2

1

D1751

2

1

D1753

2

1

D1750

2

1

D1752

2

1

C1753

2

1

R1753

2

1

3

Q1751

2

1

R1751

2

1

R1752

43

652

1

Q1750

2

1

C1750

2

1

C1751

2

1

C1752

P4

S1

S4

S7

P5

P6

G2

G1

P1

S5

S6

S3

S2

P2

P3

CN1750

2

1

C1900

2

1

C1901

2

1

C1902

2

1

R1900

2

1

C1905

2

1

C1906

2

1

C1903

2

1

C1904

G2

G1

9

8

7

6

5

4

3

2

16

15

14

13

12

11

10

1

CN1900

2

1

C1706

2

1

C1700

2

1

C1701

2

1

D1702

2

1

D1701

2

1

D1703

2

1

D1700

2

1

C1703

2

1

C1702

2

1

C1705

2

1

C1704

2

1

R1700

16

15

14

10

9

8

22

21

20

18

19

17

13

12

11

7

4

1

G2

G1

5

6

3

2

CN1700

SATA_HDD_RX_DN

SATA_HDD_RX_DP

SATA_HDD_TX_DN

SATA_HDD_TX_DP

SATA_HDD_RX_C_DP

SATA_HDD_RX_C_DN

SATA_HDD_TX_C_DN

SATA_HDD_TX_C_DP

+V3S_SATAHDDCONN

22UF_6.3V_5

28<

28>

0.01UF_50V_2

VARISTOR_DY VARISTOR_DY

VARISTOR_DY

22UF_6.3V_5 0.1UF_16V_2

P5V_S

VARISTOR_DY

RSC_0603_DY

P3V3_S

0.01UF_50V_2

SYN_127043HR022M22SZR_22P

SATA_ODD_PRSNT#

33>

32<

SATA_SSD_TX_C_DP

P3V3_S

22UF_6.3V_5

SATA_SSD_RX_DP

28<

SATA_SSD_TX_DN

SATA_SSD_TX_DP

A01

SATA_ODD_TX_DP

SATA_ODD_TX_DN

SATA_ODD_RX_DN

SATA_ODD_RX_DP

SATA_ODD_PWREN

SATA_ODD_DA# SATA_ODD_R_DA#

SATA_ODD_TX_C_DP

SATA_ODD_TX_C_DN

SATA_ODD_RX_C_DN

SATA_ODD_RX_C_DP

SATA_SSD_RX_DN

SATA_SSD_RX_C_DP

SATA_SSD_TX_C_DN

SATA_SSD_RX_C_DN

+V3S_SATASSDCONN

+V5S_SATAODDCONN_MOS

28>

0.01UF_50V_2

28<

0.01UF_50V_2

10K_5%_2

SSM3K7002BFU

P3V3_S

1M_5%_2

P5V_S

VARISTOR_DY VARISTOR_DY VARISTOR_DY VARISTOR_DY

32<>

1M_5%_2

1000PF_50V_2

AM3423P

0_5%_2

10UF_6.3V_3

1UF_6.3V_2 1UF_6.3V_2

SYN_127382FR013G503ZR_13P

28<

28>

0.01UF_50V_2

22UF_6.3V_5 0.1UF_16V_2

P5V_S

0.01UF_50V_2

ACES_88501_1601_16P

RSC_0603_DY

C

CS

CS_1310AXXXXXX-MTR

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

G

DS

S

PMOS_4D1S

G

D

G2

G1

GND

A+

A-

GND

B-

B+

GND

DP

+5V

MD

GND

OUT

IN

16

15

14

13

G

12

11

10

9

8

7

6

5

4

3

2

1

OUT

IN

RESERVED

G2

G1

V12

V5

V3.3

B+

B-

A-

A+

GND

E-SATA CONN

CLOSE TO IC PINS

40MIL

FUNCTION

DEFAULT

STANDBY

CH0,1->5DB

CH1->5DB

CH0->5DB

0

X

D1

D0

X

0

1

0

1

0

EN

0

1

E-SATA

51

97

Fri Dec 31 10:16:42 2010

EVEREST-M

Frank Hu

2

1

C1800

2

1

C1801

2

1

C1804

2

1

C1805

2

1

D1800

2

1

D1802

2

1

D1803

2

1

D1801

2

1

34

L1800

1

3

2 6

7

10

9

G4

G3

G2

G1

8

5

4

11

CN1800

2

1

C1806

2

1

C1807

2

1

C1808

2

1

C1809

2

1

C1802

2

1

C1803

2

1

C1810

2

1

C1811

2

1

R1800

2

1

R1801

2

1

R1802

2

1

R1803

2

1

R1804

20

16 10

6

5

4

15

14

21

11

12

1

2

19

18

17

13

3

7

8

9

U1800

REDRIVER_ESATA_TX_DN

REDRIVER_ESATA_TX_DP

0.1UF_16V_2

0.01UF_50V_2

51<

A01

USB_P0_DP

USB_P0_DN USB_P0_L_DN

REDRIVER_ESATA_RX_C_DP

USB_P0_L_DP

REDRIVER_ESATA_TX_C_DP

REDRIVER_ESATA_TX_C_DN

REDRIVER_ESATA_RX_C_DN

REDRIVER_ESATA_RX_DN

REDRIVER_ESATA_RX_DP

SATA_ESATA_TX_DP

SATA_ESATA_TX_DN SATA_ESATA_TX_C_DN

SATA_ESATA_TX_C_DP

REDRIVER_ESATA_RX_DP

REDRIVER_ESATA_RX_DN

REDRIVER_ESATA_TX_DP

REDRIVER_ESATA_TX_DN

SATA_ESATA_RX_DP

SATA_ESATA_RX_C_DP

SATA_ESATA_RX_DN

SATA_ESATA_RX_C_DN

32<>

WCM_2012_900T

+USB_VCC0

P3V3_S

1UF_6.3V_2 1UF_6.3V_2

0.1UF_16V_2

VARISTOR_DY

TWIN_EU103_117CRL_TW_11P

VARISTOR_DY VARISTOR_DY VARISTOR_DY

P3V3_S

51>

TI_SN75LVCP412RTJR_QFN_20P

28>

0.01UF_50V_2

51<

51>

RSC_0402_DY

4.7K_5%_2 4.7K_5%_2

P3V3_S

4.7K_5%_2

4.7K_5%_2_DY

0.01UF_50V_2

28<

CS

CS_1310AXXXXXX-MTR

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

OUT

BI

VCC

USB_P

USB_N

TXP

TXN

RXP

RXN

G4

G3

G2

G1

GND

OUT

IN

TML

VCC

GND

VCC

TX_0P

TX_0N

GND

RX_1N

RX_1P

VCC

D0

D1

EN

VCC

TX_1P

TX_1N

GND

RX_0N

RX_0P

CLOSE TO ESATA CONNECTOR

40MIL

ESATA POWER

USB CONN

Frank Hu

EVEREST-M

Sun Jan 02 18:04:58 2011

97

52

P3V3_AL

10K_5%_2

USB_OC#_1

2

1

PAD1800

2

1

R1806

2

1

R1805

2

1

C1812

2

1

C1813

2

1

C1814

2

1

C1815

8

7

6

5

3

2

1

4

U1801

0.01UF_50V_2

POWERPAD1X1M

USB0_PWREN

+V5A_ESATAPWR_IN

37>

P5V_A

0.1UF_16V_2

GMT_G547G1P81U_MSOP_8P

22UF_6.3V_5 0.1UF_16V_2 RSC_0402_DY

+USB_VCC0

CS_1310AXXXXXX-MTR

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

1

2

OUT

IN

OUT

OC#EN

IN

GND

PUT ON BOTTOM SIDE

14" KEYBOARD

25mil

K/B & TP/B CONN

14" TOUCH PAD

53

97

Fri Dec 31 10:16:43 2010

EVEREST-M

Frank Hu

2

1

D256

2

1

D255

2

1

D254

2

1

D253

2

1

D252

2

1

D251

2

1

D250

2

1

D262

2

1

C252

2

1

C250

G2

G1

6

5

4

3

2

1

CN250

2

1

D200

G2

G1

2

1

CN200

2

1

R254

2

1

D258

2

1

D259

2

1

D260

2

1

R251

2

1

R252

2

1

R253

6

5

4

3

2

1

SW200

G2

G1

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

CN251

CSC0402_DY

SCAN_IN<2>

37<

TP_ON#

NUM_LED#_3

SCROLL_LED#_3

CAPS_LED#_3

IM_DAT_5

IM_CLK_5

SCAN_OUT<3>

SCAN_OUT<7>

SCAN_OUT<12>

SCAN_OUT<8>

SCAN_OUT<14>

SCAN_OUT<10>

SCAN_OUT<5>

SCAN_OUT<6>

SCAN_OUT<9>

SCAN_OUT<11>

SCAN_OUT<0>

SCAN_OUT<1>

SCAN_OUT<17..0>

SCAN_OUT<15>

SCAN_OUT<13>

SCAN_OUT<4>

SCAN_OUT<2>

SCAN_OUT<17>

SCAN_OUT<16>

PWR_SWIN#_3

SCAN_IN<5>

SCAN_IN<6>

SCAN_IN<1>

SCAN_IN<0>

SCAN_IN<7>

SCAN_IN<2>

SCAN_IN<3>

SCAN_IN<4>

SCAN_IN<7>

SCAN_IN<4>

SCAN_IN<6>

SCAN_IN<5>

SCAN_IN<3>

SCAN_IN<0>

SCAN_IN<1>

ACES_88502_060N_6P

37>

CSC0402_DY

P5V_S

37<>

200_5%_2

EZJZ0V120JA_DY EZJZ0V120JA_DY EZJZ0V120JA_DY

3

7

12

8

14

10

5

6

9

11

0

1

15

13

4

2

17

16

0_5%_2

MISAKI_NTC017_DA1G_E160T_6P

ENTERY_3703_Q02N_03R_2P

VARISTOR_DY

53>

53< 37<

37<53<

53< 37<

PTWO_AFF340_A2G1V_P _34P

53< 37<

37<53<

53< 37<

37<

53<

37<

53<

37<

53<

37<

53<

37<

53<

37<

53<

EZJZ0V120JA_DY

P3V3_S

53<

37<

EZJZ0V120JA_DY

C

CS_1310AXXXXXX-MTR

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

BI

IN

G

1

2

3

4

5

6

G

OUT

IN

G1

2

1

G2

IN

OUT

IN

OUT

A

B

DC

IN

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

G1

G2

20MIL

ALWAYS STUFF

BLUETOOTH CONN

GND

CH_CLK

CH_DATA#

RST#

GND

2

4

6

8

10

1

3

5

7

9

USB_N

USB_P

BTMDL

VCC

DISABLE

BLUETOOTH

Frank Hu

EVEREST-M

Fri Dec 31 10:17:02 2010

97

54

2

1

R2105

2

1

C2100

2

1

C2104

G2

G1

6

5

4

3

2

1

CN2100

22UF_6.3V_5

P3V3_S

ACES_87213_0600N_6P

CS_1310AXXXXXX-MTR

BTMDL#

BTIFON#

USB_P12_DN

USB_P12_DP

32<>

55> 37>

32<>

100K_5%_2

P3V3_S

0.1UF_16V_2

C

CS A01

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

BI

3

2

1

G

4

5

6

G

25mil

375mA

1,100mA

500mA

2,750mA

MINI CARD 1

MINI1 WLAN/DEBUG CARD

1.5V

3.3V

Peak(max)mA Normal(max)mA

Note:

2.7A

SUPPORT IAMT NEED +V3A

Wireless & Debug card

EVEREST-M

Frank Hu

Fri Dec 31 10:16:43 2010

97

55

2

1

3

Q1300

2

1

R1302

2

1

R1303

2

1

C1301

2

1

C1304

2

1

C1303

2

1

C1305

2

1

C1306

2

1

C1302

2

1

3

Q1301

2

1

R1301

2

1

R1300

1

36

38

32

30

45

43

41

39

37

19

17

5

20

16

14

12

10

8

51

49

47

3

11

13

33

31

22

25

23

42

46

44

26

18

4

35

29

27

21

15

50

40

34

9

G2

G1

7

24

52

2

48

28

6

CN1300

0.1UF_16V_2 0.1UF_16V_2

LPC_3S_FRAME#

LPC_3S_AD<2>

LPC_3S_AD<0>

WXMIT_OFF#

0_5%_2

USB_P5_DN

USB_P5_DP

WIMAX_LED#

BTIFON#

BUF_PLT_RST#

LPC_3S_AD<1>

LPC_3S_AD<3>

PCI_3S_SERIRQ

CL_RST#

CL_DATA

CL_CLK

PCIE_WLAN_TX_DP

PCIE_WLAN_TX_DN

PCIE_WLAN_RX_DP

PCIE_WLAN_RX_DN

CLK_PCI_DEBUG

BUF_PLT_RST#

CLK_PCIE_WLAN_DP

CLK_PCIE_WLAN_DN

CLKREQ_WLAN#

PCIE_WAKE#

PCH_3A_SMDATA

PCH_3A_SMCLK

WXMIT_OFF#

WLON#

37>

54<>

SSM3K7002FU_DY

0_5%_2

BELLW_80051_1021_52P

29>

56<

20<

32<>

43<55<

30<

0_5%_2

22uF_6.3V_5 0.1UF_16V_2

32<>

0_5%_2

55<

20<

32<>

43<

56<

55>

43<

28<> 37<>

0.1UF_16V_2

43<

28<> 37<>

43<

37<>28<>

43<

37<>28<>

28>

37<>

43<

29<>

22uF_6.3V_5

P3V3_S

P1V5_S

SSM3K7002BFU

37>

C

CS A01

CS_1310AXXXXXX-MTR

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

G

DS

OUT

IN

G

DS

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

GG

3.3V

GND

1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

1.5V

GND

+3.3VAUX

PERST#

RESERVED

GND

RESERVED

1.5V

GND

3.3V

RESERVED

GND

PETP0

PETN0

GND

PERP0

PERN0

GND

RESERVED

GND

REFCLK+

REFCLK-

GND

CLKREQ#

RESERVED

WAKE#

MINI2 3G

25mil

MINI CARD 2

3G/GPS

1A

CLOSE TO SIM CONNECTOR

EVEREST-M

97

56

Fri Dec 31 10:17:03 2010

Frank Hu

2

1

C1404

2

1

3

Q1401

2

1

C1403

4

6

3

1

52

U1402

P6

P1

P2

P7

P5

G2

G1

P3

CN1400

2

1

C1405

2

1

C1406

2

1

C1407

2

1

C1402

2

1

C1401

2

1

C1400

1

36

38

32

30

45

43

41

39

37

19

17

5

20

16

14

12

10

8

51

49

47

3

11

13

33

31

22

25

23

42

46

44

26

18

4

35

29

27

21

15

50

40

34

9

G2

G1

7

24

52

2

48

28

6

CN1401

BELLW_80051_1021_52P

0.1UF_16V_2

22uF_6.3V_522uF_6.3V_5

UIM_PWR

UIM_DATA

UIM_RST

A01

CS_1310AXXXXXX-MTR

P3V3_S

USB_P13_DP

USB_P13_DN

BUF_PLT_RST#

3G_OFF#

UIM_CLK

UIM_DATA UIM_RST

UIM_CLK

UIM_PWR

3G_ON#

3G_OFF#

P3V3_S

0.1UF_16V_2

32<>

56>

32<>

43< 55<20<

56<>

0.1UF_16V_2

P1V5_S

0.1UF_16V_2

TAI_PMPAT5_06GLBS7N14_6P

NXP_IP4223CZ6_SOT457_6P_DY

4.7uF_6.3V_3 0.1UF_16V_2

56<>

SSM3K7002BFU

37>

56<

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

IN

OUT

IN

G

DS

BI

VIO

VBUS

GND

VIO

VIO VIO

G

I_O

VPP

VCC

RST

CLK

G

GND

GG

3.3V

GND

1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

1.5V

GND

+3.3VAUX

PERST#

RESERVED

GND

RESERVED

1.5V

GND

3.3V

RESERVED

GND

PETP0

PETN0

GND

PERP0

PERN0

GND

RESERVED

GND

REFCLK+

REFCLK-

GND

CLKREQ#

RESERVED

WAKE#

BI

HALL SENSOR

15mil

HALL SENSOR

Frank Hu

EVEREST-M

Fri Dec 31 10:17:03 2010

97

57

2

1

L50

2

1

C50

2

1

R52

1

2

3

U50

LID_SW#_3

MAG_MH248BESO_SOT23_3P

1000PF_50V_2

100K_5%_2

VARISTOR_DY

37<

P3V3_AL

C

A01

CS

CS_1310AXXXXXX-MTR

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

GND

OUT

VDD

BATTERY LED

LED

WIMAX LED

Wireless & BT LED

CARD READER LED

POWER LED

Suspend LED

DC-IN LED

HDD LED

EVEREST-M

Frank Hu

Fri Dec 31 10:16:44 2010

97

58

2

1

C149

5

4

3

2

1

U191

2

1

C156

2

1

D153

2

1

R156

5

4

3

2

1

U150

2

1

C151

2

1

R153

2

1

D151

2

1

C152

2

1

R152

2

1

D152

2

1

D150

2

1

R151

2

1

C153

2

1

R150

2

1

D159

2

1

C154

2

1

C150

2

1

D155

2

1

R154

2

1

C159

2

1

D154

2

1

R160

2

1

C155

2

1

R155

2

1

D156

TC7SZ08FU

P5V_S

CSC0402_DY

LED_3IN1

CS_1310AXXXXXX-MTR

DCIN_BLED#

PWR_BLED#

SUS_OLED#

WL_OLED#

BAT_OLED#

BAT_BLED1#

LED_3S_SATA#

72<>

37>

CSC0402_DY

TC7SZ08FU

CSC0402_DY

37>

37<

P5V_S

CSC0402_DY

19_217_T1D_CP1Q2QY_3T

CSC0402_DY

HT_191UY

19_217_T1D_CP1Q2QY_3T 220_5%_2

19_217_T1D_CP1Q2QY_3T

P5V_A

220_5%_2

P5V_S

220_5%_2

150_5%_2

P5V_S

P3V3_A

49>

CSC0402_DY

0.1UF_16V_2

19_217_T1D_CP1Q2QY_3T

37>

CSC0402_DY

HT_191UY

220_5%_2

P5V_S

150_5%_2

P3V3_S

CSC0402_DY

19_217_T1D_CP1Q2QY_3T 220_5%_2

P3V3_AL

P5V_A

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

+

-

IN

+

-

IN

30PPM

15mil

Layout note: All decoupling 0.1uF disperse closed to pin

CLOSE TO IC PIN15,18

Please place close to CLKGEN within 500mils

CLOCK GENERATOR

EVEREST-M

Frank Hu

Tue Jan 04 00:18:17 2011

97

59

CLKIN_BUF_DOT96_DP

CLKIN_BUF_DOT96_DN

CLKIN_SATA1_DP

1

R4013

R4012

2

33_5%_2_DY

2

33_5%_2_DY

2

1

R4000

2

1

R4008

2

1

R4009

2

1

R4010

2

1

R4011

2

1

R4002

2

1

R4004

2

1

R4003

2

1

C4011

5

4

3

2

1

U4001

2

1

R4001

2

1

R4014

2

1

R4015

2

1

R4016

2

1

R4017

2

1

R4005

2

1

R4006

2

1

R4007

2

1

C4003

2

1

C4004

2

1

X4000

2

1

L4001

2

1

C4010

2

1

C4009

2

1

C4008

2

1

C4007

2

1

C4005

2

1

C4006

2

1

L4000

2

1

C4002

2

1

C4000

2

1

C4001

27

28

15 17

29

1

18

24

5

13

14

31

32

10

11

30

12

9

26

2

21

8

33

3

4

20

23

19

22

16

25

7

6

U4000

IDT_ICS9LRS3197AKLFT_MLF_32P

0.1UF_16V_20.1UF_16V_2

10uF_6.3V_3

FBM_11_160808_121T

10uF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

FBM_11_160808_121T

14.31818MHz

33pF_50V_2 33pF_50V_2

+V3S_CLK_VDD

P3V3_S

P1V05_VCCPS +V1.05S_VCCP_VDD

P3V3_S

P3V3_A

CLK_R3S_PCH14_R

10K_5%_2_DY

PCH_3S_SMDATA

CLKIN_PCH14

60<

CKG_X1

A01

0_5%_2_DY

PCH_3S_SMCLK

59>

CLKOUT_DMI_CLKGEN_DN

CLKOUT_DMI_CLKGEN_DP

CS_1310AXXXXXX-MTR

CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_SATA1_DN

CLKIN_DMI_PCH_R_DN

CLKIN_DMI_PCH_R_DP

CLK_SATA1_R_DN

CLK_SATA1_R_DP

CLK_BUF_DOT96_R_DN

CLK_BUF_DOT96_R_DP

CLK_BUF_CPYCLK_R_DN

CLK_BUF_CPYCLK_R_DP

CLKOUT_DMI_CLKGEN_R_DN

CLKOUT_DMI_CLKGEN_R_DP

CLKPWRGD_R

CKG_X2

ICC_EN#

MAIN_PWRGD

CLK_XDP_CLKGEN_DP

CLKIN_BUF_CPYCLK_DN

CLK_XDP_CLKGEN_DN

CLKIN_BUF_CPYCLK_DP

CLKPWRGD

10K_5%_2

33_5%_2_DY

33>

TC7SZ08FU

1K_5%_2_DY

0.1UF_16V_2

0_5%_2_DY

33_5%_2_DY

0_5%_2_DY

0_5%_2

33_5%_2_DY

26<

27<

29<>

59>

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

+

-

OUT

BI

VDDSRC_3.3

VDDCPU_IO

CPUC1_LPR

CPUT1_LPR

GNDCPU

CPUC0_LPR

CPUT0_LPR

VDDCPU_3.3

CLKPWRGD-PD#_3.3

GNDREF

X2

X1

VDDREF_3.3

REF_3L-FSLC_3.3

SDATA_3.3

SCLK_3.3

GND

CPU_STOP#

VDDSRC_IO

SRCC1_LPR

SRCT1_LPR

GNDSRC

SATAC_LPR

SATAT_LPR

GNDSATA

GND27MHz

27MHz_SS

27MHz_nonSS

VDD_27MHz

DOT96C_LPR

DOT96T_LPR

GNDDOT96MHz

VDDDOT96MHz_3.3

Close to CPU

SERIES

PCH ONLY

10mil

XDP CONNECTOR

XDP

EVEREST-M

97

Fri Dec 31 10:16:45 2010

60

Frank Hu

2

1

R8056

2

1

R8043

2

1

R8044

2

1

R8045

2

1

R8046

2

1

R8006

2

1

R8015

2

1

R8010

2

1

R8047

2

1

R8004

2

1

R8005

2

1

R8007

2

1

R8008

2

1

R8051

2

1

R8054

2

1

R8009

2

1

R8000

2

1

R8011

2

1

R8055

2

1

R8048

2

1

R8049

2

1

R8050

2

1

R8002

2

1

R8003

2

1

R8013

2

1

R8012

2

1

R8014

2

1

R8052

2

1

R8001

2

1

R8053

4443

54

58

52

5655

57

51

53

46

39

24

22

6

4

23

21

5

3

17

15

11

9

36

34

30

28

18

16

12

10

35

33

29

27

40

42

47

45

41

2625

20

19

1413

87

6059

5049

3837

32

31

2

1

48

CN8000

SAMTEC_BSH_030_01_L_D_A_TR_60P

20<

H_TMS

51_1%_2_DY

1K_5%_2

TDO_R

10K_5%_2_DY

25<

25>

CFG<3>

CFG<2>

CFG<1>

CFG<0>

CFG<17>

H_CPUPWRGD_XDP

0_5%_2_DY

1K_5%_2_DY

0_5%_2_DY

PCH_TDI

PCH_TCK

PCH_TDO

PCH_TCK

61>

H_CPUPWRGD_XDP

A01

TMS_R

TDI_R

TRST#_R

TDO_R

PCH_TMS

PCH_TDI

PCH_TRST#

PCH_TDO

TCK_XDP

TDO_R

H_TMS

H_TCK1

PCH_TCK

PCH_TMS

H_TCK

H_TDO

H_TCK1

H_TCK

PCH_3S_SMCLK

PCH_3S_SMDATA

ALLSYS_PWROK

CFG<0>

XDP_PWRSW#

H_CPUPWRGD

TCK_XDP

XDP_PWRSW#_R

TMS_R

TDI_R

TRST#_R

XDP_DBRESET#

+V1.05S_VCCP_VCC_OBS_CD

CLK_XDP_R_DN

CLK_XDP_R_DP

CFG<7>

CFG<6>

CFG<5>

CFG<4>

CFG<9>

CFG<8>

CFG<16>

+V1.05S_VCC_OBS_AB

H_BPM7_XDP#

H_BPM6_XDP#

H_BPM5_XDP#

H_BPM4_XDP#

CFG<11>

CFG<10>

H_BPM3_XDP#

H_BPM2_XDP#

H_BPM1_XDP#

H_BPM0_XDP#

H_PRDY#

H_PREQ#

MAIN_PWRGD

H_TRST#

H_TDI

CLK_XDP_DN

CLK_XDP_DP

PLT_RST#

CLK_XDP_R_DP

SYS_RESET#

H_TDO

60<>

0_5%_2

60<

60>20<

60>

0_5%_2_DY

0_5%_2

0_5%_2_DY

0_5%_2_DY 0_5%_2_DY

60>20<

20>60<

0_5%_2_DY

60<>

20<

60<>

27< 26<

59<> 29<>

60< 25>

61>

60<>

28>

60<>

61>

28>

60<>

60>

28>

61<

60>

60<>

61>

28>

61>

60>

28>

60>

60<>

28>

61>

28>

60>

61>

0_5%_2_DY

P1V05_VCCPS

P3V3_S

25>

20>

20<

0_5%_2_DY

10K_5%_2_DY

+V1.05S

0_5%_2_DY

1K_5%_2_DY

20<

60<>

20<

39<

32<>

37<

68<

29>

59<37<

14<18>

0_5%_2_DY

20>

30<

0_5%_2_DY

60<>

20>

25<

25>

25<25>

25> 25<

25>

25<25>

25>

25> 60<

25>

1K_5%_2

P3V3_S

P1V05_VCCPS

CS_1310AXXXXXX-MTR

C

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

OUT

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GND17

TMS

TDI

TRSTn

TDO

GND15

DBR#_HOOK7

RESET#_HOOK6

VCC_OBS_CD

ITPCLK#_HOOK5

ITPCLK_HOOK4

GND13

OBSDATA_D3

OBSDATA_D2

GND11

OBSDATA_D1

OBSDATA_D0

GND9

OBSFN_D1

OBSFN_D0

GND7

OBSDATA_C3

OBSDATA_C2

GND5

OBSDATA_C1

OBSDATA_C0

GND3

OBSFN_C1

OBSFN_C0

GND1

GND16

TCK0

TCK1

SCL

SDA

GND14

HOOK3

HOOK2

VCC_OBS_AB

HOOK1

PWRGOOD_HOOK0

GND12

OBSDATA_B3

OBSDATA_B2

GND10

OBSDATA_B1

OBSDATA_B0

GND8

OBSFN_B1

OBSFN_B0

GND6

OBSDATD_A4

OBSDATD_A2

GND4

OBSDATD_A1

OBSDATD_A0

GND2

OBSFN_A1

OBSFN_A0

GND0

15MIL

ME JTAG

15MIL

Frank Hu

EVEREST-M

Fri Dec 31 10:16:46 2010

97

61

2

1

R8041

2

1

R8042

G2

G1

6

5

4

3

2

1

JACK8000

2

1

R8016

2

1

C8000

2

1

R8017

2

1

C8001

2

1

C8002

2

1

R8021

2

1

R8038

2

1

R8022

2

1

R8023

2

1

R8020

2

1

R8019

2

1

R8018

14

4

8

11

7

1

9

10

12

13

6

5

3

2

U8000

2

1

C8003

2

1

R8035

2

1

R8033

2

1

R8032

2

1

R8034

2

1

R8029

2

1

R8031

2

1

R8028

2

1

R8030

2

1

C8004

2

1

R8039

2

1

R8040

2

1

R8036

2

1

R8037

2

1

R8024

2

1

R8025

2

1

R8026

2

1

R8027

14

4

8

11

7

1

9

10

12

13

6

5

3

2

U8001

61<

ME_TDI

PCH_TMS_R

PCH_TRST#_R

+V3M

0.1UF_16V_2

22_5%_2

CS_1310AXXXXXX-MTR

PCH_TDO

PCH_TMS

PCH_TRST#

PCH_TCK

PCH_TDI

PCH_TCK_R

PCH_TDI_R

ME_TDO

ME_TRST#

ME_TDO

ME_TDI

ME_TMS

ME_TCK

ME_TMS

ME_TRST#

ME_TCK

PCH_TCK_R

1K_5%_2 1K_5%_2

1K_5%_2

3.24K_1%_2

28>60>

60<>

0.1UF_16V_2

1K_5%_2

PHP_GTL2005_TSSOP_14P

10K_5%_2

10K_5%_2_DY

+V3M

60>

60<>

28>

60<>

60>

28>

60<>

60>

28>

0_5%_2_DY

220PF_50V_2

10K_5%_2

61<

PHP_GTL2005_TSSOP_14P

806_1%_2

2.37K_1%_2

+V3M

0.1UF_16V_2 10K_5%_2_DY

10K_5%_2

0.1UF_16V_2

+V3M

61>

MLX_85510_5019_6P

10K_5%_2_DY

10K_5%_2

10K_5%_2_DY

10K_5%_2

61<

10K_5%_2_DY

619_1%_2

10K_5%_2

10K_5%_2_DY

301_1%_2

+V3M

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

IN

G2

6

5

4

3

2

1

G1

OUT

IN

GND3

B3

B2

GND2

B1

B0

VCC

GND1

A3

GTLREF

A2

DIR

A0

A1

OUT

GND3

B3

B2

GND2

B1

B0

VCC

GND1

A3

GTLREF

A2

DIR

A0

A1

PICK BUTTON BOARD

CONNECT TO TOUCHPAD MODULE

CONNECT TO TOUCHPAD SWITCH BOARD

PICK BUTTON BOARD

(FOR - TOUCHPAD MODULE, TOUCHPAD SWITCH BOARD, FINGERPRINT MODULE)

CONNECT TO MAINBOARD'S TP CONNECTOR

EVEREST-M

62

97

Fri Dec 31 10:17:03 2010

Frank Hu

G2

G1

2

1

CN9020

1

S9021

1

S9020

1

FIX9304

1

FIX9904

1

FIX9303

1

FIX9302

1

FIX9301

1

FIX9300

32

1

D9041

6

5

4

3

2

1

SW9020

6

5

4

3

2

1

SW9021

G2

G1

6

5

4

3

2

1

CN9022

G2

G1

6

5

4

3

2

1

CN9021

ACES_88766_060N_6P

MISAKI_NTC017_DA1G_E160T_6P

PHP_PESD5V2S2UT_SOT23_3P

FIX_MASK

SCREW300_800_1P

SCREW220_800_1P

ENTERY_3703_Q02N_03R_2P

GND_TP

+TP_5S

GND_TP

+TP_5S

GND_TP

A01

DB_TP_ON#

TP_IM_DAT_5

TP_IM_CLK_5

LEFT_TP

RIGHT_TP

FIX_MASK

62<

62>

RIGHT_TP

LEFT_TP

62<>

TP_IM_DAT_5

TP_IM_CLK_5

62<>

62>

62<>

62<

C

CS_1310AXXXXXX-MTR

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

6

1

G2

5

4

2

3

G1

IN

BI

G1

2

1

G2

OUT

A

B

DC

A

B

DC

OUT

BI

IN

6

1

G2

5

4

2

3

G1

TOUCH PAD SW BOARD

TOUCHPAD SWITCH BOARD

EVEREST-M

Frank Hu

Fri Dec 31 10:16:46 2010

97

63

1

S9041

1

S9040

1

FIX9043

1

FIX9042

1

FIX9041

1

FIX9040

2

1

R9040

1

PAD9041

1

PAD9040

2

1

C9040

3

2

1

D9040

6

5

4

3

2

1

SW9040

MISAKI_NTC017_DA1G_E160T_6P

PHP_PESD5V2S2UT_SOT23_3P_DY

0.01UF_50V_2

SMDPAD_1P_40X120

33_5%_2

FIX_MASK FIX_MASK FIX_MASK FIX_MASK SCREW230_700_1P

SCREW230_700_1P

GND_PB

CS A01

CS_1310AXXXXXX-MTR

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

A

B

DC

POWER BUTTON BOARD

POWER BUTTON

EVEREST-M

Frank Hu

Fri Dec 31 10:16:46 2010

97

64

1

S9001

1

S9000

2

1

C9000

G2

G1

4

3

2

1

SW9000

1

PAD9000

1

FIX9005

1

FIX9004

1

FIX9003

1

FIX9002

1

FIX9001

1

FIX9000

1

PAD9001

32

1

D9000

PHP_PESD5V2S2UT_SOT23_3P_DY

SMDPAD_1P_40X120

FIX_MASK FIX_MASK FIX_MASK FIX_MASK

FIX_MASK FIX_MASK

SMDPAD_1P_40X120

FOX_1BT002_0021L_4P

1000PF_50V_2

SCREW540_700_NP_1P SCREW540_700_NP_1P

GND_BTN

A01

CS

CS_1310AXXXXXX-MTR

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

CLOSE TO RTS5159

R9151 R9152

CARD READER & USB BOARD

CLOSE TO CN

CARDREADER & USB BOARD

USB

65

97

Fri Dec 31 10:16:47 2010

EVEREST-M

Frank Hu

2

1

C9108

1

FIX9105

1

FIX9104

1

FIX9103

1

FIX9102

1

FIX9101

1

FIX9100

2

1

34

L9150

1

G4

G3

G2

G1

4

2

3

CN9152

1

G4

G3

G2

G1

4

2

3

CN9151

2

1

C9114

2

1

34

L9151

2

1

R9150

2

1

C9152

2

1

C9153

2

1

PAD9150

2

1

C9150

2

1

C9154

2

1

C9151

8

7

6

5

3

2

1

4

U9150

2

1

C9107

2

1

C9105

2

1

C9106

1

S9102

22

9

17

11

3

1

19

18

6

14

21

20

16

2

4

5

8

7

10

13

12

15

G2

G1

CN9101

1

S9101

2

1

C9112

2

1

R9151

2

1

C9109

2

1

C9110

2

1

C9111

2

1

C9104

2

1

R9103

2

1

C9102

2

1

R9101

2

1

R9102

2

1

C9103

48

47

13

10

29

28

27

26

25

23

21

20

43

42

41

40

39

38

37

35

34

31

19

36

44

2

30

7

3

24

22

45

14

46

32

12

6

17

15

18

16

5

4

33

11

9

1

8

U9100

2

1

L9100

2

1

C9113

2

1

C9101

2

1

C9100

2

1

R9100

2

1

X9100

G2

G1

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

CN9100

ACES_50503_0184N_001_18P

12MHZ

270K_5%_2

20PF_50V_2 20PF_50V_2

0.1UF_16V_2

BLM18PG600SN1D

REA_RTS5159_VDD_GR_LQFP_48P

1UF_6.3V_2

100K_5%_2

0_5%_2

47PF_50V_2_DY

6.2K_1%_2

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

0_5%_2

0.1UF_16V_2

SCREW300_900_1P

TAIT_R009_040_LM_22P

SCREW480_800_700_1P

2.2UF_6.3V_2

1UF_6.3V_2 1UF_6.3V_2

GMT_G547G1P81U_MSOP_8P

0.1UF_16V_2

0.01UF_50V_222UF_6.3V_5_DY

POWERPAD_2_0610

330UF_6.3V 0.1UF_16V_2 RSC_0402_DY

WCM_2012_900T

10UF_6.3V_3

SYN_020133GR004M52CZL_4P

WCM_2012_900T

FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8

0.1UF_16V_2

+USB_VCC1

GND_CARD

+V5A_DB

+USB_VCC1

GND_CARD

+USB_VCC1

GND_CARD

+CARD_3V3

GND_CARD

+VBUS

GND_CARD

+V3S_CARD

+V5A_DB

+V3S_CARD

+VBUS

GND_CARD

+VBUS

GND_CARD

+VBUS

GND_CARD

+CARD_3V3

GND_CARD

+VBUS

GND_CARD

SD_D1

SD_CLK_MS_CLK

SD_D3

VREG

USB_DB_3IN1_DP

USB_DB_3IN1_DN

XTIL1

XTIL0

USB_DB_P2_DP

USB_DB_P1_DN

SB_USB_1_DB

USB_DB_3IN1_DP

USB_OC#_1_DB

LED_3IN1_DB

USB_DB_3IN1_DN

USB_DB_P2_DN

USB_DB_P1_DP

LED_3IN1_DB

MS_BS

MS_D1

SD_D0_MS_D0

MS_D2

MS_INS#

MS_D3

SD_CMD

SD_WP

SD_CD#

SD_D1

SD_CLK_MS_CLK

XTIL1

XTIL0 SD_D3

SD_D2

SD_WP

SD_CD#

SD_CLK_MS_CLK

MS_D3

MS_INS#

MS_D2

SD_D0_MS_D0

MS_D1

MS_BS

USB_DB_P2_DP

USB_DB_P1_DP

USB_DB_P2_DN

USB_DB_P2_L_DP

USB_DB_P2_L_DN

USB_DB_P1_DN

USB_DB_P1_L_DP

USB_DB_P1_L_DN

USB_DB_P2_L_DP

USB_DB_P2_L_DN

USB_DB_P1_L_DN

USB_DB_P1_L_DP

SB_USB_1_DB

+V5A_DB_USB_IN

USB_OC#_1_DB

65<

65<>

65<

65>

65<

65<>

65>

65<>

65>

65> 65>

65>

SD_D0_MS_D0

65<>

65>

SD_CMD

65<>

65<

65<>

65<

65>

CS_1310AXXXXXX-MTR

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

BI

BI BI

IN

GND

SD-CD

MS-SCLK

MS-DATA3

MS-INS

MS-DATA2

MS-DATA0

MS-DATA1

MS-BS

SD-VDD

SD-CD-WP

SD-DAT2

SD-DAT3

SD-CMD

SD-CLK

SD-DAT0

SD-DAT1

SD-WP

MS-VSS

SD-VSS

MS-VSS

MS-VCC

SD-VSS

IN

BI BI

BI

IN

BI

IN

OUT

XTLI

XTL0

GND

MODE_SEL

RST#

SP19

SP18

SP17

SP16

SP15

SP14

SP13

SP5

SP6

SP7

SP8

SP9

NC

SP10

GND

D3V3

SP11

SP12

SD_CMD

XTAL_CTR

GPIO0

EEDO

EECS

EESK

EEDI

SP1

SP2

SP3

MS_D4

SP4

MS_D5

GND

D3V3

VREG

CARD_3V3

3V3_IN

NC

GND

DP

DM

NC

RREF

AV_PLL

OUT

G

D+

D-

VCC

G

D+

D-

VCC

BI BI BI

BI

BI BI

OUT

BI

OUT

+

OUT

1

2

IN

OUT

OC#EN

IN

GND

IN

BI

IN

18

17

16

15

14

13

12

11

G2

10

9

8

7

6

5

4

3

2

1

G1

EMI

EVEREST-M

66

97

Fri Dec 31 10:17:04 2010

Frank Hu

2

1

C7500

2

1

C7503

2

1

C7501

2

1

C7502

2

1

C7504

2

1

C7507

2

1

C7505

2

1

C7506

2

1

C7508

2

1

C7509

2

1

C7510

2

1

C7511

0.1UF_16V_2

0.1UF_16V_2 0.1UF_16V_2

0.1UF_16V_2

P1V5

0.1UF_16V_2

C

CS_1310AXXXXXX-MTR

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

10.72A

3.55A

2.5A

HIGH

AFTER RESET

LOW

20mil

LOW: B1

20mil

LOW: B1

HI: B2

1 : ADDIN CARD NOT PLUGGED IN

DGPU_PRSNT#

HIGH

DGPU_PWROK

DGPU_PWR_EN#

HIGH

DGPU_HOLD_RST#

DGPU_SELECT#

DGPU_PWM_SELECT#

0 : DGPU POWER SWITCH TURNED ON

1 : DGPU POWER IS STABLE

GPU SW / POWER

1 : PWM SIGNAL FROM PCH

0 : PWM SIGNAL FROM EC

1 : DISPLAY SWITCH ENABLED FOR IGPU

1 : RESET IS RELEASED

LOW

HI: B2

20mil

HIGH

DURING RESET

0 : ADDIN CARD PRESENT

1 : POWER SWITCH TURNED OFF

0 : DGPU POWER IS NOT STABLE.

0 : KEEP DGPU IN RESET

0 : DISPLAY SWITCH ENABLED FOR DGPU

EVEREST-M

Frank Hu

67

Fri Dec 31 10:16:48 2010

97

43

9

22

23

24

25

31

32

33

34

26

27

28

29

35

36

37

38

16

15

12

11

7

6

3

2

8

5

42

41

40

4

39

30

21

20

19

18

17

14

13

10

1

U3005

2

1

R7401

2

1

R7405

2

1

R3021

2

1

R3020

2

1

R7402

2

1

3

Q7400

2

1

R7403

2

1

3

Q7401

4

3 6

5

2

1

Q7407

2

1

C7404

5

4

1

2

3

U3004

2

1

R7410

2

1

R7409

2

1

R7414

2

1

R7408

2

1

3

Q7406

2

1

C7403

2

1

R7404

2

1

3

Q7402

16

1

15

8

13

14

12

10

11

9

6

5

7

3

2

4

U3003

16

1

15

8

13

14

12

10

11

9

6

5

7

3

2

4

U3002

2

1

R7412

2

1

C7400

2

1

R7411

2

1

C7401

2

1

R7400

2

1

3

Q7410

2

1

3

Q7405

2

1

R7407

2

1

C7402

2

1

R7406

2

1

3

Q7403

3

2

1

45

6

7

8

Q7404

2

1

R7413

2

1

3

Q7408

2

1

C7405

3

2

1

45

6

7

8

Q7409

EC_DGPU_PWR_EN#

PCH_LVDS_DDCCLK

SW_LVDS_DDCDATA

PCH_LVDS_DDCDATA

GPU_LVDS_DDCDATA

SW_LVDS_DDCCLK

GPU_LVDS_DDCCLK

32>

67<

SSM3K7002BFU

DGPU_PWROK#

SW_LVDS_TXDL0_DN

SW_LVDS_TXDL0_DP

SW_LVDS_TXDL1_DN

SW_LVDS_TXDL1_DP

SW_LVDS_TXDL2_DN

SW_LVDS_TXCL_DP

PER_PI2PCIE2412ZHE_TQFN_42P

PCH_LVDS_TXCL_DP

PCH_LVDS_TXCL_DN

PCH_LVDS_TXDL2_DP

PCH_LVDS_TXDL2_DN

PCH_LVDS_TXDL1_DP

PCH_LVDS_TXDL1_DN

PCH_LVDS_TXDL0_DP

PCH_LVDS_TXDL0_DN

P1V8_S

SSM3K7002BFU

10K_5%_2

CLKREQ_GPU_PEG#_MOS

CLKREQ_GPU_PEG#

330uF_2V_15mR_Pana_-35%

220K_5%_2

CSC0402_DY

EC_DGPU_PWR_EN#

100K_5%_2

P3V3_S

10K_5%_2

AM4430N

0.1UF_25V_2

SSM3K7002BFU

P3V3_GPUS

330PF_50V_2

SSM3K7002BFU

EC_DGPU_PWR_EN

A01

SSM3K7002BFU

750K_1%_2

GPU_LCM_BKLTEN

PCH_LCM_BKLTEN

SW_LCM_BKLTEN

GPU_LCM_VDDEN

PCH_LCM_VDDEN

SW_LCM_VDDEN

P5V_S

DGPU_SELECT#

DGPU_SELECT

TC7SH14F

GPU_LCM_INVPWM

CS

CS_1310AXXXXXX-MTR

DGPU_PRSNT#

DGPU_SELECT#

DGPU_SELECT

GPU_LVDS1_TXCL_DP

GPU_LVDS1_TXCL_DN

GPU_LVDS1_TXDL2_DP

GPU_LVDS1_TXDL1_DP

GPU_LVDS1_TXDL1_DN

GPU_LVDS1_TXDL0_DP

GPU_LVDS1_TXDL2_DN

GPU_LVDS1_TXDL0_DN

SW_LVDS_TXDL2_DP

SW_LVDS_TXCL_DN

EC_LCM_INVPWM

SW_LCM_INVPWM

PCH_LCM_INVPWM

DGPU_PWM_SELECT#

DGPU_PWROK

DGPU_PWROK_5R

DGPU_PWROK#

DGPU_PWROK_5R

DGPU_PWROK

DGPU_PWROK#

10K_5%_2

10K_5%_2_DY

P3V3_S

0.1UF_16V_2

0_5%_2

0_5%_2_DY

32<

PHP_CBT3257DS_QSOP_16P

31>

48<

PHP_CBT3257DS_QSOP_16P

44<

P5V_S

680PF_50V_2

67<

10K_5%_2_DY

P3V3_A

0_5%_2

AM4430N

P1V05_VCCPS

SSM3K7002BFU

10K_5%_2

P3V3_S

SSM3K7002BFU

67<

P5V_S

AM3423P

200_5%_3

200_5%_2

P1V05_GPUS

67<

33<>

16>

P3V3_S

SSM3K7002BFU

750K_1%_2

P5V_S P1V5

200_5%_2

P1V5_GPUS

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

G

DS

IN

OUT

3A

3B2

3B1

4A

4B2

4B1

OE

VCC

GND

2A

2B2

2B1

1A

1B2

1B1

S

OUT

IN

OUT

IN

3A

3B2

3B1

4A

4B2

4B1

OE

VCC

GND

2A

2B2

2B1

1A

1B2

1B1

S

G

DS

OUT

IN

G

DS

IN

G

DS

OUT

G

DS

OUT

IN

TML

SEL

C7

C6

C5

C4

C3

C2

C1

C0

B7

B6

B5

B4

B3

B2

B1

B0

A7

A6

A5

A4

A3

A2

A1

A0

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

OUT

IN

NMOS_4D3S

D

G

S

IN

OUT

G

DS

OUT

IN

G

DS

S

PMOS_4D1S

G

D

+

NC

+

-

IN

OUT

G

DS

OUT

IN

NMOS_4D3S

D

G

S

GPU-1

20mil

15mil

10mil

CLOSE TO POWER IC

9768

Fri Dec 31 10:16:49 2010

Frank Hu

2

1

R5003

2

1

C5039

2

1

C5042

2

1

C5043

2

1

C5044

2

1

C5045

2

1

C5046

2

1

C5047

2

1

R5002

2

1

3

Q5001

2

1

C5063

2

1

C5003

2

1

C5002

2

1

C5001

2

1

C5064

2

1

C5159

2

1

C5065

2

1

C5000

2

1

R5000

5

4

3

2

1

U5001

2

1

R5026

2

1

R5027

2

1

X5000

2

1

C5069

2

1

C5068

2

1

R5073

2

1

C5158

2

1

L5007

2

1

C5157

2

1

C5137

2

1

C5135

2

1

L5006

2

1

C5138

2

1

C5136

2

1

R5074

D2

D1

B2

B1

AD9

AF9

AE9

U5000

1

2

R5076

2

1

C5005

2

1

C5006

2

1

C5007

2

1

C5008

2

1

C5010

2

1

C5009

2

1

C5011

2

1

C5012

2

1

C5014

2

1

C5013

2

1

C5015

2

1

C5016

2

1

C5017

2

1

C5018

2

1

C5019

2

1

C5020

2

1

C5021

2

1

C5022

2

1

C5024

2

1

C5023

2

1

C5025

2

1

C5026

2

1

C5027

2

1

C5028

2

1

C5030

2

1

C5029

2

1

C5031

2

1

C5032

2

1

C5034

2

1

C5033

2

1

C5035

2

1

C5036

2

1

R5017

2

1

R5075

2

1

C5139

2

1

L5009

2

1

C5142

2

1

C5145

2

1

C5004

2

1

C5134

2

1

C5146

2

1

C5150

2

1

C5153

2

1

C5149

2

1

C5154

2

1

C5132

2

1

C5140

2

1

C5143

2

1

C5147

2

1

C5151

2

1

C5155

2

1

C5133

2

1

C5141

2

1

C5144

2

1

C5148

2

1

C5152

2

1

C5156

P7

D35

AD20

J9

J13

J12

J11

J10

AP35

AM26

AL26

AK25

AL25

AM25

AM24

AM23

AL23

AK22

AL22

AM22

AM21

AM20

AL20

AK19

AL19

AP32

AN32

AM32

AM31

AM30

AM29

AL29

AK29

AK28

AL28

AM28

AM27

AM19

AM18

AM17

AL17

AJ18

AJ17

AG21

F7

AG19

AN26

AP26

AR26

AR25

AP25

AN25

AN23

AP23

AR23

AR22

AP22

AN22

AN20

AP20

AR20

AR19

AP34

AR34

AR32

AR31

AP31

AN31

AN29

AP29

AR29

AR28

AP28

AN28

AP19

AN19

AN17

AP17

AM16

AR17

AR16

AG14

AG20

AG23

AG22

AG18

AG17

AG16

AG15

AG13

AL16

AK26

AK23

AK20

AK18

AJ27

AG12

AJ25

AJ24

AJ22

AJ21

AJ19

AJ15

AJ14

AG26

AG25

AG24

AG11

AK27

AK24

AK21

AK17

AK16

AR13

AG6

AF6

AD6

AC5

AB7

AB4

AA4

Y4

V6

U7

P6

H32

G5

F4

A7

E7

E5

D7

D6

D5

C7

B7

AL7

AK15

AJ5

A2

R7

E35

AD19

U5000

18PF_50V_2

0.1uF_16V_2

+GPU_NVVDD_L_R

+GPU_V1.05S_PEX_PLLVDD

PEG_RX15_C_DP

0.1uF_6.3V_1

CLK_PEG_GPU_REF_DN

CLK_PEG_GPU_REF_DP

200_1%_2

SSM3K7002BFU

P3V3_GPUS

CLKREQ_GPU_PEG#_MOS

EC_PEG_RST#

37<

32<>

22UF_6.3V_5_DY 10UF_6.3V_3_DY 1UF_6.3V_2_DY 0.1UF_16V_2_DY

4.7uF_6.3V_3 10uF_6.3V_3 22UF_6.3V_5

P1V05_GPUS

0.1uF_16V_2

P3V3_GPUS

0.1UF_16V_2

4700PF_50V_2

KC_HLM_160808_R10J

0.1UF_16V_2

XTAL27_IN

10K_5%_2

XTAL27_OUT

27MHz

NVIDIA_N12P_GS_BGA_973P

0_5%_2_DY

CLK_GPU_27M

4.7uF_6.3V_3 0.1uF_16V_2

0_5%_2

100_1%_2

0.1UF_16V_2

1uF_6.3V_2

P3V3_GPUS

P1V05_GPUS

4.7uF_6.3V_3

PEG_TX15_DP

PEG_TX15_DN

PEG_RX15_DP

PEG_RX15_DN

PEG_TX14_DN

PEG_TX14_DP

PEG_RX14_DN

PEG_RX14_DP

PEG_TX13_DN

PEG_TX13_DP

PEG_RX13_DN

PEG_RX13_DP

PEG_TX12_DN

PEG_TX12_DP

PEG_RX12_DN

PEG_RX12_DP

PEG_RX15_C_DN

PEG_RX14_C_DN

PEG_RX14_C_DP

PEG_RX13_C_DN

PEG_RX13_C_DP

PEG_RX12_C_DP

PEG_RX12_C_DN

PEG_RX11_DN

PEG_TX11_DP

PEG_TX11_DN

PEG_RX11_DP

PEG_RX10_DN

PEG_RX10_DP

PEG_RX9_DP

PEG_RX9_DN

PEG_TX10_DP

PEG_TX10_DN

PEG_TX9_DN

PEG_TX9_DP

PEG_TX8_DN

PEG_TX8_DP

PEG_RX8_DN

PEG_RX8_DP

PEG_RX7_DN

PEG_RX7_DP

PEG_RX6_DP

PEG_RX6_DN

PEG_RX5_DN

PEG_RX5_DP

PEG_TX7_DN

PEG_TX7_DP

PEG_TX6_DN

PEG_TX6_DP

PEG_TX5_DP

PEG_TX5_DN

PEG_RX11_C_DN

PEG_RX11_C_DP

PEG_RX10_C_DN

PEG_RX10_C_DP

PEG_RX9_C_DN

PEG_RX9_C_DP

PEG_RX8_C_DP

PEG_RX8_C_DN

PEG_RX7_C_DN

PEG_RX7_C_DP

PEG_RX6_C_DP

PEG_RX6_C_DN

PEG_RX5_C_DN

PEG_RX5_C_DP

PEG_RX4_DN

PEG_RX4_DP

PEG_RX3_DN

PEG_RX3_DP

PEG_RX2_DP

PEG_RX2_DN

PEG_TX4_DP

PEG_TX4_DN

PEG_TX3_DP

PEG_TX3_DN

PEG_TX2_DN

PEG_TX2_DP

PEG_TX1_DN

PEG_RX1_DN

PEG_RX1_DP

PEG_RX0_DP

PEG_RX0_DN

PEG_TX1_DP

PEG_RX4_C_DN

PEG_RX4_C_DP

PEG_RX3_C_DN

PEG_RX3_C_DP

PEG_RX2_C_DN

PEG_RX2_C_DP

PEG_RX1_C_DP

PEG_RX1_C_DN

PEG_RX0_C_DP

PEG_RX0_C_DN

PLT_RST#

+GPU_NVVDD_L

+GPU_V1.05S_SP_PLLVDD

GND_SENSE_R

+GPU_V1.05S_PLLVDD

21>

21<

21>

21<

21>

21<

21>

21<

0.1uF_6.3V_1

21<

21>

21<

21>

21<

0.1uF_6.3V_1

21<

21>

21<

21>

PEG_TX0_DP

21>

PEG_TX0_DN

21>

0.1uF_6.3V_1

39<

60<

TC7SZ08FU

100K_5%_2

P3V3_GPUS

0.1uF_16V_2

NVIDIA_N12P_GS_BGA_973P

2.49K_1%_2

10K_5%_2

1uF_6.3V_2 1uF_6.3V_2 4.7uF_6.3V_3

0.1uF_16V_2 1uF_6.3V_2

4.7UF_6.3V_3

0.1uF_16V_2

0_5%_2_DY

0.1uF_16V_2

P1V05_GPUS

1uF_6.3V_2 1uF_6.3V_2

0.1uF_16V_2 0.1uF_16V_2

4.7UF_6.3V_3_DY 1UF_6.3V_2_DY

1uF_6.3V_2 1uF_6.3V_2

HK1005R10J_T_200mA

10K_5%_2

18PF_50V_2

4.7uF_6.3V_3

P1V05_GPUS

4.7uF_6.3V_3

KC_HLM_160808_R10J

10uF_6.3V_3

0.1UF_16V_2

10UF_6.3V_3

0.1UF_16V_2

22UF_6.3V_5

P1V05_GPUS

0.1uF_16V_2

A01

CS_1310AXXXXXX-MTR

C

ES

DATE

2

CODE

INVENTEC

DOC.NUMBER

TITLE

of

A

E

D

C

B

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

REV

CHANGE by

EVEREST

1

SHEET

SIZE

OUT

IN

OUT

IN

OUT

G

DS

IN

+

-

IN

14/16 XTAL_PLL

XTAL_SSIN XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

SP_PLLVDD

PLLVDD

OUT

BI

IN

OUT

GF108

RFU

GT21X

1/16 PCI_EXPRESS

PEX_SVDD_3V3GT21X

GF108

VDD_SENSE_3

VDD_SENSE_2

VDD_SENSE_1

VDD33_5

VDD33_4

VDD33_3

VDD33_2

VDD33_1

TESTMODE

PEX_TX9*

PEX_TX9

PEX_TX8*

PEX_TX8

PEX_TX7*

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4*

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2*

PEX_TX2

PEX_TX15*

PEX_TX15

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12*

PEX_TX12

PEX_TX11*

PEX_TX11

PEX_TX10*

PEX_TX10

PEX_TX1*

PEX_TX1

PEX_TX0*

PEX_TX0

PEX_TSTCLK_OUT*

PEX_TSTCLK_OUT

PEX_TERMP

PEX_SVDD_3V3_NC

PEX_SVDD_3V3

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7*

PEX_RX7

PEX_RX6*

PEX_RX6

PEX_RX5*

PEX_RX5

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2*

PEX_RX2

PEX_RX15*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13*

PEX_RX13

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX1*

PEX_RX1

PEX_RX0*

PEX_RX0

PEX_RST*

PEX_REFCLK*

PEX_REFCLK

PEX_PLL_HVDD_NC

PEX_PLLVDD

PEX_IOVDD_5

PEX_IOVDD_4

PEX_IOVDD_3

PEX_IOVDD_2

PEX_IOVDD_1

PEX_IOVDDQ_9

PEX_IOVDDQ_8

PEX_IOVDDQ_7

PEX_IOVDDQ_6

PEX_IOVDDQ_5

PEX_IOVDDQ_4

PEX_IOVDDQ_3

PEX_IOVDDQ_25

PEX_IOVDDQ_24

PEX_IOVDDQ_23

PEX_IOVDDQ_22

PEX_IOVDDQ_21

PEX_IOVDDQ_20

PEX_IOVDDQ_2

PEX_IOVDDQ_19

PEX_IOVDDQ_18

PEX_IOVDDQ_17

PEX_IOVDDQ_16

PEX_IOVDDQ_15

PEX_IOVDDQ_14

PEX_IOVDDQ_13

PEX_IOVDDQ_12

PEX_IOVDDQ_11

PEX_IOVDDQ_10

PEX_IOVDDQ_1

PEX_CLKREQ*

NC_9

NC_8

NC_7

NC_6

NC_5

NC_4

NC_3

NC_26

NC_25

NC_24

NC_23

NC_22

NC_21

NC_20

NC_2

NC_19

NC_18

NC_17

NC_16

NC_15

NC_14

NC_13

NC_12

NC_11

NC_10

NC_1

GND_SENSE_3

GND_SENSE_2

GND_SENSE_1

GPU-2

16mil

10mil

Fri Dec 31 10:16:50 2010

9769

Frank Hu

2

1

C5056

2

1

C5057

2

1

C5070

2

1

C5071

2

1

R5077

2

1

C5059

2

1

C5060

2

1

C5074

2

1

C5058

2

1

L5002

2

1

C5061

2

1

C5037

2

1

C5038

2

1

R5016

2

1

C5062

Y27

W27

V34

V29

V27

U29

U27

T27

R27

P27

N27

G25

G24

G28

G27

G12

G11

G15

G14

B26

A32

D32

E26

D14

E10

A10

C14

A26

A31

D31

F26

E14

D9

B10

B14

D28

A34

D34

D27

D15

F11

D10

A16

G16

G19

B11

C13

D16

A25

B25

D25

C26

A17

C28

A28

B28

A29

B34

B35

B32

C32

B31

C29

B16

C31

B29

E29

D30

F29

C33

E31

D33

F32

E32

C16

E25

D24

F25

D26

E28

F28

F27

D29

F17

F16

A14

E16

F15

F14

F13

E13

D12

E11

D11

D8

F12

A13

F9

F10

F8

E8

A8

B8

C8

C10

A11

C11

D13

B13

D20

B19

E20

B17

C19

F19

G20

A20

C17

A22

B22

C22

B23

D22

A23

D21

E22

F21

C23

D18

C25

F23

F24

F22

G21

B20

F20

C20

D19

A19

E19

F18

E23

D23

D17

E17

M27

L27

K27

U5000

2

1

R5038

2

1

C5066

2

1

C5067

2

1

R5040

2

1

R5039

2

1

R5037

2

1

C5073

2

1

C5072

2

1

C5079

2

1

C5078

2

1

C5085

2

1

C5084

2

1

C5083

2

1

C5082

2

1

C5081

2

1

C5080

2

1

R5041

2

1

C5077

2

1

L5000

2

1

C5076

2

1

C5075

AJ28

AE27

AD27

AC27

AB29

AB27

AA31

J29

J24

J23

J22

J21

J20

J17

J16

AA29

J15

J14

H29

G9

G8

G22

G18

G17

E21

B18

AA27

AE29

AD29

AH29

AG29

M29

L29

R29

P29

AC33

AJ34

AJ32

AE31

N31

J32

H35

L34

AC34

AJ35

AJ31

AD32

N32

H31

G35

L35

AF35

AL34

AL32

AF32

P30

J30

H34

P32

T29

T30

K33

K35

P34

AC35

AB32

AE33

AE34

P33

AE35

AF34

AE32

AF33

AM35

AM34

AL35

AJ33

AH32

AH34

P35

AH35

AH33

AH30

AJ30

AK32

AK30

AL33

AM33

AL31

AN33

N35

AD30

AC32

AE30

AF30

AF31

AH31

AG32

AG30

R30

R32

N34

P31

M30

N30

M32

L30

L31

K31

H30

K32

K30

L33

G32

G30

F30

G31

E33

E34

G33

G34

H33

K34

N33

L32

W34

W31

W33

W32

U33

T35

Y29

W29

V32

Y30

Y31

Y34

W35

Y35

AB35

AB34

Y33

Y32

AB33

U31

AA32

AB31

AA30

AB30

W30

T33

T34

U32

U35

U34

V30

U30

AC30

AC31

T31

T32

J27

J18

AF27

J19

AG27

U5000

1UF_6.3V_2

73<

NVIDIA_N12P_GS_BGA_973P

0.1UF_16V_2

4.7uF_6.3V_3

0.1UF_16V_2

FBM_10_160808_301A05T_500mA

FBA_CLK0_DP

FBA_CLK0_DN

FBA_CMD<30..0>

4.7UF_6.3V_3

0.1UF_16V_2

P1V5_GPUS

4.7UF_6.3V_3

FBC_CMD<30..0>

FBC_CMD<25>

75<

76<

10K_5%_2

C

+GPU_V1.05S_FB_DLLAVDD0

FBA_DQS_DP<7>

FBA_DQS_DP<6>

FBA_DQS_DP<5>

FBA_DQS_DP<4>

FBA_DQS_DP<3>

FBA_DQS_DP<2>

FBA_DQS_DP<1>

FBA_DQS_DP<0>

FBA_DQS_DN<7>

FBA_DQS_DN<6>

FBA_DQS_DN<5>

FBA_DQS_DN<4>

FBA_DQS_DN<3>

FBA_DQS_DN<2>

FBA_DQS_DN<1>

FBA_DQS_DN<0>

FBA_DQM<7>

FBA_DQM<6>

FBA_DQM<5>

FBA_DQM<4>

FBA_DQM<3>

FBA_DQM<2>

FBA_DQM<1>

FBA_DQM<0>

+GPU_V1.5S_FBA_DEBUG

FBA_D<9>

FBA_D<8>

FBA_D<7>

FBA_D<63>

FBA_D<62>

FBA_D<61>

FBA_D<60>

FBA_D<6>

FBA_D<59>

FBA_D<58>

FBA_D<57>

FBA_D<56>

FBA_D<55>

FBA_D<54>

FBA_D<53>

FBA_D<52>

FBA_D<51>

FBA_D<50>

FBA_D<5>

FBA_D<49>

FBA_D<48>

FBA_D<47>

FBA_D<46>

FBA_D<45>

FBA_D<44>

FBA_D<43>

FBA_D<42>

FBA_D<41>

FBA_D<40>

FBA_D<4>

FBA_D<39>

FBA_D<38>

FBA_D<37>

FBA_D<36>

FBA_D<35>

FBA_D<34>

FBA_D<33>

FBA_D<32>

FBA_D<31>

FBA_D<30>

FBA_D<3>

FBA_D<29>

FBA_D<28>

FBA_D<27>

FBA_D<26>

FBA_D<25>

FBA_D<24>

FBA_D<23>

FBA_D<22>

FBA_D<21>

FBA_D<20>

FBA_D<2>

FBA_D<19>

FBA_D<18>

FBA_D<17>

FBA_D<16>

FBA_D<15>

FBA_D<14>

FBA_D<13>

FBA_D<12>

FBA_D<11>

FBA_D<10>

FBA_D<1>

FBA_D<0>

FBA_CMD<22>

FBA_CMD<1>

FBA_CMD<7>

FBA_CMD<14>

FBA_CMD<26>

FBA_CMD<10>

FBA_CMD<30>

FBA_CMD<0>

FBA_CMD<12>

FBA_CMD<19>

FBA_CMD<13>

FBA_CMD<6>

FBA_CMD<21>

FBA_CMD<4>

FBA_CMD<5>

FBA_CMD<17>

FBA_CMD<3>

FBA_CMD<28>

FBA_CMD<2>

FBA_CMD<16>

FBA_CMD<11>

FBA_CMD<27>

FBA_CMD<8>

FBA_CMD<29>

FBA_CMD<9>

FBA_CMD<18>

FBA_CMD<24>

FBA_CMD<20>

FBA_CMD<25>

FBA_CLK1_DN

FBA_CLK1_DP

FBA_DQS_DP<7..0>

FBA_DQM<7..0>

FBA_DQS_DN<7..0>

FBA_D<63..0>

FBC_DQS_DN<7..0>

FBC_DQS_DP<7..0>

FBC_DQM<7..0>

FBC_D<63..0>

+GPU_V1.5S_FBCAL_PD_VDDQ

FBC_DQS_DP<7>

FBC_DQS_DP<6>

FBC_DQS_DP<5>

FBC_DQS_DP<4>

FBC_DQS_DP<3>

FBC_DQS_DP<2>

FBC_DQS_DP<1>

FBC_DQS_DP<0>

FBC_DQS_DN<7>

FBC_DQS_DN<6>

FBC_DQS_DN<5>

FBC_DQS_DN<4>

FBC_DQS_DN<3>

FBC_DQS_DN<2>

FBC_DQS_DN<1>

FBC_DQS_DN<0>

FBC_DQM<7>

FBC_DQM<6>

FBC_DQM<5>

FBC_DQM<4>

FBC_DQM<3>

FBC_DQM<2>

FBC_DQM<1>

FBC_DQM<0>

+GPU_V1.5S_FBC_DEBUG

FBC_D<9>

FBC_D<8>

FBC_D<7>

FBC_D<63>

FBC_D<62>

FBC_D<61>

FBC_D<60>

FBC_D<6>

FBC_D<59>

FBC_D<58>

FBC_D<57>

FBC_D<56>

FBC_D<55>

FBC_D<54>

FBC_D<53>

FBC_D<52>

FBC_D<51>

FBC_D<50>

FBC_D<5>

FBC_D<49>

FBC_D<48>

FBC_D<47>

FBC_D<46>

FBC_D<45>

FBC_D<44>

FBC_D<43>

FBC_D<42>

FBC_D<41>

FBC_D<40>

FBC_D<4>

FBC_D<39>

FBC_D<38>

FBC_D<37>

FBC_D<36>

FBC_D<35>

FBC_D<34>

FBC_D<33>

FBC_D<32>

FBC_D<31>

FBC_D<30>

FBC_D<3>

FBC_D<29>

FBC_D<28>

FBC_D<27>

FBC_D<26>

FBC_D<25>

FBC_D<24>

FBC_D<23>

FBC_D<22>

FBC_D<21>

FBC_D<20>

FBC_D<2>

FBC_D<19>

FBC_D<18>

FBC_D<17>

FBC_D<16>

FBC_D<15>

FBC_D<14>

FBC_D<13>

FBC_D<12>

FBC_D<11>

FBC_D<10>

FBC_D<1>

FBC_D<0>

FBC_CMD<22>

FBC_CMD<1>

FBC_CMD<7>

FBC_CMD<14>

FBC_CMD<26>

FBC_CMD<10>

FBC_CMD<30>

FBC_CMD<0>

FBC_CMD<12>

FBC_CMD<19>

FBC_CMD<13>

FBC_CMD<6>

FBC_CMD<21>

FBC_CMD<4>

FBC_CMD<5>

FBC_CMD<17>

FBC_CMD<3>

FBC_CMD<28>

FBC_CMD<2>

FBC_CMD<16>

FBC_CMD<11>

FBC_CMD<27>

FBC_CMD<8>

FBC_CMD<29>

FBC_CMD<9>

FBC_CMD<18>

FBC_CMD<24>

FBC_CMD<20>

FBC_CLK1_DN

FBC_CLK1_DP

FBC_CLK0_DN

FBC_CLK0_DP

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

74<> 73<>

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0.1UF_16V_2

1UF_6.3V_2

0.1UF_16V_2 0.1UF_16V_2

10K_5%_2

74<

12

30

13

19

6

4

21

17

5

3

16

28

11

27

29

8

9

18

24

10UF_6.3V_3

FBM_10_160808_301A05T_500mA

0.1UF_16V_2

P1V05_GPUS

10UF_6.3V_3

60.4_1%_2

P1V5_GPUS

22

20

1

14

7

10

26

0

2

25

74<73<

74<>73<>

0.1UF_16V_2

1uF_6.3V_2

P1V5_GPUS

76<> 75<>

4.7uF_6.3V_3

NVIDIA_N12P_GS_BGA_973P

P1V05_GPUS

7

6

5

4

3

2

1

7

6

0

5

4

3

2

1

0

6

7

5

3

4

1

2

0

63

62

61

60.4_1%_2 40.2_1%_2

40.2_1%_2

P1V5_GPUS

76<

30

12

19

13

6

21

4

5

17

3

28

16

11

27

8

29

9

18

24

20

60.4_1%_2

P1V5_GPUS

2260

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

2

3

1

0

1

7

14

26

10

0

2

25

75<>

75< 76<

76<>

0.1UF_16V_2

1UF_6.3V_2

4.7UF_6.3V_3

ES

CS_1310AXXXXXX-MTR

A01

DATE

2

CODE

INVENTEC

DOC.NUMBER

TITLE

of

A

E

D

C

B

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

REV

CHANGE by

EVEREST

1

SHEET

SIZE

BI

OUT

3/16 FBB

GF108

FBB_CMD7

FBB_CMD1

FBB_CMD22

FBB_CMD20

FBB_CMD24

FBB_CMD18

FBB_CMD21

FBB_CMD5

FBB_CMD17

FBB_CMD28

N/A

FBB_CMD30

FBB_CMD11

FBB_CMD16

FBB_CMD3

FBB_CMD4

FBB_CMD6

FBB_CMD13

FBB_CMD19

FBB_CMD12

FBB_CMD8

FBB_CMD26

FBB_CMD15

FBB_CMD27

FBB_CMD29

FBB_CMD0

FBB_CMD23

GT21X

FBB_CMD25

FBB_CMD2

FBB_CMD10

FBB_CMD14

FBB_CMD9

FB_CAL_TERM_GND

FB_CAL_PU_GND

FB_CAL_PD_VDDQ

FBVDDQ_38

FBVDDQ_37

FBVDDQ_36

FBVDDQ_35

FBVDDQ_34

FBVDDQ_33

FBVDDQ_32

FBVDDQ_31

FBVDDQ_30

FBVDDQ_29

FBVDDQ_28

FBB_WCK3*

FBB_WCK3

FBB_WCK2*

FBB_WCK2

FBB_WCK1*

FBB_WCK1

FBB_WCK0*

FBB_WCK0

FBB_DQS_WP7

FBB_DQS_WP6

FBB_DQS_WP5

FBB_DQS_WP4

FBB_DQS_WP3

FBB_DQS_WP2

FBB_DQS_WP1

FBB_DQS_WP0

FBB_DQS_RN7

FBB_DQS_RN6

FBB_DQS_RN5

FBB_DQS_RN4

FBB_DQS_RN3

FBB_DQS_RN2

FBB_DQS_RN1

FBB_DQS_RN0

FBB_DQM7

FBB_DQM6

FBB_DQM5

FBB_DQM4

FBB_DQM3

FBB_DQM2

FBB_DQM1

FBB_DQM0

FBB_DEBUG1

FBB_DEBUG0_CAS2

FBB_D9

FBB_D8

FBB_D7

FBB_D63

FBB_D62

FBB_D61

FBB_D60

FBB_D6

FBB_D59

FBB_D58

FBB_D57

FBB_D56

FBB_D55

FBB_D54

FBB_D53

FBB_D52

FBB_D51

FBB_D50

FBB_D5

FBB_D49

FBB_D48

FBB_D47

FBB_D46

FBB_D45

FBB_D44

FBB_D43

FBB_D42

FBB_D41

FBB_D40

FBB_D4

FBB_D39

FBB_D38

FBB_D37

FBB_D36

FBB_D35

FBB_D34

FBB_D33

FBB_D32

FBB_D31

FBB_D30

FBB_D3

FBB_D29

FBB_D28

FBB_D27

FBB_D26

FBB_D25

FBB_D24

FBB_D23

FBB_D22

FBB_D21

FBB_D20

FBB_D2

FBB_D19

FBB_D18

FBB_D17

FBB_D16

FBB_D15

FBB_D14

FBB_D13

FBB_D12

FBB_D11

FBB_D10

FBB_D1

FBB_D0

FBB_CMD9

FBB_CMD8

FBB_CMD7

FBB_CMD6

FBB_CMD5

FBB_CMD4

FBB_CMD31

FBB_CMD30

FBB_CMD3

FBB_CMD29

FBB_CMD28

FBB_CMD27

FBB_CMD26

FBB_CMD25

FBB_CMD24

FBB_CMD23

FBB_CMD22

FBB_CMD21

FBB_CMD20

FBB_CMD2

FBB_CMD19

FBB_CMD18

FBB_CMD17

FBB_CMD16

FBB_CMD15

FBB_CMD14

FBB_CMD13

FBB_CMD12

FBB_CMD11

FBB_CMD10

FBB_CMD1

FBB_CMD0

FBB_CLK1*

FBB_CLK1

FBB_CLK0*

FBB_CLK0

IN

OUT

BI

OUT

RFU

GT21X GF108

GF108 GT21X

FB_VREF

FBA_CMD7

FBA_CMD1

FBA_CMD14

FBA_CMD26

FBA_CMD25

FBA_CMD23

FBA_CMD0

FBA_CMD10

FBA_CMD22

FBA_CMD20

FBA_CMD24

FBA_CMD18

FBA_CMD9

FBA_CMD30

FBA_CMD12

FBA_CMD19

FBA_CMD13

FBA_CMD6

FBA_CMD21

FBA_CMD4

FBA_CMD5

FBA_CMD17

FBA_CMD3

FBA_CMD28

FBA_CMD16

FBA_CMD11

FBA_CMD15

FBA_CMD27

FBA_CMD8

FBA_CMD29

N/A

GF108

GT21X

FBA_CMD2

2/16 FBA

FB_VREF_NC

FB_PLLAVDD_2

FB_PLLAVDD_1

FB_DLLAVDD_2

FB_DLLAVDD_1

FBVDDQ_9

FBVDDQ_8

FBVDDQ_7

FBVDDQ_6

FBVDDQ_5

FBVDDQ_4

FBVDDQ_3

FBVDDQ_27

FBVDDQ_26

FBVDDQ_25

FBVDDQ_24

FBVDDQ_23

FBVDDQ_22

FBVDDQ_21

FBVDDQ_20

FBVDDQ_2

FBVDDQ_19

FBVDDQ_18

FBVDDQ_17

FBVDDQ_16

FBVDDQ_15

FBVDDQ_14

FBVDDQ_13

FBVDDQ_12

FBVDDQ_11

FBVDDQ_10

FBVDDQ_1

FBA_WCK3*

FBA_WCK3

FBA_WCK2*

FBA_WCK2

FBA_WCK1*

FBA_WCK1

FBA_WCK0*

FBA_WCK0

FBA_DQS_WP7

FBA_DQS_WP6

FBA_DQS_WP5

FBA_DQS_WP4

FBA_DQS_WP3

FBA_DQS_WP2

FBA_DQS_WP1

FBA_DQS_WP0

FBA_DQS_RN7

FBA_DQS_RN6

FBA_DQS_RN5

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN2

FBA_DQS_RN1

FBA_DQS_RN0

FBA_DQM7

FBA_DQM6

FBA_DQM5

FBA_DQM4

FBA_DQM3

FBA_DQM2

FBA_DQM1

FBA_DQM0

FBA_DEBUG1

FBA_DEBUG0_CAS2

FBA_D9

FBA_D8

FBA_D7

FBA_D63

FBA_D62

FBA_D61

FBA_D60

FBA_D6

FBA_D59

FBA_D58

FBA_D57

FBA_D56

FBA_D55

FBA_D54

FBA_D53

FBA_D52

FBA_D51

FBA_D50

FBA_D5

FBA_D49

FBA_D48

FBA_D47

FBA_D46

FBA_D45

FBA_D44

FBA_D43

FBA_D42

FBA_D41

FBA_D40

FBA_D4

FBA_D39

FBA_D38

FBA_D37

FBA_D36

FBA_D35

FBA_D34

FBA_D33

FBA_D32

FBA_D31

FBA_D30

FBA_D3

FBA_D29

FBA_D28

FBA_D27

FBA_D26

FBA_D25

FBA_D24

FBA_D23

FBA_D22

FBA_D21

FBA_D20

FBA_D2

FBA_D19

FBA_D18

FBA_D17

FBA_D16

FBA_D15

FBA_D14

FBA_D13

FBA_D12

FBA_D11

FBA_D10

FBA_D1

FBA_D0

FBA_CMD9

FBA_CMD8

FBA_CMD7

FBA_CMD6

FBA_CMD5

FBA_CMD4

FBA_CMD31

FBA_CMD30

FBA_CMD3

FBA_CMD29

FBA_CMD28

FBA_CMD27

FBA_CMD26

FBA_CMD25

FBA_CMD24

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD20

FBA_CMD2

FBA_CMD19

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_CMD15

FBA_CMD14

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD10

FBA_CMD1

FBA_CMD0

FBA_CLK1*

FBA_CLK1

FBA_CLK0*

FBA_CLK0

GPU-3

Frank Hu

EVEREST-M

Fri Dec 31 10:17:04 2010

97

70

2

1

C5055

2

1

C5052

2

1

C5053

2

1

C5054

2

1

C5118

2

1

C5124

2

1

C5112

2

1

C5113

2

1

C5114

2

1

C5115

2

1

C5116

2

1

C5117

2

1

C5119

2

1

C5125

2

1

C5123

2

1

C5122

2

1

C5121

2

1

C5120

2

1

C5126

2

1

C5127

2

1

C5128

2

1

C5129

2

1

C5130

2

1

C5131

AA19

AP33

AA18

AP30

AP3

AP27

AP24

AP21

AP18

AP15

AP12

AN34

AN2

AA17

AL9

AL6

AL30

AL27

AL24

AL21

AL18

AL15

AL12

AK5

AA16

AK34

AK31

AK2

AG5

AG34

AG31

AG2

AE25

AE24

AE23

AA15

AE22

AE21

AE20

AE19

AE18

AE17

AE16

AE15

AE14

AE13

AA14

AE12

AE11

AD5

AD34

AD31

AD25

AD23

AD21

AD2

AD17

AA13

AD15

AD13

AD11

AC9

AB24

AB22

AB20

AB18

AB16

AB14

AA12

Y25

Y23

AB12

Y21

Y19

Y17

Y15

Y13

Y11

V9

V5

V31

V24

AA5

V22

V20

V2

V18

V16

V14

V12

U25

U24

U23

AA34

U22

U21

U20

U19

U18

U17

U16

U15

U14

U13

AA25

U12

U11

T25

T23

T21

T19

T17

T15

T13

T11

AA24

R5

R34

R31

R2

P24

P22

P20

P18

P16

P14

AA23

P12

N25

N24

N23

N22

N21

N20

N19

N18

N17

AA22

N16

N15

N14

N13

N12

N11

M5

M34

M31

M25

AA21

M23

M21

M2

M19

M17

M15

M13

M11

L9

J5

AA20

J34

J31

J2

F5

F34

F31

F2

E9

E6

E30

AA2

AA11

E27

E24

E18

E15

E12

C34

C2

B9

B6

B33

B30

B3

B27

B24

B21

B15

B12

AP9

AP6

U5000

Y24

Y22

Y20

Y18

Y16

Y14

Y12

W25

W24

W23

W22

W21

W20

W19

W18

W17

W16

W15

W14

W13

W12

W11

V25

V23

V21

V19

V17

V15

V13

V11

T24

T22

T20

T18

T16

T14

T12

R25

R24

R23

R22

R21

R20

R19

R18

R17

R16

R15

R14

R13

R12

R11

P25

P23

P21

P19

P17

P15

P13

P11

M24

M22

M20

M18

M16

M14

M12

L25

L24

L23

L22

L21

L20

L19

L18

L17

L16

L15

L14

L13

L12

L11

AD24

AD22

AD18

AD16

AD14

AD12

AC25

AC24

AC23

AC22

AC21

AC20

AC19

AC18

AC17

AC16

AC15

AC14

AC13

AC12

AC11

AB25

AB23

AB21

AB19

AB17

AB15

AB13

AB11

U5000

0.01UF_50V_2

0.047UF_16V_2

22UF_6.3V_5

CS_1310AXXXXXX-MTR

NVIDIA_N12P_GS_BGA_973P

4.7uF_6.3V_3

0.047UF_16V_2

0.015UF_10V_2

4700PF_50V_2

PVCORE_GPU PVCORE_GPU

PVCORE_GPU

10uF_6.3V_3

0.015UF_10V_2

10uF_6.3V_3

1uF_6.3V_2

0.022uF_16V_2

0.01UF_50V_2

0.1UF_16V_2 0.1UF_16V_2

0.022uF_16V_2

0.01UF_50V_2

0.22UF_6.3V_2

0.022uF_16V_2

0.01UF_50V_2

0.22UF_6.3V_2

0.047UF_16V_2

0.22UF_6.3V_2

6800PF_25V_2

CS A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

15/16 GND

GND_9

GND_80

GND_8

GND_79

GND_78

GND_77

GND_76

GND_75

GND_74

GND_73

GND_72

GND_71

GND_70

GND_7

GND_69

GND_68

GND_67

GND_66

GND_65

GND_64

GND_63

GND_62

GND_61

GND_60

GND_6

GND_59

GND_58

GND_57

GND_56

GND_55

GND_54

GND_53

GND_52

GND_51

GND_50

GND_5

GND_49

GND_48

GND_47

GND_46

GND_45

GND_44

GND_43

GND_42

GND_41

GND_40

GND_4

GND_39

GND_38

GND_37

GND_36

GND_35

GND_34

GND_33

GND_32

GND_31

GND_30

GND_3

GND_29

GND_28

GND_27

GND_26

GND_25

GND_24

GND_23

GND_22

GND_21

GND_20

GND_2

GND_191

GND_190

GND_19

GND_189

GND_188

GND_187

GND_186

GND_185

GND_184

GND_183

GND_182

GND_181

GND_180

GND_18

GND_179

GND_178

GND_177

GND_176

GND_175

GND_174

GND_173

GND_172

GND_171

GND_170

GND_17

GND_169

GND_168

GND_167

GND_166

GND_165

GND_164

GND_163

GND_162

GND_161

GND_160

GND_16

GND_159

GND_158

GND_157

GND_156

GND_155

GND_154

GND_153

GND_152

GND_151

GND_150

GND_15

GND_149

GND_148

GND_147

GND_146

GND_145

GND_144

GND_143

GND_142

GND_141

GND_140

GND_14

GND_139

GND_138

GND_137

GND_136

GND_135

GND_134

GND_133

GND_132

GND_131

GND_130

GND_13

GND_129

GND_128

GND_127

GND_126

GND_125

GND_124

GND_123

GND_122

GND_121

GND_120

GND_12

GND_119

GND_118

GND_117

GND_116

GND_115

GND_114

GND_113

GND_112

GND_111

GND_110

GND_11

GND_109

GND_108

GND_107

GND_106

GND_105

GND_104

GND_103

GND_102

GND_101

GND_100

GND_10

GND_1

GND_099

GND_098

GND_097

GND_096

GND_095

GND_094

GND_093

GND_092

GND_091

GND_090

GND_089

GND_088

GND_087

GND_086

GND_085

GND_084

GND_083

GND_082

GND_081

16/16 NVVDD

VDD_111

VDD_110

VDD_109

VDD_108

VDD_107

VDD_106

VDD_105

VDD_104

VDD_103

VDD_102

VDD_101

VDD_100

VDD_099

VDD_098

VDD_097

VDD_096

VDD_095

VDD_094

VDD_093

VDD_092

VDD_091

VDD_090

VDD_089

VDD_088

VDD_087

VDD_086

VDD_085

VDD_084

VDD_083

VDD_082

VDD_081

VDD_080

VDD_079

VDD_078

VDD_077

VDD_076

VDD_075

VDD_074

VDD_073

VDD_072

VDD_071

VDD_070

VDD_069

VDD_068

VDD_067

VDD_066

VDD_065

VDD_064

VDD_063

VDD_062

VDD_061

VDD_060

VDD_059

VDD_058

VDD_057

VDD_056

VDD_055

VDD_054

VDD_053

VDD_052

VDD_051

VDD_050

VDD_049

VDD_048

VDD_047

VDD_046

VDD_045

VDD_044

VDD_043

VDD_042

VDD_041

VDD_040

VDD_039

VDD_038

VDD_037

VDD_036

VDD_035

VDD_034

VDD_033

VDD_032

VDD_031

VDD_030

VDD_029

VDD_028

VDD_027

VDD_026

VDD_025

VDD_024

VDD_023

VDD_022

VDD_021

VDD_020

VDD_019

VDD_018

VDD_017

VDD_016

VDD_015

VDD_014

VDD_013

VDD_012

VDD_011

VDD_010

VDD_009

VDD_008

VDD_007

VDD_006

VDD_005

VDD_004

VDD_003

VDD_002

VDD_001

20mil

GPU-4

20mil

EVEREST-M

Frank Hu

71

97

Tue Jan 04 00:15:45 2011

4.7uF_6.3V_3

1uF_6.3V_2 0.1UF_16V_2

AM13

NVIDIA_N12P_GS_BGA_973P

1UF_6.3V_2_DY

AP2

AN3

AR2

GPU_HDMI_TXC_DN

GPU_HDMI_TXC_DP

GPU_HDMI_TX0_DN

AM3

AM4

U5000

+GPU_V3S_DACA_VDD

C5105

BLM15AG221SN1D_300mA

C5104

AK13

AJ8

2

1

C5108

1K_1%_2

0.1UF_16V_2_DY

0.1UF_16V_2

4.7UF_6.3V_3

GPU_CRT_VSYNC

GPU_CRT_R

GPU_CRT_G

GPU_CRT_B

C5110C5111

FBM_10_160808_301A05T_500mA

C5106

2

1

C5040

2

1

C5041

2

1

C5048

2

1

C5049

2

1

C5050

2

1

R5022

2

1

R5023

2

1

C5051

2

1

2

1

R5024

G2

G3

AM2

AK6

AG7

AH7

AK4

AM1

AL4

AJ4

U5000

2

1

R5064

2

1

R5034

2

1

R5035

2

1

R5070

AB6

AC6

AR4

AR5

AP5

AN5

AN7

AP7

AR7

AR8AK8

AN4

AP4

L7

U5000

2

1

R5068

2

1

C5101

2

1

C5102

2

1

C5103

2

1

C5100

2

1

L5003

2

1

R5065

2

1

R5066

2

1

R5067

G4

G1

AL13

AK12

AJ12

AM15

AM14

AL14

2

1

L5004

2

C5107

2

1

2

1

C5109

2

1

2

1

L5008

2

1

2

1

2

1

R5071

2

1

R5028

2

1

R5029

2

1

R5069

AH3

AH2

AH1

AJ1

AJ2

AJ3

AL3

AL2

AD7

AF2

AF3

AL1

AJ6 AE5

AE6

AF5

AF4

AG4

AH4

AH5

AH6

AE7

AD4

AE4

K6

L1

U5000

AK7

AJ9

AP1

AM5

AL5

AM6

AM7

K2

U5000

2

1

C5096

2

1

L5005

2

1

C5095

2

1

C5097

2

1

C5099

2

1

C5098

2

1

C5091

2

1

L5001

2

1

C5092

2

1

C5093

2

1

C5094

2

1

R5072

AP11

AN11

AR10

AR11

AN10

AP10

AP8

AN8

AN13

AP13

AG10

AJ11

AK9

AL11

AK11

AL10

AK10

AM9

AM10

AL8

AM8

AM12

AM11

AG9

K1

U5000

0.1UF_16V_2

0.1UF_6.3V_1

124_1%_2

1uF_6.3V_2

+GPU_V3S_IFPA_IOVDD

4.7uF_6.3V_3

MMZ1608S181AT

1K_1%_2_DY

P3V3_GPUS

GPU_HDMI_TX0_DP

GPU_HDMI_TX1_DN

GPU_HDMI_TX1_DP

GPU_HDMI_TX2_DP

GPU_HDMI_HPDET

2.2K_1%_2

10K_5%_2_DY

IFPCD_PLLVDD

4.7uF_6.3V_3

0.1UF_16V_2

NVIDIA_N12P_GS_BGA_973P

150_1%_2

4.7uF_6.3V_3

GPU_HDMI_TX2_DN

GPU_CRT_HSYNC

GPU_LVDS1_TXDL0_DP

GPU_LVDS1_TXDL0_DN

GPU_LVDS1_TXDL1_DN

GPU_LVDS1_TXDL1_DP

GPU_LVDS1_TXDL2_DN

GPU_LVDS1_TXDL2_DP

GPU_LVDS1_TXCL_DN

GPU_LVDS1_TXCL_DP

GPU_LVDS2_TXDL0_DN

GPU_LVDS2_TXDL0_DP

+GPU_V1.05S_IFPAB_PLLVDD

GPU_LVDS2_TXDL1_DN

GPU_LVDS2_TXDL1_DP

GPU_LVDS2_TXDL2_DN

GPU_LVDS2_TXDL2_DP

GPU_LVDS2_TXCL_DN

GPU_LVDS2_TXCL_DP

NVIDIA_N12P_GS_BGA_973P

10K_5%_2

NVIDIA_N12P_GS_BGA_973P

45<

150_1%_2150_1%_2

10K_5%_2

0.1UF_16V_2_DY

IFPCD_IOVDD

0.1UF_16V_2

1K_1%_2

0.1UF_16V_21uF_6.3V_2

P1V05_GPUS

4.7uF_6.3V_3

P3V3_GPUS

NVIDIA_N12P_GS_BGA_973P

P1V05_GPUS

0.1UF_16V_2_DY

0.1UF_16V_2_DY1uF_6.3V_2

FBM_10_160808_301A05T_500mA

P3V3_GPUS

4.7uF_6.3V_3

0.1UF_16V_2

4.7uF_6.3V_3

MMZ1608S181AT

P3V3_GPUS

4.7uF_6.3V_3

1K_1%_2_DY

10K_5%_2

NVIDIA_N12P_GS_BGA_973P

10K_5%_2

C

CS_1310AXXXXXX-MTR

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

OUT

4/16 DACA

I2CA_SDA

I2CA_SCL

DACA_VSYNC

DACA_VREF

DACA_VDD

DACA_RSET

DACA_RED

DACA_HSYNC

DACA_GREEN

DACA_BLUE

IN

OUT

IFPEF

HDMI

DVI-SL

DP

HPDE

TXD2

TXD1

TXD0

DVI-DL

SDA

TXC

TXD0

TXC

SCL

HPDE

SCL

TXD2

TXD1

TXD0

TXC

SDA

SCL

TXC

TXD0

TXD1

TXD2

HPDF

TXD5

TXD4

TXD3

TXD4

9/16 IFPEF

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

IFPF_IOVDD

IFPF_AUX*

IFPF_AUX

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_IOVDD

IFPE_AUX*

IFPE_AUX

IFPEF_RSET

IFPEF_PLLVDD

GPIO21

GPIO15

HPDC

IFPC

DP

SCL

TXC

TXD0

TXD1

TXD2

SDA

DVI/HDMI

8/16 IFPC

IFPC_RSET

IFPC_PLLVDD

IFPC_L3*

IFPC_L3

IFPC_L2*

IFPC_L2

IFPC_L1*

IFPC_L1

IFPC_L0*

IFPC_L0

IFPC_IOVDD

IFPC_AUX*

IFPC_AUX

GPIO1

OUT

6/16 DACB

I2CB_SDA

I2CB_SCL

DACB_VSYNC

DACB_VREF

DACB_VDD

DACB_RSET

DACB_RED

DACB_HSYNC

DACB_GREEN

DACB_BLUE

HPDD

IFPD

TXC

DP

SDA

TXD1

TXD0

TXD2

SCL

DVI/HDMI

5/16 IFPD

IFPD_RSET

IFPD_PLLVDD

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

IFPD_IOVDD

IFPD_AUX*

IFPD_AUX

GPIO19

HPDAB

IFPAB

LVDS

IFPAB_TXD3*

IFPAB_TXD3

IFPAB_TXD0

IFPAB_TXD1*

IFPAB_TXD0*

DVI-DL

IFPAB_TXD1

IFPAB_TXD5*

IFPAB_TXD5

IFPAB_TXC*

IFPAB_TXC

IFPAB_TXD2*

IFPAB_TXD2

IFPAB_TXD4

IFPAB_TXD4*

7/16 IFPAB

IFPB_TXD7*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD4*

IFPB_TXD4

IFPB_TXC*

IFPB_TXC

IFPB_IOVDD

IFPA_TXD3*

IFPA_TXD3

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD0*

IFPA_TXD0

IFPA_TXC*

IFPA_TXC

IFPA_IOVDD

IFPAB_RSET

IFPAB_PLLVDD

GPIO0

20mil

GPU-5

PUT TOGETHER

24.9K_1% FOR NVIDIA_N12P_GS_BGA_973P

72

Frank Hu

EVEREST-M

Fri Dec 31 10:16:52 2010

97

2

1

R5001

2

1

R5020

2

1

R5019

2

1

R5018

2

1

R5021

2

1

R5036

2

1

R5052

2

1

R5050

2

1

R5009

2

1

R5030

2

1

R5033

2

1

R5043

2

1

R5032

2

1

R5031

2

1

R5015

2

1

R5014

2

1

R5013

2

1

R5010

2

1

R5012

2

1

R5011

2

1

R5008

2

1

R5007

2

1

R5004

2

1

R5005

2

1

R5006

2

1

C5088

2

1

R5057

2

1

R5058

2

1

R5061

2

1

R5062

2

1

R5063

V7

W7

W5

A5

C4

D3

D4

C3

C5

M9

N9

G6

F6

K9

AK14

AB5

A4

J25

J26

U5000

2

1

R5044

2

1

R5045

2

1

R5025

2

1

R5046

2

1

R5051

2

1

R5060

2

1

R5059

2

1

3

Q5000

2

1

R5049

2

1

R5042

2

1

R5055

2

1

R5056

2

1

R5053

2

1

R5054

2

1

C5089

2

1

C5090

1

4

7

8

5

2

3 6

U4412

B5

B4

AP16

AR14

AN16

AN14

AP14

E1

E2

E4

E3

J7

H6

H5

H4

H1

H2

H3

M7

M6

L6

L5

K3

M4

L4

L2

J6

J4

H7

K5

K4

U5000

2

1

R5047

2

1

C5086

W2

AF1

Y9

W9

AB9

AA9

W1

Y5

AC3

AC2

AC1

AC4

AB1

AB2

AB3

Y3

Y2

Y6

W6

U6

AE2

AE3

Y1

W3

W4

V4

AE1

AA6

AA7

U5000

2

1

R5048

2

1

C5087

L3

N5

U9

T9

R9

P9

N3

N2

U1

U4

T1

T2

T3

P3

P2

P1

P4

N6

T6

R6

U3

U2

N1

P5

T4

R4

N4

T5

U5

U5000

ROM_SI

NVIDIA_N12P_GS_BGA_973P

10K_5%_2_DY

24.9K_1%_2

0_5%_2

2.2K_1%_2

72>

THRM_GPU_DN

THRM_SHUTDWN#

THRM_GPU_DN

THRM_GPU_DP

P3V3_GPUS

10K_5%_2

0_5%_2_DY

10K_5%_2 10K_5%_2 10K_5%_2

GPU_VID1

GPU_VID0

GPU_LCM_BKLTEN

GPU_LCM_VDDEN

ROM_SO

ROM_SCLK

72<

2.2K_1%_2

CS

CS_1310AXXXXXX-MTR

ALERT#

THRM_GPU_DP

DCIN_BLED#

THRM_SHUTDWN#

EC_SMB2_DATA

EC_SMB2_CLK

GPU_LVDS_DDCDATA

GPU_LVDS_DDCCLK

STRAP0

STRAP1

STRAP2

ROM_SCLK

ROM_SI

ROM_SO

GPU_LCM_INVPWM

STRAP2

STRAP1

STRAP0

0_5%_2_DY

10K_5%_2

10K_5%_2 10K_5%_2

NVIDIA_N12P_GS_BGA_973P

72<

2200PF_50V_2_DY

0.1UF_16V_2_DY

P3V3_GPUS

GMT_G784_MSOP_8P__DY

SSM3K7002BFU

58<37>

10K_5%_2

100K_5%_2

P3V3_GPUS

0_5%_2_DY

0_5%_2

10K_5%_2 10K_5%_2

0_5%_2 0_5%_2

10K_5%_2

P3V3_GPUS

10K_5%_2

0_5%_2

P3V3_GPUS

0_5%_2

37<>

8>

37<>

8>

72<

45.3K_1%_2

10K_5%_2_DY 10K_5%_2_DY

34.8K_1%_2

P3V3_GPUS

72>

15K_1%_2

10K_5%_2_DY

10K_1%_2 10K_5%_2_DY

10K_5%_2_DY 15K_1%_2

P3V3_GPUS

40.2K_1%_2

10K_5%_2

16<

P3V3_GPUS

NVIDIA_N12P_GS_BGA_973P

NVIDIA_N12P_GS_BGA_973P 10K_5%_2

36K_5%_2

72<

2.2K_1%_2 0.1uF_16V_2

P3V3_GPUS

10K_5%_2

0.1UF_16V_2

P3V3_GPUS

0.1UF_16V_2

P3V3_GPUS

A01

C

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

11/16 MIOB

MIOB_VSYNC_NC

MIOB_VREF_NC

MIOB_VDDQ_NC_4

MIOB_VDDQ_NC_3

MIOB_VDDQ_NC_2

MIOB_VDDQ_NC_1

MIOB_HSYNC_NC

MIOB_DE_NC

MIOB_D9_NC

MIOB_D8_NC

MIOB_D7_NC

MIOB_D6_NC

MIOB_D5_NC

MIOB_D4_NC

MIOB_D3_NC

MIOB_D2_NC

MIOB_D1_NC

MIOB_D14_NC

MIOB_D13_NC

MIOB_D12_NC

MIOB_D11_NC

MIOB_D10_NC

MIOB_D0_NC

MIOB_CTL3_NC

MIOB_CLKOUT_NC*

MIOB_CLKOUT_NC

MIOB_CLKIN_NC

MIOB_CAL_PU_GND_NC

MIOB_CAL_PD_VDDQ_NC

OUT

13/16 MISC2

STRAP2

STRAP1

STRAP0

SPDIF_NC

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

PGOOD_OUT*

MULTI_STRAP_REF1_GND

MULTI_STRAP_REF0_GND

I2CH_SDA

I2CH_SCL

GND_H

GND_F

CEC

BUFRST*

BBIASP_NC

BBIASN_NC

OUT

BI

G

DS

BI

OUT

IN

GND

ALERT#

SMBDATA

SMBCLK

THERM#

DXN

DXP

VCC

OUT

12/16 MISC1

THERMDP

THERMDN

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

I2CS_SDA

I2CS_SCL

I2CC_SDA

I2CC_SCL

GPIO9

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO24

GPIO23

GPIO22

GPIO20

GPIO2

GPIO18

GPIO17

GPIO16

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

IN

10/16 MIOA

MIOA_VSYNC_NC

MIOA_VREF_NC

MIOA_VDDQ_NC_4

MIOA_VDDQ_NC_3

MIOA_VDDQ_NC_2

MIOA_VDDQ_NC_1

MIOA_HSYNC_NC

MIOA_DE_NC

MIOA_D9_NC

MIOA_D8_NC

MIOA_D7_NC

MIOA_D6_NC

MIOA_D5_NC

MIOA_D4_NC

MIOA_D3_NC

MIOA_D2_NC

MIOA_D1_NC

MIOA_D14_NC

MIOA_D13_NC

MIOA_D12_NC

MIOA_D11_NC

MIOA_D10_NC

MIOA_D0_NC

MIOA_CTL3_NC

MIOA_CLKOUT_NC*

MIOA_CLKOUT_NC

MIOA_CLKIN_NC

MIOA_CAL_PU_GND_NC

MIOA_CAL_PD_VDDQ_NC

1.5A

VRAM

1.5A

EVEREST-M

Frank Hu

97

73

Fri Dec 31 10:16:52 2010

2

1

R5524

2

1

C5552

2

1

R5500

2

1

C5551

2

1

C5550

2

1

C5503

2

1

R5501

2

1

C5549

2

1

C5548

2

1

C5547

2

1

C5546

2

1

C5501

2

1

R5504

2

1

R5505

2

1

C5553

2

1

C5554

2

1

C5555

2

1

C5556

2

1

C5557

2

1

C5558

2

1

C5559

2

1

R5526

2

1

R5525

2

1

R5529

2

1

R5528

2

1

R5527

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5501

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5500

FBA_CMD<20>

69<>

73<

P1V5_GPUS

10K_5%_2

160_1%_2

0.1UF_16V_2 0.1UF_16V_2

P1V5_GPUS

CS_1310AXXXXXX-MTR

FBA_VREF0

FBA_CMD<18>

FBA_CMD<29>

FBA_CMD<30>

FBA_CMD<12>

FBA_CMD<9>

FBA_CMD<13>

FBA_CMD<0>

FBA_CMD<25>

FBA_CMD<2>

FBA_CMD<24>

FBA_CMD<8>

FBA_CMD<19>

FBA_CMD<28>

FBA_DQS_DN<3>

FBA_DQS_DN<0>

FBA_DQM<0>

FBA_DQM<3>

FBA_DQS_DP<0>

FBA_DQS_DP<3>

FBA_CLK0_DN

FBA_CLK0_DP

FBA_D<1>

FBA_D<5>

FBA_D<2>

FBA_D<4>

FBA_D<0>

FBA_D<7>

FBA_D<3>

FBA_D<6>

FBA_D<29>

FBA_D<25>

FBA_D<31>

FBA_D<28>

FBA_D<30>

FBA_D<24>

FBA_D<27>

FBA_D<26>

FBA_CMD<10>

FBA_CMD<1>

FBA_CMD<3>

FBA_CMD<26>

FBA_CMD<6>

FBA_CMD<17>

FBA_CMD<14>

FBA_CMD<4>

FBA_CMD<22>

FBA_CMD<5>

FBA_CMD<21>

FBA_CMD<7>

FBA_CMD<30..0>

FBA_VREF0

FBA_D<0..7>

FBA_D<24..31>

FBA_CMD<27>

FBA_CMD<25>

FBA_VREF1

FBA_CLK0_DN

FBA_CLK0_DP

FBA_DQS_DN<1>

FBA_CMD<28>

FBA_DQS_DN<2>

FBA_CMD<19>

FBA_CMD<8>

FBA_CMD<24>

FBA_CMD<2>

FBA_CMD<25>

FBA_CMD<0>

FBA_CMD<13>

FBA_DQM<1>

FBA_DQM<2>

FBA_DQS_DP<2>

FBA_DQS_DP<1>

FBA_D<9>

FBA_D<13>

FBA_D<8>

FBA_D<12>

FBA_D<10>

FBA_D<15>

FBA_D<11>

FBA_D<14>

FBA_D<19>

FBA_D<20>

FBA_D<17>

FBA_D<22>

FBA_D<18>

FBA_D<23>

FBA_D<16>

FBA_D<21>

FBA_CLK0_DN

FBA_CLK0_DP

FBA_CMD<9>

FBA_CMD<12>

FBA_CMD<10>

FBA_CMD<1>

FBA_CMD<3>

FBA_CMD<26>

FBA_CMD<6>

FBA_CMD<17>

FBA_CMD<14>

FBA_CMD<4>

FBA_CMD<30>

FBA_CMD<29>

FBA_CMD<18>

FBA_CMD<22>

FBA_CMD<5>

FBA_CMD<21>

FBA_CMD<20>

FBA_CMD<7>

FBA_CMD<30..0>

FBA_VREF0

FBA_D<8..15>

FBA_D<16..23>

0.1UF_16V_2

P1V5_GPUS

1.1K_1%_2

0.1UF_16V_2 0.1UF_16V_2

18

29

30

12

9

13

0

25

2

24

8

19

73<

74<> 73<>

74< 69>

69<>

10K_5%_2

243_1%_2

73< 69>

0.1UF_16V_2

0.01UF_50V_2

1.1K_1%_2

P1V5_GPUS

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

0.1UF_16V_2 1uF_6.3V_2 1uF_6.3V_2

1

P1V5_GPUS

7

20

14

4

17

6

26

3

1

10

21

5

22

73<

5

2

4

0

7

6

3

29

28

31

25

30

24

27

26

69<>

0.1UF_16V_2

69>

74<> 73<>

69>

73<>74<>

0.1UF_16V_2

10K_5%_2

1.1K_1%_2

74<

0.01UF_50V_2

1.1K_1%_2

0.1UF_16V_2

69>73<

73< 69>

69<>

73<>74<>

74< 69>

69<>

19

8

24

2

25

0

13

69<>

243_1%_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

69>

73<

1uF_6.3V_2 1uF_6.3V_2

P1V5_GPUS

9

12

30

18

29

22

5

21

10

1

3

26

6

17

14

4

20

7

73<

8

12

13

9

P1V5_GPUS

11

14

15

10

69<>

17

22

20

19

21

16

23

18

69<>

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

BI

IN

BI

IN

BI

IN

BI

IN

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

BI

IN

BI

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

1.5A

VRAM

1.5A

Fri Dec 31 10:16:53 2010

Frank Hu

EVEREST-M

97

74

2

1

R5519

2

1

C5532

2

1

C5533

2

1

C5534

2

1

C5535

2

1

C5536

2

1

C5537

2

1

C5538

2

1

C5539

2

1

C5540

2

1

C5541

2

1

C5542

2

1

C5543

2

1

C5544

2

1

C5545

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5503

2

1

R5523

2

1

R5521

2

1

R5520

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5502

2

1

R5522

FBA_CMD<30>

P1V5_GPUS

74< 69>

74<>

10K_5%_2

160_1%_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

0.1UF_16V_2

FBA_CMD<5>

FBA_CMD<7>

FBA_CMD<19>

FBA_CMD<10>

FBA_CMD<29>

FBA_CMD<18>

FBA_CMD<13>

FBA_CMD<12>

FBA_CMD<14>

FBA_CMD<30>

FBA_CMD<27>

FBA_CMD<11>

FBA_CMD<16>

FBA_CMD<21>

FBA_CMD<24>

FBA_CMD<8>

FBA_CMD<28>

FBA_DQS_DN<7>

FBA_DQS_DN<5>

FBA_DQS_DP<5>

FBA_DQS_DP<7>

FBA_DQM<5>

FBA_DQM<7>

FBA_CLK1_DP

FBA_CLK1_DN

FBA_VREF1

FBA_D<63>

FBA_D<61>

FBA_D<60>

FBA_D<57>

FBA_D<62>

FBA_D<56>

FBA_D<59>

FBA_D<58>

FBA_D<40>

FBA_D<47>

FBA_D<42>

FBA_D<41>

FBA_D<45>

FBA_D<46>

FBA_D<43>

FBA_D<44>

FBA_CMD<1>

FBA_CMD<26>

FBA_CMD<3>

FBA_CMD<17>

FBA_CMD<6>

FBA_CMD<9>

FBA_CMD<20>

FBA_CMD<4>

FBA_CMD<22>

FBA_CMD<30..0>

FBA_D<56..63>

FBA_D<40..47>

FBA_CLK1_DN

FBA_CMD<16>

FBA_CMD<0>

FBA_CLK1_DP

FBA_CMD<28>

FBA_DQS_DN<6>

FBA_DQS_DN<4>

FBA_CMD<21>

FBA_CMD<8>

FBA_CMD<24>

FBA_CMD<11>

FBA_CMD<16>

FBA_CMD<27>

FBA_CMD<14>

FBA_CMD<12>

FBA_DQM<4>

FBA_DQM<6>

FBA_DQS_DP<6>

FBA_DQS_DP<4>

FBA_D<53>

FBA_D<49>

FBA_D<55>

FBA_D<50>

FBA_D<54>

FBA_D<48>

FBA_D<52>

FBA_D<51>

FBA_D<37>

FBA_D<34>

FBA_D<39>

FBA_D<33>

FBA_D<38>

FBA_D<32>

FBA_D<36>

FBA_D<35>

FBA_CLK1_DN

FBA_CLK1_DP

FBA_CMD<5>

FBA_CMD<1>

FBA_CMD<26>

FBA_CMD<3>

FBA_CMD<17>

FBA_CMD<6>

FBA_CMD<9>

FBA_CMD<20>

FBA_CMD<13>

FBA_CMD<18>

FBA_CMD<29>

FBA_CMD<7>

FBA_CMD<10>

FBA_CMD<19>

FBA_CMD<4>

FBA_CMD<22>

FBA_CMD<30..0>

FBA_VREF1

FBA_D<48..55>

FBA_D<32..39>

0.1UF_16V_2

P1V5_GPUS

0.1UF_16V_2 0.1UF_16V_2

243_1%_2

5

7

19

10

29

18

13

12

14

30

27

11

16

21

24

8

74<> 73<>

69>74< 73<

69<>

69>74<

0.1UF_16V_2 0.1UF_16V_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

1uF_6.3V_2 1uF_6.3V_2

63

61

60

57

62

P1V5_GPUS

22

4

20

9

6

26

17

3

1

74<

73<

56

58

59

40

47

42

41

45

69<>

44

43

46

69<>

0.1UF_16V_2 0.1UF_16V_2

P1V5_GPUS

74< 69>

73<>

69>

74<>

69>

73<>74<>

10K_5%_2

0.1UF_16V_2 0.1UF_16V_2

69>

74<

73<>

73<

69<>

21

8

24

11

16

27

30

14

12

69<>

243_1%_2

69>74<

1uF_6.3V_2 1uF_6.3V_2

P1V5_GPUS

13

18

29

7

10

19

5

1

26

3

17

6

9

20

4

22

74< 73<

53

49

50

55

52

48

54

51

34

37

39

33

38

32

36

69<>

35

69<>

P1V5_GPUS

C

A01

CS

CS_1310AXXXXXX-MTR

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

IN

BI

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

BI

IN

BI

IN

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

IN

BI

IN

1.5A

VRAM

1.5A

97

Frank Hu

EVEREST-M

Fri Dec 31 10:16:54 2010

75

2

1

R5514

2

1

R5506

2

1

C5502

2

1

R5507

2

1

R5503

2

1

C5500

2

1

R5502

2

1

C5518

2

1

C5519

2

1

C5520

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5505

2

1

R5518

2

1

C5521

2

1

C5522

2

1

C5523

2

1

C5524

2

1

R5516

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5504

2

1

C5525

2

1

C5526

2

1

C5527

2

1

C5528

2

1

R5517

2

1

R5515

2

1

C5529

2

1

C5530

2

1

C5531

1.1K_1%_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

FBC_D<2>

FBC_D<4>

7

FBC_D<24..31>

FBC_DQM(1)

FBC_DQSN(2)

FBC_CMD<28>

160_1%_2

0.1UF_16V_2

P1V5_GPUS

CS_1310AXXXXXX-MTR

FBC_VREF0

FBC_CMD<28>

FBC_CMD<19>

FBC_CMD<8>

FBC_CMD<24>

FBC_CMD<2>

FBC_CMD<25>

FBC_CMD<0>

FBC_CMD<13>

FBC_CMD<9>

FBC_CMD<12>

FBC_CMD<30>

FBC_CMD<29>

FBC_CMD<18>

FBC_DQS_DN<0>

FBC_DQS_DN<3>

FBC_DQM<3>

FBC_DQM<0>

FBC_DQS(3)

FBC_DQS_DP<0>

FBC_CLK0_DN

FBC_CLK0_DP

FBC_D<25>

FBC_D<30>

FBC_D<26>

FBC_D<29>

FBC_D<28>

FBC_D<31>

FBC_D<27>

FBC_D<24>

FBC_D<5>

FBC_D<1>

FBC_D<7>

FBC_D<0>

FBC_D<6>

FBC_D<3>

FBC_CMD<10>

FBC_CMD<1>

FBC_CMD<3>

FBC_CMD<26>

FBC_CMD<6>

FBC_CMD<17>

FBC_CMD<14>

FBC_CMD<4>

FBC_CMD<22>

FBC_CMD<5>

FBC_CMD<21>

FBC_CMD<20>

FBC_CMD<7>

FBC_CLK0_DN

FBC_CLK0_DP

FBC_CMD<30..0>

FBC_VREF0

FBC_D<0..7>

FBC_CMD<30..0>

FBC_VREF1

FBC_CMD<25>

FBC_DQSN(1)

FBC_CMD<19>

FBC_CMD<8>

FBC_CMD<24>

FBC_CMD<2>

FBC_CMD<25>

FBC_CMD<0>

FBC_CMD<13>

FBC_CMD<9>

FBC_DQM(2)

FBC_DQS(1)

FBC_DQS(2)

FBC_D<9>

FBC_D<15>

FBC_D<10>

FBC_D<12>

FBC_D<8>

FBC_D<14>

FBC_D<11>

FBC_D<13>

FBC_D<21>

FBC_D<22>

FBC_D<19>

FBC_D<23>

FBC_D<17>

FBC_D<20>

FBC_D<16>

FBC_D<18>

FBC_CLK0_DN

FBC_CLK0_DP

FBC_CMD<12>

FBC_CMD<10>

FBC_CMD<1>

FBC_CMD<3>

FBC_CMD<26>

FBC_CMD<6>

FBC_CMD<17>

FBC_CMD<14>

FBC_CMD<4>

FBC_CMD<30>

FBC_CMD<29>

FBC_CMD<18>

FBC_CMD<22>

FBC_CMD<5>

FBC_CMD<21>

FBC_CMD<20>

FBC_CMD<7>

FBC_VREF0

FBC_D<8..15>

FBC_D<16..23>

0.1UF_16V_2

P1V5_GPUS

1.1K_1%_2

0.1UF_16V_2 0.1UF_16V_2

76<>

69>

75<>

75<76<

19

8

24

2

25

0

13

9

12

30

29

18

10K_5%_2 243_1%_2

75< 69>

0.01UF_50V_2

1.1K_1%_2

P1V5_GPUS

0.1UF_16V_2 0.1UF_16V_2 1uF_6.3V_2 1uF_6.3V_2

69>

75<

69>

75<

25

P1V5_GPUS

5

22

21

10

1

3

26

6

17

14

4

20

7

75<

26

30

29

28

31

27

24

5

69<>

2

1

4

0

7

3

6

69<>

76<

0.1UF_16V_2

69>

76<> 75<>

P1V5_GPUS

10K_5%_2

0.1UF_16V_2

1.1K_1%_2 0.01UF_50V_2

0.1UF_16V_2 0.1UF_16V_2

19

8

24

2

25

0

13

9

243_1%_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

75<

69>

75<

69>

1uF_6.3V_2 1uF_6.3V_2

P1V5_GPUS

12

30

29

18

22

5

21

10

1

3

26

6

17

14

4

20

75<

9

15

10

12

8

P1V5_GPUS

14

13

11

69<>

22

21

19

23

17

18

16

20

69<>

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

IN

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

BI

IN

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

IN

BI

IN

BI

IN

BI

65W-75W 8A(6036A0003401)

90W 10A(6036A0002901)

FUSE6000

120W 12A(6036A0006001)

Active Low

WS

Active High

X01

9776

1310xxxxx-0-0

MODEL,PROJECT,FUNCTION

21-OCT-2002

XXX

FUSE6000

NFE31PT222Z1E9L

PVADPTR

4

3

C6033

10PF_50V_2

1000PF_50V_2

L6001

2

C6010

RSC_1206_DY

R6002

1

C6029

CSC0402_DY

CHG_EN

1

10K_5%_3_DY

R6014

2

R6011

SSM3K7002FU_DY

ACPRES#

R6013

3.3K_1%_3

EC_SMB2_CLK

EC_SMB2_DATA

HW_I_ADC

CSC0603_DY

1

20.5K_1%_2

R6012

10K_5%_3

100pF_50V_2

C6027

C6028

110K_1%_2

1

10_1%_2

R6010

1

30.1K_1%_2

2

CSC0402_DY

P3V3_AL

2

4.02K_1%_3

R6006

1M_5%_3

1

0.1UF_25V_3

2

R6023

DIODES_BAV99

C6013

0.1UF_25V_3

PVADPTR

0.1UF_25V_3

PVPACK

POWERPAD_2_0610

L6000

C6006

0.047uF_16V_2

2

BAT54C_30V_0.2A

1UF_10V_2

R6008

TI_BQ24725RGRR_QFN_20P

5

0.01_1%_6

AM4410NC

2

2200pF_50V_2

PVADPTR

1

R6000

4.7K_5%_3

1

CN6000

1

C6035

4

PVBAT

68UF_25V

1

Q6005

0.1uF_16V_2_DY

RSC_0603_DY

1

R6018

33K_5%_2_DY

R6019

PVBAT

RSC_0603_DY

1

R6017

2

PAD6000

4.02K_1%_3

R6015

10_5%_5

U6000

6

7

Q6004

2

C6011

C6008

C6026

1

P3V3_AL

2

CSC0402_DY

3

2

R6021

1

0.1UF_16V_2

C6014

1

HW_V_ADC

C6003

2

1

C6015

VRCHARGER_HG

VRCHARGER_PH

1

5

C6017

10

VRCHARGER_LG

1

2

1

2

1

D6000

2

C6012

R6007

Q6002

C6018

1

D6001

BAT54C_30V_0.2A

AM4410NC

1

AON7410

4.7UF_25V_5

2

C6001

4.7UF_25V_5

C6005

470pF_50V_2

1

C6002

Q6000

2

1

C6000

CSC0805_DY

2

3

2

1

45

6

7

8

TPCA8065_H

0.1uF_25V_3

D6002

D6003

C6009 R6004

C6025

C6023

C6019

C6016

Q6001

R6001

R6020

R6005

Q6003

R6003

C6007

C6024

R6009

C6004

C6021

R6016

C6022

C6020

2

1

2

1

2

1

2

1

2

3

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3

1

2

1

2

3

2

1

2

1

2

1

2

1

2

1

3

2

1

46

7

8

3

2

4 5

6

7

8

43 2

1

43 2

1

2

1

2

3

2

1

4 5

6

7

8

3

2

1

45

6

7

8

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

G2

G1

3

2

1

20

21

13

12

8

9

16

19

15

18

14

3

17

11

2

1

4

0.1UF_16V_2

CSC0805_DY

ACES_91302_0047L_1_4P

8A_125V

4.7UF_25V_5

CSC0805_DY

4.7UF_25V_5

4.02K_1%_3

6.98_1%_2

AON7410

SBR3U40P1_DY

0.0015uF_50V_2 2.2_5%_3

PCMC063T_4R7MN

0.1UF_25V_3

0.1UF_16V_2

0.01_1%_6

1UF_25V_3

RSC_0603_DY

P3V3_AL

Block Diagram

CS

C

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

OUT

C

A2

A1

C

A2

A1

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

+

NMOS_4D3S

D

G

S

1

2

1

G1

2

3

4

G2

IN

OUT

G

DS

VCC

TML

SRP

SRN

SDA

SCL

REGN

PHASE

LODRV

IOUT

ILIM

HIDRV

GND

CMSRC

BTST

BATDRV

ACP

ACOK

ACN

ACDRV

ACDET

REMOVE ?

77 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

BAT54C_30V_0.2A

D6105

P3V3_AL

1K_5%_2

R6106

CN6101

+V5AUXON

P5V_AL P5V_AL

1

R6105

PVBAT

THRM_SHUTDWN#

5

2

EZJZ0V120JA_DY

GMT_G686LT11U_SOT23_5P

2

PHP_PESD5V0S1BB_SOD523_2P

D6104

1

360K_1%_2

R6108

P5V_AL

2

R6109R6110

BATT_IN

EC_SMB1_DATA

EC_SMB1_CLK

1

33_5%_2

R6101

2

R6102

33_5%_2

2

1

PVPACK

1000PF_50V_2

C6106

1

R6100

D6102

D6103

D6106

FUSE6100

R6103

R6104

C6107

U6100

D6101

CN6100

D6100

2

1

2

1

2

1

2

1

2

1

3

2

1

2

1

2

1

2

1

2

1

43

1

2

1

2

1

2

1

2

1 1

2

1

2

5

6

7

3

9

8

G4

G3

G2

G1

2

1

4

LOTES_AAA_BAT_059_P03_2P

0.1uF_16V_2

10K_5%_2

510K_1%_2

100K_1%_2

EZJZ0V500AA

715K_1%_2

1K_5%_2

PHP_PESD5V0S1BB_SOD523_2P

LITTLEFUSE_R451015_15A_65V

102K_1%_3

EZJZ0V500AA

PHP_PESD5V0S1BB_SOD523_2P

SYN_200045GR009G15JZR_9P

PVRTC

Block Diagram

CS

C

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

OUT

IN

BI

OUT

1

2

1

2

1

2

-+

C

A2

A1

RESET

GND

VCC

MR

VSEN

G

GND

SMC

SMD

TS

B-I

ID

BATT+

4A

10A

7A

CHECK

WS

3.8A

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

78 97

X01

P3V3_AL

AON7410

BAT54C_30V_0.2A

PAD6203

2

PCMC063T_3R3MN

3

130K_1%_3

DIODE-BAT54-TAP-PHP

3

+V5AUXON

8

4.7UF_25V_5

C6205

POWERPAD_2_0610

4.7UF_25V_5

C6204

0.1UF_25V_3

TI_TPS51123RGER_QFN_24P

AON7702L

C6215

0.1uF_16V_2

1

3

DIODES_BAV99

D6202

D6203

DIODES_BAV99

1

C6223

1

0.1uF_16V_2

C6222

1

0.1UF_25V_2

1

3

0_5%_3

2200pF_50V_24.7_5%_3

AON7410

C6209

1

PAD6202

POWERPAD_2_0610

SSM3K7002FU

1

Q6201

PAD6205

0_5%_2

1

2

SSM3K7002FU

Q6202

R6200

100K_5%_2

1

100K_5%_2_DY

2

3

1

Q1

+V5AUXON

1

120K_1%_2

3

20K_5%_2_DY

2

R3

R6209

4.7UF_25V_5

R6207

4.7UF_25V_5

1

R6201

2

P5V_AL

R1

EC_PW_ON#

R2

10K_5%_2

1

0_5%_2_DY

2

1

EC_PW_ON

D1

SSM3K7002FU

2

Q6203

C6218

R6210

2

3

C6212

P5V_A

1

L6200

U6200

10

V3LA_HG

2

6

8

C6208

V5A_LG

19

V3LA_LG

V3LA_SW

12

11

9

8

7

20

21

23

24

22

V5A_HG

V5A_SW

0.1UF_25V_3

2

4.7UF_25V_5

C6213

10K_5%_2

R6212

RSC_0402_DY

R6215

2

1

2

+V3LDO

P5V_AL

AON7702L

1

C

CS

Block Diagram

P2V

0_5%_3

1UF_6.3V_2

1UF_25V_3

10K_1%_2

0.047uF_16V_2

2200pF_50V_2

POWERPAD_2_0610

200_5%_2

FDMC8884

PCMC063T_3R3MN

330UF_6.3V

0.22UF_6.3V_2

2.2uF_25V_5

13

18

6

15

14

4

1

2

5

16

3

17

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

22

2

1

22

1

2

1

2

1

22

2

32

4

1

2

3

1

2

1

2

1

2

1

2

1

2

1

2 2

2

1

2

1

2

1

2

8

7

6

2

3

7

56

54

1

2

8

7

6

54

1

2

3

1

2

1

2

1

2

1

2

3

1

2

R6204

C6206

C6207

C6224

Q6207

Q6206

R6211

R6213

R6216C6220

R5

R4

C6200

C6203

C6201

C6214

R6208

R6202

D6201

C6211

1

SSM3K7002FU

25

P3V3_A

5

6

7

8

Q6200

P3V3_AL

2

10K_5%_2

1

P3V3_AL P15V_A

1

PVBAT

10K_1%_2

1

PAD6201

1

330UF_6.3V

Q6205

1

L6201

1

C6202

5

R6205

2

POWERPAD_2_0610

PAD6200

2

15.4K_1%_2

P15V_A

R6206

1

PVBAT

4

RSC_0402_DY

POWERPAD_2_0610

6.8K_1%_2

Q6204

7

10UF_6.3V_3

+V5AUXON

1

2

3

4

POWERPAD1X1M

PAD6204

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

C

A2

A1

1

2

NMOS_4D3S

D

G

S

G

DS

G

DS

G

DS

1

2

+

1

2

1

2

+

1

2

IN

OUT

IN

NC

G

DS

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

SS

G

D

S

G

D

IN

1

2

VFB1

VFB2

GND

SKIPSEL

VREG5

ENC

TML

TONSEL

VIN

ENTRIP2

TRIP1

EN0

VREF

DRVL2

VBST2

VREG3

VO2 VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

LL2

DRVH2

VOUT=(1+R1/R2)*0.7

R2

R1

3.7A

22A

3.7A

VOUT=(1.8*R2)/(R1+R2)

CHECK

X01

9779

1310xxxxx-0-0

21-OCT-2002

XXX

MODEL,PROJECT,FUNCTION

R6353

P3V3_S

TPCA8A02_H

C6305

0.1UF_25V_3

VR15_PH

VR15_LG

P0V75_VREF_M

2

4

0.22uF_6.3V_2

1

Q6350

VRVCCP_LG

VRVCCP_PH

VRVCCP_HG

10K_1%_2

U6340

P5V_A

10UF_6.3V_3

GMT_G5694F11U_SOP_8P

P1V8_S

0_5%_2

TI_TPS51218DSCR_SON_10P

U6350

R6352

P5V_A

R6350

+V1.05S_VCCP_EN

1

2

C6350

1

R6351

1

5

7

Q6351

R6354 PCMC063T_3R3MN POWERPAD_2_0610

1

6

0.1UF_25V_3

C6352

PVBAT

R6304

1

100K_5%_2

1

PAD6350

POWERPAD_2_0610

4.7UF_25V_5

1

4.7UF_25V_5

2

P1V05_VCCPS

L6350

1

PAD6351

1

2

R6305

PAD6340

POWERPAD_2_0610

R6301

17

1

0_5%_2

2

R6300

1

C6300

2.2uF_6.3V_3

U6300

2

8

75K_1%_2

TI_TPS51216RUKR_QFN_20P

POWERPAD_2_0610

560UF_2.5V

4.7_5%_3

2200pF_50V_2

2.2_5%_3

10K_1%_2

0.01uF_50V_2

52.3K_1%_2

POWERPAD_2_0610

PCMC104T_1R0MN

VR15_HG

TPCA8065_H

4.7UF_25V_5

CS

C

4.7UF_25V_5

Block Diagram

AON7410

4.7_5%_3

2.2_5%_3

330UF_6.3V

5.1K_1%_2

2200pF_50V_2

AON7702L

1uF_10V_2

CSC0402_DY

4.7UF_25V_5

10K_1%_2

22UF_6.3V_5

CSC0402_DY

13K_1%_2

PAN_ELL5PR2R2N

0.1UF_16V_2

10_5%_3

10K_5%_2

VR18_PH

0.1UF_16V_2

CSC0402_DY

0.1uF_10V_2

10uF_6.3V_3

200K_1%_2

110K_1%_2

5

4

3

7

6

2

9

1

8

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

14

11

7

19

10

20

13

21

18

12 15

9

2

6

3

4

5

1

2

1

2

1

2

1

2

8

7

6

5

1

3

1

2

1

2

1

2

3 4

8

7

6

54

1

2

3

1

2

1

2

1

2

1

2

1

2

9

3

11

1

5

8

2

10

4

1

2

1

2

1

2

1

2

8

7

6

4

1

2

3

1

2

1

2

8

7

6

54

1

2

3

1

2

1

2

1

2

1

2

L6340

C6344

C6343

C6342

C6341

C6340

C6345

R6342

R6343

R6340

R6341

R6302

C6301

C6302

C6304

R6303

R6306

C6310

Q6301

C6306

R6307

L6300

Q6300

C6307 C6309

PAD6302

PAD6301

C6351

R6356

C6357

C6353

C6354

R6355

C6355 C6356

P1V5

PAD6300

2

1

PVBAT

POWERPAD_2_0610

1

C6308

4.7UF_25V_5

POWERPAD_2_0610

1

PAD6310

2

P0V75_S

C6303

16

2

1

P5V_A

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

IN

1

2

1

2

NMOS_4D3S

D

G

S S

G

D

+

DRVL

V5IN

SW

DRVH

VBST

GND

RF

VFB

EN

TRIP

PGOOD

1

2

1

2

1

2

1

2

NMOS_4D3S

D

G

S S

G

D

+

VTTSNS

VTTREF

VTTGND

VTT

VREF

VLDOIN

VDDQSNS

VBSTV5IN

TRIP

TML

SW

S5

S3

REFIN

PGOOD

PGND

MODE

GND

DRVL

DRVH

IN

1

2

REF

FB

LX

TML

GND

PGND

EN

VCC

VIN

NEW

WS WS

80 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

TI_TPS51219RTER_QFN_16P

0_5%_3

15

16

17

10K_5%_2

VRVCCIO_HG

TPCA8065_H

1

VCCIO_SENSE

2.2UF_10V_3

10K_5%_2

R6404

2

1

0_5%_2_DY

R6405

2

P3V3_A

VSS_SENSE_VCCIO

0.01UF_50V_2

1UF_10V_2

POWERPAD1X1M

18

16

15

14

13

CSC0402_DY

VTT_PG

C6408

C6407

4.7UF_25V_5

P5V_A

2

R6432

2

C6439

1

Q6400

7

5

C6404

R6407

1K_5%_2

R6402

100PF_50V_2_DY

VTT_PG

VCCIO_SEL

10UF_10V_5

0_5%_2_DY

PCMC063T_R33MN

L6430

POWERPAD_2_0610

C6444

C6443

1

RSC_0603_DY

2

PAD6431

P0V85_S

22UF_6.3V_5_DY

2

0.1UF_25V_3

R6433

0_5%_2

C6438

2

0_5%_2

2

C6437

0.1UF_16V_2

2

0_5%_3

POWERPAD_2_0610

C6406

C6405

2

13

P3V3_S

R6403

VRVCCIO_LG

P5V_A

0.22UF_6.3V_2

C6435

0.01UF_50V_2

C6434

CSC0402_DY

RSC_0603_DY

R6408

L6400

PVBAT

1.5S_CPU_PG

SLP_S3#_5R

25

1

1UF_10V_2

2

R6435

C6441

22UF_6.3V_5 22UF_6.3V_5

U6430

VCCSA_VID1

VCCSA_VID0

PAD6430

10UF_10V_5

C6430 C6431

C6436

RSC_0402_DY

R6431

2

VCCSA_SENSE

2

5.11K_1%_2

1

R6430

1

VCCSA_PG

10K_5%_2

R6436

2

P3V3_S

2

4

TI_TPS51461RGER_QFN_24P

VRVCCSA_PH

C6410

C6409

C6433

C6432

R6434

C6440

C6442

R6437

PAD6400

PAD6402

U6400

Q6401

C6401

R6400

R6401

R6406

C6402

C6400

C6403

PAD6401

1

43

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

5

24

23

22

17

9

8

7

11

1021

20

19

6

1

3

12

2

1

2

1

43 2

1

4

1

9

6

12

2

8

3

7

14

10

11

5

3

2

1

4 5

6

7

8

3

2

1

46

8

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

CSC0402_DY

3300PF_50V_2

TPCA8A02_H

4.7UF_25V_5 4.7UF_25V_5

POWERPAD_2_0610

86.6K_1%_2

C

CS

Block Diagram

100K_5%_2_DY

0.1UF_25V_3

0_5%_2

22UF_6.3V_5

560UF_2.5V

POWERPAD_2_0610

1UF_10V_2

PVCCIO

VRVCCIO_PH

22UF_6.3V_5

ETQP4LR36AFM

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

IN

+

1

2

1

2

VREF

VOUT

VID1

VID0

V5FILT

V5DRV

TML

SLEW

PGOOD

MODE

GND

EN

COMP

BST

SW

SWVIN

VIN

PGND

SW

1

2

1

2

VSNS

VREF

V5

TRIP

SW

REFIN

PWPD

PGOOD

PGND

MODE

GSNS

GND

EN

DL

DH

COMP

BST

S

G

D

NMOS_4D3S

D

G

S

IN

OUT

IN

OUT

IN

1

2

81

97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

VR_SVID_CLK

R6507

TI_TPS51650RSLR_QFN_48P

23

2.2UF_6.3V_3

7

5

1

R6535

P5V_CPU

TPCA8065_H

4.7UF_10V_3

C6507

R6534

P5V_CPU

2

100K_1%_NTC

42.2K_1%_2

24K_1%_2

30

32

10K_5%_2

VRCPU_HG2

0.1UF_25V_2

0_5%_2

GPWM1

GSKIP

CPWM3

GPWM2

R6531

2

1

VRCPU_LG2

VRCPU_PH2

PVBAT

0_5%_2

36

1

2

0_5%_2

0_5%_2_DY

R6521

R6519

P3V3_A

0_5%_2_DY

31

21

VR_SVID_ALRT#

VR_PWRGD

VR_ON

0_5%_2

1

+VGFX_PWRGD

0_5%_2_DY

VSSAXG_SENSE

VAXG_SENSE

R6506

26

2

28

0_5%_2_DY

R6515

2.2UF_6.3V_3

VREF

2

R6526

20K_5%_2

MAIN_PWRGD

1

2 2

1 1

R6527

8.66K_1%_2

VR_ON

2

1

2

1

4.12K_1%_2

33PF_50V_2

2

VREF

2

1

2

C6501

1

P3V3_A

2

1

2

R6525

R6524

56K_1%_2

1

2

1

R6528

100K_1%_NTC

R6529

1

2

1

2

C6508

30K_5%_2

0.1UF_16V_2_DY

2

0_5%_2

1

R6509

1

R6502

VR_SVID_CLK

VR_SVID_DATA

2

R6501

130_1%_2

54.9_1%_2

R6500

1

PVTT

1

VREF

C6500

0.1UF_16V_2_DY

1

C6504

2

100K_1%_2

2

1 1

VREF

4

3

2

1

5

6

7

8

1

TPCA8057_H

Q6503

2 2

1

Q6502

1

C6517

2 2

C6510

2

1

10_5%_3

2

5

62

7

8

1

4

3

2

1

TPCA8057_H

1

2

6

7

8

3

2

1

4

7

8

1

2

C6511

1

2

1

C6513

1

C6515

C6521

R6536

CSC0402_DY

RSC_0603_DY

CSC0402_DY

2

1 1

3

1

R6543

2

100K_1%_NTC

PAN_ETQP4LR36ZFC_4P

2

C6533

1

4

2

1

28.7K_1%_2

560UF_2.5V

2

1

C6534

3

470UF_2V

1

2

C6514

1

R6538

17.8K_1%_3

1

3

2

R6539

2

1

L6500

2

4

1

2

R6540

28.7K_1%_2

2

3

470UF_2V

4.7UF_25V_5

CPU_CSP1

CPU_CSN1

1

C6516

0.033UF_16V_2

2

1

R6542

L6501

4

3

2

TPCA8065_H

2

4.7UF_25V_5

C6512

Q6500

2

R6514

2

R6512

2

C6506

2.2UF_10V_3

C6505

1

R6513

PVBAT

PAD6500

POWERPAD_2_0610

6

5

1

2

33PF_50V_2

R6510

8.45K_1%_2

R6503

1

VREF

C6502

1

C6503

2

30K_1%_2

R6505

R6504

200K_1%_2

Block Diagram

CS

C

VREF

0_5%_2_DY

R6508

1

R6511

VREF

R6517

R6522

VREF

0_5%_2_DY

VREF

1

15.4K_1%_2

1

75K_1%_2

CPU_CSN1

GPU_CSN1

100K_1%_2

R6523

R6520

GPU_CSP1

GPU_CSP2

R6516

1

GPU_CSN2

R6518

CPU_CSP3

18

9

4

5

8

6

12

11

2

16

35

10

25

27

22

24

34

33

14

17

19

20

15

13

U6500

H_PROCHOT#

VR_SVID_DATA

VSSSENSE

CPU_CSN2

CPU_CSN3

CPU_CSP1

CPU_CSP2

VCCSENSE

29

R6530

1

R6533

2.2_5%_3

37

38

41

45

46

47

49

43

42

39

40

PAD6501

PVBAT

VRCPU_PH1

2.2_5%_3

R6532 C6509

1

P5V_A

48

VRCPU_LG1

44

0.1UF_25V_2

2

VRCPU_HG1

P5V_A

0.1UF_16V_2_DY

1

R6537

PAN_ETQP4LR36ZFC_4P

100K_1%_NTC

1

3

2

162K_1%_2

1

C6531

470UF_2V

C6532

1

PVCORE

17.8K_1%_3

2

162K_1%_2

C6518

CPU_CSN2

POWERPAD_2_0610

2

4.7UF_25V_5

CPU_CSP2

4.7UF_25V_5

C6519

C6520

1

4.7UF_25V_5

0.033UF_16V_2

C6522

R6541

R6544

2

PVCORE

2

3

1

15.4K_1%_2

1

Q6501

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

+

++

+

VR_ON

VR_HOT

VREF

VDIO

VCLK

VBAT

V5DRV

V5

V3R3

PGND

N_C

GVFB

GTHERM

GSKIP#

GPWM2

GPWM1

GPGOOD

GOCP_R

GND

GGFB

GF_IMAX

GCSP2

GCSP1

GCSN2

GCSN1

GCOMP

CVFB

CTHERM

CSW2

CSW1

CPWM3

CPGOOD

COCR-1

CGFB

CF-IMAX

CDL2

CDL1

CDH2

CDH1

CCSP3

CCSP2

CCSP1

CCSN3

CCSN2

CCSN1

CCOMP

CBST2

CBST1

ALERT#

1

2

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

1

2

82 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

P5V_A

VRAXG_LG1

VRAXG_PH1

5

TI_TPS51601DRBR_SON_8P

2.2_5%_3 0.1UF_25V_2

2

1

RSC_0603_DY

GPU_CSN2

C6613

C6612

C6610

Q6602

GPWM2

GSKIP#

GPWM1

GSKIP#

CPWM3

PVBAT

100K_1%_NTC

R6605

0.033UF_16V_2

GPU_CSP2

PVAXG

PVCORE

28.7K_1%_2

100K_1%_NTC

0.033UF_16V_2

162K_1%_2

2

1

C6526

4.7UF_25V_5

R6546

RSC_0603_DY

C6529

1UF_10V_2

TPCA8065_H

R6601

POWERPAD_2_0610

PAD6601

GPU_CSP1

2

PAN_ETQP4LR36ZFC_4P

R6604

R6602

2

17.8K_1%_3

4.7UF_25V_5

1

GPU_CSN1

1

CPU_CSN3

C6528

1

CPU_CSP3

4.7UF_25V_5

PAD6600

POWERPAD_2_0610

Q6600

C6600

C6603

C6602

C6527

R6607

C6614

C6606

C6609

C6524

C6601

R6606

R6600

R6545

C6608

C6523

C6615

C6607

C6530

C6525

R6608

R6547

R6609

R6603

R6548

R6611

R6550

R6610

U6601

R6549

L6601

L6600

L6502

Q6603

Q6601

Q6506

U6600

Q6505

PAD6503

C6611

C6605

C6604

U6501

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

43 2

1

43 2

1

43 2

1

3

2

1

4 5

6

7

8

3

2

1

46

7

8

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

3

2

1

4 5

6

7

8

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

72

3

9

4 5

8

1

6

72

3

9

4 5

8

1

6

72

3

9

4 5

8

1

17.8K_1%_3

PAN_ETQP4LR36ZFC_4P

17.8K_1%_3

PAN_ETQP4LR36ZFC_4P

162K_1%_2

28.7K_1%_2

4.7UF_25V_5

TPCA8065_H

VRCPU_HG3

P5V_CPU

C

CS

Block Diagram

VRAXG_HG1

2.2_5%_3

TI_TPS51601DRBR_SON_8P

TPCA8057_H

CSC0402_DY

VRCPU_PH3

VRCPU_LG3

PVBAT

P5V_A

TPCA8065_H

VRAXG_HG2

VRAXG_PH2

VRAXG_LG2

P5V_A

1UF_10V_2

4.7UF_25V_5

1UF_10V_2

TPCA8057_H

PVBAT

TI_TPS51601DRBR_SON_8P

2.2_5%_3

POWERPAD_2_0610

4.7UF_25V_5

0.1UF_25V_2

100K_1%_NTC

0.1UF_25V_2 4.7UF_25V_5

4.7UF_25V_5

CSC0402_DY

28.7K_1%_2

RSC_0603_DY

4.7UF_25V_5 162K_1%_2

4.7UF_25V_5

CSC0402_DY

TPCA8057_H

0.033UF_16V_2

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

IN

VDD

SW

SKIP#

PWM

PAD

GND

DRVL

DRVH

BST

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

VDD

SW

SKIP#

PWM

PAD

GND

DRVL

DRVH

BST

NMOS_4D3S

D

G

S

1

2

1

2

1

2

OUT

IN

VDD

SW

SKIP#

PWM

PAD

GND

DRVL

DRVH

BST

WS

Original Sch

30A

3.5A

CHECK

1

0

0.90V

1

VID0

0

POW_SW0

0.90V

+VDDC_GPU

PCORE_GPU

1.00V

PCORE_GPU

+VDDC_GPU

1.05V

1.00V

For XT

For PRO

1

0

POW_SW0

VID0

POW_SW1

VID1

0

VID1

POW_SW1

CHECK

WS

CHECK

WS

83 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

1

POW_SW1

2

R6708

P3V3_S

10K_5%_2

R6

POW_SW0

1

Q3

SSM3K7002FU

1

10K_5%_2

P3V3_S

C6709

1K_1%_2

47pF_50V_2

R6704

11

R6701

1

9

TI_TPS51217DSCR_SON_10P

1

U6700

5

4

3

2

10

8

VRGPU_SW

1

75K_1%_2

1

C6701

2

10K_5%_2

EC_DGPU_PWR_EN

1

R6802

VDDC_GPU_PG

2

C6801

1UF_6.3V_2

1

R6703

2

7

C6704

C6705

C6708

2

4.7UF_25V_5

TPCA8065_H

1

2.2_5%_3

R6700

0.1UF_25V_3

PVCORE_GPU

2

PAD6700

P3V3_S

P5V_A

2

POWERPAD_2_0610

PAD6701

2

C6707

470UF_2V

2

SLP_S3#_3R

0_5%_2

R6705

2

1

P5V_A

1

2

10K_5%_2

R6707

2

1

C6702

CSC0402_DY

R6801

10K_5%_2

I80

1

2

D6700

Q6702

3

1

2

1

4.7UF_25V_5

SBR3U40P1

R6706

PAN_ETQP4LR36WFC_4P

2

L6700

Q6700

5

40.2K_1%_2

2

3

POWERPAD_2_0610

PAD6702

PVBAT

1

C1

R7

C6706

R6702

C6703

C6700

Q6701

Q2

8

7

6

54

3

2

1

2

1

2 3 2

2

1

2

1

2

1

11

2

1

2

1

43

1

2

1

2

1

46

8

2

1

2

8

7

6

54

3

2

1

7

6

1

2

1

2

CSC0402_DY

100PF_50V_2

1uF_10V_2

POWERPAD_2_0610

470UF_2V

4.7UF_25V_5

10.2K_1%_2

20K_1%_2

TSB_TPCA8057_H_8P

68K_1%_2

SSM3K7002FU

C

CS

Block Diagram

VRGPU_HG

VRGPU_LG

TSB_TPCA8057_H_8P

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

OUT

IN

D S

G

8

7

6

5

3

1

4

2

IN

G

DS

1

2

+

1

2

+

1

2

NMOS_4D3S

D

G

S

D S

G

8

7

6

5

3

1

4

2

VFB

VBST

V5IN

TRIP

TRAN

SW

PGOOD

GND

EN

DRVL

DRVH

IN

G

DS

IN

VGA controller capacity enabled=0 (Default)

VGA controller capacity disabled=1

Disable the external BIOS ROM device=0 (Default)

Enable the external BIOS ROM device=1

If GPIO_22 = 0, then CONFIG [2:0] defines the primary

Voltage control signal for the memory-voltage regulator.

1 0 = Audio for DisplayPort and HDMI, if dongle is detected

GENLK_CLK

BACO MODE

RESERVED

GPIO_2

GPIO_1

GPIO_0

CONFIGURATION STRAPS:

Pin-Based Straps

GPU

Whistler

Advertises the PCIe device as 5.0 GT/s capable at power on=1

0 0 = No audio function

(PCB default is 0)

(ASIC Internal pull down, and PCB Default is 0)

CONFIG[1]

CONFIG[0]

GPIO_13

PCB default is left unconnected

Must be low during reset

BIF_VGA DIS

0 1 = Audio for DisplayPort only

AUD[1]

RESERVED

GPIO_21

Must be low during reset

(7A)

Advertises the PCIe device as 2.5 GT/s capable at power on=0

Tx De-emphasis enabled=1 (Default)

Tx De-emphasis disabled=0

50% Tx output swing=0

AUD [1:0]:

DESCRIPTION OF DEFAULT SETTINGS

BIOS_ROM_EN

TX_DEEMPH_EN

AUD[0]

GPIO_22

GPIO_12

TX_PWRS_ENB

STRAPS

GPIO_11

CONFIG[2]

RESERVED

GPIO_8

HSYNC

Full Tx output swing=1 (Default)

GPIO_9

memory-aperture size. Default is 0 0 1

1 1 = Audio for both DisplayPort and HDMI. (Default is 1 1)

VSYNC

Must be low during reset

PCB default is left unconnected

(2.012A)

84 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

VDDC_GPU_PG

C5108

PX_MODE

Q5105

P3V3_A

SSM3K7002FU

68pF_50V_2

C5104

1

P15V_A

SSM3K7002FU

0_5%_2_DY

C5116

C5118

2.2uF_6.3V_3

0.01uF_50V_2

1

2

Q5110

P1V8_GPUS

Q5112

AM3402N FDMC7692

1

P1V8_SP3V3_A

5

Q5117

1

R5106

2

C5107

100K_5%_2

C

CS

Block Diagram

1

DGPU_PWR_EN#

P3V3_S

10K_5%_2

R5119

200_5%_2

P1V5_GPUS

1

2.2uF_6.3V_3

P3V3_GPUS

3

2

Q5113

0_5%_2

R5517

R5516

3

C5120

0.1uF_16V_2

Q5121

AM2321P

R5123

2

SSM3K7002FU

2

1

2

1

2

1

2

1

2

1

2

1

4 5

6

7

8

2

1

3

1

3

4

36

2

1

2

1

2

1

2

1

3

Q5122

1

2

1

3

SSM3K7002FU

560K_1%_2

P15V_A

P1V5

Q5109

SSM3K7002FU

3

560K_1%_2

R5115

100K_5%_2

R5111

68pF_50V_2

R5114

1

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

IN

G

DS

G

DS

NMOS_4D3S

D

G

S

G

DS

IN

G

DS

G

DS

D

G

S

NMOS_4D1S

G

SD

UP TO 5.0-GT/S BIT RATE.

PCI EXPRESS BUS:TRANSMITTED/RECEIVER

GEN2:

TDP: 20~25 W

WHISTLER PRO

TDP: 30~35 W

WHISTLER XT

CLOSE TO GPU

85 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

0.1UF_16V_2

U5001

5

PEG_TX15_DN

PEG_TX15_DP

PEG_TX14_DN

CLK_PEG_GPU_REF_DN

P3V3_S

CLK_PEG_GPU_REF_DP

R5003

1

AH16

10K_5%_2

2

C5000

1

DGPU_HOLD_RST#

4

PEG_PLT_RST#

AMD_216_0810_001_FCBGA_962P

PEG_TX9_DP

PEG_TX8_DN

PEG_TX7_DP

PEG_TX6_DN

PEG_TX13_DN

PLT_RST#

PEG_TX0_DP

V35

PEG_RX10_C_DN

PEG_RX11_C_DP

C5154

1

Y29

Y30

H32

H33

K29

J33

PEG_RX5_C_DP

PEG_RX5_C_DN

PEG_RX4_C_DN

PEG_RX3_C_DN

PEG_RX2_C_DN

PEG_RX2_C_DP

W33Y35

C

CS

Block Diagram

PEG_TX10_DN

C5152

2

0.1UF_16V_2

2

C5146

PEG_RX7_C_DP

PEG_RX6_C_DN

PEG_RX6_C_DP

PEG_RX7_C_DN

PEG_RX8_C_DP

PEG_TX5_DN

PEG_TX1_DN

N29

K32

G38

PEG_TX14_DP

2

1

R5002

2

1

R5125

2

1

C5155

2

1

2

C5156

2

1

C5157

2

1

C5005

2

1

C5004

1

2

1

C5153

2

1

C5149

1

C5148

2

1

C5150

2

1

C5151

2

1

C5145

2

1

C5144

2

1

2

1

C5147

2

1

C5141

2

1

C5140

2

1

C5142

2

1

C5143

2

1

C5137

2

1

C5136

2

1

C5138

2

1

C5139

2

1

C5135

2

1

C5134

2

1

C5132

2

1

C5133

2

1

C5130

2

1

C5131

2

1

C5129

2

1

C5128

2

3

2

1

2

1

R5127

2

1

R5126

AA30

N30

N33

N32

P30

P29

P33

P32

T30

T29

T33

T32

U30

U29

U33

U32

W32

K30

J32

K33

L30

L29

L33

L32

Y33

Y32

M35

L36

N38

M37

P35

N36

R38

P37

T35

R36

U38

T37

U36

W38

V37

W36

F35

E37

F37

H35

G36

J38

H37

K35

J36

L38

K37

AA38

Y37

AB35

AA36

U5124

PEG_RX14_C_DP

PEG_RX14_C_DN

PEG_RX15_C_DP

P1V0_GPU

0.1UF_16V_2

PEG_RX1_C_DN

PEG_RX1_C_DP

PEG_RX0_C_DN

PEG_RX0_C_DP

PEG_TX4_DP

0_5%_2_DY

100K_5%_2

TC7SZ08FU

PEG_RX15_DN

PEG_RX15_DP

PEG_RX14_DN

PEG_RX13_DN

0.1UF_16V_2

2K_1%_2

1.27K_1%_2

PEG_TX4_DN

PEG_TX5_DP

PEG_RX4_C_DP

PEG_RX3_C_DP

PEG_TX6_DP

PEG_TX7_DN

PEG_TX11_DN

PEG_TX11_DP

PEG_TX8_DP

PEG_TX9_DN

PEG_TX3_DN

PEG_TX12_DP

PEG_TX2_DP PEG_RX2_DN

PEG_RX3_DP

PEG_TX0_DN

PEG_RX2_DP

PEG_TX13_DP

PEG_TX12_DN

PEG_RX11_C_DN

PEG_RX13_C_DP

PEG_RX10_C_DP

PEG_RX9_C_DP

PEG_RX9_C_DN

PEG_RX13_C_DN

PEG_RX6_DN

PEG_RX10_DP

PEG_RX15_C_DN

PEG_RX0_DN

PEG_RX6_DP

PEG_RX8_DP

PEG_RX9_DP

PEG_RX10_DN

PEG_RX7_DP

PEG_RX7_DN

PEG_RX8_DN

PEG_RX13_DP

PEG_RX14_DP

PEG_RX11_DN

PEG_RX1_DN

PEG_TX3_DP

PEG_TX2_DN

PEG_TX1_DP

PEG_RX9_DN

PEG_RX12_C_DP PEG_RX12_DN

PEG_RX12_C_DN

PEG_RX0_DP

0.1UF_16V_2

PEG_RX8_C_DN

0.1UF_16V_2

PEG_RX5_DN

PEG_RX5_DP

PEG_RX4_DN

PEG_RX4_DP

PEG_RX3_DN

PEG_RX11_DP

PEG_RX12_DP

PEG_RX1_DP

PEG_TX10_DP

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

BI

IN

+

-

BI

CALIBRATION

CLOCK

PCI EXPRESS INTERFACE

PCIE_TX9P

PCIE_TX9N

PCIE_TX8P

PCIE_TX8N

PCIE_TX7P

PCIE_TX7N

PCIE_TX6P

PCIE_TX6N

PCIE_TX5P

PCIE_TX5N

PCIE_TX4P

PCIE_TX4N

PCIE_TX3P

PCIE_TX3N

PCIE_TX2P

PCIE_TX2N

PCIE_TX1P

PCIE_TX1N

PCIE_TX15P

PCIE_TX15N

PCIE_TX14P

PCIE_TX14N

PCIE_TX13P

PCIE_TX13N

PCIE_TX12P

PCIE_TX12N

PCIE_TX11P

PCIE_TX11N

PCIE_TX10P

PCIE_TX10N

PCIE_TX0P

PCIE_TX0N

PERSTB

PCIE_RX9P

PCIE_RX9N

PCIE_RX8P

PCIE_RX8N

PCIE_RX7P

PCIE_RX7N

PCIE_RX6P

PCIE_RX6N

PCIE_RX5P

PCIE_RX5N

PCIE_RX4P

PCIE_RX4N

PCIE_RX3P

PCIE_RX3N

PCIE_RX2P

PCIE_RX2N

PCIE_RX1P

PCIE_RX1N

PCIE_RX15P

PCIE_RX15N

PCIE_RX14P

PCIE_RX14N

PCIE_RX13P

PCIE_RX13N

PCIE_RX12P

PCIE_RX12N

PCIE_RX11P

PCIE_RX11N

PCIE_RX10P

PCIE_RX10N

PCIE_RX0P

PCIE_RX0N

PCIE_REFCLKP

PCIE_REFCLKN

PCIE_CALRP

PCIE_CALRNPWRGOOD

1.8V,0.1A

I=0.07A

Away from noisy GND area.

CLOSE TO GPU

32 KHZ SPREAD SPECTRUM MODULATION

3.3V,0.05A

SWING: 3.3V

IF GPU_GPIO22 = 0, THEN GPIO[13:11]

DEFINES THE PRIMARY MEMORY APERTURE SIZE

GPU_

GPIO11

0.90V

For XT

PCORE_GPU

+VDDC_GPU

1.05V

1.00V

+VDDC_GPU

0.90V

1

0

POW_SW1

VID0

0

POW_SW1

VID0

POW_SW0

1

0

VID1

1

VID1

32 MB

1

FUTURE ASIC

64 MB

128 MB

I=0.005A

1

0

I=0.075A

I=0.045A

HDMI

0

00

SIZE

0

0 0

11

GPU_

GPIO13 GPIO12

SWING: 1.8V

HYNIX

(1GB)

0

1

(1GB)

(GDDR5)

SAMSUNG

Vendor

MEM_ID0

MEM_ID1

GPU Multi Level Pin Straps feature

CRT

0

MEM_ID3 MEM_ID2

(DEFAULT)

0

GPU_

256 MB

1

0

1

0

HDMI&DP Audio

[ALERT]

I=0.125A

DUAL CHANNEL FOR 3D FUNCTION

EDP

3.3V,0.13A

CLOSE TO GPU

MEMORY APERTURE

JTAG MODE

MLPS option for future ASIC

For PRO

POW_SW0 PCORE_GPU

1.00V

9786

MODEL,PROJECT,FUNCTION

X01

XXX

1310xxxxx-0-0

21-OCT-2002

R5163

R5161

10K_5%_2

1

10K_5%_2

2

R5159

10K_5%_2

1

10K_5%_2

1

POW_SW1

2

POW_SW0

2

10K_5%_2

R5179

1

GPU_LCM_BKLTEN

GPU_GPIO19

R5158

10K_5%_2

GPU_GPIO5

GPU_GPIO9

GPU_CRT_HSYNC

R5177

10K_5%_2_DY

1

R5178

R5176

GPU_CRT_VSYNC

GPU_GPIO23

10K_5%_2_DY

2

R5009

FBM_11_160808_121T

P3V3_GPUS

2

R5164

10K_5%_2_DY

R5162

10K_5%_2_DY

2

R5160R5008

10K_5%_2

P3V3_GPUS

R5020

0_5%_2_DY

R5021

0_5%_2_DY

1

GPU_THM_DAT

GPU_THM_CLK

GPU_TS_FDO

2

C5026

P1V8_GPUS

R5024

10K_5%_2_DY 10K_5%_2_DY

R5025

1

C5013

1

U5018

2

7

8

2200PF_50V_3

1

C5014

1

GPU_JTAG_TDO

GPU_JTAG_TDI

2

10K_5%_2_DY

0.1UF_16V_2

GMT_G784_MSOP_8P

2

1

2

1

R5019

1

TP5036

1

TP5035

22

1

2

1

R5041

2

1

R5202

2

1

R5208

2

1

R5040

2

1

R5039

2

1

R5038

2

1

R5037

2

1

C5206

2

1

R5203

2

1

R5209

2

1

C5210

2

1

C5213

2

1

R5211

2

1

R5212

1

TP5189

1

TP5190

2

1

C5163

2

1

C5161

1

TP5032

1

TP5031

2

1

R5023

2

1

R5022

2

1

C5006

2

1

L5007

2

1

R5012

2

1

R5010

2

1

C5166

2

1

C5011

4

3

2

1

X5015

2

1

R5016

10

1

8

4

11

3

7

6

2

9

5

U5017

1

TP5165

2

1

R5168

2

1

R5167

22

2

1

2

1

R5175

2

1

R5170

2

1

R5171

2

1

R5173

2

1

R5172

2

1

R5169

2

1

R5030

2

1

R5029

2

1

R5174

2

1

2

1

L5180

2

1

L5181

1

4 5

2

3 6

2

1

C5027

2

1

C5028

2

1

2

1

2

1

R5194

2

1

R5196

2

1

R5197

2

1

C5033

2

1

R5034

2

1

R5185

2

1

C5184

2

1

C5183

2

1

C5192

2

1

C5182

1

2

1

C5193

2

1

C5188

2

1

L5186

2

1

R5191

2

1

R5187

2

1

C5199

2

1

C5201

2

1

C5205

2

1

L5207

2

1

L5042

2

1

C5200

2

1

C5204

2

1

C5198

2

1

R5195

AD32

AU34

AV33

AW35

AW34

AC38

AG32

AC34

AH13

AG31

AC33

AC29

AU20

AT19

AU14

AV13

AR30

AT29

AU24

AV23

AT23

AT33

AR22

AU32

AU22

AR32

AV21

AT31

AT21

AV31

AR20

AU30

AT17

AT27

AR16

AR26

AU16

AU26

AV15

AV25

AT15

AT25

AR14

AR24

AJ33

AJ32

AK32

AL31

AK21

AJ21

AJ26

AK26

AB34

AD37

AA29

AC31

AC30

AD39

AM23

AL24

AM24

AN23

AK23

AC36

AK24

AD29

AH15

AJ13

AK17

AJ17

AH17

AJ23

AH23

AN13

AK13

AJ14

AL13

AN16

AM17

AN14

AG30

AK14

AM13

AM14

AM16

AL16

AK16

AJ16

AH18

AH20

AH24

AH26

AJ24

AK20

AJ20

AK19

AJ19

AD35

AD31

AD30

AE36

AT7

AU6

AW6

AR6

AU5

AW5

AP6

AP12

AU12

AW12

AR12

AW3

AT11

AV11

AP10

AU10

AW10

AR10

AT9

AV9

AN7

AV7

AU3

AU1

AU8

AR8

AR3

AW8

AP8

AR1

AF29

AN31

AN32

AM32

AG29

AK29

AM21

AM29

AM30

AK30

AN21

AL29

AL30

AJ31

AJ30

AL19

AM19

AN26

AM26

AF32

AC32

AE38

AF31

AF30

AF37

AE34

AD34

AN20

AM20

AM27

AL27

AF33

AD33

AG33

U5124

10K_5%_2

150_1%_2

EC_SMB2_CLK

THRM_GPU_DN

THRM_GPU_DP

P3V3_GPUS

GPU_PS3

GPU_CRT_R

150_1%_2

EC_SMB2_DATA

FBM_11_160808_121T

P1V8_GPUS

GPU_XOIN_27M_R

P1V0_GPU

0.1UF_16V_2

10UF_6.3V_3

1UF_6.3V_2

FBM_11_160808_121T

P1V8_GPUS

0.1UF_16V_2

GPU_HDMI_DDCDATA

GPU_HDMI_DDCCLK

715_1%_2_DY

GPU_CRT_VSYNC

GPU_CRT_HSYNC

10UF_6.3V_3

FBM_11_160808_121T

IDT_6V40088_DFN_10P

GPU_JTAG_TMS

GPU_JTAG_TRSTB

P1V8_GPUS

P3V3_GPUS

15PF_50V_2

XTAL_4PIN

27MHZ_12PF

15PF_50V_2

1M_5%_2

P3V3_GPUS

GPU_XOIN2_100M

GPU_XOIN_27M

0_5%_3_DY

10K_5%_2_DY

10UF_6.3V_3

10K_5%_2_DY

10K_5%_2

10K_5%_2_DY

10K_5%_2

TP24

10K_5%_2_DY

0_5%_3_DY

0_5%_2_DY

0.1UF_16V_2_DY

10K_5%_2_DY

0.1UF_16V_2_DY

10K_5%_2_DY

TP24

33_5%_2

0_5%_2

TP24

10K_5%_2_DY

FBM_11_160808_121T

0.1UF_16V_2

0_5%_2_DY

0.1UF_16V_2

249_1%_2

499_1%_2

1UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

0.1UF_16V_2

10K_5%_2

0.1UF_16V_2 1UF_6.3V_2

FBM_11_160808_121T

10UF_6.3V_3

499_1%_2

AMD_216_0810_001_FCBGA_962P

10K_5%_2_DY

P1V8_GPUS

GPU_GPIO11

GPU_JTAG_TCK

GPU_GPIO5

GPU_GPIO2

GPU_GPIO22

GPU_THERM_INT#

GPU_GPIO1

GPU_JTAG_TDO

GPU_JTAG_TMS

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_JTAG_TRSTB

GPU_GPIO23

GPU_GPIO22

GPU_GPIO21

POW_SW1

GPU_GPIO19

GPU_THERM_INT#

GPU_EDP_HPD

GPU_GPIO0

GPU_XOIN2_100M_R

GPU_LCM_BKLTEN

POW_SW0

GPU_THM_CLK

GPU_THM_DAT

GPU_HDMI_TX2_DN

GPU_PS1

GPU_PS2

GPU_CRT_DDCDATA

GPU_CRT_DDCCLK

GPU_EDP_AUX_DN

GPU_EDP_AUX_DP

GPU_PS1

GPU_GPIO12

GPU_GPIO9

GPU_GPIO13

GPU_TS_FDO

DPLL_PVDD

TSVDD

Everest Main Board

THRM_SHUTDWN#

THRM_GPU_DP

THRM_GPU_DN

C

CS

CS_1310AXXXXXX-MTR

1

Block Diagram

A01

1

BEN LEE February 22, 2010

VDD1D1

CLK_GPU_27M

GPU_HDMI_TXC_DP

GPU_HDMI_TXC_DN

GPU_EDP_TX0_DP

GPU_HDMI_TX1_DP

GPU_HDMI_TX1_DN

GPU_HDMI_TX0_DP

AVDD

GPU_PS3

GPU_CRT_B

GPU_EDP_TX1_DN

GPU_HDMI_TX0_DN

GPU_HDMI_TX2_DP

GPU_GPIO1

GPU_GPIO0

GPU_GPIO2

DPLL_VDDC

GPU_EDP_TX0_DN

GPU_EDP_TX1_DP

GPU_PS2

GPU_CRT_G

GPU_XOIN_27M_R

GPU_HDMI_HPD1

GPU_GPIO12

GPU_GPIO13

GPU_GPIO21

GPU_GPIO11

GPU_XOIN2_100M_R

MEM_ID0

MEM_ID1

MEM_ID2

MEM_ID3

TITLE

DATE

CODE

SIZE

1

E

D

C

B

A

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

of

CHANGE by

8

REV

DOC.NUMBER

SHEET

2

INVENTEC

BI

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

X2

X1_ICLK

VDD_27M

VDD_100M

TML

S1

S0

GND_PLL

GND_27M

27M

100M

OUT

IN

BI

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

GND

ALERT#

SMBDATA

SMBCLK

THERM#

DXN

DXP

VCC

IN

OUT

BI

OUT

BI

PLL/CLOCK

THERMAL

DDC/AUX

DAC2

DAC1

GENERAL PURPOSE I/O

I2C

MUTI GFX

DPD

DPC

DPB

DPA

SWAPLOCKB

SWAPLOCKA

XO_IN2

XO_IN

TS_A/NC

Y/NC

VSYNC

VDD2DI/NC

VDD1DI

V2SYNC/GENLK_VSYNC

TXCDP_DPD3P

TXCDM_DPD3N

TXCCP_DPC3P

TXCCM_DPC3N

TXCBP_DPB3P

TXCBM_DPB3N

TXCAP_DPA3P

TXCAM_DPA3N

TX5P_DPD0P

TX5P_DPB0P

TX5M_DPD0N

TX5M_DPB0N

TX4P_DPD1P

TX4P_DPB1P

TX4M_DPD1N

TX4M_DPB1N

TX3P_DPD2P

TX3P_DPB2P

TX3M_DPD2N

TX3M_DPB2N

TX2P_DPC0P

TX2P_DPA0P

TX2M_DPC0N

TX2M_DPA0N

TX1P_DPC1P

TX1P_DPA1P

TX1M_DPC1N

TX1M_DPA1N

TX0P_DPC2P

TX0P_DPA2P

TX0M_DPC2N

TX0M_DPA2N

SDA

SCL

RSET

RB

R2SET/NC

R2B/NC

R2/NC

R

GB

G2B/NC

G2/NC

G

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDC6DATA

DDC6CLK

DDC2DATA

DDC2CLK

DDC1DATA

DDC1CLK

COMP/NC

C/NC

BB

B2B/NC

B2/NC

B

AVSSQ

AVDD

AUX2P

AUX2N

AUX1P

AUX1N

A2VSSQ/TSVSSQ

A2VDDQ/NC

A2VDD/NC

XTALOUT

XTALIN

VSS2DI/NC

VSS1DI

VREFG

TSVSS

TSVDD

TS_FDO

DDCCLK_AUX7P

DDCDATA_AUX7N

JTAG_TRSTB

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

HSYNC

HPD1

H2SYNC/GENLK_CLK

GPIO_9_ROMSI

GPIO_8_ROMSO

GPIO_7_BLON

GPIO_6

GPIO_5_AC_BATT

GPIO_4_SMBCLK

GPIO_3_SMBDATA

GPIO_23_CLKREQB

GPIO_22_ROMCSB

GPIO_21_BB_EN

GPIO_20_PWRCNTL_1

GPIO_2

GPIO_19_CTF

GPIO_18_HPD3

GPIO_17_THERMAL_INT

GPIO_16

GPIO_15_PWRCNTL_0

GPIO_14_HPD2

GPIO_13

GPIO_12

GPIO_11

GPIO_10_ROMSCK

GPIO_1

GPIO_0

GENERICG_HPD6

GENERICF_HPD5

GENERICE_HPD4

GENERICD

GENERICC

GENERICB

GENERICA

DVPDATA_9

DVPDATA_8

DVPDATA_7

DVPDATA_6

DVPDATA_5

DVPDATA_4

DVPDATA_3

DVPDATA_23

DVPDATA_22

DVPDATA_21

DVPDATA_20

DVPDATA_2

DVPDATA_19

DVPDATA_18

DVPDATA_17

DVPDATA_16

DVPDATA_15

DVPDATA_14

DVPDATA_13

DVPDATA_12

DVPDATA_11

DVPDATA_10

DVPDATA_1

DVPDATA_0

DVPCNTL_MVP_1

DVPCNTL_MVP_0

DVPCNTL_2

DVPCNTL_1

DVPCNTL_0

DVPCLK

DPLUS

DPLL_VDDC

DPLL_PVSS

DPLL_PVDD

DMINUS

R & CAPS CLOSE TO GPU

CHANNEL A

87 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

2

1

C5217

2

1

C5216

2

1

R5044

2

1

R5043

2

1

R5215

2

1

R5214

2

1

R5221

2

1

R5220

2

1

R5222

2

1

R5219

2

1

R5218

2

1

R5045

L15

K26

D9

A14

E10

C14

E22

C32

D23

A32

K19

K23

L20

L18

AH12

M12

M27

AG12

N12

L27

J19

H17

J17

H16

J16

G16

L13

H20

H19

H23

G21

H21

J26

H26

J24

H24

J23

G24

D7

J10

E12

E16

E20

D25

D29

C34

D13

F14

E14

D15

F16

A16

A5

E6

D17

C6

A6

E8

C8

A8

G9

K10

K9

G8

G10

F18

H11

J13

H13

G13

C10

A10

F10

D11

A12

F12

A18

C18

F30

D31

E32

F32

D33

G32

E18

D19

E34

F20

A20

D21

F22

A22

C22

E24

A24

C24

F24

A35

A26

C26

F26

D27

E28

A28

C28

F28

A30

C30

C35

C37

F8

J11

C12

C16

C20

E26

E30

A34

K16

M13

K27

K24

H14

J14

G27

H27

J20

K21

K17

K20

G19

J21

U5124

P1V5_GPUS

243_1%_2

VM_A1_ADA<16>

VM_A1_ADA<15>

VM_A1_ADA<24>

24

27

VM_A1_ADA<27>

25

21

20

MVREFSA_GPU

243_1%_2

AMD_216_0810_001_FCBGA_962P

VM_A0_ADA<4>

VM_A0_ADA<3>

VM_A0_ADA<2>

VM_A0_ADA<1>

VM_A0_ADA<0>

0

MVREFDA_GPU

0.1UF_16V_2

VM_A1_ADA<31..0>

22

VM_A0_ADA<24>

VM_A0_ADA<25>

VM_A0_ADA<26>

VM_A1_AA<6>

VM_A1_AA<4>

VM_A0_AA<7..0>

0.1UF_16V_2

P1V5_GPUS

40.2_1%_2

VM_A0_ADA<23>

28

100_1%_2

19

100_1%_2

40.2_1%_2

18

19

20

VM_EDCA0_0

VM_EDCA1_0

VM_EDCA0_3

VM_A1_AA<7..0>

VM_A1_ADA<10>

VM_A1_ADA<11>

VM_A1_ADA<13>

12

VM_A1_ADA<12>

31

VM_A0_ADA<29>

VM_A0_ADA<28>

VM_A0_ADA<27>

VM_A0_ADA<22>

VM_A0_ADA<21>

VM_A0_ADA<20>

VM_A1_AA<3>

VM_A1_AA<1>

VM_A0_AA<7>

VM_A0_AA<6>

VM_A1_AA<0>

VM_A0_AA<5>

VM_A0_AA<4>

VM_A0_AA<2>

VM_A0_AA<1>

VM_A0_AA<3>

VM_A0_AA<0>

VM_A1_AA<7>

VM_A1_AA<5>

VM_A1_AA<2>

6

7

5

4

3

2

7

6

4

5

3

0

1

2

1

0

VM_A1_ADA<1>

VM_A1_ADA<2>

2

VM_WCKA0_0_DN

VM_WCKA0_1_DN

VM_WCKA1_0_DP

VM_WCKA1_0_DN

VM_WCKA1_1_DP

22

VM_A1_ADA<22>

VM_A1_ADA<9>

VM_A0_ADA<8>

VM_WCKA1_1_DN

VM_WCKA0_0_DP

VM_WCKA0_1_DP

VM_EDCA1_2

VM_EDCA1_3

VM_EDCA0_2

VM_EDCA0_1

VM_EDCA1_1

VM_A1_ADA<28>

28

27

VM_A0_ADA<30>

DDR_A_CKEA1

VM_A0_ADA<14>

30

VM_A0_ADA<16>

16

15

VM_A0_ADA<12>

VM_A0_ADA<11>

VM_A0_ADA<10>

VM_A0_ADA<9>

VM_DDBIA0_2

VM_DDBIA0_1

VM_DDBIA0_0

VM_DDBIA1_0

VM_DDBIA1_1

VM_DDBIA1_2

VM_DDBIA0_3

VM_DDBIA1_3

DDR_A_CASA1#

DDR_A_CASA0#

DDR_A_RASA1#

VM_ADBIA0

VM_ADBIA1

DDR_A_CSA1#_0

DDR_A_RASA0#

VM_A1_AA<8>

VM_A0_AA<8>

DDR_A_WEA0#

DDR_A_CKEA0

DDR_A_CSA0#_0

VM_A0_ADA<5>

VM_A0_ADA<6>

VM_A0_ADA<7>

VM_A0_ADA<13>

VM_A0_ADA<15>

VM_A0_ADA<17>

VM_A0_ADA<31>

VM_A0_ADA<18>

VM_A0_ADA<19>

5

VM_A0_ADA<31..0>

17

14

13

12

11

10

9

8

7

6

4

3

2

1

29

26

25

24

23

21

VM_A1_ADA<0>

VM_A1_ADA<18>

VM_A1_ADA<17>

VM_A1_ADA<14>

VM_A1_ADA<8>

VM_A1_ADA<7>

VM_A1_ADA<6>

VM_A1_ADA<5>

VM_A1_ADA<4>

VM_A1_ADA<3>

VM_A1_ADA<19>

VM_A1_ADA<20>

VM_A1_ADA<21>

VM_A1_ADA<23>

VM_A1_ADA<25>

VM_A1_ADA<26>

VM_A1_ADA<29>

VM_A1_ADA<30>

VM_A1_ADA<31>

31

30

29

26

23

0

1

3

4

5

6

7

8

9

10

11

13

14

15

16

17

18

DDR_A_CLKA1_DN

DDR_A_CLKA1_DP

DDR_A_CLKA0_DN

DDR_A_CLKA0_DP

DDR_A_WEA1#

C

CS

CS_1310AXXXXXX-MTR

Everest Main Board

Block Diagram

A01

BEN LEE

February 22, 2010

1 1

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

GDDR5

DDR3

GDDR5/GDDR3

DDR2

GDDR5/DDR2/GDDR3

DDR3

GDDR3/GDDR5

DDR2

MEMORY INTERFACE A

WEA1B

WEA0B

DDBIA1_3/QSA_7B/WDQSA_7

DDBIA1_2/QSA_6B/WDQSA_6

DDBIA1_1/QSA_5B/WDQSA_5

DDBIA1_0/QSA_4B/WDQSA_4

DDBIA0_3/QSA_3B/WDQSA_3

DDBIA0_2/QSA_2B/WDQSA_2

DDBIA0_1/QSA_1B/WDQSA_1

DDBIA0_0/QSA_0B/WDQSA_0

MAA1_8

MAA0_8

EDCA1_3/QSA_7/RDQSA_7

EDCA1_2/QSA_6/RDQSA_6

EDCA1_1/QSA_5/RDQSA_5

EDCA1_0/QSA_4/RDQSA_4

EDCA0_3/QSA_3/RDQSA_3

EDCA0_2/QSA_2/RDQSA_2

EDCA0_1/QSA_1/RDQSA_1

EDCA0_0/QSA_0/RDQSA_0

RASA1B

RASA0B

ADBIA1/ODTA1

ADBIA0/ODTA0

MAA1_1/MAA_9

MAA1_0/MAA_8

MAA0_7/MAA_7

MAA0_6/MAA_6

MAA0_5/MAA_5

MAA0_4/MAA_4

MAA0_3/MAA_3

MAA0_2/MAA_2

MAA1_7/MAA_A15_BA1

MAA1_6/MAA_14_BA0

MAA1_5/MAA_13_BA2

MAA1_4/MAA_12

MAA1_3/MAA_11

MAA1_2/MAA_10

MAA0_1/MAA_1

MAA0_0/MAA_0

WCKA1B_1/DQMA_7

WCKA1_1/DQMA_6

WCKA1B_0/DQMA_5

WCKA1_0/DQMA_4

WCKA0B_1/DQMA_3

WCKA0_1/DQMA_2

WCKA0B_0/DQMA_1

WCKA0_0/DQMA_0

CSA1B_1

CSA1B_0

CSA0B_1

CSA0B_0

CLKA1B

CLKA1

CLKA0B

CLKA0

CKEA1

CKEA0

CASA1B

CASA0B

MEM_CALRP2

MEM_CALRP0

MEM_CALRN2

MEM_CALRN1

MEM_CALRN0

MVREFSA

MVREFDA

MEM_CALRP1

DQA0_9/DQA_9

DQA0_8/DQA_8

DQA0_7/DQA_7

DQA1_31/DQA_63

DQA1_30/DQA_62

DQA1_29/DQA_61

DQA1_28/DQA_60

DQA0_6/DQA_6

DQA1_27/DQA_59

DQA1_26/DQA_58

DQA1_25/DQA_57

DQA1_24/DQA_56

DQA1_23/DQA_55

DQA1_22/DQA_54

DQA1_21/DQA_53

DQA1_20/DQA_52

DQA1_19/DQA_51

DQA1_18/DQA_50

DQA0_5/DQA_5

DQA1_17/DQA_49

DQA1_16/DQA_48

DQA1_15/DQA_47

DQA1_14/DQA_46

DQA1_13/DQA_45

DQA1_12/DQA_44

DQA1_11/DQA_43

DQA1_10/DQA_42

DQA1_9/DQA_41

DQA1_8/DQA_40

DQA0_4/DQA_4

DQA1_7/DQA_39

DQA1_6/DQA_38

DQA1_5/DQA_37

DQA1_4/DQA_36

DQA1_3/DQA_35

DQA1_2/DQA_34

DQA1_1/DQA_33

DQA1_0/DQA_32

DQA0_31/DQA_31

DQA0_30/DQA_30

DQA0_3/DQA_3

DQA0_29/DQA_29

DQA0_28/DQA_28

DQA0_27/DQA_27

DQA0_26/DQA_26

DQA0_25/DQA_25

DQA0_24/DQA_24

DQA0_23/DQA_23

DQA0_22/DQA_22

DQA0_21/DQA_21

DQA0_20/DQA_20

DQA0_2/DQA_2

DQA0_19/DQA_19

DQA0_18/DQA_18

DQA0_17/DQA_17

DQA0_16/DQA_16

DQA0_15/DQA_15

DQA0_14/DQA_14

DQA0_13/DQA_13

DQA0_12/DQA_12

DQA0_11/DQA_11

DQA0_10/DQA_10

DQA0_1/DQA_1

DQA0_0/DQA_0

JTAG

R & CAPS CLOSE TO GPU

25MM) AND KEEP ALL COMPONENT CLOSE TO EACH OTHER.

JTAG SIGNAL STUFF OPTION

NORMAL

MODE

(WITHIN 5MM) EXCEPT RSER2

DEBUG ONLY

1

GPU_TESTEN

SIGNALS

0

MODE

R & CAPS CLOSE TO GPU

CHANNEL B

PLACE ALL THESE COMPONENTS VERY CLOSE TO GPU (WITHIN

88 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

2

1

R5049

2

1

C5225

2

1

C5226

2

1

R5051

2

1

R5050

2

1

C5054

2

1

R5052

2

1

R5055

2

1

R5053

2

1

R5047

2

1

R5046

2

1

C5228

2

1

C5227

2

1

R5048

AB11

N10

AK5

AF5

AK6

AE4

T5

H1

T3

H3

AD28

Y10

T10

AA12

Y12

W8

AA9

Y8

AA8

AA7

AC9

AC8

W9

Y9

T8

U8

U9

N9

N8

N7

P9

T9

P8

AM5

AJ9

AH1

AB5

V5

P3

K3

F6

AH11

AF3

AF1

AD5

AD3

AD1

AD6

AP5

AP1

AB3

AP3

AN4

AM1

AM6

AL4

AK1

AM7

AM8

AL7

AK9

AB1

AG7

AG8

AF9

AF8

AK3

AJ4

AH6

AH5

AG4

AF6

AB6

AA4

H6

H5

G4

F5

F3

F1

Y5

Y3

E1

Y1

Y6

V3

V1

V6

U4

T1

T6

R4

P5

E3

P6

N4

M5

M3

M1

M6

L4

K5

K6

J4

C3

C5

AM3

AJ8

AH3

AC4

W4

P1

K1

G7

AC10

AD10

L10

P10

AL10

AK10

AD7

AD8

L8

L9

AA11

U10

AA10

W10

W7

T7

U5124

2

1

R5223

2

1

R5224

51_1%_2_DY51_1%_2_DY

0.1UF_16V_2

MVREFDB_GPU

P1V5_GPUS

40.2_1%_2

VM_B1_ADA<4>

VM_B1_ADA<3>

VM_B1_ADA<2>

VM_B1_ADA<1>

VM_B1_ADA<0>

VM_B0_ADA<31>

VM_B0_AA<0>

VM_B0_AA<2>

VM_B0_AA<5>

VM_B0_ADA<14>

14

5K_1%_2 120PF_50V_2

40.2_1%_2

100_1%_2

VM_B1_ADA<31..0>

3

0.1UF_16V_2

51_1%_2

10_1%_2

0.1UF_16V_2_DY0.1UF_16V_2_DY

10K_5%_2_DY

AMD_216_0810_001_FCBGA_962P

100_1%_2

5.11K_1%_2

P3V3_GPUS

VM_WCKB0_0_DN

VM_WCKB1_1_DN

VM_EDCB0_2

VM_DDBIB0_0

VM_DDBIB1_1

VM_B0_ADA<21>

VM_B1_AA<1>

VM_B0_AA<7>

VM_B0_ADA<15>

VM_B1_AA<7>

VM_B1_AA<6>

VM_B1_AA<5>

VM_B1_AA<7..0>

VM_B0_AA<7..0>

VM_B0_AA<6>

VM_B1_AA<0>

VM_B1_AA<2>

24

VM_B1_ADA<8>

27

VM_B1_ADA<25>

VM_B1_ADA<24>

VM_B1_ADA<22>

VM_B1_ADA<18>

VM_B1_ADA<16>

VM_B1_ADA<14>

VM_B0_AA<4>

VM_B0_ADA<13>

VM_B0_ADA<12>

VM_B0_ADA<11>

6

VM_B1_ADA<28>

VM_B1_ADA<29>

VM_B1_ADA<30>

VM_B1_ADA<31>

BEN LEE

11

A01

CS

C

February 22, 2010

CS_1310AXXXXXX-MTR

Everest Main Board

Block Diagram

MVREFSB_GPU

VM_B1_ADA<23>

VM_B1_ADA<21>

VM_B1_ADA<19>

DDR_B_CLKB0_DN

DDR_B_CLKB0_DP

DDR_B_CLKB1_DP

DDR_B_CLKB1_DN

DDR_B_RASB0#

DDR_B_RASB1#

DDR_B_CASB0#

DDR_B_CSB0#_0

DDR_B_CASB1#

VM_RESET

DDR_B_CKEB0

DDR_B_CKEB1

DDR_B_WEB0#

DDR_B_WEB1#

VM_B0_AA<8>

VM_B1_AA<8>

VM_WCKB0_0_DP

4

VM_B0_AA<3>

VM_B0_AA<1>

3

VM_B1_AA<3>

2

7

5

6

5

4

VM_WCKB0_1_DP

VM_WCKB0_1_DN

VM_WCKB1_0_DN

VM_EDCB0_0

VM_EDCB0_1

VM_EDCB1_1

VM_EDCB1_2

0

3

1

7

6

2

1

0

VM_WCKB1_0_DP

VM_B1_ADA<6>

30

VM_B0_ADA<17>

VM_B0_ADA<18>

VM_B0_ADA<4>

VM_B0_ADA<3>

VM_B1_ADA<27>

17

VM_B0_ADA<16>

VM_B0_ADA<29>

VM_B0_ADA<28>

10

VM_B1_ADA<10>

VM_EDCB1_0

VM_DDBIB0_1

VM_ADBIB1

VM_ADBIB0

VM_DDBIB0_2

VM_DDBIB0_3

VM_DDBIB1_0

VM_DDBIB1_2

VM_DDBIB1_3

VM_EDCB1_3

VM_WCKB1_1_DP

30

VM_B0_ADA<27>

VM_B0_ADA<25>

28

VM_B0_ADA<24>

7

VM_B0_ADA<8>

13

VM_B0_ADA<10>

VM_B0_ADA<9>

VM_B0_ADA<7>

VM_B0_ADA<6>

VM_B0_ADA<5>

VM_B0_ADA<2>

VM_B0_ADA<1>

VM_B0_ADA<0>

VM_B0_ADA<30>

VM_B0_ADA<23>

VM_B0_ADA<22>

VM_B0_ADA<20>

VM_B0_ADA<19>

VM_B1_ADA<20>

VM_B1_ADA<17>

VM_B1_ADA<15>

VM_B1_ADA<13>

VM_B1_ADA<12>

VM_B1_ADA<11>

VM_B1_ADA<9>

VM_B1_ADA<7>

VM_B1_ADA<5>

VM_B1_ADA<26>

23

12

17

18

25

31

29

28

26

25

22

21

20

19

16

15

14

13

11

9

8

7

6

5

4

2

1

0

31

29

27

26

24

23

22

21

20

19

18

16

15

12

11

10

9

8

5

4

3

2

1

0

DDR_B_CSB1#_0

VM_B0_ADA<31..0>

VM_RESET_R2VM_RESET_R1

VM_EDCB0_3

VM_B1_AA<4>

VM_B0_ADA<26>

GPU_TESTEN

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

BI

OUT

BI

OUT

BI

OUT

GDDR5/DDR2/GDDR3

GDDR5

DDR3

GDDR3/GDDR5

DDR2

DDR3

GDDR5/GDDR3

DDR2

MEMORY INTERFACE B

MAB1_8

MAB0_8

WEB1B

WEB0B

DDBIB1_3/QSB_7B/WDQSB_7

DDBIB1_2/QSB_6B/WDQSB_6

DDBIB1_1/QSB_5B/WDQSB_5

DDBIB1_0/QSB_4B/WDQSB_4

DDBIB0_3/QSB_3B/WDQSB_3

DDBIB0_2/QSB_2B/WDQSB_2

DDBIB0_1/QSB_1B/WDQSB_1

DDBIB0_0/QSB_0B/WDQSB_0

EDCB1_3/QSB_7/RDQSB_7

EDCB1_2/QSB_6/RDQSB_6

EDCB1_1/QSB_5/RDQSB_5

EDCB1_0/QSB_4/RDQSB_4

EDCB0_3/QSB_3/RDQSB_3

EDCB0_2/QSB_2/RDQSB_2

EDCB0_1/QSB_1/RDQSB_1

EDCB0_0/QSB_0/RDQSB_0

RASB1B

RASB0B

ADBIB1/ODTB1

ADBIB0/ODTB0

MAB1_1/MAB_9

MAB1_0/MAB_8

MAB0_7/MAB_7

MAB0_6/MAB_6

MAB0_5/MAB_5

MAB0_4/MAB_4

MAB0_3/MAB_3

MAB0_2/MAB_2

MAB1_7/BA1

MAB1_6/BA0

MAB1_5/BA2

MAB1_4/MAB_12

MAB1_3/MAB_11

MAB1_2/MAB_10

MAB0_1/MAB_1

MAB0_0/MAB_0

DRAM_RST

WCKB1B_1/DQMB_7

WCKB1_1/DQMB_6

WCKB1B_0/DQMB_5

WCKB1_0/DQMB_4

WCKB0B_1/DQMB_3

WCKB0_1/DQMB_2

WCKB0B_0/DQMB_1

WCKB0_0/DQMB_0

CSB1B_1

CSB1B_0

CSB0B_1

CSB0B_0

CLKTESTB

CLKTESTA

CLKB1B

CLKB1

CLKB0B

CLKB0

CKEB1

CKEB0

CASB1B

CASB0B

TESTEN

MVREFSB

MVREFDB

DQB0_9/DQB_9

DQB0_8/DQB_8

DQB0_7/DQB_7

DQB1_31/DQB_63

DQB1_30/DQB_62

DQB1_29/DQB_61

DQB1_28/DQB_60

DQB0_6/DQB_6

DQB1_27/DQB_59

DQB1_26/DQB_58

DQB1_25/DQB_57

DQB1_24/DQB_56

DQB1_23/DQB_55

DQB1_22/DQB_54

DQB1_21/DQB_53

DQB1_20/DQB_52

DQB1_19/DQB_51

DQB1_18/DQB_50

DQB0_5/DQB_5

DQB1_17/DQB_49

DQB1_16/DQB_48

DQB1_15/DQB_47

DQB1_14/DQB_46

DQB1_13/DQB_45

DQB1_12/DQB_44

DQB1_11/DQB_43

DQB1_10/DQB_42

DQB1_9/DQB_41

DQB1_8/DQB_40

DQB0_4/DQB_4

DQB1_7/DQB_39

DQB1_6/DQB_38

DQB1_5/DQB_37

DQB1_4/DQB_36

DQB1_3/DQB_35

DQB1_2/DQB_34

DQB1_1/DQB_33

DQB1_0/DQB_32

DQB0_31/DQB_31

DQB0_30/DQB_30

DQB0_3/DQB_3

DQB0_29/DQB_29

DQB0_28/DQB_28

DQB0_27/DQB_27

DQB0_26/DQB_26

DQB0_25/DQB_25

DQB0_24/DQB_24

DQB0_23/DQB_23

DQB0_22/DQB_22

DQB0_21/DQB_21

DQB0_20/DQB_20

DQB0_2/DQB_2

DQB0_19/DQB_19

DQB0_18/DQB_18

DQB0_17/DQB_17

DQB0_16/DQB_16

DQB0_15/DQB_15

DQB0_14/DQB_14

DQB0_13/DQB_13

DQB0_12/DQB_12

DQB0_11/DQB_11

DQB0_10/DQB_10

DQB0_1/DQB_1

DQB0_0/DQB_0

BI

1.0V,1.1A

1.8V,0.04A

1.0V,0.1A

GDDR5 900MHZ,1.5V,2.3A(PEAK)

VDDC+VDDCI=43.3A(PEAK)

GPU POWER

1.8V,0.44A

1.8V,0.04A

1.8V,0.017A

3.3V,0.06A

1.8V,0.17A

VDDC+VDDCI=43.3A(PEAK)

WAITING POWER DESIGN

VOLTAGE SENESE

1.8V,0.15A

BIF_VDDC IS SEPARATE CORE

POWER FOR THE PCIE BUS LOGIC.

1.8V,0.05A

Follow GDDR3 ORB

THAT HAVE A CHANGE OF REFERENCE PLANE

ONE CAP PER THREE SIGNALS

VOLTAGE.ADD STITCHING CAPS WHEN REQUIRED,

STITCHING CAPS OPTION FOR MEM SIGNALS

9789

MODEL,PROJECT,FUNCTION

X01

XXX

1310xxxxx-0-0

21-OCT-2002

2

1

C5278

2

1

C5280

2

1

C5286

2

1

C5277

2

1

C5279

2

1

C5285

2

1

C5292

2

1

C5299

2

1

C5309

2

1

C5311

2

1

C5317

2

1

C5323

2

1

C5329

2

1

C5315

2

1

C5322

2

1

C5327

2

1

C5333

2

1

C5340

2

1

C5308

2

1

C5296

2

1

C5303

2

1

C5291

2

1

C5061

2

1

C5284

2

1

C5290

2

1

C5295

2

1

C5302

2

1

C5307

2

1

C5314

2

1

C5321

2

1

C5326

2

1

C5332

2

1

C5337

2

1

C5062

2

1

C5064

2

1

C5298

2

1

C5304

2

1

C5310

2

1

C5063

2

1

C5065

2

1

C5066

2

1

C5056

2

1

C5058

2

1

C5060

2

1

L5057

2

1

C5059

2

1

C5241

2

1

C5244

2

1

C5236

2

1

C5239

2

1

C5232

2

1

C5229

2

1

C5248

2

1

C5252

2

1

C5254

2

1

C5259

2

1

C5266

2

1

C5271

2

1

C5234

2

1

C5237

2

1

C5270

2

1

C5265

2

1

C5258

2

1

C5253

2

1

C5251

2

1

C5247

2

1

C5246

2

1

C5240

2

1

L5336

2

1

L5233

2

1

L5250

2

1

L5249

2

1

L5230

2

1

C5231

2

1

C5235

2

1

L5243

2

1

C5260

2

1

C5267

2

1

C5275

2

1

C5257

2

1

C5264

2

1

C5276

2

1

C5245

2

1

C5238

2

1

C5242

2

1

C5263

2

1

C5269

2

1

C5274

2

1

C5256

2

1

C5273

2

1

C5268

2

1

C5262

2

1

C5255

2

1

C5272

2

1

C5261

2

1

C5281

2

1

C5287

2

1

C5283

2

1

C5289

2

1

C5294

2

1

C5301

2

1

C5306

2

1

C5313

2

1

C5320

2

1

C5325

2

1

C5331

2

1

C5339

2

1

C5312

2

1

C5319

2

1

C5324

2

1

C5330

2

1

C5338

2

1

C5305

2

1

C5300

2

1

C5293

2

1

C5288

2

1

C5282

2

1

C5335

2

1

C5328

2

1

C5318

2

1

C5334

2

1

C5297

2

1

C5316

AG15

AG13

AG11

AF15

AF13

AF12

AF11

AD12

AG24

AG23

AF24

AF23

G14

G11

AL9

AK8

AJ7

AG10

Y7

Y11

U7

U11

R11

AF7

P7

N11

M11

L7

L26

L23

L21

L16

L12

K8

AD11

K13

K11

J9

J7

H10

G29

G26

G23

G20

G17

AC7

M18

M16

M15

AD16

AD13

AC15

AC12

Y13

V15

T15

AB13

T12

R16

R13

R12

N22

N20

N17

N15

N13

M23

AA13

T27

N27

AB21

AB18

AB16

AA27

Y28

Y26

Y23

Y21

Y18

Y16

V27

V24

V22

AA24

V20

V17

U26

U23

U21

U18

U16

T24

T22

AA22

T20

T17

R26

R23

R21

R18

N24

M26

AH28

AA20

AH27

AH22

AG21

AG18

AG16

AF22

AF20

AF17

AD26

AD23

AA17

AD21

AD18

AC27

AC24

AC22

AC20

AC17

AB28

AB26

AB23

AA15

AG27

AG26

AF27

AF26

AN10

AM10

AN9

AB37

Y31

W30

W29

V28

AA34

AA33

AA32

AA31

N28

M28

L28

J30

J29

H30

H29

G31

U28

T28

R28

G30

U12

M21

V12

M20

H8

H7

AG28

AF28

AH29

U5124

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

SPV10

FBM_11_160808_121T

SPV18

0.1UF_16V_2

AMD_216_0810_001_FCBGA_962P

1UF_6.3V_2

P1V5_GPUS

PCIE_PVDD

1UF_6.3V_2

PCIE_VDDR

0.1UF_16V_2

10UF_6.3V_3

P1V8_GPUS

FBM_11_160808_121T

P3V3_GPUS

PCIE_PVDD

P1V8_GPUS

FBM_11_160808_121T

10UF_6.3V_3

1UF_6.3V_2

P1V8_GPUS

FBM_11_160808_121T

P1V8_GPUS

FBM_11_160808_121T

P1V0_GPU

10UF_6.3V_3

PVCORE_GPU

1UF_6.3V_2

BIF_VDDC

P1V8_GPUS

BLM18PG600SN1D

P1V0_GPU

10UF_6.3V_3

1UF_6.3V_2

10UF_6.3V_3 1UF_6.3V_2

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

1UF_6.3V_2

FBM_11_160808_121T

10UF_6.3V_3

1UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

1UF_6.3V_2

1UF_6.3V_21UF_6.3V_20.1UF_16V_2

1UF_6.3V_2

1UF_6.3V_210UF_6.3V_3

10UF_6.3V_3

1UF_6.3V_2

0.1UF_16V_2

P1V8_GPUS

PVCORE_GPU

VDD_CT

MVP18

VDDR4

BEN LEE

1

A01

Block Diagram

Everest Main Board

February 22, 2010

1

CS_1310AXXXXXX-MTR

CS

C

TITLE

DATE

CODE

SIZE

1

E

D

C

B

A

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

of

CHANGE by

8

REV

DOC.NUMBER

SHEET

2

INVENTEC

SENESE

VOLTAGE

CORE I/O

ISOLATED

TRANSLATION

LEVEL

I/O

MEM I/O

CORE

PCIE

PLL

POWER

FB_GND

FB_VDDCI

FB_VDDC

VDDC#30

VDDC#29

VDDCI#22

VDDCI#1

VDDCI#19

VDDCI#16

VDDCI#11

VDDCI#7

VDDC#8

VDDC#7

VDDC#58

VDDC#57

VDDC#56

VDDCI#2

VDDC#55

VDDC#54

VDDC#53

VDDC#52

VDDC#51

VDDC#50

VDDC#49

VDDC#48

VDDCI#21

VDDC#47

VDDC#6

VDDC#46

VDDC#45

VDDC#44

VDDC#43

VDDC/BIF_VDDC#42

VDDC#41

VDDC#40

VDDC#39

VDDC#38

VDDCI#20

VDDC#5

VDDC#37

VDDC#36

VDDC#35

VDDC#34

VDDCI#18

VDDCI#17

VDDC/BIF_VDDC#33

VDDC#32

VDDCI#15

VDDCI#14

VDDC#4

VDDCI#13

VDDCI#12

VDDC#31

VDDCI#10

VDDCI#9

VDDCI#8

VDDC#28

VDDC#27

VDDC#26

VDDC#25

VDDC#3

VDDC#24

VDDC#23

VDDC#22

VDDC#21

VDDC#20

VDDC#19

VDDC#18

VDDCI#6

VDDCI#5

VDDC#17

VDDC#2

VDDC#16

VDDC#15

VDDC#14

VDDC#13

VDDCI#4

VDDCI#3

VDDC#12

VDDC#11

VDDC#10

VDDC#9

VDDC#1

VDD_CT#4

VDD_CT#3

VDD_CT#2

VDD_CT#1

NC_VSSRHB

NC_VSSRHA

NC_VDDRHB

NC_VDDRHA

VDDR4#6

VDDR4#3

VDDR4#2

VDDR4#1

VDDR4#8

VDDR4#7

VDDR4#5

VDDR4#4

VDDR3#4

VDDR3#3

VDDR3#2

VDDR3#1

VDDR1#9

VDDR1#8

VDDR1#7

VDDR1#6

VDDR1#5

VDDR1#4

VDDR1#34

VDDR1#33

VDDR1#32

VDDR1#31

VDDR1#30

VDDR1#3

VDDR1#29

VDDR1#28

VDDR1#27

VDDR1#26

VDDR1#25

VDDR1#24

VDDR1#23

VDDR1#22

VDDR1#21

VDDR1#20

VDDR1#2

VDDR1#19

VDDR1#18

VDDR1#17

VDDR1#16

VDDR1#15

VDDR1#14

VDDR1#13

VDDR1#12

VDDR1#11

VDDR1#10

VDDR1#1

SPVSS

SPV10

PCIE_VDDR#8

PCIE_VDDR#7

PCIE_VDDR#6

PCIE_VDDR#5

PCIE_VDDR#4

PCIE_VDDR#3

PCIE_VDDR#2

PCIE_VDDR#1

PCIE_VDDC#9

PCIE_VDDC#8

PCIE_VDDC#7

PCIE_VDDC#6

PCIE_VDDC#5

PCIE_VDDC#4

PCIE_VDDC#3

PCIE_VDDC#2

PCIE_VDDC#12

PCIE_VDDC#11

PCIE_VDDC#10

PCIE_VDDC#1

SPV18

MPV18#2

MPV18#1

PCIE_VDDR/PCIE_PVDD

BACO

PX_MODE=0, FOR BACO MODE

PX_MODE=1, FOR NORMAL MODE

9790

MODEL,PROJECT,FUNCTION

X01

XXX

1310xxxxx-0-0

21-OCT-2002

P1V0_GPU

4.7UF_6.3V_3

AB24

Everest Main Board

Block Diagram

February 22, 2010

C

CS

CS_1310AXXXXXX-MTR

1

A01

1

BEN LEE

AMD_216_0810_001_FCBGA_962P

AM2302N

P5V_S

SSM3K7002BFU

PVCORE_GPU

10K_5%_2

1K_5%_2

4.7UF_6.3V_3

ALPHA_AO3416_SOT23_3P

VPCIE_ON

VDDC_ON

PX_EN

VPCIE_ON

VDDC_ON

0_5%_2

PX_MODE

SSM3K7002BFU

0_5%_3_DY

U5124

A3

AA6

F15

F17

F19

F21

F23

F25

F27

F29

F31

F33

AB12

F7

F9

G2

G6

H9

J2

J27

J6

J8

K14

AB15

K7

L11

L17

L2

L22

L24

L6

M17

M22

M24

N16

N18

N2

N21

N23

N26

N6

R15

R17

R2

AB20

R20

R22

R24

R27

R6

T11

T13

T16

T18

T21

AB22

T23

T26

U13

U15

U17

U2

U20

U22

U24

U27

U6

V11

V13

V16

V18

V21

V23

V26

W2

W6

AB27

Y15

Y17

Y20

Y22

Y24

Y27

AC11

AC13

A37

AC16

AC18

AC2

AC21

AC23

AC26

AC28

AC6

AD15

AD17

AA16

AD20

AD22

AD24

AD27

AD9

AE2

AE6

AF10

AF16

AF18

AA18

AF21

AG17

AG2

AG20

AG22

AG6

AG9

AH21

AJ10

AJ11

AA2

AJ2

AJ28

AJ6

AK11

AK31

AK7

AL11

AL14

AL17

AL2

AA21

AL20

AL23

AL26

AL32

AL6

AL8

AM11

AM31

AM9

AA23

AN11

AN2

AN30

AN6

AN8

AP11

AP7

AP9

AR5

B11

AA26

B13

B15

B17

B19

B21

B23

B25

B27

B29

B31

AA28

B33

B7

B9

C1

C39

E35

E5

F11

F13

AL21

AB39

J31

J34

K31

K34

K39

L31

L34

M39

N31

E39

N34

P31

P34

P39

R34

T31

T34

T39

U31

U34

F34

V34

V39

W31

W34

Y34

Y39

F39

G33

G34

H31

H34

H39

A39

AW1

AW39

Q5341

1

2

R5342

1

2

1

4

1

24

5

1

2

Q5351

2

Q5072

3

2

1

2

R5353

1

2

1

2

3

1

Q5069

D

G

S

C5347

1

2

1

2

1

2

Q5343

3

1

2

1

2

M34

5

1

3

10K_5%_2

2

C5345

P3V3_S

SSM3K7002BFU

P3V3_S

C5348

0.1UF_16V_2

R5352

1K_5%_2

3

TC7SZ08FU

R5068

0_5%_2_DY

2

11

P3V3_S

AB17

TC7SZ08FU

3

SSM3K7002BFU

DGPU_PWR_EN#

R5344

P3V3_GPUS

3

Q5070

C5346

DGPU_PWROK

R5071

U5349

U5067

PX_EN#

2

0.1UF_16V_2

VDDC_GPU_PG

PX_MODE

PVCORE_GPU

R5350

BIF_VDDC

TITLE

DATE

CODE

SIZE

1

E

D

C

B

A

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

of

CHANGE by

8

REV

DOC.NUMBER

SHEET

2

INVENTEC

+

-

G

DS

IN

OUT

G

DS

IN

S

G

D

G

S D

IN

G

D S

OUT

G

DS

G

DS

+

-

IN

GND

GND#162

GND#152

GND#97

GND#96

GND#95

GND#94

GND#93

GND#92

GND#91

GND#90

GND#89

GND#88

GND#9

GND#87

GND#86

GND#85

GND#84

GND#83

GND#82

GND#81

GND#80

GND#79

GND#8

GND#78

GND#77

GND#76

GND#75

GND#74

GND#73

GND#72

GND#71

GND#70

GND#69

GND#7

GND#68

GND#67

GND#66

GND#65

GND#64

GND#63

GND#62

GND/PX_EN#61

GND#60

GND#59

GND#6

GND#58

GND#57

GND#56

GND#55

GND#54

GND#53

GND#52

GND#51

GND#50

GND#49

GND#5

GND#48

GND#47

GND#46

GND#45

GND#44

GND#43

GND#42

GND#41

GND#40

GND#4

GND#39

GND#38

GND#37

GND#36

GND#35

GND#34

GND#33

GND#32

GND#31

GND#30

GND#3

GND#29

GND#28

GND#27

GND#26

GND#25

GND#24

GND#23

GND#22

GND#21

GND#20

GND#2

GND#19

GND#18

GND#175

GND#174

GND#173

GND#172

GND#171

GND#17

GND#170

GND#169

GND#168

GND#167

GND#166

GND#165

GND#164

GND#163

GND#161

GND#160

GND#16

GND#159

GND#158

GND#157

GND#156

GND#155

GND#154

GND#153

GND#151

GND#150

GND#149

GND#15

GND#148

GND#147

GND#146

GND#145

GND#144

GND#143

GND#142

GND#141

GND#140

GND#139

GND#14

GND#138

GND#137

GND#136

GND#135

GND#134

GND#133

GND#132

GND#131

GND#130

GND#129

GND#13

GND#128

GND#127

GND#126

GND#125

GND#124

GND#123

GND#122

GND#121

GND#120

GND#119

GND#12

GND#118

GND#117

GND#116

GND#115

GND#114

GND#113

GND#112

GND#111

GND#110

GND#109

GND#11

GND#108

GND#107

GND#106

GND#105

GND#104

GND#103

GND#102

GND#101

GND#100

GND#98

GND#10

GND#1

VSS_MECH#3

VSS_MECH#2

VSS_MECH#1

PCIE_VSS#9

PCIE_VSS#8

PCIE_VSS#7

PCIE_VSS#6

PCIE_VSS#5

PCIE_VSS#4

PCIE_VSS#35

PCIE_VSS#34

PCIE_VSS#33

PCIE_VSS#32

PCIE_VSS#31

PCIE_VSS#30

PCIE_VSS#3

PCIE_VSS#29

PCIE_VSS#28

PCIE_VSS#27

PCIE_VSS#26

PCIE_VSS#25

PCIE_VSS#24

PCIE_VSS#23

PCIE_VSS#22

PCIE_VSS#21

PCIE_VSS#20

PCIE_VSS#2

PCIE_VSS#19

PCIE_VSS#18

PCIE_VSS#17

PCIE_VSS#16

PCIE_VSS#15

PCIE_VSS#14

PCIE_VSS#13

PCIE_VSS#12

PCIE_VSS#11

PCIE_VSS#10

PCIE_VSS#1

1.8V,0.33A

SUPPORT FUTURE GPU MULTI

1.0V,0.33A

1.0V,0.22A

FUTURE ASIC

1.0V,0.33A

PS_0: BALL AM34

ADD THESE BOM OPTIONS TO

LEVEL PIN STRAPS FEATURE.

40MILL 40MILL

1.8V,0.33A

91

97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

2

1

C5076

2

1

R5075

2

1

R5074

2

1

R5073

2

1

C5379

2

1

C5376

2

1

C5373

2

1

C5380

2

1

C5377

2

1

C5374

2

1

C5381

2

1

C5378

2

1

C5375

2

1

C5361

2

1

C5364

2

1

C5367

2

1

C5360

2

1

C5363

2

1

C5366

2

1

L5371

2

1

L5369

2

1

L5357

2

1

L5355

2

1

L5368

2

1

L5354

2

1

R5372

2

1

R5370

2

1

R5358

2

1

R5356

2

1

C5365

2

1

C5362

2

1

C5359

2

1

R5384

2

1

R5382

2

1

R5383

AK27

AF35

AG36

AG38

AH37

AH35

AJ36

AJ38

AK37

AN36

AP37

AP35

AR35

AR37

AU39

AW37

AU35

AK35

AL36

AP34

AR34

AJ27

U5124

AL38

AM37

AM39

AG34

AF34

AK34

AK33

AJ34

AH34

AM33

AL33

AV19

AU18

AW18

AP23

AP22

AP15

AP14

AP21

AP20

AT13

AP13

AV29

AU28

AW28

AP26

AP25

AP33

AN33

AP24

AN24

AP32

AP31

AM35

AN38

AR18

AV17

AR28

AV27

AM34

AL34

AK39

AH39

AF39

AU37

AR39

AP39

AN34

AW22

AW20

AP19

AP18

AN19

AW16

AW14

AP17

AP16

AN17

AW32

AW30

AP30

AP29

AN29

AW26

AW24

AP28

AP27

AN27

U5124

1UF_6.3V_2

0.1UF_16V_2

10K_5%_2_DY

DPEF_VDD18

DPCD_VDD18

DPAB_VDD18

DPAB_VDD10

DPAB_VDD18

DPAB_VDD10

DPAB_VDD18

DPCD_VDD18

DPCD_VDD10 DPCD_VDD18

DPCD_VDD10

DPEF_VDD10 DPEF_VDD18

0_1%_3

DPEF_VDD10

10UF_6.3V_3

0.1UF_16V_2

1UF_6.3V_2

10UF_6.3V_3

0_1%_3

150_1%_2

10UF_6.3V_3

1UF_6.3V_2

AMD_216_0810_001_FCBGA_962P

150_1%_2 150_1%_2

0_1%_3

BLM18PG181SN1D

BLM18PG181SN1D_DY

1UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

10UF_6.3V_3

1UF_6.3V_2

0_5%_2

10K_5%_2_DY 0.1UF_16V_2_DY

0.1UF_16V_20.1UF_16V_2

P1V0_GPU

DPEF_VDD18

DPCD_VDD10

DPAB_VDD10DPCD_VDD18

P1V8_GPUS

DPAB_VDD18

C

CS_1310AXXXXXX-MTR

A01

BEN LEE

February 22, 2010

1 1

Everest Main Board

Block Diagram

CS

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

LVDS CONTROL

LVTMDP

VARY_BL

TXOUT_U3P

TXOUT_U3N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_L3P

TXOUT_L3N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

DIGON

DP E/F POWER

DP C/D POWER DP A/B POWER

DP PLL POWER

DP/DPF_VSSR#5

DP/DPF_VSSR#4

DP/DPF_VSSR#3

DP/DPF_VSSR#2

DP/DPF_VSSR#1

DPEF/DPF_VDD18#2

DPEF/DPF_VDD18#1

DPEF/DPF_VDD10#2

DPEF/DPF_VDD10#1

DP_VSSR/DPF_PVSS

DPEF_VDD18/DPF_PVDD

DPEF_CALR

DP/DPE_VSSR#4

DP/DPE_VSSR#3

DP/DPE_VSSR#2

DP/DPE_VSSR#1

DPEF/DPE_VDD18#2

DPEF/DPE_VDD18#1

DPEF/DPE_VDD10#2

DPEF/DPE_VDD10#1

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPE_PVDD

DP/DPD_VSSR#5

DP/DPD_VSSR#4

DP/DPD_VSSR#3

DP/DPD_VSSR#2

DP/DPD_VSSR#1

DPCD/DPD_VDD18#2

DPCD/DPD_VDD18#1

DPCD/DPD_VDD10#2

DPCD/DPD_VDD10#1

DP_VSSR/DPD_PVSS

DPCD_VDD18/DPD_PVDD

DPCD_CALR

DP/DPC_VSSR#5

DP/DPC_VSSR#4

DP/DPC_VSSR#3

DP/DPC_VSSR#2

DP/DPC_VSSR#1

DPCD/DPC_VDD18#2

DPCD/DPC_VDD18#1

DPCD/DPC_VDD10#2

DPCD/DPC_VDD10#1

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPC_PVDD

DP/DPB_VSSR#5

DP/DPB_VSSR#4

DP/DPB_VSSR#3

DP/DPB_VSSR#2

DP/DPB_VSSR#1

DPAB/DPB_VDD18#2

DPAB/DPB_VDD18#1

DPAB/DPB_VDD10#2

DPAB/DPB_VDD10#1

DP_VSSR/DPB_PVSS

DPAB_VDD18/DPB_PVDD

DPAB_CALR

DP/DPA_VSSR#5

DP/DPA_VSSR#4

DP/DPA_VSSR#3

DP/DPA_VSSR#2

DP/DPA_VSSR#1

DPAB/DPA_VDD18#2

DPAB/DPA_VDD18#1

DPAB/DPA_VDD10#2

DPAB/DPA_VDD10#1

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPA_PVDD

CHANNEL A MEMORY

GDDR5

9792

MODEL,PROJECT,FUNCTION

X01

XXX

1310xxxxx-0-0

21-OCT-2002

2

1

C5506

2

1

C5505

2

1

C5504

2

1

C5503

2

1

C5502

2

1

C5501

2

1

C5499

2

1

C5500

2

1

C5476

2

1

C5475

2

1

C5474

2

1

C5473

2

1

C5472

2

1

C5471

2

1

C5470

2

1

C5469

2

1

C5496

2

1

C5491

2

1

C5483

2

1

C5464

2

1

C5460

2

1

C5081

2

1

C5477

2

1

C5453

2

1

C5454

2

1

C5459

2

1

C5462

2

1

C5463

2

1

C5465

2

1

C5466

2

1

C5467

2

1

C5468

2

1

C5478

2

1

C5479

2

1

C5480

2

1

C5482

2

1

C5486

2

1

C5490

2

1

C5493

2

1

C5498

2

1

R5485

2

1

R5489

2

1

R5456

2

1

R5455

2

1

R5481

2

1

R5090

2

1

C5484

2

1

R5487

2

1

R5488

2

1

C5492

2

1

R5495

2

1

C5497

2

1

R5494

2

1

R5091

2

1

R5092

2

1

R5093

J13

L12

P4

P5

D4

D5

V3

V14

V12

V1

R4

R3

R14

R12

R11

R1

N3

N14

N12

N1

M5

M10

K2

K13

H2

H13

F5

F10

E3

E14

E12

E1

C4

C3

C14

C12

C11

C1

A3

A14

A12

A1

T5

T10

P10

L5

L10

K14

K1

H14

H1

G5

G10

D10

B5

B10

V10

A10

J14

V5

A5

T3

T14

T12

T1

P3

P14

P12

P1

N5

N10

M3

M14

M12

M1

L2

L13

K3

K12

H3

H12

G2

G13

F3

F14

F12

F1

E5

E10

D3

D14

D12

D1

B3

B14

B12

B1

R5

R10

P11

L4

L14

L11

L1

G4

G14

G11

G1

D11

C5

C10

J10

J5

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

B2

M2

M4

B4

N2

N4

T2

T4

V2

V4

M13

M11

N13

N11

A2

T13

T11

V13

V11

F13

F11

E13

E11

B13

B11

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

J4

K4

K5

K10

K11

H10

H11

H5

H4

U5094

2

1

R5079

2

1

R5080

2

1

C5082

2

1

C5461

2

1

R5458

2

1

R5457

2

1

C5086

2

1

R5085

2

1

R5084

2

1

R5088

2

1

R5083

2

1

R5087

J13

L12

P4

P5

D4

D5

V3

V14

V12

V1

R4

R3

R14

R12

R11

R1

N3

N14

N12

N1

M5

M10

K2

K13

H2

H13

F5

F10

E3

E14

E12

E1

C4

C3

C14

C12

C11

C1

A3

A14

A12

A1

T5

T10

P10

L5

L10

K14

K1

H14

H1

G5

G10

D10

B5

B10

V10

A10

J14

V5

A5

T3

T14

T12

T1

P3

P14

P12

P1

N5

N10

M3

M14

M12

M1

L2

L13

K3

K12

H3

H12

G2

G13

F3

F14

F12

F1

E5

E10

D3

D14

D12

D1

B3

B14

B12

B1

R5

R10

P11

L4

L14

L11

L1

G4

G14

G11

G1

D11

C5

C10

J10

J5

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

B2

M2

M4

B4

N2

N4

T2

T4

V2

V4

M13

M11

N13

N11

A2

T13

T11

V13

V11

F13

F11

E13

E11

B13

B11

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

J4

K4

K5

K10

K11

H10

H11

H5

H4

U5089

P1V5_GPUS

VM_A1_ADA<5>

5

VM_A1_ADA<31..0>

P1V5_GPUS

VM_A0_AA<0>

60.4_1%_2

DDR_A_CKEA0

P1V5_GPUS

0.1UF_16V_2

10UF_6.3V_3

1UF_6.3V_2

5.49K_1%_2

60.4_1%_2

DDR_A_CASA1#

DDR_A_RASA1#

DDR_A_CKEA1

P1V5_GPUS

VM_DDBIA0_2

VM_DDBIA0_3

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2_DY

10UF_6.3V_3

1UF_6.3V_2

2.37K_1%_2

1UF_6.3V_2

2.37K_1%_25.49K_1%_2

1UF_6.3V_2

5.49K_1%_2

1UF_6.3V_2

2.37K_1%_2

0_5%_2_DY

120_1%_2

0_5%_2

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

2.37K_1%_25.49K_1%_2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

0_5%_2

0_5%_2_DY

120_1%_2

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

1UF_6.3V_2

P1V5_GPUS P1V5_GPUS

P1V5_GPUS

P1V5_GPUSP1V5_GPUS

P1V5_GPUS

VM_WCKA1_0_DN

VM_WCKA1_1_DN

VM_A1_AA<6>

VM_A1_AA<5>

14

VM_A1_ADA<14>

VM_A1_ADA<15>

VM_A1_ADA<13>

VM_A1_ADA<9>

VM_A1_ADA<8>

VM_A1_ADA<11>

VM_A1_ADA<0>

VM_A1_ADA<12>

VM_A1_ADA<31>

6

4

7

3

2

1

0

11

10

8

9

12

13

31

24

30

26

29

25

28

27

18

21

17

22

23

16

20

0

1

3

2

5

4

7

6

29

27

31

25

28

24

16

20

17

21

18

22

19

23

5

6

3

7

4

2

1

0

11

10

8

9

14

12

13

15

7

6

5

3

2

1

0

VM_A1_ADA<6>

VM_A1_ADA<7>

VM_A1_ADA<2>

VM_A1_ADA<1>

VM_A1_ADA<10>

VM_A1_ADA<24>

VM_A1_ADA<30>

VM_A1_ADA<26>

VM_A1_ADA<29>

VM_A1_ADA<25>

VM_A1_ADA<28>

VM_A1_ADA<27>

VM_A1_ADA<18>

VM_A1_ADA<17>

VM_A1_ADA<22>

VM_A1_ADA<19>

VM_A1_ADA<23>

VM_A1_ADA<16>

VM_A1_ADA<20>

VM_A1_AA<2>

VM_A1_AA<0>

VM_A1_AA<1>

VM_A1_AA<4>

VM_A1_AA<3>

VM_EDCA1_3

VM_EDCA1_1

VM_DDBIA1_1

DDR_A_CLK1_DN

VM_REFDC_A1

VM_REFD2_A1

VM_REFD1_A1

VM_A0_ADA<31>

VM_A0_ADA<28>

VM_A0_ADA<19>

VM_A0_ADA<23>

VM_A0_ADA<5>

VM_A0_ADA<6>

VM_A0_ADA<3>

VM_A0_ADA<4>

VM_A0_ADA<1>

VM_A0_ADA<11>

VM_A0_ADA<8>

VM_A0_ADA<12>

VM_A0_AA<2>

VM_DDBIA0_0

DDR_A_RASA0#

VM_A0_AA<7..0>

VM_A0_AA<8>

DDR_A_CLK0_DN

DDR_A_CLK0_DP

DDR_A_WEA0#

VM_REFD1_A0

BEN LEE

1

A01

Block Diagram

Everest Main Board

February 22, 2010

1

CS

C

CS_1310AXXXXXX-MTR

VM_A0_ADA<22>

VM_A1_ADA<4>

VM_A1_ADA<3>

VM_A0_ADA<13>

VM_A0_AA<3>

VM_A0_AA<4>

26

VM_A0_ADA<31..0>

30

VM_WCKA0_0_DP

4

VM_A0_ADA<24>

VM_A1_AA<8>

VM_A1_AA<7..0>

VM_A1_AA<7>

VM_EDCA1_0

VM_ADBIA0

DDR_A_CLK1_DP

VM_EDCA0_0

VM_A0_ADA<30>

VM_A0_ADA<26>

VM_A0_ADA<29>

VM_A0_ADA<27>

VM_A0_ADA<25>

VM_A0_ADA<16>

VM_A0_ADA<20>

VM_A0_ADA<7>

VM_A0_ADA<2>

VM_A0_ADA<0>

VM_A0_ADA<10>

VM_A0_ADA<9>

VM_A0_ADA<14>

VM_A0_ADA<15>

VM_A0_AA<7>

VM_A0_AA<6>

VM_A0_AA<5>

VM_WCKA0_0_DN

VM_WCKA0_1_DP

VM_WCKA0_1_DN

VM_EDCA0_3

VM_EDCA0_2

VM_EDCA0_1

VM_DDBIA0_1

DDR_A_CASA0#

DDR_A_CSA0#_0

VM_RESET

VM_A1_ADA<21>

VM_WCKA1_0_DP

19

VM_DDBIA1_2

VM_DDBIA1_3

DDR_A_CSA1#_0

DDR_A_WEA1#

VM_A0_AA<1>

VM_DDBIA1_0

VM_WCKA1_1_DP

VM_EDCA1_2

VM_RESET

VM_ADBIA1

VM_REFD2_A0

VM_REFDC_A0

VM_A0_ADA<18>

VM_A0_ADA<21>

VM_A0_ADA<17>

15

TITLE

DATE

CODE

SIZE

1

E

D

C

B

A

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

of

CHANGE by

8

REV

DOC.NUMBER

SHEET

2

INVENTEC

BI

VSS-B5

VSS-B10

VSS-D10

VSS-G5

VSS-G10

VSS-H1

VSS-H14

VSS-K1

VSS-K14

VSS-L5

VSS-L10

VSS-P10

VSS-T5

VSS-T10

SEN

VSSQ-V14

VSSQ-V12

VSSQ-V3

VSSQ-V1

VSSQ-R14

VSSQ-R12

VSSQ-R11

VSSQ-R4

VSSQ-R3

VSSQ-R1

VSSQ-N1

VSSQ-N14

VSSQ-N12

VSSQ-N3

VSSQ-M10

VSSQ-M5

VSSQ-K13

VSSQ-K2

VSSQ-H13

VSSQ-H2

VSSQ-F10

VSSQ-F5

VSSQ-E14

VSSQ-E12

VSSQ-E3

VSSQ-E1

VSSQ-C14

VSSQ-C12

VSSQ-C11

VSSQ-C4

VSSQ-C3

VSSQ-C1

VSSQ-A14

VSSQ-A12

VSSQ-A3

VSSQ-A1

ZQ

VREFC

VDD-R10

VDD-R5

VDD-P11

VDD-L14

VDDQ-T14

VDDQ-T12

VDDQ-T3

VDDQ-T1

VDDQ-P14

VDDQ-P12

VDDQ-P3

VDDQ-P1

VDDQ-N10

VDDQ-N5

VDDQ-M14

VDDQ-M12

VDDQ-M3

VDDQ-M1

Vpp,NC1

Vpp,NC

WCK23#|WCK01#

WCK23|WCK01

WCK01#|WCK23#

WCK01|WCK23

RFU/A12/NC

VREFD2

VREFD1

MF

VDD-L11

VDD-L4

VDDQ-L13

VDDQ-L2

VDDQ-K12

VDDQ-K3

VDDQ-H12

VDDQ-H3

WE#|CS#

VDD-L1

VDD-G14

VDD-G11

VDD-G4

VDD-G1

VDD-D11

VDD-C10

VDD-C5

VDDQ-G13

VDDQ-G2

VDDQ-F14

VDDQ-F12

VDDQ-E10

DBI3#|DBI0#

DBI2#|DBI1#

DBI1#|DBI2#

DBI0#|DBI3#

EDC3|EDC0

EDC2|EDC1

EDC1|EDC2

EDC0|EDC3

VDDQ-E5

VDDQ-D14

VDDQ-D12

VDDQ-D3

VDDQ-D1

VDDQ-B14

VDDQ-B12

VDDQ-B3

VDDQ-B1

A5/BA1|A3/BA3

CK#

CK

VDDQ-F1

A1/A9|A6/A11

CKE#

RESET#

A2/BA0|A4/BA2

RAS#|CAS#

A6/A11|A1/A9

A7/A8|A0/A10

A4/BA2|A2/BA0

A0/A10|A7/A8

A3/BA3|A5/BA1

CS#|WE#

CAS#|RAS#

DQ0|DQ24

DQ1|DQ25

DQ2|DQ26

DQ3|DQ27

DQ4|DQ28

DQ5|DQ29

DQ6|DQ30

DQ7|DQ31

DQ8|DQ16

DQ9|DQ17

DQ10|DQ18

DQ11|DQ19

DQ12|DQ20

DQ13|DQ21

DQ14|DQ22

DQ15|DQ23

DQ16|DQ8

DQ17|DQ9

DQ18|DQ10

DQ19|DQ11

DQ20|DQ12

DQ21|DQ13

DQ22|DQ14

DQ23|DQ15

DQ24|DQ0

DQ25|DQ1

DQ26|DQ2

DQ27|DQ3

DQ28|DQ4

DQ29|DQ5

DQ30|DQ6

DQ31|DQ7

ABI#

VDDQ-F3

BI

VSS-B5

VSS-B10

VSS-D10

VSS-G5

VSS-G10

VSS-H1

VSS-H14

VSS-K1

VSS-K14

VSS-L5

VSS-L10

VSS-P10

VSS-T5

VSS-T10

SEN

VSSQ-V14

VSSQ-V12

VSSQ-V3

VSSQ-V1

VSSQ-R14

VSSQ-R12

VSSQ-R11

VSSQ-R4

VSSQ-R3

VSSQ-R1

VSSQ-N1

VSSQ-N14

VSSQ-N12

VSSQ-N3

VSSQ-M10

VSSQ-M5

VSSQ-K13

VSSQ-K2

VSSQ-H13

VSSQ-H2

VSSQ-F10

VSSQ-F5

VSSQ-E14

VSSQ-E12

VSSQ-E3

VSSQ-E1

VSSQ-C14

VSSQ-C12

VSSQ-C11

VSSQ-C4

VSSQ-C3

VSSQ-C1

VSSQ-A14

VSSQ-A12

VSSQ-A3

VSSQ-A1

ZQ

VREFC

VDD-R10

VDD-R5

VDD-P11

VDD-L14

VDDQ-T14

VDDQ-T12

VDDQ-T3

VDDQ-T1

VDDQ-P14

VDDQ-P12

VDDQ-P3

VDDQ-P1

VDDQ-N10

VDDQ-N5

VDDQ-M14

VDDQ-M12

VDDQ-M3

VDDQ-M1

Vpp,NC1

Vpp,NC

WCK23#|WCK01#

WCK23|WCK01

WCK01#|WCK23#

WCK01|WCK23

RFU/A12/NC

VREFD2

VREFD1

MF

VDD-L11

VDD-L4

VDDQ-L13

VDDQ-L2

VDDQ-K12

VDDQ-K3

VDDQ-H12

VDDQ-H3

WE#|CS#

VDD-L1

VDD-G14

VDD-G11

VDD-G4

VDD-G1

VDD-D11

VDD-C10

VDD-C5

VDDQ-G13

VDDQ-G2

VDDQ-F14

VDDQ-F12

VDDQ-E10

DBI3#|DBI0#

DBI2#|DBI1#

DBI1#|DBI2#

DBI0#|DBI3#

EDC3|EDC0

EDC2|EDC1

EDC1|EDC2

EDC0|EDC3

VDDQ-E5

VDDQ-D14

VDDQ-D12

VDDQ-D3

VDDQ-D1

VDDQ-B14

VDDQ-B12

VDDQ-B3

VDDQ-B1

A5/BA1|A3/BA3

CK#

CK

VDDQ-F1

A1/A9|A6/A11

CKE#

RESET#

A2/BA0|A4/BA2

RAS#|CAS#

A6/A11|A1/A9

A7/A8|A0/A10

A4/BA2|A2/BA0

A0/A10|A7/A8

A3/BA3|A5/BA1

CS#|WE#

CAS#|RAS#

DQ0|DQ24

DQ1|DQ25

DQ2|DQ26

DQ3|DQ27

DQ4|DQ28

DQ5|DQ29

DQ6|DQ30

DQ7|DQ31

DQ8|DQ16

DQ9|DQ17

DQ10|DQ18

DQ11|DQ19

DQ12|DQ20

DQ13|DQ21

DQ14|DQ22

DQ15|DQ23

DQ16|DQ8

DQ17|DQ9

DQ18|DQ10

DQ19|DQ11

DQ20|DQ12

DQ21|DQ13

DQ22|DQ14

DQ23|DQ15

DQ24|DQ0

DQ25|DQ1

DQ26|DQ2

DQ27|DQ3

DQ28|DQ4

DQ29|DQ5

DQ30|DQ6

DQ31|DQ7

ABI#

VDDQ-F3

GDDR5

CHANNEL B MEMORY

9793

MODEL,PROJECT,FUNCTION

X01

XXX

1310xxxxx-0-0

21-OCT-2002

2

1

C5403

2

1

C5396

2

1

C5388

2

1

C5440

2

1

C5434

2

1

C5426

2

1

C5443

2

1

C5446

2

1

C5447

2

1

C5448

2

1

C5449

2

1

C5450

2

1

C5451

2

1

C5452

2

1

C5418

2

1

C5417

2

1

C5416

2

1

C5415

2

1

C5414

2

1

C5413

2

1

C5412

2

1

C5411

J13

L12

P4

P5

D4

D5

V3

V14

V12

V1

R4

R3

R14

R12

R11

R1

N3

N14

N12

N1

M5

M10

K2

K13

H2

H13

F5

F10

E3

E14

E12

E1

C4

C3

C14

C12

C11

C1

A3

A14

A12

A1

T5

T10

P10

L5

L10

K14

K1

H14

H1

G5

G10

D10

B5

B10

V10

A10

J14

V5

A5

T3

T14

T12

T1

P3

P14

P12

P1

N5

N10

M3

M14

M12

M1

L2

L13

K3

K12

H3

H12

G2

G13

F3

F14

F12

F1

E5

E10

D3

D14

D12

D1

B3

B14

B12

B1

R5

R10

P11

L4

L14

L11

L1

G4

G14

G11

G1

D11

C5

C10

J10

J5

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

B2

M2

M4

B4

N2

N4

T2

T4

V2

V4

M13

M11

N13

N11

A2

T13

T11

V13

V11

F13

F11

E13

E11

B13

B11

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

J4

K4

K5

K10

K11

H10

H11

H5

H4

U5077

2

1

R5432

2

1

R5428

J13

L12

P4

P5

D4

D5

V3

V14

V12

V1

R4

R3

R14

R12

R11

R1

N3

N14

N12

N1

M5

M10

K2

K13

H2

H13

F5

F10

E3

E14

E12

E1

C4

C3

C14

C12

C11

C1

A3

A14

A12

A1

T5

T10

P10

L5

L10

K14

K1

H14

H1

G5

G10

D10

B5

B10

V10

A10

J14

V5

A5

T3

T14

T12

T1

P3

P14

P12

P1

N5

N10

M3

M14

M12

M1

L2

L13

K3

K12

H3

H12

G2

G13

F3

F14

F12

F1

E5

E10

D3

D14

D12

D1

B3

B14

B12

B1

R5

R10

P11

L4

L14

L11

L1

G4

G14

G11

G1

D11

C5

C10

J10

J5

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

B2

M2

M4

B4

N2

N4

T2

T4

V2

V4

M13

M11

N13

N11

A2

T13

T11

V13

V11

F13

F11

E13

E11

B13

B11

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

J4

K4

K5

K10

K11

H10

H11

H5

H4

U5078

2

1

R5444

2

1

R5445

2

1

R5438

2

1

C5441

2

1

R5439

2

1

R5436

2

1

R5430

2

1

C5435

2

1

R5431

2

1

R5423

2

1

C5427

2

1

R5424

2

1

C5442

2

1

C5437

2

1

C5433

2

1

C5429

2

1

C5425

2

1

C5422

2

1

C5421

2

1

C5420

2

1

C5419

2

1

C5410

2

1

R5392

2

1

R5391

2

1

R5407

2

1

R5406

2

1

C5404

2

1

R5398

2

1

R5400

2

1

R5401

2

1

C5397

2

1

R5393

2

1

R5394

2

1

C5389

2

1

C5409

2

1

C5408

2

1

C5405

2

1

C5402

2

1

C5399

2

1

C5395

2

1

C5390

2

1

R5386

2

1

R5387

2

1

C5385

0.1UF_16V_2

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

1UF_6.3V_2

5.49K_1%_2

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

VM_WCKB0_1_DP

8

VM_B1_ADA<11>

VM_B1_ADA<0>

VM_B1_ADA<1>

P1V5_GPUS

VM_B1_ADA<5>

5

P1V5_GPUS

VM_B0_AA<1>

10UF_6.3V_3 2.37K_1%_2

1UF_6.3V_2 1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

0_5%_2_DY

1UF_6.3V_2

120_1%_2

0_5%_2

60.4_1%_2

5.49K_1%_2

1UF_6.3V_2

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

2.37K_1%_2

0_5%_2_DY

5.49K_1%_2

1UF_6.3V_2

2.37K_1%_2

0_5%_2

120_1%_2

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

60.4_1%_2

0.1UF_16V_2

1UF_6.3V_2_DY

P1V5_GPUS

P1V5_GPUS P1V5_GPUS

P1V5_GPUS P1V5_GPUS P1V5_GPUS P1V5_GPUS P1V5_GPUS

P1V5_GPUS

VM_B0_ADA<31>

VM_B0_ADA<15>

VM_B1_ADA<29>

20

VM_B0_ADA<20>

VM_B0_ADA<19>

VM_B0_ADA<22>

VM_B0_ADA<16>

VM_B0_ADA<9>

VM_RESET

VM_B0_ADA<10>

VM_B1_ADA<6>

VM_B0_ADA<27>

VM_B0_ADA<1>

VM_B0_ADA<0>

VM_B0_ADA<11>

VM_B1_ADA<26>

DDR_B_WEB1#

DDR_B_CSB1#_0

VM_RESET

VM_REFD1_B1

VM_REFD2_B1

VM_EDCB1_2

VM_DDBIB1_0

VM_DDBIB1_3

DDR_B_CLK1_DP

VM_B1_ADA<31..0>

2

DDR_B_CLK1_DN

VM_B1_ADA<17>

VM_REFD1_B0

VM_REFDC_B0

VM_ADBIB0

VM_REFD2_B0

VM_WCKB0_0_DP

VM_B0_ADA<14>

VM_B1_ADA<18>

VM_B1_ADA<16>

VM_B1_AA<8>

VM_B1_AA<7..0>

5

7

VM_B0_AA<3>

VM_B0_AA<2>

VM_B0_AA<7..0>

VM_B0_AA<8>

VM_B0_AA<5>

VM_B0_AA<4>

VM_B1_ADA<21>

VM_REFDC_B1

VM_ADBIB1

DDR_B_CKEB1

DDR_B_CASB1#

DDR_B_RASB1#

VM_DDBIB1_1

VM_DDBIB1_2

VM_EDCB1_3

VM_EDCB1_1

VM_EDCB1_0

VM_WCKB1_1_DN

VM_WCKB1_0_DP

VM_WCKB1_0_DN

VM_B0_AA<0>

VM_WCKB0_0_DN VM_WCKB1_1_DP

VM_B1_ADA<22>

DDR_B_WEB0#

DDR_B_CSB0#_0

DDR_A_CKEB0

DDR_B_CASB0#

DDR_B_RASB0#

DDR_B_CLK0_DN

DDR_B_CLK0_DP

VM_DDBIB0_0

VM_DDBIB0_1

VM_DDBIB0_3

VM_DDBIB0_2

VM_EDCB0_3

VM_EDCB0_2

VM_EDCB0_0

VM_EDCB0_1

VM_WCKB0_1_DN

1

VM_B0_AA<6>

VM_B0_AA<7>

VM_B0_ADA<13>

13

Everest Main Board

BEN LEE

1

A01

Block Diagram

February 22, 2010

1

CS

C

CS_1310AXXXXXX-MTR

29

26

27

22

18

21

5

6

2

1

11

8

9

10

15

14

12

28

VM_B0_ADA<31..0>

16

31

24

23

17

25

0

2

4

6

3

19

6

7

3

0

9

15

14

12

28

27

25

30

26

17

16

23

21

18

22

19

7

6

4

3

2

1

0

31

24

1

30

4

0

3

7

VM_B0_ADA<8>

VM_B0_ADA<12>

VM_B0_ADA<30>

VM_B0_ADA<29>

VM_B0_ADA<28>

VM_B0_ADA<24>

VM_B0_ADA<25>

VM_B0_ADA<17>

VM_B0_ADA<23>

VM_B0_ADA<18>

VM_B0_ADA<21>

VM_B0_ADA<5>

VM_B0_ADA<6>

VM_B0_ADA<4>

VM_B0_ADA<7>

VM_B0_ADA<3>

VM_B0_ADA<2>

4

VM_B0_ADA<26>

11

10

20

13

VM_B1_ADA<4>

VM_B1_ADA<7>

VM_B1_ADA<24>

VM_B1_ADA<31>

VM_B1_ADA<15>

VM_B1_ADA<13>

VM_B1_ADA<14>

VM_B1_ADA<12>

VM_B1_ADA<9>

VM_B1_ADA<8>

VM_B1_ADA<10>

VM_B1_ADA<2>

VM_B1_ADA<3>

VM_B1_ADA<23>

VM_B1_ADA<30>

VM_B1_ADA<25>

VM_B1_ADA<28>

VM_B1_ADA<27>

29

VM_B1_ADA<19>

VM_B1_ADA<20>

5

VM_B1_AA<7>

VM_B1_AA<5>

VM_B1_AA<2>

VM_B1_AA<0>

VM_B1_AA<1>

VM_B1_AA<4>

VM_B1_AA<6>

VM_B1_AA<3>

TITLE

DATE

CODE

SIZE

1

E

D

C

B

A

7 6 5 4 3 2

1

7 6 5 4 3

E

D

C

B

A

FF

8

of

CHANGE by

8

REV

DOC.NUMBER

SHEET

2

INVENTEC

BI

VSS-B5

VSS-B10

VSS-D10

VSS-G5

VSS-G10

VSS-H1

VSS-H14

VSS-K1

VSS-K14

VSS-L5

VSS-L10

VSS-P10

VSS-T5

VSS-T10

SEN

VSSQ-V14

VSSQ-V12

VSSQ-V3

VSSQ-V1

VSSQ-R14

VSSQ-R12

VSSQ-R11

VSSQ-R4

VSSQ-R3

VSSQ-R1

VSSQ-N1

VSSQ-N14

VSSQ-N12

VSSQ-N3

VSSQ-M10

VSSQ-M5

VSSQ-K13

VSSQ-K2

VSSQ-H13

VSSQ-H2

VSSQ-F10

VSSQ-F5

VSSQ-E14

VSSQ-E12

VSSQ-E3

VSSQ-E1

VSSQ-C14

VSSQ-C12

VSSQ-C11

VSSQ-C4

VSSQ-C3

VSSQ-C1

VSSQ-A14

VSSQ-A12

VSSQ-A3

VSSQ-A1

ZQ

VREFC

VDD-R10

VDD-R5

VDD-P11

VDD-L14

VDDQ-T14

VDDQ-T12

VDDQ-T3

VDDQ-T1

VDDQ-P14

VDDQ-P12

VDDQ-P3

VDDQ-P1

VDDQ-N10

VDDQ-N5

VDDQ-M14

VDDQ-M12

VDDQ-M3

VDDQ-M1

Vpp,NC1

Vpp,NC

WCK23#|WCK01#

WCK23|WCK01

WCK01#|WCK23#

WCK01|WCK23

RFU/A12/NC

VREFD2

VREFD1

MF

VDD-L11

VDD-L4

VDDQ-L13

VDDQ-L2

VDDQ-K12

VDDQ-K3

VDDQ-H12

VDDQ-H3

WE#|CS#

VDD-L1

VDD-G14

VDD-G11

VDD-G4

VDD-G1

VDD-D11

VDD-C10

VDD-C5

VDDQ-G13

VDDQ-G2

VDDQ-F14

VDDQ-F12

VDDQ-E10

DBI3#|DBI0#

DBI2#|DBI1#

DBI1#|DBI2#

DBI0#|DBI3#

EDC3|EDC0

EDC2|EDC1

EDC1|EDC2

EDC0|EDC3

VDDQ-E5

VDDQ-D14

VDDQ-D12

VDDQ-D3

VDDQ-D1

VDDQ-B14

VDDQ-B12

VDDQ-B3

VDDQ-B1

A5/BA1|A3/BA3

CK#

CK

VDDQ-F1

A1/A9|A6/A11

CKE#

RESET#

A2/BA0|A4/BA2

RAS#|CAS#

A6/A11|A1/A9

A7/A8|A0/A10

A4/BA2|A2/BA0

A0/A10|A7/A8

A3/BA3|A5/BA1

CS#|WE#

CAS#|RAS#

DQ0|DQ24

DQ1|DQ25

DQ2|DQ26

DQ3|DQ27

DQ4|DQ28

DQ5|DQ29

DQ6|DQ30

DQ7|DQ31

DQ8|DQ16

DQ9|DQ17

DQ10|DQ18

DQ11|DQ19

DQ12|DQ20

DQ13|DQ21

DQ14|DQ22

DQ15|DQ23

DQ16|DQ8

DQ17|DQ9

DQ18|DQ10

DQ19|DQ11

DQ20|DQ12

DQ21|DQ13

DQ22|DQ14

DQ23|DQ15

DQ24|DQ0

DQ25|DQ1

DQ26|DQ2

DQ27|DQ3

DQ28|DQ4

DQ29|DQ5

DQ30|DQ6

DQ31|DQ7

ABI#

VDDQ-F3

BI

VSS-B5

VSS-B10

VSS-D10

VSS-G5

VSS-G10

VSS-H1

VSS-H14

VSS-K1

VSS-K14

VSS-L5

VSS-L10

VSS-P10

VSS-T5

VSS-T10

SEN

VSSQ-V14

VSSQ-V12

VSSQ-V3

VSSQ-V1

VSSQ-R14

VSSQ-R12

VSSQ-R11

VSSQ-R4

VSSQ-R3

VSSQ-R1

VSSQ-N1

VSSQ-N14

VSSQ-N12

VSSQ-N3

VSSQ-M10

VSSQ-M5

VSSQ-K13

VSSQ-K2

VSSQ-H13

VSSQ-H2

VSSQ-F10

VSSQ-F5

VSSQ-E14

VSSQ-E12

VSSQ-E3

VSSQ-E1

VSSQ-C14

VSSQ-C12

VSSQ-C11

VSSQ-C4

VSSQ-C3

VSSQ-C1

VSSQ-A14

VSSQ-A12

VSSQ-A3

VSSQ-A1

ZQ

VREFC

VDD-R10

VDD-R5

VDD-P11

VDD-L14

VDDQ-T14

VDDQ-T12

VDDQ-T3

VDDQ-T1

VDDQ-P14

VDDQ-P12

VDDQ-P3

VDDQ-P1

VDDQ-N10

VDDQ-N5

VDDQ-M14

VDDQ-M12

VDDQ-M3

VDDQ-M1

Vpp,NC1

Vpp,NC

WCK23#|WCK01#

WCK23|WCK01

WCK01#|WCK23#

WCK01|WCK23

RFU/A12/NC

VREFD2

VREFD1

MF

VDD-L11

VDD-L4

VDDQ-L13

VDDQ-L2

VDDQ-K12

VDDQ-K3

VDDQ-H12

VDDQ-H3

WE#|CS#

VDD-L1

VDD-G14

VDD-G11

VDD-G4

VDD-G1

VDD-D11

VDD-C10

VDD-C5

VDDQ-G13

VDDQ-G2

VDDQ-F14

VDDQ-F12

VDDQ-E10

DBI3#|DBI0#

DBI2#|DBI1#

DBI1#|DBI2#

DBI0#|DBI3#

EDC3|EDC0

EDC2|EDC1

EDC1|EDC2

EDC0|EDC3

VDDQ-E5

VDDQ-D14

VDDQ-D12

VDDQ-D3

VDDQ-D1

VDDQ-B14

VDDQ-B12

VDDQ-B3

VDDQ-B1

A5/BA1|A3/BA3

CK#

CK

VDDQ-F1

A1/A9|A6/A11

CKE#

RESET#

A2/BA0|A4/BA2

RAS#|CAS#

A6/A11|A1/A9

A7/A8|A0/A10

A4/BA2|A2/BA0

A0/A10|A7/A8

A3/BA3|A5/BA1

CS#|WE#

CAS#|RAS#

DQ0|DQ24

DQ1|DQ25

DQ2|DQ26

DQ3|DQ27

DQ4|DQ28

DQ5|DQ29

DQ6|DQ30

DQ7|DQ31

DQ8|DQ16

DQ9|DQ17

DQ10|DQ18

DQ11|DQ19

DQ12|DQ20

DQ13|DQ21

DQ14|DQ22

DQ15|DQ23

DQ16|DQ8

DQ17|DQ9

DQ18|DQ10

DQ19|DQ11

DQ20|DQ12

DQ21|DQ13

DQ22|DQ14

DQ23|DQ15

DQ24|DQ0

DQ25|DQ1

DQ26|DQ2

DQ27|DQ3

DQ28|DQ4

DQ29|DQ5

DQ30|DQ6

DQ31|DQ7

ABI#

VDDQ-F3

BI

0.12A

NEED A GPIO PIN

TRUTH TABLE (SEL CONTROL)

PORT A IS ACTIVE

PORT B IS ACTIVE

Unplug Cable

GPU_HDMI_HPD1

Plug Cable

L

H

Plug Cable

L

H

L

GPU_HDMI_HPDET

H

FUNCTION

H

Unplug Cable

Plug Cable

Unplug Cable

GPU_EDP_HPD

Unplug Cable

L

Plug Cable

L

H

L

DGPU_HPD_INTR#_R

PCH-COUGARPOINT: Pin H36 (TACH2/GPIO6)

L

Unplug Cable

EDP_HPD#_CN

Plug Cable

DGPU_HPD_INTR#_R

Plug Cable

0.12A

H

Unplug Cable

PCH-COUGARPOINT: Pin H36 (TACH2/GPIO6)

(GPU)

(CPU)

SEL /HPD_SEL/AUX_SEL

EDP_TX1_DP

EDP_TX1_DN

EDP_TX0_DN

EDP_TX0_DP

EDP_AUX_DP

EDP_AUX_DN

EDP_MUX_IC_SEL

0.1UF_16V_2

EC_EDP_MUX_IC_SEL

94 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

10K_5%_2

SSM3K7002BFU

P3V3_S

CPU_EDP_AUX_DN

CPU_EDP_TX1_DP

CPU_EDP_TX1_DN

GPU_EDP_TX0_DN

GPU_EDP_TX1_DN

CPU_EDP_AUX_DP

PER_PI3VEDP212ZLEX_TQFN_32P

GPU_EDP_AUX_DP

GPU_EDP_AUX_DN

2

1

3

Q5098

2

1

R5509

2

1

C5507

2

3

1

Q5512

2

1

3

Q5103

2

1

R5514

2

1

R5511

2

1

R5510

2

1

3

Q5100

2

1

R5099

2

1

R5096

2

1

R5095

2

3

1

Q5097

2

1

C5515

2

1

C5513

2

1

C5508

2

1

C5102

29

10

13

17

8

21

22

26

5

27

24

30

2

25

1

14

18

7

15

19

6

9

4

33 32

31

3

28

23

20

1612

11

U5101

P3V3_GPUS

MMBT3904

P3V3_GPUS

P3V3_S

0_5%_2

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

10K_5%_2

150K_5%_2

SSM3K7002BFU

0_5%_2

10K_5%_2

150K_5%_2

SSM3K7002BFU

MMBT3904

0.1UF_16V_2

GPU_EDP_TX0_DP

CPU_EDP_TX0_DN

EDP_MUX_IC_SEL

CPU_EDP_TX0_DP

GPU_EDP_TX1_DP

11

February 22, 2010

BEN LEE

A01

Block Diagram

Everest Main Board

CS_1310AXXXXXX-MTR

CS

C

DGPU_HPD_INTR#_R

GPU_EDP_HPD

DGPU_HPD_INTR#_R

GPU_HDMI_HPDETEDP_HPD#_CN

GPU_HDMI_HPD1

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

BI

IN

G

DS

B

CE

IN

G

DS

OUT

G

DS

IN

OUT

B

CE

BI

VDD

SEL

HPD_B

HPD_A

HPD

GND

D1-B

D1-A

D1-

D1+A

D0-B

D0-A

D0-

D0+B

D0+

AUX-B

AUX-A

AUX-

AUX+B

AUX+A

AUX+

VDD

D1+

GND

AUX_SEL

D0+A

VDD

GND

D1+B

VDD

HPD_SEL

+PWR_AUD

+PVDD2

+PWR_AUD

+PVDD2

+PVDD1

CLOSE TO CODEC PIN12

+PVDD1

CLOSE TO CODEC

+PWR_AUD

CLOSE TO CODEC

CLOSE TO CODEC PIN19

CLOSE TO CODEC

CLOSE TO CODEC PIN46

CLOSE TO CODEC PIN39

95 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

1

31

SPK_OUT_L-

2

C518

4.7UF_6.3V_3

R502

2

2.2K_1%_2

FBMA_11_160808_151A20T

L503

1

10UF_6.3V_3

1

C504

20K_1%_2

39.2K_1%_2

R513

2

R512

1

2

1

20K_1%_2

1

R511

2

1K_1%_2

22

10UF_6.3V_3

C516

0.1UF_16V_2

2

2.2UF_10V_3

24

0.1UF_16V_2

39

0.1UF_16V_2

BAT54_30V_0.2A

FBMA_11_160808_151A20T

2

1

L501

C502

dgnd

POWER

1

10UF_6.3V_3

POWER

C505

0.1UF_16V_2

2

dgnd

C503

2

1

0.1UF_16V_2

C501

0.1UF_16V_2

1

2

1

10UF_6.3V_3

2.2K_1%_2

10UF_6.3V_3

C512

1

27

23

48

47

44

45

17

1

49

7

15

5

4

3

46

41

2

22

21

28

37

6

13

33

32

14

36

35

34

26

25

38

42

18

19

20

2

1

R504

1

R501

1

2

1

C517

4.7UF_6.3V_3

1

2

dgnd

2

C511

2

C510

2.2UF_10V_3

1

2

dgnd

1

2

1

2

1

POWER

MIC_R

HP_R

HP_L

MIC_L

11

February 22, 2010

A01

Everest Main Board

C

CS_1310AXXXXXX-MTR

CS

BEN LEE

2

1

VARISTOR_DY

D503D502

1

2

dgnd

C521

11

C520

22

C519

1

2

4.7K_5%_2

R515

2

1

47K_5%_2

R514

PCSPKR_PCH_3

0.01UF_50V_2

dgnd

Block Diagram

2

VARISTOR_DY

dgnd

2

C522

D501

3

POWER

C523

2

1

L502

2

1

dgnd

1

10UF_6.3V_3

2

FBMA_11_160808_151A20T

R503

2

29

30

C508

10UF_6.3V_3

C509

0.1UF_16V_2

2

3

D505

1

2

3

R506

2

1

2

AMP_PD#

EC_MUTE#

HDA_3S_RST#

1

D504

0_5%_2

1

R507

1K_5%_2

BAT54_30V_0.2A

dgnd

POWER

MIC1_VREFO_L

1

C515

1

11

MIC1_VREFO_R MIC1_VREFO_R

MIC1_VREFO_L

2

C506

C507

10UF_6.3V_3

SPK_OUT_L+

R510

P3V3_S

1

0_5%_2

1

dgnd

2

22PF_50V_2

12

8

9

10

11

dgnd

22_5%_2

R509

2

R505

2

1

22_5%_2

AMP_PD#

MIC_IN_CLK

MIC_IN_DATA

HDA_3S_SDOUT

HDA_3S_RST#

HDA_3S_SYNC

SPK_OUT_R+

SPK_OUT_R-

10UF_6.3V_3

1

HDA_3S_BITCLK

HDA_3S_SDIN0

R508

2

1

0_5%_2

0.1UF_16V_2

P3V3_S

16

P5V_S

HPS

MICS

dgnd

2

C500

0.1UF_16V_2

P5V_S

C513

C514

POWER

U500

40

43

C520

REA_ALC269Q_VB6_GR_QFN_48P

2.2UF_10V_3

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

NC

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

NC

GND

SPDIFO

EAPD

PVDD2

SPK-R+

SPK-R-

PVSS2

PVSS1

SPK-L-

SPK-L+

PVDD1

AVDD2

AVSS2

CBP

CBN

CPVEE

HP-OUT-R

HP-OUT-L

MIC1-VREFO-L

MIC1-VREFO-R

MIC2-VREFO

LDO-CAP

VREF

AVSS1

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

SENSE-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

SENSE-A

PCBEEP

RESET#

SYNC

DVDD-IO

SDATA-IN

DVSS2

BIT-CLK

SDATA-OUT

PD#

GPIO1-DMIC-CLK

GIO0-DMIC-DATA

DVDD1

96 97

XXX

21-OCT-2002

MODEL,PROJECT,FUNCTION

1310xxxxx-0-0

X01

600OHM_25%

SINGA_2SJ_T351_019_6P

HPS

HP_R

HP_L

R603

75_5%_2

2

1

R604

75_5%_2

1

2

1

L603

2

L604

600OHM_25%

1

2

1

2

D603

VARISTOR_DY

1

2

D604

VARISTOR_DY

1

2

D605

VARISTOR_DY

C605

100PF_50V_2

2

1

C606

2

1

100PF_50V_2

100PF_50V_2_DY

1

2

C607

JACK601

4

5

1

2

3

G2

G1

6

D600

PHP_PESD5V2S2UT_SOT23_3P

2

1

3

G1

SPK_OUT_R-

SPK_OUT_R+

SPK_OUT_L-

SPK_OUT_L+

SPK_OUT_L-_R

SPK_OUT_R-_R

SPK_OUT_L+_R

SPK_OUT_R+_R

R606

0_5%_3

R607

0_5%_3

R608

0_5%_3

R605

0_5%_3

2

1

C608

1000PF_50V_2_DY

C610

2

1

2

C611

1000PF_50V_2_DY

1

2

C609

ACES_50224_0040N_001_4P

CN600

1

3

4

G2

2

MICS

MIC_R

MIC_L

L601

2

600OHM_25%

1

L602

600OHM_25%

1

2

1

D601

VARISTOR_DY

2

1

D602

VARISTOR_DY

1

100PF_50V_2

2

C603

C604

2

100PF_50V_2

1

JACK600

G1

G2

SINGA_2SJ_T351_019_6P

1

3

4

5

6

2

A01

C

CS

CS_1310AXXXXXX-MTR

Everest Main Board

Block Diagram

BEN LEE

February 22, 2010

1 1

REV

INVENTEC

3 2

CHANGE by

TITLE

SHEET

of

1

4

A A

B B

C C

DD

1

23

45

56

67

78

8

CODE

SIZE

DATE

DOC.NUMBER

OUT

IN

G1

1

2

3

4

G2

IN

OUT

IN

1.5A

VRAM

97

Fri Dec 31 10:16:55 2010

EVEREST-M

Frank Hu

2

1

R5511

2

1

R5510

2

1

R5509

2

1

R5512

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5507

2

1

C5517

2

1

C5516

2

1

C5515

2

1

C5514

2

1

C5513

2

1

C5512

2

1

C5511

2

1

R5508

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

T9

T1

P9

P1

M9

M1

J8

J2

G8

E1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

M7

T7

T3

N7

R7

L7

P7

N3

U5506

2

1

C5510

2

1

C5509

2

1

C5508

2

1

C5507

2

1

R5513

2

1

C5506

2

1

C5505

2

1

C5504

CS_1310AXXXXXX-MTR

10K_5%_2

FBC_CLK1_DP

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

10K_5%_2

P1V5_GPUS

10K_5%_2

243_1%_2

FBC_CLK1_DP

76<

FBC_DQS_DP<4>

FBC_DQS_DP<6>

FBC_D<40..47>

69<>

FBC_CLK1_DN

FBC_DQM<6>

FBC_DQS_DN<4>

FBC_CMD<21>

FBC_CMD<8>

FBC_CMD<13>

13

FBC_CMD<24>

160_1%_2

FBC_DQS_DN<6>

FBC_CMD<28>

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

FBC_DQM<5>

FBC_CMD<11>

FBC_CMD<8>

FBC_CMD<21>

FBC_DQM<7>

FBC_DQS_DP<5>

FBC_DQS_DP<7>

FBC_DQS_DN<7>

FBC_CMD<28>

FBC_DQS_DN<5>

FBC_CMD<16>

FBC_CMD<27>

FBC_CMD<14>

FBC_CMD<12>

FBC_CMD<30>

FBC_CMD<29>

FBC_CMD<7>

FBC_CMD<18>

FBC_CMD<13>

FBC_CMD<10>

FBC_CMD<26>

FBC_CMD<1>

FBC_CMD<5>

FBC_CMD<19>

FBC_CLK1_DN

FBC_CLK1_DP

FBC_D<47>

FBC_D<42>

FBC_D<41>

FBC_D<44>

FBC_D<45>

FBC_D<40>

FBC_D(43)

FBC_D<46>

FBC_D<58>

FBC_D<60>

FBC_D<59>

FBC_D<62>

FBC_D<57>

FBC_D<61>

FBC_D<56>

FBC_D<63>

FBC_CMD<3>

FBC_CMD<30..0>

FBC_CMD<20>

FBC_CMD<4>

FBC_CMD<9>

FBC_CMD<6>

FBC_CMD<17>

FBC_CMD<22>

FBC_VREF1 FBC_D<56..63>

FBC_CMD<16>

FBC_CLK1_DN

FBC_CMD<0>

FBC_CMD<27>

FBC_CMD<24>

FBC_CMD<16>

FBC_D<52>

FBC_D<48>

FBC_D<55>

FBC_D<51>

FBC_D<54>

FBC_D<50>

FBC_D<53>

FBC_D<49>

FBC_D<36>

FBC_D<33>

FBC_D<37>

FBC_D<32>

FBC_D<38>

FBC_D<34>

FBC_D<39>

FBC_D<35>

FBC_DQM<4>

FBC_CMD<11>

FBC_CMD<27>

FBC_CMD<30>

FBC_CMD<14>

FBC_CMD<12>

FBC_CMD<5>

FBC_CMD<1>

FBC_CMD<26>

FBC_CMD<3>

FBC_CMD<17>

FBC_CMD<6>

FBC_CMD<9>

FBC_CMD<20>

FBC_CMD<18>

FBC_CMD<29>

FBC_CMD<7>

FBC_CMD<10>

FBC_CMD<19>

FBC_CMD<4>

FBC_CMD<22>

FBC_CMD<30..0>

FBC_VREF1

FBC_D<48..55>

FBC_D<32..39>

0.1UF_16V_2 0.1UF_16V_2

P1V5_GPUS

243_1%_2

11

24

8

21

69>

75<>76<>

75<

76<

16

27

14

12

30

29

7

18

13

10

26

1

5

19

69>

76<

69>

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 1uF_6.3V_2 1uF_6.3V_2

47

42

41

44

45

40

43

46

P1V5_GPUS

3

20

4

9

6

17

22

76< 75<

58

60

59

62

57

61

56

63

69<>

75<>

69>

76<>

69>76<

69>

75<>76<>

76<> 75<>

69>

0.1UF_16V_2 0.1UF_16V_2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

69>76<

69<

69>

21

8

24

11

16

27

30

14

12

18

69>

76< 69>

1uF_6.3V_2 1uF_6.3V_2

P1V5_GPUS

29

7

10

19

5

1

26

3

17

6

9

20

4

22

76< 75<

51

54

55

48

52

50

49

53

69<>

36

32

38

37

33

34

39

35

69<>

C

A01

CS

SIZE

CHANGE by DATE

8

8 7

7 6

6 5

5 4

4 3

3

2

1

D

CC

BB

AA

REV

1

SHEET

2

DOC.NUMBER

of

CODE

INVENTEC

TITLE

BI

IN

BI

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

IN

BI

IN

BI

IN

BI

IN

ZQ

WE#

VSSQ#G9

VSSQ#G1

VSSQ#F9

VSSQ#E8

VSSQ#E2

VSSQ#D8

VSSQ#D1

VSSQ#B9

VSSQ#B1

VSS#T9

VSS#T1

VSS#P9

VSS#P1

VSS#M9

VSS#M1

VSS#J8

VSS#J2

VSS#G8

VSS#E1

VSS#B3

VSS#A9

VREFDQ

VREFCA

VDDQ#H9

VDDQ#H2

VDDQ#F1

VDDQ#E9

VDDQ#D2

VDDQ#C9

VDDQ#C1

VDDQ#A8

VDDQ#A1

VDD#R9

VDD#R1

VDD#N9

VDD#N1

VDD#K8

VDD#K2

VDD#G7

VDD#D9

VDD#B2

RESET#

RAS#

ODT

NC#L9

NC#L1

NC#J9

NC#J1

DQU7

DQU6

DQU5

DQU4

DQU3

DQU2

DQU1

DQU0

DQSU#

DQSU

DQSL#

DQSL

DQL7

DQL6

DQL5

DQL4

DQL3

DQL2

DQL1

DQL0

DMU

DML

CS#

CKE

CK#

CK

CAS#

BA2

BA1

BA0

A9

A8

A7

A6

A5

A4

A3

A2

A15

A14

A13

A12_BC#

A11

A10_AP

A1

A0

BI

IN

BI

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