DsPIC33/PIC24 Family Reference Manual, Liquid Crystal Display (LCD) Lcd Manual

• Liquid Crystal Display (LCD)
  • Highlights
  • 1.0 Introduction
    • Figure 1-1: LCD Driver Module Block Diagram
  • 2.0 LCD Registers
    • Register 2-1: LCDCON: LCD Control Register
    • Register 2-2: LCDPS: LCD Phase Register
  • 3.0 LCD Segment Pins Configuration
    • Table 3-1: LCDSEx Registers and Associated Segments
    • Register 3-1: LCDSEx: LCD Segment x Enable Register
    • Register 3-2: LCDDATAx: LCD Data x Register
    • Table 3-2: LCDDATAx Registers and Bits for Segment and COM Combinations
  • 4.0 LCD Clock Source Selection
    • 4.1 LCD Prescaler
      • Figure 4-1: LCD Clock Generation
  • 5.0 LCD Bias Types
    • 5.1 Internal Resistor Biasing
      • Table 5-1: Internal Resistance Ladder Power Modes
      • Figure 5-1: LCD Bias Internal Resistor Ladder Connection Diagram
      • 5.1.1 Automatic Power Mode Switching
        • Figure 5-2: LCD Reference Ladder Power Mode Switching Diagram
      • 5.1.2 Contrast Control
        • Figure 5-3: Internal Reference and Contrast Control Block Diagram
      • 5.1.3 Internal Reference
      • 5.1.4 VLCDxPE Pins
        • Register 5-1: LCDREF: LCD Reference Ladder Control Register
    • 5.2 LCD Bias Generation
      • 5.2.1 LCD BIAS TYPES
      • 5.2.2 LCD VOLTAGE REGULATOR
        • Register 5-2: LCDREG: LCD Voltage Regulator Control Register
    • 5.3 Bias Configurations
      • 5.3.1 M0 (Regulator with Boost)
      • 5.3.2 M1 (Regulator without Boost)
        • Figure 5-4: LCD Regulator Connections for M0 and M1 Configurations
      • 5.3.3 M2 (Resistor Ladder with Software Contrast)
        • Figure 5-5: Resistor Ladder Connections for M2 Configuration
      • 5.3.4 M3 (Resistor Ladder with Hardware Contrast)
        • Figure 5-6: Resistor Ladder Connections for M3 Configuration
    • 5.4 Design Considerations for the LCD Charge Pump
      • Equation 5-1:
  • 6.0 LCD Multiplex Types
    • Table 6-1: COM<7:0> Pin Function
  • 7.0 Segment Enables
  • 8.0 Pixel Control
  • 9.0 LCD Frame Frequency
    • Table 9-1: Frame Frequency Formulas
  • 10.0 LCD Waveform Generation
    • Figure 10-1: Type-A/Type-B Waveforms in Static Drive
    • Figure 10-2: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
    • Figure 10-3: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
    • Figure 10-4: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
    • Figure 10-5: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
    • Figure 10-6: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
    • Figure 10-7: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
    • Figure 10-8: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
    • Figure 10-9: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
    • Figure 10-10: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
    • Figure 10-11: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
    • Figure 10-12: Type-A Waveforms in 1/8 MUX, 1/3 Bias Drive
    • Figure 10-13: Type-B Waveforms in 1/8 MUX, 1/3 Bias Drive
  • 11.0 LCD Interrupts
    • Figure 11-1: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive
  • 12.0 Configuring the LCD Module
  • 13.0 Operation During Sleep
    • Figure 13-1: Sleep Entry/Exit when SLPEN = 1 or CS<1:0> = 00
  • 14.0 Registers
    • Table 14-1: Special Function Registers Associated with LCD Driver Module
  • 15.0 Revision History
    • Revision A (December 2010)
    • Revision B (October 2013)
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