LPC43xx_LPC43Sxx User Manual Lpc43xx
User Manual:
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- Chapter 1: Introductory information
- Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and Inter-Process Communication (IPC)
- Chapter 3: LPC43xx/LPC43Sxx Memory mapping
- Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) memory and API
- Chapter 5: LPC43xx Boot ROM
- Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP
- 6.1 How to read this chapter
- 6.2 Basic configuration
- 6.3 Features
- 6.4 General description
- 6.5 Sector numbers
- 6.6 Code Read Protection (CRP)
- 6.7 ISP commands
- 6.7.1 Unlock <Unlock code>
- 6.7.2 Set Baud Rate <Baud Rate> <stop bit>
- 6.7.3 Echo <setting>
- 6.7.4 Write to RAM <start address> <number of bytes>
- 6.7.5 Read Memory <address> <no. of bytes>
- 6.7.6 Prepare sectors for write operation <start sector number> <end sector number> <flash bank>
- 6.7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes>
- 6.7.8 Go <address> <mode>
- 6.7.9 Erase sectors <start sector number> <end sector number> <flash bank>
- 6.7.10 Blank check sectors <sector number> <end sector number> <flash bank>
- 6.7.11 Read Part Identification number
- 6.7.12 Read Boot Code version number
- 6.7.13 Read device unique ID
- 6.7.14 Compare <address1> <address2> <no of bytes>
- 6.7.15 Set active boot flash bank <flash bank>
- 6.8 IAP commands
- 6.8.1 IAP Initialization
- 6.8.2 Prepare sectors for write operation
- 6.8.3 Copy RAM to Flash
- 6.8.4 Erase Sectors
- 6.8.5 Blank check sectors
- 6.8.6 Read part identification number
- 6.8.7 Read Boot Code version number
- 6.8.8 Read device unique ID
- 6.8.9 Compare <address1> <address2> <no of bytes>
- 6.8.10 Re-invoke ISP
- 6.8.11 Erase page
- 6.8.12 Set active boot flash bank
- 6.9 ISP/IAP Status Codes
- 6.10 JTAG flash programming interface
- 6.11 Flash signature generation
- Signature generation
- Content verification
- Chapter 7: LPC43Sxx Boot ROM for secure parts
- Chapter 8: LPC43Sxx Security API
- Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller (NVIC)
- Chapter 10: LPC43xx/LPC43Sxx Event router
- Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)
- 11.1 How to read this chapter
- 11.2 Basic configuration
- 11.3 Features
- 11.4 Register description
- 11.4.1 CREG0 control register
- 11.4.2 CREG1 control register
- 11.4.3 ARM Cortex-M4 memory mapping register
- 11.4.4 CREG5 control register
- 11.4.5 DMA mux control register
- 11.4.6 Flash Accelerator Configuration register for flash bank A
- 11.4.7 Flash Accelerator Configuration register for flash bank B
- 11.4.8 ETB SRAM configuration register
- 11.4.9 CREG6 control register
- 11.4.10 Cortex-M4 TXEV event clear register
- 11.4.11 Chip ID register
- 11.4.12 ARM Cortex-M0SUB memory mapping register
- 11.4.13 Cortex-M0SUB TXEV event clear register
- 11.4.14 Cortex-M0APP TXEV event clear register
- 11.4.15 ARM Cortex-M0APP memory mapping register
- 11.4.16 USB0 frame length adjust register
- 11.4.17 USB1 frame length adjust register
- Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC)
- Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
- 13.1 How to read this chapter
- 13.2 Basic configuration
- 13.3 Features
- 13.4 General description
- 13.5 Pin description
- 13.6 Register description
- 13.6.1 Frequency monitor register
- 13.6.2 Crystal oscillator control register
- 13.6.3 PLL0USB registers
- 13.6.4 PLL0AUDIO registers
- 13.6.5 PLL1 registers
- 13.6.6 Integer divider register A
- 13.6.7 Integer divider register B, C, D
- 13.6.8 Integer divider register E
- 13.6.9 BASE_SAFE_CLK control register
- 13.6.10 BASE_USB0_CLK control register
- 13.6.11 BASE_PERIPH_CLK control register
- 13.6.12 BASE_USB1_CLK control register
- 13.6.13 BASE_M4_CLK to BASE_UART3_CLKcontrol registers
- 13.6.14 BASE_OUT_CLK register
- 13.6.15 BASE_AUDIO_CLK register
- 13.6.16 BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK register
- 13.7 Functional description
- 13.7.1 32 kHz oscillator
- 13.7.2 IRC
- 13.7.3 Crystal oscillator
- 13.7.4 PLL0 (PLL0USB and PLL0AUDIO)
- 13.7.4.1 Features
- 13.7.4.2 PLL0 description
- 13.7.4.3 Use of PLL0 operating modes
- 13.7.4.3.1 Normal Mode
- 13.7.4.3.2 Mode 1a: Normal operating mode without post-divider and without pre-divider
- 13.7.4.3.3 Mode 1b: Normal operating mode with post-divider and without pre-divider
- 13.7.4.3.4 Mode 1c: Normal operating mode without post-divider and with pre-divider
- 13.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider
- 13.7.4.3.6 Mode 3: Power down mode (pd)
- 13.7.4.4 Settings for USB0
- 13.7.4.5 Usage notes
- 13.7.5 Fractional divider for PLL0AUDIO
- 13.7.6 PLL1
- Pre-divider
- Post-divider
- Feedback divider
- Integer mode
- Non-integer mode
- Direct mode
- Power-down mode
- 13.8 Example CGU configurations
- Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)
- Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)
- Chapter 16: LPC43xx/LPC43Sxx Pin configuration
- Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO configuration
- 17.1 How to read this chapter
- 17.2 Basic configuration
- 17.3 General description
- 17.4 Register description
- 17.4.1 Pin configuration registers for normal-drive pins
- 17.4.2 Pin configuration registers for high-drive pins
- 17.4.3 Pin configuration registers for high-speed pins
- 17.4.4 Pin configuration register for USB1 pins USB1_DP/USB1_DM
- 17.4.5 Pin configuration register for open-drain I2C-bus pins
- 17.4.6 ADC0 function select register
- 17.4.7 ADC1 function select register
- 17.4.8 Analog function select register
- 17.4.9 EMC clock delay register
- 17.4.10 SD/MMC delay register
- 17.4.11 Pin interrupt select register 0
- 17.4.12 Pin interrupt select register 1
- Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)
- 18.1 How to read this chapter
- 18.2 Basic configuration
- 18.3 General description
- 18.4 Register description
- 18.4.1 Timer 0 CAP0_0 capture input multiplexer (CAP0_0_IN)
- 18.4.2 Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN)
- 18.4.3 Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN)
- 18.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN)
- 18.4.5 Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN)
- 18.4.6 Timer 1 CAP1_1 capture input multiplexer (CAP1_1_IN)
- 18.4.7 Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN)
- 18.4.8 Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN)
- 18.4.9 Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN)
- 18.4.10 Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN)
- 18.4.11 Timer 2 CAP2_2 capture input multiplexer (CAP2_2_IN)
- 18.4.12 Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN)
- 18.4.13 Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN)
- 18.4.14 Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN)
- 18.4.15 Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN)
- 18.4.16 Timer 3 CAP3_3 capture input multiplexer (CAP3_3_IN)
- 18.4.17 SCT CTIN_0 capture input multiplexer (CTIN_0_IN)
- 18.4.18 SCT CTIN_1 capture input multiplexer (CTIN_1_IN)
- 18.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN)
- 18.4.20 SCT CTIN_3 capture input multiplexer (CTIN_3_IN)
- 18.4.21 SCT CTIN_4 capture input multiplexer (CTIN_4_IN)
- 18.4.22 SCT CTIN_5 capture input multiplexer (CTIN_5_IN)
- 18.4.23 SCT CTIN_6 capture input multiplexer (CTIN_6_IN)
- 18.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN)
- 18.4.25 ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN)
- 18.4.26 Event router input 13 multiplexer (EVENTROUTER_13_IN)
- 18.4.27 Event router input 14 multiplexer (EVENTROUTER_14_IN)
- 18.4.28 Event router input 16 multiplexer (EVENTROUTER_16_IN)
- 18.4.29 ADC start0 input multiplexer (ADCSTART0_IN)
- 18.4.30 ADC start1 input multiplexer (ADCSTART1_IN)
- Chapter 19: LPC43xx/LPC43Sxx GPIO
- 19.1 How to read this chapter
- 19.2 Basic configuration
- 19.3 Features
- 19.4 General description
- 19.5 Register description
- 19.5.1 GPIO pin interrupts register description
- 19.5.1.1 Pin interrupt mode register
- 19.5.1.2 Pin interrupt level (rising edge) interrupt enable register
- 19.5.1.3 Pin interrupt level (rising edge) interrupt set register
- 19.5.1.4 Pin interrupt level (rising edge interrupt) clear register
- 19.5.1.5 Pin interrupt active level (falling edge) interrupt enable register
- 19.5.1.6 Pin interrupt active level (falling edge) interrupt set register
- 19.5.1.7 Pin interrupt active level (falling edge interrupt) clear register
- 19.5.1.8 Pin interrupt rising edge register
- 19.5.1.9 Pin interrupt falling edge register
- 19.5.1.10 Pin interrupt status register
- 19.5.2 GPIO GROUP0/GROUP1 interrupt register description
- 19.5.3 GPIO port register description
- 19.5.3.1 GPIO port byte pin registers
- 19.5.3.2 GPIO port word pin registers
- 19.5.3.3 GPIO port direction registers
- 19.5.3.4 GPIO port mask registers
- 19.5.3.5 GPIO port pin registers
- 19.5.3.6 GPIO masked port pin registers
- 19.5.3.7 GPIO port set registers
- 19.5.3.8 GPIO port clear registers
- 19.5.3.9 GPIO port toggle registers
- 19.5.1 GPIO pin interrupts register description
- 19.6 Functional description
- Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)
- 20.1 How to read this chapter
- 20.2 Basic configuration
- 20.3 Features
- 20.4 General description
- 20.5 Pin description
- 20.6 Register description
- 20.6.1 Pin multiplexer configuration registers
- 20.6.2 SGPIO multiplexer configuration registers
- 20.6.3 Slice multiplexer configuration registers
- 20.6.4 Slice data registers
- 20.6.5 Slice data shadow registers
- 20.6.6 Reload registers
- 20.6.7 Down counter registers
- 20.6.8 Position registers
- 20.6.9 Slice A mask register
- 20.6.10 Slice H mask register
- 20.6.11 Slice I mask register
- 20.6.12 Slice P mask register
- 20.6.13 GPIO input status register
- 20.6.14 GPIO output control register
- 20.6.15 GPIO output enable register
- 20.6.16 Slice count enable register
- 20.6.17 Slice count disable register
- 20.6.18 Shift clock interrupt clear mask register
- 20.6.19 Shift clock interrupt set mask register
- 20.6.20 Shift clock interrupt enable register
- 20.6.21 Shift clock interrupt status register
- 20.6.22 Shift clock interrupt clear status register
- 20.6.23 Shift clock interrupt set status register
- 20.6.24 Exchange clock interrupt clear mask register
- 20.6.25 Exchange clock interrupt set mask register
- 20.6.26 Exchange clock interrupt enable
- 20.6.27 Exchange clock interrupt status register
- 20.6.28 Exchange clock interrupt clear status register
- 20.6.29 Exchange clock interrupt set status register
- 20.6.30 Pattern match interrupt clear mask register
- 20.6.31 Pattern match interrupt set mask register
- 20.6.32 Pattern match interrupt enable
- 20.6.33 Pattern match interrupt status register
- 20.6.34 Pattern match interrupt clear status register
- 20.6.35 Pattern match interrupt set status register
- 20.6.36 Input interrupt clear mask register
- 20.6.37 Input bit match interrupt set mask register
- 20.6.38 Input bit match interrupt enable
- 20.6.39 Input bit match interrupt status register
- 20.6.40 Input bit match interrupt clear status register
- 20.6.41 Input bit match interrupt set status register
- 20.7 Functional description
- 20.8 Examples
- Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) controller
- 21.1 How to read this chapter
- 21.2 Basic configuration
- 21.3 Features
- 21.4 General description
- 21.5 DMA system connections
- 21.6 Register description
- 21.6.1 DMA Interrupt Status Register
- 21.6.2 DMA Interrupt Terminal Count Request Status Register
- 21.6.3 DMA Interrupt Terminal Count Request Clear Register
- 21.6.4 DMA Interrupt Error Status Register
- 21.6.5 DMA Interrupt Error Clear Register
- 21.6.6 DMA Raw Interrupt Terminal Count Status Register
- 21.6.7 DMA Raw Error Interrupt Status Register
- 21.6.8 DMA Enabled Channel Register
- 21.6.9 DMA Software Burst Request Register
- 21.6.10 DMA Software Single Request Register
- 21.6.11 DMA Software Last Burst Request Register
- 21.6.12 DMA Software Last Single Request Register
- 21.6.13 DMA Configuration Register
- 21.6.14 DMA Synchronization Register
- 21.6.15 DMA Channel registers
- 21.6.16 DMA Channel Source Address Registers
- 21.6.17 DMA Channel Destination Address registers
- 21.6.18 DMA Channel Linked List Item registers
- 21.6.19 DMA channel control registers
- 21.6.20 Channel Configuration registers
- 21.7 Functional description
- 21.8 Using the DMA controller
- Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
- 22.1 How to read this chapter
- 22.2 Basic configuration
- 22.3 Features
- 22.4 General description
- 22.5 Pin description
- 22.6 Register description
- 22.6.1 Control Register
- 22.6.2 Power Enable Register
- 22.6.3 Clock Divider Register
- 22.6.4 SD Clock Source Register
- 22.6.5 Clock Enable Register
- 22.6.6 Time-out Register
- 22.6.7 Card Type Register
- 22.6.8 Block Size Register
- 22.6.9 Byte Count Register
- 22.6.10 Interrupt Mask Register
- 22.6.11 Command Argument Register
- 22.6.12 Command Register
- 22.6.13 Response Register 0
- 22.6.14 Response Register 1
- 22.6.15 Response Register 2
- 22.6.16 Response Register 3
- 22.6.17 Masked Interrupt Status Register
- 22.6.18 Raw Interrupt Status Register
- 22.6.19 Status Register
- 22.6.20 FIFO Threshold Watermark Register
- 22.6.21 Card Detect Register
- 22.6.22 Write Protect Register
- 22.6.23 Transferred CIU Card Byte Count Register
- 22.6.24 Transferred Host to BIU-FIFO Byte Count Register
- 22.6.25 Debounce Count Register
- 22.6.26 Hardware Reset
- 22.6.27 Bus Mode Register
- 22.6.28 Poll Demand Register
- 22.6.29 Descriptor List Base Address Register
- 22.6.30 Internal DMAC Status Register
- 22.6.31 Internal DMAC Interrupt Enable Register
- 22.6.32 Current Host Descriptor Address Register
- 22.6.33 Current Buffer Descriptor Address Register
- 22.7 Functional description
- 22.7.1 Power/pull-up control and card detection unit
- 22.7.2 Auto-Stop
- 22.7.3 Software/hardware restrictions
- 22.7.4 Programming sequence
- 22.7.4.1 Initialization
- 22.7.4.2 Enumerated Card Stack
- 22.7.4.3 Clock Programming
- 22.7.4.4 No-Data Command With or Without Response Sequence
- 22.7.4.5 Data Transfer Commands
- 22.7.4.6 Single-Block or Multiple-Block Read
- 22.7.4.7 Single-Block or Multiple-Block Write
- 22.7.4.8 Stream Read
- 22.7.4.9 Stream Write
- 22.7.4.10 Sending Stop or Abort in Middle of Transfer
- 22.7.5 Suspend or Resume Sequence
- 22.7.6 DMA descriptors
- 22.7.6.1 SD/MMC DMA descriptors
- 22.7.6.2 Initialization
- 22.7.6.3 Host bus burst access
- 22.7.6.4 Host data buffer alignment
- 22.7.6.5 Buffer size calculations
- 22.7.6.6 Transmission
- 22.7.6.7 Reception
- 22.7.6.8 Interrupts
- 22.7.6.9 Abort
- 22.7.6.10 FBE scenarios
- 22.7.6.11 FIFO overflow and underflow
- 22.7.6.12 Programming of PBL and watermark levels
- Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)
- 23.1 How to read this chapter
- 23.2 Basic configuration
- 23.3 Features
- 23.4 General description
- 23.5 Memory bank select
- 23.6 Pin description
- 23.7 Register description
- 23.7.1 EMC Control register
- 23.7.2 EMC Status register
- 23.7.3 EMC Configuration register
- 23.7.4 Dynamic Memory Control register
- 23.7.5 Dynamic Memory Refresh Timer register
- 23.7.6 Dynamic Memory Read Configuration register
- 23.7.7 Dynamic Memory Precharge Command Period register
- 23.7.8 Dynamic Memory Active to Precharge Command Period register
- 23.7.9 Dynamic Memory Self Refresh Exit Time register
- 23.7.10 Dynamic Memory Last Data Out to Active Time register
- 23.7.11 Dynamic Memory Data In to Active Command Time register
- 23.7.12 Dynamic Memory Write Recovery Time register
- 23.7.13 Dynamic Memory Active to Active Command Period register
- 23.7.14 Dynamic Memory Auto-refresh Period register
- 23.7.15 Dynamic Memory Exit Self Refresh register
- 23.7.16 Dynamic Memory Active Bank A to Active Bank B Time register
- 23.7.17 Dynamic Memory Load Mode register to Active Command Time
- 23.7.18 Static Memory Extended Wait register
- 23.7.19 Dynamic Memory Configuration registers
- 23.7.20 Dynamic Memory RAS & CAS Delay registers
- 23.7.21 Static Memory Configuration registers
- 23.7.22 Static Memory Write Enable Delay registers
- 23.7.23 Static Memory Output Enable Delay registers
- 23.7.24 Static Memory Read Delay registers
- 23.7.25 Static Memory Page Mode Read Delay registers
- 23.7.26 Static Memory Write Delay registers
- 23.7.27 Static Memory Turn Round Delay registers
- 23.8 Functional description
- Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)
- Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller
- 25.1 How to read this chapter
- 25.2 Basic configuration
- 25.3 Features
- 25.4 Introduction
- 25.5 Pin description
- 25.6 Register description
- 25.6.1 Use of registers
- 25.6.2 Device/host capability registers
- 25.6.3 USB Command register (USBCMD)
- 25.6.4 USB Status register (USBSTS)
- 25.6.5 USB Interrupt register (USBINTR)
- 25.6.6 Frame index register (FRINDEX)
- 25.6.7 Device address (DEVICEADDR - device) and Periodic List Base (PERIODICLISTBASE- host) registers
- 25.6.8 Endpoint List Address register (ENDPOINTLISTADDR - device) and Asynchronous List Address (ASYNCLISTADDR - host) registers
- 25.6.9 TT Control register (TTCTRL)
- 25.6.10 Burst Size register (BURSTSIZE)
- 25.6.11 Transfer buffer Fill Tuning register (TXFILLTUNING)
- 25.6.12 BINTERVAL register
- 25.6.13 USB Endpoint NAK register (ENDPTNAK)
- 25.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN)
- 25.6.15 Port Status and Control register (PORTSC1)
- 25.6.16 OTG Status and Control register (OTGSC)
- 25.6.17 USB Mode register (USBMODE)
- 25.6.18 USB Endpoint Setup Status register (ENDPSETUPSTAT)
- 25.6.19 USB Endpoint Prime register (ENDPTPRIME)
- 25.6.20 USB Endpoint Flush register (ENDPTFLUSH)
- 25.6.21 USB Endpoint Status register (ENDPTSTAT)
- 25.6.22 USB Endpoint Complete register (ENDPTCOMPLETE)
- 25.6.23 USB Endpoint 0 Control register (ENDPTCTRL0)
- 25.6.24 Endpoint 1 to 5 control registers
- 25.7 Functional description
- 25.8 Deviations from EHCI standard
- 25.9 Device data structures
- 25.10 Device operational model
- 25.10.1 Device controller initialization
- 25.10.2 Port state and control
- 25.10.3 Bus reset
- 25.10.4 Suspend/resume
- 25.10.5 Managing endpoints
- 25.10.6 Operational model for packet transfers
- 25.10.7 Interrupt/bulk endpoint operational model
- 25.10.8 Control endpoint operational model
- 25.10.9 Isochronous endpoint operational model
- 25.10.10 Managing queue heads
- 25.10.11 Managing transfers with transfer descriptors
- 25.10.12 Servicing interrupts
- 25.11 System error
- 25.12 USB power optimization
- Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller
- 26.1 How to read this chapter
- 26.2 Basic configuration
- 26.3 Features
- 26.4 General description
- 26.5 Pin description
- 26.6 Register description
- 26.6.1 Device/host capability registers
- 26.6.2 USB Command register (USBCMD)
- 26.6.3 USB Status register (USBSTS)
- 26.6.4 USB Interrupt register (USBINTR)
- 26.6.5 Frame index register (FRINDEX)
- 26.6.6 Device address (DEVICEADDR) and Periodic List Base (PERIODICLISTBASE) registers
- 26.6.7 Endpoint List Address register (ENDPOINTLISTADDR) and Asynchronous List Address (ASYNCLISTADDR) registers
- 26.6.8 TT Control register (TTCTRL)
- 26.6.9 Burst Size register (BURSTSIZE)
- 26.6.10 Transfer buffer Fill Tuning register (TXFILLTUNING)
- 26.6.11 USB ULPI viewport register (ULPIVIEWPORT)
- 26.6.12 BINTERVAL register
- 26.6.13 USB Endpoint NAK register (ENDPTNAK)
- 26.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN)
- 26.6.15 Port Status and Control register (PORTSC1)
- 26.6.16 USB Mode register (USBMODE)
- 26.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT)
- 26.6.18 USB Endpoint Prime register (ENDPTPRIME)
- 26.6.19 USB Endpoint Flush register (ENDPTFLUSH)
- 26.6.20 USB Endpoint Status register (ENDPTSTAT)
- 26.6.21 USB Endpoint Complete register (ENDPTCOMPLETE)
- 26.6.22 USB Endpoint 0 Control register (ENDPTCTRL0)
- 26.6.23 Endpoint 1 to 3 control registers
- 26.7 Functional description
- Chapter 27: LPC43xx/LPC43Sxx USB API
- 27.1 How to read this chapter
- 27.2 Introduction
- 27.3 USB driver functions
- 27.4 Calling the USB device driver
- 27.5 USB API
- 27.5.1 __WORD_BYTE
- 27.5.2 _BM_T
- 27.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR
- 27.5.4 _CDC_CALL_MANAGEMENT_DESCRIPTOR
- 27.5.5 _CDC_HEADER_DESCRIPTOR
- 27.5.6 _CDC_LINE_CODING
- 27.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR
- 27.5.8 _CDC_UNION_DESCRIPTOR
- 27.5.9 _DFU_STATUS
- 27.5.10 _HID_DESCRIPTOR
- 27.5.11 _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST
- 27.5.12 _HID_REPORT_T
- 27.5.13 _MSC_CBW
- 27.5.14 _MSC_CSW
- 27.5.15 _REQUEST_TYPE
- 27.5.16 _USB_COMMON_DESCRIPTOR
- 27.5.17 _USB_CORE_DESCS_T
- 27.5.18 _USB_DEVICE_QUALIFIER_DESCRIPTOR
- 27.5.19 _USB_DFU_FUNC_DESCRIPTOR
- 27.5.20 _USB_INTERFACE_DESCRIPTOR
- 27.5.21 _USB_OTHER_SPEED_CONFIGURATION
- 27.5.22 _USB_SETUP_PACKET
- 27.5.23 _USB_STRING_DESCRIPTOR
- 27.5.24 _WB_T
- 27.5.25 USBD_API
- 27.5.26 USBD_API_INIT_PARAM
- 27.5.27 USBD_CDC_API
- 27.5.28 USBD_CDC_INIT_PARAM
- 27.5.29 USBD_CORE_API
- 27.5.30 USBD_DFU_API
- 27.5.31 USBD_DFU_INIT_PARAM
- 27.5.32 USBD_HID_API
- 27.5.33 USBD_HID_INIT_PARAM
- 27.5.34 USBD_HW_API
- 27.5.35 USBD_MSC_API
- 27.5.36 USBD_MSC_INIT_PARAM
- Chapter 28: LPC43xx/LPC43Sxx Ethernet
- 28.1 How to read this chapter
- 28.2 Basic configuration
- 28.3 Features
- 28.4 General description
- 28.5 Pin description
- 28.6 Register description
- 28.6.1 MAC Configuration register
- 28.6.2 MAC Frame filter register
- 28.6.3 MAC Hash table high register
- 28.6.4 MAC Hash table low register
- 28.6.5 MAC MII Address register
- 28.6.6 MAC MII Data register
- 28.6.7 MAC Flow control register
- 28.6.8 MAC VLAN tag register
- 28.6.9 MAC Debug register
- 28.6.10 MAC Remote wake-up frame filter register
- 28.6.11 MAC PMT control and status register
- 28.6.12 MAC Interrupt status register
- 28.6.13 MAC Interrupt mask register
- 28.6.14 MAC Address 0 high register
- 28.6.15 MAC Address 0 low register
- 28.6.16 MAC IEEE1588 time stamp control register
- 28.6.17 Sub-second increment register
- 28.6.18 System time seconds register
- 28.6.19 System time nanoseconds register
- 28.6.20 System time seconds update register
- 28.6.21 System time nanoseconds update register
- 28.6.22 Time stamp addend register
- 28.6.23 Target time seconds register
- 28.6.24 Target time nanoseconds register
- 28.6.25 System time higher words seconds register
- 28.6.26 Time stamp status register
- 28.6.27 DMA Bus mode register
- 28.6.28 DMA Transmit poll demand register
- 28.6.29 DMA Receive poll demand register
- 28.6.30 DMA Receive descriptor list address register
- 28.6.31 DMA Transmit descriptor list address register
- 28.6.32 DMA Status register
- 28.6.33 DMA Operation mode register
- 28.6.34 DMA Interrupt enable register
- 28.6.35 DMA Missed frame and buffer overflow counter register
- 28.6.36 DMA Receive interrupt watchdog timer register
- 28.6.37 DMA Current host transmit descriptor register
- 28.6.38 DMA Current host receive descriptor register
- 28.6.39 DMA Current host transmit buffer address register
- 28.6.40 DMA Current host receive buffer address register
- 28.7 Functional description
- Chapter 29: LPC43xx/LPC43Sxx LCD
- 29.1 How to read this chapter
- 29.2 Basic configuration
- 29.3 Features
- 29.4 General description
- 29.5 Pin description
- 29.6 Register description
- 29.6.1 Horizontal Timing register
- 29.6.2 Vertical Timing register
- 29.6.3 Clock and Signal Polarity register
- 29.6.4 Line End Control register
- 29.6.5 Upper Panel Frame Base Address register
- 29.6.6 Lower Panel Frame Base Address register
- 29.6.7 LCD Control register
- 29.6.8 Interrupt Mask register
- 29.6.9 Raw Interrupt Status register
- 29.6.10 Masked Interrupt Status register
- 29.6.11 Interrupt Clear register
- 29.6.12 Upper Panel Current Address register
- 29.6.13 Lower Panel Current Address register
- 29.6.14 Color Palette registers
- 29.6.15 Cursor Image registers
- 29.6.16 Cursor Control register
- 29.6.17 Cursor Configuration register
- 29.6.18 Cursor Palette register 0
- 29.6.19 Cursor Palette register 1
- 29.6.20 Cursor XY Position register
- 29.6.21 Cursor Clip Position register
- 29.6.22 Cursor Interrupt Mask register
- 29.6.23 Cursor Interrupt Clear register
- 29.6.24 Cursor Raw Interrupt Status register
- 29.6.25 Cursor Masked Interrupt Status register
- 29.7 Functional description
- 29.7.1 AHB interfaces
- 29.7.2 Dual DMA FIFOs and associated control logic
- 29.7.3 Pixel serializer
- 29.7.4 RAM palette
- 29.7.5 Hardware cursor
- 29.7.6 Gray scaler
- 29.7.7 Upper and lower panel formatters
- 29.7.8 Panel clock generator
- 29.7.9 Timing controller
- 29.7.10 STN and TFT data select
- 29.7.11 Interrupt generation
- 29.7.12 LCD power-up and power-down sequence
- 29.8 LCD timing diagrams
- 29.9 LCD panel signal usage
- Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)
- 30.1 How to read this chapter
- 30.2 Basic configuration
- 30.3 Features
- 30.4 General description
- 30.5 Pin description
- 30.6 Register description
- 30.6.1 SCT configuration register
- 30.6.2 SCT control register
- 30.6.3 SCT limit register
- 30.6.4 SCT halt condition register
- 30.6.5 SCT stop condition register
- 30.6.6 SCT start condition register
- 30.6.7 SCT counter register
- 30.6.8 SCT state register
- 30.6.9 SCT input register
- 30.6.10 SCT match/capture registers mode register
- 30.6.11 SCT output register
- 30.6.12 SCT bidirectional output control register
- 30.6.13 SCT conflict resolution register
- 30.6.14 SCT DMA request 0 and 1 registers
- 30.6.15 SCT flag enable register
- 30.6.16 SCT event flag register
- 30.6.17 SCT conflict enable register
- 30.6.18 SCT conflict flag register
- 30.6.19 SCT match registers 0 to 15 (REGMODEn bit = 0)
- 30.6.20 SCT capture registers 0 to 15 (REGMODEn bit = 1)
- 30.6.21 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
- 30.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
- 30.6.23 SCT event state mask registers 0 to 15
- 30.6.24 SCT event control registers 0 to 15
- 30.6.25 SCT output set registers 0 to 15
- 30.6.26 SCT output clear registers 0 to 15
- 30.7 Functional description
- Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with dither engine
- 31.1 How to read this chapter
- 31.2 Features
- 31.3 Register description
- 31.3.1 SCT configuration register
- 31.3.2 SCT control register
- 31.3.3 SCT limit register
- 31.3.4 SCT halt condition register
- 31.3.5 SCT stop condition register
- 31.3.6 SCT start condition register
- 31.3.7 SCT dither condition register
- 31.3.8 SCT counter register
- 31.3.9 SCT state register
- 31.3.10 SCT input register
- 31.3.11 SCT match/capture registers mode register
- 31.3.12 SCT output register
- 31.3.13 SCT bidirectional output control register
- 31.3.14 SCT conflict resolution register
- 31.3.15 SCT DMA request 0 and 1 registers
- 31.3.16 SCT flag enable register
- 31.3.17 SCT event flag register
- 31.3.18 SCT conflict enable register
- 31.3.19 SCT conflict flag register
- 31.3.20 SCT match registers 0 to 15 (REGMODEn bit = 0)
- 31.3.21 SCT fractional match registers 0 to 5
- 31.3.22 SCT capture registers 0 to 15 (REGMODEn bit = 1)
- 31.3.23 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
- 31.3.24 SCT fractional match reload registers 0 to 5
- 31.3.25 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
- 31.3.26 SCT event state mask registers 0 to 15
- 31.3.27 SCT event control registers 0 to 15
- 31.3.28 SCT output set registers 0 to 15
- 31.3.29 SCT output clear registers 0 to 15
- 31.4 Functional description
- 31.5 SCT Example
- Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3
- 32.1 How to read this chapter
- 32.2 Basic configuration
- 32.3 Features
- 32.4 General description
- 32.5 Pin description
- 32.6 Register description
- 32.6.1 Timer interrupt registers
- 32.6.2 Timer control registers
- 32.6.3 Timer counter registers
- 32.6.4 Timer prescale registers
- 32.6.5 Timer prescale counter registers
- 32.6.6 Timer match control registers
- 32.6.7 Timer match registers (MR0 - MR3)
- 32.6.8 Timer capture control registers
- 32.6.9 Timer capture registers
- 32.6.10 Timer external match registers
- 32.6.11 Timer count control registers
- 32.7 Functional description
- Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)
- 33.1 How to read this chapter
- 33.2 Basic configuration
- 33.3 Introduction
- 33.4 Features
- 33.5 General description
- 33.6 Pin description
- 33.7 Register description
- 33.7.1 MCPWM Control register
- 33.7.2 PWM Capture Control register
- 33.7.3 MCPWM Timer/Counter 0-2 registers
- 33.7.4 MCPWM Limit 0-2 registers
- 33.7.5 MCPWM Match 0-2 registers
- 33.7.6 MCPWM Dead-time register
- 33.7.7 MCPWM Communication Pattern register
- 33.7.8 MCPWM Capture read addresses
- 33.7.9 MCPWM Interrupt registers
- 33.7.10 MCPWM Count Control register
- 33.7.11 MCPWM Interrupt flag registers
- 33.7.12 MCPWM Capture clear address
- 33.8 Functional description
- Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)
- Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer (RIT)
- Chapter 36: LPC43xx/LPC43Sxx Alarm timer
- Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)
- Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)
- Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder
- Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
- 40.1 How to read this chapter
- 40.2 Basic configuration
- 40.3 Features
- 40.4 General description
- 40.5 Pin description
- 40.6 Register description
- 40.6.1 USART Receiver Buffer Register
- 40.6.2 USART Transmitter Holding Register
- 40.6.3 USART Divisor Latch LSB and MSB Registers
- 40.6.4 USART Interrupt Enable Register
- 40.6.5 USART Interrupt Identification Register
- 40.6.6 USART FIFO Control Register
- 40.6.7 USART Line Control Register
- 40.6.8 USART Line Status Register
- 40.6.9 USART Scratch Pad Register
- 40.6.10 USART Auto-baud Control Register
- 40.6.11 IrDA Control Register (USART3)
- 40.6.12 USART Fractional Divider Register
- 40.6.13 USART Oversampling Register
- 40.6.14 USART Half-duplex enable register
- 40.6.15 USART Smart card interface control register
- 40.6.16 USART RS485 Control register
- 40.6.17 USART RS485 Address Match register
- 40.6.18 USART RS485 Delay value register
- 40.6.19 USART Synchronous mode control register
- 40.6.20 USART Transmit Enable Register
- 40.7 Functional description
- Chapter 41: LPC43xx/LPC43Sxx UART1
- 41.1 How to read this chapter
- 41.2 Basic configuration
- 41.3 Features
- 41.4 General description
- 41.5 Pin description
- 41.6 Register description
- 41.6.1 UART1 Receiver Buffer Register (when DLAB = 0)
- 41.6.2 UART1 Transmitter Holding Register (when DLAB = 0)
- 41.6.3 UART1 Divisor Latch LSB and MSB Registers (when DLAB = 1)
- 41.6.4 UART1 Interrupt Enable Register (when DLAB = 0)
- 41.6.5 UART1 Interrupt Identification Register
- 41.6.6 UART1 FIFO Control Register
- 41.6.7 UART1 Line Control Register
- 41.6.8 UART1 Modem Control Register
- 41.6.9 UART1 Line Status Register
- 41.6.10 UART1 Modem Status Register
- 41.6.11 UART1 Scratch Pad Register
- 41.6.12 UART1 Auto-baud Control Register
- 41.6.13 UART1 Fractional Divider Register
- 41.6.14 UART1 RS485 Control register
- 41.6.15 UART1 RS-485 Address Match register
- 41.6.16 UART1 RS-485 Delay value register
- 41.6.17 UART1 Transmit Enable Register
- 41.7 Functional description
- Chapter 42: LPC43xx/LPC43Sxx SSP0/1
- 42.1 How to read this chapter
- 42.2 Basic configuration
- 42.3 Features
- 42.4 General description
- 42.5 Pin description
- 42.6 Register description
- 42.6.1 SSP Control Register 0
- 42.6.2 SSP Control Register 1
- 42.6.3 SSP Data Register
- 42.6.4 SSP Status Register
- 42.6.5 SSP Clock Prescale Register
- 42.6.6 SSP Interrupt Mask Set/Clear Register
- 42.6.7 SSP Raw Interrupt Status Register
- 42.6.8 SSP Masked Interrupt Status Register
- 42.6.9 SSP Interrupt Clear Register
- 42.6.10 SSP DMA Control Register
- 42.7 Functional description
- Chapter 43: LPC43xx/LPC43Sxx SPI
- Chapter 44: LPC43xx/LPC43Sxx I2S interface
- 44.1 How to read this chapter
- 44.2 Basic configuration
- 44.3 Features
- 44.4 General description
- 44.5 Pin description
- 44.6 Register description
- 44.6.1 I2S Digital Audio Output register
- 44.6.2 I2S Digital Audio Input register
- 44.6.3 I2S Transmit FIFO register
- 44.6.4 Receive FIFO register
- 44.6.5 I2S Status Feedback register
- 44.6.6 I2S DMA Configuration Register 1
- 44.6.7 I2S DMA Configuration Register 2
- 44.6.8 I2S Interrupt Request Control register
- 44.6.9 I2S Transmit Clock Rate register
- 44.6.10 I2S Receive Clock Rate register
- 44.6.11 I2S Transmit Clock Bit Rate register
- 44.6.12 I2S Receive Clock Bit Rate register
- 44.6.13 I2S Transmit Mode Control register
- 44.6.14 I2S Receive Mode Control register
- 44.7 Functional description
- Chapter 45: LPC43xx/LPC43Sxx C_CAN
- Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface
- 46.1 How to read this chapter
- 46.2 Basic configuration
- 46.3 Features
- 46.4 Applications
- 46.5 General description
- 46.6 Pin description
- 46.7 Register description
- 46.7.1 I2C Control Set register
- 46.7.2 I2C Status register
- 46.7.3 I2C Data register
- 46.7.4 I2C Slave Address register 0
- 46.7.5 I2C SCL HIGH and LOW duty cycle registers
- 46.7.6 I2C Control Clear register
- 46.7.7 I2C Monitor mode control register
- 46.7.8 I2C Slave Address registers 1 to 3
- 46.7.9 I2C Data buffer register
- 46.7.10 I2C Mask registers
- 46.8 I2C operating modes
- 46.9 I2C implementation and operation
- 46.9.1 Input filters and output stages
- 46.9.2 Address Registers, ADR0 to ADR3
- 46.9.3 Address mask registers, MASK0 to MASK3
- 46.9.4 Comparator
- 46.9.5 Shift register, DAT
- 46.9.6 Arbitration and synchronization logic
- 46.9.7 Serial clock generator
- 46.9.8 Timing and control
- 46.9.9 Control register, CONSET and CONCLR
- 46.9.10 Status decoder and status register
- 46.10 Details of I2C operating modes
- 46.10.1 Master Transmitter mode
- 46.10.2 Master Receiver mode
- 46.10.3 Slave Receiver mode
- 46.10.4 Slave Transmitter mode
- 46.10.5 Miscellaneous states
- 46.10.6 Some special cases
- 46.10.7 I2C state service routines
- 46.10.8 Initialization
- 46.10.9 I2C interrupt service
- 46.10.10 The state service routines
- 46.10.11 Adapting state services to an application
- 46.11 Software example
- Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1
- Chapter 48: 12-bit ADC (ADCHS)
- 48.1 How to read this chapter
- 48.2 Features
- 48.3 Basic configuration
- 48.4 Pin description
- 48.5 General description
- 48.6 Register description
- 48.6.1 FIFO flush register
- 48.6.2 DMA request register
- 48.6.3 FIFO fill level register
- 48.6.4 FIFO configuration register
- 48.6.5 Trigger register
- 48.6.6 Descriptor status register
- 48.6.7 Power-down register
- 48.6.8 Configuration register
- 48.6.9 Threshold A/B register
- 48.6.10 Last sample registers
- 48.6.11 Speed register
- 48.6.12 Power control register
- 48.6.13 FIFO output register
- 48.6.14 Descriptor table 0 register
- 48.6.15 Descriptor table 1 register
- 48.6.16 Interrupt 0 clear mask register
- 48.6.17 Interrupt 0 set mask register
- 48.6.18 Interrupt 0 enable register
- 48.6.19 Interrupt 0 status register
- 48.6.20 Interrupt 0 clear status register
- 48.6.21 Interrupt 0 set status register
- 48.6.22 Interrupt 1 clear mask register
- 48.6.23 Interrupt 1 set mask register
- 48.6.24 Interrupt 1 mask register
- 48.6.25 Interrupt 1 status register
- 48.6.26 Interrupt 1 clear status register
- 48.6.27 Interrupt 1 set status register
- 48.7 Functional description
- Chapter 49: LPC43xx/LPC13Sxx DAC
- Chapter 50: LPC43xx/LPC43Sxx EEPROM memory
- Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and trace functions
- Chapter 52: LPC43xx/LPC43Sxx ARM Cortex M0/M4 reference
- Chapter 53: LPC43xx/LPC43Sxx API General error codes
- Chapter 54: Supplementary information